commit b98751015677310ccddb93b8fe88538df38cea67
parent 77fc09a43669a3fb4e988495a1630730200b6a09
Author: Broadcom SDK Release <sdk.releases@broadcom.com>
Date: Mon, 4 Jan 2021 10:34:35 -0800
DNX PCIe gen3 Firmware v2.5.3.0
Diffstat:
9 files changed, 671 insertions(+), 0 deletions(-)
diff --git a/Firmware/pcie/dnx/v2.5.3/PCIe_Gen3_Firmware-RELNOTES b/Firmware/pcie/dnx/v2.5.3/PCIe_Gen3_Firmware-RELNOTES
@@ -0,0 +1,96 @@
+Release Notes for PCIe Gen3 Firmware for Broadcom Network Switch devices
+
+=====================================
+Release 2.5.3.0-DNX - for DNX devices
+=====================================
+
+Release Date: Dec, 2020
+
+For J2CP:
+PCIe FW loader version: 2.50030
+PCIe controller FW version: D000_05
+
+For other device:
+PCIe FW loader version: 2.50030
+PCIe controller FW version: D102_0B
+
+
+Devices supported in this release:
+BCM8879x (Ramon)
+BCM8869x (Jericho2)
+BCM8880x (J2C)
+BCM8882x (J2C/Q2C)
+BCM8848x (Q2A)
+BCM8828x (Q2U)
+BCM8885x (J2CP)
+
+
+Major release notes for the release
+===================================
+
+1. This is a PRE quality release.
+
+2. This PCIe firmware release requires SDK release 6.5.20 or later.
+
+
+Known Issues:
+============
+
+1. Does not support hot swapping of the PCIe Root Complex
+2. For some types of used QSPI flash memory chips, SDK releases before
+ 6.5.21 may need a patch to access the flash memory.
+
+
+Release contents:
+================
+
+PCIe_Gen3_Firmware-RELNOTES These release notes
+pcie_gen3_fw_install.txt Installation instructions
+bins/pciefw-r5-m7.bin PCIe Fimware binary for J2CP
+bins/pciefw-r5.bin PCIe Fimware binary for other devices
+tools/custom/custom.txt Sample custom settings text file
+tools/custom/custom_ascii2bin.pl Script converting custom settings from text to binary
+tools/flashwrite/ARM_DS-5 Directory with Arm R5 flash writing tool
+
+
+Enhancements and fixes per release:
+==================================
+
+Bug Fix in 2.5.3.0-DNX compared to 2.5.2.0-DNX:
+ Prevented failures to run e-apps in some scenarios.
+
+Enhancement in 2.5.2.0-DNX compared to 2.5.1-DNX:
+ Added initial support for BCM8885x (Jericho2C Plus), uses a separate binary.
+ Moved to the latest PCIe controller firmware for other devices
+
+Enhancement in 2.5.1-DNX compared to 2.5-DNX:
+ Added support for BCM8848X (Qumran 2A).
+ Added support for BCM8828X (Qumran 2U).
+
+Bug Fixes in 2.5-DNX compared to 2.5:
+ Make the DNX devices supported in this release, able to check the firmware
+ version and load a different firmware version to QSPI flash memory from the
+ SDK.
+ Fix custom settings handling (if provided by the customer) to not report
+ incorrect failures of their application.
+
+Bug Fixes in 2.5:
+ Fix for device enumeration fail sporadically when set to Gen3 mode.
+ Fix for Gen3 linkup failure upon sys_rst_l and/or PERST.
+
+
+Output to provide when requesting support for this PCIe firmware release:
+========================================================================
+ From the linux shell, the output of these commands:
+ lspci -n
+ lspci -vt
+ lspci -vvd 14e4:
+ From the BCM shell of the SDK, the output of these commands:
+ g QSPI_BSPI_REGISTERS_SCRATCH
+ g PAXB_0_GEN3_UC_LOADER_STATUS
+ g MHOST_0_MHOST_STRAP_STATUS
+ g RTS0_MHOST_0_MHOST_STRAP_STATUS
+ pciephy fw version
+ pciephy getreg 0xd230
+ mcsstat
+ iprocread 0x1327e00 64
diff --git a/Firmware/pcie/dnx/v2.5.3/bins/pciefw-r5-m7.bin b/Firmware/pcie/dnx/v2.5.3/bins/pciefw-r5-m7.bin
Binary files differ.
diff --git a/Firmware/pcie/dnx/v2.5.3/bins/pciefw-r5.bin b/Firmware/pcie/dnx/v2.5.3/bins/pciefw-r5.bin
Binary files differ.
diff --git a/Firmware/pcie/dnx/v2.5.3/pcie_gen3_fw_install.txt b/Firmware/pcie/dnx/v2.5.3/pcie_gen3_fw_install.txt
@@ -0,0 +1,208 @@
+
+NOTE: For DNX devices (BCM88xxx devices), please refer to the "DNX16 Hardware
+Design Guidelines for StrataDNX 16-nm Devices", DNX16-AN1xx.pdf, "DNX16
+(BCM88790, BCM88690) QSPI Flash Programming" section.
+
+How to install PCIe FW Loader
+=============================
+PCIe Gen3 FW can be programmed into serial flash using various methods. The
+customer can use whatever method suits their manufacturing flow best.
+
+Method 1: Using external flash programmer or gang programmer
+ This method requires all of the flash memory devices to be pre-programmed
+ with the provided firmware using an external programming device prior to
+ being mounted on the board. See programmers manual of external programmer for
+ instructions on how to erase and program serial flash device.
+
+Method 2: Using ARM DS-5 and ARM DSTREAM
+ This method allows a blank flash device to be populated on the board at the
+ time of manufacturing. A small programming utility as well as the PCIe
+ firmware are loaded into the ARM R5 inside of the Broadcom switch device via
+ its JTAG interface. Once the load is complete, the programming utility will
+ be run by the ARM R5 and will program the firmware to the flash device. This
+ package includes further instructions on this flow in
+ tools/flashwrite/ARM_DS-5
+
+Method 3: Initially advertise Gen1-only support from PCIe link partner
+ This method allows a blank flash device to be populated on the board at the
+ time of manufacturing. The Broadcom switch device is strapped to support PCIe
+ Gen3 and boot using the firmware (BOOT_DEV[2:0]=3'b000, MHOST0_BOOT_DEV=1'b1,
+ and PCIE_FORCE_GENTYPE[1:0]=2'b00). Since the PCIe link partner is
+ advertising Gen1 only support, the PCIe link will be able to come up and the
+ device will enumerate and function. The Broadcom SDK can then be loaded and
+ the SDK's PCIe Gen3 firmware in-field upgrade utility (SDK diag command
+ "pciephy fw load") can be used to program the firmware to the blank flash
+ device. Following that, the system can be reset and the PCIe link partner
+ can be reconfigured to advertise all supported PCIe speeds.
+
+ Syntax of in-field upgrade command:
+ BCM.0> pciephy fw load <Firmware file>
+ e.g.,
+ BCM.0> pciephy fw load pcieg3fw.bin
+
+ The flash driver in SDK is based on MT25QL256. If the mounted flash part is
+ compatible with MT25QL256's instruction set but unrecognized by the driver,
+ please use SoC property "pcie_flash_mem_params" to specify the parameters of
+ the flash device.
+
+ pcie_flash_mem_params=<id>,<sector_size>,<page_size>
+ <id>: Manufacturer ID.
+ <sector_size>: The samllest erase unit in bytes.
+ <page_size>: The smallest access unit in bytes.
+
+Method 4: Initially advertise Gen1-only support from Broadcom switch device
+ This method allows a blank flash device to be populated on the board at the
+ time of manufacturing. The Broadcom switch device is initially strapped to
+ support PCIe Gen1 and boot using the firmware (BOOT_DEV[2:0]=3'b000,
+ MHOST0_BOOT_DEV=1'b1, and PCIE_FORCE_GENTYPE[1:0]=2'b01). The PCIe link
+ will be able to come up and the device will enumerate and function. The
+ Broadcom SDK can then be loaded and the SDK's PCIe Gen3 firmware in-field
+ upgrade utility (SDK diag command "pciephy fw load") can be used to program
+ the firmware to the blank flash device. Following that, the
+ PCIE_FORCE_GENTYPE0 strap signal should be changed to 1'b0 and system should
+ be reset to advertise all supported PCIe speeds.
+
+ Syntax of in-field upgrade command:
+ BCM.0> pciephy fw load <Firmware file>
+ e.g.,
+ BCM.0> pciephy fw load pcieg3fw.bin
+
+Method 5: Use I2C to write the firmware.
+ This requires the CPU that the SDK is running on to be an I2C master of an
+ I2C bus to which the Broadcom switch device is connected.
+ In such a case you need to know the I2C bus number (as Linux enumerates I2C
+ buses). And also know the I2C device number of the Broadcom switch device in
+ the bus which is by default 0x44.
+ This method also requires the SDK to be built with CPU I2C support.
+ This means that FEATURE_LIST in the make.local file should contain CPU_I2C .
+
+ Here is an example command making pciephy firmware handling use I2c with a
+ specific bus number and device number:
+ BCM.0> pciephy fw access i2c 0 0x44
+
+ After this command you can either test that I2C device access work using:
+ "pciephy fw version" or directly attempt to write the firmware to the flash
+ memory: "pciephy fw load <firmware file>"
+
+ If the BDE you are using with the SDK supports I2C access to the device
+ internally, removing the need to specify the I2C bus and device numbers,
+ instead of "pciephy fw access i2c <bus id> <device id>" you may use
+ "pciephy fw i2c_bde".
+
+ If the SDK does not recognize any switch device using PCIe, the pciephy
+ command will not work. In this case a dummy device needs to be added using
+ the following soc properties, where the PCIe device and revision IDs may be
+ replaced with the IDs of the relevant device.
+ extra_unit_min=0
+ extra_unit_max=0
+ extra_unit.0=1
+ pci_override_dev.0=0x8690
+ pci_override_rev.0=1
+
+
+How to boot and verify PCIe FW
+===================================
+1. Ensure that strap signals are set to load the firmware:
+ BOOT_DEV[2:0] = 3'b000
+ MHOST0_BOOT_DEV = 1'b1
+ PCIE_FORCE_GENTYPE[1:0] = 2'b00
+
+2. Power On the system
+
+3. Load and run linux
+ a) At a linux prompt run
+ lspci -d 0x14e4: -vvv
+
+ b) The Broadcom switch device should have enumerated and should show
+ something similar to the following:
+ "05:00.0 Ethernet controller: Broadcom Limited Device b870 (rev 01)"
+
+ c) In the lspci output, check that the link status register field shows
+ speed set to 8GT/s
+ 8GT/s - PCIe Gen3
+ 5GT/s - PCIe Gen2
+ 2.5GT/s - PCIe Gen1
+
+ d) check that link capability register shows "ASPM not supported" and
+ link control register shows "ASPM disabled"
+
+ e) Run SDK and verify that "tr 502" completes successfully
+
+How to apply custom/user settings in MAC/PHY registers
+======================================================
+It is anticipated that some of MAC/PHY settings, like TX FIR etc, may be tuned
+by customer based on customer system requirements. PCIe Gen3 FW offers
+provision for such cases. This provision offers optional custom settings
+programming prior to and after SerDes FW loading. This provision requires
+custom or system specific PCIe MAC/PHY register settings to be programmed at
+30K offset of QSPI flash in the format described below i.e
+{type, address, value} triplets.
+
+ ----------------------- __
+ | 0x50434945 | |
+ | 0x41524753 | |__ Header, fixed, 4x32-bit words
+ | 0x00000000 | |
+ | 0x00000000 | __|
+ ----------------------- __
+ | 0x5052454c | |
+ | {type, addr, val} | |
+ | {type, addr, val} | | Optional pre FW load settings
+ | : | | Must have 0x5052454c as first word
+ | : | |__ followed by {type, addr, val}
+ | : | | triplets (triplet - 3x32bit words)
+ | : | | type: 0 - MAC address, 1 - PHY addr
+ | : | | addr: MAC/PHY register address
+ | {type, addr, val} | __| Val: Value to be programmed
+ ----------------------- __
+ | 0x504f5354 | |
+ | {type, addr, val} | | Optional post FW load settings
+ | : | | Must have 0x504f5354 as first word
+ | : | |__ followed by {type, addr, val}
+ | : | | triplets (triplet - 3x32bit words).
+ | : | | type: 0 - MAC address, 1 - PHY addr
+ | : | | addr: MAC/PHY register address
+ | {type, addr, val} | __| Val: Value to be programmed
+ ----------------------- __
+ | 0x00454E44 | |__Footer, fixed, 2x32-bit words
+ | 0x41524753 | __|
+ -----------------------
+
+User can program up to maximum 168 triplets (i.e 504x32-bit words).
+There is no restriction on number of triplets for pre FW load settings or post
+FW load settings, provided total number of triplets do not exceed max limit
+of 168.
+
+Customer settings are optional, may include either of or both pre and post FW
+load settings.
+
+A sample format file in text format (custom.txt) and perl based text to binary
+conversion utility provided under tools/custom/ directory of this
+release package to help customer to generate customer settings in binary format.
+
+Customer settings in text format may have comments with '#' at the begining of
+the line and also blank lines which will be ignored by text to binary conversion
+tool.
+
+Syntax of text to binary conversion tool:
+perl custom_ascii2bin.pl <input text file> <output file>
+
+Example: Conversion of sample custom.txt file
+
+linux#: perl custom_ascii2bin.pl custom.txt custom.bin
+454943505347524100000000000000004c45525000000000381800000040088254534f5001000000b0d000008024000001000000b1d0000007000000444E450053475241
+
+Hexdump of generated file should look like the following:
+linux#: hexdump -c custom.bin
+0000000 E I C P S G R A \0 \0 \0 \0 \0 \0 \0 \0
+0000010 L E R P \0 \0 \0 \0 8 030 \0 \0 \0 @ \b 202
+0000020 T S O P 001 \0 \0 \0 � � \0 \0 200 $ \0 \0
+0000030 001 \0 \0 \0 � � \0 \0 \a \0 \0 \0 D N E \0
+0000040 S G R A
+0000044
+
+Installing custom settings binary file:
+1) Append the custom settings binary file to the PCIe FW binary file (bins/pciefw-r5.bin or bins/pciefw-r5-m7.bin)
+ e.g.,
+ cat pciefw-r5.bin custom.bin >custom_pciefw-r5.bin
+2) Install the appended binary into QSPI flash at offset 0x0 using one of the
+ FW installation methods mentioned above.
diff --git a/Firmware/pcie/dnx/v2.5.3/tools/custom/custom.txt b/Firmware/pcie/dnx/v2.5.3/tools/custom/custom.txt
@@ -0,0 +1,40 @@
+# Custom settings Header, DO NOT alter
+0x50434945
+0x41524753
+0x00000000
+0x00000000
+# End of Custom settings Header
+
+# User Settings
+# Optional Pre FW load settings, to be loaded before SerDes FW loadin
+# Preload ID 0x5052454c, followed by {register type: 0 - MAC, 1 - PHY, 32bit register address and 32bit data in hexadecimal format} sets
+0x5052454c
+# Disable parity matching for Gen3 TS1s, symbols 6 through 9, required for systems with PLX switches.
+# Type
+0x00000000
+# Address
+0x00001838
+# Data
+0x82084000
+
+# Optional Post FW load settings, to be loaded after SerDes FW loading
+# Post load ID 0x504f5354, followed by {register type: 0 - MAC, 1 - PHY, 32bit register address and 32bit data in hexadecimal format} sets
+0x504f5354
+# Type
+0x00000001
+# Address
+0x0000d0b0
+# Data
+0x00002480
+# Type
+0x00000001
+#Address
+0x0000d0b1
+# Data
+0x00000007
+#End of User Settings
+
+# Custom settings footer, DO NOT alter
+0x00454E44
+0x41524753
+# End of Custom settings footer
diff --git a/Firmware/pcie/dnx/v2.5.3/tools/custom/custom_ascii2bin.pl b/Firmware/pcie/dnx/v2.5.3/tools/custom/custom_ascii2bin.pl
@@ -0,0 +1,21 @@
+my $in = $ARGV[0];
+my $out = $ARGV[1];
+
+my $str_hex;
+my $str_ascii;
+my $num;
+my $num2;
+ open(my $F, "<", "$in") or die "can't open in file";
+ open(my $FF, ">:raw", "$out") or die "can't open out file";
+LOOP: while($str_ascii = <$F>) {
+ next LOOP if(($str_ascii =~ m/^#/) || ($str_ascii =~ m/^\s*$/)); # Discard comments or white lines
+ $str_ascii =~ m/0x(.*)/;
+ $num = $1;
+ $num2=join("",(split(//,$num))[6,7,4,5,2,3,0,1]);
+ print $num2;
+ print $FF pack('H8',$num2);
+ }
+ print "\n";
+close($F);
+
+close($FF);
diff --git a/Firmware/pcie/dnx/v2.5.3/tools/flashwrite/ARM_DS-5/TD3_sflash_program_for_PCIe_Gen3_FW.docx b/Firmware/pcie/dnx/v2.5.3/tools/flashwrite/ARM_DS-5/TD3_sflash_program_for_PCIe_Gen3_FW.docx
Binary files differ.
diff --git a/Firmware/pcie/dnx/v2.5.3/tools/flashwrite/ARM_DS-5/program_sflash_td3.py b/Firmware/pcie/dnx/v2.5.3/tools/flashwrite/ARM_DS-5/program_sflash_td3.py
@@ -0,0 +1,306 @@
+import sys
+import os
+from os.path import getsize
+from arm_ds.debugger_v1 import Debugger
+#from arm_ds.debugger_v1 import DebugException
+
+print "--Start of script--"
+MAX_U_BOOT_SIZE = 0xA0000
+
+FLASH_PROGRAM_OFFSET = 0
+FLASH_PAGE_SIZE = 256
+FLASH_PAGES_PER_SECTOR = 256
+FLASH_SECTOR_SIZE = FLASH_PAGE_SIZE*FLASH_PAGES_PER_SECTOR
+FLASH_SECTOR_NUM = 512
+
+#Flash command definition
+MAX_CMD_NUM = 16
+CMD_M25PXX_PP = 0x02
+CMD_M25PXX_WREN = 0x06
+CMD_M25PXX_WRDI = 0x04
+CMD_M25PXX_EN4B = 0xb7 #/* Enter 4-byte address mode */
+CMD_M25PXX_EX4B = 0xe9 #/* Exit 4-byte address mode */
+CMD_M25PXX_SE = 0xd8
+CMD_M25PXX_RDSR = 0x05
+CMD_M25PXX_RDFSR = 0x70
+
+#We used internal RAM to store tiny program and its parameter
+BREAK_POINT_OFFSET = 0x13C
+TMP_FILE_PATH = sys.currentWorkingDir+"\\__TEMP.bin"
+
+TX_RAM = [0]*16
+CMD_BUF = [0]*MAX_CMD_NUM
+
+if len(sys.argv) == 1:
+ print " !!ErrorPlease provide the path of u-boot.bin"
+ sys.exit(0)
+
+image_path = sys.argv[1] #Get u-boot image path
+img_len = getsize(image_path) #Get size of u-boot.bin
+if img_len > MAX_U_BOOT_SIZE: #Image size can't exceed the maximum size of u-boot partition
+ print " !!Error: Wrong image size(%d), the maximum size should be less than %d" %(img_len, MAX_U_BOOT_SIZE)
+ sys.exit(0)
+
+print "Size of %s is %d bytes." %(image_path, img_len)
+
+IMAGE = [0]*img_len
+uboot_image = open(image_path, "rb")
+
+debugger = Debugger()
+cur_ec = debugger.getCurrentExecutionContext()
+memory = cur_ec.getMemoryService()
+register = cur_ec.getRegisterService()
+
+def REG_AND(addr, value):
+ v = memory.readMemory32(addr)
+ v &= value
+ memory.writeMemory32(addr, v)
+ return v
+
+def REG_OR(addr, value):
+ v = memory.readMemory32(addr)
+ v |= value
+ memory.writeMemory32(addr, v)
+ return v
+
+def num2hexstr(num):
+ hexstr = "0x%X" %num
+ return hexstr
+
+def py_bspi_enable():
+ memory.writeMemory32(QSPI_mspi_WRITE_LOCK, 0)
+
+ memory.writeMemory32(QSPI_bspi_registers_B0_CTRL, 0)
+ memory.writeMemory32(QSPI_bspi_registers_B1_CTRL, 0)
+ memory.writeMemory32(QSPI_bspi_registers_B0_CTRL, 1)
+ memory.writeMemory32(QSPI_bspi_registers_B1_CTRL, 1)
+
+ memory.writeMemory32(QSPI_bspi_registers_MAST_N_BOOT_CTRL, 0)
+
+#################################################################
+# Function:
+# py_spi_init
+# Desc:
+# Init spi controller
+#################################################################
+def py_spi_init():
+ print "Initialize spi controller..."
+ memory.writeMemory32(QSPI_mspi_SPCR1_LSB, 0)
+ memory.writeMemory32(QSPI_mspi_SPCR1_MSB, 0)
+ memory.writeMemory32(QSPI_mspi_NEWQP, 0)
+ memory.writeMemory32(QSPI_mspi_ENDQP, 0)
+ memory.writeMemory32(QSPI_mspi_SPCR2, 0)
+ #MSPI: SCK configuration
+ memory.writeMemory32(QSPI_mspi_SPCR0_LSB, 0x0000008)
+ #Master | 8 bits per word | mode: CPOL=1 / CPHA=1
+ memory.writeMemory32(QSPI_mspi_SPCR0_MSB, 0x000000A3)
+
+ memory.writeMemory32(QSPI_bspi_registers_MAST_N_BOOT_CTRL, 1) #Enable MSPI
+ #py_bspi_enable(0) #Disable BSPI
+ print "Initialize spi controller done!"
+
+
+def wait_for_complete(reg_addr, mask, value):
+ print "wait_for_complete reg_addr = 0x%X, mask=0x%X, value=0x%X" %(reg_addr, mask, value)
+ while 1:
+ reg = memory.readMemory32(reg_addr)
+ if reg&mask == value:
+ break;
+
+#################################################################
+# Function:
+# py_spi_cmd_transmit
+# Desc:
+# Fill txram buffer, and trigger spi controller to shift out date
+#################################################################
+def py_spi_cmd_transmit(tx_buf, tx_len, rx_len):
+ total_len = tx_len + rx_len
+ if total_len > MAX_CMD_NUM or total_len == 0:
+ return
+
+ for ii in range(total_len):
+ memory.writeMemory32(QSPI_mspi_CDRAM00+ii*4, 0x82)
+ if ii == total_len - 1:
+ memory.writeMemory32(QSPI_mspi_CDRAM00+ii*4, 0x02)
+ if ii >= tx_len:
+ tx_buf[ii] = 0xFF
+ memory.writeMemory32(QSPI_mspi_TXRAM00+ii*8, tx_buf[ii])
+
+ memory.writeMemory32(QSPI_mspi_NEWQP, 0)
+ memory.writeMemory32(QSPI_mspi_ENDQP, total_len - 1)
+
+ memory.writeMemory32(QSPI_mspi_MSPI_STATUS, 0) #clear status
+ memory.writeMemory32(QSPI_mspi_SPCR2, 0xC0) #cont_after_cmd|spe
+
+ wait_for_complete(QSPI_mspi_MSPI_STATUS, 0x00000001, 0x00000001)
+
+ if rx_len == 0:
+ return
+
+ for ii in range(total_len):
+ tx_buf[ii] = 0
+
+ for ii in range(rx_len):
+ tx_buf[ii] = 0
+ tx_buf[ii] = memory.readMemory32(QSPI_mspi_RXRAM00+4+tx_len*8+ii*8)
+
+
+#################################################################
+# Function:
+# py_erase_flash
+# Desc:
+# Main entry for flash erasing
+#################################################################
+def py_erase_flash(offset, img_len):
+ if offset%FLASH_SECTOR_SIZE != 0:
+ print " !!Error: Erasing offset must be aligned by 0x%x" %FLASH_SECTOR_SIZE
+ sys.exit(0)
+
+ print "Sflash erasing......"
+ erase_len = img_len
+ mod_size = erase_len%FLASH_SECTOR_SIZE
+ #print "mod_size =%d" %mod_size
+ if mod_size != 0:
+ erase_len = erase_len-mod_size+FLASH_SECTOR_SIZE #Must align by FLASH_SECTOR_SIZE
+
+ erasing_sector_num = erase_len/FLASH_SECTOR_SIZE
+ print "%d sectors need to be erased" %erasing_sector_num
+ for sector in range(erasing_sector_num):
+ CMD_BUF[0] = CMD_M25PXX_WREN #Write enable
+ py_spi_cmd_transmit(CMD_BUF, 1, 0)
+ CMD_BUF[0] = CMD_M25PXX_SE #Sector erase
+ CMD_BUF[1] = sector
+ CMD_BUF[2] = 0x00;
+ CMD_BUF[3] = 0x00;
+ py_spi_cmd_transmit(CMD_BUF, 4, 0)
+ print "polling status register"
+ while 1: #Wait for erase complete
+ CMD_BUF[0] = CMD_M25PXX_RDSR #Read status register
+ py_spi_cmd_transmit(CMD_BUF, 1, 1)
+ if CMD_BUF[0]&1 == 0:
+ break
+ print "polling flag status register"
+ while 1: #Wait for erase/program controller ready (for some Micron flashes)
+ CMD_BUF[0] = CMD_M25PXX_RDFSR #Read flag status register
+ py_spi_cmd_transmit(CMD_BUF, 1, 1)
+ if CMD_BUF[0]&0x80 == 0x80:
+ break
+ print " %dth secotr erased......done!" %(sector+1)
+ print "Erase done!"
+ #print "erase_len=%d %d" %(erase_len,erasing_sector_num)
+
+
+
+def py_new_write_flash():
+ #load_str = "loadfile " + sys.argv[2] + " " + num2hexstr(IMAGE_START_ADDRESS);
+ load_str = "restore " + sys.argv[2] + " binary "+num2hexstr(IMAGE_START_ADDRESS)
+ print load_str
+ cur_ec.executeDSCommand(load_str)
+ block_num = img_len/DATA_BLOCK_SIZE
+ print "block_num = %d" %block_num
+ uboot_image = open(image_path, "rb")
+ print sys.argv[1]
+
+ #Set input parameters for sfw.bin
+ memory.writeMemory32(PARAM_START_ADDRESS+0x08, DATA_START_ADDRESS);
+ memory.writeMemory32(PARAM_START_ADDRESS+0x0C, QSPI_mspi_SPCR0_MSB);
+ memory.writeMemory32(PARAM_START_ADDRESS+0x10, QSPI_mspi_NEWQP);
+ memory.writeMemory32(PARAM_START_ADDRESS+0x14, QSPI_mspi_ENDQP);
+ memory.writeMemory32(PARAM_START_ADDRESS+0x18, QSPI_mspi_SPCR2);
+ memory.writeMemory32(PARAM_START_ADDRESS+0x1C, QSPI_mspi_MSPI_STATUS);
+ memory.writeMemory32(PARAM_START_ADDRESS+0x20, QSPI_mspi_TXRAM00);
+ memory.writeMemory32(PARAM_START_ADDRESS+0x24, QSPI_mspi_RXRAM00);
+ memory.writeMemory32(PARAM_START_ADDRESS+0x28, QSPI_mspi_CDRAM00);
+ memory.writeMemory32(PARAM_START_ADDRESS+0x2C, QSPI_mspi_WRITE_LOCK);
+
+ break_str = "advance *" + num2hexstr(IMAGE_START_ADDRESS+BREAK_POINT_OFFSET)
+ for block_idx in range(block_num):
+ print "write block %d len %d" %(block_idx, DATA_BLOCK_SIZE)
+ file_content = uboot_image.read(DATA_BLOCK_SIZE)
+ tmp_file = open(TMP_FILE_PATH, "wb+")
+ tmp_file.write(file_content)
+ tmp_file.close()
+ restore_str = "restore "+TMP_FILE_PATH+" binary " + num2hexstr(DATA_START_ADDRESS)
+ cur_ec.executeDSCommand(restore_str)
+ memory.writeMemory32(PARAM_START_ADDRESS, block_idx*DATA_BLOCK_SIZE)
+ memory.writeMemory32(PARAM_START_ADDRESS+4, DATA_BLOCK_SIZE)
+ register.setValue("R0", PARAM_START_ADDRESS)
+ register.setValue("PC", IMAGE_START_ADDRESS)
+ register.setValue("SP", IMAGE_END_ADDRESS-4)
+ register.setValue("LR", IMAGE_END_ADDRESS-4)
+ #cur_ec.executeDSCommand("continue")
+ cur_ec.executeDSCommand(break_str)
+ cur_ec.getExecutionService().waitForStop(5000)
+ print " >>>>> Block %d, size %d, write done!" %(block_idx, DATA_BLOCK_SIZE)
+
+ last_len = img_len - block_num*DATA_BLOCK_SIZE
+ if last_len > 0:
+ print "write block %d len %d" %(block_num, last_len)
+ file_content = uboot_image.read(last_len)
+ tmp_file = open(TMP_FILE_PATH, "wb+")
+ tmp_file.write(file_content)
+ tmp_file.close()
+ restore_str = "restore "+TMP_FILE_PATH+" binary " + num2hexstr(DATA_START_ADDRESS)
+ cur_ec.executeDSCommand(restore_str)
+ memory.writeMemory32(PARAM_START_ADDRESS, block_num*DATA_BLOCK_SIZE)
+ memory.writeMemory32(PARAM_START_ADDRESS+4, last_len)
+ register.setValue("R0", PARAM_START_ADDRESS)
+ register.setValue("PC", IMAGE_START_ADDRESS)
+ register.setValue("SP", IMAGE_END_ADDRESS-4)
+ register.setValue("LR", IMAGE_END_ADDRESS-4)
+ #cur_ec.executeDSCommand("continue")
+
+ cur_ec.executeDSCommand(break_str)
+ cur_ec.getExecutionService().waitForStop(5000)
+ print " >>>>> Block %d, size %d, write done!" %(block_num, last_len)
+
+ uboot_image.close()
+ os.remove(TMP_FILE_PATH)
+ #cur_ec.executeDSCommand("delete breakpoints")
+
+
+state = cur_ec.getState()
+if(cmp(state, "RUNNING") == 0):
+ cur_ec.getExecutionService().stop()
+ cur_ec.getExecutionService().waitForStop(5000)
+ print "Force to stop debugger"
+ cur_ec.executeDSCommand("memory 0x18000000 +0xFFFFF0 noverify")
+
+
+QSPI_MSPI_BASE = 0x18021000
+RAM_SIZE = 0x10000
+RAM_START_ADDRESS = 0x2000000
+PARAM_AREA_SIZE = 0x400
+TINY_IMAGE_SIZE = 0xC00
+QSPI_mspi_SPCR0_LSB = QSPI_MSPI_BASE+0x200
+QSPI_mspi_SPCR0_MSB = QSPI_MSPI_BASE+0x204
+QSPI_mspi_SPCR1_LSB = QSPI_MSPI_BASE+0x208
+QSPI_mspi_SPCR1_MSB = QSPI_MSPI_BASE+0x20C
+QSPI_mspi_NEWQP = QSPI_MSPI_BASE+0x210
+QSPI_mspi_ENDQP = QSPI_MSPI_BASE+0x214
+QSPI_mspi_SPCR2 = QSPI_MSPI_BASE+0x218
+QSPI_mspi_MSPI_STATUS = QSPI_MSPI_BASE+0x220
+QSPI_mspi_TXRAM00 = QSPI_MSPI_BASE+0x240
+QSPI_mspi_RXRAM00 = QSPI_MSPI_BASE+0x2C0
+QSPI_mspi_CDRAM00 = QSPI_MSPI_BASE+0x340
+QSPI_mspi_WRITE_LOCK = QSPI_MSPI_BASE+0x380
+
+QSPI_bspi_registers_MAST_N_BOOT_CTRL = QSPI_MSPI_BASE+0x008
+QSPI_bspi_registers_BUSY_STATUS = QSPI_MSPI_BASE+0x00C
+QSPI_bspi_registers_B0_CTRL = QSPI_MSPI_BASE+0x018
+QSPI_bspi_registers_B1_CTRL = QSPI_MSPI_BASE+0x020
+
+PARAM_START_ADDRESS = RAM_START_ADDRESS #Parameter area
+IMAGE_START_ADDRESS = RAM_START_ADDRESS+PARAM_AREA_SIZE
+IMAGE_END_ADDRESS = IMAGE_START_ADDRESS+TINY_IMAGE_SIZE
+DATA_START_ADDRESS = IMAGE_END_ADDRESS #Data area
+DATA_BLOCK_SIZE = RAM_START_ADDRESS + RAM_SIZE - DATA_START_ADDRESS #The max length of data which could be saved in data area
+
+py_spi_init() #Init spi
+py_erase_flash(FLASH_PROGRAM_OFFSET, img_len) #Erase sector according to offset and img_len
+py_new_write_flash()
+py_bspi_enable()
+
+print "--End of script--"
+
+
diff --git a/Firmware/pcie/dnx/v2.5.3/tools/flashwrite/ARM_DS-5/sfw.bin b/Firmware/pcie/dnx/v2.5.3/tools/flashwrite/ARM_DS-5/sfw.bin
Binary files differ.
