pcie_gen3_fw_install.txt (10124B)
1 2 NOTE: For DNX devices (BCM88xxx devices), please refer to the "DNX16 Hardware 3 Design Guidelines for StrataDNX 16-nm Devices", DNX16-AN1xx.pdf, "DNX16 4 (BCM88790, BCM88690) QSPI Flash Programming" section. 5 6 How to install PCIe FW Loader 7 ============================= 8 PCIe Gen3 FW can be programmed into serial flash using various methods. The 9 customer can use whatever method suits their manufacturing flow best. 10 11 Method 1: Using external flash programmer or gang programmer 12 This method requires all of the flash memory devices to be pre-programmed 13 with the provided firmware using an external programming device prior to 14 being mounted on the board. See programmers manual of external programmer for 15 instructions on how to erase and program serial flash device. 16 17 Method 2: Using ARM DS-5 and ARM DSTREAM 18 This method allows a blank flash device to be populated on the board at the 19 time of manufacturing. A small programming utility as well as the PCIe 20 firmware are loaded into the ARM R5 inside of the Broadcom switch device via 21 its JTAG interface. Once the load is complete, the programming utility will 22 be run by the ARM R5 and will program the firmware to the flash device. This 23 package includes further instructions on this flow in 24 tools/flashwrite/ARM_DS-5 25 26 Method 3: Initially advertise Gen1-only support from PCIe link partner 27 This method allows a blank flash device to be populated on the board at the 28 time of manufacturing. The Broadcom switch device is strapped to support PCIe 29 Gen3 and boot using the firmware (BOOT_DEV[2:0]=3'b000, MHOST0_BOOT_DEV=1'b1, 30 and PCIE_FORCE_GENTYPE[1:0]=2'b00). Since the PCIe link partner is 31 advertising Gen1 only support, the PCIe link will be able to come up and the 32 device will enumerate and function. The Broadcom SDK can then be loaded and 33 the SDK's PCIe Gen3 firmware in-field upgrade utility (SDK diag command 34 "pciephy fw load") can be used to program the firmware to the blank flash 35 device. Following that, the system can be reset and the PCIe link partner 36 can be reconfigured to advertise all supported PCIe speeds. 37 38 Syntax of in-field upgrade command: 39 BCM.0> pciephy fw load <Firmware file> 40 e.g., 41 BCM.0> pciephy fw load pcieg3fw.bin 42 43 The flash driver in SDK is based on MT25QL256. If the mounted flash part is 44 compatible with MT25QL256's instruction set but unrecognized by the driver, 45 please use SoC property "pcie_flash_mem_params" to specify the parameters of 46 the flash device. 47 48 pcie_flash_mem_params=<id>,<sector_size>,<page_size> 49 <id>: Manufacturer ID. 50 <sector_size>: The samllest erase unit in bytes. 51 <page_size>: The smallest access unit in bytes. 52 53 Method 4: Initially advertise Gen1-only support from Broadcom switch device 54 This method allows a blank flash device to be populated on the board at the 55 time of manufacturing. The Broadcom switch device is initially strapped to 56 support PCIe Gen1 and boot using the firmware (BOOT_DEV[2:0]=3'b000, 57 MHOST0_BOOT_DEV=1'b1, and PCIE_FORCE_GENTYPE[1:0]=2'b01). The PCIe link 58 will be able to come up and the device will enumerate and function. The 59 Broadcom SDK can then be loaded and the SDK's PCIe Gen3 firmware in-field 60 upgrade utility (SDK diag command "pciephy fw load") can be used to program 61 the firmware to the blank flash device. Following that, the 62 PCIE_FORCE_GENTYPE0 strap signal should be changed to 1'b0 and system should 63 be reset to advertise all supported PCIe speeds. 64 65 Syntax of in-field upgrade command: 66 BCM.0> pciephy fw load <Firmware file> 67 e.g., 68 BCM.0> pciephy fw load pcieg3fw.bin 69 70 Method 5: Use I2C to write the firmware. 71 This requires the CPU that the SDK is running on to be an I2C master of an 72 I2C bus to which the Broadcom switch device is connected. 73 In such a case you need to know the I2C bus number (as Linux enumerates I2C 74 buses). And also know the I2C device number of the Broadcom switch device in 75 the bus which is by default 0x44. 76 This method also requires the SDK to be built with CPU I2C support. 77 This means that FEATURE_LIST in the make.local file should contain CPU_I2C . 78 79 Here is an example command making pciephy firmware handling use I2c with a 80 specific bus number and device number: 81 BCM.0> pciephy fw access i2c 0 0x44 82 83 After this command you can either test that I2C device access work using: 84 "pciephy fw version" or directly attempt to write the firmware to the flash 85 memory: "pciephy fw load <firmware file>" 86 87 If the BDE you are using with the SDK supports I2C access to the device 88 internally, removing the need to specify the I2C bus and device numbers, 89 instead of "pciephy fw access i2c <bus id> <device id>" you may use 90 "pciephy fw i2c_bde". 91 92 If the SDK does not recognize any switch device using PCIe, the pciephy 93 command will not work. In this case a dummy device needs to be added using 94 the following soc properties, where the PCIe device and revision IDs may be 95 replaced with the IDs of the relevant device. 96 extra_unit_min=0 97 extra_unit_max=0 98 extra_unit.0=1 99 pci_override_dev.0=0x8690 100 pci_override_rev.0=1 101 102 103 How to boot and verify PCIe FW 104 =================================== 105 1. Ensure that strap signals are set to load the firmware: 106 BOOT_DEV[2:0] = 3'b000 107 MHOST0_BOOT_DEV = 1'b1 108 PCIE_FORCE_GENTYPE[1:0] = 2'b00 109 110 2. Power On the system 111 112 3. Load and run linux 113 a) At a linux prompt run 114 lspci -d 0x14e4: -vvv 115 116 b) The Broadcom switch device should have enumerated and should show 117 something similar to the following: 118 "05:00.0 Ethernet controller: Broadcom Limited Device b870 (rev 01)" 119 120 c) In the lspci output, check that the link status register field shows 121 speed set to 8GT/s 122 8GT/s - PCIe Gen3 123 5GT/s - PCIe Gen2 124 2.5GT/s - PCIe Gen1 125 126 d) check that link capability register shows "ASPM not supported" and 127 link control register shows "ASPM disabled" 128 129 e) Run SDK and verify that "tr 502" completes successfully 130 131 How to apply custom/user settings in MAC/PHY registers 132 ====================================================== 133 It is anticipated that some of MAC/PHY settings, like TX FIR etc, may be tuned 134 by customer based on customer system requirements. PCIe Gen3 FW offers 135 provision for such cases. This provision offers optional custom settings 136 programming prior to and after SerDes FW loading. This provision requires 137 custom or system specific PCIe MAC/PHY register settings to be programmed at 138 30K offset of QSPI flash in the format described below i.e 139 {type, address, value} triplets. 140 141 ----------------------- __ 142 | 0x50434945 | | 143 | 0x41524753 | |__ Header, fixed, 4x32-bit words 144 | 0x00000000 | | 145 | 0x00000000 | __| 146 ----------------------- __ 147 | 0x5052454c | | 148 | {type, addr, val} | | 149 | {type, addr, val} | | Optional pre FW load settings 150 | : | | Must have 0x5052454c as first word 151 | : | |__ followed by {type, addr, val} 152 | : | | triplets (triplet - 3x32bit words) 153 | : | | type: 0 - MAC address, 1 - PHY addr 154 | : | | addr: MAC/PHY register address 155 | {type, addr, val} | __| Val: Value to be programmed 156 ----------------------- __ 157 | 0x504f5354 | | 158 | {type, addr, val} | | Optional post FW load settings 159 | : | | Must have 0x504f5354 as first word 160 | : | |__ followed by {type, addr, val} 161 | : | | triplets (triplet - 3x32bit words). 162 | : | | type: 0 - MAC address, 1 - PHY addr 163 | : | | addr: MAC/PHY register address 164 | {type, addr, val} | __| Val: Value to be programmed 165 ----------------------- __ 166 | 0x00454E44 | |__Footer, fixed, 2x32-bit words 167 | 0x41524753 | __| 168 ----------------------- 169 170 User can program up to maximum 168 triplets (i.e 504x32-bit words). 171 There is no restriction on number of triplets for pre FW load settings or post 172 FW load settings, provided total number of triplets do not exceed max limit 173 of 168. 174 175 Customer settings are optional, may include either of or both pre and post FW 176 load settings. 177 178 A sample format file in text format (custom.txt) and perl based text to binary 179 conversion utility provided under tools/custom/ directory of this 180 release package to help customer to generate customer settings in binary format. 181 182 Customer settings in text format may have comments with '#' at the begining of 183 the line and also blank lines which will be ignored by text to binary conversion 184 tool. 185 186 Syntax of text to binary conversion tool: 187 perl custom_ascii2bin.pl <input text file> <output file> 188 189 Example: Conversion of sample custom.txt file 190 191 linux#: perl custom_ascii2bin.pl custom.txt custom.bin 192 454943505347524100000000000000004c45525000000000381800000040088254534f5001000000b0d000008024000001000000b1d0000007000000444E450053475241 193 194 Hexdump of generated file should look like the following: 195 linux#: hexdump -c custom.bin 196 0000000 E I C P S G R A \0 \0 \0 \0 \0 \0 \0 \0 197 0000010 L E R P \0 \0 \0 \0 8 030 \0 \0 \0 @ \b 202 198 0000020 T S O P 001 \0 \0 \0 � � \0 \0 200 $ \0 \0 199 0000030 001 \0 \0 \0 � � \0 \0 \a \0 \0 \0 D N E \0 200 0000040 S G R A 201 0000044 202 203 Installing custom settings binary file: 204 1) Append the custom settings binary file to the PCIe FW binary file (bins/pciefw-r5.bin or bins/pciefw-r5-m7.bin) 205 e.g., 206 cat pciefw-r5.bin custom.bin >custom_pciefw-r5.bin 207 2) Install the appended binary into QSPI flash at offset 0x0 using one of the 208 FW installation methods mentioned above.