openbcm

commit 60a117d16805bea3d3c69106ad703d3d9afc454c
parent 0f43eb2be0f63b7b0d3952e61cac0096af83f808
Author: Broadcom SDK Release <sdk.releases@broadcom.com>
Date:   Mon, 13 Jan 2020 15:28:42 -0800

SDK-177001: Fixed synce divisor settings for blackhawk TSC core for various s...

Devices: 56980_A0
Module: PortMod

Symptom:
SyncE SDM divisor settings to be programmed in portmod driver

Fixed synce divisor settings for blackhawk TSC core for various speed
and interface modes

Diffstat:
M
sdk-6.5.16/libs/phymod/chip/tscbh/tier1/tbhmod.h
 | 
6
++++++
M
sdk-6.5.16/libs/phymod/chip/tscbh/tier2/tscbh.c
 | 
46
++++++++++++++++++++++++++++++++++++++++++++--
M
sdk-6.5.16/src/soc/portmod/pms/pm8x50.c
 | 
20
++++++++++++++++++--

3 files changed, 68 insertions(+), 4 deletions(-)
diff --git a/sdk-6.5.16/libs/phymod/chip/tscbh/tier1/tbhmod.h b/sdk-6.5.16/libs/phymod/chip/tscbh/tier1/tbhmod.h
@@ -84,6 +84,12 @@
 
 #define TSCBH_PMD_CRC_UCODE_VERIFY 1
 
+#define TSCBH_SYNCE_SDM_DIVISOR_20G_VCO  10560
+#define TSCBH_SYNCE_SDM_DIVISOR_25G_VCO  12800
+#define TSCBH_SYNCE_SDM_DIVISOR_25GP78125_VCO  13200
+#define TSCBH_SYNCE_SDM_DIVISOR_26G_VCO  13600
+
+
 #define TSCBH_CORE_TO_PHY_ACCESS(_phy_access, _core_access) \
     do{\
         PHYMOD_MEMCPY(&(_phy_access)->access, &(_core_access)->access, sizeof((_phy_access)->access));\
diff --git a/sdk-6.5.16/libs/phymod/chip/tscbh/tier2/tscbh.c b/sdk-6.5.16/libs/phymod/chip/tscbh/tier2/tscbh.c
@@ -3529,14 +3529,56 @@ int tscbh_phy_synce_clk_ctrl_set(const phymod_phy_access_t* phy,
                                  phymod_synce_clk_ctrl_t cfg)
 {
     phymod_phy_access_t phy_copy;
+    uint32_t current_pll_index, pll_div, sdm_val;
+    int osr_mode;
 
     PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy));
 
     PHYMOD_IF_ERR_RETURN
          (tbhmod_synce_mode_set(&phy_copy.access, cfg.stg0_mode, cfg.stg1_mode));
 
-    PHYMOD_IF_ERR_RETURN
-        (tbhmod_synce_clk_ctrl_set(&phy_copy.access, cfg.sdm_val));
+    /* next check if SDM mode, if yes, needs to figure out the SDM value based on the current */
+    if ((cfg.stg0_mode == 0x2) && (cfg.stg1_mode == 0x0)) {
+        /* vco the port is using */
+        /* first get the PLL index */
+        PHYMOD_IF_ERR_RETURN
+            (blackhawk_lane_pll_selection_get(&phy_copy.access, &current_pll_index));
+
+        /* next get the OSR the port is current using */
+        PHYMOD_IF_ERR_RETURN
+            (blackhawk_osr_mode_get(&phy_copy.access, &osr_mode));
+
+        /* next get the VCO the port is current using */
+        phy_copy.access.pll_idx = current_pll_index;
+        phy_copy.access.lane_mask = 0x1;
+        PHYMOD_IF_ERR_RETURN
+            (blackhawk_tsc_INTERNAL_read_pll_div(&phy_copy.access, &pll_div));
+
+        /* next based on the VCO value and osr mode, set the SDM value properly */
+        /* first check 26G VCO */
+        if ((pll_div == TBHMOD_PLL_MODE_DIV_170) || (pll_div == TBHMOD_PLL_MODE_DIV_85))  {
+            sdm_val = TSCBH_SYNCE_SDM_DIVISOR_26G_VCO;
+        } else if ((pll_div == TBHMOD_PLL_MODE_DIV_165) || (pll_div == TBHMOD_PLL_MODE_DIV_82P5)) {
+            sdm_val = TSCBH_SYNCE_SDM_DIVISOR_25GP78125_VCO;
+        } else if ((pll_div == TBHMOD_PLL_MODE_DIV_132) || (pll_div == TBHMOD_PLL_MODE_DIV_66)) {
+            sdm_val = TSCBH_SYNCE_SDM_DIVISOR_20G_VCO;
+        } else if ((pll_div == TBHMOD_PLL_MODE_DIV_160) || (pll_div == TBHMOD_PLL_MODE_DIV_80)) {
+            sdm_val = TSCBH_SYNCE_SDM_DIVISOR_25G_VCO;
+        } else {
+            PHYMOD_DEBUG_ERROR(("Unsupported VCOs\n"));
+            return PHYMOD_E_UNAVAIL;
+        }
+
+        /* need to adjust the SDM value based on OSR mode */
+        if (osr_mode == 1) {
+            sdm_val >>= 1;
+        }
+
+        /* next configure the SDM value */
+        PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy));
+        PHYMOD_IF_ERR_RETURN
+            (tbhmod_synce_clk_ctrl_set(&phy_copy.access, sdm_val));
+    }
 
     return PHYMOD_E_NONE;
 }
diff --git a/sdk-6.5.16/src/soc/portmod/pms/pm8x50.c b/sdk-6.5.16/src/soc/portmod/pms/pm8x50.c
@@ -8698,6 +8698,7 @@ int pm8x50_port_synce_clk_ctrl_set(int unit, int port, pm_info_t pm_info,
     portmod_access_get_params_t params;
     phymod_phy_access_t phy_access;
     int nof_phys;
+    int config_valid = 0;
 
     SOC_INIT_FUNC_DEFS;
 
@@ -8710,8 +8711,23 @@ int pm8x50_port_synce_clk_ctrl_set(int unit, int port, pm_info_t pm_info,
     phy_synce_cfg.stg1_mode = cfg->stg1_mode;
     phy_synce_cfg.sdm_val = cfg->sdm_val;
 
-    _SOC_IF_ERR_EXIT(phymod_phy_synce_clk_ctrl_set(&phy_access,
-                                                   phy_synce_cfg));
+    /* next validate the stage0/1 config */
+    /* first check legacy mode */
+    if (cfg->stg0_mode == 0x0) {
+        config_valid = 1;
+    } else if ((cfg->stg0_mode == 0x1) && (cfg->stg1_mode == 0x2)) {
+        config_valid = 1;
+    } else if ((cfg->stg0_mode == 0x2) && (cfg->stg1_mode == 0x0)) {
+        config_valid = 1;
+    }
+
+    if (config_valid) {
+        _SOC_IF_ERR_EXIT(phymod_phy_synce_clk_ctrl_set(&phy_access,
+                                                       phy_synce_cfg));
+    } else {
+        _SOC_EXIT_WITH_ERR(SOC_E_CONFIG,
+                  (_SOC_MSG("SyncE config is not valid \n")));
+    }
 
 exit:
     SOC_FUNC_RETURN;