tbhmod.h (23482B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *---------------------------------------------------------------------- 15 * Description: define enumerators 16 *----------------------------------------------------------------------*/ 17 /* 18 * 19 * $Copyright: 20 * All Rights Reserved.$ 21 */ 22 23 #ifndef _tbhmod_H_ 24 #define _tbhmod_H_ 25 26 #ifndef _DV_TB_ 27 #define _SDK_TBHMOD_ 1 28 #endif 29 30 #ifdef _DV_TB_ 31 #ifdef LINUX 32 #include <stdint.h> 33 #endif 34 #include <stdio.h> 35 #include <string.h> 36 #include <stdlib.h> 37 #include "errno.h" 38 #endif 39 40 #ifdef _SDK_TBHMOD_ 41 #include <phymod/phymod.h> 42 #include <phymod/phymod_debug.h> 43 #include "tbhmod_enum_defines.h" 44 #endif 45 46 #ifdef _SDK_TBHMOD_ 47 #define PHYMOD_ST phymod_access_t 48 #else 49 #define PHYMOD_ST tbhmod_dv_st 50 #endif 51 52 #include "tbhmod_spd_ctrl.h" 53 54 #define TSCBH_NOF_LANES_IN_CORE 8 55 56 #define TBHMOD_FEC_NOT_SUPRTD 0 57 #define TBHMOD_FEC_SUPRTD_NOT_REQSTD 1 58 #define TBHMOD_FEC_CL74_SUPRTD_REQSTD 4 59 #define TBHMOD_FEC_CL91_SUPRTD_REQSTD 8 60 61 #define TBHMOD_CL73_ABILITY_50G_KR1_CR1_POSITION 13 62 #define TBHMOD_CL73_ABILITY_100G_KR2_CR2_POSITION 14 63 #define TBHMOD_CL73_ABILITY_200G_KR4_CR4_POSITION 15 64 65 #define TBHMOD_VCO_NONE 0x0 66 #define TBHMOD_VCO_20G 0x1 67 #define TBHMOD_VCO_25G 0x2 68 #define TBHMOD_VCO_26G 0x4 69 #define TBHMOD_VCO_PCS_BYPASS 0x8 70 71 #define TSCBH_HW_SPEED_ID_TABLE_SIZE 64 72 #define TSCBH_HW_AM_TABLE_SIZE 64 73 #define TSCBH_HW_UM_TABLE_SIZE 64 74 75 #define REF_CLOCK_312P5 312500000 76 #define REF_CLOCK_156P25 156250000 77 78 79 #define TSCBH_ID0 0x600d 80 #define TSCBH_ID1 0x8770 81 #define TSCBH_PHY_ALL_LANES 0xff 82 #define TSCBH_TX_TAP_NUM 12 83 #define TSCBH_FORCED_SPEED_ID_OFFSET 56 84 85 #define TSCBH_PMD_CRC_UCODE_VERIFY 1 86 87 #define TSCBH_SYNCE_SDM_DIVISOR_20G_VCO 10560 88 #define TSCBH_SYNCE_SDM_DIVISOR_25G_VCO 12800 89 #define TSCBH_SYNCE_SDM_DIVISOR_25GP78125_VCO 13200 90 #define TSCBH_SYNCE_SDM_DIVISOR_26G_VCO 13600 91 92 93 #define TSCBH_CORE_TO_PHY_ACCESS(_phy_access, _core_access) \ 94 do{\ 95 PHYMOD_MEMCPY(&(_phy_access)->access, &(_core_access)->access, sizeof((_phy_access)->access));\ 96 (_phy_access)->type = (_core_access)->type; \ 97 (_phy_access)->port_loc = (_core_access)->port_loc; \ 98 (_phy_access)->device_op_mode = (_core_access)->device_op_mode; \ 99 (_phy_access)->access.lane_mask = TSCBH_PHY_ALL_LANES; \ 100 }while(0) 101 102 /* So far 4 bits debug mask are used by TBHMOD */ 103 #define TBHMOD_DBG_MEM (1L << 4) /* allocation/object */ 104 #define TBHMOD_DBG_REGACC (1L << 3) /* Print all register accesses */ 105 #define TBHMOD_DBG_FUNCVALOUT (1L << 2) /* All values returned by Tier1*/ 106 #define TBHMOD_DBG_FUNCVALIN (1L << 1) /* All values pumped into Tier1*/ 107 #define TBHMOD_DBG_FUNC (1L << 0) /* Every time we enter a Tier1*/ 108 109 typedef enum { 110 TBHMOD_AN_MODE_CL73 = 0, 111 TBHMOD_AN_MODE_CL73_BAM, 112 TBHMOD_AN_MODE_NONE, 113 TBHMOD_AN_MODE_CL73_MSA, 114 TBHMOD_AN_MODE_MSA, 115 TBHMOD_AN_MODE_TYPE_COUNT 116 }tbhmod_an_type_t; 117 118 typedef enum { 119 TBHMOD_NO_PAUSE = 0, 120 TBHMOD_SYMM_PAUSE, 121 TBHMOD_ASYM_PAUSE, 122 TBHMOD_ASYM_SYMM_PAUSE, 123 TBHMOD_AN_PAUSE_COUNT 124 }tbhmod_an_pause_t; 125 126 typedef enum { 127 OVERRIDE_CLEAR = 0x0000, 128 OVERRIDE_NUM_LANES = 0x0001, 129 OVERRIDE_OS_MODE = 0x0002, 130 OVERRIDE_T_FIFO_MODE = 0x0004, 131 OVERRIDE_T_ENC_MODE = 0x0008, 132 OVERRIDE_T_HG2_ENABLE = 0x0010, 133 OVERRIDE_T_PMA_BTMX_MODE_OEN = 0x0020, 134 OVERRIDE_SCR_MODE = 0x0040, 135 OVERRIDE_DESCR_MODE_OEN = 0x0100, 136 OVERRIDE_DEC_TL_MODE = 0x0200, 137 OVERRIDE_DESKEW_MODE = 0x0400, 138 OVERRIDE_DEC_FSM_MODE = 0x0800, 139 OVERRIDE_R_HG2_ENABLE = 0x8001, 140 OVERRIDE_BS_SM_SYNC_MODE_OEN = 0x1000, 141 OVERRIDE_BS_SYNC_EN_OEN = 0x1001, 142 OVERRIDE_BS_DIST_MODE_OEN = 0x1002, 143 OVERRIDE_BS_BTMX_MODE_OEN = 0x1004, 144 OVERRIDE_CL72_EN = 0x1008, 145 OVERRIDE_CLOCKCNT0 = 0x2000, 146 OVERRIDE_CLOCKCNT1 = 0x2001, 147 OVERRIDE_LOOPCNT0 = 0x2002, 148 OVERRIDE_LOOPCNT1 = 0x2004, 149 OVERRIDE_MAC_CREDITGENCNT = 0x2008, 150 OVERRIDE_T_CL91_CW_SCR = 0x2009, 151 OVERRIDE_T_5BIT_XOR_EN = 0x200a, 152 OVERRIDE_T_PMA_CL91_MUX_SEL = 0x200b, 153 OVERRIDE_T_PMA_WM = 0x200c, 154 OVERRIDE_T_PMA_BTMX_DELAY = 0x200d, 155 OVERRIDE_AM_SPACING_MUL = 0x200e, 156 OVERRIDE_CL91_BLKSYNC_MODE = 0x200f, 157 OVERRIDE_R_MERGE_MODE = 0x3000, 158 OVERRIDE_R_CL91_CW_SCR = 0x3001, 159 OVERRIDE_R_TC_IN_MODE = 0x3002, 160 OVERRIDE_R_TC_MODE = 0x3003, 161 OVERRIDE_R_5BIT_XOR_EN = 0x3004, 162 OVERRIDE_R_TC_OUT_MODE = 0x3005, 163 OVERRIDE_R_HG2_EN = 0x3006, 164 165 OVERRIDE_NUM_LANES_DIS = 0x00f0, 166 OVERRIDE_OS_MODE_DIS = 0x00f1, 167 OVERRIDE_T_FIFO_MODE_DIS = 0x00f2, 168 OVERRIDE_T_ENC_MODE_DIS = 0x00f3, 169 OVERRIDE_T_HG2_ENABLE_DIS = 0x00f4, 170 OVERRIDE_T_PMA_BTMX_MODE_OEN_DIS= 0x00f5, 171 OVERRIDE_SCR_MODE_DIS = 0x00f6, 172 OVERRIDE_DESCR_MODE_OEN_DIS = 0x00f7, 173 OVERRIDE_DEC_TL_MODE_DIS = 0x00f8, 174 OVERRIDE_DESKEW_MODE_DIS = 0x00f9, 175 OVERRIDE_DEC_FSM_MODE_DIS = 0x00fa, 176 OVERRIDE_R_HG2_ENABLE_DIS = 0x00fb, 177 OVERRIDE_BS_SM_SYNC_MODE_OEN_DIS= 0x00fc, 178 OVERRIDE_BS_SYNC_EN_OEN_DIS = 0x00fd, 179 OVERRIDE_BS_DIST_MODE_OEN_DIS = 0x00fe, 180 OVERRIDE_BS_BTMX_MODE_OEN_DIS = 0x00e0, 181 OVERRIDE_CL72_EN_DIS = 0x00e1, 182 OVERRIDE_CLOCKCNT0_DIS = 0x00e2, 183 OVERRIDE_CLOCKCNT1_DIS = 0x00e3, 184 OVERRIDE_LOOPCNT0_DIS = 0x00e4, 185 OVERRIDE_LOOPCNT1_DIS = 0x00e5, 186 OVERRIDE_MAC_CREDITGENCNT_DIS = 0x00e6, 187 OVERRIDE_T_CL91_CW_SCR_DIS = 0x00e7, 188 OVERRIDE_T_5BIT_XOR_EN_DIS = 0x00e8, 189 OVERRIDE_T_PMA_CL91_MUX_SEL_DIS = 0x00e9, 190 OVERRIDE_T_PMA_WM_DIS = 0x00ea, 191 OVERRIDE_T_PMA_BTMX_DELAY_DIS = 0x00eb, 192 OVERRIDE_AM_SPACING_MUL_DIS = 0x00ec, 193 OVERRIDE_CL91_BLKSYNC_MODE_DIS = 0x00ed, 194 OVERRIDE_R_MERGE_MODE_DIS = 0x00ee, 195 OVERRIDE_R_CL91_CW_SCR_DIS = 0x00d0, 196 OVERRIDE_R_TC_IN_MODE_DIS = 0x00d1, 197 OVERRIDE_R_TC_MODE_DIS = 0x00d2, 198 OVERRIDE_R_5BIT_XOR_EN_DIS = 0x00d3, 199 OVERRIDE_R_TC_OUT_MODE_DIS = 0x00d4, 200 OVERRIDE_R_HG2_EN_DIS = 0x00d5 201 } override_type_t; 202 203 typedef enum { 204 TBHMOD_REF_CLK_156P25MHZ = 1, 205 TBHMOD_REF_CLK_312P5MHZ = 2 206 } tbhmod_refclk_t; 207 208 typedef enum { 209 TBHMOD_REV_NUM_0 = 0, 210 TBHMOD_REV_NUM_1 = 1 211 } tbhmod_rev_num_t; 212 /** 213 \struct tbhmod_an_adv_ability_s 214 TBD 215 */ 216 217 typedef struct tbhmod_an_control_s { 218 tbhmod_an_type_t an_type; 219 uint16_t num_lane_adv; 220 uint16_t enable; 221 tbhmod_an_property_enable tbhmod_an_property_type; 222 } tbhmod_an_control_t; 223 224 /** 225 \struct tbhmod_an_init_s 226 227 This embodies all parameters required to program autonegotiation features in the 228 PHY for both CL37 and CL73 type autonegotiation and the BAM variants. 229 For details of individual fields, please refer to microarchitectural doc. 230 */ 231 typedef struct tbhmod_an_init_s{ 232 uint16_t an_fail_cnt; 233 uint16_t linkfailtimer_dis; 234 uint16_t linkfailtimerqua_en; 235 uint16_t an_good_check_trap; 236 uint16_t an_good_trap; 237 uint16_t bam73_adv_oui; 238 uint16_t bam73_det_oui; 239 uint16_t hpam_adv_oui; 240 uint16_t hpam_det_oui; 241 uint16_t disable_rf_report; 242 uint16_t cl73_remote_fault; 243 uint16_t cl73_nonce_match_over; 244 uint16_t cl73_nonce_match_val; 245 uint16_t cl73_transmit_nonce; 246 uint16_t base_selector; 247 } tbhmod_an_init_t; 248 249 250 /** 251 \struct tbhmod_an_timers_s 252 TBD 253 */ 254 typedef struct tbhmod_an_timers_s{ 255 uint16_t value; 256 } tbhmod_an_timers_t; 257 258 /* struct for interrupts status */ 259 typedef struct tbhmod_intr_status_s { 260 phymod_interrupt_type_t type; 261 uint8_t is_1b_err; 262 uint8_t is_2b_err; 263 } tbhmod_intr_status_t; 264 265 /*struct for 1588 tx info*/ 266 typedef struct tbhmod_ts_tx_info_s { 267 uint16_t ts_val_lo; 268 uint16_t ts_val_mid; 269 uint16_t ts_val_hi; 270 uint16_t ts_seq_id; 271 uint16_t ts_sub_nanosec; 272 } tbhmod_ts_tx_info_t; 273 274 /* MACROs for AN PAGE definition*/ 275 #define BRCM_OUI 0xAF7 276 #define BRCM_BAM_CODE 0x3 277 #define MSA_OUI 0x6A737D /* OUI defined for consortium 25G */ 278 #define MSA_OUI_13to23 0x353 279 #define MSA_OUI_2to12 0x4DF 280 #define MSA_OUI_0to1 0x1 281 282 /* Below macros are defined based on IEEE and MSA 25G spec 283 * for detailed information Please refer to the 284 * IEEE 802.3by section 73.6 Link codeword encoding 285 * MSA Spec section 3.2.5 Auto-negotiation Figure 10 286 */ 287 288 /* 50GBASE_KR_CR, 100GBASE_KR2_CR2, 200GBASE_KR4_CR4 289 * bit position is proposed in 802.3cb, but not finilized. 290 * The corresponding Macro value may need revisit. 291 */ 292 293 /* Base page definitions */ 294 #define AN_BASE0_PAGE_PAUSE_MASK 0x3 295 #define AN_BASE0_PAGE_PAUSE_OFFSET 0xA 296 297 #define AN_BASE0_PAGE_NP_MASK 0x1 298 #define AN_BASE0_PAGE_NP_OFFSET 0xF 299 300 #define AN_BASE1_TECH_ABILITY_10G_KR1_MASK 0x1 301 #define AN_BASE1_TECH_ABILITY_10G_KR1_OFFSET 0x7 302 303 #define AN_BASE1_TECH_ABILITY_40G_KR4_MASK 0x1 304 #define AN_BASE1_TECH_ABILITY_40G_KR4_OFFSET 0x8 305 306 #define AN_BASE1_TECH_ABILITY_40G_CR4_MASK 0x1 307 #define AN_BASE1_TECH_ABILITY_40G_CR4_OFFSET 0x9 308 309 #define AN_BASE1_TECH_ABILITY_100G_KR4_MASK 0x1 310 #define AN_BASE1_TECH_ABILITY_100G_KR4_OFFSET 0xC 311 312 #define AN_BASE1_TECH_ABILITY_100G_CR4_MASK 0x1 313 #define AN_BASE1_TECH_ABILITY_100G_CR4_OFFSET 0xD 314 315 #define AN_BASE1_TECH_ABILITY_25G_KRS1_CRS1_MASK 0x1 316 #define AN_BASE1_TECH_ABILITY_25G_KRS1_CRS1_OFFSET 0xE 317 318 #define AN_BASE1_TECH_ABILITY_25G_KR1_CR1_MASK 0x1 319 #define AN_BASE1_TECH_ABILITY_25G_KR1_CR1_OFFSET 0xF 320 321 #define AN_BASE2_TECH_ABILITY_50G_KR1_CR1_MASK 0x1 322 #define AN_BASE2_TECH_ABILITY_50G_KR1_CR1_OFFSET 0x2 323 324 #define AN_BASE2_TECH_ABILITY_100G_KR2_CR2_MASK 0x1 325 #define AN_BASE2_TECH_ABILITY_100G_KR2_CR2_OFFSET 0x3 326 327 #define AN_BASE2_TECH_ABILITY_200G_KR4_CR4_MASK 0x1 328 #define AN_BASE2_TECH_ABILITY_200G_KR4_CR4_OFFSET 0x4 329 330 #define AN_BASE2_25G_RS_FEC_ABILITY_REQ_MASK 0x1 331 #define AN_BASE2_25G_RS_FEC_ABILITY_REQ_OFFSET 0xC 332 333 #define AN_BASE2_25G_BASE_R_FEC_ABILITY_REQ_MASK 0x1 334 #define AN_BASE2_25G_BASE_R_FEC_ABILITY_REQ_OFFSET 0xD 335 336 #define AN_BASE2_CL74_ABILITY_REQ_SUP_MASK 0x3 337 #define AN_BASE2_CL74_ABILITY_REQ_SUP_OFFSET 0xE 338 339 /* Message Page definitions */ 340 341 #define AN_MSG_PAGE1_OUI_13to23_MASK 0x7FF 342 #define AN_MSG_PAGE1_OUI_13to23_OFFSET 0x0 343 344 #define AN_MSG_PAGE2_OUI_2to12_MASK 0x7FF 345 #define AN_MSG_PAGE2_OUI_2to12_OFFSET 0x0 346 347 /* Unformatted Page definitions */ 348 #define AN_UF_PAGE0_UD_0to8_MASK 0x1FF 349 #define AN_UF_PAGE0_UD_0to8_OFFSET 0x0 350 351 #define AN_UF_PAGE0_OUI_MASK 0x3 352 #define AN_UF_PAGE0_OUI_OFFSET 0x9 353 354 /* Unformatted Page for CL73BAM only*/ 355 #define AN_UF_PAGE1_BAM_20G_KR1_MASK 0x1 356 #define AN_UF_PAGE1_BAM_20G_KR1_OFFSET 0x2 357 358 #define AN_UF_PAGE1_BAM_20G_CR1_MASK 0x1 359 #define AN_UF_PAGE1_BAM_20G_CR1_OFFSET 0x3 360 361 #define AN_UF_PAGE1_BAM_25G_KR1_MASK 0x1 362 #define AN_UF_PAGE1_BAM_25G_KR1_OFFSET 0x4 363 364 #define AN_UF_PAGE1_BAM_25G_CR1_MASK 0x1 365 #define AN_UF_PAGE1_BAM_25G_CR1_OFFSET 0x5 366 367 #define AN_UF_PAGE1_BAM_40G_KR2_MASK 0x1 368 #define AN_UF_PAGE1_BAM_40G_KR2_OFFSET 0x6 369 370 #define AN_UF_PAGE1_BAM_40G_CR2_MASK 0x1 371 #define AN_UF_PAGE1_BAM_40G_CR2_OFFSET 0x7 372 373 #define AN_UF_PAGE1_BAM_50G_KR2_MASK 0x1 374 #define AN_UF_PAGE1_BAM_50G_KR2_OFFSET 0x8 375 376 #define AN_UF_PAGE1_BAM_50G_CR2_MASK 0x1 377 #define AN_UF_PAGE1_BAM_50G_CR2_OFFSET 0x9 378 379 #define AN_UF_PAGE1_BAM_50G_BRCM_FEC_544_CR2_KR2_MASK 0x1 380 #define AN_UF_PAGE1_BAM_50G_BRCM_FEC_544_CR2_KR2_OFFSET 0xA 381 382 #define AN_UF_PAGE1_BAM_50G_BRCM_NO_FEC_CR1_KR1_MASK 0x1 383 #define AN_UF_PAGE1_BAM_50G_BRCM_NO_FEC_CR1_KR1_OFFSET 0xD 384 385 #define AN_UF_PAGE1_BAM_50G_BRCM_FEC_528_CR1_KR1_MASK 0x1 386 #define AN_UF_PAGE1_BAM_50G_BRCM_FEC_528_CR1_KR1_OFFSET 0xE 387 388 #define AN_UF_PAGE2_BAM_200G_BRCM_NO_FEC_KR4_CR4_MASK 0x1 389 #define AN_UF_PAGE2_BAM_200G_BRCM_NO_FEC_KR4_CR4_OFFSET 0x3 390 391 #define AN_UF_PAGE2_BAM_200G_BRCM_KR4_CR4_MASK 0x1 392 #define AN_UF_PAGE2_BAM_200G_BRCM_KR4_CR4_OFFSET 0x4 393 394 #define AN_UF_PAGE2_BAM_100G_BRCM_KR4_CR4_MASK 0x1 395 #define AN_UF_PAGE2_BAM_100G_BRCM_KR4_CR4_OFFSET 0x5 396 397 #define AN_UF_PAGE2_BAM_100G_BRCM_FEC_528_KR2_CR2_MASK 0x1 398 #define AN_UF_PAGE2_BAM_100G_BRCM_FEC_528_KR2_CR2_OFFSET 0x7 399 400 #define AN_UF_PAGE2_BAM_CL91_REQ_MASK 0x1 401 #define AN_UF_PAGE2_BAM_CL91_REQ_OFFSET 0xB 402 403 #define AN_UF_PAGE2_BAM_CL74_REQ_MASK 0x1 404 #define AN_UF_PAGE2_BAM_CL74_REQ_OFFSET 0xC 405 406 #define AN_UF_PAGE2_BAM_100G_BRCM_NO_FEC_KR2_CR2_MASK 0x1 407 #define AN_UF_PAGE2_BAM_100G_BRCM_NO_FEC_KR2_CR2_OFFSET 0xD 408 409 #define AN_UF_PAGE2_BAM_100G_BRCM_NO_FEC_X4_MASK 0x1 410 #define AN_UF_PAGE2_BAM_100G_BRCM_NO_FEC_X4_OFFSET 0xE 411 412 /* Unformatted Page for MSA only*/ 413 #define AN_UF_PAGE1_MSA_25G_KR1_ABILITY_MASK 0x1 414 #define AN_UF_PAGE1_MSA_25G_KR1_ABILITY_OFFSET 0x4 415 416 #define AN_UF_PAGE1_MSA_25G_CR1_ABILITY_MASK 0x1 417 #define AN_UF_PAGE1_MSA_25G_CR1_ABILITY_OFFSET 0x5 418 419 #define AN_UF_PAGE1_MSA_50G_KR2_ABILITY_MASK 0x1 420 #define AN_UF_PAGE1_MSA_50G_KR2_ABILITY_OFFSET 0x8 421 422 #define AN_UF_PAGE1_MSA_50G_CR2_ABILITY_MASK 0x1 423 #define AN_UF_PAGE1_MSA_50G_CR2_ABILITY_OFFSET 0x9 424 425 #define AN_UF_PAGE2_MSA_CL91_SUPPORT_MASK 0x1 426 #define AN_UF_PAGE2_MSA_CL91_SUPPORT_OFFSET 0x8 427 428 #define AN_UF_PAGE2_MSA_CL74_SUPPORT_MASK 0x1 429 #define AN_UF_PAGE2_MSA_CL74_SUPPORT_OFFSET 0x9 430 431 #define AN_UF_PAGE2_MSA_CL91_REQ_MASK 0x1 432 #define AN_UF_PAGE2_MSA_CL91_REQ_OFFSET 0xA 433 434 #define AN_UF_PAGE2_MSA_CL74_REQ_MASK 0x1 435 #define AN_UF_PAGE2_MSA_CL74_REQ_OFFSET 0xB 436 437 #ifdef _DV_TB_ 438 extern int phymod_debug_check(uint32_t flags, tbhmod_st *pc); 439 #endif 440 /*extern int configure_st_entry(int st_entry_num, int st_entry_speed, tbhmod_st* pc); */ 441 extern int tbhmod_pmd_reset_seq(PHYMOD_ST* pc, int pmd_touched); /* PMD_RESET_SEQ */ 442 extern int tbhmod_pmd_x4_reset(PHYMOD_ST* pc); 443 extern int tbhmod_update_port_mode_select(PHYMOD_ST* pc,tbhmod_port_type_t port_type); 444 extern int tbhmod_tx_lane_control_get(PHYMOD_ST* pc, int *reset, int *enable); 445 extern int tbhmod_get_pcs_latched_link_status(PHYMOD_ST* pc, uint32_t *link); 446 447 448 /* extern int tbhmod_clause72_control(tbhmod_st* pc, int per_lane_control); */ 449 /*extern int tbhmod_FEC_control(tbhmod_st* pc, int fec_en, int fec_dis, int cl74or91); 450 */ 451 extern int tbhmod_power_control(PHYMOD_ST* pc, int tx, int rx); 452 extern int tbhmod_disable_pcs_blackhawk(PHYMOD_ST* pc); 453 extern int tbhmod_pmd_reset_remove(PHYMOD_ST *dv_st, int pmd_touched); 454 extern int tbhmod_set_sc_speed(PHYMOD_ST* pc,int mapped_speed, int set_sw_speed_change); 455 456 extern int tbhmod_get_mapped_speed(tbhmod_spd_intfc_type_t spd_intf, int *speed); 457 extern int tbhmod_get_mapped_speed_7nm(tbhmod_spd_intfc_type_t spd_intf, int *speed); 458 459 #ifdef _DV_TB_ 460 /*extern int tbhmod_autoneg_set(tbhmod_st* pc); */ 461 extern int tbhmod_sw_autoneg_set(PHYMOD_ST* pc, sw_autoneg_st* an_st); 462 extern int tbhmod_autoneg_set(PHYMOD_ST* pc, autoneg_set_st* an_st); 463 extern int tbhmod_autoneg_get(tbhmod_st* pc); 464 extern int tbhmod_autoneg_control(PHYMOD_ST* pc, autoneg_control_st* an_st); 465 extern int tbhmod_set_spd_intf(tbhmod_st* pc); 466 extern int tbhmod_set_an_port_mode(PHYMOD_ST* pc); 467 #endif /* _DV_TB_ */ 468 extern int tbhmod_set_an_port_mode(PHYMOD_ST* pc, int starting_lane); 469 470 471 extern int tbhmod_autoneg_ability_set(PHYMOD_ST* pc, const phymod_autoneg_advert_abilities_t* autoneg_abilities); 472 extern int tbhmod_autoneg_ability_get(PHYMOD_ST* pc, phymod_autoneg_advert_abilities_t* autoneg_abilities); 473 extern int tbhmod_autoneg_remote_ability_get(PHYMOD_ST* pc, phymod_autoneg_advert_abilities_t *autoneg_abilities); 474 extern int tbhmod_autoneg_control(PHYMOD_ST* pc, tbhmod_an_control_t *an_control); 475 extern int tbhmod_autoneg_control_get(PHYMOD_ST* pc, tbhmod_an_control_t *an_control, int *an_complete); 476 extern int tbhmod_autoneg_status_get(PHYMOD_ST* pc, int *an_en, int *an_done); 477 extern int tbhmod_set_an_timers(PHYMOD_ST* pc, phymod_ref_clk_t refclk, uint32_t *pam4_an_timer_value); /* SET_AN_TIMERS */ 478 479 #ifdef DV_AN_SUPPORT 480 #ifdef _SDK_TBHMOD_ 481 extern int tbhmod_set_spd_intf(tbhmod_st *pc, tbhmod_spd_intfc_type_t spd_intf); 482 extern int tbhmod_autoneg_set_init(tbhmod_st* pc, tbhmod_an_init_t *an_init_st); 483 extern int tbhmod_autoneg_timer_init(tbhmod_st* pc); 484 extern int tbhmod_diag(tbhmod_st *ws, tbhmod_diag_type_t diag_type); 485 extern int tbhmod_port_enable_set(tbhmod_st *pc, int enable); 486 extern int tbhmod_tx_squelch_set(tbhmod_st *pc, int enable); 487 extern int tbhmod_rx_squelch_set(tbhmod_st *pc, int enable); 488 extern int tbhmod_rx_squelch_get(tbhmod_st *pc, int *enable); 489 #endif /* _SDK_TBHMOD_ */ 490 #endif /* DV_AN_SUPPORT */ 491 492 extern int tbhmod_speed_id_get(PHYMOD_ST* pc, int *speed_id); 493 extern int tbhmod_enable_get(PHYMOD_ST* pc, uint32_t* enable); 494 extern int tbhmod_disable_set(PHYMOD_ST* pc); 495 extern int tbhmod_enable_set(PHYMOD_ST* pc); 496 extern int tbhmod_rx_lane_control_get(PHYMOD_ST* pc, int *enable); 497 extern int tbhmod_update_port_mode( PHYMOD_ST *pc); 498 499 extern int tbhmod_tx_lane_control( PHYMOD_ST* pc, int en, tbhmod_tx_disable_enum_t dis); 500 extern int tbhmod_rx_lane_control(PHYMOD_ST* pc, int per_lane_control); 501 502 extern int tbhmod_pcs_rx_lane_swap(PHYMOD_ST* pc, int rx_lane_swap); 503 extern int tbhmod_pcs_tx_lane_swap(PHYMOD_ST* pc, int tx_lane_swap); 504 505 extern int tbhmod_fec_bypass_indication_set(PHYMOD_ST *pc, uint32_t rsfec_bypass_indication); 506 extern int tbhmod_fec_bypass_indication_get(PHYMOD_ST *pc, uint32_t *rsfec_bypass_indication); 507 extern int tbhmod_rsfec_cw_type(PHYMOD_ST* pc,int en,int fec_bypass_correction); 508 509 extern int tbhmod_low_latency_mode_en(PHYMOD_ST* pc,int low_latency_mode_en); 510 extern int tbhmod_cl74_control_fec_0(PHYMOD_ST* pc, int cl74_good_parity_cnt, int cl74_invalid_parity_cnt, int cl74_dec_max_pm, int cl74_burst_err_status_mode, int cl74_dbg_err_mode); 511 extern int tbhmod_cl74_control_fec_1(PHYMOD_ST* pc,int cl74_dec_pm_mode, int cl74_dec_19b_burst_gap_count, int cl74_dec_18b_burst_gap_count, int cl74_dec_17b_burst_gap_count, int cl74_dec_gap_count_mode); 512 extern int tbhmod_cl74_control_fec_2(PHYMOD_ST* pc, int cl74_fec_err_enable_per_stream_mpp0, int cl74_dbg_enable_per_stream_mpp0, int cl74_fec_error_code_all_per_stream_mpp0, int cl74_fec_err_enable_per_stream_mpp1, int cl74_dbg_enable_per_stream_mpp1, int cl74_fec_error_code_all_per_stream_mpp1, tbhmod_port_type_t port_type); 513 extern int tbhmod_pcs_rx_scramble_idle_en(PHYMOD_ST* pc, int en); 514 /* 1588 APIs */ 515 extern int tbhmod_osts_pipeline(PHYMOD_ST* pc,uint32_t en); 516 extern int tbhmod_osts_pipeline_get(PHYMOD_ST* pc,uint32_t* en); 517 extern int tbhmod_pcs_rx_ts_en(PHYMOD_ST* pc, uint32_t en, int sfd); 518 extern int tbhmod_pcs_rx_ts_en_get(PHYMOD_ST* pc, uint32_t* en); 519 extern int tbhmod_pcs_set_1588_ui (PHYMOD_ST* pc, uint32_t vco, uint32_t vco1, int os_mode, int clk4sync_div, int pam4); 520 extern int tbhmod_1588_pmd_latency (PHYMOD_ST* pc, uint32_t vco, int os_mode, int pam4); 521 extern int tbhmod_pcs_rx_deskew_en(PHYMOD_ST* pc, int en); 522 extern int tbhmod_pcs_set_1588_xgmii (PHYMOD_ST* pc, int sfd, uint32_t vco, int os_mode); 523 extern int tbhmod_pcs_ts_deskew_valid(PHYMOD_ST* pc, int bit_mux_mode, int *rx_ts_deskew_valid); 524 extern int tbhmod_pcs_mod_rx_1588_tbl_val(PHYMOD_ST* pc, int bit_mux_mode, uint32_t vco, int os_mode, int pam4, int tbl_ln, uint32_t *table); 525 526 extern int tbhmod_pack_spd_id_tbl_entry (spd_id_tbl_entry_t *entry, uint32_t *packed_entry); 527 extern int tbhmod_unpack_spd_id_tbl_entry (uint32_t *packed_entry, spd_id_tbl_entry_t *entry); 528 extern int tbhmod_pack_am_tbl_entry (am_tbl_entry_t *entry, uint32_t *packed_entry); 529 extern int tbhmod_unpack_am_tbl_entry (uint32_t *packed_entry, am_tbl_entry_t *entry); 530 extern int tbhmod_pack_um_tbl_entry (um_tbl_entry_t *entry, uint32_t *packed_entry); 531 extern int tbhmod_unpack_um_tbl_entry (uint32_t *packed_entry, um_tbl_entry_t *entry); 532 extern int tbhmod_rx_lock_ovrd(PHYMOD_ST* pc, uint16_t ovrd); 533 extern int tbhmod_rx_sigdet_ovrd(PHYMOD_ST* pc, uint16_t ovrd); 534 extern int tbhmod_tx_lane_disable (PHYMOD_ST* pc, uint16_t ovrr, uint16_t value); 535 extern int tbhmod_pcs_set_ilkn_wm(PHYMOD_ST* pc,int ilkn_wm); 536 extern int tbhmod_init_pcs_ilkn(PHYMOD_ST* pc); 537 extern int tbhmod_plldiv_lkup_get(PHYMOD_ST* pc, int mapped_speed_id, tbhmod_refclk_t refclk, uint32_t *plldiv); 538 extern int tbhmod_pcs_ilkn_chk(PHYMOD_ST* pc, int *ilkn_set); 539 extern int tbhmod_refclk_set(PHYMOD_ST* pc, tbhmod_refclk_t ref_clk); 540 extern int tbhmod_refclk_get(PHYMOD_ST* pc, tbhmod_refclk_t* ref_clk); 541 extern int tbhmod_pmd_osmode_set(PHYMOD_ST* pc, int mapped_speed_id, tbhmod_refclk_t refclk); 542 extern int tbhmod_fec_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count); 543 extern int tbhmod_fec_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count); 544 extern int tbhmod_autoneg_fec_status_get(PHYMOD_ST* pc, uint8_t *fec_status); 545 extern int tbhmod_pcs_ilkn_enable(PHYMOD_ST* pc, int enable); 546 547 extern int tbhmod_synce_mode_set(PHYMOD_ST* pc, int stage0_mode, int stage1_mode); 548 extern int tbhmod_synce_mode_get(PHYMOD_ST* pc, int* stage0_mode, int* stage1_mode); 549 extern int tbhmod_synce_clk_ctrl_set(PHYMOD_ST* pc, uint32_t val); 550 extern int tbhmod_synce_clk_ctrl_get(PHYMOD_ST* pc, uint32_t* val); 551 extern int tbhmod_pmd_rx_lock_override_enable(PHYMOD_ST* pc, uint32_t enable); 552 extern int tbhmod_polling_for_sc_done(PHYMOD_ST* pc); 553 extern int tbhmod_read_sc_fsm_status(PHYMOD_ST* pc); 554 extern int tbhmod_read_sc_done(PHYMOD_ST* pc); 555 extern int tbhmod_resolved_port_mode_get(PHYMOD_ST* pc, uint32_t* port_mode); 556 extern int tbhmod_intr_status_get(PHYMOD_ST* pc, tbhmod_intr_status_t* intr_status); 557 extern int tbhmod_1588_tx_info_get(PHYMOD_ST * pc, tbhmod_ts_tx_info_t * ts_tx_info); 558 extern int tbhmod_revid_get(PHYMOD_ST* pc, uint32_t* rev_id); 559 extern int tbhmod_pcs_single_rx_lane_swap_set(PHYMOD_ST* pc, int rx_physical_lane, int rx_logical_lane); 560 extern int tbhmod_pcs_single_tx_lane_swap_set(PHYMOD_ST* pc, int tx_physical_lane, int tx_logical_lane); 561 extern int tbhmod_pmd_override_enable_set(PHYMOD_ST* phy, 562 phymod_override_type_t pmd_override_type, 563 uint32_t override_enable, 564 uint32_t override_val); 565 extern int tbhmod_400g_autoneg_timer_disable(PHYMOD_ST* pc, int timer_disable); 566 extern int tbhmod_fec_arch_decode_get(int fec_arch, phymod_fec_type_t* fec_type); 567 extern int tbhmod_vco_to_pll_lkup(uint32_t vco, tbhmod_refclk_t refclk, uint32_t* pll_div); 568 extern int tbhmod_pll_to_vco_get(tbhmod_refclk_t ref_clock, uint32_t pll, uint32_t* vco); 569 /* This API will take in a logical port's lane_map, 570 * return the symbol error count for each physical lane via array sum */ 571 extern int tbhmod_rsfec_symbol_error_counter_get(PHYMOD_ST* pc, 572 int bit_mux_mode, 573 int max_count, 574 int* actual_count, 575 uint32_t* symb_err_cnt); 576 #ifdef FIXME 577 extern int print_tbhmod_st(tbhmod_st* pc); 578 #endif 579 580 #endif /* _tbhmod_H_ */ 581