commit 0ed2a2fa1e7a256248a807024896578344213ed6
parent 5681683868cde4c1e73d29ea3a7e355bf79a3610
Author: Broadcom SDK Release <sdk.releases@broadcom.com>
Date: Wed, 18 Nov 2020 16:05:49 -0800
SDK-237420: CPU queue map changes for arm cores (TH3 MOD on core-1) fixes sub...
Devices: 56870_B0,56980_A0
Module: MoD
CPU queue map changes for arm cores (TH3 MOD on core-1) fixes submitted
for MOD.
Diffstat:
4 files changed, 281 insertions(+), 133 deletions(-)
diff --git a/sdk-6.5.16/src/bcm/esw/tomahawk/field_presel.c b/sdk-6.5.16/src/bcm/esw/tomahawk/field_presel.c
@@ -5990,65 +5990,127 @@ _bcm_field_th_qualify_MixedSrcClassId(int unit,
}
BCM_IF_ERROR_RETURN(_field_stage_control_get(unit, stage_id, &stage_fc));
-
switch (stage_fc->field_src_class_mode[pipe_idx]) {
case bcmFieldSrcClassModeDefault:
- hw_data = ((((data.src_class_field & 0x3) << 10 ) |
- (data.dst_class_field & 0x3FF)) << 20) |
- ((data.udf_class & 0xFF) << 12) |
- ((data.intf_class_port & 0xFF) << 4) |
- (data.intf_class_l2 & 0xF);
-
- hw_mask = ((((mask.src_class_field & 0x3) << 10 ) |
- (mask.dst_class_field & 0x3FF)) << 20) |
- ((mask.udf_class & 0xFF) << 12) |
- ((mask.intf_class_port & 0xFF) << 4) |
- (mask.intf_class_l2 & 0xF);
+ if (soc_feature(unit, soc_feature_th3_style_fp)) {
+ hw_data = (uint32)((uint32)((data.intf_class_l2 & 0xF) << 28))
+ | ((data.src_class_field & 0x3) << 26)
+ | ((data.dst_class_field & 0x3FF) << 16)
+ | ((data.udf_class & 0xFF) << 8)
+ | (data.intf_class_port & 0xFF);
+
+ hw_mask = (uint32)((uint32)((mask.intf_class_l2 & 0xF) << 28))
+ | ((mask.src_class_field & 0x3) << 26)
+ | ((mask.dst_class_field & 0x3FF) << 16)
+ | ((mask.udf_class & 0xFF) << 8)
+ | (mask.intf_class_port & 0xFF);
+ } else {
+ hw_data = (uint32)((uint32)(
+ (data.src_class_field & 0x3) << 30))
+ | ((data.dst_class_field & 0x3FF) << 20)
+ | ((data.udf_class & 0xFF) << 12)
+ | ((data.intf_class_port & 0xFF) << 4)
+ | (data.intf_class_l2 & 0xF);
+
+ hw_mask = (uint32)((uint32)(
+ (mask.src_class_field & 0x3) << 30 ))
+ | ((mask.dst_class_field & 0x3FF) << 20)
+ | ((mask.udf_class & 0xFF) << 12)
+ | ((mask.intf_class_port & 0xFF) << 4)
+ | (mask.intf_class_l2 & 0xF);
+ }
break;
case bcmFieldSrcClassModeSDN:
- hw_data = ((((data.src_class_field & 0x3) << 10 ) |
- (data.dst_class_field & 0x3FF)) << 20) |
- ((data.udf_class & 0xF) << 16) |
- ((data.intf_class_port & 0xF) << 12) |
- ((data.intf_class_l2 & 0xF) << 8) |
- ((data.intf_class_vport & 0xF) << 4) |
- (data.intf_class_l3 & 0xF);
-
- hw_mask = ((((mask.src_class_field & 0x3) << 10 ) |
- (mask.dst_class_field & 0x3FF)) << 20) |
- ((mask.udf_class & 0xF) << 16) |
- ((mask.intf_class_port & 0xF) << 12) |
- ((mask.intf_class_l2 & 0xF) << 8) |
- ((mask.intf_class_vport & 0xF) << 4) |
- (mask.intf_class_l3 & 0xF);
+ if (soc_feature(unit, soc_feature_th3_style_fp)) {
+ hw_data = (uint32)((uint32)((data.intf_class_l2 & 0xF) << 28))
+ | ((data.src_class_field & 0x3) << 26)
+ | ((data.dst_class_field & 0x3FF) << 16)
+ | ((data.udf_class & 0xF) << 12)
+ | ((data.intf_class_port & 0xF) << 4)
+ | (data.intf_class_l3 & 0xF);
+
+ hw_mask = (uint32)((uint32)((mask.intf_class_l2 & 0xF) << 28))
+ | ((mask.src_class_field & 0x3) << 26)
+ | ((mask.dst_class_field & 0x3FF) << 16)
+ | ((mask.udf_class & 0xF) << 12)
+ | ((mask.intf_class_port & 0xF) << 4)
+ | (mask.intf_class_l3 & 0xF);
+ } else {
+ hw_data = (uint32)((uint32)(
+ (data.src_class_field & 0x3) << 30))
+ | ((data.dst_class_field & 0x3FF) << 20)
+ | ((data.udf_class & 0xF) << 16)
+ | ((data.intf_class_port & 0xF) << 12)
+ | ((data.intf_class_l2 & 0xF) << 8)
+ | ((data.intf_class_vport & 0xF) << 4)
+ | (data.intf_class_l3 & 0xF);
+
+ hw_mask = (uint32)((uint32)(
+ (mask.src_class_field & 0x3) << 30))
+ | ((mask.dst_class_field & 0x3FF) << 20)
+ | ((mask.udf_class & 0xF) << 16)
+ | ((mask.intf_class_port & 0xF) << 12)
+ | ((mask.intf_class_l2 & 0xF) << 8)
+ | ((mask.intf_class_vport & 0xF) << 4)
+ | (mask.intf_class_l3 & 0xF);
+ }
break;
case bcmFieldSrcClassModeBalanced:
- hw_data = ((data.dst_class_field & 0xFF) << 24) |
- ((data.udf_class & 0xF) << 20) |
- ((data.intf_class_port & 0xFF) << 12) |
- ((data.intf_class_l2 & 0xF) << 8) |
- ((data.intf_class_vport & 0xF) << 4) |
- (data.intf_class_l3 & 0xF);
-
- hw_mask = ((mask.dst_class_field & 0xFF) << 24) |
- ((mask.udf_class & 0xF) << 20) |
- ((mask.intf_class_port & 0xFF) << 12) |
- ((mask.intf_class_l2 & 0xF) << 8) |
- ((mask.intf_class_vport & 0xF) << 4) |
- (mask.intf_class_l3 & 0xF);
+ if (soc_feature(unit, soc_feature_th3_style_fp)) {
+ hw_data = (uint32)((uint32)((data.intf_class_l2 & 0xF) << 28))
+ | ((data.dst_class_field & 0xFF) << 20)
+ | ((data.udf_class & 0xF) << 16)
+ | ((data.intf_class_port & 0xFF) << 4)
+ | (data.intf_class_l3 & 0xF);
+ hw_mask = (uint32)((uint32)((mask.intf_class_l2 & 0xF) << 28))
+ | ((mask.dst_class_field & 0xFF) << 20)
+ | ((mask.udf_class & 0xF) << 16)
+ | ((mask.intf_class_port & 0xFF) << 4)
+ | (mask.intf_class_l3 & 0xF);
+ } else {
+ hw_data = (uint32)((uint32)(
+ (data.dst_class_field & 0xFF) << 24))
+ | ((data.udf_class & 0xF) << 20)
+ | ((data.intf_class_port & 0xFF) << 12)
+ | ((data.intf_class_l2 & 0xF) << 8)
+ | ((data.intf_class_vport & 0xF) << 4)
+ | (data.intf_class_l3 & 0xF);
+
+ hw_mask = (uint32)((uint32)(
+ (mask.dst_class_field & 0xFF) << 24))
+ | ((mask.udf_class & 0xF) << 20)
+ | ((mask.intf_class_port & 0xFF) << 12)
+ | ((mask.intf_class_l2 & 0xF) << 8)
+ | ((mask.intf_class_vport & 0xF) << 4)
+ | (mask.intf_class_l3 & 0xF);
+ }
break;
case bcmFieldSrcClassModeOverlayNetworks:
- hw_data = ((data.dst_class_field & 0xF) << 28) |
- ((data.intf_class_port & 0xF) << 24) |
- ((data.intf_class_l2 & 0xFF) << 16) |
- ((data.intf_class_vport & 0xFF) << 8) |
- (data.intf_class_l3 & 0xFF);
-
- hw_mask = ((mask.dst_class_field & 0xF) << 28) |
- ((mask.intf_class_port & 0xF) << 24) |
- ((mask.intf_class_l2 & 0xFF) << 16) |
- ((mask.intf_class_vport & 0xFF) << 8) |
- (mask.intf_class_l3 & 0xFF);
+ if (soc_feature(unit, soc_feature_th3_style_fp)) {
+ hw_data = (uint32)((uint32)((data.intf_class_l2 & 0xFF) << 24))
+ | ((data.dst_class_field & 0xF) << 20)
+ | ((data.intf_class_port & 0xF) << 8)
+ | (data.intf_class_l3 & 0xFF);
+
+ hw_mask = (uint32)((uint32)((mask.intf_class_l2 & 0xFF) << 24))
+ | ((mask.dst_class_field & 0xF) << 20)
+ | ((mask.intf_class_port & 0xF) << 8)
+ | (mask.intf_class_l3 & 0xFF);
+ } else {
+ hw_data = (uint32)((uint32)(
+ (data.dst_class_field & 0xF) << 28))
+ | ((data.intf_class_port & 0xF) << 24)
+ | ((data.intf_class_l2 & 0xFF) << 16)
+ | ((data.intf_class_vport & 0xFF) << 8)
+ | (data.intf_class_l3 & 0xFF);
+
+ hw_mask = (uint32)((uint32)(
+ (mask.dst_class_field & 0xF) << 28))
+ | ((mask.intf_class_port & 0xF) << 24)
+ | ((mask.intf_class_l2 & 0xFF) << 16)
+ | ((mask.intf_class_vport & 0xFF) << 8)
+ | (mask.intf_class_l3 & 0xFF);
+ }
break;
default:
return (BCM_E_PARAM);
@@ -6177,62 +6239,118 @@ _bcm_field_th_qualify_MixedSrcClassId_get(int unit,
switch (stage_fc->field_src_class_mode[pipe_idx]) {
case bcmFieldSrcClassModeDefault:
- data->src_class_field = (hw_data >> 30) & 0x3;
- data->dst_class_field = (hw_data >> 20) & 0x3FF;
- data->udf_class = (hw_data >> 12) & 0xFF;
- data->intf_class_port = (hw_data >> 4) & 0xFF;
- data->intf_class_l2 = hw_data & 0xF;
-
- mask->src_class_field = (hw_mask >> 30) & 0x3;
- mask->dst_class_field = (hw_mask >> 20) & 0x3FF;
- mask->udf_class = (hw_mask >> 12) & 0xFF;
- mask->intf_class_port = (hw_mask >> 4) & 0xFF;
- mask->intf_class_l2 = hw_mask & 0xF;
+ if (soc_feature(unit, soc_feature_th3_style_fp)) {
+ data->intf_class_l2 = (hw_data >> 28) & 0xF;
+ data->src_class_field = (hw_data >> 26) & 0x3;
+ data->dst_class_field = (hw_data >> 16) & 0x3FF;
+ data->udf_class = (hw_data >> 8) & 0xFF;
+ data->intf_class_port = hw_data & 0xFF;
+
+ mask->intf_class_l2 = (hw_mask >> 28) & 0xF;
+ mask->src_class_field = (hw_mask >> 26) & 0x3;
+ mask->dst_class_field = (hw_mask >> 16) & 0x3FF;
+ mask->udf_class = (hw_mask >> 8) & 0xFF;
+ mask->intf_class_port = hw_mask & 0xFF;
+ } else {
+ data->src_class_field = (hw_data >> 30) & 0x3;
+ data->dst_class_field = (hw_data >> 20) & 0x3FF;
+ data->udf_class = (hw_data >> 12) & 0xFF;
+ data->intf_class_port = (hw_data >> 4) & 0xFF;
+ data->intf_class_l2 = hw_data & 0xF;
+
+ mask->src_class_field = (hw_mask >> 30) & 0x3;
+ mask->dst_class_field = (hw_mask >> 20) & 0x3FF;
+ mask->udf_class = (hw_mask >> 12) & 0xFF;
+ mask->intf_class_port = (hw_mask >> 4) & 0xFF;
+ mask->intf_class_l2 = hw_mask & 0xF;
+ }
break;
case bcmFieldSrcClassModeSDN:
- data->src_class_field = (hw_data >> 30) & 0x3;
- data->dst_class_field = (hw_data >> 20) & 0x3FF;
- data->udf_class = (hw_data >> 16) & 0xF;
- data->intf_class_port = (hw_data >> 12) & 0xF;
- data->intf_class_l2 = (hw_data >> 8) & 0xF;
- data->intf_class_vport = (hw_data >> 4) & 0xF;
- data->intf_class_l3 = hw_data & 0xF;
-
- mask->src_class_field = (hw_mask >> 30) & 0x3;
- mask->dst_class_field = (hw_mask >> 20) & 0x3FF;
- mask->udf_class = (hw_mask >> 16) & 0xF;
- mask->intf_class_port = (hw_mask >> 12) & 0xF;
- mask->intf_class_l2 = (hw_mask >> 8) & 0xF;
- mask->intf_class_vport = (hw_mask >> 4) & 0xF;
- mask->intf_class_l3 = hw_mask & 0xF;
+ if (soc_feature(unit, soc_feature_th3_style_fp)) {
+ data->intf_class_l2 = (hw_data >> 28) & 0xF;
+ data->src_class_field = (hw_data >> 26) & 0x3;
+ data->dst_class_field = (hw_data >> 16) & 0x3FF;
+ data->udf_class = (hw_data >> 12) & 0xF;
+ data->intf_class_port = (hw_data >> 4) & 0xF;
+ data->intf_class_l3 = hw_data & 0xF;
+
+ mask->intf_class_l2 = (hw_mask >> 28) & 0xF;
+ mask->src_class_field = (hw_mask >> 26) & 0x3;
+ mask->dst_class_field = (hw_mask >> 16) & 0x3FF;
+ mask->udf_class = (hw_mask >> 12) & 0xF;
+ mask->intf_class_port = (hw_mask >> 4) & 0xF;
+ mask->intf_class_l3 = hw_mask & 0xF;
+ } else {
+ data->src_class_field = (hw_data >> 30) & 0x3;
+ data->dst_class_field = (hw_data >> 20) & 0x3FF;
+ data->udf_class = (hw_data >> 16) & 0xF;
+ data->intf_class_port = (hw_data >> 12) & 0xF;
+ data->intf_class_l2 = (hw_data >> 8) & 0xF;
+ data->intf_class_vport = (hw_data >> 4) & 0xF;
+ data->intf_class_l3 = hw_data & 0xF;
+
+ mask->src_class_field = (hw_mask >> 30) & 0x3;
+ mask->dst_class_field = (hw_mask >> 20) & 0x3FF;
+ mask->udf_class = (hw_mask >> 16) & 0xF;
+ mask->intf_class_port = (hw_mask >> 12) & 0xF;
+ mask->intf_class_l2 = (hw_mask >> 8) & 0xF;
+ mask->intf_class_vport = (hw_mask >> 4) & 0xF;
+ mask->intf_class_l3 = hw_mask & 0xF;
+ }
break;
case bcmFieldSrcClassModeBalanced:
- data->dst_class_field = (hw_data >> 24) & 0xFF;
- data->udf_class = (hw_data >> 20) & 0xF;
- data->intf_class_port = (hw_data >> 12) & 0xFF;
- data->intf_class_l2 = (hw_data >> 8) & 0xF;
- data->intf_class_vport = (hw_data >> 4) & 0xF;
- data->intf_class_l3 = hw_data & 0xF;
-
- mask->dst_class_field = (hw_mask >> 24) & 0xFF;
- mask->udf_class = (hw_mask >> 20) & 0xF;
- mask->intf_class_port = (hw_mask >> 12) & 0xFF;
- mask->intf_class_l2 = (hw_mask >> 8) & 0xF;
- mask->intf_class_vport = (hw_mask >> 4) & 0xF;
- mask->intf_class_l3 = hw_mask & 0xF;
+ if (soc_feature(unit, soc_feature_th3_style_fp)) {
+ data->intf_class_l2 = (hw_data >> 28) & 0xF;
+ data->dst_class_field = (hw_data >> 20) & 0xFF;
+ data->udf_class = (hw_data >> 16) & 0xF;
+ data->intf_class_port = (hw_data >> 4) & 0xFF;
+ data->intf_class_l3 = hw_data & 0xF;
+
+ mask->intf_class_l2 = (hw_mask >> 28) & 0xF;
+ mask->dst_class_field = (hw_mask >> 20) & 0xFF;
+ mask->udf_class = (hw_mask >> 16) & 0xF;
+ mask->intf_class_port = (hw_mask >> 4) & 0xFF;
+ mask->intf_class_l3 = hw_mask & 0xF;
+ } else {
+ data->dst_class_field = (hw_data >> 24) & 0xFF;
+ data->udf_class = (hw_data >> 20) & 0xF;
+ data->intf_class_port = (hw_data >> 12) & 0xFF;
+ data->intf_class_l2 = (hw_data >> 8) & 0xF;
+ data->intf_class_vport = (hw_data >> 4) & 0xF;
+ data->intf_class_l3 = hw_data & 0xF;
+
+ mask->dst_class_field = (hw_mask >> 24) & 0xFF;
+ mask->udf_class = (hw_mask >> 20) & 0xF;
+ mask->intf_class_port = (hw_mask >> 12) & 0xFF;
+ mask->intf_class_l2 = (hw_mask >> 8) & 0xF;
+ mask->intf_class_vport = (hw_mask >> 4) & 0xF;
+ mask->intf_class_l3 = hw_mask & 0xF;
+ }
break;
case bcmFieldSrcClassModeOverlayNetworks:
- data->dst_class_field = (hw_data >> 28) & 0xF;
- data->intf_class_port = (hw_data >> 24) & 0xF;
- data->intf_class_l2 = (hw_data >> 16) & 0xFF;
- data->intf_class_vport = (hw_data >> 8) & 0xFF;
- data->intf_class_l3 = hw_data & 0xFF;
-
- mask->dst_class_field = (hw_mask >> 28) & 0xF;
- mask->intf_class_port = (hw_mask >> 24) & 0xF;
- mask->intf_class_l2 = (hw_mask >> 16) & 0xFF;
- mask->intf_class_vport = (hw_mask >> 8) & 0xFF;
- mask->intf_class_l3 = hw_mask & 0xFF;
+ if (soc_feature(unit, soc_feature_th3_style_fp)) {
+ data->intf_class_l2 = (hw_data >> 24) & 0xFF;
+ data->dst_class_field = (hw_data >> 20) & 0xF;
+ data->intf_class_port = (hw_data >> 8) & 0xF;
+ data->intf_class_l3 = hw_data & 0xFF;
+
+ mask->intf_class_l2 = (hw_mask >> 24) & 0xFF;
+ mask->dst_class_field = (hw_mask >> 20) & 0xF;
+ mask->intf_class_port = (hw_mask >> 8) & 0xF;
+ mask->intf_class_l3 = hw_mask & 0xFF;
+ } else {
+ data->dst_class_field = (hw_data >> 28) & 0xF;
+ data->intf_class_port = (hw_data >> 24) & 0xF;
+ data->intf_class_l2 = (hw_data >> 16) & 0xFF;
+ data->intf_class_vport = (hw_data >> 8) & 0xFF;
+ data->intf_class_l3 = hw_data & 0xFF;
+
+ mask->dst_class_field = (hw_mask >> 28) & 0xF;
+ mask->intf_class_port = (hw_mask >> 24) & 0xF;
+ mask->intf_class_l2 = (hw_mask >> 16) & 0xFF;
+ mask->intf_class_vport = (hw_mask >> 8) & 0xFF;
+ mask->intf_class_l3 = hw_mask & 0xFF;
+ }
break;
default:
return (BCM_E_PARAM);
diff --git a/sdk-6.5.16/src/bcm/esw/tomahawk/flowtracker.c b/sdk-6.5.16/src/bcm/esw/tomahawk/flowtracker.c
@@ -82,6 +82,7 @@ STATIC _bcm_th_ft_template_support_mapping_t _bcm_th_ft_template_element_mapping
#ifdef BCM_WARM_BOOT_SUPPORT
STATIC int _bcm_th_ft_scache_alloc(int unit, int create);
STATIC int _bcm_th_ft_wb_recover(int unit);
+#define _BCM_FT_WB_INVALID_COLLECTOR_ID 0xFFFF
#endif /* BCM_WARM_BOOT_SUPPORT */
/* TD3 chunk index to FT qualifier mapping */
@@ -6835,7 +6836,8 @@ _bcm_th_ft_scache_v0_group_recover(int unit, uint8 **scache)
/* Collector Id */
FT_SCACHE_READ(*scache, group->collector_id, uint16);
- if (ft_info->cfg_mode >= SHR_FT_CFG_MODE_V2) {
+ if (ft_info->cfg_mode >= SHR_FT_CFG_MODE_V2 &&
+ (group->collector_id != _BCM_FT_WB_INVALID_COLLECTOR_ID)) {
BCM_IF_ERROR_RETURN(
_bcm_esw_collector_ref_count_update(unit,
group->collector_id, 1));
@@ -8078,10 +8080,13 @@ _bcm_th_ft_scache_v1_group_recover(int unit, uint8 **scache)
/* Export profile Id */
FT_SCACHE_READ(*scache, group->export_profile_id, int);
- BCM_IF_ERROR_RETURN(
- _bcm_esw_collector_export_profile_ref_count_update(unit,
+ if (group->export_profile_id !=
+ BCM_INT_COLLECTOR_INVALID_EXPORT_PROFILE_ID) {
+ BCM_IF_ERROR_RETURN(
+ _bcm_esw_collector_export_profile_ref_count_update(unit,
group->export_profile_id,
1));
+ }
if (ft_info->cfg_mode >= SHR_FT_CFG_MODE_V2) {
bcm_collector_export_profile_t_init(&export_profile_info);
@@ -8091,14 +8096,16 @@ _bcm_th_ft_scache_v1_group_recover(int unit, uint8 **scache)
group->export_profile_id,
&export_profile_info));
- if (export_profile_info.wire_format == bcmCollectorWireFormatIpfix) {
- BCM_IF_ERROR_RETURN(
- _bcm_esw_collector_user_update(unit,
- group->collector_id, _BCM_COLLECTOR_EXPORT_APP_FT_IPFIX));
- } else {
- BCM_IF_ERROR_RETURN(
- _bcm_esw_collector_user_update(unit,
- group->collector_id, _BCM_COLLECTOR_EXPORT_APP_FT_PROTOBUF));
+ if (group->collector_id != _BCM_FT_WB_INVALID_COLLECTOR_ID) {
+ if (export_profile_info.wire_format == bcmCollectorWireFormatIpfix) {
+ BCM_IF_ERROR_RETURN(
+ _bcm_esw_collector_user_update(unit,
+ group->collector_id, _BCM_COLLECTOR_EXPORT_APP_FT_IPFIX));
+ } else {
+ BCM_IF_ERROR_RETURN(
+ _bcm_esw_collector_user_update(unit,
+ group->collector_id, _BCM_COLLECTOR_EXPORT_APP_FT_PROTOBUF));
+ }
}
}
@@ -8225,6 +8232,8 @@ _bcm_th_ft_scache_v1_collector_recover(int unit, uint8 **scache)
uint8 in_use;
uint16 start_id, end_id;
int collector_id;
+ int rv = BCM_E_NONE;
+ _bcm_int_ft_info_t *ft_info = FT_INFO_GET(unit);
_bcm_int_ft_v2_collector_info_t *collector_list = ft_v2_collector_info_list[unit];
_bcm_int_ft_v2_collector_info_t *collector = NULL;
@@ -8257,6 +8266,9 @@ _bcm_th_ft_scache_v1_collector_recover(int unit, uint8 **scache)
/* Collector Internal id */
FT_SCACHE_READ(*scache, collector->int_id, int);
+ rv = shr_idxres_list_reserve(ft_info->collector_pool,
+ collector->int_id, collector->int_id);
+ BCM_IF_ERROR_RETURN(rv);
}
return BCM_E_NONE;
@@ -8345,8 +8357,10 @@ _bcm_th_ft_scache_v1_export_profile_recover(int unit, uint8 **scache)
{
int i;
uint8 in_use;
+ int rv = BCM_E_NONE;
uint16 start_id, end_id;
int export_profile_id;
+ _bcm_int_ft_info_t *ft_info = FT_INFO_GET(unit);
_bcm_int_ft_v2_export_profile_info_t *export_profile_list = ft_v2_export_profile_info_list[unit];
_bcm_int_ft_v2_export_profile_info_t *export_profile = NULL;
@@ -8379,6 +8393,9 @@ _bcm_th_ft_scache_v1_export_profile_recover(int unit, uint8 **scache)
/* Export_Profile Internal id */
FT_SCACHE_READ(*scache, export_profile->int_id, int);
+ rv = shr_idxres_list_reserve(ft_info->export_profile_pool,
+ export_profile->int_id, export_profile->int_id);
+ BCM_IF_ERROR_RETURN(rv);
}
return BCM_E_NONE;
diff --git a/sdk-6.5.16/src/bcm/tomahawk3/cosq.c b/sdk-6.5.16/src/bcm/tomahawk3/cosq.c
@@ -6072,30 +6072,22 @@ int
_bcm_th3_cosq_gport_cpu_tree_create(int unit, bcm_port_t port)
{
bcm_gport_t cpu_mc_gport[_BCM_TH3_NUM_CPU_MCAST_QUEUE];
- int id, cmc, pci_cmc = SOC_PCI_CMC(unit);
- int ch_l0_map[SOC_CMCS_NUM_MAX];
+ int id, pci_cmc = SOC_PCI_CMC(unit);
+ int ch_l0_map;
bcm_gport_t sched_gport[_BCM_TH3_NUM_SCHEDULER_PER_PORT];
int numq;
+ int num_queues_uc0 = soc_property_get(unit, "num_queues_uc0", 0);
+ int num_queues_uc1 = soc_property_get(unit, "num_queues_uc1", 0);
if (!IS_CPU_PORT(unit, port)) {
return BCM_E_PARAM;
}
-
- if (SOC_CMCS_NUM(unit) > SOC_CMCS_NUM_MAX) {
- return BCM_E_INIT;
+ /* CMIC requires all 48 queues to be set and for the respective CMC */
+ if ((NUM_CPU_ARM_COSQ(unit, pci_cmc) + num_queues_uc0 + num_queues_uc1) !=
+ SOC_TH3_NUM_CPU_QUEUES) {
+ return BCM_E_PARAM;
}
- for (cmc = 0; cmc < SOC_CMCS_NUM(unit); cmc++) {
- if (cmc == pci_cmc) {
- ch_l0_map[cmc] = 0;
- } else if (cmc == SOC_ARM_CMC(unit, 0)) {
- ch_l0_map[cmc] = 7;
- } else if (cmc == SOC_ARM_CMC(unit, 1)) {
- ch_l0_map[cmc] = 8;
- } else {
- return BCM_E_PARAM;
- }
- }
numq = 48;
/* Adding L0 (schedular) nodes and attaching them to cpu port */
@@ -6110,19 +6102,28 @@ _bcm_th3_cosq_gport_cpu_tree_create(int unit, bcm_port_t port)
"sched_gport[%d]=0x%x\n"),
id, sched_gport[id]));
}
+ /* Add MC queues and attach them to Schedular nodes.
+ * L0.0 node - PCI host
+ * L0.7 node - uc0
+ * L0.8 node - uc1
+ */
+
+ /* CMICX supports only 2 CMCs.
+ * CMC0 connected to PCI.
+ * CMC1 is connected to other arm cores.
+ */
for (id = 0; id < _BCM_TH3_NUM_CPU_MCAST_QUEUE; id++) {
- cmc = (id < NUM_CPU_ARM_COSQ(unit, pci_cmc)) ? pci_cmc :
- (id < (NUM_CPU_ARM_COSQ(unit, pci_cmc) +
- NUM_CPU_ARM_COSQ(unit, 1))) ? SOC_ARM_CMC(unit, 0) :
- SOC_ARM_CMC(unit, 1);
+ ch_l0_map = (id < NUM_CPU_ARM_COSQ(unit, pci_cmc)) ? pci_cmc :
+ (id < (NUM_CPU_ARM_COSQ(unit, pci_cmc) +
+ (num_queues_uc0))) ? 7 : 8;
BCM_IF_ERROR_RETURN
(bcm_th3_cosq_gport_add(unit, 0, 1,
BCM_COSQ_GPORT_MCAST_QUEUE_GROUP,
&cpu_mc_gport[id]));
BCM_IF_ERROR_RETURN
(bcm_th3_cosq_gport_attach(unit, cpu_mc_gport[id],
- sched_gport[ch_l0_map[cmc]], id));
+ sched_gport[ch_l0_map], id));
}
diff --git a/sdk-6.5.16/src/soc/esw/drv.c b/sdk-6.5.16/src/soc/esw/drv.c
@@ -11338,7 +11338,10 @@ soc_shutdown(int unit)
int cmc;
#ifdef INCLUDE_KNET
uint8 shutdown_knet = TRUE;
+#endif
+ int warm_boot;
+#ifdef INCLUDE_KNET
if (SOC_KNET_MODE(unit) &&
soc_property_get(unit, spn_WARMBOOT_KNET_SHUTDOWN_MODE, 0)) {
shutdown_knet = FALSE;
@@ -11431,9 +11434,18 @@ soc_shutdown(int unit)
}
#endif /* BCM_TOMAHAWK3_SUPPORT */
+ warm_boot = SOC_WARM_BOOT(unit);
+ if (!warm_boot) {
+ SOC_WARM_BOOT_START(unit);
+ }
+
/* Terminate counter module; frees allocated space */
soc_counter_detach(unit);
+ if (!warm_boot) {
+ SOC_WARM_BOOT_DONE(unit);
+ }
+
#ifdef BCM_XGS_SWITCH_SUPPORT
if (soc_property_get(unit, spn_PARITY_ENABLE, TRUE) &&
