drv.c (948129B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * StrataSwitch driver 8 */ 9 10 #include <shared/bsl.h> 11 12 #include <stddef.h> 13 #include <sal/core/libc.h> 14 #include <shared/alloc.h> 15 #include <sal/core/spl.h> 16 #include <sal/core/sync.h> 17 #include <sal/core/boot.h> 18 #include <sal/core/dpc.h> 19 #include <sal/appl/sal.h> 20 #ifdef PLISIM 21 #include <sal/appl/config.h> 22 #endif 23 24 #include <soc/drv.h> 25 #include <soc/scache.h> 26 #include <soc/scache_dictionary.h> 27 #include <soc/mcm/driver.h> /* soc_base_driver_table */ 28 #include <soc/cm.h> 29 #include <soc/mem.h> 30 #include <soc/error.h> 31 #include <soc/l2x.h> 32 #include <soc/l2u.h> 33 #include <soc/dma.h> 34 #include <soc/i2c.h> 35 #include <soc/counter.h> 36 #include <soc/hercules.h> 37 #ifdef BCM_CMICM_SUPPORT 38 #include <soc/cmicm.h> 39 #include <soc/uc_msg.h> 40 #endif 41 #ifdef BCM_CMICX_SUPPORT 42 #include <soc/intr_cmicx.h> 43 #include <soc/soc_schan_fifo.h> 44 #include <shared/cmicfw/iproc_m0ssq.h> 45 #include <shared/cmicfw/iproc_mbox.h> 46 #include <shared/cmicfw/cmicx_led.h> 47 #include <shared/cmicfw/cmicx_link.h> 48 #include <soc/soc_async.h> 49 #endif 50 #include <soc/soc_mem_bulk.h> 51 #ifdef BCM_IPROC_SUPPORT 52 #include <soc/iproc.h> 53 #endif 54 #if defined(BCM_FIREBOLT_SUPPORT) 55 #include <soc/firebolt.h> 56 #endif /* BCM_FIREBOLT_SUPPORT */ 57 #if defined(BCM_BRADLEY_SUPPORT) 58 #include <soc/bradley.h> 59 #endif /* BCM_BRADLEY_SUPPORT */ 60 #if defined(BCM_TRIUMPH_SUPPORT) 61 #include <soc/triumph.h> 62 #include <soc/er_tcam.h> 63 #endif /* BCM_TRIUMPH_SUPPORT */ 64 #if defined(BCM_ENDURO_SUPPORT) 65 #include <soc/enduro.h> 66 #endif /* BCM_ENDURO_SUPPORT */ 67 #if defined(BCM_HURRICANE_SUPPORT) 68 #include <soc/hurricane.h> 69 #endif /* BCM_HURRICANE_SUPPORT */ 70 #if defined(BCM_HURRICANE2_SUPPORT) 71 #include <soc/hurricane2.h> 72 #endif /* BCM_HURRICANE2_SUPPORT */ 73 #if defined(BCM_HURRICANE3_SUPPORT) 74 #include <soc/hurricane3.h> 75 #include <soc/wolfhound2.h> 76 #endif /* BCM_HURRICANE3_SUPPORT */ 77 #if defined(BCM_GREYHOUND_SUPPORT) 78 #include <soc/greyhound.h> 79 #endif /* BCM_GREYHOUND_SUPPORT */ 80 #if defined(BCM_GREYHOUND2_SUPPORT) 81 #include <soc/greyhound2.h> 82 #endif /* BCM_GREYHOUND2_SUPPORT */ 83 #if defined(BCM_VALKYRIE_SUPPORT) 84 #include <soc/valkyrie.h> 85 #endif /* BCM_VALKYRIE_SUPPORT */ 86 #if defined(BCM_TRIUMPH2_SUPPORT) 87 #include <soc/triumph2.h> 88 #endif /* BCM_TRIUMPH2_SUPPORT */ 89 #if defined(BCM_TRIDENT_SUPPORT) 90 #include <soc/trident.h> 91 #endif /* BCM_TRIDENT_SUPPORT */ 92 #if defined(BCM_TRIDENT2_SUPPORT) 93 #include <soc/trident2.h> 94 #endif /* BCM_TRIDENT2_SUPPORT */ 95 #if defined(BCM_MONTEREY_SUPPORT) 96 #include <soc/monterey.h> 97 #endif /* BCM_MONTEREY_SUPPORT */ 98 #if defined(BCM_APACHE_SUPPORT) 99 #include <soc/apache.h> 100 #endif /* BCM_APACHE_SUPPORT */ 101 #if defined(BCM_TRIUMPH3_SUPPORT) 102 #include <soc/triumph3.h> 103 #endif /* BCM_TRIUMPH3_SUPPORT */ 104 #if defined(BCM_HELIX4_SUPPORT) 105 #include <soc/helix4.h> 106 #endif /* BCM_HELIX4_SUPPORT */ 107 #if defined(BCM_SIRIUS_SUPPORT) 108 #include <soc/sbx/sbx_drv.h> 109 #endif 110 #if defined(BCM_SHADOW_SUPPORT) 111 #include <soc/shadow.h> 112 #endif /* BCM_SHADOW_SUPPORT */ 113 #if defined(BCM_KATANA_SUPPORT) 114 #include <soc/katana.h> 115 #endif /* BCM_KATANA_SUPPORT */ 116 #if defined(BCM_KATANA2_SUPPORT) 117 #include <soc/katana2.h> 118 #include <soc/uc.h> 119 #endif /* BCM_KATANA2_SUPPORT */ 120 #if defined(BCM_SABER2_SUPPORT) 121 #include <soc/saber2.h> 122 #include <soc/shmoo_and28.h> 123 #include <soc/phy/ddr34.h> 124 #endif /* BCM_SABER2_SUPPORT */ 125 #if defined(BCM_METROLITE_SUPPORT) 126 #include <soc/metrolite.h> 127 #endif /* BCM_METROLITE_SUPPORT */ 128 #if defined(BCM_TOMAHAWK_SUPPORT) 129 #include <soc/tomahawk.h> 130 #endif /* BCM_TOMAHAWK_SUPPORT */ 131 #if defined(BCM_TOMAHAWK3_SUPPORT) 132 #include <soc/tomahawk3.h> 133 #endif /* BCM_TOMAHAWK3_SUPPORT */ 134 #if defined(BCM_TRIDENT3_SUPPORT) 135 #include <soc/trident3.h> 136 #endif /* BCM_TRIDENT3_SUPPORT */ 137 #if defined(BCM_HELIX5_SUPPORT) 138 #include <soc/helix5.h> 139 #endif /* BCM_HELIX5_SUPPORT */ 140 #if defined(BCM_MAVERICK2_SUPPORT) 141 #include <soc/maverick2.h> 142 #endif /* BCM_MAVERICK2_SUPPORT */ 143 #if defined(BCM_TOMAHAWK2_SUPPORT) 144 #include <soc/tomahawk2.h> 145 #endif /* BCM_TOMAHAWK2_SUPPORT */ 146 #if defined(BCM_TOMAHAWK3_SUPPORT) 147 #include <soc/tomahawk3.h> 148 #endif /* BCM_TOMAHAWK3_SUPPORT */ 149 150 #include <soc/mmuerr.h> 151 #include <soc/higig.h> 152 #include <soc/ipoll.h> 153 #include <soc/phyctrl.h> 154 #include <soc/dport.h> 155 #ifdef BCM_RCPU_SUPPORT 156 #include <soc/rcpu.h> 157 #endif /* BCM_RCPU_SUPPORT */ 158 #ifdef INCLUDE_KNET 159 #include <soc/knet.h> 160 #endif 161 #include <soc/esw/portctrl.h> 162 #include <soc/bondoptions.h> 163 #include <bcm_int/esw/subport.h> 164 #ifdef INCLUDE_AVS 165 #include <soc/avs.h> 166 #endif /* INCLUDE_AVS */ 167 168 #if defined(CANCUN_SUPPORT) 169 #include <soc/esw/cancun.h> 170 #endif /* CANCUN_SUPPORT */ 171 172 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 173 #include <soc/td2_td2p.h> 174 #endif 175 176 #ifdef BCM_KATANA_SUPPORT 177 #define BCM_SABER_MAX_COUNTER_DIRECTION 2 178 #define BCM_SABER_MAX_COUNTER_POOL 8 179 #endif 180 extern int _bcm_esw_ibod_sync_recovery_stop(int unit); 181 182 #ifdef ALPM_ENABLE 183 extern int alpm_dist_hitbit_thread_stop(int unit); 184 #endif 185 186 #ifdef BCM_WARM_BOOT_SUPPORT 187 STATIC int soc_warmboot_reset(int unit); 188 #endif 189 190 #ifdef BCM_ESW_SUPPORT 191 192 #define _SOC_MEM_SKIP_SCRUB(unit, mem, skip) {\ 193 soc_mem_t skip_mem = mem;\ 194 skip = (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_SER_FLAGS)? 0 : 1;\ 195 switch(mem) {\ 196 case RH_HGT_FLOWSETm:\ 197 case RH_HGT_FLOWSET_PIPE0m:\ 198 case RH_HGT_FLOWSET_PIPE1m:\ 199 case DLB_HGT_FLOWSETm:\ 200 if ((SOC_IS_TRIDENT2X(unit) || SOC_IS_TITAN2PLUS(unit)) &&\ 201 SOC_REG_IS_VALID(unit, ENHANCED_HASHING_CONTROLr)) {\ 202 uint32 is_rh_hgt = 0;\ 203 uint32 rval;\ 204 READ_ENHANCED_HASHING_CONTROLr(unit, &rval);\ 205 is_rh_hgt = soc_reg_field_get(unit, ENHANCED_HASHING_CONTROLr, rval,\ 206 RH_HGT_ENABLEf);\ 207 skip_mem = (is_rh_hgt == 1)? DLB_HGT_FLOWSETm : RH_HGT_FLOWSETm;\ 208 skip = (skip_mem == mem)?1:0;\ 209 }\ 210 if (SOC_IS_TRIDENT3X(unit) &&\ 211 SOC_REG_IS_VALID(unit, ENHANCED_HASHING_CONTROL_2r)) {\ 212 uint32 is_rh_dlb = 0;\ 213 uint32 is_hgt_lag = 0;\ 214 uint32 rval;\ 215 READ_ENHANCED_HASHING_CONTROL_2r(unit, &rval);\ 216 is_rh_dlb = soc_reg_field_get(unit, ENHANCED_HASHING_CONTROL_2r, rval,\ 217 RH_DLB_SELECTIONf);\ 218 is_hgt_lag = soc_reg_field_get(unit, ENHANCED_HASHING_CONTROL_2r, rval,\ 219 HGT_LAG_FLOWSET_TABLE_CONFIGf);\ 220 skip = (is_rh_dlb == 0)? 1 :((is_hgt_lag == 0)? 1 : 0);\ 221 }\ 222 break;\ 223 case RH_LAG_FLOWSETm:\ 224 case RH_LAG_FLOWSET_PIPE0m:\ 225 case RH_LAG_FLOWSET_PIPE1m:\ 226 if (SOC_IS_TRIDENT3X(unit) &&\ 227 SOC_REG_IS_VALID(unit, ENHANCED_HASHING_CONTROL_2r)) {\ 228 uint32 is_rh_dlb = 0;\ 229 uint32 is_hgt_lag = 0;\ 230 uint32 rval;\ 231 READ_ENHANCED_HASHING_CONTROL_2r(unit, &rval);\ 232 is_rh_dlb = soc_reg_field_get(unit, ENHANCED_HASHING_CONTROL_2r, rval,\ 233 RH_DLB_SELECTIONf);\ 234 is_hgt_lag = soc_reg_field_get(unit, ENHANCED_HASHING_CONTROL_2r, rval,\ 235 HGT_LAG_FLOWSET_TABLE_CONFIGf);\ 236 skip = (is_rh_dlb == 0)? 1 :((is_hgt_lag == 1)? 1 : 0);\ 237 }\ 238 break;\ 239 case DLB_HGT_LAG_FLOWSETm:\ 240 case DLB_HGT_LAG_FLOWSET_PIPE0m:\ 241 case DLB_HGT_LAG_FLOWSET_PIPE1m:\ 242 if (SOC_IS_TRIDENT3X(unit) &&\ 243 SOC_REG_IS_VALID(unit, ENHANCED_HASHING_CONTROL_2r)) {\ 244 uint32 is_rh_dlb = 0;\ 245 uint32 rval;\ 246 READ_ENHANCED_HASHING_CONTROL_2r(unit, &rval);\ 247 is_rh_dlb = soc_reg_field_get(unit, ENHANCED_HASHING_CONTROL_2r, rval,\ 248 RH_DLB_SELECTIONf);\ 249 skip = (is_rh_dlb == 1)? 1 : 0;\ 250 }\ 251 break;\ 252 case RH_ECMP_FLOWSETm:\ 253 case RH_ECMP_FLOWSET_PIPE0m:\ 254 case RH_ECMP_FLOWSET_PIPE1m:\ 255 if (SOC_IS_TRIDENT3X(unit) &&\ 256 SOC_REG_IS_VALID(unit, ENHANCED_HASHING_CONTROLr)) {\ 257 uint32 is_rh_dlb = 0;\ 258 uint32 rval;\ 259 READ_ENHANCED_HASHING_CONTROLr(unit, &rval);\ 260 is_rh_dlb = soc_reg_field_get(unit, ENHANCED_HASHING_CONTROLr, rval,\ 261 RH_DLB_SELECTIONf);\ 262 skip = (is_rh_dlb == 1)? 0 : 1;\ 263 }\ 264 break;\ 265 case DLB_ECMP_FLOWSETm:\ 266 case DLB_ECMP_FLOWSET_PIPE0m:\ 267 case DLB_ECMP_FLOWSET_PIPE1m:\ 268 case DLB_ECMP_FLOWSET_MEMBER_PIPE0m:\ 269 case DLB_ECMP_FLOWSET_MEMBER_PIPE1m:\ 270 case DLB_ECMP_FLOWSET_MEMBERm:\ 271 if (SOC_IS_TRIDENT3X(unit) &&\ 272 SOC_REG_IS_VALID(unit, ENHANCED_HASHING_CONTROLr)) {\ 273 uint32 is_rh_dlb = 0;\ 274 uint32 rval;\ 275 READ_ENHANCED_HASHING_CONTROLr(unit, &rval);\ 276 is_rh_dlb = soc_reg_field_get(unit, ENHANCED_HASHING_CONTROLr, rval,\ 277 RH_DLB_SELECTIONf);\ 278 skip = (is_rh_dlb == 1)? 1 : 0;\ 279 }\ 280 break;\ 281 default:\ 282 break;\ 283 }\ 284 } 285 286 #define _SOC_DRV_MEM_REUSE_MEM_STATE_NO_LOCK(unit, mem) \ 287 {\ 288 switch(mem) {\ 289 case VLAN_XLATE_1m: mem = VLAN_XLATEm; break;\ 290 case EP_VLAN_XLATE_1m: mem = EGR_VLAN_XLATEm; break;\ 291 case MPLS_ENTRY_1m: mem = MPLS_ENTRYm; break;\ 292 case VLAN_MACm: \ 293 if (SOC_IS_TRX(unit) && !soc_feature(unit, soc_feature_ism_memory)) {\ 294 mem = VLAN_XLATEm;\ 295 }\ 296 break;\ 297 case EGR_VLANm: \ 298 if (SOC_IS_KATANA2(unit)) {\ 299 mem = VLAN_TABm;\ 300 }\ 301 break;\ 302 default: break;\ 303 }\ 304 } 305 306 /* Routine to check if this is the mem whose state is being (mapped-to) actually-used by others */ 307 int _SOC_DRV_MEM_IS_REUSED_MEM(int unit, soc_mem_t mem) {\ 308 switch(mem) {\ 309 case EGR_VLAN_XLATEm: return TRUE;\ 310 case MPLS_ENTRYm: return TRUE;\ 311 case VLAN_XLATEm:\ 312 if (SOC_IS_TRX(unit)) {\ 313 return TRUE;\ 314 }\ 315 break;\ 316 case VLAN_TABm:\ 317 if (SOC_IS_KATANA2(unit)) {\ 318 return TRUE;\ 319 }\ 320 break;\ 321 default: break;\ 322 }\ 323 return FALSE;\ 324 } 325 326 void soc_drv_mem_reuse_mem_state(int unit, soc_mem_t *mem, 327 soc_mem_t *lock_mem) 328 { 329 _SOC_DRV_MEM_REUSE_MEM_STATE_NO_LOCK(unit, *mem); 330 *lock_mem = *mem; 331 switch(*mem) { 332 case L3_ENTRY_ONLYm: 333 case L3_ENTRY_IPV4_UNICASTm: 334 case L3_ENTRY_IPV6_UNICASTm: 335 case L3_ENTRY_IPV6_MULTICASTm: 336 if (soc_feature(unit, soc_feature_shared_hash_mem)) { 337 *lock_mem = L3_ENTRY_IPV4_MULTICASTm; 338 } 339 break; 340 case L3_ENTRY_ECCm: 341 case L3_ENTRY_SINGLEm: 342 case L3_ENTRY_DOUBLEm: 343 case L3_ENTRY_QUADm: 344 case L3_ENTRY_ONLY_SINGLEm: 345 case L3_ENTRY_ONLY_DOUBLEm: 346 case L3_ENTRY_ONLY_QUADm: 347 if (soc_feature(unit, soc_feature_shared_hash_mem)) { 348 *lock_mem = L3_ENTRY_ECCm; 349 } 350 break; 351 /* In TH2, VLAN_2_TAB share the same lock with VLAN_TAB*/ 352 353 case EGR_VLANm: 354 if (SOC_MEM_FIELD_VALID(unit, VLAN_TABm, VRF_IDf)) { 355 *lock_mem = VLAN_TABm; 356 } 357 break; 358 default: break; 359 } 360 if (SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT2PLUS(unit) || SOC_IS_APACHE(unit)) { 361 switch(*mem) { 362 case L3_ENTRY_LPm: 363 case L3_ENTRY_ISS_LPm: 364 case L3_ENTRY_ONLY_ECCm: 365 if (soc_feature(unit, soc_feature_shared_hash_mem)) { 366 *lock_mem = L3_ENTRY_IPV4_MULTICASTm; 367 } 368 break; 369 default: break; 370 } 371 } 372 if (SOC_IS_TRIDENT3X(unit)) { 373 switch (*mem) { 374 case EXACT_MATCH_2m: 375 case EXACT_MATCH_4m: 376 case EXACT_MATCH_2_PIPE0m: 377 case EXACT_MATCH_2_PIPE1m: 378 case EXACT_MATCH_4_PIPE0m: 379 case EXACT_MATCH_4_PIPE1m: 380 case EXACT_MATCH_ECCm: 381 case EXACT_MATCH_ECC_PIPE0m: 382 case EXACT_MATCH_ECC_PIPE1m: 383 *lock_mem = EXACT_MATCH_ECCm; 384 break; 385 case L2_ENTRY_SINGLEm: 386 case L2_ENTRY_ECCm: 387 *lock_mem = L2Xm; 388 break; 389 case VLAN_XLATE_1_DOUBLEm: 390 case VLAN_XLATE_1_ECCm: 391 *lock_mem = VLAN_XLATE_1_SINGLEm; 392 break; 393 case VLAN_XLATE_2_DOUBLEm: 394 case VLAN_XLATE_2_ECCm: 395 *lock_mem = VLAN_XLATE_2_SINGLEm; 396 break; 397 case EGR_VLAN_XLATE_1_DOUBLEm: 398 case EGR_VLAN_XLATE_1_ECCm: 399 *lock_mem = EGR_VLAN_XLATE_1_SINGLEm; 400 break; 401 case EGR_VLAN_XLATE_2_DOUBLEm: 402 case EGR_VLAN_XLATE_2_ECCm: 403 *lock_mem = EGR_VLAN_XLATE_2_SINGLEm; 404 break; 405 case MPLS_ENTRY_SINGLEm: 406 case MPLS_ENTRY_ECCm: 407 *lock_mem = MPLS_ENTRYm; 408 break; 409 default: break; 410 } 411 } 412 413 if (SOC_IS_TD2P_TT2P(unit) || SOC_IS_APACHE(unit) || SOC_IS_TOMAHAWK(unit)|| 414 SOC_IS_TOMAHAWKPLUS(unit) || SOC_IS_TOMAHAWK2(unit)) { 415 switch (*mem) { 416 case L2_ENTRY_ONLY_ECCm: 417 *lock_mem = L2Xm; 418 break; 419 case VLAN_XLATE_ECCm: 420 *lock_mem = VLAN_XLATEm; 421 break; 422 case EGR_VLAN_XLATE_ECCm: 423 *lock_mem = EGR_VLAN_XLATEm; 424 break; 425 default: break; 426 } 427 } 428 429 if (SOC_IS_TOMAHAWK3(unit)) { 430 switch (*mem) { 431 case L2_ENTRY_ECCm: 432 *lock_mem = L2Xm; 433 break; 434 default: break; 435 } 436 } 437 438 return; 439 } 440 441 void soc_drv_mem_sync_mapped_lock(int unit, soc_mem_t mem, 442 sal_mutex_t lock_mapped) 443 { 444 switch(mem) { 445 case EGR_VLAN_XLATEm: 446 SOC_MEM_STATE(unit, EP_VLAN_XLATE_1m).lock = lock_mapped; 447 break; 448 case MPLS_ENTRYm: 449 SOC_MEM_STATE(unit, MPLS_ENTRY_1m).lock = lock_mapped; 450 break; 451 case VLAN_XLATEm: 452 if (SOC_IS_TRX(unit)) { 453 if (soc_feature(unit, soc_feature_ism_memory)) { 454 SOC_MEM_STATE(unit, VLAN_XLATE_1m).lock = lock_mapped; 455 } else { 456 SOC_MEM_STATE(unit, VLAN_MACm).lock = lock_mapped; 457 } 458 } 459 break; 460 case VLAN_TABm: 461 if (SOC_IS_KATANA2(unit)) { 462 SOC_MEM_STATE(unit, EGR_VLANm).lock = lock_mapped; 463 } 464 if (SOC_MEM_FIELD_VALID(unit, VLAN_TABm, VRF_IDf)) { 465 SOC_MEM_STATE(unit, EGR_VLANm).lock = lock_mapped; 466 } 467 break; 468 case L3_ENTRY_IPV4_MULTICASTm: 469 if (soc_feature(unit, soc_feature_shared_hash_mem)) { 470 SOC_MEM_STATE(unit, L3_ENTRY_ONLYm).lock = lock_mapped; 471 SOC_MEM_STATE(unit, L3_ENTRY_IPV4_UNICASTm).lock = lock_mapped; 472 SOC_MEM_STATE(unit, L3_ENTRY_IPV6_UNICASTm).lock = lock_mapped; 473 SOC_MEM_STATE(unit, L3_ENTRY_IPV6_MULTICASTm).lock = lock_mapped; 474 if (SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT2PLUS(unit) || SOC_IS_APACHE(unit)) { 475 SOC_MEM_STATE(unit, L3_ENTRY_LPm).lock = lock_mapped; 476 SOC_MEM_STATE(unit, L3_ENTRY_ISS_LPm).lock = lock_mapped; 477 SOC_MEM_STATE(unit, L3_ENTRY_ONLY_ECCm).lock = lock_mapped; 478 } 479 } 480 break; 481 case L3_ENTRY_ECCm: 482 if (soc_feature(unit, soc_feature_shared_hash_mem)) { 483 SOC_MEM_STATE(unit, L3_ENTRY_SINGLEm).lock = lock_mapped; 484 SOC_MEM_STATE(unit, L3_ENTRY_DOUBLEm).lock = lock_mapped; 485 SOC_MEM_STATE(unit, L3_ENTRY_QUADm).lock = lock_mapped; 486 SOC_MEM_STATE(unit, L3_ENTRY_ONLY_SINGLEm).lock = lock_mapped; 487 SOC_MEM_STATE(unit, L3_ENTRY_ONLY_DOUBLEm).lock = lock_mapped; 488 SOC_MEM_STATE(unit, L3_ENTRY_ONLY_QUADm).lock = lock_mapped; 489 } 490 break; 491 case EXACT_MATCH_ECCm: 492 if (SOC_IS_TRIDENT3X(unit)) { 493 SOC_MEM_STATE(unit, EXACT_MATCH_2m).lock = lock_mapped; 494 SOC_MEM_STATE(unit, EXACT_MATCH_4m).lock = lock_mapped; 495 SOC_MEM_STATE(unit, EXACT_MATCH_2_PIPE0m).lock = lock_mapped; 496 SOC_MEM_STATE(unit, EXACT_MATCH_2_PIPE1m).lock = lock_mapped; 497 SOC_MEM_STATE(unit, EXACT_MATCH_4_PIPE0m).lock = lock_mapped; 498 SOC_MEM_STATE(unit, EXACT_MATCH_4_PIPE1m).lock = lock_mapped; 499 SOC_MEM_STATE(unit, EXACT_MATCH_ECC_PIPE0m).lock = lock_mapped; 500 SOC_MEM_STATE(unit, EXACT_MATCH_ECC_PIPE1m).lock = lock_mapped; 501 } 502 break; 503 case EGR_IP_TUNNELm: 504 if (SOC_IS_TOMAHAWK3(unit)) { 505 SOC_MEM_STATE(unit, EGR_IP_TUNNEL_MPLSm).lock = lock_mapped; 506 SOC_MEM_STATE(unit, EGR_IP_TUNNEL_IPV6m).lock = lock_mapped; 507 } 508 break; 509 default: break; 510 } 511 512 if (SOC_IS_TRIDENT3X(unit)) { 513 switch (mem) { 514 case L2Xm: 515 SOC_MEM_STATE(unit, L2_ENTRY_ECCm).lock = lock_mapped; 516 SOC_MEM_STATE(unit, L2_ENTRY_SINGLEm).lock = lock_mapped; 517 break; 518 case VLAN_XLATE_1_SINGLEm: 519 SOC_MEM_STATE(unit, VLAN_XLATE_1_ECCm).lock = lock_mapped; 520 SOC_MEM_STATE(unit, VLAN_XLATE_1_DOUBLEm).lock = lock_mapped; 521 break; 522 case VLAN_XLATE_2_SINGLEm: 523 SOC_MEM_STATE(unit, VLAN_XLATE_2_ECCm).lock = lock_mapped; 524 SOC_MEM_STATE(unit, VLAN_XLATE_2_DOUBLEm).lock = lock_mapped; 525 break; 526 case EGR_VLAN_XLATE_1_SINGLEm: 527 SOC_MEM_STATE(unit, EGR_VLAN_XLATE_1_ECCm).lock = lock_mapped; 528 SOC_MEM_STATE(unit, EGR_VLAN_XLATE_1_DOUBLEm).lock = lock_mapped; 529 break; 530 case EGR_VLAN_XLATE_2_SINGLEm: 531 SOC_MEM_STATE(unit, EGR_VLAN_XLATE_2_ECCm).lock = lock_mapped; 532 SOC_MEM_STATE(unit, EGR_VLAN_XLATE_2_DOUBLEm).lock = lock_mapped; 533 break; 534 case MPLS_ENTRYm: 535 SOC_MEM_STATE(unit, MPLS_ENTRY_ECCm).lock = lock_mapped; 536 SOC_MEM_STATE(unit, MPLS_ENTRY_SINGLEm).lock = lock_mapped; 537 break; 538 default: break; 539 } 540 } 541 542 if (SOC_IS_TD2P_TT2P(unit) || SOC_IS_APACHE(unit) || SOC_IS_TOMAHAWK(unit)|| 543 SOC_IS_TOMAHAWKPLUS(unit) || SOC_IS_TOMAHAWK2(unit)) { 544 switch (mem) { 545 case L2Xm: 546 SOC_MEM_STATE(unit, L2_ENTRY_ONLY_ECCm).lock = lock_mapped; 547 break; 548 case VLAN_XLATEm: 549 SOC_MEM_STATE(unit, VLAN_XLATE_ECCm).lock = lock_mapped; 550 break; 551 case EGR_VLAN_XLATEm: 552 SOC_MEM_STATE(unit, EGR_VLAN_XLATE_ECCm).lock = lock_mapped; 553 break; 554 default: break; 555 } 556 } 557 558 if (SOC_IS_TOMAHAWK3(unit)) { 559 switch (mem) { 560 case L2Xm: 561 SOC_MEM_STATE(unit, L2_ENTRY_ECCm).lock = lock_mapped; 562 break; 563 default: break; 564 } 565 } 566 567 return; 568 } 569 #endif /* BCM_ESW_SUPPORT */ 570 571 /* 572 * Function: 573 * soc_mmu_init 574 * Purpose: 575 * Initialize MMU registers 576 * Parameters: 577 * unit - unit number 578 * Returns: 579 * SOC_E_XXX 580 */ 581 int 582 soc_mmu_init(int unit) 583 { 584 int rv; 585 586 LOG_VERBOSE(BSL_LS_SOC_COMMON, 587 (BSL_META_U(unit, 588 "soc_mmu_init\n"))); 589 590 if (!soc_attached(unit)) { 591 return SOC_E_INIT; 592 } 593 594 if (SOC_IS_RCPU_ONLY(unit)) { 595 return SOC_E_NONE; 596 } 597 598 /* Perform Chip-Dependent Initializations */ 599 600 rv = SOC_FUNCTIONS(unit)->soc_mmu_init(unit); 601 602 return rv; 603 } 604 605 /* 606 * Function: 607 * soc_chip_driver_find 608 * Purpose: 609 * Return the soc_driver for a chip if found. 610 * If not found, return NULL. 611 * Parameters: 612 * pci_dev_id - PCI dev ID to find (exact match) 613 * pci_rev_id - PCI dev ID to find (exact match) 614 * Returns: 615 * Pointer to static driver structure 616 */ 617 soc_driver_t * 618 soc_chip_driver_find(uint16 pci_dev_id, uint8 pci_rev_id) 619 { 620 int i; 621 soc_driver_t *d; 622 uint16 driver_dev_id; 623 uint8 driver_rev_id; 624 625 if (soc_cm_get_id_driver(pci_dev_id, pci_rev_id, 626 &driver_dev_id, &driver_rev_id) < 0) { 627 return NULL; 628 } 629 630 /* 631 * Find driver in table. In theory any IDs returned by 632 * soc_cm_id_to_driver_id() should have a driver in the table. 633 */ 634 635 for (i = 0; i < SOC_NUM_SUPPORTED_CHIPS; i++) { 636 d = soc_base_driver_table[i]; 637 if ((d != NULL) && 638 (d->block_info != NULL) && 639 (d->pci_device == driver_dev_id) && 640 (d->pci_revision == driver_rev_id)) { 641 return d; 642 } 643 } 644 645 LOG_ERROR(BSL_LS_SOC_COMMON, 646 (BSL_META("soc_chip_driver_find: driver in devid table " 647 "not in soc_base_driver_table\n"))); 648 649 return NULL; 650 } 651 652 #if defined(PLISIM) && defined(BCM_KATANA2_SUPPORT) 653 STATIC char * 654 _dummy_sysconf_get_property(const char *property) 655 { 656 #ifndef NO_SAL_APPL 657 return sal_config_get(property); 658 #else 659 return NULL; 660 #endif 661 } 662 STATIC char * 663 _dummy_config_var_get(soc_cm_dev_t *dev, const char *property) 664 { 665 char str[SAL_CONFIG_STR_MAX]; 666 int i=0; 667 COMPILER_REFERENCE(dev); 668 for (i=0; (property[i] != '.') && (property[i] != '\0');i++) { 669 str[i]=property[i]; 670 } 671 str[i]='\0'; 672 return _dummy_sysconf_get_property(str); 673 } 674 #endif /* PLISIM && BCM_KATANA2_SUPPORT */ 675 676 677 678 #if defined(BCM_ESW_SUPPORT) && defined(BCM_IPROC_SUPPORT) 679 /* 680 * Function: 681 * soc_info_bondoptions_adjust 682 * Parameters: 683 * unit - Unit number 684 * Purpose: 685 * Update soc_control cache based on bond options info. 686 * Also add/remove soc features per SKU capabilities. 687 */ 688 STATIC void 689 soc_info_bondoptions_adjust(int unit) 690 { 691 int i; 692 int max_mtu; 693 694 for (i = 0; i < socBondInfoFeatureCount; i++) { 695 696 /* Bond feature is not set, skip */ 697 if (!SOC_BOND_INFO_FEATURE_GET(unit, i)) { 698 continue; 699 } 700 701 switch (i) { 702 case socBondInfoFeatureEfp512HalfSlice: 703 SOC_FEATURE_SET(unit, soc_feature_field_stage_egress_512_half_slice); 704 break; 705 case socBondInfoFeatureVfp512HalfSlice: 706 SOC_FEATURE_SET(unit, soc_feature_field_stage_lookup_512_half_slice); 707 break; 708 case socBondInfoFeatureIfpSliceHalf: 709 SOC_FEATURE_SET(unit, soc_feature_field_stage_half_slice); 710 #if defined(BCM_APACHE_SUPPORT) 711 if (SOC_IS_APACHE(unit)) { 712 SOC_FEATURE_SET(unit, soc_feature_field_half_slice_single_tcam); 713 } 714 #endif /* !BCM_APACHE_SUPPORT */ 715 break; 716 case socBondInfoFeatureNoL3Tunnel: 717 SOC_FEATURE_SET(unit, soc_feature_no_tunnel); 718 break; 719 case socBondInfoFeatureNoStaticNat: 720 SOC_FEATURE_CLEAR(unit, soc_feature_nat); 721 break; 722 case socBondInfoFeatureNoCutThru: 723 SOC_FEATURE_CLEAR(unit, soc_feature_asf); 724 SOC_FEATURE_CLEAR(unit, soc_feature_asf_multimode); 725 break; 726 case socBondInfoFeatureNoL3: 727 SOC_FEATURE_CLEAR(unit, soc_feature_l3); 728 if (SOC_IS_GREYHOUND2(unit)) { 729 SOC_FEATURE_CLEAR(unit, soc_feature_l3_ip6); 730 SOC_FEATURE_CLEAR(unit, soc_feature_l3_entry_key_type); 731 SOC_FEATURE_CLEAR(unit, soc_feature_lpm_tcam); 732 SOC_FEATURE_CLEAR(unit, soc_feature_ip_mcast); 733 SOC_FEATURE_CLEAR(unit, soc_feature_ip_mcast_repl); 734 SOC_FEATURE_CLEAR(unit, soc_feature_ipmc_unicast); 735 SOC_FEATURE_CLEAR(unit, soc_feature_ipmc_use_configured_dest_mac); 736 SOC_FEATURE_CLEAR(unit, soc_feature_urpf); 737 SOC_FEATURE_CLEAR(unit, soc_feature_l3mc_use_egress_next_hop); 738 SOC_FEATURE_CLEAR(unit, soc_feature_l3_sgv); 739 SOC_FEATURE_CLEAR(unit, soc_feature_l3_dynamic_ecmp_group); 740 SOC_FEATURE_CLEAR(unit, soc_feature_l3_ingress_interface); 741 SOC_FEATURE_CLEAR(unit, soc_feature_l3_iif_zero_invalid); 742 SOC_FEATURE_CLEAR(unit, soc_feature_l3_iif_under_4k); 743 SOC_FEATURE_SET(unit, soc_feature_l3_no_ecmp); 744 SOC_FEATURE_SET(unit, soc_feature_miml_no_l3); 745 } 746 if (SOC_IS_TOMAHAWK2(unit)) { 747 SOC_FEATURE_CLEAR(unit, soc_feature_l3_ip6); 748 SOC_FEATURE_CLEAR(unit, soc_feature_l3_entry_key_type); 749 SOC_FEATURE_CLEAR(unit, soc_feature_lpm_tcam); 750 SOC_FEATURE_CLEAR(unit, soc_feature_ip_mcast); 751 SOC_FEATURE_CLEAR(unit, soc_feature_ip_mcast_repl); 752 SOC_FEATURE_CLEAR(unit, soc_feature_ipmc_unicast); 753 SOC_FEATURE_CLEAR(unit, soc_feature_ipmc_use_configured_dest_mac); 754 SOC_FEATURE_CLEAR(unit, soc_feature_urpf); 755 SOC_FEATURE_CLEAR(unit, soc_feature_l3mc_use_egress_next_hop); 756 SOC_FEATURE_CLEAR(unit, soc_feature_l3_sgv); 757 SOC_FEATURE_CLEAR(unit, soc_feature_l3_dynamic_ecmp_group); 758 SOC_FEATURE_CLEAR(unit, soc_feature_l3_ingress_interface); 759 SOC_FEATURE_CLEAR(unit, soc_feature_l3_iif_zero_invalid); 760 SOC_FEATURE_CLEAR(unit, soc_feature_l3_iif_under_4k); 761 SOC_FEATURE_CLEAR(unit, soc_feature_ecmp_dlb); 762 SOC_FEATURE_CLEAR(unit, soc_feature_ecmp_dlb_optimized); 763 SOC_FEATURE_CLEAR(unit, soc_feature_ecmp_dlb_property_force_set); 764 SOC_FEATURE_CLEAR(unit, soc_feature_l3_iif_profile); 765 SOC_FEATURE_CLEAR(unit, soc_feature_l3_ingress_interface); 766 SOC_FEATURE_CLEAR(unit, soc_feature_nat); 767 SOC_FEATURE_CLEAR(unit, soc_feature_l2gre); 768 SOC_FEATURE_CLEAR(unit, soc_feature_l2gre_default_tunnel); 769 SOC_FEATURE_CLEAR(unit, soc_feature_l3_lookup_cmd); 770 SOC_FEATURE_CLEAR(unit, soc_feature_l3_shared_defip_table); 771 SOC_FEATURE_CLEAR(unit, soc_feature_l3_ip4_options_profile); 772 SOC_FEATURE_CLEAR(unit, soc_feature_repl_l3_intf_use_next_hop); 773 SOC_FEATURE_CLEAR(unit, soc_feature_l3_extended_host_entry); 774 SOC_FEATURE_CLEAR(unit, soc_feature_l3_ecmp_1k_groups); 775 SOC_FEATURE_CLEAR(unit, soc_feature_l3_defip_map); 776 SOC_FEATURE_CLEAR(unit, soc_feature_l3_host_ecmp_group); 777 SOC_FEATURE_CLEAR(unit, soc_feature_niv); 778 SOC_FEATURE_CLEAR(unit, soc_feature_vlan_vp); 779 SOC_FEATURE_CLEAR(unit, soc_feature_vp_lag); 780 SOC_FEATURE_CLEAR(unit, soc_feature_virtual_switching); 781 SOC_FEATURE_SET(unit, soc_feature_int_common_init); 782 } 783 break; 784 case socBondInfoFeatureNoEcmp: 785 SOC_FEATURE_SET(unit, soc_feature_l3_no_ecmp); 786 break; 787 case socBondInfoFeatureNoAlpm: 788 SOC_FEATURE_CLEAR(unit, soc_feature_alpm); 789 break; 790 case socBondInfoFeatureNoMim: 791 SOC_FEATURE_CLEAR(unit, soc_feature_mim); 792 SOC_FEATURE_CLEAR(unit, soc_feature_mim_reserve_default_port); 793 SOC_FEATURE_CLEAR(unit, soc_feature_mim_bvid_insertion_control); 794 break; 795 case socBondInfoFeatureNoMpls: 796 SOC_FEATURE_CLEAR(unit, soc_feature_mpls); 797 SOC_FEATURE_CLEAR(unit, soc_feature_mpls_enhanced); 798 SOC_FEATURE_CLEAR(unit, soc_feature_mpls_entropy); 799 SOC_FEATURE_CLEAR(unit, soc_feature_td2p_mpls_entropy_label); 800 SOC_FEATURE_CLEAR(unit, soc_feature_mpls_lsr_ecmp); 801 SOC_FEATURE_CLEAR(unit, soc_feature_mpls_segment_routing); 802 SOC_FEATURE_CLEAR(unit, soc_feature_mpls_failover); 803 SOC_FEATURE_CLEAR(unit, soc_feature_flex_ctr_mpls_3_label_count); 804 SOC_FEATURE_CLEAR(unit, soc_feature_mpls_exp_to_phb_cng_map); 805 if (SOC_IS_TOMAHAWK2(unit)) { 806 SOC_FEATURE_CLEAR(unit, soc_feature_mpls_software_failover); 807 } 808 break; 809 case socBondInfoFeatureNoTrill: 810 SOC_FEATURE_CLEAR(unit, soc_feature_trill); 811 SOC_FEATURE_CLEAR(unit, soc_feature_trill_ttl); 812 break; 813 case socBondInfoFeatureNoVxlan: 814 SOC_FEATURE_CLEAR(unit, soc_feature_vxlan); 815 SOC_FEATURE_CLEAR(unit, soc_feature_vrf_aware_vxlan_termination); 816 break; 817 case socBondInfoFeatureNoVxlanLite: 818 SOC_FEATURE_CLEAR(unit, soc_feature_vxlan_lite); 819 break; 820 case socBondInfoFeatureNoRRCOE: 821 SOC_FEATURE_CLEAR(unit, soc_feature_rroce); 822 break; 823 case socBondInfoFeatureNoPreemption: 824 SOC_FEATURE_CLEAR(unit, soc_feature_preemption); 825 SOC_FEATURE_CLEAR(unit, soc_feature_preemption_cnt); 826 break; 827 case socBondInfoFeatureNoTAS: 828 SOC_FEATURE_CLEAR(unit, soc_feature_tas); 829 break; 830 case socBondInfoFeatureNoHSR: 831 SOC_FEATURE_CLEAR(unit, soc_feature_tsn_sr_hsr); 832 break; 833 case socBondInfoFeatureNoPRP: 834 SOC_FEATURE_CLEAR(unit, soc_feature_tsn_sr_prp); 835 break; 836 case socBondInfoFeatureNo8021CB: 837 SOC_FEATURE_CLEAR(unit, soc_feature_tsn_sr_802_1cb); 838 break; 839 case socBondInfoFeatureNoL2Gre: 840 SOC_FEATURE_CLEAR(unit, soc_feature_l2gre); 841 SOC_FEATURE_CLEAR(unit, soc_feature_td2_l2gre); 842 break; 843 case socBondInfoFeatureNoRiot: 844 SOC_FEATURE_CLEAR(unit, soc_feature_riot); 845 break; 846 case socBondInfoFeatureNoFpOam: 847 SOC_FEATURE_CLEAR(unit, soc_feature_fp_based_oam); 848 break; 849 case socBondInfoFeatureNoFcoe: 850 SOC_FEATURE_CLEAR(unit, soc_feature_fcoe); 851 break; 852 case socBondInfoFeatureNoTimeSync: 853 SOC_FEATURE_CLEAR(unit, soc_feature_timesync_support); 854 break; 855 case socBondInfoFeatureNoSat: 856 SOC_FEATURE_CLEAR(unit, soc_feature_sat); 857 break; 858 case socBondInfoFeatureNoServiceMeter: 859 SOC_FEATURE_CLEAR(unit, soc_feature_global_meter); 860 break; 861 case socBondInfoFeatureNoOam: 862 SOC_FEATURE_CLEAR(unit, soc_feature_oam); 863 break; 864 case socBondInfoFeatureNoHgProxyCoe: 865 SOC_FEATURE_CLEAR(unit, soc_feature_hgproxy_subtag_coe); 866 break; 867 case socBondInfoFeatureNoSubTagCoe: 868 SOC_FEATURE_CLEAR(unit, soc_feature_subtag_coe); 869 break; 870 case socBondInfoFeatureNoLinkPhy: 871 SOC_FEATURE_CLEAR(unit, soc_feature_linkphy_coe); 872 break; 873 case socBondInfoFeatureNoAvs: 874 SOC_FEATURE_CLEAR(unit, soc_feature_avs); 875 break; 876 case socBondInfoFeatureNoEpRedirectV2: 877 SOC_FEATURE_CLEAR(unit, soc_feature_ep_redirect_v2); 878 #if defined(BCM_APACHE_SUPPORT) 879 if (SOC_IS_APACHE(unit)) { 880 SOC_FEATURE_CLEAR(unit, soc_feature_egr_mirror_true); 881 } 882 #endif /* !BCM_APACHE_SUPPORT */ 883 break; 884 case socBondInfoFeatureNoOamTrueUpMep: 885 886 break; 887 case socBondInfoFeatureNoMultiLevelProt: 888 SOC_FEATURE_CLEAR(unit, soc_feature_hierarchical_protection); 889 break; 890 case socBondInfoFeatureNoFpSat: 891 SOC_FEATURE_CLEAR(unit, soc_feature_fp_based_sat); 892 break; 893 case socBondInfoFeatureNoSegmentRouting: 894 SOC_FEATURE_CLEAR(unit, soc_feature_mpls_segment_routing); 895 break; 896 case socBondInfoFeatureHqos3Levels: 897 SOC_FEATURE_CLEAR(unit, soc_feature_mmu_hqos_four_level); 898 break; 899 case socBondInfoFeatureNoPipe_2_3: 900 SOC_FEATURE_CLEAR(unit, soc_feature_pipe2_pipe3_disabled); 901 break; 902 case socBondInfoFeatureNoExactMatch: 903 SOC_FEATURE_CLEAR(unit, soc_feature_field_exact_match_support); 904 break; 905 case socBondInfoFeatureNoEfp: 906 SOC_FEATURE_SET(unit, soc_feature_no_efp); 907 break; 908 case socBondInfoFeatureNoIfp: 909 SOC_FEATURE_SET(unit, soc_feature_no_ifp); 910 break; 911 case socBondInfoFeatureNoVfp: 912 SOC_FEATURE_SET(unit, soc_feature_no_vfp); 913 break; 914 case socBondInfoFeatureNoLpm: 915 SOC_FEATURE_CLEAR(unit, soc_feature_lpm_tcam); 916 break; 917 case socBondInfoFeatureNoUftBank0: 918 SOC_FEATURE_CLEAR(unit, soc_feature_uft_bank_0); 919 break; 920 case socBondInfoFeatureNoUftBank1: 921 SOC_FEATURE_CLEAR(unit, soc_feature_uft_bank_1); 922 break; 923 case socBondInfoFeatureNoUftBank2: 924 SOC_FEATURE_CLEAR(unit, soc_feature_uft_bank_2); 925 break; 926 case socBondInfoFeatureNoUftBank3: 927 SOC_FEATURE_CLEAR(unit, soc_feature_uft_bank_3); 928 break; 929 case socBondInfoFeatureNoMplsFrr: 930 SOC_FEATURE_CLEAR(unit, soc_feature_mpls_frr); 931 break; 932 case socBondInfoFeatureNoDynamicLoadBalancing: 933 SOC_FEATURE_CLEAR(unit, soc_feature_ecmp_dlb); 934 SOC_FEATURE_CLEAR(unit, soc_feature_ecmp_dlb_optimized); 935 SOC_FEATURE_CLEAR(unit, soc_feature_lag_dlb); 936 SOC_FEATURE_CLEAR(unit, soc_feature_hg_dlb); 937 SOC_FEATURE_CLEAR(unit, soc_feature_hgt_lag_dlb_optimized); 938 break; 939 case socBondInfoFeatureNoDynamicAlternatePath: 940 SOC_FEATURE_CLEAR(unit, soc_feature_dgm); 941 break; 942 #ifdef INCLUDE_PSTATS 943 case socBondInfoFeatureNoPstats: 944 SOC_FEATURE_CLEAR(unit, soc_feature_pstats); 945 break; 946 #endif /* INCLUDE_PSTATS */ 947 case socBondInfoFeatureNoTCB: 948 SOC_FEATURE_CLEAR(unit, soc_feature_tcb); 949 break; 950 case socBondInfoFeatureNoTimestamp: 951 SOC_FEATURE_CLEAR(unit, soc_feature_timestamp); 952 break; 953 case socBondInfoFeatureLpm2k: 954 #if defined(BCM_TOMAHAWK2_SUPPORT) 955 if (SOC_IS_TOMAHAWK2(unit)) { 956 SOC_FEATURE_CLEAR(unit, soc_feature_urpf); 957 SOC_FEATURE_CLEAR(unit, soc_feature_l3_lpm_scaling_enable); 958 } 959 #endif /* BCM_TOMAHAWK2_SUPPORT */ 960 break; 961 #if defined(BCM_TOMAHAWK2_SUPPORT) 962 case socBondInfoFeatureIfpSlice3k: 963 SOC_FEATURE_SET(unit, soc_feature_field_stage_half_slice); 964 break; 965 case socBondInfoFeatureIfpSlice1k5: 966 SOC_FEATURE_SET(unit, soc_feature_field_stage_quarter_slice); 967 break; 968 #endif /* BCM_TOMAHAWK2_SUPPORT */ 969 970 #if defined(BCM_FLOWTRACKER_SUPPORT) 971 case socBondInfoBskDisable: 972 SOC_FEATURE_CLEAR(unit, soc_feature_flex_flowtracker_ver_1); 973 break; 974 case socBondInfoBskNoPktSampling: 975 SOC_FEATURE_CLEAR(unit, 976 soc_feature_flowtracker_ver_1_collector_copy); 977 break; 978 case socBondInfoBskNoTCPBidir: 979 SOC_FEATURE_CLEAR(unit, 980 soc_feature_flowtracker_ver_1_bidirectional); 981 break; 982 case socBondInfoBskNoDoSAttackVector: 983 SOC_FEATURE_CLEAR(unit, 984 soc_feature_flowtracker_ver_1_dos_attack_check); 985 break; 986 case socBondInfoBskNoHWExportPktBuild: 987 SOC_FEATURE_CLEAR(unit, 988 soc_feature_flowtracker_ver_1_ipfix_remote_collector); 989 break; 990 case socBondInfoBskNoMicroFlowPolicer: 991 SOC_FEATURE_CLEAR(unit, soc_feature_flowtracker_ver_1_metering); 992 break; 993 case socBondInfoBskNoALU32Inst2to11: 994 SOC_FEATURE_SET(unit, soc_feature_flowtracker_ver_1_alu32_0_1_banks); 995 break; 996 case socBondInfoBskSessionDepth8k: 997 SOC_FEATURE_SET(unit, soc_feature_flowtracker_ver_1_8K_ft_table); 998 SOC_FEATURE_CLEAR(unit, soc_feature_flowtracker_ver_1_16K_ft_table); 999 SOC_FEATURE_CLEAR(unit, soc_feature_flowtracker_ver_1_32K_ft_table); 1000 break; 1001 case socBondInfoBskSessionDepth16k: 1002 SOC_FEATURE_SET(unit, soc_feature_flowtracker_ver_1_16K_ft_table); 1003 SOC_FEATURE_CLEAR(unit, soc_feature_flowtracker_ver_1_8K_ft_table); 1004 SOC_FEATURE_CLEAR(unit, soc_feature_flowtracker_ver_1_32K_ft_table); 1005 break; 1006 case socBondInfoBskSessionDepth32k: 1007 SOC_FEATURE_SET(unit, soc_feature_flowtracker_ver_1_32K_ft_table); 1008 SOC_FEATURE_CLEAR(unit, soc_feature_flowtracker_ver_1_8K_ft_table); 1009 SOC_FEATURE_CLEAR(unit, soc_feature_flowtracker_ver_1_16K_ft_table); 1010 break; 1011 #endif /* BCM_FLOWTRACKER_SUPPORT */ 1012 1013 } 1014 } 1015 1016 /* Update SOC_INFO() params */ 1017 if ((SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureFamilyMaverick)) || 1018 (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureFamilyRanger2Plus))) { 1019 max_mtu = soc_property_get(unit, spn_MAX_MTU_SIZE, 9416); 1020 if ((max_mtu != 9416) && (max_mtu != 9600)){ 1021 max_mtu = 9416; 1022 } 1023 SOC_INFO(unit).max_mtu = max_mtu; 1024 } 1025 1026 if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureFamilyRanger2Plus)) { 1027 SOC_FEATURE_CLEAR(unit, soc_feature_olp); 1028 } 1029 1030 return; 1031 } 1032 #ifdef BCM_TOMAHAWK2_SUPPORT 1033 STATIC int 1034 soc_lpm_tcam_size_adjust(int unit) 1035 { 1036 soc_persist_t *sop; 1037 int defip_config; 1038 int num_ipv6_128b_entries; 1039 int config_v6_entries = 0; 1040 int def_num_ipv6_lpm_128B, max_num_ipv6_lpm_128B; 1041 1042 sop = SOC_PERSIST(unit); 1043 if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureLpm2k)) { 1044 SOC_CONTROL(unit)->l3_defip_max_tcams = 1; 1045 } else if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureLpm8k)) { 1046 SOC_CONTROL(unit)->l3_defip_max_tcams = 4; 1047 } else if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureLpm16k)) { 1048 return SOC_E_NONE; 1049 } else { 1050 return SOC_E_NONE; 1051 } 1052 1053 max_num_ipv6_lpm_128B = (SOC_CONTROL(unit)->l3_defip_max_tcams * 1054 SOC_CONTROL(unit)->l3_defip_tcam_size) >> 1; 1055 def_num_ipv6_lpm_128B = max_num_ipv6_lpm_128B >> 1; 1056 1057 if (!(soc_feature(unit, soc_feature_alpm) && 1058 soc_property_get(unit, spn_L3_ALPM_ENABLE, 0))) { 1059 1060 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1); 1061 1062 1063 num_ipv6_128b_entries = soc_property_get(unit, 1064 spn_NUM_IPV6_LPM_128B_ENTRIES, 1065 (defip_config ? def_num_ipv6_lpm_128B : 0)); 1066 1067 num_ipv6_128b_entries = num_ipv6_128b_entries + 1068 (num_ipv6_128b_entries % 2); 1069 if (num_ipv6_128b_entries > max_num_ipv6_lpm_128B) { 1070 LOG_CLI((BSL_META_U(unit, 1071 "The specified ipv6_lpm_128b_entries (%d) exceeds max_ipv6_lpm_128b_entries (%d)\n"), 1072 num_ipv6_128b_entries, max_num_ipv6_lpm_128B)); 1073 return SOC_E_PARAM; 1074 } 1075 1076 config_v6_entries = num_ipv6_128b_entries; 1077 if (soc_feature(unit, soc_feature_l3_lpm_scaling_enable) && 1078 soc_property_get(unit, spn_LPM_SCALING_ENABLE, 0)) { 1079 num_ipv6_128b_entries = 0; 1080 if (!soc_property_get(unit, spn_LPM_IPV6_128B_RESERVED, 1)) { 1081 config_v6_entries = ((config_v6_entries / 1082 SOC_CONTROL(unit)->l3_defip_tcam_size) + 1083 ((config_v6_entries % 1084 SOC_CONTROL(unit)->l3_defip_tcam_size) 1085 ? 1 : 0)) * SOC_CONTROL(unit)->l3_defip_tcam_size; 1086 } 1087 } 1088 sop->memState[L3_DEFIP_PAIR_128m].index_max = 1089 num_ipv6_128b_entries - 1; 1090 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 1091 num_ipv6_128b_entries - 1; 1092 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 1093 num_ipv6_128b_entries - 1; 1094 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 1095 num_ipv6_128b_entries - 1; 1096 sop->memState[L3_DEFIPm].index_max = 1097 (SOC_CONTROL(unit)->l3_defip_max_tcams * 1098 SOC_CONTROL(unit)->l3_defip_tcam_size) - 1099 (num_ipv6_128b_entries * 2) - 1; 1100 1101 if (soc_feature(unit, soc_feature_l3_1k_defip_table)) { 1102 sop->memState[L3_DEFIPm].index_max = 1023; 1103 } 1104 1105 sop->memState[L3_DEFIP_ONLYm].index_max = 1106 sop->memState[L3_DEFIPm].index_max; 1107 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 1108 sop->memState[L3_DEFIPm].index_max; 1109 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 1110 sop->memState[L3_DEFIPm].index_max; 1111 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 1112 } else { 1113 if (soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1)) { 1114 /* slightly different processing for v6-128 */ 1115 if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureLpm2k)) { 1116 LOG_CLI((BSL_META_U(unit, 1117 "The specified Lpm2k can not support LPM_128\n"))); 1118 return SOC_E_PARAM; 1119 } 1120 num_ipv6_128b_entries = soc_property_get(unit, 1121 spn_NUM_IPV6_LPM_128B_ENTRIES, 1122 def_num_ipv6_lpm_128B); 1123 num_ipv6_128b_entries = num_ipv6_128b_entries + 1124 (num_ipv6_128b_entries % 2); 1125 if (soc_tomahawk_alpm_mode_get(unit) == 1 || 1126 soc_tomahawk_alpm_mode_get(unit) == 3) { 1127 num_ipv6_128b_entries = (num_ipv6_128b_entries + 3) / 4 * 4; 1128 } 1129 config_v6_entries = num_ipv6_128b_entries; 1130 sop->memState[L3_DEFIP_PAIR_128m].index_max = 1131 num_ipv6_128b_entries - 1; 1132 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 1133 num_ipv6_128b_entries - 1; 1134 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 1135 num_ipv6_128b_entries - 1; 1136 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 1137 num_ipv6_128b_entries - 1; 1138 sop->memState[L3_DEFIPm].index_max = 1139 (SOC_CONTROL(unit)->l3_defip_max_tcams * 1140 SOC_CONTROL(unit)->l3_defip_tcam_size) - 1141 (num_ipv6_128b_entries * 2) - 1; 1142 1143 sop->memState[L3_DEFIP_ONLYm].index_max = 1144 sop->memState[L3_DEFIPm].index_max; 1145 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 1146 sop->memState[L3_DEFIPm].index_max; 1147 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 1148 sop->memState[L3_DEFIPm].index_max; 1149 SOC_CONTROL(unit)->l3_defip_index_remap = 1150 (num_ipv6_128b_entries / 2) * 2; 1151 } else { 1152 sop->memState[L3_DEFIP_PAIR_128m].index_max = -1; 1153 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = -1; 1154 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = -1; 1155 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = -1; 1156 } 1157 } 1158 return soc_l3_defip_indexes_init(unit, config_v6_entries); 1159 } 1160 1161 #endif /* BC_TOMAHAWK2_SUPPORT */ 1162 1163 /* 1164 * Function: 1165 * soc_mem_config_bondoptions_adjust 1166 * Parameters: 1167 * unit - Unit number 1168 * Purpose: 1169 * Update soc_control cache based on bond options info. 1170 * Also add/remove soc features per SKU capabilities. 1171 */ 1172 STATIC int 1173 soc_mem_config_bondoptions_adjust(int unit) 1174 { 1175 soc_persist_t *sop; 1176 int uft_size; 1177 int min_l2_entries = 16; 1178 int min_l3_entries = 4; 1179 int max_l2_entries, max_l3_entries; 1180 int l2_entries, l3_entries; 1181 int cfg_l2_entries, cfg_l3_entries; 1182 int shared_l2_banks, shared_l3_banks; 1183 int shared_bank_size; 1184 int alpm_enable; 1185 1186 sop = SOC_PERSIST(unit); 1187 if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureVrf2k)) { 1188 sop->memState[VRFm].index_max = 2047; 1189 } else if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureVrf1k)) { 1190 sop->memState[VRFm].index_max = 1023; 1191 } else if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureVrf16)) { 1192 sop->memState[VRFm].index_max = 15; 1193 } 1194 1195 if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureL3Iif8k)) { 1196 sop->memState[L3_IIFm].index_max = 8191; 1197 } 1198 1199 if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureL3Intf8k)) { 1200 sop->memState[EGR_L3_INTFm].index_max = 8191; 1201 } 1202 1203 1204 if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureSVP4k)) { 1205 sop->memState[SOURCE_VPm].index_max = 4095; 1206 sop->memState[ING_DVP_TABLEm].index_max = 4095; 1207 sop->memState[ING_DVP_2_TABLEm].index_max = 4095; 1208 sop->memState[EGR_DVP_ATTRIBUTEm].index_max = 4095; 1209 sop->memState[EGR_DVP_ATTRIBUTE_1m].index_max = 4095; 1210 } 1211 1212 if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureL3NHop8k)) { 1213 sop->memState[EGR_L3_NEXT_HOPm].index_max = 8191; 1214 sop->memState[ING_L3_NEXT_HOPm].index_max = 8191; 1215 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 8191; 1216 } else if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureNextHop16k)){ 1217 sop->memState[EGR_L3_NEXT_HOPm].index_max = 16383; 1218 sop->memState[ING_L3_NEXT_HOPm].index_max = 16383; 1219 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 16383; 1220 } else if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureNextHop32k)){ 1221 sop->memState[EGR_L3_NEXT_HOPm].index_max = 32767; 1222 sop->memState[ING_L3_NEXT_HOPm].index_max = 32767; 1223 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 32767; 1224 } else if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureNextHop48k)){ 1225 sop->memState[EGR_L3_NEXT_HOPm].index_max = 49151; 1226 sop->memState[ING_L3_NEXT_HOPm].index_max = 49151; 1227 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 49151; 1228 } 1229 #if defined(BCM_ESW_SUPPORT) && defined(BCM_IPROC_SUPPORT) && defined(BCM_TOMAHAWK2_SUPPORT) 1230 if (SOC_IS_TOMAHAWK2(unit)) { 1231 int rv = SOC_E_NONE; 1232 rv = soc_lpm_tcam_size_adjust(unit); 1233 if (rv != SOC_E_NONE) { 1234 return rv; 1235 } 1236 } 1237 #endif 1238 if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureIpmcDisabled)) { 1239 sop->memState[L3_IPMCm].index_max = 0; 1240 sop->memState[L3_IPMC_1m].index_max = 0; 1241 sop->memState[L3_IPMC_REMAPm].index_max = 0; 1242 sop->memState[EGR_IPMCm].index_max = 0; 1243 } else if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureIpmc4k)) { 1244 sop->memState[L3_IPMCm].index_max = 4095; 1245 sop->memState[L3_IPMC_1m].index_max = 4095; 1246 sop->memState[L3_IPMC_REMAPm].index_max = 4095; 1247 sop->memState[EGR_IPMCm].index_max = 4095; 1248 } else if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureIpmc8k)) { 1249 sop->memState[L3_IPMCm].index_max = 8191; 1250 sop->memState[L3_IPMC_1m].index_max = 8191; 1251 sop->memState[L3_IPMC_REMAPm].index_max = 8191; 1252 sop->memState[EGR_IPMCm].index_max = 8191; 1253 } 1254 1255 if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureUft128k)) { 1256 shared_bank_size = 32; 1257 uft_size = shared_bank_size * 4; 1258 max_l2_entries = min_l2_entries + uft_size; 1259 max_l3_entries = min_l3_entries + uft_size; 1260 1261 cfg_l2_entries = soc_property_get(unit, spn_L2_MEM_ENTRIES, -1); 1262 l2_entries = cfg_l2_entries == -1 ? min_l2_entries * 1024 : cfg_l2_entries; 1263 1264 if (l2_entries <= min_l2_entries * 1024) { /* Min table size */ 1265 l2_entries = min_l2_entries * 1024; 1266 shared_l2_banks = 0; 1267 } else if (l2_entries <= max_l2_entries * 1024) { 1268 l2_entries -= min_l2_entries * 1024; 1269 shared_l2_banks = (l2_entries + (shared_bank_size * 1024 - 1)) / (shared_bank_size * 1270 1024); 1271 l2_entries = min_l2_entries * 1024 + shared_l2_banks * shared_bank_size * 1024; 1272 } else { 1273 LOG_CLI((BSL_META_U(unit, 1274 "The specified l2_mem_entries (%d) exceeds 144K\n"), 1275 cfg_l2_entries)); 1276 return SOC_E_PARAM; 1277 } 1278 1279 cfg_l3_entries = soc_property_get(unit, spn_L3_MEM_ENTRIES, -1); 1280 l3_entries = cfg_l3_entries == -1 ? (min_l3_entries * 1024 ) : cfg_l3_entries; 1281 if (l3_entries <= min_l3_entries * 1024) { /* 4k dedicated L3 entries */ 1282 l3_entries = min_l3_entries * 1024; 1283 shared_l3_banks = 0; 1284 } else if (l3_entries <= max_l3_entries * 1024) { 1285 l3_entries -= min_l3_entries * 1024; 1286 shared_l3_banks = (l3_entries + (shared_bank_size * 1024 - 1)) / (shared_bank_size * 1287 1024); 1288 l3_entries = min_l3_entries * 1024 + shared_l3_banks * shared_bank_size * 1024; 1289 } else { 1290 LOG_CLI((BSL_META_U(unit, 1291 "The specified l3_mem_entries (%d) exceeds 132k\n"), 1292 cfg_l3_entries)); 1293 return SOC_E_PARAM; 1294 } 1295 1296 1297 alpm_enable = soc_property_get(unit, spn_L3_ALPM_ENABLE, 0); 1298 if (alpm_enable && soc_feature(unit, soc_feature_alpm)) { 1299 1300 if (shared_l2_banks + shared_l3_banks > 2) { 1301 LOG_CLI((BSL_META_U(unit, 1302 "A minimum of 2 shared banks is required for ALPM " 1303 "when it is enabled\n"))); 1304 return SOC_E_PARAM; 1305 } 1306 } else if (shared_l2_banks + shared_l3_banks > 4) { 1307 return SOC_E_PARAM; 1308 } 1309 1310 sop->memState[L2Xm].index_max = l2_entries - 1; 1311 sop->memState[L2_ENTRY_ONLYm].index_max = l2_entries - 1; 1312 sop->memState[L2_ENTRY_ONLY_ECCm].index_max = l2_entries - 1; 1313 sop->memState[L2_HITDA_ONLYm].index_max = l2_entries / 4 - 1; 1314 sop->memState[L2_HITSA_ONLYm].index_max = l2_entries / 4 - 1; 1315 sop->memState[L2_ENTRY_LPm].index_max = min_l2_entries*1024 / 4 - 1; 1316 sop->memState[L2_ENTRY_ISS_LPm].index_max = 1317 (l2_entries - min_l2_entries*1024) / 4 - 1; 1318 1319 /* Adjust L3 table size */ 1320 sop->memState[L3_ENTRY_ONLYm].index_max = l3_entries - 1; 1321 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = l3_entries - 1; 1322 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = l3_entries / 2 - 1; 1323 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = l3_entries/ 2 - 1; 1324 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = l3_entries / 4 - 1; 1325 sop->memState[L3_ENTRY_ONLY_ECCm].index_max = l3_entries - 1; 1326 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = l3_entries / 4 - 1; 1327 sop->memState[L3_ENTRY_LPm].index_max = min_l3_entries*1024 / 4 - 1; 1328 sop->memState[L3_ENTRY_ISS_LPm].index_max = 1329 (l3_entries - min_l3_entries*1024) / 4 - 1; 1330 1331 /* Adjust ALPM table size */ 1332 if (alpm_enable) { 1333 /* The check below is sufficient because if ALPM mode is enabled 1334 * and number of shared banks used is > 2 we return SOC_E_PARAM 1335 * in code at the top of this function. 1336 */ 1337 if (shared_l2_banks + shared_l3_banks > 0) { 1338 sop->memState[L3_DEFIP_ALPM_RAWm].index_max = 1339 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_RAWm).index_max / 2); 1340 sop->memState[L3_DEFIP_ALPM_IPV4m].index_max = 1341 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_IPV4m).index_max / 2); 1342 sop->memState[L3_DEFIP_ALPM_IPV4_1m].index_max = 1343 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_IPV4_1m).index_max / 2); 1344 sop->memState[L3_DEFIP_ALPM_IPV6_64m].index_max = 1345 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_IPV6_64m).index_max / 2); 1346 sop->memState[L3_DEFIP_ALPM_IPV6_64_1m].index_max = 1347 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_IPV6_64_1m).index_max / 2); 1348 sop->memState[L3_DEFIP_ALPM_IPV6_128m].index_max = 1349 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_IPV6_128m).index_max / 2); 1350 sop->memState[L3_DEFIP_ALPM_HIT_ONLYm].index_max = 1351 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_HIT_ONLYm).index_max / 2); 1352 sop->memState[L3_DEFIP_ALPM_ECCm].index_max = 1353 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_ECCm).index_max / 2); 1354 } 1355 } else { 1356 sop->memState[L3_DEFIP_ALPM_RAWm].index_max = -1; 1357 sop->memState[L3_DEFIP_ALPM_IPV4m].index_max = -1; 1358 sop->memState[L3_DEFIP_ALPM_IPV4_1m].index_max = -1; 1359 sop->memState[L3_DEFIP_ALPM_IPV6_64m].index_max = -1; 1360 sop->memState[L3_DEFIP_ALPM_IPV6_64_1m].index_max = -1; 1361 sop->memState[L3_DEFIP_ALPM_IPV6_128m].index_max = -1; 1362 sop->memState[L3_DEFIP_ALPM_HIT_ONLYm].index_max = -1; 1363 sop->memState[L3_DEFIP_ALPM_ECCm].index_max = -1; 1364 } 1365 1366 } else if (SOC_BOND_INFO_FEATURE_GET(unit, socBondInfoFeatureUft256k)) { 1367 shared_bank_size = 64; 1368 uft_size = shared_bank_size * 4; 1369 max_l2_entries = min_l2_entries + uft_size; 1370 max_l3_entries = min_l3_entries + uft_size; 1371 1372 cfg_l2_entries = soc_property_get(unit, spn_L2_MEM_ENTRIES, -1); 1373 l2_entries = cfg_l2_entries == -1 ? min_l2_entries * 1024 : cfg_l2_entries; 1374 1375 if (l2_entries <= min_l2_entries * 1024) { /* Min table size */ 1376 l2_entries = min_l2_entries * 1024; 1377 shared_l2_banks = 0; 1378 } else if (l2_entries <= max_l2_entries * 1024) { 1379 l2_entries -= min_l2_entries * 1024; 1380 shared_l2_banks = (l2_entries + (shared_bank_size * 1024 - 1)) / (shared_bank_size * 1381 1024); 1382 l2_entries = min_l2_entries * 1024 + shared_l2_banks * shared_bank_size * 1024; 1383 } else { 1384 LOG_CLI((BSL_META_U(unit, 1385 "The specified l2_mem_entries (%d) exceeds 144K\n"), 1386 cfg_l2_entries)); 1387 return SOC_E_PARAM; 1388 } 1389 1390 cfg_l3_entries = soc_property_get(unit, spn_L3_MEM_ENTRIES, -1); 1391 l3_entries = cfg_l3_entries == -1 ? (min_l3_entries * 1024 ) : cfg_l3_entries; 1392 if (l3_entries <= min_l3_entries * 1024) { /* 4k dedicated L3 entries */ 1393 l3_entries = min_l3_entries * 1024; 1394 shared_l3_banks = 0; 1395 } else if (l3_entries <= max_l3_entries * 1024) { 1396 l3_entries -= min_l3_entries * 1024; 1397 shared_l3_banks = (l3_entries + (shared_bank_size * 1024 - 1)) / (shared_bank_size * 1398 1024); 1399 l3_entries = min_l3_entries * 1024 + shared_l3_banks * shared_bank_size * 1024; 1400 } else { 1401 LOG_CLI((BSL_META_U(unit, 1402 "The specified l3_mem_entries (%d) exceeds 132k\n"), 1403 cfg_l3_entries)); 1404 return SOC_E_PARAM; 1405 } 1406 1407 1408 alpm_enable = soc_property_get(unit, spn_L3_ALPM_ENABLE, 0); 1409 if (alpm_enable && soc_feature(unit, soc_feature_alpm)) { 1410 1411 if (shared_l2_banks + shared_l3_banks > 2) { 1412 LOG_CLI((BSL_META_U(unit, 1413 "A minimum of 2 shared banks is required for ALPM " 1414 "when it is enabled\n"))); 1415 return SOC_E_PARAM; 1416 } 1417 } else if (shared_l2_banks + shared_l3_banks > 4) { 1418 return SOC_E_PARAM; 1419 } 1420 1421 sop->memState[L2Xm].index_max = l2_entries - 1; 1422 sop->memState[L2_ENTRY_ONLYm].index_max = l2_entries - 1; 1423 sop->memState[L2_ENTRY_ONLY_ECCm].index_max = l2_entries - 1; 1424 sop->memState[L2_HITDA_ONLYm].index_max = l2_entries / 4 - 1; 1425 sop->memState[L2_HITSA_ONLYm].index_max = l2_entries / 4 - 1; 1426 sop->memState[L2_ENTRY_LPm].index_max = min_l2_entries*1024 / 4 - 1; 1427 sop->memState[L2_ENTRY_ISS_LPm].index_max = 1428 (l2_entries - min_l2_entries*1024) / 4 - 1; 1429 1430 /* Adjust L3 table size */ 1431 sop->memState[L3_ENTRY_ONLYm].index_max = l3_entries - 1; 1432 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = l3_entries - 1; 1433 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = l3_entries / 2 - 1; 1434 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = l3_entries/ 2 - 1; 1435 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = l3_entries / 4 - 1; 1436 sop->memState[L3_ENTRY_ONLY_ECCm].index_max = l3_entries - 1; 1437 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = l3_entries / 4 - 1; 1438 sop->memState[L3_ENTRY_LPm].index_max = min_l3_entries*1024 / 4 - 1; 1439 sop->memState[L3_ENTRY_ISS_LPm].index_max = 1440 (l3_entries - min_l3_entries*1024) / 4 - 1; 1441 1442 /* Adjust ALPM table size */ 1443 if (alpm_enable) { 1444 /* The check below is sufficient because if ALPM mode is enabled 1445 * and number of shared banks used is > 2 we return SOC_E_PARAM 1446 * in code at the top of this function. 1447 */ 1448 if (shared_l2_banks + shared_l3_banks > 0) { 1449 sop->memState[L3_DEFIP_ALPM_RAWm].index_max = 1450 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_RAWm).index_max / 2); 1451 sop->memState[L3_DEFIP_ALPM_IPV4m].index_max = 1452 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_IPV4m).index_max / 2); 1453 sop->memState[L3_DEFIP_ALPM_IPV4_1m].index_max = 1454 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_IPV4_1m).index_max / 2); 1455 sop->memState[L3_DEFIP_ALPM_IPV6_64m].index_max = 1456 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_IPV6_64m).index_max / 2); 1457 sop->memState[L3_DEFIP_ALPM_IPV6_64_1m].index_max = 1458 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_IPV6_64_1m).index_max / 2); 1459 sop->memState[L3_DEFIP_ALPM_IPV6_128m].index_max = 1460 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_IPV6_128m).index_max / 2); 1461 sop->memState[L3_DEFIP_ALPM_HIT_ONLYm].index_max = 1462 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_HIT_ONLYm).index_max / 2); 1463 sop->memState[L3_DEFIP_ALPM_ECCm].index_max = 1464 (SOC_MEM_INFO(unit, L3_DEFIP_ALPM_ECCm).index_max / 2); 1465 } 1466 } else { 1467 sop->memState[L3_DEFIP_ALPM_RAWm].index_max = -1; 1468 sop->memState[L3_DEFIP_ALPM_IPV4m].index_max = -1; 1469 sop->memState[L3_DEFIP_ALPM_IPV4_1m].index_max = -1; 1470 sop->memState[L3_DEFIP_ALPM_IPV6_64m].index_max = -1; 1471 sop->memState[L3_DEFIP_ALPM_IPV6_64_1m].index_max = -1; 1472 sop->memState[L3_DEFIP_ALPM_IPV6_128m].index_max = -1; 1473 sop->memState[L3_DEFIP_ALPM_HIT_ONLYm].index_max = -1; 1474 sop->memState[L3_DEFIP_ALPM_ECCm].index_max = -1; 1475 } 1476 } 1477 return SOC_E_NONE; 1478 } 1479 #endif /* BCM_ESW_SUPPORT && BCM_IPROC_SUPPORT */ 1480 1481 1482 1483 /* 1484 * Function: 1485 * soc_info_config 1486 * Parameters: 1487 * unit - Unit number 1488 * soc - soc_control_t associated with this unit 1489 * Purpose: 1490 * Fill in soc_info structure for a newly attached unit. 1491 * Generates bitmaps and various arrays based on block and 1492 * ports that the hardware has enabled. 1493 * 1494 * This isn't STATIC so that pcid can get at it. 1495 */ 1496 1497 int 1498 soc_info_config(int unit, soc_control_t *soc) 1499 { 1500 soc_info_t *si; 1501 soc_pbmp_t pbmp_valid; 1502 soc_pbmp_t pbmp_xport_xe; 1503 soc_pbmp_t pbmp_xport_ge; 1504 soc_pbmp_t pbmp_gport_fe; 1505 soc_pbmp_t pbmp_xport_cpri; 1506 soc_pbmp_t pbmp_roe_compression; 1507 soc_pbmp_t pbmp_gport_stack; /* GE port in Higig Lite mode */ 1508 soc_pbmp_t pbmp_gx25g; /* GX port 24 Gbps capable */ 1509 soc_pbmp_t pbmp_gx21g; /* GX port 21 Gbps capable */ 1510 soc_pbmp_t pbmp_gx20g; /* GX port 20 Gbps capable */ 1511 soc_pbmp_t pbmp_gx16g; /* GX port 16 Gbps capable */ 1512 soc_pbmp_t pbmp_gx13g; /* GX port 13 Gbps capable */ 1513 soc_pbmp_t pbmp_gx12g; /* GX port 12 Gbps capable */ 1514 soc_pbmp_t pbmp_mxq; /* MXQ port */ 1515 soc_pbmp_t pbmp_mxq1g; /* MXQ port 1 Gbps capable */ 1516 soc_pbmp_t pbmp_mxq2p5g; /* MXQ port 2.5 Gbps capable */ 1517 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 1518 soc_pbmp_t pbmp_mxq10g; /* MXQ port 10 Gbps capable */ 1519 #endif /* (BCM_KATANA_SUPPORT) || (BCM_KATANA2_SUPPORT) */ 1520 soc_pbmp_t pbmp_mxq13g; /* MXQ port 13 Gbps capable */ 1521 soc_pbmp_t pbmp_mxq21g; /* MXQ port 20,21 Gbps capable */ 1522 #if defined(BCM_SHADOW_SUPPORT) || defined(BCM_SABER2_SUPPORT) 1523 soc_pbmp_t pbmp_xl; /* XL port */ 1524 #if defined(BCM_SABER2_SUPPORT) 1525 soc_pbmp_t pbmp_xl1g; /* XL port 1 Gbps capable */ 1526 soc_pbmp_t pbmp_xl2p5g; /* XL port 2.5 Gbps capable */ 1527 #endif 1528 soc_pbmp_t pbmp_xl10g; /* XL port 10 Gbps capable */ 1529 #endif 1530 #ifdef BCM_SHADOW_SUPPORT 1531 soc_pbmp_t pbmp_xl40g; /* XL port 40 Gbps capable */ 1532 soc_pbmp_t pbmp_xl12g; /* XL port 12 Gbps capable (SCH) */ 1533 #endif /* BCM_SHADOW_SUPPORT */ 1534 #if defined(BCM_METROLITE_SUPPORT) 1535 ml_pbmp_t ml_pbmp = {0}; 1536 soc_pbmp_t pbmp_pp_unsed; 1537 #endif 1538 soc_pbmp_t pbmp_xg2p5g; /* XG port 2.5 Gbps capable */ 1539 soc_pbmp_t pbmp_xq10g; /* XQ port 10 Gbps capable */ 1540 soc_pbmp_t pbmp_xq12g; /* XQ port 12 Gbps capable */ 1541 soc_pbmp_t pbmp_xq13g; /* XQ port 13 Gbps capable */ 1542 soc_pbmp_t pbmp_xq2p5g; /* XQ port 2.5 Gbps capable */ 1543 soc_pbmp_t pbmp_xq; /* XQ port (any type) */ 1544 soc_pbmp_t pbmp_hyplite; /* Hyperlite port */ 1545 soc_pbmp_t pbmp_tmp; 1546 soc_pbmp_t pbmp_disabled; /* forcefully disabled ports */ 1547 soc_pbmp_t pbmp_pp; /* Packet Processing Port */ 1548 uint16 dev_id; 1549 uint8 rev_id; 1550 uint16 drv_dev_id; 1551 uint8 drv_rev_id; 1552 int port, phy_port, max_port, blk, bindex, pno=0, mem; 1553 char *bname, *old_bname; 1554 int blktype, old_blktype, port_idx, instance; 1555 char instance_string[3]; 1556 #ifdef BCM_HURRICANE_SUPPORT 1557 int dxgxs = 0; 1558 uint32 regval; 1559 #endif /* BCM_HURRICANE_SUPPORT */ 1560 #ifdef BCM_KATANA_SUPPORT 1561 int kt_mxqport_index=0; 1562 int kt_mxqport2[4]={27,32,33,34}; 1563 #endif /* BCM_KATANA_SUPPORT */ 1564 #ifdef BCM_KATANA2_SUPPORT 1565 int mxq7_blk=0; 1566 /* Just keeping below for informatory for short duration */ 1567 #if 0 1568 int kt2_mxqport_num=0; 1569 int kt2_mxqport_index=0; 1570 int kt2_mxqports_list[10][4]={ 1571 { 1, 2, 3, 4}, /* MXQPORT0 */ 1572 { 5, 6, 7, 8}, /* MXQPORT1 */ 1573 { 9,10,11,12}, /* MXQPORT2 */ 1574 {13,14,15,16}, /* MXQPORT3 */ 1575 {17,18,19,20}, /* MXQPORT4 */ 1576 {21,22,23,24}, /* MXQPORT5 */ 1577 {25,35,36,37}, /* MXQPORT6 */ 1578 {26,38,39,40}, /* MXQPORT7 */ 1579 {27,32,33,34}, /* MXQPORT8 */ 1580 {28,29,30,31} /* MXQPORT9 */ 1581 }; 1582 #endif 1583 kt2_pbmp_t kt2_pbmp={0}; 1584 #endif /* BCM_KATANA2_SUPPORT */ 1585 #if defined(BCM_SABER2_SUPPORT) 1586 sb2_pbmp_t sb2_pbmp={0}; 1587 #endif 1588 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) \ 1589 || defined(BCM_TRIDENT2_SUPPORT) 1590 int rv = 0; 1591 #endif 1592 #if defined(BCM_TOMAHAWK_SUPPORT) 1593 static int latency[SOC_MAX_NUM_DEVICES] = {0}; 1594 #endif 1595 1596 si = &soc->info; 1597 sal_memset((void *)si, 0, sizeof(soc_info_t)); 1598 1599 soc_cm_get_id(unit, &dev_id, &rev_id); 1600 soc_cm_get_id_driver(dev_id, rev_id, &drv_dev_id, &drv_rev_id); 1601 1602 si->driver_type = soc->chip_driver->type; 1603 si->driver_group = soc_chip_type_map[si->driver_type]; 1604 si->num_cpu_cosq = 8; 1605 si->num_mmu_base_cosq = 0; 1606 si->modid_count = 1; 1607 si->modid_max = 31; /* See SOC_MODID_MAX(unit) */ 1608 si->modport_max = 31; 1609 si->modport_max_first = -1; 1610 si->trunk_bit_pos = 5; /* 6th bit from right. See SOC_TRUNK_BIT_POS(unit) */ 1611 si->port_addr_max = 31; 1612 si->vlan_xlate_glp_wildcard = 0x3fff; /* For most chips it is 3fff but can vary */ 1613 si->cpu_hg_index = -1; 1614 si->cpu_hg_pp_port_index = -1; 1615 si->port_class_max = 64; /* By default 64 classes are supported */ 1616 si->num_flex_ingress_pools = 0; 1617 si->num_flex_egress_pools = 0; 1618 si->size_flex_ingress_pool = 0; 1619 si->size_flex_egress_pool = 0; 1620 si->pcie_phy_addr = 0; 1621 si->sflow_range_max = 24; 1622 si->nat_id_max = 2048; 1623 si->fp_hg_port_offset = -1; 1624 1625 si->max_mtu = 16360; 1626 1627 SOC_PBMP_CLEAR(pbmp_xport_xe); 1628 SOC_PBMP_CLEAR(pbmp_xport_cpri); 1629 SOC_PBMP_CLEAR(pbmp_xport_ge); 1630 SOC_PBMP_CLEAR(pbmp_gport_fe); 1631 SOC_PBMP_CLEAR(pbmp_roe_compression); 1632 SOC_PBMP_CLEAR(pbmp_gport_stack); 1633 SOC_PBMP_CLEAR(pbmp_disabled); 1634 SOC_PBMP_CLEAR(pbmp_pp); 1635 SOC_PBMP_CLEAR(si->linkphy_pbm); 1636 SOC_PBMP_CLEAR(si->lp.bitmap); 1637 SOC_PBMP_CLEAR(si->subtag_pbm); 1638 SOC_PBMP_CLEAR(si->subtag.bitmap); 1639 SOC_PBMP_CLEAR(si->subtag_allowed_pbm); 1640 SOC_PBMP_CLEAR(si->linkphy_allowed_pbm); 1641 SOC_PBMP_CLEAR(si->linkphy_pp_port_pbm); 1642 SOC_PBMP_CLEAR(si->subtag_pp_port_pbm); 1643 si->subtag_enabled = 0; 1644 si->linkphy_enabled = 0; 1645 1646 /* XGPORT is set to 1G if it is not included in one of the pbmp below */ 1647 SOC_PBMP_CLEAR(pbmp_xg2p5g); 1648 1649 /* XQPORT is set to 1G if it is not included in one of the pbmp below */ 1650 SOC_PBMP_CLEAR(pbmp_xq2p5g); 1651 SOC_PBMP_CLEAR(pbmp_xq10g); 1652 SOC_PBMP_CLEAR(pbmp_xq12g); 1653 SOC_PBMP_CLEAR(pbmp_xq13g); 1654 SOC_PBMP_CLEAR(pbmp_xq); 1655 1656 #if defined(BCM_SHADOW_SUPPORT) || defined(BCM_SABER2_SUPPORT) 1657 /* XLPORT is set to one of the pbmp below */ 1658 SOC_PBMP_CLEAR(pbmp_xl); 1659 SOC_PBMP_CLEAR(pbmp_xl10g); 1660 #endif 1661 #if defined(BCM_SHADOW_SUPPORT) 1662 SOC_PBMP_CLEAR(pbmp_xl12g); 1663 SOC_PBMP_CLEAR(pbmp_xl40g); 1664 #endif /* BCM_SHADOW_SUPPORT */ 1665 1666 /* GXPORT is set to 10G if it is not included in one of the pbmp below */ 1667 SOC_PBMP_CLEAR(pbmp_gx12g); 1668 SOC_PBMP_CLEAR(pbmp_gx13g); 1669 SOC_PBMP_CLEAR(pbmp_gx16g); 1670 SOC_PBMP_CLEAR(pbmp_gx20g); 1671 SOC_PBMP_CLEAR(pbmp_gx21g); 1672 SOC_PBMP_CLEAR(pbmp_gx25g); 1673 SOC_PBMP_CLEAR(pbmp_mxq); 1674 SOC_PBMP_CLEAR(pbmp_mxq1g); 1675 SOC_PBMP_CLEAR(pbmp_mxq2p5g); 1676 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 1677 SOC_PBMP_CLEAR(pbmp_mxq10g); 1678 #endif /* defined(BCM_KATANA_SUPPORT) || (BCM_KATANA2_SUPPORT) */ 1679 SOC_PBMP_CLEAR(pbmp_mxq13g); 1680 SOC_PBMP_CLEAR(pbmp_mxq21g); 1681 #if defined(BCM_SABER2_SUPPORT) 1682 SOC_PBMP_CLEAR(pbmp_xl1g); 1683 SOC_PBMP_CLEAR(pbmp_xl2p5g); 1684 #endif 1685 1686 SOC_PBMP_CLEAR(si->s_pbm); /* 10/100/1000/2500 Mbps comboserdes */ 1687 SOC_PBMP_CLEAR(si->gmii_pbm); 1688 SOC_PBMP_CLEAR(si->lb_pbm); 1689 SOC_PBMP_CLEAR(si->mmu_pbm); 1690 SOC_PBMP_CLEAR(pbmp_hyplite); 1691 1692 SOC_PBMP_CLEAR(si->pbm_ext_mem); 1693 for (port = 0; port < SOC_MAX_NUM_PORTS; port++) { 1694 si->max_port_p2m_mapping[port] = -1; 1695 } 1696 1697 si->num_pipe = 1; 1698 /* mmu_lossless will be updated by chip init code, wherever applicable */ 1699 si->mmu_lossless = -1; 1700 1701 /* 1702 * Used to implement the SOC_IS_*(unit) macros 1703 */ 1704 switch (drv_dev_id) { 1705 #if defined(BCM_HERCULES_SUPPORT) 1706 case BCM5675_DEVICE_ID: 1707 si->chip = SOC_INFO_CHIP_HERCULES15; 1708 soc->base_modid = -1; 1709 si->modid_count = 0; 1710 break; 1711 #endif /* BCM_HERCULES_SUPPORT */ 1712 case BCM56102_DEVICE_ID: 1713 si->chip = SOC_INFO_CHIP_FHX; 1714 si->chip_type = SOC_INFO_CHIP_TYPE_FELIX; 1715 SOC_PBMP_WORD_SET(pbmp_gport_fe, 0, 0x00ffffff); 1716 si->modid_max = 63; 1717 si->hg_offset = 24; /* SOC_HG_OFFSET */ 1718 break; 1719 case BCM56304_DEVICE_ID: 1720 si->chip = SOC_INFO_CHIP_FHX; 1721 si->chip_type = SOC_INFO_CHIP_TYPE_HELIX; 1722 si->modid_max = 63; 1723 si->hg_offset = 24; /* SOC_HG_OFFSET */ 1724 break; 1725 case BCM56112_DEVICE_ID: 1726 si->chip = SOC_INFO_CHIP_FHX; 1727 si->chip_type = SOC_INFO_CHIP_TYPE_FELIX15; 1728 SOC_PBMP_WORD_SET(pbmp_gport_fe, 0, 0x00ffffff); 1729 si->modid_max = 63; 1730 si->hg_offset = 24; /* SOC_HG_OFFSET */ 1731 break; 1732 case BCM56314_DEVICE_ID: 1733 si->chip = SOC_INFO_CHIP_FHX; 1734 si->chip_type = SOC_INFO_CHIP_TYPE_HELIX15; 1735 si->modid_max = 63; 1736 si->hg_offset = 24; /* SOC_HG_OFFSET */ 1737 break; 1738 case BCM56504_DEVICE_ID: 1739 si->chip = SOC_INFO_CHIP_FIREBOLT; 1740 si->modid_max = 63; 1741 si->hg_offset = 24; /* SOC_HG_OFFSET */ 1742 break; 1743 case BCM56800_DEVICE_ID: 1744 switch (dev_id) { 1745 case BCM56580_DEVICE_ID: 1746 si->chip = SOC_INFO_CHIP_GOLDWING; 1747 SOC_CHIP_STRING(unit) = "goldwing"; 1748 break; 1749 case BCM56700_DEVICE_ID: 1750 case BCM56701_DEVICE_ID: 1751 si->chip = SOC_INFO_CHIP_HUMV; 1752 SOC_CHIP_STRING(unit) = "humv"; 1753 break; 1754 default: 1755 si->chip = SOC_INFO_CHIP_BRADLEY; 1756 break; 1757 } 1758 si->modid_max = 127; 1759 si->num_cpu_cosq = 16; 1760 break; 1761 #if defined(BCM_RAPTOR_SUPPORT) 1762 case BCM56218_DEVICE_ID: 1763 si->chip = SOC_INFO_CHIP_RAPTOR; 1764 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, 0x00000006); 1765 SOC_PBMP_WORD_SET(si->s_pbm, 0, 0x00000006); 1766 SOC_PBMP_WORD_SET(si->hg2_pbm, 0, 0x00000006); 1767 SOC_PBMP_WORD_SET(si->gmii_pbm, 0, 0x00000008); 1768 si->modid_max = 15; /* See SOC_MODID_MAX(unit) */ 1769 /* 7th bit from right. See SOC_TRUNK_BIT_POS(unit)*/ 1770 si->trunk_bit_pos = 6; 1771 si->port_addr_max = 63; 1772 si->hg_offset = 0; /* SOC_HG_OFFSET */ 1773 break; 1774 case BCM56224_DEVICE_ID: 1775 si->chip = SOC_INFO_CHIP_RAVEN; 1776 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, 0x00000036); 1777 SOC_PBMP_WORD_SET(si->s_pbm, 0, 0x00000036); 1778 SOC_PBMP_WORD_SET(si->hg2_pbm, 0, 0x00000036); 1779 SOC_PBMP_WORD_SET(si->gmii_pbm, 0, 0x00000008); 1780 si->modid_max = 15; /* See SOC_MODID_MAX(unit) */ 1781 /* 7th bit from right. See SOC_TRUNK_BIT_POS(unit)*/ 1782 si->trunk_bit_pos = 6; 1783 si->port_addr_max = 63; 1784 si->hg_offset = 0; /* SOC_HG_OFFSET */ 1785 break; 1786 case BCM53312_DEVICE_ID: 1787 case BCM53313_DEVICE_ID: 1788 case BCM53314_DEVICE_ID: 1789 case BCM53322_DEVICE_ID: 1790 case BCM53323_DEVICE_ID: 1791 case BCM53324_DEVICE_ID: 1792 si->chip = SOC_INFO_CHIP_HAWKEYE; 1793 si->modid_max = 0; /* See SOC_MODID_MAX(unit) */ 1794 /* 7th bit from right. See SOC_TRUNK_BIT_POS(unit)*/ 1795 si->trunk_bit_pos = 6; 1796 si->port_addr_max = 31; 1797 si->hg_offset = 0; /* SOC_HG_OFFSET */ 1798 break; 1799 #endif /* BCM_RAPTOR_SUPPORT */ 1800 case BCM56514_DEVICE_ID: 1801 si->chip = SOC_INFO_CHIP_FIREBOLT2; 1802 si->modid_max = 63; 1803 si->hg_offset = 24; /* SOC_HG_OFFSET */ 1804 break; 1805 case BCM56624_DEVICE_ID: 1806 SOC_PBMP_WORD_SET(si->s_pbm, 0, 0x00000002); 1807 si->chip = SOC_INFO_CHIP_TRIUMPH; 1808 si->modid_max = 127; /* See SOC_MODID_MAX(unit) */ 1809 si->hg_offset = 28; /* SOC_HG_OFFSET */ 1810 /* 1811 * 14th bit from right. See SOC_TRUNK_BIT_POS(unit) 1812 * Note that it is not together with port/trunk-id. 1813 */ 1814 si->trunk_bit_pos = 13; 1815 si->port_addr_max = 63; 1816 si->num_cpu_cosq = 48; 1817 if (soc_property_get(unit, spn_MODULE_64PORTS, 0)) { 1818 si->modport_max = 63; 1819 } else { 1820 /* Adjust modid count based on dual-modid config parameter settings. 1821 * By default, dual-modid is enabled (32-port module mode) to allow 1822 * compatibility with other devices. 1823 */ 1824 si->modid_count = 2; 1825 } 1826 break; 1827 case BCM56680_DEVICE_ID: 1828 SOC_PBMP_WORD_SET(si->s_pbm, 0, 0x00000002); 1829 si->chip = SOC_INFO_CHIP_VALKYRIE; 1830 si->modid_max = 127; /* See SOC_MODID_MAX(unit) */ 1831 si->hg_offset = 28; /* SOC_HG_OFFSET */ 1832 /* 1833 * 14th bit from right. See SOC_TRUNK_BIT_POS(unit) 1834 * Note that it is not together with port/trunk-id. 1835 */ 1836 si->trunk_bit_pos = 13; 1837 si->port_addr_max = 63; 1838 si->num_cpu_cosq = 48; 1839 if (soc_property_get(unit, spn_MODULE_64PORTS, 0)) { 1840 si->modport_max = 63; 1841 } else { 1842 /* Adjust modid count based on dual-modid config parameter settings. 1843 * By default, dual-modid is enabled (32-port module mode) to allow 1844 * compatibility with other devices. 1845 */ 1846 si->modid_count = 2; 1847 } 1848 break; 1849 case BCM56820_DEVICE_ID: 1850 si->chip = SOC_INFO_CHIP_SCORPION; 1851 si->modid_max = 255; 1852 si->port_addr_max = 63; 1853 si->num_cpu_cosq = 32; 1854 si->trunk_bit_pos = 14; 1855 si->vlan_xlate_glp_wildcard = 0x7fff; /* glp wildcard value */ 1856 si->sflow_range_max = 16; 1857 /* SOC_HG_OFFSET = 0, default */ 1858 break; 1859 case BCM56725_DEVICE_ID: 1860 si->chip = SOC_INFO_CHIP_CONQUEROR; 1861 si->modid_max = 255; 1862 si->port_addr_max = 63; 1863 si->num_cpu_cosq = 32; 1864 si->trunk_bit_pos = 14; 1865 si->vlan_xlate_glp_wildcard = 0x7fff; /* glp wildcard value */ 1866 /* SOC_HG_OFFSET = 0, default */ 1867 break; 1868 case BCM56634_DEVICE_ID: 1869 SOC_PBMP_WORD_SET(si->s_pbm, 0, 0x00000002); 1870 SOC_PBMP_WORD_SET(si->lb_pbm, 1, 0x00400000); 1871 si->lb_port = 54; 1872 SOC_PBMP_WORD_SET(si->mmu_pbm, 1, 0x01800000); 1873 si->chip = SOC_INFO_CHIP_TRIUMPH2; 1874 si->modid_max = 127; /* See SOC_MODID_MAX(unit) */ 1875 si->hg_offset = 26; /* SOC_HG_OFFSET */ 1876 /* 1877 * 14th bit from right. See SOC_TRUNK_BIT_POS(unit) 1878 * Note that it is not together with port/trunk-id. 1879 */ 1880 si->trunk_bit_pos = 13; 1881 si->port_addr_max = 63; 1882 si->num_cpu_cosq = 48; 1883 if (soc_property_get(unit, spn_MODULE_64PORTS, 0)) { 1884 si->modport_max = 63; 1885 } else { 1886 /* Adjust modid count based on dual-modid config parameter settings. 1887 * By default, dual-modid is enabled (32-port module mode) to allow 1888 * compatibility with other devices. 1889 */ 1890 si->modid_count = 2; 1891 } 1892 si->num_time_interface = 1; 1893 switch (dev_id) { 1894 case BCM56634_DEVICE_ID: 1895 case BCM56538_DEVICE_ID: 1896 if (soc_property_get(unit, spn_BCM56634_48G_4X12, 0) || 1897 soc_property_get(unit, spn_BCM56634_48G_2X24, 0) || 1898 soc_property_get(unit, spn_BCM56538_48G_4X12, 0) || 1899 soc_property_get(unit, spn_BCM56538_48G_2X24, 0)) { 1900 si->internal_loopback = 1; 1901 } else { 1902 si->internal_loopback = 0; 1903 } 1904 break; 1905 case BCM56636_DEVICE_ID: 1906 if (soc_property_get(unit, spn_BCM56636_24G_6X12, 0) || 1907 soc_property_get(unit, spn_BCM56636_2X12_2X24, 0)) { 1908 si->internal_loopback = 1; 1909 } else { 1910 si->internal_loopback = 0; 1911 } 1912 break; 1913 case BCM56638_DEVICE_ID: 1914 if (soc_property_get(unit, spn_BCM56638_8X12, 0) || 1915 soc_property_get(unit, spn_BCM56638_4X12_2X24, 0)) { 1916 si->internal_loopback = 1; 1917 } else { 1918 si->internal_loopback = 0; 1919 } 1920 break; 1921 default: 1922 si->internal_loopback = 1; 1923 break; 1924 } 1925 break; 1926 case BCM56524_DEVICE_ID: 1927 SOC_PBMP_WORD_SET(si->lb_pbm, 1, 0x00400000); 1928 si->lb_port = 54; 1929 SOC_PBMP_WORD_SET(si->mmu_pbm, 1, 0x01800000); 1930 si->chip = SOC_INFO_CHIP_APOLLO; 1931 si->modid_max = 127; /* See SOC_MODID_MAX(unit) */ 1932 si->hg_offset = 26; /* SOC_HG_OFFSET */ 1933 /* 1934 * 14th bit from right. See SOC_TRUNK_BIT_POS(unit) 1935 * Note that it is not together with port/trunk-id. 1936 */ 1937 si->trunk_bit_pos = 13; 1938 si->port_addr_max = 63; 1939 si->num_cpu_cosq = 48; 1940 if (soc_property_get(unit, spn_MODULE_64PORTS, 0)) { 1941 si->modport_max = 63; 1942 } else { 1943 /* Adjust modid count based on dual-modid config parameter settings. 1944 * By default, dual-modid is enabled (32-port module mode) to allow 1945 * compatibility with other devices. 1946 */ 1947 si->modid_count = 2; 1948 } 1949 si->num_time_interface = 1; 1950 si->internal_loopback = 1; 1951 break; 1952 case BCM56685_DEVICE_ID: 1953 SOC_PBMP_WORD_SET(si->lb_pbm, 1, 0x00400000); 1954 si->lb_port = 54; 1955 SOC_PBMP_WORD_SET(si->mmu_pbm, 1, 0x01800000); 1956 si->chip = SOC_INFO_CHIP_VALKYRIE2; 1957 si->modid_max = 127; /* See SOC_MODID_MAX(unit) */ 1958 si->hg_offset = 26; /* SOC_HG_OFFSET */ 1959 /* 1960 * 14th bit from right. See SOC_TRUNK_BIT_POS(unit) 1961 * Note that it is not together with port/trunk-id. 1962 */ 1963 si->trunk_bit_pos = 13; 1964 si->port_addr_max = 63; 1965 si->num_cpu_cosq = 48; 1966 if (soc_property_get(unit, spn_MODULE_64PORTS, 0)) { 1967 si->modport_max = 63; 1968 } else { 1969 /* Adjust modid count based on dual-modid config parameter settings. 1970 * By default, dual-modid is enabled (32-port module mode) to allow 1971 * compatibility with other devices. 1972 */ 1973 si->modid_count = 2; 1974 } 1975 si->num_time_interface = 1; 1976 si->internal_loopback = 1; 1977 break; 1978 #if defined(BCM_ENDURO_SUPPORT) 1979 case BCM56132_DEVICE_ID: 1980 case BCM56134_DEVICE_ID: 1981 case BCM56331_DEVICE_ID: 1982 case BCM56333_DEVICE_ID: 1983 case BCM56334_DEVICE_ID: 1984 case BCM56320_DEVICE_ID: 1985 case BCM56321_DEVICE_ID: 1986 case BCM56338_DEVICE_ID: 1987 case BCM56230_DEVICE_ID: 1988 case BCM56231_DEVICE_ID: 1989 if(dev_id == BCM56338_DEVICE_ID) { 1990 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, 0xc000000); 1991 } else if(dev_id == BCM56132_DEVICE_ID) { 1992 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, 0x30000000); 1993 } else if((dev_id == BCM56334_DEVICE_ID) || (dev_id == BCM56320_DEVICE_ID) || 1994 (dev_id == BCM56321_DEVICE_ID)){ 1995 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, 0x3c000000); 1996 } 1997 /* SOC_PBMP_WORD_SET(si->s_pbm, 0, 0x00000002); 1998 SOC_PBMP_WORD_SET(si->mmu_pbm, 1, 0x01800000); */ 1999 SOC_PBMP_WORD_SET(si->lb_pbm, 0, 0x00000002); 2000 si->chip = SOC_INFO_CHIP_ENDURO; 2001 si->modid_max = 63; /* See SOC_MODID_MAX(unit) */ 2002 si->hg_offset = 26; /* SOC_HG_OFFSET */ 2003 /* 2004 * 14th bit from right. See SOC_TRUNK_BIT_POS(unit) 2005 * Note that it is not together with port/trunk-id. 2006 */ 2007 si->trunk_bit_pos = 13; 2008 /* 2009 * Note that maximum port number for enduro is 32. But port_addr_max 2010 * is defined as 63 to make enduro compatible to other TRX families. 2011 */ 2012 si->port_addr_max = 63; 2013 si->num_cpu_cosq = 48; 2014 si->internal_loopback = 1; 2015 si->num_time_interface = 1; 2016 si->fp_hg_port_offset = 4; 2017 break; 2018 #endif /* BCM_ENDURO_SUPPORT */ 2019 2020 #ifdef BCM_SHADOW_SUPPORT 2021 case BCM88732_DEVICE_ID: 2022 si->chip = SOC_INFO_CHIP_SHADOW; 2023 si->modid_max = 255; 2024 si->port_addr_max = 63; 2025 si->num_cpu_cosq = 32; 2026 si->trunk_bit_pos = 14; 2027 si->pcie_phy_addr = 0x9a; 2028 break; 2029 #endif /* BCM_SHAODOW_SUPPORT */ 2030 2031 #if defined(BCM_HURRICANE_SUPPORT) 2032 case BCM56140_DEVICE_ID: 2033 case BCM56142_DEVICE_ID: 2034 case BCM56143_DEVICE_ID: 2035 case BCM56144_DEVICE_ID: 2036 case BCM56146_DEVICE_ID: 2037 case BCM56147_DEVICE_ID: 2038 case BCM56149_DEVICE_ID: 2039 /* Read DXGXS input */ 2040 if (SAL_BOOT_PLISIM) { 2041 dxgxs=1; 2042 } else { 2043 /* At this point, Endianness may or may not be configured. Compensate for it */ 2044 soc_pci_getreg(unit, soc_reg_addr(unit, CMIC_MISC_STATUSr, 0, 0), ®val); 2045 if ((CMVEC(unit).big_endian_pio ? 1 : 0) != 2046 ((soc_pci_read(unit, CMIC_ENDIAN_SELECT) & ES_BIG_ENDIAN_PIO) ? 1 : 0) ) 2047 { 2048 dxgxs = (regval & 0x01000000) ? 1 : 0; 2049 } else { 2050 dxgxs = (regval & 0x01) ? 1 : 0; 2051 } 2052 } 2053 SOC_PBMP_CLEAR(pbmp_gport_stack); 2054 if(dev_id == BCM56142_DEVICE_ID) { 2055 if (soc_property_get(unit, spn_BCM5614X_CONFIG, 1) == 0) { 2056 /* Full Capacity (24x1G + 4xHGd) for testing */ 2057 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, 0x3c000000); 2058 } else if (soc_property_get(unit, spn_BCM5614X_CONFIG, 1) == 2) { 2059 /* 24x1G + 2xHG[13] */ 2060 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, 0x14000000); 2061 } else { 2062 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, dxgxs ? 0x34000000 : 0x1c000000); 2063 } 2064 } else if(dev_id == BCM56143_DEVICE_ID) { 2065 if (!soc_property_get(unit, spn_BCM5614X_CONFIG, 0)) { 2066 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, dxgxs ? 0x0c000000 : 0x30000000); 2067 } 2068 } 2069 2070 si->chip = SOC_INFO_CHIP_HURRICANE; 2071 si->modid_max = 63; /* See SOC_MODID_MAX(unit) */ 2072 si->hg_offset = 26; /* SOC_HG_OFFSET */ 2073 /* 2074 * 14th bit from right. See SOC_TRUNK_BIT_POS(unit) 2075 * Note that it is not together with port/trunk-id. 2076 */ 2077 si->trunk_bit_pos = 13; 2078 /* 2079 * Note that maximum port number for hurricane is 32. But port_addr_max 2080 * is defined as 63 to make hurricane compatible to other TRX families. 2081 */ 2082 si->port_addr_max = 63; 2083 si->num_cpu_cosq = 8; 2084 si->internal_loopback = 0; 2085 si->num_time_interface = 1; 2086 si->fp_hg_port_offset = 4; 2087 break; 2088 #endif /* BCM_HURRICANE_SUPPORT */ 2089 2090 #if defined(BCM_HURRICANE2_SUPPORT) 2091 case BCM56150_DEVICE_ID: 2092 case BCM56151_DEVICE_ID: 2093 case BCM56152_DEVICE_ID: 2094 case BCM53342_DEVICE_ID: 2095 case BCM53343_DEVICE_ID: 2096 case BCM53344_DEVICE_ID: 2097 case BCM53346_DEVICE_ID: 2098 case BCM53347_DEVICE_ID: 2099 case BCM53333_DEVICE_ID: 2100 case BCM53334_DEVICE_ID: 2101 case BCM53393_DEVICE_ID: 2102 case BCM53394_DEVICE_ID: 2103 2104 si->chip = SOC_INFO_CHIP_HURRICANE2; 2105 si->modid_max = 63; /* See SOC_MODID_MAX(unit) */ 2106 si->hg_offset = 26; /* SOC_HG_OFFSET */ 2107 /* 2108 * 14th bit from right. See SOC_TRUNK_BIT_POS(unit) 2109 * Note that it is not together with port/trunk-id. 2110 */ 2111 si->trunk_bit_pos = 13; 2112 /* 2113 * Note that maximum port number for hurricane is 32. But port_addr_max 2114 * is defined as 63 to make hurricane compatible to other TRX families. 2115 */ 2116 si->port_addr_max = 63; 2117 si->num_cpu_cosq = 8; 2118 si->internal_loopback = 0; 2119 si->num_time_interface = 1; 2120 si->num_flex_ingress_pools = 8; 2121 si->num_flex_egress_pools = 8; 2122 si->pcie_phy_addr = 0x2; 2123 si->num_ucs = 1; 2124 si->fp_hg_port_offset = 4; 2125 #ifdef BCM_SBUSDMA_SUPPORT 2126 soc->max_sbusdma_channels = 3; 2127 #endif 2128 break; 2129 #endif /* BCM_HURRICANE2_SUPPORT */ 2130 2131 #if defined(BCM_GREYHOUND_SUPPORT) 2132 case BCM53400_DEVICE_ID: 2133 2134 si->chip_type = SOC_INFO_CHIP_TYPE_GREYHOUND; 2135 2136 si->modid_max = 63; /* See SOC_MODID_MAX(unit) */ 2137 si->hg_offset = 0; /* SOC_HG_OFFSET */ 2138 /* 2139 * 14th bit from right. See SOC_TRUNK_BIT_POS(unit) 2140 * Note that it is not together with port/trunk-id. 2141 */ 2142 si->trunk_bit_pos = 13; 2143 /* 2144 * Note that maximum port number for greyhound is 32. But port_addr_max 2145 * is defined as 63 to make greyhound compatible to other TRX families. 2146 */ 2147 si->port_addr_max = 63; 2148 si->num_cpu_cosq = 8; 2149 si->internal_loopback = 0; 2150 si->num_time_interface = 1; 2151 si->nof_pmqs = 1; 2152 si->num_ucs = 1; 2153 si->fp_hg_port_offset = 30; 2154 #ifdef BCM_SBUSDMA_SUPPORT 2155 soc->max_sbusdma_channels = 3; 2156 #endif 2157 if ((dev_id & 0xF000) == 0x8000) { 2158 if ((dev_id & 0x0060) != 0x0000) { /* Elkhound and Bloodhound */ 2159 if ((dev_id & 0x00F6) == 0x0054) { /* 53454/53455 */ 2160 dev_id &= 0xFFF4; /* use 53454 */ 2161 } 2162 if ((dev_id & 0x00F6) == 0x0056) { /* 53456/53457 */ 2163 dev_id &= 0xFFF6; /* use 53456 */ 2164 } 2165 /* no change on Bloodhound */ 2166 } else { 2167 dev_id &= 0xFF0F; 2168 } 2169 } 2170 break; 2171 #endif /* BCM_GREYHOUND_SUPPORT */ 2172 2173 #if defined(BCM_HURRICANE3_SUPPORT) 2174 case BCM56160_DEVICE_ID: 2175 case BCM53540_DEVICE_ID: 2176 si->chip_type = SOC_INFO_CHIP_TYPE_HURRICANE3; 2177 2178 if (soc_feature(unit, soc_feature_wh2)) { 2179 si->modid_max = 63; /* See SOC_MODID_MAX(unit) */ 2180 } else { 2181 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2182 } 2183 si->hg_offset = 0; /* SOC_HG_OFFSET */ 2184 /* 2185 * 14th bit from right. See SOC_TRUNK_BIT_POS(unit) 2186 * Note that it is not together with port/trunk-id. 2187 */ 2188 si->trunk_bit_pos = 14; 2189 /* 2190 * Note that maximum port number for hurricane is 32. But port_addr_max 2191 * is defined as 63 to make hurricane compatible to other TRX families. 2192 */ 2193 si->port_addr_max = 63; 2194 si->num_cpu_cosq = 8; 2195 si->internal_loopback = 0; 2196 si->num_time_interface = 1; 2197 si->nof_pmqs = 3; 2198 si->vlan_xlate_glp_wildcard = 0x7fff; 2199 si->fp_hg_port_offset = 32; 2200 si->num_ucs = 1; 2201 #ifdef BCM_SBUSDMA_SUPPORT 2202 soc->max_sbusdma_channels = 3; 2203 #endif 2204 break; 2205 #endif /* BCM_HURRICANE3_SUPPORT */ 2206 2207 #if defined(BCM_GREYHOUND2_SUPPORT) 2208 case BCM53570_DEVICE_ID: 2209 si->chip_type = SOC_INFO_CHIP_TYPE_GREYHOUND2; 2210 2211 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2212 si->hg_offset = 0; /* SOC_HG_OFFSET */ 2213 si->fp_hg_port_offset = 66; 2214 /* 2215 * 15th bit from right. See SOC_TRUNK_BIT_POS(unit) 2216 * Note that it is not together with port/trunk-id. 2217 */ 2218 si->trunk_bit_pos = 15; 2219 /* 2220 * Note that maximum port number for hurricane is 32. But port_addr_max 2221 * is defined as 63 to make hurricane compatible to other TRX families. 2222 */ 2223 si->port_addr_max = 127; 2224 si->num_cpu_cosq = 8; 2225 si->internal_loopback = 0; 2226 si->num_time_interface = 1; 2227 si->nof_pmqs = 5; 2228 si->num_ucs = 1; 2229 si->vlan_xlate_glp_wildcard = 0xffff; 2230 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2231 #ifdef BCM_SBUSDMA_SUPPORT 2232 soc->max_sbusdma_channels = 3; 2233 soc->tdma_ch = 0; 2234 soc->tslam_ch = 1; 2235 soc->desc_ch = 2; 2236 #endif 2237 break; 2238 #endif /* BCM_GREYHOUND2_SUPPORT */ 2239 2240 case BCM56840_DEVICE_ID: 2241 if (dev_id == BCM56745_DEVICE_ID || dev_id == BCM56743_DEVICE_ID || 2242 dev_id == BCM56746_DEVICE_ID || dev_id == BCM56744_DEVICE_ID || 2243 dev_id == BCM56742_DEVICE_ID) { 2244 si->chip = SOC_INFO_CHIP_TITAN; 2245 } else { 2246 si->chip = SOC_INFO_CHIP_TRIDENT; 2247 } 2248 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2249 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2250 si->num_pipe = 2; 2251 /* si->hg_offset = 0; SOC_HG_OFFSET */ 2252 /* 2253 * 16th bit from right. See SOC_TRUNK_BIT_POS(unit) 2254 * Note that it is not together with port/trunk-id. 2255 */ 2256 si->trunk_bit_pos = 15; 2257 /* port_addr_max has to be 2^n -1 */ 2258 si->port_addr_max = 127; 2259 si->num_cpu_cosq = 48; 2260 si->pcie_phy_addr = 0xfa; 2261 if (soc_property_get(unit, spn_MODULE_64PORTS, 0)) { 2262 /* Use this property as single modid indicator for now */ 2263 si->modport_max = 127; 2264 } else { 2265 /* By default, dual-modid is enabled (32-port module mode) to allow 2266 * compatibility with other devices. In this mode, port 64 will 2267 * not be globally addressable, however still allocate 3 modid 2268 * to allow using mod/port gport to address all ports. 2269 */ 2270 si->modid_count = 3; 2271 } 2272 si->num_time_interface = 1; 2273 si->vlan_xlate_glp_wildcard = 0xffff; /* glp wildcard value */ 2274 break; 2275 2276 #ifdef BCM_HELIX4_SUPPORT 2277 case BCM56548H_DEVICE_ID: 2278 case BCM56548_DEVICE_ID: 2279 case BCM56547_DEVICE_ID: 2280 case BCM56346_DEVICE_ID: 2281 case BCM56345_DEVICE_ID: 2282 case BCM56344_DEVICE_ID: 2283 case BCM56342_DEVICE_ID: 2284 case BCM56340_DEVICE_ID: 2285 case BCM56049_DEVICE_ID: 2286 case BCM56048_DEVICE_ID: 2287 case BCM56047_DEVICE_ID: 2288 case BCM56042_DEVICE_ID: 2289 case BCM56041_DEVICE_ID: 2290 case BCM56040_DEVICE_ID: 2291 si->chip = SOC_INFO_CHIP_HELIX4; 2292 si->chip_type = SOC_INFO_CHIP_TYPE_HELIX4; 2293 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2294 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2295 /* si->hg_offset = 0; SOC_HG_OFFSET */ 2296 /* 2297 * 16th bit from right. See SOC_TRUNK_BIT_POS(unit) 2298 * Note that it is not together with port/trunk-id. 2299 */ 2300 si->trunk_bit_pos = 15; 2301 si->port_addr_max = 127; /* port_addr_max has to be 2^n -1 */ 2302 si->num_cpu_cosq = 44; 2303 /* add multiple modid */ 2304 si->num_time_interface = 1; 2305 si->vlan_xlate_glp_wildcard = 0xffff; /* glp wildcard value */ 2306 si->pcie_phy_addr = 0x5; 2307 #ifdef BCM_SBUSDMA_SUPPORT 2308 soc->max_sbusdma_channels = 3; 2309 soc_hx4_blk_counter_config(unit); 2310 #endif /* BCM_SBUSDMA_SUPPORT */ 2311 si->num_ucs = 2; 2312 if (!soc_feature(unit, soc_feature_global_meter)) { 2313 si->global_meter_pools = 0; 2314 si->global_meter_size_of_pool = 0; 2315 si->global_meter_max_size_of_pool = 0; 2316 si->num_flex_ingress_pools = 0; 2317 si->num_flex_egress_pools = 0; 2318 } else { 2319 si->global_meter_pools = 8; 2320 si->global_meter_size_of_pool = 1024; 2321 si->global_meter_max_size_of_pool = 1024; 2322 si->num_flex_ingress_pools = 8; 2323 si->num_flex_egress_pools = 8; 2324 } 2325 if (soc_property_get(unit, spn_MODULE_64PORTS, 1)) { 2326 si->modport_max = 63; 2327 } else { 2328 /* Adjust modid count based on dual-modid config parameter settings. 2329 * By default, dual-modid is enabled (32-port module mode) to allow 2330 * compatibility with other devices. 2331 */ 2332 si->modid_count = 2; 2333 } 2334 2335 break; 2336 #endif /* BCM_HELIX4_SUPPORT */ 2337 2338 case BCM56640_DEVICE_ID: 2339 case BCM56643_DEVICE_ID: 2340 case BCM56644_DEVICE_ID: 2341 case BCM56648_DEVICE_ID: 2342 case BCM56649_DEVICE_ID: 2343 case BCM56540_DEVICE_ID: 2344 case BCM56541_DEVICE_ID: 2345 case BCM56542_DEVICE_ID: 2346 case BCM56543_DEVICE_ID: 2347 case BCM56544_DEVICE_ID: 2348 case BCM56545_DEVICE_ID: 2349 case BCM56546_DEVICE_ID: 2350 case BCM56044_DEVICE_ID: 2351 case BCM56045_DEVICE_ID: 2352 case BCM56046_DEVICE_ID: 2353 si->chip = SOC_INFO_CHIP_TRIUMPH3; 2354 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2355 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2356 /* si->hg_offset = 0; SOC_HG_OFFSET */ 2357 /* 2358 * 16th bit from right. See SOC_TRUNK_BIT_POS(unit) 2359 * Note that it is not together with port/trunk-id. 2360 */ 2361 si->trunk_bit_pos = 15; 2362 si->port_addr_max = 127; /* port_addr_max has to be 2^n -1 */ 2363 si->num_cpu_cosq = (rev_id >= BCM56640_B0_REV_ID) ? 45 : 48; 2364 /* add multiple modid */ 2365 si->num_time_interface = 1; 2366 si->vlan_xlate_glp_wildcard = 0xffff; /* glp wildcard value */ 2367 si->pcie_phy_addr = 0x9e; 2368 #ifdef BCM_SBUSDMA_SUPPORT 2369 soc->max_sbusdma_channels = 3; 2370 #ifdef BCM_TRIUMPH3_SUPPORT 2371 soc_tr3_blk_counter_config(unit); 2372 #endif /* BCM_TRIUMPH3_SUPPORT */ 2373 #endif /* BCM_SBUSDMA_SUPPORT */ 2374 si->global_meter_pools = 8; 2375 si->global_meter_size_of_pool = 4096; 2376 si->global_meter_max_size_of_pool = 4096; 2377 if (dev_id == BCM56540_DEVICE_ID || 2378 dev_id == BCM56541_DEVICE_ID || 2379 dev_id == BCM56542_DEVICE_ID || 2380 dev_id == BCM56543_DEVICE_ID || 2381 dev_id == BCM56544_DEVICE_ID || 2382 dev_id == BCM56545_DEVICE_ID || 2383 dev_id == BCM56546_DEVICE_ID) { 2384 si->global_meter_size_of_pool = 2048; 2385 } 2386 si->global_meter_action_size = 8192; 2387 if (soc_property_get(unit, spn_MODULE_64PORTS, 1)) { 2388 si->modport_max = 63; 2389 } else { 2390 /* Adjust modid count based on dual-modid config parameter settings. 2391 * By default, dual-modid is enabled (32-port module mode) to allow 2392 * compatibility with other devices. 2393 */ 2394 si->modid_count = 2; 2395 } 2396 si->num_ucs = 2; 2397 2398 break; 2399 2400 #if defined(BCM_KATANA_SUPPORT) 2401 case BCM56440_DEVICE_ID: 2402 case BCM56441_DEVICE_ID: 2403 case BCM56442_DEVICE_ID: 2404 case BCM56443_DEVICE_ID: 2405 case BCM56445_DEVICE_ID: 2406 case BCM56446_DEVICE_ID: 2407 case BCM56447_DEVICE_ID: 2408 case BCM56448_DEVICE_ID: 2409 case BCM56449_DEVICE_ID: 2410 case BCM56240_DEVICE_ID: 2411 case BCM56241_DEVICE_ID: 2412 case BCM56242_DEVICE_ID: 2413 case BCM56243_DEVICE_ID: 2414 case BCM56245_DEVICE_ID: 2415 case BCM56246_DEVICE_ID: 2416 case BCM55440_DEVICE_ID: 2417 case BCM55441_DEVICE_ID: 2418 si->chip = SOC_INFO_CHIP_KATANA; 2419 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2420 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2421 si->hg_offset = 26; /* SOC_HG_OFFSET */ 2422 si->trunk_bit_pos = 15; 2423 si->port_addr_max = 127; 2424 si->num_cpu_cosq = 48; 2425 si->internal_loopback = 1; 2426 si->num_time_interface = 1; 2427 si->num_flex_ingress_pools = 8; 2428 si->num_flex_egress_pools = 8; 2429 si->pcie_phy_addr = 0x9d; 2430 if ((dev_id >= BCM56240_DEVICE_ID) && 2431 (dev_id <= BCM56246_DEVICE_ID)) { 2432 si->size_flex_ingress_pool = 512; 2433 si->size_flex_egress_pool = 256; 2434 } else { 2435 si->size_flex_ingress_pool = 2048; 2436 si->size_flex_egress_pool = 1024; 2437 } 2438 si->vlan_xlate_glp_wildcard = 0xffff; /* glp wildcard value */ 2439 si->global_meter_pools = 8; 2440 si->global_meter_size_of_pool = 1024; 2441 si->global_meter_max_size_of_pool = 1024; 2442 if ((dev_id >= BCM56240_DEVICE_ID) && 2443 (dev_id <= BCM56246_DEVICE_ID)) { 2444 si->global_meter_size_of_pool = 256; 2445 } 2446 si->global_meter_action_size = 8192; 2447 if (!(soc_property_get(unit, spn_MODULE_64PORTS, 1))) { 2448 /* Adjust modid count based on dual-modid config parameter settings. 2449 * By default, dual-modid is enabled (32-port module mode) to allow 2450 * compatibility with other devices. 2451 */ 2452 si->modid_count = 2; 2453 } 2454 si->num_ucs = 2; 2455 /* default DDR3 Configuration */ 2456 /* 16k Col * 1k Row * 8 Banks * 16 bits = 2Gb */ 2457 #if 0 /* Katana Only supports 1k Cols and 8 banks */ 2458 soc->ddr3_num_columns = soc_property_get(unit,spn_EXT_RAM_COLUMNS, 1024); 2459 soc->ddr3_num_banks = soc_property_get(unit,spn_EXT_RAM_BANKS, 8); 2460 #else 2461 soc->ddr3_num_columns = 1024; 2462 soc->ddr3_num_banks = 8; 2463 #endif 2464 soc->ddr3_num_memories = soc_property_get(unit,spn_EXT_RAM_PRESENT, 3); 2465 soc->ddr3_num_rows = soc_property_get(unit,spn_EXT_RAM_ROWS, 8192); 2466 soc->ddr3_clock_mhz = soc_property_get(unit, spn_DDR3_CLOCK_MHZ, 800); 2467 soc->ddr3_mem_grade = soc_property_get(unit, spn_DDR3_MEM_GRADE, 0); 2468 2469 break; 2470 #endif /* BCM_KATANA_SUPPORT */ 2471 2472 #if defined(BCM_KATANA2_SUPPORT) 2473 case BCM55450_DEVICE_ID: 2474 case BCM55455_DEVICE_ID: 2475 case BCM56248_DEVICE_ID: 2476 case BCM56450_DEVICE_ID: 2477 case BCM56452_DEVICE_ID: 2478 case BCM56454_DEVICE_ID: 2479 case BCM56455_DEVICE_ID: 2480 case BCM56456_DEVICE_ID: 2481 case BCM56457_DEVICE_ID: 2482 case BCM56458_DEVICE_ID: 2483 si->chip = SOC_INFO_CHIP_KATANA2; 2484 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2485 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2486 si->modport_max = 127; 2487 si->hg_offset = 26; /* SOC_HG_OFFSET */ 2488 si->trunk_bit_pos = 15; /* 16th bit from right. See SOC_TRUNK_BIT_POS(unit)*/ 2489 si->port_addr_max = 127; 2490 si->num_cpu_cosq = 48; 2491 si->internal_loopback = 1; 2492 si->num_time_interface = 1; 2493 si->num_flex_ingress_pools = 8; 2494 si->num_flex_egress_pools = 8; 2495 si->size_flex_ingress_pool = 2048; 2496 si->size_flex_egress_pool = 1024; 2497 si->vlan_xlate_glp_wildcard = 0xffff; /* glp wildcard value */ 2498 si->global_meter_pools = 8; 2499 si->global_meter_size_of_pool = 1024; 2500 si->global_meter_max_size_of_pool = 1024; 2501 si->pcie_phy_addr = 0x5; 2502 if ((dev_id >= BCM56240_DEVICE_ID) && 2503 (dev_id <= BCM56246_DEVICE_ID)) { 2504 si->global_meter_size_of_pool = 256; 2505 } 2506 2507 si->global_meter_action_size = 8192; 2508 #ifdef BCM_SBUSDMA_SUPPORT 2509 soc->max_sbusdma_channels = 3; 2510 soc_kt2_blk_counter_config(unit); 2511 #endif 2512 #ifdef PLISIM 2513 if (SOC_IS_KATANA2(unit) && (sal_boot_flags_get() & BOOT_F_PLISIM)) { 2514 /* case with pcid.sim or bcm5*_bcmsim.linux */ 2515 if (CMVEC(unit).config_var_get == NULL) { 2516 LOG_CLI((BSL_META_U(unit, 2517 "Assigning dummy config var get \n"))); 2518 CMVEC(unit).config_var_get = _dummy_config_var_get; 2519 } 2520 } 2521 #endif 2522 si->olp_port[0] = 0; 2523 si->num_ucs = 2; 2524 si->max_mtu = 12288; 2525 break; 2526 #endif /* BCM_KATANA2_SUPPORT */ 2527 #if defined(BCM_SABER2_SUPPORT) 2528 case BCM56260_DEVICE_ID: 2529 case BCM56261_DEVICE_ID: 2530 case BCM56262_DEVICE_ID: 2531 case BCM56263_DEVICE_ID: 2532 case BCM56265_DEVICE_ID: 2533 case BCM56266_DEVICE_ID: 2534 case BCM56267_DEVICE_ID: 2535 case BCM56268_DEVICE_ID: 2536 case BCM56460_DEVICE_ID: 2537 case BCM56461_DEVICE_ID: 2538 case BCM56462_DEVICE_ID: 2539 case BCM56463_DEVICE_ID: 2540 case BCM56465_DEVICE_ID: 2541 case BCM56466_DEVICE_ID: 2542 case BCM56467_DEVICE_ID: 2543 case BCM56468_DEVICE_ID: 2544 case BCM56233_DEVICE_ID: 2545 si->chip = SOC_INFO_CHIP_KATANA2; 2546 si->chip_type = SOC_INFO_CHIP_TYPE_SABER2; /* this is being added for saber2 specific stuff */ 2547 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2548 si->hg_offset = 26; /* SOC_HG_OFFSET */ 2549 si->trunk_bit_pos = 15; 2550 si->port_addr_max = 127; 2551 si->num_cpu_cosq = 48; 2552 si->internal_loopback = 1; 2553 si->num_time_interface = 1; 2554 si->num_flex_ingress_pools = 8; 2555 si->num_flex_egress_pools = 8; 2556 si->size_flex_ingress_pool = 2048; 2557 si->size_flex_egress_pool = 1024; 2558 si->vlan_xlate_glp_wildcard = 0xffff; /* glp wildcard value */ 2559 if ((dev_id == BCM56260_DEVICE_ID) || 2560 (dev_id == BCM56261_DEVICE_ID) || 2561 (dev_id == BCM56262_DEVICE_ID) || 2562 (dev_id == BCM56263_DEVICE_ID) || 2563 (dev_id == BCM56265_DEVICE_ID) || 2564 (dev_id == BCM56266_DEVICE_ID) || 2565 (dev_id == BCM56267_DEVICE_ID) || 2566 (dev_id == BCM56268_DEVICE_ID) 2567 ) { 2568 /* Number of meters reduced to half, 2569 * for SB2 (compared to SB2+). 2570 * for SB2+:8K, SB2:4K, Dagger_2:1K 2571 */ 2572 si->global_meter_size_of_pool = 512; 2573 si->global_meter_action_size = 4096; 2574 } else if (dev_id == BCM56233_DEVICE_ID) { 2575 si->global_meter_size_of_pool = 128; 2576 si->global_meter_action_size = 1024; 2577 } else { 2578 si->global_meter_size_of_pool = 1024; 2579 si->global_meter_action_size = 8192; 2580 } 2581 si->global_meter_pools = 8; 2582 si->global_meter_max_size_of_pool = 1024; 2583 2584 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2585 #ifdef BCM_SBUSDMA_SUPPORT 2586 soc->max_sbusdma_channels = 3; 2587 /* soc_sb2_blk_counter_config(unit); */ 2588 #endif 2589 #ifdef PLISIM 2590 if (sal_boot_flags_get() & BOOT_F_PLISIM) { 2591 /* case with pcid.sim or bcm5*_bcmsim.linux */ 2592 if (CMVEC(unit).config_var_get == NULL) { 2593 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2594 (BSL_META_U(unit, 2595 "Assigning dummy config var get \n"))); 2596 CMVEC(unit).config_var_get = _dummy_config_var_get; 2597 } 2598 } 2599 #endif 2600 si->olp_port[0] = 0; 2601 /* Dagger2 support 2xR5 Embedded processors 2602 * Since the mHost 0 is disabled 2603 * The num_ucs is kept 3 for maintaining exisiting for loops 2604 */ 2605 si->num_ucs = 3; 2606 si->max_mtu = 0x3000; 2607 2608 break; 2609 #endif /* BCM_SABER2_SUPPORT */ 2610 2611 #if defined(BCM_METROLITE_SUPPORT) 2612 case BCM56270_DEVICE_ID: 2613 case BCM56271_DEVICE_ID: 2614 case BCM56272_DEVICE_ID: 2615 2616 case BCM53460_DEVICE_ID: 2617 case BCM53461_DEVICE_ID: 2618 2619 si->chip = SOC_INFO_CHIP_KATANA2; 2620 si->chip_type = SOC_INFO_CHIP_TYPE_METROLITE; /* this is being added for metrolite specific stuff */ 2621 si->modid_max = 63; /* See SOC_MODID_MAX(unit) */ 2622 si->hg_offset = 26; /* SOC_HG_OFFSET */ 2623 si->trunk_bit_pos = 15; 2624 si->port_addr_max = 31; 2625 si->num_cpu_cosq = 48; 2626 si->internal_loopback = 1; 2627 si->num_time_interface = 1; 2628 si->num_flex_ingress_pools = 4; 2629 si->num_flex_egress_pools = 4; 2630 si->size_flex_ingress_pool = 512; 2631 si->size_flex_egress_pool = 512; 2632 si->vlan_xlate_glp_wildcard = 0xffff; /* glp wildcard value */ 2633 si->global_meter_pools = 8; 2634 si->global_meter_size_of_pool = 512; 2635 si->global_meter_max_size_of_pool = 512; 2636 2637 si->global_meter_action_size = 4096; 2638 #ifdef BCM_SBUSDMA_SUPPORT 2639 soc->max_sbusdma_channels = 3; 2640 soc->tdma_ch = 0; 2641 soc->tslam_ch = 1; 2642 soc->desc_ch = 2; 2643 #endif 2644 #ifdef PLISIM 2645 if (sal_boot_flags_get() & BOOT_F_PLISIM) { 2646 /* case with pcid.sim or bcm5*_bcmsim.linux */ 2647 if (CMVEC(unit).config_var_get == NULL) { 2648 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2649 (BSL_META_U(unit, 2650 "Assigning dummy config var get \n"))); 2651 CMVEC(unit).config_var_get = _dummy_config_var_get; 2652 } 2653 } 2654 #endif 2655 si->olp_port[0] = 0; 2656 si->num_ucs = 2; 2657 si->max_mtu = 0x3000; 2658 2659 break; 2660 #endif /* BCM_METROLITE_SUPPORT */ 2661 2662 case BCM56850_DEVICE_ID: 2663 case BCM56860_DEVICE_ID: 2664 switch (dev_id) { 2665 case BCM56868_DEVICE_ID: 2666 si->chip_type = SOC_INFO_CHIP_TYPE_TITAN2PLUS; 2667 break; 2668 case BCM56860_DEVICE_ID: 2669 case BCM56861_DEVICE_ID: 2670 case BCM56862_DEVICE_ID: 2671 case BCM56864_DEVICE_ID: 2672 case BCM56865_DEVICE_ID: 2673 case BCM56866_DEVICE_ID: 2674 case BCM56867_DEVICE_ID: 2675 case BCM56832_DEVICE_ID: 2676 case BCM56833_DEVICE_ID: 2677 case BCM56836_DEVICE_ID: 2678 si->chip = SOC_INFO_CHIP_TRIDENT2PLUS; 2679 break; 2680 default: 2681 if (dev_id == BCM56750_DEVICE_ID) { 2682 si->chip = SOC_INFO_CHIP_TITAN2; 2683 } else { 2684 si->chip = SOC_INFO_CHIP_TRIDENT2; 2685 } 2686 } 2687 2688 si->num_pipe = 2; 2689 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2690 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2691 /* si->hg_offset = 0; SOC_HG_OFFSET */ 2692 /* 2693 * 16th bit from right. See SOC_TRUNK_BIT_POS(unit) 2694 * Note that it is not together with port/trunk-id. 2695 */ 2696 si->trunk_bit_pos = 15; 2697 /* port_addr_max has to be 2^n -1 */ 2698 si->port_addr_max = 127; 2699 if (SOC_IS_TD2P_TT2P(unit)){ 2700 si->num_cpu_cosq = 48; 2701 } else { 2702 si->num_cpu_cosq = (rev_id >= BCM56850_A1_REV_ID) ? 44 : 48; 2703 } 2704 si->modid_count = 2705 soc_property_get(unit, spn_MODULE_NUM_MODIDS, 1) == 2 ? 2 : 1; 2706 si->modport_max = si->modid_count == 1 ? 127 : 63; 2707 si->num_time_interface = 1; 2708 si->pcie_phy_addr = 0x1da; 2709 #ifdef BCM_SBUSDMA_SUPPORT 2710 soc->max_sbusdma_channels = 3; 2711 #endif 2712 si->vlan_xlate_glp_wildcard = 0xffff; /* glp wildcard value */ 2713 si->num_ucs = 2; 2714 si->max_mtu = 9416; 2715 /* Initialize the max subport ports and groups */ 2716 si->max_subport_coe_ports = si->max_subport_coe_groups = 512; 2717 break; 2718 2719 2720 #ifdef BCM_APACHE_SUPPORT 2721 case BCM56560_DEVICE_ID: 2722 case BCM56670_DEVICE_ID: 2723 case BCM56671_DEVICE_ID: 2724 case BCM56672_DEVICE_ID: 2725 case BCM56675_DEVICE_ID: 2726 si->chip_type = SOC_INFO_CHIP_TYPE_APACHE; 2727 if (dev_id == BCM56670_DEVICE_ID || dev_id == BCM56671_DEVICE_ID || 2728 dev_id == BCM56672_DEVICE_ID || dev_id == BCM56675_DEVICE_ID) { 2729 si->chip_type = SOC_INFO_CHIP_TYPE_MONTEREY; 2730 } 2731 si->num_pipe = 1; 2732 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2733 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2734 /* si->hg_offset = 0; SOC_HG_OFFSET */ 2735 /* 2736 * 16th bit from right. See SOC_TRUNK_BIT_POS(unit) 2737 * Note that it is not together with port/trunk-id. 2738 */ 2739 si->trunk_bit_pos = 15; 2740 /* port_addr_max has to be 2^n -1 */ 2741 si->port_addr_max = 127; 2742 si->num_cpu_cosq = 48; 2743 si->modid_count = 2744 soc_property_get(unit, spn_MODULE_NUM_MODIDS, 1) == 2 ? 2 : 1; 2745 si->modport_max = si->modid_count == 1 ? 127 : 63; 2746 si->num_time_interface = 1; 2747 2748 #ifdef BCM_SBUSDMA_SUPPORT 2749 soc->max_sbusdma_channels = 3; 2750 #endif 2751 si->vlan_xlate_glp_wildcard = 0xffff; /* glp wildcard value */ 2752 si->num_ucs = 2; 2753 if (dev_id == BCM56670_DEVICE_ID || dev_id == BCM56671_DEVICE_ID || 2754 dev_id == BCM56672_DEVICE_ID ||dev_id == BCM56675_DEVICE_ID) 2755 si->num_ucs = 3; 2756 si->global_meter_pools = 8; 2757 si->global_meter_size_of_pool = 2048; 2758 si->global_meter_max_size_of_pool = 2048; 2759 si->global_meter_action_size = 16384; 2760 2761 /* Initialize the max subport ports and groups */ 2762 si->max_subport_coe_ports = si->max_subport_coe_groups = 256; 2763 si->max_mtu = 12288; /* Apache and FireBolt5 */ 2764 2765 break; 2766 #endif /* BCM_APACHE_SUPPORT */ 2767 2768 case BCM56960_DEVICE_ID: 2769 case BCM56961_DEVICE_ID: 2770 case BCM56962_DEVICE_ID: 2771 case BCM56963_DEVICE_ID: 2772 case BCM56930_DEVICE_ID: 2773 case BCM56968_DEVICE_ID: 2774 case BCM56168_DEVICE_ID: 2775 case BCM56169_DEVICE_ID: 2776 #if defined(BCM_TOMAHAWKPLUS_SUPPORT) 2777 case BCM56965_DEVICE_ID: 2778 case BCM56969_DEVICE_ID: 2779 case BCM56966_DEVICE_ID: 2780 case BCM56967_DEVICE_ID: 2781 if ((BCM56965_DEVICE_ID == dev_id) || (BCM56969_DEVICE_ID == dev_id) || 2782 (BCM56966_DEVICE_ID == dev_id) || (BCM56967_DEVICE_ID == dev_id)){ 2783 si->chip_type = SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS; 2784 si->port_class_max = 256; /* egr_vlan_xlate port class max*/ 2785 } else 2786 #endif 2787 { 2788 if (BCM56968_DEVICE_ID == dev_id){ 2789 si->chip_type = SOC_INFO_CHIP_TYPE_TITANHAWK; 2790 } 2791 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2792 } 2793 si->chip = SOC_INFO_CHIP_TOMAHAWK; 2794 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2795 /* si->hg_offset = 0; SOC_HG_OFFSET */ 2796 /* 2797 * 16th bit from right. See SOC_TRUNK_BIT_POS(unit) 2798 * Note that it is not together with port/trunk-id. 2799 */ 2800 si->trunk_bit_pos = 16; 2801 /* port_addr_max has to be 2^n -1 */ 2802 si->port_addr_max = 255; 2803 si->num_cpu_cosq = 48; 2804 si->modid_count = 2805 soc_property_get(unit, spn_MODULE_NUM_MODIDS, 1) == 2 ? 2 : 1; 2806 /* 2807 * For Dual modid support on Tomahawk (to address 136 ports), 2808 * the port split used is (64 + 128(use 72)) between two modids. 2809 * Two different modport max values are used for each modid. 2810 */ 2811 si->modport_max = si->modid_count == 1 ? 255 : 127; 2812 si->modport_max_first = si->modid_count == 1 ? -1 : 63; 2813 si->sflow_range_max = 28; 2814 si->num_pipe = 4; 2815 si->num_xpe = 4; 2816 si->num_slice = 2; 2817 si->num_layer = 2; 2818 si->num_time_interface = 1; 2819 si->num_ucs = 2; 2820 #ifdef BCM_SBUSDMA_SUPPORT 2821 soc->max_sbusdma_channels = 3; 2822 #endif 2823 si->vlan_xlate_glp_wildcard = 0x1ffff; /* glp wildcard value */ 2824 si->max_mtu = 9416; 2825 #ifdef BCM_TOMAHAWK_SUPPORT 2826 if (((soc_property_get(unit, "th_random_sampling_enable", 0)) == 1) && 2827 (soc_feature(unit, soc_feature_th_tflow))) { 2828 si->th_tflow_enabled = 1; 2829 } else { 2830 si->th_tflow_enabled = 0; 2831 } 2832 2833 if (soc_feature(unit, soc_feature_th_fp_ctc_manipulate) && 2834 (soc_property_get(unit, "th_copy_to_cpu_replace", 0)) == 1) { 2835 si->th_ctc_replace_enabled = 1; 2836 } else { 2837 si->th_ctc_replace_enabled = 0; 2838 } 2839 #endif /* BCM_TOMAHAWK_SUPPORT */ 2840 break; 2841 2842 case BCM56970_DEVICE_ID: 2843 case BCM56971_DEVICE_ID: 2844 case BCM56972_DEVICE_ID: 2845 case BCM56974_DEVICE_ID: 2846 case BCM56975_DEVICE_ID: 2847 if (BCM56975_DEVICE_ID == dev_id){ 2848 si->chip_type = SOC_INFO_CHIP_TYPE_TITANHAWK2; 2849 } else 2850 { 2851 si->chip_type= SOC_INFO_CHIP_TYPE_TOMAHAWK2; 2852 } 2853 2854 si->port_class_max = 256; /* egr_vlan_xlate port class max*/ 2855 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2856 /* si->hg_offset = 0; SOC_HG_OFFSET */ 2857 /* 2858 * 16th bit from right. See SOC_TRUNK_BIT_POS(unit) 2859 * Note that it is not together with port/trunk-id. 2860 */ 2861 si->trunk_bit_pos = 16; 2862 /* port_addr_max has to be 2^n -1 */ 2863 si->port_addr_max = 255; 2864 si->num_cpu_cosq = 48; 2865 si->modid_count = 2866 soc_property_get(unit, spn_MODULE_NUM_MODIDS, 1) == 2 ? 2 : 1; 2867 /* 2868 * For Dual modid support on Tomahawk (to address 136 ports), 2869 * the port split used is (64 + 128(use 72)) between two modids. 2870 * Two different modport max values are used for each modid. 2871 */ 2872 si->modport_max = si->modid_count == 1 ? 255 : 127; 2873 si->modport_max_first = si->modid_count == 1 ? -1 : 63; 2874 si->sflow_range_max = 28; 2875 2876 si->num_pipe = 4; 2877 si->num_xpe = 4; 2878 si->num_slice = 2; 2879 si->num_sed = 2; 2880 si->num_layer = 2; 2881 si->num_time_interface = 1; 2882 si->num_ucs = 2; 2883 #ifdef BCM_SBUSDMA_SUPPORT 2884 soc->max_sbusdma_channels = 3; 2885 #ifdef BCM_TOMAHAWK2_SUPPORT 2886 soc_tomahawk2_mmu_pstats_tbl_config(unit); 2887 #endif 2888 #endif /* BCM_SBUSDMA_SUPPORT */ 2889 si->vlan_xlate_glp_wildcard = 0x1ffff; /* glp wildcard value */ 2890 si->max_mtu = 9416; 2891 break; 2892 2893 case BCM56980_DEVICE_ID: 2894 case BCM56981_DEVICE_ID: 2895 case BCM56982_DEVICE_ID: 2896 case BCM56983_DEVICE_ID: 2897 case BCM56984_DEVICE_ID: 2898 si->chip_type = SOC_INFO_CHIP_TYPE_TOMAHAWK3; 2899 si->port_class_max = 144; /* egr_vlan_xlate port class max*/ 2900 si->modid_max = 0; /* See SOC_MODID_MAX(unit) */ 2901 /* si->hg_offset = 0; SOC_HG_OFFSET */ 2902 /* 2903 * 8th bit from right. MSB denotes if the next 8 bits are trunk number 2904 * or port number 2905 */ 2906 si->trunk_bit_pos = 8; 2907 /* port_addr_max has to be 2^n -1 */ 2908 si->port_addr_max = 255; 2909 si->num_cpu_cosq = 48; 2910 si->modid_count = 2911 soc_property_get(unit, spn_MODULE_NUM_MODIDS, 1) == 2 ? 2 : 1; 2912 /* 2913 * For Dual modid support on Tomahawk (to address 136 ports), 2914 * the port split used is (64 + 128(use 72)) between two modids. 2915 * Two different modport max values are used for each modid. 2916 */ 2917 si->modport_max = si->modid_count == 1 ? 255 : 127; 2918 si->modport_max_first = si->modid_count == 1 ? -1 : 63; 2919 si->sflow_range_max = 28; 2920 si->num_pipe = 8; 2921 si->num_itm = 2; 2922 si->num_eb = 8; 2923 si->num_time_interface = 1; 2924 si->num_ucs = 2; 2925 #ifdef BCM_SBUSDMA_SUPPORT 2926 soc->max_sbusdma_channels = 3; 2927 #endif 2928 /*si->vlan_xlate_glp_wildcard = 0x1ffff; *//* glp wildcard value */ 2929 si->max_mtu = 9416; 2930 #ifdef BCM_TOMAHAWK_SUPPORT 2931 if (((soc_property_get(unit, "th_random_sampling_enable", 0)) == 1) && 2932 (soc_feature(unit, soc_feature_th_tflow))) { 2933 si->th_tflow_enabled = 1; 2934 } else { 2935 si->th_tflow_enabled = 0; 2936 } 2937 2938 if (soc_feature(unit, soc_feature_th_fp_ctc_manipulate) && 2939 (soc_property_get(unit, "th_copy_to_cpu_replace", 0)) == 1) { 2940 si->th_ctc_replace_enabled = 1; 2941 } else { 2942 si->th_ctc_replace_enabled = 0; 2943 } 2944 #endif /* BCM_TOMAHAWK_SUPPORT */ 2945 break; 2946 2947 case BCM56870_DEVICE_ID: 2948 case BCM56873_DEVICE_ID: 2949 si->chip_type = SOC_INFO_CHIP_TYPE_TRIDENT3; 2950 si->port_class_max = 256; /* egr_vlan_xlate port class max*/ 2951 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2952 /* si->hg_offset = 0; SOC_HG_OFFSET */ 2953 /* 2954 * 17th bit from right. See SOC_TRUNK_BIT_POS(unit) 2955 * Note that it is not together with port/trunk-id. 2956 */ 2957 si->trunk_bit_pos = 16; 2958 /* port_addr_max has to be 2^n -1 */ 2959 si->port_addr_max = 255; 2960 si->num_cpu_cosq = 48; 2961 si->modid_count = 2962 soc_property_get(unit, spn_MODULE_NUM_MODIDS, 1) == 2 ? 2 : 1; 2963 /* 2964 * For Dual modid support on Trident3 (to address 136 ports), 2965 * the port split used is (64 + 128(use 72)) between two modids. 2966 * Two different modport max values are used for each modid. 2967 */ 2968 si->modport_max = si->modid_count == 1 ? 255 : 127; 2969 si->modport_max_first = si->modid_count == 1 ? -1 : 63; 2970 2971 si->num_pipe = 2; 2972 si->num_xpe = 1; 2973 si->num_slice = 1; 2974 si->num_layer = 1; 2975 si->num_time_interface = 1; 2976 si->num_ucs = 2; 2977 #ifdef BCM_SBUSDMA_SUPPORT 2978 soc->max_sbusdma_channels = 3; 2979 soc->tdma_ch = 0; 2980 soc->tslam_ch = 1; 2981 soc->desc_ch = 2; 2982 #endif 2983 si->vlan_xlate_glp_wildcard = 0x1ffff; /* glp wildcard value */ 2984 /* Initialize the max subport ports and groups */ 2985 si->max_subport_coe_ports = si->max_subport_coe_groups = 512; 2986 si->max_mtu = 9416; 2987 break; 2988 case BCM56370_DEVICE_ID: 2989 si->chip_type = SOC_INFO_CHIP_TYPE_HELIX5; 2990 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 2991 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 2992 /* si->hg_offset = 0; SOC_HG_OFFSET */ 2993 /* 2994 * 16th bit from right. See SOC_TRUNK_BIT_POS(unit) 2995 * Note that it is not together with port/trunk-id. 2996 */ 2997 si->trunk_bit_pos = 16; 2998 /* port_addr_max has to be 2^n -1 */ 2999 si->port_addr_max = 255; 3000 si->nof_pmqs = 3; 3001 si->num_cpu_cosq = 48; 3002 si->modid_count = 3003 soc_property_get(unit, spn_MODULE_NUM_MODIDS, 1) == 2 ? 2 : 1; 3004 /* 3005 * For Dual modid support on Helix-5 (to address 76 ports), 3006 * the port split used is (64 + 78(use 76)) between two modids. 3007 * Two different modport max values are used for each modid. 3008 */ 3009 si->modport_max = si->modid_count == 1 ? 255 : 127; 3010 si->modport_max_first = si->modid_count == 1 ? -1 : 63; 3011 3012 si->num_pipe = 1; 3013 si->num_xpe = 1; 3014 si->num_slice = 1; 3015 si->num_layer = 1; 3016 si->num_time_interface = 1; 3017 #ifdef BCM_SBUSDMA_SUPPORT 3018 soc->max_sbusdma_channels = 3; 3019 soc->tdma_ch = 0; 3020 soc->tslam_ch = 1; 3021 soc->desc_ch = 2; 3022 #endif 3023 si->vlan_xlate_glp_wildcard = 0x1ffff; /* glp wildcard value */ 3024 break; 3025 case BCM56770_DEVICE_ID: 3026 case BCM56771_DEVICE_ID: 3027 si->chip_type = SOC_INFO_CHIP_TYPE_MAVERICK2; 3028 si->port_class_max = 128; /* egr_vlan_xlate port class max*/ 3029 si->modid_max = 255; /* See SOC_MODID_MAX(unit) */ 3030 /* si->hg_offset = 0; SOC_HG_OFFSET */ 3031 /* 3032 * 16th bit from right. See SOC_TRUNK_BIT_POS(unit) 3033 * Note that it is not together with port/trunk-id. 3034 */ 3035 si->trunk_bit_pos = 16; 3036 /* port_addr_max has to be 2^n -1 */ 3037 si->port_addr_max = 255; 3038 si->num_cpu_cosq = 48; 3039 si->modid_count = 3040 soc_property_get(unit, spn_MODULE_NUM_MODIDS, 1) == 2 ? 2 : 1; 3041 /* 3042 * For Dual modid support on Trident3 (to address 136 ports), 3043 * the port split used is (64 + 128(use 72)) between two modids. 3044 * Two different modport max values are used for each modid. 3045 */ 3046 si->modport_max = si->modid_count == 1 ? 255 : 127; 3047 si->modport_max_first = si->modid_count == 1 ? -1 : 63; 3048 3049 si->num_pipe = 1; 3050 si->num_xpe = 1; 3051 si->num_slice = 1; 3052 si->num_layer = 1; 3053 si->num_time_interface = 1; 3054 si->num_ucs = 2; 3055 #ifdef BCM_SBUSDMA_SUPPORT 3056 soc->max_sbusdma_channels = 3; 3057 soc->tdma_ch = 0; 3058 soc->tslam_ch = 1; 3059 soc->desc_ch = 2; 3060 #endif 3061 si->vlan_xlate_glp_wildcard = 0x1ffff; /* glp wildcard value */ 3062 /* Initialize the max subport ports and groups */ 3063 si->max_subport_coe_ports = si->max_subport_coe_groups = 512; 3064 si->max_mtu = 9416; 3065 break; 3066 3067 default: 3068 si->chip = 0; 3069 si->modid_count = 0; 3070 LOG_WARN(BSL_LS_SOC_COMMON, 3071 (BSL_META_U(unit, 3072 "soc_info_config: driver device %04x unexpected\n"), 3073 drv_dev_id)); 3074 break; 3075 } 3076 3077 if (si->internal_loopback) { 3078 SOC_FEATURE_SET(unit, soc_feature_wlan); 3079 SOC_FEATURE_SET(unit, soc_feature_egr_mirror_true); 3080 SOC_FEATURE_SET(unit, soc_feature_mim); 3081 SOC_FEATURE_SET(unit, soc_feature_internal_loopback); 3082 SOC_FEATURE_SET(unit, soc_feature_mmu_virtual_ports); 3083 } else { 3084 SOC_PBMP_CLEAR(si->lb_pbm); 3085 } 3086 3087 /* Enable Egress True Mirroring on devices with EP Redire V2*/ 3088 if (soc_feature(unit, soc_feature_ep_redirect_v2)) { 3089 SOC_FEATURE_SET(unit, soc_feature_egr_mirror_true); 3090 } 3091 3092 /* 3093 * pbmp_valid is a bitmap of all ports that exist on the unit. Any 3094 * port not in this bitmap is thoroughly disregarded by the driver. 3095 * This is useful when some switch ports are unused (e.g. the IPIC 3096 * for 5691). 3097 */ 3098 pbmp_valid = soc_property_get_pbmp(unit, spn_PBMP_VALID, 1); 3099 if (soc_property_get_str(unit, spn_PBMP_GPORT_STACK) != NULL) { 3100 pbmp_gport_stack = soc_property_get_pbmp(unit, spn_PBMP_GPORT_STACK, 0); 3101 } 3102 #if defined(BCM_ENDURO_SUPPORT) || defined(BCM_KATANA_SUPPORT) 3103 if(SOC_IS_ENDURO(unit) || SOC_IS_KATANAX(unit)) { 3104 if (soc_property_get_str(unit, spn_PBMP_LOOPBACK) != NULL) { 3105 si->lb_pbm = soc_property_get_pbmp(unit, spn_PBMP_LOOPBACK, 0); 3106 } 3107 } 3108 #endif 3109 #if defined(BCM_KATANA_SUPPORT) 3110 if (SOC_IS_KATANAX(unit) && !SOC_IS_METROLITE(unit)) { 3111 if (soc_property_get_str(unit, spn_PBMP_EXT_MEM) != NULL) { 3112 si->pbm_ext_mem = soc_property_get_pbmp(unit, spn_PBMP_EXT_MEM, 0); 3113 } 3114 } 3115 #endif 3116 3117 /* Defaults for the xport settings */ 3118 SOC_PBMP_WORD_SET(pbmp_xport_ge, 0, 0); 3119 SOC_PBMP_WORD_SET(pbmp_xport_xe, 0, 0); 3120 switch (dev_id) { 3121 case BCM56580_DEVICE_ID: 3122 SOC_PBMP_WORD_SET(pbmp_xport_ge, 0, 0x0000ffff); 3123 break; 3124 case BCM56800_DEVICE_ID: 3125 SOC_PBMP_WORD_SET(pbmp_xport_xe, 0, 0x000fffff); 3126 break; 3127 case BCM56801_DEVICE_ID: 3128 SOC_PBMP_WORD_SET(pbmp_xport_xe, 0, 0x000003ff); 3129 break; 3130 case BCM56820_DEVICE_ID: 3131 SOC_PBMP_WORD_SET(pbmp_xport_xe, 0, 0x01fffffe); 3132 break; 3133 case BCM56821_DEVICE_ID: 3134 if (!soc_property_get(unit, spn_BCM56821_20X12, 0)) { 3135 SOC_PBMP_WORD_SET(pbmp_xport_xe, 0, 0x001fffe0); 3136 } 3137 break; 3138 case BCM56822_DEVICE_ID: 3139 SOC_PBMP_WORD_SET(pbmp_xport_xe, 0, 0x01ffe000); 3140 break; 3141 case BCM56825_DEVICE_ID: 3142 SOC_PBMP_WORD_SET(pbmp_xport_xe, 0, 0x01fe01fe); 3143 break; 3144 case BCM56629_DEVICE_ID: 3145 if (soc_feature(unit, soc_feature_xgport_one_xe_six_ge)) { 3146 if (!soc_property_get(unit, spn_BCM56629_40GE, 0)) { 3147 SOC_PBMP_WORD_SET(pbmp_xport_xe, 0, 0x0c004004); 3148 } 3149 } 3150 break; 3151 #ifdef BCM_SHADOW_SUPPORT 3152 case BCM88732_DEVICE_ID: 3153 SOC_PBMP_WORD_SET(pbmp_xport_xe, 0, 0x1fe); 3154 break; 3155 #endif /* BCM_SHADOW_SUPPORT */ 3156 default: 3157 break; 3158 } 3159 3160 pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 3161 pbmp_xport_xe); 3162 pbmp_xport_ge = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_GE, 3163 pbmp_xport_ge); 3164 pbmp_xport_cpri = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_CPRI, 3165 pbmp_xport_cpri); 3166 pbmp_roe_compression = soc_property_get_pbmp_default(unit, spn_PBMP_ROE_COMPRESSION, 3167 pbmp_roe_compression); 3168 3169 switch (dev_id) { 3170 #if defined(BCM_HERCULES_SUPPORT) 3171 case BCM5676_DEVICE_ID: 3172 /* 5676 (Herc4) has only ports 1, 3, 6, and 8 (only 0x14b) */ 3173 SOC_PBMP_PORT_REMOVE(pbmp_valid, 2); 3174 SOC_PBMP_PORT_REMOVE(pbmp_valid, 4); 3175 SOC_PBMP_PORT_REMOVE(pbmp_valid, 5); 3176 SOC_PBMP_PORT_REMOVE(pbmp_valid, 7); 3177 break; 3178 #endif /* BCM_HERCULES_SUPPORT */ 3179 #ifdef BCM_FIREBOLT_SUPPORT 3180 case BCM53301_DEVICE_ID: 3181 for (port = 16; port <= 27; port++) { 3182 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3183 } 3184 break; 3185 case BCM53300_DEVICE_ID: 3186 case BCM56500_DEVICE_ID: 3187 case BCM56300_DEVICE_ID: 3188 case BCM56505_DEVICE_ID: 3189 case BCM56305_DEVICE_ID: 3190 case BCM56310_DEVICE_ID: 3191 case BCM56315_DEVICE_ID: 3192 case BCM56510_DEVICE_ID: 3193 /* 3194 * Remove all HG/XE ports 3195 */ 3196 for (port = 24; port <= 27; port++) { 3197 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3198 } 3199 break; 3200 case BCM56301_DEVICE_ID: /* Helix Only */ 3201 case BCM56306_DEVICE_ID: /* Helix Only */ 3202 case BCM56311_DEVICE_ID: /* Helix 1.5 Only */ 3203 case BCM56316_DEVICE_ID: /* Helix 1.5 Only */ 3204 case BCM56501_DEVICE_ID: 3205 case BCM56506_DEVICE_ID: 3206 case BCM56511_DEVICE_ID: 3207 case BCM56516_DEVICE_ID: 3208 /* 3209 * Remove all GE ports 3210 */ 3211 for (port = 0; port <= 23; port++) { 3212 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3213 } 3214 break; 3215 case BCM56502_DEVICE_ID: 3216 case BCM56302_DEVICE_ID: 3217 case BCM56507_DEVICE_ID: 3218 case BCM56307_DEVICE_ID: 3219 case BCM56100_DEVICE_ID: 3220 case BCM56105_DEVICE_ID: 3221 case BCM56110_DEVICE_ID: 3222 case BCM56115_DEVICE_ID: 3223 case BCM56312_DEVICE_ID: 3224 case BCM56317_DEVICE_ID: 3225 case BCM56512_DEVICE_ID: 3226 case BCM56517_DEVICE_ID: 3227 SOC_PBMP_PORT_REMOVE(pbmp_valid, 26); 3228 /* passthru */ 3229 /* coverity[fallthrough: FALSE] */ 3230 case BCM56503_DEVICE_ID: 3231 case BCM56303_DEVICE_ID: 3232 case BCM56508_DEVICE_ID: 3233 case BCM56308_DEVICE_ID: 3234 case BCM56101_DEVICE_ID: 3235 case BCM56106_DEVICE_ID: 3236 case BCM56111_DEVICE_ID: 3237 case BCM56116_DEVICE_ID: 3238 case BCM56313_DEVICE_ID: 3239 case BCM56318_DEVICE_ID: 3240 case BCM56513_DEVICE_ID: 3241 case BCM56518_DEVICE_ID: 3242 SOC_PBMP_PORT_REMOVE(pbmp_valid, 27); 3243 break; 3244 case BCM53302_DEVICE_ID: 3245 SOC_PBMP_PORT_REMOVE(pbmp_valid, 24); 3246 SOC_PBMP_PORT_REMOVE(pbmp_valid, 25); 3247 break; 3248 #endif /* BCM_FIREBOLT_SUPPORT */ 3249 #if defined(BCM_RAPTOR_SUPPORT) 3250 case BCM56218R_DEVICE_ID: 3251 case BCM56219R_DEVICE_ID: 3252 SOC_PBMP_WORD_SET(pbmp_valid, 3253 0, 3254 SOC_PBMP_WORD_GET(pbmp_valid, 0) & 0xffffffc9); 3255 break; 3256 3257 case BCM56214R_DEVICE_ID: 3258 case BCM56215R_DEVICE_ID: 3259 SOC_PBMP_WORD_SET(pbmp_valid, 3260 0, 3261 SOC_PBMP_WORD_GET(pbmp_valid, 0) & 0xffffffc9); 3262 /* passthru */ 3263 /* coverity[fallthrough: FALSE] */ 3264 case BCM56214_DEVICE_ID: 3265 case BCM56215_DEVICE_ID: 3266 SOC_PBMP_WORD_SET(pbmp_valid, 1, 0x0); 3267 SOC_PBMP_PORT_REMOVE(pbmp_valid, 30); 3268 SOC_PBMP_PORT_REMOVE(pbmp_valid, 31); 3269 break; 3270 3271 case BCM56216_DEVICE_ID: 3272 case BCM56217_DEVICE_ID: 3273 SOC_PBMP_WORD_SET(pbmp_valid, 1, 0x0); 3274 SOC_PBMP_WORD_SET(pbmp_valid, 3275 0, 3276 SOC_PBMP_WORD_GET(pbmp_valid, 0) & 0x3fffff); 3277 break; 3278 3279 case BCM56212_DEVICE_ID: 3280 case BCM56213_DEVICE_ID: 3281 SOC_PBMP_WORD_SET(pbmp_valid, 1, 0x0); 3282 SOC_PBMP_WORD_SET(pbmp_valid, 3283 0, 3284 SOC_PBMP_WORD_GET(pbmp_valid, 0) & 0x3fff); 3285 break; 3286 3287 case BCM53716_DEVICE_ID: 3288 SOC_PBMP_WORD_SET(pbmp_valid, 1, 0x0); 3289 SOC_PBMP_WORD_SET(pbmp_valid, 3290 0, 3291 SOC_PBMP_WORD_GET(pbmp_valid, 0) & 0x3fffc9); 3292 break; 3293 3294 case BCM53714_DEVICE_ID: 3295 SOC_PBMP_WORD_SET(pbmp_valid, 1, 0x0); 3296 SOC_PBMP_PORT_REMOVE(pbmp_valid, 30); 3297 SOC_PBMP_PORT_REMOVE(pbmp_valid, 31); 3298 SOC_PBMP_PORT_REMOVE(pbmp_valid, 1); 3299 SOC_PBMP_PORT_REMOVE(pbmp_valid, 2); 3300 break; 3301 3302 case BCM53724_DEVICE_ID: 3303 SOC_PBMP_PORT_REMOVE(pbmp_valid, 1); 3304 SOC_PBMP_PORT_REMOVE(pbmp_valid, 2); 3305 SOC_PBMP_CLEAR(pbmp_gport_stack); 3306 break; 3307 case BCM53726_DEVICE_ID: 3308 SOC_PBMP_WORD_SET(pbmp_valid, 3309 0, 3310 SOC_PBMP_WORD_GET(pbmp_valid, 0) & 0x3ffff9); 3311 SOC_PBMP_CLEAR(pbmp_gport_stack); 3312 break; 3313 3314 case BCM53312_DEVICE_ID: 3315 case BCM53322_DEVICE_ID: 3316 SOC_PBMP_WORD_SET(pbmp_valid, 3317 0, 3318 SOC_PBMP_WORD_GET(pbmp_valid, 0) & 0x2223ff); 3319 break; 3320 3321 case BCM53313_DEVICE_ID: 3322 case BCM53323_DEVICE_ID: 3323 SOC_PBMP_WORD_SET(pbmp_valid, 3324 0, 3325 SOC_PBMP_WORD_GET(pbmp_valid, 0) & 0x23ffff); 3326 break; 3327 3328 case BCM53314_DEVICE_ID: 3329 case BCM53324_DEVICE_ID: 3330 break; 3331 3332 case BCM53718_DEVICE_ID: 3333 SOC_PBMP_PORT_REMOVE(pbmp_valid, 1); 3334 SOC_PBMP_PORT_REMOVE(pbmp_valid, 2); 3335 break; 3336 3337 case BCM56014_DEVICE_ID: 3338 SOC_PBMP_WORD_SET(pbmp_valid, 1, 0x0); 3339 SOC_PBMP_PORT_REMOVE(pbmp_valid, 30); 3340 SOC_PBMP_PORT_REMOVE(pbmp_valid, 31); 3341 /* passthru */ 3342 /* coverity[fallthrough: FALSE] */ 3343 case BCM56018_DEVICE_ID: 3344 SOC_PBMP_WORD_SET(pbmp_gport_fe, 0, 0xffffffc0); 3345 SOC_PBMP_WORD_SET(pbmp_gport_fe, 1, 0x003fffff); 3346 break; 3347 3348 case BCM56024_DEVICE_ID: 3349 case BCM56025_DEVICE_ID: 3350 SOC_PBMP_WORD_SET(pbmp_gport_fe, 0, 0xffffffc0); 3351 break; 3352 3353 case BCM56226_DEVICE_ID: 3354 case BCM56227_DEVICE_ID: 3355 SOC_PBMP_WORD_SET(pbmp_valid, 3356 0, 3357 SOC_PBMP_WORD_GET(pbmp_valid, 0) & 0x3fffff); 3358 break; 3359 3360 case BCM56228_DEVICE_ID: 3361 case BCM56229_DEVICE_ID: 3362 SOC_PBMP_WORD_SET(pbmp_valid, 3363 0, 3364 SOC_PBMP_WORD_GET(pbmp_valid, 0) & 0x3fff); 3365 break; 3366 3367 #endif /* BCM_RAPTOR_SUPPORT */ 3368 case BCM56580_DEVICE_ID: 3369 SOC_PBMP_CLEAR(pbmp_tmp); 3370 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x0000ffff); 3371 SOC_PBMP_OR(pbmp_xport_ge, pbmp_tmp); 3372 break; 3373 case BCM56701_DEVICE_ID: 3374 SOC_PBMP_PORT_REMOVE(pbmp_valid, 14); 3375 SOC_PBMP_PORT_REMOVE(pbmp_valid, 15); 3376 SOC_PBMP_PORT_REMOVE(pbmp_valid, 16); 3377 SOC_PBMP_PORT_REMOVE(pbmp_valid, 17); 3378 /* Fall through */ 3379 case BCM56700_DEVICE_ID: 3380 SOC_PBMP_PORT_REMOVE(pbmp_valid, 8); 3381 SOC_PBMP_PORT_REMOVE(pbmp_valid, 9); 3382 SOC_PBMP_PORT_REMOVE(pbmp_valid, 18); 3383 SOC_PBMP_PORT_REMOVE(pbmp_valid, 19); 3384 SOC_PBMP_CLEAR(pbmp_xport_xe); 3385 SOC_PBMP_ASSIGN(pbmp_gx13g, pbmp_valid); 3386 break; 3387 case BCM56803_DEVICE_ID: 3388 SOC_PBMP_PORT_REMOVE(pbmp_valid, 14); 3389 SOC_PBMP_PORT_REMOVE(pbmp_valid, 15); 3390 SOC_PBMP_PORT_REMOVE(pbmp_valid, 16); 3391 SOC_PBMP_PORT_REMOVE(pbmp_valid, 17); 3392 /* Fall through */ 3393 case BCM56802_DEVICE_ID: 3394 SOC_PBMP_PORT_REMOVE(pbmp_valid, 8); 3395 SOC_PBMP_PORT_REMOVE(pbmp_valid, 9); 3396 SOC_PBMP_PORT_REMOVE(pbmp_valid, 18); 3397 SOC_PBMP_PORT_REMOVE(pbmp_valid, 19); 3398 SOC_PBMP_ASSIGN(pbmp_gx13g, pbmp_valid); 3399 break; 3400 case BCM56801_DEVICE_ID: 3401 SOC_PBMP_PORT_REMOVE(pbmp_valid, 18); 3402 SOC_PBMP_PORT_REMOVE(pbmp_valid, 19); 3403 SOC_PBMP_ASSIGN(pbmp_gx13g, pbmp_valid); 3404 SOC_PBMP_CLEAR(pbmp_tmp); 3405 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x000ffc00); 3406 SOC_PBMP_AND(pbmp_gx13g, pbmp_tmp); 3407 break; 3408 case BCM56630_DEVICE_ID: 3409 for (port = 1; port <= 25; port++) { 3410 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3411 } 3412 SOC_PBMP_CLEAR(pbmp_tmp); 3413 if (soc_property_get(unit, spn_BCM56630_2X12_2X24, 0)) { 3414 /* 28x1GE + 2x12HG + 2x24HG + loopback */ 3415 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3416 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3417 SOC_PBMP_ASSIGN(pbmp_gx25g, pbmp_tmp); 3418 SOC_PBMP_CLEAR(pbmp_tmp); 3419 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3420 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3421 SOC_PBMP_ASSIGN(pbmp_gx13g, pbmp_tmp); 3422 } else { 3423 /* 24x1GE + 4x20HG + loopback */ 3424 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3425 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3426 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3427 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3428 if (soc_property_get(unit, spn_HIGIG_MAX_SPEED, 0) == 12000) { 3429 SOC_PBMP_ASSIGN(pbmp_gx12g, pbmp_tmp); 3430 } else { 3431 SOC_PBMP_ASSIGN(pbmp_gx20g, pbmp_tmp); 3432 } 3433 } 3434 for (port = 30; port <= 53; port++) { 3435 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3436 } 3437 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3438 SOC_PBMP_AND(pbmp_xq, pbmp_valid); 3439 SOC_PBMP_ASSIGN(pbmp_hyplite, pbmp_xq); 3440 break; 3441 case BCM56634_DEVICE_ID: 3442 /* Fall through */ 3443 case BCM56538_DEVICE_ID: 3444 SOC_PBMP_CLEAR(pbmp_tmp); 3445 if (soc_property_get(unit, spn_BCM56634_48G_4X12, 0) || 3446 soc_property_get(unit, spn_BCM56538_48G_4X12, 0)) { 3447 /* 48x1GE + 4x12HG + 1x12G(loopback) */ 3448 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3449 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3450 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3451 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3452 SOC_PBMP_ASSIGN(pbmp_gx13g, pbmp_tmp); 3453 } else if (soc_property_get(unit, spn_BCM56634_48G_2X24, 0) || 3454 soc_property_get(unit, spn_BCM56538_48G_2X24, 0)) { 3455 /* 48x1GE + 2x24HG + 1x12G(loopback) */ 3456 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3457 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3458 SOC_PBMP_ASSIGN(pbmp_gx25g, pbmp_tmp); 3459 SOC_PBMP_PORT_REMOVE(pbmp_valid, 28); 3460 SOC_PBMP_PORT_REMOVE(pbmp_valid, 29); 3461 } else { 3462 /* 48x1GE + 4x16HG */ 3463 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3464 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3465 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3466 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3467 SOC_PBMP_ASSIGN(pbmp_gx16g, pbmp_tmp); 3468 } 3469 SOC_PBMP_CLEAR(pbmp_tmp); 3470 for (port = 30; port <= 53; port++) { 3471 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3472 } 3473 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3474 SOC_PBMP_AND(pbmp_xq, pbmp_valid); 3475 SOC_PBMP_ASSIGN(pbmp_hyplite, pbmp_xq); 3476 break; 3477 case BCM56636_DEVICE_ID: 3478 for (port = 14; port <= 25; port++) { 3479 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3480 } 3481 for (port = 43; port <= 49; port++) { 3482 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3483 } 3484 for (port = 51; port <= 53; port++) { 3485 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3486 } 3487 SOC_PBMP_CLEAR(pbmp_tmp); 3488 SOC_PBMP_PORT_ADD(pbmp_tmp, 42); 3489 SOC_PBMP_PORT_ADD(pbmp_tmp, 50); 3490 if (soc_property_get(unit, spn_BCM56636_2X12_2X24, 0)) { 3491 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 3492 SOC_PBMP_PORT_REMOVE(pbmp_valid, 28); 3493 SOC_PBMP_PORT_REMOVE(pbmp_valid, 29); 3494 SOC_PBMP_CLEAR(pbmp_tmp); 3495 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3496 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3497 SOC_PBMP_ASSIGN(pbmp_gx25g, pbmp_tmp); 3498 } else if (soc_property_get(unit, spn_BCM56636_24G_6X12, 0)) { 3499 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 3500 SOC_PBMP_CLEAR(pbmp_tmp); 3501 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3502 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3503 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3504 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3505 SOC_PBMP_ASSIGN(pbmp_gx13g, pbmp_tmp); 3506 } else { 3507 SOC_PBMP_ASSIGN(pbmp_xq12g, pbmp_tmp); 3508 SOC_PBMP_CLEAR(pbmp_tmp); 3509 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3510 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3511 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3512 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3513 SOC_PBMP_ASSIGN(pbmp_gx16g, pbmp_tmp); 3514 } 3515 SOC_PBMP_CLEAR(pbmp_tmp); 3516 for (port = 30; port <= 53; port++) { 3517 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3518 } 3519 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3520 SOC_PBMP_AND(pbmp_xq, pbmp_valid); 3521 SOC_PBMP_ASSIGN(pbmp_hyplite, pbmp_xq); 3522 3523 /* Flex-port support */ 3524 3525 /* For each possible controlling port, ... */ 3526 for (port = 30; port <= 50; port += 4) { 3527 if (!SOC_PBMP_MEMBER(pbmp_valid, port)) continue; 3528 3529 /* Controlling port is valid port 3530 => Add corresponding subsidiary ports as valid 3531 */ 3532 3533 SOC_PBMP_PORT_ADD(pbmp_valid, port + 1); 3534 SOC_PBMP_PORT_ADD(pbmp_valid, port + 2); 3535 SOC_PBMP_PORT_ADD(pbmp_valid, port + 3); 3536 3537 if (SOC_PBMP_MEMBER(pbmp_xq10g, port) 3538 || SOC_PBMP_MEMBER(pbmp_xq12g, port) 3539 || SOC_PBMP_MEMBER(pbmp_xq13g, port) 3540 ) { 3541 /* Controlling port not in 1G mode 3542 => Mark corresponding subsidiary ports as disabled 3543 */ 3544 3545 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 1); 3546 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 2); 3547 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 3); 3548 } 3549 } 3550 3551 break; 3552 case BCM56638_DEVICE_ID: 3553 for (port = 2; port <= 25; port++) { 3554 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3555 } 3556 for (port = 31; port <= 37; port++) { 3557 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3558 } 3559 for (port = 39; port <= 41; port++) { 3560 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3561 } 3562 for (port = 43; port <= 49; port++) { 3563 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3564 } 3565 for (port = 51; port <= 53; port++) { 3566 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3567 } 3568 SOC_PBMP_CLEAR(pbmp_tmp); 3569 SOC_PBMP_PORT_ADD(pbmp_tmp, 30); 3570 SOC_PBMP_PORT_ADD(pbmp_tmp, 38); 3571 SOC_PBMP_PORT_ADD(pbmp_tmp, 42); 3572 SOC_PBMP_PORT_ADD(pbmp_tmp, 50); 3573 if (soc_property_get(unit, spn_BCM56638_4X12_2X24, 0)) { 3574 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 3575 SOC_PBMP_PORT_REMOVE(pbmp_valid, 28); 3576 SOC_PBMP_PORT_REMOVE(pbmp_valid, 29); 3577 SOC_PBMP_CLEAR(pbmp_tmp); 3578 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3579 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3580 SOC_PBMP_ASSIGN(pbmp_gx25g, pbmp_tmp); 3581 } else if (soc_property_get(unit, spn_BCM56638_8X12, 0)) { 3582 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 3583 SOC_PBMP_CLEAR(pbmp_tmp); 3584 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3585 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3586 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3587 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3588 SOC_PBMP_ASSIGN(pbmp_gx13g, pbmp_tmp); 3589 } else { 3590 SOC_PBMP_ASSIGN(pbmp_xq12g, pbmp_tmp); 3591 SOC_PBMP_CLEAR(pbmp_tmp); 3592 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3593 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3594 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3595 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3596 SOC_PBMP_ASSIGN(pbmp_gx16g, pbmp_tmp); 3597 } 3598 SOC_PBMP_CLEAR(pbmp_tmp); 3599 for (port = 30; port <= 53; port++) { 3600 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3601 } 3602 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3603 SOC_PBMP_AND(pbmp_xq, pbmp_valid); 3604 SOC_PBMP_ASSIGN(pbmp_hyplite, pbmp_xq); 3605 3606 /* Flex-port support */ 3607 3608 /* For each possible controlling port, ... */ 3609 for (port = 30; port <= 50; port += 4) { 3610 if (!SOC_PBMP_MEMBER(pbmp_valid, port)) continue; 3611 3612 /* Controlling port is valid port 3613 => Add corresponding subsidiary ports as valid 3614 */ 3615 3616 SOC_PBMP_PORT_ADD(pbmp_valid, port + 1); 3617 SOC_PBMP_PORT_ADD(pbmp_valid, port + 2); 3618 SOC_PBMP_PORT_ADD(pbmp_valid, port + 3); 3619 3620 if (SOC_PBMP_MEMBER(pbmp_xq10g, port) 3621 || SOC_PBMP_MEMBER(pbmp_xq12g, port) 3622 || SOC_PBMP_MEMBER(pbmp_xq13g, port) 3623 ) { 3624 /* Controlling port not in 1G mode 3625 => Mark corresponding subsidiary ports as disabled 3626 */ 3627 3628 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 1); 3629 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 2); 3630 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 3); 3631 } 3632 } 3633 3634 break; 3635 3636 case BCM56639_DEVICE_ID: 3637 for (port = 34; port <= 37; port++) { 3638 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3639 } 3640 for (port = 46; port <= 49; port++) { 3641 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3642 } 3643 SOC_PBMP_CLEAR(pbmp_tmp); 3644 SOC_PBMP_PORT_ADD(pbmp_tmp, 30); 3645 SOC_PBMP_PORT_ADD(pbmp_tmp, 38); 3646 SOC_PBMP_PORT_ADD(pbmp_tmp, 42); 3647 SOC_PBMP_PORT_ADD(pbmp_tmp, 50); 3648 SOC_PBMP_ASSIGN(pbmp_xq10g, pbmp_tmp); 3649 if (soc_property_get(unit, spn_BCM56639_28G_7X10, 0)) { 3650 /* 28x1GE + 7x10G + loopback */ 3651 SOC_PBMP_PORT_REMOVE(pbmp_valid, 26); 3652 SOC_PBMP_PORT_ADD(pbmp_valid, 46); 3653 SOC_PBMP_PORT_ADD(pbmp_valid, 47); 3654 SOC_PBMP_PORT_ADD(pbmp_valid, 48); 3655 SOC_PBMP_PORT_ADD(pbmp_valid, 49); 3656 } 3657 3658 SOC_PBMP_CLEAR(pbmp_tmp); 3659 for (port = 30; port <= 53; port++) { 3660 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3661 } 3662 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3663 SOC_PBMP_AND(pbmp_xq, pbmp_valid); 3664 SOC_PBMP_ASSIGN(pbmp_hyplite, pbmp_xq); 3665 3666 /* Flex-port support */ 3667 3668 /* For each possible controlling port, ... */ 3669 for (port = 30; port <= 50; port += 4) { 3670 if (!SOC_PBMP_MEMBER(pbmp_valid, port)) continue; 3671 3672 /* Controlling port is valid port 3673 => Add corresponding subsidiary ports as valid 3674 */ 3675 3676 SOC_PBMP_PORT_ADD(pbmp_valid, port + 1); 3677 SOC_PBMP_PORT_ADD(pbmp_valid, port + 2); 3678 SOC_PBMP_PORT_ADD(pbmp_valid, port + 3); 3679 3680 if (SOC_PBMP_MEMBER(pbmp_xq10g, port) 3681 || SOC_PBMP_MEMBER(pbmp_xq12g, port) 3682 || SOC_PBMP_MEMBER(pbmp_xq13g, port) 3683 ) { 3684 /* Controlling port not in 1G mode 3685 => Mark corresponding subsidiary ports as disabled 3686 */ 3687 3688 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 1); 3689 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 2); 3690 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 3); 3691 } 3692 } 3693 3694 break; 3695 case BCM56689_DEVICE_ID: 3696 SOC_PBMP_PORT_REMOVE(pbmp_valid, 1); 3697 /* Fall through */ 3698 case BCM56685_DEVICE_ID: 3699 SOC_PBMP_CLEAR(pbmp_tmp); 3700 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3701 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3702 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3703 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3704 SOC_PBMP_ASSIGN(pbmp_gx12g, pbmp_tmp); 3705 SOC_PBMP_ASSIGN(pbmp_xq2p5g, pbmp_valid); 3706 SOC_PBMP_REMOVE(pbmp_xq2p5g, pbmp_gx12g); 3707 SOC_PBMP_CLEAR(pbmp_tmp); 3708 for (port = 30; port <= 53; port++) { 3709 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3710 } 3711 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3712 SOC_PBMP_AND(pbmp_xq, pbmp_valid); 3713 SOC_PBMP_ASSIGN(pbmp_hyplite, pbmp_xq); 3714 break; 3715 case BCM56520_DEVICE_ID: 3716 for (port = 1; port <= 29; port++) { 3717 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3718 } 3719 SOC_PBMP_CLEAR(pbmp_tmp); 3720 for (port = 30; port <= 53; port++) { 3721 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3722 } 3723 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3724 SOC_PBMP_AND(pbmp_xq, pbmp_valid); 3725 SOC_PBMP_ASSIGN(pbmp_hyplite, pbmp_xq); 3726 break; 3727 case BCM56521_DEVICE_ID: 3728 SOC_PBMP_PORT_REMOVE(pbmp_valid, 1); 3729 for (port = 30; port <= 53; port++) { 3730 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3731 } 3732 SOC_PBMP_CLEAR(pbmp_tmp); 3733 if (soc_property_get(unit, spn_BCM56521_2X12_2X24, 0)) { 3734 /* 28x1GE + 2x12HG + 2x24HG + loopback */ 3735 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3736 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3737 SOC_PBMP_ASSIGN(pbmp_gx25g, pbmp_tmp); 3738 SOC_PBMP_CLEAR(pbmp_tmp); 3739 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3740 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3741 SOC_PBMP_ASSIGN(pbmp_gx13g, pbmp_tmp); 3742 } else { 3743 /* 24x1GE + 4x20HG + loopback */ 3744 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3745 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3746 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3747 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3748 if (soc_property_get(unit, spn_HIGIG_MAX_SPEED, 0) == 12000) { 3749 SOC_PBMP_ASSIGN(pbmp_gx12g, pbmp_tmp); 3750 } else { 3751 SOC_PBMP_ASSIGN(pbmp_gx20g, pbmp_tmp); 3752 } 3753 } 3754 break; 3755 case BCM56522_DEVICE_ID: 3756 for (port = 1; port <= 25; port++) { 3757 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3758 } 3759 for (port = 28; port <= 29; port++) { 3760 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3761 } 3762 SOC_PBMP_CLEAR(pbmp_tmp); 3763 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3764 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3765 if (soc_property_get(unit, spn_HIGIG_MAX_SPEED, 0) == 12000) { 3766 SOC_PBMP_ASSIGN(pbmp_gx12g, pbmp_tmp); 3767 } else { 3768 SOC_PBMP_ASSIGN(pbmp_gx25g, pbmp_tmp); 3769 } 3770 SOC_PBMP_CLEAR(pbmp_tmp); 3771 for (port = 30; port <= 53; port++) { 3772 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3773 } 3774 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3775 SOC_PBMP_AND(pbmp_xq, pbmp_valid); 3776 SOC_PBMP_ASSIGN(pbmp_hyplite, pbmp_xq); 3777 break; 3778 case BCM56524_DEVICE_ID: 3779 /* Fall through */ 3780 case BCM56534_DEVICE_ID: 3781 for (port = 1; port <= 25; port++) { 3782 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3783 } 3784 SOC_PBMP_CLEAR(pbmp_tmp); 3785 if (soc_property_get(unit, spn_BCM56524_2X12_2X24, 0) || 3786 soc_property_get(unit, spn_BCM56534_2X12_2X24, 0)) { 3787 /* 28x1GE + 2x12HG + 2x24HG + loopback */ 3788 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3789 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3790 SOC_PBMP_ASSIGN(pbmp_gx25g, pbmp_tmp); 3791 SOC_PBMP_CLEAR(pbmp_tmp); 3792 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3793 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3794 SOC_PBMP_ASSIGN(pbmp_gx13g, pbmp_tmp); 3795 } else { 3796 /* 24x1GE + 4x20HG + loopback */ 3797 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3798 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3799 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3800 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3801 if (soc_property_get(unit, spn_HIGIG_MAX_SPEED, 0) == 12000) { 3802 SOC_PBMP_ASSIGN(pbmp_gx12g, pbmp_tmp); 3803 } else { 3804 SOC_PBMP_ASSIGN(pbmp_gx20g, pbmp_tmp); 3805 } 3806 } 3807 SOC_PBMP_CLEAR(pbmp_tmp); 3808 for (port = 30; port <= 53; port++) { 3809 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3810 } 3811 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3812 SOC_PBMP_AND(pbmp_xq, pbmp_valid); 3813 SOC_PBMP_ASSIGN(pbmp_hyplite, pbmp_xq); 3814 break; 3815 case BCM56526_DEVICE_ID: 3816 for (port = 30; port <= 37; port++) { 3817 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3818 } 3819 for (port = 42; port <= 45; port++) { 3820 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3821 } 3822 for (port = 47; port <= 49; port++) { 3823 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3824 } 3825 for (port = 51; port <= 53; port++) { 3826 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3827 } 3828 SOC_PBMP_CLEAR(pbmp_tmp); 3829 SOC_PBMP_PORT_ADD(pbmp_tmp, 26); 3830 SOC_PBMP_PORT_ADD(pbmp_tmp, 27); 3831 SOC_PBMP_PORT_ADD(pbmp_tmp, 28); 3832 SOC_PBMP_PORT_ADD(pbmp_tmp, 29); 3833 if (soc_property_get(unit, spn_BCM56526_2X12_4X16, 0)) { 3834 SOC_PBMP_ASSIGN(pbmp_gx16g, pbmp_tmp); 3835 for (port = 38; port <= 41; port++) { 3836 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3837 } 3838 SOC_PBMP_CLEAR(pbmp_tmp); 3839 SOC_PBMP_PORT_ADD(pbmp_tmp, 46); 3840 SOC_PBMP_PORT_ADD(pbmp_tmp, 50); 3841 SOC_PBMP_ASSIGN(pbmp_xq12g, pbmp_tmp); 3842 } else { 3843 SOC_PBMP_ASSIGN(pbmp_gx13g, pbmp_tmp); 3844 SOC_PBMP_CLEAR(pbmp_tmp); 3845 SOC_PBMP_PORT_ADD(pbmp_tmp, 46); 3846 SOC_PBMP_PORT_ADD(pbmp_tmp, 50); 3847 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 3848 } 3849 SOC_PBMP_CLEAR(pbmp_tmp); 3850 for (port = 30; port <= 53; port++) { 3851 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3852 } 3853 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3854 SOC_PBMP_AND(pbmp_xq, pbmp_valid); 3855 SOC_PBMP_ASSIGN(pbmp_hyplite, pbmp_xq); 3856 3857 /* Flex-port support */ 3858 3859 /* For each possible controlling port, ... */ 3860 for (port = 30; port <= 50; port += 4) { 3861 if (!SOC_PBMP_MEMBER(pbmp_valid, port)) continue; 3862 3863 /* Controlling port is valid port 3864 => Add corresponding subsidiary ports as valid 3865 */ 3866 3867 SOC_PBMP_PORT_ADD(pbmp_valid, port + 1); 3868 SOC_PBMP_PORT_ADD(pbmp_valid, port + 2); 3869 SOC_PBMP_PORT_ADD(pbmp_valid, port + 3); 3870 3871 if (SOC_PBMP_MEMBER(pbmp_xq10g, port) 3872 || SOC_PBMP_MEMBER(pbmp_xq12g, port) 3873 || SOC_PBMP_MEMBER(pbmp_xq13g, port) 3874 ) { 3875 /* Controlling port not in 1G mode 3876 => Mark corresponding subsidiary ports as disabled 3877 */ 3878 3879 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 1); 3880 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 2); 3881 SOC_PBMP_PORT_ADD(pbmp_disabled, port + 3); 3882 } 3883 } 3884 3885 break; 3886 3887 #if defined(BCM_ENDURO_SUPPORT) 3888 case BCM56132_DEVICE_ID: 3889 /* 24 + 2 + 2 ports */ 3890 for (port = 30; port <= 31; port++) { 3891 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3892 } 3893 if(dev_id == BCM56132_DEVICE_ID) { 3894 SOC_PBMP_CLEAR(pbmp_tmp); 3895 for (port = 2; port <= 25; port++) { 3896 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3897 } 3898 SOC_PBMP_ASSIGN(pbmp_gport_fe, pbmp_tmp); 3899 } 3900 SOC_PBMP_CLEAR(pbmp_tmp); 3901 for (port = 26; port <= 27; port++) { 3902 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3903 } 3904 SOC_PBMP_ASSIGN(pbmp_xq2p5g, pbmp_tmp); 3905 SOC_PBMP_CLEAR(pbmp_tmp); 3906 for (port = 28; port <= 29; port++) { 3907 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3908 } 3909 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 3910 SOC_PBMP_CLEAR(pbmp_tmp); 3911 for (port = 26; port <= 29; port++) { 3912 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3913 } 3914 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3915 3916 SOC_PBMP_PORT_ADD(pbmp_tmp, 1); 3917 SOC_PBMP_AND(si->lb_pbm, pbmp_tmp); 3918 break; 3919 case BCM56134_DEVICE_ID: 3920 case BCM56331_DEVICE_ID: 3921 /* 24 + 4 ports */ 3922 for (port = 30; port <= 31; port++) { 3923 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3924 } 3925 if(dev_id == BCM56134_DEVICE_ID) { 3926 SOC_PBMP_CLEAR(pbmp_tmp); 3927 for (port = 2; port <= 25; port++) { 3928 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3929 } 3930 SOC_PBMP_ASSIGN(pbmp_gport_fe, pbmp_tmp); 3931 } 3932 SOC_PBMP_CLEAR(pbmp_tmp); 3933 for (port = 26; port <= 29; port++) { 3934 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3935 } 3936 SOC_PBMP_ASSIGN(pbmp_xq2p5g, pbmp_tmp); 3937 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3938 3939 SOC_PBMP_PORT_ADD(pbmp_tmp, 1); 3940 SOC_PBMP_AND(si->lb_pbm, pbmp_tmp); 3941 break; 3942 case BCM56334_DEVICE_ID: 3943 case BCM56320_DEVICE_ID: 3944 case BCM56321_DEVICE_ID: 3945 /* 24 + 4 ports */ 3946 for (port = 30; port <= 31; port++) { 3947 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3948 } 3949 SOC_PBMP_CLEAR(pbmp_tmp); 3950 for (port = 26; port <= 29; port++) { 3951 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3952 } 3953 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 3954 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3955 3956 SOC_PBMP_PORT_ADD(pbmp_tmp, 1); 3957 SOC_PBMP_AND(si->lb_pbm, pbmp_tmp); 3958 break; 3959 case BCM56333_DEVICE_ID: 3960 /* 16 ports */ 3961 for (port = 18; port <= 31; port++) { 3962 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3963 } 3964 SOC_PBMP_CLEAR(pbmp_tmp); 3965 SOC_PBMP_PORT_ADD(pbmp_tmp, 1); 3966 SOC_PBMP_AND(si->lb_pbm, pbmp_tmp); 3967 break; 3968 case BCM56338_DEVICE_ID: 3969 /* 8 + 2 ports */ 3970 for (port = 10; port <= 25; port++) { 3971 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3972 } 3973 for (port = 28; port <= 31; port++) { 3974 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3975 } 3976 SOC_PBMP_CLEAR(pbmp_tmp); 3977 for (port = 26; port <= 27; port++) { 3978 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 3979 } 3980 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 3981 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 3982 3983 SOC_PBMP_PORT_ADD(pbmp_tmp, 1); 3984 SOC_PBMP_AND(si->lb_pbm, pbmp_tmp); 3985 break; 3986 case BCM56230_DEVICE_ID: 3987 /* 12 ports */ 3988 for (port = 14; port <= 31; port++) { 3989 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3990 } 3991 SOC_PBMP_CLEAR(pbmp_tmp); 3992 SOC_PBMP_PORT_ADD(pbmp_tmp, 1); 3993 SOC_PBMP_AND(si->lb_pbm, pbmp_tmp); 3994 break; 3995 case BCM56231_DEVICE_ID: 3996 /* 6 ports */ 3997 for (port = 8; port <= 31; port++) { 3998 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 3999 } 4000 SOC_PBMP_CLEAR(pbmp_tmp); 4001 SOC_PBMP_PORT_ADD(pbmp_tmp, 1); 4002 SOC_PBMP_AND(si->lb_pbm, pbmp_tmp); 4003 break; 4004 #endif /* BCM_ENDURO_SUPPORT */ 4005 4006 #if defined(BCM_HURRICANE2_SUPPORT) 4007 case BCM56150_DEVICE_ID: 4008 case BCM56151_DEVICE_ID: 4009 case BCM56152_DEVICE_ID: 4010 case BCM53342_DEVICE_ID: 4011 case BCM53343_DEVICE_ID: 4012 case BCM53344_DEVICE_ID: 4013 case BCM53346_DEVICE_ID: 4014 case BCM53347_DEVICE_ID: 4015 case BCM53333_DEVICE_ID: 4016 case BCM53334_DEVICE_ID: 4017 case BCM53393_DEVICE_ID: 4018 case BCM53394_DEVICE_ID: 4019 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4020 if (soc_hu2_port_config_init(unit, dev_id) < 0) { 4021 LOG_ERROR(BSL_LS_SOC_COMMON, 4022 (BSL_META_U(unit, 4023 "Port config error !!\n"))); 4024 return SOC_E_CONFIG; 4025 } 4026 SOC_PBMP_CLEAR(si->lb_pbm); 4027 break; 4028 #endif /* BCM_HURRICANE2_SUPPORT */ 4029 4030 #if defined(BCM_HURRICANE3_SUPPORT) 4031 case BCM56160_DEVICE_ID: 4032 case BCM56162_DEVICE_ID: 4033 case BCM56163_DEVICE_ID: 4034 case BCM56164_DEVICE_ID: 4035 case BCM56166_DEVICE_ID: 4036 case BCM53440_DEVICE_ID: 4037 case BCM53443_DEVICE_ID: 4038 case BCM53442_DEVICE_ID: 4039 case BCM53434_DEVICE_ID: 4040 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4041 if (soc_hurricane3_port_config_init(unit, dev_id) < 0) { 4042 LOG_ERROR(BSL_LS_SOC_COMMON, 4043 (BSL_META_U(unit, "Port config error !!\n"))); 4044 return SOC_E_CONFIG; 4045 } 4046 SOC_PBMP_CLEAR(si->lb_pbm); 4047 break; 4048 case BCM53540_DEVICE_ID: 4049 case BCM53547_DEVICE_ID: 4050 case BCM53548_DEVICE_ID: 4051 case BCM53549_DEVICE_ID: 4052 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4053 if (soc_wolfhound2_port_config_init(unit, dev_id) < 0) { 4054 LOG_ERROR(BSL_LS_SOC_COMMON, 4055 (BSL_META_U(unit, "Port config error !!\n"))); 4056 return SOC_E_CONFIG; 4057 } 4058 SOC_PBMP_CLEAR(si->lb_pbm); 4059 break; 4060 #endif /* BCM_HURRICANE3_SUPPORT */ 4061 4062 4063 #if defined(BCM_GREYHOUND2_SUPPORT) 4064 case BCM56170_DEVICE_ID: 4065 case BCM56172_DEVICE_ID: 4066 case BCM56174_DEVICE_ID: 4067 case BCM53570_DEVICE_ID: 4068 case BCM53575_DEVICE_ID: 4069 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4070 /* coverity[stack_use_callee : FALSE] */ 4071 /* coverity[stack_use_overflow : FALSE] */ 4072 if (soc_greyhound2_port_config_init(unit, dev_id) < 0) { 4073 LOG_ERROR(BSL_LS_SOC_COMMON, 4074 (BSL_META_U(unit, "Port config error !!\n"))); 4075 return SOC_E_CONFIG; 4076 } 4077 4078 if (soc_feature(unit, soc_feature_global_meter)) { 4079 si->global_meter_pools = 1; 4080 /* size of SVM_METER_TABLE, divide by 2 for exceed/commit */ 4081 si->global_meter_size_of_pool = 4082 soc_mem_index_count(unit, SVM_METER_TABLEm) / 2; 4083 si->global_meter_max_size_of_pool = 4084 soc_mem_index_count(unit, SVM_METER_TABLEm) / 2; 4085 si->num_flex_ingress_pools = 0; 4086 si->num_flex_egress_pools = 0; 4087 si->global_meter_tcam_size = 4088 soc_mem_index_count(unit, SVC_METER_OFFSET_TCAMm); 4089 si->global_meter_offset_mode_max = 4090 (1 << soc_mem_field_length(unit, SVC_METER_OFFSET_TCAMm, 4091 OFFSET_MODEf)); 4092 si->global_meter_action_size = 4093 soc_mem_index_count(unit, SVM_POLICY_TABLEm); 4094 } else { 4095 si->global_meter_pools = 0; 4096 si->global_meter_size_of_pool = 0; 4097 si->global_meter_max_size_of_pool = 0; 4098 si->num_flex_ingress_pools = 0; 4099 si->num_flex_egress_pools = 0; 4100 si->global_meter_tcam_size = 0; 4101 si->global_meter_offset_mode_max = 0; 4102 si->global_meter_action_size = 0; 4103 } 4104 break; 4105 #endif /* BCM_GREYHOUND2_SUPPORT */ 4106 4107 #if defined(BCM_GREYHOUND_SUPPORT) 4108 case BCM53400_DEVICE_ID: 4109 case BCM53401_DEVICE_ID: 4110 case BCM53402_DEVICE_ID: 4111 case BCM53403_DEVICE_ID: 4112 case BCM53404_DEVICE_ID: 4113 case BCM53405_DEVICE_ID: 4114 case BCM53365_DEVICE_ID: 4115 case BCM53406_DEVICE_ID: 4116 case BCM53369_DEVICE_ID: 4117 case BCM53408_DEVICE_ID: 4118 case BCM56060_DEVICE_ID: 4119 case BCM56062_DEVICE_ID: 4120 case BCM56063_DEVICE_ID: 4121 case BCM56064_DEVICE_ID: 4122 case BCM56065_DEVICE_ID: 4123 case BCM56066_DEVICE_ID: 4124 case BCM53454_DEVICE_ID: 4125 case BCM53456_DEVICE_ID: 4126 case BCM53422_DEVICE_ID: 4127 case BCM53424_DEVICE_ID: 4128 case BCM53426_DEVICE_ID: 4129 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4130 if (soc_greyhound_port_config_init(unit, dev_id) < 0) { 4131 LOG_ERROR(BSL_LS_SOC_COMMON, 4132 (BSL_META_U(unit, 4133 "Port config error !!"))); 4134 return SOC_E_CONFIG; 4135 } 4136 SOC_PBMP_CLEAR(si->lb_pbm); 4137 break; 4138 #endif /* BCM_GREYHOUND_SUPPORT */ 4139 #if defined(BCM_HURRICANE_SUPPORT) 4140 case BCM56140_DEVICE_ID: 4141 if (!soc_property_get(unit, spn_BCM5614X_CONFIG, 0)) { 4142 for (port = 2; port <= 25; port++) { 4143 if ((port-2)%4) { 4144 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4145 } 4146 } 4147 } 4148 SOC_PBMP_CLEAR(pbmp_tmp); 4149 for (port = 26; port <= 29; port++) { 4150 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4151 si->port_speed_max[port] = 2500; 4152 } 4153 if (!SOC_PBMP_MEMBER(pbmp_valid, 27)) { 4154 /* Make Port 26 as HG[13] */ 4155 SOC_PBMP_PORT_REMOVE(pbmp_tmp, 26); 4156 SOC_PBMP_PORT_REMOVE(pbmp_tmp, 27); 4157 SOC_PBMP_PORT_ADD(pbmp_xq13g, 26); 4158 si->port_speed_max[26] = 13000; 4159 } 4160 if (!SOC_PBMP_MEMBER(pbmp_valid, 29)) { 4161 /* Make Port 28 as HG[13] */ 4162 SOC_PBMP_PORT_REMOVE(pbmp_tmp, 28); 4163 SOC_PBMP_PORT_REMOVE(pbmp_tmp, 29); 4164 SOC_PBMP_PORT_ADD(pbmp_xq13g, 28); 4165 si->port_speed_max[28] = 13000; 4166 } 4167 SOC_PBMP_ASSIGN(pbmp_xq2p5g, pbmp_tmp); 4168 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 4169 SOC_PBMP_OR(pbmp_xq, pbmp_xq13g); 4170 SOC_PBMP_CLEAR(si->lb_pbm); 4171 break; 4172 case BCM56142_DEVICE_ID: 4173 SOC_PBMP_CLEAR(pbmp_tmp); 4174 for (port = 26; port <= 29; port++) { 4175 /* Full Capacity (24x1G + 4xHGd) for testing */ 4176 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4177 } 4178 if (soc_property_get(unit, spn_BCM5614X_CONFIG, 1) == 2) { 4179 /* 24x1G + 2HG */ 4180 SOC_PBMP_PORT_REMOVE(pbmp_valid, 27); 4181 SOC_PBMP_PORT_REMOVE(pbmp_valid, 29); 4182 SOC_PBMP_PORT_REMOVE(pbmp_tmp, 27); 4183 SOC_PBMP_PORT_REMOVE(pbmp_tmp, 29); 4184 } else if (soc_property_get(unit, spn_BCM5614X_CONFIG, 1) != 0) { 4185 /* 24x1G + 1xHG + 2xHGd (dxgxs=1) or 4186 24x1G + 2xHGd + 1xHG (dxgxs=0)*/ 4187 SOC_PBMP_PORT_REMOVE(pbmp_valid, dxgxs ? 27 : 29); 4188 SOC_PBMP_PORT_REMOVE(pbmp_tmp, dxgxs ? 27 : 29); 4189 } 4190 4191 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 4192 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 4193 4194 /* For HGd ports, 12.768 GB is set as 12G */ 4195 if (dxgxs) { 4196 si->port_speed_max[28] = 12000; 4197 si->port_speed_max[29] = 12000; 4198 } else { 4199 si->port_speed_max[26] = 12000; 4200 si->port_speed_max[27] = 12000; 4201 } 4202 4203 if (soc_property_get(unit, spn_BCM5614X_CONFIG, 1) == 2) { 4204 if (SOC_PBMP_MEMBER(pbmp_valid, 26)) { 4205 si->port_speed_max[26] = 13000; 4206 } 4207 if (SOC_PBMP_MEMBER(pbmp_valid, 28)) { 4208 si->port_speed_max[28] = 13000; 4209 } 4210 } else { 4211 if (SOC_PBMP_MEMBER(pbmp_valid, 27)) { 4212 si->port_speed_max[26] = 12000; 4213 si->port_speed_max[27] = 12000; 4214 } else { 4215 si->port_speed_max[26] = 13000; 4216 } 4217 if (SOC_PBMP_MEMBER(pbmp_valid, 29)) { 4218 si->port_speed_max[28] = 12000; 4219 si->port_speed_max[29] = 12000; 4220 } else { 4221 si->port_speed_max[28] = 13000; 4222 } 4223 } 4224 4225 for (port = 30; port <= 31; port++) { 4226 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4227 } 4228 SOC_PBMP_CLEAR(si->lb_pbm); 4229 break; 4230 case BCM56143_DEVICE_ID: 4231 if (!soc_property_get(unit, spn_BCM5614X_CONFIG, 0)) { 4232 /* 24x1G + 2xHGdG + 2x2.5G (dxgxs=1) or 4233 24x1G + 2x2.5G + 2xHGd (dxgxs=0) */ 4234 SOC_PBMP_CLEAR(pbmp_tmp); 4235 for (port = 26; port <= 27; port++) { 4236 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4237 } 4238 if(dxgxs) { 4239 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 4240 } else { 4241 SOC_PBMP_ASSIGN(pbmp_xq2p5g, pbmp_tmp); 4242 } 4243 SOC_PBMP_CLEAR(pbmp_tmp); 4244 for (port = 28; port <= 29; port++) { 4245 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4246 } 4247 if(dxgxs) { 4248 SOC_PBMP_ASSIGN(pbmp_xq2p5g, pbmp_tmp); 4249 } else { 4250 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 4251 } 4252 SOC_PBMP_CLEAR(pbmp_tmp); 4253 for (port = 26; port <= 29; port++) { 4254 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4255 } 4256 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 4257 4258 for (port = 30; port <= 31; port++) { 4259 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4260 } 4261 SOC_PBMP_CLEAR(si->lb_pbm); 4262 } else { 4263 /* 24x1G + 4xG/4x2.5G */ 4264 SOC_PBMP_CLEAR(pbmp_tmp); 4265 for (port = 26; port <= 29; port++) { 4266 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4267 } 4268 SOC_PBMP_ASSIGN(pbmp_xq2p5g, pbmp_tmp); 4269 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 4270 si->port_speed_max[26] = 2500; 4271 si->port_speed_max[27] = 2500; 4272 si->port_speed_max[28] = 2500; 4273 si->port_speed_max[29] = 2500; 4274 } 4275 break; 4276 case BCM56144_DEVICE_ID: 4277 /* 16x1G + 2x2.5G + 2x2.5G */ 4278 for (port = 18; port <= 25; port++) { 4279 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4280 } 4281 SOC_PBMP_CLEAR(pbmp_tmp); 4282 for (port = 26; port <= 29; port++) { 4283 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4284 } 4285 SOC_PBMP_ASSIGN(pbmp_xq2p5g, pbmp_tmp); 4286 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 4287 SOC_PBMP_CLEAR(si->lb_pbm); 4288 si->port_speed_max[26] = 2500; 4289 si->port_speed_max[27] = 2500; 4290 si->port_speed_max[28] = 2500; 4291 si->port_speed_max[29] = 2500; 4292 break; 4293 case BCM56146_DEVICE_ID: 4294 /* 24xFE + 2x2.5G + 2x2.5G */ 4295 SOC_PBMP_CLEAR(pbmp_tmp); 4296 for (port = 2; port <= 25; port++) { 4297 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4298 si->port_speed_max[port] = 100; 4299 } 4300 SOC_PBMP_ASSIGN(pbmp_gport_fe, pbmp_tmp); 4301 4302 SOC_PBMP_CLEAR(pbmp_tmp); 4303 for (port = 26; port <= 29; port++) { 4304 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4305 si->port_speed_max[port] = 2500; 4306 } 4307 SOC_PBMP_ASSIGN(pbmp_xq2p5g, pbmp_tmp); 4308 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 4309 SOC_PBMP_CLEAR(si->lb_pbm); 4310 break; 4311 case BCM56147_DEVICE_ID: 4312 /* 24xFE + 1xHG + 2x2.5G */ 4313 SOC_PBMP_CLEAR(pbmp_tmp); 4314 for (port = 2; port <= 25; port++) { 4315 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4316 si->port_speed_max[port] = 100; 4317 } 4318 SOC_PBMP_ASSIGN(pbmp_gport_fe, pbmp_tmp); 4319 4320 SOC_PBMP_CLEAR(pbmp_tmp); 4321 SOC_PBMP_CLEAR(pbmp_xq13g); 4322 for (port = 26; port <= 29; port++) { 4323 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4324 si->port_speed_max[port] = 2500; 4325 } 4326 if (!soc_property_get(unit, spn_BCM5614X_CONFIG, 0)) { 4327 if (dxgxs) { 4328 /* Make Port 26 as HG[13] */ 4329 SOC_PBMP_PORT_REMOVE(pbmp_tmp, 26); 4330 SOC_PBMP_PORT_REMOVE(pbmp_tmp, 27); 4331 SOC_PBMP_PORT_REMOVE(pbmp_valid, 27); 4332 SOC_PBMP_PORT_ADD(pbmp_xq13g, 26); 4333 si->port_speed_max[26] = 13000; 4334 } else { 4335 /* Make Port 28 as HG[13] */ 4336 SOC_PBMP_PORT_REMOVE(pbmp_tmp, 28); 4337 SOC_PBMP_PORT_REMOVE(pbmp_tmp, 29); 4338 SOC_PBMP_PORT_REMOVE(pbmp_valid, 29); 4339 SOC_PBMP_PORT_ADD(pbmp_xq13g, 28); 4340 si->port_speed_max[28] = 13000; 4341 } 4342 } 4343 SOC_PBMP_ASSIGN(pbmp_xq2p5g, pbmp_tmp); 4344 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 4345 SOC_PBMP_OR(pbmp_xq, pbmp_xq13g); 4346 SOC_PBMP_CLEAR(si->lb_pbm); 4347 break; 4348 case BCM56149_DEVICE_ID: 4349 /* 24x1G + 2xXAUI + 2xHGd or 4350 24x1G + 2xHgd + 2xXAUI */ 4351 SOC_PBMP_CLEAR(pbmp_tmp); 4352 for (port = 26; port <= 29; port++) { 4353 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 4354 } 4355 SOC_PBMP_ASSIGN(pbmp_xq, pbmp_tmp); 4356 SOC_PBMP_ASSIGN(pbmp_xq13g, pbmp_tmp); 4357 4358 SOC_PBMP_CLEAR(pbmp_tmp); 4359 if (dxgxs) { 4360 /* 24x1G + 2xHgd + 2xXAUI */ 4361 if (!SOC_PBMP_MEMBER(pbmp_xport_xe, 26) && 4362 !SOC_PBMP_MEMBER(pbmp_xport_xe, 27)) { 4363 si->port_speed_max[26] = 12000; 4364 si->port_speed_max[27] = 12000; 4365 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, 0x0c000000); 4366 } 4367 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 28); 4368 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 29); 4369 } else { 4370 /* 24x1G + 2xXAUI + 2xHGd */ 4371 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 26); 4372 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 27); 4373 if (!SOC_PBMP_MEMBER(pbmp_xport_xe, 28) && 4374 !SOC_PBMP_MEMBER(pbmp_xport_xe, 29)) { 4375 si->port_speed_max[28] = 12000; 4376 si->port_speed_max[29] = 12000; 4377 SOC_PBMP_WORD_SET(pbmp_gport_stack, 0, 0x30000000); 4378 } 4379 } 4380 4381 for (port = 30; port <= 31; port++) { 4382 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4383 } 4384 SOC_PBMP_CLEAR(si->lb_pbm); 4385 break; 4386 #endif /* BCM_HURRICANE_SUPPORT */ 4387 4388 #ifdef BCM_TRIUMPH_SUPPORT 4389 case BCM56624_DEVICE_ID: 4390 SOC_PORT_SPEED_MAX_SET(unit, 28, 16000); 4391 SOC_PORT_SPEED_MAX_SET(unit, 29, 16000); 4392 SOC_PORT_SPEED_MAX_SET(unit, 30, 16000); 4393 SOC_PORT_SPEED_MAX_SET(unit, 31, 16000); 4394 for (port = 2; port <= 7; port++) { 4395 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4396 } 4397 for (port = 14; port <= 19; port++) { 4398 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4399 } 4400 for (port = 26; port <= 27; port++) { 4401 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4402 } 4403 for (port = 32; port <= 36; port++) { 4404 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4405 } 4406 for (port = 43; port <= 47; port++) { 4407 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4408 } 4409 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4410 break; 4411 case BCM56626_DEVICE_ID: 4412 for (port = 32; port <= 53; port++) { 4413 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4414 } 4415 SOC_PORT_SPEED_MAX_SET(unit, 26, 12000); 4416 SOC_PORT_SPEED_MAX_SET(unit, 27, 12000); 4417 SOC_PORT_SPEED_MAX_SET(unit, 28, 16000); 4418 SOC_PORT_SPEED_MAX_SET(unit, 29, 16000); 4419 SOC_PORT_SPEED_MAX_SET(unit, 30, 16000); 4420 SOC_PORT_SPEED_MAX_SET(unit, 31, 16000); 4421 for (port = 2; port <= 7; port++) { 4422 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4423 } 4424 for (port = 14; port <= 19; port++) { 4425 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4426 } 4427 for (port = 26; port <= 27; port++) { 4428 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4429 } 4430 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4431 break; 4432 case BCM56628_DEVICE_ID: 4433 for (port = 3; port <= 13; port++) { 4434 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4435 } 4436 for (port = 15; port <= 25; port++) { 4437 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4438 } 4439 for (port = 32; port <= 53; port++) { 4440 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4441 } 4442 SOC_PORT_SPEED_MAX_SET(unit, 2, 12000); 4443 SOC_PORT_SPEED_MAX_SET(unit, 14, 12000); 4444 SOC_PORT_SPEED_MAX_SET(unit, 26, 12000); 4445 SOC_PORT_SPEED_MAX_SET(unit, 27, 12000); 4446 SOC_PORT_SPEED_MAX_SET(unit, 28, 16000); 4447 SOC_PORT_SPEED_MAX_SET(unit, 29, 16000); 4448 SOC_PORT_SPEED_MAX_SET(unit, 30, 16000); 4449 SOC_PORT_SPEED_MAX_SET(unit, 31, 16000); 4450 for (port = 14; port <= 19; port++) { 4451 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4452 } 4453 for (port = 26; port <= 27; port++) { 4454 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4455 } 4456 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4457 break; 4458 case BCM56629_DEVICE_ID: 4459 if (soc_feature(unit, soc_feature_xgport_one_xe_six_ge)) { 4460 if (soc_property_get(unit, spn_BCM56629_40GE, 0)) { 4461 SOC_PBMP_PORT_REMOVE(pbmp_valid, 6); 4462 SOC_PBMP_PORT_REMOVE(pbmp_valid, 7); 4463 SOC_PBMP_PORT_REMOVE(pbmp_valid, 18); 4464 SOC_PBMP_PORT_REMOVE(pbmp_valid, 19); 4465 SOC_PBMP_PORT_REMOVE(pbmp_valid, 35); 4466 SOC_PBMP_PORT_REMOVE(pbmp_valid, 36); 4467 SOC_PBMP_PORT_REMOVE(pbmp_valid, 46); 4468 SOC_PBMP_PORT_REMOVE(pbmp_valid, 47); 4469 } else { 4470 for (port = 3; port <= 7; port++) { 4471 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4472 } 4473 for (port = 15; port <= 19; port++) { 4474 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4475 } 4476 for (port = 32; port <= 36; port++) { 4477 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4478 } 4479 for (port = 43; port <= 47; port++) { 4480 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4481 } 4482 SOC_PORT_SPEED_MAX_SET(unit, 2, 10000); 4483 SOC_PORT_SPEED_MAX_SET(unit, 14, 10000); 4484 SOC_PORT_SPEED_MAX_SET(unit, 26, 10000); 4485 SOC_PORT_SPEED_MAX_SET(unit, 27, 10000); 4486 } 4487 } else { 4488 for (port = 32; port <= 53; port++) { 4489 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4490 } 4491 SOC_PORT_SPEED_MAX_SET(unit, 26, 12000); 4492 SOC_PORT_SPEED_MAX_SET(unit, 27, 12000); 4493 } 4494 for (port = 2; port <= 7; port++) { 4495 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4496 } 4497 for (port = 14; port <= 19; port++) { 4498 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4499 } 4500 for (port = 26; port <= 27; port++) { 4501 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4502 } 4503 for (port = 32; port <= 36; port++) { 4504 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4505 } 4506 for (port = 43; port <= 47; port++) { 4507 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4508 } 4509 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4510 SOC_PORT_SPEED_MAX_SET(unit, 28, 12000); 4511 SOC_PORT_SPEED_MAX_SET(unit, 29, 12000); 4512 SOC_PORT_SPEED_MAX_SET(unit, 30, 12000); 4513 SOC_PORT_SPEED_MAX_SET(unit, 31, 12000); 4514 break; 4515 case BCM56620_DEVICE_ID: 4516 SOC_PBMP_PORT_REMOVE(pbmp_valid, 1); 4517 SOC_PORT_SPEED_MAX_SET(unit, 28, 16000); 4518 SOC_PORT_SPEED_MAX_SET(unit, 29, 16000); 4519 SOC_PORT_SPEED_MAX_SET(unit, 30, 16000); 4520 SOC_PORT_SPEED_MAX_SET(unit, 31, 16000); 4521 for (port = 2; port <= 7; port++) { 4522 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4523 } 4524 for (port = 14; port <= 19; port++) { 4525 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4526 } 4527 for (port = 26; port <= 27; port++) { 4528 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4529 } 4530 for (port = 32; port <= 36; port++) { 4531 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4532 } 4533 for (port = 43; port <= 47; port++) { 4534 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4535 } 4536 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4537 break; 4538 case BCM56684_DEVICE_ID: 4539 SOC_PBMP_PORT_REMOVE(pbmp_valid, 1); 4540 /* Fall through */ 4541 case BCM56680_DEVICE_ID: 4542 SOC_PBMP_CLEAR(pbmp_tmp); 4543 SOC_PORT_SPEED_MAX_SET(unit, 28, 12000); 4544 SOC_PORT_SPEED_MAX_SET(unit, 29, 12000); 4545 SOC_PORT_SPEED_MAX_SET(unit, 30, 12000); 4546 SOC_PORT_SPEED_MAX_SET(unit, 31, 12000); 4547 SOC_PBMP_ASSIGN(pbmp_xg2p5g, pbmp_valid); 4548 SOC_PBMP_PORT_REMOVE(pbmp_xg2p5g, 28); 4549 SOC_PBMP_PORT_REMOVE(pbmp_xg2p5g, 29); 4550 SOC_PBMP_PORT_REMOVE(pbmp_xg2p5g, 30); 4551 SOC_PBMP_PORT_REMOVE(pbmp_xg2p5g, 31); 4552 for (port = 2; port <= 7; port++) { 4553 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4554 } 4555 for (port = 14; port <= 19; port++) { 4556 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4557 } 4558 for (port = 26; port <= 27; port++) { 4559 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4560 } 4561 for (port = 32; port <= 36; port++) { 4562 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4563 } 4564 for (port = 43; port <= 47; port++) { 4565 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4566 } 4567 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4568 break; 4569 case BCM56686_DEVICE_ID: 4570 SOC_PBMP_PORT_REMOVE(pbmp_valid, 1); 4571 for (port = 3; port <= 13; port++) { 4572 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4573 } 4574 for (port = 14; port <= 26; port++) { 4575 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4576 } 4577 for (port = 32; port <= 36; port++) { 4578 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4579 } 4580 for (port = 43; port <= 47; port++) { 4581 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4582 } 4583 /* coverity[result_independent_of_operands] */ 4584 SOC_PORT_SPEED_MAX_SET(unit, 2, 10000); 4585 SOC_PORT_SPEED_MAX_SET(unit, 27, 10000); 4586 for (port = 2; port <= 7; port++) { 4587 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4588 } 4589 for (port = 26; port <= 27; port++) { 4590 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4591 } 4592 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4593 break; 4594 #endif /* BCM_TRIUMPH_SUPPORT */ 4595 case BCM56820_DEVICE_ID: 4596 for (port = 9; port <= 16; port++) { 4597 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4598 } 4599 break; 4600 case BCM56821_DEVICE_ID: 4601 for (port = 11; port <= 14; port++) { 4602 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4603 } 4604 if (soc_property_get(unit, spn_BCM56821_20X12, 0)) { 4605 SOC_PBMP_ASSIGN(pbmp_gx12g, pbmp_valid); 4606 SOC_PBMP_CLEAR(pbmp_tmp); 4607 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x01ff87fe); 4608 SOC_PBMP_ASSIGN(pbmp_gx12g, pbmp_tmp); 4609 } else { 4610 SOC_PBMP_ASSIGN(pbmp_gx16g, pbmp_valid); 4611 SOC_PBMP_CLEAR(pbmp_tmp); 4612 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x01e0001e); 4613 SOC_PBMP_AND(pbmp_gx16g, pbmp_tmp); 4614 } 4615 for (port = 9; port <= 16; port++) { 4616 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4617 } 4618 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4619 break; 4620 case BCM56822_DEVICE_ID: 4621 for (port = 1; port <= 4; port++) { 4622 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4623 } 4624 if (soc_property_get(unit, spn_BCM56822_8X16, 0)) { 4625 SOC_PBMP_ASSIGN(pbmp_gx16g, pbmp_valid); 4626 SOC_PBMP_CLEAR(pbmp_tmp); 4627 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x00001fe0); 4628 SOC_PBMP_AND(pbmp_gx16g, pbmp_tmp); 4629 } else { 4630 for (port = 5; port <= 6; port++) { 4631 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4632 } 4633 SOC_PBMP_ASSIGN(pbmp_gx21g, pbmp_valid); 4634 SOC_PBMP_CLEAR(pbmp_tmp); 4635 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x00001e00); 4636 SOC_PBMP_AND(pbmp_gx21g, pbmp_tmp); 4637 SOC_PBMP_ASSIGN(pbmp_gx16g, pbmp_valid); 4638 SOC_PBMP_CLEAR(pbmp_tmp); 4639 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x00000180); 4640 SOC_PBMP_AND(pbmp_gx16g, pbmp_tmp); 4641 } 4642 for (port = 9; port <= 16; port++) { 4643 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4644 } 4645 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4646 break; 4647 case BCM56725_DEVICE_ID: 4648 for (port = 25; port <= 28; port++) { 4649 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4650 } 4651 if (soc_property_get(unit, spn_BCM56725_16X16, 0)) { 4652 for (port = 1; port <= 4; port++) { 4653 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4654 } 4655 for (port = 21; port <= 24; port++) { 4656 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4657 } 4658 SOC_PBMP_ASSIGN(pbmp_gx16g, pbmp_valid); 4659 SOC_PBMP_CLEAR(pbmp_tmp); 4660 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x001fffe0); 4661 SOC_PBMP_AND(pbmp_gx16g, pbmp_tmp); 4662 break; 4663 } 4664 /* Fall through */ 4665 case BCM56823_DEVICE_ID: 4666 for (port = 1; port <= 6; port++) { 4667 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4668 } 4669 for (port = 19; port <= 24; port++) { 4670 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4671 } 4672 SOC_PBMP_ASSIGN(pbmp_gx21g, pbmp_valid); 4673 SOC_PBMP_CLEAR(pbmp_tmp); 4674 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x0001fe00); 4675 SOC_PBMP_AND(pbmp_gx21g, pbmp_tmp); 4676 SOC_PBMP_ASSIGN(pbmp_gx16g, pbmp_valid); 4677 SOC_PBMP_CLEAR(pbmp_tmp); 4678 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x00060180); 4679 SOC_PBMP_AND(pbmp_gx16g, pbmp_tmp); 4680 for (port = 9; port <= 16; port++) { 4681 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4682 } 4683 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4684 break; 4685 case BCM56825_DEVICE_ID: 4686 for (port = 26; port <= 28; port++) { 4687 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4688 } 4689 SOC_PBMP_ASSIGN(pbmp_gx21g, pbmp_valid); 4690 SOC_PBMP_CLEAR(pbmp_tmp); 4691 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x0001fe00); 4692 SOC_PBMP_AND(pbmp_gx21g, pbmp_tmp); 4693 for (port = 9; port <= 16; port++) { 4694 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4695 } 4696 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4697 break; 4698 case BCM56721_DEVICE_ID: 4699 SOC_PBMP_PORT_REMOVE(pbmp_valid, 5); 4700 SOC_PBMP_PORT_REMOVE(pbmp_valid, 6); 4701 SOC_PBMP_PORT_REMOVE(pbmp_valid, 19); 4702 SOC_PBMP_PORT_REMOVE(pbmp_valid, 20); 4703 /* Fall through */ 4704 case BCM56720_DEVICE_ID: 4705 for (port = 1; port <= 4; port++) { 4706 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4707 } 4708 for (port = 21; port <= 28; port++) { 4709 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4710 } 4711 SOC_PBMP_ASSIGN(pbmp_gx16g, pbmp_valid); 4712 SOC_PBMP_CLEAR(pbmp_tmp); 4713 SOC_PBMP_WORD_SET(pbmp_tmp, 0, 0x001fffe0); 4714 SOC_PBMP_AND(pbmp_gx16g, pbmp_tmp); 4715 for (port = 9; port <= 16; port++) { 4716 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 4717 } 4718 SOC_PBMP_AND(pbmp_hyplite, pbmp_valid); 4719 break; 4720 #ifdef BCM_TRIDENT_SUPPORT 4721 case BCM56840_DEVICE_ID: 4722 case BCM56841_DEVICE_ID: 4723 case BCM56843_DEVICE_ID: 4724 case BCM56845_DEVICE_ID: 4725 case BCM56847_DEVICE_ID: 4726 case BCM56743_DEVICE_ID: 4727 case BCM56745_DEVICE_ID: 4728 case BCM56842_DEVICE_ID: 4729 case BCM56844_DEVICE_ID: 4730 case BCM56846_DEVICE_ID: 4731 case BCM56549_DEVICE_ID: 4732 case BCM56053_DEVICE_ID: 4733 case BCM56831_DEVICE_ID: 4734 case BCM56835_DEVICE_ID: 4735 case BCM56838_DEVICE_ID: 4736 case BCM56849_DEVICE_ID: 4737 case BCM56742_DEVICE_ID: 4738 case BCM56744_DEVICE_ID: 4739 case BCM56746_DEVICE_ID: 4740 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4741 rv = soc_trident_port_config_init(unit, dev_id); 4742 if (rv < 0) { 4743 LOG_ERROR(BSL_LS_SOC_COMMON, 4744 (BSL_META_U(unit, 4745 "Port config error !!\n"))); 4746 return SOC_E_CONFIG; 4747 } 4748 for (port = 66; port <= 73; port++) { 4749 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4750 } 4751 si->cpu_hg_index = 66; 4752 break; 4753 #endif /* BCM_TRIDENT_SUPPORT */ 4754 4755 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIDENT2PLUS_SUPPORT) 4756 case BCM56860_DEVICE_ID: 4757 case BCM56850_DEVICE_ID: 4758 case BCM56851_DEVICE_ID: 4759 case BCM56852_DEVICE_ID: 4760 case BCM56853_DEVICE_ID: 4761 case BCM56854_DEVICE_ID: 4762 case BCM56855_DEVICE_ID: 4763 case BCM56834_DEVICE_ID: 4764 case BCM56750_DEVICE_ID: 4765 case BCM56830_DEVICE_ID: 4766 case BCM56861_DEVICE_ID: 4767 case BCM56862_DEVICE_ID: 4768 case BCM56864_DEVICE_ID: 4769 case BCM56865_DEVICE_ID: 4770 case BCM56866_DEVICE_ID: 4771 case BCM56867_DEVICE_ID: 4772 case BCM56868_DEVICE_ID: 4773 case BCM56832_DEVICE_ID: 4774 case BCM56833_DEVICE_ID: 4775 case BCM56836_DEVICE_ID: 4776 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4777 if (rev_id >= BCM56850_A1_REV_ID) { 4778 SOC_FEATURE_SET(unit, soc_feature_cmic_reserved_queues); 4779 } 4780 rv = soc_trident2_port_config_init(unit, dev_id, rev_id); 4781 if (rv < 0) { 4782 LOG_ERROR(BSL_LS_SOC_COMMON, 4783 (BSL_META_U(unit, 4784 "Port config error !!\n"))); 4785 return SOC_E_CONFIG; 4786 } 4787 for (port = 108; port <= 129; port++) { 4788 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4789 } 4790 si->cpu_hg_index = 106; 4791 if (dev_id == BCM56830_DEVICE_ID) { 4792 SOC_PBMP_ASSIGN(pbmp_xport_xe,pbmp_valid); 4793 } 4794 /* Flex counter pools */ 4795 si->num_flex_ingress_pools = 8; 4796 si->num_flex_egress_pools = 4; 4797 si->size_flex_ingress_pool = 4096; 4798 si->size_flex_egress_pool = 4096; 4799 4800 #ifdef BCM_TRIDENT2PLUS_SUPPORT 4801 /* Initialize subport related pbmp and subtag_pbm */ 4802 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) 4803 && soc_feature(unit, soc_feature_egr_lport_tab_profile)) { 4804 soc_td2p_subport_init(unit); 4805 } 4806 4807 if (soc_feature(unit, soc_feature_multi_next_hops_on_port)) { 4808 si->num_modules = TD2P_MAX_COE_MODULES; 4809 } 4810 #endif 4811 break; 4812 #endif /* defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIDENT2PLUS_SUPPORT) */ 4813 4814 #ifdef BCM_TOMAHAWK_SUPPORT 4815 case BCM56960_DEVICE_ID: 4816 case BCM56961_DEVICE_ID: 4817 case BCM56962_DEVICE_ID: 4818 case BCM56963_DEVICE_ID: 4819 case BCM56930_DEVICE_ID: 4820 case BCM56968_DEVICE_ID: 4821 #if defined(BCM_TOMAHAWKPLUS_SUPPORT) 4822 case BCM56965_DEVICE_ID: 4823 case BCM56969_DEVICE_ID: 4824 case BCM56966_DEVICE_ID: 4825 case BCM56967_DEVICE_ID: 4826 #endif /* BCM_TOMAHAWKPLUS_SUPPORT */ 4827 case BCM56168_DEVICE_ID: 4828 case BCM56169_DEVICE_ID: 4829 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4830 SOC_FEATURE_SET(unit, soc_feature_sbus_format_v4); 4831 rv = soc_tomahawk_port_config_init(unit, dev_id); 4832 if (rv < 0) { 4833 LOG_ERROR(BSL_LS_SOC_COMMON, 4834 (BSL_META_U(unit, 4835 "Port config error !!"))); 4836 return rv; 4837 } 4838 si->cpu_hg_index = 136; 4839 /* Flex counter pools */ 4840 si->num_flex_ingress_pools = 20; 4841 si->num_flex_egress_pools = 4; 4842 si->size_flex_ingress_pool = 4096; 4843 si->size_flex_egress_pool = 4096; 4844 break; 4845 #endif /* BCM_TOMAHAWK_SUPPORT */ 4846 4847 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 4848 case BCM56970_DEVICE_ID: 4849 case BCM56971_DEVICE_ID: 4850 case BCM56972_DEVICE_ID: 4851 case BCM56974_DEVICE_ID: 4852 case BCM56975_DEVICE_ID: 4853 case BCM56980_DEVICE_ID: 4854 case BCM56981_DEVICE_ID: 4855 case BCM56982_DEVICE_ID: 4856 case BCM56983_DEVICE_ID: 4857 case BCM56984_DEVICE_ID: 4858 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4859 SOC_FEATURE_SET(unit, soc_feature_sbus_format_v4); 4860 if (SOC_IS_TOMAHAWK2(unit)) { 4861 rv = soc_tomahawk2_port_config_init(unit, dev_id); 4862 } else { 4863 #ifdef BCM_TOMAHAWK3_SUPPORT 4864 rv = soc_tomahawk3_port_config_init(unit, dev_id); 4865 #endif /* BCM_TOMAHAWK3_SUPPORT */ 4866 } 4867 4868 if (rv < 0) { 4869 LOG_ERROR(BSL_LS_SOC_COMMON, 4870 (BSL_META_U(unit, 4871 "Port config error !!"))); 4872 return rv; 4873 } 4874 si->cpu_hg_index = 136; 4875 /* Flex counter pools */ 4876 si->num_flex_ingress_pools = 20; 4877 si->num_flex_egress_pools = 4; 4878 if (SOC_IS_TOMAHAWK3(unit)) { 4879 si->size_flex_ingress_pool = 4096; 4880 } else { 4881 si->size_flex_ingress_pool = 8192; 4882 } 4883 si->size_flex_egress_pool = 4096; 4884 /* warmboot: rely on recovery info if flexport enabled */ 4885 SOC_IF_ERROR_RETURN(soc_th_latency_get(unit, &latency[unit])); 4886 if (SOC_WARM_BOOT(unit) && si->flex_eligible) { 4887 SOC_PBMP_CLEAR(pbmp_xport_xe); 4888 for (port = 0; port < SOC_MAX_NUM_PORTS; port ++) { 4889 if ((si->port_l2p_mapping[port] > 0) && 4890 (!IS_HG_PORT(unit, port))) { 4891 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 4892 } 4893 } 4894 } 4895 break; 4896 #endif /* BCM_TOMAHAWK2_SUPPORT */ 4897 4898 #ifdef BCM_TRIDENT3_SUPPORT 4899 case BCM56870_DEVICE_ID: 4900 case BCM56873_DEVICE_ID: 4901 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4902 SOC_FEATURE_SET(unit, soc_feature_sbus_format_v4); 4903 rv = soc_trident3_port_config_init(unit, dev_id); 4904 if (rv < 0) { 4905 LOG_ERROR(BSL_LS_SOC_COMMON, 4906 (BSL_META_U(unit, 4907 "Port config error !!"))); 4908 return rv; 4909 } 4910 si->cpu_hg_index = 132; 4911 /* Flex counter pools */ 4912 si->num_flex_ingress_pools = 20; 4913 si->num_flex_egress_pools = 4; 4914 si->size_flex_ingress_pool = 8192; 4915 si->size_flex_egress_pool = 8192; 4916 si->sflow_range_max = 28; 4917 /* Initialize subport related pbmp and subtag_pbm */ 4918 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe)) { 4919 soc_td3_subport_init(unit); 4920 } 4921 if (soc_feature(unit, soc_feature_pstats)) { 4922 soc_trident3_mmu_pstats_tbl_config(unit); 4923 } 4924 if (SOC_WARM_BOOT(unit) && si->flex_eligible) { 4925 SOC_PBMP_CLEAR(pbmp_xport_xe); 4926 for (port = 0; port < SOC_MAX_NUM_PORTS; port ++) { 4927 if ((si->port_l2p_mapping[port] > 0) && 4928 (!IS_HG_PORT(unit, port))) { 4929 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 4930 } 4931 } 4932 } 4933 if (soc_feature(unit, soc_feature_multi_next_hops_on_port)) { 4934 si->num_modules = TD3_MAX_COE_MODULES; 4935 } 4936 break; 4937 #endif /* BCM_TRIDENT3_SUPPORT */ 4938 4939 #ifdef BCM_MAVERICK2_SUPPORT 4940 case BCM56770_DEVICE_ID: 4941 case BCM56771_DEVICE_ID: 4942 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 4943 SOC_FEATURE_SET(unit, soc_feature_sbus_format_v4); 4944 rv = soc_maverick2_port_config_init(unit, dev_id); 4945 if (rv < 0) { 4946 LOG_ERROR(BSL_LS_SOC_COMMON, 4947 (BSL_META_U(unit, 4948 "Port config error !!"))); 4949 } 4950 si->cpu_hg_index = 132; 4951 /* Flex counter pools */ 4952 si->num_flex_ingress_pools = 20; 4953 si->num_flex_egress_pools = 4; 4954 si->size_flex_ingress_pool = 8192; 4955 si->size_flex_egress_pool = 8192; 4956 si->sflow_range_max = 28; 4957 /* Initialize subport related pbmp and subtag_pbm */ 4958 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe)) { 4959 soc_td3_subport_init(unit); 4960 } 4961 if (soc_feature(unit, soc_feature_pstats)) { 4962 soc_trident3_mmu_pstats_tbl_config(unit); 4963 } 4964 if (SOC_WARM_BOOT(unit) && si->flex_eligible) { 4965 SOC_PBMP_CLEAR(pbmp_xport_xe); 4966 for (port = 0; port < SOC_MAX_NUM_PORTS; port ++) { 4967 if ((si->port_l2p_mapping[port] > 0) && 4968 (!IS_HG_PORT(unit, port))) { 4969 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 4970 } 4971 } 4972 } 4973 4974 if (soc_feature(unit, soc_feature_multi_next_hops_on_port)) { 4975 si->num_modules = TD3_MAX_COE_MODULES; 4976 } 4977 break; 4978 #endif /* BCM_MAVERICK2_SUPPORT */ 4979 4980 #ifdef BCM_SHADOW_SUPPORT 4981 case BCM88732_DEVICE_ID: 4982 4983 if (soc_property_get(unit, spn_BCM88732_2X40_1X40, 0)) { 4984 /* 2x40G port-link + 1x40G interlaken */ 4985 SOC_PBMP_PORT_ADD(pbmp_xl, 1); 4986 SOC_PBMP_PORT_ADD(pbmp_xl40g, 1); 4987 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 1); 4988 for (port = 2; port <= 4; port++) { 4989 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4990 } 4991 SOC_PBMP_PORT_ADD(pbmp_xl, 5); 4992 SOC_PBMP_PORT_ADD(pbmp_xl40g, 5); 4993 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 5); 4994 for (port = 6; port <= 8; port++) { 4995 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 4996 } 4997 SOC_PBMP_PORT_ADD(pbmp_xl, 9); 4998 SOC_PBMP_PORT_ADD(pbmp_xl40g, 9); 4999 SOC_PBMP_CLEAR(pbmp_tmp); 5000 for (port = 10; port <= 16; port++) { 5001 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 5002 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5003 } 5004 SOC_PBMP_ASSIGN(pbmp_disabled, pbmp_tmp); 5005 } else if (soc_property_get(unit, spn_BCM88732_2X40_2X40, 0)) { 5006 /* 2x40G port-link + 2x40G interlaken */ 5007 SOC_PBMP_PORT_ADD(pbmp_xl, 1); 5008 SOC_PBMP_PORT_ADD(pbmp_xl40g, 1); 5009 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 1); 5010 for (port = 2; port <= 4; port++) { 5011 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5012 } 5013 SOC_PBMP_PORT_ADD(pbmp_xl, 5); 5014 SOC_PBMP_PORT_ADD(pbmp_xl40g, 5); 5015 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 5); 5016 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 5); 5017 for (port = 6; port <= 8; port++) { 5018 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5019 } 5020 SOC_PBMP_PORT_ADD(pbmp_xl, 9); 5021 SOC_PBMP_PORT_ADD(pbmp_xl40g, 9); 5022 SOC_PBMP_CLEAR(pbmp_tmp); 5023 for (port = 10; port <= 12; port++) { 5024 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 5025 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5026 } 5027 SOC_PBMP_PORT_ADD(pbmp_xl, 13); 5028 SOC_PBMP_PORT_ADD(pbmp_xl40g, 13); 5029 for (port = 14; port <= 16; port++) { 5030 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 5031 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5032 } 5033 /* SOC_PBMP_ASSIGN(pbmp_disabled, pbmp_tmp); */ 5034 } else if (soc_property_get(unit, spn_BCM88732_2X40_2X40E, 0)) { 5035 /* 2x40G port-link + 2x40G Ethernet */ 5036 SOC_PBMP_PORT_ADD(pbmp_xl, 1); 5037 SOC_PBMP_PORT_ADD(pbmp_xl40g, 1); 5038 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 1); 5039 for (port = 2; port <= 4; port++) { 5040 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5041 } 5042 SOC_PBMP_PORT_ADD(pbmp_xl, 5); 5043 SOC_PBMP_PORT_ADD(pbmp_xl40g, 5); 5044 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 5); 5045 for (port = 6; port <= 8; port++) { 5046 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5047 } 5048 SOC_PBMP_PORT_ADD(pbmp_xl, 9); 5049 SOC_PBMP_PORT_ADD(pbmp_xl40g, 9); 5050 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 9); 5051 for (port = 10; port <= 12; port++) { 5052 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5053 } 5054 SOC_PBMP_PORT_ADD(pbmp_xl, 13); 5055 SOC_PBMP_PORT_ADD(pbmp_xl40g, 13); 5056 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 13); 5057 for (port = 14; port <= 16; port++) { 5058 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5059 } 5060 } else if (soc_property_get(unit, spn_BCM88732_2X40_8X10, 0)) { 5061 /* 2x40G port-link + 8x10G XFI */ 5062 SOC_PBMP_PORT_ADD(pbmp_xl, 1); 5063 SOC_PBMP_PORT_ADD(pbmp_xl40g, 1); 5064 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 1); 5065 5066 /* Mark ports as disabled*/ 5067 SOC_PBMP_CLEAR(pbmp_tmp); 5068 for (port = 2; port <= 4; port++) { 5069 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 5070 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5071 SOC_PBMP_PORT_ADD(pbmp_xl40g, 1); 5072 } 5073 for (port = 6; port <= 8; port++) { 5074 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 5075 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5076 } 5077 SOC_PBMP_ASSIGN(pbmp_disabled, pbmp_tmp); 5078 5079 5080 #if 0 5081 for (port = 2; port <= 4; port++) { 5082 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5083 } 5084 #endif 5085 SOC_PBMP_PORT_ADD(pbmp_xl, 5); 5086 SOC_PBMP_PORT_ADD(pbmp_xl40g, 5); 5087 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 5); 5088 #if 0 5089 for (port = 6; port <= 8; port++) { 5090 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5091 } 5092 #endif 5093 for (port = 9; port <= 16; port++) { 5094 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 5095 SOC_PBMP_PORT_ADD(pbmp_xl10g, port); 5096 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5097 } 5098 } else if (soc_property_get(unit, spn_BCM88732_8X10_8X10, 0)) { 5099 /* 8x10G port-link + 8x10G XFI */ 5100 for (port = 1; port <= 16; port++) { 5101 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 5102 SOC_PBMP_PORT_ADD(pbmp_xl10g, port); 5103 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5104 } 5105 } else if (soc_property_get(unit, spn_BCM88732_8X10_1X40, 0)) { 5106 /* 8x10G port-link + 1x40G interlaken */ 5107 for (port = 1; port <= 8; port++) { 5108 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 5109 SOC_PBMP_PORT_ADD(pbmp_xl10g, port); 5110 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5111 } 5112 SOC_PBMP_PORT_ADD(pbmp_xl, 9); 5113 SOC_PBMP_PORT_ADD(pbmp_xl40g, 9); 5114 SOC_PBMP_CLEAR(pbmp_tmp); 5115 for (port = 10; port <= 16; port++) { 5116 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 5117 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5118 } 5119 SOC_PBMP_ASSIGN(pbmp_disabled, pbmp_tmp); 5120 } else if (soc_property_get(unit, spn_BCM88732_1X40_4X10, 0)) { 5121 /* TDM 18 */ 5122 /* 1x40G port-link 4X10G XAUI Switch link*/ 5123 SOC_PBMP_PORT_ADD(pbmp_xl, 1); 5124 SOC_PBMP_PORT_ADD(pbmp_xl40g, 1); 5125 SOC_PBMP_PORT_ADD(pbmp_xport_xe, 1); 5126 for (port = 2; port <= 8; port++) { 5127 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5128 } 5129 5130 /* Switch Panel ports */ 5131 for (port = 9; port < 16; port+=2) { 5132 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5133 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 5134 SOC_PBMP_PORT_ADD(pbmp_xl10g, port); 5135 } 5136 /* Remove the even ports from the valid ports */ 5137 for (port = 10; port <= 16; port+=2) { 5138 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5139 } 5140 5141 } else if (soc_property_get(unit, spn_BCM88732_4X10_4X10, 0)) { 5142 /* TDM 19 */ 5143 for (port = 1; port <= 4; port++) { 5144 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 5145 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5146 SOC_PBMP_PORT_ADD(pbmp_xl10g, port); 5147 } 5148 for (port = 5; port <= 8; port++) { 5149 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5150 } 5151 5152 /* Switch Panel ports */ 5153 for (port = 9; port < 16; port+=2) { 5154 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5155 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 5156 SOC_PBMP_PORT_ADD(pbmp_xl10g, port); 5157 } 5158 /* Remove the even ports from the valid ports */ 5159 for (port = 10; port <= 16; port+=2) { 5160 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5161 } 5162 } else { 5163 /* 8x10G port-link + 2x40G interlaken */ 5164 for (port = 1; port <= 8; port++) { 5165 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 5166 SOC_PBMP_PORT_ADD(pbmp_xl10g, port); 5167 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5168 } 5169 SOC_PBMP_PORT_ADD(pbmp_xl, 9); 5170 SOC_PBMP_PORT_ADD(pbmp_xl40g, 9); 5171 SOC_PBMP_CLEAR(pbmp_tmp); 5172 for (port = 10; port <= 12; port++) { 5173 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 5174 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5175 } 5176 SOC_PBMP_PORT_ADD(pbmp_xl, 13); 5177 SOC_PBMP_PORT_ADD(pbmp_xl40g, 13); 5178 for (port = 14; port <= 16; port++) { 5179 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 5180 SOC_PBMP_PORT_ADD(pbmp_xl, port); 5181 } 5182 /* SOC_PBMP_ASSIGN(pbmp_disabled, pbmp_tmp); */ 5183 } 5184 break; 5185 #endif /* BCM_SHADOW_SUPPORT */ 5186 5187 #ifdef BCM_HELIX4_SUPPORT 5188 case BCM56548H_DEVICE_ID: 5189 case BCM56548_DEVICE_ID: 5190 case BCM56547_DEVICE_ID: 5191 case BCM56346_DEVICE_ID: 5192 case BCM56345_DEVICE_ID: 5193 case BCM56344_DEVICE_ID: 5194 case BCM56342_DEVICE_ID: 5195 case BCM56340_DEVICE_ID: 5196 case BCM56049_DEVICE_ID: 5197 case BCM56048_DEVICE_ID: 5198 case BCM56047_DEVICE_ID: 5199 case BCM56042_DEVICE_ID: 5200 case BCM56041_DEVICE_ID: 5201 case BCM56040_DEVICE_ID: 5202 5203 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 5204 rv = soc_tr3_port_config_init(unit, dev_id); 5205 if (rv < 0) { 5206 LOG_ERROR(BSL_LS_SOC_COMMON, 5207 (BSL_META_U(unit, 5208 "Port config error !!\n"))); 5209 return SOC_E_CONFIG; 5210 } 5211 for (port = 62; port <= 66; port++) { 5212 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5213 } 5214 for (port = 58; port < 62; port++) { 5215 SOC_PBMP_PORT_ADD(pbmp_valid, port); 5216 SOC_PBMP_PORT_ADD(si->lb_pbm, port); 5217 } 5218 if (BCM56548H_DEVICE_ID == dev_id) { 5219 for (port = 46; port <= 53; port++) { 5220 SOC_PBMP_PORT_REMOVE(pbmp_xport_xe, port); 5221 } 5222 } 5223 5224 5225 AXP_PORT(unit, SOC_AXP_NLF_PASSTHRU) = si->lb_port = 61; 5226 AXP_PORT(unit, SOC_AXP_NLF_SM) = 60; 5227 AXP_PORT(unit, SOC_AXP_NLF_WLAN_ENCAP) = 58; 5228 AXP_PORT(unit, SOC_AXP_NLF_WLAN_DECAP) = 59; 5229 si->cpu_hg_index = 63; 5230 if (dev_id == BCM56346_DEVICE_ID || 5231 dev_id == BCM56345_DEVICE_ID) { 5232 si->num_flex_ingress_pools = 0; 5233 si->num_flex_egress_pools = 0; 5234 si->size_flex_ingress_pool = 0; 5235 si->size_flex_egress_pool = 0; 5236 si->global_meter_action_size = 0; 5237 } else { 5238 si->num_flex_ingress_pools = 8; 5239 si->num_flex_egress_pools = 8; 5240 si->size_flex_ingress_pool = 1024; 5241 si->size_flex_egress_pool = 1024; 5242 si->global_meter_action_size = 8192; 5243 } 5244 break; 5245 #endif 5246 5247 #ifdef BCM_TRIUMPH3_SUPPORT 5248 case BCM56640_DEVICE_ID: 5249 case BCM56643_DEVICE_ID: 5250 case BCM56644_DEVICE_ID: 5251 case BCM56648_DEVICE_ID: 5252 case BCM56649_DEVICE_ID: 5253 case BCM56540_DEVICE_ID: 5254 case BCM56541_DEVICE_ID: 5255 case BCM56542_DEVICE_ID: 5256 case BCM56543_DEVICE_ID: 5257 case BCM56544_DEVICE_ID: 5258 case BCM56545_DEVICE_ID: 5259 case BCM56546_DEVICE_ID: 5260 case BCM56044_DEVICE_ID: 5261 case BCM56045_DEVICE_ID: 5262 case BCM56046_DEVICE_ID: 5263 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 5264 rv = soc_tr3_port_config_init(unit, dev_id); 5265 SOC_PBMP_CLEAR(pbmp_xport_xe); 5266 for (port = 0; port <= 57; port++) { 5267 if ((10000 == si->port_speed_max[port]) || (100000 == si->port_speed_max[port])) { 5268 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 5269 } 5270 } 5271 pbmp_xport_xe = soc_property_get_pbmp_default(unit, 5272 spn_PBMP_XPORT_XE, 5273 pbmp_xport_xe); 5274 if (rv < 0) { 5275 LOG_ERROR(BSL_LS_SOC_COMMON, 5276 (BSL_META_U(unit, 5277 "Port config error !!\n"))); 5278 return SOC_E_CONFIG; 5279 } 5280 for (port = 62; port <= 66; port++) { 5281 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5282 } 5283 for (port = 58; port < 62; port++) { 5284 SOC_PBMP_PORT_ADD(si->lb_pbm, port); 5285 SOC_PBMP_PORT_ADD(pbmp_valid, port); 5286 } 5287 5288 AXP_PORT(unit, SOC_AXP_NLF_PASSTHRU) = si->lb_port = 61; 5289 AXP_PORT(unit, SOC_AXP_NLF_SM) = 60; 5290 AXP_PORT(unit, SOC_AXP_NLF_WLAN_ENCAP) = 58; 5291 AXP_PORT(unit, SOC_AXP_NLF_WLAN_DECAP) = 59; 5292 si->cpu_hg_index = 63; 5293 si->num_flex_ingress_pools = 16; 5294 si->size_flex_ingress_pool = 8192; 5295 si->num_flex_egress_pools = 8; 5296 si->size_flex_egress_pool = 2048; 5297 if (dev_id == BCM56540_DEVICE_ID || 5298 dev_id == BCM56541_DEVICE_ID || 5299 dev_id == BCM56542_DEVICE_ID || 5300 dev_id == BCM56543_DEVICE_ID || 5301 dev_id == BCM56544_DEVICE_ID || 5302 dev_id == BCM56545_DEVICE_ID || 5303 dev_id == BCM56546_DEVICE_ID || 5304 dev_id == BCM56044_DEVICE_ID || 5305 dev_id == BCM56045_DEVICE_ID || 5306 dev_id == BCM56046_DEVICE_ID) { 5307 si->num_flex_ingress_pools = 8; 5308 si->size_flex_ingress_pool = 2048; 5309 if (dev_id == BCM56044_DEVICE_ID || 5310 dev_id == BCM56045_DEVICE_ID || 5311 dev_id == BCM56046_DEVICE_ID) { 5312 si->size_flex_egress_pool = 64; 5313 si->size_flex_ingress_pool = 256; 5314 } 5315 if (dev_id == BCM56543_DEVICE_ID) { 5316 si->size_flex_ingress_pool = 4096; 5317 } 5318 } 5319 break; 5320 #endif /* BCM_TRIUMPH3_SUPPORT */ 5321 #ifdef BCM_KATANA_SUPPORT 5322 case BCM56440_DEVICE_ID: 5323 case BCM55440_DEVICE_ID: 5324 case BCM55441_DEVICE_ID: 5325 case BCM56445_DEVICE_ID: 5326 SOC_PBMP_CLEAR(pbmp_gport_stack); 5327 SOC_PBMP_CLEAR(pbmp_mxq13g); 5328 SOC_PBMP_CLEAR(pbmp_mxq2p5g); 5329 SOC_PBMP_CLEAR(pbmp_tmp); 5330 switch (soc_property_get(unit, spn_BCM5644X_CONFIG, 0)) { 5331 case 1: /* 24x1G + 2xHG + 8x2.5GE */ 5332 for (port = 25; port <= 26; port++) { 5333 SOC_PBMP_PORT_ADD(pbmp_mxq13g, port); 5334 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 5335 } 5336 for (port = 27; port <= 34; port++) { 5337 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5338 SOC_PBMP_PORT_ADD(pbmp_tmp, port); 5339 } 5340 SOC_PBMP_ASSIGN(pbmp_mxq, pbmp_tmp); 5341 break; 5342 5343 case 2: /* 24x1G + 4x2.5HGL */ 5344 for (port = 25; port <= 28; port++) { 5345 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5346 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5347 SOC_PBMP_PORT_ADD(pbmp_gport_stack, port); 5348 } 5349 for (port = 29; port <= 34; port++) { 5350 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5351 } 5352 break; 5353 case 3: /* 24x1G + 3xHG + 4x2.5GE */ 5354 for (port = 25; port <= 27; port++) { 5355 SOC_PBMP_PORT_ADD(pbmp_mxq13g, port); 5356 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5357 } 5358 for (port = 28; port <= 31; port++) { 5359 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5360 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5361 } 5362 for (port = 32; port <= 34; port++) { 5363 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5364 } 5365 break; 5366 5367 case 4: /* 24x1G + 2xHG + 4x2.5GE + 1xHG*/ 5368 for (port = 25; port <= 26; port++) { 5369 SOC_PBMP_PORT_ADD(pbmp_mxq13g, port); 5370 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5371 } 5372 SOC_PBMP_PORT_ADD(pbmp_mxq13g, 28); 5373 SOC_PBMP_PORT_ADD(pbmp_mxq, 28); 5374 for (port = 29; port <= 31; port++) { 5375 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5376 } 5377 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, 27); 5378 SOC_PBMP_PORT_ADD(pbmp_mxq, 27); 5379 for (port = 32; port <= 34; port++) { 5380 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5381 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5382 } 5383 break; 5384 5385 5386 case 0: /* 24x1G + 4xHG */ 5387 default: 5388 for (port = 25; port <= 28; port++) { 5389 SOC_PBMP_PORT_ADD(pbmp_mxq13g, port); 5390 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5391 SOC_PBMP_PORT_ADD(pbmp_gport_stack, port); 5392 } 5393 for (port = 29; port <= 34; port++) { 5394 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5395 } 5396 break; 5397 } 5398 for (port = 36; port <= 38; port++) { 5399 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5400 } 5401 if (drv_dev_id == BCM55440_DEVICE_ID) { 5402 /* Only 17 GE ports */ 5403 for (port = 18; port <= 24; port++) { 5404 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5405 } 5406 } 5407 SOC_PBMP_CLEAR(si->tdm_pbm); 5408 SOC_PBMP_CLEAR(si->lb_pbm); 5409 SOC_PBMP_PORT_ADD(si->lb_pbm, 35); 5410 si->lb_port = 35; 5411 si->cpu_hg_index = 39; 5412 break; 5413 case BCM56441_DEVICE_ID: 5414 case BCM56446_DEVICE_ID: 5415 /* 8x1G + 2xHG */ 5416 SOC_PBMP_CLEAR(pbmp_gport_stack); 5417 SOC_PBMP_CLEAR(pbmp_hyplite); 5418 SOC_PBMP_CLEAR(pbmp_mxq13g); 5419 SOC_PBMP_CLEAR(pbmp_mxq2p5g); 5420 SOC_PBMP_CLEAR(pbmp_mxq); 5421 5422 /* 5423 * For 56441/2/3 devices port 1 is always included. The OTP settings 5424 * are checked in _soc_katana_misc_init and if CES is not enabled then 5425 * the port is removed there. 5426 */ 5427 switch (soc_property_get(unit, spn_BCM5644X_CONFIG, 0)) { 5428 case 2: /* 4x1G + 4x2.5HGL + 1xHG */ 5429 if (dev_id == BCM56441_DEVICE_ID) { 5430 /* Port 0 is used for CES */ 5431 for (port = 2; port <= 8; port++) { 5432 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5433 } 5434 } else if (dev_id == BCM56446_DEVICE_ID) { 5435 for (port = 5; port <= 12; port++) { 5436 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5437 } 5438 } 5439 for (port = 13; port <= 26; port++) { 5440 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5441 } 5442 SOC_PBMP_PORT_ADD(pbmp_mxq13g, 27); 5443 SOC_PBMP_PORT_ADD(pbmp_mxq, 27); 5444 SOC_PBMP_PORT_ADD(pbmp_gport_stack, 27); 5445 for (port = 28; port <= 31; port++) { 5446 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5447 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5448 SOC_PBMP_PORT_ADD(pbmp_gport_stack, port); 5449 } 5450 for (port = 32; port <= 34; port++) { 5451 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5452 } 5453 break; 5454 case 1: 5455 /* (Frontpanel)8xSGMII + (BackPanel) 4*2.5HGL + 4*2.5GE */ 5456 /* 56441 : GPORT1 - 9 to 16 */ 5457 /* 56446 : GPORT0 - 1 to 8 */ 5458 if (dev_id == BCM56441_DEVICE_ID) { 5459 /* Port 0 is used for CES */ 5460 for (port = 2; port <= 8; port++) { 5461 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5462 } 5463 } else if (dev_id == BCM56446_DEVICE_ID) { 5464 for (port = 9; port <= 16; port++) { 5465 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5466 } 5467 } 5468 for (port = 17; port <= 26; port++) { 5469 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5470 } 5471 /* MXQPORT2 - 27,32,33,34 */ 5472 for (kt_mxqport_index = 0 ; 5473 kt_mxqport_index < 4 ; 5474 kt_mxqport_index++) { 5475 port = kt_mxqport2[kt_mxqport_index]; /* 27,32,33,34 */ 5476 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5477 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5478 } 5479 /* 5480 MXQPORT3 - 28,29,30,31 5481 */ 5482 for (port = 28; port <= 31; port++) { 5483 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5484 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5485 SOC_PBMP_PORT_ADD(pbmp_gport_stack, port); 5486 } 5487 break; 5488 case 0: /* 8x1G + 2xHG */ 5489 default: 5490 /* (Frontpanel)8xSGMII + (BackPanel)2HG[13] */ 5491 /* 56441 : GPORT1 - 9 to 16 */ 5492 /* 56446 : GPORT0 - 1 to 8 */ 5493 5494 if (dev_id == BCM56441_DEVICE_ID) { 5495 /* Port 0 is used for CES */ 5496 for (port = 2; port <= 8; port++) { 5497 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5498 } 5499 } else if (dev_id == BCM56446_DEVICE_ID) { 5500 for (port = 9; port <= 16; port++) { 5501 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5502 } 5503 } 5504 for (port = 17; port <= 26; port++) { 5505 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5506 } 5507 /* 5508 MXQPORT2 - 27 5509 MXQPORT3 - 28 5510 */ 5511 for (port = 27; port <= 28; port++) { 5512 SOC_PBMP_PORT_ADD(pbmp_mxq13g, port); 5513 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5514 SOC_PBMP_PORT_ADD(pbmp_gport_stack, port); 5515 } 5516 for (port = 29; port <= 34; port++) { 5517 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5518 } 5519 break; 5520 } 5521 for (port = 36; port <= 38; port++) { 5522 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5523 } 5524 SOC_PBMP_CLEAR(si->tdm_pbm); 5525 SOC_PBMP_CLEAR(si->lb_pbm); 5526 SOC_PBMP_PORT_ADD(si->lb_pbm, 35); 5527 si->lb_port = 35; 5528 si->cpu_hg_index = 39; 5529 break; 5530 case BCM56442_DEVICE_ID: 5531 case BCM56447_DEVICE_ID: 5532 /* 16x1G */ 5533 SOC_PBMP_CLEAR(pbmp_gport_stack); 5534 if (dev_id == BCM56442_DEVICE_ID) { 5535 for (port = 2; port <= 8; port++) { 5536 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5537 } 5538 } else if (dev_id == BCM56447_DEVICE_ID) { 5539 for (port = 17; port <= 24; port++) { 5540 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5541 } 5542 } 5543 for (port = 25; port <= 34; port++) { 5544 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5545 } 5546 for (port = 36; port <= 38; port++) { 5547 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5548 } 5549 SOC_PBMP_CLEAR(si->lb_pbm); 5550 SOC_PBMP_PORT_ADD(si->lb_pbm, 35); 5551 si->lb_port = 35; 5552 si->cpu_hg_index = 39; 5553 break; 5554 case BCM56443_DEVICE_ID: 5555 /* 8x1G + 2xHG + 8x2.5G*/ 5556 SOC_PBMP_CLEAR(pbmp_gport_stack); 5557 SOC_PBMP_CLEAR(pbmp_hyplite); 5558 SOC_PBMP_CLEAR(pbmp_mxq13g); 5559 SOC_PBMP_CLEAR(pbmp_mxq2p5g); 5560 SOC_PBMP_CLEAR(pbmp_mxq); 5561 for (port = 2; port <= 8; port++) { 5562 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5563 } 5564 for (port = 17; port <= 24; port++) { 5565 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5566 } 5567 switch (soc_property_get(unit, spn_BCM5644X_CONFIG, 0)) { 5568 case 0: /* 8x1G + 2xHG + 8x2.5G */ 5569 for (port = 25; port <= 26; port++) { 5570 SOC_PBMP_PORT_ADD(pbmp_mxq13g, port); 5571 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5572 } 5573 for (port = 27; port <= 34; port++) { 5574 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5575 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5576 } 5577 break; 5578 case 1: /* 8x1G + 2x2.5HGL + 8x2.5G */ 5579 for (port = 25; port <= 26; port++) { 5580 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5581 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5582 SOC_PBMP_PORT_ADD(pbmp_gport_stack, port); 5583 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 5584 } 5585 for (port = 27; port <= 34; port++) { 5586 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5587 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5588 } 5589 break; 5590 default: 5591 break; 5592 } 5593 for (port = 36; port <= 38; port++) { 5594 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5595 } 5596 SOC_PBMP_CLEAR(si->lb_pbm); 5597 SOC_PBMP_PORT_ADD(si->lb_pbm, 35); 5598 si->lb_port = 35; 5599 si->cpu_hg_index = 39; 5600 break; 5601 case BCM56449_DEVICE_ID: 5602 /* 2xHG + 2x2.5HGL */ 5603 SOC_PBMP_CLEAR(pbmp_gport_stack); 5604 SOC_PBMP_CLEAR(pbmp_mxq13g); 5605 SOC_PBMP_CLEAR(pbmp_mxq2p5g); 5606 SOC_PBMP_CLEAR(pbmp_tmp); 5607 SOC_PBMP_CLEAR(pbmp_hyplite); 5608 5609 for (port = 1; port <= 24; port++) { 5610 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5611 } 5612 switch (soc_property_get(unit, spn_BCM5644X_CONFIG, 0)) { 5613 case 0: /* 2xHG + 2x2.5HGL */ 5614 for (port = 27; port <= 28; port++) { 5615 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5616 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5617 SOC_PBMP_PORT_ADD(pbmp_gport_stack, port); 5618 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 5619 } 5620 for (port = 25; port <= 26; port++) { 5621 SOC_PBMP_PORT_ADD(pbmp_mxq13g, port); 5622 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5623 } 5624 for (port = 29; port <= 34; port++) { 5625 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5626 } 5627 break; 5628 case 1: /* 4x2.5HGL */ 5629 for (port = 25; port <= 28; port++) { 5630 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5631 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5632 SOC_PBMP_PORT_ADD(pbmp_gport_stack, port); 5633 SOC_PBMP_PORT_ADD(pbmp_hyplite, port); 5634 } 5635 for (port = 29; port <= 34; port++) { 5636 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5637 } 5638 break; 5639 default: 5640 break; 5641 } 5642 for (port = 36; port <= 38; port++) { 5643 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5644 } 5645 SOC_PBMP_CLEAR(si->tdm_pbm); 5646 SOC_PBMP_CLEAR(si->lb_pbm); 5647 SOC_PBMP_PORT_ADD(si->lb_pbm, 35); 5648 si->lb_port = 35; 5649 si->cpu_hg_index = 39; 5650 break; 5651 case BCM56448_DEVICE_ID: 5652 /* 24x1G + 4x2.5HGL */ 5653 SOC_PBMP_CLEAR(pbmp_gport_stack); 5654 SOC_PBMP_CLEAR(pbmp_mxq13g); 5655 SOC_PBMP_CLEAR(pbmp_mxq2p5g); 5656 SOC_PBMP_CLEAR(pbmp_tmp); 5657 for (port = 25; port <= 28; port++) { 5658 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5659 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5660 SOC_PBMP_PORT_ADD(pbmp_gport_stack, port); 5661 } 5662 for (port = 29; port <= 34; port++) { 5663 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5664 } 5665 for (port = 36; port <= 38; port++) { 5666 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5667 } 5668 SOC_PBMP_CLEAR(si->tdm_pbm); 5669 SOC_PBMP_CLEAR(si->lb_pbm); 5670 SOC_PBMP_PORT_ADD(si->lb_pbm, 35); 5671 si->lb_port = 35; 5672 si->cpu_hg_index = 39; 5673 break; 5674 case BCM56241_DEVICE_ID: 5675 /* 6xGE + 2x2.5G*/ 5676 SOC_PBMP_CLEAR(pbmp_gport_stack); 5677 SOC_PBMP_CLEAR(pbmp_hyplite); 5678 SOC_PBMP_CLEAR(pbmp_mxq13g); 5679 SOC_PBMP_CLEAR(pbmp_mxq2p5g); 5680 SOC_PBMP_CLEAR(pbmp_mxq); 5681 for (port = 1; port <= 26; port++) { 5682 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5683 } 5684 5685 for (port = 27; port <= 34; port++) { 5686 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5687 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5688 if ((port >= 30) && (port <= 31)) { 5689 si->port_speed_max[port] = 2500; 5690 } else { 5691 si->port_speed_max[port] =1000; 5692 } 5693 } 5694 5695 for (port = 36; port <= 38; port++) { 5696 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5697 } 5698 SOC_PBMP_CLEAR(si->lb_pbm); 5699 SOC_PBMP_PORT_ADD(si->lb_pbm, 35); 5700 si->lb_port = 35; 5701 si->cpu_hg_index = 39; 5702 break; 5703 case BCM56240_DEVICE_ID: 5704 case BCM56245_DEVICE_ID: 5705 SOC_PBMP_CLEAR(pbmp_gport_stack); 5706 SOC_PBMP_CLEAR(pbmp_hyplite); 5707 SOC_PBMP_CLEAR(pbmp_mxq13g); 5708 SOC_PBMP_CLEAR(pbmp_mxq10g); 5709 SOC_PBMP_CLEAR(pbmp_mxq2p5g); 5710 SOC_PBMP_CLEAR(pbmp_mxq); 5711 for (port = 1; port <= 24; port++) { 5712 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5713 } 5714 5715 switch (soc_property_get(unit, spn_BCM5644X_CONFIG, 0)) { 5716 case 0: /* 2x10G + 2xHG[13] */ 5717 SOC_PBMP_PORT_ADD(pbmp_mxq13g, 25); 5718 SOC_PBMP_PORT_ADD(pbmp_mxq13g, 26); 5719 SOC_PBMP_PORT_ADD(pbmp_mxq10g, 27); 5720 SOC_PBMP_PORT_ADD(pbmp_mxq10g, 28); 5721 for (port = 25; port <= 28; port++) { 5722 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5723 } 5724 for (port = 29; port <= 34; port++) { 5725 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5726 } 5727 break; 5728 case 1: /* 8x2.5G + 2xHG[13] */ 5729 SOC_PBMP_PORT_ADD(pbmp_mxq13g, 25); 5730 SOC_PBMP_PORT_ADD(pbmp_mxq, 25); 5731 SOC_PBMP_PORT_ADD(pbmp_mxq13g, 26); 5732 SOC_PBMP_PORT_ADD(pbmp_mxq, 26); 5733 for (port = 27; port <= 34; port++) { 5734 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5735 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5736 } 5737 break; 5738 default: 5739 break; 5740 } 5741 for (port = 36; port <= 38; port++) { 5742 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5743 } 5744 SOC_PBMP_CLEAR(si->lb_pbm); 5745 SOC_PBMP_PORT_ADD(si->lb_pbm, 35); 5746 si->lb_port = 35; 5747 si->cpu_hg_index = 39; 5748 break; 5749 case BCM56242_DEVICE_ID: 5750 case BCM56246_DEVICE_ID: 5751 /* 10x2.5G */ 5752 SOC_PBMP_CLEAR(pbmp_gport_stack); 5753 SOC_PBMP_CLEAR(pbmp_hyplite); 5754 SOC_PBMP_CLEAR(pbmp_mxq13g); 5755 SOC_PBMP_CLEAR(pbmp_mxq10g); 5756 SOC_PBMP_CLEAR(pbmp_mxq2p5g); 5757 SOC_PBMP_CLEAR(pbmp_mxq); 5758 for (port = 1; port <= 24; port++) { 5759 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5760 } 5761 for (port = 25; port <= 34; port++) { 5762 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5763 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5764 } 5765 for (port = 36; port <= 38; port++) { 5766 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5767 } 5768 SOC_PBMP_CLEAR(si->lb_pbm); 5769 SOC_PBMP_PORT_ADD(si->lb_pbm, 35); 5770 si->lb_port = 35; 5771 si->cpu_hg_index = 39; 5772 break; 5773 case BCM56243_DEVICE_ID: 5774 /* 4x2.5G */ 5775 SOC_PBMP_CLEAR(pbmp_gport_stack); 5776 SOC_PBMP_CLEAR(pbmp_hyplite); 5777 SOC_PBMP_CLEAR(pbmp_mxq13g); 5778 SOC_PBMP_CLEAR(pbmp_mxq10g); 5779 SOC_PBMP_CLEAR(pbmp_mxq2p5g); 5780 SOC_PBMP_CLEAR(pbmp_mxq); 5781 for (port = 1; port <= 27; port++) { 5782 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5783 } 5784 for (port = 28; port <= 31; port++) { 5785 SOC_PBMP_PORT_ADD(pbmp_mxq2p5g, port); 5786 SOC_PBMP_PORT_ADD(pbmp_mxq, port); 5787 } 5788 for (port = 32; port <= 34; port++) { 5789 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5790 } 5791 for (port = 36; port <= 38; port++) { 5792 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5793 } 5794 SOC_PBMP_CLEAR(si->lb_pbm); 5795 SOC_PBMP_PORT_ADD(si->lb_pbm, 35); 5796 si->lb_port = 35; 5797 si->cpu_hg_index = 39; 5798 break; 5799 #endif /* BCM_KATANA_SUPPORT */ 5800 5801 #ifdef BCM_KATANA2_SUPPORT 5802 case BCM55450_DEVICE_ID: 5803 case BCM55455_DEVICE_ID: 5804 case BCM56248_DEVICE_ID: 5805 case BCM56450_DEVICE_ID: 5806 case BCM56452_DEVICE_ID: 5807 case BCM56454_DEVICE_ID: 5808 case BCM56455_DEVICE_ID: 5809 case BCM56456_DEVICE_ID: 5810 case BCM56457_DEVICE_ID: 5811 case BCM56458_DEVICE_ID: 5812 /* Init kt2_pbmp structure with local variable's addresses */ 5813 kt2_pbmp.pbmp_gport_stack=&pbmp_gport_stack; 5814 kt2_pbmp.pbmp_mxq=&pbmp_mxq; 5815 kt2_pbmp.pbmp_mxq1g=&pbmp_mxq1g; 5816 kt2_pbmp.pbmp_mxq2p5g=&pbmp_mxq2p5g; 5817 kt2_pbmp.pbmp_mxq10g=&pbmp_mxq10g; 5818 kt2_pbmp.pbmp_mxq13g=&pbmp_mxq13g; 5819 kt2_pbmp.pbmp_mxq21g=&pbmp_mxq21g; 5820 kt2_pbmp.pbmp_xport_xe=&pbmp_xport_xe; 5821 kt2_pbmp.pbmp_valid=&pbmp_valid; 5822 kt2_pbmp.pbmp_pp=&pbmp_pp; 5823 kt2_pbmp.pbmp_linkphy=&(si->linkphy_pbm); 5824 /* Init KT2 related pbmp now */ 5825 soc_katana2_pbmp_init(unit,kt2_pbmp); 5826 5827 SOC_PBMP_CLEAR(si->tdm_pbm); 5828 SOC_PBMP_CLEAR(si->lb_pbm); 5829 SOC_PBMP_PORT_ADD(si->lb_pbm, 41); 5830 si->lb_port = 41; 5831 si->cpu_hg_index = 42; 5832 si->cpu_hg_pp_port_index = 170; 5833 /* Initialize subport related pbmp linkphy_pbm and subtag_pbm */ 5834 soc_katana2_subport_init(unit); 5835 5836 break; 5837 #endif /* BCM_KATANA2_SUPPORT */ 5838 5839 #ifdef BCM_SABER2_SUPPORT 5840 case BCM56260_DEVICE_ID: 5841 case BCM56261_DEVICE_ID: 5842 case BCM56262_DEVICE_ID: 5843 case BCM56263_DEVICE_ID: 5844 case BCM56265_DEVICE_ID: 5845 case BCM56266_DEVICE_ID: 5846 case BCM56267_DEVICE_ID: 5847 case BCM56268_DEVICE_ID: 5848 case BCM56460_DEVICE_ID: 5849 case BCM56461_DEVICE_ID: 5850 case BCM56462_DEVICE_ID: 5851 case BCM56463_DEVICE_ID: 5852 case BCM56465_DEVICE_ID: 5853 case BCM56466_DEVICE_ID: 5854 case BCM56467_DEVICE_ID: 5855 case BCM56468_DEVICE_ID: 5856 case BCM56233_DEVICE_ID: 5857 sb2_pbmp.pbmp_gport_stack=&pbmp_gport_stack; 5858 sb2_pbmp.pbmp_mxq=&pbmp_mxq; 5859 sb2_pbmp.pbmp_mxq1g=&pbmp_mxq1g; 5860 sb2_pbmp.pbmp_mxq2p5g=&pbmp_mxq2p5g; 5861 sb2_pbmp.pbmp_mxq10g=&pbmp_mxq10g; 5862 sb2_pbmp.pbmp_xl=&pbmp_xl; 5863 sb2_pbmp.pbmp_xl1g=&pbmp_xl1g; 5864 sb2_pbmp.pbmp_xl2p5g=&pbmp_xl2p5g; 5865 sb2_pbmp.pbmp_xl10g=&pbmp_xl10g; 5866 sb2_pbmp.pbmp_xport_ge=&pbmp_xport_ge; 5867 sb2_pbmp.pbmp_xport_xe=&pbmp_xport_xe; 5868 sb2_pbmp.pbmp_valid=&pbmp_valid; 5869 sb2_pbmp.pbmp_pp=&pbmp_pp; 5870 sb2_pbmp.pbmp_linkphy=&(si->linkphy_pbm); 5871 5872 /* Init SB2 related pbmp now */ 5873 soc_saber2_pbmp_init(unit,sb2_pbmp); 5874 5875 SOC_PBMP_CLEAR(si->lb_pbm); 5876 SOC_PBMP_PORT_ADD(si->lb_pbm, 29); 5877 si->lb_port = 29; 5878 si->cpu_hg_index = 30; 5879 si->cpu_hg_pp_port_index = 96; 5880 5881 /* Initialize subport related pbmp linkphy_pbm and subtag_pbm */ 5882 if (soc_feature(unit, soc_feature_subtag_coe)) { 5883 soc_saber2_subport_init(unit); 5884 } 5885 5886 break; 5887 #endif /* BCM_SABER2_SUPPORT */ 5888 5889 #ifdef BCM_METROLITE_SUPPORT 5890 case BCM56270_DEVICE_ID: 5891 case BCM56271_DEVICE_ID: 5892 case BCM56272_DEVICE_ID: 5893 5894 case BCM53460_DEVICE_ID: 5895 case BCM53461_DEVICE_ID: 5896 5897 /* Clear PP Port Used Pbmp. */ 5898 SOC_PBMP_CLEAR(pbmp_pp_unsed); 5899 5900 /* Reconfigure global variables based on system config */ 5901 SOC_IF_ERROR_RETURN( 5902 soc_metrolite_global_param_reconfigure(unit)); 5903 5904 ml_pbmp.pbmp_gport_stack=&pbmp_gport_stack; 5905 ml_pbmp.pbmp_mxq=&pbmp_mxq; 5906 ml_pbmp.pbmp_mxq1g=&pbmp_mxq1g; 5907 ml_pbmp.pbmp_mxq2p5g=&pbmp_mxq2p5g; 5908 ml_pbmp.pbmp_mxq10g=&pbmp_mxq10g; 5909 ml_pbmp.pbmp_xl=&pbmp_xl; 5910 ml_pbmp.pbmp_xl1g=&pbmp_xl1g; 5911 ml_pbmp.pbmp_xl2p5g=&pbmp_xl2p5g; 5912 ml_pbmp.pbmp_xl10g=&pbmp_xl10g; 5913 ml_pbmp.pbmp_xport_ge=&pbmp_xport_ge; 5914 ml_pbmp.pbmp_xport_xe=&pbmp_xport_xe; 5915 ml_pbmp.pbmp_valid=&pbmp_valid; 5916 ml_pbmp.pbmp_pp=&pbmp_pp; 5917 ml_pbmp.pbmp_linkphy=&(si->linkphy_pbm); 5918 5919 /* Init ML related pbmp now */ 5920 soc_metrolite_pbmp_init(unit,ml_pbmp,&pbmp_pp_unsed); 5921 5922 SOC_PBMP_CLEAR(si->lb_pbm); 5923 SOC_PBMP_PORT_ADD(si->lb_pbm, 13); 5924 si->lb_port = 13; 5925 si->cpu_hg_index = 14; 5926 si->cpu_hg_pp_port_index = 32; 5927 5928 /* Initialize subport related pbmp linkphy_pbm and subtag_pbm */ 5929 soc_metrolite_subport_init(unit,&pbmp_pp_unsed); 5930 5931 break; 5932 #endif /* BCM_METROLITE_SUPPORT */ 5933 5934 default: 5935 /* Devices that use common port config init function for all SKUs */ 5936 switch (drv_dev_id) { 5937 #if defined(BCM_APACHE_SUPPORT) 5938 case BCM56560_DEVICE_ID: 5939 case BCM56670_DEVICE_ID: 5940 case BCM56671_DEVICE_ID: 5941 case BCM56672_DEVICE_ID: 5942 case BCM56675_DEVICE_ID: 5943 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 5944 5945 #if defined(BCM_MONTEREY_SUPPORT) 5946 if (dev_id == BCM56670_DEVICE_ID || dev_id == BCM56671_DEVICE_ID || 5947 dev_id == BCM56672_DEVICE_ID ||dev_id == BCM56675_DEVICE_ID) { 5948 rv = soc_monterey_port_config_init(unit, dev_id, rev_id); 5949 } else 5950 #endif 5951 { 5952 rv = soc_apache_port_config_init(unit, dev_id, rev_id); 5953 } 5954 if (rv < 0) { 5955 LOG_ERROR(BSL_LS_SOC_COMMON, 5956 (BSL_META_U(unit, 5957 "Port config error !!\n"))); 5958 } 5959 5960 if (dev_id == BCM56670_DEVICE_ID || dev_id ==BCM56671_DEVICE_ID || 5961 dev_id == BCM56672_DEVICE_ID ||dev_id == BCM56675_DEVICE_ID ) { 5962 /* Valid port range: [0, 74] */ 5963 for (port = 67; port <= 129; port++) { 5964 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5965 } 5966 5967 si->cpu_hg_index = 67; 5968 } else { 5969 /* Valid port range: [0, 74] */ 5970 for (port = 75; port <= 129; port++) { 5971 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 5972 } 5973 5974 si->cpu_hg_index = 75; 5975 } 5976 5977 /* Flex counter pools - Base chip defaults */ 5978 si->num_flex_ingress_pools = 8; 5979 si->num_flex_egress_pools = 4; 5980 si->size_flex_ingress_pool = 4096; 5981 si->size_flex_egress_pool = 4096; 5982 5983 /* Initialize subport related pbmp and subtag_pbm */ 5984 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe)) { 5985 soc_td2p_subport_init(unit); 5986 } 5987 5988 if (soc_feature(unit, soc_feature_multi_next_hops_on_port)) { 5989 si->num_modules = TD2P_MAX_COE_MODULES; 5990 } 5991 break; 5992 #endif /* defined(BCM_APACHE_SUPPORT) */ 5993 5994 #ifdef BCM_HELIX5_SUPPORT 5995 case BCM56370_DEVICE_ID: 5996 SOC_FEATURE_SET(unit, soc_feature_logical_port_num); 5997 SOC_FEATURE_SET(unit, soc_feature_sbus_format_v4); 5998 rv = soc_helix5_port_config_init(unit, dev_id); 5999 if (rv < 0) { 6000 LOG_ERROR(BSL_LS_SOC_COMMON, 6001 (BSL_META_U(unit, 6002 "Port config error !!"))); 6003 return rv; 6004 } 6005 si->cpu_hg_index = 72; 6006 /* Flex counter pools */ 6007 si->num_flex_ingress_pools = 20; 6008 si->num_flex_egress_pools = 4; 6009 si->size_flex_ingress_pool = 1024; 6010 si->size_flex_egress_pool = 1024; 6011 si->sflow_range_max = 28; 6012 si->max_mtu = 12288; 6013 6014 if (soc_feature(unit, soc_feature_pstats)) { 6015 soc_helix5_mmu_pstats_tbl_config(unit); 6016 } 6017 if (SOC_WARM_BOOT(unit) && si->flex_eligible) { 6018 SOC_PBMP_CLEAR(pbmp_xport_xe); 6019 for (port = 0; port < SOC_MAX_NUM_PORTS; port ++) { 6020 if ((si->port_l2p_mapping[port] > 0) && 6021 (!IS_HG_PORT(unit, port))) { 6022 SOC_PBMP_PORT_ADD(pbmp_xport_xe, port); 6023 } 6024 } 6025 } 6026 6027 if (soc_feature(unit, soc_feature_multi_next_hops_on_port)) { 6028 si->num_modules = TD3_MAX_COE_MODULES; 6029 } 6030 break; 6031 #endif /* BCM_HELIX5_SUPPORT */ 6032 6033 6034 default: 6035 break; 6036 } 6037 6038 break; 6039 } 6040 6041 /* No emulation/debug only regs when a real chip or plisim */ 6042 if (!SAL_BOOT_RTLSIM && !soc_property_get(unit, spn_EMULATION_REGS, 0)) { 6043 soc->disabled_reg_flags |= SOC_REG_FLAG_EMULATION; 6044 } 6045 6046 si->ipic_port = -1; 6047 si->ipic_block = -1; 6048 si->cmic_port = -1; 6049 si->cmic_block = -1; 6050 si->fe.min = si->fe.max = -1; 6051 si->ge.min = si->ge.max = -1; 6052 si->xe.min = si->xe.max = -1; 6053 si->ce.min = si->ce.max = -1; 6054 si->hg.min = si->hg.max = -1; 6055 si->cpri.min = si->cpri.max = -1; 6056 si->hl.min = si->hl.max = -1; 6057 si->st.min = si->st.max = -1; 6058 si->lp.min = si->lp.max = -1; 6059 si->cl.min = si->cl.max = -1; 6060 si->c.min = si->c.max = -1; 6061 si->mmu.min = si->mmu.max = -1; 6062 si->tdm.min = si->tdm.max = -1; 6063 si->ether.min = si->ether.max = -1; 6064 si->port.min = si->port.max = -1; 6065 si->all.min = si->all.max = -1; 6066 #ifdef BCM_SHADOW_SUPPORT 6067 si->ms_isec_block[0] = -1; 6068 si->ms_isec_block[1] = -1; 6069 si->ms_esec_block[0] = -1; 6070 si->ms_esec_block[1] = -1; 6071 #endif /*BCM_SHADOW_SUPPORT */ 6072 #ifdef BCM_KATANA2_SUPPORT 6073 si->rxlp_block[0] = -1; 6074 si->rxlp_block[1] = -1; 6075 si->txlp_block[0] = -1; 6076 si->txlp_block[1] = -1; 6077 si->olp_block = -1; 6078 #endif /*BCM_KATANA2_SUPPORT */ 6079 6080 for (blk = 0; blk < SOC_MAX_NUM_BLKS; blk++) { 6081 si->block_port[blk] = REG_PORT_ANY; 6082 #if defined(BCM_KATANA2_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) 6083 if ((SOC_IS_KATANA2(unit) || SOC_IS_HURRICANE2(unit))) { 6084 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_RXLP) && 6085 (SOC_BLOCK_INFO(unit, blk).number == 0)) { 6086 si->rxlp_block[0] = blk; 6087 } 6088 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_RXLP) && 6089 (SOC_BLOCK_INFO(unit, blk).number == 1)) { 6090 si->rxlp_block[1] = blk; 6091 } 6092 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_TXLP) && 6093 (SOC_BLOCK_INFO(unit, blk).number == 0)) { 6094 si->txlp_block[0] = blk; 6095 } 6096 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_TXLP) && 6097 (SOC_BLOCK_INFO(unit, blk).number == 1)) { 6098 si->txlp_block[1] = blk; 6099 } 6100 #if defined(BCM_KATANA2_SUPPORT) 6101 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_MXQPORT) && 6102 (SOC_BLOCK_INFO(unit, blk).number == 10)) { 6103 si->olp_block = blk; 6104 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6105 (BSL_META_U(unit, 6106 "OLP blk:%d \n"),si->olp_block )); 6107 } 6108 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_MXQPORT) && 6109 (SOC_BLOCK_INFO(unit, blk).number == 7)) { 6110 mxq7_blk = blk; 6111 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6112 (BSL_META_U(unit, 6113 "OLP blk:%d \n"),si->olp_block )); 6114 } 6115 #endif /*BCM_KATANA2_SUPPORT */ 6116 } 6117 #endif 6118 #if defined(BCM_METROLITE_SUPPORT) 6119 if (SOC_IS_METROLITE(unit)) { 6120 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_IECELL) && 6121 (SOC_BLOCK_INFO(unit, blk).number == 0)) { 6122 si->iecell_block[0] = blk; 6123 } 6124 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_IECELL) && 6125 (SOC_BLOCK_INFO(unit, blk).number == 1)) { 6126 si->iecell_block[1] = blk; 6127 } 6128 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_OAMP) && 6129 (SOC_BLOCK_INFO(unit, blk).number == 0)) { 6130 si->oamp_block = blk; 6131 si->block_valid[blk] = 1; 6132 } 6133 } else 6134 #endif 6135 #if defined(BCM_SABER2_SUPPORT) 6136 if (SOC_IS_SABER2(unit)) { 6137 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_IECELL) && 6138 (SOC_BLOCK_INFO(unit, blk).number == 0)) { 6139 si->iecell_block[0] = blk; 6140 } 6141 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_OAMP) && 6142 (SOC_BLOCK_INFO(unit, blk).number == 0)) { 6143 si->oamp_block = blk; 6144 si->block_valid[blk] = 1; 6145 } 6146 } 6147 #endif 6148 6149 } 6150 6151 #define ADD_PORT(ptype, port_num) \ 6152 if (!SOC_PBMP_MEMBER(si->ptype.bitmap, port_num)) { \ 6153 si->ptype.port[si->ptype.num++] = port_num; \ 6154 SOC_PBMP_PORT_ADD(si->ptype.bitmap, port_num); \ 6155 } \ 6156 if (si->ptype.min > port_num || si->ptype.min < 0) { \ 6157 si->ptype.min = port_num; \ 6158 } \ 6159 if (si->ptype.max < port_num) { \ 6160 si->ptype.max = port_num; \ 6161 } \ 6162 6163 max_port = -1; 6164 for (phy_port = 0; ; phy_port++) { 6165 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, 0); 6166 bindex = SOC_PORT_IDX_BINDEX(unit, phy_port, 0); 6167 6168 if (blk < 0 && bindex < 0) { /* end of regsfile port list */ 6169 break; 6170 } 6171 6172 if (soc_feature(unit, soc_feature_logical_port_num)) { 6173 port = si->port_p2l_mapping[phy_port]; 6174 if (port < 0) { /* not used in user config */ 6175 continue; 6176 } 6177 if (port > max_port) { 6178 max_port = port; 6179 } 6180 if (si->flex_port_p2l_mapping[phy_port] == -1) { 6181 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, port); 6182 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, port); 6183 } 6184 } else { 6185 port = phy_port; 6186 max_port = phy_port; 6187 } 6188 6189 if (!SOC_PBMP_MEMBER(pbmp_valid, port)) { /* disabled port */ 6190 int blk_list[2]; 6191 blk_list[0] = SOC_BLOCK_INFO(unit, blk).type; 6192 blk_list[1] = SOC_BLOCK_TYPE_INVALID; 6193 if (SOC_BLOCK_IN_LIST(blk_list, SOC_BLK_CPU)) { 6194 LOG_WARN(BSL_LS_SOC_COMMON, 6195 (BSL_META_U(unit, 6196 "soc_info_config: " 6197 "cannot disable cpu port\n"))); 6198 } else { 6199 blk = -1; /* mark as disabled port */ 6200 #ifdef BCM_KATANA2_SUPPORT 6201 /* 6202 * On KT2 for configurations which do not use OLP port 6203 * setup up the port info. 6204 */ 6205 if ((SOC_IS_KATANA2(unit) && (!SOC_IS_SABER2(unit)) && 6206 (port == KT2_OLP_PORT))) { 6207 if (!si->olp_port[0] && (si->block_valid[mxq7_blk])) { 6208 SOC_DRIVER(unit)->port_info[KT2_OLP_PORT].blk = 6209 mxq7_blk; 6210 SOC_DRIVER(unit)->port_info[KT2_OLP_PORT].bindex = 3; 6211 SOC_PBMP_PORT_ADD(si->block_bitmap[mxq7_blk], port); 6212 SOC_PBMP_PORT_REMOVE(si->block_bitmap[si->olp_block], 6213 port); 6214 } 6215 } 6216 #endif 6217 } 6218 } 6219 #if defined(BCM_ENDURO_SUPPORT) || defined(BCM_KATANA_SUPPORT) \ 6220 || defined(BCM_SABER2_SUPPORT) 6221 if(SOC_IS_ENDURO(unit) || SOC_IS_KATANAX(unit)) { 6222 if(!SOC_IS_SABER2(unit) && SAL_BOOT_QUICKTURN) { 6223 if (IS_LB_PORT(unit, port)) { 6224 blk = -1; /* mark as disabled port */ 6225 } 6226 } 6227 } 6228 #endif 6229 6230 #if defined(BCM_SHADOW_SUPPORT) 6231 if(SOC_IS_SHADOW(unit)) { 6232 if (SOC_PBMP_MEMBER(pbmp_disabled, port) && !IS_IL_PORT(unit, port)) { /* disabled port */ 6233 SOC_PBMP_PORT_REMOVE(pbmp_valid, port); 6234 } 6235 } 6236 #endif 6237 if (blk < 0) { /* disabled port */ 6238 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]), 6239 "?%d", port); 6240 si->port_offset[port] = port; 6241 continue; 6242 } 6243 6244 blktype = -1; 6245 bname = "?"; 6246 for (port_idx = 0; port_idx < SOC_DRIVER(unit)->port_num_blktype; 6247 port_idx++) { 6248 int skip_blk_port = 0; 6249 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, port_idx); 6250 if (SOC_IS_GREYHOUND(unit) && 6251 ((SOC_BLOCK_INFO(unit, blk).number & 0xf00) == 0xf00)){ 6252 if(phy_port == 5){ 6253 SOC_BLOCK_INFO(unit, blk).number &= ~0xf00; 6254 } 6255 skip_blk_port = 1; 6256 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6257 (BSL_META_U(unit, 6258 "skip the phy_port %d blk %d\n"), 6259 phy_port,blk)); 6260 } 6261 if (blk < 0) { /* end of block list of each port */ 6262 break; 6263 } 6264 6265 old_blktype = blktype; 6266 old_bname = bname; 6267 6268 blktype = SOC_BLOCK_INFO(unit, blk).type; 6269 bname = soc_block_port_name_lookup_ext(blktype, unit); 6270 switch (blktype) { 6271 case SOC_BLK_MXQPORT: 6272 if (!si->port_speed_max[port]) { 6273 if (SOC_PBMP_MEMBER(pbmp_mxq21g, port)) { 6274 si->port_speed_max[port] = 21000; 6275 } else if (SOC_PBMP_MEMBER(pbmp_mxq13g, port)) { 6276 si->port_speed_max[port] = 13000; 6277 } else if (SOC_PBMP_MEMBER(pbmp_mxq2p5g, port)) { 6278 si->port_speed_max[port] = 2500; 6279 } else if (SOC_PBMP_MEMBER(pbmp_mxq1g, port)) { 6280 si->port_speed_max[port] = 1000; 6281 } else { 6282 si->port_speed_max[port] = 10000; 6283 } 6284 } 6285 #if defined(BCM_HGPROXY_COE_SUPPORT) 6286 if (soc_feature(unit, soc_feature_hgproxy_subtag_coe) && 6287 SOC_PBMP_MEMBER(si->subtag_pbm, port)) { 6288 pno = si->subtag.num; 6289 ADD_PORT(subtag, port); 6290 } 6291 #endif 6292 #if defined(BCM_KATANA2_SUPPORT) 6293 if (soc_feature(unit, soc_feature_linkphy_coe) && 6294 SOC_PBMP_MEMBER(si->linkphy_pbm, port)) { 6295 pno = si->lp.num; 6296 ADD_PORT(lp, port); 6297 } 6298 if (soc_feature(unit, soc_feature_subtag_coe) && 6299 SOC_PBMP_MEMBER(si->subtag_pbm, port)) { 6300 pno = si->subtag.num; 6301 ADD_PORT(subtag, port); 6302 } 6303 #endif 6304 if (si->port_speed_max[port] < 10000) { /* GE */ 6305 pno = si->ge.num; 6306 ADD_PORT(ge, port); 6307 if (SOC_PBMP_MEMBER(pbmp_gport_stack, port)) { 6308 /* GE in Higig Lite Mode. Higig Like stack capable 6309 * port */ 6310 ADD_PORT(st, port); 6311 ADD_PORT(hl, port); 6312 #if defined(BCM_KATANA2_SUPPORT) 6313 if (SOC_IS_KATANA2(unit) && !SOC_IS_SABER2(unit)) { 6314 ADD_PORT(hg, port); 6315 } 6316 #endif 6317 } else { 6318 ADD_PORT(ether, port); 6319 } 6320 } else if (SOC_PBMP_MEMBER(pbmp_xport_xe, port)) { /* XE */ 6321 pno = si->xe.num; 6322 ADD_PORT(xe, port); 6323 ADD_PORT(ether, port); 6324 bname = "xe"; 6325 } else { /* HG */ 6326 pno = si->hg.num; 6327 ADD_PORT(hg, port); 6328 ADD_PORT(st, port); 6329 } 6330 6331 ADD_PORT(port, port); 6332 if (SOC_PBMP_MEMBER(pbmp_mxq, port)) { 6333 ADD_PORT(mxq, port); 6334 } 6335 if (SOC_PBMP_MEMBER(pbmp_hyplite, port)) { 6336 ADD_PORT(hyplite, port); 6337 } 6338 ADD_PORT(all, port); 6339 break; 6340 case SOC_BLK_EPIC: 6341 pno = si->fe.num; 6342 ADD_PORT(fe, port); 6343 ADD_PORT(ether, port); 6344 ADD_PORT(port, port); 6345 ADD_PORT(all, port); 6346 break; 6347 case SOC_BLK_GPIC: 6348 case SOC_BLK_XTPORT: 6349 case SOC_BLK_QGPORT: 6350 case SOC_BLK_GPORT: 6351 if (SOC_PBMP_MEMBER(pbmp_gport_fe, port)) { /* GE vs FE SMII */ 6352 pno = si->fe.num; 6353 bname = "fe"; 6354 ADD_PORT(fe, port); 6355 } else { 6356 if (SOC_IS_TRIUMPH3(unit)) { 6357 if (si->port_speed_max[port] == 10000) { 6358 pno = si->xe.num; 6359 ADD_PORT(xe, port); 6360 } else { 6361 pno = si->ge.num; 6362 ADD_PORT(ge, port); 6363 } 6364 } else { 6365 pno = si->ge.num; 6366 ADD_PORT(ge, port); 6367 } 6368 } 6369 if (SOC_PBMP_MEMBER(pbmp_gport_stack, port)) { 6370 /* GE in Higig Lite Mode. Higig Like stack capable port */ 6371 ADD_PORT(st, port); 6372 ADD_PORT(hl, port); 6373 } else { 6374 ADD_PORT(ether, port); 6375 } 6376 if (SOC_IS_TRIUMPH3(unit)) { 6377 ADD_PORT(xt, port); 6378 } 6379 ADD_PORT(port, port); 6380 ADD_PORT(all, port); 6381 break; 6382 case SOC_BLK_XWPORT: 6383 if (si->port_speed_max[port] && si->port_speed_max[port] < 10000) { /* GE */ 6384 pno = si->ge.num; 6385 ADD_PORT(ge, port); 6386 ADD_PORT(ether, port); 6387 bname = "ge"; 6388 } else if (SOC_PBMP_MEMBER(pbmp_xport_xe, port) || 6389 (si->port_speed_max[port] == 10000)) { /* XE */ 6390 pno = si->xe.num; 6391 ADD_PORT(xe, port); 6392 ADD_PORT(ether, port); 6393 bname = "xe"; 6394 } else { /* HG */ 6395 pno = si->hg.num; 6396 ADD_PORT(hg, port); 6397 ADD_PORT(st, port); 6398 } 6399 ADD_PORT(xw, port); 6400 ADD_PORT(port, port); 6401 ADD_PORT(all, port); 6402 break; 6403 case SOC_BLK_XPIC: 6404 pno = si->xe.num; 6405 ADD_PORT(xe, port); 6406 ADD_PORT(ether, port); 6407 ADD_PORT(port, port); 6408 ADD_PORT(all, port); 6409 break; 6410 case SOC_BLK_IPIC: 6411 si->ipic_port = port; 6412 si->ipic_block = blk; 6413 /* FALLTHROUGH */ 6414 case SOC_BLK_HPIC: 6415 pno = si->hg.num; 6416 ADD_PORT(hg, port); 6417 ADD_PORT(st, port); 6418 ADD_PORT(port, port); 6419 ADD_PORT(all, port); 6420 break; 6421 case SOC_BLK_XPORT: 6422 if (SOC_PBMP_MEMBER(pbmp_xport_xe, port)) { /* XE vs HG */ 6423 pno = si->xe.num; 6424 ADD_PORT(xe, port); 6425 ADD_PORT(ether, port); 6426 bname = "xe"; 6427 } else { 6428 pno = si->hg.num; 6429 ADD_PORT(hg, port); 6430 ADD_PORT(st, port); 6431 } 6432 si->port_speed_max[port] = 12000; 6433 ADD_PORT(port, port); 6434 ADD_PORT(all, port); 6435 break; 6436 case SOC_BLK_CPORT: 6437 if (si->port_speed_max[port] < 100000) { 6438 /* don't use the name from this block */ 6439 blktype = old_blktype; 6440 bname = old_bname; 6441 break; 6442 } 6443 ADD_PORT(c, port); 6444 /* CPort blocks like those in TD2+ use the xe port bitmap for 6445 * determining whether a port is ethernet or higig. Others 6446 * such as TD2 or TR3 use port speed to determine higig settings 6447 */ 6448 if ((soc_feature(unit, soc_feature_cport_clmac) && 6449 SOC_PBMP_MEMBER(pbmp_xport_xe, port)) || 6450 (!soc_feature(unit,soc_feature_cport_clmac) && 6451 ((si->port_speed_max[port] == 100000) || 6452 (si->port_speed_max[port] == 120000)) )) { 6453 pno = si->c.num; 6454 ADD_PORT(ce, port); 6455 ADD_PORT(ether, port); 6456 /* name is default to ce by lookup above */ 6457 } else { /* HG */ 6458 pno = si->hg.num; 6459 ADD_PORT(hg, port); 6460 ADD_PORT(st, port); 6461 bname = "hg"; 6462 } 6463 ADD_PORT(port, port); 6464 ADD_PORT(all, port); 6465 break; 6466 case SOC_BLK_CPRI: 6467 6468 if ((SOC_PBMP_MEMBER(pbmp_xport_cpri, port))) { 6469 ADD_PORT(all, port); 6470 ADD_PORT(port, port); 6471 pno = si->cpri.num; 6472 ADD_PORT(cpri, port); 6473 if ((SOC_PBMP_MEMBER(pbmp_roe_compression, port))) { 6474 SOC_PBMP_PORT_ADD(si->roe_compression, port); 6475 6476 } 6477 bname = "roe"; 6478 } 6479 break; 6480 case SOC_BLK_CXXPORT: 6481 ADD_PORT(cxx, port); 6482 /* don't use the name from this block */ 6483 blktype = old_blktype; 6484 bname = old_bname; 6485 6486 break; 6487 /* fall through to case for SOC_BLK_[CX]LPORT */ 6488 /* coverity[fallthrough: FALSE] */ 6489 case SOC_BLK_CLG2PORT: 6490 if (SOC_BLK_CLG2PORT == blktype) { 6491 ADD_PORT(clg2, port); 6492 } 6493 /* fall through to case for SOC_BLK_CLPORT */ 6494 /* coverity[fallthrough: FALSE] */ 6495 case SOC_BLK_CLPORT: 6496 #if defined(BCM_APACHE_SUPPORT) 6497 if (SOC_IS_APACHE(unit) && (!SOC_IS_MONTEREY(unit))) { 6498 if (((phy_port == 17) || (phy_port == 53)) && 6499 (si->port_speed_max[port] < 100000)) { 6500 blktype = old_blktype; 6501 bname = old_bname; 6502 continue; 6503 } 6504 } 6505 #endif 6506 if (SOC_BLK_CLPORT == blktype) { 6507 ADD_PORT(cl, port); 6508 } 6509 if(SOC_IS_MONTEREY(unit) && 6510 SOC_PBMP_MEMBER(pbmp_xport_cpri, port)) { 6511 blktype = old_blktype; 6512 bname = old_bname; 6513 break ; 6514 } 6515 6516 if ((si->port_speed_max[port] >= 100000) && 6517 (SOC_BLK_CXXPORT != blktype)) { 6518 /* Catch both CE and HG ports */ 6519 ADD_PORT(c, port); 6520 } 6521 if (SOC_PBMP_MEMBER(pbmp_xport_xe, port) && 6522 ((si->port_speed_max[port] == 100000) || 6523 (si->port_speed_max[port] == 120000))) { /* CE */ 6524 pno = si->ce.num; 6525 ADD_PORT(ce, port); 6526 ADD_PORT(ether, port); 6527 bname = "ce"; 6528 ADD_PORT(port, port); 6529 ADD_PORT(all, port); 6530 break; 6531 } 6532 6533 /* fall through to case for SOC_BLK_XLPORT */ 6534 /* coverity[fallthrough: FALSE] */ 6535 case SOC_BLK_XLPORTB0: 6536 if (SOC_BLK_XLPORTB0 == blktype) { 6537 ADD_PORT(xlb0, port); 6538 } 6539 /* fall through to case for SOC_BLK_XLPORT */ 6540 /* coverity[fallthrough: FALSE] */ 6541 case SOC_BLK_XLPORT: 6542 6543 if(SOC_IS_GREYHOUND(unit) && (skip_blk_port == 1)){ 6544 si->block_valid[blk] += 1; 6545 continue; 6546 } 6547 if ((soc_feature(unit, soc_feature_reset_xlport_block_tsc12)) && 6548 (si->port_speed_max[port] >= 100000)) { 6549 int block_num = 0, offset = 0; 6550 block_num = (phy_port-1)/16; 6551 if ( block_num % 2 == 0 ) { 6552 offset = 1; 6553 } else { 6554 offset = -1; 6555 } 6556 /* set block_valid flag for 3 SOC_BLK_XLPORT in TSC12 */ 6557 si->block_valid[blk] += 1; 6558 si->block_valid[blk+offset] += 1; 6559 si->block_valid[blk+2*offset] += 1; 6560 } 6561 #if defined(BCM_APACHE_SUPPORT) 6562 if (SOC_IS_APACHE(unit) && (!SOC_IS_MONTEREY(unit))) { 6563 if (((phy_port == 17) || (phy_port == 53))) { 6564 if ((blktype == SOC_BLK_XLPORT) && 6565 (si->port_speed_max[port] >= 100000)) { 6566 if (si->block_port[blk] < 0) { 6567 si->block_port[blk] = port; 6568 } 6569 if (si->block_port[blk + 1] < 0) { 6570 si->block_port[blk + 1] = port; 6571 } 6572 if (si->block_port[blk + 2] < 0) { 6573 si->block_port[blk + 2] = port; 6574 } 6575 si->block_valid[blk] += 1; 6576 si->block_valid[blk + 1] += 1; 6577 si->block_valid[blk + 2] += 1; 6578 /* No need to add in block bitmap */ 6579 continue; 6580 } 6581 } else if (SOC_SUCCESS(soc_apache_port_reg_blk_index_get 6582 (unit, port, SOC_BLK_CXXPORT, &blk))) { 6583 si->block_valid[blk] += 1; 6584 if (si->block_port[blk] < 0) si->block_port[blk] = port; 6585 /* Restore old blk value */ 6586 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, port_idx); 6587 } 6588 } 6589 #endif 6590 if ((SOC_BLK_XLPORT == blktype) && 6591 (si->port_speed_max[port] >= 100000)) { 6592 /* don't use the name from this block */ 6593 blktype = old_blktype; 6594 bname = old_bname; 6595 break; 6596 } 6597 if (!si->port_speed_max[port]) { 6598 #if defined(BCM_SABER2_SUPPORT) 6599 if (SOC_IS_SABER2(unit) && 6600 SOC_PBMP_MEMBER(pbmp_xl1g, port)) { 6601 si->port_speed_max[port] = 1000; 6602 } else if (SOC_IS_SABER2(unit) && 6603 SOC_PBMP_MEMBER(pbmp_xl2p5g, port)) { 6604 si->port_speed_max[port] = 2500; 6605 } else if (SOC_IS_SABER2(unit) && 6606 SOC_PBMP_MEMBER(pbmp_xl10g, port)) { 6607 if (!(SOC_PBMP_MEMBER(pbmp_xport_xe, port))) { 6608 si->port_speed_max[port] = 11000; 6609 } else { 6610 si->port_speed_max[port] = 10000; 6611 } 6612 } else 6613 #endif 6614 if (SOC_PBMP_MEMBER(pbmp_xport_ge, port)) { 6615 si->port_speed_max[port] = 2500; 6616 } else if (SOC_PBMP_MEMBER(pbmp_gx25g, port)) { 6617 si->port_speed_max[port] = 25000; 6618 } else if (SOC_PBMP_MEMBER(pbmp_gx21g, port)) { 6619 si->port_speed_max[port] = 21000; 6620 } else if (SOC_PBMP_MEMBER(pbmp_gx20g, port)) { 6621 si->port_speed_max[port] = 20000; 6622 } else if (SOC_PBMP_MEMBER(pbmp_gx16g, port)) { 6623 si->port_speed_max[port] = 16000; 6624 } else if (SOC_PBMP_MEMBER(pbmp_gx13g, port)) { 6625 si->port_speed_max[port] = 13000; 6626 } else if (SOC_PBMP_MEMBER(pbmp_gx12g, port)) { 6627 si->port_speed_max[port] = 12000; 6628 } else { 6629 si->port_speed_max[port] = 10000; 6630 } 6631 #ifdef BCM_SHADOW_SUPPORT 6632 if (SOC_IS_SHADOW(unit)) { 6633 if SOC_PBMP_MEMBER(pbmp_xl12g, port) { 6634 si->port_speed_max[port] = 12000; 6635 } else if (SOC_PBMP_MEMBER(pbmp_xl40g, port)) { 6636 si->port_speed_max[port] = 40000; 6637 } 6638 } 6639 #endif 6640 } 6641 #ifdef BCM_SABER2_SUPPORT 6642 if (SOC_IS_SABER2(unit)) { 6643 if (SOC_PBMP_MEMBER(pbmp_xport_ge,port)) { 6644 pno = si->ge.num; 6645 ADD_PORT(ge, port); 6646 ADD_PORT(ether, port); 6647 bname = "ge"; 6648 } else if (SOC_PBMP_MEMBER(pbmp_xport_xe, port)) { 6649 pno = si->xe.num; 6650 ADD_PORT(xe, port); 6651 ADD_PORT(ether, port); 6652 bname = "xe"; 6653 } else { 6654 pno = si->hg.num; 6655 ADD_PORT(hg, port); 6656 ADD_PORT(st, port); 6657 bname = "hg"; 6658 } 6659 } else 6660 #endif 6661 if (si->port_speed_max[port] < 10000) { /* GE */ 6662 #ifdef BCM_GREYHOUND_SUPPORT 6663 if (SOC_IS_GREYHOUND(unit) && 6664 si->port_speed_max[port] == 5000) { 6665 if (SOC_PBMP_MEMBER(pbmp_xport_ge, port)) { /* GE */ 6666 pno = si->ge.num; 6667 si->port_speed_max[port] = 2500; 6668 ADD_PORT(ge, port); 6669 ADD_PORT(ether, port); 6670 bname = "ge"; 6671 } else if (SOC_PBMP_MEMBER(pbmp_xport_xe, port)) { /* XE */ 6672 pno = si->xe.num; 6673 ADD_PORT(xe, port); 6674 ADD_PORT(ether, port); 6675 bname = "xe"; 6676 } else { /* HG */ 6677 pno = si->hg.num; 6678 ADD_PORT(hg, port); 6679 ADD_PORT(st, port); 6680 } 6681 } else 6682 #endif 6683 { 6684 pno = si->ge.num; 6685 ADD_PORT(ge, port); 6686 if (SOC_PBMP_MEMBER(pbmp_gport_stack, port)) { 6687 /* GE in Higig Lite Mode. Higig Like stack capable 6688 * port */ 6689 ADD_PORT(st, port); 6690 ADD_PORT(hl, port); 6691 } else { 6692 ADD_PORT(ether, port); 6693 } 6694 } 6695 } else if (SOC_PBMP_MEMBER(pbmp_xport_xe, port)) { /* XE */ 6696 pno = si->xe.num; 6697 ADD_PORT(xe, port); 6698 ADD_PORT(ether, port); 6699 bname = "xe"; 6700 #ifdef BCM_TRIUMPH3_SUPPORT 6701 if (SOC_IS_TRIUMPH3(unit)) { 6702 if (si->port_speed_max[port] == 42000) { 6703 si->port_speed_max[port] = 40000; 6704 } 6705 } 6706 #endif /* BCM_TRIUMPH3_SUPPORT */ 6707 #ifdef BCM_SHADOW_SUPPORT 6708 if (SOC_IS_SHADOW(unit) && 6709 ( 6710 soc_property_get(unit, spn_BCM88732_2X40_8X10, 0) || 6711 soc_property_get(unit, spn_BCM88732_1X40_4X10, 0) || 6712 soc_property_get(unit, spn_BCM88732_4X10_4X10, 0))) { 6713 /* TDM16 and TDM 17 */ 6714 if (SOC_PBMP_MEMBER(pbmp_disabled, port)) { 6715 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, port); 6716 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, port); 6717 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, port); 6718 } 6719 } 6720 } else if (soc_property_get(unit, spn_BCM88732_2X40_2X40, 0) || 6721 soc_property_get(unit, spn_BCM88732_2X40_1X40, 0) || 6722 soc_property_get(unit, spn_BCM88732_8X10_1X40, 0) || 6723 soc_property_get(unit, spn_BCM88732_8X10_2X40, 0)) { 6724 /* Interlaken Modes */ 6725 pno = si->il.num; 6726 ADD_PORT(il, port); 6727 bname = "il"; 6728 if (SOC_PBMP_MEMBER(pbmp_disabled, port)) { 6729 SOC_PBMP_PORT_ADD(si->il.disabled_bitmap, port); 6730 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, port); 6731 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, port); 6732 } 6733 #endif /* BCM_SHADOW_SUPPORT */ 6734 } 6735 #ifdef BCM_HURRICANE2_SUPPORT 6736 else if ((SOC_IS_HURRICANE2(unit)|| SOC_IS_GREYHOUND(unit) || 6737 SOC_IS_HURRICANE3(unit) || SOC_IS_GREYHOUND2(unit)) && 6738 (SOC_PBMP_MEMBER(pbmp_xport_ge, port))) { /* GE */ 6739 pno = si->ge.num; 6740 si->port_speed_max[port] = 1000; 6741 #ifdef BCM_GREYHOUND_SUPPORT 6742 if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit) || 6743 SOC_IS_GREYHOUND2(unit)) { 6744 si->port_speed_max[port] = 2500; 6745 } 6746 #endif 6747 ADD_PORT(ge, port); 6748 ADD_PORT(ether, port); 6749 bname = "ge"; 6750 } 6751 #endif 6752 #ifdef BCM_TRIUMPH3_SUPPORT 6753 else if (SOC_IS_TRIUMPH3(unit) && (si->port_speed_max[port] == 40000)) { 6754 pno = si->xe.num; 6755 ADD_PORT(xe, port); 6756 ADD_PORT(ether, port); 6757 bname = "xe"; 6758 } 6759 #endif /* BCM_TRIUMPH3_SUPPORT */ 6760 else { /* HG */ 6761 #if defined(BCM_TOMAHAWK_SUPPORT) 6762 if (SOC_IS_TOMAHAWKX(unit)) { 6763 if (latency[unit]) { /* multiplex as flag */ 6764 continue; 6765 } 6766 6767 /* one time */ 6768 SOC_IF_ERROR_RETURN(soc_th_latency_get(unit, &latency[unit])); 6769 if (latency[unit]) { 6770 /* Disable HG ports for low latency modes */ 6771 LOG_ERROR(BSL_LS_SOC_COMMON, 6772 (BSL_META_U(unit, 6773 "INFO: HiGig ports not supported in low " 6774 "latency modes\n" 6775 "ERROR: HiGig ports specified in config.bcm" 6776 " ignored\n" 6777 "INFO: To enable HG ports configure unit " 6778 "for normal latency in config.bcm\n"))); 6779 continue; 6780 } 6781 pno = si->hg.num; 6782 ADD_PORT(hg, port); 6783 ADD_PORT(st, port); 6784 /* name is default to hg by lookup above */ 6785 } else 6786 #endif /*BCM_TOMAHAWK_SUPPORT */ 6787 { 6788 pno = si->hg.num; 6789 ADD_PORT(hg, port); 6790 ADD_PORT(st, port); 6791 /* name is default to hg by lookup above */ 6792 } 6793 } 6794 #if defined(BCM_SHADOW_SUPPORT) 6795 if (SOC_IS_SHADOW(unit)) { 6796 if (SOC_PBMP_MEMBER(pbmp_xl, port)) { 6797 ADD_PORT(xl, port); 6798 } 6799 } else 6800 #endif /* BCM_SHADOW_SUPPORT */ 6801 { 6802 6803 if (!IS_CL_PORT(unit, port) && !IS_CLG2_PORT(unit, port) && 6804 !IS_XLB0_PORT(unit, port)) { 6805 ADD_PORT(xl, port); 6806 } 6807 } 6808 if (!SOC_IS_TRIUMPH3(unit) && !SOC_IS_SABER2(unit) && !SOC_IS_HELIX5(unit)) { 6809 6810 ADD_PORT(gx, port); 6811 } 6812 ADD_PORT(port, port); 6813 ADD_PORT(all, port); 6814 break; 6815 case SOC_BLK_GXPORT: 6816 if(SOC_IS_GREYHOUND(unit)&& (skip_blk_port == 1)){ 6817 si->block_valid[blk] += 1; 6818 continue; 6819 } 6820 #ifdef BCM_HELIX5_SUPPORT 6821 if (SOC_IS_HELIX5(unit)) { 6822 int qmode; 6823 soc_helix5_port_qsgmii_mode_get(unit, port, &qmode); 6824 if (qmode) { 6825 ADD_PORT(qsgmii, port); 6826 } 6827 } 6828 #endif 6829 if (!si->port_speed_max[port]) { 6830 if (SOC_PBMP_MEMBER(pbmp_xport_ge, port)) { 6831 si->port_speed_max[port] = 2500; 6832 } else if (SOC_PBMP_MEMBER(pbmp_gx25g, port)) { 6833 si->port_speed_max[port] = 25000; 6834 } else if (SOC_PBMP_MEMBER(pbmp_gx21g, port)) { 6835 si->port_speed_max[port] = 21000; 6836 } else if (SOC_PBMP_MEMBER(pbmp_gx20g, port)) { 6837 si->port_speed_max[port] = 20000; 6838 } else if (SOC_PBMP_MEMBER(pbmp_gx16g, port)) { 6839 si->port_speed_max[port] = 16000; 6840 } else if (SOC_PBMP_MEMBER(pbmp_gx13g, port)) { 6841 si->port_speed_max[port] = 13000; 6842 } else if (SOC_PBMP_MEMBER(pbmp_gx12g, port)) { 6843 si->port_speed_max[port] = 12000; 6844 } else { 6845 si->port_speed_max[port] = 10000; 6846 } 6847 } 6848 if (si->port_speed_max[port] < 10000) { /* GE */ 6849 pno = si->ge.num; 6850 ADD_PORT(ge, port); 6851 ADD_PORT(ether, port); 6852 bname = "ge"; 6853 } else if (SOC_PBMP_MEMBER(pbmp_xport_xe, port)) { /* XE */ 6854 pno = si->xe.num; 6855 ADD_PORT(xe, port); 6856 ADD_PORT(ether, port); 6857 bname = "xe"; 6858 } else { /* HG */ 6859 pno = si->hg.num; 6860 ADD_PORT(hg, port); 6861 ADD_PORT(st, port); 6862 /* name is default to hg by lookup above */ 6863 } 6864 if (!SOC_IS_GREYHOUND(unit)) { 6865 /* no xe capability in Greyhound's SOC_BLK_GXPORT */ 6866 ADD_PORT(gx, port); 6867 } 6868 if (SOC_PBMP_MEMBER(pbmp_hyplite, port)) { 6869 ADD_PORT(hyplite, port); 6870 } 6871 ADD_PORT(port, port); 6872 ADD_PORT(all, port); 6873 break; 6874 case SOC_BLK_XQPORT: 6875 case SOC_BLK_XGPORT: 6876 if (SOC_PBMP_MEMBER(pbmp_xport_ge, port)) { /* GE */ 6877 pno = si->ge.num; 6878 ADD_PORT(ge, port); 6879 ADD_PORT(ether, port); 6880 bname = "ge"; 6881 } else { 6882 if (!si->port_speed_max[port]) { 6883 if (SOC_PBMP_MEMBER(pbmp_xq12g, port)) { 6884 si->port_speed_max[port] = 12000; 6885 } else if (SOC_PBMP_MEMBER(pbmp_xq13g, port)) { 6886 si->port_speed_max[port] = 13000; 6887 } else if (SOC_PBMP_MEMBER(pbmp_xq10g, port)) { 6888 si->port_speed_max[port] = 10000; 6889 } else if (SOC_PBMP_MEMBER(pbmp_xg2p5g, port) || 6890 SOC_PBMP_MEMBER(pbmp_xq2p5g, port)) { 6891 si->port_speed_max[port] = 2500; 6892 } else { 6893 si->port_speed_max[port] = 1000; 6894 } 6895 } 6896 if (SOC_PBMP_MEMBER(pbmp_xq12g, port) || 6897 SOC_PBMP_MEMBER(pbmp_xq13g, port) || 6898 SOC_PBMP_MEMBER(pbmp_xq10g, port)) { 6899 ADD_PORT(gx, port); 6900 } 6901 if (si->port_speed_max[port] >= 10000) { 6902 if (SOC_PBMP_MEMBER(pbmp_xport_xe, port)) { /* XE */ 6903 pno = si->xe.num; 6904 ADD_PORT(xe, port); 6905 ADD_PORT(ether, port); 6906 bname = "xe"; 6907 } else { /* HG */ 6908 pno = si->hg.num; 6909 ADD_PORT(hg, port); 6910 ADD_PORT(st, port); 6911 bname = "hg"; 6912 } 6913 } else { 6914 pno = si->ge.num; 6915 ADD_PORT(ge, port); 6916 if (SOC_PBMP_MEMBER(pbmp_gport_stack, port)) { 6917 /* GE in Higig Lite Mode. Higig Like stack capable 6918 * port */ 6919 ADD_PORT(st, port); 6920 ADD_PORT(hl, port); 6921 } else { 6922 ADD_PORT(ether, port); 6923 } 6924 } 6925 } 6926 if (SOC_PBMP_MEMBER(pbmp_disabled, port)) { 6927 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, port); 6928 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, port); 6929 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, port); 6930 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, port); 6931 } 6932 if (SOC_PBMP_MEMBER(pbmp_xq, port)) { 6933 ADD_PORT(xq, port); 6934 } else { 6935 ADD_PORT(xg, port); 6936 } 6937 if (SOC_PBMP_MEMBER(pbmp_hyplite, port)) { 6938 ADD_PORT(hyplite, port); 6939 } 6940 ADD_PORT(port, port); 6941 ADD_PORT(all, port); 6942 break; 6943 case SOC_BLK_SPORT: 6944 pno = si->ge.num; 6945 ADD_PORT(ge, port); 6946 ADD_PORT(ether, port); 6947 ADD_PORT(port, port); 6948 ADD_PORT(all, port); 6949 break; 6950 case SOC_BLK_RDB: 6951 si->rdb_port = port; 6952 pno = si->rdbport.num; 6953 ADD_PORT(rdbport, port); 6954 ADD_PORT(all, port); 6955 break; 6956 case SOC_BLK_BROADSCAN: 6957 si->fae_port = port; 6958 pno = si->faeport.num; 6959 ADD_PORT(faeport, port); 6960 ADD_PORT(all, port); 6961 bname = "fae"; 6962 break; 6963 case SOC_BLK_MACSEC: 6964 si->macsec_port = port; 6965 pno = si->macsecport.num; 6966 ADD_PORT(macsecport, port); 6967 ADD_PORT(all, port); 6968 break; 6969 case SOC_BLK_LBPORT: 6970 pno = si->lbport.num; 6971 ADD_PORT(lbport, port); 6972 ADD_PORT(all, port); 6973 /* keep legacy setup for device with single loopback port */ 6974 si->lb_port = port; 6975 SOC_PBMP_PORT_ADD(si->lb_pbm, port); 6976 break; 6977 case SOC_BLK_AXP: 6978 pno = si->axp.num; 6979 ADD_PORT(axp, port); 6980 ADD_PORT(all, port); 6981 bname = "axp"; 6982 break; 6983 case SOC_BLK_CPIC: 6984 case SOC_BLK_CMIC: 6985 pno = 0; 6986 si->cmic_port = port; 6987 si->cmic_block = blk; 6988 SOC_PBMP_PORT_ADD(si->cmic_bitmap, port); 6989 ADD_PORT(all, port); 6990 break; 6991 case SOC_BLK_PGW_CL: 6992 /* don't use the name from this block */ 6993 blktype = old_blktype; 6994 bname = old_bname; 6995 break; 6996 case SOC_BLK_CDPORT: 6997 if (SOC_BLK_CDPORT == blktype) { 6998 ADD_PORT(cd, port); 6999 } 7000 7001 if (SOC_PBMP_MEMBER(pbmp_xport_xe, port)) { 7002 7003 if (si->port_speed_max[port] >= 100000 && 7004 si->port_speed_max[port] <= 400000) { 7005 7006 ADD_PORT(c, port); 7007 /* For 200G and 400G ports, the internal port bitmap 7008 * is cde, but externally (on the console) it is still 7009 * referred to as cd to keep the convention similar 7010 * to xe and ce for users 7011 */ 7012 if (si->port_speed_max[port] == 400000 || 7013 si->port_speed_max[port] == 200000) { 7014 pno = si->cde.num; 7015 ADD_PORT(cde, port); 7016 bname = "cd"; 7017 } else { 7018 pno = si->ce.num; 7019 ADD_PORT(ce, port); 7020 bname = "ce"; 7021 } 7022 } else { /* XE */ 7023 pno = si->xe.num; 7024 ADD_PORT(xe, port); 7025 bname = "xe"; 7026 } 7027 ADD_PORT(ether, port); 7028 } else { 7029 pno = 0; 7030 } 7031 7032 ADD_PORT(port, port); 7033 ADD_PORT(all, port); 7034 7035 break; 7036 default: 7037 pno = 0; 7038 break; 7039 } 7040 7041 #ifdef BCM_KATANA2_SUPPORT 7042 if ((SOC_IS_KATANA2(unit) && (!SOC_IS_SABER2(unit)) && (port == KT2_OLP_PORT))) { 7043 if (si->olp_port[0] == 1) { 7044 si->block_valid[si->olp_block] = 1; 7045 SOC_DRIVER(unit)->port_info[KT2_OLP_PORT].blk = 7046 si->olp_block; 7047 SOC_DRIVER(unit)->port_info[KT2_OLP_PORT].bindex = 0; 7048 si->block_port[si->olp_block] = port; 7049 SOC_PBMP_PORT_REMOVE(si->block_bitmap[mxq7_blk], port); 7050 SOC_PBMP_PORT_ADD(si->block_bitmap[si->olp_block], port); 7051 LOG_VERBOSE(BSL_LS_SOC_COMMON, 7052 (BSL_META_U(unit, 7053 "OLP Port Configuration blk=%d" 7054 "schain=%d cmic=%d\n"), 7055 SOC_DRIVER(unit)->port_info[KT2_OLP_PORT].blk, 7056 SOC_DRIVER(unit)->block_info[si->olp_block]. 7057 schan, 7058 SOC_DRIVER(unit)->block_info[si->olp_block]. 7059 cmic)); 7060 } else { 7061 si->block_valid[mxq7_blk] = 1; 7062 SOC_DRIVER(unit)->port_info[KT2_OLP_PORT].blk = mxq7_blk; 7063 SOC_DRIVER(unit)->port_info[KT2_OLP_PORT].bindex = 3; 7064 si->block_port[mxq7_blk] = port; 7065 SOC_PBMP_PORT_ADD(si->block_bitmap[mxq7_blk], port); 7066 SOC_PBMP_PORT_REMOVE(si->block_bitmap[si->olp_block], port); 7067 LOG_VERBOSE(BSL_LS_SOC_COMMON, 7068 (BSL_META_U(unit, 7069 "OLP Port Configuration blk=%d" 7070 "schain=%d cmic=%d\n"), 7071 SOC_DRIVER(unit)->port_info[KT2_OLP_PORT].blk, 7072 SOC_DRIVER(unit)->block_info[mxq7_blk].schan, 7073 SOC_DRIVER(unit)->block_info[mxq7_blk].cmic)); 7074 } 7075 } else 7076 #endif 7077 { 7078 si->block_valid[blk] += 1; 7079 if (si->block_port[blk] < 0) { 7080 si->block_port[blk] = port; 7081 } 7082 SOC_PBMP_PORT_ADD(si->block_bitmap[blk], port); 7083 } 7084 } 7085 7086 if (bname[0] == '?') { 7087 pno = port; 7088 } 7089 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]), 7090 "%s%d", bname, pno); 7091 si->port_type[port] = blktype; 7092 si->port_offset[port] = pno; 7093 #ifdef BCM_SHADOW_SUPPORT 7094 if (SOC_IS_SHADOW(unit)) { 7095 /* Add ports 1 through 8 to the MACSEC blocks */ 7096 /* Add ports 9 and 13 to the IL blocks */ 7097 blk = 0; 7098 while (SOC_BLOCK_INFO(unit, blk).type != -1) { 7099 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_MS_ISEC) || 7100 (SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_MS_ESEC)) { 7101 if (((SOC_BLOCK_INFO(unit, blk).number == 0) && (port >= 1) 7102 && (port <= 4)) || 7103 ((SOC_BLOCK_INFO(unit, blk).number == 1) && (port >= 5) 7104 && (port <= 8))) { 7105 si->block_valid[blk] += 1; 7106 if (si->block_port[blk] < 0) { 7107 si->block_port[blk] = port; 7108 } 7109 SOC_PBMP_PORT_ADD(si->block_bitmap[blk], port); 7110 } 7111 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_MS_ISEC) && 7112 (SOC_BLOCK_INFO(unit, blk).number == 0)) { 7113 si->ms_isec_block[0] = blk; 7114 } 7115 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_MS_ISEC) && 7116 (SOC_BLOCK_INFO(unit, blk).number == 1)) { 7117 si->ms_isec_block[1] = blk; 7118 } 7119 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_MS_ESEC) && 7120 (SOC_BLOCK_INFO(unit, blk).number == 0)) { 7121 si->ms_esec_block[0] = blk; 7122 } 7123 if ((SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_MS_ESEC) && 7124 (SOC_BLOCK_INFO(unit, blk).number == 1)) { 7125 si->ms_esec_block[1] = blk; 7126 } 7127 } 7128 if (SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_IL) { 7129 if (((SOC_BLOCK_INFO(unit, blk).number == 0) && (port == 9)) 7130 || ((SOC_BLOCK_INFO(unit, blk).number == 1) && 7131 (port == 13))) { 7132 if (!SOC_PBMP_MEMBER(si->il.disabled_bitmap, port)) { 7133 si->block_valid[blk] += 1; 7134 } 7135 if (si->block_port[blk] < 0) { 7136 si->block_port[blk] = port; 7137 } 7138 SOC_PBMP_PORT_ADD(si->block_bitmap[blk], port); 7139 } 7140 if ((SOC_BLOCK_INFO(unit, blk).number == 0)) { 7141 si->il_block[0] = blk; 7142 } 7143 if ((SOC_BLOCK_INFO(unit, blk).number == 1)) { 7144 si->il_block[1] = blk; 7145 } 7146 } 7147 if (SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_CW) { 7148 si->block_valid[blk] += 1; 7149 if ((SOC_BLOCK_INFO(unit, blk).number == 0)) { 7150 si->cw = blk; 7151 } 7152 } 7153 blk++; 7154 } 7155 } 7156 #endif /* BCM_SHADOW_SUPPORT */ 7157 #ifdef BCM_KATANA2_SUPPORT 7158 if (SOC_IS_KATANA2(unit)) { 7159 if (soc_kt2_linkphy_port_reg_blk_idx_get(unit, port, 7160 SOC_BLK_TXLP, &blk, NULL) == SOC_E_NONE) { 7161 /* Is a TXLP Port */ 7162 si->block_valid[blk] += 1; 7163 if (si->block_port[blk] < 0) { 7164 si->block_port[blk] = port; 7165 } 7166 SOC_PBMP_PORT_ADD(si->block_bitmap[blk], port); 7167 } 7168 if (soc_kt2_linkphy_port_reg_blk_idx_get(unit, port, 7169 SOC_BLK_RXLP, &blk, NULL) == SOC_E_NONE) { 7170 /* Is a RXLP Port */ 7171 si->block_valid[blk] += 1; 7172 if (si->block_port[blk] < 0) { 7173 si->block_port[blk] = port; 7174 } 7175 SOC_PBMP_PORT_ADD(si->block_bitmap[blk], port); 7176 } 7177 } 7178 #endif /* BCM_KATANA2_SUPPORT */ 7179 #ifdef BCM_METROLITE_SUPPORT 7180 if (SOC_IS_METROLITE(unit)) { 7181 if (soc_ml_iecell_port_reg_blk_idx_get(unit, port, 7182 SOC_BLK_IECELL, &blk, NULL) == SOC_E_NONE) { 7183 /* Is a IECELL Port */ 7184 si->block_valid[blk] += 1; 7185 if (si->block_port[blk] < 0) { 7186 si->block_port[blk] = port; 7187 } 7188 SOC_PBMP_PORT_ADD(si->block_bitmap[blk], port); 7189 } 7190 } else 7191 #endif /* BCM_METROLITE_SUPPORT */ 7192 #if defined (BCM_SABER2_SUPPORT) 7193 if (SOC_IS_SABER2(unit)) { 7194 if (soc_sb2_iecell_port_reg_blk_idx_get(unit, port, 7195 SOC_BLK_IECELL, &blk, NULL) == SOC_E_NONE) { 7196 /* Is a IECELL Port */ 7197 si->block_valid[blk] += 1; 7198 if (si->block_port[blk] < 0) { 7199 si->block_port[blk] = port; 7200 } 7201 SOC_PBMP_PORT_ADD(si->block_bitmap[blk], port); 7202 } 7203 } 7204 #endif /* BCM_SABER2_SUPPORT */ 7205 } 7206 port = max_port + 1; 7207 7208 #ifdef BCM_TRIUMPH3_SUPPORT 7209 if (SOC_IS_TRIUMPH3(unit)) { 7210 int hp, hgc = 0; 7211 PBMP_HG_ITER(unit, hp) { 7212 if (!SOC_PBMP_MEMBER(SOC_PORT_DISABLED_BITMAP(unit, port), hp)) { 7213 hgc++; 7214 } 7215 } 7216 if (hgc > _SOC_TR3_MAX_HG_PORT_COUNT) { 7217 LOG_ERROR(BSL_LS_SOC_COMMON, 7218 (BSL_META_U(unit, 7219 "Port config error (Higig port count[%d] exceeded) !!\n"), 7220 hgc)); 7221 return SOC_E_CONFIG; 7222 } 7223 } 7224 #endif /* BCM_TRIUMPH3_SUPPORT */ 7225 7226 /* The last ports are the loopback port in the internal MMU ports*/ 7227 if (si->internal_loopback) { 7228 #if defined(BCM_ENDURO_SUPPORT) 7229 if(SOC_IS_ENDURO(unit)) { 7230 int port_temp; 7231 port_temp = port; 7232 for (port = 1; port <= 29; port++) { 7233 /* The LB port in Enduro could be port 1 or HG ports, not the last port */ 7234 if (IS_LB_PORT(unit, port)) { 7235 ADD_PORT(all, port); 7236 si->port_type[port] = SOC_BLK_EPIPE; 7237 si->port_offset[port] = 0; 7238 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]), 7239 "%s%d", "lb", 0); 7240 } 7241 } 7242 /* Since the LB port in Enduro is port 1, not the last port. 7243 recover the port to previous value */ 7244 port = port_temp; 7245 } else 7246 #endif /* BCM_ENDURO_SUPPORT */ 7247 #if defined(BCM_KATANA_SUPPORT) 7248 if(SOC_IS_SABER2(unit)) { 7249 int port_temp = port; 7250 7251 if (!IS_LB_PORT(unit, port) && IS_LB_PORT(unit, port-1)) { 7252 /* If this is not LB port, Possibly the LB port is added as a 7253 regular port in the regfile.. Just check the previous port */ 7254 port_temp -= 1; 7255 } 7256 ADD_PORT(all, port_temp); 7257 si->port_type[port_temp] = SOC_BLK_EPIPE; 7258 si->port_offset[port_temp] = 0; 7259 sal_snprintf(si->port_name[port_temp], 7260 sizeof(si->port_name[port_temp]), "%s%d", "lb", 0); 7261 /* Loopback port is the last port. */ 7262 port = port_temp + 1; 7263 } else if(SOC_IS_KATANAX(unit)) { 7264 7265 int port_temp; 7266 port_temp = port; 7267 for (port = 35; port <= 41; port++) { 7268 if (IS_LB_PORT(unit, port)) { 7269 ADD_PORT(all, port); 7270 si->port_type[port] = SOC_BLK_EPIPE; 7271 si->port_offset[port] = 0; 7272 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]), 7273 "%s%d", "lb", (port - 35)); 7274 } 7275 } 7276 port = port_temp; 7277 } else 7278 #endif /* BCM_KATANA_SUPPORT */ 7279 { 7280 ADD_PORT(all, port); 7281 si->port_type[port] = SOC_BLK_EPIPE; 7282 si->port_offset[port] = 0; 7283 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]), 7284 "%s%d", "lb", 0); 7285 /* Loopback port is the last port. */ 7286 port++; 7287 } 7288 } 7289 if(!SOC_IS_ENDURO(unit) && !SOC_IS_KATANAX(unit)) { 7290 if (si->internal_loopback) { 7291 ADD_PORT(mmu, port); 7292 si->port_type[port] = SOC_BLK_MMU; 7293 si->port_offset[port] = 0; 7294 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]), 7295 "%s%d", "mmu", 0); 7296 port++; 7297 ADD_PORT(mmu, port); 7298 si->port_type[port] = SOC_BLK_MMU; 7299 si->port_offset[port] = 1; 7300 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]), 7301 "%s%d", "mmu", 1); 7302 port++; 7303 } 7304 } 7305 /* Cache the port count from the above loop. 7306 NOTE: for future code changes: 7307 Do not modify the 'port' variable before the below assignment */ 7308 si->port_num = port; 7309 7310 for (port = 0; port < SOC_MAX_NUM_PP_PORTS; port++) { 7311 if (SOC_PBMP_MEMBER(pbmp_pp, port)) { 7312 ADD_PORT(pp, port); 7313 } 7314 } 7315 #undef ADD_PORT 7316 7317 /* Generate logical to physical and mmu to physical port mapping */ 7318 if (soc_feature(unit, soc_feature_logical_port_num)) { 7319 for (port = 0; port < phy_port; port++) { 7320 si->port_l2p_mapping[port] = -1; 7321 si->port_m2p_mapping[port] = -1; 7322 } 7323 for (port = 0; port < phy_port; port++) { 7324 if (si->port_p2l_mapping[port] != -1) { 7325 si->port_l2p_mapping[si->port_p2l_mapping[port]] = port; 7326 } 7327 if (si->port_p2m_mapping[port] != -1) { 7328 si->port_m2p_mapping[si->port_p2m_mapping[port]] = port; 7329 } 7330 } 7331 /* Cleanup */ 7332 for (port = 0; port < phy_port; port++) { 7333 if (si->flex_port_p2l_mapping[port] == -1) { 7334 si->port_speed_max[si->port_p2l_mapping[port]] = 0; 7335 } 7336 } 7337 } 7338 7339 7340 /* some things need to be found in the block table */ 7341 si->arl_block = -1; 7342 si->mmu_block = -1; 7343 si->mcu_block = -1; 7344 7345 si->ipipe_block = -1; 7346 si->ipipe_hi_block = -1; 7347 si->epipe_block = -1; 7348 si->epipe_hi_block = -1; 7349 si->bsafe_block = -1; 7350 si->esm_block = -1; 7351 for (blk = 0; blk < SOC_MAX_NUM_OTPC_BLKS; blk++) { 7352 si->otpc_block[blk] = -1; 7353 } 7354 si->axp_block = -1; 7355 si->top_block = -1; 7356 si->ism_block = -1; 7357 si->etu_block = -1; 7358 si->ibod_block = -1; 7359 7360 si->igr_block = -1; 7361 si->egr_block = -1; 7362 si->bse_block = -1; 7363 si->cse_block = -1; 7364 si->hse_block = -1; 7365 si->iproc_block = -1; 7366 si->macsec_block = -1; 7367 si->crypto_block = -1; 7368 7369 sal_memset(si->has_block, 0, sizeof(soc_block_t) * COUNTOF(si->has_block)); 7370 7371 for (blk = 0; blk < SOC_MAX_NUM_CI_BLKS; blk++) { 7372 si->ci_block[blk] = -1; 7373 } 7374 7375 for (blk = 0; SOC_BLOCK_INFO(unit, blk).type >= 0; blk++) { 7376 blktype = SOC_BLOCK_INFO(unit, blk).type; 7377 instance = SOC_BLOCK_INFO(unit, blk).number; 7378 si->has_block[blk] = blktype; 7379 sal_snprintf(instance_string, sizeof(instance_string), "%d", 7380 SOC_BLOCK_INFO(unit, blk).number); 7381 switch (blktype) { 7382 case SOC_BLK_ARL: 7383 si->arl_block = blk; 7384 si->block_valid[blk] += 1; 7385 break; 7386 case SOC_BLK_MMU: 7387 si->mmu_block = blk; 7388 si->block_valid[blk] += 1; 7389 break; 7390 case SOC_BLK_MMU_GLB: 7391 si->mmu_glb_block = blk; 7392 si->block_valid[blk] += 1; 7393 break; 7394 case SOC_BLK_MMU_XPE: 7395 si->mmu_xpe_block = blk; 7396 si->block_valid[blk] += 1; 7397 break; 7398 case SOC_BLK_MMU_SC: 7399 si->mmu_sc_block = blk; 7400 si->block_valid[blk] += 1; 7401 break; 7402 case SOC_BLK_MMU_SED: 7403 si->mmu_sed_block = blk; 7404 si->block_valid[blk] += 1; 7405 break; 7406 case SOC_BLK_MMU_ITM: 7407 si->mmu_itm_block = blk; 7408 si->block_valid[blk] += 1; 7409 break; 7410 case SOC_BLK_MMU_EB: 7411 si->mmu_eb_block = blk; 7412 si->block_valid[blk] += 1; 7413 break; 7414 case SOC_BLK_MCU: 7415 si->mcu_block = blk; 7416 si->block_valid[blk] += 1; 7417 break; 7418 case SOC_BLK_IPIPE: 7419 si->ipipe_block = blk; 7420 si->block_valid[blk] += 1; 7421 break; 7422 case SOC_BLK_CI: 7423 si->ci_block[instance] = blk; 7424 si->block_valid[blk] += 1; 7425 si->block_port[blk] = (SOC_REG_ADDR_INSTANCE_MASK | instance); 7426 SOC_PBMP_PORT_ADD(si->block_bitmap[blk], instance); 7427 break; 7428 case SOC_BLK_IPIPE_HI: 7429 si->ipipe_hi_block = blk; 7430 si->block_valid[blk] += 1; 7431 SOC_PBMP_OR(si->block_bitmap[blk],PBMP_ST_ALL(unit)); 7432 SOC_PBMP_OR(si->block_bitmap[blk],PBMP_HG_ALL(unit)); 7433 SOC_PBMP_OR(si->block_bitmap[blk],PBMP_CMIC(unit)); 7434 break; 7435 case SOC_BLK_EPIPE: 7436 si->epipe_block = blk; 7437 si->block_valid[blk] += 1; 7438 break; 7439 case SOC_BLK_EPIPE_HI: 7440 si->epipe_hi_block = blk; 7441 si->block_valid[blk] += 1; 7442 SOC_PBMP_OR(si->block_bitmap[blk],PBMP_ST_ALL(unit)); 7443 SOC_PBMP_OR(si->block_bitmap[blk],PBMP_HG_ALL(unit)); 7444 SOC_PBMP_OR(si->block_bitmap[blk],PBMP_CMIC(unit)); 7445 break; 7446 #ifdef BCM_SHADOW_SUPPORT 7447 case SOC_BLK_BSE: /* Aliased with IL */ 7448 /* coverity[secure_coding] */ 7449 sal_strcpy(si->block_name[blk], "il"); 7450 break; 7451 case SOC_BLK_CSE: /* Aliased with MS_ISEC */ 7452 sal_strcpy(si->block_name[blk], "ms_isec"); 7453 break; 7454 case SOC_BLK_HSE: /* Aliased with MS_ESEC */ 7455 sal_strcpy(si->block_name[blk], "ms_esec"); 7456 break; 7457 case SOC_BLK_SYS: /* Aliased with CW */ 7458 sal_strcpy(si->block_name[blk], "cw"); 7459 break; 7460 #endif /* BCM_SHADOW_SUPPORT */ 7461 case SOC_BLK_BSAFE: 7462 si->bsafe_block = blk; 7463 si->block_valid[blk] += 1; 7464 break; 7465 case SOC_BLK_OTPC: 7466 si->otpc_block[instance] = blk; 7467 si->block_valid[blk] += 1; 7468 break; 7469 case SOC_BLK_ESM: 7470 si->esm_block = blk; 7471 si->block_valid[blk] += 1; 7472 break; 7473 case SOC_BLK_PGW_CL: 7474 si->pgw_cl_block[instance] = blk; 7475 si->block_valid[blk] += 1; 7476 break; 7477 case SOC_BLK_MACSEC: 7478 si->macsec_block = blk; 7479 si->block_valid[blk] += 1; 7480 break; 7481 case SOC_BLK_PORT_GROUP4: 7482 si->pg4_block[instance] = blk; 7483 sal_strcpy(instance_string, instance ? "_y" : "_x"); 7484 si->block_port[blk] = (SOC_REG_ADDR_INSTANCE_MASK | instance); 7485 si->block_valid[blk] += 1; 7486 break; 7487 case SOC_BLK_PORT_GROUP5: 7488 si->pg5_block[instance] = blk; 7489 sal_strcpy(instance_string, instance ? "_y" : "_x"); 7490 si->block_port[blk] = (SOC_REG_ADDR_INSTANCE_MASK | instance); 7491 si->block_valid[blk] += 1; 7492 break; 7493 case SOC_BLK_TOP: 7494 si->top_block = blk; 7495 si->block_valid[blk] += 1; 7496 break; 7497 case SOC_BLK_SER: 7498 si->ser_block = blk; 7499 si->block_valid[blk] += 1; 7500 break; 7501 case SOC_BLK_AVS: 7502 si->avs_block = blk; 7503 si->block_valid[blk] += 1; 7504 break; 7505 case SOC_BLK_AXP: 7506 si->axp_block = blk; 7507 si->block_valid[blk] += 1; 7508 break; 7509 case SOC_BLK_ISM: 7510 si->ism_block = blk; 7511 si->block_valid[blk] += 1; 7512 break; 7513 case SOC_BLK_ETU: 7514 si->etu_block = blk; 7515 si->block_valid[blk] += 1; 7516 break; 7517 case SOC_BLK_IBOD: 7518 si->ibod_block = blk; 7519 si->block_valid[blk] += 1; 7520 break; 7521 case SOC_BLK_LLS: 7522 si->lls_block = blk; 7523 si->block_valid[blk] += 1; 7524 break; 7525 case SOC_BLK_CES: 7526 si->ces_block = blk; 7527 si->block_valid[blk] += 1; 7528 break; 7529 case SOC_BLK_CEV: 7530 si->cev_block = blk; 7531 si->block_valid[blk] += 1; 7532 break; 7533 case SOC_BLK_IPROC: 7534 si->iproc_block = blk; 7535 si->block_valid[blk] += 1; 7536 break; 7537 case SOC_BLK_CRYPTO: 7538 si->crypto_block = blk; 7539 si->block_valid[blk] += 1; 7540 break; 7541 case SOC_BLK_CDMAC: 7542 sal_strcpy(si->block_name[blk], "cdmac"); 7543 si->block_valid[blk] += 1; 7544 break; 7545 case SOC_BLK_PMQPORT: 7546 case SOC_BLK_PMQ: 7547 if(SOC_IS_GREYHOUND(unit)){ 7548 if (si->port_p2l_mapping[2]== -1){ 7549 /* TSC0Q is powered down in some skus, 7550 it could be tell by checking the valid of physical port 2. */ 7551 break; 7552 } 7553 } 7554 si->pmq_block[instance] = blk; 7555 si->block_valid[blk] += 1; 7556 break; 7557 #ifdef BCM_HURRICANE3_SUPPORT 7558 case SOC_BLK_PGW_GE: 7559 if (SOC_IS_HURRICANE3(unit)) { 7560 si->pgw_ge_block[instance] = blk; 7561 sal_strcpy(instance_string, instance ? "_1" : "_0"); 7562 si->block_port[blk] = (SOC_REG_ADDR_INSTANCE_MASK | instance); 7563 si->block_valid[blk] += 1; 7564 } 7565 break; 7566 #endif /* BCM_HURRICANE3_SUPPORT */ 7567 #ifdef CANCUN_SUPPORT 7568 case SOC_BLK_CCH: 7569 si->block_valid[blk] += 1; 7570 break; 7571 #endif 7572 case SOC_BLK_TAF: 7573 si->taf_block = blk; 7574 si->block_valid[blk] += 1; 7575 break; 7576 } 7577 sal_snprintf(si->block_name[blk], sizeof(si->block_name[blk]), 7578 "%s%s", 7579 soc_block_name_lookup_ext(blktype, unit), 7580 instance_string); 7581 } 7582 si->block_num = blk; 7583 7584 /* 7585 * Calculate the mem_block_any array for this configuration 7586 * The "any" block is just the first one enabled 7587 */ 7588 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 7589 si->mem_block_any[mem] = -1; 7590 if (!SOC_MEM_IS_VALID(unit, mem)) { 7591 continue; 7592 } 7593 SOC_MEM_BLOCK_ITER(unit, mem, blk) { 7594 si->mem_block_any[mem] = blk; 7595 break; 7596 } 7597 } 7598 7599 switch (drv_dev_id) { 7600 #ifdef BCM_TRIDENT_SUPPORT 7601 case BCM56840_DEVICE_ID: 7602 soc_trident_num_cosq_init(unit); 7603 break; 7604 #endif /* BCM_TRIDENT_SUPPORT */ 7605 #ifdef BCM_TRIDENT2_SUPPORT 7606 case BCM56860_DEVICE_ID: 7607 case BCM56850_DEVICE_ID: 7608 soc_trident2_num_cosq_init(unit); 7609 break; 7610 #endif /* BCM_TRIDENT2_SUPPORT */ 7611 #ifdef BCM_TOMAHAWK_SUPPORT 7612 case BCM56960_DEVICE_ID: 7613 case BCM56961_DEVICE_ID: 7614 case BCM56962_DEVICE_ID: 7615 case BCM56963_DEVICE_ID: 7616 case BCM56930_DEVICE_ID: 7617 case BCM56968_DEVICE_ID: 7618 #if defined(BCM_TOMAHAWKPLUS_SUPPORT) 7619 case BCM56965_DEVICE_ID: 7620 case BCM56969_DEVICE_ID: 7621 case BCM56966_DEVICE_ID: 7622 case BCM56967_DEVICE_ID: 7623 #endif /* BCM_TOMAHAWKPLUS_SUPPORT */ 7624 case BCM56168_DEVICE_ID: 7625 case BCM56169_DEVICE_ID: 7626 7627 soc_tomahawk_num_cosq_init(unit); 7628 break; 7629 #endif /* BCM_TOMAHAWK_SUPPORT */ 7630 #ifdef BCM_TOMAHAWK3_SUPPORT 7631 case BCM56980_DEVICE_ID: 7632 case BCM56981_DEVICE_ID: 7633 case BCM56982_DEVICE_ID: 7634 case BCM56983_DEVICE_ID: 7635 case BCM56984_DEVICE_ID: 7636 PBMP_ALL_ITER(unit, port) { 7637 soc_tomahawk3_num_cosq_init(unit, port); 7638 } 7639 break; 7640 #endif /* BCM_TOMAHAWK3_SUPPORT */ 7641 #ifdef BCM_TRIDENT3_SUPPORT 7642 case BCM56870_DEVICE_ID: 7643 case BCM56873_DEVICE_ID: 7644 soc_trident3_num_cosq_init(unit); 7645 break; 7646 #endif /* BCM_TRIDENT3_SUPPORT */ 7647 #ifdef BCM_HELIX5_SUPPORT 7648 case BCM56370_DEVICE_ID: 7649 soc_helix5_num_cosq_init(unit); 7650 break; 7651 #endif /* BCM_HELIX5_SUPPORT */ 7652 #ifdef BCM_MAVERICK2_SUPPORT 7653 case BCM56770_DEVICE_ID: 7654 case BCM56771_DEVICE_ID: 7655 soc_maverick2_num_cosq_init(unit); 7656 break; 7657 #endif /* BCM_MAVERICK2_SUPPORT */ 7658 #ifdef BCM_TOMAHAWK2_SUPPORT 7659 case BCM56970_DEVICE_ID: 7660 case BCM56971_DEVICE_ID: 7661 case BCM56972_DEVICE_ID: 7662 case BCM56974_DEVICE_ID: 7663 case BCM56975_DEVICE_ID: 7664 7665 soc_tomahawk_num_cosq_init(unit); 7666 break; 7667 #endif /* BCM_TOMAHAWK2_SUPPORT */ 7668 7669 #ifdef BCM_KATANA_SUPPORT 7670 case BCM56440_DEVICE_ID: 7671 case BCM56441_DEVICE_ID: 7672 case BCM56442_DEVICE_ID: 7673 case BCM56443_DEVICE_ID: 7674 case BCM56445_DEVICE_ID: 7675 case BCM56446_DEVICE_ID: 7676 case BCM56447_DEVICE_ID: 7677 case BCM56448_DEVICE_ID: 7678 case BCM56449_DEVICE_ID: 7679 case BCM56240_DEVICE_ID: 7680 case BCM56241_DEVICE_ID: 7681 case BCM56242_DEVICE_ID: 7682 case BCM56243_DEVICE_ID: 7683 case BCM56245_DEVICE_ID: 7684 case BCM56246_DEVICE_ID: 7685 case BCM55440_DEVICE_ID: 7686 case BCM55441_DEVICE_ID: 7687 soc_katana_num_cosq_init(unit); 7688 break; 7689 #endif /* BCM_KATANA_SUPPORT */ 7690 #ifdef BCM_KATANA2_SUPPORT 7691 case BCM55450_DEVICE_ID: 7692 case BCM55455_DEVICE_ID: 7693 case BCM56248_DEVICE_ID: 7694 case BCM56450_DEVICE_ID: 7695 case BCM56452_DEVICE_ID: 7696 case BCM56454_DEVICE_ID: 7697 case BCM56455_DEVICE_ID: 7698 case BCM56456_DEVICE_ID: 7699 case BCM56457_DEVICE_ID: 7700 case BCM56458_DEVICE_ID: 7701 SOC_IF_ERROR_RETURN(soc_katana2_num_cosq_init(unit)); 7702 break; 7703 #endif /* BCM_KATANA2_SUPPORT */ 7704 #ifdef BCM_SABER2_SUPPORT 7705 case BCM56260_DEVICE_ID: 7706 case BCM56261_DEVICE_ID: 7707 case BCM56262_DEVICE_ID: 7708 case BCM56263_DEVICE_ID: 7709 case BCM56265_DEVICE_ID: 7710 case BCM56266_DEVICE_ID: 7711 case BCM56267_DEVICE_ID: 7712 case BCM56268_DEVICE_ID: 7713 case BCM56233_DEVICE_ID: 7714 case BCM56460_DEVICE_ID: 7715 case BCM56461_DEVICE_ID: 7716 case BCM56462_DEVICE_ID: 7717 case BCM56463_DEVICE_ID: 7718 case BCM56465_DEVICE_ID: 7719 case BCM56466_DEVICE_ID: 7720 case BCM56467_DEVICE_ID: 7721 case BCM56468_DEVICE_ID: 7722 SOC_IF_ERROR_RETURN(soc_saber2_num_cosq_init(unit)); 7723 break; 7724 #endif /* BCM_SABER2_SUPPORT */ 7725 7726 #ifdef BCM_METROLITE_SUPPORT 7727 case BCM56270_DEVICE_ID: 7728 case BCM56271_DEVICE_ID: 7729 case BCM56272_DEVICE_ID: 7730 7731 case BCM53460_DEVICE_ID: 7732 case BCM53461_DEVICE_ID: 7733 7734 SOC_IF_ERROR_RETURN(soc_metrolite_num_cosq_init(unit)); 7735 break; 7736 #endif /* BCM_METROLITE_SUPPORT */ 7737 #ifdef BCM_APACHE_SUPPORT 7738 case BCM56560_DEVICE_ID: 7739 soc_apache_num_cosq_init(unit); 7740 break; 7741 #endif /* BCM_APACHE_SUPPORT */ 7742 #ifdef BCM_MONTEREY_SUPPORT 7743 case BCM56670_DEVICE_ID: 7744 case BCM56671_DEVICE_ID: 7745 case BCM56672_DEVICE_ID: 7746 case BCM56675_DEVICE_ID: 7747 soc_monterey_num_cosq_init(unit); 7748 break; 7749 #endif /* BCM_APACHE_SUPPORT */ 7750 7751 #ifdef BCM_TRIUMPH3_SUPPORT 7752 case BCM56640_DEVICE_ID: 7753 case BCM56643_DEVICE_ID: 7754 case BCM56644_DEVICE_ID: 7755 case BCM56648_DEVICE_ID: 7756 case BCM56649_DEVICE_ID: 7757 case BCM56540_DEVICE_ID: 7758 case BCM56541_DEVICE_ID: 7759 case BCM56542_DEVICE_ID: 7760 case BCM56543_DEVICE_ID: 7761 case BCM56544_DEVICE_ID: 7762 case BCM56545_DEVICE_ID: 7763 case BCM56546_DEVICE_ID: 7764 case BCM56044_DEVICE_ID: 7765 case BCM56045_DEVICE_ID: 7766 case BCM56046_DEVICE_ID: 7767 soc_triumph3_init_num_cosq(unit); 7768 break; 7769 #endif /* BCM_TRIUMPH3_SUPPORT */ 7770 #ifdef BCM_HELIX4_SUPPORT 7771 case BCM56548H_DEVICE_ID: 7772 case BCM56548_DEVICE_ID: 7773 case BCM56547_DEVICE_ID: 7774 case BCM56346_DEVICE_ID: 7775 case BCM56345_DEVICE_ID: 7776 case BCM56344_DEVICE_ID: 7777 case BCM56342_DEVICE_ID: 7778 case BCM56340_DEVICE_ID: 7779 case BCM56049_DEVICE_ID: 7780 case BCM56048_DEVICE_ID: 7781 case BCM56047_DEVICE_ID: 7782 case BCM56042_DEVICE_ID: 7783 case BCM56041_DEVICE_ID: 7784 case BCM56040_DEVICE_ID: 7785 soc_hx4_init_num_cosq(unit); 7786 break; 7787 #endif 7788 default: 7789 break; 7790 } 7791 7792 soc_esw_dport_init(unit); 7793 7794 7795 #if defined(BCM_ESW_SUPPORT) && defined(BCM_IPROC_SUPPORT) 7796 /* 7797 * Add/Remove features, update soc_control cache based on 7798 * BondOptions info read from the relevant capability registers 7799 */ 7800 if (soc_feature(unit, soc_feature_untethered_otp)) { 7801 soc_info_bondoptions_adjust(unit); 7802 } 7803 #endif /* BCM_ESW_SUPPORT && BCM_IPROC_SUPPORT */ 7804 7805 #ifdef INCLUDE_RCPU 7806 if (SOC_IS_RCPU_ONLY(unit)) { 7807 soc_rcpu_cfg_t cfg; 7808 if (SOC_E_NONE == soc_cm_get_rcpu_cfg(unit, &cfg)) { 7809 si->rcpu_port = cfg.port; 7810 } else { 7811 si->rcpu_port = -1; 7812 } 7813 } 7814 #endif /* INCLUDE_RCPU */ 7815 /* Allocate MMU LLS usage map for all valid ports. 7816 * The code below is moved from soc_attach() to 7817 * soc_info_config() as soc_attach() is not invoked 7818 * during subsequent "rc" after first initialization is complete. 7819 * The move is done to ensure that if the number of ports change 7820 * due to any config then the MMU LLS usage bmap 7821 * allocation is accounted for new ports. 7822 */ 7823 #if defined(BCM_KATANA_SUPPORT) 7824 if (SOC_IS_KATANA(unit)) { 7825 soc_kt_lls_bmap_alloc(unit); 7826 } 7827 #endif /* BCM_KATANA_SUPPORT */ 7828 7829 #if defined(BCM_KATANA2_SUPPORT) 7830 if (SOC_IS_KATANA2(unit)) { 7831 soc_kt2_lls_bmap_alloc(unit); 7832 } 7833 #endif /* BCM_KATANA2_SUPPORT */ 7834 7835 return SOC_E_NONE; 7836 } 7837 7838 /* 7839 * Function: 7840 * soc_max_supported_vrf_get 7841 * Purpose: 7842 * Utility routine for reading maximum supported vrf value for the device. 7843 * Parameters: 7844 * unit - (IN) Unit number. 7845 * value - (OUT) Max vrf value. 7846 * Returns: 7847 * SOC_E_NONE 7848 */ 7849 int 7850 soc_max_supported_vrf_get(int unit, uint16 *value) 7851 { 7852 int bit_num = 0; 7853 #if defined(BCM_TRIUMPH_SUPPORT) 7854 uint16 dev_id; 7855 uint8 rev_id; 7856 #endif /* BCM_TRIUMPH_SUPPORT */ 7857 7858 if (NULL == value) { 7859 return (SOC_E_PARAM); 7860 } 7861 7862 #if defined (BCM_ESW_SUPPORT) && defined (BCM_IPROC_SUPPORT) 7863 if (soc_feature(unit, soc_feature_untethered_otp) && 7864 SOC_MEM_IS_VALID(unit, VRFm)) { 7865 *value = soc_mem_index_max(unit, VRFm); 7866 return SOC_E_NONE; 7867 } 7868 #endif 7869 7870 #if defined(BCM_TRIUMPH_SUPPORT) 7871 soc_cm_get_id(unit, &dev_id, &rev_id); 7872 7873 if (SOC_IS_TRIUMPH(unit) || SOC_IS_TRIUMPH2(unit)) { 7874 if (soc_mem_index_count(unit, EXT_IPV6_64_DEFIPm)) { 7875 bit_num = soc_mem_field_length(unit, EXT_IPV6_64_DEFIPm, VRF_LOf); 7876 } else { 7877 bit_num = soc_mem_field_length(unit, L3_IIFm, VRFf); 7878 } 7879 } else if (SOC_IS_TRIUMPH3(unit)) { 7880 bit_num = soc_mem_field_length(unit, L3_IIFm, VRFf); 7881 } else if (SOC_IS_VALKYRIE(unit)) { 7882 bit_num = 8; /* Hardcoded to 256 VRFs */ 7883 } else if (SOC_IS_ENDURO(unit)) { 7884 if ((dev_id == BCM56230_DEVICE_ID) || (dev_id == BCM56231_DEVICE_ID)) { 7885 bit_num = 5; /* Hardcoded to 32 VRFs for Dagger */ 7886 } else { 7887 bit_num = 7; /* Hardcoded to 128 VRFs */ 7888 } 7889 } else if (SOC_IS_APOLLO(unit) || SOC_IS_VALKYRIE2(unit)) { 7890 bit_num = soc_mem_field_length(unit, L3_IIFm, VRFf); 7891 } else if (SOC_IS_MONTEREY(unit)) { 7892 7893 *value = soc_mem_index_max(unit, VRFm); 7894 return SOC_E_NONE; 7895 } else if (SOC_IS_TD_TT(unit) || (SOC_IS_KATANAX(unit))) { 7896 if (dev_id == BCM56233_DEVICE_ID) { 7897 bit_num = 5; /* Hardcoded to 32 VRFs for Dagger2 */ 7898 } else { 7899 bit_num = soc_mem_field_length(unit, L3_IIFm, VRFf); 7900 } 7901 } else if (SOC_IS_GREYHOUND2(unit)) { 7902 if (soc_feature(unit, soc_feature_l3)) { 7903 bit_num = soc_mem_field_length(unit, L3_IIFm, VRF_IDf); 7904 } else { 7905 /* to force no VRF support if no L3 feature on some SKUs */ 7906 bit_num = 0; 7907 } 7908 } 7909 #endif /* BCM_TRIUMPH_SUPPORT */ 7910 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_RAPTOR_SUPPORT) || \ 7911 defined(BCM_SCORPION_SUPPORT) 7912 if (SOC_IS_FIREBOLT2(unit) || SOC_IS_RAVEN(unit) || 7913 SOC_IS_SC_CQ(unit)) { 7914 bit_num = soc_mem_field_length(unit, VLAN_TABm, VRF_IDf); 7915 } 7916 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_RAVEN_SUPPORT || BCM_SCORPION_SUPPORT */ 7917 *value = (( 1 << bit_num ) - 1); 7918 return (SOC_E_NONE); 7919 } 7920 7921 7922 /* 7923 * Function: 7924 * soc_max_supported_addr_class_get 7925 * Purpose: 7926 * Utility routine for reading maximum supported address 7927 * class for the device. 7928 * Parameters: 7929 * unit - (IN) Unit number. 7930 * value - (OUT) Max address class value. 7931 * Returns: 7932 * SOC_E_NONE 7933 */ 7934 STATIC int 7935 soc_max_supported_addr_class_get(int unit, uint16 *value) 7936 { 7937 int bit_num = 0; 7938 7939 if (NULL == value) { 7940 return (SOC_E_PARAM); 7941 } 7942 #ifdef BCM_SHADOW_SUPPORT 7943 if (SOC_IS_SHADOW(unit)) { 7944 /* fill in for SHADOW */ 7945 } else 7946 #endif /* BCM_SHADOW_SUPPORT */ 7947 #if defined(BCM_TRX_SUPPORT) 7948 if (SOC_IS_TRX(unit)) { 7949 if (soc_feature(unit, soc_feature_ism_memory)) { 7950 bit_num = soc_mem_field_length(unit, L2_ENTRY_1m, CLASS_IDf); 7951 } else { 7952 bit_num = soc_mem_field_length(unit, L2Xm, CLASS_IDf); 7953 } 7954 } else 7955 #endif /* BCM_TRX_SUPPORT */ 7956 #ifdef BCM_ESW_SUPPORT 7957 if (SOC_MEM_FIELD_VALID(unit, L2Xm, MAC_BLOCK_INDEXf)) { 7958 bit_num = soc_mem_field_length(unit, L2Xm, MAC_BLOCK_INDEXf); 7959 } 7960 #endif /* BCM_ESW_SUPPORT */ 7961 *value = (( 1 << bit_num ) - 1); 7962 7963 return (SOC_E_NONE); 7964 } 7965 7966 /* 7967 * Function: 7968 * soc_max_supported_overlaid_addr_class_get 7969 * Purpose: 7970 * Utility routine for reading maximum supported address 7971 * class with overlay for the device. 7972 * Parameters: 7973 * unit - (IN) Unit number. 7974 * value - (OUT) Max address class value. 7975 * Returns: 7976 * SOC_E_NONE 7977 */ 7978 STATIC int 7979 soc_max_supported_overlaid_addr_class_get(int unit, uint16 *value) 7980 { 7981 int bit_num = 0; 7982 7983 if (NULL == value) { 7984 return (SOC_E_PARAM); 7985 } 7986 7987 #if defined(BCM_TRIDENT2_SUPPORT) 7988 if (SOC_MEM_FIELD_VALID(unit, L2Xm, CLASS_IDf)) { 7989 bit_num = soc_mem_field_length(unit, L2Xm, CLASS_IDf); 7990 if (SOC_MEM_FIELD_VALID(unit, L2Xm, PRIf)) { 7991 bit_num += soc_mem_field_length(unit, L2Xm, PRIf); 7992 } 7993 } 7994 #endif /* BCM_TRX_SUPPORT */ 7995 7996 *value = (( 1 << bit_num ) - 1); 7997 7998 return (SOC_E_NONE); 7999 } 8000 8001 /* 8002 * Function: 8003 * soc_max_supported_extended_addr_class_get 8004 * Purpose: 8005 * Utility routine for reading maximum supported extended address 8006 * class for the device. 8007 * Parameters: 8008 * unit - (IN) Unit number. 8009 * value - (OUT) Max address class value. 8010 * Returns: 8011 * SOC_E_NONE 8012 */ 8013 STATIC int 8014 soc_max_supported_extended_addr_class_get(int unit, uint16 *value) 8015 { 8016 int bit_num = 0; 8017 8018 if (NULL == value) { 8019 return (SOC_E_PARAM); 8020 } 8021 if (SOC_MEM_FIELD_VALID(unit, L3_ENTRY_1m, CLASS_IDf)) { 8022 bit_num = soc_mem_field_length(unit, L3_ENTRY_1m, CLASS_IDf); 8023 } 8024 8025 *value = (( 1 << bit_num ) - 1); 8026 return (SOC_E_NONE); 8027 } 8028 8029 /* 8030 * Function: 8031 * soc_max_supported_intf_class_get 8032 * Purpose: 8033 * Utility routine for reading maximum supported interface 8034 * class for the device. 8035 * Parameters: 8036 * unit - (IN) Unit number. 8037 * value - (OUT) Maximum interface class value. 8038 * Returns: 8039 * SOC_E_NONE 8040 */ 8041 STATIC int 8042 soc_max_supported_intf_class_get(int unit, uint16 *value) 8043 { 8044 int bit_num = 0; 8045 8046 if (NULL == value) { 8047 return (SOC_E_PARAM); 8048 } 8049 8050 #if defined(BCM_TRIUMPH_SUPPORT) 8051 if (SOC_IS_TR_VL(unit)) { 8052 bit_num = soc_mem_field_length(unit, VLAN_TABm, VLAN_CLASS_IDf); 8053 } 8054 #endif /* BCM_TRIUMPH_SUPPORT */ 8055 #if defined(BCM_SCORPION_SUPPORT) 8056 if (SOC_IS_SC_CQ(unit)) { 8057 bit_num = soc_mem_field_length(unit, VLAN_TABm, CLASS_IDf); 8058 } 8059 #endif /* BCM_SCORPION_SUPPORT */ 8060 #if defined(BCM_FIREBOLT2_SUPPORT) 8061 if (SOC_IS_FIREBOLT2(unit)) { 8062 bit_num = soc_mem_field_length(unit, PORT_TABm, VFP_PORT_GROUP_IDf); 8063 } 8064 #endif /* BCM_FIREBOLT2_SUPPORT */ 8065 *value = (( 1 << bit_num ) - 1); 8066 return (SOC_E_NONE); 8067 } 8068 8069 8070 /* 8071 * Function: 8072 * soc_max_vrf_set 8073 * Purpose: 8074 * Utility routine for configuring max vrf value for the device. 8075 * Parameters: 8076 * unit - (IN) Unit number. 8077 * value - (IN) Max vrf value. 8078 * NOTE: Value must be equal or less than maximum supported vrf id, 8079 * otherwise maximum supported vrf id is used. 8080 * Value must be power of two - 1, otherwise routine calculates closest 8081 * power of 2 - 1 value less than requested one. 8082 * Returns: 8083 BCM_E_NONE 8084 */ 8085 int 8086 soc_max_vrf_set(int unit, int value) 8087 { 8088 uint16 max_supported; /* Maximum supported vrf id. */ 8089 uint16 max_vrf_id; /* Adjusted max vrf value. */ 8090 uint8 bit_number; /* Number of bits in configured value. */ 8091 8092 8093 SOC_IF_ERROR_RETURN(soc_max_supported_vrf_get(unit, &max_supported)); 8094 8095 if (value > max_supported) { 8096 return (SOC_E_PARAM); 8097 } 8098 8099 /* Find number of bits required to cover requested value. */ 8100 for (bit_number = 0; bit_number < 16; bit_number++) { 8101 max_vrf_id = ((1 << bit_number) - 1); 8102 if (value == max_vrf_id) { 8103 break; 8104 } 8105 } 8106 8107 if (max_vrf_id != value) { 8108 return (SOC_E_PARAM); 8109 } 8110 8111 SOC_VRF_MAX_SET(unit, max_vrf_id); 8112 return (SOC_E_NONE); 8113 } 8114 8115 /* 8116 * Function: 8117 * soc_xport_type_verify 8118 * Purpose: 8119 * Check all 10G ports to see if the encapsulation is changed from 8120 * the configured selection. Update the SOC port data structures to 8121 * match the HW encapsulation selection. 8122 * Parameters: 8123 * unit - XGS unit #. 8124 * Returns: 8125 * SOC_E_XXX 8126 * Notes: 8127 * WARM_BOOT mode only 8128 */ 8129 STATIC int 8130 soc_xport_type_verify(int unit) 8131 { 8132 soc_pbmp_t pbmp_10g_plus; 8133 soc_port_t port; 8134 int mode; 8135 mac_driver_t *macdp; 8136 #ifdef BCM_GREYHOUND_SUPPORT 8137 uint32 hg2_mode = 0; 8138 #endif 8139 #ifdef BCM_HURRICANE3_SUPPORT 8140 uint32 reg_val = 0; 8141 #endif /* BCM_HURRICANE3_SUPPORT */ 8142 8143 if (!soc_feature(unit, soc_feature_xport_convertible)) { 8144 /* Nothing to do */ 8145 return SOC_E_NONE; 8146 } 8147 8148 if (SOC_USE_PORTCTRL(unit)) { 8149 /* For portmod devices, hg2 bitmap is recovered 8150 * in soc_esw_portctr_init */ 8151 return SOC_E_NONE; 8152 } 8153 8154 SOC_PBMP_ASSIGN(pbmp_10g_plus, PBMP_XE_ALL(unit)); 8155 SOC_PBMP_OR(pbmp_10g_plus, PBMP_HG_ALL(unit)); 8156 SOC_PBMP_OR(pbmp_10g_plus, PBMP_CE_ALL(unit)); 8157 8158 SOC_PBMP_ITER(pbmp_10g_plus, port) { 8159 SOC_IF_ERROR_RETURN(soc_mac_probe(unit, port, &macdp)); 8160 8161 { 8162 SOC_IF_ERROR_RETURN(MAC_ENCAP_GET(macdp, unit, port, &mode)); 8163 } 8164 8165 #ifdef BCM_GREYHOUND_SUPPORT 8166 if (SOC_IS_GREYHOUND(unit)){ 8167 /* Need more check for MAC mode at IEEE encap mode if the port is 8168 * actually at HG2-LITE encap mode. 8169 */ 8170 if (mode == SOC_ENCAP_IEEE){ 8171 SOC_IF_ERROR_RETURN(soc_greyhound_pgw_encap_field_get(unit, 8172 port, HIGIG2_MODEf, &hg2_mode)); 8173 mode = (hg2_mode) ? SOC_ENCAP_HIGIG2_LITE : mode; 8174 } 8175 8176 if ((IS_XE_PORT(unit, port) && (mode != SOC_ENCAP_IEEE)) || 8177 (IS_HG_PORT(unit, port) && (mode == SOC_ENCAP_IEEE))) { 8178 soc_xport_type_mode_update(unit, port, mode); 8179 } 8180 if (mode == SOC_ENCAP_HIGIG2 || mode == SOC_ENCAP_HIGIG2_LITE) { 8181 SOC_HG2_ENABLED_PORT_ADD(unit, port); 8182 } 8183 } else 8184 #endif /* GREYHOUND */ 8185 #ifdef BCM_HURRICANE3_SUPPORT 8186 if (SOC_IS_HURRICANE3(unit) || SOC_IS_GREYHOUND2(unit)){ 8187 /* Need more check for MAC mode at IEEE encap mode if the port is 8188 * actually at HG2-LITE encap mode. 8189 */ 8190 if (mode == SOC_ENCAP_IEEE){ 8191 if (IS_XE_PORT(unit, port)) { 8192 if (IS_XL_PORT(unit, port)) { 8193 SOC_IF_ERROR_RETURN( 8194 READ_PGW_XL_CONFIGr(unit, port, ®_val)); 8195 hg2_mode = soc_reg_field_get(unit, 8196 PGW_XL_CONFIGr, reg_val, HIGIG2_MODEf); 8197 } else if (IS_CL_PORT(unit, port)) { 8198 SOC_IF_ERROR_RETURN( 8199 READ_PGW_CL_CONFIGr(unit, port, ®_val)); 8200 hg2_mode = soc_reg_field_get(unit, 8201 PGW_CL_CONFIGr, reg_val, HIGIG2_MODEf); 8202 } else { 8203 /* This should not happen */ 8204 return SOC_E_INTERNAL; 8205 } 8206 mode = (hg2_mode) ? SOC_ENCAP_HIGIG2_LITE : mode; 8207 } 8208 } 8209 8210 if ((IS_XE_PORT(unit, port) && (mode != SOC_ENCAP_IEEE)) || 8211 (IS_HG_PORT(unit, port) && (mode == SOC_ENCAP_IEEE))) { 8212 soc_xport_type_mode_update(unit, port, mode); 8213 } 8214 if (mode == SOC_ENCAP_HIGIG2 || mode == SOC_ENCAP_HIGIG2_LITE) { 8215 SOC_HG2_ENABLED_PORT_ADD(unit, port); 8216 } 8217 } else 8218 #endif /* HURRICANE3 */ 8219 #ifdef BCM_SABER2_SUPPORT 8220 if (SOC_IS_SABER2(unit)) { 8221 /* Need more check for MAC mode at IEEE encap mode if the port is 8222 * actually at HG2-LITE encap mode. 8223 */ 8224 uint32 hg2_mode = 0; 8225 uint32 reg_val = 0; 8226 if (mode == SOC_ENCAP_IEEE){ 8227 if (SOC_REG_PORT_VALID(unit, XLPORT_CONFIGr, port)) { 8228 READ_XLPORT_CONFIGr(unit, port, ®_val); 8229 hg2_mode = soc_reg_field_get(unit, 8230 XLPORT_CONFIGr, reg_val, HIGIG2_MODEf); 8231 mode = (hg2_mode) ? SOC_ENCAP_HIGIG2_LITE : mode; 8232 } 8233 } 8234 if ((IS_XE_PORT(unit, port) && (mode != SOC_ENCAP_IEEE)) || 8235 (IS_HG_PORT(unit, port) && ((mode == SOC_ENCAP_IEEE) || 8236 (mode == SOC_ENCAP_HIGIG2_LITE)))) { 8237 soc_sb2_xport_type_update(unit, port, mode); 8238 } 8239 if (mode == SOC_ENCAP_HIGIG2 || mode == SOC_ENCAP_HIGIG2_LITE) { 8240 if (IS_HG_PORT(unit, port)) { 8241 SOC_HG2_ENABLED_PORT_ADD(unit, port); 8242 } else { 8243 /* This should not happen */ 8244 return SOC_E_INTERNAL; 8245 } 8246 } 8247 } else 8248 #endif /* SABER2 */ 8249 #ifdef BCM_KATANA2_SUPPORT 8250 if (SOC_IS_KATANA2(unit) && !SOC_IS_SABER2(unit)) { 8251 /* Need more check for MAC mode at IEEE encap mode if the port is 8252 * actually at HG2-LITE encap mode. 8253 */ 8254 uint32 hg2_mode = 0; 8255 uint32 reg_val = 0; 8256 if (mode == SOC_ENCAP_IEEE) { 8257 if (SOC_REG_PORT_VALID(unit, XPORT_CONFIGr, port)) { 8258 SOC_IF_ERROR_RETURN( 8259 READ_XPORT_CONFIGr(unit, port, ®_val)); 8260 hg2_mode = soc_reg_field_get(unit, 8261 XPORT_CONFIGr, reg_val, HIGIG2_MODEf); 8262 mode = (hg2_mode) ? SOC_ENCAP_HIGIG2_LITE : mode; 8263 } 8264 } 8265 8266 if ((IS_XE_PORT(unit, port) && (mode != SOC_ENCAP_IEEE)) || 8267 (IS_HG_PORT(unit, port) && ((mode == SOC_ENCAP_IEEE) || 8268 (mode == SOC_ENCAP_HIGIG2_LITE)))) { 8269 soc_kt2_xport_type_update(unit, port, mode); 8270 } 8271 if ((mode == SOC_ENCAP_HIGIG2) || (mode == SOC_ENCAP_HIGIG2_LITE)) { 8272 if (IS_HG_PORT(unit, port)) { 8273 SOC_HG2_ENABLED_PORT_ADD(unit, port); 8274 } else { 8275 /* This should not happen */ 8276 return SOC_E_INTERNAL; 8277 } 8278 } 8279 } else 8280 #endif /* KATANA2 */ 8281 { 8282 if ((IS_XE_PORT(unit, port) || IS_CE_PORT(unit, port)) 8283 && (mode != SOC_ENCAP_IEEE)) { 8284 soc_xport_type_update(unit, port, TRUE); 8285 } else if (IS_HG_PORT(unit, port) && (mode == SOC_ENCAP_IEEE)) { 8286 soc_xport_type_update(unit, port, FALSE); 8287 } 8288 8289 if (mode == SOC_ENCAP_HIGIG2) { 8290 if (IS_HG_PORT(unit, port)) { 8291 SOC_HG2_ENABLED_PORT_ADD(unit, port); 8292 } else { 8293 /* This should not happen */ 8294 return SOC_E_INTERNAL; 8295 } 8296 } 8297 } 8298 } 8299 8300 return SOC_E_NONE; 8301 } 8302 8303 #if defined(BCM_RAVEN_SUPPORT) || defined (BCM_TRIUMPH2_SUPPORT) 8304 /* 8305 * Function: 8306 * soc_stport_type_verify 8307 * Purpose: 8308 * Check all stackable ports to see if the encapsulation is 8309 * changed from the configured selection. Update the SOC port 8310 * data structures to match the HW encapsulation selection. 8311 * Parameters: 8312 * unit - XGS unit #. 8313 * Returns: 8314 * SOC_E_XXX 8315 * Notes: 8316 * WARM_BOOT mode only 8317 */ 8318 STATIC int 8319 soc_stport_type_verify(int unit) 8320 { 8321 port_tab_entry_t ptab; 8322 soc_port_t port; 8323 soc_info_t *si = &SOC_INFO(unit); 8324 soc_reg_t ehg_rx_reg; 8325 soc_field_t port_type; 8326 uint32 ehg_rx_ctrl = 0; 8327 int to_higig = FALSE; 8328 soc_mem_t mem; 8329 ing_physical_port_table_entry_t ptab_entry; 8330 ing_device_port_entry_t ptab_dev; 8331 void *pentry; 8332 int port_type_value = 0; 8333 8334 if (SOC_USE_PORTCTRL(unit)) { 8335 /* For portmod devices, this is covered in soc_xport_type_update */ 8336 return SOC_E_NONE; 8337 } 8338 8339 /* Select correct port table field for the Higig2 configuration. */ 8340 port_type = (SOC_IS_ENDURO(unit) || SOC_IS_TRIUMPH2(unit) || 8341 SOC_IS_APOLLO(unit) || SOC_IS_VALKYRIE2(unit) || 8342 SOC_IS_HURRICANE(unit) || SOC_IS_HURRICANE2(unit) || 8343 SOC_IS_TD_TT(unit) || 8344 SOC_IS_KATANAX(unit) || SOC_IS_TRIUMPH3(unit) || 8345 SOC_IS_HURRICANE3(unit) || SOC_IS_GREYHOUND(unit) || 8346 SOC_IS_GREYHOUND2(unit)) ? 8347 PORT_TYPEf : HIGIG_PACKETf; 8348 8349 ehg_rx_reg = 8350 SOC_IS_TRIUMPH3(unit) ? PORT_EHG_RX_CONTROLr : EHG_RX_CONTROLr; 8351 8352 PBMP_PORT_ITER(unit, port) { 8353 if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit) || 8354 SOC_IS_GREYHOUND2(unit)) { 8355 if (IS_XE_PORT(unit, port) || IS_CE_PORT(unit, port) || 8356 IS_HG_PORT(unit, port)) { 8357 /* these cases were handled in soc_xport_type_verify */ 8358 continue; 8359 } 8360 } 8361 /* Handle embedded Higig cases */ 8362 if (SOC_REG_IS_VALID(unit, ehg_rx_reg)) { 8363 SOC_IF_ERROR_RETURN 8364 (soc_reg32_get(unit, ehg_rx_reg, port, 0, &ehg_rx_ctrl)); 8365 8366 if (2 == soc_reg_field_get(unit, ehg_rx_reg, 8367 ehg_rx_ctrl, MODEf)) { 8368 /* Raptor-style stacking -- HIGIG2_LITE */ 8369 if (IS_HG_PORT(unit, port)) { 8370 SOC_HG2_ENABLED_PORT_REMOVE(unit, port); 8371 } else { 8372 SOC_PBMP_PORT_ADD(si->hl.bitmap, port); 8373 } 8374 } 8375 8376 if (0 != soc_reg_field_get(unit, ehg_rx_reg, 8377 ehg_rx_ctrl, MODEf)) { 8378 /* Embedded Higig */ 8379 SOC_PBMP_PORT_ADD(si->st.bitmap, port); 8380 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, port); 8381 continue; 8382 } 8383 /* Else, fall through to below */ 8384 } 8385 if (SOC_IS_KATANA2(unit)) { 8386 mem = ING_PHYSICAL_PORT_TABLEm; 8387 sal_memset(&ptab_entry, 0, sizeof(ptab_entry)); 8388 pentry = (void *)&ptab_entry; 8389 } else if (SOC_IS_TRIDENT3X(unit)) { 8390 mem = ING_DEVICE_PORTm; 8391 sal_memset(&ptab_dev, 0, sizeof(ptab_dev)); 8392 pentry = (void *)&ptab_dev; 8393 } else { 8394 mem = PORT_TABm; 8395 sal_memset(&ptab, 0, sizeof(ptab)); 8396 pentry = (void *)&ptab; 8397 } 8398 8399 if (!IS_HG_PORT(unit, port)) { 8400 SOC_IF_ERROR_RETURN(soc_mem_read(unit, mem, 8401 MEM_BLOCK_ANY, port, pentry)); 8402 port_type_value = soc_mem_field32_get(unit, mem, pentry, port_type); 8403 to_higig = ((0 != port_type_value) && 8404 (_BCM_COE_PORT_TYPE_CASCADED != port_type_value)); 8405 8406 /* ST port settings */ 8407 if (to_higig) { 8408 SOC_PBMP_PORT_ADD(si->st.bitmap, port); 8409 SOC_PBMP_PORT_ADD(si->hl.bitmap, port); 8410 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, port); 8411 if (!IS_XE_PORT(unit, port)) { 8412 SOC_HG2_ENABLED_PORT_ADD(unit, port); 8413 } 8414 } else { 8415 SOC_PBMP_PORT_REMOVE(si->st.bitmap, port); 8416 SOC_PBMP_PORT_REMOVE(si->hl.bitmap, port); 8417 SOC_PBMP_PORT_ADD(si->ether.bitmap, port); 8418 if (!IS_XE_PORT(unit, port)) { 8419 SOC_HG2_ENABLED_PORT_REMOVE(unit, port); 8420 } 8421 } 8422 } 8423 } 8424 soc_dport_map_update(unit); 8425 return SOC_E_NONE; 8426 } 8427 #endif /* defined(BCM_RAVEN_SUPPORT) || defined (BCM_TRIUMPH2_SUPPORT) */ 8428 8429 /* 8430 * Function: 8431 * soc_port_type_verify 8432 * Purpose: 8433 * Check all ports to see if the encapsulation is changed from 8434 * the configured selection. Update the SOC port data structures to 8435 * match the HW encapsulation selection. 8436 * Parameters: 8437 * unit - XGS unit #. 8438 * Returns: 8439 * SOC_E_XXX 8440 * Notes: 8441 * WARM_BOOT mode only 8442 */ 8443 int 8444 soc_port_type_verify(int unit) 8445 { 8446 SOC_IF_ERROR_RETURN(soc_xport_type_verify(unit)); 8447 8448 #if defined(BCM_RAVEN_SUPPORT) || defined (BCM_TRIUMPH2_SUPPORT) 8449 /* Raven HG or embedded HG versions here */ 8450 SOC_IF_ERROR_RETURN(soc_stport_type_verify(unit)); 8451 #endif /* defined(BCM_RAVEN_SUPPORT) || defined (BCM_TRIUMPH2_SUPPORT) */ 8452 8453 return SOC_E_NONE; 8454 } 8455 8456 #ifdef BCM_CMICM_SUPPORT 8457 int 8458 cmicm_pcie_deemphasis_set(int unit, uint16 phy_addr) { 8459 uint16 phy_reg_val; 8460 uint32 cmic_reg_val; 8461 8462 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8463 (BSL_META_U(unit, 8464 "Changing the CMICm PCIe SerDes deemphasis on unit %d\n"), unit)); 8465 8466 /* Change the transmitter setting */ 8467 SOC_IF_ERROR_RETURN(soc_miim_write(unit, phy_addr, 0x1f, 0x8610)); 8468 SOC_IF_ERROR_RETURN(soc_miim_read(unit, phy_addr, 0x17, &phy_reg_val)); 8469 phy_reg_val = (phy_reg_val & 0xf0ff) | 0x700; 8470 SOC_IF_ERROR_RETURN(soc_miim_write(unit, phy_addr, 0x17, phy_reg_val)); 8471 8472 /* Force the PCIe link to retrain */ 8473 cmic_reg_val = 0x1004; 8474 /* coverity[result_independent_of_operands] */ 8475 SOC_IF_ERROR_RETURN(WRITE_CMIC_PCIE_CFG_ADDRESSr(unit, cmic_reg_val)); 8476 /* coverity[result_independent_of_operands] */ 8477 SOC_IF_ERROR_RETURN(READ_CMIC_PCIE_CFG_READ_DATAr(unit, &cmic_reg_val)); 8478 cmic_reg_val &= ~0x4000; 8479 /* coverity[result_independent_of_operands] */ 8480 SOC_IF_ERROR_RETURN(WRITE_CMIC_PCIE_CFG_WRITE_DATAr(unit, cmic_reg_val)); 8481 cmic_reg_val |= 0x4000; 8482 /* coverity[result_independent_of_operands] */ 8483 SOC_IF_ERROR_RETURN(WRITE_CMIC_PCIE_CFG_WRITE_DATAr(unit, cmic_reg_val)); 8484 cmic_reg_val &= ~0x4000; 8485 /* coverity[result_independent_of_operands] */ 8486 SOC_IF_ERROR_RETURN(WRITE_CMIC_PCIE_CFG_WRITE_DATAr(unit, cmic_reg_val)); 8487 8488 /* Wait a short while for the retraining to complete */ 8489 sal_usleep(1000); 8490 8491 return SOC_E_NONE; 8492 } 8493 #endif /* BCM_CMICM_SUPPORT */ 8494 8495 int cmic_pcie_cdr_bw_adj(int unit, uint16 phy_addr) { 8496 int miim_intr_enb; 8497 8498 /* Interrupts may not be working yet */ 8499 miim_intr_enb = SOC_CONTROL(unit)->miimIntrEnb; 8500 SOC_CONTROL(unit)->miimIntrEnb = 0; 8501 8502 SOC_IF_ERROR_RETURN(soc_miim_write(unit, phy_addr, 0x1f, 0x8630)); 8503 SOC_IF_ERROR_RETURN(soc_miim_write(unit, phy_addr, 0x13, 0x190)); 8504 SOC_IF_ERROR_RETURN(soc_miim_write(unit, phy_addr, 0x19, 0x191)); 8505 8506 SOC_CONTROL(unit)->miimIntrEnb = miim_intr_enb; 8507 8508 return SOC_E_NONE; 8509 } 8510 8511 int 8512 cmice_pcie_deemphasis_set(int unit, uint16 phy_addr) { 8513 uint16 phy_reg_val; 8514 8515 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8516 (BSL_META_U(unit, 8517 "Changing the CMICe PCIe SerDes deemphasis on unit %d\n"), unit)); 8518 8519 /* Change the transmitter setting */ 8520 SOC_IF_ERROR_RETURN(soc_miim_write(unit, phy_addr, 0x1f, 0x8610)); 8521 SOC_IF_ERROR_RETURN(soc_miim_read(unit, phy_addr, 0x17, &phy_reg_val)); 8522 phy_reg_val = (phy_reg_val & 0xf0ff) | 0x700; 8523 SOC_IF_ERROR_RETURN(soc_miim_write(unit, phy_addr, 0x17, phy_reg_val)); 8524 8525 /* Wait a short while */ 8526 sal_usleep(1000); 8527 8528 return SOC_E_NONE; 8529 } 8530 8531 #ifdef BCM_IPROC_SUPPORT 8532 int iproc_pcie_cdr_bw_adj(int unit, uint16 phy_addr) { 8533 uint32 cmic_reg_val; 8534 8535 /* Enable the iProc internal MDIO interface */ 8536 cmic_reg_val = 0; 8537 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_CONTROLr, &cmic_reg_val, 8538 MDCDIVf, 0x7f); 8539 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_CONTROLr(unit, 8540 cmic_reg_val)); 8541 sal_usleep(10000); 8542 8543 /* Set Block */ 8544 cmic_reg_val = 0; 8545 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8546 &cmic_reg_val, SBf, 0x1); 8547 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8548 &cmic_reg_val, TAf, 0x2); 8549 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8550 &cmic_reg_val, OPf, 0x1); 8551 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8552 &cmic_reg_val, PAf, phy_addr); 8553 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8554 &cmic_reg_val, RAf, 0x1f); 8555 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8556 &cmic_reg_val, DATAf, 0x8630); 8557 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr(unit, 8558 cmic_reg_val)); 8559 sal_usleep(10000); 8560 8561 /* Write reg 0x13 */ 8562 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8563 &cmic_reg_val, RAf, 0x13); 8564 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8565 &cmic_reg_val, DATAf, 0x190); 8566 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr(unit, 8567 cmic_reg_val)); 8568 sal_usleep(10000); 8569 8570 /* Write reg 0x19 */ 8571 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8572 &cmic_reg_val, RAf, 0x19); 8573 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8574 &cmic_reg_val, DATAf, 0x191); 8575 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr(unit, 8576 cmic_reg_val)); 8577 sal_usleep(10000); 8578 8579 return SOC_E_NONE; 8580 } 8581 8582 int 8583 iproc_pcie_deemphasis_set(int unit, uint16 phy_addr) { 8584 uint16 phy_reg_val; 8585 uint32 cmic_reg_val; 8586 8587 #ifdef BCM_HURRICANE2_SUPPORT 8588 /* DeEmphasis not needed for Hurricane2 */ 8589 if (SOC_IS_HURRICANE2(unit)) { 8590 return SOC_E_NONE; 8591 } 8592 #endif 8593 8594 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8595 (BSL_META_U(unit, 8596 "Changing the iProc PCIe SerDes deemphasis on unit %d\n"), unit)); 8597 8598 /* Enable the iProc internal MDIO interface */ 8599 cmic_reg_val = 0; 8600 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_CONTROLr, &cmic_reg_val, 8601 MDCDIVf, 0x7f); 8602 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_CONTROLr(unit, 8603 cmic_reg_val)); 8604 sal_usleep(10000); 8605 8606 /* Change the transmitter setting */ 8607 cmic_reg_val = 0; 8608 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8609 &cmic_reg_val, SBf, 0x1); 8610 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8611 &cmic_reg_val, TAf, 0x2); 8612 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8613 &cmic_reg_val, OPf, 0x1); 8614 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8615 &cmic_reg_val, PAf, phy_addr); 8616 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8617 &cmic_reg_val, RAf, 0x1f); 8618 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8619 &cmic_reg_val, DATAf, 0x8610); 8620 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr(unit, 8621 cmic_reg_val)); 8622 sal_usleep(10000); 8623 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8624 &cmic_reg_val, OPf, 0x2); 8625 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8626 &cmic_reg_val, RAf, 0x17); 8627 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr(unit, 8628 cmic_reg_val)); 8629 sal_usleep(10000); 8630 SOC_IF_ERROR_RETURN(READ_CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr(unit, 8631 &cmic_reg_val)); 8632 sal_usleep(10000); 8633 phy_reg_val = soc_reg_field_get(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8634 cmic_reg_val, DATAf); 8635 phy_reg_val = (phy_reg_val & 0xf0ff) | 0x700; 8636 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8637 &cmic_reg_val, SBf, 0x1); 8638 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8639 &cmic_reg_val, TAf, 0x2); 8640 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8641 &cmic_reg_val, OPf, 0x1); 8642 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8643 &cmic_reg_val, PAf, phy_addr); 8644 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8645 &cmic_reg_val, RAf, 0x17); 8646 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8647 &cmic_reg_val, DATAf, phy_reg_val); 8648 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr(unit, 8649 cmic_reg_val)); 8650 8651 /* Force the PCIe link to retrain */ 8652 if (soc_cm_get_bus_type(unit) & SOC_DEV_BUS_ALT) { 8653 /* PCI-1 */ 8654 cmic_reg_val = 0; 8655 soc_reg_field_set(unit, PAXB_1_CONFIG_IND_ADDRr, &cmic_reg_val, 8656 PROTOCOL_LAYERf, 0x2); 8657 soc_reg_field_set(unit, PAXB_1_CONFIG_IND_ADDRr, &cmic_reg_val, 8658 ADDRESSf, 0x4); 8659 SOC_IF_ERROR_RETURN(WRITE_PAXB_1_CONFIG_IND_ADDRr(unit, cmic_reg_val)); 8660 SOC_IF_ERROR_RETURN(READ_PAXB_1_CONFIG_IND_DATAr(unit, &cmic_reg_val)); 8661 cmic_reg_val &= ~0x4000; 8662 SOC_IF_ERROR_RETURN(WRITE_PAXB_1_CONFIG_IND_ADDRr(unit, cmic_reg_val)); 8663 cmic_reg_val |= 0x4000; 8664 SOC_IF_ERROR_RETURN(WRITE_PAXB_1_CONFIG_IND_ADDRr(unit, cmic_reg_val)); 8665 cmic_reg_val &= ~0x4000; 8666 SOC_IF_ERROR_RETURN(WRITE_PAXB_1_CONFIG_IND_ADDRr(unit, cmic_reg_val)); 8667 } else { 8668 /* PCI-0 */ 8669 cmic_reg_val = 0; 8670 soc_reg_field_set(unit, PAXB_0_CONFIG_IND_ADDRr, &cmic_reg_val, 8671 PROTOCOL_LAYERf, 0x2); 8672 soc_reg_field_set(unit, PAXB_0_CONFIG_IND_ADDRr, &cmic_reg_val, 8673 ADDRESSf, 0x4); 8674 SOC_IF_ERROR_RETURN(WRITE_PAXB_0_CONFIG_IND_ADDRr(unit, cmic_reg_val)); 8675 SOC_IF_ERROR_RETURN(READ_PAXB_0_CONFIG_IND_DATAr(unit, &cmic_reg_val)); 8676 cmic_reg_val &= ~0x4000; 8677 SOC_IF_ERROR_RETURN(WRITE_PAXB_0_CONFIG_IND_ADDRr(unit, cmic_reg_val)); 8678 cmic_reg_val |= 0x4000; 8679 SOC_IF_ERROR_RETURN(WRITE_PAXB_0_CONFIG_IND_ADDRr(unit, cmic_reg_val)); 8680 cmic_reg_val &= ~0x4000; 8681 SOC_IF_ERROR_RETURN(WRITE_PAXB_0_CONFIG_IND_ADDRr(unit, cmic_reg_val)); 8682 } 8683 /* Wait a short while for the retraining to complete */ 8684 sal_usleep(1000); 8685 8686 return SOC_E_NONE; 8687 } 8688 #endif /* BCM_IPROC_SUPPORT */ 8689 8690 #if defined(BCM_HELIX4_SUPPORT) 8691 /* 8692 * Function: 8693 * iproc_pcie_common_clk_set 8694 * Purpose: 8695 * Disable clock compensation events when Helix4 is operated in EHOST mode, 8696 * PCIe EP, x2 mode with common clock. 8697 * Assumes: BUS type is PCI, Device is Helix4. 8698 * Parameters: 8699 * unit - XGS unit 8700 * phy_addr - MDIO Address of the PCIE Phy 8701 * Returns: 8702 * SOC_E_XXX 8703 */ 8704 int iproc_pcie_common_clk_set(int unit, uint16 phy_addr) { 8705 static uint16 hx4_pcic_link_stat_reg = 0xbc; 8706 static uint32 hx4_pcic_link_width_mask = 0x03f00000; 8707 uint32 cmic_reg_val; 8708 8709 if ((soc_pci_conf_read(unit, hx4_pcic_link_stat_reg) & 8710 hx4_pcic_link_width_mask) < 0x00200000) { 8711 /* Helix4 is using a x1 link width */ 8712 return SOC_E_NONE; 8713 } 8714 8715 /* All conditions are met. Apply the change */ 8716 8717 /* Enable the iProc internal MDIO interface */ 8718 cmic_reg_val = 0; 8719 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_CONTROLr, &cmic_reg_val, 8720 MDCDIVf, 0x7f); 8721 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_CONTROLr(unit, 8722 cmic_reg_val)); 8723 sal_usleep(10000); 8724 8725 /* Set Block to 0x8630 */ 8726 cmic_reg_val = 0; 8727 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8728 &cmic_reg_val, SBf, 0x1); 8729 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8730 &cmic_reg_val, TAf, 0x2); 8731 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8732 &cmic_reg_val, OPf, 0x1); 8733 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8734 &cmic_reg_val, PAf, phy_addr); 8735 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8736 &cmic_reg_val, RAf, 0x1f); 8737 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8738 &cmic_reg_val, DATAf, 0x8630); 8739 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr(unit, 8740 cmic_reg_val)); 8741 sal_usleep(10000); 8742 8743 /* Write reg 0x1e to disable clock compensation events */ 8744 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8745 &cmic_reg_val, RAf, 0x1e); 8746 soc_reg_field_set(unit, CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr, 8747 &cmic_reg_val, DATAf, 0x0801); 8748 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATAr(unit, 8749 cmic_reg_val)); 8750 sal_usleep(10000); 8751 8752 return SOC_E_NONE; 8753 } 8754 #endif 8755 8756 8757 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) 8758 STATIC int 8759 soc_pcie_host_intf_init(int unit) 8760 { 8761 uint32 rval, val; 8762 if (soc_cm_get_bus_type(unit) & SOC_PCI_DEV_TYPE) { 8763 if (soc_feature(unit, soc_feature_cmicm)) { 8764 /* Set the timeout for bus-mastered DMA transactions */ 8765 if (SOC_REG_IS_VALID(unit, CMIC_PCIE_USERIF_TIMEOUTr) && 8766 SOC_REG_FIELD_VALID(unit, CMIC_PCIE_USERIF_TIMEOUTr, TIMEOUTf)) { 8767 val = soc_property_get(unit, spn_PCIE_HOST_INTF_TIMEOUT_USEC, 8768 50000000); 8769 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8770 (BSL_META_U(unit, 8771 "HOST_INTF_TIMEOUT_USEC = %u\n"), val)); 8772 SOC_IF_ERROR_RETURN(READ_CMIC_PCIE_USERIF_TIMEOUTr(unit, &rval)); 8773 soc_reg_field_set(unit, CMIC_PCIE_USERIF_TIMEOUTr, &rval, TIMEOUTf, 8774 val); 8775 /* coverity[result_independent_of_operands] */ 8776 SOC_IF_ERROR_RETURN(WRITE_CMIC_PCIE_USERIF_TIMEOUTr(unit, rval)); 8777 } 8778 if (SOC_REG_IS_VALID(unit, CMIC_PCIE_USERIF_PURGE_CONTROLr) && 8779 SOC_REG_FIELD_VALID(unit, CMIC_PCIE_USERIF_PURGE_CONTROLr, 8780 ENABLE_PURGE_IF_USERIF_TIMESOUTf)) { 8781 val = soc_property_get(unit, 8782 spn_PCIE_HOST_INTF_TIMEOUT_PURGE_ENABLE, 1); 8783 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8784 (BSL_META_U(unit, 8785 "HOST_INTF_TIMEOUT_PURGE_ENABLE = %u\n"), val)); 8786 SOC_IF_ERROR_RETURN( 8787 READ_CMIC_PCIE_USERIF_PURGE_CONTROLr(unit, &rval)); 8788 soc_reg_field_set(unit, CMIC_PCIE_USERIF_PURGE_CONTROLr, &rval, 8789 ENABLE_PURGE_IF_USERIF_TIMESOUTf, val); 8790 soc_reg_field_set(unit, CMIC_PCIE_USERIF_PURGE_CONTROLr, &rval, 8791 ENABLE_PURGE_IF_USERIF_RESETf, 1); 8792 soc_reg_field_set(unit, CMIC_PCIE_USERIF_PURGE_CONTROLr, &rval, 8793 ENABLE_PIO_PURGE_IF_USERIF_RESETf, 1); 8794 /* coverity[result_independent_of_operands] */ 8795 SOC_IF_ERROR_RETURN( 8796 WRITE_CMIC_PCIE_USERIF_PURGE_CONTROLr(unit, rval)); 8797 } 8798 } 8799 #ifdef BCM_CMICX_SUPPORT 8800 else if (soc_feature(unit, soc_feature_cmicx)) { 8801 /* Enable Hot Swap manager to handle CPU hot swap or Warmboot case */ 8802 if (SOC_REG_IS_VALID(unit, PAXB_0_PAXB_HOTSWAP_CTRLr) && 8803 SOC_REG_FIELD_VALID(unit, PAXB_0_PAXB_HOTSWAP_CTRLr, ENABLEf)) { 8804 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_HOTSWAP_CTRLr(unit, &rval)); 8805 soc_reg_field_set(unit, PAXB_0_PAXB_HOTSWAP_CTRLr, &rval, ENABLEf, 1); 8806 SOC_IF_ERROR_RETURN( 8807 WRITE_PAXB_0_PAXB_HOTSWAP_CTRLr(unit, rval)); 8808 } 8809 /* Disable iProc reset on PCie link down event */ 8810 SOC_IF_ERROR_RETURN 8811 (WRITE_PAXB_0_RESET_ENABLE_IN_PCIE_LINK_DOWNr(unit, 0x0)); 8812 } 8813 #endif 8814 } 8815 return SOC_E_NONE; 8816 } 8817 #endif 8818 8819 8820 static int 8821 soc_pci_hotswap_recover(int unit) 8822 { 8823 int rv = SOC_E_NONE; 8824 8825 #ifdef BCM_CMICX_SUPPORT 8826 int hot_swap_usec = 100; 8827 uint32 hot_swap_cause = 0; 8828 uint32 rval = 0; 8829 uint32 int_en; 8830 8831 if (soc_feature(unit, soc_feature_cmicx) && 8832 (soc_cm_get_bus_type(unit) & SOC_PCI_DEV_TYPE)) { 8833 /* Suggested default time out is 100 usec for FSM_STATE to be DUMMYRESP or IDLE */ 8834 hot_swap_usec = soc_property_get(unit, spn_PCIE_HOT_SWAP_TIMEOUT_USEC, 8835 100); 8836 LOG_INFO(BSL_LS_SOC_COMMON, 8837 (BSL_META_U(unit, 8838 "HOT_SWAP_TIMEOUT_USEC = %d\n"), hot_swap_usec)); 8839 8840 if (SOC_REG_IS_VALID(unit, PAXB_0_PAXB_HOTSWAP_STATr)) { 8841 int fsm_state; 8842 soc_timeout_t to; 8843 sal_usecs_t stime, etime; 8844 soc_timeout_init(&to, hot_swap_usec, 0); 8845 8846 /* READ HOTSWAP_CAUSE field to determine if hot swap event has happened */ 8847 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_HOTSWAP_STATr(unit, &rval)); 8848 hot_swap_cause = soc_reg_field_get(unit, PAXB_0_PAXB_HOTSWAP_STATr, 8849 rval, HOTSWAP_CAUSEf); 8850 fsm_state = soc_reg_field_get(unit, PAXB_0_PAXB_HOTSWAP_STATr, 8851 rval, FSM_STATEf); 8852 8853 /* Hot Swap status before Recovery */ 8854 LOG_INFO(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8855 "Hot Swap status before Recovery = 0x%x\n"), 8856 rval)); 8857 8858 if (hot_swap_cause != 0) { 8859 /* Clear and Disable PAXB interrupts */ 8860 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_INTR_STATUSr(unit, &rval)); 8861 SOC_IF_ERROR_RETURN(WRITE_PAXB_0_PAXB_INTR_STATUSr(unit, rval)); 8862 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_INTR_ENr(unit, &int_en)); 8863 SOC_IF_ERROR_RETURN(WRITE_PAXB_0_PAXB_INTR_ENr(unit, 0)); 8864 8865 /* Poll for the HotSwap FSM_STATE to be DUMMYRESP or IDLE */ 8866 stime = sal_time_usecs(); 8867 while (!soc_timeout_check(&to)) { 8868 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_HOTSWAP_STATr(unit, &rval)); 8869 fsm_state = soc_reg_field_get(unit, PAXB_0_PAXB_HOTSWAP_STATr, 8870 rval, FSM_STATEf); 8871 if ((fsm_state == 0x0) || (fsm_state == 0x03)) { 8872 break; 8873 } 8874 } 8875 etime = sal_time_usecs(); 8876 /* Check if time out has happened */ 8877 if (SAL_USECS_SUB(etime, stime) > hot_swap_usec) { 8878 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8879 "Hot Swap Wait Time Out for IDLE/DUMMYRESP\n"))); 8880 rv = SOC_E_TIMEOUT; 8881 SOC_IF_ERROR_RETURN(rv); 8882 } else { 8883 LOG_INFO(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8884 "Hot Swap logic IDLE/DUMMYRESP done in %d usec\n"), 8885 SAL_USECS_SUB(etime, stime))); 8886 } 8887 /* Only Abort the DMA for CMC0 */ 8888 rv = soc_cmicx_dma_abort(unit, SOC_DMA_ABORT_CMC0); 8889 if (SOC_FAILURE(rv)) { 8890 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8891 "Error: Hot Swap recovery DMA Abort = %d\n"), rv)); 8892 SOC_IF_ERROR_RETURN(soc_event_generate(unit, 8893 SOC_SWITCH_EVENT_UNCONTROLLED_SHUTDOWN, 8894 0, 0, 0)); 8895 } 8896 /* Asert SERVICE_COMPLETE bit in HOTSWAP CONTROL register to communicate to 8897 * PCIE subsystem that all CMIC DMA channels have been aborted 8898 */ 8899 if (SOC_REG_IS_VALID(unit, PAXB_0_PAXB_HOTSWAP_CTRLr) && 8900 SOC_REG_FIELD_VALID(unit, PAXB_0_PAXB_HOTSWAP_CTRLr, SERVICE_COMPLETEf)) { 8901 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_HOTSWAP_CTRLr(unit, &rval)); 8902 soc_reg_field_set(unit, PAXB_0_PAXB_HOTSWAP_CTRLr, &rval, SERVICE_COMPLETEf, 1); 8903 SOC_IF_ERROR_RETURN( 8904 WRITE_PAXB_0_PAXB_HOTSWAP_CTRLr(unit, rval)); 8905 } 8906 8907 SDK_CONFIG_MEMORY_BARRIER; 8908 8909 /* Wait for PAXB_RDY bit to get set in HOTSWAP_STAT register to ensure that PCIE 8910 * subsystem is ready to accept new requests 8911 */ 8912 if (SOC_REG_FIELD_VALID(unit, PAXB_0_PAXB_HOTSWAP_STATr, PAXB_RDYf)) { 8913 int ready; 8914 soc_timeout_init(&to, hot_swap_usec, 0); 8915 stime = sal_time_usecs(); 8916 while (!soc_timeout_check(&to)) { 8917 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_HOTSWAP_STATr(unit, &rval)); 8918 ready = soc_reg_field_get(unit, PAXB_0_PAXB_HOTSWAP_STATr, 8919 rval, PAXB_RDYf); 8920 if (ready) { 8921 LOG_INFO(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8922 "PAXB Ready to accept new requests.\n"))); 8923 /* Reset PAXB_RDY and HOTSWAP_CAUSE bit */ 8924 rval = 0; 8925 soc_reg_field_set(unit, PAXB_0_PAXB_HOTSWAP_STATr, 8926 &rval, PAXB_RDYf, 0x01); 8927 soc_reg_field_set(unit, PAXB_0_PAXB_HOTSWAP_STATr, 8928 &rval, HOTSWAP_CAUSEf, 0x07); 8929 SOC_IF_ERROR_RETURN( 8930 WRITE_PAXB_0_PAXB_HOTSWAP_STATr(unit, rval)); 8931 break; 8932 } 8933 } 8934 etime = sal_time_usecs(); 8935 /* Hot Swap status after Recovery */ 8936 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_HOTSWAP_STATr(unit, &rval)); 8937 LOG_INFO(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8938 "Hot Swap status after Recovery = 0x%x\n"), 8939 rval)); 8940 /* Clear and Restore PAXB interrupts */ 8941 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_INTR_STATUSr(unit, &rval)); 8942 SOC_IF_ERROR_RETURN(WRITE_PAXB_0_PAXB_INTR_STATUSr(unit, rval)); 8943 SOC_IF_ERROR_RETURN(WRITE_PAXB_0_PAXB_INTR_ENr(unit, int_en)); 8944 8945 /* Check if time out has happened */ 8946 if (SAL_USECS_SUB(etime, stime) > hot_swap_usec) { 8947 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8948 "Hot Swap Wait Time Out for READY\n"))); 8949 /* Debug information */ 8950 SOC_IF_ERROR_RETURN 8951 (READ_CMICX_M0_IDM_IDM_RESET_STATUSr(unit, &rval)); 8952 LOG_INFO(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8953 "CMICX_M0_IDM_IDM_RESET_STATUSr=0x%x \r\n"), rval)); 8954 SOC_IF_ERROR_RETURN 8955 (READ_AXI_PCIE_S0_IDM_IDM_RESET_STATUSr(unit, &rval)); 8956 LOG_INFO(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8957 "AXI_PCIE_S0_IDM_IDM_RESET_STATUSr=0x%x \r\n"), rval)); 8958 rv = SOC_E_TIMEOUT; 8959 SOC_IF_ERROR_RETURN(rv); 8960 } else { 8961 LOG_INFO(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8962 "PCI subsystem READY in %d usec\n"), 8963 SAL_USECS_SUB(etime, stime))); 8964 } 8965 } 8966 }else { 8967 LOG_INFO(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8968 "No Hot Swap event recorded\n"))); 8969 } 8970 } 8971 } 8972 #endif 8973 8974 return rv; 8975 } 8976 8977 /* 8978 * Function: 8979 * soc_pcie_hot_swap_disable 8980 * Purpose: 8981 * Disable hot swap manager. 8982 * Parameters: 8983 * unit - unit # 8984 * Returns: 8985 * SOC_E_XXX 8986 */ 8987 int 8988 soc_pcie_hot_swap_disable(int unit) 8989 { 8990 int rv = SOC_E_UNAVAIL; 8991 8992 #ifdef BCM_CMICX_SUPPORT 8993 uint32 rval; 8994 if (soc_feature(unit, soc_feature_cmicx) && 8995 (soc_cm_get_bus_type(unit) & SOC_PCI_DEV_TYPE)) { 8996 /* Disable Hot Swap manager*/ 8997 if (SOC_REG_IS_VALID(unit, PAXB_0_PAXB_HOTSWAP_CTRLr) && 8998 SOC_REG_FIELD_VALID(unit, PAXB_0_PAXB_HOTSWAP_CTRLr, ENABLEf)) { 8999 SOC_IF_ERROR_RETURN(READ_PAXB_0_PAXB_HOTSWAP_CTRLr(unit, &rval)); 9000 soc_reg_field_set(unit, PAXB_0_PAXB_HOTSWAP_CTRLr, &rval, ENABLEf, 0); 9001 SOC_IF_ERROR_RETURN( 9002 WRITE_PAXB_0_PAXB_HOTSWAP_CTRLr(unit, rval)); 9003 /* Enable reset to propogate to paxb data path logic when pcie link is down. */ 9004 SOC_IF_ERROR_RETURN 9005 (READ_PAXB_0_RESET_ENABLE_IN_PCIE_LINK_DOWNr(unit, &rval)); 9006 soc_reg_field_set(unit, PAXB_0_RESET_ENABLE_IN_PCIE_LINK_DOWNr, &rval, 9007 EN_PAXB_RESETf, 1); 9008 SOC_IF_ERROR_RETURN 9009 (WRITE_PAXB_0_RESET_ENABLE_IN_PCIE_LINK_DOWNr(unit, rval)); 9010 LOG_INFO(BSL_LS_SOC_COMMON, 9011 (BSL_META_U(unit, "PCIE HOTSWAP Manager is disabled!\n"))); 9012 rv = SOC_E_NONE; 9013 } 9014 } 9015 #endif 9016 return rv; 9017 } 9018 9019 9020 /* 9021 * Function: 9022 * soc_do_init 9023 * Purpose: 9024 * Optionally reset, and initialize a StrataSwitch. 9025 * Parameters: 9026 * unit - StrataSwitch unit # 9027 * reset - Boolean, if TRUE, device is reset. 9028 * Returns: 9029 * SOC_E_XXX 9030 * Notes: 9031 * Resets the SOC chip using the SCP reset provided by CMIC. 9032 * Fields in soc_control_t are initialized to correspond to a SOC 9033 * post-reset. SOC interrupts are configured for normal chip 9034 * operation. 9035 * 9036 * This routine may be called after a device is attached 9037 * or whenever a chip reset is required. 9038 * 9039 * IMPORTANT NOTE: 9040 * Only the quickest, most basic things should be initialized here. 9041 * This routine may NOT do anything time consuming like scanning ports, 9042 * clearing counters, etc. Such things should be done as commands in 9043 * the rc script. Otherwise, Verilog and Quickturn simulations take 9044 * too long. 9045 */ 9046 int 9047 soc_do_init(int unit, int reset) 9048 { 9049 soc_control_t *soc; 9050 soc_persist_t *sop; 9051 soc_mem_t mem; 9052 uint32 reg; 9053 uint16 max_class; 9054 uint16 mem_clear_chunk_size; 9055 int rv, blk, cache; 9056 int copyno = COPYNO_ALL; 9057 #ifdef BCM_WARM_BOOT_SUPPORT 9058 int offset = 0; 9059 int num_ipv6_128b_entries = 0; 9060 uint32 rval = 0; 9061 #endif 9062 #if !defined(SOC_NO_NAMES) 9063 #if defined(BCM_ESW_SUPPORT) || \ 9064 defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) 9065 uint8 chk_skip_cache = 0; 9066 char mem_name[128]; 9067 char *mptr; 9068 #endif 9069 #endif 9070 soc_ipg_t *soc_ipg; 9071 soc_pbmp_t pbmp; 9072 soc_port_t port; 9073 9074 if (!SOC_UNIT_VALID(unit)) { 9075 LOG_ERROR(BSL_LS_SOC_COMMON, 9076 (BSL_META_U(unit, 9077 "soc_init: unit %d not valid\n"), unit)); 9078 return SOC_E_UNIT; 9079 } 9080 9081 soc = SOC_CONTROL(unit); 9082 sop = SOC_PERSIST(unit); 9083 9084 if (!(soc->soc_flags & SOC_F_ATTACHED)) { 9085 LOG_ERROR(BSL_LS_SOC_COMMON, 9086 (BSL_META_U(unit, 9087 "soc_init: unit %d not attached\n"), unit)); 9088 return(SOC_E_UNIT); 9089 } 9090 9091 9092 9093 #if defined(BCM_RCPU_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) 9094 if (SOC_IS_RCPU_ONLY(unit)) { 9095 soc_rcpu_init(unit); 9096 } 9097 #endif 9098 #ifdef BCM_TRIUMPH3_SUPPORT 9099 if (SOC_IS_TRIUMPH3(unit)) { 9100 _bcm_esw_ibod_sync_recovery_stop(unit); 9101 } 9102 #endif 9103 9104 /* Cancel all DPCs belonging to a specified owner, and then 9105 * disable a specified owner to execute DPCs. 9106 * Soc initialization is not done, so DPCs can't be executed. 9107 * Although the DPCs can't be executed, but they can be reported. 9108 * After Soc initialization is done, the DPCs will be executed. 9109 */ 9110 sal_dpc_cancel_and_disable(INT_TO_PTR(unit)); 9111 9112 /* Initialize PCI Host interface */ 9113 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) 9114 SOC_IF_ERROR_RETURN(soc_pcie_host_intf_init(unit)); 9115 #endif 9116 9117 /* Check for PCI hot swap and recover */ 9118 SOC_IF_ERROR_RETURN(soc_pci_hotswap_recover(unit)); 9119 9120 /***********************************************************************/ 9121 /* If the device has already been initialized before, perform some */ 9122 /* de-initialization to avoid stomping on existing activities. */ 9123 /***********************************************************************/ 9124 if (SOC_WARM_BOOT(unit)) { 9125 pbmp_t empty_pbm; 9126 9127 #if defined(BCM_WARM_BOOT_SUPPORT) && defined(BCM_TOMAHAWK_SUPPORT) 9128 /* Reinit latency filters */ 9129 if (SOC_IS_TOMAHAWKX(unit)) { 9130 SOC_IF_ERROR_RETURN(soc_th_latency_wb_reinit(unit, 1)); 9131 } 9132 #endif 9133 /* Cleanup old PCIe link failure based issues */ 9134 #if defined(BCM_CMICM_SUPPORT) && defined(BCM_SBUSDMA_SUPPORT) 9135 if (soc_feature(unit, soc_feature_cmicm) && 9136 soc_feature(unit, soc_feature_sbusdma)) { 9137 int cmc = SOC_PCI_CMC(unit); 9138 int isValidRead = 0; 9139 reg = soc_pci_read(unit, CMIC_CMCx_IRQ_STAT1_OFFSET(cmc)); 9140 #ifdef BCM_TOMAHAWK2_SUPPORT 9141 if (SOC_IS_TOMAHAWK2(unit)) { 9142 /* Tomahawk2 got these obsolete fields removed */ 9143 } else 9144 #endif 9145 #ifdef BCM_SABER2_SUPPORT 9146 if (SOC_IS_SABER2(unit)) { 9147 if (soc_reg_field_get(unit, CMIC_RPE_IRQ_STAT1r, reg, 9148 PCIEINTF_NEEDS_CLEANUPf) || 9149 soc_reg_field_get(unit, CMIC_CMC0_IRQ_STAT1r, reg, 9150 PCIE_ECRC_ERR_INTRf)) { 9151 isValidRead = 1; 9152 } 9153 } else 9154 #endif 9155 { 9156 if (soc_reg_field_valid 9157 (unit, CMIC_CMC0_IRQ_STAT1r, PCIEINTF_NEEDS_CLEANUPf)) { 9158 if (soc_reg_field_get(unit, CMIC_CMC0_IRQ_STAT1r, reg, 9159 PCIEINTF_NEEDS_CLEANUPf) || 9160 soc_reg_field_get(unit, CMIC_CMC0_IRQ_STAT1r, reg, 9161 PCIE_ECRC_ERR_INTRf)) { 9162 isValidRead = 1; 9163 } 9164 } else { 9165 if (soc_reg_field_get(unit, CMIC_CMC0_IRQ_STAT1r, reg, 9166 PCIE_ECRC_ERR_INTRf)) { 9167 isValidRead = 1; 9168 } 9169 } 9170 } 9171 9172 if(isValidRead) { 9173 /* coverity[result_independent_of_operands] */ 9174 SOC_IF_ERROR_RETURN 9175 (READ_CMIC_PCIE_USERIF_STATUS_CLRr(unit, ®)); 9176 soc_reg_field_set(unit, CMIC_PCIE_USERIF_STATUS_CLRr, ®, 9177 USERIF_TIMEDOUTf, 1); 9178 soc_reg_field_set(unit, CMIC_PCIE_USERIF_STATUS_CLRr, ®, 9179 USERIF_RESETf, 1); 9180 /* coverity[result_independent_of_operands] */ 9181 SOC_IF_ERROR_RETURN 9182 (WRITE_CMIC_PCIE_USERIF_STATUS_CLRr(unit, reg)); 9183 reg = soc_pci_read(unit, CMIC_CMCx_SBUSDMA_CHy_CONTROL(cmc, 0)); 9184 soc_reg_field_set(unit, CMIC_CMC0_SBUSDMA_CH0_CONTROLr, ®, 9185 ABORTf, 1); 9186 soc_pci_write(unit, CMIC_CMCx_SBUSDMA_CHy_CONTROL(cmc, 0), reg); 9187 reg = soc_pci_read(unit, CMIC_CMCx_SBUSDMA_CHy_CONTROL(cmc, 1)); 9188 soc_reg_field_set(unit, CMIC_CMC0_SBUSDMA_CH0_CONTROLr, ®, 9189 ABORTf, 1); 9190 soc_pci_write(unit, CMIC_CMCx_SBUSDMA_CHy_CONTROL(cmc, 1), reg); 9191 reg = soc_pci_read(unit, CMIC_CMCx_SBUSDMA_CHy_CONTROL(cmc, 2)); 9192 soc_reg_field_set(unit, CMIC_CMC0_SBUSDMA_CH0_CONTROLr, ®, 9193 ABORTf, 1); 9194 soc_pci_write(unit, CMIC_CMCx_SBUSDMA_CHy_CONTROL(cmc, 2), reg); 9195 9196 SOC_IF_ERROR_RETURN(_soc_mem_sbus_fifo_dma_stop(unit, 0)); 9197 SOC_IF_ERROR_RETURN(_soc_mem_sbus_fifo_dma_stop(unit, 1)); 9198 SOC_IF_ERROR_RETURN(_soc_mem_sbus_fifo_dma_stop(unit, 2)); 9199 SOC_IF_ERROR_RETURN(_soc_mem_sbus_fifo_dma_stop(unit, 3)); 9200 } 9201 SOC_IF_ERROR_RETURN(READ_CMIC_PCIE_USERIF_PURGE_STATUSr(unit, ®)); 9202 if (reg) { 9203 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9204 (BSL_META_U(unit, 9205 "PCIE purge clear 0x%08x.\n"), reg)); 9206 /* coverity[result_independent_of_operands] */ 9207 SOC_IF_ERROR_RETURN(WRITE_CMIC_PCIE_USERIF_PURGE_CONTROLr(unit, 0)); 9208 } 9209 } 9210 #endif /* BCM_CMICM_SUPPORT && BCM_SBUSDMA_SUPPORT */ 9211 9212 if (!SOC_IS_RCPU_ONLY(unit)) { 9213 rv = soc_dma_abort(unit); 9214 9215 if (SOC_FAILURE(rv)) { 9216 SOC_IF_ERROR_RETURN(soc_event_generate(unit, 9217 SOC_SWITCH_EVENT_UNCONTROLLED_SHUTDOWN, 9218 0, 0, 0)); 9219 } 9220 } 9221 /* Assume HW linkscan is running, shut it down to allow 9222 * PHY probes. Linkscan will turn it back on when needed. */ 9223 9224 /* Set linkscan enable flag, it will be turned off by the 9225 * empty bitmap config call. */ 9226 soc->soc_flags |= SOC_F_LSE; 9227 SOC_PBMP_CLEAR(empty_pbm); 9228 9229 SOC_IF_ERROR_RETURN 9230 (soc_linkscan_config(unit, empty_pbm, empty_pbm)); 9231 } else { 9232 /* Cold Boot case */ 9233 #ifdef BCM_WARM_BOOT_SUPPORT 9234 SOC_IF_ERROR_RETURN(soc_scache_dictionary_alloc(unit)); 9235 #if defined(BCM_METROLITE_SUPPORT) 9236 if (SOC_IS_METROLITE(unit)) { 9237 SOC_IF_ERROR_RETURN(_soc_ml_flexio_scache_allocate(unit)); 9238 } else 9239 #endif 9240 #ifdef BCM_SABER2_SUPPORT 9241 if (SOC_IS_SABER2(unit)) { 9242 SOC_IF_ERROR_RETURN(_soc_saber2_flexio_scache_allocate(unit)); 9243 } else 9244 #endif 9245 #ifdef BCM_KATANA2_SUPPORT 9246 if (SOC_IS_KATANA2(unit)) { 9247 SOC_IF_ERROR_RETURN(_soc_katana2_flexio_scache_allocate(unit)); 9248 } 9249 #endif 9250 #endif 9251 } 9252 9253 /***********************************************************************/ 9254 /* Always be sure device has correct endian configuration before */ 9255 /* touching registers - device may not have been configured yet. */ 9256 /***********************************************************************/ 9257 9258 if (!SOC_WARM_BOOT(unit) && !SOC_IS_RCPU_ONLY(unit)) { 9259 soc_endian_config(unit); 9260 soc_pci_ep_config(unit, -1); 9261 } 9262 9263 /* Stop the UC & UC msging */ 9264 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_IPROC_SUPPORT) 9265 if (!SOC_WARM_BOOT(unit)) { 9266 int reset_uC = TRUE; 9267 9268 #ifdef BCM_TOMAHAWK3_SUPPORT 9269 /* For TH3, bring down portmod to make sure that the 9270 * 400G AN state machine is stopped. Otherwise, it will continue 9271 * trying to access the serdes when portmod isn't up yet 9272 */ 9273 if (SOC_IS_TOMAHAWK3(unit)) { 9274 SOC_IF_ERROR_RETURN(soc_esw_portctrl_deinit(unit)); 9275 } 9276 #endif 9277 9278 if (soc_feature(unit, soc_feature_uc)) { 9279 #if defined (BCM_IPROC_SUPPORT) 9280 if (soc_feature(unit, soc_feature_iproc)) { 9281 #if defined (BCM_UC_MHOST_SUPPORT) 9282 if (!soc_feature(unit, soc_feature_uc_mhost)) 9283 #endif /* BCM_UC_MHOST_SUPPORT */ 9284 { 9285 if (soc_cm_get_bus_type(unit) & SOC_AXI_DEV_TYPE) { 9286 /* SDK is running iHost on A9 uC, no EAPPS are running, 9287 * don't reset the uC 9288 */ 9289 reset_uC = FALSE; 9290 } 9291 } 9292 } 9293 #endif /* BCM_IPROC_SUPPORT */ 9294 } 9295 else { 9296 reset_uC = FALSE; 9297 } 9298 9299 if (reset_uC) { 9300 soc_cmic_uc_msg_shutdown_halt(unit); 9301 } 9302 } 9303 #endif /* BCM_CMICM_SUPPORT || BCM_IPROC_SUPPORT */ 9304 9305 /* Stop iproc m0 subsystem */ 9306 #ifdef BCM_CMICX_SUPPORT 9307 if (!SOC_WARM_BOOT(unit)) { 9308 if (soc_feature(unit, soc_feature_cmicx) && !(SAL_BOOT_PLISIM || SAL_BOOT_BCMSIM)) { 9309 /* Stop LED FW */ 9310 soc_cmicx_led_enable(unit, LED_STOP); 9311 /* Iproc M0 exit */ 9312 soc_iproc_m0_exit(unit); 9313 } 9314 } 9315 #endif 9316 9317 if (soc->soc_flags & SOC_F_INITED) { 9318 if (!SOC_IS_RCPU_ONLY(unit)) { 9319 SOC_IF_ERROR_RETURN(soc_dma_abort(unit)); /* Turns off/clean up DMA */ 9320 } 9321 SOC_IF_ERROR_RETURN(soc_counter_stop(unit)); /* Stop counter collection */ 9322 #ifdef INCLUDE_MEM_SCAN 9323 SOC_IF_ERROR_RETURN(soc_mem_scan_stop(unit)); /* Stop memory scanner */ 9324 #endif 9325 #ifdef BCM_SRAM_SCAN_SUPPORT 9326 SOC_IF_ERROR_RETURN(soc_sram_scan_stop(unit)); /* Stop sram scanner */ 9327 #endif 9328 #ifdef INCLUDE_I2C 9329 SOC_IF_ERROR_RETURN(soc_i2c_detach(unit)); /* Free up I2C driver mem */ 9330 #endif 9331 9332 #ifdef BCM_XGS_SWITCH_SUPPORT 9333 if (soc_feature(unit, soc_feature_arl_hashed)) { 9334 /* Stop L2X thread */ 9335 SOC_IF_ERROR_RETURN(soc_l2x_stop(unit)); 9336 } 9337 #ifdef BCM_TRIUMPH3_SUPPORT 9338 if SOC_IS_TRIUMPH3(unit) { 9339 SOC_IF_ERROR_RETURN(soc_tr3_l2_bulk_age_stop(unit)); 9340 } 9341 #endif /* BCM_TRIUMPH3_SUPPORT */ 9342 #ifdef BCM_TRIDENT2_SUPPORT 9343 if SOC_IS_TRIDENT2X(unit) { 9344 SOC_IF_ERROR_RETURN(soc_td2_l2_bulk_age_stop(unit)); 9345 } 9346 #endif /* BCM_TRIDENT2_SUPPORT */ 9347 #ifdef BCM_TOMAHAWK_SUPPORT 9348 if (SOC_IS_TOMAHAWK(unit) || SOC_IS_TOMAHAWK2(unit) || 9349 SOC_IS_TRIDENT3X(unit)) { 9350 SOC_IF_ERROR_RETURN(soc_th_l2_bulk_age_stop(unit)); 9351 } 9352 #endif /* BCM_TOMAHAWK_SUPPORT */ 9353 #endif /* BCM_XGS_SWITCH_SUPPORT */ 9354 9355 if (soc->arlShadow != NULL) { 9356 sal_mutex_take(soc->arlShadowMutex, sal_mutex_FOREVER); 9357 shr_avl_delete_all(soc->arlShadow); 9358 sal_mutex_give(soc->arlShadowMutex); 9359 } 9360 9361 #ifdef ALPM_ENABLE 9362 #if defined(BCM_TOMAHAWK_SUPPORT) 9363 if (soc_property_get(unit, spn_L3_ALPM_ENABLE, 0) && 9364 soc_feature(unit, soc_feature_alpm2)) { 9365 SOC_IF_ERROR_RETURN(alpm_dist_hitbit_thread_stop(unit)); 9366 } 9367 #endif 9368 #endif 9369 #ifdef BCM_TOMAHAWK3_SUPPORT 9370 if (SOC_IS_TOMAHAWK3(unit)) { 9371 SOC_IF_ERROR_RETURN(soc_th3_l2_age_stop(unit)); 9372 9373 /* Stop learn thread (if it's running) */ 9374 SOC_IF_ERROR_RETURN(soc_th3_l2_learn_thread_stop(unit)); 9375 9376 /* Free AVL table used for L2 learning */ 9377 if ((soc->l2x_lrn_shadow != NULL) && 9378 (soc->l2x_lrn_shadow_mutex != NULL)) { 9379 sal_mutex_take(soc->l2x_lrn_shadow_mutex, sal_mutex_FOREVER); 9380 shr_avl_delete_all(soc->l2x_lrn_shadow); 9381 sal_mutex_give(soc->l2x_lrn_shadow_mutex); 9382 9383 shr_avl_destroy(soc->l2x_lrn_shadow); 9384 soc->l2x_lrn_shadow = NULL; 9385 sal_mutex_destroy(soc->l2x_lrn_shadow_mutex); 9386 soc->l2x_lrn_shadow_mutex = NULL; 9387 } 9388 } 9389 #endif /* BCM_TOMAHAWK3_SUPPORT */ 9390 9391 /* Destroy egress metering mutex. */ 9392 if (soc->egressMeteringMutex != NULL) { 9393 sal_mutex_destroy(soc->egressMeteringMutex); 9394 soc->egressMeteringMutex = NULL; 9395 } 9396 9397 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_APACHE_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 9398 if (SOC_IS_KATANAX(unit) || SOC_IS_TRIDENT2X(unit) || 9399 SOC_IS_TITAN2X(unit) || SOC_IS_TRIUMPH3(unit)) { 9400 /* Destroy llsMutex */ 9401 if (soc->llsMutex !=NULL) { 9402 sal_mutex_destroy(soc->llsMutex); 9403 soc->llsMutex = NULL; 9404 } 9405 } 9406 #endif 9407 9408 #if defined(BCM_TOMAHAWK_SUPPORT) 9409 if (SOC_IS_TOMAHAWKX(unit)) { 9410 /* Destroy idb_lock */ 9411 if (soc->idb_lock !=NULL) { 9412 sal_mutex_destroy(soc->idb_lock); 9413 soc->idb_lock = NULL; 9414 } 9415 } 9416 #endif 9417 soc->soc_flags &= ~SOC_F_INITED; 9418 } 9419 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) 9420 if (soc_feature(unit, soc_feature_epc_linkflap_recover)) { 9421 /* Destroy linkscan_modport_map_lock_lock */ 9422 if (soc->linkscan_modport_map_lock !=NULL) { 9423 sal_mutex_destroy(soc->linkscan_modport_map_lock); 9424 soc->linkscan_modport_map_lock = NULL; 9425 } 9426 } 9427 #endif /* #(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) */ 9428 9429 #ifdef BCM_WARM_BOOT_SUPPORT 9430 if (SOC_WARM_BOOT(unit)) { 9431 rv = soc_scache_recover(unit); 9432 if (SOC_FAILURE(rv)) { 9433 /* Fall back to Level 1 Warm Boot recovery */ 9434 SOC_IF_ERROR_RETURN(soc_stable_size_set(unit, 0)); 9435 SOC_IF_ERROR_RETURN 9436 (soc_stable_set(unit, _SHR_SWITCH_STABLE_NONE, 0)); 9437 /* Error report */ 9438 SOC_IF_ERROR_RETURN 9439 (soc_event_generate(unit, SOC_SWITCH_EVENT_STABLE_ERROR, 9440 SOC_STABLE_CORRUPT, 9441 SOC_STABLE_FLAGS(unit), 0)); 9442 LOG_WARN(BSL_LS_SOC_COMMON, 9443 (BSL_META_U(unit, 9444 "Corrupt stable cache.\n"))); 9445 } else { 9446 SOC_IF_ERROR_RETURN(soc_mem_cache_scache_get(unit)); 9447 SOC_IF_ERROR_RETURN(soc_scache_dictionary_recover(unit)); 9448 #if defined(BCM_METROLITE_SUPPORT) 9449 if (SOC_IS_METROLITE(unit)) { 9450 SOC_IF_ERROR_RETURN(_soc_ml_flexio_scache_retrieve(unit)); 9451 } else 9452 #endif 9453 #ifdef BCM_SABER2_SUPPORT 9454 if (SOC_IS_SABER2(unit)) { 9455 SOC_IF_ERROR_RETURN(_soc_saber2_flexio_scache_retrieve(unit)); 9456 } else 9457 #endif 9458 #ifdef BCM_KATANA2_SUPPORT 9459 if (SOC_IS_KATANA2(unit)) { 9460 SOC_IF_ERROR_RETURN(_soc_katana2_flexio_scache_retrieve(unit)); 9461 } 9462 #endif 9463 } 9464 } 9465 #endif 9466 9467 /* Clear previous phy configs if any */ 9468 SOC_IF_ERROR_RETURN(soc_phyctrl_software_deinit(unit)); 9469 9470 /* Set bitmaps according to which type of device it is */ 9471 SOC_IF_ERROR_RETURN(soc_info_config(unit, soc)); 9472 9473 /* Set feature cache */ 9474 9475 soc_feature_init(unit); 9476 soc_dcb_unit_init(unit); 9477 9478 #if defined(BCM_ESW_SUPPORT) && defined(BCM_IPROC_SUPPORT) 9479 /* 9480 * Add/Remove features, update soc_control cache based on 9481 * Bon Options info read from the relevant capability registers 9482 */ 9483 if (soc_feature(unit, soc_feature_untethered_otp)) { 9484 soc_info_bondoptions_adjust(unit); 9485 } 9486 #endif /* BCM_ESW_SUPPORT && BCM_IPROC_SUPPORT */ 9487 9488 9489 #ifdef BCM_CB_ABORT_ON_ERR 9490 SOC_CB_ABORT_ON_ERR(unit) = soc_property_get(unit, spn_CB_ABORT_ON_ERR, 0); 9491 #endif 9492 9493 if (!SOC_IS_RCPU_ONLY(unit) && !(soc->soc_flags & SOC_F_INITED) && 9494 (soc_cm_get_bus_type(unit) & SOC_PCI_DEV_TYPE) && 9495 !(SAL_BOOT_PLISIM || SAL_BOOT_BCMSIM)) { 9496 uint32 cfg_dw = 0; 9497 uint8 cap_id = 0, base_ptr = 0; 9498 soc_info_t *si = &SOC_INFO(unit); 9499 uint16 pcie_phy_addr = si->pcie_phy_addr; 9500 uint8 change = SOC_IS_TD2P_TT2P(unit) ? FALSE : TRUE; 9501 9502 /* Device has not been initialized... */ 9503 9504 /*********************************************************************/ 9505 /* Disable clock compensation Events for Helix4 PCIe in EP, x2 mode */ 9506 /*********************************************************************/ 9507 #if defined(BCM_HELIX4_SUPPORT) 9508 if (SOC_IS_HELIX4(unit)) { 9509 SOC_IF_ERROR_RETURN(iproc_pcie_common_clk_set(unit, pcie_phy_addr)); 9510 } 9511 #endif 9512 9513 /*********************************************************************/ 9514 /* PCIe SerDes Gen1/Gen2 CDR Track Bandwidth Adjustment */ 9515 /* for Better Jitter Tolerance. */ 9516 /*********************************************************************/ 9517 if (pcie_phy_addr != 0) { 9518 #ifdef BCM_IPROC_SUPPORT 9519 if (soc_feature(unit, soc_feature_iproc)) { 9520 SOC_IF_ERROR_RETURN(iproc_pcie_cdr_bw_adj(unit, pcie_phy_addr)); 9521 } else 9522 #endif 9523 { 9524 SOC_IF_ERROR_RETURN(cmic_pcie_cdr_bw_adj(unit, pcie_phy_addr)); 9525 } 9526 } 9527 9528 if (change) { 9529 /*********************************************************************/ 9530 /* Check to see if the PCIe SerDes deemphasis needs to be changed */ 9531 /* based on the advertisement from the root complex */ 9532 /*********************************************************************/ 9533 /*Find PCIe capability base */ 9534 base_ptr = soc_pci_conf_read(unit, 0x34) & 0xff; 9535 while ((base_ptr >= 0x40) && (base_ptr < 0xff)) { 9536 cfg_dw = soc_pci_conf_read(unit, base_ptr); 9537 cap_id = cfg_dw & 0xff; 9538 if (cap_id == 0x10) break; 9539 base_ptr = (cfg_dw >> 8) & 0xff; 9540 } 9541 /* Check for PCIe Gen2 -3.5dB advertisement */ 9542 if ((cap_id == 0x10) && 9543 ((soc_pci_conf_read(unit, base_ptr + 0x10) & 0xf0000) == 0x20000) && 9544 (soc_pci_conf_read(unit, base_ptr + 0x30) & 0x00010000)) { 9545 /* Device is operating at Gen2 speeds and RC requested -3.5dB */ 9546 9547 if (pcie_phy_addr != 0) { 9548 #ifdef BCM_IPROC_SUPPORT 9549 if (soc_feature(unit, soc_feature_iproc)) { 9550 SOC_IF_ERROR_RETURN(iproc_pcie_deemphasis_set(unit, pcie_phy_addr)); 9551 } else 9552 #endif 9553 #ifdef BCM_CMICM_SUPPORT 9554 if (soc_feature(unit, soc_feature_cmicm)) { 9555 SOC_IF_ERROR_RETURN(cmicm_pcie_deemphasis_set(unit, pcie_phy_addr)); 9556 } else 9557 #endif 9558 { 9559 SOC_IF_ERROR_RETURN(cmice_pcie_deemphasis_set(unit, pcie_phy_addr)); 9560 } 9561 } 9562 } 9563 } 9564 } 9565 9566 /***********************************************************************/ 9567 /* Always enable bursting before doing any more reads or writes */ 9568 /***********************************************************************/ 9569 9570 if (!SOC_WARM_BOOT(unit) && !SOC_IS_RCPU_ONLY(unit)) { 9571 soc_pci_burst_enable(unit); 9572 } 9573 9574 #ifdef BCM_CMICX_SUPPORT 9575 if (soc_feature(unit, soc_feature_iproc_14_tx_arbiter_priority)) { 9576 SOC_IF_ERROR_RETURN(soc_cmicx_paxb_tx_arbiter_set(unit, PAXB_TX_REQ_SEQ_EN, 9577 PAXB_TX_ARB_PRIORITY)); 9578 } 9579 #endif 9580 9581 /***********************************************************************/ 9582 /* Begin initialization from a known state (reset). */ 9583 /***********************************************************************/ 9584 9585 /* 9586 * PHY drivers and ID map 9587 */ 9588 9589 9590 #if 0 9591 if (!SOC_USE_PORTCTRL(unit)) { 9592 SOC_IF_ERROR_RETURN(soc_phyctrl_software_init(unit)); 9593 } 9594 #else 9595 SOC_IF_ERROR_RETURN(soc_phyctrl_software_init(unit)); 9596 #endif 9597 9598 /* NB: The PHY init must be before fusioncore reset, which is next. */ 9599 9600 if (reset && !SOC_WARM_BOOT(unit) && !SOC_IS_RCPU_ONLY(unit)) { 9601 SOC_IF_ERROR_RETURN(soc_reset(unit)); 9602 } 9603 9604 #ifdef BCM_WARM_BOOT_SUPPORT 9605 if (SOC_WARM_BOOT(unit)){ 9606 SOC_IF_ERROR_RETURN(soc_warmboot_reset(unit)); 9607 } 9608 #endif 9609 9610 if (SOC_WARM_BOOT(unit) && soc_feature(unit, soc_feature_esm_support)) { 9611 #ifdef BCM_TRIUMPH_SUPPORT 9612 SOC_IF_ERROR_RETURN(soc_triumph_esm_init_read_config(unit)); 9613 #endif 9614 } 9615 9616 #ifdef BCM_WARM_BOOT_SUPPORT 9617 if (SOC_WARM_BOOT(unit) && SOC_IS_HELIX4(unit)) { 9618 SOC_IF_ERROR_RETURN(READ_TOP_SWITCH_FEATURE_ENABLEr(unit, &rval)); 9619 if (!(rval & 0x8)) { 9620 /* Disabling MPLS feature during warm boot for HX4, as it is 9621 disabled in cold boot by default */ 9622 SOC_FEATURE_CLEAR(unit, soc_feature_mpls); 9623 SOC_FEATURE_CLEAR(unit, soc_feature_bhh); 9624 } 9625 } 9626 #endif 9627 9628 /* Turn-off soc_feature_riot if feature disabled thru soc property */ 9629 if (soc_feature(unit, soc_feature_riot) && 9630 (0 == soc_property_get(unit, spn_RIOT_ENABLE, 0))) { 9631 SOC_FEATURE_CLEAR(unit, soc_feature_riot); 9632 } 9633 9634 /* 9635 * Update saved chip state to reflect values after reset. 9636 */ 9637 #ifdef BCM_XGS_SUPPORT 9638 if (SOC_IS_XGS(unit)) { 9639 SOC_MEM_CLEAR_HW_ACC_SET(unit, 1); 9640 } 9641 #endif /* BCM_XGS_SUPPORT */ 9642 soc->l3_defip_urpf = 0; 9643 soc->soc_flags &= (SOC_F_RESET | SOC_F_RCPU_ONLY); 9644 #ifdef BCM_XGS_SUPPORT 9645 if (SOC_IS_XGS(unit)) { 9646 SOC_MEM_CLEAR_HW_ACC_SET(unit, 1); 9647 } 9648 #endif /* BCM_XGS_SUPPORT */ 9649 sop->debugMode = 0; 9650 soc->pciParityDPC = 0; 9651 soc->pciFatalDPC = 0; 9652 soc->stat.ser_err_int = 0; 9653 soc->stat.ser_err_fifo = 0; 9654 soc->stat.ser_err_tcam = 0; 9655 soc->stat.ser_err_nak = 0; 9656 soc->stat.ser_err_stat = 0; 9657 soc->stat.ser_err_ecc = 0; 9658 soc->stat.ser_err_corr = 0; 9659 soc->stat.ser_err_clear = 0; 9660 soc->stat.ser_err_restor = 0; 9661 soc->stat.ser_err_spe = 0; 9662 soc->stat.ser_err_reg = 0; 9663 soc->stat.ser_err_mem = 0; 9664 soc->stat.ser_err_sw = 0; 9665 if (soc_feature(unit, soc_feature_ser_error_stat)) { 9666 sal_memset(soc->stat.ser_err, 0, sizeof(soc->stat.ser_err)); 9667 sal_memset(soc->stat.ser_tcam_err, 0, sizeof(soc->stat.ser_tcam_err)); 9668 } 9669 #if defined(INCLUDE_FLOWTRACKER) 9670 soc->uc_flowtracker_enable = 0; 9671 if (soc_feature(unit, soc_feature_uc_flowtracker_learn) || 9672 soc_feature(unit, soc_feature_mv2_style_flowtracker)) { 9673 if (soc_property_get(unit, spn_FLOWTRACKER_ENABLE, 0)) { 9674 soc->uc_flowtracker_enable = 1; 9675 } 9676 } 9677 #endif /* INCLUDE_FLOWTRACKER */ 9678 9679 /* 9680 * Reassign default IPG since all_pbmp might be changed during 9681 * init process after soc_reset() with config property change on 9682 * SKU/option related. 9683 * 9684 * Note : 9685 * - Default IPG setting is assigned during soc_attach(). 9686 * - SOC/BCM layer reinit may change all_pbmp and this causes some 9687 * port's defult IPG setting is not assigned properly. 9688 */ 9689 SOC_PBMP_CLEAR(pbmp); 9690 if (SOC_IS_KATANA2(unit)) { 9691 for (port = SOC_INFO(unit).cmic_port; 9692 port <= SOC_INFO(unit).lb_port; 9693 port++) { 9694 9695 SOC_PBMP_PORT_ADD(pbmp, port); 9696 } 9697 } else { 9698 SOC_PBMP_ASSIGN(pbmp, PBMP_ALL(unit)); 9699 } 9700 9701 BCM_PBMP_ITER(pbmp, port) { 9702 soc_ipg = &sop->ipg[port]; 9703 soc_ipg->hd_10 = SOC_AVERAGE_IPG_IEEE; 9704 soc_ipg->hd_100 = SOC_AVERAGE_IPG_IEEE; 9705 soc_ipg->hd_1000 = SOC_AVERAGE_IPG_IEEE; 9706 soc_ipg->hd_2500 = SOC_AVERAGE_IPG_IEEE; 9707 9708 soc_ipg->fd_10 = SOC_AVERAGE_IPG_IEEE; 9709 soc_ipg->fd_100 = SOC_AVERAGE_IPG_IEEE; 9710 soc_ipg->fd_1000 = SOC_AVERAGE_IPG_IEEE; 9711 soc_ipg->fd_2500 = SOC_AVERAGE_IPG_IEEE; 9712 soc_ipg->fd_10000 = SOC_AVERAGE_IPG_IEEE; 9713 soc_ipg->fd_xe = SOC_AVERAGE_IPG_IEEE; 9714 soc_ipg->fd_hg = SOC_AVERAGE_IPG_HG; 9715 soc_ipg->fd_hg2 = SOC_AVERAGE_IPG_IEEE; 9716 } 9717 9718 #ifdef BCM_WARM_BOOT_SUPPORT 9719 /* Recover stored Level 2 Warm Boot cache */ 9720 /* The stable and stable size must be selected first */ 9721 if (SOC_WARM_BOOT(unit)) { 9722 /* Set urpf mode early for mem cache reload to work properly */ 9723 if (soc_feature(unit, soc_feature_urpf) && 9724 (soc_feature(unit, soc_feature_l3_defip_map) || 9725 soc_feature(unit, soc_feature_l3_defip_hole))) { 9726 SOC_IF_ERROR_RETURN(READ_L3_DEFIP_RPF_CONTROLr(unit, ®)); 9727 if (soc_reg_field_get(unit, L3_DEFIP_RPF_CONTROLr, 9728 reg, DEFIP_RPF_ENABLEf)) { 9729 SOC_CONTROL(unit)->l3_defip_urpf = TRUE; 9730 } 9731 } 9732 } 9733 if (soc_feature(unit, soc_feature_l3_shared_defip_table) && 9734 (SOC_IS_TD2_TT2(unit) || SOC_IS_TRIUMPH3(unit))) { 9735 SOC_IF_ERROR_RETURN(soc_control_defip_scache_init(unit)); 9736 } 9737 9738 if (SOC_WARM_BOOT(unit)) { 9739 if (soc_feature(unit, soc_feature_l3_shared_defip_table) && 9740 (SOC_IS_TD2_TT2(unit) || SOC_IS_TRIUMPH3(unit))) { 9741 num_ipv6_128b_entries = SOC_L3_DEFIP_MAX_128B_ENTRIES(unit); 9742 rv = soc_control_defip_scache_load(unit, &num_ipv6_128b_entries); 9743 if (SOC_SUCCESS(rv) && SOC_MEM_IS_VALID(unit, L3_DEFIP_PAIR_128m)) { 9744 if (num_ipv6_128b_entries != SOC_L3_DEFIP_MAX_128B_ENTRIES(unit)) { 9745 /* Taking lock is not required as we are in soc init */ 9746 soc_defip_tables_resize(unit, num_ipv6_128b_entries); 9747 } 9748 } 9749 } 9750 } 9751 #endif /* BCM_WARM_BOOT_SUPPORT */ 9752 9753 /* 9754 * Initialize memory table status. 9755 */ 9756 cache = soc_feature(unit, soc_feature_mem_cache) && 9757 soc_property_get(unit, spn_MEM_CACHE_ENABLE, 9758 (SAL_BOOT_RTLSIM || SAL_BOOT_XGSSIM) ? 0 : 1); 9759 #if !defined(SOC_NO_NAMES) 9760 #if defined(BCM_ESW_SUPPORT) || \ 9761 defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) 9762 9763 chk_skip_cache = soc_property_get(unit, spn_MEM_CHECK_NOCACHE_OVERRIDE, 0); 9764 #endif 9765 #endif 9766 soc->stat.mem_cache_count = 0; 9767 soc->stat.mem_cache_size = 0; 9768 soc->stat.mem_cache_vmap_size = 0; 9769 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_HELIX4_SUPPORT) || \ 9770 defined(BCM_KATANA2_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) || \ 9771 defined(BCM_GREYHOUND_SUPPORT) 9772 soc->stat.tcam_corrupt_map_size = 0; 9773 #endif 9774 9775 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 9776 9777 uint8 skip_mem = 0; 9778 soc_mem_t act_mem = mem; 9779 9780 if (!SOC_MEM_IS_VALID(unit, mem)) { 9781 continue; 9782 } 9783 if (soc_mem_index_count(unit, mem) == 0) { 9784 continue; 9785 } 9786 sal_memset(sop->memState[mem].count, 0, 9787 sizeof (sop->memState[mem].count)); 9788 #ifdef BCM_ESW_SUPPORT 9789 _SOC_DRV_MEM_REUSE_MEM_STATE_NO_LOCK(unit, act_mem); 9790 #endif 9791 if (act_mem != mem) { 9792 continue; 9793 } 9794 SOC_MEM_BLOCK_ITER(unit, mem, blk) { 9795 copyno = blk; 9796 break; 9797 } 9798 9799 #ifdef BCM_HELIX5_SUPPORT 9800 if (SOC_IS_HELIX5(unit) && mem == BSC_AG_AGE_TABLEm) { 9801 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_READONLY; 9802 } 9803 #endif 9804 9805 if ((SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ETU) || 9806 (SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ESM)) { 9807 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 9808 skip_mem = 1; 9809 } 9810 /* Skip IESMIF mems when ESM is not present */ 9811 else if (SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_IPIPE) { 9812 #ifdef BCM_TRIUMPH3_SUPPORT 9813 if (SOC_IS_TRIUMPH3(unit) && /* Needs update per chip */ 9814 SOC_MEM_ADDR_STAGE_EXTENDED(SOC_MEM_BASE(unit, mem)) == 0x9) { 9815 if (!soc_feature(unit, soc_feature_esm_support) || 9816 SAL_BOOT_QUICKTURN) { 9817 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 9818 skip_mem = 1; 9819 } 9820 } 9821 #endif /* BCM_TRIUMPH3_SUPPORT */ 9822 } 9823 #ifdef BCM_TRIUMPH3_SUPPORT 9824 if (SOC_IS_TRIUMPH3(unit)) { 9825 /* Force cache L2 mem */ 9826 if (mem == L2_ENTRY_1m || mem == L2_ENTRY_2m) { 9827 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 9828 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_SPECIAL; 9829 } 9830 if (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE) { 9831 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 9832 } 9833 /* Skip caching unused views */ 9834 if (mem == ESM_PKT_TYPE_ID_ONLYm || mem == ESM_PKT_TYPE_ID_DATA_ONLYm) { 9835 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 9836 skip_mem = 1; 9837 } 9838 if (mem == MODPORT_MAP_M0m || mem == MODPORT_MAP_M1m || 9839 mem == MODPORT_MAP_M2m || mem == MODPORT_MAP_M3m) { 9840 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 9841 skip_mem = 1; 9842 } 9843 if (mem == DLB_LAG_FLOWSETm || mem == DLB_LAG_FLOWSET_TIMESTAMP_PAGEm) { 9844 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_ENTRY_CLEAR; 9845 } 9846 if (mem == DLB_ECMP_FLOWSETm || mem == DLB_ECMP_FLOWSET_TIMESTAMP_PAGEm) { 9847 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_ENTRY_CLEAR; 9848 } 9849 if (mem == MMU_WRED_PORT_SP_SHARED_COUNTm || 9850 mem == MMU_WRED_QGROUP_SHARED_COUNTm || 9851 mem == MMU_WRED_UC_QUEUE_TOTAL_COUNTm) { 9852 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_ENTRY_CLEAR; 9853 } 9854 } 9855 #endif /* BCM_TRIUMPH3_SUPPORT */ 9856 #ifdef BCM_TRIDENT_SUPPORT 9857 if (SOC_IS_TD_TT(unit) || SOC_IS_TD2_TT2(unit)) { 9858 int i; 9859 static soc_mem_t mskip[] = { 9860 L3_ENTRY_IPV4_MULTICAST_Xm, 9861 L3_ENTRY_IPV4_MULTICAST_Ym, 9862 L3_ENTRY_IPV6_UNICAST_Xm, 9863 L3_ENTRY_IPV6_UNICAST_Ym 9864 }; 9865 for (i=0; i<COUNTOF(mskip); i++) { 9866 if (mem == mskip[i]) { 9867 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 9868 skip_mem = 1; 9869 break; 9870 } 9871 } 9872 /* Force cache L2 mem */ 9873 if (mem == L2Xm) { 9874 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 9875 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_ENTRY_CLEAR; 9876 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_SPECIAL; 9877 } 9878 if (mem == DLB_HGT_FLOWSET_PORTm ) { 9879 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_SPECIAL; 9880 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 9881 } 9882 if (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE) { 9883 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 9884 } 9885 /* Skip caching unused views */ 9886 if (mem == ING_SNAT_ONLYm || mem == ING_SNAT_DATA_ONLYm || 9887 mem == FP_GLOBAL_MASK_TCAMm || 9888 mem == FP_GLOBAL_MASK_TCAM_Xm || 9889 mem == FP_GLOBAL_MASK_TCAM_Ym || 9890 mem == L2_ENTRY_LPm || mem == L3_ENTRY_LPm || 9891 mem == VLAN_XLATE_LPm || mem == EGR_VLAN_XLATE_LPm || 9892 mem == VLAN_SUBNET_DATA_ONLYm) { 9893 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 9894 skip_mem = 1; 9895 } 9896 if (mem == MODPORT_MAP_M0m || mem == MODPORT_MAP_M1m || 9897 mem == MODPORT_MAP_M2m || mem == MODPORT_MAP_M3m) { 9898 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 9899 skip_mem = 1; 9900 } 9901 } 9902 #endif /* BCM_TRIDENT_SUPPORT */ 9903 if (SOC_IS_TRIDENT3(unit) && soc_feature(unit, soc_feature_alpm2)) { 9904 if (mem == L3_DEFIP_ALPM_IPV4m || mem == L3_DEFIP_ALPM_IPV4_1m || 9905 mem == L3_DEFIP_ALPM_IPV6_64m || mem == L3_DEFIP_ALPM_IPV6_64_1m || 9906 mem == L3_DEFIP_ALPM_IPV6_128m || mem == L3_DEFIP_AUX_TABLEm) { 9907 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 9908 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 9909 skip_mem = 1; 9910 } 9911 } 9912 9913 #ifdef BCM_TRIDENT2_SUPPORT 9914 if (SOC_IS_TD2_TT2(unit)) { 9915 if (mem == L3_DEFIP_ALPM_IPV4m || mem == L3_DEFIP_ALPM_IPV4_1m || 9916 mem == L3_DEFIP_ALPM_IPV6_64m || mem == L3_DEFIP_ALPM_IPV6_64_1m || 9917 mem == L3_DEFIP_ALPM_IPV6_128m || mem == L3_DEFIP_ALPM_RAWm) { 9918 if (NUM_PIPE(unit) != 1 && 9919 !soc_property_get(unit, "l3_alpm_cache_enable", 0)) { 9920 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 9921 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 9922 skip_mem = 1; 9923 } else { 9924 if (soc_feature(unit, soc_feature_alpm_flex_stat) && 9925 soc_property_get(unit, spn_ALPM_FLEX_STAT_SUPPORT, 0)) { 9926 if (mem == L3_DEFIP_ALPM_IPV4m || 9927 mem == L3_DEFIP_ALPM_IPV6_64m) { 9928 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 9929 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 9930 skip_mem = 1; 9931 } 9932 } else { 9933 if (mem == L3_DEFIP_ALPM_IPV4_1m || 9934 mem == L3_DEFIP_ALPM_IPV6_64_1m) { 9935 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 9936 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 9937 skip_mem = 1; 9938 } 9939 } 9940 } 9941 } 9942 if (mem == L3_DEFIP_PAIR_128m || mem == L3_DEFIPm) { 9943 if (NUM_PIPE(unit) != 1 && 9944 !soc_property_get(unit, "l3_alpm_cache_enable", 0)) { 9945 /* 9946 * For multi-pipe devices, always skip caching for these mems. 9947 * For single-pipe devices like Apache, always use caching. 9948 */ 9949 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 9950 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 9951 skip_mem = 1; 9952 } 9953 } 9954 if (mem == L3_DEFIP_AUX_TABLEm) { 9955 if (NUM_PIPE(unit) != 1 && 9956 !soc_property_get(unit, "l3_alpm_cache_enable", 0)) { 9957 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 9958 skip_mem = 1; 9959 } 9960 } 9961 9962 if (mem == MMU_CTR_MC_DROP_MEM0m || mem == MMU_CTR_MC_DROP_MEM1m || 9963 mem == MMU_CTR_COLOR_DROP_MEMm || mem == MMU_CTR_ING_DROP_MEMm || 9964 mem == MMU_CTR_MTRI_DROP_MEMm || mem == MMU_CTR_UC_DROP_MEMm) { 9965 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_ENTRY_CLEAR; 9966 skip_mem = 1; 9967 } 9968 if (mem == MMU_THDM_DB_QUEUE_BST_0m || mem == MMU_THDM_DB_QUEUE_BST_1m || 9969 mem == MMU_THDM_MCQE_QUEUE_BST_0m || mem == MMU_THDM_MCQE_QUEUE_BST_1m || 9970 mem == MMU_THDM_DB_PORTSP_BST_0m || mem == MMU_THDM_DB_PORTSP_BST_1m || 9971 mem == MMU_THDM_MCQE_PORTSP_BST_0m || mem == MMU_THDM_MCQE_PORTSP_BST_1m) { 9972 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_ENTRY_CLEAR; 9973 } 9974 if (mem == RH_HGT_FLOWSETm) { 9975 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 9976 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 9977 } 9978 if (mem == DLB_HGT_FLOWSETm || mem == DLB_HGT_FLOWSET_Xm || 9979 mem == DLB_HGT_FLOWSET_Ym) { 9980 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_SPECIAL; 9981 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 9982 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 9983 } 9984 if (mem == MMU_WRED_UC_QUEUE_TOTAL_COUNT_X_PIPEm || 9985 mem == MMU_WRED_UC_QUEUE_TOTAL_COUNT_Y_PIPEm || 9986 mem == MMU_WRED_PORT_SP_SHARED_COUNT_X_PIPEm || 9987 mem == MMU_WRED_PORT_SP_SHARED_COUNT_Y_PIPEm || 9988 mem == MMU_WRED_QGROUP_SHARED_COUNT_X_PIPEm || 9989 mem == MMU_WRED_QGROUP_SHARED_COUNT_Y_PIPEm) { 9990 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_ENTRY_CLEAR; 9991 } 9992 } 9993 if ((SOC_IS_TRIDENT2X(unit) || SOC_IS_TITAN2PLUS(unit))) { 9994 if (mem == UDF_CONDITIONAL_CHECK_TABLE_CAMm) { 9995 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 9996 } 9997 if (mem == MMU_INTFI_XPIPE_FC_MAP_TBL0m || 9998 mem == MMU_INTFI_XPIPE_FC_MAP_TBL1m || 9999 mem == MMU_INTFI_YPIPE_FC_MAP_TBL0m || 10000 mem == MMU_INTFI_YPIPE_FC_MAP_TBL1m) { 10001 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 10002 skip_mem = 1; 10003 } 10004 } 10005 #endif /* BCM_TRIDENT2_SUPPORT */ 10006 #if defined(BCM_TRIUMPH2_SUPPORT) 10007 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_VALKYRIE2(unit)) { 10008 if (mem == MMU_WRED_THD_0_CELLm || 10009 mem == MMU_WRED_THD_1_CELLm || 10010 mem == MMU_WRED_THD_0_PACKETm || 10011 mem == MMU_WRED_THD_1_PACKETm || 10012 mem == MMU_WRED_PORT_THD_0_CELLm || 10013 mem == MMU_WRED_PORT_THD_1_CELLm || 10014 mem == MMU_WRED_PORT_THD_0_PACKETm || 10015 mem == MMU_WRED_PORT_THD_1_PACKETm ) { 10016 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10017 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10018 } 10019 } 10020 #endif /* BCM_TRIUMPH2_SUPPORT */ 10021 #if defined(BCM_TRIUMPH_SUPPORT) 10022 if (SOC_IS_TRIUMPH(unit)) { 10023 if (mem == L3_DEFIP_DATA_ONLYm) { 10024 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10025 } 10026 if (mem == L3_DEFIP_128m) { 10027 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10028 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10029 } 10030 } 10031 #endif /* BCM_TRIUMPH_SUPPORT */ 10032 #ifdef BCM_VALKYRIE_SUPPORT 10033 if (SOC_IS_VALKYRIE(unit)) { 10034 if (mem == FP_TCAMm || mem == VFP_TCAMm) { 10035 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10036 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10037 } 10038 } 10039 #endif /* BCM_VALKYRIE_SUPPORT */ 10040 #if defined(BCM_SCORPION_SUPPORT) 10041 if (SOC_IS_SCORPION(unit)) { 10042 if (mem == MMU_WRED_THD_0_CELLm || 10043 mem == MMU_WRED_THD_1_CELLm || 10044 mem == MMU_WRED_PORT_THD_0_CELLm || 10045 mem == MMU_WRED_PORT_THD_1_CELLm) { 10046 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10047 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10048 } 10049 } 10050 #endif /* BCM_SCORPION_SUPPORT */ 10051 #if defined(BCM_FIREBOLT2_SUPPORT) 10052 if (SOC_IS_FIREBOLT2(unit)) { 10053 switch(mem) { 10054 case L2Xm: 10055 case L2_ENTRY_ONLYm: 10056 case L3_ENTRY_ONLYm: 10057 case L3_DEFIP_DATA_ONLYm: 10058 case EFP_TCAMm: 10059 case FP_TCAMm: 10060 case VFP_TCAMm: 10061 case L3_TUNNELm: 10062 case VLAN_SUBNETm: 10063 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10064 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10065 break; 10066 case MMU_XQ0m: 10067 case MMU_XQ1m: 10068 case MMU_XQ2m: 10069 case MMU_XQ3m: 10070 case MMU_XQ4m: 10071 case MMU_XQ5m: 10072 case MMU_XQ6m: 10073 case MMU_XQ7m: 10074 case MMU_XQ8m: 10075 case MMU_XQ9m: 10076 case MMU_XQ10m: 10077 case MMU_XQ11m: 10078 case MMU_XQ12m: 10079 case MMU_XQ13m: 10080 case MMU_XQ14m: 10081 case MMU_XQ15m: 10082 case MMU_XQ16m: 10083 case MMU_XQ17m: 10084 case MMU_XQ18m: 10085 case MMU_XQ19m: 10086 case MMU_XQ20m: 10087 case MMU_XQ21m: 10088 case MMU_XQ22m: 10089 case MMU_XQ23m: 10090 case MMU_XQ24m: 10091 case MMU_XQ25m: 10092 case MMU_XQ26m: 10093 case MMU_XQ27m: 10094 case MMU_XQ28m: 10095 case MMU_CCPm: 10096 case MMU_CFAPm: 10097 case MMU_CBPPKTHEADER0m: 10098 case MMU_CBPPKTHEADER1m: 10099 case MMU_CBPCELLHEADERm: 10100 case MMU_CBPDATA0m: 10101 case MMU_CBPDATA1m: 10102 case MMU_CBPDATA2m: 10103 case MMU_CBPDATA3m: 10104 case MMU_CBPDATA4m: 10105 case MMU_CBPDATA5m: 10106 case MMU_CBPDATA6m: 10107 case MMU_CBPDATA7m: 10108 case MMU_CBPDATA8m: 10109 case MMU_CBPDATA9m: 10110 case MMU_CBPDATA10m: 10111 case MMU_CBPDATA11m: 10112 case MMU_CBPDATA12m: 10113 case MMU_CBPDATA13m: 10114 case MMU_CBPDATA14m: 10115 case MMU_CBPDATA15m: 10116 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_ENTRY_CLEAR; 10117 break; 10118 default: 10119 SOC_MEM_INFO(unit, mem).flags &= ~(SOC_MEM_FLAG_CACHABLE | SOC_MEM_SER_FLAGS); 10120 skip_mem = 1; 10121 } 10122 } 10123 #endif /* BCM_FIREBOLT2_SUPPORT */ 10124 #if defined(BCM_TRX_SUPPORT) 10125 if (SOC_IS_TRX(unit)) { 10126 /* Force cache L2 mem */ 10127 if (mem == L2Xm) { 10128 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 10129 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_ENTRY_CLEAR; 10130 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_SPECIAL; 10131 } 10132 if (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE) { 10133 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10134 } 10135 /* Skip caching unused views / views which should not be cached */ 10136 switch(mem) { 10137 case MY_STATION_TCAM_DATA_ONLYm: 10138 case MY_STATION_TCAM_ENTRY_ONLYm: 10139 case L2_USER_ENTRY_DATA_ONLYm: 10140 case L3_DEFIP_DATA_ONLYm: 10141 case L3_DEFIP_PAIR_128_DATA_ONLYm: 10142 case L3_DEFIP_128_DATA_ONLYm: 10143 case L3_DEFIP_128_ONLYm: 10144 case L3_DEFIP_ONLYm: 10145 case L3_DEFIP_PAIR_128_ONLYm: 10146 case L3_ENTRY_ONLYm: 10147 case L2_BULKm: 10148 case L2_LEARN_INSERT_FAILUREm: 10149 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 10150 skip_mem = 1; 10151 break; 10152 default: break; 10153 } 10154 } 10155 #endif /* BCM_TRX_SUPPORT */ 10156 #if defined(BCM_ENDURO_SUPPORT) 10157 if(SOC_IS_ENDURO(unit)) { 10158 if (mem == FP_METER_TABLEm) { 10159 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 10160 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_ENTRY_CLEAR; 10161 } 10162 if (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE) { 10163 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10164 } 10165 } 10166 #endif 10167 #ifdef BCM_TOMAHAWK_SUPPORT 10168 if (SOC_IS_TOMAHAWKX(unit)) { 10169 if (soc_th_check_cache_skip(unit, mem)) { 10170 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 10171 skip_mem = 1; 10172 } 10173 10174 if (mem == MMU_WRED_PORT_SP_SHARED_COUNTm || 10175 mem == MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE0m || 10176 mem == MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE1m || 10177 mem == MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE2m || 10178 mem == MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE3m || 10179 mem == MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE0m || 10180 mem == MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE1m || 10181 mem == MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE2m || 10182 mem == MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE3m) { 10183 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_ENTRY_CLEAR; 10184 } 10185 } 10186 #endif /* BCM_TOMAHAWK_SUPPORT */ 10187 #ifdef BCM_TRIDENT3_SUPPORT 10188 if (SOC_IS_TRIDENT3X(unit)) { 10189 if (soc_trident3_check_cache_skip(unit, mem)) { 10190 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 10191 skip_mem = 1; 10192 } 10193 10194 if (mem == EXACT_MATCH_LOGICAL_TABLE_SELECTm || 10195 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0m || 10196 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1m || 10197 mem == IFP_TCAMm || mem == IFP_TCAM_PIPE0m || 10198 mem == IFP_TCAM_PIPE1m || mem == IFP_TCAM_WIDEm || 10199 mem == IFP_TCAM_WIDE_PIPE0m || mem == IFP_TCAM_WIDE_PIPE1m || 10200 mem == EFP_TCAMm || mem == EFP_TCAM_PIPE0m || 10201 mem == EFP_TCAM_PIPE1m || 10202 mem == EGR_FIELD_EXTRACTION_PROFILE_1_TCAMm || 10203 mem == EGR_FIELD_EXTRACTION_PROFILE_2_TCAMm || 10204 mem == L3_DEFIP_ONLYm || mem == L3_DEFIP_PAIR_128_ONLYm || 10205 mem == EGR_QOS_CTRL_TCAM_ONLYm || mem == PKT_FLOW_SELECT_TCAM_0_ONLYm || 10206 mem == IP_MULTICAST_TCAMm) { 10207 SOC_MEM_INFO(unit,mem).flags |= SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 10208 } 10209 10210 if (mem == TCB_THRESHOLD_PROFILE_MAPm || 10211 mem == TCB_THRESHOLD_PROFILE_MAP_XPE0m || 10212 mem == TCB_THRESHOLD_PROFILE_MAP_Am || 10213 mem == TCB_THRESHOLD_PROFILE_MAP_A_XPE0m || 10214 mem == TCB_THRESHOLD_PROFILE_MAP_Bm || 10215 mem == TCB_THRESHOLD_PROFILE_MAP_B_XPE0m) { 10216 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10217 } 10218 10219 /* Overwrite the SER_RESPONSE from ECC_PARITY to CACHE_RESTORE*/ 10220 if (mem == IP_PARSER0_HME_STAGE_TCAM_ONLY_0m || 10221 mem == IP_PARSER1_HME_STAGE_TCAM_ONLY_0m || 10222 mem == IP_PARSER1_HME_STAGE_TCAM_ONLY_1m || 10223 mem == IP_PARSER1_HME_STAGE_TCAM_NARROW_ONLY_2m || 10224 mem == IP_PARSER1_HME_STAGE_TCAM_ONLY_3m || 10225 mem == IP_PARSER1_HME_STAGE_TCAM_ONLY_4m || 10226 mem == IP_PARSER2_HME_STAGE_TCAM_ONLY_0m || 10227 mem == IP_PARSER2_HME_STAGE_TCAM_ONLY_1m || 10228 mem == IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_2m || 10229 mem == IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_3m || 10230 mem == IP_PARSER2_HME_STAGE_TCAM_ONLY_4m || 10231 mem == FORWARDING_1_LOGICAL_TBL_SEL_TCAMm || 10232 mem == FORWARDING_2_LOGICAL_TBL_SEL_TCAMm || 10233 mem == FORWARDING_3_LOGICAL_TBL_SEL_TCAMm || 10234 mem == TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAMm || 10235 mem == TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAMm || 10236 mem == TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAMm || 10237 mem == TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAMm || 10238 mem == EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAMm || 10239 mem == EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAMm) { 10240 SOC_MEM_INFO(unit,mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10241 } 10242 10243 #ifdef BCM_HELIX5_SUPPORT 10244 if (mem == BSK_FTFP_TCAMm || 10245 mem == BSK_FTFP_LTS_LOGICAL_TBL_SEL_TCAMm) { 10246 SOC_MEM_INFO(unit,mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10247 } 10248 10249 if (mem == BSC_AG_AGE_TABLEm) { 10250 /* R/O Table */ 10251 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_ECC_CORRECTABLE; 10252 } 10253 #endif 10254 if (mem == SFLOW_ING_DATA_SOURCEm || 10255 mem == EGR_SEQUENCE_NUMBER_TABLEm) { 10256 SOC_MEM_INFO(unit,mem).flags &= ~SOC_MEM_FLAG_SER_ECC_CORRECTABLE; 10257 SOC_MEM_INFO(unit,mem).flags |= SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 10258 } 10259 10260 if (mem == TCB_THRESHOLD_PROFILE_MAPm || 10261 mem == TCB_THRESHOLD_PROFILE_MAP_XPE0m) { 10262 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_ENTRY_CLEAR; 10263 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_ECC_CORRECTABLE; 10264 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10265 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10266 } 10267 10268 if (NUM_PIPE(unit) == 1) { 10269 if (mem == L2_ENTRY_LPm || mem == L3_ENTRY_LPm || 10270 mem == EXACT_MATCH_LPm || mem == EXACT_MATCH_LP_PIPE0m || 10271 mem == MPLS_ENTRY_LPm || 10272 mem == VLAN_XLATE_1_LPm || mem == VLAN_XLATE_2_LPm || 10273 mem == EGR_VLAN_XLATE_1_LPm || mem == EGR_VLAN_XLATE_2_LPm) { 10274 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_ENTRY_CLEAR; 10275 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_ECC_CORRECTABLE; 10276 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_CACHE_RESTORE; 10277 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 10278 SOC_MEM_INFO(unit,mem).flags |= SOC_MEM_FLAG_SER_SPECIAL; 10279 } 10280 } 10281 } 10282 #endif 10283 #ifdef BCM_TOMAHAWK2_SUPPORT 10284 if (SOC_IS_TOMAHAWK2(unit)) { 10285 if (mem == EFP_TCAMm || mem == EFP_TCAM_PIPE0m || 10286 mem == EFP_TCAM_PIPE1m || mem == EFP_TCAM_PIPE2m || 10287 mem == EFP_TCAM_PIPE3m || mem == VFP_TCAMm || 10288 mem == VFP_TCAM_PIPE0m || mem == VFP_TCAM_PIPE1m || 10289 mem == VFP_TCAM_PIPE2m || mem == VFP_TCAM_PIPE3m || 10290 mem == IFP_TCAMm || mem == IFP_TCAM_PIPE0m || 10291 mem == IFP_TCAM_PIPE1m || mem == IFP_TCAM_PIPE2m || 10292 mem == IFP_TCAM_PIPE3m || mem == IP_MULTICAST_TCAMm || 10293 mem == FP_UDF_TCAMm || mem == FP_UDF_TCAM_PIPE0m || 10294 mem == FP_UDF_TCAM_PIPE1m || mem == FP_UDF_TCAM_PIPE2m || 10295 mem == FP_UDF_TCAM_PIPE3m || mem == IFP_TCAM_WIDEm || 10296 mem == IFP_TCAM_WIDE_PIPE0m || mem == IFP_TCAM_WIDE_PIPE1m || 10297 mem == IFP_TCAM_WIDE_PIPE2m || mem == IFP_TCAM_WIDE_PIPE3m || 10298 mem == CPU_COS_MAPm || mem == EXACT_MATCH_LOGICAL_TABLE_SELECTm) { 10299 SOC_MEM_INFO(unit,mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10300 } 10301 10302 if (soc_feature(unit, soc_feature_tcam_scan_engine) && 10303 (mem == VFP_TCAMm || mem == VFP_TCAM_PIPE0m || 10304 mem == VFP_TCAM_PIPE1m || mem == VFP_TCAM_PIPE2m || 10305 mem == VFP_TCAM_PIPE3m)) { 10306 SOC_MEM_INFO(unit,mem).flags &= ~SOC_MEM_FLAG_SER_CACHE_RESTORE; 10307 SOC_MEM_INFO(unit,mem).flags |= SOC_MEM_FLAG_SER_SPECIAL; 10308 } 10309 10310 if (mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPERm || 10311 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED0_PIPE0m || 10312 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED0_PIPE1m || 10313 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED0_PIPE2m || 10314 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED0_PIPE3m || 10315 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED1_PIPE0m || 10316 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED1_PIPE1m || 10317 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED1_PIPE2m || 10318 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED1_PIPE3m || 10319 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWERm || 10320 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED0_PIPE0m || 10321 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED0_PIPE1m || 10322 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED0_PIPE2m || 10323 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED0_PIPE3m || 10324 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED1_PIPE0m || 10325 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED1_PIPE1m || 10326 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED1_PIPE2m || 10327 mem == MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED1_PIPE3m || 10328 mem == MMU_TCB_BUFFER_CELL_DATA_UPPERm || 10329 mem == MMU_TCB_BUFFER_CELL_DATA_UPPER_XPE0m || 10330 mem == MMU_TCB_BUFFER_CELL_DATA_UPPER_XPE1m || 10331 mem == MMU_TCB_BUFFER_CELL_DATA_UPPER_XPE2m || 10332 mem == MMU_TCB_BUFFER_CELL_DATA_UPPER_XPE3m || 10333 mem == MMU_TCB_BUFFER_CELL_DATA_LOWERm || 10334 mem == MMU_TCB_BUFFER_CELL_DATA_LOWER_XPE0m || 10335 mem == MMU_TCB_BUFFER_CELL_DATA_LOWER_XPE1m || 10336 mem == MMU_TCB_BUFFER_CELL_DATA_LOWER_XPE2m || 10337 mem == MMU_TCB_BUFFER_CELL_DATA_LOWER_XPE3m) { 10338 SOC_MEM_INFO(unit,mem).flags |= SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP; 10339 } 10340 10341 if (mem == TCB_THRESHOLD_PROFILE_MAPm || 10342 mem == TCB_THRESHOLD_PROFILE_MAP_XPE0m || 10343 mem == TCB_THRESHOLD_PROFILE_MAP_XPE1m || 10344 mem == TCB_THRESHOLD_PROFILE_MAP_XPE2m || 10345 mem == TCB_THRESHOLD_PROFILE_MAP_XPE3m) { 10346 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_ENTRY_CLEAR; 10347 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10348 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10349 } 10350 } 10351 #endif 10352 #if defined(BCM_TOMAHAWK3_SUPPORT) 10353 if (SOC_IS_TOMAHAWK3(unit)) { 10354 if (mem == MMU_EBMB_PAYLOAD_SLICEm || mem == MMU_EBMB_CCBE_SLICEm || 10355 mem == MMU_EBMB_CCBE_SERm || mem == MMU_EBMB_CCBE_SER_PIPE0m|| 10356 mem == MMU_EBMB_CCBE_SER_PIPE1m || mem == MMU_EBMB_CCBE_SER_PIPE2m || 10357 mem == MMU_EBMB_CCBE_SER_PIPE3m || mem == MMU_EBMB_CCBE_SER_PIPE4m || 10358 mem == MMU_EBMB_CCBE_SER_PIPE5m || mem == MMU_EBMB_CCBE_SER_PIPE6m || 10359 mem == MMU_EBMB_CCBE_SER_PIPE7m || mem == MMU_EBMB_PAYLOAD_ITM0_CH0_SERm || 10360 mem == MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE0m || mem == MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE1m || 10361 mem == MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE2m || mem == MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE3m || 10362 mem == MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE4m || mem == MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE5m || 10363 mem == MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE6m || mem == MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE7m || 10364 mem == MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE0m || mem == MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE1m || 10365 mem == MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE2m || mem == MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE3m || 10366 mem == MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE4m || mem == MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE5m || 10367 mem == MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE6m || mem == MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE7m || 10368 mem == MMU_EBMB_PAYLOAD_ITM0_CH1_SERm || mem == MMU_EBMB_PAYLOAD_ITM1_CH1_SERm || 10369 mem == MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE0m || mem == MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE1m || 10370 mem == MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE2m || mem == MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE3m || 10371 mem == MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE4m || mem == MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE5m || 10372 mem == MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE6m || mem == MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE7m || 10373 mem == MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE0m || mem == MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE1m || 10374 mem == MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE2m || mem == MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE3m || 10375 mem == MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE4m || mem == MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE5m || 10376 mem == MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE6m || mem == MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE7m || 10377 mem == MMU_MB_PAYLOAD_SER_CH0m || mem == MMU_MB_PAYLOAD_SER_CH0_ITM0m || 10378 mem == MMU_MB_PAYLOAD_SER_CH0_ITM1m || mem == MMU_MB_PAYLOAD_SER_CH1m || 10379 mem == MMU_MB_PAYLOAD_SER_CH1_ITM0m || mem == MMU_MB_PAYLOAD_SER_CH1_ITM1m || 10380 mem == MMU_MB_PAYLOAD_SER_CH2m || mem == MMU_MB_PAYLOAD_SER_CH2_ITM0m || 10381 mem == MMU_MB_PAYLOAD_SER_CH2_ITM1m || mem == MMU_MB_PAYLOAD_SER_CH3m || 10382 mem == MMU_MB_PAYLOAD_SER_CH3_ITM0m || mem == MMU_MB_PAYLOAD_SER_CH3_ITM1m) { 10383 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_VALID; 10384 } 10385 10386 if (mem == EFP_TCAMm || mem == EFP_TCAM_PIPE0m || 10387 mem == EFP_TCAM_PIPE1m || mem == EFP_TCAM_PIPE2m || 10388 mem == EFP_TCAM_PIPE3m || mem == EFP_TCAM_PIPE4m || 10389 mem == EFP_TCAM_PIPE5m || mem == EFP_TCAM_PIPE6m || 10390 mem == EFP_TCAM_PIPE7m || mem == VFP_TCAMm || 10391 mem == VFP_TCAM_PIPE0m || mem == VFP_TCAM_PIPE1m || 10392 mem == VFP_TCAM_PIPE2m || mem == VFP_TCAM_PIPE3m || 10393 mem == VFP_TCAM_PIPE4m || mem == VFP_TCAM_PIPE5m || 10394 mem == VFP_TCAM_PIPE6m || mem == VFP_TCAM_PIPE7m || 10395 mem == IFP_TCAMm || mem == IFP_TCAM_PIPE0m || 10396 mem == IFP_TCAM_PIPE1m || mem == IFP_TCAM_PIPE2m || 10397 mem == IFP_TCAM_PIPE3m || mem == IFP_TCAM_PIPE4m || 10398 mem == IFP_TCAM_PIPE5m || mem == IFP_TCAM_PIPE6m || 10399 mem == IFP_TCAM_PIPE7m || mem == L3_DEFIP_TCAM_LEVEL1m || 10400 mem == FP_UDF_TCAMm || mem == FP_UDF_TCAM_PIPE0m || 10401 mem == FP_UDF_TCAM_PIPE1m || mem == FP_UDF_TCAM_PIPE2m || 10402 mem == FP_UDF_TCAM_PIPE3m || mem == FP_UDF_TCAM_PIPE4m || 10403 mem == FP_UDF_TCAM_PIPE5m || mem == FP_UDF_TCAM_PIPE6m || 10404 mem == FP_UDF_TCAM_PIPE7m || mem == L2_USER_ENTRY_ONLYm || 10405 mem == MY_STATION_TCAM_ENTRY_ONLYm || 10406 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLYm || 10407 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE0m || 10408 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE1m || 10409 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE2m || 10410 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE3m || 10411 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE4m || 10412 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE5m || 10413 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE6m || 10414 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE7m || 10415 mem == EXACT_MATCH_LOGICAL_TABLE_SELECTm || 10416 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0m || 10417 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1m || 10418 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2m || 10419 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3m || 10420 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE4m || 10421 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE5m || 10422 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE6m || 10423 mem == EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE7m || 10424 mem == IFP_LOGICAL_TABLE_SELECTm || 10425 mem == IFP_LOGICAL_TABLE_SELECT_PIPE0m || 10426 mem == IFP_LOGICAL_TABLE_SELECT_PIPE1m || 10427 mem == IFP_LOGICAL_TABLE_SELECT_PIPE2m || 10428 mem == IFP_LOGICAL_TABLE_SELECT_PIPE3m || 10429 mem == IFP_LOGICAL_TABLE_SELECT_PIPE4m || 10430 mem == IFP_LOGICAL_TABLE_SELECT_PIPE5m || 10431 mem == IFP_LOGICAL_TABLE_SELECT_PIPE6m || 10432 mem == IFP_LOGICAL_TABLE_SELECT_PIPE7m || 10433 mem == IFP_LOGICAL_TABLE_SELECT_TCAM_ONLYm || 10434 mem == IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE0m || 10435 mem == IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE1m || 10436 mem == IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE2m || 10437 mem == IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE3m || 10438 mem == IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE4m || 10439 mem == IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE5m || 10440 mem == IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE6m || 10441 mem == IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE7m || 10442 mem == CPU_COS_MAPm || mem == CPU_COS_MAP_ONLYm) { 10443 SOC_MEM_INFO(unit,mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10444 } 10445 10446 if (mem == L3_TUNNEL_SINGLEm || mem == L3_TUNNEL_DOUBLEm || 10447 mem == L3_TUNNEL_QUADm || mem == L3_TUNNEL_ECCm || 10448 mem == MPLS_ENTRY_SINGLEm || mem == MPLS_ENTRY_ECCm) { 10449 SOC_MEM_INFO(unit,mem).flags &= ~SOC_MEM_FLAG_SER_SPECIAL; 10450 SOC_MEM_INFO(unit,mem).flags |= SOC_MEM_FLAG_SER_CACHE_RESTORE; 10451 } 10452 10453 if (mem == MMU_QSCH_L0_WEIGHT_MEMm || mem == MMU_QSCH_L1_WEIGHT_MEMm || 10454 mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE0m || mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE1m || 10455 mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE2m || mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE3m || 10456 mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE4m || mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE5m || 10457 mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE6m || mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE7m || 10458 mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE0m || mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE1m || 10459 mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE2m || mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE3m || 10460 mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE4m || mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE5m || 10461 mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE6m || mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE7m) { 10462 SOC_MEM_INFO(unit,mem).null_entry = _soc_mem_entry_reset_value; 10463 } 10464 } 10465 #endif 10466 10467 #if !defined(SOC_NO_NAMES) 10468 #if defined(BCM_ESW_SUPPORT) || \ 10469 defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) 10470 if (chk_skip_cache) { 10471 /* coverity[secure_coding] */ 10472 sal_strcpy(mem_name, "mem_nocache_"); 10473 mptr = &mem_name[sal_strlen(mem_name)]; 10474 sal_strcpy(mptr, SOC_MEM_NAME(unit, mem)); 10475 if (soc_property_get(unit, mem_name, 0)) { 10476 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 10477 skip_mem = 1; 10478 } 10479 #ifdef BCM_TRIDENT2_SUPPORT 10480 if (SOC_IS_TD2_TT2(unit) && (NUM_PIPE(unit) != 1)) { 10481 if (mem == L3_DEFIP_ALPM_IPV4m || mem == L3_DEFIP_ALPM_IPV4_1m || 10482 mem == L3_DEFIP_ALPM_IPV6_64m || mem == L3_DEFIP_ALPM_IPV6_64_1m || 10483 mem == L3_DEFIP_ALPM_IPV6_128m || mem == L3_DEFIPm || 10484 mem == L3_DEFIP_PAIR_128m || mem == L3_DEFIP_AUX_TABLEm) { 10485 /* 10486 * ALPM tables are not cached by default. 10487 * To avoid impacting the existing behavior, cache should be 10488 * enabled explicitly with mem_nocache_xxx=0. 10489 */ 10490 if (!soc_property_get(unit, mem_name, 1)) { 10491 SOC_MEM_INFO(unit, mem).flags &= 10492 ~SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 10493 SOC_MEM_INFO(unit, mem).flags &= 10494 ~SOC_MEM_FLAG_SER_ECC_CORRECTABLE; 10495 SOC_MEM_INFO(unit, mem).flags |= 10496 SOC_MEM_FLAG_SER_CACHE_RESTORE; 10497 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_CACHABLE; 10498 skip_mem = 0; 10499 } 10500 } 10501 } 10502 #endif /* BCM_TRIDENT2_SUPPORT */ 10503 } 10504 #endif 10505 10506 #if defined(BCM_ESW_SUPPORT) 10507 if (SOC_IS_ESW(unit)) { 10508 /* coverity[secure_coding] */ 10509 sal_strcpy(mem_name, "mem_parity_enable_skip_"); 10510 mptr = &mem_name[sal_strlen(mem_name)]; 10511 sal_strcpy(mptr, SOC_MEM_NAME(unit, mem)); 10512 if (soc_property_get(unit, mem_name, 0)) { 10513 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP; 10514 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "parity_en_skip=1: for mem %s \n"), SOC_MEM_NAME(unit, mem))); 10515 #if defined(SOC_UNIQUE_ACC_TYPE_ACCESS) 10516 if (soc_feature(unit, soc_feature_unique_acc_type_access) && 10517 (SOC_MEM_UNIQUE_ACC(unit, mem) != NULL)) { 10518 int pipe; 10519 soc_mem_t mem_p; 10520 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 10521 mem_p = SOC_MEM_UNIQUE_ACC(unit, mem)[pipe]; 10522 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "parity_en_skip=1: for mem %s \n"), SOC_MEM_NAME(unit, mem_p))); 10523 SOC_MEM_INFO(unit, mem_p).flags |= SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP; 10524 } 10525 } 10526 #endif /* SOC_UNIQUE_ACC_TYPE_ACCESS */ 10527 } 10528 } 10529 #endif 10530 #endif /* !SOC_NO_NAMES */ 10531 #ifdef BCM_KATANA_SUPPORT 10532 if (SOC_IS_KATANAX(unit)) { 10533 if(mem == XPORT_WC_UCMEM_DATAm) { 10534 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_ECC_CORRECTABLE; 10535 skip_mem = 1; 10536 } 10537 } 10538 #endif 10539 10540 #ifdef BCM_SABER2_SUPPORT 10541 if (SOC_IS_SABER2(unit)) { 10542 if ((mem == LLS_L1_CONFIGm) || (mem == LLS_L0_CONFIGm)) { 10543 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 10544 skip_mem = 1; 10545 } 10546 } 10547 #endif 10548 10549 10550 #if defined(BCM_APACHE_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 10551 if (SOC_IS_APACHE(unit) || (SOC_IS_TRIDENT3X(unit) && NUM_PIPE(unit) == 1)) { 10552 if ((mem == LLS_S1_CONFIGm) || (mem == LLS_L1_CONFIGm) || (mem == LLS_L0_CONFIGm) || (mem == MMU_ENQ_PBI_DBm)) { 10553 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 10554 skip_mem = 1; 10555 } 10556 if (mem == L3_DEFIP_ALPM_IPV4m || mem == L3_DEFIP_ALPM_IPV4_1m || 10557 mem == L3_DEFIP_ALPM_IPV6_64m || mem == L3_DEFIP_ALPM_IPV6_64_1m || 10558 mem == L3_DEFIP_ALPM_IPV6_128m || mem == L3_DEFIP_ALPM_RAWm || 10559 mem == L3_DEFIPm || mem == L3_DEFIP_PAIR_128m || 10560 mem == L3_DEFIP_AUX_TABLEm) { 10561 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_SER_SPECIAL; 10562 if (soc_feature(unit, soc_feature_alpm) && 10563 soc_property_get(unit, spn_L3_ALPM_ENABLE, 0)) { 10564 SOC_MEM_INFO(unit, mem).flags &= 10565 ~SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 10566 SOC_MEM_INFO(unit, mem).flags |= 10567 SOC_MEM_FLAG_SER_CACHE_RESTORE; 10568 } else { 10569 SOC_MEM_INFO(unit, mem).flags |= 10570 SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 10571 } 10572 } 10573 } 10574 #endif 10575 #if defined(BCM_MONTEREY_SUPPORT) 10576 if (SOC_IS_MONTEREY(unit)) { 10577 if (mem == MMU_MAPPER_X_LSBm) { 10578 skip_mem = 1; 10579 } 10580 } 10581 #endif 10582 if (soc_feature(unit, soc_feature_alpm2) && 10583 soc_property_get(unit, spn_L3_ALPM_ENABLE, 0)) { 10584 if (mem == L3_DEFIP_LEVEL1m || 10585 mem == L3_DEFIP_PAIR_LEVEL1m || 10586 mem == L3_DEFIP_ALPM_LEVEL2m || 10587 mem == L3_DEFIP_ALPM_LEVEL3m || 10588 mem == L3_DEFIP_ALPM_LEVEL2_HIT_ONLYm || 10589 mem == L3_DEFIP_ALPM_LEVEL3_HIT_ONLYm || 10590 mem == L3_DEFIP_LEVEL1_HIT_ONLYm || 10591 mem == L3_DEFIPm || 10592 mem == L3_DEFIP_PAIR_128m || 10593 mem == L3_DEFIP_ALPM_RAWm || 10594 mem == L3_DEFIP_ALPM_HIT_ONLYm || 10595 mem == L3_DEFIP_HIT_ONLYm || 10596 mem == L3_DEFIP_PAIR_128_HIT_ONLYm) { 10597 skip_mem = 0; 10598 SOC_MEM_INFO(unit, mem).flags &= 10599 ~SOC_MEM_FLAG_SER_SPECIAL; 10600 SOC_MEM_INFO(unit, mem).flags &= 10601 ~SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE; 10602 SOC_MEM_INFO(unit, mem).flags |= 10603 SOC_MEM_FLAG_SER_CACHE_RESTORE; 10604 SOC_MEM_INFO(unit, mem).flags |= 10605 SOC_MEM_FLAG_CACHABLE; 10606 } 10607 } 10608 10609 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 10610 /* Skipping MMU_ENQ_PBI_DBm, as there is no easy way to not read 10611 * this memory until the ingress traffic has been disabled Hence 10612 * skipping the Memory */ 10613 if (SOC_IS_TD2P_TT2P(unit)) { 10614 if (mem == MMU_ENQ_PBI_DBm) { 10615 SOC_MEM_INFO(unit, mem).flags &= ~SOC_MEM_FLAG_CACHABLE; 10616 skip_mem = 1; 10617 } 10618 } 10619 #endif /* BCM_TRIDENT2PLUS_SUPPORT */ 10620 10621 /* Enable cache only if all criteria's are met */ 10622 if (cache && !skip_mem && 10623 ((SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_CACHE_RESTORE) || 10624 (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE) || 10625 ((SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_CACHABLE) && 10626 ((SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_ECC_CORRECTABLE) || 10627 (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_SPECIAL))))) { 10628 SOC_IF_ERROR_RETURN(soc_mem_cache_set(unit, mem, MEM_BLOCK_ALL, TRUE)); 10629 #if defined(BCM_ESW_SUPPORT) 10630 if (soc_mem_is_dynamic(unit, mem)) { 10631 SOC_MEM_INFO(unit, mem).flags |= SOC_MEM_FLAG_DYNAMIC; 10632 } 10633 #endif 10634 #ifdef BCM_WARM_BOOT_SUPPORT 10635 SOC_IF_ERROR_RETURN(soc_mem_cache_scache_load(unit, mem, &offset)); 10636 #endif 10637 } else { 10638 SOC_IF_ERROR_RETURN(soc_mem_cache_set(unit, mem, MEM_BLOCK_ALL, FALSE)); 10639 } 10640 } 10641 #if defined(BCM_XGS_SUPPORT) 10642 if (soc_feature(unit, soc_feature_regs_as_mem) && 10643 soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 10644 SOC_IF_ERROR_RETURN(soc_ser_reg_cache_init(unit)); 10645 } 10646 #endif /* BCM_XGS_SUPPORT */ 10647 10648 /***********************************************************************/ 10649 /* Configure CMIC PCI registers correctly for driver operation. */ 10650 /* */ 10651 /* NOTE: When interrupt driven, the internal SOC registers cannot */ 10652 /* be accessed until the CMIC interrupts are enabled. */ 10653 /***********************************************************************/ 10654 10655 if (!SAL_BOOT_PLISIM && !SOC_WARM_BOOT(unit) && !SOC_IS_RCPU_UNIT(unit)) { 10656 #ifdef BCM_CMICX_SUPPORT 10657 uint32 valid; 10658 SOC_IF_ERROR_RETURN(soc_pcie_fw_status_get(unit, &valid)); 10659 if(!valid) { 10660 LOG_ERROR(BSL_LS_SOC_COMMON, 10661 (BSL_META_U(unit, 10662 "PCIe firware was not loaded on unit %d\n"), unit)); 10663 return SOC_E_INIT; 10664 } 10665 #endif 10666 /* 10667 * Check that PCI memory space is mapped correctly by running a 10668 * quick diagnostic on the S-Channel message buffer. 10669 */ 10670 10671 SOC_IF_ERROR_RETURN(soc_pci_test(unit)); 10672 } 10673 10674 if (!SOC_IS_RCPU_ONLY(unit)) { 10675 /* 10676 * Adjust the CMIC CONFIG register 10677 */ 10678 #ifdef BCM_CMICM_SUPPORT 10679 if(soc_feature(unit, soc_feature_cmicm)) { 10680 if (SAL_BOOT_PLISIM) { 10681 /* Set interrupt polarity to active high */ 10682 } 10683 } else 10684 #endif 10685 #ifdef BCM_CMICX_SUPPORT 10686 if (soc_feature(unit, soc_feature_cmicx)) { 10687 /* Do Nothing; prevent incorrect register access */ 10688 } else 10689 #endif 10690 { 10691 reg = soc_pci_read(unit, CMIC_CONFIG); 10692 10693 /* 10694 * Enable enhanced DMA modes: 10695 * Scatter/gather, reload, and unaligned transfers 10696 * 10697 * Enable read and write bursts. 10698 * Note: very fast CPUs (above ~500 MHz) may combine multiple 10699 * memory operations into bursts. The CMIC will hang if burst 10700 * operations are not enabled. 10701 */ 10702 10703 reg |= (CC_SG_OPN_EN | CC_RLD_OPN_EN | CC_ALN_OPN_EN | 10704 CC_RD_BRST_EN | CC_WR_BRST_EN); 10705 10706 if (SAL_BOOT_PLISIM) { 10707 /* Set interrupt polarity to active high */ 10708 reg &= ~CC_ACT_LOW_INT; 10709 } 10710 10711 #ifdef BCM_XGS_SWITCH_SUPPORT 10712 if (SOC_IS_XGS_SWITCH(unit) && 10713 !soc_property_get(unit, spn_MDIO_EXTERNAL_MASTER, 0)) { 10714 reg |= CC_EXT_MDIO_MSTR_DIS; 10715 } 10716 #endif 10717 10718 soc_pci_write(unit, CMIC_CONFIG, reg); 10719 } 10720 10721 /* 10722 * Configure DMA channels. 10723 */ 10724 /* soc_dma_init will be invoked in soc_dma_attach */ 10725 if ((rv = soc_dma_attach(unit, reset)) < 0) { 10726 LOG_ERROR(BSL_LS_SOC_COMMON, 10727 (BSL_META_U(unit, 10728 "Packet DMA attach failed\n"))); 10729 return SOC_E_INTERNAL; 10730 } 10731 10732 } /* !SOC_IS_RCPU_ONLY(unit) */ 10733 10734 #ifdef BCM_CMICM_SUPPORT 10735 if (soc_feature(unit, soc_feature_cmicm)) { 10736 int i, j; 10737 int numq = 0, cmc_numq; 10738 10739 10740 /* Enable PCI Bus Error and Parity Error Interrupts */ 10741 /* soc_intr_enable(unit, IRQ_PCI_PARITY_ERR | IRQ_PCI_FATAL_ERR); */ 10742 /* S-Channel Error Interrupt */ 10743 /* soc_intr_enable(unit, IRQ_SCHAN_ERR); */ 10744 /* Link status updates */ 10745 if (!SOC_IS_RCPU_ONLY(unit)) { 10746 soc_cmicm_intr1_enable(unit, IRQ_CMCx_LINK_STAT_MOD); 10747 } 10748 10749 soc_cmic_uc_msg_init(unit); /* Init the uC area */ 10750 10751 for (i = 0; i < SOC_CMCS_NUM(unit); i++) { 10752 /* Clear the CPU & ARM queues */ 10753 SHR_BITCLR_RANGE(CPU_ARM_QUEUE_BITMAP(unit, i), 10754 0, NUM_CPU_COSQ(unit)); 10755 if (i == SOC_PCI_CMC(unit)) { 10756 NUM_CPU_ARM_COSQ(unit, i) = 10757 soc_property_uc_get(unit, 0, spn_NUM_QUEUES, 10758 NUM_CPU_COSQ(unit)); 10759 } else { 10760 /* Properties presume it is PCI for first CMC, then the UC's */ 10761 j = (i < SOC_PCI_CMC(unit)) ? (i + 1) : i; 10762 NUM_CPU_ARM_COSQ(unit, i) = 10763 soc_property_uc_get(unit, j, spn_NUM_QUEUES, 0); 10764 } 10765 10766 cmc_numq = NUM_CPU_ARM_COSQ(unit, i); 10767 SHR_BITSET_RANGE(CPU_ARM_QUEUE_BITMAP(unit, i), 10768 numq, cmc_numq); 10769 numq += cmc_numq; 10770 10771 if (numq > NUM_CPU_COSQ(unit)) { 10772 LOG_WARN(BSL_LS_SOC_COMMON, 10773 (BSL_META_U(unit, 10774 "soc_do_init: total cpu and arm cosq %04x unexpected\n"), 10775 numq)); 10776 } 10777 } 10778 } else 10779 #endif /* CMICM Support */ 10780 #ifdef BCM_CMICX_SUPPORT 10781 if (soc_feature(unit, soc_feature_cmicx)) { 10782 int i, j; 10783 int numq = 0, cmc_numq; 10784 10785 SOC_IF_ERROR_RETURN(soc_cmicx_uc_msg_init(unit)); /* Init the uC area */ 10786 10787 for (i = 0; i < SOC_CMCS_NUM(unit); i++) { 10788 /* Clear the CPU & ARM queues */ 10789 SHR_BITCLR_RANGE(CPU_ARM_QUEUE_BITMAP(unit, i), 10790 0, NUM_CPU_COSQ(unit)); 10791 if (i == SOC_PCI_CMC(unit)) { 10792 NUM_CPU_ARM_COSQ(unit, i) = 10793 soc_property_uc_get(unit, 0, spn_NUM_QUEUES, 10794 NUM_CPU_COSQ(unit)); 10795 } else { 10796 /* Properties presume it is PCI for first CMC, then the UC's */ 10797 j = (i < SOC_PCI_CMC(unit)) ? (i + 1) : i; 10798 NUM_CPU_ARM_COSQ(unit, i) = 10799 soc_property_uc_get(unit, j, spn_NUM_QUEUES, 0); 10800 } 10801 10802 cmc_numq = NUM_CPU_ARM_COSQ(unit, i); 10803 SHR_BITSET_RANGE(CPU_ARM_QUEUE_BITMAP(unit, i), 10804 numq, cmc_numq); 10805 numq += cmc_numq; 10806 10807 if (numq > NUM_CPU_COSQ(unit)) { 10808 LOG_WARN(BSL_LS_SOC_COMMON, 10809 (BSL_META_U(unit, 10810 "soc_do_init: total cpu and arm cosq %04x unexpected\n"), 10811 numq)); 10812 } 10813 } 10814 } else 10815 #endif /* CMICX Support */ 10816 10817 { 10818 if (!SOC_IS_RCPU_ONLY(unit)) { 10819 10820 /* 10821 * PCI Bus Error and Parity Error Interrupts 10822 */ 10823 soc_intr_enable(unit, IRQ_PCI_PARITY_ERR | IRQ_PCI_FATAL_ERR); 10824 10825 /* 10826 * S-Channel Error Interrupt 10827 */ 10828 soc_intr_enable(unit, IRQ_SCHAN_ERR); 10829 10830 /* 10831 * S-Channel Operation Complete Interrupt. 10832 * This interrupt is enabled in soc_schan_op(). 10833 * 10834 * The SCH_MSG_DONE bit must be cleared after chip reset, since it 10835 * defaults to 1. Otherwise, the interrupt will occur as soon as 10836 * it's enabled. 10837 */ 10838 soc_pci_write(unit, CMIC_SCHAN_CTRL, SC_MSG_DONE_CLR); 10839 /* 10840 * MIIM Operation Complete Interrupt 10841 * This interrupt is enabled in cmic_miim_read/write(). 10842 * 10843 * The SCH_MIIM_OP_DONE bit must be cleared after chip reset, since 10844 * it defaults to 1. Otherwise, the interrupt will occur as soon as 10845 * it's enabled. 10846 */ 10847 soc_pci_write(unit, CMIC_SCHAN_CTRL, SC_MIIM_OP_DONE_CLR); 10848 10849 /* 10850 * Link status updates 10851 */ 10852 10853 soc_intr_enable(unit, IRQ_LINK_STAT_MOD); 10854 10855 } /* !SOC_IS_RCPU_ONLY(unit) */ 10856 } 10857 10858 soc->soc_flags |= SOC_F_INITED; 10859 10860 if (!SOC_IS_RCPU_ONLY(unit)) { 10861 10862 /***********************************************************************/ 10863 /* It is legal to access SOC internal registers beyond this point. */ 10864 /* */ 10865 /* HOWEVER: */ 10866 /* */ 10867 /* This init routine should perform the utter minimum necessary. */ 10868 /* soc_misc_init() and soc_mmu_init() are used for further init. */ 10869 /***********************************************************************/ 10870 10871 #ifdef BCM_TRIUMPH_SUPPORT 10872 if (SOC_IS_TRIUMPH(unit) || SOC_IS_TRIUMPH2(unit)) { 10873 /* BP needs to be disabled for register tests to pass */ 10874 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, AUX_ARB_CONTROL_2r, 10875 REG_PORT_ANY, ESM_BP_ENABLEf, 0)); 10876 } 10877 #endif 10878 #ifdef BCM_TRIUMPH2_SUPPORT 10879 /* Make BIGMAC registers accesible for Triumph2, Apollo and Enduro */ 10880 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 10881 SOC_IS_VALKYRIE2(unit) || SOC_IS_ENDURO(unit) || SOC_IS_HURRICANE(unit)) { 10882 soc_port_t port; 10883 uint64 mac_ctrl; 10884 PBMP_PORT_ITER(unit, port) { 10885 if (!IS_HG_PORT(unit, port) && !IS_XE_PORT(unit, port)) { 10886 continue; 10887 } 10888 SOC_IF_ERROR_RETURN(READ_MAC_CTRLr(unit, port, &mac_ctrl)); 10889 soc_reg64_field32_set(unit, MAC_CTRLr, &mac_ctrl, TXRESETf, 0); 10890 soc_reg64_field32_set(unit, MAC_CTRLr, &mac_ctrl, RXRESETf, 0); 10891 SOC_IF_ERROR_RETURN(WRITE_MAC_CTRLr(unit, port, mac_ctrl)); 10892 } 10893 } 10894 #endif 10895 #ifdef BCM_SHADOW_SUPPORT 10896 /* Make sure registers which are actually memories in HW are reset */ 10897 /* Also make the XMAC registers accesible */ 10898 if (SOC_IS_SHADOW(unit)) { 10899 uint32 rval = 0; 10900 soc_port_t port; 10901 PBMP_PORT_ITER(unit, port) { 10902 if (!IS_HG_PORT(unit, port) && !IS_XE_PORT(unit, port) && 10903 !IS_SCH_PORT(unit,port)) { 10904 continue; 10905 } 10906 SOC_IF_ERROR_RETURN(READ_XLPORT_XMAC_CONTROLr(unit, port, &rval)); 10907 soc_reg_field_set(unit, XLPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 0); 10908 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XMAC_CONTROLr(unit, port, rval)); 10909 } 10910 rval = 0; 10911 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_IP_STATS_INITf, 1); 10912 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_COS_BYTES_INITf, 1); 10913 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_COS_PKTS_INITf, 1); 10914 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_VLAN_STATS_INITf, 1); 10915 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_HIGIG_CMD_STATS_INITf, 1); 10916 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_DROP_BYTES_INITf, 1); 10917 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_DROP_PKTS_INITf, 1); 10918 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_L2_BYTES_INITf, 1); 10919 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_L2_PKTS_INITf, 1); 10920 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_SKIP_STOP_STATS_INITf, 1); 10921 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_DROP_AGG_INITf, 1); 10922 soc_reg_field_set(unit, ISW2_MEM_INIT1r, &rval, RCV_IPHCKS_INITf, 1); 10923 SOC_IF_ERROR_RETURN(WRITE_ISW2_MEM_INIT1r(unit, rval)); 10924 10925 rval = 0; 10926 soc_reg_field_set(unit, ISW2_MEM_INIT2r, &rval, RDBGC0_INITf, 1); 10927 soc_reg_field_set(unit, ISW2_MEM_INIT2r, &rval, RDBGC1_INITf, 1); 10928 soc_reg_field_set(unit, ISW2_MEM_INIT2r, &rval, RDBGC2_INITf, 1); 10929 soc_reg_field_set(unit, ISW2_MEM_INIT2r, &rval, RDBGC3_INITf, 1); 10930 soc_reg_field_set(unit, ISW2_MEM_INIT2r, &rval, RDBGC4_INITf, 1); 10931 soc_reg_field_set(unit, ISW2_MEM_INIT2r, &rval, RDBGC5_INITf, 1); 10932 soc_reg_field_set(unit, ISW2_MEM_INIT2r, &rval, RDBGC6_INITf, 1); 10933 soc_reg_field_set(unit, ISW2_MEM_INIT2r, &rval, RDBGC7_INITf, 1); 10934 soc_reg_field_set(unit, ISW2_MEM_INIT2r, &rval, RDBGC8_INITf, 1); 10935 SOC_IF_ERROR_RETURN(WRITE_ISW2_MEM_INIT2r(unit, rval)); 10936 } 10937 #endif 10938 10939 } /* !SOC_IS_RCPU_ONLY */ 10940 10941 if (soc_property_get(unit, spn_L2XMSG_SHADOW_HIT_BITS, 1)) { 10942 soc->l2x_shadow_hit_bits |= L2X_SHADOW_HIT_BITS; 10943 } else { 10944 soc->l2x_shadow_hit_bits = 0; 10945 } 10946 if (soc_property_get(unit, spn_L2XMSG_SHADOW_HIT_SRC, 0)) { 10947 soc->l2x_shadow_hit_bits |= L2X_SHADOW_HIT_SRC; 10948 } 10949 if (soc_property_get(unit, spn_L2XMSG_SHADOW_HIT_DST, 0)) { 10950 soc->l2x_shadow_hit_bits |= L2X_SHADOW_HIT_DST; 10951 } 10952 10953 #ifdef BCM_XGS_SWITCH_SUPPORT 10954 if (soc_feature(unit, soc_feature_dual_hash)) { 10955 SOC_DUAL_HASH_MOVE_MAX(unit) = soc_property_get(unit, 10956 spn_DUAL_HASH_RECURSE_DEPTH, 10957 SOC_MEM_DUAL_HASH_RECURSE_DEPTH); 10958 SOC_DUAL_HASH_MOVE_MAX_L2X(unit) = soc_property_get(unit, 10959 spn_DUAL_HASH_RECURSE_DEPTH_L2X, 10960 soc_dual_hash_recurse_depth_get(unit, L2Xm)); 10961 SOC_DUAL_HASH_MOVE_MAX_MPLS(unit) = soc_property_get(unit, 10962 spn_DUAL_HASH_RECURSE_DEPTH_MPLS, 10963 soc_dual_hash_recurse_depth_get(unit, MPLS_ENTRYm)); 10964 SOC_DUAL_HASH_MOVE_MAX_VLAN(unit) = soc_property_get(unit, 10965 spn_DUAL_HASH_RECURSE_DEPTH_VLAN, 10966 soc_dual_hash_recurse_depth_get(unit, VLAN_XLATEm)); 10967 SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit) = soc_property_get(unit, 10968 spn_DUAL_HASH_RECURSE_DEPTH_EGRESS_VLAN, 10969 soc_dual_hash_recurse_depth_get(unit, EGR_VLAN_XLATEm)); 10970 #if defined(INCLUDE_L3) 10971 SOC_DUAL_HASH_MOVE_MAX_L3X(unit) = soc_property_get(unit, 10972 spn_DUAL_HASH_RECURSE_DEPTH_L3X, 10973 soc_dual_hash_recurse_depth_get(unit, L3_ENTRY_ONLYm)); 10974 #endif 10975 #if defined(BCM_TRIDENT2_SUPPORT) 10976 SOC_DUAL_HASH_MOVE_MAX_ING_DNAT_ADDRESS_TYPE(unit) = soc_property_get(unit, 10977 spn_DUAL_HASH_RECURSE_DEPTH_DNAT_POOL, 10978 soc_dual_hash_recurse_depth_get(unit, ING_DNAT_ADDRESS_TYPEm)); 10979 SOC_DUAL_HASH_MOVE_MAX_ING_VP_VLAN_MEMBER(unit) = soc_property_get(unit, 10980 spn_DUAL_HASH_RECURSE_DEPTH_ING_VP_VLAN_MEMBER, 10981 soc_dual_hash_recurse_depth_get(unit, ING_VP_VLAN_MEMBERSHIPm)); 10982 SOC_DUAL_HASH_MOVE_MAX_EGR_VP_VLAN_MEMBER(unit) = soc_property_get(unit, 10983 spn_DUAL_HASH_RECURSE_DEPTH_EGR_VP_VLAN_MEMBER, 10984 soc_dual_hash_recurse_depth_get(unit, EGR_VP_VLAN_MEMBERSHIPm)); 10985 #endif /* BCM_TRIDENT2_SUPPORT */ 10986 } 10987 if (soc_feature(unit, soc_feature_ism_memory) || soc_feature(unit, soc_feature_shared_hash_mem)) { 10988 SOC_MULTI_HASH_MOVE_MAX(unit) = soc_property_get(unit, 10989 spn_MULTI_HASH_RECURSE_DEPTH, 10990 SOC_MEM_MULTI_HASH_RECURSE_DEPTH); 10991 SOC_MULTI_HASH_MOVE_MAX_L2(unit) = soc_property_get(unit, 10992 spn_MULTI_HASH_RECURSE_DEPTH_L2, 10993 soc_multi_hash_recurse_depth_get(unit, L2_ENTRY_1m)); 10994 SOC_MULTI_HASH_MOVE_MAX_MPLS(unit) = soc_property_get(unit, 10995 spn_MULTI_HASH_RECURSE_DEPTH_MPLS, 10996 soc_multi_hash_recurse_depth_get(unit, MPLS_ENTRYm)); 10997 SOC_MULTI_HASH_MOVE_MAX_VLAN(unit) = soc_property_get(unit, 10998 spn_MULTI_HASH_RECURSE_DEPTH_VLAN, 10999 soc_multi_hash_recurse_depth_get(unit, VLAN_XLATEm)); 11000 SOC_MULTI_HASH_MOVE_MAX_VLAN_1(unit) = soc_property_get(unit, 11001 spn_MULTI_HASH_RECURSE_DEPTH_VLAN_1, 11002 soc_multi_hash_recurse_depth_get(unit, VLAN_XLATE_1_SINGLEm)); 11003 SOC_MULTI_HASH_MOVE_MAX_VLAN_2(unit) = soc_property_get(unit, 11004 spn_MULTI_HASH_RECURSE_DEPTH_VLAN_2, 11005 soc_multi_hash_recurse_depth_get(unit, VLAN_XLATE_2_SINGLEm)); 11006 SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN(unit) = soc_property_get(unit, 11007 spn_MULTI_HASH_RECURSE_DEPTH_EGRESS_VLAN, 11008 soc_multi_hash_recurse_depth_get(unit, EGR_VLAN_XLATEm)); 11009 SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN_1(unit) = soc_property_get(unit, 11010 spn_MULTI_HASH_RECURSE_DEPTH_EGRESS_VLAN_1, 11011 soc_multi_hash_recurse_depth_get(unit, EGR_VLAN_XLATE_1_SINGLEm)); 11012 SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN_2(unit) = soc_property_get(unit, 11013 spn_MULTI_HASH_RECURSE_DEPTH_EGRESS_VLAN_2, 11014 soc_multi_hash_recurse_depth_get(unit, EGR_VLAN_XLATE_2_SINGLEm)); 11015 SOC_MULTI_HASH_MOVE_MAX_L3(unit) = soc_property_get(unit, 11016 spn_MULTI_HASH_RECURSE_DEPTH_L3, 11017 soc_multi_hash_recurse_depth_get(unit, L3_ENTRY_1m)); 11018 SOC_MULTI_HASH_MOVE_MAX_FPEM(unit) = soc_property_get(unit, 11019 spn_MULTI_HASH_RECURSE_DEPTH_EXACT_MATCH, 11020 soc_multi_hash_recurse_depth_get(unit, EXACT_MATCH_2m)); 11021 } 11022 if (soc_feature(unit, soc_feature_shared_hash_mem)) { 11023 /* 11024 * Chips following TH2 are recommended to use MULTI_MOVE_MODE_BREADTH 11025 * mode if applicable. 11026 */ 11027 SOC_MULTI_HASH_MOVE_ALGORITHM(unit) = soc_property_get(unit, 11028 "multi_hash_move_algorithm", 11029 (SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) ? 11030 MULTI_MOVE_MODE_BREADTH : MULTI_MOVE_MODE_MIX); 11031 } 11032 #endif /* BCM_XGS_SWITCH_SUPPORT */ 11033 11034 /* Backwards compatible default */ 11035 SOC_MCAST_ADD_ALL_ROUTER_PORTS(unit) = 1; 11036 11037 #ifdef BCM_XGS_SWITCH_SUPPORT 11038 if (soc_feature(unit, soc_feature_arl_hashed)) { 11039 SOC_IF_ERROR_RETURN(soc_l2x_init(unit)); 11040 } 11041 #endif 11042 11043 /* Set maximum supported vrf id for the device. */ 11044 SOC_IF_ERROR_RETURN(soc_max_supported_vrf_get(unit, &max_class)); 11045 SOC_VRF_MAX_SET(unit, max_class); 11046 /* Set maximum supported address class for the device. */ 11047 SOC_IF_ERROR_RETURN(soc_max_supported_addr_class_get(unit, &max_class)); 11048 SOC_ADDR_CLASS_MAX_SET(unit, max_class); 11049 11050 /* If the feature is supported, set the maximum supported over-laid 11051 address class for the device. */ 11052 if (soc_feature(unit, soc_feature_overlaid_address_class)) { 11053 SOC_IF_ERROR_RETURN 11054 (soc_max_supported_overlaid_addr_class_get(unit, &max_class)); 11055 SOC_OVERLAID_ADDR_CLASS_MAX_SET(unit, max_class); 11056 } 11057 11058 /* For the TR3 family of devices, set the extended classID */ 11059 if (soc_feature(unit, soc_feature_extended_address_class)) { 11060 SOC_IF_ERROR_RETURN 11061 (soc_max_supported_extended_addr_class_get(unit, &max_class)); 11062 SOC_EXT_ADDR_CLASS_MAX_SET(unit, max_class); 11063 } 11064 11065 if (soc_feature(unit, soc_feature_src_mac_group)) { 11066 SOC_L2X_GROUP_ENABLE_SET(unit, TRUE); 11067 } else { 11068 SOC_L2X_GROUP_ENABLE_SET(unit, FALSE); 11069 } 11070 11071 /* Set maximum supported address class for the device. */ 11072 SOC_IF_ERROR_RETURN(soc_max_supported_intf_class_get(unit, &max_class)); 11073 SOC_INTF_CLASS_MAX_SET(unit, max_class); 11074 11075 /* Create egress metering mutex. */ 11076 if ((soc->egressMeteringMutex = 11077 sal_mutex_create("port_rate_egress_lock")) == NULL) { 11078 return (SOC_E_MEMORY); 11079 } 11080 11081 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_APACHE_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 11082 if (SOC_IS_KATANAX(unit) || SOC_IS_TRIDENT2X(unit) || 11083 SOC_IS_TITAN2X(unit) || SOC_IS_TRIUMPH3(unit)) { 11084 /* Create llsMutex. */ 11085 if ((soc->llsMutex = 11086 sal_mutex_create("lls_scheduler_lock")) == NULL) { 11087 return (SOC_E_MEMORY); 11088 } 11089 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 11090 /* intialize port_flush_pbmp */ 11091 SOC_PBMP_CLEAR(soc->port_flush_pbmp); 11092 #endif 11093 } 11094 #endif 11095 11096 #if defined(BCM_TOMAHAWK_SUPPORT) 11097 if (SOC_IS_TOMAHAWKX(unit)) { 11098 /* Create idb_lock */ 11099 if ((soc->idb_lock = sal_mutex_create("idb_lock")) == NULL) { 11100 return (SOC_E_MEMORY); 11101 } 11102 } 11103 #endif 11104 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) 11105 if (soc_feature(unit, soc_feature_epc_linkflap_recover)) { 11106 /* Create linkscan_modport_map_lock */ 11107 if ((soc->linkscan_modport_map_lock = 11108 sal_mutex_create("linkscan_modport_map_lock")) == NULL) { 11109 return (SOC_E_MEMORY); 11110 } 11111 } 11112 #endif /* #(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) */ 11113 if(soc_property_get(unit, spn_MEM_CLEAR_HW_ACCELERATION, 1)) { 11114 SOC_MEM_CLEAR_USE_DMA_SET(unit, TRUE); 11115 } 11116 11117 mem_clear_chunk_size = 11118 soc_property_get(unit, spn_MEM_CLEAR_CHUNK_SIZE, 4096); 11119 SOC_MEM_CLEAR_CHUNK_SIZE_SET(unit, mem_clear_chunk_size); 11120 11121 if (soc_property_get(unit, spn_GPORT, FALSE)) { 11122 SOC_USE_GPORT_SET(unit, TRUE); 11123 } 11124 #ifdef BCM_ASSERT_EVENT_ENABLE 11125 sal_assert_set(soc_event_assert); 11126 #endif /* BCM_ASSERT_EVENT_ENABLE */ 11127 11128 #ifdef BCM_WARM_BOOT_SUPPORT 11129 if (SOC_WARM_BOOT(unit)) { 11130 #ifdef BCM_ISM_SUPPORT 11131 /* Retreive hash config data */ 11132 if (soc_feature(unit, soc_feature_ism_memory)) { 11133 uint8 hcfg; 11134 uint8 offsets[_SOC_ISM_MAX_BANKS], count; 11135 11136 rv = soc_ism_table_hash_config_get(unit, SOC_ISM_MEM_VLAN_XLATE, 11137 &hcfg); 11138 rv |= soc_ism_table_hash_config_get(unit, SOC_ISM_MEM_L2_ENTRY, 11139 &hcfg); 11140 rv |= soc_ism_table_hash_config_get(unit, SOC_ISM_MEM_L3_ENTRY, 11141 &hcfg); 11142 rv |= soc_ism_table_hash_config_get(unit, SOC_ISM_MEM_EP_VLAN_XLATE, 11143 &hcfg); 11144 rv |= soc_ism_table_hash_config_get(unit, SOC_ISM_MEM_MPLS, &hcfg); 11145 if (rv != SOC_E_NONE) { 11146 LOG_ERROR(BSL_LS_SOC_COMMON, 11147 (BSL_META_U(unit, 11148 "Error retreiving ISM hash zero_lsb(s) !!\n"))); 11149 return SOC_E_INTERNAL; 11150 } 11151 rv = soc_ism_hash_table_offset_config_get(unit, SOC_ISM_MEM_VLAN_XLATE, 11152 offsets, &count); 11153 rv |= soc_ism_hash_table_offset_config_get(unit, SOC_ISM_MEM_L2_ENTRY, 11154 offsets, &count); 11155 rv |= soc_ism_hash_table_offset_config_get(unit, SOC_ISM_MEM_L3_ENTRY, 11156 offsets, &count); 11157 rv |= soc_ism_hash_table_offset_config_get(unit, SOC_ISM_MEM_EP_VLAN_XLATE, 11158 offsets, &count); 11159 rv |= soc_ism_hash_table_offset_config_get(unit, SOC_ISM_MEM_MPLS, 11160 offsets, &count); 11161 if (rv != SOC_E_NONE) { 11162 LOG_ERROR(BSL_LS_SOC_COMMON, 11163 (BSL_META_U(unit, 11164 "Error retreiving ISM hash offset(s) !!\n"))); 11165 return SOC_E_INTERNAL; 11166 } 11167 } 11168 #endif /* BCM_ISM_SUPPORT */ 11169 } 11170 #endif /* BCM_WARM_BOOT_SUPPORT */ 11171 11172 #if defined(BCM_TRIUMPH3_SUPPORT) && defined(INCLUDE_L3) 11173 if (soc_feature(unit, soc_feature_static_repl_head_alloc)) { 11174 soc->repl_eligible_pbmp = soc_property_get_pbmp_default(unit, 11175 spn_REPLICATION_ELIGIBLE_PBMP, PBMP_ALL(unit)); 11176 } 11177 #endif 11178 11179 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 11180 if (!SAL_BOOT_BCMSIM && !SAL_BOOT_QUICKTURN 11181 && !SAL_BOOT_XGSSIM && !SOC_WARM_BOOT(unit)) { 11182 if (soc_feature(unit, soc_feature_td2p_ovstb_toggle)) { 11183 trident2p_ovstb_toggle(unit); 11184 } 11185 } 11186 #endif 11187 11188 #if defined(CANCUN_SUPPORT) 11189 if (soc_feature(unit, soc_feature_cancun)) { 11190 soc_cancun_init(unit); 11191 } 11192 if (soc_feature(unit, soc_feature_flex_flow)) { 11193 soc_flow_db_init(unit); 11194 } 11195 #endif 11196 #ifdef INCLUDE_AVS 11197 if (soc_feature(unit, soc_feature_avs_openloop)) { 11198 soc_avs_deinit(unit); 11199 soc_avs_init(unit); 11200 } 11201 #endif /* INCLUDE_AVS */ 11202 11203 /* Set flex counter feature for new Ranger3+ parts */ 11204 #ifdef BCM_TOMAHAWK_SUPPORT 11205 SOC_IF_ERROR_RETURN(soc_flex_counter_feature_init(unit)); 11206 #endif 11207 11208 /* Start to allow this unit to run DPCs */ 11209 sal_dpc_enable(INT_TO_PTR(unit)); 11210 11211 return(SOC_E_NONE); 11212 } 11213 11214 #ifdef BCM_WARM_BOOT_SUPPORT 11215 #define SOC_INTERRUPT_SLEEP_MAX_TIMES 1000 11216 /* 11217 * Function: 11218 * soc_interrupt_service_wait 11219 * Purpose: 11220 * Check interrupt masks on various lines and keep waiting until they 11221 * are all serviced. 11222 * Parameters: 11223 * unit - (IN) Device Number 11224 * Returns: 11225 * SOC_E_NONE once all masks are clear, error if some soc call fails 11226 */ 11227 STATIC soc_error_t 11228 soc_interrupt_service_wait(int unit) 11229 { 11230 uint32 status = 0; 11231 uint32 count = 0; 11232 uint8 error_sleep = FALSE; 11233 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICDV2_SUPPORT) || \ 11234 defined(BCM_TRIDENT2_SUPPORT) 11235 uint32 mask = 0; 11236 int cmc = SOC_PCI_CMC(unit); 11237 #endif 11238 11239 while(1){ 11240 /* Keep checking the status of the IRQ line until you hit a non-zero 11241 * value, if non-zero stop the check and sleep to yield cpu for the 11242 * interrupt handling to complete. If the status is zero at the end 11243 * of all checks, just return, indicating no interrupts left to be 11244 * handled. 11245 */ 11246 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICDV2_SUPPORT) 11247 /* For CMICd/m devices check the relevant IRQ status registers */ 11248 if (soc_feature(unit, soc_feature_cmicd_v2) || 11249 soc_feature(unit, soc_feature_cmicm)) { 11250 status = soc_pci_read(unit, CMIC_CMCx_IRQ_STAT3_OFFSET(cmc)); 11251 mask = SOC_CMCx_IRQ3_MASK(unit, cmc); 11252 status &= mask; 11253 11254 /* 11255 * If the mask is disabled by the interrupt handler 11256 * try to sleep a while to wait for bcmDpc thread handles ser interrupt 11257 */ 11258 if (mask == 0) { 11259 LOG_VERBOSE(BSL_LS_SOC_SER, 11260 (BSL_META_U(unit, 11261 "IRQ3 Mask is zero!\n"))); 11262 error_sleep = TRUE; 11263 goto sleep; 11264 } 11265 if (soc_feature(unit, soc_feature_cmicd_v2) && 11266 (!status)) { 11267 status = soc_pci_read(unit, CMIC_CMCx_IRQ_STAT4_OFFSET(cmc)); 11268 mask = SOC_CMCx_IRQ4_MASK(unit, cmc); 11269 status &= mask; 11270 if (!SOC_IS_GREYHOUND(unit) && (mask == 0)) { 11271 /* Continuous interrupt (not parity error) on GH */ 11272 LOG_VERBOSE(BSL_LS_SOC_SER, 11273 (BSL_META_U(unit, 11274 "IRQ4 Mask is zero!\n"))); 11275 error_sleep = TRUE; 11276 goto sleep; 11277 } 11278 } 11279 } 11280 #endif 11281 #ifdef BCM_TRIDENT2_SUPPORT 11282 if ((SOC_IS_TRIDENT2(unit) || SOC_IS_TITAN2(unit) || 11283 SOC_IS_TD2P_TT2P(unit)) && (!status)) { 11284 status = soc_pci_read(unit, CMIC_CMCx_IRQ_STAT2_OFFSET(cmc)); 11285 mask = SOC_CMCx_IRQ2_MASK(unit, cmc); 11286 status &= mask; 11287 if (mask == 0) { 11288 LOG_VERBOSE(BSL_LS_SOC_SER, 11289 (BSL_META_U(unit, 11290 "IRQ2 Mask is zero!\n"))); 11291 error_sleep = TRUE; 11292 goto sleep; 11293 } 11294 } 11295 #endif /* BCM_TRIDENT2_SUPPORT */ 11296 11297 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICDV2_SUPPORT) || \ 11298 defined(BCM_TRIDENT2_SUPPORT) 11299 sleep: 11300 #endif 11301 /* If the status not clear yet, sleep a bit, so as to complete the 11302 * interrupt handling. If they are clear, break. 11303 */ 11304 if (++count > SOC_INTERRUPT_SLEEP_MAX_TIMES) { 11305 /* To avoid dead loop */ 11306 break; 11307 } 11308 if (status) { 11309 sal_usleep(1000); 11310 status = 0; 11311 } else if (error_sleep) { 11312 sal_usleep(1000); 11313 error_sleep = FALSE; 11314 } else { 11315 break; 11316 } 11317 } 11318 11319 return SOC_E_NONE; 11320 } 11321 11322 /* 11323 * Function: 11324 * soc_shutdown 11325 * Purpose: 11326 * Free up SOC resources without touching hardware 11327 * Parameters: 11328 * unit - StrataSwitch unit # 11329 * Returns: 11330 * SOC_E_XXX 11331 */ 11332 int 11333 soc_shutdown(int unit) 11334 { 11335 soc_control_t *soc; 11336 soc_mem_t mem, act_mem, lock_mem; 11337 int ix; 11338 int cmc; 11339 #ifdef INCLUDE_KNET 11340 uint8 shutdown_knet = TRUE; 11341 #endif 11342 int warm_boot; 11343 11344 #ifdef INCLUDE_KNET 11345 if (SOC_KNET_MODE(unit) && 11346 soc_property_get(unit, spn_WARMBOOT_KNET_SHUTDOWN_MODE, 0)) { 11347 shutdown_knet = FALSE; 11348 } 11349 #endif 11350 11351 if (!SOC_UNIT_VALID(unit)) { 11352 LOG_ERROR(BSL_LS_SOC_COMMON, 11353 (BSL_META_U(unit, 11354 "soc_shutdown: unit %d not valid\n"), unit)); 11355 return SOC_E_UNIT; 11356 } 11357 11358 soc = SOC_CONTROL(unit); 11359 11360 if (!(soc->soc_flags & SOC_F_ATTACHED)) { 11361 LOG_ERROR(BSL_LS_SOC_COMMON, 11362 (BSL_META_U(unit, 11363 "soc_shutdown: unit %d not attached\n"), unit)); 11364 return(SOC_E_UNIT); 11365 } 11366 11367 #ifdef BCM_CMICM_SUPPORT 11368 if (soc_feature(unit, soc_feature_cmicm)) { 11369 soc_cmic_uc_msg_apps_notify(unit, SOC_CMIC_UC_SHUTDOWN_NOHALT); 11370 } 11371 #endif /* BCM_CMICM_SUPPORT */ 11372 11373 #ifdef BCM_CMICX_SUPPORT 11374 if (soc_feature(unit, soc_feature_cmicx)) { 11375 soc_cmic_uc_msg_apps_notify(unit, SOC_CMIC_UC_SHUTDOWN_NOHALT); 11376 } 11377 if (soc_feature(unit, soc_feature_cmicx) && !(SAL_BOOT_PLISIM || SAL_BOOT_BCMSIM)) { 11378 LOG_INFO(BSL_LS_SOC_COMMON, (BSL_META_U(unit,"soc_shutdown: iproc m0 exit\n"))); 11379 /* Stop LED FW */ 11380 soc_cmicx_led_enable(unit, LED_STOP); 11381 /* Iproc M0 exit */ 11382 soc_iproc_m0_exit(unit); 11383 } 11384 #endif /* BCM_CMICX_SUPPORT */ 11385 11386 if (soc->soc_flags & SOC_F_INITED) { 11387 #ifdef BCM_HERCULES_SUPPORT 11388 /* Dump the MMU error stats */ 11389 soc_mmu_error_done(unit); 11390 11391 if (soc->lla_cells_good != NULL) { 11392 sal_free(soc->lla_cells_good); 11393 soc->lla_cells_good = NULL; 11394 } 11395 11396 if (soc->lla_map != NULL) { 11397 int port; 11398 PBMP_PORT_ITER(unit, port) { 11399 if (soc->lla_map[port] != NULL) { 11400 sal_free(soc->lla_map[port]); 11401 } 11402 } 11403 sal_free(soc->lla_map); 11404 soc->lla_map = NULL; 11405 } 11406 11407 if (soc->sbe_disable != NULL) { 11408 sal_free(soc->sbe_disable); 11409 soc->sbe_disable = NULL; 11410 } 11411 #endif 11412 11413 #ifdef INCLUDE_I2C 11414 SOC_IF_ERROR_RETURN(soc_i2c_detach(unit)); /* Free up I2C driver mem */ 11415 #endif 11416 11417 if (!SOC_IS_RCPU_ONLY(unit)) { 11418 /* Free up DMA memory */ 11419 SOC_IF_ERROR_RETURN(soc_dma_detach(unit)); 11420 } 11421 11422 if (soc->arlShadow != NULL) { 11423 sal_mutex_take(soc->arlShadowMutex, sal_mutex_FOREVER); 11424 shr_avl_delete_all(soc->arlShadow); 11425 sal_mutex_give(soc->arlShadowMutex); 11426 } 11427 11428 #ifdef BCM_TOMAHAWK3_SUPPORT 11429 /* Free AVL table used for L2 learning */ 11430 if ((SOC_IS_TOMAHAWK3(unit)) && (soc->l2x_lrn_shadow != NULL)) { 11431 sal_mutex_take(soc->l2x_lrn_shadow_mutex, sal_mutex_FOREVER); 11432 shr_avl_delete_all(soc->l2x_lrn_shadow); 11433 sal_mutex_give(soc->l2x_lrn_shadow_mutex); 11434 } 11435 #endif /* BCM_TOMAHAWK3_SUPPORT */ 11436 11437 warm_boot = SOC_WARM_BOOT(unit); 11438 if (!warm_boot) { 11439 SOC_WARM_BOOT_START(unit); 11440 } 11441 11442 /* Terminate counter module; frees allocated space */ 11443 soc_counter_detach(unit); 11444 11445 if (!warm_boot) { 11446 SOC_WARM_BOOT_DONE(unit); 11447 } 11448 11449 #ifdef BCM_XGS_SWITCH_SUPPORT 11450 11451 if (soc_property_get(unit, spn_PARITY_ENABLE, TRUE) && 11452 SOC_CONTROL(unit)->mem_scache_ptr == NULL) { 11453 SOC_IF_ERROR_RETURN(soc_system_scrub(unit)); 11454 11455 /* There could be instances where all outstanding interrupts 11456 * are not serviced yet, we wait here to ensure the interrupt 11457 * mask on relevant irq lines are reset before we shut down 11458 * the DPC processing 11459 */ 11460 if (SOC_FAILURE(soc_interrupt_service_wait(unit))) { 11461 LOG_ERROR(BSL_LS_SOC_COMMON, 11462 (BSL_META_U(unit, 11463 "soc_shutdown: soc_interrupt_service_wait " 11464 "ran into errors!\n"))); 11465 } 11466 } 11467 11468 if (soc_feature(unit, soc_feature_arl_hashed)) { 11469 /* Stop L2X thread */ 11470 SOC_IF_ERROR_RETURN(soc_l2x_stop(unit)); 11471 SOC_IF_ERROR_RETURN(soc_l2x_detach(unit)); 11472 } 11473 #ifdef BCM_TRIUMPH3_SUPPORT 11474 if SOC_IS_TRIUMPH3(unit) { 11475 SOC_IF_ERROR_RETURN(soc_tr3_l2_bulk_age_stop(unit)); 11476 } 11477 #endif /* BCM_TRIUMPH3_SUPPORT */ 11478 #ifdef BCM_TRIDENT2_SUPPORT 11479 if SOC_IS_TRIDENT2X(unit) { 11480 SOC_IF_ERROR_RETURN(soc_td2_l2_bulk_age_stop(unit)); 11481 } 11482 #endif /* BCM_TRIDENT2_SUPPORT */ 11483 #ifdef BCM_TOMAHAWK_SUPPORT 11484 if (SOC_IS_TOMAHAWK(unit) || SOC_IS_TOMAHAWK2(unit) || 11485 SOC_IS_TRIDENT3X(unit)) { 11486 SOC_IF_ERROR_RETURN(soc_th_l2_bulk_age_stop(unit)); 11487 } 11488 #endif /* BCM_TOMAHAWK_SUPPORT */ 11489 #ifdef ALPM_ENABLE 11490 #if defined(BCM_TOMAHAWK_SUPPORT) 11491 if (soc_property_get(unit, spn_L3_ALPM_ENABLE, 0) && 11492 soc_feature(unit, soc_feature_alpm2)) { 11493 SOC_IF_ERROR_RETURN(alpm_dist_hitbit_thread_stop(unit)); 11494 } 11495 #endif 11496 #endif 11497 #ifdef BCM_TOMAHAWK3_SUPPORT 11498 /* Stop L2 learning and aging threads */ 11499 if (SOC_IS_TOMAHAWK3(unit)) { 11500 SOC_IF_ERROR_RETURN(soc_th3_l2_age_stop(unit)); 11501 SOC_IF_ERROR_RETURN(soc_th3_l2_learn_thread_stop(unit)); 11502 } 11503 #endif /* BCM_TOMAHAWK3_SUPPORT */ 11504 11505 #ifdef BCM_SBUSDMA_SUPPORT 11506 if (SOC_SBUSDMA_DM_INFO(unit)) { 11507 SOC_IF_ERROR_RETURN(soc_sbusdma_desc_detach(unit)); 11508 } 11509 #endif /* BCM_SBUSDMA_SUPPORT */ 11510 11511 #ifdef BCM_CCMDMA_SUPPORT 11512 SOC_IF_ERROR_RETURN(soc_ccmdma_deinit(unit)); 11513 #endif 11514 11515 #ifdef BCM_FIFODMA_SUPPORT 11516 SOC_IF_ERROR_RETURN(soc_fifodma_deinit(unit)); 11517 #endif 11518 11519 #ifdef CANCUN_SUPPORT 11520 if (soc_feature(unit, soc_feature_cancun)) { 11521 soc_cancun_deinit(unit); 11522 } 11523 if (soc_feature(unit, soc_feature_flex_flow)) { 11524 soc_flow_db_deinit(unit); 11525 } 11526 #endif 11527 11528 #endif /* BCM_XGS_SWITCH_SUPPORT */ 11529 11530 soc->soc_flags &= ~SOC_F_INITED; 11531 #ifdef BCM_CMICX_SUPPORT 11532 if (soc_feature(unit, soc_feature_cmicx)) { 11533 soc_cmic_intr_all_disable(unit); 11534 } else 11535 #endif 11536 #ifdef BCM_CMICM_SUPPORT 11537 if (soc_feature(unit, soc_feature_cmicm)) { 11538 soc_cmicm_intr0_disable(unit, ~0); 11539 soc_cmicm_intr1_disable(unit, ~0); 11540 soc_cmicm_intr2_disable(unit, ~0); 11541 #ifdef BCM_CMICDV2_SUPPORT 11542 if (soc_feature(unit, soc_feature_cmicd_v2)) { 11543 soc_cmicm_intr3_disable(unit, ~0); 11544 soc_cmicm_intr4_disable(unit, ~0); 11545 soc_cmicm_intr5_disable(unit, ~0); 11546 #ifdef BCM_CMICDV4_SUPPORT 11547 if (soc_feature(unit, soc_feature_cmicd_v4)) { 11548 soc_cmicm_intr6_disable(unit, ~0); 11549 } 11550 #endif /* BCM_CMICDV4_SUPPORT */ 11551 } 11552 #endif /* BCM_CMICDV2_SUPPORT */ 11553 } else 11554 #endif 11555 { 11556 soc_intr_disable(unit, ~0); 11557 } 11558 11559 /* Shutdown polled interrupt mode if active */ 11560 if (soc->soc_flags & SOC_F_POLLED) { 11561 soc_ipoll_disconnect(unit); 11562 soc->soc_flags &= ~SOC_F_POLLED; 11563 } 11564 11565 /* Detach interrupt handler, if we installed one */ 11566 /* unit # is ISR arg */ 11567 if (soc_cm_interrupt_disconnect(unit) < 0) { 11568 LOG_ERROR(BSL_LS_SOC_COMMON, 11569 (BSL_META_U(unit, 11570 "soc_shutdown: could not disconnect interrupt line\n"))); 11571 return SOC_E_INTERNAL; 11572 } 11573 11574 /* Disable shutting down unit to run new DPCs and wait until all 11575 * existing DPCs are completed. 11576 */ 11577 sal_dpc_disable_and_wait(INT_TO_PTR(unit)); 11578 11579 /* 11580 * When detaching, take care to free up only resources that were 11581 * actually allocated, in case we are cleaning up after an attach 11582 * that failed part way through. 11583 */ 11584 if (soc->arlBuf != NULL) { 11585 soc_cm_sfree(unit, (void *)soc->arlBuf); 11586 soc->arlBuf = NULL; 11587 } 11588 11589 if (soc->arlShadow != NULL) { 11590 shr_avl_destroy(soc->arlShadow); 11591 soc->arlShadow = NULL; 11592 } 11593 11594 if (soc->arlShadowMutex != NULL) { 11595 sal_mutex_destroy(soc->arlShadowMutex); 11596 soc->arlShadowMutex = NULL; 11597 } 11598 11599 #ifdef BCM_TOMAHAWK3_SUPPORT 11600 /* Free resources allocated for L2 learning */ 11601 if (SOC_IS_TOMAHAWK3(unit)) { 11602 if (soc->l2x_lrn_shadow != NULL) { 11603 shr_avl_destroy(soc->l2x_lrn_shadow); 11604 soc->l2x_lrn_shadow = NULL; 11605 } 11606 11607 if (soc->l2x_lrn_shadow_mutex != NULL) { 11608 sal_mutex_destroy(soc->l2x_lrn_shadow_mutex); 11609 soc->l2x_lrn_shadow_mutex = NULL; 11610 } 11611 } 11612 #endif /* BCM_TOMAHAWK3_SUPPORT */ 11613 11614 #if defined(BCM_ESW_SUPPORT) && defined(BCM_IPROC_SUPPORT) 11615 /* De-Initialize bond info cache */ 11616 if (soc_feature(unit, soc_feature_untethered_otp)) { 11617 if (soc_bond_info_deinit(unit) < 0) { 11618 LOG_ERROR(BSL_LS_SOC_COMMON, 11619 (BSL_META_U(unit, 11620 "soc_shutdown: could not de-initialize " 11621 "bond info structure\n"))); 11622 return SOC_E_INTERNAL; 11623 } 11624 } 11625 #endif /* BCM_ESW_SUPPORT && BCM_IPROC_SUPPORT */ 11626 11627 11628 #ifdef SOC_ROBUST_HASH 11629 if (soc_feature(unit, soc_feature_robust_hash)) { 11630 if (soc->soc_robust_hash_config != NULL) { 11631 sal_free(soc->soc_robust_hash_config); 11632 soc->soc_robust_hash_config = NULL; 11633 } 11634 } 11635 #endif /* SOC_ROBUST_HASH */ 11636 11637 #ifdef INCLUDE_MEM_SCAN 11638 SOC_IF_ERROR_RETURN(soc_mem_scan_stop(unit)); /* Stop memory scanner */ 11639 if (soc->mem_scan_notify) { 11640 sal_sem_destroy(soc->mem_scan_notify); 11641 } 11642 #endif 11643 #ifdef BCM_SRAM_SCAN_SUPPORT 11644 SOC_IF_ERROR_RETURN(soc_sram_scan_stop(unit)); /* Stop memory scanner */ 11645 if (soc->sram_scan_notify) { 11646 sal_sem_destroy(soc->sram_scan_notify); 11647 } 11648 #endif 11649 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 11650 if (!SOC_MEM_IS_VALID(unit, mem)) { 11651 continue; 11652 } 11653 11654 act_mem = mem; 11655 #ifdef BCM_ESW_SUPPORT 11656 soc_drv_mem_reuse_mem_state(unit, &act_mem, &lock_mem); 11657 #endif 11658 /* Deallocate table cache memory, if caching enabled */ 11659 SOC_IF_ERROR_RETURN(soc_mem_cache_set(unit, act_mem, COPYNO_ALL, FALSE)); 11660 } 11661 11662 /* LOCK used in cache_set, so destroy later */ 11663 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 11664 if (!SOC_MEM_IS_VALID(unit, mem)) { 11665 continue; 11666 } 11667 11668 act_mem = mem; 11669 lock_mem = mem; 11670 #ifdef BCM_ESW_SUPPORT 11671 soc_drv_mem_reuse_mem_state(unit, &act_mem, &lock_mem); 11672 #endif 11673 if (soc->memState[lock_mem].lock != NULL) { 11674 sal_mutex_destroy(soc->memState[lock_mem].lock); 11675 soc->memState[lock_mem].lock = NULL; 11676 } 11677 #ifdef BCM_ESW_SUPPORT 11678 /* Share the lock */ 11679 soc_drv_mem_sync_mapped_lock(unit, mem, soc->memState[lock_mem].lock); 11680 #endif 11681 } 11682 #ifdef BCM_ESW_SUPPORT 11683 if (SOC_MEM_IS_VALID(unit, ING_DEVICE_PORTm) && 11684 !SOC_MEM_IS_VALID(unit, PORT_TABm)) { 11685 soc->memState[PORT_TABm].lock = soc->memState[ING_DEVICE_PORTm].lock; 11686 } 11687 #endif 11688 11689 if (soc->schanMutex) { 11690 sal_mutex_destroy(soc->schanMutex); 11691 soc->schanMutex = NULL; 11692 } 11693 11694 #ifdef BCM_CMICM_SUPPORT 11695 if (soc->fschanMutex) { 11696 sal_mutex_destroy(soc->fschanMutex); 11697 soc->fschanMutex = NULL; 11698 } 11699 #endif 11700 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) 11701 #ifdef BCM_CCMDMA_SUPPORT 11702 if (soc_feature(unit, soc_feature_cmicm) || 11703 soc_feature(unit, soc_feature_cmicx)) { 11704 for (cmc = 0; cmc < SOC_PCI_CMCS_NUM(unit); cmc++) { 11705 if (soc->ccmDmaIntr[cmc]) { 11706 sal_sem_destroy(soc->ccmDmaIntr[cmc]); 11707 soc->ccmDmaIntr[cmc] = NULL; 11708 } 11709 } 11710 } 11711 #endif 11712 #endif 11713 #ifdef BCM_CMICM_SUPPORT 11714 if (soc_feature(unit, soc_feature_cmicm)) { 11715 soc_cmic_uc_msg_stop(unit); 11716 } 11717 #endif 11718 #ifdef BCM_CMICX_SUPPORT 11719 if (soc_feature(unit, soc_feature_cmicx)) { 11720 soc_cmic_uc_msg_stop(unit); 11721 } 11722 #endif 11723 for (cmc = 0; cmc < SOC_PCI_CMCS_NUM(unit) + 1; cmc++) { 11724 if (soc->schanIntr[cmc]) { 11725 sal_sem_destroy(soc->schanIntr[cmc]); 11726 soc->schanIntr[cmc] = NULL; 11727 } 11728 } 11729 11730 if (soc->miimMutex) { 11731 sal_mutex_destroy(soc->miimMutex); 11732 soc->miimMutex = NULL; 11733 } 11734 11735 (void)soc_sbusdma_lock_deinit(unit); 11736 11737 #ifdef BCM_CMICM_SUPPORT 11738 for (cmc = 0; cmc < SOC_PCI_CMCS_NUM(unit); cmc++) { 11739 int ch; 11740 for (ch = 0; ch < N_DMA_CHAN; ch++) { 11741 if (soc->fifoDmaMutexs[cmc][ch]) { 11742 sal_mutex_destroy(soc->fifoDmaMutexs[cmc][ch]); 11743 soc->fifoDmaMutexs[cmc][ch] = NULL; 11744 } 11745 if (soc->fifoDmaIntrs[cmc][ch]) { 11746 sal_sem_destroy(soc->fifoDmaIntrs[cmc][ch]); 11747 soc->fifoDmaIntrs[cmc][ch] = NULL; 11748 } 11749 } 11750 } 11751 #endif 11752 11753 for (ix = 0; ix < 3; ix++) { 11754 if (soc->memCmdIntr[ix]) { 11755 sal_sem_destroy(soc->memCmdIntr[ix]); 11756 soc->memCmdIntr[ix] = NULL; 11757 } 11758 } 11759 11760 if (soc->arl_notify) { 11761 sal_sem_destroy(soc->arl_notify); 11762 soc->arl_notify = NULL; 11763 } 11764 11765 #if defined(BCM_TRIUMPH3_SUPPORT) 11766 if (soc_feature(unit, soc_feature_esm_correction)) { 11767 SOC_IF_ERROR_RETURN(soc_tr3_esm_recovery_stop(unit)); 11768 if (soc->esm_recovery_notify) { 11769 sal_sem_destroy(soc->esm_recovery_notify); 11770 soc->esm_recovery_notify = NULL; 11771 } 11772 if (soc->esm_lock) { 11773 sal_mutex_destroy(soc->esm_lock); 11774 soc->esm_lock = NULL; 11775 } 11776 } 11777 #endif 11778 11779 #ifdef BCM_XGS_SWITCH_SUPPORT 11780 if (NULL != soc->l2x_notify) { 11781 sal_sem_destroy(soc->l2x_notify); 11782 soc->l2x_notify = NULL; 11783 } 11784 if (NULL != soc->l2x_del_sync) { 11785 sal_mutex_destroy(soc->l2x_del_sync); 11786 soc->l2x_del_sync = NULL; 11787 } 11788 if (NULL != soc->l2x_lock) { 11789 sal_sem_destroy(soc->l2x_lock); 11790 soc->l2x_lock = NULL; 11791 } 11792 soc->l2x_pid = SAL_THREAD_ERROR; 11793 soc->l2x_interval = 0; 11794 #ifdef BCM_TOMAHAWK3_SUPPORT 11795 if (SOC_IS_TOMAHAWK3(unit)) { 11796 /* Clear L2 learning related data */ 11797 soc->l2x_learn_pid = SAL_THREAD_ERROR; 11798 soc->l2x_learn_interval = 0; 11799 11800 soc->lrn_cache_threshold = -1; 11801 soc->lrn_cache_intr_ctl = -1; 11802 soc->lrn_cache_clr_on_rd = -1; 11803 } 11804 #endif /* BCM_TOMAHAWK3_SUPPORT */ 11805 #ifdef BCM_TSN_SUPPORT 11806 if (NULL != soc->l2x_sr_sync) { 11807 sal_mutex_destroy(soc->l2x_sr_sync); 11808 soc->l2x_sr_sync = NULL; 11809 } 11810 #endif /* BCM_TSN_SUPPORT */ 11811 11812 #ifdef BCM_TRIUMPH3_SUPPORT 11813 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWKX(unit) || 11814 SOC_IS_TRIDENT3X(unit)) { 11815 if (NULL != soc->l2x_age_notify) { 11816 sal_sem_destroy(soc->l2x_age_notify); 11817 soc->l2x_age_notify = NULL; 11818 } 11819 soc->l2x_age_pid = SAL_THREAD_ERROR; 11820 soc->l2x_age_interval = 0; 11821 soc->l2x_agetime_adjust_usec = 0; 11822 soc->l2x_agetime_curr_timeblk = 0; 11823 soc->l2x_agetime_curr_timeblk_usec = 0; 11824 soc->l2x_prev_age_timeout = 0; 11825 } 11826 #endif 11827 #ifdef BCM_TRIDENT2_SUPPORT 11828 if SOC_IS_TRIDENT2X(unit) { 11829 if (NULL != soc->l2x_age_notify) { 11830 sal_sem_destroy(soc->l2x_age_notify); 11831 soc->l2x_age_notify = NULL; 11832 } 11833 if (NULL != soc->l2x_age_sync) { 11834 sal_sem_destroy(soc->l2x_age_sync); 11835 soc->l2x_age_sync = NULL; 11836 } 11837 soc->l2x_age_pid = SAL_THREAD_ERROR; 11838 soc->l2x_age_interval = 0; 11839 soc->l2x_age_enable = 0; 11840 soc->l2x_sw_aging = 0; 11841 } 11842 #endif 11843 #endif /* BCM_XGS_SWITCH_SUPPORT */ 11844 /* Destroy L3 module protection mutex. */ 11845 if (NULL != soc->l3x_lock) { 11846 sal_mutex_destroy(soc->l3x_lock); 11847 soc->l3x_lock = NULL; 11848 } 11849 11850 /* Destroy FP module protection mutex. */ 11851 if (NULL != soc->fp_lock) { 11852 sal_mutex_destroy(soc->fp_lock); 11853 soc->fp_lock = NULL; 11854 } 11855 11856 #ifdef INCLUDE_XFLOW_MACSEC 11857 if (soc_feature(unit, soc_feature_xflow_macsec)) { 11858 /* Destroy XFLOW_MACSEC module protection mutex. */ 11859 if (NULL != soc->xflow_macsec_lock) { 11860 sal_mutex_destroy(soc->xflow_macsec_lock); 11861 soc->xflow_macsec_lock = NULL; 11862 } 11863 } 11864 #endif 11865 11866 if (soc->ipfixIntr) { 11867 sal_sem_destroy(soc->ipfixIntr); 11868 soc->ipfixIntr = NULL; 11869 } 11870 11871 #if defined(INCLUDE_REGEX) 11872 if (soc->ftreportIntr) { 11873 sal_sem_destroy(soc->ftreportIntr); 11874 soc->ftreportIntr = NULL; 11875 } 11876 #endif 11877 11878 #ifdef BCM_FLOWTRACKER_EXPORT_FIFO_SUPPORT 11879 if (soc->ftExportIntr) { 11880 sal_sem_destroy(soc->ftExportIntr); 11881 soc->ftExportIntr = NULL; 11882 } 11883 #endif /* BCM_FLOWTRACKER_EXPORT_FIFO_SUPPORT */ 11884 soc->ctr_evict_interval = 0; 11885 if (soc->ctrEvictIntr) { 11886 sal_sem_destroy(soc->ctrEvictIntr); 11887 soc->ctrEvictIntr = NULL; 11888 } 11889 11890 /* Destroy egress metering mutex. */ 11891 if (soc->egressMeteringMutex != NULL) { 11892 sal_mutex_destroy(soc->egressMeteringMutex); 11893 soc->egressMeteringMutex = NULL; 11894 } 11895 11896 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_APACHE_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 11897 if (SOC_IS_KATANAX(unit) || SOC_IS_TRIDENT2X(unit) || 11898 SOC_IS_TITAN2X(unit) || SOC_IS_TRIUMPH3(unit)) { 11899 /* Destroy llsMutex */ 11900 if (soc->llsMutex !=NULL) { 11901 sal_mutex_destroy(soc->llsMutex); 11902 soc->llsMutex = NULL; 11903 } 11904 } 11905 #endif 11906 11907 #if defined(BCM_TOMAHAWK_SUPPORT) 11908 if (SOC_IS_TOMAHAWKX(unit)) { 11909 /* Destroy idb_lock */ 11910 if (soc->idb_lock !=NULL) { 11911 sal_mutex_destroy(soc->idb_lock); 11912 soc->idb_lock = NULL; 11913 } 11914 } 11915 #endif 11916 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) 11917 if (soc_feature(unit, soc_feature_epc_linkflap_recover)) { 11918 /* Destroy linkscan_modport_map_lock_lock */ 11919 if (soc->linkscan_modport_map_lock !=NULL) { 11920 sal_mutex_destroy(soc->linkscan_modport_map_lock); 11921 soc->linkscan_modport_map_lock = NULL; 11922 } 11923 } 11924 #endif /* #(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) */ 11925 if (soc->soc_wc_ucode_dma_buf != NULL) { 11926 soc_cm_sfree(unit, soc->soc_wc_ucode_dma_buf); 11927 soc->soc_wc_ucode_dma_buf = NULL; 11928 } 11929 if (soc->soc_wc_ucode_dma_buf2 != NULL) { 11930 soc_cm_sfree(unit, soc->soc_wc_ucode_dma_buf2); 11931 soc->soc_wc_ucode_dma_buf2 = NULL; 11932 } 11933 11934 if (soc->mem_ser_info_lock) { 11935 sal_mutex_destroy(soc->mem_ser_info_lock); 11936 soc->mem_ser_info_lock = NULL; 11937 } 11938 11939 /* Destroy UDF module protection mutex. */ 11940 if (NULL != soc->udf_lock) { 11941 sal_mutex_destroy(soc->udf_lock); 11942 soc->udf_lock = NULL; 11943 } 11944 11945 sal_free(SOC_PERSIST(unit)); 11946 SOC_PERSIST(unit) = NULL; 11947 11948 sal_free(SOC_CONTROL(unit)); 11949 SOC_CONTROL(unit) = NULL; 11950 11951 if (--soc_ndev_attached == 0) { 11952 /* Work done after the last SOC device is detached. */ 11953 /* (currently nothing) */ 11954 LOG_ERROR(BSL_LS_SOC_COMMON, 11955 (BSL_META_U(unit, 11956 "soc_shutdown: all units detached\n"))); 11957 } 11958 } 11959 11960 #ifdef INCLUDE_KNET 11961 if (shutdown_knet) { 11962 soc_knet_cleanup(); 11963 } 11964 #endif 11965 11966 /* Free up the Level 2 warm boot cache */ 11967 soc_scache_detach(unit); 11968 11969 return SOC_E_NONE; 11970 } 11971 11972 STATIC int 11973 _soc_mem_scrub_read (int unit, soc_mem_t mem, int blk, int index_min, int index_max, void *entry_buffer) 11974 { 11975 int ser_flags[SOC_MAX_NUM_PIPES]; 11976 soc_acc_type_t mem_acc_type; 11977 int pipe_idx = 0; 11978 int num_pipe = 1; 11979 int ser_error = 0; 11980 uint32 ser_err[2]; 11981 soc_timeout_t to; 11982 int timeout_usec; 11983 sal_memset(&ser_flags, 0, sizeof(ser_flags)); 11984 11985 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_SHADOW_SUPPORT) 11986 if ((SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_CAM) && 11987 (!(SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_EXT_CAM)) && 11988 soc_feature(unit, soc_feature_xy_tcam_direct)) { 11989 for (pipe_idx = 0; pipe_idx < NUM_PIPE(unit); pipe_idx++) { 11990 ser_flags[pipe_idx] |= _SOC_SER_FLAG_XY_READ; 11991 } 11992 } 11993 #endif 11994 11995 if (NUM_PIPE(unit) == 2) { 11996 if (SOC_BLOCK_TYPE(unit, blk) == SOC_BLK_IPIPE || 11997 SOC_BLOCK_TYPE(unit, blk) == SOC_BLK_EPIPE) { 11998 mem_acc_type = SOC_MEM_ACC_TYPE(unit, mem); 11999 switch (mem_acc_type) { 12000 case _SOC_ACC_TYPE_PIPE_Y: 12001 num_pipe = 1; 12002 ser_flags[0] |= (_SOC_SER_FLAG_MULTI_PIPE | 12003 _SOC_MEM_ADDR_ACC_TYPE_PIPE_Y); 12004 if (!soc_mem_dmaable(unit, mem, blk)) { 12005 ser_flags[0] |= _SOC_SER_FLAG_NO_DMA; 12006 } 12007 break; 12008 case _SOC_ACC_TYPE_PIPE_X: 12009 num_pipe = 1; 12010 ser_flags[0] |= (_SOC_SER_FLAG_MULTI_PIPE | 12011 _SOC_MEM_ADDR_ACC_TYPE_PIPE_X); 12012 if (!soc_mem_dmaable(unit, mem, blk)) { 12013 ser_flags[0] |= _SOC_SER_FLAG_NO_DMA; 12014 } 12015 break; 12016 default: 12017 num_pipe = 2; 12018 /* For TCAMs, SER engine has not set SOC_MEM_ADDR_ACC_TYPE_PIPE_X 12019 * in pipe_x. If read table in specified pipe_x, it will not detect 12020 * parity error. So remove the flag to match the SER engine setting. 12021 */ 12022 if ((SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_CAM) && 12023 (!(SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_EXT_CAM))) { 12024 ser_flags[0] |= _SOC_SER_FLAG_MULTI_PIPE; 12025 } else { 12026 if (SOC_IS_TRIDENT3X(unit)) { 12027 ser_flags[0] |= (_SOC_SER_FLAG_MULTI_PIPE | 12028 _SOC_MEM_ADDR_ACC_TYPE_PIPE_0); 12029 } else { 12030 ser_flags[0] |= (_SOC_SER_FLAG_MULTI_PIPE | 12031 _SOC_MEM_ADDR_ACC_TYPE_PIPE_X); 12032 } 12033 } 12034 12035 if (SOC_IS_TRIDENT3X(unit)) { 12036 ser_flags[1] |= (_SOC_SER_FLAG_MULTI_PIPE | 12037 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1); 12038 } else { 12039 ser_flags[1] |= (_SOC_SER_FLAG_MULTI_PIPE | 12040 _SOC_MEM_ADDR_ACC_TYPE_PIPE_Y); 12041 } 12042 if (!soc_mem_dmaable(unit, mem, blk)) { 12043 ser_flags[0] |= _SOC_SER_FLAG_NO_DMA; 12044 ser_flags[1] |= _SOC_SER_FLAG_NO_DMA; 12045 } 12046 break; 12047 } 12048 } else { 12049 num_pipe = 1; 12050 ser_flags[0] = 0; 12051 if (!soc_mem_dmaable(unit, mem, blk)) { 12052 ser_flags[0] |= _SOC_SER_FLAG_NO_DMA; 12053 } 12054 } 12055 #if defined(BCM_TRIDENT_SUPPORT) 12056 if ((SOC_IS_TRIDENT(unit) || SOC_IS_TITAN(unit)) && 12057 (mem == EGR_VLANm)) { 12058 num_pipe = 1; 12059 ser_flags[0] = _SOC_SER_FLAG_NO_DMA; 12060 } 12061 #endif 12062 } else { 12063 num_pipe = 1; 12064 if (SOC_IS_APACHE(unit) && (mem == EGR_VLANm)) { 12065 ser_flags[0] = _SOC_SER_FLAG_NO_DMA; 12066 } else { 12067 ser_flags[0] = 0; 12068 } 12069 if (!soc_mem_dmaable(unit, mem, blk)) { 12070 ser_flags[0] |= _SOC_SER_FLAG_NO_DMA; 12071 } 12072 } 12073 if (soc_feature(unit, soc_feature_ser_scrub_delay)){ 12074 timeout_usec = 1000000; 12075 soc_timeout_init(&to, timeout_usec, 0); 12076 do { 12077 SOC_IF_ERROR_RETURN(READ_SER_ERROR_0r(unit, &ser_err[0])); 12078 SOC_IF_ERROR_RETURN(READ_SER_ERROR_1r(unit, &ser_err[1])); 12079 if (!soc_reg_field_get(unit, SER_ERROR_0r, ser_err[0], ERROR_0_VALf) || 12080 !soc_reg_field_get(unit, SER_ERROR_1r, ser_err[1], ERROR_1_VALf)) { 12081 ser_error = 0; 12082 } else { 12083 ser_error = 1; 12084 sal_usleep(1); 12085 } 12086 if (soc_timeout_check(&to)) { 12087 return SOC_E_TIMEOUT; 12088 break; 12089 } 12090 }while (ser_error); 12091 } 12092 for (pipe_idx = 0; pipe_idx < num_pipe; pipe_idx++) { 12093 SOC_IF_ERROR_RETURN(soc_mem_ser_read_range(unit, mem, blk, 12094 index_min, index_max, 12095 ser_flags[pipe_idx], 12096 entry_buffer)); 12097 } 12098 12099 return SOC_E_NONE; 12100 } 12101 12102 12103 12104 int 12105 soc_system_scrub(int unit) 12106 { 12107 int mem, blk, copyno = COPYNO_ALL; 12108 uint32 *table = NULL; 12109 soc_mem_t act_mem; 12110 int c = 0, entry_dw, table_size, tmax = 0; 12111 int index_cnt, index_min, index_max; 12112 #ifdef BCM_ESW_SUPPORT 12113 int skip = 0; 12114 #endif 12115 12116 if (soc_feature(unit, soc_feature_ser_system_scrub)) { 12117 /* do soc_system_scrub */ 12118 } else if (!(SOC_IS_TD_TT(unit) || SOC_IS_ENDURO(unit) || 12119 SOC_IS_SABER2(unit) || SOC_IS_KATANAX(unit) || 12120 SOC_IS_TRIUMPH3(unit)) || 12121 soc_property_get(unit, "skip_system_scrub", 0)) { 12122 return SOC_E_NONE; 12123 } 12124 12125 if (soc_feature(unit, soc_feature_tcam_scan_engine)) { 12126 (void) soc_ser_tcam_scan_engine_enable(unit, TRUE); 12127 } 12128 12129 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 12130 act_mem = mem; 12131 12132 if (!SOC_MEM_IS_VALID(unit, mem)) { 12133 continue; 12134 } 12135 if (soc_mem_index_count(unit, mem) == 0) { 12136 continue; 12137 } 12138 if (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP) { 12139 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 12140 "scrub: skipping mem %s (parity is disabled)\n"), 12141 SOC_MEM_NAME(unit, mem))); 12142 continue; 12143 } 12144 #ifdef BCM_TOMAHAWK3_SUPPORT 12145 if (SOC_IS_TOMAHAWK3(unit) && 12146 soc_th3_ser_test_skip_by_at(unit, mem, SOC_MEM_ACC_TYPE(unit, mem))) { 12147 continue; 12148 } 12149 #endif 12150 #ifdef BCM_ESW_SUPPORT 12151 _SOC_DRV_MEM_REUSE_MEM_STATE_NO_LOCK(unit, act_mem); 12152 #endif 12153 if (act_mem != mem) { 12154 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: skipping mem %s, act_mem %s (act_mem != mem)\n"), SOC_MEM_NAME(unit, mem), SOC_MEM_NAME(unit, act_mem))); 12155 continue; 12156 } 12157 if (SOC_MEM_SER_CORRECTION_TYPE(unit, mem) == 0) { 12158 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: skipping mem %s (ERR_CORRECTION = 0)\n"), SOC_MEM_NAME(unit, mem))); 12159 continue; 12160 } 12161 #ifdef BCM_SBUSDMA_SUPPORT 12162 if (soc_feature(unit, soc_feature_sbusdma)) { 12163 if (mem == ING_SER_FIFOm || mem == EGR_SER_FIFOm || 12164 mem == ISM_SER_FIFOm) { 12165 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: skipping mem %s (SER_FIFOm\n"), SOC_MEM_NAME(unit, mem))); 12166 continue; 12167 } 12168 } 12169 #endif /* BCM_SBUSDMA_SUPPORT */ 12170 SOC_MEM_BLOCK_ITER(unit, mem, blk) { 12171 copyno = blk; 12172 break; 12173 } 12174 if ((SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ETU) || 12175 (SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ESM)) { 12176 continue; 12177 } 12178 /* Skip IESMIF mems when ESM is not present */ 12179 else if (SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_IPIPE) { 12180 #ifdef BCM_TRIUMPH3_SUPPORT 12181 if (SOC_IS_TRIUMPH3(unit) && /* Needs update per chip */ 12182 SOC_MEM_ADDR_STAGE_EXTENDED(SOC_MEM_BASE(unit, mem)) == 0x9) { 12183 if (!soc_feature(unit, soc_feature_esm_support) || 12184 SAL_BOOT_QUICKTURN) { 12185 continue; 12186 } 12187 } 12188 #endif /* BCM_TRIUMPH3_SUPPORT */ 12189 } 12190 #ifdef BCM_TRIUMPH3_SUPPORT 12191 if (SOC_IS_TRIUMPH3(unit)) { 12192 /* Skip unused views */ 12193 if (mem == ESM_PKT_TYPE_ID_ONLYm || mem == ESM_PKT_TYPE_ID_DATA_ONLYm) { 12194 continue; 12195 } 12196 if (mem == MODPORT_MAP_M0m || mem == MODPORT_MAP_M1m || 12197 mem == MODPORT_MAP_M2m || mem == MODPORT_MAP_M3m) { 12198 continue; 12199 } 12200 } 12201 #endif /* BCM_TRIUMPH3_SUPPORT */ 12202 #ifdef BCM_TRIDENT_SUPPORT 12203 if (SOC_IS_TD_TT(unit) || SOC_IS_TD2_TT2(unit)) { 12204 int i, skip; 12205 static soc_mem_t mskip[] = { 12206 L3_ENTRY_IPV4_MULTICAST_Xm, 12207 L3_ENTRY_IPV4_MULTICAST_Ym, 12208 L3_ENTRY_IPV6_UNICAST_Xm, 12209 L3_ENTRY_IPV6_UNICAST_Ym 12210 }; 12211 skip = 0; 12212 for (i=0; i<COUNTOF(mskip); i++) { 12213 if (mem == mskip[i]) { 12214 skip = 1; 12215 break; 12216 } 12217 } 12218 if (skip) { 12219 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: skipping mem %s (part of mskip list)\n"), SOC_MEM_NAME(unit, mem))); 12220 continue; 12221 } 12222 /* Skip unused views */ 12223 if (mem == ING_SNAT_ONLYm || mem == ING_SNAT_DATA_ONLYm || 12224 mem == FP_GLOBAL_MASK_TCAMm || 12225 /* these are NOT unused views and can have parity/ecc errors */ 12226 /* mem == L2_ENTRY_LPm || mem == L3_ENTRY_LPm || */ 12227 /* mem == VLAN_XLATE_LPm || mem == EGR_VLAN_XLATE_LPm || */ 12228 mem == VLAN_SUBNET_DATA_ONLYm || mem == L3_DEFIP_ALPM_RAWm) { 12229 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: skipping mem %s (unused views)\n"), SOC_MEM_NAME(unit, mem))); 12230 continue; 12231 } 12232 } 12233 #if defined(BCM_TRIDENT2_SUPPORT) 12234 if (SOC_IS_TD2_TT2(unit) && !SOC_IS_APACHE(unit)) { 12235 if (mem == L3_DEFIP_ALPM_IPV4m || mem == L3_DEFIP_ALPM_IPV4_1m || 12236 mem == L3_DEFIP_ALPM_IPV6_64m || mem == L3_DEFIP_ALPM_IPV6_64_1m || 12237 mem == L3_DEFIP_ALPM_IPV6_128m) { 12238 /* We call a separate traverse routine to only access the 12239 memory with the right view */ 12240 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: skipping mem %s (will call separate traverse routine)\n"), SOC_MEM_NAME(unit, mem))); 12241 continue; 12242 } 12243 } 12244 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 12245 /* we can't scrub those memory, they can lead to unnecessary SER corrections */ 12246 if (SOC_IS_TD2P_TT2P(unit) || SOC_IS_APACHE(unit)) { 12247 if (mem == REPLICATION_FIFO_BANK0m || 12248 mem == REPLICATION_FIFO_BANK1m || 12249 mem == MMU_ENQ_PBI_DBm) { 12250 LOG_VERBOSE(BSL_LS_SOC_SER, 12251 (BSL_META_U(unit, "scrub: skipping mem %s (will call separate traverse routine)\n"), 12252 SOC_MEM_NAME(unit, mem))); 12253 continue; 12254 } 12255 } 12256 /* 12257 * We skip EFP_TCAM table since parity error happens on this table on TD2+ 12258 * is detected by memscan thread now. 12259 */ 12260 if (SOC_IS_TD2P_TT2P(unit)) { 12261 if (mem == EFP_TCAMm) { 12262 LOG_VERBOSE(BSL_LS_SOC_SER, 12263 (BSL_META_U(unit, "scrub: skipping mem %s (memscan detect error)\n"), 12264 SOC_MEM_NAME(unit, mem))); 12265 continue; 12266 } 12267 } 12268 #endif /* BCM_TRIDENT2PLUS_SUPPORT */ 12269 #if defined(BCM_APACHE_SUPPORT) 12270 /* we can't scrub those memory, they can lead to unnecessary SER corrections */ 12271 if (SOC_IS_APACHE(unit)) { 12272 if((mem == MMU_MAPPER_X_LSBm) || (mem == MMU_MAPPER_Y_LSBm)) { 12273 LOG_VERBOSE(BSL_LS_SOC_SER, 12274 (BSL_META_U(unit, "scrub: skipping mem %s (will call separate traverse routine)\n"), 12275 SOC_MEM_NAME(unit, mem))); 12276 continue; 12277 } 12278 } 12279 #endif /* APACHE_SUPPORT*/ 12280 #endif 12281 #endif /* BCM_TRIDENT_SUPPORT */ 12282 #if defined(BCM_TRX_SUPPORT) 12283 if (SOC_IS_TRX(unit)) { 12284 /* Skip unused views */ 12285 if (mem == MY_STATION_TCAM_DATA_ONLYm || mem == L2_USER_ENTRY_DATA_ONLYm || 12286 mem == L3_DEFIP_DATA_ONLYm || mem == L3_DEFIP_PAIR_128_DATA_ONLYm || 12287 mem == L3_DEFIP_128_DATA_ONLYm || mem == L3_DEFIP_128_ONLYm || 12288 mem == L3_DEFIP_ONLYm || mem == L3_DEFIP_PAIR_128_ONLYm || 12289 mem == L3_ENTRY_ONLYm) { 12290 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: skipping mem %s (unused TRX views)\n"), SOC_MEM_NAME(unit, mem))); 12291 continue; 12292 } 12293 } 12294 #endif /* BCM_TRX_SUPPORT */ 12295 #ifdef BCM_KATANA_SUPPORT 12296 if (SOC_IS_KATANAX(unit)) { 12297 if(mem == XPORT_WC_UCMEM_DATAm) { 12298 continue; 12299 } 12300 } 12301 #endif /* BCM_KATANA_SUPPORT */ 12302 #if defined (BCM_SABER2_SUPPORT) 12303 if (SOC_IS_SABER2(unit)) { 12304 if (mem == RXLP_DEBUG_COUNTER0m || mem == RXLP_DEBUG_COUNTER1m || 12305 mem == RXLP_DEBUG_COUNTER2m || mem == RXLP_DEBUG_COUNTER3m || 12306 mem == RXLP_DEBUG_COUNTER4m || mem == RXLP_DEBUG_COUNTER5m || 12307 mem == RXLP_DEBUG_COUNTER6m || mem == RXLP_DEBUG_COUNTER7m || 12308 mem == RXLP_DEBUG_COUNTER8m || mem == TXLP_DEBUG_COUNTER0m || 12309 mem == TXLP_DEBUG_COUNTER1m || mem == TXLP_DEBUG_COUNTER2m || 12310 mem == TXLP_DEBUG_COUNTER3m || mem == TXLP_DEBUG_COUNTER4m || 12311 mem == TXLP_DEBUG_COUNTER5m || mem == TXLP_DEBUG_COUNTER6m || 12312 mem == TXLP_DEBUG_COUNTER7m || mem == TXLP_DEBUG_COUNTER8m ) { 12313 continue; 12314 } 12315 } 12316 #endif 12317 12318 #if defined(BCM_TOMAHAWK_SUPPORT) 12319 if (SOC_IS_TOMAHAWKX(unit)) { 12320 if (soc_th_check_scrub_skip(unit, mem, 1)) { 12321 continue; 12322 } 12323 } 12324 #endif /* BCM_TOMAHAWK_SUPPORT */ 12325 #if defined(BCM_GREYHOUND_SUPPORT) 12326 if (SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit)) { 12327 if (mem == VLAN_SUBNET_DATA_ONLYm || 12328 mem == MODPORT_MAP_IMm || mem == MODPORT_MAP_EMm || 12329 mem == CPU_COS_MAP_ONLYm || mem == L2_ENTRY_ONLYm || 12330 mem == L2_USER_ENTRY_ONLYm || mem == VLAN_SUBNET_ONLYm ) { 12331 continue; 12332 } 12333 } 12334 #endif /* BCM_GREYHOUND_SUPPORT */ 12335 12336 #ifdef BCM_ESW_SUPPORT 12337 _SOC_MEM_SKIP_SCRUB(unit, mem, skip); 12338 if (skip == 1) { 12339 continue; 12340 } 12341 #endif 12342 12343 entry_dw = soc_mem_entry_words(unit, mem); 12344 index_cnt = soc_mem_index_count(unit, mem); 12345 table_size = index_cnt * entry_dw * 4; 12346 index_max = index_cnt - 1; 12347 index_min = soc_mem_index_min(unit, mem); 12348 if (table == NULL) { 12349 table = soc_cm_salloc(unit, table_size, "scrub"); 12350 if (table == NULL) { 12351 return SOC_E_MEMORY; 12352 } 12353 tmax = table_size; 12354 } else { 12355 if (table_size > tmax) { 12356 soc_cm_sfree(unit, table); 12357 table = soc_cm_salloc(unit, table_size, "scrub"); 12358 if (table == NULL) { 12359 return SOC_E_MEMORY; 12360 } 12361 tmax = table_size; 12362 } 12363 } 12364 SOC_MEM_BLOCK_ITER(unit, mem, blk) { 12365 #if defined(BCM_TRIUMPH3_SUPPORT) 12366 if (SOC_IS_TRIUMPH3(unit)) { 12367 if (mem == PORT_EHG_RX_TUNNEL_DATAm || 12368 mem == PORT_EHG_RX_TUNNEL_MASKm || 12369 mem == PORT_EHG_TX_TUNNEL_DATAm) { 12370 if (!_soc_tr3_port_mem_blk_enabled(unit, blk)) { 12371 continue; 12372 } 12373 } 12374 } 12375 #endif /* BCM_TRIUMPH3_SUPPORT */ 12376 12377 #if defined(BCM_TOMAHAWK_SUPPORT) 12378 if (SOC_IS_TOMAHAWKX(unit)) { 12379 int i, num_inst_to_scrub = 0, acc_type_list[8], rv; 12380 uint32 ser_flags; 12381 if (SOC_TH_MEM_CHK_IFP_TCAM(mem) || 12382 SOC_TH_MEM_CHK_IFP_TCAM_WIDE(mem)) { 12383 if (soc_th_ifp_tcam_dma_read(unit, mem, blk, table, 12384 (mem == IFP_TCAMm || 12385 mem == IFP_TCAM_WIDEm), 12386 NULL 12387 ) >= 0) { 12388 /* Do nothing - with data */ 12389 c++; 12390 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "Scrub: %s\n"), SOC_MEM_NAME(unit, mem))); 12391 } 12392 continue; /* skip subsequent soc_mem_read_range irrespecive of pass, fail */ 12393 } 12394 #ifdef BCM_TOMAHAWK3_SUPPORT 12395 if (SOC_IS_TOMAHAWK3(unit)) { 12396 int skip_mem; 12397 /* Check if the memory needs to be skipped due to the 12398 * port macro it's associated with being down */ 12399 rv = soc_th3_skip_obm_mem_if_pm_down(unit, mem, &skip_mem); 12400 if (SOC_FAILURE(rv)) { 12401 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, "PM Down check error: %s\n"), SOC_MEM_NAME(unit, mem))); 12402 continue; 12403 } 12404 12405 /* skip reading this memory because we can't read it if 12406 * the PM is down */ 12407 if (skip_mem) { 12408 continue; 12409 } 12410 12411 rv = soc_th3_check_scrub_info(unit, mem, blk, copyno, 12412 &num_inst_to_scrub, acc_type_list); 12413 } else 12414 #endif 12415 { 12416 rv = soc_th_check_scrub_info(unit, mem, blk, copyno, 12417 &num_inst_to_scrub, acc_type_list); 12418 } 12419 if (SOC_FAILURE(rv)) { 12420 continue; /* skip subsequent soc_mem_read_range */ 12421 } 12422 assert(num_inst_to_scrub <= 8); 12423 for (i = 0; i < num_inst_to_scrub; i++) { 12424 #ifdef BCM_TOMAHAWK3_SUPPORT 12425 if (SOC_IS_TOMAHAWK3(unit) && 12426 soc_th3_ser_test_skip_by_at(unit, mem, acc_type_list[i])) { 12427 continue; 12428 } 12429 #endif 12430 ser_flags = 0; 12431 ser_flags |= _SOC_SER_FLAG_DISCARD_READ; 12432 ser_flags |= _SOC_SER_FLAG_MULTI_PIPE; 12433 ser_flags |= acc_type_list[i]; 12434 if (!soc_mem_dmaable(unit, mem, blk)) { 12435 ser_flags |= _SOC_SER_FLAG_NO_DMA; 12436 } 12437 if (soc_mem_ser_read_range(unit, mem, blk, index_min, 12438 index_max, ser_flags, 12439 table) >= 0) { 12440 c++; 12441 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "Scrub: %s (instance %d)\n"), SOC_MEM_NAME(unit, mem), acc_type_list[i])); 12442 } 12443 } 12444 if (num_inst_to_scrub) { 12445 continue; /* skip subsequent soc_mem_read_range 12446 irrespecive of pass, fail */ 12447 } 12448 12449 /* In some cases, soc_th_check_scrub_info() sets num_inst_to_scrub with 0, 12450 * soc_system_scrub() will not read the memories. For unique memories in multi-pipes, 12451 * soc_mem_read_range() will read them in new views with suffix '_PIPEx'. */ 12452 if (soc_mem_read_range(unit, mem, blk, index_min, 12453 index_max, table) >= 0) { 12454 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "Scrub read mem:%s\n"), SOC_MEM_NAME(unit, mem))); 12455 } 12456 } else 12457 #endif /* BCM_TOMAHAWK_SUPPORT */ 12458 { 12459 if ( _soc_mem_scrub_read(unit, mem, blk, index_min, index_max, table) >= 0) { 12460 /* Do nothing */ 12461 c++; 12462 #if !defined(SOC_NO_NAMES) 12463 #if defined(BCM_ESW_SUPPORT) || \ 12464 defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) 12465 LOG_INFO(BSL_LS_SOC_SER, 12466 (BSL_META_U(unit, 12467 "Scrub: %s\n"), SOC_MEM_NAME(unit, mem))); 12468 #endif 12469 #else 12470 LOG_INFO(BSL_LS_SOC_SOCMEM, 12471 (BSL_META_U(unit, 12472 "Scrub: %d\n"), mem)); 12473 #endif 12474 } 12475 } 12476 } 12477 } 12478 if (table) { 12479 soc_cm_sfree(unit, table); 12480 LOG_VERBOSE(BSL_LS_SOC_SER, 12481 (BSL_META_U(unit, 12482 "Mem scrub count: %d tmax: %d\n"), c, tmax)); 12483 } 12484 #ifdef ALPM_ENABLE 12485 #ifdef BCM_TRIDENT2_SUPPORT 12486 if (SOC_IS_TRIDENT2X(unit) && !SOC_IS_APACHE(unit)) { 12487 SOC_IF_ERROR_RETURN(soc_trident2_alpm_scrub(unit)); 12488 } 12489 #endif /* BCM_TRIDENT2_SUPPORT */ 12490 #endif /* ALPM_ENABLE */ 12491 return soc_ser_reg_load_scrub(unit, 0); 12492 } 12493 #endif /* BCM_WARM_BOOT_SUPPORT */ 12494 12495 #ifdef BCM_HERCULES15_SUPPORT 12496 /* 12497 * The 5675A0 has some latches in a test path that runs between all 12498 * of the XAUI macs. To ensure that the test path is initialized 12499 * correctly, all macs must be enabled, and a low frequency reference 12500 * clock must be given to unused ports. 12501 */ 12502 STATIC void 12503 soc_reset_bcm5675_a0(int unit, uint16 dev_id) 12504 { 12505 uint64 xctrl; 12506 int spl; 12507 12508 COMPILER_REFERENCE(dev_id); 12509 12510 /* 12511 * Enable core_clk to all macs. 12512 * This does not take effect until the next soft reset. 12513 */ 12514 WRITE_CMIC_CLK_ENABLEr(unit, 0x1ff); 12515 12516 /* Block interrupts while resetting */ 12517 spl = sal_splhi(); 12518 SOC_CONTROL(unit)->soc_flags |= SOC_F_BUSY; 12519 soc_pci_write(unit, CMIC_CONFIG, 12520 soc_pci_read(unit, CMIC_CONFIG) | CC_RESET_CPS); 12521 /* Unblock interrupts */ 12522 sal_spl(spl); 12523 12524 if (SAL_BOOT_QUICKTURN) { 12525 sal_usleep(10 * MILLISECOND_USEC); 12526 } else { 12527 sal_usleep(1 * MILLISECOND_USEC); 12528 } 12529 12530 soc_endian_config(unit); /* reset cleared endian settings */ 12531 /* Block interrupts */ 12532 spl = sal_splhi(); 12533 SOC_CONTROL(unit)->soc_flags &= ~SOC_F_BUSY; 12534 /* Unblock interrupts */ 12535 sal_spl(spl); 12536 12537 /* 12538 * Force all ports (even disabled ones) to run for a little 12539 * while by clearing iddq and pwrdwn. The definition of little 12540 * while depends on the refclock given to external ports, which 12541 * is assumed here to be at least 100KHz or so 12542 */ 12543 /* defaults except for iddq=0 pwrdwn=0 */ 12544 COMPILER_64_SET(xctrl, 0, 0x181); 12545 soc_reg64_write(unit, 0x500201, xctrl); /* MAC_XGXS_CTRLr */ 12546 soc_reg64_write(unit, 0x600201, xctrl); 12547 soc_reg64_write(unit, 0x700201, xctrl); 12548 soc_reg64_write(unit, 0x800201, xctrl); 12549 soc_reg64_write(unit, 0x100201, xctrl); 12550 soc_reg64_write(unit, 0x200201, xctrl); 12551 soc_reg64_write(unit, 0x300201, xctrl); 12552 soc_reg64_write(unit, 0x400201, xctrl); 12553 12554 sal_usleep(60); 12555 12556 /* back to reset defaults: iddq=1 pwrdwn=1 */ 12557 COMPILER_64_SET(xctrl, 0, 0x1e1); 12558 soc_reg64_write(unit, 0x500201, xctrl); 12559 soc_reg64_write(unit, 0x600201, xctrl); 12560 soc_reg64_write(unit, 0x700201, xctrl); 12561 soc_reg64_write(unit, 0x800201, xctrl); 12562 soc_reg64_write(unit, 0x100201, xctrl); 12563 soc_reg64_write(unit, 0x200201, xctrl); 12564 soc_reg64_write(unit, 0x300201, xctrl); 12565 soc_reg64_write(unit, 0x400201, xctrl); 12566 } 12567 #endif /* BCM_HERCULES15_SUPPORT */ 12568 12569 #ifdef BCM_XGS3_SWITCH_SUPPORT 12570 /* 12571 * Reset VCO sequencer. 12572 */ 12573 void 12574 soc_xgxs_lcpll_reset(int unit) 12575 { 12576 if (soc_feature(unit, soc_feature_xgxs_lcpll)) { 12577 uint32 val; 12578 uint16 dev_id; 12579 uint8 rev_id; 12580 12581 soc_cm_get_id(unit, &dev_id, &rev_id); 12582 12583 READ_CMIC_XGXS_PLL_CONTROL_1r(unit, &val); 12584 #if defined(BCM_RAPTOR_SUPPORT) 12585 if (soc_reg_field_valid 12586 (unit, CMIC_XGXS_PLL_CONTROL_1r, SEL_DIFF_CLOCKf)) { 12587 uint32 xtal_sel, default_val = 0; 12588 default_val = (SOC_IS_RAVEN(unit) && 12589 (rev_id == BCM56224_B0_REV_ID)) ? 1 : 0; 12590 if (soc_property_get(unit, 12591 spn_XGXS_LCPLL_XTAL_REFCLK, default_val) == 0) { 12592 xtal_sel = 1; 12593 } else { 12594 xtal_sel = 0; 12595 } 12596 soc_reg_field_set 12597 (unit, CMIC_XGXS_PLL_CONTROL_1r, 12598 &val, SEL_DIFF_CLOCKf, xtal_sel); 12599 } 12600 #endif /* BCM_RAPTOR_SUPPORT */ 12601 12602 soc_reg_field_set(unit, CMIC_XGXS_PLL_CONTROL_1r, &val, RESETf, 1); 12603 WRITE_CMIC_XGXS_PLL_CONTROL_1r(unit, val); 12604 soc_reg_field_set(unit, CMIC_XGXS_PLL_CONTROL_1r, &val, RESETf, 0); 12605 sal_usleep(50); 12606 WRITE_CMIC_XGXS_PLL_CONTROL_1r(unit, val); 12607 sal_usleep(50); 12608 } 12609 } 12610 12611 /* 12612 * Check for PLL lock for Bradley 12613 */ 12614 void 12615 _bradley_lcpll_lock_check(int unit) 12616 { 12617 uint32 val; 12618 int pll_lock_usec; 12619 int locked = 0; 12620 int retry = 3; 12621 soc_timeout_t to; 12622 12623 /* Check if first LCPLL locked */ 12624 while (!locked && retry--) { 12625 #if defined(BCM_HB_GW_SUPPORT) 12626 READ_CMIC_XGXS0_PLL_CONTROL_1r(unit, &val); 12627 soc_reg_field_set(unit, CMIC_XGXS0_PLL_CONTROL_1r, &val, 12628 PLL_SEQSTARTf, 1); 12629 WRITE_CMIC_XGXS0_PLL_CONTROL_1r(unit, val); 12630 sal_usleep(100); 12631 12632 READ_CMIC_XGXS0_PLL_CONTROL_1r(unit, &val); 12633 soc_reg_field_set(unit, CMIC_XGXS0_PLL_CONTROL_1r, &val, 12634 PLLFORCECAPDONE_ENf, 1); 12635 soc_reg_field_set(unit, CMIC_XGXS0_PLL_CONTROL_1r, &val, 12636 PLLFORCECAPDONEf, 1); 12637 soc_reg_field_set(unit, CMIC_XGXS0_PLL_CONTROL_1r, &val, 12638 PLLFORCECAPPASS_ENf, 1); 12639 soc_reg_field_set(unit, CMIC_XGXS0_PLL_CONTROL_1r, &val, 12640 PLLFORCECAPPASSf, 1); 12641 WRITE_CMIC_XGXS0_PLL_CONTROL_1r(unit, val); 12642 sal_usleep(100); 12643 12644 READ_CMIC_XGXS0_PLL_CONTROL_1r(unit, &val); 12645 soc_reg_field_set(unit, CMIC_XGXS0_PLL_CONTROL_1r, &val, 12646 PLL_SEQSTARTf, 0); 12647 WRITE_CMIC_XGXS0_PLL_CONTROL_1r(unit, val); 12648 sal_usleep(50); 12649 #endif 12650 pll_lock_usec = 500000; 12651 soc_timeout_init(&to, pll_lock_usec, 0); 12652 while (!soc_timeout_check(&to)) { 12653 READ_CMIC_XGXS0_PLL_CONTROL_2r(unit, &val); 12654 locked = soc_reg_field_get(unit, CMIC_XGXS0_PLL_CONTROL_2r, 12655 val, CMIC_XGPLL_LOCKf); 12656 if (locked) { 12657 break; 12658 } 12659 } 12660 } 12661 12662 if (!locked) { 12663 LOG_ERROR(BSL_LS_SOC_COMMON, 12664 (BSL_META_U(unit, 12665 "bradley_lcpll_lock_check: LCPLL0 not locked on unit %d " 12666 "status = 0x%08x\n"), 12667 unit, val)); 12668 } 12669 12670 /* Now check for second LCPLL */ 12671 locked = 0; 12672 retry = 3; 12673 while (!locked && retry--) { 12674 #if defined(BCM_HB_GW_SUPPORT) 12675 READ_CMIC_XGXS1_PLL_CONTROL_1r(unit, &val); 12676 soc_reg_field_set(unit, CMIC_XGXS1_PLL_CONTROL_1r, &val, 12677 PLL_SEQSTARTf, 1); 12678 WRITE_CMIC_XGXS1_PLL_CONTROL_1r(unit, val); 12679 sal_usleep(100); 12680 12681 READ_CMIC_XGXS1_PLL_CONTROL_1r(unit, &val); 12682 soc_reg_field_set(unit, CMIC_XGXS1_PLL_CONTROL_1r, &val, 12683 PLLFORCECAPDONE_ENf, 1); 12684 soc_reg_field_set(unit, CMIC_XGXS1_PLL_CONTROL_1r, &val, 12685 PLLFORCECAPDONEf, 1); 12686 soc_reg_field_set(unit, CMIC_XGXS1_PLL_CONTROL_1r, &val, 12687 PLLFORCECAPPASS_ENf, 1); 12688 soc_reg_field_set(unit, CMIC_XGXS1_PLL_CONTROL_1r, &val, 12689 PLLFORCECAPPASSf, 1); 12690 WRITE_CMIC_XGXS1_PLL_CONTROL_1r(unit, val); 12691 sal_usleep(100); 12692 12693 READ_CMIC_XGXS1_PLL_CONTROL_1r(unit, &val); 12694 soc_reg_field_set(unit, CMIC_XGXS1_PLL_CONTROL_1r, &val, 12695 PLL_SEQSTARTf, 0); 12696 WRITE_CMIC_XGXS1_PLL_CONTROL_1r(unit, val); 12697 sal_usleep(50); 12698 #endif 12699 pll_lock_usec = 500000; 12700 soc_timeout_init(&to, pll_lock_usec, 0); 12701 while (!soc_timeout_check(&to)) { 12702 READ_CMIC_XGXS1_PLL_CONTROL_2r(unit, &val); 12703 locked = soc_reg_field_get(unit, CMIC_XGXS1_PLL_CONTROL_2r, 12704 val, CMIC_XGPLL_LOCKf); 12705 if (locked) { 12706 break; 12707 } 12708 } 12709 } 12710 12711 if (!locked) { 12712 LOG_ERROR(BSL_LS_SOC_COMMON, 12713 (BSL_META_U(unit, 12714 "bradley_lcpll_lock_check: LCPLL1 not locked on unit %d " 12715 "status = 0x%08x\n"), 12716 unit, val)); 12717 } 12718 12719 } 12720 12721 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 12722 12723 #ifdef BCM_BIGMAC_SUPPORT 12724 #ifdef BCM_TRIUMPH_SUPPORT 12725 static const struct { 12726 soc_reg_t mdio_conf_reg; 12727 int hc_chan; 12728 } tr_xgxs_map[] = { 12729 { INVALIDr, -1, }, /* port 0 */ 12730 { INVALIDr, -1, }, /* port 1 */ 12731 { CMIC_XGXS_MDIO_CONFIG_0r, 0, }, /* port 2 */ 12732 { CMIC_XGXS_MDIO_CONFIG_0r, 1, }, /* port 3 */ 12733 { CMIC_XGXS_MDIO_CONFIG_0r, 2, }, /* port 4 */ 12734 { CMIC_XGXS_MDIO_CONFIG_0r, 3, }, /* port 5 */ 12735 { CMIC_XGXS_MDIO_CONFIG_1r, 0, }, /* port 6 */ 12736 { CMIC_XGXS_MDIO_CONFIG_1r, 1, }, /* port 7 */ 12737 { INVALIDr, -1, }, /* port 8 */ 12738 { INVALIDr, -1, }, /* port 9 */ 12739 { INVALIDr, -1, }, /* port 10 */ 12740 { INVALIDr, -1, }, /* port 11 */ 12741 { INVALIDr, -1, }, /* port 12 */ 12742 { INVALIDr, -1, }, /* port 13 */ 12743 { CMIC_XGXS_MDIO_CONFIG_2r, 0, }, /* port 14 */ 12744 { CMIC_XGXS_MDIO_CONFIG_2r, 1, }, /* port 15 */ 12745 { CMIC_XGXS_MDIO_CONFIG_2r, 2, }, /* port 16 */ 12746 { CMIC_XGXS_MDIO_CONFIG_2r, 3, }, /* port 17 */ 12747 { CMIC_XGXS_MDIO_CONFIG_1r, 2, }, /* port 18 */ 12748 { CMIC_XGXS_MDIO_CONFIG_1r, 3, }, /* port 19 */ 12749 { INVALIDr, -1, }, /* port 20 */ 12750 { INVALIDr, -1, }, /* port 21 */ 12751 { INVALIDr, -1, }, /* port 22 */ 12752 { INVALIDr, -1, }, /* port 23 */ 12753 { INVALIDr, -1, }, /* port 24 */ 12754 { INVALIDr, -1, }, /* port 25 */ 12755 { CMIC_XGXS_MDIO_CONFIG_3r, 0, }, /* port 26 */ 12756 { CMIC_XGXS_MDIO_CONFIG_5r, 0, }, /* port 27 */ 12757 { CMIC_XGXS_MDIO_CONFIG_6r, -1, }, /* port 28 */ 12758 { CMIC_XGXS_MDIO_CONFIG_7r, -1, }, /* port 29 */ 12759 { CMIC_XGXS_MDIO_CONFIG_8r, -1, }, /* port 30 */ 12760 { CMIC_XGXS_MDIO_CONFIG_9r, -1, }, /* port 31 */ 12761 { CMIC_XGXS_MDIO_CONFIG_3r, 1, }, /* port 32 */ 12762 { CMIC_XGXS_MDIO_CONFIG_3r, 2, }, /* port 33 */ 12763 { CMIC_XGXS_MDIO_CONFIG_3r, 3, }, /* port 34 */ 12764 { CMIC_XGXS_MDIO_CONFIG_4r, 0, }, /* port 35 */ 12765 { CMIC_XGXS_MDIO_CONFIG_4r, 1, }, /* port 36 */ 12766 { INVALIDr, -1, }, /* port 37 */ 12767 { INVALIDr, -1, }, /* port 38 */ 12768 { INVALIDr, -1, }, /* port 39 */ 12769 { INVALIDr, -1, }, /* port 40 */ 12770 { INVALIDr, -1, }, /* port 41 */ 12771 { INVALIDr, -1, }, /* port 42 */ 12772 { CMIC_XGXS_MDIO_CONFIG_5r, 1, }, /* port 43 */ 12773 { CMIC_XGXS_MDIO_CONFIG_5r, 2, }, /* port 44 */ 12774 { CMIC_XGXS_MDIO_CONFIG_5r, 3, }, /* port 45 */ 12775 { CMIC_XGXS_MDIO_CONFIG_4r, 2, }, /* port 46 */ 12776 { CMIC_XGXS_MDIO_CONFIG_4r, 3, }, /* port 47 */ 12777 { INVALIDr, -1, }, /* port 48 */ 12778 { INVALIDr, -1, }, /* port 49 */ 12779 { INVALIDr, -1, }, /* port 50 */ 12780 { INVALIDr, -1, }, /* port 51 */ 12781 { INVALIDr, -1, }, /* port 52 */ 12782 { INVALIDr, -1, }, /* port 53 */ 12783 }; 12784 #endif /* BCM_TRIUMPH_SUPPORT */ 12785 12786 STATIC int 12787 _soc_xgxs_mdio_setup(int unit, int port) 12788 { 12789 soc_reg_t reg = INVALIDr; 12790 uint32 rval; 12791 uint32 devad = 0; 12792 int skip = FALSE; 12793 12794 if (!SOC_PORT_VALID(unit, port)) 12795 { 12796 return SOC_E_PORT; 12797 } 12798 12799 if (SOC_IS_FB_FX_HX(unit)) { 12800 switch(port) { 12801 case 24: reg = CMIC_XGXS_MDIO_CONFIG_0r; break; 12802 case 25: reg = CMIC_XGXS_MDIO_CONFIG_1r; break; 12803 case 26: reg = CMIC_XGXS_MDIO_CONFIG_2r; break; 12804 case 27: reg = CMIC_XGXS_MDIO_CONFIG_3r; break; 12805 default: return SOC_E_PARAM; 12806 } 12807 } 12808 12809 #ifdef BCM_GXPORT_SUPPORT 12810 if (SOC_IS_HB_GW(unit)) { 12811 switch(port) { 12812 case 0: reg = CMIC_XGXS_MDIO_CONFIG_0r; break; 12813 case 1: reg = CMIC_XGXS_MDIO_CONFIG_1r; break; 12814 case 2: reg = CMIC_XGXS_MDIO_CONFIG_2r; break; 12815 case 3: reg = CMIC_XGXS_MDIO_CONFIG_3r; break; 12816 case 4: reg = CMIC_XGXS_MDIO_CONFIG_4r; break; 12817 case 5: reg = CMIC_XGXS_MDIO_CONFIG_5r; break; 12818 case 6: reg = CMIC_XGXS_MDIO_CONFIG_6r; break; 12819 case 7: reg = CMIC_XGXS_MDIO_CONFIG_7r; break; 12820 case 8: reg = CMIC_XGXS_MDIO_CONFIG_8r; break; 12821 case 9: reg = CMIC_XGXS_MDIO_CONFIG_9r; break; 12822 case 10: reg = CMIC_XGXS_MDIO_CONFIG_10r; break; 12823 case 11: reg = CMIC_XGXS_MDIO_CONFIG_11r; break; 12824 case 12: reg = CMIC_XGXS_MDIO_CONFIG_12r; break; 12825 case 13: reg = CMIC_XGXS_MDIO_CONFIG_13r; break; 12826 case 14: reg = CMIC_XGXS_MDIO_CONFIG_14r; break; 12827 case 15: reg = CMIC_XGXS_MDIO_CONFIG_15r; break; 12828 case 16: reg = CMIC_XGXS_MDIO_CONFIG_16r; break; 12829 case 17: reg = CMIC_XGXS_MDIO_CONFIG_17r; break; 12830 case 18: reg = CMIC_XGXS_MDIO_CONFIG_18r; break; 12831 case 19: reg = CMIC_XGXS_MDIO_CONFIG_19r; break; 12832 default: return SOC_E_PARAM; 12833 } 12834 } 12835 #endif 12836 12837 #ifdef BCM_SCORPION_SUPPORT 12838 if (SOC_IS_SC_CQ(unit)) { 12839 devad = 5; 12840 switch(port) { 12841 case 1: reg = CMIC_XGXS_MDIO_CONFIG_0r; break; 12842 case 2: reg = CMIC_XGXS_MDIO_CONFIG_1r; break; 12843 case 3: reg = CMIC_XGXS_MDIO_CONFIG_2r; break; 12844 case 4: reg = CMIC_XGXS_MDIO_CONFIG_3r; break; 12845 case 5: reg = CMIC_XGXS_MDIO_CONFIG_4r; break; 12846 case 6: reg = CMIC_XGXS_MDIO_CONFIG_5r; break; 12847 case 7: reg = CMIC_XGXS_MDIO_CONFIG_6r; break; 12848 case 8: reg = CMIC_XGXS_MDIO_CONFIG_7r; break; 12849 case 9: reg = CMIC_XGXS_MDIO_CONFIG_8r; break; 12850 case 10: reg = CMIC_XGXS_MDIO_CONFIG_9r; break; 12851 case 11: reg = CMIC_XGXS_MDIO_CONFIG_10r; break; 12852 case 12: reg = CMIC_XGXS_MDIO_CONFIG_11r; break; 12853 case 13: reg = CMIC_XGXS_MDIO_CONFIG_12r; break; 12854 case 14: reg = CMIC_XGXS_MDIO_CONFIG_13r; break; 12855 case 15: reg = CMIC_XGXS_MDIO_CONFIG_14r; break; 12856 case 16: reg = CMIC_XGXS_MDIO_CONFIG_15r; break; 12857 case 17: reg = CMIC_XGXS_MDIO_CONFIG_16r; break; 12858 case 18: reg = CMIC_XGXS_MDIO_CONFIG_17r; break; 12859 case 19: reg = CMIC_XGXS_MDIO_CONFIG_18r; break; 12860 case 20: reg = CMIC_XGXS_MDIO_CONFIG_19r; break; 12861 case 21: reg = CMIC_XGXS_MDIO_CONFIG_20r; break; 12862 case 22: reg = CMIC_XGXS_MDIO_CONFIG_21r; break; 12863 case 23: reg = CMIC_XGXS_MDIO_CONFIG_22r; break; 12864 case 24: reg = CMIC_XGXS_MDIO_CONFIG_23r; break; 12865 case 25: 12866 case 26: 12867 case 27: 12868 case 28: 12869 reg = CMIC_XGXS_MDIO_CONFIG_24r; 12870 devad = 0; 12871 break; 12872 default: return SOC_E_PARAM; 12873 } 12874 } 12875 #endif 12876 12877 #ifdef BCM_TRIUMPH_SUPPORT 12878 if (SOC_IS_TRIUMPH(unit) || SOC_IS_VALKYRIE(unit)) { 12879 reg = tr_xgxs_map[port].mdio_conf_reg; 12880 devad = 5; 12881 if (reg == INVALIDr) { 12882 return SOC_E_PARAM; 12883 } 12884 } 12885 #endif 12886 12887 #ifdef BCM_TRIUMPH2_SUPPORT 12888 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 12889 SOC_IS_VALKYRIE2(unit)) { 12890 devad = 5; 12891 switch(port) { 12892 case 30: case 31: case 32: case 33: 12893 reg = CMIC_XGXS_MDIO_CONFIG_0r; 12894 break; 12895 case 34: case 35: case 36: case 37: 12896 reg = CMIC_XGXS_MDIO_CONFIG_1r; 12897 break; 12898 case 38: case 39: case 40: case 41: 12899 reg = CMIC_XGXS_MDIO_CONFIG_2r; 12900 break; 12901 case 42: case 43: case 44: case 45: 12902 reg = CMIC_XGXS_MDIO_CONFIG_3r; 12903 break; 12904 case 46: case 47: case 48: case 49: 12905 reg = CMIC_XGXS_MDIO_CONFIG_4r; 12906 break; 12907 case 50: case 51: case 52: case 53: 12908 reg = CMIC_XGXS_MDIO_CONFIG_5r; 12909 break; 12910 case 26: reg = CMIC_XGXS_MDIO_CONFIG_6r; break; 12911 case 27: reg = CMIC_XGXS_MDIO_CONFIG_7r; break; 12912 case 28: reg = CMIC_XGXS_MDIO_CONFIG_8r; break; 12913 case 29: reg = CMIC_XGXS_MDIO_CONFIG_9r; break; 12914 default: return SOC_E_PARAM; 12915 } 12916 } 12917 #endif 12918 #ifdef BCM_TRIDENT_SUPPORT 12919 if (SOC_IS_TD_TT(unit)) { 12920 /* 12921 * MD_DEVADf and IEEE_DEVICES_IN_PKGf are not used 12922 * MD_ST uses reset value (clause 22) 12923 */ 12924 skip = TRUE; 12925 } 12926 #endif /* BCM_TRIDENT_SUPPORT */ 12927 12928 #ifdef BCM_SHADOW_SUPPORT 12929 if (SOC_IS_SHADOW(unit)) { 12930 int blk_idx; 12931 12932 blk_idx = SOC_PORT_BLOCK(unit, port); 12933 switch (blk_idx) { 12934 case 0: reg = CMIC_XGXS_MDIO_CONFIG_0r; break; 12935 case 1: reg = CMIC_XGXS_MDIO_CONFIG_1r; break; 12936 case 2: reg = CMIC_XGXS_MDIO_CONFIG_2r; break; 12937 case 3: reg = CMIC_XGXS_MDIO_CONFIG_3r; break; 12938 case 4: reg = CMIC_XGXS_MDIO_CONFIG_4r; break; 12939 case 5: reg = CMIC_XGXS_MDIO_CONFIG_5r; break; 12940 default: return SOC_E_PARAM; 12941 } 12942 } 12943 #endif /* BCM_SHADOW_SUPPORT */ 12944 12945 #ifdef BCM_ENDURO_SUPPORT 12946 if (SOC_IS_ENDURO(unit)) { 12947 devad = 5; 12948 switch(port) { 12949 case 26: reg = CMIC_XGXS_MDIO_CONFIG_0r; break; 12950 case 27: reg = CMIC_XGXS_MDIO_CONFIG_1r; break; 12951 case 28: reg = CMIC_XGXS_MDIO_CONFIG_2r; break; 12952 case 29: reg = CMIC_XGXS_MDIO_CONFIG_3r; break; 12953 default: return SOC_E_PARAM; 12954 } 12955 } 12956 #endif /* BCM_ENDURO_SUPPORT */ 12957 12958 #ifdef BCM_HURRICANE1_SUPPORT 12959 if (SOC_IS_HURRICANE(unit)) { 12960 devad = 5; 12961 switch(port) { 12962 case 26: reg = CMIC_XGXS_MDIO_CONFIG_0r; break; 12963 case 27: reg = CMIC_XGXS_MDIO_CONFIG_1r; break; 12964 case 28: reg = CMIC_XGXS_MDIO_CONFIG_2r; break; 12965 case 29: reg = CMIC_XGXS_MDIO_CONFIG_3r; break; 12966 default: return SOC_E_PARAM; 12967 } 12968 } 12969 #endif /* BCM_HURRICANE_SUPPORT */ 12970 12971 #ifdef BCM_KATANA_SUPPORT 12972 if (SOC_IS_KATANAX(unit) && !SOC_IS_SABER2(unit)) { 12973 devad = 5; 12974 switch(port) { 12975 case 25: reg = TOP_XGXS_MDIO_CONFIG_0r; break; 12976 case 26: reg = TOP_XGXS_MDIO_CONFIG_1r; break; 12977 case 27: 12978 case 32: 12979 case 33: 12980 case 34: reg = TOP_XGXS_MDIO_CONFIG_2r; break; 12981 case 28: 12982 case 29: 12983 case 30: 12984 case 31: reg = TOP_XGXS_MDIO_CONFIG_3r; break; 12985 default: return SOC_E_PARAM; 12986 } 12987 } 12988 #endif /* BCM_KATANA_SUPPORT */ 12989 12990 #ifdef BCM_TRIUMPH3_SUPPORT 12991 if (SOC_IS_TRIUMPH3(unit)) { 12992 /* 12993 * MD_DEVADf and IEEE_DEVICES_IN_PKGf are not used 12994 * MD_ST uses reset value (clause 22) 12995 */ 12996 skip = TRUE; 12997 } 12998 #endif /* BCM_TRIUMPH3_SUPPORT */ 12999 13000 if (!skip) { 13001 if (reg == INVALIDr) { 13002 return SOC_E_UNAVAIL; 13003 } 13004 #ifdef BCM_CMICM_SUPPORT 13005 if (soc_feature(unit, soc_feature_cmicm)) { 13006 /* In CMICm these regs are accessed via SCHAN */ 13007 SOC_IF_ERROR_RETURN 13008 (soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 13009 soc_reg_field_set(unit, reg, &rval, MD_DEVADf, devad); 13010 soc_reg_field_set(unit, reg, &rval, IEEE_DEVICES_IN_PKGf, 13011 IS_HG_PORT(unit, port) ? 0x03 : 0x15); 13012 SOC_IF_ERROR_RETURN 13013 (soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rval)); 13014 } else 13015 #endif /* CMICm Support */ 13016 { 13017 rval = soc_pci_read 13018 (unit, soc_reg_addr(unit, reg, REG_PORT_ANY, 0)); 13019 soc_reg_field_set(unit, reg, &rval, MD_DEVADf, devad); 13020 soc_reg_field_set(unit, reg, &rval, IEEE_DEVICES_IN_PKGf, 13021 IS_HG_PORT(unit, port) ? 0x03 : 0x15); 13022 soc_pci_write 13023 (unit, soc_reg_addr(unit, reg, REG_PORT_ANY, 0), rval); 13024 } 13025 } 13026 if (SAL_BOOT_QUICKTURN) { 13027 #ifdef BCM_FIREBOLT_SUPPORT 13028 /* Kick the QT phy model */ 13029 if (SOC_IS_FBX(unit)) { 13030 uint16 rv, kv; 13031 int phy_addr; 13032 13033 rv = 0x0800; /* Reset */ 13034 if (IS_HG_PORT(unit,port)) { 13035 kv = 0x0000; /* Configure for HG mode */ 13036 } else { 13037 kv = 0x0002; /* Configure for XE mode */ 13038 } 13039 phy_addr = port + 0x41; 13040 if (SOC_IS_SCORPION(unit)) { 13041 /* Skip over CMIC at port 0, use bus 1 instead of 2 */ 13042 phy_addr -= 0x21; 13043 } 13044 SOC_IF_ERROR_RETURN(soc_miim_write(unit, phy_addr, 0x00, rv)); 13045 SOC_IF_ERROR_RETURN(soc_miim_write(unit, phy_addr, 0x00, kv)); 13046 } else 13047 #endif /* BCM_FIREBOLT_SUPPORT */ 13048 { 13049 SOC_IF_ERROR_RETURN(soc_miim_write(unit, port + 1, 0x00, 0x0000)); 13050 } 13051 } 13052 13053 return SOC_E_NONE; 13054 } 13055 13056 #endif /* BCM_BIGMAC_SUPPORT */ 13057 13058 #if defined(BCM_HELIX15_SUPPORT) || defined(BCM_FELIX15_SUPPORT) || \ 13059 defined(BCM_FIREBOLT2_SUPPORT) 13060 /* 13061 * Get LMD Enable status and update the SOC lmd_pbm. 13062 */ 13063 STATIC int 13064 _xmac_lmd_enable_status_update(int unit) 13065 { 13066 13067 SOC_PBMP_CLEAR(SOC_LMD_PBM(unit)); 13068 13069 if (soc_feature(unit, soc_feature_lmd)) { 13070 uint32 dev_cfg; 13071 uint32 lmd_enable = 0; 13072 13073 if (SOC_IS_FIREBOLT2(unit)) { 13074 #ifndef EXCLUDE_BCM56324 13075 13076 #endif /* EXCLUDE_BCM56324 */ 13077 lmd_enable = soc_property_get(unit, spn_LMD_ENABLE_PBMP, 13078 0); 13079 13080 } else if (!SAL_BOOT_QUICKTURN) { 13081 SOC_IF_ERROR_RETURN(READ_BSAFE_GLB_DEV_STATUSr(unit, &dev_cfg)); 13082 if (soc_reg_field_get(unit, 13083 BSAFE_GLB_DEV_STATUSr, 13084 dev_cfg, 13085 PROD_CFG_VLDf)) { 13086 13087 SOC_IF_ERROR_RETURN 13088 (READ_BSAFE_GLB_PROD_CFGr(unit, &dev_cfg)); 13089 lmd_enable = soc_reg_field_get(unit, 13090 BSAFE_GLB_PROD_CFGr, 13091 dev_cfg, 13092 LMD_ENABLEf); 13093 } 13094 } 13095 13096 lmd_enable <<= SOC_HG_OFFSET(unit); 13097 SOC_PBMP_WORD_SET(SOC_LMD_PBM(unit), 0, lmd_enable); 13098 } 13099 13100 return SOC_E_NONE; 13101 } 13102 #endif /* BCM_HELIX15_SUPPORT || BCM_FELIX15_SUPPORT || 13103 BCM_FIREBOLT2_SUPPORT */ 13104 13105 #ifdef BCM_FIREBOLT_SUPPORT 13106 /* 13107 * Function: 13108 * soc_reset_bcm56504_a0 13109 * Purpose: 13110 * Special reset sequencing for BCM56504 13111 * Setup SBUS block mapping. 13112 */ 13113 13114 STATIC void 13115 soc_reset_bcm56504_a0(int unit) 13116 { 13117 uint32 val, sbus_val, to_usec; 13118 val = 0; 13119 13120 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 13121 (10 * MILLISECOND_USEC); 13122 13123 /* Reset all blocks */ 13124 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13125 13126 13127 /* bring the blocks out of reset */ 13128 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG_PLL_RST_Lf, 1); 13129 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 13130 CMIC_BSAFE_CLKGEN_RST_Lf,1); 13131 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13132 sal_usleep(50); 13133 soc_xgxs_lcpll_reset(unit); 13134 sal_usleep(to_usec); 13135 13136 #if defined(BCM_HELIX_SUPPORT) || defined(BCM_FELIX_SUPPORT) 13137 /* Felix/Helix only */ 13138 if (SOC_IS_FX_HX(unit)) { 13139 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GXP_RST_Lf, 1); 13140 } 13141 #endif /* BCM_FELIX_SUPPORT || BCM_HELIX_SUPPORT */ 13142 if (soc_reg_field_valid(unit, CMIC_SOFT_RESET_REGr, CMIC_BSAFE_RST_Lf)) { 13143 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_BSAFE_RST_Lf, 1); 13144 } 13145 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 13146 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 13147 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 1); 13148 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XP_RST_Lf, 1); 13149 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP_RST_Lf, 1); 13150 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13151 sal_usleep(to_usec); 13152 13153 /* 13154 * Firebolt/Helix/Felix 13155 * ring0 [00] : IPIPE[7] -> IPIPE_HI[8] 13156 * ring1 [01] : EPIPE[9] -> EPIPE_HI[10] 13157 * ring2 [10] : gport0[0] -> gport1[1] -> xport0[2] -> 13158 * xport1[3] -> xport2[4] -> xport3[5] -> MMU[6] 13159 * gport[12] -> gport[13] (Felix) 13160 * ring3 [11] : bsafe[11] 13161 * 13162 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 13163 * 0000__1010__1101__0100__0010__1010__1010__1010 13164 */ 13165 13166 sbus_val = 0x0ad42aaa; 13167 WRITE_CMIC_SBUS_RING_MAPr(unit, sbus_val); 13168 /* 13169 * Min 20 msec delay after LCPLL reset before checking for lock. 13170 * Lock checking required only if HG/XE ports present. 13171 */ 13172 if (SOC_PBMP_NOT_NULL(PBMP_XE_ALL(unit)) || 13173 SOC_PBMP_NOT_NULL(PBMP_HG_ALL(unit))) { 13174 soc_xgxs_lcpll_lock_check(unit); 13175 } 13176 13177 #if defined(BCM_HELIX_SUPPORT) || defined(BCM_FELIX_SUPPORT) 13178 /* 13179 * Verify Serdes base address is valid before removing Gigabit reset 13180 */ 13181 if (!SAL_BOOT_QUICKTURN && SOC_IS_FX_HX(unit)) { 13182 soc_timeout_t to; 13183 uint32 dev_cfg = 0; 13184 int rv = SOC_E_NONE; 13185 13186 soc_timeout_init(&to, 1000000, 1); /* One second timeout */ 13187 13188 for (;;) { 13189 if ((rv = READ_BSAFE_GLB_DEV_STATUSr(unit, &dev_cfg)) < 0) { 13190 break; 13191 } 13192 if (soc_reg_field_get(unit, 13193 BSAFE_GLB_DEV_STATUSr, 13194 dev_cfg, 13195 PROD_CFG_VLDf) == 1) { 13196 rv = SOC_E_NONE; 13197 break; 13198 } 13199 if (soc_reg_field_get(unit, 13200 BSAFE_GLB_DEV_STATUSr, 13201 dev_cfg, 13202 INIT_DONEf) == 1) { 13203 if ((soc_reg_field_get(unit, 13204 BSAFE_GLB_DEV_STATUSr, 13205 dev_cfg, INIT_KEYf) == 0) && 13206 (soc_reg_field_get(unit, 13207 BSAFE_GLB_DEV_STATUSr, 13208 dev_cfg, BUSYf) == 0)) { 13209 rv = SOC_E_NONE; 13210 break; 13211 } 13212 13213 } 13214 if (soc_timeout_check(&to)) { 13215 rv = SOC_E_TIMEOUT; 13216 break; 13217 } 13218 sal_usleep(to_usec); 13219 } 13220 if (rv < 0) { 13221 LOG_ERROR(BSL_LS_SOC_COMMON, 13222 (BSL_META_U(unit, 13223 "soc_reset_bcm56504_a0: Device status valid check failed on unit %d\n"), 13224 unit)); 13225 } 13226 } 13227 #endif /* BCM_HELIX_SUPPORT || BCM_FELIX_SUPPORT */ 13228 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX4_RST_Lf, 1); 13229 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13230 13231 #if defined(BCM_HELIX15_SUPPORT) || defined(BCM_FELIX15_SUPPORT) || \ 13232 defined(BCM_FIREBOLT2_SUPPORT) 13233 /* 13234 * Extract the XPORT LMD operation mode. 13235 */ 13236 if (_xmac_lmd_enable_status_update(unit) < 0) { 13237 LOG_ERROR(BSL_LS_SOC_COMMON, 13238 (BSL_META_U(unit, 13239 "soc_reset_bcm56504_a0: LMD status update failed on unit %d\n"), 13240 unit)); 13241 } 13242 #endif /* BCM_HELIX15_SUPPORT || BCM_FELIX15_SUPPORT || 13243 BCM_FIREBOLT2_SUPPORT */ 13244 } 13245 #endif /* BCM_FIREBOLT_SUPPORT */ 13246 13247 #ifdef BCM_RAPTOR1_SUPPORT 13248 /* 13249 * Function: 13250 * soc_reset_bcm56218_a0 13251 * Purpose: 13252 * Special reset sequencing for BCM56218 13253 * Setup SBUS block mapping. 13254 */ 13255 13256 STATIC void 13257 soc_reset_bcm56218_a0(int unit) 13258 { 13259 uint32 val, to_usec; 13260 val = 0; 13261 13262 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 13263 (10 * MILLISECOND_USEC); 13264 13265 /* Reset all blocks */ 13266 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13267 13268 13269 /* bring the blocks out of reset */ 13270 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG_PLL_RST_Lf, 1); 13271 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_G2P51_RST_Lf, 1); 13272 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_G2P50_RST_Lf, 1); 13273 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX12_RST_Lf, 1); 13274 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX2_RST_Lf, 1); 13275 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13276 sal_usleep(50); 13277 soc_xgxs_lcpll_reset(unit); 13278 sal_usleep(to_usec); 13279 13280 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_FP_RST_Lf, 1); 13281 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP_RST_Lf, 1); 13282 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 13283 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 13284 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 1); 13285 13286 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13287 sal_usleep(to_usec); 13288 13289 /* 13290 * Raptor 13291 * ring0 [00] : IPIPE[7] -> IPIPE_HI[8] 13292 * ring1 [01] : EPIPE[9] -> EPIPE_HI[10] 13293 * ring2 [10] : gport4[1] -> gport0[2] -> 13294 * gport1[3] -> gport2[4] -> gport3[5] -> MMU[6] 13295 * ring3 [11] : bsafe[11] 13296 * 13297 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 13298 * 0000__XXXX__1101__0100__0010__1010__1010__10XX 13299 */ 13300 13301 val = 0x0ad42aaa; 13302 WRITE_CMIC_SBUS_RING_MAPr(unit, val); 13303 /* 13304 * Min 20 msec delay after LCPLL reset before checking for lock. 13305 */ 13306 soc_xgxs_lcpll_lock_check(unit); 13307 } 13308 #endif /* BCM_RAPTOR_SUPPORT */ 13309 13310 #if defined(BCM_RAVEN_SUPPORT) 13311 STATIC void 13312 soc_mdio_setup(int unit) 13313 { 13314 uint32 val; 13315 13316 READ_CMIC_GFPORT_CLOCK_CONFIGr(unit, &val); 13317 soc_reg_field_set(unit, CMIC_GFPORT_CLOCK_CONFIGr, &val, 13318 SEL_DOZEN_SERDES_0_REF_CLK_SRCf, 3); 13319 soc_reg_field_set(unit, CMIC_GFPORT_CLOCK_CONFIGr, &val, 13320 SEL_DOZEN_SERDES_1_REF_CLK_SRCf, 3); 13321 soc_reg_field_set(unit, CMIC_GFPORT_CLOCK_CONFIGr, &val, 13322 PROG_DOZEN_SERDES_PLLDIV_CTRL_DEFf, 3); 13323 WRITE_CMIC_GFPORT_CLOCK_CONFIGr(unit, val); 13324 13325 READ_CMIC_GFPORT_CLOCK_CONFIGr(unit, &val); 13326 soc_reg_field_set(unit, CMIC_GFPORT_CLOCK_CONFIGr, &val, 13327 SEL_DOZEN_SERDES_0_REF_CLK_SRCf, 1); 13328 soc_reg_field_set(unit, CMIC_GFPORT_CLOCK_CONFIGr, &val, 13329 SEL_DOZEN_SERDES_1_REF_CLK_SRCf, 1); 13330 soc_reg_field_set(unit, CMIC_GFPORT_CLOCK_CONFIGr, &val, 13331 PROG_DOZEN_SERDES_PLLDIV_CTRL_DEFf, 0); 13332 WRITE_CMIC_GFPORT_CLOCK_CONFIGr(unit, val); 13333 13334 return; 13335 } 13336 13337 /* 13338 * Function: 13339 * soc_reset_bcm56224_a0 13340 * Purpose: 13341 * Special reset sequencing for BCM56224 13342 * Setup SBUS block mapping. 13343 */ 13344 13345 STATIC void 13346 soc_reset_bcm56224_a0(int unit) 13347 { 13348 uint32 val, to_usec; 13349 val = 0; 13350 13351 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 13352 (10 * MILLISECOND_USEC); 13353 13354 /* Reset all blocks */ 13355 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13356 13357 13358 /* bring the blocks out of reset */ 13359 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG_PLL_RST_Lf, 1); 13360 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_G2P51_RST_Lf, 1); 13361 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_G2P50_RST_Lf, 1); 13362 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_G2P52_RST_Lf, 1); 13363 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_G2P53_RST_Lf, 1); 13364 if (soc_feature(unit, soc_feature_mdio_setup)) { 13365 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX12_RST_Lf, 0); 13366 } else { 13367 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX12_RST_Lf, 1); 13368 } 13369 /*soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX2_RST_Lf, 1);*/ 13370 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13371 sal_usleep(50); 13372 soc_xgxs_lcpll_reset(unit); 13373 sal_usleep(to_usec); 13374 13375 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_FP_RST_Lf, 1); 13376 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP_RST_Lf, 1); 13377 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 13378 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 13379 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 1); 13380 13381 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13382 sal_usleep(to_usec); 13383 /* 13384 * Raptor 13385 * ring0 [00] : IPIPE[7] -> IPIPE_HI[8] 13386 * ring1 [01] : EPIPE[9] -> EPIPE_HI[10] 13387 * ring2 [10] : gport4[1] -> gport0[2] -> 13388 * gport1[3] -> gport2[4] -> gport3[5] -> MMU[6] 13389 * ring3 [11] : bsafe[11] 13390 * 13391 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 13392 * 0000__XXXX__1101__0100__0010__1010__1010__10XX 13393 */ 13394 13395 val = 0x0ad42aaa; 13396 WRITE_CMIC_SBUS_RING_MAPr(unit, val); 13397 /* 13398 * Min 20 msec delay after LCPLL reset before checking for lock. 13399 */ 13400 soc_xgxs_lcpll_lock_check(unit); 13401 if (soc_feature(unit, soc_feature_mdio_setup)) { 13402 soc_mdio_setup(unit); 13403 } 13404 } 13405 #endif /* BCM_RAVEN_SUPPORT */ 13406 13407 #if defined(BCM_HAWKEYE_SUPPORT) 13408 /* 13409 * Function: 13410 * soc_reset_bcm53314_a0 13411 * Purpose: 13412 * Special reset sequencing for BCM53314 13413 * Setup SBUS block mapping. 13414 */ 13415 13416 STATIC void 13417 soc_reset_bcm53314_a0(int unit) 13418 { 13419 uint32 val, rval, to_usec; 13420 int i, retry = 3, locked = 0; 13421 13422 to_usec = SAL_BOOT_QUICKTURN ? (500 * MILLISECOND_USEC) : 13423 (25 * MILLISECOND_USEC); 13424 13425 /* Reset all blocks */ 13426 val = 0; 13427 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13428 13429 13430 /* Bring LCPLL out of reset */ 13431 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG_PLL_RST_Lf, 1); 13432 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13433 sal_usleep(to_usec); 13434 /* Check lock status */ 13435 if ((!SAL_BOOT_PLISIM) && (!SAL_BOOT_QUICKTURN)) { 13436 for (i = 0; i < retry ; i++) { 13437 READ_CMIC_XGXS_PLL_STATUSr(unit, &rval); 13438 locked = soc_reg_field_get(unit, CMIC_XGXS_PLL_STATUSr, 13439 rval, CMIC_XG_PLL_LOCKf); 13440 if (locked) 13441 break; 13442 sal_usleep(to_usec); 13443 } 13444 if (!locked) { 13445 LOG_ERROR(BSL_LS_SOC_COMMON, 13446 (BSL_META_U(unit, 13447 "LCPLL not locked on unit %d " 13448 "status = 0x%08x\n"), 13449 unit, rval)); 13450 } 13451 } 13452 13453 /* Bring qsgmii/qgphy out of reset */ 13454 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_QSGMII2X0_RST_Lf, 1); 13455 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_QSGMII2X1_RST_Lf, 1); 13456 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_QGPHY0_RST_Lf, 1); 13457 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_QGPHY1_RST_Lf, 1); 13458 13459 /* Wait for qsgmii/qgphy PLL lock */ 13460 sal_usleep(to_usec); 13461 13462 /* Bring gport/ip/ep/mmu out of reset */ 13463 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 13464 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 13465 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 1); 13466 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13467 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP_RST_Lf, 1); 13468 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13469 13470 sal_usleep(to_usec); 13471 /* 13472 * Raptor 13473 * ring0 [00] : IPIPE[7] -> IPIPE_HI[8] 13474 * ring1 [01] : EPIPE[9] -> EPIPE_HI[10] 13475 * ring2 [10] : gport4[1] -> gport0[2] -> 13476 * gport1[3] -> gport2[4] -> gport3[5] -> MMU[6] 13477 * ring3 [11] : bsafe[11] 13478 * 13479 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 13480 * 0000__XXXX__1101__0100__0010__1010__1010__10XX 13481 */ 13482 13483 val = 0x0ad42aaa; 13484 WRITE_CMIC_SBUS_RING_MAPr(unit, val); 13485 13486 /* set UNMANAGED_MODE of CMIC_CHIP_MODE_CONTROL to 0 in the init sequence */ 13487 val = 0x0; 13488 WRITE_CMIC_CHIP_MODE_CONTROLr(unit, val); 13489 13490 /* set CMIC_INTR_WAIT_CYCLES to 0 in the init sequence */ 13491 val = 0x0; 13492 WRITE_CMIC_INTR_WAIT_CYCLESr(unit, val); 13493 13494 READ_CMIC_QGPHY_QSGMII_CONTROLr(unit, &val); 13495 soc_reg_field_set(unit, CMIC_QGPHY_QSGMII_CONTROLr, &val, SEL_LEDRAM_SERIAL_DATAf, 1); 13496 WRITE_CMIC_QGPHY_QSGMII_CONTROLr(unit, val); 13497 } 13498 #endif /* BCM_HAWKEYE_SUPPORT */ 13499 13500 #if defined (BCM_BRADLEY_SUPPORT) 13501 /* 13502 * Function: 13503 * soc_reset_bcm56800_a0 13504 * Purpose: 13505 * Special reset sequencing for BCM56800 13506 * Setup SBUS block mapping. 13507 */ 13508 13509 STATIC void 13510 soc_reset_bcm56800_a0(int unit) 13511 { 13512 uint32 val, to_usec; 13513 13514 13515 val = 0; 13516 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 13517 (20 * MILLISECOND_USEC); 13518 13519 /* Reset all blocks */ 13520 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13521 13522 /* Bring LCPLL blocks out of reset */ 13523 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 13524 CMIC_XG_PLL0_RST_Lf, 1); 13525 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 13526 CMIC_XG_PLL1_RST_Lf, 1); 13527 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 13528 CMIC_BSAFE_CLKGEN_RST_Lf,1); 13529 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13530 sal_usleep(to_usec); 13531 13532 /* 13533 * Min 20 msec delay after LCPLL reset before checking for lock. 13534 */ 13535 if ((!SAL_BOOT_PLISIM) && (!SAL_BOOT_QUICKTURN)) { 13536 _bradley_lcpll_lock_check(unit); 13537 } 13538 13539 /* Bring GX4 block out of reset after 1 msec after PLLs */ 13540 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX4_RST_Lf, 1); 13541 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13542 sal_usleep(to_usec); 13543 13544 /* 13545 * NOTE 13546 * The remaining blocks will be brought out of 13547 * reset after Unicore reset. 13548 */ 13549 13550 /* 13551 * ring0 [00] : ipipe[1] -> ipipe_x[2] -> ipipe_y[3] -> 13552 * epipe[4] -> epipe_x[5] -> epipe_y[6] 13553 * ring1 [01] : mmu[13] 13554 * ring2 [10] : bsafe[14] 13555 * ring3 [11] : gxport[0] 13556 * 13557 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 13558 * 0010__0100__0000__0000__0000__0000__0000__0011 13559 */ 13560 13561 val = 0x24000003; 13562 WRITE_CMIC_SBUS_RING_MAPr(unit, val); 13563 } 13564 #endif /* BCM_BRADLEY_SUPPORT */ 13565 13566 #ifdef BCM_TRIUMPH_SUPPORT 13567 /* 13568 * Function: 13569 * soc_reset_bcm56624_a0 13570 * Purpose: 13571 * Special reset sequencing for BCM56624 13572 * Setup SBUS block mapping. 13573 */ 13574 13575 STATIC void 13576 soc_reset_bcm56624_a0(int unit) 13577 { 13578 soc_control_t *soc = SOC_CONTROL(unit); 13579 soc_tcam_info_t *tcam_info; 13580 uint32 val, to_usec; 13581 13582 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 13583 (10 * MILLISECOND_USEC); 13584 13585 13586 /* bring the blocks out of reset */ 13587 READ_CMIC_SOFT_RESET_REGr(unit, &val); 13588 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG_PLL0_RST_Lf, 13589 1); 13590 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG_PLL1_RST_Lf, 13591 1); 13592 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13593 sal_usleep(to_usec); 13594 13595 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX8_0_RST_Lf, 1); 13596 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX8_1_RST_Lf, 1); 13597 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX8_2_RST_Lf, 1); 13598 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX9_RST_Lf, 1); 13599 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13600 sal_usleep(to_usec); 13601 13602 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XGP0_RST_Lf, 1); 13603 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XGP1_RST_Lf, 1); 13604 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XGP2_RST_Lf, 1); 13605 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XGP3_RST_Lf, 1); 13606 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XP0_RST_Lf, 1); 13607 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XP1_RST_Lf, 1); 13608 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XP2_RST_Lf, 1); 13609 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XP3_RST_Lf, 1); 13610 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_SP_RST_Lf, 1); 13611 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13612 sal_usleep(to_usec); 13613 13614 if (!soc_feature(unit, soc_feature_ignore_cmic_xgxs_pll_status) && 13615 !SAL_BOOT_PLISIM && !SAL_BOOT_QUICKTURN) { 13616 /* LCPLL 0 is for Hyperlite and serdes x8/x9 */ 13617 READ_CMIC_XGXS0_PLL_STATUSr(unit, &val); 13618 if (!soc_reg_field_get(unit, CMIC_XGXS0_PLL_STATUSr, val, 13619 CMIC_XGPLL_LOCKf)) { 13620 LOG_ERROR(BSL_LS_SOC_COMMON, 13621 (BSL_META_U(unit, 13622 "LCPLL 0 not locked on unit %d " 13623 "status = 0x%08x\n"), unit, val)); 13624 } 13625 13626 /* LCPLL 1 is for Unicore */ 13627 READ_CMIC_XGXS1_PLL_STATUSr(unit, &val); 13628 if (!soc_reg_field_get(unit, CMIC_XGXS1_PLL_STATUSr, val, 13629 CMIC_XGPLL_LOCKf)) { 13630 LOG_ERROR(BSL_LS_SOC_COMMON, 13631 (BSL_META_U(unit, 13632 "LCPLL 1 not locked on unit %d " 13633 "status = 0x%08x\n"), unit, val)); 13634 } 13635 } 13636 13637 if (soc_feature(unit, soc_feature_esm_support)) { 13638 soc_triumph_esm_init_read_config(unit); 13639 tcam_info = soc->tcam_info; 13640 13641 /* Assert reset pin of external TCAM, esm_init will de-assert it */ 13642 READ_CMIC_SOFT_RESET_REGr(unit, &val); 13643 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, EXT_TCAM_RSTf, 1); 13644 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13645 13646 /* Program PLL for DDR */ 13647 READ_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1r(unit, &val); 13648 soc_reg_field_set(unit, CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1r, &val, 13649 EN_CMLBUF1f, 1); 13650 WRITE_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1r(unit, val); 13651 13652 READ_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, &val); 13653 soc_reg_field_set(unit, CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r, &val, 13654 BYPASS_SDMODf, 1); 13655 WRITE_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, val); 13656 13657 if (tcam_info != NULL) { 13658 soc_triumph_esm_init_set_sram_freq(unit, tcam_info->sram_freq); 13659 } 13660 13661 /* Program PLL for TCAM */ 13662 READ_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_1r(unit, &val); 13663 soc_reg_field_set(unit, CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_1r, &val, 13664 EN_CMLBUF1f, 1); 13665 WRITE_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_1r(unit, val); 13666 13667 READ_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, &val); 13668 soc_reg_field_set(unit, CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r, &val, 13669 BYPASS_SDMODf, 1); 13670 WRITE_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, val); 13671 13672 if (tcam_info != NULL) { 13673 soc_triumph_esm_init_set_tcam_freq(unit, tcam_info->tcam_freq); 13674 } 13675 } 13676 13677 /* 13678 * Triumph 13679 * ring0 [00] : IPIPE[10] -> EPIPE[11] 13680 * ring1 [01] : MMU[12] 13681 * ring2 [10] : OTPC[13] -> ESM[14] 13682 * ring3 [11] : XGPORT0[2] -> XGPORT1[3] -> XGPORT2[4] -> XGPORT3[5] -> 13683 * GXPORT0[6] -> GXPORT1[7] -> GXPORT2[8] -> GXPORT3[9] -> 13684 * SPORT[1] 13685 * 13686 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 13687 * 0010__1001__0000__1111__1111__1111__1111__11XX 13688 */ 13689 13690 val = 0x290ffffe; 13691 WRITE_CMIC_SBUS_RING_MAPr(unit, val); 13692 13693 val = 0x7d0; 13694 WRITE_CMIC_SBUS_TIMEOUTr(unit, val); 13695 13696 /* Bring IP, EP, and MMU blocks out of reset */ 13697 READ_CMIC_SOFT_RESET_REGr(unit, &val); 13698 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 13699 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 13700 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 1); 13701 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13702 sal_usleep(to_usec); 13703 13704 if (soc_feature(unit, soc_feature_esm_support)) { 13705 /* Bring PVT out of reset */ 13706 READ_CMIC_SOFT_RESET_REGr(unit, &val); 13707 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_PVT_RST_Lf, 13708 1); 13709 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13710 13711 /* Bring DDR PLL out of reset */ 13712 READ_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, &val); 13713 soc_reg_field_set(unit, CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r, &val, 13714 ARESETf, 0); 13715 WRITE_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, val); 13716 sal_usleep(to_usec); 13717 soc_reg_field_set(unit, CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r, &val, 13718 DRESETf, 0); 13719 WRITE_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, val); 13720 sal_usleep(to_usec); 13721 if (soc->tcam_info != NULL && 13722 (!SAL_BOOT_QUICKTURN && !SAL_BOOT_PLISIM && !SAL_BOOT_BCMSIM)) { 13723 /* Get DDR PLL lock status (bit 1) */ 13724 READ_CMIC_MISC_STATUSr(unit, &val); 13725 if (!(val & 0x2)) { 13726 LOG_WARN(BSL_LS_SOC_COMMON, 13727 (BSL_META_U(unit, 13728 "DDR PLL not locked.\n"))); 13729 } 13730 } 13731 13732 /* Bring TCAM PLL out of reset */ 13733 READ_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, &val); 13734 soc_reg_field_set(unit, CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r, &val, 13735 ARESETf, 0); 13736 WRITE_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, val); 13737 sal_usleep(to_usec); 13738 soc_reg_field_set(unit, CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r, &val, 13739 DRESETf, 0); 13740 WRITE_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, val); 13741 sal_usleep(to_usec); 13742 if (soc->tcam_info != NULL && 13743 (!SAL_BOOT_QUICKTURN && !SAL_BOOT_PLISIM && !SAL_BOOT_BCMSIM)) { 13744 /* Get TCAM PLL lock status (bit 2) */ 13745 READ_CMIC_MISC_STATUSr(unit, &val); 13746 if (!(val & 0x4)) { 13747 LOG_WARN(BSL_LS_SOC_COMMON, 13748 (BSL_META_U(unit, 13749 "TCAM PLL not locked.\n"))); 13750 } 13751 } 13752 13753 /* Bring ESM block out of reset */ 13754 READ_CMIC_SOFT_RESET_REGr(unit, &val); 13755 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_ESM_RST_Lf, 13756 1); 13757 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13758 sal_usleep(to_usec); 13759 } 13760 } 13761 #endif /* BCM_TRIUMPH_SUPPORT */ 13762 13763 #ifdef BCM_TRIUMPH2_SUPPORT 13764 /* 13765 * Function: 13766 * soc_reset_bcm56634_a0 13767 * Purpose: 13768 * Special reset sequencing for BCM56634 13769 * Setup SBUS block mapping. 13770 */ 13771 13772 STATIC void 13773 soc_reset_bcm56634_a0(int unit) 13774 { 13775 soc_control_t *soc = SOC_CONTROL(unit); 13776 soc_tcam_info_t *tcam_info; 13777 uint32 val, to_usec, val2 = 0; 13778 13779 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 13780 (10 * MILLISECOND_USEC); 13781 13782 13783 /* bring the blocks out of reset */ 13784 READ_CMIC_SOFT_RESET_REGr(unit, &val); 13785 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG_PLL0_RST_Lf, 13786 1); 13787 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG_PLL1_RST_Lf, 13788 1); 13789 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13790 sal_usleep(to_usec); 13791 13792 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX8_0_RST_Lf, 1); 13793 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX8_1_RST_Lf, 1); 13794 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX8_2_RST_Lf, 1); 13795 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GX9_RST_Lf, 1); 13796 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13797 sal_usleep(to_usec); 13798 13799 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ0_RST_Lf, 1); 13800 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ1_RST_Lf, 1); 13801 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ2_RST_Lf, 1); 13802 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ3_RST_Lf, 1); 13803 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ4_RST_Lf, 1); 13804 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ5_RST_Lf, 1); 13805 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XP0_RST_Lf, 1); 13806 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XP1_RST_Lf, 1); 13807 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XP2_RST_Lf, 1); 13808 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XP3_RST_Lf, 1); 13809 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP0_RST_Lf, 1); 13810 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP1_RST_Lf, 1); 13811 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_SP_RST_Lf, 1); 13812 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13813 sal_usleep(to_usec); 13814 13815 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &val2, 13816 XQ0_HOTSWAP_RST_Lf, 1); 13817 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &val2, 13818 XQ1_HOTSWAP_RST_Lf, 1); 13819 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &val2, 13820 XQ2_HOTSWAP_RST_Lf, 1); 13821 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &val2, 13822 XQ3_HOTSWAP_RST_Lf, 1); 13823 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &val2, 13824 XQ4_HOTSWAP_RST_Lf, 1); 13825 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &val2, 13826 XQ5_HOTSWAP_RST_Lf, 1); 13827 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &val2, NS_RST_Lf, 1); 13828 WRITE_CMIC_SOFT_RESET_REG_2r(unit, val2); 13829 sal_usleep(to_usec); 13830 13831 if (soc_feature(unit, soc_feature_esm_support) || SOC_IS_TRIUMPH2(unit)) { 13832 soc_triumph_esm_init_read_config(unit); 13833 } 13834 tcam_info = soc->tcam_info; 13835 13836 if (tcam_info != NULL) { 13837 /* Assert reset pin of external TCAM, esm_init will de-assert it */ 13838 READ_CMIC_SOFT_RESET_REGr(unit, &val); 13839 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, EXT_TCAM_RSTf, 1); 13840 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13841 13842 /* Program PLL for DDR */ 13843 READ_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1r(unit, &val); 13844 soc_reg_field_set(unit, CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1r, &val, 13845 EN_CMLBUF1f, 1); 13846 WRITE_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1r(unit, val); 13847 13848 READ_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, &val); 13849 soc_reg_field_set(unit, CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r, &val, 13850 BYPASS_SDMODf, 1); 13851 WRITE_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, val); 13852 13853 soc_triumph_esm_init_set_sram_freq(unit, tcam_info->sram_freq); 13854 13855 /* Program PLL for TCAM */ 13856 READ_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_1r(unit, &val); 13857 soc_reg_field_set(unit, CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_1r, &val, 13858 EN_CMLBUF1f, 1); 13859 WRITE_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_1r(unit, val); 13860 13861 READ_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, &val); 13862 soc_reg_field_set(unit, CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r, &val, 13863 BYPASS_SDMODf, 1); 13864 WRITE_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, val); 13865 13866 soc_triumph_esm_init_set_tcam_freq(unit, tcam_info->tcam_freq); 13867 } 13868 13869 13870 /* 13871 * Triumph2 13872 * 13873 * map_0 includes blocks 0-7 13874 * map_1 includes blocks 8-15 13875 * map_2 includes blocks 16-23 13876 * map_3 includes blocks 24-31 13877 */ 13878 13879 val = 0x33022140; 13880 WRITE_CMIC_SBUS_RING_MAP_0r(unit, val); 13881 13882 val = 0x00033333; 13883 WRITE_CMIC_SBUS_RING_MAP_1r(unit, val); 13884 13885 val = 0x00333333; 13886 WRITE_CMIC_SBUS_RING_MAP_2r(unit, val); 13887 13888 val = 0x0; 13889 WRITE_CMIC_SBUS_RING_MAP_3r(unit, val); 13890 13891 val = 0x2000; 13892 WRITE_CMIC_SBUS_TIMEOUTr(unit, val); 13893 13894 /* Bring IP, EP, and MMU blocks out of reset */ 13895 READ_CMIC_SOFT_RESET_REGr(unit, &val); 13896 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 13897 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 13898 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 1); 13899 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13900 sal_usleep(to_usec); 13901 13902 if (soc_feature(unit, soc_feature_esm_support)) { 13903 /* Bring PVT out of reset */ 13904 READ_CMIC_SOFT_RESET_REGr(unit, &val); 13905 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_PVT_RST_Lf, 13906 1); 13907 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13908 13909 /* Bring DDR PLL out of reset */ 13910 READ_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, &val); 13911 soc_reg_field_set(unit, CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r, &val, 13912 ARESETf, 0); 13913 WRITE_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, val); 13914 sal_usleep(to_usec); 13915 soc_reg_field_set(unit, CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r, &val, 13916 DRESETf, 0); 13917 WRITE_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, val); 13918 sal_usleep(to_usec); 13919 if (soc->tcam_info != NULL && 13920 (!SAL_BOOT_QUICKTURN && !SAL_BOOT_PLISIM && !SAL_BOOT_BCMSIM)) { 13921 /* Get DDR PLL lock status (bit 1) */ 13922 READ_CMIC_MISC_STATUSr(unit, &val); 13923 if (!(val & 0x2)) { 13924 LOG_WARN(BSL_LS_SOC_COMMON, 13925 (BSL_META_U(unit, 13926 "DDR PLL not locked.\n"))); 13927 } 13928 } 13929 13930 /* Bring TCAM PLL out of reset */ 13931 READ_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, &val); 13932 soc_reg_field_set(unit, CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r, &val, 13933 ARESETf, 0); 13934 WRITE_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, val); 13935 sal_usleep(to_usec); 13936 soc_reg_field_set(unit, CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r, &val, 13937 DRESETf, 0); 13938 WRITE_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, val); 13939 sal_usleep(to_usec); 13940 if (soc->tcam_info != NULL && 13941 (!SAL_BOOT_QUICKTURN && !SAL_BOOT_PLISIM && !SAL_BOOT_BCMSIM)) { 13942 /* Get TCAM PLL lock status (bit 2) */ 13943 READ_CMIC_MISC_STATUSr(unit, &val); 13944 if (!(val & 0x4)) { 13945 LOG_WARN(BSL_LS_SOC_COMMON, 13946 (BSL_META_U(unit, 13947 "TCAM PLL not locked.\n"))); 13948 } 13949 } 13950 13951 /* Bring ESM block out of reset */ 13952 READ_CMIC_SOFT_RESET_REGr(unit, &val); 13953 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_ESM_RST_Lf, 13954 1); 13955 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 13956 sal_usleep(to_usec); 13957 } 13958 13959 if (soc_feature(unit, soc_feature_gmii_clkout)) { 13960 val2 = 0; 13961 /* select GMII 25MHz clock output */ 13962 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &val2, 13963 CLK_RECOVERY_PRI_SELECTf, 1); 13964 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &val2, 13965 CLK_RECOVERY_BKUP_SELECTf, 1); 13966 WRITE_CMIC_MISC_CONTROLr(unit, val2); 13967 13968 /* Select primary and secondary ports */ 13969 val2 = 0; 13970 soc_reg_field_set(unit, EGR_L1_CLK_RECOVERY_CTRLr, &val2, 13971 PRI_PORT_SELf, soc_property_get(unit, 13972 "L1_primary_clk_recovery_port", 0x0)); 13973 soc_reg_field_set(unit, EGR_L1_CLK_RECOVERY_CTRLr, &val2, 13974 BKUP_PORT_SELf, soc_property_get(unit, 13975 "L1_backup_clk_recovery_port", 0x0)); 13976 if (WRITE_EGR_L1_CLK_RECOVERY_CTRLr(unit, val2) != SOC_E_NONE) { 13977 LOG_CLI((BSL_META_U(unit, 13978 "Selecting L1 clock recovery ports failed !!\n"))); 13979 } 13980 } 13981 } 13982 #endif /* BCM_TRIUMPH2_SUPPORT */ 13983 13984 #ifdef BCM_ENDURO_SUPPORT 13985 /* 13986 * Function: 13987 * soc_reset_bcm56334_a0 13988 * Purpose: 13989 * Special reset sequencing for BCM56334 13990 * Setup SBUS block mapping. 13991 */ 13992 13993 STATIC void 13994 soc_reset_bcm56334_a0(int unit) 13995 { 13996 uint32 val, to_usec; 13997 uint16 dev_id; 13998 uint8 rev_id; 13999 14000 soc_cm_get_id(unit, &dev_id, &rev_id); 14001 14002 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 14003 (10 * MILLISECOND_USEC); 14004 14005 14006 if (soc_feature(unit, soc_feature_delay_core_pll_lock)) { 14007 /* put Configuring core-clk to 100MHz */ 14008 READ_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1r(unit, &val); 14009 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1r, &val, 14010 TEST_SELf, 5); 14011 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1r, &val, 14012 TEST_ENABLEf, 1); 14013 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1r(unit, val); 14014 READ_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2r(unit, &val); 14015 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2r, &val, 14016 M1DIVf, 10); 14017 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2r(unit, val); 14018 READ_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, &val); 14019 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 14020 NDIV_INTf, 40); 14021 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 14022 sal_usleep(to_usec); 14023 } 14024 14025 /* bring the blocks out of reset */ 14026 READ_CMIC_SOFT_RESET_REGr(unit, &val); 14027 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG1_PLL_RST_Lf, 14028 1); 14029 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG0_PLL_RST_Lf, 14030 1); 14031 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14032 sal_usleep(to_usec); 14033 14034 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14035 CMIC_GX8_SERDES_0_RST_Lf, 1); 14036 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14037 CMIC_GX8_SERDES_1_RST_Lf, 1); 14038 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14039 CMIC_GX8_SERDES_2_RST_Lf, 1); 14040 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14041 sal_usleep(to_usec); 14042 14043 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP0_RST_Lf, 1); 14044 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP1_RST_Lf, 1); 14045 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP2_RST_Lf, 1); 14046 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XQP0_RST_Lf, 1); 14047 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XQP1_RST_Lf, 1); 14048 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XQP2_RST_Lf, 1); 14049 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XQP3_RST_Lf, 1); 14050 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14051 sal_usleep(to_usec); 14052 14053 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ0_HOTSWAP_RST_Lf, 1); 14054 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ1_HOTSWAP_RST_Lf, 1); 14055 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ2_HOTSWAP_RST_Lf, 1); 14056 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ3_HOTSWAP_RST_Lf, 1); 14057 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, NS_RST_Lf, 1); 14058 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_OTPC_RST_Lf, 1); 14059 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, THERMAL_MON_RESETf, 1); 14060 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14061 sal_usleep(to_usec); 14062 14063 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, THERMAL_MON_RESETf, 0); 14064 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14065 sal_usleep(to_usec); 14066 14067 val = 0x11122200; 14068 WRITE_CMIC_SBUS_RING_MAP_0r(unit, val); 14069 val = 0x00330001; 14070 WRITE_CMIC_SBUS_RING_MAP_1r(unit, val); 14071 val = 0x0; 14072 WRITE_CMIC_SBUS_RING_MAP_2r(unit, val); 14073 WRITE_CMIC_SBUS_RING_MAP_3r(unit, val); 14074 WRITE_CMIC_SBUS_RING_MAP_4r(unit, val); 14075 WRITE_CMIC_SBUS_RING_MAP_5r(unit, val); 14076 WRITE_CMIC_SBUS_RING_MAP_6r(unit, val); 14077 WRITE_CMIC_SBUS_RING_MAP_7r(unit, val); 14078 14079 val = 0x7d0; 14080 WRITE_CMIC_SBUS_TIMEOUTr(unit, val); 14081 14082 /* Bring IP, EP, and MMU blocks out of reset */ 14083 READ_CMIC_SOFT_RESET_REGr(unit, &val); 14084 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 14085 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 14086 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 1); 14087 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14088 sal_usleep(to_usec); 14089 14090 if (soc_feature(unit, soc_feature_delay_core_pll_lock)) { 14091 /* assert the active bits of cmic_soft_reset_reg then de-assert */ 14092 READ_CMIC_SOFT_RESET_REGr(unit, &val); 14093 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP0_RST_Lf, 0); 14094 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP1_RST_Lf, 0); 14095 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP2_RST_Lf, 0); 14096 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, 14097 &val, CMIC_XQP0_RST_Lf, 0); 14098 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, 14099 &val, CMIC_XQP1_RST_Lf, 0); 14100 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, 14101 &val, CMIC_XQP2_RST_Lf, 0); 14102 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, 14103 &val, CMIC_XQP3_RST_Lf, 0); 14104 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 0); 14105 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 0); 14106 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 0); 14107 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14108 sal_usleep(to_usec); 14109 14110 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP0_RST_Lf, 1); 14111 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP1_RST_Lf, 1); 14112 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP2_RST_Lf, 1); 14113 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, 14114 &val, CMIC_XQP0_RST_Lf, 1); 14115 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, 14116 &val, CMIC_XQP1_RST_Lf, 1); 14117 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, 14118 &val, CMIC_XQP2_RST_Lf, 1); 14119 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, 14120 &val, CMIC_XQP3_RST_Lf, 1); 14121 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 14122 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 14123 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 1); 14124 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14125 sal_usleep(to_usec); 14126 } 14127 14128 if (soc_feature(unit, soc_feature_gmii_clkout)) { 14129 uint32 rval; 14130 static int16 _L1_port_val_map[] = { 14131 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14132 4, 5, 6, 7, 8, 9, 10, 11, 0, 0, 12, 12, 13, 13 14133 }; /* Note: 24, 25 are invalid, but we are just setting 0 in those cases */ 14134 14135 val = soc_property_get(unit, "L1_primary_clk_recovery_port", 0x0); 14136 if (val >= COUNTOF(_L1_port_val_map)) { 14137 return; 14138 } 14139 READ_CMIC_MISC_CONTROLr(unit, &rval); 14140 if ((val <= 3) || ((val >= 8) && (val <= 15)) || 14141 (val == 26) || (val == 28)) { 14142 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 14143 L1_CLK0_RECOVERY_MUXf, _L1_port_val_map[val]); 14144 } else { 14145 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 14146 L1_CLK1_RECOVERY_MUXf, _L1_port_val_map[val]); 14147 } 14148 14149 val = soc_property_get(unit, "L1_backup_clk_recovery_port", 0x0); 14150 if (val >= COUNTOF(_L1_port_val_map)) { 14151 return; 14152 } 14153 if ((val <= 3) || ((val >= 8) && (val <= 15)) || 14154 (val == 26) || (val == 28)) { 14155 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 14156 L1_CLK0_RECOVERY_MUXf, _L1_port_val_map[val]); 14157 } else { 14158 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 14159 L1_CLK1_RECOVERY_MUXf, _L1_port_val_map[val]); 14160 } 14161 WRITE_CMIC_MISC_CONTROLr(unit, rval); 14162 } 14163 } 14164 #endif /* BCM_ENDURO_SUPPORT */ 14165 14166 #ifdef BCM_SHADOW_SUPPORT 14167 /* 14168 * Function: 14169 * soc_reset_bcm88732_a0 14170 * Purpose: 14171 * Special reset sequencing for BCM88732 14172 * Setup SBUS block mapping. 14173 */ 14174 14175 STATIC void 14176 soc_reset_bcm88732_a0(int unit) 14177 { 14178 uint32 val, val2, to_usec; 14179 uint32 rval, addr; 14180 uint16 dev_id; 14181 uint8 rev_id; 14182 14183 soc_cm_get_id(unit, &dev_id, &rev_id); 14184 14185 val = 0; 14186 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 14187 (10 * MILLISECOND_USEC); 14188 14189 /* Reset all blocks */ 14190 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14191 14192 14193 /* Set NDIV=140 and PDIV=7 (NDIV_INT<< 3 | PDIV)*/ 14194 addr = soc_reg_addr(unit, CMIC_XGXS0_PLL_CONTROL_3r, REG_PORT_ANY, 0); 14195 soc_pci_getreg(unit, addr, &rval); 14196 soc_reg_field_set(unit, CMIC_XGXS0_PLL_CONTROL_3r, &rval, PLLCTRL95_64f, (140 << 3 | 7)); 14197 soc_pci_write(unit, addr, rval); 14198 14199 addr = soc_reg_addr(unit, CMIC_XGXS1_PLL_CONTROL_3r, REG_PORT_ANY, 0); 14200 soc_pci_getreg(unit, addr, &rval); 14201 soc_reg_field_set(unit, CMIC_XGXS1_PLL_CONTROL_3r, &rval, PLLCTRL95_64f, (140 << 3 | 7)); 14202 soc_pci_write(unit, addr, rval); 14203 14204 14205 /* Bring the PLLs out of reset */ 14206 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, LCPLL2_SYS_RESET_Nf, 1); 14207 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, LCPLL1_SYS_RESET_Nf, 1); 14208 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, LCPLL0_SYS_RESET_Nf, 1); 14209 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14210 sal_usleep(to_usec); 14211 14212 /* Miscellaneous other resets */ 14213 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, TEMP_MON_PEAK_RESET_Nf, 14214 1); 14215 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14216 sal_usleep(to_usec); 14217 14218 /* 14219 * Min 20 msec delay after LCPLL reset before checking for lock. 14220 */ 14221 if (!soc_feature(unit, soc_feature_ignore_cmic_xgxs_pll_status) && 14222 !SAL_BOOT_PLISIM && !SAL_BOOT_QUICKTURN) { 14223 uint32 val; 14224 14225 READ_CMIC_XGXS0_PLL_STATUSr(unit, &val); 14226 if (!(soc_reg_field_get(unit, CMIC_XGXS0_PLL_STATUSr, 14227 val, CMIC_XGPLL_LOCKf))) { 14228 LOG_ERROR(BSL_LS_SOC_COMMON, 14229 (BSL_META_U(unit, 14230 "LCPLL 0 not locked on unit %d status = 0x%08x\n"), 14231 unit, val)); 14232 } 14233 14234 READ_CMIC_XGXS1_PLL_STATUSr(unit, &val); 14235 if (!(soc_reg_field_get(unit, CMIC_XGXS1_PLL_STATUSr, 14236 val, CMIC_XGPLL_LOCKf))) { 14237 LOG_ERROR(BSL_LS_SOC_COMMON, 14238 (BSL_META_U(unit, 14239 "LCPLL 1 not locked on unit %d status = 0x%08x\n"), 14240 unit, val)); 14241 } 14242 14243 READ_CMIC_XGXS2_PLL_STATUSr(unit, &val); 14244 if (!(soc_reg_field_get(unit, CMIC_XGXS2_PLL_STATUSr, 14245 val, CMIC_XGPLL_LOCKf))) { 14246 LOG_ERROR(BSL_LS_SOC_COMMON, 14247 (BSL_META_U(unit, 14248 "LCPLL 2 not locked on unit %d status = 0x%08x\n"), 14249 unit, val)); 14250 } 14251 14252 } 14253 14254 14255 /* Bring port blocks out of reset after 1 msec after PLLs */ 14256 READ_CMIC_SOFT_RESET_REGr(unit, &val); 14257 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14258 XLPORT0_SYS_RESET_Nf, 1); 14259 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14260 XLPORT1_SYS_RESET_Nf, 1); 14261 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14262 XLPORT2_SYS_RESET_Nf, 1); 14263 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14264 XLPORT3_SYS_RESET_Nf, 1); 14265 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14266 XLPORT4_SYS_RESET_Nf, 1); 14267 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14268 XLPORT5_SYS_RESET_Nf, 1); 14269 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14270 XLPORT0_LOGIC_RESET_Nf, 1); 14271 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14272 XLPORT1_LOGIC_RESET_Nf, 1); 14273 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14274 XLPORT2_LOGIC_RESET_Nf, 1); 14275 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14276 XLPORT3_LOGIC_RESET_Nf, 1); 14277 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14278 XLPORT4_LOGIC_RESET_Nf, 1); 14279 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14280 XLPORT5_LOGIC_RESET_Nf, 1); 14281 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14282 sal_usleep(to_usec); 14283 14284 val2 = 0; 14285 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &val2, 14286 NS_RST_Lf, 1); 14287 WRITE_CMIC_SOFT_RESET_REG_2r(unit, val2); 14288 14289 /* 14290 * Shadow - ring map programming information taken from the regs file. 14291 */ 14292 val = 0x00321100; 14293 WRITE_CMIC_SBUS_RING_MAP_0r(unit, val); 14294 14295 val = 0x10320411; 14296 WRITE_CMIC_SBUS_RING_MAP_1r(unit, val); 14297 14298 val = 0x00000532; 14299 WRITE_CMIC_SBUS_RING_MAP_2r(unit, val); 14300 14301 val = 0x0; 14302 WRITE_CMIC_SBUS_RING_MAP_3r(unit, val); 14303 14304 /* Bring MACSEC and Interlaken blocks out of reset */ 14305 READ_CMIC_SOFT_RESET_REGr(unit, &val); 14306 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, MS0_SYS_RESET_Nf, 1); 14307 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, MS1_SYS_RESET_Nf, 1); 14308 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, IL0_LOGIC_RESET_Nf, 1); 14309 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, IL0_SYS_RESET_Nf, 1); 14310 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, IL1_LOGIC_RESET_Nf, 1); 14311 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, IL1_SYS_RESET_Nf, 1); 14312 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14313 sal_usleep(to_usec); 14314 14315 /* Bring PE, PD, and MMU blocks out of reset */ 14316 READ_CMIC_SOFT_RESET_REGr(unit, &val); 14317 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, PE0_SYS_RESET_Nf, 1); 14318 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, PE1_SYS_RESET_Nf, 1); 14319 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, PE0_LOGIC_RESET_Nf, 1); 14320 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, PD_SYS_RESET_Nf, 1); 14321 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, MMU0_SYS_RESET_Nf, 1); 14322 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14323 14324 /* Bring temperature monitor out of reset */ 14325 READ_CMIC_SOFT_RESET_REGr(unit, &val); 14326 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14327 TEMP_MON_PEAK_RESET_Nf, 1); 14328 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14329 sal_usleep(to_usec); 14330 } 14331 #endif /* BCM_SHADOW_SUPPORT */ 14332 14333 14334 #ifdef BCM_HURRICANE1_SUPPORT 14335 /* 14336 * Function: 14337 * soc_reset_bcm56142_a0 14338 * Purpose: 14339 * Special reset sequencing for BCM56142 14340 * Setup SBUS block mapping. 14341 */ 14342 14343 STATIC void 14344 soc_reset_bcm56142_a0(int unit) 14345 { 14346 uint32 val, to_usec; 14347 uint16 dev_id; 14348 uint8 rev_id; 14349 14350 soc_cm_get_id(unit, &dev_id, &rev_id); 14351 14352 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 14353 (10 * MILLISECOND_USEC); 14354 14355 14356 /* bring the blocks out of reset */ 14357 READ_CMIC_SOFT_RESET_REGr(unit, &val); 14358 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG0_PLL_RST_Lf, 14359 1); 14360 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14361 sal_usleep(to_usec); 14362 14363 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14364 CMIC_QSGMII2X_SERDES_0_RST_Lf, 1); 14365 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14366 CMIC_QSGMII2X_SERDES_1_RST_Lf, 1); 14367 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, 14368 CMIC_QSGMII2X_SERDES_2_RST_Lf, 1); 14369 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14370 sal_usleep(to_usec); 14371 14372 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP0_RST_Lf, 1); 14373 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP1_RST_Lf, 1); 14374 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_GP2_RST_Lf, 1); 14375 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XQP0_RST_Lf, 1); 14376 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XQP1_RST_Lf, 1); 14377 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XQP2_RST_Lf, 1); 14378 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XQP3_RST_Lf, 1); 14379 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14380 sal_usleep(to_usec); 14381 14382 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ0_HOTSWAP_RST_Lf, 1); 14383 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ1_HOTSWAP_RST_Lf, 1); 14384 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ2_HOTSWAP_RST_Lf, 1); 14385 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XQ3_HOTSWAP_RST_Lf, 1); 14386 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, THERMAL_MON_RESETf, 1); 14387 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14388 sal_usleep(to_usec); 14389 14390 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, THERMAL_MON_RESETf, 0); 14391 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14392 sal_usleep(to_usec); 14393 14394 14395 val = 0x11122200; 14396 WRITE_CMIC_SBUS_RING_MAP_0r(unit, val); 14397 val = 0x00330001; 14398 WRITE_CMIC_SBUS_RING_MAP_1r(unit, val); 14399 val = 0x0; 14400 WRITE_CMIC_SBUS_RING_MAP_2r(unit, val); 14401 WRITE_CMIC_SBUS_RING_MAP_3r(unit, val); 14402 WRITE_CMIC_SBUS_RING_MAP_4r(unit, val); 14403 WRITE_CMIC_SBUS_RING_MAP_5r(unit, val); 14404 WRITE_CMIC_SBUS_RING_MAP_6r(unit, val); 14405 WRITE_CMIC_SBUS_RING_MAP_7r(unit, val); 14406 14407 val = 0x7d0; 14408 WRITE_CMIC_SBUS_TIMEOUTr(unit, val); 14409 14410 /* Bring IP, EP, and MMU blocks out of reset */ 14411 READ_CMIC_SOFT_RESET_REGr(unit, &val); 14412 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 14413 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 14414 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 1); 14415 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, NS_RST_Lf, 1); 14416 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 14417 sal_usleep(to_usec); 14418 14419 } 14420 #endif /* BCM_HURRICANE_SUPPORT */ 14421 14422 #ifdef BCM_HURRICANE2_SUPPORT 14423 /* 14424 * Function: 14425 * soc_reset_bcm56150_a0 14426 * Purpose: 14427 * Special reset sequencing for BCM56150 14428 */ 14429 14430 STATIC int 14431 soc_reset_bcm56150_a0(int unit) 14432 { 14433 uint32 rval, to_usec; 14434 uint16 dev_id; 14435 uint8 rev_id; 14436 14437 unsigned ts_ref_freq; 14438 unsigned ts_idx; 14439 static const soc_pll_param_t ts_pll[] = { /* values for 500MHz TSPLL output */ 14440 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 14441 {12800000, 312, 0x80000, 1, 8, 1, 2, 7, 1}, 14442 {20000000, 200, 0, 1, 8, 2, 3, 8, 1}, 14443 {25000000, 160, 0, 1, 8, 2, 4, 9, 1}, 14444 {32000000, 125, 0, 1, 8, 2, 4, 9, 1}, 14445 {50000000, 80, 0, 1, 8, 3, 4, 10, 1}, 14446 { 0, 160, 0, 1, 8, 2, 4, 9, 1} /* 25MHz, from internal reference */ 14447 }; 14448 unsigned bs_ref_freq; 14449 unsigned bs_idx; 14450 uint32 bs_ndiv_high, bs_ndiv_low; 14451 static const soc_pll_param_t bs_pll[] = { /* values for 20MHz BSPLL output */ 14452 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 14453 {12800000, 250, 0, 1, 160, 1, 2, 7, 0}, 14454 {20000000, 175, 0, 1, 175, 2, 3, 8, 0}, 14455 {25000000, 140, 0, 1, 175, 2, 4, 9, 0}, 14456 {32000000, 108, 0xc0000000, 1, 174, 2, 4, 9, 0}, /* Ndiv=108.75 */ 14457 {50000000, 70, 0, 1, 175, 3, 4, 10, 0}, 14458 { 0, 140, 0, 1, 175, 2, 4, 9, 0} /* 25MHz, from internal reference */ 14459 }; 14460 #if defined(BCM_HITLESS_RESET_SUPPORT) 14461 int initialize_broadsync; 14462 const int broadsync_default_ka = 4, broadsync_default_ki = 1, broadsync_default_kp = 8; 14463 #endif /* BCM_HITLESS_RESET_SUPPORT */ 14464 14465 soc_cm_get_id(unit, &dev_id, &rev_id); 14466 14467 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 14468 (10 * MILLISECOND_USEC); 14469 14470 /* 14471 * SBUS ring and block number: 14472 * Ring0: cmic -> ip-ep -> cmic 14473 * Ring1: cmic -> xqport0 -> xqport1-> xqport2 -> xqport3-> cmic 14474 * Ring2: cmic -> gport0 -> gport1 -> gport2 -> cmic 14475 * Ring3: cmic -> otpc -> mmu -> cmic 14476 * Ring 4,5,6,7 unused 14477 */ 14478 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x11122200); /* block 7 - 0 */ 14479 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x00430000); /* block 15 - 8 */ 14480 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x00005004); /* block 23 - 16 */ 14481 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x00000000); /* block 31 - 24 */ 14482 14483 /* Bring LCPLL out of reset */ 14484 14485 sal_usleep(to_usec); 14486 14487 /* Use 156.25Mhz external or internal reference clock for LCPLL */ 14488 READ_TOP_PLL_BYP_AND_REFCLK_CONTROLr(unit, &rval); 14489 soc_reg_field_set(unit, TOP_PLL_BYP_AND_REFCLK_CONTROLr, &rval, 14490 LC_PLL1_REFCLK_SELf, 14491 soc_property_get(unit, spn_XGXS_LCPLL_XTAL_REFCLK, 0)); 14492 WRITE_TOP_PLL_BYP_AND_REFCLK_CONTROLr(unit, rval); 14493 14494 READ_TOP_XG_PLL1_CTRL_3r(unit, &rval); 14495 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_3r, &rval, 14496 CML_BYP_ENf, 14497 soc_property_get(unit, spn_XGXS_LCPLL_XTAL_REFCLK, 0)); 14498 WRITE_TOP_XG_PLL1_CTRL_3r(unit, rval); 14499 14500 14501 /* TSPLL configuration: 500MHz TS_CLK from 20/25/32/50MHz refclk */ 14502 /* CMICd divides by 2 on input, so this is a 250MHz clock to TS logic */ 14503 14504 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); /* 0->internal reference */ 14505 /* Set TS_PLL_CLK_IN_SEL based on reference frequency. If it is 0, use the internal reference */ 14506 SOC_IF_ERROR_RETURN(READ_TOP_PLL_BYP_AND_REFCLK_CONTROLr(unit,&rval)); 14507 soc_reg_field_set(unit, TOP_PLL_BYP_AND_REFCLK_CONTROLr, &rval, TS_PLL_REFCLK_SELf, 14508 (ts_ref_freq != 0)); 14509 WRITE_TOP_PLL_BYP_AND_REFCLK_CONTROLr(unit, rval); 14510 14511 for (ts_idx = 0; ts_idx < sizeof(ts_pll)/sizeof(ts_pll[0]); ++ts_idx) { 14512 if (ts_pll[ts_idx].ref_freq == ts_ref_freq) { 14513 break; 14514 } 14515 } 14516 if (ts_idx == sizeof(ts_pll)/sizeof(ts_pll[0])) { 14517 LOG_ERROR(BSL_LS_SOC_COMMON, 14518 (BSL_META_U(unit, 14519 "Invalid value for PTP_TS_PLL_REF (%u). No default PLL params.\n"), ts_ref_freq)); 14520 /* Could check for existence of SOC properties for VCO_DIV2, KA, KI, KP, NDIV_INT, NDIV_FRAC, MDIV, PDIV, and if 14521 all exist, use them. For now, just fail. 14522 */ 14523 } else { 14524 /* Enable software overwrite of TimeSync PLL settings. */ 14525 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit, &rval)); 14526 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_TS_PLL_LOADf, 1); 14527 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 14528 14529 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_0r(unit,&rval)); 14530 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_0r, &rval, VCO_DIV2f, 14531 soc_property_get(unit, spn_PTP_TS_VCO_DIV2, ts_pll[ts_idx].vco_div2)); 14532 WRITE_TOP_TS_PLL_CTRL_0r(unit, rval); 14533 14534 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_4r(unit,&rval)); 14535 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KAf, 14536 soc_property_get(unit, spn_PTP_TS_KA, ts_pll[ts_idx].ka)); 14537 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KIf, 14538 soc_property_get(unit, spn_PTP_TS_KI, ts_pll[ts_idx].ki)); 14539 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KPf, 14540 soc_property_get(unit, spn_PTP_TS_KP, ts_pll[ts_idx].kp)); 14541 WRITE_TOP_TS_PLL_CTRL_4r(unit, rval); 14542 14543 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_3r(unit,&rval)); 14544 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_INTf, 14545 soc_property_get(unit, spn_PTP_TS_PLL_N, ts_pll[ts_idx].ndiv_int)); 14546 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_FRACf, 14547 ts_pll[ts_idx].ndiv_frac); 14548 WRITE_TOP_TS_PLL_CTRL_3r(unit, rval); 14549 14550 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_2r(unit,&rval)); 14551 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, PDIVf, 14552 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, ts_pll[ts_idx].pdiv)); 14553 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, CH0_MDIVf, 14554 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, ts_pll[ts_idx].mdiv)); 14555 WRITE_TOP_TS_PLL_CTRL_2r(unit, rval); 14556 14557 /* Strobe channel-0 load-enable to set divisors. */ 14558 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_2r(unit,&rval)); 14559 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, LOAD_EN_CH0f, 0); 14560 WRITE_TOP_TS_PLL_CTRL_2r(unit, rval); 14561 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, LOAD_EN_CH0f, 1); 14562 WRITE_TOP_TS_PLL_CTRL_2r(unit, rval); 14563 } 14564 14565 /* 500Mhz TSPLL -> 250MHz ref at timestamper, implies 4ns resolution */ 14566 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); /* clock period in nanoseconds */ 14567 14568 /* Check to see if the BSPLLs have been configured yet. If so, we leave them alone, 14569 for hitless reset support. 14570 Note: On KT2 A0/B0, the BroadSync Bitclock/Heartbeat regs get reset, so we still 14571 initialize all of BroadSync. 14572 */ 14573 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_1r(unit,&rval)); 14574 14575 #if defined(BCM_HITLESS_RESET_SUPPORT) 14576 initialize_broadsync = 14577 (soc_reg_field_get(unit, TOP_BS_PLL0_CTRL_1r, 14578 rval, KAf) == broadsync_default_ka 14579 && soc_reg_field_get(unit, TOP_BS_PLL0_CTRL_1r, 14580 rval, KIf) == broadsync_default_ki 14581 && soc_reg_field_get(unit, TOP_BS_PLL0_CTRL_1r, 14582 rval, KPf) == broadsync_default_kp); 14583 14584 LOG_VERBOSE(BSL_LS_SOC_COMMON, 14585 (BSL_META_U(unit, 14586 "BSPLL regs: %s\n"), initialize_broadsync ? "Default" : "Configured")); 14587 14588 if (!initialize_broadsync) { 14589 /* JIRA CMICD-110 14590 * On A0/B0, BroadSync Bitclock/Heartbeat divisors/enable registers get reset, 14591 * though the outputs themselves do not if the registers were written to an even 14592 * number of times. Workaround: when the registers are changed, the register 14593 * should be written twice, and the same value stored in SRAM. This code will 14594 * restore the register from SRAM. 14595 */ 14596 14597 /* BS0 */ 14598 uint32 reg_cache_base = soc_cmic_bs_reg_cache(unit, 0); 14599 14600 uint32 config = soc_uc_mem_read(unit, 14601 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, config)); 14602 uint32 clk_ctrl = soc_uc_mem_read(unit, 14603 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, clk_ctrl)); 14604 uint32 heartbeat_ctrl = soc_uc_mem_read(unit, 14605 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl)); 14606 uint32 heartbeat_down = soc_uc_mem_read(unit, 14607 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration)); 14608 uint32 heartbeat_up = soc_uc_mem_read(unit, 14609 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration)); 14610 14611 if (config == 0 && clk_ctrl == 0 && heartbeat_ctrl == 0 && heartbeat_down == 0 && heartbeat_up == 0) { 14612 /* PLL was initialized, but there is no saved state. Reset BroadSync. */ 14613 initialize_broadsync = 1; 14614 LOG_ERROR(BSL_LS_SOC_COMMON, 14615 (BSL_META_U(unit, 14616 "BSPLL Configured, but no BS state to restore\n"))); 14617 } else { 14618 /* Double-writes, per CMICD-110 WAR */ 14619 WRITE_CMIC_BS0_CONFIGr(unit, config); 14620 WRITE_CMIC_BS0_CONFIGr(unit, config); 14621 WRITE_CMIC_BS0_CLK_CTRLr(unit, clk_ctrl); 14622 WRITE_CMIC_BS0_CLK_CTRLr(unit, clk_ctrl); 14623 WRITE_CMIC_BS0_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 14624 WRITE_CMIC_BS0_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 14625 WRITE_CMIC_BS0_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 14626 WRITE_CMIC_BS0_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 14627 WRITE_CMIC_BS0_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 14628 WRITE_CMIC_BS0_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 14629 14630 LOG_VERBOSE(BSL_LS_SOC_COMMON, 14631 (BSL_META_U(unit, 14632 "Restored BS0 regs:\n" 14633 " config: %08x clk_ctrl: %08x hb_ctrl: %08x\n" 14634 " hb_up: %08x hb_down: %08x\n"), 14635 config, clk_ctrl, heartbeat_ctrl, 14636 heartbeat_down, heartbeat_up)); 14637 14638 /* same, but for BS1 */ 14639 reg_cache_base = soc_cmic_bs_reg_cache(unit, 1); 14640 14641 config = soc_uc_mem_read(unit, 14642 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, config)); 14643 clk_ctrl = soc_uc_mem_read(unit, 14644 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, clk_ctrl)); 14645 heartbeat_ctrl = soc_uc_mem_read(unit, 14646 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl)); 14647 heartbeat_down = soc_uc_mem_read(unit, 14648 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration)); 14649 heartbeat_up = soc_uc_mem_read(unit, 14650 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration)); 14651 14652 WRITE_CMIC_BS1_CONFIGr(unit, config); 14653 WRITE_CMIC_BS1_CONFIGr(unit, config); 14654 WRITE_CMIC_BS1_CLK_CTRLr(unit, clk_ctrl); 14655 WRITE_CMIC_BS1_CLK_CTRLr(unit, clk_ctrl); 14656 WRITE_CMIC_BS1_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 14657 WRITE_CMIC_BS1_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 14658 WRITE_CMIC_BS1_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 14659 WRITE_CMIC_BS1_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 14660 WRITE_CMIC_BS1_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 14661 WRITE_CMIC_BS1_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 14662 14663 LOG_VERBOSE(BSL_LS_SOC_COMMON, 14664 (BSL_META_U(unit, 14665 "Restored BS1 regs:\n" 14666 " config: %08x clk_ctrl: %08x hb_ctrl: %08x\n" 14667 " hb_up: %08x hb_down: %08x\n"), 14668 config, clk_ctrl, heartbeat_ctrl, 14669 heartbeat_down, heartbeat_up)); 14670 } 14671 } 14672 14673 if (initialize_broadsync) 14674 #endif /* BCM_HITLESS_RESET_SUPPORT */ 14675 { 14676 /* as a signal to upper-level code that the BroadSync is newly initialized 14677 * disable BroadSync0/1 bitclock output. Checked in time.c / 1588 firmware */ 14678 /* coverity[result_independent_of_operands] */ 14679 SOC_IF_ERROR_RETURN(READ_CMIC_BS0_CONFIGr(unit, &rval)); 14680 soc_reg_field_set(unit, CMIC_BS0_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 14681 WRITE_CMIC_BS0_CONFIGr(unit, rval); 14682 14683 /* coverity[result_independent_of_operands] */ 14684 SOC_IF_ERROR_RETURN(READ_CMIC_BS1_CONFIGr(unit, &rval)); 14685 soc_reg_field_set(unit, CMIC_BS1_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 14686 WRITE_CMIC_BS1_CONFIGr(unit, rval); 14687 14688 /* BSPLL0 has not been configured, so reset/configure both BSPLL0 and BSPLL1 */ 14689 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 14690 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_RST_Lf, 0); 14691 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_RST_Lf, 0); 14692 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_POST_RST_Lf, 0); 14693 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_POST_RST_Lf, 0); 14694 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 14695 14696 /* Both BSPLLs configured the same, for 20MHz output by default */ 14697 14698 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 0); /* 0->internal reference */ 14699 /* Set BS_PLL_CLK_IN_SEL based on reference frequency. If it is 0, use the internal reference */ 14700 SOC_IF_ERROR_RETURN(READ_TOP_PLL_BYP_AND_REFCLK_CONTROLr(unit,&rval)); 14701 soc_reg_field_set(unit, TOP_PLL_BYP_AND_REFCLK_CONTROLr, &rval, BS_PLL0_REFCLK_SELf, 14702 (bs_ref_freq != 0)); 14703 soc_reg_field_set(unit, TOP_PLL_BYP_AND_REFCLK_CONTROLr, &rval, BS_PLL1_REFCLK_SELf, 14704 (bs_ref_freq != 0)); 14705 WRITE_TOP_PLL_BYP_AND_REFCLK_CONTROLr(unit, rval); 14706 14707 for (bs_idx = 0; bs_idx < sizeof(bs_pll)/sizeof(bs_pll[0]); ++bs_idx) { 14708 if (bs_pll[bs_idx].ref_freq == bs_ref_freq) { 14709 break; 14710 } 14711 } 14712 if (bs_idx == sizeof(bs_pll)/sizeof(bs_pll[0])) { 14713 LOG_ERROR(BSL_LS_SOC_COMMON, 14714 (BSL_META_U(unit, 14715 "Invalid value for PTP_BS_REF (%u). No default PLL params.\n"), bs_ref_freq)); 14716 /* Could check for existence of SOC properties for VCO_DIV2, KA, KI, KP, NDIV_INT, 14717 NDIV_FRAC, MDIV, PDIV, and if all exist, use them. For now, just fail. 14718 */ 14719 } else { 14720 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_3r(unit,&rval)); 14721 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_3r, &rval, VCODIV2f, 14722 soc_property_get(unit, spn_PTP_BS_VCO_DIV2, bs_pll[bs_idx].vco_div2)); 14723 WRITE_TOP_BS_PLL0_CTRL_3r(unit, rval); 14724 14725 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_3r(unit,&rval)); 14726 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_3r, &rval, VCODIV2f, 14727 soc_property_get(unit, spn_PTP_BS_VCO_DIV2, bs_pll[bs_idx].vco_div2)); 14728 WRITE_TOP_BS_PLL1_CTRL_3r(unit, rval); 14729 14730 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_1r(unit,&rval)); 14731 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, KAf, 14732 soc_property_get(unit, spn_PTP_BS_KA, bs_pll[bs_idx].ka)); 14733 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, KIf, 14734 soc_property_get(unit, spn_PTP_BS_KI, bs_pll[bs_idx].ki)); 14735 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, KPf, 14736 soc_property_get(unit, spn_PTP_BS_KP, bs_pll[bs_idx].kp)); 14737 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, PDIVf, 14738 soc_property_get(unit, spn_PTP_BS_PDIV, bs_pll[bs_idx].pdiv)); 14739 WRITE_TOP_BS_PLL0_CTRL_1r(unit, rval); 14740 14741 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_1r(unit,&rval)); 14742 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, KAf, 14743 soc_property_get(unit, spn_PTP_BS_KA, bs_pll[bs_idx].ka)); 14744 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, KIf, 14745 soc_property_get(unit, spn_PTP_BS_KI, bs_pll[bs_idx].ki)); 14746 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, KPf, 14747 soc_property_get(unit, spn_PTP_BS_KP, bs_pll[bs_idx].kp)); 14748 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, PDIVf, 14749 soc_property_get(unit, spn_PTP_BS_PDIV, bs_pll[bs_idx].pdiv)); 14750 WRITE_TOP_BS_PLL1_CTRL_1r(unit, rval); 14751 14752 bs_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, bs_pll[bs_idx].ndiv_int) << 8) | 14753 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs_pll[bs_idx].ndiv_frac) >> 24) & 0xff)); 14754 bs_ndiv_low = (soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs_pll[bs_idx].ndiv_frac) << 8); 14755 14756 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 14757 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r, &rval, BROAD_SYNC0_LCPLL_FBDIV_1f, bs_ndiv_high); 14758 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit, rval); 14759 14760 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 14761 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r, &rval, BROAD_SYNC0_LCPLL_FBDIV_0f, bs_ndiv_low); 14762 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit, rval); 14763 14764 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 14765 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r, &rval, BROAD_SYNC1_LCPLL_FBDIV_1f, bs_ndiv_high); 14766 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit, rval); 14767 14768 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 14769 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r, &rval, BROAD_SYNC1_LCPLL_FBDIV_0f, bs_ndiv_low); 14770 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit, rval); 14771 14772 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_0r(unit,&rval)); 14773 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_0r, &rval, CH0_MDIVf, 14774 soc_property_get(unit, spn_PTP_BS_MNDIV, bs_pll[bs_idx].mdiv)); 14775 WRITE_TOP_BS_PLL0_CTRL_0r(unit, rval); 14776 14777 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_0r(unit,&rval)); 14778 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_0r, &rval, CH0_MDIVf, 14779 soc_property_get(unit, spn_PTP_BS_MNDIV, bs_pll[bs_idx].mdiv)); 14780 WRITE_TOP_BS_PLL1_CTRL_0r(unit, rval); 14781 14782 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_1r(unit,&rval)); 14783 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, LOAD_EN_CHf, 0); 14784 WRITE_TOP_BS_PLL0_CTRL_1r(unit, rval); 14785 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_1r, &rval, LOAD_EN_CHf, 1); 14786 WRITE_TOP_BS_PLL0_CTRL_1r(unit, rval); 14787 14788 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_1r(unit,&rval)); 14789 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, LOAD_EN_CHf, 0); 14790 WRITE_TOP_BS_PLL1_CTRL_1r(unit, rval); 14791 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_1r, &rval, LOAD_EN_CHf, 1); 14792 WRITE_TOP_BS_PLL1_CTRL_1r(unit, rval); 14793 } 14794 14795 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 14796 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_RST_Lf, 1); 14797 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_RST_Lf, 1); 14798 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 14799 14800 /* JIRA CMICD-110: See above logic to restore BroadSync Bitclock/Heartbeat. */ 14801 /* Store default values in the SRAM, so they will be restored correctly */ 14802 /* even if SRAM is not used */ 14803 #if defined(BCM_HITLESS_RESET_SUPPORT) 14804 { 14805 /* store reset values in SRAM for BS0 */ 14806 uint32 reg_cache_base = soc_cmic_bs_reg_cache(unit, 0); 14807 READ_CMIC_BS0_CONFIGr(unit, &rval); 14808 soc_uc_mem_write(unit, reg_cache_base + 14809 offsetof(mos_msg_bs_reg_cache_t, config), rval); 14810 READ_CMIC_BS0_CLK_CTRLr(unit, &rval); 14811 soc_uc_mem_write(unit, reg_cache_base + 14812 offsetof(mos_msg_bs_reg_cache_t, clk_ctrl), rval); 14813 READ_CMIC_BS0_HEARTBEAT_CTRLr(unit, &rval); 14814 soc_uc_mem_write(unit, reg_cache_base + 14815 offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl), rval); 14816 READ_CMIC_BS0_HEARTBEAT_DOWN_DURATIONr(unit, &rval); 14817 soc_uc_mem_write(unit, reg_cache_base + 14818 offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration), rval); 14819 READ_CMIC_BS0_HEARTBEAT_UP_DURATIONr(unit, &rval); 14820 soc_uc_mem_write(unit, reg_cache_base + 14821 offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration), rval); 14822 14823 /* store reset values in SRAM for BS1 */ 14824 reg_cache_base = soc_cmic_bs_reg_cache(unit, 1); 14825 READ_CMIC_BS1_CONFIGr(unit, &rval); 14826 soc_uc_mem_write(unit, reg_cache_base + 14827 offsetof(mos_msg_bs_reg_cache_t, config), rval); 14828 READ_CMIC_BS1_CLK_CTRLr(unit, &rval); 14829 soc_uc_mem_write(unit, reg_cache_base + 14830 offsetof(mos_msg_bs_reg_cache_t, clk_ctrl), rval); 14831 READ_CMIC_BS1_HEARTBEAT_CTRLr(unit, &rval); 14832 soc_uc_mem_write(unit, reg_cache_base + 14833 offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl), rval); 14834 READ_CMIC_BS1_HEARTBEAT_DOWN_DURATIONr(unit, &rval); 14835 soc_uc_mem_write(unit, reg_cache_base + 14836 offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration), rval); 14837 READ_CMIC_BS1_HEARTBEAT_UP_DURATIONr(unit, &rval); 14838 soc_uc_mem_write(unit, reg_cache_base + 14839 offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration), rval); 14840 } 14841 } else { 14842 LOG_CLI((BSL_META_U(unit, 14843 "Leaving BroadSync in holdover\n"))); 14844 #endif /* BCM_HITLESS_RESET_SUPPORT */ 14845 } 14846 14847 #if defined(BCM_HITLESS_RESET_SUPPORT) 14848 if (initialize_broadsync) 14849 #endif /* BCM_HITLESS_RESET_SUPPORT */ 14850 { 14851 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 14852 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_POST_RST_Lf, 1); 14853 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_POST_RST_Lf, 1); 14854 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 14855 } 14856 14857 /* Check for M, A and Plain versions */ 14858 SOC_IF_ERROR_RETURN(READ_TOP_SWITCH_FEATURE_ENABLEr(unit, &rval)); 14859 if (rval & 0x1) { 14860 /* BOND_1588_ENABLE */ 14861 SOC_FEATURE_SET(unit, soc_feature_timesync_support); 14862 LOG_CLI((BSL_META_U(unit, 14863 "BOND_1588_ENABLE : " 14864 "enabling soc_feature_timesync_support\n"))); 14865 } 14866 14867 /* De-assert LCPLL's post reset */ 14868 14869 /* 14870 * Bring port blocks out of reset 14871 */ 14872 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 14873 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP0_RST_Lf, 1); 14874 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP1_RST_Lf, 1); 14875 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_QSGMII2X2_RST_Lf, 1); 14876 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_QSGMII2X1_RST_Lf, 1); 14877 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_QSGMII2X0_RST_Lf, 1); 14878 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_QSGMII2X2_FIFO_RST_Lf, 1); 14879 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_QSGMII2X1_FIFO_RST_Lf, 1); 14880 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_QSGMII2X0_FIFO_RST_Lf, 1); 14881 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GP2_RST_Lf, 1); 14882 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GP1_RST_Lf, 1); 14883 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GP0_RST_Lf, 1); 14884 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_QGPHY_RST_Lf, 0xf); 14885 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 14886 sal_usleep(to_usec); 14887 14888 /* Bring network sync out of reset */ 14889 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 14890 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_TS_RST_Lf, 1); 14891 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_SPARE_RST_Lf, 1); 14892 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 14893 14894 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 14895 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_RST_Lf, 1); 14896 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 14897 14898 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_POST_RST_Lf, 1); 14899 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 14900 14901 sal_usleep(to_usec); 14902 /* coverity[result_independent_of_operands] */ 14903 SOC_IF_ERROR_RETURN(WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0)); 14904 14905 /* Bring IP, EP, and MMU blocks out of reset */ 14906 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 14907 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 14908 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 14909 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 14910 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 14911 sal_usleep(to_usec); 14912 14913 /* reset PVTMON */ 14914 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_0r(unit, &rval)); 14915 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, FUNC_MODE_SELf, 0); 14916 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, MEASUREMENT_CALLIBRATIONf, 5); 14917 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, BG_ADJf, 3); 14918 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_0r(unit, rval)); 14919 14920 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 14921 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 14922 TOP_TEMP_MON_PEAK_RST_Lf, 0); 14923 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 14924 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 14925 TOP_TEMP_MON_PEAK_RST_Lf, 1); 14926 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 14927 14928 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_1r(unit, &rval)); 14929 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_SELECTf, 0); 14930 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RESET_Nf, 0); 14931 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 14932 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RESET_Nf, 1); 14933 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 14934 14935 /* LCPLL CML optimization */ 14936 if ((dev_id == BCM56150_DEVICE_ID) || (dev_id == BCM56152_DEVICE_ID) || \ 14937 (dev_id == BCM53346_DEVICE_ID) || (dev_id == BCM53344_DEVICE_ID) || \ 14938 (dev_id == BCM53343_DEVICE_ID) || (dev_id == BCM53342_DEVICE_ID) || \ 14939 (dev_id == BCM53333_DEVICE_ID) || (dev_id == BCM53334_DEVICE_ID)) { 14940 SOC_IF_ERROR_RETURN(READ_TOP_XG_PLL0_CTRL_3r(unit, &rval)); 14941 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_3r, &rval, CML_2ED_OUT_ENf, 0); 14942 SOC_IF_ERROR_RETURN(WRITE_TOP_XG_PLL0_CTRL_3r(unit, rval)); 14943 14944 SOC_IF_ERROR_RETURN(READ_TOP_XG_PLL1_CTRL_3r(unit, &rval)); 14945 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_3r, &rval, CML_2ED_OUT_ENf, 0); 14946 SOC_IF_ERROR_RETURN(WRITE_TOP_XG_PLL1_CTRL_3r(unit, rval)); 14947 14948 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_3r(unit, &rval)); 14949 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_3r, &rval, CML_2ED_OUT_ENf, 0); 14950 SOC_IF_ERROR_RETURN(WRITE_TOP_BS_PLL0_CTRL_3r(unit, rval)); 14951 14952 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_3r(unit, &rval)); 14953 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_3r, &rval, CML_2ED_OUT_ENf, 0); 14954 SOC_IF_ERROR_RETURN(WRITE_TOP_BS_PLL1_CTRL_3r(unit, rval)); 14955 14956 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit, &rval)); 14957 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_XG_PLL0_SW_OVWRf, 1); 14958 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_XG_PLL1_SW_OVWRf, 1); 14959 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_BS_PLL0_SW_OVWRf, 1); 14960 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_BS_PLL1_SW_OVWRf, 1); 14961 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_1r(unit, rval)); 14962 } 14963 14964 if ((dev_id == BCM56151_DEVICE_ID) || (dev_id == BCM53393_DEVICE_ID) || \ 14965 (dev_id == BCM53394_DEVICE_ID) || (dev_id == BCM53347_DEVICE_ID)) { 14966 SOC_IF_ERROR_RETURN(READ_TOP_XG_PLL1_CTRL_3r(unit, &rval)); 14967 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_3r, &rval, CML_2ED_OUT_ENf, 0); 14968 SOC_IF_ERROR_RETURN(WRITE_TOP_XG_PLL1_CTRL_3r(unit, rval)); 14969 14970 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_3r(unit, &rval)); 14971 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_3r, &rval, CML_2ED_OUT_ENf, 0); 14972 SOC_IF_ERROR_RETURN(WRITE_TOP_BS_PLL0_CTRL_3r(unit, rval)); 14973 14974 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_3r(unit, &rval)); 14975 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_3r, &rval, CML_2ED_OUT_ENf, 0); 14976 SOC_IF_ERROR_RETURN(WRITE_TOP_BS_PLL1_CTRL_3r(unit, rval)); 14977 14978 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit, &rval)); 14979 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_XG_PLL1_SW_OVWRf, 1); 14980 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_BS_PLL0_SW_OVWRf, 1); 14981 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, CMIC_TO_BS_PLL1_SW_OVWRf, 1); 14982 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_1r(unit, rval)); 14983 } 14984 14985 /* For 53343, power down unused qsgmii */ 14986 if (dev_id == BCM53343_DEVICE_ID) { 14987 SOC_IF_ERROR_RETURN(READ_TOP_QSGMII2X_CTRLr(unit, &rval)); 14988 soc_reg_field_set(unit, TOP_QSGMII2X_CTRLr, &rval, IDDQf, 0x7); 14989 SOC_IF_ERROR_RETURN(WRITE_TOP_QSGMII2X_CTRLr(unit, rval)); 14990 } 14991 /* For 53342, power down unused qsgmii and unused qgphy */ 14992 if (dev_id == BCM53342_DEVICE_ID) { 14993 SOC_IF_ERROR_RETURN(READ_TOP_QGPHY_CTRL_0r(unit, &rval)); 14994 soc_reg_field_set(unit, TOP_QGPHY_CTRL_0r, &rval, IDDQ_BIASf, 0xc); 14995 soc_reg_field_set(unit, TOP_QGPHY_CTRL_0r, &rval, EXT_PWRDOWNf, 0xff00); 14996 SOC_IF_ERROR_RETURN(WRITE_TOP_QGPHY_CTRL_0r(unit, rval)); 14997 14998 SOC_IF_ERROR_RETURN(READ_TOP_QSGMII2X_CTRLr(unit, &rval)); 14999 soc_reg_field_set(unit, TOP_QSGMII2X_CTRLr, &rval, IDDQf, 0x3); 15000 SOC_IF_ERROR_RETURN(WRITE_TOP_QSGMII2X_CTRLr(unit, rval)); 15001 } 15002 15003 /* For 53343, power down unused qsgmii */ 15004 if (dev_id == BCM53343_DEVICE_ID) { 15005 SOC_IF_ERROR_RETURN(READ_TOP_QSGMII2X_CTRLr(unit, &rval)); 15006 soc_reg_field_set(unit, TOP_QSGMII2X_CTRLr, &rval, IDDQf, 0x3); 15007 SOC_IF_ERROR_RETURN(WRITE_TOP_QSGMII2X_CTRLr(unit, rval)); 15008 } 15009 /* For 53342, power down unused qsgmii and unused qgphy */ 15010 if (dev_id == BCM53342_DEVICE_ID) { 15011 SOC_IF_ERROR_RETURN(READ_TOP_QGPHY_CTRL_0r(unit, &rval)); 15012 soc_reg_field_set(unit, TOP_QGPHY_CTRL_0r, &rval, IDDQ_BIASf, 0xc); 15013 soc_reg_field_set(unit, TOP_QGPHY_CTRL_0r, &rval, EXT_PWRDOWNf, 0xff00); 15014 SOC_IF_ERROR_RETURN(WRITE_TOP_QGPHY_CTRL_0r(unit, rval)); 15015 15016 SOC_IF_ERROR_RETURN(READ_TOP_QSGMII2X_CTRLr(unit, &rval)); 15017 soc_reg_field_set(unit, TOP_QSGMII2X_CTRLr, &rval, IDDQf, 0x3); 15018 SOC_IF_ERROR_RETURN(WRITE_TOP_QSGMII2X_CTRLr(unit, rval)); 15019 } 15020 15021 return SOC_E_NONE; 15022 } 15023 15024 #endif /* BCM_HURRICANE2_SUPPORT */ 15025 15026 #ifdef BCM_SCORPION_SUPPORT 15027 /* 15028 * Function: 15029 * soc_reset_bcm56820_a0 15030 * Purpose: 15031 * Special reset sequencing for BCM56820 15032 * Setup SBUS block mapping. 15033 */ 15034 15035 STATIC void 15036 soc_reset_bcm56820_a0(int unit) 15037 { 15038 uint32 val, to_usec; 15039 uint16 dev_id; 15040 uint8 rev_id; 15041 15042 soc_cm_get_id(unit, &dev_id, &rev_id); 15043 15044 val = 0; 15045 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 15046 (10 * MILLISECOND_USEC); 15047 15048 /* Reset all blocks */ 15049 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 15050 15051 15052 if (soc_feature(unit, soc_feature_delay_core_pll_lock) && 15053 soc_property_get(unit, "delay_core_pll_lock", 0)) { 15054 /* Core clock lock */ 15055 READ_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, &val); 15056 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15057 NDIV_INTf, 80); 15058 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15059 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15060 NDIV_INTf, 76); 15061 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15062 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15063 NDIV_INTf, 72); 15064 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15065 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15066 NDIV_INTf, 68); 15067 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15068 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15069 NDIV_INTf, 66); 15070 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15071 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15072 NDIV_INTf, 64); 15073 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15074 15075 READ_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0r(unit, &val); 15076 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0r, &val, 15077 ICPXf, 0xe); 15078 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0r(unit, val); 15079 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0r, &val, 15080 KVCO_XSf, 0x4); 15081 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0r(unit, val); 15082 15083 READ_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1r(unit, &val); 15084 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1r, &val, 15085 VCO_RNGf, 0); 15086 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1r(unit, val); 15087 15088 READ_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, &val); 15089 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15090 NDIV_INTf, 60); 15091 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15092 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15093 NDIV_INTf, 56); 15094 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15095 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15096 NDIV_INTf, 52); 15097 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15098 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15099 NDIV_INTf, 48); 15100 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15101 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, &val, 15102 NDIV_INTf, 44); 15103 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15104 15105 READ_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2r(unit, &val); 15106 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2r, &val, 15107 M1DIVf, 5); 15108 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2r(unit, val); 15109 15110 if (dev_id != BCM56820_DEVICE_ID) { 15111 READ_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, &val); 15112 soc_reg_field_set(unit, CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, 15113 &val, NDIV_INTf, 45); 15114 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15115 if ((dev_id == BCM56822_DEVICE_ID) || 15116 (dev_id == BCM56823_DEVICE_ID) || 15117 (dev_id == BCM56725_DEVICE_ID)) { 15118 soc_reg_field_set(unit, 15119 CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r, 15120 &val, NDIV_INTf, 49); 15121 WRITE_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3r(unit, val); 15122 } 15123 } 15124 sal_usleep(to_usec); 15125 if (!SAL_BOOT_QUICKTURN && !SAL_BOOT_PLISIM && !SAL_BOOT_BCMSIM) { 15126 /* Get Core PLL lock status (bit 0) */ 15127 READ_CMIC_MISC_STATUSr(unit, &val); 15128 if (!(val & 0x1)) { 15129 LOG_WARN(BSL_LS_SOC_COMMON, 15130 (BSL_META_U(unit, 15131 "Core PLL not locked.\n"))); 15132 } 15133 } 15134 } 15135 15136 /* Bring IP2 clock doubler out of reset */ 15137 READ_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, &val); 15138 soc_reg_field_set(unit, CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r, &val, 15139 ARESETf, 0); 15140 WRITE_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, val); 15141 sal_usleep(to_usec); 15142 soc_reg_field_set(unit, CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r, &val, 15143 DRESETf, 0); 15144 WRITE_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2r(unit, val); 15145 sal_usleep(to_usec); 15146 if (!SAL_BOOT_QUICKTURN && !SAL_BOOT_PLISIM && !SAL_BOOT_BCMSIM) { 15147 /* Get DDR PLL lock status (bit 1) */ 15148 READ_CMIC_MISC_STATUSr(unit, &val); 15149 if (!(val & 0x2)) { 15150 LOG_WARN(BSL_LS_SOC_COMMON, 15151 (BSL_META_U(unit, 15152 "IP2 clock doubler not locked.\n"))); 15153 } 15154 } 15155 15156 /* Bring MMU0 clock doubler out of reset */ 15157 READ_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, &val); 15158 soc_reg_field_set(unit, CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r, &val, 15159 ARESETf, 0); 15160 WRITE_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, val); 15161 sal_usleep(to_usec); 15162 soc_reg_field_set(unit, CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r, &val, 15163 DRESETf, 0); 15164 WRITE_CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2r(unit, val); 15165 sal_usleep(to_usec); 15166 if (!SAL_BOOT_QUICKTURN && !SAL_BOOT_PLISIM && !SAL_BOOT_BCMSIM) { 15167 /* Get DDR PLL lock status (bit 2) */ 15168 READ_CMIC_MISC_STATUSr(unit, &val); 15169 if (!(val & 0x4)) { 15170 LOG_WARN(BSL_LS_SOC_COMMON, 15171 (BSL_META_U(unit, 15172 "MMU0 clock doubler not locked.\n"))); 15173 } 15174 } 15175 15176 /* Bring MMU1 clock doubler out of reset */ 15177 READ_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2r(unit, &val); 15178 soc_reg_field_set(unit, CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2r, &val, 15179 ARESETf, 0); 15180 WRITE_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2r(unit, val); 15181 sal_usleep(to_usec); 15182 soc_reg_field_set(unit, CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2r, &val, 15183 DRESETf, 0); 15184 WRITE_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2r(unit, val); 15185 sal_usleep(to_usec); 15186 if (!SAL_BOOT_QUICKTURN && !SAL_BOOT_PLISIM && !SAL_BOOT_BCMSIM) { 15187 /* Get DDR PLL lock status (bit 3) */ 15188 READ_CMIC_MISC_STATUSr(unit, &val); 15189 if (!(val & 0x8)) { 15190 LOG_WARN(BSL_LS_SOC_COMMON, 15191 (BSL_META_U(unit, 15192 "MMU1 clock doubler not locked.\n"))); 15193 } 15194 } 15195 15196 /* bring the blocks out of reset */ 15197 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, XG_PLL2_RST_Lf, 1); 15198 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG_PLL1_RST_Lf, 1); 15199 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XG_PLL0_RST_Lf, 1); 15200 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 15201 sal_usleep(to_usec); 15202 15203 /* 15204 * Min 20 msec delay after LCPLL reset before checking for lock. 15205 */ 15206 if (!soc_feature(unit, soc_feature_ignore_cmic_xgxs_pll_status) && 15207 !SAL_BOOT_PLISIM && !SAL_BOOT_QUICKTURN) { 15208 uint32 val; 15209 15210 READ_CMIC_XGXS0_PLL_STATUSr(unit, &val); 15211 if (!(soc_reg_field_get(unit, CMIC_XGXS0_PLL_STATUSr, 15212 val, CMIC_XGPLL_LOCKf))) { 15213 LOG_ERROR(BSL_LS_SOC_COMMON, 15214 (BSL_META_U(unit, 15215 "LCPLL 0 not locked on unit %d status = 0x%08x\n"), 15216 unit, val)); 15217 } 15218 15219 READ_CMIC_XGXS1_PLL_STATUSr(unit, &val); 15220 if (!(soc_reg_field_get(unit, CMIC_XGXS1_PLL_STATUSr, 15221 val, CMIC_XGPLL_LOCKf))) { 15222 LOG_ERROR(BSL_LS_SOC_COMMON, 15223 (BSL_META_U(unit, 15224 "LCPLL 1 not locked on unit %d status = 0x%08x\n"), 15225 unit, val)); 15226 } 15227 15228 READ_CMIC_XGXS2_PLL_STATUSr(unit, &val); 15229 if (!(soc_reg_field_get(unit, CMIC_XGXS2_PLL_STATUSr, 15230 val, CMIC_XGPLL_LOCKf))) { 15231 LOG_ERROR(BSL_LS_SOC_COMMON, 15232 (BSL_META_U(unit, 15233 "LCPLL 2 not locked on unit %d status = 0x%08x\n"), 15234 unit, val)); 15235 } 15236 } 15237 15238 /* Bring blocks out of reset after 1 msec after PLLs */ 15239 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, QGP_RST_Lf, 1); 15240 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XGP0_RST_Lf, 1); 15241 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XGP1_RST_Lf, 1); 15242 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XGP2_RST_Lf, 1); 15243 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XGP3_RST_Lf, 1); 15244 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 15245 sal_usleep(to_usec); 15246 15247 /* 15248 * NOTE 15249 * The remaining blocks will be brought out of 15250 * reset after Unicore reset. 15251 */ 15252 15253 /* 15254 * Scorpion 15255 * ring0 [00] : IPIPE[1] -> EPIPE[4] 15256 * ring1 [01] : MMU[13] 15257 * ring2 [10] : [14] 15258 * ring3 [11] : gxport[0] -> qgport[2] 15259 * 15260 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15261 * XX10__01XX__XXXX__XXXX__XXXX__XX00__XX11__0011 15262 */ 15263 15264 val = 0x24000033; 15265 WRITE_CMIC_SBUS_RING_MAPr(unit, val); 15266 } 15267 #endif /* BCM_SCORPION_SUPPORT */ 15268 15269 #ifdef BCM_TRIDENT_SUPPORT 15270 /* 15271 * Function: 15272 * soc_reset_bcm56840_a0 15273 * Purpose: 15274 * Special reset sequencing for BCM56840 15275 * Setup SBUS block mapping. 15276 */ 15277 STATIC int 15278 soc_reset_bcm56840_a0(int unit) 15279 { 15280 uint32 rval, to_usec; 15281 uint16 dev_id, drv_dev_id; 15282 uint8 rev_id, drv_rev_id; 15283 soc_reg_t reg; 15284 uint32 addr; 15285 int index; 15286 static const soc_reg_t pll_ctrl1_reg[] = { 15287 CMIC_XGXS0_PLL_CONTROL_1r, CMIC_XGXS1_PLL_CONTROL_1r, 15288 CMIC_XGXS2_PLL_CONTROL_1r, CMIC_XGXS3_PLL_CONTROL_1r 15289 }; 15290 static const soc_reg_t pll_ctrl2_reg[] = { 15291 CMIC_XGXS0_PLL_CONTROL_2r, CMIC_XGXS1_PLL_CONTROL_2r, 15292 CMIC_XGXS2_PLL_CONTROL_2r, CMIC_XGXS3_PLL_CONTROL_2r 15293 }; 15294 static const soc_reg_t pll_ctrl3_reg[] = { 15295 CMIC_XGXS0_PLL_CONTROL_3r, CMIC_XGXS1_PLL_CONTROL_3r, 15296 CMIC_XGXS2_PLL_CONTROL_3r, CMIC_XGXS3_PLL_CONTROL_3r 15297 }; 15298 static const soc_reg_t pll_ctrl4_reg[] = { 15299 CMIC_XGXS0_PLL_CONTROL_4r, CMIC_XGXS1_PLL_CONTROL_4r, 15300 CMIC_XGXS2_PLL_CONTROL_4r, CMIC_XGXS3_PLL_CONTROL_4r 15301 }; 15302 static const soc_reg_t pll_status_reg[] = { 15303 CMIC_XGXS0_PLL_STATUSr, CMIC_XGXS1_PLL_STATUSr, 15304 CMIC_XGXS2_PLL_STATUSr, CMIC_XGXS3_PLL_STATUSr 15305 }; 15306 15307 soc_cm_get_id(unit, &dev_id, &rev_id); 15308 soc_cm_get_id_driver(dev_id, rev_id, &drv_dev_id, &drv_rev_id); 15309 15310 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 15311 (10 * MILLISECOND_USEC); 15312 15313 15314 /* Use 156.25Mhz reference clock for LCPLL */ 15315 if (soc_property_get(unit, spn_XGXS_LCPLL_XTAL_REFCLK, 0)) { 15316 for (index = 0; index < 4; index++) { 15317 reg = pll_ctrl1_reg[index]; 15318 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 15319 soc_pci_getreg(unit, addr, &rval); 15320 soc_reg_field_set(unit, reg, &rval, CH0_MDIVf, 20); 15321 soc_reg_field_set(unit, reg, &rval, CH3_MDIVf, 25); 15322 soc_reg_field_set(unit, reg, &rval, CH4_MDIVf, 125); 15323 soc_reg_field_set(unit, reg, &rval, CH5_MDIVf, 25); 15324 soc_pci_write(unit, addr, rval); 15325 15326 reg = pll_ctrl3_reg[index]; 15327 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 15328 soc_pci_getreg(unit, addr, &rval); 15329 soc_reg_field_set(unit, reg, &rval, NDIV_INTf, 140); 15330 soc_pci_write(unit, addr, rval); 15331 15332 reg = pll_ctrl2_reg[index]; 15333 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 15334 soc_pci_getreg(unit, addr, &rval); 15335 soc_reg_field_set(unit, reg, &rval, KAf, 4); 15336 soc_reg_field_set(unit, reg, &rval, KIf, 1); 15337 soc_reg_field_set(unit, reg, &rval, KPf, 9); 15338 soc_reg_field_set(unit, reg, &rval, PDIVf, 7); 15339 soc_pci_write(unit, addr, rval); 15340 15341 reg = pll_ctrl4_reg[index]; 15342 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 15343 soc_pci_getreg(unit, addr, &rval); 15344 soc_reg_field_set(unit, reg, &rval, CML_BYP_ENf, 1); 15345 soc_reg_field_set(unit, reg, &rval, TESTOUT_ENf, 0); 15346 soc_reg_field_set(unit, reg, &rval, CML_2ED_OUT_ENf, 0); 15347 soc_reg_field_set(unit, reg, &rval, TESTOUT2_ENf, 0); 15348 soc_pci_write(unit, addr, rval); 15349 } 15350 15351 READ_CMIC_MISC_CONTROLr(unit, &rval); 15352 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15353 CMIC_TO_XG_PLL0_SW_OVWRf, 1); 15354 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15355 CMIC_TO_XG_PLL1_SW_OVWRf, 1); 15356 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15357 CMIC_TO_XG_PLL2_SW_OVWRf, 1); 15358 soc_reg_field_set(unit, CMIC_MISC_CONTROLr, &rval, 15359 CMIC_TO_XG_PLL3_SW_OVWRf, 1); 15360 WRITE_CMIC_MISC_CONTROLr(unit, rval); 15361 } 15362 15363 /* Bring LCPLL out of reset */ 15364 READ_CMIC_SOFT_RESET_REGr(unit, &rval); 15365 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_XG_PLL0_RST_Lf, 15366 1); 15367 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_XG_PLL1_RST_Lf, 15368 1); 15369 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_XG_PLL2_RST_Lf, 15370 1); 15371 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_XG_PLL3_RST_Lf, 15372 1); 15373 WRITE_CMIC_SOFT_RESET_REGr(unit, rval); 15374 15375 sal_usleep(to_usec); 15376 15377 /* Wait for LCPLL lock */ 15378 if (!SAL_BOOT_SIMULATION) { 15379 for (index = 0; index < 4; index++) { 15380 reg = pll_status_reg[index]; 15381 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 15382 soc_pci_getreg(unit, addr, &rval); 15383 if (!soc_reg_field_get(unit, reg, rval, CMIC_XGPLL_LOCKf)) { 15384 LOG_ERROR(BSL_LS_SOC_COMMON, 15385 (BSL_META_U(unit, 15386 "LCPLL %d not locked on unit %d " 15387 "status = 0x%08x\n"), index, unit, rval)); 15388 } 15389 } 15390 } 15391 15392 /* De-assert LCPLL's post reset */ 15393 READ_CMIC_SOFT_RESET_REGr(unit, &rval); 15394 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, 15395 CMIC_XG_PLL0_POST_RST_Lf, 1); 15396 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, 15397 CMIC_XG_PLL1_POST_RST_Lf, 1); 15398 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, 15399 CMIC_XG_PLL2_POST_RST_Lf, 1); 15400 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, 15401 CMIC_XG_PLL3_POST_RST_Lf, 1); 15402 WRITE_CMIC_SOFT_RESET_REGr(unit, rval); 15403 15404 sal_usleep(to_usec); 15405 15406 /* 15407 * Bring port blocks out of reset 15408 * PG0: PORT_GROUP5_X, XLPORT0, XLPORT1, XLPORT2, XLPORT3, XLPORT4 15409 * PG1: PORT_GROUP4_X, XLPORT5, XLPORT6, XLPORT7, XLPORT8 15410 * PG2: PORT_GROUP5_Y, XLPORT9, XLPORT10, XLPORT11, XLPORT12, XLPORT13 15411 * PG3: PORT_GROUP4_Y, XLPORT14, XLPORT15, XLPORT16, XLPORT17 15412 */ 15413 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_PG0_RST_Lf, 1); 15414 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_PG1_RST_Lf, 1); 15415 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_PG2_RST_Lf, 1); 15416 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_PG3_RST_Lf, 1); 15417 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, 15418 CMIC_TEMP_MON_PEAK_RST_Lf, 1); 15419 WRITE_CMIC_SOFT_RESET_REGr(unit, rval); 15420 15421 sal_usleep(to_usec); 15422 15423 /* Bring network sync out of reset */ 15424 rval = 0; 15425 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &rval, XQ0_HOTSWAP_RST_Lf, 15426 1); 15427 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &rval, XQ1_HOTSWAP_RST_Lf, 15428 1); 15429 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &rval, XQ2_HOTSWAP_RST_Lf, 15430 1); 15431 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &rval, XQ3_HOTSWAP_RST_Lf, 15432 1); 15433 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &rval, XQ4_HOTSWAP_RST_Lf, 15434 1); 15435 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &rval, XQ5_HOTSWAP_RST_Lf, 15436 1); 15437 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &rval, NS_RST_Lf, 1); 15438 WRITE_CMIC_SOFT_RESET_REG_2r(unit, rval); 15439 15440 sal_usleep(to_usec); 15441 15442 /* 15443 * SBUS ring and block number: 15444 * ring 0: IP(1) 15445 * ring 1: EP(2) 15446 * ring 2: MMU(3) 15447 * ring 3: PORT_GROUP4_X(6), PORT_GROUP5_X(8), XLPORT0(10)...XLPORT8(18), 15448 * LBPORT0(28) 15449 * ring 4: PORT_GROUP4_Y(7), PORT_GROUP5_Y(9), XLPORT9(19)...XLPORT17(27) 15450 * ring 5: OTPC(4) 15451 */ 15452 WRITE_CMIC_SBUS_RING_MAP_0r(unit, 0x43052100); /* block 7 - 0 */ 15453 WRITE_CMIC_SBUS_RING_MAP_1r(unit, 0x33333343); /* block 15 - 8 */ 15454 WRITE_CMIC_SBUS_RING_MAP_2r(unit, 0x44444333); /* block 23 - 16 */ 15455 WRITE_CMIC_SBUS_RING_MAP_3r(unit, 0x00034444); /* block 31 - 24 */ 15456 /* 0x7d0 => 0x13500. There is soc_schan_op operation timed out if less than 0x13500 */ 15457 WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x13500); 15458 15459 /* Bring IP, EP, and MMU blocks out of reset */ 15460 READ_CMIC_SOFT_RESET_REGr(unit, &rval); 15461 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_EP_RST_Lf, 1); 15462 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_IP_RST_Lf, 1); 15463 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, CMIC_MMU_RST_Lf, 1); 15464 WRITE_CMIC_SOFT_RESET_REGr(unit, rval); 15465 15466 sal_usleep(to_usec); 15467 15468 READ_CMIC_THERMAL_MON_CTRLr(unit, &rval); 15469 soc_reg_field_set(unit, CMIC_THERMAL_MON_CTRLr, &rval, BG_ADJf, 1); 15470 soc_reg_field_set(unit, CMIC_THERMAL_MON_CTRLr, &rval, VTMON_RSTBf, 1); 15471 WRITE_CMIC_THERMAL_MON_CTRLr(unit, rval); 15472 15473 sal_usleep(1000); 15474 15475 READ_CMIC_SOFT_RESET_REGr(unit, &rval); 15476 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, 15477 CMIC_TEMP_MON_PEAK_RST_Lf, 0); 15478 WRITE_CMIC_SOFT_RESET_REGr(unit, rval); 15479 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, 15480 CMIC_TEMP_MON_PEAK_RST_Lf, 1); 15481 WRITE_CMIC_SOFT_RESET_REGr(unit, rval); 15482 15483 if (!(drv_rev_id == BCM56840_A0_REV_ID && rev_id < BCM56840_B0_REV_ID)) { 15484 READ_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3r(unit, &rval); 15485 soc_reg_field_set(unit, CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3r, &rval, 15486 PVTMON_RESET_Nf, 1); 15487 WRITE_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3r(unit, rval); 15488 } 15489 15490 if (dev_id == BCM56846_DEVICE_ID || dev_id == BCM56844_DEVICE_ID || 15491 dev_id == BCM56842_DEVICE_ID || dev_id == BCM56746_DEVICE_ID || 15492 dev_id == BCM56744_DEVICE_ID || dev_id == BCM56549_DEVICE_ID || 15493 dev_id == BCM56053_DEVICE_ID || dev_id == BCM56838_DEVICE_ID || 15494 dev_id == BCM56831_DEVICE_ID || dev_id == BCM56835_DEVICE_ID || 15495 dev_id == BCM56847_DEVICE_ID || dev_id == BCM56849_DEVICE_ID || 15496 dev_id == BCM56742_DEVICE_ID) { 15497 15498 rval = 0; 15499 soc_reg_field_set(unit, ING_CONFIG_2r, &rval, 15500 USE_VLAN_ING_PORT_BITMAPf, 1); 15501 soc_reg_field_set(unit, ING_CONFIG_2r, &rval, FCOE_IFP_KEY_MODEf, 1); 15502 soc_reg_field_set(unit, ING_CONFIG_2r, &rval, 15503 PROTOCOL_PKT_INDEX_PRECEDENCE_MODEf, 1); 15504 soc_reg_field_set(unit, ING_CONFIG_2r, &rval, WESP_DRAFT_11f, 1); 15505 soc_reg_field_set(unit, ING_CONFIG_2r, &rval, ECMP_HASH_16BITSf, 1); 15506 soc_reg_field_set(unit, ING_CONFIG_2r, &rval, 15507 TRILL_TRANSIT_MTU_CHECK_ENHANCEDf, 1); 15508 soc_reg_field_set(unit, ING_CONFIG_2r, &rval, L2_IS_IS_PARSE_MODEf, 1); 15509 soc_reg_field_set(unit, ING_CONFIG_2r, &rval, 15510 DISABLE_INVALID_RBRIDGE_NICKNAMESf, 1); 15511 soc_reg_field_set(unit, ING_CONFIG_2r, &rval, 15512 TRILL_ALL_ESADI_PARSE_MODEf, 1); 15513 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_2r(unit, rval)); 15514 15515 rval = 0; 15516 soc_reg_field_set(unit, EGR_CONFIG_2r, &rval, DO_NOT_MOD_TPIDf, 1); 15517 soc_reg_field_set(unit, EGR_CONFIG_2r, &rval, 15518 QCN_CNM_MESSAGE_DRAFT_24f, 1); 15519 soc_reg_field_set(unit, EGR_CONFIG_2r, &rval, 15520 USE_RBRIDGES_NICKNAMES_TABLEf, 1); 15521 soc_reg_field_set(unit, EGR_CONFIG_2r, &rval, WESP_DRAFT_11f, 1); 15522 soc_reg_field_set(unit, EGR_CONFIG_2r, &rval, 15523 TRILL_L2_IS_IS_PARSE_MODEf, 1); 15524 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIG_2r(unit, rval)); 15525 15526 rval = 0; 15527 soc_reg_field_set(unit, ING_Q_BEGINr, &rval, SW_ENC_DEC_TCAM_KEY_MASKf, 15528 1); 15529 soc_reg_field_set(unit, ING_Q_BEGINr, &rval, SUPPORT_8K_VPf, 1); 15530 soc_reg_field_set(unit, ING_Q_BEGINr, &rval, DISABLE_CELL_COMPRESSIONf, 15531 1); 15532 SOC_IF_ERROR_RETURN(WRITE_ING_Q_BEGINr(unit, rval)); 15533 15534 rval = 0; 15535 soc_reg_field_set(unit, EGR_Q_BEGINr, &rval, SW_ENC_DEC_TCAM_KEY_MASKf, 15536 1); 15537 SOC_IF_ERROR_RETURN(WRITE_EGR_Q_BEGINr(unit, rval)); 15538 } 15539 return SOC_E_NONE; 15540 } 15541 #endif /* BCM_TRIDENT_SUPPORT */ 15542 15543 #if defined(BCM_KATANA2_SUPPORT) || defined(BCM_HELIX4_SUPPORT) 15544 /* 15545 * Function: 15546 * soc_amac_init 15547 * Purpose: 15548 * Bring iproc amac out of reset. 15549 * Common function for Helix4 and Katana2 devices 15550 */ 15551 STATIC int 15552 soc_amac_init(int unit) 15553 { 15554 uint32 rval = 0; 15555 uint32 reg_index = 0; 15556 soc_reg_t amac_idm_reg[2]={ AMAC_IDM0_IDM_RESET_CONTROLr, 15557 AMAC_IDM1_IDM_RESET_CONTROLr }; 15558 soc_reg_t gmac_serdes_reg[2]={ GMAC0_SERDESCONTROLr, 15559 GMAC1_SERDESCONTROLr }; 15560 15561 for (reg_index = 0; reg_index < COUNTOF(amac_idm_reg); reg_index++) { 15562 SOC_IF_ERROR_RETURN(soc_iproc_getreg(unit, 15563 soc_reg_addr(unit, amac_idm_reg[reg_index], 15564 REG_PORT_ANY, 0), &rval)); 15565 if (soc_reg_field_get(unit, amac_idm_reg[reg_index], 15566 rval, RESETf) != 0) { 15567 soc_reg_field_set(unit, AMAC_IDM0_IDM_RESET_CONTROLr, 15568 &rval, RESETf, 0); 15569 } 15570 SOC_IF_ERROR_RETURN(soc_iproc_setreg(unit, 15571 soc_reg_addr(unit, amac_idm_reg[reg_index], 15572 REG_PORT_ANY, 0), rval)); 15573 15574 SOC_IF_ERROR_RETURN(soc_iproc_getreg(unit, soc_reg_addr(unit, 15575 gmac_serdes_reg[reg_index], 15576 REG_PORT_ANY, 0), &rval)); 15577 if (soc_reg_field_get(unit, gmac_serdes_reg[reg_index], 15578 rval, REF_TERM_SELf) == 0) { 15579 soc_reg_field_set(unit, gmac_serdes_reg[reg_index], 15580 &rval, REF_TERM_SELf, 1); 15581 } 15582 #ifdef BCM_HELIX4_SUPPORT 15583 if (soc_reg_field_get(unit, gmac_serdes_reg[reg_index], 15584 rval, REFSELf) == 0) { 15585 if (SOC_IS_HELIX4(unit)) { 15586 soc_reg_field_set(unit, GMAC0_SERDESCONTROLr, 15587 &rval, REFSELf, 1); 15588 } 15589 15590 } 15591 #endif 15592 SOC_IF_ERROR_RETURN(soc_iproc_setreg(unit, soc_reg_addr(unit, 15593 gmac_serdes_reg[reg_index], 15594 REG_PORT_ANY, 0), rval)); 15595 } 15596 return SOC_E_NONE; 15597 } 15598 #endif 15599 15600 #ifdef BCM_HELIX4_SUPPORT 15601 15602 /* 15603 * Function: 15604 * soc_reset_bcm56340_a0 15605 * Purpose: 15606 * Special reset sequencing for BCM56340 15607 * Setup SBUS block mapping. 15608 */ 15609 STATIC int 15610 soc_reset_bcm56340_a0(int unit) 15611 { 15612 int rv, val, index; 15613 uint32 rval, to_usec; 15614 soc_persist_t *sop = SOC_PERSIST(unit); 15615 uint16 dev_id; 15616 uint8 rev_id; 15617 static const soc_reg_t pll_ctrl0_reg[] = { 15618 TOP_XG_PLL0_CTRL_0r, TOP_XG_PLL1_CTRL_0r, 15619 TOP_XG_PLL2_CTRL_0r, TOP_XG_PLL3_CTRL_0r 15620 }; 15621 static const soc_reg_t pll_ctrl4_reg[] = { 15622 TOP_XG_PLL0_CTRL_4r, TOP_XG_PLL1_CTRL_4r 15623 }; 15624 15625 uint16 soc_dev; 15626 uint8 soc_rev; 15627 unsigned ts_ref_freq; 15628 unsigned ts_idx; 15629 static const soc_pll_param_t ts_pll[] = { /* values for 500MHz TSPLL output */ 15630 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 15631 {12800000, 312, 0x80000, 1, 8, 1, 2, 7, 1}, 15632 {20000000, 200, 0, 1, 8, 2, 3, 8, 1}, 15633 {25000000, 160, 0, 1, 8, 2, 4, 9, 1}, 15634 {32000000, 125, 0, 1, 8, 2, 4, 9, 1}, 15635 {50000000, 80, 0, 1, 8, 3, 4, 10, 1}, 15636 { 0, 160, 0, 1, 8, 2, 4, 9, 1} /* 25MHz, from internal reference */ 15637 }; 15638 unsigned bs_ref_freq; 15639 unsigned bs_idx; 15640 static const soc_pll_param_t bs_pll[] = { /* values for 20MHz BSPLL output */ 15641 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 15642 {12800000, 250, 0, 1, 160, 1, 2, 7, 0}, 15643 {20000000, 175, 0, 1, 175, 2, 3, 8, 0}, 15644 {25000000, 140, 0, 1, 175, 2, 4, 9, 0}, 15645 {32000000, 108, 0xc0000000, 1, 174, 2, 4, 9, 0}, /* Ndiv=108.75 */ 15646 {50000000, 70, 0, 1, 175, 3, 4, 10, 0}, 15647 { 0, 140, 0, 1, 175, 2, 4, 9, 0} /* 25MHz, from internal reference */ 15648 }; 15649 15650 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 15651 (100 * MILLISECOND_USEC); 15652 15653 /* 15654 * SBUS ring and block number: 15655 * ring 0: IP(1) 15656 * ring 1: EP(2) 15657 * ring 2: MMU(3) 15658 * ring 3: ISM(16) 15659 * ring 4: SER(17) 15660 * ring 5: AXP(4) 15661 * ring 6: XTP0(8)..XTP3(11), XLP0(12), IBOD(18), 15662 XWP0(13).., XWP2(15) 15663 * ring 7: OTPC(5), TOP_REGS(6) 15664 */ 15665 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x07752100); /* block 7 - 0 */ 15666 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x66666666); /* block 15 - 8 */ 15667 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x00000643); /* block 23 - 16 */ 15668 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x00000000); /* block 31 - 24 */ 15669 15670 15671 /* Reconfig XMAC cclk - necessary for Helix4 XL port XMAC FIFO UR */ 15672 soc_cm_get_id(unit, &soc_dev, &soc_rev); 15673 if ( (BCM56340_DEVICE_ID == soc_dev) || (BCM56041_DEVICE_ID == soc_dev) || 15674 (BCM56042_DEVICE_ID == soc_dev) || (BCM56345_DEVICE_ID == soc_dev)) { 15675 if (SOC_E_NONE != (rv = _soc_hx4_xmac_cclk_config(unit))) { 15676 LOG_ERROR(BSL_LS_SOC_COMMON, 15677 (BSL_META_U(unit, 15678 "Helix4 XMAC cclk config failed !!\n"))); 15679 return rv; 15680 } 15681 } 15682 15683 if (soc_property_get(unit, spn_XGXS_LCPLL_XTAL_REFCLK, 1)) { 15684 rval = 0x14; /* 156.25Mhz */ 15685 } else { 15686 rval = 0x7d; /* 25Mhz */ 15687 } 15688 for (index = 0; index < 2; index++) { 15689 rv = soc_reg_field32_modify(unit, pll_ctrl4_reg[index], 15690 REG_PORT_ANY, NDIV_INTf, rval); 15691 if (rv < 0) { 15692 LOG_ERROR(BSL_LS_SOC_COMMON, 15693 (BSL_META_U(unit, 15694 "Modifying TOP_XG_PLL%d_CTRL_4 failed !!\n"), 15695 index)); 15696 return rv; 15697 } 15698 } 15699 15700 if (soc_property_get(unit, spn_XGXS_QGPLL_XTAL_REFCLK, 1)) { 15701 rval = 0x14; /* 156.25Mhz */ 15702 } else { 15703 rval = 0x7d; /* 25Mhz */ 15704 } 15705 rv = soc_reg_field32_modify(unit, pll_ctrl4_reg[0], 15706 REG_PORT_ANY, NDIV_INTf, rval); 15707 if (rv < 0) { 15708 LOG_ERROR(BSL_LS_SOC_COMMON, 15709 (BSL_META_U(unit, 15710 "Modifying TOP_XG_PLL0_CTRL_4:QG_PLL failed !!\n"))); 15711 return rv; 15712 } 15713 15714 if (soc_property_get(unit, spn_XGXS_WCPLL_XTAL_REFCLK, 1)) { 15715 rval = 0x14; /* 156.25Mhz */ 15716 } else { 15717 rval = 0x7d; /* 25Mhz */ 15718 } 15719 rv = soc_reg_field32_modify(unit, pll_ctrl4_reg[1], 15720 REG_PORT_ANY, NDIV_INTf, rval); 15721 if (rv < 0) { 15722 LOG_ERROR(BSL_LS_SOC_COMMON, 15723 (BSL_META_U(unit, 15724 "Modifying TOP_XG_PLL1_CTRL_4:WC_PLL failed !!\n"))); 15725 return rv; 15726 } 15727 15728 for (index = 0; index < 4; index++) { 15729 rv = soc_reg_field32_modify(unit, pll_ctrl0_reg[index], 15730 REG_PORT_ANY, CH3_MDIVf, 25); 15731 if (rv < 0) { 15732 LOG_ERROR(BSL_LS_SOC_COMMON, 15733 (BSL_META_U(unit, 15734 "Modifying TOP_XG_PLL%d_CTRL_0 failed !!\n"), 15735 index)); 15736 return rv; 15737 } 15738 } 15739 15740 rv = READ_TOP_MISC_CONTROL_1r(unit, &rval); 15741 if (rv < 0) { 15742 LOG_ERROR(BSL_LS_SOC_COMMON, 15743 (BSL_META_U(unit, 15744 "Reading TOP_MISC_CONTROL_1 failed !!\n"))); 15745 return rv; 15746 } 15747 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, 15748 CMIC_TO_XG_PLL0_SW_OVWRf, 1); 15749 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, 15750 CMIC_TO_XG_PLL1_SW_OVWRf, 1); 15751 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, 15752 CMIC_TO_XG_PLL2_SW_OVWRf, 1); 15753 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, 15754 CMIC_TO_XG_PLL3_SW_OVWRf, 1); 15755 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, 15756 IO_HYS_EN_CTRLf, 1); 15757 rv = WRITE_TOP_MISC_CONTROL_1r(unit, rval); 15758 if (rv < 0) { 15759 LOG_ERROR(BSL_LS_SOC_COMMON, 15760 (BSL_META_U(unit, 15761 "Writing TOP_MISC_CONTROL_1 failed !!\n"))); 15762 return rv; 15763 } 15764 15765 /* Bring LCPLL out of reset */ 15766 rv = READ_TOP_SOFT_RESET_REG_2r(unit, &rval); 15767 if (rv < 0) { 15768 LOG_ERROR(BSL_LS_SOC_COMMON, 15769 (BSL_META_U(unit, 15770 "Reading TOP_SOFT_RESET_REG_2 failed !!\n"))); 15771 return rv; 15772 } 15773 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG_PLL0_RST_Lf, 1); 15774 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG_PLL1_RST_Lf, 1); 15775 rv = WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 15776 if (rv < 0) { 15777 LOG_ERROR(BSL_LS_SOC_COMMON, 15778 (BSL_META_U(unit, 15779 "Writing TOP_SOFT_RESET_REG_2 failed !!\n"))); 15780 return rv; 15781 } 15782 sal_usleep(to_usec); 15783 15784 /* Wait for LCPLL lock */ 15785 if (!SAL_BOOT_SIMULATION) { 15786 rv = READ_TOP_XG_PLL0_STATUSr(unit, &rval); 15787 if (rv < 0) { 15788 LOG_ERROR(BSL_LS_SOC_COMMON, 15789 (BSL_META_U(unit, 15790 "Reading TOP_XG_PLL0_STATUS failed !!\n"))); 15791 return rv; 15792 } 15793 if (!soc_reg_field_get(unit, TOP_XG_PLL0_STATUSr, rval, TOP_XGPLL_LOCKf)) { 15794 LOG_ERROR(BSL_LS_SOC_COMMON, 15795 (BSL_META_U(unit, 15796 "LCPLL 0 not locked on unit %d " 15797 "status = 0x%08x\n"), unit, rval)); 15798 } 15799 rv = READ_TOP_XG_PLL1_STATUSr(unit, &rval); 15800 if (rv < 0) { 15801 LOG_ERROR(BSL_LS_SOC_COMMON, 15802 (BSL_META_U(unit, 15803 "Reading TOP_XG_PLL1_STATUS failed !!\n"))); 15804 return rv; 15805 } 15806 if (!soc_reg_field_get(unit, TOP_XG_PLL1_STATUSr, rval, TOP_XGPLL_LOCKf)) { 15807 LOG_ERROR(BSL_LS_SOC_COMMON, 15808 (BSL_META_U(unit, 15809 "LCPLL 1 not locked on unit %d " 15810 "status = 0x%08x\n"), unit, rval)); 15811 } 15812 } 15813 15814 /* De-assert LCPLL's post reset */ 15815 rv = READ_TOP_SOFT_RESET_REG_2r(unit, &rval); 15816 if (rv < 0) { 15817 LOG_ERROR(BSL_LS_SOC_COMMON, 15818 (BSL_META_U(unit, 15819 "Reading TOP_SOFT_RESET_REG_2 failed !!\n"))); 15820 return rv; 15821 } 15822 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG_PLL0_POST_RST_Lf, 1); 15823 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG_PLL1_POST_RST_Lf, 1); 15824 rv = WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 15825 if (rv < 0) { 15826 LOG_ERROR(BSL_LS_SOC_COMMON, 15827 (BSL_META_U(unit, 15828 "Writing TOP_SOFT_RESET_REG_2 failed !!\n"))); 15829 return rv; 15830 } 15831 sal_usleep(to_usec); 15832 15833 15834 /* Configure TS PLL. Default of 0 is internal reference */ 15835 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); 15836 15837 for (ts_idx = 0; ts_idx < sizeof(ts_pll)/sizeof(ts_pll[0]); ++ts_idx) { 15838 if (ts_pll[ts_idx].ref_freq == ts_ref_freq) { 15839 break; 15840 } 15841 } 15842 15843 if (ts_idx == sizeof(ts_pll)/sizeof(ts_pll[0])) { 15844 LOG_ERROR(BSL_LS_SOC_COMMON, 15845 (BSL_META_U(unit, 15846 "Invalid value for PTP_TS_PLL_REF (%u)." 15847 "No default PLL params.\n"), ts_ref_freq)); 15848 } else { 15849 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_2r(unit,&rval)); 15850 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, PDIVf, 15851 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, 15852 ts_pll[ts_idx].pdiv)); 15853 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, CH0_MDIVf, 15854 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, 15855 ts_pll[ts_idx].mdiv)); 15856 WRITE_TOP_TS_PLL_CTRL_2r(unit, rval); 15857 15858 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_3r(unit,&rval)); 15859 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_INTf, 15860 soc_property_get(unit, spn_PTP_TS_PLL_N, 15861 ts_pll[ts_idx].ndiv_int)); 15862 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_FRACf, 15863 ts_pll[ts_idx].ndiv_frac); 15864 WRITE_TOP_TS_PLL_CTRL_3r(unit, rval); 15865 15866 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_4r(unit,&rval)); 15867 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KAf, 15868 soc_property_get(unit, spn_PTP_TS_KA, 15869 ts_pll[ts_idx].ka)); 15870 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KIf, 15871 soc_property_get(unit, spn_PTP_TS_KI, 15872 ts_pll[ts_idx].ki)); 15873 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KPf, 15874 soc_property_get(unit, spn_PTP_TS_KP, 15875 ts_pll[ts_idx].kp)); 15876 15877 /* SOC property == 0 => use internal reference of 25MHz */ 15878 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, REFCLK_SELf, 15879 (ts_ref_freq != 0)); 15880 WRITE_TOP_TS_PLL_CTRL_4r(unit, rval); 15881 15882 /* Strobe channel-0 load-enable to set divisors. */ 15883 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_2r(unit,&rval)); 15884 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, LOAD_EN_CH0f, 0); 15885 WRITE_TOP_TS_PLL_CTRL_2r(unit, rval); 15886 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, LOAD_EN_CH0f, 1); 15887 WRITE_TOP_TS_PLL_CTRL_2r(unit, rval); 15888 } 15889 15890 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 15891 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_RST_Lf, 1); 15892 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 15893 15894 /* Check for TSPLL lock */ 15895 if (!SAL_BOOT_SIMULATION) { 15896 sal_usleep(to_usec); 15897 15898 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_STATUSr(unit, &rval)); 15899 if (!soc_reg_field_get(unit, TOP_TS_PLL_STATUSr, rval, PLL_LOCKf)) { 15900 LOG_ERROR(BSL_LS_SOC_COMMON, 15901 (BSL_META_U(unit, 15902 "TimeSync PLL not locked on unit %d " 15903 "status = 0x%08x\n"), unit, rval)); 15904 } 15905 } 15906 15907 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 15908 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_POST_RST_Lf, 1); 15909 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 15910 15911 /* Set 250Mhz (implies 4ns resolution) default timesync clock to 15912 calculate assymetric delays */ 15913 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); /* clock period in nanoseconds */ 15914 15915 /* as a signal to upper-level code that the BroadSync is newly initialized 15916 * disable BroadSync0/1 bitclock output. Checked in time.c / 1588 firmware */ 15917 /* coverity[result_independent_of_operands] */ 15918 SOC_IF_ERROR_RETURN(READ_CMIC_BS0_CONFIGr(unit, &rval)); 15919 soc_reg_field_set(unit, CMIC_BS0_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 15920 WRITE_CMIC_BS0_CONFIGr(unit, rval); 15921 15922 /* coverity[result_independent_of_operands] */ 15923 SOC_IF_ERROR_RETURN(READ_CMIC_BS1_CONFIGr(unit, &rval)); 15924 soc_reg_field_set(unit, CMIC_BS1_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 15925 WRITE_CMIC_BS1_CONFIGr(unit, rval); 15926 15927 /* BSPLL0 has not been configured, so reset/configure both BSPLL0 and BSPLL1 */ 15928 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 15929 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_RST_Lf, 0); 15930 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_RST_Lf, 0); 15931 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_POST_RST_Lf, 0); 15932 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_POST_RST_Lf, 0); 15933 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 15934 15935 /* Both BSPLLs configured the same, for 20MHz output by default */ 15936 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 0); /* 0->internal reference */ 15937 /* Set BS_PLL_CLK_IN_SEL based on reference frequency. If it is 0, use the internal reference */ 15938 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_4r(unit,&rval)); 15939 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_4r, &rval, REFCLK_SELf, 15940 (bs_ref_freq != 0)); 15941 WRITE_TOP_BS_PLL0_CTRL_4r(unit, rval); 15942 15943 for (bs_idx = 0; bs_idx < sizeof(bs_pll)/sizeof(bs_pll[0]); ++bs_idx) { 15944 if (bs_pll[bs_idx].ref_freq == bs_ref_freq) { 15945 break; 15946 } 15947 } 15948 if (bs_idx == sizeof(bs_pll)/sizeof(bs_pll[0])) { 15949 LOG_ERROR(BSL_LS_SOC_COMMON, 15950 (BSL_META_U(unit, 15951 "Invalid value for PTP_BS_REF (%u)." 15952 "No default PLL params.\n"), bs_ref_freq)); 15953 } else { 15954 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_0r(unit,&rval)); 15955 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_0r, &rval, VCO_DIV2f, 15956 soc_property_get(unit, spn_PTP_BS_VCO_DIV2, 15957 bs_pll[bs_idx].vco_div2)); 15958 WRITE_TOP_BS_PLL0_CTRL_0r(unit, rval); 15959 15960 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_0r(unit,&rval)); 15961 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_0r, &rval, VCO_DIV2f, 15962 soc_property_get(unit, spn_PTP_BS_VCO_DIV2, 15963 bs_pll[bs_idx].vco_div2)); 15964 WRITE_TOP_BS_PLL1_CTRL_0r(unit, rval); 15965 15966 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_4r(unit,&rval)); 15967 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_4r, &rval, KAf, 15968 soc_property_get(unit, spn_PTP_BS_KA, 15969 bs_pll[bs_idx].ka)); 15970 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_4r, &rval, KIf, 15971 soc_property_get(unit, spn_PTP_BS_KI, 15972 bs_pll[bs_idx].ki)); 15973 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_4r, &rval, KPf, 15974 soc_property_get(unit, spn_PTP_BS_KP, 15975 bs_pll[bs_idx].kp)); 15976 WRITE_TOP_BS_PLL0_CTRL_4r(unit, rval); 15977 15978 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_4r(unit,&rval)); 15979 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_4r, &rval, KAf, 15980 soc_property_get(unit, spn_PTP_BS_KA, 15981 bs_pll[bs_idx].ka)); 15982 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_4r, &rval, KIf, 15983 soc_property_get(unit, spn_PTP_BS_KI, 15984 bs_pll[bs_idx].ki)); 15985 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_4r, &rval, KPf, 15986 soc_property_get(unit, spn_PTP_BS_KP, 15987 bs_pll[bs_idx].kp)); 15988 WRITE_TOP_BS_PLL1_CTRL_4r(unit, rval); 15989 15990 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_3r(unit,&rval)); 15991 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_3r, &rval, NDIV_INTf, 15992 soc_property_get(unit, spn_PTP_BS_NDIV_INT, 15993 bs_pll[bs_idx].ndiv_int)); 15994 WRITE_TOP_BS_PLL0_CTRL_3r(unit, rval); 15995 15996 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_3r(unit,&rval)); 15997 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_3r, &rval, NDIV_INTf, 15998 soc_property_get(unit, spn_PTP_BS_NDIV_INT, 15999 bs_pll[bs_idx].ndiv_int)); 16000 WRITE_TOP_BS_PLL1_CTRL_3r(unit, rval); 16001 16002 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_2r(unit,&rval)); 16003 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_2r, &rval, CH0_MDIVf, 16004 soc_property_get(unit, spn_PTP_BS_MNDIV, 16005 bs_pll[bs_idx].mdiv)); 16006 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_2r, &rval, PDIVf, 16007 soc_property_get(unit, spn_PTP_BS_PDIV, 16008 bs_pll[bs_idx].pdiv)); 16009 WRITE_TOP_BS_PLL0_CTRL_2r(unit, rval); 16010 16011 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_2r(unit,&rval)); 16012 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_2r, &rval, CH0_MDIVf, 16013 soc_property_get(unit, spn_PTP_BS_MNDIV, 16014 bs_pll[bs_idx].mdiv)); 16015 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_2r, &rval, PDIVf, 16016 soc_property_get(unit, spn_PTP_BS_PDIV, 16017 bs_pll[bs_idx].pdiv)); 16018 WRITE_TOP_BS_PLL1_CTRL_2r(unit, rval); 16019 16020 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_CTRL_2r(unit,&rval)); 16021 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_2r, &rval, LOAD_EN_CH0f, 0); 16022 WRITE_TOP_BS_PLL0_CTRL_2r(unit, rval); 16023 soc_reg_field_set(unit, TOP_BS_PLL0_CTRL_2r, &rval, LOAD_EN_CH0f, 1); 16024 WRITE_TOP_BS_PLL0_CTRL_2r(unit, rval); 16025 16026 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_CTRL_2r(unit,&rval)); 16027 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_2r, &rval, LOAD_EN_CH0f, 0); 16028 WRITE_TOP_BS_PLL1_CTRL_2r(unit, rval); 16029 soc_reg_field_set(unit, TOP_BS_PLL1_CTRL_2r, &rval, LOAD_EN_CH0f, 1); 16030 WRITE_TOP_BS_PLL1_CTRL_2r(unit, rval); 16031 } 16032 16033 /* Take BroadSync out of reset */ 16034 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 16035 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_RST_Lf, 1); 16036 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_RST_Lf, 1); 16037 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 16038 16039 /* Check for BSPLL lock */ 16040 if (!SAL_BOOT_SIMULATION) { 16041 sal_usleep(to_usec); 16042 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL0_STATUSr(unit, &rval)); 16043 if (!soc_reg_field_get(unit, TOP_BS_PLL0_STATUSr, rval, PLL_LOCKf)) { 16044 LOG_ERROR(BSL_LS_SOC_COMMON, 16045 (BSL_META_U(unit, 16046 "BroadSync0 PLL not locked on unit %d " 16047 "status = 0x%08x\n"), unit, rval)); 16048 } 16049 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL1_STATUSr(unit, &rval)); 16050 if (!soc_reg_field_get(unit, TOP_BS_PLL1_STATUSr, rval, PLL_LOCKf)) { 16051 LOG_ERROR(BSL_LS_SOC_COMMON, 16052 (BSL_META_U(unit, 16053 "BroadSync1 PLL not locked on unit %d " 16054 "status = 0x%08x\n"), unit, rval)); 16055 } 16056 } 16057 16058 /* Deassert Post-Reset */ 16059 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 16060 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_POST_RST_Lf, 1); 16061 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_POST_RST_Lf, 1); 16062 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 16063 16064 soc_cm_get_id(unit, &dev_id, &rev_id); 16065 val = soc_property_get(unit, "iproc_shutdown", 0); 16066 if (val) { 16067 uint32 cpu_mask = 0x1; 16068 /* Spiral SKUs have a single core, all other SKUs have dual cores */ 16069 if (!(dev_id == BCM56047_DEVICE_ID || dev_id == BCM56048_DEVICE_ID || 16070 dev_id == BCM56049_DEVICE_ID)) { 16071 cpu_mask |= 0x2; 16072 } 16073 rv = soc_iproc_shutdown(unit, cpu_mask, val-1); 16074 if (SOC_FAILURE(rv)) { 16075 LOG_ERROR(BSL_LS_SOC_COMMON, 16076 (BSL_META_U(unit, 16077 "Putting iproc in shutdown failed !!\n"))); 16078 } 16079 } 16080 16081 /* Check for M, A and Plain versions */ 16082 SOC_IF_ERROR_RETURN(READ_TOP_SWITCH_FEATURE_ENABLEr(unit, &rval)); 16083 if (rval & 0x1) { 16084 /* BOND_1588_ENABLE */ 16085 SOC_FEATURE_SET(unit, soc_feature_timesync_support); 16086 } 16087 if (!(rval & 0x8)) { 16088 /* BOND_MPLS_ENABLE */ 16089 SOC_FEATURE_CLEAR(unit, soc_feature_mpls); 16090 SOC_FEATURE_CLEAR(unit, soc_feature_bhh); 16091 } 16092 if (!(rval & 0x10)) { 16093 /* BOND_IP_ENABLE */ 16094 SOC_FEATURE_CLEAR(unit, soc_feature_lpm_tcam); 16095 SOC_FEATURE_CLEAR(unit, soc_feature_ip_mcast); 16096 SOC_FEATURE_CLEAR(unit, soc_feature_ip_mcast_repl); 16097 SOC_FEATURE_CLEAR(unit, soc_feature_l3); 16098 SOC_FEATURE_CLEAR(unit, soc_feature_l3_ip6); 16099 SOC_FEATURE_CLEAR(unit, soc_feature_l3_lookup_cmd); 16100 SOC_FEATURE_CLEAR(unit, soc_feature_l3_sgv); 16101 /* Following features depend on IP feature */ 16102 SOC_FEATURE_CLEAR(unit, soc_feature_subport); 16103 SOC_FEATURE_CLEAR(unit, soc_feature_subport_enhanced); 16104 SOC_FEATURE_CLEAR(unit, soc_feature_trill); 16105 SOC_FEATURE_CLEAR(unit, soc_feature_l2gre); 16106 } 16107 /* Adjust memory sizes for the A variants - addendum to soc_hx4_mem_config */ 16108 if (!(rval & 0x10)) { 16109 /* BOND_IP_ENABLE */ 16110 switch (dev_id) { 16111 case BCM56346_DEVICE_ID: 16112 case BCM56345_DEVICE_ID: 16113 case BCM56344_DEVICE_ID: 16114 case BCM56342_DEVICE_ID: 16115 case BCM56340_DEVICE_ID: 16116 sop->memState[MPLS_ENTRYm].index_max = -1; 16117 sop->memState[MPLS_ENTRY_1m].index_max = -1; 16118 sop->memState[MPLS_ENTRY_EXTDm].index_max = -1; 16119 sop->memState[L3_ENTRY_1m].index_max = -1; 16120 sop->memState[L3_ENTRY_2m].index_max = -1; 16121 sop->memState[L3_ENTRY_4m].index_max = -1; 16122 sop->memState[EGR_IPMCm].index_max = -1; 16123 sop->memState[EGR_L3_NEXT_HOPm].index_max = -1; 16124 sop->memState[ING_L3_NEXT_HOPm].index_max = -1; 16125 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = -1; 16126 sop->memState[INITIAL_PROT_NHI_TABLEm].index_max = -1; 16127 sop->memState[L3_IPMCm].index_max = 1023; 16128 sop->memState[L3_IPMC_1m].index_max = 1023; 16129 sop->memState[L3_IPMC_REMAPm].index_max = 1023; 16130 sop->memState[MMU_REPL_GROUPm].index_max = 1023; 16131 sop->memState[VRFm].index_max = 127; 16132 sop->memState[L3_DEFIPm].index_max = -1; 16133 sop->memState[L3_DEFIP_ONLYm].index_max = -1; 16134 sop->memState[L3_DEFIP_PAIR_128m].index_max = -1; 16135 break; 16136 default: 16137 break; 16138 } 16139 } 16140 16141 /* 16142 * Bring port blocks out of reset 16143 */ 16144 rv = READ_TOP_SOFT_RESET_REGr(unit, &rval); 16145 if (rv < 0) { 16146 LOG_ERROR(BSL_LS_SOC_COMMON, 16147 (BSL_META_U(unit, 16148 "Reading TOP_SOFT_RESET_REG failed !!\n"))); 16149 return rv; 16150 } 16151 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XTP0_RST_Lf, 1); 16152 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XTP1_RST_Lf, 1); 16153 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XTP2_RST_Lf, 1); 16154 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XTP3_RST_Lf, 1); 16155 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP0_RST_Lf, 1); 16156 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XWP0_RST_Lf, 1); 16157 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XWP1_RST_Lf, 1); 16158 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XWP2_RST_Lf, 1); 16159 16160 rv = WRITE_TOP_SOFT_RESET_REGr(unit, rval); 16161 if (rv < 0) { 16162 LOG_ERROR(BSL_LS_SOC_COMMON, 16163 (BSL_META_U(unit, 16164 "Writing TOP_SOFT_RESET_REG failed !!\n"))); 16165 return rv; 16166 } 16167 16168 sal_usleep(to_usec); 16169 16170 /* Bring network sync out of reset */ 16171 rv = READ_TOP_SOFT_RESET_REGr(unit, &rval); 16172 if (rv < 0) { 16173 LOG_ERROR(BSL_LS_SOC_COMMON, 16174 (BSL_META_U(unit, 16175 "Reading TOP_SOFT_RESET_REG failed !!\n"))); 16176 return rv; 16177 } 16178 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_NS_RST_Lf, 1); 16179 rv = WRITE_TOP_SOFT_RESET_REGr(unit, rval); 16180 if (rv < 0) { 16181 LOG_ERROR(BSL_LS_SOC_COMMON, 16182 (BSL_META_U(unit, 16183 "Writing TOP_SOFT_RESET_REG failed !!\n"))); 16184 return rv; 16185 } 16186 16187 sal_usleep(to_usec); 16188 16189 WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0); 16190 16191 /* Bring IP, EP, ISM, ETU, AXP, and MMU blocks out of reset */ 16192 rv = READ_TOP_SOFT_RESET_REGr(unit, &rval); 16193 if (rv < 0) { 16194 LOG_ERROR(BSL_LS_SOC_COMMON, 16195 (BSL_META_U(unit, 16196 "Reading TOP_SOFT_RESET_REG failed !!\n"))); 16197 return rv; 16198 } 16199 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 16200 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 16201 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 16202 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_ISM_RST_Lf, 1); 16203 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_AXP_RST_Lf, 1); 16204 rv = WRITE_TOP_SOFT_RESET_REGr(unit, rval); 16205 if (rv < 0) { 16206 LOG_ERROR(BSL_LS_SOC_COMMON, 16207 (BSL_META_U(unit, 16208 "Writing TOP_SOFT_RESET_REG failed !!\n"))); 16209 return rv; 16210 } 16211 16212 sal_usleep(to_usec); 16213 16214 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_1r(unit, &rval)); 16215 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RESET_Nf, 1); 16216 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 16217 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RESET_Nf, 0); 16218 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 16219 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RESET_Nf, 1); 16220 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 16221 16222 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 16223 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 16224 TOP_TEMP_MON_PEAK_RST_Lf, 0); 16225 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 16226 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 16227 TOP_TEMP_MON_PEAK_RST_Lf, 1); 16228 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 16229 16230 16231 WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7A120); 16232 16233 /* Set MDIO IO PAD voltage */ 16234 if (0 != soc_property_get(unit, spn_MDIO_IO_VOLTAGE, 0)) { 16235 rv = READ_TOP_MISC_CONTROL_1r(unit, &rval); 16236 if (rv < 0) { 16237 LOG_ERROR(BSL_LS_SOC_COMMON, 16238 (BSL_META_U(unit, 16239 "Reading TOP_MISC_CONTROL_1 failed !!\n"))); 16240 return rv; 16241 } 16242 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, 16243 XG_MDIO0_CL_SELf, 1); 16244 rv = WRITE_TOP_MISC_CONTROL_1r(unit, rval); 16245 if (rv < 0) { 16246 LOG_ERROR(BSL_LS_SOC_COMMON, 16247 (BSL_META_U(unit, 16248 "Writing TOP_MISC_CONTROL_1 failed !!\n"))); 16249 return rv; 16250 } 16251 } 16252 /* Bring AMAC out of reset */ 16253 soc_amac_init(unit); 16254 16255 return SOC_E_NONE; 16256 } 16257 #endif 16258 16259 #ifdef BCM_KATANA_SUPPORT 16260 /* 16261 * Function: 16262 * soc_reset_bcm56440_a0 16263 * Purpose: 16264 * Special reset sequencing for BCM56440 16265 * Setup SBUS block mapping. 16266 */ 16267 STATIC int 16268 soc_reset_bcm56440_a0(int unit) 16269 { 16270 uint32 rval, to_usec; 16271 uint16 dev_id; 16272 uint8 rev_id; 16273 16274 /* TS PLL settings for 250MHZ output */ 16275 unsigned ts_ref_freq = 0; 16276 unsigned ts_idx=0; 16277 16278 /* values for 250 MHz TSPLL output */ 16279 static const soc_pll_param_t katana_ts_pll[] = { 16280 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 16281 {12800000, 310, 0, 1, 16, 1, 2, 7, 1}, 16282 {20000000, 200, 0, 1, 16, 2, 3, 8, 1}, 16283 {25000000, 160, 0, 1, 16, 2, 4, 9, 1}, 16284 {32000000, 125, 0, 1, 16, 2, 4, 9, 1}, 16285 { 0, 160, 0, 1, 16, 2, 4, 9, 1} /* 16286 25MHZ from internal reference */ 16287 }; 16288 16289 unsigned bs_ref_freq; 16290 unsigned bs_idx; 16291 16292 static const soc_pll_param_t katana_bs_pll[] = { /* values for 20 MHz BSPLL output */ 16293 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 16294 {12800000, 300, 0, 1, 192, 1, 2, 7, 1}, 16295 {20000000, 400, 0, 2, 200, 1, 2, 7, 1}, 16296 {25000000, 320, 0, 2, 200, 1, 2, 7, 1}, 16297 {32000000, 375, 0, 3, 200, 1, 2, 7, 1}, 16298 { 0, 320, 0, 2, 200, 2, 4, 9, 1} /* 16299 25MHZ from internal reference */ 16300 }; 16301 16302 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 16303 (10 * MILLISECOND_USEC); 16304 16305 /* 16306 * SBUS ring and block number: 16307 * Ring0: cmic -> ip-ep -> cmic 16308 * Ring1: cmic -> mxqport0 -> mxqport1-> mxqport2 -> mxqport3-> cmic 16309 * Ring2: cmic -> gport0 -> gport1 -> gport2 -> cmic 16310 * Ring3: cmic -> otpc -> top -> cmic 16311 * Ring4: cmic -> mmu0 -> mmu1 -> cmic 16312 * Ring5: cmic -> ci0 -> ci1 -> ci2 -> lls -> cmic 16313 * Ring6: cmic -> ces -> cmic 16314 * Ring7: unused 16315 */ 16316 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x22034000); /* block 7 - 0 */ 16317 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x55311112); /* block 15 - 8 */ 16318 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x00000655); /* block 23 - 16 */ 16319 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x00000000); /* block 31 - 24 */ 16320 16321 16322 16323 soc_cm_get_id(unit, &dev_id, &rev_id); 16324 16325 switch (dev_id) { 16326 case BCM56440_DEVICE_ID: /* 135 MHz Operation */ 16327 case BCM55440_DEVICE_ID: 16328 case BCM55441_DEVICE_ID: 16329 case BCM56445_DEVICE_ID: 16330 case BCM56448_DEVICE_ID: 16331 case BCM56449_DEVICE_ID: 16332 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL1_CTRL1r(unit, &rval)); 16333 soc_reg_field_set(unit, TOP_MMU_PLL1_CTRL1r, &rval, KPf, 10); 16334 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL1_CTRL1r(unit, rval)); 16335 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL2_CTRL1r(unit, &rval)); 16336 soc_reg_field_set(unit, TOP_MMU_PLL2_CTRL1r, &rval, KPf, 10); 16337 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL2_CTRL1r(unit, rval)); 16338 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL3_CTRL1r(unit, &rval)); 16339 soc_reg_field_set(unit, TOP_MMU_PLL3_CTRL1r, &rval, KPf, 10); 16340 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL3_CTRL1r(unit, rval)); 16341 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL1_CTRL3r(unit, &rval)); 16342 soc_reg_field_set(unit, TOP_MMU_PLL1_CTRL3r, &rval, PLL_CTRL_VCO_DIV2f, 1); 16343 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL1_CTRL3r(unit, rval)); 16344 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL2_CTRL3r(unit, &rval)); 16345 soc_reg_field_set(unit, TOP_MMU_PLL2_CTRL3r, &rval, PLL_CTRL_VCO_DIV2f, 1); 16346 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL2_CTRL3r(unit, rval)); 16347 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL3_CTRL3r(unit, &rval)); 16348 soc_reg_field_set(unit, TOP_MMU_PLL3_CTRL3r, &rval, PLL_CTRL_VCO_DIV2f, 1); 16349 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL3_CTRL3r(unit, rval)); 16350 break; 16351 default: /* 90 MHz Operation */ 16352 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL1_CTRL3r(unit, &rval)); 16353 soc_reg_field_set(unit, TOP_MMU_PLL1_CTRL3r, &rval, PLL_CTRL_PWM_RATEf, 0); 16354 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL1_CTRL3r(unit, rval)); 16355 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL2_CTRL3r(unit, &rval)); 16356 soc_reg_field_set(unit, TOP_MMU_PLL2_CTRL3r, &rval, PLL_CTRL_PWM_RATEf, 0); 16357 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL2_CTRL3r(unit, rval)); 16358 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL3_CTRL3r(unit, &rval)); 16359 soc_reg_field_set(unit, TOP_MMU_PLL3_CTRL3r, &rval, PLL_CTRL_PWM_RATEf, 0); 16360 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL3_CTRL3r(unit, rval)); 16361 break; 16362 } 16363 16364 SOC_IF_ERROR_RETURN(READ_TOP_SWITCH_FEATURE_ENABLE_2r(unit, &rval)); 16365 if (soc_reg_field_get(unit, TOP_SWITCH_FEATURE_ENABLE_2r, rval, BOND_1588_ENABLEf)) { 16366 SOC_FEATURE_SET(unit, soc_feature_timesync_support); 16367 } 16368 16369 if (soc_reg_field_get(unit, TOP_SWITCH_FEATURE_ENABLE_2r, rval, 16370 BOND_CES_ENABLEf)) { 16371 if ((rev_id != BCM56440_A0_REV_ID) && 16372 (soc_property_get(unit, spn_CES_DISABLE, 0))) { 16373 /* Disable CES */ 16374 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_2r(unit, &rval)); 16375 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 16376 BOND_CES_ENABLE_OVERRIDEf, 1); 16377 WRITE_TOP_MISC_CONTROL_2r(unit, rval); 16378 } else { 16379 #if defined(INCLUDE_CES) 16380 SOC_FEATURE_SET(unit, soc_feature_ces); 16381 #else 16382 if (rev_id != BCM56440_A0_REV_ID) { 16383 /* Disable CES */ 16384 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_2r(unit, &rval)); 16385 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, 16386 BOND_CES_ENABLE_OVERRIDEf, 1); 16387 WRITE_TOP_MISC_CONTROL_2r(unit, rval); 16388 } 16389 #endif 16390 } 16391 } 16392 16393 /* Bring LCPLL out of reset */ 16394 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 16395 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG0_PLL_RST_Lf, 16396 1); 16397 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG1_PLL_RST_Lf, 16398 1); 16399 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 16400 16401 sal_usleep(to_usec); 16402 16403 /* Wait for LCPLL lock */ 16404 if (!SAL_BOOT_SIMULATION) { 16405 SOC_IF_ERROR_RETURN(READ_TOP_XGXS0_PLL_STATUSr(unit, &rval)); 16406 16407 if (!soc_reg_field_get(unit, TOP_XGXS0_PLL_STATUSr, rval, TOP_XGPLL0_LOCKf)) { 16408 LOG_ERROR(BSL_LS_SOC_COMMON, 16409 (BSL_META_U(unit, 16410 "LCPLL 0 not locked on unit %d " 16411 "status = 0x%08x\n"), unit, rval)); 16412 } 16413 if ((dev_id != BCM56240_DEVICE_ID) && (dev_id != BCM56241_DEVICE_ID) && 16414 (dev_id != BCM56242_DEVICE_ID) && (dev_id != BCM56243_DEVICE_ID) && 16415 (dev_id != BCM56245_DEVICE_ID) && (dev_id != BCM56246_DEVICE_ID) && 16416 (dev_id != BCM56449_DEVICE_ID)) { 16417 /* Variants that don't use LCPLL-1 */ 16418 SOC_IF_ERROR_RETURN(READ_TOP_XGXS1_PLL_STATUSr(unit, &rval)); 16419 if (!soc_reg_field_get(unit, TOP_XGXS1_PLL_STATUSr, rval, TOP_XGPLL1_LOCKf)) { 16420 LOG_ERROR(BSL_LS_SOC_COMMON, 16421 (BSL_META_U(unit, 16422 "LCPLL 1 not locked on unit %d " 16423 "status = 0x%08x\n"), unit, rval)); 16424 } 16425 } 16426 } 16427 16428 /* KT-1367: Timesync PLL 250MHz TS_CLK from 25MHz refclk */ 16429 /* NDIV= 100(0x64) MDIV=10(0x1) */ 16430 16431 /* TSPLL configuration: 250MHz TS_CLK from 12.8/20/25/32MHz refclk */ 16432 16433 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); 16434 16435 for (ts_idx =0; ts_idx < (sizeof(katana_ts_pll)/sizeof(katana_ts_pll[0])); 16436 ++ts_idx) { 16437 if (katana_ts_pll[ts_idx].ref_freq == ts_ref_freq) { 16438 break; 16439 }; 16440 } 16441 16442 if (ts_idx >= (sizeof(katana_ts_pll)/sizeof(katana_ts_pll[0]))) { 16443 ts_idx = 4; /* wrong config, for now use internal 25MHZ reference */ 16444 ts_ref_freq = 0; 16445 } 16446 16447 16448 /* Configure TS PLL */ 16449 /* Set TS_PLL_CLK_IN_SEL based on reference frequency. If it is 0, use the 16450 * internal reference */ 16451 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_2r(unit,&rval)); 16452 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, TS_PLL_CLK_IN_SELf, 16453 (ts_ref_freq != 0)); 16454 WRITE_TOP_MISC_CONTROL_2r(unit, rval); 16455 16456 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_0r(unit,&rval)); 16457 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_0r, &rval, VCO_DIV2f, 16458 1); /* soc_property_get(unit, spn_TIME_SYNC_VCO_DIV2, 0)); */ 16459 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_0r(unit, rval); 16460 16461 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r(unit,&rval)); 16462 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r, &rval, KAf, 16463 soc_property_get(unit, spn_PTP_TS_KA, katana_ts_pll[ts_idx].ka)); 16464 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r, &rval, KIf, 16465 soc_property_get(unit, spn_PTP_TS_KI, katana_ts_pll[ts_idx].ki)); 16466 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r, &rval, KPf, 16467 soc_property_get(unit, spn_PTP_TS_KP, katana_ts_pll[ts_idx].kp)); 16468 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r(unit, rval); 16469 16470 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r(unit,&rval)); 16471 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, PDIVf, 16472 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, 16473 katana_ts_pll[ts_idx].pdiv)); 16474 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r(unit, rval); 16475 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r(unit,&rval)); 16476 16477 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r, &rval, NDIV_INTf, 16478 soc_property_get(unit, spn_PTP_TS_PLL_N, 16479 katana_ts_pll[ts_idx].ndiv_int)); 16480 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r, &rval, NDIV_FRACf, 16481 katana_ts_pll[ts_idx].ndiv_frac); 16482 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r(unit, rval); 16483 16484 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_4r(unit,&rval)); 16485 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_4r, &rval, CH0_MDIVf, 16486 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, 16487 katana_ts_pll[ts_idx].mdiv)); 16488 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_4r(unit, rval); 16489 16490 /* 250Mhz TS PLL implies 4ns resolution */ 16491 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); /* clock period in nanoseconds */ 16492 16493 /* Configure BS PLL */ 16494 /* Note: Using 0 to signify internal reference for BroadSync PLL. 16495 Earlier, 25000000 is used for the same, where we can't distinguish between 16496 external 25MHz and internal reference */ 16497 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 0); 16498 16499 /* BSPLL configuration: 20MHz BS_CLK from 12.8/20/25/32MHz Fref or Internal ref:0*/ 16500 for (bs_idx =0; bs_idx < (sizeof(katana_bs_pll)/sizeof(katana_bs_pll[0])); 16501 ++bs_idx) { 16502 if (katana_bs_pll[bs_idx].ref_freq == bs_ref_freq) { 16503 break; 16504 }; 16505 } 16506 16507 /* If the property spn_PTP_BS_FREF is set to a value other than 16508 internal reference(0) or the permitted external fref set(i.e., 12.8/20/25/32MHz), 16509 configure the BS PLL for internal reference i.e., use the last table entry */ 16510 if (bs_idx >= (sizeof(katana_bs_pll)/sizeof(katana_bs_pll[0]))) { 16511 LOG_ERROR(BSL_LS_SOC_COMMON, 16512 (BSL_META_U(unit, 16513 "Invalid value for PTP_BS_FREF (%u). Using default PLL params.\n"), bs_ref_freq)); 16514 16515 bs_idx = (sizeof(katana_bs_pll)/sizeof(katana_bs_pll[0]))-1; 16516 bs_ref_freq = 0; 16517 } 16518 16519 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_2r(unit,&rval)); 16520 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, BS_PLL_CLK_IN_SELf, 16521 (bs_ref_freq!=0)); 16522 WRITE_TOP_MISC_CONTROL_2r(unit, rval); 16523 16524 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC_PLL_CTRL_REGISTER_0r(unit,&rval)); 16525 soc_reg_field_set(unit, TOP_BROAD_SYNC_PLL_CTRL_REGISTER_0r, &rval, VCO_DIV2f, 16526 soc_property_get(unit, spn_PTP_BS_VCO_DIV2, katana_bs_pll[bs_idx].vco_div2)); 16527 WRITE_TOP_BROAD_SYNC_PLL_CTRL_REGISTER_0r(unit, rval); 16528 16529 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC_PLL_CTRL_REGISTER_1r(unit,&rval)); 16530 soc_reg_field_set(unit, TOP_BROAD_SYNC_PLL_CTRL_REGISTER_1r, &rval, KAf, 16531 soc_property_get(unit, spn_PTP_BS_KA, katana_bs_pll[bs_idx].ka)); 16532 soc_reg_field_set(unit, TOP_BROAD_SYNC_PLL_CTRL_REGISTER_1r, &rval, KIf, 16533 soc_property_get(unit, spn_PTP_BS_KI, katana_bs_pll[bs_idx].ki)); 16534 soc_reg_field_set(unit, TOP_BROAD_SYNC_PLL_CTRL_REGISTER_1r, &rval, KPf, 16535 soc_property_get(unit, spn_PTP_BS_KP, katana_bs_pll[bs_idx].kp)); 16536 WRITE_TOP_BROAD_SYNC_PLL_CTRL_REGISTER_1r(unit, rval); 16537 16538 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC_PLL_CTRL_REGISTER_2r(unit,&rval)); 16539 soc_reg_field_set(unit, TOP_BROAD_SYNC_PLL_CTRL_REGISTER_2r, &rval, PDIVf, 16540 soc_property_get(unit, spn_PTP_BS_PDIV, katana_bs_pll[bs_idx].pdiv)); 16541 WRITE_TOP_BROAD_SYNC_PLL_CTRL_REGISTER_2r(unit, rval); 16542 16543 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC_PLL_CTRL_REGISTER_3r(unit,&rval)); 16544 soc_reg_field_set(unit, TOP_BROAD_SYNC_PLL_CTRL_REGISTER_3r, &rval, NDIV_INTf, 16545 soc_property_get(unit, spn_PTP_BS_NDIV_INT, katana_bs_pll[bs_idx].ndiv_int)); 16546 soc_reg_field_set(unit, TOP_BROAD_SYNC_PLL_CTRL_REGISTER_3r, &rval, NDIV_FRACf, 16547 soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, katana_bs_pll[bs_idx].ndiv_frac)); 16548 WRITE_TOP_BROAD_SYNC_PLL_CTRL_REGISTER_3r(unit, rval); 16549 16550 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC_PLL_CTRL_REGISTER_4r(unit,&rval)); 16551 soc_reg_field_set(unit, TOP_BROAD_SYNC_PLL_CTRL_REGISTER_4r, &rval, CH0_MDIVf, 16552 soc_property_get(unit, spn_PTP_BS_MNDIV, katana_bs_pll[bs_idx].mdiv)); 16553 WRITE_TOP_BROAD_SYNC_PLL_CTRL_REGISTER_4r(unit, rval); 16554 16555 /* CES SETUP for external OCXO */ 16556 if (soc_property_get(unit, spn_CES_PLL_REFERENCE_CLOCK_RATE, 25000000)== 16557 12800000){ 16558 16559 /* Configure CES PLL */ 16560 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_2r(unit,&rval)); 16561 soc_reg_field_set(unit, TOP_MISC_CONTROL_2r, &rval, CES_PLL_CLK_IN_SELf, 16562 1); 16563 WRITE_TOP_MISC_CONTROL_2r(unit, rval); 16564 16565 SOC_IF_ERROR_RETURN(READ_TOP_CES_PLL_CTRL_REGISTER_0r(unit,&rval)); 16566 soc_reg_field_set(unit, TOP_CES_PLL_CTRL_REGISTER_0r, &rval, VCO_DIV2f, 16567 1); 16568 WRITE_TOP_CES_PLL_CTRL_REGISTER_0r(unit, rval); 16569 16570 SOC_IF_ERROR_RETURN(READ_TOP_CES_PLL_CTRL_REGISTER_1r(unit,&rval)); 16571 soc_reg_field_set(unit, TOP_CES_PLL_CTRL_REGISTER_1r, &rval, KAf, 16572 1); 16573 soc_reg_field_set(unit, TOP_CES_PLL_CTRL_REGISTER_1r, &rval, KIf, 16574 1); 16575 soc_reg_field_set(unit, TOP_CES_PLL_CTRL_REGISTER_1r, &rval, KPf, 16576 5); 16577 WRITE_TOP_CES_PLL_CTRL_REGISTER_1r(unit, rval); 16578 16579 16580 SOC_IF_ERROR_RETURN(READ_TOP_CES_PLL_CTRL_REGISTER_2r(unit,&rval)); 16581 soc_reg_field_set(unit, TOP_CES_PLL_CTRL_REGISTER_2r, &rval, PDIVf, 16582 4); 16583 WRITE_TOP_CES_PLL_CTRL_REGISTER_2r(unit, rval); 16584 16585 SOC_IF_ERROR_RETURN(READ_TOP_CES_PLL_CTRL_REGISTER_3r(unit,&rval)); 16586 soc_reg_field_set(unit, TOP_CES_PLL_CTRL_REGISTER_3r, &rval, NDIV_INTf, 16587 625); 16588 soc_reg_field_set(unit, TOP_CES_PLL_CTRL_REGISTER_3r, &rval, NDIV_FRACf, 16589 0); 16590 WRITE_TOP_CES_PLL_CTRL_REGISTER_3r(unit, rval); 16591 16592 SOC_IF_ERROR_RETURN(READ_TOP_CES_PLL_CTRL_REGISTER_4r(unit,&rval)); 16593 soc_reg_field_set(unit, TOP_CES_PLL_CTRL_REGISTER_4r, &rval, CH0_MDIVf, 16594 80); 16595 soc_reg_field_set(unit, TOP_CES_PLL_CTRL_REGISTER_4r, &rval, CH1_MDIVf, 16596 16); 16597 16598 WRITE_TOP_CES_PLL_CTRL_REGISTER_4r(unit, rval); 16599 16600 16601 } 16602 16603 16604 16605 16606 /* De-assert LCPLL's post reset */ 16607 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 16608 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG0_PLL_POST_RST_Lf, 16609 1); 16610 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG1_PLL_POST_RST_Lf, 16611 1); 16612 if (soc_feature(unit, soc_feature_ces)) { 16613 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_CES_PLL_RST_Lf, 16614 1); 16615 } 16616 16617 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_RST_Lf, 16618 1); 16619 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL_RST_Lf, 16620 1); 16621 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 16622 16623 sal_usleep(to_usec); 16624 16625 if (!SAL_BOOT_SIMULATION) { 16626 if (soc_feature(unit, soc_feature_ces)) { 16627 SOC_IF_ERROR_RETURN(READ_TOP_CES_PLL_STATUSr(unit, &rval)); 16628 if (!soc_reg_field_get(unit, TOP_CES_PLL_STATUSr, rval, TOP_CES_PLL_LOCKf)) { 16629 LOG_ERROR(BSL_LS_SOC_COMMON, 16630 (BSL_META_U(unit, 16631 "CES PLL not locked on unit %d " 16632 "status = 0x%08x\n"), unit, rval)); 16633 } 16634 } 16635 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_STATUSr(unit, &rval)); 16636 if (!soc_reg_field_get(unit, TOP_TIME_SYNC_PLL_STATUSr, rval, 16637 TOP_TIME_SYNC_PLL_LOCKf)) { 16638 LOG_ERROR(BSL_LS_SOC_COMMON, 16639 (BSL_META_U(unit, 16640 "TimeSync PLL not locked on unit %d " 16641 "status = 0x%08x\n"), unit, rval)); 16642 } 16643 16644 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC_PLL_STATUSr(unit, &rval)); 16645 if (!soc_reg_field_get(unit, TOP_BROAD_SYNC_PLL_STATUSr, rval, 16646 TOP_BROAD_SYNC_PLL_LOCKf)) { 16647 LOG_ERROR(BSL_LS_SOC_COMMON, 16648 (BSL_META_U(unit, 16649 "BroadSync PLL not locked on unit %d " 16650 "status = 0x%08x\n"), unit, rval)); 16651 } 16652 } 16653 16654 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 16655 if (soc_feature(unit, soc_feature_ces)) { 16656 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_CES_PLL_POST_RST_Lf, 16657 1); 16658 } 16659 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_POST_RST_Lf, 16660 1); 16661 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL_POST_RST_Lf, 16662 1); 16663 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 16664 16665 sal_usleep(to_usec); 16666 16667 /* 16668 * Bring port blocks out of reset 16669 */ 16670 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 16671 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ0_RST_Lf, 1); 16672 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ1_RST_Lf, 1); 16673 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ2_RST_Lf, 1); 16674 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ3_RST_Lf, 1); 16675 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GP0_RST_Lf, 1); 16676 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GP1_RST_Lf, 1); 16677 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GP2_RST_Lf, 1); 16678 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 16679 16680 sal_usleep(to_usec); 16681 16682 /* Bring network sync out of reset */ 16683 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 16684 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ0_HOTSWAP_RST_Lf, 1); 16685 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ1_HOTSWAP_RST_Lf, 1); 16686 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ2_HOTSWAP_RST_Lf, 1); 16687 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ3_HOTSWAP_RST_Lf, 1); 16688 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_NS_RST_Lf, 1); 16689 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 16690 16691 sal_usleep(to_usec); 16692 16693 SOC_IF_ERROR_RETURN(WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0)); 16694 16695 /* Bring IP, EP, and MMU blocks out of reset */ 16696 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 16697 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 16698 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 16699 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 16700 if (soc_feature(unit, soc_feature_ces)) { 16701 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_CES_RST_Lf, 1); 16702 } 16703 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 16704 16705 sal_usleep(to_usec); 16706 16707 if (((dev_id == BCM56445_DEVICE_ID) && (rev_id == BCM56445_A0_REV_ID)) || 16708 ((dev_id == BCM56446_DEVICE_ID) && (rev_id == BCM56446_A0_REV_ID)) || 16709 ((dev_id == BCM56447_DEVICE_ID) && (rev_id == BCM56447_A0_REV_ID)) || 16710 ((dev_id == BCM56448_DEVICE_ID) && (rev_id == BCM56448_A0_REV_ID)) ) { 16711 _kt_lls_workaround(unit); 16712 } 16713 return SOC_E_NONE; 16714 } 16715 #endif /* BCM_KATANA_SUPPORT */ 16716 16717 #ifdef BCM_KATANA2_SUPPORT 16718 /* 16719 * Function: 16720 * soc_reset_bcm56450_a0 16721 * Purpose: 16722 * Special reset sequencing for BCM56450 16723 * Setup SBUS block mapping. 16724 */ 16725 STATIC int 16726 soc_reset_bcm56450_a0(int unit) 16727 { 16728 uint32 rval, to_usec; 16729 uint16 dev_id; 16730 uint8 rev_id; 16731 uint32 mmu_pkg_enable; 16732 16733 unsigned ts_ref_freq; 16734 unsigned ts_idx; 16735 static const soc_pll_param_t ts_pll[] = { /* values for 500MHz TSPLL output */ 16736 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 16737 {12800000, 312, 0x80000, 1, 8, 1, 2, 7, 1}, 16738 {20000000, 200, 0, 1, 8, 2, 3, 8, 1}, 16739 {25000000, 160, 0, 1, 8, 2, 4, 9, 1}, 16740 {32000000, 125, 0, 1, 8, 2, 4, 9, 1}, 16741 {50000000, 80, 0, 1, 8, 3, 4, 10, 1}, 16742 { 0, 160, 0, 1, 8, 2, 4, 9, 1} /* 25MHz, from internal reference */ 16743 }; 16744 unsigned bs_ref_freq; 16745 unsigned bs_idx; 16746 uint32 bs_ndiv_high, bs_ndiv_low; 16747 static const soc_pll_param_t bs_pll[] = { /* values for 20MHz BSPLL output */ 16748 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 16749 {12800000, 250, 0, 1, 160, 1, 2, 7, 0}, 16750 {20000000, 175, 0, 1, 175, 2, 3, 8, 0}, 16751 {25000000, 140, 0, 1, 175, 2, 4, 9, 0}, 16752 {32000000, 108, 0xc0000000, 1, 174, 2, 4, 9, 0}, /* Ndiv=108.75 */ 16753 {50000000, 70, 0, 1, 175, 3, 4, 10, 0}, 16754 { 0, 140, 0, 1, 175, 2, 4, 9, 0} /* 25MHz, from internal reference */ 16755 }; 16756 #if defined(BCM_HITLESS_RESET_SUPPORT) 16757 int initialize_broadsync; 16758 const int broadsync_default_ka = 4, broadsync_default_ki = 1, broadsync_default_kp = 8; 16759 #endif /* BCM_HITLESS_RESET_SUPPORT */ 16760 16761 soc_cm_get_id(unit, &dev_id, &rev_id); 16762 16763 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 16764 (10 * MILLISECOND_USEC); 16765 16766 /* 16767 * SBUS ring and block number: 16768 * Ring0: cmic -> ip-ep -> cmic 16769 * Ring1: cmic -> mxqport0 -> mxqport1-> mxqport2 -> mxqport3-> cmic 16770 * Ring2: cmic -> gport0 -> gport1 -> gport2 -> cmic 16771 * Ring3: cmic -> otpc -> top -> cmic 16772 * Ring4: cmic -> mmu0 -> mmu1 -> cmic 16773 * Ring5: cmic -> ci0 -> ci1 -> ci2 -> lls -> cmic 16774 * Ring6: cmic -> ces -> cmic 16775 * Ring7: unused 16776 */ 16777 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x66034000); /* block 7 - 0 */ 16778 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x11112222); /* block 15 - 8 */ 16779 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x55555553); /* block 23 - 16 */ 16780 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x00637777); /* block 31 - 24 */ 16781 16782 /* Bring MMUPLL out of reset */ 16783 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL_INITr(unit, &rval)); 16784 soc_reg_field_set(unit, TOP_MMU_PLL_INITr, &rval, 16785 PLL1_RESETBf, 1); 16786 soc_reg_field_set(unit, TOP_MMU_PLL_INITr, &rval, 16787 PLL2_RESETBf, 1); 16788 soc_reg_field_set(unit, TOP_MMU_PLL_INITr, &rval, 16789 PLL3_RESETBf, 1); 16790 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL_INITr(unit, rval)); 16791 16792 sal_usleep(to_usec); 16793 16794 /* Wait for MMUPLL lock */ 16795 if (!SAL_BOOT_SIMULATION) { 16796 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL_STATUS0r(unit, &rval)); 16797 if (!soc_reg_field_get(unit, TOP_MMU_PLL_STATUS0r, rval, MMU_PLL1_LOCKf)) { 16798 LOG_ERROR(BSL_LS_SOC_COMMON, 16799 (BSL_META_U(unit, 16800 "MMUPLL 1 not locked on unit %d " 16801 "status = 0x%08x\n"), unit, rval)); 16802 } 16803 if (!soc_reg_field_get(unit, TOP_MMU_PLL_STATUS0r, rval, MMU_PLL2_LOCKf)) { 16804 LOG_ERROR(BSL_LS_SOC_COMMON, 16805 (BSL_META_U(unit, 16806 "MMUPLL 2 not locked on unit %d " 16807 "status = 0x%08x\n"), unit, rval)); 16808 } 16809 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL_STATUS1r(unit, &rval)); 16810 if (!soc_reg_field_get(unit, TOP_MMU_PLL_STATUS1r, rval, MMU_PLL3_LOCKf)) { 16811 LOG_ERROR(BSL_LS_SOC_COMMON, 16812 (BSL_META_U(unit, 16813 "MMUPLL 3 not locked on unit %d " 16814 "status = 0x%08x\n"), unit, rval)); 16815 } 16816 } 16817 SOC_IF_ERROR_RETURN(READ_TOP_MMU_PLL_INITr(unit, &rval)); 16818 soc_reg_field_set(unit, TOP_MMU_PLL_INITr, &rval, 16819 PLL1_POST_RESETBf, 1); 16820 soc_reg_field_set(unit, TOP_MMU_PLL_INITr, &rval, 16821 PLL2_POST_RESETBf, 1); 16822 soc_reg_field_set(unit, TOP_MMU_PLL_INITr, &rval, 16823 PLL3_POST_RESETBf, 1); 16824 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_PLL_INITr(unit, rval)); 16825 16826 /* TSPLL configuration: 500MHz TS_CLK from 20/25/32/50MHz refclk */ 16827 /* CMICd divides by 2 on input, so this is a 250MHz clock to TS logic */ 16828 16829 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 50000000); /* 50MHz is default. 0->internal reference */ 16830 /* Set TS_PLL_CLK_IN_SEL based on reference frequency. If it is 0, use the internal reference */ 16831 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit,&rval)); 16832 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, TS_PLL_CLK_IN_SELf, 16833 (ts_ref_freq != 0)); 16834 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 16835 16836 for (ts_idx = 0; ts_idx < sizeof(ts_pll)/sizeof(ts_pll[0]); ++ts_idx) { 16837 if (ts_pll[ts_idx].ref_freq == ts_ref_freq) { 16838 break; 16839 } 16840 } 16841 if (ts_idx == sizeof(ts_pll)/sizeof(ts_pll[0])) { 16842 LOG_ERROR(BSL_LS_SOC_COMMON, 16843 (BSL_META_U(unit, 16844 "Invalid value for PTP_TS_PLL_REF (%u). No default PLL params.\n"), ts_ref_freq)); 16845 /* Could check for existence of SOC properties for VCO_DIV2, KA, KI, KP, NDIV_INT, NDIV_FRAC, MDIV, PDIV, and if 16846 all exist, use them. For now, just fail. 16847 */ 16848 } else { 16849 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_0r(unit,&rval)); 16850 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_0r, &rval, VCO_DIV2f, 16851 soc_property_get(unit, spn_PTP_TS_VCO_DIV2, ts_pll[ts_idx].vco_div2)); 16852 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_0r(unit, rval); 16853 16854 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r(unit,&rval)); 16855 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r, &rval, KAf, 16856 soc_property_get(unit, spn_PTP_TS_KA, ts_pll[ts_idx].ka)); 16857 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r, &rval, KIf, 16858 soc_property_get(unit, spn_PTP_TS_KI, ts_pll[ts_idx].ki)); 16859 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r, &rval, KPf, 16860 soc_property_get(unit, spn_PTP_TS_KP, ts_pll[ts_idx].kp)); 16861 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r(unit, rval); 16862 16863 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r(unit,&rval)); 16864 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, PDIVf, 16865 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, ts_pll[ts_idx].pdiv)); 16866 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r(unit, rval); 16867 16868 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r(unit,&rval)); 16869 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r, &rval, NDIV_INTf, 16870 soc_property_get(unit, spn_PTP_TS_PLL_N, ts_pll[ts_idx].ndiv_int)); 16871 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r, &rval, NDIV_FRACf, 16872 ts_pll[ts_idx].ndiv_frac); 16873 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r(unit, rval); 16874 16875 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_4r(unit,&rval)); 16876 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_4r, &rval, CH0_MDIVf, 16877 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, ts_pll[ts_idx].mdiv)); 16878 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_4r(unit, rval); 16879 } 16880 16881 /* 500Mhz TSPLL -> 250MHz ref at timestamper, implies 4ns resolution */ 16882 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); /* clock period in nanoseconds */ 16883 16884 /* Check to see if the BSPLLs have been configured yet. If so, we leave them alone, 16885 for hitless reset support. 16886 Note: On KT2 A0/B0, the BroadSync Bitclock/Heartbeat regs get reset, so we still 16887 initialize all of BroadSync. 16888 */ 16889 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit,&rval)); 16890 16891 #if defined(BCM_HITLESS_RESET_SUPPORT) 16892 initialize_broadsync = 16893 (soc_reg_field_get(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r, 16894 rval, KAf) == broadsync_default_ka 16895 && soc_reg_field_get(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r, 16896 rval, KIf) == broadsync_default_ki 16897 && soc_reg_field_get(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r, 16898 rval, KPf) == broadsync_default_kp); 16899 16900 LOG_VERBOSE(BSL_LS_SOC_COMMON, 16901 (BSL_META_U(unit, 16902 "BSPLL regs: %s\n"), initialize_broadsync ? "Default" : "Configured")); 16903 16904 if (!initialize_broadsync) { 16905 /* JIRA CMICD-110 16906 * On A0/B0, BroadSync Bitclock/Heartbeat divisors/enable registers get reset, 16907 * though the outputs themselves do not if the registers were written to an even 16908 * number of times. Workaround: when the registers are changed, the register 16909 * should be written twice, and the same value stored in SRAM. This code will 16910 * restore the register from SRAM. 16911 */ 16912 16913 /* BS0 */ 16914 uint32 reg_cache_base = soc_cmic_bs_reg_cache(unit, 0); 16915 16916 uint32 config = soc_uc_mem_read(unit, 16917 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, config)); 16918 uint32 clk_ctrl = soc_uc_mem_read(unit, 16919 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, clk_ctrl)); 16920 uint32 heartbeat_ctrl = soc_uc_mem_read(unit, 16921 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl)); 16922 uint32 heartbeat_down = soc_uc_mem_read(unit, 16923 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration)); 16924 uint32 heartbeat_up = soc_uc_mem_read(unit, 16925 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration)); 16926 16927 if (config == 0 && clk_ctrl == 0 && heartbeat_ctrl == 0 && heartbeat_down == 0 && heartbeat_up == 0) { 16928 /* PLL was initialized, but there is no saved state. Reset BroadSync. */ 16929 initialize_broadsync = 1; 16930 LOG_ERROR(BSL_LS_SOC_COMMON, 16931 (BSL_META_U(unit, 16932 "BSPLL Configured, but no BS state to restore\n"))); 16933 } else { 16934 /* Double-writes, per CMICD-110 WAR */ 16935 WRITE_CMIC_BS0_CONFIGr(unit, config); 16936 WRITE_CMIC_BS0_CONFIGr(unit, config); 16937 WRITE_CMIC_BS0_CLK_CTRLr(unit, clk_ctrl); 16938 WRITE_CMIC_BS0_CLK_CTRLr(unit, clk_ctrl); 16939 WRITE_CMIC_BS0_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 16940 WRITE_CMIC_BS0_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 16941 WRITE_CMIC_BS0_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 16942 WRITE_CMIC_BS0_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 16943 WRITE_CMIC_BS0_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 16944 WRITE_CMIC_BS0_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 16945 16946 LOG_VERBOSE(BSL_LS_SOC_COMMON, 16947 (BSL_META_U(unit, 16948 "Restored BS0 regs:\n" 16949 " config: %08x clk_ctrl: %08x hb_ctrl: %08x\n" 16950 " hb_up: %08x hb_down: %08x\n"), 16951 config, clk_ctrl, heartbeat_ctrl, 16952 heartbeat_down, heartbeat_up)); 16953 16954 /* same, but for BS1 */ 16955 reg_cache_base = soc_cmic_bs_reg_cache(unit, 1); 16956 16957 config = soc_uc_mem_read(unit, 16958 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, config)); 16959 clk_ctrl = soc_uc_mem_read(unit, 16960 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, clk_ctrl)); 16961 heartbeat_ctrl = soc_uc_mem_read(unit, 16962 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl)); 16963 heartbeat_down = soc_uc_mem_read(unit, 16964 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration)); 16965 heartbeat_up = soc_uc_mem_read(unit, 16966 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration)); 16967 16968 WRITE_CMIC_BS1_CONFIGr(unit, config); 16969 WRITE_CMIC_BS1_CONFIGr(unit, config); 16970 WRITE_CMIC_BS1_CLK_CTRLr(unit, clk_ctrl); 16971 WRITE_CMIC_BS1_CLK_CTRLr(unit, clk_ctrl); 16972 WRITE_CMIC_BS1_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 16973 WRITE_CMIC_BS1_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 16974 WRITE_CMIC_BS1_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 16975 WRITE_CMIC_BS1_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 16976 WRITE_CMIC_BS1_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 16977 WRITE_CMIC_BS1_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 16978 16979 LOG_VERBOSE(BSL_LS_SOC_COMMON, 16980 (BSL_META_U(unit, 16981 "Restored BS1 regs:\n" 16982 " config: %08x clk_ctrl: %08x hb_ctrl: %08x\n" 16983 " hb_up: %08x hb_down: %08x\n"), 16984 config, clk_ctrl, heartbeat_ctrl, 16985 heartbeat_down, heartbeat_up)); 16986 } 16987 } 16988 16989 if (initialize_broadsync) 16990 #endif /* BCM_HITLESS_RESET_SUPPORT */ 16991 { 16992 /* as a signal to upper-level code that the BroadSync is newly initialized 16993 * disable BroadSync0/1 bitclock output. Checked in time.c / 1588 firmware */ 16994 SOC_IF_ERROR_RETURN(READ_CMIC_BS0_CONFIGr(unit, &rval)); 16995 soc_reg_field_set(unit, CMIC_BS0_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 16996 WRITE_CMIC_BS0_CONFIGr(unit, rval); 16997 16998 SOC_IF_ERROR_RETURN(READ_CMIC_BS1_CONFIGr(unit, &rval)); 16999 soc_reg_field_set(unit, CMIC_BS1_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 17000 WRITE_CMIC_BS1_CONFIGr(unit, rval); 17001 17002 /* BSPLL0 has not been configured, so reset/configure both BSPLL0 and BSPLL1 */ 17003 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_3r(unit, &rval)); 17004 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS0_PLL_RST_Lf, 0); 17005 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS1_PLL_RST_Lf, 0); 17006 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS0_PLL_POST_RST_Lf, 0); 17007 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS1_PLL_POST_RST_Lf, 0); 17008 WRITE_TOP_SOFT_RESET_REG_3r(unit, rval); 17009 17010 /* Both BSPLLs configured the same, for 20MHz output by default */ 17011 17012 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 50000000); /* 50MHz is default. 0->internal reference */ 17013 /* Set BS_PLL_CLK_IN_SEL based on reference frequency. If it is 0, use the internal reference */ 17014 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit,&rval)); 17015 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, BS0_PLL_CLK_IN_SELf, 17016 (bs_ref_freq != 0)); 17017 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, BS1_PLL_CLK_IN_SELf, 17018 (bs_ref_freq != 0)); 17019 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 17020 17021 for (bs_idx = 0; bs_idx < sizeof(bs_pll)/sizeof(bs_pll[0]); ++bs_idx) { 17022 if (bs_pll[bs_idx].ref_freq == bs_ref_freq) { 17023 break; 17024 } 17025 } 17026 if (bs_idx == sizeof(bs_pll)/sizeof(bs_pll[0])) { 17027 LOG_ERROR(BSL_LS_SOC_COMMON, 17028 (BSL_META_U(unit, 17029 "Invalid value for PTP_BS_REF (%u). No default PLL params.\n"), bs_ref_freq)); 17030 /* Could check for existence of SOC properties for VCO_DIV2, KA, KI, KP, NDIV_INT, 17031 NDIV_FRAC, MDIV, PDIV, and if all exist, use them. For now, just fail. 17032 */ 17033 } else { 17034 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r(unit,&rval)); 17035 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r, &rval, VCODIV2f, 17036 soc_property_get(unit, spn_PTP_BS_VCO_DIV2, bs_pll[bs_idx].vco_div2)); 17037 WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r(unit, rval); 17038 17039 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r(unit,&rval)); 17040 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r, &rval, VCODIV2f, 17041 soc_property_get(unit, spn_PTP_BS_VCO_DIV2, bs_pll[bs_idx].vco_div2)); 17042 WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r(unit, rval); 17043 17044 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit,&rval)); 17045 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r, &rval, KAf, 17046 soc_property_get(unit, spn_PTP_BS_KA, bs_pll[bs_idx].ka)); 17047 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r, &rval, KIf, 17048 soc_property_get(unit, spn_PTP_BS_KI, bs_pll[bs_idx].ki)); 17049 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r, &rval, KPf, 17050 soc_property_get(unit, spn_PTP_BS_KP, bs_pll[bs_idx].kp)); 17051 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r, &rval, PDIVf, 17052 soc_property_get(unit, spn_PTP_BS_PDIV, bs_pll[bs_idx].pdiv)); 17053 WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit, rval); 17054 17055 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r(unit,&rval)); 17056 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r, &rval, KAf, 17057 soc_property_get(unit, spn_PTP_BS_KA, bs_pll[bs_idx].ka)); 17058 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r, &rval, KIf, 17059 soc_property_get(unit, spn_PTP_BS_KI, bs_pll[bs_idx].ki)); 17060 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r, &rval, KPf, 17061 soc_property_get(unit, spn_PTP_BS_KP, bs_pll[bs_idx].kp)); 17062 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r, &rval, PDIVf, 17063 soc_property_get(unit, spn_PTP_BS_PDIV, bs_pll[bs_idx].pdiv)); 17064 WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r(unit, rval); 17065 17066 bs_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, bs_pll[bs_idx].ndiv_int) << 8) | 17067 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs_pll[bs_idx].ndiv_frac) >> 24) & 0xff)); 17068 bs_ndiv_low = (soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs_pll[bs_idx].ndiv_frac) << 8); 17069 17070 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 17071 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r, &rval, BROAD_SYNC0_LCPLL_FBDIV_1f, bs_ndiv_high); 17072 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit, rval); 17073 17074 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 17075 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r, &rval, BROAD_SYNC0_LCPLL_FBDIV_0f, bs_ndiv_low); 17076 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit, rval); 17077 17078 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 17079 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r, &rval, BROAD_SYNC1_LCPLL_FBDIV_1f, bs_ndiv_high); 17080 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit, rval); 17081 17082 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 17083 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r, &rval, BROAD_SYNC1_LCPLL_FBDIV_0f, bs_ndiv_low); 17084 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit, rval); 17085 17086 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_0r(unit,&rval)); 17087 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_0r, &rval, CH1_MDIVf, 17088 soc_property_get(unit, spn_PTP_BS_MNDIV, bs_pll[bs_idx].mdiv)); 17089 WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_0r(unit, rval); 17090 17091 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_0r(unit,&rval)); 17092 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_0r, &rval, CH1_MDIVf, 17093 soc_property_get(unit, spn_PTP_BS_MNDIV, bs_pll[bs_idx].mdiv)); 17094 WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_0r(unit, rval); 17095 } 17096 17097 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_3r(unit, &rval)); 17098 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS0_PLL_RST_Lf, 1); 17099 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS1_PLL_RST_Lf, 1); 17100 WRITE_TOP_SOFT_RESET_REG_3r(unit, rval); 17101 17102 /* JIRA CMICD-110: See above logic to restore BroadSync Bitclock/Heartbeat. */ 17103 /* Store default values in the SRAM, so they will be restored correctly */ 17104 /* even if SRAM is not used */ 17105 #if defined(BCM_HITLESS_RESET_SUPPORT) 17106 { 17107 /* store reset values in SRAM for BS0 */ 17108 uint32 reg_cache_base = soc_cmic_bs_reg_cache(unit, 0); 17109 READ_CMIC_BS0_CONFIGr(unit, &rval); 17110 soc_uc_mem_write(unit, reg_cache_base + 17111 offsetof(mos_msg_bs_reg_cache_t, config), rval); 17112 READ_CMIC_BS0_CLK_CTRLr(unit, &rval); 17113 soc_uc_mem_write(unit, reg_cache_base + 17114 offsetof(mos_msg_bs_reg_cache_t, clk_ctrl), rval); 17115 READ_CMIC_BS0_HEARTBEAT_CTRLr(unit, &rval); 17116 soc_uc_mem_write(unit, reg_cache_base + 17117 offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl), rval); 17118 READ_CMIC_BS0_HEARTBEAT_DOWN_DURATIONr(unit, &rval); 17119 soc_uc_mem_write(unit, reg_cache_base + 17120 offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration), rval); 17121 READ_CMIC_BS0_HEARTBEAT_UP_DURATIONr(unit, &rval); 17122 soc_uc_mem_write(unit, reg_cache_base + 17123 offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration), rval); 17124 17125 /* store reset values in SRAM for BS1 */ 17126 reg_cache_base = soc_cmic_bs_reg_cache(unit, 1); 17127 READ_CMIC_BS1_CONFIGr(unit, &rval); 17128 soc_uc_mem_write(unit, reg_cache_base + 17129 offsetof(mos_msg_bs_reg_cache_t, config), rval); 17130 READ_CMIC_BS1_CLK_CTRLr(unit, &rval); 17131 soc_uc_mem_write(unit, reg_cache_base + 17132 offsetof(mos_msg_bs_reg_cache_t, clk_ctrl), rval); 17133 READ_CMIC_BS1_HEARTBEAT_CTRLr(unit, &rval); 17134 soc_uc_mem_write(unit, reg_cache_base + 17135 offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl), rval); 17136 READ_CMIC_BS1_HEARTBEAT_DOWN_DURATIONr(unit, &rval); 17137 soc_uc_mem_write(unit, reg_cache_base + 17138 offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration), rval); 17139 READ_CMIC_BS1_HEARTBEAT_UP_DURATIONr(unit, &rval); 17140 soc_uc_mem_write(unit, reg_cache_base + 17141 offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration), rval); 17142 } 17143 } else { 17144 LOG_CLI((BSL_META_U(unit, 17145 "Leaving BroadSync in holdover\n"))); 17146 17147 if (rev_id == BCM56450_A0_REV_ID) { 17148 /* WAR for reset of TOP_MISC_CONTROL_1.BSn_PLL_CLK_IN_SEL registers */ 17149 /* Note that on A0 there will still be a "hit" if an external reference is used */ 17150 /* But this prevents the wrong value from being persisted after a reset */ 17151 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 50000000); /* 50MHz is default. 0->internal reference */ 17152 /* Reference frequency != 0 => use external reference */ 17153 if (bs_ref_freq != 0) { 17154 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit,&rval)); 17155 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, BS0_PLL_CLK_IN_SELf, 1); 17156 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, BS1_PLL_CLK_IN_SELf, 1); 17157 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 17158 } 17159 } 17160 #endif /* BCM_HITLESS_RESET_SUPPORT */ 17161 } 17162 17163 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 17164 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 17165 TOP_TS_PLL_RST_Lf, 1); 17166 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 17167 TOP_DDR_PLL0_RST_Lf, 1); 17168 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 17169 17170 sal_usleep(to_usec); 17171 17172 if (!SAL_BOOT_SIMULATION) { 17173 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_STATUSr(unit, &rval)); 17174 if (!soc_reg_field_get(unit, TOP_TIME_SYNC_PLL_STATUSr, rval, 17175 TOP_TIME_SYNC_PLL_LOCKf)) { 17176 LOG_ERROR(BSL_LS_SOC_COMMON, 17177 (BSL_META_U(unit, 17178 "TimeSync PLL not locked on unit %d " 17179 "status = 0x%08x\n"), unit, rval)); 17180 } 17181 17182 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_STATUSr(unit, &rval)); 17183 if (!soc_reg_field_get(unit, TOP_BROAD_SYNC0_PLL_STATUSr, rval, 17184 TOP_BROAD_SYNC0_PLL_LOCKf)) { 17185 LOG_ERROR(BSL_LS_SOC_COMMON, 17186 (BSL_META_U(unit, 17187 "BroadSync0 PLL not locked on unit %d " 17188 "status = 0x%08x\n"), unit, rval)); 17189 } 17190 17191 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_STATUSr(unit, &rval)); 17192 if (!soc_reg_field_get(unit, TOP_BROAD_SYNC1_PLL_STATUSr, rval, 17193 TOP_BROAD_SYNC1_PLL_LOCKf)) { 17194 LOG_ERROR(BSL_LS_SOC_COMMON, 17195 (BSL_META_U(unit, 17196 "BroadSync1 PLL not locked on unit %d " 17197 "status = 0x%08x\n"), unit, rval)); 17198 } 17199 17200 if (dev_id != BCM56456_DEVICE_ID) { 17201 SOC_IF_ERROR_RETURN(READ_TOP_DDR_PLL0_STATUSr(unit, &rval)); 17202 if (!soc_reg_field_get(unit, TOP_DDR_PLL0_STATUSr, rval, 17203 DDR_PLL0_LOCKf)) { 17204 LOG_ERROR(BSL_LS_SOC_COMMON, 17205 (BSL_META_U(unit, 17206 "DDR PLL not locked on unit %d " 17207 "status = 0x%08x\n"), unit, rval)); 17208 } 17209 } 17210 } 17211 17212 #if defined(BCM_HITLESS_RESET_SUPPORT) 17213 if (initialize_broadsync) 17214 #endif /* BCM_HITLESS_RESET_SUPPORT */ 17215 { 17216 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_3r(unit, &rval)); 17217 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS0_PLL_POST_RST_Lf, 1); 17218 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS1_PLL_POST_RST_Lf, 1); 17219 WRITE_TOP_SOFT_RESET_REG_3r(unit, rval); 17220 } 17221 17222 /* Check for M, A and Plain versions */ 17223 SOC_IF_ERROR_RETURN(READ_TOP_SWITCH_FEATURE_ENABLE_1r(unit, &rval)); 17224 if (rval & 0x10000000) { 17225 /* BOND_1588_ENABLE */ 17226 SOC_FEATURE_SET(unit, soc_feature_timesync_support); 17227 LOG_CLI((BSL_META_U(unit, 17228 "BOND_1588_ENABLE : " 17229 "enabling soc_feature_timesync_support\n"))); 17230 } 17231 17232 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 17233 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 17234 TOP_TS_PLL_POST_RST_Lf, 1); 17235 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 17236 TOP_DDR_PLL0_POST_RST_Lf, 1); 17237 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 17238 17239 sal_usleep(to_usec); 17240 LOG_CLI((BSL_META_U(unit, 17241 "###################################################\n"))); 17242 if (SOC_INFO(unit).olp_port[0]) { 17243 LOG_CLI((BSL_META_U(unit, 17244 "OLP PORT IS *USED* \n"))); 17245 } else { 17246 LOG_CLI((BSL_META_U(unit, 17247 "OLP PORT IS *NOT USED* \n"))); 17248 SOC_IF_ERROR_RETURN(READ_TOP_SW_BOND_OVRD_CTRL0r(unit, &rval)); 17249 soc_reg_field_set(unit,TOP_SW_BOND_OVRD_CTRL0r,&rval, 17250 OLP_ENABLEf,0); 17251 SOC_IF_ERROR_RETURN(WRITE_TOP_SW_BOND_OVRD_CTRL0r(unit, rval)); 17252 } 17253 LOG_CLI((BSL_META_U(unit, 17254 "###################################################\n"))); 17255 17256 /* 17257 * Bring port blocks out of reset 17258 */ 17259 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 17260 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ0_RST_Lf, 1); 17261 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ1_RST_Lf, 1); 17262 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ2_RST_Lf, 1); 17263 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ3_RST_Lf, 1); 17264 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ4_RST_Lf, 1); 17265 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ5_RST_Lf, 1); 17266 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ6_RST_Lf, 1); 17267 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ7_RST_Lf, 1); 17268 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ8_RST_Lf, 1); 17269 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ9_RST_Lf, 1); 17270 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ10_RST_Lf, 1); 17271 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 17272 17273 sal_usleep(to_usec); 17274 17275 /* Bring network sync out of reset */ 17276 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 17277 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ0_HOTSWAP_RST_Lf, 1); 17278 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ1_HOTSWAP_RST_Lf, 1); 17279 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ2_HOTSWAP_RST_Lf, 1); 17280 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ3_HOTSWAP_RST_Lf, 1); 17281 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ4_HOTSWAP_RST_Lf, 1); 17282 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ5_HOTSWAP_RST_Lf, 1); 17283 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ6_HOTSWAP_RST_Lf, 1); 17284 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ7_HOTSWAP_RST_Lf, 1); 17285 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ8_HOTSWAP_RST_Lf, 1); 17286 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ9_HOTSWAP_RST_Lf, 1); 17287 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ10_HOTSWAP_RST_Lf, 1); 17288 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_NS_RST_Lf, 1); 17289 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 17290 17291 sal_usleep(to_usec); 17292 17293 SOC_IF_ERROR_RETURN(WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0)); 17294 17295 /* enable packing mode based on soc propoerty before mmu is out of reset */ 17296 SOC_IF_ERROR_RETURN(READ_TOP_SW_BOND_OVRD_CTRL1r(unit, &rval)); 17297 17298 mmu_pkg_enable = soc_property_get(unit, spn_MMU_MULTI_PACKETS_PER_CELL, 0); 17299 if(mmu_pkg_enable > ((1 << (soc_reg_field_length(unit, TOP_SW_BOND_OVRD_CTRL1r, 17300 MMU_PACKING_ENABLEf))) - 1)) { 17301 LOG_ERROR(BSL_LS_SOC_COMMON, 17302 (BSL_META_U(unit, 17303 "soc_reset_bcm56450_a0: " 17304 "specified MMU_MULTI_PACKETS_PER_CELL %d exceeds " 17305 "maximum\n"), 17306 mmu_pkg_enable)); 17307 return SOC_E_PARAM; 17308 } 17309 soc_reg_field_set(unit, TOP_SW_BOND_OVRD_CTRL1r, &rval, 17310 MMU_PACKING_ENABLEf, mmu_pkg_enable); 17311 SOC_IF_ERROR_RETURN(WRITE_TOP_SW_BOND_OVRD_CTRL1r(unit, rval)); 17312 17313 /* Bring IP, EP, and MMU blocks out of reset */ 17314 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 17315 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 17316 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 17317 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 17318 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 17319 17320 /* Bring AMAC out of reset */ 17321 soc_amac_init(unit); 17322 17323 sal_usleep(to_usec); 17324 return SOC_E_NONE; 17325 } 17326 #endif /* BCM_KATANA2_SUPPORT */ 17327 17328 #ifdef BCM_METROLITE_SUPPORT 17329 17330 STATIC int 17331 _soc_metrolite_tspll_bspll_config(int unit) 17332 { 17333 uint32 rval; 17334 unsigned ts_ref_freq; 17335 unsigned ts_idx; 17336 17337 /* values for 500MHz TSPLL output-f(vco)=3500, chan=0, f(out)=500*/ 17338 static const soc_pll_param_t ts_pll[] = { 17339 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 17340 {50000000, 70, 0, 1, 7, 0, 2, 3, 1}, 17341 { 0, 70, 0, 1, 7, 0, 2, 3, 1} 17342 }; 17343 17344 unsigned bs_ref_freq; 17345 unsigned bs_idx; 17346 uint32 bs_ndiv_high, bs_ndiv_low; 17347 17348 /* values for 20MHz BSPLL output-f(vco) = 3100,channel = 1,f(out) = 20*/ 17349 static const soc_pll_param_t bs_pll[] = { 17350 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 17351 {50000000, 62, 0, 1, 155, 0, 0, 0, 0}, 17352 { 0, 62, 0, 1, 155, 0, 0, 0, 0} 17353 }; 17354 17355 /* TSPLL configuration: 500MHz TS_CLK from 20/25/32/50MHz refclk */ 17356 /* CMICd divides by 2 on input, so this is a 250MHz clock to TS logic */ 17357 17358 /* 50MHz is default ->internal reference */ 17359 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); 17360 /* Configure TS PLL */ 17361 for (ts_idx = 0; ts_idx < sizeof(ts_pll)/sizeof(ts_pll[0]); ++ts_idx) { 17362 if (ts_pll[ts_idx].ref_freq == ts_ref_freq) { 17363 break; 17364 } 17365 } 17366 if (ts_idx == sizeof(ts_pll)/sizeof(ts_pll[0])) { 17367 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 17368 "Invalid value for PTP_TS_PLL_REF (%u). No default PLL params. \ 17369 Using internal clock \n"), ts_ref_freq)); 17370 /* resetting back to internal clock */ 17371 ts_ref_freq = 0; 17372 ts_idx = ts_idx - 1; 17373 } 17374 17375 /* Put TS, BS PLLs to reset before changing PLL control registers */ 17376 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 17377 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 17378 TOP_TS_PLL_RST_Lf, 0); 17379 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 17380 TOP_TS_PLL_POST_RST_Lf, 0); 17381 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 17382 17383 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_3r(unit, &rval)); 17384 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, 17385 TOP_BS0_PLL_RST_Lf, 0); 17386 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, 17387 TOP_BS1_PLL_RST_Lf, 0); 17388 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, 17389 TOP_BS0_PLL_POST_RST_Lf, 0); 17390 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, 17391 TOP_BS1_PLL_POST_RST_Lf, 0); 17392 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_3r(unit, rval)); 17393 17394 /* TS PLL */ 17395 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r(unit,&rval)); 17396 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r, &rval, FREF_SELf, 17397 (ts_ref_freq != 0)); 17398 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r(unit, rval); 17399 17400 if (SAL_BOOT_QUICKTURN) { 17401 LOG_VERBOSE(BSL_LS_SOC_COMMON, 17402 (BSL_META_U(unit, 17403 "%s:%d Skipping PLL Configuration \n"), __FUNCTION__,__LINE__)); 17404 } else { 17405 LOG_VERBOSE(BSL_LS_SOC_COMMON, 17406 (BSL_META_U(unit, 17407 "%s:%d Continuing PLL Configuration \n"), __FUNCTION__,__LINE__)); 17408 17409 if (SOC_REG_FIELD_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_0r, VCO_DIV2f)) { 17410 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_0r(unit,&rval)); 17411 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_0r, &rval, VCO_DIV2f, 17412 ts_pll[ts_idx].vco_div2); 17413 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_0r(unit, rval); 17414 } 17415 17416 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r)) { 17417 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r(unit,&rval)); 17418 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, KAf, 17419 soc_property_get(unit, spn_PTP_TS_KA, ts_pll[ts_idx].ka)); 17420 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, KIf, 17421 soc_property_get(unit, spn_PTP_TS_KI, ts_pll[ts_idx].ki)); 17422 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, KPf, 17423 soc_property_get(unit, spn_PTP_TS_KP, ts_pll[ts_idx].kp)); 17424 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, 17425 NDIV_FRACf, ts_pll[ts_idx].ndiv_frac); 17426 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r(unit, rval); 17427 } 17428 17429 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r)) { 17430 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r(unit,&rval)); 17431 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r, &rval, NDIV_INTf, 17432 soc_property_get(unit, spn_PTP_TS_PLL_N, 17433 ts_pll[ts_idx].ndiv_int)); 17434 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r(unit, rval); 17435 } 17436 17437 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r)) { 17438 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit,&rval)); 17439 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r, &rval, PDIVf, 17440 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, ts_pll[ts_idx].pdiv)); 17441 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r, &rval, CH0_MDIVf, 17442 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, 17443 ts_pll[ts_idx].mdiv)); 17444 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r, &rval, CH1_MDIVf, 17445 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, 17446 ts_pll[ts_idx].mdiv)); 17447 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit, rval); 17448 } 17449 } 17450 17451 /* 250Mhz TS PLL implies 4ns resolution */ 17452 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); /* clock period in nanoseconds */ 17453 17454 17455 /* Configure Broadsync PLL's */ 17456 /* Both BSPLLs configured the same, for 20MHz output by default */ 17457 17458 /* 50MHz is default. 0->internal reference */ 17459 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 0); 17460 for (bs_idx = 0; bs_idx < sizeof(bs_pll)/sizeof(bs_pll[0]); ++bs_idx) { 17461 if (bs_pll[bs_idx].ref_freq == bs_ref_freq) { 17462 break; 17463 } 17464 } 17465 17466 if (bs_idx == sizeof(bs_pll)/sizeof(bs_pll[0])) { 17467 LOG_ERROR(BSL_LS_SOC_COMMON, 17468 (BSL_META_U(unit, 17469 "Invalid value for PTP_BS_REF (%u). No default PLL params. \ 17470 Resetting to internal clock\n"), bs_ref_freq)); 17471 bs_idx = bs_idx - 1; 17472 bs_ref_freq = 0; 17473 } 17474 17475 /* bs0 pll - set reference clock */ 17476 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_6r(unit,&rval)); 17477 rval = (bs_ref_freq == 0) ? rval : rval | 1 << 18; 17478 WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_6r(unit, rval); 17479 17480 /* bs1 pll - set reference clock */ 17481 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_6r(unit,&rval)); 17482 rval = (bs_ref_freq == 0) ? rval : rval | 1 << 18; 17483 WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_6r(unit, rval); 17484 17485 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit,&rval)); 17486 17487 /* as a signal to upper-level code that the BroadSync is newly initialized 17488 * disable BroadSync0/1 bitclock output. Checked in time.c / 1588 firmware 17489 */ 17490 /* coverity[result_independent_of_operands] */ 17491 SOC_IF_ERROR_RETURN(READ_CMIC_BS0_CONFIGr(unit, &rval)); 17492 soc_reg_field_set(unit, CMIC_BS0_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 17493 WRITE_CMIC_BS0_CONFIGr(unit, rval); 17494 17495 /* coverity[result_independent_of_operands] */ 17496 SOC_IF_ERROR_RETURN(READ_CMIC_BS1_CONFIGr(unit, &rval)); 17497 soc_reg_field_set(unit, CMIC_BS1_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 17498 WRITE_CMIC_BS1_CONFIGr(unit, rval); 17499 17500 /* bs pll - ndiv, mdiv, channel info */ 17501 bs_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, bs_pll[bs_idx].ndiv_int) << 6) | 17502 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs_pll[bs_idx].ndiv_frac) >> 18) & 0x3f)); 17503 17504 bs_ndiv_low = (soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs_pll[bs_idx].ndiv_frac) << 14); 17505 17506 /* bs pll - 0 configuration */ 17507 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 17508 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r, &rval, 17509 BROAD_SYNC0_LCPLL_FBDIV_1f, bs_ndiv_high); 17510 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit, rval); 17511 17512 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 17513 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r, &rval, 17514 BROAD_SYNC0_LCPLL_FBDIV_0f, bs_ndiv_low); 17515 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit, rval); 17516 17517 /* for BS , use channel 0 */ 17518 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit,&rval)); 17519 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r, &rval, 17520 CH1_MDIVf, soc_property_get(unit, spn_PTP_BS_MNDIV, 17521 bs_pll[bs_idx].mdiv)); 17522 WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit, rval); 17523 17524 /* bs pll - 1 configuration */ 17525 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 17526 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r, &rval, 17527 BROAD_SYNC1_LCPLL_FBDIV_1f, bs_ndiv_high); 17528 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit, rval); 17529 17530 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 17531 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r, &rval, 17532 BROAD_SYNC1_LCPLL_FBDIV_0f, bs_ndiv_low); 17533 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit, rval); 17534 17535 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r(unit,&rval)); 17536 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r, &rval, 17537 CH1_MDIVf, soc_property_get(unit, spn_PTP_BS_MNDIV, 17538 bs_pll[bs_idx].mdiv)); 17539 WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r(unit, rval); 17540 17541 return SOC_E_NONE; 17542 } 17543 17544 17545 STATIC int 17546 _soc_metrolite_tspll_bspll_lock(int unit) 17547 { 17548 uint32 rval, to_usec; 17549 17550 /* Wait for pll lock */ 17551 to_usec = 10 * MILLISECOND_USEC; 17552 sal_usleep(to_usec); 17553 if (!SAL_BOOT_SIMULATION) { 17554 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_STATUSr(unit, &rval)); 17555 if (!soc_reg_field_get(unit, TOP_TIME_SYNC_PLL_STATUSr, rval, 17556 TOP_TIME_SYNC_PLL_LOCKf)) { 17557 LOG_WARN(BSL_LS_SOC_COMMON, 17558 (BSL_META_U(unit, 17559 "TimeSync PLL not locked on unit %d " 17560 "status = 0x%08x\n"), unit, rval)); 17561 } 17562 17563 if (SOC_REG_IS_VALID(unit, TOP_BROAD_SYNC0_PLL_STATUSr)) { 17564 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_STATUSr(unit, &rval)); 17565 if (!soc_reg_field_get(unit, TOP_BROAD_SYNC0_PLL_STATUSr, rval, 17566 TOP_BROAD_SYNC0_PLL_LOCKf)) { 17567 LOG_WARN(BSL_LS_SOC_COMMON, 17568 (BSL_META_U(unit, 17569 "BroadSync0 PLL not locked on unit %d " 17570 "status = 0x%08x\n"), unit, rval)); 17571 } 17572 } 17573 17574 if (SOC_REG_IS_VALID(unit, TOP_BROAD_SYNC1_PLL_STATUSr)) { 17575 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_STATUSr(unit, &rval)); 17576 if (!soc_reg_field_get(unit, TOP_BROAD_SYNC1_PLL_STATUSr, rval, 17577 TOP_BROAD_SYNC1_PLL_LOCKf)) { 17578 LOG_WARN(BSL_LS_SOC_COMMON, 17579 (BSL_META_U(unit, 17580 "BroadSync1 PLL not locked on unit %d " 17581 "status = 0x%08x\n"), unit, rval)); 17582 } 17583 } 17584 } 17585 17586 return 0; 17587 } 17588 17589 /* 17590 * Function: 17591 * soc_reset_bcm56270_a0 17592 * Purpose: 17593 * Special reset sequencing for BCM56270 17594 * Setup SBUS block mapping. 17595 */ 17596 STATIC int 17597 soc_reset_bcm56270_a0(int unit) 17598 { 17599 uint32 rval, to_usec; 17600 uint16 dev_id; 17601 uint8 rev_id; 17602 17603 17604 soc_cm_get_id(unit, &dev_id, &rev_id); 17605 17606 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 17607 (10 * MILLISECOND_USEC); 17608 17609 soc_metrolite_sbus_ring_map_config(unit); 17610 sal_usleep(to_usec); 17611 17612 17613 /* Master LCPLL */ 17614 rval = 0x197d2014; 17615 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS0_PLL_CONTROL_1r(unit, rval)); 17616 17617 rval = 0x40004015; 17618 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS0_PLL_CONTROL_2r(unit, rval)); 17619 17620 rval = 0x897004; 17621 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS0_PLL_CONTROL_3r(unit, rval)); 17622 17623 SOC_IF_ERROR_RETURN(READ_TOP_XGXS0_PLL_CONTROL_4r(unit, &rval)); 17624 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17625 CP1f, 0x1); 17626 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17627 CPf, 0x3); 17628 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17629 CZf, 0x3); 17630 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17631 RPf, 0x3); 17632 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17633 RZf, 0); 17634 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17635 ICPf, 0xA); 17636 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17637 VCO_GAINf, 0xF); 17638 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS0_PLL_CONTROL_4r(unit, rval)); 17639 17640 SOC_IF_ERROR_RETURN(READ_TOP_XGXS0_PLL_CONTROL_6r(unit, &rval)); 17641 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_6r, &rval, 17642 CH2_MDIVf, 0x7); 17643 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_6r, &rval, 17644 PDIVf, 0x1); 17645 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS0_PLL_CONTROL_6r(unit, rval)); 17646 17647 17648 /* Broad Sync0 LCPLL */ 17649 rval = 0x00805004; 17650 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r(unit, rval)); 17651 17652 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_6r(unit, 17653 &rval)); 17654 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_6r, &rval, 17655 LDO_CTRLf, 0x22); 17656 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_6r(unit, 17657 rval)); 17658 17659 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r(unit, 17660 &rval)); 17661 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 17662 CP1f, 0x1); 17663 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 17664 CPf, 0x3); 17665 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 17666 CZf, 0x3); 17667 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 17668 RPf, 0x7); 17669 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 17670 RZf, 0x2); 17671 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 17672 ICPf, 0xA); 17673 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 17674 VCO_GAINf, 0xF); 17675 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r(unit, 17676 rval)); 17677 17678 /* Broad Sync1 LCPLL */ 17679 rval = 0x00805004; 17680 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r(unit, rval)); 17681 17682 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_6r(unit, 17683 &rval)); 17684 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_6r, &rval, 17685 LDO_CTRLf, 0x22); 17686 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_6r(unit, 17687 rval)); 17688 17689 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r(unit, 17690 &rval)); 17691 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 17692 CP1f, 0x1); 17693 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 17694 CPf, 0x3); 17695 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 17696 CZf, 0x3); 17697 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 17698 RPf, 0x7); 17699 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 17700 RZf, 0x2); 17701 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 17702 ICPf, 0xA); 17703 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 17704 VCO_GAINf, 0xF); 17705 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r(unit, 17706 rval)); 17707 17708 /* Top Master LCPLL settings */ 17709 rval = 0x7d0; 17710 SOC_IF_ERROR_RETURN(WRITE_TOP_MASTER_LCPLL_FBDIV_CTRL_1r(unit, rval)); 17711 17712 /* End of PLL settings. Togle LCPLL soft reset. */ 17713 SOC_IF_ERROR_RETURN(READ_TOP_LCPLL_SOFT_RESET_REGr(unit, &rval)); 17714 soc_reg_field_set(unit, TOP_LCPLL_SOFT_RESET_REGr, &rval, 17715 LCPLL_SOFT_RESETf, 0x1); 17716 SOC_IF_ERROR_RETURN(WRITE_TOP_LCPLL_SOFT_RESET_REGr(unit, rval)); 17717 17718 sal_usleep(to_usec); 17719 soc_reg_field_set(unit, TOP_LCPLL_SOFT_RESET_REGr, &rval, 17720 LCPLL_SOFT_RESETf, 0x0); 17721 SOC_IF_ERROR_RETURN(WRITE_TOP_LCPLL_SOFT_RESET_REGr(unit, rval)); 17722 17723 sal_usleep(to_usec); 17724 17725 /* Wait for LCPLL lock */ 17726 if (!SAL_BOOT_SIMULATION) { 17727 SOC_IF_ERROR_RETURN(READ_TOP_XGXS0_PLL_STATUSr(unit, &rval)); 17728 17729 if (!soc_reg_field_get(unit, TOP_XGXS0_PLL_STATUSr, rval, TOP_XGPLL0_LOCKf)) { 17730 LOG_VERBOSE(BSL_LS_SOC_COMMON, 17731 (BSL_META_U(unit, 17732 "LCPLL 0 not locked on unit %d " 17733 "status = 0x%08x\n"), unit, rval)); 17734 } 17735 } 17736 17737 17738 17739 /* top_soft_reset_reg */ 17740 /* Bring IP, EP, and MMU blocks out of reset */ 17741 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 17742 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_ARS_RST_Lf, 1); 17743 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_AVS_RST_Lf, 1); 17744 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_NS_RST_Lf, 1); 17745 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 17746 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 17747 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 17748 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ_HOTSWAP_RST_Lf, 1); 17749 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_PM1_RST_Lf, 1); 17750 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_PM0_RST_Lf, 1); 17751 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ_RST_Lf, 1); 17752 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 17753 17754 17755 /* IPIPE and EPIPE configurations */ 17756 SOC_IF_ERROR_RETURN(soc_saber2_hw_reset_control_init(unit)); 17757 17758 /* Metrolite TS and BS PLL configurations */ 17759 SOC_IF_ERROR_RETURN(_soc_metrolite_tspll_bspll_config(unit)); 17760 17761 sal_usleep(to_usec); 17762 17763 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 17764 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 17765 TOP_TS_PLL_RST_Lf, 1); 17766 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 17767 17768 sal_usleep(to_usec); 17769 17770 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 17771 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 17772 TOP_TS_PLL_POST_RST_Lf, 1); 17773 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 17774 17775 /* Bring BS PLL out of reset */ 17776 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_3r(unit, &rval)); 17777 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, 17778 TOP_BS0_PLL_RST_Lf, 1); 17779 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, 17780 TOP_BS1_PLL_RST_Lf, 1); 17781 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, 17782 TOP_BS0_PLL_POST_RST_Lf, 1); 17783 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, 17784 TOP_BS1_PLL_POST_RST_Lf, 1); 17785 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_3r(unit, rval)); 17786 17787 /* Check the lock status of TS and BS PLL */ 17788 _soc_metrolite_tspll_bspll_lock(unit); 17789 17790 return SOC_E_NONE; 17791 } 17792 #endif /* BCM_METROLITE_SUPPORT */ 17793 17794 17795 #ifdef BCM_SABER2_SUPPORT 17796 /* 17797 * Function: 17798 * soc_reset_bcm56260_a0 17799 * Purpose: 17800 * Special reset sequencing for BCM56260 17801 * Setup SBUS block mapping. 17802 */ 17803 STATIC int 17804 soc_reset_bcm56260_a0(int unit) 17805 { 17806 uint32 rval, to_usec; 17807 uint16 dev_id; 17808 uint8 rev_id; 17809 uint32 ddr3_clock_mhz = 0; 17810 uint32 num_rows = 32768; 17811 uint32 ddr3_mem_grade = 0; 17812 uint32 ext_pbmp_count=0; 17813 pbmp_t ext_pbmp; 17814 soc_port_t port; 17815 17816 unsigned ts_ref_freq; 17817 unsigned ts_idx; 17818 17819 /* values for 500MHz TSPLL output-f(vco)=3500, chan=0, f(out)=500*/ 17820 static const soc_pll_param_t ts_pll[] = { 17821 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 17822 {12800000, 625, 0, 2, 8, 0, 2, 3, 1}, 17823 {20000000, 175, 0, 1, 7, 0, 2, 3, 1}, 17824 {25000000, 140, 0, 1, 7, 0, 2, 3, 1}, 17825 {32000000, 125, 0, 1, 8, 0, 2, 3, 1}, 17826 {50000000, 70, 0, 1, 7, 0, 2, 3, 1}, 17827 { 0, 70, 0, 1, 7, 0, 2, 3, 1} 17828 }; 17829 unsigned bs_ref_freq; 17830 unsigned bs_idx; 17831 uint32 bs_ndiv_high, bs_ndiv_low; 17832 /* values for 20MHz BSPLL output-f(vco) = 3100,channel = 1,f(out) = 20*/ 17833 /* 25MHZ have frequency doubler on */ 17834 static const soc_pll_param_t bs_pll[] = { 17835 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 17836 {12800000, 242, 3145728, 1, 155, 0, 0, 0, 0}, 17837 {20000000, 155, 0, 1, 155, 0, 0, 0, 0}, 17838 {25000000, 62, 0, 1, 155, 0, 0, 0, 0}, 17839 {32000000, 96, 14680064, 1, 155, 0, 0, 0, 0}, 17840 {50000000, 62, 0, 1, 155, 0, 0, 0, 0}, 17841 { 0, 62, 0, 1, 155, 0, 0, 0, 0} 17842 }; 17843 17844 soc_cm_get_id(unit, &dev_id, &rev_id); 17845 17846 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 17847 (10 * MILLISECOND_USEC); 17848 17849 /* 17850 * SBUS ring and block number: 17851 * Ring0: cmic -> ip-ep -> cmic 17852 * Ring1: cmic -> mxqport0 -> mxqport1-> mxqport2 -> mxqport3-> cmic 17853 * Ring2: cmic -> gport0 -> gport1 -> gport2 -> cmic 17854 * Ring3: cmic -> otpc -> top -> cmic 17855 * Ring4: cmic -> mmu0 -> mmu1 -> cmic 17856 * Ring5: cmic -> ci0 -> ci1 -> ci2 -> lls -> cmic 17857 * Ring6: cmic -> ces -> cmic 17858 * Ring7: unused 17859 */ 17860 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x66034000); /* block 7 - 0 */ 17861 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x55312222); /* block 15 - 8 */ 17862 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x03103775); /* block 23 - 16 */ 17863 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x0); /* block 31 - 24 */ 17864 17865 SOC_IF_ERROR_RETURN(READ_TOP_XGXS0_PLL_CONTROL_4r(unit, &rval)); 17866 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17867 CH1_CLK_ENABLEf, 0); 17868 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS0_PLL_CONTROL_4r(unit, rval)); 17869 17870 /* Reset all mHost processors */ 17871 SOC_IF_ERROR_RETURN(WRITE_MHOST_0_CR5_RST_CTRLr(unit, 0)); 17872 SOC_IF_ERROR_RETURN(WRITE_RTS_MHOST_1_CR5_RST_CTRLr(unit, 0)); 17873 SOC_IF_ERROR_RETURN(WRITE_RTS_MHOST_2_CR5_RST_CTRLr(unit, 0)); 17874 /*Reset the common UARTs */ 17875 if (!(soc_cm_get_bus_type(unit) & SOC_AXI_DEV_TYPE)) { 17876 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONG_UART0_UART_SRRr(unit, 1)); 17877 } 17878 SOC_IF_ERROR_RETURN(WRITE_CHIPCOMMONG_UART1_UART_SRRr(unit, 1)); 17879 17880 /* Settings for PLLs */ 17881 /* iProc DDR LCPLL */ 17882 /* Configure IPROC DDR PLL only in case of EP mode. */ 17883 if (soc_cm_get_bus_type(unit) & SOC_PCI_DEV_TYPE) { 17884 rval = 0x00805004; 17885 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_DDR_PLL_CTRL_2r(unit, 17886 rval)); 17887 17888 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_IPROC_DDR_PLL_CTRL_6r(unit, 17889 &rval)); 17890 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_6r, &rval, 17891 LDO_CTRLf, 0x22); 17892 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_DDR_PLL_CTRL_6r(unit, 17893 rval)); 17894 17895 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r(unit, 17896 &rval)); 17897 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r, &rval, 17898 CP1f, 0x1); 17899 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r, &rval, 17900 CPf, 0x1); 17901 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r, &rval, 17902 CZf, 0x3); 17903 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r, &rval, 17904 RPf, 0); 17905 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r, &rval, 17906 RZf, 0x2); 17907 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r, &rval, 17908 ICPf, 0x14); 17909 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r, &rval, 17910 VCO_GAINf, 0xF); 17911 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r(unit, 17912 rval)); 17913 17914 /* Issuing Reset to iProc DDR LCPLL with SW override */ 17915 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r(unit, 17916 &rval)); 17917 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r, &rval, 17918 IPROC_DDR_PLL_SW_OVWRf, 0x1); 17919 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r(unit, 17920 rval)); 17921 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r, &rval, 17922 IPROC_DDR_PLL_RESETBf, 0); 17923 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r, &rval, 17924 IPROC_DDR_PLL_POST_RESETBf, 0); 17925 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r(unit, 17926 rval)); 17927 17928 sal_usleep(to_usec); 17929 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r(unit, 17930 &rval)); 17931 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r, &rval, 17932 IPROC_DDR_PLL_RESETBf, 1); 17933 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r(unit, 17934 rval)); 17935 sal_usleep(to_usec); 17936 17937 if (!SAL_BOOT_SIMULATION) { 17938 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_IPROC_DDR_PLL_STATUSr(unit, &rval)); 17939 17940 if (!soc_reg_field_get(unit, IPROC_WRAP_IPROC_DDR_PLL_STATUSr, 17941 rval, IPROC_DDR_PLL_LOCKf)) { 17942 LOG_VERBOSE(BSL_LS_SOC_COMMON, 17943 (BSL_META_U(unit, 17944 "IPROC DDR not locked on unit %d " 17945 "status = 0x%08x\n"), unit, rval)); 17946 } 17947 } 17948 17949 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r(unit, 17950 &rval)); 17951 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r, &rval, 17952 IPROC_DDR_PLL_POST_RESETBf, 1); 17953 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r(unit, 17954 rval)); 17955 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r, &rval, 17956 IPROC_DDR_PLL_SW_OVWRf, 0x0); 17957 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_DDR_PLL_CTRL_0r(unit, 17958 rval)); 17959 } 17960 17961 /* Master LCPLL */ 17962 rval = 0x00805004; 17963 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS0_PLL_CONTROL_3r(unit, rval)); 17964 17965 SOC_IF_ERROR_RETURN(READ_TOP_XGXS0_PLL_CONTROL_7r(unit, &rval)); 17966 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_7r, &rval, 17967 LDO_CTRLf, 0x22); 17968 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS0_PLL_CONTROL_7r(unit, rval)); 17969 17970 SOC_IF_ERROR_RETURN(READ_TOP_XGXS0_PLL_CONTROL_4r(unit, &rval)); 17971 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17972 CP1f, 0x1); 17973 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17974 CPf, 0x3); 17975 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17976 CZf, 0x3); 17977 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17978 RPf, 0x7); 17979 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17980 RZf, 0x2); 17981 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17982 ICPf, 0xA); 17983 soc_reg_field_set(unit, TOP_XGXS0_PLL_CONTROL_4r, &rval, 17984 VCO_GAINf, 0xF); 17985 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS0_PLL_CONTROL_4r(unit, rval)); 17986 17987 /* Serdes LCPLL */ 17988 rval = 0x197d0714; 17989 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS1_PLL_CONTROL_1r(unit, rval)); 17990 17991 rval = 0x40004015; 17992 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS1_PLL_CONTROL_2r(unit, rval)); 17993 17994 rval = 0x897004; 17995 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS1_PLL_CONTROL_3r(unit, rval)); 17996 17997 SOC_IF_ERROR_RETURN(READ_TOP_XGXS1_PLL_CONTROL_7r(unit, &rval)); 17998 soc_reg_field_set(unit, TOP_XGXS1_PLL_CONTROL_7r, &rval, 17999 LDO_CTRLf, 0x22); 18000 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS1_PLL_CONTROL_7r(unit, rval)); 18001 18002 SOC_IF_ERROR_RETURN(READ_TOP_XGXS1_PLL_CONTROL_4r(unit, &rval)); 18003 soc_reg_field_set(unit, TOP_XGXS1_PLL_CONTROL_4r, &rval, 18004 CP1f, 0x1); 18005 soc_reg_field_set(unit, TOP_XGXS1_PLL_CONTROL_4r, &rval, 18006 CPf, 0x3); 18007 soc_reg_field_set(unit, TOP_XGXS1_PLL_CONTROL_4r, &rval, 18008 CZf, 0x3); 18009 soc_reg_field_set(unit, TOP_XGXS1_PLL_CONTROL_4r, &rval, 18010 RPf, 0x3); 18011 soc_reg_field_set(unit, TOP_XGXS1_PLL_CONTROL_4r, &rval, 18012 RZf, 0); 18013 soc_reg_field_set(unit, TOP_XGXS1_PLL_CONTROL_4r, &rval, 18014 ICPf, 0xA); 18015 soc_reg_field_set(unit, TOP_XGXS1_PLL_CONTROL_4r, &rval, 18016 VCO_GAINf, 0xF); 18017 SOC_IF_ERROR_RETURN(WRITE_TOP_XGXS1_PLL_CONTROL_4r(unit, rval)); 18018 18019 /* Both BSPLLs configured the same, for 20MHz output by default */ 18020 /* 50MHz is default. 0->internal reference */ 18021 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 0); 18022 18023 /* Set BS_PLL_CLK_IN_SEL based on reference frequency. If it is 0, use the 18024 * internal reference 18025 */ 18026 for (bs_idx = 0; bs_idx < sizeof(bs_pll)/sizeof(bs_pll[0]); ++bs_idx) { 18027 if (bs_pll[bs_idx].ref_freq == bs_ref_freq) { 18028 break; 18029 } 18030 } 18031 18032 if (bs_idx == sizeof(bs_pll)/sizeof(bs_pll[0])) { 18033 LOG_ERROR(BSL_LS_SOC_COMMON, 18034 (BSL_META_U(unit, 18035 "Invalid value for PTP_BS_REF (%u). No default PLL params. Resetting to internal clock\n"), 18036 bs_ref_freq)); 18037 bs_idx = bs_idx - 1; 18038 } 18039 18040 /* bs pll - set reference clock */ 18041 18042 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit,&rval)); 18043 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, BS0_PLL_CLK_IN_SELf, 18044 (bs_ref_freq != 0)); 18045 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, BS1_PLL_CLK_IN_SELf, 18046 (bs_ref_freq != 0)); 18047 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 18048 18049 bs_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, bs_pll[bs_idx].ndiv_int) << 6) | 18050 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs_pll[bs_idx].ndiv_frac) >> 18) & 0x3f)); 18051 18052 bs_ndiv_low = (soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs_pll[bs_idx].ndiv_frac) << 14); 18053 18054 /* Broad Sync0 LCPLL */ 18055 rval = 0x00805004; 18056 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r(unit, rval)); 18057 18058 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_6r(unit, 18059 &rval)); 18060 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_6r, &rval, 18061 LDO_CTRLf, 0x22); 18062 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_6r(unit, 18063 rval)); 18064 18065 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r(unit, 18066 &rval)); 18067 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 18068 CP1f, 0x1); 18069 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 18070 CPf, 0x3); 18071 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 18072 CZf, 0x3); 18073 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 18074 RPf, 0x7); 18075 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 18076 RZf, 0x2); 18077 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 18078 ICPf, 0xA); 18079 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r, &rval, 18080 VCO_GAINf, 0xF); 18081 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4r(unit, 18082 rval)); 18083 18084 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 18085 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r, &rval, 18086 BROAD_SYNC0_LCPLL_FBDIV_1f, bs_ndiv_high); 18087 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit, rval); 18088 18089 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 18090 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r, &rval, 18091 BROAD_SYNC0_LCPLL_FBDIV_0f, bs_ndiv_low); 18092 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit, rval); 18093 18094 /* for BS , use channel 1 */ 18095 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit,&rval)); 18096 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r, &rval, 18097 CH1_MDIVf, soc_property_get(unit, spn_PTP_BS_MNDIV, 18098 bs_pll[bs_idx].mdiv)); 18099 WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit, rval); 18100 18101 /* for 25MHz, set bit 13 to enable frequency doubler */ 18102 if (bs_ref_freq == 25000000) { 18103 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r(unit,&rval)); 18104 rval |= (1<<13); 18105 WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r(unit, rval); 18106 } 18107 18108 /* Broad Sync1 LCPLL */ 18109 rval = 0x00805004; 18110 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r(unit, rval)); 18111 18112 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_6r(unit, 18113 &rval)); 18114 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_6r, &rval, 18115 LDO_CTRLf, 0x22); 18116 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_6r(unit, 18117 rval)); 18118 18119 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r(unit, 18120 &rval)); 18121 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 18122 CP1f, 0x1); 18123 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 18124 CPf, 0x3); 18125 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 18126 CZf, 0x3); 18127 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 18128 RPf, 0x7); 18129 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 18130 RZf, 0x2); 18131 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 18132 ICPf, 0xA); 18133 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r, &rval, 18134 VCO_GAINf, 0xF); 18135 SOC_IF_ERROR_RETURN(WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4r(unit, 18136 rval)); 18137 18138 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 18139 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r, &rval, 18140 BROAD_SYNC1_LCPLL_FBDIV_1f, bs_ndiv_high); 18141 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit, rval); 18142 18143 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 18144 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r, &rval, 18145 BROAD_SYNC1_LCPLL_FBDIV_0f, bs_ndiv_low); 18146 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit, rval); 18147 18148 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r(unit,&rval)); 18149 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r, &rval, 18150 CH1_MDIVf, soc_property_get(unit, spn_PTP_BS_MNDIV, 18151 bs_pll[bs_idx].mdiv)); 18152 WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r(unit, rval); 18153 18154 /* for 25MHz, set bit 13 to enable frequency doubler */ 18155 if (bs_ref_freq == 25000000) { 18156 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r(unit,&rval)); 18157 rval |= (1<<13); 18158 WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r(unit, rval); 18159 } 18160 18161 /* Top Serdes LCPLL settings */ 18162 rval = 0; 18163 SOC_IF_ERROR_RETURN(WRITE_TOP_SERDES_LCPLL_FBDIV_CTRL_0r(unit, rval)); 18164 rval = 0x7d0; 18165 SOC_IF_ERROR_RETURN(WRITE_TOP_SERDES_LCPLL_FBDIV_CTRL_1r(unit, rval)); 18166 18167 /* Top Master LCPLL settings to default reset values */ 18168 rval = 0; 18169 SOC_IF_ERROR_RETURN(WRITE_TOP_MASTER_LCPLL_FBDIV_CTRL_0r(unit, rval)); 18170 rval = 0xfa0; 18171 SOC_IF_ERROR_RETURN(WRITE_TOP_MASTER_LCPLL_FBDIV_CTRL_1r(unit, rval)); 18172 18173 /* End of PLL settings. Togle LCPLL soft reset. */ 18174 SOC_IF_ERROR_RETURN(READ_TOP_LCPLL_SOFT_RESET_REGr(unit, &rval)); 18175 soc_reg_field_set(unit, TOP_LCPLL_SOFT_RESET_REGr, &rval, 18176 LCPLL_SOFT_RESETf, 0x1); 18177 SOC_IF_ERROR_RETURN(WRITE_TOP_LCPLL_SOFT_RESET_REGr(unit, rval)); 18178 18179 sal_usleep(to_usec); 18180 soc_reg_field_set(unit, TOP_LCPLL_SOFT_RESET_REGr, &rval, 18181 LCPLL_SOFT_RESETf, 0x0); 18182 SOC_IF_ERROR_RETURN(WRITE_TOP_LCPLL_SOFT_RESET_REGr(unit, rval)); 18183 18184 sal_usleep(to_usec); 18185 18186 /* Wait for LCPLL lock */ 18187 if (!SAL_BOOT_SIMULATION) { 18188 SOC_IF_ERROR_RETURN(READ_TOP_XGXS0_PLL_STATUSr(unit, &rval)); 18189 18190 if (!soc_reg_field_get(unit, TOP_XGXS0_PLL_STATUSr, rval, TOP_XGPLL0_LOCKf)) { 18191 LOG_VERBOSE(BSL_LS_SOC_COMMON, 18192 (BSL_META_U(unit, 18193 "LCPLL 0 not locked on unit %d " 18194 "status = 0x%08x\n"), unit, rval)); 18195 } 18196 SOC_IF_ERROR_RETURN(READ_TOP_XGXS1_PLL_STATUSr(unit, &rval)); 18197 if (!soc_reg_field_get(unit, TOP_XGXS1_PLL_STATUSr, rval, TOP_XGPLL1_LOCKf)) { 18198 LOG_WARN(BSL_LS_SOC_COMMON, 18199 (BSL_META_U(unit, 18200 "LCPLL 1 not locked on unit %d " 18201 "status = 0x%08x\n"), unit, rval)); 18202 } 18203 } 18204 18205 18206 /* Configure TS PLL */ 18207 /* 50MHz is default ->internal reference */ 18208 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); 18209 18210 /* Configure TS PLL */ 18211 for (ts_idx = 0; ts_idx < sizeof(ts_pll)/sizeof(ts_pll[0]); ++ts_idx) { 18212 if (ts_pll[ts_idx].ref_freq == ts_ref_freq) { 18213 break; 18214 } 18215 } 18216 if (ts_idx == sizeof(ts_pll)/sizeof(ts_pll[0])) { 18217 LOG_ERROR(BSL_LS_SOC_COMMON, 18218 (BSL_META_U(unit, 18219 "Invalid value for PTP_TS_PLL_REF (%u). No default PLL params. Using internal clock \n"), 18220 ts_ref_freq)); 18221 /* resetting back to internal clock */ 18222 ts_idx = ts_idx - 1; 18223 } 18224 18225 18226 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit,&rval)); 18227 if (soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0) == 0) { 18228 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, TS_PLL_CLK_IN_SELf, 0); 18229 } else { 18230 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, TS_PLL_CLK_IN_SELf, 1); 18231 } 18232 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 18233 18234 /* 250Mhz TS PLL implies 4ns resolution */ 18235 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r)) { 18236 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r(unit,&rval)); 18237 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, 18238 NDIV_FRACf, ts_pll[ts_idx].ndiv_frac); 18239 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r(unit, rval); 18240 } 18241 18242 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r)) { 18243 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit,&rval)); 18244 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r, &rval, PDIVf, 18245 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, ts_pll[ts_idx].pdiv)); 18246 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit, rval); 18247 } 18248 18249 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r)) { 18250 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r(unit,&rval)); 18251 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r, &rval, NDIV_INTf, 18252 soc_property_get(unit, spn_PTP_TS_PLL_N, 18253 ts_pll[ts_idx].ndiv_int)); 18254 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r(unit, rval); 18255 } 18256 18257 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r)) { 18258 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit,&rval)); 18259 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r, &rval, CH0_MDIVf, 18260 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, 18261 ts_pll[ts_idx].mdiv)); 18262 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit, rval); 18263 } 18264 18265 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r)) { 18266 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit,&rval)); 18267 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r, &rval, CH1_MDIVf, 18268 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, 18269 ts_pll[ts_idx].mdiv)); 18270 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit, rval); 18271 } 18272 18273 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); /* clock period in nanoseconds */ 18274 18275 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 18276 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_RST_Lf, 1); 18277 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 18278 18279 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_3r(unit, &rval)); 18280 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS0_PLL_RST_Lf, 1); 18281 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS1_PLL_RST_Lf, 1); 18282 WRITE_TOP_SOFT_RESET_REG_3r(unit, rval); 18283 18284 sal_usleep(to_usec); 18285 18286 if (!SAL_BOOT_SIMULATION) { 18287 if (soc_feature(unit, soc_feature_ces)) { 18288 SOC_IF_ERROR_RETURN(READ_TOP_CES_PLL_STATUSr(unit, &rval)); 18289 if (!soc_reg_field_get(unit, TOP_CES_PLL_STATUSr, rval, TOP_CES_PLL_LOCKf)) { 18290 LOG_WARN(BSL_LS_SOC_COMMON, 18291 (BSL_META_U(unit, 18292 "CES PLL not locked on unit %d " 18293 "status = 0x%08x\n"), unit, rval)); 18294 } 18295 } 18296 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_STATUSr(unit, &rval)); 18297 if (!soc_reg_field_get(unit, TOP_TIME_SYNC_PLL_STATUSr, rval, 18298 TOP_TIME_SYNC_PLL_LOCKf)) { 18299 LOG_WARN(BSL_LS_SOC_COMMON, 18300 (BSL_META_U(unit, 18301 "TimeSync PLL not locked on unit %d " 18302 "status = 0x%08x\n"), unit, rval)); 18303 } 18304 18305 if (SOC_REG_IS_VALID(unit, TOP_BROAD_SYNC0_PLL_STATUSr)) { 18306 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_STATUSr(unit, &rval)); 18307 if (!soc_reg_field_get(unit, TOP_BROAD_SYNC0_PLL_STATUSr, rval, 18308 TOP_BROAD_SYNC0_PLL_LOCKf)) { 18309 LOG_WARN(BSL_LS_SOC_COMMON, 18310 (BSL_META_U(unit, 18311 "BroadSync0 PLL not locked on unit %d " 18312 "status = 0x%08x\n"), unit, rval)); 18313 } 18314 } 18315 18316 if (SOC_REG_IS_VALID(unit, TOP_BROAD_SYNC1_PLL_STATUSr)) { 18317 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_STATUSr(unit, &rval)); 18318 if (!soc_reg_field_get(unit, TOP_BROAD_SYNC1_PLL_STATUSr, rval, 18319 TOP_BROAD_SYNC1_PLL_LOCKf)) { 18320 LOG_WARN(BSL_LS_SOC_COMMON, 18321 (BSL_META_U(unit, 18322 "BroadSync1 PLL not locked on unit %d " 18323 "status = 0x%08x\n"), unit, rval)); 18324 } 18325 } 18326 } 18327 18328 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 18329 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_POST_RST_Lf, 1); 18330 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 18331 18332 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_3r(unit, &rval)); 18333 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS0_PLL_POST_RST_Lf, 1); 18334 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_3r, &rval, TOP_BS1_PLL_POST_RST_Lf, 1); 18335 WRITE_TOP_SOFT_RESET_REG_3r(unit, rval); 18336 18337 18338 /* Disable differential testout buffers to save power */ 18339 SOC_IF_ERROR_RETURN(READ_TOP_CORE_PLL0_CTRL_REGISTER_1r(unit, &rval)); 18340 soc_reg_field_set(unit, TOP_CORE_PLL0_CTRL_REGISTER_1r, &rval, 18341 TESTOUT_ENf, 0); 18342 SOC_IF_ERROR_RETURN(WRITE_TOP_CORE_PLL0_CTRL_REGISTER_1r(unit, rval)); 18343 18344 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r(unit, &rval)); 18345 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r, &rval, 18346 TESTOUT_ENf, 0); 18347 SOC_IF_ERROR_RETURN(WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_1r(unit, rval)); 18348 18349 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_IPROC_PLL_CTRL_1r(unit, &rval)); 18350 soc_reg_field_set(unit, IPROC_WRAP_IPROC_PLL_CTRL_1r, &rval, 18351 TESTOUT_ENf, 0); 18352 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_PLL_CTRL_1r(unit, rval)); 18353 18354 /* SKU specific power savings */ 18355 if ((dev_id == BCM56461_DEVICE_ID) || (dev_id == BCM56466_DEVICE_ID) || 18356 (dev_id == BCM56261_DEVICE_ID) || (dev_id == BCM56266_DEVICE_ID)) { 18357 /* Disable USB PHY in CPU disabled SKUs */ 18358 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_IPROC_STRAP_CTRLr(unit, &rval)); 18359 soc_reg_field_set(unit, IPROC_WRAP_IPROC_STRAP_CTRLr, &rval, 18360 DISABLE_USB2Hf, 1); 18361 soc_reg_field_set(unit, IPROC_WRAP_IPROC_STRAP_CTRLr, &rval, 18362 DISABLE_USB2Df, 1); 18363 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_STRAP_CTRLr(unit, rval)); 18364 18365 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_USBPHY_CTRL_0r(unit, &rval)); 18366 soc_reg_field_set(unit, IPROC_WRAP_USBPHY_CTRL_0r, &rval, RESETBf, 0); 18367 soc_reg_field_set(unit, IPROC_WRAP_USBPHY_CTRL_0r, &rval, 18368 PLL_RESETBf, 0); 18369 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_USBPHY_CTRL_0r(unit, rval)); 18370 18371 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r(unit, 18372 &rval)); 18373 soc_reg_field_set(unit, IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r, &rval, 18374 CH2_CLK_ENABLEf, 1); 18375 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_DDR_PLL_CTRL_3r(unit, 18376 rval)); 18377 } 18378 18379 /* Disable IPROC DDR when Ext packet buffer is disabled. 18380 * But keep iproc enabled when iHost is supported. 18381 */ 18382 if ((dev_id == BCM56466_DEVICE_ID) || (dev_id == BCM56266_DEVICE_ID)) { 18383 SOC_IF_ERROR_RETURN(READ_IPROC_WRAP_IPROC_STRAP_CTRLr(unit, &rval)); 18384 soc_reg_field_set(unit, IPROC_WRAP_IPROC_STRAP_CTRLr, &rval, 18385 DISABLE_IPROC_DDRf, 1); 18386 SOC_IF_ERROR_RETURN(WRITE_IPROC_WRAP_IPROC_STRAP_CTRLr(unit, rval)); 18387 } 18388 18389 /* Disable iHost in SKUs that does not support iHost */ 18390 if ((dev_id == BCM56461_DEVICE_ID) || (dev_id == BCM56466_DEVICE_ID) || 18391 (dev_id == BCM56261_DEVICE_ID) || (dev_id == BCM56266_DEVICE_ID)) { 18392 18393 SOC_IF_ERROR_RETURN(READ_DMU_PCU_IPROC_CONTROLr(unit, &rval)); 18394 /* Check if iHost is not powered down, then power it down */ 18395 if (soc_reg_field_get(unit, 18396 DMU_PCU_IPROC_CONTROLr, rval, IHOST_PWRCTRLI0f) != 0x3) 18397 { 18398 18399 SOC_IF_ERROR_RETURN(READ_IHOST_SCU_POWER_STATUSr(unit, &rval)); 18400 soc_reg_field_set(unit, IHOST_SCU_POWER_STATUSr, &rval, 18401 CPU0_STATUSf, 3); 18402 SOC_IF_ERROR_RETURN(WRITE_IHOST_SCU_POWER_STATUSr(unit, rval)); 18403 18404 SOC_IF_ERROR_RETURN(READ_DMU_PCU_IPROC_CONTROLr(unit, &rval)); 18405 soc_reg_field_set(unit, DMU_PCU_IPROC_CONTROLr, &rval, 18406 IHOST_PWRCTRLI0f, 3); 18407 SOC_IF_ERROR_RETURN(WRITE_DMU_PCU_IPROC_CONTROLr(unit, rval)); 18408 18409 SOC_IF_ERROR_RETURN(READ_CRU_CPU0_POWERDOWNr(unit, &rval)); 18410 soc_reg_field_set(unit, CRU_CPU0_POWERDOWNr, &rval, 18411 WAIT_FOR_WFIf, 1); 18412 soc_reg_field_set(unit, CRU_CPU0_POWERDOWNr, &rval, 18413 START_CPU0_POWERDOWN_SEQf, 1); 18414 SOC_IF_ERROR_RETURN(WRITE_CRU_CPU0_POWERDOWNr(unit, rval)); 18415 } 18416 } 18417 /* Bring port blocks out of reset */ 18418 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 18419 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ0_RST_Lf, 1); 18420 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ1_RST_Lf, 1); 18421 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ2_RST_Lf, 1); 18422 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ3_RST_Lf, 1); 18423 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ4_RST_Lf, 1); 18424 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ5_RST_Lf, 1); 18425 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_PM_RST_Lf, 1); 18426 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 18427 18428 sal_usleep(to_usec); 18429 /* Bring network sync out of reset */ 18430 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 18431 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ0_HOTSWAP_RST_Lf, 1); 18432 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ1_HOTSWAP_RST_Lf, 1); 18433 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ2_HOTSWAP_RST_Lf, 1); 18434 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ3_HOTSWAP_RST_Lf, 1); 18435 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ4_HOTSWAP_RST_Lf, 1); 18436 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MXQ5_HOTSWAP_RST_Lf, 1); 18437 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_PM_HOTSWAP_RST_Lf, 1); 18438 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_NS_RST_Lf, 1); 18439 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 18440 18441 sal_usleep(to_usec); 18442 18443 /* coverity[result_independent_of_operands] */ 18444 SOC_IF_ERROR_RETURN(WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0)); 18445 18446 SOC_IF_ERROR_RETURN(READ_TOP_MMU_DDR_PHY_CTRLr(unit, &rval)); 18447 soc_reg_field_set(unit, TOP_MMU_DDR_PHY_CTRLr, &rval, I_PWRONIN_PHYf, 1); 18448 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_DDR_PHY_CTRLr(unit, rval)); 18449 sal_usleep(1000); 18450 18451 SOC_IF_ERROR_RETURN(READ_TOP_MMU_DDR_PHY_CTRLr(unit, &rval)); 18452 soc_reg_field_set(unit, TOP_MMU_DDR_PHY_CTRLr, &rval, I_PWROKIN_PHYf, 1); 18453 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_DDR_PHY_CTRLr(unit, rval)); 18454 sal_usleep(1000); 18455 18456 SOC_IF_ERROR_RETURN(READ_TOP_MMU_DDR_PHY_CTRLr(unit, &rval)); 18457 soc_reg_field_set(unit, TOP_MMU_DDR_PHY_CTRLr, &rval, I_ISO_PHY_DFIf, 1); 18458 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_DDR_PHY_CTRLr(unit, rval)); 18459 sal_usleep(1000); 18460 18461 rval = 0; 18462 soc_reg_field_set(unit, TOP_CI_PHY_CONTROLr, &rval, DDR_RESET_Nf, 1); 18463 SOC_IF_ERROR_RETURN(WRITE_TOP_CI_PHY_CONTROLr(unit, rval)); 18464 sal_usleep(1000); 18465 18466 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 18467 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_AVS_RST_Lf, 1); 18468 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_OOBFC0_RST_Lf, 1); 18469 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_OOBFC1_RST_Lf, 1); 18470 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 18471 18472 /* Bring IP, EP, and MMU blocks out of reset */ 18473 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 18474 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 18475 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 18476 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 18477 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 18478 18479 /* IPIPE and EPIPE configurations */ 18480 SOC_IF_ERROR_RETURN(soc_saber2_hw_reset_control_init(unit)); 18481 18482 sal_usleep(to_usec); 18483 if (soc_feature(unit, soc_feature_ddr3)) { 18484 ddr3_clock_mhz = 800; 18485 18486 SOC_DDR3_NUM_COLUMNS(unit) = soc_property_get(unit, spn_EXT_RAM_COLUMNS, 18487 1024); 18488 SOC_DDR3_NUM_BANKS(unit) = soc_property_get(unit,spn_EXT_RAM_BANKS, 8); 18489 SOC_DDR3_NUM_MEMORIES(unit) = soc_property_get(unit,spn_EXT_RAM_PRESENT, 18490 0); 18491 SOC_DDR3_NUM_ROWS(unit) = soc_property_get(unit,spn_EXT_RAM_ROWS, 18492 num_rows); 18493 SOC_DDR3_CLOCK_MHZ(unit) = soc_property_get(unit, spn_DDR3_CLOCK_MHZ, 18494 ddr3_clock_mhz); 18495 SOC_DDR3_MEM_GRADE(unit) = soc_property_get(unit, spn_DDR3_MEM_GRADE, 18496 ddr3_mem_grade); 18497 18498 ext_pbmp = soc_property_get_pbmp(unit, spn_PBMP_EXT_MEM, 0); 18499 SOC_PBMP_COUNT(ext_pbmp, ext_pbmp_count); 18500 if (SOC_DDR3_NUM_MEMORIES(unit)) { 18501 SOC_IF_ERROR_RETURN(soc_sb2_and28_dram_init_reset(unit)); 18502 } 18503 } 18504 18505 for (port = 1; port < 24; port +=4 ) { 18506 if (SOC_PORT_VALID(unit, port)) { 18507 SOC_IF_ERROR_RETURN(READ_XPORT_XGXS_CTRLr(unit, port, &rval)); 18508 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, PWRDWNf, 0); 18509 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, port, rval)); 18510 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, RSTB_HWf, 1); 18511 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, port, rval)); 18512 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, IDDQf, 0); 18513 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, port, rval)); 18514 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, RSTB_PLLf, 1); 18515 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, port, rval)); 18516 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, RSTB_MDIOREGSf, 1); 18517 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, port, rval)); 18518 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, TXD1G_FIFO_RSTBf, 0xf); 18519 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, port, rval)); 18520 soc_reg_field_set(unit, XPORT_XGXS_CTRLr, &rval, TXD10G_FIFO_RSTBf, 1); 18521 SOC_IF_ERROR_RETURN(WRITE_XPORT_XGXS_CTRLr(unit, port, rval)); 18522 } 18523 } 18524 18525 return SOC_E_NONE; 18526 } 18527 #endif /* BCM_SABER2_SUPPORT */ 18528 18529 int soc_esw_schan_fifo_init(int unit, int ccmdma) 18530 { 18531 int rval = SOC_E_NONE; 18532 18533 #ifdef BCM_CMICX_SUPPORT 18534 if (soc_feature(unit, soc_feature_cmicx)) { 18535 soc_control_t *soc; 18536 soc_schan_fifo_config_t cfg; 18537 int rval; 18538 #ifdef BCM_SOC_ASYNC_SUPPORT 18539 soc_async_prop_t prop; 18540 18541 prop.prio = 40; 18542 prop.q_size = 50; 18543 prop.type = p_schan_fifo; 18544 prop.threads = 1; 18545 #endif 18546 soc = SOC_CONTROL(unit); 18547 soc_cmic_intr_all_disable(unit); 18548 18549 /* Initialize schan fifo */ 18550 /* Read properties */ 18551 soc->schanFifoTimeout = 18552 soc_property_get(unit, spn_SCHANFIFO_TIMEOUT_USEC, 18553 30000000); 18554 soc->schanFifoIntrEnb = 18555 soc_property_get(unit, spn_SCHANFIFO_INTR_ENABLE, 1); 18556 18557 cfg.intrEnb = soc->schanFifoIntrEnb; 18558 cfg.dma = ccmdma; 18559 cfg.timeout = soc->schanFifoTimeout; 18560 18561 #ifdef BCM_SOC_ASYNC_SUPPORT 18562 rval = soc_schan_fifo_init(unit, &prop, &cfg); 18563 #else 18564 rval = soc_schan_fifo_init(unit, NULL, &cfg); 18565 #endif 18566 if (rval != SOC_E_NONE) { 18567 LOG_ERROR(BSL_LS_SOC_COMMON, 18568 (BSL_META_U(unit, 18569 "Schan FIFO Init failed \n"))); 18570 return SOC_E_FAIL; 18571 } 18572 } 18573 #endif /* BCM_CMICX_SUPPORT */ 18574 18575 return rval; 18576 18577 } 18578 18579 18580 /* 18581 * Function: 18582 * soc_reset 18583 * Purpose: 18584 * Reset the unit via the CMIC CPS reset function. 18585 */ 18586 18587 int 18588 soc_reset(int unit) 18589 { 18590 uint16 dev_id; 18591 uint8 rev_id; 18592 int spl; 18593 char *mode = NULL; 18594 18595 if (SOC_IS_RCPU_ONLY(unit)) { 18596 /* Skip reset process for rcpu only unit */ 18597 return SOC_E_NONE; 18598 } 18599 18600 /* 18601 * Configure endian mode in case the system just came out of reset. 18602 */ 18603 18604 soc_endian_config(unit); 18605 soc_pci_ep_config(unit, -1); 18606 18607 /* 18608 * Configure bursting in case the system just came out of reset. 18609 */ 18610 18611 soc_pci_burst_enable(unit); 18612 18613 18614 /* 18615 * After setting the reset bit, StrataSwitch PCI registers cannot be 18616 * accessed for 300 cycles or the CMIC will hang. This is mostly of 18617 * concern on the Quickturn simulation but we leave plenty of time. 18618 */ 18619 18620 soc_cm_get_id(unit, &dev_id, &rev_id); 18621 18622 /* Suspend IRQ polling while resetting */ 18623 soc_ipoll_pause(unit); 18624 18625 if (soc_property_get(unit, spn_SOC_SKIP_RESET, 0)) { 18626 LOG_WARN(BSL_LS_SOC_COMMON, 18627 (BSL_META_U(unit, 18628 "soc_init: skipping hard reset\n"))); 18629 } 18630 else 18631 { 18632 /* CPS reset problematic on PLI, the amount of time 18633 * to wait is not constant and may vary from machine 18634 * to machine. So, don't do it. 18635 */ 18636 if (!SAL_BOOT_RTLSIM) { 18637 #ifdef BCM_TOMAHAWK_SUPPORT 18638 if (SOC_IS_TOMAHAWKX(unit) && !SOC_IS_TOMAHAWK3(unit)) { 18639 uint32 rval, xrval; 18640 int bn = 0; 18641 uint32 top_tsc_enable_default = 0xffffffff; 18642 18643 /*CMIC_SBUS_RING_MAP_0_7 is used to check whether SBUS was configured or not*/ 18644 SOC_IF_ERROR_RETURN(READ_CMIC_SBUS_RING_MAP_0_7r(unit, &rval)); 18645 18646 /* Adjust TOP_TSC_ENABLE enable/disable status only when SBUS configured 18647 and the register is ready*/ 18648 if ((rval != 0) && ((READ_TOP_TSC_ENABLEr(unit, &rval)) == SOC_E_NONE)) { 18649 /*Calculate different bits number between old and ASIC default value*/ 18650 xrval = rval ^ top_tsc_enable_default; 18651 for (bn = 0; xrval != 0; bn++) { 18652 xrval &= (xrval - 1); 18653 } 18654 18655 /*Do two steps configuration change for the case of different bits number beyond 10*/ 18656 if (bn > 10) { 18657 /*Change half of those different bits to ASIC default value*/ 18658 bn /= 2; 18659 xrval = rval ^ top_tsc_enable_default; 18660 do { 18661 xrval &= (xrval-1); 18662 } while (bn-- > 0); 18663 18664 xrval ^= top_tsc_enable_default; 18665 SOC_IF_ERROR_RETURN(WRITE_TOP_TSC_ENABLEr(unit, xrval)); 18666 sal_usleep(100000); 18667 } 18668 #ifdef BCM_TOMAHAWK2_SUPPORT 18669 /*TH2 has 64 port macros*/ 18670 if (SOC_REG_IS_VALID(unit, TOP_TSC_ENABLE_1r)){ 18671 SOC_IF_ERROR_RETURN(READ_TOP_TSC_ENABLE_1r(unit, &rval)); 18672 xrval = rval ^ top_tsc_enable_default; 18673 for (bn = 0; xrval != 0; bn++) { 18674 xrval &= (xrval - 1); 18675 } 18676 18677 /*Do two steps configuration change for the case of different bits number beyond 10*/ 18678 if (bn > 10) { 18679 /*Change half of those different bits to ASIC default value*/ 18680 bn /= 2; 18681 xrval = rval ^ top_tsc_enable_default; 18682 do { 18683 xrval &= (xrval-1); 18684 } while (bn-- > 0); 18685 18686 xrval ^= top_tsc_enable_default; 18687 SOC_IF_ERROR_RETURN(WRITE_TOP_TSC_ENABLE_1r(unit, xrval)); 18688 sal_usleep(100000); 18689 } 18690 } 18691 #endif /*BCM_TOMAHAWK2_SUPPORT*/ 18692 } 18693 } 18694 #endif 18695 18696 #ifdef BCM_HERCULES_SUPPORT 18697 #ifdef BCM_HERCULES15_SUPPORT 18698 /* special processing on 5675/6A0 with disabled ports */ 18699 if (SOC_IS_HERCULES15(unit) && 18700 rev_id == BCM5675_A0_REV_ID && 18701 !SAL_BOOT_QUICKTURN && 18702 SOC_PBMP_WORD_GET(PBMP_ALL(unit), 0) != 0x1ff) { 18703 soc_reset_bcm5675_a0(unit, dev_id); 18704 } 18705 #endif 18706 if (SOC_IS_HERCULES(unit)) { 18707 /* Set clock enable on active ports before soft reset */ 18708 WRITE_CMIC_CLK_ENABLEr(unit, 18709 SOC_PBMP_WORD_GET(PBMP_ALL(unit), 0)); 18710 } 18711 #endif 18712 /* Block interrupts while setting the busy flag */ 18713 spl = sal_splhi(); 18714 SOC_CONTROL(unit)->soc_flags |= SOC_F_BUSY; 18715 18716 /* Unblock interrupts */ 18717 sal_spl(spl); 18718 18719 #ifdef BCM_CMICM_SUPPORT 18720 if (soc_feature(unit, soc_feature_cmicm)) { 18721 #ifdef BCM_TOMAHAWK_SUPPORT 18722 /* For TH+/TH2 the behaviour of IDDQ field of CLPORT_XGXS0_CTRL_REG has changed */ 18723 /* Cannot reset all falcon cores at the same time, try to reset 8 cores at a time */ 18724 if (soc_feature(unit, soc_feature_iddq_new_default)) { 18725 uint32 rval; 18726 /*CMIC_SBUS_RING_MAP_0_7 is used to check whether SBUS was configured or not*/ 18727 SOC_IF_ERROR_RETURN(READ_CMIC_SBUS_RING_MAP_0_7r(unit, &rval)); 18728 if (rval != 0) { 18729 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_3r(unit, 0xffffff00)); 18730 sal_usleep(500); 18731 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_3r(unit, 0xffff0000)); 18732 sal_usleep(500); 18733 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_3r(unit, 0xff000000)); 18734 sal_usleep(500); 18735 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_3r(unit, 0x000000)); 18736 sal_usleep(500); 18737 18738 if (SOC_IS_TOMAHAWK2(unit)) { 18739 SOC_IF_ERROR_RETURN 18740 (WRITE_TOP_SOFT_RESET_REG_4r(unit, 0xffffff00)); 18741 sal_usleep(500); 18742 SOC_IF_ERROR_RETURN 18743 (WRITE_TOP_SOFT_RESET_REG_4r(unit, 0xffff0000)); 18744 sal_usleep(500); 18745 SOC_IF_ERROR_RETURN 18746 (WRITE_TOP_SOFT_RESET_REG_4r(unit, 0xff000000)); 18747 sal_usleep(500); 18748 SOC_IF_ERROR_RETURN 18749 (WRITE_TOP_SOFT_RESET_REG_4r(unit, 0x000000)); 18750 sal_usleep(500); 18751 } 18752 } 18753 } 18754 #endif 18755 soc_pci_write(unit, CMIC_CPS_RESET_OFFSET, 1); 18756 } else 18757 #endif 18758 #ifdef BCM_CMICX_SUPPORT 18759 if (soc_feature(unit, soc_feature_cmicx)) { 18760 uint32 v; 18761 if (SOC_IS_TOMAHAWK3(unit)) { 18762 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_3r(unit, 0xffffff00)); 18763 sal_usleep(500); 18764 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_3r(unit, 0xffff0000)); 18765 sal_usleep(500); 18766 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_3r(unit, 0xff000000)); 18767 sal_usleep(500); 18768 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_3r(unit, 0x000000)); 18769 sal_usleep(500); 18770 } 18771 18772 if (!SAL_BOOT_SIMULATION || SAL_BOOT_QUICKTURN) { 18773 18774 if (SOC_IS_HELIX5(unit)) { 18775 /* CMICx DMA channels need to be released/aborted properly 18776 * and start at clean state by calling call 'soc_cmicx_dma_abort'. 18777 * sw_reset_n=0 cannot be used for iHost devices 18778 */ 18779 SOC_IF_ERROR_RETURN(soc_cmicx_dma_abort(unit, 0)); 18780 } else { 18781 /* To maintian compatibility with all 18782 * previous devices, write '0' to 18783 * SW_RESET_N of DMU_CRU_RESET 18784 */ 18785 v = 2; 18786 WRITE_DMU_CRU_RESETr(unit, v); 18787 } 18788 } 18789 } else 18790 #endif 18791 { 18792 soc_pci_write(unit, CMIC_CONFIG, 18793 soc_pci_read(unit, CMIC_CONFIG) | CC_RESET_CPS); 18794 } 18795 18796 if (soc_feature(unit, soc_feature_reset_delay) && !SAL_BOOT_QUICKTURN) { 18797 sal_usleep(1000000); 18798 } else { 18799 if (SAL_BOOT_QUICKTURN) { 18800 sal_usleep(10 * MILLISECOND_USEC); 18801 } else { 18802 sal_usleep(1 * MILLISECOND_USEC); 18803 } 18804 } 18805 } 18806 } 18807 18808 /* 18809 * Sleep some extra time to allow the StrataSwitch chip to finish 18810 * initializing the ARL tables, which takes 60000 to 70000 cycles. 18811 * On PLI, sleeping 10us won't make a difference. 18812 */ 18813 if (SAL_BOOT_QUICKTURN) { 18814 sal_usleep(250 * MILLISECOND_USEC); 18815 } else { 18816 sal_usleep(10 * MILLISECOND_USEC); 18817 } 18818 18819 /* On some boards that run at lower freq, reading the CMIC_CONFIG 18820 * register for the first time after CPS reset returns 0. The SW 18821 * workaround is to perform an extra read. 18822 * Eventhough Hu is the only (first) board with this issue, this 18823 * could be a common Workaround.. 18824 */ 18825 if (!soc_feature(unit, soc_feature_cmicm) && !soc_feature(unit, soc_feature_cmicx)) { 18826 soc_pci_read(unit, CMIC_CONFIG); 18827 sal_usleep(1000); 18828 } 18829 18830 /* Restore endian mode since the reset cleared it. */ 18831 18832 soc_endian_config(unit); 18833 soc_pci_ep_config(unit, -1); 18834 18835 /* Restore bursting */ 18836 18837 soc_pci_burst_enable(unit); 18838 18839 18840 /* Synchronize cached interrupt mask */ 18841 #ifdef BCM_CMICX_SUPPORT 18842 if (soc_feature(unit, soc_feature_cmicx)) { 18843 soc_cmic_intr_all_disable(unit); 18844 } else 18845 #endif 18846 #ifdef BCM_CMICM_SUPPORT 18847 if (soc_feature(unit, soc_feature_cmicm)) { 18848 uint32 addr, rval; 18849 uint32 msi_en = 1; 18850 18851 if (soc_feature(unit, soc_feature_iproc) && 18852 (soc_cm_get_bus_type(unit) & SOC_DEV_BUS_MSI) == 0) { 18853 /* 18854 * For iProc designs, MSI must be turned off in the CMIC 18855 * to prevent invalid MSI messages from corrupting host 18856 * CPU memory. 18857 */ 18858 msi_en = 0; 18859 } 18860 18861 addr = CMIC_CMCx_PCIE_MISCEL_OFFSET(SOC_PCI_CMC(unit)); 18862 rval = soc_pci_read(unit, addr); 18863 18864 soc_reg_field_set(unit, CMIC_CMC0_PCIE_MISCELr, 18865 &rval, ENABLE_MSIf, msi_en); 18866 18867 18868 soc_pci_write(unit, addr, rval); 18869 18870 soc_cmicm_intr0_disable(unit, ~0); 18871 soc_cmicm_intr1_disable(unit, ~0); 18872 soc_cmicm_intr2_disable(unit, ~0); 18873 #ifdef BCM_CMICDV2_SUPPORT 18874 if (soc_feature(unit, soc_feature_cmicd_v2)) { 18875 soc_cmicm_intr3_disable(unit, ~0); 18876 soc_cmicm_intr4_disable(unit, ~0); 18877 soc_cmicm_intr5_disable(unit, ~0); 18878 #ifdef BCM_CMICDV4_SUPPORT 18879 if (soc_feature(unit, soc_feature_cmicd_v4)) { 18880 soc_cmicm_intr6_disable(unit, ~0); 18881 } 18882 #endif /* BCM_CMICDV4_SUPPORT */ 18883 } 18884 #endif /* BCM_CMICDV2_SUPPORT */ 18885 } else 18886 #endif 18887 { 18888 soc_intr_disable(unit, ~0); 18889 } 18890 18891 #ifdef BCM_CMICX_SUPPORT 18892 if (soc_feature(unit, soc_feature_cmicx) && 18893 !((SAL_BOOT_PLISIM || SAL_BOOT_BCMSIM))) { 18894 int ccmdma = 0; 18895 ccmdma = soc_property_get(unit, spn_CCM_DMA_ENABLE, 1); 18896 SOC_IF_ERROR_RETURN(soc_esw_schan_fifo_init(unit, ccmdma)); 18897 } 18898 #endif 18899 18900 /* Initialize bulk mem API */ 18901 mode = soc_property_get_str(unit, spn_SOC_MEM_BULK_SCHAN_OP_MODE); 18902 if (mode) { 18903 SOC_CONTROL(unit)->memBulkSchanPioMode = 18904 (sal_strcasecmp(mode , "pio") == 0) ? 1 : 0; 18905 } else { 18906 SOC_CONTROL(unit)->memBulkSchanPioMode = 0; 18907 } 18908 SOC_IF_ERROR_RETURN(soc_mem_bulk_init(unit)); 18909 18910 /* Block interrupts */ 18911 spl = sal_splhi(); 18912 SOC_CONTROL(unit)->soc_flags &= ~SOC_F_BUSY; 18913 /* Unblock interrupts */ 18914 sal_spl(spl); 18915 18916 /* Resume IRQ polling if active */ 18917 soc_ipoll_continue(unit); 18918 18919 #if defined(BCM_CMICM_SUPPORT) 18920 if (soc_feature(unit, soc_feature_cmicm)) { 18921 /* Set the timeout for bus-mastered DMA transactions to 50ms */ 18922 if (SOC_REG_IS_VALID(unit, CMIC_PCIE_USERIF_TIMEOUTr) && 18923 SOC_REG_FIELD_VALID(unit, CMIC_PCIE_USERIF_TIMEOUTr, TIMEOUTf)) { 18924 uint32 rval; 18925 18926 SOC_IF_ERROR_RETURN(READ_CMIC_PCIE_USERIF_TIMEOUTr(unit, &rval)); 18927 soc_reg_field_set(unit, CMIC_PCIE_USERIF_TIMEOUTr, &rval, TIMEOUTf, 18928 50000000); 18929 /* coverity[result_independent_of_operands] */ 18930 SOC_IF_ERROR_RETURN(WRITE_CMIC_PCIE_USERIF_TIMEOUTr(unit, rval)); 18931 } 18932 } 18933 #endif 18934 18935 18936 #ifdef BCM_FIREBOLT_SUPPORT 18937 #ifdef BCM_RAPTOR1_SUPPORT 18938 if (SOC_IS_RAPTOR(unit)) { 18939 soc_reset_bcm56218_a0(unit); 18940 } else 18941 #endif /* BCM_RAPTOR_SUPPORT */ 18942 #ifdef BCM_RAVEN_SUPPORT 18943 if (SOC_IS_RAVEN(unit)) { 18944 soc_reset_bcm56224_a0(unit); 18945 } else 18946 #endif 18947 #ifdef BCM_HAWKEYE_SUPPORT 18948 if (SOC_IS_HAWKEYE(unit)) { 18949 soc_reset_bcm53314_a0(unit); 18950 } else 18951 #endif 18952 #ifdef BCM_TRIUMPH2_SUPPORT 18953 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 18954 SOC_IS_VALKYRIE2(unit)) { 18955 soc_reset_bcm56634_a0(unit); 18956 } else 18957 #endif 18958 #ifdef BCM_ENDURO_SUPPORT 18959 if (SOC_IS_ENDURO(unit)) { 18960 soc_reset_bcm56334_a0(unit); 18961 } else 18962 #endif 18963 #ifdef BCM_HURRICANE1_SUPPORT 18964 if (SOC_IS_HURRICANE(unit)) { 18965 soc_reset_bcm56142_a0(unit); 18966 } else 18967 #endif 18968 #ifdef BCM_HURRICANE2_SUPPORT 18969 if (SOC_IS_HURRICANE2(unit)) { 18970 SOC_IF_ERROR_RETURN(soc_reset_bcm56150_a0(unit)); 18971 } else 18972 #endif 18973 #ifdef BCM_HURRICANE3_SUPPORT 18974 if (SOC_IS_HURRICANE3(unit)) { 18975 if ((dev_id & 0xFFF0) == BCM53540_DEVICE_ID) { 18976 SOC_IF_ERROR_RETURN(soc_wolfhound2_chip_reset(unit)); 18977 } else { 18978 SOC_IF_ERROR_RETURN(soc_hurricane3_chip_reset(unit)); 18979 } 18980 } else 18981 #endif 18982 #ifdef BCM_GREYHOUND_SUPPORT 18983 if (SOC_IS_GREYHOUND(unit)) { 18984 SOC_IF_ERROR_RETURN(soc_greyhound_chip_reset(unit)); 18985 } else 18986 #endif 18987 #ifdef BCM_GREYHOUND2_SUPPORT 18988 if (SOC_IS_GREYHOUND2(unit)) { 18989 SOC_IF_ERROR_RETURN(soc_greyhound2_chip_reset(unit)); 18990 } else 18991 #endif 18992 #ifdef BCM_HELIX4_SUPPORT 18993 if (SOC_IS_HELIX4(unit)) { 18994 SOC_IF_ERROR_RETURN(soc_reset_bcm56340_a0(unit)); 18995 } else 18996 #endif 18997 #ifdef BCM_TRIUMPH3_SUPPORT 18998 if (SOC_IS_TRIUMPH3(unit)) { 18999 SOC_IF_ERROR_RETURN(soc_triumph3_chip_reset(unit)); 19000 } else 19001 #endif 19002 #ifdef BCM_TOMAHAWK2_SUPPORT 19003 if (SOC_IS_TOMAHAWK2(unit)) { 19004 SOC_IF_ERROR_RETURN(soc_tomahawk2_chip_reset(unit)); 19005 } else 19006 #endif 19007 #ifdef BCM_TOMAHAWK_SUPPORT 19008 if (SOC_IS_TOMAHAWK(unit)) { 19009 SOC_IF_ERROR_RETURN(soc_tomahawk_chip_reset(unit)); 19010 } else 19011 #endif 19012 #ifdef BCM_TOMAHAWK3_SUPPORT 19013 if (SOC_IS_TOMAHAWK3(unit)) { 19014 SOC_IF_ERROR_RETURN(soc_tomahawk3_chip_reset(unit)); 19015 } else 19016 #endif 19017 #ifdef BCM_MONTEREY_SUPPORT 19018 /* This should be before APACHE check */ 19019 if (SOC_IS_MONTEREY(unit)) { 19020 SOC_IF_ERROR_RETURN(soc_monterey_chip_reset(unit)); 19021 } else 19022 #endif 19023 #ifdef BCM_TRIDENT3_SUPPORT 19024 if (SOC_IS_TRIDENT3(unit)) { 19025 SOC_IF_ERROR_RETURN(soc_trident3_chip_reset(unit)); 19026 } else 19027 #endif 19028 #ifdef BCM_HELIX5_SUPPORT 19029 if (SOC_IS_HELIX5(unit)) { 19030 SOC_IF_ERROR_RETURN(soc_helix5_chip_reset(unit)); 19031 } else 19032 #endif 19033 #ifdef BCM_MAVERICK2_SUPPORT 19034 if (SOC_IS_MAVERICK2(unit)) { 19035 SOC_IF_ERROR_RETURN(soc_maverick2_chip_reset(unit)); 19036 } else 19037 #endif 19038 #ifdef BCM_APACHE_SUPPORT 19039 /* This should be before TD2_TT2 check */ 19040 if (SOC_IS_APACHE(unit)) { 19041 SOC_IF_ERROR_RETURN(soc_apache_chip_reset(unit)); 19042 } else 19043 #endif 19044 #ifdef BCM_TRIDENT2_SUPPORT 19045 if (SOC_IS_TD2_TT2(unit)) { 19046 SOC_IF_ERROR_RETURN(soc_trident2_chip_reset(unit)); 19047 } else 19048 #endif 19049 #ifdef BCM_TRIDENT_SUPPORT 19050 if (SOC_IS_TD_TT(unit)) { 19051 SOC_IF_ERROR_RETURN(soc_reset_bcm56840_a0(unit)); 19052 } else 19053 #endif 19054 #ifdef BCM_KATANA_SUPPORT 19055 if (SOC_IS_KATANA(unit)) { 19056 SOC_IF_ERROR_RETURN(soc_reset_bcm56440_a0(unit)); 19057 } else 19058 #endif 19059 #ifdef BCM_METROLITE_SUPPORT 19060 if (SOC_IS_METROLITE(unit)) { 19061 SOC_IF_ERROR_RETURN(soc_reset_bcm56270_a0(unit)); 19062 } else 19063 #endif 19064 #ifdef BCM_SABER2_SUPPORT 19065 if (SOC_IS_SABER2(unit)) { 19066 SOC_IF_ERROR_RETURN(soc_reset_bcm56260_a0(unit)); 19067 } else 19068 #endif 19069 #ifdef BCM_KATANA2_SUPPORT 19070 if (SOC_IS_KATANA2(unit)) { 19071 SOC_IF_ERROR_RETURN(soc_reset_bcm56450_a0(unit)); 19072 } else 19073 #endif 19074 #ifdef BCM_TRIUMPH_SUPPORT 19075 if (SOC_IS_TR_VL(unit)) { 19076 soc_reset_bcm56624_a0(unit); 19077 } else 19078 #endif 19079 #ifdef BCM_SHADOW_SUPPORT 19080 if (SOC_IS_SHADOW(unit)) { 19081 uint32 rval = 0; 19082 soc_reg_field_set(unit, CMIC_EB3_VLI_CONFIG_REGISTERr, &rval, 19083 EB3_DATA_PARITY_ENABLEf, 1); 19084 soc_reg_field_set(unit, CMIC_EB3_VLI_CONFIG_REGISTERr, &rval, 19085 EB3_ADDR_PARITY_ENABLEf, 1); 19086 WRITE_CMIC_EB3_VLI_CONFIG_REGISTERr(unit, rval); 19087 soc_reset_bcm88732_a0(unit); 19088 } else 19089 #endif 19090 #ifdef BCM_SCORPION_SUPPORT 19091 if (SOC_IS_SC_CQ(unit)) { 19092 soc_reset_bcm56820_a0(unit); 19093 } else 19094 #endif 19095 if (SOC_IS_FB_FX_HX(unit)) { 19096 soc_reset_bcm56504_a0(unit); 19097 } else 19098 #if defined (BCM_BRADLEY_SUPPORT) 19099 if (SOC_IS_HB_GW(unit)) { 19100 soc_reset_bcm56800_a0(unit); 19101 } 19102 #endif /* BCM_BRADLEY_SUPPORT */ 19103 #endif /* BCM_FIREBOLT_SUPPORT */ 19104 19105 #ifdef BCM_XGS3_SWITCH_SUPPORT 19106 if (SOC_IS_XGS3_SWITCH(unit)) { 19107 soc_port_t port; 19108 /* 19109 * For H/W linkscan 19110 */ 19111 #if defined (BCM_CMICM_SUPPORT) 19112 if (soc_feature(unit, soc_feature_cmicm) && 19113 !soc_property_get(unit, spn_MDIO_EXTERNAL_MASTER, 0)) { 19114 uint32 rval; 19115 READ_CMIC_MIIM_SCAN_CTRLr(unit, &rval); 19116 soc_reg_field_set(unit, CMIC_MIIM_SCAN_CTRLr, &rval, 19117 OVER_RIDE_EXT_MDIO_MSTR_CNTRLf, 1); 19118 WRITE_CMIC_MIIM_SCAN_CTRLr(unit, rval); 19119 } 19120 #endif 19121 if (!SOC_IS_SC_CQ(unit) && !SOC_IS_TD_TT(unit) && 19122 !soc_feature(unit, soc_feature_cmicm)) { 19123 WRITE_CMIC_MIIM_PORT_TYPE_MAPr(unit, 19124 SOC_PBMP_WORD_GET(PBMP_HG_ALL(unit), 0) | 19125 SOC_PBMP_WORD_GET(PBMP_XE_ALL(unit), 0)); 19126 } 19127 if (SAL_BOOT_QUICKTURN) { 19128 /* Kick the QT phy model */ 19129 PBMP_GE_ITER(unit, port) { 19130 if (SOC_IS_SCORPION(unit)) { 19131 SOC_IF_ERROR_RETURN 19132 (soc_miim_write(unit, port - 24, 0x00, 0x140)); 19133 } else { 19134 if (SOC_IS_HELIX4(unit)) { 19135 SOC_IF_ERROR_RETURN 19136 (soc_miim_write(unit, port, 0x00, 0xFFFF)); 19137 } else if (SOC_IS_TRIDENT3X(unit)) { 19138 /* Do Nothing for Trident3 */ 19139 } else { 19140 SOC_IF_ERROR_RETURN 19141 (soc_miim_write(unit, port, 0x00, 0x140)); 19142 } 19143 } 19144 } 19145 PBMP_FE_ITER(unit, port) { 19146 SOC_IF_ERROR_RETURN(soc_miim_write(unit, port, 0x00, 0x2100)); 19147 } 19148 } 19149 } 19150 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 19151 19152 #ifdef BCM_BIGMAC_SUPPORT 19153 #ifdef BCM_SCORPION_SUPPORT 19154 #ifdef BCM_SHADOW_SUPPORT 19155 if (SOC_IS_SC_CQ(unit) && (!SOC_IS_SHADOW(unit))) { 19156 #else /* BCM_SHADOW_SUPPORT */ 19157 if (SOC_IS_SC_CQ(unit)) { 19158 #endif 19159 soc_port_t port; 19160 soc_pbmp_t qg_pbmp; 19161 uint32 val, to_usec; 19162 19163 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 19164 (10 * MILLISECOND_USEC); 19165 19166 /* Bring Unicore out of reset */ 19167 PBMP_GX_ITER(unit, port) { 19168 _soc_xgxs_mdio_setup(unit, port); 19169 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19170 val = 0; 19171 soc_reg_field_set(unit, XPORT_XGXS_NEWCTL_REGr, 19172 &val, TXD1G_FIFO_RSTBf, 0xf); 19173 SOC_IF_ERROR_RETURN 19174 (WRITE_XPORT_XGXS_NEWCTL_REGr(unit, port, val)); 19175 } 19176 SOC_PBMP_ASSIGN(qg_pbmp, PBMP_GE_ALL(unit)); 19177 SOC_PBMP_REMOVE(qg_pbmp, PBMP_GX_ALL(unit)); 19178 SOC_PBMP_ITER(qg_pbmp, port) { 19179 _soc_xgxs_mdio_setup(unit, port); 19180 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19181 break; 19182 } 19183 19184 /* Bring remaining blocks out of reset */ 19185 READ_CMIC_SOFT_RESET_REGr(unit, &val); 19186 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 19187 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 19188 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 19189 1); 19190 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 19191 sal_usleep(to_usec); 19192 } else 19193 #endif /* BCM_SCORPION_SUPPORT */ 19194 #ifdef BCM_TRIUMPH_SUPPORT 19195 if (SOC_IS_TRIUMPH(unit) || SOC_IS_VALKYRIE(unit)) { 19196 soc_reg_t reg; 19197 int port, hc_idx; 19198 int hc_port[6]; /* any port in the hyperlite block */ 19199 uint32 txd1g_map[6], val; 19200 19201 /* bring unicore out of reset */ 19202 PBMP_GX_ITER(unit, port) { 19203 _soc_xgxs_mdio_setup(unit, port); 19204 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19205 val = 0; 19206 soc_reg_field_set(unit, XPORT_XGXS_NEWCTL_REGr, 19207 &val, TXD1G_FIFO_RSTBf, 0xf); 19208 SOC_IF_ERROR_RETURN 19209 (WRITE_XPORT_XGXS_NEWCTL_REGr(unit, port, val)); 19210 } 19211 19212 /* bring hyperlite out of reset */ 19213 for (hc_idx = 0; hc_idx < 6; hc_idx++) { 19214 hc_port[hc_idx] = -1; 19215 txd1g_map[hc_idx] = 0; 19216 } 19217 PBMP_XG_ITER(unit, port) { 19218 switch (tr_xgxs_map[port].mdio_conf_reg) { 19219 case CMIC_XGXS_MDIO_CONFIG_0r: hc_idx = 0; break; 19220 case CMIC_XGXS_MDIO_CONFIG_1r: hc_idx = 1; break; 19221 case CMIC_XGXS_MDIO_CONFIG_2r: hc_idx = 2; break; 19222 case CMIC_XGXS_MDIO_CONFIG_3r: hc_idx = 3; break; 19223 case CMIC_XGXS_MDIO_CONFIG_4r: hc_idx = 4; break; 19224 case CMIC_XGXS_MDIO_CONFIG_5r: hc_idx = 5; break; 19225 default: continue; 19226 } 19227 if (hc_port[hc_idx] == -1) { 19228 hc_port[hc_idx] = port; 19229 } 19230 if (!IS_XE_PORT(unit, port) && !IS_HG_PORT(unit, port)) { 19231 txd1g_map[hc_idx] |= 1 << tr_xgxs_map[port].hc_chan; 19232 } else { 19233 txd1g_map[hc_idx] = 0x0f; 19234 } 19235 } 19236 for (hc_idx = 0; hc_idx < 6; hc_idx++) { 19237 if (hc_port[hc_idx] == -1) { 19238 continue; 19239 } 19240 port = hc_port[hc_idx]; 19241 _soc_xgxs_mdio_setup(unit, port); 19242 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19243 reg = hc_idx != 1 && hc_idx != 4 ? XGPORT_XGXS_NEWCTL_REGr : 19244 XGPORT_EXTRA_XGXS_NEWCTL_REGr; 19245 val = 0; 19246 soc_reg_field_set(unit, reg, &val, TXD1G_FIFO_RSTBf, 19247 txd1g_map[hc_idx]); 19248 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, val)); 19249 } 19250 } else 19251 #endif /* BCM_TRIUMPH_SUPPORT */ 19252 #ifdef BCM_TRIUMPH2_SUPPORT 19253 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 19254 SOC_IS_VALKYRIE2(unit)) { 19255 int port, hc_idx; 19256 int hc_port[6]; /* any port in the hyperlite block */ 19257 uint32 txd1g_map[6], val; 19258 19259 /* bring unicore out of reset */ 19260 PBMP_GX_ITER(unit, port) { 19261 if (IS_XQ_PORT(unit, port)) { 19262 /* Register does not exist for XQ ports */ 19263 continue; 19264 } 19265 _soc_xgxs_mdio_setup(unit, port); 19266 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19267 val = 0; 19268 soc_reg_field_set(unit, XPORT_XGXS_NEWCTL_REGr, 19269 &val, TXD1G_FIFO_RSTBf, 0xf); 19270 SOC_IF_ERROR_RETURN 19271 (WRITE_XPORT_XGXS_NEWCTL_REGr(unit, port, val)); 19272 } 19273 19274 /* bring hyperlite out of reset */ 19275 for (hc_idx = 0; hc_idx < 6; hc_idx++) { 19276 hc_port[hc_idx] = -1; 19277 txd1g_map[hc_idx] = 0; 19278 } 19279 PBMP_XQ_ITER(unit, port) { 19280 hc_idx = (port - 30) / 4; 19281 19282 if (hc_port[hc_idx] == -1) { 19283 hc_port[hc_idx] = port; 19284 } 19285 if (!IS_XE_PORT(unit, port) && !IS_HG_PORT(unit, port)) { 19286 txd1g_map[hc_idx] |= 1 << ((port - 30) & 0x3); 19287 } else { 19288 txd1g_map[hc_idx] = 0x0f; 19289 } 19290 } 19291 for (hc_idx = 0; hc_idx < 6; hc_idx++) { 19292 if (hc_port[hc_idx] == -1) { 19293 continue; 19294 } 19295 port = hc_port[hc_idx]; 19296 _soc_xgxs_mdio_setup(unit, port); 19297 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19298 val = 0; 19299 soc_reg_field_set(unit, XQPORT_XGXS_NEWCTL_REGr, &val, 19300 TXD1G_FIFO_RSTBf, txd1g_map[hc_idx]); 19301 SOC_IF_ERROR_RETURN(WRITE_XQPORT_XGXS_NEWCTL_REGr(unit, port, 19302 val)); 19303 } 19304 } else 19305 #endif /* BCM_TRIUMPH2_SUPPORT */ 19306 #ifdef BCM_BRADLEY_SUPPORT 19307 if (SOC_IS_HB_GW(unit)) { 19308 soc_port_t port; 19309 uint32 val, to_usec; 19310 19311 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 19312 (10 * MILLISECOND_USEC); 19313 19314 /* Bring Unicore out of reset */ 19315 PBMP_GX_ITER(unit, port) { 19316 SOC_IF_ERROR_RETURN(soc_unicore_reset(unit, port)); 19317 } 19318 19319 /* Bring remaining blocks out of reset */ 19320 READ_CMIC_SOFT_RESET_REGr(unit, &val); 19321 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_BSAFE_RST_Lf, 1); 19322 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_IP_RST_Lf, 1); 19323 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_EP_RST_Lf, 1); 19324 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_MMU_RST_Lf, 1); 19325 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &val, CMIC_XP_RST_Lf, 1); 19326 WRITE_CMIC_SOFT_RESET_REGr(unit, val); 19327 sal_usleep(to_usec); 19328 } else 19329 #endif /* BCM_BRADLEY_SUPPORT */ 19330 #ifdef BCM_ENDURO_SUPPORT 19331 if (SOC_IS_ENDURO(unit)) { 19332 soc_port_t port; 19333 uint32 val; 19334 19335 /* bring unicore out of reset */ 19336 PBMP_XQ_ITER(unit, port) { 19337 _soc_xgxs_mdio_setup(unit, port); 19338 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19339 val = 0; 19340 soc_reg_field_set(unit, XQPORT_XGXS_NEWCTL_REGr, &val, 19341 TXD1G_FIFO_RSTBf, 0xf); 19342 SOC_IF_ERROR_RETURN(WRITE_XQPORT_XGXS_NEWCTL_REGr(unit, port, val)); 19343 } 19344 } else 19345 #endif /* BCM_ENDURO_SUPPORT */ 19346 #ifdef BCM_SHADOW_SUPPORT 19347 if (SOC_IS_SHADOW(unit)) { 19348 /* setup xgxs mdio */ 19349 /* reset xgxs */ 19350 soc_info_t *si; 19351 soc_port_t port; 19352 int blk; 19353 uint32 rval; 19354 19355 si = &SOC_INFO(unit); 19356 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 19357 port = SOC_BLOCK_PORT(unit, blk); 19358 _soc_xgxs_mdio_setup(unit, port); 19359 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19360 19361 /* Bring XMAC out of reset */ 19362 if (si->port_speed_max[port] < 10000) { 19363 continue; 19364 } 19365 SOC_IF_ERROR_RETURN(READ_XLPORT_XMAC_CONTROLr(unit, port, &rval)); 19366 soc_reg_field_set(unit, XLPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 19367 1); 19368 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XMAC_CONTROLr(unit, port, rval)); 19369 sal_udelay(10); 19370 19371 soc_reg_field_set(unit, XLPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 19372 0); 19373 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XMAC_CONTROLr(unit, port, rval)); 19374 } 19375 } else 19376 #endif /* BCM_SHADOW_SUPPORT */ 19377 #ifdef BCM_HURRICANE1_SUPPORT 19378 if (SOC_IS_HURRICANE(unit)) { 19379 soc_port_t port; 19380 uint32 val; 19381 19382 /* bring unicore out of reset */ 19383 PBMP_XQ_ITER(unit, port) { 19384 _soc_xgxs_mdio_setup(unit, port); 19385 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19386 val = 0; 19387 soc_reg_field_set(unit, XQPORT_XGXS_NEWCTL_REGr, &val, 19388 TXD1G_FIFO_RSTBf, 0xf); 19389 SOC_IF_ERROR_RETURN(WRITE_XQPORT_XGXS_NEWCTL_REGr(unit, port, val)); 19390 } 19391 } else 19392 #endif /* BCM_HURRICANE_SUPPORT */ 19393 #ifdef BCM_HURRICANE2_SUPPORT 19394 if (SOC_IS_HURRICANE2(unit)) { 19395 SOC_IF_ERROR_RETURN(soc_hurricane2_tsc_reset(unit)); 19396 } else 19397 #endif /* BCM_HURRICANE2_SUPPORT */ 19398 #ifdef BCM_TOMAHAWKPLUS_SUPPORT 19399 /* Check for TOMAHAWKPLUS before TOMAHAWK since TH+ is superset */ 19400 if (SOC_IS_TOMAHAWKPLUS(unit)) { 19401 SOC_IF_ERROR_RETURN(soc_tomahawkplus_port_reset(unit)); 19402 } else 19403 #endif /* BCM_TOMAHAWK_SUPPORT */ 19404 #ifdef BCM_TOMAHAWK3_SUPPORT 19405 if (SOC_IS_TOMAHAWK3(unit)) { 19406 SOC_IF_ERROR_RETURN(soc_tomahawk3_port_reset(unit)); 19407 } else 19408 #endif /* BCM_TOMAHAWK3_SUPPORT */ 19409 #ifdef BCM_TOMAHAWK_SUPPORT 19410 if (SOC_IS_TOMAHAWKX(unit)) { 19411 SOC_IF_ERROR_RETURN(soc_tomahawk_port_reset(unit)); 19412 } else 19413 #endif /* BCM_TOMAHAWK_SUPPORT */ 19414 #ifdef BCM_MONTEREY_SUPPORT 19415 if (SOC_IS_MONTEREY(unit)) { 19416 SOC_IF_ERROR_RETURN(soc_monterey_tsc_reset(unit)); 19417 } else 19418 #endif /* BCM_MONTEREY_SUPPORT */ 19419 #ifdef BCM_TRIDENT3_SUPPORT 19420 if (SOC_IS_TRIDENT3(unit)) { 19421 SOC_IF_ERROR_RETURN(soc_trident3_port_reset(unit)); 19422 } else 19423 #endif /* BCM_TRIDENT3_SUPPORT */ 19424 #ifdef BCM_HELIX5_SUPPORT 19425 if (SOC_IS_HELIX5(unit)) { 19426 SOC_IF_ERROR_RETURN(soc_helix5_port_reset(unit)); 19427 } else 19428 #endif /* BCM_HELIX5_SUPPORT */ 19429 #ifdef BCM_MAVERICK2_SUPPORT 19430 if (SOC_IS_MAVERICK2(unit)) { 19431 SOC_IF_ERROR_RETURN(soc_maverick2_port_reset(unit)); 19432 } else 19433 #endif /* BCM_MAVERICK2_SUPPORT */ 19434 #ifdef BCM_APACHE_SUPPORT 19435 if (SOC_IS_APACHE(unit)) { 19436 SOC_IF_ERROR_RETURN(soc_apache_tsc_reset(unit)); 19437 } else 19438 #endif /* BCM_APACHE_SUPPORT */ 19439 #ifdef BCM_TRIDENT2_SUPPORT 19440 if (SOC_IS_TD2_TT2(unit)) { 19441 SOC_IF_ERROR_RETURN(soc_trident2_tsc_reset(unit)); 19442 } else 19443 #endif /* BCM_TRIDENT2_SUPPORT */ 19444 #ifdef BCM_TRIDENT_SUPPORT 19445 if (SOC_IS_TD_TT(unit)) { 19446 soc_info_t *si; 19447 int rv, blk, port, phy_port, saved_phy_port, saved_port_type; 19448 uint32 rval; 19449 19450 si = &SOC_INFO(unit); 19451 19452 /* Toggle unused Warpcore */ 19453 port = 1; /* borrow logical port 1 for the unused block */ 19454 saved_phy_port = si->port_l2p_mapping[port]; 19455 saved_port_type = si->port_type[port]; 19456 si->port_type[port] = SOC_BLK_XLPORT; 19457 for (blk = 0; SOC_BLOCK_TYPE(unit, blk) >= 0; blk++) { 19458 if (SOC_BLOCK_TYPE(unit, blk) != SOC_BLK_XLPORT) { 19459 continue; 19460 } 19461 if (SOC_INFO(unit).block_valid[blk]) { 19462 continue; 19463 } 19464 for (phy_port = 0; ; phy_port++) { 19465 if (blk == SOC_PORT_BLOCK(unit, phy_port)) { 19466 break; 19467 } 19468 if (SOC_PORT_BLOCK(unit, phy_port) < 0 && 19469 SOC_PORT_BINDEX(unit, phy_port) < 0) { 19470 phy_port = -1; 19471 break; 19472 } 19473 } 19474 if (phy_port >= 0) { 19475 si->port_l2p_mapping[port] = phy_port; 19476 rv = soc_wc_xgxs_reset(unit, port, 0); 19477 if (SOC_FAILURE(rv)) { 19478 break; 19479 } 19480 } 19481 } 19482 for (blk = 0; SOC_BLOCK_TYPE(unit, blk) >= 0; blk++) { 19483 if (SOC_BLOCK_TYPE(unit, blk) != SOC_BLK_XLPORT) { 19484 continue; 19485 } 19486 if (SOC_INFO(unit).block_valid[blk]) { 19487 continue; 19488 } 19489 for (phy_port = 0; ; phy_port++) { 19490 if (blk == SOC_PORT_BLOCK(unit, phy_port)) { 19491 break; 19492 } 19493 if (SOC_PORT_BLOCK(unit, phy_port) < 0 && 19494 SOC_PORT_BINDEX(unit, phy_port) < 0) { 19495 phy_port = -1; 19496 break; 19497 } 19498 } 19499 if (phy_port >= 0) { 19500 si->port_l2p_mapping[port] = phy_port; 19501 rv = soc_wc_xgxs_power_down(unit, port, 0); 19502 if (SOC_FAILURE(rv)) { 19503 break; 19504 } 19505 } 19506 } 19507 si->port_l2p_mapping[port] = saved_phy_port; 19508 si->port_type[port] = saved_port_type; 19509 19510 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 19511 port = SOC_BLOCK_PORT(unit, blk); 19512 _soc_xgxs_mdio_setup(unit, port); 19513 SOC_IF_ERROR_RETURN(soc_wc_xgxs_reset(unit, port, 0)); 19514 } 19515 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 19516 port = SOC_BLOCK_PORT(unit, blk); 19517 SOC_IF_ERROR_RETURN(soc_wc_xgxs_pll_check(unit, port, 0)); 19518 } 19519 19520 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 19521 port = SOC_BLOCK_PORT(unit, blk); 19522 /* Bring XMAC out of reset */ 19523 if (si->port_speed_max[port] < 10000) { 19524 continue; 19525 } 19526 SOC_IF_ERROR_RETURN(READ_XLPORT_XMAC_CONTROLr(unit, port, &rval)); 19527 soc_reg_field_set(unit, XLPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 19528 1); 19529 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XMAC_CONTROLr(unit, port, rval)); 19530 sal_udelay(10); 19531 19532 soc_reg_field_set(unit, XLPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 19533 0); 19534 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XMAC_CONTROLr(unit, port, rval)); 19535 } 19536 } else 19537 #endif /* BCM_TRIDENT_SUPPORT */ 19538 #ifdef BCM_METROLITE_SUPPORT 19539 if(SOC_IS_METROLITE(unit)) { 19540 soc_port_t port; 19541 int blk; 19542 uint32 rval; 19543 19544 SOC_BLOCK_ITER(unit, blk, SOC_BLK_MXQPORT) { 19545 port = SOC_BLOCK_PORT(unit, blk); 19546 _soc_xgxs_mdio_setup(unit, port); 19547 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19548 19549 SOC_IF_ERROR_RETURN(READ_XPORT_XMAC_CONTROLr(unit, port, &rval)); 19550 soc_reg_field_set(unit, XPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 19551 1); 19552 SOC_IF_ERROR_RETURN(WRITE_XPORT_XMAC_CONTROLr(unit, port, rval)); 19553 sal_udelay(10); 19554 19555 soc_reg_field_set(unit, XPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 19556 0); 19557 SOC_IF_ERROR_RETURN(WRITE_XPORT_XMAC_CONTROLr(unit, port, rval)); 19558 } 19559 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 19560 port = SOC_BLOCK_PORT(unit, blk); 19561 19562 SOC_IF_ERROR_RETURN(READ_XLPORT_MAC_CONTROLr(unit, port, &rval)); 19563 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, 19564 XMAC0_RESETf, 1); 19565 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, port, rval)); 19566 sal_udelay(10); 19567 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, 19568 XMAC0_RESETf, 0); 19569 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, port, rval)); 19570 19571 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19572 } 19573 } else 19574 #endif 19575 19576 #ifdef BCM_SABER2_SUPPORT 19577 if(SOC_IS_SABER2(unit)) { 19578 soc_port_t port; 19579 int blk; 19580 uint32 rval; 19581 19582 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 19583 port = SOC_BLOCK_PORT(unit, blk); 19584 19585 SOC_IF_ERROR_RETURN(READ_XLPORT_MAC_CONTROLr(unit, port, &rval)); 19586 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, 19587 XMAC0_RESETf, 1); 19588 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, port, rval)); 19589 sal_udelay(10); 19590 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, 19591 XMAC0_RESETf, 0); 19592 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, port, rval)); 19593 19594 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19595 } 19596 } else 19597 #endif 19598 #ifdef BCM_KATANA_SUPPORT 19599 if (SOC_IS_KATANAX(unit)) { 19600 soc_port_t port; 19601 int blk; 19602 uint32 rval; 19603 19604 SOC_BLOCK_ITER(unit, blk, SOC_BLK_MXQPORT) { 19605 port = SOC_BLOCK_PORT(unit, blk); 19606 _soc_xgxs_mdio_setup(unit, port); 19607 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19608 /* Bring XMAC out of reset */ 19609 if (SOC_IS_KATANA(unit)) { 19610 SOC_IF_ERROR_RETURN(READ_XPORT_XGXS_NEWCTL_REGr(unit,port,&rval)); 19611 soc_reg_field_set(unit, XPORT_XGXS_NEWCTL_REGr, &rval, TXD1G_FIFO_RSTBf, 19612 0xf); 19613 WRITE_XPORT_XGXS_NEWCTL_REGr(unit,port,rval); 19614 } 19615 SOC_IF_ERROR_RETURN(READ_XPORT_XMAC_CONTROLr(unit, port, &rval)); 19616 soc_reg_field_set(unit, XPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 19617 1); 19618 SOC_IF_ERROR_RETURN(WRITE_XPORT_XMAC_CONTROLr(unit, port, rval)); 19619 sal_udelay(10); 19620 19621 soc_reg_field_set(unit, XPORT_XMAC_CONTROLr, &rval, XMAC_RESETf, 19622 0); 19623 SOC_IF_ERROR_RETURN(WRITE_XPORT_XMAC_CONTROLr(unit, port, rval)); 19624 } 19625 SOC_BLOCK_ITER(unit, blk, SOC_BLK_GPORT) { 19626 port = SOC_BLOCK_PORT(unit, blk); 19627 SOC_IF_ERROR_RETURN(READ_QUAD0_SERDES_CTRLr(unit, port, &rval)); 19628 soc_reg_field_set(unit, QUAD0_SERDES_CTRLr, &rval, RSTB_PLLf, 1); 19629 SOC_IF_ERROR_RETURN(WRITE_QUAD0_SERDES_CTRLr(unit, port, rval)); 19630 if (SOC_PORT_VALID(unit, port+4)) { 19631 SOC_IF_ERROR_RETURN(WRITE_QUAD1_SERDES_CTRLr(unit, port+4, rval)); 19632 } 19633 sal_usleep(100000); 19634 SOC_IF_ERROR_RETURN(READ_QUAD0_SERDES_CTRLr(unit, port, &rval)); 19635 soc_reg_field_set(unit, QUAD0_SERDES_CTRLr, &rval, HW_RSTLf, 1); 19636 SOC_IF_ERROR_RETURN(WRITE_QUAD0_SERDES_CTRLr(unit, port, rval)); 19637 if (SOC_PORT_VALID(unit, port+4)) { 19638 SOC_IF_ERROR_RETURN(WRITE_QUAD1_SERDES_CTRLr(unit, port+4, rval)); 19639 } 19640 sal_usleep(10000); 19641 soc_reg_field_set(unit, QUAD0_SERDES_CTRLr, &rval, TXFIFO_RSTLf, 0xf); 19642 soc_reg_field_set(unit, QUAD0_SERDES_CTRLr, &rval, RSTB_PLLf, 1); 19643 soc_reg_field_set(unit, QUAD0_SERDES_CTRLr, &rval, RSTB_MDIOREGSf, 1); 19644 SOC_IF_ERROR_RETURN(WRITE_QUAD0_SERDES_CTRLr(unit, port, rval)); 19645 if (SOC_PORT_VALID(unit, port+4)) { 19646 SOC_IF_ERROR_RETURN(WRITE_QUAD1_SERDES_CTRLr(unit, port+4, rval)); 19647 } 19648 rval = 0xff; /* Set UMAC0_RESETf..UMAC7_RESETf */ 19649 SOC_IF_ERROR_RETURN(WRITE_GPORT_UMAC_CONTROLr(unit, port, rval)); 19650 sal_udelay(10); 19651 rval = 0; /* Reset UMAC0_RESETf..UMAC7_RESETf */ 19652 SOC_IF_ERROR_RETURN(WRITE_GPORT_UMAC_CONTROLr(unit, port, rval)); 19653 } 19654 } else 19655 #endif /* BCM_KATANA_SUPPORT */ 19656 #ifdef BCM_TRIUMPH3_SUPPORT 19657 if (SOC_IS_TRIUMPH3(unit)) { 19658 soc_info_t *si; 19659 soc_port_t port; 19660 int phy, lane, blk, block_has_ports, high_speed_port, xgxs0_reset; 19661 uint32 rval; 19662 19663 si = &SOC_INFO(unit); 19664 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 19665 block_has_ports = FALSE; 19666 xgxs0_reset = FALSE; 19667 high_speed_port = -1; 19668 for (phy = 0; phy < _SOC_TR3_PHY_PER_PORT_BLOCK; phy++) { 19669 for (lane = 0; lane < _SOC_TR3_LANES_PER_PHY; lane++) { 19670 port = si->port_p2l_mapping[si->blk_fpp[blk] + 19671 ((phy * _SOC_TR3_LANES_PER_PHY) + lane)]; 19672 if (SOC_PORT_VALID(unit, port) && 19673 si->port_speed_max[port] >= 100000) { 19674 /* Save the 100G+ speed port becuase we must 19675 * init the other two PHYs, even though they don't 19676 * match a valid port. */ 19677 high_speed_port = port; 19678 } else if (high_speed_port >= 0) { 19679 port = high_speed_port; 19680 } 19681 if (SOC_PORT_VALID(unit, port)) { 19682 SOC_IF_ERROR_RETURN 19683 (soc_wc_xgxs_reset(unit, port, phy)); 19684 block_has_ports |= 1 << phy; 19685 if ((0 != phy) && !xgxs0_reset) { 19686 /* We must always reset the first WC 19687 * in the block */ 19688 SOC_IF_ERROR_RETURN 19689 (soc_wc_xgxs_reset(unit, port, 0)); 19690 } 19691 xgxs0_reset = TRUE; 19692 break; /* Only need to reset PHY once */ 19693 } 19694 } 19695 } 19696 if (!block_has_ports) { 19697 continue; /* All ports disabled */ 19698 } 19699 port = SOC_BLOCK_PORT(unit, blk); 19700 SOC_IF_ERROR_RETURN(READ_PORT_MAC_CONTROLr(unit, port, &rval)); 19701 if ((soc_feature(unit, soc_feature_cmac)) && (high_speed_port >= 0)) { 19702 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19703 CMAC_RESETf, 1); 19704 } 19705 if (block_has_ports & 1) { 19706 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19707 XMAC0_RESETf, 1); 19708 } 19709 if (block_has_ports & 2) { 19710 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19711 XMAC1_RESETf, 1); 19712 } 19713 if (block_has_ports & 4) { 19714 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19715 XMAC2_RESETf, 1); 19716 } 19717 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 19718 sal_udelay(10); 19719 if ((soc_feature(unit, soc_feature_cmac)) && (high_speed_port >= 0)) { 19720 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19721 CMAC_RESETf, 0); 19722 } 19723 if (block_has_ports & 1) { 19724 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19725 XMAC0_RESETf, 0); 19726 } 19727 if (block_has_ports & 2) { 19728 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19729 XMAC1_RESETf, 0); 19730 } 19731 if (block_has_ports & 4) { 19732 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19733 XMAC2_RESETf, 0); 19734 } 19735 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 19736 19737 /* Take MLD out of reset */ 19738 SOC_IF_ERROR_RETURN(READ_PORT_MLD_CTRL_REGr(unit, port, &rval)); 19739 soc_reg_field_set(unit, PORT_MLD_CTRL_REGr, &rval, 19740 RSTB_MDIOREGSf, 1); 19741 soc_reg_field_set(unit, PORT_MLD_CTRL_REGr, &rval, 19742 RSTB_HWf, 1); 19743 SOC_IF_ERROR_RETURN(WRITE_PORT_MLD_CTRL_REGr(unit, port, rval)); 19744 } 19745 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XTPORT) { 19746 block_has_ports = FALSE; 19747 xgxs0_reset = FALSE; 19748 for (phy = 0; phy < _SOC_TR3_PHY_PER_PORT_BLOCK; phy++) { 19749 for (lane = 0; lane < _SOC_TR3_LANES_PER_PHY; lane++) { 19750 port = si->port_p2l_mapping[si->blk_fpp[blk] + 19751 ((phy * _SOC_TR3_LANES_PER_PHY) + lane)]; 19752 if (SOC_PORT_VALID(unit, port)) { 19753 SOC_IF_ERROR_RETURN 19754 (soc_wc_xgxs_reset(unit, port, phy)); 19755 block_has_ports |= 1 << phy; 19756 if ((0 != phy) && !xgxs0_reset) { 19757 /* We must always reset the first WC in the block, even it is invalid*/ 19758 SOC_IF_ERROR_RETURN 19759 (soc_wc_xgxs_reset(unit, port, 0)); 19760 SOC_IF_ERROR_RETURN 19761 (soc_wc_xgxs_pll_check(unit, port, 0)); 19762 } 19763 xgxs0_reset = TRUE; 19764 break; /* Only need to reset PHY once */ 19765 } 19766 } 19767 } 19768 if (!block_has_ports) { 19769 continue; /* All ports disabled */ 19770 } 19771 port = SOC_BLOCK_PORT(unit, blk); 19772 SOC_IF_ERROR_RETURN(READ_PORT_MAC_CONTROLr(unit, port, &rval)); 19773 if (block_has_ports & 1) { 19774 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19775 XMAC0_RESETf, 1); 19776 } 19777 if (block_has_ports & 2) { 19778 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19779 XMAC1_RESETf, 1); 19780 } 19781 if (block_has_ports & 4) { 19782 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19783 XMAC2_RESETf, 1); 19784 } 19785 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 19786 sal_udelay(10); 19787 if (block_has_ports & 1) { 19788 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19789 XMAC0_RESETf, 0); 19790 } 19791 if (block_has_ports & 2) { 19792 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19793 XMAC1_RESETf, 0); 19794 } 19795 if (block_has_ports & 4) { 19796 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19797 XMAC2_RESETf, 0); 19798 } 19799 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 19800 } 19801 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 19802 block_has_ports = FALSE; 19803 /* Only one PHY per XLPORT */ 19804 for (lane = 0; lane < _SOC_TR3_LANES_PER_PHY; lane++) { 19805 port = si->port_p2l_mapping[si->blk_fpp[blk] + lane]; 19806 if (SOC_PORT_VALID(unit, port)) { 19807 block_has_ports = TRUE; 19808 break; 19809 } 19810 } 19811 if (!block_has_ports) { 19812 continue; /* All ports disabled */ 19813 } 19814 port = SOC_BLOCK_PORT(unit, blk); 19815 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19816 SOC_IF_ERROR_RETURN(READ_PORT_MAC_CONTROLr(unit, port, &rval)); 19817 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19818 XMAC0_RESETf, 1); 19819 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 19820 sal_udelay(10); 19821 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19822 XMAC0_RESETf, 0); 19823 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 19824 } 19825 #ifdef BCM_HELIX4_SUPPORT 19826 if (SOC_IS_HELIX4(unit)) { 19827 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XWPORT) { 19828 block_has_ports = FALSE; 19829 /* Only one PHY per XWPORT */ 19830 for (lane = 0; lane < _SOC_TR3_LANES_PER_PHY; lane++) { 19831 port = si->port_p2l_mapping[si->blk_fpp[blk] + lane]; 19832 if (SOC_PORT_VALID(unit, port)) { 19833 block_has_ports = TRUE; 19834 break; 19835 } 19836 } 19837 if (!block_has_ports) { 19838 continue; /* All ports disabled */ 19839 } 19840 port = SOC_BLOCK_PORT(unit, blk); 19841 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 19842 SOC_IF_ERROR_RETURN(READ_PORT_MAC_CONTROLr(unit, port, &rval)); 19843 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19844 XMAC0_RESETf, 1); 19845 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 19846 sal_udelay(10); 19847 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 19848 XMAC0_RESETf, 0); 19849 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 19850 } 19851 } 19852 #endif /* BCM_HELIX4_SUPPORT */ 19853 } else 19854 #endif /* BCM_TRIUMPH3_SUPPORT */ 19855 #ifdef BCM_GREYHOUND_SUPPORT 19856 if (SOC_IS_GREYHOUND(unit)) { 19857 SOC_IF_ERROR_RETURN(soc_greyhound_tsc_reset(unit)); 19858 } else 19859 #endif /* BCM_TRIDENT2_SUPPORT */ 19860 #ifdef BCM_HURRICANE3_SUPPORT 19861 if (SOC_IS_HURRICANE3(unit)) { 19862 SOC_IF_ERROR_RETURN(soc_hurricane3_tsc_reset(unit)); 19863 } else 19864 #endif /* BCM_HURRICANE3_SUPPORT */ 19865 #ifdef BCM_GREYHOUND2_SUPPORT 19866 if (SOC_IS_GREYHOUND2(unit)) { 19867 SOC_IF_ERROR_RETURN(soc_greyhound2_tsc_reset(unit)); 19868 } else 19869 #endif /* BCM_TRIDENT2_SUPPORT */ 19870 19871 { 19872 soc_port_t port; 19873 19874 /* Reset the fusion core for HiGig ports. Does nothing in sim */ 19875 /* Fusioncore must be out of reset before we probe for XGXS PHY. 19876 * Otherwise, XGXS PHY will not respond. 19877 */ 19878 PBMP_HG_ITER(unit, port) { 19879 _soc_xgxs_mdio_setup(unit, port); 19880 soc_fusioncore_reset(unit, port); 19881 } 19882 PBMP_XE_ITER(unit, port) { 19883 _soc_xgxs_mdio_setup(unit, port); 19884 soc_fusioncore_reset(unit, port); 19885 } 19886 } 19887 #endif /* BCM_BIGMAC_SUPPORT */ 19888 return 0; 19889 } 19890 19891 #ifdef BCM_WARM_BOOT_SUPPORT 19892 /* 19893 * Function: 19894 * soc_warmboot_reset 19895 * Purpose: 19896 * function used for chip specific process during warmboot 19897 */ 19898 19899 STATIC int 19900 soc_warmboot_reset(int unit) { 19901 19902 #ifdef BCM_GREYHOUND_SUPPORT 19903 if (SOC_IS_GREYHOUND(unit)){ 19904 soc_greyhound_chip_warmboot_reset(unit); 19905 } 19906 #endif 19907 19908 #if defined(BCM_TOMAHAWK_SUPPORT) 19909 if (SOC_IS_TOMAHAWK(unit)) { 19910 soc_tomahawk_chip_warmboot_reset(unit); 19911 } 19912 #endif 19913 19914 #if defined(BCM_TOMAHAWK2_SUPPORT) 19915 if (SOC_IS_TOMAHAWK2(unit)) { 19916 soc_tomahawk2_chip_warmboot_reset(unit); 19917 } 19918 #endif 19919 19920 SOC_IF_ERROR_RETURN(soc_port_type_verify(unit)); 19921 19922 return SOC_E_NONE; 19923 } 19924 #endif 19925 19926 /* 19927 * Function: 19928 * soc_detach 19929 * Purpose: 19930 * Detach a SOC device and deallocate all resources allocated. 19931 * Notes: 19932 * The chip is reset prior to detaching in order to quiesce 19933 * any DMA, etc. operations that may be in progress. 19934 */ 19935 19936 int 19937 soc_detach(int unit) 19938 { 19939 soc_control_t *soc; 19940 soc_mem_t mem, act_mem, lock_mem; 19941 int ix; 19942 int cmc; 19943 int do_reset; 19944 19945 LOG_INFO(BSL_LS_SOC_PCI, 19946 (BSL_META_U(unit, 19947 "Detaching\n"))); 19948 19949 soc = SOC_CONTROL(unit); 19950 19951 if (NULL == soc) { 19952 return SOC_E_NONE; 19953 } 19954 19955 if (0 == (soc->soc_flags & SOC_F_ATTACHED)) { 19956 return SOC_E_NONE; 19957 } 19958 19959 #ifdef BCM_HERCULES_SUPPORT 19960 /* Dump the MMU error stats */ 19961 soc_mmu_error_done(unit); 19962 19963 if (soc->lla_cells_good != NULL) { 19964 sal_free(soc->lla_cells_good); 19965 soc->lla_cells_good = NULL; 19966 } 19967 19968 if (soc->lla_map != NULL) { 19969 int port; 19970 PBMP_PORT_ITER(unit, port) { 19971 if (soc->lla_map[port] != NULL) { 19972 sal_free(soc->lla_map[port]); 19973 } 19974 } 19975 sal_free(soc->lla_map); 19976 soc->lla_map = NULL; 19977 } 19978 19979 if (soc->sbe_disable != NULL) { 19980 sal_free(soc->sbe_disable); 19981 soc->sbe_disable = NULL; 19982 } 19983 #endif 19984 19985 /* Free up any memory used by the I2C driver */ 19986 19987 #ifdef INCLUDE_I2C 19988 SOC_IF_ERROR_RETURN(soc_i2c_detach(unit)); 19989 #endif 19990 19991 /* Disable shutting down unit to run new DPCs and wait until all 19992 * existing DPCs are completed */ 19993 sal_dpc_disable_and_wait(INT_TO_PTR(unit)); 19994 19995 /* 19996 * Call soc_init to cancel link scan task, counter DMA task, 19997 * outstanding DMAs, interrupt generation, and anything else the 19998 * driver or chip may be doing. 19999 */ 20000 20001 do_reset = TRUE; 20002 #if defined(PLISIM) 20003 if (SAL_BOOT_PLISIM) { 20004 do_reset = FALSE; 20005 } 20006 #endif /* PLISIM */ 20007 if (do_reset) { 20008 if (soc_reset_init(unit) < 0) { 20009 LOG_ERROR(BSL_LS_SOC_COMMON, 20010 (BSL_META_U(unit, 20011 "could not reset and init soc \n"))); 20012 } 20013 } 20014 20015 20016 /* Device specific cleanup/deinit */ 20017 if (SOC_FUNCTIONS(unit)->soc_misc_deinit) { 20018 if (SOC_FAILURE(SOC_FUNCTIONS(unit)->soc_misc_deinit(unit))) { 20019 LOG_ERROR(BSL_LS_SOC_COMMON, 20020 (BSL_META_U(unit, 20021 "Misc deinit failed \n"))); 20022 return SOC_E_FAIL; 20023 } 20024 } 20025 20026 /* 20027 * PHY drivers and ID map 20028 */ 20029 20030 20031 #if 0 20032 if (SOC_USE_PORTCTRL(unit)) { 20033 SOC_IF_ERROR_RETURN(soc_portctrl_software_deinit(unit)); 20034 } else { 20035 SOC_IF_ERROR_RETURN(soc_phyctrl_software_deinit(unit)); 20036 } 20037 #else 20038 if (SOC_USE_PORTCTRL(unit)) { 20039 SOC_IF_ERROR_RETURN(soc_esw_portctrl_deinit(unit)); 20040 } 20041 20042 SOC_IF_ERROR_RETURN(soc_phyctrl_software_deinit(unit)); 20043 #endif 20044 20045 if (!SOC_IS_RCPU_ONLY(unit)) { 20046 /* Free up DMA memory */ 20047 SOC_IF_ERROR_RETURN(soc_dma_detach(unit)); 20048 } 20049 20050 /* Shutdown polled interrupt mode if active */ 20051 soc_ipoll_disconnect(unit); 20052 soc->soc_flags &= ~SOC_F_POLLED; 20053 20054 /* Detach interrupt handler, if we installed one */ 20055 /* unit # is ISR arg */ 20056 if (soc_cm_interrupt_disconnect(unit) < 0) { 20057 LOG_ERROR(BSL_LS_SOC_COMMON, 20058 (BSL_META_U(unit, 20059 "soc_detach: could not disconnect interrupt line\n"))); 20060 } 20061 20062 /* 20063 * When detaching, take care to free up only resources that were 20064 * actually allocated, in case we are cleaning up after an attach 20065 * that failed part way through. 20066 */ 20067 20068 if (soc->arlBuf != NULL) { 20069 soc_cm_sfree(unit, (void *)soc->arlBuf); 20070 soc->arlBuf = NULL; 20071 } 20072 20073 if (soc->arlShadow != NULL) { 20074 shr_avl_destroy(soc->arlShadow); 20075 soc->arlShadow = NULL; 20076 } 20077 20078 if (soc->arlShadowMutex != NULL) { 20079 sal_mutex_destroy(soc->arlShadowMutex); 20080 soc->arlShadowMutex = NULL; 20081 } 20082 20083 #ifdef BCM_TOMAHAWK3_SUPPORT 20084 if (soc->l2x_lrn_shadow != NULL) { 20085 shr_avl_destroy(soc->l2x_lrn_shadow); 20086 soc->l2x_lrn_shadow = NULL; 20087 } 20088 20089 if (soc->l2x_lrn_shadow_mutex != NULL) { 20090 sal_mutex_destroy(soc->l2x_lrn_shadow_mutex); 20091 soc->l2x_lrn_shadow_mutex = NULL; 20092 } 20093 #endif /* BCM_TOMAHAWK3_SUPPORT */ 20094 20095 if (soc->ipArbiterMutex != NULL) { 20096 sal_mutex_destroy(soc->ipArbiterMutex); 20097 soc->ipArbiterMutex = NULL; 20098 } 20099 20100 /* Terminate counter module; frees allocated space */ 20101 20102 soc_counter_detach(unit); 20103 20104 if (soc->counterMutex) { 20105 sal_mutex_destroy(soc->counterMutex); 20106 soc->counterMutex = NULL; 20107 } 20108 20109 if (soc->evictMutex) { 20110 sal_mutex_destroy(soc->evictMutex); 20111 soc->evictMutex = NULL; 20112 } 20113 #ifdef SOC_ROBUST_HASH 20114 if (soc_feature(unit, soc_feature_robust_hash)) { 20115 if (soc->soc_robust_hash_config != NULL) { 20116 sal_free(soc->soc_robust_hash_config); 20117 soc->soc_robust_hash_config = NULL; 20118 } 20119 } 20120 #endif /* SOC_ROBUST_HASH */ 20121 20122 20123 /* Deallocate L2X module and shadow table resources */ 20124 20125 #ifdef BCM_XGS_SWITCH_SUPPORT 20126 if (soc_feature(unit, soc_feature_arl_hashed)) { 20127 SOC_IF_ERROR_RETURN(soc_l2x_detach(unit)); 20128 } 20129 #ifdef BCM_TRIUMPH3_SUPPORT 20130 if SOC_IS_TRIUMPH3(unit) { 20131 SOC_IF_ERROR_RETURN(soc_tr3_l2_bulk_age_stop(unit)); 20132 } 20133 #endif /* BCM_TRIUMPH3_SUPPORT */ 20134 #ifdef BCM_TRIDENT2_SUPPORT 20135 if SOC_IS_TRIDENT2X(unit) { 20136 SOC_IF_ERROR_RETURN(soc_td2_l2_bulk_age_stop(unit)); 20137 } 20138 #endif /* BCM_TRIDENT2_SUPPORT */ 20139 #ifdef BCM_TOMAHAWK_SUPPORT 20140 if (SOC_IS_TOMAHAWK(unit) || SOC_IS_TOMAHAWK2(unit) || 20141 SOC_IS_TRIDENT3X(unit)) { 20142 SOC_IF_ERROR_RETURN(soc_th_l2_bulk_age_stop(unit)); 20143 } 20144 #endif /* BCM_TOMAHAWK_SUPPORT */ 20145 #ifdef ALPM_ENABLE 20146 #if defined(BCM_TOMAHAWK_SUPPORT) 20147 if (soc_property_get(unit, spn_L3_ALPM_ENABLE, 0) && 20148 soc_feature(unit, soc_feature_alpm2)) { 20149 SOC_IF_ERROR_RETURN(alpm_dist_hitbit_thread_stop(unit)); 20150 } 20151 #endif 20152 #endif 20153 #ifdef BCM_TOMAHAWK3_SUPPORT 20154 /* Stop L2 learning and aging threads */ 20155 if (SOC_IS_TOMAHAWK3(unit)) { 20156 SOC_IF_ERROR_RETURN(soc_th3_l2_age_stop(unit)); 20157 SOC_IF_ERROR_RETURN(soc_th3_l2_learn_thread_stop(unit)); 20158 } 20159 #endif /* BCM_TOMAHAWK3_SUPPORT */ 20160 #ifdef BCM_SBUSDMA_SUPPORT 20161 if (SOC_SBUSDMA_DM_INFO(unit)) { 20162 SOC_IF_ERROR_RETURN(soc_sbusdma_desc_detach(unit)); 20163 } 20164 #endif /* BCM_SBUSDMA_SUPPORT */ 20165 #endif /* BCM_XGS_SWITCH_SUPPORT */ 20166 20167 #ifdef INCLUDE_MEM_SCAN 20168 SOC_IF_ERROR_RETURN(soc_mem_scan_stop(unit)); /* Stop memory scanner */ 20169 if (soc->mem_scan_notify) { 20170 sal_sem_destroy(soc->mem_scan_notify); 20171 } 20172 #endif 20173 #ifdef BCM_SRAM_SCAN_SUPPORT 20174 SOC_IF_ERROR_RETURN(soc_sram_scan_stop(unit)); /* Stop memory scanner */ 20175 if (soc->sram_scan_notify) { 20176 sal_sem_destroy(soc->sram_scan_notify); 20177 } 20178 #endif 20179 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 20180 if (!SOC_MEM_IS_VALID(unit, mem)) { 20181 continue; 20182 } 20183 act_mem = mem; 20184 #ifdef BCM_ESW_SUPPORT 20185 soc_drv_mem_reuse_mem_state(unit, &act_mem, &lock_mem); 20186 #endif 20187 /* Deallocate table cache memory, if caching enabled */ 20188 SOC_IF_ERROR_RETURN(soc_mem_cache_set(unit, act_mem, COPYNO_ALL, FALSE)); 20189 } 20190 20191 /* LOCK used in cache_set, so destroy later */ 20192 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 20193 if (!SOC_MEM_IS_VALID(unit, mem)) { 20194 continue; 20195 } 20196 act_mem = mem; 20197 lock_mem = mem; 20198 #ifdef BCM_ESW_SUPPORT 20199 soc_drv_mem_reuse_mem_state(unit,&act_mem, &lock_mem); 20200 #endif 20201 if (soc->memState[lock_mem].lock != NULL) { 20202 sal_mutex_destroy(soc->memState[lock_mem].lock); 20203 soc->memState[lock_mem].lock = NULL; 20204 } 20205 #ifdef BCM_ESW_SUPPORT 20206 /* Share the lock */ 20207 soc_drv_mem_sync_mapped_lock(unit, mem, soc->memState[lock_mem].lock); 20208 #endif 20209 } 20210 20211 #ifdef BCM_ESW_SUPPORT 20212 if (SOC_MEM_IS_VALID(unit, ING_DEVICE_PORTm) && 20213 !SOC_MEM_IS_VALID(unit, PORT_TABm)) { 20214 soc->memState[PORT_TABm].lock = soc->memState[ING_DEVICE_PORTm].lock; 20215 } 20216 #endif 20217 20218 if (soc->schanMutex) { 20219 sal_mutex_destroy(soc->schanMutex); 20220 soc->schanMutex = NULL; 20221 } 20222 20223 #ifdef BCM_CMICM_SUPPORT 20224 if (soc->fschanMutex) { 20225 sal_mutex_destroy(soc->fschanMutex); 20226 soc->fschanMutex = NULL; 20227 } 20228 #ifdef BCM_CCMDMA_SUPPORT 20229 for (cmc = 0; cmc < SOC_PCI_CMCS_NUM(unit); cmc++) { 20230 if (soc->ccmDmaIntr[cmc]) { 20231 sal_sem_destroy(soc->ccmDmaIntr[cmc]); 20232 soc->ccmDmaIntr[cmc] = NULL; 20233 } 20234 } 20235 #endif 20236 if (soc_feature(unit, soc_feature_cmicm)) { 20237 soc_cmic_uc_msg_stop(unit); 20238 } 20239 #endif 20240 #ifdef BCM_CMICX_SUPPORT 20241 if (soc_feature(unit, soc_feature_cmicx)) { 20242 soc_cmic_uc_msg_stop(unit); 20243 } 20244 #endif 20245 20246 for (cmc = 0; cmc < SOC_PCI_CMCS_NUM(unit) + 1; cmc++) { 20247 if (soc->schanIntr[cmc]) { 20248 sal_sem_destroy(soc->schanIntr[cmc]); 20249 soc->schanIntr[cmc] = NULL; 20250 } 20251 } 20252 20253 if (soc->miimMutex) { 20254 sal_mutex_destroy(soc->miimMutex); 20255 soc->miimMutex = NULL; 20256 } 20257 20258 (void)soc_sbusdma_lock_deinit(unit); 20259 20260 #ifdef BCM_CMICM_SUPPORT 20261 for (cmc = 0; cmc < SOC_PCI_CMCS_NUM(unit); cmc++) { 20262 int ch; 20263 for (ch = 0; ch < N_DMA_CHAN; ch++) { 20264 if (soc->fifoDmaMutexs[cmc][ch]) { 20265 sal_mutex_destroy(soc->fifoDmaMutexs[cmc][ch]); 20266 soc->fifoDmaMutexs[cmc][ch] = NULL; 20267 } 20268 if (soc->fifoDmaIntrs[cmc][ch]) { 20269 sal_sem_destroy(soc->fifoDmaIntrs[cmc][ch]); 20270 soc->fifoDmaIntrs[cmc][ch] = NULL; 20271 } 20272 } 20273 } 20274 #endif 20275 20276 if (soc->miimIntr) { 20277 sal_sem_destroy(soc->miimIntr); 20278 soc->miimIntr = NULL; 20279 } 20280 20281 for (ix = 0; ix < 3; ix++) { 20282 if (soc->memCmdIntr[ix]) { 20283 sal_sem_destroy(soc->memCmdIntr[ix]); 20284 soc->memCmdIntr[ix] = NULL; 20285 } 20286 } 20287 20288 if (soc->arl_notify) { 20289 sal_sem_destroy(soc->arl_notify); 20290 soc->arl_notify = NULL; 20291 } 20292 20293 #if defined(BCM_TRIUMPH3_SUPPORT) 20294 if (soc_feature(unit, soc_feature_esm_correction)) { 20295 SOC_IF_ERROR_RETURN(soc_tr3_esm_recovery_stop(unit)); 20296 if (soc->esm_recovery_notify) { 20297 sal_sem_destroy(soc->esm_recovery_notify); 20298 soc->esm_recovery_notify = NULL; 20299 } 20300 if (soc->esm_lock) { 20301 sal_mutex_destroy(soc->esm_lock); 20302 soc->esm_lock = NULL; 20303 } 20304 } 20305 #endif 20306 20307 #ifdef BCM_XGS_SWITCH_SUPPORT 20308 if (NULL != soc->l2x_notify) { 20309 sal_sem_destroy(soc->l2x_notify); 20310 soc->l2x_notify = NULL; 20311 } 20312 if (NULL != soc->l2x_del_sync) { 20313 sal_mutex_destroy(soc->l2x_del_sync); 20314 soc->l2x_del_sync = NULL; 20315 } 20316 if (NULL != soc->l2x_lock) { 20317 sal_sem_destroy(soc->l2x_lock); 20318 soc->l2x_lock = NULL; 20319 } 20320 soc->l2x_pid = SAL_THREAD_ERROR; 20321 soc->l2x_interval = 0; 20322 20323 #ifdef BCM_TOMAHAWK3_SUPPORT 20324 if (SOC_IS_TOMAHAWK3(unit)) { 20325 /* Clear L2 learning related data */ 20326 soc->l2x_learn_pid = SAL_THREAD_ERROR; 20327 soc->l2x_learn_interval = 0; 20328 if (NULL != soc->l2x_lrn_shadow_mutex) { 20329 sal_mutex_destroy(soc->l2x_lrn_shadow_mutex); 20330 soc->l2x_lrn_shadow_mutex = NULL; 20331 } 20332 20333 soc->lrn_cache_threshold = -1; 20334 soc->lrn_cache_intr_ctl = -1; 20335 soc->lrn_cache_clr_on_rd = -1; 20336 } 20337 #endif /* BCM_TOMAHAWK3_SUPPORT */ 20338 #ifdef BCM_TSN_SUPPORT 20339 if (NULL != soc->l2x_sr_sync) { 20340 sal_mutex_destroy(soc->l2x_sr_sync); 20341 soc->l2x_sr_sync = NULL; 20342 } 20343 #endif /* BCM_TSN_SUPPORT */ 20344 20345 #ifdef BCM_TRIUMPH3_SUPPORT 20346 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_TOMAHAWKX(unit) || 20347 SOC_IS_TRIDENT3X(unit)) { 20348 if (NULL != soc->l2x_age_notify) { 20349 sal_sem_destroy(soc->l2x_age_notify); 20350 soc->l2x_age_notify = NULL; 20351 } 20352 soc->l2x_age_pid = SAL_THREAD_ERROR; 20353 soc->l2x_age_interval = 0; 20354 soc->l2x_agetime_adjust_usec = 0; 20355 soc->l2x_agetime_curr_timeblk = 0; 20356 soc->l2x_agetime_curr_timeblk_usec = 0; 20357 soc->l2x_prev_age_timeout = 0; 20358 } 20359 #endif 20360 #ifdef BCM_TRIDENT2_SUPPORT 20361 if SOC_IS_TRIDENT2X(unit) { 20362 if (NULL != soc->l2x_age_notify) { 20363 sal_sem_destroy(soc->l2x_age_notify); 20364 soc->l2x_age_notify = NULL; 20365 } 20366 if (NULL != soc->l2x_age_sync) { 20367 sal_sem_destroy(soc->l2x_age_sync); 20368 soc->l2x_age_sync = NULL; 20369 } 20370 soc->l2x_age_pid = SAL_THREAD_ERROR; 20371 soc->l2x_age_interval = 0; 20372 soc->l2x_age_enable = 0; 20373 soc->l2x_sw_aging = 0; 20374 } 20375 #endif 20376 #endif /* BCM_XGS_SWITCH_SUPPORT */ 20377 /* Destroy L3 module protection mutex. */ 20378 if (NULL != soc->l3x_lock) { 20379 sal_mutex_destroy(soc->l3x_lock); 20380 soc->l3x_lock = NULL; 20381 } 20382 20383 /* Destroy FP module protection mutex. */ 20384 if (NULL != soc->fp_lock) { 20385 sal_mutex_destroy(soc->fp_lock); 20386 soc->fp_lock = NULL; 20387 } 20388 20389 #ifdef INCLUDE_XFLOW_MACSEC 20390 if (soc_feature(unit, soc_feature_xflow_macsec)) { 20391 /* Destroy XFLOW_MACSEC module protection mutex. */ 20392 if (NULL != soc->xflow_macsec_lock) { 20393 sal_mutex_destroy(soc->xflow_macsec_lock); 20394 soc->xflow_macsec_lock = NULL; 20395 } 20396 } 20397 #endif 20398 20399 if (soc->ipfixIntr) { 20400 sal_sem_destroy(soc->ipfixIntr); 20401 soc->ipfixIntr = NULL; 20402 } 20403 20404 #if defined(INCLUDE_REGEX) 20405 if (soc->ftreportIntr) { 20406 sal_sem_destroy(soc->ftreportIntr); 20407 soc->ftreportIntr = NULL; 20408 } 20409 #endif 20410 20411 #ifdef BCM_FLOWTRACKER_EXPORT_FIFO_SUPPORT 20412 if (soc->ftExportIntr) { 20413 sal_sem_destroy(soc->ftExportIntr); 20414 soc->ftExportIntr = NULL; 20415 } 20416 #endif /* BCM_FLOWTRACKER_EXPORT_FIFO_SUPPORT */ 20417 soc->ctr_evict_interval = 0; 20418 if (soc->ctrEvictIntr) { 20419 sal_sem_destroy(soc->ctrEvictIntr); 20420 soc->ctrEvictIntr = NULL; 20421 } 20422 20423 if (soc->socControlMutex) { 20424 sal_mutex_destroy(soc->socControlMutex); 20425 soc->socControlMutex = NULL; 20426 } 20427 20428 if (soc->mem_ser_info_lock) { 20429 sal_mutex_destroy(soc->mem_ser_info_lock); 20430 soc->mem_ser_info_lock = NULL; 20431 } 20432 20433 if (soc->egressMeteringMutex) { 20434 sal_mutex_destroy(soc->egressMeteringMutex); 20435 soc->egressMeteringMutex = NULL; 20436 } 20437 20438 if (soc->schan_wb_mutex != NULL) { 20439 sal_mutex_destroy(soc->schan_wb_mutex); 20440 soc->schan_wb_mutex = NULL; 20441 } 20442 20443 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_APACHE_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 20444 if (SOC_IS_KATANAX(unit) || SOC_IS_TRIDENT2X(unit) || 20445 SOC_IS_TITAN2X(unit) || SOC_IS_TRIUMPH3(unit)) { 20446 /* Destroy llsMutex */ 20447 if (soc->llsMutex !=NULL) { 20448 sal_mutex_destroy(soc->llsMutex); 20449 soc->llsMutex = NULL; 20450 } 20451 } 20452 #endif 20453 20454 #if defined(BCM_TOMAHAWK_SUPPORT) 20455 if (SOC_IS_TOMAHAWKX(unit)) { 20456 /* Destroy idb_lock */ 20457 if (soc->idb_lock !=NULL) { 20458 sal_mutex_destroy(soc->idb_lock); 20459 soc->idb_lock = NULL; 20460 } 20461 } 20462 #endif 20463 #ifdef INCLUDE_MEM_SCAN 20464 if (soc->mem_scan_lock != NULL) { 20465 sal_mutex_destroy(soc->mem_scan_lock); 20466 soc->mem_scan_lock = NULL; 20467 } 20468 #endif 20469 20470 if (soc->ser_err_stat_lock != NULL) { 20471 sal_mutex_destroy(soc->ser_err_stat_lock); 20472 soc->ser_err_stat_lock = NULL; 20473 } 20474 20475 /* Destroy UDF module protection mutex. */ 20476 if (NULL != soc->udf_lock) { 20477 sal_mutex_destroy(soc->udf_lock); 20478 soc->udf_lock = NULL; 20479 } 20480 20481 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) 20482 if (soc_feature(unit, soc_feature_epc_linkflap_recover)) { 20483 /* Destroy linkscan_modport_map_lock_lock */ 20484 if (soc->linkscan_modport_map_lock !=NULL) { 20485 sal_mutex_destroy(soc->linkscan_modport_map_lock); 20486 soc->linkscan_modport_map_lock = NULL; 20487 } 20488 } 20489 #endif /* #(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) */ 20490 if (soc->tcam_info) { 20491 sal_free(soc->tcam_info); 20492 } 20493 20494 /* MMU LLS usage map */ 20495 for (ix = 0; ix < SOC_MAX_NUM_PORTS; ix++) { 20496 #if defined(BCM_KATANA2_SUPPORT) 20497 if (soc->port_lls_s0_bmap[ix] != NULL) { 20498 sal_free(soc->port_lls_s0_bmap[ix]); 20499 } 20500 #endif /* BCM_KATANA2_SUPPORT */ 20501 #if defined(BCM_KATANA2_SUPPORT) || defined(BCM_APACHE_SUPPORT) 20502 if (soc->port_lls_s1_bmap[ix] != NULL) { 20503 sal_free(soc->port_lls_s1_bmap[ix]); 20504 } 20505 #endif /* BCM_KATANA2_SUPPORT || BCM_APACHE_SUPPORT*/ 20506 if (soc->port_lls_l0_bmap[ix] != NULL) { 20507 sal_free(soc->port_lls_l0_bmap[ix]); 20508 } 20509 if (soc->port_lls_l1_bmap[ix] != NULL) { 20510 sal_free(soc->port_lls_l1_bmap[ix]); 20511 } 20512 if (soc->port_lls_l2_bmap[ix] != NULL) { 20513 sal_free(soc->port_lls_l2_bmap[ix]); 20514 } 20515 } 20516 20517 #ifdef BCM_TRIUMPH_SUPPORT 20518 if (soc->ext_l2_ppa_info != NULL) { 20519 sal_free(soc->ext_l2_ppa_info); 20520 soc->ext_l2_ppa_info = NULL; 20521 } 20522 if (soc->ext_l2_ppa_vlan != NULL) { 20523 sal_free(soc->ext_l2_ppa_vlan); 20524 soc->ext_l2_ppa_vlan = NULL; 20525 } 20526 #endif /* BCM_TRIUMPH_SUPPORT */ 20527 20528 if (soc->tdm_info != NULL) { 20529 sal_free(soc->tdm_info); 20530 soc->tdm_info = NULL; 20531 } 20532 20533 if (soc->soc_wc_ucode_dma_buf != NULL) { 20534 soc_cm_sfree(unit, soc->soc_wc_ucode_dma_buf); 20535 soc->soc_wc_ucode_dma_buf = NULL; 20536 } 20537 if (soc->soc_wc_ucode_dma_buf2 != NULL) { 20538 soc_cm_sfree(unit, soc->soc_wc_ucode_dma_buf2); 20539 soc->soc_wc_ucode_dma_buf2 = NULL; 20540 } 20541 20542 #if defined(BCM_RCPU_SUPPORT) && defined(BCM_XGS3_SWITCH_SUPPORT) 20543 if (SOC_IS_RCPU_ONLY(unit)) { 20544 soc_rcpu_deinit(unit); 20545 } 20546 #endif /* !defined(PLISIM) */ 20547 /* In current SDK, l3 defip index is saved in soc_control block. 20548 * the relative resource has to be released before soc_control 20549 * block free */ 20550 SOC_IF_ERROR_RETURN(soc_l3_defip_indexes_deinit(unit)); 20551 20552 sal_free(SOC_PERSIST(unit)); 20553 SOC_PERSIST(unit) = NULL; 20554 20555 sal_free(SOC_CONTROL(unit)); 20556 SOC_CONTROL(unit) = NULL; 20557 20558 #ifdef BCM_WARM_BOOT_SUPPORT 20559 /* Second times detach cause SOC_E_CONFIG so not CheckingFalseReturn value*/ 20560 soc_scache_detach(unit); 20561 #endif /* BCM_WARM_BOOT_SUPPORT */ 20562 20563 if (--soc_ndev_attached == 0) { 20564 /* Work done after the last SOC device is detached. */ 20565 /* (currently nothing) */ 20566 } 20567 20568 return SOC_E_NONE; 20569 } 20570 20571 /* 20572 * Function: 20573 * _soc_functions_find 20574 * Purpose: 20575 * Return function array corresponding to the driver 20576 * Returns: 20577 * Pointer to static function array soc_functions_t 20578 */ 20579 20580 STATIC soc_functions_t * 20581 _soc_functions_find(soc_driver_t *drv) 20582 { 20583 switch (drv->type) { 20584 20585 #ifdef BCM_HERCULES15_SUPPORT 20586 case SOC_CHIP_BCM5675_A0: return &soc_hercules15_drv_funs; 20587 #endif 20588 20589 #ifdef BCM_FIREBOLT_SUPPORT 20590 case SOC_CHIP_BCM56504_A0: return &soc_firebolt_drv_funs; 20591 case SOC_CHIP_BCM56504_B0: return &soc_firebolt_drv_funs; 20592 case SOC_CHIP_BCM56102_A0: return &soc_firebolt_drv_funs; 20593 case SOC_CHIP_BCM56304_B0: return &soc_firebolt_drv_funs; 20594 case SOC_CHIP_BCM56112_A0: return &soc_firebolt_drv_funs; 20595 case SOC_CHIP_BCM56314_A0: return &soc_firebolt_drv_funs; 20596 case SOC_CHIP_BCM56514_A0: return &soc_firebolt_drv_funs; 20597 #ifdef BCM_RAPTOR_SUPPORT 20598 case SOC_CHIP_BCM56218_A0: return &soc_firebolt_drv_funs; 20599 case SOC_CHIP_BCM56224_A0: return &soc_firebolt_drv_funs; 20600 case SOC_CHIP_BCM56224_B0: return &soc_firebolt_drv_funs; 20601 case SOC_CHIP_BCM53314_A0: return &soc_firebolt_drv_funs; 20602 case SOC_CHIP_BCM53324_A0: return &soc_firebolt_drv_funs; 20603 #endif 20604 #ifdef BCM_BRADLEY_SUPPORT 20605 case SOC_CHIP_BCM56800_A0: return &soc_bradley_drv_funs; 20606 case SOC_CHIP_BCM56820_A0: return &soc_bradley_drv_funs; 20607 case SOC_CHIP_BCM56725_A0: return &soc_bradley_drv_funs; 20608 #endif 20609 #ifdef BCM_SHADOW_SUPPORT 20610 case SOC_CHIP_BCM88732_A0: return &soc_shadow_drv_funs; 20611 #endif 20612 #ifdef BCM_TRIUMPH_SUPPORT 20613 case SOC_CHIP_BCM56624_A0: return &soc_triumph_drv_funs; 20614 case SOC_CHIP_BCM56624_B0: return &soc_triumph_drv_funs; 20615 #endif 20616 #ifdef BCM_VALKYRIE_SUPPORT 20617 case SOC_CHIP_BCM56680_A0: return &soc_valkyrie_drv_funs; 20618 case SOC_CHIP_BCM56680_B0: return &soc_valkyrie_drv_funs; 20619 #endif 20620 #ifdef BCM_TRIUMPH2_SUPPORT 20621 case SOC_CHIP_BCM56634_A0: return &soc_triumph2_drv_funs; 20622 case SOC_CHIP_BCM56634_B0: return &soc_triumph2_drv_funs; 20623 case SOC_CHIP_BCM56524_A0: return &soc_triumph2_drv_funs; 20624 case SOC_CHIP_BCM56524_B0: return &soc_triumph2_drv_funs; 20625 case SOC_CHIP_BCM56685_A0: return &soc_triumph2_drv_funs; 20626 case SOC_CHIP_BCM56685_B0: return &soc_triumph2_drv_funs; 20627 #endif 20628 #ifdef BCM_ENDURO_SUPPORT 20629 case SOC_CHIP_BCM56334_A0: return &soc_enduro_drv_funs; 20630 case SOC_CHIP_BCM56334_B0: return &soc_enduro_drv_funs; 20631 #endif 20632 #ifdef BCM_HURRICANE_SUPPORT 20633 case SOC_CHIP_BCM56142_A0: return &soc_hurricane_drv_funs; 20634 #endif 20635 #ifdef BCM_HURRICANE2_SUPPORT 20636 case SOC_CHIP_BCM56150_A0: return &soc_hurricane2_drv_funs; 20637 #endif 20638 #ifdef BCM_TRIDENT_SUPPORT 20639 case SOC_CHIP_BCM56840_A0: return &soc_trident_drv_funs; 20640 case SOC_CHIP_BCM56840_B0: return &soc_trident_drv_funs; 20641 #endif 20642 #ifdef BCM_TRIDENT2_SUPPORT 20643 case SOC_CHIP_BCM56850_A0: return &soc_trident2_drv_funs; 20644 case SOC_CHIP_BCM56860_A0: return &soc_trident2_drv_funs; 20645 #endif 20646 #ifdef BCM_TOMAHAWK_SUPPORT 20647 case SOC_CHIP_BCM56960_A0: return &soc_tomahawk_drv_funs; 20648 case SOC_CHIP_BCM56965_A0: return &soc_tomahawk_drv_funs; 20649 case SOC_CHIP_BCM56965_A1: return &soc_tomahawk_drv_funs; 20650 case SOC_CHIP_BCM56970_A0: return &soc_tomahawk_drv_funs; 20651 #endif 20652 #ifdef BCM_TOMAHAWK3_SUPPORT 20653 case SOC_CHIP_BCM56980_A0: return &soc_tomahawk3_drv_funs; 20654 case SOC_CHIP_BCM56980_B0: return &soc_tomahawk3_drv_funs; 20655 #endif 20656 #ifdef BCM_TRIDENT3_SUPPORT 20657 case SOC_CHIP_BCM56870_A0: return &soc_trident3_drv_funs; 20658 case SOC_CHIP_BCM56873_A0: return &soc_trident3_drv_funs; 20659 #endif 20660 #ifdef BCM_HELIX5_SUPPORT 20661 case SOC_CHIP_BCM56370_A0: return &soc_helix5_drv_funs; 20662 #endif 20663 #ifdef BCM_MAVERICK2_SUPPORT 20664 case SOC_CHIP_BCM56770_A0: return &soc_maverick2_drv_funs; 20665 case SOC_CHIP_BCM56771_A0: return &soc_maverick2_drv_funs; 20666 #endif 20667 #ifdef BCM_APACHE_SUPPORT 20668 case SOC_CHIP_BCM56560_A0: return &soc_apache_drv_funs; 20669 case SOC_CHIP_BCM56560_B0: return &soc_apache_drv_funs; 20670 #endif 20671 #ifdef BCM_MONTEREY_SUPPORT 20672 case SOC_CHIP_BCM56670_A0: return &soc_monterey_drv_funs; 20673 case SOC_CHIP_BCM56670_B0: return &soc_monterey_drv_funs; 20674 #endif 20675 #ifdef BCM_TRIUMPH3_SUPPORT 20676 case SOC_CHIP_BCM56640_A0: return &soc_triumph3_drv_funs; 20677 case SOC_CHIP_BCM56640_B0: return &soc_triumph3_drv_funs; 20678 #endif 20679 #ifdef BCM_HELIX4_SUPPORT 20680 case SOC_CHIP_BCM56340_A0: return &soc_helix4_drv_funs; 20681 #endif 20682 #ifdef BCM_KATANA_SUPPORT 20683 case SOC_CHIP_BCM56440_A0: return &soc_katana_drv_funs; 20684 case SOC_CHIP_BCM56440_B0: return &soc_katana_drv_funs; 20685 #endif 20686 #ifdef BCM_KATANA2_SUPPORT 20687 case SOC_CHIP_BCM56450_A0: return &soc_katana2_drv_funs; 20688 case SOC_CHIP_BCM56450_B0: return &soc_katana2_drv_funs; 20689 case SOC_CHIP_BCM56450_B1: return &soc_katana2_drv_funs; 20690 #endif 20691 #ifdef BCM_GREYHOUND_SUPPORT 20692 case SOC_CHIP_BCM53400_A0: return &soc_greyhound_drv_funs; 20693 #endif 20694 20695 #ifdef BCM_HURRICANE3_SUPPORT 20696 case SOC_CHIP_BCM56160_A0: return &soc_hurricane3_drv_funs; 20697 case SOC_CHIP_BCM53540_A0: return &soc_wolfhound2_drv_funs; 20698 #endif 20699 #ifdef BCM_GREYHOUND2_SUPPORT 20700 case SOC_CHIP_BCM53570_A0: return &soc_greyhound2_drv_funs; 20701 case SOC_CHIP_BCM53570_B0: return &soc_greyhound2_drv_funs; 20702 #endif 20703 20704 #ifdef BCM_SABER2_SUPPORT 20705 case SOC_CHIP_BCM56260_A0: return &soc_saber2_drv_funs; 20706 case SOC_CHIP_BCM56260_B0: return &soc_saber2_drv_funs; 20707 #endif 20708 #ifdef BCM_METROLITE_SUPPORT 20709 case SOC_CHIP_BCM56270_A0: return &soc_metrolite_drv_funs; 20710 #endif 20711 #endif 20712 default: return NULL; 20713 } 20714 } 20715 20716 /* Warning: This function and _soc_mem_lock_map should be used in pairs */ 20717 STATIC int 20718 _soc_mem_lock_create(int unit, soc_control_t *soc) { 20719 soc_mem_t mem; 20720 20721 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 20722 /* 20723 * should only create mutexes for valid memories. 20724 */ 20725 if (!SOC_MEM_IS_VALID(unit, mem)) { 20726 continue; 20727 } 20728 /* Handle many to one state sharing */ 20729 if (soc->memState[mem].lock == NULL) { 20730 char mem_name[128]; 20731 #if !defined(SOC_NO_NAMES) 20732 #if defined(BCM_ESW_SUPPORT) || \ 20733 defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) 20734 sal_strncpy(mem_name, SOC_MEM_NAME(unit, mem), 20735 sizeof(mem_name)-1); 20736 #else 20737 sal_snprintf(mem_name, sizeof(mem_name), "%s%d", 20738 "mem_mutex_", mem); 20739 #endif 20740 #else 20741 sal_snprintf(mem_name, sizeof(mem_name), "%s%d", 20742 "mem_mutex_", mem); 20743 #endif 20744 if ((soc->memState[mem].lock = 20745 sal_mutex_create(mem_name)) == NULL) { 20746 return -1; 20747 } 20748 /* Set cache copy pointers to NULL */ 20749 sal_memset(soc->memState[mem].cache, 20750 0, sizeof(soc->memState[mem].cache)); 20751 } 20752 } 20753 return 0; 20754 } 20755 #ifdef BCM_ESW_SUPPORT 20756 STATIC void 20757 _soc_mem_lock_map(int unit, soc_control_t *soc) 20758 { 20759 soc_mem_t mem, act_mem, lock_mem; 20760 20761 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 20762 if (!SOC_MEM_IS_VALID(unit, mem)) { 20763 continue; 20764 } 20765 act_mem = mem; 20766 lock_mem = mem; 20767 soc_drv_mem_reuse_mem_state(unit, &act_mem, &lock_mem); 20768 /* In function _soc_mem_lock_create, all memory semaphores are created */ 20769 if (mem != lock_mem) { 20770 if (soc->memState[mem].lock != NULL) { 20771 sal_mutex_destroy(soc->memState[mem].lock); 20772 soc->memState[mem].lock = NULL; 20773 } 20774 /* We can't add _SOC_MEM_SYNC_MAPPED_LOCK(unit, lock_mem, soc->memState[lock_mem].lock) 20775 * between next "for" cluase to here. 20776 * First time, when L3_ENTRY_ONLYm comes, and Lock of L3_ENTRY_IPV4_MULTICASTm is mapped to memories 20777 * L3_ENTRY_ONLYm/L3_ENTRY_IPV4_UNICASTm/L3_ENTRY_IPV6_UNICASTm/L3_ENTRY_IPV6_MULTICASTm. 20778 * Second time, when L3_ENTRY_IPV4_UNICASTm comes, Lock of L3_ENTRY_IPV4_MULTICASTm will be destoryed. 20779 * That's so bad. 20780 */ 20781 } 20782 } 20783 20784 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 20785 if (!SOC_MEM_IS_VALID(unit, mem)) { 20786 continue; 20787 } 20788 act_mem = mem; 20789 lock_mem = mem; 20790 soc_drv_mem_reuse_mem_state(unit, &act_mem, &lock_mem); 20791 if (mem != lock_mem) { 20792 soc_drv_mem_sync_mapped_lock(unit, lock_mem, soc->memState[lock_mem].lock); 20793 } 20794 } 20795 20796 if (SOC_MEM_IS_VALID(unit, ING_DEVICE_PORTm) && 20797 !SOC_MEM_IS_VALID(unit, PORT_TABm)) { 20798 soc->memState[PORT_TABm].lock = soc->memState[ING_DEVICE_PORTm].lock; 20799 } 20800 20801 return; 20802 } 20803 #endif 20804 20805 /* 20806 * Function: 20807 * soc_attach 20808 * Purpose: 20809 * Initialize the soc_control_t structure for a device, 20810 * allocating all memory and semaphores required. 20811 * Parameters: 20812 * unit - StrataSwitch unit # 20813 * detach - Callback function called on detach. 20814 * Returns: 20815 * SOC_E_XXX 20816 * Notes: 20817 * No chip initialization is done other than masking all interrupts, 20818 * see soc_init or soc_reset_init. 20819 */ 20820 int 20821 soc_attach(int unit) 20822 { 20823 soc_control_t *soc; 20824 soc_persist_t *sop; 20825 int rv = SOC_E_MEMORY; 20826 soc_mem_t mem; 20827 uint16 dev_id, drv_dev_id; 20828 uint8 rev_id, drv_rev_id; 20829 soc_port_t port; 20830 int ix; 20831 ipoll_handler_t iph = soc_intr; 20832 uint8 table_dma_enable=0; 20833 uint8 tslam_dma_enable=0; 20834 int enable; 20835 int cmc; 20836 char *mode = NULL; 20837 #ifdef BCM_CMICM_SUPPORT 20838 int ch; 20839 #endif 20840 20841 #ifdef BCM_KATANA_SUPPORT 20842 uint32 saber_pool_size[BCM_SABER_MAX_COUNTER_DIRECTION] = 20843 {511, 255}; 20844 soc_mem_t saber_counter_table[BCM_SABER_MAX_COUNTER_DIRECTION] 20845 [BCM_SABER_MAX_COUNTER_POOL]={ 20846 {ING_FLEX_CTR_COUNTER_TABLE_0m, 20847 ING_FLEX_CTR_COUNTER_TABLE_1m, 20848 ING_FLEX_CTR_COUNTER_TABLE_2m, 20849 ING_FLEX_CTR_COUNTER_TABLE_3m, 20850 ING_FLEX_CTR_COUNTER_TABLE_4m, 20851 ING_FLEX_CTR_COUNTER_TABLE_5m, 20852 ING_FLEX_CTR_COUNTER_TABLE_6m, 20853 ING_FLEX_CTR_COUNTER_TABLE_7m}, 20854 {EGR_FLEX_CTR_COUNTER_TABLE_0m, 20855 EGR_FLEX_CTR_COUNTER_TABLE_1m, 20856 EGR_FLEX_CTR_COUNTER_TABLE_2m, 20857 EGR_FLEX_CTR_COUNTER_TABLE_3m, 20858 EGR_FLEX_CTR_COUNTER_TABLE_4m, 20859 EGR_FLEX_CTR_COUNTER_TABLE_5m, 20860 EGR_FLEX_CTR_COUNTER_TABLE_6m, 20861 EGR_FLEX_CTR_COUNTER_TABLE_7m}}; 20862 uint32 saber_counter_direction=0; 20863 uint32 saber_counter_pool=0; 20864 #endif 20865 soc_pbmp_t pbmp_all; 20866 SOC_PBMP_CLEAR(pbmp_all); 20867 20868 LOG_INFO(BSL_LS_SOC_PCI, 20869 (BSL_META_U(unit, 20870 "soc_attach: unit %d\n"), unit)); 20871 20872 /* 20873 * Allocate soc_control and soc_persist if not already. 20874 */ 20875 20876 if (SOC_CONTROL(unit) == NULL) { 20877 SOC_CONTROL(unit) = 20878 sal_alloc(sizeof (soc_control_t), "soc_control"); 20879 if (SOC_CONTROL(unit) == NULL) { 20880 return SOC_E_MEMORY; 20881 } 20882 sal_memset(SOC_CONTROL(unit), 0, sizeof (soc_control_t)); 20883 } 20884 20885 SOC_PERSIST(unit) = sal_alloc(sizeof (soc_persist_t), "soc_persist"); 20886 if (NULL == SOC_PERSIST(unit)) { 20887 return SOC_E_MEMORY; 20888 } 20889 20890 sal_memset(SOC_PERSIST(unit), 0, sizeof (soc_persist_t)); 20891 20892 #ifdef BCM_WARM_BOOT_SUPPORT 20893 SOC_IF_ERROR_RETURN(soc_stable_attach(unit)); 20894 #endif /* BCM_WARM_BOOT_SUPPORT */ 20895 20896 soc = SOC_CONTROL(unit); 20897 sop = SOC_PERSIST(unit); 20898 sop->version = 1; 20899 20900 soc_cm_get_id(unit, &dev_id, &rev_id); 20901 soc_cm_get_id_driver(dev_id, rev_id, &drv_dev_id, &drv_rev_id); 20902 20903 /* 20904 * Instantiate the driver -- Verify chip revision matches driver 20905 * compilation revision. 20906 */ 20907 soc->chip_driver = soc_chip_driver_find(dev_id, rev_id); 20908 20909 if (soc->chip_driver == NULL) { 20910 LOG_ERROR(BSL_LS_SOC_COMMON, 20911 (BSL_META_U(unit, 20912 "soc_attach: unit %d has no driver " 20913 "(device 0x%04x rev 0x%02x)\n"), 20914 unit, dev_id, rev_id)); 20915 return SOC_E_UNAVAIL; 20916 } 20917 20918 soc->soc_functions = _soc_functions_find(soc->chip_driver); 20919 20920 if (soc->soc_functions == NULL) { 20921 LOG_ERROR(BSL_LS_SOC_COMMON, 20922 (BSL_META_U(unit, 20923 "soc_attach: unit %d has no functions\n"), 20924 unit)); 20925 return SOC_E_INTERNAL; 20926 } 20927 20928 /* Start to allow this unit to run DPCs */ 20929 sal_dpc_enable(INT_TO_PTR(unit)); 20930 20931 #ifdef INCLUDE_RCPU 20932 if (soc_property_get(unit, spn_PCI2EB_OVERRIDE, 0)) { 20933 soc->remote_cpu = TRUE; 20934 } else { 20935 soc->remote_cpu = FALSE; 20936 } 20937 20938 /* Is this an RCPU Only unit? */ 20939 if (soc_property_get(unit, spn_RCPU_ONLY, 0) || 20940 (soc_cm_get_bus_type(unit) & SOC_RCPU_DEV_TYPE)) { 20941 soc->remote_cpu = TRUE; 20942 soc->soc_flags |= SOC_F_RCPU_ONLY; 20943 } 20944 #endif /* INCLUDE_RCPU */ 20945 20946 soc->soc_rcpu_schan_op = NULL; 20947 20948 soc->ev_cb_head = NULL; 20949 20950 /* Set feature cache, since used by mutex creation */ 20951 soc_feature_init(unit); 20952 SOC_PCI_CMCS_NUM(unit) = soc_property_uc_get(unit, 0, spn_PCI_CMCS_NUM, 1); 20953 /* Install the Interrupt Handler */ 20954 /* Make sure interrupts are masked before connecting line. */ 20955 #ifdef BCM_CMICX_SUPPORT 20956 if (soc_feature(unit, soc_feature_cmicx)) { 20957 int arm; 20958 /* initialize the interrupt framework */ 20959 SOC_IF_ERROR_RETURN(soc_cmic_intr_init(unit)); 20960 20961 SOC_CMCS_NUM(unit) = 2; 20962 20963 if (SAL_BOOT_SIMULATION) { 20964 SOC_PCI_CMCS_NUM(unit) = soc_property_uc_get(unit, 0, 20965 spn_PCI_CMCS_NUM, 2); 20966 } 20967 20968 if ((SOC_PCI_CMCS_NUM(unit) < 1) || 20969 (SOC_PCI_CMCS_NUM(unit) > SOC_CMCS_NUM(unit))) { 20970 LOG_ERROR(BSL_LS_SOC_COMMON, 20971 (BSL_META_U(unit, 20972 "soc_attach: " 20973 "PCI CMCS NUM %d not between 1 to %d\n"), 20974 SOC_PCI_CMCS_NUM(unit), SOC_CMCS_NUM(unit))); 20975 return SOC_E_PARAM; 20976 } 20977 SOC_PCI_CMC(unit) = soc_property_uc_get(unit, 0, spn_PCI_CMC, 0); 20978 if (SOC_PCI_CMC(unit) >= SOC_CMCS_NUM(unit)) { 20979 LOG_ERROR(BSL_LS_SOC_COMMON, 20980 (BSL_META_U(unit, 20981 "soc_attach: " 20982 "PCI CMC %d exceeds maximum of %d\n"), 20983 SOC_PCI_CMC(unit), SOC_CMCS_NUM(unit))); 20984 return SOC_E_PARAM; 20985 } 20986 arm = 0; 20987 for (ix = 0; ix < SOC_CMCS_NUM(unit); ix++) { 20988 if (SOC_PCI_CMC(unit) != ix) { 20989 SOC_ARM_CMC(unit, arm) = ix; 20990 arm++; 20991 } 20992 } 20993 20994 /* Disable all interrupts */ 20995 soc_cmic_intr_all_disable(unit); 20996 20997 iph = soc_cmicx_intr; 20998 } else 20999 #endif 21000 #ifdef BCM_CMICM_SUPPORT 21001 if (soc_feature(unit, soc_feature_cmicm)) { 21002 int arm; 21003 21004 /* Initialize PCI/iProc based host irq offset */ 21005 if (soc_cm_get_bus_type(unit) & SOC_AXI_DEV_TYPE) { 21006 soc_cmicm_ihost_irq_offset_set(unit); 21007 } else { 21008 soc_cmicm_ihost_irq_offset_reset(unit); 21009 } 21010 SOC_CMCS_NUM(unit) = 3; 21011 21012 if ((SOC_PCI_CMCS_NUM(unit) < 1) || 21013 (SOC_PCI_CMCS_NUM(unit) > SOC_CMCS_NUM(unit))) { 21014 LOG_ERROR(BSL_LS_SOC_COMMON, 21015 (BSL_META_U(unit, 21016 "soc_attach: " 21017 "specified PCI CMCS NUM %d must be within 1 to %d\n"), 21018 SOC_PCI_CMCS_NUM(unit), SOC_CMCS_NUM(unit))); 21019 return SOC_E_PARAM; 21020 } 21021 SOC_PCI_CMC(unit) = soc_property_uc_get(unit, 0, spn_PCI_CMC, 0); 21022 if (SOC_PCI_CMC(unit) >= SOC_CMCS_NUM(unit)) { 21023 LOG_ERROR(BSL_LS_SOC_COMMON, 21024 (BSL_META_U(unit, 21025 "soc_attach: " 21026 "specified PCI CMC %d exceeds maximum of %d\n"), 21027 SOC_PCI_CMC(unit), SOC_CMCS_NUM(unit))); 21028 return SOC_E_PARAM; 21029 } 21030 arm = 0; 21031 for (ix = 0; ix < SOC_CMCS_NUM(unit); ix++) { 21032 21033 if (SOC_PCI_CMC(unit) != ix) { 21034 SOC_ARM_CMC(unit, arm) = ix; 21035 arm++; 21036 } 21037 } 21038 /* Disable interrupts */ 21039 soc_cmicm_intr0_disable(unit, ~0); 21040 soc_cmicm_intr1_disable(unit, ~0); 21041 soc_cmicm_intr2_disable(unit, ~0); 21042 #ifdef BCM_CMICDV2_SUPPORT 21043 if (soc_feature(unit, soc_feature_cmicd_v2)) { 21044 soc_cmicm_intr3_disable(unit, ~0); 21045 soc_cmicm_intr4_disable(unit, ~0); 21046 soc_cmicm_intr5_disable(unit, ~0); 21047 #ifdef BCM_CMICDV4_SUPPORT 21048 if (soc_feature(unit, soc_feature_cmicd_v4)) { 21049 soc_cmicm_intr6_disable(unit, ~0); 21050 } 21051 #endif /* BCM_CMICDV4_SUPPORT */ 21052 } 21053 #endif /* BCM_CMICDV2_SUPPORT */ 21054 if (soc_feature(unit, soc_feature_cmicm_multi_dma_cmc)) { 21055 soc_cmicm_cmcx_intr0_disable(unit, SOC_ARM_CMC(unit, 0), ~0); 21056 soc_cmicm_cmcx_intr0_disable(unit, SOC_ARM_CMC(unit, 1), ~0); 21057 } 21058 } else 21059 #endif 21060 { 21061 soc_intr_disable(unit, ~0); 21062 } 21063 21064 #ifdef BCM_CMICM_SUPPORT 21065 if(soc_feature(unit, soc_feature_cmicm)) { 21066 iph = soc_cmicm_intr; 21067 } 21068 #endif 21069 if (soc_property_get(unit, spn_POLLED_IRQ_MODE, 0)) { 21070 if (soc_ipoll_connect(unit, iph, INT_TO_PTR(unit)) < 0) { 21071 LOG_ERROR(BSL_LS_SOC_COMMON, 21072 (BSL_META_U(unit, 21073 "soc_attach: " 21074 "error initializing polled interrupt mode\n"))); 21075 return SOC_E_INTERNAL; 21076 } 21077 soc->soc_flags |= SOC_F_POLLED; 21078 } else { 21079 /* unit # is ISR arg */ 21080 if (soc_cm_interrupt_connect(unit, iph, INT_TO_PTR(unit)) < 0) { 21081 LOG_ERROR(BSL_LS_SOC_COMMON, 21082 (BSL_META_U(unit, 21083 "soc_attach: could not connect interrupt line\n"))); 21084 return SOC_E_INTERNAL; 21085 } 21086 } 21087 21088 if (soc->soc_flags & SOC_F_ATTACHED) { 21089 LOG_ERROR(BSL_LS_SOC_COMMON, 21090 (BSL_META_U(unit, 21091 "soc_attach: unit %d already attached\n"), 21092 unit)); 21093 return(SOC_E_NONE); 21094 } 21095 21096 /* 21097 * Create mutexes first as these are needed even if initialization fails. 21098 */ 21099 21100 if ((soc->socControlMutex = sal_mutex_create("SOC_CONTROL")) == NULL) { 21101 goto error; 21102 } 21103 21104 if ((soc->mem_ser_info_lock = sal_mutex_create("em_ser_info")) == NULL) { 21105 goto error; 21106 } 21107 21108 if ((soc->schanMutex = sal_mutex_create("SCHAN")) == NULL) { 21109 goto error; 21110 } 21111 21112 if ((soc->ipArbiterMutex = sal_mutex_create("IPARBITER")) == NULL) { 21113 goto error; 21114 } 21115 21116 #ifdef BCM_CMICM_SUPPORT 21117 if (soc_property_get(unit, spn_FSCHAN_ENABLE, 0)) { 21118 if ((soc->fschanMutex = sal_mutex_create("FSCHAN")) == NULL) { 21119 goto error; 21120 } 21121 } else { 21122 soc->fschanMutex = NULL; 21123 } 21124 #endif 21125 21126 if ((soc->miimMutex = sal_mutex_create("MIIM")) == NULL) { 21127 goto error; 21128 } 21129 if (0 != _soc_mem_lock_create(unit, soc)) { 21130 goto error; 21131 } 21132 21133 #ifdef INCLUDE_MEM_SCAN 21134 if ((soc->mem_scan_notify = 21135 sal_sem_create("memscan timer", sal_sem_BINARY, 0)) == NULL) { 21136 goto error; 21137 } 21138 21139 soc->mem_scan_pid = SAL_THREAD_ERROR; 21140 soc->mem_scan_interval = 0; 21141 if ((soc->mem_scan_lock = 21142 sal_mutex_create("mem_scan_lock")) == NULL) { 21143 goto error; 21144 } 21145 #endif 21146 21147 #ifdef BCM_SRAM_SCAN_SUPPORT 21148 if ((soc->sram_scan_notify = 21149 sal_sem_create("sramscan timer", sal_sem_BINARY, 0)) == NULL) { 21150 goto error; 21151 } 21152 21153 soc->sram_scan_pid = SAL_THREAD_ERROR; 21154 soc->sram_scan_interval = 0; 21155 #endif 21156 21157 if (soc_feature(unit, soc_feature_ser_error_stat)) { 21158 if ((soc->ser_err_stat_lock = 21159 sal_mutex_create("ser_err_stat_lock")) == NULL) { 21160 goto error; 21161 } 21162 } 21163 21164 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) 21165 #ifdef BCM_CCMDMA_SUPPORT 21166 for (cmc = 0; cmc < SOC_PCI_CMCS_NUM(unit); cmc++) { 21167 soc->ccmDmaMutex[cmc] = NULL; 21168 soc->ccmDmaIntr[cmc] = NULL; 21169 } 21170 if (soc_feature(unit, soc_feature_cmicm) || 21171 soc_feature(unit, soc_feature_cmicx)) { 21172 int ccmdma = 0; 21173 ccmdma = soc_property_get(unit, spn_CCM_DMA_ENABLE, 0); 21174 if (ccmdma) { 21175 if (SAL_BOOT_QUICKTURN) { 21176 soc->ccmDmaTimeout = CCMDMA_TIMEOUT_QT; 21177 } else { 21178 soc->ccmDmaTimeout = CCMDMA_TIMEOUT; 21179 } 21180 soc->ccmDmaTimeout = soc_property_get(unit, spn_CCMDMA_TIMEOUT_USEC, 21181 soc->ccmDmaTimeout); 21182 if (soc->ccmDmaTimeout) { 21183 for (cmc = 0; cmc < SOC_PCI_CMCS_NUM(unit); cmc++) { 21184 soc->ccmDmaMutex[cmc] = sal_mutex_create("ccmDMA"); 21185 if (soc->ccmDmaMutex[cmc] == NULL) { 21186 goto error; 21187 } 21188 soc->ccmDmaIntr[cmc] = sal_sem_create("CCMDMA interrupt", 21189 sal_sem_BINARY, 0); 21190 if (soc->ccmDmaIntr[cmc] == NULL) { 21191 goto error; 21192 } 21193 soc->ccmDmaIntrEnb = soc_property_get(unit, 21194 spn_CCMDMA_INTR_ENABLE, 1); 21195 } 21196 } 21197 soc_ccmdma_init(unit); 21198 } 21199 } 21200 #endif 21201 21202 #ifdef BCM_CMICX_SUPPORT 21203 if (soc_feature(unit, soc_feature_cmicx) && 21204 !((SAL_BOOT_PLISIM || SAL_BOOT_BCMSIM))) { 21205 int ccmdma = 0; 21206 ccmdma = soc_property_get(unit, spn_CCM_DMA_ENABLE, 0); 21207 if (soc_esw_schan_fifo_init(unit, ccmdma) != SOC_E_NONE) { 21208 return SOC_E_FAIL; 21209 } 21210 } 21211 #endif 21212 21213 #ifdef BCM_FIFODMA_SUPPORT 21214 soc_fifodma_init(unit); 21215 #endif 21216 /* Cross-CPU communications with UCs */ 21217 if (soc_feature(unit, soc_feature_cmicm)) { 21218 soc_cmic_uc_msg_start(unit); 21219 } 21220 #ifdef BCM_CMICX_SUPPORT 21221 if (soc_feature(unit, soc_feature_cmicx)) { 21222 soc_cmic_uc_msg_start(unit); 21223 } 21224 #endif 21225 #endif /* CMICM Support or BCM_CMICX_SUPPORT*/ 21226 /* Initialize bulk mem API */ 21227 mode = soc_property_get_str(unit, spn_SOC_MEM_BULK_SCHAN_OP_MODE); 21228 if (mode) { 21229 soc->memBulkSchanPioMode = 21230 (sal_strcasecmp(mode , "pio") == 0) ? 1 : 0; 21231 } else { 21232 soc->memBulkSchanPioMode = 0; 21233 } 21234 if (soc_mem_bulk_init(unit) != SOC_E_NONE) { 21235 goto error; 21236 } 21237 21238 if (soc_feature(unit, soc_feature_mem_cmd)) { 21239 soc->memCmdTimeout = soc_property_get(unit, 21240 spn_MEMCMD_TIMEOUT_USEC, 21241 1000000); 21242 soc->memCmdIntrEnb = soc_property_get(unit, 21243 spn_MEMCMD_INTR_ENABLE, 0); 21244 for (ix = 0; ix < 3; ix++) { 21245 if ((soc->memCmdIntr[ix] = 21246 sal_sem_create("MemCmd interrupt", sal_sem_BINARY, 0)) == NULL) { 21247 goto error; 21248 } 21249 } 21250 } else { 21251 for (ix = 0; ix < 3; ix++) { 21252 soc->memCmdIntr[ix] = 0; 21253 } 21254 } 21255 21256 if (soc_feature(unit, soc_feature_ipfix)) { 21257 soc->ipfixIntrEnb = 21258 soc_property_get(unit, spn_IPFIX_INTR_ENABLE, 21259 soc_feature(unit, soc_feature_fifo_dma) ? 1 : 0); 21260 } 21261 21262 if (soc_feature(unit, soc_feature_regex)) { 21263 soc->ftreportIntrEnb = 21264 soc_property_get(unit, spn_FLOW_TRACKER_INTR_ENABLE, 1); 21265 } 21266 #ifdef BCM_FLOWTRACKER_EXPORT_FIFO_SUPPORT 21267 if (soc_feature(unit, soc_feature_bscan_ft_fifodma_support)) { 21268 soc->ftExportIntrEnb = 21269 soc_property_get(unit, spn_FLOWTRACKER_EXPORT_FIFO_INTR_ENABLE, 1); 21270 } 21271 #endif /* BCM_FLOWTRACKER_EXPORT_FIFO_SUPPORT */ 21272 21273 if (soc_feature(unit, soc_feature_fifo_dma)) { 21274 soc->l2modDmaIntrEnb = 21275 soc_property_get(unit, spn_L2MOD_DMA_INTR_ENABLE, 1); 21276 soc->ctrEvictDmaIntrEnb = 21277 soc_property_get(unit, "ctr_evict_dma_intr_enable", 1); 21278 } 21279 21280 if (soc_feature(unit, soc_feature_multi_sbus_cmds)) { 21281 soc->sbusCmdSpacing = 21282 soc_property_get(unit, "multi_sbus_cmds_spacing", -1); 21283 } 21284 21285 if ((soc->counterMutex = sal_mutex_create("Counter")) == NULL) { 21286 goto error; 21287 } 21288 21289 if ((soc->evictMutex = sal_mutex_create("Evict")) == NULL) { 21290 goto error; 21291 } 21292 #if defined(BCM_TRIUMPH3_SUPPORT) 21293 if (soc_feature(unit, soc_feature_esm_correction)) { 21294 if ((soc->esm_recovery_notify = sal_sem_create("etu recovery", 21295 sal_sem_BINARY, 0)) == NULL) { 21296 goto error; 21297 } 21298 if ((soc->esm_lock = sal_mutex_create("esm")) == NULL) { 21299 goto error; 21300 } 21301 21302 soc->esm_recovery_pid = SAL_THREAD_ERROR; 21303 soc->esm_recovery_enable = FALSE; 21304 } 21305 #endif 21306 21307 /* 21308 * Attached flag must be true during initialization. 21309 * If initialization fails, the flag is cleared by soc_detach (below). 21310 */ 21311 21312 soc->soc_flags |= SOC_F_ATTACHED; 21313 21314 soc_family_suffix_update(unit); 21315 21316 if (soc_ndev_attached++ == 0) { 21317 int chip; 21318 21319 /* Work to be done before the first SOC device is attached. */ 21320 for (chip = 0; chip < SOC_NUM_SUPPORTED_CHIPS; chip++) { 21321 /* Call each chip driver's init function */ 21322 if (soc_base_driver_table[chip]->init) { 21323 (soc_base_driver_table[chip]->init)(); 21324 } 21325 } 21326 } 21327 21328 #if defined(BCM_ESW_SUPPORT) && defined(BCM_IPROC_SUPPORT) 21329 /* Initialize bond info cache */ 21330 if (soc_feature(unit, soc_feature_untethered_otp)) { 21331 if (soc_bond_info_init(unit) < 0) { 21332 LOG_ERROR(BSL_LS_SOC_COMMON, 21333 (BSL_META_U(unit, 21334 "soc_attach: could not initialize bond info structure\n"))); 21335 return SOC_E_INTERNAL; 21336 } 21337 } 21338 #endif /* BCM_ESW_SUPPORT && BCM_IPROC_SUPPORT */ 21339 21340 21341 /* 21342 * Set up port bitmaps. They are also set up on each soc_init so 21343 * they can be changed from a CLI without rebooting. 21344 */ 21345 if (0 != (soc_info_config(unit, soc))) { 21346 goto error; 21347 } 21348 #ifdef BCM_ESW_SUPPORT 21349 _soc_mem_lock_map(unit, soc); 21350 #endif 21351 21352 soc_dcb_unit_init(unit); 21353 21354 table_dma_enable = soc_property_get(unit, spn_TABLE_DMA_ENABLE, 1); 21355 tslam_dma_enable = soc_property_get(unit, spn_TSLAM_DMA_ENABLE, 1); 21356 #ifdef PLISIM 21357 #if defined(BCM_KATANA_SUPPORT) 21358 if (SOC_IS_KATANAX(unit) && (SAL_BOOT_PLISIM || SAL_BOOT_BCMSIM)) { 21359 LOG_ERROR(BSL_LS_SOC_COMMON, 21360 (BSL_META_U(unit, 21361 "WARNING:TABLE DMA is currently not working" 21362 " so ignoring its setting %d\n"), table_dma_enable)); 21363 LOG_ERROR(BSL_LS_SOC_COMMON, 21364 (BSL_META_U(unit, 21365 "WARNING:TSLAM DMA is currently not working" 21366 " so ignoring its setting %d\n"), tslam_dma_enable)); 21367 table_dma_enable = 0; 21368 tslam_dma_enable = 0; 21369 } 21370 #else 21371 LOG_ERROR(BSL_LS_SOC_COMMON, 21372 (BSL_META_U(unit, 21373 "INFO:TABLE DMA setting %d \n"),table_dma_enable)); 21374 LOG_ERROR(BSL_LS_SOC_COMMON, 21375 (BSL_META_U(unit, 21376 "INFO:TSLAM DMA setting %d \n"),tslam_dma_enable)); 21377 #endif 21378 #endif 21379 21380 rv = soc_sbusdma_lock_init(unit); 21381 if (rv != SOC_E_NONE) { 21382 goto error; 21383 } 21384 21385 #ifdef INCLUDE_RCPU 21386 if (SOC_IS_RCPU_ONLY(unit)) { 21387 table_dma_enable = 0; 21388 tslam_dma_enable = 0; 21389 } 21390 #endif /* INCLUDE_RCPU */ 21391 21392 if (soc_feature(unit, soc_feature_table_dma) && 21393 table_dma_enable) { 21394 table_dma_enable = 1; 21395 } else { 21396 table_dma_enable = 0; 21397 } 21398 21399 if (soc_feature(unit, soc_feature_tslam_dma) && 21400 tslam_dma_enable) { 21401 tslam_dma_enable = 1; 21402 } else { 21403 tslam_dma_enable = 0; 21404 } 21405 soc->tdma_enb = table_dma_enable; 21406 soc->tslam_enb = tslam_dma_enable; 21407 21408 #ifdef BCM_CMICM_SUPPORT 21409 if (SAL_BOOT_QUICKTURN) { 21410 soc->fifoDmaTimeout = FIFO_TIMEOUT_QT; 21411 } else { 21412 soc->fifoDmaTimeout = FIFO_TIMEOUT; 21413 } 21414 soc->fifoDmaTimeout = soc_property_get(unit, spn_DMA_DESC_TIMEOUT_USEC, 21415 soc->fifoDmaTimeout); 21416 if (soc->fifoDmaTimeout) { 21417 for (cmc = 0; cmc < SOC_PCI_CMCS_NUM(unit); cmc++) { 21418 for (ch = 0; ch < N_DMA_CHAN; ch++) { 21419 soc->fifoDmaMutexs[cmc][ch] = NULL; 21420 soc->fifoDmaMutexs[cmc][ch] = sal_mutex_create("FifoDMA"); 21421 if (soc->fifoDmaMutexs[cmc][ch] == NULL) { 21422 goto error; 21423 } 21424 soc->fifoDmaIntrs[cmc][ch] = NULL; 21425 soc->fifoDmaIntrs[cmc][ch] = sal_sem_create("FIFODMA interrupt", 21426 sal_sem_BINARY, 0); 21427 if (soc->fifoDmaIntrs[cmc][ch] == NULL) { 21428 goto error; 21429 } 21430 } 21431 } 21432 soc->fifoDmaIntrEnb = soc_property_get(unit, 21433 spn_L2MOD_DMA_INTR_ENABLE, 1); 21434 } 21435 #endif 21436 21437 if ((soc->schan_wb_mutex = sal_mutex_create("SchanWB")) == NULL) { 21438 goto error; 21439 } 21440 21441 #ifdef BROADCOM_DEBUG 21442 /* must be after soc_info_config, due to use of data structures */ 21443 if (!SOC_IS_HELIX4(unit)) { 21444 _soc_counter_verify(unit); 21445 } 21446 #endif /* BROADCOM_DEBUG */ 21447 21448 soc_cm_get_id(unit, &dev_id, &rev_id); 21449 21450 /* 21451 * Initialize memory index_maxes. Chip specific overrides follow. 21452 */ 21453 SOC_CONTROL(unit)->tcam_protect_write = 21454 soc_property_get(unit, "tcam_protect_write", FALSE); 21455 SOC_CONTROL(unit)->tcam_protect_write_init = 21456 SOC_CONTROL(unit)->tcam_protect_write; 21457 enable = soc_property_get(unit, "force_read_through", FALSE); 21458 SOC_MEM_FORCE_READ_THROUGH_SET(unit, enable); 21459 enable = soc_property_get(unit, "cache_coherency_check", TRUE); 21460 SOC_MEM_CACHE_COHERENCY_CHECK_SET(unit, enable); 21461 SOC_CONTROL(unit)->dma_from_mem_cache = 21462 soc_property_get(unit, "dma_from_cache", TRUE); 21463 enable = soc_property_get(unit, "reg_ser_error_assert", FALSE); 21464 SOC_REG_RETURN_SER_ERROR_SET(unit, enable); 21465 SOC_SER_CORRECTION_SUPPORT(unit) = 21466 soc_property_get(unit, spn_PARITY_CORRECTION, 21467 (SAL_BOOT_RTLSIM || SAL_BOOT_XGSSIM) ? 0 : 1); 21468 SOC_SER_COUNTER_CORRECTION(unit) = 21469 soc_property_get(unit, spn_PARITY_COUNTER_CLEAR, 1) ? 0 : 1; 21470 SOC_CONTROL(unit)->l2e_ppa = soc_property_get(unit, "tr3_l2e_ppa", 1); 21471 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 21472 if (!SOC_MEM_IS_VALID(unit, mem)) { 21473 sop->memState[mem].index_max = -1; 21474 continue; 21475 } 21476 sop->memState[mem].index_max = SOC_MEM_INFO(unit, mem).index_max; 21477 if (soc_feature(unit, soc_feature_xy_tcam) && 21478 SOC_CONTROL(unit)->tcam_protect_write && 21479 (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_CAM) && 21480 (!(SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_EXT_CAM))) { 21481 switch (mem) { 21482 case FP_TCAMm: 21483 case FP_GM_FIELDSm: 21484 case FP_GLOBAL_MASK_TCAMm: 21485 case FP_GLOBAL_MASK_TCAM_Xm: 21486 case FP_GLOBAL_MASK_TCAM_Ym: 21487 case VFP_TCAMm: 21488 case EFP_TCAMm: 21489 case FP_UDF_TCAMm: 21490 #if defined BCM_TOMAHAWK_SUPPORT 21491 case IFP_TCAMm: 21492 case IFP_TCAM_PIPE0m: 21493 case IFP_TCAM_PIPE1m: 21494 case IFP_TCAM_PIPE2m: 21495 case IFP_TCAM_PIPE3m: 21496 case IFP_TCAM_WIDEm: 21497 case IFP_TCAM_WIDE_PIPE0m: 21498 case IFP_TCAM_WIDE_PIPE1m: 21499 case IFP_TCAM_WIDE_PIPE2m: 21500 case IFP_TCAM_WIDE_PIPE3m: 21501 case FP_UDF_TCAM_PIPE0m: 21502 case FP_UDF_TCAM_PIPE1m: 21503 case FP_UDF_TCAM_PIPE2m: 21504 case FP_UDF_TCAM_PIPE3m: 21505 case IFP_LOGICAL_TABLE_SELECTm: 21506 case IFP_LOGICAL_TABLE_SELECT_PIPE0m: 21507 case IFP_LOGICAL_TABLE_SELECT_PIPE1m: 21508 case IFP_LOGICAL_TABLE_SELECT_PIPE2m: 21509 case IFP_LOGICAL_TABLE_SELECT_PIPE3m: 21510 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLYm: 21511 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE0m: 21512 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE1m: 21513 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE2m: 21514 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE3m: 21515 case EXACT_MATCH_LOGICAL_TABLE_SELECTm: 21516 case EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0m: 21517 case EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1m: 21518 case EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2m: 21519 case EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3m: 21520 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLYm: 21521 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE0m: 21522 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE1m: 21523 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE2m: 21524 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE3m: 21525 #endif /* BCM_TOMAHAWK_SUPPORT */ 21526 break; 21527 default: 21528 sop->memState[mem].index_max--; 21529 break; 21530 } 21531 } 21532 #ifdef BCM_TRIUMPH3_SUPPORT 21533 if (SOC_IS_TRIUMPH3(unit) && 21534 !((dev_id == BCM56640_DEVICE_ID) || 21535 (dev_id == BCM56643_DEVICE_ID) || 21536 (dev_id == BCM56545_DEVICE_ID))) { 21537 int blk, copyno = COPYNO_ALL; 21538 SOC_MEM_BLOCK_ITER(unit, mem, blk) { 21539 copyno = blk; 21540 break; 21541 } 21542 /* Disable unavailable ESM and IESMIF mems */ 21543 if ((SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_ETU) || 21544 ((SOC_BLOCK_TYPE(unit, copyno) == SOC_BLK_IPIPE) && 21545 (SOC_MEM_ADDR_STAGE_EXTENDED(SOC_MEM_BASE(unit, mem)) 21546 == 0x9))) { 21547 sop->memState[mem].index_max = -1; 21548 } 21549 } 21550 #endif /* BCM_TRIUMPH3_SUPPORT */ 21551 } 21552 21553 /* Need to know the bypass mode before resolving 21554 * which memories and features are enabled in this configuration. */ 21555 if (SOC_IS_TRIDENT3X(unit)) { 21556 SOC_SWITCH_BYPASS_MODE(unit) = SOC_SWITCH_BYPASS_MODE_NONE; 21557 } else { 21558 SOC_SWITCH_BYPASS_MODE(unit) = SOC_IS_SC_CQ(unit) || SOC_IS_TD_TT(unit) ? 21559 soc_property_get(unit, spn_SWITCH_BYPASS_MODE, 21560 SOC_SWITCH_BYPASS_MODE_NONE) : 21561 SOC_SWITCH_BYPASS_MODE_NONE; 21562 } 21563 21564 /* Initialize double-tagged mode to FALSE */ 21565 SOC_DT_MODE(unit) = 0; 21566 21567 #ifdef BCM_GREYHOUND_SUPPORT 21568 if (SOC_IS_GREYHOUND(unit)){ 21569 if (((dev_id & 0xF000) == 0x8000) && (dev_id != BCM53365_DEVICE_ID)) { 21570 if ((dev_id & 0x0060) != 0x0000) { 21571 /* Elkhound and Bloodhound */ 21572 if ((dev_id & 0x00F6) == 0x0054) { /* 53454/53455 */ 21573 dev_id &= 0xFFF4; /* use 53454 */ 21574 } 21575 if ((dev_id & 0x00F6) == 0x0056) { /* 53456/53457 */ 21576 dev_id &= 0xFFF6; /* use 53456*/ 21577 } 21578 /* no change on Bloodhound */ 21579 } else { 21580 dev_id &= 0xFF0F; 21581 } 21582 } 21583 } 21584 #endif 21585 21586 switch (dev_id) { 21587 #ifdef BCM_FIREBOLT_SUPPORT 21588 case BCM56404_DEVICE_ID: 21589 soc_helix_mem_config(unit); 21590 break; 21591 case BCM53300_DEVICE_ID: 21592 case BCM53301_DEVICE_ID: 21593 case BCM53302_DEVICE_ID: 21594 soc_bcm53300_mem_config(unit); 21595 break; 21596 #endif /* BCM_FIREBOLT_SUPPORT */ 21597 #ifdef BCM_RAPTOR_SUPPORT 21598 case BCM53716_DEVICE_ID: 21599 sop->memState[FP_TCAMm].index_max = 255; 21600 sop->memState[FP_POLICY_TABLEm].index_max = 255; 21601 sop->memState[FP_METER_TABLEm].index_max = 255; 21602 sop->memState[FP_COUNTER_TABLEm].index_max = 255; 21603 break; 21604 case BCM53718_DEVICE_ID: 21605 case BCM53714_DEVICE_ID: 21606 sop->memState[FP_TCAMm].index_max = 511; 21607 sop->memState[FP_POLICY_TABLEm].index_max = 511; 21608 sop->memState[FP_METER_TABLEm].index_max = 511; 21609 sop->memState[FP_COUNTER_TABLEm].index_max = 511; 21610 break; 21611 case BCM53724_DEVICE_ID: 21612 case BCM53726_DEVICE_ID: 21613 soc_bcm53724_mem_config(unit); 21614 break; 21615 case BCM56225_DEVICE_ID: 21616 case BCM56227_DEVICE_ID: 21617 case BCM56229_DEVICE_ID: 21618 soc_bcm56225_mem_config(unit); 21619 break; 21620 #endif /* BCM_RAPTOR_SUPPORT */ 21621 #ifdef BCM_FIREBOLT2_SUPPORT 21622 #ifndef EXCLUDE_BCM56324 21623 case BCM56322_DEVICE_ID: 21624 case BCM56324_DEVICE_ID: 21625 #endif /* EXCLUDE_BCM56324 */ 21626 case BCM56510_DEVICE_ID: 21627 case BCM56511_DEVICE_ID: 21628 case BCM56512_DEVICE_ID: 21629 case BCM56513_DEVICE_ID: 21630 case BCM56514_DEVICE_ID: 21631 case BCM56516_DEVICE_ID: 21632 case BCM56517_DEVICE_ID: 21633 case BCM56518_DEVICE_ID: 21634 case BCM56519_DEVICE_ID: 21635 soc_firebolt2_mem_config(unit); 21636 break; 21637 #endif /* BCM_FIREBOLT2_SUPPORT */ 21638 #ifdef BCM_TRIUMPH_SUPPORT 21639 case BCM56620_DEVICE_ID: 21640 case BCM56624_DEVICE_ID: 21641 case BCM56626_DEVICE_ID: 21642 case BCM56628_DEVICE_ID: 21643 case BCM56629_DEVICE_ID: 21644 soc_triumph_esm_init_mem_config(unit); 21645 break; 21646 #ifdef BCM_TRIUMPH2_SUPPORT 21647 case BCM56634_DEVICE_ID: 21648 case BCM56636_DEVICE_ID: 21649 case BCM56638_DEVICE_ID: 21650 case BCM56630_DEVICE_ID: 21651 case BCM56639_DEVICE_ID: 21652 case BCM56538_DEVICE_ID: 21653 soc_triumph_esm_init_mem_config(unit); 21654 soc_triumph2_mem_config(unit); 21655 break; 21656 #endif /* BCM_TRIUMPH2_SUPPORT */ 21657 #if defined(BCM_APOLLO_SUPPORT) 21658 case BCM56526_DEVICE_ID: 21659 case BCM56521_DEVICE_ID: 21660 case BCM56520_DEVICE_ID: 21661 case BCM56522_DEVICE_ID: 21662 case BCM56524_DEVICE_ID: 21663 case BCM56534_DEVICE_ID: 21664 soc_triumph2_mem_config(unit); 21665 break; 21666 #endif /* BCM_APOLLO_SUPPORT */ 21667 #ifdef BCM_VALKYRIE2_SUPPORT 21668 case BCM56685_DEVICE_ID: 21669 case BCM56689_DEVICE_ID: 21670 soc_triumph2_mem_config(unit); 21671 break; 21672 #endif /* BCM_VALKYRIE2_SUPPORT */ 21673 case BCM56686_DEVICE_ID: 21674 sop->memState[FP_TCAMm].index_max = 2047; 21675 sop->memState[FP_POLICY_TABLEm].index_max = 2047; 21676 sop->memState[FP_METER_TABLEm].index_max = 2047; 21677 sop->memState[FP_COUNTER_TABLEm].index_max = 2047; 21678 sop->memState[FP_GLOBAL_MASK_TCAMm].index_max = 2047; 21679 21680 sop->memState[EFP_TCAMm].index_max = 255; 21681 sop->memState[EFP_POLICY_TABLEm].index_max = 255; 21682 sop->memState[EFP_METER_TABLEm].index_max = 255; 21683 sop->memState[EFP_COUNTER_TABLEm].index_max = 255; 21684 21685 sop->memState[VFP_TCAMm].index_max = 255; 21686 sop->memState[VFP_POLICY_TABLEm].index_max = 255; 21687 break; 21688 #endif /* BCM_TRIUMPH_SUPPORT */ 21689 #ifdef BCM_SCORPION_SUPPORT 21690 case BCM56820_DEVICE_ID: 21691 case BCM56821_DEVICE_ID: 21692 case BCM56822_DEVICE_ID: 21693 case BCM56823_DEVICE_ID: 21694 case BCM56825_DEVICE_ID: 21695 case BCM56720_DEVICE_ID: 21696 case BCM56721_DEVICE_ID: 21697 case BCM56725_DEVICE_ID: 21698 #ifdef BCM_SHADOW_SUPPORT 21699 case BCM88732_DEVICE_ID: 21700 #endif /* BCM_SHADOW_SUPPORT */ 21701 soc_scorpion_mem_config(unit); 21702 break; 21703 #endif /* BCM_SCORPION_SUPPORT */ 21704 #ifdef BCM_ENDURO_SUPPORT 21705 case BCM56320_DEVICE_ID: 21706 case BCM56321_DEVICE_ID: 21707 case BCM56230_DEVICE_ID: 21708 case BCM56231_DEVICE_ID: 21709 soc_enduro_mem_config(unit); 21710 break; 21711 #endif /* BCM_ENDURO_SUPPORT */ 21712 #ifdef BCM_KATANA_SUPPORT 21713 case BCM56240_DEVICE_ID: 21714 case BCM56241_DEVICE_ID: 21715 case BCM56242_DEVICE_ID: 21716 case BCM56243_DEVICE_ID: 21717 case BCM56245_DEVICE_ID: 21718 case BCM56246_DEVICE_ID: 21719 sop->memState[L2Xm].index_max = 16383; 21720 sop->memState[L2_ENTRY_ONLYm].index_max = 16383; 21721 sop->memState[L2_HITDA_ONLYm].index_max = 2047; 21722 sop->memState[L3_ENTRY_ONLYm].index_max = 4095; 21723 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = 255; 21724 sop->memState[L3_DEFIPm].index_max = 2047; 21725 sop->memState[L3_DEFIP_PAIR_128m].index_max = 1023; 21726 sop->memState[L3_DEFIP_ONLYm].index_max = 2047; 21727 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 2047; 21728 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 2047; 21729 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 1023; 21730 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max =1023; 21731 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 1023; 21732 sop->memState[MPLS_ENTRYm].index_max = 1023; 21733 sop->memState[VLAN_XLATEm].index_max = 4095; 21734 sop->memState[VLAN_MACm].index_max = 4095; 21735 sop->memState[FP_COUNTER_TABLEm].index_max = 2047; 21736 sop->memState[FP_GLOBAL_MASK_TCAMm].index_max = 2047; 21737 sop->memState[FP_METER_TABLEm].index_max = 2047; 21738 sop->memState[FP_POLICY_TABLEm].index_max = 2047; 21739 sop->memState[FP_TCAMm].index_max = 2047; 21740 sop->memState[MMU_CBPI_0m].index_max = 2751; 21741 sop->memState[MMU_CBPI_1m].index_max = 2751; 21742 sop->memState[MMU_CBPI_2m].index_max = 2751; 21743 sop->memState[MMU_CBPI_3m].index_max = 2751; 21744 sop->memState[MMU_CBPI_4m].index_max = 2751; 21745 sop->memState[MMU_CBPI_5m].index_max = 2751; 21746 sop->memState[MMU_CBPI_6m].index_max = 2751; 21747 sop->memState[MMU_CBPI_7m].index_max = 2751; 21748 sop->memState[MMU_CBPI_8m].index_max = 2751; 21749 sop->memState[MMU_CBPI_9m].index_max = 2751; 21750 sop->memState[MMU_CBPI_10m].index_max = 2751; 21751 sop->memState[MMU_CBPI_11m].index_max = 2751; 21752 sop->memState[LLS_L0_CONFIGm].index_max = 127; 21753 sop->memState[LLS_L1_CONFIGm].index_max = 255; 21754 sop->memState[LLS_L2_PARENTm].index_max = 511; 21755 for(saber_counter_direction=0; 21756 saber_counter_direction<BCM_SABER_MAX_COUNTER_DIRECTION; 21757 saber_counter_direction++) { 21758 for(saber_counter_pool=0; 21759 saber_counter_pool<BCM_SABER_MAX_COUNTER_POOL; 21760 saber_counter_pool++) { 21761 sop->memState[saber_counter_table 21762 [saber_counter_direction][saber_counter_pool]]. 21763 index_max = saber_pool_size 21764 [saber_counter_direction]; 21765 } 21766 } 21767 if (soc_kt_mem_config(unit, dev_id) != SOC_E_NONE) { 21768 goto error; 21769 } 21770 break; 21771 case BCM55441_DEVICE_ID: 21772 sop->memState[FP_COUNTER_TABLEm].index_max = 2047; 21773 sop->memState[FP_GLOBAL_MASK_TCAMm].index_max = 2047; 21774 sop->memState[FP_METER_TABLEm].index_max = 2047; 21775 sop->memState[FP_POLICY_TABLEm].index_max = 2047; 21776 sop->memState[FP_TCAMm].index_max = 2047; 21777 sop->memState[LLS_L0_CONFIGm].index_max = 255; 21778 sop->memState[LLS_L1_CONFIGm].index_max = 1023; 21779 sop->memState[LLS_L2_PARENTm].index_max = 1023; 21780 if (soc_kt_mem_config(unit, dev_id) != SOC_E_NONE) { 21781 goto error; 21782 } 21783 break; 21784 case BCM56440_DEVICE_ID: 21785 case BCM56441_DEVICE_ID: 21786 case BCM56442_DEVICE_ID: 21787 case BCM56443_DEVICE_ID: 21788 case BCM56445_DEVICE_ID: 21789 case BCM56446_DEVICE_ID: 21790 case BCM56447_DEVICE_ID: 21791 case BCM56448_DEVICE_ID: 21792 case BCM56449_DEVICE_ID: 21793 if (soc_kt_mem_config(unit, dev_id) != SOC_E_NONE) { 21794 goto error; 21795 } 21796 break; 21797 #endif /* BCM_KATANA_SUPPORT */ 21798 #ifdef BCM_KATANA2_SUPPORT 21799 case BCM55450_DEVICE_ID: 21800 case BCM55455_DEVICE_ID: 21801 case BCM56248_DEVICE_ID: 21802 case BCM56450_DEVICE_ID: 21803 case BCM56452_DEVICE_ID: 21804 case BCM56454_DEVICE_ID: 21805 case BCM56455_DEVICE_ID: 21806 case BCM56456_DEVICE_ID: 21807 case BCM56457_DEVICE_ID: 21808 case BCM56458_DEVICE_ID: 21809 if (soc_kt2_mem_config(unit, dev_id) != SOC_E_NONE) { 21810 goto error; 21811 } 21812 break; 21813 #if defined(BCM_SABER2_SUPPORT) 21814 case BCM56260_DEVICE_ID: 21815 case BCM56261_DEVICE_ID: 21816 case BCM56262_DEVICE_ID: 21817 case BCM56263_DEVICE_ID: 21818 case BCM56265_DEVICE_ID: 21819 case BCM56266_DEVICE_ID: 21820 case BCM56267_DEVICE_ID: 21821 case BCM56268_DEVICE_ID: 21822 case BCM56460_DEVICE_ID: 21823 case BCM56461_DEVICE_ID: 21824 case BCM56462_DEVICE_ID: 21825 case BCM56463_DEVICE_ID: 21826 case BCM56465_DEVICE_ID: 21827 case BCM56466_DEVICE_ID: 21828 case BCM56467_DEVICE_ID: 21829 case BCM56468_DEVICE_ID: 21830 case BCM56233_DEVICE_ID: 21831 if (soc_sb2_mem_config(unit, dev_id) != SOC_E_NONE) { 21832 goto error; 21833 } 21834 break; 21835 #endif 21836 #if defined(BCM_METROLITE_SUPPORT) 21837 case BCM56270_DEVICE_ID: 21838 case BCM56271_DEVICE_ID: 21839 case BCM56272_DEVICE_ID: 21840 21841 case BCM53460_DEVICE_ID: 21842 case BCM53461_DEVICE_ID: 21843 21844 if (soc_ml_mem_config(unit, dev_id) != SOC_E_NONE) { 21845 goto error; 21846 } 21847 break; 21848 #endif 21849 #endif 21850 #ifdef BCM_HURRICANE2_SUPPORT 21851 case BCM56150_DEVICE_ID: 21852 case BCM56151_DEVICE_ID: 21853 case BCM53347_DEVICE_ID: 21854 case BCM53346_DEVICE_ID: 21855 case BCM53344_DEVICE_ID: 21856 case BCM56152_DEVICE_ID: 21857 case BCM53333_DEVICE_ID: 21858 case BCM53334_DEVICE_ID: 21859 case BCM53342_DEVICE_ID: 21860 case BCM53343_DEVICE_ID: 21861 case BCM53393_DEVICE_ID: 21862 case BCM53394_DEVICE_ID: 21863 if (soc_hu2_mem_config(unit, dev_id) != SOC_E_NONE) { 21864 goto error; 21865 } 21866 break; 21867 #endif 21868 #ifdef BCM_HELIX4_SUPPORT 21869 case BCM56548H_DEVICE_ID: 21870 case BCM56548_DEVICE_ID: 21871 case BCM56547_DEVICE_ID: 21872 case BCM56346_DEVICE_ID: 21873 case BCM56345_DEVICE_ID: 21874 case BCM56344_DEVICE_ID: 21875 case BCM56342_DEVICE_ID: 21876 case BCM56340_DEVICE_ID: 21877 case BCM56049_DEVICE_ID: 21878 case BCM56048_DEVICE_ID: 21879 case BCM56047_DEVICE_ID: 21880 case BCM56042_DEVICE_ID: 21881 case BCM56041_DEVICE_ID: 21882 case BCM56040_DEVICE_ID: 21883 if (soc_hx4_mem_config(unit, dev_id) != SOC_E_NONE) { 21884 goto error; 21885 } 21886 break; 21887 #endif 21888 #ifdef BCM_TRIUMPH3_SUPPORT 21889 case BCM56540_DEVICE_ID: 21890 case BCM56541_DEVICE_ID: 21891 case BCM56542_DEVICE_ID: 21892 case BCM56543_DEVICE_ID: 21893 case BCM56544_DEVICE_ID: 21894 case BCM56545_DEVICE_ID: 21895 case BCM56546_DEVICE_ID: 21896 case BCM56648_DEVICE_ID: 21897 case BCM56649_DEVICE_ID: 21898 case BCM56640_DEVICE_ID: 21899 case BCM56643_DEVICE_ID: 21900 case BCM56644_DEVICE_ID: 21901 case BCM56044_DEVICE_ID: 21902 case BCM56045_DEVICE_ID: 21903 case BCM56046_DEVICE_ID: 21904 soc_triumph3_esm_init_mem_config(unit); 21905 if (soc_tr3_mem_config(unit, dev_id, rev_id) != SOC_E_NONE) { 21906 goto error; 21907 } 21908 break; 21909 #endif /* BCM_TRIUMPH3_SUPPORT */ 21910 #if defined(BCM_TRIDENT_SUPPORT) 21911 case BCM56838_DEVICE_ID: 21912 case BCM56847_DEVICE_ID: 21913 case BCM56835_DEVICE_ID: 21914 case BCM56831_DEVICE_ID: 21915 case BCM56742_DEVICE_ID: 21916 if (soc_trident_mem_config(unit) < 0) { 21917 goto error; 21918 } 21919 break; 21920 #endif /* BCM_TRIDENT_SUPPORT */ 21921 #if defined(BCM_TRIDENT2_SUPPORT) 21922 case BCM56860_DEVICE_ID: 21923 case BCM56850_DEVICE_ID: 21924 case BCM56851_DEVICE_ID: 21925 case BCM56852_DEVICE_ID: 21926 case BCM56853_DEVICE_ID: 21927 case BCM56854_DEVICE_ID: 21928 case BCM56855_DEVICE_ID: 21929 case BCM56834_DEVICE_ID: 21930 case BCM56750_DEVICE_ID: 21931 case BCM56830_DEVICE_ID: 21932 case BCM56861_DEVICE_ID: 21933 case BCM56862_DEVICE_ID: 21934 case BCM56864_DEVICE_ID: 21935 case BCM56865_DEVICE_ID: 21936 case BCM56866_DEVICE_ID: 21937 case BCM56867_DEVICE_ID: 21938 case BCM56868_DEVICE_ID: 21939 case BCM56832_DEVICE_ID: 21940 case BCM56833_DEVICE_ID: 21941 case BCM56836_DEVICE_ID: 21942 if (soc_trident2_mem_config(unit) < 0) { 21943 goto error; 21944 } 21945 break; 21946 #endif /* BCM_TRIDENT2_SUPPORT */ 21947 #if defined(BCM_GREYHOUND_SUPPORT) 21948 case BCM53400_DEVICE_ID: 21949 case BCM53401_DEVICE_ID: 21950 case BCM53402_DEVICE_ID: 21951 case BCM53403_DEVICE_ID: 21952 case BCM53404_DEVICE_ID: 21953 case BCM53405_DEVICE_ID: 21954 case BCM53365_DEVICE_ID: 21955 case BCM53406_DEVICE_ID: 21956 case BCM53369_DEVICE_ID: 21957 case BCM53408_DEVICE_ID: 21958 case BCM56060_DEVICE_ID: 21959 case BCM56062_DEVICE_ID: 21960 case BCM56063_DEVICE_ID: 21961 case BCM56064_DEVICE_ID: 21962 case BCM56065_DEVICE_ID: 21963 case BCM56066_DEVICE_ID: 21964 case BCM53454_DEVICE_ID: 21965 case BCM53456_DEVICE_ID: 21966 case BCM53422_DEVICE_ID: 21967 case BCM53424_DEVICE_ID: 21968 case BCM53426_DEVICE_ID: 21969 if (soc_greyhound_mem_config(unit, dev_id) < 0) { 21970 goto error; 21971 } 21972 break; 21973 #endif /* BCM_GREYHOUND_SUPPORT */ 21974 #if defined(BCM_TOMAHAWK_SUPPORT) 21975 case BCM56960_DEVICE_ID: 21976 case BCM56961_DEVICE_ID: 21977 case BCM56962_DEVICE_ID: 21978 case BCM56963_DEVICE_ID: 21979 case BCM56930_DEVICE_ID: 21980 case BCM56968_DEVICE_ID: 21981 #if defined(BCM_TOMAHAWKPLUS_SUPPORT) 21982 case BCM56965_DEVICE_ID: 21983 case BCM56969_DEVICE_ID: 21984 case BCM56966_DEVICE_ID: 21985 case BCM56967_DEVICE_ID: 21986 #endif /* BCM_TOMAHAWKPLUS_SUPPORT */ 21987 case BCM56168_DEVICE_ID: 21988 case BCM56169_DEVICE_ID: 21989 if (soc_tomahawk_mem_config(unit) < 0) { 21990 goto error; 21991 } 21992 break; 21993 #endif /* BCM_TOMAHAWK_SUPPORT */ 21994 #if defined(BCM_TOMAHAWK3_SUPPORT) 21995 case BCM56980_DEVICE_ID: 21996 case BCM56981_DEVICE_ID: 21997 case BCM56982_DEVICE_ID: 21998 case BCM56983_DEVICE_ID: 21999 case BCM56984_DEVICE_ID: 22000 if (soc_tomahawk3_mem_config(unit) < 0) { 22001 goto error; 22002 } 22003 break; 22004 #endif /* BCM_TOMAHAWK3_SUPPORT */ 22005 #if defined(BCM_TRIDENT3_SUPPORT) 22006 case BCM56870_DEVICE_ID: 22007 case BCM56873_DEVICE_ID: 22008 if (soc_trident3_mem_config(unit) < 0) { 22009 goto error; 22010 } 22011 break; 22012 #endif /* BCM_TRIDENT3_SUPPORT */ 22013 #if defined(BCM_MAVERICK2_SUPPORT) 22014 case BCM56770_DEVICE_ID: 22015 case BCM56771_DEVICE_ID: 22016 if (soc_maverick2_mem_config(unit) < 0) { 22017 goto error; 22018 } 22019 break; 22020 #endif /* BCM_HELIX5_SUPPORT */ 22021 #if defined(BCM_APACHE_SUPPORT) 22022 case BCM56560_DEVICE_ID: 22023 case BCM56561_DEVICE_ID: 22024 case BCM56565_DEVICE_ID: 22025 case BCM56566_DEVICE_ID: 22026 case BCM56762_DEVICE_ID: 22027 case BCM56764_DEVICE_ID: 22028 case BCM56766_DEVICE_ID: 22029 if (soc_apache_mem_config(unit) < 0) { 22030 goto error; 22031 } 22032 break; 22033 #endif /* BCM_APACHE_SUPPORT */ 22034 #if defined(BCM_HURRICANE3_SUPPORT) 22035 case BCM56160_DEVICE_ID: 22036 case BCM56162_DEVICE_ID: 22037 case BCM56163_DEVICE_ID: 22038 case BCM56164_DEVICE_ID: 22039 case BCM56166_DEVICE_ID: 22040 case BCM53440_DEVICE_ID: 22041 case BCM53443_DEVICE_ID: 22042 case BCM53442_DEVICE_ID: 22043 case BCM53434_DEVICE_ID: 22044 if (soc_hurricane3_mem_config(unit, dev_id) < 0) { 22045 goto error; 22046 } 22047 break; 22048 case BCM53540_DEVICE_ID: /* WH2 */ 22049 case BCM53547_DEVICE_ID: 22050 case BCM53548_DEVICE_ID: 22051 case BCM53549_DEVICE_ID: 22052 if (soc_wolfhound2_mem_config(unit, dev_id) < 0) { 22053 goto error; 22054 } 22055 break; 22056 #endif /* BCM_HURRICANE3_SUPPORT */ 22057 #if defined(BCM_TOMAHAWK2_SUPPORT) 22058 case BCM56970_DEVICE_ID: 22059 case BCM56971_DEVICE_ID: 22060 case BCM56972_DEVICE_ID: 22061 case BCM56974_DEVICE_ID: 22062 case BCM56975_DEVICE_ID: 22063 if (soc_tomahawk_mem_config(unit) < 0) { 22064 goto error; 22065 } 22066 break; 22067 #endif /* BCM_TOMAHAWK2_SUPPORT */ 22068 22069 #if defined(BCM_GREYHOUND2_SUPPORT) 22070 case BCM56170_DEVICE_ID: 22071 case BCM56172_DEVICE_ID: 22072 case BCM56174_DEVICE_ID: 22073 case BCM53570_DEVICE_ID: 22074 case BCM53575_DEVICE_ID: 22075 if (soc_greyhound2_mem_config(unit, dev_id) < 0) { 22076 goto error; 22077 } 22078 break; 22079 #endif /* BCM_GREYHOUND2_SUPPORT */ 22080 22081 default: 22082 switch (drv_dev_id) { 22083 #if defined(BCM_MONTEREY_SUPPORT) 22084 case BCM56670_DEVICE_ID: 22085 case BCM56671_DEVICE_ID: 22086 case BCM56672_DEVICE_ID: 22087 case BCM56675_DEVICE_ID: 22088 if (soc_monterey_mem_config(unit) < 0) { 22089 goto error; 22090 } 22091 break; 22092 #endif /* BCM_MONTEREY_SUPPORT */ 22093 #if defined(BCM_APACHE_SUPPORT) 22094 case BCM56560_DEVICE_ID: 22095 if (soc_apache_mem_config(unit) < 0) { 22096 goto error; 22097 } 22098 break; 22099 #endif /* BCM_APACHE_SUPPORT */ 22100 #if defined(BCM_HELIX5_SUPPORT) 22101 case BCM56370_DEVICE_ID: 22102 if (soc_helix5_mem_config(unit) < 0) { 22103 goto error; 22104 } 22105 break; 22106 #endif /* BCM_HELIX5_SUPPORT */ 22107 default: 22108 break; 22109 } 22110 break; 22111 } 22112 #ifdef BCM_ESW_SUPPORT 22113 if (soc_feature(unit, soc_feature_ipmc_reduced_table_size)) { 22114 sop->memState[L3_IPMCm].index_max = 2047; 22115 } 22116 #endif /* BCM_ESW_SUPPORT */ 22117 22118 #if defined(BCM_ESW_SUPPORT) && defined(BCM_IPROC_SUPPORT) 22119 /* 22120 * Update memState based on the actual table sizes on the SKU using 22121 * BondOptions info read from the relevant capability registers 22122 */ 22123 if (soc_feature(unit, soc_feature_untethered_otp)) { 22124 rv = soc_mem_config_bondoptions_adjust(unit); 22125 if (rv != SOC_E_NONE) { 22126 goto error; 22127 } 22128 } 22129 #endif /* BCM_ESW_SUPPORT && BCM_IPROC_SUPPORT */ 22130 22131 22132 #if defined(BCM_ESW_SUPPORT) || \ 22133 defined(BCM_PETRA_SUPPORT) || defined(BCM_DFE_SUPPORT) 22134 #if !defined(SOC_NO_NAMES) 22135 if (soc_property_get(unit, spn_MEM_CHECK_MAX_OVERRIDE, 0)) { 22136 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 22137 uint32 max; 22138 uint32 max_adj; 22139 char mem_name[128]; 22140 char *mptr; 22141 22142 if (!SOC_MEM_IS_VALID(unit, mem)) { 22143 continue; 22144 } 22145 max = sop->memState[mem].index_max; 22146 22147 /* coverity[secure_coding] */ 22148 sal_strcpy(mem_name, "memmax_"); 22149 mptr = &mem_name[sal_strlen(mem_name)]; 22150 sal_strcpy(mptr, SOC_MEM_NAME(unit, mem)); 22151 max_adj = soc_property_get(unit, mem_name, max); 22152 if (max_adj == max) { 22153 sal_strcpy(mptr, SOC_MEM_UFNAME(unit, mem)); 22154 max_adj = soc_property_get(unit, mem_name, max); 22155 } 22156 if (max_adj == max) { 22157 sal_strcpy(mptr, SOC_MEM_UFALIAS(unit, mem)); 22158 max_adj = soc_property_get(unit, mem_name, max); 22159 } 22160 sop->memState[mem].index_max = max_adj; 22161 22162 } 22163 } 22164 #endif /* !SOC_NO_NAMES */ 22165 #endif 22166 /* Allocate counter module resources */ 22167 if (soc_counter_attach(unit)) { 22168 goto error; 22169 } 22170 22171 /* Allocate MMU LLS usage map */ 22172 #if defined(BCM_APACHE_SUPPORT) 22173 if (SOC_IS_APACHE(unit)) { 22174 if (!SOC_IS_MONTEREY(unit)) { 22175 if (soc_apache_lls_bmap_alloc(unit) < 0) { 22176 goto error; 22177 } 22178 } 22179 } else 22180 #endif /* BCM_APACHE_SUPPORT */ 22181 #if defined(BCM_TRIDENT2_SUPPORT) 22182 if (!SOC_IS_TOMAHAWKX(unit) && !SOC_IS_MONTEREY(unit) && SOC_IS_TD2_TT2(unit)) { 22183 if (!soc_feature(unit, soc_feature_no_lls)) { 22184 if (soc_trident2_lls_bmap_alloc(unit) < 0) { 22185 goto error; 22186 } 22187 } 22188 } 22189 #endif /* BCM_TRIDENT2_SUPPORT */ 22190 22191 #if defined(BCM_TRIUMPH3_SUPPORT) 22192 if (SOC_IS_TRIUMPH3(unit)) { 22193 if (soc_tr3_lls_bmap_alloc(unit) < 0) { 22194 goto error; 22195 } 22196 } 22197 #endif /* BCM_TRIUMPH3_SUPPORT */ 22198 22199 /* Allocate L2X module and shadow table resources */ 22200 22201 #ifdef BCM_XGS_SWITCH_SUPPORT 22202 if (soc_feature(unit, soc_feature_arl_hashed) && 22203 soc_l2x_attach(unit) < 0) { 22204 goto error; 22205 } 22206 #endif 22207 22208 /* 22209 * Create binary semaphores for interrupt signals, initially empty 22210 * making us block when we try to "take" on them. In soc_intr(), 22211 * when we receive the interrupt, a "give" is performed, which will 22212 * wake us back up. 22213 */ 22214 22215 for (cmc = 0; cmc < SOC_PCI_CMCS_NUM(unit) + 1; cmc++) { 22216 if ((soc->schanIntr[cmc] = 22217 sal_sem_create("SCHAN interrupt", sal_sem_BINARY, 0)) == NULL) { 22218 goto error; 22219 } 22220 } 22221 22222 if ((soc->miimIntr = 22223 sal_sem_create("MIIM interrupt", sal_sem_BINARY, 0)) == NULL) { 22224 goto error; 22225 } 22226 22227 /* Initialize target device */ 22228 22229 if (SAL_BOOT_QUICKTURN) { 22230 soc->schanTimeout = SCHAN_TIMEOUT_QT; 22231 soc->miimTimeout = MIIM_TIMEOUT_QT; 22232 soc->bistTimeout = BIST_TIMEOUT_QT; 22233 } else if (SAL_BOOT_PLISIM) { 22234 soc->schanTimeout = SCHAN_TIMEOUT_PLI; 22235 soc->miimTimeout = MIIM_TIMEOUT_PLI; 22236 soc->bistTimeout = BIST_TIMEOUT_PLI; 22237 } else { 22238 soc->schanTimeout = SCHAN_TIMEOUT; 22239 soc->miimTimeout = MIIM_TIMEOUT; 22240 soc->bistTimeout = BIST_TIMEOUT; 22241 } 22242 22243 soc->schanTimeout = soc_property_get(unit, spn_SCHAN_TIMEOUT_USEC, 22244 soc->schanTimeout); 22245 soc->miimTimeout = soc_property_get(unit, spn_MIIM_TIMEOUT_USEC, 22246 soc->miimTimeout); 22247 soc->bistTimeout = soc_property_get(unit, spn_BIST_TIMEOUT_MSEC, 22248 soc->bistTimeout); 22249 22250 soc->schanIntrEnb = soc_property_get(unit, spn_SCHAN_INTR_ENABLE, 1); 22251 soc->schanIntrBlk = soc_property_get(unit, spn_SCHAN_ERROR_BLOCK_USEC, 22252 250000); 22253 22254 #ifdef INCLUDE_RCPU 22255 if (SOC_IS_RCPU_ONLY(unit)) { 22256 /* 22257 * Use polling mode for RCPU by defalut. If remote interrupt packet is 22258 * enabled for RCPU MIIM access, the register CMIC_INTR_PKT_PACING_DELAY 22259 * should be programmed properly to allow continuous generation of 22260 * interrupt packets. 22261 */ 22262 soc->miimTimeout = MIIM_TIMEOUT_RCPU; 22263 soc->miimIntrEnb = soc_property_get(unit, spn_MIIM_INTR_ENABLE, 0); 22264 } else 22265 #endif /* INCLUDE_RCPU */ 22266 { 22267 /* use polling mode as default during init. Expect to save time */ 22268 soc->miimIntrEnb = soc_property_get(unit, spn_MIIM_INTR_ENABLE, 0); 22269 } 22270 22271 /* arl_notify is also used for Table DMA on 5690 */ 22272 22273 if ((soc->arl_notify = 22274 sal_sem_create("ARL interrupt", sal_sem_BINARY, 0)) == NULL) { 22275 goto error; 22276 } 22277 22278 soc->arl_notified = 0; 22279 22280 soc->arlDropWarn = 0; 22281 22282 soc->arlResyncDelay = 22283 soc_property_get(unit, spn_ARL_RESYNC_DELAY, 3000000); 22284 22285 #ifdef BCM_XGS_SWITCH_SUPPORT 22286 if ((soc->l2x_notify = 22287 sal_sem_create("l2xmsg timer", sal_sem_BINARY, 0)) == NULL) { 22288 goto error; 22289 } 22290 if ((soc->l2x_del_sync = 22291 sal_mutex_create("l2xmsg delete sync")) == NULL) { 22292 goto error; 22293 } 22294 if ((soc->l2x_lock = 22295 sal_sem_create("l2xmsg lock", sal_sem_BINARY, 1)) == NULL) { 22296 goto error; 22297 } 22298 soc->l2x_pid = SAL_THREAD_ERROR; 22299 soc->l2x_interval = 0; 22300 #ifdef BCM_TOMAHAWK3_SUPPORT 22301 if (SOC_IS_TOMAHAWK3(unit)) { 22302 /* Clear L2 learning related data */ 22303 soc->l2x_learn_pid = SAL_THREAD_ERROR; 22304 soc->l2x_learn_interval = 0; 22305 if (soc->l2x_lrn_shadow != NULL) { 22306 shr_avl_delete_all(soc->l2x_lrn_shadow); 22307 shr_avl_destroy(soc->l2x_lrn_shadow); 22308 soc->l2x_lrn_shadow = NULL; 22309 } 22310 22311 if (NULL != soc->l2x_lrn_shadow_mutex) { 22312 sal_mutex_destroy(soc->l2x_lrn_shadow_mutex); 22313 soc->l2x_lrn_shadow_mutex = NULL; 22314 } 22315 soc->lrn_cache_threshold = -1; 22316 soc->lrn_cache_intr_ctl = -1; 22317 soc->lrn_cache_clr_on_rd = -1; 22318 } 22319 #endif /* BCM_TOMAHAWK3_SUPPORT */ 22320 #ifdef BCM_TSN_SUPPORT 22321 if ((soc->l2x_sr_sync = 22322 sal_mutex_create("l2xmsg sr sync")) == NULL) { 22323 goto error; 22324 } 22325 #endif /* BCM_TSN_SUPPORT */ 22326 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 22327 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_KATANA2(unit) || 22328 SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) { 22329 if ((soc->l2x_age_notify = 22330 sal_sem_create("l2xAge timer", sal_sem_BINARY, 0)) == NULL) { 22331 goto error; 22332 } 22333 soc->l2x_age_pid = SAL_THREAD_ERROR; 22334 soc->l2x_age_interval = 0; 22335 soc->l2x_agetime_adjust_usec = 0; 22336 soc->l2x_agetime_curr_timeblk = 0; 22337 soc->l2x_agetime_curr_timeblk_usec = 0; 22338 soc->l2x_prev_age_timeout= 0; 22339 } 22340 #endif 22341 #if defined(BCM_TRIDENT2_SUPPORT) 22342 if (SOC_IS_TRIDENT2X(unit)) { 22343 if ((soc->l2x_age_notify = 22344 sal_sem_create("l2xAge timer", sal_sem_BINARY, 0)) == NULL) { 22345 goto error; 22346 } 22347 if ((soc->l2x_age_sync = 22348 sal_sem_create("l2xAge sync", sal_sem_BINARY, 1)) == NULL) { 22349 goto error; 22350 } 22351 soc->l2x_age_pid = SAL_THREAD_ERROR; 22352 soc->l2x_age_interval = 0; 22353 soc->l2x_age_enable = 0; 22354 soc->l2x_sw_aging = 0; 22355 } 22356 #endif 22357 #endif 22358 22359 /* Create L3 module protection mutex. */ 22360 if ((soc->l3x_lock = sal_mutex_create("L3 module mutex")) == NULL) { 22361 goto error; 22362 } 22363 22364 /* Create FP module protection mutex. */ 22365 if ((soc->fp_lock = sal_mutex_create("FP module mutex")) == NULL) { 22366 goto error; 22367 } 22368 22369 #ifdef INCLUDE_XFLOW_MACSEC 22370 if (soc_feature(unit, soc_feature_xflow_macsec)) { 22371 /* Create XFLOW_MACSEC module protection mutex. */ 22372 if ((soc->xflow_macsec_lock = 22373 sal_mutex_create("XFLOW_MACSEC module mutex")) == NULL) { 22374 goto error; 22375 } 22376 } 22377 #endif 22378 22379 /* Create UDF module protection mutex. */ 22380 if ((soc->udf_lock = sal_mutex_create("UDF module mutex")) == NULL) { 22381 goto error; 22382 } 22383 22384 #ifdef BCM_SBUSDMA_SUPPORT 22385 if (soc_feature(unit, soc_feature_sbusdma)) { 22386 if (soc_sbusdma_init(unit, soc_property_get(unit, spn_DMA_DESC_TIMEOUT_USEC, 0), 22387 soc_property_get(unit, spn_DMA_DESC_INTR_ENABLE, 0))) { 22388 goto error; 22389 } 22390 } 22391 #endif 22392 22393 soc->arl_pid = SAL_THREAD_ERROR; 22394 soc->arl_dma_cnt0 = 0; 22395 soc->arl_dma_xfer = 0; 22396 soc->arl_mbuf_done = 0; 22397 soc->arl_msg_drop = 0; 22398 soc->arl_exit = 1; 22399 soc->arlNextBuf = 0; 22400 soc->arlRateLimit = soc_property_get(unit, spn_ARL_RATE_LIMIT, 3000); 22401 22402 if ((soc->ipfixIntr = 22403 sal_sem_create("IPFIX interrupt", sal_sem_BINARY, 0)) == NULL) { 22404 goto error; 22405 } 22406 22407 #if defined(INCLUDE_REGEX) 22408 if ((soc->ftreportIntr = 22409 sal_sem_create("Regex interrupt", sal_sem_BINARY, 0)) == NULL) { 22410 goto error; 22411 } 22412 #endif 22413 #ifdef BCM_FLOWTRACKER_EXPORT_FIFO_SUPPORT 22414 if ((soc->ftExportIntr = 22415 sal_sem_create("FT DMA Export interrupt", sal_sem_BINARY, 0)) == NULL) { 22416 goto error; 22417 } 22418 #endif /* BCM_FLOWTRACKER_EXPORT_FIFO_SUPPORT */ 22419 22420 soc->ctr_evict_pid = SAL_THREAD_ERROR; 22421 soc->ctr_evict_interval = 0; 22422 soc->ctrEvictIntr = sal_sem_create("Counter eviction interrupt", 22423 sal_sem_BINARY, 0); 22424 if (soc->ctrEvictIntr == NULL) { 22425 goto error; 22426 } 22427 22428 #ifdef BCM_HERCULES_SUPPORT 22429 soc->mmu_errors = NULL; 22430 22431 if (SOC_IS_HERCULES(unit)) { 22432 int port, entry_count; 22433 if ((soc->lla_cells_good = 22434 sal_alloc(SOC_MAX_NUM_PORTS * sizeof(uint32), 22435 "LLA good cells count")) == NULL) { 22436 goto error; 22437 } 22438 22439 if ((soc->lla_map = 22440 sal_alloc(SOC_MAX_NUM_PORTS * sizeof(SHR_BITDCL *), 22441 "LLA map cache pointers")) == NULL) { 22442 goto error; 22443 } 22444 22445 if ((soc->sbe_disable = 22446 sal_alloc(SOC_MAX_NUM_PORTS * sizeof(int), 22447 "PP SBE intr port disable")) == NULL) { 22448 goto error; 22449 } 22450 22451 entry_count = soc_mem_index_count(unit, MEM_LLAm); 22452 PBMP_ALL_ITER(unit, port) { 22453 soc->lla_cells_good[port] = entry_count; 22454 soc->lla_map[port] = NULL; 22455 soc->sbe_disable[port] = FALSE; 22456 } 22457 } else { 22458 soc->lla_cells_good = NULL; 22459 soc->lla_map = NULL; 22460 soc->sbe_disable = NULL; 22461 } 22462 #endif 22463 22464 /* Clear statistics */ 22465 22466 sal_memset(&soc->stat, 0, sizeof (soc->stat)); 22467 22468 /* Initialize link forwarding bitmaps */ 22469 22470 SOC_PBMP_CLEAR(sop->link_fwd); 22471 22472 #ifdef INCLUDE_RCPU 22473 if (SOC_IS_RCPU_ONLY(unit)) { 22474 SOC_PBMP_PORT_ADD(sop->link_fwd, CMIC_PORT(unit)); 22475 if (SOC_PORT_VALID(unit, RCPU_PORT(unit))) { 22476 SOC_PBMP_PORT_ADD(sop->link_fwd, RCPU_PORT(unit)); 22477 } 22478 } 22479 #endif /* INCLUDE_RCPU */ 22480 22481 soc->link_mask2 = PBMP_ALL(unit); 22482 22483 soc->soc_link_pause = 0; 22484 22485 #ifdef BCM_RAVEN_SUPPORT 22486 if (SOC_IS_RAVEN(unit)) { 22487 22488 /* Assume: 22489 * - All ports are internal (max of 128 ports) 22490 * - Internal ports require 3 states in the hardware state machine 22491 * - CMIC is running at 100MHz 22492 */ 22493 soc->hw_linkscan_delay_ns = 128 * 3 * 10; 22494 } 22495 #endif 22496 22497 /* 22498 * Configure nominal IPG register settings. 22499 * By default the IPG should be 96 bit-times. 22500 */ 22501 if (SOC_IS_KATANA2(unit)) { 22502 /* SOC_PBMP_ASSIGN(pbmp_all,PBMP_ALL(unit)); */ 22503 for (port = SOC_INFO(unit).cmic_port; 22504 port <= SOC_INFO(unit).lb_port; 22505 port++) { 22506 SOC_PBMP_PORT_ADD(pbmp_all,port); 22507 } 22508 } else { 22509 SOC_PBMP_ASSIGN(pbmp_all,PBMP_ALL(unit)); 22510 } 22511 /* PBMP_ALL_ITER(unit, port) { */ 22512 SOC_PBMP_ITER(pbmp_all, port) { 22513 sop->ipg[port].hd_10 = 96; 22514 sop->ipg[port].hd_100 = 96; 22515 sop->ipg[port].hd_1000 = 96; 22516 sop->ipg[port].hd_2500 = 96; 22517 22518 sop->ipg[port].fd_10 = 96; 22519 sop->ipg[port].fd_100 = 96; 22520 sop->ipg[port].fd_1000 = 96; 22521 sop->ipg[port].fd_2500 = 96; 22522 sop->ipg[port].fd_10000 = 96; 22523 sop->ipg[port].fd_xe = 96; 22524 sop->ipg[port].fd_hg = 64; 22525 sop->ipg[port].fd_hg2 = 96; 22526 } 22527 22528 /* 22529 * Initialize CES control structs 22530 */ 22531 #if defined(BCM_KATANA_SUPPORT) 22532 soc->ces_ctrl = (void*)NULL; 22533 soc->tdm_ctrl = (void*)NULL; 22534 #endif 22535 22536 if (soc_schan_init(unit) != SOC_E_NONE) { 22537 goto error; 22538 } 22539 22540 LOG_CLI((BSL_META_U(unit, 22541 "SOC unit %d attached to %s device %s\n"), 22542 unit, (soc->soc_flags & SOC_F_RCPU_ONLY) ? "RCPU" : "PCI", 22543 soc_dev_name(unit))); 22544 22545 #ifdef PORTMOD_SUPPORT 22546 if (SOC_USE_PORTCTRL(unit)) { 22547 SOC_IF_ERROR_RETURN( 22548 soc_esw_portctrl_functions_register(unit, soc->chip_driver)); 22549 } 22550 #endif 22551 22552 22553 if (!SOC_IS_HELIX5(unit)) { 22554 #ifdef BCM_CMICX_SUPPORT 22555 if (soc_feature(unit, soc_feature_cmicx)&& !(SAL_BOOT_PLISIM || SAL_BOOT_BCMSIM)) { 22556 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "reset m0ssq\n"))); 22557 /* Put M0 core in reset */ 22558 soc_iproc_m0ssq_reset(unit, M0SSQ_RESET_ENABLE); 22559 } 22560 #endif 22561 } 22562 22563 #ifdef BCM_GREYHOUND_SUPPORT 22564 /* To pause L2 hardware learning when tables are being written. */ 22565 if (SOC_IS_GREYHOUND(unit)) { 22566 if (soc_feature(unit, soc_feature_oam) && 22567 soc_property_get(unit, spn_OAM_PAUSE_L2_LEARN_ON_TABLE_WRITE, 0)) { 22568 soc->l2x_learn_pause_on_table_write = 1; 22569 } 22570 } 22571 #endif /* BCM_GREYHOUND_SUPPORT */ 22572 22573 #if defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 22574 if (soc_property_get(unit, spn_SW_TIMESTAMP_FIFO_ENABLE, 1)) { 22575 soc->sw_timestamp_fifo_enable = 1; 22576 } 22577 #endif /* BCM_TRIUMPH2_SUPPORT | BCM_TRIUMPH3_SUPPORT */ 22578 22579 soc->max_num_pipe = soc_property_get(unit, "num_pipe", NUM_PIPE(unit)); 22580 22581 #ifdef BCM_TOMAHAWK_SUPPORT 22582 if (SOC_IS_TOMAHAWK3(unit)) { 22583 if (dev_id == BCM56983_DEVICE_ID || 22584 soc_property_get(unit, "th3_em_halfchip", 0)) { 22585 soc->em_halfchip = 1; 22586 } 22587 } 22588 #endif /* BCM_TOMAHAWK_SUPPORT */ 22589 22590 return(SOC_E_NONE); 22591 22592 error: 22593 LOG_ERROR(BSL_LS_SOC_COMMON, 22594 (BSL_META_U(unit, 22595 "soc_attach: unit %d failed\n"), unit)); 22596 22597 /* COVERITY 22598 * Intentional stack usage 22599 */ 22600 /* coverity[stack_use_return : FALSE] */ 22601 /* coverity[stack_use_callee_max : FALSE] */ 22602 /* coverity[stack_use_overflow : FALSE] */ 22603 soc_detach(unit); /* Perform necessary clean-ups on error */ 22604 return rv; 22605 } 22606 22607 /* 22608 * Function: 22609 * soc_bpdu_addr_set 22610 * Purpose: 22611 * Set BPDU address 22612 * Parameters: 22613 * unit - StrataSwitch unit # 22614 * index - bpdu index 22615 * addr - mac address 22616 * Returns: 22617 * SOC_E_XXX - on error 22618 * SOC_E_NONE - success 22619 */ 22620 int 22621 soc_bpdu_addr_set(int unit, int index, sal_mac_addr_t addr) 22622 { 22623 #ifdef BCM_XGS3_SWITCH_SUPPORT 22624 if (SOC_IS_XGS3_SWITCH(unit)) { 22625 l2u_entry_t entry; 22626 uint32 mask[3]; 22627 int skip_l2u; 22628 22629 skip_l2u = soc_property_get(unit, spn_SKIP_L2_USER_ENTRY, 0); 22630 if (skip_l2u) { 22631 return SOC_E_UNAVAIL; 22632 } 22633 22634 if ((index < 0) || 22635 (index >= soc_mem_index_count(unit, L2_USER_ENTRYm))) { 22636 return SOC_E_PARAM; 22637 } 22638 sal_memset(&entry, 0, sizeof(entry)); 22639 soc_L2_USER_ENTRYm_field32_set(unit, &entry, VALIDf, 1); 22640 soc_L2_USER_ENTRYm_field32_set(unit, &entry, CPUf, 1); 22641 soc_L2_USER_ENTRYm_field32_set(unit, &entry, BPDUf, 1); 22642 soc_mem_mac_addr_set(unit, L2_USER_ENTRYm, &entry, MAC_ADDRf, addr); 22643 mask[0] = 0xffffffff; 22644 mask[1] = 0x0000ffff; 22645 mask[2] = 0; 22646 soc_L2_USER_ENTRYm_field_set(unit, (uint32 *)&entry, MASKf, mask); 22647 #if defined(BCM_RAVEN_SUPPORT) 22648 if (soc_mem_field_valid(unit, L2_USER_ENTRYm, RESERVED_MASKf)) { 22649 soc_mem_field32_set(unit, L2_USER_ENTRYm, &entry, RESERVED_MASKf, 0); 22650 } 22651 if (soc_mem_field_valid(unit, L2_USER_ENTRYm, RESERVED_KEYf)) { 22652 soc_mem_field32_set(unit, L2_USER_ENTRYm, &entry, RESERVED_KEYf, 0); 22653 } 22654 #endif /* BCM_RAVEN_SUPPORT */ 22655 SOC_IF_ERROR_RETURN(soc_l2u_insert(unit, &entry, index, &index)); 22656 return SOC_E_NONE; 22657 } 22658 #endif 22659 return SOC_E_UNAVAIL; 22660 } 22661 22662 int 22663 soc_bpdu_addr_get(int unit, int index, sal_mac_addr_t *addr) 22664 { 22665 #ifdef BCM_XGS3_SWITCH_SUPPORT 22666 if (SOC_IS_XGS3_SWITCH(unit)) { 22667 l2u_entry_t entry; 22668 int skip_l2u; 22669 22670 skip_l2u = soc_property_get(unit, spn_SKIP_L2_USER_ENTRY, 0); 22671 if (skip_l2u) { 22672 return SOC_E_UNAVAIL; 22673 } 22674 22675 if ((index < 0) || 22676 (index >= soc_mem_index_count(unit, L2_USER_ENTRYm))) { 22677 return SOC_E_PARAM; 22678 } 22679 SOC_IF_ERROR_RETURN(soc_l2u_get(unit, &entry, index)); 22680 if ((0 == soc_L2_USER_ENTRYm_field32_get(unit, &entry, VALIDf)) || 22681 (0 == soc_L2_USER_ENTRYm_field32_get(unit, &entry, BPDUf))) { 22682 /* Not a valid BPDU entry */ 22683 return SOC_E_NOT_FOUND; 22684 } 22685 soc_mem_mac_addr_get(unit, L2_USER_ENTRYm, &entry, MAC_ADDRf, *addr); 22686 return SOC_E_NONE; 22687 } 22688 #endif 22689 return SOC_E_UNAVAIL; 22690 } 22691 22692 /* 22693 * Function: 22694 * soc_esw_hw_qnum_get 22695 * Purpose: 22696 * Get queue to use for PBSMH packet transmission. 22697 * Parameters: 22698 * unit - SOC unit # 22699 * port - SOC port # 22700 * cos - CoS (from Tx packet) 22701 * qnum - (OUT) H/W queue to use 22702 * Returns: 22703 * SOC_E_XXX 22704 */ 22705 int 22706 soc_esw_hw_qnum_get(int unit, int port, int cos, int *qnum) 22707 { 22708 switch (SOC_DCB_TYPE(unit)) { 22709 #ifdef BCM_KATANA_SUPPORT 22710 case 24: 22711 case 29: 22712 *qnum = SOC_INFO(unit).port_uc_cosq_base[port] + cos; 22713 break; 22714 #endif 22715 #ifdef BCM_TRIUMPH3_SUPPORT 22716 case 23: 22717 *qnum = SOC_INFO(unit).port_uc_cosq_base[port] + cos; 22718 break; 22719 #endif 22720 #ifdef BCM_TOMAHAWK_SUPPORT 22721 22722 #endif 22723 #ifdef BCM_TRIDENT2_SUPPORT 22724 case 26: 22725 case 33: 22726 *qnum = SOC_INFO(unit).port_uc_cosq_base[port] + cos; 22727 *qnum = soc_td2_logical_qnum_hw_qnum(unit, port, *qnum, 1); 22728 break; 22729 #endif 22730 #ifdef BCM_APACHE_SUPPORT 22731 case 35: 22732 *qnum = SOC_INFO(unit).port_uc_cosq_base[port] + cos; 22733 #ifdef BCM_MONTEREY_SUPPORT 22734 if (SOC_IS_MONTEREY(unit)) { 22735 *qnum = soc_monterey_logical_qnum_hw_qnum(unit, port, *qnum, 1); 22736 } else 22737 #endif 22738 { 22739 *qnum = soc_apache_logical_qnum_hw_qnum(unit, port, *qnum, 1); 22740 } 22741 break; 22742 #endif 22743 #ifdef BCM_TRIDENT3_SUPPORT 22744 case 36: 22745 22746 #endif 22747 #ifdef BCM_TOMAHAWK3_SUPPORT 22748 case 38: 22749 22750 #endif 22751 22752 default: 22753 *qnum = cos; 22754 break; 22755 } 22756 return SOC_E_NONE; 22757 } 22758 22759 #ifdef INCLUDE_RCPU 22760 /* 22761 * Function: 22762 * soc_rcpu_schan_op_register 22763 * Purpose: 22764 * Registers SCHAN operation routine over RCPU mechanism 22765 * Parameters: 22766 * unit - SOC unit # 22767 * f - (IN) Function to be called for SCHAN operations over RCPU 22768 * Returns: 22769 * SOC_E_XXX 22770 */ 22771 int 22772 soc_rcpu_schan_op_register(int unit, soc_rcpu_schan_op_cb f) 22773 { 22774 if (!SOC_IS_RCPU_UNIT(unit) && !SOC_IS_RCPU_ONLY(unit)) { 22775 return SOC_E_UNAVAIL; 22776 } 22777 22778 if (NULL == f) { 22779 return SOC_E_PARAM; 22780 } 22781 22782 SOC_CONTROL(unit)->soc_rcpu_schan_op = f; 22783 22784 return SOC_E_NONE; 22785 } 22786 22787 /* 22788 * Function: 22789 * soc_rcpu_schan_op_unregister 22790 * Purpose: 22791 * Unregisters SCHAN operation routine over RCPU mechanism 22792 * Schan will be performed via normal flow (PCI or EB) 22793 * Parameters: 22794 * unit - SOC unit # 22795 * Returns: 22796 * SOC_E_XXX 22797 */ 22798 int 22799 soc_rcpu_schan_op_unregister(int unit) 22800 { 22801 if (!SOC_IS_RCPU_UNIT(unit) && !SOC_IS_RCPU_ONLY(unit)) { 22802 return SOC_E_UNAVAIL; 22803 } 22804 22805 SOC_CONTROL(unit)->soc_rcpu_schan_op = NULL; 22806 22807 return SOC_E_NONE; 22808 } 22809 22810 #endif /* INCLUDE_RCPU */ 22811 22812 #ifdef BCM_COSQ_HIGIG_MAP_DISABLE 22813 static const soc_field_t cos_field[8] = { 22814 COS0f, COS1f, COS2f, COS3f, COS4f, COS5f, COS6f, COS7f 22815 }; 22816 22817 /* 22818 * Function: 22819 * soc_cosq_higig_map_disable 22820 * Purpose: 22821 * Initialize the identity mapping for ipics 22822 * Parameters: 22823 * unit - SOC unit # 22824 * Returns: 22825 * SOC_E_XXX 22826 */ 22827 int 22828 soc_cosq_stack_port_map_disable(int unit) 22829 { 22830 soc_port_t port; 22831 uint64 val64; 22832 int prio; 22833 22834 COMPILER_64_ZERO(val64); 22835 for (prio = 0; prio < 8; prio++) { 22836 soc_reg64_field32_set(unit, ICOS_SELr, &val64, 22837 cos_field[prio], prio); 22838 } 22839 PBMP_ST_ITER(unit, port) { 22840 /* map prio0->cos0, prio1->cos1, ... , prio7->cos7 */ 22841 SOC_IF_ERROR_RETURN(WRITE_ICOS_SELr(unit, port, val64)); 22842 } 22843 if (SOC_IS_XGS3_SWITCH(unit)) { 22844 SOC_IF_ERROR_RETURN(WRITE_ICOS_SELr(unit, (CMIC_PORT(unit)), val64)); 22845 } 22846 return SOC_E_NONE; 22847 } 22848 #endif /* BCM_COSQ_HIGIG_MAP_DISABLE */ 22849 22850 #ifdef BCM_XGS3_SWITCH_SUPPORT 22851 static const soc_field_t prio_field[8] = { 22852 PRI0f, PRI1f, PRI2f, PRI3f, PRI4f, PRI5f, PRI6f, PRI7f 22853 }; 22854 22855 /* 22856 * Function: 22857 * soc_cpu_priority_mapping_init 22858 * Purpose: 22859 * Initialize the identity mapping for ipics 22860 * Parameters: 22861 * unit - SOC unit # 22862 * Returns: 22863 * SOC_E_XXX 22864 */ 22865 int 22866 soc_cpu_priority_mapping_init(int unit) 22867 { 22868 int prio; 22869 uint32 val; 22870 22871 val = 0; 22872 for (prio = 0; prio < 8; prio++) { 22873 soc_reg_field_set(unit, CPU_PRIORITY_SELr, &val, 22874 prio_field[prio], prio); 22875 } 22876 SOC_IF_ERROR_RETURN(WRITE_CPU_PRIORITY_SELr(unit, val)); 22877 return SOC_E_NONE; 22878 } 22879 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 22880 22881 int soc_esw_div64(uint64 x, uint32 y, uint32 *result) 22882 { 22883 uint64 rem; 22884 uint64 b; 22885 uint64 res, d; 22886 uint32 high; 22887 22888 COMPILER_64_SET(rem, COMPILER_64_HI(x), COMPILER_64_LO(x)); 22889 COMPILER_64_SET(b, 0, y); 22890 COMPILER_64_SET(d, 0, 1); 22891 22892 high = COMPILER_64_HI(rem); 22893 22894 COMPILER_64_ZERO(res); 22895 if (high >= y) { 22896 /* NOTE: Follow code is used to handle 64bits result 22897 * high /= y; 22898 * res = (uint64_t) (high << 32); 22899 * rem -= (uint64_t)((high * y) << 32); 22900 */ 22901 LOG_ERROR(BSL_LS_SOC_COMMON, 22902 (BSL_META("soc_sbx_div64: result > 32bits\n"))); 22903 return SOC_E_PARAM; 22904 } 22905 22906 while ((!COMPILER_64_BITTEST(b, 63)) && 22907 (COMPILER_64_LT(b, rem)) ) { 22908 COMPILER_64_ADD_64(b,b); 22909 COMPILER_64_ADD_64(d,d); 22910 } 22911 22912 do { 22913 if (COMPILER_64_GE(rem, b)) { 22914 COMPILER_64_SUB_64(rem, b); 22915 COMPILER_64_ADD_64(res, d); 22916 } 22917 COMPILER_64_SHR(b, 1); 22918 COMPILER_64_SHR(d, 1); 22919 } while (!COMPILER_64_IS_ZERO(d)); 22920 22921 *result = COMPILER_64_LO(res); 22922 22923 /* 22924 LOG_VERBOSE(BSL_LS_SOC_COMMON, 22925 (BSL_META_U(unit, 22926 "%s: divisor 0x%x%8.8x dividor 0x%x result 0x%x\n"), 22927 FUNCTION_NAME(), high, COMPILER_64_LO(x), y, *result)); 22928 */ 22929 return 0; 22930 } 22931 22932 22933 /* 22934 * Function: 22935 * soc_warpcore_firmware_set 22936 * Purpose: 22937 * Load Warpcore PHY firmware using hardware acceleration 22938 * Parameters: 22939 * unit - unit number 22940 * port - device port number 22941 * array - (IN) Warpcore firmware data stream pointer 22942 * datalen - length of firmware data stream 22943 * wc_instance - number of the Warpcore in this port block 22944 * wc_ucmem_data - Device specific memory for loading WC firmware 22945 * wc_ucmem_ctrl - Device specific register for selecting WC port 22946 * Returns: 22947 * SOC_E_XXX 22948 */ 22949 int 22950 soc_warpcore_firmware_set(int unit, int port, 22951 uint8 *array, int datalen, int wc_instance, 22952 soc_mem_t wc_ucmem_data, soc_reg_t wc_ucmem_ctrl) 22953 { 22954 soc_control_t *soc; 22955 int entry_bytes, entry_num; 22956 int blk, skip_port = 0, alloc_size = 0; 22957 int count, extra_bytes, i, j; 22958 uint8 *array_ptr, *dma_buf_ptr = NULL; 22959 static int arr_pos_le[3] [16] 22960 = {{15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0}, 22961 { 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7}, 22962 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}}; 22963 static int arr_pos_be[3] [16] 22964 = {{12, 13, 14, 15, 8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2, 3}, 22965 {11, 10, 9, 8, 15, 14, 13, 12, 3, 2, 1, 0, 7, 6, 5, 4}, 22966 {3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12}}; 22967 int *arr_pos; 22968 int pio, packet, other; 22969 int phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 22970 uint32 be_host; 22971 22972 soc = SOC_CONTROL(unit); 22973 22974 entry_bytes = soc_mem_entry_bytes(unit, wc_ucmem_data); 22975 entry_num = soc_mem_index_count(unit, wc_ucmem_data); 22976 if (datalen > (entry_bytes * entry_num)) { 22977 /* Can't fit all of the firmware into the device load table. */ 22978 return SOC_E_RESOURCE; 22979 } 22980 22981 soc_cm_get_endian(unit, &pio, &packet, &other); 22982 if (other) { 22983 if (soc_feature(unit, soc_feature_tsce) || 22984 soc_feature(unit, soc_feature_tscf)) { 22985 arr_pos = arr_pos_be[2]; 22986 } else if (SOC_IS_TD2_TT2(unit)) { 22987 arr_pos = arr_pos_be[1]; 22988 } else { 22989 arr_pos = arr_pos_be[0]; 22990 } 22991 } else { 22992 if (soc_feature(unit, soc_feature_tsce) || 22993 soc_feature(unit, soc_feature_tscf)) { 22994 arr_pos = arr_pos_le[2]; 22995 } else if (SOC_IS_TD2_TT2(unit)) { 22996 arr_pos = arr_pos_le[1]; 22997 } else { 22998 arr_pos = arr_pos_le[0]; 22999 } 23000 /* If platform is keystone big enddian and chip is bcm56545, 23001 * use the arr_pos_be[0]. Because no swaping in CIMIC table DMA.*/ 23002 #if defined(BCM_TRIUMPH3_SUPPORT) && defined(KEYSTONE) && defined(BE_HOST) 23003 if (SOC_IS_TRIUMPH3(unit)) { 23004 arr_pos = arr_pos_be[0]; 23005 } 23006 #endif 23007 } 23008 23009 /* Overwrite the arr_pos according to host endian */ 23010 if (soc_feature(unit, soc_feature_serdes_firmware_pos_by_host_endian)) { 23011 /* We need to byte swap on big endian host */ 23012 be_host = 1; 23013 if (*((uint8 *)&be_host) == 1) { 23014 be_host = 0; 23015 } 23016 if (be_host) { 23017 arr_pos = arr_pos_be[2]; 23018 } else { 23019 arr_pos = arr_pos_le[2]; 23020 } 23021 } 23022 23023 #ifdef BCM_TOMAHAWK_SUPPORT 23024 if (soc_feature(unit, soc_feature_tsce)) { 23025 /* Intercept and handle mgmt ports which use TSCE */ 23026 if ((SOC_IS_TOMAHAWKX(unit) || SOC_IS_TRIDENT3X(unit)) && 23027 (SOC_PBMP_MEMBER(PBMP_MANAGEMENT(unit), (port)))) { 23028 if (soc->soc_wc_ucode_dma_buf2 == NULL) { 23029 count = datalen / entry_bytes; 23030 extra_bytes = datalen % entry_bytes; 23031 soc->soc_wc_ucode_alloc_size2 = datalen; 23032 if (extra_bytes != 0) { 23033 soc->soc_wc_ucode_alloc_size2 += entry_bytes - extra_bytes; 23034 } 23035 soc->soc_wc_ucode_dma_buf2 = 23036 soc_cm_salloc(unit, soc->soc_wc_ucode_alloc_size2, 23037 "WC ucode DMA buffer"); 23038 if (soc->soc_wc_ucode_dma_buf2 == NULL) { 23039 return SOC_E_MEMORY; 23040 } 23041 23042 /* 23043 * The byte order in each 128-bit *_WC_UCMEM_DATA entry is: 23044 * bit position: (bit 31-0) - (bit 63-32) - (bit 95-64) - (bit 127-96) 23045 * byte offset: 0c 0d 0e 0f - 08 09 0a 0b - 04 05 06 07 - 00 01 02 03 23046 */ 23047 array_ptr = array; 23048 dma_buf_ptr = soc->soc_wc_ucode_dma_buf2; 23049 for (i = 0; i < count; i++) { 23050 for (j = 0; j < 16; j++) { 23051 dma_buf_ptr[arr_pos[j]] = array_ptr[j]; 23052 } 23053 array_ptr += entry_bytes; 23054 dma_buf_ptr += entry_bytes; 23055 } 23056 if (extra_bytes != 0) { 23057 sal_memset(dma_buf_ptr, 0, entry_bytes); 23058 for (j = 0; j < extra_bytes; j++) { 23059 dma_buf_ptr[arr_pos[j]] = array_ptr[j]; 23060 } 23061 } 23062 } 23063 datalen = soc->soc_wc_ucode_alloc_size2; 23064 dma_buf_ptr = (uint8*)soc->soc_wc_ucode_dma_buf2; 23065 skip_port = 1; /* Mark port handled */ 23066 } 23067 } 23068 #endif /* BCM_TOMAHAWK_SUPPORT */ 23069 /* Fall back to legacy handling */ 23070 if (!skip_port) { 23071 /* Count the required buffer size */ 23072 count = datalen / entry_bytes; 23073 extra_bytes = datalen % entry_bytes; 23074 alloc_size = datalen; 23075 if (extra_bytes != 0) { 23076 alloc_size += entry_bytes - extra_bytes; 23077 } 23078 23079 /* If the buffer size is different, re-allocate the buffer */ 23080 if (alloc_size != soc->soc_wc_ucode_alloc_size) { 23081 if (soc->soc_wc_ucode_dma_buf != NULL) { 23082 soc_cm_sfree(unit, soc->soc_wc_ucode_dma_buf); 23083 soc->soc_wc_ucode_dma_buf = NULL; 23084 } 23085 23086 soc->soc_wc_ucode_alloc_size = alloc_size; 23087 } 23088 23089 if (soc->soc_wc_ucode_dma_buf == NULL) { 23090 soc->soc_wc_ucode_dma_buf = 23091 soc_cm_salloc(unit, soc->soc_wc_ucode_alloc_size, 23092 "WC ucode DMA buffer"); 23093 if (soc->soc_wc_ucode_dma_buf == NULL) { 23094 return SOC_E_MEMORY; 23095 } 23096 23097 /* 23098 * The byte order in each 128-bit *_WC_UCMEM_DATA entry is: 23099 * bit position: (bit 31-0) - (bit 63-32) - (bit 95-64) - (bit 127-96) 23100 * byte offset: 0c 0d 0e 0f - 08 09 0a 0b - 04 05 06 07 - 00 01 02 03 23101 * 23102 * For Trident2: 23103 * bit position: (bit 31-0) - (bit 63-32) - (bit 95-64) - (bit 127-96) 23104 * byte offset: 0b 0a 09 08 - 0f 0e 0d 0c - 03 02 01 00 - 07 06 05 04 23105 */ 23106 array_ptr = array; 23107 dma_buf_ptr = (uint8*)soc->soc_wc_ucode_dma_buf; 23108 for (i = 0; i < count; i++) { 23109 for (j = 0; j < 16; j++) { 23110 dma_buf_ptr[arr_pos[j]] = array_ptr[j]; 23111 } 23112 array_ptr += entry_bytes; 23113 dma_buf_ptr += entry_bytes; 23114 } 23115 if (extra_bytes != 0) { 23116 sal_memset(dma_buf_ptr, 0, entry_bytes); 23117 for (j = 0; j < extra_bytes; j++) { 23118 dma_buf_ptr[arr_pos[j]] = array_ptr[j]; 23119 } 23120 } 23121 } 23122 datalen = soc->soc_wc_ucode_alloc_size; 23123 dma_buf_ptr = (uint8*)soc->soc_wc_ucode_dma_buf; 23124 } 23125 23126 #if defined(BCM_GREYHOUND_SUPPORT) 23127 if (SOC_IS_GREYHOUND(unit)){ 23128 SOC_IF_ERROR_RETURN(_soc_gh_sbus_tsc_block(unit, 23129 phy_port, wc_ucmem_data, &blk)); 23130 } else 23131 #endif /* BCM_GREYHOUND_SUPPORT */ 23132 #if defined(BCM_HURRICANE3_SUPPORT) 23133 if (SOC_IS_HURRICANE3(unit)){ 23134 SOC_IF_ERROR_RETURN 23135 (soc_hurricane3_sbus_tsc_block(unit, phy_port, &blk)); 23136 23137 if (SOC_REG_BLOCK_IS(unit, wc_ucmem_ctrl, SOC_BLK_PMQ)) { 23138 port = blk | SOC_REG_ADDR_BLOCK_ID_MASK; 23139 } 23140 } else 23141 #endif /* BCM_GREYHOUND_SUPPORT */ 23142 #if defined(BCM_GREYHOUND2_SUPPORT) 23143 if (SOC_IS_GREYHOUND2(unit)){ 23144 SOC_IF_ERROR_RETURN 23145 (soc_greyhound2_sbus_tsc_block(unit, phy_port, &blk)); 23146 23147 if (SOC_REG_BLOCK_IS(unit, wc_ucmem_ctrl, SOC_BLK_PMQ)) { 23148 /* Port orverride for PMQ block register access */ 23149 port = blk | SOC_REG_ADDR_BLOCK_ID_MASK; 23150 } 23151 } else 23152 #endif /* BCM_GREYHOUND2_SUPPORT */ 23153 { 23154 blk = SOC_PORT_BLOCK(unit, phy_port); 23155 } 23156 23157 /* enable parallel bus access */ 23158 SOC_IF_ERROR_RETURN 23159 (soc_reg_field32_modify(unit, wc_ucmem_ctrl, port, 23160 ACCESS_MODEf, 1)); 23161 if (soc_reg_field_valid(unit, wc_ucmem_ctrl, INST_SELECTf)) { 23162 SOC_IF_ERROR_RETURN 23163 (soc_reg_field32_modify(unit, wc_ucmem_ctrl, port, 23164 INST_SELECTf, wc_instance)); 23165 } 23166 if (soc_reg_field_valid(unit, wc_ucmem_ctrl, WR_BROADCASTf)) { 23167 SOC_IF_ERROR_RETURN 23168 (soc_reg_field32_modify(unit, wc_ucmem_ctrl, port, 23169 WR_BROADCASTf, 23170 IS_C_PORT(unit, port) ? 1 : 0)); 23171 } 23172 23173 SOC_IF_ERROR_RETURN 23174 (soc_mem_write_range(unit, wc_ucmem_data, blk, 0, 23175 datalen / entry_bytes - 1, dma_buf_ptr)); 23176 23177 /* disable parallel bus access, and enable MDIO access */ 23178 SOC_IF_ERROR_RETURN 23179 (soc_reg_field32_modify(unit, wc_ucmem_ctrl, port, 23180 ACCESS_MODEf, 0)); 23181 23182 return SOC_E_NONE; 23183 } 23184 23185 STATIC uint32 23186 soc_sbus_mdio_addr(uint32 phy_addr, uint32 phy_reg) 23187 { 23188 int devad; 23189 uint32 sbus_mdio_addr; 23190 23191 /* Extract lane and DEVAD from address extension */ 23192 devad = (phy_reg >> 27) & 0x1f; 23193 23194 /* Build WC/TSC PHY register address */ 23195 sbus_mdio_addr = (phy_reg & 0xffff); 23196 sbus_mdio_addr |= ((phy_addr & 0x1f) << 19); 23197 sbus_mdio_addr |= (devad << 27); 23198 23199 return sbus_mdio_addr; 23200 } 23201 23202 STATIC uint32 23203 soc_sbus_mdio_lane(uint32 phy_reg) 23204 { 23205 /* Extract lane from address extension */ 23206 return (phy_reg >> 16) & 0x7; 23207 } 23208 23209 int 23210 soc_sbus_mdio_reg_read(int unit, int port, int blk, int wc_instance, 23211 uint32 phy_addr, uint32 phy_reg, uint32 *phy_data, 23212 soc_mem_t wc_ucmem_data, soc_reg_t wc_ucmem_ctrl) 23213 { 23214 int rv = SOC_E_NONE; 23215 int entry_bytes; 23216 uint32 ucmem_entry[16]; 23217 23218 entry_bytes = soc_mem_entry_bytes(unit, wc_ucmem_data); 23219 if (entry_bytes > sizeof(ucmem_entry)) { 23220 return SOC_E_PARAM; 23221 } 23222 23223 sal_memset(ucmem_entry, 0, sizeof(ucmem_entry)); 23224 23225 soc_mem_lock(unit, wc_ucmem_data); 23226 23227 if (soc_reg_field_valid(unit, wc_ucmem_ctrl, INST_SELECTf)) { 23228 SOC_IF_ERROR_RETURN 23229 (soc_reg_field32_modify(unit, wc_ucmem_ctrl, port, 23230 INST_SELECTf, wc_instance)); 23231 } 23232 23233 /* Write AER register */ 23234 ucmem_entry[0] = soc_sbus_mdio_addr(phy_addr, 0xffde); 23235 ucmem_entry[1] = (soc_sbus_mdio_lane(phy_reg) << 16); 23236 ucmem_entry[2] = 1; /* Write register */ 23237 rv = soc_mem_write(unit, wc_ucmem_data, blk, 0, &ucmem_entry); 23238 23239 /* Setup PHY register address */ 23240 ucmem_entry[0] = soc_sbus_mdio_addr(phy_addr, phy_reg) | ucmem_entry[1]; 23241 ucmem_entry[2] = 0; /* Read register */ 23242 if (SOC_SUCCESS(rv)) { 23243 rv = soc_mem_write(unit, wc_ucmem_data, blk, 0, &ucmem_entry); 23244 } 23245 23246 /* Read PHY register contents */ 23247 if (SOC_SUCCESS(rv)) { 23248 rv = soc_mem_read(unit, wc_ucmem_data, blk, 0, &ucmem_entry); 23249 } 23250 23251 soc_mem_unlock(unit, wc_ucmem_data); 23252 23253 if (SOC_IS_APACHE(unit)) { 23254 *phy_data = ucmem_entry[1]; 23255 } else { 23256 *phy_data = ucmem_entry[0]; 23257 } 23258 23259 LOG_INFO(BSL_LS_SOC_MII, 23260 (BSL_META_U(unit, 23261 "soc_sbus_mdio_reg_read[%d]: " 23262 "addr=0x%x reg=0x%08x data=0x%04x (%d/%d/%d/%d)\n"), 23263 unit, phy_addr, phy_reg, *phy_data, 23264 port, blk, wc_instance, rv)); 23265 23266 return rv; 23267 } 23268 23269 int 23270 soc_sbus_mdio_reg_write(int unit, int port, int blk, int wc_instance, 23271 uint32 phy_addr, uint32 phy_reg, uint32 phy_data, 23272 soc_mem_t wc_ucmem_data, soc_reg_t wc_ucmem_ctrl) 23273 { 23274 int rv = SOC_E_NONE; 23275 int entry_bytes; 23276 uint32 ucmem_entry[16]; 23277 23278 entry_bytes = soc_mem_entry_bytes(unit, wc_ucmem_data); 23279 if (entry_bytes > sizeof(ucmem_entry)) { 23280 return SOC_E_PARAM; 23281 } 23282 23283 /* If write mask (upper 16 bits) is empty, add full mask */ 23284 if ((phy_data & 0xffff0000) == 0) { 23285 phy_data |= 0xffff0000; 23286 } 23287 sal_memset(ucmem_entry, 0, sizeof(ucmem_entry)); 23288 23289 soc_mem_lock(unit, wc_ucmem_data); 23290 23291 if (soc_reg_field_valid(unit, wc_ucmem_ctrl, INST_SELECTf)) { 23292 SOC_IF_ERROR_RETURN 23293 (soc_reg_field32_modify(unit, wc_ucmem_ctrl, port, 23294 INST_SELECTf, wc_instance)); 23295 } 23296 23297 /* Write AER register */ 23298 ucmem_entry[0] = soc_sbus_mdio_addr(phy_addr, 0xffde); 23299 ucmem_entry[1] = (soc_sbus_mdio_lane(phy_reg) << 16); 23300 ucmem_entry[2] = 1; /* Write register */ 23301 rv = soc_mem_write(unit, wc_ucmem_data, blk, 0, &ucmem_entry); 23302 23303 /* Write PHY register */ 23304 if (SOC_SUCCESS(rv)) { 23305 ucmem_entry[0] = soc_sbus_mdio_addr(phy_addr, phy_reg) | ucmem_entry[1]; 23306 ucmem_entry[1] = (phy_data << 16); 23307 rv = soc_mem_write(unit, wc_ucmem_data, blk, 0, &ucmem_entry); 23308 } 23309 23310 soc_mem_unlock(unit, wc_ucmem_data); 23311 23312 LOG_INFO(BSL_LS_SOC_MII, 23313 (BSL_META_U(unit, 23314 "soc_sbus_mdio_reg_write[%d]: " 23315 "addr=0x%x reg=0x%08x data=0x%04x (%d/%d/%d/%d)\n"), 23316 unit, phy_addr, phy_reg, phy_data, 23317 port, blk, wc_instance, rv)); 23318 23319 return rv; 23320 } 23321 23322 int 23323 soc_sbus_tsc_reg_read(int unit, int port, int blk, uint32 phy_addr, 23324 uint32 phy_reg, uint32 *phy_data) 23325 { 23326 int rv = SOC_E_NONE; 23327 int pport = SOC_INFO(unit).port_l2p_mapping[port]; 23328 int entry_bytes; 23329 uint32 ucmem_entry[16]; 23330 soc_mem_t mem = XLPORT_WC_UCMEM_DATAm; 23331 #ifdef BCM_TOMAHAWK3_SUPPORT 23332 int pm_type; 23333 #endif 23334 23335 #if 0 23336 /* TSC reg read/write is handled by PortMod internally */ 23337 if (SOC_USE_PORTCTRL(unit)) { 23338 return SOC_E_INTERNAL; 23339 } 23340 #endif 23341 23342 LOG_DEBUG(BSL_LS_SOC_MII, 23343 (BSL_META_U(unit, 23344 "soc_sbus_tsc_reg_read" 23345 "(%d,%d,%d,0x%x,0x%08x,*phy_data)..\n"), 23346 unit, port, blk, phy_addr, phy_reg)); 23347 23348 if (soc_feature(unit, soc_feature_tscf)) { 23349 if (SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_CLPORT && 23350 SOC_MEM_IS_VALID(unit, CLPORT_WC_UCMEM_DATAm)) { 23351 mem = CLPORT_WC_UCMEM_DATAm; 23352 } 23353 } 23354 23355 if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_GPORT && 23356 SOC_MEM_IS_VALID(unit, GPORT_WC_UCMEM_DATAm)) { 23357 mem = GPORT_WC_UCMEM_DATAm; 23358 } 23359 23360 if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_CDPORT && 23361 SOC_MEM_IS_VALID(unit, CDPORT_TSC_UCMEM_DATAm)) { 23362 mem = CDPORT_TSC_UCMEM_DATAm; 23363 } 23364 23365 if (SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_PMQPORT && 23366 SOC_MEM_IS_VALID(unit, PMQPORT_WC_UCMEM_DATAm)) { 23367 mem = PMQPORT_WC_UCMEM_DATAm; 23368 } 23369 23370 entry_bytes = soc_mem_entry_bytes(unit, mem); 23371 if (entry_bytes > sizeof(ucmem_entry)) { 23372 return SOC_E_PARAM; 23373 } 23374 23375 sal_memset(ucmem_entry, 0, sizeof(ucmem_entry)); 23376 23377 soc_mem_lock(unit, mem); 23378 23379 /* Expect phy_reg here carried full 32 bits TSC address already. */ 23380 23381 /* assigning TSC register address to wc_ucmem_data[31:0] */ 23382 ucmem_entry[0] = phy_reg & 0xffffffff; 23383 ucmem_entry[2] = 0; /* for TSC register READ */ 23384 LOG_DEBUG(BSL_LS_SOC_MII, 23385 (BSL_META_U(unit, 23386 " ucmem_data_entry[95:64-63:32-31:0]=" 23387 "0x%08x-0x%08x-0x%08x\n"), 23388 ucmem_entry[0], ucmem_entry[1], ucmem_entry[2])); 23389 SOC_ALLOW_WB_WRITE(unit, soc_mem_write(unit, mem, blk, 0, &ucmem_entry), rv); 23390 23391 /* read data back from wc_ucmem_data[47:32] */ 23392 if (SOC_SUCCESS(rv)) { 23393 rv = soc_mem_read(unit, mem, blk, 0, &ucmem_entry); 23394 } 23395 23396 #ifdef BCM_TOMAHAWK3_SUPPORT 23397 if (SOC_PORTCTRL_FUNCTIONS(unit) && 23398 SOC_PORTCTRL_FUNCTIONS(unit)->soc_portctrl_pm_type_get) { 23399 23400 rv = SOC_PORTCTRL_FUNCTIONS(unit)->soc_portctrl_pm_type_get(unit, 23401 pport, &pm_type); 23402 23403 if (SOC_FAILURE(rv)) { 23404 return rv; 23405 } 23406 if (pm_type == portmodDispatchTypePm8x50) { 23407 *phy_data = (ucmem_entry[1] >> 16) & 0xffff; 23408 } else { 23409 *phy_data = ucmem_entry[1]; 23410 } 23411 } else 23412 #endif 23413 { 23414 *phy_data = ucmem_entry[1]; 23415 } 23416 23417 soc_mem_unlock(unit, mem); 23418 23419 LOG_DEBUG(BSL_LS_SOC_MII, 23420 (BSL_META_U(unit, 23421 "soc_sbus_tsc_reg_read: *phy_data=0x%04x,rv=%d\n"), 23422 *phy_data, rv)); 23423 23424 return rv; 23425 23426 } 23427 23428 int 23429 soc_sbus_tsc_reg_write(int unit, int port, int blk, uint32 phy_addr, 23430 uint32 phy_reg, uint32 phy_data) 23431 { 23432 int rv = SOC_E_NONE; 23433 int pport = SOC_INFO(unit).port_l2p_mapping[port]; 23434 int entry_bytes; 23435 uint32 ucmem_entry[16]; 23436 uint32 data, data_mask; 23437 soc_mem_t mem = XLPORT_WC_UCMEM_DATAm; 23438 23439 #if 0 23440 /* TSC reg read/write is handled by PortMod internally */ 23441 if (SOC_USE_PORTCTRL(unit)) { 23442 return SOC_E_INTERNAL; 23443 } 23444 #endif 23445 23446 LOG_DEBUG(BSL_LS_SOC_MII, 23447 (BSL_META_U(unit, 23448 "soc_sbus_tsc_reg_write" 23449 "(%d,%d,%d,0x%x,0x%08x,0x%04x)..\n"), 23450 unit, port, blk, phy_addr, phy_reg, phy_data)); 23451 23452 if (soc_feature(unit, soc_feature_tscf)) { 23453 if (SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_CLPORT && 23454 SOC_MEM_IS_VALID(unit, CLPORT_WC_UCMEM_DATAm)) { 23455 mem = CLPORT_WC_UCMEM_DATAm; 23456 } 23457 } 23458 23459 if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_GPORT && 23460 SOC_MEM_IS_VALID(unit, GPORT_WC_UCMEM_DATAm)) { 23461 mem = GPORT_WC_UCMEM_DATAm; 23462 } 23463 23464 if (SOC_PORT_BLOCK_TYPE(unit, pport) == SOC_BLK_CDPORT && 23465 SOC_MEM_IS_VALID(unit, CDPORT_TSC_UCMEM_DATAm)) { 23466 mem = CDPORT_TSC_UCMEM_DATAm; 23467 } 23468 23469 if (SOC_BLOCK_INFO(unit, blk).type == SOC_BLK_PMQPORT && 23470 SOC_MEM_IS_VALID(unit, PMQPORT_WC_UCMEM_DATAm)) { 23471 mem = PMQPORT_WC_UCMEM_DATAm; 23472 } 23473 23474 entry_bytes = soc_mem_entry_bytes(unit, mem); 23475 if (entry_bytes > sizeof(ucmem_entry)) { 23476 return SOC_E_PARAM; 23477 } 23478 23479 /* If write mask (upper 16 bits) is empty, add full mask */ 23480 if ((phy_data & 0xffff0000) == 0) { 23481 phy_data |= 0xffff0000; 23482 } 23483 sal_memset(ucmem_entry, 0, sizeof(ucmem_entry)); 23484 23485 soc_mem_lock(unit, mem); 23486 23487 /* Expect phy_reg here carried full 32 bits TSC address already. */ 23488 23489 /* assigning TSC register address to wc_ucmem_data[31:0] and write the 23490 * data/datamask to to wc_ucmem_data[63:32] */ 23491 ucmem_entry[0] = phy_reg & 0xffffffff; 23492 /* data : wc_ucmem_data[48:63] datamask : wc_ucmem_data[32:47] */ 23493 data = (phy_data & 0xffff) << 16; 23494 data_mask = (~phy_data & 0xffff0000) >> 16; 23495 ucmem_entry[1] = data | data_mask; 23496 ucmem_entry[2] = 1; /* for TSC register write */ 23497 LOG_DEBUG(BSL_LS_SOC_MII, 23498 (BSL_META_U(unit, 23499 " ucmem_data_entry[95:64-63:32-31:0]=" 23500 "0x%08x-0x%08x-0x%08x\n"), 23501 ucmem_entry[0], ucmem_entry[1], ucmem_entry[2])); 23502 23503 rv = soc_mem_write(unit, mem, blk, 0, &ucmem_entry); 23504 23505 soc_mem_unlock(unit, mem); 23506 23507 LOG_DEBUG(BSL_LS_SOC_MII, 23508 (BSL_META_U(unit, 23509 "soc_sbus_tsc_reg_write : rv=%d\n"),rv)); 23510 23511 return rv; 23512 } 23513 23514 23515 /* 23516 * Function: 23517 * soc_dump 23518 * Purpose: 23519 * Dump useful information from the soc structure. 23520 * Parameters: 23521 * unit - unit number to dump 23522 * pfx - character string to prefix output line. 23523 * Returns: 23524 * SOC_E_XXX 23525 */ 23526 23527 int 23528 soc_dump(int unit, const char *pfx) 23529 { 23530 soc_control_t *soc; 23531 soc_persist_t *sop; 23532 soc_stat_t *stat; 23533 int i; 23534 uint16 dev_id; 23535 uint8 rev_id; 23536 23537 if (!SOC_UNIT_VALID(unit)) { 23538 return(SOC_E_UNIT); 23539 } 23540 23541 soc = SOC_CONTROL(unit); 23542 sop = SOC_PERSIST(unit); 23543 23544 stat = SOC_STAT(unit); 23545 23546 LOG_CLI((BSL_META_U(unit, 23547 "%sUnit %d Driver Control Structure:\n"), pfx, unit)); 23548 23549 soc_cm_get_id(unit, &dev_id, &rev_id); 23550 23551 LOG_CLI((BSL_META_U(unit, 23552 "%sChip=%s Rev=0x%02x Driver=%s\n"), 23553 pfx, 23554 soc_dev_name(unit), 23555 rev_id, 23556 SOC_CHIP_NAME(soc->chip_driver->type))); 23557 LOG_CLI((BSL_META_U(unit, 23558 "%sFlags=0x%x:"), 23559 pfx, soc->soc_flags)); 23560 if (soc->soc_flags & SOC_F_ATTACHED) { 23561 LOG_CLI((BSL_META_U(unit, 23562 " attached"))); 23563 } 23564 if (soc->soc_flags & SOC_F_INITED) { 23565 LOG_CLI((BSL_META_U(unit, 23566 " initialized"))); 23567 } 23568 if (soc->soc_flags & SOC_F_LSE) { 23569 LOG_CLI((BSL_META_U(unit, 23570 " link-scan"))); 23571 } 23572 if (soc->soc_flags & SOC_F_SL_MODE) { 23573 LOG_CLI((BSL_META_U(unit, 23574 " sl-mode"))); 23575 } 23576 if (soc->soc_flags & SOC_F_POLLED) { 23577 LOG_CLI((BSL_META_U(unit, 23578 " polled"))); 23579 } 23580 if (soc->soc_flags & SOC_F_URPF_ENABLED) { 23581 LOG_CLI((BSL_META_U(unit, 23582 " urpf"))); 23583 } 23584 if (soc->soc_flags & SOC_F_MEM_CLEAR_USE_DMA) { 23585 LOG_CLI((BSL_META_U(unit, 23586 " mem-clear-use-dma"))); 23587 } 23588 if (soc->soc_flags & SOC_F_IPMCREPLSHR) { 23589 LOG_CLI((BSL_META_U(unit, 23590 " ipmc-repl-shared"))); 23591 } 23592 if (soc->remote_cpu) { 23593 LOG_CLI((BSL_META_U(unit, 23594 " rcpu"))); 23595 } 23596 LOG_CLI((BSL_META_U(unit, 23597 "; board type 0x%x"), soc->board_type)); 23598 LOG_CLI((BSL_META_U(unit, 23599 "\n"))); 23600 LOG_CLI((BSL_META_U(unit, 23601 "%s"), pfx)); 23602 soc_cm_dump(unit); 23603 23604 LOG_CLI((BSL_META_U(unit, 23605 "%sDisabled: reg_flags=0x%x mem_flags=0x%x\n"), 23606 pfx, 23607 soc->disabled_reg_flags, soc->disabled_mem_flags)); 23608 LOG_CLI((BSL_META_U(unit, 23609 "%sSchanOps=%d MMUdbg=%d LinkPause=%d\n"), 23610 pfx, 23611 stat->schan_op, 23612 sop->debugMode, soc->soc_link_pause)); 23613 LOG_CLI((BSL_META_U(unit, 23614 "%sCounter: int=%dus per=%dus dmaBuf=%p\n" 23615 "%s EvictInvalidPoolIdCount=%u\n"), 23616 pfx, 23617 soc->counter_interval, 23618 SAL_USECS_SUB(soc->counter_coll_cur, soc->counter_coll_prev), 23619 (void *)soc->counter_buf32, 23620 pfx, soc->counter_evict_inval_poolid_count)); 23621 LOG_CLI((BSL_META_U(unit, 23622 "%sTimeout: Schan=%d(%dus) MIIM=%d(%dus)\n"), 23623 pfx, 23624 stat->err_sc_tmo, soc->schanTimeout, 23625 stat->err_mii_tmo, soc->miimTimeout)); 23626 LOG_CLI((BSL_META_U(unit, 23627 "%sIntr: Total=%d Sc=%d ScErr=%d MMU/ARLErr=%d\n" 23628 "%s LinkStat=%d PCIfatal=%d PCIparity=%d\n" 23629 "%s ARLdrop=%d ARLmbuf=%d ARLxfer=%d ARLcnt0=%d\n" 23630 "%s TableDMA=%d TSLAM-DMA=%d" 23631 " CCM-DMA=%d SW=%d" 23632 "\n%s MemCmd[BSE]=%d MemCmd[CSE]=%d MemCmd[HSE]=%d\n" 23633 "%s ChipFunc[0]=%d ChipFunc[1]=%d ChipFunc[2]=%d\n" 23634 "%s ChipFunc[3]=%d ChipFunc[4]=%d\n" 23635 "%s FifoDma[0]=%d FifoDma[1]=%d FifoDma[2]=%d FifoDma[3]=%d\n" 23636 "%s I2C=%d MII=%d StatsDMA=%d Desc=%d Chain=%d PciTimeOut=%d\n"), 23637 pfx, stat->intr, stat->intr_sc, stat->intr_sce, stat->intr_mmu, 23638 pfx, stat->intr_ls, 23639 stat->intr_pci_fe, stat->intr_pci_pe, 23640 pfx, stat->intr_arl_d, stat->intr_arl_m, 23641 stat->intr_arl_x, stat->intr_arl_0, 23642 pfx, stat->intr_tdma, stat->intr_tslam, 23643 stat->intr_ccmdma, stat->intr_sw, 23644 pfx, stat->intr_mem_cmd[0], 23645 stat->intr_mem_cmd[1], stat->intr_mem_cmd[2], 23646 pfx, stat->intr_chip_func[0], stat->intr_chip_func[1], 23647 stat->intr_chip_func[2], 23648 pfx, stat->intr_chip_func[3], stat->intr_chip_func[4], 23649 pfx, stat->intr_fifo_dma[0], stat->intr_fifo_dma[1], 23650 stat->intr_fifo_dma[2], stat->intr_fifo_dma[3], 23651 pfx, stat->intr_i2c, stat->intr_mii, stat->intr_stats, 23652 stat->intr_desc, stat->intr_chain, stat->pci_cmpl_timeout)); 23653 LOG_CLI((BSL_META_U(unit, 23654 "%sError: SDRAM=%d CFAP=%d Fcell=%d MmuSR=%d\n"), 23655 pfx, 23656 stat->err_sdram, stat->err_cfap, 23657 stat->err_fcell, stat->err_sr)); 23658 #ifdef BCM_CMICX_SUPPORT 23659 if (soc_feature(unit, soc_feature_cmicx)) { 23660 LOG_CLI((BSL_META_U(unit, 23661 "%sM0: msg=%d resp=%d intr=%d\n"), 23662 pfx, 23663 stat->m0_msg, stat->m0_resp, 23664 stat->m0_intr)); 23665 23666 LOG_CLI((BSL_META_U(unit, 23667 "%sUc sw programmable total intr=%d\n"), 23668 pfx, 23669 stat->uc_sw_prg_intr)); 23670 23671 LOG_CLI((BSL_META_U(unit, 23672 "%sM0 sw programmable intr: u0=%d u1=%d u2=%d u3=%d\n"), 23673 pfx, 23674 stat->m0_u0_sw_intr, stat->m0_u1_sw_intr, 23675 stat->m0_u2_sw_intr, stat->m0_u3_sw_intr)); 23676 23677 LOG_CLI((BSL_META_U(unit, 23678 "%sSBUS DMA err_intr_res=%u\n"), 23679 pfx, 23680 stat->err_sbusdma_intr_res)); 23681 23682 } 23683 #endif 23684 if (soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 23685 LOG_CLI((BSL_META_U(unit, 23686 "%sSER events(mem=%d reg=%d nak=%d stat=%d ecc=%d " 23687 "direct=%d fifo=%d tcam=%d)\n"), 23688 pfx, 23689 stat->ser_err_mem, stat->ser_err_reg, 23690 stat->ser_err_nak, stat->ser_err_stat, 23691 stat->ser_err_ecc, stat->ser_err_int, 23692 stat->ser_err_fifo, stat->ser_err_tcam)); 23693 if (SOC_SER_CORRECTION_SUPPORT(unit)) { 23694 LOG_CLI((BSL_META_U(unit, 23695 "%sSER corrections(fix=%d clear=%d " 23696 "restore=%d special=%d err:%d)\n"), 23697 pfx, stat->ser_err_corr, stat->ser_err_clear, 23698 stat->ser_err_restor, stat->ser_err_spe, 23699 stat->ser_err_sw)); 23700 } 23701 } 23702 LOG_CLI((BSL_META_U(unit, 23703 "%sPKT DMA: dcb=t%d tpkt=%u tbyt=%u rpkt=%u rbyt=%u\n"), 23704 pfx, 23705 SOC_DCB_TYPE(unit), 23706 stat->dma_tpkt, stat->dma_tbyt, 23707 stat->dma_rpkt, stat->dma_rbyt)); 23708 LOG_CLI((BSL_META_U(unit, 23709 "%sDV: List: max-q=%d cur-tq=%d cur-rq=%d dv-size=%d\n"), 23710 pfx, 23711 soc->soc_dv_cnt, soc->soc_dv_tx_free_cnt, 23712 soc->soc_dv_rx_free_cnt, soc->soc_dv_size)); 23713 LOG_CLI((BSL_META_U(unit, 23714 "%sDV: Statistics: allocs=%d frees=%d alloc-q=%d\n"), 23715 pfx, stat->dv_alloc, stat->dv_free, stat->dv_alloc_q)); 23716 if (soc_feature(unit, soc_feature_mem_cache) && 23717 soc_property_get(unit, spn_MEM_CACHE_ENABLE, TRUE)) { 23718 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_HELIX4_SUPPORT) || \ 23719 defined(BCM_KATANA2_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) || \ 23720 defined(BCM_GREYHOUND_SUPPORT) 23721 LOG_CLI((BSL_META_U(unit, 23722 "%sMem cache (count=%d size=%d vmap size=%d " 23723 "errmap size=%d)\n"), 23724 pfx, 23725 stat->mem_cache_count, stat->mem_cache_size, 23726 stat->mem_cache_vmap_size, stat->tcam_corrupt_map_size)); 23727 #else 23728 LOG_CLI((BSL_META_U(unit, 23729 "%sMem cache (count=%d size=%d vmap size=%d)\n"), pfx, 23730 stat->mem_cache_count, stat->mem_cache_size, 23731 stat->mem_cache_vmap_size)); 23732 #endif 23733 } 23734 #if defined(BCM_XGS_SUPPORT) 23735 if (soc_feature(unit, soc_feature_regs_as_mem)) { 23736 int count, size; 23737 soc_ser_reg_cache_info(unit, &count, &size); 23738 LOG_CLI((BSL_META_U(unit, 23739 "%sReg cache (count=%d size=%d)\n"), 23740 pfx, count, size)); 23741 } 23742 #endif /* BCM_XGS_SUPPORT */ 23743 for (i = 0; i < soc->soc_max_channels; i++) { 23744 sdc_t *sdc = &soc->soc_channels[i]; 23745 char *type; 23746 switch(sdc->sc_type) { 23747 case DV_NONE: type = "--"; break; 23748 case DV_TX: type = "TX"; break; 23749 case DV_RX: type = "RX"; break; 23750 default: type = "*INVALID*"; break; 23751 } 23752 LOG_CLI((BSL_META_U(unit, 23753 "%sdma-ch-%d %s %s Queue=%d (%p)%s%s%s%s\n"), 23754 pfx, i, type, 23755 sdc->sc_dv_active ? "Active" : "Idle ", 23756 sdc->sc_q_cnt, (void *)sdc->sc_q, 23757 (sdc->sc_flags & SOC_DMA_F_DEFAULT) ? " default" : "", 23758 (sdc->sc_flags & SOC_DMA_F_POLL) ? " polled" : " intr", 23759 (sdc->sc_flags & SOC_DMA_F_MBM) ? " mbm" : " no-mbm", 23760 (sdc->sc_flags & SOC_DMA_F_TX_DROP) ? " tx-drop" : "")); 23761 } 23762 23763 return(0); 23764 } 23765 23766 #if defined(BROADCOM_DEBUG) 23767 /* 23768 * Function: 23769 * soc_chip_dump 23770 * Purpose: 23771 * Display driver and chip information 23772 * Notes: 23773 * Pass unit -1 to avoid referencing unit number. 23774 */ 23775 23776 void 23777 soc_chip_dump(int unit, soc_driver_t *d) 23778 { 23779 soc_info_t *si; 23780 int i, count = 0; 23781 soc_port_t port; 23782 soc_port_t port1; 23783 char pfmt[SOC_PBMP_FMT_LEN]; 23784 uint16 dev_id; 23785 uint8 rev_id; 23786 int blk, bindex; 23787 char instance_string[3], block_name[14]; 23788 #if defined(BCM_KATANA2_SUPPORT) 23789 soc_field_t wc_xfi_mode_sel_fld[]={WC0_8_XFI_MODE_SELf,WC1_8_XFI_MODE_SELf}; 23790 uint32 wc_xfi_mode_sel_val[2]={0}; 23791 uint32 top_misc_control_1_val = 0; 23792 #endif 23793 23794 23795 if (d == NULL) { 23796 LOG_CLI((BSL_META_U(unit, 23797 "unit %d: no driver attached\n"), unit)); 23798 return; 23799 } 23800 23801 LOG_CLI((BSL_META_U(unit, 23802 "driver %s (%s)\n"), SOC_CHIP_NAME(d->type), d->chip_string)); 23803 LOG_CLI((BSL_META_U(unit, 23804 "\tregsfile\t\t%s\n"), d->origin)); 23805 LOG_CLI((BSL_META_U(unit, 23806 "\tpci identifier\t\tvendor 0x%04x device 0x%04x rev 0x%02x\n"), 23807 d->pci_vendor, d->pci_device, d->pci_revision)); 23808 LOG_CLI((BSL_META_U(unit, 23809 "\tclasses of service\t%d\n"), d->num_cos)); 23810 LOG_CLI((BSL_META_U(unit, 23811 "\tmaximums\t\tblock %d ports %d mem_bytes %d\n"), 23812 SOC_MAX_NUM_BLKS, SOC_MAX_NUM_PORTS, SOC_MAX_MEM_BYTES)); 23813 23814 if (unit < 0) { 23815 return; 23816 } 23817 si = &SOC_INFO(unit); 23818 for (blk = 0; d->block_info[blk].type >= 0; blk++) { 23819 sal_snprintf(instance_string, sizeof(instance_string), "%d", 23820 d->block_info[blk].number); 23821 if (d->block_info[blk].type == SOC_BLK_PORT_GROUP4 || 23822 d->block_info[blk].type == SOC_BLK_PORT_GROUP5) { 23823 /* coverity[secure_coding] */ 23824 sal_strcpy(instance_string, 23825 d->block_info[blk].number ? "_y" : "_x"); 23826 } 23827 sal_snprintf(block_name, sizeof(block_name), "%s%s", 23828 soc_block_name_lookup_ext(d->block_info[blk].type, unit), 23829 instance_string); 23830 LOG_CLI((BSL_META_U(unit, 23831 "\tblk %d\t\t%-14s schan %d cmic %d\n"), 23832 blk, 23833 block_name, 23834 d->block_info[blk].schan, 23835 d->block_info[blk].cmic)); 23836 } 23837 bindex = -1; 23838 for (port = 0; ; port++) { 23839 for (i = 0; i < d->port_num_blktype; i++) { 23840 blk = d->port_info[port * d->port_num_blktype + i].blk; 23841 bindex = d->port_info[port * d->port_num_blktype + i].bindex; 23842 if(blk < 0) { 23843 break; 23844 } 23845 if (i == 0) { 23846 LOG_CLI((BSL_META_U(unit, 23847 "\tport %-3d\t"), 23848 soc_feature(unit, soc_feature_logical_port_num) ? 23849 si->port_p2l_mapping[port] : port)); 23850 } else { 23851 LOG_CLI((BSL_META_U(unit, 23852 "\t \t"))); 23853 } 23854 LOG_CLI((BSL_META_U(unit, 23855 "%s\tblk %d %s%d.%d\n"), 23856 soc_block_port_name_lookup_ext(d->block_info[blk].type, 23857 unit), 23858 blk, 23859 soc_block_name_lookup_ext(d->block_info[blk].type, unit), 23860 d->block_info[blk].number, 23861 bindex)); 23862 } 23863 if (bindex < 0) { /* end of list */ 23864 break; 23865 } 23866 } 23867 23868 soc_cm_get_id(unit, &dev_id, &rev_id); 23869 LOG_CLI((BSL_META_U(unit, 23870 "unit %d:\n"), unit)); 23871 LOG_CLI((BSL_META_U(unit, 23872 "\tpci\t\t\tdevice %04x rev %02x\n"), dev_id, rev_id)); 23873 #ifdef BCM_CMICM_SUPPORT 23874 LOG_CLI((BSL_META_U(unit, 23875 "\tcmc used by pci\t\tCMC%d\n"), SOC_PCI_CMC(unit))); 23876 #endif 23877 LOG_CLI((BSL_META_U(unit, 23878 "\tdriver\t\t\ttype %d (%s) group %d (%s)\n"), 23879 si->driver_type, SOC_CHIP_NAME(si->driver_type), 23880 si->driver_group, soc_chip_group_names[si->driver_group])); 23881 LOG_CLI((BSL_META_U(unit, 23882 "\tchip\t\t\t%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" 23883 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n"), 23884 SOC_IS_HERCULES15(unit) ? "hercules15 " : "", 23885 SOC_IS_FIREBOLT(unit) ? "firebolt " : "", 23886 SOC_IS_FIREBOLT2(unit) ? "firebolt2 " : "", 23887 SOC_IS_TRIUMPH3(unit) ? "triumph3 " : "", 23888 SOC_IS_HELIX4(unit) ? "helix4 " : "", 23889 SOC_IS_KATANA(unit) ? "katana " : "", 23890 SOC_IS_KATANA2(unit) ? "katana2 " : "", 23891 SOC_IS_HELIX1(unit) ? "helix " : "", 23892 SOC_IS_FELIX1(unit) ? "felix " : "", 23893 SOC_IS_HELIX15(unit) ? "helix15 " : "", 23894 SOC_IS_FELIX15(unit) ? "felix15 " : "", 23895 SOC_IS_RAPTOR(unit) ? "raptor " : "", 23896 SOC_IS_TRIUMPH(unit) ? "triumph " : "", 23897 SOC_IS_RAVEN(unit) ? "raven " : "", 23898 SOC_IS_HAWKEYE(unit) ? "hawkeye " : "", 23899 SOC_IS_SCORPION(unit) ? "scorpion " : "", 23900 SOC_IS_VALKYRIE(unit) ? "valkyrie " : "", 23901 SOC_IS_CONQUEROR(unit) ? "conqueror " : "", 23902 SOC_IS_TRIUMPH2(unit) ? "triumph2 " : "", 23903 SOC_IS_ENDURO(unit) ? "enduro " : "", 23904 SOC_IS_TRIDENT(unit) ? "trident " : "", 23905 SOC_IS_TITAN(unit) ? "titan " : "", 23906 SOC_IS_TRIDENT2(unit) ? "trident2 " : "", 23907 SOC_IS_TITAN2(unit) ? "titan2 " : "", 23908 SOC_IS_TRIDENT3(unit) ? "trident3 " : "", 23909 SOC_IS_HELIX5(unit) ? "helix5 " : "", 23910 SOC_IS_MAVERICK2(unit) ? "maverick2 " : "", 23911 SOC_IS_TOMAHAWK(unit) ? "tomahawk " : "", 23912 SOC_IS_TOMAHAWK2(unit) ? "tomahawk2 " : "", 23913 SOC_IS_TITAN2PLUS(unit) ? "titan2plus " : "", 23914 SOC_IS_TRIDENT2PLUS(unit) ? "trident2plus " : "", 23915 SOC_IS_XGS(unit) ? "xgs " : "", 23916 SOC_IS_XGS_FABRIC(unit) ? "xgs_fabric " : "", 23917 SOC_IS_XGS3_SWITCH(unit) ? "xgs3_switch " : "", 23918 SOC_IS_XGS_SWITCH(unit) ? "xgs_switch " : "")); 23919 23920 #define SOC_IS_SHOW(unit, a) \ 23921 if (a(unit)) { \ 23922 LOG_CLI((BSL_META_U(unit, \ 23923 "\t%s\n"), #a)); \ 23924 } 23925 23926 SOC_IS_SHOW(unit, SOC_IS_DRACO1) 23927 SOC_IS_SHOW(unit, SOC_IS_DRACO15) 23928 SOC_IS_SHOW(unit, SOC_IS_DRACO) 23929 SOC_IS_SHOW(unit, SOC_IS_HERCULES1) 23930 SOC_IS_SHOW(unit, SOC_IS_LYNX) 23931 SOC_IS_SHOW(unit, SOC_IS_TUCANA) 23932 SOC_IS_SHOW(unit, SOC_IS_XGS12_SWITCH) 23933 SOC_IS_SHOW(unit, SOC_IS_HERCULES15) 23934 SOC_IS_SHOW(unit, SOC_IS_HERCULES15) 23935 SOC_IS_SHOW(unit, SOC_IS_HERCULES) 23936 SOC_IS_SHOW(unit, SOC_IS_FIREBOLT) 23937 SOC_IS_SHOW(unit, SOC_IS_FB) 23938 SOC_IS_SHOW(unit, SOC_IS_FB_FX_HX) 23939 SOC_IS_SHOW(unit, SOC_IS_HB_GW) 23940 SOC_IS_SHOW(unit, SOC_IS_HBX) 23941 SOC_IS_SHOW(unit, SOC_IS_FBX) 23942 SOC_IS_SHOW(unit, SOC_IS_HURRICANE2) 23943 SOC_IS_SHOW(unit, SOC_IS_GREYHOUND) 23944 SOC_IS_SHOW(unit, SOC_IS_HELIX) 23945 SOC_IS_SHOW(unit, SOC_IS_HELIX1) 23946 SOC_IS_SHOW(unit, SOC_IS_HELIX15) 23947 SOC_IS_SHOW(unit, SOC_IS_FELIX) 23948 SOC_IS_SHOW(unit, SOC_IS_FELIX1) 23949 SOC_IS_SHOW(unit, SOC_IS_FELIX15) 23950 SOC_IS_SHOW(unit, SOC_IS_RAPTOR) 23951 SOC_IS_SHOW(unit, SOC_IS_RAVEN) 23952 SOC_IS_SHOW(unit, SOC_IS_HAWKEYE) 23953 SOC_IS_SHOW(unit, SOC_IS_FX_HX) 23954 SOC_IS_SHOW(unit, SOC_IS_GOLDWING) 23955 SOC_IS_SHOW(unit, SOC_IS_HUMV) 23956 SOC_IS_SHOW(unit, SOC_IS_BRADLEY) 23957 SOC_IS_SHOW(unit, SOC_IS_FIREBOLT2) 23958 SOC_IS_SHOW(unit, SOC_IS_TRIUMPH) 23959 SOC_IS_SHOW(unit, SOC_IS_ENDURO) 23960 SOC_IS_SHOW(unit, SOC_IS_HURRICANE) 23961 SOC_IS_SHOW(unit, SOC_IS_HURRICANEX) 23962 SOC_IS_SHOW(unit, SOC_IS_TR_VL) 23963 SOC_IS_SHOW(unit, SOC_IS_VALKYRIE) 23964 SOC_IS_SHOW(unit, SOC_IS_SCORPION) 23965 SOC_IS_SHOW(unit, SOC_IS_SC_CQ) 23966 SOC_IS_SHOW(unit, SOC_IS_CONQUEROR) 23967 SOC_IS_SHOW(unit, SOC_IS_TRIUMPH2) 23968 SOC_IS_SHOW(unit, SOC_IS_APOLLO) 23969 SOC_IS_SHOW(unit, SOC_IS_VALKYRIE2) 23970 SOC_IS_SHOW(unit, SOC_IS_TRIDENT) 23971 SOC_IS_SHOW(unit, SOC_IS_TITAN) 23972 SOC_IS_SHOW(unit, SOC_IS_TD_TT) 23973 SOC_IS_SHOW(unit, SOC_IS_SHADOW) 23974 SOC_IS_SHOW(unit, SOC_IS_TRIUMPH3) 23975 SOC_IS_SHOW(unit, SOC_IS_HELIX4) 23976 SOC_IS_SHOW(unit, SOC_IS_KATANA) 23977 SOC_IS_SHOW(unit, SOC_IS_KATANAX) 23978 SOC_IS_SHOW(unit, SOC_IS_KATANA2) 23979 SOC_IS_SHOW(unit, SOC_IS_TRIDENT2) 23980 SOC_IS_SHOW(unit, SOC_IS_TITAN2) 23981 SOC_IS_SHOW(unit, SOC_IS_TD2_TT2) 23982 SOC_IS_SHOW(unit, SOC_IS_TOMAHAWK) 23983 SOC_IS_SHOW(unit, SOC_IS_APACHE) 23984 SOC_IS_SHOW(unit, SOC_IS_TRIDENT3X) 23985 SOC_IS_SHOW(unit, SOC_IS_HELIX5) 23986 SOC_IS_SHOW(unit, SOC_IS_MAVERICK2) 23987 SOC_IS_SHOW(unit, SOC_IS_TRX) 23988 SOC_IS_SHOW(unit, SOC_IS_XGS) 23989 SOC_IS_SHOW(unit, SOC_IS_XGS_FABRIC) 23990 SOC_IS_SHOW(unit, SOC_IS_XGS_SWITCH) 23991 SOC_IS_SHOW(unit, SOC_IS_XGS12_FABRIC) 23992 SOC_IS_SHOW(unit, SOC_IS_XGS3_SWITCH) 23993 SOC_IS_SHOW(unit, SOC_IS_XGS3_FABRIC) 23994 SOC_IS_SHOW(unit, SOC_IS_ARAD) 23995 SOC_IS_SHOW(unit, SOC_IS_ARADPLUS) 23996 SOC_IS_SHOW(unit, SOC_IS_ARDON) 23997 SOC_IS_SHOW(unit, SOC_IS_ARAD_A0) 23998 SOC_IS_SHOW(unit, SOC_IS_ARAD_B0) 23999 SOC_IS_SHOW(unit, SOC_IS_ARAD_B1) 24000 SOC_IS_SHOW(unit, SOC_IS_ARADPLUS_A0) 24001 SOC_IS_SHOW(unit, SOC_IS_ARAD_B0_AND_ABOVE) 24002 SOC_IS_SHOW(unit, SOC_IS_ARAD_B1_AND_BELOW) 24003 SOC_IS_SHOW(unit, SOC_IS_ARADPLUS_AND_BELOW) 24004 SOC_IS_SHOW(unit, SOC_IS_ACP) 24005 SOC_IS_SHOW(unit, SOC_IS_QMX) 24006 SOC_IS_SHOW(unit, SOC_IS_JERICHO) 24007 SOC_IS_SHOW(unit, SOC_IS_QMX_A0) 24008 SOC_IS_SHOW(unit, SOC_IS_JERICHO_A0) 24009 SOC_IS_SHOW(unit, SOC_IS_FE1600_A0) 24010 SOC_IS_SHOW(unit, SOC_IS_FE1600_B0) 24011 SOC_IS_SHOW(unit, SOC_IS_FE1600_B0_AND_ABOVE) 24012 SOC_IS_SHOW(unit, SOC_IS_FE1600) 24013 SOC_IS_SHOW(unit, SOC_IS_FE3200) 24014 SOC_IS_SHOW(unit, SOC_IS_FE3200_A0) 24015 SOC_IS_SHOW(unit, SOC_IS_DFE_TYPE) 24016 SOC_IS_SHOW(unit, SOC_IS_FE1600_REDUCED) 24017 SOC_IS_SHOW(unit, SOC_IS_BCM88754_A0) 24018 SOC_IS_SHOW(unit, SOC_IS_RELOADING) 24019 24020 24021 LOG_CLI((BSL_META_U(unit, 24022 "\tmax modid\t\t%d\n"), si->modid_max)); 24023 LOG_CLI((BSL_META_U(unit, 24024 "\tnum ports\t\t%d\n"), si->port_num)); 24025 LOG_CLI((BSL_META_U(unit, 24026 "\tnum modids\t\t%d\n"), si->modid_count)); 24027 LOG_CLI((BSL_META_U(unit, 24028 "\tnum blocks\t\t%d\n"), si->block_num)); 24029 LOG_CLI((BSL_META_U(unit, 24030 "\tnum pipes\t\t%d\n"), si->num_pipe)); 24031 LOG_CLI((BSL_META_U(unit, 24032 "\tFE ports\t%d\t%s (%d:%d)\n"), 24033 si->fe.num, SOC_PBMP_FMT(si->fe.bitmap, pfmt), 24034 si->fe.min, si->fe.max)); 24035 LOG_CLI((BSL_META_U(unit, 24036 "\tGE ports\t%d\t%s (%d:%d)\n"), 24037 si->ge.num, SOC_PBMP_FMT(si->ge.bitmap, pfmt), 24038 si->ge.min, si->ge.max)); 24039 LOG_CLI((BSL_META_U(unit, 24040 "\tXE ports\t%d\t%s (%d:%d)\n"), 24041 si->xe.num, SOC_PBMP_FMT(si->xe.bitmap, pfmt), 24042 si->xe.min, si->xe.max)); 24043 LOG_CLI((BSL_META_U(unit, 24044 "\tCE ports\t%d\t%s (%d:%d)\n"), 24045 si->ce.num, SOC_PBMP_FMT(si->ce.bitmap, pfmt), 24046 si->ce.min, si->ce.max)); 24047 LOG_CLI((BSL_META_U(unit, 24048 "\tHG ports\t%d\t%s (%d:%d)\n"), 24049 si->hg.num, SOC_PBMP_FMT(si->hg.bitmap, pfmt), 24050 si->hg.min, si->hg.max)); 24051 LOG_CLI((BSL_META_U(unit, 24052 "\tST ports\t%d\t%s (%d:%d)\n"), 24053 si->st.num, SOC_PBMP_FMT(si->st.bitmap, pfmt), 24054 si->st.min, si->st.max)); 24055 LOG_CLI((BSL_META_U(unit, 24056 "\tETHER ports\t%d\t%s (%d:%d)\n"), 24057 si->ether.num, SOC_PBMP_FMT(si->ether.bitmap, pfmt), 24058 si->ether.min, si->ether.max)); 24059 LOG_CLI((BSL_META_U(unit, 24060 "\tPORT ports\t%d\t%s (%d:%d)\n"), 24061 si->port.num, SOC_PBMP_FMT(si->port.bitmap, pfmt), 24062 si->port.min, si->port.max)); 24063 LOG_CLI((BSL_META_U(unit, 24064 "\tALL ports\t%d\t%s (%d:%d)\n"), 24065 si->all.num, SOC_PBMP_FMT(si->all.bitmap, pfmt), 24066 si->all.min, si->all.max)); 24067 LOG_CLI((BSL_META_U(unit, 24068 "\tIPIC port\t%d\tblock %d\n"), 24069 si->ipic_port, si->ipic_block)); 24070 LOG_CLI((BSL_META_U(unit, 24071 "\tCMIC port\t%d\t%s block %d\n"), 24072 si->cmic_port, 24073 SOC_PBMP_FMT(si->cmic_bitmap, pfmt), si->cmic_block)); 24074 LOG_CLI((BSL_META_U(unit, 24075 "\tother blocks\t\tARL %d MMU %d MCU %d\n"), 24076 si->arl_block, si->mmu_block, si->mcu_block)); 24077 LOG_CLI((BSL_META_U(unit, 24078 "\t \t\tIPIPE %d IPIPE_HI %d EPIPE %d EPIPE_HI %d " 24079 "BSAFE %d ESM %d OTPC %d\n"), 24080 si->ipipe_block, si->ipipe_hi_block, 24081 si->epipe_block, si->epipe_hi_block, 24082 si->bsafe_block, si->esm_block, si->otpc_block[0])); 24083 24084 for (i = 0; i < COUNTOF(si->has_block); i++) { 24085 if (si->has_block[i]) { 24086 count++; 24087 } 24088 } 24089 LOG_CLI((BSL_META_U(unit, 24090 "\thas blocks\t%d\t"), count)); 24091 for (i = 0; i < COUNTOF(si->has_block); i++) { 24092 if (si->has_block[i]) { 24093 LOG_CLI((BSL_META_U(unit, 24094 "%s "), 24095 soc_block_name_lookup_ext(si->has_block[i], unit))); 24096 if ((i) && !(i%6)) { 24097 LOG_CLI((BSL_META_U(unit, 24098 "\n\t\t\t\t"))); 24099 } 24100 } 24101 } 24102 #if defined(BCM_KATANA2_SUPPORT) 24103 if (SOC_IS_KATANA2(unit) && !SOC_IS_SABER2(unit)) { 24104 READ_TOP_MISC_CONTROL_1r(unit,&top_misc_control_1_val); 24105 wc_xfi_mode_sel_val[0] = soc_reg_field_get( 24106 unit, TOP_MISC_CONTROL_1r, 24107 top_misc_control_1_val, 24108 wc_xfi_mode_sel_fld[0]); 24109 if (wc_xfi_mode_sel_val[0]) { 24110 LOG_CLI((BSL_META_U(unit, 24111 "\n========================================="))); 24112 LOG_CLI((BSL_META_U(unit, 24113 "\nATTN: KT2 Device's block MXQ8 in XFI MODE"))); 24114 LOG_CLI((BSL_META_U(unit, 24115 "\nPort 25 mapped to 32 and 36 mapped to 34"))); 24116 LOG_CLI((BSL_META_U(unit, 24117 "\n=========================================\n"))); 24118 } 24119 wc_xfi_mode_sel_val[1] = soc_reg_field_get( 24120 unit, TOP_MISC_CONTROL_1r, 24121 top_misc_control_1_val, 24122 wc_xfi_mode_sel_fld[1]); 24123 if (wc_xfi_mode_sel_val[1]) { 24124 LOG_CLI((BSL_META_U(unit, 24125 "\n========================================="))); 24126 LOG_CLI((BSL_META_U(unit, 24127 "\nATTN: KT2 Device's block MXQ9 in XFI MODE"))); 24128 LOG_CLI((BSL_META_U(unit, 24129 "\nPort 26 mapped to 29 and 39 mapped to 31"))); 24130 LOG_CLI((BSL_META_U(unit, 24131 "\n=========================================\n"))); 24132 } 24133 } 24134 #endif 24135 LOG_CLI((BSL_META_U(unit, 24136 "\n"))); 24137 LOG_CLI((BSL_META_U(unit, 24138 "\tport names\t\t"))); 24139 for (port = 0; port < si->port_num; port++) { 24140 if (port > 0 && (port % 5) == 0) { 24141 LOG_CLI((BSL_META_U(unit, 24142 "\n\t\t\t\t"))); 24143 } 24144 port1 = port; 24145 #if defined(BCM_KATANA2_SUPPORT) 24146 if (SOC_IS_KATANA2(unit)) { 24147 switch(port) { 24148 case 25: 24149 case 36: 24150 if (wc_xfi_mode_sel_val[0]) { 24151 port1 = (port == 25) ? 32 : 34; 24152 } 24153 break; 24154 case 26: 24155 case 39: 24156 if (wc_xfi_mode_sel_val[1]) { 24157 port1 = (port == 26) ? 29 : 31; 24158 } 24159 break; 24160 default: 24161 break; 24162 } 24163 } 24164 #endif 24165 LOG_CLI((BSL_META_U(unit, 24166 "%d=%s\t"), 24167 port1, si->port_name[port])); 24168 } 24169 LOG_CLI((BSL_META_U(unit, 24170 "\n"))); 24171 i = 0; 24172 for (blk = 0; SOC_BLOCK_INFO(unit, blk).type >= 0; blk++) { 24173 if (SOC_PBMP_IS_NULL(si->block_bitmap[blk])) { 24174 continue; 24175 } 24176 if (++i == 1) { 24177 LOG_CLI((BSL_META_U(unit, 24178 "\tblock bitmap\t"))); 24179 } else { 24180 LOG_CLI((BSL_META_U(unit, 24181 "\n\t\t\t"))); 24182 } 24183 LOG_CLI((BSL_META_U(unit, 24184 "%-2d %-14s %s (%d ports)"), 24185 blk, 24186 si->block_name[blk], 24187 SOC_PBMP_FMT(si->block_bitmap[blk], pfmt), 24188 si->block_valid[blk])); 24189 } 24190 if (i > 0) { 24191 LOG_CLI((BSL_META_U(unit, 24192 "\n"))); 24193 } 24194 24195 { 24196 soc_feature_t f; 24197 24198 LOG_CLI((BSL_META_U(unit, 24199 "\tfeatures\t"))); 24200 i = 0; 24201 for (f = 0; f < soc_feature_count; f++) { 24202 if (soc_feature(unit, f)) { 24203 if (++i > 3) { 24204 LOG_CLI((BSL_META_U(unit, 24205 "\n\t\t\t"))); 24206 i = 1; 24207 } 24208 LOG_CLI((BSL_META_U(unit, 24209 "%s "), soc_feature_name[f])); 24210 } 24211 } 24212 LOG_CLI((BSL_META_U(unit, 24213 "\n"))); 24214 } 24215 } 24216 24217 #endif /* BROADCOM_DEBUG */