openbcm

commit 5b6c697420e7ca7fc43c62d5cb8d943c6b0ae975
parent b140dd528a9bde60e2b7489d8c9a383c6cb4ab6f
Author: Broadcom SDK Release <sdk.releases@broadcom.com>
Date:   Wed, 15 Jan 2020 19:02:32 -0800

SDK-172319: Fixed synce divisor settings for blackhawk TSC core for various s...

Devices: 56980_A0
Module: syncE

Symptom:
TH3: synce configure on 2 lane 100G port is wrong

Fixed synce divisor settings for blackhawk TSC core for various speed
and interface modes

Diffstat:
M
sdk-6.5.16/src/bcm/esw/time.c
 | 
57
++++++++++++---------------------------------------------

1 file changed, 12 insertions(+), 45 deletions(-)
diff --git a/sdk-6.5.16/src/bcm/esw/time.c b/sdk-6.5.16/src/bcm/esw/time.c
@@ -90,6 +90,7 @@
 #include <soc/phy/phyctrl.h>
 #endif /* BCM_GREYHOUND2_SUPPORT */
 #ifdef PORTMOD_SUPPORT
+#include <soc/esw/portctrl.h>
 #include <soc/portmod/portmod.h>
 #include <soc/portmod/portmod_internal.h>
 #endif
@@ -9734,38 +9735,17 @@ _bcm_esw_time_synce_clock_source_frequency_get(int unit,
                         break;
                 }
             } else if (dispatch_type == phymodDispatchTypeTscbh) {
-                switch (port_speed) {
-                    case 10000:
-                    case 40000:
-                        /* 10G or 40G ports -  VCO 20.625 */
-                        if (sdm_divisor == 0x14a0) {
-                            *frequency = bcmTimeSyncE25MHz;
-                        } else {
-                            return BCM_E_PARAM;
-                        }
-                        break;
-                     case 20000:
-                     case 100000:
-                        /* 100G or 20G ports - VCO 25.78125*/
-                        if (sdm_divisor == 0x3390) {
-                            *frequency = bcmTimeSyncE25MHz;
-                        } else {
-                            return BCM_E_PARAM;
-                        }
-                        break;
-                     case 50000:
-                     case 400000:
-                        /* 100G or 20G ports - VCO 25.78125*/
-                        if (sdm_divisor == 0x3520) {
-                            *frequency = bcmTimeSyncE25MHz;
-                        } else {
-                            return BCM_E_PARAM;
-                        }
-                        break;
-                       default:
-                        return BCM_E_PARAM;
-                        break;
+#ifdef PORTMOD_SUPPORT
+                if (SOC_USE_PORTCTRL(unit)) {
+                    portmod_port_synce_clk_ctrl_t config;
+                    portmod_port_synce_clk_ctrl_t_init(unit, &config);
+
+                    SOC_IF_ERROR_RETURN(portmod_port_synce_clk_ctrl_get(unit, clk_src_config->port, &config));
+                    if ((config.stg0_mode == 0x2) && (config.stg1_mode == 0x0)) {
+                        *frequency = bcmTimeSyncE25MHz;
+                    }
                 }
+#endif
             } else if (dispatch_type == phymodDispatchTypeTsce_dpll) {
                 switch (port_speed) {
                     case 1000:
@@ -10517,20 +10497,7 @@ _bcm_esw_time_synce_clock_source_frequency_set(int unit,
                             div_in.stage0_sdm_frac  = 0x58;
                         }
                     } else if (dispatch_type == phymodDispatchTypeTscbh) {
-                        /* TSCBH ports */
-                        if (port_speed == 10000 || port_speed == 40000) {
-                            /* 10G or 40G ports -  VCO 20.625 */
-                            div_in.stage0_sdm_whole = 0x14;
-                            div_in.stage0_sdm_frac  = 0xa0;
-                        } else if (port_speed == 100000 || port_speed == 20000) {
-                            /* 100G or 20G or 400G ports - VCO 25.78125*/
-                            div_in.stage0_sdm_whole = 0x33;
-                            div_in.stage0_sdm_frac  = 0x90;
-                        } else if (port_speed == 50000 || port_speed == 400000){
-                            /* 50G port VCO 26.5625 */
-                            div_in.stage0_sdm_whole = 0x35;
-                            div_in.stage0_sdm_frac  = 0x20;
-                        }
+                        /* DO NOTHING: portmod API will program the proper settings for SDM mode. */
                     } else if (dispatch_type == phymodDispatchTypeTsce_dpll) {
                         if (port_speed == 1000 || port_speed == 10000 || port_speed == 40000 || port_speed == 20000) {
                             div_in.stage0_sdm_whole = 0x14;