linux-kernel-bde.c (156592B)
1 /* 2 * Copyright 2017 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License, version 2, as 6 * published by the Free Software Foundation (the "GPL"). 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License version 2 (GPLv2) for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * version 2 (GPLv2) along with this source code. 15 */ 16 17 /* 18 * Linux Kernel BDE 19 */ 20 21 #include <gmodule.h> 22 #include <linux-bde.h> 23 #include <linux_dma.h> 24 #include <mpool.h> 25 #include <linux/delay.h> 26 #include <linux/types.h> 27 #include <sdk_config.h> 28 #include <soc/devids.h> 29 #include <linux/version.h> 30 31 #include "linux_shbde.h" 32 33 #define MEMCPY memcpy 34 35 #ifdef CONFIG_X86_64 36 #if (defined(__GNUC__) && (__GNUC__ == 8)) 37 /* 38 * Prevent gcc 8.1.10 using a compiler inline memcpy even if using -fno-builtin or 39 * -fno-builtin-memcpy . 40 * __inline_memcpy and __memcpy are kernel functions that may be used instead, 41 * for either an inline or non-inline implementations of the function 42 */ 43 #undef MEMCPY 44 #define MEMCPY __memcpy 45 #endif /* (defined(__GNUC__) && (__GNUC__ == 8)) */ 46 #endif /* CONFIG_X86_64 */ 47 48 49 #if defined(CMIC_SOFT_BYTE_SWAP) 50 #define CMIC_SWAP32(_x) ((((_x) & 0xff000000) >> 24) \ 51 | (((_x) & 0x00ff0000) >> 8) \ 52 | (((_x) & 0x0000ff00) << 8) \ 53 | (((_x) & 0x000000ff) << 24)) 54 #endif /* defined(CMIC_SOFT_BYTE_SWAP) */ 55 56 #define PCI_USE_INT_NONE (-1) 57 #define PCI_USE_INT_INTX (0) 58 #define PCI_USE_INT_MSI (1) 59 #define PCI_USE_INT_MSIX (2) 60 #ifdef CONFIG_PCI_MSI 61 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,110)) 62 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 63 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) 64 #endif 65 #define msi_control_reg(base) (base + PCI_MSI_FLAGS) 66 #endif 67 #endif 68 MODULE_AUTHOR("Broadcom Corporation"); 69 MODULE_DESCRIPTION("Kernel BDE"); 70 MODULE_LICENSE("GPL"); 71 72 /* 73 * PCIe max payload size in bytes. 74 * The default value if not specified to the kernel module by maxpayload is historically 256. 75 * The default value may be changed using the BDE_PCIE_MAXPAYLOAD_DEFAULT macro. 76 */ 77 #ifndef BDE_PCIE_MAXPAYLOAD_DEFAULT 78 #define BDE_PCIE_MAXPAYLOAD_DEFAULT 256 79 #endif 80 int maxpayload = BDE_PCIE_MAXPAYLOAD_DEFAULT; 81 LKM_MOD_PARAM(maxpayload, "i", int, 0); 82 MODULE_PARM_DESC(maxpayload, 83 "Limit maximum payload size and request size on PCIe devices"); 84 85 /* Use MSI or MSIX interrupts */ 86 int usemsi = -1; 87 LKM_MOD_PARAM(usemsi, "i", int, 0); 88 MODULE_PARM_DESC(usemsi, 89 "Use MSI/ MSIX interrupts if supported by kernel"); 90 91 /* Ignore all recognized devices (for debug purposes) */ 92 int nodevices; 93 LKM_MOD_PARAM(nodevices, "i", int, 0); 94 MODULE_PARM_DESC(nodevices, 95 "Ignore all recognized devices (default no)"); 96 97 int msixcnt = 1; 98 99 /* 100 * This usually is defined at /usr/include/linux/pci_ids.h 101 * But this ID is newer. 102 */ 103 #ifndef PCI_DEVICE_ID_PLX_9656 104 #define PCI_DEVICE_ID_PLX_9656 0x9656 105 #endif 106 107 #ifndef PCI_DEVICE_ID_PLX_9056 108 #define PCI_DEVICE_ID_PLX_9056 0x9056 109 #endif 110 111 /* For 2.4.x kernel support */ 112 #ifndef IRQF_SHARED 113 #define IRQF_SHARED SA_SHIRQ 114 #endif 115 116 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 117 typedef unsigned long resource_size_t; 118 #endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) */ 119 120 #ifdef BCM_ICS 121 #define BCM_ICS_CMIC_BASE 0x08000000 122 #else 123 124 /* Force interrupt line */ 125 static int forceirq = -1; 126 static uint32_t forceirqubm = 0xffffffff; 127 LKM_MOD_PARAM(forceirq, "i", int, 0); 128 LKM_MOD_PARAM(forceirqubm, "i", uint, 0); 129 MODULE_PARM_DESC(forceirq, 130 "Override IRQ line assigned by boot loader"); 131 MODULE_PARM_DESC(forceirqubm, 132 "Bitmap for overriding the IRQ line assigned by boot loader for given units"); 133 134 /* Create SPI slave device (cannot be probed) */ 135 static uint32_t spi_devid = 0; 136 LKM_MOD_PARAM(spi_devid, "i", uint, 0); 137 MODULE_PARM_DESC(spi_devid, 138 "Create SPI slave device using this device ID"); 139 140 /* Select SPI device revision (cannot be probed) */ 141 static uint32_t spi_revid = 1; 142 LKM_MOD_PARAM(spi_revid, "i", uint, 0); 143 MODULE_PARM_DESC(spi_revid, 144 "Select device revision for SPI slave device"); 145 146 #endif /* BCM_ICS */ 147 148 /* Debug output */ 149 static int debug; 150 LKM_MOD_PARAM(debug, "i", int, 0); 151 MODULE_PARM_DESC(debug, 152 "Set debug level (default 0"); 153 /* Use high memory for DMA */ 154 155 /* module param for probing EB devices. */ 156 static char *eb_bus; 157 LKM_MOD_PARAM(eb_bus, "s", charp, 0); 158 MODULE_PARM_DESC(eb_bus, 159 "List of EB devices on platform. Input format (BA=%x IRQ=%d RD16=%d WR16=%d"); 160 161 #ifdef KEYSTONE 162 /* Force SPI Frequency */ 163 static int spifreq = 0; 164 LKM_MOD_PARAM(spifreq, "i", int, 0); 165 MODULE_PARM_DESC(spifreq, 166 "Force SPI Frequency for Keystone CPU (0 for default frequency)"); 167 #endif 168 169 170 /* Compatibility */ 171 #ifdef LKM_2_4 172 #define _ISR_RET void 173 #define _ISR_PARAMS(_i,_d,_r) int _i, void *_d, struct pt_regs *_r 174 #define IRQ_NONE 175 #define IRQ_HANDLED 176 #define SYNC_IRQ(_i) synchronize_irq() 177 #else /* LKM_2_6 */ 178 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) 179 #define _ISR_RET irqreturn_t 180 #else 181 #define _ISR_RET int 182 #endif 183 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) 184 #define _ISR_PARAMS(_i,_d,_r) int _i, void *_d 185 #else 186 #define _ISR_PARAMS(_i,_d,_r) int _i, void *_d, struct pt_regs *_r 187 typedef irqreturn_t (*irq_handler_t)(int _i, void *_d, struct pt_regs *_r); 188 #endif 189 #define SYNC_IRQ(_i) synchronize_irq(_i) 190 char * ___strtok; 191 char * strtok(char * s,const char * ct) 192 { 193 char *sbegin, *send; 194 sbegin = s ? s : ___strtok; 195 if (!sbegin) { 196 return NULL; 197 } 198 sbegin += strspn(sbegin,ct); 199 if (*sbegin == '\0') { 200 ___strtok = NULL; 201 return( NULL ); 202 } 203 send = strpbrk( sbegin, ct); 204 if (send && *send != '\0') 205 *send++ = '\0'; 206 ___strtok = send; 207 return (sbegin); 208 } 209 LKM_EXPORT_SYM(___strtok); 210 LKM_EXPORT_SYM(strtok); 211 #endif /* LKM_2_x */ 212 213 /* PCIe capabilities */ 214 #ifndef PCI_CAP_ID_EXP 215 #define PCI_CAP_ID_EXP 0x10 216 #endif 217 #ifndef PCI_EXP_DEVCAP 218 #define PCI_EXP_DEVCAP 4 219 #endif 220 #ifndef PCI_EXP_DEVCTL 221 #define PCI_EXP_DEVCTL 8 222 #endif 223 #ifndef PCI_EXT_CAP_START 224 #define PCI_EXT_CAP_START 0x100 225 #endif 226 #ifndef PCI_EXT_CAP_ID 227 #define PCI_EXT_CAP_ID(_hdr) (_hdr & 0x0000ffff) 228 #endif 229 #ifndef PCI_EXT_CAP_VER 230 #define PCI_EXT_CAP_VER(_hdr) ((_hdr >> 16) & 0xf) 231 #endif 232 #ifndef PCI_EXT_CAP_NEXT 233 #define PCI_EXT_CAP_NEXT(_hdr) ((_hdr >> 20) & 0xffc) 234 #endif 235 #ifndef PCI_EXT_CAP_ID_VNDR 236 #define PCI_EXT_CAP_ID_VNDR 0x0b 237 #endif 238 239 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 240 #define PCI_FIND_DEV(_d, _v, _fr) pci_find_device(_d, _v, _fr) 241 #else 242 #define PCI_FIND_DEV(_d, _v, _fr) pci_get_device(_d, _v, _fr) 243 #endif 244 245 #if defined(CONFIG_RESOURCES_64BIT) || defined(CONFIG_PHYS_ADDR_T_64BIT) 246 #define PHYS_ADDR_IS_64BIT 247 #endif 248 249 /* Structure of private SPI device */ 250 struct spi_dev { 251 uint8 cid; /* Chip ID */ 252 uint32 part; /* Part number of the chip */ 253 uint8 rev; /* Revision of the chip */ 254 void *robo; /* ptr to robo info required to access SPI */ 255 unsigned short phyid_high; /* PHYID HIGH in MII regs of detected chip */ 256 unsigned short phyid_low; /* PHYID LOW in MII regs of detected chip */ 257 }; 258 259 struct bde_spi_device_id { 260 unsigned short phyid_high; /* PHYID HIGH in MII regs of detected chip */ 261 unsigned short phyid_low; /* PHYID LOW in MII regs of detected chip */ 262 uint32 model_info; 263 uint32 rev_info; 264 uint32 spifreq; 265 }; 266 267 /* Maximum number of I/O windows supported per device. */ 268 #define BDE_NUM_IOWIN_MAX 3 269 270 /* I/O memory window definition. */ 271 struct memwin_s { 272 273 /* Physical address of I/O window. */ 274 resource_size_t addr; 275 276 /* Size of I/O window (in bytes). */ 277 resource_size_t size; 278 }; 279 280 /* Control Data */ 281 typedef struct bde_ctrl_s { 282 struct list_head list; 283 284 /* Specify the type of device, pci, spi, switch, ether ... */ 285 uint32 dev_type; 286 287 int domain_no; 288 int bus_no; 289 int be_pio; 290 int use_msi; 291 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 292 struct msix_entry *entries; 293 #endif 294 int msix_cnt; 295 union { 296 /* Linux PCI device pointer */ 297 struct pci_dev* _pci_dev; 298 299 /* SPI device pointer */ 300 struct spi_dev* _spi_dev; 301 } dev; 302 #define pci_device dev._pci_dev 303 #define spi_device dev._spi_dev 304 305 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 306 struct device *dma_dev; 307 #endif 308 309 struct memwin_s iowin[BDE_NUM_IOWIN_MAX]; 310 311 /* Secondary mapped base address */ 312 sal_vaddr_t alt_base_addr; 313 314 /* BDE device description */ 315 ibde_dev_t bde_dev; 316 317 /* Interrupt Handling */ 318 int iLine; /* Interrupt line */ 319 void (*isr)(void *); 320 void *isr_data; 321 322 /* 323 * Controls to allow two drivers to share a single set of 324 * hardware registers. Typically a kernel driver will handle 325 * a subset of hardware interrupts and a user mode driver 326 * will handle the remaining interrupts. 327 */ 328 void (*isr2)(void *); 329 void *isr2_data; 330 uint32_t fmask; /* Interrupts controlled by secondary handler */ 331 uint32_t imask; /* Enabled interrupts for primary handler */ 332 uint32_t imask2; /* Enabled interrupts for secondary handler */ 333 spinlock_t lock; /* Lock for IRQ mask synchronization */ 334 335 /* Hardware abstraction for shared BDE functions */ 336 shbde_hal_t shbde; 337 338 /* Device state : BDE_DEV_STATE_REMOVED/CHANGED */ 339 uint32 dev_state; 340 341 /* inst_id */ 342 uint32 inst_id; 343 } bde_ctrl_t; 344 345 static bde_ctrl_t _devices[LINUX_BDE_MAX_DEVICES]; 346 static int _ndevices = 0; 347 static int _switch_ndevices = 0; 348 static int _ether_ndevices = 0; 349 static int _cpu_ndevices = 0; 350 351 #define VALID_DEVICE(_n) ((_n >= 0) && (_n < _ndevices)) 352 353 #if defined(IPROC_CMICD) && defined(CONFIG_OF) 354 #define ICFG_CHIP_ID_REG 0x10236000 355 #define IHOST_CMICX_MAX_INTRS 129 356 static uint32 iproc_cmicx_irqs[IHOST_CMICX_MAX_INTRS]; 357 #endif 358 359 /* CPU MMIO area used with CPU cards provided on demo boards */ 360 #if defined(BCM_SAND_SUPPORT) && (defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__)) 361 static void *cpu_address = NULL; 362 #endif 363 364 365 /* Broadcom BCM4704 */ 366 #define BCM4704_VENDOR_ID 0x14E4 367 #define BCM4704_DEVICE_ID 0x4704 368 369 /* SiByte PCI Host */ 370 #define SIBYTE_PCI_VENDOR_ID 0x166D 371 #define SIBYTE_PCI_DEVICE_ID 0x0001 372 373 /* Intel 21150 PCI-PCI Bridge */ 374 #define DC21150_VENDOR_ID 0x1011 375 #define DC21150_DEVICE_ID 0x0022 376 377 /* HiNT HB4 PCI-PCI Bridge (21150 clone) */ 378 #define HINT_HB4_VENDOR_ID 0x3388 379 #define HINT_HB4_DEVICE_ID 0x0022 380 381 /* Pericom PI7C8150 PCI-PCI Bridge (21150 clone) */ 382 #define PI7C8150_VENDOR_ID 0x12D8 383 #define PI7C8150_DEVICE_ID 0x8150 384 385 /* Pericom PI7C9X130 PCI-PCIE Bridge */ 386 #define PCI_VNDID_PERICOM 0x12D8 387 #define PCI_DEVID_PI7C9X130 0xE130 388 #define DEV_CTRL_REG 0xb8 389 390 #define MAX_PAYLOAD_256B (1 << 5) 391 #define MAX_PAYLOAD_512B (2 << 5) 392 #define MAX_READ_REQ_256B (1 << 12) 393 394 395 /* Freescale 8548 PCI-E host Bridge */ 396 #define FSL_VENDOR_ID 0x1957 397 #define FSL8548PCIE_DEVICE_ID 0x0013 398 #define FSL2020EPCIE_DEVICE_ID 0x0070 399 #define FSL8548PCIE_DEV_CTRL_REG 0x54 400 401 /* 4716 PCI-E host Bridge */ 402 #define BCM4716_VENDOR_ID 0x14e4 403 #define BCM4716PCIE_DEVICE_ID 0x4716 404 #define BCM4716PCIE_DEV_CAP_REG 0xd4 405 #define BCM4716PCIE_DEV_CTRL_REG 0xd8 406 #define BCM53000_VENDOR_ID 0x14e4 407 #define BCM53000PCIE_DEVICE_ID 0x5300 408 409 #define BCM53000PCIE_DEV(port) ((port == 0) ? pcie0 : pcie1) 410 #define BCM53000PCIE_BASE(port) ((port == 0) ? 0xb8005000 : 0xb800e000) 411 #define BCM53000PCIE_FUNC0_COFIG_SPACE 0x400 412 #define BCM53000PCIE_SROM_SPACE 0x800 413 #define BCM53000PCIE_DEV_CAP_REG 0xd4 414 #define BCM53000PCIE_DEV_CTRL_REG 0xd8 415 #define BCM53000PCIE_MAX_PAYLOAD_MASK 0x7 416 #define BCM53000PCIE_CAP_MAX_PAYLOAD_256B (1 << 0) 417 #define BCM53000PCIE_DEFAULT_STATUS 0x00100146 418 419 /* 16bit wide register. offset 14, 14*2 = 0x1c */ 420 #define BCM53000PCIE_SPROM_OFFSET 0x1c 421 /* bit 15:13 spromData.MaxPayloadSize. 1: 256 bytes */ 422 #define BCM53000PCIE_SPROM_MAX_PAYLOAD_MASK 0xe000 423 #define BCM53000PCIE_SPROM_MAX_PAYLOAD_256B (1 << 13) 424 425 426 /* Intel 21150, HiNT HB4 and other 21150-compatible */ 427 #define PCI_CFG_DEC21150_SEC_CLK 0x68 428 429 #define BCM4704_ENUM_BASE 0x18000000 430 #define BCM4704_MEMC_BASE (BCM4704_ENUM_BASE+0x8000) 431 #define BCM4704_MEMC_PRIORINV 0x18 432 433 /* PLX PCI-E Switch */ 434 #define PLX_PEX8608_DEV_ID 0x8608 435 #define PLX_PEX8617_DEV_ID 0x8617 436 #define PLX_PEX86XX_DEV_CTRL_REG 0x70 437 438 /* Broadcom BCM58525 */ 439 #define BCM58525_PCI_VENDOR_ID 0x14E4 440 #define BCM58525_PCI_DEVICE_ID 0x8025 441 #define BCM58522_PCI_DEVICE_ID 0x8022 442 443 /* Broadcom BCM58712 */ 444 #define BCM58712_PCI_VENDOR_ID 0x14E4 445 #define BCM58712_PCI_DEVICE_ID 0x168E 446 447 /* Default gicd address if not available in DTB */ 448 #define IHOST_GICD_REG_ADDR 0x10781100 449 #define IHOST_GICD_REG_REMAP_LEN 0x100 450 451 #define IHOST_GICD_REG_ADDR_VALID(d, addr) \ 452 (_devices[d].bde_dev.base_address1 && \ 453 (addr & 0xFFFFFF00) == _devices[d].iowin[1].addr) 454 455 #define IHOST_GICD_REG_ADDR_REMAP(d, addr) \ 456 (void *)(_devices[d].bde_dev.base_address1 + \ 457 (addr - ((sal_vaddr_t)_devices[d].iowin[1].addr))) 458 459 static uint32_t _read(int d, uint32_t addr); 460 461 #ifdef BCM_ICS 462 #else 463 /* Used to determine overall memory limits across all devices */ 464 static uint32_t _pci_mem_start = 0xFFFFFFFF; 465 static uint32_t _pci_mem_end = 0; 466 467 /* Used to control MSI interrupts */ 468 static int use_msi = 0; 469 #endif 470 471 #ifdef BCM_PLX9656_LOCAL_BUS 472 473 #define CPLD_OFFSET 0x00800000 474 #define CPLD_REVISION_REG 0x0000 475 #define CPLD_REVISION_MASK 0xffff 476 #define CPLD_RESET_REG 0x0004 477 #define CPLD_RESET_NONE 0x0000 478 479 #define PL0_OFFSET 0x00800000 480 #define PL0_SIZE 0x00040000 481 #define PL0_REVISION_REG 0x0000 482 483 /* Assume there's only one PLX PCI-to-Local bus bridge if any */ 484 static bde_ctrl_t plx_ctrl; 485 static int num_plx = 0; 486 487 #endif /* BCM_PLX9656_LOCAL_BUS */ 488 489 static spinlock_t bus_lock; 490 491 static int 492 _parse_eb_args(char *str, char * format, ...) 493 __attribute__ ((format (scanf, 2, 3))); 494 495 static int 496 _parse_eb_args(char *str, char * format, ...) 497 { 498 va_list args; 499 500 va_start(args, format); 501 vsscanf(str, format, args); 502 va_end(args); 503 504 return 0; 505 } 506 507 static void 508 _bde_add_device(void) 509 { 510 int add_switch_device = 0; 511 if (_devices[_ndevices].dev_type & BDE_SWITCH_DEV_TYPE) { 512 _switch_ndevices++; 513 add_switch_device = 1; 514 } else if (_devices[_ndevices].dev_type & BDE_ETHER_DEV_TYPE) { 515 _ether_ndevices++; 516 } else if (_devices[_ndevices].dev_type & BDE_CPU_DEV_TYPE) { 517 _cpu_ndevices++; 518 } else { 519 return; 520 } 521 _ndevices++; 522 523 /* 524 * In order to be backward compatible with the user mode BDE 525 * (specifically the interrupt IOCTLs) and the CM, switch devices 526 * *must* come first. If this is not the case (due to the probing 527 * order), we let the non-switch device(s) drop down to the end of 528 * the device array. 529 */ 530 if (add_switch_device) { 531 bde_ctrl_t tmp_dev; 532 int i, s = 0; 533 534 while (s < _switch_ndevices) { 535 if (_devices[s].dev_type & BDE_SWITCH_DEV_TYPE) { 536 s++; 537 continue; 538 } 539 tmp_dev = _devices[s]; 540 for (i = s; i < _ndevices - 1; i++) { 541 _devices[i] = _devices[i+1]; 542 } 543 _devices[i] = tmp_dev; 544 } 545 546 _dma_init(_switch_ndevices-1); 547 } 548 549 /* Initialize device locks */ 550 spin_lock_init(&_devices[_ndevices-1].lock); 551 } 552 553 static int 554 _eb_device_create(resource_size_t paddr, int irq, int rd_hw, int wr_hw) 555 { 556 bde_ctrl_t *ctrl; 557 uint32 dev_rev_id = 0x0, dev_id; 558 559 dev_id = _ndevices; 560 561 ctrl = _devices + _ndevices; 562 563 ctrl->dev_type |= BDE_EB_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 564 ctrl->pci_device = NULL; /* No PCI bus */ 565 566 if(rd_hw) { 567 ctrl->dev_type |= BDE_DEV_BUS_RD_16BIT; 568 } 569 570 if (wr_hw) { 571 ctrl->dev_type |= BDE_DEV_BUS_WR_16BIT; 572 } 573 574 /* Map in the device */ 575 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(paddr, 0x10000); 576 ctrl->iowin[0].addr = paddr; 577 ctrl->iowin[0].size = 0x10000; 578 579 dev_rev_id = _read(dev_id, 0x178); /* CMIC_DEV_REV_ID */ 580 581 ctrl->bde_dev.device = dev_rev_id & 0xFFFF; 582 ctrl->bde_dev.rev = (dev_rev_id >> 16) & 0xFF; 583 584 ctrl->iLine = irq; 585 ctrl->isr = NULL; 586 ctrl->isr_data = NULL; 587 588 gprintk("Created EB device at BA=%x IRQ=%d RD16=%d WR16=%d device=0x%x\n", 589 (unsigned int)paddr, irq, rd_hw, wr_hw, ctrl->bde_dev.device); 590 591 _bde_add_device(); 592 593 return 0; 594 } 595 596 #ifdef BCM_SAND_SUPPORT 597 598 #include <soc/devids.h> 599 600 static int 601 sand_device_create(void) 602 { 603 bde_ctrl_t* ctrl; 604 605 ctrl = _devices; /* FIX_ME: on petra, take first device */ 606 607 #ifndef __DUNE_LINUX_BCM_CPU_PCIE__ 608 ctrl->dev_type |= BDE_PCI_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 609 ctrl->pci_device = NULL; /* No PCI bus */ 610 611 /* Map in the device */ /* FIX_ME: not realy map anything */ 612 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(0x40000000, 0x100000); 613 ctrl->iowin[0].addr = 0x40000000; 614 ctrl->iowin[0].size = 0x100000; 615 616 ctrl->iLine = 0; 617 ctrl->isr = NULL; 618 ctrl->isr_data = NULL; 619 620 ctrl->bde_dev.device = BCM88950_DEVICE_ID; 621 ctrl->bde_dev.rev = BCM88950_A0_REV_ID; 622 #endif 623 624 /* Map CPU regs */ 625 #ifdef __DUNE_WRX_BCM_CPU__ 626 cpu_address = IOREMAP(0x18000000, 0x4000000); 627 #elif defined(__DUNE_GTO_BCM_CPU__) 628 cpu_address = IOREMAP(0xe0000000, 0x100000); 629 #endif 630 631 if ((ctrl->bde_dev.device == PCP_PCI_DEVICE_ID)) { 632 ctrl->bde_dev.device = GEDI_DEVICE_ID; 633 ctrl->bde_dev.rev = GEDI_REV_ID; 634 } 635 636 if ((ctrl->bde_dev.device == ACP_PCI_DEVICE_ID)) { 637 ctrl->dev_type |= BDE_PCI_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 638 } 639 640 #ifndef __DUNE_LINUX_BCM_CPU_PCIE__ 641 _bde_add_device(); 642 #endif 643 644 return 0; 645 } 646 #endif /* BCM_SAND_SUPPORT */ 647 648 #ifdef IPROC_CMICD 649 static void 650 iproc_cmicd_get_irqres(ibde_dev_t bde_dev, struct resource *res_irq) 651 { 652 shbde_iproc_config_t iproc_config, *icfg = &iproc_config; 653 654 /* iProc configuration parameters */ 655 memset(icfg, 0, sizeof(*icfg)); 656 shbde_iproc_config_init(icfg, bde_dev.device, bde_dev.rev); 657 658 if ((icfg->iproc_ver == 0) && (debug >= 1)) { 659 gprintk("Unable to determine iProc version\n"); 660 } 661 662 if (icfg->iproc_ver == 7) { 663 res_irq->start = 221; 664 } else if (icfg->iproc_ver == 10) { 665 res_irq->start = 184; 666 } 667 668 } 669 670 #include <linux/platform_device.h> 671 #include <linux/of.h> 672 673 extern int iproc_platform_driver_register(struct platform_driver *drv); 674 extern void iproc_platform_driver_unregister(struct platform_driver *drv); 675 extern int iproc_platform_device_register(struct platform_device *drv); 676 extern void iproc_platform_device_unregister(struct platform_device *drv); 677 678 extern struct resource * 679 iproc_platform_get_resource(struct platform_device *dev, unsigned int type, 680 unsigned int num); 681 682 #define IPROC_CHIPCOMMONA_BASE 0x18000000 683 #define IPROC_CMICD_BASE 0x48000000 684 #define IPROC_CMICD_SIZE 0x40000 685 #define IPROC_CMICD_INT 194 686 687 #define IPROC_CMICD_COMPATIBLE "brcm,iproc-cmicd" 688 #define IPROC_CMICX_COMPATIBLE "brcm,iproc-cmicx" 689 690 static int 691 iproc_cmicd_probe(struct platform_device *pldev) 692 { 693 bde_ctrl_t *ctrl; 694 uint32 size, dev_rev_id; 695 struct resource *memres, *irqres; 696 #ifdef CONFIG_OF 697 if (debug >= 1) { 698 gprintk("iproc_cmicd_probe %s\n", pldev->dev.of_node ? "with device node":""); 699 } 700 #endif 701 memres = iproc_platform_get_resource(pldev, IORESOURCE_MEM, 0); 702 if (memres == NULL) { 703 gprintk("Unable to retrieve iProc CMIC resources"); 704 return -1; 705 } 706 size = memres->end - memres->start + 1; 707 708 ctrl = _devices + _ndevices; 709 710 ctrl->dev_type = BDE_AXI_DEV_TYPE | BDE_SWITCH_DEV_TYPE | BDE_256K_REG_SPACE; 711 ctrl->pci_device = NULL; /* No PCI bus */ 712 713 /* Map CMIC block in the AXI memory space into CPU address space */ 714 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(memres->start, size); 715 if (!ctrl->bde_dev.base_address) { 716 gprintk("Error mapping iProc CMIC registers"); 717 return -1; 718 } 719 ctrl->iowin[0].addr = memres->start; 720 ctrl->iowin[0].size = size; 721 722 #ifdef CONFIG_OF 723 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 724 uint32 *icfg_chip_id; 725 icfg_chip_id = (uint32 *)IOREMAP(ICFG_CHIP_ID_REG, 2 * sizeof(uint32)); 726 if (icfg_chip_id == NULL) { 727 gprintk("Error mapping ICFG_CHIP_ID_REG\n"); 728 return -1; 729 } 730 ctrl->bde_dev.device = readl(icfg_chip_id) & 0xffff; 731 ctrl->bde_dev.rev = readl(icfg_chip_id+1) & 0xff; 732 iounmap(icfg_chip_id); 733 /* Map GICD block in the AXI memory space into CPU address space */ 734 memres = iproc_platform_get_resource(pldev, IORESOURCE_MEM, 1); 735 if (memres) { 736 ctrl->bde_dev.base_address1 = (sal_vaddr_t)IOREMAP(memres->start, memres->end - memres->start + 1); 737 ctrl->iowin[1].addr = memres->start; 738 ctrl->iowin[1].size = memres->end - memres->start + 1; 739 } else { 740 /* Use default address if not available in DTB */ 741 ctrl->bde_dev.base_address1 = (sal_vaddr_t)IOREMAP(IHOST_GICD_REG_ADDR, IHOST_GICD_REG_REMAP_LEN); 742 ctrl->iowin[1].addr = IHOST_GICD_REG_ADDR; 743 ctrl->iowin[1].size = IHOST_GICD_REG_REMAP_LEN; 744 } 745 if (ctrl->bde_dev.base_address1) { 746 if (debug >= 1) { 747 gprintk("base_address1:0x%lx phys_address1:0x%lx\n", 748 (unsigned long)ctrl->bde_dev.base_address1, (unsigned long)ctrl->iowin[1].addr); 749 } 750 } else { 751 gprintk("Error mapping ihost GICD registers\n"); 752 } 753 } else 754 #endif 755 { 756 /* Read switch device ID from CMIC */ 757 dev_rev_id = *((uint32 *)(ctrl->bde_dev.base_address + 0x10224)); 758 #if defined(BCM_CMICM_SUPPORT) && defined(BE_HOST) 759 ctrl->bde_dev.device = ( (((dev_rev_id >> 16) & 0xff) << 8) | 760 ((dev_rev_id >> 24) & 0xff)); 761 ctrl->bde_dev.rev = (dev_rev_id >> 8) & 0xff ; 762 #else 763 ctrl->bde_dev.device = dev_rev_id & 0xffff; 764 ctrl->bde_dev.rev = (dev_rev_id >> 16) & 0xff; 765 #endif 766 ctrl->bde_dev.base_address1 = 0; 767 } 768 769 #ifdef CONFIG_OF 770 if (!pldev->dev.of_node) 771 #endif 772 { 773 /* Assign locally if not available from device node */ 774 iproc_cmicd_get_irqres(ctrl->bde_dev, &pldev->resource[0]); 775 } 776 777 #ifdef CONFIG_OF 778 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 779 int i; 780 memset(iproc_cmicx_irqs, 0, IHOST_CMICX_MAX_INTRS*sizeof(uint32_t)); 781 for (i = 0; i < IHOST_CMICX_MAX_INTRS; i++) { 782 irqres = iproc_platform_get_resource(pldev, IORESOURCE_IRQ, i); 783 if (irqres) { 784 iproc_cmicx_irqs[i] = irqres->start; 785 } 786 if (debug >= 1) { 787 gprintk("iproc_cmicx_irqs[%d] = %d\n", i, iproc_cmicx_irqs[i]); 788 } 789 } 790 ctrl->iLine = iproc_cmicx_irqs[0]; 791 } else 792 #endif 793 { 794 irqres = iproc_platform_get_resource(pldev, IORESOURCE_IRQ, 0); 795 ctrl->iLine = irqres->start; 796 } 797 798 ctrl->isr = NULL; 799 ctrl ->isr_data = NULL; 800 801 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 802 ctrl->dma_dev = &pldev->dev; 803 #endif 804 805 /* Let's boogie */ 806 _bde_add_device(); 807 return 0; 808 } 809 810 static int 811 iproc_cmicd_remove(struct platform_device *pldev) 812 { 813 return 0; 814 } 815 #ifdef CONFIG_OF 816 static const struct of_device_id iproc_cmicd_of_match[] = { 817 { .compatible = IPROC_CMICD_COMPATIBLE }, 818 { .compatible = IPROC_CMICX_COMPATIBLE }, 819 {}, 820 }; 821 MODULE_DEVICE_TABLE(of, iproc_cmicd_of_match); 822 #endif 823 static char iproc_cmicd_string[] = "bcmiproc-cmicd"; 824 825 static struct platform_driver iproc_cmicd_driver = 826 { 827 .probe = iproc_cmicd_probe, 828 .remove = iproc_cmicd_remove, 829 .driver = 830 { 831 .name = iproc_cmicd_string, 832 .owner = THIS_MODULE, 833 #ifdef CONFIG_OF 834 .of_match_table = iproc_cmicd_of_match, 835 #endif 836 }, 837 }; 838 839 typedef enum { 840 IPROC_CMICD_RES_INTR = 0, 841 IPROC_CMICD_RES_MEM 842 } IPROC_CMICD_RES_E; 843 844 static struct resource iproc_cmicd_resources[] = { 845 [IPROC_CMICD_RES_INTR] = { 846 .flags = IORESOURCE_IRQ, 847 .start = IPROC_CMICD_INT, 848 }, 849 [IPROC_CMICD_RES_MEM] = { 850 .flags = IORESOURCE_MEM, 851 .start = IPROC_CMICD_BASE, 852 .end = IPROC_CMICD_BASE+IPROC_CMICD_SIZE-1, 853 }, 854 }; 855 856 static void 857 iproc_cmicd_release(struct device *dev) 858 { 859 } 860 861 static u64 iproc_cmicd_dmamask = DMA_BIT_MASK(32); 862 863 static struct platform_device iproc_cmicd_pdev = { 864 .name = iproc_cmicd_string, 865 .id = 0, 866 .dev = { 867 .release = iproc_cmicd_release, 868 .init_name = iproc_cmicd_string, 869 .dma_mask = &iproc_cmicd_dmamask, 870 .coherent_dma_mask = DMA_BIT_MASK(32), 871 }, 872 .resource = iproc_cmicd_resources, 873 .num_resources = ARRAY_SIZE(iproc_cmicd_resources), 874 }; 875 876 static int 877 iproc_has_cmicd(void) 878 { 879 void *iproc_cca_base; 880 uint32 cca_cid; 881 882 /* Read ChipcommonA chip id register to identify current SOC */ 883 iproc_cca_base = IOREMAP(IPROC_CHIPCOMMONA_BASE, 0x3000); 884 if (iproc_cca_base == NULL) { 885 gprintk("iproc_has_cmicd: ioremap of ChipcommonA registers failed"); 886 return 0; 887 } 888 cca_cid = readl((uint32 *)iproc_cca_base); 889 cca_cid &= 0xffff; 890 iounmap(iproc_cca_base); 891 892 /* Only allowed accessing CMICD module if the SOC has it */ 893 switch (cca_cid) { 894 default: 895 break; 896 } 897 898 /* Device has CMIC */ 899 return 1; 900 } 901 902 #define IPROC_CHIPCOMMONA_EROM_PTR_OFFSET (0x180000fc) 903 #define EROM_MAX_SIZE (0x1000) 904 #define EROM_PARTNUM_CMICD (0x14) 905 906 #define EROM_DESC_COMPIDENT (0x1) 907 #define EROM_DESC_MASTER (0x3) 908 #define EROM_DESC_ADDR (0x5) 909 #define EROM_DESC_END (0xF) 910 #define EROM_DESC_EMPTY (0) 911 912 #define EROM_IS_DESC_COMPIDENT(x) ((x & 0x7) == EROM_DESC_COMPIDENT) 913 #define EROM_IS_DESC_MASTER(x) ((x & 0x7) == EROM_DESC_MASTER) 914 #define EROM_IS_DESC_ADDR(x) ((x & 0x7) == EROM_DESC_ADDR) 915 #define EROM_IS_DESC_END(x) ((x & 0xF) == EROM_DESC_END) 916 917 #define EROM_GET_PARTNUM(x) ((x >> 8) & (0xFFF)) /* Bit 8~19 */ 918 #define EROM_GET_ADDRESS(x) ((x >> 12) & (0xFFFFF)) /* Bit 12~31 */ 919 #define EROM_GET_SIZETYPE(x) ((x >> 4) & (0x3)) /* Bit 4~5 */ 920 #define EROM_GET_AG32(x) ((x >> 3) & (0x1)) /* Bit 3 */ 921 #define EROM_GET_SIZE(x) ((x >> 12) & (0xFFFFF)) /* Bit 12~31 */ 922 #define EROM_GET_SG32(x) ((x >> 3) & (0x1)) /* Bit 3 */ 923 924 #define EROM_ADDR_SIZETYPE_4K (0) 925 #define EROM_ADDR_SIZETYPE_8K (1) 926 #define EROM_ADDR_SIZETYPE_16K (2) 927 #define EROM_ADDR_SIZETYPE_MORE (3) 928 929 #define EROM_ADDR_FLAG_AG32 (1) /* Address space greater than 32 bit */ 930 #define EROM_ADDR_FLAG_SIZE (2) /* Addition size descriptor */ 931 #define EROM_ADDR_FLAG_SG32 (4) /* Size descriptor greater than 32 bit */ 932 933 static void 934 iproc_cmicd_get_memregion(struct resource *res_mem) 935 { 936 void *erom_ptr_oft; 937 uint32_t erom_phy_addr; 938 uint32_t *erom_base; 939 uint32_t i = 0; 940 uint32_t word = 0; 941 uint8_t more_addr_word = 0; /* bit 0: AG32; bit 1: SIZE; bit 2: SG32 */ 942 uint8_t found_cmicd_dev = 0; 943 uint8_t size_type = 0; 944 bool is_compident_a = 1; /* 1: CompidentA; o/w: CompidentB */ 945 946 erom_ptr_oft = IOREMAP(IPROC_CHIPCOMMONA_EROM_PTR_OFFSET, 0x100); 947 948 erom_phy_addr = readl((uint32 *)(erom_ptr_oft)); 949 iounmap(erom_ptr_oft); 950 951 erom_base = IOREMAP(erom_phy_addr, EROM_MAX_SIZE); 952 953 while (1) { 954 word = readl((uint32 *)(erom_base + i)); 955 956 if (EROM_IS_DESC_ADDR(word) || more_addr_word) { 957 if (more_addr_word == 0) { /* Normal Addr Desc */ 958 if (EROM_GET_AG32(word) == 1) { 959 more_addr_word |= EROM_ADDR_FLAG_AG32; 960 } 961 962 size_type = EROM_GET_SIZETYPE(word); 963 if (size_type == EROM_ADDR_SIZETYPE_MORE) { 964 more_addr_word |= EROM_ADDR_FLAG_SIZE; 965 } 966 967 if (found_cmicd_dev == 1) { 968 res_mem->start = EROM_GET_ADDRESS(word) << 12; 969 if (size_type < EROM_ADDR_SIZETYPE_MORE) { 970 res_mem->end = res_mem->start + 4096 * (1 << size_type) - 1; 971 } 972 } 973 } 974 else if (more_addr_word & EROM_ADDR_FLAG_AG32) { /* UpperAddr Desc */ 975 more_addr_word &= ~EROM_ADDR_FLAG_AG32; 976 977 if (found_cmicd_dev == 1) { 978 /* res_mem->start |= word << 32; */ 979 gprintk("Expect cmicd address to be 32-bit\n"); 980 } 981 } 982 else if (more_addr_word & EROM_ADDR_FLAG_SIZE) { /* Size Desc */ 983 if (EROM_GET_SG32(word) == 1) { 984 more_addr_word |= EROM_ADDR_FLAG_SG32; 985 } 986 987 more_addr_word &= ~EROM_ADDR_FLAG_SIZE; 988 989 if (found_cmicd_dev == 1) { 990 res_mem->end = res_mem->start + (EROM_GET_SIZE(word) << 12) - 1; 991 } 992 } 993 else if (more_addr_word & EROM_ADDR_FLAG_SG32) { /* UpperSize Desc */ 994 more_addr_word &= ~EROM_ADDR_FLAG_SG32; 995 996 if (found_cmicd_dev == 1) { 997 /* res_mem->end += (word) << 32; */ 998 gprintk("Expect cmicd size to be 32-bit\n"); 999 } 1000 } 1001 1002 if (found_cmicd_dev == 1 && more_addr_word == 0) { 1003 break; /* We have gotten all necessary information, exit the loop */ 1004 } 1005 } 1006 else if (EROM_IS_DESC_COMPIDENT(word)) { 1007 if (is_compident_a == 1) { 1008 if (EROM_GET_PARTNUM(word) == EROM_PARTNUM_CMICD) { 1009 found_cmicd_dev = 1; 1010 } 1011 } 1012 1013 is_compident_a = 1 - is_compident_a; 1014 } 1015 else if (EROM_IS_DESC_END(word)) { 1016 break; 1017 } 1018 1019 i++; 1020 } 1021 iounmap(erom_base); 1022 1023 if (debug >= 1) { 1024 gprintk("CMICD info by %s: cmicd_mem.start=%lx, cmicd_mem.end=%lx\n", 1025 found_cmicd_dev ? "EROM" : "Default", 1026 (unsigned long)iproc_cmicd_resources[IPROC_CMICD_RES_MEM].start, 1027 (unsigned long)iproc_cmicd_resources[IPROC_CMICD_RES_MEM].end); 1028 } 1029 } 1030 #endif /* IPROC_CMICD */ 1031 1032 #ifdef BCM_ICS 1033 static int 1034 _ics_bde_create(void) 1035 { 1036 bde_ctrl_t *ctrl; 1037 uint32 dev_rev_id = 0x0; 1038 resource_size_t paddr; 1039 1040 if (_ndevices == 0) { 1041 ctrl = _devices + _ndevices; 1042 1043 ctrl->dev_type |= BDE_ICS_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 1044 ctrl->pci_device = NULL; /* No PCI bus */ 1045 1046 /* Map in the device */ 1047 paddr = BCM_ICS_CMIC_BASE; 1048 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(paddr, 0x10000); 1049 ctrl->iowin[0].addr = paddr; 1050 ctrl->iowin[0].size = 0x10000; 1051 1052 dev_rev_id = *((unsigned int *)(KSEG1ADDR(paddr + 0x178))); 1053 1054 ctrl->bde_dev.device = dev_rev_id & 0xFFFF; 1055 ctrl->bde_dev.rev = (dev_rev_id >> 16) & 0xFF; 1056 1057 ctrl->iLine = 5; /* From raptor linux BSP */ 1058 1059 ctrl->isr = NULL; 1060 ctrl->isr_data = NULL; 1061 printk("Created ICS device ..%x\n", ctrl->bde_dev.base_address); 1062 _bde_add_device(); 1063 } 1064 1065 return 0; 1066 } 1067 1068 #else /* !BCM_ICS */ 1069 1070 extern struct pci_bus *pci_find_bus(int domain, int busnr); 1071 1072 /* 1073 * PCI device table. 1074 * Populated from the include/soc/devids.h file. 1075 */ 1076 1077 static const struct pci_device_id _id_table[] = { 1078 { BROADCOM_VENDOR_ID, BCM5675_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1079 { BROADCOM_VENDOR_ID, BCM5676_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1080 { BROADCOM_VENDOR_ID, BCM56218X_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1081 { BROADCOM_VENDOR_ID, BCM56218_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1082 { BROADCOM_VENDOR_ID, BCM56219_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1083 { BROADCOM_VENDOR_ID, BCM56218R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1084 { BROADCOM_VENDOR_ID, BCM56219R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1085 { BROADCOM_VENDOR_ID, BCM56214_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1086 { BROADCOM_VENDOR_ID, BCM56215_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1087 { BROADCOM_VENDOR_ID, BCM56214R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1088 { BROADCOM_VENDOR_ID, BCM56215R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1089 { BROADCOM_VENDOR_ID, BCM56216_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1090 { BROADCOM_VENDOR_ID, BCM56217_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1091 { BROADCOM_VENDOR_ID, BCM56212_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1092 { BROADCOM_VENDOR_ID, BCM56213_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1093 { BROADCOM_VENDOR_ID, BCM56230_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1094 { BROADCOM_VENDOR_ID, BCM56231_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1095 { BROADCOM_VENDOR_ID, BCM53718_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1096 { BROADCOM_VENDOR_ID, BCM53714_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1097 { BROADCOM_VENDOR_ID, BCM53716_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1098 { BROADCOM_VENDOR_ID, BCM56018_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1099 { BROADCOM_VENDOR_ID, BCM56014_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1100 { BROADCOM_VENDOR_ID, BCM56224_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1101 { BROADCOM_VENDOR_ID, BCM56225_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1102 { BROADCOM_VENDOR_ID, BCM56226_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1103 { BROADCOM_VENDOR_ID, BCM56227_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1104 { BROADCOM_VENDOR_ID, BCM56228_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1105 { BROADCOM_VENDOR_ID, BCM56229_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1106 { BROADCOM_VENDOR_ID, BCM56024_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1107 { BROADCOM_VENDOR_ID, BCM56025_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1108 { BROADCOM_VENDOR_ID, BCM53724_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1109 { BROADCOM_VENDOR_ID, BCM53726_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1110 { BROADCOM_VENDOR_ID, BCM56100_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1111 { BROADCOM_VENDOR_ID, BCM56101_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1112 { BROADCOM_VENDOR_ID, BCM56102_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1113 { BROADCOM_VENDOR_ID, BCM56105_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1114 { BROADCOM_VENDOR_ID, BCM56106_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1115 { BROADCOM_VENDOR_ID, BCM56107_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1116 { BROADCOM_VENDOR_ID, BCM56110_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1117 { BROADCOM_VENDOR_ID, BCM56111_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1118 { BROADCOM_VENDOR_ID, BCM56112_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1119 { BROADCOM_VENDOR_ID, BCM56115_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1120 { BROADCOM_VENDOR_ID, BCM56116_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1121 { BROADCOM_VENDOR_ID, BCM56117_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1122 { BROADCOM_VENDOR_ID, BCM56300_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1123 { BROADCOM_VENDOR_ID, BCM56301_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1124 { BROADCOM_VENDOR_ID, BCM56302_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1125 { BROADCOM_VENDOR_ID, BCM56303_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1126 { BROADCOM_VENDOR_ID, BCM56304_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1127 { BROADCOM_VENDOR_ID, BCM56404_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1128 { BROADCOM_VENDOR_ID, BCM56305_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1129 { BROADCOM_VENDOR_ID, BCM56306_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1130 { BROADCOM_VENDOR_ID, BCM56307_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1131 { BROADCOM_VENDOR_ID, BCM56308_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1132 { BROADCOM_VENDOR_ID, BCM56309_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1133 { BROADCOM_VENDOR_ID, BCM56310_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1134 { BROADCOM_VENDOR_ID, BCM56311_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1135 { BROADCOM_VENDOR_ID, BCM56312_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1136 { BROADCOM_VENDOR_ID, BCM56313_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1137 { BROADCOM_VENDOR_ID, BCM56314_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1138 { BROADCOM_VENDOR_ID, BCM56315_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1139 { BROADCOM_VENDOR_ID, BCM56316_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1140 { BROADCOM_VENDOR_ID, BCM56317_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1141 { BROADCOM_VENDOR_ID, BCM56318_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1142 { BROADCOM_VENDOR_ID, BCM56319_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1143 #ifndef EXCLUDE_BCM56324 1144 { BROADCOM_VENDOR_ID, BCM56322_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1145 { BROADCOM_VENDOR_ID, BCM56324_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1146 #endif /* EXCLUDE_BCM56324 */ 1147 { BROADCOM_VENDOR_ID, BCM53312_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1148 { BROADCOM_VENDOR_ID, BCM53313_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1149 { BROADCOM_VENDOR_ID, BCM53314_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1150 { BROADCOM_VENDOR_ID, BCM53324_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1151 { BROADCOM_VENDOR_ID, BCM53333_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1152 { BROADCOM_VENDOR_ID, BCM53334_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1153 { BROADCOM_VENDOR_ID, BCM53342_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1154 { BROADCOM_VENDOR_ID, BCM53343_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1155 { BROADCOM_VENDOR_ID, BCM53344_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1156 { BROADCOM_VENDOR_ID, BCM53346_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1157 { BROADCOM_VENDOR_ID, BCM53347_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1158 { BROADCOM_VENDOR_ID, BCM53393_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1159 { BROADCOM_VENDOR_ID, BCM53394_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1160 { BROADCOM_VENDOR_ID, BCM53300_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1161 { BROADCOM_VENDOR_ID, BCM53301_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1162 { BROADCOM_VENDOR_ID, BCM53302_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1163 { BROADCOM_VENDOR_ID, BCM56500_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1164 { BROADCOM_VENDOR_ID, BCM56501_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1165 { BROADCOM_VENDOR_ID, BCM56502_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1166 { BROADCOM_VENDOR_ID, BCM56503_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1167 { BROADCOM_VENDOR_ID, BCM56504_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1168 { BROADCOM_VENDOR_ID, BCM56505_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1169 { BROADCOM_VENDOR_ID, BCM56506_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1170 { BROADCOM_VENDOR_ID, BCM56507_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1171 { BROADCOM_VENDOR_ID, BCM56508_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1172 { BROADCOM_VENDOR_ID, BCM56509_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1173 { BROADCOM_VENDOR_ID, BCM56510_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1174 { BROADCOM_VENDOR_ID, BCM56511_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1175 { BROADCOM_VENDOR_ID, BCM56512_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1176 { BROADCOM_VENDOR_ID, BCM56513_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1177 { BROADCOM_VENDOR_ID, BCM56514_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1178 { BROADCOM_VENDOR_ID, BCM56516_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1179 { BROADCOM_VENDOR_ID, BCM56517_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1180 { BROADCOM_VENDOR_ID, BCM56518_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1181 { BROADCOM_VENDOR_ID, BCM56519_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1182 { BROADCOM_VENDOR_ID, BCM56580_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1183 { BROADCOM_VENDOR_ID, BCM56620_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1184 { BROADCOM_VENDOR_ID, BCM56624_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1185 { BROADCOM_VENDOR_ID, BCM56626_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1186 { BROADCOM_VENDOR_ID, BCM56628_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1187 { BROADCOM_VENDOR_ID, BCM56629_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1188 { BROADCOM_VENDOR_ID, BCM56680_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1189 { BROADCOM_VENDOR_ID, BCM56684_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1190 { BROADCOM_VENDOR_ID, BCM56700_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1191 { BROADCOM_VENDOR_ID, BCM56701_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1192 { BROADCOM_VENDOR_ID, BCM56720_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1193 { BROADCOM_VENDOR_ID, BCM56721_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1194 { BROADCOM_VENDOR_ID, BCM56725_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1195 { BROADCOM_VENDOR_ID, BCM56800_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1196 { BROADCOM_VENDOR_ID, BCM56801_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1197 { BROADCOM_VENDOR_ID, BCM56802_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1198 { BROADCOM_VENDOR_ID, BCM56803_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1199 { BROADCOM_VENDOR_ID, BCM56820_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1200 { BROADCOM_VENDOR_ID, BCM56821_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1201 { BROADCOM_VENDOR_ID, BCM56822_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1202 { BROADCOM_VENDOR_ID, BCM56823_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1203 { BROADCOM_VENDOR_ID, BCM56825_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1204 { BROADCOM_VENDOR_ID, BCM56630_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1205 { BROADCOM_VENDOR_ID, BCM56634_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1206 { BROADCOM_VENDOR_ID, BCM56636_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1207 { BROADCOM_VENDOR_ID, BCM56638_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1208 { BROADCOM_VENDOR_ID, BCM56639_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1209 { BROADCOM_VENDOR_ID, BCM56538_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1210 { BROADCOM_VENDOR_ID, BCM56520_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1211 { BROADCOM_VENDOR_ID, BCM56521_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1212 { BROADCOM_VENDOR_ID, BCM56522_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1213 { BROADCOM_VENDOR_ID, BCM56524_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1214 { BROADCOM_VENDOR_ID, BCM56526_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1215 { BROADCOM_VENDOR_ID, BCM56534_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1216 { BROADCOM_VENDOR_ID, BCM56685_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1217 { BROADCOM_VENDOR_ID, BCM56689_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1218 { BROADCOM_VENDOR_ID, BCM56331_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1219 { BROADCOM_VENDOR_ID, BCM56333_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1220 { BROADCOM_VENDOR_ID, BCM56334_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1221 { BROADCOM_VENDOR_ID, BCM56338_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1222 { BROADCOM_VENDOR_ID, BCM56320_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1223 { BROADCOM_VENDOR_ID, BCM56321_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1224 { BROADCOM_VENDOR_ID, BCM56132_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1225 { BROADCOM_VENDOR_ID, BCM56134_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1226 { BROADCOM_VENDOR_ID, BCM88732_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1227 { BROADCOM_VENDOR_ID, BCM56140_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1228 { BROADCOM_VENDOR_ID, BCM56142_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1229 { BROADCOM_VENDOR_ID, BCM56143_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1230 { BROADCOM_VENDOR_ID, BCM56144_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1231 { BROADCOM_VENDOR_ID, BCM56146_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1232 { BROADCOM_VENDOR_ID, BCM56147_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1233 { BROADCOM_VENDOR_ID, BCM56149_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1234 { BROADCOM_VENDOR_ID, BCM56150_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1235 { BROADCOM_VENDOR_ID, BCM56151_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1236 { BROADCOM_VENDOR_ID, BCM56152_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1237 { BROADCOM_VENDOR_ID, BCM56930_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1238 { BROADCOM_VENDOR_ID, BCM56931_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1239 { BROADCOM_VENDOR_ID, BCM56935_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1240 { BROADCOM_VENDOR_ID, BCM56936_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1241 { BROADCOM_VENDOR_ID, BCM56939_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1242 { BROADCOM_VENDOR_ID, BCM56840_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1243 { BROADCOM_VENDOR_ID, BCM56841_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1244 { BROADCOM_VENDOR_ID, BCM56842_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1245 { BROADCOM_VENDOR_ID, BCM56843_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1246 { BROADCOM_VENDOR_ID, BCM56844_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1247 { BROADCOM_VENDOR_ID, BCM56845_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1248 { BROADCOM_VENDOR_ID, BCM56846_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1249 { BROADCOM_VENDOR_ID, BCM56847_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1250 { BROADCOM_VENDOR_ID, BCM56549_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1251 { BROADCOM_VENDOR_ID, BCM56053_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1252 { BROADCOM_VENDOR_ID, BCM56838_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1253 { BROADCOM_VENDOR_ID, BCM56831_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1254 { BROADCOM_VENDOR_ID, BCM56835_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1255 { BROADCOM_VENDOR_ID, BCM56849_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1256 { BROADCOM_VENDOR_ID, BCM56742_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1257 { BROADCOM_VENDOR_ID, BCM56743_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1258 { BROADCOM_VENDOR_ID, BCM56744_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1259 { BROADCOM_VENDOR_ID, BCM56745_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1260 { BROADCOM_VENDOR_ID, BCM56746_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1261 { BROADCOM_VENDOR_ID, BCM56640_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1262 { BROADCOM_VENDOR_ID, BCM56548_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1263 { BROADCOM_VENDOR_ID, BCM56547_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1264 { BROADCOM_VENDOR_ID, BCM56346_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1265 { BROADCOM_VENDOR_ID, BCM56345_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1266 { BROADCOM_VENDOR_ID, BCM56344_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1267 { BROADCOM_VENDOR_ID, BCM56342_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1268 { BROADCOM_VENDOR_ID, BCM56340_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1269 { BROADCOM_VENDOR_ID, BCM56049_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1270 { BROADCOM_VENDOR_ID, BCM56048_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1271 { BROADCOM_VENDOR_ID, BCM56047_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1272 { BROADCOM_VENDOR_ID, BCM56042_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1273 { BROADCOM_VENDOR_ID, BCM56041_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1274 { BROADCOM_VENDOR_ID, BCM56040_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1275 { BROADCOM_VENDOR_ID, BCM56643_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1276 { BROADCOM_VENDOR_ID, BCM56644_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1277 { BROADCOM_VENDOR_ID, BCM56648_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1278 { BROADCOM_VENDOR_ID, BCM56649_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1279 { BROADCOM_VENDOR_ID, BCM56540_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1280 { BROADCOM_VENDOR_ID, BCM56541_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1281 { BROADCOM_VENDOR_ID, BCM56542_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1282 { BROADCOM_VENDOR_ID, BCM56543_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1283 { BROADCOM_VENDOR_ID, BCM56544_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1284 { BROADCOM_VENDOR_ID, BCM56545_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1285 { BROADCOM_VENDOR_ID, BCM56546_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1286 { BROADCOM_VENDOR_ID, BCM56044_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1287 { BROADCOM_VENDOR_ID, BCM56045_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1288 { BROADCOM_VENDOR_ID, BCM56046_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1289 { BROADCOM_VENDOR_ID, BCM55440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1290 { BROADCOM_VENDOR_ID, BCM56440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1291 { BROADCOM_VENDOR_ID, BCM56441_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1292 { BROADCOM_VENDOR_ID, BCM56442_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1293 { BROADCOM_VENDOR_ID, BCM56443_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1294 { BROADCOM_VENDOR_ID, BCM56445_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1295 { BROADCOM_VENDOR_ID, BCM56446_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1296 { BROADCOM_VENDOR_ID, BCM56447_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1297 { BROADCOM_VENDOR_ID, BCM56448_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1298 { BROADCOM_VENDOR_ID, BCM56449_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1299 { BROADCOM_VENDOR_ID, BCM56240_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1300 { BROADCOM_VENDOR_ID, BCM56241_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1301 { BROADCOM_VENDOR_ID, BCM56242_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1302 { BROADCOM_VENDOR_ID, BCM56243_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1303 { BROADCOM_VENDOR_ID, BCM56245_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1304 { BROADCOM_VENDOR_ID, BCM56246_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1305 { BROADCOM_VENDOR_ID, BCM55450_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1306 { BROADCOM_VENDOR_ID, BCM55455_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1307 { BROADCOM_VENDOR_ID, BCM56260_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1308 { BROADCOM_VENDOR_ID, BCM56270_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1309 { BROADCOM_VENDOR_ID, BCM56271_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1310 { BROADCOM_VENDOR_ID, BCM56272_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1311 { BROADCOM_VENDOR_ID, BCM53460_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1312 { BROADCOM_VENDOR_ID, BCM53461_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1313 { BROADCOM_VENDOR_ID, BCM56261_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1314 { BROADCOM_VENDOR_ID, BCM56262_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1315 { BROADCOM_VENDOR_ID, BCM56263_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1316 { BROADCOM_VENDOR_ID, BCM56265_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1317 { BROADCOM_VENDOR_ID, BCM56266_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1318 { BROADCOM_VENDOR_ID, BCM56267_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1319 { BROADCOM_VENDOR_ID, BCM56268_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1320 { BROADCOM_VENDOR_ID, BCM56233_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1321 { BROADCOM_VENDOR_ID, BCM56460_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1322 { BROADCOM_VENDOR_ID, BCM56461_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1323 { BROADCOM_VENDOR_ID, BCM56462_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1324 { BROADCOM_VENDOR_ID, BCM56463_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1325 { BROADCOM_VENDOR_ID, BCM56465_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1326 { BROADCOM_VENDOR_ID, BCM56466_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1327 { BROADCOM_VENDOR_ID, BCM56467_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1328 { BROADCOM_VENDOR_ID, BCM56468_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1329 { BROADCOM_VENDOR_ID, BCM56246_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1330 { BROADCOM_VENDOR_ID, BCM56248_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1331 { BROADCOM_VENDOR_ID, BCM56450_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1332 { BROADCOM_VENDOR_ID, BCM56452_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1333 { BROADCOM_VENDOR_ID, BCM56454_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1334 { BROADCOM_VENDOR_ID, BCM56455_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1335 { BROADCOM_VENDOR_ID, BCM56456_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1336 { BROADCOM_VENDOR_ID, BCM56457_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1337 { BROADCOM_VENDOR_ID, BCM56458_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1338 { BROADCOM_VENDOR_ID, BCM56850_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1339 { BROADCOM_VENDOR_ID, BCM56851_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1340 { BROADCOM_VENDOR_ID, BCM56852_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1341 { BROADCOM_VENDOR_ID, BCM56853_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1342 { BROADCOM_VENDOR_ID, BCM56854_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1343 { BROADCOM_VENDOR_ID, BCM56855_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1344 { BROADCOM_VENDOR_ID, BCM56834_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1345 { BROADCOM_VENDOR_ID, BCM56750_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1346 { BROADCOM_VENDOR_ID, BCM56830_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1347 { BROADCOM_VENDOR_ID, BCM55440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1348 { BROADCOM_VENDOR_ID, BCM55441_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1349 { BROADCOM_VENDOR_ID, BCM56060_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1350 { BROADCOM_VENDOR_ID, BCM56062_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1351 { BROADCOM_VENDOR_ID, BCM56063_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1352 { BROADCOM_VENDOR_ID, BCM56064_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1353 { BROADCOM_VENDOR_ID, BCM56065_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1354 { BROADCOM_VENDOR_ID, BCM56066_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1355 { BROADCOM_VENDOR_ID, BCM53401_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1356 { BROADCOM_VENDOR_ID, BCM53411_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1357 { BROADCOM_VENDOR_ID, BCM53402_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1358 { BROADCOM_VENDOR_ID, BCM53412_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1359 { BROADCOM_VENDOR_ID, BCM53403_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1360 { BROADCOM_VENDOR_ID, BCM53413_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1361 { BROADCOM_VENDOR_ID, BCM53404_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1362 { BROADCOM_VENDOR_ID, BCM53414_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1363 { BROADCOM_VENDOR_ID, BCM53405_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1364 { BROADCOM_VENDOR_ID, BCM53415_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1365 { BROADCOM_VENDOR_ID, BCM53406_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1366 { BROADCOM_VENDOR_ID, BCM53416_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1367 { BROADCOM_VENDOR_ID, BCM53408_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1368 { BROADCOM_VENDOR_ID, BCM53418_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1369 { BROADCOM_VENDOR_ID, BCM53454_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1370 { BROADCOM_VENDOR_ID, BCM53455_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1371 { BROADCOM_VENDOR_ID, BCM53456_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1372 { BROADCOM_VENDOR_ID, BCM53457_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1373 { BROADCOM_VENDOR_ID, BCM53422_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1374 { BROADCOM_VENDOR_ID, BCM53424_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1375 { BROADCOM_VENDOR_ID, BCM53426_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1376 { BROADCOM_VENDOR_ID, BCM53365_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1377 { BROADCOM_VENDOR_ID, BCM53369_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1378 { BROADCOM_VENDOR_ID, BCM56960_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1379 { BROADCOM_VENDOR_ID, BCM56961_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1380 { BROADCOM_VENDOR_ID, BCM56962_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1381 { BROADCOM_VENDOR_ID, BCM56963_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1382 { BROADCOM_VENDOR_ID, BCM56930_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1383 { BROADCOM_VENDOR_ID, BCM56968_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1384 { BROADCOM_VENDOR_ID, BCM56970_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1385 { BROADCOM_VENDOR_ID, BCM56971_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1386 { BROADCOM_VENDOR_ID, BCM56972_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1387 { BROADCOM_VENDOR_ID, BCM56974_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1388 { BROADCOM_VENDOR_ID, BCM56975_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1389 { BROADCOM_VENDOR_ID, BCM56168_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1390 { BROADCOM_VENDOR_ID, BCM56169_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1391 { BROADCOM_VENDOR_ID, BCM56560_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1392 { BROADCOM_VENDOR_ID, BCM56561_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1393 { BROADCOM_VENDOR_ID, BCM56562_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1394 { BROADCOM_VENDOR_ID, BCM56565_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1395 { BROADCOM_VENDOR_ID, BCM56566_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1396 { BROADCOM_VENDOR_ID, BCM56567_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1397 { BROADCOM_VENDOR_ID, BCM56670_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1398 { BROADCOM_VENDOR_ID, BCM56671_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1399 { BROADCOM_VENDOR_ID, BCM56672_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1400 { BROADCOM_VENDOR_ID, BCM56675_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1401 { BROADCOM_VENDOR_ID, BCM56568_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1402 { BROADCOM_VENDOR_ID, BCM56670_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1403 { BROADCOM_VENDOR_ID, BCM56760_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1404 { BROADCOM_VENDOR_ID, BCM56761_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1405 { BROADCOM_VENDOR_ID, BCM56762_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1406 { BROADCOM_VENDOR_ID, BCM56764_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1407 { BROADCOM_VENDOR_ID, BCM56765_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1408 { BROADCOM_VENDOR_ID, BCM56766_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1409 { BROADCOM_VENDOR_ID, BCM56768_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1410 { BROADCOM_VENDOR_ID, BCM56069_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1411 { BROADCOM_VENDOR_ID, BCM56068_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1412 { BROADCOM_VENDOR_ID, BCM56160_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1413 { BROADCOM_VENDOR_ID, BCM56162_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1414 { BROADCOM_VENDOR_ID, BCM56163_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1415 { BROADCOM_VENDOR_ID, BCM56164_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1416 { BROADCOM_VENDOR_ID, BCM56166_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1417 { BROADCOM_VENDOR_ID, BCM53440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1418 { BROADCOM_VENDOR_ID, BCM53443_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1419 { BROADCOM_VENDOR_ID, BCM53442_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1420 { BROADCOM_VENDOR_ID, BCM53434_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1421 { BROADCOM_VENDOR_ID, BCM56965_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1422 { BROADCOM_VENDOR_ID, BCM56969_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1423 { BROADCOM_VENDOR_ID, BCM56966_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1424 { BROADCOM_VENDOR_ID, BCM56967_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1425 { BROADCOM_VENDOR_ID, BCM56170_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1426 { BROADCOM_VENDOR_ID, BCM56172_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1427 { BROADCOM_VENDOR_ID, BCM56174_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1428 { BROADCOM_VENDOR_ID, BCM53570_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1429 { BROADCOM_VENDOR_ID, BCM53575_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1430 { BROADCOM_VENDOR_ID, BCM56070_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1431 { BROADCOM_VENDOR_ID, BCM56071_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1432 { BROADCOM_VENDOR_ID, BCM56072_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1433 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9656, PCI_ANY_ID, PCI_ANY_ID }, 1434 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, PCI_ANY_ID, PCI_ANY_ID }, 1435 { BCM53000_VENDOR_ID, BCM53000PCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1436 #ifdef BCM_PETRA_SUPPORT 1437 { BROADCOM_VENDOR_ID, BCM88650_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1438 { BROADCOM_VENDOR_ID, BCM88350_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1439 { BROADCOM_VENDOR_ID, BCM88351_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1440 { BROADCOM_VENDOR_ID, BCM88450_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1441 { BROADCOM_VENDOR_ID, BCM88451_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1442 { BROADCOM_VENDOR_ID, BCM88550_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1443 { BROADCOM_VENDOR_ID, BCM88551_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1444 { BROADCOM_VENDOR_ID, BCM88552_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1445 { BROADCOM_VENDOR_ID, BCM88651_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1446 { BROADCOM_VENDOR_ID, BCM88654_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1447 { PCP_PCI_VENDOR_ID, PCP_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1448 { ACP_PCI_VENDOR_ID, ACP_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1449 { BROADCOM_VENDOR_ID, BCM88660_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1450 { BROADCOM_VENDOR_ID, BCM88670_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1451 { BROADCOM_VENDOR_ID, BCM88671_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1452 { BROADCOM_VENDOR_ID, BCM88671M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1453 { BROADCOM_VENDOR_ID, BCM88672_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1454 { BROADCOM_VENDOR_ID, BCM88673_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1455 { BROADCOM_VENDOR_ID, BCM88674_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1456 { BROADCOM_VENDOR_ID, BCM88675_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1457 { BROADCOM_VENDOR_ID, BCM88675M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1458 { BROADCOM_VENDOR_ID, BCM88676_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1459 { BROADCOM_VENDOR_ID, BCM88676M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1460 { BROADCOM_VENDOR_ID, BCM88677_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1461 { BROADCOM_VENDOR_ID, BCM88678_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1462 { BROADCOM_VENDOR_ID, BCM88679_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1463 { BROADCOM_VENDOR_ID, BCM88370_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1464 { BROADCOM_VENDOR_ID, BCM88371_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1465 { BROADCOM_VENDOR_ID, BCM88371M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1466 { BROADCOM_VENDOR_ID, BCM88375_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1467 { BROADCOM_VENDOR_ID, BCM88470_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1468 { BROADCOM_VENDOR_ID, BCM88470P_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1469 { BROADCOM_VENDOR_ID, BCM88471_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1470 { BROADCOM_VENDOR_ID, BCM88473_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1471 { BROADCOM_VENDOR_ID, BCM88474_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1472 { BROADCOM_VENDOR_ID, BCM88474H_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1473 { BROADCOM_VENDOR_ID, BCM88476_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1474 { BROADCOM_VENDOR_ID, BCM88477_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1475 1476 1477 { BROADCOM_VENDOR_ID, BCM88270_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1478 { BROADCOM_VENDOR_ID, BCM88271_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1479 { BROADCOM_VENDOR_ID, BCM88272_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1480 { BROADCOM_VENDOR_ID, BCM88273_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1481 { BROADCOM_VENDOR_ID, BCM88274_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1482 { BROADCOM_VENDOR_ID, BCM88276_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1483 { BROADCOM_VENDOR_ID, BCM88278_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1484 { BROADCOM_VENDOR_ID, BCM88279_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1485 1486 { BROADCOM_VENDOR_ID, BCM8206_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1487 1488 { BROADCOM_VENDOR_ID, BCM88376_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1489 { BROADCOM_VENDOR_ID, BCM88376M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1490 { BROADCOM_VENDOR_ID, BCM88377_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1491 { BROADCOM_VENDOR_ID, BCM88378_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1492 { BROADCOM_VENDOR_ID, BCM88379_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1493 { BROADCOM_VENDOR_ID, BCM88680_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1494 { BROADCOM_VENDOR_ID, BCM88681_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1495 { BROADCOM_VENDOR_ID, BCM88682_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1496 { BROADCOM_VENDOR_ID, BCM88683_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1497 { BROADCOM_VENDOR_ID, BCM88684_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1498 { BROADCOM_VENDOR_ID, BCM88685_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1499 { BROADCOM_VENDOR_ID, BCM88687_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1500 { BROADCOM_VENDOR_ID, BCM88380_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1501 { BROADCOM_VENDOR_ID, BCM88381_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1502 { BROADCOM_VENDOR_ID, BCM88202_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1503 { BROADCOM_VENDOR_ID, BCM88360_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1504 { BROADCOM_VENDOR_ID, BCM88361_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1505 { BROADCOM_VENDOR_ID, BCM88363_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1506 { BROADCOM_VENDOR_ID, BCM88460_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1507 { BROADCOM_VENDOR_ID, BCM88461_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1508 { BROADCOM_VENDOR_ID, BCM88560_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1509 { BROADCOM_VENDOR_ID, BCM88561_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1510 { BROADCOM_VENDOR_ID, BCM88562_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1511 { BROADCOM_VENDOR_ID, BCM88661_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1512 { BROADCOM_VENDOR_ID, BCM88664_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1513 #endif 1514 #ifdef BCM_DNX_SUPPORT 1515 { BROADCOM_VENDOR_ID, BCM88690_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1516 { BROADCOM_VENDOR_ID, BCM88690_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1517 { BROADCOM_VENDOR_ID, BCM88691_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1518 { BROADCOM_VENDOR_ID, BCM88692_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1519 { BROADCOM_VENDOR_ID, BCM88693_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1520 { BROADCOM_VENDOR_ID, BCM88694_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1521 { BROADCOM_VENDOR_ID, BCM88695_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1522 { BROADCOM_VENDOR_ID, BCM88696_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1523 { BROADCOM_VENDOR_ID, BCM88697_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1524 { BROADCOM_VENDOR_ID, BCM88698_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1525 { BROADCOM_VENDOR_ID, BCM88699_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1526 { BROADCOM_VENDOR_ID, BCM8869A_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1527 { BROADCOM_VENDOR_ID, BCM8869B_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1528 { BROADCOM_VENDOR_ID, BCM8869C_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1529 { BROADCOM_VENDOR_ID, BCM8869D_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1530 { BROADCOM_VENDOR_ID, BCM8869E_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1531 { BROADCOM_VENDOR_ID, BCM8869F_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1532 { BROADCOM_VENDOR_ID, BCM88800_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1533 { BROADCOM_VENDOR_ID, BCM88821_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1534 { BROADCOM_VENDOR_ID, BCM88826_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1535 { BROADCOM_VENDOR_ID, BCM88802_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1536 { BROADCOM_VENDOR_ID, BCM88803_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1537 { BROADCOM_VENDOR_ID, BCM88804_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1538 { BROADCOM_VENDOR_ID, BCM88805_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1539 { BROADCOM_VENDOR_ID, BCM88806_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1540 { BROADCOM_VENDOR_ID, BCM88820_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1541 { BROADCOM_VENDOR_ID, BCM88822_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1542 { BROADCOM_VENDOR_ID, BCM88823_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1543 { BROADCOM_VENDOR_ID, BCM88824_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1544 { BROADCOM_VENDOR_ID, BCM88825_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1545 { BROADCOM_VENDOR_ID, BCM88480_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1546 { BROADCOM_VENDOR_ID, BCM88481_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1547 { BROADCOM_VENDOR_ID, BCM88482_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1548 { BROADCOM_VENDOR_ID, BCM88483_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1549 { BROADCOM_VENDOR_ID, BCM88484_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1550 { BROADCOM_VENDOR_ID, BCM88485_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1551 { BROADCOM_VENDOR_ID, BCM88486_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1552 { BROADCOM_VENDOR_ID, BCM88487_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1553 { BROADCOM_VENDOR_ID, BCM88488_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1554 { BROADCOM_VENDOR_ID, BCM88489_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1555 { BROADCOM_VENDOR_ID, BCM8848A_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1556 { BROADCOM_VENDOR_ID, BCM8848B_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1557 { BROADCOM_VENDOR_ID, BCM8848C_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1558 { BROADCOM_VENDOR_ID, BCM8848D_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1559 { BROADCOM_VENDOR_ID, BCM8848E_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1560 { BROADCOM_VENDOR_ID, BCM8848F_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1561 { BROADCOM_VENDOR_ID, BCM88280_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1562 { BROADCOM_VENDOR_ID, BCM88281_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1563 { BROADCOM_VENDOR_ID, BCM88282_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1564 { BROADCOM_VENDOR_ID, BCM88283_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1565 { BROADCOM_VENDOR_ID, BCM88284_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1566 { BROADCOM_VENDOR_ID, BCM88285_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1567 { BROADCOM_VENDOR_ID, BCM88286_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1568 { BROADCOM_VENDOR_ID, BCM88287_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1569 { BROADCOM_VENDOR_ID, BCM88288_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1570 { BROADCOM_VENDOR_ID, BCM88289_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1571 { BROADCOM_VENDOR_ID, BCM8828A_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1572 { BROADCOM_VENDOR_ID, BCM8828B_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1573 { BROADCOM_VENDOR_ID, BCM8828C_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1574 { BROADCOM_VENDOR_ID, BCM8828D_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1575 { BROADCOM_VENDOR_ID, BCM8828E_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1576 { BROADCOM_VENDOR_ID, BCM8828F_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1577 { BROADCOM_VENDOR_ID, BCM88850_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1578 #endif /* BCM_DNX_SUPPORT */ 1579 #ifdef BCM_DFE_SUPPORT 1580 { BROADCOM_VENDOR_ID, BCM88750_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1581 { BROADCOM_VENDOR_ID, BCM88753_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1582 { BROADCOM_VENDOR_ID, BCM88755_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1583 { BROADCOM_VENDOR_ID, BCM88770_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1584 { BROADCOM_VENDOR_ID, BCM88773_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1585 { BROADCOM_VENDOR_ID, BCM88774_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1586 { BROADCOM_VENDOR_ID, BCM88775_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1587 { BROADCOM_VENDOR_ID, BCM88776_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1588 { BROADCOM_VENDOR_ID, BCM88777_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1589 #ifndef DNX_IGNORE_FE3200 1590 { BROADCOM_VENDOR_ID, BCM88950_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1591 #endif 1592 { BROADCOM_VENDOR_ID, BCM88953_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1593 { BROADCOM_VENDOR_ID, BCM88954_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1594 { BROADCOM_VENDOR_ID, BCM88955_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1595 { BROADCOM_VENDOR_ID, BCM88956_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1596 { BROADCOM_VENDOR_ID, BCM88752_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1597 { BROADCOM_VENDOR_ID, BCM88772_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1598 { BROADCOM_VENDOR_ID, BCM88952_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1599 #endif 1600 #ifdef BCM_DNXF_SUPPORT 1601 { BROADCOM_VENDOR_ID, BCM88790_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1602 { BROADCOM_VENDOR_ID, BCM88791_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1603 { BROADCOM_VENDOR_ID, BCM88792_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1604 { BROADCOM_VENDOR_ID, BCM88793_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1605 { BROADCOM_VENDOR_ID, BCM88794_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1606 { BROADCOM_VENDOR_ID, BCM88795_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1607 { BROADCOM_VENDOR_ID, BCM88796_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1608 { BROADCOM_VENDOR_ID, BCM88797_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1609 { BROADCOM_VENDOR_ID, BCM88798_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1610 { BROADCOM_VENDOR_ID, BCM88799_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1611 { BROADCOM_VENDOR_ID, BCM8879A_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1612 { BROADCOM_VENDOR_ID, BCM8879B_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1613 { BROADCOM_VENDOR_ID, BCM8879C_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1614 { BROADCOM_VENDOR_ID, BCM8879D_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1615 { BROADCOM_VENDOR_ID, BCM8879F_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1616 #endif 1617 { BROADCOM_VENDOR_ID, BCM56860_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1618 { BROADCOM_VENDOR_ID, BCM56861_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1619 { BROADCOM_VENDOR_ID, BCM56862_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1620 { BROADCOM_VENDOR_ID, BCM56864_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1621 { BROADCOM_VENDOR_ID, BCM56865_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1622 { BROADCOM_VENDOR_ID, BCM56866_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1623 { BROADCOM_VENDOR_ID, BCM56867_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1624 { BROADCOM_VENDOR_ID, BCM56868_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1625 { BROADCOM_VENDOR_ID, BCM56833_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1626 { BROADCOM_VENDOR_ID, BCM56832_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1627 { BROADCOM_VENDOR_ID, BCM56836_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1628 { BROADCOM_VENDOR_ID, BCM56870_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1629 { BROADCOM_VENDOR_ID, BCM56273_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1630 { BROADCOM_VENDOR_ID, BCM56274_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1631 { BROADCOM_VENDOR_ID, BCM56275_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1632 { BROADCOM_VENDOR_ID, BCM56276_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1633 { BROADCOM_VENDOR_ID, BCM56277_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1634 { BROADCOM_VENDOR_ID, BCM56278_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1635 { BROADCOM_VENDOR_ID, BCM56279_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1636 { BROADCOM_VENDOR_ID, BCM56575_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1637 { BROADCOM_VENDOR_ID, BCM56370_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1638 { BROADCOM_VENDOR_ID, BCM56371_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1639 { BROADCOM_VENDOR_ID, BCM56372_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1640 { BROADCOM_VENDOR_ID, BCM56374_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1641 { BROADCOM_VENDOR_ID, BCM56375_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1642 { BROADCOM_VENDOR_ID, BCM56376_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1643 { BROADCOM_VENDOR_ID, BCM56377_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1644 { BROADCOM_VENDOR_ID, BCM56577_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1645 { BROADCOM_VENDOR_ID, BCM56578_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1646 { BROADCOM_VENDOR_ID, BCM56579_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1647 { BROADCOM_VENDOR_ID, BCM56873_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1648 { BROADCOM_VENDOR_ID, BCM56770_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1649 { BROADCOM_VENDOR_ID, BCM56771_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1650 { BROADCOM_VENDOR_ID, BCM56980_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1651 { BROADCOM_VENDOR_ID, BCM56981_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1652 { BROADCOM_VENDOR_ID, BCM56982_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1653 { BROADCOM_VENDOR_ID, BCM56983_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1654 { BROADCOM_VENDOR_ID, BCM56984_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1655 { BROADCOM_VENDOR_ID, BCM53540_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1656 { BROADCOM_VENDOR_ID, BCM53547_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1657 { BROADCOM_VENDOR_ID, BCM53548_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1658 { BROADCOM_VENDOR_ID, BCM53549_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1659 { BROADCOM_VENDOR_ID, BCM56470_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1660 { BROADCOM_VENDOR_ID, BCM56471_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1661 { BROADCOM_VENDOR_ID, BCM56472_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1662 { BROADCOM_VENDOR_ID, BCM56475_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1663 { 0, 0, 0, 0 } 1664 };; 1665 1666 MODULE_DEVICE_TABLE(pci, _id_table); 1667 1668 #define pci_bus_b(n) list_entry(n, struct pci_bus, node) 1669 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) 1670 #define MAX_RC_NUM 4 1671 1672 static struct pci_bus * 1673 pci_do_bus_find(struct pci_bus* bus, int rc, int vendor, int device) 1674 { 1675 struct list_head *tmp; 1676 struct pci_dev *dev; 1677 struct pci_bus *sub_bus; 1678 int func = 0; 1679 1680 if (unlikely(list_empty(&bus->children))) { 1681 return NULL; 1682 } 1683 list_for_each(tmp, &bus->children) { 1684 sub_bus = pci_bus_b(tmp); 1685 dev = sub_bus->self; 1686 func = dev->devfn & 0x7; 1687 if (dev->vendor == vendor && dev->device == device && rc == func) { 1688 if (debug >= 1) { 1689 gprintk("pci_do_bus_find: dev->vendor = 0x%x, dev->device = 0x%x on rc(%d)\n", 1690 dev->vendor, dev->device, rc); 1691 } 1692 return sub_bus; 1693 } 1694 } 1695 return NULL; 1696 } 1697 1698 static struct pci_dev * 1699 _pci_do_bus_dev_find(struct pci_bus* bus, unsigned int vendor, unsigned int device) 1700 { 1701 struct list_head *tmp; 1702 struct pci_dev *dev; 1703 1704 if (unlikely(list_empty(&bus->devices))) { 1705 return NULL; 1706 } 1707 list_for_each(tmp, &bus->devices) { 1708 dev = pci_dev_b(tmp); 1709 if (dev->vendor == vendor && (device == PCI_ANY_ID || dev->device == device)) { 1710 if (debug >= 1) { 1711 gprintk("_pci_do_rc_dev_find: vendor = %x, device = %x\n", vendor, device); 1712 } 1713 return dev; 1714 } 1715 } 1716 return NULL; 1717 } 1718 1719 static struct pci_dev * 1720 pci_do_rc_dev_find(int rc) 1721 { 1722 struct pci_bus *root_bus = pci_find_bus(0,0); 1723 struct pci_bus *bus_rc = NULL; 1724 struct pci_dev *dev_on_rc = NULL; 1725 unsigned int pci_dev_id = 0; 1726 1727 if(NULL == root_bus) { 1728 if (debug >= 1) gprintk("Not find root bus\n"); 1729 return NULL; 1730 } 1731 bus_rc = pci_do_bus_find(root_bus, rc, 0x184e, 0x1004); 1732 if (NULL == bus_rc) { 1733 if (debug >= 1) { 1734 gprintk("Not find vendor(0x184e) device(0x1004) bus\n"); 1735 } 1736 return NULL; 1737 } 1738 for(pci_dev_id = 0; pci_dev_id < sizeof(_id_table)/sizeof(struct pci_device_id); pci_dev_id++) { 1739 dev_on_rc = _pci_do_bus_dev_find(bus_rc, _id_table[pci_dev_id].vendor, _id_table[pci_dev_id].device); 1740 if (NULL != dev_on_rc) { 1741 return dev_on_rc; 1742 } 1743 } 1744 if (debug >= 1) { 1745 gprintk("Not find device at rc(%d)\n", rc); 1746 } 1747 return NULL; 1748 } 1749 1750 /* 1751 * Function: p2p_bridge 1752 * 1753 * Purpose: 1754 * Finalize initialization secondary PCI-PCI bridge. 1755 * Parameters: 1756 * membase - start of memory address space for secondary PCI bus 1757 * Returns: 1758 * 0 1759 * Notes: 1760 * The membase depends on the processor architecture, and is 1761 * derived from the memory space addresses set up by the kernel. 1762 */ 1763 static int 1764 p2p_bridge(void) 1765 { 1766 struct pci_dev *dev, *dev_on_rc; 1767 uint16 cmd; 1768 uint16 mem_base; 1769 uint16 mem_limit; 1770 uint8 bridge_ctrl; 1771 uint8 rc_index; 1772 1773 if ((dev = PCI_FIND_DEV(DC21150_VENDOR_ID, DC21150_DEVICE_ID, NULL)) != NULL || 1774 (dev = PCI_FIND_DEV(HINT_HB4_VENDOR_ID, HINT_HB4_DEVICE_ID, NULL)) != NULL || 1775 (dev = PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)) != NULL) { 1776 1777 if (debug >= 1) gprintk("fixing up PCI-to-PCI bridge\n"); 1778 /* Adjust command register */ 1779 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1780 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 1781 /* Disable device */ 1782 pci_write_config_word(dev, PCI_COMMAND, 0); 1783 /* Initialize non-prefetchable memory window if needed */ 1784 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base); 1785 if (mem_base == 0) { 1786 mem_base = (uint16)((_pci_mem_start & 0xFFF00000) >> 16); 1787 mem_limit = (uint16)((_pci_mem_end & 0xFFF00000) >> 16); 1788 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base); 1789 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit); 1790 } 1791 /* Enable PCI clocks on remote end */ 1792 pci_write_config_word(dev, PCI_CFG_DEC21150_SEC_CLK, 0); 1793 /* Re-enable config space */ 1794 pci_write_config_word(dev, PCI_COMMAND, cmd); 1795 1796 /* Avoid DMA data corruption */ 1797 if (dev->vendor == HINT_HB4_VENDOR_ID) { 1798 /* Fix for HiNT bridge and BCM4704 DMA problem */ 1799 if ((dev = PCI_FIND_DEV(BCM4704_VENDOR_ID, BCM4704_DEVICE_ID, NULL)) != NULL) { 1800 /* Reset PrefetchEn (PE) */ 1801 pci_write_config_dword(dev, 0x8c, 1); 1802 if (debug >= 1) { 1803 gprintk("reset PrefetchEn on BCM4704 when HiNT bridge is present\n"); 1804 } 1805 } 1806 } 1807 } 1808 /* Enable fast back-to-back read/write */ 1809 if ((dev = PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)) != NULL) { 1810 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1811 cmd |= PCI_COMMAND_FAST_BACK; 1812 pci_read_config_byte(dev, PCI_BRIDGE_CONTROL, &bridge_ctrl); 1813 bridge_ctrl |= PCI_BRIDGE_CTL_FAST_BACK; 1814 pci_write_config_word(dev, PCI_COMMAND, 0); 1815 pci_write_config_byte(dev, PCI_BRIDGE_CONTROL, bridge_ctrl); 1816 pci_write_config_word(dev, PCI_COMMAND, cmd); 1817 } 1818 /* Netlogic XLP CPU */ 1819 for(rc_index = 0; rc_index < MAX_RC_NUM; rc_index++) { 1820 dev_on_rc = pci_do_rc_dev_find(rc_index); 1821 if (dev_on_rc != NULL ) { 1822 dev = PCI_FIND_DEV(0x184e, 0x1004, NULL); 1823 if (dev != NULL ) { 1824 pci_write_config_dword(dev,0x78,MAX_PAYLOAD_256B | 1825 MAX_READ_REQ_256B); 1826 } 1827 } 1828 } 1829 if ((dev = PCI_FIND_DEV(0x14e4, 0xb634, NULL)) != NULL) { 1830 pci_write_config_dword(dev,0x78,MAX_PAYLOAD_256B | 1831 MAX_READ_REQ_256B); 1832 } 1833 1834 if ((dev = PCI_FIND_DEV(PCI_VNDID_PERICOM, PCI_DEVID_PI7C9X130, NULL)) != NULL) { 1835 /* 1836 * Configure the PCIE cap: Max payload size: 256, Max Read 1837 * Request size: 256, disabling relax ordering. 1838 * Writes to the PCIE capability device control register 1839 */ 1840 pci_write_config_dword(dev, DEV_CTRL_REG, 1841 MAX_PAYLOAD_256B | MAX_READ_REQ_256B); 1842 } 1843 1844 if ((dev = PCI_FIND_DEV(FSL_VENDOR_ID, FSL8548PCIE_DEVICE_ID, NULL)) != NULL || 1845 (dev = PCI_FIND_DEV(FSL_VENDOR_ID, FSL2020EPCIE_DEVICE_ID, NULL)) != NULL) { 1846 /* 1847 * Configure the PCIE cap: Max payload size: 256, Max Read 1848 * Request size: 256, disabling relax ordering. 1849 * Writes to the PCIE capability device control register 1850 */ 1851 pci_write_config_dword(dev, FSL8548PCIE_DEV_CTRL_REG, 1852 MAX_PAYLOAD_256B | MAX_READ_REQ_256B); 1853 } 1854 if ((dev = PCI_FIND_DEV(BCM4716_VENDOR_ID, BCM4716PCIE_DEVICE_ID, NULL)) != NULL || 1855 (dev = PCI_FIND_DEV(BCM53000_VENDOR_ID, BCM53000PCIE_DEVICE_ID, NULL)) != NULL) { 1856 uint32 tmp, maxpayld, device_bmp=0, mask; 1857 unsigned long addr; 1858 uint16 tmp16, tmp161; 1859 int i, bus0 = -1, bus1 = -1, port; 1860 struct pci_dev *pcie0, *pcie1; 1861 1862 pcie0 = dev; 1863 bus0 = dev->bus->number; 1864 if ((pcie1 = PCI_FIND_DEV(BCM53000_VENDOR_ID, BCM53000PCIE_DEVICE_ID, pcie0)) != NULL) { 1865 bus1 = pcie1->bus->number; 1866 } 1867 1868 for(i = 0; i < _ndevices; i++) { 1869 bde_ctrl_t *ctrl = _devices + i; 1870 1871 mask = BDE_SWITCH_DEV_TYPE | BDE_PCI_DEV_TYPE; 1872 if ((ctrl->dev_type & mask) == mask) { 1873 if (ctrl->pci_device->bus->number == bus0) { 1874 device_bmp |= 1 << 0; 1875 } 1876 if (ctrl->pci_device->bus->number == bus1) { 1877 device_bmp |= 1 << 1; 1878 } 1879 } 1880 } 1881 1882 /* configure the PCIE cap: Max payload size: 256, Max Read 1883 * Request size: 256, disabling relax ordering. 1884 * Writes to the PCIE capability device control register 1885 */ 1886 1887 i = 0; 1888 while(device_bmp) { 1889 if (device_bmp & (1 << i)){ 1890 port = i ; 1891 pci_read_config_dword(BCM53000PCIE_DEV(port), 1892 BCM53000PCIE_DEV_CAP_REG, &tmp); 1893 maxpayld = (tmp & BCM53000PCIE_MAX_PAYLOAD_MASK); 1894 if (debug >= 1) { 1895 gprintk("port %d\n",port); 1896 gprintk("DevCap (@%x): 0x%x%c\n", BCM53000PCIE_DEV_CAP_REG, tmp, 1897 (maxpayld != BCM53000PCIE_CAP_MAX_PAYLOAD_256B) ? ' ':'\n'); 1898 } 1899 if (maxpayld != BCM53000PCIE_CAP_MAX_PAYLOAD_256B) { 1900 addr = BCM53000PCIE_BASE(port); 1901 addr |= (BCM53000PCIE_SROM_SPACE | BCM53000PCIE_SPROM_OFFSET); 1902 tmp16 = *((uint16 *)addr); 1903 if (debug >= 1){ 1904 gprintk("addr %lx spromData.MaxPayloadSize: 0x%x\n", addr, tmp16); 1905 } 1906 mask = BCM53000PCIE_SPROM_MAX_PAYLOAD_MASK; 1907 if ((tmp16 & mask) != BCM53000PCIE_SPROM_MAX_PAYLOAD_256B) { 1908 tmp161 = (tmp16 & ~mask) | BCM53000PCIE_SPROM_MAX_PAYLOAD_256B; 1909 *((uint16 *)addr) = tmp161; 1910 if (debug >= 1) { 1911 tmp16 = 0; 1912 tmp16 = *((uint16 *)addr); 1913 gprintk("Enable spromData.MaxPayloadSize to 1 (256 bytes): " 1914 "0x%x (%s w/ 0x%x)\n", tmp161, 1915 ((tmp16 & mask) == BCM53000PCIE_SPROM_MAX_PAYLOAD_256B) ? 1916 "Success":"Fail", 1917 tmp16); 1918 } 1919 } 1920 pci_read_config_dword(BCM53000PCIE_DEV(port), 1921 BCM53000PCIE_DEV_CAP_REG, &tmp); 1922 if (debug >= 1){ 1923 gprintk("DevCap (@%x): now is 0x%x\n\n", 1924 BCM53000PCIE_DEV_CAP_REG, tmp); 1925 } 1926 } 1927 1928 addr = BCM53000PCIE_BASE(port); 1929 addr |= (BCM53000PCIE_FUNC0_COFIG_SPACE | BCM53000PCIE_DEV_CTRL_REG); 1930 tmp16 = *((uint16 *)addr); 1931 if (debug >= 1) { 1932 gprintk("DevControl (@%x): 0x%x\n", BCM53000PCIE_DEV_CTRL_REG, tmp16); 1933 } 1934 if (!(tmp16 & MAX_PAYLOAD_256B) || !(tmp16 & MAX_READ_REQ_256B)) { 1935 tmp161 = tmp16 | MAX_PAYLOAD_256B | MAX_READ_REQ_256B; 1936 *((uint16 *)addr) = tmp161; 1937 if (debug >= 1) { 1938 tmp16 = 0; 1939 tmp16 = *((uint16 *)addr); 1940 gprintk("addr %lx Enable DevControl MaxPayloadSize to 1 (256 bytes): " 1941 "0x%x (%s w/ 0x%x)\n", addr, tmp161, 1942 (tmp16 & MAX_PAYLOAD_256B) ? "Success":"Fail", 1943 tmp16); 1944 gprintk("Enable DevControl MaxReadRequestSize to 1 (256 bytes): " 1945 "0x%x (%s w/ 0x%x)\n\n", tmp161, 1946 (tmp16 & MAX_READ_REQ_256B) ? "Success":"Fail", 1947 tmp16); 1948 } 1949 } 1950 device_bmp &= ~(1 << i); 1951 } 1952 i++; 1953 } 1954 } 1955 1956 /* 1957 * Configure max payload to 512 on all ports in the PLX8608/PLX8617. 1958 * The device supports 128, 512, and 1024 max payload sizes. 1959 */ 1960 dev = NULL; 1961 while ((dev = PCI_FIND_DEV(PCI_VENDOR_ID_PLX, PCI_ANY_ID, dev)) != NULL) { 1962 if ((dev->device == PLX_PEX8608_DEV_ID) || 1963 (dev->device == PLX_PEX8617_DEV_ID)) { 1964 uint16 ctrl_reg; 1965 pci_read_config_word(dev, PLX_PEX86XX_DEV_CTRL_REG, &ctrl_reg); 1966 ctrl_reg = (ctrl_reg & ~(7<<5)) | MAX_PAYLOAD_512B; 1967 pci_write_config_word(dev, PLX_PEX86XX_DEV_CTRL_REG, ctrl_reg); 1968 } 1969 } 1970 return 0; 1971 } 1972 1973 #ifdef BCM_PLX9656_LOCAL_BUS 1974 1975 #define PLX_LAS0_BA 0x00000004 /* LAS0 Local Base Address Remap */ 1976 #define PLX_LAS1_BA 0x000000f4 /* LAS1 Local Base Address Remap */ 1977 #define PLX_LAS_EN 0x00000001 /* Space Enable bit */ 1978 1979 #define PLX_MMAP_PCIBAR0 0 /* Memory-Mapped Config (PCIBAR0) */ 1980 #define PLX_LAS0_PCIBAR2 2 /* Local Address Space 0 (PCIBAR2) */ 1981 #define PLX_LAS1_PCIBAR3 3 /* Local Address Space 1 (PCIBAR3) */ 1982 1983 STATIC int 1984 _plx_las_bar_get(struct pci_dev *dev) 1985 { 1986 void *local_config_addr; 1987 int bar = -1; 1988 1989 local_config_addr = IOREMAP(pci_resource_start(dev, PLX_MMAP_PCIBAR0), 1990 pci_resource_len(dev, PLX_MMAP_PCIBAR0)); 1991 if (local_config_addr) { 1992 uint32 las_remap_reg; 1993 /* 1994 * Make sure LAS0BA or LAS1BA is enabled before returning 1995 * BAR that will be used to access the Local Bus 1996 */ 1997 las_remap_reg = ioread32(local_config_addr + PLX_LAS0_BA); 1998 if (las_remap_reg & PLX_LAS_EN) { 1999 bar = PLX_LAS0_PCIBAR2; 2000 } else { 2001 las_remap_reg = ioread32(local_config_addr + PLX_LAS1_BA); 2002 if (las_remap_reg & PLX_LAS_EN) { 2003 bar = PLX_LAS1_PCIBAR3; 2004 } 2005 } 2006 } 2007 iounmap(local_config_addr); 2008 return bar; 2009 } 2010 #endif /* BCM_PLX9656_LOCAL_BUS */ 2011 2012 static void 2013 _shbde_log_func(int level, const char *str, int param) 2014 { 2015 level = (level >= SHBDE_DBG) ? 1 : 0; 2016 if (debug >= level) { 2017 gprintk("%s (%d)\n", str, param); 2018 } 2019 } 2020 /* 2021 * Function: _device_rescan_validate 2022 * 2023 * Purpose: 2024 * Check if the device is ever probed or not. 2025 * Parameters: 2026 * dev - Linux PCI device structure 2027 * Returns: 2028 * >= 0 : dev is ever probed 2029 * reutrn value is the index point to the _devices[] 2030 * -1 : dev is not probed before. 2031 */ 2032 static int 2033 _device_rescan_validate(struct pci_dev *dev) 2034 { 2035 bde_ctrl_t *ctrl; 2036 int i; 2037 2038 if (PCI_FUNC(dev->devfn) > 0) { 2039 return -1; 2040 } 2041 ctrl = NULL; 2042 for (i = 0; i < _ndevices; i ++) { 2043 ctrl = _devices + i; 2044 /* check the device id */ 2045 if (dev->device == ctrl->bde_dev.device) { 2046 /* check the bus number */ 2047 if ((dev->bus)) { 2048 if ((dev->bus->number == ctrl->bus_no) && 2049 (pci_domain_nr(dev->bus) == ctrl->domain_no)) { 2050 return i; 2051 } 2052 } 2053 } 2054 } 2055 return -1; 2056 } 2057 2058 #ifdef CONFIG_PCI_MSI 2059 2060 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2061 /** 2062 * _pci_msix_table_size - return the number of device's MSI-X table entries 2063 * @dev: pointer to the pci_dev data structure of MSI-X device function 2064 */ 2065 static int 2066 _pci_msix_table_size(struct pci_dev *dev) 2067 { 2068 int nr_entries = 0; 2069 2070 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,110)) 2071 u16 control; 2072 int pos; 2073 2074 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 2075 if (pos) { 2076 pci_read_config_word(dev, msi_control_reg(pos), &control); 2077 nr_entries = msix_table_size(control); 2078 } 2079 #else 2080 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) 2081 { 2082 /* Pass large entry value to enable MSIX to get # of entires */ 2083 struct msix_entry *entries; 2084 entries = kmalloc(sizeof(struct msix_entry) * 2085 PCI_MSIX_FLAGS_QSIZE, GFP_KERNEL); 2086 if (entries != NULL) { 2087 nr_entries = pci_enable_msix(dev, 2088 entries, PCI_MSIX_FLAGS_QSIZE); 2089 if (nr_entries < 0) { 2090 nr_entries = 0; 2091 } 2092 pci_disable_msix(dev); 2093 kfree(entries); 2094 } 2095 } 2096 #else 2097 nr_entries = pci_msix_vec_count(dev); 2098 #endif 2099 #endif 2100 2101 return nr_entries; 2102 } 2103 #endif 2104 2105 static int 2106 _msi_connect(bde_ctrl_t *ctrl) 2107 { 2108 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2109 int ret; 2110 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 2111 int i; 2112 2113 ret = _pci_msix_table_size(ctrl->pci_device); 2114 if (ret == 0) { 2115 /* MSI-X failed */ 2116 gprintk("MSI-X not supported.\n"); 2117 goto er_intx; 2118 } 2119 ctrl->entries = kcalloc(ret, sizeof(struct msix_entry), GFP_KERNEL); 2120 2121 if (!ctrl->entries) { 2122 goto er_intx; 2123 } 2124 /* Only one vector is mapped by default */ 2125 /* May be more in future, can be controlled using module param */ 2126 ctrl->msix_cnt = msixcnt; 2127 if (unlikely(debug > 1)) 2128 gprintk("MSIX Table size = %d\n", ctrl->msix_cnt); 2129 for (i = 0; i < ctrl->msix_cnt; i++) 2130 ctrl->entries[i].entry = i; 2131 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0) 2132 ret = pci_enable_msix_range(ctrl->pci_device, 2133 ctrl->entries, ctrl->msix_cnt, ctrl->msix_cnt); 2134 #else 2135 ret = pci_enable_msix(ctrl->pci_device, 2136 ctrl->entries, ctrl->msix_cnt); 2137 if (ret > 0) { 2138 /* Not enough vectors available , Retry MSI-X */ 2139 gprintk("Retrying with MSI-X interrupts = %d\n", ret); 2140 ctrl->msix_cnt = ret; 2141 msixcnt = ret; 2142 ret = pci_enable_msix(ctrl->pci_device, 2143 ctrl->entries, ctrl->msix_cnt); 2144 if (ret != 0) 2145 goto er_intx_free; 2146 } 2147 #endif 2148 if (ret < 0) { 2149 /* Error */ 2150 goto er_intx_free; 2151 } else { 2152 gprintk("Enabled MSI-X interrupts = %d\n", ctrl->msix_cnt); 2153 return 0; 2154 } 2155 } 2156 #endif 2157 2158 if (ctrl->use_msi == PCI_USE_INT_MSI) { 2159 if (pci_enable_msi(ctrl->pci_device) == 0) { 2160 ctrl->iLine = ctrl->pci_device->irq; 2161 } else { 2162 /* MSI failed */ 2163 gprintk("Failed to initialize MSI interrupts.\n"); 2164 goto er_intx; 2165 } 2166 } else { 2167 /* failed */ 2168 gprintk("Not MSI/MSIX interrupt.\n"); 2169 goto er_intx; 2170 } 2171 return 0; 2172 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2173 er_intx_free: 2174 gprintk("Failed to enable MSI-X interrupts = %d\n", ret); 2175 kfree(ctrl->entries); 2176 #endif 2177 er_intx: 2178 return -1; 2179 2180 } 2181 2182 static int 2183 _msi_disconnect(bde_ctrl_t *ctrl) 2184 { 2185 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2186 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 2187 if (ctrl->msix_cnt) { 2188 pci_disable_msix(ctrl->pci_device); 2189 kfree(ctrl->entries); 2190 ctrl->entries = NULL; 2191 ctrl->msix_cnt = 0; 2192 } 2193 } 2194 #endif 2195 if (ctrl->use_msi == PCI_USE_INT_MSI) { 2196 pci_disable_msi(ctrl->pci_device); 2197 } else { 2198 gprintk("MSI not used\n"); 2199 } 2200 return 0; 2201 } 2202 2203 #endif 2204 2205 2206 static void 2207 config_pci_intr_type(struct pci_dev *dev, bde_ctrl_t *ctrl, int iproc) 2208 { 2209 #ifdef CONFIG_PCI_MSI 2210 int ret; 2211 shbde_iproc_config_t icfg; 2212 2213 /* Each device follows global policy by default */ 2214 ctrl->use_msi = use_msi; 2215 2216 if (unlikely(debug > 1)) 2217 gprintk("%s: msi = %d\n", __func__, ctrl->use_msi); 2218 2219 /* Check IPROC version for MSIX support */ 2220 if (iproc && ctrl->bde_dev.base_address1 && 2221 (ctrl->use_msi == PCI_USE_INT_MSIX)) { 2222 if (shbde_pci_iproc_version_get(&ctrl->shbde, dev, &icfg.iproc_ver, 2223 &icfg.cmic_ver, &icfg.cmic_rev)) { 2224 if (icfg.iproc_ver < 0xe) { 2225 gprintk("%s: MSI-X not supported, using MSI.\n", __func__); 2226 ctrl->use_msi = PCI_USE_INT_MSI; 2227 } 2228 } 2229 } 2230 2231 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2232 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 2233 /* check for support MSIX vector */ 2234 ret = _pci_msix_table_size(ctrl->pci_device); 2235 if (ret == 0) { 2236 gprintk("%s: Zero MSIX table size\n", __func__); 2237 ctrl->use_msi = PCI_USE_INT_MSI; 2238 } 2239 } 2240 #endif 2241 2242 if (ctrl->use_msi == PCI_USE_INT_MSI) { 2243 /* check for support MSI vector */ 2244 ret = pci_enable_msi(ctrl->pci_device); 2245 if (ret < 0) { 2246 ctrl->use_msi = PCI_USE_INT_INTX; 2247 gprintk("%s: Failed to enable MSI, using INTx.\n", __func__); 2248 } else { 2249 pci_disable_msi(ctrl->pci_device); 2250 } 2251 } 2252 #else 2253 ctrl->use_msi = PCI_USE_INT_INTX; 2254 #endif 2255 } 2256 2257 /* 2258 * Function: _pci_probe 2259 * 2260 * Purpose: 2261 * Device initialization callback used by the Linux PCI 2262 * subsystem. Called as a result of pci_register_driver(). 2263 * Parameters: 2264 * dev - Linux PCI device structure 2265 * Returns: 2266 * 0 2267 */ 2268 static int 2269 _pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) 2270 { 2271 bde_ctrl_t *ctrl; 2272 resource_size_t paddr; 2273 uint16 cmd = 0; 2274 uint32 bar_len; 2275 int i, cmic_bar; 2276 int baroff = 0; 2277 int iproc = 0; 2278 int plx_dev = 0; 2279 int eth_dev = 0; 2280 int cpu_dev = 0; 2281 int update_devid = 0; 2282 int paxb_core = 0; 2283 int add_dev = 0, rescan = 0, rescan_idx = -1; 2284 shbde_hal_t shared_bde, *shbde = &shared_bde; 2285 2286 if (debug >= 4) {gprintk("probing: vendor_id=0x%x, device_id=0x%x\n", dev->vendor, dev->device);} 2287 if (nodevices == 1) { 2288 return 0; 2289 } 2290 2291 /* Initialize Linux hardware abstraction for shared BDE functions */ 2292 linux_shbde_hal_init(shbde, _shbde_log_func); 2293 2294 /* 2295 * If an AXI-based switch device has been found already, then it means 2296 * that the AXI bus has been probed, and that we should ignore devices 2297 * found on PCI bus zero. 2298 */ 2299 2300 #if defined(IPROC_CMICD) 2301 if ((dev->bus) && (dev->bus->number == 0)) { 2302 int i; 2303 uint32 mask = BDE_SWITCH_DEV_TYPE | BDE_AXI_DEV_TYPE; 2304 2305 for (i = 0; i < _ndevices; i++) { 2306 ctrl = _devices + i; 2307 2308 if ((ctrl->dev_type & mask) == mask) { 2309 return 0; 2310 } 2311 } 2312 } 2313 #endif /* IPROC_CMICD */ 2314 2315 /* 2316 * Note that a few supported devices have a non-Broadcom PCI vendor ID, 2317 * but since none of their associated PCI device IDs collide with the 2318 * Broadcom device IDs, the probe code below only checks the device ID. 2319 */ 2320 2321 switch (dev->device) { 2322 case PCI_DEVICE_ID_PLX_9056: 2323 #ifdef DNX_TEST_BOARD 2324 break; /* a PCIe bridge to a non PCIe device should be treated as the device */ 2325 #endif /* DNX_TEST_BOARD */ 2326 case PCI_DEVICE_ID_PLX_9656: 2327 plx_dev = 1; 2328 break; 2329 case BCM53000PCIE_DEVICE_ID: 2330 cpu_dev = 1; 2331 break; 2332 /* 2333 * The device ID for 56500, 56100 and 56300 family of devices may 2334 * be incorrect just after a PCI HW reset. It needs to be read 2335 * again after stabilization. 2336 */ 2337 case BCM56102_DEVICE_ID: 2338 case BCM56504_DEVICE_ID: 2339 case BCM56304_DEVICE_ID: 2340 case BCM56314_DEVICE_ID: 2341 case BCM56112_DEVICE_ID: 2342 update_devid = 1; 2343 break; 2344 default: 2345 break; 2346 } 2347 2348 /* Check if the device is ever probed. */ 2349 rescan_idx = _device_rescan_validate(dev); 2350 if (rescan_idx != -1) { 2351 rescan = 1; 2352 } 2353 2354 ctrl = NULL; 2355 if (plx_dev) { 2356 #if defined(BCM_PLX9656_LOCAL_BUS) 2357 /* PLX chip itself won't be part of _devices[]. */ 2358 baroff = _plx_las_bar_get(dev); 2359 if (baroff == -1) { 2360 gprintk("No Local Address Space enabled in PLX\n"); 2361 return 0; 2362 } 2363 ctrl = &plx_ctrl; 2364 num_plx++; 2365 #endif 2366 } else if (eth_dev) { 2367 if (_ether_ndevices >= LINUX_BDE_MAX_ETHER_DEVICES) { 2368 return 0;; 2369 } 2370 ctrl = _devices + _ndevices; 2371 ctrl->dev_type |= BDE_ETHER_DEV_TYPE; 2372 ctrl->iLine = dev->irq; 2373 add_dev = 1; 2374 if (debug >= 1) 2375 gprintk("Found PCI device %04x:%04x as Ethernet device\n", 2376 dev->vendor, dev->device); 2377 } else if (cpu_dev) { 2378 if (_cpu_ndevices >= LINUX_BDE_MAX_CPU_DEVICES) { 2379 return 0;; 2380 } 2381 ctrl = _devices + _ndevices; 2382 ctrl->dev_type |= BDE_CPU_DEV_TYPE; 2383 add_dev = 1; 2384 if (debug >= 1) 2385 gprintk("Found PCI device %04x:%04x as CPU device\n", 2386 dev->vendor, dev->device); 2387 } else { 2388 if (PCI_FUNC(dev->devfn) > 0) { 2389 return 0; 2390 } 2391 if (_switch_ndevices >= LINUX_BDE_MAX_SWITCH_DEVICES) { 2392 return 0; 2393 } 2394 2395 if (rescan) { 2396 if (debug >= 1) { 2397 gprintk("PCI device %04x:%04x is re-probed \n", 2398 dev->vendor, dev->device); 2399 } 2400 ctrl = _devices + rescan_idx; 2401 ctrl->dev_state = BDE_DEV_STATE_CHANGED; 2402 } else { 2403 ctrl = _devices + _ndevices; 2404 ctrl->dev_type |= BDE_SWITCH_DEV_TYPE; 2405 ctrl->domain_no = pci_domain_nr(dev->bus); 2406 ctrl->bus_no = dev->bus->number; 2407 ctrl->dev_state = BDE_DEV_STATE_NORMAL; 2408 add_dev = 1; 2409 } 2410 2411 /* Save shared BDE HAL in device structure */ 2412 MEMCPY(&ctrl->shbde, shbde, sizeof(ctrl->shbde)); 2413 2414 if (update_devid) { 2415 /* Re-read the device ID */ 2416 pci_read_config_word(dev, 2417 PCI_DEVICE_ID, 2418 &ctrl->bde_dev.device); 2419 dev->device = ctrl->bde_dev.device; 2420 } 2421 2422 if (debug >= 4) {gprintk("Enabling PCI device : vendor_id=0x%x, device_id=0x%x\n", dev->vendor, dev->device);} 2423 if (pci_enable_device(dev)) { 2424 gprintk("Cannot enable PCI device : vendor_id = %x, device_id = %x\n", 2425 dev->vendor, dev->device); 2426 } 2427 2428 /* FIXME: "workarounds" previously called "total h_acks" */ 2429 /* 2430 * These are workarounds to get around some existing 2431 * kernel problems :( 2432 */ 2433 2434 /* 2435 * While probing we determine the overall limits for the PCI 2436 * memory windows across all devices. These limits are used 2437 * later on by the PCI-PCI bridge code. 2438 */ 2439 if (pci_resource_start(dev, baroff) < _pci_mem_start) { 2440 _pci_mem_start = pci_resource_start(dev, baroff); 2441 } 2442 if (pci_resource_end(dev, baroff) > _pci_mem_end) { 2443 _pci_mem_end = pci_resource_end(dev, baroff); 2444 } 2445 2446 #ifdef CONFIG_SANDPOINT 2447 /* 2448 * Something wrong with the PCI subsystem in the mousse kernel. 2449 * The device is programmed correctly, but the irq in the pci 2450 * structure is hosed. This checks for the hosed-ness and fixes it. 2451 */ 2452 if (dev->irq > 100) { 2453 dev->irq = 2; 2454 gprintk("irq problem: setting irq = %d\n", dev->irq); 2455 } 2456 #endif 2457 2458 #ifdef CONFIG_BMW 2459 /* 2460 * PCI subsystem does not always program the system correctly. 2461 */ 2462 if (dev->irq < 16 && dev->irq != 2) { 2463 dev->irq = 2; 2464 gprintk("irq problem: setting irq = %d\n", dev->irq); 2465 } 2466 #endif 2467 2468 #ifdef CONFIG_IDT_79EB334 2469 /* 2470 * IDT kernel is not currently mapping interrupts correctly 2471 * Hardwired to core mips interrupt, irq 3 for kernel 2.4.18 2472 */ 2473 if (dev->irq != 3) { 2474 dev->irq = 3; 2475 gprintk("irq problem: setting irq = %d\n", dev->irq); 2476 } 2477 #endif 2478 2479 #ifdef CONFIG_BCM94702_CPCI 2480 /* 2481 * Hardwired to core mips interrupt irq 6 on MBZ 2482 */ 2483 if (dev->irq != 6) { 2484 dev->irq = 6; 2485 gprintk("irq problem: setting irq = %d\n", dev->irq); 2486 } 2487 #endif 2488 2489 if ((PCI_FIND_DEV(BCM4704_VENDOR_ID, BCM4704_DEVICE_ID, NULL)) != NULL) { 2490 /* 2491 * Decrease the PCI bus priority for the CPU for better overall 2492 * system performance. This change significantly reduces the 2493 * number of PCI retries from other devices on the PCI bus. 2494 */ 2495 void * _mc_vbase = IOREMAP(BCM4704_MEMC_BASE, 0x1000); 2496 int priorinv = 0x80; 2497 static int done = 0; 2498 if (!done) { 2499 done = 1; 2500 writel(priorinv, _mc_vbase + BCM4704_MEMC_PRIORINV); 2501 if (debug >= 1) 2502 gprintk("set BCM4704 PriorInvTim register to 0x%x\n", priorinv); 2503 iounmap(_mc_vbase); 2504 } 2505 } 2506 2507 if ((PCI_FIND_DEV(SIBYTE_PCI_VENDOR_ID, SIBYTE_PCI_DEVICE_ID, NULL)) != NULL) { 2508 /* 2509 * The BCM91125CPCI CPU boards with a PCI-PCI bridge use the same 2510 * interrupt line for all switch ships behind the bridge. 2511 */ 2512 if (PCI_FIND_DEV(DC21150_VENDOR_ID, DC21150_DEVICE_ID, NULL) || 2513 PCI_FIND_DEV(HINT_HB4_VENDOR_ID, HINT_HB4_DEVICE_ID, NULL) || 2514 PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)) { 2515 /* 2516 * By default we try to guess the correct IRQ based on the design. 2517 * For now we only look at the bridge vendor, but it may be necessary 2518 * to look at the switch chip configuration as well. 2519 */ 2520 if (forceirq == -1) { 2521 if ((PCI_FIND_DEV(HINT_HB4_VENDOR_ID, HINT_HB4_DEVICE_ID, NULL)) || 2522 ((dev->device == BCM5674_DEVICE_ID) && 2523 (PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)))) { 2524 forceirq = 58; 2525 } else { 2526 forceirq = 56; 2527 } 2528 } 2529 } 2530 } 2531 2532 if (((PCI_FIND_DEV(BCM58525_PCI_VENDOR_ID, BCM58525_PCI_DEVICE_ID, NULL)) != NULL) || 2533 ((PCI_FIND_DEV(BCM58525_PCI_VENDOR_ID, BCM58522_PCI_DEVICE_ID, NULL)) != NULL) || 2534 ((PCI_FIND_DEV(BCM58712_PCI_VENDOR_ID, BCM58712_PCI_DEVICE_ID, NULL)) != NULL) ) { 2535 /* BCM58525/BCM58712 CPU boards support 128 Max payload size */ 2536 if (maxpayload && maxpayload != 128) { 2537 maxpayload = 128; 2538 if (debug >= 1) gprintk("force max payload size to 128\n"); 2539 } 2540 } 2541 2542 if (forceirq > 0 && dev->irq != (uint32) forceirq) { 2543 if (forceirqubm & (1U << (_ndevices - 1))) { 2544 dev->irq = forceirq; 2545 if (debug >= 1) gprintk("force irq to %d\n", forceirq); 2546 } 2547 } else if (debug >= 1) gprintk("found irq %d\n", dev->irq); 2548 2549 ctrl->iLine = dev->irq; 2550 if (unlikely(debug > 1)) 2551 gprintk("%s:irq = %d\n",__func__, ctrl->iLine); 2552 2553 if (shbde_pci_is_pcie(shbde, dev)) { 2554 /* Set PCIe max payload */ 2555 shbde_pci_max_payload_set(shbde, dev, maxpayload); 2556 } else { 2557 /* Set PCI retry to infinite on non-PCIe switch device */ 2558 pci_write_config_word(dev, 0x40, 0x0080); 2559 if (debug >= 1) gprintk("set DMA retry to infinite on switch device\n"); 2560 } 2561 } 2562 2563 #if defined(BCM_DFE_SUPPORT) 2564 switch (dev->device) { 2565 case BCM88750_DEVICE_ID: 2566 case BCM88753_DEVICE_ID: 2567 case BCM88755_DEVICE_ID: 2568 case BCM88770_DEVICE_ID: 2569 case BCM88773_DEVICE_ID: 2570 case BCM88774_DEVICE_ID: 2571 case BCM88775_DEVICE_ID: 2572 case BCM88776_DEVICE_ID: 2573 case BCM88777_DEVICE_ID: 2574 case BCM88950_DEVICE_ID: 2575 case BCM88953_DEVICE_ID: 2576 case BCM88954_DEVICE_ID: 2577 case BCM88955_DEVICE_ID: 2578 case BCM88956_DEVICE_ID: 2579 case BCM88752_DEVICE_ID: 2580 case BCM88772_DEVICE_ID: 2581 case BCM88952_DEVICE_ID: 2582 2583 /* 2584 * For DMA transactions - set Max_Payload_Size and 2585 * Max_Read_Request_Size to 128 bytes. 2586 */ 2587 pci_write_config_byte(dev, 0xb5, 0x0c); 2588 pci_write_config_byte(dev, 0xb4, 0x0); 2589 break; 2590 default: 2591 break; 2592 } 2593 #endif /* BCM_DFE_SUPPORT */ 2594 2595 /* Prevent compiler warning */ 2596 if (ctrl == NULL) { 2597 return 0; 2598 } 2599 2600 ctrl->be_pio = 0; 2601 ctrl->dev_type |= BDE_PCI_DEV_TYPE; 2602 ctrl->pci_device = dev; 2603 pci_set_drvdata(dev, ctrl); 2604 2605 /* 2606 * Sample setting of unique ID, used the PCIe address of the device: 2607 * domain, bus, slot, function in hex digits: DDDDBBSS (SS includes the slot/device and function. 2608 * Tested with old kernels from 2.6 . 2609 * Do not use the PCI_DEVID macro which old kernel versions don't have. */ 2610 ctrl->bde_dev.dev_unique_id = dev->bus ? 2611 (((uint32)pci_domain_nr(dev->bus)) << 16) ^ (((uint32)dev->bus->number) << 8) ^ dev->devfn : 2612 dev->devfn; 2613 2614 /* Check for iProc device */ 2615 if (shbde_pci_is_iproc(shbde, dev, &cmic_bar)) { 2616 iproc = 1; 2617 if (cmic_bar >= 0) { 2618 baroff = cmic_bar; 2619 } 2620 } 2621 #ifdef DNX_TEST_BOARD 2622 else if (dev->device == PLX9056_DEVICE_ID && baroff == 0) { 2623 baroff = 2; 2624 ctrl->dev_type |= BDE_NO_IPROC/* | BDE_BYTE_SWAP*/; 2625 } 2626 #endif /* DNX_TEST_BOARD */ 2627 2628 /* Get the device revision */ 2629 pci_read_config_byte(dev, PCI_REVISION_ID, &ctrl->bde_dev.rev); 2630 2631 /* Map in the device */ 2632 ctrl->bde_dev.device = dev->device; 2633 paddr = pci_resource_start(dev, baroff); 2634 2635 switch (dev->device) { 2636 #if defined(BCM_PETRA_SUPPORT) && defined(__DUNE_LINUX_BCM_CPU_PCIE__) 2637 case GEDI_DEVICE_ID: 2638 case PCP_PCI_DEVICE_ID: 2639 bar_len = 0x1000000; 2640 break; 2641 #endif 2642 default: 2643 bar_len = pci_resource_len(dev, baroff); 2644 break; 2645 } 2646 2647 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(paddr, bar_len); 2648 ctrl->iowin[0].addr = paddr; 2649 ctrl->iowin[0].size = bar_len; 2650 2651 if (debug >= 3) { 2652 gprintk("BAR %d: kernel addr:0x%lx phys addr:0x%lx length:%lx\n", 2653 baroff, (unsigned long)ctrl->bde_dev.base_address, (unsigned long)paddr, (unsigned long)bar_len); 2654 } 2655 2656 /* Map secondary address spaces */ 2657 for (i = 1; i < BDE_NUM_IOWIN_MAX; i++) { 2658 ctrl->iowin[i].addr = 0; 2659 ctrl->iowin[i].size = 0; 2660 } 2661 ctrl->bde_dev.base_address1 = 0; 2662 2663 if (iproc 2664 #ifdef DNX_TEST_BOARD 2665 || (dev->device == PLX9056_DEVICE_ID && baroff == 2) 2666 #endif /* DNX_TEST_BOARD */ 2667 ) { 2668 paddr = pci_resource_start(dev, 0); 2669 bar_len = pci_resource_len(dev, 0); 2670 ctrl->bde_dev.base_address1 = (sal_vaddr_t)IOREMAP(paddr, bar_len); 2671 ctrl->iowin[1].addr = paddr; 2672 ctrl->iowin[1].size = bar_len; 2673 if (debug >= 3) { 2674 gprintk("BAR 0: kernel addr:0x%lx phys addr:0x%lx length:%lx\n", 2675 (unsigned long)ctrl->bde_dev.base_address1, (unsigned long)paddr, (unsigned long)bar_len); 2676 } 2677 } 2678 2679 /* configure interrupt type */ 2680 config_pci_intr_type(dev, ctrl, iproc); 2681 2682 /* Configure iProc PCI-AXI bridge */ 2683 if (iproc && ctrl->bde_dev.base_address1) { 2684 void *iproc_regs; 2685 shbde_iproc_config_t *icfg = &shbde->icfg; 2686 2687 /* Mapped iProc regs in PCI BAR 0 */ 2688 iproc_regs = (void *)ctrl->bde_dev.base_address1; 2689 2690 /* iProc configuration parameters */ 2691 (void)shbde_pci_iproc_version_get(shbde, dev, &icfg->iproc_ver, 2692 &icfg->cmic_ver, &icfg->cmic_rev); 2693 shbde_iproc_config_init(icfg, ctrl->bde_dev.device, ctrl->bde_dev.rev); 2694 2695 if (debug >= 2) { 2696 gprintk("iproc version = %x dma_hi_bits = %x\n", icfg->iproc_ver, icfg->dma_hi_bits); 2697 } 2698 icfg->use_msi = ctrl->use_msi; 2699 2700 /* Call shared function */ 2701 paxb_core = shbde_iproc_paxb_init(shbde, iproc_regs, icfg); 2702 2703 /* Save PCI core information for CMIC */ 2704 if (paxb_core == 1) { 2705 ctrl->dev_type |= BDE_DEV_BUS_ALT; 2706 } 2707 2708 /* Save MSI enable state information */ 2709 if (ctrl->use_msi) { 2710 ctrl->dev_type |= BDE_DEV_BUS_MSI; 2711 } 2712 2713 /* iProc PCIe preemphasis */ 2714 shbde_iproc_pcie_preemphasis_set(shbde, iproc_regs, icfg, dev); 2715 } 2716 2717 /* Save shared BDE HAL in device structure */ 2718 MEMCPY(&ctrl->shbde, shbde, sizeof(ctrl->shbde)); 2719 2720 2721 ctrl->isr = NULL; 2722 ctrl->isr_data = NULL; 2723 2724 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2725 if (!(cmd & PCI_COMMAND_MEMORY) || !(cmd & PCI_COMMAND_MASTER)) { 2726 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 2727 pci_write_config_word(dev, PCI_COMMAND, cmd); 2728 if (debug >= 1) gprintk("enable PCI resources 0x%x (PCI_COMMAND)\n", cmd); 2729 } 2730 2731 /* Check if we need 256 KB memory window (default is 64 KB) */ 2732 bar_len = pci_resource_len(dev, baroff); 2733 if (bar_len == 0x40000) { 2734 ctrl->dev_type |= BDE_256K_REG_SPACE; 2735 if (debug >= 1) gprintk("PCI resource len 256K\n"); 2736 } else if (bar_len == 0x800000) { 2737 ctrl->dev_type |= BDE_256K_REG_SPACE | BDE_8MB_REG_SPACE; 2738 if (debug >= 1) gprintk("PCI resource len 8MB\n"); 2739 } 2740 2741 2742 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 2743 ctrl->dma_dev = &dev->dev; 2744 #endif 2745 2746 if (debug >= 2) { 2747 gprintk("_pci_probe: configured dev:0x%x rev:0x%x with base_addresses: 0x%lx 0x%lx\n", 2748 (unsigned)ctrl->bde_dev.device, (unsigned)ctrl->bde_dev.rev, 2749 (unsigned long)ctrl->bde_dev.base_address, (unsigned long)ctrl->bde_dev.base_address1); 2750 } 2751 2752 if (add_dev) { 2753 _bde_add_device(); 2754 } 2755 /* Let's boogie */ 2756 return 0; 2757 } 2758 2759 /* 2760 * Function: _pci_remove 2761 * 2762 * Purpose: 2763 * Detach driver from device. Called from pci_unregister_driver(). 2764 * Parameters: 2765 * dev - Linux PCI device structure 2766 * Returns: 2767 * 0 2768 */ 2769 static void 2770 _pci_remove(struct pci_dev* dev) 2771 { 2772 bde_ctrl_t *ctrl; 2773 2774 if (nodevices == 1) { 2775 return; 2776 } 2777 2778 #if defined(BCM_DFE_SUPPORT) 2779 if (dev->device == PCI_DEVICE_ID_PLX_9056) { 2780 return; 2781 } 2782 #endif 2783 2784 ctrl = (bde_ctrl_t *) pci_get_drvdata(dev); 2785 2786 if (ctrl == NULL) { 2787 /* Unused device */ 2788 return; 2789 } 2790 ctrl->dev_state = BDE_DEV_STATE_REMOVED; 2791 if (debug >= 1) { 2792 gprintk("PCI device %04x:%04x is removed. \n", 2793 dev->vendor, dev->device); 2794 } 2795 if (ctrl->bde_dev.base_address1) { 2796 iounmap((void *)ctrl->bde_dev.base_address1); 2797 } 2798 if (ctrl->bde_dev.base_address) { 2799 iounmap((void *)ctrl->bde_dev.base_address); 2800 } 2801 2802 /* Free our interrupt handler, if we have one */ 2803 if (ctrl->isr || ctrl->isr2) { 2804 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2805 if (ctrl->use_msi >= PCI_USE_INT_MSIX) { 2806 int i; 2807 for (i = 0; i < ctrl->msix_cnt; i++) 2808 free_irq(ctrl->entries[i].vector, ctrl); 2809 } 2810 else 2811 #endif 2812 { 2813 free_irq(ctrl->iLine, ctrl); 2814 } 2815 } 2816 #ifdef CONFIG_PCI_MSI 2817 _msi_disconnect(ctrl); 2818 #endif 2819 ctrl->isr = NULL; 2820 ctrl->isr_data = NULL; 2821 ctrl->isr2 = NULL; 2822 ctrl->isr2_data = NULL; 2823 } 2824 2825 static struct pci_driver _device_driver = { 2826 probe: _pci_probe, 2827 remove: _pci_remove, 2828 id_table: _id_table, 2829 /* The rest are dynamic */ 2830 }; 2831 2832 static void 2833 _spi_device_setup(void) { 2834 bde_ctrl_t *ctrl; 2835 ctrl = _devices + _ndevices; 2836 ctrl->dev_type |= BDE_SWITCH_DEV_TYPE; 2837 ctrl->iLine = 0xa3; 2838 ctrl->be_pio = 0; 2839 ctrl->dev_type |= BDE_SPI_DEV_TYPE; 2840 ctrl->bde_dev.device = spi_devid; 2841 ctrl->bde_dev.rev = spi_revid; 2842 if (debug >= 1) { 2843 gprintk("SPI Slave Mode: force ctrl->bde_dev.device=0x%x\n",ctrl->bde_dev.device); 2844 gprintk("SPI Slave Mode: force ctrl->bde_dev.rev=0x%x\n",ctrl->bde_dev.rev); 2845 gprintk("SPI Slave Mode: force ctrl->dev_type=0x%x\n",ctrl->dev_type); 2846 } 2847 _bde_add_device(); 2848 } 2849 #endif /* BCM_ICS */ 2850 2851 2852 2853 2854 #if defined(BCM_METROCORE_LOCAL_BUS) 2855 static bde_ctrl_t* 2856 map_local_bus(uint64_t addr, uint32_t size) 2857 { 2858 bde_ctrl_t *ctrl; 2859 2860 ctrl = _devices + _ndevices; 2861 2862 /* 2863 * For now: use EB type as `local bus' 2864 * (memory mapped, no DMA, no interrupts) 2865 * metrocore local bus supports interrupts, but we don't use them. 2866 */ 2867 ctrl->dev_type |= BDE_EB_DEV_TYPE | BDE_SWITCH_DEV_TYPE 2868 | (size > 64 * 1024 ? BDE_128K_REG_SPACE : 0); 2869 ctrl->pci_device = NULL; /* No PCI bus */ 2870 2871 /* Map in the device */ 2872 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(addr, size); 2873 ctrl->iowin[0].addr = addr; 2874 ctrl->iowin[0].size = size; 2875 2876 _bde_add_device(); 2877 return(ctrl); 2878 } 2879 2880 #define BME_REVISION_OFFSET (0x0) 2881 2882 #endif 2883 2884 #ifdef BCM_PLX9656_LOCAL_BUS 2885 2886 #if 1 2887 #define DEV_REG_BASE_OFFSET PL0_OFFSET /* Polaris register base */ 2888 #define DEV_REG_DEVID 0 /* Device ID is first register */ 2889 #endif 2890 2891 /* 2892 * The difference at map_local_bus2: 2893 * 2894 * The PLX9656 PCI-to-LOCAL bridge chip already has been iomapped the 2895 * whole address space. So the devices off local bus don't need to be 2896 * mapped again. They only need to claim their own sub-space. 2897 */ 2898 static bde_ctrl_t * 2899 map_local_bus2(bde_ctrl_t *plx_ctrl, uint32_t dev_base, uint32_t size) 2900 { 2901 uint32_t dev_rev_id; 2902 uint8_t *addr; 2903 bde_ctrl_t *ctrl; 2904 2905 ctrl = _devices + _ndevices; 2906 2907 /* 2908 * For now: use EB type as `local bus' 2909 * (memory mapped, no DMA, no interrupts) 2910 * metrocore local bus supports interrupts, but we don't use them. 2911 */ 2912 ctrl->dev_type |= BDE_EB_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 2913 ctrl->dev_type |= BDE_320K_REG_SPACE; /* Polaris 18 bits address + FPGA */ 2914 ctrl->pci_device = NULL; /* No PCI bus */ 2915 2916 /* Map in the device */ 2917 ctrl->bde_dev.base_address = plx_ctrl->bde_dev.base_address + dev_base; 2918 ctrl->iowin[0].addr = plx_ctrl->iowin[0].addr + (resource_size_t)dev_base; 2919 ctrl->iowin[0].size = size; 2920 2921 #if 1 2922 addr = (uint8_t *)ctrl->bde_dev.base_address + PL0_REVISION_REG; 2923 #endif 2924 dev_rev_id = readl(addr); 2925 ctrl->bde_dev.device = dev_rev_id >> 16; 2926 ctrl->bde_dev.rev = (dev_rev_id & 0xFF); 2927 2928 2929 _bde_add_device(); 2930 2931 switch (ctrl->bde_dev.device) { 2932 default: 2933 return 0; 2934 } 2935 return(ctrl); 2936 } 2937 2938 static int 2939 probe_plx_local_bus(void) 2940 { 2941 bde_ctrl_t *ctrl; 2942 uint32_t val; 2943 uint8_t *addr; 2944 char addr_hi_str[16]; 2945 2946 if (num_plx > 1) { 2947 printk(KERN_ERR "There's more than one PLX 9656/9056 chip\n"); 2948 return -1; 2949 } 2950 addr_hi_str[0] = 0; 2951 #ifdef PHYS_ADDR_IS_64BIT 2952 sprintf(addr_hi_str, "%08x", (uint32_t)(plx_ctrl.iowin[0].addr >> 32)); 2953 #endif 2954 printk(KERN_ERR "Found PLX %04x:%04x vir: 0x%08x phy: 0x%s%08x\n", 2955 plx_ctrl.bde_dev.device, plx_ctrl.bde_dev.rev, 2956 plx_ctrl.bde_dev.base_address, addr_hi_str, 2957 (uint32_t)(plx_ctrl.iowin[0].addr)); 2958 2959 addr = (uint8_t *)plx_ctrl.bde_dev.base_address + CPLD_OFFSET + CPLD_REVISION_REG; 2960 val = readl(addr); 2961 printk(KERN_ERR "plx: CPLD revision %d\n", val & CPLD_REVISION_MASK); 2962 #if 000 2963 addr = (uint8_t *)plx_ctrl.bde_dev.base_address + CPLD_OFFSET + CPLD_RESET_REG; 2964 writel(CPLD_RESET_NONE, addr); 2965 #endif 2966 #if 1 2967 ctrl = map_local_bus2(&plx_ctrl, PL0_OFFSET, PL0_SIZE); 2968 #endif 2969 if (ctrl == 0) 2970 return -1; 2971 2972 /* Uses PLX IRQ for Polaris LC */ 2973 ctrl->iLine = 48; 2974 ctrl->isr = NULL; 2975 ctrl->isr_data = NULL; 2976 2977 return 0; 2978 } 2979 2980 #endif /* BCM_PLX9656_LOCAL_BUS */ 2981 2982 2983 2984 2985 /* 2986 * Generic module functions 2987 */ 2988 2989 /* 2990 * Function: _init 2991 * 2992 * Purpose: 2993 * Module initialization. 2994 * Attaches to kernel BDE. 2995 * Parameters: 2996 * None 2997 * Returns: 2998 * 0 on success, < 0 on error. 2999 */ 3000 static int 3001 _init(void) 3002 { 3003 #ifdef IPROC_CMICD 3004 #ifdef CONFIG_OF 3005 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 3006 iproc_platform_driver_register(&iproc_cmicd_driver); 3007 } else 3008 #endif 3009 if (iproc_has_cmicd()) { 3010 iproc_cmicd_get_memregion(&iproc_cmicd_resources[IPROC_CMICD_RES_MEM]); 3011 iproc_platform_driver_register(&iproc_cmicd_driver); 3012 #ifdef CONFIG_OF 3013 if (!of_find_compatible_node(NULL, NULL, IPROC_CMICD_COMPATIBLE)) 3014 #endif 3015 { 3016 /* Register platform device if no device node in dtb */ 3017 iproc_platform_device_register(&iproc_cmicd_pdev); 3018 } 3019 } 3020 #endif /* IPROC_CMICD */ 3021 3022 #ifdef BCM_ICS 3023 _ics_bde_create(); 3024 #else /* PCI */ 3025 /* Register our goodies */ 3026 _device_driver.name = LINUX_KERNEL_BDE_NAME; 3027 3028 3029 /* Configure MSI interrupt support */ 3030 use_msi = usemsi; 3031 3032 #ifdef CONFIG_PCI_MSI 3033 if (use_msi == PCI_USE_INT_NONE) { 3034 /* Compilation flag determines default value */ 3035 #ifdef BDE_LINUX_USE_MSIX_INTERRUPT 3036 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 3037 use_msi = PCI_USE_INT_MSIX; 3038 #else 3039 use_msi = PCI_USE_INT_MSI; 3040 #endif 3041 #elif defined(BDE_LINUX_USE_MSI_INTERRUPT) 3042 use_msi = PCI_USE_INT_MSI; 3043 #else 3044 use_msi = PCI_USE_INT_INTX; 3045 #endif 3046 } 3047 #else 3048 if (use_msi > PCI_USE_INT_INTX) { 3049 /* Warn if invalid configuration */ 3050 gprintk("MSI interrupts not supported by kernel\n"); 3051 } 3052 use_msi = PCI_USE_INT_INTX; 3053 #endif /* CONFIG_PCI_MSI */ 3054 3055 if (unlikely(debug >= 1)) 3056 gprintk("%s(%d):use_msi = %d\n", __func__, __LINE__, use_msi); 3057 if (spi_devid) { 3058 _spi_device_setup(); 3059 } else { 3060 if (pci_register_driver(&_device_driver) < 0) { 3061 return -ENODEV; 3062 } 3063 } 3064 3065 /* Note: PCI-PCI bridge uses results from pci_register_driver */ 3066 p2p_bridge(); 3067 3068 #ifdef BCM_METROCORE_LOCAL_BUS 3069 if (probe_metrocore_local_bus()) { 3070 return -1; 3071 } 3072 #endif 3073 #ifdef BCM_PLX9656_LOCAL_BUS 3074 if (num_plx > 0) { 3075 probe_plx_local_bus(); 3076 } 3077 #endif 3078 #endif /* BCM_ICS */ 3079 3080 3081 #ifdef BCM_SAND_SUPPORT 3082 sand_device_create(); 3083 #endif 3084 3085 /* 3086 * Probe for EB Bus devices. 3087 */ 3088 if (eb_bus) { 3089 char *tok; 3090 uint irq = -1, eb_rd16bit=0, eb_wr16bit =0; 3091 unsigned int eb_ba = 0x0; 3092 3093 gprintk("EB bus info: %s\n", eb_bus); 3094 tok = strtok(eb_bus,","); 3095 while (tok) { 3096 _parse_eb_args(tok, "BA=%x IRQ=%d RD16=%d WR16=%d", 3097 &eb_ba, &irq, &eb_rd16bit, &eb_wr16bit); 3098 _eb_device_create(eb_ba, irq, eb_rd16bit, eb_wr16bit); 3099 tok = strtok(NULL,","); 3100 } 3101 } 3102 3103 return 0; 3104 } 3105 3106 /* 3107 * Function: _cleanup 3108 * 3109 * Purpose: 3110 * Module cleanup function. 3111 * Parameters: 3112 * None 3113 * Returns: 3114 * Always 0 3115 */ 3116 static int 3117 _cleanup(void) 3118 { 3119 int i; 3120 3121 _dma_cleanup(); 3122 3123 #ifdef IPROC_CMICD 3124 #ifdef CONFIG_OF 3125 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 3126 iproc_platform_driver_unregister(&iproc_cmicd_driver); 3127 } else 3128 #endif 3129 if (iproc_has_cmicd()) { 3130 #ifdef CONFIG_OF 3131 if (!of_find_compatible_node(NULL, NULL, IPROC_CMICD_COMPATIBLE)) 3132 #endif 3133 { 3134 iproc_platform_device_unregister(&iproc_cmicd_pdev); 3135 } 3136 iproc_platform_driver_unregister(&iproc_cmicd_driver); 3137 } 3138 #endif 3139 3140 for (i = 0; i < _ndevices; i++) { 3141 bde_ctrl_t *ctrl = _devices + i; 3142 3143 /* free allocated kernel space memory */ 3144 if (ctrl->dev_type & BDE_SPI_DEV_TYPE) { 3145 if (ctrl->spi_device) { 3146 kfree(ctrl->spi_device); 3147 } 3148 } 3149 } 3150 #if defined(BCM_SAND_SUPPORT) && (defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__)) 3151 if (cpu_address) { /* unmap CPU card MMIO */ 3152 iounmap(cpu_address); 3153 cpu_address = NULL; 3154 } 3155 #endif 3156 3157 #ifdef BCM_ICS 3158 #else 3159 pci_unregister_driver(&_device_driver); 3160 #endif /* BCM_ICS */ 3161 return 0; 3162 } 3163 3164 /* 3165 * Function: _pprint 3166 * 3167 * Purpose: 3168 * Print proc filesystem information. 3169 * Parameters: 3170 * None 3171 * Returns: 3172 * Always 0 3173 */ 3174 static int 3175 _pprint(void) 3176 { 3177 int i = 0; 3178 3179 pprintf("Broadcom Device Enumerator (%s)\n", LINUX_KERNEL_BDE_NAME); 3180 3181 pprintf("Module parameters:\n"); 3182 pprintf("\tmaxpayload=%d\n", maxpayload); 3183 pprintf("\tusemsi=%d\n", usemsi); 3184 3185 _dma_pprint(); 3186 3187 if (_ndevices == 0) { 3188 pprintf("No devices found\n"); 3189 } else { 3190 pprintf("Devices:\n"); 3191 } 3192 for (i = 0; i < _ndevices; i++) { 3193 bde_ctrl_t *ctrl = _devices + i; 3194 3195 if (ctrl->dev_type & BDE_SWITCH_DEV_TYPE) { 3196 pprintf("\t%d (swi) : ", i); 3197 } else if (ctrl->dev_type & BDE_ETHER_DEV_TYPE) { 3198 pprintf("\t%d (eth) : ", i); 3199 } else if (ctrl->dev_type & BDE_CPU_DEV_TYPE) { 3200 pprintf("\t%d (cpu) : ", i); 3201 } else { 3202 pprintf("\t%d (?) : ", i); 3203 } 3204 3205 if (ctrl->dev_state == BDE_DEV_STATE_REMOVED) { 3206 pprintf("PCI device 0x%x:0x%x:%d REMOVED\n", 3207 ctrl->pci_device->vendor, 3208 ctrl->pci_device->device, 3209 ctrl->bde_dev.rev); 3210 continue; 3211 } 3212 if (ctrl->dev_type & BDE_PCI_DEV_TYPE) { 3213 pprintf("PCI device %02x:%02x.%x 0x%x:0x%x:%d:0x%.8lx:0x%.8lx:%d%s\n", 3214 (unsigned int)ctrl->pci_device->bus->number, 3215 PCI_SLOT(ctrl->pci_device->devfn), 3216 PCI_FUNC(ctrl->pci_device->devfn), 3217 ctrl->pci_device->vendor, 3218 ctrl->pci_device->device, 3219 ctrl->bde_dev.rev, 3220 (unsigned long)pci_resource_start(ctrl->pci_device, 0), 3221 (unsigned long)pci_resource_start(ctrl->pci_device, 2), 3222 ctrl->pci_device->irq, 3223 ctrl->use_msi ? " (MSI)" : ""); 3224 } else if (ctrl->dev_type & BDE_SPI_DEV_TYPE) { 3225 pprintf("SPI Device %d:%x:%x:0x%x:0x%x:%d\n", 3226 ctrl->spi_device->cid, 3227 ctrl->spi_device->part, 3228 ctrl->spi_device->rev, 3229 ctrl->spi_device->phyid_high, 3230 ctrl->spi_device->phyid_low, 3231 ctrl->bde_dev.rev); 3232 } else if (ctrl->dev_type & BDE_ICS_DEV_TYPE) { 3233 pprintf("ICS Device 0x%x:0x%x\n", 3234 ctrl->bde_dev.device, 3235 ctrl->bde_dev.rev); 3236 } else if (ctrl->dev_type & BDE_AXI_DEV_TYPE) { 3237 pprintf("AXI Device 0x%x:0x%x:0x%.8lx:%d\n", 3238 ctrl->bde_dev.device, 3239 ctrl->bde_dev.rev, 3240 (unsigned long)ctrl->iowin[0].addr, 3241 ctrl->iLine); 3242 } else if (ctrl->dev_type & BDE_EB_DEV_TYPE) { 3243 pprintf("EB Bus Device 0x%x:0x%x\n", 3244 ctrl->bde_dev.device, 3245 ctrl->bde_dev.rev); 3246 } 3247 if (debug >= 1) { 3248 pprintf("\t\timask:imask2:fmask 0x%x:0x%x:0x%x\n", 3249 ctrl->imask, 3250 ctrl->imask2, 3251 ctrl->fmask); 3252 } 3253 } 3254 return 0; 3255 } 3256 /* 3257 * Some kernels are configured to prevent mapping of kernel RAM memory 3258 * into user space via the /dev/mem device. 3259 * 3260 * The function below provides a backdoor to map IO and DMA memory to 3261 * user space via the BDE device file. 3262 */ 3263 static int 3264 _bde_mmap(struct file *filp, struct vm_area_struct *vma) 3265 { 3266 unsigned long paddr = vma->vm_pgoff << PAGE_SHIFT; 3267 unsigned long size = vma->vm_end - vma->vm_start; 3268 int i, j, pio_range_valid = 0; 3269 3270 for(i = 0; i < _ndevices; i++) { 3271 bde_ctrl_t *ctrl = _devices + i; 3272 if (ctrl->dev_type & BDE_SWITCH_DEV_TYPE) { 3273 for (j = 0; j < BDE_NUM_IOWIN_MAX; j++) { 3274 if (paddr >= (unsigned long)ctrl->iowin[j].addr && 3275 (paddr + size) <= (unsigned long)(ctrl->iowin[j].addr + ctrl->iowin[j].size)) { 3276 pio_range_valid = 1; 3277 break; 3278 } 3279 if ((ctrl->dev_type & BDE_AXI_DEV_TYPE) && (paddr == ctrl->iowin[j].addr)) { 3280 pio_range_valid = 1; 3281 break; 3282 } 3283 } 3284 } 3285 } 3286 3287 if (pio_range_valid) { 3288 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3289 3290 if (remap_pfn_range(vma, 3291 vma->vm_start, 3292 vma->vm_pgoff, 3293 size, 3294 vma->vm_page_prot)) { 3295 gprintk("Failed to mmap phys range 0x%lx-0x%lx to 0x%lx-0x%lx\n", 3296 paddr, paddr + size, vma->vm_start,vma->vm_end); 3297 return -EAGAIN; 3298 } 3299 return 0; 3300 } 3301 3302 return _dma_mmap(filp, vma); 3303 } 3304 3305 /* Workaround for broken Busybox/PPC insmod */ 3306 static char _modname[] = LINUX_KERNEL_BDE_NAME; 3307 3308 static gmodule_t _gmodule = { 3309 name: LINUX_KERNEL_BDE_NAME, 3310 major: LINUX_KERNEL_BDE_MAJOR, 3311 init: _init, 3312 cleanup: _cleanup, 3313 pprint: _pprint, 3314 mmap: _bde_mmap, 3315 }; 3316 3317 gmodule_t * 3318 gmodule_get(void) 3319 { 3320 _gmodule.name = _modname; 3321 return &_gmodule; 3322 } 3323 3324 3325 /* 3326 * BDE Interface 3327 */ 3328 3329 static const char * 3330 _name(void) 3331 { 3332 return LINUX_KERNEL_BDE_NAME; 3333 } 3334 3335 static int 3336 _num_devices(int type) 3337 { 3338 switch (type) { 3339 case BDE_ALL_DEVICES: 3340 return _ndevices; 3341 case BDE_SWITCH_DEVICES: 3342 return _switch_ndevices; 3343 case BDE_ETHER_DEVICES: 3344 return _ether_ndevices; 3345 case BDE_CPU_DEVICES: 3346 return _cpu_ndevices; 3347 } 3348 3349 return 0; 3350 } 3351 3352 static const ibde_dev_t * 3353 _get_dev(int d) 3354 { 3355 if (!VALID_DEVICE(d)) { 3356 gprintk("_get_dev: Invalid device index %d\n", d); 3357 return NULL; 3358 } 3359 3360 return &_devices[d].bde_dev; 3361 } 3362 3363 static uint32 3364 _get_dev_type(int d) 3365 { 3366 if (!VALID_DEVICE(d)) { 3367 gprintk("_get_dev: Invalid device index %d\n", d); 3368 return 0; 3369 } 3370 3371 return _devices[d].dev_type; 3372 } 3373 3374 static uint32 3375 _pci_conf_read(int d, uint32 addr) 3376 { 3377 #ifdef BCM_ICS 3378 return 0xFFFFFFFF; 3379 #else 3380 uint32 rc = 0; 3381 3382 if (!VALID_DEVICE(d)) { 3383 gprintk("_pci_conf_read: Invalid device index %d\n", d); 3384 return 0xFFFFFFFF; 3385 } 3386 3387 if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { 3388 gprintk("_pci_conf_read: Not PCI device %d, type %x\n", 3389 d, _devices[d].dev_type); 3390 return 0xFFFFFFFF; 3391 } 3392 3393 pci_read_config_dword(_devices[d].pci_device, addr, &rc); 3394 return rc; 3395 #endif /* BCM_ICS */ 3396 } 3397 3398 static int 3399 _pci_conf_write(int d, uint32 addr, uint32 data) 3400 { 3401 #ifdef BCM_ICS 3402 return -1; 3403 #else 3404 if (!VALID_DEVICE(d)) { 3405 gprintk("_pci_conf_write: Invalid device index %d\n", d); 3406 return -1; 3407 } 3408 3409 if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { 3410 gprintk("_pci_conf_write: Not PCI device %d, type %x\n", 3411 d, _devices[d].dev_type); 3412 return -1; 3413 } 3414 3415 pci_write_config_dword(_devices[d].pci_device, addr, data); 3416 return 0; 3417 #endif /* BCM_ICS */ 3418 } 3419 3420 /* Initialized when the bde is created */ 3421 static linux_bde_bus_t _bus; 3422 3423 static void 3424 _pci_bus_features(int unit, int *be_pio, int *be_packet, int *be_other) 3425 { 3426 if ((_devices[unit].bde_dev.device & 0xFF00) != 0x5600 && 3427 (_devices[unit].bde_dev.device & 0xF000) != 0xc000 && 3428 (_devices[unit].bde_dev.device & 0xF000) != 0xb000 && 3429 (_devices[unit].bde_dev.device & 0xF000) != 0x8000 && 3430 (_devices[unit].bde_dev.device & 0xFFF0) != 0x0230 && 3431 (_devices[unit].bde_dev.device & 0xFFF0) != 0xa440) { 3432 if (be_pio) *be_pio = 0; 3433 if (be_packet) *be_packet = 0; 3434 if (be_other) *be_other = 0; 3435 } else { 3436 if (be_pio) *be_pio = _bus.be_pio; 3437 if (be_packet) *be_packet = _bus.be_packet; 3438 if (be_other) *be_other = _bus.be_other; 3439 } 3440 #if defined(BCM_METROCORE_LOCAL_BUS) 3441 if (_devices[unit].dev_type & BDE_EB_DEV_TYPE && be_pio) { 3442 *be_pio = 1; 3443 } 3444 #endif 3445 3446 } 3447 3448 static uint32_t 3449 _read(int d, uint32_t addr) 3450 { 3451 unsigned long flags; 3452 volatile uint16 msb, lsb; 3453 uint32 sl_addr, data; 3454 3455 if (!VALID_DEVICE(d)) { 3456 return -1; 3457 } 3458 3459 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3460 return -1; 3461 } 3462 3463 if (_devices[d].dev_type & BDE_DEV_BUS_RD_16BIT) { 3464 /* 3465 * Adjust the address presented to Eb slave. Move A15:A0 to A16:A1. 3466 */ 3467 sl_addr = (addr & 0xffff0000) | ((addr & 0xffff) << 1); 3468 /* Disable interrupts */ 3469 spin_lock_irqsave(&bus_lock, flags); 3470 3471 lsb = *((uint16 *)(_devices[d].bde_dev.base_address + sl_addr)); 3472 msb = *((uint16 *)(_devices[d].bde_dev.base_address + sl_addr)); 3473 spin_unlock_irqrestore(&bus_lock, flags); 3474 3475 return (msb << 16) | lsb; 3476 } else { 3477 data = ((VOL uint32_t *)_devices[d].bde_dev.base_address)[addr / 4]; 3478 #if defined(CMIC_SOFT_BYTE_SWAP) 3479 data = CMIC_SWAP32(data); 3480 #endif 3481 return data; 3482 } 3483 } 3484 3485 static int 3486 _write(int d, uint32_t addr, uint32_t data) 3487 { 3488 unsigned long flags; 3489 uint32 sl_addr; 3490 3491 if (!VALID_DEVICE(d)) { 3492 return -1; 3493 } 3494 3495 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3496 return -1; 3497 } 3498 3499 if (_devices[d].dev_type & BDE_DEV_BUS_WR_16BIT) { 3500 /* 3501 * Adjust the address presented to Eb slave. Move A15:A0 to A16:A1. 3502 */ 3503 sl_addr = (addr & 0xffff0000) | ((addr & 0xffff) << 1); 3504 3505 /* Disable interrupts */ 3506 spin_lock_irqsave(&bus_lock, flags); 3507 3508 *((VOL uint16 *)(_devices[d].bde_dev.base_address + sl_addr)) = 3509 data & 0xffff; 3510 *((VOL uint16 *)(_devices[d].bde_dev.base_address + sl_addr)) = 3511 (data >> 16) & 0xffff; 3512 spin_unlock_irqrestore(&bus_lock, flags); 3513 } else { 3514 #if defined(CMIC_SOFT_BYTE_SWAP) 3515 data = CMIC_SWAP32(data); 3516 #endif 3517 ((VOL uint32_t *)_devices[d].bde_dev.base_address)[addr / 4] = data; 3518 #ifdef KEYSTONE 3519 /* Enforce PCIe transaction ordering. Commit the write transaction */ 3520 __asm__ __volatile__("sync"); 3521 #endif 3522 } 3523 return 0; 3524 3525 } 3526 3527 static _ISR_RET 3528 _isr(_ISR_PARAMS(irq, dev_id, iregs)) 3529 { 3530 bde_ctrl_t *ctrl = (bde_ctrl_t *) dev_id; 3531 3532 if (ctrl && ctrl->isr) { 3533 ctrl->isr(ctrl->isr_data); 3534 } 3535 if (ctrl && ctrl->isr2) { 3536 ctrl->isr2(ctrl->isr2_data); 3537 } 3538 return IRQ_HANDLED; 3539 } 3540 3541 static int 3542 _interrupt_connect(int d, 3543 void (*isr)(void *), 3544 void *isr_data) 3545 { 3546 bde_ctrl_t *ctrl; 3547 unsigned long irq_flags; 3548 int isr2_dev; 3549 int isr_active; 3550 int ret = 0; 3551 3552 isr2_dev = d & LKBDE_ISR2_DEV; 3553 d &= ~LKBDE_ISR2_DEV; 3554 3555 if (!VALID_DEVICE(d)) { 3556 gprintk("_interrupt_connect: Invalid device index %d\n", d); 3557 return -1; 3558 } 3559 if (debug >= 1) { 3560 gprintk("_interrupt_connect d %d\n", d); 3561 } 3562 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3563 gprintk("_interrupt_connect: Not PCI device %d, type %x\n", 3564 d, _devices[d].dev_type); 3565 return -1; 3566 } 3567 3568 ctrl = _devices + d; 3569 3570 isr_active = (ctrl->isr || ctrl->isr2) ? 1 : 0; 3571 3572 if (unlikely(debug > 1)) 3573 gprintk("%s:isr_active = %d\n", __func__, isr_active); 3574 3575 if (isr2_dev) { 3576 if (debug >= 1) { 3577 gprintk("connect secondary isr\n"); 3578 } 3579 ctrl->isr2_data = isr_data; 3580 ctrl->isr2 = isr; 3581 if (isr_active) { 3582 /* Main handler (_isr) already installed */ 3583 return 0; 3584 } 3585 } else { 3586 if (debug >= 1) { 3587 gprintk("connect primary isr\n"); 3588 } 3589 ctrl->isr = isr; 3590 ctrl->isr_data = isr_data; 3591 if (isr_active) { 3592 /* Main handler (_isr) already installed */ 3593 return 0; 3594 } 3595 } 3596 3597 if (ctrl->iLine != -1) { 3598 irq_flags = IRQF_SHARED; 3599 #ifdef CONFIG_PCI_MSI 3600 if (ctrl->use_msi >= PCI_USE_INT_MSI) { 3601 ret = _msi_connect(ctrl); 3602 if(ret != 0) 3603 goto msi_exit; 3604 } 3605 #endif 3606 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 3607 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 3608 int i; 3609 for (i = 0; i < ctrl->msix_cnt; i++) { 3610 if (unlikely(debug >= 1)) { 3611 gprintk("%s(%d):device# = %d, irq = %d\n", 3612 __func__, __LINE__, d, ctrl->entries[i].vector); 3613 } 3614 ret = request_irq(ctrl->entries[i].vector, (irq_handler_t)_isr, 0, 3615 LINUX_KERNEL_BDE_NAME, ctrl); 3616 if (ret < 0) 3617 break; 3618 } 3619 if (ret < 0) { 3620 while (i >= 0) 3621 free_irq(ctrl->entries[i--].vector, ctrl); 3622 3623 goto err_disable_msi; 3624 } 3625 } 3626 else 3627 #endif 3628 { 3629 #if defined(IPROC_CMICD) && defined(CONFIG_OF) 3630 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 3631 int i, j; 3632 for (i = 0; i < IHOST_CMICX_MAX_INTRS; i++) { 3633 if (!iproc_cmicx_irqs[i]) { 3634 continue; 3635 } 3636 if (unlikely(debug >= 1)) 3637 gprintk("%s(%d):device# = %d, request_irq(%d)\n", 3638 __func__, __LINE__, d, iproc_cmicx_irqs[i]); 3639 ret = request_irq(iproc_cmicx_irqs[i], (irq_handler_t)_isr, 3640 irq_flags, LINUX_KERNEL_BDE_NAME, ctrl); 3641 if (ret < 0) { 3642 gprintk("request_irq(%d) failed(%d)\n", iproc_cmicx_irqs[i], ret); 3643 break; 3644 } 3645 } 3646 if (ret < 0) { 3647 for (j = 0; j < i; j++) { 3648 if (!iproc_cmicx_irqs[j]) { 3649 continue; 3650 } 3651 free_irq(iproc_cmicx_irqs[j], ctrl); 3652 } 3653 goto err_disable_msi; 3654 } 3655 } else 3656 #endif 3657 { 3658 ret = request_irq(ctrl->iLine, _isr, irq_flags, 3659 LINUX_KERNEL_BDE_NAME, ctrl); 3660 if (ret < 0) 3661 goto err_disable_msi; 3662 3663 if (unlikely(debug >= 1)) 3664 gprintk("%s(%d):device# = %d, irq_flags = %lu, irq = %d\n", 3665 __func__, __LINE__, d, 3666 irq_flags, ctrl->pci_device ? ctrl->pci_device->irq : ctrl->iLine); 3667 } 3668 } 3669 } 3670 return 0; 3671 3672 err_disable_msi: 3673 #ifdef CONFIG_PCI_MSI 3674 _msi_disconnect(ctrl); 3675 3676 msi_exit: 3677 #endif 3678 gprintk("could not request IRQ\n"); 3679 ctrl->isr = NULL; 3680 ctrl->isr_data = NULL; 3681 ctrl->isr2 = NULL; 3682 ctrl->isr2_data = NULL; 3683 3684 return -1; 3685 } 3686 3687 static int 3688 _interrupt_disconnect(int d) 3689 { 3690 bde_ctrl_t *ctrl; 3691 int isr2_dev; 3692 int isr_active; 3693 3694 isr2_dev = d & LKBDE_ISR2_DEV; 3695 d &= ~LKBDE_ISR2_DEV; 3696 3697 if (!VALID_DEVICE(d)) { 3698 return -1; 3699 } 3700 3701 if (debug >= 1) { 3702 gprintk("_interrupt_disconnect d %d\n", d); 3703 } 3704 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3705 gprintk("_interrupt_disconnect: Not PCI device %d, type %x\n", 3706 d, _devices[d].dev_type); 3707 return -1; 3708 } 3709 3710 ctrl = _devices + d; 3711 3712 isr_active = (ctrl->isr || ctrl->isr2) ? 1 : 0; 3713 3714 if (unlikely(debug > 1)) 3715 gprintk("%s: isr_active = %d\n", __func__, isr_active); 3716 3717 if (isr2_dev) { 3718 if (debug >= 1) { 3719 gprintk("disconnect secondary isr\n"); 3720 } 3721 ctrl->isr2 = NULL; 3722 ctrl->isr2_data = NULL; 3723 ctrl->fmask = 0; 3724 if (ctrl->isr) { 3725 /* Primary handler still active */ 3726 SYNC_IRQ(ctrl->iLine); 3727 return 0; 3728 } 3729 } else { 3730 if (debug >= 1) { 3731 gprintk("disconnect primary isr\n"); 3732 } 3733 ctrl->isr = NULL; 3734 ctrl->isr_data = NULL; 3735 if (ctrl->isr2) { 3736 /* Secondary handler still active */ 3737 SYNC_IRQ(ctrl->iLine); 3738 return 0; 3739 } 3740 } 3741 3742 if (isr_active) { 3743 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 3744 if (ctrl->use_msi >= PCI_USE_INT_MSIX) { 3745 int i; 3746 for (i = 0; i < ctrl->msix_cnt; i++) { 3747 if (unlikely(debug > 1)) { 3748 gprintk("%s(%d):device# = %d, irq = %d\n", 3749 __func__, __LINE__, d, ctrl->entries[i].vector); 3750 } 3751 free_irq(ctrl->entries[i].vector, ctrl); 3752 } 3753 } 3754 else 3755 #endif 3756 #if defined(IPROC_CMICD) && defined(CONFIG_OF) 3757 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 3758 int i; 3759 for (i = 0; i < IHOST_CMICX_MAX_INTRS; i++) { 3760 if (!iproc_cmicx_irqs[i]) { 3761 continue; 3762 } 3763 if (unlikely(debug > 1)) { 3764 gprintk("%s(%d):device# = %d, free_irq(%d)\n", 3765 __func__, __LINE__, d, iproc_cmicx_irqs[i]); 3766 } 3767 free_irq(iproc_cmicx_irqs[i], ctrl); 3768 } 3769 } else 3770 #endif 3771 { 3772 free_irq(ctrl->iLine, ctrl); 3773 } 3774 #ifdef CONFIG_PCI_MSI 3775 if (ctrl->use_msi >= PCI_USE_INT_MSI) { 3776 _msi_disconnect(ctrl); 3777 } 3778 #endif 3779 } 3780 3781 return 0; 3782 } 3783 3784 static uint32_t 3785 _iproc_ihost_read(int d, uint32_t addr) 3786 { 3787 uint32_t *mapaddr; 3788 uint32_t reg_val; 3789 mapaddr = IOREMAP(addr, sizeof(uint32_t)); 3790 if (mapaddr == NULL) { 3791 return -1; 3792 } 3793 reg_val = readl(mapaddr); 3794 iounmap(mapaddr); 3795 return reg_val; 3796 } 3797 3798 static int 3799 _iproc_ihost_write(int d, uint32_t addr, uint32_t data) 3800 { 3801 uint32_t *mapaddr; 3802 mapaddr = IOREMAP(addr, sizeof(uint32_t)); 3803 if (mapaddr == NULL) { 3804 return -1; 3805 } 3806 writel(data, mapaddr); 3807 iounmap(mapaddr); 3808 return 0; 3809 } 3810 3811 static uint32_t 3812 _iproc_read(int d, uint32_t addr) 3813 { 3814 if (!VALID_DEVICE(d)) { 3815 return -1; 3816 } 3817 3818 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3819 return -1; 3820 } 3821 3822 if (_devices[d].dev_type & BDE_AXI_DEV_TYPE) { 3823 if (IHOST_GICD_REG_ADDR_VALID(d, addr)) { 3824 return readl(IHOST_GICD_REG_ADDR_REMAP(d, addr)); 3825 } 3826 return _iproc_ihost_read(d, addr); 3827 } 3828 3829 return shbde_iproc_pci_read(&_devices[d].shbde, 3830 (void *)_devices[d].bde_dev.base_address1, 3831 addr); 3832 } 3833 3834 static int 3835 _iproc_write(int d, uint32_t addr, uint32_t data) 3836 { 3837 if (!VALID_DEVICE(d)) { 3838 return -1; 3839 } 3840 3841 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3842 return -1; 3843 } 3844 3845 if (_devices[d].dev_type & BDE_AXI_DEV_TYPE) { 3846 if (IHOST_GICD_REG_ADDR_VALID(d, addr)) { 3847 writel(data, IHOST_GICD_REG_ADDR_REMAP(d, addr)); 3848 return 0; 3849 } 3850 return _iproc_ihost_write(d, addr, data); 3851 } 3852 3853 shbde_iproc_pci_write(&_devices[d].shbde, 3854 (void *)_devices[d].bde_dev.base_address1, 3855 addr, data); 3856 3857 return 0; 3858 } 3859 3860 static int 3861 _get_cmic_ver(int d , uint32_t *ver) 3862 { 3863 3864 unsigned int cap_base; 3865 uint32_t rval = 0; 3866 3867 if (!VALID_DEVICE(d)) { 3868 gprintk("%s: Invalid device index %d\n", __func__, d); 3869 return -1; 3870 } 3871 3872 if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { 3873 gprintk("%s: Not PCI device %d, type %x\n", __func__, 3874 d, _devices[d].dev_type); 3875 return -1; 3876 } 3877 3878 /* Look for PCIe vendor-specific extended capability (VSEC) */ 3879 cap_base = PCI_EXT_CAP_START; 3880 while (cap_base) { 3881 pci_read_config_dword(_devices[d].pci_device, cap_base, &rval); 3882 if (rval == 0xffffffff) { 3883 /* Assume PCI HW read error */ 3884 gprintk("%s: PCI HW read error\n", __func__); 3885 return -1; 3886 } 3887 3888 if (PCI_EXT_CAP_ID(rval) == PCI_EXT_CAP_ID_VNDR) { 3889 break; 3890 } 3891 cap_base = PCI_EXT_CAP_NEXT(rval); 3892 } 3893 if (cap_base) { 3894 /* 3895 * VSEC layout: 3896 * 3897 * 0x00: PCI Express Extended Capability Header 3898 * 0x04: Vendor-Specific Header 3899 * 0x08: Vendor-Specific Register 1 3900 * 0x0c: Vendor-Specific Register 2 3901 * ... 3902 * 0x24: Vendor-Specific Register 8 3903 */ 3904 pci_read_config_dword(_devices[d].pci_device, cap_base + 8, &rval); 3905 if (unlikely(debug > 1)) 3906 gprintk("%s:Found VSEC = %u\n", __func__, rval); 3907 3908 /* Determine if CMICX */ 3909 rval = ((rval >> 12) & 0xf); 3910 *ver = rval; 3911 3912 return 0; 3913 } else { 3914 gprintk("%s:VSEC not found\n", __func__); 3915 } 3916 3917 return -1; 3918 } 3919 3920 #ifdef BCM_SAND_SUPPORT 3921 int 3922 lkbde_cpu_write(int d, uint32 addr, uint32 *buf) 3923 { 3924 #if defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__) 3925 *((uint32_t*)((uint8_t*)cpu_address + addr)) = *buf; 3926 #endif 3927 3928 return 0; 3929 } 3930 3931 int 3932 lkbde_cpu_read(int d, uint32 addr, uint32 *buf) 3933 { 3934 #if defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__) 3935 *buf = *((uint32_t*)((uint8_t*)cpu_address + addr)); 3936 #else 3937 *buf = (uint32_t)(-1); 3938 #endif 3939 3940 return 0; 3941 } 3942 3943 int 3944 lkbde_cpu_pci_register(int d) 3945 { 3946 bde_ctrl_t* ctrl; 3947 uint16 cmd = 0; 3948 3949 if (!VALID_DEVICE(d)) { 3950 return -1; 3951 } 3952 3953 ctrl = &_devices[d]; 3954 3955 /* enable device */ 3956 if (pci_enable_device(ctrl->pci_device)) { 3957 gprintk("Cannot enable pci device : vendor_id = %x, device_id = %x\n", 3958 ctrl->pci_device->vendor, ctrl->pci_device->device); 3959 } 3960 3961 /* Add PCI_COMMAND_MEMORY and PCI_COMMAND_MASTER */ 3962 pci_read_config_word(ctrl->pci_device, PCI_COMMAND, &cmd); 3963 if (!(cmd & PCI_COMMAND_MEMORY) || !(cmd & PCI_COMMAND_MASTER)) { 3964 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 3965 pci_write_config_word(ctrl->pci_device, PCI_COMMAND, cmd); 3966 } 3967 3968 switch (ctrl->bde_dev.device) { 3969 case GEDI_DEVICE_ID: 3970 /* Fix bar 0 address */ /* FIXME: write full phy address */ 3971 pci_write_config_byte(ctrl->pci_device, 0x13, 0x60); 3972 3973 /* Fix Max payload size */ 3974 pci_write_config_byte(ctrl->pci_device, 0x88, 0x2f); 3975 pci_write_config_byte(ctrl->pci_device, 0x89, 0x10); 3976 break; 3977 case BCM88750_DEVICE_ID: 3978 case BCM88753_DEVICE_ID: 3979 case BCM88755_DEVICE_ID: 3980 case BCM88770_DEVICE_ID: 3981 case BCM88773_DEVICE_ID: 3982 case BCM88774_DEVICE_ID: 3983 case BCM88775_DEVICE_ID: 3984 case BCM88776_DEVICE_ID: 3985 case BCM88777_DEVICE_ID: 3986 case BCM88950_DEVICE_ID: 3987 case BCM88953_DEVICE_ID: 3988 case BCM88954_DEVICE_ID: 3989 case BCM88955_DEVICE_ID: 3990 case BCM88956_DEVICE_ID: 3991 case BCM88752_DEVICE_ID: 3992 case BCM88772_DEVICE_ID: 3993 case BCM88952_DEVICE_ID: 3994 case ACP_PCI_DEVICE_ID: 3995 case BCM88650_DEVICE_ID: 3996 3997 case BCM88670_DEVICE_ID: 3998 case BCM88671_DEVICE_ID: 3999 case BCM88671M_DEVICE_ID: 4000 case BCM88672_DEVICE_ID: 4001 case BCM88673_DEVICE_ID: 4002 case BCM88674_DEVICE_ID: 4003 case BCM88675_DEVICE_ID: 4004 case BCM88675M_DEVICE_ID: 4005 case BCM88676_DEVICE_ID: 4006 case BCM88676M_DEVICE_ID: 4007 case BCM88677_DEVICE_ID: 4008 case BCM88678_DEVICE_ID: 4009 case BCM88679_DEVICE_ID: 4010 4011 case BCM88370_DEVICE_ID: 4012 case BCM88371_DEVICE_ID: 4013 case BCM88371M_DEVICE_ID: 4014 case BCM88375_DEVICE_ID: 4015 case BCM88376_DEVICE_ID: 4016 case BCM88376M_DEVICE_ID: 4017 case BCM88377_DEVICE_ID: 4018 case BCM88378_DEVICE_ID: 4019 case BCM88379_DEVICE_ID: 4020 case BCM88681_DEVICE_ID: 4021 case BCM88682_DEVICE_ID: 4022 case BCM88683_DEVICE_ID: 4023 case BCM88684_DEVICE_ID: 4024 case BCM88685_DEVICE_ID: 4025 case BCM88687_DEVICE_ID: 4026 case BCM88380_DEVICE_ID: 4027 case BCM88381_DEVICE_ID: 4028 case BCM88680_DEVICE_ID: 4029 case BCM88470_DEVICE_ID: 4030 case BCM88470P_DEVICE_ID: 4031 case BCM88471_DEVICE_ID: 4032 case BCM88473_DEVICE_ID: 4033 case BCM88474_DEVICE_ID: 4034 case BCM88474H_DEVICE_ID: 4035 case BCM88476_DEVICE_ID: 4036 case BCM88477_DEVICE_ID: 4037 case BCM88270_DEVICE_ID: 4038 case BCM88271_DEVICE_ID: 4039 case BCM88272_DEVICE_ID: 4040 case BCM88273_DEVICE_ID: 4041 case BCM88274_DEVICE_ID: 4042 case BCM88276_DEVICE_ID: 4043 case BCM88278_DEVICE_ID: 4044 case BCM8206_DEVICE_ID: 4045 case BCM88350_DEVICE_ID: 4046 case BCM88351_DEVICE_ID: 4047 case BCM88450_DEVICE_ID: 4048 case BCM88451_DEVICE_ID: 4049 case BCM88550_DEVICE_ID: 4050 case BCM88551_DEVICE_ID: 4051 case BCM88552_DEVICE_ID: 4052 case BCM88651_DEVICE_ID: 4053 case BCM88654_DEVICE_ID: 4054 case BCM88660_DEVICE_ID: 4055 case BCM88360_DEVICE_ID: 4056 case BCM88361_DEVICE_ID: 4057 case BCM88363_DEVICE_ID: 4058 case BCM88460_DEVICE_ID: 4059 case BCM88461_DEVICE_ID: 4060 case BCM88560_DEVICE_ID: 4061 case BCM88561_DEVICE_ID: 4062 case BCM88562_DEVICE_ID: 4063 case BCM88661_DEVICE_ID: 4064 case BCM88664_DEVICE_ID: 4065 /* Fix bar 0 address */ /* FIXME: write full phy address */ 4066 pci_write_config_byte(ctrl->pci_device, 0x12, 0x10); 4067 pci_write_config_byte(ctrl->pci_device, 0x13, 0x60); 4068 4069 /* 4070 * For DMA transactions - set Max_Payload_Size and 4071 * Max_Read_Request_Size to 128 bytes. 4072 */ 4073 pci_write_config_byte(ctrl->pci_device, 0xb5, 0x0c); 4074 pci_write_config_byte(ctrl->pci_device, 0xb4, 0x0); 4075 break; 4076 default: 4077 break; 4078 } 4079 4080 /* configure iproc >=14 devices by device family */ 4081 #if defined(BCM_DNXF_SUPPORT) || defined(BCM_DNX_SUPPORT) 4082 switch (ctrl->bde_dev.device & DNXC_DEVID_FAMILY_MASK) { 4083 #ifdef BCM_DNX_SUPPORT 4084 case JERICHO2_DEVICE_ID: 4085 case J2C_DEVICE_ID: 4086 case J2C_2ND_DEVICE_ID: 4087 case Q2A_DEVICE_ID: 4088 case Q2U_DEVICE_ID: 4089 case J2P_DEVICE_ID: 4090 #endif 4091 #ifdef BCM_DNXF_SUPPORT 4092 case BCM88790_DEVICE_ID: 4093 #endif 4094 /* 4095 * For DMA transactions - set Max_Payload_Size and 4096 * Max_Read_Request_Size to 128 bytes. 4097 */ 4098 pci_write_config_byte(ctrl->pci_device, 0xb5, 0x0c); 4099 pci_write_config_byte(ctrl->pci_device, 0xb4, 0x0); 4100 break; 4101 } 4102 #endif /* defined(BCM_DNXF_SUPPORT) || defined(BCM_DNX_SUPPORT) */ 4103 4104 /* Redo ioremap */ 4105 if (ctrl->bde_dev.base_address) { 4106 iounmap((void *)ctrl->bde_dev.base_address); 4107 } 4108 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(ctrl->iowin[0].addr, 0x1000000); 4109 4110 if (debug >= 1) { 4111 gprintk("%s, %s(): info:\n", __FILE__, __FUNCTION__); 4112 gprintk("_ndevices=%d, _switch_ndevices=%d\n", 4113 _ndevices, _switch_ndevices); 4114 gprintk("ctrl->dev_type=0x%x, ctrl->phys_address=0x%lx\n", 4115 ctrl->dev_type, (unsigned long)ctrl->iowin[0].addr); 4116 gprintk("ctrl->bde_dev.device=0x%x, ctrl->bde_dev.rev=0x%x, " 4117 "ctrl->bde_dev.base_address=0x%lx\n", 4118 ctrl->bde_dev.device, ctrl->bde_dev.rev, 4119 (unsigned long)ctrl->bde_dev.base_address); 4120 } 4121 4122 return 0; 4123 } 4124 4125 /* 4126 * Export Low level access function - currently for PCP DMA Kernel module. 4127 */ 4128 int 4129 lkbde_mem_write(int d, uint32 addr, uint32 *buf) 4130 { 4131 bde_ctrl_t* ctrl; 4132 void *full_addr; 4133 4134 if (!VALID_DEVICE(d)) return -1; 4135 ctrl = &_devices[d]; 4136 4137 full_addr = (void *)ctrl->bde_dev.base_address + addr; 4138 *((uint32_t*)full_addr) = *buf; 4139 return 0; 4140 } 4141 LKM_EXPORT_SYM(lkbde_mem_write); 4142 4143 int 4144 lkbde_mem_read(int d, uint32 addr, uint32 *buf) 4145 { 4146 bde_ctrl_t* ctrl; 4147 void *full_addr; 4148 4149 if (!VALID_DEVICE(d)) return -1; 4150 ctrl = &_devices[d]; 4151 4152 full_addr = (void *)ctrl->bde_dev.base_address + addr; 4153 *buf = *((uint32_t*)full_addr); 4154 return 0; 4155 } 4156 LKM_EXPORT_SYM(lkbde_mem_read); 4157 #endif /* BCM_SAND_SUPPORT */ 4158 4159 static ibde_t _ibde = { 4160 name: _name, 4161 num_devices: _num_devices, 4162 get_dev: _get_dev, 4163 get_dev_type: _get_dev_type, 4164 pci_conf_read: _pci_conf_read, 4165 pci_conf_write: _pci_conf_write, 4166 pci_bus_features: _pci_bus_features, 4167 read: _read, 4168 write: _write, 4169 salloc: _salloc, 4170 sfree: _sfree, 4171 sinval: _sinval, 4172 sflush: _sflush, 4173 interrupt_connect: _interrupt_connect, 4174 interrupt_disconnect: _interrupt_disconnect, 4175 l2p: _l2p, 4176 p2l: _p2l, 4177 4178 NULL, 4179 NULL, 4180 iproc_read: _iproc_read, 4181 iproc_write: _iproc_write, 4182 get_cmic_ver: _get_cmic_ver, 4183 }; 4184 4185 /* 4186 * Function: linux_bde_create 4187 * 4188 * Purpose: 4189 * Creator function for this BDE interface. 4190 * Parameters: 4191 * bus - pointer to the bus features structure you want this 4192 * bde to export. Depends on the system. 4193 * ibde - pointer to a location to recieve the bde interface pointer. 4194 * Returns: 4195 * 0 on success 4196 * -1 on failure. 4197 * Notes: 4198 * This is the main BDE create function for this interface. 4199 * Used by the external system initialization code. 4200 */ 4201 int 4202 linux_bde_create(linux_bde_bus_t *bus, ibde_t **ibde) 4203 { 4204 4205 memset(&_bus, 0, sizeof(_bus)); 4206 4207 if (bus) { 4208 _bus = *bus; 4209 } 4210 #ifdef NONCOHERENT_DMA_MEMORY 4211 #ifdef REMAP_DMA_NONCACHED 4212 /* 4213 * If we have a non-cached DMA memory pool 4214 * there is no need to flush and invalidate. 4215 */ 4216 if (_dma_pool_allocated()) { 4217 _ibde.sinval = NULL; 4218 _ibde.sflush = NULL; 4219 } 4220 #endif 4221 #else 4222 _ibde.sinval = NULL; 4223 _ibde.sflush = NULL; 4224 #endif 4225 *ibde = &_ibde; 4226 return 0; 4227 } 4228 4229 /* 4230 * Function: linux_bde_destroy 4231 * 4232 * Purpose: 4233 * destroy this bde 4234 * Parameters: 4235 * BDE interface pointer 4236 * Returns: 4237 * 0 on success, < 0 on error. 4238 */ 4239 int 4240 linux_bde_destroy(ibde_t *ibde) 4241 { 4242 /* nothing */ 4243 return 0; 4244 } 4245 4246 /* 4247 * Backdoors provided by the kernel bde 4248 */ 4249 4250 uint32_t 4251 lkbde_get_dev_phys(int d) 4252 { 4253 if (!VALID_DEVICE(d)) { 4254 return -1; 4255 } 4256 4257 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4258 gprintk("lkbde_get_dev_phys: Not PCI device %d, type %x\n", 4259 d, _devices[d].dev_type); 4260 return 0; 4261 } 4262 return _devices[d].iowin[0].addr; 4263 } 4264 4265 uint32_t 4266 lkbde_get_dev_phys_hi(int d) 4267 { 4268 if (!VALID_DEVICE(d)) { 4269 return -1; 4270 } 4271 4272 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4273 gprintk("lkbde_get_dev_phys: Not PCI device %d, type %x\n", 4274 d, _devices[d].dev_type); 4275 return 0; 4276 } 4277 #ifdef PHYS_ADDR_IS_64BIT 4278 return (uint32_t)(_devices[d].iowin[0].addr >> 32); 4279 #else 4280 return 0; 4281 #endif 4282 } 4283 4284 void * 4285 lkbde_get_dev_virt(int d) 4286 { 4287 if (!VALID_DEVICE(d)) { 4288 return NULL; 4289 } 4290 4291 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4292 gprintk("lkbde_get_dev_virt: Not PCI device %d, type %x\n", 4293 d, _devices[d].dev_type); 4294 return 0; 4295 } 4296 4297 if (_devices[d].alt_base_addr) { 4298 return (void *)_devices[d].alt_base_addr; 4299 } 4300 4301 return (void *)_devices[d].bde_dev.base_address; 4302 } 4303 4304 int 4305 lkbde_get_dev_resource(int d, int rsrc, uint32_t *flags, 4306 uint32_t *phys_lo, uint32_t *phys_hi) 4307 { 4308 if (!VALID_DEVICE(d)) { 4309 return -1; 4310 } 4311 4312 *flags = 0; 4313 *phys_lo = 0; 4314 *phys_hi = 0; 4315 4316 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4317 gprintk("lkbde_get_dev_phys: Not PCI device %d, type %x\n", 4318 d, _devices[d].dev_type); 4319 return 0; 4320 } 4321 4322 switch (rsrc) { 4323 case 0: 4324 *phys_lo = (uint32_t)(_devices[d].iowin[0].addr); 4325 #ifdef PHYS_ADDR_IS_64BIT 4326 *phys_hi = (uint32_t)(_devices[d].iowin[0].addr >> 32); 4327 #endif 4328 break; 4329 case 1: 4330 *phys_lo = (uint32_t)(_devices[d].iowin[1].addr); 4331 #ifdef PHYS_ADDR_IS_64BIT 4332 *phys_hi = (uint32_t)(_devices[d].iowin[1].addr >> 32); 4333 #endif 4334 break; 4335 default: 4336 break; 4337 } 4338 4339 return 0; 4340 } 4341 4342 void * 4343 lkbde_get_dma_dev(int d) 4344 { 4345 if (!VALID_DEVICE(d)) { 4346 return NULL; 4347 } 4348 4349 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 4350 return (void *)_devices[d].dma_dev; 4351 #else 4352 return (void *)_devices[d].pci_device; 4353 #endif 4354 } 4355 4356 void * 4357 lkbde_get_hw_dev(int d) 4358 { 4359 if (!VALID_DEVICE(d)) { 4360 return NULL; 4361 } 4362 4363 return (void *)_devices[d].pci_device; 4364 } 4365 4366 int 4367 lkbde_dev_state_set(int d, uint32 state) 4368 { 4369 bde_ctrl_t *ctrl; 4370 4371 if (!VALID_DEVICE(d)) { 4372 return -1; 4373 } 4374 ctrl = _devices + d; 4375 ctrl->dev_state = state; 4376 return 0; 4377 } 4378 4379 int 4380 lkbde_dev_state_get(int d, uint32 *state) 4381 { 4382 bde_ctrl_t *ctrl; 4383 if (!VALID_DEVICE(d)) { 4384 gprintk("_get_dev: Invalid device index %d\n", d); 4385 return -1; 4386 } 4387 ctrl = _devices + d; 4388 4389 *state = ctrl->dev_state; 4390 return 0; 4391 } 4392 4393 int 4394 lkbde_dev_instid_set(int d, uint32 instid) 4395 { 4396 bde_ctrl_t *ctrl; 4397 4398 if (!VALID_DEVICE(d)) { 4399 return -1; 4400 } 4401 ctrl = _devices + d; 4402 ctrl->inst_id = instid; 4403 4404 return 0; 4405 } 4406 4407 int 4408 lkbde_dev_instid_get(int d, uint32 *instid) 4409 { 4410 bde_ctrl_t *ctrl; 4411 4412 if (!VALID_DEVICE(d)) { 4413 return -1; 4414 } 4415 ctrl = _devices + d; 4416 *instid = ctrl->inst_id; 4417 4418 return 0; 4419 } 4420 /* 4421 * When a secondary interrupt handler is installed this function 4422 * is used for synchronizing hardware access to the IRQ mask 4423 * register. The secondary driver will supply a non-zero fmask 4424 * (filter mask) to indicate which interrupt bits it controls. 4425 * The fmask is ignored for the primary driver. 4426 */ 4427 int 4428 lkbde_irq_mask_set(int d, uint32_t addr, uint32_t mask, uint32_t fmask) 4429 { 4430 bde_ctrl_t *ctrl; 4431 int isr2_dev, iproc_reg; 4432 unsigned long flags; 4433 4434 isr2_dev = d & LKBDE_ISR2_DEV; 4435 iproc_reg = d & LKBDE_IPROC_REG; 4436 d &= ~(LKBDE_ISR2_DEV | LKBDE_IPROC_REG); 4437 4438 if (!VALID_DEVICE(d)) { 4439 return -1; 4440 } 4441 4442 ctrl = _devices + d; 4443 4444 /* Lock is required to synchronize access from user space */ 4445 spin_lock_irqsave(&ctrl->lock, flags); 4446 4447 if (isr2_dev) { 4448 /* This is the secondary interrupt handler */ 4449 ctrl->fmask = fmask; 4450 ctrl->imask2 = mask & ctrl->fmask; 4451 } else { 4452 /* This is the primary interrupt handler */ 4453 ctrl->imask = mask & ~ctrl->fmask; 4454 } 4455 4456 if (iproc_reg) { 4457 _iproc_write(d, addr, ctrl->imask | ctrl->imask2); 4458 } else { 4459 _write(d, addr, ctrl->imask | ctrl->imask2); 4460 } 4461 4462 spin_unlock_irqrestore(&ctrl->lock, flags); 4463 4464 return 0; 4465 } 4466 4467 /* 4468 * When a secondary interrupt handler is installed, this function 4469 * is used to avoid activating the user mode interrupt handler 4470 * thread if all pending interrupts are handled in kernel space. 4471 * 4472 * The mask returned is the mask of all interrupts, it can be used 4473 * to do a logical AND with fmask, the result will tell you if 4474 * the user mode interrupt handler needs to be invoked. 4475 * 4476 * Note that if no secondary handler is installed, the value of 4477 * "mask & fmask" will be zero, and hence there will be no need to read the 4478 * current interrupt status from hardware (from kernel space). 4479 */ 4480 int 4481 lkbde_irq_mask_get(int d, uint32_t *mask, uint32_t *fmask) 4482 { 4483 bde_ctrl_t *ctrl; 4484 4485 d &= ~(LKBDE_ISR2_DEV | LKBDE_IPROC_REG); 4486 4487 if (!VALID_DEVICE(d)) { 4488 return -1; 4489 } 4490 4491 if (mask == NULL || fmask == NULL) { 4492 return -1; 4493 } 4494 4495 ctrl = _devices + d; 4496 4497 *fmask = ctrl->fmask; 4498 *mask = ctrl->imask | ctrl->imask2; 4499 4500 return 0; 4501 } 4502 4503 int 4504 lkbde_get_num_devices(int type) 4505 { 4506 return _num_devices(type); 4507 } 4508 4509 /* 4510 * Export functions 4511 */ 4512 LKM_EXPORT_SYM(linux_bde_create); 4513 LKM_EXPORT_SYM(linux_bde_destroy); 4514 LKM_EXPORT_SYM(lkbde_get_dev_phys); 4515 LKM_EXPORT_SYM(lkbde_get_dev_virt); 4516 LKM_EXPORT_SYM(lkbde_get_dev_resource); 4517 LKM_EXPORT_SYM(lkbde_get_hw_dev); 4518 LKM_EXPORT_SYM(lkbde_get_dma_dev); 4519 LKM_EXPORT_SYM(lkbde_irq_mask_set); 4520 LKM_EXPORT_SYM(lkbde_irq_mask_get); 4521 LKM_EXPORT_SYM(lkbde_get_dev_phys_hi); 4522 LKM_EXPORT_SYM(lkbde_dev_state_set); 4523 LKM_EXPORT_SYM(lkbde_dev_state_get); 4524 LKM_EXPORT_SYM(lkbde_dev_instid_set); 4525 LKM_EXPORT_SYM(lkbde_dev_instid_get); 4526 #ifdef BCM_SAND_SUPPORT 4527 LKM_EXPORT_SYM(lkbde_cpu_write); 4528 LKM_EXPORT_SYM(lkbde_cpu_read); 4529 LKM_EXPORT_SYM(lkbde_cpu_pci_register); 4530 #endif