gdpll_shared.h (5973B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 6 * 7 * File: gdpll_shared.h 8 * Purpose: Shared GDPLL header file between M7 and the host 9 */ 10 11 #ifndef __BCM_INT_GDPLL_SHARED_H__ 12 #define __BCM_INT_GDPLL_SHARED_H__ 13 14 #if defined(INCLUDE_GDPLL) 15 16 /* M7 DTCM region references */ 17 #define DPLL_ALIVE_SIZE 4 /* This is the M7 Alive Indication */ 18 #define DPLL_FW_VERSION_SIZE 40 /* This is the M7 version size */ 19 #define DPLL_DEBUG_ENABLE_SIZE 4 /* This is the M7 switch for debug push */ 20 #define DPLL_PARAM_SIZE 236 /* This size is given to accomodate max 3 states */ 21 #define DPLL_GENERIC_SIZE (1024*2) 22 23 /* For any offset that gets added for versioning, etc */ 24 #define DPLL_ALIVE_OFFSET 0 /* This is the M7 Alive Indication */ 25 #define DPLL_FW_VERSION_OFFSET (DPLL_ALIVE_OFFSET + DPLL_ALIVE_SIZE) /* This is the M7 version start */ 26 #define DPLL_BCN_UPDATE_LOC (DPLL_FW_VERSION_OFFSET + DPLL_FW_VERSION_SIZE) /* Location used by R5 and Host for BCN counter */ 27 #define DPLL_NTPTOD_UPDATE_LOC (DPLL_BCN_UPDATE_LOC + 4) /* Location used by R5 and Host for NTPTOD counter updates */ 28 #define DPLL_PTPTOD_UPDATE_LOC (DPLL_NTPTOD_UPDATE_LOC + 4) /* Location used by R5 and Host for PTPTOD counter updates */ 29 #define DPLL_1588_FREQ_LOCK_LOC (DPLL_PTPTOD_UPDATE_LOC + 4) 30 #define DPLL_1588_DPLL_OFFSET_LOC (DPLL_1588_FREQ_LOCK_LOC + 4) 31 32 #define DPLL_BS0PLL_FREQ_LOCK_LOC (DPLL_1588_DPLL_OFFSET_LOC + 4) 33 #define DPLL_BS0PLL_DPLL_OFFSET_LOC (DPLL_BS0PLL_FREQ_LOCK_LOC + 4) 34 35 #define DPLL_BS1PLL_FREQ_LOCK_LOC (DPLL_BS0PLL_DPLL_OFFSET_LOC + 4) 36 #define DPLL_BS1PLL_DPLL_OFFSET_LOC (DPLL_BS1PLL_FREQ_LOCK_LOC + 4) 37 #define DPLL_BS0_UPDATE_LOC (DPLL_BS1PLL_DPLL_OFFSET_LOC + 4) 38 #define DPLL_BS1_UPDATE_LOC (DPLL_BS0_UPDATE_LOC + 4) 39 #define DPLL_NTPTOD_DPLL_OFFSET_LOC (DPLL_BS1_UPDATE_LOC + 4) 40 #define DPLL_PTPTOD_DPLL_OFFSET_LOC (DPLL_NTPTOD_DPLL_OFFSET_LOC + 4) 41 #define DPLL_CHAN_DUMP_LOC (DPLL_PTPTOD_DPLL_OFFSET_LOC + 4) /* size: sizeof(dpll_dump_t)*/ 42 43 44 #define DPLL_DEBUG_ENABLE_OFFSET (DPLL_GENERIC_SIZE)/*200*/ /* This is the M7 switch for debug push */ 45 #define DPLL_PARAM_START_OFFSET (DPLL_DEBUG_ENABLE_OFFSET + DPLL_DEBUG_ENABLE_SIZE) 46 #define DPLL_CHAN_PARAM_ADDR(base, chan) \ 47 (base + DPLL_PARAM_START_OFFSET + (DPLL_PARAM_SIZE * (chan))) 48 49 /* M7 SW Interrupt types */ 50 #define INTR_STATE_CHANGE 0x1 51 52 /* Channel debug data */ 53 typedef struct COMPILER_ATTRIBUTE((__packed__)) gdpll_chan_debug_dump_s { 54 int64 feedback; 55 int64 reference; 56 int64 perror; 57 } gdpll_chan_debug_dump_t; 58 59 typedef struct COMPILER_ATTRIBUTE((__packed__)) dpll_dump_s { 60 uint32 chan; 61 gdpll_chan_debug_dump_t debug_dump[2]; 62 } dpll_dump_t; 63 64 #define BCM_GDPLL_NUM_STATES 3 65 66 /* Per DPLL Configuration variables stored in state memory */ 67 typedef struct COMPILER_ATTRIBUTE((__packed__)) m7_gdpll_chan_dpll_config_s { 68 int32 K1[BCM_GDPLL_NUM_STATES]; 69 int8 K1Shift[BCM_GDPLL_NUM_STATES]; 70 int32 K1K2[BCM_GDPLL_NUM_STATES]; 71 int8 K1K2Shift[BCM_GDPLL_NUM_STATES]; 72 uint32 LockDetThres[BCM_GDPLL_NUM_STATES]; 73 uint32 LockIndicatorThresholdLo; 74 uint32 LockIndicatorThresholdHi; 75 uint16 DwellCount[BCM_GDPLL_NUM_STATES]; 76 uint64 PhaseErrorLimiterThres[BCM_GDPLL_NUM_STATES]; 77 uint8 NCObits; /* How many bits in NCO */ 78 uint8 PhaseCounterRef; /* use the phase counter instead of timestamp as reference input */ 79 uint8 DPLLNumOfStates; 80 uint16 IdumpMod[BCM_GDPLL_NUM_STATES]; 81 uint8 PhaseErrorShift; 82 int64 NominalLoopFilter; /* Nominal value of loop filter */ 83 uint8 InvertPhaseError; 84 uint8 NormalizePhaseError; /* remove full cycles of phase error */ 85 int32 PhaseErrorThres0; 86 int32 PhaseErrorThres1; 87 uint16 HoldoverFilterCoeff; 88 } m7_gdpll_chan_dpll_config_t; 89 90 /* Per DPLL state variables stored in state memory */ 91 typedef struct COMPILER_ATTRIBUTE((__packed__)) m7_gdpll_chan_dpll_state_s { 92 int64 Offset; 93 uint8 LockIndicator; /* Initialize to FALSE */ 94 uint8 LossOfLockIndicator; /* Initialize to FALSE */ 95 uint8 LargeErrorIndicator; /* Initialize to FALSE */ 96 uint8 PadByte1; /* Pad for aligned 32b access */ 97 uint8 HoldoverFlag; /* Initialize to FALSE. Used to get the DPLL into holdover */ 98 uint8 InitPhaseCounterFlag; /* Initialize to FALSE */ 99 uint8 InitOffsetFlag; /* Initialize to FALSE */ 100 uint8 PadByte2; /* Pad for aligned 32b access */ 101 uint8 DPLLState; 102 int64 LoopFilter; 103 uint32 DwellCounter; 104 uint32 LockDetFilter; 105 uint64 PhaseCounter; 106 uint64 PhaseCounterDelta; 107 uint16 PhaseCounterN; /* Initialize to 1 */ 108 uint16 PhaseCounterM; /* Initialize to 0 */ 109 uint16 PhaseCounterFrac; /* Initialize to 0 */ 110 uint16 IdumpCounter; /* Initialize to 0 */ 111 int64 AccumPhaseError; /* Initialize to 0 */ 112 int64 PrevIn0[2]; /* Initialize to 0 */ 113 int64 PrevIn1[2]; /* Initialize to 0 */ 114 uint8 LargeErrorCounter; 115 } m7_gdpll_chan_dpll_state_t; 116 117 /* Internal datastructure for dpll config */ 118 typedef struct COMPILER_ATTRIBUTE((__packed__)) m7_dpll_param_s { 119 int debugMode; 120 m7_gdpll_chan_dpll_state_t m7_dpll_state; 121 m7_gdpll_chan_dpll_config_t m7_dpll_config; 122 } m7_dpll_param_t; 123 124 #endif /* INCLUDE_GDPLL */ 125 #endif /* __BCM_INT_GDPLL_SHARED_H__ */