cosq.h (53604B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 6 * 7 * File: cosq.h 8 * Purpose: COSQ internal definitions to the BCM library. 9 */ 10 11 #ifndef _BCM_INT_DPP_COSQ_H_ 12 #define _BCM_INT_DPP_COSQ_H_ 13 14 #include <shared/swstate/sw_state.h> 15 16 #include <shared/gport.h> 17 18 #include <soc/dpp/drv.h> 19 #include <soc/dpp/dpp_config_defs.h> 20 21 #include <soc/dpp/TMC/tmc_api_egr_queuing.h> 22 #include <soc/dpp/TMC/tmc_api_general.h> 23 #include <soc/dpp/TMC/tmc_api_end2end_scheduler.h> 24 25 #include <bcm/debug.h> 26 #include <bcm/fabric.h> 27 #include <bcm/cosq.h> 28 29 /* 30 * If OPTIMIZE_VALIDATE_INFO_GET_AT_ENTRY is non-zero then code related 31 * to optimization of _bcm_petra_cosq_alloc_n_gport_validate_info_get() is added. 32 * This code uses some data base search right at entry of procedure using, 33 * its input parameters (unit, gport, cosq, flags) either directly or by deriving 34 * flow_id. 35 */ 36 #define OPTIMIZE_VALIDATE_INFO_GET_AT_ENTRY 1 37 /* 38 * The following definitions are only meaningful when OPTIMIZE_VALIDATE_INFO_GET_AT_ENTRY 39 * is non zero. 40 * { 41 */ 42 #if OPTIMIZE_VALIDATE_INFO_GET_AT_ENTRY 43 /* { */ 44 typedef enum vig_source_of_flow_id_e 45 { 46 VIG_SRC_FID_FIRST = 0, 47 VIG_SRC_FID_NONE = VIG_SRC_FID_FIRST,/* no source */ 48 /* 49 * Either E2E_PORT or E2E_PORT_TC 50 */ 51 VIG_SRC_FID_E2E_PORT, 52 VIG_SRC_FID_SCHEDULER, 53 VIG_SRC_FID_SCHED_CIR, 54 VIG_SRC_FID_SCHED_PIR, 55 VIG_SRC_FID_VOQ_CONNECTOR, 56 VIG_SRC_FID_COMPOSITE_SF2, 57 VIG_SRC_FID_NUM_ELEMENTS 58 } vig_source_of_flow_id_t; 59 60 /* } */ 61 #endif 62 /* 63 * } 64 */ 65 #define BCM_PETRA_COSQ_CREDIT_WATHDOG_USE_MAX 0x1 66 #define BCM_PETRA_COSQ_CREDIT_WATHDOG_USE_MIN 0x2 67 #define BCM_PETRA_COSQ_CREDIT_WATHDOG_USE_ENABLE 0x4 68 69 70 /* Currently this is not done and thus it is stored in persistent storage. */ 71 /* The following definition should be removed once the above is implemented */ 72 /* This will help in retreiving the sttae from h/w. */ 73 #define BCM_DPP_COSQ_CONN_NO_MODID_OPTIMIZATION 1 74 75 /* 76 * reserved queue flows 77 */ 78 #define DPP_DEVICE_COSQ_QUEUE_RESERVED_FLOW_START SHR_DEVICE_QUEUE_RESERVED_FLOW_START 79 #define DPP_DEVICE_COSQ_QUEUE_RESERVED_TOTAL_FLOWS 16 80 81 #define DPP_DEVICE_COSQ_QUEUE_REGION_UNICAST 3 82 #define DPP_DEVICE_COSQ_QUEUE_REGION_MULTICAST 4 83 #define DPP_DEVICE_COSQ_QUEUE_REGION_ISQ 5 84 85 /* Start of Flow regions that are not simple */ 86 #define DPP_DEVICE_PETRA_COSQ_CONFIG_FLOW_REGION_START 25 /* 1 based */ 87 #define DPP_DEVICE_PETRA_COSQ_FLOW_REGION_FIXED_TYPE0_END 24 /* 1 based */ 88 #define DPP_DEVICE_PETRA_COSQ_CONFIG_FLOW_REGIONS 32 89 #define DPP_DEVICE_PETRA_COSQ_TOTAL_FLOW_REGIONS 56 90 91 #define DPP_DEVICE_ARAD_COSQ_CONFIG_FLOW_REGION_START 65 /* 1 based */ 92 #define DPP_DEVICE_ARAD_COSQ_FLOW_REGION_FIXED_TYPE0_END 64 /* 1 based */ 93 #define DPP_DEVICE_ARAD_COSQ_CONFIG_FLOW_REGIONS 64 94 95 #define DPP_DEVICE_QAX_COSQ_FLOW_REGION_FIXED_TYPE0_END 96 /* 1 based */ 96 97 #define DPP_DEVICE_COSQ_CONFIG_FLOW_REGION_START(unit) (DPP_DEVICE_ARAD_COSQ_CONFIG_FLOW_REGION_START) /*1 base*/ 98 #define DPP_DEVICE_COSQ_CONFIG_FLOW_REGIONS(unit) (DPP_DEVICE_ARAD_COSQ_CONFIG_FLOW_REGIONS) 99 #define DPP_DEVICE_COSQ_CONFIG_FLOW_REGIONS_END(unit) (DPP_DEVICE_COSQ_CONFIG_FLOW_REGION_START(unit) + DPP_DEVICE_COSQ_CONFIG_FLOW_REGIONS(unit) - 1) /*1 base*/ 100 101 #define DPP_DEVICE_COSQ_TOTAL_FLOW_REGIONS(unit) (SOC_TMC_COSQ_TOTAL_FLOW_REGIONS) 102 #define DPP_DEVICE_COSQ_FLOW_REGION_FIXED_TYPE0_END(unit) ((SOC_IS_QAX(unit)? DPP_DEVICE_QAX_COSQ_FLOW_REGION_FIXED_TYPE0_END : DPP_DEVICE_ARAD_COSQ_FLOW_REGION_FIXED_TYPE0_END)) 103 104 #define DPP_DEVICE_COSQ_MAX_REGION_VAL 127 105 106 #define DPP_DEVICE_COSQ_CONFIG_QUEUE_REGIONS(unit) (SOC_DPP_DEFS_GET(unit, nof_queues_per_pipe)/DPP_DEVICE_COSQ_NBR_QUEUES_IN_REGION) 107 #define DPP_DEVICE_COSQ_CONFIG_INTERDIGITATED_REGIONS(unit) (DPP_DEVICE_COSQ_CONFIG_QUEUE_REGIONS(unit) / SOC_DPP_DEFS_GET(unit, nof_pools_per_interdigitated_region)) 108 #define DPP_DEVICE_PETRA_COSQ_MAX_QUEUE(unit) (SOC_DPP_DEFS_GET(unit, nof_queues_per_pipe) - 1) 109 #define DPP_DEVICE_PETRA_COSQ_MAX_FLOW(unit) (SOC_DPP_CONFIG(unit)->tm.max_connectors-1) 110 111 #define DPP_DEVICE_PETRA_VOQ_HD_SIZE(unit) ((SOC_DPP_CORE_MODE_IS_SYMMETRIC(unit)) ? \ 112 (SOC_DPP_DEFS_GET(unit, nof_queues_per_pipe) - 1) : \ 113 ((SOC_DPP_DEFS_GET(unit, nof_queues_per_pipe) * SOC_DPP_CONFIG(unit)->core_mode.nof_active_cores) - 1)) 114 115 #define DPP_DEVICE_PETRA_VOQ_HD_CORE(unit, element_index) (!SOC_DPP_CORE_MODE_IS_SYMMETRIC(unit) ? (element_index / SOC_DPP_DEFS_GET(unit, nof_queues_per_pipe)) : 0) 116 #define DPP_DEVICE_PETRA_VOQ_HD_ID(unit, core, element_index) ((core != BCM_CORE_ALL && !SOC_DPP_CORE_MODE_IS_SYMMETRIC(unit)) ? (element_index - (core * SOC_DPP_DEFS_GET(unit, nof_queues_per_pipe))) : element_index) 117 #define DPP_DEVICE_PETRA_VOQ_HD_ELEMENT(unit, core, voq_index) ((core != BCM_CORE_ALL && !SOC_DPP_CORE_MODE_IS_SYMMETRIC(unit)) ? (voq_index + (core * SOC_DPP_DEFS_GET(unit, nof_queues_per_pipe))) : voq_index) 118 119 #define DPP_DEVICE_PETRA_COSQ_QUEUE_QUARTET_DIVISOR 4 120 #define DPP_DEVICE_INGR_QUEUE_PRI_TEMPLATE_MAX 3 /* hi/lo ingress priority queue template ndx */ 121 #define DPP_DEVICE_INGR_QUEUE_PRI_TEMPLATE_REGION_SIZE 64 /* hi/lo queue region size 64 queues */ 122 123 #define DPP_DEVICE_COSQ_HR_MASK (BCM_COSQ_GPORT_SCHEDULER_HR_DUAL_WFQ | \ 124 BCM_COSQ_GPORT_SCHEDULER_HR_ENHANCED | \ 125 BCM_COSQ_GPORT_SCHEDULER_HR_SINGLE_WFQ) 126 127 #define DPP_DEVICE_COSQ_CL_MASK (BCM_COSQ_GPORT_SCHEDULER_CLASS_MODE1_4SP | \ 128 BCM_COSQ_GPORT_SCHEDULER_CLASS_MODE2_3SP_WFQ | \ 129 BCM_COSQ_GPORT_SCHEDULER_CLASS_MODE3_WFQ_2SP | \ 130 BCM_COSQ_GPORT_SCHEDULER_CLASS_MODE4_2SP_WFQ | \ 131 BCM_COSQ_GPORT_SCHEDULER_CLASS_MODE5_1SP_WFQ) 132 133 #define DPP_DEVICE_COSQ_CL_ENHANCED_MASK (BCM_COSQ_GPORT_SCHEDULER_CLASS_ENHANCED_LOWPRI_FQ | \ 134 BCM_COSQ_GPORT_SCHEDULER_CLASS_ENHANCED_HIGHPRI_FQ) 135 136 #define DPP_DEVICE_COSQ_CL_WFQ_MASK (BCM_COSQ_GPORT_SCHEDULER_CLASS_WFQ_MODE_DISCREET | \ 137 BCM_COSQ_GPORT_SCHEDULER_CLASS_WFQ_MODE_CLASS | \ 138 BCM_COSQ_GPORT_SCHEDULER_CLASS_WFQ_MODE_INDEPENDENT| \ 139 BCM_COSQ_GPORT_SCHEDULER_CLASS_WFQ_MODE_INDEPENDENT_PROPORTIONAL) 140 141 #define DPP_DEVICE_COSQ_DUAL_SHAPER_MASK (BCM_COSQ_GPORT_SCHEDULER_DUAL_SHAPER) 142 143 #define DPP_DEVICE_COSQ_FQ_MASK (BCM_COSQ_GPORT_SCHEDULER_FQ) 144 145 #define DPP_DEVICE_COSQ_MAX_COS 8 146 #define DPP_DEVICE_COSQ_COS_ALLOC_SZ 4 147 148 /* currently used for SE resources */ 149 #define DPP_DEVICE_COSQ_RESOURCE_ALLOC_NREF_VALUE 1 150 151 /* number of profiles handled for egress queue mapping */ 152 #define DPP_DEVICE_COSQ_EGRESS_QUEUE_MAP_NOF_PROFILES (4) 153 /* number of profiles handled for egress thresholds & fcs */ 154 155 #define DPP_DEVICE_COSQ_EGR_NOF_Q_PRIO(unit) (SOC_DPP_CONFIG(unit)->tm.max_egr_q_prio) 156 #define DPP_DEVICE_COSQ_EGR_NOF_Q_PRIO_MAX (SOC_TMC_EGR_NOF_Q_PRIO_ARAD) 157 #define DPP_DEVICE_COSQ_EGR_NOF_DP (4) 158 #define DPP_DEVICE_COSQ_EGR_NOF_TC (8) 159 #define DPP_DEVICE_COSQ_EGR_NOF_Q_PRIO_MAPPING_TYPES (SOC_TMC_EGR_NOF_Q_PRIO_MAPPING_TYPES) 160 #define DPP_DEVICE_COSQ_ING_NOF_TC (8) 161 #define DPP_DEVICE_COSQ_ING_NOF_DP (4) 162 163 164 #define DPP_DEVICE_COSQ_VSQ_NOF_CATEGORY(unit) (SOC_DPP_CONFIG(unit)->tm.nof_vsq_category) 165 #define DPP_DEVICE_COSQ_VSQ_NOF_CATEGORY_MAX (SOC_TMC_NOF_VSQ_GROUPS) 166 #define DPP_DEVICE_COSQ_VSQ_NOF_RSRC_POOLS(unit) (SOC_IS_ARADPLUS_AND_BELOW(unit) ? 1 : SOC_TMC_ITM_NOF_RSRC_POOLS) 167 #define DPP_DEVICE_COSQ_VSQ_NOF_SRC_BASED_VSQS (SOC_TMC_NOF_SRC_BASED_VSQ_GROUPS) 168 #define DPP_DEVICE_COSQ_VSQ_NOF_NON_SRC_BASED_VSQS (SOC_TMC_NOF_VSQ_GROUPS - SOC_TMC_NOF_SRC_BASED_VSQ_GROUPS) 169 170 #define DPP_DEVICE_COSQ_QUEUE_NOF_CATEGORY (4) 171 172 #define DPP_DEVICE_COSQ_CL_SE_ID_MIN_ARAD SOC_TMC_CL_SE_ID_MIN_ARAD 173 #define DPP_DEVICE_COSQ_CL_SE_ID_MAX_ARAD SOC_TMC_CL_SE_ID_MAX_ARAD 174 #define DPP_DEVICE_COSQ_FQ_SE_ID_MIN_ARAD SOC_TMC_FQ_SE_ID_MIN_ARAD 175 #define DPP_DEVICE_COSQ_FQ_SE_ID_MAX_ARAD SOC_TMC_FQ_SE_ID_MAX_ARAD 176 #define DPP_DEVICE_COSQ_HR_SE_ID_MIN_ARAD SOC_TMC_HR_SE_ID_MIN_ARAD 177 #define DPP_DEVICE_COSQ_HR_SE_ID_MAX_ARAD SOC_TMC_HR_SE_ID_MAX_ARAD 178 #define DPP_DEVICE_COSQ_SCH_FLOW_ID_INVALID_ARAD SOC_TMC_SCH_FLOW_ID_INVALID_ARAD 179 180 #define DPP_DEVICE_COSQ_NBR_QUEUES_IN_QUARTET 4 181 #define DPP_DEVICE_COSQ_NBR_QUEUES_IN_REGION 1024 182 #define BCM_DEVICE_PETRA_COSQ_QUEUE_QUAD_GET(qid) (qid/DPP_DEVICE_COSQ_NBR_QUEUES_IN_QUARTET) 183 #define BCM_DEVICE_PETRA_COSQ_QUEUE_REGION_GET(qid) (qid/DPP_DEVICE_COSQ_NBR_QUEUES_IN_REGION) 184 #define BCM_DEVICE_PETRA_COSQ_FLOW_REGION_GET(flow_id) (flow_id/DPP_DEVICE_COSQ_NBR_QUEUES_IN_REGION) 185 186 #define BCM_DEVICE_PETRA_COSQ_DWEIGHT_MAX_INDEX 4 187 188 /* start of interface range in gport port definition */ 189 #define BCM_DPP_PORT_INTERFACE_START SOC_DPP_PORT_INTERFACE_START 190 #define BCM_DPP_PORT_INTERFACE_END SOC_DPP_PORT_INTERFACE_END 191 #define BCM_DPP_PORT_INTERNAL_OLP(core) SOC_DPP_PORT_INTERNAL_OLP(core) 192 #define BCM_DPP_PORT_INTERNAL_ERP(core) SOC_DPP_PORT_INTERNAL_ERP(core) 193 #define BCM_DPP_PORT_INTERNAL_OAMP(core) SOC_DPP_PORT_INTERNAL_OAMP(core) 194 195 #define BCM_DPP_PORT_IS_INTERFACE(port) \ 196 (((port) >= BCM_DPP_PORT_INTERFACE_START) && ((port) <= BCM_DPP_PORT_INTERFACE_END)) 197 198 199 /* default egr tc/dp map profile */ 200 #define DPP_COSQ_PB_EGR_QUEUE_DEFAULT_PROFILE_MAP (0) 201 202 #define DPP_COSQ_EG_DISCOUNT_DEFAULT_VALUE (0) 203 204 #define BCM_PETRA_COSQ_QUEUE_RANGE_SET_MIN 0 205 #define BCM_PETRA_COSQ_QUEUE_RANGE_SET_MAX 1 206 #define BCM_PETRA_COSQ_QUEUE_RANGE_SET_BOTH 2 207 208 #define BCM_INT_DPP_COSQ_GPORT_COMPOSITE_SF2_TYPE_GET(type, gport_sf2) \ 209 { \ 210 if (_SHR_COSQ_GPORT_IS_COMPOSITE_SF2(gport_sf2)) { \ 211 if ((_SHR_COSQ_GPORT_RESERVED_TYPE_GET(gport_sf2)) == _SHR_COSQ_EXT_GPORT_RESERVED_VOQ_CONNECTOR) { \ 212 (type) = BCM_COSQ_GPORT_TYPE_VOQ_CONNECTOR; \ 213 } else { \ 214 (type) = BCM_GPORT_TYPE_SCHEDULER; \ 215 } \ 216 } \ 217 } 218 219 #define BCM_DPP_SCHEDULER_ONLY_CORE_SET(gport, core) _SHR_GPORT_SCHEDULER_ONLY_CORE_SET(gport, core) 220 /* 221 * FMQ Definitions 222 */ 223 #define DPP_DEVICE_FMQ_CLASS_PORTS 4 224 #define DPP_DEVICE_COSQ_FMQ_NON_ENHANCED_QID_MIN 0 225 #define DPP_DEVICE_COSQ_FMQ_NON_ENHANCED_QID_MAX 3 226 227 228 /* Scheduler attributes per device */ 229 #define DPP_COSQ_SCH_MAX_FLOW_ID(unit) (SOC_DPP_CONFIG(unit)->tm.max_connectors-1) 230 #define DPP_COSQ_SCH_MAX_PORT_ID(unit) (SOC_TMC_SCH_MAX_PORT_ID_ARAD) 231 #define DPP_COSQ_SCH_PORT_ID_INVALID(unit) (SOC_DPP_CONFIG(unit)->tm.invalid_port_id_num) 232 #define DPP_COSQ_SCH_SE_ID_INVALID(unit) (SOC_DPP_CONFIG(unit)->tm.invalid_se_id_num) 233 #define DPP_COSQ_SCH_FLOW_ID_INVALID(unit) (SOC_DPP_CONFIG(unit)->tm.invalid_voq_connector_id_num) 234 235 /* Cosq gport fabric pipes WFQ whight check */ 236 #define DPP_COSQ_GPORT_FABRIC_PIPE_WFQ_WHIGHT_MAX (127) 237 #define DPP_COSQ_GPORT_FABRIC_PIPE_WFQ_WHIGHT_IS_VALID(weight)\ 238 ((weight > 0) && (weight <= DPP_COSQ_GPORT_FABRIC_PIPE_WFQ_WHIGHT_MAX)) 239 240 /* iterate over all cores */ 241 #define BCM_DPP_CORES_ITER(core_id, index) SOC_DPP_CORES_ITER(core_id, index) 242 #define BCM_DPP_ASSYMETRIC_CORES_ITER(core_id, index) SOC_DPP_ASSYMETRIC_CORES_ITER(core_id, index) 243 244 /*flow ids QAX offsets - QAXs flow_ndx range is 64k-128k, so user flow_id input needs to be shifted*/ 245 /*flow ids QUX offsets - QUXs flow_ndx range is 96k-128k, so user flow_id input needs to be shifted*/ 246 #define QAX_FLOW_ID_OFFSET(unit) (SOC_IS_QUX(unit) ? (96*1024) : (64*1024)) 247 #define BCM_COSQ_FLOW_ID_QAX_ADD_OFFSET(unit, id) (id + QAX_FLOW_ID_OFFSET(unit)) 248 #define BCM_COSQ_FLOW_ID_QAX_SUB_OFFSET(unit, id) (id - QAX_FLOW_ID_OFFSET(unit)) 249 250 251 typedef enum dpp_device_cosq_region_type_e 252 { 253 DPP_DEVICE_COSQ_REGION_TYPE0 = 0,/* connector flows */ 254 DPP_DEVICE_COSQ_REGION_TYPE1 = 1,/* {connector, SE} flows is_cl_cir*/ 255 DPP_DEVICE_COSQ_REGION_TYPE2 = 2, /* {connector, SE} flows not odd_even is_cl_cir*/ 256 DPP_DEVICE_COSQ_REGION_TYPE3 = 3, /* {connector, SE} flows not odd_even - HR */ 257 DPP_DEVICE_COSQ_REGION_TYPE5 = 5,/* {connector, SE} flows not is_cl_cir*/ 258 DPP_DEVICE_COSQ_REGION_TYPE6 = 6, /* {connector, SE} flows not odd_even not is_cl_cir*/ 259 DPP_DEVICE_COSQ_REGION_TYPE_LAST 260 } dpp_device_cosq_region_type_t; 261 262 263 typedef enum bcm_dpp_cl_scheduler_profile_e { 264 bcm_dpp_cosq_cl_cid_mode3_ind, 265 bcm_dpp_cosq_cl_cid_mode3_ind_ehp_fq, 266 bcm_dpp_cosq_cl_cid_mode3_ind_elp_fq, 267 bcm_dpp_cosq_cl_cid_mode4_ind, 268 bcm_dpp_cosq_cl_cid_mode4_ind_ehp_fq, 269 bcm_dpp_cosq_cl_cid_mode4_ind_elp_fq, 270 bcm_dpp_cosq_cl_cid_mode5_ind, 271 bcm_dpp_cosq_cl_cid_mode5_ind_ehp_fq, 272 bcm_dpp_cosq_cl_cid_mode5_ind_elp_fq, 273 274 bcm_dpp_cosq_cl_cid_mode1, 275 bcm_dpp_cosq_cl_cid_mode1_ehp_fq, 276 bcm_dpp_cosq_cl_cid_mode1_elp_fq, 277 278 279 /* template management */ 280 bcm_dpp_cosq_cl_cid_mode3_des, 281 bcm_dpp_cosq_cl_cid_mode3_des_ehp_fq, 282 bcm_dpp_cosq_cl_cid_mode3_des_elp_fq, 283 bcm_dpp_cosq_cl_cid_mode4_des, 284 bcm_dpp_cosq_cl_cid_mode4_des_ehp_fq, 285 bcm_dpp_cosq_cl_cid_mode4_des_elp_fq, 286 bcm_dpp_cosq_cl_cid_mode5_des, 287 bcm_dpp_cosq_cl_cid_mode5_des_ehp_fq, 288 bcm_dpp_cosq_cl_cid_mode5_des_elp_fq, 289 bcm_dpp_cosq_cl_cid_mode2_des, 290 bcm_dpp_cosq_cl_cid_mode2_des_ehp_fq, 291 bcm_dpp_cosq_cl_cid_mode2_des_elp_fq, 292 bcm_dpp_cosq_cl_cid_mode3_cls, 293 bcm_dpp_cosq_cl_cid_mode3_cls_ehp_fq, 294 bcm_dpp_cosq_cl_cid_mode3_cls_elp_fq, 295 bcm_dpp_cosq_cl_cid_mode4_cls, 296 bcm_dpp_cosq_cl_cid_mode4_cls_ehp_fq, 297 bcm_dpp_cosq_cl_cid_mode4_cls_elp_fq, 298 bcm_dpp_cosq_cl_cid_mode5_cls, 299 bcm_dpp_cosq_cl_cid_mode5_cls_ehp_fq, 300 bcm_dpp_cosq_cl_cid_mode5_cls_elp_fq, 301 bcm_dpp_cosq_cl_cid_mode2_cls, 302 bcm_dpp_cosq_cl_cid_mode2_cls_ehp_fq, 303 bcm_dpp_cosq_cl_cid_mode2_cls_elp_fq, 304 305 bcm_dpp_cosq_cl_cid_last /* last one. This and following one's are managed profiles. Ref note */ 306 } bcm_dpp_cosq_cl_scheduler_profiles_t; 307 308 #define DPP_DEVICE_COSQ_CL_CLASS_TABLE_INIT(class_tbl, cid, cl_mode, emode, weight_type, weights) \ 309 class_tbl->class_types[cid].id = cid; \ 310 class_tbl->class_types[cid].mode = cl_mode; \ 311 class_tbl->class_types[cid].enhanced_mode = emode; \ 312 class_tbl->class_types[cid].weight_mode = weight_type; \ 313 if ( (weight_type == SOC_TMC_SCH_CL_WEIGHTS_MODE_INDEPENDENT_PER_FLOW) || \ 314 (weight_type == SOC_TMC_SCH_CL_CLASS_WEIGHTS_MODE_LAST) ) { \ 315 class_tbl->class_types[cid].weight[0] = 0; \ 316 class_tbl->class_types[cid].weight[1] = 0; \ 317 class_tbl->class_types[cid].weight[2] = 0; \ 318 class_tbl->class_types[cid].weight[3] = 0; \ 319 } \ 320 else { \ 321 class_tbl->class_types[cid].weight[0] = *(weights + 0); \ 322 class_tbl->class_types[cid].weight[1] = *(weights + 1); \ 323 class_tbl->class_types[cid].weight[2] = *(weights + 2); \ 324 class_tbl->class_types[cid].weight[3] = *(weights + 3); \ 325 } 326 327 #define DPP_DEVICE_COSQ_CLASS_INFO_INIT(info, class_type, mode_weight, weight_max, dclass_max) \ 328 info->type = class_type; \ 329 info->weight_mode = mode_weight; \ 330 info->max_weight = weight_max; \ 331 info->max_discrete_class = dclass_max; 332 333 #define DPP_DEVICE_COSQ_CL_CLASS_DATA_INIT(class_data, cl_mode, emode, weight_type, weights) \ 334 class_data.mode = cl_mode; \ 335 class_data.enhanced_mode = emode; \ 336 class_data.weight_mode = weight_type; \ 337 class_data.weights[0] = weights[0]; \ 338 class_data.weights[1] = weights[1]; \ 339 class_data.weights[2] = weights[2]; \ 340 class_data.weights[3] = weights[3]; 341 342 typedef enum bcm_dpp_cosq_gport_type_info_e { 343 dpp_device_cosq_gport_child_element = 0x1, 344 dpp_device_cosq_gport_parent_element = 0x2, 345 dpp_device_cosq_gport_sched_nocirpir_ds_element = 0x4, 346 dpp_device_cosq_gport_connector_element = 0x8 347 } bcm_dpp_cosq_gport_type_info_t; 348 349 typedef enum bcm_dpp_cosq_hdlist_type_e { 350 dpp_cosq_hdlist_voq_group = 0, /* queue group data structures */ 351 dpp_cosq_hdlist_connector_group, /* connector group data structure */ 352 dpp_cosq_hdlist_se, /* se data structures */ 353 dpp_cosq_hdlist_flow, /* each flow data structure (applicable to connector/SE resources */ 354 dpp_cosq_hdlist_invalid 355 } bcm_dpp_cosq_hdlist_type_t; 356 357 /* 358 * Data structures 359 */ 360 361 /* enumerations for "flag" parameter in resource data structures */ 362 363 typedef struct bcm_dpp_cosq_gport_info_s { 364 int is_connector; /* connector */ 365 int is_se; /* se */ 366 int is_composite; /* valid for connector and SE */ 367 int is_non_contiguous; /* valid if is_connector=FALSE */ 368 int is_dual; /* dual configuation */ 369 int is_sf2; /* sf2 request */ 370 int flow_id; /* flow_id corresonding to the gport */ 371 int se_id; /* valid if is_connector=FALSE */ 372 int actual_flow_id; 373 SOC_TMC_SCH_FLOW *flow_config; 374 SOC_TMC_SCH_SE_INFO *se_config; 375 } bcm_dpp_cosq_gport_info_t; 376 377 typedef struct bcm_dpp_cosq_sched_class_info_s { 378 int mode; 379 int enhanced_mode; 380 int weight_mode; 381 int weights[SOC_TMC_SCH_MAX_NOF_DISCRETE_WEIGHT_VALS]; 382 } bcm_dpp_cosq_sched_class_data_t; 383 384 typedef struct bcm_dpp_cosq_class_info_s { 385 int type; /* type */ 386 int weight_mode; /* weight mode */ 387 int max_weight; /* max weights if weight mode is independent */ 388 int max_discrete_class; /* max discrete classes if weight mode is discrete */ 389 } bcm_dpp_cosq_class_info_t; 390 391 typedef struct { 392 393 bcm_gport_t base_queue; 394 int num_cos; 395 396 }bcm_dpp_gport_state; 397 398 399 /* 400 * Data structures for various resources (voq, connector, se, flows) 401 * data structure fields kept to minimum. State learnt from h/w where possible 402 */ 403 /* voq group data structure */ 404 typedef struct bcm_dpp_cosq_voq_config_s { /* Queue group */ 405 uint8 num_cos; 406 uint8 flags; 407 uint32 ref_cnt; 408 } bcm_dpp_cosq_voq_config_t; 409 410 /* connector group data structure */ 411 /* 412 * Definitions related to bit map on 'flags' element. 413 * { 414 */ 415 /* 416 * If the bit covered by CONNECTION_IS_VALID_MASK is set then 417 * corresponding tables (FQM/FFM) have been loaded by legitimate 418 * values. 419 */ 420 #define CONNECTION_IS_VALID_MASK (0x1 << 0) 421 /* 422 * } 423 */ 424 typedef struct bcm_dpp_cosq_connector_config_s { /* Connector Group */ 425 /* 426 * Number of queues on this group. If set to zero then this 427 * group is not in use (removed). 428 */ 429 uint8 num_cos; 430 uint8 flags; 431 #ifdef BCM_DPP_COSQ_CONN_NO_MODID_OPTIMIZATION 432 uint8 src_modid; 433 #endif /* BCM_DPP_COSQ_CONN_NO_MODID_OPTIMIZATION */ 434 uint32 ref_cnt; 435 } bcm_dpp_cosq_connector_config_t; 436 437 /* se data structure */ 438 typedef struct bcm_dpp_cosq_se_config_s { /* Scheduler */ 439 uint32 ref_cnt; /* reference DPP_DEVICE_COSQ_RESOURCE_ALLOC_NREF_VALUE definition */ 440 } bcm_dpp_cosq_se_config_t; 441 442 /* flow data structure */ 443 typedef struct bcm_dpp_cosq_flow_config_s { /* flows - Connectors/SEs */ 444 int weight; 445 /* 0 => implies no weight, */ 446 /* +ve value => normal meaning */ 447 /* -ve value => attach sub-point */ 448 int mode; /* mode saved from the sched_set of the SE */ 449 } bcm_dpp_cosq_flow_config_t; 450 451 typedef struct bcm_dpp_cosq_list_hd_s { 452 PARSER_HINT_ARR bcm_dpp_cosq_voq_config_t *voq_buf; 453 PARSER_HINT_ARR bcm_dpp_cosq_connector_config_t *connector_buf; 454 PARSER_HINT_ARR bcm_dpp_cosq_se_config_t *se_buf; 455 PARSER_HINT_ARR bcm_dpp_cosq_flow_config_t *flow_buf; 456 int num_elements; 457 bcm_dpp_cosq_hdlist_type_t type; 458 } bcm_dpp_cosq_list_hd_t; 459 460 typedef struct bcm_dpp_cosq_rx_cal_s { 461 int valid; 462 int intf; 463 int cal_mode_ndx; 464 } bcm_dpp_cosq_rx_cal_t; 465 466 typedef struct bcm_dpp_cosq_tx_cal_s { 467 int valid; 468 int intf; 469 int cal_mode_ndx; 470 } bcm_dpp_cosq_tx_cal_t; 471 472 typedef struct bcm_dpp_cosq_cal_s { 473 bcm_dpp_cosq_rx_cal_t rx; 474 bcm_dpp_cosq_tx_cal_t tx; 475 } bcm_dpp_cosq_cal_t; 476 477 typedef enum bcm_dpp_cosq_pfc_rx_type_e { 478 _BCM_DPP_COSQ_PFC_RX_NONE = 0x0, 479 _BCM_DPP_COSQ_PFC_RX_DEFAULT = 0x1, 480 _BCM_DPP_COSQ_PFC_RX_PORT_OVER = 0x2, 481 _BCM_DPP_COSQ_PFC_RX_INTF_COSQ = 0x3, 482 _BCM_DPP_COSQ_PFC_RX_LAST = 0x4 483 } bcm_dpp_cosq_pfc_rx_type_t; 484 485 typedef struct bcm_dpp_cosq_ingress_config_s { 486 bcm_fabric_vsq_category_mode_t vsq_category_mode; 487 int ucast_qid_start; 488 int ucast_qid_end; 489 } bcm_dpp_cosq_ingress_config_t; 490 491 typedef struct bcm_dpp_cosq_config_new_s { 492 int hr_fc_default_template; 493 int hr_fc_default_template_data; 494 SOC_TMC_SCH_SE_TYPE default_se_type; 495 int default_se_class; 496 uint32 voq_flags; /* e.g. sequencing state */ 497 uint32 connector_flags; /* e.g. sequencing state */ 498 uint32 se_flags; /* e.g. sequencing state */ 499 bcm_dpp_cosq_se_config_t se_config; 500 SOC_TMC_SCH_SE_ID default_se[SOC_DPP_DEFS_MAX(NOF_CORES)] ; 501 int default_se_flow[SOC_DPP_DEFS_MAX(NOF_CORES)] ; 502 bcm_gport_t isq_port[SOC_DPP_DEFS_MAX(NOF_CORES)]; 503 bcm_gport_t fmq_class_ports[SOC_DPP_DEFS_MAX(NOF_CORES)][DPP_DEVICE_FMQ_CLASS_PORTS]; 504 bcm_dpp_cosq_voq_config_t voq_config[DPP_DEVICE_COSQ_MAX_COS]; 505 bcm_dpp_cosq_connector_config_t connector_config[DPP_DEVICE_COSQ_MAX_COS]; 506 bcm_dpp_cosq_cal_t inband_cal[SOC_DPP_MAX_INTERLAKEN_PORTS]; 507 bcm_dpp_cosq_cal_t oob_cal[SOC_DPP_MAX_OOB_PORTS]; 508 bcm_dpp_cosq_pfc_rx_type_t rx_pfc_map_info[SOC_MAX_NUM_PORTS]; 509 bcm_dpp_cosq_ingress_config_t ingress[SOC_DPP_DEFS_MAX(NOF_CORES)]; 510 bcm_dpp_cosq_list_hd_t voq_hd[1]; 511 bcm_dpp_cosq_list_hd_t flow_hd[SOC_DPP_DEFS_MAX(NOF_CORES)]; 512 bcm_dpp_cosq_list_hd_t connector_hd[SOC_DPP_DEFS_MAX(NOF_CORES)] ; 513 bcm_dpp_cosq_list_hd_t se_hd[SOC_DPP_DEFS_MAX(NOF_CORES)] ; 514 } bcm_dpp_cosq_config_t; 515 516 517 typedef struct { 518 int max_entries; 519 /* maximium regions entries that can be present */ 520 int valid_entries; 521 /* valid regions entries that are present */ 522 PARSER_HINT_ARR int *entries; 523 /* region info */ 524 } bcm_dpp_am_cosq_pool_ref_t; 525 526 typedef struct { 527 int is_quad_region_allocated; /* is 4K region allocated */ 528 int is_interdigitated; /* is 4K region interdigitated */ 529 } bcm_dpp_am_cosq_interdigitated_ref_t; 530 531 typedef struct { 532 int is_valid; /* region is valid */ 533 int is_dynamic; /* region is dynamically allocated */ 534 int pool_id; /* region pool id */ 535 int type_id; /* region type id */ 536 int type; /* region type */ 537 int p_pool_id; /* region parent pool id */ 538 SHR_BITDCL res[SHR_BITALLOCSIZE(DPP_DEVICE_COSQ_MAX_REGION_VAL+1)]; /* reference to original region resource */ 539 int start; /* resource start */ 540 int count; /* count of resources */ 541 } bcm_dpp_am_cosq_pool_entry_t; 542 543 typedef struct { 544 int max_entries; 545 /* maximium regions entries that can be present */ 546 int valid_entries; 547 /* valid regions entries that are present */ 548 PARSER_HINT_ARR bcm_dpp_am_cosq_pool_entry_t *entries; 549 /* region info */ 550 } bcm_dpp_am_cosq_pool_info_t; 551 552 typedef struct { 553 /* E2E */ 554 SHR_BITDCL *e2e_fixed_res; 555 /* e2e total static/fixed resources reference (bitmap) */ 556 557 bcm_dpp_am_cosq_pool_info_t e2e_total_res_pool; 558 /* e2e worst case free dynamic resource pool info */ 559 bcm_dpp_am_cosq_pool_ref_t connector_cont_res_pool_ref; 560 /* connector contiguous resource pool info */ 561 bcm_dpp_am_cosq_pool_ref_t connector_non_cont_region_type_1_res_pool_ref; 562 /* connector non-contiguous resource pool info */ 563 bcm_dpp_am_cosq_pool_ref_t connector_non_cont_region_type_2_res_pool_ref; 564 /* connector non-contiguous resource pool info */ 565 bcm_dpp_am_cosq_pool_ref_t se_cl_fq_region_type_1_res_pool_ref; 566 /* connector se {cl, fq} resource pool info */ 567 bcm_dpp_am_cosq_pool_ref_t se_cl_fq_region_type_2_res_pool_ref; 568 /* connector se {cl, fq} resource pool info */ 569 bcm_dpp_am_cosq_pool_ref_t se_cl_hr_res_pool_ref; 570 /* connector se {cl, hr} resource pool info */ 571 bcm_dpp_am_cosq_pool_ref_t fq_connector_region_type_2_sync_res_pool_ref; 572 /* connector se {connector, fq} odd even synce resource pool info */ 573 bcm_dpp_am_cosq_pool_ref_t hr_connector_region_type_2_sync_res_pool_ref; 574 /* connector se {connector, hr} odd even synce resource pool info */ 575 576 /* Queue */ 577 SHR_BITDCL *queue_fixed_res; 578 SHR_BITDCL *queue_unicast_total_dynamic_res; 579 /* queue total dynamic resources reference (bitmap) */ 580 SHR_BITDCL *queue_unicast_free_dynamic_res; 581 /* queue free dynamic resources reference (bitmap) */ 582 SHR_BITDCL *queue_multicast_total_dynamic_res; 583 /* queue total dynamic resources reference (bitmap) */ 584 SHR_BITDCL *queue_multicast_free_dynamic_res; 585 SHR_BITDCL *queue_isq_total_dynamic_res; 586 /* queue total dynamic resources reference (bitmap) */ 587 SHR_BITDCL *queue_isq_free_dynamic_res; 588 /* queue free dynamic resources reference (bitmap) */ 589 590 PARSER_HINT_ARR bcm_dpp_am_cosq_interdigitated_ref_t *quad_interdigitated_res; 591 /* 4K region interdigitated info */ 592 593 bcm_dpp_am_cosq_pool_ref_t queue_unicast_cont_res_pool_ref; 594 /* queue contiguous resource pool info */ 595 bcm_dpp_am_cosq_pool_ref_t queue_unicast_non_cont_res_pool_ref; 596 /* queue non-contiguous resource pool info */ 597 bcm_dpp_am_cosq_pool_ref_t queue_multicast_cont_res_pool_ref; 598 /* queue contiguous resource pool info */ 599 bcm_dpp_am_cosq_pool_ref_t queue_multicast_non_cont_res_pool_ref; 600 /* queue non-contiguous resource pool info */ 601 bcm_dpp_am_cosq_pool_ref_t queue_isq_cont_res_pool_ref; 602 /* queue contiguous resource pool info */ 603 bcm_dpp_am_cosq_pool_ref_t queue_isq_non_cont_res_pool_ref; 604 /* queue non-contiguous resource pool info */ 605 bcm_dpp_am_cosq_pool_info_t queue_total_res_pool; 606 /* queue worst case free dynamic resource pool info */ 607 608 } bcm_dpp_am_cosq_res_info_t; 609 610 typedef enum { 611 e2e_fixed_res_bmp, 612 queue_fixed_res_bmp, 613 queue_unicast_total_dynamic_res_bmp, 614 queue_unicast_free_dynamic_res_bmp, 615 queue_multicast_total_dynamic_res_bmp, 616 queue_multicast_free_dynamic_res_bmp, 617 queue_isq_total_dynamic_res_bmp, 618 queue_isq_free_dynamic_res_bmp, 619 e2e_total_res_pool_type_bmp, 620 queue_total_res_pool_type_bmp 621 } bcm_dpp_cosq_bmp_type_t; 622 623 typedef enum { 624 connector_cont_res_pool_ref_type, 625 connector_non_cont_region_type_1_res_pool_ref_type, 626 connector_non_cont_region_type_2_res_pool_ref_type, 627 se_cl_fq_region_type_1_res_pool_ref_type, 628 se_cl_fq_region_type_2_res_pool_ref_type, 629 se_cl_hr_res_pool_ref_type, 630 fq_connector_region_type_2_sync_res_pool_ref_type, 631 hr_connector_region_type_2_sync_res_pool_ref_type, 632 queue_unicast_cont_res_pool_ref_type, 633 queue_unicast_non_cont_res_pool_ref_type, 634 queue_multicast_cont_res_pool_ref_type, 635 queue_multicast_non_cont_res_pool_ref_type, 636 queue_isq_cont_res_pool_ref_type, 637 queue_isq_non_cont_res_pool_ref_type 638 } bcm_dpp_am_cosq_pool_ref_type_t; 639 640 typedef enum { 641 max_entries_field, 642 valid_entries_field, 643 entries_field 644 } bcm_dpp_am_cosq_pool_ref_field_t; 645 646 typedef enum { 647 e2e_total_res_pool_type, 648 queue_total_res_pool_type 649 } bcm_dpp_am_cosq_pool_info_type_t; 650 651 #define BCM_DPP_AM_COSQ_SCH_NOF_ALLOCATION_SCHEMES 48 652 653 typedef struct bcm_dpp_cosq_info_s { 654 bcm_dpp_cosq_config_t cosq_config; 655 bcm_dpp_am_cosq_res_info_t cosq_res_info[SOC_DPP_DEFS_MAX(NOF_CORES)]; 656 } bcm_dpp_cosq_info_t; 657 658 659 typedef struct bcm_dpp_cosq_egress_thresh_key_info_s { 660 661 /* Soc_petra B*/ 662 663 /* Schedule (UC) words consumed per priority - Soc_petra-B*/ 664 uint32 sch_drop_words_consumed[DPP_DEVICE_COSQ_EGR_NOF_Q_PRIO_MAX]; 665 /* Unschedule (MC) words consumed per {priority,dp} - Soc_petra-B*/ 666 uint32 unsch_drop_words_consumed[DPP_DEVICE_COSQ_EGR_NOF_Q_PRIO_MAX][DPP_DEVICE_COSQ_EGR_NOF_DP]; 667 /* Schedule (UC) pkts consumed per priority - Soc_petra-B */ 668 uint32 sch_drop_pkts_consumed[DPP_DEVICE_COSQ_EGR_NOF_Q_PRIO_MAX]; 669 /* Unschedule (MC) pkts consumed per {priority,dp} - Soc_petra-B*/ 670 uint32 unsch_drop_pkts_consumed[DPP_DEVICE_COSQ_EGR_NOF_Q_PRIO_MAX][DPP_DEVICE_COSQ_EGR_NOF_DP]; 671 /* Schedule (UC) flow control words consumed per priority - Soc_petra-B*/ 672 uint32 sch_fc_words_consumed[DPP_DEVICE_COSQ_EGR_NOF_Q_PRIO_MAX]; 673 674 /* ARAD */ 675 676 /* Schedule (UC) packet descriptors - ARAD */ 677 uint32 sch_drop_packet_descriptors; 678 /* Schedule (UC) packet descriptors per tc - ARAD */ 679 uint32 sch_drop_packet_descriptors_tc[DPP_DEVICE_COSQ_EGR_NOF_TC]; 680 /* Unschedule (MC) packet descriptors per - ARAD */ 681 uint32 unsch_drop_packet_descriptors; 682 /* Unschedule (MC) packet descriptors per {tc,dp} - ARAD*/ 683 uint32 unsch_drop_packet_descriptors_tc_dp[DPP_DEVICE_COSQ_EGR_NOF_TC][DPP_DEVICE_COSQ_EGR_NOF_DP]; 684 /* Schedule (UC) data buffers - ARAD*/ 685 uint32 sch_drop_data_buffers; 686 /* Schedule (UC) data buffers per tc - ARAD*/ 687 uint32 sch_drop_data_buffers_tc[DPP_DEVICE_COSQ_EGR_NOF_TC]; 688 /* Unschedule (MC) data buffers - ARAD*/ 689 uint32 unsch_drop_data_buffers; 690 /* Unschedule (MC) data buffers per {tc,dp} - ARAD*/ 691 uint32 unsch_drop_data_buffers_tc_dp[DPP_DEVICE_COSQ_EGR_NOF_TC][DPP_DEVICE_COSQ_EGR_NOF_DP]; 692 /* Schedule (UC) flow control packet descriptors - ARAD*/ 693 uint32 sch_fc_packet_descriptors; 694 /* Schedule (UC) flow control packet descriptors per tc - ARAD*/ 695 uint32 sch_fc_packet_descriptors_tc[DPP_DEVICE_COSQ_EGR_NOF_TC]; 696 /* Schedule (UC) flow control data buffers - ARAD*/ 697 uint32 sch_fc_data_buffers; 698 /* Schedule (UC) flow control data buffers per tc - ARAD*/ 699 uint32 sch_fc_data_buffers_tc[DPP_DEVICE_COSQ_EGR_NOF_TC]; 700 /* Unschedule (MC) data buffers available per tc - ARAD*/ 701 uint32 unsch_drop_packet_descriptors_available_tc[DPP_DEVICE_COSQ_EGR_NOF_TC]; 702 uint32 port_fc_packet_descriptors; 703 uint32 port_fc_data_buffers; 704 705 /* JERICHO */ 706 /* Min unschedule (MC) packet descriptors - JERICHO */ 707 uint32 unsch_drop_packet_descriptors_min; 708 /* Alpha for dynamic threshold unschedule (MC) packet descriptors - JERICHO */ 709 int32 unsch_drop_packet_descriptors_alpha; 710 /* Min and Alpha for Port level - FC*/ 711 uint32 port_fc_packet_descriptors_min; 712 int32 port_fc_packet_descriptors_alpha; 713 uint32 port_fc_data_buffers_min; 714 int32 port_fc_data_buffers_alpha; 715 716 /* Min unschedule (MC) packet descriptors per {tc,dp} - JERICHO*/ 717 uint32 unsch_drop_packet_descriptors_min_tc_dp[DPP_DEVICE_COSQ_EGR_NOF_TC][DPP_DEVICE_COSQ_EGR_NOF_DP]; 718 /* Alpha for dynamic threshold unschedule (MC) packet descriptors per {tc,dp} - JERICHO*/ 719 int32 unsch_drop_packet_descriptors_alpha_tc_dp[DPP_DEVICE_COSQ_EGR_NOF_TC][DPP_DEVICE_COSQ_EGR_NOF_DP]; 720 721 uint32 sch_fc_packet_descriptors_min_tc[DPP_DEVICE_COSQ_EGR_NOF_TC]; 722 int32 sch_fc_packet_descriptors_alpha_tc[DPP_DEVICE_COSQ_EGR_NOF_TC]; 723 uint32 sch_fc_data_buffers_min_tc[DPP_DEVICE_COSQ_EGR_NOF_TC]; 724 int32 sch_fc_data_buffers_alpha_tc[DPP_DEVICE_COSQ_EGR_NOF_TC]; 725 726 } bcm_dpp_cosq_egress_thresh_key_info_t; 727 728 typedef struct bcm_dpp_cosq_egress_interface_unicast_thresh_key_info_s { 729 730 /* ARAD */ 731 732 /* flow control words consumed - used for data buffers */ 733 uint32 fc_words_consumed; 734 /* flow control packet descriptors - ARAD */ 735 uint32 fc_packet_descriptors; 736 /* flow control pd/db - min, alpha- JER*/ 737 uint32 fc_packet_descriptors_min; 738 int32 fc_packet_descriptors_alpha; 739 uint32 fc_words_consumed_min; 740 int32 fc_words_consumed_alpha; 741 742 } bcm_dpp_cosq_egress_interface_unicast_thresh_key_info_t; 743 744 typedef struct bcm_dpp_cosq_egress_interface_multicast_thresh_key_info_s { 745 746 /* ARAD */ 747 748 /* packet descriptors - ARAD */ 749 uint32 packet_descriptors; 750 } bcm_dpp_cosq_egress_interface_multicast_thresh_key_info_t; 751 752 typedef struct bcm_dpp_cosq_egress_queue_mapping_info_s { 753 /* Schedule (UC) words consumed per priority */ 754 SOC_TMC_EGR_Q_PRIORITY queue_mapping[DPP_DEVICE_COSQ_EGR_NOF_Q_PRIO_MAPPING_TYPES][DPP_DEVICE_COSQ_ING_NOF_TC][DPP_DEVICE_COSQ_ING_NOF_DP]; 755 } bcm_dpp_cosq_egress_queue_mapping_info_t; 756 757 758 typedef enum { 759 DPP_COSQ_INGRESS_THRESHOLD_INVALID = -1, 760 DPP_COSQ_INGRESS_THRESHOLD_TOTAL_BYTES = 0, 761 DPP_COSQ_INGRESS_THRESHOLD_SRAM_BYTES, 762 DPP_COSQ_INGRESS_THRESHOLD_SRAM_PDS, 763 DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES 764 } bcm_dpp_cosq_ingress_threshold_type_e; 765 766 767 typedef struct { 768 uint32 min; 769 uint32 max; 770 int alpha; 771 772 } bcm_dpp_cosq_ingress_fadt_threshold_t; 773 774 typedef struct bcm_dpp_cosq_ingress_rate_class_info_s { 775 /* -------------- 776 * Tail Drop 777 * --------------*/ 778 /* Maximal queue size per DP in Buffer Descriptors */ 779 uint32 queue_max_size_bds[DPP_DEVICE_COSQ_ING_NOF_DP]; 780 /* queue size Alpha per DP in Buffer Descriptors */ 781 int8 queue_alpha_bds[DPP_DEVICE_COSQ_ING_NOF_DP]; 782 /* Jericho only -- Maximal queue OCB FADT settings per DP */ 783 bcm_dpp_cosq_ingress_fadt_threshold_t queue_ocb_fadt_tail_drop[DPP_DEVICE_COSQ_ING_NOF_DP]; 784 /* Jericho only -- static threshold on OCB free resources per DP */ 785 uint32 min_free_ocb_buffers[DPP_DEVICE_COSQ_ING_NOF_DP]; 786 787 /* Maximal queue size/FADT settings per DP */ 788 bcm_dpp_cosq_ingress_fadt_threshold_t queue_fadt_tail_drop[DPP_DEVICE_COSQ_ING_NOF_DP][DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES]; 789 790 /* -------------- 791 * Guaranteed 792 * --------------*/ 793 /* Guaranteed queue size in Buffer Descriptors -- not used in QAX and later */ 794 uint32 queue_min_size_bds; 795 /* Guaranteed queue size */ 796 uint32 queue_quaranteed_size[DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES]; 797 798 799 /* -------------- 800 * WRED Settings 801 * --------------*/ 802 /* Enable WRED algorithm test */ 803 uint8 wred_enable[DPP_DEVICE_COSQ_ING_NOF_DP]; 804 /* WRED Min queue average size */ 805 uint32 wred_min_avrg_th[DPP_DEVICE_COSQ_ING_NOF_DP]; 806 /* WRED Max queue average size */ 807 uint32 wred_max_avrg_th[DPP_DEVICE_COSQ_ING_NOF_DP]; 808 /* WRED ignore packet size */ 809 uint8 wred_ignore_packet_size[DPP_DEVICE_COSQ_ING_NOF_DP]; 810 /* WRED Max probability */ 811 uint32 wred_max_probability[DPP_DEVICE_COSQ_ING_NOF_DP]; 812 /* WRED exp. weight */ 813 uint32 wred_exp_wq; 814 815 /* -------------- 816 * OCB 817 * --------------*/ 818 /* Jericho and before only */ 819 SOC_TMC_MGMT_OCB_VOQ_INFO ocb_info[DPP_DEVICE_COSQ_ING_NOF_TC][DPP_DEVICE_COSQ_QUEUE_NOF_CATEGORY]; 820 821 /* QAX and later only */ 822 int ocb_only; 823 824 /* -------------- 825 * ECN Tail Drop 826 * --------------*/ 827 /* ECN max queue sizes (mark congestion above these sizes) */ 828 uint32 ecn_queue_max_size; /* size in bytes */ 829 uint32 ecn_queue_max_size_bds; /* size in BDs/buffers */ 830 831 /* -------------- 832 * ECN WRED settings 833 * --------------*/ 834 uint8 ecn_wred_enable; /* Enable WRED for marking congestion */ 835 uint32 ecn_wred_min_avrg_th; /* ECN WRED Min queue average size */ 836 uint32 ecn_wred_max_avrg_th; /* ECN WRED Max queue average size */ 837 uint8 ecn_wred_ignore_packet_size; /* ECN WRED ignore packet size */ 838 uint32 ecn_wred_max_probability; /* ECN WRED Max probability */ 839 840 /* -------------- 841 * System RED 842 * --------------*/ 843 SOC_TMC_ITM_SYS_RED_QT_INFO sys_red_qt; 844 SOC_TMC_ITM_SYS_RED_QT_DP_INFO sys_red_qt_dp[DPP_DEVICE_COSQ_ING_NOF_DP]; 845 846 /* -------------- 847 * DRAM Bound 848 * --------------*/ 849 SOC_TMC_ITM_DRAM_BOUND_INFO dram_bound_info; 850 851 } bcm_dpp_cosq_ingress_rate_class_info_t; 852 853 854 typedef enum { 855 BCM_DPP_COSQ_RATE_CLASS_ELEMENT_INVALID = -1, 856 BCM_DPP_COSQ_RATE_CLASS_ELEMENT_TAIL_DROP, 857 BCM_DPP_COSQ_RATE_CLASS_ELEMENT_WRED, 858 BCM_DPP_COSQ_RATE_CLASS_ELEMENT_DRAM_BOUND, 859 BCM_DPP_COSQ_RATE_CLASS_ELEMENT_DRAM_BOUND_RECOVERY, 860 BCM_DPP_COSQ_RATE_CLASS_ELEMENT_OCB_ONLY 861 862 } bcm_dpp_cosq_rate_class_elements_t; 863 864 typedef struct { 865 bcm_dpp_cosq_rate_class_elements_t valid_element; 866 uint32 flags; 867 868 /* wred */ 869 bcm_cosq_gport_discard_t discard; 870 871 /* FADT DRAM bounds */ 872 bcm_cosq_fadt_info_t fadt_info; 873 bcm_cosq_fadt_threshold_t fadt_threshold; 874 875 /* DRAM bound recovery */ 876 int dram_bound_recovery_threshold; 877 878 /* OCB only */ 879 int ocb_only; 880 } bcm_dpp_cosq_rate_class_threshold_info_t; 881 882 /* System RED drop probability info */ 883 typedef struct bcm_dpp_cosq_ingress_system_red_dp_pr_info_s { 884 uint32 sys_red_dp_pr_val; 885 } bcm_dpp_cosq_ingress_system_red_dp_pr_info_t; 886 887 typedef struct bcm_dpp_cosq_vsq_rate_class_taildrop_info_s { 888 /* Tail drop settings */ 889 /* Maximal queue size per DP - not used in QAX and up*/ 890 uint32 max_size[DPP_DEVICE_COSQ_ING_NOF_DP]; 891 /* Maximal queue size in BDs threshold - not used in QAX and up*/ 892 uint32 max_size_bds[DPP_DEVICE_COSQ_ING_NOF_DP]; 893 894 /* QAX and up */ 895 /* Maximal VSQ size per type per DP */ 896 uint32 max_size_th[DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES][DPP_DEVICE_COSQ_ING_NOF_DP]; 897 } bcm_dpp_cosq_vsq_rate_class_taildrop_info_t; 898 899 typedef struct bcm_dpp_cosq_vsq_rate_class_wred_info_s { 900 /* Enable WRED algorithm test */ 901 uint8 enable[DPP_DEVICE_COSQ_ING_NOF_DP]; 902 /* WRED Min queue average size */ 903 uint32 min_avrg_th[DPP_DEVICE_COSQ_ING_NOF_DP]; 904 /* WRED Max queue average size */ 905 uint32 max_avrg_th[DPP_DEVICE_COSQ_ING_NOF_DP]; 906 /* WRED ignore packet size */ 907 uint8 ignore_packet_size[DPP_DEVICE_COSQ_ING_NOF_DP]; 908 /* WRED Max probability */ 909 uint32 max_probability[DPP_DEVICE_COSQ_ING_NOF_DP]; 910 /* WRED exp. weight */ 911 uint32 wred_exp_wq; 912 } bcm_dpp_cosq_vsq_rate_class_wred_info_t; 913 914 typedef struct bcm_dpp_cosq_vsq_rate_class_fc_info_s { 915 /* FC settings */ 916 SOC_TMC_THRESH_WITH_HYST_INFO queue_size; 917 SOC_TMC_THRESH_WITH_HYST_INFO bd_size; 918 /* QAX and up only */ 919 SOC_TMC_THRESH_WITH_HYST_INFO size[DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES]; 920 SOC_TMC_THRESH_WITH_FADT_HYST_INFO fadt_size[DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES]; 921 } bcm_dpp_cosq_vsq_rate_class_fc_info_t; 922 923 typedef struct bcm_dpp_cosq_vsq_rate_class_fadt_info_s { 924 uint32 max_threshold; 925 uint32 min_threshold; 926 int alpha; 927 } bcm_dpp_cosq_vsq_rate_class_fadt_info_t; 928 929 typedef struct bcm_dpp_cosq_vsq_rate_class_headroom_info_s { 930 uint32 max_headroom; 931 uint32 max_headroom_nominal; 932 uint32 max_headroom_extension; 933 } bcm_dpp_cosq_vsq_rate_class_pg_headroom_info_t; 934 935 typedef struct bcm_dpp_cosq_queue_vsq_rate_class_info_s { 936 bcm_dpp_cosq_vsq_rate_class_wred_info_t wred; 937 bcm_dpp_cosq_vsq_rate_class_taildrop_info_t taildrop; 938 bcm_dpp_cosq_vsq_rate_class_fc_info_t fc; 939 } bcm_dpp_cosq_queue_vsq_rate_class_info_t; 940 941 typedef struct bcm_dpp_cosq_src_port_vsq_rate_class_info_s { 942 bcm_dpp_cosq_vsq_rate_class_wred_info_t wred; 943 /* not used in QAX and up */ 944 bcm_dpp_cosq_vsq_rate_class_taildrop_info_t shared; 945 /* not used in QAX and up */ 946 bcm_dpp_cosq_vsq_rate_class_taildrop_info_t headroom; 947 bcm_dpp_cosq_vsq_rate_class_fc_info_t fc; 948 /*Max VSQ guaranteed occupancy threshold- not used in QAX and up*/ 949 uint32 min_threshold[DPP_DEVICE_COSQ_ING_NOF_DP]; 950 /* QAX and up only */ 951 uint32 guaranteed_size[DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES][DPP_DEVICE_COSQ_ING_NOF_DP]; 952 uint32 shared_size[DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES][DPP_DEVICE_COSQ_ING_NOF_DP]; 953 uint32 headroom_size[DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES]; 954 } bcm_dpp_cosq_src_port_vsq_rate_class_info_t; 955 956 typedef struct bcm_dpp_cosq_pg_vsq_rate_class_info_s { 957 bcm_dpp_cosq_vsq_rate_class_wred_info_t wred; 958 /* not used in QAX and up */ 959 bcm_dpp_cosq_vsq_rate_class_taildrop_info_t shared; 960 /* not used in QAX and up */ 961 bcm_dpp_cosq_vsq_rate_class_taildrop_info_t headroom; 962 bcm_dpp_cosq_vsq_rate_class_fc_info_t fc; 963 /*Max VSQ guaranteed occupancy threshold - not used in QAX and up*/ 964 uint32 min_threshold[DPP_DEVICE_COSQ_ING_NOF_DP]; 965 /* not used in QAX and up */ 966 int32 queue_alpha_bds[DPP_DEVICE_COSQ_ING_NOF_DP]; 967 SOC_TMC_ITM_VSQ_PG_PRM prm; 968 /* QAX and up only */ 969 uint32 guaranteed_size[DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES][DPP_DEVICE_COSQ_ING_NOF_DP]; 970 bcm_dpp_cosq_vsq_rate_class_fadt_info_t shared_size[DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES][DPP_DEVICE_COSQ_ING_NOF_DP]; 971 bcm_dpp_cosq_vsq_rate_class_pg_headroom_info_t headroom_size[DPP_COSQ_INGRESS_THRESHOLD_NOF_TYPES]; 972 } bcm_dpp_cosq_pg_vsq_rate_class_info_t; 973 974 typedef struct bcm_dpp_cosq_vsq_rate_class_info_s { 975 bcm_dpp_cosq_queue_vsq_rate_class_info_t queue[SOC_TMC_NOF_NON_SRC_BASED_VSQ_GROUPS]; 976 bcm_dpp_cosq_src_port_vsq_rate_class_info_t port[SOC_TMC_ITM_NOF_RSRC_POOLS]; 977 bcm_dpp_cosq_pg_vsq_rate_class_info_t pg; 978 } bcm_dpp_cosq_vsq_rate_class_info_t; 979 980 981 /* 982 * VSQ valid types 983 */ 984 typedef enum { 985 /* 986 * VSQ General type 987 */ 988 BCM_DPP_COSQ_VSQ_TYPE_GLOBAL = _SHR_COSQ_VSQ_GL, 989 /* 990 * VSQ Category 991 */ 992 BCM_DPP_COSQ_VSQ_TYPE_CTGRY = _SHR_COSQ_VSQ_CT, 993 /* 994 * VSQ CTCC 995 */ 996 BCM_DPP_COSQ_VSQ_TYPE_CTCC = _SHR_COSQ_VSQ_CTCC, 997 /* 998 * VSQ CTTC 999 */ 1000 BCM_DPP_COSQ_VSQ_TYPE_CTTC = _SHR_COSQ_VSQ_CTTC, 1001 /* 1002 * VSQ PP 1003 */ 1004 BCM_DPP_COSQ_VSQ_TYPE_PP = _SHR_COSQ_VSQ_PP, 1005 /* 1006 * VSQ SRC Port (VSQE) 1007 */ 1008 BCM_DPP_COSQ_VSQ_TYPE_SRC_PORT = _SHR_COSQ_VSQ_SRC_PORT, 1009 /* 1010 * VSQ PG (VSQF) 1011 */ 1012 BCM_DPP_COSQ_VSQ_TYPE_PG = _SHR_COSQ_VSQ_PG, 1013 /*Arad legacy VSQ names*/ 1014 /* 1015 * VSQ PFC (VSQE) 1016 */ 1017 BCM_DPP_COSQ_VSQ_TYPE_LLFC = _SHR_COSQ_VSQ_SRC_PORT, 1018 /* 1019 * VSQ LLFC (VSQF) 1020 */ 1021 BCM_DPP_COSQ_VSQ_TYPE_PFC = _SHR_COSQ_VSQ_PG, 1022 /* 1023 * Last entry 1024 */ 1025 BCM_DPP_COSQ_VSQ_NOF_TYPES 1026 } bcm_dpp_cosq_vsq_type_t; 1027 1028 #define BCM_DPP_COSQ_GPORT_VSQ_TYPE_GET(_gport) _SHR_COSQ_GPORT_VSQ_TYPE_GET(_gport) 1029 1030 /* 1031 * External functions 1032 */ 1033 void bcm_petra_vig_display_whole_db(void) ; 1034 int bcm_petra_cosq_fmq_hr_allocate(int unit, bcm_core_t core, int nbr_ports, uint32 *tm_ports); 1035 int bcm_petra_cosq_fmq_hr_deallocate(int unit, bcm_core_t core, int nbr_ports, uint32 *tm_ports); 1036 int bcm_petra_cosq_fmq_vsq_category_mode_set(int unit, int core, bcm_fabric_vsq_category_mode_t vsq_category_mode); 1037 int bcm_petra_cosq_fmq_vsq_category_mode_get(int unit, int core, bcm_fabric_vsq_category_mode_t *vsq_category_mode); 1038 1039 int bcm_petra_cosq_isq_hr_allocate(int unit, bcm_core_t core, uint32 *tm_port); 1040 int bcm_petra_cosq_isq_hr_deallocate(int unit, bcm_core_t core, uint32 *tm_port); 1041 1042 int 1043 _bcm_petra_cosq_core_get(int unit, bcm_gport_t gport, int allow_core_all, int *core); 1044 extern int 1045 _bcm_petra_cosq_gport_vsq_gport_get(int unit, 1046 bcm_gport_t vsq_gport, 1047 bcm_cos_queue_t cosq, 1048 int *core_id, 1049 uint8 *is_ocb_only, 1050 bcm_dpp_cosq_vsq_type_t *vsq_group_type, 1051 int *vsq_index); 1052 #ifdef BCM_ARAD_SUPPORT 1053 int 1054 _bcm_petra_cosq_voq_rate_class_default_set(int unit, 1055 int rate_class, 1056 bcm_dpp_cosq_ingress_rate_class_info_t *rate_class_info); 1057 #endif /*BCM_ARAD_SUPPORT*/ 1058 extern uint8 * 1059 _bcm_petra_cosq_element_alloc(int unit, bcm_dpp_cosq_list_hd_t *hd, int element_index); 1060 1061 extern uint8 * 1062 _bcm_petra_cosq_element_get(int unit, bcm_dpp_cosq_list_hd_t *hd, int element_index); 1063 1064 extern int 1065 _bcm_petra_cosq_qid_type_get(int unit, int core, int base_qid, int *gport, 1066 int *is_muticast, int *is_unicast, int *is_isq, int *queue_type); 1067 1068 /* 1069 * Static Functions (Resource allocation) 1070 */ 1071 int 1072 _bcm_petra_flow_region_config(int unit, int core, int region_start, int region_end, 1073 int is_interdigitated, int is_oddEven, int is_clCir); 1074 1075 int 1076 _bcm_petra_queue_region_config(int unit, int core, int region_start, int region_end, 1077 int is_interdigitated); 1078 int 1079 _bcm_petra_cosq_queue_range_set(int unit, int core_id, int type, int configuration_type, int sw_only, SOC_SAND_U32_RANGE* queue_range); 1080 1081 int 1082 _bcm_petra_flow_region_config_get(int unit, int core, int flow_region, uint8 *p_is_interdigitated, int *p_is_oddEven, int *p_is_clCir); 1083 1084 int 1085 _bcm_petra_queue_region_config_get(int unit, int core, int queue_region, uint8 *is_interdigitated); 1086 1087 int 1088 _bcm_petra_cosq_credit_watchdog_range_set(int unit, int core_id, uint32 flags, bcm_cosq_range_t *range, int common_message_time); 1089 1090 int 1091 _bcm_petra_cosq_credit_watchdog_range_get(int unit, int core_id, bcm_cosq_range_t *range); 1092 1093 /* 1094 * Static Functions (Resource allocation) 1095 * End 1096 */ 1097 int 1098 _bcm_petra_flow_id_get(int unit, int core, int base_flow_id, int cos, int is_non_contiguous, int is_composite, int is_remove, int *flow); 1099 1100 int 1101 _bcm_petra_composite_flow_id_get(int unit, int core, int base_flow_id, int cos, int is_non_contiguous, int is_composite, int *flow); 1102 1103 int 1104 _bcm_petra_se_dual_flow_id_get(int unit, int flow_id, SOC_TMC_SCH_SE_TYPE type, int is_odd_even, int *flow); 1105 1106 int 1107 _bcm_petra_se_composite_flow_id_get(int unit, int flow_id, SOC_TMC_SCH_SE_TYPE type, int is_odd_even, int *flow); 1108 1109 int 1110 _bcm_petra_cosq_egress_thresh_map_get(int unit, int port, uint32 *profile); 1111 int 1112 _bcm_cosq_petra_vsq_category_set(int unit, int core_id, int range_type, SOC_SAND_U32_RANGE* queue_range); 1113 int 1114 _bcm_cosq_petra_vsq_category_get(int unit, int core_id, int range_type, SOC_SAND_U32_RANGE* queue_range); 1115 int 1116 _bcm_petra_cosq_queue_range_get(int unit, int core_id, int type, SOC_SAND_U32_RANGE* queue_range); 1117 int 1118 _bcm_petra_cosq_ucast_qid_range_set(int unit, int core, int qid_start, int qid_end); 1119 1120 int 1121 _bcm_petra_cosq_ucast_qid_range_get(int unit, int core, int *qid_start, int *qid_end); 1122 1123 int 1124 _bcm_petra_cosq_is_se_reserved(int unit, int core, int se_id, int *is_reserved); 1125 1126 int 1127 _bcm_petra_cosq_is_conn_reserved(int unit, int conn_id, int *is_reserved); 1128 1129 int 1130 bcm_petra_cosq_resource_gport_port_get(int unit, bcm_gport_t gport, bcm_port_t *port); 1131 1132 int 1133 _bcm_petra_cosq_is_queue_reserved(int unit, int queue_id, int *is_reserved); 1134 1135 int 1136 _bcm_cosq_before_traffic_validation(int unit); 1137 1138 int 1139 _bcm_petra_cosq_gport_egress_queue_mapping_hw_get(int unit, 1140 int profile, 1141 int core, 1142 bcm_dpp_cosq_egress_queue_mapping_info_t* mapping_info); 1143 int 1144 _bcm_petra_cosq_gport_egress_map_init(int unit, 1145 bcm_gport_t port); 1146 1147 int 1148 _bcm_petra_cosq_egress_thresh_entry_get(int unit, 1149 int core, 1150 int profile, 1151 bcm_dpp_cosq_egress_thresh_key_info_t* thresh_info); 1152 1153 int 1154 _bcm_petra_cosq_fc_port_threshold_init(int unit, soc_port_t port, int *mc_reserved_pds, int is_dynamic); 1155 1156 /* dyamic port */ 1157 int 1158 _bcm_petra_cosq_hr_handle(int unit, int port, int enable); 1159 1160 1161 /* translate from packets per second to kbps */ 1162 int 1163 _bcm_petra_cosq_egress_port_scheduler_pps_to_kbps(int unit, int core, uint32 pps, uint32 *kbps); 1164 1165 /* translate from kbps to packets per second */ 1166 int 1167 _bcm_petra_cosq_egress_port_scheduler_kbps_to_pps(int unit, int core, uint32 kbps, uint32 *pps); 1168 1169 void 1170 _bcm_petra_cosq_gport_qax_flow_id_add(int unit, bcm_gport_t *gport, int core); 1171 1172 #ifdef BCM_WARM_BOOT_SUPPORT_SW_DUMP 1173 extern int 1174 _bcm_dpp_cosq_sw_dump(int unit); 1175 #endif /* BCM_WARM_BOOT_SUPPORT_SW_DUMP */ 1176 1177 #endif /* _BCM_INT_DPP_COSQ_H_ */