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synce.h (2366B)

      1 /** \file bcm_int/dnx/synce/synce.h
      2  *
      3  * Functions for handling synce init sequences.
      4  */
      5 /*
      6  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      7  * 
      8  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
      9  */
     10 
     11 #ifndef _SYNCE_INCLUDED__
     12 /*
     13  * {
     14  */
     15 
     16 #define _SYNCE_INCLUDED__
     17 
     18 /*************
     19  * INCLUDES  *
     20  */
     21 /*
     22  * {
     23  */
     24 
     25 /*
     26  * }
     27  */
     28 
     29 /*************
     30  * DEFINES   *
     31  */
     32 /*
     33  * {
     34  */
     35 
     36 /*
     37  * }
     38  */
     39 /*************
     40  * MACROS    *
     41  */
     42 /*
     43  * {
     44  */
     45 /*
     46  * }
     47  */
     48 
     49 /*************
     50  * ENUMS     *
     51  */
     52 /*
     53  * {
     54  */
     55 
     56 /*
     57  * }
     58  */
     59 
     60 /*************
     61  * TYPE DEFS *
     62  */
     63 /*
     64  * {
     65  */
     66 typedef enum
     67 {
     68     /**
     69      *  Synchronous Ethernet signal - differential (two signals
     70      *  per clock) recovered clock, two differential outputs
     71      */
     72     DNX_NIF_SYNCE_MODE_TWO_DIFF_CLK = 0,
     73     /**
     74      *  Synchronous Ethernet signal - recovered clock accompanied
     75      *  by a valid indication, two clk+valid outputs
     76      */
     77     DNX_NIF_SYNCE_MODE_TWO_CLK_AND_VALID = 1,
     78     /**
     79      *  Number of types in ARAD_NIF_SYNCE_MODE
     80      */
     81     DNX_NIF_SYNCE_NOF_MODES = 2
     82 } SOC_DNX_PLL_NIF_SYNCE_MODE;
     83 
     84 typedef enum
     85 {
     86     /**
     87      *  SyncE reference clock PM divider 1
     88      */
     89     DNX_NIF_SYNCE_PM_DIV_1 = 0,
     90     /**
     91      *  SyncE reference clock PM divider 7
     92      */
     93     DNX_NIF_SYNCE_PM_DIV_7 = 1,
     94     /**
     95      *  SyncE reference clock PM divider 11
     96      */
     97     DNX_NIF_SYNCE_PM_DIV_11 = 2,
     98 
     99     DNX_NIF_SYNCE_NOF_PM_DIVIDERS = 3
    100 } DNX_SYNCE_PM_DIVIDER;
    101 /*
    102  * }
    103  */
    104 
    105 /*************
    106  * GLOBALS   *
    107  */
    108 /*
    109  * {
    110  */
    111 /*
    112  * }
    113  */
    114 /*************
    115  * FUNCTIONS *
    116  */
    117 /*
    118  * {
    119  */
    120 shr_error_e dnx_synce_init(
    121     int unit);
    122 
    123 shr_error_e dnx_synce_deinit(
    124     int unit);
    125 
    126 int dnx_synce_port_set(
    127     int unit,
    128     uint32 synce_index,
    129     bcm_port_t port);
    130 
    131 int dnx_synce_port_get(
    132     int unit,
    133     uint32 synce_index,
    134     bcm_port_t * port);
    135 
    136 int dnx_synce_divider_set(
    137     int unit,
    138     uint32 synce_index,
    139     int divider);
    140 
    141 int dnx_synce_divider_get(
    142     int unit,
    143     uint32 synce_index,
    144     int *divider);
    145 
    146 int dnx_nif_synce_enable_get(
    147     int unit,
    148     int core,
    149     int *enable);
    150 
    151 int dnx_nif_synce_enable_set(
    152     int unit,
    153     int core,
    154     int enable);
    155 
    156 int dnx_nif_synce_ref_clk_div_get(
    157     int unit,
    158     bcm_port_t port,
    159     int *pm_synce_div,
    160     int *nif_synce_div);
    161 /*
    162  * }
    163  */
    164 #endif /* __SYNCE_INCLUDED__ */