hbmc_firmware.h (11613B)
1 2 3 /* 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 7 */ 8 9 #ifndef _BCMINT_DNX_DRAM_HBMC_HBMC_FIRMWARE_H_INCLUDED 10 11 #define _BCMINT_DNX_DRAM_HBMC_HBMC_FIRMWARE_H_INCLUDED 12 13 14 #ifndef BCM_DNX_SUPPORT 15 #error "This file is for use by DNX (JR2) family only!" 16 #endif 17 18 #include <shared/shrextend/shrextend_debug.h> 19 20 21 #define DNX_HBMC_FIRMWARE_ALL_CHANNELS (-1) 22 23 24 typedef enum 25 { 26 27 DNX_HBMC_FIRMWARE_INTERRUPT_CODE_REVISION = 0x0, 28 29 DNX_HBMC_FIRMWARE_INTERRUPT_CODE_BUILD_ID = 0x1, 30 31 DNX_HBMC_FIRMWARE_INTERRUPT_CODE_LAUNCH_OPERATION_ON_ALL_CHANNELS = 0x30, 32 33 DNX_HBMC_FIRMWARE_INTERRUPT_CODE_LAUNCH_OPERATION_ON_A_SINGLE_CHANNEL = 0x31, 34 35 DNX_HBMC_FIRMWARE_INTERRUPT_CODE_GET_OPERATION_RESULT = 0x32, 36 37 DNX_HBMC_FIRMWARE_INTERRUPT_CODE_GET_PARAMETER_VALUE = 0x33, 38 39 DNX_HBMC_FIRMWARE_INTERRUPT_CODE_SET_PARAMETER = 0x34, 40 41 DNX_HBMC_FIRMWARE_INTERRUPT_CODE_SET_PARAMETER_VALUE = 0x35 42 } dnx_hbmc_firmware_interrupt_code_e; 43 44 45 typedef enum 46 { 47 48 DNX_HBMC_FIRMWARE_OPERATION_RESET_PHY_AND_HBM = 0x0, 49 50 DNX_HBMC_FIRMWARE_OPERATION_RESET_PHY_FIFO_POINTERS = 0x1, 51 52 DNX_HBMC_FIRMWARE_OPERATION_RESET_HBM = 0x2, 53 54 DNX_HBMC_FIRMWARE_OPERATION_POWER_ON_FLOW = 0x5, 55 56 DNX_HBMC_FIRMWARE_OPERATION_BYPASS_TEST = 0x7, 57 58 DNX_HBMC_FIRMWARE_OPERATION_READ_DEVICE_ID = 0x8, 59 60 DNX_HBMC_FIRMWARE_OPERATION_AWORD_TEST = 0x9, 61 62 DNX_HBMC_FIRMWARE_OPERATION_AERR_TEST = 0xa, 63 64 DNX_HBMC_FIRMWARE_OPERATION_DWORD_TEST = 0xb, 65 66 DNX_HBMC_FIRMWARE_OPERATION_DERR_TEST = 0xc, 67 68 DNX_HBMC_FIRMWARE_OPERATION_LANE_REPAIR = 0xd, 69 70 DNX_HBMC_FIRMWARE_OPERATION_AWORD_ILB_TEST = 0xe, 71 72 DNX_HBMC_FIRMWARE_OPERATION_DWORD_ILB_TEST = 0xf, 73 74 DNX_HBMC_FIRMWARE_OPERATION_READ_DEVICE_TEMP = 0x10, 75 76 DNX_HBMC_FIRMWARE_OPERATION_BURN_HARD_LANE_REPAIRS = 0x11, 77 78 DNX_HBMC_FIRMWARE_OPERATION_APPLY_HARD_LANE_REPAIRS_TO_PHY = 0x12, 79 80 DNX_HBMC_FIRMWARE_OPERATION_RUN_SAMSUNG_MBIST = 0x13, 81 82 DNX_HBMC_FIRMWARE_OPERATION_RUN_SK_HYNIX_MBIST = 0x14, 83 84 DNX_HBMC_FIRMWARE_OPERATION_RESET_MODE_REGISTERS = 0x15, 85 86 DNX_HBMC_FIRMWARE_OPERATION_RESET_PHY_CONFIG = 0x16, 87 88 DNX_HBMC_FIRMWARE_OPERATION_AWORD_SLB_TEST = 0x17, 89 90 DNX_HBMC_FIRMWARE_OPERATION_DWORD_SLB_TEST = 0x18, 91 92 DNX_HBMC_FIRMWARE_OPERATION_CHIPPING_TEST = 0x19, 93 94 DNX_HBMC_FIRMWARE_OPERATION_RESERVED = 0x1a, 95 96 DNX_HBMC_FIRMWARE_OPERATION_AERR_ILB_TEST = 0x1b, 97 98 DNX_HBMC_FIRMWARE_OPERATION_AERR_SLB_TEST = 0x1c, 99 100 DNX_HBMC_FIRMWARE_OPERATION_DERR_ILB_TEST = 0x1d, 101 102 DNX_HBMC_FIRMWARE_OPERATION_DERR_SLB_TEST = 0x1e, 103 104 DNX_HBMC_FIRMWARE_OPERATION_RUN_MMT = 0x20, 105 106 DNX_HBMC_FIRMWARE_OPERATION_LANE_VERIFY = 0x21, 107 108 DNX_HBMC_FIRMWARE_OPERATION_START_MMT = 0x22, 109 110 DNX_HBMC_FIRMWARE_OPERATION_STOP_MMT = 0x23, 111 112 DNX_HBMC_FIRMWARE_OPERATION_LOAD_TMRS_CODE = 0x24, 113 114 DNX_HBMC_FIRMWARE_OPERATION_CATTRIP_TEST = 0x26, 115 116 DNX_HBMC_FIRMWARE_OPERATION_HBM_RUN_CELL_REPAIR_MODE = 0x29, 117 118 DNX_HBMC_FIRMWARE_OPERATION_HBM_RUN_FUSE_SCAN = 0x2a, 119 120 DNX_HBMC_FIRMWARE_OPERATION_HBM_REPORT_LANE_REPAIRS = 0x2c, 121 122 DNX_HBMC_FIRMWARE_OPERATION_HBM_REPORT_NEW_LANE_REPAIRS = 0x2d, 123 124 DNX_HBMC_FIRMWARE_OPERATION_HBM_SKH_TM = 0x2e, 125 126 DNX_HBMC_FIRMWARE_OPERATION_HBM_REAPPLY_CELL_REPAIRS = 0x2f, 127 128 DNX_HBMC_FIRMWARE_OPERATION_HBM_REPAIR_LANE_REPAIRS_BY_MODE = 0x30, 129 130 DNX_HBMC_FIRMWARE_OPERATION_HBM_BEGIN_COLLECTING_LANE_FAILURES = 0x32, 131 132 DNX_HBMC_FIRMWARE_OPERATION_HBM_CONVERT_LANE_FAILURES_TO_SOFT_REPAIRS = 0x33, 133 134 DNX_HBMC_FIRMWARE_OPERATION_HBM_COMP_LANE_REPAIR = 0x34, 135 136 DNX_HBMC_FIRMWARE_OPERATION_HBM_DWORD_WRITE = 0x35, 137 138 DNX_HBMC_FIRMWARE_OPERATION_HBM_DWORD_READ = 0x36 139 } dnx_hbmc_firmware_operation_e; 140 141 142 typedef enum 143 { 144 DNX_HBMC_FIRMWARE_PARAM_HBM_RESERVED = 0x00, 145 DNX_HBMC_FIRMWARE_PARAM_HBM_MAX_TIMEOUT = 0x01, 146 DNX_HBMC_FIRMWARE_PARAM_HBM_TINIT1_CYCLES = 0x02, 147 DNX_HBMC_FIRMWARE_PARAM_HBM_TINIT2_CYCLES = 0x03, 148 DNX_HBMC_FIRMWARE_PARAM_HBM_TINIT3_CYCLES = 0x04, 149 DNX_HBMC_FIRMWARE_PARAM_HBM_TINIT4_CYCLES = 0x05, 150 DNX_HBMC_FIRMWARE_PARAM_HBM_TINIT5_CYCLES = 0x06, 151 DNX_HBMC_FIRMWARE_PARAM_HBM_RW_LATENCY_OFFSET = 0x07, 152 DNX_HBMC_FIRMWARE_PARAM_HBM_LATENCY_ODD_N_EVEN = 0x08, 153 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE_REGISTER0 = 0x0a, 154 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE_REGISTER1 = 0x0b, 155 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE_REGISTER2 = 0x0c, 156 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE_REGISTER3 = 0x0d, 157 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE_REGISTER4 = 0x0e, 158 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE_REGISTER5 = 0x0f, 159 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE_REGISTER6 = 0x10, 160 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE_REGISTER7 = 0x11, 161 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE_REGISTER8 = 0x12, 162 DNX_HBMC_FIRMWARE_PARAM_HBM_PHY_CONFIG0 = 0x13, 163 DNX_HBMC_FIRMWARE_PARAM_HBM_PHY_CONFIG1 = 0x14, 164 DNX_HBMC_FIRMWARE_PARAM_HBM_PHY_CONFIG2 = 0x15, 165 DNX_HBMC_FIRMWARE_PARAM_HBM_PHY_CONFIG3 = 0x16, 166 DNX_HBMC_FIRMWARE_PARAM_HBM_PHY_CONFIG4 = 0x17, 167 DNX_HBMC_FIRMWARE_PARAM_HBM_PHY_CONFIG5 = 0x18, 168 DNX_HBMC_FIRMWARE_PARAM_HBM_PHY_CONFIG6 = 0x19, 169 DNX_HBMC_FIRMWARE_PARAM_HBM_LBP_DRV_IMP = 0x1a, 170 DNX_HBMC_FIRMWARE_PARAM_HBM_DELAY_CONFIG_DLL = 0x1b, 171 DNX_HBMC_FIRMWARE_PARAM_HBM_IGNORE_PHYUPD_HANDSHAKE = 0x1c, 172 DNX_HBMC_FIRMWARE_PARAM_HBM_TUPDMRS_CYCLES = 0x1d, 173 DNX_HBMC_FIRMWARE_PARAM_HBM_T_RDLAT_OFFSET = 0x1e, 174 DNX_HBMC_FIRMWARE_PARAM_HBM_MBIST_REPAIR_MODE = 0x1f, 175 DNX_HBMC_FIRMWARE_PARAM_HBM_MBIST_PATTERN = 0x20, 176 DNX_HBMC_FIRMWARE_PARAM_HBM_SAMSUNG_MBIST_HARD_REPAIR_CYCLES = 0x21, 177 DNX_HBMC_FIRMWARE_PARAM_HBM_HARD_LANE_REPAIR_CYCLES = 0x22, 178 DNX_HBMC_FIRMWARE_PARAM_HBM_MBIST_BANK_ADDRESS_END = 0x24, 179 DNX_HBMC_FIRMWARE_PARAM_HBM_MBIST_ROW_ADDRESS_END = 0x25, 180 DNX_HBMC_FIRMWARE_PARAM_HBM_MBIST_COLUMN_ADDRESS_END = 0x26, 181 DNX_HBMC_FIRMWARE_PARAM_HBM_FREQ = 0x27, 182 DNX_HBMC_FIRMWARE_PARAM_HBM_DIV_MODE = 0x28, 183 DNX_HBMC_FIRMWARE_PARAM_HBM_CKE_EXIT_STATE = 0x29, 184 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_MODE_REGISTER0 = 0x2a, 185 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_MODE_REGISTER1 = 0x2b, 186 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_MODE_REGISTER2 = 0x2c, 187 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_MODE_REGISTER3 = 0x2d, 188 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_MODE_REGISTER4 = 0x2e, 189 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_MODE_REGISTER5 = 0x2f, 190 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_MODE_REGISTER6 = 0x30, 191 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_MODE_REGISTER7 = 0x31, 192 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_MODE_REGISTER8 = 0x32, 193 DNX_HBMC_FIRMWARE_PARAM_MMT_DWORD_MISR0 = 0x33, 194 DNX_HBMC_FIRMWARE_PARAM_MMT_DWORD_MISR1 = 0x34, 195 DNX_HBMC_FIRMWARE_PARAM_MMT_DWORD_MISR2 = 0x35, 196 DNX_HBMC_FIRMWARE_PARAM_MMT_DWORD_MISR3 = 0x36, 197 DNX_HBMC_FIRMWARE_PARAM_MMT_DWORD_MISR4 = 0x37, 198 DNX_HBMC_FIRMWARE_PARAM_MMT_LFSR_COMPARE_STICKY = 0x38, 199 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_T_RDLAT_OFFSET = 0x39, 200 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE_REGISTER15 = 0x3a, 201 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_MODE_REGISTER15 = 0x3b, 202 DNX_HBMC_FIRMWARE_PARAM_HBM_BYPASS_TESTMODE_RESET = 0x3c, 203 DNX_HBMC_FIRMWARE_PARAM_HBM_DISABLE_ADDR_LANE_REPAIR = 0x3d, 204 DNX_HBMC_FIRMWARE_PARAM_HBM_MMT_CONFIGURATION = 0x3e, 205 DNX_HBMC_FIRMWARE_PARAM_HBM_BYPASS_REPAIR_ON_RESET = 0x3f, 206 DNX_HBMC_FIRMWARE_PARAM_HBM_STACK_HEIGHT = 0x40, 207 DNX_HBMC_FIRMWARE_PARAM_HBM_MANUFACTURING_ID = 0x41, 208 DNX_HBMC_FIRMWARE_PARAM_HBM_DENSITY = 0x42, 209 DNX_HBMC_FIRMWARE_PARAM_HBM_MANUALLY_CONFIGURE_ID = 0x43, 210 DNX_HBMC_FIRMWARE_PARAM_HBM_PARITY_LATENCY = 0x44, 211 DNX_HBMC_FIRMWARE_PARAM_HBM_TEST_PARITY_LATENCY = 0x45, 212 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_DWORD0 = 0x49, 213 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_DWORD1 = 0x4a, 214 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_DWORD2 = 0x4b, 215 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_DWORD3 = 0x4c, 216 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_DWORD4 = 0x4d, 217 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_DWORD5 = 0x4e, 218 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_DWORD6 = 0x4f, 219 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_AWORD0 = 0x50, 220 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_AWORD1 = 0x51, 221 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_AWORD2 = 0x52, 222 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_AWORD3 = 0x53, 223 DNX_HBMC_FIRMWARE_PARAM_MMT_CONFIG_AWORD4 = 0x54, 224 DNX_HBMC_FIRMWARE_PARAM_MMT_AWORD_MISR0 = 0x55, 225 DNX_HBMC_FIRMWARE_PARAM_MMT_AWORD_MISR1 = 0x56, 226 DNX_HBMC_FIRMWARE_PARAM_MMT_T_RDLAT_OFFSET = 0x57, 227 DNX_HBMC_FIRMWARE_PARAM_MMT_MODE_REGISTER0 = 0x58, 228 DNX_HBMC_FIRMWARE_PARAM_MMT_MODE_REGISTER1 = 0x59, 229 DNX_HBMC_FIRMWARE_PARAM_MMT_MODE_REGISTER2 = 0x5a, 230 DNX_HBMC_FIRMWARE_PARAM_MMT_MODE_REGISTER3 = 0x5b, 231 DNX_HBMC_FIRMWARE_PARAM_MMT_MODE_REGISTER4 = 0x5c, 232 DNX_HBMC_FIRMWARE_PARAM_MMT_MODE_REGISTER5 = 0x5d, 233 DNX_HBMC_FIRMWARE_PARAM_MMT_MODE_REGISTER6 = 0x5e, 234 DNX_HBMC_FIRMWARE_PARAM_MMT_MODE_REGISTER7 = 0x5f, 235 DNX_HBMC_FIRMWARE_PARAM_MMT_MODE_REGISTER8 = 0x60, 236 DNX_HBMC_FIRMWARE_PARAM_MMT_MODE_REGISTER16 = 0x61, 237 DNX_HBMC_FIRMWARE_PARAM_HBM_SAMSUNG_MBIST_WORKAROUND = 0x62, 238 DNX_HBMC_FIRMWARE_PARAM_HBM_DWORD_OP = 0x63, 239 DNX_HBMC_FIRMWARE_PARAM_HBM_MMT_TCR_SETTING = 0x64, 240 DNX_HBMC_FIRMWARE_PARAM_HBM_MMT_SUPPLY_CONDITIONING = 0x65, 241 DNX_HBMC_FIRMWARE_PARAM_HBM_MODEL_NUMBER = 0x66, 242 DNX_HBMC_FIRMWARE_PARAM_HBM_DATE_CODE = 0x67, 243 DNX_HBMC_FIRMWARE_PARAM_HBM_MBIST_VERIFY = 0x68, 244 DNX_HBMC_FIRMWARE_PARAM_HBM_SAVE_SOFT_LANE_REPAIRS = 0x69, 245 DNX_HBMC_FIRMWARE_PARAM_HBM_MMT_READ_REPEAT = 0x6a, 246 DNX_HBMC_FIRMWARE_PARAM_HBM_MMT_COLUMN_RANGE = 0x6b, 247 DNX_HBMC_FIRMWARE_PARAM_HBM_MMT_BURST_LENGTH = 0x6c, 248 DNX_HBMC_FIRMWARE_PARAM_HBM_AWORD_MODE = 0x6d, 249 DNX_HBMC_FIRMWARE_PARAM_HBM_SPICO_FREQ = 0x6e, 250 DNX_HBMC_FIRMWARE_PARAM_HBM_TM0 = 0x6f, 251 DNX_HBMC_FIRMWARE_PARAM_HBM_TM1 = 0x70, 252 DNX_HBMC_FIRMWARE_PARAM_HBM_TM2 = 0x71, 253 DNX_HBMC_FIRMWARE_PARAM_HBM_TM3 = 0x72, 254 DNX_HBMC_FIRMWARE_PARAM_HBM_TM4 = 0x73, 255 DNX_HBMC_FIRMWARE_PARAM_HBM_MODE1_LANE_REPAIR_LIMIT = 0x76, 256 DNX_HBMC_FIRMWARE_PARAM_HBM_TOTAL_LANE_REPAIR_LIMIT = 0x77, 257 DNX_HBMC_FIRMWARE_PARAM_HBM_USE_MMT_IN_COMP_REPAIR = 0x78, 258 DNX_HBMC_FIRMWARE_PARAM_HBM_MMT_RDDATA_EN = 0x79, 259 DNX_HBMC_FIRMWARE_PARAM_HBM_MMT_ROW_RANGE = 0x7a 260 } dnx_hbmc_firmware_param_e; 261 262 263 typedef struct 264 { 265 266 uint32 revision; 267 268 uint32 build_id; 269 } dnx_hbmc_firmware_info_t; 270 271 272 typedef struct dnx_hbmc_firmware_operation_result_hbm_spare_s 273 { 274 275 uint32 hbm_spare_data[DNX_DATA_MAX_DRAM_FIRMWARE_NOF_HBM_SPARE_DATA_RESULTS]; 276 } dnx_hbmc_firmware_operation_result_hbm_spare_t; 277 278 279 shr_error_e dnx_hbmc_firmware_info_get( 280 int unit, 281 int hbmc_index, 282 dnx_hbmc_firmware_info_t * firmware_info); 283 284 285 shr_error_e dnx_hbmc_firmware_launch_operation( 286 int unit, 287 int hbmc_index, 288 int hbmc_channel, 289 dnx_hbmc_firmware_operation_e operation); 290 291 292 shr_error_e dnx_hbmc_firmware_operation_result_spare_get( 293 int unit, 294 int hbmc_index, 295 uint32 nof_hbm_spares, 296 dnx_hbmc_firmware_operation_result_hbm_spare_t * hbm_spare); 297 298 299 shr_error_e dnx_hbmc_firmware_param_set( 300 int unit, 301 int hbmc_index, 302 dnx_hbmc_firmware_param_e param, 303 uint32 value); 304 305 306 shr_error_e dnx_hbmc_firmware_param_get( 307 int unit, 308 int hbmc_index, 309 dnx_hbmc_firmware_param_e param, 310 uint32 *value); 311 312 313 shr_error_e dnx_hbmc_firmware_phy_init( 314 int unit, 315 int hbmc_index); 316 317 #endif