gddr6_func.h (4757B)
1 2 3 /* 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 7 */ 8 9 #ifndef _BCMINT_DNX_DRAM_GDDR6_GDDR6_FUNC_H_INCLUDED 10 #define _BCMINT_DNX_DRAM_GDDR6_GDDR6_FUNC_H_INCLUDED 11 12 13 #include <soc/shmoo_g6phy16.h> 14 #include <bcm_int/dnx/dram/gddr6/gddr6.h> 15 16 17 18 19 20 typedef enum 21 { 22 23 GDDR6_DRAM_BIST_DATA_PATTERN_CUSTOM, 24 25 GDDR6_DRAM_BIST_DATA_PATTERN_RANDOM_PRBS, 26 27 GDDR6_DRAM_BIST_DATA_PATTERN_DIFF, 28 29 GDDR6_DRAM_BIST_DATA_PATTERN_DIFF_REVERT, 30 31 32 GDDR6_DRAM_BIST_DATA_PATTERN_ONE, 33 34 GDDR6_DRAM_BIST_DATA_PATTERN_ZERO, 35 36 GDDR6_DRAM_BIST_DATA_PATTERN_BIT_MODE, 37 38 GDDR6_DRAM_BIST_DATA_PATTERN_SHIFT_MODE, 39 40 GDDR6_DRAM_BIST_DATA_PATTERN_ADDR_MODE, 41 42 GDDR6_DRAM_BIST_NOF_DATA_PATTERN_MODES 43 } dnx_gddr6_bist_pattern_mode; 44 typedef enum 45 { 46 LDFF = 0, 47 RDTR = 1, 48 WRTR = 2, 49 CADT = 3, 50 VENDOR_ID = 4 51 } dnx_gddr6_training_bist_mode; 52 53 typedef struct ldff_pattern_s 54 { 55 uint32 dq_pattern[SHMOO_G6PHY16_BIST_NOF_PATTERNS][4]; 56 uint32 dbi_pattern[SHMOO_G6PHY16_BIST_NOF_PATTERNS]; 57 uint32 edc_pattern[SHMOO_G6PHY16_BIST_NOF_PATTERNS]; 58 } dnx_gddr6_ldff_pattern; 59 60 typedef struct training_bist_cmd_configuration_s 61 { 62 uint64 commands; 63 int write_weight; 64 int read_weight; 65 int fifo_depth; 66 dnx_gddr6_training_bist_mode training_bist_mode; 67 } dnx_gddr6_training_bist_cmd_configuration; 68 69 typedef struct dnx_gddr6_periodic_temp_readout_config_s 70 { 71 uint32 readout_to_readout_prd; 72 uint32 refresh_to_readout_prd; 73 uint32 readout_done_to_done_prd; 74 } dnx_gddr6_periodic_temp_readout_config_t; 75 76 typedef struct dnx_gddr6_periodic_temp_readout_status_s 77 { 78 uint32 temperature; 79 uint32 is_valid; 80 uint32 max_temperature; 81 } dnx_gddr6_periodic_temp_readout_status_t; 82 83 typedef struct training_cadt_bist_configuration_s 84 { 85 int commands; 86 shmoo_g6phy16_cadt_mode_t cadt_mode; 87 int cadt_to_cadt_prd; 88 int cadt_to_rden_prd; 89 int cadt_prbs_mode; 90 int cadt_seed; 91 int cadt_invert_caui2; 92 uint32 cadt_pattern[SHMOO_G6PHY16_BIST_NOF_PATTERNS]; 93 } dnx_gddr6_training_cadt_bist_configuration; 94 95 typedef struct training_bist_configuration_s 96 { 97 dnx_gddr6_bist_pattern_mode dq_pattern_mode; 98 dnx_gddr6_bist_pattern_mode dbi_pattern_mode; 99 dnx_gddr6_bist_pattern_mode edc_pattern_mode; 100 dnx_gddr6_ldff_pattern pattern; 101 dnx_gddr6_training_bist_cmd_configuration cmd_cfg; 102 dnx_gddr6_training_cadt_bist_configuration cadt_cfg; 103 } dnx_gddr6_training_bist_configuration; 104 105 typedef struct bist_configuration_s 106 { 107 uint64 nof_commands; 108 int write_weight; 109 int read_weight; 110 int same_row; 111 112 dnx_gddr6_bist_address_mode_t bank_mode; 113 int bank_start; 114 int bank_end; 115 int bank_seed; 116 dnx_gddr6_bist_address_mode_t column_mode; 117 int column_start; 118 int column_end; 119 int column_seed; 120 dnx_gddr6_bist_address_mode_t row_mode; 121 int row_start; 122 int row_end; 123 int row_seed; 124 125 dnx_gddr6_bist_data_mode_t data_mode; 126 uint32 dbi_mode; 127 128 uint32 data_seed[8]; 129 uint32 dbi_seed; 130 131 uint32 bist_dq_pattern[8][8]; 132 uint32 bist_dbi_pattern[8]; 133 134 uint32 bist_timer_us; 135 } dnx_gddr6_bist_configuration_t; 136 137 typedef struct last_returned_data 138 { 139 uint32 last_returned_dq[8]; 140 uint32 last_returned_dbi; 141 uint32 last_returned_edc; 142 } dnx_gddr6_bist_last_returned_data_t; 143 144 145 shr_error_e dnx_gddr6_controller_init( 146 int unit, 147 int dram_index, 148 int ignore_vendor); 149 150 151 shr_error_e dnx_gddr6_dram_init( 152 int unit, 153 int dram_index, 154 gddr6_dram_init_phase_t phase); 155 156 shr_error_e dnx_gddr6_shmoo_dram_info_get( 157 int unit, 158 g6phy16_shmoo_dram_info_t * shmoo_info); 159 160 shr_error_e dnx_gddr6_wck2clk_training_start( 161 int unit, 162 int dram_index); 163 164 165 shr_error_e dnx_gddr6_bist_error_counter_get( 166 int unit, 167 int dram_index, 168 dnx_gddr6_bist_err_cnt_t * bist_error_count); 169 170 shr_error_e dnx_gddr6_data_bist_configure( 171 int unit, 172 int dram_index, 173 int channel, 174 dnx_gddr6_bist_configuration_t * bist_cfg); 175 176 177 shr_error_e dnx_gddr6_vendor_info_get( 178 int unit, 179 int dram_index, 180 uint32 mode, 181 uint32 *gddr6_vendor); 182 183 shr_error_e dnx_gddr6_load_precharge_all_command( 184 int unit, 185 int dram_index, 186 uint32 cabi_enabled); 187 188 shr_error_e dnx_gddr6_load_activate_command( 189 int unit, 190 int dram_index, 191 uint32 bank, 192 uint32 cabi_enabled); 193 194 195 shr_error_e dnx_gddr6_dram_err_cnt_get( 196 int unit, 197 int dram_index, 198 int channel, 199 dnx_gddr6_dram_err_cnt_t * dram_err_cnt); 200 201 202 shr_error_e dnx_gddr6_bist_err_cnt_get( 203 int unit, 204 int dram_index, 205 int channel, 206 dnx_gddr6_bist_err_cnt_t * bist_err_cnt); 207 208 #endif