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gddr6_cb.h (3312B)

      1 
      2 
      3 /*
      4  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      5  * 
      6  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
      7  */
      8 
      9 #ifndef _BCMINT_DNX_DRAM_GDDR6_GDDR6_CB_H_INCLUDED
     10 
     11 #define _BCMINT_DNX_DRAM_GDDR6_GDDR6_CB_H_INCLUDED
     12 
     13 #include <soc/shmoo_g6phy16.h>
     14 
     15 shr_error_e dnx_gddr6_modify_mrs_cb(
     16     int unit,
     17     int dram_index,
     18     int channel_index,
     19     uint32 mr_index,
     20     uint32 data,
     21     uint32 mask);
     22 
     23 shr_error_e dnx_gddr6_pll_set_cb(
     24     int unit,
     25     int dram_index,
     26     const g6phy16_drc_pll_t * pll_info);
     27 
     28 
     29 shr_error_e dnx_gddr6_phy_reg_read_cb(
     30     int unit,
     31     int dram_index,
     32     uint32 addr,
     33     uint32 *data);
     34 
     35 shr_error_e dnx_gddr6_phy_reg_write_cb(
     36     int unit,
     37     int dram_index,
     38     uint32 addr,
     39     uint32 data);
     40 
     41 shr_error_e dnx_gddr6_phy_reg_modify_cb(
     42     int unit,
     43     int dram_index,
     44     uint32 addr,
     45     uint32 data,
     46     uint32 mask);
     47 
     48 shr_error_e dnx_gddr6_enable_wr_crc_cb(
     49     int unit,
     50     int dram_index,
     51     int enable);
     52 
     53 shr_error_e dnx_gddr6_enable_rd_crc_cb(
     54     int unit,
     55     int dram_index,
     56     int enable);
     57 
     58 shr_error_e dnx_gddr6_enable_wr_dbi_cb(
     59     int unit,
     60     int dram_index,
     61     int enable);
     62 
     63 shr_error_e dnx_gddr6_enable_rd_dbi_cb(
     64     int unit,
     65     int dram_index,
     66     int enable);
     67 
     68 shr_error_e dnx_gddr6_soft_reset_controller_without_dram_cb(
     69     int unit,
     70     int dram_index);
     71 
     72 shr_error_e dnx_gddr6_bist_conf_set_cb(
     73     int unit,
     74     int dram_index,
     75     const g6phy16_bist_info_t * info);
     76 
     77 shr_error_e dnx_gddr6_bist_run_cb(
     78     int unit,
     79     int dram_index,
     80     const g6phy16_bist_info_t * info);
     81 
     82 shr_error_e dnx_gddr6_bist_err_cnt_cb(
     83     int unit,
     84     int dram_index,
     85     g6phy16_bist_err_cnt_t * info);
     86 
     87 
     88 shr_error_e dnx_gddr6_dram_init_cb(
     89     int unit,
     90     int dram_index,
     91     gddr6_dram_init_phase_t phase);
     92 
     93 
     94 shr_error_e dnx_gddr6_dram_info_access_cb(
     95     int unit,
     96     g6phy16_shmoo_dram_info_t * shmoo_info);
     97 
     98 
     99 shr_error_e dnx_gddr6_enable_wck2ck_training_cb(
    100     int unit,
    101     int dram_index,
    102     int enable);
    103 
    104 shr_error_e dnx_gddr6_enable_write_leveling_cb(
    105     int unit,
    106     int dram_index,
    107     uint32 command_parity_lattency,
    108     int use_continious_dqs,
    109     int enable);
    110 
    111 shr_error_e dnx_gddr6_mpr_en_cb(
    112     int unit,
    113     int dram_index,
    114     int enable);
    115 
    116 shr_error_e dnx_gddr6_mpr_load_cb(
    117     int unit,
    118     int dram_index,
    119     uint8 *mpr_pattern);
    120 
    121 
    122 shr_error_e dnx_gddr6_vendor_info_get_cb(
    123     int unit,
    124     int dram_index,
    125     g6phy16_vendor_info_t * vendor_info);
    126 
    127 
    128 shr_error_e dnx_gddr6_dqs_pulse_gen_cb(
    129     int unit,
    130     int dram_index,
    131     int use_continious_dqs);
    132 
    133 
    134 shr_error_e dnx_gddr6_training_bist_conf_set_cb(
    135     int unit,
    136     int dram_index,
    137     g6phy16_training_bist_info_t * info);
    138 
    139 
    140 shr_error_e dnx_gddr6_training_bist_err_cnt_cb(
    141     int unit,
    142     int dram_index,
    143     g6phy16_training_bist_err_cnt_t * info);
    144 
    145 
    146 shr_error_e dnx_gddr6_shmoo_drc_dq_byte_pairs_swap_info_get_cb(
    147     int unit,
    148     int dram_index,
    149     int *pairs_were_swapped);
    150 
    151 
    152 shr_error_e dnx_gddr6_force_dqs_cb(
    153     int unit,
    154     int dram_index,
    155     uint32 force_dqs);
    156 
    157 
    158 shr_error_e dnx_gddr6_enable_refresh_cb(
    159     int unit,
    160     int dram_index,
    161     int enable,
    162     uint32 new_trefi,
    163     uint32 new_trefi_ab,
    164     uint32 *curr_refi,
    165     uint32 *curr_refi_ab);
    166 
    167 #endif