gddr6.h (6860B)
1 2 3 /* 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 7 */ 8 9 #ifndef _BCMINT_DNX_DRAM_GDDR6_GDDR6_H_INCLUDED 10 11 #define _BCMINT_DNX_DRAM_GDDR6_GDDR6_H_INCLUDED 12 13 #include <shared/shrextend/shrextend_debug.h> 14 15 #ifdef DNX_DATA_INTERNAL 16 #undef DNX_DATA_INTERNAL 17 #endif 18 #include <soc/shmoo_g6phy16.h> 19 #include <soc/dnx/swstate/auto_generated/types/dnx_dram_types.h> 20 #include <bcm/switch.h> 21 22 23 #define DNX_GDDR6_ITER_ALL -1 24 #define DNX_GDDR6_CHANNEL_ITER_ALL -1 25 26 #define GDDR6_SWAP_SUFFIX_BUFFER_SIZE 256 27 #define GDDR6_SOC_PROPERTY_STR_BUFFER_SIZE 256 28 #define GDDR6_VAL_STR_BUFFER_SIZE 1024 29 #define GDDR6_STR_VAL_SIZE (32) 30 31 #define BURST_LENGTH 16 32 #define BURST_LENGTH_DIV_4 BURST_LENGTH/4 33 #define DNX_GDDR6_VAL_IS_IN_CLOCKS_BIT (31) 34 35 36 typedef enum 37 { 38 FIRST_DNX_GDDR6_PHY_TUNE_ACTION_E = 0, 39 40 DNX_GDDR6_RESTORE_TUNE_PARAMETERS = FIRST_DNX_GDDR6_PHY_TUNE_ACTION_E, 41 42 DNX_GDDR6_RUN_TUNE, 43 44 DNX_GDDR6_RESTORE_TUNE_PARAMETERS_OR_RUN_TUNE, 45 46 DNX_GDDR6_SKIP_TUNE, 47 48 NUM_DNX_GDDR6_PHY_TUNE_ACTION_E 49 } dnx_gddr6_phy_tune_action_e; 50 51 52 typedef enum dnx_gddr6_tdu_matrix_option_e 53 { 54 55 DNX_GDDR6_SINGLE_DRAM_ATM = 0, 56 57 DNX_GDDR6_2_DRAMS_ATM = 1, 58 59 DNX_GDDR6_NOF_ATMS = 2 60 } dnx_gddr6_tdu_matrix_option_t; 61 62 typedef enum dnx_gddr6_bist_address_mode_e 63 { 64 DNX_GDDR6_BIST_ADDRESS_MODE_INCREMENTAL = 0, 65 DNX_GDDR6_BIST_ADDRESS_MODE_PRBS = 1, 66 } dnx_gddr6_bist_address_mode_t; 67 68 typedef enum dnx_gddr6_info_mode_e 69 { 70 DNX_GDDR6_ID1 = 1, 71 DNX_GDDR6_TEMP = 2, 72 DNX_GDDR6_ID2 = 3, 73 } dnx_gddr6_info_mode_t; 74 75 typedef enum dnx_gddr6_bist_data_mode_e 76 { 77 DNX_GDDR6_BIST_DATA_MODE_PATTERN = 0, 78 DNX_GDDR6_BIST_DATA_MODE_PRBS = 1, 79 } dnx_gddr6_bist_data_mode_t; 80 81 82 typedef struct gddr6_dram_err_cnt_s 83 { 84 85 uint32 read_crc_err_cnt[DNX_DATA_MAX_DRAM_GDDR6_BYTES_PER_CHANNEL][2]; 86 87 uint32 write_crc_err_cnt[DNX_DATA_MAX_DRAM_GDDR6_BYTES_PER_CHANNEL][2]; 88 } dnx_gddr6_dram_err_cnt_t; 89 90 typedef struct gddr6_bist_err_cnt_s 91 { 92 uint32 cadt_err_cnt; 93 uint32 cadt_err_bitmap[1]; 94 uint32 bist_data_err_cnt; 95 uint32 bist_data_err_bitmap[1]; 96 uint32 bist_edc_err_cnt; 97 uint32 bist_edc_err_bitmap[1]; 98 uint32 bist_dbi_err_cnt; 99 uint32 bist_dbi_err_bitmap[1]; 100 } dnx_gddr6_bist_err_cnt_t; 101 102 typedef struct gddr6_bist_status_cnt_s 103 { 104 uint32 write_command_cnt[2]; 105 uint32 read_command_cnt[2]; 106 uint32 read_data_cnt[2]; 107 uint32 read_training_data_cnt[2]; 108 uint32 read_edc_cnt[2]; 109 uint32 wrtr_command_cnt[2]; 110 uint32 rdtr_command_cnt[2]; 111 uint32 ldff_command_cnt[2]; 112 } dnx_gddr6_bist_status_cnt_t; 113 114 115 shr_error_e dnx_gddr6_index_verify( 116 int unit, 117 int dram_index); 118 119 120 shr_error_e dnx_gddr6_sw_state_init( 121 int unit); 122 123 124 shr_error_e dnx_gddr6_init( 125 int unit); 126 127 128 shr_error_e dnx_gddr6_deinit( 129 int unit); 130 131 132 shr_error_e dnx_gddr6_configure_plls( 133 int unit, 134 int dram_index, 135 const g6phy16_drc_pll_t * pll_info); 136 137 138 shr_error_e dnx_gddr6_phy_out_of_reset( 139 int unit, 140 int dram_index); 141 142 143 shr_error_e dnx_gddr6_phy_pll_init( 144 int unit, 145 int dram_index); 146 147 148 shr_error_e dnx_gddr6_mode_register_get( 149 int unit, 150 int dram_index, 151 int channel, 152 int mr_index, 153 uint32 *value); 154 155 shr_error_e dnx_gddr6_mode_register_set( 156 int unit, 157 int dram_index, 158 int channel, 159 int mr_index, 160 uint32 value); 161 162 shr_error_e dnx_gddr6_channels_soft_init( 163 int unit, 164 int dram_ndx); 165 166 shr_error_e dnx_gddr6_ind_access_physical_address_read( 167 int unit, 168 uint32 dram_index, 169 uint32 channel, 170 uint32 bank, 171 uint32 row, 172 uint32 column, 173 uint32 *data); 174 175 shr_error_e dnx_gddr6_ind_access_physical_address_write( 176 int unit, 177 uint32 dram_index, 178 uint32 channel, 179 uint32 bank, 180 uint32 row, 181 uint32 column, 182 uint32 *pattern); 183 184 shr_error_e dnx_gddr6_ind_access_logical_buffer_read( 185 int unit, 186 int buffer, 187 int index, 188 uint32 *data); 189 190 191 shr_error_e dnx_gddr6_ind_access_logical_buffer_write( 192 int unit, 193 int buffer, 194 int index, 195 uint32 *pattern); 196 197 shr_error_e soc_dnx_gddr6_access_init( 198 int unit); 199 200 201 shr_error_e dnx_gddr6_tdu_configure( 202 int unit); 203 204 205 shr_error_e dnx_gddr6_channels_soft_reset_set( 206 int unit, 207 int dram_index, 208 int in_soft_reset); 209 210 211 shr_error_e dnx_gddr6_channels_soft_init_set( 212 int unit, 213 int dram_index, 214 int in_soft_init); 215 216 217 shr_error_e dnx_gddr6_phy_init( 218 int unit); 219 220 shr_error_e dnx_gddr6_dram_refresh_enable_bitmap_get( 221 int unit, 222 int dram_index, 223 uint32 *refresh_enable_bitmap, 224 uint32 *refresh_ab_enable_bitmap); 225 226 shr_error_e dnx_gddr6_dram_refresh_enable_bitmap_set( 227 int unit, 228 int dram_index, 229 uint32 refresh_enable_bitmap, 230 uint32 refresh_ab_enable_bitmap); 231 232 233 shr_error_e dnx_gddr6_bist_start( 234 int unit, 235 int dram_index, 236 int channel); 237 238 239 shr_error_e dnx_gddr6_bist_stop( 240 int unit, 241 int dram_index, 242 int channel); 243 244 245 shr_error_e dnx_gddr6_bist_run_done_poll( 246 int unit, 247 int dram_index, 248 int channel); 249 250 251 shr_error_e dnx_gddr6_run_phy_tune( 252 int unit, 253 int dram_index, 254 int shmoo_type, 255 uint32 shmoo_flags, 256 dnx_gddr6_phy_tune_action_e action); 257 258 259 shr_error_e dnx_gddr6_bist_errors_check( 260 int unit, 261 dnx_gddr6_bist_status_cnt_t * bist_status_cnt, 262 dnx_gddr6_bist_err_cnt_t * bist_err_cnt, 263 int *bist_error_indicated); 264 265 266 shr_error_e dnx_gddr6_redirect_traffic_to_ocb( 267 int unit, 268 uint32 enable, 269 uint8 *dram_is_empty); 270 271 272 shr_error_e dnx_gddr6_bist_status_get( 273 int unit, 274 int dram_index, 275 int channel, 276 dnx_gddr6_bist_status_cnt_t * bist_status_cnt); 277 278 279 shr_error_e dnx_gddr6_dynamic_calibration_enable( 280 int unit, 281 int dram_index, 282 int channel, 283 int set_init_position); 284 285 286 shr_error_e dnx_gddr6_dynamic_calibration_disable( 287 int unit, 288 int dram_index, 289 int channel); 290 291 292 shr_error_e dnx_gddr6_dynamic_calibration_is_enabled( 293 int unit, 294 int dram_index, 295 int channel, 296 uint32 *is_enabled); 297 298 299 shr_error_e dnx_gddr6_dram_temp_get( 300 int unit, 301 int dram_index, 302 bcm_switch_thermo_sensor_t * sensor_data); 303 304 305 shr_error_e dnx_gddr6_dram_vendor_id_get( 306 int unit, 307 int dram, 308 uint32 *vendor_id); 309 310 311 shr_error_e dnx_gddr6_dram_vendor_id_to_vendor_info_decode( 312 int unit, 313 uint32 vendor_id, 314 gddr6_dram_vendor_info_t * vendor_info); 315 316 317 shr_error_e dnx_gddr6_vendor_info_from_sw_state_get( 318 int unit, 319 int dram_index, 320 gddr6_dram_vendor_info_t * vendor_info); 321 322 323 shr_error_e dnx_gddr6_vendor_info_from_sw_state_set( 324 int unit, 325 int dram_index, 326 gddr6_dram_vendor_info_t * vendor_info); 327 328 329 extern shr_error_e dnx_gddr6_call_backs_register( 330 int unit); 331 332 shr_error_e dnx_gddr6_dcc_blocks_enable_set( 333 int unit); 334 335 #endif