iqs.h (15083B)
1 /** \file bcm_int/dnx/cosq/ingress/iqs.h 2 * 3 * 4 * Module IQS - Ingress Queue Scheduling 5 * 6 * Configuration of Ingress TM queue scheduling, inclues: 7 * * Credit request profiles 8 * * Credit worth 9 * * FSM reorder mechanism 10 * 11 * Not including: 12 * * FMQ Credit generation(legacy implementation) 13 */ 14 15 /* 16 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 17 * 18 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 19 */ 20 21 #ifndef _DNX_IQS_INCLUDED__ 22 #define _DNX_IQS_INCLUDED__ 23 24 #ifndef BCM_DNX_SUPPORT 25 #error "This file is for use by DNX family only!" 26 #endif 27 28 #include <shared/shrextend/shrextend_error.h> 29 #include <bcm/cosq.h> 30 #include <soc/dnx/dbal/auto_generated/dbal_defines_fields.h> 31 #include <sal/core/time.h> 32 33 /* 34 * Defines: 35 * { 36 */ 37 38 /* 39 * } 40 */ 41 /* 42 * Typedefs: 43 * { 44 */ 45 46 /** 47 * \brief - SRAM or S2D deq parameters threshold types 48 */ 49 typedef enum 50 { 51 /* 52 * Below max deq cmd 53 */ 54 DNX_IQS_DEQ_PARAM_TYPE_MAX_DEQ_CMD_BELOW, 55 56 /* 57 * Above max deq cmd 58 */ 59 DNX_IQS_DEQ_PARAM_TYPE_MAX_DEQ_CMD_ABOVE, 60 61 /* 62 * Above 150% od max deq cmd 63 */ 64 DNX_IQS_DEQ_PARAM_TYPE_MAX_DEQ_CMD_ABOVE_EXTREME, 65 66 DNX_IQS_DEQ_PARAM_TYPE_NOF 67 } dnx_iqs_deq_param_type_e; 68 69 /** 70 * \brief - 71 * FSM (Flow Status Message) modes 72 */ 73 typedef enum 74 { 75 /** 76 * Add sequential number to FSM cell in order to handle reordering (recommended) 77 */ 78 dnx_iqs_fsm_mode_sequential = 0, 79 /** 80 * Wait before sending new FSM in order to prevent reordering. 81 */ 82 dnx_iqs_fsm_mode_delayed = 1, 83 84 /** 85 * Must be last 86 */ 87 dnx_iqs_fsm_mode_nof 88 } dnx_iqs_fsm_mode_e; 89 90 /** 91 * \brief Ingress congestion voq state info. 92 */ 93 typedef struct 94 { 95 /** 96 * credit request state 97 */ 98 dbal_enum_value_field_queue_credit_request_state_e credit_request_state; 99 /** 100 * Credit balance Bytes 101 */ 102 int credit_balance; 103 } dnx_iqs_voq_state_info_t; 104 105 /* 106 * } 107 */ 108 /* 109 * Module Init 110 * { 111 */ 112 113 /** 114 * \brief 115 * Initialize dnx iqs module. 116 * 117 * \param [in] unit - 118 * The unit number. 119 * \return 120 * See \ref shr_error_e 121 * \remark 122 * * None 123 * \see 124 * * None 125 */ 126 shr_error_e dnx_iqs_init( 127 int unit); 128 129 /* 130 * } 131 */ 132 133 /* 134 * Credit request profiles 135 * (Just the functions used by other modules) 136 * { 137 */ 138 /** 139 * \brief - 140 * Verify that the used profile_id already set once 141 * 142 * \param [in] unit - Unit-ID 143 * \param [in] profile_id - credit request profile id 144 * 145 * \return 146 * See shr_error_e 147 * \remark 148 * * None 149 * \see 150 * * None 151 */ 152 shr_error_e dnx_iqs_credit_request_profile_valid_verify( 153 int unit, 154 int profile_id); 155 /** 156 * \brief - 157 * Map ingress queue to credit request profile. 158 * 159 * \param [in] unit - Unit-ID 160 * \param [in] core - device core id 161 * \param [in] queue_id - ingress queue_id of base_queue 162 * \param [in] queue_offset - ingress queue offset inside a bundle 163 * \param [in] profile_id - credit request profile id 164 * 165 * \return 166 * See shr_error_e 167 * \remark 168 * * None 169 * \see 170 * * None 171 */ 172 shr_error_e dnx_iqs_credit_request_profile_map_set( 173 int unit, 174 int core, 175 int queue_id, 176 int queue_offset, 177 int profile_id); 178 179 /** 180 * \brief - 181 * Get the mapping of ingress queue to credit request profile. 182 * 183 * \param [in] unit - Unit-ID 184 * \param [in] core - device core id 185 * \param [in] queue_id - ingress queue_id of base queue 186 * \param [in] queue_offset - ingress queue offset inside a bundle 187 * \param [out] profile_id - credit request profile id 188 * 189 * \return 190 * See shr_error_e 191 * \remark 192 * * None 193 * \see 194 * * None 195 */ 196 shr_error_e dnx_iqs_credit_request_profile_map_get( 197 int unit, 198 int core, 199 int queue_id, 200 int queue_offset, 201 int *profile_id); 202 203 /** 204 * \brief - 205 * Clear ingress queue to credit request profile map. 206 * 207 * \param [in] unit - Unit-ID 208 * \param [in] core - device core id 209 * \param [in] queue_id - ingress queue_id of base_queue 210 * \param [in] queue_offset - ingress queue offset inside a bundle 211 * 212 * \return 213 * See shr_error_e 214 * \remark 215 * * None 216 * \see 217 * * None 218 */ 219 shr_error_e dnx_iqs_credit_request_profile_map_clear( 220 int unit, 221 int core, 222 int queue_id, 223 int queue_offset); 224 225 /* 226 * } 227 */ 228 /* 229 * Watchdog Period 230 * (Just the functions used by fabric APIs) 231 * { 232 */ 233 /** 234 * \brief - 235 * Set min queue id for watchdog mechanism to scan. 236 * Note that this function set sw data base only. 237 * In order to configure the hw accordingly - call to dnx_iqs_credit_watchdog_hw_set() 238 * 239 * \param [in] unit - Unit-ID 240 * \param [in] min_queue_id - min queue id 241 * 242 * \return 243 * See shr_error_e 244 * \remark 245 * * None 246 * \see 247 * * None 248 */ 249 shr_error_e dnx_iqs_credit_watchdog_queue_min_sw_set( 250 int unit, 251 int min_queue_id); 252 253 /** 254 * \brief - 255 * Get min queue id for watchdog mechanism to scan. 256 * 257 * \param [in] unit - Unit-ID 258 * \param [out] min_queue_id - min queue id 259 * 260 * \return 261 * See shr_error_e 262 * \remark 263 * * None 264 * \see 265 * * None 266 */ 267 shr_error_e dnx_iqs_credit_watchdog_queue_min_sw_get( 268 int unit, 269 int *min_queue_id); 270 271 /** 272 * \brief - 273 * Set max queue id for watchdog mechanism to scan. 274 * Note that this function set sw data base only. 275 * In order to configure the hw accordingly - call to dnx_iqs_credit_watchdog_hw_set() 276 * 277 * \param [in] unit - Unit-ID 278 * \param [in] min_queue_id - min queue id 279 * 280 * \return 281 * See shr_error_e 282 * \remark 283 * * None 284 * \see 285 * * None 286 */ 287 shr_error_e dnx_iqs_credit_watchdog_queue_max_sw_set( 288 int unit, 289 int min_queue_id); 290 291 /** 292 * \brief - 293 * Get max queue id for watchdog mechanism to scan. 294 * 295 * \param [in] unit - Unit-ID 296 * \param [out] min_queue_id - min queue id 297 * 298 * \return 299 * See shr_error_e 300 * \remark 301 * * None 302 * \see 303 * * None 304 */ 305 shr_error_e dnx_iqs_credit_watchdog_queue_max_sw_get( 306 int unit, 307 int *min_queue_id); 308 /** 309 * \brief - 310 * Enable / Disable credit watchdog mechanism. 311 * Note that this function set sw data base only. 312 * In order to configure the hw accordingly - call to dnx_iqs_credit_watchdog_hw_set() 313 * 314 * \param [in] unit - Unit-ID 315 * \param [in] enable - 1 to enable, 0 to disable 316 * 317 * \return 318 * See shr_error_e 319 * \remark 320 * * None 321 * \see 322 * * None 323 */ 324 shr_error_e dnx_iqs_credit_watchdog_enable_sw_set( 325 int unit, 326 int enable); 327 328 /** 329 * \brief - 330 * Enable / Disable credit watchdog mechanism. 331 * 332 * \param [in] unit - Unit-ID 333 * \param [out] enable - 1 to enable, 0 to disable 334 * 335 * \return 336 * See shr_error_e 337 * \remark 338 * * None 339 * \see 340 * * None 341 */ 342 shr_error_e dnx_iqs_credit_watchdog_enable_sw_get( 343 int unit, 344 int *enable); 345 346 /** 347 * \brief - 348 * Set Watchdog mechanism HW according to watchdog mechanism sw state. 349 * 350 * \param [in] unit - Unit-ID 351 * 352 * \return 353 * See shr_error_e 354 * \remark 355 * * None 356 * \see 357 * * None 358 */ 359 shr_error_e dnx_iqs_credit_watchdog_hw_set( 360 int unit); 361 362 /** 363 * \brief - 364 * Verify credit watchdog configuration 365 * 366 * \param [in] unit - Unit-ID 367 * 368 * \return 369 * See shr_error_e 370 * \remark 371 * * None 372 * \see 373 * * None 374 */ 375 shr_error_e dnx_iqs_credit_watchdog_verify( 376 int unit); 377 378 /* 379 * } 380 */ 381 /* 382 * Credit Worth 383 * { 384 */ 385 /** 386 * \brief - 387 * There are two groups of credit worth. 388 * Get credit worth of each group. 389 * 390 * \param [in] unit - Unit-ID 391 * \param [in] group_id - group 0 or group 1 392 * \param [out] credit_worth_bytes - credit worth in bytes 393 * 394 * \return 395 * See shr_error_e 396 * \remark 397 * * None 398 * \see 399 * * None 400 */ 401 shr_error_e dnx_iqs_credit_worth_group_get( 402 int unit, 403 int group_id, 404 uint32 *credit_worth_bytes); 405 /* 406 * } 407 */ 408 /* 409 * FSM mode 410 * Used to prevent FSM reordering 411 * { 412 */ 413 /** 414 * \brief - 415 * Set FSM mode per destination FAP-ID (sequential or delayed) 416 * 417 * \param [in] unit - Unit-ID 418 * \param [in] fap_id - destination fap id 419 * \param [in] fsm_mode - sequential or delayed, see enum 420 * 421 * \return 422 * See shr_error_e 423 * \remark 424 * * None 425 * \see 426 * * None 427 */ 428 shr_error_e dnx_iqs_fsm_mode_set( 429 int unit, 430 uint32 fap_id, 431 dnx_iqs_fsm_mode_e fsm_mode); 432 /** 433 * \brief - 434 * Get FSM mode per destination FAP-ID (sequential or delayed) 435 * 436 * \param [in] unit - Unit-ID 437 * \param [in] fap_id - destination fap id 438 * \param [in] fsm_mode - sequential or delayed, see enum 439 * 440 * \return 441 * See shr_error_e 442 * \remark 443 * * None 444 * \see 445 * * None 446 */ 447 shr_error_e dnx_iqs_fsm_mode_get( 448 int unit, 449 uint32 fap_id, 450 dnx_iqs_fsm_mode_e * fsm_mode); 451 /* 452 * } 453 */ 454 /* 455 * Debug 456 * { 457 */ 458 /** 459 * \brief - 460 * Set auto-credit over a range of queues 461 * 462 * \param [in] unit - Unit-ID 463 * \param [in] queue_min - min queue range. for disable set to 0. 464 * \param [in] queue_max - max queue range. for disable set to 0. 465 * \param [in] rate - rate of auto-credit in Mbps. 0 disables auto-credit. 466 * 467 * \return 468 * See shr_error_e 469 * \remark 470 * * None 471 * \see 472 * * None 473 */ 474 shr_error_e dnx_iqs_debug_autocredit_rate_set( 475 int unit, 476 uint32 queue_min, 477 uint32 queue_max, 478 uint32 rate); 479 480 /** 481 * \brief - 482 * Get auto-credit rate over a range of queues 483 * 484 * \param [in] unit - Unit-ID 485 * \param [out] queue_min - min queue range. 486 * \param [out] queue_max - max queue range. 487 * \param [out] rate - rate of auto-credit in Mbps. 0 disables auto-credit. 488 * 489 * \return 490 * See shr_error_e 491 * \remark 492 * * None 493 * \see 494 * * None 495 */ 496 shr_error_e dnx_iqs_debug_autocredit_rate_get( 497 int unit, 498 uint32 *queue_min, 499 uint32 *queue_max, 500 uint32 *rate); 501 502 /** 503 * \brief - Function to get queue state signals and credit request info 504 * 505 * \param [in] unit - unit index 506 * \param [in] voq_gport - voq_gport 507 * \param [in] cos - vos offset in the bundle 508 * \param [out] voq_state_info - voq credit state info 509 * 510 * \return 511 * shr_error_e 512 * 513 * \remark 514 * \see 515 * * None 516 */ 517 shr_error_e dnx_iqs_voq_state_info_get( 518 int unit, 519 bcm_gport_t voq_gport, 520 int cos, 521 dnx_iqs_voq_state_info_t * voq_state_info); 522 523 /** 524 * \brief - Map Queue to DQCQ priority 525 * 526 * \param [in] unit - unit index 527 * \param [in] core - device core id 528 * \param [in] voq - voq number 529 * \param [in] priority - priority index 530 * 531 * \return 532 * shr_error_e 533 * \remark 534 * only valid when DQCQ 8 priorities feature is enabled 535 * \see 536 * * None 537 */ 538 shr_error_e dnx_iqs_queue_to_priority_map_set( 539 int unit, 540 int core, 541 uint32 voq, 542 uint32 priority); 543 544 /** 545 * \brief - Get mapping from Queue to DQCQ priority 546 * 547 * \param [in] unit - unit index 548 * \param [in] core - device core id 549 * \param [in] voq - voq number 550 * \param [out] priority - priority index 551 * 552 * \return 553 * shr_error_e 554 * \remark 555 * only valid when DQCQ 8 priorities feature is enabled 556 * \see 557 * * None 558 */ 559 shr_error_e dnx_iqs_queue_to_priority_map_get( 560 int unit, 561 int core, 562 uint32 voq, 563 uint32 *priority); 564 565 /** 566 * \brief - Set DQCQ priority minimal LOW priority. 567 * DQCQ priorities are monotronic. 568 * 569 * \param [in] unit - unit index 570 * \param [in] min_low_priority - the minimum LOW priority. 571 * 572 * \return 573 * shr_error_e 574 * \remark 575 * only valid when DQCQ 8 priorities feature is enabled 576 * \see 577 * * None 578 */ 579 shr_error_e dnx_iqs_min_low_priority_set( 580 int unit, 581 uint32 min_low_priority); 582 583 /** 584 * \brief - Get DQCQ priority minimal LOW priority indication. 585 * DQCQ priorities are monotronic , and set to either HIGH or LOW priority. 586 * 587 * \param [in] unit - unit index 588 * \param [out] min_low_priority - minimal LOW priority 589 * 590 * \return 591 * shr_error_e 592 * \remark 593 * only valid when DQCQ 8 priorities feature is enabled 594 * \see 595 * * None 596 */ 597 shr_error_e dnx_iqs_min_low_priority_get( 598 int unit, 599 uint32 *min_low_priority); 600 601 /** 602 * \brief - Set Queue id for flush operation. 603 * 604 * \param [in] unit - unit index 605 * \param [in] core - device core id 606 * \param [in] voq - voq id to flush (actual flush operation is done in dnx_iqs_queue_flush_attributes_set) 607 * 608 * \return 609 * shr_error_e 610 * \see 611 * * None 612 */ 613 shr_error_e dnx_iqs_queue_flush_queue_id_set( 614 int unit, 615 int core, 616 uint32 voq); 617 618 /** 619 * \brief - Get Queue id for flush operation. 620 * (actual flush operation is done in dnx_iqs_queue_flush_attributes_set) 621 * 622 * \param [in] unit - unit index 623 * \param [in] core - device core id 624 * \param [out] voq - voq id flushed 625 * 626 * \return 627 * shr_error_e 628 * \see 629 * * None 630 */ 631 shr_error_e dnx_iqs_queue_flush_queue_id_get( 632 int unit, 633 int core, 634 uint32 *voq); 635 636 /** 637 * \brief - Set Queue flush attributes for flush operation. 638 * (Queue id to be flushed is specified in dnx_iqs_queue_flush_queue_id_set) 639 * 640 * \param [in] unit - unit index 641 * \param [in] core - device core id 642 * \param [in] is_del_dqcq - indication whether to put the queue in delete DQCQ, or keep in the relevant DQCQ 643 * \param [in] bytes_units_to_send - Number of bytes to send from the queue in flush process (64B units) 644 * \param [in] flush_en - trigger the flush operation 645 * 646 * \return 647 * shr_error_e 648 * \see 649 * * None 650 */ 651 shr_error_e dnx_iqs_queue_flush_attributes_set( 652 int unit, 653 int core, 654 uint32 is_del_dqcq, 655 uint32 bytes_units_to_send, 656 uint32 flush_en); 657 658 /** 659 * \brief - Get Queue flush attributes for flush operation. 660 * (Queue id to be flushed is specified in dnx_iqs_queue_flush_queue_id_set) 661 * 662 * \param [in] unit - unit index 663 * \param [in] core - device core id 664 * \param [out] is_del_dqcq - indication whether the queue in set in delete DQCQ, or kept in the relevant DQCQ 665 * \param [out] bytes_units_to_send - Number of bytes to send from the queue in flush process (64B units) 666 * \param [out] flush_en - indication whether flush operation is still triggered (when flush is done, this value should be set to 0) 667 * 668 * \return 669 * shr_error_e 670 * \see 671 * * None 672 */ 673 shr_error_e dnx_iqs_queue_flush_attributes_get( 674 int unit, 675 int core, 676 uint32 *is_del_dqcq, 677 uint32 *bytes_units_to_send, 678 uint32 *flush_en); 679 680 /** 681 * \brief - 682 * Polling VOQ flush process is done 683 * 684 * \param [in] unit - Unit-ID 685 * \param [in] core - device core id 686 * \param [in] timeout - time out value in usecs, maximal time for polling 687 * 688 * \return 689 * See shr_error_e 690 * \remark 691 * * None 692 * \see 693 * * None 694 */ 695 shr_error_e dnx_iqs_queue_flush_trigger_down_polling( 696 int unit, 697 int core, 698 sal_usecs_t timeout); 699 700 /** 701 * \brief - 702 * Enable/disable profile as push queue 703 * 704 * \param [in] unit - Unit-ID 705 * \param [in] profile_id - credit request profile id for push queue 706 * \param [in] enable - enable push queue 707 * 708 * \return 709 * See shr_error_e 710 * \remark 711 * * None 712 * \see 713 * * None 714 */ 715 shr_error_e dnx_iqs_push_queue_set( 716 int unit, 717 uint32 profile_id, 718 uint32 enable); 719 720 /** 721 * \brief - 722 * Get push queue profile 723 * 724 * \param [in] unit - Unit-ID 725 * \param [in] profile_id - credit request profile id for push queue 726 * \param [in] enable - is push queue enable 727 * 728 * \return 729 * See shr_error_e 730 * \remark 731 * * None 732 * \see 733 * * None 734 */ 735 shr_error_e dnx_iqs_push_queue_get( 736 int unit, 737 uint32 *profile_id, 738 uint32 *enable); 739 740 /* 741 * } 742 */ 743 744 #endif/*_DNX_IQS_INCLUDED__*/