egr_queuing.h (45746B)
1 /** \file egr_queuing.h 2 * 3 * 4 * Internal DNX Port APIs 5 * 6 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 7 * 8 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 9 */ 10 11 #ifndef EGR_QUEUING_H_INCLUDED 12 /** { */ 13 #define EGR_QUEUING_H_INCLUDED 14 15 #ifndef BCM_DNX_SUPPORT 16 #error "This file is for use by DNX (JR2) family only!" 17 #endif 18 19 #include <shared/shrextend/shrextend_debug.h> 20 #include <bcm/types.h> 21 #include <bcm/cosq.h> 22 #include <bcm_int/dnx/cosq/cosq.h> 23 24 #include <soc/dnx/dnx_data/auto_generated/dnx_data_egr_queuing.h> 25 26 /************* 27 * DEFINES * 28 */ 29 /* { */ 30 31 /* 32 * Number of FAP-data-ports. 33 */ 34 #define DNX_NOF_FAP_PORTS 256 35 #define DNX_MAX_FAP_PORT_ID (DNX_NOF_FAP_PORTS-1) 36 37 #define DNX_EGR_QUEUE_DEFAULT_PROFILE_MAP (0) 38 #define DNX_EGR_Q_ALMOST_EMPTY_DELAY (3) 39 #define DNX_EGQ_COUNTER_INFO_GET(_info, _handle_id, _table, _field, _name, _type, _has_ovf) \ 40 { \ 41 sal_snprintf(_info.name, DNX_EGQ_COUNTER_NAME_LEN, "%s", _name); \ 42 _info.type = _type; \ 43 _info.has_ovf = _has_ovf; \ 44 dbal_tables_field_size_get(unit, _table, _field, 0, 0, 0,&_info.counter_size); \ 45 dbal_value_field64_request(unit, _handle_id, _field, INST_SINGLE, &(_info.count_val)); \ 46 } 47 #define DNX_EGQ_SHAPER_MODE_NOF_BITS (1) 48 49 /** 50 * PS_MODE values to load into HW to indicate priority mode for a qpair group 51 * (port scheduler). See EPS_PS_MODE register (or DBAL_TABLE_ 52 */ 53 #define DNX_EGQ_PS_MODE_ONE_PRIORITY_VAL (0) 54 #define DNX_EGQ_PS_MODE_TWO_PRIORITY_VAL (1) 55 #define DNX_EGQ_PS_MODE_FOUR_PRIORITY_VAL (2) 56 #define DNX_EGQ_PS_MODE_EIGHT_PRIORITY_VAL (3) 57 58 #define DNX_EGQ_TCG_WEIGHT_MIN (0) 59 #define DNX_EGQ_TCG_WEIGHT_MAX (255) 60 /** 61 * TCG: Number of groups 62 */ 63 #define DNX_NOF_TCGS (dnx_data_egr_queuing.params.nof_tcg_get(unit)) 64 #define DNX_TCG_MIN 0 65 #define DNX_TCG_MAX (DNX_NOF_TCGS-1) 66 /* 67 * This range, DNX_TCG_MIN - DNX_TCG_MAX, must not overlap BCM_COSQ_SP0 - BCM_COSQ_SP7 68 * See dnx_cosq_egq_gport_egress_tc_to_tcg_map_set() 69 */ 70 #if (DNX_DATA_MAX_EGR_QUEUING_PARAMS_NOF_TCG >= BCM_COSQ_SP0) 71 #error "Must be smaller than" 72 #endif 73 #define DNX_EGR_NOF_Q_PAIRS (dnx_data_egr_queuing.params.nof_q_pairs_get(unit)) 74 #define DNX_EGR_NOF_BASE_Q_PAIRS (DNX_EGR_NOF_Q_PAIRS) 75 /** 76 * Number of qpairs per one port scheduler. 77 */ 78 #define DNX_EGR_NOF_Q_PAIRS_IN_PS (dnx_data_egr_queuing.params.nof_q_pairs_in_ps_get(unit)) 79 #define DNX_NOF_TCGS_IN_PS (dnx_data_egr_queuing.params.nof_egr_q_prio_get(unit)) 80 /** 81 * Total number of port schedulers. This is calculated by dividing the total 82 * number of 'qpair's by the number of qpairs per one port scheduler. 83 * See 'nof_q_pairs_in_ps' and 'nof_q_pairs' in dnx_egr_queuing.xml 84 */ 85 #define DNX_EGR_NOF_PS (dnx_data_egr_queuing.params.nof_port_schedulers_get(unit)) 86 #define DNX_EGR_NOF_TCG_IDS (DNX_EGR_NOF_PS * DNX_NOF_TCGS) 87 #define DNX_EGQ_COUNTER_NAME_LEN (64) 88 #define DNX_EGQ_RQP_COUNTER_NUM (18) 89 #define DNX_EGQ_PQP_COUNTER_NUM (8) 90 #define DNX_EGQ_EPNI_COUNTER_NUM (5) 91 #define DNX_EGQ_COUNTER_NUM_SUM (DNX_EGQ_RQP_COUNTER_NUM + DNX_EGQ_PQP_COUNTER_NUM + 2*DNX_EGQ_EPNI_COUNTER_NUM) 92 93 #define DNX_EGQ_NOF_TCG_IN_BITS (dnx_data_egr_queuing.params.nof_bits_in_nof_tcg_get(unit)) 94 95 /** 96 * Flag to indicate counters that can be configured. 97 */ 98 #define DNX_EGQ_PROGRAMMABLE_COUNTER (0x1) 99 /** 100 * Flag to indicate counters that can not be configured. 101 */ 102 #define DNX_EGQ_NON_PROGRAMMABLE_COUNTER (0x2) 103 /** 104 * Flag to indicate EPNI Queue counters. 105 */ 106 #define DNX_EGQ_EPNI_QUEUE_COUNTER (0x4) 107 /** 108 * Flag to indicate EPNI Interface counters. 109 */ 110 #define DNX_EGQ_EPNI_IF_COUNTER (0x8) 111 /** 112 * Flag to indicate EPNI Mirror counters. 113 */ 114 #define DNX_EGQ_EPNI_MIRROR_COUNTER (0x10) 115 /** 116 * Flag to indicate the configuration of counting bytes. 117 */ 118 #define DNX_EGQ_CONFIGURATION_COUNT_BYTES (0x20) 119 /** 120 * Flag to indicate the configuration of counting packets. 121 */ 122 #define DNX_EGQ_CONFIGURATION_COUNT_PACKETS (0x40) 123 #define DNX_EGR_OFP_SCH_WFQ_WEIGHT_MAX 255 124 125 #define DNX_EGR_SINGLE_MEMBER_TCG_START (4) 126 #define DNX_EGR_SINGLE_MEMBER_TCG_END (7) 127 128 /* } */ 129 /************* 130 * TYPEDEFS * 131 */ 132 /* { */ 133 134 typedef enum 135 { 136 /** 137 * Discrete partition scheme . 138 * Set the thresholds independently. 139 * If the number of allocated resources exceeds the threshold of a given priority, . 140 * then all packets with that priority are dropped. 141 */ 142 DNX_EGR_QUEUING_PARTITION_SCHEME_DISCRETE = 0, 143 /** 144 * Strict partition scheme. Set the thresholds in ascending order. 145 * If the number of allocated resources exceeds a threshold, 146 * Threshold(i) for example, 147 * then all packets whose priority is less than i are dropped. 148 */ 149 DNX_EGR_QUEUING_PARTITION_SCHEME_STRICT = 1, 150 /** 151 * Total number of partition schemes. 152 */ 153 DNX_NOF_EGR_QUEUING_PARTITION_SCHEMES = 2 154 } dnx_egr_queuing_partition_scheme_e; 155 156 typedef struct 157 { 158 /** 159 * The lower the weight the higher the bandwidth. 160 * Weight of 0 for a class indicates that this class 161 * has SP over the other class. 162 * When both have equal weights it implies simple RR. 163 * Range: 0-255 164 */ 165 uint32 tcg_weight; 166 /** 167 * If set, tcg weight is valid and taking part of the 168 * WFQ policy. 169 */ 170 uint8 tcg_weight_valid; 171 172 } dnx_egr_tcg_sch_wfq_t; 173 174 typedef enum 175 { 176 /** 177 * Port shaper is in data mode. 178 */ 179 DNX_EGR_PORT_SHAPER_DATA_MODE = 0, 180 /** 181 * Port shaper is in packet mode. 182 */ 183 DNX_EGR_PORT_SHAPER_PACKET_MODE = 1, 184 /** 185 * Total number of Port shaper modes. 186 */ 187 DNX_EGR_NOF_PORT_SHAPER_MODES = 2 188 } dnx_egr_port_shaper_mode_e; 189 190 typedef enum 191 { 192 /** 193 * Port with one priority. 194 */ 195 DNX_EGR_PORT_ONE_PRIORITY = 1, 196 /** 197 * Port with two priorities. 198 */ 199 DNX_EGR_PORT_TWO_PRIORITIES = 2, 200 /* 201 * Port with two priorities. 202 */ 203 DNX_EGR_PORT_FOUR_PRIORITIES = 4, 204 /** 205 * Port with eight priorities. 206 */ 207 DNX_EGR_PORT_EIGHT_PRIORITIES = 8, 208 /** 209 * Total number of Port prioritie modes. 210 */ 211 DNX_EGR_NOF_PORT_PRIORITY_MODES = 4 212 } dnx_egr_port_priority_mode_e; 213 214 /** 215 * Port id. 216 * DNX range: 0-255. 217 */ 218 typedef uint32 dnx_fap_port_id_t; 219 220 typedef struct 221 { 222 /** 223 * Egress Traffic Class. In general, Range: 0 - 1. 224 * (Equivalent to High (0)/Low (1)). The range can be higher 225 * according to the extended queuing OFP-group 226 * configuration (Possible global maximum: 1, 3, 5 and 7). 227 */ 228 uint32 tc; 229 /** 230 * Egress Drop precedence (drop priority). Range: 0 - 3. 231 */ 232 uint32 dp; 233 234 } dnx_egr_q_priority_t; 235 236 typedef enum 237 { 238 FIRST_DNX_EGR_CAL_TYPE = 0, 239 CAL_TYPE_FQP = FIRST_DNX_EGR_CAL_TYPE, 240 CAL_TYPE_PQP, 241 NUM_DNX_EGR_CAL_TYPE 242 } dnx_egr_cal_type_e; 243 /** 244 * specifies the selection of Almost empty minimum gap when All Qs under an interface are AE but the interface is not. 245 */ 246 typedef enum dnx_egr_ifc_min_gap_e 247 { 248 /** 249 * selected for non-channelized interface with 4 or 8 priorities 250 */ 251 DNX_EGR_IFC_MIN_GAP_4_8, 252 /** 253 * selected for channelized interface 254 */ 255 DNX_EGR_IFC_MIN_GAP_CHANNELIZED, 256 /** 257 * selected for channelized interface with 1 or 2 priorities 258 */ 259 DNX_EGR_IFC_MIN_GAP_1_2, 260 DNX_EGR_IFC_MIN_GAP_MAX 261 } dnx_egr_ifc_min_gap_e; 262 /** 263 * specifies the Egress multicast replication fifo's types 264 */ 265 typedef enum dnx_egr_emr_fifo_e 266 { 267 DNX_EGR_EMR_FIFO_TDM, 268 DNX_EGR_EMR_FIFO_UC, 269 DNX_EGR_EMR_FIFO_MC_HIGH, 270 DNX_EGR_EMR_FIFO_MC_LOW, 271 DNX_EGR_EMR_FIFO_MAX 272 } dnx_egr_emr_fifo_t; 273 /** 274 * specifies the egq counter type 275 */ 276 typedef enum dnx_egq_counter_type_e 277 { 278 DNX_EGQ_COUTNER_TYPE_PACKET, 279 DNX_EGQ_COUTNER_TYPE_BYTE 280 } dnx_egq_counter_type_t; 281 /** 282 * specifies the egq counter filter configuration 283 */ 284 typedef enum dnx_egq_counter_filter_e 285 { 286 DNX_EGQ_COUTNER_FILTER_BY_QP, 287 DNX_EGQ_COUTNER_FILTER_BY_OTM, 288 DNX_EGQ_COUTNER_FILTER_BY_IF, 289 DNX_EGQ_COUTNER_FILTER_BY_MIRROR, 290 DNX_EGQ_COUTNER_FILTER_BY_NONE 291 } dnx_egq_counter_filter_t; 292 /** 293 * data structure for egq counter information 294 */ 295 typedef struct 296 { 297 char name[DNX_EGQ_COUNTER_NAME_LEN]; 298 dnx_egq_counter_type_t type; 299 uint64 count_val; 300 int has_ovf; 301 int count_ovf; 302 int counter_size; 303 } dnx_egq_counter_info_t; 304 typedef struct 305 { 306 /** 307 * Service pool eligibility. Indicates if it can use shared resources. 308 * Range: 0 - 1. 309 */ 310 uint32 pool_eligibility; 311 /** 312 * Service Pool index. 313 * Range: 0 - 1. 314 */ 315 uint32 pool_id; 316 /** 317 * Traffic Class group for service pool thresholds. 318 * Range: 0 - 7. 319 */ 320 uint32 tc_group; 321 } dnx_egr_queuing_mc_cos_map_t; 322 323 typedef enum 324 { 325 FIRST_DNX_EGR_Q_PRIO_MAPPING_TYPE = 0, 326 /** 327 * Mapping from Traffic Class and Drop Precedence to Egress 328 * Queue Priority:Unicast packets to scheduled queues. 329 */ 330 DNX_EGR_UCAST_TO_SCHED = FIRST_DNX_EGR_Q_PRIO_MAPPING_TYPE, 331 /** 332 * Multicast packets to unscheduled queues (unscheduled 333 * multicast). 334 */ 335 DNX_EGR_MCAST_TO_UNSCHED, 336 /** 337 * Must be the last value. Indicates the number of [Traffic 338 * Class, Drop Precedence] to Egress Queue Priority Mapping 339 * modes. 340 */ 341 NUM_DNX_EGR_Q_PRIO_MAPPING_TYPE 342 } dnx_egr_q_prio_mapping_type_e; 343 344 /* 345 * See dnx_egr_q_prio_mapping_type_e 346 */ 347 #define DNX_DEVICE_COSQ_EGR_NOF_Q_PRIO_MAPPING_TYPES (NUM_DNX_EGR_Q_PRIO_MAPPING_TYPE) 348 349 typedef struct 350 { 351 /** 352 * Schedule (UC) words consumed per priority 353 */ 354 dnx_egr_q_priority_t queue_mapping[NUM_DNX_EGR_Q_PRIO_MAPPING_TYPE][DNX_COSQ_NOF_TC][DNX_COSQ_NOF_DP]; 355 } dnx_cosq_egress_queue_mapping_info_t; 356 357 /* 358 * Set of parameters related to FQP profile 359 */ 360 typedef struct 361 { 362 int irdy_thr; 363 int txq_max_bytes; 364 int is_belong_to_sub_calendar; 365 int txq_tdm_irdy; 366 int min_gap; 367 int serve_consecutive_if; 368 } dnx_fqp_profile_params_t; 369 370 /* 371 * TCG Traffic class groups. Range: 0-7 372 */ 373 typedef uint32 dnx_tcg_ndx_t; 374 typedef enum 375 { 376 /** 377 * Egress priority for unscheduled traffic - low 378 */ 379 DNX_EGR_Q_PRIO_LOW = 0, 380 /** 381 * Egress priority for unscheduled traffic - high 382 */ 383 DNX_EGR_Q_PRIO_HIGH = 1, 384 /** 385 * Number of egress priorities for unscheduled traffic - petra B. 386 */ 387 DNX_EGR_NOF_Q_PRIO_PB = 2, 388 /** 389 * Egress priority in DNX 0 - 7 390 */ 391 DNX_EGR_Q_PRIO_0 = 0, 392 DNX_EGR_Q_PRIO_1 = 1, 393 DNX_EGR_Q_PRIO_2 = 2, 394 DNX_EGR_Q_PRIO_3 = 3, 395 DNX_EGR_Q_PRIO_4 = 4, 396 DNX_EGR_Q_PRIO_5 = 5, 397 DNX_EGR_Q_PRIO_6 = 6, 398 DNX_EGR_Q_PRIO_7 = 7, 399 /** 400 * Number of egress priorities for unscheduled traffic. 401 */ 402 DNX_EGR_NOF_Q_PRIO 403 } dnx_egr_q_prio_e; 404 typedef struct 405 { 406 /** 407 * TCG (Traffic class groups) that the q-pair is mapped to. 408 * Range: 0 - 7 . 409 */ 410 dnx_tcg_ndx_t tcg_ndx[DNX_EGR_NOF_Q_PRIO]; 411 } dnx_egr_queuing_tcg_info_t; 412 413 typedef struct 414 { 415 /** 416 * Unscheduled, or Unscheduled weight. The lower the 417 * weight the higher the bandwidth. Weight of 0 for a class 418 * indicates that this class has SP over the other class. 419 * When both have equal weights it implies simple RR. 420 * Range: 0-255 421 */ 422 uint32 unsched_weight; 423 /** 424 * Scheduled, or Scheduled weight. Format -same as 425 * unscheduled. Range: 0 - 255. 426 */ 427 uint32 sched_weight; 428 429 } dnx_egr_ofp_sch_wfq_t; 430 431 typedef enum 432 { 433 FIRST_DNX_EGR_OFP_INTERFACE_PRIO = 0, 434 /** 435 * Outgoing FAP Strict Priority, for egress scheduling - 436 * high. Note: this priority is only valid for ports mapped 437 * to channelized NIF port! Otherwise - ignored. 438 */ 439 DNX_EGR_OFP_INTERFACE_PRIO_HIGH = FIRST_DNX_EGR_OFP_INTERFACE_PRIO, 440 /** 441 * OFP priority - low 442 */ 443 DNX_EGR_OFP_INTERFACE_PRIO_LOW, 444 /** 445 * Must be the last value. Indicates the number of OFP 446 * scheduling priorities. 447 */ 448 DNX_EGR_OFP_CHNIF_NOF_PRIORITIES 449 } dnx_egr_ofp_interface_prio_e; 450 451 typedef struct 452 { 453 uint32 mc_or_mc_low_queue_weight; 454 uint32 uc_or_uc_low_queue_weight; 455 } dnx_egq_dwm_tbl_data_t; 456 457 typedef struct 458 { 459 uint32 lb_key_max; 460 uint32 lb_key_min; 461 uint32 second_range_lb_key_max; 462 uint32 second_range_lb_key_min; 463 uint32 is_stacking_port; 464 uint32 peer_tm_domain_id; 465 uint32 port_type; 466 uint32 cnm_intrcpt_fc_vec_llfc; 467 uint32 cnm_intrcpt_fc_vec_pfc; 468 uint32 cnm_intrcpt_fc_en; 469 uint32 cnm_intrcpt_drop_en; 470 uint32 ad_count_out_port_flag; 471 uint32 cgm_port_profile; /* Threshold type */ 472 uint32 cgm_interface; 473 uint32 base_q_pair_num; 474 uint32 cos_map_profile; 475 uint32 pmf_data; 476 uint32 disable_filtering; 477 } dnx_egq_ppct_tbl_data_t; 478 479 typedef struct 480 { 481 /** 482 * 4b 483 */ 484 uint32 map_profile; 485 /** 486 * 1b 487 */ 488 uint32 is_egr_mc; 489 /** 490 * 3b 491 */ 492 uint32 tc; 493 /** 494 * 2b 495 */ 496 uint32 dp; 497 498 } dnx_egq_tc_dp_map_tbl_entry_t; 499 typedef struct 500 { 501 uint32 tc; 502 uint32 dp; 503 } dnx_egq_tc_dp_map_tbl_data_t; 504 505 typedef int dnx_port_t; 506 507 typedef struct 508 { 509 /** 510 * Strict Priority, if mapped to channelized 511 * Interface. Otherwise - ignored by the HW. 512 */ 513 dnx_egr_ofp_interface_prio_e nif_priority; 514 /** 515 * WFQ weights. The WFQ is among priority traffic 516 * (scheduled/unscheduled). Each index corresponds 517 * to q-pair. 518 * Valid for DNX only. 519 */ 520 dnx_egr_ofp_sch_wfq_t ofp_wfq_q_pair[DNX_EGR_NOF_Q_PRIO]; 521 } dnx_egr_ofp_sch_info_t; 522 523 /* } */ 524 /**************** 525 * PROTOTYPES * 526 */ 527 /* { */ 528 529 int dnx_egr_queuing_default_tc_dp_map_set( 530 int unit, 531 bcm_port_t port); 532 /** 533 * \brief - 534 * Sets bandwidth for egress mirror/recycle channel 535 * 536 * \param [in] unit - 537 * HW Unit-ID 538 * \param [in] core - 539 * Core to update HW on. 540 * \param [in] is_mirror - 541 * If non zero then update DBAL_FIELD_HP_MIRR_RATE in HW (HP_MIRR_TRAFFIC_SHAPER_CONFIGURATION) 542 * Else update DBAL_FIELD_RCY_RATE (RECYLED_TRAFFIC_SHAPER_CONFIGURATION) 543 * \param [in] kbits_sec_speed - 544 * Required rate, in kbps. 545 * \return 546 * If zero (_SHR_E_NONE), then no error was encountered. 547 * Otherwise, see shr_error_e 548 * \remark 549 * * None 550 * \see 551 * * bcm_dnx_cosq_gport_bandwidth_set 552 */ 553 shr_error_e dnx_egr_queuing_recycle_bandwidth_set( 554 int unit, 555 int core, 556 int is_mirror, 557 uint32 kbits_sec_speed); 558 /** 559 * \brief - gets bandwidth for egress recycle channel (mirror/recycle) 560 * 561 * \param [in] unit - 562 * HW Unit-ID 563 * \param [in] core - 564 * Core to retrieve HW info for. 565 * \param [in] is_mirror - 566 * If non zero then access DBAL_FIELD_HP_MIRR_RATE in HW (HP_MIRR_TRAFFIC_SHAPER_CONFIGURATION) 567 * Else access DBAL_FIELD_RCY_RATE (RECYLED_TRAFFIC_SHAPER_CONFIGURATION) 568 * \param [out] kbits_sec_speed_p - 569 * This procedure loads pointed memory by channel rate in kbps 570 * \return 571 * shr_error_e 572 * \remark 573 * * None 574 * \see 575 * * bcm_dnx_cosq_gport_bandwidth_get 576 */ 577 shr_error_e dnx_egr_queuing_recycle_bandwidth_get( 578 int unit, 579 int core, 580 int is_mirror, 581 uint32 *kbits_sec_speed_p); 582 /** 583 * \brief - 584 * Sets burst size for egress recycle channel (mirror/recycle) 585 * \param [in] unit - 586 * HW Unit-ID 587 * \param [in] core - 588 * Core to use for HW access. 589 * \param [in] is_mirror - 590 * If non-zero, channel is mirror recycle port 591 * Else, channel is plain recycle port 592 * \param [out] burst - 593 * Required channel burst size, in bytes 594 * \return 595 * shr_error_e 596 * \remark 597 * * None 598 * \see 599 * * bcm_dnx_cosq_control_set 600 */ 601 shr_error_e dnx_egr_recycle_burst_set( 602 int unit, 603 int core, 604 int is_mirror, 605 uint32 burst); 606 /** 607 * \brief - 608 * Gets burst size for egress recycle channel (mirror/recycle) 609 * \param [in] unit - 610 * HW Unit-ID 611 * \param [in] core - 612 * Core to use for HW access. 613 * \param [in] is_mirror - 614 * If non-zero, channel is mirror recycle port 615 * Else, channel is plain recycle port 616 * \param [out] burst - 617 * This procedure loads pointed memory by channel burst size, in bytes 618 * \return 619 * shr_error_e 620 * \remark 621 * * None 622 * \see 623 * * bcm_dnx_cosq_control_get 624 */ 625 shr_error_e dnx_egr_recycle_burst_get( 626 int unit, 627 int core, 628 int is_mirror, 629 uint32 *burst); 630 /** 631 * \brief - 632 * Sets weight for EIR traffic on egress recycle channel (Either mirror or recycle) 633 * \param [in] unit - 634 * HW Unit-ID 635 * \param [in] core - 636 * Core to use for HW access. 637 * \param [in] is_mirror - 638 * If non-zero, channel is WFQ mirror recycle port 639 * Else, channel is WFQ plain recycle port 640 * \param [in] weight - 641 * If zero then disable traffic, as specified in 'is_mirror'. 642 * Else, enable this type of traffic and set its weight as specified. 643 * In that case, weight can be in the range 1 - 255. 644 * \return 645 * shr_error_e 646 * \remark 647 * * None 648 * \see 649 * * bcm_dnx_cosq_gport_sched_set (GPORT_IS_RCY/GPORT_IS_RCY_MIRR) 650 */ 651 shr_error_e dnx_egr_recycle_weight_set( 652 int unit, 653 int core, 654 int is_mirror, 655 uint32 weight); 656 /** 657 * \brief - 658 * Gets weight for EIR traffic on egress recycle channel (Either mirror or recycle) 659 * \param [in] unit - 660 * HW Unit-ID 661 * \param [in] core - 662 * Core to use to retrieve HW info from. 663 * \param [in] is_mirror - 664 * If non-zero, channel is WFQ mirror recycle port 665 * Else, channel is WFQ plain recycle port 666 * \param [out] weight - 667 * This procedure loads pointed memory by channel weight. Range is 1-255. 668 * If loaded by '0' then traffic is disabled on this channel. 669 * \return 670 * shr_error_e 671 * \remark 672 * * None 673 * \see 674 * * None 675 */ 676 shr_error_e dnx_egr_recycle_weight_get( 677 int unit, 678 int core, 679 int is_mirror, 680 uint32 *weight); 681 /** 682 * \brief - gets port to egress recycle interface mapping 683 * 684 * \param [in] unit - Unit-ID 685 * \param [in] port - port 686 * \param [out] rcy_if_idx - recycle interface index 687 * 688 * \return 689 * shr_error_e 690 * \remark 691 * * None 692 * \see 693 * * None 694 */ 695 shr_error_e dnx_egr_port_recycle_interface_map_get( 696 int unit, 697 bcm_port_t port, 698 int *rcy_if_idx); 699 /** 700 * \brief - egr_queuing implementation nif credit init 701 * 702 * \param [in] unit - Unit-ID 703 * \param [in] port - port 704 * 705 * \return 706 * shr_error_e 707 * \remark 708 * * None 709 * \see 710 * * None 711 */ 712 shr_error_e dnx_egr_queuing_nif_credit_default_set( 713 int unit, 714 bcm_port_t port); 715 716 /** 717 * \brief - sets the IRDY & txq_max_bytes threshold per speed. The value retrieved from dnx_data 718 * 719 * \param [in] unit - Unit-ID 720 * \param [in] port - port 721 * 722 * \return 723 * shr_error_e 724 * \remark 725 * * None 726 * \see 727 * * None 728 */ 729 shr_error_e dnx_egr_queuing_if_thr_set( 730 int unit, 731 bcm_port_t port); 732 733 /** 734 * \brief - configure in HW if the egress interface is belong to sub calendar or not, according to the interface speed. 735 * \param [in] unit - Unit-ID 736 * \param [in] port - port 737 * 738 * \return 739 * shr_error_e 740 * \remark 741 * * None 742 * \see 743 * * None 744 */ 745 shr_error_e dnx_egr_queuing_if_sub_calendar_set( 746 int unit, 747 bcm_port_t port); 748 749 /** 750 * \brief - 751 * Based on setup of rate of master ports, load interface calendars for 752 * both FQP and PQP. 753 * 754 * \param [in] unit - 755 * HW Unit-ID 756 * \param [in] core - 757 * Core to use to access HW. 758 * \return 759 * If zero (_SHR_E_NONE), then no error was encountered. 760 * Otherwise, see shr_error_e 761 * \remark 762 * * Indirect input is the 'rate' setup for all master ports (assigned per interface). 763 * See dnx_algo_port_interface_rate_get() 764 * \see 765 * * dnx_egr_queuing_nif_calendar_set 766 */ 767 shr_error_e dnx_egr_queuing_nif_calendar_set( 768 int unit, 769 bcm_core_t core); 770 /* 771 * \brief - 772 * This procedure is called, within the sequence of adding a port, to 773 * set 'packet mode' for an interface port (and for all ports under 774 * this interface). 775 * Calling this procedure is not compulsory. If not called, default 776 * value is used. 777 * \param [in] unit - 778 * int. HW identifier of unit. 779 * \param [in] logical_port - 780 * bcm_port_t. Identifier of the interface to initialize (using a contained port). 781 * \param [in] arg - 782 * int. Value to set for 'packet mode'. May be '1' (if 'packet mode' 783 * is required) of '0' (standard bit mode). 784 * \return 785 * If zero (_SHR_E_NONE), then no error was encountered. 786 * Otherwise, see shr_error_e 787 * \remark 788 * * If 'packet mode' is required then shaping is done in units of 789 * full packets. 790 * * This procedure is only meaningful for 'egress TM' ports. It is 791 * assumed here that a validity check has been carried out by the 792 * caller. 793 * \see 794 * * dnx_egr_queuing_port_add_handle 795 * * port_add_remove_sequence[] 796 * * bcm_dnx_port_add 797 */ 798 shr_error_e dnx_egr_queuing_interface_packet_mode_set( 799 int unit, 800 bcm_port_t logical_port, 801 int arg); 802 /* 803 * \brief - 804 * This procedure is called to get 'packet mode' for an interface port 805 * (and for all ports under this interface). 806 * \param [in] unit - 807 * int. HW identifier of unit. 808 * \param [in] logical_port - 809 * bcm_port_t. Identifier of the interface to inquire (via contained logical port). 810 * \param [out] arg - 811 * Pointer to int. This procedure loads pointed memory by current value 812 * of 'packet mode'. May be '1' (if 'packet mode' is active) of '0' 813 * (standard bit mode). 814 * \return 815 * If zero (_SHR_E_NONE), then no error was encountered. 816 * Otherwise, see shr_error_e 817 * \remark 818 * * If 'packet mode' is set then shaping is done in units of 819 * full packets. 820 * * This procedure is only meaningful for 'egress TM' ports. It is 821 * assumed here that a validity check has been carried out by the 822 * caller. 823 * \see 824 * * dnx_egr_queuing_port_add_handle 825 * * port_add_remove_sequence[] 826 * * bcm_dnx_port_add 827 * * dnx_egr_queuing_interface_packet_mode_set 828 */ 829 shr_error_e dnx_egr_queuing_interface_packet_mode_get( 830 int unit, 831 bcm_port_t logical_port, 832 int *arg); 833 834 /* 835 * \brief - 836 * This procedure is called, within the sequence of adding a port, to 837 * set 'packet mode' for a logical port 838 * Calling this procedure is not compulsory. If not called, default 839 * value is used. 840 * \param [in] unit - 841 * int. HW identifier of unit. 842 * \param [in] logical_port - 843 * bcm_port_t. Identifier of the logical port. 844 * \param [in] arg - 845 * int. Value to set for 'packet mode'. May be '1' (if 'packet mode' 846 * is required) of '0' (standard bit mode). 847 * \return 848 * If zero (_SHR_E_NONE), then no error was encountered. 849 * Otherwise, see shr_error_e 850 * \remark 851 * * If 'packet mode' is required then shaping is done in units of 852 * full packets. 853 * * This procedure is only meaningful for 'egress TM' ports. It is 854 * assumed here that a validity check has been carried out by the 855 * caller. 856 * \see 857 */ 858 shr_error_e dnx_egr_queuing_port_packet_mode_set( 859 int unit, 860 bcm_port_t logical_port, 861 int arg); 862 /* 863 * \brief - 864 * This procedure is called to get 'packet mode' for a logical port 865 * \param [in] unit - 866 * int. HW identifier of unit. 867 * \param [in] logical_port - 868 * bcm_port_t. Identifier of the logical port. 869 * \param [out] arg - 870 * Pointer to int. This procedure loads pointed memory by current value 871 * of 'packet mode'. May be '1' (if 'packet mode' is active) of '0' 872 * (standard bit mode). 873 * \return 874 * If zero (_SHR_E_NONE), then no error was encountered. 875 * Otherwise, see shr_error_e 876 * \remark 877 * * If 'packet mode' is set then shaping is done in units of 878 * full packets. 879 * * This procedure is only meaningful for 'egress TM' ports. It is 880 * assumed here that a validity check has been carried out by the 881 * caller. 882 * \see 883 * * dnx_egr_queuing_port_packet_mode_set 884 */ 885 shr_error_e dnx_egr_queuing_port_packet_mode_get( 886 int unit, 887 bcm_port_t logical_port, 888 int *arg); 889 890 /* 891 * \brief - 892 * This procedure is called, within the sequence of adding a port, to 893 * carry out all initializations required which are related to EGQ. 894 * (This is, then, a step in bcm_dnx_port_add()) 895 * \param [in] unit - 896 * HW identifier of unit. 897 * \return 898 * If zero (_SHR_E_NONE), then no error was encountered. 899 * Otherwise, see shr_error_e 900 * \remark 901 * * None 902 * \see 903 * * port_add_remove_sequence (step "EgqQueuing") 904 * * bcm_dnx_port_add 905 * * bcm_port_add API 906 * * port_add_remove_sequence[] 907 */ 908 shr_error_e dnx_egr_queuing_port_add_handle( 909 int unit); 910 /* 911 * \brief - 912 * This procedure is called, within the sequence of removing a port, to 913 * carry out all 'deinit' operations required which are related to EGQ. 914 * (This is, then, a step in bcm_dnx_port_remove()) 915 * \param [in] unit - 916 * HW identifier of unit. 917 * \return 918 * If zero (_SHR_E_NONE), then no error was encountered. 919 * Otherwise, see shr_error_e 920 * \remark 921 * * None 922 * \see 923 * * port_add_remove_sequence (step "EgqQueuing") 924 * * bcm_dnx_port_remove 925 * * bcm_port_remove API 926 * * port_add_remove_sequence[] 927 */ 928 shr_error_e dnx_egr_queuing_port_remove_handle( 929 int unit); 930 /** 931 * \brief - 932 * Given logical port (corresponding to OTM port), set mode of operation: 933 * SP before WFQ or the other way round. 934 * \param [in] unit - 935 * Int. Identifier of HW platform. 936 * \param [in] logical_port - 937 * bcm_port_t. Logical port identifying the specific base qpair on which rquired 938 * operation is to be done. 939 * \param [in] enable - 940 * uint32. If non-zero then SP is done before WFQ (per OTM port). Otherwise, 941 * WFQ is done before SP. 942 * \return 943 * shr_error_e 944 * \remark 945 * * None 946 * \see 947 * * None 948 */ 949 shr_error_e dnx_egr_queuing_prio_over_cast_set( 950 int unit, 951 bcm_port_t logical_port, 952 int enable); 953 /** 954 * \brief - 955 * Given logical port (corresponding to OTM port), get mode of operation: 956 * SP before WFQ or the other way round. 957 * \param [in] unit - 958 * Int. Identifier of HW platform. 959 * \param [in] logical_port - 960 * bcm_port_t. Logical port identifying the specific base qpair on which rquired 961 * operation is to be done. 962 * \param [in] enable_p - 963 * Pointer to uint32. This procedure loads pointed memory by a non-zero value if 964 * SP is done before WFQ (per OTM port). Otherwise, a zero value is loaded. 965 * \return 966 * shr_error_e 967 * \remark 968 * * None 969 * \see 970 * * None 971 */ 972 shr_error_e dnx_egr_queuing_prio_over_cast_get( 973 int unit, 974 bcm_port_t logical_port, 975 int *enable_p); 976 /* 977 * \brief - 978 * enable/disable port qpairs. Flush option is available for disable mode only. 979 * \param [in] unit - 980 * Int. Identifier of HW platform. 981 * \param [in] logical_port - 982 * bcm_port_t. Logical port identifying the specific base qpair on which rquired 983 * operations are to be done. 984 * \param [in] enable - 985 * uint32. Flag. 986 * If TRUE then set CGM HW to NOT return a 'disable' indication 987 * on this 'base qpair' and all its corresponding 'priority' qpairs. 988 * Else 989 * A 'disable' indication will be returned for all specified qpairs. 990 * Also, if 'enable' is FALSE then see 'flush' below. 991 * \param [in] flush - 992 * uint32. Flag. Only meaningful if 'enable' is FALSE. So, if 'enable'/'flush' 993 * are set to FALSE/TRUE then the following is carried out: 994 * * Temporarily diconnect port 995 * * * Disable port shapers. 996 * * * Set egress port to ignore flow control. 997 * * Flush: Make sure that the otm port has no unicast packet left. 998 * * Flush: Make sure that the otm port has no multicast packet left. 999 * * Connect port 1000 * * * Set egress port to not ignore flow control 1001 * * * Enable port shapers. 1002 * \return 1003 * \retval Zero - On success 1004 * \retval Error - Identifier as per shr_error_e 1005 * \remark 1006 * * Note that it is assumed that, on entry, flow control is active and port 1007 * shapers are active! 1008 * * In case of internal failure, flow control and port shaper are returned back to 1009 * active state. 1010 * \see 1011 * * dnx_egr_queuing_port_fc_enable_set 1012 * * dnx_egr_queuing_port_disable 1013 */ 1014 shr_error_e dnx_egr_queuing_port_enable_and_flush_set( 1015 int unit, 1016 bcm_port_t logical_port, 1017 uint32 enable, 1018 uint32 flush); 1019 /** 1020 * \brief - get the port qpairs enable status. 1021 * 1022 * \param [in] unit - Unit-ID 1023 * \param [in] port - port 1024 * \param [out] enable - enable status 1025 * 1026 * \return 1027 * shr_error_e 1028 * \remark 1029 * * None 1030 * \see 1031 * * None 1032 */ 1033 shr_error_e dnx_egr_queuing_port_enable_get( 1034 int unit, 1035 bcm_port_t port, 1036 uint32 *enable); 1037 /** 1038 * \brief - configure egq pqp counter parameters. 1039 * 1040 * \param [in] unit - Unit-ID 1041 * \param [in] core - Core-ID 1042 * \param [in] count_by - indicate count by qp, hr or egq if 1043 * \param [in] count_place - could be qp, hr_id or egq_if, which is decided by count_by. 1044 * 1045 * \return 1046 * shr_error_e 1047 * \remark 1048 * * None 1049 * \see 1050 * * None 1051 */ 1052 shr_error_e dnx_egr_queuing_pqp_counter_configuration_set( 1053 int unit, 1054 int core, 1055 int count_by, 1056 int count_place); 1057 /** 1058 * \brief - configure egq rqp counter parameters. 1059 * 1060 * \param [in] unit - Unit-ID 1061 * \param [in] core - Core-ID 1062 * \param [in] flag - Flag 1063 * \param [in] count_by - indicate count by qp, hr or egq if 1064 * \param [in] count_place - could be qp, hr_id or egq_if, which is decided by count_by. 1065 * 1066 * \return 1067 * shr_error_e 1068 * \remark 1069 * * None 1070 * \see 1071 * * None 1072 */ 1073 shr_error_e dnx_egr_queuing_epni_counter_configuration_set( 1074 int unit, 1075 int core, 1076 int flag, 1077 int count_by, 1078 int count_place); 1079 1080 /** 1081 * \brief - disable egress queue port and flush it to make sure that the queue is empty 1082 * 1083 * \param [in] unit - Unit-ID 1084 * 1085 * \return 1086 * shr_error_e 1087 * \remark 1088 * * Called from port_remove sequence 1089 * \see 1090 * * None 1091 */ 1092 shr_error_e dnx_egr_queuing_port_disable( 1093 int unit); 1094 /** 1095 * \brief - egr_queuing module init 1096 * 1097 * \param [in] unit - Unit-ID 1098 * 1099 * \return 1100 * shr_error_e 1101 * \remark 1102 * * None 1103 * \see 1104 * * None 1105 */ 1106 shr_error_e dnx_egr_queuing_init( 1107 int unit); 1108 /** 1109 * \brief - egr_queuing module deinit 1110 * 1111 * \param [in] unit - Unit-ID 1112 * 1113 * \return 1114 * shr_error_e 1115 * \remark 1116 * * None 1117 * \see 1118 * * None 1119 */ 1120 shr_error_e dnx_egr_queuing_deinit( 1121 int unit); 1122 /** 1123 * \brief - allocate egress interface 1124 * 1125 * \param [in] unit - Unit ID 1126 * \param [in] port - logical port 1127 * \param [in] master_logical_port - master port in case channelized or DNX_ALGO_PORT_INVALID otherwise 1128 * \param [in] core - core ID 1129 * \param [in] interface_type - interface type of port 1130 * \param [in] channelized_if - if true, allocate from the pool of channelized interfaces. 1131 * \param [out] egr_if - egress interface ID 1132 * 1133 * \return 1134 * shr_error_e 1135 * \remark 1136 * * None 1137 * \see 1138 * * None 1139 */ 1140 shr_error_e dnx_egr_queuing_interface_alloc( 1141 int unit, 1142 bcm_port_t port, 1143 int master_logical_port, 1144 bcm_core_t core, 1145 bcm_port_if_t interface_type, 1146 int channelized_if, 1147 int *egr_if); 1148 /* 1149 * \brief - 1150 * Sets egress queue priority per traffic class and drop 1151 * precedence. 1152 * \param [in] unit - 1153 * HW Identifier of the device to access. 1154 * \param [in] core - 1155 * Core to use when accessing HW. 1156 * \param [in] map_type_ndx - 1157 * dnx_egr_q_prio_mapping_type_e. Mapping type, defining what traffic type 1158 * (unicast/multicast) is mapped to what egress queue type 1159 * (scheduled/unscheduled). 1160 * May be: 1161 * DNX_EGR_UCAST_TO_SCHED 1162 * DNX_EGR_MCAST_TO_UNSCHED 1163 * \param [in] tc_ndx - 1164 * uint32. Traffic Class, as embedded in the packet header. Range: 1165 * 0 - 7. 1166 * \param [in] tc_ndx - 1167 * uint32. Drop Precedence, as embedded in the packet header. 1168 * Range: 0 - 3. 1169 * \param [in] map_profile_ndx - 1170 * uint32. Identifier of the profile to store in HW. Range: 0 - 3. 1171 * \param [in] priority - 1172 * Pointer to dnx_egr_q_priority_t. TC and DP to select for selected 1173 * egress queue. 1174 * \return 1175 * If zero (_SHR_E_NONE), then no error was encountered. 1176 * Otherwise, see shr_error_e 1177 * \remark 1178 * * Each OFP is mapped to an egress queue profile by the 1179 * dnx_egr_q_profile_map_set API. 1180 * * Indirect output is into HW, table PQP_TC_DP_MAP 1181 * \see 1182 * * dnx_egq_tc_dp_map_tbl_set 1183 */ 1184 shr_error_e dnx_egr_queuing_prio_set( 1185 int unit, 1186 int core, 1187 dnx_egr_q_prio_mapping_type_e map_type_ndx, 1188 uint32 tc_ndx, 1189 uint32 dp_ndx, 1190 uint32 map_profile_ndx, 1191 dnx_egr_q_priority_t * priority); 1192 /********************************************************************* 1193 * Gets the configuration set by the 1194 * "dnx_egr_q_prio_set" API. 1195 * Refer to "dnx_egr_q_prio_set" API for details. 1196 */ 1197 shr_error_e dnx_egr_queuing_prio_get( 1198 int unit, 1199 int core, 1200 dnx_egr_q_prio_mapping_type_e map_type_ndx, 1201 uint32 tc_ndx, 1202 uint32 dp_ndx, 1203 uint32 map_profile_ndx, 1204 dnx_egr_q_priority_t * priority); 1205 /* 1206 * \brief - 1207 * Given a TM port, set its TC_MAP profile. 1208 * \param [in] unit - 1209 * HW Identifier of the device to access. 1210 * \param [in] core_id - 1211 * Core to use when accessing HW. 1212 * \param [in] tm_port - 1213 * uint32. The port to set the profile for. 1214 * \param [in] map_profile_id - 1215 * uint32. Traffic Class map profile. Range: 1216 * 0 - 7. 1217 * \return 1218 * If zero (_SHR_E_NONE), then no error was encountered. 1219 * Otherwise, see shr_error_e 1220 * \remark 1221 * * None 1222 * \see 1223 * * dnx_cosq_gport_egress_queue_map_set 1224 */ 1225 shr_error_e dnx_egr_queuing_profile_map_set( 1226 int unit, 1227 int core_id, 1228 uint32 tm_port, 1229 uint32 map_profile_id); 1230 /********************************************************************* 1231 * Gets the configuration set by the 1232 * "dnx_egr_q_profile_map_set" API. 1233 * Refer to "dnx_egr_q_profile_map_set" API for 1234 * details. 1235 */ 1236 int dnx_egr_queuing_profile_map_get( 1237 int unit, 1238 int core_id, 1239 uint32 pp_port, 1240 uint32 *map_profile_id); 1241 /* 1242 * \brief - 1243 * Given a TM port, set its Priority mode (Essentially number of 1244 * priorities: One of 1,2,4,8) 1245 * \param [in] unit - 1246 * HW Identifier of the device to access. 1247 * \param [in] core_id - 1248 * Core to use when accessing HW. 1249 * \param [in] logical_port - 1250 * bcm_port_t. Logical port index to configure. 1251 * \param [in] priority_mode - 1252 * dnx_egr_port_priority_mode_e. Priority mode to 1253 * assign to this port 1254 * \return 1255 * If zero (_SHR_E_NONE), then no error was encountered. 1256 * Otherwise, see shr_error_e 1257 * \remark 1258 * * None 1259 * \see 1260 * * dnx_cosq_gport_egress_queue_map_set 1261 */ 1262 int dnx_egr_queuing_port_prio_mode_set( 1263 int unit, 1264 int core_id, 1265 bcm_port_t logical_port, 1266 dnx_egr_port_priority_mode_e priority_mode); 1267 /********************************************************************* 1268 * is_high_priority indicates if port is high or low priority 1269 */ 1270 /* 1271 * \brief - 1272 * Given 'logical_port' and 'priority' (cosq) on this port, indicate 1273 * whether this qpair combination is marked as 'high priority' on attached NIF. 1274 * \param [in] unit - 1275 * HW Identifier of the device to access. 1276 * \param [in] core - 1277 * Core to use when accessing HW. 1278 * \param [in] logical_port - 1279 * Logical port to identify the corresponding 'base qpair' and, 1280 * consequently, the qpair to investigate. 1281 * \param [in] cosq - 1282 * uint32. Priority to use, together with 'base qpair' to indicate 1283 * the qpair to investigate. 1284 * \param [out] is_high_priority - 1285 * Pointer to int. This procedure loads pointed memory by indication 1286 * on whether 'logical_port', on this 'priority', is marked as SP (TRUE) 1287 * or not (FALSE). 1288 * \return 1289 * If zero (_SHR_E_NONE), then no error was encountered. 1290 * Otherwise, see shr_error_e 1291 * \remark 1292 * * None 1293 * \see 1294 * * dnx_cosq_gport_egress_scheduler_queue_sched_get 1295 * * dnx_cosq_control_egress_port_tc_get 1296 */ 1297 shr_error_e dnx_egr_queuing_is_high_priority_queue_get( 1298 int unit, 1299 int core, 1300 bcm_port_t logical_port, 1301 uint32 cosq, 1302 int *is_high_priority); 1303 /** 1304 * \brief 1305 * Schedule mode for Channelized NIF port and CPU interface. 1306 * Set value of Strict priority to be used by this system. SP range: H/L 1307 * Given 'gport' to identify a specific base qpair, set it priority 1308 * as specified in 'mode' (high or low). 1309 * \param [in] unit - 1310 * HW Unit-ID 1311 * \param [in] gport - 1312 * bcm_gport_t. Gport used to identify the target 'base qpair'. Together with 1313 * 'cosq' the exact target qpair can be identified ('target qpair' = 'base qpair' plus 1314 * 'priority') 1315 * \param [in] cosq - 1316 * bcm_cos_queue_t. Must be zero. (All priorities are set) 1317 * \param [in] mode - 1318 * int. Priority to assign to interface corresponding to indicated qpair. Can only 1319 * be high (BCM_COSQ_SP0) or low (BCM_COSQ_SP1). 1320 * See dnx_egq_dbal_gport_scheduler_queue_sched_set(). 1321 * \param [out] weight - 1322 * int. Ignored by this procedure. 1323 * \return 1324 * If zero (_SHR_E_NONE), then no error was encountered. 1325 * Otherwise, see shr_error_e 1326 * \remark 1327 * * Accessing HW table EPS_QP_CFG, field QP_IS_HP 1328 * * Accessing DBAL table DBAL_TABLE_EGQ_QPAIR_ATTRIBUTES, field DBAL_FIELD_QP_IS_HP 1329 * \see 1330 * * dnx_cosq_gport_egress_scheduler_port_sched_get 1331 * * dnx_cosq_gport_egress_scheduler_queue_sched_set 1332 */ 1333 shr_error_e dnx_egr_queuing_port_is_high_set( 1334 int unit, 1335 bcm_gport_t gport, 1336 bcm_cos_queue_t cosq, 1337 int mode, 1338 int weight); 1339 /* 1340 * Purpose: 1341 * Schedule mode for Channelized NIF port and CPU interface. 1342 * Choose Strict priority to Connect to. SP range: H/L 1343 */ 1344 /** 1345 * \brief 1346 * Schedule mode for Channelized NIF port and CPU interface. 1347 * Get value of Strict priority to be used by this system. SP range: H/L 1348 * Given 'gport' to identify a specific base qpair, Get its priority 1349 * into 'mode' (high or low). 1350 * \param [in] unit - 1351 * HW Unit-ID 1352 * \param [in] gport - 1353 * bcm_gport_t. Gport used to identify the target 'base qpair'. Together with 1354 * 'cosq' the exact target qpair can be identified ('target qpair' = 'base qpair' plus 1355 * 'priority') 1356 * \param [in] cosq - 1357 * bcm_cos_queue_t. Must be zero. (All priorities are set) 1358 * \param [out] mode - 1359 * Pointer to int. This procedure loads pointed memory by priority assigned to 1360 * interface corresponding to indicated qpair. Can only be high (BCM_COSQ_SP0) 1361 * or low (BCM_COSQ_SP1). 1362 * See dnx_egq_dbal_gport_scheduler_queue_sched_set(). 1363 * \param [out] weight - 1364 * Pointer to int. Ignored by this procedure. 1365 * \return 1366 * If zero (_SHR_E_NONE), then no error was encountered. 1367 * Otherwise, see shr_error_e 1368 * \remark 1369 * * Accessing HW table EPS_QP_CFG, field QP_IS_HP 1370 * * Accessing DBAL table DBAL_TABLE_EGQ_QPAIR_ATTRIBUTES, field DBAL_FIELD_QP_IS_HP 1371 * \see 1372 * * dnx_cosq_gport_egress_scheduler_port_sched_get 1373 * * dnx_cosq_gport_egress_scheduler_queue_sched_set 1374 */ 1375 shr_error_e dnx_egr_queuing_port_is_high_get( 1376 int unit, 1377 bcm_gport_t gport, 1378 bcm_cos_queue_t cosq, 1379 int *mode, 1380 int *weight); 1381 /* 1382 * \brief - 1383 * Set new profile for egress queue mapping 1384 * Given 'profile' and 'mapping info' load HW with specified new information. 1385 * 'profile' is a sw/hw identifier of the mapping info. 1386 * 'Mapping_info' indicates TC and DP to assign to unicast or multicast 1387 * traffic which enters egress processing with specific TC and DP. 1388 * The mapping is, then, from traffic type (unicast/multicast) plus TC and DP 1389 * to new TC and DP combination. 1390 * \param [in] unit - 1391 * HW Identifier of the device to access. 1392 * \param [in] core - 1393 * Core to use when accessing HW. 1394 * \param [in] profile - 1395 * int. Identifier of profile (in SW data base) with indicated mapping details. range: 1396 * 4 bits. 1397 * \param [in] mapping_info - 1398 * dnx_cosq_egress_queue_mapping_info_t. Structure fully loaded by info indicating 1399 * all mapping combinations as explained above. 1400 * All entries of the three dimensional array are assumed to have been loaded 1401 * by the caller. 1402 * \return 1403 * If zero (_SHR_E_NONE), then no error was encountered. 1404 * Otherwise, see shr_error_e 1405 * \remark 1406 * * None 1407 * \see 1408 * * dnx_egr_queuing_prio_set 1409 * * dnx_cosq_egq_gport_egress_queue_map_set 1410 */ 1411 shr_error_e dnx_egr_queuing_profile_mapping_set( 1412 int unit, 1413 int core, 1414 int profile, 1415 const dnx_cosq_egress_queue_mapping_info_t * mapping_info); 1416 1417 /********************************************************************* 1418 * Get calendar id from interface id. 1419 * Calender id is the interface id 1420 * Except ifc ids, which do not part of the channelized pool. 1421 * For them, All goes to last calender 1422 */ 1423 1424 /* 1425 * \brief - 1426 * Get calendar id from interface id. 1427 * Calender id is the interface id 1428 * Except ifc ids, which do not part of the channelized pool. 1429 * For them, All goes to last calender 1430 * \param [in] unit - 1431 * HW Identifier of the device to access. 1432 * \param [in] logical_port - 1433 * logical port 1434 * \param [in] channelized - 1435 * egress interface channelized 1436 * \param [out] calendar_id - 1437 * calendar id calculated by the function 1438 * \return 1439 * If zero (_SHR_E_NONE), then no error was encountered. 1440 * Otherwise, see shr_error_e 1441 * \remark 1442 * * None 1443 */ 1444 shr_error_e dnx_egr_queuing_calendar_index_get( 1445 int unit, 1446 bcm_port_t logical_port, 1447 int *calendar_id); 1448 1449 /** 1450 * \brief - update total credit size for all interfaces, and verify we do not cross the capacity of ESB buffer size 1451 * 1452 * \param [in] unit - Unit-ID 1453 * \param [in] logical_port - logical port 1454 * \param [in] speed - new speed 1455 * 1456 * \return 1457 * shr_error_e 1458 * \remark 1459 * * None 1460 * \see 1461 * * None 1462 */ 1463 shr_error_e dnx_egr_queuing_total_egr_if_credits_update( 1464 int unit, 1465 bcm_port_t logical_port, 1466 int speed); 1467 1468 /** 1469 * \brief - 1470 * Given rate, in Mega Bits Per Second, find the number of blocks of 1471 * 12.5G that are required to contain it and, then, find the lowest power 1472 * of '2' which contain this number. See 'remark' below. 1473 * 1474 * \param [in] unit - 1475 * HW Unit-ID 1476 * \param [in] rate - 1477 * Pointer to 'uint32'. Rate, in Mega Bits Per Second, to convert as per 1478 * 'brief' above. See 'remark' below . 1479 * \param [out] weight_p - 1480 * Pointer to uint32. This procedure loads pointed memory as described in 1481 * 'brief' above. If 'rate' is '0' then '0' is loaded. 1482 * \return 1483 * If zero (_SHR_E_NONE), then no error was encountered. 1484 * Otherwise, see shr_error_e 1485 * \remark 1486 * * Examples: 1487 * rate is '1'. The number of blocks is '1' and the calculated 1488 * weight is '1'. 1489 * rate is '12,500'. The number of blocks is '1' and the calculated 1490 * weight is '1'. 1491 * rate is '12,501'. The number of blocks is '2' and the calculated 1492 * weight is '2'. 1493 * rate is '25,001'. The number of blocks is '3' and the calculated 1494 * weight is '4'. 1495 * \see 1496 * * dnx_egr_q_nif_cal_set 1497 */ 1498 int dnx_egr_queuing_nif_rate_to_weight( 1499 int unit, 1500 uint32 rate, 1501 uint32 *weight_p); 1502 1503 /** 1504 * \brief 1505 * Calculate the parameters for building a MUX calendar. 1506 * 1507 * \param [in] unit - unit id 1508 * \param [in] weights - array of weights for each object in the calendar. 1509 * \param [in] max_cal_len - maximal possible calendar length 1510 * \param [out] cal_len_optimal - optimal calendar length 1511 * \param [out] nof_cal_objects - nof objects in calendar 1512 * \param [out] dummy_start - the point where actual entries end and padding begins 1513 * 1514 * \return 1515 * shr_error_e - Error Type 1516 * \remark 1517 * 1518 * \see 1519 * * None 1520 */ 1521 shr_error_e dnx_egr_queuing_cal_params_calc( 1522 int unit, 1523 uint32 *weights, 1524 uint32 max_cal_len, 1525 uint32 *cal_len_optimal, 1526 uint32 *nof_cal_objects, 1527 uint32 *dummy_start); 1528 1529 /** 1530 * \brief 1531 * convert HW egress interface type to bcm interface type. 1532 * Any HW interface that does not belong to one of the special interfaces, will be threated as NIF_ETH 1533 * 1534 * \param [in] unit - unit id 1535 * \param [in] hw_egr_if - hw egress interface, as defined in dnx_data_egr_queuing.params. 1536 * \param [out] bcm_egr_if - the converted value, as defined in bcm layer. 1537 * 1538 * \return 1539 * shr_error_e - Error Type 1540 * \remark 1541 * 1542 * \see 1543 * * None 1544 */ 1545 shr_error_e dnx_egr_queuing_hw_egr_if_convert( 1546 int unit, 1547 int hw_egr_if, 1548 bcm_port_if_t * bcm_egr_if); 1549 1550 /** 1551 * \brief - 1552 * Enable/disable interface shaper correlated with specified port. 1553 * \param [in] unit - 1554 * Int. Identifier of HW platform. 1555 * \param [in] logical_port - 1556 * bcm_port_t. Logical port identifying the specific base qpair on which rquired 1557 * operations are to be done. 1558 * \param [in] enable - 1559 * uint32. Flag. If TRUE then enable interface shaper. Else, disable. 1560 * \return 1561 * \retval Zero - On success 1562 * \retval Error - Identifier as per shr_error_e 1563 * \remark 1564 * * Operation is carried out only if general flag, indicating whether 1565 * all inreface shapers are enabled (in HW), is asserted. 1566 * * Specific interface is controlled via HW register 1567 * EPS_EGRESS_CALENDAR_SHAPER_SETTINGS (field IFC_SPR_DIS) 1568 * \see 1569 * * dnx_egr_queuing_port_all_shapers_enable_set 1570 * * dnx_algo_port_egr_if_get 1571 */ 1572 shr_error_e dnx_egr_queuing_interface_shaper_enable_set( 1573 int unit, 1574 bcm_port_t logical_port, 1575 uint32 enable); 1576 1577 /* } */ 1578 1579 /** } */ 1580 #endif /* EGR_QUEUING_H_INCLUDED */