egq_dbal.h (18805B)
1 /** 2 * \file bcm_int/dnx/cosq/egress/egq_dbal.h 3 * 4 * 5 * Mainly prototypes of low level DBAL access procedures, for EGQ on DNX. \n 6 */ 7 8 /* 9 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 10 * 11 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 12 */ 13 14 #ifndef EGQ_DBAL_H_INCLUDED 15 /* { */ 16 #define EGQ_DBAL_H_INCLUDED 17 18 #ifndef BCM_DNX_SUPPORT 19 #error "This file is for use by DNX family only!" 20 #endif 21 22 /* 23 * Defines: 24 * { 25 */ 26 /* 27 * } 28 */ 29 /* 30 * Typedefs: 31 * { 32 */ 33 /* 34 * } 35 */ 36 /* 37 * Functions 38 * { 39 */ 40 /** 41 * \brief - sets tcg cir sp. configuration per core 42 * 43 * \param [in] unit - 44 * Unit-ID 45 * \param [in] gport - 46 * If 'gport' is non zero then core is extracted from it. Otherwise, 47 * all cores are loaded with the input 'enable' value. 48 * \param [in] enable - enable 49 * 50 * \return 51 * If zero (_SHR_E_NONE), then no error was encountered. 52 * Otherwise, see shr_error_e 53 * \remark 54 * * If 'enable' is asserted then HW chooses CIR according to SP to 55 * lower TCG, otherwise do RR between all TCGs 56 * \see 57 * * None 58 */ 59 shr_error_e dnx_egq_dbal_tcg_cir_sp_en_set( 60 int unit, 61 bcm_gport_t gport, 62 uint32 enable); 63 /** 64 * \brief - gets tcg cir sp. configuration per core 65 * 66 * \param [in] unit - 67 * Unit-ID 68 * \param [in] gport - 69 * If 'gport' is non zero then core is extracted from it. Otherwise, 70 * core '0' is used to retrieve output into *enable_p. 71 * \param [out] enable_p - 72 * This procedure loads pointed memory by 'enable' flag as written in HW. 73 * 74 * \return 75 * If zero (_SHR_E_NONE), then no error was encountered. 76 * Otherwise, see shr_error_e 77 * \remark 78 * * If 'enable' is asserted (This procedure loads it by a non-zero value) then 79 * HW chooses CIR according to SP to lower TCG, otherwise do RR between all TCGs 80 * \see 81 * * None 82 */ 83 shr_error_e dnx_egq_dbal_tcg_cir_sp_en_get( 84 int unit, 85 bcm_gport_t gport, 86 uint32 *enable_p); 87 /** 88 * \brief - configures egress multicast replication fifo parameters received from dnx data to HW 89 * 90 * \param [in] unit - Unit-ID 91 * \param [in] core - core-id 92 * \param [in] tdm_exist - indicates if there is tdm traffic in the system 93 * * 94 * \return 95 * If zero (_SHR_E_NONE), then no error was encountered. 96 * Otherwise, see shr_error_e 97 * \remark 98 * * None 99 * \see 100 * * None 101 */ 102 shr_error_e dnx_egq_dbal_emr_fifo_default_set( 103 int unit, 104 int core, 105 uint32 tdm_exist); 106 /** 107 * \brief - Set the flow control mapping CMIC to EGQ 108 * 109 * \param [in] unit - Unit-ID 110 * \param [in] core - Core ID 111 * \param [in] cpu_cos - CPU_COS which is channel number + cosq 112 * \param [in] qpair - Q-pair to be mapped to the corresponding CPU_COS 113 * 114 * \return 115 * If zero (_SHR_E_NONE), then no error was encountered. 116 * Otherwise, see shr_error_e 117 * \remark 118 * * None 119 * \see 120 * * None 121 */ 122 shr_error_e dnx_egq_dbal_cmic_egq_map_set( 123 int unit, 124 bcm_core_t core, 125 int cpu_cos, 126 int qpair); 127 /********************************************************************* 128 * Enable/disable the egress shaping. 129 */ 130 /** 131 * \brief - 132 * Set HW to enable or disable all the following shapers (on all cores): 133 * OTM_SPR_ENA, 134 * QPAIR_SPR_ENA, 135 * TCG_SPR_ENA, 136 * \param [in] unit - 137 * Unit HW ID 138 * \param [in] enable - 139 * Value to load into HW. '1' indicates 'enable' 140 * \return 141 * If zero (_SHR_E_NONE), then no error was encountered. 142 * Otherwise, see shr_error_e 143 * \remark 144 * * None 145 * \see 146 * * None 147 */ 148 shr_error_e dnx_egq_dbal_shaping_enable_set( 149 int unit, 150 uint8 enable); 151 /** 152 * \brief - 153 * Get, from HW, the flag indicating whether to to enable or disable all 154 * the following shapers (on all cores): 155 * OTM_SPR_ENA, 156 * QPAIR_SPR_ENA, 157 * TCG_SPR_ENA, 158 * Actually, only OTM_SPR_ENA is read since they are all loaded by 159 * the same value. 160 * \param [in] unit - 161 * Unit HW ID 162 * \param [out] enable_p - 163 * Pointer to uint8. This procedure loads pointed memory by the value of 164 * the OTM_SPR_ENA flag. A value of '1' indicates 'enable' 165 * \return 166 * If zero (_SHR_E_NONE), then no error was encountered. 167 * Otherwise, see shr_error_e 168 * \remark 169 * * None 170 * \see 171 * * None 172 */ 173 shr_error_e dnx_egq_dbal_shaping_enable_get( 174 int unit, 175 uint8 *enable_p); 176 /** 177 * \brief - get egq rqp counter information . 178 * 179 * \param [in] unit - Unit-ID 180 * \param [in] core - Core-ID 181 * \param [out] counter_info - store counter information 182 * \param [out] nof_counter - return number of counters 183 * 184 * \return 185 * shr_error_e 186 * \remark 187 * * None 188 * \see 189 * * None 190 */ 191 shr_error_e dnx_egq_dbal_rqp_counter_info_get( 192 int unit, 193 int core, 194 dnx_egq_counter_info_t * counter_info, 195 int *nof_counter); 196 /** 197 * \brief - clear egq pqp counter . 198 * 199 * \param [in] unit - Unit-ID 200 * \param [in] core - Core-ID 201 * 202 * \return 203 * shr_error_e 204 * \remark 205 * * None 206 * \see 207 * * None 208 */ 209 shr_error_e dnx_egq_dbal_pqp_counter_configuration_reset( 210 int unit, 211 int core); 212 /** 213 * \brief - get egq pqp counter information . 214 * 215 * \param [in] unit - Unit-ID 216 * \param [in] core - Core-ID 217 * \param [out] counter_info - store counter information 218 * 219 * \return 220 * shr_error_e 221 * \remark 222 * * None 223 * \see 224 * * None 225 */ 226 shr_error_e dnx_egq_dbal_pqp_counter_info_get( 227 int unit, 228 int core, 229 dnx_egq_counter_info_t * counter_info); 230 /** 231 * \brief - clear egq epni counter . 232 * 233 * \param [in] unit - Unit-ID 234 * \param [in] core - Core-ID 235 * 236 * \return 237 * shr_error_e 238 * \remark 239 * * None 240 * \see 241 * * None 242 */ 243 shr_error_e dnx_egq_dbal_epni_counter_configuration_reset( 244 int unit, 245 int core); 246 /** 247 * \brief - get egq epni counter information . 248 * 249 * \param [in] unit - Unit-ID 250 * \param [in] core - Core-ID 251 * \param [in] flag - flag 252 * \param [out] counter_info - store counter information 253 * \param [out] nof_counter - return number of counters 254 * 255 * \return 256 * shr_error_e 257 * \remark 258 * * None 259 * \see 260 * * None 261 */ 262 shr_error_e dnx_egq_dbal_epni_counter_info_get( 263 int unit, 264 int core, 265 int flag, 266 dnx_egq_counter_info_t * counter_info, 267 int *nof_counter); 268 /** 269 * \brief 270 * Get data from HW. Given qpair, as key, get WFQ-related weigths corresponding 271 * to unicast and to multicast traffic. 272 * \param [in] unit - 273 * HW Unit-ID 274 * \param [in] core - 275 * Core to use for HW access. 276 * \param [in] entry_offset - 277 * Qpair for which information is to be retrieved. Range is 0 - 511 278 * (DNX_EGR_NOF_Q_PAIRS) 279 * \param [out] egq_dwm_tbl_data_p - 280 * Pointer to dnx_egq_dwm_tbl_data_t. This procedure loads 281 * egq_dwm_tbl_data_p->mc_or_mc_low_queue_weight, 282 * egq_dwm_tbl_data_p->uc_or_uc_low_queue_weight (each assumed to be uint32!) from HW table 283 * at location corresponding to specified 'entry_offset' (qpair). 284 * Both parameters are 8 bits in size and indicate the relative weight for uc/mc 285 * traffic associated with this qpair. 286 * Weight of 0 for one queue indicates that it has SP (strict priority) over the other. 287 * When both have equal weights, this implies simple RR (round robin). Maximum weight 288 * difference is 255:1 289 * \return 290 * If zero (_SHR_E_NONE), then no error was encountered. 291 * Otherwise, see shr_error_e 292 * \remark 293 * * Accessing HW table EPS_DWM, fields UC_OR_UC_LOW_QUEUE_WEIGHT, MC_OR_MC_LOW_QUEUE_WEIGHT 294 * * Accessing DBAL table DBAL_TABLE_EGQ_QPAIR_ATTRIBUTES, fields MC_OR_MC_LOW_QUEUE_WEIGHT, 295 * UC_OR_UC_LOW_QUEUE_WEIGHT using 'entry_offset' and 'core' as key. 296 * \see 297 * * None 298 */ 299 shr_error_e dnx_egq_dbal_weights_tbl_get( 300 int unit, 301 int core, 302 uint32 entry_offset, 303 dnx_egq_dwm_tbl_data_t * egq_dwm_tbl_data_p); 304 /** 305 * \brief 306 * Write data into HW. Given qpair, as key, set WFQ-related weigths corresponding 307 * to unicast and to multicast traffic. 308 * \param [in] unit - 309 * HW Unit-ID 310 * \param [in] core - 311 * Core to use for HW access. 312 * \param [in] entry_offset - 313 * Qpair for which information is to be set. Range is 0 - 511 314 * (DNX_EGR_NOF_Q_PAIRS) 315 * \param [in] egq_dwm_tbl_data_p - 316 * Pointer to dnx_egq_dwm_tbl_data_t. This procedure loads 317 * egq_dwm_tbl_data_p->mc_or_mc_low_queue_weight, 318 * egq_dwm_tbl_data_p->uc_or_uc_low_queue_weight (each assumed to be uint32!) into HW table 319 * at location corresponding to specified 'entry_offset' (qpair). 320 * Both parameters are 8 bits in size and indicate the relative weight for uc/mc 321 * traffic associated with this qpair. 322 * Weight of 0 for one queue indicates that it has SP (strict priority) over the other. 323 * When both have equal weights, this implies simple RR (round robin). Maximum weight 324 * difference is 255:1 325 * \return 326 * If zero (_SHR_E_NONE), then no error was encountered. 327 * Otherwise, see shr_error_e 328 * \remark 329 * * Accessing HW table EPS_DWM, fields UC_OR_UC_LOW_QUEUE_WEIGHT, MC_OR_MC_LOW_QUEUE_WEIGHT 330 * * Accessing DBAL table DBAL_TABLE_EGQ_QPAIR_ATTRIBUTES, fields MC_OR_MC_LOW_QUEUE_WEIGHT, 331 * UC_OR_UC_LOW_QUEUE_WEIGHT using 'entry_offset' and 'core' as key. 332 * \see 333 * * None 334 */ 335 shr_error_e dnx_egq_dbal_weights_tbl_set( 336 int unit, 337 int core, 338 uint32 entry_offset, 339 dnx_egq_dwm_tbl_data_t * egq_dwm_tbl_data_p); 340 /** 341 * \brief 342 * Get data from HW. Given TC, DP, MC flag, and profile, all 343 * used, together, as key, get TC and DP for traffic corresponding to 344 * this profile. 345 * \param [in] unit - 346 * HW Unit-ID 347 * \param [in] core_id - 348 * Core to use for HW access. 349 * \param [in] entry - 350 * Pointer to dnx_egq_tc_dp_map_tbl_entry_t. Input key to table of profiles: 351 * map_profile (4b) 352 * is_egr_mc (1b) 353 * tc (3b) 354 * dp (2b) 355 * \param [out] tbl_data - 356 * Pointer to dnx_egq_tc_dp_map_tbl_data_t. This procedure loads 357 * tbl_data->tc, tbl_data->dp (each assumed to be uint32!) from HW table 358 * at location corresponding to specified 'entry'. TC is 3 bits. DP is 2 bits. 359 * \return 360 * If zero (_SHR_E_NONE), then no error was encountered. 361 * Otherwise, see shr_error_e 362 * \remark 363 * * Accessing HW table PQP_TC_DP_MAP, fields EGRESS_TC, CGM_MC_DP 364 * * Accessing DBAL table EGQ_TC_DP_MAP, fields EGRESS_TC, CGM_MC_DP 365 * using 'entry' and 'core_id' as key. 366 * \see 367 * * None 368 */ 369 int dnx_egq_dbal_tc_dp_map_tbl_get( 370 int unit, 371 int core_id, 372 dnx_egq_tc_dp_map_tbl_entry_t * entry, 373 dnx_egq_tc_dp_map_tbl_data_t * tbl_data); 374 /** 375 * \brief 376 * Load data into HW. Given TC, DP, MC flag, and profile, all 377 * used, together, as key, set TC and DP for traffic corresponding to 378 * this profile. 379 * \param [in] unit - 380 * HW Unit-ID 381 * \param [in] core_id - 382 * Core to use for HW access. 383 * \param [in] entry - 384 * Pointer to dnx_egq_tc_dp_map_tbl_entry_t. Input key to table of profiles: 385 * map_profile (4b) 386 * is_egr_mc (1b) 387 * tc (3b) 388 * dp (2b) 389 * \param [in] tbl_data - 390 * Pointer to dnx_egq_tc_dp_map_tbl_data_t. This procedure loads 391 * tbl_data->tc, tbl_data->dp (each assumed to be uint32!) into HW table 392 * at location corresponding to specified 'entry'. TC is 3 bits. DP is 2 bits. 393 * \return 394 * If zero (_SHR_E_NONE), then no error was encountered. 395 * Otherwise, see shr_error_e 396 * \remark 397 * * Accessing HW table PQP_TC_DP_MAP, fields EGRESS_TC, CGM_MC_DP 398 * * Accessing DBAL table EGQ_TC_DP_MAP, fields EGRESS_TC, CGM_MC_DP 399 * using 'entry' and 'core_id' as key. 400 * \see 401 * * None 402 */ 403 int dnx_egq_dbal_tc_dp_map_tbl_set( 404 int unit, 405 int core_id, 406 dnx_egq_tc_dp_map_tbl_entry_t * entry, 407 dnx_egq_tc_dp_map_tbl_data_t * tbl_data); 408 /** 409 * \brief 410 * Extract data from HW. Given PP port, get its assigned profile (which 411 * determines the TC for traffic on this port). 412 * \param [in] unit - 413 * HW Unit-ID 414 * \param [in] core_id - 415 * Core to retrieve info for. 416 * \param [in] internal_port - 417 * uint32. PP port for which to get required info. Range: 0 - 255 (8 bits) 418 * \param [out] egq_ppct_tbl_data - 419 * Pointer to dnx_egq_ppct_tbl_data_t. This procedure loads 420 * egq_ppct_tbl_data->cos_map_profile (assumed to be uint32!) by profile 421 * value corresponding to specified port. Profile range: 0 - 7 (3 bits) 422 * \return 423 * If zero (_SHR_E_NONE), then no error was encountered. 424 * Otherwise, see shr_error_e 425 * \remark 426 * * Accessing HW table ERPP_PER_PORT_TABLE, field TC_MAP_PROFILE 427 * * Accessing DBAL table EGRESS_PP_PORT, field COS_MAP_PROFILE 428 * using 'internal_port' and 'core_id' as key. 429 * \see 430 * * None 431 */ 432 int dnx_egq_dbal_cos_map_profile_get( 433 int unit, 434 int core_id, 435 uint32 internal_port, 436 dnx_egq_ppct_tbl_data_t * egq_ppct_tbl_data); 437 /** 438 * \brief 439 * Load data into HW. Given PP port, set its assigned profile (which 440 * determines the TC for traffic on this port). 441 * \param [in] unit - 442 * HW Unit-ID 443 * \param [in] core_id - 444 * Core to use for HW access. 445 * \param [in] internal_port - 446 * uint32. PP port for which to set required info. Range: 0 - 255 (8 bits) 447 * \param [out] egq_ppct_tbl_data - 448 * Pointer to dnx_egq_ppct_tbl_data_t. This procedure loads 449 * egq_ppct_tbl_data->cos_map_profile (assumed to be uint32!) into HW 450 * at location corresponding to specified port. Profile range: 0 - 7 (3 bits) 451 * \return 452 * If zero (_SHR_E_NONE), then no error was encountered. 453 * Otherwise, see shr_error_e 454 * \remark 455 * * Accessing HW table ERPP_PER_PORT_TABLE, field TC_MAP_PROFILE 456 * * Accessing DBAL table EGRESS_PP_PORT, field COS_MAP_PROFILE 457 * using 'internal_port' and 'core_id' as key. 458 * \see 459 * * None 460 */ 461 int dnx_egq_dbal_cos_map_profile_set( 462 int unit, 463 int core_id, 464 uint32 internal_port, 465 dnx_egq_ppct_tbl_data_t * egq_ppct_tbl_data); 466 /* 467 * \brief - 468 * Set global maximal burst size for all 'OTM ports' (on ALL cores) which are 469 * in 'empty' state. 470 * \param [in] unit - 471 * HW identifier of unit. 472 * \param [in] arg - 473 * uint32. Value of maximal burst in credits. Note that if a value of '0' is selected 474 * then no maximal limit is set on collection of credits for qpairs which are empty. 475 * Value is limited to a maximal value of DNX_OFP_RATES_BURST_LIMIT_MAX. 476 * \return 477 * If zero (_SHR_E_NONE), then no error was encountered. 478 * Otherwise, see shr_error_e 479 * \remark 480 * * Note that all cores are updated. 481 * \see 482 * * dnx_egq_dbal_empty_port_max_credit_set 483 * * bcm_dnx_cosq_control_set 484 */ 485 shr_error_e dnx_egq_dbal_empty_port_max_credit_set( 486 int unit, 487 int arg); 488 /* 489 * \brief - 490 * Get global maximal burst size for all 'OTM ports' (on ALL cores) which are 491 * in 'empty' state. 492 * \param [in] unit - 493 * HW identifier of unit. 494 * \param [in] arg - 495 * Pointer to uint32. This procedure loads pointed memory by the value of 496 * maximal burst in credits. Note that if a value of '0' is selected 497 * then no maximal limit was set on collection of credits for qpairs which 498 * are empty. 499 * Value is limited to a maximal value of DNX_OFP_RATES_BURST_LIMIT_MAX. 500 * \return 501 * If zero (_SHR_E_NONE), then no error was encountered. 502 * Otherwise, see shr_error_e 503 * \remark 504 * * Note that all cores are updated. 505 * \see 506 * * dnx_egq_dbal_empty_port_max_credit_get 507 * * bcm_dnx_cosq_control_get 508 */ 509 shr_error_e dnx_egq_dbal_empty_port_max_credit_get( 510 int unit, 511 int *arg); 512 /** 513 * \brief 514 * Schedule mode for Channelized NIF port and CPU interface. 515 * Choose Strict priority to Connect to. SP range: H/L 516 * Given 'gport' and priority ('cosq') to identify a specific qpair, 517 * set its priority as specified in 'mode' (high or low). 518 * \param [in] unit - 519 * HW Unit-ID 520 * \param [in] gport - 521 * bcm_gport_t. Gport used to identify the target 'base qpair'. Together with 522 * 'cosq' the exact target qpair can be identified ('target qpair' = 'base qpair' plus 523 * 'priority') 524 * \param [in] cosq - 525 * bcm_cos_queue_t. Priority of target qpair. Can either be in the range from 0 to 526 * 7 or BCM_COSQ_HIGH_PRIORITY or BCM_COSQ_LOW_PRIORITY. See dnx_cosq_bcm_cosq_to_egr_q_prio(). 527 * \param [in] mode - 528 * int. Priority to assign to interface corresponding to indicated qpair. Can only 529 * be high (BCM_COSQ_SP0) or low (BCM_COSQ_SP1). See dnx_egq_dbal_gport_scheduler_queue_sched_set(). 530 * \param [in] weight - 531 * int. Ignored by this procedure. 532 * \return 533 * If zero (_SHR_E_NONE), then no error was encountered. 534 * Otherwise, see shr_error_e 535 * \remark 536 * * Accessing HW table EPS_QP_CFG, field QP_IS_HP 537 * * Accessing DBAL table DBAL_TABLE_EGQ_QPAIR_ATTRIBUTES, field DBAL_FIELD_QP_IS_HP 538 * \see 539 * * dnx_cosq_gport_egress_scheduler_port_sched_set 540 * * dnx_cosq_gport_egress_scheduler_queue_sched_get 541 */ 542 shr_error_e dnx_egq_dbal_gport_scheduler_queue_sched_set( 543 int unit, 544 bcm_gport_t gport, 545 bcm_cos_queue_t cosq, 546 int mode, 547 int weight); 548 549 /** 550 * \brief - set FQP interface profile parameters 551 * 552 * \param [in] unit - Unit-ID 553 * \param [in] core - core 554 * \param [in] profile_id - profile id 555 * \param [in] profile_params - profile parameter structure 556 * 557 * \return 558 * shr_error_e 559 * \remark 560 * * None 561 * \see 562 * * None 563 */ 564 shr_error_e dnx_egq_dbal_fqp_profile_params_set( 565 int unit, 566 int core, 567 int profile_id, 568 dnx_fqp_profile_params_t * profile_params); 569 570 /** 571 * \brief - set FQP interface profile id 572 * 573 * \param [in] unit - Unit-ID 574 * \param [in] core - core 575 * \param [in] egr_if - egress interface 576 * \param [in] profile_id - profile id 577 * 578 * \return 579 * shr_error_e 580 * \remark 581 * * None 582 * \see 583 * * None 584 */ 585 shr_error_e dnx_egq_dbal_fqp_profile_id_set( 586 int unit, 587 int core, 588 int egr_if, 589 int profile_id); 590 591 /** 592 * \brief - get FQP interface profile id 593 * 594 * \param [in] unit - Unit-ID 595 * \param [in] core - core 596 * \param [in] egr_if - egress interface 597 * \param [out] profile_id - profile id 598 * 599 * \return 600 * shr_error_e 601 * \remark 602 * * None 603 * \see 604 * * None 605 */ 606 shr_error_e dnx_egq_dbal_fqp_profile_id_get( 607 int unit, 608 int core, 609 int egr_if, 610 int *profile_id); 611 612 /** 613 * \brief - get FQP interface profile params 614 * 615 * \param [in] unit - Unit-ID 616 * \param [in] core - core 617 * \param [in] egr_if - egress interface 618 * \param [in] profile_id - profile id 619 * \param [out] profile_params - profile parameter strucutre 620 * 621 * \return 622 * shr_error_e 623 * \remark 624 * * None 625 * \see 626 * * None 627 */ 628 shr_error_e dnx_egq_dbal_fqp_profile_params_get( 629 int unit, 630 int core, 631 int egr_if, 632 int profile_id, 633 dnx_fqp_profile_params_t * profile_params); 634 635 /** 636 * \brief - set PQP almost empty thresholds 637 * 638 * \param [in] unit - Unit-ID 639 * 640 * \return 641 * shr_error_e 642 * \remark 643 * * None 644 * \see 645 * * None 646 */ 647 shr_error_e dnx_egq_dbal_pqp_almost_empty_thresholds_set( 648 int unit); 649 /* 650 * } 651 */ 652 /* } */ 653 #endif /* EGQ_DBAL_H_INCLUDED */