port.h (377469B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 7 * 8 */ 9 10 #ifndef __BCM_PORT_H__ 11 #define __BCM_PORT_H__ 12 13 #include <shared/portmode.h> 14 #include <shared/port.h> 15 #include <shared/phyconfig.h> 16 #include <shared/phyreg.h> 17 #include <shared/switch.h> 18 #include <bcm/types.h> 19 #include <bcm/stat.h> 20 #include <shared/port_ability.h> 21 22 #define BCM_PIPES_MAX _SHR_SWITCH_MAX_PIPES 23 24 #define BCM_PORT_WIDE_DATA_WIDTH 57 25 26 #define BCM_PORT_WIDE_DATA_STRENGTH_SET(_data, _strength) \ 27 COMPILER_64_SET(_data,( (_strength ) ? ( COMPILER_64_HI(_data) | (1 << ((BCM_PORT_WIDE_DATA_WIDTH -1) -32))) : (COMPILER_64_HI(_data) & ~( 1 << ((BCM_PORT_WIDE_DATA_WIDTH -1) -32)))) ,COMPILER_64_LO(_data)) 28 29 #define BCM_PORT_WIDE_DATA_STRENGTH_GET(_data) \ 30 (COMPILER_64_HI(_data) >> ((BCM_PORT_WIDE_DATA_WIDTH -1) -32) ) 31 32 /* Port Configuration structure. */ 33 typedef struct bcm_port_config_s { 34 bcm_pbmp_t fe; /* Mask of FE ports. */ 35 bcm_pbmp_t ge; /* Mask of GE ports. */ 36 bcm_pbmp_t xe; /* Mask of 10gig ports. */ 37 bcm_pbmp_t ce; /* Mask of 100gig ports. */ 38 bcm_pbmp_t le; /* Mask of 50gig ports. */ 39 bcm_pbmp_t cc; /* Mask of 200gig ports. */ 40 bcm_pbmp_t cd; /* Mask of 400gig ports. */ 41 bcm_pbmp_t e; /* Mask of eth ports. */ 42 bcm_pbmp_t hg; /* Mask of HiGig ports. */ 43 bcm_pbmp_t sci; /* Mask of SCI ports. */ 44 bcm_pbmp_t sfi; /* Mask of SFI ports. */ 45 bcm_pbmp_t spi; /* Mask of SPI ports. */ 46 bcm_pbmp_t spi_subport; /* Mask of SPI subports. */ 47 bcm_pbmp_t port; /* Mask of all front panel ports. */ 48 bcm_pbmp_t cpu; /* Mask of CPU ports. */ 49 bcm_pbmp_t all; /* Mask of all ports. */ 50 bcm_pbmp_t stack_int; /* Deprecated - unused. */ 51 bcm_pbmp_t stack_ext; /* Mask of Stack ports. */ 52 bcm_pbmp_t tdm; /* Mask of TDM ports. */ 53 bcm_pbmp_t pon; /* Mask of PON ports. */ 54 bcm_pbmp_t llid; /* Mask of LLID ports. */ 55 bcm_pbmp_t il; /* Mask of ILKN ports. */ 56 bcm_pbmp_t xl; /* Mask of XLAUI ports. */ 57 bcm_pbmp_t rcy; /* Mask of RECYCLE ports. */ 58 bcm_pbmp_t sat; /* Mask of SAT ports. */ 59 bcm_pbmp_t ipsec; /* Mask of IPSEC ports. */ 60 bcm_pbmp_t per_pipe[BCM_PIPES_MAX]; /* Mask of ports per pipe. The number of 61 pipes per device can be obtained via 62 num_pipes field of bcm_info_t. */ 63 bcm_pbmp_t nif; /* Mask of Network Interfaces ports. */ 64 bcm_pbmp_t control; /* Mask of hot swap controlling ports. */ 65 bcm_pbmp_t eventor; /* Mask of Eventor ports. */ 66 bcm_pbmp_t olp; /* Mask of OLP ports. */ 67 bcm_pbmp_t oamp; /* Mask of OAMP ports. */ 68 bcm_pbmp_t erp; /* Mask of ERP ports. */ 69 bcm_pbmp_t roe; /* Mask of ROE ports. */ 70 bcm_pbmp_t rcy_mirror; /* Mask of mirror recycle ports (sniff) */ 71 bcm_pbmp_t per_pp_pipe[BCM_PP_PIPES_MAX]; /* Mask of ports per PP pipe. The number 72 of PP pipes per device can be 73 obtained via num_pp_pipes field of 74 bcm_info_t. */ 75 bcm_pbmp_t stat; /* Mask of stat ports. */ 76 bcm_pbmp_t crps; /* Mask of crps ports. */ 77 } bcm_port_config_t; 78 79 /* Port destination info structure. */ 80 typedef struct bcm_port_dest_info_s { 81 uint32 flags; /* Future expansion. */ 82 bcm_gport_t gport; /* e.g. sysport gport, unicast gport, multicast gport, 83 etc... */ 84 bcm_cos_t priority; /* Traffic class (0-7). */ 85 bcm_color_t dp; /* Drop precedence (0-3). */ 86 } bcm_port_dest_info_t; 87 88 /* Port ability */ 89 typedef _shr_port_ability_t bcm_port_ability_t; 90 91 #define BCM_PORT_ABILITY_10MB _SHR_PA_SPEED_10MB 92 #define BCM_PORT_ABILITY_100MB _SHR_PA_SPEED_100MB 93 #define BCM_PORT_ABILITY_1000MB _SHR_PA_SPEED_1000MB 94 #define BCM_PORT_ABILITY_2500MB _SHR_PA_SPEED_2500MB 95 #define BCM_PORT_ABILITY_3000MB _SHR_PA_SPEED_3000MB 96 #define BCM_PORT_ABILITY_5000MB _SHR_PA_SPEED_5000MB 97 #define BCM_PORT_ABILITY_6000MB _SHR_PA_SPEED_6000MB 98 #define BCM_PORT_ABILITY_10GB _SHR_PA_SPEED_10GB 99 #define BCM_PORT_ABILITY_11GB _SHR_PA_SPEED_11GB 100 #define BCM_PORT_ABILITY_12GB _SHR_PA_SPEED_12GB 101 #define BCM_PORT_ABILITY_12P5GB _SHR_PA_SPEED_12P5GB 102 #define BCM_PORT_ABILITY_13GB _SHR_PA_SPEED_13GB 103 #define BCM_PORT_ABILITY_15GB _SHR_PA_SPEED_15GB 104 #define BCM_PORT_ABILITY_16GB _SHR_PA_SPEED_16GB 105 #define BCM_PORT_ABILITY_20GB _SHR_PA_SPEED_20GB 106 #define BCM_PORT_ABILITY_21GB _SHR_PA_SPEED_21GB 107 #define BCM_PORT_ABILITY_23GB _SHR_PA_SPEED_23GB 108 #define BCM_PORT_ABILITY_24GB _SHR_PA_SPEED_24GB 109 #define BCM_PORT_ABILITY_25GB _SHR_PA_SPEED_25GB 110 #define BCM_PORT_ABILITY_27GB _SHR_PA_SPEED_27GB 111 #define BCM_PORT_ABILITY_30GB _SHR_PA_SPEED_30GB 112 #define BCM_PORT_ABILITY_32GB _SHR_PA_SPEED_32GB 113 #define BCM_PORT_ABILITY_40GB _SHR_PA_SPEED_40GB 114 #define BCM_PORT_ABILITY_42GB _SHR_PA_SPEED_42GB 115 #define BCM_PORT_ABILITY_48GB _SHR_PA_SPEED_48GB 116 #define BCM_PORT_ABILITY_50GB _SHR_PA_SPEED_50GB 117 #define BCM_PORT_ABILITY_53GB _SHR_PA_SPEED_53GB 118 #define BCM_PORT_ABILITY_100GB _SHR_PA_SPEED_100GB 119 #define BCM_PORT_ABILITY_106GB _SHR_PA_SPEED_106GB 120 #define BCM_PORT_ABILITY_120GB _SHR_PA_SPEED_120GB 121 #define BCM_PORT_ABILITY_127GB _SHR_PA_SPEED_127GB 122 #define BCM_PORT_ABILITY_INTERFACE_TBI _SHR_PA_INTF_TBI 123 #define BCM_PORT_ABILITY_INTERFACE_MII _SHR_PA_INTF_MII 124 #define BCM_PORT_ABILITY_INTERFACE_GMII _SHR_PA_INTF_GMII 125 #define BCM_PORT_ABILITY_INTERFACE_SGMII _SHR_PA_INTF_SGMII 126 #define BCM_PORT_ABILITY_INTERFACE_XGMII _SHR_PA_INTF_XGMII 127 #define BCM_PORT_ABILITY_INTERFACE_QSGMII _SHR_PA_INTF_QSGMII 128 #define BCM_PORT_ABILITY_INTERFACE_CGMII _SHR_PA_INTF_CGMII 129 #define BCM_PORT_ABILITY_MEDIUM_COPPER _SHR_PA_MEDIUM_COPPER 130 #define BCM_PORT_ABILITY_MEDIUM_FIBER _SHR_PA_MEDIUM_FIBER 131 #define BCM_PORT_ABILITY_MEDIUM_BACKPLANE _SHR_PA_MEDIUM_BACKPLANE 132 #define BCM_PORT_ABILITY_LB_NONE _SHR_PA_LB_NONE 133 #define BCM_PORT_ABILITY_LB_MAC _SHR_PA_LB_MAC 134 #define BCM_PORT_ABILITY_LB_PHY _SHR_PA_LB_PHY 135 #define BCM_PORT_ABILITY_LB_LINE _SHR_PA_LB_LINE 136 #define BCM_PORT_ABILITY_AUTONEG _SHR_PA_AUTONEG 137 #define BCM_PORT_ABILITY_COMBO _SHR_PA_COMBO 138 #define BCM_PORT_ABILITY_PAUSE_TX _SHR_PA_PAUSE_TX 139 #define BCM_PORT_ABILITY_PAUSE_RX _SHR_PA_PAUSE_RX 140 #define BCM_PORT_ABILITY_PAUSE _SHR_PA_PAUSE /* Both TX and RX. */ 141 #define BCM_PORT_ABILITY_PAUSE_ASYMM _SHR_PA_PAUSE_ASYMM /* The following is used 142 only by 143 bcm_port_ability_get, 144 and indicates that a 145 port can support 146 having PAUSE_TX be 147 different than 148 PAUSE_RX. */ 149 #define BCM_PORT_ABILITY_FEC_NONE _SHR_PA_FEC_NONE /* No FEC request */ 150 #define BCM_PORT_ABILITY_FEC_CL74 _SHR_PA_FEC_CL74 /* FEC CL74 request. */ 151 #define BCM_PORT_ABILITY_FEC_CL91 _SHR_PA_FEC_CL91 /* FEC CL91 request. */ 152 #define BCM_PORT_ABILITY_EEE_100MB_BASETX _SHR_PA_EEE_100MB_BASETX /* EEE ability at 153 100M-BaseTX. */ 154 #define BCM_PORT_ABILITY_EEE_1GB_BASET _SHR_PA_EEE_1GB_BASET /* EEE ability at 155 1G-BaseT. */ 156 #define BCM_PORT_ABILITY_EEE_10GB_BASET _SHR_PA_EEE_10GB_BASET /* EEE ability at 157 10G-BaseT. */ 158 #define BCM_PORT_ABILITY_EEE_10GB_KX _SHR_PA_EEE_10GB_KX /* EEE ability at 159 10GB-KX. */ 160 #define BCM_PORT_ABILITY_EEE_10GB_KX4 _SHR_PA_EEE_10GB_KX4 /* EEE ability at 161 10GB-KX4. */ 162 #define BCM_PORT_ABILITY_EEE_10GB_KR _SHR_PA_EEE_10GB_KR /* EEE ability at 163 10GB-KR. */ 164 #define BCM_PORT_ABILITY_CHANNEL_LONG _SHR_PA_CHANNEL_LONG /* port is long channel. */ 165 #define BCM_PORT_ABILITY_CHANNEL_SHORT _SHR_PA_CHANNEL_SHORT /* port is short channel. */ 166 167 /* 168 * Port ability mask. 169 * 170 * The following flags are used to indicate which set of capabilities are 171 * provided by a PHY or MAC when retrieving the ability of a port, 172 * setting or getting the local advertisement, getting the remote 173 * advertisement, or setting the MAC encapsulation and/or CRC modes. 174 */ 175 typedef _shr_port_mode_t bcm_port_abil_t; 176 177 #define BCM_PORT_ABIL_10MB_HD _SHR_PM_10MB_HD 178 #define BCM_PORT_ABIL_10MB_FD _SHR_PM_10MB_FD 179 #define BCM_PORT_ABIL_100MB_HD _SHR_PM_100MB_HD 180 #define BCM_PORT_ABIL_100MB_FD _SHR_PM_100MB_FD 181 #define BCM_PORT_ABIL_1000MB_HD _SHR_PM_1000MB_HD 182 #define BCM_PORT_ABIL_1000MB_FD _SHR_PM_1000MB_FD 183 #define BCM_PORT_ABIL_2500MB_HD _SHR_PM_2500MB_HD 184 #define BCM_PORT_ABIL_2500MB_FD _SHR_PM_2500MB_FD 185 #define BCM_PORT_ABIL_3000MB_HD _SHR_PM_3000MB_HD 186 #define BCM_PORT_ABIL_3000MB_FD _SHR_PM_3000MB_FD 187 #define BCM_PORT_ABIL_10GB_HD _SHR_PM_10GB_HD 188 #define BCM_PORT_ABIL_10GB_FD _SHR_PM_10GB_FD 189 #define BCM_PORT_ABIL_12GB_HD _SHR_PM_12GB_HD 190 #define BCM_PORT_ABIL_12GB_FD _SHR_PM_12GB_FD 191 #define BCM_PORT_ABIL_13GB_HD _SHR_PM_13GB_HD 192 #define BCM_PORT_ABIL_13GB_FD _SHR_PM_13GB_FD 193 #define BCM_PORT_ABIL_16GB_HD _SHR_PM_16GB_HD 194 #define BCM_PORT_ABIL_16GB_FD _SHR_PM_16GB_FD 195 #define BCM_PORT_ABIL_TBI _SHR_PM_TBI 196 #define BCM_PORT_ABIL_MII _SHR_PM_MII 197 #define BCM_PORT_ABIL_GMII _SHR_PM_GMII 198 #define BCM_PORT_ABIL_SGMII _SHR_PM_SGMII 199 #define BCM_PORT_ABIL_XGMII _SHR_PM_XGMII 200 #define BCM_PORT_ABIL_LB_MAC _SHR_PM_LB_MAC 201 #define BCM_PORT_ABIL_LB_PHY _SHR_PM_LB_PHY 202 #define BCM_PORT_ABIL_LB_NONE _SHR_PM_LB_NONE 203 #define BCM_PORT_ABIL_AN _SHR_PM_AN 204 #define BCM_PORT_ABIL_COMBO _SHR_PM_COMBO 205 #define BCM_PORT_ABIL_PAUSE_TX _SHR_PM_PAUSE_TX 206 #define BCM_PORT_ABIL_PAUSE_RX _SHR_PM_PAUSE_RX 207 #define BCM_PORT_ABIL_PAUSE _SHR_PM_PAUSE /* Both TX and RX. */ 208 #define BCM_PORT_ABIL_10B BCM_PORT_ABIL_TBI /* Deprecated */ 209 #define BCM_PORT_ABIL_PAUSE_ASYMM _SHR_PM_PAUSE_ASYMM /* The following is used only by 210 bcm_port_ability_get, and 211 indicates that a port can 212 support having PAUSE_TX be 213 different than PAUSE_RX. */ 214 #define BCM_PORT_ABIL_10MB _SHR_PM_10MB 215 #define BCM_PORT_ABIL_100MB _SHR_PM_100MB 216 #define BCM_PORT_ABIL_1000MB _SHR_PM_1000MB 217 #define BCM_PORT_ABIL_2500MB _SHR_PM_2500MB 218 #define BCM_PORT_ABIL_3000MB _SHR_PM_3000MB 219 #define BCM_PORT_ABIL_10GB _SHR_PM_10GB 220 #define BCM_PORT_ABIL_12GB _SHR_PM_12GB 221 #define BCM_PORT_ABIL_13GB _SHR_PM_13GB 222 #define BCM_PORT_ABIL_16GB _SHR_PM_16GB 223 #define BCM_PORT_ABIL_HD _SHR_PM_HD 224 #define BCM_PORT_ABIL_FD _SHR_PM_FD 225 #define BCM_PORT_ABIL_SPD_ANY _SHR_PM_SPEED_ALL 226 227 #define BCM_PORT_ABIL_SPD_MAX(abil) \ 228 _SHR_PM_SPEED_MAX(abil) 229 230 #define BCM_PORT_ABILITY_SPEED_MAX(abil) _SHR_PA_SPEED_MAX(abil) 231 232 #define BCM_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_0 _SHR_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_0 233 #define BCM_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_1 _SHR_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_1 234 #define BCM_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_2 _SHR_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_2 235 #define BCM_PORT_CONTROL_FABRIC_HEADER_CUSTOM _SHR_PORT_CONTROL_FABRIC_HEADER_CUSTOM 236 #define BCM_PORT_CONTROL_FABRIC_HEADER_88640_TM _SHR_PORT_CONTROL_FABRIC_HEADER_88640_TM 237 #define BCM_PORT_CONTROL_FABRIC_HEADER_88640_RAW _SHR_PORT_CONTROL_FABRIC_HEADER_88640_RAW 238 239 /* Port Management packet Classification flags. */ 240 #define BCM_PORT_MANAGEMENT_PACKET_ETHERTYPE 0x01 /* If set, ether type is 241 valid in the 242 configuration 243 structure. */ 244 #define BCM_PORT_MANAGEMENT_PACKET_DEST_MAC 0x02 /* If set, Destination 245 MAC is valid in the 246 configuration 247 structure. */ 248 #define BCM_PORT_MANAGEMENT_PACKET_CLEAR 0x80 /* If set, Destination 249 MAC and or EtherType 250 to be cleared from 251 Management packet 252 classification. */ 253 254 /* Port Management Packet Classification Configuration structure. */ 255 typedef struct bcm_port_management_packet_config_s { 256 uint32 flags; /* See BCM_PORT_MANAGEMENT_XXX flag definitions. */ 257 bcm_ethertype_t ethertype; /* Ether Type for packet classification. */ 258 bcm_mac_t dest_mac; /* Destination mac address for packet 259 classification */ 260 } bcm_port_management_packet_config_t; 261 262 #ifndef BCM_HIDE_DISPATCHABLE 263 264 /* Initialize the port subsystem. */ 265 extern int bcm_port_init( 266 int unit); 267 268 /* 269 * Initialize the port subsystem without affecting the current state of 270 * stack ports. 271 */ 272 extern int bcm_port_clear( 273 int unit); 274 275 /* Probe the port to determine the proper MAC and PHY drivers. */ 276 extern int bcm_port_probe( 277 int unit, 278 bcm_pbmp_t pbmp, 279 bcm_pbmp_t *okay_pbmp); 280 281 /* Detach ports from the BCM API. */ 282 extern int bcm_port_detach( 283 int unit, 284 bcm_pbmp_t pbmp, 285 bcm_pbmp_t *detached); 286 287 /* Retrieved the port configuration for the specified device. */ 288 extern int bcm_port_config_get( 289 int unit, 290 bcm_port_config_t *config); 291 292 /* Enable or disable a port. */ 293 extern int bcm_port_enable_set( 294 int unit, 295 bcm_port_t port, 296 int enable); 297 298 /* Enable or disable a port. */ 299 extern int bcm_port_enable_get( 300 int unit, 301 bcm_port_t port, 302 int *enable); 303 304 /* Set or retrieve autonegotiation settings for a port. */ 305 extern int bcm_port_advert_set( 306 int unit, 307 bcm_port_t port, 308 bcm_port_abil_t ability_mask); 309 310 /* Set or retrieve auto-negotiation abilities for a port. */ 311 extern int bcm_port_ability_advert_set( 312 int unit, 313 bcm_port_t port, 314 bcm_port_ability_t *ability_mask); 315 316 /* Set or retrieve autonegotiation settings for a port. */ 317 extern int bcm_port_advert_get( 318 int unit, 319 bcm_port_t port, 320 bcm_port_abil_t *ability_mask); 321 322 /* Set or retrieve auto-negotiation abilities for a port. */ 323 extern int bcm_port_ability_advert_get( 324 int unit, 325 bcm_port_t port, 326 bcm_port_ability_t *ability_mask); 327 328 /* Set or retrieve autonegotiation settings for a port. */ 329 extern int bcm_port_advert_remote_get( 330 int unit, 331 bcm_port_t port, 332 bcm_port_abil_t *ability_mask); 333 334 /* Retrieve the valid abilities of a remote port. */ 335 extern int bcm_port_ability_remote_get( 336 int unit, 337 bcm_port_t port, 338 bcm_port_ability_t *ability_mask); 339 340 /* 341 * Retrieve the valid operating modes of a port including speed and 342 * duplex. 343 */ 344 extern int bcm_port_ability_get( 345 int unit, 346 bcm_port_t port, 347 bcm_port_abil_t *local_ability_mask); 348 349 /* Retrieve the valid abilities of a local port. */ 350 extern int bcm_port_ability_local_get( 351 int unit, 352 bcm_port_t port, 353 bcm_port_ability_t *local_ability_mask); 354 355 #endif /* BCM_HIDE_DISPATCHABLE */ 356 357 /* Backward compatibility. */ 358 #define bcm_port_remote_advert_get bcm_port_advert_remote_get 359 360 #ifndef BCM_HIDE_DISPATCHABLE 361 362 /* Get or set the management packet classification properties. */ 363 extern int bcm_port_management_packet_config_set( 364 int unit, 365 bcm_port_t port, 366 bcm_port_management_packet_config_t *config); 367 368 /* Get or set the management packet classification properties. */ 369 extern int bcm_port_management_packet_config_get( 370 int unit, 371 bcm_port_t port, 372 bcm_port_management_packet_config_t *config_array, 373 int max_config, 374 int *config_count); 375 376 /* Get or set the default VLAN for packets that ingress untagged. */ 377 extern int bcm_port_untagged_vlan_set( 378 int unit, 379 bcm_port_t port, 380 bcm_vlan_t vid); 381 382 /* Get or set the default VLAN for packets that ingress untagged. */ 383 extern int bcm_port_untagged_vlan_get( 384 int unit, 385 bcm_port_t port, 386 bcm_vlan_t *vid_ptr); 387 388 /* Get or set the default priority for packets that ingress untagged. */ 389 extern int bcm_port_untagged_priority_set( 390 int unit, 391 bcm_port_t port, 392 int priority); 393 394 /* Get or set the default priority for packets that ingress untagged. */ 395 extern int bcm_port_untagged_priority_get( 396 int unit, 397 bcm_port_t port, 398 int *priority); 399 400 #endif /* BCM_HIDE_DISPATCHABLE */ 401 402 #define BCM_PORT_DSCP_MAP_NONE 0 /* Disable DSCP mapping */ 403 #define BCM_PORT_DSCP_MAP_ZERO 1 /* Map only if incoming DSCP 404 = 0. */ 405 #define BCM_PORT_DSCP_MAP_ALL 2 /* Map all. */ 406 #define BCM_PORT_DSCP_MAP_UNTAGGED_ONLY 3 /* Map only when packet is 407 untagged. */ 408 #define BCM_PORT_DSCP_MAP_DEFAULT 4 /* Map according to default 409 mapping,Not looking at PCP 410 or TOS. */ 411 #define BCM_PORT_DSCP_MAP_IPV4_ONLY (1 << 3) /* Map DSCP only for IPv4 412 packets. */ 413 #define BCM_PORT_DSCP_MAP_IPV6_ONLY (1 << 4) /* Map DSCP only for IPv6 414 packets. */ 415 #define BCM_PORT_DSCP_MAP_IPV4_NONE (1 << 5) /* Disable DSCP mapping for 416 IPv4 packets. */ 417 #define BCM_PORT_DSCP_MAP_IPV6_NONE (1 << 6) /* Disable DSCP mapping for 418 IPv6 packets. */ 419 420 #ifndef BCM_HIDE_DISPATCHABLE 421 422 /* Control mapping of Differentiated Services Code Points (DSCP). */ 423 extern int bcm_port_dscp_map_mode_set( 424 int unit, 425 bcm_port_t port, 426 int mode); 427 428 /* Control mapping of Differentiated Services Code Points (DSCP). */ 429 extern int bcm_port_dscp_map_mode_get( 430 int unit, 431 bcm_port_t port, 432 int *mode); 433 434 /* Control mapping of Differentiated Services Code Points (DSCP) */ 435 extern int bcm_port_dscp_map_set( 436 int unit, 437 bcm_port_t port, 438 int srccp, 439 int mapcp, 440 int prio); 441 442 /* Control mapping of Differentiated Services Code Points (DSCP) */ 443 extern int bcm_port_dscp_map_get( 444 int unit, 445 bcm_port_t port, 446 int srccp, 447 int *mapcp, 448 int *prio); 449 450 /* Get or set the current linkscan mode for the specified port. */ 451 extern int bcm_port_linkscan_set( 452 int unit, 453 bcm_port_t port, 454 int linkscan); 455 456 /* Get or set the current linkscan mode for the specified port. */ 457 extern int bcm_port_linkscan_get( 458 int unit, 459 bcm_port_t port, 460 int *linkscan); 461 462 /* 463 * Configure or retrieve the current auto-negotiation settings for a 464 * port, 465 * or restart auto-negotiation if already enabled. 466 */ 467 extern int bcm_port_autoneg_set( 468 int unit, 469 bcm_port_t port, 470 int autoneg); 471 472 /* 473 * Configure or retrieve the current auto-negotiation settings for a 474 * port, 475 * or restart auto-negotiation if already enabled. 476 */ 477 extern int bcm_port_autoneg_get( 478 int unit, 479 bcm_port_t port, 480 int *autoneg); 481 482 /* Get or set the current operating speed of a port. */ 483 extern int bcm_port_speed_max( 484 int unit, 485 bcm_port_t port, 486 int *speed); 487 488 /* Get or set the current operating speed of a port. */ 489 extern int bcm_port_speed_set( 490 int unit, 491 bcm_port_t port, 492 int speed); 493 494 /* Get or set the current operating speed of a port. */ 495 extern int bcm_port_speed_get( 496 int unit, 497 bcm_port_t port, 498 int *speed); 499 500 #endif /* BCM_HIDE_DISPATCHABLE */ 501 502 /* bcm_port_ms_t */ 503 typedef _shr_port_ms_t bcm_port_ms_t; 504 505 #define BCM_PORT_MS_SLAVE _SHR_PORT_MS_SLAVE 506 #define BCM_PORT_MS_MASTER _SHR_PORT_MS_MASTER 507 #define BCM_PORT_MS_AUTO _SHR_PORT_MS_AUTO 508 #define BCM_PORT_MS_NONE _SHR_PORT_MS_NONE 509 #define BCM_PORT_MS_COUNT _SHR_PORT_MS_COUNT 510 511 #ifndef BCM_HIDE_DISPATCHABLE 512 513 /* Set or get the Master mode on the PHY attached to the specified port. */ 514 extern int bcm_port_master_set( 515 int unit, 516 bcm_port_t port, 517 int ms); 518 519 /* Set or get the Master mode on the PHY attached to the specified port. */ 520 extern int bcm_port_master_get( 521 int unit, 522 bcm_port_t port, 523 int *ms); 524 525 #endif /* BCM_HIDE_DISPATCHABLE */ 526 527 /* bcm_port_if_t */ 528 typedef _shr_port_if_t bcm_port_if_t; 529 530 /* Port properties structure. */ 531 typedef struct bcm_port_interface_config_s { 532 uint32 flags; /* flags of port. */ 533 uint32 channel; /* channel of port. */ 534 uint32 phy_port; /* related phy port. */ 535 bcm_port_if_t interface; /* interface of port. */ 536 } bcm_port_interface_config_t; 537 538 /* physical port properties structure. */ 539 typedef struct bcm_port_interface_info_s { 540 uint32 phy_port; /* related phy port. */ 541 bcm_port_if_t interface; /* interface of port. */ 542 uint32 num_lanes; /* number of lanes the interface uses. */ 543 bcm_pbmp_t phy_pbmp; /* bitmap of phy lanes the interface occupies. */ 544 uint32 interface_id; /* should be indicated in case the id can't be 545 derived from phy_port. */ 546 int max_speed; /* The supported port max speed via legacy flex 547 port operations, i.e. the max speed 548 provisioned through soc property port_map. */ 549 } bcm_port_interface_info_t; 550 551 /* port mapping properties structure. */ 552 typedef struct bcm_port_mapping_info_s { 553 uint32 channel; /* logical port channel. */ 554 int core; /* core id */ 555 uint32 tm_port; /* tm port id */ 556 uint32 pp_port; /* pp port id */ 557 uint32 base_q_pair; /* base queue pair id */ 558 uint32 num_priorities; /* number of port priorities */ 559 uint32 base_hr; /* base hr id */ 560 uint32 num_sch_priorities; /* number of sch port priorities */ 561 uint32 base_uc_queue; /* base uc queue */ 562 uint32 num_uc_queue; /* number of uc queue */ 563 uint32 base_mc_queue; /* base mc queue */ 564 uint32 num_mc_queue; /* number of mc queue */ 565 } bcm_port_mapping_info_t; 566 567 /* Initialize structure bcm_port_mapping_info_t */ 568 extern void bcm_port_mapping_info_t_init( 569 bcm_port_mapping_info_t *mapping); 570 571 /* Port link state structure. */ 572 typedef struct bcm_port_link_state_s { 573 int status; /* link status, one of BCM_PORT_LINK_STATUS_* */ 574 int latch_down; /* indicates whether link latch has been down since last 575 call to API. */ 576 } bcm_port_link_state_t; 577 578 #define BCM_PORT_IF_NOCXN _SHR_PORT_IF_NOCXN 579 #define BCM_PORT_IF_NULL _SHR_PORT_IF_NULL 580 #define BCM_PORT_IF_MII _SHR_PORT_IF_MII /* MII Operating mode, 581 not supported on all 582 ports */ 583 #define BCM_PORT_IF_GMII _SHR_PORT_IF_GMII /* GMII Operating mode, 584 not supported on all 585 ports */ 586 #define BCM_PORT_IF_SGMII _SHR_PORT_IF_SGMII 587 #define BCM_PORT_IF_TBI _SHR_PORT_IF_TBI /* TBI interface 588 supported on Gigabit 589 Ethernet ports 590 operating at gigabit 591 speeds */ 592 #define BCM_PORT_IF_XGMII _SHR_PORT_IF_XGMII /* 10-Gigabit interface */ 593 #define BCM_PORT_IF_RGMII _SHR_PORT_IF_RGMII /* Reduced Gigabit Media 594 Independent Interface */ 595 #define BCM_PORT_IF_SFI _SHR_PORT_IF_SFI /* SFI 10-Gigabit serial 596 electrical interface */ 597 #define BCM_PORT_IF_XFI _SHR_PORT_IF_XFI /* XFI 10-Gigabit serial 598 electrical interface */ 599 #define BCM_PORT_IF_KR _SHR_PORT_IF_KR /* Backplane 10 GbE 600 64B/66B interface */ 601 #define BCM_PORT_IF_KR2 _SHR_PORT_IF_KR2 /* Backplane 2x10GbE 602 64B/66B interface */ 603 #define BCM_PORT_IF_KR4 _SHR_PORT_IF_KR4 /* Backplane 4x10 GbE 604 64B/66B interface */ 605 #define BCM_PORT_IF_CR _SHR_PORT_IF_CR /* Copper 10 GbE 64B/66B 606 interface */ 607 #define BCM_PORT_IF_CR2 _SHR_PORT_IF_CR2 /* Copper 2x10GbE 64B/66B 608 interface */ 609 #define BCM_PORT_IF_CR4 _SHR_PORT_IF_CR4 /* Copper 4x10 GbE 610 64B/66B interface. */ 611 #define BCM_PORT_IF_XLAUI _SHR_PORT_IF_XLAUI /* 40 Gigabit Attachment 612 Unit Interface */ 613 #define BCM_PORT_IF_XLAUI2 _SHR_PORT_IF_XLAUI2 /* 40 Gigabit Attachment 614 Unit Interface over 2 615 lanes */ 616 #define BCM_PORT_IF_RXAUI _SHR_PORT_IF_RXAUI 617 #define BCM_PORT_IF_XAUI _SHR_PORT_IF_XAUI 618 #define BCM_PORT_IF_SPAUI _SHR_PORT_IF_SPAUI 619 #define BCM_PORT_IF_QSGMII _SHR_PORT_IF_QSGMII 620 #define BCM_PORT_IF_ILKN _SHR_PORT_IF_ILKN 621 #define BCM_PORT_IF_RCY _SHR_PORT_IF_RCY 622 #define BCM_PORT_IF_FAT_PIPE _SHR_PORT_IF_FAT_PIPE 623 #define BCM_PORT_IF_SR _SHR_PORT_IF_SR /* Fiber SR/LR 64B/66B 624 interface */ 625 #define BCM_PORT_IF_SR2 _SHR_PORT_IF_SR2 /* Fiber 2x10GbE 64B/66B 626 interface. */ 627 #define BCM_PORT_IF_CAUI _SHR_PORT_IF_CAUI 628 #define BCM_PORT_IF_LR _SHR_PORT_IF_LR /* Fiber LR 64B/66B 629 interface */ 630 #define BCM_PORT_IF_LR4 _SHR_PORT_IF_LR4 /* Fiber LR4 64B/66B 631 interface */ 632 #define BCM_PORT_IF_SR4 _SHR_PORT_IF_SR4 /* Fiber SR4 64B/66B 633 interface */ 634 #define BCM_PORT_IF_KX _SHR_PORT_IF_KX 635 #define BCM_PORT_IF_ZR _SHR_PORT_IF_ZR /* Fiber ZR 64B/66B 636 interface */ 637 #define BCM_PORT_IF_SR10 _SHR_PORT_IF_SR10 /* Fiber SR10 64B/66B 638 interface. */ 639 #define BCM_PORT_IF_CR10 _SHR_PORT_IF_CR10 /* Copper CR10 64B/66B 640 interface. */ 641 #define BCM_PORT_IF_KR10 _SHR_PORT_IF_KR10 /* Backplane KR10 64B/66B 642 interface. */ 643 #define BCM_PORT_IF_LR10 _SHR_PORT_IF_LR10 /* Fiber LR10 64B/66B 644 interface. */ 645 #define BCM_PORT_IF_OTL _SHR_PORT_IF_OTL /* Fiber 4x25 GbE OTL 646 interface */ 647 #define BCM_PORT_IF_CPU _SHR_PORT_IF_CPU 648 #define BCM_PORT_IF_ER _SHR_PORT_IF_ER /* Fiber ER 64B/66B 649 interface */ 650 #define BCM_PORT_IF_ER2 _SHR_PORT_IF_ER2 /* Fiber ER2 2x10G 651 64B/66B interface */ 652 #define BCM_PORT_IF_ER4 _SHR_PORT_IF_ER4 /* Fiber ER4 4x10G 653 64B/66B interface */ 654 #define BCM_PORT_IF_CX _SHR_PORT_IF_CX /* Copper 10G 10B/8B 655 interface */ 656 #define BCM_PORT_IF_CX2 _SHR_PORT_IF_CX2 /* Copper 2x10G 10B/8B 657 interface. */ 658 #define BCM_PORT_IF_CX4 _SHR_PORT_IF_CX4 /* Copper 4x10G 10B/8B 659 interface */ 660 #define BCM_PORT_IF_CAUI_C2C _SHR_PORT_IF_CAUI_C2C /* CAUI 100G C2C 661 interface */ 662 #define BCM_PORT_IF_CAUI_C2M _SHR_PORT_IF_CAUI_C2M /* CAUI 100G C2M 663 interface */ 664 #define BCM_PORT_IF_VSR _SHR_PORT_IF_VSR /* Fiber VSR 10G 64B/66B 665 interface */ 666 #define BCM_PORT_IF_LR2 _SHR_PORT_IF_LR2 /* Fiber 2x10Gbe LR 667 64B/66B interface */ 668 #define BCM_PORT_IF_LRM _SHR_PORT_IF_LRM /* Fiber LRM multipoint 669 64B/66B interface */ 670 #define BCM_PORT_IF_XLPPI _SHR_PORT_IF_XLPPI /* 40G parallel physical 671 interface */ 672 #define BCM_PORT_IF_LBG _SHR_PORT_IF_LBG /* Link bonding interface */ 673 #define BCM_PORT_IF_CAUI4 _SHR_PORT_IF_CAUI4 /* CAUI4 100G interface */ 674 #define BCM_PORT_IF_OAMP _SHR_PORT_IF_OAMP 675 #define BCM_PORT_IF_OLP _SHR_PORT_IF_OLP 676 #define BCM_PORT_IF_ERP _SHR_PORT_IF_ERP 677 #define BCM_PORT_IF_SAT _SHR_PORT_IF_SAT 678 #define BCM_PORT_IF_RCY_MIRROR _SHR_PORT_IF_RCY_MIRROR 679 #define BCM_PORT_IF_EVENTOR _SHR_PORT_IF_EVENTOR 680 #define BCM_PORT_IF_NIF_ETH _SHR_PORT_IF_NIF_ETH /* NIF interface */ 681 #define BCM_PORT_IF_FLEXE_CLIENT _SHR_PORT_IF_FLEXE_CLIENT /* FlexE client */ 682 #define BCM_PORT_IF_VIRTUAL_FLEXE_CLIENT _SHR_PORT_IF_VIRTUAL_FLEXE_CLIENT /* Virtual FlexE client */ 683 #define BCM_PORT_IF_SCH _SHR_PORT_IF_SCH 684 #define BCM_PORT_IF_CRPS _SHR_PORT_IF_CRPS 685 #define BCM_PORT_IF_COUNT _SHR_PORT_IF_COUNT 686 687 #define BCM_PORT_IF_10B BCM_PORT_IF_TBI /* Deprecated */ 688 689 #ifndef BCM_HIDE_DISPATCHABLE 690 691 /* 692 * Configure the physical interface between the MAC and the PHY for 693 * the specified port. 694 */ 695 extern int bcm_port_interface_set( 696 int unit, 697 bcm_port_t port, 698 bcm_port_if_t intf); 699 700 /* 701 * Configure the physical interface between the MAC and the PHY for 702 * the specified port. 703 */ 704 extern int bcm_port_interface_get( 705 int unit, 706 bcm_port_t port, 707 bcm_port_if_t *intf); 708 709 /* Configure or retrieve port interface configuration */ 710 extern int bcm_port_interface_config_set( 711 int unit, 712 bcm_port_t port, 713 bcm_port_interface_config_t *config); 714 715 /* Configure or retrieve port interface configuration */ 716 extern int bcm_port_interface_config_get( 717 int unit, 718 bcm_port_t port, 719 bcm_port_interface_config_t *config); 720 721 /* add/remove/get port */ 722 extern int bcm_port_add( 723 int unit, 724 bcm_port_t port, 725 uint32 flags, 726 bcm_port_interface_info_t *interface_info, 727 bcm_port_mapping_info_t *mapping_info); 728 729 /* add/remove/get port */ 730 extern int bcm_port_get( 731 int unit, 732 bcm_port_t port, 733 uint32 *flags, 734 bcm_port_interface_info_t *interface_info, 735 bcm_port_mapping_info_t *mapping_info); 736 737 /* add/remove/get port */ 738 extern int bcm_port_remove( 739 int unit, 740 bcm_port_t port, 741 uint32 flags); 742 743 #endif /* BCM_HIDE_DISPATCHABLE */ 744 745 /* Port add flags. */ 746 #define BCM_PORT_ADD_BASE_Q_PAIR_WITH_ID 0x0001 /* Static base queue pair 747 configuration, should 748 be passed in API */ 749 #define BCM_PORT_ADD_CONFIG_CHANNELIZED 0x0002 /* Indicate a channelized 750 interface */ 751 #define BCM_PORT_ADD_CGM_AUTO_ADJUST_DISABLE 0x0004 /* Disable CGM 752 adjustments */ 753 #define BCM_PORT_ADD_HIGH_GIG 0x0008 /* Indicate a High Gig 754 port */ 755 #define BCM_PORT_ADD_DONT_PROBE 0x0010 /* Don't initialize the 756 physical port */ 757 #define BCM_PORT_ADD_USE_PHY_PBMP 0x0020 /* The phy pots occupided 758 by the interface are 759 indicated by phy_pbmp 760 in interface_info 761 struct */ 762 #define BCM_PORT_ADD_TDM_QUEUING_ON 0x0040 /* TDM queuing is on for 763 this port, it's 764 handled as a TDM 765 interleaved port */ 766 #define BCM_PORT_ADD_TDM_PORT 0x0080 /* Indicate a new TDM 767 port */ 768 #define BCM_PORT_ADD_KBP_PORT 0x0100 /* Indicate it is a port 769 for KBP */ 770 #define BCM_PORT_ADD_STIF_PORT 0x0200 /* Indicate it is a port 771 for statistics 772 interface */ 773 #define BCM_PORT_ADD_MODEM_PORT 0x0400 /* Indicate it is a port 774 used for Link bonding 775 modem */ 776 #define BCM_PORT_ADD_BICAST_PORT 0x0800 /* Indicate it is a port 777 used for Bicast */ 778 #define BCM_PORT_ADD_ILKN_OVER_FABRIC_PORT 0x1000 /* Indicate it is an over 779 fabric port */ 780 #define BCM_PORT_ADD_CROSS_CONNECT 0x2000 /* Indicate it is a port 781 for cross connect */ 782 #define BCM_PORT_ADD_FLEXE_PHY 0x4000 /* Indicate it is a port 783 for FlexE physical 784 interface */ 785 #define BCM_PORT_ADD_FLEXE_MAC 0x8000 /* Indicate it is a port 786 for FlexE MAC channel */ 787 #define BCM_PORT_ADD_FLEXE_SAR 0x10000 /* Indicate it is a port 788 for FlexE SAR channel */ 789 #define BCM_PORT_ADD_EGRESS_INTERLEAVING_ENABLE 0x20000 /* Indicates egress 790 interleaving enable */ 791 #define BCM_PORT_ADD_IF_TDM_ONLY 0x40000 /* Indicate if the 792 interface will have 793 only TDM ports */ 794 #define BCM_PORT_ADD_IF_TDM_HYBRID 0x80000 /* Indicates if the 795 interface will have 796 some TDM ports and 797 some NON-TDM ports */ 798 #define BCM_PORT_ADD_SCH_PRIORITY_PROPAGATION_EN 0x100000 /* Enable scheduler 799 priority propagation 800 on the port */ 801 #define BCM_PORT_ADD_SCH_ONLY 0x200000 /* Add scheduler to the 802 existing port */ 803 #define BCM_PORT_ADD_INGRESS_INTERLEAVING_ENABLE 0x400000 /* Indicates ingress 804 interface interleaving 805 enable */ 806 #define BCM_PORT_ADD_STIF_AND_DATA_PORT 0x800000 /* Indicate it is a 807 statistics interface 808 port with data traffic 809 capabilities */ 810 811 /* Port remove flags. */ 812 #define BCM_PORT_REMOVE_SCH_ONLY 0x1 /* Remove scheduler only from the 813 port */ 814 815 /* bcm_port_duplex_t */ 816 typedef _shr_port_duplex_t bcm_port_duplex_t; 817 818 #define BCM_PORT_DUPLEX_HALF _SHR_PORT_DUPLEX_HALF 819 #define BCM_PORT_DUPLEX_FULL _SHR_PORT_DUPLEX_FULL 820 #define BCM_PORT_DUPLEX_COUNT _SHR_PORT_DUPLEX_COUNT 821 822 /* Port pause modes. */ 823 typedef enum bcm_port_pause_e { 824 BCM_PORT_PAUSE_NONE = 0, 825 BCM_PORT_PAUSE_ASYM_RX = 1, 826 BCM_PORT_PAUSE_ASYM_TX = 2, 827 BCM_PORT_PAUSE_SYM = 3 828 } bcm_port_pause_t; 829 830 /* Port PCS modes */ 831 typedef enum bcm_port_pcs_e { 832 bcmPortPCS8b9bLFec = 0, 833 bcmPortPCS8b10b = 1, 834 bcmPortPCS64b66bFec = 2, 835 bcmPortPCS64b66bBec = 3, 836 bcmPortPCS64b66b = 4, 837 bcmPortPCS64b66bRsFec = 5, 838 bcmPortPCS64b66bLowLatencyRsFec = 6, 839 bcmPortPCS64b66b15TRsFec = 7, 840 bcmPortPCS64b66b15TLowLatencyRsFec = 8 841 } bcm_port_pcs_t; 842 843 /* Set NIV Port type. */ 844 typedef enum bcm_port_niv_type_e { 845 BCM_PORT_NIV_TYPE_UPLINK = 0, /* NIV Uplink port */ 846 BCM_PORT_NIV_TYPE_RESERVED_1 = 1, /* Reserved */ 847 BCM_PORT_NIV_TYPE_RESERVED_2 = 2, /* Reserved */ 848 BCM_PORT_NIV_TYPE_UPLINK_ACCESS = BCM_PORT_NIV_TYPE_UPLINK, /* NIV uplink port */ 849 BCM_PORT_NIV_TYPE_UPLINK_TRANSIT = BCM_PORT_NIV_TYPE_UPLINK, /* NIV uplink port */ 850 BCM_PORT_NIV_TYPE_DOWNLINK_ACCESS = 3, /* NIV Downlink access port */ 851 BCM_PORT_NIV_TYPE_DOWNLINK_TRANSIT = 4, /* NIV downlink transit port */ 852 BCM_PORT_NIV_TYPE_SWITCH = 5, /* NIV switch port */ 853 BCM_PORT_NIV_TYPE_NONE = 6 854 } bcm_port_niv_type_t; 855 856 /* Set Extender Port type. */ 857 typedef enum bcm_port_extender_type_e { 858 BCM_PORT_EXTENDER_TYPE_UPLINK = 0, 859 BCM_PORT_EXTENDER_TYPE_DOWNLINK_ACCESS = 1, 860 BCM_PORT_EXTENDER_TYPE_DOWNLINK_TRANSIT= 2, 861 BCM_PORT_EXTENDER_TYPE_SWITCH = 3, 862 BCM_PORT_EXTENDER_TYPE_NONE 863 } bcm_port_extender_type_t; 864 865 /* Set Egress Port QoS Resolution Type. */ 866 typedef enum bcm_qos_resolution_type_e { 867 BCM_PORT_QOS_SERIAL_RESOLUTION = 0, 868 BCM_PORT_QOS_LAYERED_RESOLUTION = 1, 869 BCM_PORT_QOS_RESOLUTION_TYPE_NONE 870 } bcm_qos_resolution_type_t; 871 872 /* Port COS remap Selection. */ 873 typedef enum bcm_port_cos_remap_e { 874 BCM_PORT_COS_REMAP_VLAN_PRI = 0, 875 BCM_PORT_COS_REMAP_DSCP = 1, 876 BCM_PORT_COS_REMAP_EXP = 2 877 } bcm_port_cos_remap_t; 878 879 /* Port TPID source Selection. */ 880 typedef enum bcm_port_tpid_src_e { 881 bcmPortTpidSrcVp = 0, 882 bcmPortTpidSrcVpn = 1, 883 bcmPortTpidSrcPort = 2, 884 bcmPortTpidSrcTrillPayload = 3, 885 bcmPortTpidSrcCount = 4 886 } bcm_port_tpid_src_t; 887 888 #ifndef BCM_HIDE_DISPATCHABLE 889 890 /* Get or set the current duplex mode of a port. */ 891 extern int bcm_port_duplex_set( 892 int unit, 893 bcm_port_t port, 894 int duplex); 895 896 /* Get or set the current duplex mode of a port. */ 897 extern int bcm_port_duplex_get( 898 int unit, 899 bcm_port_t port, 900 int *duplex); 901 902 /* 903 * Enable or disable transmission of pause frames and honoring received 904 * pause frames on a port. 905 */ 906 extern int bcm_port_pause_set( 907 int unit, 908 bcm_port_t port, 909 int pause_tx, 910 int pause_rx); 911 912 /* 913 * Enable or disable transmission of pause frames and honoring received 914 * pause frames on a port. 915 */ 916 extern int bcm_port_pause_get( 917 int unit, 918 bcm_port_t port, 919 int *pause_tx, 920 int *pause_rx); 921 922 /* 923 * Get or set the source MAC address transmitted in MAC control pause 924 * frames. 925 */ 926 extern int bcm_port_pause_addr_set( 927 int unit, 928 bcm_port_t port, 929 bcm_mac_t mac); 930 931 /* 932 * Get or set the source MAC address transmitted in MAC control pause 933 * frames. 934 */ 935 extern int bcm_port_pause_addr_get( 936 int unit, 937 bcm_port_t port, 938 bcm_mac_t mac); 939 940 /* Configure or retrieve asymmetric pause setting for a port. */ 941 extern int bcm_port_pause_sym_set( 942 int unit, 943 bcm_port_t port, 944 int pause); 945 946 /* Configure or retrieve asymmetric pause setting for a port. */ 947 extern int bcm_port_pause_sym_get( 948 int unit, 949 bcm_port_t port, 950 int *pause); 951 952 #endif /* BCM_HIDE_DISPATCHABLE */ 953 954 /* Backward compatibility. */ 955 #define bcm_port_sym_pause_set bcm_port_pause_sym_set 956 #define bcm_port_sym_pause_get bcm_port_pause_sym_get 957 958 #ifndef BCM_HIDE_DISPATCHABLE 959 960 /* Process a link change event and perform required device configuration. */ 961 extern int bcm_port_update( 962 int unit, 963 bcm_port_t port, 964 int link); 965 966 /* Set or retrieve the current maximum packet size permitted on a port. */ 967 extern int bcm_port_frame_max_set( 968 int unit, 969 bcm_port_t port, 970 int size); 971 972 /* Set or retrieve the current maximum packet size permitted on a port. */ 973 extern int bcm_port_frame_max_get( 974 int unit, 975 bcm_port_t port, 976 int *size); 977 978 /* 979 * Set or retrieve the current maximum L3 packet size permitted on a 980 * port. 981 */ 982 extern int bcm_port_l3_mtu_set( 983 int unit, 984 bcm_port_t port, 985 int size); 986 987 /* 988 * Set or retrieve the current maximum L3 packet size permitted on a 989 * port. 990 */ 991 extern int bcm_port_l3_mtu_get( 992 int unit, 993 bcm_port_t port, 994 int *size); 995 996 /* 997 * Set or retrieve the current maximum encapsulated L3 packet size 998 * permitted on a port (Link-Layer MTU). 999 */ 1000 extern int bcm_port_l3_encapsulated_mtu_set( 1001 int unit, 1002 bcm_port_t port, 1003 int size); 1004 1005 /* 1006 * Set or retrieve the current maximum encapsulated L3 packet size 1007 * permitted on a port (Link-Layer MTU). 1008 */ 1009 extern int bcm_port_l3_encapsulated_mtu_get( 1010 int unit, 1011 bcm_port_t port, 1012 int *size); 1013 1014 /* Get or set half-duplex flow control (jam) for a port. */ 1015 extern int bcm_port_jam_set( 1016 int unit, 1017 bcm_port_t port, 1018 int enable); 1019 1020 /* Get or set half-duplex flow control (jam) for a port. */ 1021 extern int bcm_port_jam_get( 1022 int unit, 1023 bcm_port_t port, 1024 int *enable); 1025 1026 /* Get or set the interframe gap settings for the specified port. */ 1027 extern int bcm_port_ifg_set( 1028 int unit, 1029 bcm_port_t port, 1030 int speed, 1031 bcm_port_duplex_t duplex, 1032 int bit_times); 1033 1034 /* Get or set the interframe gap settings for the specified port. */ 1035 extern int bcm_port_ifg_get( 1036 int unit, 1037 bcm_port_t port, 1038 int speed, 1039 bcm_port_duplex_t duplex, 1040 int *bit_times); 1041 1042 #endif /* BCM_HIDE_DISPATCHABLE */ 1043 1044 /* Values for flags parameter of bcm_port_force_vlan_set/get. */ 1045 #define BCM_PORT_FORCE_VLAN_ENABLE 0x01 /* Enable force VLAN on 1046 this port. */ 1047 #define BCM_PORT_FORCE_VLAN_UNTAG 0x02 /* Egress untagged when 1048 force VLAN is enabled 1049 on this port. */ 1050 #define BCM_PORT_FORCE_VLAN_PROMISCUOUS_PORT 0x04 /* Promiscuous port type. */ 1051 #define BCM_PORT_FORCE_VLAN_ISOLATED_PORT 0x08 /* isolated port type. */ 1052 #define BCM_PORT_FORCE_VLAN_COMMUNITY_PORT 0x0c /* community port type. */ 1053 #define BCM_PORT_FORCE_VLAN_PORT_TYPE_MASK 0x0c /* port type mask. */ 1054 1055 #ifndef BCM_HIDE_DISPATCHABLE 1056 1057 /* Set/Get force VLAN attribute of a port. */ 1058 extern int bcm_port_force_vlan_set( 1059 int unit, 1060 bcm_port_t port, 1061 bcm_vlan_t vlan, 1062 int pkt_prio, 1063 uint32 flags); 1064 1065 /* Set/Get force VLAN attribute of a port. */ 1066 extern int bcm_port_force_vlan_get( 1067 int unit, 1068 bcm_port_t port, 1069 bcm_vlan_t *vlan, 1070 int *pkt_prio, 1071 uint32 *flags); 1072 1073 #endif /* BCM_HIDE_DISPATCHABLE */ 1074 1075 /* Flags for direct PHY register access. */ 1076 #define BCM_PORT_PHY_INTERNAL _SHR_PORT_PHY_INTERNAL 1077 #define BCM_PORT_PHY_NOMAP _SHR_PORT_PHY_NOMAP 1078 #define BCM_PORT_PHY_CLAUSE45 _SHR_PORT_PHY_CLAUSE45 1079 #define BCM_PORT_PHY_I2C_DATA8 _SHR_PORT_PHY_I2C_DATA8 1080 #define BCM_PORT_PHY_I2C_DATA16 _SHR_PORT_PHY_I2C_DATA16 1081 #define BCM_PORT_PHY_PVT_DATA _SHR_PORT_PHY_PVT_DATA 1082 #define BCM_PORT_PHY_BROADCAST_WRITE _SHR_PORT_PHY_BROADCAST_WRITE 1083 #define BCM_PORT_PHY_REG_RDB _SHR_PORT_PHY_REG_RDB 1084 #define BCM_PORT_PHY_REG_MACSEC _SHR_PORT_PHY_REG_MACSEC 1085 #define BCM_PORT_PHY_REG64_DATA_HI32 _SHR_PORT_PHY_REG64_DATA_HI32 1086 1087 #define BCM_PORT_PHY_CLAUSE45_ADDR(_devad, _regad) \ 1088 _SHR_PORT_PHY_CLAUSE45_ADDR(_devad, _regad) 1089 1090 #define BCM_PORT_PHY_CLAUSE45_DEVAD(_reg_addr) \ 1091 _SHR_PORT_PHY_CLAUSE45_DEVAD(_reg_addr) 1092 1093 #define BCM_PORT_PHY_CLAUSE45_REGAD(_reg_addr) \ 1094 _SHR_PORT_PHY_CLAUSE45_REGAD(_reg_addr) 1095 1096 #define BCM_PORT_PHY_I2C_ADDR(_devad, _regad) \ 1097 _SHR_PORT_PHY_I2C_ADDR(_devad, _regad) 1098 1099 #define BCM_PORT_PHY_I2C_DEVAD(_reg_addr) \ 1100 _SHR_PORT_PHY_I2C_DEVAD(_reg_addr) 1101 1102 #define BCM_PORT_PHY_I2C_REGAD(_reg_addr) \ 1103 _SHR_PORT_PHY_I2C_REGAD(_reg_addr) 1104 1105 /* Flags for indirect PHY register access. */ 1106 #define BCM_PORT_PHY_REG_1000X _SHR_PORT_PHY_REG_1000X 1107 1108 #define BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_type, _reg_selector) \ 1109 _SHR_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_type, _reg_selector) 1110 1111 #define BCM_PORT_PHY_REG_FLAGS(_reg_addr) _SHR_PORT_PHY_REG_FLAGS(_reg_addr) 1112 1113 #define BCM_PORT_PHY_REG_BANK(_reg_addr) _SHR_PORT_PHY_REG_BANK(_reg_addr) 1114 1115 #define BCM_PORT_PHY_REG_ADDR(_reg_addr) _SHR_PORT_PHY_REG_ADDR(_reg_addr) 1116 1117 #ifndef BCM_HIDE_DISPATCHABLE 1118 1119 /* Read or write PHY registers associated with a port. */ 1120 extern int bcm_port_phy_set( 1121 int unit, 1122 bcm_port_t port, 1123 uint32 flags, 1124 uint32 phy_reg_addr, 1125 uint32 phy_data); 1126 1127 /* Read or write PHY registers associated with a port. */ 1128 extern int bcm_port_phy_get( 1129 int unit, 1130 bcm_port_t port, 1131 uint32 flags, 1132 uint32 phy_reg_addr, 1133 uint32 *phy_data); 1134 1135 /* Read or write PHY registers associated with a port. */ 1136 extern int bcm_port_phy_modify( 1137 int unit, 1138 bcm_port_t port, 1139 uint32 flags, 1140 uint32 phy_reg_addr, 1141 uint32 phy_data, 1142 uint32 phy_mask); 1143 1144 /* 1145 * Read data from a slave device connected to a PHY associated with a 1146 * port. 1147 */ 1148 extern int bcm_port_phy_multi_get( 1149 int unit, 1150 bcm_port_t port, 1151 uint32 flags, 1152 uint32 dev_addr, 1153 uint32 offset, 1154 int max_size, 1155 uint8 *data, 1156 int *actual_size); 1157 1158 #endif /* BCM_HIDE_DISPATCHABLE */ 1159 1160 /* PHY reset callback function prototype. */ 1161 typedef _shr_port_phy_reset_cb_t bcm_port_phy_reset_cb_t; 1162 1163 #ifndef BCM_HIDE_DISPATCHABLE 1164 1165 /* Register or unregister a callout to post process PHY resets. */ 1166 extern int bcm_port_phy_reset_register( 1167 int unit, 1168 bcm_port_t port, 1169 bcm_port_phy_reset_cb_t callback, 1170 void *user_data); 1171 1172 /* Register or unregister a callout to post process PHY resets. */ 1173 extern int bcm_port_phy_reset_unregister( 1174 int unit, 1175 bcm_port_t port, 1176 bcm_port_phy_reset_cb_t callback, 1177 void *user_data); 1178 1179 /* Perform low level PHY reset. */ 1180 extern int bcm_port_phy_reset( 1181 int unit, 1182 bcm_port_t port); 1183 1184 #endif /* BCM_HIDE_DISPATCHABLE */ 1185 1186 /* MDI crossover control. */ 1187 typedef _shr_port_mdix_t bcm_port_mdix_t; 1188 1189 /* MDI crossover control values. */ 1190 #define BCM_PORT_MDIX_AUTO _SHR_PORT_MDIX_AUTO 1191 #define BCM_PORT_MDIX_FORCE_AUTO _SHR_PORT_MDIX_FORCE_AUTO 1192 #define BCM_PORT_MDIX_NORMAL _SHR_PORT_MDIX_NORMAL 1193 #define BCM_PORT_MDIX_XOVER _SHR_PORT_MDIX_XOVER 1194 #define BCM_PORT_MDIX_COUNT _SHR_PORT_MDIX_COUNT 1195 1196 /* MDI crossover status. */ 1197 typedef _shr_port_mdix_status_t bcm_port_mdix_status_t; 1198 1199 /* MDI crossover status values. */ 1200 #define BCM_PORT_MDIX_STATUS_NORMAL _SHR_PORT_MDIX_STATUS_NORMAL 1201 #define BCM_PORT_MDIX_STATUS_XOVER _SHR_PORT_MDIX_STATUS_XOVER 1202 #define BCM_PORT_MDIX_STATUS_COUNT _SHR_PORT_MDIX_STATUS_COUNT 1203 1204 #ifndef BCM_HIDE_DISPATCHABLE 1205 1206 /* Get or set the Auto MDIX mode for a port. */ 1207 extern int bcm_port_mdix_set( 1208 int unit, 1209 bcm_port_t port, 1210 bcm_port_mdix_t mode); 1211 1212 /* Get or set the Auto MDIX mode for a port. */ 1213 extern int bcm_port_mdix_get( 1214 int unit, 1215 bcm_port_t port, 1216 bcm_port_mdix_t *mode); 1217 1218 /* Get or set the Auto MDIX mode for a port. */ 1219 extern int bcm_port_mdix_status_get( 1220 int unit, 1221 bcm_port_t port, 1222 bcm_port_mdix_status_t *status); 1223 1224 #endif /* BCM_HIDE_DISPATCHABLE */ 1225 1226 /* Combo port control/status. */ 1227 typedef _shr_port_medium_t bcm_port_medium_t; 1228 1229 /* Combo port control/status values. */ 1230 #define BCM_PORT_MEDIUM_NONE _SHR_PORT_MEDIUM_NONE 1231 #define BCM_PORT_MEDIUM_COPPER _SHR_PORT_MEDIUM_COPPER 1232 #define BCM_PORT_MEDIUM_FIBER _SHR_PORT_MEDIUM_FIBER 1233 #define BCM_PORT_MEDIUM_BACKPLANE _SHR_PORT_MEDIUM_BACKPLANE 1234 #define BCM_PORT_MEDIUM_ALL _SHR_PORT_MEDIUM_ALL 1235 #define BCM_PORT_MEDIUM_COUNT _SHR_PORT_MEDIUM_COUNT 1236 1237 /* Call back function prototype for media status changes. */ 1238 typedef _shr_port_medium_status_cb_t bcm_port_medium_status_cb_t; 1239 1240 /* bcm_phy_config_t */ 1241 typedef _shr_phy_config_t bcm_phy_config_t; 1242 1243 #ifndef BCM_HIDE_DISPATCHABLE 1244 1245 /* Get or set medium preferences for combination ports. */ 1246 extern int bcm_port_medium_config_set( 1247 int unit, 1248 bcm_port_t port, 1249 bcm_port_medium_t medium, 1250 bcm_phy_config_t *config); 1251 1252 /* Get or set medium preferences for combination ports. */ 1253 extern int bcm_port_medium_config_get( 1254 int unit, 1255 bcm_port_t port, 1256 bcm_port_medium_t medium, 1257 bcm_phy_config_t *config); 1258 1259 /* Get or set medium preferences for combination ports. */ 1260 extern int bcm_port_medium_get( 1261 int unit, 1262 bcm_port_t port, 1263 bcm_port_medium_t *medium); 1264 1265 /* Register or unregister a callback function on media status changes. */ 1266 extern int bcm_port_medium_status_register( 1267 int unit, 1268 bcm_port_t port, 1269 bcm_port_medium_status_cb_t callback, 1270 void *user_data); 1271 1272 /* Register or unregister a callback function on media status changes. */ 1273 extern int bcm_port_medium_status_unregister( 1274 int unit, 1275 bcm_port_t port, 1276 bcm_port_medium_status_cb_t callback, 1277 void *user_data); 1278 1279 #endif /* BCM_HIDE_DISPATCHABLE */ 1280 1281 /* Port loopback modes. */ 1282 typedef enum bcm_port_loopback_e { 1283 BCM_PORT_LOOPBACK_NONE = 0, 1284 BCM_PORT_LOOPBACK_MAC = 1, 1285 BCM_PORT_LOOPBACK_PHY = 2, 1286 BCM_PORT_LOOPBACK_PHY_REMOTE = 3, 1287 BCM_PORT_LOOPBACK_MAC_REMOTE = 4, 1288 BCM_PORT_LOOPBACK_COUNT = 5 1289 } bcm_port_loopback_t; 1290 1291 #ifndef BCM_HIDE_DISPATCHABLE 1292 1293 /* Set or retrieve the current loopback mode of a port. */ 1294 extern int bcm_port_loopback_set( 1295 int unit, 1296 bcm_port_t port, 1297 int loopback); 1298 1299 /* Set or retrieve the current loopback mode of a port. */ 1300 extern int bcm_port_loopback_get( 1301 int unit, 1302 bcm_port_t port, 1303 int *loopback); 1304 1305 /* 1306 * Set the spanning tree state for a port (single instance spanning tree 1307 * only). 1308 */ 1309 extern int bcm_port_stp_set( 1310 int unit, 1311 bcm_port_t port, 1312 int state); 1313 1314 /* 1315 * Set the spanning tree state for a port (single instance spanning tree 1316 * only). 1317 */ 1318 extern int bcm_port_stp_get( 1319 int unit, 1320 bcm_port_t port, 1321 int *state); 1322 1323 #endif /* BCM_HIDE_DISPATCHABLE */ 1324 1325 /* bcm_port_discard_e */ 1326 typedef enum bcm_port_discard_e { 1327 BCM_PORT_DISCARD_NONE = 0, 1328 BCM_PORT_DISCARD_ALL = 1, 1329 BCM_PORT_DISCARD_UNTAG = 2, 1330 BCM_PORT_DISCARD_TAG = 3, 1331 BCM_PORT_DISCARD_INGRESS = 4, 1332 BCM_PORT_DISCARD_EGRESS = 5, 1333 BCM_PORT_DISCARD_COUNT = 6 1334 } bcm_port_discard_t; 1335 1336 #define BCM_PORT_DISCARD_MODE_INGRESS_ONLY (1 << 15) /* Discard state should 1337 be set for ingress 1338 only */ 1339 #define BCM_PORT_DISCARD_MODE_EGRESS_ONLY (1 << 14) /* Discard state should 1340 be set for egress only */ 1341 1342 #ifndef BCM_HIDE_DISPATCHABLE 1343 1344 /* 1345 * Configure port discard mode for packets ingressing tagged and 1346 * untagged. 1347 */ 1348 extern int bcm_port_discard_set( 1349 int unit, 1350 bcm_port_t port, 1351 int mode); 1352 1353 /* 1354 * Configure port discard mode for packets ingressing tagged and 1355 * untagged. 1356 */ 1357 extern int bcm_port_discard_get( 1358 int unit, 1359 bcm_port_t port, 1360 int *mode); 1361 1362 #endif /* BCM_HIDE_DISPATCHABLE */ 1363 1364 /* 1365 * Flags for learn mode 1366 * 1367 * This call takes flags to turn on and off mutually-independent actions 1368 * that should be taken when a packet is received with an unknown source 1369 * address, or source lookup failure (SLF). 1370 * 1371 * The set call returns BCM_E_UNAVAIL for flag combinations that are not 1372 * supported by the hardware. 1373 */ 1374 #define BCM_PORT_LEARN_ARL 0x01 /* Learn SLF address. */ 1375 #define BCM_PORT_LEARN_CPU 0x02 /* Copy SLF packet to CPU. */ 1376 #define BCM_PORT_LEARN_FWD 0x04 /* Forward SLF packet */ 1377 #define BCM_PORT_LEARN_PENDING 0x08 /* Mark learned SLF as pending */ 1378 #define BCM_PORT_LEARN_ON 0x01 /* Deprecated name */ 1379 #define BCM_PORT_LEARN_SWITCH 0x04 /* Deprecated name */ 1380 1381 #ifndef BCM_HIDE_DISPATCHABLE 1382 1383 /* Control the hardware and software learning support on a port. */ 1384 extern int bcm_port_learn_set( 1385 int unit, 1386 bcm_port_t port, 1387 uint32 flags); 1388 1389 /* Control the hardware and software learning support on a port. */ 1390 extern int bcm_port_learn_get( 1391 int unit, 1392 bcm_port_t port, 1393 uint32 *flags); 1394 1395 /* Control the hardware and software learning support on a port. */ 1396 extern int bcm_port_learn_modify( 1397 int unit, 1398 bcm_port_t port, 1399 uint32 add, 1400 uint32 remove); 1401 1402 #endif /* BCM_HIDE_DISPATCHABLE */ 1403 1404 #define BCM_PORT_LINK_STATUS_DOWN 0 1405 #define BCM_PORT_LINK_STATUS_UP 1 1406 #define BCM_PORT_LINK_STATUS_FAILED 2 1407 #define BCM_PORT_LINK_STATUS_REMOTE_FAULT 3 1408 #define BCM_PORT_LINK_STATUS_LOCAL_FAULT 4 1409 #define BCM_PORT_LINK_STATUS_LOCAL_AND_REMOTE_FAULT 5 1410 1411 #ifndef BCM_HIDE_DISPATCHABLE 1412 1413 /* Retrieve the current link status of a port. */ 1414 extern int bcm_port_link_status_get( 1415 int unit, 1416 bcm_port_t port, 1417 int *status); 1418 1419 /* Retrieve the current link state of a port. */ 1420 extern int bcm_port_link_state_get( 1421 int unit, 1422 bcm_port_t port, 1423 uint32 flags, 1424 bcm_port_link_state_t *state); 1425 1426 /* Clear failed link status from a port which has undergone LAG failover. */ 1427 extern int bcm_port_link_failed_clear( 1428 int unit, 1429 bcm_port_t port); 1430 1431 #endif /* BCM_HIDE_DISPATCHABLE */ 1432 1433 /* 1434 * Modes for VLAN input filtering. 1435 * 1436 * Superceded APIs: use bcm_port_vlan_member_[get|set] instead. 1437 */ 1438 #define BCM_PORT_IFILTER_OFF 0 1439 #define BCM_PORT_IFILTER_ON 1 1440 1441 #ifndef BCM_HIDE_DISPATCHABLE 1442 1443 /* 1444 * Set or retrieve current behavior of tagged packets arriving on a port 1445 * not a member of the specified VLAN. 1446 */ 1447 extern int bcm_port_ifilter_set( 1448 int unit, 1449 bcm_port_t port, 1450 int mode); 1451 1452 /* 1453 * Set or retrieve current behavior of tagged packets arriving on a port 1454 * not a member of the specified VLAN. 1455 */ 1456 extern int bcm_port_ifilter_get( 1457 int unit, 1458 bcm_port_t port, 1459 int *mode); 1460 1461 #endif /* BCM_HIDE_DISPATCHABLE */ 1462 1463 /* Modes for VLAN ingress/egress filtering. */ 1464 #define BCM_PORT_VLAN_MEMBER_INGRESS 0x00000001 1465 #define BCM_PORT_VLAN_MEMBER_EGRESS 0x00000002 1466 1467 /* Table method for VLAN ingress/egress filtering. */ 1468 #define BCM_PORT_VLAN_MEMBER_VP_VLAN_MEMBERSHIP 0x00000004 1469 1470 /* 1471 * Do not perform a VFI membership check on VP, instead do a VLAN check 1472 * on physical port. 1473 */ 1474 #define BCM_PORT_VLAN_MEMBER_VP_DO_NOT_CHECK 0x00000008 1475 1476 #ifndef BCM_HIDE_DISPATCHABLE 1477 1478 /* 1479 * Set or retrieve current behavior of tagged packets arriving/leaving on 1480 * a port not a member of the specified VLAN. 1481 */ 1482 extern int bcm_port_vlan_member_set( 1483 int unit, 1484 bcm_port_t port, 1485 uint32 flags); 1486 1487 /* 1488 * Set or retrieve current behavior of tagged packets arriving/leaving on 1489 * a port not a member of the specified VLAN. 1490 */ 1491 extern int bcm_port_vlan_member_get( 1492 int unit, 1493 bcm_port_t port, 1494 uint32 *flags); 1495 1496 /* Enable or disable BPDU processing on a port. */ 1497 extern int bcm_port_bpdu_enable_set( 1498 int unit, 1499 bcm_port_t port, 1500 int enable); 1501 1502 /* Enable or disable BPDU processing on a port. */ 1503 extern int bcm_port_bpdu_enable_get( 1504 int unit, 1505 bcm_port_t port, 1506 int *enable); 1507 1508 /* Enable or disable l3 switching on an ingress port. */ 1509 extern int bcm_port_l3_enable_set( 1510 int unit, 1511 bcm_port_t port, 1512 int enable); 1513 1514 /* Enable or disable l3 switching on an ingress port. */ 1515 extern int bcm_port_l3_enable_get( 1516 int unit, 1517 bcm_port_t port, 1518 int *enable); 1519 1520 /* bcm_port_tgid_set */ 1521 extern int bcm_port_tgid_set( 1522 int unit, 1523 bcm_port_t port, 1524 int tgid, 1525 int psc); 1526 1527 /* bcm_port_tgid_get */ 1528 extern int bcm_port_tgid_get( 1529 int unit, 1530 bcm_port_t port, 1531 int *tgid, 1532 int *psc); 1533 1534 #endif /* BCM_HIDE_DISPATCHABLE */ 1535 1536 /* bcm_port_mcast_flood_t */ 1537 typedef _shr_port_mcast_flood_t bcm_port_mcast_flood_t; 1538 1539 #define BCM_PORT_MCAST_FLOOD_ALL _SHR_PORT_MCAST_FLOOD_ALL 1540 #define BCM_PORT_MCAST_FLOOD_UNKNOWN _SHR_PORT_MCAST_FLOOD_UNKNOWN 1541 #define BCM_PORT_MCAST_FLOOD_NONE _SHR_PORT_MCAST_FLOOD_NONE 1542 #define BCM_PORT_MCAST_FLOOD_COUNT _SHR_PORT_MCAST_FLOOD_COUNT 1543 1544 /* Backward compatibility. */ 1545 #define BCM_PORT_PFM_MODEA BCM_PORT_MCAST_FLOOD_ALL 1546 #define BCM_PORT_PFM_MODEB BCM_PORT_MCAST_FLOOD_UNKNOWN 1547 #define BCM_PORT_PFM_MODEC BCM_PORT_MCAST_FLOOD_NONE 1548 1549 #ifndef BCM_HIDE_DISPATCHABLE 1550 1551 /* Set or retrieve the current unknown multicast behavior. */ 1552 extern int bcm_port_pfm_set( 1553 int unit, 1554 bcm_port_t port, 1555 int mode); 1556 1557 /* Set or retrieve the current unknown multicast behavior. */ 1558 extern int bcm_port_pfm_get( 1559 int unit, 1560 bcm_port_t port, 1561 int *mode); 1562 1563 #endif /* BCM_HIDE_DISPATCHABLE */ 1564 1565 /* 1566 * Port Encapsulation modes 1567 * 1568 * Members of the XGS family of switches support multiple frame 1569 * (link-level) encapsulation modes (HIGIG, BCM5632, Ethernet). 1570 */ 1571 typedef _shr_port_encap_t bcm_port_encap_t; 1572 1573 #define BCM_PORT_ENCAP_IEEE _SHR_PORT_ENCAP_IEEE 1574 #define BCM_PORT_ENCAP_HIGIG _SHR_PORT_ENCAP_HIGIG 1575 #define BCM_PORT_ENCAP_B5632 _SHR_PORT_ENCAP_B5632 1576 #define BCM_PORT_ENCAP_HIGIG2 _SHR_PORT_ENCAP_HIGIG2 1577 #define BCM_PORT_ENCAP_HIGIG2_LITE _SHR_PORT_ENCAP_HIGIG2_LITE 1578 #define BCM_PORT_ENCAP_HIGIG2_L2 _SHR_PORT_ENCAP_HIGIG2_L2 1579 #define BCM_PORT_ENCAP_HIGIG2_IP_GRE _SHR_PORT_ENCAP_HIGIG2_IP_GRE 1580 #define BCM_PORT_ENCAP_OBSOLETE _SHR_PORT_ENCAP_OBSOLETE 1581 #define BCM_PORT_ENCAP_PREAMBLE_SOP_ONLY _SHR_PORT_ENCAP_PREAMBLE_SOP_ONLY 1582 #define BCM_PORT_ENCAP_HIGIG_OVER_ETHERNET _SHR_PORT_ENCAP_HIGIG_OVER_ETHERNET 1583 #define BCM_PORT_ENCAP_CPRI _SHR_PORT_ENCAP_CPRI 1584 #define BCM_PORT_ENCAP_RSVD4 _SHR_PORT_ENCAP_RSVD4 1585 #define BCM_PORT_ENCAP_HIGIG3 _SHR_PORT_ENCAP_HIGIG3 1586 #define BCM_PORT_ENCAP_COUNT _SHR_PORT_ENCAP_COUNT 1587 1588 /* Port Encapsulation abilities */ 1589 typedef _shr_pa_encap_t bcm_pa_encap_t; 1590 1591 #define BCM_PA_ENCAP_IEEE _SHR_PA_ENCAP_IEEE 1592 #define BCM_PA_ENCAP_HIGIG _SHR_PA_ENCAP_HIGIG 1593 #define BCM_PA_ENCAP_B5632 _SHR_PA_ENCAP_B5632 1594 #define BCM_PA_ENCAP_HIGIG2 _SHR_PA_ENCAP_HIGIG2 1595 #define BCM_PA_ENCAP_HIGIG2_LITE _SHR_PA_ENCAP_HIGIG2_LITE 1596 #define BCM_PA_ENCAP_HIGIG2_L2 _SHR_PA_ENCAP_HIGIG2_L2 1597 #define BCM_PA_ENCAP_HIGIG2_IP_GRE _SHR_PA_ENCAP_HIGIG2_IP_GRE 1598 #define BCM_PA_ENCAP_OBSOLETE _SHR_PA_ENCAP_OBSOLETE 1599 #define BCM_PA_ENCAP_HIGIG_OVER_ETHERNET _SHR_PA_ENCAP_HIGIG_OVER_ETHERNET 1600 #define BCM_PA_ENCAP_CPRI _SHR_PA_ENCAP_CPRI 1601 #define BCM_PA_ENCAP_RSVD4 _SHR_PA_ENCAP_RSVD4 1602 1603 /* bcm_port_encap_config_s */ 1604 typedef struct bcm_port_encap_config_s { 1605 bcm_port_encap_t encap; /* Port encapsulation one of the BCM_PORT_ENCAP_* */ 1606 uint16 oui_ethertype; /* Vendor specific ether type. */ 1607 uint16 higig_ethertype; /* HiGig ether type */ 1608 uint8 oui[3]; /* Vendor specific value */ 1609 uint16 hgoe_reserved; /* Value for reserved field in HGoE header */ 1610 bcm_mac_t dst_mac; /* Destination MAC address */ 1611 bcm_mac_t src_mac; /* Source MAC address */ 1612 uint16 tpid; /* Outer L2 header TPID */ 1613 uint16 vlan; /* Outer L2 header VLAN tag */ 1614 uint8 ttl; /* Hop limit. */ 1615 uint8 tos; /* Traffic Class/Tos byte */ 1616 bcm_ip_t src_addr; /* Tunnel source ip address (IPv4) */ 1617 bcm_ip_t dst_addr; /* Tunnel destination ip address (IPv4) */ 1618 } bcm_port_encap_config_t; 1619 1620 #ifndef BCM_HIDE_DISPATCHABLE 1621 1622 /* Set or get the link level encapsulation configuration. */ 1623 extern int bcm_port_encap_config_set( 1624 int unit, 1625 bcm_gport_t gport, 1626 bcm_port_encap_config_t *encap_config); 1627 1628 /* Set or get the link level encapsulation configuration. */ 1629 extern int bcm_port_encap_config_get( 1630 int unit, 1631 bcm_gport_t gport, 1632 bcm_port_encap_config_t *encap_config); 1633 1634 /* Set or get the link level encapsulation mode. */ 1635 extern int bcm_port_encap_set( 1636 int unit, 1637 bcm_port_t port, 1638 int mode); 1639 1640 /* Set or get the link level encapsulation mode. */ 1641 extern int bcm_port_encap_get( 1642 int unit, 1643 bcm_port_t port, 1644 int *mode); 1645 1646 /* 1647 * Get the current count of cells or packets queued on a port for 1648 * transmission. 1649 */ 1650 extern int bcm_port_queued_count_get( 1651 int unit, 1652 bcm_port_t port, 1653 uint32 *count); 1654 1655 #endif /* BCM_HIDE_DISPATCHABLE */ 1656 1657 /* bcm_port_frametype_t */ 1658 typedef int bcm_port_frametype_t; 1659 1660 /* Protocol based VLAN support. */ 1661 #define BCM_PORT_FRAMETYPE_ETHER2 0x1 1662 #define BCM_PORT_FRAMETYPE_8023 0x2 1663 #define BCM_PORT_FRAMETYPE_SNAP BCM_PORT_FRAMETYPE_8023 1664 #define BCM_PORT_FRAMETYPE_LLC 0x4 1665 #define BCM_PORT_FRAMETYPE_SNAP_PRIVATE 0x8 1666 1667 /* bcm_port_ethertype_t */ 1668 typedef bcm_ethertype_t bcm_port_ethertype_t; 1669 1670 /* Backplane multiplexing type */ 1671 typedef enum bcm_port_control_ability_e { 1672 BCM_PORT_ABILITY_SFI = 1, 1673 BCM_PORT_ABILITY_DUAL_SFI = 2, 1674 BCM_PORT_ABILITY_SCI = 3, 1675 BCM_PORT_ABILITY_SFI_SCI = 4, 1676 BCM_PORT_ABILITY_DUAL_SFI_LOCAL = 5, 1677 BCM_PORT_ABILITY_DUAL_SFI_LOOPBACK=BCM_PORT_ABILITY_DUAL_SFI_LOCAL, 1678 BCM_PORT_ABILITY_SFI_LOOPBACK = 6 1679 } bcm_port_control_ability_t; 1680 1681 /* PRBS Polynomial type */ 1682 typedef _shr_port_prbs_polynomial_t bcm_port_prbs_t; 1683 1684 #define BCM_PORT_PRBS_POLYNOMIAL_X7_X6_1 _SHR_PORT_PRBS_POLYNOMIAL_X7_X6_1 1685 #define BCM_PORT_PRBS_POLYNOMIAL_X15_X14_1 _SHR_PORT_PRBS_POLYNOMIAL_X15_X14_1 1686 #define BCM_PORT_PRBS_POLYNOMIAL_X23_X18_1 _SHR_PORT_PRBS_POLYNOMIAL_X23_X18_1 1687 #define BCM_PORT_PRBS_POLYNOMIAL_X31_X28_1 _SHR_PORT_PRBS_POLYNOMIAL_X31_X28_1 1688 #define BCM_PORT_PRBS_POLYNOMIAL_X9_X5_1 _SHR_PORT_PRBS_POLYNOMIAL_X9_X5_1 1689 #define BCM_PORT_PRBS_POLYNOMIAL_X11_X9_1 _SHR_PORT_PRBS_POLYNOMIAL_X11_X9_1 1690 #define BCM_PORT_PRBS_POLYNOMIAL_X58_X31_1 _SHR_PORT_PRBS_POLYNOMIAL_X58_X31_1 1691 #define BCM_PORT_PRBS_POLYNOMIAL_X49_X40_1 _SHR_PORT_PRBS_POLYNOMIAL_X49_X40_1 1692 #define BCM_PORT_PRBS_POLYNOMIAL_X20_X3_1 _SHR_PORT_PRBS_POLYNOMIAL_X20_X3_1 1693 #define BCM_PORT_PRBS_POLYNOMIAL_X13_X12_X2_1 _SHR_PORT_PRBS_POLYNOMIAL_X13_X12_X2_1 1694 #define BCM_PORT_PRBS_POLYNOMIAL_X20_X3_1 _SHR_PORT_PRBS_POLYNOMIAL_X20_X3_1 1695 #define BCM_PORT_PRBS_POLYNOMIAL_X10_X7_1 _SHR_PORT_PRBS_POLYNOMIAL_X10_X7_1 1696 #define BCM_PORT_PRBS_POLYNOMIAL_PAM4_13Q _SHR_PORT_PRBS_POLYNOMIAL_PAM4_13Q 1697 1698 /* PHY PCS mode */ 1699 typedef _shr_port_phy_pcs_mode_t bcm_port_phy_pcs_mode_t; 1700 1701 #define BCM_PORT_PHY_CONTROL_PCS_MODE_IEEE _SHR_PORT_PHY_CONTROL_PCS_MODE_IEEE 1702 #define BCM_PORT_PHY_CONTROL_PCS_MODE_BRCM _SHR_PORT_PHY_CONTROL_PCS_MODE_BRCM 1703 1704 /* Backward compatibility. */ 1705 #define bcm_port_untagged_protocol_vlan_add \ 1706 bcm_port_protocol_vlan_add 1707 #define bcm_port_untagged_protocol_vlan_delete \ 1708 bcm_port_protocol_vlan_delete 1709 #define bcm_port_untagged_protocol_vlan_delete_all \ 1710 bcm_port_protocol_vlan_delete_all 1711 1712 #ifndef BCM_HIDE_DISPATCHABLE 1713 1714 /* Add or delete a protocol-based VLAN. */ 1715 extern int bcm_port_protocol_vlan_add( 1716 int unit, 1717 bcm_port_t port, 1718 bcm_port_frametype_t frame, 1719 bcm_port_ethertype_t ether, 1720 bcm_vlan_t vid); 1721 1722 /* Add or delete a protocol-based VLAN. */ 1723 extern int bcm_port_protocol_vlan_delete( 1724 int unit, 1725 bcm_port_t port, 1726 bcm_port_frametype_t frame, 1727 bcm_port_ethertype_t ether); 1728 1729 /* Add or delete a protocol-based VLAN. */ 1730 extern int bcm_port_protocol_vlan_delete_all( 1731 int unit, 1732 bcm_port_t port); 1733 1734 /* Configure ports to block or allow packets from a given ingress port. */ 1735 extern int bcm_port_egress_set( 1736 int unit, 1737 bcm_port_t port, 1738 int modid, 1739 bcm_pbmp_t pbmp); 1740 1741 /* Configure ports to block or allow packets from a given ingress port. */ 1742 extern int bcm_port_egress_get( 1743 int unit, 1744 bcm_port_t port, 1745 int modid, 1746 bcm_pbmp_t *pbmp); 1747 1748 /* 1749 * Configure which egress ports a stacking port is permitted to forward 1750 * packets to. 1751 */ 1752 extern int bcm_port_modid_enable_set( 1753 int unit, 1754 bcm_port_t port, 1755 int modid, 1756 int enable); 1757 1758 /* 1759 * Configure which egress ports a stacking port is permitted to forward 1760 * packets to. 1761 */ 1762 extern int bcm_port_modid_enable_get( 1763 int unit, 1764 bcm_port_t port, 1765 int modid, 1766 int *enable); 1767 1768 /* 1769 * Configure which egress ports a stacking port is permitted to forward 1770 * packets to. 1771 */ 1772 extern int bcm_port_modid_egress_set( 1773 int unit, 1774 bcm_port_t port, 1775 bcm_module_t modid, 1776 bcm_pbmp_t pbmp); 1777 1778 /* 1779 * Configure which egress ports a stacking port is permitted to forward 1780 * packets to. 1781 */ 1782 extern int bcm_port_modid_egress_get( 1783 int unit, 1784 bcm_port_t port, 1785 bcm_module_t modid, 1786 bcm_pbmp_t *pbmp); 1787 1788 #endif /* BCM_HIDE_DISPATCHABLE */ 1789 1790 /* Flood blocking modes. */ 1791 #define BCM_PORT_FLOOD_BLOCK_BCAST 0x1 1792 #define BCM_PORT_FLOOD_BLOCK_UNKNOWN_UCAST 0x2 1793 #define BCM_PORT_FLOOD_BLOCK_UNKNOWN_MCAST 0x4 1794 #define BCM_PORT_FLOOD_BLOCK_ALL 0x8 1795 #define BCM_PORT_FLOOD_BLOCK_UNKNOWN_IP_MCAST 0x10 1796 #define BCM_PORT_FLOOD_BLOCK_UNKNOWN_NONIP_MCAST 0x20 1797 #define BCM_PORT_FLOOD_BLOCK_KNOWN_MCAST 0x40 1798 #define BCM_PORT_FLOOD_BLOCK_KNOWN_UCAST 0x80 1799 1800 #ifndef BCM_HIDE_DISPATCHABLE 1801 1802 /* Selectively block flooding traffic. */ 1803 extern int bcm_port_flood_block_set( 1804 int unit, 1805 bcm_port_t ingress_port, 1806 bcm_port_t egress_port, 1807 uint32 flags); 1808 1809 /* Selectively block flooding traffic. */ 1810 extern int bcm_port_flood_block_get( 1811 int unit, 1812 bcm_port_t ingress_port, 1813 bcm_port_t egress_port, 1814 uint32 *flags); 1815 1816 /* Configure a port for egress rate shaping. */ 1817 extern int bcm_port_rate_egress_set( 1818 int unit, 1819 bcm_port_t port, 1820 uint32 kbits_sec, 1821 uint32 kbits_burst); 1822 1823 /* Configure a port for egress rate shaping in packet mode. */ 1824 extern int bcm_port_rate_egress_pps_set( 1825 int unit, 1826 bcm_port_t port, 1827 uint32 pps, 1828 uint32 burst); 1829 1830 /* Configure a port for egress rate shaping. */ 1831 extern int bcm_port_rate_egress_get( 1832 int unit, 1833 bcm_port_t port, 1834 uint32 *kbits_sec, 1835 uint32 *kbits_burst); 1836 1837 /* Configure a port for egress rate shaping in packet mode. */ 1838 extern int bcm_port_rate_egress_pps_get( 1839 int unit, 1840 bcm_port_t port, 1841 uint32 *pps, 1842 uint32 *burst); 1843 1844 /* Configure a port for ingress rate policing. */ 1845 extern int bcm_port_rate_ingress_set( 1846 int unit, 1847 bcm_port_t port, 1848 uint32 kbits_sec, 1849 uint32 kbits_burst); 1850 1851 /* Configure a port for ingress rate policing. */ 1852 extern int bcm_port_rate_ingress_get( 1853 int unit, 1854 bcm_port_t port, 1855 uint32 *kbits_sec, 1856 uint32 *kbits_burst); 1857 1858 /* 1859 * Configure a port's ingress rate limiting pause frame control 1860 * parameters. 1861 */ 1862 extern int bcm_port_rate_pause_set( 1863 int unit, 1864 bcm_port_t port, 1865 uint32 kbits_pause, 1866 uint32 kbits_resume); 1867 1868 /* 1869 * Configure a port's ingress rate limiting pause frame control 1870 * parameters. 1871 */ 1872 extern int bcm_port_rate_pause_get( 1873 int unit, 1874 bcm_port_t port, 1875 uint32 *kbits_pause, 1876 uint32 *kbits_resume); 1877 1878 /* Control the sampling of packets ingressing or egressing a port. */ 1879 extern int bcm_port_sample_rate_set( 1880 int unit, 1881 bcm_port_t port, 1882 int ingress_rate, 1883 int egress_rate); 1884 1885 /* Control the sampling of packets ingressing or egressing a port. */ 1886 extern int bcm_port_sample_rate_get( 1887 int unit, 1888 bcm_port_t port, 1889 int *ingress_rate, 1890 int *egress_rate); 1891 1892 #endif /* BCM_HIDE_DISPATCHABLE */ 1893 1894 /* Double tagging modes. */ 1895 #define BCM_PORT_DTAG_MODE_NONE 0 /* No double tagging. */ 1896 #define BCM_PORT_DTAG_MODE_INTERNAL 1 /* Service Provider port. */ 1897 #define BCM_PORT_DTAG_MODE_EXTERNAL 2 /* Customer port. */ 1898 #define BCM_PORT_DTAG_REMOVE_EXTERNAL_TAG 4 /* Remove customer tag. */ 1899 #define BCM_PORT_DTAG_ADD_EXTERNAL_TAG 8 /* Add customer tag. */ 1900 #define BCM_PORT_DTAG_MODE_TRANSPARENT 16 /* Transparent port, all 1901 packets assume port's 1902 default VID. */ 1903 1904 #ifndef BCM_HIDE_DISPATCHABLE 1905 1906 /* Set or retrieve the current double tagging mode for a port. */ 1907 extern int bcm_port_dtag_mode_set( 1908 int unit, 1909 bcm_port_t port, 1910 int mode); 1911 1912 /* Set or retrieve the current double tagging mode for a port. */ 1913 extern int bcm_port_dtag_mode_get( 1914 int unit, 1915 bcm_port_t port, 1916 int *mode); 1917 1918 /* Set the default tag protocol ID (TPID) for the specified port. */ 1919 extern int bcm_port_tpid_set( 1920 int unit, 1921 bcm_port_t port, 1922 uint16 tpid); 1923 1924 /* Set the default tag protocol ID (TPID) for the specified port. */ 1925 extern int bcm_port_tpid_get( 1926 int unit, 1927 bcm_port_t port, 1928 uint16 *tpid); 1929 1930 /* Add an allowed outer tag protocol ID (TPID) for the specified port. */ 1931 extern int bcm_port_tpid_add( 1932 int unit, 1933 bcm_port_t port, 1934 uint16 tpid, 1935 int color_select); 1936 1937 /* Delete allowed outer tag protocol ID (TPID) for the specified port. */ 1938 extern int bcm_port_tpid_delete( 1939 int unit, 1940 bcm_port_t port, 1941 uint16 tpid); 1942 1943 /* Delete allowed outer tag protocol ID (TPID) for the specified port. */ 1944 extern int bcm_port_tpid_delete_all( 1945 int unit, 1946 bcm_port_t port); 1947 1948 /* 1949 * Set the default L2 tunnel payload tag protocol ID (TPID) for the 1950 * specified port. 1951 */ 1952 extern int bcm_port_l2_tunnel_payload_tpid_set( 1953 int unit, 1954 bcm_port_t port, 1955 uint16 tpid); 1956 1957 /* 1958 * Set the default L2 tunnel payload tag protocol ID (TPID) for the 1959 * specified port. 1960 */ 1961 extern int bcm_port_l2_tunnel_payload_tpid_get( 1962 int unit, 1963 bcm_port_t port, 1964 uint16 *tpid); 1965 1966 /* 1967 * Add an allowed L2 tunnel payload outer tag protocol ID (TPID) for the 1968 * specified port. 1969 */ 1970 extern int bcm_port_l2_tunnel_payload_tpid_add( 1971 int unit, 1972 bcm_port_t port, 1973 uint16 tpid, 1974 int color_select); 1975 1976 /* 1977 * Delete allowed L2 tunnel payload outer tag protocol ID (TPID) for the 1978 * specified port. 1979 */ 1980 extern int bcm_port_l2_tunnel_payload_tpid_delete( 1981 int unit, 1982 bcm_port_t port, 1983 uint16 tpid); 1984 1985 /* 1986 * Delete allowed L2 tunnel payload outer tag protocol ID (TPID) for the 1987 * specified port. 1988 */ 1989 extern int bcm_port_l2_tunnel_payload_tpid_delete_all( 1990 int unit, 1991 bcm_port_t port); 1992 1993 /* Set the default tag protocol ID (TPID) for the specified port. */ 1994 extern int bcm_port_inner_tpid_set( 1995 int unit, 1996 bcm_port_t port, 1997 uint16 tpid); 1998 1999 /* Set the default tag protocol ID (TPID) for the specified port. */ 2000 extern int bcm_port_inner_tpid_get( 2001 int unit, 2002 bcm_port_t port, 2003 uint16 *tpid); 2004 2005 #endif /* BCM_HIDE_DISPATCHABLE */ 2006 2007 /* Port TPID class flags. */ 2008 #define BCM_PORT_TPID_CLASS_OUTER_IS_PRIO 0x0001 /* Outer identified TPID 2009 is priority i.e, VLAN 2010 ID equals to zero */ 2011 #define BCM_PORT_TPID_CLASS_DISCARD 0x0002 /* Discard packet */ 2012 #define BCM_PORT_TPID_CLASS_OUTER_C 0x0004 /* Outer tag is customer 2013 tag */ 2014 #define BCM_PORT_TPID_CLASS_INNER_C 0x0008 /* Inner tag is customer 2015 tag */ 2016 #define BCM_PORT_TPID_CLASS_INGRESS_ONLY 0x0010 /* Ingress only */ 2017 #define BCM_PORT_TPID_CLASS_EGRESS_ONLY 0x0020 /* Egress only */ 2018 #define BCM_PORT_TPID_CLASS_OUTER_NOT_PRIO 0x0040 /* Outer identified TPID 2019 is not priority i.e, 2020 VLAN ID different than 2021 zero */ 2022 #define BCM_PORT_TPID_CLASS_NATIVE_EVE 0x0080 /* Native Egress vlan 2023 classification. */ 2024 #define BCM_PORT_TPID_CLASS_NATIVE_IVE 0x0100 /* Native Ingress vlan 2025 classification. */ 2026 #define BCM_PORT_TPID_CLASS_WITH_ID 0x0200 /* Create specified 2027 TAG-STRUCT SW-ID. */ 2028 #define BCM_PORT_TPID_CLASS_EGRESS_IP_TUNNEL 0x0400 /* Egress IP Tunnel vlan 2029 classification. */ 2030 2031 /* Special TPID values for Port TPID class configuration */ 2032 #define BCM_PORT_TPID_CLASS_TPID_INVALID 0xFFFFFFFF /* Value for invalid TPID 2033 in port TPID class 2034 configuration */ 2035 #define BCM_PORT_TPID_CLASS_TPID_ANY 0xFFFFFFFE /* Value for any TPID in 2036 port TPID class 2037 configuration */ 2038 2039 /* bcm_port_tag_format_class_t */ 2040 typedef uint16 bcm_port_tag_format_class_t; 2041 2042 /* VLAN tag structure type */ 2043 typedef enum bcm_port_tag_struct_type_e { 2044 bcmTagStructTypeUntag = 0, /* Type Untagged */ 2045 bcmTagStructTypeSTag = 1, /* Type S tag */ 2046 bcmTagStructTypeCTag = 2, /* Type C tag */ 2047 bcmTagStructTypeSCTag = 3, /* Type S C tag */ 2048 bcmTagStructTypeSPrioCTag = 4, /* Type S prio C tag */ 2049 bcmTagStructTypeSSTag = 5, /* Type S S tag */ 2050 bcmTagStructTypeCCTag = 6, /* Type C C tag */ 2051 bcmNofTagStructType = 7 /* Number of tag structure types */ 2052 } bcm_port_tag_struct_type_t; 2053 2054 typedef enum bcm_port_control_recycle_application_e { 2055 bcmPortControlRecycleAppDefault = 0, /* Default port settings according to 2056 header-type. */ 2057 bcmPortControlRecycleAppDropAndContinue = 1, /* Drop and Continue. */ 2058 bcmPortControlRecycleAppExtendedEncap = 2, /* Extended Encapsulation. */ 2059 bcmPortControlRecycleAppExtendedTerm = 3, /* Extended Termination. */ 2060 bcmPortControlRecycleAppReflector = 4, /* Reflector Application. */ 2061 bcmPortControlRecycleAppSbfdReflector = 5, /* SBFD Reflector Application. */ 2062 bcmPortControlRecycleAppBridgeFallback = 6, /* Bridge fallback. */ 2063 bcmPortControlRecycleAppExtendedEncapUncollapse = 7 /* Uncollapsed Extended Encapsulation, 2064 forwarding decision is done in 2nd 2065 pass */ 2066 } bcm_port_control_recycle_application_t; 2067 2068 /* bcm_port_tpid_class_s */ 2069 typedef struct bcm_port_tpid_class_s { 2070 uint32 flags; /* BCM_PORT_TPID_CLASS_XXX */ 2071 bcm_gport_t port; /* Port ID */ 2072 uint32 tpid1; /* First TPID value, -1 for invalid */ 2073 uint32 tpid2; /* Second TPID value, -1 for invalid */ 2074 bcm_port_tag_format_class_t tag_format_class_id; /* VLAN tag format ID */ 2075 int vlan_translation_action_id; /* Default translation action ID */ 2076 uint32 vlan_translation_qos_map_id; /* Default translation QoS map ID */ 2077 uint32 tpid_class_id; /* TPID profile. */ 2078 } bcm_port_tpid_class_t; 2079 2080 /* 2081 * Initialize a structure that holds both the key and the info for Port 2082 * TPID class configuration. 2083 */ 2084 extern void bcm_port_tpid_class_t_init( 2085 bcm_port_tpid_class_t *tpid_class); 2086 2087 #ifndef BCM_HIDE_DISPATCHABLE 2088 2089 /* 2090 * Set VLAN tag classification for a port. Set tag-classifier for given 2091 * identified TPIDs on packet. 2092 */ 2093 extern int bcm_port_tpid_class_set( 2094 int unit, 2095 bcm_port_tpid_class_t *tpid_class); 2096 2097 /* Get VLAN tag classification for a port. */ 2098 extern int bcm_port_tpid_class_get( 2099 int unit, 2100 bcm_port_tpid_class_t *tpid_class); 2101 2102 /* 2103 * Create/destroy a VLAN tag classification ID used to aggregate a group 2104 * of ports for further processing such as VLAN translation and field 2105 * processing. 2106 */ 2107 extern int bcm_port_tpid_class_create( 2108 int unit, 2109 uint32 flags, 2110 bcm_port_tag_struct_type_t tag_struct_type, 2111 bcm_port_tag_format_class_t *tag_format_class_id); 2112 2113 /* 2114 * Create/destroy a VLAN tag classification ID used to aggregate a group 2115 * of ports for further processing such as VLAN translation and field 2116 * processing. 2117 */ 2118 extern int bcm_port_tpid_class_destroy( 2119 int unit, 2120 uint32 flags, 2121 bcm_port_tag_format_class_t tag_format_class_id); 2122 2123 #endif /* BCM_HIDE_DISPATCHABLE */ 2124 2125 /* bcm_port_cable_state_t */ 2126 typedef _shr_port_cable_state_t bcm_port_cable_state_t; 2127 2128 #define BCM_PORT_CABLE_STATE_OK _SHR_PORT_CABLE_STATE_OK 2129 #define BCM_PORT_CABLE_STATE_OPEN _SHR_PORT_CABLE_STATE_OPEN 2130 #define BCM_PORT_CABLE_STATE_SHORT _SHR_PORT_CABLE_STATE_SHORT 2131 #define BCM_PORT_CABLE_STATE_OPENSHORT _SHR_PORT_CABLE_STATE_OPENSHORT 2132 #define BCM_PORT_CABLE_STATE_CROSSTALK _SHR_PORT_CABLE_STATE_CROSSTALK 2133 #define BCM_PORT_CABLE_STATE_UNKNOWN _SHR_PORT_CABLE_STATE_UNKNOWN 2134 #define BCM_PORT_CABLE_STATE_COUNT _SHR_PORT_CABLE_STATE_COUNT 2135 2136 /* bcm_port_cable_diag_t */ 2137 typedef _shr_port_cable_diag_t bcm_port_cable_diag_t; 2138 2139 #ifndef BCM_HIDE_DISPATCHABLE 2140 2141 /* Perform cable diagnostics on the specified port. */ 2142 extern int bcm_port_cable_diag( 2143 int unit, 2144 bcm_port_t port, 2145 bcm_port_cable_diag_t *status); 2146 2147 #endif /* BCM_HIDE_DISPATCHABLE */ 2148 2149 #define BCM_PORT_L3_MODIFY_NO_SRCMAC 0x0001 2150 #define BCM_PORT_L3_MODIFY_NO_DSTMAC 0x0002 2151 #define BCM_PORT_L3_MODIFY_NO_TTL 0x0004 2152 #define BCM_PORT_L3_MODIFY_NO_VLAN 0x0008 2153 2154 #ifndef BCM_HIDE_DISPATCHABLE 2155 2156 /* Get or set the L3 unicast packet modification operations of a port. */ 2157 extern int bcm_port_l3_modify_set( 2158 int unit, 2159 bcm_port_t port, 2160 uint32 flags); 2161 2162 /* Get or set the L3 unicast packet modification operations of a port. */ 2163 extern int bcm_port_l3_modify_get( 2164 int unit, 2165 bcm_port_t port, 2166 uint32 *flags); 2167 2168 #endif /* BCM_HIDE_DISPATCHABLE */ 2169 2170 #define BCM_PORT_IPMC_MODIFY_NO_SRCMAC 0x0001 2171 #define BCM_PORT_IPMC_MODIFY_NO_TTL 0x0004 2172 #define BCM_PORT_IPMC_CHECK_NO_TTL 0x0008 2173 2174 #ifndef BCM_HIDE_DISPATCHABLE 2175 2176 /* Get or set the L3 multicast packet modification operations of a port. */ 2177 extern int bcm_port_ipmc_modify_set( 2178 int unit, 2179 bcm_port_t port, 2180 uint32 flags); 2181 2182 /* Get or set the L3 multicast packet modification operations of a port. */ 2183 extern int bcm_port_ipmc_modify_get( 2184 int unit, 2185 bcm_port_t port, 2186 uint32 *flags); 2187 2188 #endif /* BCM_HIDE_DISPATCHABLE */ 2189 2190 /* 2191 * Port information valid fields 2192 * 2193 * Each field in the bcm_port_info_t structure has a corresponding mask 2194 * bit to control whether to get or set that value during the execution 2195 * of the bcm_port_selective_get/_set functions. The OR of all requested 2196 * ATTR masks should be stored in the action_mask field and the OR of all 2197 * requested ATTR2 masks should be stored in the action_mask2 field of 2198 * the bcm_port_info_t before calling the functions. 2199 */ 2200 #define BCM_PORT_ATTR_ENABLE_MASK 0x00000001 2201 #define BCM_PORT_ATTR_LINKSTAT_MASK 0x00000002 /* Get only. */ 2202 #define BCM_PORT_ATTR_AUTONEG_MASK 0x00000004 2203 #define BCM_PORT_ATTR_SPEED_MASK 0x00000008 2204 #define BCM_PORT_ATTR_DUPLEX_MASK 0x00000010 2205 #define BCM_PORT_ATTR_LINKSCAN_MASK 0x00000020 2206 #define BCM_PORT_ATTR_LEARN_MASK 0x00000040 2207 #define BCM_PORT_ATTR_DISCARD_MASK 0x00000080 2208 #define BCM_PORT_ATTR_VLANFILTER_MASK 0x00000100 2209 #define BCM_PORT_ATTR_UNTAG_PRI_MASK 0x00000200 2210 #define BCM_PORT_ATTR_UNTAG_VLAN_MASK 0x00000400 2211 #define BCM_PORT_ATTR_STP_STATE_MASK 0x00000800 2212 #define BCM_PORT_ATTR_PFM_MASK 0x00001000 2213 #define BCM_PORT_ATTR_LOOPBACK_MASK 0x00002000 2214 #define BCM_PORT_ATTR_PHY_MASTER_MASK 0x00004000 2215 #define BCM_PORT_ATTR_INTERFACE_MASK 0x00008000 2216 #define BCM_PORT_ATTR_PAUSE_TX_MASK 0x00010000 2217 #define BCM_PORT_ATTR_PAUSE_RX_MASK 0x00020000 2218 #define BCM_PORT_ATTR_PAUSE_MAC_MASK 0x00040000 2219 #define BCM_PORT_ATTR_LOCAL_ADVERT_MASK 0x00080000 2220 #define BCM_PORT_ATTR_REMOTE_ADVERT_MASK 0x00100000 /* Get only. */ 2221 #define BCM_PORT_ATTR_ENCAP_MASK 0x00200000 2222 #define BCM_PORT_ATTR_RATE_MCAST_MASK 0x00400000 2223 #define BCM_PORT_ATTR_RATE_BCAST_MASK 0x00800000 2224 #define BCM_PORT_ATTR_RATE_DLFBC_MASK 0x01000000 2225 #define BCM_PORT_ATTR_SPEED_MAX_MASK 0x02000000 /* Get only. */ 2226 #define BCM_PORT_ATTR_ABILITY_MASK 0x04000000 /* Get only. */ 2227 #define BCM_PORT_ATTR_FRAME_MAX_MASK 0x08000000 2228 #define BCM_PORT_ATTR_MDIX_MASK 0x10000000 2229 #define BCM_PORT_ATTR_MDIX_STATUS_MASK 0x20000000 2230 #define BCM_PORT_ATTR_MEDIUM_MASK 0x40000000 2231 #define BCM_PORT_ATTR_FAULT_MASK 0x80000000 /* Get only. */ 2232 #define BCM_PORT_ATTR2_PORT_ABILITY 0x00000001 2233 2234 /* Backward compatibility. */ 2235 #define BCM_PORT_ATTR_SPEED_MAX BCM_PORT_ATTR_SPEED_MAX_MASK 2236 #define BCM_PORT_ATTR_ABILITY BCM_PORT_ATTR_ABILITY_MASK 2237 2238 #define BCM_PORT_ATTR_ALL_MASK 0xffffffff 2239 #define BCM_PORT_ATTR_PAUSE_MASK \ 2240 (BCM_PORT_ATTR_PAUSE_TX_MASK | \ 2241 BCM_PORT_ATTR_PAUSE_RX_MASK) 2242 #define BCM_PORT_ATTR_RATE_MASK \ 2243 (BCM_PORT_ATTR_RATE_MCAST_MASK | \ 2244 BCM_PORT_ATTR_RATE_BCAST_MASK | \ 2245 BCM_PORT_ATTR_RATE_DLFBC_MASK) 2246 2247 /* Attributes that can be controlled on BCM5670/75. */ 2248 #define BCM_PORT_HERC_ATTRS \ 2249 (BCM_PORT_ATTR_ENABLE_MASK | \ 2250 BCM_PORT_ATTR_LINKSTAT_MASK | \ 2251 BCM_PORT_ATTR_SPEED_MASK | \ 2252 BCM_PORT_ATTR_DUPLEX_MASK | \ 2253 BCM_PORT_ATTR_LINKSCAN_MASK | \ 2254 BCM_PORT_ATTR_INTERFACE_MASK | \ 2255 BCM_PORT_ATTR_LOOPBACK_MASK | \ 2256 BCM_PORT_ATTR_PAUSE_TX_MASK | \ 2257 BCM_PORT_ATTR_PAUSE_RX_MASK | \ 2258 BCM_PORT_ATTR_PAUSE_MAC_MASK | \ 2259 BCM_PORT_ATTR_FRAME_MAX_MASK | \ 2260 BCM_PORT_ATTR_ENCAP_MASK) 2261 2262 /* Attributes specific to XGS devices. */ 2263 #define BCM_PORT_XGS_ATTRS (BCM_PORT_ATTR_ENCAP_MASK) 2264 2265 /* Auto-negotiated values. */ 2266 #define BCM_PORT_AN_ATTRS \ 2267 (BCM_PORT_ATTR_SPEED_MASK | \ 2268 BCM_PORT_ATTR_DUPLEX_MASK | \ 2269 BCM_PORT_ATTR_PAUSE_MASK) 2270 2271 /* bcm_port_info_s */ 2272 typedef struct bcm_port_info_s { 2273 uint32 action_mask; /* BCM_PORT_ATTR_xxx. */ 2274 uint32 action_mask2; /* BCM_PORT_ATTR2_xxx. */ 2275 int enable; 2276 int linkstatus; 2277 int autoneg; 2278 int speed; 2279 int duplex; 2280 int linkscan; 2281 uint32 learn; 2282 int discard; 2283 uint32 vlanfilter; 2284 int untagged_priority; 2285 bcm_vlan_t untagged_vlan; 2286 int stp_state; 2287 int pfm; 2288 int loopback; 2289 int phy_master; 2290 bcm_port_if_t interface; 2291 int pause_tx; 2292 int pause_rx; 2293 int encap_mode; 2294 bcm_mac_t pause_mac; 2295 bcm_port_abil_t local_advert; 2296 bcm_port_ability_t local_ability; 2297 int remote_advert_valid; 2298 bcm_port_abil_t remote_advert; 2299 bcm_port_ability_t remote_ability; 2300 int mcast_limit; 2301 int mcast_limit_enable; 2302 int bcast_limit; 2303 int bcast_limit_enable; 2304 int dlfbc_limit; 2305 int dlfbc_limit_enable; 2306 int speed_max; 2307 bcm_port_abil_t ability; 2308 bcm_port_ability_t port_ability; 2309 int frame_max; 2310 bcm_port_mdix_t mdix; 2311 bcm_port_mdix_status_t mdix_status; 2312 bcm_port_medium_t medium; 2313 uint32 fault; 2314 } bcm_port_info_t; 2315 2316 #ifndef BCM_HIDE_DISPATCHABLE 2317 2318 /* Get or set multiple port characteristics. */ 2319 extern int bcm_port_info_get( 2320 int unit, 2321 bcm_port_t port, 2322 bcm_port_info_t *info); 2323 2324 /* Get or set multiple port characteristics. */ 2325 extern int bcm_port_info_set( 2326 int unit, 2327 bcm_port_t port, 2328 bcm_port_info_t *info); 2329 2330 /* Get or set multiple port characteristics. */ 2331 extern int bcm_port_selective_get( 2332 int unit, 2333 bcm_port_t port, 2334 bcm_port_info_t *info); 2335 2336 /* Get or set multiple port characteristics. */ 2337 extern int bcm_port_selective_set( 2338 int unit, 2339 bcm_port_t port, 2340 bcm_port_info_t *info); 2341 2342 /* Get or set multiple port characteristics. */ 2343 extern int bcm_port_info_restore( 2344 int unit, 2345 bcm_port_t port, 2346 bcm_port_info_t *info); 2347 2348 /* Get or set multiple port characteristics. */ 2349 extern int bcm_port_info_save( 2350 int unit, 2351 bcm_port_t port, 2352 bcm_port_info_t *info); 2353 2354 /* Gets the physical driver name. */ 2355 extern int bcm_port_phy_drv_name_get( 2356 int unit, 2357 bcm_port_t port, 2358 char *name, 2359 int len); 2360 2361 #endif /* BCM_HIDE_DISPATCHABLE */ 2362 2363 /* Values for EPON port DBA Polling Intervals. */ 2364 #define BCM_PORT_PON_POLLING_INTERVALS 8 /* Number of DBA Polling 2365 Intervals. */ 2366 2367 /* bcm_port_pon_info_s */ 2368 typedef struct bcm_port_pon_info_s { 2369 int llid; 2370 int enable; 2371 int linkstatus; 2372 int oam_discovery_status; 2373 int loopback; 2374 bcm_mac_t olt_mac_addr; 2375 int polling_intervals[BCM_PORT_PON_POLLING_INTERVALS]; 2376 } bcm_port_pon_info_t; 2377 2378 #ifndef BCM_HIDE_DISPATCHABLE 2379 2380 /* Get or set multiple port characteristics for PON and link port. */ 2381 extern int bcm_port_pon_info_get( 2382 int unit, 2383 bcm_port_t pon_port, 2384 bcm_port_pon_info_t *info); 2385 2386 /* Get or set multiple port characteristics for PON and link port. */ 2387 extern int bcm_port_pon_info_set( 2388 int unit, 2389 bcm_port_t pon_port, 2390 bcm_port_pon_info_t *info); 2391 2392 #endif /* BCM_HIDE_DISPATCHABLE */ 2393 2394 /* Port link fault signalling. */ 2395 #define BCM_PORT_FAULT_LOCAL _SHR_PORT_FAULT_LOCAL 2396 #define BCM_PORT_FAULT_REMOTE _SHR_PORT_FAULT_REMOTE 2397 2398 /* 2399 * Port Rate Egress Traffic identifiers for QE FIFO Selectors into 2400 * Shapers. 2401 */ 2402 #define BCM_PORT_RATE_TRAFFIC_UC_EF 0x0001 2403 #define BCM_PORT_RATE_TRAFFIC_UC_NON_EF 0x0002 2404 #define BCM_PORT_RATE_TRAFFIC_NON_UC_EF 0x0200 2405 #define BCM_PORT_RATE_TRAFFIC_NON_UC_NON_EF 0x0100 2406 #define BCM_PORT_RATE_TRAFFIC_ALL 0x0303 2407 2408 #ifndef BCM_HIDE_DISPATCHABLE 2409 2410 /* Get link fault type. */ 2411 extern int bcm_port_fault_get( 2412 int unit, 2413 bcm_port_t port, 2414 uint32 *flags); 2415 2416 /* 2417 * Set or get port index of a trunk for ingress port that is used to 2418 * select the egress port in the trunk. 2419 */ 2420 extern int bcm_port_trunk_index_set( 2421 int unit, 2422 bcm_port_t port, 2423 int port_index); 2424 2425 /* 2426 * Set or get port index of a trunk for ingress port that is used to 2427 * select the egress port in the trunk. 2428 */ 2429 extern int bcm_port_trunk_index_get( 2430 int unit, 2431 bcm_port_t port, 2432 int *port_index); 2433 2434 /* Set or retrieve color assignment for a given port and priority. */ 2435 extern int bcm_port_priority_color_set( 2436 int unit, 2437 bcm_port_t port, 2438 int prio, 2439 bcm_color_t color); 2440 2441 /* Set or retrieve color assignment for a given port and priority. */ 2442 extern int bcm_port_priority_color_get( 2443 int unit, 2444 bcm_port_t port, 2445 int prio, 2446 bcm_color_t *color); 2447 2448 /* 2449 * Set or retrieve color assignment for a given port and Canonical Format 2450 * Indicator (CFI). 2451 */ 2452 extern int bcm_port_cfi_color_set( 2453 int unit, 2454 bcm_port_t port, 2455 int cfi, 2456 bcm_color_t color); 2457 2458 /* 2459 * Set or retrieve color assignment for a given port and Canonical Format 2460 * Indicator (CFI). 2461 */ 2462 extern int bcm_port_cfi_color_get( 2463 int unit, 2464 bcm_port_t port, 2465 int cfi, 2466 bcm_color_t *color); 2467 2468 /* 2469 * Map the incoming packet priority and CFI to internal priority and 2470 * color. 2471 */ 2472 extern int bcm_port_vlan_priority_map_set( 2473 int unit, 2474 bcm_port_t port, 2475 int pkt_pri, 2476 int cfi, 2477 int internal_pri, 2478 bcm_color_t color); 2479 2480 /* 2481 * Map the incoming packet priority and CFI to internal priority and 2482 * color. 2483 */ 2484 extern int bcm_port_vlan_priority_map_get( 2485 int unit, 2486 bcm_port_t port, 2487 int pkt_pri, 2488 int cfi, 2489 int *internal_pri, 2490 bcm_color_t *color); 2491 2492 /* 2493 * Map the internal priority and color to outgoing packet priority and 2494 * Canonical Format Indicator (CFI). 2495 */ 2496 extern int bcm_port_vlan_priority_unmap_set( 2497 int unit, 2498 bcm_port_t port, 2499 int internal_pri, 2500 bcm_color_t color, 2501 int pkt_pri, 2502 int cfi); 2503 2504 /* 2505 * Map the internal priority and color to outgoing packet priority and 2506 * Canonical Format Indicator (CFI). 2507 */ 2508 extern int bcm_port_vlan_priority_unmap_get( 2509 int unit, 2510 bcm_port_t port, 2511 int internal_pri, 2512 bcm_color_t color, 2513 int *pkt_pri, 2514 int *cfi); 2515 2516 /* 2517 * Map the incoming packet priority and CFI to internal priority and 2518 * color on a per-port per-vlan basis. 2519 */ 2520 extern int bcm_port_vlan_pri_map_set( 2521 int unit, 2522 bcm_port_t port, 2523 bcm_vlan_t vlan, 2524 int pkt_pri, 2525 int cfi, 2526 int internal_pri, 2527 bcm_color_t color); 2528 2529 /* 2530 * Get the mapping of incoming packet priority and CFI to internal 2531 * priority and color. 2532 */ 2533 extern int bcm_port_vlan_pri_map_get( 2534 int unit, 2535 bcm_port_t port, 2536 bcm_vlan_t vlan, 2537 int pkt_pri, 2538 int cfi, 2539 int *internal_pri, 2540 bcm_color_t *color); 2541 2542 /* Map the incoming IP packet DSCP to internal priority and color. */ 2543 extern int bcm_port_vlan_dscp_map_set( 2544 int unit, 2545 bcm_port_t port, 2546 bcm_vlan_t vlan, 2547 int dscp, 2548 int internal_pri, 2549 bcm_color_t color); 2550 2551 /* Map the incoming IP packet DSCP to internal priority and color. */ 2552 extern int bcm_port_vlan_dscp_map_get( 2553 int unit, 2554 bcm_port_t port, 2555 bcm_vlan_t vlan, 2556 int dscp, 2557 int *internal_pri, 2558 bcm_color_t *color); 2559 2560 /* Map the internal priority and color to outgoing packet DSCP. */ 2561 extern int bcm_port_dscp_unmap_set( 2562 int unit, 2563 bcm_port_t port, 2564 int internal_pri, 2565 bcm_color_t color, 2566 int pkt_dscp); 2567 2568 /* Map the internal priority and color to outgoing packet DSCP. */ 2569 extern int bcm_port_dscp_unmap_get( 2570 int unit, 2571 bcm_port_t port, 2572 int internal_pri, 2573 bcm_color_t color, 2574 int *pkt_dscp); 2575 2576 #endif /* BCM_HIDE_DISPATCHABLE */ 2577 2578 /* Initialize a Priority Mapping structure. */ 2579 extern void bcm_priority_mapping_t_init( 2580 bcm_priority_mapping_t *pri_map); 2581 2582 #ifndef BCM_HIDE_DISPATCHABLE 2583 2584 /* 2585 * Set the mapping of wire/packet PRI and CFI to internal priority and 2586 * color. 2587 */ 2588 extern int bcm_port_vlan_priority_mapping_set( 2589 int unit, 2590 bcm_port_t port, 2591 bcm_vlan_t vid, 2592 int pkt_pri, 2593 int cfi, 2594 bcm_priority_mapping_t *pri_map); 2595 2596 /* 2597 * Get the mapping of wire/packet PRI and CFI to internal priority and 2598 * color. 2599 */ 2600 extern int bcm_port_vlan_priority_mapping_get( 2601 int unit, 2602 bcm_port_t port, 2603 bcm_vlan_t vid, 2604 int pkt_pri, 2605 int cfi, 2606 bcm_priority_mapping_t *pri_map); 2607 2608 /* Set the inner tag value to be added to the outgoing packet. */ 2609 extern int bcm_port_vlan_inner_tag_set( 2610 int unit, 2611 bcm_port_t port, 2612 uint16 inner_tag); 2613 2614 /* Set the inner tag value to be added to the outgoing packet. */ 2615 extern int bcm_port_vlan_inner_tag_get( 2616 int unit, 2617 bcm_port_t port, 2618 uint16 *inner_tag); 2619 2620 /* Set or get egress override port. */ 2621 extern int bcm_port_force_forward_set( 2622 int unit, 2623 bcm_port_t port, 2624 bcm_port_t egr_port, 2625 int enable); 2626 2627 /* Set or get egress override port. */ 2628 extern int bcm_port_force_forward_get( 2629 int unit, 2630 bcm_port_t port, 2631 bcm_port_t *egr_port, 2632 int *enabled); 2633 2634 #endif /* BCM_HIDE_DISPATCHABLE */ 2635 2636 #define BCM_PORT_FORCE_FORWARD_DISABLE 0x0 /* Normal switching */ 2637 #define BCM_PORT_FORCE_FORWARD_ALL 0x1 /* Redirect all ingress port 2638 traffic to specified port */ 2639 #define BCM_PORT_FORCE_FORWARD_LOCAL 0x2 /* Redirect all ingress port 2640 traffic which would 2641 otherwise go to a local 2642 port to the specified port */ 2643 2644 #ifndef BCM_HIDE_DISPATCHABLE 2645 2646 /* Set or get egress override port mode. */ 2647 extern int bcm_port_force_forward_mode_set( 2648 int unit, 2649 bcm_port_t port, 2650 bcm_port_t egr_port, 2651 uint32 flags); 2652 2653 /* Set or get egress override port mode. */ 2654 extern int bcm_port_force_forward_mode_get( 2655 int unit, 2656 bcm_port_t port, 2657 bcm_port_t *egr_port, 2658 uint32 *flags); 2659 2660 /* 2661 * Get or set the destination of a packet (recycled-path) for the second 2662 * pass. 2663 */ 2664 extern int bcm_port_force_dest_set( 2665 int unit, 2666 bcm_gport_t gport, 2667 bcm_port_dest_info_t *dest_info); 2668 2669 /* 2670 * Get or set the destination of a packet (recycled-path) for the second 2671 * pass. 2672 */ 2673 extern int bcm_port_force_dest_get( 2674 int unit, 2675 bcm_gport_t gport, 2676 bcm_port_dest_info_t *dest_info); 2677 2678 #endif /* BCM_HIDE_DISPATCHABLE */ 2679 2680 /* bcm_port_class_e */ 2681 typedef enum bcm_port_class_e { 2682 bcmPortClassFieldLookup = 0, /* Class for field stage Lookup */ 2683 bcmPortClassFieldIngress = 1, /* Class for field stage Ingress */ 2684 bcmPortClassFieldEgress = 2, /* Class for field stage Egress */ 2685 bcmPortClassVlanTranslateEgress = 3, /* Class for egress VLAN translation */ 2686 bcmPortClassIngress = 4, /* Class for ingress basis grouping */ 2687 bcmPortClassId = 5, /* Class for mapping local-port to 2688 vlan-domain. vlan domain is used in 2689 mapping packet VID to Vlan */ 2690 bcmPortClassFieldIngressPacketProcessing = 6, /* Packet processing port Class lower 32 2691 bits for field stage Ingress */ 2692 bcmPortClassFieldEgressPacketProcessing = 7, /* Packet processing port Class for 2693 field stage Egress */ 2694 bcmPortClassL2Lookup = 8, /* Class for L2 lookup */ 2695 bcmPortClassForwardIngress = 9, /* Class for ingress forwarding */ 2696 bcmPortClassForwardEgress = 10, /* Class for egress forwarding */ 2697 bcmPortClassFieldIngressVlanTranslation = 11, /* Class for field stage Ingress Vlan 2698 Translation */ 2699 bcmPortClassFieldIngressTunnelTerminated = 12, /* Class for field stage Ingress Tunnel 2700 Terminated */ 2701 bcmPortClassProgramEditorEgressPacketProcessing = 13, /* Class for Egress Programmable Editor 2702 properties */ 2703 bcmPortClassEgress = 14, /* EGR_PORT class ID field for field 2704 stage Egress */ 2705 bcmPortClassFieldIngressGroupSel = 15, /* Per port Class ID for field stage 2706 Ingress group selection */ 2707 bcmPortClassFieldIngressSystemPort = 16, /* virtual port instance of SGLP in IFP 2708 IPBM key */ 2709 bcmPortClassFieldIngressSourceGport = 17, /* virtual port instance of SVP in IFP 2710 IPBM key */ 2711 bcmPortClassFieldIngressDevicePort = 18, /* virtual port instance of device port 2712 in IFP IPBM key */ 2713 bcmPortClassVlanTranslateIngress = 19, /* Class for ingress VLAN translation */ 2714 bcmPortClassProgramEditorEgressTrafficManagement = 20, /* Traffic management port Class for 2715 field stage Egress */ 2716 bcmPortClassFieldIngressPacketProcessingHigh = 21, /* Packet processing port Class high 32 2717 bits for field stage Ingress */ 2718 bcmPortClassVlanMember = 22, /* Class for VLAN Membership */ 2719 bcmPortClassFieldIngressVport = 23, /* Class for LIF encoded as Gport in the 2720 Field Ingres stages */ 2721 bcmPortClassFieldEgressVport = 24, /* Class for LIF encoded as Gport in the 2722 Field stage ePMF */ 2723 bcmPortClassFieldIngressPMF1PacketProcessingPort = 25, /* Class for packet processing port in 2724 Field stage iPMF1 */ 2725 bcmPortClassFieldIngressPMF1PacketProcessingPortCs = 26, /* Context selection class for packet 2726 processing port in Field stage iPMF1 */ 2727 bcmPortClassFieldIngressPMF3PacketProcessingPort = 27, /* Class for packet processing port in 2728 Field stage iPMF3 */ 2729 bcmPortClassFieldIngressPMF3PacketProcessingPortCs = 28, /* Context selection class for packet 2730 processing port in Field stage iPMF3 */ 2731 bcmPortClassFieldEgressPacketProcessingPort = 29, /* Class for packet processing port in 2732 Field stage ePMF */ 2733 bcmPortClassFieldEgressPacketProcessingPortCs = 30, /* Context selection class for packet 2734 processing port in Field stage ePMF */ 2735 bcmPortClassFieldExternalPacketProcessingPortCs = 31, /* Context selection class for packet 2736 processing port in Field stage 2737 external */ 2738 bcmPortClassFieldIngressPMF1TrafficManagementPort = 32, /* Class for traffic management port in 2739 Field stage iPMF1 */ 2740 bcmPortClassFieldIngressPMF1TrafficManagementPortCs = 33, /* Context selection class for traffic 2741 management port in Field stage iPMF1 */ 2742 bcmPortClassFieldIngressPMF3TrafficManagementPort = 34, /* Class for traffic management port in 2743 Field stage iPMF3 */ 2744 bcmPortClassFieldIngressPMF3TrafficManagementPortCs = 35, /* Context selection class for traffic 2745 management port in Field stage iPMF3 */ 2746 bcmPortClassFieldEgressTrafficManagementPort = 36, /* Class for traffic management 2747 processing port in Field stage ePMF */ 2748 bcmPortClassFieldExternalTrafficManagementPortCs = 37, /* Context selection class for traffic 2749 management port in Field stage 2750 external */ 2751 bcmPortClassFieldIngressPMF1PacketProcessingPortGeneralData = 38, /* Extra constant to assign to a packet 2752 processing port, up to 32lsb. Field 2753 stage iPMF1. */ 2754 bcmPortClassFieldIngressPMF1PacketProcessingPortGeneralDataHigh = 39, /* Extra constant to assign to a packet 2755 processing port, beyond the first 32 2756 bits. Field stage iPMF1. */ 2757 bcmPortClassFieldIngressPMF3PacketProcessingPortGeneralData = 40, /* Extra constant to assign to a packet 2758 processing port, first 32 bits. Field 2759 stage iPMF3. */ 2760 bcmPortClassFieldIngressPMF3PacketProcessingPortGeneralDataHigh = 41, /* Extra constant to assign to a packet 2761 processing port, beyond the first 32 2762 bits. Field stage iPMF3. */ 2763 bcmPortClassOpaqueCtrlId = 42, /* Opaque control ID available for IFP 2764 key selection */ 2765 bcmPortClassEgressOpaqueCtrlId = 43, /* Opaque control ID available for EFP 2766 key selection */ 2767 bcmPortClassOpaqueCtrlId1 = 44, /* Opaque control ID available for VFP 2768 key selection */ 2769 bcmPortClassOpaqueCtrlId2 = 45, /* Opaque control ID A for flex digest 2770 and VFP key selection. */ 2771 bcmPortClassOpaqueCtrlId3 = 46, /* Opaque control ID B for flex digest 2772 and VFP key selection. */ 2773 bcmPortClassCount = 47 /* Last enum value. */ 2774 } bcm_port_class_t; 2775 2776 #ifndef BCM_HIDE_DISPATCHABLE 2777 2778 /* 2779 * Set or get port classification ID to aggregate a group of ports for 2780 * further processing such as VLAN translation and field processing. 2781 */ 2782 extern int bcm_port_class_set( 2783 int unit, 2784 bcm_port_t port, 2785 bcm_port_class_t pclass, 2786 uint32 class_id); 2787 2788 /* 2789 * Set or get port classification ID to aggregate a group of ports for 2790 * further processing such as VLAN translation and field processing. 2791 */ 2792 extern int bcm_port_class_get( 2793 int unit, 2794 bcm_port_t port, 2795 bcm_port_class_t pclass, 2796 uint32 *class_id); 2797 2798 #endif /* BCM_HIDE_DISPATCHABLE */ 2799 2800 /* Features that can be controlled on a per-port basis. */ 2801 typedef enum bcm_port_control_e { 2802 bcmPortControlBridge = 0, /* Enable local port bridging. */ 2803 bcmPortControlTrunkHashSet = 1, /* Select one of the two sets of hash 2804 bits selection configuration for 2805 trunking. */ 2806 bcmPortControlFabricTrunkHashSet = 2, /* Select one of the two sets of hash 2807 bits selection configuration for 2808 fabric trunking. */ 2809 bcmPortControlECMPHashSet = 3, /* Select one of the two sets of hash 2810 bits selection configuration for 2811 ECMP. */ 2812 bcmPortControlLoadBalanceHashSet = 4, /* Select one of the two sets of hash 2813 bits selection configuration for LBID 2814 to be populated in HiGig2 header. */ 2815 bcmPortControlLoadBalancingNumber = 5, /* Assigns the Load Balancing Number of 2816 this port for HiGig2 headers. */ 2817 bcmPortControlErrorSymbolDetect = 6, /* Enable or disable XAUI |E| monitoring 2818 feature for port's XAUI lanes. */ 2819 bcmPortControlErrorSymbolCount = 7, /* Get the number of XAUI |E| symbol 2820 occured since last read. Setting any 2821 value to the count will set it to 2822 zero. */ 2823 bcmPortControlIP4 = 8, /* Enable IPv4 Routing on port. */ 2824 bcmPortControlIP6 = 9, /* Enable IPv6 Routing on port. */ 2825 bcmPortControlIP4Mcast = 10, /* Enable IPv4 Multicast on port. */ 2826 bcmPortControlIP6Mcast = 11, /* Enable IPv6 Multicast on port. */ 2827 bcmPortControlIP4McastL2 = 12, /* Enable L2 switching on IPv4 IPMC 2828 packets based on (SG,*G) instead of 2829 (DMAC,VLAN). */ 2830 bcmPortControlIP6McastL2 = 13, /* Enable L2 switching on IPv6 IPMC 2831 packets based on (SG,*G) instead of 2832 (DMAC,VLAN). */ 2833 bcmPortControlMpls = 14, /* Enable MPLS on the port ingress. */ 2834 bcmPortControlPassControlFrames = 15, /* Enable controls frames on port. */ 2835 bcmPortControlFilterLookup = 16, /* Enable port lookup Field Processor. */ 2836 bcmPortControlFilterIngress = 17, /* Enable ingress Field Processor on 2837 port. */ 2838 bcmPortControlFilterEgress = 18, /* Enable egress Field Processor on 2839 port. */ 2840 bcmPortControlFrameSpacingStretch = 19, /* One byte of inter packet gap is added 2841 for specified number of packet data 2842 bytes. If the value is 10, one byte 2843 of IPG is added for each 10 byte of 2844 packet data. */ 2845 bcmPortControlPreservePacketPriority = 20, /* Preserve packet original IEEE 802.1p 2846 priority. */ 2847 bcmPortControlLearnClassEnable = 21, /* Enable class based station movement 2848 checks. */ 2849 bcmPortControlTrustIncomingVlan = 22, /* Trust incoming packet's Vlan tag */ 2850 bcmPortControlDoNotCheckVlan = 23, /* Enable/disable spanning tree and Vlan 2851 membership checks on ingress Ethernet 2852 and higig packets. For CPU port 2853 configuration is applied only for 2854 higig packets. To configure these 2855 settings for Ethernet packets 2856 bcmPortControlDoNotCheckVlanFromCpu 2857 port control can be used. */ 2858 bcmPortControlDoNotCheckVlanFromCpu = 24, /* Enable/disable spanning tree and Vlan 2859 membership checks on Ethernet packets 2860 that are ingressed from CPU port. */ 2861 bcmPortControlIEEE8021ASEnableIngress = 25, /* Enable/disable ingress processing of 2862 IEEE 802.1AS protocol packets. */ 2863 bcmPortControlIEEE8021ASEnableEgress = 26, /* Enable/disable egress processing of 2864 IEEE 802.1AS protocol packets. */ 2865 bcmPortControlPrbsMode = 27, /* PRBS location - 0=>Phy PRBS 1=>MAC/SI 2866 Port */ 2867 bcmPortControlPrbsPolynomial = 28, /* Assigns PRBS polynomial, 2868 BCM_PORT_PRBS_POLYNOMIAL_ */ 2869 bcmPortControlPrbsTxInvertData = 29, /* Configure inversion of Tx data */ 2870 bcmPortControlPrbsForceTxError = 30, /* Configure insertion of Tx errors */ 2871 bcmPortControlPrbsTxEnable = 31, /* Enable Tx PRBS */ 2872 bcmPortControlPrbsRxEnable = 32, /* Enable Rx PRBS */ 2873 bcmPortControlPrbsRxStatus = 33, /* PRBS Rx status */ 2874 bcmPortControlSerdesDriverStrength = 34, /* Assigns Driver Strength */ 2875 bcmPortControlSerdesDriverEqualization = 35, /* Assigns Driver Equalization */ 2876 bcmPortControlSerdesDriverEqualizationFarEnd = 36, /* Informs software of far end transmit 2877 driver equalization setting for 2878 tuning */ 2879 bcmPortControlSerdesDriverTune = 37, /* Start hardware receive equalization 2880 tuning */ 2881 bcmPortControlSerdesDriverEqualizationTuneStatusFarEnd = 38, /* Get results of tune operation which 2882 include suggested far end 2883 equalization update */ 2884 bcmPortControlAbility = 39, /* Assigns Port ability, 2885 BCM_PORT_ABILITY_ */ 2886 bcmPortControlMacInMac = 40, /* Enable/Disable MiM frame processing */ 2887 bcmPortControlSrcBmacMissToCpu = 41, /* Mac-in-Mac Source BMAC lookup miss, 2888 Send to CPU (value = TRUE/FALSE) */ 2889 bcmPortControlOamLoopback = 42, /* Enable/Disable 802.3 Clause 57 Oam 2890 Loopback */ 2891 bcmPortControlEgressVlanPriUsesPktPri = 43, /* If set, outgoing packets derive their 2892 priority from the incoming priority */ 2893 bcmPortControlPacketFlowMode = 45, /* Enable/Disable requeue for hybrid 2894 mode */ 2895 bcmPortControlTrain = 46, /* Start/stop training sequence */ 2896 bcmPortControlRxEnable = 47, /* Rx enable/disable */ 2897 bcmPortControlTxEnable = 48, /* Tx enable/disable */ 2898 bcmPortControlRxLink = 49, /* Retreives Rx Status */ 2899 bcmPortControlTxLink = 50, /* Retreives Tx Status */ 2900 bcmPortControlIpfixRate = 51, /* Set IPFIX flow rate meter id */ 2901 bcmPortControlOAMEnable = 52, /* Enable reception of OAM messages */ 2902 bcmPortControlCustomerQueuing = 53, /* Enable customer domain queuing */ 2903 bcmPortControlFabricKnockoutId = 54, /* sets port identifier, used for source 2904 knockout functionality */ 2905 bcmPortControlLanes = 55, /* Sets the number of active lanes for a 2906 port that can be dynamically 2907 hot-swapped. */ 2908 bcmPortControlEgressNonUnicastLossless = 56, /* Enable/Disable multicast Lossless 2909 operation */ 2910 bcmPortControlPFCEthertype = 57, /* Priority Flow Control packet 2911 EtherType */ 2912 bcmPortControlPFCOpcode = 58, /* Priority Flow Control packet opcode */ 2913 bcmPortControlPFCReceive = 59, /* Priority Flow Control packet receive 2914 enable */ 2915 bcmPortControlPFCTransmit = 60, /* Priority Flow Control packet transmit 2916 enable */ 2917 bcmPortControlPFCClasses = 61, /* Priority Flow Control number of 2918 classes */ 2919 bcmPortControlPFCPassFrames = 62, /* Allow Priority Flow Control packets 2920 into switch device */ 2921 bcmPortControlPFCDestMacOui = 63, /* Priority Flow Control packet 2922 destination MAC address, upper three 2923 bytes */ 2924 bcmPortControlPFCDestMacNonOui = 64, /* Priority Flow Control packet 2925 destination MAC address, lower three 2926 bytes */ 2927 bcmPortControlPFCRefreshTime = 65, /* Priority Flow Control refresh time */ 2928 bcmPortControlVrf = 66, /* Enable per-port VRF to override 2929 per-Vlan VRF */ 2930 bcmPortControlL3Ingress = 67, /* Enable per-port L3-IIF for IP traffic */ 2931 bcmPortControlL2Learn = 69, /* Configure L2 learning behavior using 2932 BCM_PORT_LEARN_xxx flags */ 2933 bcmPortControlL2Move = 70, /* Configure L2 station movement 2934 behavior using BCM_PORT_LEARN_xxx 2935 flags */ 2936 bcmPortControlForwardStaticL2MovePkt = 71, /* Allow forwarding L2 packet even if L2 2937 movement is detected against an 2938 existing static entry in L2 table */ 2939 bcmPortControlLinkFaultLocalEnable = 72, /* Enable local LSS message processing */ 2940 bcmPortControlLinkFaultRemoteEnable = 73, /* Enable remote LSS message processing */ 2941 bcmPortControlLinkFaultLocal = 74, /* Read local LSS message processing 2942 status */ 2943 bcmPortControlLinkFaultRemote = 75, /* Read remote LSS message processing 2944 status */ 2945 bcmPortControlTimestampTransmit = 76, /* Read the timestamp value assigned to 2946 TX packet */ 2947 bcmPortControlTimestampEnable = 77, /* Set the port to be capable of 2948 timestamping TX packet */ 2949 bcmPortControlTCPriority = 78, /* Indicates the default Traffic Class 2950 attributes assoiated with the port */ 2951 bcmPortControlDropPrecedence = 79, /* Indicates the default Drop Precedence 2952 attributes assoiated with the port */ 2953 bcmPortControlFabricQueue = 80, /* Enable ext header on HiGig port. */ 2954 bcmPortControlLinkdownTransmit = 81, /* Enable transmission when linkdown */ 2955 bcmPortControlEEETransmitWakeTime = 82, /* Time(in microsecs) to wait before 2956 transmitter can begin transmitting 2957 leaving Low Power Idle State */ 2958 bcmPortControlEEEReceiveWakeTime = 83, /* Time(in microsecs) Receiver counts 2959 for SLEEP or IDLE symbols to move to 2960 Active from Low Power Idle State */ 2961 bcmPortControlEEETransmitSleepTime = 84, /* Time(in microsecs) Tranmitter sends 2962 SLEEP symbols before going to QUIET 2963 state */ 2964 bcmPortControlEEEReceiveSleepTime = 85, /* Time(in microsecs) Receiver is in 2965 SLEEP state before entering QUIET 2966 state */ 2967 bcmPortControlEEETransmitQuietTime = 86, /* Time(in microsecs) transmit stays in 2968 Quiet state before entering REFRESH 2969 state */ 2970 bcmPortControlEEEReceiveQuietTime = 87, /* Time(in microsecs) Receiver stays in 2971 Quiet state before it expects REFRESH 2972 signal */ 2973 bcmPortControlEEETransmitRefreshTime = 88, /* Time(in microsecs) transmitter stays 2974 in Refresh state */ 2975 bcmPortControlSerdesTuneMarginMax = 89, /* SerDes max tune margin value */ 2976 bcmPortControlSerdesTuneMarginMode = 90, /* SerDes in tune margin mode */ 2977 bcmPortControlSerdesTuneMarginValue = 91, /* Value used to measure tune margin */ 2978 bcmPortControlStatOversize = 92, /* Threshold above which packet will be 2979 counted as oversized */ 2980 bcmPortControlStatOversizeIsError = 93, /* Oversize Threshold flag to control 2981 oversize packets as error counts */ 2982 bcmPortControlEEEEnable = 94, /* Enable/Disable Energy Efficient 2983 Ethernet */ 2984 bcmPortControlEEEStatisticsClear = 95, /* Clear Energy Efficient Ethernet Low 2985 Power Idle Statistics */ 2986 bcmPortControlEEETransmitIdleTime = 96, /* Time (in microsecs) for which 2987 condition to move to LPI state is 2988 satisfied, at the end of which MAC 2989 transitions to LPI state */ 2990 bcmPortControlEEETransmitEventCount = 97, /* Number of time MAC TX enters LPI 2991 state for a given measurement 2992 interval */ 2993 bcmPortControlEEETransmitDuration = 98, /* Time (in microseconds) for which MAC 2994 TX is in LPI state during a 2995 measurement interval */ 2996 bcmPortControlEEEReceiveEventCount = 99, /* Number of time MAC RX enters LPI 2997 state for a given measurement 2998 interval */ 2999 bcmPortControlEEEReceiveDuration = 100, /* Time (in microseconds) for which MAC 3000 RX is in LPI state during a 3001 measurement interval */ 3002 bcmPortControlEEETransmitIdleTimeHund = 101, /* The same as 3003 PortControlEEETransmitIdleTime for 3004 the link speed at 100MB data rate */ 3005 bcmPortControlEEETransmitWakeTimeHund = 102, /* The same as 3006 PortControlEEETransmitWakeTime for 3007 the link speed at 100MB data rate */ 3008 bcmPortControlEEETransmitMinLPITime = 103, /* Time (in microseconds) MAC stay in 3009 LPI state before leaving it */ 3010 bcmPortControlEEETransmitMinLPITimeHund = 104, /* The same as 3011 PortControlEEETransmitMinLPITime for 3012 the link speed at 100MB data rate */ 3013 bcmPortControlNivAccessVirtualInterfaceId = 105, /* Source virtual interface identifier 3014 (value range 0-0xfff) */ 3015 bcmPortControlNivNonVntagDrop = 106, /* Set Ingress drop control, if VNTAG is 3016 not present (value = TRUE/FALSE) */ 3017 bcmPortControlNivVntagDrop = 107, /* Set Ingress drop control, if VNTAG is 3018 present (value = TRUE/FALSE) */ 3019 bcmPortControlNivNonVntagAdd = 108, /* Set ADD tag action, when VNTAG is not 3020 present(value = TRUE/FALSE) */ 3021 bcmPortControlNivVntagIngressReplace = 109, /* Set REPLACE Ingress tag action, when 3022 VNTAG is present (value = TRUE/FALSE) */ 3023 bcmPortControlNivVntagEgressReplace = 110, /* Set REPLACE Egress tag action, when 3024 VNTAG is present (value = TRUE/FALSE) */ 3025 bcmPortControlNivVntagIngressDelete = 111, /* Set DELETE Ingress tag action, when 3026 VNTAG is present (value = TRUE/FALSE) */ 3027 bcmPortControlNivVntagEgressDelete = 112, /* Set DELETE Egress tag action, when 3028 VNTAG is present (value = TRUE/FALSE) */ 3029 bcmPortControlNivRpfCheck = 113, /* Set incoming packet VNTAG.SRC_VIF RPF 3030 check control (value = TRUE/FALSE) */ 3031 bcmPortControlNivSourceKnockout = 114, /* Set outgoing packet NIV pruning check 3032 control (value = TRUE/FALSE) */ 3033 bcmPortControlNivForwardPort = 115, /* Set destination port for forwarding - 3034 mainly for upstream traffic only, but 3035 use -1 as special to flag the port as 3036 uplink port (value = local port 3037 number or -1) */ 3038 bcmPortControlNivType = 116, /* Set NIV port type (enumerated value 3039 within bcm_port_niv_type_t) */ 3040 bcmPortControlNivNameSpace = 117, /* Set namespace value (value range 3041 0-0xfff) */ 3042 bcmPortControlRemoteCpuEnable = 118, /* Enables the port to accept packets 3043 from Remote CPU */ 3044 bcmPortControlRemoteCpuTcMapping = 119, /* Enable/Disable the mapping between TC 3045 and COS queue for received ToCPU 3046 packets */ 3047 bcmPortControlArbiterActive = 120, /* Indicates if the SCI link is active 3048 and its arbiter association. -1 3049 indicates disabled, 0 indicates 3050 active and associted with Arbiter 0, 3051 1 indicates active and associated 3052 with Arbiter 1 */ 3053 bcmPortControlArbiterForceDown = 121, /* Status to be indicated to arbiter. 3054 TRUE forces Down, FALSE does not 3055 force down */ 3056 bcmPortControlTrill = 123, /* Enable/Disable TRILL frame processing 3057 (value = TRUE/FALSE) */ 3058 bcmPortControlTrillAllow = 124, /* Allow TRILL frames (value = 3059 TRUE/FALSE) */ 3060 bcmPortControlNonTrillAllow = 125, /* Allow Non-TRILL frames (value = 3061 TRUE/FALSE) */ 3062 bcmPortControlTrillCoreISISToCPU = 126, /* Core IS-IS frames received, Send to 3063 CPU (value = TRUE/FALSE) */ 3064 bcmPortControlTrillHashSelect = 127, /* Select one of 2 sets of configuration 3065 for TRILL ECMP hashing (value = 1/0 ) */ 3066 bcmPortControlFabricHeaderFormat = 128, /* Select appropriate fabric header 3067 type. */ 3068 bcmPortControlFabricSourceKnockout = 130, /* Disables packet forwarding to 3069 non-trunk port on local modid */ 3070 bcmPortControlFaultResponseLocalDataAndIdle = 131, /* If Local Fault indicated, continue 3071 sending data, send Idles */ 3072 bcmPortControlFaultResponseLocalDataAndRf = 132, /* If Local Fault indicated, continue 3073 sending data, send Remote Fault 3074 Indication */ 3075 bcmPortControlFaultResponseLocalDataAndLf = 133, /* If Local Fault indicated, continue 3076 sending data, send Local Fault 3077 Indication */ 3078 bcmPortControlFaultResponseLocalNoDataIdle = 134, /* If Local Fault indicated, stop 3079 sending data, send Idles */ 3080 bcmPortControlFaultResponseLocalNoDataRf = 135, /* If Local Fault indicated, stop 3081 sending data, send Remote Fault 3082 Indication */ 3083 bcmPortControlFaultResponseLocalNoDataLf = 136, /* If Local Fault indicated, stop 3084 sending data, send Local Fault 3085 Indication */ 3086 bcmPortControlFaultResponseRemoteDataAndIdle = 137, /* If Remote Fault indicated, continue 3087 sending data, send Idles */ 3088 bcmPortControlFaultResponseRemoteDataAndRf = 138, /* If Remote Fault indicated, continue 3089 sending data, send Remote Fault 3090 Indication */ 3091 bcmPortControlFaultResponseRemoteDataAndLf = 139, /* If Remote Fault indicated, continue 3092 sending data, send Remote Fault 3093 Indication */ 3094 bcmPortControlFaultResponseRemoteNoDataIdle = 140, /* If Remote Fault indicated, stop 3095 sending data, send Idles */ 3096 bcmPortControlFaultResponseRemoteNoDataRf = 141, /* If Remote Fault indicated, stop 3097 sending data, send Remote Fault 3098 Indication */ 3099 bcmPortControlFaultResponseRemoteNoDataLf = 142, /* If Remote Fault indicated, stop 3100 sending data, send Remote Fault 3101 Indication */ 3102 bcmPortControlPCS = 143, /* The Physical Coding Sub-layer of the 3103 port */ 3104 bcmPortControlLinkDownPowerOn = 144, /* 0: The Link is disabled on the MAC 3105 level, the SerDes power-state is not 3106 changed 1: Activate the link on the 3107 MAC level, the SerDes power-state is 3108 not changed */ 3109 bcmPortControlRegex = 145, /* Enable/Disable tracking of IPv4 flows */ 3110 bcmPortControlRegexTcp = 146, /* Enable/Disable tracking of IPv6 flows */ 3111 bcmPortControlRegexUdp = 147, /* Enable/Disable tracking of IPv4 UDP 3112 flows */ 3113 bcmPortControlPonEncryptKeyExpiryTime = 148, /* Set timeout value for encryption keys 3114 (s) */ 3115 bcmPortControlPonHoldoverState = 149, /* Enable holdover state */ 3116 bcmPortControlPonHoldoverTime = 150, /* Set holdover time (ms) */ 3117 bcmPortControlPonMultiLlid = 151, /* Set LLID number */ 3118 bcmPortControlPonFecMode = 152, /* Set FEC mode on Rx and Tx together, 3119 Rx/Tx off (value = 0), Rx on and Tx 3120 off (value = 1), Rx off and Tx on 3121 (value = 2), Rx/Tx on (value = 3) or 3122 FEC is settable per link (value = 4) */ 3123 bcmPortControlPonUserTraffic = 153, /* Enable user traffic */ 3124 bcmPortControlEthPortAutoNegFailureAlarmState = 154, /* Alarm on/off state of the 3125 EthPortAutoNegFailure */ 3126 bcmPortControlEthPortLosAlarmState = 155, /* Alarm on/off state of the EthPortLos */ 3127 bcmPortControlEthPortFailureAlarmState = 156, /* Alarm on/off state of the 3128 EthPortFailure */ 3129 bcmPortControlEthPortLoopbackAlarmState = 157, /* Alarm on/off state of the 3130 EthPortLoopback */ 3131 bcmPortControlEthPortCongestionAlarmState = 158, /* Alarm on/off state of the 3132 EthPortCongestion */ 3133 bcmPortControlMplsEntropyHashSet = 159, /* Select one of 2 sets of configuration 3134 for MPLS Entropy hashing (value = 3135 1/0) */ 3136 bcmPortControlStripCRC = 160, /* If set no cell CRC is calculated, 3137 else 8-bit CRC will be added to each 3138 data cell. Relevant for VSC256 mode 3139 only. */ 3140 bcmPortControlPrivateVlanIsolate = 161, /* Argument = 1/0. Enable, disable 3141 system port being port isolate type. 3142 By default port will be community. */ 3143 bcmPortControlPrivateVlanModeSet = bcmPortControlPrivateVlanIsolate, /* Argument = 2/1/0. Set system port 3144 private vlan mode (0 : community, 1 : 3145 isolate, 2 : promiscuous). By 3146 default it is community. */ 3147 bcmPortControlFloodUnknownUcastGroup = 162, /* Override the per-vsi settings. */ 3148 bcmPortControlFloodUnknownMcastGroup = 163, /* Override the per-vsi settings. */ 3149 bcmPortControlFloodBroadcastGroup = 164, /* Override the per-vsi settings. */ 3150 bcmPortControlDefaultQueue = 165, /* Specify default queue ID for use with 3151 the port */ 3152 bcmPortControlL2GreEnable = 166, /* Set per port enable for L2-GRE 3153 (Value=TRUE/FALSE) */ 3154 bcmPortControlL2GreTunnelbasedVpnId = 167, /* Set per port VPNID lookup key 3155 (Value=TRUE/FALSE) */ 3156 bcmPortControlL2GreDefaultTunnelEnable = 168, /* Set per port dafult-SVP for Tunnel 3157 lookup failure(Value=TRUE/FALSE) */ 3158 bcmPortControlL2SaAuthenticaion = 169, /* to enable SA authentication check on 3159 a port */ 3160 bcmPortControlUnknownMacDaAction = 170, /* Per port configures set of actions 3161 that are taken by the device when an 3162 unknown destination address is 3163 recognized on an ingressing packet */ 3164 bcmPortControlDiscardMacSaAction = 171, /* Per port configures set of actions 3165 that are taken by the device upon SA 3166 lookup when L2 entry flag with 3167 SA-discard */ 3168 bcmPortControlManagementPacketIp6Reserved = 172, /* Classify Packets with IPV6 multicast 3169 reserved address FF0X:0:0:0:0:0:0:0 3170 on a port as management frames */ 3171 bcmPortControlManagementPacketIp4Reserved = 173, /* Classify Packets with IPV4 multicast 3172 reserved address 224.0.0.x on a port 3173 as management frames */ 3174 bcmPortControlManagementPacketLinkConstrained = 174, /* Classify Packets with 3175 link-constrained multicast range 3176 DMAC=01-80-C2-00-00-0x as management 3177 frames */ 3178 bcmPortControlManagementPacketGarp = 175, /* Classify Packets with DA range 3179 0x0180c2000020 through 0x0180c200002f 3180 as management frames */ 3181 bcmPortControlManagementPacketCos = 176, /* COS assignment for Management Packets */ 3182 bcmPortControlManagementPacketColor = 177, /* Drop Precedence for Management 3183 Packets */ 3184 bcmPortControlTaggedL3PacketPktPri = 178, /* Set packet Priority source for tagged 3185 L3 packets (enumerated value within 3186 bcm_port_cos_remap_t) */ 3187 bcmPortControlTaggedMPLSPacketPktPri = 179, /* Set packet Priority source for tagged 3188 MPLS packets (enumerated value within 3189 bcm_port_cos_remap_t) */ 3190 bcmPortControlTaggedMPLSL3PacketPktPri = 180, /* Set packet Priority source for tagged 3191 MPLS L3 packets (enumerated value 3192 within bcm_port_cos_remap_t) */ 3193 bcmPortControlEEEEventCountSymmetric = 181, /* Operate EEE counter in symmetric 3194 mode, where TX and RX counters 3195 increment together */ 3196 bcmPortControlEEELinkActiveDuration = 182, /* Time(in microsecs) to wait before EEE 3197 transitions to Active state after 3198 link status becomes active */ 3199 bcmPortControlEsmEligibility = 183, /* Indicates if ESM search is enabled 3200 for packets coming in on this port */ 3201 bcmPortControlTrillDesignatedVlan = 184, /* VLAN which carries Trill packets 3202 between RBridges */ 3203 bcmPortControlMplsFRREnable = 185, /* Enable or disable FRR on MPLS 3204 packets. */ 3205 bcmPortControlMplsContextSpecificLabelEnable = 186, /* Enable or disable Upstream assignment 3206 label on MPLS packets. */ 3207 bcmPortControlVxlanEnable = 187, /* Set per port enable for VXLAN 3208 (Value=TRUE/FALSE) */ 3209 bcmPortControlVxlanTunnelbasedVnId = 188, /* Set per port VNID lookup key 3210 (Value=TRUE/FALSE) */ 3211 bcmPortControlVxlanDefaultTunnelEnable = 189, /* Set per port dafult-SVP for Tunnel 3212 lookup failure(Value=TRUE/FALSE) */ 3213 bcmPortControlFieldEgressClassSelect = 190, /* Select Class Id to pass to EFP */ 3214 bcmPortControlPonMpcpDiscoveryRate = 191, /* EPON Port MPCP Discovery rate in 3215 miliseconds. */ 3216 bcmPortControlPonMpcpDiscoveryGrantLength = 192, /* EPON Port MPCP Discovery Grant length 3217 in bytes. */ 3218 bcmPortControlPonMpcpOneRegistrationPerGrant = 193, /* Allow only one registration per grant */ 3219 bcmPortControlPonOamHeartbeatRate = 194, /* EPON port OAM heartbeat rate in 3220 seconds */ 3221 bcmPortControlPonMaxLinks = 195, /* EPON port maximum number of links */ 3222 bcmPortControlPonRamanMitigationMode = 196, /* EPON port Raman Mitigation mode */ 3223 bcmPortControlPonLoopTimeMinPropDelay = 197, /* EPON Loop Timing Minimum Propagation 3224 Delay */ 3225 bcmPortControlPonLoopTimeMaxPropDelay = 198, /* EPON Loop Timing Maximum Propagation 3226 Delay */ 3227 bcmPortControlPonLoopTimeOnuDelay = 199, /* EPON Loop Timing Onu Delay */ 3228 bcmPortControlPonLoopTimeNullGrantSize = 200, /* EPON Loop Timing Null Grant size */ 3229 bcmPortControlPonLoopTimeOltDelay = 201, /* EPON Loop Timing OLT delay */ 3230 bcmPortControlPonSfecAllowedBitErrors = 202, /* EPON SFEC Allowed bit errors */ 3231 bcmPortControlPonTfecAllowedBitErrors = 203, /* EPON TFEC Allowed bit errors */ 3232 bcmPortControlPonFecRxBypass = 204, /* Rx FEC Bypass mode */ 3233 bcmPortControlPonSyncTime = 205, /* EPON Sync Time in 16ns(TQ) unit */ 3234 bcmPortControlPonEncryptionMode = 206, /* EPON encryption mode (0 : None, 1 : 3235 AE, 2 : CTC, 3 : Zero-overhead AE). */ 3236 bcmPortControlPonEncryptionDirection = 207, /* EPON encryption direction (1 : 3237 downstream only, 2 : bi-direction). */ 3238 bcmPortControlPonOamKeyExchangeMsgBypass = 208, /* Bypass processing Key Exchange OAM 3239 from Pon port */ 3240 bcmPortControlTunnelIdIngressSource = 209, /* Move outermost VLAN tag to Tunnel ID 3241 on ingress */ 3242 bcmPortControlTunnelIdEgressAdd = 210, /* Add outermost VLAN tag as Tunnel ID 3243 on egress */ 3244 bcmPortControlPonOamHeartbeatTimeout = 211, /* EPON Oam heartbeat timeout in sec 3245 unit */ 3246 bcmPortControlPonMpcpReportTimeout = 212, /* EPON report timeout in ms unit */ 3247 bcmPortControlPon1GDiscoveryWindow = 213, /* Enable 1G discovery window */ 3248 bcmPortControlPon10GDiscoveryWindow = 214, /* Enable 10G discovery window */ 3249 bcmPortControlExtendedPortVid = 215, /* Extended port VID (value range 3250 0-0xfff) */ 3251 bcmPortControlNonEtagDrop = 216, /* Set Ingress drop control, if ETAG is 3252 not present (value = TRUE/FALSE) */ 3253 bcmPortControlEtagDrop = 217, /* Set Ingress drop control, if ETAG is 3254 present (value = TRUE/FALSE) */ 3255 bcmPortControlNonEtagAdd = 218, /* Set ADD tag action, when ETAG is not 3256 present (value = TRUE/FALSE) */ 3257 bcmPortControlEtagIngressReplace = 219, /* Set REPLACE Ingress tag action, when 3258 ETAG is present (value = TRUE/FALSE) */ 3259 bcmPortControlEtagEgressReplace = 220, /* Set REPLACE Egress tag action, when 3260 ETAG is present (value = TRUE/FALSE) */ 3261 bcmPortControlEtagIngressDelete = 221, /* Set DELETE Ingress tag action, when 3262 ETAG is present (value = TRUE/FALSE) */ 3263 bcmPortControlEtagEgressDelete = 222, /* Set DELETE Egress tag action, when 3264 ETAG is present (value = TRUE/FALSE) */ 3265 bcmPortControlExtenderRpfCheck = 223, /* Set incoming packet ETAG.SVID RPF 3266 check control (value = TRUE/FALSE) */ 3267 bcmPortControlExtenderSourceKnockout = 224, /* Set source extended port VID pruning 3268 control (value = TRUE/FALSE) */ 3269 bcmPortControlExtenderForwardPort = 225, /* Set destination port for upstream 3270 Extender forwarding (value = local 3271 port number) */ 3272 bcmPortControlExtenderType = 226, /* Set Extender port type (enumerated 3273 value within 3274 bcm_port_extender_type_t) */ 3275 bcmPortControlExtenderNameSpace = 227, /* Set namespace value (value range 3276 0-0xfff) */ 3277 bcmPortControlEtagPcpDeSelect = 228, /* Set source of PCP and DE fields when 3278 adding an ETAG to an ingress packet 3279 (value = 3280 bcm_extender_pcp_de_select_t) */ 3281 bcmPortControlEtagPcp = 229, /* Set default PCP field when adding an 3282 ETAG to an ingress packet (value = 3283 0-7) */ 3284 bcmPortControlEtagDe = 230, /* Set default DE field when adding an 3285 ETAG to an ingress packet (value = 3286 0-1) */ 3287 bcmPortControlUseEtagPri = 231, /* Use ETAG PCP and DE fields to derive 3288 internal priority and color */ 3289 bcmPortControlProhibitedDot1p = 232, /* Set prohibited 802.1p values */ 3290 bcmPortControlEgressFilterDisable = 233, /* Enable/ disable Egress Filtering */ 3291 bcmPortControlLLFCReceive = 234, /* Link Level Flow Control packet 3292 receive enable */ 3293 bcmPortControlLLFCTransmit = 235, /* Link Level Flow Control packet 3294 transmit enable */ 3295 bcmPortControlSAFCReceive = 236, /* Service Aware Flow Control packet 3296 receive enable */ 3297 bcmPortControlSAFCTransmit = 237, /* Service Aware Flow Control packet 3298 transmit enable */ 3299 bcmPortControlMacSwap = 238, /* Enable or Disable MAC swapping on the 3300 port for incoming packet */ 3301 bcmPortControlOverlayRecycle = 241, /* Set port as recycle port for overlay 3302 packets second pass */ 3303 bcmPortControlEvbType = 242, /* Set EVB port type (enumerated value 3304 within bcm_port_evb_type_t) */ 3305 bcmPortControlOamLookupWithDvp = 243, /* Use DVP as one of the keys for OAM 3306 lookup */ 3307 bcmPortControlSubportTagEnable = 244, /* Enable/disable 'third VLAN tag' 3308 (subport tag) channelization over 3309 Ethernet */ 3310 bcmPortControlVMac = 247, /* Enable/Disable VMAC function. */ 3311 bcmPortControlEgressModifyDscp = 248, /* Enable DSCP/EXP marking. In simple 3312 mode enable on port. In advanced mode 3313 enable on inlif profile. */ 3314 bcmPortControlFcoeRouteEnable = 249, /* Enables FCOE routing */ 3315 bcmPortControlFcoeVftEnable = 250, /* Controls VFT header expected on port */ 3316 bcmPortControlFcoeZoneCheckEnable = 251, /* Enables zone check */ 3317 bcmPortControlFcoeSourceBindCheckEnable = 252, /* Enables source bind check */ 3318 bcmPortControlFcoeFpmaPrefixCheckEnable = 253, /* Enables FPMA prefix check */ 3319 bcmPortControlFcoeDoNotLearn = 254, /* Disables learning for packets with 3320 FCOE EtherType */ 3321 bcmPortControlFcoeNetworkPort = 255, /* Sets whether the port is network 3322 (uplink) or not (downfacing) */ 3323 bcmPortControlFcoeFabricSel = 256, /* Selects the source of fabric Id and 3324 priority */ 3325 bcmPortControlFcoeFabricId = 257, /* Sets the port default 12-bit fabric 3326 Id */ 3327 bcmPortControlFcoeFabricPri = 258, /* Sets the port default fabric priority */ 3328 bcmPortControlFcoeFcCrcAction = 259, /* Sets the FC CRC action to take */ 3329 bcmPortControlFcoeFcCrcRecompute = 260, /* Sets the re-compute CRC options */ 3330 bcmPortControlFcoeFcEofIgnore = 261, /* Sets the control to Ignore EOF */ 3331 bcmPortControlMcastGroupRemap = 262, /* Enable remapping of multicast group 3332 index. */ 3333 bcmPortControlLocalSwitching = 263, /* to enable Local route switching on a 3334 port */ 3335 bcmPortControlFecErrorDetectEnable = 264, /* Enables marking of failed error 3336 correction on the cells */ 3337 bcmPortControlLowLatencyLLFCEnable = 265, /* Enables an improvment in latency on 3338 the expense of bandwidth */ 3339 bcmPortControlErspanEnable = 266, /* Enable/Disable ERSPAN mirroring */ 3340 bcmPortControlPFCXOffTime = 267, /* Priority Flow Control xoff time */ 3341 bcmPortControlOamDefaultProfile = 268, /* OAM default profile */ 3342 bcmPortControlSubportPktTagDrop = 269, /* Set Ingress drop control, if LLTAG is 3343 present (value = TRUE/FALSE) */ 3344 bcmPortControlNoSubportPktTagDrop = 270, /* Set Ingress drop control, if LLTAG is 3345 not present (value = TRUE/FALSE) */ 3346 bcmPortControlUseSubportPktTagPri = 271, /* Use LLTAG PCP and DE fields to derive 3347 internal priority and color */ 3348 bcmPortControlVlanVpGroupEgress = 272, /* VP group for egress vlan membership */ 3349 bcmPortControlVlanVpGroupIngress = 273, /* VP group for ingress vlan membership */ 3350 bcmPortControlEEEMode = 274, /* Select Energy Efficient Ethernet mode */ 3351 bcmPortControlProbeSerdesReset = 275, /* Request to reset SerDes on next probe 3352 to the SerDes */ 3353 bcmPortControlFcoeVsanSel = bcmPortControlFcoeFabricSel, /* Selects the source of VSAN ID and 3354 priority */ 3355 bcmPortControlFcoeVsanId = bcmPortControlFcoeFabricId, /* Sets the port default 12-bit VSAN ID */ 3356 bcmPortControlFcoeVsanPri = bcmPortControlFcoeFabricPri, /* Sets the port default VSAN priority */ 3357 bcmPortControlIPMC4Ucast = 276, /* Enable IPMCv4 Unicast MACDA feature 3358 on port. */ 3359 bcmPortControlIPMC6Ucast = 277, /* Enable IPMCv6 Unicast MACDA feature 3360 on port. */ 3361 bcmPortControlWredDropCountUpdateEnableQueueMask = 278, /* Set the queue mask to enable the WRED 3362 dropped counter increase. */ 3363 bcmPortControlWredDropCountUpdateEnableColorMask = 279, /* Set the color mask to enable the WRED 3364 dropped counter increase. */ 3365 bcmPortControlReserved280 = 280, /* Reserved. */ 3366 bcmPortControlReserved281 = 281, /* Reserved. */ 3367 bcmPortControlRxFastLOS = 282, /* Enable/disable accelerated linkscan 3368 capability on port */ 3369 bcmPortControlFcoeTranslateKeyFirst = 283, /* The key to use for the first VLAN 3370 translate search if the EtherType is 3371 FCOE */ 3372 bcmPortControlFcoeTranslateKeySecond = 284, /* The key to use for the second VLAN 3373 translate search if the EtherType is 3374 FCOE */ 3375 bcmPortControlMmuDrain = 285, /* Draining the cells of the port */ 3376 bcmPortControlMmuTrafficEnable = 286, /* Enable/disable enqueing the packets 3377 to the port */ 3378 bcmPortControlStatCollectionEnable = 287, /* Enable/disable the gathering of MIB 3379 statistics on the port */ 3380 bcmPortControlLlfcCellsCongestionIndEnable = 288, /* EnableDisable extracting cells 3381 congestion indication from LLFC cells */ 3382 bcmPortControlTrunkLoadBalancingRandomizer = 289, /* Assigns the Load Balancing 3383 Randomizer-value for LAGs(value = 3384 integer between 0 and 15) */ 3385 bcmPortControlECMPLevel1LoadBalancingRandomizer = 290, /* Assigns the Load Balancing 3386 Randomizer-value for ECMP (at Level 1 3387 in Two level ECMP)(value = integer 3388 between 0 and 15) */ 3389 bcmPortControlECMPLevel2LoadBalancingRandomizer = 291, /* Assigns the Load Balancing 3390 Randomizer-value for ECMP at Level 2 3391 in Two Level ECMP(value = integer 3392 between 0 and 15) */ 3393 bcmPortControlMplsExplicitNullEnable = 292, /* Enable or disable Explicit NULL 3394 termination database */ 3395 bcmPortControlExtenderEnable = 293, /* Enable/disable port extender 3396 capability on the port */ 3397 bcmPortControlSubportTagSize = 294, /* Set the CoE egress subport tag size. 3398 When set inserts a wide subport tag, 3399 else inserts a regular subport tag */ 3400 bcmPortControlSystemPortOverride = 295, /* When set, port group id used for 3401 egress VLAN translation is replaced 3402 with destination global logical port */ 3403 bcmPortControlOamDefaultProfileEgress = 296, /* OAM default profile for Egress */ 3404 bcmPortControlPadToSize = 297, /* Min packet size in bytes, packets 3405 smaller than this value are padded 3406 with '0' */ 3407 bcmPortControlVxlanVpnAssignmentCriteria = 298, /* VxLAN vpn assignment criteria */ 3408 bcmPortControlVxlanTerminationMatchCriteria = 299, /* VxLAN termination match criteria */ 3409 bcmPortControlVxlanGportAssignmentCriteria = 300, /* VxLAN virtual port assignment 3410 criteria */ 3411 bcmPortControlOOBFCTxReportIngEnable = 301, /* OOB FC Tx Ingress Congestion 3412 Notification Enable */ 3413 bcmPortControlOOBFCTxReportEgrEnable = 302, /* OOB FC Tx Egress Congestion 3414 Notification Enable */ 3415 bcmPortControlMplsEncapsulateExtendedLabel = 303, /* Encapsulate additional MPLS tunnel on 3416 a given outlif */ 3417 bcmPortControlSampleIngressDest = 304, /* Set Ingress sFlow sample destination */ 3418 bcmPortControlSampleFlexDest = 305, /* Set Flex sFlow sample destination */ 3419 bcmPortControlSampleFlexRate = 306, /* Set Flex sFlow sampling rate */ 3420 bcmPortControlExternalBufferEnable = 307, /* Enable/disable the MMU External 3421 Buffer on the port */ 3422 bcmPortControlTrustMimlPri = 308, /* If set, use packet priority from MiML 3423 header for internal priority mapping */ 3424 bcmPortControlTrustCustomHeaderPri = 309, /* If set, determine internal Priority 3425 based on custom header */ 3426 bcmPortControlCustomHeaderEncapEnable = 310, /* If set, enable the capability of 3427 custom header encapsulation */ 3428 bcmPortControlLinkPhyEnable = 311, /* Enable LinkPhy on a Port */ 3429 bcmPortControlOlpEnable = 312, /* Enable/disable OLP 3430 encapsulation/Decapsulation on a 3431 given port */ 3432 bcmPortControlPortMacOui = 313, /* OUI field of PORT specific MAC. Used 3433 for OAM and SAT */ 3434 bcmPortControlPortMacNonOui = 314, /* NON OUI field of PORT specific MAC. 3435 Used for OAM and SAT */ 3436 bcmPortControlSatEnable = 315, /* Enable/Disable SAT feature. */ 3437 bcmPortControl1588P2PDelay = 316, /* Update path delay in 1588 p2p 3438 mechanism. */ 3439 bcmPortControlSampleIngressEnable = 317, /* Enable/Disable ingress port-based 3440 sflow. */ 3441 bcmPortControlSampleEgressEnable = 318, /* Enable/Disable egress port-based 3442 sflow. */ 3443 bcmPortControlSampleIngressRate = 319, /* Set Ingress sFlow sample rate. */ 3444 bcmPortControlSampleEgressRate = 320, /* Set Egress sFlow sample rate. */ 3445 bcmPortControlMplsSpeculativeParse = 321, /* Enable the speculative parsing of 3446 headers over MPLS. */ 3447 bcmPortControlFieldHiGigClassSelect = 322, /* Control classid selection into HG 3448 header. */ 3449 bcmPortControlDvpGroupId = 323, /* Configure DVP group value which will 3450 be used to compare against SVP for 3451 pruning decision */ 3452 bcmPortControlDvpGroupKnockoutEnable = 324, /* Enable/Disable DVP group based 3453 pruning. Supported values are 3454 0-Disable, 1-Enable */ 3455 bcmPortControlUntaggedVlanMember = 325, /* Set the VLAN-Membership state per 3456 port for packets classified as 3457 untagged */ 3458 bcmPortControlMPLSEncapsulateAdditionalLabel = 326, /* Set additional label enable on 3459 outgoing LIF */ 3460 bcmPortControlPreserveDscpIngress = 327, /* Preserve DSCP after routing, ingress 3461 logical port configuration */ 3462 bcmPortControlPreserveDscpEgress = 328, /* Preserve DSCP after routing, egress 3463 logical port configuration */ 3464 bcmPortControlPWETerminationPortModeEnable = 329, /* Enable PWE termination port mode on a 3465 port, if enabled, PWE label 3466 termination lookup key will be 3467 <port+label> */ 3468 bcmPortControlOuterPolicerRemark = 330, /* set/get in-lif profile or map DP 3469 profile mapping in-lif profile to 3470 remark outer PCP-DEI. */ 3471 bcmPortControlInnerPolicerRemark = 331, /* set/get in-lif profile or map DP 3472 profile mapping in-lif profile to 3473 remark inner PCP-DEI. */ 3474 bcmPortControlAllowTtlInheritance = 332, /* Enabling Ingress inheritance of TTL 3475 per Outgoing Logical interface 3476 (consume Out-LIF profile) */ 3477 bcmPortControlAllowQosInheritance = 333, /* Enabling Ingress inheritance DSCP-EXP 3478 per Outgoing Logical interface 3479 (consume Out-LIF profile) */ 3480 bcmPortControlPacketTimeStampInsertRx = 334, /* Insert RX packet timestamp for 3481 packets arriving on the port. */ 3482 bcmPortControlPacketTimeStampInsertTx = 335, /* Insert TX packet timestamp for 3483 packets exiting the port. */ 3484 bcmPortControlPacketTimeStampSrcPortInsertCancel = 336, /* Cancel/override both RX and TX time 3485 stamp insertions for the packets 3486 arriving on the port. */ 3487 bcmPortControlPacketTimeStampDestPortInsertCancel = 337, /* Cancel/override both RX and TX time 3488 stamp insertions for the packets 3489 exiting the port. */ 3490 bcmPortControlPacketTimeStampRxId = 338, /* Set Source identifier of RX (Ingress) 3491 Packet Time Stamp record header. */ 3492 bcmPortControlPacketTimeStampTxId = 339, /* Set Source identifier of TX (Egress) 3493 Packet Time Stamp record header. */ 3494 bcmPortControlPacketTimeStampByteMeterAdjust = 340, /* Set if need to adjust meter for 3495 packet timestamp. */ 3496 bcmPortControlDoNotCheckVlanEgress = 341, /* Enable/Disable egress VLAN checks for 3497 VP port. */ 3498 bcmPortControlE2EFCTransmitEnable = 342, /* Enable E2EFC message transmit. */ 3499 bcmPortControlE2EFCReceiveEnable = 343, /* Enable E2EFC message receive. */ 3500 bcmPortControlE2EFCCopyToCpuEnable = 344, /* Enable E2EFC message copy-to-CPU. */ 3501 bcmPortControlE2EFCDestMacOui = 345, /* E2EFC message destination MAC upper 3 3502 bytes, only for E2EFC TX. */ 3503 bcmPortControlE2EFCDestMacNonOui = 346, /* E2EFC message destination MAC lower 3 3504 bytes, only for E2EFC TX. */ 3505 bcmPortControlE2EFCSrcMacOui = 347, /* E2EFC message source MAC upper 3 3506 bytes, only for E2EFC TX. */ 3507 bcmPortControlE2EFCSrcMacNonOui = 348, /* E2EFC message source MAC lower 3 3508 bytes, only for E2EFC TX. */ 3509 bcmPortControlE2EFCEtherType = 349, /* E2EFC message EtherType/length, only 3510 for E2EFC TX. */ 3511 bcmPortControlE2EFCOpcode = 350, /* E2EFC message opcode, only for E2EFC 3512 TX. */ 3513 bcmPortControlForceBridgeForwarding = 351, /* Set port to Force Bridge Forwarding. */ 3514 bcmPortControlIlknRxPathEnable = 352, /* Enable/Disable rx path on Ilkn port. 3515 Only use with no linkscan */ 3516 bcmPortControlEgressAclTwoPassEditing = 353, /* Enable/Disable egress ACL two pass 3517 editing on a recycle port */ 3518 bcmPortControlLLFCAfterFecEnable = 354, /* Enable/Disable FEC on LLFC and 3519 congestion indication */ 3520 bcmPortControlResetSerdes = 355, /* Apply reset and relesase reset to 3521 SerDes core. Hard resets PCS and PMD */ 3522 bcmPortControlPONEnable = 356, /* Enable or disable pon capability on 3523 the port */ 3524 bcmPortControlLogicalInterfaceSameFilter = 357, /* Set or unset Same-interface filtering 3525 according to logical-interface ID 3526 while incoming and outgoing port-ID 3527 will be ignored. */ 3528 bcmPortControlIPv6TerminationCascadedModeEnable = 358, /* Enable per port cascading lookup of 3529 IPv6 tunnel termination */ 3530 bcmPortControlMimUcastTermEnable = 359, /* Enable/Disable MiM UC Termination 3531 Mode */ 3532 bcmPortControlMimMcastTermEnable = 360, /* Enable/Disable MiM MC and BC 3533 Termination Mode */ 3534 bcmPortControlTXPISDMOverride = 361, /* Override TXPI SDM value */ 3535 bcmPortControlTXPISDMStatus = 362, /* The final result value of TXPI SDM */ 3536 bcmPortControlBicastPort = 363, /* Sets the Bicast mapping for port */ 3537 bcmPortControlObmClassifierPriority = 364, /* Indicates the default OBM Traffic 3538 class for port */ 3539 bcmPortControlObmClassifierEnableDscp = 365, /* Enable OBM DSCP Classifier on port */ 3540 bcmPortControlObmClassifierEnableMpls = 366, /* Enable OBM MPLS Classifier on port */ 3541 bcmPortControlObmClassifierEnableEtag = 367, /* Enable OBM ETAG Classifier on port */ 3542 bcmPortControlObmClassifierEtagEthertype = 368, /* Configure EtherType for OBM ETAG 3543 Classifier */ 3544 bcmPortControlObmClassifierVntagEthertype = 369, /* Configure EtherType for OBM VNTAG 3545 Classifier */ 3546 bcmPortControlControlCellsFecBypassEnable = 370, /* Determine if FEC is bypassed by two 3547 control cells types: credit cells and 3548 flow status cells. 3549 3550 Enable FEC bypass means to NOT do FEC 3551 on these controls cells.Disable FEC 3552 bypass means to do FEC on these 3553 controls cells. 3554 This 3555 configuration is relevant for RS FEC 3556 types only. */ 3557 bcmPortControlPrbsRxInvertData = 371, /* Configure inversion of Rx data */ 3558 bcmPortControlFcoeTranslateKeyFirstEgress = 372, /* The key to use for the first Egress 3559 VLAN translate search if the 3560 EtherType is FCOE */ 3561 bcmPortControlFcoeTranslateKeySecondEgress = 373, /* The key to use for the second Egress 3562 VLAN translate search if the 3563 EtherType is FCOE */ 3564 bcmPortControlIntEnable = 374, /* Enable INT at port level */ 3565 bcmPortControlIntPortMetaData = 375, /* Enable per port Metadata inserstion */ 3566 bcmPortControlIntTurnaround = 376, /* Program a egress port as INT 3567 turnaround port */ 3568 bcmPortControlQosRemarkResolution = 377, /* Program a egress port QoS 3569 resolution(enumerated value within 3570 bcm_port_qos_resolution_type_t) */ 3571 bcmPortControlObmClassifierInternal = 378, /* Used to enable/disable internal OBM 3572 classification. By default external 3573 OBM classification is enabled. Once 3574 internal OBM classification is 3575 disabled, external OBM classification 3576 becomes active. */ 3577 bcmPortControlWirelessCosMapSelect = 379, /* Used to select the wireless cos map 3578 for the traffic for a port. */ 3579 bcmPortControlHiGigCosSelect = 380, /* Used to select the HiGig cos for a 3580 port. */ 3581 bcmPortControlTpidSrc = 381, /* Used to configure TPID source on VP */ 3582 bcmPortControlInternalLoopback = 382, /* Enable/Disable the port's internal 3583 loopback mode */ 3584 bcmPortConrolEgressVlanPortArpPointed = 383, /* Used to configure the index to vlan 3585 port per ARP. */ 3586 bcmPortControlVrrpScalingPort = 384, /* Used to enable/disable VRRP scaling 3587 per port. */ 3588 bcmPortControlObmInterruptTypeDropPreempt = 385, /* Used to enable obm interrupt for 3589 preempt drop. */ 3590 bcmPortControlObmInterruptTypeDropExpress = 386, /* Used to enable obm interrupt for 3591 express drop. */ 3592 bcmPortControlObmInterruptTypeOverflowPreempt = 387, /* Used to enable interrupt for preempt 3593 overflow */ 3594 bcmPortControlObmInterruptTypeOverflowExpress = 388, /* Used to enable interrupt for express 3595 overflow. */ 3596 bcmPortControlForwardNetworkGroup = 389, /* Enable/Disable Forward network group 3597 functionality. */ 3598 bcmPortControlIngressQosModelRemark = 390, /* Used to configure Ingress remark QOS 3599 model */ 3600 bcmPortControlIngressQosModelPhb = 391, /* Used to configure Ingress PHB QOS 3601 model */ 3602 bcmPortControlIngressQosModelTtl = 392, /* Used to configure Ingress TTL QOS 3603 model */ 3604 bcmPortControlMetadata = 393, /* Used to configure egress port 3605 metadata */ 3606 bcmPortControlFirstHeaderSize = 394, /* Used to configure the size of the 3607 first header to skip. */ 3608 bcmPortControlDistributeLearnMessageMode = 395, /* Used to configure distribute learn 3609 message mode. */ 3610 bcmPortControlDiscardEgress = 396, /* enable/disable to discard all traffic 3611 on that outgoing port. */ 3612 bcmPortControlIngressEnable = 397, /* enable/disable single ingress port. */ 3613 bcmPortControlRuntThreshold = 398, /* configure rxrunt threshold to mac. */ 3614 bcmPortControlReflectorL2 = 399, /* configure port to internal reflector 3615 without system header. */ 3616 bcmPortControlRxPriority = 400, /* configure port Rx priority. */ 3617 bcmPortControlIP4TunnelTermEnable = 401, /* Enable or disable IPv4 tunnel 3618 termination. */ 3619 bcmPortControlIP6TunnelTermEnable = 402, /* Enable or disable IPv6 tunnel 3620 termination. */ 3621 bcmPortControlQoSRemarkEgressEnable = 403, /* Enable or disable egress port-based 3622 QoS remarking. */ 3623 bcmPortControlBridgeEgress = 404, /* Enable or disable egress port-based 3624 bridging. */ 3625 bcmPortControlLatencyEcnEnable = 405, /* Enable or disable latency based ECN 3626 on egress port. */ 3627 bcmPortControlModEnable = 406, /* Enable or disable port-based MOD. */ 3628 bcmPortControlModProfileId = 407, /* Designate a MOD profile id to a port. */ 3629 bcmPortControlLinkFaultLocalClear = 408, /* Clear the sticky local_fault_status 3630 bit. */ 3631 bcmPortControlLinkFaultRemoteClear = 409, /* Clear the sticky remote_fault_status 3632 bit. */ 3633 bcmPortControlIngressSampleProfile = 410, /* Ingress sample profile id. */ 3634 bcmPortControlPFCFromLLFCEnable = 411, /* Enable/disable LLFC RMC threshold to 3635 generate PFC on the specified port. */ 3636 bcmPortControlFirstHeaderSizeAfterInjected = 412, /* Used to configure the size of the 3637 first header to skip after injected. */ 3638 bcmPortControlFlexeDoubleNbTdmSlotEnable = 413, /* Control the number of slots for FlexE 3639 NB TDM calendar for 50G NRZ port with 3640 FEC enabled. */ 3641 bcmPortControlRecycleApp = 414, /* Configure Port Recycle application. */ 3642 bcmPortControlSystemPortInjectedMap = 415, /* Enable mapping system port to 3643 local-port for injected traffic 3644 scenarios. */ 3645 bcmPortControlPacketTimeStampIngressInsertTx = 416, /* Enable to insert TX timestamp on 3646 transmitted packets when they are 3647 arriving on the ingress port. */ 3648 bcmPortControlPacketTimeStampIngressInsertTxCancel = 417, /* Enable to skip TX timestamp insertion 3649 on transmitted packets when they are 3650 arriving on the ingress port. */ 3651 bcmPortControlEgressVlanPriSrc = 418, /* Select the source of egress VLAN 3652 priority. */ 3653 bcmPortControlTxStall = 419, /* Stall dequeuing packets. */ 3654 bcmPortControlTxByteState = 420, /* Enable TX byte state to update TX 3655 byte count that would be inserted 3656 into IFA metadata. */ 3657 bcmPortControlPacketProcssingPort = 421, /* Set the packet processing port 3658 number. */ 3659 bcmPortControlIfaEnable = 422, /* Enable IFA. */ 3660 bcmPortControlIoamEnable = 423, /* Enable IOAM. */ 3661 bcmPortControlPFCStatus = 424, /* Get port's current received PFCs 3662 status. */ 3663 bcmPortControlRoeLinkdownTransmit = 425, /* For the given ROE port tx traffic is 3664 enabled even if link is downt. */ 3665 bcmPortControlRoeLinkdownReceive = 426, /* For the given ROE port rx traffic is 3666 enabled even if link is down. */ 3667 bcmPortControlEgressPktPriCfiCopyIngressEnable = 427, /* Enable or disable egress packet 3668 priority and CFI copy on ingress 3669 port. */ 3670 bcmPortControlEgressTosCopyIngressEnable = 428, /* Enable or disable egress TOS copy on 3671 ingress port. */ 3672 bcmPortControlEgressL2OpaqueTag = 429 /* Set egress L2 opaque tag. */ 3673 } bcm_port_control_t; 3674 3675 /* EEE modes. */ 3676 typedef enum bcm_port_eee_mode_e { 3677 bcmPortEEENativeMode = 0, /* EEE native mode */ 3678 bcmPortEEEBurstAndBatchMode = 1 /* EEE burst and batch mode */ 3679 } bcm_port_eee_mode_t; 3680 3681 /* Types of Tunnel ID. */ 3682 typedef enum bcm_port_tunnel_id_e { 3683 BCM_PORT_TUNNEL_ID_NONE = 0, /* No Tunnel ID */ 3684 BCM_PORT_TUNNEL_ID_VLAN = 1 /* VLAN tag as Tunnel ID */ 3685 } bcm_port_tunnel_id_t; 3686 3687 #ifndef BCM_HIDE_DISPATCHABLE 3688 3689 /* Get or set various features at the port level. */ 3690 extern int bcm_port_control_set( 3691 int unit, 3692 bcm_port_t port, 3693 bcm_port_control_t type, 3694 int value); 3695 3696 /* Get or set various features at the port level. */ 3697 extern int bcm_port_control_get( 3698 int unit, 3699 bcm_port_t port, 3700 bcm_port_control_t type, 3701 int *value); 3702 3703 /* 3704 * Get the list of ancillary/flex ports belonging to the same port block 3705 * as the 3706 * controlling port. 3707 */ 3708 extern int bcm_port_subsidiary_ports_get( 3709 int unit, 3710 bcm_port_t port, 3711 bcm_pbmp_t *pbmp); 3712 3713 #endif /* BCM_HIDE_DISPATCHABLE */ 3714 3715 /* Initializes the bcm_port_info_t structure. */ 3716 extern void bcm_port_info_t_init( 3717 bcm_port_info_t *info); 3718 3719 /* Initialize a Port Ability structure. */ 3720 extern void bcm_port_ability_t_init( 3721 bcm_port_ability_t *ability); 3722 3723 /* Initializes the bcm_phy_config_t structure. */ 3724 extern void bcm_phy_config_t_init( 3725 bcm_phy_config_t *config); 3726 3727 /* Initializes the bcm_port_interface_config_t structure. */ 3728 extern void bcm_port_interface_config_t_init( 3729 bcm_port_interface_config_t *config); 3730 3731 /* Initialize a Port Configuration structure. */ 3732 extern void bcm_port_config_t_init( 3733 bcm_port_config_t *pconfig); 3734 3735 /* Initialize a Port Encapsulation Configuration structure. */ 3736 extern void bcm_port_encap_config_t_init( 3737 bcm_port_encap_config_t *encap_config); 3738 3739 #define BCM_PORT_CONGESTION_CONFIG_E2ECC 0x00000001 3740 #define BCM_PORT_CONGESTION_CONFIG_HCFC 0x00000002 3741 #define BCM_PORT_CONGESTION_CONFIG_DESTMOD_FLOW_CONTROL 0x00000004 3742 #define BCM_PORT_CONGESTION_CONFIG_MAX_SPLIT4 0x00000008 3743 #define BCM_PORT_CONGESTION_CONFIG_TX 0x00000010 3744 #define BCM_PORT_CONGESTION_CONFIG_RX 0x00000020 3745 #define BCM_PORT_CONGESTION_CONFIG_SAFC 0x00000040 3746 #define BCM_PORT_CONGESTION_CONFIG_QCN 0x00000080 3747 #define BCM_PORT_CONGESTION_CONFIG_DEST_PORT_VALID 0x00000100 3748 #define BCM_PORT_CONGESTION_CONFIG_DESTMODPORT_FLOW_CONTROL 0x00000200 3749 #define BCM_PORT_CONGESTION_CONFIG_E2ECC_COE_STRICT_MODE 0x00000400 3750 #define BCM_PORT_CONGESTION_CONFIG_E2ECC_COE_FLEX_MODE 0x00000800 3751 #define BCM_PORT_CONGESTION_CONFIG_VLAN_PAUSE_COE 0x00001000 3752 #define BCM_PORT_CONGESTION_CONFIG_COPY_TO_CPU 0x00002000 3753 3754 /* bcm_port_congestion_config_s */ 3755 typedef struct bcm_port_congestion_config_s { 3756 uint32 flags; /* congestion mode. */ 3757 uint8 port_bits; /* HiGig format for port status */ 3758 int packets_per_sec; /* frequency of sending congestion messages */ 3759 bcm_gport_t src_port; /* gport of type mmodid:port, wildcard on 3760 receive */ 3761 uint16 multicast_id; /* Multicast Identifier */ 3762 bcm_cos_t traffic_class; /* Traffic Class */ 3763 bcm_color_t color; /* Color */ 3764 bcm_vlan_t vlan; /* Vlan */ 3765 uint8 pri; /* Packet priority */ 3766 uint8 cfi; /* CFI */ 3767 bcm_mac_t src_mac; /* Source MAC address */ 3768 bcm_mac_t dest_mac; /* Destination MAC address */ 3769 uint16 ethertype; /* Ethernet Type */ 3770 uint16 opcode; /* Opcode */ 3771 uint8 version; /* QCN PDU version */ 3772 uint8 reserved_v; /* QCN PDU reserved_v */ 3773 bcm_gport_t dst_port; /* gport of type mmodid:port */ 3774 } bcm_port_congestion_config_t; 3775 3776 /* Initialize a Port Congestion Configuration structure. */ 3777 extern void bcm_port_congestion_config_t_init( 3778 bcm_port_congestion_config_t *config); 3779 3780 #ifndef BCM_HIDE_DISPATCHABLE 3781 3782 /* Configure/retrieve flow control protocol mode. */ 3783 extern int bcm_port_congestion_config_set( 3784 int unit, 3785 bcm_gport_t port, 3786 bcm_port_congestion_config_t *config); 3787 3788 /* Configure/retrieve flow control protocol mode. */ 3789 extern int bcm_port_congestion_config_get( 3790 int unit, 3791 bcm_gport_t port, 3792 bcm_port_congestion_config_t *config); 3793 3794 #endif /* BCM_HIDE_DISPATCHABLE */ 3795 3796 /* bcm_port_phy_control_t */ 3797 typedef _shr_port_phy_control_t bcm_port_phy_control_t; 3798 3799 /* 3800 * PHY interrupts sources for use with PORT_PHY_CONTROL_INTR_MASK and 3801 * PORT_PHY_CONTROL_INTR_STATUS. 3802 */ 3803 #define BCM_PORT_PHY_INTR_TIMESYNC_FRAMESYNC _SHR_PORT_PHY_INTR_TIMESYNC_FRAMESYNC 3804 #define BCM_PORT_PHY_INTR_TIMESYNC_TIMESTAMP _SHR_PORT_PHY_INTR_TIMESYNC_TIMESTAMP 3805 #define BCM_PORT_PHY_INTR_LINK_EVENT _SHR_PORT_PHY_INTR_LINK_EVENT 3806 #define BCM_PORT_PHY_INTR_AUTONEG_EVENT _SHR_PORT_PHY_INTR_AUTONEG_EVENT 3807 #define BCM_PORT_PHY_INTR_PLL_EVENT _SHR_PORT_PHY_INTR_PLL_EVENT 3808 #define BCM_PORT_PHY_INTR_UC_EVENT _SHR_PORT_PHY_INTR_UC_EVENT 3809 #define BCM_PORT_PHY_INTR_EMON_EVENT _SHR_PORT_PHY_INTR_EMON_EVENT 3810 #define BCM_PORT_PHY_INTR_AUX_EVENT _SHR_PORT_PHY_INTR_AUX_EVENT 3811 3812 /* Controls for changing PHY settings. */ 3813 #define BCM_PORT_PHY_CONTROL_WAN _SHR_PORT_PHY_CONTROL_WAN 3814 #define BCM_PORT_PHY_CONTROL_PREEMPHASIS _SHR_PORT_PHY_CONTROL_PREEMPHASIS 3815 #define BCM_PORT_PHY_CONTROL_PREEMPHASIS_LANE0 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE0 3816 #define BCM_PORT_PHY_CONTROL_PREEMPHASIS_LANE1 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE1 3817 #define BCM_PORT_PHY_CONTROL_PREEMPHASIS_LANE2 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE2 3818 #define BCM_PORT_PHY_CONTROL_PREEMPHASIS_LANE3 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE3 3819 #define BCM_PORT_PHY_CONTROL_DRIVER_CURRENT _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT 3820 #define BCM_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE0 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE0 3821 #define BCM_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE1 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE1 3822 #define BCM_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE2 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE2 3823 #define BCM_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE3 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE3 3824 #define BCM_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT 3825 #define BCM_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE0 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE0 3826 #define BCM_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE1 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE1 3827 #define BCM_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE2 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE2 3828 #define BCM_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE3 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE3 3829 #define BCM_PORT_PHY_CONTROL_EQUALIZER_BOOST _SHR_PORT_PHY_CONTROL_EQUALIZER_BOOST 3830 #define BCM_PORT_PHY_CONTROL_INTERFACE _SHR_PORT_PHY_CONTROL_INTERFACE 3831 #define BCM_PORT_PHY_CONTROL_MACSEC_ENABLE _SHR_PORT_PHY_CONTROL_MACSEC_ENABLE 3832 #define BCM_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED 3833 #define BCM_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_SPEED _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_SPEED 3834 #define BCM_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_DUPLEX _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_DUPLEX 3835 #define BCM_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_PAUSE _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_PAUSE 3836 #define BCM_PORT_PHY_CONTROL_MACSEC_PAUSE_RX_FORWARD _SHR_PORT_PHY_CONTROL_MACSEC_PAUSE_RX_FORWARD 3837 #define BCM_PORT_PHY_CONTROL_MACSEC_PAUSE_TX_FORWARD _SHR_PORT_PHY_CONTROL_MACSEC_PAUSE_TX_FORWARD 3838 #define BCM_PORT_PHY_CONTROL_MACSEC_LINE_IPG _SHR_PORT_PHY_CONTROL_MACSEC_LINE_IPG 3839 #define BCM_PORT_PHY_CONTROL_MACSEC_SWITCH_IPG _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_IPG 3840 #define BCM_PORT_PHY_CONTROL_LONGREACH_SPEED _SHR_PORT_PHY_CONTROL_LONGREACH_SPEED 3841 #define BCM_PORT_PHY_CONTROL_LONGREACH_PAIRS _SHR_PORT_PHY_CONTROL_LONGREACH_PAIRS 3842 #define BCM_PORT_PHY_CONTROL_LONGREACH_GAIN _SHR_PORT_PHY_CONTROL_LONGREACH_GAIN 3843 #define BCM_PORT_PHY_CONTROL_LONGREACH_AUTONEG _SHR_PORT_PHY_CONTROL_LONGREACH_AUTONEG 3844 #define BCM_PORT_PHY_CONTROL_LONGREACH_LOCAL_ABILITY _SHR_PORT_PHY_CONTROL_LONGREACH_LOCAL_ABILITY 3845 #define BCM_PORT_PHY_CONTROL_LONGREACH_REMOTE_ABILITY _SHR_PORT_PHY_CONTROL_LONGREACH_REMOTE_ABILITY 3846 #define BCM_PORT_PHY_CONTROL_LONGREACH_CURRENT_ABILITY _SHR_PORT_PHY_CONTROL_LONGREACH_CURRENT_ABILITY 3847 #define BCM_PORT_PHY_CONTROL_LONGREACH_MASTER _SHR_PORT_PHY_CONTROL_LONGREACH_MASTER 3848 #define BCM_PORT_PHY_CONTROL_LONGREACH_ACTIVE _SHR_PORT_PHY_CONTROL_LONGREACH_ACTIVE 3849 #define BCM_PORT_PHY_CONTROL_LONGREACH_ENABLE _SHR_PORT_PHY_CONTROL_LONGREACH_ENABLE 3850 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_NONE _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_NONE 3851 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_1PAIR 3852 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_2PAIR 3853 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_1PAIR 3854 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_2PAIR 3855 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_1PAIR 3856 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_2PAIR 3857 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_1PAIR 3858 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_2PAIR 3859 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_1PAIR 3860 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_2PAIR 3861 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_1PAIR 3862 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_2PAIR 3863 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_4PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_4PAIR 3864 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_RX _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_RX 3865 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_TX _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_TX 3866 #define BCM_PORT_PHY_CONTROL_POWER _SHR_PORT_PHY_CONTROL_POWER 3867 #define BCM_PORT_PHY_CONTROL_POWER_FULL _SHR_PORT_PHY_CONTROL_POWER_FULL 3868 #define BCM_PORT_PHY_CONTROL_POWER_LOW _SHR_PORT_PHY_CONTROL_POWER_LOW 3869 #define BCM_PORT_PHY_CONTROL_POWER_AUTO _SHR_PORT_PHY_CONTROL_POWER_AUTO 3870 #define BCM_PORT_PHY_CONTROL_POWER_AUTO_DISABLE _SHR_PORT_PHY_CONTROL_POWER_AUTO_DISABLE 3871 #define BCM_PORT_PHY_CONTROL_POWER_AUTO_FULL _SHR_PORT_PHY_CONTROL_POWER_AUTO_FULL 3872 #define BCM_PORT_PHY_CONTROL_POWER_AUTO_LOW _SHR_PORT_PHY_CONTROL_POWER_AUTO_LOW 3873 #define BCM_PORT_PHY_CONTROL_POWER_AUTO_SLEEP_TIME _SHR_PORT_PHY_CONTROL_POWER_AUTO_SLEEP_TIME 3874 #define BCM_PORT_PHY_CONTROL_POWER_AUTO_WAKE_TIME _SHR_PORT_PHY_CONTROL_POWER_AUTO_WAKE_TIME 3875 #define BCM_PORT_PHY_CONTROL_LOOPBACK_EXTERNAL _SHR_PORT_PHY_CONTROL_LOOPBACK_EXTERNAL 3876 #define BCM_PORT_PHY_CONTROL_EDC_CONFIG_NONE _SHR_PORT_PHY_CONTROL_EDC_CONFIG_NONE 3877 #define BCM_PORT_PHY_CONTROL_EDC_CONFIG_HARDWARE _SHR_PORT_PHY_CONTROL_EDC_CONFIG_HARDWARE 3878 #define BCM_PORT_PHY_CONTROL_EDC_CONFIG_SOFTWARE _SHR_PORT_PHY_CONTROL_EDC_CONFIG_SOFTWARE 3879 #define BCM_PORT_PHY_CONTROL_EDC_MODE _SHR_PORT_PHY_CONTROL_EDC_MODE 3880 #define BCM_PORT_PHY_CONTROL_CLOCK_ENABLE _SHR_PORT_PHY_CONTROL_CLOCK_ENABLE 3881 #define BCM_PORT_PHY_CONTROL_CLOCK_SECONDARY_ENABLE _SHR_PORT_PHY_CONTROL_CLOCK_SECONDARY_ENABLE 3882 #define BCM_PORT_PHY_CONTROL_CLOCK_FREQUENCY _SHR_PORT_PHY_CONTROL_CLOCK_FREQUENCY 3883 #define BCM_PORT_PHY_CONTROL_CLOCK_MODE_AUTO _SHR_PORT_PHY_CONTROL_CLOCK_MODE_AUTO 3884 #define BCM_PORT_PHY_CONTROL_CLOCK_AUTO_SECONDARY _SHR_PORT_PHY_CONTROL_CLOCK_AUTO_SECONDARY 3885 #define BCM_PORT_PHY_CONTROL_CLOCK_SOURCE _SHR_PORT_PHY_CONTROL_CLOCK_SOURCE 3886 #define BCM_PORT_PHY_CONTROL_PORT_PRIMARY _SHR_PORT_PHY_CONTROL_PORT_PRIMARY 3887 #define BCM_PORT_PHY_CONTROL_PORT_OFFSET _SHR_PORT_PHY_CONTROL_PORT_OFFSET 3888 #define BCM_PORT_PHY_CONTROL_LINKDOWN_TRANSMIT _SHR_PORT_PHY_CONTROL_LINKDOWN_TRANSMIT 3889 #define BCM_PORT_PHY_CONTROL_EDC_CONFIG _SHR_PORT_PHY_CONTROL_EDC_CONFIG 3890 #define BCM_PORT_PHY_CONTROL_SUPER_ISOLATE _SHR_PORT_PHY_CONTROL_SUPER_ISOLATE 3891 #define BCM_PORT_PHY_CONTROL_SOFT_RESET _SHR_PORT_PHY_CONTROL_SOFT_RESET 3892 #define BCM_PORT_PHY_CONTROL_EEE _SHR_PORT_PHY_CONTROL_EEE 3893 #define BCM_PORT_PHY_CONTROL_EEE_AUTO _SHR_PORT_PHY_CONTROL_EEE_AUTO 3894 #define BCM_PORT_PHY_CONTROL_EEE_AUTO_IDLE_THRESHOLD _SHR_PORT_PHY_CONTROL_EEE_AUTO_IDLE_THRESHOLD 3895 #define BCM_PORT_PHY_CONTROL_EEE_AUTO_BUFFER_LIMIT _SHR_PORT_PHY_CONTROL_EEE_AUTO_BUFFER_LIMIT 3896 #define BCM_PORT_PHY_CONTROL_EEE_AUTO_FIXED_LATENCY _SHR_PORT_PHY_CONTROL_EEE_AUTO_FIXED_LATENCY 3897 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_WAKE_TIME _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_WAKE_TIME 3898 #define BCM_PORT_PHY_CONTROL_EEE_RECEIVE_WAKE_TIME _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_WAKE_TIME 3899 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_SLEEP_TIME _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_SLEEP_TIME 3900 #define BCM_PORT_PHY_CONTROL_EEE_RECEIVE_SLEEP_TIME _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_SLEEP_TIME 3901 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_QUIET_TIME _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_QUIET_TIME 3902 #define BCM_PORT_PHY_CONTROL_EEE_RECEIVE_QUIET_TIME _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_QUIET_TIME 3903 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_REFRESH_TIME _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_REFRESH_TIME 3904 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_EVENTS _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_EVENTS 3905 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_DURATION _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_DURATION 3906 #define BCM_PORT_PHY_CONTROL_EEE_RECEIVE_EVENTS _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_EVENTS 3907 #define BCM_PORT_PHY_CONTROL_EEE_RECEIVE_DURATION _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_DURATION 3908 #define BCM_PORT_PHY_CONTROL_EEE_STATISTICS_CLEAR _SHR_PORT_PHY_CONTROL_EEE_STATISTICS_CLEAR 3909 #define BCM_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MAX _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MAX 3910 #define BCM_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MODE _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MODE 3911 #define BCM_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_VALUE _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_VALUE 3912 #define BCM_PORT_PHY_CONTROL_PARALLEL_DETECTION _SHR_PORT_PHY_CONTROL_PARALLEL_DETECTION 3913 #define BCM_PORT_PHY_CONTROL_PARALLEL_DETECTION_10G _SHR_PORT_PHY_CONTROL_PARALLEL_DETECTION_10G 3914 #define BCM_PORT_PHY_CONTROL_LOOPBACK_INTERNAL _SHR_PORT_PHY_CONTROL_LOOPBACK_INTERNAL 3915 #define BCM_PORT_PHY_CONTROL_LOOPBACK_REMOTE _SHR_PORT_PHY_CONTROL_LOOPBACK_REMOTE 3916 #define BCM_PORT_PHY_CONTROL_LOOPBACK_REMOTE_PCS_BYPASS _SHR_PORT_PHY_CONTROL_LOOPBACK_REMOTE_PCS_BYPASS 3917 #define BCM_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION 3918 #define BCM_PORT_PHY_CONTROL_FEC_OFF _SHR_PORT_PHY_CONTROL_FEC_OFF 3919 #define BCM_PORT_PHY_CONTROL_FEC_ON _SHR_PORT_PHY_CONTROL_FEC_ON 3920 #define BCM_PORT_PHY_CONTROL_FEC_AUTO _SHR_PORT_PHY_CONTROL_FEC_AUTO 3921 #define BCM_PORT_PHY_CONTROL_SCRAMBLER _SHR_PORT_PHY_CONTROL_SCRAMBLER 3922 #define BCM_PORT_PHY_CONTROL_CUSTOM1 _SHR_PORT_PHY_CONTROL_CUSTOM1 3923 #define BCM_PORT_PHY_CONTROL_BERT_PATTERN _SHR_PORT_PHY_CONTROL_BERT_PATTERN 3924 #define BCM_PORT_PHY_CONTROL_BERT_RUN _SHR_PORT_PHY_CONTROL_BERT_RUN 3925 #define BCM_PORT_PHY_CONTROL_BERT_CRPAT _SHR_PORT_PHY_CONTROL_BERT_CRPAT 3926 #define BCM_PORT_PHY_CONTROL_BERT_CJPAT _SHR_PORT_PHY_CONTROL_BERT_CJPAT 3927 #define BCM_PORT_PHY_CONTROL_BERT_PACKET_SIZE _SHR_PORT_PHY_CONTROL_BERT_PACKET_SIZE 3928 #define BCM_PORT_PHY_CONTROL_BERT_IPG _SHR_PORT_PHY_CONTROL_BERT_IPG 3929 #define BCM_PORT_PHY_CONTROL_BERT_TX_PACKETS _SHR_PORT_PHY_CONTROL_BERT_TX_PACKETS 3930 #define BCM_PORT_PHY_CONTROL_BERT_RX_PACKETS _SHR_PORT_PHY_CONTROL_BERT_RX_PACKETS 3931 #define BCM_PORT_PHY_CONTROL_BERT_RX_ERROR_BITS _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_BITS 3932 #define BCM_PORT_PHY_CONTROL_BERT_RX_ERROR_BYTES _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_BYTES 3933 #define BCM_PORT_PHY_CONTROL_BERT_RX_ERROR_PACKETS _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_PACKETS 3934 #define BCM_PORT_PHY_CONTROL_PON_LASER_TX_POWER_TIME _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER_TIME 3935 #define BCM_PORT_PHY_CONTROL_PON_LASER_TX_POWER_MODE _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER_MODE 3936 #define BCM_PORT_PHY_CONTROL_PON_LASER_TX_STATUS _SHR_PORT_PHY_CONTROL_PON_LASER_TX_STATUS 3937 #define BCM_PORT_PHY_CONTROL_PON_LASER_RX_STATE _SHR_PORT_PHY_CONTROL_PON_LASER_RX_STATE 3938 #define BCM_PORT_PHY_CONTROL_PON_LASER_TRANCEIVER_TEMP _SHR_PORT_PHY_CONTROL_PON_LASER_TRANCEIVER_TEMP 3939 #define BCM_PORT_PHY_CONTROL_PON_LASER_SUPPLY_VOLTAGE _SHR_PORT_PHY_CONTROL_PON_LASER_SUPPLY_VOLTAGE 3940 #define BCM_PORT_PHY_CONTROL_PON_LASER_TX_BIAS _SHR_PORT_PHY_CONTROL_PON_LASER_TX_BIAS 3941 #define BCM_PORT_PHY_CONTROL_PON_LASER_TX_POWER _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER 3942 #define BCM_PORT_PHY_CONTROL_PON_LASER_RX_POWER _SHR_PORT_PHY_CONTROL_PON_LASER_RX_POWER 3943 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_STATE 3944 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_REPORT_THRESHOLD 3945 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_CLEAR_THRESHOLD 3946 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_STATE 3947 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_REPORT_THRESHOLD 3948 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_CLEAR_THRESHOLD 3949 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_STATE 3950 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_REPORT_THRESHOLD 3951 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_CLEAR_THRESHOLD 3952 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_STATE 3953 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_REPORT_THRESHOLD 3954 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_CLEAR_THRESHOLD 3955 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_STATE 3956 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_REPORT_THRESHOLD 3957 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_CLEAR_THRESHOLD 3958 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_STATE 3959 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_REPORT_THRESHOLD 3960 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_CLEAR_THRESHOLD 3961 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_STATE 3962 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_REPORT_THRESHOLD 3963 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_CLEAR_THRESHOLD 3964 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_STATE 3965 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_REPORT_THRESHOLD 3966 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_CLEAR_THRESHOLD 3967 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_STATE 3968 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_REPORT_THRESHOLD 3969 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_CLEAR_THRESHOLD 3970 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_STATE 3971 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_REPORT_THRESHOLD 3972 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_CLEAR_THRESHOLD 3973 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_STATE 3974 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_REPORT_THRESHOLD 3975 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_CLEAR_THRESHOLD 3976 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_STATE 3977 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_REPORT_THRESHOLD 3978 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_CLEAR_THRESHOLD 3979 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_STATE 3980 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_REPORT_THRESHOLD 3981 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_CLEAR_THRESHOLD 3982 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_STATE 3983 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_REPORT_THRESHOLD 3984 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_CLEAR_THRESHOLD 3985 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_STATE 3986 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_REPORT_THRESHOLD 3987 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_CLEAR_THRESHOLD 3988 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_STATE 3989 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_REPORT_THRESHOLD 3990 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_CLEAR_THRESHOLD 3991 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_STATE 3992 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_REPORT_THRESHOLD 3993 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_CLEAR_THRESHOLD 3994 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_STATE 3995 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_REPORT_THRESHOLD 3996 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_CLEAR_THRESHOLD 3997 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_STATE 3998 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_REPORT_THRESHOLD 3999 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_CLEAR_THRESHOLD 4000 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_STATE 4001 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_REPORT_THRESHOLD 4002 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_CLEAR_THRESHOLD 4003 #define BCM_PORT_PHY_CONTROL_DLL_POWER_AUTO _SHR_PORT_PHY_CONTROL_DLL_POWER_AUTO 4004 #define BCM_PORT_PHY_CONTROL_TX_LANE_SQUELCH _SHR_PORT_PHY_CONTROL_TX_LANE_SQUELCH 4005 #define BCM_PORT_PHY_CONTROL_RX_LANE_SQUELCH _SHR_PORT_PHY_CONTROL_RX_LANE_SQUELCH 4006 #define BCM_PORT_PHY_CONTROL_DRIVER_POST2_CURRENT _SHR_PORT_PHY_CONTROL_DRIVER_POST2_CURRENT 4007 #define BCM_PORT_PHY_CONTROL_RX_PPM _SHR_PORT_PHY_CONTROL_RX_PPM 4008 #define BCM_PORT_PHY_CONTROL_RX_POLARITY _SHR_PORT_PHY_CONTROL_RX_POLARITY 4009 #define BCM_PORT_PHY_CONTROL_TX_POLARITY _SHR_PORT_PHY_CONTROL_TX_POLARITY 4010 #define BCM_PORT_PHY_CONTROL_RX_RESET _SHR_PORT_PHY_CONTROL_RX_RESET 4011 #define BCM_PORT_PHY_CONTROL_TX_RESET _SHR_PORT_PHY_CONTROL_TX_RESET 4012 #define BCM_PORT_PHY_CONTROL_CL72 _SHR_PORT_PHY_CONTROL_CL72 4013 #define BCM_PORT_PHY_CONTROL_CL72_STATUS _SHR_PORT_PHY_CONTROL_CL72_STATUS 4014 #define BCM_PORT_PHY_CONTROL_LANE_SWAP _SHR_PORT_PHY_CONTROL_LANE_SWAP 4015 #define BCM_PORT_PHY_CONTROL_RX_PEAK_FILTER _SHR_PORT_PHY_CONTROL_RX_PEAK_FILTER 4016 #define BCM_PORT_PHY_CONTROL_RX_LOW_FREQ_PEAK_FILTER _SHR_PORT_PHY_CONTROL_RX_LOW_FREQ_PEAK_FILTER 4017 #define BCM_PORT_PHY_CONTROL_RX_VGA _SHR_PORT_PHY_CONTROL_RX_VGA 4018 #define BCM_PORT_PHY_CONTROL_RX_TAP1 _SHR_PORT_PHY_CONTROL_RX_TAP1 4019 #define BCM_PORT_PHY_CONTROL_RX_TAP2 _SHR_PORT_PHY_CONTROL_RX_TAP2 4020 #define BCM_PORT_PHY_CONTROL_RX_TAP3 _SHR_PORT_PHY_CONTROL_RX_TAP3 4021 #define BCM_PORT_PHY_CONTROL_RX_TAP4 _SHR_PORT_PHY_CONTROL_RX_TAP4 4022 #define BCM_PORT_PHY_CONTROL_RX_TAP5 _SHR_PORT_PHY_CONTROL_RX_TAP5 4023 #define BCM_PORT_PHY_CONTROL_RX_TAP6 _SHR_PORT_PHY_CONTROL_RX_TAP6 4024 #define BCM_PORT_PHY_CONTROL_RX_VGA_RELEASE _SHR_PORT_PHY_CONTROL_RX_VGA_RELEASE 4025 #define BCM_PORT_PHY_CONTROL_RX_TAP1_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP1_RELEASE 4026 #define BCM_PORT_PHY_CONTROL_RX_TAP2_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP2_RELEASE 4027 #define BCM_PORT_PHY_CONTROL_RX_TAP3_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP3_RELEASE 4028 #define BCM_PORT_PHY_CONTROL_RX_TAP4_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP4_RELEASE 4029 #define BCM_PORT_PHY_CONTROL_RX_TAP5_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP5_RELEASE 4030 #define BCM_PORT_PHY_CONTROL_RX_TAP6_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP6_RELEASE 4031 #define BCM_PORT_PHY_CONTROL_RX_ADAPTATION_RESUME _SHR_PORT_PHY_CONTROL_RX_ADAPTATION_RESUME 4032 #define BCM_PORT_PHY_CONTROL_RX_PLUS1_SLICER _SHR_PORT_PHY_CONTROL_RX_PLUS1_SLICER 4033 #define BCM_PORT_PHY_CONTROL_RX_MINUS1_SLICER _SHR_PORT_PHY_CONTROL_RX_MINUS1_SLICER 4034 #define BCM_PORT_PHY_CONTROL_RX_D_SLICER _SHR_PORT_PHY_CONTROL_RX_D_SLICER 4035 #define BCM_PORT_PHY_CONTROL_RX_SIGNAL_DETECT _SHR_PORT_PHY_CONTROL_RX_SIGNAL_DETECT 4036 #define BCM_PORT_PHY_CONTROL_RX_SEQ_DONE _SHR_PORT_PHY_CONTROL_RX_SEQ_DONE 4037 #define BCM_PORT_PHY_CONTROL_RX_SEQ_TOGGLE _SHR_PORT_PHY_CONTROL_RX_SEQ_TOGGLE 4038 #define BCM_PORT_PHY_CONTROL_DUMP _SHR_PORT_PHY_CONTROL_DUMP 4039 #define BCM_PORT_PHY_CONTROL_FIRMWARE_MODE _SHR_PORT_PHY_CONTROL_FIRMWARE_MODE 4040 #define BCM_PORT_PHY_CONTROL_DFE _SHR_PORT_PHY_CONTROL_DFE 4041 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_20BIT _SHR_PORT_PHY_CONTROL_TX_PATTERN_20BIT 4042 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_256BIT _SHR_PORT_PHY_CONTROL_TX_PATTERN_256BIT 4043 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA0 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA0 4044 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA1 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA1 4045 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA2 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA2 4046 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA3 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA3 4047 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA4 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA4 4048 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA5 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA5 4049 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA6 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA6 4050 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA7 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA7 4051 #define BCM_PORT_PHY_CONTROL_PHASE_INTERP _SHR_PORT_PHY_CONTROL_PHASE_INTERP 4052 #define BCM_PORT_PHY_CONTROL_TX_PPM_ADJUST _SHR_PORT_PHY_CONTROL_TX_PPM_ADJUST 4053 #define BCM_PORT_PHY_CONTROL_SOFTWARE_RX_LOS _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS 4054 #define BCM_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_LINK_WAIT_TIMER_US _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_LINK_WAIT_TIMER_US 4055 #define BCM_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_RESTART_TIMER_US _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_RESTART_TIMER_US 4056 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_ENABLE _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_ENABLE 4057 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_INVERT_DATA _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_INVERT_DATA 4058 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_POLYNOMIAL _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_POLYNOMIAL 4059 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_ENABLE _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_ENABLE 4060 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_INVERT_DATA _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_INVERT_DATA 4061 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_POLYNOMIAL _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_POLYNOMIAL 4062 #define BCM_PORT_PHY_CONTROL_RX_PEAK_FILTER_TEMP_COMP _SHR_PORT_PHY_CONTROL_RX_PEAK_FILTER_TEMP_COMP 4063 #define BCM_PORT_PHY_CONTROL_CL73_FSM_AUTO_RECOVER _SHR_PORT_PHY_CONTROL_CL73_FSM_AUTO_RECOVER 4064 #define BCM_PORT_PHY_CONTROL_DRIVER_SUPPLY _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY 4065 #define BCM_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_1_0V _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_1_0V 4066 #define BCM_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_0V_700MV _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_0V_700MV 4067 #define BCM_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_700MV _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_700MV 4068 #define BCM_PORT_PHY_CONTROL_DIGITAL_TEMP _SHR_PORT_PHY_CONTROL_DIGITAL_TEMP 4069 #define BCM_PORT_PHY_CONTROL_ANALOG_TEMP _SHR_PORT_PHY_CONTROL_ANALOG_TEMP 4070 #define BCM_PORT_PHY_CONTROL_MGBASET_802P3BZ_PRIORITY _SHR_PORT_PHY_CONTROL_MGBASET_802P3BZ_PRIORITY 4071 #define BCM_PORT_PHY_CONTROL_RX_LOS_NONE _SHR_PORT_PHY_CONTROL_RX_LOS_NONE 4072 #define BCM_PORT_PHY_CONTROL_RX_LOS_SOFTWARE _SHR_PORT_PHY_CONTROL_RX_LOS_SOFTWARE 4073 #define BCM_PORT_PHY_CONTROL_RX_LOS_FIRMWARE _SHR_PORT_PHY_CONTROL_RX_LOS_FIRMWARE 4074 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE _SHR_PORT_PHY_CONTROL_AUTONEG_MODE 4075 #define BCM_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE 4076 #define BCM_PORT_PHY_CONTROL_PRBS_TX_ENABLE _SHR_PORT_PHY_CONTROL_PRBS_TX_ENABLE 4077 #define BCM_PORT_PHY_CONTROL_PRBS_TX_INVERT_DATA _SHR_PORT_PHY_CONTROL_PRBS_TX_INVERT_DATA 4078 #define BCM_PORT_PHY_CONTROL_PRBS_POLYNOMIAL _SHR_PORT_PHY_CONTROL_PRBS_POLYNOMIAL 4079 #define BCM_PORT_PHY_CONTROL_PRBS_RX_STATUS _SHR_PORT_PHY_CONTROL_PRBS_RX_STATUS 4080 #define BCM_PORT_PHY_CONTROL_PRBS_RX_ENABLE _SHR_PORT_PHY_CONTROL_PRBS_RX_ENABLE 4081 #define BCM_PORT_PHY_CONTROL_PRBS_RX_INVERT_DATA _SHR_PORT_PHY_CONTROL_PRBS_RX_INVERT_DATA 4082 #define BCM_PORT_PHY_CONTROL_PRBS_CHECK_MODE _SHR_PORT_PHY_CONTROL_PRBS_CHECK_MODE 4083 #define BCM_PORT_PHY_CONTROL_MOD_AUTO_DETECT_ENABLE _SHR_PORT_PHY_CONTROL_MOD_AUTO_DETECT_ENABLE 4084 #define BCM_PORT_PHY_CONTROL_TX_FIR_PRE _SHR_PORT_PHY_CONTROL_TX_FIR_PRE 4085 #define BCM_PORT_PHY_CONTROL_TX_FIR_MAIN _SHR_PORT_PHY_CONTROL_TX_FIR_MAIN 4086 #define BCM_PORT_PHY_CONTROL_TX_FIR_POST _SHR_PORT_PHY_CONTROL_TX_FIR_POST 4087 #define BCM_PORT_PHY_CONTROL_TX_FIR_POST2 _SHR_PORT_PHY_CONTROL_TX_FIR_POST2 4088 #define BCM_PORT_PHY_CONTROL_TX_FIR_POST3 _SHR_PORT_PHY_CONTROL_TX_FIR_POST3 4089 #define BCM_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE 4090 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PMA_OS _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PMA_OS 4091 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_SCR_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_SCR_MODE 4092 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_ENCODE_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_ENCODE_MODE 4093 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL48_CHECK_END _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL48_CHECK_END 4094 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_BLK_SYNC_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_BLK_SYNC_MODE 4095 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_REORDER_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_REORDER_MODE 4096 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL36_EN _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL36_EN 4097 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESCR1_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESCR1_MODE 4098 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_DEC1_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DEC1_MODE 4099 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESKEW_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESKEW_MODE 4100 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_MODE 4101 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_BYTE_DEL _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_BYTE_DEL 4102 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_BRCM64B66_DESCR _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_BRCM64B66_DESCR 4103 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_SGMII_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_SGMII_MODE 4104 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT0 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT0 4105 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT1 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT1 4106 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT0 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT0 4107 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT1 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT1 4108 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_MAC_CGC _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_MAC_CGC 4109 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_REPCNT _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_REPCNT 4110 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CRDTEN _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CREDTEN 4111 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CLKCNT _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CLKCNT 4112 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CGC _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CGC 4113 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL72_EN _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL72_EN 4114 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PLL_DIVIDER _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PLL_DIVIDER 4115 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLEAR _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLEAR 4116 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_ENTRY _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_ENTRY 4117 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_HCD _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_HCD 4118 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PMA_OS _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PMA_OS 4119 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_SCR_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_SCR_MODE 4120 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_ENCODE_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_ENCODE_MODE 4121 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_CL48_CHECK_END _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL48_CHECK_END 4122 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_BLK_SYNC_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_BLK_SYNC_MODE 4123 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_REORDER_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_REORDER_MODE 4124 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_CL36_EN _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL36_EN 4125 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_DESCR1_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESCR1_MODE 4126 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_DEC1_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DEC1_MODE 4127 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_DESKEW_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESKEW_MODE 4128 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_MODE 4129 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_BYTE_DEL _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_BYTE_DEL 4130 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_BRCM64B66_DESCR _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_BRCM64B66_DESCR 4131 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_SGMII_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_SGMII_MODE 4132 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT0 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT0 4133 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT1 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT1 4134 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT0 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT0 4135 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT1 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT1 4136 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_MAC_CGC _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_MAC_CGC 4137 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_REPCNT _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_REPCNT 4138 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CRDTEN _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CREDTEN 4139 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CLKCNT _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CLKCNT 4140 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CGC _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CGC 4141 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_CL72_EN _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL72_EN 4142 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_NUM_OF_LANES _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_NUM_OF_LANES 4143 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PLL_DIVIDER _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PLL_DIVIDER 4144 #define BCM_PORT_PHY_CONTROL_LOOPBACK_PMD _SHR_PORT_PHY_CONTROL_LOOPBACK_PMD 4145 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_GEN_ENABLE _SHR_PORT_PHY_CONTROL_TX_PATTERN_GEN_ENABLE 4146 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_LENGTH _SHR_PORT_PHY_CONTROL_TX_PATTERN_LENGTH 4147 #define BCM_PORT_PHY_CONTROL_INTR_MASK _SHR_PORT_PHY_CONTROL_INTR_MASK /* PHY interrupt enable 4148 mask (a bit set to 1 4149 means interrupt 4150 enabled) */ 4151 #define BCM_PORT_PHY_CONTROL_INTR_STATUS _SHR_PORT_PHY_CONTROL_INTR_STATUS /* PHY interrupt control 4152 mask (write 1 to 4153 clear) */ 4154 #define BCM_PORT_PHY_CONTROL_XSW_LANE_MAP _SHR_PORT_PHY_CONTROL_XSW_LANE_MAP /* Cross-switch lane map. 4155 Bits[3:0] map Rx lane 4156 0, bits [7:4] map Rx 4157 lane 1, etc. Default 4158 mapping is 0x76543210. */ 4159 #define BCM_PORT_PHY_CONTROL_FIRMWARE_DFE_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_DFE_ENABLE /* enable digital 4160 feedback equalization */ 4161 #define BCM_PORT_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE /* enable digital 4162 feedback equalization */ 4163 #define BCM_PORT_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE /* enable digital 4164 feedback equalization */ 4165 #define BCM_PORT_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE /* enable cl72 restart 4166 timeout */ 4167 #define BCM_PORT_PHY_CONTROL_FIRMWARE_AN_CL72_TX_INIT_SKIP_ON_RESTART _SHR_PORT_PHY_CONTROL_FIRMWARE_AN_CL72_TX_INIT_SKIP_ON_RESTART /* skip the TXFIR 4168 initialization in a 4169 restart event during 4170 the AN link training */ 4171 #define BCM_PORT_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE /* enable auto polarity 4172 for cl72 training */ 4173 #define BCM_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE /* enable firmware lane 4174 config rx forced 4175 extended reach */ 4176 #define BCM_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE /* enable firmware lane 4177 config rx forced 4178 normal reach */ 4179 #define BCM_PORT_PHY_CONTROL_GPIO_CONFIG _SHR_PORT_PHY_CONTROL_GPIO_CONFIG /* Config GPIO PINs. Bits 4180 [3:0] controls GPIO 4181 pin 0, bits [7:4] 4182 controls GPIO pin 1, 4183 etc */ 4184 #define BCM_PORT_PHY_CONTROL_GPIO_VALUE _SHR_PORT_PHY_CONTROL_GPIO_VALUE /* Set value for GPIO 4185 PINs. Bits [3:0] 4186 controls GPIO pin 0, 4187 bits [7:4] controls 4188 GPIO pin 1, etc */ 4189 #define BCM_PORT_PHY_CONTROL_GPIO_CONFIG_DISABLED _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_DISABLED 4190 #define BCM_PORT_PHY_CONTROL_GPIO_CONFIG_OUTPUT _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_OUTPUT 4191 #define BCM_PORT_PHY_CONTROL_GPIO_CONFIG_INPUT _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_INPUT 4192 #define BCM_PORT_PHY_CONTROL_PCS_MODE _SHR_PORT_PHY_CONTROL_PCS_MODE 4193 #define BCM_PORT_PHY_CONTROL_AUTONEG_ALLOW_PLL_CHANGE _SHR_PORT_PHY_CONTROL_AUTONEG_ALLOW_PLL_CHANGE 4194 #define BCM_PORT_PHY_CONTROL_MEDIUM_TYPE _SHR_PORT_PHY_CONTROL_MEDIUM_TYPE 4195 #define BCM_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL91 _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL91 4196 #define BCM_PORT_PHY_CONTROL_AUTONEG_FEC_OVERRIDE _SHR_PORT_PHY_CONTROL_AUTONEG_FEC_OVERRIDE /* FEC override for 100G 4197 AN noFEC mode */ 4198 #define BCM_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL108 _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL108 4199 #define BCM_PORT_PHY_CONTROL_FEC_BYPASS_INDICATION_ENABLE _SHR_PORT_PHY_CONTROL_FEC_BYPASS_INDICATION_ENABLE 4200 #define BCM_PORT_PHY_CONTROL_UNRELIABLE_LOS _SHR_PORT_PHY_CONTROL_UNRELIABLE_LOS 4201 #define BCM_PORT_PHY_CONTROL_FORCED_SPEED_LINE_SIDE _SHR_PORT_PHY_CONTROL_FORCED_SPEED_LINE_SIDE /* Set speed on line side 4202 of external PHY in 4203 case of EBE mode only */ 4204 #define BCM_PORT_PHY_CONTROL_EGRESS_FLOW_CONTROL_MODE _SHR_PORT_PHY_EGRESS_FLOW_CONTROL_MODE /* Supported flow modes 4205 as defined in 4206 bcm_port_phy_control_flow_control_mode_t. */ 4207 #define BCM_PORT_PHY_CONTROL_INGRESS_FLOW_CONTROL_MODE _SHR_PORT_PHY_INGRESS_FLOW_CONTROL_MODE /* Supported flow modes 4208 as defined in 4209 bcm_port_phy_control_flow_control_mode_t */ 4210 #define BCM_PORT_PHY_CONTROL_PSM_COS_BMP _SHR_PORT_PHY_CONTROL_PSM_COS_BMP 4211 #define BCM_PORT_PHY_CONTROL_AUTONEG_OUI _SHR_PORT_PHY_CONTROL_AUTONEG_OUI 4212 #define BCM_PORT_PHY_CONTROL_AUTONEG_LINE_SIDE _SHR_PORT_PHY_CONTROL_AUTONEG_LINE_SIDE /* Valid in case of EBE 4213 mode of MT2 PHY device 4214 and can be applied to 4215 enable Autoneg only on 4216 line side of MT2 4217 ports. */ 4218 #define BCM_PORT_PHY_CONTROL_FEC_CORRECTED_BLOCK_COUNT _SHR_PORT_PHY_CONTROL_FEC_CORRECTED_BLOCK_COUNT /* CL74 FEC corrected 4219 block count. */ 4220 #define BCM_PORT_PHY_CONTROL_FEC_UNCORRECTED_BLOCK_COUNT _SHR_PORT_PHY_CONTROL_FEC_UNCORRECTED_BLOCK_COUNT /* CL74 FEC uncorrected 4221 block count. */ 4222 #define BCM_PORT_PHY_CONTROL_FEC_CORRECTED_CODEWORD_COUNT _SHR_PORT_PHY_CONTROL_FEC_CORRECTED_CODEWORD_COUNT /* CL91 FEC corrected 4223 code word count. */ 4224 #define BCM_PORT_PHY_CONTROL_FEC_UNCORRECTED_CODEWORD_COUNT _SHR_PORT_PHY_CONTROL_FEC_UNCORRECTED_CODEWORD_COUNT /* CL91 FEC uncorrected 4225 code word count. */ 4226 #define BCM_PORT_PHY_CONTROL_TX_PAM4_PRECODER_ENABLE _SHR_PORT_PHY_CONTROL_TX_PAM4_PRECODER_ENABLE /* TX pam4 precoder 4227 enable */ 4228 #define BCM_PORT_PHY_CONTROL_LP_TX_PRECODER_ENABLE _SHR_PORT_PHY_CONTROL_LP_TX_PRECODER_ENABLE /* indicate link partner 4229 tx has precoder 4230 enabled */ 4231 #define BCM_PORT_PHY_CONTROL_PAM4_TX_PATTERN_ENABLE _SHR_PORT_PHY_CONTROL_PAM4_TX_PATTERN_ENABLE /* PAM4 test pattern 4232 enable */ 4233 #define BCM_PORT_PHY_CONTROL_FEC_SYMBOL_ERROR_COUNT _SHR_PORT_PHY_CONTROL_FEC_SYMBOL_ERROR_COUNT /* fec symbol error count */ 4234 #define BCM_PORT_PHY_CONTROL_TX_FIR_MODE _SHR_PORT_PHY_CONTROL_TX_FIR_MODE /* tx fir mode */ 4235 #define BCM_PORT_PHY_CONTROL_TX_FIR_PRE2 _SHR_PORT_PHY_CONTROL_TX_FIR_PRE2 /* tx fir pre2 tap */ 4236 #define BCM_PORT_PHY_CONTROL_RX_HIGH_FREQ_PEAK_FILTER _SHR_PORT_PHY_CONTROL_RX_HIGH_FREQ_PEAK_FILTER /* rx high freq peaking 4237 filter */ 4238 #define BCM_PORT_PHY_CONTROL_FAST_BER_PROJ _SHR_PORT_PHY_CONTROL_FAST_BER_PROJ /* get the BER projection 4239 using PRBS */ 4240 #define BCM_PORT_PHY_CONTROL_CHANNEL_LOSS_HINT _SHR_PORT_PHY_CONTROL_CHANNEL_LOSS_HINT /* specify the channel db 4241 loss */ 4242 #define BCM_PORT_PHY_CONTROL_LINK_TRAINING_INIT_TX_FIR_POST _SHR_PORT_PHY_CONTROL_LINK_TRAINING_INIT_TX_FIR_POST /* set the tx fir post 4243 initial value in uC 4244 RAM for link training */ 4245 #define BCM_PORT_PHY_CONTROL_PCS_RESET _SHR_PORT_PHY_CONTROL_PCS_RESET /* toggle speed change */ 4246 #define BCM_PORT_PHY_CONTROL_PFC_USE_IP_COS _SHR_PORT_PHY_CONTROL_PFC_USE_IP_COS /* Use IP COS mapping in 4247 case of PFC mode */ 4248 #define BCM_PORT_PHY_CONTROL_BASE_R_FEC_ECC_INTR_ENABLE _SHR_PORT_PHY_CONTROL_BASE_R_FEC_ECC_INTR_ENABLE /* enable/disable base R 4249 fec ECC intetrrupt */ 4250 #define BCM_PORT_PHY_CONTROL_PMD_DIAG_DEBUG_LANE_EVENT_LOG_LEVEL _SHR_PORT_PHY_CONTROL_PMD_DIAG_DEBUG_LANE_EVENT_LOG_LEVEL /* set the PMD debug log 4251 level (valid value 0 4252 to 6, default is 2), 4253 user should call port 4254 disable first, then 4255 change the debug 4256 level, followed with 4257 port enable call */ 4258 #define BCM_PORT_PHY_CONTROL_FLEXE_50G_NOFEC_20K_AM_SPACING_ENABLE _SHR_PORT_PHY_CONTROL_FLEXE_50G_NOFEC_20K_AM_SPACING_ENABLE /* configure the AM 4259 spacing to 20K for 50G 4260 (2x25G) without FEC on 4261 FLEXE */ 4262 #define BCM_PORT_PHY_CONTROL_FEC_CORRUPTION_PERIOD _SHR_PORT_PHY_CONTROL_FEC_CORRUPTION_PERIOD /* config FEC corruption 4263 period */ 4264 #define BCM_PORT_PHY_CONTROL_FW_AN_FORCE_EXTENDED_REACH_ENABLE _SHR_PORT_PHY_CONTROL_FW_AN_FORCE_EXTENDED_REACH_ENABLE /* enabling Force 4265 Extended Reach in 4266 AutoNeg mode */ 4267 #define BCM_PORT_PHY_CONTROL_FW_AN_FORCE_NORMAL_REACH_ENABLE _SHR_PORT_PHY_CONTROL_FW_AN_FORCE_NORMAL_REACH_ENABLE /* enabling Force Normal 4268 Reach in AutoNeg mode */ 4269 4270 #define BCM_PORT_PHY_FIRMWARE_DEFAULT _SHR_PORT_PHY_FIRMWARE_DEFAULT /* firmware mode control 4271 default */ 4272 #define BCM_PORT_PHY_FIRMWARE_SFP_OPT_SR4 _SHR_PORT_PHY_FIRMWARE_SFP_OPT_SR4 /* optical short range */ 4273 #define BCM_PORT_PHY_FIRMWARE_SFP_DAC _SHR_PORT_PHY_FIRMWARE_SFP_DAC /* direct attach copper */ 4274 #define BCM_PORT_PHY_FIRMWARE_XLAUI _SHR_PORT_PHY_FIRMWARE_XLAUI /* 40G XLAUI mode */ 4275 #define BCM_PORT_PHY_FIRMWARE_FORCE_OSDFE _SHR_PORT_PHY_FIRMWARE_FORCE_OSDFE /* force over sample 4276 digital feedback 4277 equalization */ 4278 #define BCM_PORT_PHY_FIRMWARE_FORCE_BRDFE _SHR_PORT_PHY_FIRMWARE_FORCE_BRDFE /* force baud rate 4279 digital feedback 4280 equalization */ 4281 #define BCM_PORT_PHY_FIRMWARE_SW_CL72 _SHR_PORT_PHY_FIRMWARE_SW_CL72 /* software cl72 with AN 4282 on */ 4283 #define BCM_PORT_PHY_FIRMWARE_CL72_WITHOUT_AN _SHR_PORT_PHY_FIRMWARE_CL72_WITHOUT_AN /* cl72 without AN */ 4284 4285 #define BCM_PORT_PHY_DFE_AUTO _SHR_PORT_PHY_DFE_AUTO /* Auto control of DFE by firmware */ 4286 #define BCM_PORT_PHY_DFE_FREEZE _SHR_PORT_PHY_DFE_FREEZE /* Freeze DFE to current values */ 4287 4288 #define BCM_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_DEFAULT _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_DEFAULT /* default drivermode */ 4289 #define BCM_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_NOT_SUPPORTED _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_NOT_SUPPORTED /* not supported 4290 drivermode */ 4291 #define BCM_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP /* half amp drivermode */ 4292 #define BCM_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP_HI_IMPED _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP_HI_IMPED /* high impedence half 4293 amp drivermode */ 4294 4295 #define BCM_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_OFF _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_OFF /* hg2 codec off */ 4296 #define BCM_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_8BYTE_IPG _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_8BYTE_IPG /* 8-byte IPG setting */ 4297 #define BCM_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_9BYTE_IPG _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_9BYTE_IPG /* 9-byte IPG setting */ 4298 4299 #define BCM_PORT_PHY_CONTROL_TX_FIR_MODE_INVALID _SHR_PORT_PHY_TX_FIR_MODE_INVALID /* Invalid TX mode */ 4300 #define BCM_PORT_PHY_CONTROL_TX_FIR_3TAP_MODE _SHR_PORT_PHY_TX_FIR_3TAP_MODE /* TX fir 3 tap mode */ 4301 #define BCM_PORT_PHY_CONTROL_TX_FIR_6TAP_MODE _SHR_PORT_PHY_TX_FIR_6TAP_MODE /* tx fir 6 tap mode */ 4302 4303 #define BCM_PORT_PHY_CONTROL_PAM4_TX_PATTERN_INVALID _SHR_PORT_PHY_PAM4_TX_PATTERN_INVALID /* Invalid PAM4 test 4304 pattern */ 4305 #define BCM_PORT_PHY_CONTROL_PAM4_TX_PATTERN_OFF _SHR_PORT_PHY_PAM4_TX_PATTERN_OFF /* PAM4 tx test pattern 4306 off */ 4307 #define BCM_PORT_PHY_CONTROL_PAM4_TX_PATTERN_JP03B _SHR_PORT_PHY_PAM4_TX_PATTERN_JP03B /* PAM4 tx pattern JP03B */ 4308 #define BCM_PORT_PHY_CONTROL_PAM4_TX_PATTERN_LINEAR _SHR_PORT_PHY_PAM4_TX_PATTERN_LINEAR /* PAM4 tx pattern linear */ 4309 4310 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37 /* Autoneg mode CL37 */ 4311 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM /* Autoneg mode CL37 & 4312 BAM */ 4313 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL73 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73 /* Autoneg mode CL73 */ 4314 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM /* Autoneg mode CL73 & 4315 BAM */ 4316 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73 /* Autoneg mode CL37 & 4317 CL73 */ 4318 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73_BAM _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73_BAM /* Autoneg mode CL37 & 4319 CL73 BAM */ 4320 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73 /* Autoneg mode CL37 BAM 4321 & CL73 */ 4322 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73_BAM _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73_BAM /* Autoneg mode CL37 BAM 4323 & CL73 BAM */ 4324 4325 #define BCM_PORT_PHY_CONTROL_AUTONEG_OUI_DEFAULT _SHR_PORT_PHY_CONTROL_AUTONEG_OUI_DEFAULT /* Autoneg OUI default */ 4326 4327 #ifndef BCM_HIDE_DISPATCHABLE 4328 4329 /* Set/Get PHY specific configurations. */ 4330 extern int bcm_port_phy_control_set( 4331 int unit, 4332 bcm_port_t port, 4333 bcm_port_phy_control_t type, 4334 uint32 value); 4335 4336 /* Set/Get PHY specific configurations. */ 4337 extern int bcm_port_phy_control_get( 4338 int unit, 4339 bcm_port_t port, 4340 bcm_port_phy_control_t type, 4341 uint32 *value); 4342 4343 /* Set the given firmware to the PHY's non-volatile storage device. */ 4344 extern int bcm_port_phy_firmware_set( 4345 int unit, 4346 bcm_port_t port, 4347 uint32 flags, 4348 int offset, 4349 uint8 *array, 4350 int length); 4351 4352 /* Get the GPORT ID for the specified local port number. */ 4353 extern int bcm_port_gport_get( 4354 int unit, 4355 bcm_port_t port, 4356 bcm_gport_t *gport); 4357 4358 /* 4359 * Request if the given virtual port gport value is available on the 4360 * device. 4361 */ 4362 extern int bcm_port_gport_is_free( 4363 int unit, 4364 bcm_gport_t gport); 4365 4366 /* 4367 * Retrieve the minimum and maximum unallocated gport values for 4368 * a given gport type. 4369 */ 4370 extern int bcm_port_gport_free_range_get( 4371 int unit, 4372 uint32 gport_type, 4373 bcm_gport_t *gport_min, 4374 bcm_gport_t *gport_max); 4375 4376 /* Get local port number encoded within a GPORT ID. */ 4377 extern int bcm_port_local_get( 4378 int unit, 4379 bcm_gport_t gport, 4380 bcm_port_t *local_port); 4381 4382 #endif /* BCM_HIDE_DISPATCHABLE */ 4383 4384 /* flags for retreiving internal ports */ 4385 #define BCM_PORT_INTERNAL_EGRESS_REPLICATION 0x0001 4386 #define BCM_PORT_INTERNAL_OLP 0x0002 4387 #define BCM_PORT_INTERNAL_RECYCLE 0x0004 4388 #define BCM_PORT_INTERNAL_OAMP 0x0008 4389 #define BCM_PORT_INTERNAL_CONF_SCOPE_CORE0 0x0010 4390 #define BCM_PORT_INTERNAL_CONF_SCOPE_CORE1 0x0020 4391 4392 #ifndef BCM_HIDE_DISPATCHABLE 4393 4394 /* Get handles to internal ports. */ 4395 extern int bcm_port_internal_get( 4396 int unit, 4397 uint32 flags, 4398 int internal_ports_max, 4399 bcm_gport_t *internal_gport, 4400 int *internal_ports_count); 4401 4402 /* 4403 * Update the specified logical port (GPORT) with the given range(s) of 4404 * VIDs. 4405 */ 4406 extern int bcm_port_vlan_vector_set( 4407 int unit, 4408 bcm_gport_t port_id, 4409 bcm_vlan_vector_t vlan_vec); 4410 4411 /* Get the range(s) of VIDs for the specified logical port (GPORT). */ 4412 extern int bcm_port_vlan_vector_get( 4413 int unit, 4414 bcm_gport_t port_id, 4415 bcm_vlan_vector_t vlan_vec); 4416 4417 #endif /* BCM_HIDE_DISPATCHABLE */ 4418 4419 /* Backward compatibility. */ 4420 typedef _shr_port_stp_t bcm_port_stp_t; 4421 4422 /* Backward compatibility. */ 4423 #define BCM_PORT_STP_DISABLE _SHR_PORT_STP_DISABLE 4424 #define BCM_PORT_STP_BLOCK _SHR_PORT_STP_BLOCK 4425 #define BCM_PORT_STP_LISTEN _SHR_PORT_STP_LISTEN 4426 #define BCM_PORT_STP_LEARN _SHR_PORT_STP_LEARN 4427 #define BCM_PORT_STP_FORWARD _SHR_PORT_STP_FORWARD 4428 #define BCM_PORT_STP_COUNT _SHR_PORT_STP_COUNT 4429 4430 /* Backward compatibility. */ 4431 #define bcm_port_vlan_set(u, p, vid) \ 4432 bcm_port_untagged_vlan_set(u, p, vid) 4433 4434 /* Backward compatibility. */ 4435 #define bcm_port_vlan_get(u, p, vdata) \ 4436 bcm_port_untagged_vlan_get((u), (p), &((vdata)->vlan_tag)), \ 4437 bcm_vlan_port_get((u), (vdata)->vlan_tag, \ 4438 &((vdata)->port_bitmap), &((vdata)->ut_port_bitmap)) 4439 4440 #ifndef BCM_HIDE_DISPATCHABLE 4441 4442 /* Retrieve the Policer ID associated for the specified physical port. */ 4443 extern int bcm_port_policer_get( 4444 int unit, 4445 bcm_port_t port, 4446 bcm_policer_t *policer_id); 4447 4448 /* Set the Policer ID associated for the specified physical port. */ 4449 extern int bcm_port_policer_set( 4450 int unit, 4451 bcm_port_t port, 4452 bcm_policer_t policer_id); 4453 4454 #endif /* BCM_HIDE_DISPATCHABLE */ 4455 4456 /* Types of statistics that are maintained per gport. */ 4457 typedef enum bcm_port_stat_e { 4458 bcmPortStatIngressPackets = 0, /* Packets that ingress on the gport */ 4459 bcmPortStatIngressBytes = 1, /* Bytes that ingress on the gport */ 4460 bcmPortStatEgressPackets = 2, /* Packets that egress on the gport */ 4461 bcmPortStatEgressBytes = 3, /* Bytes that egress on the gport */ 4462 bcmPortStatIngressPreemptPackets = 4, /* Preemptable packets that ingress on 4463 the gport */ 4464 bcmPortStatIngressPreemptBytes = 5, /* Bytes of preemptable packets that 4465 ingress on the gport */ 4466 bcmPortStatEgressPreemptPackets = 6, /* Preemptable packets that egress on 4467 the gport */ 4468 bcmPortStatEgressPreemptBytes = 7 /* Bytes of preemptable packets that 4469 egress on the gport */ 4470 } bcm_port_stat_t; 4471 4472 #ifndef BCM_HIDE_DISPATCHABLE 4473 4474 /* Enable/disable packet and byte counters for the selected gport. */ 4475 extern int bcm_port_stat_enable_set( 4476 int unit, 4477 bcm_gport_t port, 4478 int enable); 4479 4480 /* Get port counter value for specified port statistic type. */ 4481 extern int bcm_port_stat_get( 4482 int unit, 4483 bcm_gport_t port, 4484 bcm_port_stat_t stat, 4485 uint64 *val); 4486 4487 /* 4488 * Force an immediate counter update and retrieve port counter value for 4489 * specified port statistic type. 4490 */ 4491 extern int bcm_port_stat_sync_get( 4492 int unit, 4493 bcm_gport_t port, 4494 bcm_port_stat_t stat, 4495 uint64 *val); 4496 4497 /* Get stat counter ID associated with given gport. */ 4498 extern int bcm_port_stat_id_get( 4499 int unit, 4500 bcm_gport_t port, 4501 bcm_port_stat_t stat, 4502 uint32 *stat_counter_id); 4503 4504 /* Get port counter value for specified port statistic type. */ 4505 extern int bcm_port_stat_get32( 4506 int unit, 4507 bcm_gport_t port, 4508 bcm_port_stat_t stat, 4509 uint32 *val); 4510 4511 /* 4512 * Force an immediate counter update and retrieve port counter value for 4513 * specified port statistic type. 4514 */ 4515 extern int bcm_port_stat_sync_get32( 4516 int unit, 4517 bcm_gport_t port, 4518 bcm_port_stat_t stat, 4519 uint32 *val); 4520 4521 /* Set port counter value for specified port statistic type. */ 4522 extern int bcm_port_stat_set( 4523 int unit, 4524 bcm_gport_t port, 4525 bcm_port_stat_t stat, 4526 uint64 val); 4527 4528 /* Set port counter value for specified port statistic type. */ 4529 extern int bcm_port_stat_set32( 4530 int unit, 4531 bcm_gport_t port, 4532 bcm_port_stat_t stat, 4533 uint32 val); 4534 4535 /* Get 64-bit/32-bit counter value for multiple port statistic types. */ 4536 extern int bcm_port_stat_multi_get( 4537 int unit, 4538 bcm_gport_t port, 4539 int nstat, 4540 bcm_port_stat_t *stat_arr, 4541 uint64 *value_arr); 4542 4543 /* Get 64-bit/32-bit counter value for multiple port statistic types. */ 4544 extern int bcm_port_stat_multi_get32( 4545 int unit, 4546 bcm_gport_t port, 4547 int nstat, 4548 bcm_port_stat_t *stat_arr, 4549 uint32 *value_arr); 4550 4551 /* Set 64-bit/32-bit counter value for multiple port statistic types. */ 4552 extern int bcm_port_stat_multi_set( 4553 int unit, 4554 bcm_gport_t port, 4555 int nstat, 4556 bcm_port_stat_t *stat_arr, 4557 uint64 *value_arr); 4558 4559 /* Set 64-bit/32-bit counter value for multiple port statistic types. */ 4560 extern int bcm_port_stat_multi_set32( 4561 int unit, 4562 bcm_gport_t port, 4563 int nstat, 4564 bcm_port_stat_t *stat_arr, 4565 uint32 *value_arr); 4566 4567 #endif /* BCM_HIDE_DISPATCHABLE */ 4568 4569 /* Generic port match criteria */ 4570 typedef enum bcm_port_match_e { 4571 BCM_PORT_MATCH_INVALID = 0, /* Illegal */ 4572 BCM_PORT_MATCH_NONE = 1, /* No matching criteria */ 4573 BCM_PORT_MATCH_PORT = 2, /* Match on module/port or trunk */ 4574 BCM_PORT_MATCH_PORT_VLAN = 3, /* Match on module/port or trunk + outer 4575 VLAN or SVLAN */ 4576 BCM_PORT_MATCH_PORT_VLAN_RANGE = 4, /* Match on module/port or trunk + VLAN 4577 range */ 4578 BCM_PORT_MATCH_PORT_VLAN_STACKED = 5, /* Match on module/port or trunk + 4579 inner/outer VLAN */ 4580 BCM_PORT_MATCH_TUNNEL_VLAN_SRCMAC = 6, /* Match on MiM B-VLAN and source MAC */ 4581 BCM_PORT_MATCH_LABEL = 7, /* Match on MPLS label */ 4582 BCM_PORT_MATCH_LABEL_PORT = 8, /* Match on MPLS label + module/port or 4583 trunk */ 4584 BCM_PORT_MATCH_LABEL_VLAN = 9, /* Match on MPLS label + VLAN */ 4585 BCM_PORT_MATCH_PORT_PCP_VLAN = 10, /* Mod/port/trunk + outer VLAN + outer 4586 PCP. */ 4587 BCM_PORT_MATCH_PORT_PCP_VLAN_STACKED = 11, /* Mod/port/trunk + outer/inner VLAN + 4588 outer/inner PCP. */ 4589 BCM_PORT_MATCH_PORT_INITIAL_VLAN = 12, /* Mod/port/trunk + Initial-VID */ 4590 BCM_PORT_MATCH_PORT_PON_TUNNEL = 13, /* Mod/port/trunk + PON Tunnel Value. */ 4591 BCM_PORT_MATCH_PORT_PON_TUNNEL_VLAN = 14, /* Mod/port/trunk + PON Tunnel Value + 4592 outer VLAN. */ 4593 BCM_PORT_MATCH_PORT_PON_TUNNEL_VLAN_STACKED = 15, /* Mod/port/trunk + PON Tunnel Value + 4594 outer VLAN + inner VLAN. */ 4595 BCM_PORT_MATCH_PORT_PON_TUNNEL_PCP_VLAN = 16, /* Mod/port/trunk + PON Tunnel Value + 4596 outer PCP + outer VLAN. */ 4597 BCM_PORT_MATCH_PORT_PON_TUNNEL_PCP_VLAN_STACKED = 17, /* Mod/port/trunk + PON Tunnel Value + 4598 outer PCP + outer VLAN + inner VLAN. */ 4599 BCM_PORT_MATCH_PORT_PON_TUNNEL_PCP_VLAN_ETHERTYPE = 18, /* Mod/port/trunk + PON Tunnel Value + 4600 Outer PCP + outer VLAN + EtherType. */ 4601 BCM_PORT_MATCH_PORT_PON_TUNNEL_PCP_VLAN_VLAN_ETHERTYPE = 19, /* Mod/port/trunk + PON Tunnel Value + 4602 Outer PCP + outer VLAN + Inner VLAN + 4603 EtherType. */ 4604 BCM_PORT_MATCH_PORT_PON_TUNNEL_ETHERTYPE = 20, /* Mod/port/trunk + PON Tunnel Value + 4605 EtherType. */ 4606 BCM_PORT_MATCH_PORT_PON_TUNNEL_VLAN_ETHERTYPE = 21, /* Mod/port/trunk + PON Tunnel Value + 4607 outer VLAN + EtherType. */ 4608 BCM_PORT_MATCH_PORT_PON_TUNNEL_VLAN_STACKED_ETHERTYPE = 22, /* Mod/port/trunk + PON Tunnel Value + 4609 outer VLAN + inner VLAN + EtherType. */ 4610 BCM_PORT_MATCH_PORT_VLAN16 = 23, /* Mod/port/trunk + 16-bit outer VLAN 4611 tag. */ 4612 BCM_PORT_MATCH_PORT_PON_TUNNEL_PCP = 24, /* Mod/port/trunk + PON Tunnel Value + 4613 outer PCP. */ 4614 BCM_PORT_MATCH_PORT_UNTAGGED = 25, /* Mod/port/trunk for untagged packets. */ 4615 BCM_PORT_MATCH_PORT_EXTENDED_PORT_VID = 26, /* Mod/port/trunk + Extender port VID */ 4616 BCM_PORT_MATCH_PORT_EXTENDED_PORT_VID_VLAN = 27, /* Mod/port/trunk + Extender port VID + 4617 VLAN */ 4618 BCM_PORT_MATCH_PORT_PON_TUNNEL_INNER_VLAN = 28, /* Mod/port/trunk + LLVID [11:0] of 4619 LLTAG + I-VID[11:0] */ 4620 BCM_PORT_MATCH_PORT_NIV_PORT_VIF = 29, /* Mod/port/trunk + NIV port VIF */ 4621 BCM_PORT_MATCH_PORT_NIV_PORT_VIF_VLAN = 30, /* Mod/port/trunk + NIV port VIF + VLAN */ 4622 BCM_PORT_MATCH_PORT_INNER_VLAN = 31, /* Mod/port/trunk + inner VLAN */ 4623 BCM_PORT_MATCH_PORT_VPN = 32, /* Logical Port + VPN */ 4624 BCM_PORT_MATCH_PORT_EXTENDED_PORT_VID_INITIAL_VLAN = 33, /* Mod/port/trunk + Extender port VID + 4625 initial VLAN */ 4626 BCM_PORT_MATCH_PORT_INNER_VLAN_RANGE = 34, /* Match on module/port or trunk + inner 4627 VLAN range */ 4628 BCM_PORT_MATCH_PORT_VLAN_STACKED_RANGE = 35, /* Match on module/port or trunk + inner 4629 VLAN range + outer VLAN range */ 4630 BCM_PORT_MATCH_PORT_INNER_VLAN16 = 36, /* Mod/port/trunk + 16-bit Inner VLAN 4631 tag */ 4632 BCM_PORT_MATCH_PORT_I2E_CLASS = 37, /* port + Ingress to Egress(I2E) class 4633 id vlan type */ 4634 BCM_PORT_MATCH_PORT_CVLAN = 38, /* Mod/port/trunk + CVLAN */ 4635 BCM_PORT_MATCH_MAC_PORT = 39, /* Match on mac address + Mod/port/trunk 4636 or virtual port */ 4637 BCM_PORT_MATCH_MAC_PORT_CLASS = 40, /* Match on mac address + port class id */ 4638 BCM_PORT_MATCH_PORT_SVLAN_STACKED = 41, /* Match on module/port or trunk + 4639 inner/outer both SVLAN */ 4640 BCM_PORT_MATCH_PORT_CVLAN_STACKED = 42, /* Match on module/port or trunk + 4641 inner/outer both CVLAN */ 4642 BCM_PORT_MATCH_PORT_I2E_CLASS_IFP_TYPE = 43, /* port + Ingress to Egress(I2E) class 4643 id IFP type */ 4644 BCM_PORT_MATCH_PORT_PON_TUNNEL_CVLAN = 44, /* Mod/port/trunk + PON Tunnel Value + 4645 outer CVLAN. */ 4646 BCM_PORT_MATCH_PORT_PON_TUNNEL_CVLAN_STACKED = 45, /* Mod/port/trunk + PON Tunnel Value + 4647 inner/outer both CVLAN. */ 4648 BCM_PORT_MATCH_PORT_PON_TUNNEL_SVLAN_STACKED = 46, /* Mod/port/trunk + PON Tunnel Value + 4649 inner/outer both SVLAN. */ 4650 BCM_PORT_MATCH_PORT_PON_TUNNEL_UNTAGGED = 47, /* Mod/port/trunk + PON Tunnel Value + 4651 untagged packets. */ 4652 BCM_PORT_MATCH_PORT_GROUP_VLAN = 48, /* Match on port group + outer VLAN. */ 4653 BCM_PORT_MATCH_PORT_GROUP_INNER_VLAN = 49, /* Match on port group + inner VLAN. */ 4654 BCM_PORT_MATCH_PORT_GROUP_VLAN_STACKED = 50, /* Match on port group + inner and 4655 outer VLAN. */ 4656 BCM_PORT_MATCH_COUNT = 51 /* Must be last */ 4657 } bcm_port_match_t; 4658 4659 /* Flags for bcm_port_match_info_t */ 4660 #define BCM_PORT_MATCH_INGRESS_ONLY 0x00000001 /* Indicates Ingress settings */ 4661 #define BCM_PORT_MATCH_EGRESS_ONLY 0x00000002 /* Indicates Egress settings */ 4662 #define BCM_PORT_MATCH_NATIVE 0x00000004 /* Indicates Native Ethernet 4663 settings */ 4664 #define BCM_PORT_MATCH_MIM 0x00000008 /* ISEM entry added contains 4665 an ISID that points to a 4666 MiM LIF. */ 4667 #define BCM_PORT_MATCH_MIM_SERVICE_SMAC 0x00000010 /* Match contains a BSA 4668 nickname (in addition to 4669 ISID). */ 4670 4671 /* Generic port match attribute structure */ 4672 typedef struct bcm_port_match_info_s { 4673 bcm_port_match_t match; /* Match criteria */ 4674 bcm_gport_t port; /* Match port */ 4675 bcm_vlan_t match_vlan; /* Outer VLAN ID to match */ 4676 bcm_vlan_t match_vlan_max; /* Maximum VLAN ID in range to match */ 4677 bcm_vlan_t match_inner_vlan; /* Inner VLAN ID to match */ 4678 bcm_vlan_t match_inner_vlan_max; /* Maximum Inner VLAN ID in range to 4679 match */ 4680 bcm_vlan_t match_tunnel_vlan; /* B-domain VID */ 4681 bcm_mac_t match_tunnel_srcmac; /* B-domain source MAC address */ 4682 bcm_mpls_label_t match_label; /* MPLS label */ 4683 uint32 flags; /* BCM_PORT_MATCH_XXX flags */ 4684 bcm_tunnel_id_t match_pon_tunnel; /* PON Tunnel value to match. */ 4685 bcm_port_ethertype_t match_ethertype; /* Ethernet type value to match */ 4686 int match_pcp; /* Outer PCP ID to match */ 4687 bcm_vlan_action_set_t *action; /* Match action */ 4688 uint16 extended_port_vid; /* Extender port VID */ 4689 bcm_vpn_t vpn; /* VPN ID */ 4690 uint16 niv_port_vif; /* NIV port VIF */ 4691 uint32 isid; 4692 bcm_mac_t src_mac; /* Source Mac Address */ 4693 uint32 port_class; /* Port Class Id */ 4694 } bcm_port_match_info_t; 4695 4696 /* Initialize a Port Match Information structure. */ 4697 extern void bcm_port_match_info_t_init( 4698 bcm_port_match_info_t *port_match_info); 4699 4700 #ifndef BCM_HIDE_DISPATCHABLE 4701 4702 /* 4703 * Add a match to an existing virtual port, or add multiple matches to a 4704 * shared virtual port and also gports such as Mirror destination ID. 4705 */ 4706 extern int bcm_port_match_add( 4707 int unit, 4708 bcm_gport_t port, 4709 bcm_port_match_info_t *match); 4710 4711 /* Remove a match from an existing port. */ 4712 extern int bcm_port_match_delete( 4713 int unit, 4714 bcm_gport_t port, 4715 bcm_port_match_info_t *match); 4716 4717 /* Replace an old match with a new one for an existing port. */ 4718 extern int bcm_port_match_replace( 4719 int unit, 4720 bcm_gport_t port, 4721 bcm_port_match_info_t *old_match, 4722 bcm_port_match_info_t *new_match); 4723 4724 /* Get all the matches for an existing port. */ 4725 extern int bcm_port_match_multi_get( 4726 int unit, 4727 bcm_gport_t port, 4728 int size, 4729 bcm_port_match_info_t *match_array, 4730 int *count); 4731 4732 /* Assign a set of matches to an existing port. */ 4733 extern int bcm_port_match_set( 4734 int unit, 4735 bcm_gport_t port, 4736 int size, 4737 bcm_port_match_info_t *match_array); 4738 4739 /* Delete all matches for an existing port. */ 4740 extern int bcm_port_match_delete_all( 4741 int unit, 4742 bcm_gport_t port); 4743 4744 #endif /* BCM_HIDE_DISPATCHABLE */ 4745 4746 /* Timesync Configuration flags. */ 4747 #define BCM_PORT_TIMESYNC_DEFAULT 0x00000001 /* Port Timesync 4748 configuration */ 4749 #define BCM_PORT_TIMESYNC_MPLS 0x00000002 /* Port Timesync MPLS 4750 configuration */ 4751 #define BCM_PORT_TIMESYNC_ONE_STEP_TIMESTAMP 0x00000004 /* Port one step 4752 timestamp 4753 configuration */ 4754 #define BCM_PORT_TIMESYNC_TWO_STEP_TIMESTAMP 0x00000008 /* Port two step 4755 timestamp 4756 configuration */ 4757 #define BCM_PORT_TIMESYNC_TIMESTAMP_CFUPDATE_ALL 0x00000010 /* All 1588 packets will 4758 be egress timestamped. 4759 By default, only 4760 ingress timestamped 4761 packets are egress 4762 timestamped */ 4763 #define BCM_PORT_TIMESYNC_EXTERNAL_MAC_ENABLE 0x00000020 /* enable external mac 4764 for the port */ 4765 #define BCM_PORT_PHY_CONTROL_FAIL_OVER_MODE _SHR_PORT_PHY_CONTROL_FAIL_OVER_MODE 4766 #define BCM_PORT_PHY_CONTROL_SHORT_CHANNEL_MODE _SHR_PORT_PHY_SHORT_CHANNEL_MODE 4767 #define BCM_PORT_PHY_CONTROL_SHORT_CHANNEL_MODE_STATUS _SHR_PORT_PHY_CONTROL_SHORT_CHANNEL_MODE_STATUS 4768 #define BCM_PORT_PHY_CONTROL_EYE_VAL_HZ_L _SHR_PORT_PHY_CONTROL_EYE_VAL_HZ_L /* Eye scan value, 4769 Horizantal left */ 4770 #define BCM_PORT_PHY_CONTROL_EYE_VAL_HZ_R _SHR_PORT_PHY_CONTROL_EYE_VAL_HZ_R /* Eye scan value, 4771 Horizantal right */ 4772 #define BCM_PORT_PHY_CONTROL_EYE_VAL_VT_U _SHR_PORT_PHY_CONTROL_EYE_VAL_VT_U /* Eye scan value, 4773 vertical up */ 4774 #define BCM_PORT_PHY_CONTROL_EYE_VAL_VT_D _SHR_PORT_PHY_CONTROL_EYE_VAL_VT_D /* Eye scan value, 4775 vertical down */ 4776 4777 /* Timesync Packet type bitmaps. */ 4778 #define BCM_PORT_TIMESYNC_PKT_SYNC 0x00000001 /* Sync Event Packet type */ 4779 #define BCM_PORT_TIMESYNC_PKT_DELAY_REQ 0x00000002 /* Delay Request Event 4780 Packet type */ 4781 #define BCM_PORT_TIMESYNC_PKT_PDELAY_REQ 0x00000004 /* Pdelay Request Event 4782 Packet type */ 4783 #define BCM_PORT_TIMESYNC_PKT_PDELAY_RESP 0x00000008 /* Pdelay Response Event 4784 Packet type */ 4785 #define BCM_PORT_TIMESYNC_PKT_FOLLOWUP 0x00000100 /* Followup General 4786 Packet type */ 4787 #define BCM_PORT_TIMESYNC_PKT_DELAY_RESP 0x00000200 /* Delay_resp General 4788 Packet type */ 4789 #define BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP 0x00000400 /* Pdelay_resp_followup 4790 General Packet type */ 4791 #define BCM_PORT_TIMESYNC_PKT_ANNOUNCE 0x00000800 /* Announce General 4792 Packet type */ 4793 #define BCM_PORT_TIMESYNC_PKT_SIGNALLING 0x00001000 /* Signalling General 4794 Packet type */ 4795 #define BCM_PORT_TIMESYNC_PKT_MANAGMENT 0x00002000 /* Management General 4796 Packet type */ 4797 #define BCM_PORT_TIMESYNC_PKT_INVALID 0x00004000 /* Invalid Packet type */ 4798 4799 /* Timesync configuration. */ 4800 typedef struct bcm_port_timesync_config_s { 4801 uint32 flags; /* Timesync Configuration flags */ 4802 uint32 pkt_drop; /* Pakcet Drop bitmap of event and general packet 4803 types */ 4804 uint32 pkt_tocpu; /* CPU forward bitmap of event and general packet 4805 types */ 4806 int mpls_min_label; /* Timesync over MPLS min label */ 4807 int mpls_max_label; /* Timesync over MPLS max label */ 4808 bcm_mac_t src_mac_addr; /* Source mac address for one-step timestamp update */ 4809 int user_trap_id; /* 1588 user trap id */ 4810 } bcm_port_timesync_config_t; 4811 4812 #ifndef BCM_HIDE_DISPATCHABLE 4813 4814 /* Set timesync configurations for the port. */ 4815 extern int bcm_port_timesync_config_set( 4816 int unit, 4817 bcm_port_t port, 4818 int config_count, 4819 bcm_port_timesync_config_t *config_array); 4820 4821 /* Get timesync configurations for the port. */ 4822 extern int bcm_port_timesync_config_get( 4823 int unit, 4824 bcm_port_t port, 4825 int array_size, 4826 bcm_port_timesync_config_t *config_array, 4827 int *array_count); 4828 4829 #endif /* BCM_HIDE_DISPATCHABLE */ 4830 4831 #define BCM_PORT_PHY_TIMESYNC_CAP_MPLS _SHR_PORT_PHY_TIMESYNC_CAP_MPLS /* PHY is 1588 over MPLS 4832 capable */ 4833 #define BCM_PORT_PHY_TIMESYNC_CAP_ENHANCED_TSFIFO _SHR_PORT_PHY_TIMESYNC_CAP_ENHANCED_TSFIFO /* PHY has enhanced 4834 TSFIFO */ 4835 #define BCM_PORT_PHY_TIMESYNC_CAP_INBAND_TS _SHR_PORT_PHY_TIMESYNC_CAP_INBAND_TS /* PHY supports inband 4836 timestamping */ 4837 #define BCM_PORT_PHY_TIMESYNC_CAP_FOLLOW_UP_ASSIST _SHR_PORT_PHY_TIMESYNC_CAP_FOLLOW_UP_ASSIST /* PHY supports follow up 4838 assist */ 4839 #define BCM_PORT_PHY_TIMESYNC_CAP_DELAY_RESP_ASSIST _SHR_PORT_PHY_TIMESYNC_CAP_DELAY_RESP_ASSIST /* PHY supports delay 4840 response assist */ 4841 #define BCM_PORT_PHY_TIMESYNC_CAP_CAPTURE_TIMESTAMP_MSG _SHR_PORT_PHY_TIMESYNC_CAP_CAPTURE_TIMESTAMP_MSG /* PHY supports selective 4842 timestamp capture of 4843 1588 messages */ 4844 #define BCM_PORT_PHY_TIMESYNC_VALID_FLAGS _SHR_PORT_PHY_TIMESYNC_VALID_FLAGS /* Flags field is valid */ 4845 #define BCM_PORT_PHY_TIMESYNC_VALID_ITPID _SHR_PORT_PHY_TIMESYNC_VALID_ITPID /* itpid is valid */ 4846 #define BCM_PORT_PHY_TIMESYNC_VALID_OTPID _SHR_PORT_PHY_TIMESYNC_VALID_OTPID /* otpid is valid */ 4847 #define BCM_PORT_PHY_TIMESYNC_VALID_OTPID2 _SHR_PORT_PHY_TIMESYNC_VALID_OTPID2 /* otpid2 is valid */ 4848 #define BCM_PORT_PHY_TIMESYNC_VALID_GMODE _SHR_PORT_PHY_TIMESYNC_VALID_GMODE /* gmode is valid */ 4849 #define BCM_PORT_PHY_TIMESYNC_VALID_FRAMESYNC_MODE _SHR_PORT_PHY_TIMESYNC_VALID_FRAMESYNC_MODE /* framesync mode is 4850 valid */ 4851 #define BCM_PORT_PHY_TIMESYNC_VALID_SYNCOUT_MODE _SHR_PORT_PHY_TIMESYNC_VALID_SYNCOUT_MODE /* syncout mode is valid */ 4852 #define BCM_PORT_PHY_TIMESYNC_VALID_TS_DIVIDER _SHR_PORT_PHY_TIMESYNC_VALID_TS_DIVIDER /* ts divider mode is 4853 valid */ 4854 #define BCM_PORT_PHY_TIMESYNC_VALID_ORIGINAL_TIMECODE _SHR_PORT_PHY_TIMESYNC_VALID_ORIGINAL_TIMECODE /* original timecode is 4855 valid */ 4856 #define BCM_PORT_PHY_TIMESYNC_VALID_TX_TIMESTAMP_OFFSET _SHR_PORT_PHY_TIMESYNC_VALID_TX_TIMESTAMP_OFFSET /* tx timestamp offset is 4857 valid */ 4858 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_TIMESTAMP_OFFSET _SHR_PORT_PHY_TIMESYNC_VALID_RX_TIMESTAMP_OFFSET /* rx timestamp offset is 4859 valid */ 4860 #define BCM_PORT_PHY_TIMESYNC_VALID_TX_SYNC_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_SYNC_MODE /* tx sync mode is valid */ 4861 #define BCM_PORT_PHY_TIMESYNC_VALID_TX_DELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_DELAY_REQUEST_MODE /* tx delay request mode 4862 is valid */ 4863 #define BCM_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_REQUEST_MODE /* tx pdelay request mode 4864 is valid */ 4865 #define BCM_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_RESPONSE_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_RESPONSE_MODE /* tx pdelay response 4866 mode is valid */ 4867 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_SYNC_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_SYNC_MODE /* rx sync mode is valid */ 4868 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_DELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_DELAY_REQUEST_MODE /* rx delay request mode 4869 is valid */ 4870 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_REQUEST_MODE /* rx pdelay request mode 4871 is valid */ 4872 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_RESPONSE_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_RESPONSE_MODE /* rx pdelay response 4873 mode is valid */ 4874 #define BCM_PORT_PHY_TIMESYNC_VALID_MPLS_CONTROL _SHR_PORT_PHY_TIMESYNC_VALID_MPLS_CONTROL /* mpls control is valid */ 4875 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_LINK_DELAY _SHR_PORT_PHY_TIMESYNC_VALID_RX_LINK_DELAY /* rx link delay is valid */ 4876 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_SYNC_FREQ _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_SYNC_FREQ /* sync freq. is valid */ 4877 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K1 _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K1 /* phy 1588 dpll k1 is 4878 valid */ 4879 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K2 _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K2 /* phy 1588 dpll k2 is 4880 valid */ 4881 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K3 _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K3 /* phy 1588 dpll k3 is 4882 valid */ 4883 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_LOOP_FILTER _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_LOOP_FILTER /* phy 1588 dpll loop 4884 filter is valid */ 4885 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE /* phy 1588 dpll ref 4886 phase is valid */ 4887 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE_DELTA _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE_DELTA /* phy 1588 dpll ref 4888 phase delta is valid */ 4889 #define BCM_PORT_PHY_TIMESYNC_VALID_TIMER_ADJUSTMENT _SHR_PORT_PHY_TIMESYNC_VALID_TIMER_ADJUSTMENT /* phy 1588 direct timer 4890 adjustment is valid */ 4891 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_INBAND_CONTROL _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_INBAND_CONTROL /* phy 1588 inband ts 4892 control is valid */ 4893 #define BCM_PORT_PHY_TIMESYNC_ENABLE _SHR_PORT_PHY_TIMESYNC_ENABLE /* Enable Time 4894 Synchronization 4895 Interface */ 4896 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TS_ENABLE _SHR_PORT_PHY_TIMESYNC_CAPTURE_TS_ENABLE /* Enable Packet 4897 Timestamping */ 4898 #define BCM_PORT_PHY_TIMESYNC_HEARTBEAT_TS_ENABLE _SHR_PORT_PHY_TIMESYNC_HEARTBEAT_TS_ENABLE /* Enable Heartbeat 4899 Timestamping */ 4900 #define BCM_PORT_PHY_TIMESYNC_RX_CRC_ENABLE _SHR_PORT_PHY_TIMESYNC_RX_CRC_ENABLE /* Enable CRC checking */ 4901 #define BCM_PORT_PHY_TIMESYNC_8021AS_ENABLE _SHR_PORT_PHY_TIMESYNC_8021AS_ENABLE /* Enable IEEE802.1AS 4902 mode */ 4903 #define BCM_PORT_PHY_TIMESYNC_L2_ENABLE _SHR_PORT_PHY_TIMESYNC_L2_ENABLE /* IEEE1588 over Layer 2 */ 4904 #define BCM_PORT_PHY_TIMESYNC_IP4_ENABLE _SHR_PORT_PHY_TIMESYNC_IP4_ENABLE /* IEEE1588 over IPV4 UDP */ 4905 #define BCM_PORT_PHY_TIMESYNC_IP6_ENABLE _SHR_PORT_PHY_TIMESYNC_IP6_ENABLE /* IEEE1588 over IPV6 UDP */ 4906 #define BCM_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT _SHR_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT /* Use external clock 4907 source (DPLL) */ 4908 #define BCM_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT_MODE _SHR_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT_MODE /* DPLL mode, 0 - phase 4909 lock, 1 - frequency 4910 lock */ 4911 #define BCM_PORT_PHY_TIMESYNC_1588_ENCRYPTED_MODE _SHR_PORT_PHY_TIMESYNC_1588_ENCRYPTED_MODE /* Encrypted mode, 0 - 4912 disable, 1 - enable */ 4913 #define BCM_PORT_PHY_TIMESYNC_FOLLOW_UP_ASSIST_ENABLE _SHR_PORT_PHY_TIMESYNC_FOLLOW_UP_ASSIST_ENABLE /* Enable follow up 4914 assistant */ 4915 #define BCM_PORT_PHY_TIMESYNC_DELAY_RESP_ASSIST_ENABLE _SHR_PORT_PHY_TIMESYNC_DELAY_RESP_ASSIST_ENABLE /* Enable delay response 4916 assistant */ 4917 #define BCM_PORT_PHY_TIMESYNC_64BIT_TIMESTAMP_ENABLE _SHR_PORT_PHY_TIMESYNC_64BIT_TIMESTAMP_ENABLE /* Enable 64bit 4918 timestamping */ 4919 #define BCM_PORT_PHY_TIMESYNC_1588_OVER_HSR_ENABLE _SHR_PORT_PHY_TIMESYNC_1588_OVER_HSR_ENABLE /* Enable 1588 over HSR */ 4920 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_SYNC _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_SYNC /* Capture timestamp of 4921 Tx Sync packets */ 4922 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_DELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_DELAY_REQ /* Capture timestamp of 4923 Tx Delay Request 4924 packets */ 4925 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_REQ /* Capture timestamp of 4926 Tx PDelay Request 4927 packets */ 4928 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_RESP _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_RESP /* Capture timestamp of 4929 Tx PDelay Response 4930 packets */ 4931 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_SYNC _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_SYNC /* Capture timestamp of 4932 Rx Sync packets */ 4933 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_DELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_DELAY_REQ /* Capture timestamp of 4934 Rx Delay Request 4935 packets */ 4936 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_REQ /* Capture timestamp of 4937 Rx PDelay Request 4938 packets */ 4939 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_RESP _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_RESP /* Capture timestamp of 4940 Rx PDelay Response 4941 packets */ 4942 #define BCM_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_CHECK _SHR_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_CHECK /* Enable inband resv0 id 4943 check */ 4944 #define BCM_PORT_PHY_TIMESYNC_INBAND_SYNC_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_SYNC_ENABLE /* Enable inband 4945 timestamping for Sync */ 4946 #define BCM_PORT_PHY_TIMESYNC_INBAND_DELAY_RQ_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_DELAY_RQ_ENABLE /* Enable inband 4947 timestamping for Delay 4948 Request */ 4949 #define BCM_PORT_PHY_TIMESYNC_INBAND_PDELAY_RQ_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_PDELAY_RQ_ENABLE /* Enable inband 4950 timestamping for 4951 PDelay Request */ 4952 #define BCM_PORT_PHY_TIMESYNC_INBAND_PDELAY_RESP_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_PDELAY_RESP_ENABLE /* Enable inband 4953 timestamping for 4954 PDelay Response */ 4955 #define BCM_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_UPDATE _SHR_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_UPDATE /* Enables update of 4956 resv0 field in the 4957 ingress packet with 4958 the resv0_id */ 4959 #define BCM_PORT_PHY_TIMESYNC_INBAND_FOLLOW_UP_ASSIST _SHR_PORT_PHY_TIMESYNC_INBAND_FOLLOW_UP_ASSIST /* Enable inband 4960 Follow_Up (T1) assist */ 4961 #define BCM_PORT_PHY_TIMESYNC_INBAND_DELAY_RESP_ASSIST _SHR_PORT_PHY_TIMESYNC_INBAND_DELAY_RESP_ASSIST /* Enable inband 4962 Delay_Response (T3) 4963 assist */ 4964 #define BCM_PORT_PHY_TIMESYNC_INBAND_TIMER_MODE_SELECT _SHR_PORT_PHY_TIMESYNC_INBAND_TIMER_MODE_SELECT /* Select 80- or 48-bit 4965 counter for inband PTP 4966 messages */ 4967 #define BCM_PORT_PHY_TIMESYNC_INBAND_CAP_SRC_PORT_CLK_ID _SHR_PORT_PHY_TIMESYNC_INBAND_CAP_SRC_PORT_CLK_ID /* By default, MAC DA is 4968 captured and saved in 4969 the memory/FIFO. To 4970 capture source port 4971 clock ID instead, this 4972 flag can be used. Only 4973 one of them can be 4974 selected at a time. */ 4975 #define BCM_PORT_PHY_TIMESYNC_INBAND_MATCH_VLAN_ID _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_VLAN_ID /* Enable the comparison 4976 of the VLAN ID field 4977 during delay 4978 response(T3) and 4979 follow up packet. */ 4980 #define BCM_PORT_PHY_TIMESYNC_INBAND_MATCH_SRC_PORT_NUM _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_SRC_PORT_NUM /* Enable the comparison 4981 of the source port 4982 number during delay 4983 response(T3) and 4984 follow up packet. */ 4985 #define BCM_PORT_PHY_TIMESYNC_INBAND_MATCH_MAC_ADDR _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_MAC_ADDR /* Enable the comparison 4986 of the MAC address 4987 during delay 4988 response(T3) and 4989 follow up packet. */ 4990 #define BCM_PORT_PHY_TIMESYNC_INBAND_MATCH_IP_ADDR _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_IP_ADDR /* Enable the comparison 4991 of the IP address 4992 during delay 4993 response(T3) and 4994 follow up packet. */ 4995 #define BCM_PORT_PHY_TIMESYNC_MPLS_LABEL_IN _SHR_PORT_PHY_TIMESYNC_MPLS_LABEL_IN /* MPLS label applies to 4996 ingress packets */ 4997 #define BCM_PORT_PHY_TIMESYNC_MPLS_LABEL_OUT _SHR_PORT_PHY_TIMESYNC_MPLS_LABEL_OUT /* MPLS label applies to 4998 egress packets */ 4999 #define BCM_PORT_PHY_TIMESYNC_MPLS_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_ENABLE /* Enable processing of 5000 MPLS 1588 packets */ 5001 #define BCM_PORT_PHY_TIMESYNC_MPLS_ENTROPY_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_ENTROPY_ENABLE /* Enable MPLS entropy on 5002 1588 packets */ 5003 #define BCM_PORT_PHY_TIMESYNC_MPLS_SPECIAL_LABEL_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_SPECIAL_LABEL_ENABLE /* Enable MPLS special 5004 label on 1588 packets */ 5005 #define BCM_PORT_PHY_TIMESYNC_MPLS_CONTROL_WORD_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_CONTROL_WORD_ENABLE /* Enable MPLS control 5006 word on 1588 packets */ 5007 #define BCM_PORT_PHY_TIMESYNC_TN_LOAD _SHR_PORT_PHY_TIMESYNC_TN_LOAD /* Load Tn upon framesync */ 5008 #define BCM_PORT_PHY_TIMESYNC_TN_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_TN_ALWAYS_LOAD /* Always load Tn upon 5009 framesync */ 5010 #define BCM_PORT_PHY_TIMESYNC_TIMECODE_LOAD _SHR_PORT_PHY_TIMESYNC_TIMECODE_LOAD /* Load timecode upon 5011 framesync */ 5012 #define BCM_PORT_PHY_TIMESYNC_TIMECODE_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_TIMECODE_ALWAYS_LOAD /* Always load timecode 5013 upon framesync */ 5014 #define BCM_PORT_PHY_TIMESYNC_SYNCOUT_LOAD _SHR_PORT_PHY_TIMESYNC_SYNCOUT_LOAD /* Load syncout upon 5015 framesync */ 5016 #define BCM_PORT_PHY_TIMESYNC_SYNCOUT_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_SYNCOUT_ALWAYS_LOAD /* Always load syncout 5017 upon framesync */ 5018 #define BCM_PORT_PHY_TIMESYNC_NCO_DIVIDER_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_DIVIDER_LOAD /* Load NCO divider upon 5019 framesync */ 5020 #define BCM_PORT_PHY_TIMESYNC_NCO_DIVIDER_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_DIVIDER_ALWAYS_LOAD /* Always load NCO 5021 divider upon framesync */ 5022 #define BCM_PORT_PHY_TIMESYNC_LOCAL_TIME_LOAD _SHR_PORT_PHY_TIMESYNC_LOCAL_TIME_LOAD /* Load local time upon 5023 framesync */ 5024 #define BCM_PORT_PHY_TIMESYNC_LOCAL_TIME_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_LOCAL_TIME_ALWAYS_LOAD /* Always load local time 5025 upon framesync */ 5026 #define BCM_PORT_PHY_TIMESYNC_NCO_ADDEND_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_ADDEND_LOAD /* Load NCO addend upon 5027 framesync */ 5028 #define BCM_PORT_PHY_TIMESYNC_NCO_ADDEND_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_ADDEND_ALWAYS_LOAD /* Always load NCO addend 5029 upon framesync */ 5030 #define BCM_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_LOAD /* Load DPLL loop filter 5031 upon framesync */ 5032 #define BCM_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_ALWAYS_LOAD /* Always load DPLL loop 5033 filter upon framesync */ 5034 #define BCM_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_LOAD /* Load DPLL ref phase 5035 upon framesync */ 5036 #define BCM_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_ALWAYS_LOAD /* Always load DPLL ref 5037 phase upon framesync */ 5038 #define BCM_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_LOAD /* Load DPLL ref phase 5039 delta upon framesync */ 5040 #define BCM_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_ALWAYS_LOAD /* Always load DPLL ref 5041 phase delta upon 5042 framesync */ 5043 #define BCM_PORT_PHY_TIMESYNC_DPLL_K3_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K3_LOAD /* Load DPLL coefficient 5044 K3 upon framesync */ 5045 #define BCM_PORT_PHY_TIMESYNC_DPLL_K3_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K3_ALWAYS_LOAD /* Always load DPLL 5046 coefficient K3 upon 5047 framesync */ 5048 #define BCM_PORT_PHY_TIMESYNC_DPLL_K2_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K2_LOAD /* Load DPLL coefficient 5049 K2 upon framesync */ 5050 #define BCM_PORT_PHY_TIMESYNC_DPLL_K2_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K2_ALWAYS_LOAD /* Always load DPLL 5051 coefficient K2 upon 5052 framesync */ 5053 #define BCM_PORT_PHY_TIMESYNC_DPLL_K1_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K1_LOAD /* Load DPLL coefficient 5054 K1 upon framesync */ 5055 #define BCM_PORT_PHY_TIMESYNC_DPLL_K1_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K1_ALWAYS_LOAD /* Always load DPLL 5056 coefficient K1 upon 5057 framesync */ 5058 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT /* Packet timestamp 5059 interrupt */ 5060 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_0 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_0 /* Packet timestamp 5061 interrupt from port 0 */ 5062 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_1 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_1 /* Packet timestamp 5063 interrupt from port 1 */ 5064 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_2 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_2 /* Packet timestamp 5065 interrupt from port 2 */ 5066 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_3 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_3 /* Packet timestamp 5067 interrupt from port 3 */ 5068 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_4 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_4 /* Packet timestamp 5069 interrupt from port 4 */ 5070 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_5 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_5 /* Packet timestamp 5071 interrupt from port 5 */ 5072 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_6 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_6 /* Packet timestamp 5073 interrupt from port 6 */ 5074 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_7 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_7 /* Packet timestamp 5075 interrupt from port 7 */ 5076 #define BCM_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT /* Framesync interrupt */ 5077 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_MASK _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_MASK /* Packet timestamp 5078 interrupt mask */ 5079 #define BCM_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT_MASK _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT_MASK /* Framesync interrupt 5080 mask */ 5081 #define BCM_PORT_PHY_TIMESYNC_ONE_STEP_ENABLE _SHR_PORT_PHY_TIMESYNC_ONE_STEP_ENABLE /* Enable One-Step 5082 timestamping */ 5083 5084 /* Actions on Egress event messages */ 5085 typedef enum bcm_port_phy_timesync_event_message_egress_mode_e { 5086 bcmPortPhyTimesyncEventMessageEgressModeNone = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_NONE, /* Do nothing */ 5087 bcmPortPhyTimesyncEventMessageEgressModeUpdateCorrectionField = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_UPDATE_CORRECTIONFIELD, /* Update correction field */ 5088 bcmPortPhyTimesyncEventMessageEgressModeReplaceCorrectionFieldOrigin = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_REPLACE_CORRECTIONFIELD_ORIGIN, /* Replace correction field + original 5089 timecode */ 5090 bcmPortPhyTimesyncEventMessageEgressModeCaptureTimestamp = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_CAPTURE_TIMESTAMP /* Capture TX timestamp */ 5091 } bcm_port_phy_timesync_event_message_egress_mode_t; 5092 5093 /* Actions on ingress event messages */ 5094 typedef enum bcm_port_phy_timesync_event_message_ingress_mode_e { 5095 bcmPortPhyTimesyncEventMessageIngressModeNone = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_NONE, /* Do nothing */ 5096 bcmPortPhyTimesyncEventMessageIngressModeUpdateCorrectionField = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_UPDATE_CORRECTIONFIELD, /* Update correction field */ 5097 bcmPortPhyTimesyncEventMessageIngressModeInsertTimestamp = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_TIMESTAMP, /* Insert timestamp */ 5098 bcmPortPhyTimesyncEventMessageIngressModeInsertDelaytime = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_DELAYTIME /* Insert delay */ 5099 } bcm_port_phy_timesync_event_message_ingress_mode_t; 5100 5101 /* Global mode actions */ 5102 typedef enum bcm_port_phy_timesync_global_mode_e { 5103 bcmPortPhyTimesyncModeFree = _SHR_PORT_PHY_TIMESYNC_MODE_FREE, /* Do nothing */ 5104 bcmPortPhyTimesyncModeSyncin = _SHR_PORT_PHY_TIMESYNC_MODE_SYNCIN, /* Use syncin as the source */ 5105 bcmPortPhyTimesyncModeCpu = _SHR_PORT_PHY_TIMESYNC_MODE_CPU /* CPU based framesync */ 5106 } bcm_port_phy_timesync_global_mode_t; 5107 5108 /* Fast call actions */ 5109 typedef enum bcm_port_control_phy_timesync_e { 5110 bcmPortControlPhyTimesyncCaptureTimestamp = _SHR_PORT_CONTROL_PHY_TIMESYNC_CAPTURE_TIMESTAMP, /* Captured TS from packets */ 5111 bcmPortControlPhyTimesyncHeartbeatTimestamp = _SHR_PORT_CONTROL_PHY_TIMESYNC_HEARTBEAT_TIMESTAMP, /* Heartbeat TS at framesync */ 5112 bcmPortControlPhyTimesyncNCOAddend = _SHR_PORT_CONTROL_PHY_TIMESYNC_NCOADDEND, /* NCO addend (for non DPLL mode) */ 5113 bcmPortControlPhyTimesyncFrameSync = _SHR_PORT_CONTROL_PHY_TIMESYNC_FRAMESYNC, /* Cause immediate framesync */ 5114 bcmPortControlPhyTimesyncLocalTime = _SHR_PORT_CONTROL_PHY_TIMESYNC_LOCAL_TIME, /* Set local time (44 bits) */ 5115 bcmPortControlPhyTimesyncLoadControl = _SHR_PORT_CONTROL_PHY_TIMESYNC_LOAD_CONTROL, /* Load control and sticky bits */ 5116 bcmPortControlPhyTimesyncInterrupt = _SHR_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT, /* 1588 PHY interrupt status */ 5117 bcmPortControlPhyTimesyncInterruptMask = _SHR_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT_MASK, /* 1588 PHY interrupt mask */ 5118 bcmPortControlPhyTimesyncTxTimestampOffset = _SHR_PORT_CONTROL_PHY_TIMESYNC_TX_TIMESTAMP_OFFSET, /* TX AFE delay */ 5119 bcmPortControlPhyTimesyncRxTimestampOffset = _SHR_PORT_CONTROL_PHY_TIMESYNC_RX_TIMESTAMP_OFFSET, /* RX AFE delay */ 5120 bcmPortControlPhyTimesyncNSETimeOffset = _SHR_PORT_CONTROL_PHY_TIMESYNC_NSE_TIME_OFFSET, /* En_adj_80 << 15 | En_adj_48 << 14 | 5121 14 bit 2's comp value */ 5122 bcmPortControlPhyTimesyncTimestampOffset = _SHR_PORT_CONTROL_PHY_TIMESYNC_TIMESTAMP_OFFSET, /* the delay from CMIC to the PCS */ 5123 bcmPortControlPhyTimesyncTimestampAdjust = _SHR_PORT_CONTROL_PHY_TIMESYNC_TIMESTAMP_ADJUST, /* the adjustment of TS */ 5124 bcmPortControlPhyTimesyncOneStepEnable = _SHR_PORT_CONTROL_PHY_TIMESYNC_ONE_STEP_ENABLE /* One step proecssing mode for TS */ 5125 } bcm_port_control_phy_timesync_t; 5126 5127 /* AM norm modes for aggregated port speeds */ 5128 typedef enum bcm_port_phy_timesync_compensation_mode_e { 5129 bcmPortPhyTimesyncCompensationModeNone = _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_NONE, /* No compensation */ 5130 bcmPortPhyTimesyncCompensationModeEarliestLane = _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_EARLIEST_LANE, /* Compensate based on the earliest lane */ 5131 bcmPortPhyTimesyncCompensationModeLatestlane = _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_LATEST_LANE /* Compensate based on the latest lane. */ 5132 } bcm_port_phy_timesync_compensation_mode_t; 5133 5134 /* SA-Discard actions */ 5135 #define BCM_PORT_CONTROL_DISCARD_MACSA_NONE 0x1 /* Packets with drop-sa 5136 are switched by the 5137 device */ 5138 #define BCM_PORT_CONTROL_DISCARD_MACSA_DROP 0x2 /* Packets with drop-sa 5139 are dropped */ 5140 #define BCM_PORT_CONTROL_DISCARD_MACSA_TRAP 0x4 /* Packets with drop-sa 5141 are copied to the CPU */ 5142 5143 /* Unknown DA actions */ 5144 #define BCM_PORT_CONTROL_UNKNOWN_MACDA_NONE 0x1 /* Packets with 5145 unknown-da are 5146 switched by the device */ 5147 #define BCM_PORT_CONTROL_UNKNOWN_MACDA_DROP 0x2 /* Packets with 5148 unknown-da are dropped */ 5149 #define BCM_PORT_CONTROL_UNKNOWN_MACDA_TRAP 0x4 /* Packets with 5150 unknown-da are copied 5151 to the CPU */ 5152 5153 /* Per Port Filter enable/disable control */ 5154 #define BCM_PORT_CONTROL_FILTER_DISABLE_UNKNOWN_DA_UC 0x1 /* disable egress filter 5155 for unknown Unicast 5156 packets */ 5157 #define BCM_PORT_CONTROL_FILTER_DISABLE_UNKNOWN_DA_MC 0x2 /* disable egress filter 5158 for unknown Multicast 5159 packets */ 5160 #define BCM_PORT_CONTROL_FILTER_DISABLE_DA_BC 0x4 /* disable egress filter 5161 for Broadcast packets */ 5162 #define BCM_PORT_CONTROL_FILTER_DISABLE_ALL 0xFFFFFFFF /* disable all egress 5163 filter */ 5164 5165 /* sFlow packet sample destiantion flags */ 5166 #define BCM_PORT_CONTROL_SAMPLE_DEST_CPU 0x1 /* Copy packet samples to 5167 CPU */ 5168 #define BCM_PORT_CONTROL_SAMPLE_DEST_MIRROR 0x2 /* Copy packet samples to 5169 all mirror 5170 destinations created 5171 with 5172 BCM_MIRROR_PORT_SFLOW 5173 flag */ 5174 5175 /* Set EVB Port type. */ 5176 typedef enum bcm_port_evb_type_e { 5177 bcmPortEvbTypeNone = 0, 5178 bcmPortEvbTypeUplinkAccess = 1, 5179 bcmPortEvbTypeCount = 2 /* Must be last */ 5180 } bcm_port_evb_type_t; 5181 5182 /* SyncE recovered clock source */ 5183 typedef enum bcm_port_phy_clock_source_e { 5184 bcmPortPhyClockSourcePrimary = _SHR_PORT_PHY_CLOCK_SOURCE_PRIMARY, /* Recovery clock is being derived from 5185 primary port's recovered clock */ 5186 bcmPortPhyClockSourceSecondary = _SHR_PORT_PHY_CLOCK_SOURCE_SECONDARY /* Recovery clock is being derived from 5187 the secondary port's recovered clock */ 5188 } bcm_port_phy_clock_source_t; 5189 5190 /* FrameSync mode */ 5191 typedef enum bcm_port_phy_timesync_framesync_mode_e { 5192 bcmPortPhyTimesyncFramesyncNone = _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_NONE, /* Do nothing */ 5193 bcmPortPhyTimesyncFramesyncSyncin0 = _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN0, /* Use long pulse on SyncIn0 for 5194 FrameSync */ 5195 bcmPortPhyTimesyncFramesyncSyncin1 = _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN1, /* Use SyncIn1 as FrameSync */ 5196 bcmPortPhyTimesyncFramesyncSyncout = _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCOUT, /* Use internal SyncOut as FrameSync */ 5197 bcmPortPhyTimesyncFramesyncCpu = _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_CPU /* CPU based immediate FrameSync */ 5198 } bcm_port_phy_timesync_framesync_mode_t; 5199 5200 /* FrameSync configuration type. */ 5201 typedef struct bcm_port_phy_timesync_framesync_s { 5202 bcm_port_phy_timesync_framesync_mode_t mode; /* framesync mode */ 5203 uint32 length_threshold; /* syncin threshold for framesync */ 5204 uint32 event_offset; /* event offset for framesync */ 5205 } bcm_port_phy_timesync_framesync_t; 5206 5207 /* SyncOut mode */ 5208 typedef enum bcm_port_phy_timesync_syncout_mode_e { 5209 bcmPortPhyTimesyncSyncoutDisable = _SHR_PORT_PHY_TIMESYNC_SYNCOUT_DISABLE, /* Do nothing */ 5210 bcmPortPhyTimesyncSyncoutOneTime = _SHR_PORT_PHY_TIMESYNC_SYNCOUT_ONE_TIME, /* One time SYNC pulse on a match with 5211 the timesync heartbeat */ 5212 bcmPortPhyTimesyncSyncoutPulseTrain = _SHR_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN, /* Pulse train on SyncOut */ 5213 bcmPortPhyTimesyncSyncoutPulseTrainWithSync = _SHR_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN_WITH_SYNC /* Combination of pulse train and one 5214 time SYNC */ 5215 } bcm_port_phy_timesync_syncout_mode_t; 5216 5217 /* Event Message Type */ 5218 typedef enum bcm_port_phy_timesync_msg_e { 5219 bcmPortPhyTimesyncMsgSync = _SHR_PORT_PHY_TIMESYNC_MSG_SYNC, /* Sync */ 5220 bcmPortPhyTimesyncMsgDelayReq = _SHR_PORT_PHY_TIMESYNC_MSG_DELAY_REQ, /* Delay Request */ 5221 bcmPortPhyTimesyncMsgPdelayReq = _SHR_PORT_PHY_TIMESYNC_MSG_PDELAY_REQ, /* PDelay Request */ 5222 bcmPortPhyTimesyncMsgPdelayResp = _SHR_PORT_PHY_TIMESYNC_MSG_PDELAY_RESP /* PDelay Response */ 5223 } bcm_port_phy_timesync_msg_t; 5224 5225 /* Protocol Type */ 5226 typedef enum bcm_port_phy_timesync_prot_e { 5227 bcmPortPhyTimesyncProtLayer2 = _SHR_PORT_PHY_TIMESYNC_PROT_LAYER2, /* 1588 over Layer 2 */ 5228 bcmPortPhyTimesyncProtIpv4Udp = _SHR_PORT_PHY_TIMESYNC_PROT_IPV4_UDP, /* 1588 over IPv4 UDP */ 5229 bcmbcmPortPhyTimesyncProtIpv6Udp = _SHR_PORT_PHY_TIMESYNC_PROT_IPV6_UDP /* 1588 over IPv6 UDP */ 5230 } bcm_port_phy_timesync_prot_t; 5231 5232 /* Direction Type */ 5233 typedef enum bcm_port_phy_timesync_dir_e { 5234 bcmPortPhyTimesyncDirEgress = _SHR_PORT_PHY_TIMESYNC_DIR_EGRESS, /* Egress Packet */ 5235 bcmPortPhyTimesyncDirIngress = _SHR_PORT_PHY_TIMESYNC_DIR_INGRESS /* Igress Packet */ 5236 } bcm_port_phy_timesync_dir_t; 5237 5238 /* TimeSync timer mode */ 5239 typedef enum bcm_port_phy_timesync_timer_mode_e { 5240 bcmPortPhyTimesyncTimerModeNone = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_NONE, /* No TimeSync timer */ 5241 bcmPortPhyTimesyncTimerModeDefault = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_DEFAULT, /* Use the default TimeSync timer */ 5242 bcmPortPhyTimesyncTimerMode32bit = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_32BIT, /* Use 32-bit TimeSync timer */ 5243 bcmPortPhyTimesyncTimerMode48bit = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_48BIT, /* Use 48-bit TimeSync timer */ 5244 bcmPortPhyTimesyncTimerMode64bit = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_64BIT, /* Use 64-bit TimeSync timer */ 5245 bcmPortPhyTimesyncTimerMode80bit = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_80BIT /* Use 80-bit TimeSync timer */ 5246 } bcm_port_phy_timesync_timer_mode_t; 5247 5248 /* Flow control modes */ 5249 typedef enum bcm_port_phy_control_flow_control_mode_e { 5250 bcmPortPhyControlFlowCtrlModeNone = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_MODE_NONE, /* No flow control mode (Relay mode) */ 5251 bcmPortPhyControlFlowCtrlLegacyPauseEn = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_LEGACY_PAUSE_EN, /* Lagacy Pause flow control mode */ 5252 bcmPortPhyControlFlowCtrlPfcPause = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_PFC_PAUSE, /* PFC flow control mode */ 5253 bcmPortPhyControlFlowCtrlLlfc = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_LLFC /* LLFC flow control mode */ 5254 } bcm_port_phy_control_flow_control_mode_t; 5255 5256 /* Parameter for bcmPortControlFieldEgressClassSelect */ 5257 typedef enum bcm_port_field_egress_class_select_e { 5258 bcmPortEgressClassSelectNone = 0, /* Class Id Not Assigned. */ 5259 bcmPortEgressClassSelectPort = 1, /* Class Id from Port Interface. */ 5260 bcmPortEgressClassSelectSvp = 2, /* Class Id from SVP. */ 5261 bcmPortEgressClassSelectL3Interface = 3, /* Class Id from L3 IIF Interface. */ 5262 bcmPortEgressClassSelectFieldSrc = 4, /* Class Id from VFP HI. */ 5263 bcmPortEgressClassSelectFieldDst = 5, /* Class Id from VFP LOW. */ 5264 bcmPortEgressClassSelectL2Src = 6, /* Class Id from L2 SRC. */ 5265 bcmPortEgressClassSelectL2Dst = 7, /* Class Id from L2 DST. */ 5266 bcmPortEgressClassSelectL3Src = 8, /* Class Id from L3 SRC. */ 5267 bcmPortEgressClassSelectL3Dst = 9, /* Class Id from L3 DST. */ 5268 bcmPortEgressClassSelectVlan = 10, /* Class Id from VLAN Interface. */ 5269 bcmPortEgressClassSelectVrf = 11, /* Class Id from VRF. */ 5270 bcmPortEgressClassSelectFieldIngress = 12, /* Class Id from IFP Policy Table. */ 5271 bcmPortEgressClassSelectCount = 13 /* Always Last. Not a usable value. */ 5272 } bcm_port_field_egress_class_select_t; 5273 5274 /* Parameter for bcmPortControlFieldHiGigClassSelect */ 5275 typedef enum bcm_port_field_higig_class_select_e { 5276 bcmPortFieldHiGigClassSelectNone = 0, /* Class Id Not Assigned. */ 5277 bcmPortFieldHiGigClassSelectIngressToEgress = 1, /* Class Id passed from ingress to 5278 egress. */ 5279 bcmPortFieldHiGigClassSelectL3Egress = 2, /* Class Id from L3 egress object. */ 5280 bcmPortFieldHiGigClassSelectL3EgressIntf = 3, /* Class Id from L3 egress interface. */ 5281 bcmPortFieldHiGigClassSelectEgressGport = 4, /* Class Id from egress dvp. */ 5282 bcmPortFieldHiGigClassSelectCount = 5 /* Always Last. Not a usable value. */ 5283 } bcm_port_field_higig_class_select_t; 5284 5285 /* syncout configuration type. */ 5286 typedef struct bcm_port_phy_timesync_syncout_s { 5287 bcm_port_phy_timesync_syncout_mode_t mode; /* syncout mode */ 5288 uint16 pulse_1_length; /* pulse 1 length in ns */ 5289 uint16 pulse_2_length; /* pulse 2 length in ns */ 5290 uint32 interval; /* interval in ns */ 5291 uint64 syncout_ts; /* syncout timestamp */ 5292 } bcm_port_phy_timesync_syncout_t; 5293 5294 /* MPLS label type. */ 5295 typedef struct bcm_port_phy_timesync_mpls_label_s { 5296 bcm_mpls_label_t value; /* label value */ 5297 bcm_mpls_label_t mask; /* label mask */ 5298 uint32 flags; /* MPLS label flags */ 5299 } bcm_port_phy_timesync_mpls_label_t; 5300 5301 /* MPLS control type. */ 5302 typedef struct bcm_port_phy_timesync_mpls_control_s { 5303 uint32 flags; /* MPLS control flags */ 5304 bcm_mpls_label_t special_label; /* special label value */ 5305 bcm_port_phy_timesync_mpls_label_t labels[10]; /* Timesync MPLS labels */ 5306 int size; /* Number of valid elements in label 5307 array */ 5308 } bcm_port_phy_timesync_mpls_control_t; 5309 5310 /* Timer adjustment type. */ 5311 typedef struct bcm_port_phy_timesync_timer_adjust_s { 5312 bcm_port_phy_timesync_timer_mode_t mode; /* Timer adjustment mode */ 5313 int delta; /* Timer adjustment delta value */ 5314 } bcm_port_phy_timesync_timer_adjust_t; 5315 5316 /* Inband TS control type. */ 5317 typedef struct bcm_port_phy_timesync_inband_control_s { 5318 uint32 flags; /* Inband TS control flags */ 5319 uint32 resv0_id; /* Resv0 ID used */ 5320 bcm_port_phy_timesync_timer_mode_t timer_mode; /* Timer mode */ 5321 } bcm_port_phy_timesync_inband_control_t; 5322 5323 /* Enhanced capture type. */ 5324 typedef struct bcm_port_phy_timesync_enhanced_capture_s { 5325 bcm_port_phy_timesync_msg_t msg_type; /* Message type */ 5326 bcm_port_phy_timesync_prot_t protocol; /* Protocol type */ 5327 bcm_port_phy_timesync_dir_t direction; /* Direction type */ 5328 uint32 seq_id; /* Sequence ID */ 5329 uint32 domain; /* Domain */ 5330 uint64 timestamp; /* Timestamp */ 5331 uint64 source_port_identity; /* Source port identity */ 5332 uint16 source_port; /* Source port */ 5333 uint16 vlan_id; /* Vlan ID */ 5334 } bcm_port_phy_timesync_enhanced_capture_t; 5335 5336 /* Base timesync configuration type. */ 5337 typedef struct bcm_port_phy_timesync_config_s { 5338 uint32 capabilities; /* Flags BCM_PORT_PHY_TIMESYNC_CAP_* */ 5339 uint32 validity_mask; /* Flags BCM_PORT_PHY_TIMESYNC_VALID_* */ 5340 uint32 flags; /* Flags BCM_PORT_PHY_TIMESYNC_* */ 5341 uint16 itpid; /* 1588 inner tag */ 5342 uint16 otpid; /* 1588 outer tag */ 5343 uint16 otpid2; /* 1588 outer tag2 */ 5344 bcm_port_phy_timesync_timer_adjust_t timer_adjust; /* Direct timer adjustment */ 5345 bcm_port_phy_timesync_inband_control_t inband_control; /* Inband TS control */ 5346 bcm_port_phy_timesync_global_mode_t gmode; /* Global mode */ 5347 bcm_port_phy_timesync_framesync_t framesync; /* Framesync */ 5348 bcm_port_phy_timesync_syncout_t syncout; /* Syncout */ 5349 uint16 ts_divider; /* TS divider */ 5350 bcm_time_spec_t original_timecode; /* Original timecode to be inserted */ 5351 uint32 tx_timestamp_offset; /* TX AFE delay in ns - per port */ 5352 uint32 rx_timestamp_offset; /* RX AFE delay in ns - per port */ 5353 uint32 rx_link_delay; /* RX link delay */ 5354 bcm_port_phy_timesync_event_message_egress_mode_t tx_sync_mode; /* sync */ 5355 bcm_port_phy_timesync_event_message_egress_mode_t tx_delay_request_mode; /* delay request */ 5356 bcm_port_phy_timesync_event_message_egress_mode_t tx_pdelay_request_mode; /* pdelay request */ 5357 bcm_port_phy_timesync_event_message_egress_mode_t tx_pdelay_response_mode; /* pdelay response */ 5358 bcm_port_phy_timesync_event_message_ingress_mode_t rx_sync_mode; /* sync */ 5359 bcm_port_phy_timesync_event_message_ingress_mode_t rx_delay_request_mode; /* delay request */ 5360 bcm_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_request_mode; /* pdelay request */ 5361 bcm_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_response_mode; /* pdelay response */ 5362 bcm_port_phy_timesync_mpls_control_t mpls_control; /* MPLS control */ 5363 uint32 sync_freq; /* DPLL sync freq. */ 5364 uint16 phy_1588_dpll_k1; /* DPLL K1 */ 5365 uint16 phy_1588_dpll_k2; /* DPLL K2 */ 5366 uint16 phy_1588_dpll_k3; /* DPLL K3 */ 5367 uint64 phy_1588_dpll_loop_filter; /* DPLL loop filter */ 5368 uint64 phy_1588_dpll_ref_phase; /* DPLL ref phase */ 5369 uint32 phy_1588_dpll_ref_phase_delta; /* DPLL ref phase delta */ 5370 } bcm_port_phy_timesync_config_t; 5371 5372 /* Initialize a Port Configuration structure. */ 5373 extern void bcm_port_timesync_config_t_init( 5374 bcm_port_timesync_config_t *port_timesync_config); 5375 5376 /* Initialize a Port Configuration structure. */ 5377 extern void bcm_port_phy_timesync_config_t_init( 5378 bcm_port_phy_timesync_config_t *conf); 5379 5380 #ifndef BCM_HIDE_DISPATCHABLE 5381 5382 /* Set/get the port configuration for the specified device. */ 5383 extern int bcm_port_phy_timesync_config_set( 5384 int unit, 5385 bcm_port_t port, 5386 bcm_port_phy_timesync_config_t *conf); 5387 5388 /* Set/get the port configuration for the specified device. */ 5389 extern int bcm_port_phy_timesync_config_get( 5390 int unit, 5391 bcm_port_t port, 5392 bcm_port_phy_timesync_config_t *conf); 5393 5394 /* Retrieved the port configuration for the specified device. */ 5395 extern int bcm_port_control_phy_timesync_set( 5396 int unit, 5397 bcm_port_t port, 5398 bcm_port_control_phy_timesync_t type, 5399 uint64 value); 5400 5401 /* Retrieved the port configuration for the specified device. */ 5402 extern int bcm_port_control_phy_timesync_get( 5403 int unit, 5404 bcm_port_t port, 5405 bcm_port_control_phy_timesync_t type, 5406 uint64 *value); 5407 5408 /* Retrieved the port configuration for the specified device. */ 5409 extern int bcm_port_phy_timesync_enhanced_capture_get( 5410 int unit, 5411 bcm_port_t port, 5412 bcm_port_phy_timesync_enhanced_capture_t *value); 5413 5414 #endif /* BCM_HIDE_DISPATCHABLE */ 5415 5416 #define BCM_PORT_PHY_OAM_DM_MAC_CHECK_ENABLE _SHR_PORT_PHY_OAM_MAC_CHECK_ENABLE /* Enable MAC check for 5417 Delay Measurement */ 5418 #define BCM_PORT_PHY_OAM_DM_CONTROL_WORD_ENABLE _SHR_PORT_PHY_OAM_CONTROL_WORD_ENABLE /* Enable Control Word 5419 for Delay Measurement */ 5420 #define BCM_PORT_PHY_OAM_DM_ENTROPY_ENABLE _SHR_PORT_PHY_OAM_DM_ENTROPY_ENABLE /* Enable entropy for 5421 Delay Measurement */ 5422 #define BCM_PORT_PHY_OAM_DM_TS_FORMAT _SHR_PORT_PHY_OAM_DM_TS_FORMAT /* Select timestamp 5423 format PTP(0)/NTP(1) 5424 for Delay Measurement */ 5425 5426 /* Port controls for phy OAM */ 5427 typedef enum bcm_port_control_phy_oam_e { 5428 bcmPortControlPhyOamDmTxEthertype = _SHR_PORT_CONTROL_PHY_OAM_DM_TX_ETHERTYPE, /* OAM Delay measurement Tx EtherType */ 5429 bcmPortControlPhyOamDmRxEthertype = _SHR_PORT_CONTROL_PHY_OAM_DM_RX_ETHERTYPE, /* OAM Delay measurement Rx EtherType */ 5430 bcmPortControlPhyOamDmTxPortMacAddressIndex = _SHR_PORT_CONTROL_PHY_OAM_DM_TX_PORT_MAC_ADDRESS_INDEX, /* Index to select the MAC address. Use 5431 index of 1 to select MacAddress1, 5432 index of 2 for MacAddress2 and so 5433 forth. */ 5434 bcmPortControlPhyOamDmRxPortMacAddressIndex = _SHR_PORT_CONTROL_PHY_OAM_DM_RX_PORT_MAC_ADDRESS_INDEX, /* Index to select the MAC address. Use 5435 index of 1 to select MacAddress1, 5436 index of 2 for MacAddress2 and so 5437 forth. */ 5438 bcmPortControlPhyOamDmMacAddress1 = _SHR_PORT_CONTROL_PHY_OAM_DM_MAC_ADDRESS_1, /* OAM Delay measurement MAC address 1. 5439 There can be multiple MAC address to 5440 choose from in a PHY depending upon 5441 the design */ 5442 bcmPortControlPhyOamDmMacAddress2 = _SHR_PORT_CONTROL_PHY_OAM_DM_MAC_ADDRESS_2, /* OAM Delay measurement MAC address 2. 5443 There can be multiple MAC address to 5444 choose from in a PHY depending upon 5445 the design */ 5446 bcmPortControlPhyOamDmMacAddress3 = _SHR_PORT_CONTROL_PHY_OAM_DM_MAC_ADDRESS_3 /* OAM Delay measurement MAC address 3. 5447 There can be multiple MAC address to 5448 choose from in a PHY depending upon 5449 the design */ 5450 } bcm_port_control_phy_oam_t; 5451 5452 /* Phy OAM Delay Measurement Modes */ 5453 typedef enum bcm_port_config_phy_oam_dm_mode_e { 5454 bcmPortConfigPhyOamDmModeY1731 = _SHR_PORT_CONFIG_PHY_OAM_DM_Y1731, /* OAM Delay measurement Y.7131 Mode */ 5455 bcmPortConfigPhyOamDmModeBhh = _SHR_PORT_CONFIG_PHY_OAM_DM_BHH, /* OAM Delay measurement BHH Mode */ 5456 bcmPortConfigPhyOamDmModeIetf = _SHR_PORT_CONFIG_PHY_OAM_DM_IETF /* OAM Delay measurement IETF Mode */ 5457 } bcm_port_config_phy_oam_dm_mode_t; 5458 5459 /* Phy OAM Delay measurement config type. */ 5460 typedef struct bcm_port_config_phy_oam_dm_s { 5461 uint32 flags; /* OAM Delay Measurement config flags */ 5462 bcm_port_config_phy_oam_dm_mode_t mode; /* OAM Delay Measurement mode Y.1731, 5463 BHH or IETF */ 5464 } bcm_port_config_phy_oam_dm_t; 5465 5466 /* Phy OAM config type. */ 5467 typedef struct bcm_port_config_phy_oam_s { 5468 bcm_port_config_phy_oam_dm_t tx_dm_config; /* OAM delay measurement config for Tx */ 5469 bcm_port_config_phy_oam_dm_t rx_dm_config; /* OAM delay measurement config for Rx */ 5470 } bcm_port_config_phy_oam_t; 5471 5472 #ifndef BCM_HIDE_DISPATCHABLE 5473 5474 /* Set OAM configurations for the PHY. */ 5475 extern int bcm_port_config_phy_oam_set( 5476 int unit, 5477 bcm_port_t port, 5478 bcm_port_config_phy_oam_t *conf); 5479 5480 /* Gets OAM configurations for the PHY. */ 5481 extern int bcm_port_config_phy_oam_get( 5482 int unit, 5483 bcm_port_t port, 5484 bcm_port_config_phy_oam_t *conf); 5485 5486 /* Set the value for a particular OAM control type. */ 5487 extern int bcm_port_control_phy_oam_set( 5488 int unit, 5489 bcm_port_t port, 5490 bcm_port_control_phy_oam_t type, 5491 uint64 value); 5492 5493 /* Get the value for a particular OAM control type. */ 5494 extern int bcm_port_control_phy_oam_get( 5495 int unit, 5496 bcm_port_t port, 5497 bcm_port_control_phy_oam_t type, 5498 uint64 *value); 5499 5500 #endif /* BCM_HIDE_DISPATCHABLE */ 5501 5502 #define BCM_PORT_CONGESTION_MAPPING_CLEAR _SHR_PORT_CONGESTION_MAPPING_CLEAR /* Clear mapping */ 5503 #define BCM_PORT_CONGESTION_MAPPING_RX _SHR_PORT_CONGESTION_MAPPING_RX /* Mapping for Rx 5504 Direction */ 5505 #define BCM_PORT_CONGESTION_MAPPING_TX _SHR_PORT_CONGESTION_MAPPING_TX /* Mapping for Tx 5506 Direction */ 5507 5508 #define BCM_PORT_CHANNEL_ID_SET(_channel_id, _port_base, _port_ch) \ 5509 _SHR_PORT_CHANNEL_ID_SET(_channel_id, _port_base, _port_ch) 5510 5511 #define BCM_PORT_CHANNEL_ID_PORT_BASE_GET(_channel_id) \ 5512 _SHR_PORT_CHANNEL_ID_PORT_BASE_GET(_channel_id) 5513 5514 #define BCM_PORT_CHANNEL_ID_PORT_CH_GET(_channel_id) \ 5515 _SHR_PORT_CHANNEL_ID_PORT_CH_GET(_channel_id) 5516 5517 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_BACKPLANE _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_BACKPLANE 5518 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_COPPER_CABLE _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_COPPER_CABLE 5519 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_OPTICS _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_OPTICS 5520 5521 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_SET(lane_config) \ 5522 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_SET(lane_config) 5523 5524 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_GET(lane_config) \ 5525 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_GET(lane_config) 5526 5527 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_CLEAR(lane_config) \ 5528 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_CLEAR(lane_config) 5529 5530 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_SET(lane_config) \ 5531 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_SET(lane_config) 5532 5533 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_GET(lane_config) \ 5534 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_GET(lane_config) 5535 5536 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_CLEAR(lane_config) \ 5537 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_CLEAR(lane_config) 5538 5539 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_SET(lane_config) \ 5540 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_SET(lane_config) 5541 5542 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_GET(lane_config) \ 5543 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_GET(lane_config) 5544 5545 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_CLEAR(lane_config) \ 5546 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_CLEAR(lane_config) 5547 5548 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_SET(lane_config, medium_type) \ 5549 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_SET(lane_config, medium_type) 5550 5551 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_GET(lane_config) \ 5552 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_GET(lane_config) 5553 5554 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_CLEAR(lane_config) \ 5555 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_CLEAR(lane_config) 5556 5557 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_SET(lane_config) \ 5558 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_SET(lane_config) 5559 5560 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_GET(lane_config) \ 5561 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_GET(lane_config) 5562 5563 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_CLEAR(lane_config) \ 5564 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_CLEAR(lane_config) 5565 5566 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_SET(lane_config) \ 5567 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_SET(lane_config) 5568 5569 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_GET(lane_config) \ 5570 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_GET(lane_config) 5571 5572 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_CLEAR(lane_config) \ 5573 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_CLEAR(lane_config) 5574 5575 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_SET(lane_config) \ 5576 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_SET(lane_config) 5577 5578 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_GET(lane_config) \ 5579 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_GET(lane_config) 5580 5581 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_CLEAR(lane_config) \ 5582 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_CLEAR(lane_config) 5583 5584 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_SET(lane_config) \ 5585 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_SET(lane_config) 5586 5587 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_GET(lane_config) \ 5588 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_GET(lane_config) 5589 5590 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_CLEAR(lane_config) \ 5591 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_CLEAR(lane_config) 5592 5593 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_SET(lane_config) \ 5594 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_SET(lane_config) 5595 5596 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_GET(lane_config) \ 5597 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_GET(lane_config) 5598 5599 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_CLEAR(lane_config) \ 5600 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_CLEAR(lane_config) 5601 5602 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_SET(lane_config) \ 5603 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_SET(lane_config) 5604 5605 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_GET(lane_config) \ 5606 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_GET(lane_config) 5607 5608 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_CLEAR(lane_config) \ 5609 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_CLEAR(lane_config) 5610 5611 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_SET(lane_config) \ 5612 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_SET(lane_config) 5613 5614 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_GET(lane_config) \ 5615 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_GET(lane_config) 5616 5617 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_CLEAR(lane_config) \ 5618 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_CLEAR(lane_config) 5619 5620 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_SET(lane_config) \ 5621 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_SET(lane_config) 5622 5623 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_GET(lane_config) \ 5624 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_GET(lane_config) 5625 5626 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_CLEAR(lane_config) \ 5627 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_CLEAR(lane_config) 5628 5629 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_SET(lane_config, channel_loss) \ 5630 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_SET(lane_config, channel_loss) 5631 5632 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_GET(lane_config) \ 5633 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_GET(lane_config) 5634 5635 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_CLEAR(lane_config) \ 5636 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_CLEAR(lane_config) 5637 5638 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_SET(lane_config) \ 5639 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_SET(lane_config) 5640 5641 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_GET(lane_config) \ 5642 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_GET(lane_config) 5643 5644 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_CLEAR(lane_config) \ 5645 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_CLEAR(lane_config) 5646 5647 #ifndef BCM_HIDE_DISPATCHABLE 5648 5649 /* Set mapping for port to HCFC port(channel_id) */ 5650 extern int bcm_port_congestion_set( 5651 int unit, 5652 bcm_gport_t congestion_port, 5653 bcm_gport_t port, 5654 uint32 flags, 5655 int channel_id); 5656 5657 /* retreive mapping for port to HCFC port(channel_id) */ 5658 extern int bcm_port_congestion_get( 5659 int unit, 5660 bcm_gport_t congestion_port, 5661 bcm_gport_t port, 5662 uint32 flags, 5663 int *channel_id); 5664 5665 /* Attach counter entries to the given gport. */ 5666 extern int bcm_port_stat_attach( 5667 int unit, 5668 bcm_gport_t port, 5669 uint32 stat_counter_id); 5670 5671 /* Detach counter entries to the given gport. */ 5672 extern int bcm_port_stat_detach( 5673 int unit, 5674 bcm_gport_t port); 5675 5676 /* 5677 * Detach counter entries to the given gport with a given stat counter 5678 * id. 5679 */ 5680 extern int bcm_port_stat_detach_with_id( 5681 int unit, 5682 bcm_gport_t port, 5683 uint32 stat_counter_id); 5684 5685 /* Get counter values for specified gport based on port statistic type. */ 5686 extern int bcm_port_stat_counter_get( 5687 int unit, 5688 bcm_gport_t port, 5689 bcm_port_stat_t stat, 5690 uint32 num_entries, 5691 uint32 *counter_indexes, 5692 bcm_stat_value_t *counter_values); 5693 5694 /* 5695 * Force an immediate counter update and retrieve counter values for 5696 * specified gport based on port statistic type. 5697 */ 5698 extern int bcm_port_stat_counter_sync_get( 5699 int unit, 5700 bcm_gport_t port, 5701 bcm_port_stat_t stat, 5702 uint32 num_entries, 5703 uint32 *counter_indexes, 5704 bcm_stat_value_t *counter_values); 5705 5706 /* Set counter values for specified gport based on port statistic type. */ 5707 extern int bcm_port_stat_counter_set( 5708 int unit, 5709 bcm_gport_t port, 5710 bcm_port_stat_t stat, 5711 uint32 num_entries, 5712 uint32 *counter_indexes, 5713 bcm_stat_value_t *counter_values); 5714 5715 /* Attach flex state action to the given gport. */ 5716 extern int bcm_port_flexstate_attach( 5717 int unit, 5718 bcm_gport_t port, 5719 uint32 action_id); 5720 5721 /* 5722 * Detach flex state action to the given gport with a given flex state 5723 * id. 5724 */ 5725 extern int bcm_port_flexstate_detach_with_id( 5726 int unit, 5727 bcm_gport_t port, 5728 uint32 action_id); 5729 5730 /* Set the encapsulation to port mapping from encap_id to port. */ 5731 extern int bcm_port_encap_map_set( 5732 int unit, 5733 uint32 flags, 5734 bcm_if_t encap_id, 5735 bcm_gport_t port); 5736 5737 /* Get the encapsulation to port mapping from encap_id. */ 5738 extern int bcm_port_encap_map_get( 5739 int unit, 5740 uint32 flags, 5741 bcm_if_t encap_id, 5742 bcm_gport_t *port); 5743 5744 #endif /* BCM_HIDE_DISPATCHABLE */ 5745 5746 /* Allow remapping an encapsulation to a port on a different core. */ 5747 #define BCM_PORT_ENCAP_MAP_ALLOW_CORE_CHANGE 1 5748 5749 #define BCM_PORT_PON_TUNNEL_WITH_ID 0x01 5750 5751 #ifndef BCM_HIDE_DISPATCHABLE 5752 5753 /* Add service classifications(tunnel-port-ids) per pon port. */ 5754 extern int bcm_port_pon_tunnel_add( 5755 int unit, 5756 bcm_gport_t pon_port, 5757 uint32 flags, 5758 bcm_gport_t *tunnel_port_id); 5759 5760 /* Remove service classifications(tunnel-port-ids) per pon port. */ 5761 extern int bcm_port_pon_tunnel_remove( 5762 int unit, 5763 bcm_gport_t tunnel_port_id); 5764 5765 /* Set the tunnel id to the service class mapping */ 5766 extern int bcm_port_pon_tunnel_map_set( 5767 int unit, 5768 bcm_gport_t pon_port, 5769 bcm_tunnel_id_t tunnel_id, 5770 bcm_gport_t tunnel_port_id); 5771 5772 /* Get the tunnel id to the service class mapping */ 5773 extern int bcm_port_pon_tunnel_map_get( 5774 int unit, 5775 bcm_gport_t pon_port, 5776 bcm_tunnel_id_t tunnel_id, 5777 bcm_gport_t *tunnel_port_id); 5778 5779 #endif /* BCM_HIDE_DISPATCHABLE */ 5780 5781 /* Statistics threshold flag. */ 5782 #define BCM_STAT_THRESHOLD_FLAGS_NOT (1 << 0) 5783 5784 /* threshold type */ 5785 typedef enum bcm_stat_threshold_type_e { 5786 bcmStatThresholdDisabled = 0, 5787 bcmStatThresholdSingle = 1, 5788 bcmStatThresholdRange = 2, 5789 bcmStatThresholdZero = 3, 5790 bcmStatThresholdSigned = 4 5791 } bcm_stat_threshold_type_t; 5792 5793 /* 5794 * Statistics threshold information. 5795 * Interpretations of arg1 and arg2: 5796 * single: 5797 * stat > arg1 raises alarm; stat <= arg2 clears alarm 5798 * range: 5799 * !(arg1 <= stat <= arg2) raises alarm; inverse clears alarm 5800 * zero: 5801 * stat == 0 raises alarm; stat != 0 clears alarm. arg1/2 ignored 5802 * signed: 5803 * as range, except arg1/2 are interpreted as signed (int32_t) 5804 */ 5805 typedef struct bcm_stat_threshold_s { 5806 bcm_stat_threshold_type_t type; /* threshold type, per-type data follows */ 5807 uint32 flags; /* threshold flag */ 5808 uint32 arg1; /* threshold parameter 1 */ 5809 uint32 arg2; /* threshold parameter 2 */ 5810 } bcm_stat_threshold_t; 5811 5812 #ifndef BCM_HIDE_DISPATCHABLE 5813 5814 /* Statistics threshold set */ 5815 extern int bcm_stat_threshold_set( 5816 int unit, 5817 bcm_port_t port, 5818 bcm_stat_val_t stat, 5819 bcm_stat_threshold_t *threshold); 5820 5821 /* Statistics threshold get */ 5822 extern int bcm_stat_threshold_get( 5823 int unit, 5824 bcm_port_t port, 5825 bcm_stat_val_t stat, 5826 bcm_stat_threshold_t *threshold); 5827 5828 /* Get all allowed outer tag protocol IDs (TPIDs) for the specified port. */ 5829 extern int bcm_port_tpid_get_all( 5830 int unit, 5831 bcm_port_t port, 5832 int size, 5833 uint16 *tpid_array, 5834 int *color_array, 5835 int *count); 5836 5837 /* 5838 * Get all allowed L2 tunnel payload outer tag protocol IDs (TPIDs) for 5839 * the specified port. 5840 */ 5841 extern int bcm_port_l2_tunnel_payload_tpid_get_all( 5842 int unit, 5843 bcm_port_t port, 5844 int size, 5845 uint16 *tpid_array, 5846 int *color_array, 5847 int *count); 5848 5849 #endif /* BCM_HIDE_DISPATCHABLE */ 5850 5851 /* FCOE Fabric select. Used with bcmPortControlFcoeFabricSel */ 5852 typedef enum bcm_port_fcoe_vsan_select_e { 5853 bcmPortFcoeVsanSelectVft = 0, /* use VFT header */ 5854 bcmPortFcoeVsanSelectPort = 1, /* use Port Table value */ 5855 bcmPortFcoeVsanSelectInnerVlan = 2, /* use incoming inner VID/COS */ 5856 bcmPortFcoeVsanSelectOuterVlan = 3 /* use incoming outer VID/COS */ 5857 } bcm_port_fcoe_vsan_select_t; 5858 5859 /* 5860 * BCM56960 Port ASF (Cut-thru) Modes. Used with 5861 * bcmSwitchAlternateStoreForward 5862 */ 5863 typedef enum bcm_port_asf_mode_e { 5864 bcmPortAsfModeStoreAndForward = 0, /* Store and Forward (SAF) forwarding 5865 mode */ 5866 bcmPortAsfModeSameSpeed = 1, /* Cut-thru forwarding between same 5867 speed ports */ 5868 bcmPortAsfModeSlowToFast = 2, /* Cut-thru forwarding between slower to 5869 faster speed ports */ 5870 bcmPortAsfModeFastToSlow = 3 /* Cut-thru forwarding between faster to 5871 slower speed ports */ 5872 } bcm_port_asf_mode_t; 5873 5874 /* Define port mapping type */ 5875 typedef enum bcm_port_extender_mapping_type_e { 5876 bcmPortExtenderMappingTypePonTunnel = 0, /* Map information includes PON port and 5877 Tunnel-ID */ 5878 bcmPortExtenderMappingTypePortVlan = 1, /* Map information includes Phy Port and 5879 VLAN-ID */ 5880 bcmPortExtenderMappingTypeUserDefineValue = 2 /* Map information includes user define 5881 fields */ 5882 } bcm_port_extender_mapping_type_t; 5883 5884 #define BCM_PORT_EXTENDER_MAPPING_INGRESS 0x0001 /* Map information to 5885 Incoming local PP port */ 5886 #define BCM_PORT_EXTENDER_MAPPING_EGRESS 0x0002 /* Map information to 5887 Outgoing local PP port */ 5888 5889 /* port mapping information */ 5890 typedef struct bcm_port_extender_mapping_info_s { 5891 bcm_gport_t pp_port; /* Mapped Local PP port */ 5892 bcm_tunnel_id_t tunnel_id; /* Tunnel-ID */ 5893 bcm_gport_t phy_port; /* Physical Port connected to interface x 5894 channel */ 5895 bcm_vlan_t vlan; /* VLAN-ID */ 5896 uint32 user_define_value; /* User define value from header */ 5897 } bcm_port_extender_mapping_info_t; 5898 5899 /* Initialize a port extender mapping struct. */ 5900 extern void bcm_port_extender_mapping_info_t_init( 5901 bcm_port_extender_mapping_info_t *mapping_info); 5902 5903 #ifndef BCM_HIDE_DISPATCHABLE 5904 5905 /* 5906 * Configure/retrieve port extender mapping from different inputs to 5907 * Local pp port. 5908 */ 5909 extern int bcm_port_extender_mapping_info_set( 5910 int unit, 5911 uint32 flags, 5912 bcm_port_extender_mapping_type_t type, 5913 bcm_port_extender_mapping_info_t *mapping_info); 5914 5915 /* 5916 * Configure/retrieve port extender mapping from different inputs to 5917 * Local pp port. 5918 */ 5919 extern int bcm_port_extender_mapping_info_get( 5920 int unit, 5921 uint32 flags, 5922 bcm_port_extender_mapping_type_t type, 5923 bcm_port_extender_mapping_info_t *mapping_info); 5924 5925 #endif /* BCM_HIDE_DISPATCHABLE */ 5926 5927 /* Define vxlan vpn assignment criteria type */ 5928 typedef enum bcm_port_vxlan_vpn_assignment_criteria_e { 5929 bcmPortVxlanVpnAssignOnVnid = 0, /* use VNID. */ 5930 bcmPortVxlanVpnAssignOnVnidSrcIp = 1, /* use VNID and SIP. */ 5931 bcmPortVxlanVpnAssignOnVnidOuterVlan = 2, /* use VNID and OVID. */ 5932 bcmPortVxlanVpnAssignOnVnidOuterVlanSrcIp = 3 /* use VNID , OVID and SIP. */ 5933 } bcm_port_vxlan_vpn_assignment_criteria_t; 5934 5935 /* Define vxlan termination match criteria type */ 5936 typedef enum bcm_port_vxlan_termination_match_criteria_e { 5937 bcmPortVxlanTerminationMatchDstIp = 0, /* Match destination IP. */ 5938 bcmPortVxlanTerminationMatchOuterVlanDstIp = 1, /* Match outer VLAN ID and destination 5939 IP. */ 5940 bcmPortVxlanTerminationMatchSrcDstIp = 2, /* Match source & destination IP. */ 5941 bcmPortVxlanTerminationMatchOuterVlanSrcDstIp = 3 /* Match outer VLAN ID and source & 5942 destination IP. */ 5943 } bcm_port_vxlan_termination_match_criteria_t; 5944 5945 /* Define vxlan gport assignment criteria type */ 5946 typedef enum bcm_port_vxlan_gport_assignment_criteria_e { 5947 bcmPortVxlanGportAssignOnSrcIp = 0, /* use SIP. */ 5948 bcmPortVxlanGportAssignOnOuterVlanSrcIp = 1 /* use OVID and SIP. */ 5949 } bcm_port_vxlan_gport_assignment_criteria_t; 5950 5951 #ifndef BCM_HIDE_DISPATCHABLE 5952 5953 /* Add a GPORT ID for the specified physical port. */ 5954 extern int bcm_port_gport_add( 5955 int unit, 5956 bcm_port_t local_port, 5957 bcm_gport_t modport); 5958 5959 /* Del the GPORT ID for the specified physical port. */ 5960 extern int bcm_port_gport_delete( 5961 int unit, 5962 bcm_port_t local_port, 5963 bcm_gport_t modport); 5964 5965 /* Delete all the GPORT IDs for the specified physical port. */ 5966 extern int bcm_port_gport_delete_all( 5967 int unit, 5968 bcm_port_t local_port); 5969 5970 /* Get all the GPORT ID for the specified physical port. */ 5971 extern int bcm_port_gport_get_all( 5972 int unit, 5973 bcm_port_t local_port, 5974 int size, 5975 bcm_gport_t *gport_array, 5976 int *count); 5977 5978 /* Configure/retrieve additional data for a wide LIF. */ 5979 extern int bcm_port_wide_data_set( 5980 int unit, 5981 bcm_gport_t gport, 5982 uint32 flags, 5983 uint64 data); 5984 5985 /* Configure/retrieve additional data for a wide LIF. */ 5986 extern int bcm_port_wide_data_get( 5987 int unit, 5988 bcm_gport_t gport, 5989 uint32 flags, 5990 uint64 *data); 5991 5992 /* Get local Encap id (local LIF id) per Gport (Global LIF id) */ 5993 extern int bcm_port_encap_local_get( 5994 int unit, 5995 bcm_gport_t gport, 5996 uint32 flags, 5997 int *encap_local_id); 5998 5999 #endif /* BCM_HIDE_DISPATCHABLE */ 6000 6001 /* Port wide data set/get flags. */ 6002 #define BCM_PORT_WIDE_DATA_INGRESS 0x1 /* If set, wide data related to 6003 ingress port (lif) extension. */ 6004 #define BCM_PORT_WIDE_DATA_EGRESS 0x2 /* If set, wide data related to 6005 egress port (lif) extension. */ 6006 6007 /* Port encap local id get flags. */ 6008 #define BCM_PORT_ENCAP_LOCAL_INGRESS 0x1 /* If set, encap local id 6009 related to ingress port 6010 (lif). */ 6011 #define BCM_PORT_ENCAP_LOCAL_EGRESS 0x2 /* If set, encap local id 6012 related to egress port 6013 (lif). */ 6014 6015 /* serdes channel supported */ 6016 typedef enum bcm_port_phy_channel_e { 6017 bcmPortPhyChannelShort = _SHR_PORT_PHY_CHANNEL_SHORT, /* short channel */ 6018 bcmPortPhyChannelLong = _SHR_PORT_PHY_CHANNEL_LONG, /* long channel */ 6019 bcmPortPhyChannelAll = _SHR_PORT_PHY_CHANNEL_ALL, /* this is only used by 6020 bcm_port_apeed_ability_local_get */ 6021 bcmPortPhyChannelCount = _SHR_PORT_PHY_CHANNEL_COUNT /* channel count */ 6022 } bcm_port_phy_channel_t; 6023 6024 /* serdes pause supported */ 6025 typedef enum bcm_port_phy_pause_e { 6026 bcmPortPhyPauseNone = _SHR_PORT_PHY_PAUSE_NONE, /* no pause */ 6027 bcmPortPhyPauseTx = _SHR_PORT_PHY_PAUSE_TX, /* tx pause */ 6028 bcmPortPhyPauseRx = _SHR_PORT_PHY_PAUSE_RX, /* rx pause */ 6029 bcmPortPhyPauseSymm = _SHR_PORT_PHY_PAUSE_SYMM, /* Symm pause type */ 6030 bcmPortPhyPauseALL = _SHR_PORT_PHY_PAUSE_ALL, /* this type is used only by 6031 bcm_port_speed_ability_local get */ 6032 bcmPortPhyPauseCount = _SHR_PORT_PHY_PAUSE_COUNT /* pause types count */ 6033 } bcm_port_phy_pause_t; 6034 6035 /* antoneg mode supported */ 6036 typedef enum bcm_port_autoneg_mode_e { 6037 bcmPortAnModeCL37 = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37, /* cl37 autoneg mode */ 6038 bcmPortAnModeCL37BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM, /* CL37 BAM mode */ 6039 bcmPortAnModeCL73 = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73, /* CL73 an mode */ 6040 bcmPortAnModeCL73BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM, /* CL73 BAM an mode */ 6041 bcmPortAnModeCL37_CL73 = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73, /* autoneg CL37 and CL73 */ 6042 bcmPortAnModeCL37_CL73BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73_BAM, /* autoneg CL37 and CL73BAM */ 6043 bcmPortAnModeCL37BAM_CL73BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73_BAM, /* autoneg CL37BAM and CL73BAM */ 6044 bcmPortAnModeCL73MSA = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_MSA, /* autoneg cl73 msa mode */ 6045 bcmPortAnModeNone = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_NONE, /* this is only used by 6046 bcm_port_apeed_ability_local_get for 6047 forced speed */ 6048 bcmPortAnModeCount = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_COUNT /* an mode count */ 6049 } bcm_port_autoneg_mode_t; 6050 6051 /* FEC types supported */ 6052 typedef enum bcm_port_phy_fec_e { 6053 bcmPortPhyFecDefaultRequest = _SHR_PORT_PHY_FEC_DEFAULT_REQUEST, /* Set this value to request default 6054 fec_type when calling 6055 bcm_port_resource_default_get */ 6056 bcmPortPhyFecInvalid = _SHR_PORT_PHY_FEC_INVALID, /* invalid */ 6057 bcmPortPhyFecNone = _SHR_PORT_PHY_FEC_NONE, /* no fec */ 6058 bcmPortPhyFecBaseR = _SHR_PORT_PHY_FEC_BASE_R, /* CL74/Base-R. 64/66b KR FEC for fabric */ 6059 bcmPortPhyFecRsFec = _SHR_PORT_PHY_FEC_RS_FEC, /* CL91/RS-FEC */ 6060 bcmPortPhyFecRs544 = _SHR_PORT_PHY_FEC_RS_544, /* Rs544, using 1xN RS FEC architecture */ 6061 bcmPortPhyFecRs272 = _SHR_PORT_PHY_FEC_RS_272, /* Rs272, using 1xN RS FEC architecture */ 6062 bcmPortPhyFecRs206 = _SHR_PORT_PHY_FEC_RS_206, /* Rs206. 64/66b 5T RS FEC for fabric */ 6063 bcmPortPhyFecRs108 = _SHR_PORT_PHY_FEC_RS_108, /* Rs108. 64/66b 5T low latency RS FEC 6064 for fabric */ 6065 bcmPortPhyFecRs545 = _SHR_PORT_PHY_FEC_RS_545, /* Rs545. 64/66b 15T RS FEC for fabric */ 6066 bcmPortPhyFecRs304 = _SHR_PORT_PHY_FEC_RS_304, /* Rs304. 64/66b 15T low latency RS FEC 6067 for fabric */ 6068 bcmPortPhyFecRs544_2xN = _SHR_PORT_PHY_FEC_RS_544_2XN, /* Rs544, using 2xN RS FEC architecture */ 6069 bcmPortPhyFecRs272_2xN = _SHR_PORT_PHY_FEC_RS_272_2XN, /* Rs272, using 2xN RS FEC architecture */ 6070 bcmPortPhyFecCount = _SHR_PORT_PHY_FEC_COUNT /* Fec type count */ 6071 } bcm_port_phy_fec_t; 6072 6073 /* Port resource flags. */ 6074 #define BCM_PORT_RESOURCE_25G_USE_50G_CALENDAR 0x1 /* If set, 25G port will 6075 use 50G calendar. */ 6076 #define BCM_PORT_RESOURCE_SPEED_ONLY 0x2 /* If set, retain port 6077 configuration for 6078 flexport operations 6079 where port mapping, 6080 lanes and encap mode 6081 are unchanged. */ 6082 #define BCM_PORT_RESOURCE_ASYMMETRICAL 0x4 /* If set, indicate the 6083 Rx and Tx resources 6084 are asymmetric. */ 6085 #define BCM_PORT_RESOURCE_TX 0x8 /* If set, only allocate 6086 TX resource. */ 6087 #define BCM_PORT_RESOURCE_CASCADED 0x10 /* If set, the port is a 6088 cascaded port. */ 6089 #define BCM_PORT_RESOURCE_TVCO_PRIORITIZE_26P562G 0x20 /* If set, prioritize 6090 using 26.562G TVCO 6091 instead of 25.781G. */ 6092 6093 /* speed_ability supported by a port */ 6094 typedef struct bcm_port_speed_ability_s { 6095 uint32 speed; /* port speed in mbps */ 6096 uint32 resolved_num_lanes; /* autoneg resolved speed num lane */ 6097 uint32 parallel_detect_en; /* parallel detect */ 6098 uint32 link_training; /* link training */ 6099 bcm_port_phy_fec_t fec_type; /* fec_type for port */ 6100 bcm_port_medium_t medium; /* medium type of a port */ 6101 bcm_port_phy_pause_t pause; /* pause */ 6102 bcm_port_phy_channel_t channel; /* short/long channel for a port */ 6103 bcm_port_autoneg_mode_t an_mode; /* autoneg mode */ 6104 } bcm_port_speed_ability_t; 6105 6106 #ifndef BCM_HIDE_DISPATCHABLE 6107 6108 /* Set or get a port advertised speed on BCM56980 */ 6109 extern int bcm_port_autoneg_ability_advert_set( 6110 int unit, 6111 bcm_port_t port, 6112 int num_ability, 6113 bcm_port_speed_ability_t *abilities_array); 6114 6115 /* Set or get a port advertised speed on BCM56980 */ 6116 extern int bcm_port_autoneg_ability_advert_get( 6117 int unit, 6118 bcm_port_t port, 6119 int max_num_ability, 6120 bcm_port_speed_ability_t *abilities_array, 6121 int *actual_num_ability); 6122 6123 /* Get a port link partner advertised speed on BCM56980 */ 6124 extern int bcm_port_autoneg_ability_remote_get( 6125 int unit, 6126 bcm_port_t port, 6127 int max_num_ability, 6128 bcm_port_speed_ability_t *abilities_array, 6129 int *actual_num_ability); 6130 6131 /* Get a local port supported speed ability on BCM56980 */ 6132 extern int bcm_port_speed_ability_local_get( 6133 int unit, 6134 bcm_port_t port, 6135 int max_num_ability, 6136 bcm_port_speed_ability_t *abilities_array, 6137 int *actual_num_ability); 6138 6139 #endif /* BCM_HIDE_DISPATCHABLE */ 6140 6141 /* Port Resource Configuration */ 6142 typedef struct bcm_port_resource_s { 6143 uint32 flags; /* BCM_PORT_RESOURCE_XXX */ 6144 bcm_gport_t port; /* Local logical port number to connect to 6145 the given physical port */ 6146 int physical_port; /* Local physical port, -1 if the logical to 6147 physical mapping is to be deleted */ 6148 int speed; /* Initial speed after FlexPort operation */ 6149 int rx_speed; /* Indicate the Rx speed, valid only 6150 BCM_PORT_RESOURCE_ASYMMETRICAL flags is 6151 set */ 6152 int lanes; /* Number of PHY lanes for this physical 6153 port */ 6154 bcm_port_encap_t encap; /* Encapsulation mode for port */ 6155 bcm_port_phy_fec_t fec_type; /* fec_type for port */ 6156 int phy_lane_config; /* serdes pmd lane config for port */ 6157 int link_training; /* link training on or off */ 6158 int roe_compression; /* enable roe_compression */ 6159 int num_subports; /* Number of subports if this is cascaded 6160 port. */ 6161 int line_card; /* Line card number for the cascaded port */ 6162 int base_flexe_instance; /* Base FlexE instance ID. "-1" means the 6163 base instance ID is allocated by SW. For 6164 50G FlexE PHY, base instance ID can be 6165 0~7; For 100G FlexE PHY, valid values are 6166 0/2/4/6; For 200G FlexE PHY, valid values 6167 are 0/4; For 400G FlexE PHY, valid value 6168 is 0 */ 6169 } bcm_port_resource_t; 6170 6171 /* Initialize a Port Resource Configuration structure. */ 6172 extern void bcm_port_resource_t_init( 6173 bcm_port_resource_t *resource); 6174 6175 #ifndef BCM_HIDE_DISPATCHABLE 6176 6177 /* 6178 * Perform a FlexPort operation changing the port resources for a given 6179 * logical port. 6180 */ 6181 extern int bcm_port_resource_set( 6182 int unit, 6183 bcm_gport_t port, 6184 bcm_port_resource_t *resource); 6185 6186 /* Get the port resource configuration. */ 6187 extern int bcm_port_resource_get( 6188 int unit, 6189 bcm_gport_t port, 6190 bcm_port_resource_t *resource); 6191 6192 #endif /* BCM_HIDE_DISPATCHABLE */ 6193 6194 #define BCM_PORT_RESOURCE_DEFAULT_REQUEST _SHR_PORT_RESOURCE_DEFAULT_REQUEST /* For 6195 bcm_port_resource_default_get 6196 - set this value to 6197 all struct members for 6198 which to get default 6199 value from the API. */ 6200 6201 #ifndef BCM_HIDE_DISPATCHABLE 6202 6203 /* 6204 * Get suggested default resource values prior to calling 6205 * bcm_port_resource_set. 6206 */ 6207 extern int bcm_port_resource_default_get( 6208 int unit, 6209 bcm_gport_t port, 6210 uint32 flags, 6211 bcm_port_resource_t *resource); 6212 6213 /* 6214 * Performs a FlexPort operation changing the port resources for a set of 6215 * ports. 6216 */ 6217 extern int bcm_port_resource_multi_set( 6218 int unit, 6219 int nport, 6220 bcm_port_resource_t *resource); 6221 6222 #endif /* BCM_HIDE_DISPATCHABLE */ 6223 6224 /* Port Resource traverse callback. */ 6225 typedef int (*bcm_port_resource_traverse_cb)( 6226 int unit, 6227 bcm_port_resource_t *resource, 6228 void *user_data); 6229 6230 #ifndef BCM_HIDE_DISPATCHABLE 6231 6232 /* 6233 * Iterate over the port resource configurations on a given unit and call 6234 * user-provided callback for every entry. 6235 */ 6236 extern int bcm_port_resource_traverse( 6237 int unit, 6238 bcm_port_resource_traverse_cb trav_fn, 6239 void *user_data); 6240 6241 /* 6242 * Validate a port's speed configuration on the BCM56980 by fetching the 6243 * affected ports. 6244 */ 6245 extern int bcm_port_resource_speed_config_validate( 6246 int unit, 6247 bcm_port_resource_t *resource, 6248 bcm_pbmp_t *pbmp); 6249 6250 /* Get/Modify the speed for a given port. */ 6251 extern int bcm_port_resource_speed_get( 6252 int unit, 6253 bcm_gport_t port, 6254 bcm_port_resource_t *resource); 6255 6256 /* Get/Modify the speed for a given port. */ 6257 extern int bcm_port_resource_speed_set( 6258 int unit, 6259 bcm_gport_t port, 6260 bcm_port_resource_t *resource); 6261 6262 /* Modify the Port Speeds for a set of ports in a single Port Macro. */ 6263 extern int bcm_port_resource_speed_multi_set( 6264 int unit, 6265 int nport, 6266 bcm_port_resource_t *resource); 6267 6268 /* Enable traffic after Fast Reboot and reconfiguration has completed */ 6269 extern int bcm_port_fast_reboot_traffic_enable( 6270 int unit); 6271 6272 /* Set the list of enabled TDM ports. */ 6273 extern int bcm_port_ingress_tdm_failover_set( 6274 int unit, 6275 int flag, 6276 bcm_pbmp_t tdm_enable_pbmp); 6277 6278 /* Get the list of enabled TDM ports. */ 6279 extern int bcm_port_ingress_tdm_failover_get( 6280 int unit, 6281 int flag, 6282 bcm_pbmp_t *tdm_enable_pbmp); 6283 6284 /* Assign/retrieve the Priority Group mapped to the input priority. */ 6285 extern int bcm_port_priority_group_mapping_set( 6286 int unit, 6287 bcm_gport_t gport, 6288 int prio, 6289 int priority_group ); 6290 6291 /* Assign/retrieve the Priority Group mapped to the input priority. */ 6292 extern int bcm_port_priority_group_mapping_get( 6293 int unit, 6294 bcm_gport_t gport, 6295 int prio, 6296 int *priority_group); 6297 6298 #endif /* BCM_HIDE_DISPATCHABLE */ 6299 6300 /* Priority Group attributes */ 6301 typedef struct bcm_port_priority_group_config_s { 6302 int shared_pool_xoff_enable; /* enable/disable of triggering PFC 6303 messages of the Priority Group when 6304 exceeds egress shared pool xoff 6305 threshold */ 6306 int shared_pool_discard_enable; /* enable/disable of dropping packets of 6307 the Priority Group when exceeds 6308 egress shared pool discard threshold */ 6309 int pfc_transmit_enable; /* enable/disable of transmitting PFC 6310 message even in IBP state */ 6311 uint16 priority_enable_vector_mask; /* Priority enable vector mask that 6312 mapped to PriorityEnableVector field 6313 in the PFC message */ 6314 } bcm_port_priority_group_config_t; 6315 6316 #ifndef BCM_HIDE_DISPATCHABLE 6317 6318 /* Set/get the port priority group configuration. */ 6319 extern int bcm_port_priority_group_config_set( 6320 int unit, 6321 bcm_gport_t gport, 6322 int priority_group, 6323 bcm_port_priority_group_config_t *prigrp_config); 6324 6325 /* Set/get the port priority group configuration. */ 6326 extern int bcm_port_priority_group_config_get( 6327 int unit, 6328 bcm_gport_t gport, 6329 int priority_group, 6330 bcm_port_priority_group_config_t *prigrp_config); 6331 6332 #endif /* BCM_HIDE_DISPATCHABLE */ 6333 6334 /* Initialize a port priority group configuration struct. */ 6335 extern void bcm_port_priority_group_config_t_init( 6336 bcm_port_priority_group_config_t *prigrp_config); 6337 6338 /* Flags for port based packet redirection. */ 6339 #define BCM_PORT_REDIRECT_TRUNCATE 0x00000001 /* If set, redirected 6340 packets will be 6341 truncated. */ 6342 #define BCM_PORT_REDIRECT_SOURCE_USE_ORIGINAL_SOURCE 0x00000002 /* If set, the original 6343 source port is used as 6344 source of redirected 6345 packets. */ 6346 #define BCM_PORT_REDIRECT_SOURCE_USE_ORIGINAL_DESTINATION 0x00000004 /* If set, the original 6347 destination port is 6348 used as source of 6349 redirected packets. */ 6350 #define BCM_PORT_REDIRECT_DROPPED_PACKET 0x00000008 /* If set, only packets 6351 dropped will be 6352 rediredcted. */ 6353 #define BCM_PORT_REDIRECT_NOT_DROPPED_PACKET 0x00000010 /* If set, only packets 6354 not dropped will be 6355 rediredcted. */ 6356 #define BCM_PORT_REDIRECT_DESTINATION_PORT 0x00000020 /* If set, the 6357 destination for 6358 redirected ports will 6359 be set as a port. */ 6360 #define BCM_PORT_REDIRECT_DESTINATION_TRUNK 0x00000040 /* If set, the 6361 destination for 6362 redirected ports will 6363 be set as a trunk. */ 6364 #define BCM_PORT_REDIRECT_DESTINATION_MCAST 0x00000080 /* If set, the 6365 destination for 6366 redirected ports will 6367 be set as a L2 6368 Multicast group. */ 6369 6370 /* Flags used to select the buffer priority for redirected packets. */ 6371 #define BCM_PORT_REDIRECT_BUFFER_PRIORITY_LOW 0x00000001 /* If set, a low buffer 6372 priority will be used 6373 for redirected 6374 packets. */ 6375 #define BCM_PORT_REDIRECT_BUFFER_PRIORITY_MEDIUM 0x00000002 /* If set, a medium 6376 buffer priority will 6377 be used for redirected 6378 packets. */ 6379 #define BCM_PORT_REDIRECT_BUFFER_PRIORITY_HIGH 0x00000004 /* If set, a high buffer 6380 priority will be used 6381 for redirected 6382 packets. */ 6383 6384 /* New redirection packet color */ 6385 typedef enum bcm_port_redirect_color_e { 6386 bcmPortRedirectColorNone = 0, 6387 bcmPortRedirectColorGreen = 1, 6388 bcmPortRedirectColorYellow = 2, 6389 bcmPortRedirectColorRed = 3 6390 } bcm_port_redirect_color_t; 6391 6392 /* Preemption control */ 6393 typedef enum bcm_port_preempt_control_e { 6394 bcmPortPreemptControlPreemptionSupport = 0, /* Support preemption operation. */ 6395 bcmPortPreemptControlQueueBitmap = 1, /* Specify the preemptable queue in 6396 bitmap. */ 6397 bcmPortPreemptControlEnableTx = 2, /* Enable preemption in transmit 6398 direction. */ 6399 bcmPortPreemptControlVerifyEnable = 3, /* Enable preemption verify operation. */ 6400 bcmPortPreemptControlVerifyTime = 4, /* The wait time in ms between 6401 verification attempts. */ 6402 bcmPortPreemptControlVerifyAttempts = 5, /* The number of verification attempts. */ 6403 bcmPortPreemptControlNonFinalFragSizeTx = 6, /* The minimum size (in Bytes) of 6404 non-final fragment of a packet in 6405 transmit direction. */ 6406 bcmPortPreemptControlFinalFragSizeTx = 7, /* The minimum size (in Bytes) of final 6407 fragment of a packet in transmit 6408 direction. */ 6409 bcmPortPreemptControlNonFinalFragSizeRx = 8, /* The minimum size (in Bytes) of 6410 non-final fragment of a packet in 6411 receive direction. */ 6412 bcmPortPreemptControlFinalFragSizeRx = 9, /* The minimum size (in Bytes) of final 6413 fragment of a packet in receive 6414 direction. */ 6415 bcmPortPreemptControlHoldReqCntMode = 10, /* The MMU preemption request count mode 6416 for snmpBcmMacMergeHoldCount */ 6417 bcmPortPreemptControlCount = 11 /* always the last one */ 6418 } bcm_port_preempt_control_t; 6419 6420 /* Preemption status */ 6421 typedef enum bcm_port_preempt_status_e { 6422 bcmPortPreemptStatusTx = 0, /* Preemption status in the transmit 6423 direction. */ 6424 bcmPortPreemptStatusVerify = 1 /* Preemption verify operation status . */ 6425 } bcm_port_preempt_status_t; 6426 6427 /* Preemption TX status */ 6428 typedef enum bcm_port_preempt_status_tx_e { 6429 bcmPortPreemptStatusTxInactive = 0, /* Verify is enabled but its status is 6430 either failed or not initiated. Or 6431 Preemption is not enabled. */ 6432 bcmPortPreemptStatusTxVerifying = 1, /* Preemption is enabled and proceeding 6433 the verify operation. */ 6434 bcmPortPreemptStatusTxActive = 2 /* Preemption is activated. */ 6435 } bcm_port_preempt_status_tx_t; 6436 6437 /* Preemption Verify status */ 6438 typedef enum bcm_port_preempt_status_verify_e { 6439 bcmPortPreemptStatusVerifyDisabled = 0, /* Verify operation is not enabled. */ 6440 bcmPortPreemptStatusVerifyInitial = 1, /* Verify operation is enabled but the 6441 not started yet. */ 6442 bcmPortPreemptStatusVerifyInProgress = 2, /* Verify operation is in progress. */ 6443 bcmPortPreemptStatusVerifySucceeded = 3, /* Verify operation is succeeded. */ 6444 bcmPortPreemptStatusVerifyFailed = 4 /* Verify operation is failed. */ 6445 } bcm_port_preempt_status_verify_t; 6446 6447 /* Port redirection attributes */ 6448 typedef struct bcm_port_redirect_config_s { 6449 int flags; /* Flags to pass with configuration data */ 6450 int strength; /* Strength of the entry */ 6451 int buffer_priority; /* Buffering priority of the redirected 6452 packet */ 6453 int destination; /* Destination of the redirected packets */ 6454 int priority; /* Priority to be assigned for 6455 redirected packets */ 6456 bcm_port_redirect_color_t color; /* Color to be assigned to redirected 6457 packets */ 6458 } bcm_port_redirect_config_t; 6459 6460 /* Initialize a port redirection structure. */ 6461 extern void bcm_port_redirect_config_t_init( 6462 bcm_port_redirect_config_t *redirect_config); 6463 6464 #ifndef BCM_HIDE_DISPATCHABLE 6465 6466 /* Configure/retrieve port redirection data */ 6467 extern int bcm_port_redirect_config_set( 6468 int unit, 6469 bcm_gport_t port, 6470 bcm_port_redirect_config_t *redirect_config); 6471 6472 /* Configure/retrieve port redirection data */ 6473 extern int bcm_port_redirect_config_get( 6474 int unit, 6475 bcm_gport_t gport, 6476 bcm_port_redirect_config_t *redirect_config); 6477 6478 #endif /* BCM_HIDE_DISPATCHABLE */ 6479 6480 /* Port redirection attributes */ 6481 typedef struct bcm_port_nif_prio_s { 6482 int priority_level; /* NIF Priority level to set/get */ 6483 } bcm_port_nif_prio_t; 6484 6485 #ifndef BCM_HIDE_DISPATCHABLE 6486 6487 /* Set/Get port NIF priority. */ 6488 extern int bcm_port_nif_priority_set( 6489 int unit, 6490 bcm_gport_t local_port, 6491 uint32 flags, 6492 bcm_port_nif_prio_t *priority, 6493 bcm_pbmp_t *affected_ports); 6494 6495 /* Set/Get port NIF priority. */ 6496 extern int bcm_port_nif_priority_get( 6497 int unit, 6498 bcm_gport_t local_port, 6499 uint32 flags, 6500 bcm_port_nif_prio_t *priority, 6501 bcm_pbmp_t *affected_ports); 6502 6503 /* Get or set various configurations for Preemption */ 6504 extern int bcm_port_preemption_control_set( 6505 int unit, 6506 bcm_gport_t gport, 6507 bcm_port_preempt_control_t type, 6508 uint32 arg); 6509 6510 /* Get or set various configurations for Preemption */ 6511 extern int bcm_port_preemption_control_get( 6512 int unit, 6513 bcm_gport_t gport, 6514 bcm_port_preempt_control_t type, 6515 uint32 *arg); 6516 6517 /* Get the specified preemption status */ 6518 extern int bcm_port_preemption_status_get( 6519 int unit, 6520 bcm_gport_t gport, 6521 bcm_port_preempt_status_t type, 6522 uint32 *status); 6523 6524 #endif /* BCM_HIDE_DISPATCHABLE */ 6525 6526 /* E2EFC modes */ 6527 typedef enum bcm_port_e2efc_mode_e { 6528 bcmPortE2efcModeTx = 0, /* E2EFC frame transmit mode */ 6529 bcmPortE2efcModeRx = 1, /* E2EFC frame receive mode */ 6530 bcmPortE2efcModeCount = 2 /* Must be last. Not a usable value */ 6531 } bcm_port_e2efc_mode_t; 6532 6533 /* Configuration of remote module */ 6534 typedef struct bcm_port_e2efc_remote_module_config_s { 6535 bcm_gport_t local_port; /* Local port for E2EFC message transaction, only 6536 for E2EFC TX */ 6537 int pkt_per_second; /* Frequency of sending E2EFC messages, only for 6538 E2EFC TX */ 6539 } bcm_port_e2efc_remote_module_config_t; 6540 6541 /* Initialize a bcm_port_e2efc_remote_module_config_t structure. */ 6542 extern void bcm_port_e2efc_remote_module_config_t_init( 6543 bcm_port_e2efc_remote_module_config_t *e2efc_rmod_cfg); 6544 6545 #ifndef BCM_HIDE_DISPATCHABLE 6546 6547 /* Set/get the remote module that applies E2EFC mechanism. */ 6548 extern int bcm_port_e2efc_remote_module_enable_set( 6549 int unit, 6550 bcm_module_t remote_module, 6551 bcm_port_e2efc_mode_t mode, 6552 int enable, 6553 bcm_port_e2efc_remote_module_config_t *e2efc_rmod_cfg); 6554 6555 /* Set/get the remote module that applies E2EFC mechanism. */ 6556 extern int bcm_port_e2efc_remote_module_enable_get( 6557 int unit, 6558 bcm_module_t remote_module, 6559 bcm_port_e2efc_mode_t mode, 6560 int *enable, 6561 bcm_port_e2efc_remote_module_config_t *e2efc_rmod_cfg); 6562 6563 #endif /* BCM_HIDE_DISPATCHABLE */ 6564 6565 /* bcm_port_e2efc_remote_module_traverse_cb */ 6566 typedef int (*bcm_port_e2efc_remote_module_traverse_cb)( 6567 int unit, 6568 bcm_module_t remote_module, 6569 bcm_port_e2efc_mode_t mode, 6570 void *user_data); 6571 6572 #ifndef BCM_HIDE_DISPATCHABLE 6573 6574 /* 6575 * Iterate over the E2EFC remote module configuration on a given unit and 6576 * call user-provided callback for every entry. 6577 */ 6578 extern int bcm_port_e2efc_remote_module_traverse( 6579 int unit, 6580 bcm_port_e2efc_remote_module_traverse_cb cb, 6581 void *user_data); 6582 6583 #endif /* BCM_HIDE_DISPATCHABLE */ 6584 6585 /* 6586 * Resource type would be used to configure set, reset and discard 6587 * thresholds 6588 */ 6589 typedef enum bcm_port_e2efc_resource_type_e { 6590 BCM_E2EFC_RESOURCE_TYPE_NONE = 0, /* Resource type not needed */ 6591 BCM_E2EFC_RESOURCE_TYPE_INT_MEM = 1, /* Resource type internal Memory 6592 configured in number of bytes */ 6593 BCM_E2EFC_RESOURCE_TYPE_QEN = 2, /* Resource type queue entries 6594 configured in number of packets */ 6595 BCM_E2EFC_RESOURCE_TYPE_RQE = 3, /* Resource type replication queue 6596 engine entries configured in number 6597 of packets */ 6598 BCM_E2EFC_RESOURCE_TYPE_EXT_MEM = 4, /* Resource type external Memory 6599 configured in number of bytes */ 6600 BCM_E2EFC_RESOURCE_TYPE_EMA = 5, /* Resource type external Memory access 6601 configured in number of bytes */ 6602 BCM_E2EFC_RESOURCE_TYPE_COUNT = 6 /* Number of E2EFC Resource type */ 6603 } bcm_port_e2efc_resource_type_t; 6604 6605 /* Configuration for remote port */ 6606 typedef struct bcm_port_e2efc_remote_port_config_s { 6607 bcm_module_t remote_module; /* Remote module id that E2EFC applied */ 6608 bcm_port_t remote_port; /* Remote port id to be configured */ 6609 int xoff_threshold_bytes; /* Assert backpressure when number of 6610 buffers used is at or above this 6611 threshold in bytes */ 6612 int xoff_threshold_packets; /* Assert backpressure when number of 6613 buffers used is at or above this 6614 threshold in packets */ 6615 int xon_threshold_bytes; /* Remove backpressure when number of 6616 buffers used drop below this 6617 threshold in bytes */ 6618 int xon_threshold_packets; /* Remove backpressure when number of 6619 buffers used drop below this 6620 threshold in packets */ 6621 int drop_threshold_bytes; /* Drop packets when number of buffers 6622 used hit this threshold in bytes */ 6623 int drop_threshold_packets; /* Drop packets when number of buffers 6624 used hit this threshold in packets */ 6625 bcm_port_e2efc_resource_type_t e2efc_resource_type; /* Type of resource being 6626 configured.Internal Memory, External 6627 Memory and EMA shall be configured in 6628 terms of bytes and Queue entry and 6629 RQE shall be configured in terms of 6630 packets */ 6631 } bcm_port_e2efc_remote_port_config_t; 6632 6633 /* Initialize a bcm_port_e2efc_remote_port_config_t structure. */ 6634 extern void bcm_port_e2efc_remote_port_config_t_init( 6635 bcm_port_e2efc_remote_port_config_t *e2efc_rport_cfg); 6636 6637 #ifndef BCM_HIDE_DISPATCHABLE 6638 6639 /* Add remote module-port and set configuration. */ 6640 extern int bcm_port_e2efc_remote_port_add( 6641 int unit, 6642 bcm_port_e2efc_remote_port_config_t *e2efc_rport_cfg, 6643 int *rport_handle_id); 6644 6645 /* Set/get the configuration of the remote port. */ 6646 extern int bcm_port_e2efc_remote_port_set( 6647 int unit, 6648 int rport_handle_id, 6649 bcm_port_e2efc_remote_port_config_t *e2efc_rport_cfg); 6650 6651 /* Set/get the configuration of the remote port. */ 6652 extern int bcm_port_e2efc_remote_port_get( 6653 int unit, 6654 int rport_handle_id, 6655 bcm_port_e2efc_remote_port_config_t *e2efc_rport_cfg); 6656 6657 /* Delete remote port. */ 6658 extern int bcm_port_e2efc_remote_port_delete( 6659 int unit, 6660 int rport_handle_id); 6661 6662 #endif /* BCM_HIDE_DISPATCHABLE */ 6663 6664 /* bcm_port_e2efc_remote_port_traverse_cb */ 6665 typedef int (*bcm_port_e2efc_remote_port_traverse_cb)( 6666 int unit, 6667 int rport_handle_id, 6668 void *user_data); 6669 6670 #ifndef BCM_HIDE_DISPATCHABLE 6671 6672 /* 6673 * Iterate over the E2EFC remote port configuration on a given unit and 6674 * call user-provided callback for every entry. 6675 */ 6676 extern int bcm_port_e2efc_remote_port_traverse( 6677 int unit, 6678 bcm_port_e2efc_remote_port_traverse_cb cb, 6679 void *user_data); 6680 6681 #endif /* BCM_HIDE_DISPATCHABLE */ 6682 6683 /* bcm_port_timesync_tx_info */ 6684 typedef struct bcm_port_timesync_tx_info_s { 6685 uint64 timestamp; /* transmit timestamp of ptp packet */ 6686 uint32 sequence_id; /* sequence id of transmitted ptp packet */ 6687 uint32 sub_ns; /* timestamp sub-nanosecond */ 6688 } bcm_port_timesync_tx_info_t; 6689 6690 #ifndef BCM_HIDE_DISPATCHABLE 6691 6692 /* Get 1588 packet's transmit information form the port. */ 6693 extern int bcm_port_timesync_tx_info_get( 6694 int unit, 6695 bcm_port_t port, 6696 bcm_port_timesync_tx_info_t *tx_info); 6697 6698 #endif /* BCM_HIDE_DISPATCHABLE */ 6699 6700 /* Timestamp adjust */ 6701 typedef _shr_port_timestamp_adjust_t bcm_port_timestamp_adjust_t; 6702 6703 #ifndef BCM_HIDE_DISPATCHABLE 6704 6705 /* Get or set timestamp OSTS/TSTS adjust. */ 6706 extern int bcm_port_timestamp_adjust_get( 6707 int unit, 6708 bcm_port_t port, 6709 bcm_port_timestamp_adjust_t *ts_adjust); 6710 6711 /* Get or set timestamp OSTS/TSTS adjust. */ 6712 extern int bcm_port_timestamp_adjust_set( 6713 int unit, 6714 bcm_port_t port, 6715 bcm_port_timestamp_adjust_t *ts_adjust); 6716 6717 #endif /* BCM_HIDE_DISPATCHABLE */ 6718 6719 /* Port max priority groups. */ 6720 #define BCM_PORT_MAX_NOF_PRIORITY_GROUPS 3 6721 6722 /* Port priority */ 6723 #define BCM_PORT_F_PRIORITY_0 (1<<1) /* User defined priority 0. */ 6724 #define BCM_PORT_F_PRIORITY_1 (1<<2) /* User defined priority 1. */ 6725 #define BCM_PORT_F_PRIORITY_2 (1<<3) /* User defined priority 2. */ 6726 #define BCM_PORT_F_PRIORITY_3 (1<<4) /* User defined priority 3. */ 6727 #define BCM_PORT_F_PRIORITY_TDM (1<<16) /* User defined priority TDM */ 6728 6729 /* Priority Scheduler. */ 6730 typedef enum bcm_port_nif_scheduler_e { 6731 bcmPortNifSchedulerLow = 0, /* Low Priority Scheduler */ 6732 bcmPortNifSchedulerHigh = 1, /* High Priority Scheduler */ 6733 bcmPortNifSchedulerTDM = 2 /* TDM Priority Scheduler */ 6734 } bcm_port_nif_scheduler_t; 6735 6736 /* bcm_port_prio_group_config_t */ 6737 typedef struct bcm_port_prio_group_config_s { 6738 uint32 source_priority; /* see BCM_PORT_F_PRIORITY_* */ 6739 bcm_port_nif_scheduler_t sch_priority; /* see bcm_port_nif_scheduler_t */ 6740 int num_of_entries; /* Indicate how many memory entries each 6741 priority group takes. Set to -1 for 6742 equal division between all 6743 priorities; otherwise indicate number 6744 of entries up to 128 per lane */ 6745 } bcm_port_prio_group_config_t; 6746 6747 /* bcm_port_prio_config_t */ 6748 typedef struct bcm_port_prio_config_s { 6749 int nof_priority_groups; /* see BCM_PORT_F_PRIORITY */ 6750 bcm_port_prio_group_config_t priority_groups[BCM_PORT_MAX_NOF_PRIORITY_GROUPS]; 6751 } bcm_port_prio_config_t; 6752 6753 #ifndef BCM_HIDE_DISPATCHABLE 6754 6755 /* 6756 * Configure priority groups for the port. Priority group is meant to 6757 * connect one or more user priorities (see BCM_PORT_F_PRIORITY_*) to a 6758 * scheduler priority (High, Low, TDM) Each priority group acts as a 6759 * logical FIFO. The size of the FIFO can be dynamically specified, in 6760 * entries. 6761 */ 6762 extern int bcm_port_priority_config_set( 6763 int unit, 6764 bcm_port_t port, 6765 bcm_port_prio_config_t *port_priority_config); 6766 6767 /* Retrieve the port priority group configuration. */ 6768 extern int bcm_port_priority_config_get( 6769 int unit, 6770 bcm_port_t port, 6771 bcm_port_prio_config_t *priority_config); 6772 6773 #endif /* BCM_HIDE_DISPATCHABLE */ 6774 6775 #define BCM_PORT_LANE_TO_SERDES_NOT_MAPPED -1 /* A lane is unmapped for 6776 both Tx and Rx. 6777 Unmapped lanes can't 6778 be assigned to a port. */ 6779 6780 /* 6781 * This struct holds serdes information (rx and tx) related to a specific 6782 * lane. 6783 */ 6784 typedef struct bcm_port_lane_to_serdes_map_s { 6785 int serdes_rx_id; 6786 int serdes_tx_id; 6787 } bcm_port_lane_to_serdes_map_t; 6788 6789 #ifndef BCM_HIDE_DISPATCHABLE 6790 6791 /* Map lanes to serdeses. */ 6792 extern int bcm_port_lane_to_serdes_map_set( 6793 int unit, 6794 int flags, 6795 int map_size, 6796 bcm_port_lane_to_serdes_map_t *serdes_map); 6797 6798 /* Map lanes to serdeses. */ 6799 extern int bcm_port_lane_to_serdes_map_get( 6800 int unit, 6801 int flags, 6802 int map_size, 6803 bcm_port_lane_to_serdes_map_t *serdes_map); 6804 6805 #endif /* BCM_HIDE_DISPATCHABLE */ 6806 6807 #define BCM_PORT_LANE_TO_SERDES_FABRIC_SIDE 0x1 /* Update lane to serdes 6808 mapping on fabric 6809 side. */ 6810 6811 #ifndef BCM_HIDE_DISPATCHABLE 6812 6813 /* 6814 * This API is used to configure the order of the ILKN lanes. Each index 6815 * in lanes[] array stands for ILKN lane ID. The values of lanes[] array 6816 * is the NIF/Fabric lanes mapped to ILKN logical lane. 6817 */ 6818 extern int bcm_port_ilkn_lane_map_set( 6819 int unit, 6820 int flags, 6821 bcm_port_t port, 6822 int num_of_lanes, 6823 int *lanes); 6824 6825 /* 6826 * Get the order of the ILKN lanes for ILKN ports. Each index in lanes[] 6827 * array stands for ILKN lane ID. The values of lanes[] array is the 6828 * NIF/Fabric lanes mapped to ILKN logical lane. 6829 */ 6830 extern int bcm_port_ilkn_lane_map_get( 6831 int unit, 6832 int flags, 6833 bcm_port_t port, 6834 int num_of_lanes, 6835 int *lanes); 6836 6837 #endif /* BCM_HIDE_DISPATCHABLE */ 6838 6839 /* Per port and LIF flooding destination information. */ 6840 typedef struct bcm_port_flood_group_s { 6841 bcm_gport_t unknown_unicast_group; /* Destination for unknown unicast 6842 packets. */ 6843 bcm_gport_t unknown_multicast_group; /* Destination for unknown multicast 6844 packets. */ 6845 bcm_gport_t broadcast_group; /* Destination for broadcast packets. */ 6846 } bcm_port_flood_group_t; 6847 6848 /* Initialize a port flooding group structure. */ 6849 extern void bcm_port_flood_group_t_init( 6850 bcm_port_flood_group_t *flood_groups); 6851 6852 #ifndef BCM_HIDE_DISPATCHABLE 6853 6854 /* Set/Get the flooding groups for ports or LIFs. */ 6855 extern int bcm_port_flood_group_set( 6856 int unit, 6857 bcm_gport_t port, 6858 uint32 flags, 6859 bcm_port_flood_group_t *flood_groups); 6860 6861 /* Set/Get the flooding groups for ports or LIFs. */ 6862 extern int bcm_port_flood_group_get( 6863 int unit, 6864 bcm_gport_t port, 6865 uint32 flags, 6866 bcm_port_flood_group_t *flood_groups); 6867 6868 #endif /* BCM_HIDE_DISPATCHABLE */ 6869 6870 typedef enum bcm_port_phy_tx_tap_mode_e { 6871 bcmPortPhyTxTapMode3Tap = _SHR_PORT_PHY_TX_TAP_MODE_3_TAP, 6872 bcmPortPhyTxTapMode6Tap = _SHR_PORT_PHY_TX_TAP_MODE_6_TAP 6873 } bcm_port_phy_tx_tap_mode_t; 6874 6875 typedef enum bcm_port_phy_signalling_mode_e { 6876 bcmPortPhySignallingModeNRZ = _SHR_PORT_PHY_SIGNALLING_MODE_NRZ, 6877 bcmPortPhySignallingModePAM4 = _SHR_PORT_PHY_SIGNALLING_MODE_PAM4 6878 } bcm_port_phy_signalling_mode_t; 6879 6880 typedef struct bcm_port_phy_tx_s { 6881 int pre2; 6882 int pre; 6883 int main; 6884 int post; 6885 int post2; 6886 int post3; 6887 int amp; 6888 int drv_mode; 6889 bcm_port_phy_tx_tap_mode_t tx_tap_mode; 6890 bcm_port_phy_signalling_mode_t signalling_mode; 6891 } bcm_port_phy_tx_t; 6892 6893 /* Initialize the bcm_port_phy_tx_t structure. */ 6894 extern void bcm_port_phy_tx_t_init( 6895 bcm_port_phy_tx_t *tx); 6896 6897 #ifndef BCM_HIDE_DISPATCHABLE 6898 6899 /* Modify TX FIR parameters for a given port */ 6900 extern int bcm_port_phy_tx_set( 6901 int unit, 6902 bcm_port_t port, 6903 bcm_port_phy_tx_t *tx); 6904 6905 /* Get TX FIR parameters for a given port */ 6906 extern int bcm_port_phy_tx_get( 6907 int unit, 6908 bcm_port_t port, 6909 bcm_port_phy_tx_t *tx); 6910 6911 #endif /* BCM_HIDE_DISPATCHABLE */ 6912 6913 typedef struct bcm_port_rlm_config_s { 6914 int is_initiator; 6915 uint32 active_lane_bit_map; /* input only valid for initator */ 6916 } bcm_port_rlm_config_t; 6917 6918 /* Initialize a Port Reduced Lane Mode Configuration structure. */ 6919 extern void bcm_port_rlm_config_t_init( 6920 bcm_port_rlm_config_t *rlm_config); 6921 6922 #ifndef BCM_HIDE_DISPATCHABLE 6923 6924 /* Set and get the configuration for Reduced Lane Mode (RLM) on a port. */ 6925 extern int bcm_port_rlm_config_set( 6926 int unit, 6927 bcm_port_t port, 6928 bcm_port_rlm_config_t *rlm_config, 6929 int enable); 6930 6931 /* Set and get the configuration for Reduced Lane Mode (RLM) on a port. */ 6932 extern int bcm_port_rlm_config_get( 6933 int unit, 6934 bcm_port_t port, 6935 bcm_port_rlm_config_t *rlm_config, 6936 int *enable); 6937 6938 #endif /* BCM_HIDE_DISPATCHABLE */ 6939 6940 typedef enum bcm_port_rlm_status_e { 6941 bcmPortRlmDisabled = _SHR_PORT_RLM_DISABLED, 6942 bcmPortRlmBusy = _SHR_PORT_RLM_BUSY, 6943 bcmPortRlmDone = _SHR_PORT_RLM_DONE, 6944 bcmPortRlmFailed = _SHR_PORT_RLM_FAILED, 6945 bcmPortRlmCount = _SHR_PORT_RLM_COUNT 6946 } bcm_port_rlm_status_t; 6947 6948 #ifndef BCM_HIDE_DISPATCHABLE 6949 6950 /* Check the Reduced Lane Mode (RLM) status of a port */ 6951 extern int bcm_port_rlm_status_get( 6952 int unit, 6953 bcm_port_t port, 6954 bcm_port_rlm_status_t *rlm_status); 6955 6956 #endif /* BCM_HIDE_DISPATCHABLE */ 6957 6958 /* FlexE PHY info structure. */ 6959 typedef struct bcm_port_flexe_group_phy_info_s { 6960 bcm_port_t port; /* Logical port ID for FlexE physical port */ 6961 int logical_phy_id; /* Logical PHY ID for FlexE PHY */ 6962 } bcm_port_flexe_group_phy_info_t; 6963 6964 #ifndef BCM_HIDE_DISPATCHABLE 6965 6966 /* Create an FlexE group and add related PHYs. */ 6967 extern int bcm_port_flexe_group_create( 6968 int unit, 6969 bcm_gport_t gport, 6970 uint32 flags, 6971 int nof_pcs, 6972 bcm_port_flexe_group_phy_info_t *phy_info); 6973 6974 /* Get FlexE group info. */ 6975 extern int bcm_port_flexe_group_get( 6976 int unit, 6977 bcm_gport_t gport, 6978 uint32 flags, 6979 int max_nof_pcs, 6980 bcm_port_flexe_group_phy_info_t *phy_info, 6981 int *actual_nof_pcs); 6982 6983 /* Add one FlexE physical port into one group. */ 6984 extern int bcm_port_flexe_group_phy_add( 6985 int unit, 6986 bcm_gport_t gport, 6987 uint32 flags, 6988 bcm_port_flexe_group_phy_info_t *phy_info); 6989 6990 /* Remove one FlexE physical port from one group. */ 6991 extern int bcm_port_flexe_group_phy_remove( 6992 int unit, 6993 bcm_gport_t gport, 6994 uint32 flags, 6995 bcm_port_flexe_group_phy_info_t *phy_info); 6996 6997 /* Destroy one FlexE group. */ 6998 extern int bcm_port_flexe_group_destroy( 6999 int unit, 7000 bcm_gport_t gport); 7001 7002 #endif /* BCM_HIDE_DISPATCHABLE */ 7003 7004 /* FlexE calendar types. */ 7005 typedef enum bcm_port_flexe_group_cal_e { 7006 bcmPortFlexeGroupCalA = 0, /* FlexE calendar A */ 7007 bcmPortFlexeGroupCalB = 1, /* FlexE calendar B */ 7008 bcmPortFlexeGroupCalCount = 2 /* FlexE calendar count */ 7009 } bcm_port_flexe_group_cal_t; 7010 7011 /* Port FlexE flags. */ 7012 #define BCM_PORT_FLEXE_RX 0x1 /* Indicate it is for FlexE RX 7013 direction only */ 7014 #define BCM_PORT_FLEXE_TX 0x2 /* Indicate it is for FlexE TX 7015 direction only */ 7016 #define BCM_PORT_FLEXE_OVERHEAD 0x4 /* Indicate it is for FlexE overhead 7017 only */ 7018 #define BCM_PORT_FLEXE_BYPASS 0x8 /* Indicate some FlexE logics are 7019 bypassed in FlexE core, such as 7020 demux */ 7021 7022 #ifndef BCM_HIDE_DISPATCHABLE 7023 7024 /* FlexE group calendar slots configuration. */ 7025 extern int bcm_port_flexe_group_cal_slots_set( 7026 int unit, 7027 bcm_gport_t gport, 7028 uint32 flags, 7029 bcm_port_flexe_group_cal_t calendar_id, 7030 int nof_slots, 7031 int *calendar_slots); 7032 7033 /* GET FlexE group calendar slots configuration. */ 7034 extern int bcm_port_flexe_group_cal_slots_get( 7035 int unit, 7036 bcm_gport_t gport, 7037 uint32 flags, 7038 bcm_port_flexe_group_cal_t calendar_id, 7039 int max_nof_slots, 7040 int *calendar_slots, 7041 int *actual_nof_slots); 7042 7043 /* Set the active calendar in FlexE Mux/Demux. */ 7044 extern int bcm_port_flexe_group_cal_active_set( 7045 int unit, 7046 bcm_gport_t gport, 7047 uint32 flags, 7048 bcm_port_flexe_group_cal_t active_cal); 7049 7050 /* Get the active calendar in FlexE Mux/Demux. */ 7051 extern int bcm_port_flexe_group_cal_active_get( 7052 int unit, 7053 bcm_gport_t gport, 7054 uint32 flags, 7055 bcm_port_flexe_group_cal_t *active_cal); 7056 7057 #endif /* BCM_HIDE_DISPATCHABLE */ 7058 7059 /* FlexE Overhead types. */ 7060 typedef enum bcm_port_flexe_oh_type_e { 7061 bcmPortFlexeOhGroupID = 0, /* Group ID in FlexE overhead */ 7062 bcmPortFlexeOhLogicalPhyID = 1, /* Logical PHY ID in FlexE overhead */ 7063 bcmPortFlexeOhCalInUse = 2, /* Calendar in use bit in FlexE overhead */ 7064 bcmPortFlexeOhCalRequest = 3, /* Calendar request bit in FlexE overhead */ 7065 bcmPortFlexeOhCalAck = 4, /* Calendar ack bit in FlexE overhead */ 7066 bcmPortFlexeOhSyncConfig = 5, /* Synchronization configuration bit in 7067 FlexE overhead */ 7068 bcmPortFlexeOhCount = 6 /* Number of overhead types */ 7069 } bcm_port_flexe_oh_type_t; 7070 7071 #ifndef BCM_HIDE_DISPATCHABLE 7072 7073 /* Configure the overhead according to the overhead type. */ 7074 extern int bcm_port_flexe_oh_set( 7075 int unit, 7076 bcm_gport_t gport, 7077 uint32 flags, 7078 bcm_port_flexe_oh_type_t type, 7079 int val); 7080 7081 /* Get the overhead according to the overhead type. */ 7082 extern int bcm_port_flexe_oh_get( 7083 int unit, 7084 bcm_gport_t gport, 7085 uint32 flags, 7086 bcm_port_flexe_oh_type_t type, 7087 int *val); 7088 7089 /* Configure FlexE traffic flow for single direction. */ 7090 extern int bcm_port_flexe_flow_set( 7091 int unit, 7092 uint32 flags, 7093 bcm_port_t src_port, 7094 int channel, 7095 bcm_port_t dest_port); 7096 7097 /* Clear FlexE traffic flow for single direction. */ 7098 extern int bcm_port_flexe_flow_clear( 7099 int unit, 7100 bcm_port_t src_port, 7101 int channel, 7102 bcm_port_t dest_port); 7103 7104 #endif /* BCM_HIDE_DISPATCHABLE */ 7105 7106 /* FlexE PHY info structure. */ 7107 typedef struct bcm_port_flexe_oh_alarm_s { 7108 uint8 alarm_active; /* Indicate if there is active alarm */ 7109 uint8 phymap_mismatch; /* Phymap mismatch alarm */ 7110 bcm_port_flexe_time_slot_t cal_a_mismatch; /* The client ID in calendar A mismatch, 7111 return value is time slots */ 7112 bcm_port_flexe_time_slot_t cal_b_mismatch; /* The client ID in calendar B mismatch, 7113 return value is time slots */ 7114 uint8 group_deskew_alarm; /* FlexE group deskew alarm */ 7115 uint8 group_id_mismatch; /* Group ID mismatch alarm */ 7116 uint8 phy_id_mismatch; /* Phy ID mismatch alarm */ 7117 uint8 lost_of_frame; /* This alarm will be raised if out of 7118 frame status lasts for a certain time */ 7119 uint8 lost_of_multiframe; /* This alarm will be raised if out of 7120 multiframe status lasts for a certain 7121 time */ 7122 uint8 oh_block_1_alarm; /* Error happens in the first overhead 7123 block */ 7124 uint8 c_bit_alarm; /* The alarm for C bit in overhead */ 7125 uint8 crc_error; /* There is CRC16 error in overhead */ 7126 uint8 rpf_alarm; /* RPF alarm in overhead */ 7127 uint8 sc_mismatch; /* Sync config mismatch alarm in 7128 overhead */ 7129 } bcm_port_flexe_oh_alarm_t; 7130 7131 #ifndef BCM_HIDE_DISPATCHABLE 7132 7133 /* Get overhead alarms. */ 7134 extern int bcm_port_flexe_oh_alarm_get( 7135 int unit, 7136 bcm_gport_t gport, 7137 uint32 flags, 7138 bcm_port_flexe_oh_alarm_t *alarms); 7139 7140 #endif /* BCM_HIDE_DISPATCHABLE */ 7141 7142 /* FlexE PHY info structure. */ 7143 typedef struct bcm_port_flexe_oam_alarm_s { 7144 uint8 alarm_active; /* Indicate if there is active alarm */ 7145 uint8 rx_base_csf_lpi; /* Rx base OAM client signal LPI fault alarm */ 7146 uint8 rx_base_cs_lf; /* Rx base OAM client signal Local Fault 7147 alarm */ 7148 uint8 rx_base_cs_rf; /* Rx base OAM client signal Remote Fault 7149 alarm */ 7150 uint8 base_oam_los; /* Base OAM no receive alarm */ 7151 uint8 rx_sdbip; /* Rx SDBIP alarm */ 7152 uint8 rx_base_crc; /* Rx OAM base CRC error alarm */ 7153 uint8 rx_base_rdi; /* Rx OAM base RDI alarm */ 7154 uint8 rx_base_period_mismatch; /* Rx base OAM period mismatch alarm */ 7155 uint8 local_fault; /* Local fault alarm in Rx direction */ 7156 uint8 remote_fault; /* Remote fault alarm in Rx direction */ 7157 uint8 sdrei; /* Signal defect REI alarm */ 7158 uint8 sfbip; /* Signal fail BIP alarm */ 7159 uint8 sfrei; /* Signal fail REI alarm */ 7160 } bcm_port_flexe_oam_alarm_t; 7161 7162 #ifndef BCM_HIDE_DISPATCHABLE 7163 7164 /* Get OAM alarms. */ 7165 extern int bcm_port_flexe_oam_alarm_get( 7166 int unit, 7167 bcm_port_t port, 7168 uint32 flags, 7169 bcm_port_flexe_oam_alarm_t *alarms); 7170 7171 #endif /* BCM_HIDE_DISPATCHABLE */ 7172 7173 /* FlexE OAM control type */ 7174 typedef enum bcm_port_flexe_oam_control_type_e { 7175 bcmPortFlexeOamControlRxBasePeriod = 0, /* Rx OAM base period */ 7176 bcmPortFlexeOamControlTxBasePeriod = 1, /* Tx OAM base period */ 7177 bcmPortFlexeOamControlTxBaseEnable = 2, /* Enable the Tx base OAM */ 7178 bcmPortFlexeOamControlRxBypassEnable = 3, /* Enable Rx OAM bypass */ 7179 bcmPortFlexeOamControlTxBypassEnable = 4, /* Enable Tx OAM bypass */ 7180 bcmPortFlexeOamControlInsertLocalFault = 5, /* Insert local fault to client signal */ 7181 bcmPortFlexeOamControlInsertRemoteFault = 6, /* Insert remote fault to client signal */ 7182 bcmPortFlexeOamControlSdBip8BlockNum = 7, /* Block number for SD BIP8 checking */ 7183 bcmPortFlexeOamControlSdBip8SetThreshold = 8, /* Threshold for setting SD BIP8 */ 7184 bcmPortFlexeOamControlSdBip8ClearThreshold = 9, /* Threshold for clearing SD BIP8 */ 7185 bcmPortFlexeOamControlSfBip8BlockNum = 10, /* Block number for SF BIP8 checking */ 7186 bcmPortFlexeOamControlSfBip8SetThreshold = 11, /* Threshold for setting SF BIP8 */ 7187 bcmPortFlexeOamControlSfBip8ClearThreshold = 12, /* Threshold for clearing SF BIP8 */ 7188 bcmPortFlexeOamControlSdBeiBlockNum = 13, /* Block number for SD Bei checking */ 7189 bcmPortFlexeOamControlSdBeiSetThreshold = 14, /* Threshold for setting SD Bei */ 7190 bcmPortFlexeOamControlSdBeiClearThreshold = 15, /* Threshold for clearing SD Bei */ 7191 bcmPortFlexeOamControlSfBeiBlockNum = 16, /* Block number for SF Bei checking */ 7192 bcmPortFlexeOamControlSfBeiSetThreshold = 17, /* Threshold for setting SF Bei */ 7193 bcmPortFlexeOamControlSfBeiClearThreshold = 18, /* Threshold for clearing SF Bei */ 7194 bcmPortSarOamControlIlkn2SarBypassEnable = 19, /* Enable SAR OAM bypass, direction: 7195 ILKN-to-SAR */ 7196 bcmPortSarOamControlSar2IlknBypassEnable = 20 /* Enable SAR OAM bypass, direction: 7197 SAR-to-ILKN */ 7198 } bcm_port_flexe_oam_control_type_t; 7199 7200 /* FlexE OAM base period type */ 7201 typedef enum bcm_port_flexe_oam_base_period_e { 7202 bcmPortFlexeOamBasePeriod16K = 0, /* OAM base period 16K */ 7203 bcmPortFlexeOamBasePeriod32K = 1, /* OAM base period 32K */ 7204 bcmPortFlexeOamBasePeriod64K = 2, /* OAM base period 64K */ 7205 bcmPortFlexeOamBasePeriod512K = 3 /* OAM base period 512K */ 7206 } bcm_port_flexe_oam_base_period_t; 7207 7208 #ifndef BCM_HIDE_DISPATCHABLE 7209 7210 /* Get FlexE OAM configurations. */ 7211 extern int bcm_port_flexe_oam_control_get( 7212 int unit, 7213 bcm_port_t port, 7214 uint32 flags, 7215 bcm_port_flexe_oam_control_type_t type, 7216 uint32 *val); 7217 7218 /* Set FlexE OAM configurations. */ 7219 extern int bcm_port_flexe_oam_control_set( 7220 int unit, 7221 bcm_port_t port, 7222 uint32 flags, 7223 bcm_port_flexe_oam_control_type_t type, 7224 uint32 val); 7225 7226 #endif /* BCM_HIDE_DISPATCHABLE */ 7227 7228 /* FlexE OAM base period type */ 7229 typedef enum bcm_port_flexe_oam_stat_e { 7230 bcmbcmPortFlexeOamStatBip8 = 0, /* OAM BIP8 error counter */ 7231 bcmPortFlexeOamStatBei = 1, /* OAM BEI error counter */ 7232 bcmPortFlexeOamPacketCount = 2, /* OAM packet counter */ 7233 bcmPortFlexeBaseOamPacketCount = 3 /* OAM base packet counter */ 7234 } bcm_port_flexe_oam_stat_t; 7235 7236 #ifndef BCM_HIDE_DISPATCHABLE 7237 7238 /* Get OAM stat counters. */ 7239 extern int bcm_port_flexe_oam_stat_get( 7240 int unit, 7241 bcm_port_t port, 7242 uint32 flags, 7243 bcm_port_flexe_oam_stat_t stat, 7244 uint64 *val); 7245 7246 /* Get the rxcdr and txpi clock in Hz for given port. */ 7247 extern int bcm_port_txpi_rxcdr_clk_get( 7248 int unit, 7249 bcm_port_t port, 7250 uint32 *txpi_clk, 7251 uint32 *rxcdr_clk); 7252 7253 #endif /* BCM_HIDE_DISPATCHABLE */ 7254 7255 /* POST-FEC BER projection input */ 7256 typedef struct bcm_port_ber_proj_params_s { 7257 int hist_errcnt_thresh; /* Histogram error count threshold */ 7258 int interval_second; /* Measurement time that PRBS errors are 7259 accumulated */ 7260 bcm_port_phy_fec_t fec_type; /* fec_type for port */ 7261 } bcm_port_ber_proj_params_t; 7262 7263 /* POST-FEC BER projection input */ 7264 typedef struct bcm_port_ber_proj_analyzer_errcnt_s { 7265 int start_hist_errcnt_thresh; /* Histogram error count threshold */ 7266 int max_errcnt_thresh; /* PRBS error count threshold */ 7267 uint32 proj_ber; /* projected BER */ 7268 uint32 ber_proj_prbs_errcnt[16]; /* Array which stores prbs error count */ 7269 } bcm_port_ber_proj_analyzer_errcnt_t; 7270 7271 #ifndef BCM_HIDE_DISPATCHABLE 7272 7273 /* Get POST FEC Projection info. */ 7274 extern int bcm_port_post_ber_proj_get( 7275 int unit, 7276 bcm_port_t port, 7277 bcm_port_ber_proj_params_t *ber_proj, 7278 int max_errcnt, 7279 bcm_port_ber_proj_analyzer_errcnt_t *errcnt_array, 7280 int *actual_errcnt); 7281 7282 /* Configure PCS lane map for the entire PM. */ 7283 extern int bcm_port_pcs_lane_map_set( 7284 int unit, 7285 bcm_port_t port, 7286 uint32 flags, 7287 int num_map, 7288 bcm_port_lane_to_serdes_map_t *serdes_map); 7289 7290 /* Get the L2 interface ID of a gport. */ 7291 extern int bcm_port_l2_interface_id_get( 7292 int unit, 7293 bcm_gport_t port, 7294 int *interface_id); 7295 7296 /* Get the GPORT of a L2 interface ID. */ 7297 extern int bcm_port_l2_interface_gport_get( 7298 int unit, 7299 int interface_id, 7300 bcm_gport_t *port); 7301 7302 /* Get the port bitmap of a given pipe. */ 7303 extern int bcm_port_pipe_pbmp_get( 7304 int unit, 7305 int pipe, 7306 bcm_pbmp_t *pbmp); 7307 7308 /* Get the port btimap of a given packet buffer. */ 7309 extern int bcm_port_buffer_pbmp_get( 7310 int unit, 7311 int buffer_id, 7312 bcm_pbmp_t *pbmp); 7313 7314 #endif /* BCM_HIDE_DISPATCHABLE */ 7315 7316 /* Source of egress VLAN priority. */ 7317 typedef enum bcm_port_egress_vlan_pri_src_e { 7318 bcmPortEgressVlanPriSrcIntPri = 0, /* The source is the internal priority 7319 map. */ 7320 bcmPortEgressVlanPriSrcPktPri = 1, /* Keep the packet priority. */ 7321 bcmPortEgressVlanPriSrcVpn = 2 /* The source is egress VPN or egress 7322 VLAN translation by looking up both 7323 VPN and port group (higher priority 7324 than egress VPN). */ 7325 } bcm_port_egress_vlan_pri_src_t; 7326 7327 /* Port group type. */ 7328 typedef enum bcm_port_group_type_e { 7329 bcmPortGroupEgressL2Interface = 0, /* L2 OIF. */ 7330 bcmPortGroupDvp = 1, /* DVP. */ 7331 bcmPortGroupCount = 2 /* Number of port group type. */ 7332 } bcm_port_group_type_t; 7333 7334 /* Port group range. */ 7335 typedef struct bcm_port_group_range_s { 7336 int min; /* Lower limit of the range. */ 7337 int max; /* Upper limit of the range. */ 7338 } bcm_port_group_range_t; 7339 7340 #ifndef BCM_HIDE_DISPATCHABLE 7341 7342 /* Get port group range based on port group type. */ 7343 extern int bcm_port_group_range_get( 7344 int unit, 7345 bcm_port_group_type_t type, 7346 bcm_port_group_range_t *range); 7347 7348 #endif /* BCM_HIDE_DISPATCHABLE */ 7349 7350 typedef enum bcm_port_fdr_symb_err_window_size_e { 7351 bcmPortFdrSymbErrWindowCw128 = _SHR_PORT_FDR_SYMB_ERR_WINDOW_CW_128, 7352 bcmPortFdrSymbErrWindowCw1K = _SHR_PORT_FDR_SYMB_ERR_WINDOW_CW_1K, 7353 bcmPortFdrSymbErrWindowCw8K = _SHR_PORT_FDR_SYMB_ERR_WINDOW_CW_8K, 7354 bcmPortFdrSymbErrWindowCw64K = _SHR_PORT_FDR_SYMB_ERR_WINDOW_CW_64K, 7355 bcmPortFdrSymbErrWindowCw512K = _SHR_PORT_FDR_SYMB_ERR_WINDOW_CW_512K, 7356 bcmPortFdrSymbErrWindowCw4M = _SHR_PORT_FDR_SYMB_ERR_WINDOW_CW_4M, 7357 bcmPortFdrSymbErrWindowCw32M = _SHR_PORT_FDR_SYMB_ERR_WINDOW_CW_32M, 7358 bcmPortFdrSymbErrWindowCw256M = _SHR_PORT_FDR_SYMB_ERR_WINDOW_CW_256M, 7359 bcmPortFdrSymbErrWindowCwCount = _SHR_PORT_FDR_SYMB_ERR_WINDOW_CW_COUNT 7360 } bcm_port_fdr_symb_err_window_size_t; 7361 7362 typedef struct bcm_port_fdr_config_s { 7363 int fdr_enable; /* enable Flight Data Recorder (FDR) */ 7364 bcm_port_fdr_symb_err_window_size_t window_size; /* indicate a window size for FDR symbol 7365 error */ 7366 uint32 symb_err_threshold; /* indicate a threshold value for FDR 7367 symbol error */ 7368 int symb_err_stats_sel; /* To select the stats range of symbol 7369 errors in bcm_port_fdr_stats_t, in 7370 which cw_sN_errs indicates count of 7371 code words with S+N symbol errors. 7372 symb_err_stats_sel = 0 indicates S is 7373 0. symb_err_stats_sel = 1 indicates S 7374 = 9 or S = 8 based on the chip. The 7375 cw_s8_errs is 0 when the 7376 chip-dependent value of S is 8. */ 7377 int intr_enable; /* enable Flight Data Recorder (FDR) 7378 interrupt */ 7379 } bcm_port_fdr_config_t; 7380 7381 #ifndef BCM_HIDE_DISPATCHABLE 7382 7383 /* Set the configuration for Flight Data Recorder (FDR) on a port. */ 7384 extern int bcm_port_fdr_config_set( 7385 int unit, 7386 bcm_port_t port, 7387 bcm_port_fdr_config_t *fdr_config); 7388 7389 /* Get the configuration for Flight Data Recorder (FDR) on a port. */ 7390 extern int bcm_port_fdr_config_get( 7391 int unit, 7392 bcm_port_t port, 7393 bcm_port_fdr_config_t *fdr_config); 7394 7395 #endif /* BCM_HIDE_DISPATCHABLE */ 7396 7397 typedef struct bcm_port_fdr_stats_s { 7398 uint64 start_time; /* indicate the time when Flight Data Recorder 7399 (FDR) start to collect data */ 7400 uint64 end_time; /* indicate the time when the last statistics 7401 are collected */ 7402 uint32 num_uncorrect_cws; /* indicate the total number of uncorrectable 7403 code words */ 7404 uint32 num_cws; /* total number of code words used for the 7405 statistics collection */ 7406 uint32 num_symb_errs; /* total number of symbol errors detected */ 7407 uint32 cw_s0_errs; /* Number of Code Words with S + 0 symbol errors 7408 where S is the selected value via 7409 symb_err_stats_sel in bcm_port_fdr_config_t. 7410 If symb_err_stats_sel is 0, S is 0. If 7411 symb_err_stats_sel is 1, S = 9 or S = 8 based 7412 on the chip. */ 7413 uint32 cw_s1_errs; /* Number of Code Words with S + 1 symbol errors 7414 where S is the selected value via 7415 symb_err_stats_sel in bcm_port_fdr_config_t. 7416 If symb_err_stats_sel is 0, S is 0. If 7417 symb_err_stats_sel is 1, S = 9 or S = 8 based 7418 on the chip. */ 7419 uint32 cw_s2_errs; /* Number of Code Words with S + 2 symbol errors 7420 where S is the selected value via 7421 symb_err_stats_sel in bcm_port_fdr_config_t. 7422 If symb_err_stats_sel is 0, S is 0. If 7423 symb_err_stats_sel is 1, S = 9 or S = 8 based 7424 on the chip. */ 7425 uint32 cw_s3_errs; /* Number of Code Words with S + 3 symbol errors 7426 where S is the selected value via 7427 symb_err_stats_sel in bcm_port_fdr_config_t. 7428 If symb_err_stats_sel is 0, S is 0. If 7429 symb_err_stats_sel is 1, S = 9 or S = 8 based 7430 on the chip. */ 7431 uint32 cw_s4_errs; /* Number of Code Words with S + 4 symbol errors 7432 where S is the selected value via 7433 symb_err_stats_sel in bcm_port_fdr_config_t. 7434 If symb_err_stats_sel is 0, S is 0. If 7435 symb_err_stats_sel is 1, S = 9 or S = 8 based 7436 on the chip. */ 7437 uint32 cw_s5_errs; /* Number of Code Words with S + 5 symbol errors 7438 where S is the selected value via 7439 symb_err_stats_sel in bcm_port_fdr_config_t. 7440 If symb_err_stats_sel is 0, S is 0. If 7441 symb_err_stats_sel is 1, S = 9 or S = 8 based 7442 on the chip. */ 7443 uint32 cw_s6_errs; /* Number of Code Words with S + 6 symbol errors 7444 where S is the selected value via 7445 symb_err_stats_sel in bcm_port_fdr_config_t. 7446 If symb_err_stats_sel is 0, S is 0. If 7447 symb_err_stats_sel is 1, S = 9 or S = 8 based 7448 on the chip. */ 7449 uint32 cw_s7_errs; /* Number of Code Words with S + 7 symbol errors 7450 where S is the selected value via 7451 symb_err_stats_sel in bcm_port_fdr_config_t. 7452 If symb_err_stats_sel is 0, S is 0. If 7453 symb_err_stats_sel is 1, S = 9 or S = 8 based 7454 on the chip. */ 7455 uint32 cw_s8_errs; /* Number of Code Words with S + 8 symbol errors 7456 where S is the selected value via 7457 symb_err_stats_sel in bcm_port_fdr_config_t. 7458 If symb_err_stats_sel is 0, S is 0. If 7459 symb_err_stats_sel is 1, S = 9 or S = 8 based 7460 on the chip. */ 7461 } bcm_port_fdr_stats_t; 7462 7463 #ifndef BCM_HIDE_DISPATCHABLE 7464 7465 /* Get the statistics of Flight Data Recorder (FDR) on a port */ 7466 extern int bcm_port_fdr_stats_get( 7467 int unit, 7468 bcm_port_t port, 7469 bcm_port_fdr_stats_t *fdr_stats); 7470 7471 #endif /* BCM_HIDE_DISPATCHABLE */ 7472 7473 /* bcm_port_fdr_handler_t */ 7474 typedef void (*bcm_port_fdr_handler_t)( 7475 int unit, 7476 bcm_port_t port, 7477 bcm_port_fdr_stats_t *fdr_stats, 7478 void *user_data); 7479 7480 #ifndef BCM_HIDE_DISPATCHABLE 7481 7482 /* 7483 * Register port Flight Data Recorder (FDR) interrupt notification 7484 * callbacks 7485 */ 7486 extern int bcm_port_fdr_callback_register( 7487 int unit, 7488 bcm_port_fdr_handler_t f, 7489 void *user_data); 7490 7491 /* 7492 * Unregister port Flight Data Recorder (FDR) interrupt notification 7493 * callbacks 7494 */ 7495 extern int bcm_port_fdr_callback_unregister( 7496 int unit, 7497 bcm_port_fdr_handler_t f, 7498 void *user_data); 7499 7500 #endif /* BCM_HIDE_DISPATCHABLE */ 7501 7502 /* Bit error mask to generate FEC error. */ 7503 typedef struct bcm_port_phy_fec_error_mask_s { 7504 uint32 error_mask_bit_31_0; /* Error mask bit 31-0. */ 7505 uint32 error_mask_bit_63_32; /* Error mask bit 63-32. */ 7506 uint16 error_mask_bit_79_64; /* Error mask bit 79-64. */ 7507 } bcm_port_phy_fec_error_mask_t; 7508 7509 #ifndef BCM_HIDE_DISPATCHABLE 7510 7511 /* Set one-time fec error injection. */ 7512 extern int bcm_port_phy_fec_error_inject_set( 7513 int unit, 7514 bcm_port_t port, 7515 uint16 error_control_map, 7516 bcm_port_phy_fec_error_mask_t bit_error_mask); 7517 7518 /* Get configuration of one-time fec error injection. */ 7519 extern int bcm_port_phy_fec_error_inject_get( 7520 int unit, 7521 bcm_port_t port, 7522 uint16 *error_control_map, 7523 bcm_port_phy_fec_error_mask_t *bit_error_mask); 7524 7525 #endif /* BCM_HIDE_DISPATCHABLE */ 7526 7527 #endif /* __BCM_PORT_H__ */