gdpll.h (12863B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 7 * 8 */ 9 10 #ifndef __BCM_GDPLL_H__ 11 #define __BCM_GDPLL_H__ 12 13 #if defined(INCLUDE_GDPLL) 14 15 #include <bcm/types.h> 16 17 /* GDPLL Macros */ 18 #define BCM_GDPLL_NUM_CHANNELS 128 /* Supported number of GDPLL 19 channels */ 20 #define BCM_GDPLL_NUM_PORTS 64 /* GDPLL supports 64 ports */ 21 #define BCM_GDPLL_NUM_CPRI_PORTS 32 /* GDPLL supports 32 CPRI ports */ 22 #define BCM_GDPLL_NUM_STATES 3 /* GDPLL number of states */ 23 24 /* GDPLL Flags for channel create */ 25 #define BCM_GDPLL_CONF_DPLL 0x1 /* Configure DPLL */ 26 #define BCM_GDPLL_EVENT_CONFIG_REF 0x2 /* Configure channel reference */ 27 #define BCM_GDPLL_EVENT_CONFIG_FB 0x4 /* Configure channel feedback */ 28 #define BCM_GDPLL_CHAN_ALLOC 0x8 /* Channel alloc */ 29 #define BCM_GDPLL_CHAN_SET_PRIORITY 0x10 /* Set channel priority */ 30 #define BCM_GDPLL_CHAN_OUTPUT_CONF 0x20 /* Configure channel output */ 31 32 /* GDPLL Flags to retrieve state in gdpll_chan_state_t */ 33 #define BCM_GDPLL_CHAN_STATE_LOCK 0x1 /* Channel Lock flag */ 34 #define BCM_GDPLL_CHAN_STATE_ENABLE 0x2 /* Channel enable flag */ 35 #define BCM_GDPLL_CHAN_STATE_ERROR 0x4 /* Channel error flag */ 36 37 /* GDPLL Input Events */ 38 typedef enum bcm_gdpll_input_event_e { 39 bcmGdpllInputEventCpu = 0, /* CPU generated input event type */ 40 bcmGdpllInputEventBS0HB = 1, /* BroadSync0 heartbeat input event type */ 41 bcmGdpllInputEventBS1HB = 2, /* BroadSync1 heartbeat input event type */ 42 bcmGdpllInputEventGPIO0 = 3, /* GPIO0 input event type */ 43 bcmGdpllInputEventGPIO1 = 4, /* GPIO1 input event type */ 44 bcmGdpllInputEventGPIO2 = 5, /* GPIO2 input event type */ 45 bcmGdpllInputEventGPIO3 = 6, /* GPIO3 input event type */ 46 bcmGdpllInputEventGPIO4 = 7, /* GPIO4 input event type */ 47 bcmGdpllInputEventGPIO5 = 8, /* GPIO5 input event type */ 48 bcmGdpllInputEventIPDM0 = 9, /* IPDM0 input event type */ 49 bcmGdpllInputEventIPDM1 = 10, /* IPDM1 input event type */ 50 bcmGdpllInputEventTS1TS = 11, /* TS1 counter timestamp event type */ 51 bcmGdpllInputEventBS0PLL = 12, /* BroadSync0 PLL input event type */ 52 bcmGdpllInputEventBS1PLL = 13, /* BroadSync1 PLL input event type */ 53 bcmGdpllInputEventRSVD1IF = 14, /* RSVD1 interface input event type */ 54 bcmGdpllInputEventRSVD1RF = 15, /* BCN counter input event type */ 55 bcmGdpllInputEventBS0ConvTC = 16, /* BroadSync0 converted timecode input 56 type */ 57 bcmGdpllInputEventBS1ConvTC = 17, /* BroadSync1 converted timecode input 58 type */ 59 bcmGdpllInputEventLCPLL0 = 18, /* Serdes LCPLL0 input event type */ 60 bcmGdpllInputEventLCPLL1 = 19, /* Serdes LCPLL1 input event type */ 61 bcmGdpllInputEventLCPLL2 = 20, /* Serdes LCPLL2 input event type */ 62 bcmGdpllInputEventLCPLL3 = 21, /* Serdes LCPLL3 input event type */ 63 bcmGdpllInputEventPORT = 22, /* Input event from port type */ 64 bcmGdpllInputEventR5 = 23, /* Input event from R5 core */ 65 bcmGdpllInputEventMax = 24 /* Input event max value */ 66 } bcm_gdpll_input_event_t; 67 68 /* GDPLL chan error codes */ 69 typedef enum bcm_gdpll_chan_error_e { 70 bcmGdpllChanErrorNone = 0, /* No error */ 71 bcmGdpllChanErrorOverload = 1, /* M7 Overload */ 72 bcmGdpllChanErrorTsPpm = 2, /* TS PPM Violation */ 73 bcmGdpllChanErrorTsTout = 3, /* Late Timestamp. WD timer expired */ 74 bcmGdpllChanErrorDpllLError = 4 /* DPLL tracking large error */ 75 } bcm_gdpll_chan_error_t; 76 77 /* GDPLL port events */ 78 typedef enum bcm_gdpll_port_event_e { 79 bcmGdpllPortEventRXSOF = 0, /* CPRI port recieve SOF input event */ 80 bcmGdpllPortEventTXSOF = 1, /* CPRI port transmit SOF input event */ 81 bcmGdpllPortEventROE = 2, /* CPRI ROE timestamp event */ 82 bcmGdpllPortEventRXCDR = 3, /* Port recieve CDR event */ 83 bcmGdpllPortEventTXPI = 4 /* Port TXPI event */ 84 } bcm_gdpll_port_event_t; 85 86 /* GDPLL event destination */ 87 typedef enum bcm_gdpll_event_dest_e { 88 bcmGdpllEventDestCPU = 0, /* Event forward to CPU FIFO */ 89 bcmGdpllEventDestM7 = 1, /* Event forward to GDPLL IA */ 90 bcmGdpllEventDestALL = 2 /* Event forward to both */ 91 } bcm_gdpll_event_dest_t; 92 93 /* GDPLL channel output NCO control types */ 94 typedef enum bcm_gdpll_output_event_e { 95 bcmGdpllOutputEventBSPLL0 = 0, /* NCO out for BroadSync0 PLL */ 96 bcmGdpllOutputEventBSPLL1 = 1, /* NCO out for BroadSync1 PLL */ 97 bcmGdpllOutputEventLCPLL0 = 2, /* NCO out for serdes LCPLL0 */ 98 bcmGdpllOutputEventLCPLL1 = 3, /* NCO out for serdes LCPLL1 */ 99 bcmGdpllOutputEventLCPLL2 = 4, /* NCO out for serdes LCPLL2 */ 100 bcmGdpllOutputEventLCPLL3 = 5, /* NCO out for serdes LCPLL3 */ 101 bcmGdpllOutputEventTS0 = 6, /* NCO out for TS0 counter */ 102 bcmGdpllOutputEventTS1 = 7, /* NCO out for TS1 counter */ 103 bcmGdpllOutputEventTXPI = 8, /* NCO out for TXPI on a given port */ 104 bcmGdpllOutputEventBCN = 9, /* NCO out for BCN counter */ 105 bcmGdpllOutputEventNTPTOD = 10, /* NCO out for NTP TOD */ 106 bcmGdpllOutputEventPTPTOD = 11 /* NCO out for PTP TOD */ 107 } bcm_gdpll_output_event_t; 108 109 /* GDPLL Channel prioritization */ 110 typedef enum bcm_gdpll_chan_priority_e { 111 bcmGdpllChanPriority0 = 0, /* Highest priority */ 112 bcmGdpllChanPriority1 = 1, 113 bcmGdpllChanPriority2 = 2, 114 bcmGdpllChanPriority3 = 3 /* Lowest priority */ 115 } bcm_gdpll_chan_priority_t; 116 117 /* GDPLL Debug modes */ 118 typedef enum bcm_gdpll_debug_mode_e { 119 bcmGdpllDebugMode1 = 0, /* To enable debug Mode-1 */ 120 bcmGdpllDebugMode2 = 1, /* To enable debug Mode-2 */ 121 bcmGdpllDebugCount = 2 /* Channel debug mode count */ 122 } bcm_gdpll_debug_mode_t; 123 124 /* TS Pair forwarding */ 125 typedef enum bcm_gdpll_debug_dest_e { 126 bcmGdpllDebugDestCPU = 0, /* TS-Pair forward to CPU-FIFO */ 127 bcmGdpllDebugDestM7 = 1, /* TS-Pair forward to M7 */ 128 bcmGdpllDebugDestALL = 2 /* TS-Pair forward to both M7 and CPU */ 129 } bcm_gdpll_debug_dest_t; 130 131 /* GDPLL CB Type definitions */ 132 typedef enum bcm_gdpll_cb_reg_e { 133 bcmGdpllCbRsvd1 = 0, /* CB for RSVD1 */ 134 bcmGdpllCbChanState = 1, /* CB for gdpll chan state change */ 135 bcmGdpllCbMax = 2 /* CB max value */ 136 } bcm_gdpll_cb_reg_t; 137 138 /* GDPLL Channel input structure. */ 139 typedef struct bcm_gdpll_chan_input_s { 140 bcm_gdpll_input_event_t input_event; /* Input event type for the channel */ 141 bcm_port_t port; /* Event input from the port */ 142 bcm_gdpll_port_event_t port_event_type; /* Event input type from the port */ 143 uint32 event_divisor; /* Divisor value for an input event */ 144 bcm_gdpll_event_dest_t event_dest; /* Input event forwarding destination 145 type */ 146 int ts_counter; /* 0: TS0, 1:TS1 */ 147 int ppm_check_enable; /* PPM check enable flag, boolean */ 148 uint16 ppm_value; /* PPM value */ 149 uint16 event_frequency; /* Event frequency for PPM check 150 configuration */ 151 } bcm_gdpll_chan_input_t; 152 153 /* DPLL Config structure. */ 154 typedef struct bcm_gdpll_chan_dpll_config_s { 155 int32 k1[BCM_GDPLL_NUM_STATES]; /* DPLL config parameter */ 156 uint8 k1Shift[BCM_GDPLL_NUM_STATES]; /* left or right sight, 48 places max */ 157 int32 k1k2[BCM_GDPLL_NUM_STATES]; 158 uint8 k1k2Shift[BCM_GDPLL_NUM_STATES]; 159 uint32 lockDetThres[BCM_GDPLL_NUM_STATES]; 160 uint32 lockIndicatorThresholdLo; /* Lock Indicator threshold */ 161 uint32 lockIndicatorThresholdLHi; /* Lock Indicator threshold */ 162 uint16 dwell_count[BCM_GDPLL_NUM_STATES]; 163 uint64 phase_error_limiter_thres[BCM_GDPLL_NUM_STATES]; 164 uint8 nco_bits; 165 uint8 phase_counter_ref; /* Boolean */ 166 uint8 dpll_num_states; 167 uint16 idump_mod[BCM_GDPLL_NUM_STATES]; 168 uint8 phase_error_shift; 169 uint64 nominal_loop_filter; 170 uint8 invert_phase_error; 171 uint8 norm_phase_error; 172 uint32 phase_error_thres0; 173 uint32 phase_error_thres1; 174 uint16 holdover_filter_coeff; 175 } bcm_gdpll_chan_dpll_config_t; 176 177 /* Per DPLL state variables stored in state memory. */ 178 typedef struct bcm_gdpll_chan_dpll_state_s { 179 uint8 dpll_state; /* Software DPLL state */ 180 int64 loop_filter; /* filter parameter */ 181 uint32 dwell_counter; /* filter dwell counter */ 182 uint32 lockDetFilter; /* Filter parameter */ 183 int64 offset; 184 uint8 init_flag; /* Initialize to TRUE */ 185 uint8 init_offset_flag; /* Initialize to FALSE */ 186 uint64 phase_counter; /* Phase counter value, unsigned 52 */ 187 uint64 phaseCounterDelta; 188 uint16 phaseCounterN; 189 uint16 phaseCounterM; 190 uint16 phaseCounterFrac; 191 uint16 idumpCounter; 192 int64 accumPhaseError; 193 uint8 lockIndicator; 194 uint8 lossOfLockIndicator; 195 uint8 largeErrorIndicator; 196 } bcm_gdpll_chan_dpll_state_t; 197 198 /* GDPLL Channel state */ 199 typedef struct bcm_gdpll_chan_state_s { 200 int chan; /* Channel handle */ 201 uint32 state; /* Channel state info */ 202 bcm_gdpll_chan_error_t error_code; /* Error code on the given channel */ 203 } bcm_gdpll_chan_state_t; 204 205 /* GDPLL Channel configuration */ 206 typedef struct bcm_gdpll_chan_s { 207 bcm_gdpll_chan_input_t event_ref; /* Channel input reference */ 208 bcm_gdpll_chan_input_t event_fb; /* Channel input feedback */ 209 bcm_gdpll_chan_priority_t chan_prio; /* Channel priority configurations */ 210 bcm_gdpll_chan_dpll_config_t chan_dpll_config; /* Channel DPLL configuration */ 211 bcm_gdpll_chan_dpll_state_t chan_dpll_state; /* Channel DPLL state */ 212 bcm_gdpll_output_event_t out_event; /* Channel output configuration for NCO 213 control */ 214 bcm_port_t port; /* Output port for TXPI controls */ 215 bcm_gdpll_debug_dest_t ts_pair_dest; /* Debug Configurations to forward 216 timestamp pairs */ 217 } bcm_gdpll_chan_t; 218 219 #ifndef BCM_HIDE_DISPATCHABLE 220 221 /* Polling API for GDPLL input event */ 222 extern int bcm_gdpll_input_event_poll( 223 int unit, 224 bcm_gdpll_input_event_t input_event, 225 uint32 timeout); 226 227 /* Create the GDPLL channel. */ 228 extern int bcm_gdpll_chan_create( 229 int unit, 230 uint32 flags, 231 bcm_gdpll_chan_t *gdpll_chan, 232 int *pChan); 233 234 /* Destroy the GDPLL channel. */ 235 extern int bcm_gdpll_chan_destroy( 236 int unit, 237 int chan); 238 239 /* Set the GDPLL channel offset */ 240 extern int bcm_gdpll_offset_set( 241 int unit, 242 int chan, 243 uint64 offset); 244 245 /* Get the GDPLL channel offset */ 246 extern int bcm_gdpll_offset_get( 247 int unit, 248 int chan, 249 uint64 *dpllOffset); 250 251 /* Enable the GDPLL channel */ 252 extern int bcm_gdpll_chan_enable( 253 int unit, 254 int chan, 255 int enable); 256 257 /* Get the state of the GDPLL channel */ 258 extern int bcm_gdpll_chan_state_get( 259 int unit, 260 int chan, 261 uint32 *dpllState); 262 263 /* Enable debug on a given GDPLL channel */ 264 extern int bcm_gdpll_chan_debug_enable( 265 int unit, 266 int chan, 267 bcm_gdpll_debug_mode_t debug_mode, 268 int enable); 269 270 /* Enable global GDPLL debug feature */ 271 extern int bcm_gdpll_debug( 272 int unit, 273 int enable); 274 275 /* Flush the GDPLL pipeline */ 276 extern int bcm_gdpll_flush( 277 int unit); 278 279 #endif /* BCM_HIDE_DISPATCHABLE */ 280 281 /* GDPLL debug buffer recieve callback */ 282 typedef int (*bcm_gdpll_debug_cb)( 283 int unit, 284 void *user_data, 285 uint32 debug_buff, 286 uint32 debug_buf_size); 287 288 #ifndef BCM_HIDE_DISPATCHABLE 289 290 /* Register callback function for debug buffer */ 291 extern int bcm_gdpll_debug_cb_register( 292 int unit, 293 bcm_gdpll_debug_cb cb, 294 void *user_data); 295 296 #endif /* BCM_HIDE_DISPATCHABLE */ 297 298 /* GDPLL generic callback */ 299 typedef int (*bcm_gdpll_cb)( 300 int unit, 301 void *user_data, 302 uint32 *cb_data, 303 int cb_type); 304 305 #ifndef BCM_HIDE_DISPATCHABLE 306 307 /* Register callback function for a given type */ 308 extern int bcm_gdpll_cb_register( 309 int unit, 310 bcm_gdpll_cb_reg_t cb_type, 311 bcm_gdpll_cb cb, 312 void *user_data); 313 314 /* Un-register callback function for a given type */ 315 extern int bcm_gdpll_cb_unregister( 316 int unit, 317 bcm_gdpll_cb_reg_t cb_type); 318 319 /* Get the GDPLL channel. */ 320 extern int bcm_gdpll_chan_get( 321 int unit, 322 int chan, 323 bcm_gdpll_chan_t *gdpll_chan); 324 325 #endif /* defined(INCLUDE_GDPLL) */ 326 327 #endif /* BCM_HIDE_DISPATCHABLE */ 328 329 #endif /* __BCM_GDPLL_H__ */