cpri.h (120421B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 7 * 8 */ 9 10 #ifndef __BCM_CPRI_H__ 11 #define __BCM_CPRI_H__ 12 13 #include <bcm/types.h> 14 #include <shared/cpri.h> 15 16 #ifndef BCM_HIDE_DISPATCHABLE 17 18 /* Initialize the CPRI subsystem. */ 19 extern int bcm_cpri_init( 20 int unit); 21 22 /* De-initialize the CPRI subsystem. */ 23 extern int bcm_cpri_detach( 24 int unit); 25 26 #endif /* BCM_HIDE_DISPATCHABLE */ 27 28 /* CPRI Port types */ 29 typedef enum bcm_cpri_port_type_e { 30 bcmCpriPortTypeCpri = 0, /* CPRI port */ 31 bcmCpriPortTypeRsvd4 = 1 /* RSVD4 port */ 32 } bcm_cpri_port_type_t; 33 34 /* bcm_cpri_port_speed_t */ 35 typedef _shr_cpri_port_speed_t bcm_cpri_port_speed_t; 36 37 #define BCM_CPRI_PORT_SPEED_1228P8 _shrCpriPortSpeed1228p8 38 #define BCM_CPRI_PORT_SPEED_2457P6 _shrCpriPortSpeed2457p6 39 #define BCM_CPRI_PORT_SPEED_3072P0 _shrCpriPortSpeed3072p0 40 #define BCM_CPRI_PORT_SPEED_4915P2 _shrCpriPortSpeed4915p2 41 #define BCM_CPRI_PORT_SPEED_6144P0 _shrCpriPortSpeed6144p0 42 #define BCM_CPRI_PORT_SPEED_9830P4 _shrCpriPortSpeed9830p4 43 #define BCM_CPRI_PORT_SPEED_10137P6 _shrCpriPortSpeed10137p6 44 #define BCM_CPRI_PORT_SPEED_12165P12 _shrCpriPortSpeed12165p12 45 #define BCM_CPRI_PORT_SPEED_24330P24 _shrCpriPortSpeed24330p24 46 47 #ifndef BCM_HIDE_DISPATCHABLE 48 49 /* Configures the Rx speed of the specified CPRI port. */ 50 extern int bcm_cpri_port_rx_speed_set( 51 int unit, 52 bcm_gport_t port, 53 bcm_cpri_port_type_t port_type, 54 bcm_cpri_port_speed_t speed); 55 56 /* Retrieves the Rx speed of the specified CPRI port. */ 57 extern int bcm_cpri_port_rx_speed_get( 58 int unit, 59 bcm_gport_t port, 60 bcm_cpri_port_type_t *port_type, 61 bcm_cpri_port_speed_t *speed); 62 63 /* Configures the Tx speed of the specified CPRI port. */ 64 extern int bcm_cpri_port_tx_speed_set( 65 int unit, 66 bcm_gport_t port, 67 bcm_cpri_port_type_t port_type, 68 bcm_cpri_port_speed_t speed); 69 70 /* Retrieves the Tx speed of the specified CPRI port. */ 71 extern int bcm_cpri_port_tx_speed_get( 72 int unit, 73 bcm_gport_t port, 74 bcm_cpri_port_type_t *port_type, 75 bcm_cpri_port_speed_t *speed); 76 77 #endif /* BCM_HIDE_DISPATCHABLE */ 78 79 /* bcm_cpri_frame_sync_mode_t */ 80 typedef _shr_cpri_frame_sync_mode_t bcm_cpri_frame_sync_mode_t; 81 82 /* CPRI Frame Sync Modes */ 83 #define BCM_CPRI_FRAME_SYNC_MODE_HYPER _shrCpriFrameSyncModeHyper 84 #define BCM_CPRI_FRAME_SYNC_MODE_RADIO _shrCpriFrameSyncModeRadio 85 #define BCM_CPRI_FRAME_SYNC_MODE_BASIC _shrCpriFrameSyncModeBasic 86 87 /* CPRI Frame truncation modes */ 88 typedef enum bcm_cpri_frame_trunc_mode_e { 89 bcmCpriFrameTruncMode15_to_16 = 0, /* Truncation 15 to 16 bits */ 90 bcmCpriFrameTruncModeAdd_0 = 1, /* Truncation Add 0. */ 91 bcmCpriFrameTruncMode16_to_15 = 2, /* Truncation of 16 to 15 bits */ 92 bcmCpriFrameTruncModeAdd_1 = 3 /* Truncation of adding 1. */ 93 } bcm_cpri_frame_trunc_mode_t; 94 95 /* CPRI Frame compression modes */ 96 typedef enum bcm_cpri_frame_compress_mode_e { 97 bcmCpriFrameCompressModeCompress = 0, /* Compress Mode */ 98 bcmCpriFrameCompressModeDecompress = 1, /* Decompress Mode */ 99 bcmCpriFrameCompressModeNone = 2 /* No Compression */ 100 } bcm_cpri_frame_compress_mode_t; 101 102 /* CPRI Framer stages */ 103 typedef enum bcm_cpri_stage_e { 104 bcmCpriStageRxParser = 0, /* Rx Parser */ 105 bcmCpriStageTxAssembler = 1 /* Tx Assembler */ 106 } bcm_cpri_stage_t; 107 108 /* CPRI Axc Framer Configuration */ 109 typedef struct bcm_cpri_axc_frame_info_s { 110 int axc_id; /* AxC ID - output for get_all only */ 111 int start_bit; /* Start bit position of basic frame */ 112 int num_bits; /* Number of bits in AxC */ 113 int map_method; /* Mapping method 0 - Method 1, 1 - 114 Method 2 (not Supported) 2 - Method 3 */ 115 int stuffing_count; /* Nst for method#1 bits */ 116 int K; /* Container block count */ 117 int sample_size_M; /* Sample size */ 118 int Nv; /* Nv value for method 3 */ 119 int Na; /* Na value for method 3 */ 120 int Nc; /* Numnber of containers in a basic 121 frame - method 3 only */ 122 bcm_cpri_frame_sync_mode_t frame_sync_mode; /* CPRI Frame synchronization modes */ 123 int basic_frame_offset; /* Frame number offset of basic frame */ 124 int radio_frame_offset; /* Frame number offset of radio frame */ 125 int hyper_frame_offset; /* Frame number offset of hyper frame */ 126 int num_samples_per_roe_pkt; /* Number of samples in RoE payload */ 127 int truncation_enable; /* True/False */ 128 bcm_cpri_frame_trunc_mode_t truncation_mode; /* */ 129 bcm_cpri_frame_compress_mode_t compress_mode; /* */ 130 uint8 priority; /* Priority 0-3 */ 131 uint16 rx_queue_size; /* Queue size in bytes */ 132 uint16 cycle_size; /* Only for Tx, Jitter buffer size in 133 number of packets. */ 134 } bcm_cpri_axc_frame_info_t; 135 136 #ifndef BCM_HIDE_DISPATCHABLE 137 138 /* 139 * Set/Get up the AxC(method 1) or AxC group(method 3) on a CPRI port in 140 * the Rx datapath. 141 */ 142 extern int bcm_cpri_port_rx_axc_frame_add( 143 int unit, 144 bcm_gport_t port, 145 int axc_id, 146 bcm_cpri_axc_frame_info_t *axc_info); 147 148 /* 149 * Retrieves the AxC (method 1) or AxC group (method 3) in the Rx datapth 150 * on a CPRI port. 151 */ 152 extern int bcm_cpri_port_rx_axc_frame_get( 153 int unit, 154 bcm_gport_t port, 155 int axc_id, 156 bcm_cpri_axc_frame_info_t *axc_info); 157 158 /* 159 * Retrieves the configured list of AxC (method 1) or AxC group (method 160 * 3) on a CPRI port. 161 */ 162 extern int bcm_cpri_port_rx_axc_frame_get_all( 163 int unit, 164 bcm_gport_t port, 165 int max_count, 166 bcm_cpri_axc_frame_info_t *axc_info_list, 167 int *axc_count); 168 169 /* 170 * Remove the specified AxC (method 1) or AxC group (method 3) on a CPRI 171 * port. 172 */ 173 extern int bcm_cpri_port_rx_axc_frame_delete( 174 int unit, 175 bcm_gport_t port, 176 int axc_id); 177 178 /* 179 * Sets up the AxC (method 1) or AxC group (method 3) in the Tx datapath 180 * on a CPRI port. 181 */ 182 extern int bcm_cpri_port_tx_axc_frame_add( 183 int unit, 184 bcm_gport_t port, 185 int axc_id, 186 bcm_cpri_axc_frame_info_t *axc_info); 187 188 /* 189 * Retrieves the AxC (method 1) or AxC group (method 3) in the Tx 190 * datapath 191 * on a CPRI port. 192 */ 193 extern int bcm_cpri_port_tx_axc_frame_get( 194 int unit, 195 bcm_gport_t port, 196 int axc_id, 197 bcm_cpri_axc_frame_info_t *axc_info); 198 199 /* 200 * Retrieves the configured list of AxC (method 1) or AxC group (method 201 * 3) in the Tx datapath on a CPRI port. 202 */ 203 extern int bcm_cpri_port_tx_axc_frame_get_all( 204 int unit, 205 bcm_gport_t port, 206 int max_count, 207 bcm_cpri_axc_frame_info_t *axc_info_list, 208 int *axc_count); 209 210 /* 211 * Remove the specified AxC (method 1) or AxC group (method 3) on a CPRI 212 * port. 213 */ 214 extern int bcm_cpri_port_tx_axc_frame_delete( 215 int unit, 216 bcm_gport_t port, 217 int axc_id); 218 219 #endif /* BCM_HIDE_DISPATCHABLE */ 220 221 /* CPRI Encap flags */ 222 #define BCM_CPRI_ENCAP_USE_TAG_ID_FOR_VLAN 0x1 223 #define BCM_CPRI_ENCAP_USE_TAG_ID_FOR_FLOWID 0x2 224 #define BCM_CPRI_ENCAP_USE_OPCODE 0x4 225 226 /* CPRI VLAN Types */ 227 typedef enum bcm_cpri_vlan_type_e { 228 bcmCpriVlanTypeNone = 0, /* No VLAN */ 229 bcmCpriVlanTypeSingle = 1, /* Single Tagged VLAN */ 230 bcmCpriVlanTypeQinQ = 2, /* VLAN Q in Q */ 231 bcmCpriVlanTypeSingleTable1 = 3 /* Single Tagged VLAN using table 1 */ 232 } bcm_cpri_vlan_type_t; 233 234 /* CPRI RoE Subtypes */ 235 typedef enum bcm_cpri_roe_subtype_e { 236 bcmCpriRoESubtypeControl = 0, /* RoE subtype Control */ 237 bcmCpriRoESubtypeResv = 1, /* RoE subtype Reserve */ 238 bcmCpriRoESubtypeAgnostic = 2, /* RoE subtype Agnostic */ 239 bcmCpriRoESubtypeCpriData = 3, /* Roe subtype Data */ 240 bcmCpriRoESubtypeNative = 4, /* RoE Subtype Native */ 241 bcmCpriRoESubtypeSlowCM = 5 /* RoE subtype Slow C&M */ 242 } bcm_cpri_roe_subtype_t; 243 244 /* CPRI RoE Opcodes */ 245 typedef enum bcm_cpri_roe_opcode_e { 246 bcmCpriRoEOpcodeOamTlv = 0, /* OAM TLV */ 247 bcmCpriRoEOpcodeCtrlAxC = 1, /* Control AxC */ 248 bcmCpriRoEOpcodeVSD = 2, /* VSD */ 249 bcmCpriRoEOpcodeTiming = 3 /* Timing */ 250 } bcm_cpri_roe_opcode_t; 251 252 /* CPRI Header Encapsulation types */ 253 typedef enum bcm_cpri_hdr_encap_type_e { 254 bcmCpriHdrEncapTypeRoe = 0, /* ROE encapsulation type */ 255 bcmCpriHdrEncapTypeNone = 1, /* no ROE encapsulation */ 256 bcmCpriHdrEncapTypeCount = 2 /* should be last */ 257 } bcm_cpri_hdr_encap_type_t; 258 259 /* bcm_cpri_roe_frame_format_t */ 260 typedef _shr_cpri_roe_frame_format_t bcm_cpri_roe_frame_format_t; 261 262 /* CPRI RoE Frame Format. */ 263 #define BCM_CPRI_ROE_FRAME_FORMAT_IEEE1914 _shrCpriRoeFrameFormatIEEE1914 /* Selection of IEEE1914 264 frame format */ 265 #define BCM_CPRI_ROE_FRAME_FORMAT_RSVD3 _shrCpriRoeFrameFormatRsvd3 /* Selection of RSVD3 266 frame format */ 267 #define BCM_CPRI_ROE_FRAME_FORMAT_ECPRI8 _shrCpriRoeFrameFormatEcpri8 /* Selection of 8 bytes 268 eCPRI frame format */ 269 #define BCM_CPRI_ROE_FRAME_FORMAT_ECPRI12 _shrCpriRoeFrameFormatEcpri12 /* Selection of 12 bytes 270 eCPRI frame format */ 271 272 /* CPRI Encap Information */ 273 typedef struct bcm_cpri_encap_info_s { 274 uint32 flags; /* CPRI Encap Info flags */ 275 uint16 flow_id; /* Flow ID */ 276 bcm_cpri_roe_subtype_t subtype; /* RoE subtype */ 277 bcm_cpri_hdr_encap_type_t hdr_type; /* CPRI header encapsulation type */ 278 int roe_ordering_info_index; /* RoE ordering Info index */ 279 int macda_index; /* Index to MAC DA address */ 280 int macsa_index; /* Index to MAC SA address */ 281 bcm_cpri_vlan_type_t vlan_type; /* CPRI Vlan type */ 282 int vlan0_idx; /* VLAN 0 Table index */ 283 int vlan1_idx; /* VLAN 1 table index */ 284 int vlan0_priority; /* VLAN 0 priority */ 285 int vlan1_priority; /* VLAN 1 priority */ 286 uint8 vlan_ethertype_idx; /* VLAN EtherType index */ 287 bcm_cpri_roe_opcode_t opcode; /* RoE opcode */ 288 bcm_cpri_roe_frame_format_t type; /* RoE Frame Header Formatt */ 289 uint8 version; /* Header Version used in RSVD3 */ 290 uint32 ecpri_pc_id; /* PC_ID of eCPRI header, 16 bits for 291 eCPRI8 and 8 bits for eCPRI12 */ 292 uint32 ecpri_msg_type; /* Message Type eCPRI header, 8 bits 293 only */ 294 uint8 ecpri12_header_byte0; /* Only for eCPRI12, Protocol Rev, Rsvd 295 and C bits. */ 296 } bcm_cpri_encap_info_t; 297 298 #ifndef BCM_HIDE_DISPATCHABLE 299 300 /* Configure/Retrieve the encapsulation header info for a given AxC ID. */ 301 extern int bcm_cpri_port_encap_set( 302 int unit, 303 bcm_gport_t port, 304 int queue_num, 305 bcm_cpri_encap_info_t *encap_config); 306 307 /* Configure/Retrieve the encapsulation header info for a given AxC ID. */ 308 extern int bcm_cpri_port_encap_get( 309 int unit, 310 bcm_gport_t port, 311 int queue_num, 312 bcm_cpri_encap_info_t *encap_config); 313 314 #endif /* BCM_HIDE_DISPATCHABLE */ 315 316 /* CPRI Encapsulation VLAN configuration */ 317 typedef struct bcm_cpri_encap_vlan_config_s { 318 uint32 ethertype_vlan_tagged; /* Tagged VLAN */ 319 uint32 ethertype_vlan_qinq; /* QinQ VLAN */ 320 uint32 roe_ethertype_0; /* RoE ether type 0 */ 321 uint32 roe_ethertype_1; /* RoE ether type 1 */ 322 } bcm_cpri_encap_vlan_config_t; 323 324 #ifndef BCM_HIDE_DISPATCHABLE 325 326 /* Set/Get the VLAN EtherType configuration for encapsulation header. */ 327 extern int bcm_cpri_port_encap_vlan_config_set( 328 int unit, 329 bcm_gport_t port, 330 bcm_cpri_encap_vlan_config_t *vlan_config); 331 332 /* Set/Get the VLAN EtherType configuration for encapsulation header. */ 333 extern int bcm_cpri_port_encap_vlan_config_get( 334 int unit, 335 bcm_gport_t port, 336 bcm_cpri_encap_vlan_config_t *vlan_config); 337 338 #endif /* BCM_HIDE_DISPATCHABLE */ 339 340 /* CPRI Encap RoE Ordering Info Info types */ 341 typedef enum bcm_cpri_roe_info_type_e { 342 bcmCpriRoEInfoTypeUseSeq = 0, /* Use Sequene number */ 343 bcmCpriRoEInfoTypeBfnForQcnt = 1, /* Use Bfn for Qcnt */ 344 bcmCpriRoEInfoTypePInfo = 2 /* P info */ 345 } bcm_cpri_roe_info_type_t; 346 347 /* CPRI Encap RoE Ordering Info Increment types */ 348 typedef enum bcm_cpri_roe_incr_type_e { 349 bcmCpriRoEIncrTypeNone = 0, /* No increment. */ 350 bcmCpriRoEIncrTypeConstant = 1, /* Increment by a Contant */ 351 bcmCpriRoEIncrTypePayloadSize = 2 /* Increment by payload size */ 352 } bcm_cpri_roe_incr_type_t; 353 354 /* CPRI Encap RoE Ordering Information */ 355 typedef struct bcm_cpri_encap_roe_oi_s { 356 bcm_cpri_roe_info_type_t info_type; /* ordering info type */ 357 bcm_cpri_roe_incr_type_t p_seq_incr; /* seqNumPIncProp */ 358 bcm_cpri_roe_incr_type_t q_seq_incr; /* seqNumQIncProp */ 359 uint32 pcnt_size; /* Number in the range 1 to 32 */ 360 uint32 pcnt_increment; /* seqNumPInc */ 361 uint32 pcnt_max; /* seqNumPMax */ 362 uint32 qcnt_size; /* Number in the range 0 to (32-pcnt) */ 363 uint32 qcnt_increment; /* seqNumQInc */ 364 uint32 qcnt_max; /* seqNumQMax */ 365 uint32 seq_rsvd; /* seqNumRsvd Value */ 366 } bcm_cpri_encap_roe_oi_t; 367 368 #ifndef BCM_HIDE_DISPATCHABLE 369 370 /* Set/Get the ordering info for encapsulation header. */ 371 extern int bcm_cpri_port_encap_roe_ordering_info_set( 372 int unit, 373 bcm_gport_t port, 374 int index, 375 bcm_cpri_encap_roe_oi_t *ordering_info); 376 377 /* Set/Get the ordering info for encapsulation header. */ 378 extern int bcm_cpri_port_encap_roe_ordering_info_get( 379 int unit, 380 bcm_gport_t port, 381 int index, 382 bcm_cpri_encap_roe_oi_t *ordering_info); 383 384 #endif /* BCM_HIDE_DISPATCHABLE */ 385 386 /* CPRI Encap RoE Ordering Info Sequence Offset configuration */ 387 typedef struct bcm_cpri_roe_oi_seq_offset_s { 388 uint32 pcnt_size; /* Pcnt Size */ 389 uint32 pcnt_offset; /* Pcnt Offset */ 390 uint32 qcnt_size; /* Qcnt Size */ 391 uint32 qcnt_offset; /* Qcnt Offset */ 392 } bcm_cpri_roe_oi_seq_offset_t; 393 394 #ifndef BCM_HIDE_DISPATCHABLE 395 396 /* Set/Get sequence offset information associated with the ordering info. */ 397 extern int bcm_cpri_port_encap_roe_ordering_sequence_offset_set( 398 int unit, 399 bcm_gport_t port, 400 int queue, 401 int control, 402 bcm_cpri_roe_oi_seq_offset_t *seq_offset); 403 404 /* Set/Get sequence offset information associated with the ordering info. */ 405 extern int bcm_cpri_port_encap_roe_ordering_sequence_offset_get( 406 int unit, 407 bcm_gport_t port, 408 int queue, 409 int control, 410 bcm_cpri_roe_oi_seq_offset_t *seq_offset); 411 412 /* Set/Get the encapsulation entry MAC DA for lookup. */ 413 extern int bcm_cpri_port_encap_roe_entry_macda_set( 414 int unit, 415 bcm_gport_t port, 416 int index, 417 bcm_mac_t macaddr); 418 419 /* Set/Get the encapsulation entry MAC SA for lookup. */ 420 extern int bcm_cpri_port_encap_roe_entry_macsa_set( 421 int unit, 422 bcm_gport_t port, 423 int index, 424 bcm_mac_t macaddr); 425 426 /* Set/Get the encapsulation entry MAC DA for lookup. */ 427 extern int bcm_cpri_port_encap_roe_entry_macda_get( 428 int unit, 429 bcm_gport_t port, 430 int index, 431 bcm_mac_t *macaddr); 432 433 /* Set/Get the encapsulation entry MAC SA for lookup. */ 434 extern int bcm_cpri_port_encap_roe_entry_macsa_get( 435 int unit, 436 bcm_gport_t port, 437 int index, 438 bcm_mac_t *macaddr); 439 440 #endif /* BCM_HIDE_DISPATCHABLE */ 441 442 /* CPRI Vlan flags */ 443 #define BCM_CPRI_VLAN_FLAG_VLAN_0 0x0 444 #define BCM_CPRI_VLAN_FLAG_VLAN_1 0x1 445 446 #ifndef BCM_HIDE_DISPATCHABLE 447 448 /* Set/Get VLAN ID for the given encap entry. */ 449 extern int bcm_cpri_port_encap_roe_entry_vlan_set( 450 int unit, 451 bcm_gport_t port, 452 uint32 flags, 453 uint32 index, 454 bcm_vlan_t vlan_id); 455 456 /* Set/Get VLAN ID for the given encap entry. */ 457 extern int bcm_cpri_port_encap_roe_entry_vlan_get( 458 int unit, 459 bcm_gport_t port, 460 uint32 flags, 461 uint32 index, 462 bcm_vlan_t *vlan_id); 463 464 #endif /* BCM_HIDE_DISPATCHABLE */ 465 466 /* CPRI Packet EtherTypes */ 467 typedef enum bcm_cpri_ethertype_e { 468 bcmCpriEthertypeRoe = 0, /* EtherType RoE */ 469 bcmCpriEthertypeFast = 1, /* EtherType Fast Ethernet */ 470 bcmCpriEthertypeVlan = 2, /* EtherType VLAN */ 471 bcmCpriEthertypeQinQ = 3 /* EtherType QinQ */ 472 } bcm_cpri_ethertype_t; 473 474 #ifndef BCM_HIDE_DISPATCHABLE 475 476 /* Set/Get the EtherType for CPRI decap. */ 477 extern int bcm_cpri_port_decap_ethertype_set( 478 int unit, 479 bcm_gport_t port, 480 bcm_cpri_ethertype_t type, 481 uint16 tpid); 482 483 /* Set/Get the EtherType for CPRI decap. */ 484 extern int bcm_cpri_port_decap_ethertype_get( 485 int unit, 486 bcm_gport_t port, 487 bcm_cpri_ethertype_t type, 488 uint16 *tpid); 489 490 #endif /* BCM_HIDE_DISPATCHABLE */ 491 492 /* CPRI Decap Flow types */ 493 typedef enum bcm_cpri_decap_flow_type_e { 494 bcmCpriDecapFlowTypeIQData = 0, /* Flow Type IQ Data */ 495 bcmCpriDecapFlowTypeIQDataWithTimestamp = 1, /* Flow Type IQ Data with Timestamp */ 496 bcmCpriDecapFlowTypeControlWithOpcode = 2, /* Flow Type Control with Opcode */ 497 bcmCpriDecapFlowTypeControl = 3 /* Flow Type Control, without opcode */ 498 } bcm_cpri_decap_flow_type_t; 499 500 /* CPRI Decap Flow lookup options */ 501 typedef enum bcm_cpri_decap_flow_lookup_e { 502 bcmCpriDecapFlowLookupQueueNum = 0, /* Use Queue Number */ 503 bcmCpriDecapFlowLookupFlowID = 1, /* Use Flow ID to look up Queue number */ 504 bcmCpriDecapFlowLookupOpcode = 2 /* User Opcode to look up Queue number */ 505 } bcm_cpri_decap_flow_lookup_t; 506 507 /* CPRI Decap Flow classification information */ 508 typedef struct bcm_cpri_decap_flow_config_s { 509 bcm_cpri_decap_flow_type_t flow_type; /* Flow Type */ 510 bcm_cpri_decap_flow_lookup_t lookup_option; /* Look Up option */ 511 int queue_num; /* Queue Number */ 512 } bcm_cpri_decap_flow_config_t; 513 514 #ifndef BCM_HIDE_DISPATCHABLE 515 516 /* Configure flow classification table in CPRI decap. */ 517 extern int bcm_cpri_port_decap_flow_config_set( 518 int unit, 519 bcm_gport_t port, 520 uint8 roe_subtype, 521 bcm_cpri_decap_flow_config_t *config); 522 523 /* Configure flow classification table in CPRI decap. */ 524 extern int bcm_cpri_port_decap_flow_config_get( 525 int unit, 526 bcm_gport_t port, 527 uint8 roe_subtype, 528 bcm_cpri_decap_flow_config_t *config); 529 530 /* Configure Subtype to mapped to invalid queue to drop. */ 531 extern int bcm_cpri_port_decap_flow_config_clear( 532 int unit, 533 bcm_gport_t port, 534 uint8 roe_subtype); 535 536 #endif /* BCM_HIDE_DISPATCHABLE */ 537 538 /* CPRI Decapsulation RoE Ordering Information */ 539 typedef struct bcm_cpri_decap_roe_oi_s { 540 bcm_cpri_roe_info_type_t info_type; /* */ 541 uint32 pcnt_size; /* Number in the range 1 to 32 */ 542 uint32 pcnt_increment; /* seqNumPInc */ 543 uint32 pcnt_max; /* seqNumPMax */ 544 uint32 qcnt_size; /* Number in the range 0 to (32-pcnt) */ 545 uint32 qcnt_increment; /* seqNumQInc */ 546 uint32 qcnt_max; /* seqNumQMax */ 547 uint8 p_ext; /* Extended P Counter */ 548 uint8 gsm_tsn_bitmap; /* TSN bitmap */ 549 uint32 pcnt_pkt_count; /* Maximum pkt count described by P 550 counter */ 551 uint32 modulo_2; /* Queue Cycle Size is modulo 2 */ 552 } bcm_cpri_decap_roe_oi_t; 553 554 #ifndef BCM_HIDE_DISPATCHABLE 555 556 /* Set/Get the ordering info for Decapsulation. */ 557 extern int bcm_cpri_port_decap_roe_ordering_info_set( 558 int unit, 559 bcm_gport_t port, 560 int index, 561 bcm_cpri_decap_roe_oi_t *ordering_info); 562 563 /* Set/Get the ordering info for Decapsulation. */ 564 extern int bcm_cpri_port_decap_roe_ordering_info_get( 565 int unit, 566 bcm_gport_t port, 567 int index, 568 bcm_cpri_decap_roe_oi_t *ordering_info); 569 570 /* Set/Get sequence offset information associated with the ordering info. */ 571 extern int bcm_cpri_port_decap_roe_ordering_sequence_offset_set( 572 int unit, 573 bcm_gport_t port, 574 int queue, 575 bcm_cpri_roe_oi_seq_offset_t *seq_offset); 576 577 /* Set/Get sequence offset information associated with the ordering info. */ 578 extern int bcm_cpri_port_decap_roe_ordering_sequence_offset_get( 579 int unit, 580 bcm_gport_t port, 581 int queue, 582 bcm_cpri_roe_oi_seq_offset_t *seq_offset); 583 584 #endif /* BCM_HIDE_DISPATCHABLE */ 585 586 /* Tx TGEN configuration */ 587 typedef struct bcm_cpri_tx_frame_tgen_config_s { 588 uint32 tx_tgen_hfn; /* new hyperframe hfn number on next hyperframe */ 589 uint32 tx_tgen_bfn; /* new radio frame bfn number on next radio 590 frame */ 591 uint32 tx_tgen_bfn_sel; /* use cfg_tgen_bfn on next hyperframe or radio 592 frame */ 593 uint64 tx_tgen_ts_offset; /* start frame event after matching this offset */ 594 } bcm_cpri_tx_frame_tgen_config_t; 595 596 #ifndef BCM_HIDE_DISPATCHABLE 597 598 /* Configure tgen for port */ 599 extern int bcm_cpri_port_tx_frame_tgen_config_set( 600 int unit, 601 bcm_gport_t port, 602 int enable, 603 bcm_cpri_tx_frame_tgen_config_t *tgen_config); 604 605 #endif /* BCM_HIDE_DISPATCHABLE */ 606 607 /* RSVD4 Rx frame configuration */ 608 typedef struct bcm_rsvd4_rx_frame_config_s { 609 int speed_multiple; /* Only values 4 and 8 are supported */ 610 } bcm_rsvd4_rx_frame_config_t; 611 612 #ifndef BCM_HIDE_DISPATCHABLE 613 614 /* Set RSVD4 frame configuration */ 615 extern int bcm_cpri_port_rsvd4_rx_frame_config_set( 616 int unit, 617 bcm_gport_t port, 618 bcm_rsvd4_rx_frame_config_t *config); 619 620 /* Get RSVD4 frame configuration */ 621 extern int bcm_cpri_port_rsvd4_rx_frame_config_get( 622 int unit, 623 bcm_gport_t port, 624 bcm_rsvd4_rx_frame_config_t *config); 625 626 #endif /* BCM_HIDE_DISPATCHABLE */ 627 628 /* RSVD4 Rx Config fields */ 629 typedef enum bcm_rsvd4_rx_config_e { 630 bcmRsvd4RxConfigDescrambleEnable = 0, /* Descrambling Enable */ 631 bcmRsvd4RxConfigSyncThreshold = 1, /* Sync Threshold */ 632 bcmRsvd4RxConfigUnsyncThreshold = 2, /* Unsync Threshold */ 633 bcmRsvd4RxConfigFrameSyncThreshold = 3, /* Frame Sync Threshold */ 634 bcmRsvd4RxConfigFrameUnsyncThreshold = 4, /* Frame Unsync Threshold */ 635 bcmRsvd4RxConfigBlockSize = 5 /* Block Size */ 636 } bcm_rsvd4_rx_config_t; 637 638 /* bcm_rsvd4_rx_fsm_control_t */ 639 typedef _shr_rsvd4_rx_config_t bcm_rsvd4_rx_fsm_control_t; 640 641 /* RSVD4 RX FSM Control. */ 642 #define BCM_RSVD4_RX_FSM_CONTROL_DESCRAMBLE_ENABLE _shrRsvd4RxConfigDescrambleEnable /* Descramble Enable */ 643 #define BCM_RSVD4_RX_FSM_CONTROL_SYNC_T _shrRsvd4RxConfigSyncThreshold /* Sync Threshold. */ 644 #define BCM_RSVD4_RX_FSM_CONTROL_UNSYNC_T _shrRsvd4RxConfigUnsyncThreshold /* UnSync Threashold. */ 645 #define BCM_RSVD4_RX_FSM_CONTROL_FRAME_SYNC_T _shrRsvd4RxConfigFrameSyncThreshold /* Frame Sync Threadhold. */ 646 #define BCM_RSVD4_RX_FSM_CONTROL_FRAME_UNSYNC_T _shrRsvd4RxConfigFrameUnsyncThreshold /* Frame UnSync Threshold */ 647 #define BCM_RSVD4_RX_FSM_CONTROL_COUNT _shrRsvd4RxConfigCount /* Last Entry */ 648 649 #ifndef BCM_HIDE_DISPATCHABLE 650 651 /* Set RSVD4 Rx FSM Control and/or Configuration. */ 652 extern int bcm_cpri_port_rsvd4_rx_fsm_control_set( 653 int unit, 654 bcm_gport_t port, 655 bcm_rsvd4_rx_fsm_control_t control_type, 656 uint32 value); 657 658 /* Get RSVD4 Rx FSM Control and/or Configuration. */ 659 extern int bcm_cpri_port_rsvd4_rx_fsm_control_get( 660 int unit, 661 bcm_gport_t port, 662 bcm_rsvd4_rx_fsm_control_t control_type, 663 uint32 *value); 664 665 #endif /* BCM_HIDE_DISPATCHABLE */ 666 667 /* bcm_cpri_debug_attr_t */ 668 typedef _shr_cpri_deubg_attr_t bcm_cpri_debug_attr_t; 669 670 /* CPRI DEBUG ATTRIBUTE. */ 671 #define BCM_CPRI_DEBUG_DECAP_QUEUE_STATUS _shrCpriDeubgAttrDecapQueueStatus /* Decap Queue Status. */ 672 #define BCM_CPRI_DEBUG_ENCAP_QUEUE_STATUS _shrCpriDeubgAttrEncapQueueStatus /* Encap Queue Status. */ 673 #define BCM_CPRI_DEBUG_DECAP_QUEUE_COUNTER _shrCpriDeubgAttrEncapQueueCounter /* Decap Queue Counter. */ 674 #define BCM_CPRI_DEBUG_ENCAP_QUEUE_COUNTER _shrCpriDeubgAttrDecapQueueCounter /* Encap Queue Counter. */ 675 #define BCM_CPRI_DEBUG_DECAP_DROPPED_COUNTER _shrCpriDeubgAttrDecapDroppedCounter /* Decap Dropped Counter. */ 676 #define BCM_CPRI_DEBUG_COUNT _shrCpriDeubgAttrCount /* Last Entry */ 677 678 #ifndef BCM_HIDE_DISPATCHABLE 679 680 /* Get the value for the debug attribute. */ 681 extern int bcm_cpri_port_debug_get( 682 int unit, 683 bcm_gport_t port, 684 bcm_cpri_debug_attr_t type, 685 int index, 686 int buffer_size, 687 uint32 *data); 688 689 /* Set the value for the debug attribute. */ 690 extern int bcm_cpri_port_debug_set( 691 int unit, 692 bcm_gport_t port, 693 bcm_cpri_debug_attr_t type, 694 int index, 695 int buffer_size, 696 uint32 *data); 697 698 /* Clear the value for the debug attribute. */ 699 extern int bcm_cpri_port_debug_clear( 700 int unit, 701 bcm_gport_t port, 702 bcm_cpri_debug_attr_t type, 703 int index); 704 705 #endif /* BCM_HIDE_DISPATCHABLE */ 706 707 /* bcm_rsvd4_tx_fsm_control_t */ 708 typedef _shr_rsvd4_tx_config_t bcm_rsvd4_tx_fsm_control_t; 709 710 /* RSVD4 TX FSM Control. */ 711 #define BCM_RSVD4_TX_FSM_CONTROL_FORCE_OFF_STATE _shrRsvd4TxConfigForceOffState /* Force Off State. */ 712 #define BCM_RSVD4_TX_FSM_CONTROL_ACK_T _shrRsvd4TxConfigAckT /* Ack Threhold */ 713 #define BCM_RSVD4_TX_FSM_CONTROL_FORCE_IDLE_ACK _shrRsvd4TxConfigForcedIdleAck /* Force Idle Ack. */ 714 #define BCM_RSVD4_TX_FSM_CONTROL_LOS_ENABLE _shrRsvd4TxConfigLosEnable /* Set LOS_ENABLE config */ 715 #define BCM_RSVD4_TX_FSM_CONTROL_SCRAMBLE_ENABLE _shrRsvd4TxConfigScrambleEnable /* Scramble enable */ 716 #define BCM_RSVD4_TX_FSM_CONTROL_SCRAMBLE_SEED _shrRsvd4TxConfigScrambleSeed /* Scramble Seed */ 717 #define BCM_RSVD4_TX_FSM_CONTROL_TRANSMITTER_EN _shrRsvd4TxConfigTransmitterEnable /* TRANSMITTER_EN set */ 718 #define BCM_RSVD4_TX_FSM_CONTROL_COUNT _shrRsvd4TxConfigCount /* Last Entry */ 719 720 #ifndef BCM_HIDE_DISPATCHABLE 721 722 /* Set RSVD4 Tx FSM Control and/or Configuration. */ 723 extern int bcm_cpri_port_rsvd4_tx_fsm_control_set( 724 int unit, 725 bcm_gport_t port, 726 bcm_rsvd4_tx_fsm_control_t control_type, 727 uint32 value); 728 729 /* Get RSVD4 Tx FSM Control and/or Configuration. */ 730 extern int bcm_cpri_port_rsvd4_tx_fsm_control_get( 731 int unit, 732 bcm_gport_t port, 733 bcm_rsvd4_tx_fsm_control_t control_type, 734 uint32 *value); 735 736 /* Set RSVD4 frame configuration for debug purpose */ 737 extern int bcm_cpri_port_rsvd4_rx_frame_config_debug_set( 738 int unit, 739 bcm_gport_t port, 740 bcm_rsvd4_rx_config_t config_type, 741 uint32 value); 742 743 #endif /* BCM_HIDE_DISPATCHABLE */ 744 745 /* RSVD4 Rx FSM States */ 746 typedef enum bcm_rsvd4_rx_fsm_state_e { 747 bcmRsvd4RxFsmStateUnsync = 0, /* State Unsync */ 748 bcmRsvd4RxFsmStateWaitForSeed = 1, /* State Wait For Seed */ 749 bcmRsvd4RxFsmStateWaitForAck = 2, /* State Wait For Seed */ 750 bcmRsvd4RxFsmStateWaitForK28p7Idles = 3, /* State Wait for K28.7 Idles */ 751 bcmRsvd4RxFsmStateWaitForFrameSync = 4, /* State Wait for Frame Sync */ 752 bcmRsvd4RxFsmStateFrameSync = 5 /* State Frame Sync */ 753 } bcm_rsvd4_rx_fsm_state_t; 754 755 #ifndef BCM_HIDE_DISPATCHABLE 756 757 /* To set the RSVD4 state machine to a particular state for debug purpose */ 758 extern int bcm_cpri_port_rsvd4_rx_fsm_state_set( 759 int unit, 760 bcm_gport_t port, 761 bcm_rsvd4_rx_fsm_state_t state); 762 763 #endif /* BCM_HIDE_DISPATCHABLE */ 764 765 /* RSVD4 Rx FSM Override parameters */ 766 typedef enum bcm_rsvd4_rx_params_e { 767 bcmRsvd4RxParams_Frame_Unsync_T_Invalid_MG_Rcvd = 0, /* Frame Unsync Threshold */ 768 bcmRsvd4RxParams_Frame_Sync_T_Valid_MG_Rcvd = 1, /* Frame Sync Threshold */ 769 bcmRsvd4RxParams_K_MG_Idles_Rcvd = 2, /* K Frame Received */ 770 bcmRsvd4RxParams_Idle_Req_Rcvd = 3, /* Idle Request Received */ 771 bcmRsvd4RxParams_Idle_Ack_Rcvd = 4, /* Idle Ack Received */ 772 bcmRsvd4RxParams_SeedCapAndVerifyDone = 5 /* Seed Capture and Verify Done */ 773 } bcm_rsvd4_rx_params_t; 774 775 #ifndef BCM_HIDE_DISPATCHABLE 776 777 /* To set the RSVD4 state machine to a particular state for debug purpose */ 778 extern int bcm_cpri_port_rsvd4_rx_override_set( 779 int unit, 780 bcm_gport_t port, 781 bcm_rsvd4_rx_params_t parameter, 782 int enable, 783 int value); 784 785 #endif /* BCM_HIDE_DISPATCHABLE */ 786 787 /* bcm_rsvd4_msg_ts_mode_t */ 788 typedef _shr_rsvd4_msg_ts_mode_t bcm_rsvd4_msg_ts_mode_t; 789 790 /* RSVD4 TS MSG Modes. */ 791 #define BCM_RSVD4_MSG_TSMODE_WCDMA _shrRsvd4MsgTsModeWCDMA /* Msg Timestamp WCDMA mode */ 792 #define BCM_RSVD4_MSG_TSMODE_LTE _shrRsvd4MsgTsModeLTE /* Msg Timestamp LTE mode */ 793 #define BCM_RSVD4_MSG_TSMODE_GSM_DL _shrRsvd4MsgTsModeGSMDL /* Msg Timestamp GSM DL mode */ 794 #define BCM_RSVD4_MSG_TSMODE_GSM_UL _shrRsvd4MsgTsModeGSMUL /* Msg Timestamp GSM UL mode */ 795 796 /* bcm_rsvd4_sync_mode_t */ 797 typedef _shr_rsvd4_sync_mode_t bcm_rsvd4_sync_mode_t; 798 799 /* RSVD4 Frame Sync Modes. */ 800 #define BCM_RSVD4_SYNC_MODE_NO_SYNC _shrRsvd4SyncModeNoSync /* Sync On any message */ 801 #define BCM_RSVD4_SYNC_MODE_MSG_AND_MASTER_FRAME_OFFSET _shrRsvd4SyncModeMsgAndMasterFrameOffset /* Sync On Master Frame 802 and Msg Offset */ 803 #define BCM_RSVD4_SYNC_MODE_TS_NO_SYNC _shrRsvd4SyncModeTsNoSync /* Sync On any message 804 timestamp, GSM Only */ 805 #define BCM_RSVD4_SYNC_MODE_TS_MSG_AND_MASTER_FRAME_OFFSET _shrRsvd4SyncModeTsMsgAndMasterFrameOffset /* Sync On Master Frame 806 And Msg Offset 807 timestamp, GSM Only */ 808 809 /* RSVD4 Rx Flow configuration */ 810 typedef struct bcm_rsvd4_rx_flow_info_s { 811 uint32 mask; /* header mask */ 812 uint32 match_data; /* header data to match */ 813 uint16 payload_size; /* payload size in bits */ 814 uint16 last_payload_index; /* last payload index */ 815 bcm_rsvd4_msg_ts_mode_t msg_ts_mode; /* Msg timestamp mode */ 816 bcm_rsvd4_sync_mode_t sync_mode; /* Sync Mode */ 817 uint16 stuffing_count; /* Stuffing Count */ 818 uint32 message_number_offset; /* Message number Offset for Sync */ 819 uint16 master_frame_offset; /* Master Frame Offset for Sync */ 820 uint16 msg_ts_count; /* Msg timestamp Count */ 821 uint16 container_blk_count; /* Container Block Count */ 822 uint8 priority; /* Priority */ 823 uint32 queue_size; /* Queue Size in bytes. */ 824 uint8 gsm_pad_size; /* GSM Pad Size */ 825 uint8 gsm_extra_pad_size; /* GSM Extra Pad size */ 826 uint8 gsm_pad_en; /* GSM Pad Enable */ 827 uint8 gsm_ctrl_loc; /* GSM control location */ 828 uint32 axc_id; /* AxC ID */ 829 uint32 last_payload_size; /* last Payload size */ 830 uint8 gsm_tsn_bitmap; /* GSM TSN bitmap */ 831 } bcm_rsvd4_rx_flow_info_t; 832 833 #ifndef BCM_HIDE_DISPATCHABLE 834 835 /* Add RSVD4 Rx Flow data AxC */ 836 extern int bcm_cpri_port_rsvd4_rx_flow_add( 837 int unit, 838 bcm_gport_t port, 839 int flow_id, 840 bcm_rsvd4_rx_flow_info_t *flow_info); 841 842 /* Delete RSVD4 Rx Flow data AxC */ 843 extern int bcm_cpri_port_rsvd4_rx_flow_delete( 844 int unit, 845 bcm_gport_t port, 846 int flow_id); 847 848 /* Set RSVD4 Rx master frame sync information */ 849 extern int bcm_cpri_port_rsvd4_rx_bfn_sync_config_set( 850 int unit, 851 bcm_gport_t port, 852 uint16 master_frame_count, 853 uint64 master_frame_start); 854 855 #endif /* BCM_HIDE_DISPATCHABLE */ 856 857 /* RSVD4 Frame Synchronization Info. */ 858 typedef struct bcm_rsvd4_frame_sync_info_s { 859 uint32 master_frame_number; /* RSVD4 Master Frame Number */ 860 } bcm_rsvd4_frame_sync_info_t; 861 862 #ifndef BCM_HIDE_DISPATCHABLE 863 864 /* Get RSVD4 Rx current frame sync info */ 865 extern int bcm_cpri_port_rsvd4_rx_current_frame_sync_info_get( 866 int unit, 867 bcm_gport_t port, 868 bcm_rsvd4_frame_sync_info_t *frame_sync_info); 869 870 /* Get RSVD4 Tx current frame sync info */ 871 extern int bcm_cpri_port_rsvd4_tx_current_frame_sync_info_get( 872 int unit, 873 bcm_gport_t port, 874 bcm_rsvd4_frame_sync_info_t *frame_sync_info); 875 876 #endif /* BCM_HIDE_DISPATCHABLE */ 877 878 /* RSVD4 Tx frame configuration */ 879 typedef struct bcm_rsvd4_tx_frame_config_s { 880 uint8 los_enable; /* LOS enable */ 881 uint8 rsvd4_scrambler_seed; /* RSVD4 scrambler seed */ 882 int speed_multiple; /* Only values 4 and 8 are supported */ 883 } bcm_rsvd4_tx_frame_config_t; 884 885 #ifndef BCM_HIDE_DISPATCHABLE 886 887 /* RSVD4 Tx frame configuration */ 888 extern int bcm_cpri_port_rsvd4_tx_frame_config_set( 889 int unit, 890 bcm_gport_t port, 891 bcm_rsvd4_tx_frame_config_t *config); 892 893 /* RSVD4 Tx frame configuration get */ 894 extern int bcm_cpri_port_rsvd4_tx_frame_config_get( 895 int unit, 896 bcm_gport_t port, 897 bcm_rsvd4_tx_frame_config_t *config); 898 899 #endif /* BCM_HIDE_DISPATCHABLE */ 900 901 /* RSVD4 Tx Config fields */ 902 typedef enum bcm_rsvd4_tx_config_e { 903 bcmRsvd4TxConfigForceOffState = 0, /* Force Off State */ 904 bcmRsvd4TxConfigAckT = 1, /* Ack T */ 905 bcmRsvd4TxConfigForceIdleAck = 2, /* Force Idle Ack */ 906 bcmRsvd4TxConfigLosEnable = 3, /* LOS Enable */ 907 bcmRsvd4TxConfigScrambleEnable = 4, /* Scrambling Enable */ 908 bcmRsvd4TxConfigScrambleSeed = 5, /* Scrambling Seed */ 909 bcmRsvd4TxConfigTransmitterEnable = 6 /* Transmitter Enable */ 910 } bcm_rsvd4_tx_config_t; 911 912 #ifndef BCM_HIDE_DISPATCHABLE 913 914 /* Set RSVD4 Tx frame configuration for debug purpose */ 915 extern int bcm_cpri_port_rsvd4_tx_frame_config_debug_set( 916 int unit, 917 bcm_gport_t port, 918 bcm_rsvd4_tx_config_t config_type, 919 uint32 value); 920 921 #endif /* BCM_HIDE_DISPATCHABLE */ 922 923 /* RSVD4 Tx FSM States */ 924 typedef enum bcm_rsvd4_tx_fsm_state_e { 925 bcmRsvd4TxFsmStateOff = 0, /* State Off */ 926 bcmRsvd4TxFsmStateIdle = 1, /* State Idle */ 927 bcmRsvd4TxFsmStateIdleReq = 2, /* State Idle request */ 928 bcmRsvd4TxFsmStateIdleAck = 3, /* State Idle Acknowledge */ 929 bcmRsvd4TxFsmStateFrameTx = 4 /* State frame Tx */ 930 } bcm_rsvd4_tx_fsm_state_t; 931 932 #ifndef BCM_HIDE_DISPATCHABLE 933 934 /* To set the RSVD4 state machine to a particular state for debug purpose */ 935 extern int bcm_cpri_port_rsvd4_tx_fsm_state_set( 936 int unit, 937 bcm_gport_t port, 938 bcm_rsvd4_tx_fsm_state_t state); 939 940 #endif /* BCM_HIDE_DISPATCHABLE */ 941 942 /* RSVD4 Tx override parameteres for debug purpose */ 943 typedef enum bcm_rsvd4_tx_params_e { 944 bcmRsvd4TxParams_StartTx = 0, /* Start Tx */ 945 bcmRsvd4TxParams_PCS_Ack_CAP = 1, /* PCS Ack */ 946 bcmRsvd4TxParams_PCS_Idle_REQ = 2, /* PCS Idle Req */ 947 bcmRsvd4TxParams_PCS_SCR_Lock = 3, /* PCS SCR locked */ 948 bcmRsvd4TxParams_LOS_Status = 4 /* LOS Status */ 949 } bcm_rsvd4_tx_params_t; 950 951 #ifndef BCM_HIDE_DISPATCHABLE 952 953 /* To set the RSVD4 state machine to a particular state for debug purpose */ 954 extern int bcm_cpri_port_rsvd4_tx_override_set( 955 int unit, 956 bcm_gport_t port, 957 bcm_rsvd4_tx_params_t parameter, 958 int enable, 959 int value); 960 961 #endif /* BCM_HIDE_DISPATCHABLE */ 962 963 /* RSVD4 Tx Flow configuration */ 964 typedef struct bcm_rsvd4_tx_flow_info_s { 965 int axc_id; /* axc_id */ 966 uint16 stuffing_count; /* Stuffing Count */ 967 uint32 message_number_offset; /* Msg Number Offset for Sync */ 968 uint16 master_frame_offset; /* Master Frame number offset for Sync */ 969 uint32 container_blk_count; /* Container Block Count */ 970 uint16 message_addr; /* Message Address */ 971 uint32 msg_ts_offset; /* Msg Timestamp Offset */ 972 bcm_rsvd4_msg_ts_mode_t msg_ts_mode; /* Msg Timestamp Mode */ 973 uint8 message_type; /* Message Type */ 974 bcm_rsvd4_sync_mode_t sync_mode; /* Sync Mode */ 975 uint16 msg_ts_count; /* Msg Timestamp Count */ 976 uint8 index_to_secondary_dbm; /* index to secondary DBM */ 977 uint8 secondary_dbm_enable; /* Secondary DBM enable */ 978 uint8 num_active_slot; /* number of active slot */ 979 uint16 payload_size; /* payload size in bits */ 980 uint16 last_payload_size; /* last payload size */ 981 uint8 last_index; /* last payload index */ 982 uint8 pad_enable; 983 uint8 pad_size; /* pad size */ 984 uint8 extra_pad_size; /* extra pad size */ 985 uint8 cycle_size; /* Jitter buffer size in number of 986 packets */ 987 uint32 buffer_size; /* Packet size in bytes */ 988 uint8 gsm_ctrl_loc; /* GSM control location */ 989 } bcm_rsvd4_tx_flow_info_t; 990 991 #ifndef BCM_HIDE_DISPATCHABLE 992 993 /* Add RSVD4 Tx Flow data AxC */ 994 extern int bcm_cpri_port_rsvd4_tx_flow_add( 995 int unit, 996 bcm_gport_t port, 997 int flow_id, 998 bcm_rsvd4_tx_flow_info_t *flow_info); 999 1000 /* Delete a RSVD4 Tx Flow data AxC */ 1001 extern int bcm_cpri_port_rsvd4_tx_flow_delete( 1002 int unit, 1003 bcm_gport_t port, 1004 int flow_id); 1005 1006 #endif /* BCM_HIDE_DISPATCHABLE */ 1007 1008 /* RSVD4 dual bitmap entry */ 1009 typedef struct bcm_rsvd4_dbm_entry_s { 1010 uint8 bm1_multiple; /* Bit Map 1 Multiple */ 1011 uint32 bm1[3]; /* Bit Map 1 */ 1012 uint8 bm1_size; /* Bit Map 1 size */ 1013 uint32 bm2[2]; /* Bit Map 2 */ 1014 uint8 bm2_size; /* Bit map 2 size */ 1015 uint8 num_slots; /* number of slot for Each bit map */ 1016 uint8 pos_index; /* Position Index */ 1017 uint8 pos_entries; /* Number of Position Table Entries */ 1018 } bcm_rsvd4_dbm_entry_t; 1019 1020 #ifndef BCM_HIDE_DISPATCHABLE 1021 1022 /* Set/Get up a DBM entry */ 1023 extern int bcm_cpri_port_rsvd4_dbm_entry_set( 1024 int unit, 1025 bcm_gport_t port, 1026 int index, 1027 bcm_rsvd4_dbm_entry_t *entry); 1028 1029 /* Set/Get up a DBM entry */ 1030 extern int bcm_cpri_port_rsvd4_dbm_entry_get( 1031 int unit, 1032 bcm_gport_t port, 1033 int index, 1034 bcm_rsvd4_dbm_entry_t *entry); 1035 1036 /* Clear a DBM entry */ 1037 extern int bcm_cpri_port_rsvd4_dbm_entry_clear( 1038 int unit, 1039 bcm_gport_t port, 1040 int index); 1041 1042 #endif /* BCM_HIDE_DISPATCHABLE */ 1043 1044 /* RSVD4 Secondary dual bitmap entry */ 1045 typedef struct bcm_rsvd4_secondary_dbm_entry_s { 1046 uint8 bm1_multiple; /* Bit Map 1 multiple */ 1047 uint8 bm1; /* Bit Map 1 */ 1048 uint8 bm1_size; /* Bit Map 1 size */ 1049 uint8 bm2; /* Bit Map 2 */ 1050 uint8 bm2_size; /* Bit Map 2 Size */ 1051 uint8 num_slots; /* Number of Slots for each Bit */ 1052 } bcm_rsvd4_secondary_dbm_entry_t; 1053 1054 #ifndef BCM_HIDE_DISPATCHABLE 1055 1056 /* Set/Get up a secondary DBM entry */ 1057 extern int bcm_cpri_port_rsvd4_secondary_dbm_entry_set( 1058 int unit, 1059 bcm_gport_t port, 1060 int index, 1061 bcm_rsvd4_secondary_dbm_entry_t *entry); 1062 1063 /* Set/Get up a secondary DBM entry */ 1064 extern int bcm_cpri_port_rsvd4_secondary_dbm_entry_get( 1065 int unit, 1066 bcm_gport_t port, 1067 int index, 1068 bcm_rsvd4_secondary_dbm_entry_t *entry); 1069 1070 /* Clear a Secondary DBM entry */ 1071 extern int bcm_cpri_port_rsvd4_secondary_dbm_entry_clear( 1072 int unit, 1073 bcm_gport_t port, 1074 int index); 1075 1076 #endif /* BCM_HIDE_DISPATCHABLE */ 1077 1078 /* CPRI Flow types */ 1079 typedef enum bcm_cpri_flow_type_e { 1080 bcmCpriFlowTypeData = 0, /* Data Flow Type */ 1081 bcmCpriFlowTypeCtrl = 1, /* Control Flow Type */ 1082 bcmCpriFlowTypeCount = 2 /* Should be last */ 1083 } bcm_cpri_flow_type_t; 1084 1085 /* CPRI dbm position table entry */ 1086 typedef struct bcm_cpri_dbm_position_entry_s { 1087 uint8 valid; /* Valid */ 1088 uint8 flow_id; /* Flow id */ 1089 bcm_cpri_flow_type_t flow_type; /* Flow type - Data or Ctrl */ 1090 uint8 index; /* X slot position , 0 to (Num_slot-1) */ 1091 } bcm_cpri_dbm_position_entry_t; 1092 1093 /* CPRI transmission rule types */ 1094 typedef enum bcm_cpri_tx_rule_type_e { 1095 bcmCpriTxRuleTypeData = 0, /* Tx Rule type Data */ 1096 bcmCpriTxRuleTypeCtrl = 1, /* Tx Rule Type Control */ 1097 bcmCpriTxRuleTypeCount = 2 /* Should be last */ 1098 } bcm_cpri_tx_rule_type_t; 1099 1100 /* CPRI modulo rule types */ 1101 typedef enum bcm_cpri_modulo_rule_mod_e { 1102 bcmCpriModuloRuleMod1 = 0, /* Modulo 1 */ 1103 bcmCpriModuloRuleMod2 = 1, /* Modulo 2 */ 1104 bcmCpriModuloRuleMod4 = 2, /* Module 4 */ 1105 bcmCpriModuloRuleMod8 = 3, /* Modulo 8 */ 1106 bcmCpriModuloRuleMod16 = 4, /* Modulo 16 */ 1107 bcmCpriModuloRuleMod32 = 5, /* Modulo 32 */ 1108 bcmCpriModuloRuleMod64 = 6, /* Modulo 64 */ 1109 bcmCpriModuloRuleModCount = 7 /* Should be last */ 1110 } bcm_cpri_modulo_rule_mod_t; 1111 1112 /* CPRI modulo rule entry */ 1113 typedef struct bcm_cpri_modulo_rule_entry_s { 1114 uint8 active; /* Entry is active */ 1115 bcm_cpri_modulo_rule_mod_t modulo_value; /* Modulo value */ 1116 uint8 modulo_index; /* Modulo index */ 1117 uint8 dbm_enable; /* Dual bitmap rule is enabled */ 1118 uint8 dbm_dbm_id; /* Flow Id or DBM profile ID if dbm is 1119 enabled */ 1120 bcm_cpri_flow_type_t flow_type; /* Flow type - Data or Ctrl */ 1121 } bcm_cpri_modulo_rule_entry_t; 1122 1123 #ifndef BCM_HIDE_DISPATCHABLE 1124 1125 /* Set/Get the tx rsvd4 modulo rule entry. */ 1126 extern int bcm_cpri_port_rsvd4_tx_modulo_rule_entry_set( 1127 int unit, 1128 bcm_gport_t port, 1129 uint32 modulo_rule_num, 1130 bcm_cpri_tx_rule_type_t modulo_rule_type, 1131 bcm_cpri_modulo_rule_entry_t *modulo_rule); 1132 1133 /* Set/Get the tx rsvd4 modulo rule entry. */ 1134 extern int bcm_cpri_port_rsvd4_tx_modulo_rule_entry_get( 1135 int unit, 1136 bcm_gport_t port, 1137 uint32 modulo_rule_num, 1138 bcm_cpri_tx_rule_type_t modulo_rule_type, 1139 bcm_cpri_modulo_rule_entry_t *modulo_rule); 1140 1141 /* Set/Get the tx rsvd4 position entry. */ 1142 extern int bcm_cpri_port_rsvd4_tx_position_entry_set( 1143 int unit, 1144 bcm_gport_t port, 1145 uint32 pos_index, 1146 bcm_cpri_dbm_position_entry_t *pos_entry); 1147 1148 /* Set/Get the tx rsvd4 position entry. */ 1149 extern int bcm_cpri_port_rsvd4_tx_position_entry_get( 1150 int unit, 1151 bcm_gport_t port, 1152 uint32 pos_index, 1153 bcm_cpri_dbm_position_entry_t *pos_entry); 1154 1155 /* Set/Get decap flow to queue mapping. */ 1156 extern int bcm_cpri_port_decap_flow_to_queue_mapping_set( 1157 int unit, 1158 bcm_gport_t port, 1159 uint32 flow_id, 1160 uint32 queue_num); 1161 1162 /* Set/Get decap flow to queue mapping. */ 1163 extern int bcm_cpri_port_decap_flow_to_queue_mapping_get( 1164 int unit, 1165 bcm_gport_t port, 1166 uint32 flow_id, 1167 uint32 *queue_num); 1168 1169 /* Remapped the flow to invalid queue. */ 1170 extern int bcm_cpri_port_decap_flow_to_queue_mapping_clear( 1171 int unit, 1172 bcm_gport_t port, 1173 uint32 flow_id); 1174 1175 /* Set/Get decap queue to ordering info index. */ 1176 extern int bcm_cpri_port_decap_queue_to_ordering_info_index_set( 1177 int unit, 1178 bcm_gport_t port, 1179 uint32 queue_num, 1180 uint32 ordering_info_index); 1181 1182 /* Set/Get decap queue to ordering info index. */ 1183 extern int bcm_cpri_port_decap_queue_to_ordering_info_index_get( 1184 int unit, 1185 bcm_gport_t port, 1186 uint32 queue_num, 1187 uint32 *ordering_info_index); 1188 1189 #endif /* BCM_HIDE_DISPATCHABLE */ 1190 1191 /* bcm_rsvd4_control_msg_proc_type_t */ 1192 typedef _shr_rsvd4_control_msg_proc_type_t bcm_rsvd4_control_msg_proc_type_t; 1193 1194 /* RSVD4 Control Message Processing Type. */ 1195 #define BCM_RSVD4_CONTROL_MSG_PROC_ETH _shrRsvd4CtrlMsgProcFE /* Multi Message Fast 1196 Ethernet. */ 1197 #define BCM_RSVD4_CONTROL_MSG_PROC_FCB _shrRsvd4CtrlMsgProcFE /* FCB. */ 1198 #define BCM_RSVD4_CONTROL_MSG_PROC_PAYLOAD _shrRsvd4CtrlMsgProcPayload /* Message Payload 1199 Extraction. */ 1200 #define BCM_RSVD4_CONTROL_MSG_PROC_FULL _shrRsvd4CtrlMsgProcFull /* Full Message. */ 1201 #define BCM_RSVD4_CONTROL_MSG_PROC_FULL_WITH_TAG _shrRsvd4CtrlMsgProcFullWithTag /* Full Message with Tag. */ 1202 1203 /* RSVD4 control flow configuration */ 1204 typedef struct bcm_rsvd4_control_flow_config_s { 1205 uint32 match_mask; /* Header Mask */ 1206 uint32 match_data; /* Header Match Data */ 1207 uint8 queue_num; /* Queue number */ 1208 bcm_rsvd4_control_msg_proc_type_t type; /* Message process type */ 1209 int sync_en; /* sync profile enable */ 1210 uint8 sync_profile; /* sync profile number */ 1211 uint8 priority; /* 0-3 */ 1212 uint32 queue_size; /* in bytes */ 1213 } bcm_rsvd4_control_flow_config_t; 1214 1215 #ifndef BCM_HIDE_DISPATCHABLE 1216 1217 /* Add/Delete control message flow. */ 1218 extern int bcm_cpri_port_rsvd4_rx_control_flow_add( 1219 int unit, 1220 int port, 1221 int control_flow_id, 1222 bcm_rsvd4_control_flow_config_t *config); 1223 1224 /* Add/Delete control message flow. */ 1225 extern int bcm_cpri_port_rsvd4_rx_control_flow_delete( 1226 int unit, 1227 int port, 1228 int control_flow_id, 1229 bcm_rsvd4_control_flow_config_t *control_flow_cfg); 1230 1231 #endif /* BCM_HIDE_DISPATCHABLE */ 1232 1233 /* bcm_rsvd4_fast_eth_config_info_t */ 1234 typedef struct bcm_rsvd4_fast_eth_config_info_s { 1235 uint32 queue_num; /* Queue Number */ 1236 int no_fcs_err_check; /* Ignore FCS Error */ 1237 uint32 min_packet_size; /* Minimum packet size */ 1238 uint32 max_packet_size; /* Maximum Packet Size */ 1239 int min_packet_drop; /* Enable drop of Packet size below min packet size */ 1240 int max_packet_drop; /* Enable drop of Packet size above max packet 1241 size */ 1242 int strip_crc; /* Strip CRC */ 1243 } bcm_rsvd4_fast_eth_config_info_t; 1244 1245 #ifndef BCM_HIDE_DISPATCHABLE 1246 1247 /* Setup the fast Ethernet control flow. */ 1248 extern int bcm_cpri_port_rsvd4_cm_fast_eth_config_set( 1249 int unit, 1250 int port, 1251 int control_flow_id, 1252 bcm_rsvd4_fast_eth_config_info_t *config); 1253 1254 #endif /* BCM_HIDE_DISPATCHABLE */ 1255 1256 /* bcm_rsvd4_sync_count_cycle_t */ 1257 typedef _shr_rsvd4_sync_count_cycle_t bcm_rsvd4_sync_count_cycle_t; 1258 1259 /* RSVD4 Sync Count Cycle. */ 1260 #define BCM_RSVD4_SYNC_COUNT_EVERY_MF _shrRsvd4SyncCountCycleEveryMF 1261 #define BCM_RSVD4_SYNC_COUNT_UPTO_SIX_MF _shrRsvd4SyncCountCycleUpToSixMF 1262 1263 /* */ 1264 typedef struct bcm_rsvd4_sync_profile_entry_s { 1265 uint32 master_frame_offset; /* Master frame Offset */ 1266 uint32 message_offset; /* Message Number Offset */ 1267 bcm_rsvd4_sync_count_cycle_t count_cycle; /* Count Cycle */ 1268 } bcm_rsvd4_sync_profile_entry_t; 1269 1270 #ifndef BCM_HIDE_DISPATCHABLE 1271 1272 /* Configure/Retrieve sync profile entry. */ 1273 extern int bcm_cpri_port_rsvd4_sync_profile_entry_set( 1274 int unit, 1275 int port, 1276 int index, 1277 bcm_rsvd4_sync_profile_entry_t *config); 1278 1279 /* Configure/Retrieve sync profile entry. */ 1280 extern int bcm_cpri_port_rsvd4_sync_profile_entry_get( 1281 int unit, 1282 int port, 1283 int index, 1284 bcm_rsvd4_sync_profile_entry_t *config); 1285 1286 #endif /* BCM_HIDE_DISPATCHABLE */ 1287 1288 /* Tag Generation Entry information. */ 1289 typedef struct bcm_cpri_tag_gen_entry_s { 1290 uint32 tag_id; /* Tag ID */ 1291 uint32 mask; /* Mask */ 1292 uint32 header; /* Header Info */ 1293 uint32 word_count; /* Word Count, Only for RTWP` */ 1294 } bcm_cpri_tag_gen_entry_t; 1295 1296 /* RSVD4 Control flow group */ 1297 typedef enum bcm_rsvd4_control_group_id_e { 1298 bcmRsvd4ControlGroupId0 = 0, /* RSVD4 Control Flow Group 0 */ 1299 bcmRsvd4ControlGroupId1 = 1 /* RSVD4 Control Flow Group 1 */ 1300 } bcm_rsvd4_control_group_id_t; 1301 1302 /* RSVD4 Slot Type */ 1303 typedef enum bcm_rsvd4_slot_type_e { 1304 bcmRsvd4SlotData = 0, /* RSVD4 Slot Type Data */ 1305 bcmRsvd4SlotControl = 1 /* RSVD4 Slot Type Control */ 1306 } bcm_rsvd4_slot_type_t; 1307 1308 /* RSVD4 Priority */ 1309 typedef enum bcm_rsvd4_priority_e { 1310 bcmRsvd4Priority0 = 0, /* RSVD4 Priority 0 */ 1311 bcmRsvd4Priority1 = 1, /* RSVD4 Priority 1 */ 1312 bcmRsvd4Priority2 = 2, /* RSVD4 Priority 2 */ 1313 bcmRsvd4Priority3 = 3 /* RSVD4 Priority 3 */ 1314 } bcm_rsvd4_priority_t; 1315 1316 /* RSVD4 Control flow configuration */ 1317 typedef struct bcm_rsvd4_tx_control_flow_group_config_s { 1318 uint8 queue_num; /* Queue Number */ 1319 bcm_rsvd4_control_msg_proc_type_t type; /* Process type */ 1320 bcm_rsvd4_priority_t priority; /* Queue priority */ 1321 } bcm_rsvd4_tx_control_flow_group_config_t; 1322 1323 #ifndef BCM_HIDE_DISPATCHABLE 1324 1325 /* Add/Delete flow to/from rsvd4 tx control group. */ 1326 extern int bcm_cpri_port_rsvd4_tx_control_flow_group_member_add( 1327 int unit, 1328 int port, 1329 bcm_rsvd4_control_group_id_t group_num, 1330 bcm_rsvd4_tx_control_flow_group_config_t *config); 1331 1332 /* Add/Delete flow to/from rsvd4 tx control group. */ 1333 extern int bcm_cpri_port_rsvd4_tx_control_flow_group_member_delete( 1334 int unit, 1335 int port, 1336 bcm_rsvd4_control_group_id_t group_num, 1337 bcm_rsvd4_priority_t priority); 1338 1339 #endif /* BCM_HIDE_DISPATCHABLE */ 1340 1341 /* */ 1342 typedef struct bcm_rsvd4_tx_cm_eth_config_s { 1343 uint8 msg_node; /* Message Node */ 1344 uint8 msg_subnode; /* Message Subnode */ 1345 uint8 msg_type; /* Message Type */ 1346 uint8 msg_padding; /* Message Padding */ 1347 } bcm_rsvd4_tx_cm_eth_config_t; 1348 1349 #ifndef BCM_HIDE_DISPATCHABLE 1350 1351 /* Configure the rsvd4 tx fast Ethernet control. */ 1352 extern int bcm_cpri_port_rsvd4_tx_cm_eth_config_set( 1353 int unit, 1354 int port, 1355 bcm_rsvd4_tx_cm_eth_config_t *config); 1356 1357 #endif /* BCM_HIDE_DISPATCHABLE */ 1358 1359 /* RSVD4 Tx control message raw configuration */ 1360 typedef struct bcm_rsvd4_tx_cm_raw_config_s { 1361 uint8 msg_id; /* Message ID */ 1362 uint8 msg_type; /* Message Type */ 1363 } bcm_rsvd4_tx_cm_raw_config_t; 1364 1365 #ifndef BCM_HIDE_DISPATCHABLE 1366 1367 /* Configure the rsvd4 tx raw control message. */ 1368 extern int bcm_cpri_port_rsvd4_tx_cm_raw_config_set( 1369 int unit, 1370 int port, 1371 bcm_rsvd4_tx_cm_raw_config_t *config); 1372 1373 #endif /* BCM_HIDE_DISPATCHABLE */ 1374 1375 /* RSVD4 tx control flow configuration */ 1376 typedef struct bcm_rsvd4_tx_control_flow_config_s { 1377 uint8 queue_num; /* Queue Number */ 1378 uint8 crc_mode; /* crc mode for multi eth control axc */ 1379 uint32 cycle_size; /* cycle size of control axc for buffer 1380 allocation */ 1381 uint32 queue_size; /* queue size of control axc */ 1382 bcm_rsvd4_control_msg_proc_type_t type; /* Message processing type */ 1383 } bcm_rsvd4_tx_control_flow_config_t; 1384 1385 #ifndef BCM_HIDE_DISPATCHABLE 1386 1387 /* Add tx rsvd4 control flow. */ 1388 extern int bcm_cpri_port_rsvd4_tx_control_flow_add( 1389 int unit, 1390 int port, 1391 int control_flow_id, 1392 bcm_rsvd4_tx_control_flow_config_t *config); 1393 1394 #endif /* BCM_HIDE_DISPATCHABLE */ 1395 1396 /* RSVD4 Control Message tunnel CRC options */ 1397 typedef _shr_rsvd4_crc_option_t bcm_rsvd4_cm_tunnel_crc_option_t; 1398 1399 /* RSVD4 Control Message tunnel CRC options. */ 1400 #define BCM_RSVD4_CM_TUNNEL_CRC_USE_ROE _shrRsvd4CrcOptionUseRoe /* Use CRC from ROE 1401 packet. */ 1402 #define BCM_RSVD4_CM_TUNNEL_CRC_REGENERATE _shrRsvd4CrcOptionRegenerate /* Regenerate New CRC */ 1403 1404 #ifndef BCM_HIDE_DISPATCHABLE 1405 1406 /* Set tx rsvd4 tunnel control message crc option. */ 1407 extern int bcm_cpri_port_rsvd4_tx_cm_tunnel_crc_config_set( 1408 int unit, 1409 int port, 1410 bcm_rsvd4_cm_tunnel_crc_option_t crc_option); 1411 1412 #endif /* BCM_HIDE_DISPATCHABLE */ 1413 1414 /* RSVD4 control message header config */ 1415 typedef struct bcm_rsvd4_tx_cm_hdr_entry_s { 1416 uint8 rsvd4_header_node; /* Message Header Node */ 1417 uint8 rsvd4_header_subnode; /* Message Header subnode */ 1418 uint8 rsvd4_control_payload_node; /* Control Payload node */ 1419 } bcm_rsvd4_tx_cm_hdr_entry_t; 1420 1421 #ifndef BCM_HIDE_DISPATCHABLE 1422 1423 /* Configure rsvd4 tx control message header. */ 1424 extern int bcm_cpri_port_rsvd4_tx_cm_hdr_config_entry_set( 1425 int unit, 1426 int port, 1427 int index, 1428 bcm_rsvd4_tx_cm_hdr_entry_t *entry); 1429 1430 /* Configure rsvd4 tx control message header look up set. */ 1431 extern int bcm_cpri_port_rsvd4_tx_cm_hdr_lkup_entry_set( 1432 int unit, 1433 int port, 1434 int flow_id, 1435 int header_index); 1436 1437 #endif /* BCM_HIDE_DISPATCHABLE */ 1438 1439 /* bcm_cpri_crc_mode_t */ 1440 typedef _shr_cpri_hdlc_crc_mode_t bcm_cpri_crc_mode_t; 1441 1442 /* bcm_cpri_hdlc_flag_size_t */ 1443 typedef _shr_cpri_hdlc_flag_size_t bcm_cpri_hdlc_flag_size_t; 1444 1445 /* cpri_cw_filter_mode_t */ 1446 typedef _shr_cpri_cw_filter_mode_t bcm_cpri_cw_filter_mode_t; 1447 1448 /* bcm_cpri_hdlc_filling_pattern_t */ 1449 typedef _shr_cpri_hdlc_filling_flag_pattern_t bcm_cpri_hdlc_filling_pattern_t; 1450 1451 /* bcm_cpri_gcw_mask_t */ 1452 typedef _shr_cpri_gcw_mask_t bcm_cpri_gcw_mask_t; 1453 1454 /* bcm_cpri_l1_signal_prot_map_t */ 1455 typedef _shr_cpri_l1_signal_prot_map_t bcm_cpri_l1_signal_prot_map_t; 1456 1457 /* Use on l1 signal protection API.. */ 1458 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_LOF _SHR_L1_SIGNAL_PROT_MAP_LOF /* Select/Add LOF bit. */ 1459 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_LOS _SHR_L1_SIGNAL_PROT_MAP_LOS /* Select/Add LOS bit. */ 1460 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_SDI _SHR_L1_SIGNAL_PROT_MAP_SDI /* Select/Add SDI bit. */ 1461 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_RAI _SHR_L1_SIGNAL_PROT_MAP_RAI /* Select/Add RAI bit. */ 1462 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_RESET _SHR_L1_SIGNAL_PROT_MAP_RESET /* Select/Add RESET bit. */ 1463 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_ETH_PTR _SHR_L1_SIGNAL_PROT_MAP_ETH_PTR /* Select/Add ETH_PTR 1464 bit. */ 1465 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_HDLC_RATE _SHR_L1_SIGNAL_PROT_MAP_HDLC_RATE /* Select/Add HDLC Rate 1466 bit. */ 1467 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_PROTOCOL_VER _SHR_L1_SIGNAL_PROT_MAP_VER /* Select/Add Version 1468 bit. */ 1469 1470 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_LOF_SET(flags) \ 1471 _SHR_L1_SIGNAL_PROT_MAP_LOF_SET(flags) 1472 1473 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_LOS_SET(flags) \ 1474 _SHR_L1_SIGNAL_PROT_MAP_LOS_SET(flags) 1475 1476 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_SDI_SET(flags) \ 1477 _SHR_L1_SIGNAL_PROT_MAP_SDI_SET(flags) 1478 1479 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_RAI_SET(flags) \ 1480 _SHR_L1_SIGNAL_PROT_MAP_RAI_SET(flags) 1481 1482 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_RESET_SET(flags) \ 1483 _SHR_L1_SIGNAL_PROT_MAP_RESET_SET(flags) 1484 1485 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_ETH_PTR_SET(flags) \ 1486 _SHR_L1_SIGNAL_PROT_MAP_ETH_PTR_SET(flags) 1487 1488 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_HDLC_RATE_SET(flags) \ 1489 _SHR_L1_SIGNAL_PROT_MAP_HDLC_RATE_SET(flags) 1490 1491 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_VER_SET(flags) \ 1492 _SHR_L1_SIGNAL_PROT_MAP_VER_SET(flags) 1493 1494 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_LOF_CLR(flags) \ 1495 _SHR_L1_SIGNAL_PROT_MAP_LOF_CLR(flags) 1496 1497 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_LOS_CLR(flags) \ 1498 _SHR_L1_SIGNAL_PROT_MAP_LOS_CLR(flags) 1499 1500 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_SDI_CLR(flags) \ 1501 _SHR_L1_SIGNAL_PROT_MAP_SDI_CLR(flags) 1502 1503 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_RAI_CLR(flags) \ 1504 _SHR_L1_SIGNAL_PROT_MAP_RAI_CLR(flags) 1505 1506 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_RESET_CLR(flags) \ 1507 _SHR_L1_SIGNAL_PROT_MAP_RESET_CLR(flags) 1508 1509 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_ETH_PTR_CLR(flags) \ 1510 _SHR_L1_SIGNAL_PROT_MAP_ETH_PTR_CLR(flags) 1511 1512 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_HDLC_RATE_CLR(flags) \ 1513 _SHR_L1_SIGNAL_PROT_MAP_HDLC_RATE_CLR(flags) 1514 1515 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_VER_CLR(flags) \ 1516 _SHR_L1_SIGNAL_PROT_MAP_VER_CLR(flags) 1517 1518 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_LOF_GET(flags) \ 1519 _SHR_L1_SIGNAL_PROT_MAP_LOF_GET(flags) 1520 1521 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_LOS_GET(flags) \ 1522 _SHR_L1_SIGNAL_PROT_MAP_LOS_GET(flags) 1523 1524 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_SDI_GET(flags) \ 1525 _SHR_L1_SIGNAL_PROT_MAP_SDI_GET(flags) 1526 1527 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_RAI_GET(flags) \ 1528 _SHR_L1_SIGNAL_PROT_MAP_RAI_GET(flags) 1529 1530 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_RESET_GET(flags) \ 1531 _SHR_L1_SIGNAL_PROT_MAP_RESET_GET(flags) 1532 1533 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_ETH_PTR_GET(flags) \ 1534 _SHR_L1_SIGNAL_PROT_MAP_ETH_PTR_GET(flags) 1535 1536 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_HDLC_RATE_GET(flags) \ 1537 _SHR_L1_SIGNAL_PROT_MAP_HDLC_RATE_GET(flags) 1538 1539 #define BCM_CPRI_CW_L1_SIGNAL_PROT_MAP_VER_GET(flags) \ 1540 _SHR_L1_SIGNAL_PROT_MAP_VER_GET(flags) 1541 1542 #define BCM_CPRI_CRC_APPEND _shrCpriHdlcCrcAppend 1543 #define BCM_CPRI_CRC_REPLACE _shrCpriHdlcCrcReplace 1544 #define BCM_CPRI_CRC_NO_UPDATE _shrCpriHdlcCrcNoUpdate 1545 1546 #define BCM_CPRI_HDLC_FLAG_SIZE_1_BYTE _shrCpriHdlcNumFlagSizeOneByte 1547 #define BCM_CPRI_HDLC_FLAG_SIZE_2_BYTE _shrCpriHdlcNumFlagSizeTwoByte 1548 1549 #define BCM_CPRI_HDLC_FILLING_PATTERN_7E _shrCpriHdlcFillingFlagPattern7E 1550 #define BCM_CPRI_HDLC_FILLING_PATTERN_7F _shrCpriHdlcFillingFlagPattern7F 1551 #define BCM_CPRI_HDLC_FILLING_PATTERN_FF _shrCpriHdlcFillingFlagPatternFF 1552 1553 #define BCM_CPRI_HDLC_FCS_SIZE_8_BITS _shrCpriHdlcFcsSize8Bits 1554 #define BCM_CPRI_HDLC_FCS_SIZE_16_BITS _shrCpriHdlcFcsSize16Bits 1555 #define BCM_CPRI_HDLC_FCS_SIZE_32_BITS _shrCpriHdlcFcsSize32Bits 1556 1557 #define BCM_CPRI_FILTER_DISABLE _shrCpriFilterDisable 1558 #define BCM_CPRI_FILTER_NON_ZERO _shrCpriFilterNonZero 1559 #define BCM_CPRI_FILTER_PERIODIC _shrCpriFilterPeriodic 1560 #define BCM_CPRI_FILTER_CHANGE _shrCpriFilterChange 1561 #define BCM_CPRI_FILTER_PATTERN _shrCpriFilterPatternMatch 1562 1563 #define BCM_CPRI_GCW_MASK_NO_BYTE _shrCpriGcwMaskNone 1564 #define BCM_CPRI_GCW_MASK_LSB_BYTE _shrCpriGcwMaskLSB 1565 #define BCM_CPRI_GCW_MASK_MSB_BYTE _shrCpriGcwMaskMSB 1566 #define BCM_CPRI_GCW_MASK_BOTH_BYTE _shrCpriGcwMaskBOTH 1567 1568 /* bcm_cpri_l1_function_t */ 1569 typedef _shr_cpri_l1_function_t bcm_cpri_l1_function_t; 1570 1571 /* Z.130.0 L1 Function Bits. */ 1572 #define BCM_CPRI_CW_L1_FUNCTION_RESET _SHR_L1_FUNCTION_RESET /* L1 function reset bit. */ 1573 #define BCM_CPRI_CW_L1_FUNCTION_RAI _SHR_L1_FUNCTION_RAI /* L1 function Remote Alarm 1574 Indication (RAI) bit. */ 1575 #define BCM_CPRI_CW_L1_FUNCTION_SDI _SHR_L1_FUNCTION_SDI /* L1 function SAP Defect 1576 Indication (SDI) bit. */ 1577 #define BCM_CPRI_CW_L1_FUNCTION_LOS _SHR_L1_FUNCTION_LOS /* L1 function Loss of Signal 1578 (LOS) bit. */ 1579 #define BCM_CPRI_CW_L1_FUNCTION_LOF _SHR_L1_FUNCTION_LOF /* L1 function Loss of Frame 1580 (LOF) bit. */ 1581 1582 #define BCM_CPRI_CW_L1_FUNCTION_RESET_SET(flags) \ 1583 _SHR_L1_FUNCTION_RESET_SET(flags) 1584 1585 #define BCM_CPRI_CW_L1_FUNCTION_RAI_SET(flags) \ 1586 _SHR_L1_FUNCTION_RAI_SET(flags) 1587 1588 #define BCM_CPRI_CW_L1_FUNCTION_SDI_SET(flags) \ 1589 _SHR_L1_FUNCTION_SDI_SET(flags) 1590 1591 #define BCM_CPRI_CW_L1_FUNCTION_LOS_SET(flags) \ 1592 _SHR_L1_FUNCTION_LOS_SET(flags) 1593 1594 #define BCM_CPRI_CW_L1_FUNCTION_LOF_SET(flags) \ 1595 _SHR_L1_FUNCTION_LOF_SET(flags) 1596 1597 #define BCM_CPRI_CW_L1_FUNCTION_RESET_GET(flags) \ 1598 _SHR_L1_FUNCTION_RESET_GET(flags) 1599 1600 #define BCM_CPRI_CW_L1_FUNCTION_RAI_GET(flags) \ 1601 _SHR_L1_FUNCTION_RAI_GET(flags) 1602 1603 #define BCM_CPRI_CW_L1_FUNCTION_SDI_GET(flags) \ 1604 _SHR_L1_FUNCTION_SDI_GET(flags) 1605 1606 #define BCM_CPRI_CW_L1_FUNCTION_LOS_GET(flags) \ 1607 _SHR_L1_FUNCTION_LOS_GET(flags) 1608 1609 #define BCM_CPRI_CW_L1_FUNCTION_LOF_GET(flags) \ 1610 _SHR_L1_FUNCTION_LOF_GET(flags) 1611 1612 #define BCM_CPRI_CW_L1_FUNCTION_RESET_CLR(flags) \ 1613 _SHR_L1_FUNCTION_RESET_CLR(flags) 1614 1615 #define BCM_CPRI_CW_L1_FUNCTION_RAI_CLR(flags) \ 1616 _SHR_L1_FUNCTION_RAI_CLR(flags) 1617 1618 #define BCM_CPRI_CW_L1_FUNCTION_SDI_CLR(flags) \ 1619 _SHR_L1_FUNCTION_SDI_CLR(flags) 1620 1621 #define BCM_CPRI_CW_L1_FUNCTION_LOS_CLR(flags) \ 1622 _SHR_L1_FUNCTION_LOS_CLR(flags) 1623 1624 #define BCM_CPRI_CW_L1_FUNCTION_LOF_CLR(flags) \ 1625 _SHR_L1_FUNCTION_LOF_CLR(flags) 1626 1627 /* Z.66.0 HDLC Rate. */ 1628 #define BCM_CPRI_HDLC_RATE_NO_HDLC 0x00 /* No HDLC . */ 1629 #define BCM_CPRI_HDLC_RATE_240KBPS 0x01 /* 240 Kbps . */ 1630 #define BCM_CPRI_HDLC_RATE_480KBPS 0x02 /* 480 Kbps . */ 1631 #define BCM_CPRI_HDLC_RATE_960KBPS 0x03 /* 960 Kbps . */ 1632 #define BCM_CPRI_HDLC_RATE_1920KBPS 0x04 /* 1920 Kbps . */ 1633 #define BCM_CPRI_HDLC_RATE_2400KBPS 0x05 /* 2400 Kbps . */ 1634 #define BCM_CPRI_HDLC_RATE_HIGHEST 0x06 /* Highest Rate . */ 1635 #define BCM_CPRI_HDLC_RATE_NEGOTIATED 0x07 /* Negotiated on higher 1636 layer. */ 1637 1638 /* CPRI Control Word Layer 1 inband information. */ 1639 typedef struct bcm_cpri_cw_l1_inband_info_s { 1640 uint32 eth_ptr; /* Z.194.0 Ethernet pointer p. */ 1641 uint32 layer1_function; /* Z.130.0 l1 function */ 1642 uint32 hdlc_rate; /* Z.66.0 HDLC rate */ 1643 uint32 protocol_ver; /* Z.2.0 version 1 or 2 */ 1644 } bcm_cpri_cw_l1_inband_info_t; 1645 1646 typedef enum bcm_cpri_crc_init_value_e { 1647 bcmCpriHdlcCrcInitValAll0 = _shrCpriHdlcCrcInitValAll0, /* All 0s */ 1648 bcmCpriHdlcCrcInitValAll1 = _shrCpriHdlcCrcInitValAll1, /* All 1s */ 1649 bcmCpriHdlcCrcInitValCount = _shrCpriHdlcCrcInitValCount /* Should be last */ 1650 } bcm_cpri_crc_init_value_t; 1651 1652 typedef enum bcm_cpri_hdlc_fcs_size_e { 1653 bcmCpriHdlcFcsSize8Bits = _shrCpriHdlcFcsSize8Bits, /* 8 bits */ 1654 bcmCpriHdlcFcsSize16Bits = _shrCpriHdlcFcsSize16Bits, /* 16 bits */ 1655 bcmCpriHdlcFcsSize32Bits = _shrCpriHdlcFcsSize32Bits, /* 32 bits */ 1656 bcmCpriHdlcFcsSizeCount = _shrCpriHdlcFcsSizeCount /* Should be last */ 1657 } bcm_cpri_hdlc_fcs_size_t; 1658 1659 /* */ 1660 typedef struct bcm_cpri_slow_hdlc_config_info_s { 1661 bcm_cpri_crc_mode_t hdlc_crc_mode; /* HDLC CRC mode */ 1662 bcm_cpri_hdlc_flag_size_t tx_flag_size; /* Flag Size */ 1663 bcm_cpri_hdlc_filling_pattern_t tx_filling_pattern; /* Fill Pattern */ 1664 bcm_cpri_crc_init_value_t crc_init_val; /* all 0's or all 1's */ 1665 int use_fe_mac; /* True/False */ 1666 int crc_byte_swap; /* True/False */ 1667 int no_fcs_err_check; /* True/False */ 1668 uint32 hdlc_cw_sel; /* Control Word Select */ 1669 uint32 hdlc_cw_size; /* Control Word Size */ 1670 bcm_cpri_hdlc_fcs_size_t hdlc_fcs_size; /* FCS size */ 1671 int hdlc_run_drop; /* Runt Drop Threshold */ 1672 int hdlc_max_drop; /* Max Drop Threshold */ 1673 uint32 hdlc_min_size; /* Min Size Thereshold */ 1674 uint32 hdlc_max_size; /* Max Size Threshold */ 1675 uint32 hdlc_queue_num; /* Queue number */ 1676 uint32 priority; /* 0-3 */ 1677 uint32 queue_size; /* in bytes */ 1678 uint32 cycle_size; /* Jitter Buffer Size in number of 1679 packets */ 1680 uint32 buffer_size; /* pkt size */ 1681 } bcm_cpri_slow_hdlc_config_info_t; 1682 1683 /* */ 1684 typedef struct bcm_cpri_fast_eth_config_info_s { 1685 uint32 sub_channel_start; /* The first sub-channel allocated for fast 1686 c&m */ 1687 uint32 sub_channel_size; /* sub channel size */ 1688 uint32 cw_sel; /* Select sub-channel words */ 1689 uint32 cw_size; /* Number of bytes per word to use. Valid 1690 values are 0 to 16. */ 1691 uint32 queue_num; /* queue number */ 1692 int ignore_fcs_err; /* True or False */ 1693 uint32 min_pkt_size; /* min packet size */ 1694 uint32 max_pkt_size; /* max packet size */ 1695 int drop_undersize_pkt; /* Enable drop of Packet size below min 1696 packet size */ 1697 int drop_oversize_pkt; /* Enable drop of Packet size above max 1698 packet size */ 1699 int strip_crc; /* True or False */ 1700 uint32 min_ipg; /* Min Inter Packet Gap */ 1701 bcm_cpri_crc_mode_t crc_mode; /* 0-append 1-replace 2-No update */ 1702 uint32 priority; /* 0-3 */ 1703 uint32 queue_size; /* in bytes */ 1704 uint32 cycle_size; /* Jitter Buffer size, in number of packets */ 1705 uint32 buffer_size; /* pkt size */ 1706 } bcm_cpri_fast_eth_config_info_t; 1707 1708 /* bcm_cpri_vsd_control_subchan_num_bytes_t */ 1709 typedef _shr_cpri_vsd_control_subchan_num_bytes_t bcm_cpri_vsd_control_subchan_num_bytes_t; 1710 1711 #define BCM_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_1 _shrVsdCtrlSubchanNumBytes1 1712 #define BCM_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_2 _shrVsdCtrlSubchanNumBytes2 1713 1714 /* bcm_cpri_vsd_control_subchan_size_t */ 1715 typedef _shr_cpri_vsd_control_subchan_size_t bcm_cpri_vsd_control_subchan_size_t; 1716 1717 #define BCM_CPRI_VSD_CONTROL_SUBCHAN_SIZE_2 _shrVsdCtrlSubchanSize2 1718 #define BCM_CPRI_VSD_CONTROL_SUBCHAN_SIZE_4 _shrVsdCtrlSubchanSize4 1719 1720 /* bcm_cpri_vsd_control_flow_num_bytes_t */ 1721 typedef _shr_cpri_vsd_control_flow_num_bytes_t bcm_cpri_vsd_control_flow_num_bytes_t; 1722 1723 #define BCM_CPRI_CONTROL_FLOW_NUM_BYTES_2 _shrVsdCtrlFlowNumBytes2 1724 #define BCM_CPRI_CONTROL_FLOW_NUM_BYTES_4 _shrVsdCtrlFlowNumBytes4 1725 1726 /* */ 1727 typedef struct bcm_cpri_rx_vsd_config_info_s { 1728 uint32 subchan_start; /* starting control subchannel number */ 1729 bcm_cpri_vsd_control_subchan_size_t subchan_size; /* 2 or 4 sub channels. */ 1730 bcm_cpri_vsd_control_subchan_num_bytes_t subchan_bytes; /* Sub Channel Number of Bytes 1,2 or 4. */ 1731 int subchan_step; /* 0 - No Skip 1- Skip One Sub Chan. */ 1732 uint32 queue_num; /* Queue Number */ 1733 uint32 vsd_valid_sector_mask[4]; /* total of 128 possible sectors */ 1734 uint32 priority; /* 0-3 */ 1735 uint32 queue_size; /* in bytes */ 1736 bcm_cpri_vsd_control_flow_num_bytes_t flow_bytes; /* number of bytes per flow 2 or 4. */ 1737 } bcm_cpri_rx_vsd_config_info_t; 1738 1739 /* VSD Flow Information */ 1740 typedef struct bcm_cpri_rx_vsd_flow_info_s { 1741 uint32 hyper_frame_number; /* Hyper Frame Number */ 1742 uint32 hyper_frame_modulo; /* Hyper Frame Modulo */ 1743 int filter_zero_data; /* Filer all 0's Data. */ 1744 uint32 section_num[4]; /* Section numbers of the group, 0 .. 127 . */ 1745 uint32 num_sector; /* Number of Sectors */ 1746 uint32 tag_id; /* Tag ID */ 1747 } bcm_cpri_rx_vsd_flow_info_t; 1748 1749 /* */ 1750 typedef struct bcm_cpri_rx_vsd_raw_config_info_s { 1751 uint32 schan_start; /* starting control subchannel number */ 1752 uint32 schan_size; /* Number of sub channels */ 1753 uint32 cw_sel; /* 4 bits bit map. which Xs bytes to 1754 use */ 1755 uint32 cw_size; /* number of bytes per word to extract 1756 0 to Tcw/8. Max 16 bytes */ 1757 uint32 queue_num; /* The queue number to be used for the 1758 payload data in the encapsulation 1759 memory. */ 1760 uint32 match_mask; /* Mask to apply to the data before 1761 comparing to the match_value. */ 1762 uint32 match_value; /* Value to match. */ 1763 uint32 match_offset; /* The offset of the first byte in the 1764 flow to match. */ 1765 uint32 hfn_modulo; /* Modulo value. Valid values are 1 to 1766 150. */ 1767 uint32 hfn_offset; /* Programmable offset. Valid values are 1768 0 to 149. */ 1769 bcm_cpri_cw_filter_mode_t filter_mode; /* Filter Mode */ 1770 uint32 priority; /* 0-3 */ 1771 uint32 queue_size; /* in_bytes */ 1772 } bcm_cpri_rx_vsd_raw_config_info_t; 1773 1774 /* */ 1775 typedef struct bcm_cpri_rx_rsvd5_config_info_s { 1776 uint32 schan_start; /* The first sub-channel allocated for the RSVD5 1777 parser. Valid values are 16 to 63 */ 1778 uint32 schan_size; /* Number of sub channels 1, 2 or 4 for CPRI 1779 4x, 8x and 16x.2 or 4 for CPRI 2x and 1780 10x.Setting the field to 0 disables the 1781 engine. Values other than 1, 2, 4 not 1782 supported. */ 1783 int disable_parity_check; /* True/False */ 1784 uint32 queue_num; /* Queue Number */ 1785 uint32 priority; /* 0-3 */ 1786 uint32 queue_size; /* in_bytes */ 1787 } bcm_cpri_rx_rsvd5_config_info_t; 1788 1789 /* Tag configuration */ 1790 typedef struct bcm_cpri_control_tag_config_s { 1791 uint32 default_tag; /* Default tag ID */ 1792 uint32 no_match_tag; /* No Match Tag ID */ 1793 } bcm_cpri_control_tag_config_t; 1794 1795 /* RX GCW Configuration */ 1796 typedef struct bcm_cpri_rx_gcw_config_info_s { 1797 uint32 Ns; /* sub channel # */ 1798 uint32 Xs; /* word number */ 1799 uint32 Y; /* first byte number valid value 0-7 1800 for 0,2,4,..14) */ 1801 bcm_cpri_gcw_mask_t mask; /* Mask */ 1802 bcm_cpri_cw_filter_mode_t filter_mode; /* Filter Mode */ 1803 uint32 hfn_index; /* Programmable offset. Valid values 1804 are 0 to 149. */ 1805 uint32 hfn_modulo; /* Modulo value. Valid values are 1 to 1806 150. */ 1807 uint32 match_value; /* Match Value */ 1808 uint32 match_mask; /* Mask to apply to the data before 1809 comparing to the match_value. */ 1810 } bcm_cpri_rx_gcw_config_info_t; 1811 1812 /* Control Word Sync Info */ 1813 typedef struct bcm_cpri_cw_sync_info_s { 1814 uint32 hfn; /* current hyperframe number Z.64.0 */ 1815 uint32 bfn; /* cpri radio frame number Z.192.0 Z.128.0 */ 1816 } bcm_cpri_cw_sync_info_t; 1817 1818 /* VSD Config informations. */ 1819 typedef struct bcm_cpri_tx_vsd_config_info_s { 1820 uint32 subchan_start; /* starting control subchannel number */ 1821 bcm_cpri_vsd_control_subchan_size_t subchan_size; /* 2 or 4 sub channels. */ 1822 bcm_cpri_vsd_control_subchan_num_bytes_t subchan_bytes; /* Sub Channel Number of Bytes 1,2 or 4. */ 1823 int subchan_step; /* 0 - No Skip 1- Skip One Sub Chan. */ 1824 uint32 queue; /* 0x44 (68) default */ 1825 uint32 vsd_valid_sector_mask[4]; /* total of 128 possible sectors */ 1826 uint32 cycle_size; /* hdlc rate */ 1827 uint32 buffer_size; /* pkt size */ 1828 bcm_cpri_vsd_control_flow_num_bytes_t flow_bytes; /* number of bytes per flow 2 or 4. */ 1829 int byte_order_swap; /* Byte Order Swap 0:[15:8]=byte0 1830 [7:0]=byte1 1: [15:8]=byte1 1831 [7:0]=byte0 */ 1832 } bcm_cpri_tx_vsd_config_info_t; 1833 1834 /* VSD Flow Information */ 1835 typedef struct bcm_cpri_tx_vsd_flow_info_s { 1836 uint32 hyper_frame_number; /* Hyper Frame Number */ 1837 uint32 hyper_frame_modulo; /* Hyper Frame Modulo */ 1838 int repeat_mode; /* Repeat Mode. */ 1839 uint32 section_num[4]; /* Section numbers of the group, 0 .. 127 . */ 1840 uint32 num_sector; /* Number of Sectors */ 1841 uint32 roe_flow_id; /* RoE Flow ID */ 1842 } bcm_cpri_tx_vsd_flow_info_t; 1843 1844 /* VSD Raw configuration */ 1845 typedef struct bcm_cpri_tx_vsd_raw_config_info_s { 1846 uint32 schan_start; /* starting control subchannel number */ 1847 uint32 schan_size; /* Number of sub channels */ 1848 uint32 cw_sel; /* 4 bits bit map. which Xs bytes to use */ 1849 uint32 cw_size; /* number of bytes per word to extract 0 to Tcw/8. 1850 Max 16 bytes */ 1851 uint32 queue_num; /* The decap queue number to be used for VSD raw 1852 data. Valid values are 64-79. Should be different 1853 than other control queue numbers.. */ 1854 uint32 map_mode; /* Map Mode */ 1855 int repeat_mode; /* True/False */ 1856 int bfn0_filter_enable; /* True/False */ 1857 int bfn1_filter_enable; /* True/False */ 1858 uint32 hfn_index; /* hfn number */ 1859 uint32 hfn_modulo; /* hfn modulo */ 1860 uint32 idle_value; /* Idle value */ 1861 uint32 cycle_size; /* jitter buffer size in number of pakcets */ 1862 uint32 buffer_size; /* packet size size */ 1863 } bcm_cpri_tx_vsd_raw_config_info_t; 1864 1865 /* VSD raw fiter information */ 1866 typedef struct bcm_cpri_tx_cw_vsd_raw_filter_info_s { 1867 uint32 bfn0_value; /* BFN value for filter */ 1868 uint32 bfn0_mask; /* BFN mask for filter */ 1869 uint32 bfn1_value; /* BFN value for filter */ 1870 uint32 bfn1_mask; /* BFN mask for filter */ 1871 } bcm_cpri_tx_cw_vsd_raw_filter_info_t; 1872 1873 /* RSVD5 configuration */ 1874 typedef struct bcm_cpri_tx_cw_rsvd5_config_info_s { 1875 uint32 schan_start; /* The first sub-channel allocated for the RSVD5 1876 parser. Valid values are 16 to 63 */ 1877 uint32 schan_size; /* Number of sub channels 1, 2 or 4 for CPRI 4x, 8x 1878 and 16x.2 or 4 for CPRI 2x and 10x.Setting the 1879 field to 0 disables the engine. Values other than 1880 1, 2, 4 not supported. */ 1881 int crc_check_enable; /* True/False */ 1882 uint32 queue_num; /* Queue number */ 1883 uint32 cycle_size; /* Jitter buffer size in number of packets */ 1884 uint32 buffer_size; /* packet size */ 1885 } bcm_cpri_tx_cw_rsvd5_config_info_t; 1886 1887 /* GCW config information */ 1888 typedef struct bcm_cpri_tx_gcw_config_info_s { 1889 uint32 Ns; /* sub channel # */ 1890 uint32 Xs; /* word number */ 1891 uint32 Y; /* first byte number valid value 0-7 for 1892 0,2,4,..14) */ 1893 bcm_cpri_gcw_mask_t mask; /* Mask */ 1894 int repeat_mode; /* True/False */ 1895 int bfn0_filter_enable; /* Insert only when BFN matches values 1896 specified by the BFN configuration register. */ 1897 int bfn1_filter_enable; /* Insert only when BFN matches values 1898 specified by the BFN configuration register. */ 1899 uint32 hfn_index; /* Programmable offset. Valid values are 0 to 1900 149. */ 1901 uint32 hfn_modulo; /* Modulo value. Valid values are 1 to 150. */ 1902 } bcm_cpri_tx_gcw_config_info_t; 1903 1904 /* GCW Filter information */ 1905 typedef struct bcm_cpri_tx_gcw_tx_filter_info_s { 1906 uint32 bfn0_value; /* BFN value for filter */ 1907 uint32 bfn0_mask; /* BFN mask for filter */ 1908 uint32 bfn1_value; /* BFN value for filter */ 1909 uint32 bfn1_mask; /* BFN mask for filter */ 1910 } bcm_cpri_tx_gcw_tx_filter_info_t; 1911 1912 #ifndef BCM_HIDE_DISPATCHABLE 1913 1914 extern int bcm_cpri_port_rx_cw_sync_info_get( 1915 int unit, 1916 int port, 1917 uint32 *hyper_frame_num, 1918 uint32 *radio_frame_num); 1919 1920 /* Get the control word L1 Inband Protocol information. */ 1921 extern int bcm_cpri_port_rx_cw_l1_inband_info_get( 1922 int unit, 1923 int port, 1924 bcm_cpri_cw_l1_inband_info_t *l1_inband_info); 1925 1926 /* Set/Get the control word signal protection. */ 1927 extern int bcm_cpri_port_rx_cw_l1_signal_protection_set( 1928 int unit, 1929 int port, 1930 uint32 signal_map, 1931 uint32 enable); 1932 1933 /* Set/Get the control word signal protection. */ 1934 extern int bcm_cpri_port_rx_cw_l1_signal_protection_get( 1935 int unit, 1936 int port, 1937 uint32 signal_map, 1938 uint32 *enable); 1939 1940 /* Sets/Gets the hdlc control flow. */ 1941 extern int bcm_cpri_port_cw_slow_hdlc_config_set( 1942 int unit, 1943 int port, 1944 bcm_cpri_slow_hdlc_config_info_t *config); 1945 1946 /* Sets/Gets the hdlc control flow. */ 1947 extern int bcm_cpri_port_cw_slow_hdlc_config_get( 1948 int unit, 1949 int port, 1950 bcm_cpri_slow_hdlc_config_info_t *config); 1951 1952 /* Sets/Gets the fast Ethernet control flow. */ 1953 extern int bcm_cpri_port_cw_fast_eth_config_set( 1954 int unit, 1955 int port, 1956 bcm_cpri_fast_eth_config_info_t *config); 1957 1958 /* Sets/Gets the fast Ethernet control flow. */ 1959 extern int bcm_cpri_port_cw_fast_eth_config_get( 1960 int unit, 1961 int port, 1962 bcm_cpri_fast_eth_config_info_t *config); 1963 1964 /* 1965 * This API configures/retrieves the VSD (Vendor Specific Data) control 1966 * stream information. 1967 */ 1968 extern int bcm_cpri_port_rx_cw_vsd_config_set( 1969 int unit, 1970 int port, 1971 bcm_cpri_rx_vsd_config_info_t *config); 1972 1973 /* 1974 * This API configures/retrieves the VSD (Vendor Specific Data) control 1975 * stream information. 1976 */ 1977 extern int bcm_cpri_port_rx_cw_vsd_config_get( 1978 int unit, 1979 int port, 1980 bcm_cpri_rx_vsd_config_info_t *config); 1981 1982 /* Configure/Retrieve the VSD(Vendor Specific Data) control flow */ 1983 extern int bcm_cpri_port_rx_cw_vsd_ctrl_flow_add( 1984 int unit, 1985 int port, 1986 uint16 group_id, 1987 bcm_cpri_rx_vsd_flow_info_t *config); 1988 1989 /* Configure/Retrieve the VSD(Vendor Specific Data) control flow */ 1990 extern int bcm_cpri_port_rx_cw_vsd_ctrl_flow_delete( 1991 int unit, 1992 int port, 1993 uint16 group_id); 1994 1995 /* Configure/Retrieve the VSD(Vendor Specific Data) control flow */ 1996 extern int bcm_cpri_port_rx_cw_vsd_ctrl_flow_get( 1997 int unit, 1998 int port, 1999 uint16 group_id, 2000 bcm_cpri_rx_vsd_flow_info_t *config); 2001 2002 /* Configure the tag to flow mapping. */ 2003 extern int bcm_cpri_encap_control_queue_tag_to_flow_id_map_set( 2004 int unit, 2005 int port, 2006 uint32 tag_id, 2007 uint32 flow_id); 2008 2009 extern int bcm_cpri_port_rx_cw_vsd_raw_config_set( 2010 int unit, 2011 int port, 2012 uint8 vsd_raw_id, 2013 bcm_cpri_rx_vsd_raw_config_info_t *config); 2014 2015 extern int bcm_cpri_port_rx_cw_vsd_raw_config_get( 2016 int unit, 2017 int port, 2018 uint8 vsd_raw_id, 2019 bcm_cpri_rx_vsd_raw_config_info_t *config); 2020 2021 /* Set/Get rsvd5 configuration on a port. */ 2022 extern int bcm_cpri_port_rx_cw_rsvd5_config_set( 2023 int unit, 2024 int port, 2025 bcm_cpri_rx_rsvd5_config_info_t *config); 2026 2027 /* Set/Get rsvd5 configuration on a port. */ 2028 extern int bcm_cpri_port_rx_cw_rsvd5_config_get( 2029 int unit, 2030 int port, 2031 bcm_cpri_rx_rsvd5_config_info_t *config); 2032 2033 /* Configure rx default and no match tag. */ 2034 extern int bcm_cpri_port_rx_tag_config_set( 2035 int unit, 2036 int port, 2037 bcm_cpri_control_tag_config_t *config); 2038 2039 /* Add/Delete entry from tag generation table. */ 2040 extern int bcm_cpri_port_rx_tag_entry_add( 2041 int unit, 2042 int port, 2043 bcm_cpri_tag_gen_entry_t *config); 2044 2045 /* Add/Delete entry from tag generation table. */ 2046 extern int bcm_cpri_port_rx_tag_entry_delete( 2047 int unit, 2048 int port, 2049 bcm_cpri_tag_gen_entry_t *config); 2050 2051 /* Set/Get CPRI generic control word configuration. */ 2052 extern int bcm_cpri_port_rx_cw_gcw_config_set( 2053 int unit, 2054 int port, 2055 uint8 index, 2056 bcm_cpri_rx_gcw_config_info_t *config); 2057 2058 /* Set/Get CPRI generic control word configuration. */ 2059 extern int bcm_cpri_port_rx_cw_gcw_config_get( 2060 int unit, 2061 int port, 2062 uint8 index, 2063 bcm_cpri_rx_gcw_config_info_t *config); 2064 2065 /* Configure tx control word sync information. */ 2066 extern int bcm_cpri_port_tx_cw_sync_info_set( 2067 int unit, 2068 int port, 2069 bcm_cpri_cw_sync_info_t *entry); 2070 2071 /* Configure tx control word sync information. */ 2072 extern int bcm_cpri_port_tx_cw_sync_info_get( 2073 int unit, 2074 int port, 2075 bcm_cpri_cw_sync_info_t *entry); 2076 2077 /* Set/Get CPRI Tx control word layer 1 inband information. */ 2078 extern int bcm_cpri_port_tx_cw_l1_inband_info_set( 2079 int unit, 2080 int port, 2081 bcm_cpri_cw_l1_inband_info_t *inband_info); 2082 2083 /* Set/Get CPRI Tx control word layer 1 inband information. */ 2084 extern int bcm_cpri_port_tx_cw_l1_inband_info_get( 2085 int unit, 2086 int port, 2087 bcm_cpri_cw_l1_inband_info_t *inband_info); 2088 2089 /* Set/Get CPRI tx vendor specific control word. */ 2090 extern int bcm_cpri_port_tx_cw_vsd_config_set( 2091 int unit, 2092 int port, 2093 bcm_cpri_tx_vsd_config_info_t *entry); 2094 2095 /* Set/Get CPRI tx vendor specific control word. */ 2096 extern int bcm_cpri_port_tx_cw_vsd_config_get( 2097 int unit, 2098 int port, 2099 bcm_cpri_tx_vsd_config_info_t *entry); 2100 2101 /* Set CPRI tx vendor specific control flow. */ 2102 extern int bcm_cpri_port_tx_cw_vsd_ctrl_flow_add( 2103 int unit, 2104 int port, 2105 uint16 group_id, 2106 bcm_cpri_tx_vsd_flow_info_t *config); 2107 2108 /* Set CPRI tx vendor specific control flow. */ 2109 extern int bcm_cpri_port_tx_cw_vsd_ctrl_flow_delete( 2110 int unit, 2111 int port, 2112 uint16 group_id); 2113 2114 /* Set CPRI tx vendor specific control flow. */ 2115 extern int bcm_cpri_port_tx_cw_vsd_ctrl_flow_get( 2116 int unit, 2117 int port, 2118 uint16 group_id, 2119 bcm_cpri_tx_vsd_flow_info_t *config); 2120 2121 /* Configure/Retrieve CPRI tx vendor specific raw flow configuration. */ 2122 extern int bcm_cpri_port_tx_cw_vsd_raw_flow_config_set( 2123 int unit, 2124 int port, 2125 uint8 index, 2126 bcm_cpri_tx_vsd_raw_config_info_t *config); 2127 2128 /* Configure/Retrieve CPRI tx vendor specific raw flow configuration. */ 2129 extern int bcm_cpri_port_tx_cw_vsd_raw_flow_config_get( 2130 int unit, 2131 int port, 2132 uint8 index, 2133 bcm_cpri_tx_vsd_raw_config_info_t *config); 2134 2135 /* Set/Get tx vendor specific raw control filter configuration. */ 2136 extern int bcm_cpri_port_tx_cw_vsd_raw_filter_set( 2137 int unit, 2138 int port, 2139 bcm_cpri_tx_cw_vsd_raw_filter_info_t *config); 2140 2141 /* Set/Get tx vendor specific raw control filter configuration. */ 2142 extern int bcm_cpri_port_tx_cw_vsd_raw_filter_get( 2143 int unit, 2144 int port, 2145 bcm_cpri_tx_cw_vsd_raw_filter_info_t *config); 2146 2147 /* Set/Get CPRI Tx RSVD5 control configuration. */ 2148 extern int bcm_cpri_port_tx_cw_rsvd5_config_set( 2149 int unit, 2150 int port, 2151 bcm_cpri_tx_cw_rsvd5_config_info_t *config); 2152 2153 /* Set/Get CPRI Tx RSVD5 control configuration. */ 2154 extern int bcm_cpri_port_tx_cw_rsvd5_config_get( 2155 int unit, 2156 int port, 2157 bcm_cpri_tx_cw_rsvd5_config_info_t *config); 2158 2159 /* Set/GetCPRI Tx generic control word configuration. */ 2160 extern int bcm_cpri_port_tx_cw_gcw_config_set( 2161 int unit, 2162 int port, 2163 uint8 index, 2164 bcm_cpri_tx_gcw_config_info_t *config); 2165 2166 /* Set/GetCPRI Tx generic control word configuration. */ 2167 extern int bcm_cpri_port_tx_cw_gcw_config_get( 2168 int unit, 2169 int port, 2170 uint8 index, 2171 bcm_cpri_tx_gcw_config_info_t *config); 2172 2173 /* Set/Get CPRI Tx generic control word filter configuration. */ 2174 extern int bcm_cpri_port_tx_cw_gcw_filter_set( 2175 int unit, 2176 int port, 2177 bcm_cpri_tx_gcw_tx_filter_info_t *config); 2178 2179 /* Set/Get CPRI Tx generic control word filter configuration. */ 2180 extern int bcm_cpri_port_tx_cw_gcw_filter_get( 2181 int unit, 2182 int port, 2183 bcm_cpri_tx_gcw_tx_filter_info_t *config); 2184 2185 #endif /* BCM_HIDE_DISPATCHABLE */ 2186 2187 /* CPRI interrupt types */ 2188 typedef _shr_cpri_interrupt_type_t bcm_cpri_interrupt_type_t; 2189 2190 /* CPRI interrupt types */ 2191 #define BCM_CPRI_INTR_RX_PCS_64B66B_BLK_LCK_LL _shrCpriIntrRxPcs64B66BBlkLckLl /* RX PCS Block lock 2192 status - latch low 2193 version. */ 2194 #define BCM_CPRI_INTR_RX_PCS_64B66B_BLK_LCK_LH _shrCpriIntrRxPcs64B66BBlkLckLh /* RX PCS Block lock 2195 status - latch high 2196 version. */ 2197 #define BCM_CPRI_INTR_RX_PCS_64B66B_HI_BER_LL _shrCpriIntrRxPcs64B66BHiBerLl /* RX PCS BER - latch low 2198 version. */ 2199 #define BCM_CPRI_INTR_RX_PCS_64B66B_HI_BER_LH _shrCpriIntrRxPcs64B66BHiBerLh /* RX PCS BER - latch 2200 high version. */ 2201 #define BCM_CPRI_INTR_RX_PCS_LOS_LL _shrCpriIntrRxPcsLosLl /* RX PCS LOS - CPRI port 2202 Link UP. */ 2203 #define BCM_CPRI_INTR_RX_PCS_LOS_LH _shrCpriIntrRxPcsLosLh /* RX PCS LOS - CPRI port 2204 Link DOWN. */ 2205 #define BCM_CPRI_INTR_RX_PCS_LINK_STATUS_LL _shrCpriIntrRxPcsLinkStatusLl /* RX PCS link status - 2206 latch low version. */ 2207 #define BCM_CPRI_INTR_RX_PCS_LINK_STATUS_LH _shrCpriIntrRxPcsLinkStatusLh /* RX PCS link status - 2208 latch high version. */ 2209 #define BCM_CPRI_INTR_RX_PCS_EXTRACT_FIFO_OVRFLOW _shrCpriIntrRxPcsExtractFifoOvrFlow /* RX PCS extract FIFO 2210 overflow interrupt. */ 2211 #define BCM_CPRI_INTR_RX_GCW _shrCpriIntrRxGcw /* Interrupt for RX GCW 2212 Word(0-15) is loaded. */ 2213 #define BCM_CPRI_INTR_RX_1588_TS_FIFO _shrCpriIntrRx1588TsFifo /* RX 1588 FIFO intr */ 2214 #define BCM_CPRI_INTR_RX_1588_CAPTURED_TS _shrCpriIntrRx1588CapturedTs /* RX 1588 Sw capture 2215 interrupt. */ 2216 #define BCM_CPRI_INTR_RX_ENCAP_DATA_Q_OVERFLOW _shrCpriIntrRxEncapDataQOverflow /* Encap Data Queue FIFO 2217 Over-Flow */ 2218 #define BCM_CPRI_INTR_RX_ENCAP_CTRL_Q_OVERFLOW _shrCpriIntrRxEncapCtrlQOverflow /* Encap Ctrl Queue FIFO 2219 Over-Flow */ 2220 #define BCM_CPRI_INTR_RX_ENCAP_GSM_TS_Q_ERR _shrCpriIntrRxEncapGsmTsQErr /* Encap Per Queue GSM 2221 Time-Slot Error */ 2222 #define BCM_CPRI_INTR_RX_ENCAP_WORKQ_FIFO_OVERFLOW _shrCpriIntrRxEncapWqFiFoOverflow /* Encap Per Work-Queue 2223 FIFO Over Error */ 2224 #define BCM_CPRI_INTR_RX_ENCAP_RXFRM_IN_FIFO_OVERFLOW _shrCpriIntrRxEncapRxFrmInFifoOverflow /* Encap RX-framer 2225 Input-buffer FIFO Over 2226 Error */ 2227 #define BCM_CPRI_INTR_RX_ENCAP_IPSM_CDC_FIFO_ERR _shrCpriIntrRxEncapIpsmCdcFifoErr /* Encap IPSM CDC FIFO 2228 Error */ 2229 #define BCM_CPRI_INTR_RX_FRM_RSVD4_TS _shrCpriIntrRxFrmRsvd4Ts /* Per Axc(0-63) 2230 Timestamp interrupt in 2231 RSVD4 mode */ 2232 #define BCM_CPRI_INTR_RX_FRM_RSVD4_SINGLE_TS_ERR _shrCpriIntrRxFrmRsvd4SingleTsErr /* single timestamp 2233 error in RSVD4 mode */ 2234 #define BCM_CPRI_INTR_RX_FRM_L1_SIGNAL_CHANGE _shrCpriIntrRxFrmL1SigChange /* L1 signal change */ 2235 #define BCM_CPRI_INTR_RX_PCS_FEC_CS_CW_BAD _shrCpriIntrRxPcsFecCsCwBad /* cw_bad during CW_SYNC 2236 state */ 2237 #define BCM_CPRI_INTR_TX_DECAP_DATA_Q_OVFL_ERR _shrCpriIntrTxDecapDataQOvflErr /* Decap Per Queue Decap 2238 Data Queue FIFO 2239 Over-Flow Error */ 2240 #define BCM_CPRI_INTR_TX_DECAP_DATA_Q_UDFL_ERR _shrCpriIntrTxDecapDataQUdflErr /* Decap Per Queue Decap 2241 Data Queue FIFO 2242 underflow Error */ 2243 #define BCM_CPRI_INTR_TX_DECAP_DATA_BUFSIZE_ERR _shrCpriIntrTxDecapDataQBufSizeErr /* Decap Per Queue Decap 2244 Data Queue BUFF SIZE 2245 Error */ 2246 #define BCM_CPRI_INTR_TX_DECAP_AG_MODE_PKT_MISS _shrCpriIntrTxDecapAgModePktMiss /* Agnostic mode missing 2247 packet */ 2248 #define BCM_CPRI_INTR_TX_1588_CAPTURED_TS _shrCpriIntrTx1588CapturedTs /* TX 1588 Sw capture 2249 interrupt. */ 2250 #define BCM_CPRI_INTR_TX_1588_TS_FIFO _shrCpriIntrTx1588TsFifo /* TX 1588 FIFO capture 2251 interrupt. */ 2252 #define BCM_CPRI_INTR_TX_FRM_CWA_CTRL_PKT_FLOW_ID_ERR _shrCpriIntrTxFrmCwaCtrlPktFlowIdErr /* CWA ctrl flow packet 2253 flow id error */ 2254 #define BCM_CPRI_INTR_TX_FRM_BFA_HF_START_MISALIGN _shrCpriIntrTxFrmBfaHfStartMisalign /* BFA hf start misalign */ 2255 #define BCM_CPRI_INTR_TX_FRM_DR_MULTI_ETH_PSIZE_UNDERSIZE _shrCpriIntrTxFrmDrMultiEthPsizeUndersize /* RSVD4 control proc 2256 decap req multi eth - 2257 packet undersize */ 2258 #define BCM_CPRI_INTR_TX_FRM_DR_ACK_MISALIGN _shrCpriIntrTxFrmDrAckMisalign /* RSVD4 control proc 2259 decap req multi eth - 2260 packet undersize */ 2261 #define BCM_CPRI_INTR_TX_FRM_CWA_MULTIPLE_VALIDS _shrCpriIntrTxFrmCwaMultipleValids /* CPRI control asm 2262 valids from multiple 2263 engines are asserted 2264 at same time */ 2265 #define BCM_CPRI_INTR_TX_FRM_CWA_SDVM_PROC_OVERFLOW _shrCpriIntrTxFrmCwaSdvmProcOverflow /* CPRI control asm RSVD5 2266 proc buffer overflow */ 2267 #define BCM_CPRI_INTR_TX_FRM_ARB_PSIZE_ZERO _shrCpriIntrTxFrmArbPsizeZero /* decap sop control word 2268 packet size = 0 */ 2269 #define BCM_CPRI_INTR_TX_FRM_ARB_CPRI_ACK_MISMATCH _shrCpriIntrTxFrmArbCpriAckMismatch /* arbiter cpri ack 2270 mismatch */ 2271 #define BCM_CPRI_INTR_TX_FRM_ARB_RSVD4_REQ_CONFLICT _shrCpriIntrTxFrmArbRsvd4ReqConflict /* arbiter RSVD4 req 2272 conflict */ 2273 #define BCM_CPRI_INTR_TX_FRM_ARB_RSVD4_ACK_MISALIGN _shrCpriIntrTxFrmArbRsvd4AckMisalign /* arbiter RSVD4 ack 2274 misaligned */ 2275 #define BCM_CPRI_INTR_TX_FRM_CWA_HDLC_BUF_OVERFLOW _shrCpriIntrTxFrmCwaHdlcBufferOverflow /* CPRI control asm hdlc 2276 (slow cm) buffer 2277 overflow */ 2278 #define BCM_CPRI_INTR_TX_FRM_CWA_FAST_ETH_BUF_OVERFLOW _shrCpriIntrTxFrmCwaFastEthBufferOverflow /* CPRI control asm fast 2279 Ethernet (fast cm) 2280 buffer overflow */ 2281 #define BCM_CPRI_INTR_TX_FRM_CWA_VSD_RAW_BUF_OVERFLOW _shrCpriIntrTxFrmCwaVsdRawBufferOverflow /* CPRI control asm vsd 2282 raw buffer overflow */ 2283 #define BCM_CPRI_INTR_TX_FRM_CWA_SDVM_BUF_OVERFLOW _shrCpriIntrTxFrmCwaSdvmBufferOverflow /* CPRI control asm Rsvd5 2284 buffer overflow */ 2285 #define BCM_CPRI_INTR_TX_FRM_MULTI_ETH_BUF_OVERFLOW _shrCpriIntrTxFrmMultiEthBufferOverflow /* RSVD4 control 2286 multi-msg eth buffer 2287 overflow */ 2288 #define BCM_CPRI_INTR_TX_FRM_MULTI_ETH_BUF_UNDERFLOW _shrCpriIntrTxFrmMultiEthBufferUnderflow /* RSVD4 control 2289 multi-msg eth buffer 2290 underflow */ 2291 #define BCM_CPRI_INTR_TX_GCW _shrCpriIntrTxGcw /* RSVD4 control 2292 multi-msg eth buffer 2293 underflow */ 2294 #define BCM_CPRI_INTR_TX_PCS_GBOX_OVERFLOW _shrCpriIntrTxPcsGboxOverflow /* gearbox buffer 2295 overflow */ 2296 #define BCM_CPRI_INTR_TX_PCS_GBOX_UNDERFLOW _shrCpriIntrTxPcsGboxUnderflow /* gearbox buffer 2297 underflow */ 2298 #define BCM_CPRI_INTR_TX_PCS_FIFO_OVERFLOW _shrCpriIntrTxPcsFifoOverflow /* TX assembly FIFO 2299 overflow */ 2300 #define BCM_CPRI_INTR_TX_PCS_FIFO_UNDERFLOW _shrCpriIntrTxPcsFifoUnderflow /* TX assembly FIFO 2301 underflow */ 2302 2303 /* CPRI port interrupt info */ 2304 typedef _shr_cpri_intr_info_t bcm_cpri_interrupt_info_t; 2305 2306 #define BCM_CPRI_INTR_DATA_NUM_OF_DATA64 _shrIntrDataNumOfData64 2307 2308 /* CPRI interrupt data, ths is sent to the user registered callback */ 2309 typedef bcm_cpri_interrupt_info_t bcm_cpri_interrupt_data_t; 2310 2311 /* 2312 * Callback function used for receiving notification about CPRI port RX, 2313 * TX, 1588 interrupts. 2314 */ 2315 typedef void (*bcm_cpri_port_interrupt_callback_t)( 2316 int unit, 2317 bcm_port_t port, 2318 bcm_cpri_interrupt_data_t *data, 2319 void *userdata); 2320 2321 #ifndef BCM_HIDE_DISPATCHABLE 2322 2323 /* Register/Unregsiter callback function for CPRI port interrupts. */ 2324 extern int bcm_cpri_port_interrupt_callback_register( 2325 int unit, 2326 bcm_cpri_interrupt_type_t cpri_intr_type, 2327 bcm_cpri_port_interrupt_callback_t callback, 2328 void *user_data); 2329 2330 /* Register/Unregsiter callback function for CPRI port interrupts. */ 2331 extern int bcm_cpri_port_interrupt_callback_unregister( 2332 int unit, 2333 bcm_cpri_interrupt_type_t cpri_intr_type, 2334 bcm_cpri_port_interrupt_callback_t callback); 2335 2336 /* Set Enable/Disable CPRI port interrupts base on type and index.. */ 2337 extern int bcm_cpri_port_interrupt_enable_set( 2338 int unit, 2339 bcm_port_t port, 2340 bcm_cpri_interrupt_type_t cpri_intr_type, 2341 int data, 2342 int enable); 2343 2344 /* Get Enable/Disable CPRI port interrupts base on type and index. */ 2345 extern int bcm_cpri_port_interrupt_enable_get( 2346 int unit, 2347 bcm_port_t port, 2348 bcm_cpri_interrupt_type_t cpri_intr_type, 2349 int data, 2350 int *enable); 2351 2352 #endif /* BCM_HIDE_DISPATCHABLE */ 2353 2354 /* Cpri direction info */ 2355 typedef _shr_cpri_dir_t bcm_cpri_dir_t; 2356 2357 /* CPRI directions flags */ 2358 #define BCM_CPRI_DIR_TX _shrCpriDirTx 2359 #define BCM_CPRI_DIR_RX _shrCpriDirRx 2360 2361 /* Cpri capture mode info */ 2362 typedef _shr_cpri_1588_capture_mode_t bcm_cpri_1588_capture_mode_t; 2363 2364 /* CPRI port 1588 timestamp capture modes */ 2365 #define BCM_CPRI_1588_MATCH_BFN_AND_HFN _shrCpri1588CaptureModeMatchBfnHfn /* */ 2366 #define BCM_CPRI_1588_MATCH_HFN_ONLY _shrCpri1588CaptureModeMatchHfnOnly /* */ 2367 2368 /* CPRI 1588 Timestamp capture config information. */ 2369 typedef struct bcm_cpri_1588_capture_config_s { 2370 bcm_cpri_1588_capture_mode_t mode; /* Timestamp Capture type */ 2371 uint32 capture_bfn_num; /* if RSVD4, upper 12 bits of msg grp 2372 count */ 2373 uint32 capture_hfn_num; /* if RSVD4, lower 8 bits of msg grp 2374 count */ 2375 } bcm_cpri_1588_capture_config_t; 2376 2377 #ifndef BCM_HIDE_DISPATCHABLE 2378 2379 /* Configure port 1588 timestamp capture once. */ 2380 extern int bcm_cpri_port_1588_timestamp_capture_config_set( 2381 int unit, 2382 bcm_port_t port, 2383 bcm_cpri_dir_t direction, 2384 bcm_cpri_1588_capture_config_t *config); 2385 2386 /* Configure port 1588 timestamp capture once. */ 2387 extern int bcm_cpri_port_1588_timestamp_capture_config_get( 2388 int unit, 2389 bcm_port_t port, 2390 bcm_cpri_dir_t direction, 2391 bcm_cpri_1588_capture_config_t *config); 2392 2393 #endif /* BCM_HIDE_DISPATCHABLE */ 2394 2395 /* CPRI 1588 Timestamp config information. */ 2396 typedef struct bcm_cpri_1588_config_s { 2397 uint64 nano_sec; /* 48 bits only */ 2398 uint8 sub_nano_sec; /* 4 bits only */ 2399 uint8 sign_bit; /* 1 bit only */ 2400 } bcm_cpri_1588_config_t; 2401 2402 #ifndef BCM_HIDE_DISPATCHABLE 2403 2404 /* Configure CPRI port 1588 timestamp adjust value. */ 2405 extern int bcm_cpri_port_1588_timestamp_config_set( 2406 int unit, 2407 bcm_port_t port, 2408 bcm_cpri_dir_t direction, 2409 bcm_cpri_1588_config_t *config); 2410 2411 /* Configure CPRI port 1588 timestamp adjust value. */ 2412 extern int bcm_cpri_port_1588_timestamp_config_get( 2413 int unit, 2414 bcm_port_t port, 2415 bcm_cpri_dir_t direction, 2416 bcm_cpri_1588_config_t *config); 2417 2418 #endif /* BCM_HIDE_DISPATCHABLE */ 2419 2420 /* Cpri timestamp capture type info */ 2421 typedef _shr_cpri_1588_ts_type_t bcm_cpri_1588_ts_type_t; 2422 2423 /* CPRI port 1588 timestamp capture types */ 2424 #define BCM_CPRI_1588_TS_TYPE_FIFO _shrCpri1588TsTypeFifo /* */ 2425 #define BCM_CPRI_1588_TS_TYPE_CMIC _shrCpri1588TsTypeCMIC /* */ 2426 #define BCM_CPRI_1588_TS_TYPE_SW _shrCpri1588TsTypeSw /* */ 2427 2428 /* Cpri timestamp ts config info */ 2429 typedef struct bcm_cpri_1588_timestamp_ts_config_s { 2430 int enable; /* enable/disable */ 2431 uint32 modulo_count; /* modulo count */ 2432 } bcm_cpri_1588_timestamp_ts_config_t; 2433 2434 #ifndef BCM_HIDE_DISPATCHABLE 2435 2436 /* Configure CPRI port 1588 timestamp for repeating timestamp capture. */ 2437 extern int bcm_cpri_port_1588_timestamp_ts_config_set( 2438 int unit, 2439 bcm_port_t port, 2440 bcm_cpri_dir_t direction, 2441 bcm_cpri_1588_ts_type_t type, 2442 bcm_cpri_1588_timestamp_ts_config_t *config); 2443 2444 /* Configure CPRI port 1588 timestamp for repeating timestamp capture. */ 2445 extern int bcm_cpri_port_1588_timestamp_ts_config_get( 2446 int unit, 2447 bcm_port_t port, 2448 bcm_cpri_dir_t direction, 2449 bcm_cpri_1588_ts_type_t type, 2450 bcm_cpri_1588_timestamp_ts_config_t *config); 2451 2452 #endif /* BCM_HIDE_DISPATCHABLE */ 2453 2454 /* Cpri timestamp value */ 2455 typedef uint64 bcm_cpri_1588_timestamp_t; 2456 2457 #ifndef BCM_HIDE_DISPATCHABLE 2458 2459 /* Get CPRI port 1588 captured timestamp. */ 2460 extern int bcm_cpri_port_1588_timestamp_get( 2461 int unit, 2462 bcm_port_t port, 2463 bcm_cpri_dir_t direction, 2464 bcm_cpri_1588_ts_type_t type, 2465 int max_count, 2466 int *count, 2467 bcm_cpri_1588_timestamp_t *ts_list); 2468 2469 #endif /* BCM_HIDE_DISPATCHABLE */ 2470 2471 /* multiples of basic frame length */ 2472 typedef _shr_cpri_roe_payload_multiple_t bcm_cpri_roe_payload_multiple_t; 2473 2474 #define BCM_CPRI_PAYLOAD_MULTIPLE_BASIC_FRAME_1X _shrCpriPayloadMultiple1X 2475 #define BCM_CPRI_PAYLOAD_MULTIPLE_BASIC_FRAME_1P5X _shrCpriPayloadMultiple1p5X 2476 #define BCM_CPRI_PAYLOAD_MULTIPLE_BASIC_FRAME_2X _shrCpriPayloadMultiple2X 2477 #define BCM_CPRI_PAYLOAD_MULTIPLE_BASIC_FRAME_4X _shrCpriPayloadMultiple4X 2478 #define BCM_CPRI_PAYLOAD_MULTIPLE_BASIC_FRAME_8X _shrCpriPayloadMultiple8X 2479 2480 /* CPRI Order Info Type .orderInfoType. */ 2481 typedef _shr_cpri_roe_ordering_info_option_t bcm_cpri_ordering_info_option_t; 2482 2483 /* CPRI Order Info Type .orderInfoType */ 2484 #define BCM_CPRI_ORDERING_INFO_OPTION_SEQ_NUM _shrCpriRoeOrderingInfoOptionSeqNum /* Sequnece number in 2485 ordering info. */ 2486 #define BCM_CPRI_ORDERING_INFO_OPTION_TIMESTAMP _shrCpriRoeOrderingInfoOptionTimestamp /* Timestamp in ordering 2487 info */ 2488 2489 /* CPRI agnostic configuration */ 2490 typedef struct bcm_cpri_port_agnostic_config_s { 2491 bcm_cpri_frame_sync_mode_t frame_sync_mode; /* Radio, Hyper or Basic */ 2492 uint32 basic_frame_offset; /* Basic frame offset */ 2493 uint32 radio_frame_offset; /* Radio frame offset */ 2494 uint32 hyper_frame_offset; /* Hyper frame offset */ 2495 bcm_cpri_roe_payload_multiple_t payload_multiple; /* ROE payload size */ 2496 uint32 presentation_mod_count; /* timestamp filtering */ 2497 uint32 presentation_mod_offset; /* tx only */ 2498 uint32 tx_queue_mod_cnt; /* jitter buffer cycle size tx only */ 2499 bcm_cpri_ordering_info_option_t ordering_info_option; /* Ordering info option. */ 2500 } bcm_cpri_port_agnostic_config_t; 2501 2502 #ifndef BCM_HIDE_DISPATCHABLE 2503 2504 /* API to set/get the agnostic mode and its configuration. */ 2505 extern int bcm_cpri_port_agnostic_config_set( 2506 int unit, 2507 bcm_port_t port, 2508 bcm_cpri_dir_t dir, 2509 int enable, 2510 bcm_cpri_port_agnostic_config_t *config); 2511 2512 /* API to set/get the agnostic mode and its configuration. */ 2513 extern int bcm_cpri_port_agnostic_config_get( 2514 int unit, 2515 bcm_port_t port, 2516 bcm_cpri_dir_t dir, 2517 int *enable, 2518 bcm_cpri_port_agnostic_config_t *config); 2519 2520 #endif /* BCM_HIDE_DISPATCHABLE */ 2521 2522 /* Cpri encapsulation presentation timestamp attribute */ 2523 typedef _shr_cpri_presentation_ts_attribute_t bcm_cpri_presentation_ts_attribute_t; 2524 2525 #define BCM_CPRI_ENCAP_PRESENTATION_TS_ADJUST _shrCpriEncapPresentationTsAdjust 2526 #define BCM_CPRI_ENCAP_PRESENTATION_APPROX_INC _shrCpriEncapPresentationApproxInc 2527 2528 /* Cpri presentation time */ 2529 typedef _shr_cpri_presentation_time_t bcm_cpri_presentation_time_t; 2530 2531 #ifndef BCM_HIDE_DISPATCHABLE 2532 2533 /* API to set/get the presentation attribute. */ 2534 extern int bcm_cpri_encap_presentation_time_config_set( 2535 int unit, 2536 bcm_port_t port, 2537 bcm_cpri_presentation_ts_attribute_t attribute, 2538 bcm_cpri_presentation_time_t *time); 2539 2540 /* API to set/get the presentation attribute. */ 2541 extern int bcm_cpri_encap_presentation_time_config_get( 2542 int unit, 2543 bcm_port_t port, 2544 bcm_cpri_presentation_ts_attribute_t attribute, 2545 bcm_cpri_presentation_time_t *time_offset); 2546 2547 #endif /* BCM_HIDE_DISPATCHABLE */ 2548 2549 /* Cpri decap presentation config */ 2550 typedef _shr_cpri_decap_presentation_config_t bcm_cpri_decap_presentation_config_t; 2551 2552 #ifndef BCM_HIDE_DISPATCHABLE 2553 2554 /* API to set/get the decap presentation time. */ 2555 extern int bcm_cpri_decap_presentation_time_config_set( 2556 int unit, 2557 bcm_port_t port, 2558 bcm_cpri_decap_presentation_config_t *config); 2559 2560 /* API to set/get the decap presentation time. */ 2561 extern int bcm_cpri_decap_presentation_time_config_get( 2562 int unit, 2563 bcm_port_t port, 2564 bcm_cpri_decap_presentation_config_t *config); 2565 2566 #endif /* BCM_HIDE_DISPATCHABLE */ 2567 2568 /* CPRI Port stats */ 2569 typedef enum bcm_cpri_stat_type_e { 2570 bcmCpriStatRxSymbolErr = 0, /* Rx Bytes Symbol Error Count. */ 2571 bcmCpriStatRxSeedMismatch = 1, /* Rx Seed Mismatch Count. */ 2572 bcmCpriStatRxStateErrTransition = 2, /* Rx number of transuition into Err 2573 state. */ 2574 bcmCpriStatTxVsdCtrlFlowIdErr = 3, /* Tx Vsd Control Flow ID out of range 2575 (0..127) error Count. */ 2576 bcmCpriStatTxVsdCtrlPktSizeErr = 4, /* Tx Vsd Control Packet size error 2577 count. >16 bytes. */ 2578 bcmCpriStatTxVsdRawPktSizeErr = 5, /* Tx Vsd Raw Packet size error count. */ 2579 bcmCpriStatTxRsvd5CrcErr = 6, /* Tx RSVD5 Dropped Packet Count due to 2580 CRC error. */ 2581 bcmCpriStatRxRsvd4SingleMsgCrcErr = 7, /* Rx RSVD4 Control Single Message 2582 Dropped Packet Count due to CRC 2583 error. */ 2584 bcmCpriStatRxTagLookupFailed = 8, /* Rx Tag Look up failed Count. */ 2585 bcmCpriStatRxRsvd4SingleMsgCnt = 9, /* Rx RSVD4 Single Message Count . */ 2586 bcmCpriStatRxRsvd4MultiMsgCnt = 10, /* Rx RSVD4 Multi Message Count. */ 2587 bcmCpriStatRxRsvd4MultiMsgSeqErr = 11, /* Rx RSVD4 Multi Message Sequence Error 2588 Count. */ 2589 bcmCpriStatRxDataByteErr = 12, /* Rx Data Bytes in Error. */ 2590 bcmCpriStatRxRsvd4HeaderErr = 13, /* Rx RSVD4 Dropped Messages Due to 2591 Header Error. */ 2592 bcmCpriStatRxRsvd4HeaderNoMatch = 14, /* Rx RSVD4 Messags Header No Match 2593 Found. */ 2594 bcmCpriStatRxRsvd4MsgCnt = 15, /* Rx RSVD4 Total Message Count. */ 2595 bcmCpriStatRxHfnErr = 16, /* Rx incorrect Hyper frame 2596 number(HFN). */ 2597 bcmCpriStatRxBfnErr = 17, /* Rx incorrect Radio frame 2598 number(BFN). */ 2599 bcmCpriStatRxCtrlWordErr = 18, /* Rx Control Word Error. */ 2600 bcmCpriStatRxGcwErr = 19, /* Rx GCW Dropped Words due to Byte 2601 Error. */ 2602 bcmCpriStatRxVsdRawErr = 20, /* Rx VSD Raw Dropped packets Due to 2603 byte error. */ 2604 bcmCpriStatRxVsdCtrlErr = 21, /* Rx VSD Control Dropped packets Due 2605 to byte error. */ 2606 bcmCpriStatTxRsvd4DataMsgCnt = 22, /* Tx Rsvd4 Data Message Count. */ 2607 bcmCpriStatTxRsvd4DataEmptyMsgCnt = 23, /* Tx Rsvd4 Data Empty Message Count. */ 2608 bcmCpriStatTxRsvd4CtrlMsgCnt = 24, /* Tx Rsvd4 Control Message Count. */ 2609 bcmCpriStatTxRsvd4CtrlEmptyMsgCnt = 25, /* Tx Rsvd4 Control Empty Message 2610 Count. */ 2611 bcmCpriStatRxRsvd5ParityErr = 26, /* Rx RSVD5 Parity Errored Message 2612 Count. */ 2613 bcmCpriStatRxHdlcErrFrame = 27, /* Rx HDLC Errored frame Count. */ 2614 bcmCpriStatRxHdlcGoodFrame = 28, /* Rx HDLC Good Frame Count. */ 2615 bcmCpriStatRxFastEthDroppedPkt = 29, /* Rx Fast Ethernet Dropped Packet. */ 2616 bcmCpriStatRxFastEthGoodPkt = 30, /* Rx Fast Ethernet Good Packet. */ 2617 bcmCpriStatMax = 31 /* Last One. */ 2618 } bcm_cpri_stat_type_t; 2619 2620 #ifndef BCM_HIDE_DISPATCHABLE 2621 2622 /* API to retrieve the CPRI port stats. */ 2623 extern int bcm_cpri_port_stat_get( 2624 int unit, 2625 bcm_gport_t port, 2626 bcm_cpri_stat_type_t type, 2627 uint64 *val); 2628 2629 /* Enable/Disable FEC. */ 2630 extern int bcm_cpri_port_fec_enable_set( 2631 int unit, 2632 bcm_gport_t port, 2633 bcm_cpri_dir_t dir, 2634 int enable); 2635 2636 /* Enable/Disable FEC. */ 2637 extern int bcm_cpri_port_fec_enable_get( 2638 int unit, 2639 bcm_gport_t port, 2640 bcm_cpri_dir_t dir, 2641 int *enable); 2642 2643 #endif /* BCM_HIDE_DISPATCHABLE */ 2644 2645 /* Cpri FEC timestamp source */ 2646 typedef _shr_cpri_fec_ts_source_t bcm_cpri_fec_ts_source_t; 2647 2648 #define BCM_CPRI_FEC_TS_SOURCE_66b _shrCpriFecTsSource66b 2649 #define BCM_CPRI_FEC_TS_SOURCE_257b _shrCpriFecTsSource257b 2650 2651 /* Cpri FEC timestamp config info */ 2652 typedef struct bcm_cpri_fec_timestamp_config_s { 2653 int enable; /* Enable/Disable. */ 2654 bcm_cpri_fec_ts_source_t fec_fifo_ts_source_select; /* Source 66 bit or 257 bit. */ 2655 bcm_cpri_fec_ts_source_t fec_cmic_ts_source_select; /* Source 66 bit or 257 bit. */ 2656 uint32 control_bit_offset_0; /* Control Bit Offset. */ 2657 uint32 control_bit_offset_1; /* Control Bit Offset. */ 2658 uint32 control_bit_offset_2; /* Control Bit Offset. */ 2659 uint32 control_bit_offset_3; /* Control Bit Offset. */ 2660 } bcm_cpri_fec_timestamp_config_t; 2661 2662 #ifndef BCM_HIDE_DISPATCHABLE 2663 2664 /* Setup FEC related timestamp configuration. */ 2665 extern int bcm_cpri_port_fec_timestamp_config_set( 2666 int unit, 2667 bcm_gport_t port, 2668 bcm_cpri_dir_t dir, 2669 bcm_cpri_fec_timestamp_config_t *config); 2670 2671 /* Setup FEC related timestamp configuration. */ 2672 extern int bcm_cpri_port_fec_timestamp_config_get( 2673 int unit, 2674 bcm_gport_t port, 2675 bcm_cpri_dir_t dir, 2676 bcm_cpri_fec_timestamp_config_t *config); 2677 2678 #endif /* BCM_HIDE_DISPATCHABLE */ 2679 2680 /* Cpri FEC aux config para */ 2681 typedef _shr_cpri_fec_aux_config_t bcm_cpri_fec_aux_config_t; 2682 2683 #define BCM_CPRI_FEC_AUX_CONFIG_SCRAMBLE_BYPASS_TX _shrCpriFecAuxConfigScrambleBypassTx 2684 #define BCM_CPRI_FEC_AUX_CONFIG_DESCRAMBLE_BYPASS_RX _shrCpriFecAuxConfigDescrambleBypassRx 2685 #define BCM_CPRI_FEC_AUX_CONFIG_BYPASS_INDICATION_ENABLE _shrCpriFecAuxConfigBypassIndicationEnable 2686 #define BCM_CPRI_FEC_AUX_CONFIG_BYPASS_CORRECTION_ENABLE _shrCpriFecAuxConfigBypassCorrectionEnable 2687 #define BCM_CPRI_FEC_AUX_CONFIG_CORRUPT_ALTERNATE_BLOCKS_ENABLE _shrCpriFecAuxConfigCorruptAlternateBlocksEnable 2688 #define BCM_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_CORRUPT_ENABLE _shrCpriFecAuxConfigSymbolErrorCorruptEnable 2689 #define BCM_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_TMR_PERIOD _shrCpriFecAuxConfigSymbolErrorTmrPeriod 2690 #define BCM_CPRI_FEC_AUX_CONFIG_SYMBOL_ERR_CNT_THRESHOLD _shrCpriFecAuxConfigSymbolErrCntThreshold 2691 #define BCM_CPRI_FEC_AUX_CONFIG_SET_SYMB_ERR_WINDOW_128 _shrCpriFecAuxConfigSetSymbErrWindow128 2692 #define BCM_CPRI_FEC_AUX_CONFIG_GBOX_TICK_DENOMINATOR _shrCpriFecAuxConfigGboxTickDenominator 2693 #define BCM_CPRI_FEC_AUX_CONFIG_GBOX_TICK_NUMERATOR _shrCpriFecAuxConfigGboxTickNumerator 2694 #define BCM_CPRI_FEC_AUX_CONFIG_SOFT_RESET _shrCpriFecAuxConfigSoftReset 2695 2696 #ifndef BCM_HIDE_DISPATCHABLE 2697 2698 /* Setup Auxiliary configuration for FEC. */ 2699 extern int bcm_cpri_port_fec_aux_config_set( 2700 int unit, 2701 bcm_gport_t port, 2702 bcm_cpri_fec_aux_config_t param_id, 2703 uint32 value); 2704 2705 /* Setup Auxiliary configuration for FEC. */ 2706 extern int bcm_cpri_port_fec_aux_config_get( 2707 int unit, 2708 bcm_gport_t port, 2709 bcm_cpri_fec_aux_config_t param_id, 2710 uint32 *value); 2711 2712 #endif /* BCM_HIDE_DISPATCHABLE */ 2713 2714 /* Cpri FEC Counter type. */ 2715 typedef _shr_cpri_fec_stat_type_t bcm_cpri_fec_stat_type_t; 2716 2717 #define BCM_CPRI_FEC_STAT_CORRECTED_CODEWORD _shrCpriFecStatTypeCorrectedCodeword 2718 #define BCM_CPRI_FEC_STAT_UNCORRECTED_CODEWORD _shrCpriFecStatTypeUncorrectedCodeword 2719 #define BCM_CPRI_FEC_STAT_BIT_ERROR _shrCpriFecStatTypeBitError 2720 #define BCM_CPRI_FEC_STAT_SYMBOL_ERROR _shrCpriFecStatTypeSymbolError 2721 #define BCM_CPRI_FEC_STAT_INVALID _shrCpriFecStatTypeInvalid 2722 2723 #ifndef BCM_HIDE_DISPATCHABLE 2724 2725 /* Get the FEC Statistic Counter */ 2726 extern int bcm_cpri_port_fec_stat_get( 2727 int unit, 2728 bcm_gport_t port, 2729 bcm_cpri_fec_stat_type_t type, 2730 uint32 *counter_value); 2731 2732 /* Set and Program Compression Table. */ 2733 extern int bcm_cpri_port_compression_lookup_table_set( 2734 int unit, 2735 bcm_gport_t port, 2736 int table_depth, 2737 uint32 *comp_table); 2738 2739 /* Set and Program Compression Table. */ 2740 extern int bcm_cpri_port_compression_lookup_table_get( 2741 int unit, 2742 bcm_gport_t port, 2743 int max_depth, 2744 int *table_depth, 2745 uint32 *comp_table); 2746 2747 /* Set and Program DeCompression Table. */ 2748 extern int bcm_cpri_port_decompression_lookup_table_set( 2749 int unit, 2750 bcm_gport_t port, 2751 int table_depth, 2752 uint32 *comp_table); 2753 2754 /* Set and Program DeCompression Table. */ 2755 extern int bcm_cpri_port_decompression_lookup_table_get( 2756 int unit, 2757 bcm_gport_t port, 2758 int max_depth, 2759 int *table_depth, 2760 uint32 *comp_table); 2761 2762 /* Set Decapsulation Queue Flow Control configuration. */ 2763 extern int bcm_cpri_port_decap_queue_flow_control_set( 2764 int unit, 2765 bcm_gport_t port, 2766 uint32 queue_num, 2767 uint32 xon_threshold, 2768 uint32 xoff_threshold, 2769 int enable); 2770 2771 /* Get Decapsulation Queue Flow Control configuration. */ 2772 extern int bcm_cpri_port_decap_queue_flow_control_get( 2773 int unit, 2774 bcm_gport_t port, 2775 uint32 queue_num, 2776 uint32 *xon_threshold, 2777 uint32 *xoff_threshold, 2778 int *enable); 2779 2780 /* Get Rx GCW word. */ 2781 extern int bcm_cpri_port_rx_cw_gcw_word_get( 2782 int unit, 2783 bcm_port_t port, 2784 int group_index, 2785 uint16 *gcw_word); 2786 2787 /* Set Tx GCW word. */ 2788 extern int bcm_cpri_port_tx_cw_gcw_word_set( 2789 int unit, 2790 bcm_port_t port, 2791 int group_index, 2792 uint16 gcw_word); 2793 2794 #endif /* BCM_HIDE_DISPATCHABLE */ 2795 2796 /* CPRI Tunnel Mode Configuration. */ 2797 typedef struct bcm_cpri_port_tunnel_config_s { 2798 uint32 payload_size; /* RoE payload size. In bytes. */ 2799 bcm_cpri_ordering_info_option_t ordering_info_option; /* Ordering info option. */ 2800 uint32 presentation_mod_count; /* Mod Count for Presentation time. */ 2801 uint32 presentation_mod_offset; /* Mod Offset for Presentation time. */ 2802 uint32 tx_queue_mod_count; /* Jitter buffer cycle size, Tx Only. */ 2803 } bcm_cpri_port_tunnel_config_t; 2804 2805 #ifndef BCM_HIDE_DISPATCHABLE 2806 2807 /* Set tunnel Mode configuration. */ 2808 extern int bcm_cpri_port_tunnel_mode_config_set( 2809 int unit, 2810 bcm_port_t port, 2811 bcm_cpri_dir_t direction, 2812 int enable, 2813 bcm_cpri_port_tunnel_config_t *config); 2814 2815 /* Set tunnel Mode configuration. */ 2816 extern int bcm_cpri_port_tunnel_mode_config_get( 2817 int unit, 2818 bcm_port_t port, 2819 bcm_cpri_dir_t direction, 2820 int *enable, 2821 bcm_cpri_port_tunnel_config_t *config); 2822 2823 #endif /* BCM_HIDE_DISPATCHABLE */ 2824 2825 /* CPRI RSVD4 Agnostic Mode Configuration. */ 2826 typedef struct bcm_cpri_port_rsvd4_agnostic_config_s { 2827 bcm_cpri_ordering_info_option_t ordering_info_option; /* Ordering info option. */ 2828 bcm_rsvd4_sync_mode_t sync_mode; /* Sync Mode */ 2829 uint32 payload_multiple; /* Multiple of Message group 1-3. */ 2830 uint32 master_frame_offset; /* Master Frame Offset for Sync */ 2831 uint32 message_group_offset; /* Message Group Offset for Sync */ 2832 uint32 presentation_mod_count; /* Mod Count for Presentation time. */ 2833 uint32 presentation_mod_offset; /* Mod Offset for Presentation time. */ 2834 uint32 tx_queue_mod_count; /* Jitter buffer cycle size, Tx Only. */ 2835 } bcm_cpri_port_rsvd4_agnostic_config_t; 2836 2837 #ifndef BCM_HIDE_DISPATCHABLE 2838 2839 /* Set RSVD4 Agnostic Mode configuration. */ 2840 extern int bcm_cpri_port_rsvd4_agnostic_mode_config_set( 2841 int unit, 2842 bcm_port_t port, 2843 bcm_cpri_dir_t direction, 2844 int enable, 2845 bcm_cpri_port_rsvd4_agnostic_config_t *config); 2846 2847 /* Set RSVD4 Agnostic Mode configuration. */ 2848 extern int bcm_cpri_port_rsvd4_agnostic_mode_config_get( 2849 int unit, 2850 bcm_port_t port, 2851 bcm_cpri_dir_t direction, 2852 int *enable, 2853 bcm_cpri_port_rsvd4_agnostic_config_t *config); 2854 2855 #endif /* BCM_HIDE_DISPATCHABLE */ 2856 2857 /* CPRI RoE Header Field, */ 2858 typedef _shr_cpri_roe_header_field_t bcm_cpri_roe_header_field_t; 2859 2860 #define BCM_CPRI_ROE_HEADER_FIELD_SUBTYPE _shrCpriRoeHeaderFieldSubType 2861 #define BCM_CPRI_ROE_HEADER_FIELD_FLOW_ID _shrCpriRoeHeaderFieldFlowID 2862 #define BCM_CPRI_ROE_HEADER_FIELD_LENGTH_15_8 _shrCpriRoeHeaderFieldLength_15_8 2863 #define BCM_CPRI_ROE_HEADER_FIELD_LENGTH_7_0 _shrCpriRoeHeaderFieldLength_7_0 2864 #define BCM_CPRI_ROE_HEADER_FIELD_ORDER_INFO_32_34 _shrCpriRoeHeaderFieldOrderInfo_32_24 2865 #define BCM_CPRI_ROE_HEADER_FIELD_ORDER_INFO_23_16 _shrCpriRoeHeaderFieldOrderInfo_23_16 2866 #define BCM_CPRI_ROE_HEADER_FIELD_ORDER_INFO_15_8 _shrCpriRoeHeaderFieldOrderInfo_15_8 2867 #define BCM_CPRI_ROE_HEADER_FIELD_ORDER_INFO_7_0 _shrCpriRoeHeaderFieldOrderInfo_7_0 2868 #define BCM_CPRI_ROE_HEADER_FIELD_OPCODE _shrCpriRoeHeaderFieldOpcode 2869 #define BCM_CPRI_ROE_HEADER_FIELD_UNMAPPED _shrCpriRoeHeaderFieldUnmapped 2870 2871 /* CPRI eCPRI Header Field, */ 2872 typedef _shr_cpri_ecpri_header_field_t bcm_cpri_ecpri_header_field_t; 2873 2874 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_0 _shrCpriEcpriHeaderFieldByte0 2875 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_1 _shrCpriEcpriHeaderFieldByte1 2876 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_2 _shrCpriEcpriHeaderFieldByte2 2877 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_3 _shrCpriEcpriHeaderFieldByte3 2878 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_4 _shrCpriEcpriHeaderFieldByte4 2879 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_5 _shrCpriEcpriHeaderFieldByte5 2880 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_6 _shrCpriEcpriHeaderFieldByte6 2881 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_7 _shrCpriEcpriHeaderFieldByte7 2882 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_8 _shrCpriEcpriHeaderFieldByte8 2883 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_9 _shrCpriEcpriHeaderFieldByte9 2884 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_10 _shrCpriEcpriHeaderFieldByte10 2885 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_11 _shrCpriEcpriHeaderFieldByte11 2886 #define BCM_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_0 _shrCpriEcpriHeaderFieldVlan0Byte0 2887 #define BCM_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_1 _shrCpriEcpriHeaderFieldVlan0Byte1 2888 #define BCM_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_0 _shrCpriEcpriHeaderFieldVlan1Byte0 2889 #define BCM_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_1 _shrCpriEcpriHeaderFieldVlan1Byte1 2890 2891 /* CPRI RoE Frame Configuration. */ 2892 typedef struct bcm_cpri_port_frame_config_s { 2893 bcm_cpri_roe_frame_format_t port_frame_format; /* Port Frame Format. */ 2894 bcm_cpri_ecpri_header_field_t decap_primary_key; /* Decap Primary Key */ 2895 bcm_cpri_ecpri_header_field_t decap_secondary_key; /* Decap Secondary Key. */ 2896 } bcm_cpri_port_frame_config_t; 2897 2898 #ifndef BCM_HIDE_DISPATCHABLE 2899 2900 /* Set RoE frame format for the port. */ 2901 extern int bcm_cpri_port_frame_config_set( 2902 int unit, 2903 bcm_port_t port, 2904 bcm_cpri_port_frame_config_t *config); 2905 2906 /* Configure decap secondary key to queue mapping. */ 2907 extern int bcm_cpri_port_decap_secondary_key_to_queue_mapping_set( 2908 int unit, 2909 bcm_port_t port, 2910 uint32 secondary_key, 2911 uint32 queue_num); 2912 2913 /* Configure decap secondary key to queue mapping. */ 2914 extern int bcm_cpri_port_decap_secondary_key_to_queue_mapping_get( 2915 int unit, 2916 bcm_port_t port, 2917 uint32 secondary_key, 2918 uint32 *queue_num); 2919 2920 /* Set Compression Saturation Threshold Value. */ 2921 extern int bcm_cpri_port_compression_saturation_config_set( 2922 int unit, 2923 bcm_port_t port, 2924 uint32 threshold_value); 2925 2926 /* Set Compression Saturation Threshold Value. */ 2927 extern int bcm_cpri_port_compression_saturation_config_get( 2928 int unit, 2929 bcm_port_t port, 2930 uint32 *threshold_value); 2931 2932 /* Set/Get DeCompression Saturation Value. */ 2933 extern int bcm_cpri_port_decompression_saturation_config_set( 2934 int unit, 2935 bcm_port_t port, 2936 uint32 sat_value); 2937 2938 /* Set/Get DeCompression Saturation Value. */ 2939 extern int bcm_cpri_port_decompression_saturation_config_get( 2940 int unit, 2941 bcm_port_t port, 2942 uint32 *sat_value); 2943 2944 /* Clear Rx Data Path in Framer and Encapsulation. */ 2945 extern int bcm_cpri_port_rx_pipeline_clear( 2946 int unit, 2947 bcm_gport_t port); 2948 2949 /* Clear Tx Data Path in Framer and Decapsulation. */ 2950 extern int bcm_cpri_port_tx_pipeline_clear( 2951 int unit, 2952 bcm_gport_t port); 2953 2954 /* Get tx enable status */ 2955 extern int bcm_cpri_port_tx_enable_get( 2956 int unit, 2957 bcm_gport_t port, 2958 int *enable); 2959 2960 /* Set tx enable */ 2961 extern int bcm_cpri_port_tx_enable_set( 2962 int unit, 2963 bcm_gport_t port, 2964 int enable); 2965 2966 #endif /* BCM_HIDE_DISPATCHABLE */ 2967 2968 /* CPRI Speed Scan Port Information. */ 2969 typedef struct bcm_cpri_speed_scan_port_info_s { 2970 int link_status; /* Link Status. */ 2971 bcm_cpri_port_speed_t speed; /* CPRI port speed. */ 2972 } bcm_cpri_speed_scan_port_info_t; 2973 2974 /* Callback function used for speed scan to notify link status change.. */ 2975 typedef void (*bcm_cpri_speed_scan_handler_t)( 2976 int unit, 2977 bcm_port_t port, 2978 bcm_cpri_speed_scan_port_info_t *port_info, 2979 void *userdata); 2980 2981 #ifndef BCM_HIDE_DISPATCHABLE 2982 2983 /* Initialize the CPRI Speed Scan. */ 2984 extern int bcm_cpri_speed_scan_init( 2985 int unit); 2986 2987 /* CPRI Speed Scan unit level configuration. */ 2988 extern int bcm_cpri_speed_scan_config_set( 2989 int unit, 2990 int interval_in_us, 2991 int enable); 2992 2993 /* CPRI Speed Scan unit level configuration. */ 2994 extern int bcm_cpri_speed_scan_config_get( 2995 int unit, 2996 int *interval_in_us, 2997 int *enable); 2998 2999 /* CPRI Adding port to speed scan list. */ 3000 extern int bcm_cpri_speed_scan_port_config_add( 3001 int unit, 3002 bcm_port_t port, 3003 bcm_cpri_port_speed_t *speed_list, 3004 int num_speed); 3005 3006 /* CPRI Delete port from speed scan list. */ 3007 extern int bcm_cpri_speed_scan_port_config_delete( 3008 int unit, 3009 bcm_port_t port); 3010 3011 /* CPRI Speed Scan Port configuration get. */ 3012 extern int bcm_cpri_speed_scan_port_config_get( 3013 int unit, 3014 bcm_port_t port, 3015 bcm_cpri_port_speed_t *speed_list, 3016 int num_element, 3017 int *num_speed); 3018 3019 /* Register handler function for CPRI speed scanning. */ 3020 extern int bcm_cpri_speed_scan_callback_register( 3021 int unit, 3022 bcm_cpri_speed_scan_handler_t callback, 3023 void *user_data); 3024 3025 /* UnRegister handler function for CPRI speed scanning. */ 3026 extern int bcm_cpri_speed_scan_callback_unregister( 3027 int unit, 3028 bcm_cpri_speed_scan_handler_t callback); 3029 3030 #endif /* BCM_HIDE_DISPATCHABLE */ 3031 3032 /* RSVD1 msg information */ 3033 typedef struct bcm_cpri_rsvd1_msg_s { 3034 uint32 rsvd1_msg0; /* msg0 */ 3035 uint32 rsvd1_msg1; /* msg1 */ 3036 uint32 rsvd1_msg2; /* msg2 */ 3037 } bcm_cpri_rsvd1_msg_t; 3038 3039 #ifndef BCM_HIDE_DISPATCHABLE 3040 3041 /* Function to retrieve rsvd1 message. */ 3042 extern int bcm_cpri_rsvd1_msg_get( 3043 int unit, 3044 bcm_cpri_rsvd1_msg_t *rsvd1_msg); 3045 3046 #endif /* BCM_HIDE_DISPATCHABLE */ 3047 3048 #endif /* __BCM_CPRI_H__ */