utils_line_PTG.h (5109B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 5 */ 6 7 8 #ifndef __UTILS_LINE_PTG_INCLUDED__ 9 /* { */ 10 #define __UTILS_LINE_PTG_INCLUDED__ 11 12 /************* 13 * INCLUDES * 14 */ 15 /* { */ 16 17 #if !DUNE_BCM 18 19 #include "DuneDriver/SAND/Utils/include/sand_framework.h" 20 21 #endif 22 23 /* } */ 24 /************* 25 * DEFINES * 26 */ 27 /* { */ 28 29 #define GFA_PETRA_BACK_END_IS_PETRA_GFA (TRUE) 30 31 #if GFA_PETRA_BACK_END_IS_PETRA_GFA 32 #define UTILS_PTG_FRONT_END_IO_FPGA_BASE_ADDR (0x50300000) 33 #define UTILS_PTG_FRONT_END_FILE_SYSTEM_FLASH_BASE_ADDR (0x50400000) 34 #define UTILS_PTG_FRONT_END_DEVICE_0_BASE_ADDR (0x50000000) 35 #define UTILS_PTG_FRONT_END_DEVICE_1_BASE_ADDR (0x50100000) 36 #else 37 #define UTILS_PTG_FRONT_END_IO_FPGA_BASE_ADDR (0x40700000) 38 #define UTILS_PTG_FRONT_END_FILE_SYSTEM_FLASH_BASE_ADDR (0x50400000) 39 #define UTILS_PTG_FRONT_END_DEVICE_0_BASE_ADDR (0x50000000) 40 #define UTILS_PTG_FRONT_END_DEVICE_1_BASE_ADDR (0x50100000) 41 #endif 42 43 #define UTILS_PTG_FRONT_END_IO_FPGA_SIZE (0x00100000) 44 #define UTILS_PTG_FRONT_END_FILE_SYSTEM_FLASH_SIZE (0x00100000) 45 #define UTILS_PTG_FRONT_END_DEVICE_0_SIZE (0x00100000) 46 #define UTILS_PTG_FRONT_END_DEVICE_1_SIZE (0x00100000) 47 48 #define UTILS_PTG_DEVICE_FRONT_END_PTG_0_RESET_BIT (4) 49 #define UTILS_PTG_DEVICE_FRONT_END_PTG_1_RESET_BIT (5) 50 #define UTILS_PTG_DEVICE_FRONT_END_IO_AGENT_RESET_BIT (6) 51 #define UTILS_PTG_DEVICE_FRONT_END_FLASH_RESET_BIT (7) 52 53 #define UTILS_PTG_DEVICE_FRONT_END_PTG_0_RESET (SOC_SAND_BIT(UTILS_PTG_DEVICE_FRONT_END_PTG_0_RESET_BIT)) 54 #define UTILS_PTG_DEVICE_FRONT_END_PTG_1_RESET (SOC_SAND_BIT(UTILS_PTG_DEVICE_FRONT_END_PTG_1_RESET_BIT)) 55 #define UTILS_PTG_DEVICE_FRONT_END_IO_AGENT_RESET (SOC_SAND_BIT(UTILS_PTG_DEVICE_FRONT_END_IO_AGENT_RESET_BIT)) 56 #define UTILS_PTG_DEVICE_FRONT_END_FLASH_RESET (SOC_SAND_BIT(UTILS_PTG_DEVICE_FRONT_END_FLASH_RESET_BIT)) 57 58 /* FILE_SYSTEM_FLASH { */ 59 #define UTILS_PTG_FILE_SYSTEM_FLASH_ADDR (UTILS_PTG_FRONT_END_FILE_SYSTEM_FLASH_BASE_ADDR) 60 #define UTILS_PTG_FILE_SYSTEM_FLASH_MAX_ADDR (UTILS_PTG_FILE_SYSTEM_FLASH_ADDR + UTILS_PTG_FRONT_END_FILE_SYSTEM_FLASH_SIZE - 1) 61 #define UTILS_PTG_FILE_SYSTEM_FLASH_SIZE (UTILS_PTG_FILE_SYSTEM_FLASH_MAX_ADDR - UTILS_PTG_FILE_SYSTEM_FLASH_ADDR + 1) 62 #define UTILS_PTG_FILE_SYSTEM_FLASH_SIZE_TO_USE (UTILS_PTG_FILE_SYSTEM_FLASH_SIZE - 12) 63 #define UTILS_PTG_FILE_SYSTEM_FLASH_TYPE (FLASH_28F640) 64 #define UTILS_PTG_FILE_SYSTEM_FLASH_SECTOR_SIZE (FLASH_28F320_SECTOR) /* two flashes*/ 65 #define UTILS_PTG_FILE_SYSTEM_FLASH_ADRS_JUMP (1) /* 4 bytes alignment */ 66 #define UTILS_PTG_FILE_SYSTEM_FLASH_WIDTH (4) /* two flashes-> 4 bytes alignment */ 67 /* } FILE_SYSTEM_FLASH */ 68 69 /* IO_AGENT_FPGA { */ 70 #define UTILS_PTG_IO_AGENT_FPGA_FILE "FPG0005A.rbf" 71 #define UTILS_PTG_IO_AGENT_FPGA_GPIO (SOC_SAND_SET_FLD_IN_PLACE(0x0, 7, SOC_SAND_BIT(7))|SOC_SAND_SET_FLD_IN_PLACE(0x0, 6, SOC_SAND_BIT(6))|SOC_SAND_SET_FLD_IN_PLACE(0x0, 1, SOC_SAND_BIT(1))|SOC_SAND_SET_FLD_IN_PLACE(0x0, 0, SOC_SAND_BIT(0))) 72 /* } IO_AGENT_FPGA */ 73 74 /* DEVICE_FPGA { */ 75 #define UTILS_PTG_DEVICE_FPGA_FILE "FPG0006A.rbf" 76 #define UTILS_PTG_DEVICE_FPGA_GPIO (SOC_SAND_SET_FLD_IN_PLACE(0x0, 7, SOC_SAND_BIT(7))|SOC_SAND_SET_FLD_IN_PLACE(0x0, 6, SOC_SAND_BIT(6))|SOC_SAND_SET_FLD_IN_PLACE(0x1, 1, SOC_SAND_BIT(1))|SOC_SAND_SET_FLD_IN_PLACE(0x0, 0, SOC_SAND_BIT(0))) 77 /* } DEVICE_FPGA */ 78 79 /* } */ 80 81 /************* 82 * MACROS * 83 */ 84 /* { */ 85 86 /* } */ 87 88 /************* 89 * TYPE DEFS * 90 */ 91 /* { */ 92 typedef struct 93 { 94 uint8 address; 95 uint8 msb; 96 uint8 lsb; 97 }UTILS_PTG_FLD_ADDR; 98 99 /* } */ 100 101 /************* 102 * GLOBALS * 103 */ 104 /* { */ 105 106 /* } */ 107 108 /************* 109 * FUNCTIONS * 110 */ 111 /* { */ 112 113 void 114 utils_ptg_fpga_io_fld_set( 115 SOC_SAND_IN UTILS_PTG_FLD_ADDR *fld, 116 SOC_SAND_IN uint8 data 117 ); 118 119 uint8 120 utils_ptg_fpga_io_fld_get( 121 SOC_SAND_IN UTILS_PTG_FLD_ADDR *fld 122 ); 123 124 uint16 125 utils_ptg_mdio_get( 126 SOC_SAND_IN uint8 phy_ndx, 127 SOC_SAND_IN uint32 address 128 ); 129 130 void 131 utils_ptg_mdio_set( 132 SOC_SAND_IN uint8 phy_ndx, 133 SOC_SAND_IN uint32 address, 134 SOC_SAND_IN uint16 data 135 ); 136 137 uint8 138 utils_ptg_is_line_card_connected( 139 ); 140 141 uint8 142 utils_ptg_is_line_card_phy_connected( 143 ); 144 145 uint8 146 utils_ptg_is_line_card_ptg_connected( 147 ); 148 149 SOC_SAND_RET 150 utils_ptg_ptg_init( 151 SOC_SAND_IN uint8 start_server 152 ); 153 154 SOC_SAND_RET 155 utils_ptg_phy_init( 156 ); 157 158 SOC_SAND_RET 159 utils_ptg_init_host_board( 160 SOC_SAND_IN char board_version[B_HOST_MAX_DEFAULT_BOARD_VERSION_LEN] 161 ); 162 163 /* } */ 164 165 /* } __FAP21V_UTILS_LINE_PTG_INCLUDED__*/ 166 #endif