ref_sys.h (7417B)
1 2 /* 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 6 */ 7 #ifndef SOC_REF_SYS_INCLUDED 8 /* { */ 9 #define SOC_REF_SYS_INCLUDED 10 /* 11 * Set 'USE_DUNE_REFERENCE_PLATFORM' to a value of 'FALSE' to 12 * include definitions specific to packages (such as 13 * fe200_atm package) which are independent packages and are 14 * portable to other environments and operating systems. 15 * When defined to a non-zero value, it indicates that the package 16 * is being tested under Dune's reference system. 17 */ 18 #define USE_DUNE_REFERENCE_PLATFORM 1 19 #if USE_DUNE_REFERENCE_PLATFORM 20 /* { */ 21 /* 22 * Set 'SAND_LOW_LEVEL_SIMULATION' to a value of 'TRUE' to run the program 23 * under visual studio. Se to 'FALSE' on final version. 24 */ 25 /* } */ 26 #else 27 /* { */ 28 #include "fe200_atm_sys.h" 29 /* } */ 30 #endif 31 32 #if !DUNE_BCM 33 /* { */ 34 #define STATUS int 35 #define FALSE 0 36 #define TRUE 1 37 #if !defined(ERROR) 38 #define ERROR TRUE 39 #endif 40 41 #if !defined(OK) 42 #define OK 0 43 #endif 44 45 46 /* } */ 47 #endif 48 49 #if !DUNE_BCM 50 #else 51 #define CRATE_TEST_EVAL (0) /*Negev-Rev-A*/ 52 #define CRATE_32_PORT_40G_STANDALONE (1) /*Gobi: SOC_SAND_FAP20V*/ 53 #define CRATE_32_PORT_40G_IO (2) 54 #define CRATE_FABRIC_BOX (3) 55 #define CRATE_64_PORT_10G_STANDALONE (4) /*Gobi: SOC_SAND_FAP10M*/ 56 #define CRATE_32_PORT_10G_IO (5) 57 #define CRATE_NEGEV_REV_B (6) 58 #endif 59 60 /* 61 * Definitions related to debugging 62 * { 63 */ 64 /* 65 * Set true (non-zero) for demo (snake et al.) ONLY!!!. 66 * Set to zero in standard versions. 67 */ 68 #define CODE_FOR_DEMO_ONLY 1 69 /* 70 * Set true (non-zero) for debug stage ONLY!!!. Produces debug code additions. 71 */ 72 #define DEBUG_AID 1 73 /* 74 * Set true (non-zero) for debug stage ONLY!!!. 75 * Produces debug code additions for 'ui memory' module. 76 */ 77 /* 78 * Set true (non-zero) for debug stage ONLY!!!. 79 * This will define PCI interrupt to be an interrupt which 80 * may be controlled (i.e. injected) by SW (for debug purposes) 81 */ 82 /* 83 * Set true (non-zero) for debug stage ONLY!!!. 84 * Produces debug code and simulation related to DUNE chip set module. 85 * There are 2 simultors :SIMULATE_DUNE_CHIP and SIMULATE_CHIP_SIM/ 86 * SIMULATE_CHIP_SIM -- related to ChipSim lib. 87 */ 88 #define SIMULATE_DUNE_CHIP 0 89 #define SIMULATE_CHIP_SIM 0 90 #if SIMULATE_CHIP_SIM 91 /* { */ 92 /* 93 * Flag: SIMULATE FEs at initialization. 94 */ 95 /* 96 * Flag: SIMULATE FAPs at initialization. 97 */ 98 /* } */ 99 #endif 100 #if (SIMULATE_CHIP_SIM) & (SIMULATE_DUNE_CHIP) 101 #error "Only one is allowed active (SIMULATE_CHIP_SIM) & (SIMULATE_DUNE_CHIP)" 102 #endif 103 104 /* 105 * } 106 */ 107 /* 108 * Object: Buff_mem 109 * This object enables the user to store 'mem read' results 110 * in local memory to later be retriebed. This feature enables 111 * faster working with an external script agent (like proComm). 112 * Storage is always in units of char (one byte). 113 * { 114 */ 115 /* 116 * Size of local storage of results. 117 */ 118 #define SIZEOF_BUFF_MEM 4000 119 /* 120 * } 121 */ 122 /* 123 * Base memory address and size of SDRAM. 124 * Update with final address when final board is 125 * ready. 126 */ 127 #define SDRAM_BASE_ADDR 0x00000000 128 #define SDRAM_SIZE 0x08000000 /*Udic*/ 129 /* 130 * Base memory address and size of E2PROM. 131 * Update with final address when final board is 132 * ready. 133 */ 134 #define E2PROM_BASE_ADDR 0x20000000 135 #define E2PROM_SIZE 0x2000 136 /* 137 * Base memory address and size of EPLD. 138 * Also very basic definitions related to version and 139 * board identity (to be used at early boot stages). 140 * Update with final address when final board is 141 * ready. 142 */ 143 #define EPLD_BASE_ADDR 0x30000000 144 #define EPLD_SIZE 0x10 145 #define NEW_MEZZANINE_WITH_PCI 0x00000020 146 /* 147 * Base memory address and size of GP1. 148 * Update with final address when final board is 149 * ready. 150 */ 151 #define GP1_BASE_ADDR 0x40000000 152 /* 153 * Base memory address of FE. 154 * Update with final address when final board is 155 * ready. 156 */ 157 #if (SIMULATE_DUNE_CHIP || SIMULATE_CHIP_SIM) 158 /* { */ 159 #define FE_1_BASE_ADDR (&Fe_regs[0]) 160 #define FE_2_BASE_ADDR (&Fe_regs[1]) 161 162 #define FAP10M_1_BASE_ADDR (&Fap10m_regs[0]) 163 #define FAP10M_2_BASE_ADDR (&Fap10m_regs[1]) 164 /* } */ 165 #else 166 /* { */ 167 #define FE_1_BASE_ADDR (GP1_BASE_ADDR) 168 #define FE_2_BASE_ADDR (GP1_BASE_ADDR | 0x100000) 169 170 #define FAP10M_1_BASE_ADDR (GP1_BASE_ADDR) 171 #define FAP10M_2_BASE_ADDR (GP1_BASE_ADDR | 0x00100000) 172 173 /* } */ 174 #endif 175 176 /* 177 * Number of FE chips on this board. 178 */ 179 #define NUM_FE_ON_BOARD 2 180 /* 181 * Number of FE chips on this board. 182 */ 183 /* 184 * Base memory address and size of GP2. 185 * Update with final address when final board is 186 * ready. 187 */ 188 #define GP2_BASE_ADDR 0x50000000 189 #define GP2_SIZE 0x800000 190 /* 191 * Base memory address and size of GP3. 192 * Update with final address when final board is 193 * ready. 194 */ 195 #define GP3_BASE_ADDR 0x70000000 196 #define GP3_SIZE 0x400000 197 /* 198 * Definitions added for new mezzanine card 199 * { 200 */ 201 /* 202 * Base memory address and size of SDRAM handled by GT64131. 203 */ 204 #define GT64131_SDRAM_BASE_ADDR 0x10000000 205 #define GT64131_SDRAM_SIZE 0x02000000 206 /* 207 * Base memory address and size of registers of GT64131. 208 */ 209 #define GT64131_REGS_BASE_ADDR 0x14000000 210 #define GT64131_REGS_SIZE 0x00001000 211 /* 212 * Base memory address and size of PCI I/O. 213 */ 214 #define PCI_IO_BASE_ADDR 0x18000000 215 #define PCI_IO_REGS_SIZE 0x08000000 216 /* 217 * Base memory address and size of PCI memory. Bank #1 218 * Prepare place of 8K bytes. Avoid exaggeration 219 * here since this increases initialization time 220 * at startup (vmGlobalMapInit() in usrMmuInit()) 221 */ 222 #define PCI_MEM1_BASE_ADDR 0x70000000 223 #define PCI_MEM1_REGS_SIZE 0x00002000 224 /* 225 * Base memory address and size of PCI memory. Bank #2 226 * Prepare place of 128M bytes. Avoid exaggeration 227 * here since this increases initialization time 228 * at startup (vmGlobalMapInit() in usrMmuInit()) 229 */ 230 #define PCI_MEM2_BASE_ADDR 0x80000000 231 #define PCI_MEM2_REGS_SIZE 0x08000000 232 /* 233 * } 234 */ 235 236 237 /* 238 * Set true for debug stage. Produces debug printing. 239 */ 240 #define DEBUG_PRINT TRUE 241 /* 242 * Set true for telnet debug stage. Produces debug printing. 243 */ 244 #define TELNET_DEBUG_PRINT FALSE 245 /* 246 * Set true to display current line again after error during line mode. 247 */ 248 #define SHOW_PROMPT_LINE_AFTER_ERROR_DURING_LINE_MODE FALSE 249 250 #ifndef _ASMLANGUAGE 251 /* { */ 252 /* 253 * Pointer to a procedure that returns int 254 */ 255 typedef int (*PROC_PTR)(void) ; 256 /* 257 * Pointer to a procedure that returns int and gets unsigned long 258 */ 259 typedef int (*PROC_PTR_LONG)(unsigned long) ; 260 /* } */ 261 #endif 262 /* 263 * Definitions which are specific for reference system. 264 * { 265 */ 266 267 /* 268 * Software signals. 269 * The FEC driver uses one signal 270 * The FAP10 driver uses one signal 271 */ 272 273 /* 274 * Number of sectors, starting from '0', assigned to 275 * downloading of user program. 276 */ 277 /* 278 * If include_enhanced_cli is defined then extra features, such as 279 * 'parameter string with default does not require a value' are added. 280 */ 281 #define INCLUDE_ENHANCED_CLI FALSE 282 #ifndef _ASMLANGUAGE 283 /* { */ 284 /* 285 * prototypes 286 */ 287 /* 288 * { 289 */ 290 void 291 progStop( 292 void 293 ) ; 294 /* 295 * } 296 */ 297 298 /* 299 * 0 -- No calls to SOC_SAND_FAP20V driver 300 * So it shell not be included in the linking. 301 * 1 -- Call to SOC_SAND_FAP20V driver 302 * { 303 */ 304 305 #ifndef FAP20M_STANDALONE_PACKAGE 306 /*#define LINK_FAP20V_LIBRARIES 1*/ 307 #endif 308 /* 309 * } 310 */ 311 312 /* } */ 313 #endif 314 /* 315 * } 316 */ 317 /* } */ 318 #endif 319 320