dune_chips.h (21326B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 5 */ 6 #ifndef DUNE_CHIPS_INCLUDED 7 /* { */ 8 #define DUNE_CHIPS_INCLUDED 9 10 #define __ATTRIBUTE_PACKED__ __attribute__ ((packed)) 11 12 #include "bits_bytes_macros.h" 13 /* 14 * Definitions related to 'version' register. 15 * This register is mutual to all Dune's devices. 16 */ 17 18 #define DUNE_VERSION_REGISTERS_ADDRESS 0x0 19 20 #define CHIP_TYPE_MS_BIT 23 21 #define CHIP_TYPE_NUM_BITS 20 22 #define CHIP_TYPE_LS_BIT (CHIP_TYPE_MS_BIT + 1 - CHIP_TYPE_NUM_BITS) 23 #define CHIP_TYPE_MASK \ 24 (((unsigned long)SOC_SAND_BIT(CHIP_TYPE_MS_BIT) - SOC_SAND_BIT(CHIP_TYPE_LS_BIT)) + SOC_SAND_BIT(CHIP_TYPE_MS_BIT)) 25 #define CHIP_TYPE_SHIFT CHIP_TYPE_LS_BIT 26 27 #define DBG_VER_MS_BIT 27 28 #define DBG_VER_NUM_BITS 4 29 #define DBG_VER_LS_BIT (DBG_VER_MS_BIT + 1 - DBG_VER_NUM_BITS) 30 #define DBG_VER_MASK \ 31 (((unsigned long)SOC_SAND_BIT(DBG_VER_MS_BIT) - SOC_SAND_BIT(DBG_VER_LS_BIT)) + SOC_SAND_BIT(DBG_VER_MS_BIT)) 32 #define DBG_VER_SHIFT DBG_VER_LS_BIT 33 34 #define CHIP_VER_MS_BIT 31 35 #define CHIP_VER_NUM_BITS 4 36 #define CHIP_VER_LS_BIT (CHIP_VER_MS_BIT + 1 - CHIP_VER_NUM_BITS) 37 #define CHIP_VER_MASK \ 38 (((unsigned long)SOC_SAND_BIT(CHIP_VER_MS_BIT) - SOC_SAND_BIT(CHIP_VER_LS_BIT)) + SOC_SAND_BIT(CHIP_VER_MS_BIT)) 39 #define CHIP_VER_SHIFT CHIP_VER_LS_BIT 40 41 42 /* 43 * Memory structures describing FE registers in a way that 44 * enables the cpu to both display and change it. 45 * { 46 */ 47 /* 48 * Structure to use to interpret a value of a field to 49 * human readable text. 50 */ 51 typedef struct 52 { 53 /* 54 * Value of field. 55 */ 56 unsigned long value ; 57 /* 58 * Human readable text description of this value for this field. 59 */ 60 const char *value_text_description ; 61 } VAL_TO_TEXT ; 62 /* 63 * Maximal number of of 'VAL_TO_TEXT' items per field. 64 */ 65 /* 66 * Structure to use to describe the structure of a group: 67 * A group is assumed to be represented by a set of 32-bits 68 * registers. Each register is located at a specified offset 69 * from the beginning of the group (at long word intervals) 70 * and may be repeated a specific number of times. 71 */ 72 typedef struct 73 { 74 /* 75 * Number of repetitions of 32-bits register. 76 * Must be '1' or more. 77 */ 78 unsigned short num_repetitions ; 79 /* 80 * Identifier of representative 32-bits register. 81 * This ID must be one of those specified 82 * in 'Register identifiers' below. 83 */ 84 unsigned short register_id ; 85 /* 86 * Byte offset, from the beginning of memory block, 87 * assigned to FE, of first 32-bits register. 88 * The LS two bits are supposed to be '0' and 89 * are ignored, anyway. 90 */ 91 unsigned long byte_offset ; 92 } ELEMENT_OF_GROUP ; 93 /* 94 * Maximal number of of 'ELEMENT_OF_GROUP' items per group. 95 */ 96 #define MAX_ELEMENT_OF_GROUP_ITEMS 10 97 /* 98 * Maximal number of of 32-bits regsiters per group. 99 */ 100 #define MAX_REGS_IN_ONE_GROUP 256 101 /* 102 * Field identifiers 103 */ 104 #define FE_NO_FIELD 1 105 #define FE_LAST_FIELD 65535 106 #define FE_CHIP_TYPE_FIELD 2 107 #define FE_DBG_VER_FIELD 3 108 #define FE_CHIP_VER_FIELD 4 109 #define FE_CHIP_ID_FIELD 5 110 #define FE_MODE_FE2_FIELD 6 111 #define FE_REPEATER_FIELD 7 112 #define FE_PLANES_FIELD 8 113 #define FE_MULTISTAGE_FIELD 9 114 #define FE_TX_DATA_CELL_TRIGGER_FIELD 10 115 #define FE_CSRFO_1_FIELD 11 116 #define FE_SRFNE_1_FIELD 12 117 #define FE_CSRFO_2_FIELD 13 118 #define FE_SRFNE_2_FIELD 14 119 #define FE_PEC_1_FIELD 15 120 #define FE_PECO_1_FIELD 16 121 #define FE_PEC_2_FIELD 17 122 #define FE_PECO_2_FIELD 18 123 #define FE_RCI_P_TRH_FIELD 19 124 #define FE_GCI_P_TRH_1_FIELD 20 125 #define FE_GCI_P_TRH_2_FIELD 21 126 #define FE_GCI_P_TRH_3_FIELD 22 127 #define FE_CTR_CELL_CNT_1_FIELD 23 128 #define FE_CTR_CELL_CNT_O_1_FIELD 24 129 #define FE_CTR_CELL_CNT_2_FIELD 25 130 #define FE_CTR_CELL_CNT_O_2_FIELD 26 131 #define FE_SRC_D_ID_N_1_FIELD 27 132 #define FE_SRC_D_LVL_N_1_FIELD 28 133 #define FE_SRC_D_LN_N_N_1_FIELD 29 134 #define FE_SRC_D_ID_N_2_FIELD 30 135 #define FE_SRC_D_LVL_N_2_FIELD 31 136 #define FE_SRC_D_LN_N_N_2_FIELD 32 137 #define FE_FEL_N_00_CHANGED_FIELD 33 138 #define FE_FEL_N_32_CHANGED_FIELD 34 139 #define FE_SRC_MUL_FIELD 35 140 #define FE_RM_DID_OR_FIELD 36 141 #define FE_FE_23_DUP_ID_FIELD 37 142 #define FE_FE_23_DDEST1_FIELD 38 143 #define FE_FE_23_DDEST2_FIELD 39 144 #define FE_FE_23_DEST_ID_FIELD 40 145 #define FE_OR_DEST_ID_FIELD 41 146 #define FE_OR_INPUT_LN_FIELD 42 147 #define FE_RMAC_CRC_D_FIELD 43 148 #define FE_TX_CDC_FIELD 44 149 #define FE_RX_CDC_FIELD 45 150 #define FE_RX_GC_CNT_N_1_FIELD 46 151 #define FE_RX_GC_CNT_N_2_FIELD 47 152 #define FE_RX_GC_CNT_N_3_FIELD 48 153 #define FE_RX_GC_CNT_N_4_FIELD 49 154 #define FE_RX_CRC_ERR_N_1_FIELD 50 155 #define FE_RX_CRC_ERR_N_2_FIELD 51 156 #define FE_RX_CRC_ERR_N_3_FIELD 52 157 #define FE_RX_CRC_ERR_N_4_FIELD 53 158 #define FE_RX_MA_ERR_N_1_FIELD 54 159 #define FE_RX_MA_ERR_N_2_FIELD 55 160 #define FE_RX_MA_ERR_N_3_FIELD 56 161 #define FE_RX_MA_ERR_N_4_FIELD 57 162 #define FE_RX_CODEG_ERR_N_1_FIELD 58 163 #define FE_RX_CODEG_ERR_N_2_FIELD 59 164 #define FE_RX_CODEG_ERR_N_3_FIELD 60 165 #define FE_RX_CODEG_ERR_N_4_FIELD 61 166 #define FE_TX_CNT_N_1_FIELD 62 167 #define FE_TX_CNT_N_2_FIELD 63 168 #define FE_TX_CNT_N_3_FIELD 64 169 #define FE_TX_CNT_N_4_FIELD 65 170 #define FE_PRBS_1_GENO_FIELD 66 171 #define FE_PRBS_1_CKO_FIELD 67 172 #define FE_PRBS_2_GENO_FIELD 68 173 #define FE_PRBS_2_CKO_FIELD 69 174 #define FE_PRBS_3_GENO_FIELD 70 175 #define FE_PRBS_3_CKO_FIELD 71 176 #define FE_PRBS_4_GENO_FIELD 72 177 #define FE_PRBS_4_CKO_FIELD 73 178 #define FE_PRBS_1_GENL_FIELD 74 179 #define FE_PRBS_1_CKL_FIELD 75 180 #define FE_PRBS_2_GENL_FIELD 76 181 #define FE_PRBS_2_CKL_FIELD 77 182 #define FE_PRBS_3_GENL_FIELD 78 183 #define FE_PRBS_3_CKL_FIELD 79 184 #define FE_PRBS_4_GENL_FIELD 80 185 #define FE_PRBS_4_CKL_FIELD 81 186 #define FE_BER_CNT_1_FIELD 82 187 #define FE_BER_VALID_1_FIELD 83 188 #define FE_BER_CNT_2_FIELD 84 189 #define FE_BER_VALID_2_FIELD 85 190 #define FE_BER_CNT_3_FIELD 86 191 #define FE_BER_VALID_3_FIELD 87 192 #define FE_BER_CNT_4_FIELD 88 193 #define FE_BER_VALID_4_FIELD 89 194 #define FE_PD_TBG_FIELD 90 195 #define FE_PD_FCT_FIELD 91 196 #define FE_AMP_FIELD 92 197 #define FE_PEN_FIELD 93 198 #define FE_MEN_FIELD 94 199 #define FE_VCMS_FIELD 95 200 #define FE_LAST_TX_FIELD 96 201 #define FE_PAYLOAD_TX_FIELD 97 202 #define FE_FIRST_BYTE_TX_FIELD 98 203 #define FE_FE3_SW_FIELD 99 204 #define FE_FE2_SW_FIELD 100 205 #define FE_DEST_LVL_TX_FIELD 101 206 #define FE_SRC_LVL_TX_FIELD 102 207 #define FE_SRC_ID_TX_FIELD 103 208 #define FE_COLN_FIELD 104 209 #define FE_LAST_RX_FIELD 105 210 #define FE_PAYLOAD_RX_FIELD 106 211 #define FE_FIRST_BYTE_RX_FIELD 107 212 #define FE_SRC_LVL_RX_FIELD 108 213 #define FE_SRC_ID_RX_FIELD 109 214 #define FE_PURE_IND_ADDR_FIELD 110 215 #define FE_MODULE_FIELD 111 216 #define FE_RD_NOT_WR_FIELD 112 217 #define FE_IND_TRIGGER_FIELD 113 218 #define FE_WRITE_BUFF_ANY_FIELD 114 219 #define FE_WRITE_BUFF_LAST_FIELD 115 220 #define FE_RTP_RR_FIELD 116 221 #define FE_DCHA_RR_ANY_FIELD 117 222 #define FE_DCHA_RR_LAST_FIELD 118 223 #define FE_DCHB_RR_ANY_FIELD 119 224 #define FE_DCHB_RR_LAST_FIELD 120 225 #define FE_DCLA_RR_ANY_FIELD 121 226 #define FE_DCLA_RR_LAST_FIELD 122 227 #define FE_DCLB_RR_ANY_FIELD 123 228 #define FE_DCLB_RR_LAST_FIELD 124 229 #define FE_CCSA_RR_ANY_FIELD 125 230 #define FE_CCSA_RR_LAST_FIELD 126 231 #define FE_CCSB_RR_ANY_FIELD 127 232 #define FE_CCSB_RR_LAST_FIELD 128 233 #define FE1_MULTICAST_DISTRIBUTION_FIELD 129 234 #define FE2_MULTICAST_REPLICATION_L_FIELD 130 235 #define FE2_MULTICAST_REPLICATION_H_FIELD 131 236 #define FE3_MULTICAST_REPLICATION_FIELD 132 237 #define FE1_UNICAST_DISTRIBUTION_FIELD 133 238 #define FE2_UNICAST_ROUTING_FIELD 134 239 #define FE3_UNICAST_ROUTING_FIELD 135 240 /* 241 * Interrupt Fields 242 */ 243 #define FE_FECINT_FIELD 500 244 #define FE_FECINT_MASK_FIELD 600 245 /* 246 * Register identifiers 247 */ 248 #define FE_VERSION_REG 2 249 #define FE_CONFIGURATION_REG 3 250 #define FE_TX_DATA_CELL_TRIGGER_REG 4 251 #define FE_SR_DATA_CELL_FIFO_IND_1_REG 5 252 #define FE_SR_DATA_CELL_FIFO_IND_2_REG 6 253 #define FE_PKT_DATA_CELL_COUNTER_1_REG 7 254 #define FE_PKT_DATA_CELL_COUNTER_2_REG 8 255 #define FE_RCI_N_CGI_THRESHOLDS_REG 9 256 #define FE_CONTROL_CELLS_CNTR_1_REG 10 257 #define FE_CONTROL_CELLS_CNTR_2_REG 11 258 #define FE_CONNECTIVITY_1_REG 12 259 #define FE_CONNECTIVITY_2_REG 13 260 #define FE_CONNECTIVITY_MAP_CHANGE_1_REG 14 261 #define FE_CONNECTIVITY_MAP_CHANGE_2_REG 15 262 #define FE_ROUTING_PROC_ENABLES_REG 16 263 #define FE_REACH_FAULT_IND_REG 17 264 #define FE_REACH_DUP_DEST_REG 18 265 #define FE_REACH_DEST_OR_REG 19 266 #define FE_MAC_ENABLERS_REG 20 267 #define FE_MAC_RX_CNTRS_1_REG 21 268 #define FE_MAC_RX_CNTRS_2_REG 22 269 #define FE_MAC_RX_CNTRS_3_REG 23 270 #define FE_MAC_RX_CNTRS_4_REG 24 271 #define FE_MAC_TX_CNTRS_1_REG 25 272 #define FE_MAC_TX_CNTRS_2_REG 26 273 #define FE_MAC_TX_CNTRS_3_REG 27 274 #define FE_MAC_TX_CNTRS_4_REG 28 275 #define FE_PRBS_ENABLERS_REG 29 276 #define FE_PRBS_LINK_NUMS_REG 30 277 #define FE_MAC_BER_CNTRS_1_REG 31 278 #define FE_MAC_BER_CNTRS_2_REG 32 279 #define FE_MAC_BER_CNTRS_3_REG 33 280 #define FE_MAC_BER_CNTRS_4_REG 34 281 #define FE_SERDES_FRST_REG 35 282 #define FE_SERDES_REST_REG 36 283 #define FE_LAST_TX_REG 37 284 #define FE_BODY_TX_REG 38 285 #define FE_SWITCHES_TX_REG 39 286 #define FE_PATHS_TX_REG 40 287 #define FE_LAST_RX_REG 41 288 #define FE_BODY_RX_REG 42 289 #define FE_SWITCHES_RX_REG 43 290 #define FE_PATHS_RX_REG 44 291 #define FE_ACCESS_ADDR_REG 45 292 #define FE_IND_TRIGGER_REG 46 293 #define FE_WRITE_BUFF_ANY_REG 47 294 #define FE_WRITE_BUFF_LAST_REG 48 295 #define FE_RTP_RR_REG 49 296 #define FE_DCHA_RR_ANY_REG 50 297 #define FE_DCHA_RR_LAST_REG 51 298 #define FE_DCHB_RR_ANY_REG 52 299 #define FE_DCHB_RR_LAST_REG 53 300 #define FE_DCLA_RR_ANY_REG 54 301 #define FE_DCLA_RR_LAST_REG 55 302 #define FE_DCLB_RR_ANY_REG 56 303 #define FE_DCLB_RR_LAST_REG 57 304 #define FE_CCSA_RR_ANY_REG 58 305 #define FE_CCSA_RR_LAST_REG 59 306 #define FE_CCSB_RR_ANY_REG 60 307 #define FE_CCSB_RR_LAST_REG 61 308 #define FE1_MULTICAST_DISTRIBUTION_REG 62 309 #define FE2_MULTICAST_REPLICATION_L_REG 63 310 #define FE2_MULTICAST_REPLICATION_H_REG 64 311 #define FE3_MULTICAST_REPLICATION_REG 65 312 #define FE1_UNICAST_DISTRIBUTION_REG 66 313 #define FE2_UNICAST_ROUTING_REG 67 314 #define FE3_UNICAST_ROUTING_REG 68 315 /* 316 * Main interrupt register 317 */ 318 #define FE_INT_MODULE_SRC_REG 100 319 #define FE_INT_MODULE_SRC_MASK_REG 101 320 #define FE_CCS_OVERFLOW_REG 102 321 /* 322 * Group identifiers 323 */ 324 #define FE_NO_GROUP 1 325 #define FE_TX_SR_DATA_CELL_GROUP 2 326 #define FE_CONNECT_MAP_GROUP 3 327 #define FE_MAC_RX_CNTRS_GROUP 4 328 #define FE_MAC_TX_CNTRS_GROUP 5 329 #define FE_MAC_BER_CNTRS_GROUP 6 330 #define FE_SERDES_ENABLERS_GROUP 7 331 #define FE_RX_SR_DATA_CELL_GROUP 8 332 #define FE_IND_WRITE_BUFF_GROUP 9 333 #define FE_DCHA_RR_GROUP 10 334 #define FE_DCHB_RR_GROUP 11 335 #define FE_DCLA_RR_GROUP 12 336 #define FE_DCLB_RR_GROUP 13 337 #define FE_CCSA_RR_GROUP 14 338 #define FE_CCSB_RR_GROUP 15 339 #define FE1_MULTICAST_DISTRIBUTION_GROUP 16 340 #define FE2_MULTICAST_REPLICATION_L_GROUP 17 341 #define FE2_MULTICAST_REPLICATION_H_GROUP 18 342 #define FE3_MULTICAST_REPLICATION_GROUP 19 343 #define FE1_UNICAST_DISTRIBUTION_GROUP 20 344 #define FE2_UNICAST_ROUTING_GROUP 21 345 #define FE3_UNICAST_ROUTING_GROUP 22 346 347 /* 348 * Block identifiers 349 */ 350 /* 351 * 0X0000 - 0x00FF 352 */ 353 #define FE_GEN_REGS_BLOCK 2 354 /* 355 * 0x0100 - 0x01FF 356 */ 357 #define FE_DCS_DCHA_BLOCK 3 358 /* 359 * 0x0200 - 0x02FF 360 */ 361 #define FE_DCS_DCLA_BLOCK 4 362 /* 363 * 0x0300 - 0x03FF 364 */ 365 #define FE_DCS_DCHB_BLOCK 5 366 /* 367 * 0x0400 - 0x04FF 368 */ 369 #define FE_DCS_DCLB_BLOCK 6 370 /* 371 * 0x0500 - 0x054F 372 */ 373 #define FE_DCS_ECI_BLOCK 7 374 /* 375 * 0x0550 - 0x05FF 376 */ 377 /* 378 * 0x0600 - 0x06FF 379 */ 380 #define FE_CCSA_CCS_BLOCK 9 381 /* 382 * 0x0700 - 0x07FF 383 */ 384 #define FE_CCSB_CCS_BLOCK 10 385 /* 386 * 0x0800 - 0x08FF 387 */ 388 #define FE_RTP_ECI_BLOCK 11 389 /* 390 * 0x0900 - 0x09FF 391 */ 392 #define FE_RTP_RTP_BLOCK 12 393 /* 394 * 0x0A00 - 0x0AF0 395 */ 396 #define FE_MAC_ECI_BLOCK 13 397 /* 398 * 0x0AF0 - 0x0AFF 399 */ 400 /* 401 * 0x0B00 - 0x0DFF 402 */ 403 #define FE_MAC_MAC_BLOCK 15 404 /* 405 * 0x0E00 - 0x0EFF 406 */ 407 /* 408 * 0x0F00 - 0x0FFF 409 */ 410 #define FE_SERDES_ECI_1_BLOCK 17 411 /* 412 * 0x30002000 - 0x3000381F 413 */ 414 #define FE_INDIRECT_BLOCK 18 415 416 /* 417 * Values for 'display_mode' element 418 */ 419 #define DISPLAY_HEX SOC_SAND_BIT(0) 420 #define DISPLAY_UNSIGNED_INT SOC_SAND_BIT(1) 421 #define DISPLAY_BINARY SOC_SAND_BIT(2) 422 /* 423 * Values for 'access_type' field 424 */ 425 #define ACCESS_READ SOC_SAND_BIT(0) 426 #define ACCESS_WRITE SOC_SAND_BIT(1) 427 #define ACCESS_CLEAR SOC_SAND_BIT(2) 428 #define ACCESS_INDIRECT SOC_SAND_BIT(3) 429 typedef struct 430 { 431 /* 432 * Identifier of field. For example 'FE_CHIP_TYPE_FIELD'. 433 */ 434 unsigned short field_id ; 435 /* 436 * Identifier of register. For example 'FE_CONGIGURATION_REG'. 437 */ 438 unsigned short reg_id ; 439 /* 440 * Identifier of block to which this register belongs. 441 * For example 'FE_DCHA_DCS_BLOCK'. 442 */ 443 unsigned short reg_block_id ; 444 /* 445 * Identifier of group of registers (long variables) 446 * to which this register belongs. 447 * Usually, registers do not belong to any group. 448 * For example 'FE_TX_SR_DATA_CELL_GROUP'. 449 */ 450 unsigned short reg_group_id ; 451 /* 452 * Byte offset (from the beginning of memory area 453 * assigned to FE) of long variable to which this 454 * register belongs. 455 * This offset must be long aligned (must have its 456 * two LS bits set to zero) and, in any case, those 457 * bits are ignored. 458 * Memory area assigned to FE is assumed to be long-aligned. 459 */ 460 unsigned long reg_base_offset ; 461 /* 462 * Mask of the bits which make this field within the 463 * long variable register to which this field belongs. 464 */ 465 unsigned long field_mask ; 466 /* 467 * Shift that should be applied to field in order 468 * to set it so that its LS bit is also the LS bit 469 * of containing long variable register. 470 */ 471 unsigned long field_shift ; 472 /* 473 * Human readable identifier of field. 474 * For example "FE_CHIP_TYPE_FIELD". 475 */ 476 char *field_name ; 477 /* 478 * Human readable text description of field. 479 */ 480 char *field_text_description ; 481 /* 482 * Human readable identifier of register. 483 * For example "FE_CONGIGURATION_REG". 484 */ 485 char *reg_name ; 486 /* 487 * Human readable text description of register. 488 */ 489 char *reg_text_description ; 490 /* 491 * Human readable identifier of group of registers 492 * (long variables) to which this register belongs. 493 * For example "FE_TX_SR_DATA_CELL_GROUP". 494 */ 495 char *reg_group_name ; 496 /* 497 * Human readable text description of group of 498 * registers (long variables) to which this register 499 * belongs. 500 */ 501 char *reg_group_text_description ; 502 /* 503 * Human readable identifier of block to which this 504 * register belongs. 505 * For example "FE_DCHA_DCS_BLOCK". 506 */ 507 char *reg_block_name ; 508 /* 509 * Human readable text description of block to 510 * which this register belongs. 511 */ 512 char *reg_block_text_description ; 513 /* 514 * Required display mode for this field 515 * DISPLAY_HEX 516 * DISPLAY_UNSIGNED_INT 517 * DISPLAY_BINARY 518 */ 519 unsigned char display_mode ; 520 /* 521 * Access type allowed for this field 522 * ACCESS_READ 523 * ACCESS_WRITE 524 * ACCESS_CLEAR 525 */ 526 unsigned char access_type ; 527 VAL_TO_TEXT *val_to_text ; 528 /* 529 * This element is only relevant for entries which 530 * are, essentially, descriptors of groups. 531 */ 532 ELEMENT_OF_GROUP *element_of_group ; 533 /* 534 * Attribute bits and fields. Same as in VAL_NUM_DESCRIPTOR. 535 * an be : 536 * HAS_NO_MIN_VALUE, HAS_MIN_VALUE, 537 * HAS_NO_MAX_VALUE, HAS_MAX_VALUE 538 * This parameter is only relevant for registers which 539 * are writable. 540 */ 541 unsigned long val_numeric_attributes ; 542 /* 543 * Maximal allowed value. Same as in VAL_NUM_DESCRIPTOR. 544 * This parameter is only relevant for registers which 545 * are writable. 546 */ 547 long val_max ; 548 /* 549 * Minimal allowed value. Same as in VAL_NUM_DESCRIPTOR. 550 * This parameter is only relevant for registers which 551 * are writable. 552 */ 553 long val_min ; 554 } DESC_FE_REG ; 555 /* 556 * } 557 */ 558 /* 559 * EPLD registers 560 * { 561 */ 562 typedef struct 563 { 564 unsigned char version ; /* offset: 0x00 */ 565 unsigned char test_register ; /* offset: 0x01 */ 566 unsigned char wait_state_3_0 ; /* offset: 0x02 */ 567 unsigned char wait_state_7_4 ; /* offset: 0x03 */ 568 unsigned char wait_state_11_8 ; /* offset: 0x04 */ 569 unsigned char wait_state_15_12 ; /* offset: 0x05 */ 570 unsigned char leds_control ; /* offset: 0x06 */ 571 unsigned char slot_id ; /* offset: 0x07 */ 572 unsigned char reset_control ; /* offset: 0x08 */ 573 unsigned char watchdog ; /* offset: 0x09 */ 574 unsigned char gp_bus_data ; /* offset: 0x0A */ 575 unsigned char gp_io_conf ; /* offset: 0x0B */ 576 unsigned char nvram_erase_control ; /* offset: 0x0C */ 577 unsigned char interrupt_cause ; /* offset: 0x0D */ 578 unsigned char interrupt_mask ; /* offset: 0x0E */ 579 } __ATTRIBUTE_PACKED__ EPLD_REGS ; 580 /* 581 * Mask of meaningful bits on slot id register. 582 */ 583 /* 584 * Maximal slot_id for line card. 585 * Line cards have slot_id from 1 to MAX_SLOT_ID_LINE_CARD 586 */ 587 #define MAX_SLOT_ID_LINE_CARD 16 588 /* 589 * Maximal slot_id for fabric card. 590 * Fabric cards have slot_id from (MAX_SLOT_ID_LINE_CARD+1) 591 * to MAX_SLOT_ID_LINE_CARD 592 */ 593 #define MAX_SLOT_ID_FABRIC_CARD 24 594 /* 595 * Mask of crate ID bits on internal register C of MPC860. 596 */ 597 /* 598 * Shift of crate ID bits (from bit 0) on internal register C of MPC860. 599 */ 600 /* 601 * Mask of crate TYPE bits on internal register C of MPC860. 602 */ 603 /* 604 * Shift of crate TYPE bits (from bit 0) on internal register C of MPC860. 605 */ 606 /* 607 * The various types of crates: 608 */ 609 #define CRATE_TEST_EVAL (0) /*Negev-Rev-A*/ 610 #define CRATE_32_PORT_40G_STANDALONE (1) /*Gobi: SOC_SAND_FAP20V*/ 611 #define CRATE_32_PORT_40G_IO (2) 612 #define CRATE_FABRIC_BOX (3) 613 #define CRATE_64_PORT_10G_STANDALONE (4) /*Gobi: SOC_SAND_FAP10M*/ 614 #define CRATE_32_PORT_10G_IO (5) 615 #define CRATE_NEGEV_REV_B (6) 616 617 /* 618 * Bit in 'watchdog' which, when zeroed, enables INTERNAL watchdog 619 * and, when set, disables it. 620 */ 621 /* 622 * Bits containing INTERNAL watchdog timer. Every unit is 623 * 100 ms. 624 */ 625 #define INTERNAL_WATCHDOG_MASK 0x1F 626 /* 627 * Bit in 'watchdog' which, when set, causes only IRQ0 on 628 * watchdog expiry but NO reset. 629 */ 630 /* 631 * Bit in 'watchdog' which, when zeroed, enables external watchdog 632 * and, when set, disables it. 633 */ 634 /* 635 * Units of internal watchdog timer, in ms. 636 */ 637 /* 638 * Inrerrupt cause register: This register contains bit map 639 * of interrupts from underlying board. There are 640 * currently five sources defined. Names below relate to 641 * DB-MX620-10GS with PCI (but the same entries may get other 642 * names for other boards). 643 */ 644 /* 645 * Inrerrupt mask register: Same bit map as Inrerrupt cause register 646 */ 647 /* 648 * } 649 */ 650 651 /* } */ 652 #endif