diag.h (14032B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 7 * 8 * File: diag.h 9 * Purpose: Device diagnostics commands. 10 */ 11 12 13 #ifndef _DIAG_H_INCLUDED_ 14 #define _DIAG_H_INCLUDED_ 15 16 #include <soc/chip.h> 17 #include <appl/diag/diag.h> 18 19 #if (!defined(BCM_DNX_SUPPORT) && !defined(BCM_DNXF_SUPPORT)) 20 #include <soc/dpp/TMC/tmc_api_diagnostics.h> 21 #endif 22 23 /* 24 *DNX Diag pack infrastructure 25 */ 26 #define DNX_DIAG_ID_UNAVAIL (-1) 27 28 typedef cmd_result_t (*diag_dnx_action_func_ptr_t)(int unit, args_t* a); 29 typedef void (*diag_dnx_usage_func_ptr_t)(int unit); 30 typedef int (*diag_dnx_diag_id_supported_func_ptr_t)(int unit, int diag_id); 31 32 typedef struct diag_dnx_table_s { 33 char* module_char; /*Command name*/ 34 diag_dnx_action_func_ptr_t action_func; /*Callback to command fuction*/ 35 diag_dnx_usage_func_ptr_t usage_func; /*Callback to command usage function*/ 36 int diag_id; /*diag id - used in order to make sure this command is supported by the device*/ 37 } diag_dnx_table_t; 38 39 /* 40 * Function: 41 * diag_dnx_usage_print 42 * Purpose: 43 * print the usage of all the supported commands by this unit. 44 * Parameters: 45 * unit - (IN) Unit number. 46 * diag_pack - (IN) Diag pack table. 47 * diag_id_support - (IN) Callback to a function that checks if diag_id supported. 48 */ 49 void diag_dnx_usage_print(int unit, 50 const diag_dnx_table_t *diag_pack, 51 diag_dnx_diag_id_supported_func_ptr_t diag_id_support); 52 53 /* 54 * Function: 55 * diag_dnx_usage_print 56 * Purpose: 57 * Dispatch according to command name and if the diag_id is supported. 58 * Parameters: 59 * unit - (IN) Unit number. 60 * diag_pack - (IN) Diag pack table. 61 * diag_id_support - (IN) Callback to a function that checks if diag_id supported. 62 * cmd_name - (IN) Command full name. 63 * args - (IN) args required by the command. 64 */ 65 cmd_result_t diag_dnx_dispatch(int unit, 66 const diag_dnx_table_t *diag_pack, 67 diag_dnx_diag_id_supported_func_ptr_t diag_id_support, 68 char *cmd_name, 69 args_t *args); 70 71 int diag_dcmn_phy_measure_port(int unit, bcm_port_t port, bcm_stat_val_t type,uint32* rate_int, uint32* rate_remainder); 72 73 cmd_result_t dpp_do_dump_table(int unit, soc_mem_t mem, unsigned array_index, int copyno, int index, int count, int flags); 74 /* read or write wide memory, supports ARAD only */ 75 cmd_result_t 76 _soc_arad_mem_array_wide_access(int unit, uint32 flags, soc_mem_t mem, unsigned array_index, int copyno, int index, void *entry_data, 77 unsigned operation) ;/* operation should be 1 for read and 0 for write */ 78 79 /* Get the root node for the diags list and the top node in the file(creates the file if does not exist) */ 80 int dnx_diag_xml_root_get(int unit, char* xml_file, void **curTop, void **curRoot); 81 82 #if (!defined(BCM_DNX_SUPPORT) && !defined(BCM_DNXF_SUPPORT)) 83 /*************************************** 84 * Writes last packet information 85 * to info parameter 86 */ 87 cmd_result_t 88 dpp_diag_last_packet_info_get(int unit, int core, SOC_TMC_DIAG_LAST_PACKET_INFO *info); 89 #endif 90 91 #define DIAG_COUNTERS_F_ARADPLUS_ONLY 0x1 92 93 #define DIAG_COUNTERS_F_JERICHO_ONLY 0x2 94 #define DIAG_COUNTERS_F_JERICHOPLUS_ONLY 0x4 95 96 typedef struct diag_counter_data_s { 97 char* reg_name; 98 soc_block_type_t block; 99 soc_reg_t reg; 100 unsigned reg_index; /* register index, should be 0 when not a register array. */ 101 soc_field_t cnt_field; 102 soc_field_t overflow_field; 103 uint32 flags; 104 } diag_counter_data_t; 105 106 typedef enum jericho_graphic_counters { 107 108 EGQ_EHP_MULTICAST_HIGH_DISCARDS_COUNTER, 109 EGQ_EHP_MULTICAST_LOW_DISCARDS_COUNTER, 110 EGQ_ERPP_LAG_PRUNING_DISCARDS_COUNTER, 111 EGQ_ERPP_PMF_DISCARDS_COUNTER, 112 EGQ_ERPP_VLAN_MEMBERSHIP_DISCARDS_COUNTER, 113 EGQ_EHP_DISCARD_PACKET_COUNTER, 114 EGQ_EHP_MULTICAST_HIGH_PACKET_COUNTER, 115 EGQ_EHP_MULTICAST_LOW_PACKET_COUNTER, 116 EGQ_EHP_UNICAST_PACKET_COUNTER, 117 EGQ_FQP_PACKET_COUNTER, 118 EGQ_PQP_DISCARD_MULTICAST_PACKET_COUNTER, 119 EGQ_PQP_DISCARD_UNICAST_PACKET_COUNTER, 120 EGQ_PQP_MULTICAST_BYTES_COUNTER, 121 EGQ_PQP_MULTICAST_PACKET_COUNTER, 122 EGQ_PQP_UNICAST_BYTES_COUNTER, 123 EGQ_PQP_UNICAST_PACKET_COUNTER, 124 EPNI_EPE_BYTES_COUNTER, 125 EPNI_EPE_DISCARDED_PACKETS_COUNTER, 126 EPNI_EPE_PACKET_COUNTER, 127 FDA_EGQ_N_CELLS_IN_CNT_IPT0, 128 FDA_EGQ_N_CELLS_IN_CNT_IPT1, 129 FDA_EGQ_N_CELLS_IN_CNT_MESHMC0, 130 FDA_EGQ_N_CELLS_IN_CNT_MESHMC1, 131 FDA_EGQ_N_CELLS_IN_CNT_TDM0, 132 FDA_EGQ_N_CELLS_IN_CNT_TDM1, 133 FDA_EGQ_N_CELLS_OUT_CNT_IPT0, 134 FDA_EGQ_N_CELLS_OUT_CNT_IPT1, 135 FDA_EGQ_N_CELLS_OUT_CNT_FAB_PIPE_10, 136 FDA_EGQ_N_CELLS_OUT_CNT_FAB_PIPE_11, 137 FDA_EGQ_N_CELLS_OUT_CNT_FAB_PIPE_00, 138 FDA_EGQ_N_CELLS_OUT_CNT_FAB_PIPE_01, 139 FDA_EGQ_N_CELLS_OUT_CNT_FAB_PIPE_20, 140 FDA_EGQ_N_CELLS_OUT_CNT_FAB_PIPE_21, 141 FDA_EGQ_N_CELLS_OUT_CNT_TDM0, 142 FDA_EGQ_N_CELLS_OUT_CNT_TDM1, 143 FDA_EGQ_N_CELLS_OUT_CNT_MESHMC0, 144 FDA_EGQ_N_CELLS_OUT_CNT_MESHMC1, 145 FDA_EGQ_N_FABFIF_0_PRIO_1_DROP_CNT0, 146 FDA_EGQ_N_FABFIF_0_PRIO_1_DROP_CNT1, 147 FDA_EGQ_N_FABFIF_0_PRIO_0_DROP_CNT0, 148 FDA_EGQ_N_FABFIF_0_PRIO_0_DROP_CNT1, 149 FDA_EGQ_N_FABFIF_0_PRIO_2_DROP_CNT0, 150 FDA_EGQ_N_FABFIF_0_PRIO_2_DROP_CNT1, 151 FDA_EGQ_N_FABFIF_1_PRIO_0_DROP_CNT0, 152 FDA_EGQ_N_FABFIF_1_PRIO_0_DROP_CNT1, 153 FDA_EGQ_N_FABFIF_1_PRIO_1_DROP_CNT0, 154 FDA_EGQ_N_FABFIF_1_PRIO_1_DROP_CNT1, 155 FDA_EGQ_N_FABFIF_1_PRIO_2_DROP_CNT0, 156 FDA_EGQ_N_FABFIF_1_PRIO_2_DROP_CNT1, 157 FDA_EGQ_N_FABFIF_2_PRIO_1_DROP_CNT0, 158 FDA_EGQ_N_FABFIF_2_PRIO_1_DROP_CNT1, 159 FDA_EGQ_N_FABFIF_2_PRIO_0_DROP_CNT0, 160 FDA_EGQ_N_FABFIF_2_PRIO_0_DROP_CNT1, 161 FDA_EGQ_N_FABFIF_2_PRIO_2_DROP_CNT0, 162 FDA_EGQ_N_FABFIF_2_PRIO_2_DROP_CNT1, 163 FDA_EGQ_N_MESHMC_PRIO_0_DROP_CNT0, 164 FDA_EGQ_N_MESHMC_PRIO_0_DROP_CNT1, 165 FDA_EGQ_N_MESHMC_PRIO_1_DROP_CNT0, 166 FDA_EGQ_N_MESHMC_PRIO_1_DROP_CNT1, 167 FDA_EGQ_N_MESHMC_PRIO_2_DROP_CNT0, 168 FDA_EGQ_N_MESHMC_PRIO_2_DROP_CNT1, 169 FDA_EGQ_N_TDM_OVF_DROP_CNT0, 170 FDA_EGQ_N_TDM_OVF_DROP_CNT1, 171 FDA_FAB_36_SCH_CELLS_IN_CNT_P_1, 172 FDA_FAB_48_SCH_CELLS_IN_CNT_P_1, 173 FDA_FAB_36_SCH_CELLS_IN_CNT_P_2, 174 FDA_FAB_48_SCH_CELLS_IN_CNT_P_2, 175 FDA_FAB_36_SCH_CELLS_IN_CNT_P_3, 176 FDA_FAB_48_SCH_CELLS_IN_CNT_P_3, 177 FDR_CELL_IN_CNT, 178 FDR_P_1_CELL_IN_CNT, 179 FDR_P_2_CELL_IN_CNT, 180 FDR_P_3_CELL_IN_CNT, 181 FDT_DESC_CELL_CNT, 182 FDT_IRE_DESC_CELL_CNT, 183 FDT_DATA_CELL_CNT, 184 IDR_MMU_INTERFACE_COUNTER, 185 IDR_OCB_INTERFACE_COUNTER, 186 IPT_CRC_ERR_CNT, 187 IPT_CFG_EVNT_CNT, 188 IPT_CFG_BYT_CNT, 189 IPT_EGQ_0_PKT_CNT, 190 IPT_EGQ_1_PKT_CNT, 191 IPT_ENQ_0_PKT_CNT, 192 IPT_ENQ_1_PKT_CNT, 193 IPT_FDT_0_PKT_CNT, 194 IPT_FDT_1_PKT_CNT, 195 IQM_DEQUEUE_PACKET_COUNTER, 196 IQM_ENQUEUE_PACKET_COUNTER, 197 IQM_QUEUE_DELETED_PACKET_COUNTER, 198 IQM_QUEUE_ENQ_DISCARDED_PACKET_COUNTER, 199 IRE_CPU_PACKET_COUNTER, 200 IRE_FDT_INTERFACE_COUNTER, 201 IRE_NIF_N_PACKET_COUNTER0, 202 IRE_NIF_N_PACKET_COUNTER1, 203 IRE_OAMP_PACKET_COUNTER, 204 IRE_OLP_PACKET_COUNTER, 205 IRE_RCY_N_PACKET_COUNTER0, 206 IRE_RCY_N_PACKET_COUNTER1, 207 IRE_RCY_N_PACKET_COUNTER2, 208 IRE_RCY_N_PACKET_COUNTER3, 209 MMU_IDR_PACKET_COUNTER, 210 NBIH_RX_TOTAL_BYTE_COUNTER, 211 NBIH_RX_TOTAL_PKT_COUNTER, 212 NBIH_RX_NUM_TOTAL_DROPPED_EOPS, 213 NBIH_TX_TOTAL_BYTE_COUNTER, 214 NBIH_TX_TOTAL_PKT_COUNTER, 215 NBIL_RX_NUM_TOTAL_DROPPED_EOPS, 216 NOF_GRAPHIC_COUNTERS /*always last*/ 217 218 } jericho_graphic_counters_e; 219 220 typedef enum jericho_rqp_graphic_counters { 221 EGQ_PRP_PACKET_GOOD_UC_CNT0, 222 EGQ_PRP_PACKET_GOOD_UC_CNT1, 223 EGQ_PRP_PACKET_GOOD_MC_CNT0, 224 EGQ_PRP_PACKET_GOOD_MC_CNT1, 225 EGQ_PRP_PACKET_GOOD_TDM_CNT0, 226 EGQ_PRP_PACKET_GOOD_TDM_CNT1, 227 EGQ_PRP_PACKET_DISCARD_UC_CNT0, 228 EGQ_PRP_PACKET_DISCARD_UC_CNT1, 229 EGQ_PRP_PACKET_DISCARD_MC_CNT0, 230 EGQ_PRP_PACKET_DISCARD_MC_CNT1, 231 EGQ_PRP_PACKET_DISCARD_TDM_CNT0, 232 EGQ_PRP_PACKET_DISCARD_TDM_CNT1, 233 EGQ_PRP_SOP_DISCARD_UC_CNT0, 234 EGQ_PRP_SOP_DISCARD_UC_CNT1, 235 EGQ_PRP_SOP_DISCARD_MC_CNT0, 236 EGQ_PRP_SOP_DISCARD_MC_CNT1, 237 EGQ_PRP_SOP_DISCARD_TDM_CNT0, 238 EGQ_PRP_SOP_DISCARD_TDM_CNT1, 239 NOF_RQP_GRAPHIC_COUNTERS /*always last*/ 240 } jericho_rqp_graphic_counters_e; 241 242 typedef enum qax_graphic_counters { 243 244 QAX_EGQ_EHP_DISCARD_PACKET_COUNTER, 245 QAX_EGQ_EHP_MULTICAST_HIGH_PACKET_COUNTER, 246 QAX_EGQ_EHP_MULTICAST_LOW_PACKET_COUNTER, 247 QAX_EGQ_EHP_UNICAST_PACKET_COUNTER, 248 QAX_EGQ_FQP_PACKET_COUNTER, 249 QAX_EGQ_PQP_DISCARD_MULTICAST_PACKET_COUNTER, 250 QAX_EGQ_PQP_DISCARD_UNICAST_PACKET_COUNTER, 251 QAX_EGQ_PQP_MULTICAST_BYTES_COUNTER, 252 QAX_EGQ_PQP_MULTICAST_PACKET_COUNTER, 253 QAX_EGQ_PQP_UNICAST_BYTES_COUNTER, 254 QAX_EGQ_PQP_UNICAST_PACKET_COUNTER, 255 QAX_EPNI_EPE_BYTES_COUNTER, 256 QAX_EPNI_EPE_DISCARDED_PACKETS_COUNTER, 257 QAX_EPNI_EPE_PACKET_COUNTER, 258 QAX_FDA_EGQ_N_CELLS_IN_CNT_IPT, 259 QAX_FDA_EGQ_N_CELLS_IN_CNT_MESHMC, 260 QAX_FDA_EGQ_N_CELLS_IN_CNT_TDM, 261 QAX_FDA_EGQ_N_CELLS_OUT_CNT_IPT, 262 QAX_FDA_EGQ_N_CELLS_OUT_CNT_FAB_PIPE_1, 263 QAX_FDA_EGQ_N_CELLS_OUT_CNT_FAB_PIPE_0, 264 QAX_FDA_EGQ_N_CELLS_OUT_CNT_FAB_PIPE_2, 265 QAX_FDA_EGQ_N_CELLS_OUT_CNT_TDM, 266 QAX_FDA_EGQ_N_CELLS_OUT_CNT_MESHMC, 267 QAX_FDA_EGQ_N_MESHMC_PRIO_0_DROP_CNT, 268 QAX_FDA_EGQ_N_MESHMC_PRIO_1_DROP_CNT, 269 QAX_FDA_EGQ_N_MESHMC_PRIO_2_DROP_CNT, 270 QAX_FDA_EGQ_N_TDM_OVF_DROP_CNT, 271 QAX_FDR_CELL_IN_CNT, 272 QAX_FDR_P_1_CELL_IN_CNT, 273 QAX_FDR_P_2_CELL_IN_CNT, 274 QAX_FDR_P_3_CELL_IN_CNT, 275 QAX_FDT_DESC_CELL_CNT, 276 QAX_FDT_IRE_DESC_CELL_CNT, 277 QAX_FDT_DATA_CELL_CNT, 278 /*QAX_IDR_MMU_INTERFACE_COUNTER,*/ 279 /*QAX_IDR_OCB_INTERFACE_COUNTER,*/ 280 /*QAX_IPT_CRC_ERR_CNT,*/ 281 /*QAX_IPT_CFG_EVNT_CNT, 282 QAX_IPT_CFG_BYT_CNT, 283 QAX_IPT_FDT_0_PKT_CNT, 284 QAX_IPT_FDT_1_PKT_CNT,*/ 285 QAX_CGM_VOQ_SRAM_DEQ_PACKET_COUNTER, 286 QAX_CGM_VOQ_SRAM_ENQ_PACKET_COUNTER, 287 QAX_CGM_VOQ_SRAM_DEL_PACKET_COUNTER, 288 QAX_CGM_VOQ_SRAM_ENQ_RJCT_PACKET_COUNTER, 289 QAX_CGM_VOQ_DRAM_DEQ_PACKET_COUNTER, 290 QAX_CGM_VOQ_DRAM_ENQ_PACKET_COUNTER, 291 QAX_CGM_VOQ_DRAM_DEL_PACKET_COUNTER, 292 QAX_IRE_CPU_PACKET_COUNTER, 293 QAX_IRE_FDT_INTERFACE_COUNTER, 294 QAX_IRE_NIF_PACKET_COUNTER, 295 QAX_IRE_OAMP_PACKET_COUNTER, 296 QAX_IRE_OLP_PACKET_COUNTER, 297 QAX_IRE_RCY_PACKET_COUNTER, 298 QAX_MMU_IDR_PACKET_COUNTER, 299 QAX_SPB_ALMOST_FULL_0_SRAM_REJECT_COUNTER, 300 QAX_SPB_ALMOST_FULL_1_SRAM_REJECT_COUNTER, 301 QAX_SPB_ALMOST_FULL_2_SRAM_REJECT_COUNTER, 302 QAX_SPB_ALMOST_FULL_SRAM_REJECT_COUNTER, 303 QAX_NBIH_RX_TOTAL_BYTE_COUNTER, 304 QAX_NBIH_RX_TOTAL_PKT_COUNTER, 305 QAX_NBIH_RX_NUM_TOTAL_DROPPED_EOPS, 306 QAX_NBIH_TX_TOTAL_BYTE_COUNTER, 307 QAX_NBIH_TX_TOTAL_PKT_COUNTER, 308 QAX_NBIL_RX_NUM_TOTAL_DROPPED_EOPS, 309 QAX_TXQ_EGQ_SRAM_COUNTER, 310 QAX_TXQ_EGQ_DRAM_COUNTER, 311 QAX_TXQ_FDT_SRAM_COUNTER, 312 QAX_TXQ_FDT_DRAM_COUNTER, 313 QAX_NOF_GRAPHIC_COUNTERS /*always last*/ 314 315 } qax_graphic_counters_e; 316 317 typedef enum qux_graphic_counters { 318 /** EHP */ 319 QUX_EGQ_EHP_DISCARD_PACKET_COUNTER, 320 QUX_EGQ_EHP_MULTICAST_HIGH_PACKET_COUNTER, 321 QUX_EGQ_EHP_MULTICAST_LOW_PACKET_COUNTER, 322 QUX_EGQ_EHP_UNICAST_PACKET_COUNTER, 323 QUX_EGQ_EHP_MULTICAST_HIGH_DISCARDS_COUNTER, 324 QUX_EGQ_EHP_MULTICAST_LOW_DISCARDS_COUNTER, 325 326 /** FQP */ 327 QUX_EGQ_FQP_CELL_COUNTER, 328 QUX_EGQ_FQP_PACKET_COUNTER, 329 /** PQP */ 330 QUX_EGQ_PQP_DISCARD_MULTICAST_PACKET_COUNTER, 331 QUX_EGQ_PQP_DISCARD_UNICAST_PACKET_COUNTER, 332 QUX_EGQ_PQP_MULTICAST_BYTES_COUNTER, 333 QUX_EGQ_PQP_MULTICAST_PACKET_COUNTER, 334 QUX_EGQ_PQP_UNICAST_BYTES_COUNTER, 335 QUX_EGQ_PQP_UNICAST_PACKET_COUNTER, 336 337 QUX_EPNI_EPE_BYTES_COUNTER, 338 QUX_EPNI_EPE_DISCARDED_PACKETS_COUNTER, 339 QUX_EPNI_EPE_PACKET_COUNTER, 340 QUX_EPNI_EPE_MIRRORED_PACKETS_COUNTER, 341 342 QUX_CGM_VOQ_SRAM_DEQ_PACKET_COUNTER, 343 QUX_CGM_VOQ_SRAM_ENQ_PACKET_COUNTER, 344 QUX_CGM_VOQ_SRAM_DEL_PACKET_COUNTER, 345 QUX_CGM_VOQ_SRAM_ENQ_RJCT_PACKET_COUNTER, 346 QUX_CGM_VOQ_DRAM_DEQ_PACKET_COUNTER, 347 QUX_CGM_VOQ_DRAM_ENQ_PACKET_COUNTER, 348 QUX_CGM_VOQ_DRAM_DEL_PACKET_COUNTER, 349 QUX_CGM_QNUM_NOT_VALID_PACKETS, 350 351 QUX_IRE_CPU_PACKET_COUNTER, 352 QUX_IRE_NIF_PACKET_COUNTER, 353 QUX_IRE_OAMP_PACKET_COUNTER, 354 QUX_IRE_OLP_PACKET_COUNTER, 355 QUX_IRE_RCY_PACKET_COUNTER, 356 QUX_IRE_IPSEC_PACKET_COUNTER, 357 QUX_IRE_SAT_PACKET_COUNTER, 358 359 QUX_MMU_RD_REQ_COUNTER, 360 QUX_MMU_WR_REQ_COUNTER, 361 QUX_MMU_SPB_GOOD_PACKET_CNT, 362 QUX_MMU_SPB_PACKET_ERROR_CNT, 363 QUX_MMU_DRAM_GOOD_PACKET_CNT, 364 QUX_MMU_DRAM_PACKET_CRC_ERROR_CNT, 365 QUX_MMU_DRAM_PACKET_PKUP_DISCARD_CNT, 366 367 QUX_SPB_ALMOST_FULL_0_SRAM_REJECT_COUNTER, 368 QUX_SPB_ALMOST_FULL_1_SRAM_REJECT_COUNTER, 369 QUX_SPB_ALMOST_FULL_2_SRAM_REJECT_COUNTER, 370 QUX_SPB_ALMOST_FULL_SRAM_REJECT_COUNTER, 371 QUX_SPB_FULL_SRAM_REJECT_COUNTER, 372 QUX_SPB_DISCARDED_PACKETS_CNT_0, 373 QUX_SPB_DISCARDED_PACKETS_CNT_1, 374 QUX_SPB_DISCARDED_PACKETS_CNT_2, 375 QUX_SPB_DISCARDED_PACKETS_CNT_3, 376 377 QUX_NIF_RX_TOTAL_BYTE_COUNTER, 378 QUX_NIF_RX_TOTAL_PKT_COUNTER, 379 QUX_NIF_RX_NUM_TOTAL_DROPPED_EOPS, 380 QUX_NIF_TX_TOTAL_BYTE_COUNTER, 381 QUX_NIF_TX_TOTAL_PKT_COUNTER, 382 QUX_TXQ_EGQ_SRAM_COUNTER, 383 QUX_TXQ_EGQ_DRAM_COUNTER, 384 QUX_NOF_GRAPHIC_COUNTERS /*always last*/ 385 } qux_graphic_counters_e; 386 387 typedef enum qux_rqp_graphic_counters { 388 QUX_EGQ_PRP_PACKET_GOOD_UC_CNT, 389 QUX_EGQ_PRP_PACKET_GOOD_MC_CNT, 390 QUX_EGQ_PRP_PACKET_DISCARD_UC_CNT, 391 QUX_EGQ_PRP_PACKET_DISCARD_MC_CNT, 392 QUX_EGQ_PRP_SOP_DISCARD_UC_CNT, 393 QUX_EGQ_PRP_SOP_DISCARD_MC_CNT, 394 QUX_EGQ_PRP_PACKET_IN_CNT, 395 QUX_EGQ_PQP_CELL_IN_CNT, 396 NOF_QUX_RQP_GRAPHIC_COUNTERS /*always last*/ 397 } qux_rqp_graphic_counters_e; 398 399 400 typedef enum qax_rqp_graphic_counters { 401 ASLALSLSALSA 402 } qax_rqp_graphic_counters_e; 403 404 #endif /*_DIAG_H_INCLUDED_*/