cmicx_sim_sbus_dma.h (43445B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 8 /* 9 * cmicx_sim_sbus_dma.h 10 * 11 * this file contains header definitions for sbus dma functionality 12 */ 13 14 #ifndef _CMICX_SIM_SBUS_DMA_H_ 15 #define _CMICX_SIM_SBUS_DMA_H_ 16 17 /* includes */ 18 #include "cmicx_sim_util.h" 19 20 21 /* defines for SBUS DMA register bits */ 22 #define CMIC_SBUSDMA_CONTROL_DESC_LAST_BIT 31 23 #define CMIC_SBUSDMA_CONTROL_DESC_SKIP_BIT 30 24 #define CMIC_SBUSDMA_CONTROL_DESC_JUMP_BIT 29 25 #define CMIC_SBUSDMA_CONTROL_DESC_APPEND_BIT 28 26 #define CMIC_SBUSDMA_CONTROL_DESC_DESCRIPTORS_REMAINING_MSB 27 27 #define CMIC_SBUSDMA_CONTROL_DESC_DESCRIPTORS_REMAINING_LSB 24 28 #define CMIC_SBUSDMA_CONTROL_REG_DESC_PREFETCH_ENABLE_BIT 4 29 #define CMIC_SBUSDMA_CONTROL_REG_ENDIANNESS_BIT 3 30 #define CMIC_SBUSDMA_CONTROL_REG_MODE_BIT 2 31 #define CMIC_SBUSDMA_CONTROL_REG_ABORT_BIT 1 32 #define CMIC_SBUSDMA_CONTROL_REG_START_BIT 0 33 #define CMIC_SBUSDMA_REQUEST_REG_DECR_BIT 31 34 #define CMIC_SBUSDMA_REQUEST_REG_REQ_SINGLE_BIT 30 35 #define CMIC_SBUSDMA_REQUEST_REG_INCR_NOADD_BIT 29 36 #define CMIC_SBUSDMA_REQUEST_REG_INCR_SHIFT_MSB 28 37 #define CMIC_SBUSDMA_REQUEST_REG_INCR_SHIFT_LSB 24 38 #define CMIC_SBUSDMA_REQUEST_REG_PEND_CLOCKS_MSB 23 39 #define CMIC_SBUSDMA_REQUEST_REG_PEND_CLOCKS_LSB 16 40 #define CMIC_SBUSDMA_REQUEST_REG_DMA_WR_TO_NULLSPACE_BIT 13 41 #define CMIC_SBUSDMA_REQUEST_REG_WORDSWAP_IN_64BIT_SBUSDATA_BIT 12 42 #define CMIC_SBUSDMA_REQUEST_REG_MEMWR_ENDIANNESS_BIT 11 43 #define CMIC_SBUSDMA_REQUEST_REG_MEMRD_ENDIANNESS_BIT 10 44 #define CMIC_SBUSDMA_REQUEST_REG_REQ_WORDS_MSB 9 45 #define CMIC_SBUSDMA_REQUEST_REG_REQ_WORDS_LSB 5 46 #define CMIC_SBUSDMA_REQUEST_REG_REP_WORDS_MSB 4 47 #define CMIC_SBUSDMA_REQUEST_REG_REP_WORDS_LSB 0 48 #define CMIC_SBUSDMA_STATUS_REG_ECC_2BIT_CHECK_FAIL_BIT 13 49 #define CMIC_SBUSDMA_STATUS_REG_SBUSDMA_ACTIVE_BIT 12 50 #define CMIC_SBUSDMA_STATUS_REG_ACTIVE_BIT 11 51 #define CMIC_SBUSDMA_STATUS_REG_DESCRD_ERROR_BIT 10 52 #define CMIC_SBUSDMA_STATUS_REG_SBUSACK_TIMEOUT_BIT 9 53 #define CMIC_SBUSDMA_STATUS_REG_SBUSACK_ERROR_BIT 8 54 #define CMIC_SBUSDMA_STATUS_REG_SBUSACK_NACK_BIT 7 55 #define CMIC_SBUSDMA_STATUS_REG_SBUSACK_WRONG_OPCODE_BIT 6 56 #define CMIC_SBUSDMA_STATUS_REG_SBUSACK_WRONG_BEATCOUNT_BIT 5 57 #define CMIC_SBUSDMA_STATUS_REG_SER_CHECK_FAIL_BIT 4 58 #define CMIC_SBUSDMA_STATUS_REG_HOSTMEMRD_ERROR_BIT 3 59 #define CMIC_SBUSDMA_STATUS_REG_HOSTMEMWR_ERROR_BIT 2 60 #define CMIC_SBUSDMA_STATUS_REG_ERROR_BIT 1 61 #define CMIC_SBUSDMA_STATUS_REG_DONE_BIT 0 62 #define CMIC_SBUSDMA_DEBUG_REG_ECC_2BIT_CHECK_FAIL_BIT 1 63 #define CMIC_SBUSDMA_DEBUG_REG_DESC_DONE_BIT 0 64 #define CMIC_SBUSDMA_CONFIG_REG_ENABLE_EARLY_BRESP_BIT 3 65 #define CMIC_SBUSDMA_CONFIG_REG_ENABLE_SBUSDMA_CH2_FLOW_CONTROL_BIT 2 66 #define CMIC_SBUSDMA_CONFIG_REG_ENABLE_SBUSDMA_CH1_FLOW_CONTROL_BIT 1 67 #define CMIC_SBUSDMA_CONFIG_REG_ENABLE_SBUSDMA_CH0_FLOW_CONTROL_BIT 0 68 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH0_WEIGHT_LSB 0 69 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH0_WEIGHT_MSB 3 70 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH1_WEIGHT_LSB 4 71 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH1_WEIGHT_MSB 7 72 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH2_WEIGHT_LSB 8 73 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH2_WEIGHT_MSB 11 74 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH0_WEIGHT_LSB 12 75 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH0_WEIGHT_MSB 15 76 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH1_WEIGHT_LSB 16 77 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH1_WEIGHT_MSB 19 78 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH2_WEIGHT_LSB 20 79 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH2_WEIGHT_MSB 23 80 81 /* defines for sbus dma functionality */ 82 #define CMIC_SBUS_DMA_ACCESS_COUNTDOWN_VALUE 4 83 #define CMIC_SBUS_DMA_ID_STRING_LENGTH 32 84 #define CMIC_SBUS_DMA_WORDS_PER_DESCRIPTOR 8 85 #define CMIC_SBUS_DMA_BYTES_PER_WORD 4 86 #define CMIC_SBUS_DMA_DESCRIPTOR_MODE true 87 #define CMIC_SBUS_DMA_REGISTER_MODE false 88 89 90 /* sbus dma data struct - contains all the data necessary for sbus dma handling */ 91 typedef struct { 92 93 /* identification string for this sbus dma module */ 94 char id_string[CMIC_SBUS_DMA_ID_STRING_LENGTH]; 95 96 /* control register values */ 97 bool desc_prefetch_enable; 98 bool endianness; 99 bool mode; 100 bool start; 101 bool command_is_write; 102 103 /* internal control values */ 104 bool last_desc; /* indicates the last descriptor in a descriptor stream */ 105 bool timer_running; /* high when we are in timer mode and an access has been started (by the control register), whether an access is currently running or not */ 106 bool access_running; /* high when we are running an sbus dma access of any kind */ 107 int timer_countdown; /* current countdown value to next sbus dma initiation. taken from the timer register initially. */ 108 bool sequence_pending; /* high when we have an sbus dma sequence running (pending) */ 109 int sbus_command_countdown; /* countdown for a single sbus command completion */ 110 int pend_clocks_countdown; /* countdown for the pending clocks waiting period in between sbus commands */ 111 112 /* request register values */ 113 bool decrement; 114 bool req_single; 115 bool incr_noadd; 116 int incr_shift; 117 int pend_clocks; 118 bool dma_wr_to_nullspace; 119 bool wordswap_in_64bit_sbus_data; 120 bool memwr_endianness; 121 bool memrd_endianness; 122 int req_words; 123 int resp_words; 124 125 /* count register values */ 126 unsigned int cur_count; 127 128 /* opcode register value */ 129 reg_t opcode; 130 131 /* start register address value */ 132 addr_t cur_sbus_address; 133 134 /* hostmem register address value */ 135 uint64_t cur_hostmem_address; 136 137 /* hostmem descriptor start address value */ 138 uint64_t cur_desc_address; 139 140 /* status bits */ 141 bool ecc_2bit_check_fail; 142 bool sbusdma_active; 143 bool active; 144 bool descrd_error; 145 bool sbusack_timeout; 146 bool sbusack_error; 147 bool sbusack_nack; 148 bool sbusack_wrong_opcode; 149 bool sbusack_wrong_beatcount; 150 bool ser_check_fail; 151 bool hostmemrd_error; 152 bool hostmemwr_error; 153 bool error; 154 bool done; 155 156 /* debug register values */ 157 bool desc_done; 158 159 /* iter count register value */ 160 reg_t iter_count; 161 162 /* timer register value */ 163 reg_t timer; 164 165 /* last configured values for things */ 166 reg_t cur_sbusdma_config_request; 167 reg_t cur_sbusdma_config_count; 168 reg_t cur_sbusdma_config_opcode; 169 reg_t cur_sbusdma_config_sbus_start_address; 170 uint64_t cur_sbusdma_config_hostmem_start_address; 171 uint64_t cur_sbusdma_config_desc_start_address; 172 173 /* per cmc sbusdma config values */ 174 bool enable_sbusdma_flow_control; 175 176 } cmicx_sbus_dma_data_t; 177 178 179 /* sbus dma support functions */ 180 struct cmicx_cmc_struct; 181 bool cmic_sbus_dma_access_start(cmicx_sbus_dma_data_t *sbus_dma_data); 182 bool cmic_sbus_dma_access_abort(cmicx_sbus_dma_data_t *sbus_dma_data); 183 bool cmic_sbusdma_control_read(reg_t *reg,cmicx_sbus_dma_data_t *); 184 bool cmic_sbusdma_control_write(reg_t reg,cmicx_sbus_dma_data_t *); 185 bool cmic_sbusdma_request_read(reg_t *reg,cmicx_sbus_dma_data_t *); 186 bool cmic_sbusdma_request_write(reg_t reg,cmicx_sbus_dma_data_t *); 187 bool cmic_sbusdma_count_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data); 188 bool cmic_sbusdma_opcode_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data); 189 bool cmic_sbusdma_sbus_start_address_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data); 190 bool cmic_sbusdma_hostmem_start_address_lo_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data); 191 bool cmic_sbusdma_hostmem_start_address_hi_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data); 192 bool cmic_sbusdma_desc_start_address_lo_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data); 193 bool cmic_sbusdma_desc_start_address_hi_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data); 194 bool cmic_sbusdma_status_read(reg_t *reg,cmicx_sbus_dma_data_t *); 195 bool cmic_sbusdma_shared_config_read(reg_t *val,struct cmicx_cmc_struct *cmc); 196 bool cmic_sbusdma_shared_config_write(reg_t val,struct cmicx_cmc_struct *cmc); 197 bool cmic_sbusdma_debug_read(reg_t *val,cmicx_sbus_dma_data_t *sbus_dma_data); 198 bool cmic_sbusdma_debug_clr_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data); 199 200 201 /* sbus dma register access functions */ 202 pcid_read_func_t cmic_top_sbus_ring_arb_ctrl_sbusdma_read; 203 pcid_write_func_t cmic_top_sbus_ring_arb_ctrl_sbusdma_write; 204 pcid_read_func_t cmic_cmc0_shared_config_read; 205 pcid_write_func_t cmic_cmc0_shared_config_write; 206 pcid_read_func_t cmic_cmc0_sbusdma_ch0_control_read; 207 pcid_write_func_t cmic_cmc0_sbusdma_ch0_control_write; 208 pcid_read_func_t cmic_cmc0_sbusdma_ch0_request_read; 209 pcid_write_func_t cmic_cmc0_sbusdma_ch0_request_write; 210 pcid_read_func_t cmic_cmc0_sbusdma_ch0_count_read; 211 pcid_write_func_t cmic_cmc0_sbusdma_ch0_count_write; 212 pcid_read_func_t cmic_cmc0_sbusdma_ch0_opcode_read; 213 pcid_write_func_t cmic_cmc0_sbusdma_ch0_opcode_write; 214 pcid_read_func_t cmic_cmc0_sbusdma_ch0_sbus_start_address_read; 215 pcid_write_func_t cmic_cmc0_sbusdma_ch0_sbus_start_address_write; 216 pcid_read_func_t cmic_cmc0_sbusdma_ch0_hostmem_start_address_lo_read; 217 pcid_write_func_t cmic_cmc0_sbusdma_ch0_hostmem_start_address_lo_write; 218 pcid_read_func_t cmic_cmc0_sbusdma_ch0_hostmem_start_address_hi_read; 219 pcid_write_func_t cmic_cmc0_sbusdma_ch0_hostmem_start_address_hi_write; 220 pcid_read_func_t cmic_cmc0_sbusdma_ch0_desc_start_address_lo_read; 221 pcid_write_func_t cmic_cmc0_sbusdma_ch0_desc_start_address_lo_write; 222 pcid_read_func_t cmic_cmc0_sbusdma_ch0_desc_start_address_hi_read; 223 pcid_write_func_t cmic_cmc0_sbusdma_ch0_desc_start_address_hi_write; 224 pcid_read_func_t cmic_cmc0_sbusdma_ch0_status_read; 225 pcid_write_func_t cmic_cmc0_sbusdma_ch0_status_write; 226 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_hostmem_address_lo_read; 227 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_hostmem_address_lo_write; 228 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_hostmem_address_hi_read; 229 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_hostmem_address_hi_write; 230 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_sbus_address_read; 231 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_sbus_address_write; 232 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_desc_address_lo_read; 233 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_desc_address_lo_write; 234 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_desc_address_hi_read; 235 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_desc_address_hi_write; 236 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_request_read; 237 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_request_write; 238 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_count_read; 239 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_count_write; 240 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_read; 241 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_write; 242 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_read; 243 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_write; 244 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_read; 245 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_write; 246 pcid_read_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_opcode_read; 247 pcid_write_func_t cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_opcode_write; 248 pcid_read_func_t cmic_cmc0_sbusdma_ch0_sbusdma_debug_read; 249 pcid_write_func_t cmic_cmc0_sbusdma_ch0_sbusdma_debug_write; 250 pcid_read_func_t cmic_cmc0_sbusdma_ch0_sbusdma_debug_clr_read; 251 pcid_write_func_t cmic_cmc0_sbusdma_ch0_sbusdma_debug_clr_write; 252 pcid_read_func_t cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_address_lo_read; 253 pcid_write_func_t cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_address_lo_write; 254 pcid_read_func_t cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_address_hi_read; 255 pcid_write_func_t cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_address_hi_write; 256 pcid_read_func_t cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_control_read; 257 pcid_write_func_t cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_control_write; 258 pcid_read_func_t cmic_cmc0_sbusdma_ch0_iter_count_read; 259 pcid_write_func_t cmic_cmc0_sbusdma_ch0_iter_count_write; 260 pcid_read_func_t cmic_cmc0_sbusdma_ch0_timer_read; 261 pcid_write_func_t cmic_cmc0_sbusdma_ch0_timer_write; 262 pcid_read_func_t cmic_cmc0_sbusdma_ch0_tm_control_0_read; 263 pcid_write_func_t cmic_cmc0_sbusdma_ch0_tm_control_0_write; 264 pcid_read_func_t cmic_cmc0_sbusdma_ch0_tm_control_1_read; 265 pcid_write_func_t cmic_cmc0_sbusdma_ch0_tm_control_1_write; 266 pcid_read_func_t cmic_cmc0_sbusdma_ch0_tm_control_2_read; 267 pcid_write_func_t cmic_cmc0_sbusdma_ch0_tm_control_2_write; 268 pcid_read_func_t cmic_cmc0_sbusdma_ch1_control_read; 269 pcid_write_func_t cmic_cmc0_sbusdma_ch1_control_write; 270 pcid_read_func_t cmic_cmc0_sbusdma_ch1_request_read; 271 pcid_write_func_t cmic_cmc0_sbusdma_ch1_request_write; 272 pcid_read_func_t cmic_cmc0_sbusdma_ch1_count_read; 273 pcid_write_func_t cmic_cmc0_sbusdma_ch1_count_write; 274 pcid_read_func_t cmic_cmc0_sbusdma_ch1_opcode_read; 275 pcid_write_func_t cmic_cmc0_sbusdma_ch1_opcode_write; 276 pcid_read_func_t cmic_cmc0_sbusdma_ch1_sbus_start_address_read; 277 pcid_write_func_t cmic_cmc0_sbusdma_ch1_sbus_start_address_write; 278 pcid_read_func_t cmic_cmc0_sbusdma_ch1_hostmem_start_address_lo_read; 279 pcid_write_func_t cmic_cmc0_sbusdma_ch1_hostmem_start_address_lo_write; 280 pcid_read_func_t cmic_cmc0_sbusdma_ch1_hostmem_start_address_hi_read; 281 pcid_write_func_t cmic_cmc0_sbusdma_ch1_hostmem_start_address_hi_write; 282 pcid_read_func_t cmic_cmc0_sbusdma_ch1_desc_start_address_lo_read; 283 pcid_write_func_t cmic_cmc0_sbusdma_ch1_desc_start_address_lo_write; 284 pcid_read_func_t cmic_cmc0_sbusdma_ch1_desc_start_address_hi_read; 285 pcid_write_func_t cmic_cmc0_sbusdma_ch1_desc_start_address_hi_write; 286 pcid_read_func_t cmic_cmc0_sbusdma_ch1_status_read; 287 pcid_write_func_t cmic_cmc0_sbusdma_ch1_status_write; 288 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_hostmem_address_lo_read; 289 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_hostmem_address_lo_write; 290 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_hostmem_address_hi_read; 291 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_hostmem_address_hi_write; 292 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_sbus_address_read; 293 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_sbus_address_write; 294 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_desc_address_lo_read; 295 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_desc_address_lo_write; 296 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_desc_address_hi_read; 297 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_desc_address_hi_write; 298 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_request_read; 299 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_request_write; 300 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_count_read; 301 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_count_write; 302 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_read; 303 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_write; 304 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_read; 305 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_write; 306 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_read; 307 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_write; 308 pcid_read_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_opcode_read; 309 pcid_write_func_t cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_opcode_write; 310 pcid_read_func_t cmic_cmc0_sbusdma_ch1_sbusdma_debug_read; 311 pcid_write_func_t cmic_cmc0_sbusdma_ch1_sbusdma_debug_write; 312 pcid_read_func_t cmic_cmc0_sbusdma_ch1_sbusdma_debug_clr_read; 313 pcid_write_func_t cmic_cmc0_sbusdma_ch1_sbusdma_debug_clr_write; 314 pcid_read_func_t cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_address_lo_read; 315 pcid_write_func_t cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_address_lo_write; 316 pcid_read_func_t cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_address_hi_read; 317 pcid_write_func_t cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_address_hi_write; 318 pcid_read_func_t cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_control_read; 319 pcid_write_func_t cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_control_write; 320 pcid_read_func_t cmic_cmc0_sbusdma_ch1_iter_count_read; 321 pcid_write_func_t cmic_cmc0_sbusdma_ch1_iter_count_write; 322 pcid_read_func_t cmic_cmc0_sbusdma_ch1_timer_read; 323 pcid_write_func_t cmic_cmc0_sbusdma_ch1_timer_write; 324 pcid_read_func_t cmic_cmc0_sbusdma_ch1_tm_control_0_read; 325 pcid_write_func_t cmic_cmc0_sbusdma_ch1_tm_control_0_write; 326 pcid_read_func_t cmic_cmc0_sbusdma_ch1_tm_control_1_read; 327 pcid_write_func_t cmic_cmc0_sbusdma_ch1_tm_control_1_write; 328 pcid_read_func_t cmic_cmc0_sbusdma_ch1_tm_control_2_read; 329 pcid_write_func_t cmic_cmc0_sbusdma_ch1_tm_control_2_write; 330 pcid_read_func_t cmic_cmc0_sbusdma_ch2_control_read; 331 pcid_write_func_t cmic_cmc0_sbusdma_ch2_control_write; 332 pcid_read_func_t cmic_cmc0_sbusdma_ch2_request_read; 333 pcid_write_func_t cmic_cmc0_sbusdma_ch2_request_write; 334 pcid_read_func_t cmic_cmc0_sbusdma_ch2_count_read; 335 pcid_write_func_t cmic_cmc0_sbusdma_ch2_count_write; 336 pcid_read_func_t cmic_cmc0_sbusdma_ch2_opcode_read; 337 pcid_write_func_t cmic_cmc0_sbusdma_ch2_opcode_write; 338 pcid_read_func_t cmic_cmc0_sbusdma_ch2_sbus_start_address_read; 339 pcid_write_func_t cmic_cmc0_sbusdma_ch2_sbus_start_address_write; 340 pcid_read_func_t cmic_cmc0_sbusdma_ch2_hostmem_start_address_lo_read; 341 pcid_write_func_t cmic_cmc0_sbusdma_ch2_hostmem_start_address_lo_write; 342 pcid_read_func_t cmic_cmc0_sbusdma_ch2_hostmem_start_address_hi_read; 343 pcid_write_func_t cmic_cmc0_sbusdma_ch2_hostmem_start_address_hi_write; 344 pcid_read_func_t cmic_cmc0_sbusdma_ch2_desc_start_address_lo_read; 345 pcid_write_func_t cmic_cmc0_sbusdma_ch2_desc_start_address_lo_write; 346 pcid_read_func_t cmic_cmc0_sbusdma_ch2_desc_start_address_hi_read; 347 pcid_write_func_t cmic_cmc0_sbusdma_ch2_desc_start_address_hi_write; 348 pcid_read_func_t cmic_cmc0_sbusdma_ch2_status_read; 349 pcid_write_func_t cmic_cmc0_sbusdma_ch2_status_write; 350 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_hostmem_address_lo_read; 351 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_hostmem_address_lo_write; 352 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_hostmem_address_hi_read; 353 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_hostmem_address_hi_write; 354 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_sbus_address_read; 355 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_sbus_address_write; 356 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_desc_address_lo_read; 357 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_desc_address_lo_write; 358 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_desc_address_hi_read; 359 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_desc_address_hi_write; 360 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_request_read; 361 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_request_write; 362 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_count_read; 363 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_count_write; 364 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_read; 365 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_write; 366 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_read; 367 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_write; 368 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_read; 369 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_write; 370 pcid_read_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_opcode_read; 371 pcid_write_func_t cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_opcode_write; 372 pcid_read_func_t cmic_cmc0_sbusdma_ch2_sbusdma_debug_read; 373 pcid_write_func_t cmic_cmc0_sbusdma_ch2_sbusdma_debug_write; 374 pcid_read_func_t cmic_cmc0_sbusdma_ch2_sbusdma_debug_clr_read; 375 pcid_write_func_t cmic_cmc0_sbusdma_ch2_sbusdma_debug_clr_write; 376 pcid_read_func_t cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_address_lo_read; 377 pcid_write_func_t cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_address_lo_write; 378 pcid_read_func_t cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_address_hi_read; 379 pcid_write_func_t cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_address_hi_write; 380 pcid_read_func_t cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_control_read; 381 pcid_write_func_t cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_control_write; 382 pcid_read_func_t cmic_cmc0_sbusdma_ch2_iter_count_read; 383 pcid_write_func_t cmic_cmc0_sbusdma_ch2_iter_count_write; 384 pcid_read_func_t cmic_cmc0_sbusdma_ch2_timer_read; 385 pcid_write_func_t cmic_cmc0_sbusdma_ch2_timer_write; 386 pcid_read_func_t cmic_cmc0_sbusdma_ch2_tm_control_0_read; 387 pcid_write_func_t cmic_cmc0_sbusdma_ch2_tm_control_0_write; 388 pcid_read_func_t cmic_cmc0_sbusdma_ch2_tm_control_1_read; 389 pcid_write_func_t cmic_cmc0_sbusdma_ch2_tm_control_1_write; 390 pcid_read_func_t cmic_cmc0_sbusdma_ch2_tm_control_2_read; 391 pcid_write_func_t cmic_cmc0_sbusdma_ch2_tm_control_2_write; 392 pcid_read_func_t cmic_cmc0_sbusdma_ch3_control_read; 393 pcid_write_func_t cmic_cmc0_sbusdma_ch3_control_write; 394 pcid_read_func_t cmic_cmc0_sbusdma_ch3_request_read; 395 pcid_write_func_t cmic_cmc0_sbusdma_ch3_request_write; 396 pcid_read_func_t cmic_cmc0_sbusdma_ch3_count_read; 397 pcid_write_func_t cmic_cmc0_sbusdma_ch3_count_write; 398 pcid_read_func_t cmic_cmc0_sbusdma_ch3_opcode_read; 399 pcid_write_func_t cmic_cmc0_sbusdma_ch3_opcode_write; 400 pcid_read_func_t cmic_cmc0_sbusdma_ch3_sbus_start_address_read; 401 pcid_write_func_t cmic_cmc0_sbusdma_ch3_sbus_start_address_write; 402 pcid_read_func_t cmic_cmc0_sbusdma_ch3_hostmem_start_address_lo_read; 403 pcid_write_func_t cmic_cmc0_sbusdma_ch3_hostmem_start_address_lo_write; 404 pcid_read_func_t cmic_cmc0_sbusdma_ch3_hostmem_start_address_hi_read; 405 pcid_write_func_t cmic_cmc0_sbusdma_ch3_hostmem_start_address_hi_write; 406 pcid_read_func_t cmic_cmc0_sbusdma_ch3_desc_start_address_lo_read; 407 pcid_write_func_t cmic_cmc0_sbusdma_ch3_desc_start_address_lo_write; 408 pcid_read_func_t cmic_cmc0_sbusdma_ch3_desc_start_address_hi_read; 409 pcid_write_func_t cmic_cmc0_sbusdma_ch3_desc_start_address_hi_write; 410 pcid_read_func_t cmic_cmc0_sbusdma_ch3_status_read; 411 pcid_write_func_t cmic_cmc0_sbusdma_ch3_status_write; 412 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_hostmem_address_lo_read; 413 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_hostmem_address_lo_write; 414 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_hostmem_address_hi_read; 415 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_hostmem_address_hi_write; 416 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_sbus_address_read; 417 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_sbus_address_write; 418 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_desc_address_lo_read; 419 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_desc_address_lo_write; 420 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_desc_address_hi_read; 421 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_desc_address_hi_write; 422 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_request_read; 423 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_request_write; 424 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_count_read; 425 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_count_write; 426 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_read; 427 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_write; 428 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_read; 429 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_write; 430 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_read; 431 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_write; 432 pcid_read_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_opcode_read; 433 pcid_write_func_t cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_opcode_write; 434 pcid_read_func_t cmic_cmc0_sbusdma_ch3_sbusdma_debug_read; 435 pcid_write_func_t cmic_cmc0_sbusdma_ch3_sbusdma_debug_write; 436 pcid_read_func_t cmic_cmc0_sbusdma_ch3_sbusdma_debug_clr_read; 437 pcid_write_func_t cmic_cmc0_sbusdma_ch3_sbusdma_debug_clr_write; 438 pcid_read_func_t cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_address_lo_read; 439 pcid_write_func_t cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_address_lo_write; 440 pcid_read_func_t cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_address_hi_read; 441 pcid_write_func_t cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_address_hi_write; 442 pcid_read_func_t cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_control_read; 443 pcid_write_func_t cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_control_write; 444 pcid_read_func_t cmic_cmc0_sbusdma_ch3_iter_count_read; 445 pcid_write_func_t cmic_cmc0_sbusdma_ch3_iter_count_write; 446 pcid_read_func_t cmic_cmc0_sbusdma_ch3_timer_read; 447 pcid_write_func_t cmic_cmc0_sbusdma_ch3_timer_write; 448 pcid_read_func_t cmic_cmc0_sbusdma_ch3_tm_control_0_read; 449 pcid_write_func_t cmic_cmc0_sbusdma_ch3_tm_control_0_write; 450 pcid_read_func_t cmic_cmc0_sbusdma_ch3_tm_control_1_read; 451 pcid_write_func_t cmic_cmc0_sbusdma_ch3_tm_control_1_write; 452 pcid_read_func_t cmic_cmc0_sbusdma_ch3_tm_control_2_read; 453 pcid_write_func_t cmic_cmc0_sbusdma_ch3_tm_control_2_write; 454 pcid_read_func_t cmic_cmc1_shared_config_read; 455 pcid_write_func_t cmic_cmc1_shared_config_write; 456 pcid_read_func_t cmic_cmc1_sbusdma_ch0_control_read; 457 pcid_write_func_t cmic_cmc1_sbusdma_ch0_control_write; 458 pcid_read_func_t cmic_cmc1_sbusdma_ch0_request_read; 459 pcid_write_func_t cmic_cmc1_sbusdma_ch0_request_write; 460 pcid_read_func_t cmic_cmc1_sbusdma_ch0_count_read; 461 pcid_write_func_t cmic_cmc1_sbusdma_ch0_count_write; 462 pcid_read_func_t cmic_cmc1_sbusdma_ch0_opcode_read; 463 pcid_write_func_t cmic_cmc1_sbusdma_ch0_opcode_write; 464 pcid_read_func_t cmic_cmc1_sbusdma_ch0_sbus_start_address_read; 465 pcid_write_func_t cmic_cmc1_sbusdma_ch0_sbus_start_address_write; 466 pcid_read_func_t cmic_cmc1_sbusdma_ch0_hostmem_start_address_lo_read; 467 pcid_write_func_t cmic_cmc1_sbusdma_ch0_hostmem_start_address_lo_write; 468 pcid_read_func_t cmic_cmc1_sbusdma_ch0_hostmem_start_address_hi_read; 469 pcid_write_func_t cmic_cmc1_sbusdma_ch0_hostmem_start_address_hi_write; 470 pcid_read_func_t cmic_cmc1_sbusdma_ch0_desc_start_address_lo_read; 471 pcid_write_func_t cmic_cmc1_sbusdma_ch0_desc_start_address_lo_write; 472 pcid_read_func_t cmic_cmc1_sbusdma_ch0_desc_start_address_hi_read; 473 pcid_write_func_t cmic_cmc1_sbusdma_ch0_desc_start_address_hi_write; 474 pcid_read_func_t cmic_cmc1_sbusdma_ch0_status_read; 475 pcid_write_func_t cmic_cmc1_sbusdma_ch0_status_write; 476 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_hostmem_address_lo_read; 477 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_hostmem_address_lo_write; 478 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_hostmem_address_hi_read; 479 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_hostmem_address_hi_write; 480 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_sbus_address_read; 481 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_sbus_address_write; 482 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_desc_address_lo_read; 483 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_desc_address_lo_write; 484 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_desc_address_hi_read; 485 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_desc_address_hi_write; 486 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_request_read; 487 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_request_write; 488 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_count_read; 489 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_count_write; 490 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_read; 491 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_write; 492 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_read; 493 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_write; 494 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_read; 495 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_write; 496 pcid_read_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_opcode_read; 497 pcid_write_func_t cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_opcode_write; 498 pcid_read_func_t cmic_cmc1_sbusdma_ch0_sbusdma_debug_read; 499 pcid_write_func_t cmic_cmc1_sbusdma_ch0_sbusdma_debug_write; 500 pcid_read_func_t cmic_cmc1_sbusdma_ch0_sbusdma_debug_clr_read; 501 pcid_write_func_t cmic_cmc1_sbusdma_ch0_sbusdma_debug_clr_write; 502 pcid_read_func_t cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_address_lo_read; 503 pcid_write_func_t cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_address_lo_write; 504 pcid_read_func_t cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_address_hi_read; 505 pcid_write_func_t cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_address_hi_write; 506 pcid_read_func_t cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_control_read; 507 pcid_write_func_t cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_control_write; 508 pcid_read_func_t cmic_cmc1_sbusdma_ch0_iter_count_read; 509 pcid_write_func_t cmic_cmc1_sbusdma_ch0_iter_count_write; 510 pcid_read_func_t cmic_cmc1_sbusdma_ch0_timer_read; 511 pcid_write_func_t cmic_cmc1_sbusdma_ch0_timer_write; 512 pcid_read_func_t cmic_cmc1_sbusdma_ch0_tm_control_0_read; 513 pcid_write_func_t cmic_cmc1_sbusdma_ch0_tm_control_0_write; 514 pcid_read_func_t cmic_cmc1_sbusdma_ch0_tm_control_1_read; 515 pcid_write_func_t cmic_cmc1_sbusdma_ch0_tm_control_1_write; 516 pcid_read_func_t cmic_cmc1_sbusdma_ch0_tm_control_2_read; 517 pcid_write_func_t cmic_cmc1_sbusdma_ch0_tm_control_2_write; 518 pcid_read_func_t cmic_cmc1_sbusdma_ch1_control_read; 519 pcid_write_func_t cmic_cmc1_sbusdma_ch1_control_write; 520 pcid_read_func_t cmic_cmc1_sbusdma_ch1_request_read; 521 pcid_write_func_t cmic_cmc1_sbusdma_ch1_request_write; 522 pcid_read_func_t cmic_cmc1_sbusdma_ch1_count_read; 523 pcid_write_func_t cmic_cmc1_sbusdma_ch1_count_write; 524 pcid_read_func_t cmic_cmc1_sbusdma_ch1_opcode_read; 525 pcid_write_func_t cmic_cmc1_sbusdma_ch1_opcode_write; 526 pcid_read_func_t cmic_cmc1_sbusdma_ch1_sbus_start_address_read; 527 pcid_write_func_t cmic_cmc1_sbusdma_ch1_sbus_start_address_write; 528 pcid_read_func_t cmic_cmc1_sbusdma_ch1_hostmem_start_address_lo_read; 529 pcid_write_func_t cmic_cmc1_sbusdma_ch1_hostmem_start_address_lo_write; 530 pcid_read_func_t cmic_cmc1_sbusdma_ch1_hostmem_start_address_hi_read; 531 pcid_write_func_t cmic_cmc1_sbusdma_ch1_hostmem_start_address_hi_write; 532 pcid_read_func_t cmic_cmc1_sbusdma_ch1_desc_start_address_lo_read; 533 pcid_write_func_t cmic_cmc1_sbusdma_ch1_desc_start_address_lo_write; 534 pcid_read_func_t cmic_cmc1_sbusdma_ch1_desc_start_address_hi_read; 535 pcid_write_func_t cmic_cmc1_sbusdma_ch1_desc_start_address_hi_write; 536 pcid_read_func_t cmic_cmc1_sbusdma_ch1_status_read; 537 pcid_write_func_t cmic_cmc1_sbusdma_ch1_status_write; 538 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_hostmem_address_lo_read; 539 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_hostmem_address_lo_write; 540 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_hostmem_address_hi_read; 541 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_hostmem_address_hi_write; 542 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_sbus_address_read; 543 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_sbus_address_write; 544 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_desc_address_lo_read; 545 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_desc_address_lo_write; 546 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_desc_address_hi_read; 547 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_desc_address_hi_write; 548 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_request_read; 549 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_request_write; 550 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_count_read; 551 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_count_write; 552 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_read; 553 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_write; 554 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_read; 555 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_write; 556 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_read; 557 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_write; 558 pcid_read_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_opcode_read; 559 pcid_write_func_t cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_opcode_write; 560 pcid_read_func_t cmic_cmc1_sbusdma_ch1_sbusdma_debug_read; 561 pcid_write_func_t cmic_cmc1_sbusdma_ch1_sbusdma_debug_write; 562 pcid_read_func_t cmic_cmc1_sbusdma_ch1_sbusdma_debug_clr_read; 563 pcid_write_func_t cmic_cmc1_sbusdma_ch1_sbusdma_debug_clr_write; 564 pcid_read_func_t cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_address_lo_read; 565 pcid_write_func_t cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_address_lo_write; 566 pcid_read_func_t cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_address_hi_read; 567 pcid_write_func_t cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_address_hi_write; 568 pcid_read_func_t cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_control_read; 569 pcid_write_func_t cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_control_write; 570 pcid_read_func_t cmic_cmc1_sbusdma_ch1_iter_count_read; 571 pcid_write_func_t cmic_cmc1_sbusdma_ch1_iter_count_write; 572 pcid_read_func_t cmic_cmc1_sbusdma_ch1_timer_read; 573 pcid_write_func_t cmic_cmc1_sbusdma_ch1_timer_write; 574 pcid_read_func_t cmic_cmc1_sbusdma_ch1_tm_control_0_read; 575 pcid_write_func_t cmic_cmc1_sbusdma_ch1_tm_control_0_write; 576 pcid_read_func_t cmic_cmc1_sbusdma_ch1_tm_control_1_read; 577 pcid_write_func_t cmic_cmc1_sbusdma_ch1_tm_control_1_write; 578 pcid_read_func_t cmic_cmc1_sbusdma_ch1_tm_control_2_read; 579 pcid_write_func_t cmic_cmc1_sbusdma_ch1_tm_control_2_write; 580 pcid_read_func_t cmic_cmc1_sbusdma_ch2_control_read; 581 pcid_write_func_t cmic_cmc1_sbusdma_ch2_control_write; 582 pcid_read_func_t cmic_cmc1_sbusdma_ch2_request_read; 583 pcid_write_func_t cmic_cmc1_sbusdma_ch2_request_write; 584 pcid_read_func_t cmic_cmc1_sbusdma_ch2_count_read; 585 pcid_write_func_t cmic_cmc1_sbusdma_ch2_count_write; 586 pcid_read_func_t cmic_cmc1_sbusdma_ch2_opcode_read; 587 pcid_write_func_t cmic_cmc1_sbusdma_ch2_opcode_write; 588 pcid_read_func_t cmic_cmc1_sbusdma_ch2_sbus_start_address_read; 589 pcid_write_func_t cmic_cmc1_sbusdma_ch2_sbus_start_address_write; 590 pcid_read_func_t cmic_cmc1_sbusdma_ch2_hostmem_start_address_lo_read; 591 pcid_write_func_t cmic_cmc1_sbusdma_ch2_hostmem_start_address_lo_write; 592 pcid_read_func_t cmic_cmc1_sbusdma_ch2_hostmem_start_address_hi_read; 593 pcid_write_func_t cmic_cmc1_sbusdma_ch2_hostmem_start_address_hi_write; 594 pcid_read_func_t cmic_cmc1_sbusdma_ch2_desc_start_address_lo_read; 595 pcid_write_func_t cmic_cmc1_sbusdma_ch2_desc_start_address_lo_write; 596 pcid_read_func_t cmic_cmc1_sbusdma_ch2_desc_start_address_hi_read; 597 pcid_write_func_t cmic_cmc1_sbusdma_ch2_desc_start_address_hi_write; 598 pcid_read_func_t cmic_cmc1_sbusdma_ch2_status_read; 599 pcid_write_func_t cmic_cmc1_sbusdma_ch2_status_write; 600 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_hostmem_address_lo_read; 601 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_hostmem_address_lo_write; 602 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_hostmem_address_hi_read; 603 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_hostmem_address_hi_write; 604 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_sbus_address_read; 605 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_sbus_address_write; 606 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_desc_address_lo_read; 607 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_desc_address_lo_write; 608 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_desc_address_hi_read; 609 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_desc_address_hi_write; 610 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_request_read; 611 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_request_write; 612 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_count_read; 613 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_count_write; 614 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_read; 615 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_write; 616 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_read; 617 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_write; 618 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_read; 619 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_write; 620 pcid_read_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_opcode_read; 621 pcid_write_func_t cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_opcode_write; 622 pcid_read_func_t cmic_cmc1_sbusdma_ch2_sbusdma_debug_read; 623 pcid_write_func_t cmic_cmc1_sbusdma_ch2_sbusdma_debug_write; 624 pcid_read_func_t cmic_cmc1_sbusdma_ch2_sbusdma_debug_clr_read; 625 pcid_write_func_t cmic_cmc1_sbusdma_ch2_sbusdma_debug_clr_write; 626 pcid_read_func_t cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_address_lo_read; 627 pcid_write_func_t cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_address_lo_write; 628 pcid_read_func_t cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_address_hi_read; 629 pcid_write_func_t cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_address_hi_write; 630 pcid_read_func_t cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_control_read; 631 pcid_write_func_t cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_control_write; 632 pcid_read_func_t cmic_cmc1_sbusdma_ch2_iter_count_read; 633 pcid_write_func_t cmic_cmc1_sbusdma_ch2_iter_count_write; 634 pcid_read_func_t cmic_cmc1_sbusdma_ch2_timer_read; 635 pcid_write_func_t cmic_cmc1_sbusdma_ch2_timer_write; 636 pcid_read_func_t cmic_cmc1_sbusdma_ch2_tm_control_0_read; 637 pcid_write_func_t cmic_cmc1_sbusdma_ch2_tm_control_0_write; 638 pcid_read_func_t cmic_cmc1_sbusdma_ch2_tm_control_1_read; 639 pcid_write_func_t cmic_cmc1_sbusdma_ch2_tm_control_1_write; 640 pcid_read_func_t cmic_cmc1_sbusdma_ch2_tm_control_2_read; 641 pcid_write_func_t cmic_cmc1_sbusdma_ch2_tm_control_2_write; 642 pcid_read_func_t cmic_cmc1_sbusdma_ch3_control_read; 643 pcid_write_func_t cmic_cmc1_sbusdma_ch3_control_write; 644 pcid_read_func_t cmic_cmc1_sbusdma_ch3_request_read; 645 pcid_write_func_t cmic_cmc1_sbusdma_ch3_request_write; 646 pcid_read_func_t cmic_cmc1_sbusdma_ch3_count_read; 647 pcid_write_func_t cmic_cmc1_sbusdma_ch3_count_write; 648 pcid_read_func_t cmic_cmc1_sbusdma_ch3_opcode_read; 649 pcid_write_func_t cmic_cmc1_sbusdma_ch3_opcode_write; 650 pcid_read_func_t cmic_cmc1_sbusdma_ch3_sbus_start_address_read; 651 pcid_write_func_t cmic_cmc1_sbusdma_ch3_sbus_start_address_write; 652 pcid_read_func_t cmic_cmc1_sbusdma_ch3_hostmem_start_address_lo_read; 653 pcid_write_func_t cmic_cmc1_sbusdma_ch3_hostmem_start_address_lo_write; 654 pcid_read_func_t cmic_cmc1_sbusdma_ch3_hostmem_start_address_hi_read; 655 pcid_write_func_t cmic_cmc1_sbusdma_ch3_hostmem_start_address_hi_write; 656 pcid_read_func_t cmic_cmc1_sbusdma_ch3_desc_start_address_lo_read; 657 pcid_write_func_t cmic_cmc1_sbusdma_ch3_desc_start_address_lo_write; 658 pcid_read_func_t cmic_cmc1_sbusdma_ch3_desc_start_address_hi_read; 659 pcid_write_func_t cmic_cmc1_sbusdma_ch3_desc_start_address_hi_write; 660 pcid_read_func_t cmic_cmc1_sbusdma_ch3_status_read; 661 pcid_write_func_t cmic_cmc1_sbusdma_ch3_status_write; 662 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_hostmem_address_lo_read; 663 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_hostmem_address_lo_write; 664 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_hostmem_address_hi_read; 665 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_hostmem_address_hi_write; 666 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_sbus_address_read; 667 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_sbus_address_write; 668 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_desc_address_lo_read; 669 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_desc_address_lo_write; 670 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_desc_address_hi_read; 671 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_desc_address_hi_write; 672 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_request_read; 673 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_request_write; 674 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_count_read; 675 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_count_write; 676 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_read; 677 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_write; 678 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_read; 679 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_write; 680 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_read; 681 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_write; 682 pcid_read_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_opcode_read; 683 pcid_write_func_t cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_opcode_write; 684 pcid_read_func_t cmic_cmc1_sbusdma_ch3_sbusdma_debug_read; 685 pcid_write_func_t cmic_cmc1_sbusdma_ch3_sbusdma_debug_write; 686 pcid_read_func_t cmic_cmc1_sbusdma_ch3_sbusdma_debug_clr_read; 687 pcid_write_func_t cmic_cmc1_sbusdma_ch3_sbusdma_debug_clr_write; 688 pcid_read_func_t cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_address_lo_read; 689 pcid_write_func_t cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_address_lo_write; 690 pcid_read_func_t cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_address_hi_read; 691 pcid_write_func_t cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_address_hi_write; 692 pcid_read_func_t cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_control_read; 693 pcid_write_func_t cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_control_write; 694 pcid_read_func_t cmic_cmc1_sbusdma_ch3_iter_count_read; 695 pcid_write_func_t cmic_cmc1_sbusdma_ch3_iter_count_write; 696 pcid_read_func_t cmic_cmc1_sbusdma_ch3_timer_read; 697 pcid_write_func_t cmic_cmc1_sbusdma_ch3_timer_write; 698 pcid_read_func_t cmic_cmc1_sbusdma_ch3_tm_control_0_read; 699 pcid_write_func_t cmic_cmc1_sbusdma_ch3_tm_control_0_write; 700 pcid_read_func_t cmic_cmc1_sbusdma_ch3_tm_control_1_read; 701 pcid_write_func_t cmic_cmc1_sbusdma_ch3_tm_control_1_write; 702 pcid_read_func_t cmic_cmc1_sbusdma_ch3_tm_control_2_read; 703 pcid_write_func_t cmic_cmc1_sbusdma_ch3_tm_control_2_write; 704 705 706 #endif /* _SBUS_DMA_H_ */ 707 708