cmicx_sim_sbus_dma.c (107940B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 8 9 /* 10 * cmicx_sim_sbus_dma.c 11 * 12 * contains implementation of sbus dma register access functions, as well as helper functions, update functions, and init functions for sbus dma. 13 */ 14 15 16 /* includes */ 17 #include <string.h> 18 #ifndef CMICX_STANDALONE_SIM 19 #include <../systems/sim/pcid/cmicx_sim.h> 20 #include <../systems/sim/pcid/cmicx_sim_pcid.h> 21 #include <../systems/sim/pcid/cmicx_sim_schan.h> 22 #include <../systems/sim/pcid/cmicx_sim_sbus_dma.h> 23 #else 24 #include "cmicx_sim.h" 25 #include "cmicx_sim_pcid.h" 26 #include "cmicx_sim_schan.h" 27 #include "cmicx_sim_sbus_dma.h" 28 #endif 29 30 /* external cmicx global structure pointer */ 31 extern cmicx_t *cmicx; 32 33 34 /**********************************************************************/ 35 /* sbus dma support functions. update, init, start access, abort, etc */ 36 /**********************************************************************/ 37 38 39 /* init function */ 40 bool cmicx_sbus_dma_init(cmicx_sbus_dma_data_t *sbus_dma_data,char *id_string) 41 { 42 /* if the given id string is too long, log an error and quit */ 43 if ((strlen(id_string)+1)>CMIC_SBUS_DMA_ID_STRING_LENGTH) { 44 cmicx_error("ERROR: given id string \""); 45 cmicx_error(id_string); 46 cmicx_error("\" for sbus dma unit is too long.\n"); 47 return false; 48 } 49 50 /* copy the id string to the storage for the schan */ 51 strcpy(sbus_dma_data->id_string,id_string); 52 53 /* control register values */ 54 sbus_dma_data->desc_prefetch_enable = false; 55 sbus_dma_data->endianness = false; 56 sbus_dma_data->mode = CMIC_SBUS_DMA_REGISTER_MODE; 57 sbus_dma_data->start = false; 58 sbus_dma_data->command_is_write = false; 59 60 /* internal control values */ 61 sbus_dma_data->last_desc = false; 62 sbus_dma_data->timer_running = false; 63 sbus_dma_data->access_running = false; 64 sbus_dma_data->timer_countdown = 0; 65 sbus_dma_data->sequence_pending = false; 66 sbus_dma_data->sbus_command_countdown = 0; 67 sbus_dma_data->pend_clocks_countdown = 0; 68 69 /* request register values */ 70 sbus_dma_data->decrement = false; 71 sbus_dma_data->req_single = false; 72 sbus_dma_data->incr_noadd = false; 73 sbus_dma_data->incr_shift = 0; 74 sbus_dma_data->pend_clocks = 0; 75 sbus_dma_data->dma_wr_to_nullspace = false; 76 sbus_dma_data->wordswap_in_64bit_sbus_data = false; 77 sbus_dma_data->memwr_endianness = 0; 78 sbus_dma_data->memrd_endianness = 0; 79 sbus_dma_data->req_words = 0; 80 sbus_dma_data->resp_words = 0; 81 82 /* count register values */ 83 sbus_dma_data->cur_count = 0; 84 85 /* opcode register value */ 86 sbus_dma_data->opcode = 0; 87 88 /* start register address value */ 89 sbus_dma_data->cur_sbus_address = 0; 90 91 /* hostmem register address value */ 92 sbus_dma_data->cur_hostmem_address = 0; 93 94 /* hostmem descriptor start address value */ 95 sbus_dma_data->cur_desc_address = 0; 96 97 /* status bits */ 98 sbus_dma_data->ecc_2bit_check_fail = false; 99 sbus_dma_data->sbusdma_active = false; 100 sbus_dma_data->active = false; 101 sbus_dma_data->descrd_error = false; 102 sbus_dma_data->sbusack_timeout = false; 103 sbus_dma_data->sbusack_error = false; 104 sbus_dma_data->sbusack_nack = false; 105 sbus_dma_data->sbusack_wrong_opcode = false; 106 sbus_dma_data->sbusack_wrong_beatcount = false; 107 sbus_dma_data->ser_check_fail = false; 108 sbus_dma_data->hostmemrd_error = false; 109 sbus_dma_data->hostmemwr_error = false; 110 sbus_dma_data->error = false; 111 sbus_dma_data->done = false; 112 113 /* debug register values */ 114 sbus_dma_data->desc_done = false; 115 116 /* iter count register value */ 117 sbus_dma_data->iter_count = 0; 118 119 /* timer register value */ 120 sbus_dma_data->timer = 0; 121 122 /* current values for things (fed to cur registers) */ 123 sbus_dma_data->cur_sbusdma_config_request = 0; 124 sbus_dma_data->cur_sbusdma_config_count = 0; 125 sbus_dma_data->cur_sbusdma_config_opcode = 0; 126 sbus_dma_data->cur_sbusdma_config_sbus_start_address = 0; 127 sbus_dma_data->cur_sbusdma_config_hostmem_start_address = 0; 128 sbus_dma_data->cur_sbusdma_config_desc_start_address = 0; 129 130 /* per cmc sbusdma config values */ 131 sbus_dma_data->enable_sbusdma_flow_control = false; 132 133 /* successful initialization complete */ 134 cmicx_log("successfully init'd \""); 135 cmicx_log(sbus_dma_data->id_string); 136 cmicx_log("\"."); 137 cmicx_log_newline(); 138 return true; 139 140 } 141 142 143 /* update function for sbus dma */ 144 /* 145 * steps for updating an sbus dma: 146 * 1) if we have no access running and we are in timer-based mode, then we may need to start a new access. perform a timer countdown and start this access 147 * once the timer reaches 0. if we already have an access running, skip to step 2. 148 * 2) once we have an access running, if we are in descriptor mode and not currently running an sbus command sequence, make a memory request for a descriptor 149 * if we need to (and wait until that request comes back). otherwise, skip to step 3. 150 * 3) start the internal sbus timer (counter) process, to start processing the next (or first) sbus command of a sequence. 151 * 4) decrement the counter until the count expires, at which point execute the sbus command, using the current register data. if descriptor mode was enabled, 152 * the proper data will have been loaded into these registers already. 153 * 5) intiate the pend_clocks counter to begin the core clock delay between subsequent sbus dma commands. 154 * 6) count down the pend_clocks counter until it expires, at which point repeat this entire process, starting with step 1 if we have ended an sbus dma access, 155 * step 2 if we have only ended an sbus dma sequence, or step 3 if we haven't ended either of these. 156 */ 157 bool cmicx_sbus_dma_update(pcid_info_t *pcid_info, cmicx_sbus_dma_data_t *sbus_dma_data) 158 { 159 160 /* variables */ 161 reg_t command[CMIC_SCHAN_NUM_MESSAGE_REGS]; 162 int num_words; 163 reg_t ack_command[CMIC_SCHAN_NUM_MESSAGE_REGS]; 164 int ack_num_words; 165 bool append = false; 166 bool skip = false; 167 bool jump = false; 168 /* int descriptors_remaining = 0; */ 169 reg_t mem[CMIC_SBUS_DMA_WORDS_PER_DESCRIPTOR]; /* return memory from pcid (used for desc requests) */ 170 addr_t temp_address; 171 reg_t temp; 172 int i; 173 174 /* print log messages for this schan */ 175 cmicx_log_level_set(0); 176 cmicx_log("updating \""); 177 cmicx_log(sbus_dma_data->id_string); 178 cmicx_log("\"... "); 179 cmicx_log_level_set(3); 180 181 182 /* if we don't have an access running, then check if we are in timer-based mode. if we are, then perform a countdown to initiate an access. */ 183 /* if we are not in timer-based bode, then we just bail out of the function. */ 184 if (sbus_dma_data->access_running==false) { 185 186 if (sbus_dma_data->timer_running==true) { 187 188 /* countdown to next access start */ 189 if (sbus_dma_data->timer_countdown!=0) { 190 sbus_dma_data->timer_countdown--; 191 } 192 if (sbus_dma_data->timer_countdown==0) { 193 194 /* we have reached the end of the countdown, so now we can start a new access. */ 195 /* if in register mode, restore the original register settings, and start an access. */ 196 if (sbus_dma_data->mode==CMIC_SBUS_DMA_REGISTER_MODE) { 197 cmic_sbusdma_request_write( sbus_dma_data->cur_sbusdma_config_request, sbus_dma_data); 198 cmic_sbusdma_count_write( sbus_dma_data->cur_sbusdma_config_count, sbus_dma_data); 199 cmic_sbusdma_opcode_write( sbus_dma_data->cur_sbusdma_config_opcode, sbus_dma_data); 200 cmic_sbusdma_sbus_start_address_write( sbus_dma_data->cur_sbusdma_config_sbus_start_address, sbus_dma_data); 201 cmic_sbusdma_hostmem_start_address_lo_write(UINT64_LOWER32_REFERENCE(sbus_dma_data->cur_sbusdma_config_hostmem_start_address),sbus_dma_data); 202 cmic_sbusdma_hostmem_start_address_hi_write(UINT64_UPPER32_REFERENCE(sbus_dma_data->cur_sbusdma_config_hostmem_start_address),sbus_dma_data); 203 if (cmic_sbus_dma_access_start(sbus_dma_data)==false) { 204 return false; 205 } 206 } 207 208 /* if in descriptor mode, restore the original descriptor address, and start an access. */ 209 else { 210 cmic_sbusdma_desc_start_address_lo_write(UINT64_LOWER32_REFERENCE(sbus_dma_data->cur_sbusdma_config_desc_start_address),sbus_dma_data); 211 cmic_sbusdma_desc_start_address_hi_write(UINT64_UPPER32_REFERENCE(sbus_dma_data->cur_sbusdma_config_desc_start_address),sbus_dma_data); 212 if (cmic_sbus_dma_access_start(sbus_dma_data)==false) { 213 return false; 214 } 215 } 216 217 } 218 219 } 220 221 } 222 223 /* if we have an access running, then handle descriptor requesting, counter setup/decrement and command completion if necessary. */ 224 else { 225 226 227 /* if we are in descriptor mode and we do not have an sbus dma sequence pending, then */ 228 /* we need to initiate a memory read at this point, to get the new descriptors. */ 229 if ((sbus_dma_data->mode==CMIC_SBUS_DMA_DESCRIPTOR_MODE) && (sbus_dma_data->sequence_pending==false)) { 230 231 /* we need to loop the descriptor request, because we may need to skip or jump to other descriptors, necessitating a re-request */ 232 do { 233 234 /* make the memory read over the pcid to get the descriptor words */ 235 cmicx_pcid_mem_read(pcid_info,sbus_dma_data->cur_desc_address,(void *)mem,CMIC_SBUS_DMA_WORDS_PER_DESCRIPTOR*CMICX_BYTES_PER_WORD); 236 cmicx_log("descriptor read from memory, words: "); 237 for (i=0; i<CMIC_SBUS_DMA_WORDS_PER_DESCRIPTOR; i++) { 238 cmicx_log_hex(mem[i]); 239 cmicx_log(", "); 240 } 241 cmicx_log_newline(); 242 243 /* parse the special descriptor control word */ 244 sbus_dma_data->last_desc = REG_BIT_GET( mem[0],CMIC_SBUSDMA_CONTROL_DESC_LAST_BIT); 245 append = REG_BIT_GET( mem[0],CMIC_SBUSDMA_CONTROL_DESC_APPEND_BIT); 246 skip = REG_BIT_GET( mem[0],CMIC_SBUSDMA_CONTROL_DESC_SKIP_BIT); 247 jump = REG_BIT_GET( mem[0],CMIC_SBUSDMA_CONTROL_DESC_JUMP_BIT); 248 /* descriptors_remaining = REG_FIELD_GET(mem[0],CMIC_SBUSDMA_CONTROL_DESC_DESCRIPTORS_REMAINING_MSB,CMIC_SBUSDMA_CONTROL_DESC_DESCRIPTORS_REMAINING_LSB); */ 249 /* ^^^ this prefetch parameter is not actually used at the moment, but may be used in the future */ 250 251 /* load all the descriptors into the appropriate config registers */ 252 /* use the existing PCID reg write helper functions to save some code */ 253 /* if we are in little endian, then swap the descriptors' endianness */ 254 if (sbus_dma_data->endianness) { 255 cmic_sbusdma_request_write( cmicx_reverse_word_endianness(mem[1]),sbus_dma_data); 256 cmic_sbusdma_count_write( cmicx_reverse_word_endianness(mem[2]),sbus_dma_data); 257 cmic_sbusdma_opcode_write( cmicx_reverse_word_endianness(mem[3]),sbus_dma_data); 258 cmic_sbusdma_sbus_start_address_write( cmicx_reverse_word_endianness(mem[4]),sbus_dma_data); 259 if (append==false) { 260 cmic_sbusdma_hostmem_start_address_lo_write(cmicx_reverse_word_endianness(mem[5]),sbus_dma_data); 261 cmic_sbusdma_hostmem_start_address_hi_write(cmicx_reverse_word_endianness(mem[6]),sbus_dma_data); 262 } 263 } 264 else { 265 cmic_sbusdma_request_write( mem[1],sbus_dma_data); 266 cmic_sbusdma_count_write( mem[2],sbus_dma_data); 267 cmic_sbusdma_opcode_write( mem[3],sbus_dma_data); 268 cmic_sbusdma_sbus_start_address_write( mem[4],sbus_dma_data); 269 if (append==false) { 270 cmic_sbusdma_hostmem_start_address_lo_write(mem[5],sbus_dma_data); 271 cmic_sbusdma_hostmem_start_address_hi_write(mem[6],sbus_dma_data); 272 } 273 } 274 275 /* update the descriptor address appropriately, including a skip/jump if needed. */ 276 if (sbus_dma_data->last_desc==false) { 277 if (jump==true) { 278 sbus_dma_data->cur_desc_address = sbus_dma_data->cur_hostmem_address; 279 } 280 if (skip==true) { 281 sbus_dma_data->cur_desc_address += (CMIC_SBUS_DMA_BYTES_PER_WORD*CMIC_SBUS_DMA_WORDS_PER_DESCRIPTOR); /* bytes per word (4) times number of descriptors (8) */ 282 } 283 } 284 285 } 286 while (((skip==true) || (jump==true)) && (sbus_dma_data->last_desc==false)); 287 288 /* at this point we definitely have a valid descriptor, so mark the sbusdma_active bit to indicate that we have started a new descriptor. */ 289 sbus_dma_data->sbusdma_active = true; 290 291 } 292 293 294 /* if we are not in descriptor mode, then we need to pretend that this is the last descriptor */ 295 /* in a descriptor chain, so that the sbus command handling code can act appropriately */ 296 if (sbus_dma_data->mode==CMIC_SBUS_DMA_REGISTER_MODE) { 297 sbus_dma_data->last_desc = true; 298 } 299 300 301 /* at this point, we definitely have valid data in the registers - we've either loaded a descriptor, or we're just using */ 302 /* the already existing written register data. thus, we can start sending sbus commands, if we haven't already. */ 303 /* if we are not currently sending anything, then start a new command, and set the sbus dma sequence flag if we need to. */ 304 if ((sbus_dma_data->sbus_command_countdown==0) && (sbus_dma_data->pend_clocks_countdown==0)) { 305 306 /* if we are starting a sequence, then we need to make sure that we have flagged that we are pending an sbus dma sequence now */ 307 if (sbus_dma_data->sequence_pending==false) { 308 sbus_dma_data->sequence_pending = true; 309 } 310 311 /* begin a new sbus command access if possible, based on the sbus command (first word/"opcode") */ 312 if (cmic_schan_sbus_command_start(sbus_dma_data->opcode,&sbus_dma_data->command_is_write)==true) { 313 314 /* set variables for successfully beginning sbus command, and print sbus-dma-specific log messages */ 315 sbus_dma_data->sbus_command_countdown = CMIC_SBUS_DMA_ACCESS_COUNTDOWN_VALUE; 316 sbus_dma_data->pend_clocks_countdown = sbus_dma_data->pend_clocks/50; 317 /* add scaling factor here ^^^, because 318 simulating one extra update for every 319 clock tick is excessive. */ 320 cmicx_log("command was part of sbus dma sequence on \""); 321 cmicx_log(sbus_dma_data->id_string); 322 cmicx_log("\". num of mem/data words with command: "); 323 cmicx_log_int(sbus_dma_data->req_words); 324 cmicx_log(". sbus address: "); 325 cmicx_log_addr(sbus_dma_data->cur_sbus_address); 326 cmicx_log_newline(); 327 328 } 329 else { 330 cmicx_log("ERROR: could not successfully start sbus command for sbus dma sequence.\n"); 331 return false; 332 } 333 334 } 335 336 337 /* at this point we are just updating sbus commands that we have pending. decrement the command countdown if we can, */ 338 /* until it reaches 0. once it reaches 0, then we can finish an sbus command (or do the pending clocks countdown) */ 339 if (sbus_dma_data->sbus_command_countdown!=0) { 340 sbus_dma_data->sbus_command_countdown--; 341 } 342 if (sbus_dma_data->sbus_command_countdown==0) { 343 344 /* if the pending clocks countdown hasn't reached 0 yet, then decrement it (until it eventually reaches zero). */ 345 /* once the pending clocks countdown reaches zero, then we can complete the sbus command. */ 346 if (sbus_dma_data->pend_clocks_countdown!=0) { 347 sbus_dma_data->pend_clocks_countdown--; 348 } 349 if (sbus_dma_data->pend_clocks_countdown==0) { 350 351 /* prepare for completing the sbus command. if we have a write command, we need to pull data from memory. the amount to pull is specified by */ 352 /* req_words, and should match the value given in the sbus command opcode word. */ 353 temp_address = sbus_dma_data->cur_hostmem_address; 354 command[0] = sbus_dma_data->opcode; 355 command[1] = sbus_dma_data->cur_sbus_address; 356 if (sbus_dma_data->command_is_write==true) { 357 if (sbus_dma_data->req_words!=(CMIC_SCHAN_COMMAND_STRIP_DLEN(sbus_dma_data->opcode)/CMICX_BYTES_PER_WORD)) { 358 cmicx_log("ERROR: req_words supplied on sbus dma \""); 359 cmicx_log(sbus_dma_data->id_string); 360 cmicx_log("\" is not congruent with dlen value in opcode supplied. req_words: "); 361 cmicx_log_int(sbus_dma_data->req_words); 362 cmicx_log(" dlen value: "); 363 cmicx_log_int(CMIC_SCHAN_COMMAND_STRIP_DLEN(sbus_dma_data->opcode)/CMICX_BYTES_PER_WORD); 364 cmicx_log(" sbus opcode: "); 365 cmicx_log_reg(sbus_dma_data->opcode); 366 cmicx_log_newline(); 367 return false; 368 } 369 cmicx_pcid_mem_read(pcid_info,temp_address,(void *)&(command[2]),(sbus_dma_data->req_words*CMICX_BYTES_PER_WORD)); 370 temp_address += (sbus_dma_data->req_words*CMICX_BYTES_PER_WORD); 371 } 372 373 /* try to complete the sbus command if we can, since we have already loaded the command opcode word, an address, and any data words to the command[] memory. */ 374 if (cmic_schan_sbus_command_complete(pcid_info, command,ack_command,((sbus_dma_data->command_is_write==false) ? sbus_dma_data->resp_words : 0),&num_words)==true) { 375 376 if (sbus_dma_data->command_is_write==false) { 377 378 /* check that the expected number of response data words matches the actual number from the ack (otherwise we have an error). */ 379 ack_num_words = (CMIC_SCHAN_COMMAND_STRIP_DLEN(ack_command[0])/CMICX_BYTES_PER_WORD)+1; 380 if (sbus_dma_data->resp_words!=(ack_num_words-1)) { 381 cmicx_log("ERROR: number of data words recieved from sbus command ack does not match response expected from sbus dma settings. ack num words: "); 382 cmicx_log_int(ack_num_words); 383 cmicx_log(". sbus address: "); 384 cmicx_log_addr(command[1]); 385 cmicx_log_newline(); 386 return false; 387 } 388 389 /* if we have 64-bits of data and the wordswap_in_64bit_sbusdata flag is enabled (from the request register), then we need to swap these two words before using them */ 390 if ((ack_num_words==3) && (sbus_dma_data->wordswap_in_64bit_sbus_data==true)) { 391 temp = ack_command[1]; 392 ack_command[1] = ack_command[2]; 393 ack_command[2] = temp; 394 } 395 396 /* load the ack sbus command data words ONLY into host memory (if any exist), while incrementing the host memory pointer */ 397 if (sbus_dma_data->dma_wr_to_nullspace==false) { 398 cmicx_pcid_mem_write(pcid_info,temp_address,(void *)&(ack_command[1]),(ack_num_words-1)*CMICX_BYTES_PER_WORD); 399 temp_address += (ack_num_words-1)*CMIC_SBUS_DMA_BYTES_PER_WORD; 400 } 401 cmicx_log(" wrote ack data words to host memory during sbus dma transaction on \""); 402 cmicx_log(sbus_dma_data->id_string); 403 cmicx_log("\". num words: "); 404 cmicx_log_int(ack_num_words-1); 405 cmicx_log("... "); 406 407 } 408 else { 409 cmicx_log(" sbus write command complete on \""); 410 cmicx_log(sbus_dma_data->id_string); 411 cmicx_log("\", not writing any words to memory... "); 412 } 413 414 } 415 else { 416 cmicx_log("ERROR: could not complete sbus command during sbus dma sequence. sbus address: "); 417 cmicx_log_addr(command[1]); 418 cmicx_log_newline(); 419 return false; 420 } 421 422 423 /* decrement our command count, since we've finished a command. if we are then not at the last command, increment the sbus address register */ 424 /* to set up for the next sbus command to be dispatched, and assign the new current hostmem address value */ 425 sbus_dma_data->cur_count--; 426 cmicx_log("cur_count: "); 427 cmicx_log_int(sbus_dma_data->cur_count); 428 cmicx_log(" "); 429 cmicx_log_newline(); 430 if (sbus_dma_data->cur_count!=0) { 431 432 /* if we are supposed to increment/decrement the address, perform the increment/decrement */ 433 if (sbus_dma_data->incr_noadd==false) { 434 if (sbus_dma_data->decrement==true) { 435 sbus_dma_data->cur_sbus_address -= (1<<sbus_dma_data->incr_shift); 436 } 437 else { 438 sbus_dma_data->cur_sbus_address += (1<<sbus_dma_data->incr_shift); 439 } 440 } 441 442 /* make sure the current hostmem address is up-to-date for the next sbus command. */ 443 if (sbus_dma_data->req_single == false) { 444 sbus_dma_data->cur_hostmem_address = temp_address; 445 } 446 } 447 448 /* if we are done with the last command in the sequence, then we need to determine what to do. either end the sbus dma access altogether, */ 449 /* or just end the descriptor and move on to the next. */ 450 else { 451 452 /* the sbus dma sequence is done, no matter what mode we're in. but if we're in descriptor mode, then also toggle the discriptor notification bits. */ 453 sbus_dma_data->sequence_pending = false; 454 if (sbus_dma_data->mode==CMIC_SBUS_DMA_DESCRIPTOR_MODE) { 455 sbus_dma_data->desc_done = true; 456 sbus_dma_data->sbusdma_active = false; 457 } 458 459 /* if this was the last desc in the sbus dma access, then mark the sbus dma access done altogether */ 460 if (sbus_dma_data->last_desc) { 461 462 /* if timer mode is enabled, then we need to prepare for another round of the sbus dma, with the originally programmed settings. set the timer countdown. */ 463 /* note 'done' is not marked, because sbus dma will never complete without abort when in timer based mode. */ 464 if (sbus_dma_data->timer_running==true) { 465 sbus_dma_data->access_running = false; 466 sbus_dma_data->timer_countdown = sbus_dma_data->timer; 467 cmicx_log("ending sbus dma access on \""); 468 cmicx_log(sbus_dma_data->id_string); 469 cmicx_log("\", but timer mode is on. a new one will start soon."); 470 cmicx_log_newline(); 471 } 472 473 /* if timer mode is not enabled, then we are entirely done with the sbus dma */ 474 else { 475 sbus_dma_data->access_running = false; 476 sbus_dma_data->done = true; 477 cmicx_log("ending sbus dma access on \""); 478 cmicx_log(sbus_dma_data->id_string); 479 cmicx_log("\""); 480 cmicx_log_newline(); 481 } 482 } 483 484 /* not ending the sbus dma access, but done with the descriptor. set the next current descriptor address */ 485 else { 486 sbus_dma_data->cur_desc_address += (CMIC_SBUS_DMA_BYTES_PER_WORD*CMIC_SBUS_DMA_WORDS_PER_DESCRIPTOR); /* bytes per word (4) times number of descriptors (8) */ 487 } 488 489 } 490 491 /* increment the iteration count for the iter_count register, since we've completed another sbus command in the sequence */ 492 sbus_dma_data->iter_count++; 493 494 } 495 496 } 497 498 499 } 500 501 /* end update successfully */ 502 cmicx_log_level_set(0); 503 cmicx_log(" ...done."); 504 cmicx_log_newline(); 505 cmicx_log_level_set(3); 506 return true; 507 508 } 509 510 511 /* starts a new sbus dma access for a given sbus dma module */ 512 bool cmic_sbus_dma_access_start(cmicx_sbus_dma_data_t *sbus_dma_data) { 513 514 /* start logging */ 515 cmicx_log("attempting to start new sbus dma access on \""); 516 cmicx_log(sbus_dma_data->id_string); 517 cmicx_log("\"... "); 518 519 /* already running failure */ 520 if (sbus_dma_data->access_running==true) { 521 cmicx_log(" failure: access already running.\n"); 522 return false; 523 } 524 525 /* set variables for successfully beginning sbus dma access */ 526 sbus_dma_data->access_running = true; 527 sbus_dma_data->start = true; 528 sbus_dma_data->iter_count = 0; 529 sbus_dma_data->last_desc = false; 530 sbus_dma_data->sequence_pending = false; 531 sbus_dma_data->sbus_command_countdown = 0; 532 sbus_dma_data->pend_clocks_countdown = 0; 533 sbus_dma_data->active = true; 534 535 /* if we are in timer-based mode, we need to make sure timer_running is high, so that */ 536 /* we continue to loop sbus dma accesses after this one completes. */ 537 if (sbus_dma_data->timer!=0) { 538 sbus_dma_data->timer_running = true; 539 } 540 541 /* sbus dma access successfully started */ 542 cmicx_log(" successfully started sbus dma access."); 543 cmicx_log_newline(); 544 return true; 545 } 546 547 548 /* aborts an sbus dma access for a given sbus dma module */ 549 bool cmic_sbus_dma_access_abort(cmicx_sbus_dma_data_t *sbus_dma_data) { 550 551 /* if we have an access running or we are in timer-based mode, abort the sbus dma activity and log a message. */ 552 /* otherwise, just log a message that we could not abort. */ 553 if ((sbus_dma_data->access_running==true) || (sbus_dma_data->timer!=0)) { 554 sbus_dma_data->access_running = false; 555 sbus_dma_data->last_desc = false; 556 sbus_dma_data->timer_running = false; 557 sbus_dma_data->timer_countdown = 0; 558 sbus_dma_data->sequence_pending = false; 559 sbus_dma_data->sbus_command_countdown = 0; 560 sbus_dma_data->pend_clocks_countdown = 0; 561 sbus_dma_data->done = true; 562 cmicx_log("sbus dma access on \""); 563 cmicx_log(sbus_dma_data->id_string); 564 cmicx_log("\" successfully aborted."); 565 cmicx_log_newline(); 566 return true; 567 } 568 else { 569 cmicx_log("could not abort sbus dma access on \""); 570 cmicx_log(sbus_dma_data->id_string); 571 cmicx_log("\", no access currently pending.\n"); 572 return false; 573 } 574 575 } 576 577 578 579 /**********************************************/ 580 /* sbus dma register access support functions */ 581 /**********************************************/ 582 583 584 /* control register read support function */ 585 bool cmic_sbusdma_control_read(reg_t *val,cmicx_sbus_dma_data_t *sbus_dma_data) { 586 587 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_CONTROL_REG_DESC_PREFETCH_ENABLE_BIT,sbus_dma_data->desc_prefetch_enable); 588 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_CONTROL_REG_ENDIANNESS_BIT, sbus_dma_data->endianness ); 589 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_CONTROL_REG_MODE_BIT, sbus_dma_data->mode ); 590 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_CONTROL_REG_ABORT_BIT, false ); 591 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_CONTROL_REG_START_BIT, sbus_dma_data->start ); 592 return true; 593 594 } 595 596 597 /* control register write support function */ 598 bool cmic_sbusdma_control_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data) { 599 600 bool return_value = true; 601 602 /* grab new bits from reg value write */ 603 bool new_ctrl_desc_prefetch_enable_bit = REG_BIT_GET(val,CMIC_SBUSDMA_CONTROL_REG_DESC_PREFETCH_ENABLE_BIT); 604 bool new_ctrl_endianness_bit = REG_BIT_GET(val,CMIC_SBUSDMA_CONTROL_REG_ENDIANNESS_BIT); 605 bool new_ctrl_mode_bit = REG_BIT_GET(val,CMIC_SBUSDMA_CONTROL_REG_MODE_BIT); 606 bool new_ctrl_abort_bit = REG_BIT_GET(val,CMIC_SBUSDMA_CONTROL_REG_ABORT_BIT); 607 bool new_ctrl_start_bit = REG_BIT_GET(val,CMIC_SBUSDMA_CONTROL_REG_START_BIT); 608 609 /* check that we are not trying to change the endianness or mode while we already have an access running */ 610 if (sbus_dma_data->access_running==true) { 611 612 if (new_ctrl_mode_bit!=sbus_dma_data->mode) { 613 cmicx_log("attempting to change sbus dma mode on "); 614 cmicx_log(sbus_dma_data->id_string); 615 cmicx_log(" while sbus dma is running. failure.\n"); 616 return_value = false; 617 } 618 if (new_ctrl_endianness_bit!=sbus_dma_data->endianness) { 619 cmicx_log("attempting to change sbus dma endianness on "); 620 cmicx_log(sbus_dma_data->id_string); 621 cmicx_log(" while sbus dma is running. failure.\n"); 622 return_value = false; 623 } 624 if (new_ctrl_desc_prefetch_enable_bit!=sbus_dma_data->desc_prefetch_enable) { 625 cmicx_log("attempting to change sbus dma desc_prefetch enable mode on "); 626 cmicx_log(sbus_dma_data->id_string); 627 cmicx_log(" while sbus dma is running. failure.\n"); 628 return_value = false; 629 } 630 631 } 632 else { 633 sbus_dma_data->desc_prefetch_enable = new_ctrl_desc_prefetch_enable_bit; 634 sbus_dma_data->endianness = new_ctrl_abort_bit; 635 sbus_dma_data->mode = new_ctrl_mode_bit; 636 } 637 638 /* start a new access or abort if requested */ 639 if (new_ctrl_abort_bit==true) { 640 if (cmic_sbus_dma_access_abort(sbus_dma_data)==false) { 641 return_value = false; 642 } 643 if (new_ctrl_start_bit==true) { 644 cmicx_log("ctrl start bit being ignored on \""); 645 cmicx_log(sbus_dma_data->id_string); 646 cmicx_log("\" due to simultaneous abort attempt."); 647 cmicx_log_newline(); 648 } 649 } 650 else { 651 if (new_ctrl_start_bit==true) { 652 if (sbus_dma_data->access_running==false) { 653 if (cmic_sbus_dma_access_start(sbus_dma_data)==false) { 654 return_value = false; 655 } 656 } 657 else { 658 cmicx_log("ctrl start bit being ignored on \""); 659 cmicx_log(sbus_dma_data->id_string); 660 cmicx_log("\" due to access already running."); 661 cmicx_log_newline(); 662 } 663 } 664 } 665 666 /* if we are trying to clear the start bit: check that it is legal, and then make all the necessary internal state changes */ 667 if (new_ctrl_start_bit==false) { 668 669 /* if the done bit is high and no access is running, we can clear the start bit successfully (and most error bits) */ 670 if ((sbus_dma_data->done==true) && (sbus_dma_data->access_running==false)) { 671 sbus_dma_data->start = false; 672 sbus_dma_data->sbusdma_active = false; 673 sbus_dma_data->active = false; 674 sbus_dma_data->descrd_error = false; 675 sbus_dma_data->sbusack_timeout = false; 676 sbus_dma_data->sbusack_error = false; 677 sbus_dma_data->sbusack_nack = false; 678 sbus_dma_data->sbusack_wrong_opcode = false; 679 sbus_dma_data->sbusack_wrong_beatcount = false; 680 sbus_dma_data->ser_check_fail = false; 681 sbus_dma_data->hostmemrd_error = false; 682 sbus_dma_data->hostmemwr_error = false; 683 sbus_dma_data->error = false; 684 sbus_dma_data->done = false; 685 } 686 687 /* invalid case for clearing start bit */ 688 else { 689 cmicx_log("trying to clear start bit for \""); 690 cmicx_log(sbus_dma_data->id_string); 691 cmicx_log("\": status register done bit is not high, or sbus dma access is currently running. failure.\n"); 692 return_value = false; 693 } 694 695 } 696 697 /* 698 cmicx_log("cur hostmem address: \""); 699 cmicx_log_ 700 */ 701 702 return return_value; 703 } 704 705 706 707 /* status register read support function */ 708 bool cmic_sbusdma_status_read(reg_t *val,cmicx_sbus_dma_data_t *sbus_dma_data) { 709 710 /* pack the current status bits into the register */ 711 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_ECC_2BIT_CHECK_FAIL_BIT, sbus_dma_data->ecc_2bit_check_fail); 712 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_SBUSDMA_ACTIVE_BIT, sbus_dma_data->sbusdma_active); 713 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_ACTIVE_BIT, sbus_dma_data->active); 714 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_DESCRD_ERROR_BIT, sbus_dma_data->descrd_error); 715 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_SBUSACK_TIMEOUT_BIT, sbus_dma_data->sbusack_timeout); 716 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_SBUSACK_ERROR_BIT, sbus_dma_data->sbusack_error); 717 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_SBUSACK_NACK_BIT, sbus_dma_data->sbusack_nack); 718 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_SBUSACK_WRONG_OPCODE_BIT, sbus_dma_data->sbusack_wrong_opcode); 719 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_SBUSACK_WRONG_BEATCOUNT_BIT,sbus_dma_data->sbusack_wrong_beatcount); 720 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_SER_CHECK_FAIL_BIT, sbus_dma_data->ser_check_fail); 721 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_HOSTMEMRD_ERROR_BIT, sbus_dma_data->hostmemrd_error); 722 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_HOSTMEMWR_ERROR_BIT, sbus_dma_data->hostmemwr_error); 723 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_ERROR_BIT, sbus_dma_data->error); 724 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_STATUS_REG_DONE_BIT, sbus_dma_data->done); 725 return true; 726 727 } 728 729 /* request register read helper function */ 730 bool cmic_sbusdma_request_read(reg_t *val,cmicx_sbus_dma_data_t *sbus_dma_data) { 731 REG_BIT_SET_TO( *val,CMIC_SBUSDMA_REQUEST_REG_DECR_BIT, sbus_dma_data->decrement); 732 REG_BIT_SET_TO( *val,CMIC_SBUSDMA_REQUEST_REG_REQ_SINGLE_BIT, sbus_dma_data->req_single); 733 REG_BIT_SET_TO( *val,CMIC_SBUSDMA_REQUEST_REG_INCR_NOADD_BIT, sbus_dma_data->incr_noadd); 734 REG_FIELD_SET_TO(*val,CMIC_SBUSDMA_REQUEST_REG_INCR_SHIFT_MSB, CMIC_SBUSDMA_REQUEST_REG_INCR_SHIFT_LSB, sbus_dma_data->incr_shift); 735 REG_FIELD_SET_TO(*val,CMIC_SBUSDMA_REQUEST_REG_PEND_CLOCKS_MSB,CMIC_SBUSDMA_REQUEST_REG_PEND_CLOCKS_LSB,sbus_dma_data->pend_clocks); 736 REG_BIT_SET_TO( *val,CMIC_SBUSDMA_REQUEST_REG_DMA_WR_TO_NULLSPACE_BIT, sbus_dma_data->dma_wr_to_nullspace); 737 REG_BIT_SET_TO( *val,CMIC_SBUSDMA_REQUEST_REG_WORDSWAP_IN_64BIT_SBUSDATA_BIT, sbus_dma_data->wordswap_in_64bit_sbus_data); 738 REG_BIT_SET_TO( *val,CMIC_SBUSDMA_REQUEST_REG_MEMWR_ENDIANNESS_BIT, sbus_dma_data->memwr_endianness); 739 REG_BIT_SET_TO( *val,CMIC_SBUSDMA_REQUEST_REG_MEMRD_ENDIANNESS_BIT, sbus_dma_data->memrd_endianness); 740 REG_FIELD_SET_TO(*val,CMIC_SBUSDMA_REQUEST_REG_REQ_WORDS_MSB,CMIC_SBUSDMA_REQUEST_REG_REQ_WORDS_LSB, sbus_dma_data->req_words); 741 REG_FIELD_SET_TO(*val,CMIC_SBUSDMA_REQUEST_REG_REP_WORDS_MSB,CMIC_SBUSDMA_REQUEST_REG_REP_WORDS_LSB, sbus_dma_data->resp_words); 742 return true; 743 } 744 745 /* request register write helper function */ 746 bool cmic_sbusdma_request_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data) { 747 sbus_dma_data->decrement = REG_BIT_GET( val,CMIC_SBUSDMA_REQUEST_REG_DECR_BIT); 748 sbus_dma_data->req_single = REG_BIT_GET( val,CMIC_SBUSDMA_REQUEST_REG_REQ_SINGLE_BIT); 749 sbus_dma_data->incr_noadd = REG_BIT_GET( val,CMIC_SBUSDMA_REQUEST_REG_INCR_NOADD_BIT); 750 sbus_dma_data->incr_shift = REG_FIELD_GET(val,CMIC_SBUSDMA_REQUEST_REG_INCR_SHIFT_MSB, CMIC_SBUSDMA_REQUEST_REG_INCR_SHIFT_LSB); 751 sbus_dma_data->pend_clocks = REG_FIELD_GET(val,CMIC_SBUSDMA_REQUEST_REG_PEND_CLOCKS_MSB,CMIC_SBUSDMA_REQUEST_REG_PEND_CLOCKS_LSB); 752 sbus_dma_data->dma_wr_to_nullspace = REG_BIT_GET( val,CMIC_SBUSDMA_REQUEST_REG_DMA_WR_TO_NULLSPACE_BIT); 753 sbus_dma_data->wordswap_in_64bit_sbus_data = REG_BIT_GET( val,CMIC_SBUSDMA_REQUEST_REG_WORDSWAP_IN_64BIT_SBUSDATA_BIT); 754 sbus_dma_data->memwr_endianness = REG_BIT_GET( val,CMIC_SBUSDMA_REQUEST_REG_INCR_NOADD_BIT); 755 sbus_dma_data->memrd_endianness = REG_BIT_GET( val,CMIC_SBUSDMA_REQUEST_REG_MEMWR_ENDIANNESS_BIT); 756 sbus_dma_data->req_words = REG_FIELD_GET(val,CMIC_SBUSDMA_REQUEST_REG_REQ_WORDS_MSB,CMIC_SBUSDMA_REQUEST_REG_REQ_WORDS_LSB); 757 sbus_dma_data->resp_words = REG_FIELD_GET(val,CMIC_SBUSDMA_REQUEST_REG_REP_WORDS_MSB,CMIC_SBUSDMA_REQUEST_REG_REP_WORDS_LSB); 758 sbus_dma_data->cur_sbusdma_config_request = val; 759 return true; 760 } 761 762 /* count register write helper function */ 763 bool cmic_sbusdma_count_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data) { 764 sbus_dma_data->cur_count = val; 765 sbus_dma_data->cur_sbusdma_config_count = val; 766 return true; 767 } 768 769 /* opcode register write helper function */ 770 bool cmic_sbusdma_opcode_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data) { 771 sbus_dma_data->opcode = val; 772 sbus_dma_data->cur_sbusdma_config_opcode = val; 773 return true; 774 } 775 776 /* sbus start address write helper function */ 777 bool cmic_sbusdma_sbus_start_address_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data) { 778 sbus_dma_data->cur_sbus_address = val; 779 sbus_dma_data->cur_sbusdma_config_sbus_start_address = val; 780 return true; 781 } 782 783 /* hostmem start address write helper function - lo */ 784 bool cmic_sbusdma_hostmem_start_address_lo_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data) { 785 UINT64_LOWER32_REFERENCE(sbus_dma_data->cur_hostmem_address) = val; 786 UINT64_LOWER32_REFERENCE(sbus_dma_data->cur_sbusdma_config_hostmem_start_address) = val; 787 return true; 788 } 789 790 /* hostmem start address write helper function - hi */ 791 bool cmic_sbusdma_hostmem_start_address_hi_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data) { 792 UINT64_UPPER32_REFERENCE(sbus_dma_data->cur_hostmem_address) = val; 793 UINT64_UPPER32_REFERENCE(sbus_dma_data->cur_sbusdma_config_hostmem_start_address) = val; 794 return true; 795 } 796 797 /* desc start address write helper function - lo */ 798 bool cmic_sbusdma_desc_start_address_lo_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data) { 799 UINT64_LOWER32_REFERENCE(sbus_dma_data->cur_desc_address) = val; 800 UINT64_LOWER32_REFERENCE(sbus_dma_data->cur_sbusdma_config_desc_start_address) = val; 801 return true; 802 } 803 804 /* desc start address write helper function - hi */ 805 bool cmic_sbusdma_desc_start_address_hi_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data) { 806 UINT64_UPPER32_REFERENCE(sbus_dma_data->cur_desc_address) = val; 807 UINT64_UPPER32_REFERENCE(sbus_dma_data->cur_sbusdma_config_desc_start_address) = val; 808 return true; 809 } 810 811 /* cmc config register read helper function */ 812 bool cmic_sbusdma_shared_config_read(reg_t *val,cmicx_cmc_t *cmc_data) { 813 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_CONFIG_REG_ENABLE_EARLY_BRESP_BIT, cmc_data->enable_early_bresp); 814 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_CONFIG_REG_ENABLE_SBUSDMA_CH0_FLOW_CONTROL_BIT, cmc_data->sbus_dma[0].enable_sbusdma_flow_control); 815 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_CONFIG_REG_ENABLE_SBUSDMA_CH1_FLOW_CONTROL_BIT, cmc_data->sbus_dma[1].enable_sbusdma_flow_control); 816 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_CONFIG_REG_ENABLE_SBUSDMA_CH2_FLOW_CONTROL_BIT, cmc_data->sbus_dma[2].enable_sbusdma_flow_control); 817 return true; 818 } 819 820 /* cmc config register write helper function */ 821 bool cmic_sbusdma_shared_config_write(reg_t val,cmicx_cmc_t *cmc_data) { 822 823 /* get new values */ 824 bool new_sbusdma_early_bresp = REG_BIT_GET(val,CMIC_SBUSDMA_CONFIG_REG_ENABLE_EARLY_BRESP_BIT); 825 bool new_sbusdma_flow_control_ch0 = REG_BIT_GET(val,CMIC_SBUSDMA_CONFIG_REG_ENABLE_SBUSDMA_CH0_FLOW_CONTROL_BIT); 826 bool new_sbusdma_flow_control_ch1 = REG_BIT_GET(val,CMIC_SBUSDMA_CONFIG_REG_ENABLE_SBUSDMA_CH1_FLOW_CONTROL_BIT); 827 bool new_sbusdma_flow_control_ch2 = REG_BIT_GET(val,CMIC_SBUSDMA_CONFIG_REG_ENABLE_SBUSDMA_CH2_FLOW_CONTROL_BIT); 828 829 /* display outputs for flow controls being enabled, because this won't actually have any effect in the sim */ 830 if (new_sbusdma_early_bresp==true) { 831 cmicx_log("enabling early bresp on \""); 832 } 833 else { 834 cmicx_log("disabling early bresp on \""); 835 } 836 cmicx_log(cmc_data->id_string); 837 cmicx_log("\""); 838 cmicx_log_newline(); 839 if (new_sbusdma_flow_control_ch0==true) { 840 cmicx_log("enabling flow control on \""); 841 } 842 else { 843 cmicx_log("disabling flow control on \""); 844 } 845 cmicx_log(cmc_data->sbus_dma[0].id_string); 846 cmicx_log("\""); 847 cmicx_log_newline(); 848 if (new_sbusdma_flow_control_ch1==true) { 849 cmicx_log("enabling flow control on \""); 850 } 851 else { 852 cmicx_log("disabling flow control on \""); 853 } 854 cmicx_log(cmc_data->sbus_dma[1].id_string); 855 cmicx_log("\""); 856 cmicx_log_newline(); 857 if (new_sbusdma_flow_control_ch2==true) { 858 cmicx_log("enabling flow control on \""); 859 } 860 else { 861 cmicx_log("disabling flow control on \""); 862 } 863 cmicx_log(cmc_data->sbus_dma[2].id_string); 864 cmicx_log("\""); 865 cmicx_log_newline(); 866 867 /* set actual internal control values and exit */ 868 cmc_data->enable_early_bresp = new_sbusdma_early_bresp; 869 cmc_data->sbus_dma[0].enable_sbusdma_flow_control = new_sbusdma_flow_control_ch0; 870 cmc_data->sbus_dma[1].enable_sbusdma_flow_control = new_sbusdma_flow_control_ch1; 871 cmc_data->sbus_dma[2].enable_sbusdma_flow_control = new_sbusdma_flow_control_ch2; 872 return true; 873 } 874 875 /* sbus dma debug register read */ 876 bool cmic_sbusdma_debug_read(reg_t *val,cmicx_sbus_dma_data_t *sbus_dma_data) { 877 878 REG_BIT_SET_TO(*val,CMIC_SBUSDMA_DEBUG_REG_DESC_DONE_BIT, sbus_dma_data->desc_done); 879 return true; 880 } 881 882 /* sbus dma debug clear register write */ 883 bool cmic_sbusdma_debug_clr_write(reg_t val,cmicx_sbus_dma_data_t *sbus_dma_data) { 884 885 bool new_ecc_2bit_check_fail = REG_BIT_GET(val,CMIC_SBUSDMA_DEBUG_REG_ECC_2BIT_CHECK_FAIL_BIT); 886 bool new_desc_done = REG_BIT_GET(val,CMIC_SBUSDMA_DEBUG_REG_DESC_DONE_BIT); 887 888 if (new_ecc_2bit_check_fail==true) { 889 sbus_dma_data->ecc_2bit_check_fail = false; 890 } 891 if (new_desc_done==true) { 892 sbus_dma_data->desc_done = false; 893 } 894 895 return true; 896 } 897 898 899 900 /****************************************************/ 901 /* define sbus dma register direct access functions */ 902 /****************************************************/ 903 904 /* sbus ring arbiter control read/write */ 905 bool cmic_top_sbus_ring_arb_ctrl_sbusdma_read(reg_t *val) { 906 REG_FIELD_SET_TO(*val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH0_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH0_WEIGHT_LSB,cmicx->sbus_ring_arb_ctrl_sbusdma_cmc0_ch_weight[0]); 907 REG_FIELD_SET_TO(*val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH1_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH1_WEIGHT_LSB,cmicx->sbus_ring_arb_ctrl_sbusdma_cmc0_ch_weight[1]); 908 REG_FIELD_SET_TO(*val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH2_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH2_WEIGHT_LSB,cmicx->sbus_ring_arb_ctrl_sbusdma_cmc0_ch_weight[2]); 909 REG_FIELD_SET_TO(*val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH0_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH0_WEIGHT_LSB,cmicx->sbus_ring_arb_ctrl_sbusdma_cmc1_ch_weight[0]); 910 REG_FIELD_SET_TO(*val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH1_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH1_WEIGHT_LSB,cmicx->sbus_ring_arb_ctrl_sbusdma_cmc1_ch_weight[1]); 911 REG_FIELD_SET_TO(*val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH2_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH2_WEIGHT_LSB,cmicx->sbus_ring_arb_ctrl_sbusdma_cmc1_ch_weight[2]); 912 return true; 913 } 914 bool cmic_top_sbus_ring_arb_ctrl_sbusdma_write(reg_t val) { 915 cmicx->sbus_ring_arb_ctrl_sbusdma_cmc0_ch_weight[0] = REG_FIELD_GET(val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH0_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH0_WEIGHT_LSB); 916 cmicx->sbus_ring_arb_ctrl_sbusdma_cmc0_ch_weight[1] = REG_FIELD_GET(val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH1_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH1_WEIGHT_LSB); 917 cmicx->sbus_ring_arb_ctrl_sbusdma_cmc0_ch_weight[2] = REG_FIELD_GET(val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH2_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC0_CH2_WEIGHT_LSB); 918 cmicx->sbus_ring_arb_ctrl_sbusdma_cmc1_ch_weight[0] = REG_FIELD_GET(val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH0_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH0_WEIGHT_LSB); 919 cmicx->sbus_ring_arb_ctrl_sbusdma_cmc1_ch_weight[1] = REG_FIELD_GET(val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH1_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH1_WEIGHT_LSB); 920 cmicx->sbus_ring_arb_ctrl_sbusdma_cmc1_ch_weight[2] = REG_FIELD_GET(val,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH2_WEIGHT_MSB,CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_CMC1_CH2_WEIGHT_LSB); 921 return true; 922 } 923 924 /* cmc 0 shared config */ 925 bool cmic_cmc0_shared_config_read(reg_t *val) { 926 return cmic_sbusdma_shared_config_read(val,&cmicx->cmc0); 927 } 928 bool cmic_cmc0_shared_config_write(reg_t val) { 929 return cmic_sbusdma_shared_config_write(val,&cmicx->cmc0); 930 } 931 932 /* cmc0, sbus dma ch0 */ 933 bool cmic_cmc0_sbusdma_ch0_control_read(reg_t *val) { 934 return cmic_sbusdma_control_read(val,&cmicx->cmc0.sbus_dma[0]); 935 } 936 bool cmic_cmc0_sbusdma_ch0_control_write(reg_t val) { 937 return cmic_sbusdma_control_write(val,&cmicx->cmc0.sbus_dma[0]); 938 } 939 bool cmic_cmc0_sbusdma_ch0_request_read(reg_t *val) { 940 return cmic_sbusdma_request_read(val,&cmicx->cmc0.sbus_dma[0]); 941 } 942 bool cmic_cmc0_sbusdma_ch0_request_write(reg_t val) { 943 return cmic_sbusdma_request_write(val,&cmicx->cmc0.sbus_dma[0]); 944 } 945 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_count_read, cmicx->cmc0.sbus_dma[0].cur_count ) 946 bool cmic_cmc0_sbusdma_ch0_count_write(reg_t val) { 947 return cmic_sbusdma_count_write(val,&cmicx->cmc0.sbus_dma[0]); 948 } 949 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_opcode_read, cmicx->cmc0.sbus_dma[0].opcode ) 950 bool cmic_cmc0_sbusdma_ch0_opcode_write(reg_t val) { 951 return cmic_sbusdma_opcode_write(val,&cmicx->cmc0.sbus_dma[0]); 952 } 953 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_sbus_start_address_read, cmicx->cmc0.sbus_dma[0].cur_sbus_address ) 954 bool cmic_cmc0_sbusdma_ch0_sbus_start_address_write(reg_t val) { 955 return cmic_sbusdma_sbus_start_address_write(val,&cmicx->cmc0.sbus_dma[0]); 956 } 957 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[0].cur_hostmem_address)) 958 bool cmic_cmc0_sbusdma_ch0_hostmem_start_address_lo_write(reg_t val) { 959 return cmic_sbusdma_hostmem_start_address_lo_write(val,&cmicx->cmc0.sbus_dma[0]); 960 } 961 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[0].cur_hostmem_address)) 962 bool cmic_cmc0_sbusdma_ch0_hostmem_start_address_hi_write(reg_t val) { 963 return cmic_sbusdma_hostmem_start_address_hi_write(val,&cmicx->cmc0.sbus_dma[0]); 964 } 965 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_desc_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[0].cur_desc_address) ) 966 bool cmic_cmc0_sbusdma_ch0_desc_start_address_lo_write(reg_t val) { 967 return cmic_sbusdma_desc_start_address_lo_write(val,&cmicx->cmc0.sbus_dma[0]); 968 } 969 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_desc_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[0].cur_desc_address) ) 970 bool cmic_cmc0_sbusdma_ch0_desc_start_address_hi_write(reg_t val) { 971 return cmic_sbusdma_desc_start_address_hi_write(val,&cmicx->cmc0.sbus_dma[0]); 972 } 973 bool cmic_cmc0_sbusdma_ch0_status_read(reg_t *val) { 974 return cmic_sbusdma_status_read(val,&cmicx->cmc0.sbus_dma[0]); 975 } 976 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_status_write) 977 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_hostmem_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[0].cur_hostmem_address)) 978 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_hostmem_address_lo_write) 979 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_hostmem_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[0].cur_hostmem_address)) 980 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_hostmem_address_hi_write) 981 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_sbus_address_read, cmicx->cmc0.sbus_dma[0].cur_sbus_address) 982 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_sbus_address_write) 983 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_desc_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[0].cur_desc_address)) 984 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_desc_address_lo_write) 985 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_desc_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[0].cur_desc_address)) 986 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_desc_address_hi_write) 987 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_request_read, cmicx->cmc0.sbus_dma[0].cur_sbusdma_config_request) 988 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_request_write) 989 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_count_read, cmicx->cmc0.sbus_dma[0].cur_sbusdma_config_count) 990 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_count_write) 991 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_read, cmicx->cmc0.sbus_dma[0].cur_sbusdma_config_sbus_start_address) 992 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_write) 993 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[0].cur_sbusdma_config_hostmem_start_address)) 994 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_write) 995 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[0].cur_sbusdma_config_hostmem_start_address)) 996 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_write) 997 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_opcode_read, cmicx->cmc0.sbus_dma[0].cur_sbusdma_config_opcode) 998 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_opcode_write) 999 bool cmic_cmc0_sbusdma_ch0_sbusdma_debug_read(reg_t *val) { 1000 return cmic_sbusdma_debug_read(val,&cmicx->cmc0.sbus_dma[0]); 1001 } 1002 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_sbusdma_debug_write) 1003 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch0_sbusdma_debug_clr_read) 1004 bool cmic_cmc0_sbusdma_ch0_sbusdma_debug_clr_write(reg_t val) { 1005 return cmic_sbusdma_debug_clr_write(val,&cmicx->cmc0.sbus_dma[0]); 1006 } 1007 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_address_lo_read) 1008 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_address_lo_write) 1009 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_address_hi_read) 1010 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_address_hi_write) 1011 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_control_read) 1012 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_sbusdma_eccerr_control_write) 1013 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_iter_count_read, cmicx->cmc0.sbus_dma[0].iter_count) 1014 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_iter_count_write) 1015 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch0_timer_read, cmicx->cmc0.sbus_dma[0].timer) 1016 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_sbusdma_ch0_timer_write, cmicx->cmc0.sbus_dma[0].timer) 1017 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch0_tm_control_0_read) 1018 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_tm_control_0_write) 1019 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch0_tm_control_1_read) 1020 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_tm_control_1_write) 1021 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch0_tm_control_2_read) 1022 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch0_tm_control_2_write) 1023 1024 /* cmc0, sbus dma ch1 */ 1025 bool cmic_cmc0_sbusdma_ch1_control_read(reg_t *val) { 1026 return cmic_sbusdma_control_read(val,&cmicx->cmc0.sbus_dma[1]); 1027 } 1028 bool cmic_cmc0_sbusdma_ch1_control_write(reg_t val) { 1029 return cmic_sbusdma_control_write(val,&cmicx->cmc0.sbus_dma[1]); 1030 } 1031 bool cmic_cmc0_sbusdma_ch1_request_read(reg_t *val) { 1032 return cmic_sbusdma_request_read(val,&cmicx->cmc0.sbus_dma[1]); 1033 } 1034 bool cmic_cmc0_sbusdma_ch1_request_write(reg_t val) { 1035 return cmic_sbusdma_request_write(val,&cmicx->cmc0.sbus_dma[1]); 1036 } 1037 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_count_read, cmicx->cmc0.sbus_dma[1].cur_count ) 1038 bool cmic_cmc0_sbusdma_ch1_count_write(reg_t val) { 1039 return cmic_sbusdma_count_write(val,&cmicx->cmc0.sbus_dma[1]); 1040 } 1041 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_opcode_read, cmicx->cmc0.sbus_dma[1].opcode ) 1042 bool cmic_cmc0_sbusdma_ch1_opcode_write(reg_t val) { 1043 return cmic_sbusdma_opcode_write(val,&cmicx->cmc0.sbus_dma[1]); 1044 } 1045 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_sbus_start_address_read, cmicx->cmc0.sbus_dma[1].cur_sbus_address ) 1046 bool cmic_cmc0_sbusdma_ch1_sbus_start_address_write(reg_t val) { 1047 return cmic_sbusdma_sbus_start_address_write(val,&cmicx->cmc0.sbus_dma[1]); 1048 } 1049 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[1].cur_hostmem_address)) 1050 bool cmic_cmc0_sbusdma_ch1_hostmem_start_address_lo_write(reg_t val) { 1051 return cmic_sbusdma_hostmem_start_address_lo_write(val,&cmicx->cmc0.sbus_dma[1]); 1052 } 1053 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[1].cur_hostmem_address)) 1054 bool cmic_cmc0_sbusdma_ch1_hostmem_start_address_hi_write(reg_t val) { 1055 return cmic_sbusdma_hostmem_start_address_hi_write(val,&cmicx->cmc0.sbus_dma[1]); 1056 } 1057 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_desc_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[1].cur_desc_address) ) 1058 bool cmic_cmc0_sbusdma_ch1_desc_start_address_lo_write(reg_t val) { 1059 return cmic_sbusdma_desc_start_address_lo_write(val,&cmicx->cmc0.sbus_dma[1]); 1060 } 1061 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_desc_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[1].cur_desc_address) ) 1062 bool cmic_cmc0_sbusdma_ch1_desc_start_address_hi_write(reg_t val) { 1063 return cmic_sbusdma_desc_start_address_hi_write(val,&cmicx->cmc0.sbus_dma[1]); 1064 } 1065 bool cmic_cmc0_sbusdma_ch1_status_read(reg_t *val) { 1066 return cmic_sbusdma_status_read(val,&cmicx->cmc0.sbus_dma[1]); 1067 } 1068 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_status_write) 1069 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_hostmem_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[1].cur_hostmem_address)) 1070 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_hostmem_address_lo_write) 1071 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_hostmem_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[1].cur_hostmem_address)) 1072 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_hostmem_address_hi_write) 1073 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_sbus_address_read, cmicx->cmc0.sbus_dma[1].cur_sbus_address) 1074 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_sbus_address_write) 1075 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_desc_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[1].cur_desc_address)) 1076 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_desc_address_lo_write) 1077 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_desc_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[1].cur_desc_address)) 1078 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_desc_address_hi_write) 1079 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_request_read, cmicx->cmc0.sbus_dma[1].cur_sbusdma_config_request) 1080 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_request_write) 1081 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_count_read, cmicx->cmc0.sbus_dma[1].cur_sbusdma_config_count) 1082 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_count_write) 1083 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_read, cmicx->cmc0.sbus_dma[1].cur_sbusdma_config_sbus_start_address) 1084 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_write) 1085 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[1].cur_sbusdma_config_hostmem_start_address)) 1086 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_write) 1087 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[1].cur_sbusdma_config_hostmem_start_address)) 1088 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_write) 1089 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_opcode_read, cmicx->cmc0.sbus_dma[1].cur_sbusdma_config_opcode) 1090 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_opcode_write) 1091 bool cmic_cmc0_sbusdma_ch1_sbusdma_debug_read(reg_t *val) { 1092 return cmic_sbusdma_debug_read(val,&cmicx->cmc0.sbus_dma[1]); 1093 } 1094 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_sbusdma_debug_write) 1095 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch1_sbusdma_debug_clr_read) 1096 bool cmic_cmc0_sbusdma_ch1_sbusdma_debug_clr_write(reg_t val) { 1097 return cmic_sbusdma_debug_clr_write(val,&cmicx->cmc0.sbus_dma[1]); 1098 } 1099 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_address_lo_read) 1100 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_address_lo_write) 1101 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_address_hi_read) 1102 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_address_hi_write) 1103 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_control_read) 1104 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_sbusdma_eccerr_control_write) 1105 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_iter_count_read, cmicx->cmc0.sbus_dma[1].iter_count) 1106 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_iter_count_write) 1107 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch1_timer_read, cmicx->cmc0.sbus_dma[1].timer) 1108 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_sbusdma_ch1_timer_write, cmicx->cmc0.sbus_dma[1].timer) 1109 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch1_tm_control_0_read) 1110 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_tm_control_0_write) 1111 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch1_tm_control_1_read) 1112 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_tm_control_1_write) 1113 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch1_tm_control_2_read) 1114 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch1_tm_control_2_write) 1115 1116 /* cmc0, sbus dma ch2 */ 1117 bool cmic_cmc0_sbusdma_ch2_control_read(reg_t *val) { 1118 return cmic_sbusdma_control_read(val,&cmicx->cmc0.sbus_dma[2]); 1119 } 1120 bool cmic_cmc0_sbusdma_ch2_control_write(reg_t val) { 1121 return cmic_sbusdma_control_write(val,&cmicx->cmc0.sbus_dma[2]); 1122 } 1123 bool cmic_cmc0_sbusdma_ch2_request_read(reg_t *val) { 1124 return cmic_sbusdma_request_read(val,&cmicx->cmc0.sbus_dma[2]); 1125 } 1126 bool cmic_cmc0_sbusdma_ch2_request_write(reg_t val) { 1127 return cmic_sbusdma_request_write(val,&cmicx->cmc0.sbus_dma[2]); 1128 } 1129 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_count_read, cmicx->cmc0.sbus_dma[2].cur_count ) 1130 bool cmic_cmc0_sbusdma_ch2_count_write(reg_t val) { 1131 return cmic_sbusdma_count_write(val,&cmicx->cmc0.sbus_dma[2]); 1132 } 1133 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_opcode_read, cmicx->cmc0.sbus_dma[2].opcode ) 1134 bool cmic_cmc0_sbusdma_ch2_opcode_write(reg_t val) { 1135 return cmic_sbusdma_opcode_write(val,&cmicx->cmc0.sbus_dma[2]); 1136 } 1137 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_sbus_start_address_read, cmicx->cmc0.sbus_dma[2].cur_sbus_address ) 1138 bool cmic_cmc0_sbusdma_ch2_sbus_start_address_write(reg_t val) { 1139 return cmic_sbusdma_sbus_start_address_write(val,&cmicx->cmc0.sbus_dma[2]); 1140 } 1141 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[2].cur_hostmem_address)) 1142 bool cmic_cmc0_sbusdma_ch2_hostmem_start_address_lo_write(reg_t val) { 1143 return cmic_sbusdma_hostmem_start_address_lo_write(val,&cmicx->cmc0.sbus_dma[2]); 1144 } 1145 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[2].cur_hostmem_address)) 1146 bool cmic_cmc0_sbusdma_ch2_hostmem_start_address_hi_write(reg_t val) { 1147 return cmic_sbusdma_hostmem_start_address_hi_write(val,&cmicx->cmc0.sbus_dma[2]); 1148 } 1149 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_desc_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[2].cur_desc_address) ) 1150 bool cmic_cmc0_sbusdma_ch2_desc_start_address_lo_write(reg_t val) { 1151 return cmic_sbusdma_desc_start_address_lo_write(val,&cmicx->cmc0.sbus_dma[2]); 1152 } 1153 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_desc_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[2].cur_desc_address) ) 1154 bool cmic_cmc0_sbusdma_ch2_desc_start_address_hi_write(reg_t val) { 1155 return cmic_sbusdma_desc_start_address_hi_write(val,&cmicx->cmc0.sbus_dma[2]); 1156 } 1157 bool cmic_cmc0_sbusdma_ch2_status_read(reg_t *val) { 1158 return cmic_sbusdma_status_read(val,&cmicx->cmc0.sbus_dma[2]); 1159 } 1160 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_status_write) 1161 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_hostmem_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[2].cur_hostmem_address)) 1162 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_hostmem_address_lo_write) 1163 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_hostmem_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[2].cur_hostmem_address)) 1164 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_hostmem_address_hi_write) 1165 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_sbus_address_read, cmicx->cmc0.sbus_dma[2].cur_sbus_address) 1166 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_sbus_address_write) 1167 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_desc_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[2].cur_desc_address)) 1168 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_desc_address_lo_write) 1169 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_desc_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[2].cur_desc_address)) 1170 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_desc_address_hi_write) 1171 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_request_read, cmicx->cmc0.sbus_dma[2].cur_sbusdma_config_request) 1172 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_request_write) 1173 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_count_read, cmicx->cmc0.sbus_dma[2].cur_sbusdma_config_count) 1174 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_count_write) 1175 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_read, cmicx->cmc0.sbus_dma[2].cur_sbusdma_config_sbus_start_address) 1176 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_write) 1177 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[2].cur_sbusdma_config_hostmem_start_address)) 1178 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_write) 1179 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[2].cur_sbusdma_config_hostmem_start_address)) 1180 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_write) 1181 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_opcode_read, cmicx->cmc0.sbus_dma[2].cur_sbusdma_config_opcode) 1182 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_opcode_write) 1183 bool cmic_cmc0_sbusdma_ch2_sbusdma_debug_read(reg_t *val) { 1184 return cmic_sbusdma_debug_read(val,&cmicx->cmc0.sbus_dma[2]); 1185 } 1186 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_sbusdma_debug_write) 1187 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch2_sbusdma_debug_clr_read) 1188 bool cmic_cmc0_sbusdma_ch2_sbusdma_debug_clr_write(reg_t val) { 1189 return cmic_sbusdma_debug_clr_write(val,&cmicx->cmc0.sbus_dma[2]); 1190 } 1191 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_address_lo_read) 1192 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_address_lo_write) 1193 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_address_hi_read) 1194 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_address_hi_write) 1195 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_control_read) 1196 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_sbusdma_eccerr_control_write) 1197 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_iter_count_read, cmicx->cmc0.sbus_dma[2].iter_count) 1198 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_iter_count_write) 1199 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch2_timer_read, cmicx->cmc0.sbus_dma[2].timer) 1200 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_sbusdma_ch2_timer_write, cmicx->cmc0.sbus_dma[2].timer) 1201 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch2_tm_control_0_read) 1202 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_tm_control_0_write) 1203 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch2_tm_control_1_read) 1204 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_tm_control_1_write) 1205 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch2_tm_control_2_read) 1206 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch2_tm_control_2_write) 1207 1208 1209 /* cmc0, sbus dma ch3 */ 1210 bool cmic_cmc0_sbusdma_ch3_control_read(reg_t *val) { 1211 return cmic_sbusdma_control_read(val,&cmicx->cmc0.sbus_dma[3]); 1212 } 1213 bool cmic_cmc0_sbusdma_ch3_control_write(reg_t val) { 1214 return cmic_sbusdma_control_write(val,&cmicx->cmc0.sbus_dma[3]); 1215 } 1216 bool cmic_cmc0_sbusdma_ch3_request_read(reg_t *val) { 1217 return cmic_sbusdma_request_read(val,&cmicx->cmc0.sbus_dma[3]); 1218 } 1219 bool cmic_cmc0_sbusdma_ch3_request_write(reg_t val) { 1220 return cmic_sbusdma_request_write(val,&cmicx->cmc0.sbus_dma[3]); 1221 } 1222 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_count_read, cmicx->cmc0.sbus_dma[3].cur_count ) 1223 bool cmic_cmc0_sbusdma_ch3_count_write(reg_t val) { 1224 return cmic_sbusdma_count_write(val,&cmicx->cmc0.sbus_dma[3]); 1225 } 1226 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_opcode_read, cmicx->cmc0.sbus_dma[3].opcode ) 1227 bool cmic_cmc0_sbusdma_ch3_opcode_write(reg_t val) { 1228 return cmic_sbusdma_opcode_write(val,&cmicx->cmc0.sbus_dma[3]); 1229 } 1230 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_sbus_start_address_read, cmicx->cmc0.sbus_dma[3].cur_sbus_address ) 1231 bool cmic_cmc0_sbusdma_ch3_sbus_start_address_write(reg_t val) { 1232 return cmic_sbusdma_sbus_start_address_write(val,&cmicx->cmc0.sbus_dma[3]); 1233 } 1234 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[3].cur_hostmem_address)) 1235 bool cmic_cmc0_sbusdma_ch3_hostmem_start_address_lo_write(reg_t val) { 1236 return cmic_sbusdma_hostmem_start_address_lo_write(val,&cmicx->cmc0.sbus_dma[3]); 1237 } 1238 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[3].cur_hostmem_address)) 1239 bool cmic_cmc0_sbusdma_ch3_hostmem_start_address_hi_write(reg_t val) { 1240 return cmic_sbusdma_hostmem_start_address_hi_write(val,&cmicx->cmc0.sbus_dma[3]); 1241 } 1242 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_desc_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[3].cur_desc_address) ) 1243 bool cmic_cmc0_sbusdma_ch3_desc_start_address_lo_write(reg_t val) { 1244 return cmic_sbusdma_desc_start_address_lo_write(val,&cmicx->cmc0.sbus_dma[3]); 1245 } 1246 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_desc_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[3].cur_desc_address) ) 1247 bool cmic_cmc0_sbusdma_ch3_desc_start_address_hi_write(reg_t val) { 1248 return cmic_sbusdma_desc_start_address_hi_write(val,&cmicx->cmc0.sbus_dma[3]); 1249 } 1250 bool cmic_cmc0_sbusdma_ch3_status_read(reg_t *val) { 1251 return cmic_sbusdma_status_read(val,&cmicx->cmc0.sbus_dma[3]); 1252 } 1253 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_status_write) 1254 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_hostmem_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[3].cur_hostmem_address)) 1255 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_hostmem_address_lo_write) 1256 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_hostmem_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[3].cur_hostmem_address)) 1257 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_hostmem_address_hi_write) 1258 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_sbus_address_read, cmicx->cmc0.sbus_dma[3].cur_sbus_address) 1259 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_sbus_address_write) 1260 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_desc_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[3].cur_desc_address)) 1261 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_desc_address_lo_write) 1262 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_desc_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[3].cur_desc_address)) 1263 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_desc_address_hi_write) 1264 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_request_read, cmicx->cmc0.sbus_dma[3].cur_sbusdma_config_request) 1265 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_request_write) 1266 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_count_read, cmicx->cmc0.sbus_dma[3].cur_sbusdma_config_count) 1267 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_count_write) 1268 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_read, cmicx->cmc0.sbus_dma[3].cur_sbusdma_config_sbus_start_address) 1269 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_write) 1270 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.sbus_dma[3].cur_sbusdma_config_hostmem_start_address)) 1271 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_write) 1272 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.sbus_dma[3].cur_sbusdma_config_hostmem_start_address)) 1273 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_write) 1274 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_opcode_read, cmicx->cmc0.sbus_dma[3].cur_sbusdma_config_opcode) 1275 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_opcode_write) 1276 bool cmic_cmc0_sbusdma_ch3_sbusdma_debug_read(reg_t *val) { 1277 return cmic_sbusdma_debug_read(val,&cmicx->cmc0.sbus_dma[3]); 1278 } 1279 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_sbusdma_debug_write) 1280 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch3_sbusdma_debug_clr_read) 1281 bool cmic_cmc0_sbusdma_ch3_sbusdma_debug_clr_write(reg_t val) { 1282 return cmic_sbusdma_debug_clr_write(val,&cmicx->cmc0.sbus_dma[3]); 1283 } 1284 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_address_lo_read) 1285 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_address_lo_write) 1286 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_address_hi_read) 1287 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_address_hi_write) 1288 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_control_read) 1289 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_sbusdma_eccerr_control_write) 1290 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_iter_count_read, cmicx->cmc0.sbus_dma[3].iter_count) 1291 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_iter_count_write) 1292 PCID_REG_READ_FUNC_GEN( cmic_cmc0_sbusdma_ch3_timer_read, cmicx->cmc0.sbus_dma[3].timer) 1293 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_sbusdma_ch3_timer_write, cmicx->cmc0.sbus_dma[3].timer) 1294 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch3_tm_control_0_read) 1295 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_tm_control_0_write) 1296 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch3_tm_control_1_read) 1297 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_tm_control_1_write) 1298 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_sbusdma_ch3_tm_control_2_read) 1299 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc0_sbusdma_ch3_tm_control_2_write) 1300 1301 1302 /* cmc 1 shared config */ 1303 bool cmic_cmc1_shared_config_read(reg_t *val) { 1304 return cmic_sbusdma_shared_config_read(val,&cmicx->cmc1); 1305 } 1306 bool cmic_cmc1_shared_config_write(reg_t val) { 1307 return cmic_sbusdma_shared_config_write(val,&cmicx->cmc1); 1308 } 1309 1310 /* cmc 1, sbus dma ch0 */ 1311 bool cmic_cmc1_sbusdma_ch0_control_read(reg_t *val) { 1312 return cmic_sbusdma_control_read(val,&cmicx->cmc1.sbus_dma[0]); 1313 } 1314 bool cmic_cmc1_sbusdma_ch0_control_write(reg_t val) { 1315 return cmic_sbusdma_control_write(val,&cmicx->cmc1.sbus_dma[0]); 1316 } 1317 bool cmic_cmc1_sbusdma_ch0_request_read(reg_t *val) { 1318 return cmic_sbusdma_request_read(val,&cmicx->cmc1.sbus_dma[0]); 1319 } 1320 bool cmic_cmc1_sbusdma_ch0_request_write(reg_t val) { 1321 return cmic_sbusdma_request_write(val,&cmicx->cmc1.sbus_dma[0]); 1322 } 1323 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_count_read, cmicx->cmc1.sbus_dma[0].cur_count ) 1324 bool cmic_cmc1_sbusdma_ch0_count_write(reg_t val) { 1325 return cmic_sbusdma_count_write(val,&cmicx->cmc1.sbus_dma[0]); 1326 } 1327 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_opcode_read, cmicx->cmc1.sbus_dma[0].opcode ) 1328 bool cmic_cmc1_sbusdma_ch0_opcode_write(reg_t val) { 1329 return cmic_sbusdma_opcode_write(val,&cmicx->cmc1.sbus_dma[0]); 1330 } 1331 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_sbus_start_address_read, cmicx->cmc1.sbus_dma[0].cur_sbus_address ) 1332 bool cmic_cmc1_sbusdma_ch0_sbus_start_address_write(reg_t val) { 1333 return cmic_sbusdma_sbus_start_address_write(val,&cmicx->cmc1.sbus_dma[0]); 1334 } 1335 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[0].cur_hostmem_address)) 1336 bool cmic_cmc1_sbusdma_ch0_hostmem_start_address_lo_write(reg_t val) { 1337 return cmic_sbusdma_hostmem_start_address_lo_write(val,&cmicx->cmc1.sbus_dma[0]); 1338 } 1339 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[0].cur_hostmem_address)) 1340 bool cmic_cmc1_sbusdma_ch0_hostmem_start_address_hi_write(reg_t val) { 1341 return cmic_sbusdma_hostmem_start_address_hi_write(val,&cmicx->cmc1.sbus_dma[0]); 1342 } 1343 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_desc_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[0].cur_desc_address) ) 1344 bool cmic_cmc1_sbusdma_ch0_desc_start_address_lo_write(reg_t val) { 1345 return cmic_sbusdma_desc_start_address_lo_write(val,&cmicx->cmc1.sbus_dma[0]); 1346 } 1347 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_desc_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[0].cur_desc_address) ) 1348 bool cmic_cmc1_sbusdma_ch0_desc_start_address_hi_write(reg_t val) { 1349 return cmic_sbusdma_desc_start_address_hi_write(val,&cmicx->cmc1.sbus_dma[0]); 1350 } 1351 bool cmic_cmc1_sbusdma_ch0_status_read(reg_t *val) { 1352 return cmic_sbusdma_status_read(val,&cmicx->cmc1.sbus_dma[0]); 1353 } 1354 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_status_write) 1355 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_hostmem_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[0].cur_hostmem_address)) 1356 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_hostmem_address_lo_write) 1357 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_hostmem_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[0].cur_hostmem_address)) 1358 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_hostmem_address_hi_write) 1359 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_sbus_address_read, cmicx->cmc1.sbus_dma[0].cur_sbus_address) 1360 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_sbus_address_write) 1361 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_desc_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[0].cur_desc_address)) 1362 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_desc_address_lo_write) 1363 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_desc_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[0].cur_desc_address)) 1364 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_desc_address_hi_write) 1365 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_request_read, cmicx->cmc1.sbus_dma[0].cur_sbusdma_config_request) 1366 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_request_write) 1367 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_count_read, cmicx->cmc1.sbus_dma[0].cur_sbusdma_config_count) 1368 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_count_write) 1369 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_read, cmicx->cmc1.sbus_dma[0].cur_sbusdma_config_sbus_start_address) 1370 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_write) 1371 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[0].cur_sbusdma_config_hostmem_start_address)) 1372 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_write) 1373 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[0].cur_sbusdma_config_hostmem_start_address)) 1374 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_write) 1375 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_opcode_read, cmicx->cmc1.sbus_dma[0].cur_sbusdma_config_opcode) 1376 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_opcode_write) 1377 bool cmic_cmc1_sbusdma_ch0_sbusdma_debug_read(reg_t *val) { 1378 return cmic_sbusdma_debug_read(val,&cmicx->cmc1.sbus_dma[0]); 1379 } 1380 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_sbusdma_debug_write) 1381 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch0_sbusdma_debug_clr_read) 1382 bool cmic_cmc1_sbusdma_ch0_sbusdma_debug_clr_write(reg_t val) { 1383 return cmic_sbusdma_debug_clr_write(val,&cmicx->cmc1.sbus_dma[0]); 1384 } 1385 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_address_lo_read) 1386 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_address_lo_write) 1387 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_address_hi_read) 1388 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_address_hi_write) 1389 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_control_read) 1390 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_sbusdma_eccerr_control_write) 1391 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_iter_count_read, cmicx->cmc1.sbus_dma[0].iter_count) 1392 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_iter_count_write) 1393 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch0_timer_read, cmicx->cmc1.sbus_dma[0].timer) 1394 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_sbusdma_ch0_timer_write, cmicx->cmc1.sbus_dma[0].timer) 1395 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch0_tm_control_0_read) 1396 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_tm_control_0_write) 1397 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch0_tm_control_1_read) 1398 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_tm_control_1_write) 1399 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch0_tm_control_2_read) 1400 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch0_tm_control_2_write) 1401 1402 /* cmc 1, sbus dma ch1 */ 1403 bool cmic_cmc1_sbusdma_ch1_control_read(reg_t *val) { 1404 return cmic_sbusdma_control_read(val,&cmicx->cmc1.sbus_dma[1]); 1405 } 1406 bool cmic_cmc1_sbusdma_ch1_control_write(reg_t val) { 1407 return cmic_sbusdma_control_write(val,&cmicx->cmc1.sbus_dma[1]); 1408 } 1409 bool cmic_cmc1_sbusdma_ch1_request_read(reg_t *val) { 1410 return cmic_sbusdma_request_read(val,&cmicx->cmc1.sbus_dma[1]); 1411 } 1412 bool cmic_cmc1_sbusdma_ch1_request_write(reg_t val) { 1413 return cmic_sbusdma_request_write(val,&cmicx->cmc1.sbus_dma[1]); 1414 } 1415 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_count_read, cmicx->cmc1.sbus_dma[1].cur_count ) 1416 bool cmic_cmc1_sbusdma_ch1_count_write(reg_t val) { 1417 return cmic_sbusdma_count_write(val,&cmicx->cmc1.sbus_dma[1]); 1418 } 1419 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_opcode_read, cmicx->cmc1.sbus_dma[1].opcode ) 1420 bool cmic_cmc1_sbusdma_ch1_opcode_write(reg_t val) { 1421 return cmic_sbusdma_opcode_write(val,&cmicx->cmc1.sbus_dma[1]); 1422 } 1423 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_sbus_start_address_read, cmicx->cmc1.sbus_dma[1].cur_sbus_address ) 1424 bool cmic_cmc1_sbusdma_ch1_sbus_start_address_write(reg_t val) { 1425 return cmic_sbusdma_sbus_start_address_write(val,&cmicx->cmc1.sbus_dma[1]); 1426 } 1427 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[1].cur_hostmem_address)) 1428 bool cmic_cmc1_sbusdma_ch1_hostmem_start_address_lo_write(reg_t val) { 1429 return cmic_sbusdma_hostmem_start_address_lo_write(val,&cmicx->cmc1.sbus_dma[1]); 1430 } 1431 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[1].cur_hostmem_address)) 1432 bool cmic_cmc1_sbusdma_ch1_hostmem_start_address_hi_write(reg_t val) { 1433 return cmic_sbusdma_hostmem_start_address_hi_write(val,&cmicx->cmc1.sbus_dma[1]); 1434 } 1435 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_desc_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[1].cur_desc_address) ) 1436 bool cmic_cmc1_sbusdma_ch1_desc_start_address_lo_write(reg_t val) { 1437 return cmic_sbusdma_desc_start_address_lo_write(val,&cmicx->cmc1.sbus_dma[1]); 1438 } 1439 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_desc_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[1].cur_desc_address) ) 1440 bool cmic_cmc1_sbusdma_ch1_desc_start_address_hi_write(reg_t val) { 1441 return cmic_sbusdma_desc_start_address_hi_write(val,&cmicx->cmc1.sbus_dma[1]); 1442 } 1443 bool cmic_cmc1_sbusdma_ch1_status_read(reg_t *val) { 1444 return cmic_sbusdma_status_read(val,&cmicx->cmc1.sbus_dma[1]); 1445 } 1446 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_status_write) 1447 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_hostmem_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[1].cur_hostmem_address)) 1448 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_hostmem_address_lo_write) 1449 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_hostmem_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[1].cur_hostmem_address)) 1450 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_hostmem_address_hi_write) 1451 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_sbus_address_read, cmicx->cmc1.sbus_dma[1].cur_sbus_address) 1452 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_sbus_address_write) 1453 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_desc_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[1].cur_desc_address)) 1454 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_desc_address_lo_write) 1455 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_desc_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[1].cur_desc_address)) 1456 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_desc_address_hi_write) 1457 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_request_read, cmicx->cmc1.sbus_dma[1].cur_sbusdma_config_request) 1458 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_request_write) 1459 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_count_read, cmicx->cmc1.sbus_dma[1].cur_sbusdma_config_count) 1460 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_count_write) 1461 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_read, cmicx->cmc1.sbus_dma[1].cur_sbusdma_config_sbus_start_address) 1462 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_write) 1463 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[1].cur_sbusdma_config_hostmem_start_address)) 1464 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_write) 1465 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[1].cur_sbusdma_config_hostmem_start_address)) 1466 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_write) 1467 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_opcode_read, cmicx->cmc1.sbus_dma[1].cur_sbusdma_config_opcode) 1468 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_opcode_write) 1469 bool cmic_cmc1_sbusdma_ch1_sbusdma_debug_read(reg_t *val) { 1470 return cmic_sbusdma_debug_read(val,&cmicx->cmc1.sbus_dma[1]); 1471 } 1472 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_sbusdma_debug_write) 1473 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch1_sbusdma_debug_clr_read) 1474 bool cmic_cmc1_sbusdma_ch1_sbusdma_debug_clr_write(reg_t val) { 1475 return cmic_sbusdma_debug_clr_write(val,&cmicx->cmc1.sbus_dma[1]); 1476 } 1477 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_address_lo_read) 1478 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_address_lo_write) 1479 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_address_hi_read) 1480 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_address_hi_write) 1481 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_control_read) 1482 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_sbusdma_eccerr_control_write) 1483 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_iter_count_read, cmicx->cmc1.sbus_dma[1].iter_count) 1484 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_iter_count_write) 1485 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch1_timer_read, cmicx->cmc1.sbus_dma[1].timer) 1486 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_sbusdma_ch1_timer_write, cmicx->cmc1.sbus_dma[1].timer) 1487 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch1_tm_control_0_read) 1488 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_tm_control_0_write) 1489 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch1_tm_control_1_read) 1490 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_tm_control_1_write) 1491 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch1_tm_control_2_read) 1492 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch1_tm_control_2_write) 1493 1494 /* cmc1, sbus dma ch2 */ 1495 bool cmic_cmc1_sbusdma_ch2_control_read(reg_t *val) { 1496 return cmic_sbusdma_control_read(val,&cmicx->cmc1.sbus_dma[2]); 1497 } 1498 bool cmic_cmc1_sbusdma_ch2_control_write(reg_t val) { 1499 return cmic_sbusdma_control_write(val,&cmicx->cmc1.sbus_dma[2]); 1500 } 1501 bool cmic_cmc1_sbusdma_ch2_request_read(reg_t *val) { 1502 return cmic_sbusdma_request_read(val,&cmicx->cmc1.sbus_dma[2]); 1503 } 1504 bool cmic_cmc1_sbusdma_ch2_request_write(reg_t val) { 1505 return cmic_sbusdma_request_write(val,&cmicx->cmc1.sbus_dma[2]); 1506 } 1507 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_count_read, cmicx->cmc1.sbus_dma[2].cur_count ) 1508 bool cmic_cmc1_sbusdma_ch2_count_write(reg_t val) { 1509 return cmic_sbusdma_count_write(val,&cmicx->cmc1.sbus_dma[2]); 1510 } 1511 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_opcode_read, cmicx->cmc1.sbus_dma[2].opcode ) 1512 bool cmic_cmc1_sbusdma_ch2_opcode_write(reg_t val) { 1513 return cmic_sbusdma_opcode_write(val,&cmicx->cmc1.sbus_dma[2]); 1514 } 1515 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_sbus_start_address_read, cmicx->cmc1.sbus_dma[2].cur_sbus_address ) 1516 bool cmic_cmc1_sbusdma_ch2_sbus_start_address_write(reg_t val) { 1517 return cmic_sbusdma_sbus_start_address_write(val,&cmicx->cmc1.sbus_dma[2]); 1518 } 1519 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[2].cur_hostmem_address)) 1520 bool cmic_cmc1_sbusdma_ch2_hostmem_start_address_lo_write(reg_t val) { 1521 return cmic_sbusdma_hostmem_start_address_lo_write(val,&cmicx->cmc1.sbus_dma[2]); 1522 } 1523 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[2].cur_hostmem_address)) 1524 bool cmic_cmc1_sbusdma_ch2_hostmem_start_address_hi_write(reg_t val) { 1525 return cmic_sbusdma_hostmem_start_address_hi_write(val,&cmicx->cmc1.sbus_dma[2]); 1526 } 1527 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_desc_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[2].cur_desc_address) ) 1528 bool cmic_cmc1_sbusdma_ch2_desc_start_address_lo_write(reg_t val) { 1529 return cmic_sbusdma_desc_start_address_lo_write(val,&cmicx->cmc1.sbus_dma[2]); 1530 } 1531 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_desc_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[2].cur_desc_address) ) 1532 bool cmic_cmc1_sbusdma_ch2_desc_start_address_hi_write(reg_t val) { 1533 return cmic_sbusdma_desc_start_address_hi_write(val,&cmicx->cmc1.sbus_dma[2]); 1534 } 1535 bool cmic_cmc1_sbusdma_ch2_status_read(reg_t *val) { 1536 return cmic_sbusdma_status_read(val,&cmicx->cmc1.sbus_dma[2]); 1537 } 1538 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_status_write) 1539 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_hostmem_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[2].cur_hostmem_address)) 1540 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_hostmem_address_lo_write) 1541 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_hostmem_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[2].cur_hostmem_address)) 1542 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_hostmem_address_hi_write) 1543 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_sbus_address_read, cmicx->cmc1.sbus_dma[2].cur_sbus_address) 1544 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_sbus_address_write) 1545 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_desc_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[2].cur_desc_address)) 1546 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_desc_address_lo_write) 1547 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_desc_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[2].cur_desc_address)) 1548 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_desc_address_hi_write) 1549 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_request_read, cmicx->cmc1.sbus_dma[2].cur_sbusdma_config_request) 1550 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_request_write) 1551 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_count_read, cmicx->cmc1.sbus_dma[2].cur_sbusdma_config_count) 1552 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_count_write) 1553 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_read, cmicx->cmc1.sbus_dma[2].cur_sbusdma_config_sbus_start_address) 1554 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_write) 1555 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[2].cur_sbusdma_config_hostmem_start_address)) 1556 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_write) 1557 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[2].cur_sbusdma_config_hostmem_start_address)) 1558 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_write) 1559 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_opcode_read, cmicx->cmc1.sbus_dma[2].cur_sbusdma_config_opcode) 1560 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_opcode_write) 1561 bool cmic_cmc1_sbusdma_ch2_sbusdma_debug_read(reg_t *val) { 1562 return cmic_sbusdma_debug_read(val,&cmicx->cmc1.sbus_dma[2]); 1563 } 1564 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_sbusdma_debug_write) 1565 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch2_sbusdma_debug_clr_read) 1566 bool cmic_cmc1_sbusdma_ch2_sbusdma_debug_clr_write(reg_t val) { 1567 return cmic_sbusdma_debug_clr_write(val,&cmicx->cmc1.sbus_dma[2]); 1568 } 1569 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_address_lo_read) 1570 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_address_lo_write) 1571 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_address_hi_read) 1572 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_address_hi_write) 1573 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_control_read) 1574 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_sbusdma_eccerr_control_write) 1575 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_iter_count_read, cmicx->cmc1.sbus_dma[2].iter_count) 1576 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_iter_count_write) 1577 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch2_timer_read, cmicx->cmc1.sbus_dma[2].timer) 1578 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_sbusdma_ch2_timer_write, cmicx->cmc1.sbus_dma[2].timer) 1579 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch2_tm_control_0_read) 1580 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_tm_control_0_write) 1581 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch2_tm_control_1_read) 1582 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_tm_control_1_write) 1583 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch2_tm_control_2_read) 1584 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch2_tm_control_2_write) 1585 1586 /* cmc1, sbus dma ch3 */ 1587 bool cmic_cmc1_sbusdma_ch3_control_read(reg_t *val) { 1588 return cmic_sbusdma_control_read(val,&cmicx->cmc1.sbus_dma[3]); 1589 } 1590 bool cmic_cmc1_sbusdma_ch3_control_write(reg_t val) { 1591 return cmic_sbusdma_control_write(val,&cmicx->cmc1.sbus_dma[3]); 1592 } 1593 bool cmic_cmc1_sbusdma_ch3_request_read(reg_t *val) { 1594 return cmic_sbusdma_request_read(val,&cmicx->cmc1.sbus_dma[3]); 1595 } 1596 bool cmic_cmc1_sbusdma_ch3_request_write(reg_t val) { 1597 return cmic_sbusdma_request_write(val,&cmicx->cmc1.sbus_dma[3]); 1598 } 1599 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_count_read, cmicx->cmc1.sbus_dma[3].cur_count ) 1600 bool cmic_cmc1_sbusdma_ch3_count_write(reg_t val) { 1601 return cmic_sbusdma_count_write(val,&cmicx->cmc1.sbus_dma[3]); 1602 } 1603 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_opcode_read, cmicx->cmc1.sbus_dma[3].opcode ) 1604 bool cmic_cmc1_sbusdma_ch3_opcode_write(reg_t val) { 1605 return cmic_sbusdma_opcode_write(val,&cmicx->cmc1.sbus_dma[3]); 1606 } 1607 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_sbus_start_address_read, cmicx->cmc1.sbus_dma[3].cur_sbus_address ) 1608 bool cmic_cmc1_sbusdma_ch3_sbus_start_address_write(reg_t val) { 1609 return cmic_sbusdma_sbus_start_address_write(val,&cmicx->cmc1.sbus_dma[3]); 1610 } 1611 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[3].cur_hostmem_address)) 1612 bool cmic_cmc1_sbusdma_ch3_hostmem_start_address_lo_write(reg_t val) { 1613 return cmic_sbusdma_hostmem_start_address_lo_write(val,&cmicx->cmc1.sbus_dma[3]); 1614 } 1615 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[3].cur_hostmem_address)) 1616 bool cmic_cmc1_sbusdma_ch3_hostmem_start_address_hi_write(reg_t val) { 1617 return cmic_sbusdma_hostmem_start_address_hi_write(val,&cmicx->cmc1.sbus_dma[3]); 1618 } 1619 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_desc_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[3].cur_desc_address) ) 1620 bool cmic_cmc1_sbusdma_ch3_desc_start_address_lo_write(reg_t val) { 1621 return cmic_sbusdma_desc_start_address_lo_write(val,&cmicx->cmc1.sbus_dma[3]); 1622 } 1623 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_desc_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[3].cur_desc_address) ) 1624 bool cmic_cmc1_sbusdma_ch3_desc_start_address_hi_write(reg_t val) { 1625 return cmic_sbusdma_desc_start_address_hi_write(val,&cmicx->cmc1.sbus_dma[3]); 1626 } 1627 bool cmic_cmc1_sbusdma_ch3_status_read(reg_t *val) { 1628 return cmic_sbusdma_status_read(val,&cmicx->cmc1.sbus_dma[3]); 1629 } 1630 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_status_write) 1631 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_hostmem_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[3].cur_hostmem_address)) 1632 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_hostmem_address_lo_write) 1633 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_hostmem_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[3].cur_hostmem_address)) 1634 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_hostmem_address_hi_write) 1635 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_sbus_address_read, cmicx->cmc1.sbus_dma[3].cur_sbus_address) 1636 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_sbus_address_write) 1637 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_desc_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[3].cur_desc_address)) 1638 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_desc_address_lo_write) 1639 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_desc_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[3].cur_desc_address)) 1640 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_desc_address_hi_write) 1641 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_request_read, cmicx->cmc1.sbus_dma[3].cur_sbusdma_config_request) 1642 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_request_write) 1643 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_count_read, cmicx->cmc1.sbus_dma[3].cur_sbusdma_config_count) 1644 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_count_write) 1645 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_read, cmicx->cmc1.sbus_dma[3].cur_sbusdma_config_sbus_start_address) 1646 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_write) 1647 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.sbus_dma[3].cur_sbusdma_config_hostmem_start_address)) 1648 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_write) 1649 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.sbus_dma[3].cur_sbusdma_config_hostmem_start_address)) 1650 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_write) 1651 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_opcode_read, cmicx->cmc1.sbus_dma[3].cur_sbusdma_config_opcode) 1652 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_opcode_write) 1653 bool cmic_cmc1_sbusdma_ch3_sbusdma_debug_read(reg_t *val) { 1654 return cmic_sbusdma_debug_read(val,&cmicx->cmc1.sbus_dma[3]); 1655 } 1656 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_sbusdma_debug_write) 1657 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch3_sbusdma_debug_clr_read) 1658 bool cmic_cmc1_sbusdma_ch3_sbusdma_debug_clr_write(reg_t val) { 1659 return cmic_sbusdma_debug_clr_write(val,&cmicx->cmc1.sbus_dma[3]); 1660 } 1661 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_address_lo_read) 1662 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_address_lo_write) 1663 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_address_hi_read) 1664 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_address_hi_write) 1665 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_control_read) 1666 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_sbusdma_eccerr_control_write) 1667 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_iter_count_read, cmicx->cmc1.sbus_dma[3].iter_count) 1668 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_iter_count_write) 1669 PCID_REG_READ_FUNC_GEN( cmic_cmc1_sbusdma_ch3_timer_read, cmicx->cmc1.sbus_dma[3].timer) 1670 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_sbusdma_ch3_timer_write, cmicx->cmc1.sbus_dma[3].timer) 1671 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch3_tm_control_0_read) 1672 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_tm_control_0_write) 1673 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch3_tm_control_1_read) 1674 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_tm_control_1_write) 1675 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_sbusdma_ch3_tm_control_2_read) 1676 PCID_REG_WRITE_NULL_FUNC_GEN(cmic_cmc1_sbusdma_ch3_tm_control_2_write) 1677