cmicx_sim_packet_dma.c (134480B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 8 9 /* 10 * cmicx_packet_dma.c 11 * 12 * contains implementation of packet dma register access functions, as well as helper functions, update functions, and init functions for packet dma. 13 */ 14 15 16 /* includes */ 17 #include <stdio.h> 18 #include <string.h> 19 #ifndef CMICX_STANDALONE_SIM 20 #include <../systems/sim/pcid/cmicx_sim.h> 21 #include <../systems/sim/pcid/cmicx_sim_pcid.h> 22 #include <../systems/sim/pcid/cmicx_sim_schan.h> 23 #include <../systems/sim/pcid/cmicx_sim_packet_dma.h> 24 #else 25 #include "cmicx_sim.h" 26 #include "cmicx_sim_pcid.h" 27 #include "cmicx_sim_schan.h" 28 #include "cmicx_sim_packet_dma.h" 29 #endif 30 31 /* external cmicx global structure pointer */ 32 extern cmicx_t *cmicx; 33 34 /* global files for input/output of packets and global buffer data for storing packets */ 35 static FILE *cmicx_packet_dma_ip_file; 36 static FILE *cmicx_packet_dma_ep_file; 37 static FILE *cmicx_packet_dma_loopback_write_file; 38 static FILE *cmicx_packet_dma_loopback_read_file; 39 static unsigned char packet_data_buffer[CMIC_PACKET_DMA_PACKET_DATA_BUFFER_SIZE]; 40 static int current_buffer_index; 41 static int packet_cos; 42 43 44 /**********************************************************************/ 45 /* packet dma support functions. update, init, start access, abort, etc */ 46 /**********************************************************************/ 47 48 /* global packet dma init function. note the ep file name and ip file name. this function takes care of opening the files for */ 49 /* packet input and output into the cmicx through the packet dma hardware (among other global packet dma things). */ 50 bool cmicx_packet_dma_global_init(char *ip_file_name,char *ep_file_name,char *loopback_file_name) { 51 52 /* open the log file for packet output from the packet dma through tx, and packet input to the packet dma through rx. */ 53 /* these files correspond to the ingress and egress ports of the switch chip, respectively, and can be the same file. */ 54 /* in this case, it would constitute a loopback of the packet data from the tx packet port of the cmicx to the rx packet port. */ 55 cmicx_packet_dma_ip_file = fopen(ip_file_name,"a"); 56 cmicx_packet_dma_ep_file = fopen(ep_file_name,"r"); 57 cmicx_packet_dma_loopback_write_file = fopen(loopback_file_name,"a"); 58 cmicx_packet_dma_loopback_read_file = fopen(loopback_file_name,"r"); 59 if ((cmicx_packet_dma_ip_file==NULL) || (cmicx_packet_dma_ep_file==NULL) || (cmicx_packet_dma_loopback_write_file==NULL) || (cmicx_packet_dma_loopback_read_file==NULL)) { 60 return false; 61 } 62 return true; 63 64 } 65 66 67 /* init function for individual packet dma channel */ 68 bool cmicx_packet_dma_init(cmicx_packet_dma_data_t *packet_dma_data,char *id_string,int channel_number) 69 { 70 int i; 71 72 /* if the given id string is too long, log an error and quit */ 73 if ((strlen(id_string)+1)>CMIC_PACKET_DMA_ID_STRING_LENGTH) { 74 cmicx_error("ERROR: given id string \""); 75 cmicx_error(id_string); 76 cmicx_error("\" for packet dma unit is too long.\n"); 77 return false; 78 } 79 80 /* copy the id string and channel number to the storage for the schan */ 81 strcpy(packet_dma_data->id_string,id_string); 82 packet_dma_data->channel_number = channel_number; 83 84 /* control register values */ 85 packet_dma_data->ctrl_direction = false; 86 packet_dma_data->ctrl_dma_en = false; 87 packet_dma_data->ctrl_abort_dma = false; 88 packet_dma_data->ctrl_pktdma_endianness = false; 89 packet_dma_data->ctrl_desc_endianness = false; 90 packet_dma_data->ctrl_drop_rx_pkt_on_chain_end = false; 91 packet_dma_data->ctrl_rld_sts_upd_dis = false; 92 packet_dma_data->ctrl_desc_done_intr_mode = false; 93 packet_dma_data->ctrl_enable_continuous_dma = false; 94 packet_dma_data->ctrl_contiguous_descriptors = false; 95 packet_dma_data->ctrl_ep_to_cpu_header_size_dwords = 14; 96 packet_dma_data->ctrl_ep_to_cpu_alignment_bytes = 0; 97 packet_dma_data->ctrl_ep_to_cpu_header_endianness = false; 98 99 /* internal control values */ 100 packet_dma_data->last_desc = false; /* indicates the last descriptor in a descriptor stream */ 101 packet_dma_data->last_packet_chunk = false; /* indicates that we are dealing with the last chunk in a packet. we either start a new packet or end access after this. */ 102 packet_dma_data->packet_chunk_countdown = 0; /* holds the current countdown for completing the transfer of this packet chunk. when this reaches 0, the chunk is marked as complete. */ 103 packet_dma_data->chain_pending = false; /* indicates that we are still chaining descriptors, regardless of whether we are mid-packet or mid-packet-chunk or not */ 104 packet_dma_data->waiting_on_packet = false; /* indicates whether this channel is currently waiting for valid packet data or not (used in the rx case). */ 105 packet_dma_data->header_bytes_remaining = 0; /* indicates the number of bytes left in the header of a packet, before the header is fully transferred. */ 106 107 /* interrupt coalescing values */ 108 packet_dma_data->intr_coal_enable = false; 109 packet_dma_data->intr_coal_count = 0; 110 packet_dma_data->intr_coal_timer = 0; 111 packet_dma_data->intr_coal_cur_timer = 0; 112 packet_dma_data->intr_coal_cur_desc_done_count = 0; 113 packet_dma_data->intr_coal_cur_chain_done_count = 0; 114 115 /* stat register values */ 116 packet_dma_data->stat_ch_in_halt = false; 117 packet_dma_data->stat_pktwr_ecc_err = false; 118 packet_dma_data->stat_descrd_addr_decode_err = false; 119 packet_dma_data->stat_pktwrrd_addr_decode_err = false; 120 packet_dma_data->stat_stwt_addr_decode_err = false; 121 packet_dma_data->stat_dma_active = false; 122 packet_dma_data->stat_chain_done = false; 123 packet_dma_data->irq_stat_desc_done = false; 124 packet_dma_data->irq_stat_chain_done = false; 125 packet_dma_data->irq_stat_intr_coalescing_intr = false; 126 packet_dma_data->irq_stat_desc_controlled_intr = false; 127 128 /* cos control register values */ 129 for (i=0; i<CMIC_PACKET_DMA_COS_COUNT; i++) { 130 packet_dma_data->cos_ctrl_bmp[i] = false; 131 } 132 133 /* pkt count register values */ 134 packet_dma_data->txpkt_count = 0; 135 packet_dma_data->rxpkt_count = 0; 136 137 /* descriptor address values */ 138 packet_dma_data->desc_addr = 0x0; 139 packet_dma_data->desc_halt_addr = 0x0; 140 packet_dma_data->cur_desc_addr = 0x0; 141 142 /* values garnered from descriptors */ 143 packet_dma_data->packet_mem_addr = 0x0; 144 packet_dma_data->desc_byte_count = 0; 145 packet_dma_data->desc_reload = false; 146 packet_dma_data->desc_higig_pkt = false; 147 packet_dma_data->desc_purge_packet = false; 148 packet_dma_data->desc_interrupt = 0; 149 packet_dma_data->desc_descriptors_remaining = 0; 150 packet_dma_data->desc_packet_bytes_transferred = 0; 151 packet_dma_data->desc_packet_end_bit = false; 152 packet_dma_data->desc_packet_start_bit = false; 153 packet_dma_data->desc_packet_cell_error_bit = false; 154 packet_dma_data->desc_packet_data_read_ecc_error_bit = false; 155 packet_dma_data->desc_packet_completion_error_bit = false; 156 packet_dma_data->desc_packet_done_bit = false; 157 158 /* storage for buffered packet data on this channel */ 159 packet_dma_data->current_buffer_index = 0; 160 packet_dma_data->current_buffer_read_index = 0; 161 162 163 /* successful initialization complete */ 164 cmicx_log("successfully init'd \""); 165 cmicx_log(packet_dma_data->id_string); 166 cmicx_log("\"."); 167 cmicx_log_newline(); 168 return true; 169 170 } 171 172 173 /* global packet dma update function. the main purpose of this function is to read in rx packets from the EP input file. */ 174 /* from there, these packets are fed to individual packet dma channels performing Rx. */ 175 bool cmicx_packet_dma_global_update(void) { 176 177 int i; 178 int num_bytes; 179 unsigned temp_val; 180 int return_value; 181 bool need_transfer = false; 182 bool transfer_blocked = false; 183 FILE *input_file; 184 bool cmc0_packet_dma_need_transfer[CMICX_NUM_PACKET_DMA_PER_CMC]; 185 bool cmc1_packet_dma_need_transfer[CMICX_NUM_PACKET_DMA_PER_CMC]; 186 187 /* set default values for "need transfer" bits. */ 188 for (i=0; i<CMICX_NUM_PACKET_DMA_PER_CMC; i++) { 189 cmc0_packet_dma_need_transfer[i] = false; 190 cmc1_packet_dma_need_transfer[i] = false; 191 } 192 193 cmicx_log_level_set(0); 194 cmicx_log("packet dma global update... "); 195 cmicx_log_level_set(3); 196 197 /* if we can get a new packet because the global packet buffer is currently empty, then do it. */ 198 if (current_buffer_index==0) { 199 200 /* if we have loopback enabled, we need to read in from the loopback file. */ 201 if (cmicx->ip_2_ep_loopback_enable==true) { 202 input_file = cmicx_packet_dma_loopback_read_file; 203 } 204 else { 205 input_file = cmicx_packet_dma_ep_file; 206 } 207 208 /* make sure that we can read from the file. */ 209 if (input_file==NULL) { 210 /* this error (below) is going to be masked, because it is a pretty common case (didn't create the input packet file), especially when utilizing hardware loopback. */ 211 /* 212 cmicx_log("ERROR: cannot read from packet input file. "); 213 cmicx_log_newline(); 214 return false; 215 */ 216 return true; 217 } 218 219 /* read the packet header, and simultaneously ensure that it is in the right format. */ 220 return_value = fscanf(input_file," [packet] bytes: %d COS: %d ",&num_bytes,&packet_cos); 221 222 /* check if we've hit the end of file, without reading anything. if we have at this point, then we simply don't have any data available to read. move on. */ 223 if (return_value==EOF) { 224 return true; 225 } 226 227 /* check for the error case (header not in the format we wanted, or we unexpectedly hit EOF. this is an unrecoverable error. */ 228 if ((return_value!=2) || (ferror(input_file)!=0) || (feof(input_file)!=0)) { 229 cmicx_log("error: error reading packet header from packet input file into packet dma."); 230 cmicx_log_newline(); 231 cmicx_error("error: error reading packet header from packet input file into packet dma.\n"); 232 return false; 233 } 234 235 /* check that we will not try to load too many bytes into the buffer. */ 236 if (num_bytes>CMIC_PACKET_DMA_PACKET_DATA_BUFFER_SIZE) { 237 cmicx_log("error: too many bytes in input packet at ep interface. would overflow global packet data buffer if read."); 238 cmicx_log_newline(); 239 cmicx_error("error: too many bytes in input packet at ep interface. would overflow global packet data buffer if read.\n"); 240 return false; 241 } 242 243 /* If the num_bytes is greater than the check above, we exit */ 244 /* read the actual packet data, byte-by-byte, into the packet data buffer. */ 245 /* coverity[tainted_data : FALSE] */ 246 for (i=0; i<num_bytes; i++) { 247 248 /* read a byte, and then make sure we have read correctly. */ 249 return_value = fscanf(input_file,"%02X",&temp_val); 250 packet_data_buffer[current_buffer_index] = (unsigned char)temp_val; 251 if ((return_value!=1) || (ferror(input_file)!=0) || (feof(input_file)!=0)) { 252 cmicx_log("error: error reading packet data from packet input file for packet dma."); 253 cmicx_log_newline(); 254 cmicx_error("error: error reading packet data from packet input file for packet dma.\n"); 255 return false; 256 } 257 current_buffer_index++; 258 259 /* check for end-of-packet, if we expect it. */ 260 if (i==(num_bytes-1)) { 261 /* Error values are checked below */ 262 /* coverity[check_return] */ 263 fscanf(input_file," [/packet]"); 264 if ((ferror(input_file)!=0) || (feof(input_file)!=0)) { 265 cmicx_log("error: error reading packet data from packet input file for packet dma. packet did not end when expected."); 266 cmicx_log_newline(); 267 cmicx_error("error: error reading packet data from packet input file for packet dma. packet did not end when expected.\n"); 268 return false; 269 } 270 } 271 272 /* just the common in-between byte case. this covers end-of-lines in between packet bytes and also spaces in between packet bytes on the same line. */ 273 else { 274 /* Error values are checked below */ 275 /* coverity[check_return] */ 276 fscanf(input_file," "); 277 if ((ferror(input_file)!=0) || (feof(input_file)!=0)) { 278 cmicx_log("error: error reading packet data from packet input file for packet dma. packet not in the correct format (somehow)."); 279 cmicx_log_newline(); 280 cmicx_error("error: error reading packet data from packet input file for packet dma. packet not in the correct format (somehow).\n"); 281 return false; 282 } 283 } 284 285 } 286 287 /* at this point, we have successfully read a full packet into the global buffer */ 288 cmicx_log("global packet dma update: full packet read from input file."); 289 cmicx_log_newline(); 290 } 291 292 /* set default values for "need transfer" bits. */ 293 need_transfer = false; 294 transfer_blocked = false; 295 for (i=0; i<CMICX_NUM_PACKET_DMA_PER_CMC; i++) { 296 cmc0_packet_dma_need_transfer[i] = false; 297 cmc1_packet_dma_need_transfer[i] = false; 298 } 299 300 /* if the packet buffer is not currently empty, then we have a packet there. distribute it to the appropriate packet dma channels for rx (if we can). */ 301 /* note that this operation is atomic - a packet will either get distributed to all the appropriate channels at once and the global buffer will be freed up, or it won't. */ 302 if (current_buffer_index!=0) { 303 304 /* go through each packet dma channel, and see if 1) the channel is active, 2) the channel is in rx mode 3) the channel is accepting packets */ 305 /* with the class of service we currently have available. if all of these conditions are true, then we need to disburse the currently global packet to this channel. */ 306 for (i=0; i<CMICX_NUM_PACKET_DMA_PER_CMC; i++) { 307 308 if ((cmicx->cmc0.packet_dma[i].ctrl_dma_en==true) && 309 (cmicx->cmc0.packet_dma[i].ctrl_direction==false) && 310 (cmicx->cmc0.packet_dma[i].cos_ctrl_bmp[packet_cos]==true) && 311 ((cmicx->cmc0.packet_dma[i].chain_pending==true) || (cmicx->cmc0.packet_dma[i].ctrl_drop_rx_pkt_on_chain_end==false))) { 312 313 need_transfer = true; 314 cmc0_packet_dma_need_transfer[i] = true; 315 if (cmicx->cmc0.packet_dma[i].current_buffer_index!=0) { 316 transfer_blocked = true; 317 break; 318 } 319 320 } 321 322 if ((cmicx->cmc1.packet_dma[i].ctrl_dma_en==true) && 323 (cmicx->cmc1.packet_dma[i].ctrl_direction==false) && 324 (cmicx->cmc1.packet_dma[i].cos_ctrl_bmp[packet_cos]==true) && 325 ((cmicx->cmc1.packet_dma[i].chain_pending==true) || (cmicx->cmc1.packet_dma[i].ctrl_drop_rx_pkt_on_chain_end==false))) { 326 327 need_transfer = true; 328 cmc1_packet_dma_need_transfer[i] = true; 329 if (cmicx->cmc1.packet_dma[i].current_buffer_index!=0) { 330 transfer_blocked = true; 331 break; 332 } 333 334 } 335 336 } 337 338 /* complete the transfer of the packet in the global buffer to all necessary packet dma channels, if we can. otherwise, the packet will sit in the global buffer */ 339 if ((need_transfer==true) && (transfer_blocked==false)) { 340 341 for (i=0; i<CMICX_NUM_PACKET_DMA_PER_CMC; i++) { 342 343 if (cmc0_packet_dma_need_transfer[i]==true) { 344 memcpy((void *)cmicx->cmc0.packet_dma[i].packet_data_buffer,(void *)packet_data_buffer,current_buffer_index); 345 cmicx->cmc0.packet_dma[i].current_buffer_index = current_buffer_index; 346 cmicx->cmc0.packet_dma[i].current_buffer_read_index = 0; 347 } 348 if (cmc1_packet_dma_need_transfer[i]==true) { 349 memcpy((void *)cmicx->cmc1.packet_dma[i].packet_data_buffer,(void *)packet_data_buffer,current_buffer_index); 350 cmicx->cmc1.packet_dma[i].current_buffer_index = current_buffer_index; 351 cmicx->cmc1.packet_dma[i].current_buffer_read_index = 0; 352 } 353 354 } 355 356 current_buffer_index = 0; 357 358 } 359 360 361 } 362 363 /* successful global packet dma update */ 364 cmicx_log_level_set(0); 365 cmicx_log(" ...done."); 366 cmicx_log_newline(); 367 cmicx_log_level_set(3); 368 return true; 369 370 } 371 372 373 /* update function for individual packet dma channels */ 374 /* 375 * steps for updating a packet dma: 376 * 1) check if a chain is currently pending. if so, then move to step 2. if not, then we are done. 377 * 2) if we are in halt mode currently, then check if the halt address has been updated and no longer matches the current descriptor address. 378 * if so, then exit halt mode and continue on with step 3. if not, then we are done. 379 * 3) check if we are not currently working on a packet chunk (descriptor). if so, then we do a request for a new descriptor, and start a new packet chunk (countdown and all) 380 * 4) once we reach the end of a packet chunk countdown, then we can complete the chunk, and perform tx and rx specific tasks (dma'ing, etc). 381 * 5) if we've reached the end of a packet, then we can transfer an entire packet to the IP interface in the case of tx. 382 * 5) if we are on the last descriptor (and hence also the last packet chunk/at the end of a packet), then we can end the packet dma chain. 383 */ 384 bool cmicx_packet_dma_update(pcid_info_t *pcid_info, cmicx_packet_dma_data_t *packet_dma_data) { 385 386 bool chain = false; 387 bool scatter = false; 388 bool gather = false; 389 bool scatter_or_gather = false; 390 reg_t mem[CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR]; /* return memory from pcid (used for desc requests) */ 391 int i; 392 int bytes_available; 393 int bytes_transferred; 394 bool end_bit; 395 bool start_bit; 396 FILE *output_file; 397 int packet_cos; 398 unsigned char temp_packet_data[CMIC_PACKET_DMA_TEMP_PACKET_DATA_SIZE]; 399 int front_diff; 400 int rear_diff; 401 int num_words; 402 int alignment_bytes; 403 int data_bytes_transferred; 404 int header_bytes_transferred; 405 406 memset((void *)temp_packet_data,0,CMIC_PACKET_DMA_TEMP_PACKET_DATA_SIZE); 407 408 /* print log messages for this schan */ 409 cmicx_log_level_set(0); 410 cmicx_log("updating \""); 411 cmicx_log(packet_dma_data->id_string); 412 cmicx_log("\"... "); 413 cmicx_log_level_set(3); 414 415 /* handle interrupts to be sent from the timer, if interrupt coalescing is enabled. */ 416 if ((packet_dma_data->intr_coal_enable==true) && (packet_dma_data->intr_coal_timer!=0)) { 417 418 packet_dma_data->intr_coal_cur_timer++; 419 420 if (packet_dma_data->intr_coal_cur_timer==packet_dma_data->intr_coal_timer) { 421 cmic_packet_dma_interrupts_post(packet_dma_data); 422 } 423 424 } 425 426 /* if we have a chain pending, then handle descriptor requesting, counter setup/decrement and packet chunk completion */ 427 /* if necessary. if we don't have a chain pending, then we just bail out of the function. */ 428 if (packet_dma_data->chain_pending==true) { 429 430 /* first, check if we are in halt mode currently. if so, we cannot proceed further (unless the addresses do not match anymore). */ 431 if (packet_dma_data->stat_ch_in_halt==true) { 432 433 if (packet_dma_data->cur_desc_addr!=packet_dma_data->desc_halt_addr) { 434 packet_dma_data->stat_ch_in_halt = false; 435 cmicx_log("\""); 436 cmicx_log(packet_dma_data->id_string); 437 cmicx_log("\" leaving halt mode. "); 438 } 439 440 } 441 442 /* if we are no longer in halt mode (or we never were). */ 443 if (packet_dma_data->stat_ch_in_halt==false) { 444 445 /* if we do not have a packet dma packet chunk (descriptor) pending, then we need to initiate a memory read at this point, to get a new descriptor (and wait for the data to come back). */ 446 if ((packet_dma_data->packet_chunk_countdown==0) && (packet_dma_data->waiting_on_packet==false)) { 447 448 /* reset the "reload" value before we start loading descriptors. */ 449 packet_dma_data->desc_reload = false; 450 451 /* we need to loop the descriptor request, because we may need to reload descriptors, necessitating a re-request */ 452 do { 453 454 /* if continuous dma mode is enabled and we have reached the halt address, then we need to go into halt mode and stop (exit early). */ 455 /* can only do this if we are allowed to update status fields (hence, we are not reloading a descriptor or the rld_sts_upd_dis bit is set to 0. */ 456 if ((packet_dma_data->ctrl_enable_continuous_dma==true) && 457 (packet_dma_data->cur_desc_addr==packet_dma_data->desc_halt_addr) && 458 ((packet_dma_data->desc_reload==false) || (packet_dma_data->ctrl_rld_sts_upd_dis==false))) { 459 460 packet_dma_data->stat_ch_in_halt = true; 461 cmicx_log("\""); 462 cmicx_log(packet_dma_data->id_string); 463 cmicx_log("\" going into halt mode on address "); 464 cmicx_log_uint64(packet_dma_data->cur_desc_addr); 465 cmicx_log(". ...done. "); 466 cmicx_log_newline(); 467 return true; 468 469 } 470 471 /* make the memory read over the pcid to get the descriptor words */ 472 cmicx_pcid_mem_read(pcid_info,packet_dma_data->cur_desc_addr,(void *)mem,CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR*CMICX_BYTES_PER_WORD); 473 cmicx_log("packet dma descriptor read from memory on \""); 474 cmicx_log(packet_dma_data->id_string); 475 cmicx_log("\", words: "); 476 for (i=0; i<CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR; i++) { 477 cmicx_log_hex(mem[i]); 478 cmicx_log(", "); 479 } 480 cmicx_log_newline(); 481 482 /* if we have little endian descriptors, reverse the bytes of the descriptor words */ 483 if (packet_dma_data->ctrl_desc_endianness==true) { 484 for (i=0; i<CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR; i++) { 485 mem[i] = cmicx_reverse_word_endianness(mem[i]); 486 } 487 } 488 489 /* descriptor dwords 0 and 1: packet memory address */ 490 UINT64_LOWER32_REFERENCE(packet_dma_data->packet_mem_addr) = mem[0]; 491 UINT64_UPPER32_REFERENCE(packet_dma_data->packet_mem_addr) = mem[1]; 492 493 /* descriptor dword 2: special descriptor control word */ 494 packet_dma_data->desc_byte_count = REG_FIELD_GET( mem[2], CMIC_PKTDMA_DESC_DWORD2_BYTE_COUNT_MSB,CMIC_PKTDMA_DESC_DWORD2_BYTE_COUNT_LSB ); 495 chain = REG_BIT_GET( mem[2], CMIC_PKTDMA_DESC_DWORD2_CHAIN_BIT ); 496 scatter = REG_BIT_GET( mem[2], CMIC_PKTDMA_DESC_DWORD2_SCATTER_BIT ); 497 gather = REG_BIT_GET( mem[2], CMIC_PKTDMA_DESC_DWORD2_GATHER_BIT ); 498 packet_dma_data->desc_reload = REG_BIT_GET( mem[2], CMIC_PKTDMA_DESC_DWORD2_RELOAD_BIT ); 499 packet_dma_data->desc_higig_pkt = REG_BIT_GET( mem[2], CMIC_PKTDMA_DESC_DWORD2_HIGIG_PKT_BIT ); 500 packet_dma_data->desc_purge_packet = REG_BIT_GET( mem[2], CMIC_PKTDMA_DESC_DWORD2_PURGE_PACKET_BIT ); 501 packet_dma_data->desc_interrupt = REG_FIELD_GET( mem[2], CMIC_PKTDMA_DESC_DWORD2_INTERRUPT_MSB,CMIC_PKTDMA_DESC_DWORD2_INTERRUPT_LSB ); 502 packet_dma_data->desc_descriptors_remaining = REG_FIELD_GET( mem[2], CMIC_PKTDMA_DESC_DWORD2_DESCRIPTORS_REMAINING_MSB,CMIC_PKTDMA_DESC_DWORD2_DESCRIPTORS_REMAINING_LSB ); 503 504 /* possible use cases, that set certain flags. taken directly from the CMICx microarchitecture on the packet dma (section 7.4.1.1.1). */ 505 scatter_or_gather = (packet_dma_data->ctrl_direction==true) ? scatter : gather; 506 if ((chain==false) && (packet_dma_data->desc_reload==false) && (scatter_or_gather==false)) { 507 packet_dma_data->last_desc = true; 508 packet_dma_data->last_packet_chunk = true; 509 } 510 if ((chain==false) && (packet_dma_data->desc_reload==false) && (scatter_or_gather==true)) { 511 cmicx_log("error: packet dma use case not supported: chain: false. reload: false. scatter/gather: true."); 512 return false; 513 } 514 if ((chain==false) && (packet_dma_data->desc_reload==true)) { 515 /* unused case for ending a chain. still performs desc reload and updates desc address, but chain necessarily ends. */ 516 packet_dma_data->last_desc = true; 517 packet_dma_data->last_packet_chunk = true; 518 } 519 if ((chain==true) && (packet_dma_data->desc_reload==false) && (scatter_or_gather==false)) { 520 packet_dma_data->last_desc = false; 521 packet_dma_data->last_packet_chunk = true; 522 } 523 if ((chain==true) && (packet_dma_data->desc_reload==false) && (scatter_or_gather==true)) { 524 packet_dma_data->last_desc = false; 525 packet_dma_data->last_packet_chunk = false; 526 } 527 if ((chain==true) && (packet_dma_data->desc_reload==true)) { 528 /* the normal reload descriptor case */ 529 packet_dma_data->last_desc = false; 530 packet_dma_data->last_packet_chunk = false; 531 } 532 533 /* update the descriptor address appropriately if necessary and we require a reload of the descriptor. */ 534 if (packet_dma_data->desc_reload==true) { 535 cmic_packet_dma_descriptor_done(pcid_info, packet_dma_data); 536 packet_dma_data->cur_desc_addr = packet_dma_data->packet_mem_addr; 537 if (packet_dma_data->last_desc==true) { 538 cmic_packet_dma_chain_done(packet_dma_data); 539 cmicx_log(" ...done. "); 540 cmicx_log_newline(); 541 return true; 542 } 543 } 544 545 } 546 while (packet_dma_data->desc_reload==true); 547 548 /* at this point, we definitely have valid data in the control values - we've just loaded a new descriptor. thus, we can start grabbing/sending a packet segment */ 549 /* described by that descriptor. this could include starting a new packet, or continuing one that we already have been working on. set variables for successfully */ 550 /* beginning a packet chunk below, and print log messages. */ 551 packet_dma_data->packet_chunk_countdown = CMIC_PACKET_DMA_ACCESS_COUNTDOWN_VALUE; 552 cmicx_log("starting to handle new packet chunk on \""); 553 cmicx_log(packet_dma_data->id_string); 554 cmicx_log("\". packet chunk length: "); 555 cmicx_log_int(packet_dma_data->desc_byte_count); 556 cmicx_log(". packet chunk address (source or destination): "); 557 cmicx_log_uint64(packet_dma_data->packet_mem_addr); 558 cmicx_log(". "); 559 cmicx_log_newline(); 560 561 } 562 563 564 /* at this point we are just updating packet chunks (descriptors) that we have pending. decrement the chunk countdown if we can, */ 565 /* until it reaches 0. once it reaches 0, then we can finish a packet chunk (a descriptor). */ 566 if (packet_dma_data->packet_chunk_countdown!=0) { 567 packet_dma_data->packet_chunk_countdown--; 568 } 569 if (packet_dma_data->packet_chunk_countdown==0) { 570 571 572 /* at this point, we can complete the packet chunk (a descriptor). */ 573 /* if we are doing a tx transmission, then we need to read the packet chunk from host memory, and write it to the local packet fifo. */ 574 if (packet_dma_data->ctrl_direction==true) { 575 576 /* make sure we don't overrun the buffer in the process of writing to it */ 577 if ((packet_dma_data->current_buffer_index+packet_dma_data->desc_byte_count)>=CMIC_PACKET_DMA_PACKET_DATA_BUFFER_SIZE) { 578 cmicx_log("error: attempting to write packet chunk past end of internal packet dma channel buffer on packet tx."); 579 return false; 580 } 581 582 /* do the dma read to a temporary buffer, because we may need to reverse word endianness. */ 583 /* note that we make our read here for 32-bit word chunks (that are aligned to 32-bit words in memory), because of the endianness issue. */ 584 front_diff = (packet_dma_data->packet_mem_addr%4); 585 rear_diff = ((packet_dma_data->desc_byte_count+front_diff)%4); 586 rear_diff = (rear_diff>0) ? (4-rear_diff) : 0; 587 num_words = (front_diff+packet_dma_data->desc_byte_count+rear_diff)/CMICX_BYTES_PER_WORD; 588 cmicx_pcid_mem_read(pcid_info,(packet_dma_data->packet_mem_addr-front_diff),(void *)temp_packet_data,(num_words*CMICX_BYTES_PER_WORD)); 589 590 /* if we need to swap packet endianness, then do it. */ 591 if (packet_dma_data->ctrl_pktdma_endianness==true) { 592 for (i=0; i<num_words; i++) { 593 *((reg_t *)&(temp_packet_data[i*CMICX_BYTES_PER_WORD])) = cmicx_reverse_word_endianness(*((reg_t *)&(temp_packet_data[i*CMICX_BYTES_PER_WORD]))); 594 } 595 } 596 597 /* finally, copy the appropriate data to the actual local packet data buffer for this channel, in preparation for transmission. */ 598 /* also, log some messages that the chunk we were working on is done. */ 599 memcpy((void *)&(packet_dma_data->packet_data_buffer[packet_dma_data->current_buffer_index]),(void *)&(temp_packet_data[front_diff]),packet_dma_data->desc_byte_count); 600 packet_dma_data->current_buffer_index += packet_dma_data->desc_byte_count; 601 cmicx_log("packet chunk completing. wrote "); 602 cmicx_log_int(packet_dma_data->desc_byte_count); 603 cmicx_log(" bytes from host memory to \""); 604 cmicx_log(packet_dma_data->id_string); 605 cmicx_log("\"'s internal packet buffer. "); 606 607 /* write the descriptor ack word for tx to memory (dword 3 of the descriptor data) */ 608 mem[3] = 0; 609 REG_FIELD_SET_TO(mem[3],CMIC_PKTDMA_DESC_DWORD3_PACKET_BYTES_TRANSFERRED_MSB,CMIC_PKTDMA_DESC_DWORD3_PACKET_BYTES_TRANSFERRED_LSB, packet_dma_data->desc_byte_count); 610 REG_BIT_SET_TO( mem[3],CMIC_PKTDMA_DESC_DWORD3_PACKET_COMPLETION_ERROR_BIT, false); 611 REG_BIT_SET_TO( mem[3],CMIC_PKTDMA_DESC_DWORD3_PACKET_DONE_BIT, true); 612 if (packet_dma_data->ctrl_desc_endianness==true) { 613 mem[3] = cmicx_reverse_word_endianness(mem[3]); 614 } 615 cmicx_pcid_mem_write(pcid_info,packet_dma_data->cur_desc_addr+((CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR-1)*CMICX_BYTES_PER_WORD),(void *)&(mem[3]),CMICX_BYTES_PER_WORD); 616 617 /* if we are done with the packet transfer (this is the last chunk), then we can send the buffer (the whole packet) */ 618 /* to the "ingress pipe" of the chip (actually file output for us), and reset the packet buffer. */ 619 if (packet_dma_data->last_packet_chunk==true) { 620 621 /* write the data to file. if we have hardware loopback enabled, we need to write to the loopback file. otherwise, the regular output file is ok. */ 622 if (cmicx->ip_2_ep_loopback_enable==true) { 623 output_file = cmicx_packet_dma_loopback_write_file; 624 /* loopback causes us to grab the cos from the packet. it comes from bits 58-63 of the packet (the last 6 bits of the 8th byte in the packet header). */ 625 /* see section 7.6.2 of the CMICx microarchitecture document for more detail. */ 626 packet_cos = (int)REG_FIELD_GET(packet_dma_data->packet_data_buffer[7],5,0); 627 } 628 else { 629 output_file = cmicx_packet_dma_ip_file; 630 packet_cos = packet_dma_data->channel_number; 631 } 632 if (output_file!=NULL) { 633 fprintf(output_file,"[packet]\n"); 634 fprintf(output_file,"bytes: %d\n",packet_dma_data->current_buffer_index); 635 fprintf(output_file,"COS: %d\n",packet_cos); 636 for (i=0; i<packet_dma_data->current_buffer_index; i++) { 637 fprintf(output_file,"%02X ",(packet_dma_data->packet_data_buffer[i] & 0xFF)); /* why is this 0xFF necessary? nothing should be sign extended (but yet it is). */ 638 if (((i%CMIC_PACKET_DMA_BYTES_PER_LINE)==(CMIC_PACKET_DMA_BYTES_PER_LINE-1)) || (i==(packet_dma_data->current_buffer_index-1))) { 639 fprintf(output_file,"\n"); 640 } 641 if (i==(packet_dma_data->current_buffer_index-1)) { 642 fprintf(output_file,"[/packet]\n"); 643 } 644 } 645 fflush(output_file); 646 } 647 648 /* log messages that we sent the packet successfully, and reset the buffer index, so it can be reused. */ 649 cmicx_log("packet on \""); 650 cmicx_log(packet_dma_data->id_string); 651 cmicx_log("\" fully dma'd. sent "); 652 cmicx_log_int(packet_dma_data->current_buffer_index); 653 cmicx_log(" byte packet out over IP interface. "); 654 packet_dma_data->current_buffer_index = 0; 655 656 } 657 658 cmicx_log_newline(); 659 660 } 661 662 663 /* for an rx transmission, write packet data from this channel's packet buffer to host memory */ 664 else { 665 666 /* see if we have data currently available in our local packet buffer. if not, we need to wait on a packet. */ 667 if (packet_dma_data->current_buffer_index==0) { 668 packet_dma_data->waiting_on_packet = true; 669 } 670 671 /* else, if we do have data available, then we can start writing this data to host memory. */ 672 else { 673 674 packet_dma_data->waiting_on_packet = false; 675 bytes_available = (packet_dma_data->current_buffer_index-packet_dma_data->current_buffer_read_index); 676 677 /* if we have no bytes available, we've already reached the end of the packet with previous descriptors, and this descriptor is just going to be skipped. */ 678 if (bytes_available==0) { 679 bytes_transferred = 0; 680 end_bit = false; 681 start_bit = false; 682 } 683 684 /* make sure we don't read more from the buffer than we currently have in the process of reading from it. */ 685 /* if we try to, then we have to mark the end of the packet, and all further descriptors (for this packet) are ignored. */ 686 else if (packet_dma_data->desc_byte_count>=bytes_available) { 687 bytes_transferred = bytes_available; 688 end_bit = true; 689 start_bit = (packet_dma_data->current_buffer_read_index==0) ? true : false; 690 } 691 692 /* if we are reading less than we have in the buffer */ 693 else { 694 bytes_transferred = packet_dma_data->desc_byte_count; 695 end_bit = false; 696 start_bit = (packet_dma_data->current_buffer_read_index==0) ? true : false; 697 } 698 699 /* do the actual dma write from the packet buffer directly to host memory (if we can). also log some messages. */ 700 if (bytes_transferred!=0) { 701 702 /* if we are starting this packet, then we need to reset the size of the header that still needs to be transferred. */ 703 if (start_bit==true) { 704 packet_dma_data->header_bytes_remaining = packet_dma_data->ctrl_ep_to_cpu_header_size_dwords*CMICX_BYTES_PER_WORD; 705 } 706 707 /* if we are transferring solely header in this descriptor (either part of the header or the whole header, but no data or alignment bytes). */ 708 if ((packet_dma_data->header_bytes_remaining!=0) && (packet_dma_data->header_bytes_remaining>=bytes_transferred)) { 709 alignment_bytes = 0; 710 header_bytes_transferred = bytes_transferred; 711 data_bytes_transferred = 0; 712 } 713 714 /* if we are transferring the remainder of the header and at least 1 byte of data with this descriptor. */ 715 else if ((packet_dma_data->header_bytes_remaining!=0) && (packet_dma_data->header_bytes_remaining<bytes_transferred)) { 716 717 /* if we have to add some space after the header, for alignment. make sure we can transfer the rest of the header, the alignment bytes, and at least one byte of data. */ 718 if ((packet_dma_data->header_bytes_remaining+packet_dma_data->ctrl_ep_to_cpu_alignment_bytes+1)<=bytes_transferred) { 719 alignment_bytes = packet_dma_data->ctrl_ep_to_cpu_alignment_bytes; 720 header_bytes_transferred = packet_dma_data->header_bytes_remaining; 721 data_bytes_transferred = (bytes_transferred-header_bytes_transferred-alignment_bytes); 722 } 723 724 /* we cannot accommodate the alignment spacing at this point even if it is specified, so leave it out. just transfer data bytes. */ 725 else { 726 alignment_bytes = 0; 727 header_bytes_transferred = packet_dma_data->header_bytes_remaining; 728 data_bytes_transferred = (bytes_transferred-header_bytes_transferred); 729 } 730 731 } 732 733 /* if we are only doing a data transfer. */ 734 else { 735 alignment_bytes = 0; 736 header_bytes_transferred = 0; 737 data_bytes_transferred = bytes_transferred; 738 } 739 740 bytes_transferred -= alignment_bytes; 741 742 743 /* ---------- do a header transfer, if applicable. ---------- */ 744 745 /* write the data to a temporary buffer first, in case we have to deal with endianness issues. */ 746 memset((void *)temp_packet_data,0,CMIC_PACKET_DMA_TEMP_PACKET_DATA_SIZE); 747 memcpy((void *)temp_packet_data,(void *)&(packet_dma_data->packet_data_buffer[packet_dma_data->current_buffer_read_index]),header_bytes_transferred); 748 packet_dma_data->current_buffer_read_index += header_bytes_transferred; 749 750 /* if we have to do an endianness swap for packet header data, then do it before writing the data to host memory. */ 751 if (packet_dma_data->ctrl_ep_to_cpu_header_endianness==true) { 752 if ((header_bytes_transferred%4)!=0) { 753 cmicx_log("ERROR: trying to swap packet header endianness for incoming packet on \""); 754 cmicx_log(packet_dma_data->id_string); 755 cmicx_log("\", but desc byte count supplied not a multiple of 4 (header packet data cannot be broken down into 32-bit chunks for endianness swapping)."); 756 cmicx_log_newline(); 757 } 758 else { 759 for (i=0; i<(header_bytes_transferred/4); i++) { 760 *((reg_t *)&(temp_packet_data[i*CMICX_BYTES_PER_WORD])) = cmicx_reverse_word_endianness(*((reg_t *)&(temp_packet_data[i*CMICX_BYTES_PER_WORD]))); 761 } 762 } 763 } 764 765 /* perform the actual write to memory (from our temporary buffer) */ 766 cmicx_pcid_mem_write(pcid_info,packet_dma_data->packet_mem_addr,(void *)temp_packet_data,header_bytes_transferred); 767 packet_dma_data->header_bytes_remaining -= header_bytes_transferred; 768 769 770 /* ---------- do a data transfer, if applicable. ---------- */ 771 772 /* perform data transfer to the temporary buffer. */ 773 memset((void *)temp_packet_data,0,CMIC_PACKET_DMA_TEMP_PACKET_DATA_SIZE); 774 memcpy((void *)temp_packet_data,(void *)&(packet_dma_data->packet_data_buffer[packet_dma_data->current_buffer_read_index]),data_bytes_transferred); 775 packet_dma_data->current_buffer_read_index += data_bytes_transferred; 776 777 /* if we have to do an endianness swap for packet data, then do it before writing the data to host memory. */ 778 if (packet_dma_data->ctrl_pktdma_endianness==true) { 779 if ((data_bytes_transferred%4)!=0) { 780 cmicx_log("ERROR: trying to swap packet data endianness for incoming packet on \""); 781 cmicx_log(packet_dma_data->id_string); 782 cmicx_log("\", but byte count supplied not a multiple of 4 (packet data cannot be broken down into 32-bit chunks for endianness swapping)."); 783 cmicx_log_newline(); 784 } 785 else { 786 for (i=0; i<(data_bytes_transferred/4); i++) { 787 *((reg_t *)&(temp_packet_data[i*CMICX_BYTES_PER_WORD])) = cmicx_reverse_word_endianness(*((reg_t *)&(temp_packet_data[i*CMICX_BYTES_PER_WORD]))); 788 } 789 } 790 } 791 792 /* perform the actual write to memory (from our temporary buffer) */ 793 cmicx_pcid_mem_write(pcid_info,(packet_dma_data->packet_mem_addr+header_bytes_transferred+alignment_bytes),(void *)temp_packet_data,data_bytes_transferred); 794 795 796 /* display output */ 797 cmicx_log("packet chunk completing. wrote "); 798 cmicx_log_int(bytes_transferred); 799 cmicx_log(" bytes of packet to host memory from \""); 800 cmicx_log(packet_dma_data->id_string); 801 cmicx_log("\"'s internal packet buffer. "); 802 803 } 804 else { 805 cmicx_log("skipping descriptor on \""); 806 cmicx_log(packet_dma_data->id_string); 807 cmicx_log("\". "); 808 } 809 810 /* write the descriptor ack word for rx to memory (dword 3 of the descriptor data) */ 811 mem[3] = 0; 812 REG_FIELD_SET_TO(mem[3],CMIC_PKTDMA_DESC_DWORD3_PACKET_BYTES_TRANSFERRED_MSB,CMIC_PKTDMA_DESC_DWORD3_PACKET_BYTES_TRANSFERRED_LSB, bytes_transferred); 813 REG_BIT_SET_TO( mem[3],CMIC_PKTDMA_DESC_DWORD3_PACKET_END_BIT, end_bit); 814 REG_BIT_SET_TO( mem[3],CMIC_PKTDMA_DESC_DWORD3_PACKET_START_BIT, start_bit); 815 REG_BIT_SET_TO( mem[3],CMIC_PKTDMA_DESC_DWORD3_PACKET_CELL_ERROR_BIT, false); 816 REG_BIT_SET_TO( mem[3],CMIC_PKTDMA_DESC_DWORD3_PACKET_DATA_READ_ECC_ERROR_BIT, false); 817 REG_BIT_SET_TO( mem[3],CMIC_PKTDMA_DESC_DWORD3_PACKET_COMPLETION_ERROR_BIT, false); 818 REG_BIT_SET_TO( mem[3],CMIC_PKTDMA_DESC_DWORD3_PACKET_DONE_BIT, true); 819 if (packet_dma_data->ctrl_desc_endianness==true) { 820 mem[3] = cmicx_reverse_word_endianness(mem[3]); 821 } 822 cmicx_pcid_mem_write(pcid_info,packet_dma_data->cur_desc_addr+((CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR-1)*CMICX_BYTES_PER_WORD),(void *)&(mem[3]),CMICX_BYTES_PER_WORD); 823 824 /* if we are done with the packet transfer because we've read the last chunk from the buffer, then log messages that we sent */ 825 /* the whole packet successfully, and reset the buffer index, so it can be reused for another incoming packet */ 826 if (end_bit==true) { 827 cmicx_log("packet on \""); 828 cmicx_log(packet_dma_data->id_string); 829 cmicx_log("\" fully written to host memory. read "); 830 cmicx_log_int(packet_dma_data->current_buffer_read_index); 831 cmicx_log(" byte(s) of packet from the EP interface. "); 832 packet_dma_data->current_buffer_index = 0; 833 packet_dma_data->current_buffer_read_index = 0; 834 } 835 836 /* if we're done with the packet transfer because we've hit the last designated descriptor for this packet, then */ 837 /* log messages that we sent only part of the packet successfully, and reset the buffer index, so it can be reused. */ 838 else if ((packet_dma_data->last_packet_chunk==true) && (bytes_available>0)) { 839 cmicx_log("packet on \""); 840 cmicx_log(packet_dma_data->id_string); 841 cmicx_log("\" partially written to host memory. read "); 842 cmicx_log_int(packet_dma_data->current_buffer_read_index); 843 cmicx_log(" byte(s) of packet from the EP interface. "); 844 packet_dma_data->current_buffer_index = 0; 845 packet_dma_data->current_buffer_read_index = 0; 846 } 847 848 cmicx_log_newline(); 849 } 850 851 } 852 853 854 /* we need to check that we are not currently waiting on packet data, so we know if we can complete this descriptor or not. */ 855 if (packet_dma_data->waiting_on_packet==false) { 856 857 /* at this point we are ending this descriptor, so we should indicate descriptor done status to the registers/interrupts and set the next current descriptor address appropriately. */ 858 cmic_packet_dma_descriptor_done(pcid_info, packet_dma_data); 859 packet_dma_data->cur_desc_addr += (CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR*CMICX_BYTES_PER_WORD); /* 4*4 because we have four words of four bytes each */ 860 861 /* if we are done with the packet, then we need to determine what to do. either end the packet dma access altogether, */ 862 /* or just move on to the next descriptor (starting the next packet). */ 863 if (packet_dma_data->last_packet_chunk==true) { 864 865 if (packet_dma_data->ctrl_direction==true) { 866 packet_dma_data->txpkt_count++; 867 } 868 else { 869 packet_dma_data->rxpkt_count++; 870 } 871 872 /* if this was the last desc in the packet dma access, then mark the packet dma access done altogether */ 873 if (packet_dma_data->last_desc==true) { 874 cmic_packet_dma_chain_done(packet_dma_data); 875 cmicx_log_newline(); 876 } 877 878 } 879 880 } 881 882 883 } 884 885 } 886 887 } 888 889 /* end update successfully */ 890 cmicx_log_level_set(0); 891 cmicx_log(" ...done."); 892 cmicx_log_newline(); 893 cmicx_log_level_set(3); 894 return true; 895 896 } 897 898 899 /* helper function to indicate that a packet dma descriptor has been completed. this functionality is needed during both descriptor reloads and normal descriptor completion. */ 900 void cmic_packet_dma_descriptor_done(pcid_info_t *pcid_info, cmicx_packet_dma_data_t *packet_dma_data) { 901 int i; 902 reg_t mem[CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR]; /* return memory from pcid (used for desc requests) */ 903 904 /* for actual descriptor done interrupt */ 905 if ((packet_dma_data->ctrl_desc_done_intr_mode==false) || (REG_BIT_GET(packet_dma_data->desc_interrupt,0)==true)) { 906 907 /* if we have interrupt coalescing and count coalescing enabled, then we have to coalesce our interrupt. otherwise, just post it right away. */ 908 if ((packet_dma_data->intr_coal_enable==true) && (packet_dma_data->intr_coal_count!=0)) { 909 packet_dma_data->intr_coal_cur_desc_done_count++; 910 if ((packet_dma_data->intr_coal_cur_desc_done_count+packet_dma_data->intr_coal_cur_chain_done_count)==packet_dma_data->intr_coal_count) { 911 cmic_packet_dma_interrupts_post(packet_dma_data); 912 } 913 } 914 else { 915 packet_dma_data->intr_coal_cur_desc_done_count++; 916 cmic_packet_dma_interrupts_post(packet_dma_data); 917 } 918 919 } 920 921 /* update status fields, if we can (when reload is set and rld_sts_upd_dis is true, we cannot). */ 922 if ((packet_dma_data->desc_reload==false) || (packet_dma_data->ctrl_rld_sts_upd_dis==false)) { 923 924 /* for irq_stat bit setting */ 925 if ((packet_dma_data->ctrl_desc_done_intr_mode==false) || (REG_BIT_GET(packet_dma_data->desc_interrupt,1)==true)) { 926 packet_dma_data->irq_stat_desc_controlled_intr = true; 927 } 928 929 /* always set the regular desc done bit */ 930 packet_dma_data->irq_stat_desc_done = true; 931 932 } 933 934 cmicx_pcid_mem_read(pcid_info,packet_dma_data->cur_desc_addr,(void *)mem,CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR*CMICX_BYTES_PER_WORD); 935 cmicx_log("packet dma descriptor read from memory after descriptor completion \""); 936 cmicx_log(packet_dma_data->id_string); 937 cmicx_log("\", words: "); 938 for (i=0; i<CMIC_PACKET_DMA_WORDS_PER_DESCRIPTOR; i++) { 939 cmicx_log_hex(mem[i]); 940 cmicx_log(", "); 941 } 942 cmicx_log_newline(); 943 } 944 945 946 /* helper function for ending the descriptor chain. this functionality is used in more than one place. */ 947 void cmic_packet_dma_chain_done(cmicx_packet_dma_data_t *packet_dma_data) { 948 949 packet_dma_data->chain_pending = false; 950 951 /* if we have interrupt coalescing and count coalescing enabled, then we have to coalesce our interrupt. otherwise, just post it right away. */ 952 if ((packet_dma_data->intr_coal_enable==true) && (packet_dma_data->intr_coal_count!=0)) { 953 packet_dma_data->intr_coal_cur_chain_done_count++; 954 if ((packet_dma_data->intr_coal_cur_desc_done_count+packet_dma_data->intr_coal_cur_chain_done_count)==packet_dma_data->intr_coal_count) { 955 cmic_packet_dma_interrupts_post(packet_dma_data); 956 } 957 } 958 else { 959 packet_dma_data->intr_coal_cur_chain_done_count++; 960 cmic_packet_dma_interrupts_post(packet_dma_data); 961 } 962 963 /* update status fields, if we can (when reload is set and rld_sts_upd_dis is true, we cannot). */ 964 if ((packet_dma_data->desc_reload==false) || (packet_dma_data->ctrl_rld_sts_upd_dis==false)) { 965 packet_dma_data->stat_dma_active = false; 966 packet_dma_data->stat_chain_done = true; 967 packet_dma_data->irq_stat_chain_done = true; 968 } 969 970 cmicx_log("ending packet dma access on \""); 971 cmicx_log(packet_dma_data->id_string); 972 cmicx_log("\". "); 973 } 974 975 /* helper function to post all pending interrupts from a given packet dma channel. */ 976 void cmic_packet_dma_interrupts_post(cmicx_packet_dma_data_t *packet_dma_data) { 977 978 int i; 979 for (i=0; i<packet_dma_data->intr_coal_cur_desc_done_count; i++) { 980 /* post actual per-desc interrupts here (method TBD) */ 981 } 982 for (i=0; i<packet_dma_data->intr_coal_cur_chain_done_count; i++) { 983 /* post actual per-chain interrupts here (method TBD) */ 984 } 985 986 /* log messages and reset counters */ 987 cmicx_log("posted "); 988 cmicx_log_int(packet_dma_data->intr_coal_cur_desc_done_count); 989 cmicx_log(" desc interrupts and "); 990 cmicx_log_int(packet_dma_data->intr_coal_cur_chain_done_count); 991 cmicx_log(" chain interrupts to host."); 992 cmicx_log_newline(); 993 packet_dma_data->intr_coal_cur_timer = 0; 994 packet_dma_data->intr_coal_cur_desc_done_count = 0; 995 packet_dma_data->intr_coal_cur_chain_done_count = 0; 996 997 } 998 999 1000 /* starts a new packet dma access for a given packet dma module */ 1001 bool cmic_packet_dma_access_start(cmicx_packet_dma_data_t *packet_dma_data) { 1002 1003 /* start logging */ 1004 cmicx_log("attempting to start new packet dma access on \""); 1005 cmicx_log(packet_dma_data->id_string); 1006 cmicx_log("\"... "); 1007 1008 /* already running failure */ 1009 if (packet_dma_data->chain_pending==true) { 1010 cmicx_log(" failure: access already running."); 1011 cmicx_log_newline(); 1012 return false; 1013 } 1014 1015 /* dma en not cleared error */ 1016 if (packet_dma_data->ctrl_dma_en==true) { 1017 cmicx_log(" failure: packet dma en bit still high (not cleared)."); 1018 cmicx_log_newline(); 1019 return false; 1020 } 1021 1022 /* set variables for successfully beginning packet dma access, and print log messages */ 1023 packet_dma_data->chain_pending = true; 1024 packet_dma_data->last_desc = false; 1025 packet_dma_data->last_packet_chunk = false; 1026 packet_dma_data->packet_chunk_countdown = 0; 1027 packet_dma_data->ctrl_dma_en = true; 1028 packet_dma_data->stat_dma_active = true; 1029 packet_dma_data->current_buffer_index = 0; 1030 packet_dma_data->cur_desc_addr = packet_dma_data->desc_addr; 1031 cmicx_log(" successfully started packet dma access."); 1032 cmicx_log_newline(); 1033 return true; 1034 } 1035 1036 1037 /* aborts a packet dma access for a given packet dma module */ 1038 bool cmic_packet_dma_access_abort(cmicx_packet_dma_data_t *packet_dma_data) { 1039 1040 /* if we have an access running, abort it and log a message, otherwise, just log a message that we could not abort. */ 1041 if ((packet_dma_data->chain_pending==true) && (packet_dma_data->ctrl_abort_dma==false)) { 1042 packet_dma_data->chain_pending = false; 1043 packet_dma_data->ctrl_abort_dma = true; 1044 packet_dma_data->stat_dma_active = false; 1045 cmicx_log("packet dma access on \""); 1046 cmicx_log(packet_dma_data->id_string); 1047 cmicx_log("\" successfully aborted."); 1048 cmicx_log_newline(); 1049 return true; 1050 } 1051 else { 1052 cmicx_log("could not abort packet dma access on \""); 1053 cmicx_log(packet_dma_data->id_string); 1054 cmicx_log("\", no access currently pending or abort has already happened.\n"); 1055 return false; 1056 } 1057 1058 } 1059 1060 1061 1062 /**********************************************/ 1063 /* packet dma register access support functions */ 1064 /**********************************************/ 1065 1066 /* request register read helper function */ 1067 bool cmic_pktdma_intr_coal_read(reg_t *val,cmicx_packet_dma_data_t *packet_dma_data) { 1068 REG_BIT_SET_TO( *val,CMIC_PKTDMA_INTR_COAL_REG_ENABLE_BIT, packet_dma_data->intr_coal_enable); 1069 REG_FIELD_SET_TO(*val,CMIC_PKTDMA_INTR_COAL_REG_COUNT_MSB,CMIC_PKTDMA_INTR_COAL_REG_COUNT_LSB,packet_dma_data->intr_coal_count); 1070 REG_FIELD_SET_TO(*val,CMIC_PKTDMA_INTR_COAL_REG_TIMER_MSB,CMIC_PKTDMA_INTR_COAL_REG_TIMER_LSB,packet_dma_data->intr_coal_timer); 1071 return true; 1072 } 1073 1074 /* request register write helper function */ 1075 bool cmic_pktdma_intr_coal_write(reg_t val,cmicx_packet_dma_data_t *packet_dma_data) { 1076 packet_dma_data->intr_coal_enable = REG_BIT_GET( val,CMIC_PKTDMA_INTR_COAL_REG_ENABLE_BIT); 1077 packet_dma_data->intr_coal_count = REG_FIELD_GET(val,CMIC_PKTDMA_INTR_COAL_REG_COUNT_MSB,CMIC_PKTDMA_INTR_COAL_REG_COUNT_LSB); 1078 packet_dma_data->intr_coal_timer = REG_FIELD_GET(val,CMIC_PKTDMA_INTR_COAL_REG_TIMER_MSB,CMIC_PKTDMA_INTR_COAL_REG_TIMER_LSB); 1079 return true; 1080 } 1081 1082 /* control register read support function */ 1083 bool cmic_pktdma_ctrl_read(reg_t *val,cmicx_packet_dma_data_t *packet_dma_data) { 1084 1085 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_DIRECTION_BIT, packet_dma_data->ctrl_direction); 1086 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_DMA_EN_BIT, packet_dma_data->ctrl_dma_en); 1087 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_ABORT_DMA_BIT, packet_dma_data->ctrl_abort_dma); 1088 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_PKTDMA_ENDIANNESS_BIT, packet_dma_data->ctrl_pktdma_endianness); 1089 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_DESC_ENDIANNESS_BIT, packet_dma_data->ctrl_desc_endianness); 1090 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_DROP_RX_PKT_ON_CHAIN_END_BIT, packet_dma_data->ctrl_drop_rx_pkt_on_chain_end); 1091 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_RLD_STS_UPD_DIS_BIT, packet_dma_data->ctrl_rld_sts_upd_dis); 1092 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_DESC_DONE_INTR_MODE_BIT, packet_dma_data->ctrl_desc_done_intr_mode); 1093 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_ENABLE_CONTINUOUS_DMA_BIT, packet_dma_data->ctrl_enable_continuous_dma); 1094 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_CONTIGUOUS_DESCRIPTORS_BIT, packet_dma_data->ctrl_contiguous_descriptors); 1095 REG_FIELD_SET_TO(*val,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_SIZE_DWORDS_MSB,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_SIZE_DWORDS_LSB, packet_dma_data->ctrl_ep_to_cpu_header_size_dwords); 1096 REG_FIELD_SET_TO(*val,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_ALIGNMENT_BYTES_MSB,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_ALIGNMENT_BYTES_LSB, packet_dma_data->ctrl_ep_to_cpu_alignment_bytes); 1097 REG_BIT_SET_TO( *val,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_ENDIANNESS_BIT, packet_dma_data->ctrl_ep_to_cpu_header_endianness); 1098 return true; 1099 1100 } 1101 1102 1103 /* control register write support function */ 1104 bool cmic_pktdma_ctrl_write(reg_t val,cmicx_packet_dma_data_t *packet_dma_data) { 1105 1106 bool return_value = true; 1107 1108 /* grab new bits/fields from reg value write */ 1109 bool new_ctrl_direction = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_DIRECTION_BIT ); 1110 bool new_ctrl_dma_en = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_DMA_EN_BIT ); 1111 bool new_ctrl_abort_dma = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_ABORT_DMA_BIT ); 1112 bool new_ctrl_pktdma_endianness = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_PKTDMA_ENDIANNESS_BIT ); 1113 bool new_ctrl_desc_endianness = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_DESC_ENDIANNESS_BIT ); 1114 bool new_ctrl_drop_rx_pkt_on_chain_end = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_DROP_RX_PKT_ON_CHAIN_END_BIT); 1115 bool new_ctrl_rld_sts_upd_dis = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_RLD_STS_UPD_DIS_BIT ); 1116 bool new_ctrl_desc_done_intr_mode = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_DESC_DONE_INTR_MODE_BIT ); 1117 bool new_ctrl_enable_continuous_dma = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_ENABLE_CONTINUOUS_DMA_BIT ); 1118 bool new_ctrl_contiguous_descriptors = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_CONTIGUOUS_DESCRIPTORS_BIT ); 1119 int new_ctrl_ep_to_cpu_header_size_dwords = REG_FIELD_GET(val,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_SIZE_DWORDS_MSB,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_SIZE_DWORDS_LSB); 1120 int new_ctrl_ep_to_cpu_alignment_bytes = REG_FIELD_GET(val,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_ALIGNMENT_BYTES_MSB,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_ALIGNMENT_BYTES_LSB); 1121 bool new_ctrl_ep_to_cpu_header_endianness = REG_BIT_GET( val,CMIC_PKTDMA_CTRL_REG_EP_TO_CPU_HEADER_ENDIANNESS_BIT); 1122 1123 /* check that we are not trying to change anything that we cannot while we already have a chain pending */ 1124 if (packet_dma_data->chain_pending==true) { 1125 1126 if (new_ctrl_direction!=packet_dma_data->ctrl_direction) { 1127 cmicx_log("attempting to change packet dma direction on "); 1128 cmicx_log(packet_dma_data->id_string); 1129 cmicx_log(" while packet dma is running. failure.\n"); 1130 return_value = false; 1131 } 1132 if (new_ctrl_pktdma_endianness!=packet_dma_data->ctrl_pktdma_endianness) { 1133 cmicx_log("attempting to change packet dma endianness on "); 1134 cmicx_log(packet_dma_data->id_string); 1135 cmicx_log(" while packet dma is running. failure.\n"); 1136 return_value = false; 1137 } 1138 if (new_ctrl_desc_endianness!=packet_dma_data->ctrl_desc_endianness) { 1139 cmicx_log("attempting to change packet dma desc endianness on "); 1140 cmicx_log(packet_dma_data->id_string); 1141 cmicx_log(" while packet dma is running. failure.\n"); 1142 return_value = false; 1143 } 1144 if (new_ctrl_desc_done_intr_mode!=packet_dma_data->ctrl_desc_done_intr_mode) { 1145 cmicx_log("attempting to change packet dma descriptor done interrupt mode on "); 1146 cmicx_log(packet_dma_data->id_string); 1147 cmicx_log(" while packet dma is running. failure.\n"); 1148 return_value = false; 1149 } 1150 if (new_ctrl_ep_to_cpu_header_endianness!=packet_dma_data->ctrl_ep_to_cpu_header_endianness) { 1151 cmicx_log("attempting to change packet dma ep to cpu [packet header] endianness on "); 1152 cmicx_log(packet_dma_data->id_string); 1153 cmicx_log(" while packet dma is running. failure.\n"); 1154 return_value = false; 1155 } 1156 if (new_ctrl_ep_to_cpu_header_size_dwords!=packet_dma_data->ctrl_ep_to_cpu_header_size_dwords) { 1157 cmicx_log("attempting to change packet dma header size dwords value on "); 1158 cmicx_log(packet_dma_data->id_string); 1159 cmicx_log(" while packet dma is running. failure.\n"); 1160 return_value = false; 1161 } 1162 if (new_ctrl_ep_to_cpu_alignment_bytes!=packet_dma_data->ctrl_ep_to_cpu_alignment_bytes) { 1163 cmicx_log("attempting to change packet dma alignment bytes value on "); 1164 cmicx_log(packet_dma_data->id_string); 1165 cmicx_log(" while packet dma is running. failure.\n"); 1166 return_value = false; 1167 } 1168 1169 } 1170 else { 1171 packet_dma_data->ctrl_direction = new_ctrl_direction; 1172 packet_dma_data->ctrl_pktdma_endianness = new_ctrl_pktdma_endianness; 1173 packet_dma_data->ctrl_desc_endianness = new_ctrl_desc_endianness; 1174 packet_dma_data->ctrl_drop_rx_pkt_on_chain_end = new_ctrl_drop_rx_pkt_on_chain_end; 1175 packet_dma_data->ctrl_rld_sts_upd_dis = new_ctrl_rld_sts_upd_dis; 1176 packet_dma_data->ctrl_desc_done_intr_mode = new_ctrl_desc_done_intr_mode; 1177 packet_dma_data->ctrl_enable_continuous_dma = new_ctrl_enable_continuous_dma; 1178 packet_dma_data->ctrl_contiguous_descriptors = new_ctrl_contiguous_descriptors; 1179 packet_dma_data->ctrl_ep_to_cpu_header_size_dwords = new_ctrl_ep_to_cpu_header_size_dwords; 1180 packet_dma_data->ctrl_ep_to_cpu_alignment_bytes = new_ctrl_ep_to_cpu_alignment_bytes; 1181 packet_dma_data->ctrl_ep_to_cpu_header_endianness = new_ctrl_ep_to_cpu_header_endianness; 1182 } 1183 1184 /* start a new access or abort if requested */ 1185 if (new_ctrl_dma_en==true) { 1186 if (cmic_packet_dma_access_start(packet_dma_data)==false) { 1187 return_value = false; 1188 } 1189 } 1190 if (new_ctrl_abort_dma==true) { 1191 if (cmic_packet_dma_access_abort(packet_dma_data)==false) { 1192 return_value = false; 1193 } 1194 } 1195 else { 1196 packet_dma_data->ctrl_abort_dma = false; 1197 } 1198 1199 /* if we are trying to clear the dma enable bit */ 1200 if (new_ctrl_dma_en==false) { 1201 1202 /* if the chain done bit is high, then we can clear our dma enable bit, our statuses, and our errors successfully. */ 1203 if ((packet_dma_data->stat_chain_done==true) && (packet_dma_data->chain_pending==false)) { 1204 packet_dma_data->ctrl_dma_en = false; 1205 packet_dma_data->stat_chain_done = false; 1206 packet_dma_data->stat_dma_active = false; 1207 packet_dma_data->stat_stwt_addr_decode_err = false; 1208 packet_dma_data->stat_pktwrrd_addr_decode_err = false; 1209 packet_dma_data->stat_descrd_addr_decode_err = false; 1210 packet_dma_data->stat_pktwr_ecc_err = false; 1211 } 1212 1213 /* invalid case for clearing dma enable bit */ 1214 else { 1215 cmicx_log("trying to clear dma enable bit for \""); 1216 cmicx_log(packet_dma_data->id_string); 1217 cmicx_log("\": chain done bit is not high, or chain is still pending. failure.\n"); 1218 return_value = false; 1219 } 1220 1221 } 1222 1223 return return_value; 1224 } 1225 1226 1227 1228 /* status register read support function */ 1229 bool cmic_pktdma_stat_read(reg_t *val,cmicx_packet_dma_data_t *packet_dma_data) { 1230 1231 REG_BIT_SET_TO(*val,CMIC_PKTDMA_STAT_REG_CHAIN_DONE_BIT, packet_dma_data->stat_chain_done); 1232 REG_BIT_SET_TO(*val,CMIC_PKTDMA_STAT_REG_DMA_ACTIVE_BIT, packet_dma_data->stat_dma_active); 1233 REG_BIT_SET_TO(*val,CMIC_PKTDMA_STAT_REG_STWT_ADDR_DECODE_ERR_BIT, packet_dma_data->stat_stwt_addr_decode_err); 1234 REG_BIT_SET_TO(*val,CMIC_PKTDMA_STAT_REG_PKTWRRD_ADDR_DECODE_ERR_BIT, packet_dma_data->stat_pktwrrd_addr_decode_err); 1235 REG_BIT_SET_TO(*val,CMIC_PKTDMA_STAT_REG_DESCRD_ADDR_DECODE_ERR_BIT, packet_dma_data->stat_descrd_addr_decode_err); 1236 REG_BIT_SET_TO(*val,CMIC_PKTDMA_STAT_REG_PKTWR_ECC_ERR_BIT, packet_dma_data->stat_pktwr_ecc_err); 1237 REG_BIT_SET_TO(*val,CMIC_PKTDMA_STAT_REG_CH_IN_HALT_BIT, packet_dma_data->stat_ch_in_halt); 1238 return true; 1239 1240 } 1241 1242 /* request register read helper function */ 1243 bool cmic_pktdma_shared_irq_stat0_read(reg_t *val,cmicx_cmc_t *cmc) { 1244 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH0_DESC_DONE_BIT, cmc->packet_dma[0].irq_stat_desc_done); 1245 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH0_CHAIN_DONE_BIT, cmc->packet_dma[0].irq_stat_chain_done); 1246 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH0_INTR_COALESCING_INTR_BIT, cmc->packet_dma[0].irq_stat_intr_coalescing_intr); 1247 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH0_DESC_CONTROLLED_INTR_BIT, cmc->packet_dma[0].irq_stat_desc_controlled_intr); 1248 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH1_DESC_DONE_BIT, cmc->packet_dma[1].irq_stat_desc_done); 1249 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH1_CHAIN_DONE_BIT, cmc->packet_dma[1].irq_stat_chain_done); 1250 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH1_INTR_COALESCING_INTR_BIT, cmc->packet_dma[1].irq_stat_intr_coalescing_intr); 1251 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH1_DESC_CONTROLLED_INTR_BIT, cmc->packet_dma[1].irq_stat_desc_controlled_intr); 1252 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH2_DESC_DONE_BIT, cmc->packet_dma[2].irq_stat_desc_done); 1253 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH2_CHAIN_DONE_BIT, cmc->packet_dma[2].irq_stat_chain_done); 1254 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH2_INTR_COALESCING_INTR_BIT, cmc->packet_dma[2].irq_stat_intr_coalescing_intr); 1255 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH2_DESC_CONTROLLED_INTR_BIT, cmc->packet_dma[2].irq_stat_desc_controlled_intr); 1256 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH3_DESC_DONE_BIT, cmc->packet_dma[3].irq_stat_desc_done); 1257 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH3_CHAIN_DONE_BIT, cmc->packet_dma[3].irq_stat_chain_done); 1258 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH3_INTR_COALESCING_INTR_BIT, cmc->packet_dma[3].irq_stat_intr_coalescing_intr); 1259 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH3_DESC_CONTROLLED_INTR_BIT, cmc->packet_dma[3].irq_stat_desc_controlled_intr); 1260 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH4_DESC_DONE_BIT, cmc->packet_dma[4].irq_stat_desc_done); 1261 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH4_CHAIN_DONE_BIT, cmc->packet_dma[4].irq_stat_chain_done); 1262 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH4_INTR_COALESCING_INTR_BIT, cmc->packet_dma[4].irq_stat_intr_coalescing_intr); 1263 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH4_DESC_CONTROLLED_INTR_BIT, cmc->packet_dma[4].irq_stat_desc_controlled_intr); 1264 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH5_DESC_DONE_BIT, cmc->packet_dma[5].irq_stat_desc_done); 1265 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH5_CHAIN_DONE_BIT, cmc->packet_dma[5].irq_stat_chain_done); 1266 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH5_INTR_COALESCING_INTR_BIT, cmc->packet_dma[5].irq_stat_intr_coalescing_intr); 1267 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH5_DESC_CONTROLLED_INTR_BIT, cmc->packet_dma[5].irq_stat_desc_controlled_intr); 1268 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH6_DESC_DONE_BIT, cmc->packet_dma[6].irq_stat_desc_done); 1269 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH6_CHAIN_DONE_BIT, cmc->packet_dma[6].irq_stat_chain_done); 1270 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH6_INTR_COALESCING_INTR_BIT, cmc->packet_dma[6].irq_stat_intr_coalescing_intr); 1271 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH6_DESC_CONTROLLED_INTR_BIT, cmc->packet_dma[6].irq_stat_desc_controlled_intr); 1272 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH7_DESC_DONE_BIT, cmc->packet_dma[7].irq_stat_desc_done); 1273 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH7_CHAIN_DONE_BIT, cmc->packet_dma[7].irq_stat_chain_done); 1274 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH7_INTR_COALESCING_INTR_BIT, cmc->packet_dma[7].irq_stat_intr_coalescing_intr); 1275 REG_BIT_SET_TO(*val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH7_DESC_CONTROLLED_INTR_BIT, cmc->packet_dma[7].irq_stat_desc_controlled_intr); 1276 return true; 1277 } 1278 1279 /* request register write helper function */ 1280 bool cmic_pktdma_shared_irq_stat_clr0_write(reg_t val,cmicx_cmc_t *cmc) { 1281 cmc->packet_dma[0].irq_stat_desc_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH0_DESC_DONE_BIT ); 1282 cmc->packet_dma[0].irq_stat_chain_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH0_CHAIN_DONE_BIT ); 1283 cmc->packet_dma[0].irq_stat_intr_coalescing_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH0_INTR_COALESCING_INTR_BIT); 1284 cmc->packet_dma[0].irq_stat_desc_controlled_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH0_DESC_CONTROLLED_INTR_BIT); 1285 cmc->packet_dma[1].irq_stat_desc_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH1_DESC_DONE_BIT ); 1286 cmc->packet_dma[1].irq_stat_chain_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH1_CHAIN_DONE_BIT ); 1287 cmc->packet_dma[1].irq_stat_intr_coalescing_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH1_INTR_COALESCING_INTR_BIT); 1288 cmc->packet_dma[1].irq_stat_desc_controlled_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH1_DESC_CONTROLLED_INTR_BIT); 1289 cmc->packet_dma[2].irq_stat_desc_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH2_DESC_DONE_BIT ); 1290 cmc->packet_dma[2].irq_stat_chain_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH2_CHAIN_DONE_BIT ); 1291 cmc->packet_dma[2].irq_stat_intr_coalescing_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH2_INTR_COALESCING_INTR_BIT); 1292 cmc->packet_dma[2].irq_stat_desc_controlled_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH2_DESC_CONTROLLED_INTR_BIT); 1293 cmc->packet_dma[3].irq_stat_desc_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH3_DESC_DONE_BIT ); 1294 cmc->packet_dma[3].irq_stat_chain_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH3_CHAIN_DONE_BIT ); 1295 cmc->packet_dma[3].irq_stat_intr_coalescing_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH3_INTR_COALESCING_INTR_BIT); 1296 cmc->packet_dma[3].irq_stat_desc_controlled_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH3_DESC_CONTROLLED_INTR_BIT); 1297 cmc->packet_dma[4].irq_stat_desc_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH4_DESC_DONE_BIT ); 1298 cmc->packet_dma[4].irq_stat_chain_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH4_CHAIN_DONE_BIT ); 1299 cmc->packet_dma[4].irq_stat_intr_coalescing_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH4_INTR_COALESCING_INTR_BIT); 1300 cmc->packet_dma[4].irq_stat_desc_controlled_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH4_DESC_CONTROLLED_INTR_BIT); 1301 cmc->packet_dma[5].irq_stat_desc_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH5_DESC_DONE_BIT ); 1302 cmc->packet_dma[5].irq_stat_chain_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH5_CHAIN_DONE_BIT ); 1303 cmc->packet_dma[5].irq_stat_intr_coalescing_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH5_INTR_COALESCING_INTR_BIT); 1304 cmc->packet_dma[5].irq_stat_desc_controlled_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH5_DESC_CONTROLLED_INTR_BIT); 1305 cmc->packet_dma[6].irq_stat_desc_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH6_DESC_DONE_BIT ); 1306 cmc->packet_dma[6].irq_stat_chain_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH6_CHAIN_DONE_BIT ); 1307 cmc->packet_dma[6].irq_stat_intr_coalescing_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH6_INTR_COALESCING_INTR_BIT); 1308 cmc->packet_dma[6].irq_stat_desc_controlled_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH6_DESC_CONTROLLED_INTR_BIT); 1309 cmc->packet_dma[7].irq_stat_desc_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH7_DESC_DONE_BIT ); 1310 cmc->packet_dma[7].irq_stat_chain_done = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH7_CHAIN_DONE_BIT ); 1311 cmc->packet_dma[7].irq_stat_intr_coalescing_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH7_INTR_COALESCING_INTR_BIT); 1312 cmc->packet_dma[7].irq_stat_desc_controlled_intr = REG_BIT_GET(val,CMIC_PKTDMA_SHARED_IRQ_STAT0_REG_CH7_DESC_CONTROLLED_INTR_BIT); 1313 return true; 1314 } 1315 1316 /* cos control rx 0 read helper function */ 1317 bool cmic_pktdma_cos_ctrl_rx_0_read(reg_t *val,cmicx_packet_dma_data_t *packet_dma_data) { 1318 int i; 1319 for (i=0; i<32; i++) { 1320 REG_BIT_SET_TO(*val,i,packet_dma_data->cos_ctrl_bmp[i]); 1321 } 1322 return true; 1323 } 1324 1325 /* cos control rx 0 write helper function */ 1326 bool cmic_pktdma_cos_ctrl_rx_0_write(reg_t val,cmicx_packet_dma_data_t *packet_dma_data) { 1327 int i; 1328 for (i=0; i<32; i++) { 1329 packet_dma_data->cos_ctrl_bmp[i] = REG_BIT_GET(val,i); 1330 } 1331 return true; 1332 } 1333 1334 /* cos control rx 1 read helper function */ 1335 bool cmic_pktdma_cos_ctrl_rx_1_read(reg_t *val,cmicx_packet_dma_data_t *packet_dma_data) { 1336 int i; 1337 for (i=0; i<32; i++) { 1338 REG_BIT_SET_TO(*val,i,packet_dma_data->cos_ctrl_bmp[i+32]); 1339 } 1340 return true; 1341 } 1342 1343 /* cos control rx 1 write helper function */ 1344 bool cmic_pktdma_cos_ctrl_rx_1_write(reg_t val,cmicx_packet_dma_data_t *packet_dma_data) { 1345 int i; 1346 for (i=0; i<32; i++) { 1347 packet_dma_data->cos_ctrl_bmp[i+32] = REG_BIT_GET(val,i); 1348 } 1349 return true; 1350 } 1351 1352 1353 1354 /******************************************************/ 1355 /* define packet dma register direct access functions */ 1356 /******************************************************/ 1357 1358 /* top-level cmic registers */ 1359 bool cmic_top_config_read(reg_t *val) { 1360 REG_BIT_SET_TO(*val,CMIC_TOP_CONFIG_REG_ENABLE_PIO_WRITE_NON_POSTED_BIT,cmicx->enable_pio_write_non_posted); 1361 REG_BIT_SET_TO(*val,CMIC_TOP_CONFIG_REG_IP_2_EP_LOOPBACK_ENABLE_BIT, cmicx->ip_2_ep_loopback_enable); 1362 return true; 1363 } 1364 bool cmic_top_config_write(reg_t val) { 1365 cmicx->enable_pio_write_non_posted = REG_BIT_GET(val,CMIC_TOP_CONFIG_REG_ENABLE_PIO_WRITE_NON_POSTED_BIT); 1366 cmicx->ip_2_ep_loopback_enable = REG_BIT_GET(val,CMIC_TOP_CONFIG_REG_IP_2_EP_LOOPBACK_ENABLE_BIT); 1367 cmicx_log("setting hardware loopback enable to: "); 1368 cmicx_log_int((int)cmicx->ip_2_ep_loopback_enable); 1369 cmicx_log_newline(); 1370 return true; 1371 } 1372 PCID_REG_READ_NULL_FUNC_GEN( cmic_top_epintf_release_all_credits_read) 1373 bool cmic_top_epintf_release_all_credits_write(reg_t val) { 1374 /* 1375 cmicx->val = 0; 1376 */ 1377 return true; 1378 } 1379 1380 /* cmc0 shared stat registers */ 1381 bool cmic_cmc0_shared_irq_stat0_read(reg_t *val) { 1382 return cmic_pktdma_shared_irq_stat0_read(val,&cmicx->cmc0); 1383 } 1384 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_shared_irq_stat0_write ) 1385 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc0_shared_irq_stat_clr0_read ) 1386 bool cmic_cmc0_shared_irq_stat_clr0_write(reg_t val) { 1387 return cmic_pktdma_shared_irq_stat_clr0_write(val,&cmicx->cmc0); 1388 } 1389 1390 /* cmc0 packet dma ch0 */ 1391 bool cmic_cmc0_pktdma_ch0_ctrl_read(reg_t *val) { 1392 return cmic_pktdma_ctrl_read(val,&cmicx->cmc0.packet_dma[0]); 1393 } 1394 bool cmic_cmc0_pktdma_ch0_ctrl_write(reg_t val) { 1395 return cmic_pktdma_ctrl_write(val,&cmicx->cmc0.packet_dma[0]); 1396 } 1397 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch0_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[0].desc_addr) ) 1398 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch0_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[0].desc_addr) ) 1399 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch0_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[0].desc_addr) ) 1400 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch0_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[0].desc_addr) ) 1401 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch0_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[0].desc_halt_addr) ) 1402 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch0_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[0].desc_halt_addr) ) 1403 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch0_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[0].desc_halt_addr) ) 1404 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch0_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[0].desc_halt_addr) ) 1405 bool cmic_cmc0_pktdma_ch0_stat_read(reg_t *val) { 1406 return cmic_pktdma_stat_read(val,&cmicx->cmc0.packet_dma[0]); 1407 } 1408 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch0_stat_write ) 1409 bool cmic_cmc0_pktdma_ch0_cos_ctrl_rx_0_read(reg_t *val) { 1410 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc0.packet_dma[0]); 1411 } 1412 bool cmic_cmc0_pktdma_ch0_cos_ctrl_rx_0_write(reg_t val) { 1413 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc0.packet_dma[0]); 1414 } 1415 bool cmic_cmc0_pktdma_ch0_cos_ctrl_rx_1_read(reg_t *val) { 1416 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc0.packet_dma[0]); 1417 } 1418 bool cmic_cmc0_pktdma_ch0_cos_ctrl_rx_1_write(reg_t val) { 1419 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc0.packet_dma[0]); 1420 } 1421 bool cmic_cmc0_pktdma_ch0_intr_coal_read(reg_t *val) { 1422 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc0.packet_dma[0]); 1423 } 1424 bool cmic_cmc0_pktdma_ch0_intr_coal_write(reg_t val) { 1425 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc0.packet_dma[0]); 1426 } 1427 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch0_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[0].cur_desc_addr) ) 1428 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch0_curr_desc_lo_write ) 1429 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch0_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[0].cur_desc_addr) ) 1430 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch0_curr_desc_hi_write ) 1431 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch0_pkt_count_rxpkt_read, cmicx->cmc0.packet_dma[0].rxpkt_count) 1432 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch0_pkt_count_rxpkt_write) 1433 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch0_pkt_count_txpkt_read, cmicx->cmc0.packet_dma[0].txpkt_count) 1434 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch0_pkt_count_txpkt_write) 1435 1436 /* cmc0 packet dma ch1 */ 1437 bool cmic_cmc0_pktdma_ch1_ctrl_read(reg_t *val) { 1438 return cmic_pktdma_ctrl_read(val,&cmicx->cmc0.packet_dma[1]); 1439 } 1440 bool cmic_cmc0_pktdma_ch1_ctrl_write(reg_t val) { 1441 return cmic_pktdma_ctrl_write(val,&cmicx->cmc0.packet_dma[1]); 1442 } 1443 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch1_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[1].desc_addr) ) 1444 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch1_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[1].desc_addr) ) 1445 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch1_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[1].desc_addr) ) 1446 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch1_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[1].desc_addr) ) 1447 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch1_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[1].desc_halt_addr) ) 1448 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch1_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[1].desc_halt_addr) ) 1449 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch1_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[1].desc_halt_addr) ) 1450 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch1_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[1].desc_halt_addr) ) 1451 bool cmic_cmc0_pktdma_ch1_stat_read(reg_t *val) { 1452 return cmic_pktdma_stat_read(val,&cmicx->cmc0.packet_dma[1]); 1453 } 1454 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch1_stat_write ) 1455 bool cmic_cmc0_pktdma_ch1_cos_ctrl_rx_0_read(reg_t *val) { 1456 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc0.packet_dma[1]); 1457 } 1458 bool cmic_cmc0_pktdma_ch1_cos_ctrl_rx_0_write(reg_t val) { 1459 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc0.packet_dma[1]); 1460 } 1461 bool cmic_cmc0_pktdma_ch1_cos_ctrl_rx_1_read(reg_t *val) { 1462 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc0.packet_dma[1]); 1463 } 1464 bool cmic_cmc0_pktdma_ch1_cos_ctrl_rx_1_write(reg_t val) { 1465 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc0.packet_dma[1]); 1466 } 1467 bool cmic_cmc0_pktdma_ch1_intr_coal_read(reg_t *val) { 1468 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc0.packet_dma[1]); 1469 } 1470 bool cmic_cmc0_pktdma_ch1_intr_coal_write(reg_t val) { 1471 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc0.packet_dma[1]); 1472 } 1473 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch1_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[1].cur_desc_addr) ) 1474 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch1_curr_desc_lo_write ) 1475 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch1_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[1].cur_desc_addr) ) 1476 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch1_curr_desc_hi_write ) 1477 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch1_pkt_count_rxpkt_read, cmicx->cmc0.packet_dma[1].rxpkt_count) 1478 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch1_pkt_count_rxpkt_write) 1479 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch1_pkt_count_txpkt_read, cmicx->cmc0.packet_dma[1].txpkt_count) 1480 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch1_pkt_count_txpkt_write) 1481 1482 /* cmc0 packet dma ch2*/ 1483 bool cmic_cmc0_pktdma_ch2_ctrl_read(reg_t *val) { 1484 return cmic_pktdma_ctrl_read(val,&cmicx->cmc0.packet_dma[2]); 1485 } 1486 bool cmic_cmc0_pktdma_ch2_ctrl_write(reg_t val) { 1487 return cmic_pktdma_ctrl_write(val,&cmicx->cmc0.packet_dma[2]); 1488 } 1489 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch2_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[2].desc_addr) ) 1490 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch2_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[2].desc_addr) ) 1491 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch2_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[2].desc_addr) ) 1492 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch2_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[2].desc_addr) ) 1493 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch2_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[2].desc_halt_addr) ) 1494 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch2_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[2].desc_halt_addr) ) 1495 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch2_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[2].desc_halt_addr) ) 1496 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch2_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[2].desc_halt_addr) ) 1497 bool cmic_cmc0_pktdma_ch2_stat_read(reg_t *val) { 1498 return cmic_pktdma_stat_read(val,&cmicx->cmc0.packet_dma[2]); 1499 } 1500 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch2_stat_write ) 1501 bool cmic_cmc0_pktdma_ch2_cos_ctrl_rx_0_read(reg_t *val) { 1502 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc0.packet_dma[2]); 1503 } 1504 bool cmic_cmc0_pktdma_ch2_cos_ctrl_rx_0_write(reg_t val) { 1505 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc0.packet_dma[2]); 1506 } 1507 bool cmic_cmc0_pktdma_ch2_cos_ctrl_rx_1_read(reg_t *val) { 1508 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc0.packet_dma[2]); 1509 } 1510 bool cmic_cmc0_pktdma_ch2_cos_ctrl_rx_1_write(reg_t val) { 1511 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc0.packet_dma[2]); 1512 } 1513 bool cmic_cmc0_pktdma_ch2_intr_coal_read(reg_t *val) { 1514 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc0.packet_dma[2]); 1515 } 1516 bool cmic_cmc0_pktdma_ch2_intr_coal_write(reg_t val) { 1517 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc0.packet_dma[2]); 1518 } 1519 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch2_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[2].cur_desc_addr) ) 1520 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch2_curr_desc_lo_write ) 1521 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch2_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[2].cur_desc_addr) ) 1522 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch2_curr_desc_hi_write ) 1523 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch2_pkt_count_rxpkt_read, cmicx->cmc0.packet_dma[2].rxpkt_count) 1524 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch2_pkt_count_rxpkt_write) 1525 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch2_pkt_count_txpkt_read, cmicx->cmc0.packet_dma[2].txpkt_count) 1526 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch2_pkt_count_txpkt_write) 1527 1528 /* cmc0 packet dma ch3 */ 1529 bool cmic_cmc0_pktdma_ch3_ctrl_read(reg_t *val) { 1530 return cmic_pktdma_ctrl_read(val,&cmicx->cmc0.packet_dma[3]); 1531 } 1532 bool cmic_cmc0_pktdma_ch3_ctrl_write(reg_t val) { 1533 return cmic_pktdma_ctrl_write(val,&cmicx->cmc0.packet_dma[3]); 1534 } 1535 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch3_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[3].desc_addr) ) 1536 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch3_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[3].desc_addr) ) 1537 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch3_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[3].desc_addr) ) 1538 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch3_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[3].desc_addr) ) 1539 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch3_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[3].desc_halt_addr) ) 1540 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch3_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[3].desc_halt_addr) ) 1541 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch3_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[3].desc_halt_addr) ) 1542 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch3_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[3].desc_halt_addr) ) 1543 bool cmic_cmc0_pktdma_ch3_stat_read(reg_t *val) { 1544 return cmic_pktdma_stat_read(val,&cmicx->cmc0.packet_dma[3]); 1545 } 1546 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch3_stat_write ) 1547 bool cmic_cmc0_pktdma_ch3_cos_ctrl_rx_0_read(reg_t *val) { 1548 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc0.packet_dma[3]); 1549 } 1550 bool cmic_cmc0_pktdma_ch3_cos_ctrl_rx_0_write(reg_t val) { 1551 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc0.packet_dma[3]); 1552 } 1553 bool cmic_cmc0_pktdma_ch3_cos_ctrl_rx_1_read(reg_t *val) { 1554 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc0.packet_dma[3]); 1555 } 1556 bool cmic_cmc0_pktdma_ch3_cos_ctrl_rx_1_write(reg_t val) { 1557 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc0.packet_dma[3]); 1558 } 1559 bool cmic_cmc0_pktdma_ch3_intr_coal_read(reg_t *val) { 1560 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc0.packet_dma[3]); 1561 } 1562 bool cmic_cmc0_pktdma_ch3_intr_coal_write(reg_t val) { 1563 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc0.packet_dma[3]); 1564 } 1565 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch3_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[3].cur_desc_addr) ) 1566 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch3_curr_desc_lo_write ) 1567 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch3_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[3].cur_desc_addr) ) 1568 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch3_curr_desc_hi_write ) 1569 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch3_pkt_count_rxpkt_read, cmicx->cmc0.packet_dma[3].rxpkt_count) 1570 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch3_pkt_count_rxpkt_write) 1571 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch3_pkt_count_txpkt_read, cmicx->cmc0.packet_dma[3].txpkt_count) 1572 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch3_pkt_count_txpkt_write) 1573 1574 /* cmc0 packet dma ch4 */ 1575 bool cmic_cmc0_pktdma_ch4_ctrl_read(reg_t *val) { 1576 return cmic_pktdma_ctrl_read(val,&cmicx->cmc0.packet_dma[4]); 1577 } 1578 bool cmic_cmc0_pktdma_ch4_ctrl_write(reg_t val) { 1579 return cmic_pktdma_ctrl_write(val,&cmicx->cmc0.packet_dma[4]); 1580 } 1581 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch4_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[4].desc_addr) ) 1582 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch4_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[4].desc_addr) ) 1583 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch4_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[4].desc_addr) ) 1584 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch4_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[4].desc_addr) ) 1585 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch4_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[4].desc_halt_addr) ) 1586 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch4_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[4].desc_halt_addr) ) 1587 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch4_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[4].desc_halt_addr) ) 1588 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch4_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[4].desc_halt_addr) ) 1589 bool cmic_cmc0_pktdma_ch4_stat_read(reg_t *val) { 1590 return cmic_pktdma_stat_read(val,&cmicx->cmc0.packet_dma[4]); 1591 } 1592 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch4_stat_write ) 1593 bool cmic_cmc0_pktdma_ch4_cos_ctrl_rx_0_read(reg_t *val) { 1594 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc0.packet_dma[4]); 1595 } 1596 bool cmic_cmc0_pktdma_ch4_cos_ctrl_rx_0_write(reg_t val) { 1597 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc0.packet_dma[4]); 1598 } 1599 bool cmic_cmc0_pktdma_ch4_cos_ctrl_rx_1_read(reg_t *val) { 1600 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc0.packet_dma[4]); 1601 } 1602 bool cmic_cmc0_pktdma_ch4_cos_ctrl_rx_1_write(reg_t val) { 1603 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc0.packet_dma[4]); 1604 } 1605 bool cmic_cmc0_pktdma_ch4_intr_coal_read(reg_t *val) { 1606 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc0.packet_dma[4]); 1607 } 1608 bool cmic_cmc0_pktdma_ch4_intr_coal_write(reg_t val) { 1609 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc0.packet_dma[4]); 1610 } 1611 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch4_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[4].cur_desc_addr) ) 1612 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch4_curr_desc_lo_write ) 1613 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch4_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[4].cur_desc_addr) ) 1614 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch4_curr_desc_hi_write ) 1615 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch4_pkt_count_rxpkt_read, cmicx->cmc0.packet_dma[4].rxpkt_count) 1616 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch4_pkt_count_rxpkt_write) 1617 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch4_pkt_count_txpkt_read, cmicx->cmc0.packet_dma[4].txpkt_count) 1618 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch4_pkt_count_txpkt_write) 1619 1620 /* cmc0 packet dma ch5 */ 1621 bool cmic_cmc0_pktdma_ch5_ctrl_read(reg_t *val) { 1622 return cmic_pktdma_ctrl_read(val,&cmicx->cmc0.packet_dma[5]); 1623 } 1624 bool cmic_cmc0_pktdma_ch5_ctrl_write(reg_t val) { 1625 return cmic_pktdma_ctrl_write(val,&cmicx->cmc0.packet_dma[5]); 1626 } 1627 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch5_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[5].desc_addr) ) 1628 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch5_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[5].desc_addr) ) 1629 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch5_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[5].desc_addr) ) 1630 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch5_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[5].desc_addr) ) 1631 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch5_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[5].desc_halt_addr) ) 1632 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch5_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[5].desc_halt_addr) ) 1633 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch5_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[5].desc_halt_addr) ) 1634 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch5_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[5].desc_halt_addr) ) 1635 bool cmic_cmc0_pktdma_ch5_stat_read(reg_t *val) { 1636 return cmic_pktdma_stat_read(val,&cmicx->cmc0.packet_dma[5]); 1637 } 1638 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch5_stat_write ) 1639 bool cmic_cmc0_pktdma_ch5_cos_ctrl_rx_0_read(reg_t *val) { 1640 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc0.packet_dma[5]); 1641 } 1642 bool cmic_cmc0_pktdma_ch5_cos_ctrl_rx_0_write(reg_t val) { 1643 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc0.packet_dma[5]); 1644 } 1645 bool cmic_cmc0_pktdma_ch5_cos_ctrl_rx_1_read(reg_t *val) { 1646 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc0.packet_dma[5]); 1647 } 1648 bool cmic_cmc0_pktdma_ch5_cos_ctrl_rx_1_write(reg_t val) { 1649 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc0.packet_dma[5]); 1650 } 1651 bool cmic_cmc0_pktdma_ch5_intr_coal_read(reg_t *val) { 1652 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc0.packet_dma[5]); 1653 } 1654 bool cmic_cmc0_pktdma_ch5_intr_coal_write(reg_t val) { 1655 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc0.packet_dma[5]); 1656 } 1657 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch5_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[5].cur_desc_addr) ) 1658 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch5_curr_desc_lo_write ) 1659 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch5_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[5].cur_desc_addr) ) 1660 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch5_curr_desc_hi_write ) 1661 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch5_pkt_count_rxpkt_read, cmicx->cmc0.packet_dma[5].rxpkt_count) 1662 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch5_pkt_count_rxpkt_write) 1663 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch5_pkt_count_txpkt_read, cmicx->cmc0.packet_dma[5].txpkt_count) 1664 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch5_pkt_count_txpkt_write) 1665 1666 /* cmc0 packet dma ch6 */ 1667 bool cmic_cmc0_pktdma_ch6_ctrl_read(reg_t *val) { 1668 return cmic_pktdma_ctrl_read(val,&cmicx->cmc0.packet_dma[6]); 1669 } 1670 bool cmic_cmc0_pktdma_ch6_ctrl_write(reg_t val) { 1671 return cmic_pktdma_ctrl_write(val,&cmicx->cmc0.packet_dma[6]); 1672 } 1673 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch6_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[6].desc_addr) ) 1674 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch6_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[6].desc_addr) ) 1675 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch6_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[6].desc_addr) ) 1676 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch6_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[6].desc_addr) ) 1677 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch6_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[6].desc_halt_addr) ) 1678 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch6_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[6].desc_halt_addr) ) 1679 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch6_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[6].desc_halt_addr) ) 1680 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch6_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[6].desc_halt_addr) ) 1681 bool cmic_cmc0_pktdma_ch6_stat_read(reg_t *val) { 1682 return cmic_pktdma_stat_read(val,&cmicx->cmc0.packet_dma[6]); 1683 } 1684 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch6_stat_write ) 1685 bool cmic_cmc0_pktdma_ch6_cos_ctrl_rx_0_read(reg_t *val) { 1686 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc0.packet_dma[6]); 1687 } 1688 bool cmic_cmc0_pktdma_ch6_cos_ctrl_rx_0_write(reg_t val) { 1689 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc0.packet_dma[6]); 1690 } 1691 bool cmic_cmc0_pktdma_ch6_cos_ctrl_rx_1_read(reg_t *val) { 1692 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc0.packet_dma[6]); 1693 } 1694 bool cmic_cmc0_pktdma_ch6_cos_ctrl_rx_1_write(reg_t val) { 1695 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc0.packet_dma[6]); 1696 } 1697 bool cmic_cmc0_pktdma_ch6_intr_coal_read(reg_t *val) { 1698 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc0.packet_dma[6]); 1699 } 1700 bool cmic_cmc0_pktdma_ch6_intr_coal_write(reg_t val) { 1701 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc0.packet_dma[6]); 1702 } 1703 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch6_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[6].cur_desc_addr) ) 1704 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch6_curr_desc_lo_write ) 1705 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch6_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[6].cur_desc_addr) ) 1706 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch6_curr_desc_hi_write ) 1707 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch6_pkt_count_rxpkt_read, cmicx->cmc0.packet_dma[6].rxpkt_count) 1708 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch6_pkt_count_rxpkt_write) 1709 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch6_pkt_count_txpkt_read, cmicx->cmc0.packet_dma[6].txpkt_count) 1710 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch6_pkt_count_txpkt_write) 1711 1712 /* cmc0 packet dma ch7 */ 1713 bool cmic_cmc0_pktdma_ch7_ctrl_read(reg_t *val) { 1714 return cmic_pktdma_ctrl_read(val,&cmicx->cmc0.packet_dma[7]); 1715 } 1716 bool cmic_cmc0_pktdma_ch7_ctrl_write(reg_t val) { 1717 return cmic_pktdma_ctrl_write(val,&cmicx->cmc0.packet_dma[7]); 1718 } 1719 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch7_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[7].desc_addr) ) 1720 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch7_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[7].desc_addr) ) 1721 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch7_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[7].desc_addr) ) 1722 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch7_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[7].desc_addr) ) 1723 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch7_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[7].desc_halt_addr) ) 1724 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch7_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[7].desc_halt_addr) ) 1725 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch7_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[7].desc_halt_addr) ) 1726 PCID_REG_WRITE_FUNC_GEN( cmic_cmc0_pktdma_ch7_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[7].desc_halt_addr) ) 1727 bool cmic_cmc0_pktdma_ch7_stat_read(reg_t *val) { 1728 return cmic_pktdma_stat_read(val,&cmicx->cmc0.packet_dma[7]); 1729 } 1730 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch7_stat_write ) 1731 bool cmic_cmc0_pktdma_ch7_cos_ctrl_rx_0_read(reg_t *val) { 1732 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc0.packet_dma[7]); 1733 } 1734 bool cmic_cmc0_pktdma_ch7_cos_ctrl_rx_0_write(reg_t val) { 1735 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc0.packet_dma[7]); 1736 } 1737 bool cmic_cmc0_pktdma_ch7_cos_ctrl_rx_1_read(reg_t *val) { 1738 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc0.packet_dma[7]); 1739 } 1740 bool cmic_cmc0_pktdma_ch7_cos_ctrl_rx_1_write(reg_t val) { 1741 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc0.packet_dma[7]); 1742 } 1743 bool cmic_cmc0_pktdma_ch7_intr_coal_read(reg_t *val) { 1744 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc0.packet_dma[7]); 1745 } 1746 bool cmic_cmc0_pktdma_ch7_intr_coal_write(reg_t val) { 1747 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc0.packet_dma[7]); 1748 } 1749 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch7_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc0.packet_dma[7].cur_desc_addr) ) 1750 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch7_curr_desc_lo_write ) 1751 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch7_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc0.packet_dma[7].cur_desc_addr) ) 1752 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch7_curr_desc_hi_write ) 1753 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch7_pkt_count_rxpkt_read, cmicx->cmc0.packet_dma[7].rxpkt_count) 1754 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch7_pkt_count_rxpkt_write) 1755 PCID_REG_READ_FUNC_GEN( cmic_cmc0_pktdma_ch7_pkt_count_txpkt_read, cmicx->cmc0.packet_dma[7].txpkt_count) 1756 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc0_pktdma_ch7_pkt_count_txpkt_write) 1757 1758 /* cmc1 shared stat registers */ 1759 bool cmic_cmc1_shared_irq_stat0_read(reg_t *val) { 1760 return cmic_pktdma_shared_irq_stat0_read(val,&cmicx->cmc1); 1761 } 1762 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_shared_irq_stat0_write ) 1763 PCID_REG_READ_NULL_FUNC_GEN( cmic_cmc1_shared_irq_stat_clr0_read ) 1764 bool cmic_cmc1_shared_irq_stat_clr0_write(reg_t val) { 1765 return cmic_pktdma_shared_irq_stat_clr0_write(val,&cmicx->cmc1); 1766 } 1767 1768 /* cmc1 packet dma ch0 */ 1769 bool cmic_cmc1_pktdma_ch0_ctrl_read(reg_t *val) { 1770 return cmic_pktdma_ctrl_read(val,&cmicx->cmc1.packet_dma[0]); 1771 } 1772 bool cmic_cmc1_pktdma_ch0_ctrl_write(reg_t val) { 1773 return cmic_pktdma_ctrl_write(val,&cmicx->cmc1.packet_dma[0]); 1774 } 1775 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch0_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[0].desc_addr) ) 1776 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch0_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[0].desc_addr) ) 1777 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch0_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[0].desc_addr) ) 1778 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch0_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[0].desc_addr) ) 1779 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch0_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[0].desc_halt_addr) ) 1780 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch0_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[0].desc_halt_addr) ) 1781 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch0_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[0].desc_halt_addr) ) 1782 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch0_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[0].desc_halt_addr) ) 1783 bool cmic_cmc1_pktdma_ch0_stat_read(reg_t *val) { 1784 return cmic_pktdma_stat_read(val,&cmicx->cmc1.packet_dma[0]); 1785 } 1786 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch0_stat_write ) 1787 bool cmic_cmc1_pktdma_ch0_cos_ctrl_rx_0_read(reg_t *val) { 1788 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc1.packet_dma[0]); 1789 } 1790 bool cmic_cmc1_pktdma_ch0_cos_ctrl_rx_0_write(reg_t val) { 1791 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc1.packet_dma[0]); 1792 } 1793 bool cmic_cmc1_pktdma_ch0_cos_ctrl_rx_1_read(reg_t *val) { 1794 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc1.packet_dma[0]); 1795 } 1796 bool cmic_cmc1_pktdma_ch0_cos_ctrl_rx_1_write(reg_t val) { 1797 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc1.packet_dma[0]); 1798 } 1799 bool cmic_cmc1_pktdma_ch0_intr_coal_read(reg_t *val) { 1800 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc1.packet_dma[0]); 1801 } 1802 bool cmic_cmc1_pktdma_ch0_intr_coal_write(reg_t val) { 1803 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc1.packet_dma[0]); 1804 } 1805 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch0_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[0].cur_desc_addr) ) 1806 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch0_curr_desc_lo_write ) 1807 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch0_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[0].cur_desc_addr) ) 1808 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch0_curr_desc_hi_write ) 1809 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch0_pkt_count_rxpkt_read, cmicx->cmc1.packet_dma[0].rxpkt_count) 1810 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch0_pkt_count_rxpkt_write) 1811 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch0_pkt_count_txpkt_read, cmicx->cmc1.packet_dma[0].txpkt_count) 1812 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch0_pkt_count_txpkt_write) 1813 1814 /* cmc1 packet dma ch1 */ 1815 bool cmic_cmc1_pktdma_ch1_ctrl_read(reg_t *val) { 1816 return cmic_pktdma_ctrl_read(val,&cmicx->cmc1.packet_dma[1]); 1817 } 1818 bool cmic_cmc1_pktdma_ch1_ctrl_write(reg_t val) { 1819 return cmic_pktdma_ctrl_write(val,&cmicx->cmc1.packet_dma[1]); 1820 } 1821 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch1_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[1].desc_addr) ) 1822 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch1_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[1].desc_addr) ) 1823 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch1_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[1].desc_addr) ) 1824 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch1_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[1].desc_addr) ) 1825 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch1_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[1].desc_halt_addr) ) 1826 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch1_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[1].desc_halt_addr) ) 1827 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch1_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[1].desc_halt_addr) ) 1828 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch1_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[1].desc_halt_addr) ) 1829 bool cmic_cmc1_pktdma_ch1_stat_read(reg_t *val) { 1830 return cmic_pktdma_stat_read(val,&cmicx->cmc1.packet_dma[1]); 1831 } 1832 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch1_stat_write ) 1833 bool cmic_cmc1_pktdma_ch1_cos_ctrl_rx_0_read(reg_t *val) { 1834 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc1.packet_dma[1]); 1835 } 1836 bool cmic_cmc1_pktdma_ch1_cos_ctrl_rx_0_write(reg_t val) { 1837 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc1.packet_dma[1]); 1838 } 1839 bool cmic_cmc1_pktdma_ch1_cos_ctrl_rx_1_read(reg_t *val) { 1840 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc1.packet_dma[1]); 1841 } 1842 bool cmic_cmc1_pktdma_ch1_cos_ctrl_rx_1_write(reg_t val) { 1843 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc1.packet_dma[1]); 1844 } 1845 bool cmic_cmc1_pktdma_ch1_intr_coal_read(reg_t *val) { 1846 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc1.packet_dma[1]); 1847 } 1848 bool cmic_cmc1_pktdma_ch1_intr_coal_write(reg_t val) { 1849 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc1.packet_dma[1]); 1850 } 1851 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch1_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[1].cur_desc_addr) ) 1852 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch1_curr_desc_lo_write ) 1853 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch1_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[1].cur_desc_addr) ) 1854 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch1_curr_desc_hi_write ) 1855 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch1_pkt_count_rxpkt_read, cmicx->cmc1.packet_dma[1].rxpkt_count) 1856 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch1_pkt_count_rxpkt_write) 1857 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch1_pkt_count_txpkt_read, cmicx->cmc1.packet_dma[1].txpkt_count) 1858 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch1_pkt_count_txpkt_write) 1859 1860 /* cmc1 packet dma ch2 */ 1861 bool cmic_cmc1_pktdma_ch2_ctrl_read(reg_t *val) { 1862 return cmic_pktdma_ctrl_read(val,&cmicx->cmc1.packet_dma[2]); 1863 } 1864 bool cmic_cmc1_pktdma_ch2_ctrl_write(reg_t val) { 1865 return cmic_pktdma_ctrl_write(val,&cmicx->cmc1.packet_dma[2]); 1866 } 1867 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch2_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[2].desc_addr) ) 1868 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch2_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[2].desc_addr) ) 1869 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch2_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[2].desc_addr) ) 1870 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch2_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[2].desc_addr) ) 1871 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch2_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[2].desc_halt_addr) ) 1872 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch2_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[2].desc_halt_addr) ) 1873 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch2_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[2].desc_halt_addr) ) 1874 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch2_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[2].desc_halt_addr) ) 1875 bool cmic_cmc1_pktdma_ch2_stat_read(reg_t *val) { 1876 return cmic_pktdma_stat_read(val,&cmicx->cmc1.packet_dma[2]); 1877 } 1878 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch2_stat_write ) 1879 bool cmic_cmc1_pktdma_ch2_cos_ctrl_rx_0_read(reg_t *val) { 1880 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc1.packet_dma[2]); 1881 } 1882 bool cmic_cmc1_pktdma_ch2_cos_ctrl_rx_0_write(reg_t val) { 1883 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc1.packet_dma[2]); 1884 } 1885 bool cmic_cmc1_pktdma_ch2_cos_ctrl_rx_1_read(reg_t *val) { 1886 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc1.packet_dma[2]); 1887 } 1888 bool cmic_cmc1_pktdma_ch2_cos_ctrl_rx_1_write(reg_t val) { 1889 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc1.packet_dma[2]); 1890 } 1891 bool cmic_cmc1_pktdma_ch2_intr_coal_read(reg_t *val) { 1892 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc1.packet_dma[2]); 1893 } 1894 bool cmic_cmc1_pktdma_ch2_intr_coal_write(reg_t val) { 1895 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc1.packet_dma[2]); 1896 } 1897 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch2_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[2].cur_desc_addr) ) 1898 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch2_curr_desc_lo_write ) 1899 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch2_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[2].cur_desc_addr) ) 1900 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch2_curr_desc_hi_write ) 1901 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch2_pkt_count_rxpkt_read, cmicx->cmc1.packet_dma[2].rxpkt_count) 1902 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch2_pkt_count_rxpkt_write) 1903 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch2_pkt_count_txpkt_read, cmicx->cmc1.packet_dma[2].txpkt_count) 1904 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch2_pkt_count_txpkt_write) 1905 1906 /* cmc1 packet dma ch3 */ 1907 bool cmic_cmc1_pktdma_ch3_ctrl_read(reg_t *val) { 1908 return cmic_pktdma_ctrl_read(val,&cmicx->cmc1.packet_dma[3]); 1909 } 1910 bool cmic_cmc1_pktdma_ch3_ctrl_write(reg_t val) { 1911 return cmic_pktdma_ctrl_write(val,&cmicx->cmc1.packet_dma[3]); 1912 } 1913 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch3_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[3].desc_addr) ) 1914 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch3_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[3].desc_addr) ) 1915 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch3_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[3].desc_addr) ) 1916 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch3_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[3].desc_addr) ) 1917 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch3_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[3].desc_halt_addr) ) 1918 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch3_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[3].desc_halt_addr) ) 1919 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch3_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[3].desc_halt_addr) ) 1920 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch3_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[3].desc_halt_addr) ) 1921 bool cmic_cmc1_pktdma_ch3_stat_read(reg_t *val) { 1922 return cmic_pktdma_stat_read(val,&cmicx->cmc1.packet_dma[3]); 1923 } 1924 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch3_stat_write ) 1925 bool cmic_cmc1_pktdma_ch3_cos_ctrl_rx_0_read(reg_t *val) { 1926 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc1.packet_dma[3]); 1927 } 1928 bool cmic_cmc1_pktdma_ch3_cos_ctrl_rx_0_write(reg_t val) { 1929 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc1.packet_dma[3]); 1930 } 1931 bool cmic_cmc1_pktdma_ch3_cos_ctrl_rx_1_read(reg_t *val) { 1932 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc1.packet_dma[3]); 1933 } 1934 bool cmic_cmc1_pktdma_ch3_cos_ctrl_rx_1_write(reg_t val) { 1935 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc1.packet_dma[3]); 1936 } 1937 bool cmic_cmc1_pktdma_ch3_intr_coal_read(reg_t *val) { 1938 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc1.packet_dma[3]); 1939 } 1940 bool cmic_cmc1_pktdma_ch3_intr_coal_write(reg_t val) { 1941 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc1.packet_dma[3]); 1942 } 1943 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch3_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[3].cur_desc_addr) ) 1944 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch3_curr_desc_lo_write ) 1945 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch3_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[3].cur_desc_addr) ) 1946 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch3_curr_desc_hi_write ) 1947 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch3_pkt_count_rxpkt_read, cmicx->cmc1.packet_dma[3].rxpkt_count) 1948 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch3_pkt_count_rxpkt_write) 1949 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch3_pkt_count_txpkt_read, cmicx->cmc1.packet_dma[3].txpkt_count) 1950 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch3_pkt_count_txpkt_write) 1951 1952 /* cmc0 packet dma ch4 */ 1953 bool cmic_cmc1_pktdma_ch4_ctrl_read(reg_t *val) { 1954 return cmic_pktdma_ctrl_read(val,&cmicx->cmc1.packet_dma[4]); 1955 } 1956 bool cmic_cmc1_pktdma_ch4_ctrl_write(reg_t val) { 1957 return cmic_pktdma_ctrl_write(val,&cmicx->cmc1.packet_dma[4]); 1958 } 1959 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch4_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[4].desc_addr) ) 1960 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch4_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[4].desc_addr) ) 1961 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch4_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[4].desc_addr) ) 1962 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch4_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[4].desc_addr) ) 1963 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch4_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[4].desc_halt_addr) ) 1964 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch4_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[4].desc_halt_addr) ) 1965 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch4_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[4].desc_halt_addr) ) 1966 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch4_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[4].desc_halt_addr) ) 1967 bool cmic_cmc1_pktdma_ch4_stat_read(reg_t *val) { 1968 return cmic_pktdma_stat_read(val,&cmicx->cmc1.packet_dma[4]); 1969 } 1970 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch4_stat_write ) 1971 bool cmic_cmc1_pktdma_ch4_cos_ctrl_rx_0_read(reg_t *val) { 1972 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc1.packet_dma[4]); 1973 } 1974 bool cmic_cmc1_pktdma_ch4_cos_ctrl_rx_0_write(reg_t val) { 1975 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc1.packet_dma[4]); 1976 } 1977 bool cmic_cmc1_pktdma_ch4_cos_ctrl_rx_1_read(reg_t *val) { 1978 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc1.packet_dma[4]); 1979 } 1980 bool cmic_cmc1_pktdma_ch4_cos_ctrl_rx_1_write(reg_t val) { 1981 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc1.packet_dma[4]); 1982 } 1983 bool cmic_cmc1_pktdma_ch4_intr_coal_read(reg_t *val) { 1984 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc1.packet_dma[4]); 1985 } 1986 bool cmic_cmc1_pktdma_ch4_intr_coal_write(reg_t val) { 1987 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc1.packet_dma[4]); 1988 } 1989 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch4_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[4].cur_desc_addr) ) 1990 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch4_curr_desc_lo_write ) 1991 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch4_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[4].cur_desc_addr) ) 1992 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch4_curr_desc_hi_write ) 1993 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch4_pkt_count_rxpkt_read, cmicx->cmc1.packet_dma[4].rxpkt_count) 1994 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch4_pkt_count_rxpkt_write) 1995 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch4_pkt_count_txpkt_read, cmicx->cmc1.packet_dma[4].txpkt_count) 1996 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch4_pkt_count_txpkt_write) 1997 1998 /* cmc1 packet dma ch5 */ 1999 bool cmic_cmc1_pktdma_ch5_ctrl_read(reg_t *val) { 2000 return cmic_pktdma_ctrl_read(val,&cmicx->cmc1.packet_dma[5]); 2001 } 2002 bool cmic_cmc1_pktdma_ch5_ctrl_write(reg_t val) { 2003 return cmic_pktdma_ctrl_write(val,&cmicx->cmc1.packet_dma[5]); 2004 } 2005 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch5_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[5].desc_addr) ) 2006 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch5_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[5].desc_addr) ) 2007 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch5_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[5].desc_addr) ) 2008 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch5_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[5].desc_addr) ) 2009 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch5_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[5].desc_halt_addr) ) 2010 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch5_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[5].desc_halt_addr) ) 2011 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch5_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[5].desc_halt_addr) ) 2012 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch5_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[5].desc_halt_addr) ) 2013 bool cmic_cmc1_pktdma_ch5_stat_read(reg_t *val) { 2014 return cmic_pktdma_stat_read(val,&cmicx->cmc1.packet_dma[5]); 2015 } 2016 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch5_stat_write ) 2017 bool cmic_cmc1_pktdma_ch5_cos_ctrl_rx_0_read(reg_t *val) { 2018 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc1.packet_dma[5]); 2019 } 2020 bool cmic_cmc1_pktdma_ch5_cos_ctrl_rx_0_write(reg_t val) { 2021 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc1.packet_dma[5]); 2022 } 2023 bool cmic_cmc1_pktdma_ch5_cos_ctrl_rx_1_read(reg_t *val) { 2024 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc1.packet_dma[5]); 2025 } 2026 bool cmic_cmc1_pktdma_ch5_cos_ctrl_rx_1_write(reg_t val) { 2027 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc1.packet_dma[5]); 2028 } 2029 bool cmic_cmc1_pktdma_ch5_intr_coal_read(reg_t *val) { 2030 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc1.packet_dma[5]); 2031 } 2032 bool cmic_cmc1_pktdma_ch5_intr_coal_write(reg_t val) { 2033 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc1.packet_dma[5]); 2034 } 2035 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch5_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[5].cur_desc_addr) ) 2036 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch5_curr_desc_lo_write ) 2037 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch5_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[5].cur_desc_addr) ) 2038 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch5_curr_desc_hi_write ) 2039 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch5_pkt_count_rxpkt_read, cmicx->cmc1.packet_dma[5].rxpkt_count) 2040 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch5_pkt_count_rxpkt_write) 2041 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch5_pkt_count_txpkt_read, cmicx->cmc1.packet_dma[5].txpkt_count) 2042 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch5_pkt_count_txpkt_write) 2043 2044 /* cmc1 packet dma ch6 */ 2045 bool cmic_cmc1_pktdma_ch6_ctrl_read(reg_t *val) { 2046 return cmic_pktdma_ctrl_read(val,&cmicx->cmc1.packet_dma[6]); 2047 } 2048 bool cmic_cmc1_pktdma_ch6_ctrl_write(reg_t val) { 2049 return cmic_pktdma_ctrl_write(val,&cmicx->cmc1.packet_dma[6]); 2050 } 2051 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch6_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[6].desc_addr) ) 2052 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch6_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[6].desc_addr) ) 2053 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch6_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[6].desc_addr) ) 2054 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch6_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[6].desc_addr) ) 2055 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch6_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[6].desc_halt_addr) ) 2056 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch6_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[6].desc_halt_addr) ) 2057 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch6_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[6].desc_halt_addr) ) 2058 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch6_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[6].desc_halt_addr) ) 2059 bool cmic_cmc1_pktdma_ch6_stat_read(reg_t *val) { 2060 return cmic_pktdma_stat_read(val,&cmicx->cmc1.packet_dma[6]); 2061 } 2062 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch6_stat_write ) 2063 bool cmic_cmc1_pktdma_ch6_cos_ctrl_rx_0_read(reg_t *val) { 2064 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc1.packet_dma[6]); 2065 } 2066 bool cmic_cmc1_pktdma_ch6_cos_ctrl_rx_0_write(reg_t val) { 2067 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc1.packet_dma[6]); 2068 } 2069 bool cmic_cmc1_pktdma_ch6_cos_ctrl_rx_1_read(reg_t *val) { 2070 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc1.packet_dma[6]); 2071 } 2072 bool cmic_cmc1_pktdma_ch6_cos_ctrl_rx_1_write(reg_t val) { 2073 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc1.packet_dma[6]); 2074 } 2075 bool cmic_cmc1_pktdma_ch6_intr_coal_read(reg_t *val) { 2076 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc1.packet_dma[6]); 2077 } 2078 bool cmic_cmc1_pktdma_ch6_intr_coal_write(reg_t val) { 2079 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc1.packet_dma[6]); 2080 } 2081 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch6_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[6].cur_desc_addr) ) 2082 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch6_curr_desc_lo_write ) 2083 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch6_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[6].cur_desc_addr) ) 2084 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch6_curr_desc_hi_write ) 2085 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch6_pkt_count_rxpkt_read, cmicx->cmc1.packet_dma[6].rxpkt_count) 2086 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch6_pkt_count_rxpkt_write) 2087 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch6_pkt_count_txpkt_read, cmicx->cmc1.packet_dma[6].txpkt_count) 2088 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch6_pkt_count_txpkt_write) 2089 2090 /* cmc1 packet dma ch7 */ 2091 bool cmic_cmc1_pktdma_ch7_ctrl_read(reg_t *val) { 2092 return cmic_pktdma_ctrl_read(val,&cmicx->cmc1.packet_dma[7]); 2093 } 2094 bool cmic_cmc1_pktdma_ch7_ctrl_write(reg_t val) { 2095 return cmic_pktdma_ctrl_write(val,&cmicx->cmc1.packet_dma[7]); 2096 } 2097 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch7_desc_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[7].desc_addr) ) 2098 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch7_desc_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[7].desc_addr) ) 2099 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch7_desc_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[7].desc_addr) ) 2100 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch7_desc_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[7].desc_addr) ) 2101 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch7_desc_halt_addr_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[7].desc_halt_addr) ) 2102 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch7_desc_halt_addr_lo_write, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[7].desc_halt_addr) ) 2103 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch7_desc_halt_addr_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[7].desc_halt_addr) ) 2104 PCID_REG_WRITE_FUNC_GEN( cmic_cmc1_pktdma_ch7_desc_halt_addr_hi_write, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[7].desc_halt_addr) ) 2105 bool cmic_cmc1_pktdma_ch7_stat_read(reg_t *val) { 2106 return cmic_pktdma_stat_read(val,&cmicx->cmc1.packet_dma[7]); 2107 } 2108 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch7_stat_write ) 2109 bool cmic_cmc1_pktdma_ch7_cos_ctrl_rx_0_read(reg_t *val) { 2110 return cmic_pktdma_cos_ctrl_rx_0_read(val,&cmicx->cmc1.packet_dma[7]); 2111 } 2112 bool cmic_cmc1_pktdma_ch7_cos_ctrl_rx_0_write(reg_t val) { 2113 return cmic_pktdma_cos_ctrl_rx_0_write(val,&cmicx->cmc1.packet_dma[7]); 2114 } 2115 bool cmic_cmc1_pktdma_ch7_cos_ctrl_rx_1_read(reg_t *val) { 2116 return cmic_pktdma_cos_ctrl_rx_1_read(val,&cmicx->cmc1.packet_dma[7]); 2117 } 2118 bool cmic_cmc1_pktdma_ch7_cos_ctrl_rx_1_write(reg_t val) { 2119 return cmic_pktdma_cos_ctrl_rx_1_write(val,&cmicx->cmc1.packet_dma[7]); 2120 } 2121 bool cmic_cmc1_pktdma_ch7_intr_coal_read(reg_t *val) { 2122 return cmic_pktdma_intr_coal_read(val,&cmicx->cmc1.packet_dma[7]); 2123 } 2124 bool cmic_cmc1_pktdma_ch7_intr_coal_write(reg_t val) { 2125 return cmic_pktdma_intr_coal_write(val,&cmicx->cmc1.packet_dma[7]); 2126 } 2127 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch7_curr_desc_lo_read, UINT64_LOWER32_REFERENCE(cmicx->cmc1.packet_dma[7].cur_desc_addr) ) 2128 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch7_curr_desc_lo_write ) 2129 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch7_curr_desc_hi_read, UINT64_UPPER32_REFERENCE(cmicx->cmc1.packet_dma[7].cur_desc_addr) ) 2130 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch7_curr_desc_hi_write ) 2131 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch7_pkt_count_rxpkt_read, cmicx->cmc1.packet_dma[7].rxpkt_count) 2132 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch7_pkt_count_rxpkt_write) 2133 PCID_REG_READ_FUNC_GEN( cmic_cmc1_pktdma_ch7_pkt_count_txpkt_read, cmicx->cmc1.packet_dma[7].txpkt_count) 2134 PCID_REG_WRITE_NULL_FUNC_GEN( cmic_cmc1_pktdma_ch7_pkt_count_txpkt_write) 2135 2136