cmicx_sim.h (88144B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 8 /* 9 * cmicx_sim.h 10 * 11 * header for the cmic module 12 */ 13 14 15 #ifndef _CMICX_SIM_H_ 16 #define _CMICX_SIM_H_ 17 18 19 /* includes */ 20 #include "../../../include/soc/mcm/cmicx.h" 21 #include "cmicx_sim_schan.h" 22 #include "cmicx_sim_sbus_dma.h" 23 #include "cmicx_sim_packet_dma.h" 24 25 26 /*****************************************************/ 27 /* defines for CMIC pci-available register addresses */ 28 /*****************************************************/ 29 30 /* general PCID stuff */ 31 #define NUM_PCID_REGISTERS (NUM_CMICX_REGS+1) /* +1 because of control reg */ 32 #define MAX_PCID_MEM_VALUES 1000000 /* number of cmicx sim memory 33 values able to be stored 34 (statically allocated upon 35 initialization) */ 36 #define CMICX_MAX_SWITCH_REGISTERS 1000 /* maximum number of switch 37 registers that we can/will 38 store. */ 39 #define CMICX_MAX_SWITCH_MEMORIES 1000000 /* maximum number of switch 40 memory values that we can/ 41 will store. */ 42 #define CMICX_SIM_PCI_BASE_ADDR 0x03200000 43 #define CMICX_SIM_CONTROL_REG_ADDR 0xFFFF0 44 45 /* schan registers */ 46 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SCHAN_REG_ADDR CMIC_TOP_SBUS_RING_ARB_CTRL_SCHAN_OFFSET 47 #define CMIC_TOP_SBUS_TIMEOUT_REG_ADDR CMIC_TOP_SBUS_TIMEOUT_OFFSET 48 #define CMIC_TOP_SBUS_RING_MAP_0_7_REG_ADDR CMIC_TOP_SBUS_RING_MAP_0_7_OFFSET 49 #define CMIC_TOP_SBUS_RING_MAP_8_15_REG_ADDR CMIC_TOP_SBUS_RING_MAP_8_15_OFFSET 50 #define CMIC_TOP_SBUS_RING_MAP_16_23_REG_ADDR CMIC_TOP_SBUS_RING_MAP_16_23_OFFSET 51 #define CMIC_TOP_SBUS_RING_MAP_24_31_REG_ADDR CMIC_TOP_SBUS_RING_MAP_24_31_OFFSET 52 #define CMIC_TOP_SBUS_RING_MAP_32_39_REG_ADDR CMIC_TOP_SBUS_RING_MAP_32_39_OFFSET 53 #define CMIC_TOP_SBUS_RING_MAP_40_47_REG_ADDR CMIC_TOP_SBUS_RING_MAP_40_47_OFFSET 54 #define CMIC_TOP_SBUS_RING_MAP_48_55_REG_ADDR CMIC_TOP_SBUS_RING_MAP_48_55_OFFSET 55 #define CMIC_TOP_SBUS_RING_MAP_56_63_REG_ADDR CMIC_TOP_SBUS_RING_MAP_56_63_OFFSET 56 #define CMIC_TOP_SBUS_RING_MAP_64_71_REG_ADDR CMIC_TOP_SBUS_RING_MAP_64_71_OFFSET 57 #define CMIC_TOP_SBUS_RING_MAP_72_79_REG_ADDR CMIC_TOP_SBUS_RING_MAP_72_79_OFFSET 58 #define CMIC_TOP_SBUS_RING_MAP_80_87_REG_ADDR CMIC_TOP_SBUS_RING_MAP_80_87_OFFSET 59 #define CMIC_TOP_SBUS_RING_MAP_88_95_REG_ADDR CMIC_TOP_SBUS_RING_MAP_88_95_OFFSET 60 #define CMIC_TOP_SBUS_RING_MAP_96_103_REG_ADDR CMIC_TOP_SBUS_RING_MAP_96_103_OFFSET 61 #define CMIC_TOP_SBUS_RING_MAP_104_111_REG_ADDR CMIC_TOP_SBUS_RING_MAP_104_111_OFFSET 62 #define CMIC_TOP_SBUS_RING_MAP_112_119_REG_ADDR CMIC_TOP_SBUS_RING_MAP_112_119_OFFSET 63 #define CMIC_TOP_SBUS_RING_MAP_120_127_REG_ADDR CMIC_TOP_SBUS_RING_MAP_120_127_OFFSET 64 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE0_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x00) 65 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE1_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x04) 66 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE2_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x08) 67 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE3_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x0C) 68 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE4_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x10) 69 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE5_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x14) 70 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE6_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x18) 71 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE7_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x1C) 72 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE8_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x20) 73 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE9_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x24) 74 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE10_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x28) 75 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE11_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x2C) 76 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE12_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x30) 77 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE13_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x34) 78 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE14_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x38) 79 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE15_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x3C) 80 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE16_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x40) 81 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE17_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x44) 82 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE18_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x48) 83 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE19_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x4C) 84 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE20_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x50) 85 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE21_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + 0x54) 86 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE0_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x00) 87 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE1_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x04) 88 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE2_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x08) 89 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE3_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x0C) 90 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE4_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x10) 91 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE5_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x14) 92 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE6_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x18) 93 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE7_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x1C) 94 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE8_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x20) 95 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE9_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x24) 96 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE10_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x28) 97 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE11_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x2C) 98 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE12_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x30) 99 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE13_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x34) 100 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE14_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x38) 101 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE15_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x3C) 102 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE16_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x40) 103 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE17_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x44) 104 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE18_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x48) 105 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE19_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x4C) 106 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE20_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x50) 107 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE21_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET + 0x54) 108 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE0_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x00) 109 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE1_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x04) 110 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE2_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x08) 111 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE3_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x0C) 112 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE4_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x10) 113 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE5_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x14) 114 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE6_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x18) 115 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE7_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x1C) 116 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE8_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x20) 117 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE9_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x24) 118 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE10_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x28) 119 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE11_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x2C) 120 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE12_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x30) 121 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE13_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x34) 122 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE14_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x38) 123 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE15_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x3C) 124 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE16_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x40) 125 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE17_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x44) 126 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE18_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x48) 127 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE19_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x4C) 128 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE20_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x50) 129 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE21_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET + 0x54) 130 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE0_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x00) 131 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE1_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x04) 132 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE2_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x08) 133 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE3_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x0C) 134 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE4_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x10) 135 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE5_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x14) 136 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE6_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x18) 137 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE7_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x1C) 138 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE8_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x20) 139 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE9_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x24) 140 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE10_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x28) 141 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE11_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x2C) 142 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE12_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x30) 143 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE13_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x34) 144 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE14_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x38) 145 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE15_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x3C) 146 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE16_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x40) 147 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE17_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x44) 148 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE18_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x48) 149 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE19_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x4C) 150 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE20_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x50) 151 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE21_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET + 0x54) 152 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE0_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x00) 153 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE1_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x04) 154 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE2_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x08) 155 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE3_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x0C) 156 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE4_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x10) 157 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE5_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x14) 158 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE6_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x18) 159 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE7_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x1C) 160 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE8_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x20) 161 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE9_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x24) 162 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE10_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x28) 163 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE11_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x2C) 164 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE12_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x30) 165 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE13_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x34) 166 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE14_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x38) 167 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE15_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x3C) 168 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE16_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x40) 169 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE17_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x44) 170 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE18_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x48) 171 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE19_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x4C) 172 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE20_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x50) 173 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE21_REG_ADDR (CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET + 0x54) 174 #define CMIC_COMMON_POOL_SCHAN_CH0_CTRL_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH0_CTRL_OFFSET 175 #define CMIC_COMMON_POOL_SCHAN_CH0_ACK_DATA_BEAT_COUNT_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH0_ACK_DATA_BEAT_COUNT_OFFSET 176 #define CMIC_COMMON_POOL_SCHAN_CH0_ERR_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH0_ERR_OFFSET 177 #define CMIC_COMMON_POOL_SCHAN_CH1_CTRL_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH1_CTRL_OFFSET 178 #define CMIC_COMMON_POOL_SCHAN_CH1_ACK_DATA_BEAT_COUNT_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH1_ACK_DATA_BEAT_COUNT_OFFSET 179 #define CMIC_COMMON_POOL_SCHAN_CH1_ERR_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH1_ERR_OFFSET 180 #define CMIC_COMMON_POOL_SCHAN_CH2_CTRL_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH2_CTRL_OFFSET 181 #define CMIC_COMMON_POOL_SCHAN_CH2_ACK_DATA_BEAT_COUNT_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH2_ACK_DATA_BEAT_COUNT_OFFSET 182 #define CMIC_COMMON_POOL_SCHAN_CH2_ERR_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH2_ERR_OFFSET 183 #define CMIC_COMMON_POOL_SCHAN_CH3_CTRL_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH3_CTRL_OFFSET 184 #define CMIC_COMMON_POOL_SCHAN_CH3_ACK_DATA_BEAT_COUNT_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH3_ACK_DATA_BEAT_COUNT_OFFSET 185 #define CMIC_COMMON_POOL_SCHAN_CH3_ERR_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH3_ERR_OFFSET 186 #define CMIC_COMMON_POOL_SCHAN_CH4_CTRL_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH4_CTRL_OFFSET 187 #define CMIC_COMMON_POOL_SCHAN_CH4_ACK_DATA_BEAT_COUNT_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH4_ACK_DATA_BEAT_COUNT_OFFSET 188 #define CMIC_COMMON_POOL_SCHAN_CH4_ERR_REG_ADDR CMIC_COMMON_POOL_SCHAN_CH4_ERR_OFFSET 189 190 /* sbus dma registers */ 191 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_ADDR CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_OFFSET 192 #define CMIC_CMC0_SHARED_CONFIG_REG_ADDR CMIC_CMC0_SHARED_CONFIG_OFFSET 193 #define CMIC_CMC0_SBUSDMA_CH0_CONTROL_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CONTROL_OFFSET 194 #define CMIC_CMC0_SBUSDMA_CH0_REQUEST_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_REQUEST_OFFSET 195 #define CMIC_CMC0_SBUSDMA_CH0_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_COUNT_OFFSET 196 #define CMIC_CMC0_SBUSDMA_CH0_OPCODE_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_OPCODE_OFFSET 197 #define CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET 198 #define CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_OFFSET 199 #define CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_OFFSET 200 #define CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LO_OFFSET 201 #define CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HI_OFFSET 202 #define CMIC_CMC0_SBUSDMA_CH0_STATUS_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_STATUS_OFFSET 203 #define CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO_OFFSET 204 #define CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI_OFFSET 205 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESS_OFFSET 206 #define CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO_OFFSET 207 #define CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI_OFFSET 208 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET 209 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET 210 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET 211 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET 212 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET 213 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_OFFSET 214 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_OFFSET 215 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_OFFSET 216 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET 217 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET 218 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL_OFFSET 219 #define CMIC_CMC0_SBUSDMA_CH0_TIMER_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_TIMER_OFFSET 220 #define CMIC_CMC0_SBUSDMA_CH0_ITER_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_ITER_COUNT_OFFSET 221 #define CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_0_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_0_OFFSET 222 #define CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_1_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_1_OFFSET 223 #define CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_2_REG_ADDR CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_2_OFFSET 224 #define CMIC_CMC0_SBUSDMA_CH1_CONTROL_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CONTROL_OFFSET 225 #define CMIC_CMC0_SBUSDMA_CH1_REQUEST_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_REQUEST_OFFSET 226 #define CMIC_CMC0_SBUSDMA_CH1_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_COUNT_OFFSET 227 #define CMIC_CMC0_SBUSDMA_CH1_OPCODE_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_OPCODE_OFFSET 228 #define CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESS_OFFSET 229 #define CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO_OFFSET 230 #define CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI_OFFSET 231 #define CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_LO_OFFSET 232 #define CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_HI_OFFSET 233 #define CMIC_CMC0_SBUSDMA_CH1_STATUS_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_STATUS_OFFSET 234 #define CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO_OFFSET 235 #define CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI_OFFSET 236 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESS_OFFSET 237 #define CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO_OFFSET 238 #define CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI_OFFSET 239 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET 240 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET 241 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET 242 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET 243 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET 244 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_OFFSET 245 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_OFFSET 246 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_OFFSET 247 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET 248 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET 249 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL_OFFSET 250 #define CMIC_CMC0_SBUSDMA_CH1_TIMER_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_TIMER_OFFSET 251 #define CMIC_CMC0_SBUSDMA_CH1_ITER_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_ITER_COUNT_OFFSET 252 #define CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_0_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_0_OFFSET 253 #define CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_1_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_1_OFFSET 254 #define CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_2_REG_ADDR CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_2_OFFSET 255 #define CMIC_CMC0_SBUSDMA_CH2_CONTROL_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CONTROL_OFFSET 256 #define CMIC_CMC0_SBUSDMA_CH2_REQUEST_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_REQUEST_OFFSET 257 #define CMIC_CMC0_SBUSDMA_CH2_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_COUNT_OFFSET 258 #define CMIC_CMC0_SBUSDMA_CH2_OPCODE_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_OPCODE_OFFSET 259 #define CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESS_OFFSET 260 #define CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO_OFFSET 261 #define CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI_OFFSET 262 #define CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_LO_OFFSET 263 #define CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_HI_OFFSET 264 #define CMIC_CMC0_SBUSDMA_CH2_STATUS_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_STATUS_OFFSET 265 #define CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO_OFFSET 266 #define CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI_OFFSET 267 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESS_OFFSET 268 #define CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO_OFFSET 269 #define CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI_OFFSET 270 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET 271 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET 272 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET 273 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET 274 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET 275 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_OFFSET 276 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_OFFSET 277 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_OFFSET 278 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET 279 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET 280 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL_OFFSET 281 #define CMIC_CMC0_SBUSDMA_CH2_TIMER_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_TIMER_OFFSET 282 #define CMIC_CMC0_SBUSDMA_CH2_ITER_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_ITER_COUNT_OFFSET 283 #define CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_0_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_0_OFFSET 284 #define CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_1_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_1_OFFSET 285 #define CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_2_REG_ADDR CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_2_OFFSET 286 #define CMIC_CMC0_SBUSDMA_CH3_CONTROL_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CONTROL_OFFSET 287 #define CMIC_CMC0_SBUSDMA_CH3_REQUEST_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_REQUEST_OFFSET 288 #define CMIC_CMC0_SBUSDMA_CH3_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_COUNT_OFFSET 289 #define CMIC_CMC0_SBUSDMA_CH3_OPCODE_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_OPCODE_OFFSET 290 #define CMIC_CMC0_SBUSDMA_CH3_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_SBUS_START_ADDRESS_OFFSET 291 #define CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO_OFFSET 292 #define CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI_OFFSET 293 #define CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_LO_OFFSET 294 #define CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_HI_OFFSET 295 #define CMIC_CMC0_SBUSDMA_CH3_STATUS_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_STATUS_OFFSET 296 #define CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO_OFFSET 297 #define CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI_OFFSET 298 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUS_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_SBUS_ADDRESS_OFFSET 299 #define CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO_OFFSET 300 #define CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI_OFFSET 301 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET 302 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET 303 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET 304 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET 305 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET 306 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT_OFFSET 307 #define CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_OFFSET 308 #define CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR_OFFSET 309 #define CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET 310 #define CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET 311 #define CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_CONTROL_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_CONTROL_OFFSET 312 #define CMIC_CMC0_SBUSDMA_CH3_TIMER_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_TIMER_OFFSET 313 #define CMIC_CMC0_SBUSDMA_CH3_ITER_COUNT_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_ITER_COUNT_OFFSET 314 #define CMIC_CMC0_SBUSDMA_CH3_TM_CONTROL_0_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_TM_CONTROL_0_OFFSET 315 #define CMIC_CMC0_SBUSDMA_CH3_TM_CONTROL_1_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_TM_CONTROL_1_OFFSET 316 #define CMIC_CMC0_SBUSDMA_CH3_TM_CONTROL_2_REG_ADDR CMIC_CMC0_SBUSDMA_CH3_TM_CONTROL_2_OFFSET 317 #define CMIC_CMC1_SHARED_CONFIG_REG_ADDR CMIC_CMC1_SHARED_CONFIG_OFFSET 318 #define CMIC_CMC1_SBUSDMA_CH0_CONTROL_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CONTROL_OFFSET 319 #define CMIC_CMC1_SBUSDMA_CH0_REQUEST_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_REQUEST_OFFSET 320 #define CMIC_CMC1_SBUSDMA_CH0_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_COUNT_OFFSET 321 #define CMIC_CMC1_SBUSDMA_CH0_OPCODE_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_OPCODE_OFFSET 322 #define CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET 323 #define CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_OFFSET 324 #define CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_OFFSET 325 #define CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_LO_OFFSET 326 #define CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_HI_OFFSET 327 #define CMIC_CMC1_SBUSDMA_CH0_STATUS_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_STATUS_OFFSET 328 #define CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO_OFFSET 329 #define CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI_OFFSET 330 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESS_OFFSET 331 #define CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO_OFFSET 332 #define CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI_OFFSET 333 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET 334 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET 335 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET 336 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET 337 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET 338 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_OFFSET 339 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_OFFSET 340 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_OFFSET 341 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET 342 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET 343 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL_OFFSET 344 #define CMIC_CMC1_SBUSDMA_CH0_TIMER_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_TIMER_OFFSET 345 #define CMIC_CMC1_SBUSDMA_CH0_ITER_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_ITER_COUNT_OFFSET 346 #define CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_0_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_0_OFFSET 347 #define CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_1_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_1_OFFSET 348 #define CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_2_REG_ADDR CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_2_OFFSET 349 #define CMIC_CMC1_SBUSDMA_CH1_CONTROL_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CONTROL_OFFSET 350 #define CMIC_CMC1_SBUSDMA_CH1_REQUEST_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_REQUEST_OFFSET 351 #define CMIC_CMC1_SBUSDMA_CH1_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_COUNT_OFFSET 352 #define CMIC_CMC1_SBUSDMA_CH1_OPCODE_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_OPCODE_OFFSET 353 #define CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESS_OFFSET 354 #define CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO_OFFSET 355 #define CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI_OFFSET 356 #define CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_LO_OFFSET 357 #define CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_HI_OFFSET 358 #define CMIC_CMC1_SBUSDMA_CH1_STATUS_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_STATUS_OFFSET 359 #define CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO_OFFSET 360 #define CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI_OFFSET 361 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESS_OFFSET 362 #define CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO_OFFSET 363 #define CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI_OFFSET 364 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET 365 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET 366 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET 367 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET 368 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET 369 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_OFFSET 370 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_OFFSET 371 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_OFFSET 372 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET 373 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET 374 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL_OFFSET 375 #define CMIC_CMC1_SBUSDMA_CH1_TIMER_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_TIMER_OFFSET 376 #define CMIC_CMC1_SBUSDMA_CH1_ITER_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_ITER_COUNT_OFFSET 377 #define CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_0_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_0_OFFSET 378 #define CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_1_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_1_OFFSET 379 #define CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_2_REG_ADDR CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_2_OFFSET 380 #define CMIC_CMC1_SBUSDMA_CH2_CONTROL_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CONTROL_OFFSET 381 #define CMIC_CMC1_SBUSDMA_CH2_REQUEST_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_REQUEST_OFFSET 382 #define CMIC_CMC1_SBUSDMA_CH2_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_COUNT_OFFSET 383 #define CMIC_CMC1_SBUSDMA_CH2_OPCODE_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_OPCODE_OFFSET 384 #define CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESS_OFFSET 385 #define CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO_OFFSET 386 #define CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI_OFFSET 387 #define CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_LO_OFFSET 388 #define CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_HI_OFFSET 389 #define CMIC_CMC1_SBUSDMA_CH2_STATUS_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_STATUS_OFFSET 390 #define CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO_OFFSET 391 #define CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI_OFFSET 392 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESS_OFFSET 393 #define CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO_OFFSET 394 #define CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI_OFFSET 395 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET 396 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET 397 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET 398 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET 399 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET 400 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_OFFSET 401 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_OFFSET 402 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_OFFSET 403 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET 404 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET 405 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL_OFFSET 406 #define CMIC_CMC1_SBUSDMA_CH2_TIMER_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_TIMER_OFFSET 407 #define CMIC_CMC1_SBUSDMA_CH2_ITER_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_ITER_COUNT_OFFSET 408 #define CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_0_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_0_OFFSET 409 #define CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_1_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_1_OFFSET 410 #define CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_2_REG_ADDR CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_2_OFFSET 411 #define CMIC_CMC1_SBUSDMA_CH3_CONTROL_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CONTROL_OFFSET 412 #define CMIC_CMC1_SBUSDMA_CH3_REQUEST_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_REQUEST_OFFSET 413 #define CMIC_CMC1_SBUSDMA_CH3_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_COUNT_OFFSET 414 #define CMIC_CMC1_SBUSDMA_CH3_OPCODE_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_OPCODE_OFFSET 415 #define CMIC_CMC1_SBUSDMA_CH3_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_SBUS_START_ADDRESS_OFFSET 416 #define CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO_OFFSET 417 #define CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI_OFFSET 418 #define CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_LO_OFFSET 419 #define CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_HI_OFFSET 420 #define CMIC_CMC1_SBUSDMA_CH3_STATUS_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_STATUS_OFFSET 421 #define CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO_OFFSET 422 #define CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI_OFFSET 423 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUS_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_SBUS_ADDRESS_OFFSET 424 #define CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO_OFFSET 425 #define CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI_OFFSET 426 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET 427 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET 428 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET 429 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET 430 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET 431 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT_OFFSET 432 #define CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_OFFSET 433 #define CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR_OFFSET 434 #define CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET 435 #define CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET 436 #define CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_CONTROL_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_CONTROL_OFFSET 437 #define CMIC_CMC1_SBUSDMA_CH3_TIMER_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_TIMER_OFFSET 438 #define CMIC_CMC1_SBUSDMA_CH3_ITER_COUNT_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_ITER_COUNT_OFFSET 439 #define CMIC_CMC1_SBUSDMA_CH3_TM_CONTROL_0_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_TM_CONTROL_0_OFFSET 440 #define CMIC_CMC1_SBUSDMA_CH3_TM_CONTROL_1_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_TM_CONTROL_1_OFFSET 441 #define CMIC_CMC1_SBUSDMA_CH3_TM_CONTROL_2_REG_ADDR CMIC_CMC1_SBUSDMA_CH3_TM_CONTROL_2_OFFSET 442 443 /* packet dma registers */ 444 #define CMIC_TOP_CONFIG_REG_ADDR CMIC_TOP_CONFIG_OFFSET 445 #define CMIC_TOP_EPINTF_RELEASE_ALL_CREDITS_REG_ADDR CMIC_TOP_EPINTF_RELEASE_ALL_CREDITS_OFFSET 446 #define CMIC_CMC0_SHARED_IRQ_STAT0_REG_ADDR CMIC_CMC0_SHARED_IRQ_STAT0_OFFSET 447 #define CMIC_CMC0_SHARED_IRQ_STAT1_REG_ADDR CMIC_CMC0_SHARED_IRQ_STAT1_OFFSET 448 #define CMIC_CMC0_SHARED_IRQ_STAT_CLR0_REG_ADDR CMIC_CMC0_SHARED_IRQ_STAT_CLR0_OFFSET 449 #define CMIC_CMC0_PKTDMA_CH0_CTRL_REG_ADDR CMIC_CMC0_PKTDMA_CH0_CTRL_OFFSET 450 #define CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO_OFFSET 451 #define CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI_OFFSET 452 #define CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_LO_OFFSET 453 #define CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_HI_OFFSET 454 #define CMIC_CMC0_PKTDMA_CH0_STAT_REG_ADDR CMIC_CMC0_PKTDMA_CH0_STAT_OFFSET 455 #define CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_0_REG_ADDR CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_0_OFFSET 456 #define CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_1_REG_ADDR CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_1_OFFSET 457 #define CMIC_CMC0_PKTDMA_CH0_INTR_COAL_REG_ADDR CMIC_CMC0_PKTDMA_CH0_INTR_COAL_OFFSET 458 #define CMIC_CMC0_PKTDMA_CH0_CURR_DESC_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH0_CURR_DESC_LO_OFFSET 459 #define CMIC_CMC0_PKTDMA_CH0_CURR_DESC_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH0_CURR_DESC_HI_OFFSET 460 #define CMIC_CMC0_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC0_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET 461 #define CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT_OFFSET 462 #define CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_TXPKT_OFFSET 463 #define CMIC_CMC0_PKTDMA_CH1_CTRL_REG_ADDR CMIC_CMC0_PKTDMA_CH1_CTRL_OFFSET 464 #define CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_LO_OFFSET 465 #define CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_HI_OFFSET 466 #define CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_LO_OFFSET 467 #define CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_HI_OFFSET 468 #define CMIC_CMC0_PKTDMA_CH1_STAT_REG_ADDR CMIC_CMC0_PKTDMA_CH1_STAT_OFFSET 469 #define CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_0_REG_ADDR CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_0_OFFSET 470 #define CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_1_REG_ADDR CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_1_OFFSET 471 #define CMIC_CMC0_PKTDMA_CH1_INTR_COAL_REG_ADDR CMIC_CMC0_PKTDMA_CH1_INTR_COAL_OFFSET 472 #define CMIC_CMC0_PKTDMA_CH1_CURR_DESC_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH1_CURR_DESC_LO_OFFSET 473 #define CMIC_CMC0_PKTDMA_CH1_CURR_DESC_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH1_CURR_DESC_HI_OFFSET 474 #define CMIC_CMC0_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC0_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG_OFFSET 475 #define CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT_OFFSET 476 #define CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_TXPKT_OFFSET 477 #define CMIC_CMC0_PKTDMA_CH2_CTRL_REG_ADDR CMIC_CMC0_PKTDMA_CH2_CTRL_OFFSET 478 #define CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_LO_OFFSET 479 #define CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_HI_OFFSET 480 #define CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_LO_OFFSET 481 #define CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_HI_OFFSET 482 #define CMIC_CMC0_PKTDMA_CH2_STAT_REG_ADDR CMIC_CMC0_PKTDMA_CH2_STAT_OFFSET 483 #define CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_0_REG_ADDR CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_0_OFFSET 484 #define CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_1_REG_ADDR CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_1_OFFSET 485 #define CMIC_CMC0_PKTDMA_CH2_INTR_COAL_REG_ADDR CMIC_CMC0_PKTDMA_CH2_INTR_COAL_OFFSET 486 #define CMIC_CMC0_PKTDMA_CH2_CURR_DESC_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH2_CURR_DESC_LO_OFFSET 487 #define CMIC_CMC0_PKTDMA_CH2_CURR_DESC_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH2_CURR_DESC_HI_OFFSET 488 #define CMIC_CMC0_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC0_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG_OFFSET 489 #define CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT_OFFSET 490 #define CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_TXPKT_OFFSET 491 #define CMIC_CMC0_PKTDMA_CH3_CTRL_REG_ADDR CMIC_CMC0_PKTDMA_CH3_CTRL_OFFSET 492 #define CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_LO_OFFSET 493 #define CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_HI_OFFSET 494 #define CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_LO_OFFSET 495 #define CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_HI_OFFSET 496 #define CMIC_CMC0_PKTDMA_CH3_STAT_REG_ADDR CMIC_CMC0_PKTDMA_CH3_STAT_OFFSET 497 #define CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_0_REG_ADDR CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_0_OFFSET 498 #define CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_1_REG_ADDR CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_1_OFFSET 499 #define CMIC_CMC0_PKTDMA_CH3_INTR_COAL_REG_ADDR CMIC_CMC0_PKTDMA_CH3_INTR_COAL_OFFSET 500 #define CMIC_CMC0_PKTDMA_CH3_CURR_DESC_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH3_CURR_DESC_LO_OFFSET 501 #define CMIC_CMC0_PKTDMA_CH3_CURR_DESC_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH3_CURR_DESC_HI_OFFSET 502 #define CMIC_CMC0_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC0_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG_OFFSET 503 #define CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT_OFFSET 504 #define CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_TXPKT_OFFSET 505 #define CMIC_CMC0_PKTDMA_CH4_CTRL_REG_ADDR CMIC_CMC0_PKTDMA_CH4_CTRL_OFFSET 506 #define CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_LO_OFFSET 507 #define CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_HI_OFFSET 508 #define CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_LO_OFFSET 509 #define CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_HI_OFFSET 510 #define CMIC_CMC0_PKTDMA_CH4_STAT_REG_ADDR CMIC_CMC0_PKTDMA_CH4_STAT_OFFSET 511 #define CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_0_REG_ADDR CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_0_OFFSET 512 #define CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_1_REG_ADDR CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_1_OFFSET 513 #define CMIC_CMC0_PKTDMA_CH4_INTR_COAL_REG_ADDR CMIC_CMC0_PKTDMA_CH4_INTR_COAL_OFFSET 514 #define CMIC_CMC0_PKTDMA_CH4_CURR_DESC_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH4_CURR_DESC_LO_OFFSET 515 #define CMIC_CMC0_PKTDMA_CH4_CURR_DESC_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH4_CURR_DESC_HI_OFFSET 516 #define CMIC_CMC0_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC0_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG_OFFSET 517 #define CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT_OFFSET 518 #define CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_TXPKT_OFFSET 519 #define CMIC_CMC0_PKTDMA_CH5_CTRL_REG_ADDR CMIC_CMC0_PKTDMA_CH5_CTRL_OFFSET 520 #define CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_LO_OFFSET 521 #define CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_HI_OFFSET 522 #define CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_LO_OFFSET 523 #define CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_HI_OFFSET 524 #define CMIC_CMC0_PKTDMA_CH5_STAT_REG_ADDR CMIC_CMC0_PKTDMA_CH5_STAT_OFFSET 525 #define CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_0_REG_ADDR CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_0_OFFSET 526 #define CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_1_REG_ADDR CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_1_OFFSET 527 #define CMIC_CMC0_PKTDMA_CH5_INTR_COAL_REG_ADDR CMIC_CMC0_PKTDMA_CH5_INTR_COAL_OFFSET 528 #define CMIC_CMC0_PKTDMA_CH5_CURR_DESC_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH5_CURR_DESC_LO_OFFSET 529 #define CMIC_CMC0_PKTDMA_CH5_CURR_DESC_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH5_CURR_DESC_HI_OFFSET 530 #define CMIC_CMC0_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC0_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG_OFFSET 531 #define CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT_OFFSET 532 #define CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_TXPKT_OFFSET 533 #define CMIC_CMC0_PKTDMA_CH6_CTRL_REG_ADDR CMIC_CMC0_PKTDMA_CH6_CTRL_OFFSET 534 #define CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_LO_OFFSET 535 #define CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_HI_OFFSET 536 #define CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_LO_OFFSET 537 #define CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_HI_OFFSET 538 #define CMIC_CMC0_PKTDMA_CH6_STAT_REG_ADDR CMIC_CMC0_PKTDMA_CH6_STAT_OFFSET 539 #define CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_0_REG_ADDR CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_0_OFFSET 540 #define CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_1_REG_ADDR CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_1_OFFSET 541 #define CMIC_CMC0_PKTDMA_CH6_INTR_COAL_REG_ADDR CMIC_CMC0_PKTDMA_CH6_INTR_COAL_OFFSET 542 #define CMIC_CMC0_PKTDMA_CH6_CURR_DESC_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH6_CURR_DESC_LO_OFFSET 543 #define CMIC_CMC0_PKTDMA_CH6_CURR_DESC_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH6_CURR_DESC_HI_OFFSET 544 #define CMIC_CMC0_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC0_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG_OFFSET 545 #define CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT_OFFSET 546 #define CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_TXPKT_OFFSET 547 #define CMIC_CMC0_PKTDMA_CH7_CTRL_REG_ADDR CMIC_CMC0_PKTDMA_CH7_CTRL_OFFSET 548 #define CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_LO_OFFSET 549 #define CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_HI_OFFSET 550 #define CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_LO_OFFSET 551 #define CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_HI_OFFSET 552 #define CMIC_CMC0_PKTDMA_CH7_STAT_REG_ADDR CMIC_CMC0_PKTDMA_CH7_STAT_OFFSET 553 #define CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_0_REG_ADDR CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_0_OFFSET 554 #define CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_1_REG_ADDR CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_1_OFFSET 555 #define CMIC_CMC0_PKTDMA_CH7_INTR_COAL_REG_ADDR CMIC_CMC0_PKTDMA_CH7_INTR_COAL_OFFSET 556 #define CMIC_CMC0_PKTDMA_CH7_CURR_DESC_LO_REG_ADDR CMIC_CMC0_PKTDMA_CH7_CURR_DESC_LO_OFFSET 557 #define CMIC_CMC0_PKTDMA_CH7_CURR_DESC_HI_REG_ADDR CMIC_CMC0_PKTDMA_CH7_CURR_DESC_HI_OFFSET 558 #define CMIC_CMC0_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC0_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG_OFFSET 559 #define CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT_OFFSET 560 #define CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_TXPKT_OFFSET 561 #define CMIC_CMC1_SHARED_IRQ_STAT0_REG_ADDR CMIC_CMC1_SHARED_IRQ_STAT0_OFFSET 562 #define CMIC_CMC1_SHARED_IRQ_STAT1_REG_ADDR CMIC_CMC1_SHARED_IRQ_STAT1_OFFSET 563 #define CMIC_CMC1_SHARED_IRQ_STAT_CLR0_REG_ADDR CMIC_CMC1_SHARED_IRQ_STAT_CLR0_OFFSET 564 #define CMIC_CMC1_PKTDMA_CH0_CTRL_REG_ADDR CMIC_CMC1_PKTDMA_CH0_CTRL_OFFSET 565 #define CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_LO_OFFSET 566 #define CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_HI_OFFSET 567 #define CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_LO_OFFSET 568 #define CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_HI_OFFSET 569 #define CMIC_CMC1_PKTDMA_CH0_STAT_REG_ADDR CMIC_CMC1_PKTDMA_CH0_STAT_OFFSET 570 #define CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_0_REG_ADDR CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_0_OFFSET 571 #define CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_1_REG_ADDR CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_1_OFFSET 572 #define CMIC_CMC1_PKTDMA_CH0_INTR_COAL_REG_ADDR CMIC_CMC1_PKTDMA_CH0_INTR_COAL_OFFSET 573 #define CMIC_CMC1_PKTDMA_CH0_CURR_DESC_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH0_CURR_DESC_LO_OFFSET 574 #define CMIC_CMC1_PKTDMA_CH0_CURR_DESC_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH0_CURR_DESC_HI_OFFSET 575 #define CMIC_CMC1_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC1_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET 576 #define CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT_OFFSET 577 #define CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_TXPKT_OFFSET 578 #define CMIC_CMC1_PKTDMA_CH1_CTRL_REG_ADDR CMIC_CMC1_PKTDMA_CH1_CTRL_OFFSET 579 #define CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_LO_OFFSET 580 #define CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_HI_OFFSET 581 #define CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_LO_OFFSET 582 #define CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_HI_OFFSET 583 #define CMIC_CMC1_PKTDMA_CH1_STAT_REG_ADDR CMIC_CMC1_PKTDMA_CH1_STAT_OFFSET 584 #define CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_0_REG_ADDR CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_0_OFFSET 585 #define CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_1_REG_ADDR CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_1_OFFSET 586 #define CMIC_CMC1_PKTDMA_CH1_INTR_COAL_REG_ADDR CMIC_CMC1_PKTDMA_CH1_INTR_COAL_OFFSET 587 #define CMIC_CMC1_PKTDMA_CH1_CURR_DESC_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH1_CURR_DESC_LO_OFFSET 588 #define CMIC_CMC1_PKTDMA_CH1_CURR_DESC_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH1_CURR_DESC_HI_OFFSET 589 #define CMIC_CMC1_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC1_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG_OFFSET 590 #define CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT_OFFSET 591 #define CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_TXPKT_OFFSET 592 #define CMIC_CMC1_PKTDMA_CH2_CTRL_REG_ADDR CMIC_CMC1_PKTDMA_CH2_CTRL_OFFSET 593 #define CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_LO_OFFSET 594 #define CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_HI_OFFSET 595 #define CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_LO_OFFSET 596 #define CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_HI_OFFSET 597 #define CMIC_CMC1_PKTDMA_CH2_STAT_REG_ADDR CMIC_CMC1_PKTDMA_CH2_STAT_OFFSET 598 #define CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_0_REG_ADDR CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_0_OFFSET 599 #define CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_1_REG_ADDR CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_1_OFFSET 600 #define CMIC_CMC1_PKTDMA_CH2_INTR_COAL_REG_ADDR CMIC_CMC1_PKTDMA_CH2_INTR_COAL_OFFSET 601 #define CMIC_CMC1_PKTDMA_CH2_CURR_DESC_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH2_CURR_DESC_LO_OFFSET 602 #define CMIC_CMC1_PKTDMA_CH2_CURR_DESC_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH2_CURR_DESC_HI_OFFSET 603 #define CMIC_CMC1_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC1_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG_OFFSET 604 #define CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT_OFFSET 605 #define CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_TXPKT_OFFSET 606 #define CMIC_CMC1_PKTDMA_CH3_CTRL_REG_ADDR CMIC_CMC1_PKTDMA_CH3_CTRL_OFFSET 607 #define CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_LO_OFFSET 608 #define CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_HI_OFFSET 609 #define CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_LO_OFFSET 610 #define CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_HI_OFFSET 611 #define CMIC_CMC1_PKTDMA_CH3_STAT_REG_ADDR CMIC_CMC1_PKTDMA_CH3_STAT_OFFSET 612 #define CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_0_REG_ADDR CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_0_OFFSET 613 #define CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_1_REG_ADDR CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_1_OFFSET 614 #define CMIC_CMC1_PKTDMA_CH3_INTR_COAL_REG_ADDR CMIC_CMC1_PKTDMA_CH3_INTR_COAL_OFFSET 615 #define CMIC_CMC1_PKTDMA_CH3_CURR_DESC_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH3_CURR_DESC_LO_OFFSET 616 #define CMIC_CMC1_PKTDMA_CH3_CURR_DESC_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH3_CURR_DESC_HI_OFFSET 617 #define CMIC_CMC1_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC1_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG_OFFSET 618 #define CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT_OFFSET 619 #define CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_TXPKT_OFFSET 620 #define CMIC_CMC1_PKTDMA_CH4_CTRL_REG_ADDR CMIC_CMC1_PKTDMA_CH4_CTRL_OFFSET 621 #define CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_LO_OFFSET 622 #define CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_HI_OFFSET 623 #define CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_LO_OFFSET 624 #define CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_HI_OFFSET 625 #define CMIC_CMC1_PKTDMA_CH4_STAT_REG_ADDR CMIC_CMC1_PKTDMA_CH4_STAT_OFFSET 626 #define CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_0_REG_ADDR CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_0_OFFSET 627 #define CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_1_REG_ADDR CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_1_OFFSET 628 #define CMIC_CMC1_PKTDMA_CH4_INTR_COAL_REG_ADDR CMIC_CMC1_PKTDMA_CH4_INTR_COAL_OFFSET 629 #define CMIC_CMC1_PKTDMA_CH4_CURR_DESC_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH4_CURR_DESC_LO_OFFSET 630 #define CMIC_CMC1_PKTDMA_CH4_CURR_DESC_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH4_CURR_DESC_HI_OFFSET 631 #define CMIC_CMC1_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC1_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG_OFFSET 632 #define CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT_OFFSET 633 #define CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_TXPKT_OFFSET 634 #define CMIC_CMC1_PKTDMA_CH5_CTRL_REG_ADDR CMIC_CMC1_PKTDMA_CH5_CTRL_OFFSET 635 #define CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_LO_OFFSET 636 #define CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_HI_OFFSET 637 #define CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_LO_OFFSET 638 #define CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_HI_OFFSET 639 #define CMIC_CMC1_PKTDMA_CH5_STAT_REG_ADDR CMIC_CMC1_PKTDMA_CH5_STAT_OFFSET 640 #define CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_0_REG_ADDR CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_0_OFFSET 641 #define CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_1_REG_ADDR CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_1_OFFSET 642 #define CMIC_CMC1_PKTDMA_CH5_INTR_COAL_REG_ADDR CMIC_CMC1_PKTDMA_CH5_INTR_COAL_OFFSET 643 #define CMIC_CMC1_PKTDMA_CH5_CURR_DESC_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH5_CURR_DESC_LO_OFFSET 644 #define CMIC_CMC1_PKTDMA_CH5_CURR_DESC_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH5_CURR_DESC_HI_OFFSET 645 #define CMIC_CMC1_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC1_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG_OFFSET 646 #define CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT_OFFSET 647 #define CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_TXPKT_OFFSET 648 #define CMIC_CMC1_PKTDMA_CH6_CTRL_REG_ADDR CMIC_CMC1_PKTDMA_CH6_CTRL_OFFSET 649 #define CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_LO_OFFSET 650 #define CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_HI_OFFSET 651 #define CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_LO_OFFSET 652 #define CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_HI_OFFSET 653 #define CMIC_CMC1_PKTDMA_CH6_STAT_REG_ADDR CMIC_CMC1_PKTDMA_CH6_STAT_OFFSET 654 #define CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_0_REG_ADDR CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_0_OFFSET 655 #define CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_1_REG_ADDR CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_1_OFFSET 656 #define CMIC_CMC1_PKTDMA_CH6_INTR_COAL_REG_ADDR CMIC_CMC1_PKTDMA_CH6_INTR_COAL_OFFSET 657 #define CMIC_CMC1_PKTDMA_CH6_CURR_DESC_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH6_CURR_DESC_LO_OFFSET 658 #define CMIC_CMC1_PKTDMA_CH6_CURR_DESC_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH6_CURR_DESC_HI_OFFSET 659 #define CMIC_CMC1_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC1_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG_OFFSET 660 #define CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT_OFFSET 661 #define CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_TXPKT_OFFSET 662 #define CMIC_CMC1_PKTDMA_CH7_CTRL_REG_ADDR CMIC_CMC1_PKTDMA_CH7_CTRL_OFFSET 663 #define CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_LO_OFFSET 664 #define CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_HI_OFFSET 665 #define CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_LO_OFFSET 666 #define CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_HI_OFFSET 667 #define CMIC_CMC1_PKTDMA_CH7_STAT_REG_ADDR CMIC_CMC1_PKTDMA_CH7_STAT_OFFSET 668 #define CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_0_REG_ADDR CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_0_OFFSET 669 #define CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_1_REG_ADDR CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_1_OFFSET 670 #define CMIC_CMC1_PKTDMA_CH7_INTR_COAL_REG_ADDR CMIC_CMC1_PKTDMA_CH7_INTR_COAL_OFFSET 671 #define CMIC_CMC1_PKTDMA_CH7_CURR_DESC_LO_REG_ADDR CMIC_CMC1_PKTDMA_CH7_CURR_DESC_LO_OFFSET 672 #define CMIC_CMC1_PKTDMA_CH7_CURR_DESC_HI_REG_ADDR CMIC_CMC1_PKTDMA_CH7_CURR_DESC_HI_OFFSET 673 #define CMIC_CMC1_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG_REG_ADDR CMIC_CMC1_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG_OFFSET 674 #define CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT_OFFSET 675 #define CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_TXPKT_REG_ADDR CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_TXPKT_OFFSET 676 677 /* schan fifo registers */ 678 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE0_REG_ADDR 0x18C0 679 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE1_REG_ADDR 0x18D0 680 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE2_REG_ADDR 0x18E0 681 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE3_REG_ADDR 0x18F0 682 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE4_REG_ADDR 0x1900 683 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE5_REG_ADDR 0x1910 684 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE6_REG_ADDR 0x1920 685 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE7_REG_ADDR 0x1930 686 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE8_REG_ADDR 0x1940 687 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE9_REG_ADDR 0x1950 688 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE10_REG_ADDR 0x1960 689 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE11_REG_ADDR 0x1970 690 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE12_REG_ADDR 0x1980 691 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE13_REG_ADDR 0x1990 692 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE14_REG_ADDR 0x19A0 693 #define CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE15_REG_ADDR 0x19B0 694 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE0_REG_ADDR 0x19C0 695 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE1_REG_ADDR 0x19D0 696 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE2_REG_ADDR 0x19E0 697 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE3_REG_ADDR 0x19F0 698 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE4_REG_ADDR 0x1A00 699 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE5_REG_ADDR 0x1A10 700 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE6_REG_ADDR 0x1A20 701 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE7_REG_ADDR 0x1A30 702 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE8_REG_ADDR 0x1A40 703 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE9_REG_ADDR 0x1A50 704 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE10_REG_ADDR 0x1A60 705 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE11_REG_ADDR 0x1A70 706 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE12_REG_ADDR 0x1A80 707 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE13_REG_ADDR 0x1A90 708 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE14_REG_ADDR 0x1AA0 709 #define CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE15_REG_ADDR 0x1AB0 710 #define CMIC_CMC0_SCHAN_FIFO_STATUS_BUFF1_REG_ADDR 0x1AC0 711 #define CMIC_CMC0_SCHAN_FIFO_STATUS_BUFF2_REG_ADDR 0x1AD0 712 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE0_REG_ADDR 0x18C0 713 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE1_REG_ADDR 0x18D0 714 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE2_REG_ADDR 0x18E0 715 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE3_REG_ADDR 0x18F0 716 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE4_REG_ADDR 0x1900 717 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE5_REG_ADDR 0x1910 718 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE6_REG_ADDR 0x1920 719 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE7_REG_ADDR 0x1930 720 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE8_REG_ADDR 0x1940 721 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE9_REG_ADDR 0x1950 722 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE10_REG_ADDR 0x1960 723 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE11_REG_ADDR 0x1970 724 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE12_REG_ADDR 0x1980 725 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE13_REG_ADDR 0x1990 726 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE14_REG_ADDR 0x19A0 727 #define CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE15_REG_ADDR 0x19B0 728 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE0_REG_ADDR 0x19C0 729 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE1_REG_ADDR 0x19D0 730 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE2_REG_ADDR 0x19E0 731 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE3_REG_ADDR 0x19F0 732 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE4_REG_ADDR 0x1A00 733 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE5_REG_ADDR 0x1A10 734 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE6_REG_ADDR 0x1A20 735 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE7_REG_ADDR 0x1A30 736 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE8_REG_ADDR 0x1A40 737 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE9_REG_ADDR 0x1A50 738 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE10_REG_ADDR 0x1A60 739 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE11_REG_ADDR 0x1A70 740 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE12_REG_ADDR 0x1A80 741 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE13_REG_ADDR 0x1A90 742 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE14_REG_ADDR 0x1AA0 743 #define CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE15_REG_ADDR 0x1AB0 744 #define CMIC_CMC1_SCHAN_FIFO_STATUS_BUFF1_REG_ADDR 0x1AC0 745 #define CMIC_CMC1_SCHAN_FIFO_STATUS_BUFF2_REG_ADDR 0x1AD0 746 747 748 /************************************************************************************/ 749 /* general-purpose macro definitions and other definitions for top-level cmic stuff */ 750 /************************************************************************************/ 751 752 /* general cmicx sim defines */ 753 #define CMICX_BYTES_PER_WORD 4 754 755 /* defines for cmicx sim constants */ 756 #define CMICX_NUM_CMC 2 757 #define CMICX_NUM_PACKET_DMA_PER_CMC 8 758 #define CMICX_NUM_SBUS_DMA_PER_CMC 4 759 #define CMICX_NUM_SCHAN_IN_COMMON 5 760 #define CMIC_CMC_ID_STRING_LENGTH 32 761 762 /* bits for cmicx sim control register */ 763 #define CMICX_SIM_CONTROL_REG_PCID_MEM_DUMP_BIT 0 764 #define CMICX_SIM_CONTROL_REG_SWITCH_REGISTERS_DUMP_BIT 1 765 #define CMICX_SIM_CONTROL_REG_SWITCH_MEMORIES_DUMP_BIT 2 766 #define CMICX_SIM_CONTROL_REG_LOG_LEVEL_CUTOFF_SET_BIT 15 767 #define CMICX_SIM_CONTROL_REG_LOG_LEVEL_CUTOFF_LSB 16 768 #define CMICX_SIM_CONTROL_REG_LOG_LEVEL_CUTOFF_MSB 23 769 770 771 /* macros to generate register access functions */ 772 #define PCID_REG_READ_FUNC_GEN(func_name,variable_name) bool func_name(reg_t *val) { *val = variable_name; return true; } 773 #define PCID_REG_READ_NULL_FUNC_GEN(func_name) bool func_name(reg_t *val) { *val = 0; return true; } 774 #define PCID_REG_WRITE_FUNC_GEN(func_name,variable_name) bool func_name(reg_t val) { variable_name = val; return true; } 775 #define PCID_REG_WRITE_NULL_FUNC_GEN(func_name) bool func_name(reg_t val) { return true; } 776 777 778 /* bit and field get/set macros for registers */ 779 #define REG_BIT_SET_TO(reg,bitnum,val) reg = (reg & ~(((reg_t)0x1)<<bitnum)) | (((reg_t)val)<<bitnum) 780 #define REG_BIT_SET(reg,bitnum) reg |= (((reg_t)0x1)<<bitnum) 781 #define REG_BIT_CLEAR(reg,bitnum) reg &= ~(((reg_t)0x1)<<bitnum) 782 #define REG_BIT_GET(reg,bitnum) ((reg & (((reg_t)0x1)<<bitnum))>>bitnum) 783 #define REG_FIELD_SET_TO(reg,msb,lsb,val) reg = (reg & (((~((reg_t)0x0))<<(31-msb)) | ((~((reg_t)0x0))>>lsb))) | ((reg_t)val<<lsb) 784 #define REG_FIELD_GET(reg,msb,lsb) ((reg<<(31-msb))>>(31-(msb-lsb))) 785 786 /* macros to reference subfields of large values (32-bit chunks of a 64-bit uint, etc) */ 787 /* *** NOTE THESE WILL PROBABLY BREAK ON LITTLE ENDIAN SYSTEMS (should work on fix for this) */ 788 #define UINT64_LOWER32_REFERENCE(val) (*(((uint32_t *)(&(val))) )) 789 #define UINT64_UPPER32_REFERENCE(val) (*(((uint32_t *)(&(val)))+1)) 790 791 792 /* structure definition for a cmc submodule of the cmicx */ 793 typedef struct cmicx_cmc_struct { 794 795 /* identification string for the cmc */ 796 char id_string[CMIC_CMC_ID_STRING_LENGTH]; 797 798 /* flags for config settings per-cmc */ 799 bool enable_early_bresp; 800 801 /* sbus dma and packet dma structures */ 802 cmicx_sbus_dma_data_t sbus_dma[CMICX_NUM_SBUS_DMA_PER_CMC]; 803 cmicx_packet_dma_data_t packet_dma[CMICX_NUM_PACKET_DMA_PER_CMC]; 804 805 } cmicx_cmc_t; 806 807 808 /* structure definition for the common block inside the cmicx */ 809 typedef struct cmicx_common_struct { 810 811 /* identification string for the common structure */ 812 char id_string[CMIC_CMC_ID_STRING_LENGTH]; 813 814 /* schan and schan fifo structures in the common struct */ 815 cmicx_schan_data_t schan[CMICX_NUM_SCHAN_IN_COMMON]; 816 /* cmicx_schan_fifo_data_t schan_fifo; */ 817 818 } cmicx_common_t; 819 820 821 /* structure definition for the cmicx module */ 822 typedef struct cmicx_struct { 823 824 /* pcid stuff, including function map table for pcid data access, and pcid memory space */ 825 int last_pcid_register; 826 addr_t pcid_addrs[ NUM_PCID_REGISTERS]; 827 pcid_read_func_t *pcid_read_funcs[ NUM_PCID_REGISTERS]; 828 pcid_write_func_t *pcid_write_funcs[NUM_PCID_REGISTERS]; 829 int last_pcid_memory_address_index; 830 addr_t pcid_memory_addresses[MAX_PCID_MEM_VALUES]; 831 unsigned char pcid_memory[ MAX_PCID_MEM_VALUES]; 832 833 /* switch register and memory data */ 834 int last_switch_register; 835 addr_t switch_register_addresses[CMICX_MAX_SWITCH_REGISTERS]; 836 reg_t switch_registers[ CMICX_MAX_SWITCH_REGISTERS]; 837 int last_switch_memory; 838 addr_t switch_memory_addresses[CMICX_MAX_SWITCH_MEMORIES]; 839 reg_t *switch_memories[ CMICX_MAX_SWITCH_MEMORIES]; 840 841 /* sub-structures that are duplicated in the cmicx (cmc, etc) */ 842 cmicx_cmc_t cmc0; 843 cmicx_cmc_t cmc1; 844 cmicx_common_t common; 845 846 /* schan functionality regs */ 847 bool enable_pio_write_non_posted; 848 char sbus_ring_arb_ctrl_schan_common_ch_weight[CMICX_NUM_SCHAN_IN_COMMON]; 849 char sbus_ring_arb_ctrl_schan_common_fifo_weight; 850 reg_t sbus_timeout_reg; 851 reg_t sbus_ring_map_0_7_reg; 852 reg_t sbus_ring_map_8_15_reg; 853 reg_t sbus_ring_map_16_23_reg; 854 reg_t sbus_ring_map_24_31_reg; 855 reg_t sbus_ring_map_32_39_reg; 856 reg_t sbus_ring_map_40_47_reg; 857 reg_t sbus_ring_map_48_55_reg; 858 reg_t sbus_ring_map_56_63_reg; 859 reg_t sbus_ring_map_64_71_reg; 860 reg_t sbus_ring_map_72_79_reg; 861 reg_t sbus_ring_map_80_87_reg; 862 reg_t sbus_ring_map_88_95_reg; 863 reg_t sbus_ring_map_96_103_reg; 864 reg_t sbus_ring_map_104_111_reg; 865 reg_t sbus_ring_map_112_119_reg; 866 reg_t sbus_ring_map_120_127_reg; 867 868 /* sbus dma functionality variables */ 869 char sbus_ring_arb_ctrl_sbusdma_cmc0_ch_weight[CMICX_NUM_SBUS_DMA_PER_CMC]; 870 char sbus_ring_arb_ctrl_sbusdma_cmc1_ch_weight[CMICX_NUM_SBUS_DMA_PER_CMC]; 871 872 /* packet dma functionality regs */ 873 bool ip_2_ep_loopback_enable; 874 875 } cmicx_t; 876 877 878 /* cmicx top-level functions */ 879 bool cmicx_init(void); 880 881 /* switch register/memory read/write functions */ 882 bool cmicx_switch_reg_read(addr_t addr,reg_t *val); 883 bool cmicx_switch_reg_write(addr_t addr,reg_t val); 884 void cmicx_switch_registers_dump(void); 885 bool cmicx_switch_mem_read(addr_t addr,reg_t *mem,int req,int *resp); 886 bool cmicx_switch_mem_write(addr_t addr,reg_t *mem,int amount); 887 void cmicx_switch_memories_dump(void); 888 889 /* control register read/write functions */ 890 pcid_read_func_t cmicx_sim_control_reg_read; 891 pcid_write_func_t cmicx_sim_control_reg_write; 892 893 894 #endif /* CMICX_H */ 895