cmicx_sim.c (161965B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 8 /* 9 * cmicx_sim.c 10 * 11 * cmicx module main implementation 12 */ 13 14 #ifndef CMICX_STANDALONE_SIM 15 #include <unistd.h> 16 #include <../systems/bde/pli/verinet.h> 17 #include <../systems/sim/pcid/pcid.h> 18 #include <../systems/sim/pcid/cmicx_sim.h> 19 #include <../systems/sim/pcid/cmicx_sim_pcid.h> 20 #include <../systems/sim/pcid/cmicx_sim_schan.h> 21 #include <../systems/sim/pcid/cmicx_sim_sbus_dma.h> 22 #include <../systems/sim/pcid/cmicx_sim_packet_dma.h> 23 #else 24 #include <stdio.h> 25 #include <stdlib.h> 26 #include "cmicx_sim.h" 27 #include "cmicx_sim_pcid.h" 28 #include "cmicx_sim_schan.h" 29 #include "cmicx_sim_sbus_dma.h" 30 #include "cmicx_sim_packet_dma.h" 31 #endif 32 #include <string.h> 33 #include <time.h> 34 35 36 cmicx_t cmicx_data; 37 /* global pointer for cmicx structure */ 38 cmicx_t *cmicx = &cmicx_data; 39 40 /* initialize the cmicx module */ 41 bool cmicx_init(void) { 42 43 /* variables */ 44 int i; 45 char id_string[CMIC_SBUS_DMA_ID_STRING_LENGTH]; 46 47 /* initialize logging system */ 48 if (cmicx_logging_init("CMICX_SIM_LOG.log")==false) { 49 cmicx_log("ERROR: Could not open log file for logging CMICx sim output."); 50 } 51 cmicx_log_newline(); 52 cmicx_log("Initializing CMICx simulation..."); 53 cmicx_log_newline(); 54 55 56 /* initialize schan data */ 57 strcpy(id_string,"common schan 0 "); 58 for (i=0; i<CMICX_NUM_SCHAN_IN_COMMON; i++) { 59 id_string[13] = ((char)(i+48)); /* add 48 to get the ascii code for the schan number */ 60 cmicx_schan_init(&cmicx->common.schan[i], id_string); 61 } 62 63 64 /* initialize schan fifo data */ 65 /* TBD */ 66 67 68 /* intialize cmcs, in preparation for sbus dma init */ 69 strcpy(cmicx->cmc0.id_string,"cmc0"); 70 cmicx->cmc0.enable_early_bresp = false; 71 strcpy(cmicx->cmc1.id_string,"cmc1"); 72 cmicx->cmc1.enable_early_bresp = false; 73 74 /* intialize sbus dma data */ 75 strcpy(id_string,"cmc0 sbus dma ch0 "); 76 for (i=0; i<CMICX_NUM_SBUS_DMA_PER_CMC; i++) { 77 id_string[16] = ((char)(i+48)); /* add 48 to get the ascii code for the sbus dma channel number */ 78 cmicx_sbus_dma_init(&cmicx->cmc0.sbus_dma[i], id_string); 79 } 80 strcpy(id_string,"cmc1 sbus dma ch0 "); 81 for (i=0; i<CMICX_NUM_SBUS_DMA_PER_CMC; i++) { 82 id_string[16] = ((char)(i+48)); /* add 48 to get the ascii code for the sbus dma channel number */ 83 cmicx_sbus_dma_init(&cmicx->cmc1.sbus_dma[i], id_string); 84 } 85 86 87 /* initialize packet dma. the global init takes care of opening input/output files for packet data */ 88 cmicx_packet_dma_global_init("CMICX_SIM_IP_PACKETS.out","CMICX_SIM_EP_PACKETS.in","CMICX_SIM_LOOPBACK_PACKETS.inout"); 89 strcpy(id_string,"cmc0 packet dma ch0 "); 90 for (i=0; i<CMICX_NUM_PACKET_DMA_PER_CMC; i++) { 91 id_string[18] = ((char)(i+48)); /* add 48 to get the ascii code for the [packet dma] number */ 92 cmicx_packet_dma_init(&cmicx->cmc0.packet_dma[i], id_string, i); 93 } 94 strcpy(id_string,"cmc1 packet dma ch0 "); 95 for (i=0; i<CMICX_NUM_PACKET_DMA_PER_CMC; i++) { 96 id_string[18] = ((char)(i+48)); /* add 48 to get the ascii code for the [packet dma] number */ 97 cmicx_packet_dma_init(&cmicx->cmc1.packet_dma[i], id_string, i); 98 } 99 100 101 /* initialize the PCID register counter and memory, and the switch register count and memory count */ 102 cmicx->last_pcid_register = -1; 103 cmicx->last_pcid_memory_address_index = -1; 104 cmicx->last_switch_register = -1; 105 cmicx->last_switch_memory = -1; 106 107 /* initialize schan functionality regs. weights are 0xE by default, per the spec. */ 108 cmicx->enable_pio_write_non_posted = false; 109 for (i=0; i<CMICX_NUM_SCHAN_IN_COMMON; i++) { 110 cmicx->sbus_ring_arb_ctrl_schan_common_ch_weight[i] = 0xE; 111 } 112 cmicx->sbus_ring_arb_ctrl_schan_common_fifo_weight = 0xE; 113 cmicx->sbus_ring_map_0_7_reg = 0x0; 114 cmicx->sbus_ring_map_8_15_reg = 0x0; 115 cmicx->sbus_ring_map_16_23_reg = 0x0; 116 cmicx->sbus_ring_map_24_31_reg = 0x0; 117 cmicx->sbus_ring_map_32_39_reg = 0x0; 118 cmicx->sbus_ring_map_40_47_reg = 0x0; 119 cmicx->sbus_ring_map_48_55_reg = 0x0; 120 cmicx->sbus_ring_map_56_63_reg = 0x0; 121 cmicx->sbus_timeout_reg = 0x00002700; 122 123 /* initialize sbus dma functionality variables. weights are 0xE by default, per the spec. */ 124 for (i=0; i<CMICX_NUM_SBUS_DMA_PER_CMC; i++) { 125 cmicx->sbus_ring_arb_ctrl_sbusdma_cmc0_ch_weight[i] = 0xE; 126 } 127 for (i=0; i<CMICX_NUM_SBUS_DMA_PER_CMC; i++) { 128 cmicx->sbus_ring_arb_ctrl_sbusdma_cmc1_ch_weight[i] = 0xE; 129 } 130 131 /* initialize packet dma functionality registers. */ 132 cmicx->ip_2_ep_loopback_enable = false; 133 134 135 /* add cmicx sim control register */ 136 if (! cmicx_pcid_register_add(CMICX_SIM_CONTROL_REG_ADDR, cmicx_sim_control_reg_read, cmicx_sim_control_reg_write) ) { 137 cmicx_error("could not initialize cmicx sim control register\n"); 138 } 139 /* add pcid schan registers */ 140 if (! ( cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_ARB_CTRL_SCHAN_REG_ADDR, cmic_top_sbus_ring_arb_ctrl_schan_read, cmic_top_sbus_ring_arb_ctrl_schan_write ) && 141 cmicx_pcid_register_add(CMIC_TOP_SBUS_TIMEOUT_REG_ADDR, cmic_top_sbus_timeout_read, cmic_top_sbus_timeout_write ) && 142 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_0_7_REG_ADDR, cmic_top_sbus_ring_map_0_7_read, cmic_top_sbus_ring_map_0_7_write ) && 143 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_8_15_REG_ADDR, cmic_top_sbus_ring_map_8_15_read, cmic_top_sbus_ring_map_8_15_write ) && 144 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_16_23_REG_ADDR, cmic_top_sbus_ring_map_16_23_read, cmic_top_sbus_ring_map_16_23_write ) && 145 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_24_31_REG_ADDR, cmic_top_sbus_ring_map_24_31_read, cmic_top_sbus_ring_map_24_31_write ) && 146 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_32_39_REG_ADDR, cmic_top_sbus_ring_map_32_39_read, cmic_top_sbus_ring_map_32_39_write ) && 147 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_40_47_REG_ADDR, cmic_top_sbus_ring_map_40_47_read, cmic_top_sbus_ring_map_40_47_write ) && 148 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_48_55_REG_ADDR, cmic_top_sbus_ring_map_48_55_read, cmic_top_sbus_ring_map_48_55_write ) && 149 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_56_63_REG_ADDR, cmic_top_sbus_ring_map_56_63_read, cmic_top_sbus_ring_map_56_63_write ) && 150 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_64_71_REG_ADDR, cmic_top_sbus_ring_map_64_71_read, cmic_top_sbus_ring_map_64_71_write ) && 151 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_72_79_REG_ADDR, cmic_top_sbus_ring_map_72_79_read, cmic_top_sbus_ring_map_72_79_write ) && 152 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_80_87_REG_ADDR, cmic_top_sbus_ring_map_80_87_read, cmic_top_sbus_ring_map_80_87_write ) && 153 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_88_95_REG_ADDR, cmic_top_sbus_ring_map_88_95_read, cmic_top_sbus_ring_map_88_95_write ) && 154 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_96_103_REG_ADDR, cmic_top_sbus_ring_map_96_103_read, cmic_top_sbus_ring_map_96_103_write ) && 155 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_104_111_REG_ADDR, cmic_top_sbus_ring_map_104_111_read, cmic_top_sbus_ring_map_104_111_write ) && 156 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_112_119_REG_ADDR, cmic_top_sbus_ring_map_112_119_read, cmic_top_sbus_ring_map_112_119_write ) && 157 cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_MAP_120_127_REG_ADDR, cmic_top_sbus_ring_map_120_127_read, cmic_top_sbus_ring_map_120_127_write ) && 158 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE0_REG_ADDR, cmic_common_pool_schan_ch0_message0_read, cmic_common_pool_schan_ch0_message0_write ) && 159 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE1_REG_ADDR, cmic_common_pool_schan_ch0_message1_read, cmic_common_pool_schan_ch0_message1_write ) && 160 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE2_REG_ADDR, cmic_common_pool_schan_ch0_message2_read, cmic_common_pool_schan_ch0_message2_write ) && 161 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE3_REG_ADDR, cmic_common_pool_schan_ch0_message3_read, cmic_common_pool_schan_ch0_message3_write ) && 162 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE4_REG_ADDR, cmic_common_pool_schan_ch0_message4_read, cmic_common_pool_schan_ch0_message4_write ) && 163 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE5_REG_ADDR, cmic_common_pool_schan_ch0_message5_read, cmic_common_pool_schan_ch0_message5_write ) && 164 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE6_REG_ADDR, cmic_common_pool_schan_ch0_message6_read, cmic_common_pool_schan_ch0_message6_write ) && 165 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE7_REG_ADDR, cmic_common_pool_schan_ch0_message7_read, cmic_common_pool_schan_ch0_message7_write ) && 166 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE8_REG_ADDR, cmic_common_pool_schan_ch0_message8_read, cmic_common_pool_schan_ch0_message8_write ) && 167 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE9_REG_ADDR, cmic_common_pool_schan_ch0_message9_read, cmic_common_pool_schan_ch0_message9_write ) && 168 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE10_REG_ADDR, cmic_common_pool_schan_ch0_message10_read, cmic_common_pool_schan_ch0_message10_write ) && 169 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE11_REG_ADDR, cmic_common_pool_schan_ch0_message11_read, cmic_common_pool_schan_ch0_message11_write ) && 170 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE12_REG_ADDR, cmic_common_pool_schan_ch0_message12_read, cmic_common_pool_schan_ch0_message12_write ) && 171 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE13_REG_ADDR, cmic_common_pool_schan_ch0_message13_read, cmic_common_pool_schan_ch0_message13_write ) && 172 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE14_REG_ADDR, cmic_common_pool_schan_ch0_message14_read, cmic_common_pool_schan_ch0_message14_write ) && 173 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE15_REG_ADDR, cmic_common_pool_schan_ch0_message15_read, cmic_common_pool_schan_ch0_message15_write ) && 174 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE16_REG_ADDR, cmic_common_pool_schan_ch0_message16_read, cmic_common_pool_schan_ch0_message16_write ) && 175 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE17_REG_ADDR, cmic_common_pool_schan_ch0_message17_read, cmic_common_pool_schan_ch0_message17_write ) && 176 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE18_REG_ADDR, cmic_common_pool_schan_ch0_message18_read, cmic_common_pool_schan_ch0_message18_write ) && 177 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE19_REG_ADDR, cmic_common_pool_schan_ch0_message19_read, cmic_common_pool_schan_ch0_message19_write ) && 178 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE20_REG_ADDR, cmic_common_pool_schan_ch0_message20_read, cmic_common_pool_schan_ch0_message20_write ) && 179 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE21_REG_ADDR, cmic_common_pool_schan_ch0_message21_read, cmic_common_pool_schan_ch0_message21_write ) && 180 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE0_REG_ADDR, cmic_common_pool_schan_ch1_message0_read, cmic_common_pool_schan_ch1_message0_write ) && 181 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE1_REG_ADDR, cmic_common_pool_schan_ch1_message1_read, cmic_common_pool_schan_ch1_message1_write ) && 182 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE2_REG_ADDR, cmic_common_pool_schan_ch1_message2_read, cmic_common_pool_schan_ch1_message2_write ) && 183 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE3_REG_ADDR, cmic_common_pool_schan_ch1_message3_read, cmic_common_pool_schan_ch1_message3_write ) && 184 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE4_REG_ADDR, cmic_common_pool_schan_ch1_message4_read, cmic_common_pool_schan_ch1_message4_write ) && 185 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE5_REG_ADDR, cmic_common_pool_schan_ch1_message5_read, cmic_common_pool_schan_ch1_message5_write ) && 186 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE6_REG_ADDR, cmic_common_pool_schan_ch1_message6_read, cmic_common_pool_schan_ch1_message6_write ) && 187 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE7_REG_ADDR, cmic_common_pool_schan_ch1_message7_read, cmic_common_pool_schan_ch1_message7_write ) && 188 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE8_REG_ADDR, cmic_common_pool_schan_ch1_message8_read, cmic_common_pool_schan_ch1_message8_write ) && 189 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE9_REG_ADDR, cmic_common_pool_schan_ch1_message9_read, cmic_common_pool_schan_ch1_message9_write ) && 190 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE10_REG_ADDR, cmic_common_pool_schan_ch1_message10_read, cmic_common_pool_schan_ch1_message10_write ) && 191 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE11_REG_ADDR, cmic_common_pool_schan_ch1_message11_read, cmic_common_pool_schan_ch1_message11_write ) && 192 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE12_REG_ADDR, cmic_common_pool_schan_ch1_message12_read, cmic_common_pool_schan_ch1_message12_write ) && 193 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE13_REG_ADDR, cmic_common_pool_schan_ch1_message13_read, cmic_common_pool_schan_ch1_message13_write ) && 194 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE14_REG_ADDR, cmic_common_pool_schan_ch1_message14_read, cmic_common_pool_schan_ch1_message14_write ) && 195 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE15_REG_ADDR, cmic_common_pool_schan_ch1_message15_read, cmic_common_pool_schan_ch1_message15_write ) && 196 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE16_REG_ADDR, cmic_common_pool_schan_ch1_message16_read, cmic_common_pool_schan_ch1_message16_write ) && 197 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE17_REG_ADDR, cmic_common_pool_schan_ch1_message17_read, cmic_common_pool_schan_ch1_message17_write ) && 198 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE18_REG_ADDR, cmic_common_pool_schan_ch1_message18_read, cmic_common_pool_schan_ch1_message18_write ) && 199 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE19_REG_ADDR, cmic_common_pool_schan_ch1_message19_read, cmic_common_pool_schan_ch1_message19_write ) && 200 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE20_REG_ADDR, cmic_common_pool_schan_ch1_message20_read, cmic_common_pool_schan_ch1_message20_write ) && 201 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE21_REG_ADDR, cmic_common_pool_schan_ch1_message21_read, cmic_common_pool_schan_ch1_message21_write ) && 202 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE0_REG_ADDR, cmic_common_pool_schan_ch2_message0_read, cmic_common_pool_schan_ch2_message0_write ) && 203 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE1_REG_ADDR, cmic_common_pool_schan_ch2_message1_read, cmic_common_pool_schan_ch2_message1_write ) && 204 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE2_REG_ADDR, cmic_common_pool_schan_ch2_message2_read, cmic_common_pool_schan_ch2_message2_write ) && 205 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE3_REG_ADDR, cmic_common_pool_schan_ch2_message3_read, cmic_common_pool_schan_ch2_message3_write ) && 206 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE4_REG_ADDR, cmic_common_pool_schan_ch2_message4_read, cmic_common_pool_schan_ch2_message4_write ) && 207 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE5_REG_ADDR, cmic_common_pool_schan_ch2_message5_read, cmic_common_pool_schan_ch2_message5_write ) && 208 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE6_REG_ADDR, cmic_common_pool_schan_ch2_message6_read, cmic_common_pool_schan_ch2_message6_write ) && 209 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE7_REG_ADDR, cmic_common_pool_schan_ch2_message7_read, cmic_common_pool_schan_ch2_message7_write ) && 210 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE8_REG_ADDR, cmic_common_pool_schan_ch2_message8_read, cmic_common_pool_schan_ch2_message8_write ) && 211 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE9_REG_ADDR, cmic_common_pool_schan_ch2_message9_read, cmic_common_pool_schan_ch2_message9_write ) && 212 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE10_REG_ADDR, cmic_common_pool_schan_ch2_message10_read, cmic_common_pool_schan_ch2_message10_write ) && 213 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE11_REG_ADDR, cmic_common_pool_schan_ch2_message11_read, cmic_common_pool_schan_ch2_message11_write ) && 214 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE12_REG_ADDR, cmic_common_pool_schan_ch2_message12_read, cmic_common_pool_schan_ch2_message12_write ) && 215 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE13_REG_ADDR, cmic_common_pool_schan_ch2_message13_read, cmic_common_pool_schan_ch2_message13_write ) && 216 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE14_REG_ADDR, cmic_common_pool_schan_ch2_message14_read, cmic_common_pool_schan_ch2_message14_write ) && 217 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE15_REG_ADDR, cmic_common_pool_schan_ch2_message15_read, cmic_common_pool_schan_ch2_message15_write ) && 218 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE16_REG_ADDR, cmic_common_pool_schan_ch2_message16_read, cmic_common_pool_schan_ch2_message16_write ) && 219 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE17_REG_ADDR, cmic_common_pool_schan_ch2_message17_read, cmic_common_pool_schan_ch2_message17_write ) && 220 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE18_REG_ADDR, cmic_common_pool_schan_ch2_message18_read, cmic_common_pool_schan_ch2_message18_write ) && 221 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE19_REG_ADDR, cmic_common_pool_schan_ch2_message19_read, cmic_common_pool_schan_ch2_message19_write ) && 222 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE20_REG_ADDR, cmic_common_pool_schan_ch2_message20_read, cmic_common_pool_schan_ch2_message20_write ) && 223 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE21_REG_ADDR, cmic_common_pool_schan_ch2_message21_read, cmic_common_pool_schan_ch2_message21_write ) && 224 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE0_REG_ADDR, cmic_common_pool_schan_ch3_message0_read, cmic_common_pool_schan_ch3_message0_write ) && 225 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE1_REG_ADDR, cmic_common_pool_schan_ch3_message1_read, cmic_common_pool_schan_ch3_message1_write ) && 226 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE2_REG_ADDR, cmic_common_pool_schan_ch3_message2_read, cmic_common_pool_schan_ch3_message2_write ) && 227 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE3_REG_ADDR, cmic_common_pool_schan_ch3_message3_read, cmic_common_pool_schan_ch3_message3_write ) && 228 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE4_REG_ADDR, cmic_common_pool_schan_ch3_message4_read, cmic_common_pool_schan_ch3_message4_write ) && 229 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE5_REG_ADDR, cmic_common_pool_schan_ch3_message5_read, cmic_common_pool_schan_ch3_message5_write ) && 230 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE6_REG_ADDR, cmic_common_pool_schan_ch3_message6_read, cmic_common_pool_schan_ch3_message6_write ) && 231 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE7_REG_ADDR, cmic_common_pool_schan_ch3_message7_read, cmic_common_pool_schan_ch3_message7_write ) && 232 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE8_REG_ADDR, cmic_common_pool_schan_ch3_message8_read, cmic_common_pool_schan_ch3_message8_write ) && 233 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE9_REG_ADDR, cmic_common_pool_schan_ch3_message9_read, cmic_common_pool_schan_ch3_message9_write ) && 234 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE10_REG_ADDR, cmic_common_pool_schan_ch3_message10_read, cmic_common_pool_schan_ch3_message10_write ) && 235 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE11_REG_ADDR, cmic_common_pool_schan_ch3_message11_read, cmic_common_pool_schan_ch3_message11_write ) && 236 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE12_REG_ADDR, cmic_common_pool_schan_ch3_message12_read, cmic_common_pool_schan_ch3_message12_write ) && 237 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE13_REG_ADDR, cmic_common_pool_schan_ch3_message13_read, cmic_common_pool_schan_ch3_message13_write ) && 238 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE14_REG_ADDR, cmic_common_pool_schan_ch3_message14_read, cmic_common_pool_schan_ch3_message14_write ) && 239 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE15_REG_ADDR, cmic_common_pool_schan_ch3_message15_read, cmic_common_pool_schan_ch3_message15_write ) && 240 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE16_REG_ADDR, cmic_common_pool_schan_ch3_message16_read, cmic_common_pool_schan_ch3_message16_write ) && 241 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE17_REG_ADDR, cmic_common_pool_schan_ch3_message17_read, cmic_common_pool_schan_ch3_message17_write ) && 242 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE18_REG_ADDR, cmic_common_pool_schan_ch3_message18_read, cmic_common_pool_schan_ch3_message18_write ) && 243 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE19_REG_ADDR, cmic_common_pool_schan_ch3_message19_read, cmic_common_pool_schan_ch3_message19_write ) && 244 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE20_REG_ADDR, cmic_common_pool_schan_ch3_message20_read, cmic_common_pool_schan_ch3_message20_write ) && 245 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE21_REG_ADDR, cmic_common_pool_schan_ch3_message21_read, cmic_common_pool_schan_ch3_message21_write ) && 246 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE0_REG_ADDR, cmic_common_pool_schan_ch4_message0_read, cmic_common_pool_schan_ch4_message0_write ) && 247 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE1_REG_ADDR, cmic_common_pool_schan_ch4_message1_read, cmic_common_pool_schan_ch4_message1_write ) && 248 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE2_REG_ADDR, cmic_common_pool_schan_ch4_message2_read, cmic_common_pool_schan_ch4_message2_write ) && 249 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE3_REG_ADDR, cmic_common_pool_schan_ch4_message3_read, cmic_common_pool_schan_ch4_message3_write ) && 250 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE4_REG_ADDR, cmic_common_pool_schan_ch4_message4_read, cmic_common_pool_schan_ch4_message4_write ) && 251 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE5_REG_ADDR, cmic_common_pool_schan_ch4_message5_read, cmic_common_pool_schan_ch4_message5_write ) && 252 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE6_REG_ADDR, cmic_common_pool_schan_ch4_message6_read, cmic_common_pool_schan_ch4_message6_write ) && 253 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE7_REG_ADDR, cmic_common_pool_schan_ch4_message7_read, cmic_common_pool_schan_ch4_message7_write ) && 254 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE8_REG_ADDR, cmic_common_pool_schan_ch4_message8_read, cmic_common_pool_schan_ch4_message8_write ) && 255 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE9_REG_ADDR, cmic_common_pool_schan_ch4_message9_read, cmic_common_pool_schan_ch4_message9_write ) && 256 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE10_REG_ADDR, cmic_common_pool_schan_ch4_message10_read, cmic_common_pool_schan_ch4_message10_write ) && 257 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE11_REG_ADDR, cmic_common_pool_schan_ch4_message11_read, cmic_common_pool_schan_ch4_message11_write ) && 258 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE12_REG_ADDR, cmic_common_pool_schan_ch4_message12_read, cmic_common_pool_schan_ch4_message12_write ) && 259 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE13_REG_ADDR, cmic_common_pool_schan_ch4_message13_read, cmic_common_pool_schan_ch4_message13_write ) && 260 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE14_REG_ADDR, cmic_common_pool_schan_ch4_message14_read, cmic_common_pool_schan_ch4_message14_write ) && 261 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE15_REG_ADDR, cmic_common_pool_schan_ch4_message15_read, cmic_common_pool_schan_ch4_message15_write ) && 262 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE16_REG_ADDR, cmic_common_pool_schan_ch4_message16_read, cmic_common_pool_schan_ch4_message16_write ) && 263 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE17_REG_ADDR, cmic_common_pool_schan_ch4_message17_read, cmic_common_pool_schan_ch4_message17_write ) && 264 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE18_REG_ADDR, cmic_common_pool_schan_ch4_message18_read, cmic_common_pool_schan_ch4_message18_write ) && 265 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE19_REG_ADDR, cmic_common_pool_schan_ch4_message19_read, cmic_common_pool_schan_ch4_message19_write ) && 266 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE20_REG_ADDR, cmic_common_pool_schan_ch4_message20_read, cmic_common_pool_schan_ch4_message20_write ) && 267 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE21_REG_ADDR, cmic_common_pool_schan_ch4_message21_read, cmic_common_pool_schan_ch4_message21_write ) && 268 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_CTRL_REG_ADDR, cmic_common_pool_schan_ch0_ctrl_read, cmic_common_pool_schan_ch0_ctrl_write ) && 269 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_ACK_DATA_BEAT_COUNT_REG_ADDR, cmic_common_pool_schan_ch0_ack_data_beat_count_read, cmic_common_pool_schan_ch0_ack_data_beat_count_write ) && 270 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH0_ERR_REG_ADDR, cmic_common_pool_schan_ch0_err_read, cmic_common_pool_schan_ch0_err_write ) && 271 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_CTRL_REG_ADDR, cmic_common_pool_schan_ch1_ctrl_read, cmic_common_pool_schan_ch1_ctrl_write ) && 272 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_ACK_DATA_BEAT_COUNT_REG_ADDR, cmic_common_pool_schan_ch1_ack_data_beat_count_read, cmic_common_pool_schan_ch1_ack_data_beat_count_write ) && 273 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH1_ERR_REG_ADDR, cmic_common_pool_schan_ch1_err_read, cmic_common_pool_schan_ch1_err_write ) && 274 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_CTRL_REG_ADDR, cmic_common_pool_schan_ch2_ctrl_read, cmic_common_pool_schan_ch2_ctrl_write ) && 275 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_ACK_DATA_BEAT_COUNT_REG_ADDR, cmic_common_pool_schan_ch2_ack_data_beat_count_read, cmic_common_pool_schan_ch2_ack_data_beat_count_write ) && 276 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH2_ERR_REG_ADDR, cmic_common_pool_schan_ch2_err_read, cmic_common_pool_schan_ch2_err_write ) && 277 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_CTRL_REG_ADDR, cmic_common_pool_schan_ch3_ctrl_read, cmic_common_pool_schan_ch3_ctrl_write ) && 278 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_ACK_DATA_BEAT_COUNT_REG_ADDR, cmic_common_pool_schan_ch3_ack_data_beat_count_read, cmic_common_pool_schan_ch3_ack_data_beat_count_write ) && 279 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH3_ERR_REG_ADDR, cmic_common_pool_schan_ch3_err_read, cmic_common_pool_schan_ch3_err_write ) && 280 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_CTRL_REG_ADDR, cmic_common_pool_schan_ch4_ctrl_read, cmic_common_pool_schan_ch4_ctrl_write ) && 281 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_ACK_DATA_BEAT_COUNT_REG_ADDR, cmic_common_pool_schan_ch4_ack_data_beat_count_read, cmic_common_pool_schan_ch4_ack_data_beat_count_write ) && 282 cmicx_pcid_register_add(CMIC_COMMON_POOL_SCHAN_CH4_ERR_REG_ADDR, cmic_common_pool_schan_ch4_err_read, cmic_common_pool_schan_ch4_err_write ) ) ) { 283 cmicx_error("could not initialize schan PCID registers\n"); 284 } 285 286 /* add PCID sbus dma registers */ 287 if (! ( cmicx_pcid_register_add(CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_REG_ADDR, cmic_top_sbus_ring_arb_ctrl_sbusdma_read, cmic_top_sbus_ring_arb_ctrl_sbusdma_write ) && 288 cmicx_pcid_register_add(CMIC_CMC0_SHARED_CONFIG_REG_ADDR, cmic_cmc0_shared_config_read, cmic_cmc0_shared_config_write) && 289 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CONTROL_REG_ADDR, cmic_cmc0_sbusdma_ch0_control_read, cmic_cmc0_sbusdma_ch0_control_write) && 290 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_REQUEST_REG_ADDR, cmic_cmc0_sbusdma_ch0_request_read, cmic_cmc0_sbusdma_ch0_request_write) && 291 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch0_count_read, cmic_cmc0_sbusdma_ch0_count_write) && 292 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_OPCODE_REG_ADDR, cmic_cmc0_sbusdma_ch0_opcode_read, cmic_cmc0_sbusdma_ch0_opcode_write) && 293 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch0_sbus_start_address_read, cmic_cmc0_sbusdma_ch0_sbus_start_address_write) && 294 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch0_hostmem_start_address_lo_read, cmic_cmc0_sbusdma_ch0_hostmem_start_address_lo_write) && 295 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch0_hostmem_start_address_hi_read, cmic_cmc0_sbusdma_ch0_hostmem_start_address_hi_write) && 296 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch0_desc_start_address_lo_read, cmic_cmc0_sbusdma_ch0_desc_start_address_lo_write) && 297 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch0_desc_start_address_hi_read, cmic_cmc0_sbusdma_ch0_desc_start_address_hi_write) && 298 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_STATUS_REG_ADDR, cmic_cmc0_sbusdma_ch0_status_read, cmic_cmc0_sbusdma_ch0_status_write) && 299 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_hostmem_address_lo_read, cmic_cmc0_sbusdma_ch0_cur_hostmem_address_lo_write) && 300 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_hostmem_address_hi_read, cmic_cmc0_sbusdma_ch0_cur_hostmem_address_hi_write) && 301 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_sbus_address_read, cmic_cmc0_sbusdma_ch0_cur_sbus_address_write) && 302 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_desc_address_lo_read, cmic_cmc0_sbusdma_ch0_cur_desc_address_lo_write) && 303 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_desc_address_hi_read, cmic_cmc0_sbusdma_ch0_cur_desc_address_hi_write) && 304 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_request_read, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_request_write) && 305 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_count_read, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_count_write) && 306 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_read, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_write) && 307 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_read, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_write) && 308 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_read, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_write) && 309 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_opcode_read, cmic_cmc0_sbusdma_ch0_cur_sbusdma_config_opcode_write) && 310 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_REG_ADDR, cmic_cmc0_sbusdma_ch0_sbusdma_debug_read, cmic_cmc0_sbusdma_ch0_sbusdma_debug_write) && 311 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_REG_ADDR, cmic_cmc0_sbusdma_ch0_sbusdma_debug_clr_read, cmic_cmc0_sbusdma_ch0_sbusdma_debug_clr_write) && 312 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_TIMER_REG_ADDR, cmic_cmc0_sbusdma_ch0_timer_read, cmic_cmc0_sbusdma_ch0_timer_write) && 313 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH0_ITER_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch0_iter_count_read, cmic_cmc0_sbusdma_ch0_iter_count_write) && 314 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CONTROL_REG_ADDR, cmic_cmc0_sbusdma_ch1_control_read, cmic_cmc0_sbusdma_ch1_control_write) && 315 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_REQUEST_REG_ADDR, cmic_cmc0_sbusdma_ch1_request_read, cmic_cmc0_sbusdma_ch1_request_write) && 316 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch1_count_read, cmic_cmc0_sbusdma_ch1_count_write) && 317 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_OPCODE_REG_ADDR, cmic_cmc0_sbusdma_ch1_opcode_read, cmic_cmc0_sbusdma_ch1_opcode_write) && 318 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch1_sbus_start_address_read, cmic_cmc0_sbusdma_ch1_sbus_start_address_write) && 319 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch1_hostmem_start_address_lo_read, cmic_cmc0_sbusdma_ch1_hostmem_start_address_lo_write) && 320 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch1_hostmem_start_address_hi_read, cmic_cmc0_sbusdma_ch1_hostmem_start_address_hi_write) && 321 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch1_desc_start_address_lo_read, cmic_cmc0_sbusdma_ch1_desc_start_address_lo_write) && 322 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch1_desc_start_address_hi_read, cmic_cmc0_sbusdma_ch1_desc_start_address_hi_write) && 323 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_STATUS_REG_ADDR, cmic_cmc0_sbusdma_ch1_status_read, cmic_cmc0_sbusdma_ch1_status_write) && 324 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_hostmem_address_lo_read, cmic_cmc0_sbusdma_ch1_cur_hostmem_address_lo_write) && 325 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_hostmem_address_hi_read, cmic_cmc0_sbusdma_ch1_cur_hostmem_address_hi_write) && 326 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_sbus_address_read, cmic_cmc0_sbusdma_ch1_cur_sbus_address_write) && 327 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_desc_address_lo_read, cmic_cmc0_sbusdma_ch1_cur_desc_address_lo_write) && 328 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_desc_address_hi_read, cmic_cmc0_sbusdma_ch1_cur_desc_address_hi_write) && 329 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_request_read, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_request_write) && 330 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_count_read, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_count_write) && 331 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_read, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_write) && 332 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_read, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_write) && 333 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_read, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_write) && 334 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_opcode_read, cmic_cmc0_sbusdma_ch1_cur_sbusdma_config_opcode_write) && 335 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_REG_ADDR, cmic_cmc0_sbusdma_ch1_sbusdma_debug_read, cmic_cmc0_sbusdma_ch1_sbusdma_debug_write) && 336 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_REG_ADDR, cmic_cmc0_sbusdma_ch1_sbusdma_debug_clr_read, cmic_cmc0_sbusdma_ch1_sbusdma_debug_clr_write) && 337 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_TIMER_REG_ADDR, cmic_cmc0_sbusdma_ch1_timer_read, cmic_cmc0_sbusdma_ch1_timer_write) && 338 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH1_ITER_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch1_iter_count_read, cmic_cmc0_sbusdma_ch1_iter_count_write) && 339 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CONTROL_REG_ADDR, cmic_cmc0_sbusdma_ch2_control_read, cmic_cmc0_sbusdma_ch2_control_write) && 340 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_REQUEST_REG_ADDR, cmic_cmc0_sbusdma_ch2_request_read, cmic_cmc0_sbusdma_ch2_request_write) && 341 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch2_count_read, cmic_cmc0_sbusdma_ch2_count_write) && 342 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_OPCODE_REG_ADDR, cmic_cmc0_sbusdma_ch2_opcode_read, cmic_cmc0_sbusdma_ch2_opcode_write) && 343 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch2_sbus_start_address_read, cmic_cmc0_sbusdma_ch2_sbus_start_address_write) && 344 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch2_hostmem_start_address_lo_read, cmic_cmc0_sbusdma_ch2_hostmem_start_address_lo_write) && 345 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch2_hostmem_start_address_hi_read, cmic_cmc0_sbusdma_ch2_hostmem_start_address_hi_write) && 346 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch2_desc_start_address_lo_read, cmic_cmc0_sbusdma_ch2_desc_start_address_lo_write) && 347 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch2_desc_start_address_hi_read, cmic_cmc0_sbusdma_ch2_desc_start_address_hi_write) && 348 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_STATUS_REG_ADDR, cmic_cmc0_sbusdma_ch2_status_read, cmic_cmc0_sbusdma_ch2_status_write) && 349 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_hostmem_address_lo_read, cmic_cmc0_sbusdma_ch2_cur_hostmem_address_lo_write) && 350 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_hostmem_address_hi_read, cmic_cmc0_sbusdma_ch2_cur_hostmem_address_hi_write) && 351 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_sbus_address_read, cmic_cmc0_sbusdma_ch2_cur_sbus_address_write) && 352 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_desc_address_lo_read, cmic_cmc0_sbusdma_ch2_cur_desc_address_lo_write) && 353 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_desc_address_hi_read, cmic_cmc0_sbusdma_ch2_cur_desc_address_hi_write) && 354 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_request_read, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_request_write) && 355 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_count_read, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_count_write) && 356 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_read, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_write) && 357 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_read, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_write) && 358 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_read, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_write) && 359 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_opcode_read, cmic_cmc0_sbusdma_ch2_cur_sbusdma_config_opcode_write) && 360 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_REG_ADDR, cmic_cmc0_sbusdma_ch2_sbusdma_debug_read, cmic_cmc0_sbusdma_ch2_sbusdma_debug_write) && 361 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_REG_ADDR, cmic_cmc0_sbusdma_ch2_sbusdma_debug_clr_read, cmic_cmc0_sbusdma_ch2_sbusdma_debug_clr_write) && 362 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_TIMER_REG_ADDR, cmic_cmc0_sbusdma_ch2_timer_read, cmic_cmc0_sbusdma_ch2_timer_write) && 363 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH2_ITER_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch2_iter_count_read, cmic_cmc0_sbusdma_ch2_iter_count_write) && 364 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CONTROL_REG_ADDR, cmic_cmc0_sbusdma_ch3_control_read, cmic_cmc0_sbusdma_ch3_control_write) && 365 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_REQUEST_REG_ADDR, cmic_cmc0_sbusdma_ch3_request_read, cmic_cmc0_sbusdma_ch3_request_write) && 366 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch3_count_read, cmic_cmc0_sbusdma_ch3_count_write) && 367 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_OPCODE_REG_ADDR, cmic_cmc0_sbusdma_ch3_opcode_read, cmic_cmc0_sbusdma_ch3_opcode_write) && 368 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch3_sbus_start_address_read, cmic_cmc0_sbusdma_ch3_sbus_start_address_write) && 369 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch3_hostmem_start_address_lo_read, cmic_cmc0_sbusdma_ch3_hostmem_start_address_lo_write) && 370 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch3_hostmem_start_address_hi_read, cmic_cmc0_sbusdma_ch3_hostmem_start_address_hi_write) && 371 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch3_desc_start_address_lo_read, cmic_cmc0_sbusdma_ch3_desc_start_address_lo_write) && 372 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch3_desc_start_address_hi_read, cmic_cmc0_sbusdma_ch3_desc_start_address_hi_write) && 373 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_STATUS_REG_ADDR, cmic_cmc0_sbusdma_ch3_status_read, cmic_cmc0_sbusdma_ch3_status_write) && 374 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_hostmem_address_lo_read, cmic_cmc0_sbusdma_ch3_cur_hostmem_address_lo_write) && 375 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_hostmem_address_hi_read, cmic_cmc0_sbusdma_ch3_cur_hostmem_address_hi_write) && 376 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_SBUS_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_sbus_address_read, cmic_cmc0_sbusdma_ch3_cur_sbus_address_write) && 377 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_desc_address_lo_read, cmic_cmc0_sbusdma_ch3_cur_desc_address_lo_write) && 378 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_desc_address_hi_read, cmic_cmc0_sbusdma_ch3_cur_desc_address_hi_write) && 379 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_request_read, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_request_write) && 380 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_count_read, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_count_write) && 381 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_read, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_write) && 382 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_read, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_write) && 383 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_read, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_write) && 384 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_opcode_read, cmic_cmc0_sbusdma_ch3_cur_sbusdma_config_opcode_write) && 385 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_REG_ADDR, cmic_cmc0_sbusdma_ch3_sbusdma_debug_read, cmic_cmc0_sbusdma_ch3_sbusdma_debug_write) && 386 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR_REG_ADDR, cmic_cmc0_sbusdma_ch3_sbusdma_debug_clr_read, cmic_cmc0_sbusdma_ch3_sbusdma_debug_clr_write) && 387 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_TIMER_REG_ADDR, cmic_cmc0_sbusdma_ch3_timer_read, cmic_cmc0_sbusdma_ch3_timer_write) && 388 cmicx_pcid_register_add(CMIC_CMC0_SBUSDMA_CH3_ITER_COUNT_REG_ADDR, cmic_cmc0_sbusdma_ch3_iter_count_read, cmic_cmc0_sbusdma_ch3_iter_count_write) && 389 cmicx_pcid_register_add(CMIC_CMC1_SHARED_CONFIG_REG_ADDR, cmic_cmc1_shared_config_read, cmic_cmc1_shared_config_write) && 390 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CONTROL_REG_ADDR, cmic_cmc1_sbusdma_ch0_control_read, cmic_cmc1_sbusdma_ch0_control_write) && 391 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_REQUEST_REG_ADDR, cmic_cmc1_sbusdma_ch0_request_read, cmic_cmc1_sbusdma_ch0_request_write) && 392 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch0_count_read, cmic_cmc1_sbusdma_ch0_count_write) && 393 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_OPCODE_REG_ADDR, cmic_cmc1_sbusdma_ch0_opcode_read, cmic_cmc1_sbusdma_ch0_opcode_write) && 394 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch0_sbus_start_address_read, cmic_cmc1_sbusdma_ch0_sbus_start_address_write) && 395 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch0_hostmem_start_address_lo_read, cmic_cmc1_sbusdma_ch0_hostmem_start_address_lo_write) && 396 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch0_hostmem_start_address_hi_read, cmic_cmc1_sbusdma_ch0_hostmem_start_address_hi_write) && 397 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch0_desc_start_address_lo_read, cmic_cmc1_sbusdma_ch0_desc_start_address_lo_write) && 398 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch0_desc_start_address_hi_read, cmic_cmc1_sbusdma_ch0_desc_start_address_hi_write) && 399 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_STATUS_REG_ADDR, cmic_cmc1_sbusdma_ch0_status_read, cmic_cmc1_sbusdma_ch0_status_write) && 400 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_hostmem_address_lo_read, cmic_cmc1_sbusdma_ch0_cur_hostmem_address_lo_write) && 401 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_hostmem_address_hi_read, cmic_cmc1_sbusdma_ch0_cur_hostmem_address_hi_write) && 402 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_sbus_address_read, cmic_cmc1_sbusdma_ch0_cur_sbus_address_write) && 403 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_desc_address_lo_read, cmic_cmc1_sbusdma_ch0_cur_desc_address_lo_write) && 404 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_desc_address_hi_read, cmic_cmc1_sbusdma_ch0_cur_desc_address_hi_write) && 405 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_request_read, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_request_write) && 406 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_count_read, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_count_write) && 407 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_read, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_sbus_start_address_write) && 408 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_read, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_lo_write) && 409 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_read, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_hostmem_start_address_hi_write) && 410 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_opcode_read, cmic_cmc1_sbusdma_ch0_cur_sbusdma_config_opcode_write) && 411 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_REG_ADDR, cmic_cmc1_sbusdma_ch0_sbusdma_debug_read, cmic_cmc1_sbusdma_ch0_sbusdma_debug_write) && 412 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_REG_ADDR, cmic_cmc1_sbusdma_ch0_sbusdma_debug_clr_read, cmic_cmc1_sbusdma_ch0_sbusdma_debug_clr_write) && 413 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_TIMER_REG_ADDR, cmic_cmc1_sbusdma_ch0_timer_read, cmic_cmc1_sbusdma_ch0_timer_write) && 414 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH0_ITER_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch0_iter_count_read, cmic_cmc1_sbusdma_ch0_iter_count_write) && 415 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CONTROL_REG_ADDR, cmic_cmc1_sbusdma_ch1_control_read, cmic_cmc1_sbusdma_ch1_control_write) && 416 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_REQUEST_REG_ADDR, cmic_cmc1_sbusdma_ch1_request_read, cmic_cmc1_sbusdma_ch1_request_write) && 417 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch1_count_read, cmic_cmc1_sbusdma_ch1_count_write) && 418 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_OPCODE_REG_ADDR, cmic_cmc1_sbusdma_ch1_opcode_read, cmic_cmc1_sbusdma_ch1_opcode_write) && 419 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch1_sbus_start_address_read, cmic_cmc1_sbusdma_ch1_sbus_start_address_write) && 420 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch1_hostmem_start_address_lo_read, cmic_cmc1_sbusdma_ch1_hostmem_start_address_lo_write) && 421 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch1_hostmem_start_address_hi_read, cmic_cmc1_sbusdma_ch1_hostmem_start_address_hi_write) && 422 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch1_desc_start_address_lo_read, cmic_cmc1_sbusdma_ch1_desc_start_address_lo_write) && 423 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch1_desc_start_address_hi_read, cmic_cmc1_sbusdma_ch1_desc_start_address_hi_write) && 424 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_STATUS_REG_ADDR, cmic_cmc1_sbusdma_ch1_status_read, cmic_cmc1_sbusdma_ch1_status_write) && 425 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_hostmem_address_lo_read, cmic_cmc1_sbusdma_ch1_cur_hostmem_address_lo_write) && 426 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_hostmem_address_hi_read, cmic_cmc1_sbusdma_ch1_cur_hostmem_address_hi_write) && 427 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_sbus_address_read, cmic_cmc1_sbusdma_ch1_cur_sbus_address_write) && 428 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_desc_address_lo_read, cmic_cmc1_sbusdma_ch1_cur_desc_address_lo_write) && 429 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_desc_address_hi_read, cmic_cmc1_sbusdma_ch1_cur_desc_address_hi_write) && 430 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_request_read, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_request_write) && 431 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_count_read, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_count_write) && 432 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_read, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_sbus_start_address_write) && 433 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_read, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_lo_write) && 434 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_read, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_hostmem_start_address_hi_write) && 435 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_opcode_read, cmic_cmc1_sbusdma_ch1_cur_sbusdma_config_opcode_write) && 436 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_REG_ADDR, cmic_cmc1_sbusdma_ch1_sbusdma_debug_read, cmic_cmc1_sbusdma_ch1_sbusdma_debug_write) && 437 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_REG_ADDR, cmic_cmc1_sbusdma_ch1_sbusdma_debug_clr_read, cmic_cmc1_sbusdma_ch1_sbusdma_debug_clr_write) && 438 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_TIMER_REG_ADDR, cmic_cmc1_sbusdma_ch1_timer_read, cmic_cmc1_sbusdma_ch1_timer_write) && 439 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH1_ITER_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch1_iter_count_read, cmic_cmc1_sbusdma_ch1_iter_count_write) && 440 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CONTROL_REG_ADDR, cmic_cmc1_sbusdma_ch2_control_read, cmic_cmc1_sbusdma_ch2_control_write) && 441 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_REQUEST_REG_ADDR, cmic_cmc1_sbusdma_ch2_request_read, cmic_cmc1_sbusdma_ch2_request_write) && 442 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch2_count_read, cmic_cmc1_sbusdma_ch2_count_write) && 443 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_OPCODE_REG_ADDR, cmic_cmc1_sbusdma_ch2_opcode_read, cmic_cmc1_sbusdma_ch2_opcode_write) && 444 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch2_sbus_start_address_read, cmic_cmc1_sbusdma_ch2_sbus_start_address_write) && 445 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch2_hostmem_start_address_lo_read, cmic_cmc1_sbusdma_ch2_hostmem_start_address_lo_write) && 446 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch2_hostmem_start_address_hi_read, cmic_cmc1_sbusdma_ch2_hostmem_start_address_hi_write) && 447 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch2_desc_start_address_lo_read, cmic_cmc1_sbusdma_ch2_desc_start_address_lo_write) && 448 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch2_desc_start_address_hi_read, cmic_cmc1_sbusdma_ch2_desc_start_address_hi_write) && 449 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_STATUS_REG_ADDR, cmic_cmc1_sbusdma_ch2_status_read, cmic_cmc1_sbusdma_ch2_status_write) && 450 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_hostmem_address_lo_read, cmic_cmc1_sbusdma_ch2_cur_hostmem_address_lo_write) && 451 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_hostmem_address_hi_read, cmic_cmc1_sbusdma_ch2_cur_hostmem_address_hi_write) && 452 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_sbus_address_read, cmic_cmc1_sbusdma_ch2_cur_sbus_address_write) && 453 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_desc_address_lo_read, cmic_cmc1_sbusdma_ch2_cur_desc_address_lo_write) && 454 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_desc_address_hi_read, cmic_cmc1_sbusdma_ch2_cur_desc_address_hi_write) && 455 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_request_read, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_request_write) && 456 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_count_read, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_count_write) && 457 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_read, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_sbus_start_address_write) && 458 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_read, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_lo_write) && 459 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_read, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_hostmem_start_address_hi_write) && 460 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_opcode_read, cmic_cmc1_sbusdma_ch2_cur_sbusdma_config_opcode_write) && 461 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_REG_ADDR, cmic_cmc1_sbusdma_ch2_sbusdma_debug_read, cmic_cmc1_sbusdma_ch2_sbusdma_debug_write) && 462 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_REG_ADDR, cmic_cmc1_sbusdma_ch2_sbusdma_debug_clr_read, cmic_cmc1_sbusdma_ch2_sbusdma_debug_clr_write) && 463 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_TIMER_REG_ADDR, cmic_cmc1_sbusdma_ch2_timer_read, cmic_cmc1_sbusdma_ch2_timer_write) && 464 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH2_ITER_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch2_iter_count_read, cmic_cmc1_sbusdma_ch2_iter_count_write) && 465 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CONTROL_REG_ADDR, cmic_cmc1_sbusdma_ch3_control_read, cmic_cmc1_sbusdma_ch3_control_write) && 466 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_REQUEST_REG_ADDR, cmic_cmc1_sbusdma_ch3_request_read, cmic_cmc1_sbusdma_ch3_request_write) && 467 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch3_count_read, cmic_cmc1_sbusdma_ch3_count_write) && 468 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_OPCODE_REG_ADDR, cmic_cmc1_sbusdma_ch3_opcode_read, cmic_cmc1_sbusdma_ch3_opcode_write) && 469 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch3_sbus_start_address_read, cmic_cmc1_sbusdma_ch3_sbus_start_address_write) && 470 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch3_hostmem_start_address_lo_read, cmic_cmc1_sbusdma_ch3_hostmem_start_address_lo_write) && 471 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch3_hostmem_start_address_hi_read, cmic_cmc1_sbusdma_ch3_hostmem_start_address_hi_write) && 472 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch3_desc_start_address_lo_read, cmic_cmc1_sbusdma_ch3_desc_start_address_lo_write) && 473 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch3_desc_start_address_hi_read, cmic_cmc1_sbusdma_ch3_desc_start_address_hi_write) && 474 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_STATUS_REG_ADDR, cmic_cmc1_sbusdma_ch3_status_read, cmic_cmc1_sbusdma_ch3_status_write) && 475 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_hostmem_address_lo_read, cmic_cmc1_sbusdma_ch3_cur_hostmem_address_lo_write) && 476 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_hostmem_address_hi_read, cmic_cmc1_sbusdma_ch3_cur_hostmem_address_hi_write) && 477 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_SBUS_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_sbus_address_read, cmic_cmc1_sbusdma_ch3_cur_sbus_address_write) && 478 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_desc_address_lo_read, cmic_cmc1_sbusdma_ch3_cur_desc_address_lo_write) && 479 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_desc_address_hi_read, cmic_cmc1_sbusdma_ch3_cur_desc_address_hi_write) && 480 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_request_read, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_request_write) && 481 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_count_read, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_count_write) && 482 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_read, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_sbus_start_address_write) && 483 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_read, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_lo_write) && 484 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_read, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_hostmem_start_address_hi_write) && 485 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE_REG_ADDR, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_opcode_read, cmic_cmc1_sbusdma_ch3_cur_sbusdma_config_opcode_write) && 486 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_REG_ADDR, cmic_cmc1_sbusdma_ch3_sbusdma_debug_read, cmic_cmc1_sbusdma_ch3_sbusdma_debug_write) && 487 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR_REG_ADDR, cmic_cmc1_sbusdma_ch3_sbusdma_debug_clr_read, cmic_cmc1_sbusdma_ch3_sbusdma_debug_clr_write) && 488 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_TIMER_REG_ADDR, cmic_cmc1_sbusdma_ch3_timer_read, cmic_cmc1_sbusdma_ch3_timer_write) && 489 cmicx_pcid_register_add(CMIC_CMC1_SBUSDMA_CH3_ITER_COUNT_REG_ADDR, cmic_cmc1_sbusdma_ch3_iter_count_read, cmic_cmc1_sbusdma_ch3_iter_count_write) ) ) { 490 cmicx_error("could not initialize schan PCID registers\n"); 491 } 492 493 /* add PCID packet dma registers */ 494 if ( !( cmicx_pcid_register_add(CMIC_TOP_CONFIG_REG_ADDR, cmic_top_config_read, cmic_top_config_write ) && 495 cmicx_pcid_register_add(CMIC_TOP_EPINTF_RELEASE_ALL_CREDITS_REG_ADDR, cmic_top_epintf_release_all_credits_read, cmic_top_epintf_release_all_credits_write ) && 496 cmicx_pcid_register_add(CMIC_CMC0_SHARED_IRQ_STAT0_REG_ADDR, cmic_cmc0_shared_irq_stat0_read, cmic_cmc0_shared_irq_stat0_write ) && 497 cmicx_pcid_register_add(CMIC_CMC0_SHARED_IRQ_STAT_CLR0_REG_ADDR, cmic_cmc0_shared_irq_stat_clr0_read, cmic_cmc0_shared_irq_stat_clr0_write ) && 498 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_CTRL_REG_ADDR, cmic_cmc0_pktdma_ch0_ctrl_read, cmic_cmc0_pktdma_ch0_ctrl_write ) && 499 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch0_desc_addr_lo_read, cmic_cmc0_pktdma_ch0_desc_addr_lo_write ) && 500 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch0_desc_addr_hi_read, cmic_cmc0_pktdma_ch0_desc_addr_hi_write ) && 501 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch0_desc_halt_addr_lo_read, cmic_cmc0_pktdma_ch0_desc_halt_addr_lo_write ) && 502 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch0_desc_halt_addr_hi_read, cmic_cmc0_pktdma_ch0_desc_halt_addr_hi_write ) && 503 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_STAT_REG_ADDR, cmic_cmc0_pktdma_ch0_stat_read, cmic_cmc0_pktdma_ch0_stat_write ) && 504 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_0_REG_ADDR, cmic_cmc0_pktdma_ch0_cos_ctrl_rx_0_read, cmic_cmc0_pktdma_ch0_cos_ctrl_rx_0_write ) && 505 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_1_REG_ADDR, cmic_cmc0_pktdma_ch0_cos_ctrl_rx_1_read, cmic_cmc0_pktdma_ch0_cos_ctrl_rx_1_write ) && 506 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_INTR_COAL_REG_ADDR, cmic_cmc0_pktdma_ch0_intr_coal_read, cmic_cmc0_pktdma_ch0_intr_coal_write ) && 507 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_CURR_DESC_LO_REG_ADDR, cmic_cmc0_pktdma_ch0_curr_desc_lo_read, cmic_cmc0_pktdma_ch0_curr_desc_lo_write ) && 508 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_CURR_DESC_HI_REG_ADDR, cmic_cmc0_pktdma_ch0_curr_desc_hi_read, cmic_cmc0_pktdma_ch0_curr_desc_hi_write ) && 509 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc0_pktdma_ch0_pkt_count_rxpkt_read, cmic_cmc0_pktdma_ch0_pkt_count_rxpkt_write ) && 510 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc0_pktdma_ch0_pkt_count_txpkt_read, cmic_cmc0_pktdma_ch0_pkt_count_txpkt_write ) && 511 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_CTRL_REG_ADDR, cmic_cmc0_pktdma_ch1_ctrl_read, cmic_cmc0_pktdma_ch1_ctrl_write ) && 512 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch1_desc_addr_lo_read, cmic_cmc0_pktdma_ch1_desc_addr_lo_write ) && 513 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch1_desc_addr_hi_read, cmic_cmc0_pktdma_ch1_desc_addr_hi_write ) && 514 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch1_desc_halt_addr_lo_read, cmic_cmc0_pktdma_ch1_desc_halt_addr_lo_write ) && 515 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch1_desc_halt_addr_hi_read, cmic_cmc0_pktdma_ch1_desc_halt_addr_hi_write ) && 516 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_STAT_REG_ADDR, cmic_cmc0_pktdma_ch1_stat_read, cmic_cmc0_pktdma_ch1_stat_write ) && 517 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_0_REG_ADDR, cmic_cmc0_pktdma_ch1_cos_ctrl_rx_0_read, cmic_cmc0_pktdma_ch1_cos_ctrl_rx_0_write ) && 518 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_1_REG_ADDR, cmic_cmc0_pktdma_ch1_cos_ctrl_rx_1_read, cmic_cmc0_pktdma_ch1_cos_ctrl_rx_1_write ) && 519 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_INTR_COAL_REG_ADDR, cmic_cmc0_pktdma_ch1_intr_coal_read, cmic_cmc0_pktdma_ch1_intr_coal_write ) && 520 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_CURR_DESC_LO_REG_ADDR, cmic_cmc0_pktdma_ch1_curr_desc_lo_read, cmic_cmc0_pktdma_ch1_curr_desc_lo_write ) && 521 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_CURR_DESC_HI_REG_ADDR, cmic_cmc0_pktdma_ch1_curr_desc_hi_read, cmic_cmc0_pktdma_ch1_curr_desc_hi_write ) && 522 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc0_pktdma_ch1_pkt_count_rxpkt_read, cmic_cmc0_pktdma_ch1_pkt_count_rxpkt_write ) && 523 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc0_pktdma_ch1_pkt_count_txpkt_read, cmic_cmc0_pktdma_ch1_pkt_count_txpkt_write ) && 524 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_CTRL_REG_ADDR, cmic_cmc0_pktdma_ch2_ctrl_read, cmic_cmc0_pktdma_ch2_ctrl_write ) && 525 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch2_desc_addr_lo_read, cmic_cmc0_pktdma_ch2_desc_addr_lo_write ) && 526 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch2_desc_addr_hi_read, cmic_cmc0_pktdma_ch2_desc_addr_hi_write ) && 527 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch2_desc_halt_addr_lo_read, cmic_cmc0_pktdma_ch2_desc_halt_addr_lo_write ) && 528 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch2_desc_halt_addr_hi_read, cmic_cmc0_pktdma_ch2_desc_halt_addr_hi_write ) && 529 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_STAT_REG_ADDR, cmic_cmc0_pktdma_ch2_stat_read, cmic_cmc0_pktdma_ch2_stat_write ) && 530 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_0_REG_ADDR, cmic_cmc0_pktdma_ch2_cos_ctrl_rx_0_read, cmic_cmc0_pktdma_ch2_cos_ctrl_rx_0_write ) && 531 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_1_REG_ADDR, cmic_cmc0_pktdma_ch2_cos_ctrl_rx_1_read, cmic_cmc0_pktdma_ch2_cos_ctrl_rx_1_write ) && 532 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_INTR_COAL_REG_ADDR, cmic_cmc0_pktdma_ch2_intr_coal_read, cmic_cmc0_pktdma_ch2_intr_coal_write ) && 533 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_CURR_DESC_LO_REG_ADDR, cmic_cmc0_pktdma_ch2_curr_desc_lo_read, cmic_cmc0_pktdma_ch2_curr_desc_lo_write ) && 534 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_CURR_DESC_HI_REG_ADDR, cmic_cmc0_pktdma_ch2_curr_desc_hi_read, cmic_cmc0_pktdma_ch2_curr_desc_hi_write ) && 535 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc0_pktdma_ch2_pkt_count_rxpkt_read, cmic_cmc0_pktdma_ch2_pkt_count_rxpkt_write ) && 536 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc0_pktdma_ch2_pkt_count_txpkt_read, cmic_cmc0_pktdma_ch2_pkt_count_txpkt_write ) && 537 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_CTRL_REG_ADDR, cmic_cmc0_pktdma_ch3_ctrl_read, cmic_cmc0_pktdma_ch3_ctrl_write ) && 538 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch3_desc_addr_lo_read, cmic_cmc0_pktdma_ch3_desc_addr_lo_write ) && 539 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch3_desc_addr_hi_read, cmic_cmc0_pktdma_ch3_desc_addr_hi_write ) && 540 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch3_desc_halt_addr_lo_read, cmic_cmc0_pktdma_ch3_desc_halt_addr_lo_write ) && 541 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch3_desc_halt_addr_hi_read, cmic_cmc0_pktdma_ch3_desc_halt_addr_hi_write ) && 542 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_STAT_REG_ADDR, cmic_cmc0_pktdma_ch3_stat_read, cmic_cmc0_pktdma_ch3_stat_write ) && 543 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_0_REG_ADDR, cmic_cmc0_pktdma_ch3_cos_ctrl_rx_0_read, cmic_cmc0_pktdma_ch3_cos_ctrl_rx_0_write ) && 544 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_1_REG_ADDR, cmic_cmc0_pktdma_ch3_cos_ctrl_rx_1_read, cmic_cmc0_pktdma_ch3_cos_ctrl_rx_1_write ) && 545 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_INTR_COAL_REG_ADDR, cmic_cmc0_pktdma_ch3_intr_coal_read, cmic_cmc0_pktdma_ch3_intr_coal_write ) && 546 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_CURR_DESC_LO_REG_ADDR, cmic_cmc0_pktdma_ch3_curr_desc_lo_read, cmic_cmc0_pktdma_ch3_curr_desc_lo_write ) && 547 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_CURR_DESC_HI_REG_ADDR, cmic_cmc0_pktdma_ch3_curr_desc_hi_read, cmic_cmc0_pktdma_ch3_curr_desc_hi_write ) && 548 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc0_pktdma_ch3_pkt_count_rxpkt_read, cmic_cmc0_pktdma_ch3_pkt_count_rxpkt_write ) && 549 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc0_pktdma_ch3_pkt_count_txpkt_read, cmic_cmc0_pktdma_ch3_pkt_count_txpkt_write ) && 550 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_CTRL_REG_ADDR, cmic_cmc0_pktdma_ch4_ctrl_read, cmic_cmc0_pktdma_ch4_ctrl_write ) && 551 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch4_desc_addr_lo_read, cmic_cmc0_pktdma_ch4_desc_addr_lo_write ) && 552 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch4_desc_addr_hi_read, cmic_cmc0_pktdma_ch4_desc_addr_hi_write ) && 553 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch4_desc_halt_addr_lo_read, cmic_cmc0_pktdma_ch4_desc_halt_addr_lo_write ) && 554 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch4_desc_halt_addr_hi_read, cmic_cmc0_pktdma_ch4_desc_halt_addr_hi_write ) && 555 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_STAT_REG_ADDR, cmic_cmc0_pktdma_ch4_stat_read, cmic_cmc0_pktdma_ch4_stat_write ) && 556 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_0_REG_ADDR, cmic_cmc0_pktdma_ch4_cos_ctrl_rx_0_read, cmic_cmc0_pktdma_ch4_cos_ctrl_rx_0_write ) && 557 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_1_REG_ADDR, cmic_cmc0_pktdma_ch4_cos_ctrl_rx_1_read, cmic_cmc0_pktdma_ch4_cos_ctrl_rx_1_write ) && 558 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_INTR_COAL_REG_ADDR, cmic_cmc0_pktdma_ch4_intr_coal_read, cmic_cmc0_pktdma_ch4_intr_coal_write ) && 559 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_CURR_DESC_LO_REG_ADDR, cmic_cmc0_pktdma_ch4_curr_desc_lo_read, cmic_cmc0_pktdma_ch4_curr_desc_lo_write ) && 560 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_CURR_DESC_HI_REG_ADDR, cmic_cmc0_pktdma_ch4_curr_desc_hi_read, cmic_cmc0_pktdma_ch4_curr_desc_hi_write ) && 561 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc0_pktdma_ch4_pkt_count_rxpkt_read, cmic_cmc0_pktdma_ch4_pkt_count_rxpkt_write ) && 562 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc0_pktdma_ch4_pkt_count_txpkt_read, cmic_cmc0_pktdma_ch4_pkt_count_txpkt_write ) && 563 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_CTRL_REG_ADDR, cmic_cmc0_pktdma_ch5_ctrl_read, cmic_cmc0_pktdma_ch5_ctrl_write ) && 564 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch5_desc_addr_lo_read, cmic_cmc0_pktdma_ch5_desc_addr_lo_write ) && 565 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch5_desc_addr_hi_read, cmic_cmc0_pktdma_ch5_desc_addr_hi_write ) && 566 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch5_desc_halt_addr_lo_read, cmic_cmc0_pktdma_ch5_desc_halt_addr_lo_write ) && 567 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch5_desc_halt_addr_hi_read, cmic_cmc0_pktdma_ch5_desc_halt_addr_hi_write ) && 568 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_STAT_REG_ADDR, cmic_cmc0_pktdma_ch5_stat_read, cmic_cmc0_pktdma_ch5_stat_write ) && 569 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_0_REG_ADDR, cmic_cmc0_pktdma_ch5_cos_ctrl_rx_0_read, cmic_cmc0_pktdma_ch5_cos_ctrl_rx_0_write ) && 570 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_1_REG_ADDR, cmic_cmc0_pktdma_ch5_cos_ctrl_rx_1_read, cmic_cmc0_pktdma_ch5_cos_ctrl_rx_1_write ) && 571 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_INTR_COAL_REG_ADDR, cmic_cmc0_pktdma_ch5_intr_coal_read, cmic_cmc0_pktdma_ch5_intr_coal_write ) && 572 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_CURR_DESC_LO_REG_ADDR, cmic_cmc0_pktdma_ch5_curr_desc_lo_read, cmic_cmc0_pktdma_ch5_curr_desc_lo_write ) && 573 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_CURR_DESC_HI_REG_ADDR, cmic_cmc0_pktdma_ch5_curr_desc_hi_read, cmic_cmc0_pktdma_ch5_curr_desc_hi_write ) && 574 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc0_pktdma_ch5_pkt_count_rxpkt_read, cmic_cmc0_pktdma_ch5_pkt_count_rxpkt_write ) && 575 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc0_pktdma_ch5_pkt_count_txpkt_read, cmic_cmc0_pktdma_ch5_pkt_count_txpkt_write ) && 576 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_CTRL_REG_ADDR, cmic_cmc0_pktdma_ch6_ctrl_read, cmic_cmc0_pktdma_ch6_ctrl_write ) && 577 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch6_desc_addr_lo_read, cmic_cmc0_pktdma_ch6_desc_addr_lo_write ) && 578 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch6_desc_addr_hi_read, cmic_cmc0_pktdma_ch6_desc_addr_hi_write ) && 579 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch6_desc_halt_addr_lo_read, cmic_cmc0_pktdma_ch6_desc_halt_addr_lo_write ) && 580 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch6_desc_halt_addr_hi_read, cmic_cmc0_pktdma_ch6_desc_halt_addr_hi_write ) && 581 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_STAT_REG_ADDR, cmic_cmc0_pktdma_ch6_stat_read, cmic_cmc0_pktdma_ch6_stat_write ) && 582 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_0_REG_ADDR, cmic_cmc0_pktdma_ch6_cos_ctrl_rx_0_read, cmic_cmc0_pktdma_ch6_cos_ctrl_rx_0_write ) && 583 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_1_REG_ADDR, cmic_cmc0_pktdma_ch6_cos_ctrl_rx_1_read, cmic_cmc0_pktdma_ch6_cos_ctrl_rx_1_write ) && 584 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_INTR_COAL_REG_ADDR, cmic_cmc0_pktdma_ch6_intr_coal_read, cmic_cmc0_pktdma_ch6_intr_coal_write ) && 585 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_CURR_DESC_LO_REG_ADDR, cmic_cmc0_pktdma_ch6_curr_desc_lo_read, cmic_cmc0_pktdma_ch6_curr_desc_lo_write ) && 586 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_CURR_DESC_HI_REG_ADDR, cmic_cmc0_pktdma_ch6_curr_desc_hi_read, cmic_cmc0_pktdma_ch6_curr_desc_hi_write ) && 587 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc0_pktdma_ch6_pkt_count_rxpkt_read, cmic_cmc0_pktdma_ch6_pkt_count_rxpkt_write ) && 588 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc0_pktdma_ch6_pkt_count_txpkt_read, cmic_cmc0_pktdma_ch6_pkt_count_txpkt_write ) && 589 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_CTRL_REG_ADDR, cmic_cmc0_pktdma_ch7_ctrl_read, cmic_cmc0_pktdma_ch7_ctrl_write ) && 590 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch7_desc_addr_lo_read, cmic_cmc0_pktdma_ch7_desc_addr_lo_write ) && 591 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch7_desc_addr_hi_read, cmic_cmc0_pktdma_ch7_desc_addr_hi_write ) && 592 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc0_pktdma_ch7_desc_halt_addr_lo_read, cmic_cmc0_pktdma_ch7_desc_halt_addr_lo_write ) && 593 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc0_pktdma_ch7_desc_halt_addr_hi_read, cmic_cmc0_pktdma_ch7_desc_halt_addr_hi_write ) && 594 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_STAT_REG_ADDR, cmic_cmc0_pktdma_ch7_stat_read, cmic_cmc0_pktdma_ch7_stat_write ) && 595 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_0_REG_ADDR, cmic_cmc0_pktdma_ch7_cos_ctrl_rx_0_read, cmic_cmc0_pktdma_ch7_cos_ctrl_rx_0_write ) && 596 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_1_REG_ADDR, cmic_cmc0_pktdma_ch7_cos_ctrl_rx_1_read, cmic_cmc0_pktdma_ch7_cos_ctrl_rx_1_write ) && 597 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_INTR_COAL_REG_ADDR, cmic_cmc0_pktdma_ch7_intr_coal_read, cmic_cmc0_pktdma_ch7_intr_coal_write ) && 598 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_CURR_DESC_LO_REG_ADDR, cmic_cmc0_pktdma_ch7_curr_desc_lo_read, cmic_cmc0_pktdma_ch7_curr_desc_lo_write ) && 599 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_CURR_DESC_HI_REG_ADDR, cmic_cmc0_pktdma_ch7_curr_desc_hi_read, cmic_cmc0_pktdma_ch7_curr_desc_hi_write ) && 600 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc0_pktdma_ch7_pkt_count_rxpkt_read, cmic_cmc0_pktdma_ch7_pkt_count_rxpkt_write ) && 601 cmicx_pcid_register_add(CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc0_pktdma_ch7_pkt_count_txpkt_read, cmic_cmc0_pktdma_ch7_pkt_count_txpkt_write ) && 602 cmicx_pcid_register_add(CMIC_CMC1_SHARED_IRQ_STAT0_REG_ADDR, cmic_cmc1_shared_irq_stat0_read, cmic_cmc1_shared_irq_stat0_write ) && 603 cmicx_pcid_register_add(CMIC_CMC1_SHARED_IRQ_STAT_CLR0_REG_ADDR, cmic_cmc1_shared_irq_stat_clr0_read, cmic_cmc1_shared_irq_stat_clr0_write ) && 604 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_CTRL_REG_ADDR, cmic_cmc1_pktdma_ch0_ctrl_read, cmic_cmc1_pktdma_ch0_ctrl_write ) && 605 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch0_desc_addr_lo_read, cmic_cmc1_pktdma_ch0_desc_addr_lo_write ) && 606 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch0_desc_addr_hi_read, cmic_cmc1_pktdma_ch0_desc_addr_hi_write ) && 607 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch0_desc_halt_addr_lo_read, cmic_cmc1_pktdma_ch0_desc_halt_addr_lo_write ) && 608 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch0_desc_halt_addr_hi_read, cmic_cmc1_pktdma_ch0_desc_halt_addr_hi_write ) && 609 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_STAT_REG_ADDR, cmic_cmc1_pktdma_ch0_stat_read, cmic_cmc1_pktdma_ch0_stat_write ) && 610 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_0_REG_ADDR, cmic_cmc1_pktdma_ch0_cos_ctrl_rx_0_read, cmic_cmc1_pktdma_ch0_cos_ctrl_rx_0_write ) && 611 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_1_REG_ADDR, cmic_cmc1_pktdma_ch0_cos_ctrl_rx_1_read, cmic_cmc1_pktdma_ch0_cos_ctrl_rx_1_write ) && 612 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_INTR_COAL_REG_ADDR, cmic_cmc1_pktdma_ch0_intr_coal_read, cmic_cmc1_pktdma_ch0_intr_coal_write ) && 613 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_CURR_DESC_LO_REG_ADDR, cmic_cmc1_pktdma_ch0_curr_desc_lo_read, cmic_cmc1_pktdma_ch0_curr_desc_lo_write ) && 614 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_CURR_DESC_HI_REG_ADDR, cmic_cmc1_pktdma_ch0_curr_desc_hi_read, cmic_cmc1_pktdma_ch0_curr_desc_hi_write ) && 615 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc1_pktdma_ch0_pkt_count_rxpkt_read, cmic_cmc1_pktdma_ch0_pkt_count_rxpkt_write ) && 616 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc1_pktdma_ch0_pkt_count_txpkt_read, cmic_cmc1_pktdma_ch0_pkt_count_txpkt_write ) && 617 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_CTRL_REG_ADDR, cmic_cmc1_pktdma_ch1_ctrl_read, cmic_cmc1_pktdma_ch1_ctrl_write ) && 618 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch1_desc_addr_lo_read, cmic_cmc1_pktdma_ch1_desc_addr_lo_write ) && 619 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch1_desc_addr_hi_read, cmic_cmc1_pktdma_ch1_desc_addr_hi_write ) && 620 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch1_desc_halt_addr_lo_read, cmic_cmc1_pktdma_ch1_desc_halt_addr_lo_write ) && 621 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch1_desc_halt_addr_hi_read, cmic_cmc1_pktdma_ch1_desc_halt_addr_hi_write ) && 622 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_STAT_REG_ADDR, cmic_cmc1_pktdma_ch1_stat_read, cmic_cmc1_pktdma_ch1_stat_write ) && 623 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_0_REG_ADDR, cmic_cmc1_pktdma_ch1_cos_ctrl_rx_0_read, cmic_cmc1_pktdma_ch1_cos_ctrl_rx_0_write ) && 624 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_1_REG_ADDR, cmic_cmc1_pktdma_ch1_cos_ctrl_rx_1_read, cmic_cmc1_pktdma_ch1_cos_ctrl_rx_1_write ) && 625 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_INTR_COAL_REG_ADDR, cmic_cmc1_pktdma_ch1_intr_coal_read, cmic_cmc1_pktdma_ch1_intr_coal_write ) && 626 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_CURR_DESC_LO_REG_ADDR, cmic_cmc1_pktdma_ch1_curr_desc_lo_read, cmic_cmc1_pktdma_ch1_curr_desc_lo_write ) && 627 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_CURR_DESC_HI_REG_ADDR, cmic_cmc1_pktdma_ch1_curr_desc_hi_read, cmic_cmc1_pktdma_ch1_curr_desc_hi_write ) && 628 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc1_pktdma_ch1_pkt_count_rxpkt_read, cmic_cmc1_pktdma_ch1_pkt_count_rxpkt_write ) && 629 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc1_pktdma_ch1_pkt_count_txpkt_read, cmic_cmc1_pktdma_ch1_pkt_count_txpkt_write ) && 630 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_CTRL_REG_ADDR, cmic_cmc1_pktdma_ch2_ctrl_read, cmic_cmc1_pktdma_ch2_ctrl_write ) && 631 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch2_desc_addr_lo_read, cmic_cmc1_pktdma_ch2_desc_addr_lo_write ) && 632 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch2_desc_addr_hi_read, cmic_cmc1_pktdma_ch2_desc_addr_hi_write ) && 633 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch2_desc_halt_addr_lo_read, cmic_cmc1_pktdma_ch2_desc_halt_addr_lo_write ) && 634 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch2_desc_halt_addr_hi_read, cmic_cmc1_pktdma_ch2_desc_halt_addr_hi_write ) && 635 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_STAT_REG_ADDR, cmic_cmc1_pktdma_ch2_stat_read, cmic_cmc1_pktdma_ch2_stat_write ) && 636 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_0_REG_ADDR, cmic_cmc1_pktdma_ch2_cos_ctrl_rx_0_read, cmic_cmc1_pktdma_ch2_cos_ctrl_rx_0_write ) && 637 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_1_REG_ADDR, cmic_cmc1_pktdma_ch2_cos_ctrl_rx_1_read, cmic_cmc1_pktdma_ch2_cos_ctrl_rx_1_write ) && 638 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_INTR_COAL_REG_ADDR, cmic_cmc1_pktdma_ch2_intr_coal_read, cmic_cmc1_pktdma_ch2_intr_coal_write ) && 639 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_CURR_DESC_LO_REG_ADDR, cmic_cmc1_pktdma_ch2_curr_desc_lo_read, cmic_cmc1_pktdma_ch2_curr_desc_lo_write ) && 640 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_CURR_DESC_HI_REG_ADDR, cmic_cmc1_pktdma_ch2_curr_desc_hi_read, cmic_cmc1_pktdma_ch2_curr_desc_hi_write ) && 641 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc1_pktdma_ch2_pkt_count_rxpkt_read, cmic_cmc1_pktdma_ch2_pkt_count_rxpkt_write ) && 642 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc1_pktdma_ch2_pkt_count_txpkt_read, cmic_cmc1_pktdma_ch2_pkt_count_txpkt_write ) && 643 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_CTRL_REG_ADDR, cmic_cmc1_pktdma_ch3_ctrl_read, cmic_cmc1_pktdma_ch3_ctrl_write ) && 644 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch3_desc_addr_lo_read, cmic_cmc1_pktdma_ch3_desc_addr_lo_write ) && 645 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch3_desc_addr_hi_read, cmic_cmc1_pktdma_ch3_desc_addr_hi_write ) && 646 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch3_desc_halt_addr_lo_read, cmic_cmc1_pktdma_ch3_desc_halt_addr_lo_write ) && 647 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch3_desc_halt_addr_hi_read, cmic_cmc1_pktdma_ch3_desc_halt_addr_hi_write ) && 648 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_STAT_REG_ADDR, cmic_cmc1_pktdma_ch3_stat_read, cmic_cmc1_pktdma_ch3_stat_write ) && 649 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_0_REG_ADDR, cmic_cmc1_pktdma_ch3_cos_ctrl_rx_0_read, cmic_cmc1_pktdma_ch3_cos_ctrl_rx_0_write ) && 650 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_1_REG_ADDR, cmic_cmc1_pktdma_ch3_cos_ctrl_rx_1_read, cmic_cmc1_pktdma_ch3_cos_ctrl_rx_1_write ) && 651 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_INTR_COAL_REG_ADDR, cmic_cmc1_pktdma_ch3_intr_coal_read, cmic_cmc1_pktdma_ch3_intr_coal_write ) && 652 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_CURR_DESC_LO_REG_ADDR, cmic_cmc1_pktdma_ch3_curr_desc_lo_read, cmic_cmc1_pktdma_ch3_curr_desc_lo_write ) && 653 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_CURR_DESC_HI_REG_ADDR, cmic_cmc1_pktdma_ch3_curr_desc_hi_read, cmic_cmc1_pktdma_ch3_curr_desc_hi_write ) && 654 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc1_pktdma_ch3_pkt_count_rxpkt_read, cmic_cmc1_pktdma_ch3_pkt_count_rxpkt_write ) && 655 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc1_pktdma_ch3_pkt_count_txpkt_read, cmic_cmc1_pktdma_ch3_pkt_count_txpkt_write ) && 656 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_CTRL_REG_ADDR, cmic_cmc1_pktdma_ch4_ctrl_read, cmic_cmc1_pktdma_ch4_ctrl_write ) && 657 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch4_desc_addr_lo_read, cmic_cmc1_pktdma_ch4_desc_addr_lo_write ) && 658 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch4_desc_addr_hi_read, cmic_cmc1_pktdma_ch4_desc_addr_hi_write ) && 659 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch4_desc_halt_addr_lo_read, cmic_cmc1_pktdma_ch4_desc_halt_addr_lo_write ) && 660 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch4_desc_halt_addr_hi_read, cmic_cmc1_pktdma_ch4_desc_halt_addr_hi_write ) && 661 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_STAT_REG_ADDR, cmic_cmc1_pktdma_ch4_stat_read, cmic_cmc1_pktdma_ch4_stat_write ) && 662 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_0_REG_ADDR, cmic_cmc1_pktdma_ch4_cos_ctrl_rx_0_read, cmic_cmc1_pktdma_ch4_cos_ctrl_rx_0_write ) && 663 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_1_REG_ADDR, cmic_cmc1_pktdma_ch4_cos_ctrl_rx_1_read, cmic_cmc1_pktdma_ch4_cos_ctrl_rx_1_write ) && 664 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_INTR_COAL_REG_ADDR, cmic_cmc1_pktdma_ch4_intr_coal_read, cmic_cmc1_pktdma_ch4_intr_coal_write ) && 665 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_CURR_DESC_LO_REG_ADDR, cmic_cmc1_pktdma_ch4_curr_desc_lo_read, cmic_cmc1_pktdma_ch4_curr_desc_lo_write ) && 666 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_CURR_DESC_HI_REG_ADDR, cmic_cmc1_pktdma_ch4_curr_desc_hi_read, cmic_cmc1_pktdma_ch4_curr_desc_hi_write ) && 667 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc1_pktdma_ch4_pkt_count_rxpkt_read, cmic_cmc1_pktdma_ch4_pkt_count_rxpkt_write ) && 668 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc1_pktdma_ch4_pkt_count_txpkt_read, cmic_cmc1_pktdma_ch4_pkt_count_txpkt_write ) && 669 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_CTRL_REG_ADDR, cmic_cmc1_pktdma_ch5_ctrl_read, cmic_cmc1_pktdma_ch5_ctrl_write ) && 670 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch5_desc_addr_lo_read, cmic_cmc1_pktdma_ch5_desc_addr_lo_write ) && 671 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch5_desc_addr_hi_read, cmic_cmc1_pktdma_ch5_desc_addr_hi_write ) && 672 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch5_desc_halt_addr_lo_read, cmic_cmc1_pktdma_ch5_desc_halt_addr_lo_write ) && 673 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch5_desc_halt_addr_hi_read, cmic_cmc1_pktdma_ch5_desc_halt_addr_hi_write ) && 674 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_STAT_REG_ADDR, cmic_cmc1_pktdma_ch5_stat_read, cmic_cmc1_pktdma_ch5_stat_write ) && 675 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_0_REG_ADDR, cmic_cmc1_pktdma_ch5_cos_ctrl_rx_0_read, cmic_cmc1_pktdma_ch5_cos_ctrl_rx_0_write ) && 676 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_1_REG_ADDR, cmic_cmc1_pktdma_ch5_cos_ctrl_rx_1_read, cmic_cmc1_pktdma_ch5_cos_ctrl_rx_1_write ) && 677 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_INTR_COAL_REG_ADDR, cmic_cmc1_pktdma_ch5_intr_coal_read, cmic_cmc1_pktdma_ch5_intr_coal_write ) && 678 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_CURR_DESC_LO_REG_ADDR, cmic_cmc1_pktdma_ch5_curr_desc_lo_read, cmic_cmc1_pktdma_ch5_curr_desc_lo_write ) && 679 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_CURR_DESC_HI_REG_ADDR, cmic_cmc1_pktdma_ch5_curr_desc_hi_read, cmic_cmc1_pktdma_ch5_curr_desc_hi_write ) && 680 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc1_pktdma_ch5_pkt_count_rxpkt_read, cmic_cmc1_pktdma_ch5_pkt_count_rxpkt_write ) && 681 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc1_pktdma_ch5_pkt_count_txpkt_read, cmic_cmc1_pktdma_ch5_pkt_count_txpkt_write ) && 682 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_CTRL_REG_ADDR, cmic_cmc1_pktdma_ch6_ctrl_read, cmic_cmc1_pktdma_ch6_ctrl_write ) && 683 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch6_desc_addr_lo_read, cmic_cmc1_pktdma_ch6_desc_addr_lo_write ) && 684 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch6_desc_addr_hi_read, cmic_cmc1_pktdma_ch6_desc_addr_hi_write ) && 685 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch6_desc_halt_addr_lo_read, cmic_cmc1_pktdma_ch6_desc_halt_addr_lo_write ) && 686 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch6_desc_halt_addr_hi_read, cmic_cmc1_pktdma_ch6_desc_halt_addr_hi_write ) && 687 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_STAT_REG_ADDR, cmic_cmc1_pktdma_ch6_stat_read, cmic_cmc1_pktdma_ch6_stat_write ) && 688 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_0_REG_ADDR, cmic_cmc1_pktdma_ch6_cos_ctrl_rx_0_read, cmic_cmc1_pktdma_ch6_cos_ctrl_rx_0_write ) && 689 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_1_REG_ADDR, cmic_cmc1_pktdma_ch6_cos_ctrl_rx_1_read, cmic_cmc1_pktdma_ch6_cos_ctrl_rx_1_write ) && 690 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_INTR_COAL_REG_ADDR, cmic_cmc1_pktdma_ch6_intr_coal_read, cmic_cmc1_pktdma_ch6_intr_coal_write ) && 691 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_CURR_DESC_LO_REG_ADDR, cmic_cmc1_pktdma_ch6_curr_desc_lo_read, cmic_cmc1_pktdma_ch6_curr_desc_lo_write ) && 692 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_CURR_DESC_HI_REG_ADDR, cmic_cmc1_pktdma_ch6_curr_desc_hi_read, cmic_cmc1_pktdma_ch6_curr_desc_hi_write ) && 693 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc1_pktdma_ch6_pkt_count_rxpkt_read, cmic_cmc1_pktdma_ch6_pkt_count_rxpkt_write ) && 694 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc1_pktdma_ch6_pkt_count_txpkt_read, cmic_cmc1_pktdma_ch6_pkt_count_txpkt_write ) && 695 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_CTRL_REG_ADDR, cmic_cmc1_pktdma_ch7_ctrl_read, cmic_cmc1_pktdma_ch7_ctrl_write ) && 696 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch7_desc_addr_lo_read, cmic_cmc1_pktdma_ch7_desc_addr_lo_write ) && 697 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch7_desc_addr_hi_read, cmic_cmc1_pktdma_ch7_desc_addr_hi_write ) && 698 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_LO_REG_ADDR, cmic_cmc1_pktdma_ch7_desc_halt_addr_lo_read, cmic_cmc1_pktdma_ch7_desc_halt_addr_lo_write ) && 699 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_HI_REG_ADDR, cmic_cmc1_pktdma_ch7_desc_halt_addr_hi_read, cmic_cmc1_pktdma_ch7_desc_halt_addr_hi_write ) && 700 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_STAT_REG_ADDR, cmic_cmc1_pktdma_ch7_stat_read, cmic_cmc1_pktdma_ch7_stat_write ) && 701 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_0_REG_ADDR, cmic_cmc1_pktdma_ch7_cos_ctrl_rx_0_read, cmic_cmc1_pktdma_ch7_cos_ctrl_rx_0_write ) && 702 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_1_REG_ADDR, cmic_cmc1_pktdma_ch7_cos_ctrl_rx_1_read, cmic_cmc1_pktdma_ch7_cos_ctrl_rx_1_write ) && 703 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_INTR_COAL_REG_ADDR, cmic_cmc1_pktdma_ch7_intr_coal_read, cmic_cmc1_pktdma_ch7_intr_coal_write ) && 704 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_CURR_DESC_LO_REG_ADDR, cmic_cmc1_pktdma_ch7_curr_desc_lo_read, cmic_cmc1_pktdma_ch7_curr_desc_lo_write ) && 705 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_CURR_DESC_HI_REG_ADDR, cmic_cmc1_pktdma_ch7_curr_desc_hi_read, cmic_cmc1_pktdma_ch7_curr_desc_hi_write ) && 706 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT_REG_ADDR, cmic_cmc1_pktdma_ch7_pkt_count_rxpkt_read, cmic_cmc1_pktdma_ch7_pkt_count_rxpkt_write ) && 707 cmicx_pcid_register_add(CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_TXPKT_REG_ADDR, cmic_cmc1_pktdma_ch7_pkt_count_txpkt_read, cmic_cmc1_pktdma_ch7_pkt_count_txpkt_write ) ) ) { 708 cmicx_error("could not initialize packet dma PCID registers\n"); 709 } 710 711 /* add PCID schan fifo registers */ 712 /*if ( !( cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE0_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message1_read, cmic_cmc0_schan_fifo_buff1_message1_write ) && 713 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE1_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message1_read, cmic_cmc0_schan_fifo_buff1_message1_write ) && 714 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE2_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message2_read, cmic_cmc0_schan_fifo_buff1_message2_write ) && 715 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE3_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message3_read, cmic_cmc0_schan_fifo_buff1_message3_write ) && 716 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE4_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message4_read, cmic_cmc0_schan_fifo_buff1_message4_write ) && 717 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE5_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message5_read, cmic_cmc0_schan_fifo_buff1_message5_write ) && 718 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE6_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message6_read, cmic_cmc0_schan_fifo_buff1_message6_write ) && 719 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE7_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message7_read, cmic_cmc0_schan_fifo_buff1_message7_write ) && 720 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE8_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message8_read, cmic_cmc0_schan_fifo_buff1_message8_write ) && 721 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE9_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message9_read, cmic_cmc0_schan_fifo_buff1_message9_write ) && 722 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE10_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message10_read, cmic_cmc0_schan_fifo_buff1_message10_write ) && 723 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE11_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message11_read, cmic_cmc0_schan_fifo_buff1_message11_write ) && 724 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE12_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message12_read, cmic_cmc0_schan_fifo_buff1_message12_write ) && 725 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE13_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message13_read, cmic_cmc0_schan_fifo_buff1_message13_write ) && 726 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE14_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message14_read, cmic_cmc0_schan_fifo_buff1_message14_write ) && 727 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF1_MESSAGE15_REG_ADDR, cmic_cmc0_schan_fifo_buff1_message15_read, cmic_cmc0_schan_fifo_buff1_message15_write ) && 728 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE0_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message0_read, cmic_cmc0_schan_fifo_buff2_message0_write ) && 729 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE1_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message1_read, cmic_cmc0_schan_fifo_buff2_message1_write ) && 730 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE2_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message2_read, cmic_cmc0_schan_fifo_buff2_message2_write ) && 731 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE3_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message3_read, cmic_cmc0_schan_fifo_buff2_message3_write ) && 732 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE4_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message4_read, cmic_cmc0_schan_fifo_buff2_message4_write ) && 733 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE5_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message5_read, cmic_cmc0_schan_fifo_buff2_message5_write ) && 734 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE6_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message6_read, cmic_cmc0_schan_fifo_buff2_message6_write ) && 735 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE7_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message7_read, cmic_cmc0_schan_fifo_buff2_message7_write ) && 736 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE8_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message8_read, cmic_cmc0_schan_fifo_buff2_message8_write ) && 737 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE9_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message9_read, cmic_cmc0_schan_fifo_buff2_message9_write ) && 738 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE10_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message10_read, cmic_cmc0_schan_fifo_buff2_message10_write ) && 739 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE11_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message11_read, cmic_cmc0_schan_fifo_buff2_message11_write ) && 740 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE12_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message12_read, cmic_cmc0_schan_fifo_buff2_message12_write ) && 741 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE13_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message13_read, cmic_cmc0_schan_fifo_buff2_message13_write ) && 742 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE14_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message14_read, cmic_cmc0_schan_fifo_buff2_message14_write ) && 743 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_BUFF2_MESSAGE15_REG_ADDR, cmic_cmc0_schan_fifo_buff2_message15_read, cmic_cmc0_schan_fifo_buff2_message15_write ) && 744 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_STATUS_BUFF1_REG_ADDR, cmic_cmc0_schan_fifo_status_buff1_read, cmic_cmc0_schan_fifo_status_buff1_write ) && 745 cmicx_pcid_register_add( CMIC_CMC0_SCHAN_FIFO_STATUS_BUFF2_REG_ADDR, cmic_cmc0_schan_fifo_status_buff2_read, cmic_cmc0_schan_fifo_status_buff2_write ) && 746 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE0_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message0_read, cmic_cmc1_schan_fifo_buff1_message0_write ) && 747 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE1_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message1_read, cmic_cmc1_schan_fifo_buff1_message1_write ) && 748 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE2_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message2_read, cmic_cmc1_schan_fifo_buff1_message2_write ) && 749 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE3_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message3_read, cmic_cmc1_schan_fifo_buff1_message3_write ) && 750 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE4_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message4_read, cmic_cmc1_schan_fifo_buff1_message4_write ) && 751 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE5_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message5_read, cmic_cmc1_schan_fifo_buff1_message5_write ) && 752 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE6_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message6_read, cmic_cmc1_schan_fifo_buff1_message6_write ) && 753 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE7_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message7_read, cmic_cmc1_schan_fifo_buff1_message7_write ) && 754 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE8_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message8_read, cmic_cmc1_schan_fifo_buff1_message8_write ) && 755 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE9_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message9_read, cmic_cmc1_schan_fifo_buff1_message9_write ) && 756 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE10_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message10_read, cmic_cmc1_schan_fifo_buff1_message10_write ) && 757 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE11_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message11_read, cmic_cmc1_schan_fifo_buff1_message11_write ) && 758 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE12_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message12_read, cmic_cmc1_schan_fifo_buff1_message12_write ) && 759 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE13_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message13_read, cmic_cmc1_schan_fifo_buff1_message13_write ) && 760 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE14_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message14_read, cmic_cmc1_schan_fifo_buff1_message14_write ) && 761 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF1_MESSAGE15_REG_ADDR, cmic_cmc1_schan_fifo_buff1_message15_read, cmic_cmc1_schan_fifo_buff1_message15_write ) && 762 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE0_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message0_read, cmic_cmc1_schan_fifo_buff2_message0_write ) && 763 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE1_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message1_read, cmic_cmc1_schan_fifo_buff2_message1_write ) && 764 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE2_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message2_read, cmic_cmc1_schan_fifo_buff2_message2_write ) && 765 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE3_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message3_read, cmic_cmc1_schan_fifo_buff2_message3_write ) && 766 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE4_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message4_read, cmic_cmc1_schan_fifo_buff2_message4_write ) && 767 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE5_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message5_read, cmic_cmc1_schan_fifo_buff2_message5_write ) && 768 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE6_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message6_read, cmic_cmc1_schan_fifo_buff2_message6_write ) && 769 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE7_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message7_read, cmic_cmc1_schan_fifo_buff2_message7_write ) && 770 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE8_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message8_read, cmic_cmc1_schan_fifo_buff2_message8_write ) && 771 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE9_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message9_read, cmic_cmc1_schan_fifo_buff2_message9_write ) && 772 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE10_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message10_read, cmic_cmc1_schan_fifo_buff2_message10_write ) && 773 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE11_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message11_read, cmic_cmc1_schan_fifo_buff2_message11_write ) && 774 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE12_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message12_read, cmic_cmc1_schan_fifo_buff2_message12_write ) && 775 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE13_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message13_read, cmic_cmc1_schan_fifo_buff2_message13_write ) && 776 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE14_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message14_read, cmic_cmc1_schan_fifo_buff2_message14_write ) && 777 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_BUFF2_MESSAGE15_REG_ADDR, cmic_cmc1_schan_fifo_buff2_message15_read, cmic_cmc1_schan_fifo_buff2_message15_write ) && 778 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_STATUS_BUFF1_REG_ADDR, cmic_cmc1_schan_fifo_status_buff1_read, cmic_cmc1_schan_fifo_status_buff1_write ) && 779 cmicx_pcid_register_add( CMIC_CMC1_SCHAN_FIFO_STATUS_BUFF2_REG_ADDR, cmic_cmc1_schan_fifo_status_buff2_read, cmic_cmc1_schan_fifo_status_buff2_write ) ) ) { 780 cmicx_error("could not initialize schan fifo PCID registers\n"); 781 } 782 */ 783 784 785 /* log message of successful initialization of cmicx sim */ 786 cmicx_log("CMICx simulation successfully initialized."); 787 cmicx_log_newline(); 788 return true; 789 } 790 791 792 /* updates the cmicx to its next state, based on the current state */ 793 bool cmicx_update(pcid_info_t *pcid_info) { 794 795 int i; 796 int j; 797 798 /* calculate (and display) the time it's been since the last cmicx sim top-level update */ 799 cmicx_log_level_set(0); 800 cmicx_log("time since last cmicx_update: "); 801 cmicx_log_elapsed_time(); 802 cmicx_log_newline(); 803 cmicx_log_level_set(3); 804 805 806 /************************************************************************/ 807 /* old method: loop through each unit needing an update and update once */ 808 /************************************************************************/ 809 810 /* update the state of each outstanding schan command coming from an schan block */ 811 /* 812 cmicx_schan_update(pcid_info, &cmicx->cmc0.schan_data); 813 cmicx_schan_update(pcid_info, &cmicx->cmc1.schan_data); 814 cmicx_schan_update(pcid_info, &cmicx->common.schan_data); 815 */ 816 817 /* update the state of each outstanding sbus dma unit */ 818 /* 819 cmicx_sbus_dma_update(pcid_info, &cmicx->cmc0.sbus_dma_ch0); 820 cmicx_sbus_dma_update(pcid_info, &cmicx->cmc0.sbus_dma_ch1); 821 cmicx_sbus_dma_update(pcid_info, &cmicx->cmc0.sbus_dma_ch2); 822 cmicx_sbus_dma_update(pcid_info, &cmicx->cmc1.sbus_dma_ch0); 823 cmicx_sbus_dma_update(pcid_info, &cmicx->cmc1.sbus_dma_ch1); 824 cmicx_sbus_dma_update(pcid_info, &cmicx->cmc1.sbus_dma_ch2); 825 */ 826 827 /* update the state of each scha fifo unit */ 828 829 /* update the state of each packet dma channel */ 830 /* 831 for (i=0; i<CMICX_NUM_PACKET_DMA_PER_CMC; i++) { 832 cmicx_packet_dma_update(pcid_info, &cmicx->cmc0.packet_dma[i]); 833 cmicx_packet_dma_update(pcid_info, &cmicx->cmc1.packet_dma[i]); 834 } 835 */ 836 837 838 /***********************************************************************************************************/ 839 /* new method: use WRR weightings in CMIC_TOP_SBUS_RING_ARB_CTRL_* registers to update Sbus master devices */ 840 /* a weighted number of times. update everything else that does not access the sbus once. */ 841 /***********************************************************************************************************/ 842 843 /* update all regular schan units based on their sbus arbiter weights. */ 844 for (i=0; i<CMICX_NUM_SCHAN_IN_COMMON; i++) { 845 846 /* make a number of updates based on the weight value of this schan unit */ 847 for (j=0; j<cmicx->sbus_ring_arb_ctrl_schan_common_ch_weight[i]; j++) { 848 if (cmicx_schan_update(pcid_info, &cmicx->common.schan[i])==false) { 849 cmicx_log("ERROR: failure to update schan \""); 850 cmicx_log(cmicx->common.schan[i].id_string); 851 cmicx_log("\".\n"); 852 return false; 853 } 854 } 855 856 } 857 858 /* update the single schan fifo unit based on its sbus arbiter weight */ 859 /* 860 for (i=0; i<cmicx->sbus_ring_arb_ctrl_schan_common_fifo_weight; i++) { 861 cmicx_schan_fifo_update(&cmicx->common.schan_fifo); 862 } 863 */ 864 865 /* update all sbus dma units a number of times, based on their sbus arbiter weights. a weight of zero means no update. */ 866 for (i=0; i<CMICX_NUM_SBUS_DMA_PER_CMC; i++) { 867 for (j=0; j<cmicx->sbus_ring_arb_ctrl_sbusdma_cmc0_ch_weight[i]; j++) { 868 if (cmicx_sbus_dma_update(pcid_info, &cmicx->cmc0.sbus_dma[i])==false) { 869 cmicx_log("ERROR: failure to update sbus dma \""); 870 cmicx_log(cmicx->cmc0.sbus_dma[i].id_string); 871 cmicx_log("\".\n"); 872 return false; 873 } 874 } 875 } 876 for (i=0; i<CMICX_NUM_SBUS_DMA_PER_CMC; i++) { 877 for (j=0; j<cmicx->sbus_ring_arb_ctrl_sbusdma_cmc1_ch_weight[i]; j++) { 878 if (cmicx_sbus_dma_update(pcid_info, &cmicx->cmc1.sbus_dma[i])==false) { 879 cmicx_log("ERROR: failure to update sbus dma \""); 880 cmicx_log(cmicx->cmc1.sbus_dma[i].id_string); 881 cmicx_log("\".\n"); 882 return false; 883 } 884 } 885 } 886 887 /* update the global packet dma, and the state of each packet dma channel once. */ 888 /* no weighting here, since there isn't an equivalent of sbus weighting for packet dma (only dma read and write weights (to do later?)). */ 889 cmicx_packet_dma_global_update(); 890 for (i=0; i<CMICX_NUM_PACKET_DMA_PER_CMC; i++) { 891 cmicx_packet_dma_update(pcid_info, &cmicx->cmc0.packet_dma[i]); 892 cmicx_packet_dma_update(pcid_info, &cmicx->cmc1.packet_dma[i]); 893 } 894 895 /* successful update complete */ 896 cmicx_log_level_set(0); 897 cmicx_log("CMICx successfully updated."); 898 cmicx_log_newline(); 899 cmicx_log("this cmicx update took: "); 900 cmicx_log_elapsed_time(); 901 cmicx_log_newline(); 902 cmicx_log_level_set(3); 903 return true; 904 905 } 906 907 908 /* for a pcid register read, check for the address and make the necessary call. as a simple optimization, we store the last accessed address index */ 909 /* and start looking from there, because that is most likely where we are going to access again (most recently used policy). */ 910 bool cmicx_pcid_register_read(addr_t addr,reg_t *reg) { 911 912 int i; 913 static int last_i = 0; /* note last_i here is static, so it persists between calls */ 914 bool past_last_i = false; 915 reg_t return_value; 916 917 for (i=last_i; (past_last_i==true)?(i!=last_i):(cmicx->last_pcid_register>=0); i=(i+1)%(cmicx->last_pcid_register+1)) { 918 past_last_i = true; 919 if (cmicx->pcid_addrs[i]==addr) { 920 last_i = i; 921 return_value = (cmicx->pcid_read_funcs[i])(reg); 922 cmicx_log_level_set(2); 923 cmicx_log("PCID register read at: "); 924 cmicx_log_uint64(addr); 925 cmicx_log(". value: "); 926 cmicx_log_reg(*reg); 927 cmicx_log("."); 928 cmicx_log_newline(); 929 cmicx_log_level_set(3); 930 return return_value; 931 } 932 } 933 934 cmicx_log("ERROR: could not read from cmicx pci register "); 935 cmicx_log_addr(addr); 936 cmicx_log(" - register does not exist.\n"); 937 /*cmicx_error("ERROR: read from invalid register. check log file.\n");*/ 938 return false; 939 } 940 941 942 /* for a pcid register write, check for the address and make the necessary call. as a simple optimization, we store the last accessed address index */ 943 /* and start looking from there, because that is most likely where we are going to access again (most recently used policy). */ 944 bool cmicx_pcid_register_write(addr_t addr,reg_t reg) { 945 946 int i; 947 static int last_i = 0; /* note last_i here is static, so it persists between calls */ 948 bool past_last_i = false; 949 reg_t return_value; 950 951 for (i=last_i; (past_last_i==true)?(i!=last_i):(cmicx->last_pcid_register>=0); i=(i+1)%(cmicx->last_pcid_register+1)) { 952 past_last_i = true; 953 if (cmicx->pcid_addrs[i]==addr) { 954 last_i = i; 955 return_value = (cmicx->pcid_write_funcs[i])(reg); 956 cmicx_log_level_set(2); 957 cmicx_log("PCID register write at: "); 958 cmicx_log_uint64(addr); 959 cmicx_log(". value: "); 960 cmicx_log_reg(reg); 961 cmicx_log("."); 962 cmicx_log_newline(); 963 cmicx_log_level_set(3); 964 return return_value; 965 } 966 } 967 968 cmicx_log("ERROR: could not write to cmicx pci register "); 969 cmicx_log_addr(addr); 970 cmicx_log(" - register does not exist.\n"); 971 /*cmicx_error("ERROR: write to invalid register. check log file.\n");*/ 972 return false; 973 } 974 975 976 /* function to add a pcid register to the list of available registers. this list maps a pcid address to a read and write function for that address */ 977 /* note this could be switched to a red-black tree or some other faster implementation */ 978 bool cmicx_pcid_register_add(addr_t addr,pcid_read_func_t *read_func,pcid_write_func_t *write_func) { 979 980 int i; 981 982 /* make sure the pcid register of the given address doesn't exist already */ 983 for (i=0; i<=cmicx->last_pcid_register; i++) { 984 if (cmicx->pcid_addrs[i]==addr) { 985 cmicx_log("ERROR: could not add pcid register with address "); 986 cmicx_log_addr(addr); 987 cmicx_log(" to array - already exists\n"); 988 return false; 989 } 990 } 991 992 /* add the register if there is room */ 993 if (cmicx->last_pcid_register!=(NUM_PCID_REGISTERS-1)) { 994 cmicx->last_pcid_register++; 995 #ifdef CMICX_STANDALONE_SIM 996 cmicx->pcid_addrs[cmicx->last_pcid_register] = addr; 997 #else 998 cmicx->pcid_addrs[cmicx->last_pcid_register] = (CMICX_SIM_PCI_BASE_ADDR | addr); /* if we are running this as part of the sdk, then we need to use the pci base address offset. */ 999 #endif 1000 cmicx->pcid_read_funcs[cmicx->last_pcid_register] = read_func; 1001 cmicx->pcid_write_funcs[cmicx->last_pcid_register] = write_func; 1002 return true; 1003 } 1004 else { 1005 cmicx_log("ERROR: could not add pcid register with address "); 1006 cmicx_log_addr(addr); 1007 cmicx_log(" to array - too many registers already (would exceed bounds of array\n"); 1008 return false; 1009 } 1010 1011 } 1012 1013 1014 /* sends an interrupt from the CMICx PCID sim to the SDK. */ 1015 bool cmicx_pcid_interrupt_send(pcid_info_t *pcid_info) { 1016 int rv; 1017 1018 rv = send_interrupt(pcid_info->client->intsock,0); 1019 if (rv < 0) { 1020 cmicx_log("soc_internal_send_int failed"); 1021 pcid_info->opt_rpc_error = 1; 1022 } else { 1023 cmicx_log("interrupt sent!"); 1024 } 1025 cmicx_log_newline(); 1026 return false; 1027 1028 } 1029 1030 1031 /* pcid memory read function. reads a chunk of memory from the internally stored cmicx memory data (simulated memory space). */ 1032 /* does not do anything special when the memory can't be found. */ 1033 bool cmicx_pcid_mem_read(pcid_info_t *pcid_info, addr_t addr,void *mem,int amount) { 1034 1035 #ifdef CMICX_STANDALONE_SIM 1036 1037 int i; 1038 int j; 1039 int last_j = 0; 1040 bool found = false; 1041 bool past_last_j = false; 1042 1043 /* debug */ 1044 cmicx_log_level_set(1); 1045 cmicx_log_newline(); 1046 cmicx_log("mem_read: reading "); 1047 cmicx_log_int(amount); 1048 cmicx_log(" bytes from memory location "); 1049 cmicx_log_uint64(addr); 1050 cmicx_log_newline(); 1051 cmicx_log_level_set(3); 1052 1053 /* standalone sim case: read each byte from the internal cmicx sim memory */ 1054 for (i=0; i<amount; i++) { 1055 1056 /* find our mem entry in the pcid_memory[] array. notice the (last_j) start value and stop value here. */ 1057 /* simple optimization, because our memory values will probably be in order of address internally (but it need not necessarily be that way) */ 1058 found = false; 1059 past_last_j = false; 1060 for (j=last_j; (past_last_j==true)?(j!=last_j):(cmicx->last_pcid_memory_address_index>=0); j=(j+1)%(cmicx->last_pcid_memory_address_index+1)) { 1061 past_last_j = true; 1062 if (cmicx->pcid_memory_addresses[j]==addr) { 1063 ((unsigned char *)mem)[i] = cmicx->pcid_memory[j]; 1064 found = true; 1065 last_j = j; 1066 break; 1067 } 1068 } 1069 1070 /* if we haven't found anything yet at this point, then this memory location does not exist in the array. we have an error trying to read it. */ 1071 if (found==false) { 1072 cmicx_log("ERROR: could not find memory entry at address "); 1073 cmicx_log_addr(addr); 1074 cmicx_log(" when reading memory\n"); 1075 return false; 1076 } 1077 else { 1078 addr += 1; 1079 } 1080 1081 } 1082 1083 #else 1084 1085 /* sdk case: we need to perform a dma read to get the host memory */ 1086 cmicx_log("dma: about to read "); 1087 cmicx_log_int(amount); 1088 cmicx_log(" bytes from addr "); 1089 cmicx_log_addr(addr); 1090 cmicx_log("..."); 1091 dma_read_bytes(pcid_info->client->dmasock,addr,(uint8 *)mem,amount); 1092 cmicx_log(" done."); 1093 cmicx_log_newline(); 1094 1095 #endif 1096 1097 return true; 1098 } 1099 1100 1101 /* pcid memory write function. writes a chunk of memory from the internally stored cmicx memory data (simulated memory space). */ 1102 /* when the memory is not already found, expands the known memory internally (still uses a statically allocated array for storage, though). */ 1103 bool cmicx_pcid_mem_write(pcid_info_t *pcid_info, addr_t addr,void *mem,int amount) { 1104 1105 #ifdef CMICX_STANDALONE_SIM 1106 int i; 1107 int j; 1108 int last_j = 0; 1109 bool found = false; 1110 bool past_last_j = false; 1111 1112 /* debug */ 1113 cmicx_log_level_set(1); 1114 cmicx_log_newline(); 1115 cmicx_log("mem_write: writing "); 1116 cmicx_log_int(amount); 1117 cmicx_log(" bytes to memory at location "); 1118 cmicx_log_uint64(addr); 1119 cmicx_log_newline(); 1120 cmicx_log_level_set(3); 1121 1122 /* standalone sim case: write each word to the internal cmicx sim memory */ 1123 for (i=0; i<amount; i++) { 1124 1125 /* search the memory array for this address. note the last_j start and stop point optimization. this is a simple */ 1126 /* optimization, since the memory values will probably be in order of address (but need not necessarily be that way). */ 1127 found = false; 1128 past_last_j = false; 1129 for (j=last_j; (past_last_j==true)?(j!=last_j):(cmicx->last_pcid_memory_address_index>=0); j=(j+1)%(cmicx->last_pcid_memory_address_index+1)) { 1130 past_last_j = true; 1131 if (cmicx->pcid_memory_addresses[j]==addr) { 1132 cmicx->pcid_memory[j] = ((unsigned char *)mem)[i]; 1133 found = true; 1134 last_j = j; 1135 break; 1136 } 1137 } 1138 1139 /* if we haven't found anything yet, then this memory location does not exist in the array. add it. */ 1140 if (found==false) { 1141 if (cmicx->last_pcid_memory_address_index!=(MAX_PCID_MEM_VALUES-1)) { 1142 cmicx->last_pcid_memory_address_index++; 1143 cmicx->pcid_memory_addresses[cmicx->last_pcid_memory_address_index] = addr; 1144 cmicx->pcid_memory[ cmicx->last_pcid_memory_address_index] = ((char *)mem)[i]; 1145 } 1146 else { 1147 cmicx_log("ERROR: no space in internal memory array when trying to add memory at address "); 1148 cmicx_log_addr(addr); 1149 cmicx_log("\n"); 1150 return false; 1151 } 1152 } 1153 1154 addr += 1; 1155 1156 } 1157 1158 #else 1159 1160 /* sdk case: we need to write to the host memory over pcid */ 1161 cmicx_log("dma: about to write "); 1162 cmicx_log_int(amount); 1163 cmicx_log(" bytes to addr "); 1164 cmicx_log_addr(addr); 1165 cmicx_log("..."); 1166 dma_write_bytes(pcid_info->client->dmasock,addr,(uint8 *)mem,amount); 1167 cmicx_log(" done."); 1168 cmicx_log_newline(); 1169 1170 #endif 1171 1172 return true; 1173 1174 } 1175 1176 /* will dump the internal pcid memory to the cmicx sim log (used for testing/debugging) */ 1177 void cmicx_pcid_mem_dump() { 1178 1179 int i; 1180 const int chain_limit = 4; 1181 int chain_count = 0; 1182 1183 cmicx_log_level_set(5); 1184 cmicx_log("CMICx sim local PCID memory cache dump (count "); 1185 cmicx_log_int(cmicx->last_pcid_memory_address_index+1); 1186 cmicx_log("):"); 1187 for (i=0; i<=cmicx->last_pcid_memory_address_index; i++) { 1188 1189 /* if the current address is just one more than the last address and we have not been chaining for too long, then we can chain this byte. */ 1190 if ((i>0) && (cmicx->pcid_memory_addresses[i]==(cmicx->pcid_memory_addresses[i-1]+1)) && (chain_count<chain_limit)) { 1191 cmicx_log(" "); 1192 cmicx_log_byte(cmicx->pcid_memory[i]); 1193 chain_count++; 1194 } 1195 1196 /* otherwise, we need to print the address and reset the chain count. */ 1197 else { 1198 cmicx_log("\n"); 1199 cmicx_log_uint64(cmicx->pcid_memory_addresses[i]); 1200 cmicx_log(": "); 1201 cmicx_log_byte(cmicx->pcid_memory[i]); 1202 chain_count = 1; 1203 } 1204 1205 } 1206 cmicx_log_newline(); 1207 cmicx_log_level_set(3); 1208 1209 } 1210 1211 1212 /* cmicx switch register read function. reads from a switch register. if it doesnt exist, create it first with the value 0xBEEF, and then return that value */ 1213 bool cmicx_switch_reg_read(addr_t addr,reg_t *val) { 1214 1215 int j; 1216 static int last_j = 0; /* note last_j here is static, so it persists between calls */ 1217 bool past_last_j = false; 1218 1219 /* find our register entry in the switch_register[] array. notice the static (last_j) start value and stop value here. */ 1220 /* simple optimization, because our register values will probably be in order of address internally (but it need not necessarily be that way) */ 1221 for (j=last_j; (past_last_j==true)?(j!=last_j):(cmicx->last_switch_register>=0); j=(j+1)%(cmicx->last_switch_register+1)) { 1222 past_last_j = true; 1223 if (cmicx->switch_register_addresses[j]==addr) { 1224 *val = cmicx->switch_registers[j]; 1225 last_j = j; 1226 return true; 1227 } 1228 } 1229 1230 /* if we haven't found anything yet at this point, then this switch register does not exist in the array. */ 1231 /* write the value 0 to the register, and then return that value */ 1232 if (cmicx->last_switch_register!=(CMICX_MAX_SWITCH_REGISTERS-1)) { 1233 cmicx->last_switch_register++; 1234 cmicx->switch_register_addresses[cmicx->last_switch_register] = addr; 1235 cmicx->switch_registers[ cmicx->last_switch_register] = 0; 1236 *val = cmicx->switch_registers[ cmicx->last_switch_register]; 1237 } 1238 else { 1239 cmicx_log("ERROR: no space in switch register array when trying to add register at address "); 1240 cmicx_log_addr(addr); 1241 cmicx_log(" during read\n"); 1242 return false; 1243 } 1244 1245 return true; 1246 } 1247 1248 1249 /* cmicx switch register write function. writes to a switch register. if it doesnt exist, create it first. */ 1250 bool cmicx_switch_reg_write(addr_t addr,reg_t val) { 1251 1252 int j; 1253 static int last_j = 0; /* note last_j here is static, so it persists between calls */ 1254 bool past_last_j = false; 1255 1256 /* search the switch register array for this address. note the last_j start and stop point optimization. this is a simple */ 1257 /* optimization, since the register values will probably be in order of address (but need not necessarily be that way). */ 1258 for (j=last_j; (past_last_j==true)?(j!=last_j):(cmicx->last_switch_register>=0); j=(j+1)%(cmicx->last_switch_register+1)) { 1259 past_last_j = true; 1260 if (cmicx->switch_register_addresses[j]==addr) { 1261 cmicx->switch_registers[j] = val; 1262 last_j = j; 1263 return true; 1264 } 1265 } 1266 1267 /* if we haven't found anything yet, then this register does not exist in the array. add it. */ 1268 if (cmicx->last_switch_register!=(CMICX_MAX_SWITCH_REGISTERS-1)) { 1269 cmicx->last_switch_register++; 1270 cmicx->switch_register_addresses[cmicx->last_switch_register] = addr; 1271 cmicx->switch_registers[ cmicx->last_switch_register] = val; 1272 } 1273 else { 1274 cmicx_log("ERROR: no space in switch register array when trying to add register at address "); 1275 cmicx_log_addr(addr); 1276 cmicx_log("\n"); 1277 return false; 1278 } 1279 1280 return true; 1281 } 1282 1283 /* will dump the internal cmicx switch registers to the cmicx sim log (used for testing/debugging) */ 1284 void cmicx_switch_registers_dump() { 1285 1286 int i; 1287 1288 cmicx_log_level_set(5); 1289 cmicx_log("CMICx sim switch register cache dump (count "); 1290 cmicx_log_int(cmicx->last_switch_register+1); 1291 cmicx_log("):\n"); 1292 for (i=0; i<=cmicx->last_switch_register; i++) { 1293 cmicx_log_addr(cmicx->switch_register_addresses[i]); 1294 cmicx_log(": "); 1295 cmicx_log_hex(cmicx->switch_registers[i]); 1296 if (i!=cmicx->last_switch_register) { 1297 cmicx_log("\n"); 1298 } 1299 } 1300 cmicx_log_newline(); 1301 cmicx_log_level_set(3); 1302 1303 } 1304 1305 1306 /* cmicx switch memory read function. reads from a switch memory value at a given address up to a certain number of words, */ 1307 /* if that memory value already exists/was allocated. if the memory value was already allocated but is of a smaller size, then */ 1308 /* only that many words are read. if the memory at this address does not exist yet, then it is created with the size of req, */ 1309 /* filled with 0xBEEF, and then returned. in all cases, req indicates the desired size of the memory (and the maximum number of */ 1310 /* words returnable), and resp indicates the number of words actually returned. thus, in all cases, resp<=req. */ 1311 bool cmicx_switch_mem_read(addr_t addr,reg_t *words,int req,int *resp) { 1312 1313 int j; 1314 static int last_j = 0; /* note last_j here is static, so it persists between calls */ 1315 bool past_last_j = false; 1316 1317 cmicx_log_level_set(-1); 1318 cmicx_log("reading mem block of size "); 1319 cmicx_log_int(req); 1320 cmicx_log(" at address "); 1321 cmicx_log_addr(addr); 1322 cmicx_log_newline(); 1323 cmicx_log_level_set(3); 1324 1325 /* find our memory in the switch_memories[] array. notice the static (last_j) start value and stop value here. */ 1326 /* simple optimization, because our memory values will probably be in order of address internally (but it need not necessarily be that way) */ 1327 for (j=last_j; (past_last_j==true)?(j!=last_j):(cmicx->last_switch_memory>=0); j=(j+1)%(cmicx->last_switch_memory+1)) { 1328 past_last_j = true; 1329 1330 /* we have found the memory. copy as much data as we can to the target and return. */ 1331 if (cmicx->switch_memory_addresses[j]==addr) { 1332 1333 /* the 0th element of the array holds the number of valid words in this memory. this statement determines if this or req is the limiting factor in copying data. */ 1334 if (cmicx->switch_memories[j][0]>=req) { 1335 *resp = req; 1336 } 1337 else { 1338 *resp = cmicx->switch_memories[j][0]; 1339 } 1340 memcpy((void *)words,(void *)&(cmicx->switch_memories[j][1]),(*resp)*sizeof(reg_t)); 1341 last_j = j; 1342 return true; 1343 } 1344 } 1345 1346 /* if we haven't found anything yet at this point, then this memory does not exist in the array. */ 1347 /* create the memory with the request size, fill it with 0, and then return this memory */ 1348 if (cmicx->last_switch_memory!=(CMICX_MAX_SWITCH_MEMORIES-1)) { 1349 cmicx->last_switch_memory++; 1350 cmicx->switch_memory_addresses[cmicx->last_switch_memory] = addr; 1351 cmicx->switch_memories[ cmicx->last_switch_memory] = (reg_t *)malloc(sizeof(reg_t)*(req+1)); /* allocate (req+1) words because we will store the number of words in position [0] (usage below) */ 1352 if (cmicx->switch_memories[ cmicx->last_switch_memory]==NULL) { 1353 cmicx_log("ERROR: no actual memory when trying to allocate memory for switch memory block during switch mem block read (switch mem addr="); 1354 cmicx_log_addr(addr); 1355 cmicx_log(")\n"); 1356 return false; 1357 } 1358 cmicx->switch_memories[ cmicx->last_switch_memory][0] = req; 1359 for (j=1; j<=req; j++) { 1360 cmicx->switch_memories[cmicx->last_switch_memory][j] = 0; 1361 } 1362 last_j = cmicx->last_switch_memory; 1363 *resp = cmicx->switch_memories[last_j][0]; 1364 memcpy((void *)words,(void *)&(cmicx->switch_memories[last_j][1]),(*resp)*sizeof(reg_t)); 1365 } 1366 else { 1367 cmicx_log("ERROR: no space in switch memory array when trying to add memory at address "); 1368 cmicx_log_addr(addr); 1369 cmicx_log(" during read\n"); 1370 return false; 1371 } 1372 1373 return true; 1374 1375 } 1376 1377 /* cmicx switch memory writing function. writes memory of a specified size to a switch memory address. if the memory already exists */ 1378 /* as a different size, the old memory is thrown away and overwritten with new memory of the new size. */ 1379 bool cmicx_switch_mem_write(addr_t addr,reg_t *words,int num) { 1380 1381 int j; 1382 static int last_j = 0; /* note last_j here is static, so it persists between calls */ 1383 bool past_last_j = false; 1384 bool memory_exists = false; 1385 bool need_new_memory_block = true; 1386 1387 cmicx_log_level_set(-1); 1388 cmicx_log("writing mem block of size "); 1389 cmicx_log_int(num); 1390 cmicx_log(" at address "); 1391 cmicx_log_addr(addr); 1392 cmicx_log_newline(); 1393 cmicx_log_level_set(3); 1394 1395 /* search the memory array for this address. note the last_j start and stop point optimization. this is a simple */ 1396 /* optimization, since the memory values will probably be in order of address (but need not necessarily be that way). */ 1397 for (j=last_j; (past_last_j==true)?(j!=last_j):(cmicx->last_switch_memory>=0); j=(j+1)%(cmicx->last_switch_memory+1)) { 1398 past_last_j = true; 1399 1400 /* if we have found the memory and it is already the right size, then mark that we don't need a new memory block created. if it is not the right size, then throw away the existing block, */ 1401 /* and allow one to be created later. in both cases we break out of the loop, and the last step of the function will copy the data to the memory block later. */ 1402 if (cmicx->switch_memory_addresses[j]==addr) { 1403 1404 if (cmicx->switch_memories[j][0]==num) { 1405 need_new_memory_block = false; 1406 } 1407 else { 1408 free(cmicx->switch_memories[j]); 1409 need_new_memory_block = true; 1410 } 1411 1412 last_j = j; 1413 memory_exists = true; 1414 break; 1415 } 1416 } 1417 1418 /* if we haven't found anything yet, then this memory does not exist in the array. add it. note that the next step in the function will take care of */ 1419 /* actually creating the memory block (because this functionality is shared with the loop above). */ 1420 if (memory_exists==false) { 1421 if (cmicx->last_switch_memory!=(CMICX_MAX_SWITCH_MEMORIES-1)) { 1422 cmicx->last_switch_memory++; 1423 cmicx->switch_memory_addresses[cmicx->last_switch_memory] = addr; 1424 last_j = cmicx->last_switch_memory; 1425 need_new_memory_block = true; 1426 } 1427 else { 1428 cmicx_log("ERROR: no space in switch memory array when trying to add memory at address "); 1429 cmicx_log_addr(addr); 1430 cmicx_log("\n"); 1431 return false; 1432 } 1433 } 1434 1435 /* create a new memory block if we need it. allocate (num+1) words because we will store the number of words in the mem block in position [0] (usage below) */ 1436 if (need_new_memory_block==true) { 1437 cmicx->switch_memories[last_j] = (reg_t *)malloc(sizeof(reg_t)*(num+1)); 1438 if (cmicx->switch_memories[last_j]==NULL) { 1439 cmicx_log("ERROR: no actual memory when trying to allocate memory for switch memory block during switch mem block write (switch mem addr="); 1440 cmicx_log_addr(addr); 1441 cmicx_log(")\n"); 1442 return false; 1443 } 1444 } 1445 1446 /* finally, copy the data memory data to the destination, and exit successfully */ 1447 cmicx->switch_memories[last_j][0] = num; 1448 memcpy((void *)&(cmicx->switch_memories[last_j][1]),(void *)words,num*sizeof(reg_t)); 1449 return true; 1450 1451 } 1452 1453 /* will dump the internal cmicx switch memories to the cmicx sim log (used for testing/debugging) */ 1454 void cmicx_switch_memories_dump() { 1455 1456 int i; 1457 int j; 1458 1459 cmicx_log_level_set(5); 1460 cmicx_log("CMICx sim switch memories dump (count "); 1461 cmicx_log_int(cmicx->last_switch_memory+1); 1462 cmicx_log("):\n"); 1463 for (i=0; i<=cmicx->last_switch_memory; i++) { 1464 cmicx_log_addr(cmicx->switch_memory_addresses[i]); 1465 cmicx_log(" (count "); 1466 cmicx_log_int(cmicx->switch_memories[i][0]); 1467 cmicx_log("):\n"); 1468 for (j=1; j<=cmicx->switch_memories[i][0]; j++) { 1469 cmicx_log_hex(cmicx->switch_memories[i][j]); 1470 if (!((i==cmicx->last_switch_memory) && (j==cmicx->switch_memories[i][0]))) { 1471 cmicx_log("\n"); 1472 } 1473 } 1474 } 1475 cmicx_log_newline(); 1476 cmicx_log_level_set(3); 1477 1478 } 1479 1480 1481 /* cmicx sim control reg read and write functions */ 1482 bool cmicx_sim_control_reg_read(reg_t *val) { 1483 *val = 0; 1484 return true; 1485 } 1486 bool cmicx_sim_control_reg_write(reg_t val) { 1487 1488 if (REG_BIT_GET(val,CMICX_SIM_CONTROL_REG_PCID_MEM_DUMP_BIT)==true) { 1489 cmicx_pcid_mem_dump(); 1490 } 1491 if (REG_BIT_GET(val,CMICX_SIM_CONTROL_REG_SWITCH_REGISTERS_DUMP_BIT)==true) { 1492 cmicx_switch_registers_dump(); 1493 } 1494 if (REG_BIT_GET(val,CMICX_SIM_CONTROL_REG_SWITCH_MEMORIES_DUMP_BIT)==true) { 1495 cmicx_switch_memories_dump(); 1496 } 1497 1498 if (REG_BIT_GET(val,CMICX_SIM_CONTROL_REG_LOG_LEVEL_CUTOFF_SET_BIT)==true) { 1499 cmicx_log_level_cutoff_set((int)REG_FIELD_GET(val,CMICX_SIM_CONTROL_REG_LOG_LEVEL_CUTOFF_MSB,CMICX_SIM_CONTROL_REG_LOG_LEVEL_CUTOFF_LSB)); 1500 } 1501 1502 return true; 1503 } 1504 1505