cmicsim.h (6571B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: cmicsim.h 8 * Purpose: 9 * Notes: 10 * REMEMBER REMEMBER REMEMBER REMEMBER REMEMBER 11 * 12 * SCHAN memory 0 to 0x4c is aliased to 0x800 on some chips. If you 13 * ever manually adjust one of those spaces, make sure to take care 14 * of the other. This is done currently in schan_op and in 15 * pli_setreg_service. 16 */ 17 18 #ifndef _CMICSIM_H_ 19 #define _CMICSIM_H_ 20 21 #include <soc/defs.h> 22 #include <sys/types.h> 23 24 #include "pcid.h" 25 #include "mem.h" 26 27 #define PCIM_SIZE_H(unit) \ 28 (soc_feature(unit, soc_feature_led_proc) ? 0x2000 : \ 29 soc_feature(unit, soc_feature_schmsg_alias) ? 0x900 : \ 30 0x200) 31 32 #define PCIM_SIZE(unit) \ 33 (SOC_CONTROL(unit) ? PCIM_SIZE_H(unit) : 0x2000) 34 35 #define PCIM_CMICM_SIZE 0x38000 36 37 #define PCIM_ALIAS_OFFSET 0x800 38 #define PCIM_ALIASED_BYTES 0x50 39 40 #define PCIM(pcid, addr) (pcid)->pcim[(addr) / 4] 41 42 #define PCIC(pcid, addr) (pcid)->pcic[(addr) / 4] 43 44 #define MF_ES_PIO 0 /* PIO endian swapping */ 45 #define MF_ES_DMA_PACKET 1 /* DMA packet endian swapping */ 46 #define MF_ES_DMA_OTHER 2 /* DMA other endian swapping */ 47 48 extern void soc_internal_pcic_init(pcid_info_t *pcid_info, 49 uint16 pci_dev_id, uint16 pci_ven_id, uint8 pci_rev_id, 50 uint32 pci_mbar0); 51 extern uint32 soc_internal_endian_swap(pcid_info_t *, uint32 data, int mode); 52 extern int soc_internal_write_reg(pcid_info_t * pcid_info, uint32 address, 53 uint32 * data); 54 extern int soc_internal_read_reg(pcid_info_t * pcid_info, uint32 address, 55 uint32 * data); 56 extern int soc_internal_write_mem(pcid_info_t * pcid_info, uint32 address, 57 uint32 * data); 58 extern int soc_internal_read_mem(pcid_info_t * pcid_info, uint32 address, 59 uint32 * data); 60 extern int soc_internal_read_aggrmem(pcid_info_t * pcid_info, uint32 addr, 61 uint32 * data); 62 extern int soc_internal_write_aggrmem(pcid_info_t * pcid_info, uint32 addr, 63 uint32 * data); 64 extern int soc_internal_read_bytes(pcid_info_t *pcid_info, uint32 address, 65 uint8 *data, int len); 66 extern int soc_internal_write_bytes(pcid_info_t *pcid_info, uint32 address, 67 uint8 *data, int len); 68 extern int soc_internal_vlan_tab_init(pcid_info_t *pcid_info); 69 extern void soc_internal_miim_op(pcid_info_t * pcid_info, int read); 70 extern void soc_internal_reset(pcid_info_t *pcid_info); 71 extern void soc_internal_memory_fetch(pcid_info_t * pcid_info, uint32 addr, 72 uint8 * buf, int length, int mode); 73 extern void soc_internal_memory_store(pcid_info_t * pcid_info, uint32 addr, 74 uint8 * buf, int length, int mode); 75 extern void soc_internal_bytes_fetch(pcid_info_t *pcid_info, uint32 addr, 76 uint8 *buf, int length); 77 extern void soc_internal_bytes_store(pcid_info_t *pcid_info, uint32 addr, 78 uint8 *buf, int length); 79 80 extern int soc_internal_vlan_tab_init(pcid_info_t *pcid_info); 81 extern void soc_internal_send_int(pcid_info_t *pcid_info); 82 extern void soc_internal_cmicm_send_int(pcid_info_t *pcid_info, uint32 reg); 83 extern void soc_internal_schan_ctrl_write(pcid_info_t *pcid_info, uint32 value); 84 extern void soc_internal_cmicm_schan_ctrl_write(pcid_info_t *pcid_info, uint32 reg, uint32 value); 85 extern void soc_internal_xgs3_table_dma(pcid_info_t *pcid_info); 86 extern void soc_internal_xgs3_cmicm_table_dma(pcid_info_t *pcid_info); 87 extern void soc_internal_xgs3_tslam_dma(pcid_info_t *pcid_info); 88 extern void soc_internal_xgs3_cmicm_tslam_dma(pcid_info_t *pcid_info); 89 extern void soc_internal_cmicm_sbusdma(pcid_info_t *pcid_info, uint32 reg); 90 91 92 extern int pcid_add_pkt(pcid_info_t *pcid_info, uint8 *pkt_data, 93 int pkt_len, uint32 *dcbd); 94 95 96 extern int soc_internal_extended_write_reg(pcid_info_t *pcid_info, 97 soc_block_t block, int acc_type, 98 uint32 address, uint32 *data); 99 extern int soc_internal_extended_read_reg(pcid_info_t *pcid_info, 100 soc_block_t block, int acc_type, 101 uint32 address, uint32 *data); 102 extern int soc_internal_extended_write_mem(pcid_info_t *pcid_info, 103 soc_block_t block, int acc_type, 104 uint32 address, uint32 *data); 105 extern int soc_internal_extended_read_mem(pcid_info_t *pcid_info, 106 soc_block_t block, int acc_type, 107 uint32 address, uint32 *data); 108 extern int soc_internal_extended_write_aggrmem(pcid_info_t *pcid_info, 109 soc_block_t block, 110 int acc_type, 111 uint32 address, uint32 *data); 112 extern int soc_internal_extended_read_aggrmem(pcid_info_t *pcid_info, 113 soc_block_t block, 114 int acc_type, 115 uint32 address, uint32 *data); 116 extern int soc_internal_extended_write_bytes(pcid_info_t *pcid_info, 117 soc_block_t block, int acc_type, 118 uint32 address, 119 uint8 *data, int len); 120 extern int soc_internal_extended_read_bytes(pcid_info_t *pcid_info, 121 soc_block_t block, int acc_type, 122 uint32 address, 123 uint8 *data, int len); 124 extern int soc_internal_extended_write_mem_index(pcid_info_t *pcid_info, 125 soc_mem_t mem, int index, 126 uint32 *data); 127 extern int soc_internal_extended_read_mem_index(pcid_info_t *pcid_info, 128 soc_mem_t mem, int index, 129 uint32 *data); 130 #endif /* _CMICSIM_H_ */