linux-kernel-bde.c (147475B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Linux Kernel BDE 8 */ 9 10 #include <gmodule.h> 11 #include <linux-bde.h> 12 #include <linux_dma.h> 13 #include <mpool.h> 14 #include <linux/delay.h> 15 #include <linux/types.h> 16 #include <sdk_config.h> 17 #include <soc/devids.h> 18 #include <soc/cmic.h> 19 #include <soc/drv.h> 20 #include <linux/version.h> 21 22 #include "linux_shbde.h" 23 24 25 #ifdef __GNUC__ 26 #if __GNUC__ == 8 27 /* 28 * Prevent gcc 8.1.10 using a compiler inline memcpy even if using -fno-builtin or 29 * -fno-builtin-memcpy . 30 * __inline_memcpy and __memcpy are kernel functions that may be used instead, 31 * for either an inline or non-inline implementations of the function 32 */ 33 #define MEMCPY __inline_memcpy 34 #else 35 #define MEMCPY memcpy 36 #endif /* __GNUC__ == 8 */ 37 #else /* ifdef __GNUC__ */ 38 #define MEMCPY memcpy 39 #endif /* ifdef __GNUC__ */ 40 41 #define PCI_USE_INT_NONE (-1) 42 #define PCI_USE_INT_INTX (0) 43 #define PCI_USE_INT_MSI (1) 44 #define PCI_USE_INT_MSIX (2) 45 #ifdef CONFIG_PCI_MSI 46 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,110)) 47 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 48 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) 49 #endif 50 #define msi_control_reg(base) (base + PCI_MSI_FLAGS) 51 #endif 52 #endif 53 MODULE_AUTHOR("Broadcom Corporation"); 54 MODULE_DESCRIPTION("Kernel BDE"); 55 MODULE_LICENSE("Proprietary"); 56 57 /* PCIe max payload */ 58 int maxpayload = 256; 59 LKM_MOD_PARAM(maxpayload, "i", int, 0); 60 MODULE_PARM_DESC(maxpayload, 61 "Limit maximum payload size and request size on PCIe devices"); 62 63 /* Use MSI or MSIX interrupts */ 64 int usemsi = -1; 65 LKM_MOD_PARAM(usemsi, "i", int, 0); 66 MODULE_PARM_DESC(usemsi, 67 "Use MSI/ MSIX interrupts if supported by kernel"); 68 69 /* Ignore all recognized devices (for debug purposes) */ 70 int nodevices; 71 LKM_MOD_PARAM(nodevices, "i", int, 0); 72 MODULE_PARM_DESC(nodevices, 73 "Ignore all recognized devices (default no)"); 74 75 int msixcnt = 1; 76 77 /* 78 * This usually is defined at /usr/include/linux/pci_ids.h 79 * But this ID is newer. 80 */ 81 #ifndef PCI_DEVICE_ID_PLX_9656 82 #define PCI_DEVICE_ID_PLX_9656 0x9656 83 #endif 84 85 #ifndef PCI_DEVICE_ID_PLX_9056 86 #define PCI_DEVICE_ID_PLX_9056 0x9056 87 #endif 88 89 /* For 2.4.x kernel support */ 90 #ifndef IRQF_SHARED 91 #define IRQF_SHARED SA_SHIRQ 92 #endif 93 94 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) 95 typedef unsigned long resource_size_t; 96 #endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) */ 97 98 #ifdef BCM_ICS 99 #define BCM_ICS_CMIC_BASE 0x08000000 100 #else 101 102 /* Force interrupt line */ 103 static int forceirq = -1; 104 static uint32_t forceirqubm = 0xffffffff; 105 LKM_MOD_PARAM(forceirq, "i", int, 0); 106 LKM_MOD_PARAM(forceirqubm, "i", uint, 0); 107 MODULE_PARM_DESC(forceirq, 108 "Override IRQ line assigned by boot loader"); 109 MODULE_PARM_DESC(forceirqubm, 110 "Bitmap for overriding the IRQ line assigned by boot loader for given units"); 111 112 /* Create SPI slave device (cannot be probed) */ 113 static uint32_t spi_devid = 0; 114 LKM_MOD_PARAM(spi_devid, "i", uint, 0); 115 MODULE_PARM_DESC(spi_devid, 116 "Create SPI slave device using this device ID"); 117 118 /* Select SPI device revision (cannot be probed) */ 119 static uint32_t spi_revid = 1; 120 LKM_MOD_PARAM(spi_revid, "i", uint, 0); 121 MODULE_PARM_DESC(spi_revid, 122 "Select device revision for SPI slave device"); 123 124 #endif /* BCM_ICS */ 125 126 /* Debug output */ 127 static int debug; 128 LKM_MOD_PARAM(debug, "i", int, 0); 129 MODULE_PARM_DESC(debug, 130 "Set debug level (default 0"); 131 /* Use high memory for DMA */ 132 133 /* module param for probing EB devices. */ 134 static char *eb_bus; 135 LKM_MOD_PARAM(eb_bus, "s", charp, 0); 136 MODULE_PARM_DESC(eb_bus, 137 "List of EB devices on platform. Input format (BA=%x IRQ=%d RD16=%d WR16=%d"); 138 139 #ifdef KEYSTONE 140 /* Force SPI Frequency */ 141 static int spifreq = 0; 142 LKM_MOD_PARAM(spifreq, "i", int, 0); 143 MODULE_PARM_DESC(spifreq, 144 "Force SPI Frequency for Keystone CPU (0 for default frequency)"); 145 #endif 146 147 148 /* Compatibility */ 149 #ifdef LKM_2_4 150 #define _ISR_RET void 151 #define _ISR_PARAMS(_i,_d,_r) int _i, void *_d, struct pt_regs *_r 152 #define IRQ_NONE 153 #define IRQ_HANDLED 154 #define SYNC_IRQ(_i) synchronize_irq() 155 #else /* LKM_2_6 */ 156 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) 157 #define _ISR_RET irqreturn_t 158 #else 159 #define _ISR_RET int 160 #endif 161 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) 162 #define _ISR_PARAMS(_i,_d,_r) int _i, void *_d 163 #else 164 #define _ISR_PARAMS(_i,_d,_r) int _i, void *_d, struct pt_regs *_r 165 typedef irqreturn_t (*irq_handler_t)(int _i, void *_d, struct pt_regs *_r); 166 #endif 167 #define SYNC_IRQ(_i) synchronize_irq(_i) 168 char * ___strtok; 169 char * strtok(char * s,const char * ct) 170 { 171 char *sbegin, *send; 172 sbegin = s ? s : ___strtok; 173 if (!sbegin) { 174 return NULL; 175 } 176 sbegin += strspn(sbegin,ct); 177 if (*sbegin == '\0') { 178 ___strtok = NULL; 179 return( NULL ); 180 } 181 send = strpbrk( sbegin, ct); 182 if (send && *send != '\0') 183 *send++ = '\0'; 184 ___strtok = send; 185 return (sbegin); 186 } 187 LKM_EXPORT_SYM(___strtok); 188 LKM_EXPORT_SYM(strtok); 189 #endif /* LKM_2_x */ 190 191 /* PCIe capabilities */ 192 #ifndef PCI_CAP_ID_EXP 193 #define PCI_CAP_ID_EXP 0x10 194 #endif 195 #ifndef PCI_EXP_DEVCAP 196 #define PCI_EXP_DEVCAP 4 197 #endif 198 #ifndef PCI_EXP_DEVCTL 199 #define PCI_EXP_DEVCTL 8 200 #endif 201 #ifndef PCI_EXT_CAP_START 202 #define PCI_EXT_CAP_START 0x100 203 #endif 204 #ifndef PCI_EXT_CAP_ID 205 #define PCI_EXT_CAP_ID(_hdr) (_hdr & 0x0000ffff) 206 #endif 207 #ifndef PCI_EXT_CAP_VER 208 #define PCI_EXT_CAP_VER(_hdr) ((_hdr >> 16) & 0xf) 209 #endif 210 #ifndef PCI_EXT_CAP_NEXT 211 #define PCI_EXT_CAP_NEXT(_hdr) ((_hdr >> 20) & 0xffc) 212 #endif 213 #ifndef PCI_EXT_CAP_ID_VNDR 214 #define PCI_EXT_CAP_ID_VNDR 0x0b 215 #endif 216 217 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 218 #define PCI_FIND_DEV(_d, _v, _fr) pci_find_device(_d, _v, _fr) 219 #else 220 #define PCI_FIND_DEV(_d, _v, _fr) pci_get_device(_d, _v, _fr) 221 #endif 222 223 #if defined(CONFIG_RESOURCES_64BIT) || defined(CONFIG_PHYS_ADDR_T_64BIT) 224 #define PHYS_ADDR_IS_64BIT 225 #endif 226 227 /* Structure of private SPI device */ 228 struct spi_dev { 229 uint8 cid; /* Chip ID */ 230 uint32 part; /* Part number of the chip */ 231 uint8 rev; /* Revision of the chip */ 232 void *robo; /* ptr to robo info required to access SPI */ 233 unsigned short phyid_high; /* PHYID HIGH in MII regs of detected chip */ 234 unsigned short phyid_low; /* PHYID LOW in MII regs of detected chip */ 235 }; 236 237 struct bde_spi_device_id { 238 unsigned short phyid_high; /* PHYID HIGH in MII regs of detected chip */ 239 unsigned short phyid_low; /* PHYID LOW in MII regs of detected chip */ 240 uint32 model_info; 241 uint32 rev_info; 242 uint32 spifreq; 243 }; 244 245 /* Control Data */ 246 typedef struct bde_ctrl_s { 247 struct list_head list; 248 249 /* Specify the type of device, pci, spi, switch, ether ... */ 250 uint32 dev_type; 251 252 int domain_no; 253 int bus_no; 254 int be_pio; 255 int use_msi; 256 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 257 struct msix_entry *entries; 258 #endif 259 int msix_cnt; 260 union { 261 /* Linux PCI device pointer */ 262 struct pci_dev* _pci_dev; 263 264 /* SPI device pointer */ 265 struct spi_dev* _spi_dev; 266 } dev; 267 #define pci_device dev._pci_dev 268 #define spi_device dev._spi_dev 269 270 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 271 struct device *dma_dev; 272 #endif 273 274 /* Physical addresses */ 275 resource_size_t phys_address; 276 resource_size_t phys_address1; 277 resource_size_t phys_address2; 278 279 /* Secondary mapped base address */ 280 sal_vaddr_t alt_base_addr; 281 282 /* BDE device description */ 283 ibde_dev_t bde_dev; 284 285 /* Interrupt Handling */ 286 int iLine; /* Interrupt line */ 287 void (*isr)(void *); 288 void *isr_data; 289 290 /* 291 * Controls to allow two drivers to share a single set of 292 * hardware registers. Typically a kernel driver will handle 293 * a subset of hardware interrupts and a user mode driver 294 * will handle the remaining interrupts. 295 */ 296 void (*isr2)(void *); 297 void *isr2_data; 298 uint32_t fmask; /* Interrupts controlled by secondary handler */ 299 uint32_t imask; /* Enabled interrupts for primary handler */ 300 uint32_t imask2; /* Enabled interrupts for secondary handler */ 301 spinlock_t lock; /* Lock for IRQ mask synchronization */ 302 303 /* Hardware abstraction for shared BDE functions */ 304 shbde_hal_t shbde; 305 306 /* Device state : BDE_DEV_STATE_REMOVED/CHANGED */ 307 uint32 dev_state; 308 309 /* inst_id */ 310 uint32 inst_id; 311 } bde_ctrl_t; 312 313 static bde_ctrl_t _devices[LINUX_BDE_MAX_DEVICES]; 314 static int _ndevices = 0; 315 static int _switch_ndevices = 0; 316 static int _ether_ndevices = 0; 317 static int _cpu_ndevices = 0; 318 319 #define VALID_DEVICE(_n) ((_n >= 0) && (_n < _ndevices)) 320 321 #if defined(IPROC_CMICD) && defined(CONFIG_OF) 322 #define ICFG_CHIP_ID_REG 0x10236000 323 #define IHOST_CMICX_MAX_INTRS 128 324 static uint32 iproc_cmicx_irqs[IHOST_CMICX_MAX_INTRS]; 325 #endif 326 327 /* CPU MMIO area used with CPU cards provided on demo boards */ 328 #if defined(BCM_SAND_SUPPORT) && (defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__)) 329 static void *cpu_address = NULL; 330 #endif 331 332 333 /* Broadcom BCM4704 */ 334 #define BCM4704_VENDOR_ID 0x14E4 335 #define BCM4704_DEVICE_ID 0x4704 336 337 /* SiByte PCI Host */ 338 #define SIBYTE_PCI_VENDOR_ID 0x166D 339 #define SIBYTE_PCI_DEVICE_ID 0x0001 340 341 /* Intel 21150 PCI-PCI Bridge */ 342 #define DC21150_VENDOR_ID 0x1011 343 #define DC21150_DEVICE_ID 0x0022 344 345 /* HiNT HB4 PCI-PCI Bridge (21150 clone) */ 346 #define HINT_HB4_VENDOR_ID 0x3388 347 #define HINT_HB4_DEVICE_ID 0x0022 348 349 /* Pericom PI7C8150 PCI-PCI Bridge (21150 clone) */ 350 #define PI7C8150_VENDOR_ID 0x12D8 351 #define PI7C8150_DEVICE_ID 0x8150 352 353 /* Pericom PI7C9X130 PCI-PCIE Bridge */ 354 #define PCI_VNDID_PERICOM 0x12D8 355 #define PCI_DEVID_PI7C9X130 0xE130 356 #define DEV_CTRL_REG 0xb8 357 358 #define MAX_PAYLOAD_256B (1 << 5) 359 #define MAX_PAYLOAD_512B (2 << 5) 360 #define MAX_READ_REQ_256B (1 << 12) 361 362 363 /* Freescale 8548 PCI-E host Bridge */ 364 #define FSL_VENDOR_ID 0x1957 365 #define FSL8548PCIE_DEVICE_ID 0x0013 366 #define FSL2020EPCIE_DEVICE_ID 0x0070 367 #define FSL8548PCIE_DEV_CTRL_REG 0x54 368 369 /* 4716 PCI-E host Bridge */ 370 #define BCM4716_VENDOR_ID 0x14e4 371 #define BCM4716PCIE_DEVICE_ID 0x4716 372 #define BCM4716PCIE_DEV_CAP_REG 0xd4 373 #define BCM4716PCIE_DEV_CTRL_REG 0xd8 374 #define BCM53000_VENDOR_ID 0x14e4 375 #define BCM53000PCIE_DEVICE_ID 0x5300 376 377 #define BCM53000PCIE_DEV(port) ((port == 0) ? pcie0 : pcie1) 378 #define BCM53000PCIE_BASE(port) ((port == 0) ? 0xb8005000 : 0xb800e000) 379 #define BCM53000PCIE_FUNC0_COFIG_SPACE 0x400 380 #define BCM53000PCIE_SROM_SPACE 0x800 381 #define BCM53000PCIE_DEV_CAP_REG 0xd4 382 #define BCM53000PCIE_DEV_CTRL_REG 0xd8 383 #define BCM53000PCIE_MAX_PAYLOAD_MASK 0x7 384 #define BCM53000PCIE_CAP_MAX_PAYLOAD_256B (1 << 0) 385 #define BCM53000PCIE_DEFAULT_STATUS 0x00100146 386 387 /* 16bit wide register. offset 14, 14*2 = 0x1c */ 388 #define BCM53000PCIE_SPROM_OFFSET 0x1c 389 /* bit 15:13 spromData.MaxPayloadSize. 1: 256 bytes */ 390 #define BCM53000PCIE_SPROM_MAX_PAYLOAD_MASK 0xe000 391 #define BCM53000PCIE_SPROM_MAX_PAYLOAD_256B (1 << 13) 392 393 394 /* Intel 21150, HiNT HB4 and other 21150-compatible */ 395 #define PCI_CFG_DEC21150_SEC_CLK 0x68 396 397 #define BCM4704_ENUM_BASE 0x18000000 398 #define BCM4704_MEMC_BASE (BCM4704_ENUM_BASE+0x8000) 399 #define BCM4704_MEMC_PRIORINV 0x18 400 401 /* PLX PCI-E Switch */ 402 #define PLX_PEX8608_DEV_ID 0x8608 403 #define PLX_PEX8617_DEV_ID 0x8617 404 #define PLX_PEX86XX_DEV_CTRL_REG 0x70 405 406 /* Broadcom BCM58525 */ 407 #define BCM58525_PCI_VENDOR_ID 0x14E4 408 #define BCM58525_PCI_DEVICE_ID 0x8025 409 #define BCM58522_PCI_DEVICE_ID 0x8022 410 411 /* Broadcom BCM58712 */ 412 #define BCM58712_PCI_VENDOR_ID 0x14E4 413 #define BCM58712_PCI_DEVICE_ID 0x168E 414 415 /* Default gicd address if not available in DTB */ 416 #define IHOST_GICD_REG_ADDR 0x10781100 417 #define IHOST_GICD_REG_REMAP_LEN 0x100 418 419 #define IHOST_GICD_REG_ADDR_VALID(d, addr) \ 420 (_devices[d].bde_dev.base_address1 && \ 421 (addr & 0xFFFFFF00) == _devices[d].phys_address1) 422 423 #define IHOST_GICD_REG_ADDR_REMAP(d, addr) \ 424 (void *)(_devices[d].bde_dev.base_address1 + (addr - _devices[d].phys_address1)) 425 426 static uint32_t _read(int d, uint32_t addr); 427 428 #ifdef BCM_ICS 429 #else 430 /* Used to determine overall memory limits across all devices */ 431 static uint32_t _pci_mem_start = 0xFFFFFFFF; 432 static uint32_t _pci_mem_end = 0; 433 434 /* Used to control MSI interrupts */ 435 static int use_msi = 0; 436 #endif 437 438 #ifdef BCM_PLX9656_LOCAL_BUS 439 440 #define CPLD_OFFSET 0x00800000 441 #define CPLD_REVISION_REG 0x0000 442 #define CPLD_REVISION_MASK 0xffff 443 #define CPLD_RESET_REG 0x0004 444 #define CPLD_RESET_NONE 0x0000 445 446 #define PL0_OFFSET 0x00800000 447 #define PL0_SIZE 0x00040000 448 #define PL0_REVISION_REG 0x0000 449 450 /* Assume there's only one PLX PCI-to-Local bus bridge if any */ 451 static bde_ctrl_t plx_ctrl; 452 static int num_plx = 0; 453 454 #endif /* BCM_PLX9656_LOCAL_BUS */ 455 456 static spinlock_t bus_lock; 457 458 static int 459 _parse_eb_args(char *str, char * format, ...) 460 __attribute__ ((format (scanf, 2, 3))); 461 462 static int 463 _parse_eb_args(char *str, char * format, ...) 464 { 465 va_list args; 466 467 va_start(args, format); 468 vsscanf(str, format, args); 469 va_end(args); 470 471 return 0; 472 } 473 474 static void 475 _bde_add_device(void) 476 { 477 int add_switch_device = 0; 478 if (_devices[_ndevices].dev_type & BDE_SWITCH_DEV_TYPE) { 479 _switch_ndevices++; 480 add_switch_device = 1; 481 } else if (_devices[_ndevices].dev_type & BDE_ETHER_DEV_TYPE) { 482 _ether_ndevices++; 483 } else if (_devices[_ndevices].dev_type & BDE_CPU_DEV_TYPE) { 484 _cpu_ndevices++; 485 } else { 486 return; 487 } 488 _ndevices++; 489 490 /* 491 * In order to be backward compatible with the user mode BDE 492 * (specifically the interrupt IOCTLs) and the CM, switch devices 493 * *must* come first. If this is not the case (due to the probing 494 * order), we let the non-switch device(s) drop down to the end of 495 * the device array. 496 */ 497 if (add_switch_device) { 498 bde_ctrl_t tmp_dev; 499 int i, s = 0; 500 501 while (s < _switch_ndevices) { 502 if (_devices[s].dev_type & BDE_SWITCH_DEV_TYPE) { 503 s++; 504 continue; 505 } 506 tmp_dev = _devices[s]; 507 for (i = s; i < _ndevices - 1; i++) { 508 _devices[i] = _devices[i+1]; 509 } 510 _devices[i] = tmp_dev; 511 } 512 513 _dma_init(_switch_ndevices-1); 514 } 515 516 /* Initialize device locks */ 517 spin_lock_init(&_devices[_ndevices-1].lock); 518 } 519 520 static int 521 _eb_device_create(resource_size_t paddr, int irq, int rd_hw, int wr_hw) 522 { 523 bde_ctrl_t *ctrl; 524 uint32 dev_rev_id = 0x0, dev_id; 525 526 dev_id = _ndevices; 527 528 ctrl = _devices + _ndevices; 529 530 ctrl->dev_type |= BDE_EB_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 531 ctrl->pci_device = NULL; /* No PCI bus */ 532 533 if(rd_hw) { 534 ctrl->dev_type |= BDE_DEV_BUS_RD_16BIT; 535 } 536 537 if (wr_hw) { 538 ctrl->dev_type |= BDE_DEV_BUS_WR_16BIT; 539 } 540 541 /* Map in the device */ 542 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(paddr, 0x10000); 543 ctrl->phys_address = paddr; 544 545 dev_rev_id = _read(dev_id, 0x178); /* CMIC_DEV_REV_ID */ 546 547 ctrl->bde_dev.device = dev_rev_id & 0xFFFF; 548 ctrl->bde_dev.rev = (dev_rev_id >> 16) & 0xFF; 549 550 ctrl->iLine = irq; 551 ctrl->isr = NULL; 552 ctrl->isr_data = NULL; 553 554 gprintk("Created EB device at BA=%x IRQ=%d RD16=%d WR16=%d device=0x%x\n", 555 (unsigned int)paddr, irq, rd_hw, wr_hw, ctrl->bde_dev.device); 556 557 _bde_add_device(); 558 559 return 0; 560 } 561 562 #ifdef BCM_SAND_SUPPORT 563 564 #include <soc/devids.h> 565 566 static int 567 sand_device_create(void) 568 { 569 bde_ctrl_t* ctrl; 570 571 ctrl = _devices; 572 573 #ifndef __DUNE_LINUX_BCM_CPU_PCIE__ 574 ctrl->dev_type |= BDE_PCI_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 575 ctrl->pci_device = NULL; /* No PCI bus */ 576 577 /* Map in the device */ 578 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(0x40000000, 0x100000); 579 ctrl->phys_address = 0x40000000; 580 581 ctrl->iLine = 0; 582 ctrl->isr = NULL; 583 ctrl->isr_data = NULL; 584 585 ctrl->bde_dev.device = BCM88950_DEVICE_ID; 586 ctrl->bde_dev.rev = BCM88950_A0_REV_ID; 587 #endif 588 589 /* Map CPU regs */ 590 #ifdef __DUNE_WRX_BCM_CPU__ 591 cpu_address = IOREMAP(0x18000000, 0x4000000); 592 #elif defined(__DUNE_GTO_BCM_CPU__) 593 cpu_address = IOREMAP(0xe0000000, 0x100000); 594 #endif 595 596 if ((ctrl->bde_dev.device == PCP_PCI_DEVICE_ID)) { 597 ctrl->bde_dev.device = GEDI_DEVICE_ID; 598 ctrl->bde_dev.rev = GEDI_REV_ID; 599 } 600 601 if ((ctrl->bde_dev.device == ACP_PCI_DEVICE_ID)) { 602 ctrl->dev_type |= BDE_PCI_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 603 } 604 605 #ifndef __DUNE_LINUX_BCM_CPU_PCIE__ 606 _bde_add_device(); 607 #endif 608 609 return 0; 610 } 611 #endif /* BCM_SAND_SUPPORT */ 612 613 #ifdef IPROC_CMICD 614 static void 615 iproc_cmicd_get_irqres(ibde_dev_t bde_dev, struct resource *res_irq) 616 { 617 shbde_iproc_config_t iproc_config, *icfg = &iproc_config; 618 619 /* iProc configuration parameters */ 620 memset(icfg, 0, sizeof(*icfg)); 621 shbde_iproc_config_init(icfg, bde_dev.device, bde_dev.rev); 622 623 if ((icfg->iproc_ver == 0) && (debug >= 1)) { 624 gprintk("Unable to determine iProc version\n"); 625 } 626 627 if (icfg->iproc_ver == 7) { 628 res_irq->start = 221; 629 } else if (icfg->iproc_ver == 10) { 630 res_irq->start = 184; 631 } 632 633 } 634 635 #include <linux/platform_device.h> 636 #include <linux/of.h> 637 638 extern int iproc_platform_driver_register(struct platform_driver *drv); 639 extern void iproc_platform_driver_unregister(struct platform_driver *drv); 640 extern int iproc_platform_device_register(struct platform_device *drv); 641 extern void iproc_platform_device_unregister(struct platform_device *drv); 642 643 extern struct resource * 644 iproc_platform_get_resource(struct platform_device *dev, unsigned int type, 645 unsigned int num); 646 647 #define IPROC_CHIPCOMMONA_BASE 0x18000000 648 #define IPROC_CMICD_BASE 0x48000000 649 #define IPROC_CMICD_SIZE 0x40000 650 #define IPROC_CMICD_INT 194 651 652 #define IPROC_CMICD_COMPATIBLE "brcm,iproc-cmicd" 653 #define IPROC_CMICX_COMPATIBLE "brcm,iproc-cmicx" 654 655 static int 656 iproc_cmicd_probe(struct platform_device *pldev) 657 { 658 bde_ctrl_t *ctrl; 659 uint32 size, dev_rev_id; 660 struct resource *memres, *irqres; 661 #ifdef CONFIG_OF 662 if (debug >= 1) { 663 gprintk("iproc_cmicd_probe %s\n", pldev->dev.of_node ? "with device node":""); 664 } 665 #endif 666 memres = iproc_platform_get_resource(pldev, IORESOURCE_MEM, 0); 667 if (memres == NULL) { 668 gprintk("Unable to retrieve iProc CMIC resources"); 669 return -1; 670 } 671 size = memres->end - memres->start + 1; 672 673 ctrl = _devices + _ndevices; 674 675 ctrl->dev_type = BDE_AXI_DEV_TYPE | BDE_SWITCH_DEV_TYPE | BDE_256K_REG_SPACE; 676 ctrl->pci_device = NULL; /* No PCI bus */ 677 678 /* Map CMIC block in the AXI memory space into CPU address space */ 679 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(memres->start, size); 680 if (!ctrl->bde_dev.base_address) { 681 gprintk("Error mapping iProc CMIC registers"); 682 return -1; 683 } 684 ctrl->phys_address = memres->start; 685 686 #ifdef CONFIG_OF 687 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 688 uint32 *icfg_chip_id; 689 icfg_chip_id = (uint32 *)IOREMAP(ICFG_CHIP_ID_REG, 2 * sizeof(uint32)); 690 if (icfg_chip_id == NULL) { 691 gprintk("Error mapping ICFG_CHIP_ID_REG\n"); 692 return -1; 693 } 694 ctrl->bde_dev.device = readl(icfg_chip_id) & 0xffff; 695 ctrl->bde_dev.rev = readl(icfg_chip_id+1) & 0xff; 696 iounmap(icfg_chip_id); 697 /* Map GICD block in the AXI memory space into CPU address space */ 698 memres = iproc_platform_get_resource(pldev, IORESOURCE_MEM, 1); 699 if (memres) { 700 ctrl->bde_dev.base_address1 = (sal_vaddr_t)IOREMAP(memres->start, memres->end - memres->start + 1); 701 ctrl->phys_address1 = memres->start; 702 } else { 703 /* Use default address if not available in DTB */ 704 ctrl->bde_dev.base_address1 = (sal_vaddr_t)IOREMAP(IHOST_GICD_REG_ADDR, IHOST_GICD_REG_REMAP_LEN); 705 ctrl->phys_address1 = IHOST_GICD_REG_ADDR; 706 } 707 if (ctrl->bde_dev.base_address1) { 708 if (debug >= 1) { 709 gprintk("base_address1:0x%lx phys_address1:0x%lx\n", 710 (unsigned long)ctrl->bde_dev.base_address1, (unsigned long)ctrl->phys_address1); 711 } 712 } else { 713 gprintk("Error mapping ihost GICD registers\n"); 714 } 715 } else 716 #endif 717 { 718 /* Read switch device ID from CMIC */ 719 dev_rev_id = *((uint32 *)(ctrl->bde_dev.base_address + 0x10224)); 720 #if defined(BCM_CMICM_SUPPORT) && defined(BE_HOST) 721 ctrl->bde_dev.device = ( (((dev_rev_id >> 16) & 0xff) << 8) | 722 ((dev_rev_id >> 24) & 0xff)); 723 ctrl->bde_dev.rev = (dev_rev_id >> 8) & 0xff ; 724 #else 725 ctrl->bde_dev.device = dev_rev_id & 0xffff; 726 ctrl->bde_dev.rev = (dev_rev_id >> 16) & 0xff; 727 #endif 728 ctrl->bde_dev.base_address1 = 0; 729 } 730 731 #ifdef CONFIG_OF 732 if (!pldev->dev.of_node) 733 #endif 734 { 735 /* Assign locally if not available from device node */ 736 iproc_cmicd_get_irqres(ctrl->bde_dev, &pldev->resource[0]); 737 } 738 739 #ifdef CONFIG_OF 740 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 741 int i; 742 for (i = 0; i < IHOST_CMICX_MAX_INTRS; i++) { 743 irqres = iproc_platform_get_resource(pldev, IORESOURCE_IRQ, i); 744 iproc_cmicx_irqs[i] = irqres->start; 745 if (debug >= 1) { 746 gprintk("iproc_cmicx_irqs[%d] = %d\n", i, iproc_cmicx_irqs[i]); 747 } 748 } 749 ctrl->iLine = iproc_cmicx_irqs[0]; 750 } else 751 #endif 752 { 753 irqres = iproc_platform_get_resource(pldev, IORESOURCE_IRQ, 0); 754 ctrl->iLine = irqres->start; 755 } 756 757 ctrl->isr = NULL; 758 ctrl ->isr_data = NULL; 759 760 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 761 ctrl->dma_dev = &pldev->dev; 762 #endif 763 764 /* Let's boogie */ 765 _bde_add_device(); 766 return 0; 767 } 768 769 static int 770 iproc_cmicd_remove(struct platform_device *pldev) 771 { 772 return 0; 773 } 774 #ifdef CONFIG_OF 775 static const struct of_device_id iproc_cmicd_of_match[] = { 776 { .compatible = IPROC_CMICD_COMPATIBLE }, 777 { .compatible = IPROC_CMICX_COMPATIBLE }, 778 {}, 779 }; 780 MODULE_DEVICE_TABLE(of, iproc_cmicd_of_match); 781 #endif 782 static char iproc_cmicd_string[] = "bcmiproc-cmicd"; 783 784 static struct platform_driver iproc_cmicd_driver = 785 { 786 .probe = iproc_cmicd_probe, 787 .remove = iproc_cmicd_remove, 788 .driver = 789 { 790 .name = iproc_cmicd_string, 791 .owner = THIS_MODULE, 792 #ifdef CONFIG_OF 793 .of_match_table = iproc_cmicd_of_match, 794 #endif 795 }, 796 }; 797 798 typedef enum { 799 IPROC_CMICD_RES_INTR = 0, 800 IPROC_CMICD_RES_MEM 801 } IPROC_CMICD_RES_E; 802 803 static struct resource iproc_cmicd_resources[] = { 804 [IPROC_CMICD_RES_INTR] = { 805 .flags = IORESOURCE_IRQ, 806 .start = IPROC_CMICD_INT, 807 }, 808 [IPROC_CMICD_RES_MEM] = { 809 .flags = IORESOURCE_MEM, 810 .start = IPROC_CMICD_BASE, 811 .end = IPROC_CMICD_BASE+IPROC_CMICD_SIZE-1, 812 }, 813 }; 814 815 static void 816 iproc_cmicd_release(struct device *dev) 817 { 818 } 819 820 static u64 iproc_cmicd_dmamask = DMA_BIT_MASK(32); 821 822 static struct platform_device iproc_cmicd_pdev = { 823 .name = iproc_cmicd_string, 824 .id = 0, 825 .dev = { 826 .release = iproc_cmicd_release, 827 .init_name = iproc_cmicd_string, 828 .dma_mask = &iproc_cmicd_dmamask, 829 .coherent_dma_mask = DMA_BIT_MASK(32), 830 }, 831 .resource = iproc_cmicd_resources, 832 .num_resources = ARRAY_SIZE(iproc_cmicd_resources), 833 }; 834 835 static int 836 iproc_has_cmicd(void) 837 { 838 void *iproc_cca_base; 839 uint32 cca_cid; 840 841 /* Read ChipcommonA chip id register to identify current SOC */ 842 iproc_cca_base = IOREMAP(IPROC_CHIPCOMMONA_BASE, 0x3000); 843 if (iproc_cca_base == NULL) { 844 gprintk("iproc_has_cmicd: ioremap of ChipcommonA registers failed"); 845 return 0; 846 } 847 cca_cid = readl((uint32 *)iproc_cca_base); 848 cca_cid &= 0xffff; 849 iounmap(iproc_cca_base); 850 851 /* Only allowed accessing CMICD module if the SOC has it */ 852 switch (cca_cid) { 853 default: 854 break; 855 } 856 857 /* Device has CMIC */ 858 return 1; 859 } 860 861 #define IPROC_CHIPCOMMONA_EROM_PTR_OFFSET (0x180000fc) 862 #define EROM_MAX_SIZE (0x1000) 863 #define EROM_PARTNUM_CMICD (0x14) 864 865 #define EROM_DESC_COMPIDENT (0x1) 866 #define EROM_DESC_MASTER (0x3) 867 #define EROM_DESC_ADDR (0x5) 868 #define EROM_DESC_END (0xF) 869 #define EROM_DESC_EMPTY (0) 870 871 #define EROM_IS_DESC_COMPIDENT(x) ((x & 0x7) == EROM_DESC_COMPIDENT) 872 #define EROM_IS_DESC_MASTER(x) ((x & 0x7) == EROM_DESC_MASTER) 873 #define EROM_IS_DESC_ADDR(x) ((x & 0x7) == EROM_DESC_ADDR) 874 #define EROM_IS_DESC_END(x) ((x & 0xF) == EROM_DESC_END) 875 876 #define EROM_GET_PARTNUM(x) ((x >> 8) & (0xFFF)) /* Bit 8~19 */ 877 #define EROM_GET_ADDRESS(x) ((x >> 12) & (0xFFFFF)) /* Bit 12~31 */ 878 #define EROM_GET_SIZETYPE(x) ((x >> 4) & (0x3)) /* Bit 4~5 */ 879 #define EROM_GET_AG32(x) ((x >> 3) & (0x1)) /* Bit 3 */ 880 #define EROM_GET_SIZE(x) ((x >> 12) & (0xFFFFF)) /* Bit 12~31 */ 881 #define EROM_GET_SG32(x) ((x >> 3) & (0x1)) /* Bit 3 */ 882 883 #define EROM_ADDR_SIZETYPE_4K (0) 884 #define EROM_ADDR_SIZETYPE_8K (1) 885 #define EROM_ADDR_SIZETYPE_16K (2) 886 #define EROM_ADDR_SIZETYPE_MORE (3) 887 888 #define EROM_ADDR_FLAG_AG32 (1) /* Address space greater than 32 bit */ 889 #define EROM_ADDR_FLAG_SIZE (2) /* Addition size descriptor */ 890 #define EROM_ADDR_FLAG_SG32 (4) /* Size descriptor greater than 32 bit */ 891 892 static void 893 iproc_cmicd_get_memregion(struct resource *res_mem) 894 { 895 void *erom_ptr_oft; 896 uint32_t erom_phy_addr; 897 uint32_t *erom_base; 898 uint32_t i = 0; 899 uint32_t word = 0; 900 uint8_t more_addr_word = 0; /* bit 0: AG32; bit 1: SIZE; bit 2: SG32 */ 901 uint8_t found_cmicd_dev = 0; 902 uint8_t size_type = 0; 903 bool is_compident_a = 1; /* 1: CompidentA; o/w: CompidentB */ 904 905 erom_ptr_oft = IOREMAP(IPROC_CHIPCOMMONA_EROM_PTR_OFFSET, 0x100); 906 907 erom_phy_addr = readl((uint32 *)(erom_ptr_oft)); 908 iounmap(erom_ptr_oft); 909 910 erom_base = IOREMAP(erom_phy_addr, EROM_MAX_SIZE); 911 912 while (1) { 913 word = readl((uint32 *)(erom_base + i)); 914 915 if (EROM_IS_DESC_ADDR(word) || more_addr_word) { 916 if (more_addr_word == 0) { /* Normal Addr Desc */ 917 if (EROM_GET_AG32(word) == 1) { 918 more_addr_word |= EROM_ADDR_FLAG_AG32; 919 } 920 921 size_type = EROM_GET_SIZETYPE(word); 922 if (size_type == EROM_ADDR_SIZETYPE_MORE) { 923 more_addr_word |= EROM_ADDR_FLAG_SIZE; 924 } 925 926 if (found_cmicd_dev == 1) { 927 res_mem->start = EROM_GET_ADDRESS(word) << 12; 928 if (size_type < EROM_ADDR_SIZETYPE_MORE) { 929 res_mem->end = res_mem->start + 4096 * (1 << size_type) - 1; 930 } 931 } 932 } 933 else if (more_addr_word & EROM_ADDR_FLAG_AG32) { /* UpperAddr Desc */ 934 more_addr_word &= ~EROM_ADDR_FLAG_AG32; 935 936 if (found_cmicd_dev == 1) { 937 /* res_mem->start |= word << 32; */ 938 gprintk("Expect cmicd address to be 32-bit\n"); 939 } 940 } 941 else if (more_addr_word & EROM_ADDR_FLAG_SIZE) { /* Size Desc */ 942 if (EROM_GET_SG32(word) == 1) { 943 more_addr_word |= EROM_ADDR_FLAG_SG32; 944 } 945 946 more_addr_word &= ~EROM_ADDR_FLAG_SIZE; 947 948 if (found_cmicd_dev == 1) { 949 res_mem->end = res_mem->start + (EROM_GET_SIZE(word) << 12) - 1; 950 } 951 } 952 else if (more_addr_word & EROM_ADDR_FLAG_SG32) { /* UpperSize Desc */ 953 more_addr_word &= ~EROM_ADDR_FLAG_SG32; 954 955 if (found_cmicd_dev == 1) { 956 /* res_mem->end += (word) << 32; */ 957 gprintk("Expect cmicd size to be 32-bit\n"); 958 } 959 } 960 961 if (found_cmicd_dev == 1 && more_addr_word == 0) { 962 break; /* We have gotten all necessary information, exit the loop */ 963 } 964 } 965 else if (EROM_IS_DESC_COMPIDENT(word)) { 966 if (is_compident_a == 1) { 967 if (EROM_GET_PARTNUM(word) == EROM_PARTNUM_CMICD) { 968 found_cmicd_dev = 1; 969 } 970 } 971 972 is_compident_a = 1 - is_compident_a; 973 } 974 else if (EROM_IS_DESC_END(word)) { 975 break; 976 } 977 978 i++; 979 } 980 iounmap(erom_base); 981 982 if (debug >= 1) { 983 gprintk("CMICD info by %s: cmicd_mem.start=%lx, cmicd_mem.end=%lx\n", 984 found_cmicd_dev ? "EROM" : "Default", 985 (unsigned long)iproc_cmicd_resources[IPROC_CMICD_RES_MEM].start, 986 (unsigned long)iproc_cmicd_resources[IPROC_CMICD_RES_MEM].end); 987 } 988 } 989 #endif /* IPROC_CMICD */ 990 991 #ifdef BCM_ICS 992 static int 993 _ics_bde_create(void) 994 { 995 bde_ctrl_t *ctrl; 996 uint32 dev_rev_id = 0x0; 997 resource_size_t paddr; 998 999 if (_ndevices == 0) { 1000 ctrl = _devices + _ndevices; 1001 1002 ctrl->dev_type |= BDE_ICS_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 1003 ctrl->pci_device = NULL; /* No PCI bus */ 1004 1005 /* Map in the device */ 1006 paddr = BCM_ICS_CMIC_BASE; 1007 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(paddr, 0x10000); 1008 ctrl->phys_address = paddr; 1009 1010 dev_rev_id = *((unsigned int *)(KSEG1ADDR(paddr + 0x178))); 1011 1012 ctrl->bde_dev.device = dev_rev_id & 0xFFFF; 1013 ctrl->bde_dev.rev = (dev_rev_id >> 16) & 0xFF; 1014 1015 ctrl->iLine = 5; /* From raptor linux BSP */ 1016 1017 ctrl->isr = NULL; 1018 ctrl->isr_data = NULL; 1019 printk("Created ICS device ..%x\n", ctrl->bde_dev.base_address); 1020 _bde_add_device(); 1021 } 1022 1023 return 0; 1024 } 1025 1026 #else /* !BCM_ICS */ 1027 1028 extern struct pci_bus *pci_find_bus(int domain, int busnr); 1029 1030 /* 1031 * PCI device table. 1032 * Populated from the include/soc/devids.h file. 1033 */ 1034 1035 static const struct pci_device_id _id_table[] = { 1036 { BROADCOM_VENDOR_ID, BCM5675_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1037 { BROADCOM_VENDOR_ID, BCM5676_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1038 { BROADCOM_VENDOR_ID, BCM56218X_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1039 { BROADCOM_VENDOR_ID, BCM56218_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1040 { BROADCOM_VENDOR_ID, BCM56219_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1041 { BROADCOM_VENDOR_ID, BCM56218R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1042 { BROADCOM_VENDOR_ID, BCM56219R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1043 { BROADCOM_VENDOR_ID, BCM56214_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1044 { BROADCOM_VENDOR_ID, BCM56215_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1045 { BROADCOM_VENDOR_ID, BCM56214R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1046 { BROADCOM_VENDOR_ID, BCM56215R_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1047 { BROADCOM_VENDOR_ID, BCM56216_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1048 { BROADCOM_VENDOR_ID, BCM56217_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1049 { BROADCOM_VENDOR_ID, BCM56212_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1050 { BROADCOM_VENDOR_ID, BCM56213_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1051 { BROADCOM_VENDOR_ID, BCM56230_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1052 { BROADCOM_VENDOR_ID, BCM56231_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1053 { BROADCOM_VENDOR_ID, BCM53718_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1054 { BROADCOM_VENDOR_ID, BCM53714_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1055 { BROADCOM_VENDOR_ID, BCM53716_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1056 { BROADCOM_VENDOR_ID, BCM56018_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1057 { BROADCOM_VENDOR_ID, BCM56014_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1058 { BROADCOM_VENDOR_ID, BCM56224_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1059 { BROADCOM_VENDOR_ID, BCM56225_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1060 { BROADCOM_VENDOR_ID, BCM56226_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1061 { BROADCOM_VENDOR_ID, BCM56227_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1062 { BROADCOM_VENDOR_ID, BCM56228_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1063 { BROADCOM_VENDOR_ID, BCM56229_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1064 { BROADCOM_VENDOR_ID, BCM56024_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1065 { BROADCOM_VENDOR_ID, BCM56025_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1066 { BROADCOM_VENDOR_ID, BCM53724_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1067 { BROADCOM_VENDOR_ID, BCM53726_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1068 { BROADCOM_VENDOR_ID, BCM56100_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1069 { BROADCOM_VENDOR_ID, BCM56101_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1070 { BROADCOM_VENDOR_ID, BCM56102_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1071 { BROADCOM_VENDOR_ID, BCM56105_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1072 { BROADCOM_VENDOR_ID, BCM56106_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1073 { BROADCOM_VENDOR_ID, BCM56107_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1074 { BROADCOM_VENDOR_ID, BCM56110_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1075 { BROADCOM_VENDOR_ID, BCM56111_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1076 { BROADCOM_VENDOR_ID, BCM56112_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1077 { BROADCOM_VENDOR_ID, BCM56115_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1078 { BROADCOM_VENDOR_ID, BCM56116_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1079 { BROADCOM_VENDOR_ID, BCM56117_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1080 { BROADCOM_VENDOR_ID, BCM56300_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1081 { BROADCOM_VENDOR_ID, BCM56301_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1082 { BROADCOM_VENDOR_ID, BCM56302_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1083 { BROADCOM_VENDOR_ID, BCM56303_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1084 { BROADCOM_VENDOR_ID, BCM56304_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1085 { BROADCOM_VENDOR_ID, BCM56404_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1086 { BROADCOM_VENDOR_ID, BCM56305_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1087 { BROADCOM_VENDOR_ID, BCM56306_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1088 { BROADCOM_VENDOR_ID, BCM56307_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1089 { BROADCOM_VENDOR_ID, BCM56308_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1090 { BROADCOM_VENDOR_ID, BCM56309_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1091 { BROADCOM_VENDOR_ID, BCM56310_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1092 { BROADCOM_VENDOR_ID, BCM56311_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1093 { BROADCOM_VENDOR_ID, BCM56312_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1094 { BROADCOM_VENDOR_ID, BCM56313_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1095 { BROADCOM_VENDOR_ID, BCM56314_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1096 { BROADCOM_VENDOR_ID, BCM56315_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1097 { BROADCOM_VENDOR_ID, BCM56316_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1098 { BROADCOM_VENDOR_ID, BCM56317_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1099 { BROADCOM_VENDOR_ID, BCM56318_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1100 { BROADCOM_VENDOR_ID, BCM56319_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1101 #ifndef EXCLUDE_BCM56324 1102 { BROADCOM_VENDOR_ID, BCM56322_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1103 { BROADCOM_VENDOR_ID, BCM56324_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1104 #endif /* EXCLUDE_BCM56324 */ 1105 { BROADCOM_VENDOR_ID, BCM53312_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1106 { BROADCOM_VENDOR_ID, BCM53313_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1107 { BROADCOM_VENDOR_ID, BCM53314_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1108 { BROADCOM_VENDOR_ID, BCM53324_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1109 { BROADCOM_VENDOR_ID, BCM53333_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1110 { BROADCOM_VENDOR_ID, BCM53334_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1111 { BROADCOM_VENDOR_ID, BCM53342_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1112 { BROADCOM_VENDOR_ID, BCM53343_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1113 { BROADCOM_VENDOR_ID, BCM53344_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1114 { BROADCOM_VENDOR_ID, BCM53346_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1115 { BROADCOM_VENDOR_ID, BCM53347_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1116 { BROADCOM_VENDOR_ID, BCM53393_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1117 { BROADCOM_VENDOR_ID, BCM53394_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1118 { BROADCOM_VENDOR_ID, BCM53300_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1119 { BROADCOM_VENDOR_ID, BCM53301_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1120 { BROADCOM_VENDOR_ID, BCM53302_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1121 { BROADCOM_VENDOR_ID, BCM56500_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1122 { BROADCOM_VENDOR_ID, BCM56501_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1123 { BROADCOM_VENDOR_ID, BCM56502_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1124 { BROADCOM_VENDOR_ID, BCM56503_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1125 { BROADCOM_VENDOR_ID, BCM56504_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1126 { BROADCOM_VENDOR_ID, BCM56505_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1127 { BROADCOM_VENDOR_ID, BCM56506_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1128 { BROADCOM_VENDOR_ID, BCM56507_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1129 { BROADCOM_VENDOR_ID, BCM56508_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1130 { BROADCOM_VENDOR_ID, BCM56509_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1131 { BROADCOM_VENDOR_ID, BCM56510_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1132 { BROADCOM_VENDOR_ID, BCM56511_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1133 { BROADCOM_VENDOR_ID, BCM56512_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1134 { BROADCOM_VENDOR_ID, BCM56513_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1135 { BROADCOM_VENDOR_ID, BCM56514_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1136 { BROADCOM_VENDOR_ID, BCM56516_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1137 { BROADCOM_VENDOR_ID, BCM56517_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1138 { BROADCOM_VENDOR_ID, BCM56518_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1139 { BROADCOM_VENDOR_ID, BCM56519_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1140 { BROADCOM_VENDOR_ID, BCM56580_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1141 { BROADCOM_VENDOR_ID, BCM56620_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1142 { BROADCOM_VENDOR_ID, BCM56624_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1143 { BROADCOM_VENDOR_ID, BCM56626_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1144 { BROADCOM_VENDOR_ID, BCM56628_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1145 { BROADCOM_VENDOR_ID, BCM56629_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1146 { BROADCOM_VENDOR_ID, BCM56680_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1147 { BROADCOM_VENDOR_ID, BCM56684_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1148 { BROADCOM_VENDOR_ID, BCM56700_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1149 { BROADCOM_VENDOR_ID, BCM56701_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1150 { BROADCOM_VENDOR_ID, BCM56720_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1151 { BROADCOM_VENDOR_ID, BCM56721_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1152 { BROADCOM_VENDOR_ID, BCM56725_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1153 { BROADCOM_VENDOR_ID, BCM56800_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1154 { BROADCOM_VENDOR_ID, BCM56801_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1155 { BROADCOM_VENDOR_ID, BCM56802_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1156 { BROADCOM_VENDOR_ID, BCM56803_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1157 { BROADCOM_VENDOR_ID, BCM56820_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1158 { BROADCOM_VENDOR_ID, BCM56821_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1159 { BROADCOM_VENDOR_ID, BCM56822_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1160 { BROADCOM_VENDOR_ID, BCM56823_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1161 { BROADCOM_VENDOR_ID, BCM56825_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1162 { BROADCOM_VENDOR_ID, BCM56630_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1163 { BROADCOM_VENDOR_ID, BCM56634_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1164 { BROADCOM_VENDOR_ID, BCM56636_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1165 { BROADCOM_VENDOR_ID, BCM56638_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1166 { BROADCOM_VENDOR_ID, BCM56639_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1167 { BROADCOM_VENDOR_ID, BCM56538_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1168 { BROADCOM_VENDOR_ID, BCM56520_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1169 { BROADCOM_VENDOR_ID, BCM56521_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1170 { BROADCOM_VENDOR_ID, BCM56522_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1171 { BROADCOM_VENDOR_ID, BCM56524_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1172 { BROADCOM_VENDOR_ID, BCM56526_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1173 { BROADCOM_VENDOR_ID, BCM56534_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1174 { BROADCOM_VENDOR_ID, BCM56685_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1175 { BROADCOM_VENDOR_ID, BCM56689_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1176 { BROADCOM_VENDOR_ID, BCM56331_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1177 { BROADCOM_VENDOR_ID, BCM56333_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1178 { BROADCOM_VENDOR_ID, BCM56334_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1179 { BROADCOM_VENDOR_ID, BCM56338_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1180 { BROADCOM_VENDOR_ID, BCM56320_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1181 { BROADCOM_VENDOR_ID, BCM56321_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1182 { BROADCOM_VENDOR_ID, BCM56132_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1183 { BROADCOM_VENDOR_ID, BCM56134_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1184 { BROADCOM_VENDOR_ID, BCM88732_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1185 { BROADCOM_VENDOR_ID, BCM56140_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1186 { BROADCOM_VENDOR_ID, BCM56142_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1187 { BROADCOM_VENDOR_ID, BCM56143_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1188 { BROADCOM_VENDOR_ID, BCM56144_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1189 { BROADCOM_VENDOR_ID, BCM56146_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1190 { BROADCOM_VENDOR_ID, BCM56147_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1191 { BROADCOM_VENDOR_ID, BCM56149_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1192 { BROADCOM_VENDOR_ID, BCM56150_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1193 { BROADCOM_VENDOR_ID, BCM56151_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1194 { BROADCOM_VENDOR_ID, BCM56152_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1195 { BROADCOM_VENDOR_ID, BCM56930_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1196 { BROADCOM_VENDOR_ID, BCM56931_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1197 { BROADCOM_VENDOR_ID, BCM56935_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1198 { BROADCOM_VENDOR_ID, BCM56936_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1199 { BROADCOM_VENDOR_ID, BCM56939_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1200 { BROADCOM_VENDOR_ID, BCM56840_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1201 { BROADCOM_VENDOR_ID, BCM56841_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1202 { BROADCOM_VENDOR_ID, BCM56842_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1203 { BROADCOM_VENDOR_ID, BCM56843_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1204 { BROADCOM_VENDOR_ID, BCM56844_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1205 { BROADCOM_VENDOR_ID, BCM56845_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1206 { BROADCOM_VENDOR_ID, BCM56846_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1207 { BROADCOM_VENDOR_ID, BCM56847_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1208 { BROADCOM_VENDOR_ID, BCM56549_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1209 { BROADCOM_VENDOR_ID, BCM56053_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1210 { BROADCOM_VENDOR_ID, BCM56838_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1211 { BROADCOM_VENDOR_ID, BCM56831_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1212 { BROADCOM_VENDOR_ID, BCM56835_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1213 { BROADCOM_VENDOR_ID, BCM56849_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1214 { BROADCOM_VENDOR_ID, BCM56742_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1215 { BROADCOM_VENDOR_ID, BCM56743_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1216 { BROADCOM_VENDOR_ID, BCM56744_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1217 { BROADCOM_VENDOR_ID, BCM56745_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1218 { BROADCOM_VENDOR_ID, BCM56746_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1219 { BROADCOM_VENDOR_ID, BCM56640_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1220 { BROADCOM_VENDOR_ID, BCM56548_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1221 { BROADCOM_VENDOR_ID, BCM56547_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1222 { BROADCOM_VENDOR_ID, BCM56346_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1223 { BROADCOM_VENDOR_ID, BCM56345_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1224 { BROADCOM_VENDOR_ID, BCM56344_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1225 { BROADCOM_VENDOR_ID, BCM56342_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1226 { BROADCOM_VENDOR_ID, BCM56340_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1227 { BROADCOM_VENDOR_ID, BCM56049_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1228 { BROADCOM_VENDOR_ID, BCM56048_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1229 { BROADCOM_VENDOR_ID, BCM56047_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1230 { BROADCOM_VENDOR_ID, BCM56042_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1231 { BROADCOM_VENDOR_ID, BCM56041_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1232 { BROADCOM_VENDOR_ID, BCM56040_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1233 { BROADCOM_VENDOR_ID, BCM56643_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1234 { BROADCOM_VENDOR_ID, BCM56644_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1235 { BROADCOM_VENDOR_ID, BCM56648_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1236 { BROADCOM_VENDOR_ID, BCM56649_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1237 { BROADCOM_VENDOR_ID, BCM56540_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1238 { BROADCOM_VENDOR_ID, BCM56541_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1239 { BROADCOM_VENDOR_ID, BCM56542_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1240 { BROADCOM_VENDOR_ID, BCM56543_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1241 { BROADCOM_VENDOR_ID, BCM56544_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1242 { BROADCOM_VENDOR_ID, BCM56545_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1243 { BROADCOM_VENDOR_ID, BCM56546_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1244 { BROADCOM_VENDOR_ID, BCM56044_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1245 { BROADCOM_VENDOR_ID, BCM56045_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1246 { BROADCOM_VENDOR_ID, BCM56046_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1247 { BROADCOM_VENDOR_ID, BCM55440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1248 { BROADCOM_VENDOR_ID, BCM56440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1249 { BROADCOM_VENDOR_ID, BCM56441_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1250 { BROADCOM_VENDOR_ID, BCM56442_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1251 { BROADCOM_VENDOR_ID, BCM56443_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1252 { BROADCOM_VENDOR_ID, BCM56445_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1253 { BROADCOM_VENDOR_ID, BCM56446_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1254 { BROADCOM_VENDOR_ID, BCM56447_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1255 { BROADCOM_VENDOR_ID, BCM56448_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1256 { BROADCOM_VENDOR_ID, BCM56449_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1257 { BROADCOM_VENDOR_ID, BCM56240_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1258 { BROADCOM_VENDOR_ID, BCM56241_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1259 { BROADCOM_VENDOR_ID, BCM56242_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1260 { BROADCOM_VENDOR_ID, BCM56243_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1261 { BROADCOM_VENDOR_ID, BCM56245_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1262 { BROADCOM_VENDOR_ID, BCM56246_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1263 { BROADCOM_VENDOR_ID, BCM55450_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1264 { BROADCOM_VENDOR_ID, BCM55455_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1265 { BROADCOM_VENDOR_ID, BCM56260_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1266 { BROADCOM_VENDOR_ID, BCM56270_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1267 { BROADCOM_VENDOR_ID, BCM56271_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1268 { BROADCOM_VENDOR_ID, BCM56272_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1269 { BROADCOM_VENDOR_ID, BCM53460_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1270 { BROADCOM_VENDOR_ID, BCM53461_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1271 { BROADCOM_VENDOR_ID, BCM56261_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1272 { BROADCOM_VENDOR_ID, BCM56262_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1273 { BROADCOM_VENDOR_ID, BCM56263_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1274 { BROADCOM_VENDOR_ID, BCM56265_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1275 { BROADCOM_VENDOR_ID, BCM56266_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1276 { BROADCOM_VENDOR_ID, BCM56267_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1277 { BROADCOM_VENDOR_ID, BCM56268_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1278 { BROADCOM_VENDOR_ID, BCM56233_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1279 { BROADCOM_VENDOR_ID, BCM56460_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1280 { BROADCOM_VENDOR_ID, BCM56461_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1281 { BROADCOM_VENDOR_ID, BCM56462_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1282 { BROADCOM_VENDOR_ID, BCM56463_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1283 { BROADCOM_VENDOR_ID, BCM56465_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1284 { BROADCOM_VENDOR_ID, BCM56466_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1285 { BROADCOM_VENDOR_ID, BCM56467_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1286 { BROADCOM_VENDOR_ID, BCM56468_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1287 { BROADCOM_VENDOR_ID, BCM56246_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1288 { BROADCOM_VENDOR_ID, BCM56248_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1289 { BROADCOM_VENDOR_ID, BCM56450_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1290 { BROADCOM_VENDOR_ID, BCM56452_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1291 { BROADCOM_VENDOR_ID, BCM56454_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1292 { BROADCOM_VENDOR_ID, BCM56455_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1293 { BROADCOM_VENDOR_ID, BCM56456_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1294 { BROADCOM_VENDOR_ID, BCM56457_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1295 { BROADCOM_VENDOR_ID, BCM56458_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1296 { BROADCOM_VENDOR_ID, BCM56850_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1297 { BROADCOM_VENDOR_ID, BCM56851_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1298 { BROADCOM_VENDOR_ID, BCM56852_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1299 { BROADCOM_VENDOR_ID, BCM56853_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1300 { BROADCOM_VENDOR_ID, BCM56854_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1301 { BROADCOM_VENDOR_ID, BCM56855_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1302 { BROADCOM_VENDOR_ID, BCM56834_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1303 { BROADCOM_VENDOR_ID, BCM56750_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1304 { BROADCOM_VENDOR_ID, BCM56830_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1305 { BROADCOM_VENDOR_ID, BCM55440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1306 { BROADCOM_VENDOR_ID, BCM55441_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1307 { BROADCOM_VENDOR_ID, BCM56060_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1308 { BROADCOM_VENDOR_ID, BCM56062_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1309 { BROADCOM_VENDOR_ID, BCM56063_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1310 { BROADCOM_VENDOR_ID, BCM56064_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1311 { BROADCOM_VENDOR_ID, BCM56065_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1312 { BROADCOM_VENDOR_ID, BCM56066_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1313 { BROADCOM_VENDOR_ID, BCM53401_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1314 { BROADCOM_VENDOR_ID, BCM53411_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1315 { BROADCOM_VENDOR_ID, BCM53402_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1316 { BROADCOM_VENDOR_ID, BCM53412_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1317 { BROADCOM_VENDOR_ID, BCM53403_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1318 { BROADCOM_VENDOR_ID, BCM53413_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1319 { BROADCOM_VENDOR_ID, BCM53404_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1320 { BROADCOM_VENDOR_ID, BCM53414_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1321 { BROADCOM_VENDOR_ID, BCM53405_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1322 { BROADCOM_VENDOR_ID, BCM53415_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1323 { BROADCOM_VENDOR_ID, BCM53406_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1324 { BROADCOM_VENDOR_ID, BCM53416_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1325 { BROADCOM_VENDOR_ID, BCM53408_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1326 { BROADCOM_VENDOR_ID, BCM53418_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1327 { BROADCOM_VENDOR_ID, BCM53454_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1328 { BROADCOM_VENDOR_ID, BCM53455_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1329 { BROADCOM_VENDOR_ID, BCM53456_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1330 { BROADCOM_VENDOR_ID, BCM53457_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1331 { BROADCOM_VENDOR_ID, BCM53422_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1332 { BROADCOM_VENDOR_ID, BCM53424_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1333 { BROADCOM_VENDOR_ID, BCM53426_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1334 { BROADCOM_VENDOR_ID, BCM53365_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1335 { BROADCOM_VENDOR_ID, BCM53369_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1336 { BROADCOM_VENDOR_ID, BCM56960_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1337 { BROADCOM_VENDOR_ID, BCM56961_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1338 { BROADCOM_VENDOR_ID, BCM56962_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1339 { BROADCOM_VENDOR_ID, BCM56963_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1340 { BROADCOM_VENDOR_ID, BCM56930_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1341 { BROADCOM_VENDOR_ID, BCM56968_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1342 { BROADCOM_VENDOR_ID, BCM56970_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1343 { BROADCOM_VENDOR_ID, BCM56971_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1344 { BROADCOM_VENDOR_ID, BCM56972_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1345 { BROADCOM_VENDOR_ID, BCM56974_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1346 { BROADCOM_VENDOR_ID, BCM56975_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1347 { BROADCOM_VENDOR_ID, BCM56168_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1348 { BROADCOM_VENDOR_ID, BCM56169_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1349 { BROADCOM_VENDOR_ID, BCM56560_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1350 { BROADCOM_VENDOR_ID, BCM56561_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1351 { BROADCOM_VENDOR_ID, BCM56562_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1352 { BROADCOM_VENDOR_ID, BCM56565_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1353 { BROADCOM_VENDOR_ID, BCM56566_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1354 { BROADCOM_VENDOR_ID, BCM56567_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1355 { BROADCOM_VENDOR_ID, BCM56670_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1356 { BROADCOM_VENDOR_ID, BCM56671_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1357 { BROADCOM_VENDOR_ID, BCM56672_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1358 { BROADCOM_VENDOR_ID, BCM56675_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1359 { BROADCOM_VENDOR_ID, BCM56568_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1360 { BROADCOM_VENDOR_ID, BCM56670_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1361 { BROADCOM_VENDOR_ID, BCM56760_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1362 { BROADCOM_VENDOR_ID, BCM56761_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1363 { BROADCOM_VENDOR_ID, BCM56762_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1364 { BROADCOM_VENDOR_ID, BCM56764_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1365 { BROADCOM_VENDOR_ID, BCM56765_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1366 { BROADCOM_VENDOR_ID, BCM56766_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1367 { BROADCOM_VENDOR_ID, BCM56768_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1368 { BROADCOM_VENDOR_ID, BCM56069_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1369 { BROADCOM_VENDOR_ID, BCM56068_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1370 { BROADCOM_VENDOR_ID, BCM56160_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1371 { BROADCOM_VENDOR_ID, BCM56162_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1372 { BROADCOM_VENDOR_ID, BCM56163_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1373 { BROADCOM_VENDOR_ID, BCM56164_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1374 { BROADCOM_VENDOR_ID, BCM56166_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1375 { BROADCOM_VENDOR_ID, BCM53440_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1376 { BROADCOM_VENDOR_ID, BCM53443_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1377 { BROADCOM_VENDOR_ID, BCM53442_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1378 { BROADCOM_VENDOR_ID, BCM53434_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1379 { BROADCOM_VENDOR_ID, BCM56965_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1380 { BROADCOM_VENDOR_ID, BCM56969_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1381 { BROADCOM_VENDOR_ID, BCM56966_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1382 { BROADCOM_VENDOR_ID, BCM56967_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1383 { BROADCOM_VENDOR_ID, BCM56170_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1384 { BROADCOM_VENDOR_ID, BCM56172_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1385 { BROADCOM_VENDOR_ID, BCM56174_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1386 { BROADCOM_VENDOR_ID, BCM53570_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1387 { BROADCOM_VENDOR_ID, BCM53575_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1388 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9656, PCI_ANY_ID, PCI_ANY_ID }, 1389 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, PCI_ANY_ID, PCI_ANY_ID }, 1390 { BCM53000_VENDOR_ID, BCM53000PCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1391 #ifdef BCM_PETRA_SUPPORT 1392 { BROADCOM_VENDOR_ID, BCM88650_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1393 { BROADCOM_VENDOR_ID, BCM88350_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1394 { BROADCOM_VENDOR_ID, BCM88351_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1395 { BROADCOM_VENDOR_ID, BCM88450_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1396 { BROADCOM_VENDOR_ID, BCM88451_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1397 { BROADCOM_VENDOR_ID, BCM88550_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1398 { BROADCOM_VENDOR_ID, BCM88551_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1399 { BROADCOM_VENDOR_ID, BCM88552_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1400 { BROADCOM_VENDOR_ID, BCM88651_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1401 { BROADCOM_VENDOR_ID, BCM88654_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1402 { PCP_PCI_VENDOR_ID, PCP_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1403 { ACP_PCI_VENDOR_ID, ACP_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1404 { BROADCOM_VENDOR_ID, BCM88660_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1405 { BROADCOM_VENDOR_ID, BCM88670_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1406 { BROADCOM_VENDOR_ID, BCM88671_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1407 { BROADCOM_VENDOR_ID, BCM88671M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1408 { BROADCOM_VENDOR_ID, BCM88672_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1409 { BROADCOM_VENDOR_ID, BCM88673_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1410 { BROADCOM_VENDOR_ID, BCM88674_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1411 { BROADCOM_VENDOR_ID, BCM88675_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1412 { BROADCOM_VENDOR_ID, BCM88675M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1413 { BROADCOM_VENDOR_ID, BCM88676_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1414 { BROADCOM_VENDOR_ID, BCM88676M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1415 { BROADCOM_VENDOR_ID, BCM88677_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1416 { BROADCOM_VENDOR_ID, BCM88678_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1417 { BROADCOM_VENDOR_ID, BCM88679_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1418 { BROADCOM_VENDOR_ID, BCM88370_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1419 { BROADCOM_VENDOR_ID, BCM88371_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1420 { BROADCOM_VENDOR_ID, BCM88371M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1421 { BROADCOM_VENDOR_ID, BCM88375_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1422 { BROADCOM_VENDOR_ID, BCM88470_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1423 { BROADCOM_VENDOR_ID, BCM88470P_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1424 { BROADCOM_VENDOR_ID, BCM88471_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1425 { BROADCOM_VENDOR_ID, BCM88473_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1426 { BROADCOM_VENDOR_ID, BCM88474_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1427 { BROADCOM_VENDOR_ID, BCM88474H_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1428 { BROADCOM_VENDOR_ID, BCM88476_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1429 { BROADCOM_VENDOR_ID, BCM88477_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1430 1431 1432 { BROADCOM_VENDOR_ID, BCM88270_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1433 { BROADCOM_VENDOR_ID, BCM88272_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1434 { BROADCOM_VENDOR_ID, BCM88273_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1435 { BROADCOM_VENDOR_ID, BCM88274_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1436 { BROADCOM_VENDOR_ID, BCM88278_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1437 { BROADCOM_VENDOR_ID, BCM88279_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1438 1439 { BROADCOM_VENDOR_ID, BCM8206_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1440 1441 { BROADCOM_VENDOR_ID, BCM88376_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1442 { BROADCOM_VENDOR_ID, BCM88376M_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1443 { BROADCOM_VENDOR_ID, BCM88377_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1444 { BROADCOM_VENDOR_ID, BCM88378_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1445 { BROADCOM_VENDOR_ID, BCM88379_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1446 { BROADCOM_VENDOR_ID, BCM88680_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1447 { BROADCOM_VENDOR_ID, BCM88681_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1448 { BROADCOM_VENDOR_ID, BCM88682_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1449 { BROADCOM_VENDOR_ID, BCM88683_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1450 { BROADCOM_VENDOR_ID, BCM88684_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1451 { BROADCOM_VENDOR_ID, BCM88685_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1452 { BROADCOM_VENDOR_ID, BCM88380_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1453 { BROADCOM_VENDOR_ID, BCM88381_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1454 { BROADCOM_VENDOR_ID, BCM88202_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1455 { BROADCOM_VENDOR_ID, BCM88360_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1456 { BROADCOM_VENDOR_ID, BCM88361_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1457 { BROADCOM_VENDOR_ID, BCM88363_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1458 { BROADCOM_VENDOR_ID, BCM88460_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1459 { BROADCOM_VENDOR_ID, BCM88461_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1460 { BROADCOM_VENDOR_ID, BCM88560_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1461 { BROADCOM_VENDOR_ID, BCM88561_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1462 { BROADCOM_VENDOR_ID, BCM88562_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1463 { BROADCOM_VENDOR_ID, BCM88661_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1464 { BROADCOM_VENDOR_ID, BCM88664_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1465 #endif 1466 #ifdef BCM_DNX_SUPPORT 1467 { BROADCOM_VENDOR_ID, BCM88690_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1468 { BROADCOM_VENDOR_ID, BCM88690_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1469 { BROADCOM_VENDOR_ID, BCM88691_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1470 { BROADCOM_VENDOR_ID, BCM88692_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1471 { BROADCOM_VENDOR_ID, BCM88693_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1472 { BROADCOM_VENDOR_ID, BCM88694_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1473 { BROADCOM_VENDOR_ID, BCM88695_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1474 { BROADCOM_VENDOR_ID, BCM88696_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1475 { BROADCOM_VENDOR_ID, BCM88697_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1476 { BROADCOM_VENDOR_ID, BCM88698_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1477 { BROADCOM_VENDOR_ID, BCM88699_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1478 { BROADCOM_VENDOR_ID, BCM8869A_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1479 { BROADCOM_VENDOR_ID, BCM8869B_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1480 { BROADCOM_VENDOR_ID, BCM8869C_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1481 { BROADCOM_VENDOR_ID, BCM8869D_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1482 { BROADCOM_VENDOR_ID, BCM8869F_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1483 { BROADCOM_VENDOR_ID, BCM88800_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1484 #endif /* BCM_DNX_SUPPORT */ 1485 #ifdef BCM_DFE_SUPPORT 1486 { BROADCOM_VENDOR_ID, BCM88750_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1487 { BROADCOM_VENDOR_ID, BCM88753_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1488 { BROADCOM_VENDOR_ID, BCM88755_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1489 { BROADCOM_VENDOR_ID, BCM88770_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1490 { BROADCOM_VENDOR_ID, BCM88773_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1491 { BROADCOM_VENDOR_ID, BCM88774_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1492 { BROADCOM_VENDOR_ID, BCM88775_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1493 { BROADCOM_VENDOR_ID, BCM88776_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1494 { BROADCOM_VENDOR_ID, BCM88777_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1495 #ifndef DNX_IGNORE_FE3200 1496 { BROADCOM_VENDOR_ID, BCM88950_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1497 #endif 1498 { BROADCOM_VENDOR_ID, BCM88953_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1499 { BROADCOM_VENDOR_ID, BCM88954_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1500 { BROADCOM_VENDOR_ID, BCM88955_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1501 { BROADCOM_VENDOR_ID, BCM88956_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1502 { BROADCOM_VENDOR_ID, BCM88752_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1503 { BROADCOM_VENDOR_ID, BCM88772_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1504 { BROADCOM_VENDOR_ID, BCM88952_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1505 #endif 1506 #ifdef BCM_DNXF_SUPPORT 1507 { BROADCOM_VENDOR_ID, BCM88790_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1508 { BROADCOM_VENDOR_ID, BCM88791_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1509 { BROADCOM_VENDOR_ID, BCM88792_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1510 { BROADCOM_VENDOR_ID, BCM88793_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1511 { BROADCOM_VENDOR_ID, BCM88794_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1512 { BROADCOM_VENDOR_ID, BCM88795_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1513 { BROADCOM_VENDOR_ID, BCM88796_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1514 { BROADCOM_VENDOR_ID, BCM88797_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1515 { BROADCOM_VENDOR_ID, BCM88798_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1516 { BROADCOM_VENDOR_ID, BCM88799_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1517 { BROADCOM_VENDOR_ID, BCM8879A_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1518 { BROADCOM_VENDOR_ID, BCM8879B_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1519 { BROADCOM_VENDOR_ID, BCM8879C_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1520 { BROADCOM_VENDOR_ID, BCM8879D_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1521 { BROADCOM_VENDOR_ID, BCM8879F_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1522 #endif 1523 { BROADCOM_VENDOR_ID, BCM56860_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1524 { BROADCOM_VENDOR_ID, BCM56861_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1525 { BROADCOM_VENDOR_ID, BCM56862_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1526 { BROADCOM_VENDOR_ID, BCM56864_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1527 { BROADCOM_VENDOR_ID, BCM56865_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1528 { BROADCOM_VENDOR_ID, BCM56866_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1529 { BROADCOM_VENDOR_ID, BCM56867_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1530 { BROADCOM_VENDOR_ID, BCM56868_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1531 { BROADCOM_VENDOR_ID, BCM56833_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1532 { BROADCOM_VENDOR_ID, BCM56832_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1533 { BROADCOM_VENDOR_ID, BCM56836_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1534 { BROADCOM_VENDOR_ID, BCM56870_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1535 { BROADCOM_VENDOR_ID, BCM56370_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1536 { BROADCOM_VENDOR_ID, BCM56371_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1537 { BROADCOM_VENDOR_ID, BCM56372_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1538 { BROADCOM_VENDOR_ID, BCM56374_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1539 { BROADCOM_VENDOR_ID, BCM56375_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1540 { BROADCOM_VENDOR_ID, BCM56376_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1541 { BROADCOM_VENDOR_ID, BCM56377_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1542 { BROADCOM_VENDOR_ID, BCM56577_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1543 { BROADCOM_VENDOR_ID, BCM56578_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1544 { BROADCOM_VENDOR_ID, BCM56579_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1545 { BROADCOM_VENDOR_ID, BCM56873_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1546 { BROADCOM_VENDOR_ID, BCM56770_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1547 { BROADCOM_VENDOR_ID, BCM56771_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1548 { BROADCOM_VENDOR_ID, BCM56980_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1549 { BROADCOM_VENDOR_ID, BCM56981_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1550 { BROADCOM_VENDOR_ID, BCM56982_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1551 { BROADCOM_VENDOR_ID, BCM56983_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1552 { BROADCOM_VENDOR_ID, BCM56984_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1553 { BROADCOM_VENDOR_ID, BCM53540_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1554 { BROADCOM_VENDOR_ID, BCM53547_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1555 { BROADCOM_VENDOR_ID, BCM53548_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1556 { BROADCOM_VENDOR_ID, BCM53549_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, 1557 { 0, 0, 0, 0 } 1558 };; 1559 1560 MODULE_DEVICE_TABLE(pci, _id_table); 1561 1562 #define pci_bus_b(n) list_entry(n, struct pci_bus, node) 1563 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) 1564 #define MAX_RC_NUM 4 1565 1566 static struct pci_bus * 1567 pci_do_bus_find(struct pci_bus* bus, int rc, int vendor, int device) 1568 { 1569 struct list_head *tmp; 1570 struct pci_dev *dev; 1571 struct pci_bus *sub_bus; 1572 int func = 0; 1573 1574 if (unlikely(list_empty(&bus->children))) { 1575 return NULL; 1576 } 1577 list_for_each(tmp, &bus->children) { 1578 sub_bus = pci_bus_b(tmp); 1579 dev = sub_bus->self; 1580 func = dev->devfn & 0x7; 1581 if (dev->vendor == vendor && dev->device == device && rc == func) { 1582 if (debug >= 1) { 1583 gprintk("pci_do_bus_find: dev->vendor = 0x%x, dev->device = 0x%x on rc(%d)\n", 1584 dev->vendor, dev->device, rc); 1585 } 1586 return sub_bus; 1587 } 1588 } 1589 return NULL; 1590 } 1591 1592 static struct pci_dev * 1593 _pci_do_bus_dev_find(struct pci_bus* bus, unsigned int vendor, unsigned int device) 1594 { 1595 struct list_head *tmp; 1596 struct pci_dev *dev; 1597 1598 if (unlikely(list_empty(&bus->devices))) { 1599 return NULL; 1600 } 1601 list_for_each(tmp, &bus->devices) { 1602 dev = pci_dev_b(tmp); 1603 if (dev->vendor == vendor && (device == PCI_ANY_ID || dev->device == device)) { 1604 if (debug >= 1) { 1605 gprintk("_pci_do_rc_dev_find: vendor = %x, device = %x\n", vendor, device); 1606 } 1607 return dev; 1608 } 1609 } 1610 return NULL; 1611 } 1612 1613 static struct pci_dev * 1614 pci_do_rc_dev_find(int rc) 1615 { 1616 struct pci_bus *root_bus = pci_find_bus(0,0); 1617 struct pci_bus *bus_rc = NULL; 1618 struct pci_dev *dev_on_rc = NULL; 1619 unsigned int pci_dev_id = 0; 1620 1621 if(NULL == root_bus) { 1622 if (debug >= 1) gprintk("Not find root bus\n"); 1623 return NULL; 1624 } 1625 bus_rc = pci_do_bus_find(root_bus, rc, 0x184e, 0x1004); 1626 if (NULL == bus_rc) { 1627 if (debug >= 1) { 1628 gprintk("Not find vendor(0x184e) device(0x1004) bus\n"); 1629 } 1630 return NULL; 1631 } 1632 for(pci_dev_id = 0; pci_dev_id < sizeof(_id_table)/sizeof(struct pci_device_id); pci_dev_id++) { 1633 dev_on_rc = _pci_do_bus_dev_find(bus_rc, _id_table[pci_dev_id].vendor, _id_table[pci_dev_id].device); 1634 if (NULL != dev_on_rc) { 1635 return dev_on_rc; 1636 } 1637 } 1638 if (debug >= 1) { 1639 gprintk("Not find device at rc(%d)\n", rc); 1640 } 1641 return NULL; 1642 } 1643 1644 /* 1645 * Function: p2p_bridge 1646 * 1647 * Purpose: 1648 * Finalize initialization secondary PCI-PCI bridge. 1649 * Parameters: 1650 * membase - start of memory address space for secondary PCI bus 1651 * Returns: 1652 * 0 1653 * Notes: 1654 * The membase depends on the processor architecture, and is 1655 * derived from the memory space addresses set up by the kernel. 1656 */ 1657 static int 1658 p2p_bridge(void) 1659 { 1660 struct pci_dev *dev, *dev_on_rc; 1661 uint16 cmd; 1662 uint16 mem_base; 1663 uint16 mem_limit; 1664 uint8 bridge_ctrl; 1665 uint8 rc_index; 1666 1667 if ((dev = PCI_FIND_DEV(DC21150_VENDOR_ID, DC21150_DEVICE_ID, NULL)) != NULL || 1668 (dev = PCI_FIND_DEV(HINT_HB4_VENDOR_ID, HINT_HB4_DEVICE_ID, NULL)) != NULL || 1669 (dev = PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)) != NULL) { 1670 1671 if (debug >= 1) gprintk("fixing up PCI-to-PCI bridge\n"); 1672 /* Adjust command register */ 1673 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1674 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 1675 /* Disable device */ 1676 pci_write_config_word(dev, PCI_COMMAND, 0); 1677 /* Initialize non-prefetchable memory window if needed */ 1678 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base); 1679 if (mem_base == 0) { 1680 mem_base = (uint16)((_pci_mem_start & 0xFFF00000) >> 16); 1681 mem_limit = (uint16)((_pci_mem_end & 0xFFF00000) >> 16); 1682 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base); 1683 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit); 1684 } 1685 /* Enable PCI clocks on remote end */ 1686 pci_write_config_word(dev, PCI_CFG_DEC21150_SEC_CLK, 0); 1687 /* Re-enable config space */ 1688 pci_write_config_word(dev, PCI_COMMAND, cmd); 1689 1690 /* Avoid DMA data corruption */ 1691 if (dev->vendor == HINT_HB4_VENDOR_ID) { 1692 /* Fix for HiNT bridge and BCM4704 DMA problem */ 1693 if ((dev = PCI_FIND_DEV(BCM4704_VENDOR_ID, BCM4704_DEVICE_ID, NULL)) != NULL) { 1694 /* Reset PrefetchEn (PE) */ 1695 pci_write_config_dword(dev, 0x8c, 1); 1696 if (debug >= 1) { 1697 gprintk("reset PrefetchEn on BCM4704 when HiNT bridge is present\n"); 1698 } 1699 } 1700 } 1701 } 1702 /* Enable fast back-to-back read/write */ 1703 if ((dev = PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)) != NULL) { 1704 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1705 cmd |= PCI_COMMAND_FAST_BACK; 1706 pci_read_config_byte(dev, PCI_BRIDGE_CONTROL, &bridge_ctrl); 1707 bridge_ctrl |= PCI_BRIDGE_CTL_FAST_BACK; 1708 pci_write_config_word(dev, PCI_COMMAND, 0); 1709 pci_write_config_byte(dev, PCI_BRIDGE_CONTROL, bridge_ctrl); 1710 pci_write_config_word(dev, PCI_COMMAND, cmd); 1711 } 1712 /* Netlogic XLP CPU */ 1713 for(rc_index = 0; rc_index < MAX_RC_NUM; rc_index++) { 1714 dev_on_rc = pci_do_rc_dev_find(rc_index); 1715 if (dev_on_rc != NULL ) { 1716 dev = PCI_FIND_DEV(0x184e, 0x1004, NULL); 1717 if (dev != NULL ) { 1718 pci_write_config_dword(dev,0x78,MAX_PAYLOAD_256B | 1719 MAX_READ_REQ_256B); 1720 } 1721 } 1722 } 1723 if ((dev = PCI_FIND_DEV(0x14e4, 0xb634, NULL)) != NULL) { 1724 pci_write_config_dword(dev,0x78,MAX_PAYLOAD_256B | 1725 MAX_READ_REQ_256B); 1726 } 1727 1728 if ((dev = PCI_FIND_DEV(PCI_VNDID_PERICOM, PCI_DEVID_PI7C9X130, NULL)) != NULL) { 1729 /* 1730 * Configure the PCIE cap: Max payload size: 256, Max Read 1731 * Request size: 256, disabling relax ordering. 1732 * Writes to the PCIE capability device control register 1733 */ 1734 pci_write_config_dword(dev, DEV_CTRL_REG, 1735 MAX_PAYLOAD_256B | MAX_READ_REQ_256B); 1736 } 1737 1738 if ((dev = PCI_FIND_DEV(FSL_VENDOR_ID, FSL8548PCIE_DEVICE_ID, NULL)) != NULL || 1739 (dev = PCI_FIND_DEV(FSL_VENDOR_ID, FSL2020EPCIE_DEVICE_ID, NULL)) != NULL) { 1740 /* 1741 * Configure the PCIE cap: Max payload size: 256, Max Read 1742 * Request size: 256, disabling relax ordering. 1743 * Writes to the PCIE capability device control register 1744 */ 1745 pci_write_config_dword(dev, FSL8548PCIE_DEV_CTRL_REG, 1746 MAX_PAYLOAD_256B | MAX_READ_REQ_256B); 1747 } 1748 if ((dev = PCI_FIND_DEV(BCM4716_VENDOR_ID, BCM4716PCIE_DEVICE_ID, NULL)) != NULL || 1749 (dev = PCI_FIND_DEV(BCM53000_VENDOR_ID, BCM53000PCIE_DEVICE_ID, NULL)) != NULL) { 1750 uint32 tmp, maxpayld, device_bmp=0, mask; 1751 unsigned long addr; 1752 uint16 tmp16, tmp161; 1753 int i, bus0 = -1, bus1 = -1, port; 1754 struct pci_dev *pcie0, *pcie1; 1755 1756 pcie0 = dev; 1757 bus0 = dev->bus->number; 1758 if ((pcie1 = PCI_FIND_DEV(BCM53000_VENDOR_ID, BCM53000PCIE_DEVICE_ID, pcie0)) != NULL) { 1759 bus1 = pcie1->bus->number; 1760 } 1761 1762 for(i = 0; i < _ndevices; i++) { 1763 bde_ctrl_t *ctrl = _devices + i; 1764 1765 mask = BDE_SWITCH_DEV_TYPE | BDE_PCI_DEV_TYPE; 1766 if ((ctrl->dev_type & mask) == mask) { 1767 if (ctrl->pci_device->bus->number == bus0) { 1768 device_bmp |= 1 << 0; 1769 } 1770 if (ctrl->pci_device->bus->number == bus1) { 1771 device_bmp |= 1 << 1; 1772 } 1773 } 1774 } 1775 1776 /* configure the PCIE cap: Max payload size: 256, Max Read 1777 * Request size: 256, disabling relax ordering. 1778 * Writes to the PCIE capability device control register 1779 */ 1780 1781 i = 0; 1782 while(device_bmp) { 1783 if (device_bmp & (1 << i)){ 1784 port = i ; 1785 pci_read_config_dword(BCM53000PCIE_DEV(port), 1786 BCM53000PCIE_DEV_CAP_REG, &tmp); 1787 maxpayld = (tmp & BCM53000PCIE_MAX_PAYLOAD_MASK); 1788 if (debug >= 1) { 1789 gprintk("port %d\n",port); 1790 gprintk("DevCap (@%x): 0x%x%c\n", BCM53000PCIE_DEV_CAP_REG, tmp, 1791 (maxpayld != BCM53000PCIE_CAP_MAX_PAYLOAD_256B) ? ' ':'\n'); 1792 } 1793 if (maxpayld != BCM53000PCIE_CAP_MAX_PAYLOAD_256B) { 1794 addr = BCM53000PCIE_BASE(port); 1795 addr |= (BCM53000PCIE_SROM_SPACE | BCM53000PCIE_SPROM_OFFSET); 1796 tmp16 = *((uint16 *)addr); 1797 if (debug >= 1){ 1798 gprintk("addr %lx spromData.MaxPayloadSize: 0x%x\n", addr, tmp16); 1799 } 1800 mask = BCM53000PCIE_SPROM_MAX_PAYLOAD_MASK; 1801 if ((tmp16 & mask) != BCM53000PCIE_SPROM_MAX_PAYLOAD_256B) { 1802 tmp161 = (tmp16 & ~mask) | BCM53000PCIE_SPROM_MAX_PAYLOAD_256B; 1803 *((uint16 *)addr) = tmp161; 1804 if (debug >= 1) { 1805 tmp16 = 0; 1806 tmp16 = *((uint16 *)addr); 1807 gprintk("Enable spromData.MaxPayloadSize to 1 (256 bytes): " 1808 "0x%x (%s w/ 0x%x)\n", tmp161, 1809 ((tmp16 & mask) == BCM53000PCIE_SPROM_MAX_PAYLOAD_256B) ? 1810 "Success":"Fail", 1811 tmp16); 1812 } 1813 } 1814 pci_read_config_dword(BCM53000PCIE_DEV(port), 1815 BCM53000PCIE_DEV_CAP_REG, &tmp); 1816 if (debug >= 1){ 1817 gprintk("DevCap (@%x): now is 0x%x\n\n", 1818 BCM53000PCIE_DEV_CAP_REG, tmp); 1819 } 1820 } 1821 1822 addr = BCM53000PCIE_BASE(port); 1823 addr |= (BCM53000PCIE_FUNC0_COFIG_SPACE | BCM53000PCIE_DEV_CTRL_REG); 1824 tmp16 = *((uint16 *)addr); 1825 if (debug >= 1) { 1826 gprintk("DevControl (@%x): 0x%x\n", BCM53000PCIE_DEV_CTRL_REG, tmp16); 1827 } 1828 if (!(tmp16 & MAX_PAYLOAD_256B) || !(tmp16 & MAX_READ_REQ_256B)) { 1829 tmp161 = tmp16 | MAX_PAYLOAD_256B | MAX_READ_REQ_256B; 1830 *((uint16 *)addr) = tmp161; 1831 if (debug >= 1) { 1832 tmp16 = 0; 1833 tmp16 = *((uint16 *)addr); 1834 gprintk("addr %lx Enable DevControl MaxPayloadSize to 1 (256 bytes): " 1835 "0x%x (%s w/ 0x%x)\n", addr, tmp161, 1836 (tmp16 & MAX_PAYLOAD_256B) ? "Success":"Fail", 1837 tmp16); 1838 gprintk("Enable DevControl MaxReadRequestSize to 1 (256 bytes): " 1839 "0x%x (%s w/ 0x%x)\n\n", tmp161, 1840 (tmp16 & MAX_READ_REQ_256B) ? "Success":"Fail", 1841 tmp16); 1842 } 1843 } 1844 device_bmp &= ~(1 << i); 1845 } 1846 i++; 1847 } 1848 } 1849 1850 /* 1851 * Configure max payload to 512 on all ports in the PLX8608/PLX8617. 1852 * The device supports 128, 512, and 1024 max payload sizes. 1853 */ 1854 dev = NULL; 1855 while ((dev = PCI_FIND_DEV(PCI_VENDOR_ID_PLX, PCI_ANY_ID, dev)) != NULL) { 1856 if ((dev->device == PLX_PEX8608_DEV_ID) || 1857 (dev->device == PLX_PEX8617_DEV_ID)) { 1858 uint16 ctrl_reg; 1859 pci_read_config_word(dev, PLX_PEX86XX_DEV_CTRL_REG, &ctrl_reg); 1860 ctrl_reg = (ctrl_reg & ~(7<<5)) | MAX_PAYLOAD_512B; 1861 pci_write_config_word(dev, PLX_PEX86XX_DEV_CTRL_REG, ctrl_reg); 1862 } 1863 } 1864 return 0; 1865 } 1866 1867 #ifdef BCM_PLX9656_LOCAL_BUS 1868 1869 #define PLX_LAS0_BA 0x00000004 /* LAS0 Local Base Address Remap */ 1870 #define PLX_LAS1_BA 0x000000f4 /* LAS1 Local Base Address Remap */ 1871 #define PLX_LAS_EN 0x00000001 /* Space Enable bit */ 1872 1873 #define PLX_MMAP_PCIBAR0 0 /* Memory-Mapped Config (PCIBAR0) */ 1874 #define PLX_LAS0_PCIBAR2 2 /* Local Address Space 0 (PCIBAR2) */ 1875 #define PLX_LAS1_PCIBAR3 3 /* Local Address Space 1 (PCIBAR3) */ 1876 1877 STATIC int 1878 _plx_las_bar_get(struct pci_dev *dev) 1879 { 1880 void *local_config_addr; 1881 int bar = -1; 1882 1883 local_config_addr = IOREMAP(pci_resource_start(dev, PLX_MMAP_PCIBAR0), 1884 pci_resource_len(dev, PLX_MMAP_PCIBAR0)); 1885 if (local_config_addr) { 1886 uint32 las_remap_reg; 1887 /* 1888 * Make sure LAS0BA or LAS1BA is enabled before returning 1889 * BAR that will be used to access the Local Bus 1890 */ 1891 las_remap_reg = ioread32(local_config_addr + PLX_LAS0_BA); 1892 if (las_remap_reg & PLX_LAS_EN) { 1893 bar = PLX_LAS0_PCIBAR2; 1894 } else { 1895 las_remap_reg = ioread32(local_config_addr + PLX_LAS1_BA); 1896 if (las_remap_reg & PLX_LAS_EN) { 1897 bar = PLX_LAS1_PCIBAR3; 1898 } 1899 } 1900 } 1901 iounmap(local_config_addr); 1902 return bar; 1903 } 1904 #endif /* BCM_PLX9656_LOCAL_BUS */ 1905 1906 static void 1907 _shbde_log_func(int level, const char *str, int param) 1908 { 1909 level = (level >= SHBDE_DBG) ? 1 : 0; 1910 if (debug >= level) { 1911 gprintk("%s (%d)\n", str, param); 1912 } 1913 } 1914 /* 1915 * Function: _device_rescan_validate 1916 * 1917 * Purpose: 1918 * Check if the device is ever probed or not. 1919 * Parameters: 1920 * dev - Linux PCI device structure 1921 * Returns: 1922 * >= 0 : dev is ever probed 1923 * reutrn value is the index point to the _devices[] 1924 * -1 : dev is not probed before. 1925 */ 1926 static int 1927 _device_rescan_validate(struct pci_dev *dev) 1928 { 1929 bde_ctrl_t *ctrl; 1930 int i; 1931 1932 if (PCI_FUNC(dev->devfn) > 0) { 1933 return -1; 1934 } 1935 ctrl = NULL; 1936 for (i = 0; i < _ndevices; i ++) { 1937 ctrl = _devices + i; 1938 /* check the device id */ 1939 if (dev->device == ctrl->bde_dev.device) { 1940 /* check the bus number */ 1941 if ((dev->bus)) { 1942 if ((dev->bus->number == ctrl->bus_no) && 1943 (pci_domain_nr(dev->bus) == ctrl->domain_no)) { 1944 return i; 1945 } 1946 } 1947 } 1948 } 1949 return -1; 1950 } 1951 1952 #ifdef CONFIG_PCI_MSI 1953 1954 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 1955 /** 1956 * _pci_msix_table_size - return the number of device's MSI-X table entries 1957 * @dev: pointer to the pci_dev data structure of MSI-X device function 1958 */ 1959 static int 1960 _pci_msix_table_size(struct pci_dev *dev) 1961 { 1962 int nr_entries = 0; 1963 1964 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,110)) 1965 u16 control; 1966 int pos; 1967 1968 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1969 if (pos) { 1970 pci_read_config_word(dev, msi_control_reg(pos), &control); 1971 nr_entries = msix_table_size(control); 1972 } 1973 #else 1974 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) 1975 { 1976 /* Pass large entry value to enable MSIX to get # of entires */ 1977 struct msix_entry *entries; 1978 entries = kmalloc(sizeof(struct msix_entry) * 1979 PCI_MSIX_FLAGS_QSIZE, GFP_KERNEL); 1980 if (entries != NULL) { 1981 nr_entries = pci_enable_msix(dev, 1982 entries, PCI_MSIX_FLAGS_QSIZE); 1983 if (nr_entries < 0) { 1984 nr_entries = 0; 1985 } 1986 pci_disable_msix(dev); 1987 kfree(entries); 1988 } 1989 } 1990 #else 1991 nr_entries = pci_msix_vec_count(dev); 1992 #endif 1993 #endif 1994 1995 return nr_entries; 1996 } 1997 #endif 1998 1999 static int 2000 _msi_connect(bde_ctrl_t *ctrl) 2001 { 2002 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2003 int ret; 2004 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 2005 int i; 2006 2007 ret = _pci_msix_table_size(ctrl->pci_device); 2008 if (ret == 0) { 2009 /* MSI-X failed */ 2010 gprintk("MSI-X not supported.\n"); 2011 goto er_intx; 2012 } 2013 ctrl->entries = kcalloc(ret, sizeof(struct msix_entry), GFP_KERNEL); 2014 2015 if (!ctrl->entries) { 2016 goto er_intx; 2017 } 2018 /* Only one vector is mapped by default */ 2019 /* May be more in future, can be controlled using module param */ 2020 ctrl->msix_cnt = msixcnt; 2021 if (unlikely(debug > 1)) 2022 gprintk("MSIX Table size = %d\n", ctrl->msix_cnt); 2023 for (i = 0; i < ctrl->msix_cnt; i++) 2024 ctrl->entries[i].entry = i; 2025 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0) 2026 ret = pci_enable_msix_range(ctrl->pci_device, 2027 ctrl->entries, ctrl->msix_cnt, ctrl->msix_cnt); 2028 #else 2029 ret = pci_enable_msix(ctrl->pci_device, 2030 ctrl->entries, ctrl->msix_cnt); 2031 if (ret > 0) { 2032 /* Not enough vectors available , Retry MSI-X */ 2033 gprintk("Retrying with MSI-X interrupts = %d\n", ret); 2034 ctrl->msix_cnt = ret; 2035 msixcnt = ret; 2036 ret = pci_enable_msix(ctrl->pci_device, 2037 ctrl->entries, ctrl->msix_cnt); 2038 if (ret != 0) 2039 goto er_intx_free; 2040 } 2041 #endif 2042 if (ret < 0) { 2043 /* Error */ 2044 goto er_intx_free; 2045 } else { 2046 gprintk("Enabled MSI-X interrupts = %d\n", ctrl->msix_cnt); 2047 return 0; 2048 } 2049 } 2050 #endif 2051 2052 if (ctrl->use_msi == PCI_USE_INT_MSI) { 2053 if (pci_enable_msi(ctrl->pci_device) == 0) { 2054 ctrl->iLine = ctrl->pci_device->irq; 2055 } else { 2056 /* MSI failed */ 2057 gprintk("Failed to initialize MSI interrupts.\n"); 2058 goto er_intx; 2059 } 2060 } else { 2061 /* failed */ 2062 gprintk("Not MSI/MSIX interrupt.\n"); 2063 goto er_intx; 2064 } 2065 return 0; 2066 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2067 er_intx_free: 2068 gprintk("Failed to enable MSI-X interrupts = %d\n", ret); 2069 kfree(ctrl->entries); 2070 #endif 2071 er_intx: 2072 return -1; 2073 2074 } 2075 2076 static int 2077 _msi_disconnect(bde_ctrl_t *ctrl) 2078 { 2079 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2080 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 2081 if (ctrl->msix_cnt) { 2082 pci_disable_msix(ctrl->pci_device); 2083 kfree(ctrl->entries); 2084 ctrl->entries = NULL; 2085 ctrl->msix_cnt = 0; 2086 } 2087 } 2088 #endif 2089 if (ctrl->use_msi == PCI_USE_INT_MSI) { 2090 pci_disable_msi(ctrl->pci_device); 2091 } else { 2092 gprintk("MSI not used\n"); 2093 } 2094 return 0; 2095 } 2096 2097 #endif 2098 2099 2100 static void 2101 config_pci_intr_type(struct pci_dev *dev, bde_ctrl_t *ctrl, int iproc) 2102 { 2103 #ifdef CONFIG_PCI_MSI 2104 int ret; 2105 shbde_iproc_config_t icfg; 2106 2107 /* Each device follows global policy by default */ 2108 ctrl->use_msi = use_msi; 2109 2110 if (unlikely(debug > 1)) 2111 gprintk("%s: msi = %d\n", __func__, ctrl->use_msi); 2112 2113 /* Check IPROC version for MSIX support */ 2114 if (iproc && ctrl->bde_dev.base_address1 && 2115 (ctrl->use_msi == PCI_USE_INT_MSIX)) { 2116 if (shbde_pci_iproc_version_get(&ctrl->shbde, dev, &icfg.iproc_ver, 2117 &icfg.cmic_ver, &icfg.cmic_rev)) { 2118 if (icfg.iproc_ver < 0xe) { 2119 gprintk("%s: MSI-X not supported, using MSI.\n", __func__); 2120 ctrl->use_msi = PCI_USE_INT_MSI; 2121 } 2122 } 2123 } 2124 2125 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2126 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 2127 /* check for support MSIX vector */ 2128 ret = _pci_msix_table_size(ctrl->pci_device); 2129 if (ret == 0) { 2130 gprintk("%s: Zero MSIX table size\n", __func__); 2131 ctrl->use_msi = PCI_USE_INT_MSI; 2132 } 2133 } 2134 #endif 2135 2136 if (ctrl->use_msi == PCI_USE_INT_MSI) { 2137 /* check for support MSI vector */ 2138 ret = pci_enable_msi(ctrl->pci_device); 2139 if (ret < 0) { 2140 ctrl->use_msi = PCI_USE_INT_INTX; 2141 gprintk("%s: Failed to enable MSI, using INTx.\n", __func__); 2142 } else { 2143 pci_disable_msi(ctrl->pci_device); 2144 } 2145 } 2146 #else 2147 ctrl->use_msi = PCI_USE_INT_INTX; 2148 #endif 2149 } 2150 2151 /* 2152 * Function: _pci_probe 2153 * 2154 * Purpose: 2155 * Device initialization callback used by the Linux PCI 2156 * subsystem. Called as a result of pci_register_driver(). 2157 * Parameters: 2158 * dev - Linux PCI device structure 2159 * Returns: 2160 * 0 2161 */ 2162 static int 2163 _pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) 2164 { 2165 bde_ctrl_t *ctrl; 2166 resource_size_t paddr; 2167 uint16 cmd = 0; 2168 uint32 bar_len; 2169 int cmic_bar; 2170 int baroff = 0; 2171 int iproc = 0; 2172 int plx_dev = 0; 2173 int eth_dev = 0; 2174 int cpu_dev = 0; 2175 int update_devid = 0; 2176 int paxb_core = 0; 2177 int add_dev = 0, rescan = 0, rescan_idx = -1; 2178 shbde_hal_t shared_bde, *shbde = &shared_bde; 2179 2180 if (debug >= 4) {gprintk("probing: vendor_id=0x%x, device_id=0x%x\n", dev->vendor, dev->device);} 2181 if (nodevices == 1) { 2182 return 0; 2183 } 2184 2185 /* Initialize Linux hardware abstraction for shared BDE functions */ 2186 linux_shbde_hal_init(shbde, _shbde_log_func); 2187 2188 /* 2189 * If an AXI-based switch device has been found already, then it means 2190 * that the AXI bus has been probed, and that we should ignore devices 2191 * found on PCI bus zero. 2192 */ 2193 2194 #if defined(IPROC_CMICD) 2195 if ((dev->bus) && (dev->bus->number == 0)) { 2196 int i; 2197 uint32 mask = BDE_SWITCH_DEV_TYPE | BDE_AXI_DEV_TYPE; 2198 2199 for (i = 0; i < _ndevices; i++) { 2200 ctrl = _devices + i; 2201 2202 if ((ctrl->dev_type & mask) == mask) { 2203 return 0; 2204 } 2205 } 2206 } 2207 #endif /* IPROC_CMICD */ 2208 2209 /* 2210 * Note that a few supported devices have a non-Broadcom PCI vendor ID, 2211 * but since none of their associated PCI device IDs collide with the 2212 * Broadcom device IDs, the probe code below only checks the device ID. 2213 */ 2214 2215 switch (dev->device) { 2216 case PCI_DEVICE_ID_PLX_9056: 2217 #ifdef DNX_TEST_BOARD 2218 break; /* a PCIe bridge to a non PCIe device should be treated as the device */ 2219 #endif /* DNX_TEST_BOARD */ 2220 case PCI_DEVICE_ID_PLX_9656: 2221 plx_dev = 1; 2222 break; 2223 case BCM53000PCIE_DEVICE_ID: 2224 cpu_dev = 1; 2225 break; 2226 /* 2227 * The device ID for 56500, 56100 and 56300 family of devices may 2228 * be incorrect just after a PCI HW reset. It needs to be read 2229 * again after stabilization. 2230 */ 2231 case BCM56102_DEVICE_ID: 2232 case BCM56504_DEVICE_ID: 2233 case BCM56304_DEVICE_ID: 2234 case BCM56314_DEVICE_ID: 2235 case BCM56112_DEVICE_ID: 2236 update_devid = 1; 2237 break; 2238 default: 2239 break; 2240 } 2241 2242 /* Check if the device is ever probed. */ 2243 rescan_idx = _device_rescan_validate(dev); 2244 if (rescan_idx != -1) { 2245 rescan = 1; 2246 } 2247 2248 ctrl = NULL; 2249 if (plx_dev) { 2250 #if defined(BCM_PLX9656_LOCAL_BUS) 2251 /* PLX chip itself won't be part of _devices[]. */ 2252 baroff = _plx_las_bar_get(dev); 2253 if (baroff == -1) { 2254 gprintk("No Local Address Space enabled in PLX\n"); 2255 return 0; 2256 } 2257 ctrl = &plx_ctrl; 2258 num_plx++; 2259 #endif 2260 } else if (eth_dev) { 2261 if (_ether_ndevices >= LINUX_BDE_MAX_ETHER_DEVICES) { 2262 return 0;; 2263 } 2264 ctrl = _devices + _ndevices; 2265 ctrl->dev_type |= BDE_ETHER_DEV_TYPE; 2266 ctrl->iLine = dev->irq; 2267 add_dev = 1; 2268 if (debug >= 1) 2269 gprintk("Found PCI device %04x:%04x as Ethernet device\n", 2270 dev->vendor, dev->device); 2271 } else if (cpu_dev) { 2272 if (_cpu_ndevices >= LINUX_BDE_MAX_CPU_DEVICES) { 2273 return 0;; 2274 } 2275 ctrl = _devices + _ndevices; 2276 ctrl->dev_type |= BDE_CPU_DEV_TYPE; 2277 add_dev = 1; 2278 if (debug >= 1) 2279 gprintk("Found PCI device %04x:%04x as CPU device\n", 2280 dev->vendor, dev->device); 2281 } else { 2282 if (PCI_FUNC(dev->devfn) > 0) { 2283 return 0; 2284 } 2285 if (_switch_ndevices >= LINUX_BDE_MAX_SWITCH_DEVICES) { 2286 return 0; 2287 } 2288 2289 if (rescan) { 2290 if (debug >= 1) { 2291 gprintk("PCI device %04x:%04x is re-probed \n", 2292 dev->vendor, dev->device); 2293 } 2294 ctrl = _devices + rescan_idx; 2295 ctrl->dev_state = BDE_DEV_STATE_CHANGED; 2296 } else { 2297 ctrl = _devices + _ndevices; 2298 ctrl->dev_type |= BDE_SWITCH_DEV_TYPE; 2299 ctrl->domain_no = pci_domain_nr(dev->bus); 2300 ctrl->bus_no = dev->bus->number; 2301 ctrl->dev_state = BDE_DEV_STATE_NORMAL; 2302 add_dev = 1; 2303 } 2304 2305 /* Save shared BDE HAL in device structure */ 2306 MEMCPY(&ctrl->shbde, shbde, sizeof(ctrl->shbde)); 2307 2308 if (update_devid) { 2309 /* Re-read the device ID */ 2310 pci_read_config_word(dev, 2311 PCI_DEVICE_ID, 2312 &ctrl->bde_dev.device); 2313 dev->device = ctrl->bde_dev.device; 2314 } 2315 2316 if (debug >= 4) {gprintk("Enabling PCI device : vendor_id=0x%x, device_id=0x%x\n", dev->vendor, dev->device);} 2317 if (pci_enable_device(dev)) { 2318 gprintk("Cannot enable PCI device : vendor_id = %x, device_id = %x\n", 2319 dev->vendor, dev->device); 2320 } 2321 2322 2323 /* 2324 * These are workarounds to get around some existing 2325 * kernel problems :( 2326 */ 2327 2328 /* 2329 * While probing we determine the overall limits for the PCI 2330 * memory windows across all devices. These limits are used 2331 * later on by the PCI-PCI bridge code. 2332 */ 2333 if (pci_resource_start(dev, baroff) < _pci_mem_start) { 2334 _pci_mem_start = pci_resource_start(dev, baroff); 2335 } 2336 if (pci_resource_end(dev, baroff) > _pci_mem_end) { 2337 _pci_mem_end = pci_resource_end(dev, baroff); 2338 } 2339 2340 #ifdef CONFIG_SANDPOINT 2341 /* 2342 * Something wrong with the PCI subsystem in the mousse kernel. 2343 * The device is programmed correctly, but the irq in the pci 2344 * structure is hosed. This checks for the hosed-ness and fixes it. 2345 */ 2346 if (dev->irq > 100) { 2347 dev->irq = 2; 2348 gprintk("irq problem: setting irq = %d\n", dev->irq); 2349 } 2350 #endif 2351 2352 #ifdef CONFIG_BMW 2353 /* 2354 * PCI subsystem does not always program the system correctly. 2355 */ 2356 if (dev->irq < 16 && dev->irq != 2) { 2357 dev->irq = 2; 2358 gprintk("irq problem: setting irq = %d\n", dev->irq); 2359 } 2360 #endif 2361 2362 #ifdef CONFIG_IDT_79EB334 2363 /* 2364 * IDT kernel is not currently mapping interrupts correctly 2365 * Hardwired to core mips interrupt, irq 3 for kernel 2.4.18 2366 */ 2367 if (dev->irq != 3) { 2368 dev->irq = 3; 2369 gprintk("irq problem: setting irq = %d\n", dev->irq); 2370 } 2371 #endif 2372 2373 #ifdef CONFIG_BCM94702_CPCI 2374 /* 2375 * Hardwired to core mips interrupt irq 6 on MBZ 2376 */ 2377 if (dev->irq != 6) { 2378 dev->irq = 6; 2379 gprintk("irq problem: setting irq = %d\n", dev->irq); 2380 } 2381 #endif 2382 2383 if ((PCI_FIND_DEV(BCM4704_VENDOR_ID, BCM4704_DEVICE_ID, NULL)) != NULL) { 2384 /* 2385 * Decrease the PCI bus priority for the CPU for better overall 2386 * system performance. This change significantly reduces the 2387 * number of PCI retries from other devices on the PCI bus. 2388 */ 2389 void * _mc_vbase = IOREMAP(BCM4704_MEMC_BASE, 0x1000); 2390 int priorinv = 0x80; 2391 static int done = 0; 2392 if (!done) { 2393 done = 1; 2394 writel(priorinv, _mc_vbase + BCM4704_MEMC_PRIORINV); 2395 if (debug >= 1) 2396 gprintk("set BCM4704 PriorInvTim register to 0x%x\n", priorinv); 2397 iounmap(_mc_vbase); 2398 } 2399 } 2400 2401 if ((PCI_FIND_DEV(SIBYTE_PCI_VENDOR_ID, SIBYTE_PCI_DEVICE_ID, NULL)) != NULL) { 2402 /* 2403 * The BCM91125CPCI CPU boards with a PCI-PCI bridge use the same 2404 * interrupt line for all switch ships behind the bridge. 2405 */ 2406 if (PCI_FIND_DEV(DC21150_VENDOR_ID, DC21150_DEVICE_ID, NULL) || 2407 PCI_FIND_DEV(HINT_HB4_VENDOR_ID, HINT_HB4_DEVICE_ID, NULL) || 2408 PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)) { 2409 /* 2410 * By default we try to guess the correct IRQ based on the design. 2411 * For now we only look at the bridge vendor, but it may be necessary 2412 * to look at the switch chip configuration as well. 2413 */ 2414 if (forceirq == -1) { 2415 if ((PCI_FIND_DEV(HINT_HB4_VENDOR_ID, HINT_HB4_DEVICE_ID, NULL)) || 2416 ((dev->device == BCM5674_DEVICE_ID) && 2417 (PCI_FIND_DEV(PI7C8150_VENDOR_ID, PI7C8150_DEVICE_ID, NULL)))) { 2418 forceirq = 58; 2419 } else { 2420 forceirq = 56; 2421 } 2422 } 2423 } 2424 } 2425 2426 if (((PCI_FIND_DEV(BCM58525_PCI_VENDOR_ID, BCM58525_PCI_DEVICE_ID, NULL)) != NULL) || 2427 ((PCI_FIND_DEV(BCM58525_PCI_VENDOR_ID, BCM58522_PCI_DEVICE_ID, NULL)) != NULL) || 2428 ((PCI_FIND_DEV(BCM58712_PCI_VENDOR_ID, BCM58712_PCI_DEVICE_ID, NULL)) != NULL) ) { 2429 /* BCM58525/BCM58712 CPU boards support 128 Max payload size */ 2430 if (maxpayload) { 2431 maxpayload = 128; 2432 if (debug >= 1) gprintk("force max payload size to 128\n"); 2433 } 2434 } 2435 2436 if (forceirq > 0 && dev->irq != (uint32) forceirq) { 2437 if (forceirqubm & (1U << (_ndevices - 1))) { 2438 dev->irq = forceirq; 2439 if (debug >= 1) gprintk("force irq to %d\n", forceirq); 2440 } 2441 } else if (debug >= 1) gprintk("found irq %d\n", dev->irq); 2442 2443 ctrl->iLine = dev->irq; 2444 if (unlikely(debug > 1)) 2445 gprintk("%s:irq = %d\n",__func__, ctrl->iLine); 2446 2447 if (shbde_pci_is_pcie(shbde, dev)) { 2448 /* Set PCIe max payload */ 2449 shbde_pci_max_payload_set(shbde, dev, maxpayload); 2450 } else { 2451 /* Set PCI retry to infinite on non-PCIe switch device */ 2452 pci_write_config_word(dev, 0x40, 0x0080); 2453 if (debug >= 1) gprintk("set DMA retry to infinite on switch device\n"); 2454 } 2455 } 2456 2457 #if defined(BCM_DFE_SUPPORT) 2458 switch (dev->device) { 2459 case BCM88750_DEVICE_ID: 2460 case BCM88753_DEVICE_ID: 2461 case BCM88755_DEVICE_ID: 2462 case BCM88770_DEVICE_ID: 2463 case BCM88773_DEVICE_ID: 2464 case BCM88774_DEVICE_ID: 2465 case BCM88775_DEVICE_ID: 2466 case BCM88776_DEVICE_ID: 2467 case BCM88777_DEVICE_ID: 2468 case BCM88950_DEVICE_ID: 2469 case BCM88953_DEVICE_ID: 2470 case BCM88954_DEVICE_ID: 2471 case BCM88955_DEVICE_ID: 2472 case BCM88956_DEVICE_ID: 2473 case BCM88752_DEVICE_ID: 2474 case BCM88772_DEVICE_ID: 2475 case BCM88952_DEVICE_ID: 2476 2477 /* 2478 * For DMA transactions - set Max_Payload_Size and 2479 * Max_Read_Request_Size to 128 bytes. 2480 */ 2481 pci_write_config_byte(dev, 0xb5, 0x0c); 2482 pci_write_config_byte(dev, 0xb4, 0x0); 2483 break; 2484 default: 2485 break; 2486 } 2487 #endif /* BCM_DFE_SUPPORT */ 2488 2489 #if defined(BCM_DNXF_SUPPORT) 2490 /*All Ramon devices from 0x8790 to 0x879F*/ 2491 if ((dev->device & BCM_DNXF_DEVID_MASK) == BCM88790_DEVICE_ID) { 2492 /* 2493 * For DMA transactions - set Max_Payload_Size and 2494 * Max_Read_Request_Size to 128 bytes. 2495 */ 2496 pci_write_config_byte(dev, 0xb5, 0x0c); 2497 pci_write_config_byte(dev, 0xb4, 0x0); 2498 2499 } 2500 #endif 2501 2502 /* Prevent compiler warning */ 2503 if (ctrl == NULL) { 2504 return 0; 2505 } 2506 2507 ctrl->be_pio = 0; 2508 ctrl->dev_type |= BDE_PCI_DEV_TYPE; 2509 ctrl->pci_device = dev; 2510 pci_set_drvdata(dev, ctrl); 2511 2512 /* Check for iProc device */ 2513 if (shbde_pci_is_iproc(shbde, dev, &cmic_bar)) { 2514 iproc = 1; 2515 if (cmic_bar >= 0) { 2516 baroff = cmic_bar; 2517 } 2518 } 2519 #ifdef DNX_TEST_BOARD 2520 else if (dev->device == PLX9056_DEVICE_ID && baroff == 0) { 2521 baroff = 2; 2522 ctrl->dev_type |= BDE_NO_IPROC/* | BDE_BYTE_SWAP*/; 2523 } 2524 #endif /* DNX_TEST_BOARD */ 2525 2526 /* Get the device revision */ 2527 pci_read_config_byte(dev, PCI_REVISION_ID, &ctrl->bde_dev.rev); 2528 2529 /* Map in the device */ 2530 ctrl->bde_dev.device = dev->device; 2531 paddr = pci_resource_start(dev, baroff); 2532 2533 switch (dev->device) { 2534 #if defined(BCM_PETRA_SUPPORT) && defined(__DUNE_LINUX_BCM_CPU_PCIE__) 2535 case GEDI_DEVICE_ID: 2536 case PCP_PCI_DEVICE_ID: 2537 bar_len = 0x1000000; 2538 break; 2539 #endif 2540 default: 2541 bar_len = pci_resource_len(dev, baroff); 2542 break; 2543 } 2544 2545 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(paddr, bar_len); 2546 ctrl->phys_address = paddr; 2547 if (debug >= 3) { 2548 gprintk("BAR %d: kernel addr:0x%lx phys addr:0x%lx length:%lx\n", 2549 baroff, (unsigned long)ctrl->bde_dev.base_address, (unsigned long)paddr, (unsigned long)bar_len); 2550 } 2551 2552 /* Map secondary address spaces */ 2553 if (iproc 2554 #ifdef DNX_TEST_BOARD 2555 || (dev->device == PLX9056_DEVICE_ID && baroff == 2) 2556 #endif /* DNX_TEST_BOARD */ 2557 ) { 2558 paddr = pci_resource_start(dev, 0); 2559 bar_len = pci_resource_len(dev, 0); 2560 ctrl->bde_dev.base_address1 = (sal_vaddr_t)IOREMAP(paddr, bar_len); 2561 ctrl->phys_address1 = paddr; 2562 if (debug >= 3) { 2563 gprintk("BAR 0: kernel addr:0x%lx phys addr:0x%lx length:%lx\n", 2564 (unsigned long)ctrl->bde_dev.base_address1, (unsigned long)paddr, (unsigned long)bar_len); 2565 } 2566 } 2567 2568 /* configure interrupt type */ 2569 config_pci_intr_type(dev, ctrl, iproc); 2570 2571 /* Configure iProc PCI-AXI bridge */ 2572 if (iproc && ctrl->bde_dev.base_address1) { 2573 void *iproc_regs; 2574 shbde_iproc_config_t *icfg = &shbde->icfg; 2575 2576 /* Mapped iProc regs in PCI BAR 0 */ 2577 iproc_regs = (void *)ctrl->bde_dev.base_address1; 2578 2579 /* iProc configuration parameters */ 2580 (void)shbde_pci_iproc_version_get(shbde, dev, &icfg->iproc_ver, 2581 &icfg->cmic_ver, &icfg->cmic_rev); 2582 shbde_iproc_config_init(icfg, ctrl->bde_dev.device, ctrl->bde_dev.rev); 2583 2584 if (debug >= 2) { 2585 gprintk("iproc version = %x dma_hi_bits = %x\n", icfg->iproc_ver, icfg->dma_hi_bits); 2586 } 2587 icfg->use_msi = ctrl->use_msi; 2588 2589 /* Call shared function */ 2590 paxb_core = shbde_iproc_paxb_init(shbde, iproc_regs, icfg); 2591 2592 /* Save PCI core information for CMIC */ 2593 if (paxb_core == 1) { 2594 ctrl->dev_type |= BDE_DEV_BUS_ALT; 2595 } 2596 2597 /* Save MSI enable state information */ 2598 if (ctrl->use_msi) { 2599 ctrl->dev_type |= BDE_DEV_BUS_MSI; 2600 } 2601 2602 /* iProc PCIe preemphasis */ 2603 shbde_iproc_pcie_preemphasis_set(shbde, iproc_regs, icfg, dev); 2604 } 2605 2606 /* Save shared BDE HAL in device structure */ 2607 MEMCPY(&ctrl->shbde, shbde, sizeof(ctrl->shbde)); 2608 2609 2610 ctrl->isr = NULL; 2611 ctrl->isr_data = NULL; 2612 2613 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2614 if (!(cmd & PCI_COMMAND_MEMORY) || !(cmd & PCI_COMMAND_MASTER)) { 2615 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 2616 pci_write_config_word(dev, PCI_COMMAND, cmd); 2617 if (debug >= 1) gprintk("enable PCI resources 0x%x (PCI_COMMAND)\n", cmd); 2618 } 2619 2620 /* Check if we need 256 KB memory window (default is 64 KB) */ 2621 bar_len = pci_resource_len(dev, baroff); 2622 if (bar_len == 0x40000) { 2623 ctrl->dev_type |= BDE_256K_REG_SPACE; 2624 if (debug >= 1) gprintk("PCI resource len 256K\n"); 2625 } else if (bar_len == 0x800000) { 2626 ctrl->dev_type |= BDE_256K_REG_SPACE | BDE_8MB_REG_SPACE; 2627 if (debug >= 1) gprintk("PCI resource len 8MB\n"); 2628 } 2629 2630 2631 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 2632 ctrl->dma_dev = &dev->dev; 2633 #endif 2634 2635 if (debug >= 2) { 2636 gprintk("_pci_probe: configured dev:0x%x rev:0x%x with base_addresses: 0x%lx 0x%lx\n", 2637 (unsigned)ctrl->bde_dev.device, (unsigned)ctrl->bde_dev.rev, 2638 (unsigned long)ctrl->bde_dev.base_address, (unsigned long)ctrl->bde_dev.base_address1); 2639 } 2640 2641 if (add_dev) { 2642 _bde_add_device(); 2643 } 2644 /* Let's boogie */ 2645 return 0; 2646 } 2647 2648 /* 2649 * Function: _pci_remove 2650 * 2651 * Purpose: 2652 * Detach driver from device. Called from pci_unregister_driver(). 2653 * Parameters: 2654 * dev - Linux PCI device structure 2655 * Returns: 2656 * 0 2657 */ 2658 static void 2659 _pci_remove(struct pci_dev* dev) 2660 { 2661 bde_ctrl_t *ctrl; 2662 2663 if (nodevices == 1) { 2664 return; 2665 } 2666 2667 #if defined(BCM_DFE_SUPPORT) 2668 if (dev->device == PCI_DEVICE_ID_PLX_9056) { 2669 return; 2670 } 2671 #endif 2672 2673 ctrl = (bde_ctrl_t *) pci_get_drvdata(dev); 2674 2675 if (ctrl == NULL) { 2676 /* Unused device */ 2677 return; 2678 } 2679 ctrl->dev_state = BDE_DEV_STATE_REMOVED; 2680 if (debug >= 1) { 2681 gprintk("PCI device %04x:%04x is removed. \n", 2682 dev->vendor, dev->device); 2683 } 2684 if (ctrl->bde_dev.base_address1) { 2685 iounmap((void *)ctrl->bde_dev.base_address1); 2686 } 2687 if (ctrl->bde_dev.base_address) { 2688 iounmap((void *)ctrl->bde_dev.base_address); 2689 } 2690 2691 /* Free our interrupt handler, if we have one */ 2692 if (ctrl->isr || ctrl->isr2) { 2693 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2694 if (ctrl->use_msi >= PCI_USE_INT_MSIX) { 2695 int i; 2696 for (i = 0; i < ctrl->msix_cnt; i++) 2697 free_irq(ctrl->entries[i].vector, ctrl); 2698 } 2699 else 2700 #endif 2701 { 2702 free_irq(ctrl->iLine, ctrl); 2703 } 2704 } 2705 #ifdef CONFIG_PCI_MSI 2706 _msi_disconnect(ctrl); 2707 #endif 2708 ctrl->isr = NULL; 2709 ctrl->isr_data = NULL; 2710 ctrl->isr2 = NULL; 2711 ctrl->isr2_data = NULL; 2712 } 2713 2714 static struct pci_driver _device_driver = { 2715 probe: _pci_probe, 2716 remove: _pci_remove, 2717 id_table: _id_table, 2718 /* The rest are dynamic */ 2719 }; 2720 2721 static void 2722 _spi_device_setup(void) { 2723 bde_ctrl_t *ctrl; 2724 ctrl = _devices + _ndevices; 2725 ctrl->dev_type |= BDE_SWITCH_DEV_TYPE; 2726 ctrl->iLine = 0xa3; 2727 ctrl->be_pio = 0; 2728 ctrl->dev_type |= BDE_SPI_DEV_TYPE; 2729 ctrl->bde_dev.device = spi_devid; 2730 ctrl->bde_dev.rev = spi_revid; 2731 if (debug >= 1) { 2732 gprintk("SPI Slave Mode: force ctrl->bde_dev.device=0x%x\n",ctrl->bde_dev.device); 2733 gprintk("SPI Slave Mode: force ctrl->bde_dev.rev=0x%x\n",ctrl->bde_dev.rev); 2734 gprintk("SPI Slave Mode: force ctrl->dev_type=0x%x\n",ctrl->dev_type); 2735 } 2736 _bde_add_device(); 2737 } 2738 #endif /* BCM_ICS */ 2739 2740 2741 2742 2743 #if defined(BCM_METROCORE_LOCAL_BUS) 2744 static bde_ctrl_t* 2745 map_local_bus(uint64_t addr, uint32_t size) 2746 { 2747 bde_ctrl_t *ctrl; 2748 2749 ctrl = _devices + _ndevices; 2750 2751 /* 2752 * For now: use EB type as `local bus' 2753 * (memory mapped, no DMA, no interrupts) 2754 * metrocore local bus supports interrupts, but we don't use them. 2755 */ 2756 ctrl->dev_type |= BDE_EB_DEV_TYPE | BDE_SWITCH_DEV_TYPE 2757 | (size > 64 * 1024 ? BDE_128K_REG_SPACE : 0); 2758 ctrl->pci_device = NULL; /* No PCI bus */ 2759 2760 /* Map in the device */ 2761 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(addr, size); 2762 ctrl->phys_address = addr; 2763 2764 _bde_add_device(); 2765 return(ctrl); 2766 } 2767 2768 #define BME_REVISION_OFFSET (0x0) 2769 2770 #endif 2771 2772 #ifdef BCM_PLX9656_LOCAL_BUS 2773 2774 #if 1 2775 #define DEV_REG_BASE_OFFSET PL0_OFFSET /* Polaris register base */ 2776 #define DEV_REG_DEVID 0 /* Device ID is first register */ 2777 #endif 2778 2779 /* 2780 * The difference at map_local_bus2: 2781 * 2782 * The PLX9656 PCI-to-LOCAL bridge chip already has been iomapped the 2783 * whole address space. So the devices off local bus don't need to be 2784 * mapped again. They only need to claim their own sub-space. 2785 */ 2786 static bde_ctrl_t * 2787 map_local_bus2(bde_ctrl_t *plx_ctrl, uint32_t dev_base, uint32_t size) 2788 { 2789 uint32_t dev_rev_id; 2790 uint8_t *addr; 2791 bde_ctrl_t *ctrl; 2792 2793 ctrl = _devices + _ndevices; 2794 2795 /* 2796 * For now: use EB type as `local bus' 2797 * (memory mapped, no DMA, no interrupts) 2798 * metrocore local bus supports interrupts, but we don't use them. 2799 */ 2800 ctrl->dev_type |= BDE_EB_DEV_TYPE | BDE_SWITCH_DEV_TYPE; 2801 ctrl->dev_type |= BDE_320K_REG_SPACE; /* Polaris 18 bits address + FPGA */ 2802 ctrl->pci_device = NULL; /* No PCI bus */ 2803 2804 /* Map in the device */ 2805 ctrl->bde_dev.base_address = plx_ctrl->bde_dev.base_address + dev_base; 2806 ctrl->phys_address = plx_ctrl->phys_address + (resource_size_t)dev_base; 2807 2808 #if 1 2809 addr = (uint8_t *)ctrl->bde_dev.base_address + PL0_REVISION_REG; 2810 #endif 2811 dev_rev_id = readl(addr); 2812 ctrl->bde_dev.device = dev_rev_id >> 16; 2813 ctrl->bde_dev.rev = (dev_rev_id & 0xFF); 2814 2815 2816 _bde_add_device(); 2817 2818 switch (ctrl->bde_dev.device) { 2819 default: 2820 return 0; 2821 } 2822 return(ctrl); 2823 } 2824 2825 static int 2826 probe_plx_local_bus(void) 2827 { 2828 bde_ctrl_t *ctrl; 2829 uint32_t val; 2830 uint8_t *addr; 2831 char addr_hi_str[16]; 2832 2833 if (num_plx > 1) { 2834 printk(KERN_ERR "There's more than one PLX 9656/9056 chip\n"); 2835 return -1; 2836 } 2837 addr_hi_str[0] = 0; 2838 #ifdef PHYS_ADDR_IS_64BIT 2839 sprintf(addr_hi_str, "%08x", (uint32_t)(plx_ctrl.phys_address >> 32)); 2840 #endif 2841 printk(KERN_ERR "Found PLX %04x:%04x vir: 0x%08x phy: 0x%s%08x\n", 2842 plx_ctrl.bde_dev.device, plx_ctrl.bde_dev.rev, 2843 plx_ctrl.bde_dev.base_address, addr_hi_str, 2844 (uint32_t)(plx_ctrl.phys_address)); 2845 2846 addr = (uint8_t *)plx_ctrl.bde_dev.base_address + CPLD_OFFSET + CPLD_REVISION_REG; 2847 val = readl(addr); 2848 printk(KERN_ERR "plx: CPLD revision %d\n", val & CPLD_REVISION_MASK); 2849 #if 000 2850 addr = (uint8_t *)plx_ctrl.bde_dev.base_address + CPLD_OFFSET + CPLD_RESET_REG; 2851 writel(CPLD_RESET_NONE, addr); 2852 #endif 2853 #if 1 2854 ctrl = map_local_bus2(&plx_ctrl, PL0_OFFSET, PL0_SIZE); 2855 #endif 2856 if (ctrl == 0) 2857 return -1; 2858 2859 /* Uses PLX IRQ for Polaris LC */ 2860 ctrl->iLine = 48; 2861 ctrl->isr = NULL; 2862 ctrl->isr_data = NULL; 2863 2864 return 0; 2865 } 2866 2867 #endif /* BCM_PLX9656_LOCAL_BUS */ 2868 2869 2870 2871 2872 /* 2873 * Generic module functions 2874 */ 2875 2876 /* 2877 * Function: _init 2878 * 2879 * Purpose: 2880 * Module initialization. 2881 * Attaches to kernel BDE. 2882 * Parameters: 2883 * None 2884 * Returns: 2885 * 0 on success, < 0 on error. 2886 */ 2887 static int 2888 _init(void) 2889 { 2890 #ifdef IPROC_CMICD 2891 #ifdef CONFIG_OF 2892 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 2893 iproc_platform_driver_register(&iproc_cmicd_driver); 2894 } else 2895 #endif 2896 if (iproc_has_cmicd()) { 2897 iproc_cmicd_get_memregion(&iproc_cmicd_resources[IPROC_CMICD_RES_MEM]); 2898 iproc_platform_driver_register(&iproc_cmicd_driver); 2899 #ifdef CONFIG_OF 2900 if (!of_find_compatible_node(NULL, NULL, IPROC_CMICD_COMPATIBLE)) 2901 #endif 2902 { 2903 /* Register platform device if no device node in dtb */ 2904 iproc_platform_device_register(&iproc_cmicd_pdev); 2905 } 2906 } 2907 #endif /* IPROC_CMICD */ 2908 2909 #ifdef BCM_ICS 2910 _ics_bde_create(); 2911 #else /* PCI */ 2912 /* Register our goodies */ 2913 _device_driver.name = LINUX_KERNEL_BDE_NAME; 2914 2915 2916 /* Configure MSI interrupt support */ 2917 use_msi = usemsi; 2918 2919 #ifdef CONFIG_PCI_MSI 2920 if (use_msi == PCI_USE_INT_NONE) { 2921 /* Compilation flag determines default value */ 2922 #ifdef BDE_LINUX_USE_MSIX_INTERRUPT 2923 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 2924 use_msi = PCI_USE_INT_MSIX; 2925 #else 2926 use_msi = PCI_USE_INT_MSI; 2927 #endif 2928 #elif defined(BDE_LINUX_USE_MSI_INTERRUPT) 2929 use_msi = PCI_USE_INT_MSI; 2930 #else 2931 use_msi = PCI_USE_INT_INTX; 2932 #endif 2933 } 2934 #else 2935 if (use_msi > PCI_USE_INT_INTX) { 2936 /* Warn if invalid configuration */ 2937 gprintk("MSI interrupts not supported by kernel\n"); 2938 } 2939 use_msi = PCI_USE_INT_INTX; 2940 #endif /* CONFIG_PCI_MSI */ 2941 2942 if (unlikely(debug >= 1)) 2943 gprintk("%s(%d):use_msi = %d\n", __func__, __LINE__, use_msi); 2944 if (spi_devid) { 2945 _spi_device_setup(); 2946 } else { 2947 if (pci_register_driver(&_device_driver) < 0) { 2948 return -ENODEV; 2949 } 2950 } 2951 2952 /* Note: PCI-PCI bridge uses results from pci_register_driver */ 2953 p2p_bridge(); 2954 2955 #ifdef BCM_METROCORE_LOCAL_BUS 2956 if (probe_metrocore_local_bus()) { 2957 return -1; 2958 } 2959 #endif 2960 #ifdef BCM_PLX9656_LOCAL_BUS 2961 if (num_plx > 0) { 2962 probe_plx_local_bus(); 2963 } 2964 #endif 2965 #endif /* BCM_ICS */ 2966 2967 2968 #ifdef BCM_SAND_SUPPORT 2969 sand_device_create(); 2970 #endif 2971 2972 /* 2973 * Probe for EB Bus devices. 2974 */ 2975 if (eb_bus) { 2976 char *tok; 2977 uint irq = -1, eb_rd16bit=0, eb_wr16bit =0; 2978 unsigned int eb_ba = 0x0; 2979 2980 gprintk("EB bus info: %s\n", eb_bus); 2981 tok = strtok(eb_bus,","); 2982 while (tok) { 2983 _parse_eb_args(tok, "BA=%x IRQ=%d RD16=%d WR16=%d", 2984 &eb_ba, &irq, &eb_rd16bit, &eb_wr16bit); 2985 _eb_device_create(eb_ba, irq, eb_rd16bit, eb_wr16bit); 2986 tok = strtok(NULL,","); 2987 } 2988 } 2989 2990 return 0; 2991 } 2992 2993 /* 2994 * Function: _cleanup 2995 * 2996 * Purpose: 2997 * Module cleanup function. 2998 * Parameters: 2999 * None 3000 * Returns: 3001 * Always 0 3002 */ 3003 static int 3004 _cleanup(void) 3005 { 3006 int i; 3007 3008 _dma_cleanup(); 3009 3010 #ifdef IPROC_CMICD 3011 #ifdef CONFIG_OF 3012 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 3013 iproc_platform_driver_unregister(&iproc_cmicd_driver); 3014 } else 3015 #endif 3016 if (iproc_has_cmicd()) { 3017 #ifdef CONFIG_OF 3018 if (!of_find_compatible_node(NULL, NULL, IPROC_CMICD_COMPATIBLE)) 3019 #endif 3020 { 3021 iproc_platform_device_unregister(&iproc_cmicd_pdev); 3022 } 3023 iproc_platform_driver_unregister(&iproc_cmicd_driver); 3024 } 3025 #endif 3026 3027 for (i = 0; i < _ndevices; i++) { 3028 bde_ctrl_t *ctrl = _devices + i; 3029 3030 /* free allocated kernel space memory */ 3031 if (ctrl->dev_type & BDE_SPI_DEV_TYPE) { 3032 if (ctrl->spi_device) { 3033 kfree(ctrl->spi_device); 3034 } 3035 } 3036 } 3037 #if defined(BCM_SAND_SUPPORT) && (defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__)) 3038 if (cpu_address) { /* unmap CPU card MMIO */ 3039 iounmap(cpu_address); 3040 cpu_address = NULL; 3041 } 3042 #endif 3043 3044 #ifdef BCM_ICS 3045 #else 3046 pci_unregister_driver(&_device_driver); 3047 #endif /* BCM_ICS */ 3048 return 0; 3049 } 3050 3051 /* 3052 * Function: _pprint 3053 * 3054 * Purpose: 3055 * Print proc filesystem information. 3056 * Parameters: 3057 * None 3058 * Returns: 3059 * Always 0 3060 */ 3061 static int 3062 _pprint(void) 3063 { 3064 int i = 0; 3065 3066 pprintf("Broadcom Device Enumerator (%s)\n", LINUX_KERNEL_BDE_NAME); 3067 3068 _dma_pprint(); 3069 3070 if (_ndevices == 0) { 3071 pprintf("No devices found\n"); 3072 } else { 3073 pprintf("Devices:\n"); 3074 } 3075 for (i = 0; i < _ndevices; i++) { 3076 bde_ctrl_t *ctrl = _devices + i; 3077 3078 if (ctrl->dev_type & BDE_SWITCH_DEV_TYPE) { 3079 pprintf("\t%d (swi) : ", i); 3080 } else if (ctrl->dev_type & BDE_ETHER_DEV_TYPE) { 3081 pprintf("\t%d (eth) : ", i); 3082 } else if (ctrl->dev_type & BDE_CPU_DEV_TYPE) { 3083 pprintf("\t%d (cpu) : ", i); 3084 } else { 3085 pprintf("\t%d (?) : ", i); 3086 } 3087 3088 if (ctrl->dev_state == BDE_DEV_STATE_REMOVED) { 3089 pprintf("PCI device 0x%x:0x%x:%d REMOVED\n", 3090 ctrl->pci_device->vendor, 3091 ctrl->pci_device->device, 3092 ctrl->bde_dev.rev); 3093 continue; 3094 } 3095 if (ctrl->dev_type & BDE_PCI_DEV_TYPE) { 3096 pprintf("PCI device %02x:%02x.%x 0x%x:0x%x:%d:0x%.8lx:0x%.8lx:%d%s\n", 3097 (unsigned int)ctrl->pci_device->bus->number, 3098 PCI_SLOT(ctrl->pci_device->devfn), 3099 PCI_FUNC(ctrl->pci_device->devfn), 3100 ctrl->pci_device->vendor, 3101 ctrl->pci_device->device, 3102 ctrl->bde_dev.rev, 3103 (unsigned long)pci_resource_start(ctrl->pci_device, 0), 3104 (unsigned long)pci_resource_start(ctrl->pci_device, 2), 3105 ctrl->pci_device->irq, 3106 ctrl->use_msi ? " (MSI)" : ""); 3107 } else if (ctrl->dev_type & BDE_SPI_DEV_TYPE) { 3108 pprintf("SPI Device %d:%x:%x:0x%x:0x%x:%d\n", 3109 ctrl->spi_device->cid, 3110 ctrl->spi_device->part, 3111 ctrl->spi_device->rev, 3112 ctrl->spi_device->phyid_high, 3113 ctrl->spi_device->phyid_low, 3114 ctrl->bde_dev.rev); 3115 } else if (ctrl->dev_type & BDE_ICS_DEV_TYPE) { 3116 pprintf("ICS Device 0x%x:0x%x\n", 3117 ctrl->bde_dev.device, 3118 ctrl->bde_dev.rev); 3119 } else if (ctrl->dev_type & BDE_AXI_DEV_TYPE) { 3120 pprintf("AXI Device 0x%x:0x%x:0x%.8lx:%d\n", 3121 ctrl->bde_dev.device, 3122 ctrl->bde_dev.rev, 3123 (unsigned long)ctrl->phys_address, 3124 ctrl->iLine); 3125 } else if (ctrl->dev_type & BDE_EB_DEV_TYPE) { 3126 pprintf("EB Bus Device 0x%x:0x%x\n", 3127 ctrl->bde_dev.device, 3128 ctrl->bde_dev.rev); 3129 } 3130 if (debug >= 1) { 3131 pprintf("\t\timask:imask2:fmask 0x%x:0x%x:0x%x\n", 3132 ctrl->imask, 3133 ctrl->imask2, 3134 ctrl->fmask); 3135 } 3136 } 3137 return 0; 3138 } 3139 3140 /* Workaround for broken Busybox/PPC insmod */ 3141 static char _modname[] = LINUX_KERNEL_BDE_NAME; 3142 3143 static gmodule_t _gmodule = { 3144 name: LINUX_KERNEL_BDE_NAME, 3145 major: LINUX_KERNEL_BDE_MAJOR, 3146 init: _init, 3147 cleanup: _cleanup, 3148 pprint: _pprint, 3149 mmap: _dma_mmap, 3150 }; 3151 3152 gmodule_t * 3153 gmodule_get(void) 3154 { 3155 _gmodule.name = _modname; 3156 return &_gmodule; 3157 } 3158 3159 3160 /* 3161 * BDE Interface 3162 */ 3163 3164 static const char * 3165 _name(void) 3166 { 3167 return LINUX_KERNEL_BDE_NAME; 3168 } 3169 3170 static int 3171 _num_devices(int type) 3172 { 3173 switch (type) { 3174 case BDE_ALL_DEVICES: 3175 return _ndevices; 3176 case BDE_SWITCH_DEVICES: 3177 return _switch_ndevices; 3178 case BDE_ETHER_DEVICES: 3179 return _ether_ndevices; 3180 case BDE_CPU_DEVICES: 3181 return _cpu_ndevices; 3182 } 3183 3184 return 0; 3185 } 3186 3187 static const ibde_dev_t * 3188 _get_dev(int d) 3189 { 3190 if (!VALID_DEVICE(d)) { 3191 gprintk("_get_dev: Invalid device index %d\n", d); 3192 return NULL; 3193 } 3194 3195 return &_devices[d].bde_dev; 3196 } 3197 3198 static uint32 3199 _get_dev_type(int d) 3200 { 3201 if (!VALID_DEVICE(d)) { 3202 gprintk("_get_dev: Invalid device index %d\n", d); 3203 return 0; 3204 } 3205 3206 return _devices[d].dev_type; 3207 } 3208 3209 static uint32 3210 _pci_conf_read(int d, uint32 addr) 3211 { 3212 #ifdef BCM_ICS 3213 return 0xFFFFFFFF; 3214 #else 3215 uint32 rc = 0; 3216 3217 if (!VALID_DEVICE(d)) { 3218 gprintk("_pci_conf_read: Invalid device index %d\n", d); 3219 return 0xFFFFFFFF; 3220 } 3221 3222 if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { 3223 gprintk("_pci_conf_read: Not PCI device %d, type %x\n", 3224 d, _devices[d].dev_type); 3225 return 0xFFFFFFFF; 3226 } 3227 3228 pci_read_config_dword(_devices[d].pci_device, addr, &rc); 3229 return rc; 3230 #endif /* BCM_ICS */ 3231 } 3232 3233 static int 3234 _pci_conf_write(int d, uint32 addr, uint32 data) 3235 { 3236 #ifdef BCM_ICS 3237 return -1; 3238 #else 3239 if (!VALID_DEVICE(d)) { 3240 gprintk("_pci_conf_write: Invalid device index %d\n", d); 3241 return -1; 3242 } 3243 3244 if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { 3245 gprintk("_pci_conf_write: Not PCI device %d, type %x\n", 3246 d, _devices[d].dev_type); 3247 return -1; 3248 } 3249 3250 pci_write_config_dword(_devices[d].pci_device, addr, data); 3251 return 0; 3252 #endif /* BCM_ICS */ 3253 } 3254 3255 /* Initialized when the bde is created */ 3256 static linux_bde_bus_t _bus; 3257 3258 static void 3259 _pci_bus_features(int unit, int *be_pio, int *be_packet, int *be_other) 3260 { 3261 if ((_devices[unit].bde_dev.device & 0xFF00) != 0x5600 && 3262 (_devices[unit].bde_dev.device & 0xF000) != 0xc000 && 3263 (_devices[unit].bde_dev.device & 0xF000) != 0xb000 && 3264 (_devices[unit].bde_dev.device & 0xF000) != 0x8000 && 3265 (_devices[unit].bde_dev.device & 0xFFF0) != 0x0230 && 3266 (_devices[unit].bde_dev.device & 0xFFF0) != 0xa440) { 3267 if (be_pio) *be_pio = 0; 3268 if (be_packet) *be_packet = 0; 3269 if (be_other) *be_other = 0; 3270 } else { 3271 if (be_pio) *be_pio = _bus.be_pio; 3272 if (be_packet) *be_packet = _bus.be_packet; 3273 if (be_other) *be_other = _bus.be_other; 3274 } 3275 #if defined(BCM_METROCORE_LOCAL_BUS) 3276 if (_devices[unit].dev_type & BDE_EB_DEV_TYPE && be_pio) { 3277 *be_pio = 1; 3278 } 3279 #endif 3280 3281 } 3282 3283 static uint32_t 3284 _read(int d, uint32_t addr) 3285 { 3286 unsigned long flags; 3287 volatile uint16 msb, lsb; 3288 uint32 sl_addr, data; 3289 3290 if (!VALID_DEVICE(d)) { 3291 return -1; 3292 } 3293 3294 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3295 return -1; 3296 } 3297 3298 if (_devices[d].dev_type & BDE_DEV_BUS_RD_16BIT) { 3299 /* 3300 * Adjust the address presented to Eb slave. Move A15:A0 to A16:A1. 3301 */ 3302 sl_addr = (addr & 0xffff0000) | ((addr & 0xffff) << 1); 3303 /* Disable interrupts */ 3304 spin_lock_irqsave(&bus_lock, flags); 3305 3306 lsb = *((uint16 *)(_devices[d].bde_dev.base_address + sl_addr)); 3307 msb = *((uint16 *)(_devices[d].bde_dev.base_address + sl_addr)); 3308 spin_unlock_irqrestore(&bus_lock, flags); 3309 3310 return (msb << 16) | lsb; 3311 } else { 3312 data = ((VOL uint32_t *)_devices[d].bde_dev.base_address)[addr / 4]; 3313 #if defined(CMIC_SOFT_BYTE_SWAP) 3314 data = CMIC_SWAP32(data); 3315 #endif 3316 return data; 3317 } 3318 } 3319 3320 static int 3321 _write(int d, uint32_t addr, uint32_t data) 3322 { 3323 unsigned long flags; 3324 uint32 sl_addr; 3325 3326 if (!VALID_DEVICE(d)) { 3327 return -1; 3328 } 3329 3330 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3331 return -1; 3332 } 3333 3334 if (_devices[d].dev_type & BDE_DEV_BUS_WR_16BIT) { 3335 /* 3336 * Adjust the address presented to Eb slave. Move A15:A0 to A16:A1. 3337 */ 3338 sl_addr = (addr & 0xffff0000) | ((addr & 0xffff) << 1); 3339 3340 /* Disable interrupts */ 3341 spin_lock_irqsave(&bus_lock, flags); 3342 3343 *((VOL uint16 *)(_devices[d].bde_dev.base_address + sl_addr)) = 3344 data & 0xffff; 3345 *((VOL uint16 *)(_devices[d].bde_dev.base_address + sl_addr)) = 3346 (data >> 16) & 0xffff; 3347 spin_unlock_irqrestore(&bus_lock, flags); 3348 } else { 3349 #if defined(CMIC_SOFT_BYTE_SWAP) 3350 data = CMIC_SWAP32(data); 3351 #endif 3352 ((VOL uint32_t *)_devices[d].bde_dev.base_address)[addr / 4] = data; 3353 #ifdef KEYSTONE 3354 /* Enforce PCIe transaction ordering. Commit the write transaction */ 3355 __asm__ __volatile__("sync"); 3356 #endif 3357 } 3358 return 0; 3359 3360 } 3361 3362 static _ISR_RET 3363 _isr(_ISR_PARAMS(irq, dev_id, iregs)) 3364 { 3365 bde_ctrl_t *ctrl = (bde_ctrl_t *) dev_id; 3366 3367 if (ctrl && ctrl->isr) { 3368 ctrl->isr(ctrl->isr_data); 3369 } 3370 if (ctrl && ctrl->isr2) { 3371 ctrl->isr2(ctrl->isr2_data); 3372 } 3373 return IRQ_HANDLED; 3374 } 3375 3376 static int 3377 _interrupt_connect(int d, 3378 void (*isr)(void *), 3379 void *isr_data) 3380 { 3381 bde_ctrl_t *ctrl; 3382 unsigned long irq_flags; 3383 int isr2_dev; 3384 int isr_active; 3385 int ret = 0; 3386 3387 isr2_dev = d & LKBDE_ISR2_DEV; 3388 d &= ~LKBDE_ISR2_DEV; 3389 3390 if (!VALID_DEVICE(d)) { 3391 gprintk("_interrupt_connect: Invalid device index %d\n", d); 3392 return -1; 3393 } 3394 if (debug >= 1) { 3395 gprintk("_interrupt_connect d %d\n", d); 3396 } 3397 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3398 gprintk("_interrupt_connect: Not PCI device %d, type %x\n", 3399 d, _devices[d].dev_type); 3400 return -1; 3401 } 3402 3403 ctrl = _devices + d; 3404 3405 isr_active = (ctrl->isr || ctrl->isr2) ? 1 : 0; 3406 3407 if (unlikely(debug > 1)) 3408 gprintk("%s:isr_active = %d\n", __func__, isr_active); 3409 3410 if (isr2_dev) { 3411 if (debug >= 1) { 3412 gprintk("connect secondary isr\n"); 3413 } 3414 ctrl->isr2_data = isr_data; 3415 ctrl->isr2 = isr; 3416 if (isr_active) { 3417 /* Main handler (_isr) already installed */ 3418 return 0; 3419 } 3420 } else { 3421 if (debug >= 1) { 3422 gprintk("connect primary isr\n"); 3423 } 3424 ctrl->isr = isr; 3425 ctrl->isr_data = isr_data; 3426 if (isr_active) { 3427 /* Main handler (_isr) already installed */ 3428 return 0; 3429 } 3430 } 3431 3432 if (ctrl->iLine != -1) { 3433 irq_flags = IRQF_SHARED; 3434 #ifdef CONFIG_PCI_MSI 3435 if (ctrl->use_msi >= PCI_USE_INT_MSI) { 3436 ret = _msi_connect(ctrl); 3437 if(ret != 0) 3438 goto msi_exit; 3439 } 3440 #endif 3441 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 3442 if (ctrl->use_msi == PCI_USE_INT_MSIX) { 3443 int i; 3444 for (i = 0; i < ctrl->msix_cnt; i++) { 3445 if (unlikely(debug >= 1)) { 3446 gprintk("%s(%d):device# = %d, irq = %d\n", 3447 __func__, __LINE__, d, ctrl->entries[i].vector); 3448 } 3449 ret = request_irq(ctrl->entries[i].vector, (irq_handler_t)_isr, 0, 3450 LINUX_KERNEL_BDE_NAME, ctrl); 3451 if (ret < 0) 3452 break; 3453 } 3454 if (ret < 0) { 3455 while (i >= 0) 3456 free_irq(ctrl->entries[i--].vector, ctrl); 3457 3458 goto err_disable_msi; 3459 } 3460 } 3461 else 3462 #endif 3463 { 3464 #if defined(IPROC_CMICD) && defined(CONFIG_OF) 3465 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 3466 int i, j; 3467 for (i = 0; i < IHOST_CMICX_MAX_INTRS; i++) { 3468 if (unlikely(debug >= 1)) 3469 gprintk("%s(%d):device# = %d, request_irq(%d)\n", 3470 __func__, __LINE__, d, iproc_cmicx_irqs[i]); 3471 ret = request_irq(iproc_cmicx_irqs[i], (irq_handler_t)_isr, 3472 irq_flags, LINUX_KERNEL_BDE_NAME, ctrl); 3473 if (ret < 0) { 3474 gprintk("request_irq(%d) failed(%d)\n", iproc_cmicx_irqs[i], ret); 3475 break; 3476 } 3477 } 3478 if (ret < 0) { 3479 for (j = 0; j < i; j++) { 3480 free_irq(iproc_cmicx_irqs[j], ctrl); 3481 } 3482 goto err_disable_msi; 3483 } 3484 } else 3485 #endif 3486 { 3487 ret = request_irq(ctrl->iLine, _isr, irq_flags, 3488 LINUX_KERNEL_BDE_NAME, ctrl); 3489 if (ret < 0) 3490 goto err_disable_msi; 3491 3492 if (unlikely(debug >= 1)) 3493 gprintk("%s(%d):device# = %d, irq_flags = %lu, irq = %d\n", 3494 __func__, __LINE__, d, 3495 irq_flags, ctrl->pci_device ? ctrl->pci_device->irq : ctrl->iLine); 3496 } 3497 } 3498 } 3499 return 0; 3500 3501 err_disable_msi: 3502 #ifdef CONFIG_PCI_MSI 3503 _msi_disconnect(ctrl); 3504 3505 msi_exit: 3506 #endif 3507 gprintk("could not request IRQ\n"); 3508 ctrl->isr = NULL; 3509 ctrl->isr_data = NULL; 3510 ctrl->isr2 = NULL; 3511 ctrl->isr2_data = NULL; 3512 3513 return -1; 3514 } 3515 3516 static int 3517 _interrupt_disconnect(int d) 3518 { 3519 bde_ctrl_t *ctrl; 3520 int isr2_dev; 3521 int isr_active; 3522 3523 isr2_dev = d & LKBDE_ISR2_DEV; 3524 d &= ~LKBDE_ISR2_DEV; 3525 3526 if (!VALID_DEVICE(d)) { 3527 return -1; 3528 } 3529 3530 if (debug >= 1) { 3531 gprintk("_interrupt_disconnect d %d\n", d); 3532 } 3533 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3534 gprintk("_interrupt_disconnect: Not PCI device %d, type %x\n", 3535 d, _devices[d].dev_type); 3536 return -1; 3537 } 3538 3539 ctrl = _devices + d; 3540 3541 isr_active = (ctrl->isr || ctrl->isr2) ? 1 : 0; 3542 3543 if (unlikely(debug > 1)) 3544 gprintk("%s: isr_active = %d\n", __func__, isr_active); 3545 3546 if (isr2_dev) { 3547 if (debug >= 1) { 3548 gprintk("disconnect secondary isr\n"); 3549 } 3550 ctrl->isr2 = NULL; 3551 ctrl->isr2_data = NULL; 3552 ctrl->fmask = 0; 3553 if (ctrl->isr) { 3554 /* Primary handler still active */ 3555 SYNC_IRQ(ctrl->iLine); 3556 return 0; 3557 } 3558 } else { 3559 if (debug >= 1) { 3560 gprintk("disconnect primary isr\n"); 3561 } 3562 ctrl->isr = NULL; 3563 ctrl->isr_data = NULL; 3564 if (ctrl->isr2) { 3565 /* Secondary handler still active */ 3566 SYNC_IRQ(ctrl->iLine); 3567 return 0; 3568 } 3569 } 3570 3571 if (isr_active) { 3572 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,84)) 3573 if (ctrl->use_msi >= PCI_USE_INT_MSIX) { 3574 int i; 3575 for (i = 0; i < ctrl->msix_cnt; i++) { 3576 if (unlikely(debug > 1)) { 3577 gprintk("%s(%d):device# = %d, irq = %d\n", 3578 __func__, __LINE__, d, ctrl->entries[i].vector); 3579 } 3580 free_irq(ctrl->entries[i].vector, ctrl); 3581 } 3582 } 3583 else 3584 #endif 3585 #if defined(IPROC_CMICD) && defined(CONFIG_OF) 3586 if (of_find_compatible_node(NULL, NULL, IPROC_CMICX_COMPATIBLE)) { 3587 int i; 3588 for (i = 0; i < IHOST_CMICX_MAX_INTRS; i++) { 3589 if (unlikely(debug > 1)) { 3590 gprintk("%s(%d):device# = %d, free_irq(%d)\n", 3591 __func__, __LINE__, d, iproc_cmicx_irqs[i]); 3592 } 3593 free_irq(iproc_cmicx_irqs[i], ctrl); 3594 } 3595 } else 3596 #endif 3597 { 3598 free_irq(ctrl->iLine, ctrl); 3599 } 3600 #ifdef CONFIG_PCI_MSI 3601 if (ctrl->use_msi >= PCI_USE_INT_MSI) { 3602 _msi_disconnect(ctrl); 3603 } 3604 #endif 3605 } 3606 3607 return 0; 3608 } 3609 3610 static uint32_t 3611 _iproc_ihost_read(int d, uint32_t addr) 3612 { 3613 uint32_t *mapaddr; 3614 uint32_t reg_val; 3615 mapaddr = IOREMAP(addr, sizeof(uint32_t)); 3616 if (mapaddr == NULL) { 3617 return -1; 3618 } 3619 reg_val = readl(mapaddr); 3620 iounmap(mapaddr); 3621 return reg_val; 3622 } 3623 3624 static int 3625 _iproc_ihost_write(int d, uint32_t addr, uint32_t data) 3626 { 3627 uint32_t *mapaddr; 3628 mapaddr = IOREMAP(addr, sizeof(uint32_t)); 3629 if (mapaddr == NULL) { 3630 return -1; 3631 } 3632 writel(data, mapaddr); 3633 iounmap(mapaddr); 3634 return 0; 3635 } 3636 3637 static uint32_t 3638 _iproc_read(int d, uint32_t addr) 3639 { 3640 if (!VALID_DEVICE(d)) { 3641 return -1; 3642 } 3643 3644 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3645 return -1; 3646 } 3647 3648 if (_devices[d].dev_type & BDE_AXI_DEV_TYPE) { 3649 if (IHOST_GICD_REG_ADDR_VALID(d, addr)) { 3650 return readl(IHOST_GICD_REG_ADDR_REMAP(d, addr)); 3651 } 3652 return _iproc_ihost_read(d, addr); 3653 } 3654 3655 return shbde_iproc_pci_read(&_devices[d].shbde, 3656 (void *)_devices[d].bde_dev.base_address1, 3657 addr); 3658 } 3659 3660 static int 3661 _iproc_write(int d, uint32_t addr, uint32_t data) 3662 { 3663 if (!VALID_DEVICE(d)) { 3664 return -1; 3665 } 3666 3667 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 3668 return -1; 3669 } 3670 3671 if (_devices[d].dev_type & BDE_AXI_DEV_TYPE) { 3672 if (IHOST_GICD_REG_ADDR_VALID(d, addr)) { 3673 writel(data, IHOST_GICD_REG_ADDR_REMAP(d, addr)); 3674 return 0; 3675 } 3676 return _iproc_ihost_write(d, addr, data); 3677 } 3678 3679 shbde_iproc_pci_write(&_devices[d].shbde, 3680 (void *)_devices[d].bde_dev.base_address1, 3681 addr, data); 3682 3683 return 0; 3684 } 3685 3686 static int 3687 _get_cmic_ver(int d , uint32_t *ver) 3688 { 3689 3690 unsigned int cap_base; 3691 uint32_t rval = 0; 3692 3693 if (!VALID_DEVICE(d)) { 3694 gprintk("%s: Invalid device index %d\n", __func__, d); 3695 return -1; 3696 } 3697 3698 if (!(_devices[d].dev_type & BDE_PCI_DEV_TYPE)) { 3699 gprintk("%s: Not PCI device %d, type %x\n", __func__, 3700 d, _devices[d].dev_type); 3701 return -1; 3702 } 3703 3704 /* Look for PCIe vendor-specific extended capability (VSEC) */ 3705 cap_base = PCI_EXT_CAP_START; 3706 while (cap_base) { 3707 pci_read_config_dword(_devices[d].pci_device, cap_base, &rval); 3708 if (rval == 0xffffffff) { 3709 /* Assume PCI HW read error */ 3710 gprintk("%s: PCI HW read error\n", __func__); 3711 return -1; 3712 } 3713 3714 if (PCI_EXT_CAP_ID(rval) == PCI_EXT_CAP_ID_VNDR) { 3715 break; 3716 } 3717 cap_base = PCI_EXT_CAP_NEXT(rval); 3718 } 3719 if (cap_base) { 3720 /* 3721 * VSEC layout: 3722 * 3723 * 0x00: PCI Express Extended Capability Header 3724 * 0x04: Vendor-Specific Header 3725 * 0x08: Vendor-Specific Register 1 3726 * 0x0c: Vendor-Specific Register 2 3727 * ... 3728 * 0x24: Vendor-Specific Register 8 3729 */ 3730 pci_read_config_dword(_devices[d].pci_device, cap_base + 8, &rval); 3731 if (unlikely(debug > 1)) 3732 gprintk("%s:Found VSEC = %u\n", __func__, rval); 3733 3734 /* Determine if CMICX */ 3735 rval = ((rval >> 12) & 0xf); 3736 *ver = rval; 3737 3738 return 0; 3739 } else { 3740 gprintk("%s:VSEC not found\n", __func__); 3741 } 3742 3743 return -1; 3744 } 3745 3746 #ifdef BCM_SAND_SUPPORT 3747 int 3748 lkbde_cpu_write(int d, uint32 addr, uint32 *buf) 3749 { 3750 #if defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__) 3751 *((uint32_t*)((uint8_t*)cpu_address + addr)) = *buf; 3752 #endif 3753 3754 return 0; 3755 } 3756 3757 int 3758 lkbde_cpu_read(int d, uint32 addr, uint32 *buf) 3759 { 3760 #if defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_GTO_BCM_CPU__) 3761 *buf = *((uint32_t*)((uint8_t*)cpu_address + addr)); 3762 #else 3763 *buf = (uint32_t)(-1); 3764 #endif 3765 3766 return 0; 3767 } 3768 3769 int 3770 lkbde_cpu_pci_register(int d) 3771 { 3772 bde_ctrl_t* ctrl; 3773 uint16 cmd = 0; 3774 3775 if (!VALID_DEVICE(d)) { 3776 return -1; 3777 } 3778 3779 ctrl = &_devices[d]; 3780 3781 /* enable device */ 3782 if (pci_enable_device(ctrl->pci_device)) { 3783 gprintk("Cannot enable pci device : vendor_id = %x, device_id = %x\n", 3784 ctrl->pci_device->vendor, ctrl->pci_device->device); 3785 } 3786 3787 /* Add PCI_COMMAND_MEMORY and PCI_COMMAND_MASTER */ 3788 pci_read_config_word(ctrl->pci_device, PCI_COMMAND, &cmd); 3789 if (!(cmd & PCI_COMMAND_MEMORY) || !(cmd & PCI_COMMAND_MASTER)) { 3790 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 3791 pci_write_config_word(ctrl->pci_device, PCI_COMMAND, cmd); 3792 } 3793 3794 switch (ctrl->bde_dev.device) { 3795 case GEDI_DEVICE_ID: 3796 /* Fix bar 0 address */ 3797 pci_write_config_byte(ctrl->pci_device, 0x13, 0x60); 3798 3799 /* Fix Max payload size */ 3800 pci_write_config_byte(ctrl->pci_device, 0x88, 0x2f); 3801 pci_write_config_byte(ctrl->pci_device, 0x89, 0x10); 3802 break; 3803 case BCM88750_DEVICE_ID: 3804 case BCM88753_DEVICE_ID: 3805 case BCM88755_DEVICE_ID: 3806 case BCM88770_DEVICE_ID: 3807 case BCM88773_DEVICE_ID: 3808 case BCM88774_DEVICE_ID: 3809 case BCM88775_DEVICE_ID: 3810 case BCM88776_DEVICE_ID: 3811 case BCM88777_DEVICE_ID: 3812 case BCM88950_DEVICE_ID: 3813 case BCM88953_DEVICE_ID: 3814 case BCM88954_DEVICE_ID: 3815 case BCM88955_DEVICE_ID: 3816 case BCM88956_DEVICE_ID: 3817 case BCM88752_DEVICE_ID: 3818 case BCM88772_DEVICE_ID: 3819 case BCM88952_DEVICE_ID: 3820 case ACP_PCI_DEVICE_ID: 3821 case BCM88650_DEVICE_ID: 3822 3823 case BCM88670_DEVICE_ID: 3824 case BCM88671_DEVICE_ID: 3825 case BCM88671M_DEVICE_ID: 3826 case BCM88672_DEVICE_ID: 3827 case BCM88673_DEVICE_ID: 3828 case BCM88674_DEVICE_ID: 3829 case BCM88675_DEVICE_ID: 3830 case BCM88675M_DEVICE_ID: 3831 case BCM88676_DEVICE_ID: 3832 case BCM88676M_DEVICE_ID: 3833 case BCM88677_DEVICE_ID: 3834 case BCM88678_DEVICE_ID: 3835 case BCM88679_DEVICE_ID: 3836 3837 case BCM88370_DEVICE_ID: 3838 case BCM88371_DEVICE_ID: 3839 case BCM88371M_DEVICE_ID: 3840 case BCM88375_DEVICE_ID: 3841 case BCM88376_DEVICE_ID: 3842 case BCM88376M_DEVICE_ID: 3843 case BCM88377_DEVICE_ID: 3844 case BCM88378_DEVICE_ID: 3845 case BCM88379_DEVICE_ID: 3846 case BCM88681_DEVICE_ID: 3847 case BCM88682_DEVICE_ID: 3848 case BCM88683_DEVICE_ID: 3849 case BCM88684_DEVICE_ID: 3850 case BCM88685_DEVICE_ID: 3851 case BCM88380_DEVICE_ID: 3852 case BCM88381_DEVICE_ID: 3853 case BCM88680_DEVICE_ID: 3854 case BCM88800_DEVICE_ID: 3855 case BCM88470_DEVICE_ID: 3856 case BCM88470P_DEVICE_ID: 3857 case BCM88471_DEVICE_ID: 3858 case BCM88473_DEVICE_ID: 3859 case BCM88474_DEVICE_ID: 3860 case BCM88474H_DEVICE_ID: 3861 case BCM88476_DEVICE_ID: 3862 case BCM88477_DEVICE_ID: 3863 case BCM88270_DEVICE_ID: 3864 case BCM88272_DEVICE_ID: 3865 case BCM88273_DEVICE_ID: 3866 case BCM88274_DEVICE_ID: 3867 case BCM88278_DEVICE_ID: 3868 case BCM8206_DEVICE_ID: 3869 case BCM88350_DEVICE_ID: 3870 case BCM88351_DEVICE_ID: 3871 case BCM88450_DEVICE_ID: 3872 case BCM88451_DEVICE_ID: 3873 case BCM88550_DEVICE_ID: 3874 case BCM88551_DEVICE_ID: 3875 case BCM88552_DEVICE_ID: 3876 case BCM88651_DEVICE_ID: 3877 case BCM88654_DEVICE_ID: 3878 case BCM88660_DEVICE_ID: 3879 case BCM88360_DEVICE_ID: 3880 case BCM88361_DEVICE_ID: 3881 case BCM88363_DEVICE_ID: 3882 case BCM88460_DEVICE_ID: 3883 case BCM88461_DEVICE_ID: 3884 case BCM88560_DEVICE_ID: 3885 case BCM88561_DEVICE_ID: 3886 case BCM88562_DEVICE_ID: 3887 case BCM88661_DEVICE_ID: 3888 case BCM88664_DEVICE_ID: 3889 /* Fix bar 0 address */ 3890 pci_write_config_byte(ctrl->pci_device, 0x12, 0x10); 3891 pci_write_config_byte(ctrl->pci_device, 0x13, 0x60); 3892 3893 /* 3894 * For DMA transactions - set Max_Payload_Size and 3895 * Max_Read_Request_Size to 128 bytes. 3896 */ 3897 pci_write_config_byte(ctrl->pci_device, 0xb5, 0x0c); 3898 pci_write_config_byte(ctrl->pci_device, 0xb4, 0x0); 3899 break; 3900 default: 3901 break; 3902 } 3903 3904 #ifdef BCM_DNX_SUPPORT 3905 /*All Jericho 2 devices from 0x8690 to 0x869F*/ 3906 if (SOC_IS_JERICHO_2_TYPE(ctrl->bde_dev.device)) { 3907 /* Fix bar 0 address */ 3908 pci_write_config_byte(ctrl->pci_device, 0x12, 0x10); 3909 pci_write_config_byte(ctrl->pci_device, 0x13, 0x60); 3910 3911 /* 3912 * For DMA transactions - set Max_Payload_Size and 3913 * Max_Read_Request_Size to 128 bytes. 3914 */ 3915 pci_write_config_byte(ctrl->pci_device, 0xb5, 0x0c); 3916 pci_write_config_byte(ctrl->pci_device, 0xb4, 0x0); 3917 } 3918 #endif 3919 3920 /* Redo ioremap */ 3921 if (ctrl->bde_dev.base_address) { 3922 iounmap((void *)ctrl->bde_dev.base_address); 3923 } 3924 ctrl->bde_dev.base_address = (sal_vaddr_t)IOREMAP(ctrl->phys_address, 0x1000000); 3925 3926 if (debug >= 1) { 3927 gprintk("%s, %s(): info:\n", __FILE__, __FUNCTION__); 3928 gprintk("_ndevices=%d, _switch_ndevices=%d\n", 3929 _ndevices, _switch_ndevices); 3930 gprintk("ctrl->dev_type=0x%x, ctrl->phys_address=0x%lx\n", 3931 ctrl->dev_type, (unsigned long)ctrl->phys_address); 3932 gprintk("ctrl->bde_dev.device=0x%x, ctrl->bde_dev.rev=0x%x, " 3933 "ctrl->bde_dev.base_address=0x%lx\n", 3934 ctrl->bde_dev.device, ctrl->bde_dev.rev, 3935 (unsigned long)ctrl->bde_dev.base_address); 3936 } 3937 3938 return 0; 3939 } 3940 3941 /* 3942 * Export Low level access function - currently for PCP DMA Kernel module. 3943 */ 3944 int 3945 lkbde_mem_write(int d, uint32 addr, uint32 *buf) 3946 { 3947 bde_ctrl_t* ctrl; 3948 void *full_addr; 3949 3950 if (!VALID_DEVICE(d)) return -1; 3951 ctrl = &_devices[d]; 3952 3953 full_addr = (void *)ctrl->bde_dev.base_address + addr; 3954 *((uint32_t*)full_addr) = *buf; 3955 return 0; 3956 } 3957 LKM_EXPORT_SYM(lkbde_mem_write); 3958 3959 int 3960 lkbde_mem_read(int d, uint32 addr, uint32 *buf) 3961 { 3962 bde_ctrl_t* ctrl; 3963 void *full_addr; 3964 3965 if (!VALID_DEVICE(d)) return -1; 3966 ctrl = &_devices[d]; 3967 3968 full_addr = (void *)ctrl->bde_dev.base_address + addr; 3969 *buf = *((uint32_t*)full_addr); 3970 return 0; 3971 } 3972 LKM_EXPORT_SYM(lkbde_mem_read); 3973 #endif /* BCM_SAND_SUPPORT */ 3974 3975 static ibde_t _ibde = { 3976 name: _name, 3977 num_devices: _num_devices, 3978 get_dev: _get_dev, 3979 get_dev_type: _get_dev_type, 3980 pci_conf_read: _pci_conf_read, 3981 pci_conf_write: _pci_conf_write, 3982 pci_bus_features: _pci_bus_features, 3983 read: _read, 3984 write: _write, 3985 salloc: _salloc, 3986 sfree: _sfree, 3987 sinval: _sinval, 3988 sflush: _sflush, 3989 interrupt_connect: _interrupt_connect, 3990 interrupt_disconnect: _interrupt_disconnect, 3991 l2p: _l2p, 3992 p2l: _p2l, 3993 3994 NULL, 3995 NULL, 3996 iproc_read: _iproc_read, 3997 iproc_write: _iproc_write, 3998 get_cmic_ver: _get_cmic_ver, 3999 }; 4000 4001 /* 4002 * Function: linux_bde_create 4003 * 4004 * Purpose: 4005 * Creator function for this BDE interface. 4006 * Parameters: 4007 * bus - pointer to the bus features structure you want this 4008 * bde to export. Depends on the system. 4009 * ibde - pointer to a location to recieve the bde interface pointer. 4010 * Returns: 4011 * 0 on success 4012 * -1 on failure. 4013 * Notes: 4014 * This is the main BDE create function for this interface. 4015 * Used by the external system initialization code. 4016 */ 4017 int 4018 linux_bde_create(linux_bde_bus_t *bus, ibde_t **ibde) 4019 { 4020 4021 memset(&_bus, 0, sizeof(_bus)); 4022 4023 if (bus) { 4024 _bus = *bus; 4025 } 4026 #ifdef NONCOHERENT_DMA_MEMORY 4027 #ifdef REMAP_DMA_NONCACHED 4028 /* 4029 * If we have a non-cached DMA memory pool 4030 * there is no need to flush and invalidate. 4031 */ 4032 if (_dma_pool_allocated()) { 4033 _ibde.sinval = NULL; 4034 _ibde.sflush = NULL; 4035 } 4036 #endif 4037 #else 4038 _ibde.sinval = NULL; 4039 _ibde.sflush = NULL; 4040 #endif 4041 *ibde = &_ibde; 4042 return 0; 4043 } 4044 4045 /* 4046 * Function: linux_bde_destroy 4047 * 4048 * Purpose: 4049 * destroy this bde 4050 * Parameters: 4051 * BDE interface pointer 4052 * Returns: 4053 * 0 on success, < 0 on error. 4054 */ 4055 int 4056 linux_bde_destroy(ibde_t *ibde) 4057 { 4058 /* nothing */ 4059 return 0; 4060 } 4061 4062 /* 4063 * Backdoors provided by the kernel bde 4064 */ 4065 4066 uint32_t 4067 lkbde_get_dev_phys(int d) 4068 { 4069 if (!VALID_DEVICE(d)) { 4070 return -1; 4071 } 4072 4073 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4074 gprintk("lkbde_get_dev_phys: Not PCI device %d, type %x\n", 4075 d, _devices[d].dev_type); 4076 return 0; 4077 } 4078 return _devices[d].phys_address; 4079 } 4080 4081 uint32_t 4082 lkbde_get_dev_phys_hi(int d) 4083 { 4084 if (!VALID_DEVICE(d)) { 4085 return -1; 4086 } 4087 4088 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4089 gprintk("lkbde_get_dev_phys: Not PCI device %d, type %x\n", 4090 d, _devices[d].dev_type); 4091 return 0; 4092 } 4093 #ifdef PHYS_ADDR_IS_64BIT 4094 return (uint32_t)(_devices[d].phys_address >> 32); 4095 #else 4096 return 0; 4097 #endif 4098 } 4099 4100 void * 4101 lkbde_get_dev_virt(int d) 4102 { 4103 if (!VALID_DEVICE(d)) { 4104 return NULL; 4105 } 4106 4107 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4108 gprintk("lkbde_get_dev_virt: Not PCI device %d, type %x\n", 4109 d, _devices[d].dev_type); 4110 return 0; 4111 } 4112 4113 if (_devices[d].alt_base_addr) { 4114 return (void *)_devices[d].alt_base_addr; 4115 } 4116 4117 return (void *)_devices[d].bde_dev.base_address; 4118 } 4119 4120 int 4121 lkbde_get_dev_resource(int d, int rsrc, uint32_t *flags, 4122 uint32_t *phys_lo, uint32_t *phys_hi) 4123 { 4124 if (!VALID_DEVICE(d)) { 4125 return -1; 4126 } 4127 4128 *flags = 0; 4129 *phys_lo = 0; 4130 *phys_hi = 0; 4131 4132 if (!(BDE_DEV_MEM_MAPPED(_devices[d].dev_type))) { 4133 gprintk("lkbde_get_dev_phys: Not PCI device %d, type %x\n", 4134 d, _devices[d].dev_type); 4135 return 0; 4136 } 4137 4138 switch (rsrc) { 4139 case 0: 4140 *phys_lo = (uint32_t)(_devices[d].phys_address); 4141 #ifdef PHYS_ADDR_IS_64BIT 4142 *phys_hi = (uint32_t)(_devices[d].phys_address >> 32); 4143 #endif 4144 break; 4145 case 1: 4146 *phys_lo = (uint32_t)(_devices[d].phys_address1); 4147 #ifdef PHYS_ADDR_IS_64BIT 4148 *phys_hi = (uint32_t)(_devices[d].phys_address1 >> 32); 4149 #endif 4150 break; 4151 default: 4152 break; 4153 } 4154 4155 return 0; 4156 } 4157 4158 void * 4159 lkbde_get_dma_dev(int d) 4160 { 4161 if (!VALID_DEVICE(d)) { 4162 return NULL; 4163 } 4164 4165 #ifdef LINUX_BDE_DMA_DEVICE_SUPPORT 4166 return (void *)_devices[d].dma_dev; 4167 #else 4168 return (void *)_devices[d].pci_device; 4169 #endif 4170 } 4171 4172 void * 4173 lkbde_get_hw_dev(int d) 4174 { 4175 if (!VALID_DEVICE(d)) { 4176 return NULL; 4177 } 4178 4179 return (void *)_devices[d].pci_device; 4180 } 4181 4182 int 4183 lkbde_dev_state_set(int d, uint32 state) 4184 { 4185 bde_ctrl_t *ctrl; 4186 4187 if (!VALID_DEVICE(d)) { 4188 return -1; 4189 } 4190 ctrl = _devices + d; 4191 ctrl->dev_state = state; 4192 return 0; 4193 } 4194 4195 int 4196 lkbde_dev_state_get(int d, uint32 *state) 4197 { 4198 bde_ctrl_t *ctrl; 4199 if (!VALID_DEVICE(d)) { 4200 gprintk("_get_dev: Invalid device index %d\n", d); 4201 return -1; 4202 } 4203 ctrl = _devices + d; 4204 4205 *state = ctrl->dev_state; 4206 return 0; 4207 } 4208 4209 int 4210 lkbde_dev_instid_set(int d, uint32 instid) 4211 { 4212 bde_ctrl_t *ctrl; 4213 4214 if (!VALID_DEVICE(d)) { 4215 return -1; 4216 } 4217 ctrl = _devices + d; 4218 ctrl->inst_id = instid; 4219 4220 return 0; 4221 } 4222 4223 int 4224 lkbde_dev_instid_get(int d, uint32 *instid) 4225 { 4226 bde_ctrl_t *ctrl; 4227 4228 if (!VALID_DEVICE(d)) { 4229 return -1; 4230 } 4231 ctrl = _devices + d; 4232 *instid = ctrl->inst_id; 4233 4234 return 0; 4235 } 4236 /* 4237 * When a secondary interrupt handler is installed this function 4238 * is used for synchronizing hardware access to the IRQ mask 4239 * register. The secondary driver will supply a non-zero fmask 4240 * (filter mask) to indicate which interrupt bits it controls. 4241 * The fmask is ignored for the primary driver. 4242 */ 4243 int 4244 lkbde_irq_mask_set(int d, uint32_t addr, uint32_t mask, uint32_t fmask) 4245 { 4246 bde_ctrl_t *ctrl; 4247 int isr2_dev, iproc_reg; 4248 unsigned long flags; 4249 4250 isr2_dev = d & LKBDE_ISR2_DEV; 4251 iproc_reg = d & LKBDE_IPROC_REG; 4252 d &= ~(LKBDE_ISR2_DEV | LKBDE_IPROC_REG); 4253 4254 if (!VALID_DEVICE(d)) { 4255 return -1; 4256 } 4257 4258 ctrl = _devices + d; 4259 4260 /* Lock is required to synchronize access from user space */ 4261 spin_lock_irqsave(&ctrl->lock, flags); 4262 4263 if (isr2_dev) { 4264 /* This is the secondary interrupt handler */ 4265 ctrl->fmask = fmask; 4266 ctrl->imask2 = mask & ctrl->fmask; 4267 } else { 4268 /* This is the primary interrupt handler */ 4269 ctrl->imask = mask & ~ctrl->fmask; 4270 } 4271 4272 if (iproc_reg) { 4273 _iproc_write(d, addr, ctrl->imask | ctrl->imask2); 4274 } else { 4275 _write(d, addr, ctrl->imask | ctrl->imask2); 4276 } 4277 4278 spin_unlock_irqrestore(&ctrl->lock, flags); 4279 4280 return 0; 4281 } 4282 4283 /* 4284 * When a secondary interrupt handler is installed, this function 4285 * is used to avoid activating the user mode interrupt handler 4286 * thread if all pending interrupts are handled in kernel space. 4287 * 4288 * The mask returned is the mask of all interrupts, it can be used 4289 * to do a logical AND with fmask, the result will tell you if 4290 * the user mode interrupt handler needs to be invoked. 4291 * 4292 * Note that if no secondary handler is installed, the value of 4293 * "mask & fmask" will be zero, and hence there will be no need to read the 4294 * current interrupt status from hardware (from kernel space). 4295 */ 4296 int 4297 lkbde_irq_mask_get(int d, uint32_t *mask, uint32_t *fmask) 4298 { 4299 bde_ctrl_t *ctrl; 4300 4301 d &= ~(LKBDE_ISR2_DEV | LKBDE_IPROC_REG); 4302 4303 if (!VALID_DEVICE(d)) { 4304 return -1; 4305 } 4306 4307 if (mask == NULL || fmask == NULL) { 4308 return -1; 4309 } 4310 4311 ctrl = _devices + d; 4312 4313 *fmask = ctrl->fmask; 4314 *mask = ctrl->imask | ctrl->imask2; 4315 4316 return 0; 4317 } 4318 4319 int 4320 lkbde_get_num_devices(int type) 4321 { 4322 return _num_devices(type); 4323 } 4324 4325 /* 4326 * Export functions 4327 */ 4328 LKM_EXPORT_SYM(linux_bde_create); 4329 LKM_EXPORT_SYM(linux_bde_destroy); 4330 LKM_EXPORT_SYM(lkbde_get_dev_phys); 4331 LKM_EXPORT_SYM(lkbde_get_dev_virt); 4332 LKM_EXPORT_SYM(lkbde_get_dev_resource); 4333 LKM_EXPORT_SYM(lkbde_get_hw_dev); 4334 LKM_EXPORT_SYM(lkbde_get_dma_dev); 4335 LKM_EXPORT_SYM(lkbde_irq_mask_set); 4336 LKM_EXPORT_SYM(lkbde_irq_mask_get); 4337 LKM_EXPORT_SYM(lkbde_get_dev_phys_hi); 4338 LKM_EXPORT_SYM(lkbde_dev_state_set); 4339 LKM_EXPORT_SYM(lkbde_dev_state_get); 4340 LKM_EXPORT_SYM(lkbde_dev_instid_set); 4341 LKM_EXPORT_SYM(lkbde_dev_instid_get); 4342 #ifdef BCM_SAND_SUPPORT 4343 LKM_EXPORT_SYM(lkbde_cpu_write); 4344 LKM_EXPORT_SYM(lkbde_cpu_read); 4345 LKM_EXPORT_SYM(lkbde_cpu_pci_register); 4346 #endif