pm_qtc.c (98014B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <soc/types.h> 11 #include <soc/error.h> 12 #include <soc/wb_engine.h> 13 #include <soc/portmod/portmod_internal.h> 14 #include <soc/portmod/portmod.h> 15 #include <soc/portmod/portmod_common.h> 16 #include <soc/portmod/portmod_dispatch.h> 17 #include <soc/portmod/portmod_chain.h> 18 #include <soc/portmod/portmod_system.h> 19 20 #include <soc/portmod/unimac.h> 21 #include <soc/portmod/pm_qtc.h> 22 23 #ifdef _ERR_MSG_MODULE_NAME 24 #error "_ERR_MSG_MODULE_NAME redefined" 25 #endif 26 #define _ERR_MSG_MODULE_NAME BSL_LS_SOC_PORT 27 28 #ifdef PORTMOD_PM_QTC_SUPPORT 29 30 /* 10G mode at 10.3125G and 1G mode at 1.25G */ 31 #define PM_QTC_LANES_PER_CORE (16) 32 #define MAX_PORTS_PER_PM_QTC (16) 33 34 #define PM_QTC_INFO(pm_info) ((pm_info)->pm_data.pm_qtc_db) 35 36 #define PM_QTC_PHY_ACCESS_GET(unit, port, pm_info, phy_acc) \ 37 do { \ 38 uint32 is_bypass; \ 39 phy_acc = 0; \ 40 SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isBypassed], &is_bypass); \ 41 phy_acc = (is_bypass && PM_QTC_INFO(pm_info)->first_phy != -1) ? (PM_QTC_INFO(pm_info)->first_phy | SOC_REG_ADDR_PHY_ACC_MASK) : port; \ 42 } while (0) 43 44 #define PM_QTC_PORT_NUM_TO_PHY_ACCESS(_ac,_nphy,_p) \ 45 do { \ 46 int i; \ 47 for (i = 0; i < (_nphy); i++) { \ 48 PORTMOD_USER_ACC_LPORT_SET(&((_ac)[i].access), (_p)); \ 49 } \ 50 } while(0) 51 52 extern int pm_qtc_phy_control_set(phymod_phy_access_t *phy_access, int chain_len, soc_phy_control_t type, phymod_tx_t*, uint32, uint32 v); 53 /*extern int pm_qtc_phy_control_get(int u, soc_port_t p, pm_info_t pm, soc_phy_control_t type, phymod_tx_t*, uint32, uint32 *v);*/ 54 extern int pm_qtc_phy_control_get(phymod_phy_access_t *phy_access, int chain_len, soc_phy_control_t type, phymod_tx_t*, uint32, uint32 *v); 55 56 /* Warm Boot Variables to indicate the boot state */ 57 typedef enum pm_qtc_fabric_wb_vars{ 58 isInitialized, 59 isActive, 60 isBypassed, 61 ports, 62 threePortsMode, 63 phy_type 64 }pm_qtc_wb_vars_t; 65 66 67 typedef struct pm_qtc_port_s { 68 portmod_port_interface_config_t interface_config; 69 portmod_port_init_config_t port_init_config; 70 phymod_phy_init_config_t phy_init_config; 71 phymod_phy_inf_config_t phy_interface_config; 72 } pm_qtc_port_t; 73 74 struct pm_qtc_s{ 75 portmod_pbmp_t phys; 76 int first_phy; 77 phymod_ref_clk_t ref_clk; 78 phymod_polarity_t polarity; 79 phymod_lane_map_t lane_map; 80 phymod_firmware_load_method_t fw_load_method; 81 phymod_firmware_loader_f external_fw_loader; 82 phymod_core_access_t core_access[1 + MAX_PHYN]; 83 uint32 first_phy_lane[1 + MAX_PHYN]; /* need one less, keep in line with core_access index. */ 84 int nof_phys; /* internal + External Phys */ 85 pm_qtc_port_t port_config[PM_QTC_LANES_PER_CORE]; 86 uint8 default_fw_loader_is_used; 87 uint8 default_bus_is_used; 88 portmod_phy_external_reset_f portmod_phy_external_reset; 89 portmod_mac_soft_reset_f portmod_mac_soft_reset; 90 int core_num; 91 int core_num_int; /* 0, 1, 2 for TSC12 * - leaving it here, in case we add gphy here */ 92 }; 93 94 #define PM_QTC_QUAD_MODE_IF(interface) \ 95 (interface == SOC_PORT_IF_CAUI || \ 96 interface == SOC_PORT_IF_XLAUI || \ 97 interface == SOC_PORT_IF_DNX_XAUI) 98 99 #define PM_QTC_DUAL_MODE_IF(interface) \ 100 (interface == SOC_PORT_IF_RXAUI) 101 102 STATIC 103 int pm_qtc_port_soft_reset(int unit, int port, pm_info_t pm_info, int enable); 104 105 int pm_qtc_pm_interface_type_is_supported(int unit, soc_port_if_t interface, 106 int* is_supported) 107 { 108 SOC_INIT_FUNC_DEFS; 109 switch(interface){ 110 case SOC_PORT_IF_SGMII: 111 case SOC_PORT_IF_QSGMII: 112 case SOC_PORT_IF_GMII: 113 case SOC_PORT_IF_XFI: 114 *is_supported = TRUE; 115 break; 116 default: 117 *is_supported = FALSE; 118 break; 119 } 120 SOC_FUNC_RETURN; 121 } 122 123 STATIC 124 int _pm_qtc_port_index_get(int unit, int port, pm_info_t pm_info, 125 int *first_index, uint32 *bitmap) 126 { 127 int i, rv = 0, tmp_port = 0; 128 129 SOC_INIT_FUNC_DEFS; 130 131 *first_index = -1; 132 *bitmap = 0; 133 134 for( i = 0 ; i < MAX_PORTS_PER_PM_QTC; i++) { 135 rv = SOC_WB_ENGINE_GET_ARR (unit, SOC_WB_ENGINE_PORTMOD, 136 pm_info->wb_vars_ids[ports], &tmp_port, i); 137 _SOC_IF_ERR_EXIT(rv); 138 139 if(tmp_port == port){ 140 *first_index = (*first_index == -1 ? i : *first_index); 141 SHR_BITSET(bitmap, i); 142 } 143 } 144 145 if(*first_index == -1) { 146 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, 147 (_SOC_MSG("port was not found in internal DB %d"), port)); 148 } 149 150 exit: 151 SOC_FUNC_RETURN; 152 } 153 154 /* 155 * Initialize the buffer to support warmboot 156 * The state of warmboot is store in the variables like 157 * isInitialized, isActive, isBypassed, ports.. etc., 158 * All of these variables need to be added to warmboot 159 * any variables added to save the state of warmboot should be 160 * included here. 161 */ 162 STATIC 163 int pm_qtc_wb_buffer_init(int unit, int wb_buffer_index, pm_info_t pm_info) 164 { 165 /* Declare the common variables needed for warmboot */ 166 WB_ENGINE_INIT_TABLES_DEFS; 167 int wb_var_id, rv=0; 168 int buffer_id = wb_buffer_index; /*required by SOC_WB_ENGINE_ADD_ Macros*/ 169 SOC_INIT_FUNC_DEFS; 170 171 COMPILER_REFERENCE(buffer_is_dynamic); 172 173 SOC_WB_ENGINE_ADD_BUFF(SOC_WB_ENGINE_PORTMOD, wb_buffer_index, "pm_qtc", NULL, NULL, VERSION(1), 1, SOC_WB_ENGINE_PRE_RELEASE); 174 _SOC_IF_ERR_EXIT(rv); 175 176 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 177 SOC_WB_ENGINE_ADD_VAR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "is_initialized", wb_buffer_index, sizeof(uint32), NULL, VERSION(1)); 178 _SOC_IF_ERR_EXIT(rv); 179 pm_info->wb_vars_ids[isInitialized] = wb_var_id; 180 181 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 182 SOC_WB_ENGINE_ADD_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "ports", wb_buffer_index, sizeof(int), NULL, MAX_PORTS_PER_PM_QTC, VERSION(1)); 183 _SOC_IF_ERR_EXIT(rv); 184 pm_info->wb_vars_ids[ports] = wb_var_id; 185 186 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 187 SOC_WB_ENGINE_ADD_VAR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "is_active", wb_buffer_index, sizeof(uint32), NULL, VERSION(1)); 188 _SOC_IF_ERR_EXIT(rv); 189 pm_info->wb_vars_ids[isActive] = wb_var_id; 190 191 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 192 SOC_WB_ENGINE_ADD_VAR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "is_bypassed", wb_buffer_index, sizeof(uint32), NULL, VERSION(1)); 193 _SOC_IF_ERR_EXIT(rv); 194 pm_info->wb_vars_ids[isBypassed] = wb_var_id; 195 196 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 197 SOC_WB_ENGINE_ADD_VAR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "three_ports_mode", wb_buffer_index, sizeof(uint32), NULL, VERSION(1)); 198 _SOC_IF_ERR_EXIT(rv); 199 pm_info->wb_vars_ids[threePortsMode] = wb_var_id; 200 201 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 202 SOC_WB_ENGINE_ADD_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "phy_type", wb_buffer_index, sizeof(int), NULL, MAX_PORTS_PER_PM_QTC, VERSION(1)); 203 _SOC_IF_ERR_EXIT(rv); 204 pm_info->wb_vars_ids[phy_type] = wb_var_id; 205 206 207 _SOC_IF_ERR_EXIT(soc_wb_engine_init_buffer(unit, SOC_WB_ENGINE_PORTMOD, wb_buffer_index, FALSE)); 208 if(!SOC_WARM_BOOT(unit)){ 209 rv = SOC_WB_ENGINE_MEMSET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[ports], -1); 210 _SOC_IF_ERR_EXIT(rv); 211 } 212 213 214 exit: 215 SOC_FUNC_RETURN 216 217 218 } 219 220 STATIC portmod_ucode_buf_t pm_qtc_ucode_buf[SOC_MAX_NUM_DEVICES] = {{NULL, 0}}; 221 222 int pm_qtc_pm_destroy(int unit, pm_info_t pm_info) 223 { 224 if(pm_info->pm_data.pm_qtc_db != NULL) { 225 sal_free(pm_info->pm_data.pm_qtc_db); 226 pm_info->pm_data.pm_qtc_db = NULL; 227 } 228 229 /* free pm_qtc_ucode_buf */ 230 if(pm_qtc_ucode_buf[unit].ucode_dma_buf != NULL){ 231 portmod_sys_dma_free(unit, pm_qtc_ucode_buf[unit].ucode_dma_buf); 232 pm_qtc_ucode_buf[unit].ucode_dma_buf = NULL; 233 } 234 pm_qtc_ucode_buf[unit].ucode_alloc_size = 0; 235 236 return SOC_E_NONE; 237 } 238 239 STATIC int 240 pm_qtc_default_fw_loader(const phymod_core_access_t* core, uint32_t length, const uint8_t* data) 241 { 242 243 int rv; 244 portmod_default_user_access_t *user_data; 245 int unit = ((portmod_default_user_access_t*)core->access.user_acc)->unit; 246 portmod_ucode_buf_order_t load_order; 247 SOC_INIT_FUNC_DEFS; 248 249 user_data = (portmod_default_user_access_t*)core->access.user_acc; 250 /* user_data->blk_id = user_data->blk_id | SOC_REG_ADDR_BLOCK_ID_MASK; */ 251 252 if (PORTMOD_USER_ACCESS_FW_LOAD_REVERSE_GET(user_data)) { 253 load_order = portmod_ucode_buf_order_reversed; 254 } else { 255 load_order = portmod_ucode_buf_order_straight; 256 } 257 258 rv = portmod_firmware_set(unit, 259 user_data->blk_id, 260 data, 261 length, 262 load_order, 263 0, 264 &(pm_qtc_ucode_buf[unit]), 265 NULL, 266 GPORT_WC_UCMEM_DATAm, 267 GPORT_WC_UCMEM_CTRLr ); 268 _SOC_IF_ERR_EXIT(rv); 269 270 exit: 271 SOC_FUNC_RETURN; 272 273 } 274 275 STATIC 276 int 277 pm_qtc_default_bus_write(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t val) 278 { 279 return portmod_common_phy_sbus_reg_write(GPORT_WC_UCMEM_DATAm, user_acc, core_addr, reg_addr, val); 280 } 281 282 STATIC 283 int 284 pm_qtc_default_bus_read(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t *val) 285 { 286 return portmod_common_phy_sbus_reg_read(GPORT_WC_UCMEM_DATAm, user_acc, core_addr, reg_addr, val); 287 } 288 289 int pm_qtc_port_soft_reset_toggle(int unit, int port, pm_info_t pm_info, int idx) 290 { 291 int phy_acc; 292 uint32 reg_val, old_val; 293 294 SOC_INIT_FUNC_DEFS; 295 296 PM_QTC_PHY_ACCESS_GET(unit, port, pm_info, phy_acc); 297 298 _SOC_IF_ERR_EXIT(READ_COMMAND_CONFIGr(unit, phy_acc, ®_val)); 299 old_val = reg_val; 300 301 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_RESETf, 1); 302 303 _SOC_IF_ERR_EXIT(WRITE_COMMAND_CONFIGr(unit, phy_acc, reg_val)); 304 _SOC_IF_ERR_EXIT(WRITE_COMMAND_CONFIGr(unit, phy_acc, old_val)); 305 306 exit: 307 SOC_FUNC_RETURN; 308 } 309 310 phymod_bus_t pm_qtc_default_bus = { 311 "PM_QTC Bus", 312 pm_qtc_default_bus_read, 313 pm_qtc_default_bus_write, 314 NULL, 315 portmod_common_mutex_take, 316 portmod_common_mutex_give, 317 NULL, 318 NULL, 319 PHYMOD_BUS_CAP_WR_MODIFY | PHYMOD_BUS_CAP_LANE_CTRL 320 }; 321 322 int pm_qtc_pm_init(int unit, 323 const portmod_pm_create_info_internal_t* pm_add_info, 324 int wb_buffer_index, pm_info_t pm_info) 325 { 326 327 const portmod_pm_qtc_create_info_t *info; 328 pm_qtc_t pm_qtc_data = NULL; 329 int i, pm_is_active, rv ; 330 SOC_INIT_FUNC_DEFS; 331 332 info = &pm_add_info->pm_specific_info.pm_qtc; 333 pm_qtc_data = sal_alloc(sizeof(struct pm_qtc_s), "pm_qtc_specific_db"); 334 SOC_NULL_CHECK(pm_qtc_data); 335 336 pm_info->type = portmodDispatchTypePm_qtc; 337 pm_info->unit = unit; 338 pm_info->wb_buffer_id = wb_buffer_index; 339 pm_info->pm_data.pm_qtc_db = pm_qtc_data; 340 PORTMOD_PBMP_ASSIGN(pm_qtc_data->phys, pm_add_info->phys); 341 pm_qtc_data->core_access[0].type = phymodDispatchTypeInvalid; 342 pm_qtc_data->default_bus_is_used = 0; 343 pm_qtc_data->default_fw_loader_is_used = 0; 344 pm_qtc_data->portmod_phy_external_reset = pm_add_info->pm_specific_info.pm_qtc.portmod_phy_external_reset; 345 pm_qtc_data->portmod_mac_soft_reset = pm_add_info->pm_specific_info.pm_qtc.portmod_mac_soft_reset; 346 pm_qtc_data->first_phy = -1; 347 348 pm_qtc_data->nof_phys = 0; 349 /* YTU why MAX_PHYN= 3? should it be just one core */ 350 for(i = 0 ; i < MAX_PHYN + 1; i++){ /* only one phy */ 351 phymod_core_access_t_init(&pm_qtc_data->core_access[i]); 352 pm_qtc_data->first_phy_lane[i] = 0; 353 } 354 355 if(info->ref_clk != phymodRefClk156Mhz && info->ref_clk != phymodRefClk125Mhz) { 356 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("illegal ref clock"))); 357 } 358 if(info->lane_map.num_of_lanes != PM_QTC_LANES_PER_CORE){ 359 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 360 (_SOC_MSG("lanes map length should be 4"))); 361 } 362 _SOC_IF_ERR_EXIT(phymod_firmware_load_method_t_validate( 363 info->fw_load_method)); 364 365 sal_memcpy(&pm_qtc_data->polarity, &info->polarity, 366 sizeof(phymod_polarity_t)); 367 sal_memcpy(&(pm_qtc_data->core_access[0].access), &info->access, 368 sizeof(phymod_access_t)); 369 sal_memcpy(&pm_qtc_data->lane_map, &info->lane_map, 370 sizeof(pm_qtc_data->lane_map)); 371 pm_qtc_data->ref_clk = info->ref_clk; 372 pm_qtc_data->fw_load_method = info->fw_load_method; 373 pm_qtc_data->external_fw_loader = info->external_fw_loader; 374 375 if(info->access.bus == NULL) { 376 /* if null - use default */ 377 pm_qtc_data->core_access[0].access.bus = &pm_qtc_default_bus; 378 pm_qtc_data->default_bus_is_used = 1; 379 } 380 381 if(pm_qtc_data->external_fw_loader == NULL) { 382 /* if null - use default */ 383 pm_qtc_data->external_fw_loader = pm_qtc_default_fw_loader; 384 pm_qtc_data->default_fw_loader_is_used = 1; 385 } 386 387 pm_qtc_data->nof_phys = 1; 388 389 pm_qtc_data->core_num = info->core_num; 390 /*init wb buffer*/ 391 _SOC_IF_ERR_EXIT(pm_qtc_wb_buffer_init(unit, wb_buffer_index, pm_info)); 392 393 394 if(SOC_WARM_BOOT(unit)){ 395 for( i = 0 ; i < MAX_PORTS_PER_PM_QTC; i++) { 396 rv = SOC_WB_ENGINE_GET_ARR (unit, SOC_WB_ENGINE_PORTMOD, 397 pm_info->wb_vars_ids[phy_type], &pm_qtc_data->core_access[i].type, i); 398 _SOC_IF_ERR_EXIT(rv); 399 400 } 401 } 402 403 if(!SOC_WARM_BOOT(unit)){ 404 405 pm_is_active = 0; 406 rv = SOC_WB_ENGINE_SET_VAR (unit, SOC_WB_ENGINE_PORTMOD, 407 pm_info->wb_vars_ids[isActive], &pm_is_active); 408 _SOC_IF_ERR_EXIT(rv); 409 410 /* 411 rv = SOC_WB_ENGINE_SET_VAR (unit, SOC_WB_ENGINE_PORTMOD, 412 pm_info->wb_vars_ids[isBypassed], 0); 413 _SOC_IF_ERR_EXIT(rv); 414 415 rv = SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, 416 pm_info->wb_vars_ids[threePortsMode], 0); 417 _SOC_IF_ERR_EXIT(rv); 418 419 rv = SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, 420 pm_info->wb_vars_ids[threePortsMode], 0); 421 _SOC_IF_ERR_EXIT(rv); 422 */ 423 424 425 } 426 427 exit: 428 if(SOC_FUNC_ERROR){ 429 pm_qtc_pm_destroy(unit, pm_info); 430 } 431 SOC_FUNC_RETURN; 432 } 433 434 int 435 pm_qtc_default_bus_update(int unit, pm_info_t pm_info, const portmod_bus_update_t* update) 436 { 437 return SOC_E_NONE; 438 } 439 440 STATIC 441 int _pm_qtc_tsc_reset(int unit, pm_info_t pm_info, int port, int in_reset) 442 { 443 uint32 reg_val; 444 int phy_acc; 445 portmod_default_user_access_t *user_data; 446 phymod_core_access_t* core; 447 448 SOC_INIT_FUNC_DEFS; 449 450 core = (PM_QTC_INFO(pm_info)->core_access); 451 user_data = (portmod_default_user_access_t*)core->access.user_acc; 452 453 /* PM_QTC_PHY_ACCESS_GET(unit, port, pm_info, phy_acc); */ 454 phy_acc = user_data->blk_id | SOC_REG_ADDR_BLOCK_ID_MASK; 455 456 457 458 if(in_reset) { 459 _SOC_IF_ERR_EXIT(READ_GPORT_XGXS0_CTRL_REGr(unit, phy_acc, ®_val)); 460 /* 461 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, IDDQf, 1); 462 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, PLLBYPf, 0); 463 */ 464 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, PWRDWNf, 1); 465 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, REFIN_ENf, 0); 466 /* soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, REFOUT_ENf, 0); */ 467 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, RSTB_HWf, 0); 468 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, RSTB_PLLf, 0); 469 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, RSTB_REFCLKf, 0); 470 /* soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, TSCCLK_ENf, 1); */ 471 _SOC_IF_ERR_EXIT(WRITE_GPORT_XGXS0_CTRL_REGr(unit, phy_acc, reg_val)); 472 } else { 473 _SOC_IF_ERR_EXIT(READ_GPORT_XGXS0_CTRL_REGr(unit, phy_acc, ®_val)); 474 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, IDDQf, 0); 475 /* soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, PLLBYPf, 0); */ 476 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, PWRDWNf, 0); 477 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, REFIN_ENf, 1); 478 /* soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, REFOUT_ENf, 1); */ 479 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, RSTB_HWf, 1); 480 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, RSTB_PLLf, 1); 481 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, RSTB_REFCLKf, 1); 482 soc_reg_field_set(unit, GPORT_XGXS0_CTRL_REGr, ®_val, TSCCLK_ENf, 1); 483 _SOC_IF_ERR_EXIT(WRITE_GPORT_XGXS0_CTRL_REGr(unit, phy_acc, reg_val)); 484 } 485 486 exit: 487 488 SOC_FUNC_RETURN; 489 } 490 491 #if 0 492 static int _xlport_mode_get(int unit, int phy_acc, int bindex, 493 portmod_core_port_mode_t *core_mode, int *cur_lanes) 494 { 495 496 return SOC_E_NONE; 497 498 } 499 500 static int _xlport_mode_set(int unit, int phy_acc, portmod_core_port_mode_t cur_mode) 501 { 502 503 504 return SOC_E_NONE; 505 } 506 507 static int _gport_lag_failover_status_toggle(int unit, pm_info_t pm_info, int port) 508 { 509 510 uint32_t rval; 511 int phy_acc; 512 portmod_default_user_access_t *user_data; 513 phymod_core_access_t* core; 514 515 SOC_INIT_FUNC_DEFS; 516 517 core = (PM_QTC_INFO(pm_info)->core_access); 518 user_data = (portmod_default_user_access_t*)core->access.user_acc; 519 520 /* PM_QTC_PHY_ACCESS_GET(unit, port, pm_info, phy_acc); */ 521 phy_acc = user_data->blk_id | SOC_REG_ADDR_BLOCK_ID_MASK; 522 523 /* Toggle link bit to notify IPIPE on link up */ 524 _SOC_IF_ERR_EXIT(READ_PGW_GE_LAG_FAILOVER_CONFIGr(unit, phy_acc, &rval)); 525 soc_reg_field_set(unit, PGW_GE_LAG_FAILOVER_CONFIGr, &rval, LINK_STATUS_UPf, 1); 526 _SOC_IF_ERR_EXIT(WRITE_PGW_GE_LAG_FAILOVER_CONFIGr(unit, phy_acc, rval)); 527 soc_reg_field_set(unit, PGW_GE_LAG_FAILOVER_CONFIGr, &rval, LINK_STATUS_UPf, 0); 528 _SOC_IF_ERR_EXIT(WRITE_PGW_GE_LAG_FAILOVER_CONFIGr(unit, phy_acc, rval)); 529 530 exit: 531 532 SOC_FUNC_RETURN; 533 534 } 535 536 #endif 537 538 int pm_qtc_port_cntmaxsize_get(int unit, int port, pm_info_t pm_info, int *val) 539 { 540 return SOC_E_NONE; 541 542 } 543 544 int pm_qtc_port_cntmaxsize_set(int unit, int port, pm_info_t pm_info, int val) 545 { 546 547 return SOC_E_NONE; 548 } 549 550 int pm_qtc_port_modid_set (int unit, int port, pm_info_t pm_info, int value) 551 { 552 return SOC_E_NONE; 553 554 } 555 556 int pm_qtc_port_encap_set (int unit, int port, pm_info_t pm_info, 557 int flags, portmod_encap_t encap) 558 { 559 return (unimac_encap_set(unit, port, encap)); 560 561 } 562 563 int pm_qtc_port_encap_get (int unit, int port, pm_info_t pm_info, 564 int *flags, portmod_encap_t *encap) 565 { 566 return (unimac_encap_get(unit, port, encap)); 567 568 } 569 570 int pm_qtc_port_config_port_type_set (int unit, int port, pm_info_t pm_info, int type) 571 { 572 return SOC_E_NONE; 573 574 } 575 576 int pm_qtc_port_config_port_type_get (int unit, int port, pm_info_t pm_info, int *type) 577 { 578 return SOC_E_NONE; 579 580 } 581 582 int pm_qtc_port_led_chain_config (int unit, int port, pm_info_t pm_info, 583 int value) 584 { 585 return SOC_E_NONE; 586 587 } 588 589 typedef enum unimac_port_mode_e{ 590 XLMAC_4_LANES_SEPARATE = 0, 591 XLMAC_3_TRI_0_1_2_2 = 1, 592 XLMAC_3_TRI_0_0_2_3 = 2, 593 XLMAC_2_LANES_DUAL = 3, 594 XLMAC_4_LANES_TOGETHER = 4 595 } unimac_port_mode_t; 596 597 int pm_qtc_port_phy_lane_access_get(int unit, int port, pm_info_t pm_info, 598 const portmod_access_get_params_t* params, 599 int max_phys, 600 phymod_phy_access_t* phy_access, 601 int* nof_phys, 602 int* is_most_ext) 603 { 604 int phyn = 0, rv; 605 int port_index, lane_mask; 606 SOC_INIT_FUNC_DEFS; 607 608 if(params->phyn > PM_QTC_INFO(pm_info)->nof_phys){ 609 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 610 (_SOC_MSG("phyn exceeded. max allowed %d. got %d"), 611 PM_QTC_INFO(pm_info)->nof_phys - 1, params->phyn)); 612 } 613 614 phyn = params->phyn; 615 616 if(phyn < 0) { 617 phyn = PM_QTC_INFO(pm_info)->nof_phys - 1; 618 } 619 620 sal_memcpy (&phy_access[0], &(PM_QTC_INFO(pm_info)->core_access[phyn]), 621 sizeof(PM_QTC_INFO(pm_info)->core_access[phyn])); 622 623 if(SOC_WARM_BOOT(unit)) { 624 rv = SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[phy_type], &(phy_access[0].type), phyn); 625 _SOC_IF_ERR_EXIT(rv); 626 } 627 628 _SOC_IF_ERR_EXIT(_pm_qtc_port_index_get(unit, port, pm_info, &port_index, 629 &(phy_access[0].access.lane_mask))); 630 631 if (params->lane != -1) { 632 lane_mask = port_index + params->lane; 633 phy_access[0].access.lane_mask &= (0x1 << lane_mask); 634 } 635 636 phy_access[0].access.lane_mask <<= PM_QTC_INFO(pm_info)->first_phy_lane[phyn]; 637 638 *nof_phys = 1; 639 640 if (is_most_ext) { 641 if (phyn == PM_QTC_INFO(pm_info)->nof_phys-1) { 642 *is_most_ext = 1; 643 } else { 644 *is_most_ext = 0; 645 } 646 } 647 648 exit: 649 SOC_FUNC_RETURN; 650 } 651 652 STATIC 653 int _pm_qtc_pm_enable (int unit, int port, pm_info_t pm_info, int port_index, 654 const portmod_port_add_info_t* add_info, int enable) 655 { 656 657 uint32 reg_val; 658 int rv; 659 int phy_acc, temp, phy; 660 phymod_core_init_config_t core_conf; 661 phymod_core_status_t core_status; 662 phymod_core_access_t* core_access; 663 uint32 nof_phys; 664 const portmod_port_interface_config_t* config; 665 portmod_pbmp_t port_phys_in_pm; 666 SOC_INIT_FUNC_DEFS; 667 668 PM_QTC_PHY_ACCESS_GET(unit, port, pm_info, phy_acc); 669 config = &(add_info->interface_config); 670 671 if(enable) { 672 673 674 /* Configure GPort */ 675 /* _SOC_IF_ERR_EXIT(READ_GPORT_RSV_MASKr(unit, phy_acc, ®_val)); */ 676 reg_val = 0x78; 677 _SOC_IF_ERR_EXIT(WRITE_GPORT_RSV_MASKr(unit, phy_acc, reg_val)); 678 679 reg_val = 0x3478; 680 _SOC_IF_ERR_EXIT(WRITE_GPORT_STAT_UPDATE_MASKr(unit, phy_acc, reg_val)); 681 682 /* TBD : PGW_GE WRITE : GP0_TDM_MODEf */ 683 684 _SOC_IF_ERR_EXIT(READ_GPORT_CONFIGr(unit, phy_acc, ®_val)); 685 soc_reg_field_set(unit, GPORT_CONFIGr, ®_val, CLR_CNTf, 0); 686 soc_reg_field_set(unit, GPORT_CONFIGr, ®_val, GPORT_ENf, 1); 687 _SOC_IF_ERR_EXIT(WRITE_GPORT_CONFIGr(unit, phy_acc, reg_val)); 688 689 _SOC_IF_ERR_EXIT(READ_GPORT_CONFIGr(unit, phy_acc, ®_val)); 690 soc_reg_field_set(unit, GPORT_CONFIGr, ®_val, CLR_CNTf, 1); 691 soc_reg_field_set(unit, GPORT_CONFIGr, ®_val, GPORT_ENf, 1); 692 _SOC_IF_ERR_EXIT(WRITE_GPORT_CONFIGr(unit, phy_acc, reg_val)); 693 694 _SOC_IF_ERR_EXIT(READ_GPORT_CONFIGr(unit, phy_acc, ®_val)); 695 soc_reg_field_set(unit, GPORT_CONFIGr, ®_val, CLR_CNTf, 0); 696 soc_reg_field_set(unit, GPORT_CONFIGr, ®_val, GPORT_ENf, 1); 697 _SOC_IF_ERR_EXIT(WRITE_GPORT_CONFIGr(unit, phy_acc, reg_val)); 698 699 /* Get Serdes OOR */ 700 _SOC_IF_ERR_EXIT(_pm_qtc_tsc_reset(unit, pm_info, port, 1)); 701 _SOC_IF_ERR_EXIT(_pm_qtc_tsc_reset(unit, pm_info, port, 0)); 702 703 nof_phys = PM_QTC_INFO(pm_info)->nof_phys; 704 core_access = (PM_QTC_INFO(pm_info)->core_access); 705 706 707 /* pass the port number in case legacy phy driver is used */ 708 PM_QTC_PORT_NUM_TO_PHY_ACCESS(core_access,nof_phys,port); 709 710 _SOC_IF_ERR_EXIT(portmod_port_phychain_core_probe(unit, port, core_access, 711 nof_phys)); 712 713 /* Get the first phy related to this port */ 714 PORTMOD_PBMP_ASSIGN(port_phys_in_pm, add_info->phys); 715 PORTMOD_PBMP_AND(port_phys_in_pm, PM_QTC_INFO(pm_info)->phys); 716 717 temp = 0; 718 PORTMOD_PBMP_ITER(PM_QTC_INFO(pm_info)->phys, phy) { 719 if(PORTMOD_PBMP_MEMBER(port_phys_in_pm, phy)) { 720 rv = SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 721 pm_info->wb_vars_ids[phy_type], &core_access->type, temp); 722 _SOC_IF_ERR_EXIT(rv); 723 } 724 temp++; 725 } 726 727 _SOC_IF_ERR_EXIT(phymod_core_init_config_t_init(&core_conf)); 728 729 /* set internal setting. */ 730 core_conf.firmware_load_method = PM_QTC_INFO(pm_info)->fw_load_method; 731 core_conf.firmware_loader = PM_QTC_INFO(pm_info)->external_fw_loader; 732 core_conf.lane_map = PM_QTC_INFO(pm_info)->lane_map; 733 734 _SOC_IF_ERR_EXIT(phymod_phy_inf_config_t_init(&core_conf.interface)); 735 _SOC_IF_ERR_EXIT(portmod_intf_to_phymod_intf(unit, config->speed, 736 config->interface, &core_conf.interface.interface_type)); 737 core_conf.interface.data_rate = config->speed; 738 core_conf.interface.interface_modes = config->interface_modes; 739 core_conf.interface.ref_clock = PM_QTC_INFO(pm_info)->ref_clk; 740 core_conf.interface.pll_divider_req = 0x2; /* FIX THIS - IN PORTCTRL.c */ 741 742 _SOC_IF_ERR_EXIT(phymod_core_status_t_init(&core_status)); 743 core_status.pmd_active = 0; 744 745 if(PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY_GET(add_info)) { 746 PHYMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY_SET(&core_conf); 747 } 748 749 _SOC_IF_ERR_EXIT(portmod_port_phychain_core_init(core_access, 750 nof_phys, 751 &core_conf, 752 &core_status)); 753 } else { /* disable */ 754 755 /* Put Serdes in reset*/ 756 _SOC_IF_ERR_EXIT(_pm_qtc_tsc_reset(unit, pm_info, port, 1)); 757 758 /* put MAC in reset */ 759 _SOC_IF_ERR_EXIT(unimac_soft_reset_set(unit, port, 1)); 760 } 761 762 exit: 763 SOC_FUNC_RETURN; 764 } 765 766 767 STATIC 768 int _pm_qtc_pm_port_init(int unit, int port, int phy_acc, int internal_port, 769 const portmod_port_add_info_t* add_info, int enable) 770 { 771 uint32 reg_val; 772 /* soc_field_t port_fields[] = {PORT0f, PORT1f, PORT2f, PORT3f}; */ 773 SOC_INIT_FUNC_DEFS; 774 775 776 /* Configure UniMAC */ 777 if(enable) { 778 _SOC_IF_ERR_EXIT(READ_FRM_LENGTHr(unit, phy_acc, ®_val)); 779 reg_val = 0x2800; 780 _SOC_IF_ERR_EXIT(WRITE_FRM_LENGTHr(unit, phy_acc, reg_val)); 781 782 _SOC_IF_ERR_EXIT(READ_COMMAND_CONFIGr(unit, phy_acc, ®_val)); 783 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, CNTL_FRM_ENAf, 0); 784 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, CRC_FWDf, 1); 785 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, ENA_EXT_CONFIGf, 0); 786 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, EN_INTERNAL_TX_CRSf, 0); 787 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, ETH_SPEEDf, 0x2); /* SET THE SPEED TBD */ 788 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, FCS_CORRUPT_URUN_ENf, 0); 789 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, FD_TX_URUN_FIX_ENf, 0); 790 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, HD_ENAf, 0); 791 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, IGNORE_TX_PAUSEf, 0); 792 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, LINE_LOOPBACKf, 0); 793 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, LOOP_ENAf, 0); 794 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, MAC_LOOP_CONf, 0); 795 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, NO_LGTH_CHECKf, 1); 796 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, OOB_EFC_ENf, 0); 797 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, OVERFLOW_ENf, 0); 798 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PAD_ENf, 0); 799 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PAUSE_FWDf, 1); 800 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PAUSE_IGNOREf, 0); 801 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PROMIS_ENf, 1); 802 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RUNT_FILTER_DISf, 0); 803 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RX_ENAf, 0); 804 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RX_ERR_DISCf, 0); 805 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RX_LOW_LATENCY_ENf, 0); 806 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_OVERRIDE_RXf, 0); 807 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_OVERRIDE_TXf, 0); 808 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_RESETf, 1); 809 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, TX_ADDR_INSf, 0); 810 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, TX_ENAf, 0); 811 _SOC_IF_ERR_EXIT(WRITE_COMMAND_CONFIGr(unit, phy_acc, reg_val)); 812 813 _SOC_IF_ERR_EXIT(READ_COMMAND_CONFIGr(unit, phy_acc, ®_val)); 814 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, CNTL_FRM_ENAf, 1); 815 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, CRC_FWDf, 1); 816 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, ENA_EXT_CONFIGf, 0); 817 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, EN_INTERNAL_TX_CRSf, 0); 818 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, ETH_SPEEDf, 0x2); /* SET THE SPEED TBD */ 819 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, FCS_CORRUPT_URUN_ENf, 0); 820 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, FD_TX_URUN_FIX_ENf, 0); 821 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, HD_ENAf, 0); 822 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, IGNORE_TX_PAUSEf, 0); 823 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, LINE_LOOPBACKf, 0); 824 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, LOOP_ENAf, 0); 825 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, MAC_LOOP_CONf, 0); 826 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, NO_LGTH_CHECKf, 1); 827 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, OOB_EFC_ENf, 0); 828 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, OVERFLOW_ENf, 0); 829 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PAD_ENf, 0); 830 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PAUSE_FWDf, 0); 831 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PAUSE_IGNOREf, 0); 832 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PROMIS_ENf, 1); 833 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RUNT_FILTER_DISf, 0); 834 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RX_ENAf, 1); 835 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RX_ERR_DISCf, 0); 836 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RX_LOW_LATENCY_ENf, 0); 837 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_OVERRIDE_RXf, 0); 838 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_OVERRIDE_TXf, 0); 839 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_RESETf, 0); 840 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, TX_ADDR_INSf, 0); 841 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, TX_ENAf, 1); 842 _SOC_IF_ERR_EXIT(WRITE_COMMAND_CONFIGr(unit, phy_acc, reg_val)); 843 844 reg_val = 0x8; 845 _SOC_IF_ERR_EXIT(WRITE_TX_IPG_LENGTHr(unit, phy_acc, reg_val)); 846 847 } 848 else { 849 _SOC_IF_ERR_EXIT(READ_COMMAND_CONFIGr(unit, phy_acc, ®_val)); 850 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, CNTL_FRM_ENAf, 0); 851 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, CRC_FWDf, 1); 852 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, ENA_EXT_CONFIGf, 0); 853 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, EN_INTERNAL_TX_CRSf, 0); 854 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, ETH_SPEEDf, 0x2); /* SET THE SPEED TBD */ 855 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, FCS_CORRUPT_URUN_ENf, 0); 856 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, FD_TX_URUN_FIX_ENf, 0); 857 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, HD_ENAf, 0); 858 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, IGNORE_TX_PAUSEf, 0); 859 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, LINE_LOOPBACKf, 0); 860 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, LOOP_ENAf, 0); 861 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, MAC_LOOP_CONf, 0); 862 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, NO_LGTH_CHECKf, 1); 863 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, OOB_EFC_ENf, 0); 864 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, OVERFLOW_ENf, 0); 865 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PAD_ENf, 0); 866 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PAUSE_FWDf, 1); 867 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PAUSE_IGNOREf, 0); 868 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, PROMIS_ENf, 1); 869 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RUNT_FILTER_DISf, 0); 870 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RX_ENAf, 0); 871 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RX_ERR_DISCf, 0); 872 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, RX_LOW_LATENCY_ENf, 0); 873 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_OVERRIDE_RXf, 0); 874 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_OVERRIDE_TXf, 0); 875 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_RESETf, 1); 876 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, TX_ADDR_INSf, 0); 877 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, TX_ENAf, 0); 878 _SOC_IF_ERR_EXIT(WRITE_COMMAND_CONFIGr(unit, phy_acc, reg_val)); 879 880 } 881 882 exit: 883 SOC_FUNC_RETURN; 884 885 886 } 887 888 STATIC 889 int portmod_interface_pm_qtc_to_phymod_interface(int unit, 890 int port, 891 const portmod_port_interface_config_t *interface_config, 892 const portmod_port_init_config_t *init_config, 893 phymod_phy_inf_config_t *phy_interface_config) ; 894 STATIC 895 int portmod_interface_pm_qtc_xphy_to_phymod_interface(int unit, 896 int port, 897 const portmod_port_interface_config_t *interface_config, 898 const portmod_port_init_config_t *init_config, 899 phymod_phy_inf_config_t *phy_interface_config) ; 900 901 /* 902 * clear pm_info's phy_interface_config, and set few members of phy_interface_config 903 * initialize phy_init_config tx params and set registers 904 */ 905 int _pm_qtc_port_interface_config_init_set(int unit, int port, 906 pm_info_t pm_info, 907 const portmod_port_interface_config_t* config) 908 { 909 uint32 pm_is_bypassed = 0; 910 int i, nof_phys = 0, rv = 0; /* phy_acc; */ 911 phymod_phy_access_t phy_access[1 + MAX_PHYN]; 912 phymod_phy_access_t phy_access_lane; 913 914 phymod_phy_inf_config_t *phy_interface_config; 915 portmod_access_get_params_t params; 916 phymod_tx_t phymod_tx; 917 portmod_port_init_config_t *init_config; 918 phymod_phy_init_config_t *phy_init_config; 919 int port_index; 920 uint32_t bitmap; 921 922 SOC_INIT_FUNC_DEFS; 923 924 /* PM_QTC_PHY_ACCESS_GET(unit, port, pm_info, phy_acc); */ 925 926 _SOC_IF_ERR_EXIT(_pm_qtc_port_index_get (unit, port, pm_info, &port_index, 927 &bitmap)); 928 init_config = &PM_QTC_INFO(pm_info)->port_config[port_index].port_init_config; 929 phy_interface_config = &PM_QTC_INFO(pm_info)->port_config[port_index].phy_interface_config; 930 phy_init_config = &PM_QTC_INFO(pm_info)->port_config[port_index].phy_init_config; 931 932 rv = SOC_WB_ENGINE_GET_VAR (unit, SOC_WB_ENGINE_PORTMOD, 933 pm_info->wb_vars_ids[isBypassed], 934 &pm_is_bypassed); 935 _SOC_IF_ERR_EXIT(rv); 936 937 if(!pm_is_bypassed){ 938 /* set port speed */ 939 rv = unimac_speed_set(unit, port, config->speed); 940 _SOC_IF_ERR_EXIT(rv); 941 942 /* set encapsulation */ 943 rv = unimac_encap_set (unit, port, SOC_ENCAP_IEEE); 944 _SOC_IF_ERR_EXIT(rv); 945 } 946 947 948 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 949 _SOC_IF_ERR_EXIT(pm_qtc_port_phy_lane_access_get(unit, port, pm_info, 950 ¶ms, 1, &phy_access_lane, &nof_phys, NULL)); 951 952 _SOC_IF_ERR_EXIT(phymod_phy_media_type_tx_get(&phy_access_lane, phymodMediaTypeChipToChip, &phymod_tx)); 953 954 /* overlap preemphasis and amp from config */ 955 if(init_config->tx_params_user_flag & PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG) { 956 phymod_tx.pre = init_config->tx_params.pre ; 957 phymod_tx.main = init_config->tx_params.main ; 958 phymod_tx.post = init_config->tx_params.post ; 959 } 960 if(init_config->tx_params_user_flag & PORTMOD_USER_SET_TX_AMP_BY_CONFIG) { 961 phymod_tx.amp = init_config->tx_params.amp ; 962 } 963 for(i=0 ; i<PM_QTC_LANES_PER_CORE/4 ; i++) { 964 phy_init_config->tx[i].pre = phymod_tx.pre ; 965 phy_init_config->tx[i].main = phymod_tx.main ; 966 phy_init_config->tx[i].post = phymod_tx.post ; 967 phy_init_config->tx[i].post2= phymod_tx.post2; 968 phy_init_config->tx[i].post3= phymod_tx.post3; 969 phy_init_config->tx[i].amp = phymod_tx.amp ; 970 } 971 972 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, 973 phy_access ,(1+MAX_PHYN), 974 &nof_phys)); 975 976 _SOC_IF_ERR_EXIT(phymod_phy_inf_config_t_init (phy_interface_config)); 977 _SOC_IF_ERR_EXIT(portmod_intf_to_phymod_intf(unit, config->speed, 978 config->interface, &phy_interface_config->interface_type)); 979 980 phy_interface_config->data_rate = config->speed; 981 phy_interface_config->interface_modes = config->interface_modes; 982 phy_interface_config->ref_clock = PM_QTC_INFO(pm_info)->ref_clk; 983 984 if(nof_phys > 1) 985 { /* external phy. */ 986 portmod_interface_pm_qtc_xphy_to_phymod_interface(unit, port, 987 config, init_config, phy_interface_config); 988 } 989 else 990 { /* internal phy. */ 991 portmod_interface_pm_qtc_to_phymod_interface(unit, port, 992 config, init_config, phy_interface_config); 993 } 994 995 SOC_IF_ERROR_RETURN(portmod_port_phychain_tx_set(phy_access, 996 nof_phys, phy_init_config->tx)); 997 exit: 998 SOC_FUNC_RETURN; 999 } 1000 1001 int pm_qtc_port_attach (int unit, int port, pm_info_t pm_info, 1002 const portmod_port_add_info_t* add_info) 1003 { 1004 int port_index = -1, rv = 0, phy, i, phys_count = 0, nof_phys, my_i, port_i; 1005 uint32 pm_is_active = 0, bitmap; 1006 /* uint32 pm_is_bypassed = 0; */ 1007 portmod_pbmp_t port_phys_in_pm; 1008 int first_phy = -1, phy_acc; 1009 1010 phymod_phy_init_config_t *phy_init_config; 1011 phymod_phy_inf_config_t *phy_interface_config; 1012 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1013 phymod_phy_access_t phy_access_lane; 1014 portmod_port_ability_t port_ability; 1015 portmod_access_get_params_t params; 1016 1017 1018 SOC_INIT_FUNC_DEFS; 1019 1020 PM_QTC_PHY_ACCESS_GET(unit, port, pm_info, phy_acc); 1021 1022 /* pm_is_bypassed = 0; */ 1023 1024 /* Get the first phy related to this port */ 1025 PORTMOD_PBMP_ASSIGN(port_phys_in_pm, add_info->phys); 1026 PORTMOD_PBMP_AND(port_phys_in_pm, PM_QTC_INFO(pm_info)->phys); 1027 PORTMOD_PBMP_COUNT(port_phys_in_pm, phys_count); 1028 1029 i = 0; 1030 PORTMOD_PBMP_ITER(PM_QTC_INFO(pm_info)->phys, phy) { 1031 if(PORTMOD_PBMP_MEMBER(port_phys_in_pm, phy)) { 1032 rv = SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 1033 pm_info->wb_vars_ids[ports], &port, i); 1034 _SOC_IF_ERR_EXIT(rv); 1035 first_phy = (first_phy == -1) ? phy : first_phy; 1036 port_index = (port_index == -1 ? i : port_index); 1037 } 1038 i++; 1039 } 1040 1041 PM_QTC_INFO(pm_info)->first_phy = first_phy; 1042 if(port_index<0 || port_index>=PM_QTC_LANES_PER_CORE) { 1043 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 1044 (_SOC_MSG("can't attach port %d. can't find relevant phy"), port)); 1045 } 1046 1047 /* port_index is 0, 1, 2, or 3 */ 1048 rv = SOC_WB_ENGINE_GET_VAR (unit, SOC_WB_ENGINE_PORTMOD, 1049 pm_info->wb_vars_ids[isActive], &pm_is_active); 1050 _SOC_IF_ERR_EXIT(rv); 1051 1052 /* init data for interface_config and port_init_config */ 1053 sal_memcpy(&PM_QTC_INFO(pm_info)->port_config[port_index].interface_config, 1054 &add_info->interface_config, 1055 sizeof(portmod_port_interface_config_t)); 1056 1057 sal_memcpy(&PM_QTC_INFO(pm_info)->port_config[port_index].port_init_config, 1058 &add_info->init_config, 1059 sizeof(portmod_port_init_config_t)); 1060 1061 /* if not active - initalize PM */ 1062 if(!pm_is_active){ 1063 1064 /*init the PM*/ 1065 rv = _pm_qtc_pm_enable (unit, port, pm_info, port_index, add_info, 1); 1066 _SOC_IF_ERR_EXIT(rv); 1067 1068 pm_is_active = 1; 1069 rv = SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, 1070 pm_info->wb_vars_ids[isActive], &pm_is_active); 1071 _SOC_IF_ERR_EXIT(rv); 1072 } 1073 1074 /* initalize port */ 1075 rv = _pm_qtc_pm_port_init(unit, port, phy_acc, port_index, add_info, 1); 1076 _SOC_IF_ERR_EXIT(rv); 1077 1078 /* initialze phys */ 1079 _SOC_IF_ERR_EXIT(_pm_qtc_port_index_get (unit, port, pm_info, &port_index, 1080 &bitmap)); 1081 phy_init_config = &PM_QTC_INFO(pm_info)->port_config[port_index].phy_init_config; 1082 phy_interface_config = &PM_QTC_INFO(pm_info)->port_config[port_index].phy_interface_config; 1083 1084 /* clean up polarity and tx of phy_init_config */ 1085 _SOC_IF_ERR_EXIT(phymod_phy_init_config_t_init(phy_init_config)); 1086 1087 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 1088 _SOC_IF_ERR_EXIT(pm_qtc_port_phy_lane_access_get(unit, port, pm_info, 1089 ¶ms, 1, &phy_access_lane, &nof_phys, NULL)); 1090 1091 my_i = 0; 1092 for(i=0 ; i<PM_QTC_LANES_PER_CORE ; i++) { 1093 1094 rv = SOC_WB_ENGINE_GET_ARR (unit, SOC_WB_ENGINE_PORTMOD, 1095 pm_info->wb_vars_ids[ports], &port_i, i); 1096 _SOC_IF_ERR_EXIT(rv); 1097 1098 if(port_i != port) { 1099 continue; 1100 } 1101 1102 if(SHR_BITGET(&PM_QTC_INFO(pm_info)->polarity.tx_polarity,i)) { 1103 SHR_BITSET(&phy_init_config->polarity.tx_polarity, my_i); 1104 } 1105 1106 if(SHR_BITGET(&PM_QTC_INFO(pm_info)->polarity.rx_polarity,i)) { 1107 SHR_BITSET(&phy_init_config->polarity.rx_polarity, my_i); 1108 } 1109 1110 /* 1111 _SOC_IF_ERR_EXIT(phymod_phy_media_type_tx_get(&phy_access_lane, phymodMediaTypeChipToChip, &phy_init_config>tx[my_i])); 1112 */ 1113 my_i++; 1114 } 1115 1116 phy_init_config->op_mode = add_info->phy_op_mode; 1117 1118 _SOC_IF_ERR_EXIT(_pm_qtc_port_interface_config_init_set(unit, port, 1119 pm_info, &add_info->interface_config)); 1120 1121 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, 1122 phy_access ,(1+MAX_PHYN), 1123 &nof_phys)); 1124 1125 _SOC_IF_ERR_EXIT(portmod_port_phychain_phy_init(phy_access, nof_phys, 1126 phy_init_config)); 1127 1128 _SOC_IF_ERR_EXIT(portmod_port_phychain_interface_config_set(unit, port, phy_access, nof_phys, 1129 PM_QTC_INFO(pm_info)->port_config[port_index].interface_config.flags , 1130 phy_interface_config, 1131 PM_QTC_INFO(pm_info)->ref_clk, 1132 TRUE )); /* Apply to ALL PHY with same interface config */ 1133 1134 1135 /* set the default advert ability */ 1136 _SOC_IF_ERR_EXIT 1137 (pm_qtc_port_ability_local_get(unit, port, pm_info, &port_ability)); 1138 _SOC_IF_ERR_EXIT 1139 (pm_qtc_port_ability_advert_set(unit, port, pm_info, &port_ability)); 1140 1141 /* De-Assert SOFT_RESET */ 1142 _SOC_IF_ERR_EXIT(pm_qtc_port_soft_reset(unit, port, pm_info, 0)); 1143 exit: 1144 SOC_FUNC_RETURN; 1145 } 1146 1147 1148 int pm_qtc_port_detach(int unit, int port, pm_info_t pm_info) 1149 { 1150 int enable, tmp_port, i=0, rv=0, port_index = -1; 1151 int invalid_port = -1, is_last_one = TRUE, phy_acc; 1152 uint32 inactive = 0; 1153 1154 SOC_INIT_FUNC_DEFS; 1155 1156 PM_QTC_PHY_ACCESS_GET(unit, port, pm_info, phy_acc); 1157 1158 _SOC_IF_ERR_EXIT(pm_qtc_port_enable_get(unit, port, pm_info, 0, &enable)); 1159 if(enable) { 1160 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 1161 (_SOC_MSG("can't detach active port %d"), port)); 1162 } 1163 1164 /*remove from array and check if it was the last one*/ 1165 for( i = 0 ; i < MAX_PORTS_PER_PM_QTC; i++) { 1166 rv = SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 1167 pm_info->wb_vars_ids[ports], &tmp_port, i); 1168 _SOC_IF_ERR_EXIT(rv); 1169 1170 if(tmp_port == port){ 1171 port_index = (port_index == -1 ? i : port_index); 1172 rv = SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 1173 pm_info->wb_vars_ids[ports], &invalid_port, i); 1174 _SOC_IF_ERR_EXIT(rv); 1175 } else if (tmp_port != -1) { 1176 is_last_one = FALSE; 1177 } 1178 } 1179 1180 if(port_index == -1) { 1181 _SOC_EXIT_WITH_ERR(SOC_E_PORT,(_SOC_MSG("Port %d wasn't found"),port)); 1182 } 1183 1184 rv = _pm_qtc_pm_port_init(unit, port, phy_acc, port_index, NULL, 0); 1185 _SOC_IF_ERR_EXIT(rv); 1186 1187 /*deinit PM in case of last one*/ 1188 if (is_last_one) { 1189 rv = _pm_qtc_pm_enable(unit, port, pm_info, port_index, NULL, 0); 1190 _SOC_IF_ERR_EXIT(rv); 1191 1192 rv = SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, 1193 pm_info->wb_vars_ids[isActive], &inactive); 1194 _SOC_IF_ERR_EXIT(rv); 1195 } 1196 1197 exit: 1198 SOC_FUNC_RETURN; 1199 } 1200 1201 1202 int pm_qtc_pm_bypass_set(int unit, pm_info_t pm_info, int bypass_enable) 1203 { 1204 return SOC_E_NONE; 1205 1206 } 1207 1208 int pm_qtc_pm_core_info_get(int unit, pm_info_t pm_info, int phyn, portmod_pm_core_info_t* core_info) 1209 { 1210 return SOC_E_NONE; 1211 1212 } 1213 1214 int pm_qtc_port_enable_set (int unit, int port, pm_info_t pm_info, 1215 int flags, int enable) 1216 { 1217 1218 uint32 is_bypassed = 0; 1219 int rv = 0; 1220 int actual_flags = flags, /*rst_flags, */ nof_phys = 0 ; 1221 1222 phymod_phy_power_t phy_power; 1223 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1224 1225 SOC_INIT_FUNC_DEFS; 1226 1227 /* If no Rx/Tx flags - set both */ 1228 if ((!PORTMOD_PORT_ENABLE_TX_GET(flags)) && 1229 (!PORTMOD_PORT_ENABLE_RX_GET(flags))) 1230 { 1231 PORTMOD_PORT_ENABLE_RX_SET(actual_flags); 1232 PORTMOD_PORT_ENABLE_TX_SET(actual_flags); 1233 } 1234 1235 /* If no Mac/Phy flags - set both */ 1236 if ((!PORTMOD_PORT_ENABLE_PHY_GET(flags)) && 1237 (!PORTMOD_PORT_ENABLE_MAC_GET(flags))) 1238 { 1239 PORTMOD_PORT_ENABLE_PHY_SET(actual_flags); 1240 PORTMOD_PORT_ENABLE_MAC_SET(actual_flags); 1241 } 1242 1243 rv = SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, 1244 pm_info->wb_vars_ids[isBypassed], &is_bypassed); 1245 _SOC_IF_ERR_EXIT(rv); 1246 1247 _SOC_IF_ERR_EXIT(phymod_phy_power_t_init(&phy_power)); 1248 phy_power.rx = phymodPowerNoChange; 1249 phy_power.tx = phymodPowerNoChange; 1250 1251 if(PORTMOD_PORT_ENABLE_RX_GET(actual_flags)){ 1252 phy_power.rx = (enable) ? phymodPowerOn : phymodPowerOff; 1253 } 1254 if(PORTMOD_PORT_ENABLE_TX_GET(actual_flags)){ 1255 phy_power.tx = (enable) ? phymodPowerOn : phymodPowerOff; 1256 } 1257 1258 if(enable) { 1259 if((PORTMOD_PORT_ENABLE_MAC_GET(actual_flags)) && (!is_bypassed)){ 1260 if(PM_QTC_INFO(pm_info)->portmod_mac_soft_reset) { 1261 /* rst_flags |= XLMAC_ENABLE_SET_FLAGS_SOFT_RESET_DIS; */ 1262 } 1263 rv = unimac_enable_set(unit, port, 0, 1); 1264 _SOC_IF_ERR_EXIT(rv); 1265 if(PM_QTC_INFO(pm_info)->portmod_mac_soft_reset) { 1266 _SOC_IF_ERR_EXIT(pm_qtc_port_soft_reset(unit, port, pm_info, 0)); 1267 } 1268 } 1269 1270 if(PORTMOD_PORT_ENABLE_PHY_GET(actual_flags)) 1271 { 1272 _SOC_IF_ERR_EXIT 1273 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1274 phy_access ,(1+MAX_PHYN), 1275 &nof_phys)); 1276 1277 _SOC_IF_ERR_EXIT 1278 (portmod_port_phychain_power_set(unit, port, phy_access, nof_phys, &phy_power)); 1279 1280 _SOC_IF_ERR_EXIT 1281 (portmod_port_phychain_tx_lane_control_set(unit, port, phy_access, nof_phys, 1282 phymodTxSquelchOff)); 1283 1284 _SOC_IF_ERR_EXIT 1285 (portmod_port_phychain_rx_lane_control_set(unit, port, phy_access, nof_phys, 1286 phymodRxSquelchOff)); 1287 } 1288 } else { 1289 if (PORTMOD_PORT_ENABLE_PHY_GET(actual_flags)) { 1290 _SOC_IF_ERR_EXIT 1291 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1292 phy_access ,(1+MAX_PHYN), 1293 &nof_phys)); 1294 _SOC_IF_ERR_EXIT 1295 (portmod_port_phychain_tx_lane_control_set(unit, port, phy_access, nof_phys, 1296 phymodTxSquelchOn)); 1297 _SOC_IF_ERR_EXIT 1298 (portmod_port_phychain_rx_lane_control_set(unit, port, phy_access, nof_phys, 1299 phymodRxSquelchOn)); 1300 _SOC_IF_ERR_EXIT 1301 (portmod_port_phychain_power_set(unit, port, phy_access, nof_phys, &phy_power)); 1302 } 1303 1304 if((PORTMOD_PORT_ENABLE_MAC_GET(actual_flags)) && (!is_bypassed)){ 1305 rv = unimac_enable_set(unit, port, 0, 0); 1306 _SOC_IF_ERR_EXIT(rv); 1307 } 1308 } 1309 1310 exit: 1311 SOC_FUNC_RETURN; 1312 1313 return SOC_E_NONE; 1314 1315 } 1316 1317 int pm_qtc_port_enable_get (int unit, int port, pm_info_t pm_info, int flags, 1318 int* enable) 1319 { 1320 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1321 int nof_phys = 0; 1322 phymod_phy_tx_lane_control_t tx_control = phymodTxSquelchOn; 1323 phymod_phy_rx_lane_control_t rx_control = phymodRxSquelchOn; 1324 int phy_enable = 0; 1325 int mac_enable = 0, mac_rx_enable, mac_tx_enable; 1326 1327 SOC_INIT_FUNC_DEFS; 1328 SOC_NULL_CHECK(pm_info); 1329 1330 if (PORTMOD_PORT_ENABLE_PHY_GET(flags)||(0 == flags)) { 1331 1332 _SOC_IF_ERR_EXIT 1333 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1334 phy_access ,(1+MAX_PHYN), 1335 &nof_phys)); 1336 1337 _SOC_IF_ERR_EXIT 1338 (portmod_port_phychain_tx_lane_control_get(phy_access, nof_phys, 1339 &tx_control)); 1340 _SOC_IF_ERR_EXIT 1341 (portmod_port_phychain_rx_lane_control_get(phy_access, nof_phys, 1342 &rx_control)); 1343 phy_enable = ((tx_control == phymodTxSquelchOn) && 1344 (rx_control == phymodRxSquelchOn)) ? 0 : 1; 1345 if(0 != flags) { 1346 *enable = phy_enable; 1347 } 1348 } 1349 1350 if (PORTMOD_PORT_ENABLE_MAC_GET(flags)||(0 == flags)) { 1351 if (PORTMOD_PORT_ENABLE_RX_GET(flags)||(0 == flags)) { 1352 _SOC_IF_ERR_EXIT(unimac_enable_get(unit, port, UNIMAC_ENABLE_SET_FLAGS_RX_EN, &mac_rx_enable)); 1353 mac_enable |= (mac_rx_enable) ? 1 : 0; 1354 } 1355 if (PORTMOD_PORT_ENABLE_TX_GET(flags)||(0 == flags)) { 1356 _SOC_IF_ERR_EXIT(unimac_enable_get(unit, port, UNIMAC_ENABLE_SET_FLAGS_TX_EN, &mac_tx_enable)); 1357 mac_enable |= (mac_tx_enable) ? 1 : 0; 1358 } 1359 if(0 != flags) { 1360 *enable = mac_enable; 1361 } 1362 } 1363 1364 if(0 == flags){ 1365 *enable = (mac_enable || phy_enable) ; 1366 } 1367 1368 exit: 1369 SOC_FUNC_RETURN; 1370 } 1371 1372 /*! 1373 * portmod_interface_pm_qtc_to_phymod_interface 1374 * 1375 * @brief passing and process data structure from in to out 1376 * 1377 * @param[in] interface_config 1378 * @param[im] init_config 1379 * 1380 * @param[out] phy_interface_config 1381 */ 1382 STATIC 1383 int portmod_interface_pm_qtc_to_phymod_interface(int unit, 1384 int port, 1385 const portmod_port_interface_config_t *interface_config, 1386 const portmod_port_init_config_t *init_config, 1387 phymod_phy_inf_config_t *phy_interface_config) 1388 { 1389 int port_num_lanes; 1390 int fiber_pref; 1391 1392 port_num_lanes = interface_config->port_num_lanes; 1393 fiber_pref = PHYMOD_INTF_MODES_FIBER_GET(interface_config); 1394 1395 /*for qsgmii mode */ 1396 if (port_num_lanes == 1) { 1397 phy_interface_config->interface_type = phymodInterfaceQSGMII; 1398 } else { 1399 switch (interface_config->speed) { 1400 case 10: 1401 phy_interface_config->interface_type = phymodInterfaceSGMII; 1402 break; 1403 case 100: 1404 phy_interface_config->interface_type = phymodInterfaceSGMII; 1405 break; 1406 case 1000: 1407 if (fiber_pref) { 1408 phy_interface_config->interface_type = phymodInterface1000X; 1409 } else { 1410 phy_interface_config->interface_type = phymodInterfaceSGMII; 1411 } 1412 break; 1413 case 2500: 1414 phy_interface_config->interface_type = phymodInterface1000X; 1415 break; 1416 default: 1417 return SOC_E_PARAM; 1418 } 1419 } 1420 return SOC_E_PARAM; 1421 } 1422 1423 /*! 1424 * portmod_interface_pm_qtc_xphy_to_phymod_interface 1425 * 1426 * @brief passing and process data structure from in to out 1427 * 1428 * @param[in] interface_config 1429 * @param[im] init_config 1430 * 1431 * @param[out] phy_interface_config 1432 */ 1433 STATIC 1434 int portmod_interface_pm_qtc_xphy_to_phymod_interface(int unit, 1435 int port, 1436 const portmod_port_interface_config_t *interface_config, 1437 const portmod_port_init_config_t *init_config, 1438 phymod_phy_inf_config_t *phy_interface_config) 1439 { 1440 return SOC_E_NONE; 1441 1442 1443 1444 1445 } 1446 1447 int pm_qtc_port_interface_config_set(int unit, int port, 1448 pm_info_t pm_info, 1449 const portmod_port_interface_config_t* config, 1450 int phy_init_flags) 1451 { 1452 uint32 pm_is_bypassed = 0; 1453 int nof_phys = 0, rv = 0; /* phy_acc; */ 1454 phymod_phy_access_t phy_access_arr[1+MAX_PHYN]; 1455 phymod_phy_access_t phy_access; 1456 phymod_phy_inf_config_t phy_interface_config; 1457 portmod_access_get_params_t params; 1458 portmod_port_init_config_t *init_config; 1459 phymod_phy_init_config_t *phy_init_config; 1460 int port_index; 1461 uint32_t bitmap; 1462 portmod_port_interface_config_t *interface_config ; 1463 portmod_port_interface_config_t config_temp ; 1464 SOC_INIT_FUNC_DEFS; 1465 1466 /* PM_QTC_PHY_ACCESS_GET(unit, port, pm_info, phy_acc); */ 1467 1468 _SOC_IF_ERR_EXIT(_pm_qtc_port_index_get (unit, port, pm_info, &port_index, 1469 &bitmap)); 1470 init_config = &PM_QTC_INFO(pm_info)->port_config[port_index].port_init_config; 1471 phy_init_config = &PM_QTC_INFO(pm_info)->port_config[port_index].phy_init_config; 1472 interface_config = &PM_QTC_INFO(pm_info)->port_config[port_index].interface_config; 1473 1474 interface_config->port_refclk_int = PM_QTC_INFO(pm_info)->ref_clk; 1475 1476 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 1477 params.phyn = 0; 1478 params.lane = -1; 1479 params.sys_side = PORTMOD_SIDE_LINE; 1480 1481 _SOC_IF_ERR_EXIT(pm_qtc_port_phy_lane_access_get(unit, port, pm_info, 1482 ¶ms, 1, &phy_access, &nof_phys, NULL)); 1483 1484 rv = SOC_WB_ENGINE_GET_VAR (unit, SOC_WB_ENGINE_PORTMOD, 1485 pm_info->wb_vars_ids[isBypassed], 1486 &pm_is_bypassed); 1487 _SOC_IF_ERR_EXIT(rv); 1488 1489 if(config->flags & PHYMOD_INTF_F_INTF_PARAM_SET_ONLY) { 1490 /* only flag saved by interface_config->flags */ 1491 interface_config->flags = PHYMOD_INTF_F_INTF_PARAM_SET_ONLY; 1492 interface_config->interface = config->interface ; 1493 1494 SOC_FUNC_RETURN; 1495 } 1496 1497 if (!(config->flags & PHYMOD_INTF_F_SET_SPD_TRIGGER) && (!pm_is_bypassed)){ 1498 1499 /* set port speed */ 1500 /*flags = XLMAC_SPEED_SET_FLAGS_SOFT_RESET_DIS; */ 1501 rv = unimac_speed_set(unit, port, config->speed); 1502 _SOC_IF_ERR_EXIT(rv); 1503 1504 /* set encapsulation */ 1505 /*flags = XLMAC_ENCAP_SET_FLAGS_SOFT_RESET_DIS; */ 1506 rv = unimac_encap_set (unit, port, /*flags, */ config->encap_mode); 1507 _SOC_IF_ERR_EXIT(rv); 1508 1509 /* De-Assert SOFT_RESET */ 1510 rv = pm_qtc_port_soft_reset(unit, port, pm_info, 0); 1511 _SOC_IF_ERR_EXIT(rv); 1512 } 1513 1514 _SOC_IF_ERR_EXIT(phymod_phy_inf_config_t_init (&phy_interface_config)); 1515 _SOC_IF_ERR_EXIT(portmod_intf_to_phymod_intf(unit, config->speed, 1516 config->interface, &phy_interface_config.interface_type)); 1517 1518 phy_interface_config.data_rate = config->speed; 1519 phy_interface_config.interface_modes = config->interface_modes; 1520 phy_interface_config.ref_clock = PM_QTC_INFO(pm_info)->ref_clk; 1521 1522 /* copy const *config to config_temp cause config.interface may come from storage */ 1523 _SOC_IF_ERR_EXIT(portmod_port_interface_config_t_init(unit, &config_temp)); 1524 sal_memcpy(&config_temp, config, sizeof(portmod_port_interface_config_t)); 1525 1526 if(interface_config->flags & PHYMOD_INTF_F_INTF_PARAM_SET_ONLY) { 1527 /* overwrite config->interface form storage */ 1528 config_temp.interface = interface_config->interface ; 1529 interface_config->flags = 0 ; 1530 } 1531 1532 portmod_interface_pm_qtc_to_phymod_interface(unit, port, 1533 &config_temp, init_config, &phy_interface_config); 1534 1535 _SOC_IF_ERR_EXIT 1536 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1537 phy_access_arr ,(1+MAX_PHYN), 1538 &nof_phys)); 1539 1540 if( nof_phys > 1 ){ 1541 /* external phy interface translation. */ 1542 portmod_interface_pm_qtc_xphy_to_phymod_interface(unit, port, 1543 &config_temp, init_config, &phy_interface_config); 1544 1545 } else { 1546 portmod_interface_pm_qtc_to_phymod_interface(unit, port, 1547 &config_temp, init_config, &phy_interface_config); 1548 } 1549 1550 if (!(config->flags & PHYMOD_INTF_F_SET_SPD_TRIGGER)) { 1551 _SOC_IF_ERR_EXIT(portmod_port_phychain_tx_set(phy_access_arr, nof_phys, phy_init_config->tx)); 1552 } 1553 1554 _SOC_IF_ERR_EXIT 1555 (portmod_port_phychain_interface_config_set(unit, port, phy_access_arr, nof_phys, 1556 config_temp.flags, 1557 &phy_interface_config, 1558 PM_QTC_INFO(pm_info)->ref_clk, 1559 phy_init_flags)); 1560 exit: 1561 SOC_FUNC_RETURN; 1562 } 1563 1564 int pm_qtc_port_interface_config_get (int unit, int port, pm_info_t pm_info, 1565 portmod_port_interface_config_t* config) 1566 { 1567 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1568 phymod_phy_inf_config_t phy_interface_config; 1569 portmod_port_interface_config_t *interface_config ; 1570 int port_index; 1571 uint32_t bitmap; 1572 int nof_phys = 0, rv = 0, ref_clock ; 1573 1574 SOC_INIT_FUNC_DEFS; 1575 1576 ref_clock = PM_QTC_INFO(pm_info)->ref_clk; 1577 1578 _SOC_IF_ERR_EXIT(_pm_qtc_port_index_get (unit, port, pm_info, &port_index, 1579 &bitmap)); 1580 interface_config = &PM_QTC_INFO(pm_info)->port_config[port_index].interface_config; 1581 1582 _SOC_IF_ERR_EXIT(phymod_phy_inf_config_t_init(&phy_interface_config)); 1583 1584 _SOC_IF_ERR_EXIT 1585 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1586 phy_access ,(1+MAX_PHYN), 1587 &nof_phys)); 1588 1589 phy_interface_config.data_rate = interface_config->max_speed; 1590 phy_interface_config.interface_type = phymodInterfaceXGMII; 1591 phy_interface_config.ref_clock = ref_clock; 1592 1593 _SOC_IF_ERR_EXIT 1594 (portmod_port_phychain_interface_config_get(unit, port, phy_access, nof_phys, 1595 0, ref_clock, 1596 &phy_interface_config)); 1597 1598 config->speed = phy_interface_config.data_rate; 1599 config->interface_modes = phy_interface_config.interface_modes; 1600 config->flags = 0; 1601 config->interface = interface_config->interface; 1602 rv = portmod_intf_from_phymod_intf (unit, 1603 phy_interface_config.interface_type, &(config->interface)); 1604 _SOC_IF_ERR_EXIT(rv); 1605 1606 rv = unimac_encap_get(unit, port, &config->encap_mode); 1607 _SOC_IF_ERR_EXIT(rv); 1608 1609 config->port_num_lanes = interface_config->port_num_lanes; 1610 config->max_speed = interface_config->max_speed; 1611 config->pll_divider_req = interface_config->pll_divider_req; 1612 config->interface_modes = interface_config->interface_modes; 1613 1614 exit: 1615 SOC_FUNC_RETURN; 1616 } 1617 1618 int pm_qtc_port_default_interface_get(int unit, int port, pm_info_t pm_info, const portmod_port_interface_config_t* config, soc_port_if_t* interface) 1619 { 1620 *interface = SOC_PORT_IF_NULL; 1621 return SOC_E_NONE; 1622 } 1623 1624 int pm_qtc_port_loopback_get(int unit, int port, pm_info_t pm_info, 1625 portmod_loopback_mode_t loopback_type, int* enable) 1626 { 1627 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1628 int nof_phys; 1629 uint32_t tmp_enable=0; 1630 phymod_loopback_mode_t phymod_lb_type; 1631 1632 SOC_INIT_FUNC_DEFS; 1633 1634 switch(loopback_type){ 1635 case portmodLoopbackMacOuter: 1636 _SOC_IF_ERR_EXIT(unimac_loopback_get(unit, port, enable)); 1637 break; 1638 1639 case portmodLoopbackPhyGloopPMD: 1640 case portmodLoopbackPhyRloopPMD: /*slide*/ 1641 case portmodLoopbackPhyGloopPCS: /*slide*/ 1642 if(PM_QTC_INFO(pm_info)->nof_phys == 0) { 1643 (*enable) = 0; /* No phy --> no phy loopback*/ 1644 } else { 1645 _SOC_IF_ERR_EXIT(portmod_commmon_portmod_to_phymod_loopback_type(unit, 1646 loopback_type, &phymod_lb_type)); 1647 _SOC_IF_ERR_EXIT 1648 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1649 phy_access ,(1+MAX_PHYN), 1650 &nof_phys)); 1651 1652 _SOC_IF_ERR_EXIT(portmod_port_phychain_loopback_get(unit, port, 1653 phy_access, 1654 nof_phys, 1655 phymod_lb_type, 1656 &tmp_enable)); 1657 *enable = tmp_enable; 1658 1659 } 1660 break; 1661 default: 1662 (*enable) = 0; /* not supported --> no loopback */ 1663 break; 1664 } 1665 1666 exit: 1667 SOC_FUNC_RETURN; 1668 1669 } 1670 1671 int pm_qtc_port_loopback_set (int unit, int port, pm_info_t pm_info, 1672 portmod_loopback_mode_t loopback_type, int enable) 1673 { 1674 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1675 int nof_phys; 1676 phymod_loopback_mode_t phymod_lb_type; 1677 1678 SOC_INIT_FUNC_DEFS; 1679 1680 /* 1681 PM_QTC_PHY_ACCESS_GET(unit, port, pm_info, phy_acc); 1682 */ 1683 1684 /* loopback type validation*/ 1685 switch(loopback_type){ 1686 case portmodLoopbackMacOuter: 1687 _SOC_IF_ERR_EXIT(unimac_loopback_set(unit, port, enable)); 1688 break; 1689 1690 case portmodLoopbackPhyGloopPMD: 1691 case portmodLoopbackPhyRloopPMD: /*slide*/ 1692 case portmodLoopbackPhyGloopPCS: /*slide*/ 1693 if(PM_QTC_INFO(pm_info)->nof_phys != 0) { 1694 if (enable) { 1695 _SOC_IF_ERR_EXIT(unimac_loopback_set(unit, port, 0)); 1696 } 1697 _SOC_IF_ERR_EXIT(portmod_commmon_portmod_to_phymod_loopback_type(unit, 1698 loopback_type, &phymod_lb_type)); 1699 1700 _SOC_IF_ERR_EXIT 1701 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1702 phy_access ,(1+MAX_PHYN), 1703 &nof_phys)); 1704 1705 _SOC_IF_ERR_EXIT(portmod_port_phychain_loopback_set(unit, port, 1706 phy_access, 1707 nof_phys, 1708 phymod_lb_type, 1709 enable)); 1710 } 1711 break; 1712 default: 1713 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, ( 1714 _SOC_MSG("unsupported loopback type %d"), loopback_type)); 1715 break; 1716 } 1717 #if 0 1718 if (enable) 1719 _SOC_IF_ERR_EXIT(_gport_lag_failover_status_toggle(unit, pm_info, port)); 1720 #endif 1721 exit: 1722 SOC_FUNC_RETURN; 1723 1724 } 1725 1726 int pm_qtc_port_rx_mac_enable_set(int unit, int port, pm_info_t pm_info, int enable) 1727 { 1728 SOC_INIT_FUNC_DEFS; 1729 1730 _SOC_IF_ERR_EXIT(unimac_rx_enable_set(unit, port, enable)); 1731 1732 exit: 1733 SOC_FUNC_RETURN; 1734 1735 } 1736 1737 int pm_qtc_port_rx_mac_enable_get(int unit, int port, pm_info_t pm_info, int* enable) 1738 { 1739 SOC_INIT_FUNC_DEFS; 1740 1741 _SOC_IF_ERR_EXIT(unimac_rx_enable_get(unit, port, enable)); 1742 1743 exit: 1744 SOC_FUNC_RETURN; 1745 1746 } 1747 1748 int pm_qtc_port_ability_local_get (int unit, int port, pm_info_t pm_info, 1749 portmod_port_ability_t* ability) 1750 { 1751 portmod_port_interface_config_t *interface_config; 1752 int fiber_pref, port_index; 1753 /* int max_speed = 1000; */ 1754 int num_of_lanes = 0 ; 1755 uint32 bitmap, tmpbit ; 1756 1757 1758 if (_pm_qtc_port_index_get (unit, port, pm_info, &port_index, &bitmap)) 1759 return (SOC_E_PARAM); 1760 1761 interface_config = &(PM_QTC_INFO(pm_info)->port_config[port_index].interface_config); 1762 1763 fiber_pref = PHYMOD_INTF_MODES_FIBER_GET(interface_config); 1764 /* max_speed = interface_config->max_speed; */ 1765 1766 tmpbit = bitmap ; 1767 while(tmpbit) { 1768 num_of_lanes += ((tmpbit&1)?1:0) ; 1769 tmpbit >>= 1 ; 1770 } 1771 1772 sal_memset(ability, 0, sizeof(*ability)); 1773 1774 1775 ability->loopback = SOC_PA_LB_PHY | SOC_PA_LB_MAC; 1776 ability->medium = SOC_PA_MEDIUM_FIBER; 1777 ability->pause = SOC_PA_PAUSE | SOC_PA_PAUSE_ASYMM; 1778 ability->flags = SOC_PA_AUTONEG; 1779 ability->speed_half_duplex = SOC_PA_ABILITY_NONE; 1780 1781 if (num_of_lanes==1) { 1782 ability->speed_full_duplex |= SOC_PA_SPEED_10MB | 1783 SOC_PA_SPEED_100MB | 1784 SOC_PA_SPEED_1000MB | 1785 SOC_PA_SPEED_2500MB; 1786 1787 /* 1788 if (fiber_pref) { 1789 ability->speed_full_duplex |= SOC_PA_SPEED_2500MB | 1790 SOC_PA_SPEED_10GB; 1791 ability->speed_full_duplex |= SOC_PA_SPEED_100MB; 1792 } else { 1793 ability->speed_full_duplex |= SOC_PA_SPEED_10MB | 1794 SOC_PA_SPEED_100MB; 1795 } 1796 */ 1797 1798 ability->pause = SOC_PA_PAUSE | SOC_PA_PAUSE_ASYMM; 1799 ability->interface = SOC_PA_INTF_GMII | SOC_PA_INTF_SGMII; 1800 ability->medium = SOC_PA_MEDIUM_FIBER; 1801 1802 } else { 1803 1804 ability->speed_full_duplex = SOC_PA_SPEED_1000MB; 1805 if (fiber_pref) { 1806 ability->speed_full_duplex |= SOC_PA_SPEED_2500MB; 1807 ability->speed_full_duplex |= SOC_PA_SPEED_100MB; 1808 } else { 1809 ability->speed_full_duplex |= SOC_PA_SPEED_10MB | 1810 SOC_PA_SPEED_100MB; 1811 } 1812 ability->pause = SOC_PA_PAUSE | SOC_PA_PAUSE_ASYMM; 1813 ability->interface = SOC_PA_INTF_XGMII; 1814 ability->medium = SOC_PA_MEDIUM_FIBER; 1815 ability->flags = SOC_PA_AUTONEG; 1816 } 1817 1818 LOG_INFO(BSL_LS_SOC_PHY, 1819 (BSL_META_U(unit, 1820 "%-22s:unit=%d p=%d sp=%08x bitmap=%x\n"), 1821 __FUNCTION__, unit, port, ability->speed_full_duplex, bitmap)); 1822 1823 return (SOC_E_NONE); 1824 } 1825 1826 static int _pm_qtc_nof_lanes_get(int unit, int port, pm_info_t pm_info) 1827 { 1828 int port_index, rv; 1829 uint32_t bitmap, bcnt = 0; 1830 1831 rv = _pm_qtc_port_index_get (unit, port, pm_info, &port_index, 1832 &bitmap); 1833 if (rv) return (0); /* bit count is zero will flag error */ 1834 1835 while (bitmap) { 1836 if (bitmap & 0x1) bcnt++; 1837 bitmap >>= 1; 1838 } 1839 1840 return (bcnt); 1841 1842 } 1843 1844 int pm_qtc_port_autoneg_set (int unit, int port, pm_info_t pm_info, 1845 const phymod_autoneg_control_t* an) 1846 { 1847 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1848 int nof_phys; 1849 int port_index; 1850 uint32_t bitmap; 1851 phymod_autoneg_control_t *pAn = (phymod_autoneg_control_t*)an; 1852 1853 SOC_INIT_FUNC_DEFS; 1854 1855 _SOC_IF_ERR_EXIT(_pm_qtc_port_index_get (unit, port, pm_info, &port_index, 1856 &bitmap)); 1857 1858 if(PM_QTC_INFO(pm_info)->nof_phys == 0) { 1859 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, (_SOC_MSG("AN isn't supported"))); 1860 } else { 1861 if (pAn->num_lane_adv == 0) { 1862 pAn->num_lane_adv = _pm_qtc_nof_lanes_get(unit, port, pm_info); 1863 } 1864 1865 pAn->an_mode = PM_QTC_INFO(pm_info)->port_config[port_index].port_init_config.an_mode; 1866 1867 if (pAn->an_mode == phymod_AN_MODE_NONE) { 1868 pAn->an_mode = phymod_AN_MODE_SGMII; 1869 } 1870 1871 _SOC_IF_ERR_EXIT 1872 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1873 phy_access ,(1+MAX_PHYN), 1874 &nof_phys)); 1875 1876 _SOC_IF_ERR_EXIT 1877 (portmod_port_phychain_autoneg_set(unit, port, phy_access, nof_phys, an)); 1878 } 1879 1880 exit: 1881 SOC_FUNC_RETURN; 1882 1883 1884 } 1885 1886 int pm_qtc_port_autoneg_get (int unit, int port, pm_info_t pm_info, 1887 phymod_autoneg_control_t* an) 1888 { 1889 return SOC_E_NONE; 1890 1891 } 1892 1893 int pm_qtc_port_autoneg_status_get (int unit, int port, pm_info_t pm_info, 1894 phymod_autoneg_status_t* an_status) 1895 { 1896 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1897 int nof_phys; 1898 1899 SOC_INIT_FUNC_DEFS; 1900 1901 if(PM_QTC_INFO(pm_info)->nof_phys == 0) { 1902 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, (_SOC_MSG("Autoneg isn't supported"))); 1903 } else { 1904 _SOC_IF_ERR_EXIT 1905 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1906 phy_access ,(1+MAX_PHYN), 1907 &nof_phys)); 1908 _SOC_IF_ERR_EXIT 1909 (portmod_port_phychain_autoneg_status_get(phy_access, nof_phys, an_status)); 1910 } 1911 1912 exit: 1913 SOC_FUNC_RETURN; 1914 1915 } 1916 1917 int pm_qtc_port_link_get(int unit, int port, pm_info_t pm_info, int flags, int* link) 1918 { 1919 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1920 int nof_phys; 1921 SOC_INIT_FUNC_DEFS; 1922 1923 _SOC_IF_ERR_EXIT 1924 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1925 phy_access ,(1+MAX_PHYN), 1926 &nof_phys)); 1927 _SOC_IF_ERR_EXIT 1928 (portmod_port_phychain_link_status_get(phy_access, nof_phys, flags, (uint32_t*) link)); 1929 exit: 1930 SOC_FUNC_RETURN; 1931 } 1932 1933 int pm_qtc_port_mac_link_get(int unit, int port, pm_info_t pm_info, int* link) 1934 { 1935 return SOC_E_NONE; 1936 } 1937 1938 1939 int pm_qtc_port_prbs_config_set(int unit, int port, pm_info_t pm_info, 1940 portmod_prbs_mode_t mode, int flags, const phymod_prbs_t* config) 1941 { 1942 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1943 int nof_phys; 1944 1945 SOC_INIT_FUNC_DEFS; 1946 1947 if(mode == 1 /*MAC*/) { 1948 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 1949 (_SOC_MSG("MAC PRBS is not supported for PMQTC"))); 1950 } 1951 1952 if(PM_QTC_INFO(pm_info)->nof_phys == 0) { 1953 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, 1954 (_SOC_MSG("phy PRBS isn't supported"))); 1955 } 1956 1957 _SOC_IF_ERR_EXIT 1958 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1959 phy_access ,(1+MAX_PHYN), 1960 &nof_phys)); 1961 _SOC_IF_ERR_EXIT 1962 (portmod_port_phychain_prbs_config_set(phy_access, nof_phys, flags, config)); 1963 1964 exit: 1965 SOC_FUNC_RETURN; 1966 } 1967 1968 int pm_qtc_port_prbs_config_get (int unit, int port, pm_info_t pm_info, 1969 portmod_prbs_mode_t mode, int flags, phymod_prbs_t* config) 1970 { 1971 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1972 int nof_phys; 1973 SOC_INIT_FUNC_DEFS; 1974 1975 if(mode == 1 /*MAC*/) { 1976 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 1977 (_SOC_MSG("MAC PRBS is not supported for PMQTC"))); 1978 } 1979 1980 if(PM_QTC_INFO(pm_info)->nof_phys == 0) { 1981 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, 1982 (_SOC_MSG("phy PRBS isn't supported"))); 1983 } 1984 1985 _SOC_IF_ERR_EXIT 1986 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1987 phy_access ,(1+MAX_PHYN), 1988 &nof_phys)); 1989 _SOC_IF_ERR_EXIT 1990 (portmod_port_phychain_prbs_config_get(phy_access, nof_phys, flags, config)); 1991 1992 exit: 1993 SOC_FUNC_RETURN; 1994 } 1995 1996 1997 int pm_qtc_port_prbs_enable_set (int unit, int port, pm_info_t pm_info, 1998 portmod_prbs_mode_t mode, int flags, int enable) 1999 { 2000 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2001 int nof_phys; 2002 SOC_INIT_FUNC_DEFS; 2003 2004 if(mode == 1 /*MAC*/) { 2005 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ( 2006 _SOC_MSG("MAC PRBS is not supported for PMQTC"))); 2007 } 2008 2009 if(PM_QTC_INFO(pm_info)->nof_phys == 0) { 2010 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, ( 2011 _SOC_MSG("phy PRBS isn't supported"))); 2012 } 2013 2014 _SOC_IF_ERR_EXIT 2015 (portmod_port_chain_phy_access_get(unit, port, pm_info, 2016 phy_access ,(1+MAX_PHYN), 2017 &nof_phys)); 2018 _SOC_IF_ERR_EXIT 2019 (portmod_port_phychain_prbs_enable_set(phy_access, nof_phys, flags, enable)); 2020 2021 exit: 2022 SOC_FUNC_RETURN; 2023 } 2024 2025 int pm_qtc_port_prbs_enable_get (int unit, int port, pm_info_t pm_info, 2026 portmod_prbs_mode_t mode, int flags, int* enable) 2027 { 2028 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2029 uint32 is_enabled; 2030 int nof_phys; 2031 SOC_INIT_FUNC_DEFS; 2032 2033 if(mode == 1 /*MAC*/) { 2034 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 2035 (_SOC_MSG("MAC PRBS is not supported for PMQTC"))); 2036 } 2037 2038 if(PM_QTC_INFO(pm_info)->nof_phys == 0) { 2039 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, 2040 (_SOC_MSG("phy PRBS isn't supported"))); 2041 } 2042 2043 _SOC_IF_ERR_EXIT 2044 (portmod_port_chain_phy_access_get(unit, port, pm_info, 2045 phy_access ,(1+MAX_PHYN), 2046 &nof_phys)); 2047 2048 _SOC_IF_ERR_EXIT 2049 (portmod_port_phychain_prbs_enable_get(phy_access, nof_phys, flags, &is_enabled)); 2050 2051 (*enable) = (is_enabled ? 1 : 0); 2052 2053 exit: 2054 SOC_FUNC_RETURN; 2055 } 2056 2057 2058 int pm_qtc_port_prbs_status_get(int unit, int port, pm_info_t pm_info, 2059 portmod_prbs_mode_t mode, int flags, phymod_prbs_status_t* status) 2060 { 2061 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2062 int nof_phys; 2063 SOC_INIT_FUNC_DEFS; 2064 2065 if(mode == 1 /*MAC*/) { 2066 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 2067 (_SOC_MSG("MAC PRBS is not supported for PMQTC"))); 2068 } 2069 2070 if(PM_QTC_INFO(pm_info)->nof_phys == 0) { 2071 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, 2072 (_SOC_MSG("phy PRBS isn't supported"))); 2073 } 2074 2075 _SOC_IF_ERR_EXIT 2076 (portmod_port_chain_phy_access_get(unit, port, pm_info, 2077 phy_access ,(1+MAX_PHYN), 2078 &nof_phys)); 2079 _SOC_IF_ERR_EXIT 2080 (portmod_port_phychain_prbs_status_get(phy_access, nof_phys, flags, status)); 2081 2082 exit: 2083 SOC_FUNC_RETURN; 2084 2085 } 2086 2087 2088 int pm_qtc_port_firmware_mode_set (int unit, int port, pm_info_t pm_info, 2089 phymod_firmware_mode_t fw_mode) 2090 { 2091 2092 return SOC_E_NONE; 2093 2094 } 2095 2096 int pm_qtc_port_firmware_mode_get (int unit, int port, pm_info_t pm_info, 2097 phymod_firmware_mode_t* fw_mode) 2098 { 2099 2100 2101 return SOC_E_NONE; 2102 } 2103 2104 2105 int pm_qtc_port_runt_threshold_set (int unit, int port, 2106 pm_info_t pm_info, int value) 2107 { 2108 2109 return SOC_E_NONE; 2110 2111 } 2112 2113 int pm_qtc_port_runt_threshold_get(int unit, int port, pm_info_t pm_info, int* value) 2114 { 2115 2116 return SOC_E_NONE; 2117 2118 } 2119 2120 2121 int pm_qtc_port_max_packet_size_set (int unit, int port, 2122 pm_info_t pm_info, int value) 2123 { 2124 SOC_INIT_FUNC_DEFS; 2125 2126 _SOC_IF_ERR_EXIT(unimac_rx_max_size_set(unit, port, value)); 2127 2128 exit: 2129 SOC_FUNC_RETURN; 2130 2131 } 2132 2133 int pm_qtc_port_max_packet_size_get (int unit, int port, 2134 pm_info_t pm_info, int* value) 2135 { 2136 SOC_INIT_FUNC_DEFS; 2137 _SOC_IF_ERR_EXIT(unimac_rx_max_size_get(unit, port, value)); 2138 2139 exit: 2140 SOC_FUNC_RETURN; 2141 2142 } 2143 2144 2145 int pm_qtc_port_pad_size_set(int unit, int port, pm_info_t pm_info, int value) 2146 { 2147 return SOC_E_NONE; 2148 2149 } 2150 2151 int pm_qtc_port_pad_size_get(int unit, int port, pm_info_t pm_info, int* value) 2152 { 2153 return SOC_E_NONE; 2154 2155 2156 } 2157 2158 2159 int pm_qtc_port_tx_drop_on_local_fault_set (int unit, int port, 2160 pm_info_t pm_info, int enable) 2161 { 2162 return SOC_E_NONE; 2163 } 2164 2165 int pm_qtc_port_tx_drop_on_local_fault_get (int unit, int port, 2166 pm_info_t pm_info, int* enable) 2167 { 2168 return SOC_E_NONE; 2169 } 2170 2171 2172 int pm_qtc_port_tx_drop_on_remote_fault_set(int unit, int port, 2173 pm_info_t pm_info, int enable) 2174 { 2175 return SOC_E_NONE; 2176 } 2177 2178 int pm_qtc_port_tx_drop_on_remote_fault_get (int unit, int port, 2179 pm_info_t pm_info, int* enable) 2180 { 2181 return SOC_E_NONE; 2182 } 2183 2184 int pm_qtc_port_local_fault_enable_set (int unit, int port, 2185 pm_info_t pm_info, int enable) 2186 { 2187 return SOC_E_NONE; 2188 } 2189 2190 int pm_qtc_port_local_fault_enable_get (int unit, int port, 2191 pm_info_t pm_info, int* enable) 2192 { 2193 return SOC_E_NONE; 2194 } 2195 2196 int pm_qtc_port_local_fault_status_get(int unit, int port, 2197 pm_info_t pm_info, int* value) 2198 { 2199 return SOC_E_NONE; 2200 } 2201 2202 int pm_qtc_port_local_fault_control_set(int unit, int port, pm_info_t pm_info, 2203 const portmod_local_fault_control_t* control) 2204 { 2205 return SOC_E_NONE; 2206 } 2207 2208 int pm_qtc_port_local_fault_control_get(int unit, int port, pm_info_t pm_info, 2209 portmod_local_fault_control_t* control) 2210 { 2211 return SOC_E_NONE; 2212 } 2213 2214 int pm_qtc_port_remote_fault_status_get(int unit, int port, 2215 pm_info_t pm_info, int* value) 2216 { 2217 return SOC_E_NONE; 2218 } 2219 2220 int pm_qtc_port_remote_fault_control_set(int unit, int port, pm_info_t pm_info, 2221 const portmod_remote_fault_control_t* control) 2222 { 2223 return SOC_E_NONE; 2224 } 2225 2226 int pm_qtc_port_remote_fault_control_get(int unit, int port, pm_info_t pm_info, 2227 portmod_remote_fault_control_t* control) 2228 { 2229 return SOC_E_NONE; 2230 } 2231 2232 2233 int pm_qtc_port_pause_control_set(int unit, int port, pm_info_t pm_info, 2234 const portmod_pause_control_t* control) 2235 { 2236 return SOC_E_NONE; 2237 } 2238 2239 int pm_qtc_port_pause_control_get(int unit, int port, pm_info_t pm_info, 2240 portmod_pause_control_t* control) 2241 { 2242 return SOC_E_NONE; 2243 } 2244 2245 int pm_qtc_port_llfc_control_set(int unit, int port, 2246 pm_info_t pm_info, const portmod_llfc_control_t* control) 2247 { 2248 return SOC_E_NONE; 2249 } 2250 2251 int pm_qtc_port_llfc_control_get(int unit, int port, 2252 pm_info_t pm_info, portmod_llfc_control_t* control) 2253 { 2254 return SOC_E_NONE; 2255 } 2256 2257 int pm_qtc_port_core_access_get (int unit, int port, 2258 pm_info_t pm_info, int phyn, int max_cores, 2259 phymod_core_access_t* core_access_arr, 2260 int* nof_cores, 2261 int* is_most_ext) 2262 { 2263 return SOC_E_NONE; 2264 } 2265 2266 int pm_qtc_ext_phy_attach_to_pm(int unit, pm_info_t pm_info, const phymod_core_access_t *ext_phy_access, uint32 first_phy_lane) 2267 { 2268 return SOC_E_NONE; 2269 } 2270 2271 int pm_qtc_ext_phy_detach_from_pm(int unit, pm_info_t pm_info, phymod_core_access_t *ext_phy_access) 2272 { 2273 return SOC_E_NONE; 2274 } 2275 2276 /*! 2277 * pm_qtc_port_frame_spacing_stretch_set 2278 * 2279 * @brief Port Mac Control Spacing Stretch 2280 * 2281 * @param [in] unit - unit id 2282 * @param [in] port - logical port 2283 * @param [in] spacing - 2284 */ 2285 int pm_qtc_port_frame_spacing_stretch_set (int unit, int port, 2286 pm_info_t pm_info,int spacing) 2287 { 2288 return SOC_E_NONE; 2289 } 2290 2291 /*! 2292 * pm_qtc_port_frame_spacing_stretch_get 2293 * 2294 * @brief Port Mac Control Spacing Stretch 2295 * 2296 * @param [in] unit - unit id 2297 * @param [in] port - logical port 2298 * @param [in] spacing - 2299 */ 2300 int pm_qtc_port_frame_spacing_stretch_get (int unit, int port, 2301 pm_info_t pm_info, 2302 const int *spacing) 2303 { 2304 return SOC_E_NONE; 2305 } 2306 2307 /*! 2308 * pm_qtc_port_diag_fifo_status_get 2309 * 2310 * @brief get port timestamps in fifo 2311 * 2312 * @param [in] unit - unit id 2313 * @param [in] port - logical port 2314 * @param [in] diag_info - 2315 */ 2316 int pm_qtc_port_diag_fifo_status_get (int unit, int port,pm_info_t pm_info, 2317 const portmod_fifo_status_t* diag_info) 2318 { 2319 return SOC_E_NONE; 2320 } 2321 2322 /*! 2323 * pm_qtc_port_pfc_config_set 2324 * 2325 * @brief set pass control frames. 2326 * 2327 * @param [in] unit - unit id 2328 * @param [in] port - logical port 2329 * @param [in] pfc_cfg - 2330 */ 2331 int pm_qtc_port_pfc_config_set (int unit, int port,pm_info_t pm_info, 2332 const portmod_pfc_config_t* pfc_cfg) 2333 { 2334 /* return(unimac_pfc_config_set(unit, port, pfc_cfg)); */ 2335 return SOC_E_NONE; 2336 } 2337 2338 2339 /*! 2340 * pm_qtc_port_pfc_config_get 2341 * 2342 * @brief set pass control frames. 2343 * 2344 * @param [in] unit - unit id 2345 * @param [in] port - logical port 2346 * @param [in] pfc_cfg - 2347 */ 2348 int pm_qtc_port_pfc_config_get (int unit, int port,pm_info_t pm_info, 2349 const portmod_pfc_config_t* pfc_cfg) 2350 { 2351 /* return (unimac_pfc_config_get (unit, port, pfc_cfg)); */ 2352 return SOC_E_NONE; 2353 } 2354 2355 int pm_qtc_port_pfc_control_set(int unit, int port, pm_info_t pm_info, const portmod_pfc_control_t* control) 2356 { 2357 2358 return SOC_E_NONE; 2359 2360 } 2361 2362 int pm_qtc_port_pfc_control_get(int unit, int port, pm_info_t pm_info, portmod_pfc_control_t* control) 2363 { 2364 2365 2366 return SOC_E_NONE; 2367 } 2368 2369 /*! 2370 * pm_qtc_port_eee_set 2371 * 2372 * @brief set EEE control and timers 2373 * 2374 * @param [in] unit - unit id 2375 * @param [in] port - logical port 2376 * @param [in] eee - 2377 */ 2378 int pm_qtc_port_eee_set(int unit, int port, pm_info_t pm_info,const portmod_eee_t* eee) 2379 { 2380 return SOC_E_NONE; 2381 } 2382 2383 /*! 2384 * pm_qtc_port_eee_get 2385 * 2386 * @brief get EEE control and timers 2387 * 2388 * @param [in] unit - unit id 2389 * @param [in] port - logical port 2390 * @param [in] eee - 2391 */ 2392 int pm_qtc_port_eee_get(int unit, int port, pm_info_t pm_info, portmod_eee_t* eee) 2393 { 2394 return SOC_E_NONE; 2395 } 2396 2397 /*! 2398 * pm_qtc_port_vlan_tag_set 2399 * 2400 * @brief vlan tag set. 2401 * 2402 * @param [in] unit - unit id 2403 * @param [in] port - logical port 2404 * @param [in] vlan_tag - 2405 */ 2406 int pm_qtc_port_vlan_tag_set(int unit, int port, pm_info_t pm_info,const portmod_vlan_tag_t* vlan_tag) 2407 { 2408 return SOC_E_NONE; 2409 } 2410 2411 2412 /*! 2413 * pm_qtc_port_vlan_tag_get 2414 * 2415 * @brief vlan tag get. 2416 * 2417 * @param [in] unit - unit id 2418 * @param [in] port - logical port 2419 * @param [in] vlan_tag - 2420 */ 2421 int pm_qtc_port_vlan_tag_get(int unit, int port, pm_info_t pm_info, portmod_vlan_tag_t* vlan_tag) 2422 { 2423 return SOC_E_NONE; 2424 } 2425 2426 /*! 2427 * pm_qtc_port_duplex_set 2428 * 2429 * @brief duplex set. 2430 * 2431 * @param [in] unit - unit id 2432 * @param [in] port - logical port 2433 * @param [in] enable - 2434 */ 2435 int pm_qtc_port_duplex_set(int unit, int port, pm_info_t pm_info,int enable) 2436 { 2437 return SOC_E_NONE; 2438 } 2439 2440 2441 /*! 2442 * pm_qtc_port_duplex_get 2443 * 2444 * @brief duplex get. 2445 * 2446 * @param [in] unit - unit id 2447 * @param [in] port - logical port 2448 * @param [in] vlan_tag - 2449 */ 2450 int pm_qtc_port_duplex_get(int unit, int port, pm_info_t pm_info, int* enable) 2451 { 2452 return SOC_E_NONE; 2453 } 2454 2455 /*! 2456 * pm_qtc_port_speed_get 2457 * 2458 * @brief duplex get. 2459 * 2460 * @param [in] unit - unit id 2461 * @param [in] port - logical port 2462 * @param [in] speed - 2463 */ 2464 int pm_qtc_port_speed_get(int unit, int port, pm_info_t pm_info, int* speed) 2465 { 2466 return SOC_E_NONE; 2467 } 2468 2469 int pm_qtc_port_phy_reg_read(int unit, int port, pm_info_t pm_info, int lane, int flags, int reg_addr, uint32* value) 2470 { 2471 return SOC_E_NONE; 2472 } 2473 2474 int pm_qtc_port_phy_reg_write(int unit, int port, pm_info_t pm_info, int lane, int flags, int reg_addr, uint32 value) 2475 { 2476 return SOC_E_NONE; 2477 } 2478 2479 int pm_qtc_port_reset_set (int unit, int port, pm_info_t pm_info, 2480 int reset_mode, int opcode, int direction) 2481 { 2482 return SOC_E_NONE; 2483 } 2484 2485 int pm_qtc_port_reset_get (int unit, int port, pm_info_t pm_info, 2486 int reset_mode, int opcode, int* direction) 2487 { 2488 return SOC_E_NONE; 2489 } 2490 2491 /*Port remote Adv get*/ 2492 int pm_qtc_port_adv_remote_get (int unit, int port, pm_info_t pm_info, 2493 int* ability_mask) 2494 { 2495 return (0); 2496 } 2497 2498 /*get port auto negotiation local ability*/ 2499 int pm_qtc_port_ability_advert_get(int unit, int port, pm_info_t pm_info, 2500 portmod_port_ability_t* ability) 2501 { 2502 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2503 int nof_phys = 0; 2504 phymod_autoneg_ability_t an_ability; 2505 portmod_port_ability_t port_ability; 2506 int phy_index; 2507 2508 SOC_INIT_FUNC_DEFS; 2509 2510 _SOC_IF_ERR_EXIT 2511 (portmod_port_chain_phy_access_get(unit, port, pm_info, 2512 phy_access ,(1+MAX_PHYN), 2513 &nof_phys)); 2514 2515 _SOC_IF_ERR_EXIT 2516 (portmod_port_phychain_autoneg_ability_get(unit, port, phy_access, nof_phys, 2517 &an_ability, &port_ability)); 2518 2519 phy_index = nof_phys -1; 2520 if (phy_index && PORTMOD_IS_LEGACY_PHY_GET(&(phy_access[phy_index].access))) { 2521 sal_memcpy(ability, &port_ability, sizeof(portmod_port_ability_t)); 2522 } else { 2523 portmod_common_phy_to_port_ability(&an_ability, ability); 2524 } 2525 2526 exit: 2527 SOC_FUNC_RETURN; 2528 } 2529 2530 int pm_qtc_port_ability_advert_set(int unit, int port, pm_info_t pm_info, 2531 portmod_port_ability_t* ability) 2532 { 2533 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2534 int nof_phys = 0, port_index; 2535 uint32 bitmap; 2536 portmod_port_ability_t port_ability; 2537 phymod_autoneg_ability_t an_ability; 2538 portmod_access_get_params_t params; 2539 pm_qtc_port_t *pInfo = NULL; 2540 2541 int port_num_lanes, line_interface, cx4_10g; 2542 int an_cl72, an_fec, hg_mode; 2543 2544 SOC_INIT_FUNC_DEFS; 2545 2546 _SOC_IF_ERR_EXIT(_pm_qtc_port_index_get (unit, port, pm_info, &port_index, 2547 &bitmap)); 2548 pInfo = &(PM_QTC_INFO(pm_info)->port_config[port_index]); 2549 2550 2551 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 2552 params.lane = -1; 2553 params.phyn = 0; 2554 params.sys_side = PORTMOD_SIDE_LINE; 2555 2556 _SOC_IF_ERR_EXIT 2557 (pm_qtc_port_ability_local_get(unit, port, pm_info, &port_ability)); 2558 2559 /* Make sure to advertise only abilities supported by the port */ 2560 port_ability.pause &= ability->pause; 2561 port_ability.interface &= ability->interface; 2562 port_ability.medium &= ability->medium; 2563 port_ability.eee &= ability->eee; 2564 port_ability.loopback &= ability->loopback; 2565 port_ability.flags &= ability->flags; 2566 port_ability.speed_half_duplex &= ability->speed_half_duplex; 2567 port_ability.speed_full_duplex &= ability->speed_full_duplex; 2568 2569 port_num_lanes = pInfo->interface_config.port_num_lanes; 2570 line_interface = pInfo->interface_config.interface; 2571 cx4_10g = pInfo->port_init_config.cx4_10g; 2572 an_cl72 = pInfo->port_init_config.an_cl72; 2573 an_fec = pInfo->port_init_config.an_fec; 2574 hg_mode = PHYMOD_INTF_MODES_HIGIG_GET(&pInfo->interface_config); 2575 2576 portmod_common_port_to_phy_ability(&port_ability, &an_ability, 2577 port_num_lanes, line_interface, cx4_10g, 2578 an_cl72, an_fec, hg_mode); 2579 2580 _SOC_IF_ERR_EXIT 2581 (portmod_port_chain_phy_access_get(unit, port, pm_info, 2582 phy_access ,(1+MAX_PHYN), 2583 &nof_phys)); 2584 2585 _SOC_IF_ERR_EXIT 2586 (portmod_port_phychain_autoneg_ability_set(unit, port, phy_access, nof_phys, 2587 &an_ability, &port_ability)); 2588 2589 LOG_VERBOSE(BSL_LS_BCM_PORT, 2590 (BSL_META_U(unit, 2591 "Speed(HD=0x%08x, FD=0x%08x) Pause=0x%08x orig(HD=0x%08x, FD=0x%08x) \n" 2592 "Interface=0x%08x Medium=0x%08x Loopback=0x%08x Flags=0x%08x\n"), 2593 port_ability.speed_half_duplex, 2594 port_ability.speed_full_duplex, 2595 port_ability.pause, 2596 ability->speed_half_duplex, 2597 ability->speed_full_duplex, 2598 port_ability.interface, 2599 port_ability.medium, port_ability.loopback, 2600 port_ability.flags)); 2601 exit: 2602 SOC_FUNC_RETURN; 2603 } 2604 2605 /*Port ability remote Adv get*/ 2606 int pm_qtc_port_ability_remote_get(int unit, int port, pm_info_t pm_info, 2607 portmod_port_ability_t* ability) 2608 { 2609 return SOC_E_NONE; 2610 } 2611 2612 int pm_qtc_port_rx_control_set (int unit, int port, pm_info_t pm_info, 2613 const portmod_rx_control_t* rx_ctrl) 2614 { 2615 return SOC_E_NONE; 2616 } 2617 2618 int pm_qtc_port_tx_mac_sa_set(int unit, int port, pm_info_t pm_info, sal_mac_addr_t mac_addr) 2619 { 2620 return SOC_E_NONE; 2621 } 2622 2623 2624 int pm_qtc_port_tx_mac_sa_get(int unit, int port, pm_info_t pm_info, sal_mac_addr_t mac_addr) 2625 { 2626 return SOC_E_NONE; 2627 } 2628 2629 int pm_qtc_port_rx_mac_sa_set(int unit, int port, pm_info_t pm_info, sal_mac_addr_t mac_addr) 2630 { 2631 return SOC_E_NONE; 2632 } 2633 2634 2635 int pm_qtc_port_rx_mac_sa_get(int unit, int port, pm_info_t pm_info, sal_mac_addr_t mac_addr) 2636 { 2637 return SOC_E_NONE; 2638 } 2639 2640 int pm_qtc_port_tx_average_ipg_set (int unit, int port, 2641 pm_info_t pm_info, int value) 2642 { 2643 return SOC_E_NONE; 2644 } 2645 2646 2647 int pm_qtc_port_tx_average_ipg_get (int unit, int port, 2648 pm_info_t pm_info, int* value) 2649 { 2650 return SOC_E_NONE; 2651 } 2652 2653 int pm_qtc_port_update (int unit, int port, pm_info_t pm_info, 2654 const portmod_port_update_control_t* update_control) 2655 { 2656 return SOC_E_NONE; 2657 } 2658 2659 int pm_qtc_port_drv_name_get (int unit, int port, pm_info_t pm_info, 2660 char* buf, int len) 2661 { 2662 return SOC_E_NONE; 2663 } 2664 2665 int pm_qtc_port_clear_rx_lss_status_set (int unit, soc_port_t port, 2666 pm_info_t pm_info, int lcl_fault, int rmt_fault) 2667 { 2668 return SOC_E_NONE; 2669 } 2670 2671 int pm_qtc_port_clear_rx_lss_status_get (int unit, soc_port_t port, 2672 pm_info_t pm_info, int *lcl_fault, int *rmt_fault) 2673 { 2674 return SOC_E_NONE; 2675 } 2676 2677 int pm_qtc_port_lag_failover_status_toggle (int unit, soc_port_t port, pm_info_t pm_info) 2678 { 2679 return SOC_E_NONE; 2680 } 2681 2682 int pm_qtc_port_lag_failover_loopback_set (int unit, soc_port_t port, 2683 pm_info_t pm_info, int value) 2684 { 2685 return SOC_E_NONE; 2686 } 2687 2688 int pm_qtc_port_lag_failover_loopback_get (int unit, soc_port_t port, 2689 pm_info_t pm_info, int *value) 2690 { 2691 return SOC_E_NONE; 2692 } 2693 2694 int pm_qtc_port_mode_set(int unit, soc_port_t port, 2695 pm_info_t pm_info, const portmod_port_mode_info_t *mode) 2696 { 2697 return SOC_E_NONE; 2698 } 2699 2700 int pm_qtc_port_mode_get(int unit, soc_port_t port, 2701 pm_info_t pm_info, portmod_port_mode_info_t *mode) 2702 { 2703 return SOC_E_NONE; 2704 } 2705 2706 int 2707 pm_qtc_port_trunk_hwfailover_config_set(int unit, soc_port_t port, pm_info_t pm_info, int hw_count) 2708 { 2709 return SOC_E_NONE; 2710 } 2711 2712 int 2713 pm_qtc_port_trunk_hwfailover_config_get(int unit, soc_port_t port, pm_info_t pm_info, 2714 int *enable) 2715 { 2716 return SOC_E_NONE; 2717 } 2718 2719 2720 int 2721 pm_qtc_port_trunk_hwfailover_status_get(int unit, soc_port_t port, pm_info_t pm_info, 2722 int *loopback) 2723 { 2724 return SOC_E_NONE; 2725 } 2726 2727 int pm_qtc_port_diag_ctrl(int unit, soc_port_t port, pm_info_t pm_info, 2728 uint32 inst, int op_type, int op_cmd, const void *arg) 2729 { 2730 return SOC_E_NONE; 2731 } 2732 2733 int 2734 pm_qtc_port_ref_clk_get(int unit, soc_port_t port, pm_info_t pm_info, int *ref_clk) 2735 { 2736 return SOC_E_NONE; 2737 } 2738 2739 int pm_qtc_port_lag_remove_failover_lpbk_get(int unit, int port, pm_info_t pm_info, int *val) 2740 { 2741 return SOC_E_NONE; 2742 } 2743 2744 int pm_qtc_port_lag_remove_failover_lpbk_set(int unit, int port, pm_info_t pm_info, int val) 2745 { 2746 return SOC_E_NONE; 2747 } 2748 2749 int pm_qtc_port_lag_failover_disable(int unit, int port, pm_info_t pm_info) 2750 { 2751 return SOC_E_NONE; 2752 } 2753 2754 int pm_qtc_port_mac_ctrl_set(int unit, int port, 2755 pm_info_t pm_info, uint64 ctrl) 2756 { 2757 return SOC_E_NONE; 2758 } 2759 2760 int pm_qtc_port_drain_cell_get(int unit, int port, 2761 pm_info_t pm_info, portmod_drain_cells_t *drain_cells) 2762 { 2763 return SOC_E_NONE; 2764 } 2765 2766 int pm_qtc_port_drain_cell_stop (int unit, int port, 2767 pm_info_t pm_info, const portmod_drain_cells_t *drain_cells) 2768 { 2769 return (SOC_E_NONE); 2770 } 2771 2772 int pm_qtc_port_drain_cell_start(int unit, int port, pm_info_t pm_info) 2773 { 2774 return SOC_E_NONE; 2775 } 2776 2777 int pm_qtc_port_txfifo_cell_cnt_get(int unit, int port, 2778 pm_info_t pm_info, uint32* fval) 2779 { 2780 /* return(unimac_txfifo_cell_cnt_get(unit, port, fval)); */ 2781 *fval =0; 2782 return SOC_E_NONE; 2783 } 2784 2785 int pm_qtc_port_egress_queue_drain_get(int unit, int port, 2786 pm_info_t pm_info, uint64 *ctrl, int *rx) 2787 { 2788 return SOC_E_NONE; 2789 } 2790 2791 int pm_qtc_port_drain_cells_rx_enable (int unit, int port, 2792 pm_info_t pm_info, int rx_en) 2793 { 2794 return SOC_E_NONE; 2795 } 2796 2797 int pm_qtc_port_egress_queue_drain_rx_en(int unit, int port, 2798 pm_info_t pm_info, int rx_en) 2799 { 2800 return SOC_E_NONE; 2801 } 2802 2803 int pm_qtc_port_mac_reset_set(int unit, int port, 2804 pm_info_t pm_info, int val) 2805 { 2806 return SOC_E_NONE; 2807 } 2808 2809 int pm_qtc_port_mac_reset_get(int unit, int port, pm_info_t pm_info, int* val) 2810 { 2811 return SOC_E_NONE; 2812 } 2813 2814 int pm_qtc_port_mac_reset_check(int unit, int port, pm_info_t pm_info, 2815 int enable, int* reset) 2816 { 2817 return SOC_E_NONE; 2818 } 2819 2820 int pm_qtc_port_core_num_get(int unit, int port, pm_info_t pm_info, 2821 int* core_num) 2822 { 2823 return SOC_E_NONE; 2824 } 2825 2826 int pm_qtc_port_e2ecc_hdr_set (int unit, int port, pm_info_t pm_info, 2827 const portmod_port_higig_e2ecc_hdr_t* e2ecc_hdr) 2828 { 2829 return SOC_E_NONE; 2830 } 2831 2832 2833 int pm_qtc_port_e2ecc_hdr_get (int unit, int port, pm_info_t pm_info, 2834 portmod_port_higig_e2ecc_hdr_t* e2ecc_hdr) 2835 { 2836 return (SOC_E_NONE); 2837 } 2838 2839 int pm_qtc_port_e2e_enable_set (int unit, int port, pm_info_t pm_info, int enable) 2840 { 2841 return (SOC_E_NONE); 2842 } 2843 2844 2845 int pm_qtc_port_e2e_enable_get (int unit, int port, pm_info_t pm_info, int *enable) 2846 { 2847 return (SOC_E_NONE); 2848 } 2849 2850 int pm_qtc_port_fallback_lane_get(int unit, int port, pm_info_t pm_info, int* fallback_lane) 2851 { 2852 return (SOC_E_NONE); 2853 } 2854 2855 STATIC 2856 int pm_qtc_port_soft_reset(int unit, int port, pm_info_t pm_info, int in_out) 2857 { 2858 return (SOC_E_NONE); 2859 } 2860 2861 2862 /*Port discard set*/ 2863 int pm_qtc_port_discard_set(int unit, int port, pm_info_t pm_info, int discard) 2864 { 2865 return (SOC_E_NONE); 2866 /* return(unimac_discard_set(unit, port, discard)); */ 2867 } 2868 2869 2870 2871 2872 #endif /* PORTMOD_PM_QTC_SUPPORT */ 2873 2874 #undef _ERR_MSG_MODULE_NAME