pm4x10_qtc.c (238762B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <soc/drv.h> 11 #include <soc/types.h> 12 #include <soc/error.h> 13 #include <soc/wb_engine.h> 14 #include <soc/portmod/portmod_internal.h> 15 #include <soc/portmod/portmod_common.h> 16 #include <soc/portmod/portmod.h> 17 #include <soc/portmod/portmod_dispatch.h> 18 #include <soc/portmod/portmod_chain.h> 19 20 #include <soc/portmod/unimac.h> 21 #include <soc/portmod/pm4x10_qtc.h> 22 #include <soc/portmod/pm4x10.h> 23 #include <soc/portmod/pm_qtc.h> 24 25 #include <soc/portmod/portmod_system.h> 26 27 #ifdef _ERR_MSG_MODULE_NAME 28 #error "_ERR_MSG_MODULE_NAME redefined" 29 #endif 30 #define _ERR_MSG_MODULE_NAME BSL_LS_SOC_PORT 31 32 #ifdef PORTMOD_PM4X10_QTC_SUPPORT 33 34 #define PM_4x10_QTC_INFO(pm_info) ((pm_info)->pm_data.pm4x10_qtc_db) 35 36 #define PM4X10_QTC_LANES_PER_CORE (4) 37 #define MAX_PORTS_PER_PM4X10_QTC (16) 38 #define PM4X10_QTC_MAX_PORTS_PER_LANE (4) 39 40 /* WB defines */ 41 #define PM4x10_QTC_WB_BUFFER_VERSION (2) 42 43 #define PM4x10_QTC_IS_INITIALIZED_SET(unit, pm_info, is_initialized) \ 44 SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isInitialized], &is_initialized) 45 #define PM4x10_QTC_IS_INITIALIZED_GET(unit, pm_info, is_initialized) \ 46 SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isInitialized], is_initialized) 47 48 #define PM4x10_QTC_IS_ACTIVE_SET(unit, pm_info, is_active) \ 49 SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isActive], &is_active) 50 #define PM4x10_QTC_IS_ACTIVE_GET(unit, pm_info, is_active) \ 51 SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isActive], is_active) 52 53 #define PM4x10_QTC_QTC_MODE_SET(unit, pm_info, qtc_mode) \ 54 SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[qtcMode], &qtc_mode) 55 #define PM4x10_QTC_QTC_MODE_GET(unit, pm_info, qtc_mode) \ 56 SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[qtcMode], qtc_mode) 57 58 #define PM4x10_QTC_ACTIVE_PORT_NUM_SET(unit, pm_info, active_port_num) \ 59 SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[activePortNum], &active_port_num) 60 #define PM4x10_QTC_ACTIVE_PORT_NUM_GET(unit, pm_info, active_port_num) \ 61 SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[activePortNum], active_port_num) 62 63 #define PM4x10_QTC_PORTS_SET(unit, pm_info, port, port_index) \ 64 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[ports], \ 65 &port, port_index) 66 #define PM4x10_QTC_PORTS_GET(unit, pm_info, port, port_index) \ 67 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[ports], \ 68 port, port_index) 69 70 #define PM4x10_QTC_PHY_TYPE_SET(unit, pm_info, type) \ 71 SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[phyType], &type) 72 #define PM4x10_QTC_PHY_TYPE_GET(unit, pm_info, type) \ 73 SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[phyType], type) 74 75 #define PM4x10_QTC_SPEED_SET(unit, pm_info, speed, port_index) \ 76 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 77 pm_info->wb_vars_ids[dataRate], &speed, port_index) 78 #define PM4x10_QTC_SPEED_GET(unit, pm_info, speed, port_index) \ 79 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 80 pm_info->wb_vars_ids[dataRate], speed, port_index) 81 82 #define PM4x10_QTC_MAX_SPEED_SET(unit, pm_info, max_speed, port_index) \ 83 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 84 pm_info->wb_vars_ids[maxSpeed], &max_speed, port_index) 85 #define PM4x10_QTC_MAX_SPEED_GET(unit, pm_info, max_speed, port_index) \ 86 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 87 pm_info->wb_vars_ids[maxSpeed], max_speed, port_index) 88 89 #define PM4x10_QTC_INTERFACE_TYPE_SET(unit, pm_info, interface_type, port_index) \ 90 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 91 pm_info->wb_vars_ids[interfaceType], &interface_type, port_index) 92 #define PM4x10_QTC_INTERFACE_TYPE_GET(unit, pm_info, interface_type, port_index) \ 93 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 94 pm_info->wb_vars_ids[interfaceType], interface_type, port_index) 95 96 #define PM4x10_QTC_AN_MODE_SET(unit, pm_info, an_mode, port_index) \ 97 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 98 pm_info->wb_vars_ids[anMode], &an_mode, port_index) 99 #define PM4x10_QTC_AN_MODE_GET(unit, pm_info, an_mode, port_index) \ 100 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 101 pm_info->wb_vars_ids[anMode], an_mode, port_index) 102 103 #define PM4x10_QTC_PORT_LANE_CONNECTION_DB_SET(unit, pm_info, lane_connection_db, xphy_idx, port_index) \ 104 SOC_WB_ENGINE_SET_DBL_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[laneConnectionDb], \ 105 (uint8 *)lane_connection_db, port_index, xphy_idx) 106 #define PM4x10_QTC_PORT_LANE_CONNECTION_DB_GET(unit, pm_info, lane_connection_db, xphy_idx, port_index) \ 107 SOC_WB_ENGINE_GET_DBL_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[laneConnectionDb], \ 108 (uint8 *)lane_connection_db, port_index, xphy_idx) 109 110 #define PM4x10_QTC_PORT_NUM_PHYS_SET(unit, pm_info, nof_phys, port_index) \ 111 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[nofPhys], nof_phys, port_index) 112 #define PM4x10_QTC_PORT_NUM_PHYS_GET(unit, pm_info, nof_phys, port_index) \ 113 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[nofPhys], nof_phys, port_index) 114 115 #define PM4x10_QTC_PORT_DYNAMIC_STATE_SET(unit, pm_info, dynamic_state, port_index) \ 116 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 117 pm_info->wb_vars_ids[portDynamicState], &dynamic_state, port_index) 118 #define PM4x10_QTC_PORT_DYNAMIC_STATE_GET(unit, pm_info, dynamic_state, port_index) \ 119 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 120 pm_info->wb_vars_ids[portDynamicState], dynamic_state, port_index) 121 122 #define PM4x10_QTC_IS_INTERFACE_RESTORE_SET(unit, pm_info, is_interface_restore, \ 123 port_index) \ 124 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 125 pm_info->wb_vars_ids[isInterfaceRestore], \ 126 &is_interface_restore, port_index) 127 #define PM4x10_QTC_IS_INTERFACE_RESTORE_GET(unit, pm_info, is_interface_restore, \ 128 port_index) \ 129 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, \ 130 pm_info->wb_vars_ids[isInterfaceRestore], \ 131 is_interface_restore, port_index) 132 133 typedef enum pm4x10_qtc_wb_vars{ 134 isInitialized, 135 isActive, 136 qtcMode, 137 activePortNum, /* Active port number of the PM4x10_QTC core*/ 138 phyType, 139 ports, 140 dataRate, /* port speed - phy_intf_config.data_rate */ 141 maxSpeed, /* Max Port Speed Supported */ 142 interfaceType, /* interface of type soc_port_if_t */ 143 anMode, 144 laneConnectionDb, /* represents the physical topology of the serdes and ext phy lanes */ 145 nofPhys, /* number of phys for the port */ 146 portDynamicState, 147 isInterfaceRestore /*indicate whether interface should be restored from DB*/ 148 }pm4x10_qtc_wb_vars_t; 149 150 struct pm4x10_qtc_s{ 151 pm_info_t pm4x10; 152 portmod_pbmp_t phys; 153 int first_phy; 154 phymod_ref_clk_t ref_clk; 155 phymod_polarity_t polarity; 156 phymod_lane_map_t lane_map; 157 phymod_firmware_load_method_t fw_load_method; 158 phymod_firmware_loader_f external_fw_loader; 159 phymod_core_access_t int_core_access; 160 int nof_phys[MAX_PORTS_PER_PM4X10_QTC]; /* internal + External Phys for each lane*/ 161 portmod_xphy_lane_connection_t lane_conn[MAX_PHYN][MAX_PORTS_PER_PM4X10_QTC]; 162 uint8 default_fw_loader_is_used; 163 uint8 default_bus_is_used; 164 portmod_phy_external_reset_f portmod_phy_external_reset; 165 portmod_mac_soft_reset_f portmod_mac_soft_reset; 166 int core_num; 167 uint32 core_clock_khz; 168 int warmboot_skip_db_restore; 169 }; 170 171 #define PM4x10_INFO(pm_info) PM_4x10_QTC_INFO(pm_info)->pm4x10 172 173 #define PM4x10_QTC_LOCAL_VARIABLE_DEFS \ 174 portmod_qtc_mode_t qtc_mode = portmodQtcModeInvalid 175 176 #define PM4x10_QTC_QMOD_GET(pm_info) \ 177 do { \ 178 _SOC_IF_ERR_EXIT(PM4x10_QTC_QTC_MODE_GET(unit, pm_info, &qtc_mode)); \ 179 } while (0) 180 181 #define IS_QMOD ((qtc_mode == portmodQtcModeQsgmii) || \ 182 (qtc_mode == portmodQtcModeUsxgmii)) 183 184 #define PM4x10_QTC_CORE_ACTIVE_GET(core_is_active) \ 185 do { \ 186 core_is_active = 0; \ 187 _SOC_IF_ERR_EXIT(PM4x10_QTC_ACTIVE_PORT_NUM_GET(unit, pm_info, &active_port_num)); \ 188 if (active_port_num) { \ 189 core_is_active = 1; \ 190 } \ 191 } while (0) 192 193 #define PORTMOD_PM4x10_QTC_IS_GEN1(pm_version) ((pm_version.type == PM_TYPE_PM4X10Q) && (pm_version.gen == PM_GEN1)) 194 #define PORTMOD_PM4x10_QTC_IS_GEN1_GEN2(pm_version) ((pm_version.type == PM_TYPE_PM4X10Q) && ((pm_version.gen == PM_GEN1) || (pm_version.gen == PM_GEN2))) 195 #define PORTMOD_PM4x10_QTC_IS_GEN2_16nm(pm_version) ((pm_version.type == PM_TYPE_PM4X10Q) && (pm_version.gen == PM_GEN2) && (pm_version.tech_process == PM_TECH_16NM)) 196 #define PORTMOD_PM4x10_QTC_IS_GEN2_28nm(pm_version) ((pm_version.type == PM_TYPE_PM4X10Q) && (pm_version.gen == PM_GEN2) && (pm_version.tech_process == PM_TECH_28NM)) 197 #define PORTMOD_PM4x10_QTC_REVISION_IS_A0(pm_version) ((pm_version.revision_letter == PM_REVISION_A) && (pm_version.revision_number == PM_REVISION_0)) 198 199 #define UNIMAC_MEM_INIT_DONE_MASK 0xffff 200 #define GP_GMIB_MEM_INIT_DONE_MASK 0xf0000 201 202 int _pm4x10_qtc_port_autoneg_set(int unit, int port, pm_info_t pm_info, uint32 phy_flags, const phymod_autoneg_control_t* an); 203 204 #if 0 205 STATIC 206 int _pm4x10_qtc_pm_version_get(int unit, int port, pm_info_t pm_info, pm_version_t *version) 207 { 208 uint32 reg_val, pm_type; 209 int reg_port; 210 portmod_default_user_access_t *user_data; 211 SOC_INIT_FUNC_DEFS; 212 213 user_data = (portmod_default_user_access_t*)PM_4x10_QTC_INFO(pm_info)->int_core_access.access.user_acc; 214 reg_port = user_data->blk_id | SOC_REG_ADDR_BLOCK_ID_MASK; 215 version->type = PM_TYPE_INVALID; 216 version->gen = PM_GEN_INVALID; 217 version->tech_process = PM_TECH_INVALID; 218 version->revision_number = PM_REVISION_NUM_INVALID; 219 version->revision_letter = PM_REVISION_LETTER_INVALID; 220 221 /* 222 * PM version ID register is not defined in PM GEN1. 223 */ 224 if (SOC_REG_IS_VALID(unit, PMQ_PM_VERSION_IDr)) { 225 _SOC_IF_ERR_EXIT(READ_PMQ_PM_VERSION_IDr(unit, reg_port, ®_val)); 226 227 pm_type = soc_reg_field_get(unit, PMQ_PM_VERSION_IDr, reg_val, PM_TYPEf); 228 if (pm_type == 3) { 229 version->type = PM_TYPE_PM4X10Q; 230 version->gen = PM_GEN2; 231 } 232 /* The hardware value of techology/revision starts from 0 */ 233 version->tech_process = soc_reg_field_get(unit, PMQ_PM_VERSION_IDr, reg_val, TECH_PROCESSf) +1; 234 version->revision_number = soc_reg_field_get(unit, PMQ_PM_VERSION_IDr, reg_val, REV_NUMBERf) + 1; 235 version->revision_letter = soc_reg_field_get(unit, PMQ_PM_VERSION_IDr, reg_val, REV_LETTERf) + 1; 236 } else { 237 version->type = PM_TYPE_PM4X10Q; 238 version->gen = PM_GEN1; 239 } 240 241 exit: 242 SOC_FUNC_RETURN; 243 } 244 #endif 245 246 int pm4x10_qtc_pm_interface_type_is_supported(int unit, soc_port_if_t interface, 247 int* is_supported) 248 { 249 SOC_INIT_FUNC_DEFS; 250 switch(interface){ 251 case SOC_PORT_IF_SGMII: 252 case SOC_PORT_IF_QSGMII: 253 case SOC_PORT_IF_GMII: 254 *is_supported = TRUE; 255 break; 256 default: 257 *is_supported = FALSE; 258 break; 259 } 260 if (*is_supported == FALSE) { 261 _SOC_IF_ERR_EXIT(pm4x10_pm_interface_type_is_supported(unit, interface, is_supported)); 262 } 263 264 exit: 265 SOC_FUNC_RETURN; 266 } 267 268 int portmod_pm4x10_qtc_wb_upgrade_func(int unit, void *arg, int recovered_version, int new_version) 269 { 270 pm_info_t pm_info; 271 SOC_INIT_FUNC_DEFS; 272 273 pm_info = arg; 274 PM_4x10_QTC_INFO(pm_info)->warmboot_skip_db_restore = TRUE; 275 276 SOC_FUNC_RETURN; 277 } 278 279 STATIC 280 int pm4x10_qtc_wb_buffer_init(int unit, int wb_buffer_index, pm_info_t pm_info) 281 { 282 /* Declare the common variables needed for warmboot */ 283 WB_ENGINE_INIT_TABLES_DEFS; 284 int wb_var_id, rv; 285 int buffer_id = wb_buffer_index; /*required by SOC_WB_ENGINE_ADD_ Macros*/ 286 uint32 is_initialized, is_active; 287 int qtc_mode, active_port_num, lane, phyn, phy_type; 288 portmod_xphy_lane_connection_t lane_conn; 289 SOC_INIT_FUNC_DEFS; 290 291 COMPILER_REFERENCE(buffer_is_dynamic); 292 293 SOC_WB_ENGINE_ADD_BUFF(SOC_WB_ENGINE_PORTMOD, wb_buffer_index, "pm4x10_qtc", 294 portmod_pm4x10_qtc_wb_upgrade_func, pm_info, 295 PM4x10_QTC_WB_BUFFER_VERSION, 1, SOC_WB_ENGINE_PRE_RELEASE); 296 _SOC_IF_ERR_EXIT(rv); 297 298 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 299 SOC_WB_ENGINE_ADD_VAR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "is_initialized", 300 wb_buffer_index, sizeof(uint32), NULL, VERSION(1)); 301 _SOC_IF_ERR_EXIT(rv); 302 pm_info->wb_vars_ids[isInitialized] = wb_var_id; 303 304 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 305 SOC_WB_ENGINE_ADD_VAR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "is_active", 306 wb_buffer_index, sizeof(uint32), NULL, VERSION(1)); 307 _SOC_IF_ERR_EXIT(rv); 308 pm_info->wb_vars_ids[isActive] = wb_var_id; 309 310 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 311 SOC_WB_ENGINE_ADD_VAR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "qtc_mode", 312 wb_buffer_index, sizeof(int), NULL, VERSION(1)); 313 _SOC_IF_ERR_EXIT(rv); 314 pm_info->wb_vars_ids[qtcMode] = wb_var_id; 315 316 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 317 SOC_WB_ENGINE_ADD_VAR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "active_port_num", 318 wb_buffer_index, sizeof(int), NULL, VERSION(1)); 319 _SOC_IF_ERR_EXIT(rv); 320 pm_info->wb_vars_ids[activePortNum] = wb_var_id; 321 322 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 323 SOC_WB_ENGINE_ADD_VAR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "phy_type", 324 wb_buffer_index, sizeof(int), NULL, VERSION(1)); 325 _SOC_IF_ERR_EXIT(rv); 326 pm_info->wb_vars_ids[phyType] = wb_var_id; 327 328 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 329 SOC_WB_ENGINE_ADD_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "ports", 330 wb_buffer_index, sizeof(int), NULL, MAX_PORTS_PER_PM4X10_QTC, 331 VERSION(1)); 332 _SOC_IF_ERR_EXIT(rv); 333 pm_info->wb_vars_ids[ports] = wb_var_id; 334 335 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 336 SOC_WB_ENGINE_ADD_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "data_rate", 337 wb_buffer_index, sizeof(int), NULL, 338 MAX_PORTS_PER_PM4X10_QTC, VERSION(1)); 339 _SOC_IF_ERR_EXIT(rv); 340 pm_info->wb_vars_ids[dataRate] = wb_var_id; 341 342 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 343 SOC_WB_ENGINE_ADD_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "max_speed", 344 wb_buffer_index, sizeof(uint32), NULL, 345 MAX_PORTS_PER_PM4X10_QTC, VERSION(1)); 346 _SOC_IF_ERR_EXIT(rv); 347 pm_info->wb_vars_ids[maxSpeed] = wb_var_id; 348 349 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 350 SOC_WB_ENGINE_ADD_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "interface_type", 351 wb_buffer_index, sizeof(uint32), NULL, 352 MAX_PORTS_PER_PM4X10_QTC, VERSION(1)); 353 _SOC_IF_ERR_EXIT(rv); 354 pm_info->wb_vars_ids[interfaceType] = wb_var_id; 355 356 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 357 SOC_WB_ENGINE_ADD_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "an_mode", 358 wb_buffer_index, sizeof(uint32), NULL, 359 MAX_PORTS_PER_PM4X10_QTC, VERSION(1)); 360 _SOC_IF_ERR_EXIT(rv); 361 pm_info->wb_vars_ids[anMode] = wb_var_id; 362 363 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 364 SOC_WB_ENGINE_ADD_2D_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "lane_connection_db", 365 wb_buffer_index, sizeof(portmod_xphy_lane_connection_t), NULL, 366 MAX_PORTS_PER_PM4X10_QTC, MAX_PHYN, VERSION(1)); 367 _SOC_IF_ERR_EXIT(rv); 368 pm_info->wb_vars_ids[laneConnectionDb] = wb_var_id; 369 370 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 371 SOC_WB_ENGINE_ADD_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "nof_phys", 372 wb_buffer_index, sizeof(int), NULL, 373 MAX_PORTS_PER_PM4X10_QTC, VERSION(1)); 374 _SOC_IF_ERR_EXIT(rv); 375 pm_info->wb_vars_ids[nofPhys] = wb_var_id; 376 377 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 378 SOC_WB_ENGINE_ADD_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, "port_dynamic_state", 379 wb_buffer_index, sizeof(uint32_t), NULL, 380 MAX_PORTS_PER_PM4X10_QTC, VERSION(1)); 381 _SOC_IF_ERR_EXIT(rv); 382 pm_info->wb_vars_ids[portDynamicState] = wb_var_id; 383 384 _SOC_IF_ERR_EXIT(portmod_next_wb_var_id_get(unit, &wb_var_id)); 385 SOC_WB_ENGINE_ADD_ARR(SOC_WB_ENGINE_PORTMOD, wb_var_id, 386 "is_interface_restore", wb_buffer_index, 387 sizeof(uint32), NULL, MAX_PORTS_PER_PM4X10_QTC, 388 VERSION(2)); 389 _SOC_IF_ERR_EXIT(rv); 390 pm_info->wb_vars_ids[isInterfaceRestore] = wb_var_id; 391 392 _SOC_IF_ERR_EXIT(soc_wb_engine_init_buffer(unit, SOC_WB_ENGINE_PORTMOD, wb_buffer_index, FALSE)); 393 394 if(!SOC_WARM_BOOT(unit)){ 395 is_initialized = 0; 396 _SOC_IF_ERR_EXIT(PM4x10_QTC_IS_INITIALIZED_SET(unit, pm_info, is_initialized)); 397 398 is_active = 0; 399 _SOC_IF_ERR_EXIT(PM4x10_QTC_IS_ACTIVE_SET(unit, pm_info, is_active)); 400 401 qtc_mode = 0; 402 _SOC_IF_ERR_EXIT(PM4x10_QTC_QTC_MODE_SET(unit, pm_info, qtc_mode)); 403 404 active_port_num = 0; 405 _SOC_IF_ERR_EXIT(PM4x10_QTC_ACTIVE_PORT_NUM_SET(unit, pm_info, active_port_num)); 406 407 phy_type = 0; 408 _SOC_IF_ERR_EXIT(PM4x10_QTC_PHY_TYPE_SET(unit, pm_info, phy_type)); 409 410 rv = SOC_WB_ENGINE_MEMSET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 411 pm_info->wb_vars_ids[ports], -1); 412 _SOC_IF_ERR_EXIT(rv); 413 rv = SOC_WB_ENGINE_MEMSET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 414 pm_info->wb_vars_ids[dataRate], 0); 415 _SOC_IF_ERR_EXIT(rv); 416 rv = SOC_WB_ENGINE_MEMSET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 417 pm_info->wb_vars_ids[maxSpeed], 0); 418 _SOC_IF_ERR_EXIT(rv); 419 rv = SOC_WB_ENGINE_MEMSET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 420 pm_info->wb_vars_ids[interfaceType], _SHR_PORT_IF_COUNT); 421 _SOC_IF_ERR_EXIT(rv); 422 423 rv = SOC_WB_ENGINE_MEMSET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 424 pm_info->wb_vars_ids[anMode], phymod_AN_MODE_Count); 425 _SOC_IF_ERR_EXIT(rv); 426 for(phyn = 0 ; phyn < MAX_PHYN ; phyn++){ 427 for(lane = 0 ; lane < PM4X10_QTC_LANES_PER_CORE ; lane++) { 428 portmod_xphy_lane_connection_t_init(unit, &lane_conn); 429 _SOC_IF_ERR_EXIT(PM4x10_QTC_PORT_LANE_CONNECTION_DB_SET(unit, pm_info, 430 &lane_conn, phyn, lane)); 431 } 432 } 433 rv = SOC_WB_ENGINE_MEMSET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 434 pm_info->wb_vars_ids[nofPhys], 0); 435 _SOC_IF_ERR_EXIT(rv); 436 437 rv = SOC_WB_ENGINE_MEMSET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 438 pm_info->wb_vars_ids[portDynamicState], 0); 439 _SOC_IF_ERR_EXIT(rv); 440 441 rv = SOC_WB_ENGINE_MEMSET_ARR(unit, SOC_WB_ENGINE_PORTMOD, 442 pm_info->wb_vars_ids[isInterfaceRestore], 0); 443 _SOC_IF_ERR_EXIT(rv); 444 } 445 446 exit: 447 SOC_FUNC_RETURN; 448 } 449 450 STATIC portmod_ucode_buf_t pm4x10_qtc_ucode_buf[SOC_MAX_NUM_DEVICES] = {{NULL, 0}}; 451 STATIC portmod_ucode_buf_t pm4x10_qtc_ucode_buf_2nd[SOC_MAX_NUM_DEVICES] = {{NULL, 0}}; 452 453 454 STATIC int 455 pm4x10_qtc_default_fw_loader(const phymod_core_access_t* core, uint32_t length, const uint8_t* data) 456 { 457 int rv; 458 portmod_default_user_access_t *user_data; 459 int unit = ((portmod_default_user_access_t*)core->access.user_acc)->unit; 460 portmod_ucode_buf_order_t load_order; 461 SOC_INIT_FUNC_DEFS; 462 463 user_data = (portmod_default_user_access_t*)core->access.user_acc; 464 /* user_data->blk_id = user_data->blk_id | SOC_REG_ADDR_BLOCK_ID_MASK; */ 465 466 if (PORTMOD_USER_ACCESS_FW_LOAD_REVERSE_GET(user_data)) { 467 load_order = portmod_ucode_buf_order_reversed; 468 } else { 469 load_order = portmod_ucode_buf_order_straight; 470 } 471 472 rv = portmod_firmware_set(unit, 473 user_data->blk_id, 474 data, 475 length, 476 load_order, 477 0, 478 &(pm4x10_qtc_ucode_buf[unit]), 479 &(pm4x10_qtc_ucode_buf_2nd[unit]), 480 PMQPORT_WC_UCMEM_DATAm, 481 PMQPORT_WC_UCMEM_CTRLr); 482 _SOC_IF_ERR_EXIT(rv); 483 484 exit: 485 SOC_FUNC_RETURN; 486 487 } 488 489 STATIC 490 int 491 pm4x10_qtc_default_bus_write(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t val) 492 { 493 return portmod_common_phy_sbus_reg_write(PMQPORT_WC_UCMEM_DATAm, user_acc, core_addr, reg_addr, val); 494 } 495 496 STATIC 497 int 498 pm4x10_qtc_default_bus_read(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t *val) 499 { 500 return portmod_common_phy_sbus_reg_read(PMQPORT_WC_UCMEM_DATAm, user_acc, core_addr, reg_addr, val); 501 } 502 503 phymod_bus_t pm4x10_qtc_default_bus = { 504 "PM4x10_QTC Bus", 505 pm4x10_qtc_default_bus_read, 506 pm4x10_qtc_default_bus_write, 507 NULL, 508 portmod_common_mutex_take, 509 portmod_common_mutex_give, 510 NULL, 511 NULL, 512 PHYMOD_BUS_CAP_WR_MODIFY | PHYMOD_BUS_CAP_LANE_CTRL 513 }; 514 515 STATIC 516 int _pm4x10_qtc_port_index_get(int unit, int port, pm_info_t pm_info, 517 int *first_index, uint32 *bitmap) 518 { 519 int i, tmp_port = 0; 520 SOC_INIT_FUNC_DEFS; 521 522 *first_index = -1; 523 *bitmap = 0; 524 525 for ( i = 0 ; i < MAX_PORTS_PER_PM4X10_QTC; i++) { 526 _SOC_IF_ERR_EXIT(PM4x10_QTC_PORTS_GET(unit, pm_info, &tmp_port, i)); 527 528 if (tmp_port == port) { 529 *first_index = (*first_index == -1) ? i : *first_index; 530 SHR_BITSET(bitmap, i); 531 } 532 } 533 534 if(*first_index == -1) { 535 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, 536 (_SOC_MSG("port was not found in internal DB %d"), port)); 537 } 538 539 exit: 540 SOC_FUNC_RETURN; 541 } 542 543 STATIC 544 int _pm4x10_qtc_pm_qtc_pm_init(int unit, const portmod_pm_create_info_internal_t* pm_add_info, int wb_buffer_index, pm_info_t pm_info) 545 { 546 pm4x10_qtc_t pm4x10_qtc_data = NULL; 547 const portmod_pm_qtc_create_info_t *pm_qtc_info = &pm_add_info->pm_specific_info.pm4x10_qtc.pm_qtc_info; 548 int i, j, nof_phys = 0, lane, phyn, phy; 549 portmod_xphy_lane_connection_t *db_lane_conn; 550 portmod_qtc_mode_t qtc_mode = portmodQtcModeInvalid; 551 SOC_INIT_FUNC_DEFS; 552 553 pm4x10_qtc_data = sal_alloc(sizeof(struct pm4x10_qtc_s), "pm4x10_qtc_specific_db"); 554 SOC_NULL_CHECK(pm4x10_qtc_data); 555 sal_memset(pm4x10_qtc_data, 0, sizeof(struct pm4x10_qtc_s)); 556 pm_info->pm_data.pm4x10_qtc_db = pm4x10_qtc_data; 557 558 PORTMOD_PBMP_ASSIGN(pm4x10_qtc_data->phys, pm_add_info->phys); 559 pm4x10_qtc_data->default_bus_is_used = 0; 560 pm4x10_qtc_data->default_fw_loader_is_used = 0; 561 pm4x10_qtc_data->portmod_phy_external_reset = pm_add_info->pm_specific_info.pm_qtc.portmod_phy_external_reset; 562 pm4x10_qtc_data->portmod_mac_soft_reset = pm_add_info->pm_specific_info.pm_qtc.portmod_mac_soft_reset; 563 for (i = 0 ; i < MAX_PORTS_PER_PM4X10_QTC; i++) { 564 pm4x10_qtc_data->nof_phys[i] = 0; 565 } 566 PORTMOD_PBMP_ITER(pm_add_info->phys, phy) { 567 pm4x10_qtc_data->first_phy = phy; 568 break; 569 } 570 571 /* init intertnal SerDes core access */ 572 phymod_core_access_t_init(&pm4x10_qtc_data->int_core_access); 573 574 /* initialize lane connections */ 575 for (i = 0; i < MAX_PHYN; i++) { 576 for (j = 0; j < MAX_PORTS_PER_PM4X10_QTC; j++) { 577 portmod_xphy_lane_connection_t_init(unit, &pm4x10_qtc_data->lane_conn[i][j]); 578 } 579 } 580 581 _SOC_IF_ERR_EXIT(phymod_firmware_load_method_t_validate( 582 pm_qtc_info->fw_load_method)); 583 584 sal_memcpy(&pm4x10_qtc_data->polarity, &pm_qtc_info->polarity, 585 sizeof(phymod_polarity_t)); 586 sal_memcpy(&(pm4x10_qtc_data->int_core_access.access), &pm_qtc_info->access, 587 sizeof(phymod_access_t)); 588 sal_memcpy(&pm4x10_qtc_data->lane_map, &pm_qtc_info->lane_map, 589 sizeof(pm4x10_qtc_data->lane_map)); 590 pm4x10_qtc_data->ref_clk = pm_qtc_info->ref_clk; 591 pm4x10_qtc_data->fw_load_method = pm_qtc_info->fw_load_method; 592 pm4x10_qtc_data->external_fw_loader = pm_qtc_info->external_fw_loader; 593 pm4x10_qtc_data->core_clock_khz = pm_qtc_info->core_clock_khz; 594 pm4x10_qtc_data->warmboot_skip_db_restore = TRUE; 595 596 if(pm_qtc_info->access.bus == NULL) { 597 /* if null - use default */ 598 pm4x10_qtc_data->int_core_access.access.bus = &pm4x10_qtc_default_bus; 599 pm4x10_qtc_data->default_bus_is_used = 1; 600 } 601 602 if(pm4x10_qtc_data->external_fw_loader == NULL) { 603 /* if null - use default */ 604 pm4x10_qtc_data->external_fw_loader = pm4x10_qtc_default_fw_loader; 605 pm4x10_qtc_data->default_fw_loader_is_used = 1; 606 } 607 608 for (i = 0; i < MAX_PORTS_PER_PM4X10_QTC; i++) { 609 pm4x10_qtc_data->nof_phys[i] = 1; 610 } 611 612 pm4x10_qtc_data->core_num = pm_qtc_info->core_num; 613 614 /*init wb buffer*/ 615 _SOC_IF_ERR_EXIT(pm4x10_qtc_wb_buffer_init(unit, wb_buffer_index, pm_info)); 616 617 if (SOC_WARM_BOOT(unit)) { 618 _SOC_IF_ERR_EXIT(PM4x10_QTC_PHY_TYPE_GET(unit, pm_info, 619 &pm4x10_qtc_data->int_core_access.type)); 620 621 /* restore nof_phys from wb */ 622 for (i = 0; i < MAX_PORTS_PER_PM4X10_QTC; i++) { 623 _SOC_IF_ERR_EXIT(PM4x10_QTC_PORT_NUM_PHYS_GET(unit, pm_info, &nof_phys, i)); 624 pm4x10_qtc_data->nof_phys[i] = nof_phys; 625 } 626 627 for (phyn = 0; phyn < MAX_PHYN; phyn++) { 628 for (lane = 0; lane < MAX_PORTS_PER_PM4X10_QTC; lane++) { 629 db_lane_conn = &(PM_4x10_QTC_INFO(pm_info)->lane_conn[phyn][lane]); 630 _SOC_IF_ERR_EXIT(PM4x10_QTC_PORT_LANE_CONNECTION_DB_GET(unit, pm_info, 631 db_lane_conn, phyn, lane)); 632 } 633 } 634 635 /* restore qtc mode */ 636 _SOC_IF_ERR_EXIT(PM4x10_QTC_QTC_MODE_GET(unit, pm_info, &qtc_mode)); 637 if (qtc_mode == portmodQtcModeQsgmii) { 638 PM_4x10_QTC_INFO(pm_info)->int_core_access.access.flags |= PHYMOD_ACC_F_QMODE; 639 } else if (qtc_mode == portmodQtcModeUsxgmii) { 640 PM_4x10_QTC_INFO(pm_info)->int_core_access.access.flags |= PHYMOD_ACC_F_USXMODE; 641 } 642 643 } 644 645 exit: 646 SOC_FUNC_RETURN; 647 } 648 649 STATIC 650 int _pm4x10_qtc_pm4x10_pm_init(int unit, const portmod_pm_create_info_internal_t* pm_add_info, int wb_buffer_index, pm_info_t pm_info) 651 { 652 const portmod_pm4x10_qtc_create_info_t *info = &pm_add_info->pm_specific_info.pm4x10_qtc; 653 int rv; 654 portmod_pm_create_info_internal_t pm4x10_add_info; 655 SOC_INIT_FUNC_DEFS; 656 657 portmod_pm_create_info_internal_t_init(unit, &pm4x10_add_info); 658 659 pm_info->pm_data.pm4x10_qtc_db->pm4x10= sal_alloc(sizeof(struct pm_info_s), "port_macros"); 660 SOC_NULL_CHECK(pm_info->pm_data.pm4x10_qtc_db->pm4x10); 661 sal_memset(pm_info->pm_data.pm4x10_qtc_db->pm4x10, 0, sizeof(struct pm_info_s)); 662 663 /*pm4x10 init*/ 664 PORTMOD_PBMP_ASSIGN(pm4x10_add_info.phys, pm_add_info->phys); 665 pm4x10_add_info.type = portmodDispatchTypePm4x10; 666 sal_memcpy(&pm4x10_add_info.pm_specific_info.pm4x10, &info->pm4x10_info, 667 sizeof(portmod_pm4x10_create_info_t)); 668 rv = __portmod__dispatch__[pm4x10_add_info.type]->f_portmod_pm_init(unit, 669 &pm4x10_add_info, wb_buffer_index, pm_info->pm_data.pm4x10_qtc_db->pm4x10); 670 _SOC_IF_ERR_EXIT(rv); 671 672 exit: 673 SOC_FUNC_RETURN; 674 } 675 676 int pm4x10_qtc_pm_init(int unit, const portmod_pm_create_info_internal_t* pm_add_info, int wb_buffer_index, pm_info_t pm_info) 677 { 678 int pm4x10_wb_buffer_id; 679 SOC_INIT_FUNC_DEFS; 680 681 pm_info->unit = unit; 682 pm_info->type = portmodDispatchTypePm4x10_qtc; 683 pm_info->wb_buffer_id = wb_buffer_index; 684 685 /*pm_qtc init*/ 686 _SOC_IF_ERR_EXIT(_pm4x10_qtc_pm_qtc_pm_init(unit, pm_add_info, 687 wb_buffer_index, pm_info)); 688 689 /*pm4x10 init*/ 690 pm4x10_wb_buffer_id = wb_buffer_index + 1; 691 _SOC_IF_ERR_EXIT(_pm4x10_qtc_pm4x10_pm_init(unit, pm_add_info, 692 pm4x10_wb_buffer_id, pm_info)); 693 694 exit: 695 if(SOC_FUNC_ERROR){ 696 pm4x10_qtc_pm_destroy(unit, pm_info); 697 } 698 SOC_FUNC_RETURN; 699 } 700 701 int pm4x10_qtc_pm_destroy(int unit, pm_info_t pm_info) 702 { 703 SOC_INIT_FUNC_DEFS; 704 705 if(pm_info->pm_data.pm4x10_qtc_db != NULL) { 706 if (pm_info->pm_data.pm4x10_qtc_db->pm4x10 != NULL) { 707 SOC_IF_ERROR_RETURN(pm4x10_pm_destroy(unit, pm_info->pm_data.pm4x10_qtc_db->pm4x10)); 708 sal_free(pm_info->pm_data.pm4x10_qtc_db->pm4x10); 709 pm_info->pm_data.pm4x10_qtc_db->pm4x10 = NULL; 710 } 711 sal_free(pm_info->pm_data.pm4x10_qtc_db); 712 pm_info->pm_data.pm4x10_qtc_db = NULL; 713 } 714 715 /* free pm4x10_ucode_buf */ 716 if(pm4x10_qtc_ucode_buf[unit].ucode_dma_buf != NULL){ 717 portmod_sys_dma_free(unit, pm4x10_qtc_ucode_buf[unit].ucode_dma_buf); 718 pm4x10_qtc_ucode_buf[unit].ucode_dma_buf = NULL; 719 } 720 pm4x10_qtc_ucode_buf[unit].ucode_alloc_size = 0; 721 722 if (pm4x10_qtc_ucode_buf_2nd[unit].ucode_dma_buf != NULL) { 723 portmod_sys_dma_free(unit, pm4x10_qtc_ucode_buf_2nd[unit].ucode_dma_buf); 724 pm4x10_qtc_ucode_buf_2nd[unit].ucode_dma_buf = NULL; 725 } 726 pm4x10_qtc_ucode_buf_2nd[unit].ucode_alloc_size = 0; 727 728 SOC_FUNC_RETURN; 729 } 730 731 STATIC 732 int _pm4x10_qtc_ext_phy_interface_check(int unit, int port, phymod_phy_access_t *phy_acc, 733 const portmod_port_interface_config_t *interface_config, 734 soc_port_if_t interface, int *is_valid) 735 { 736 int rv = 0; 737 int num_lanes = 0, data_rate = 0; 738 uint32_t interface_mode = 0; 739 phymod_interface_t phymod_intf; 740 int is_legacy_phy = 0, xphy_id; 741 SOC_INIT_FUNC_DEFS; 742 743 num_lanes = interface_config->port_num_lanes; 744 interface_mode = interface_config->interface_modes; 745 data_rate = interface_config->speed; 746 747 xphy_id = phy_acc->access.addr; 748 _SOC_IF_ERR_EXIT(portmod_xphy_is_legacy_phy_get(unit, xphy_id, &is_legacy_phy)); 749 750 if (is_legacy_phy) { 751 /* if its a legacy PHY let the PHY driver decide the valid interface types */ 752 *is_valid = 1; 753 rv = SOC_E_NONE; 754 SOC_EXIT; 755 } 756 757 /* convert portmod interface to phymod interface */ 758 rv = portmod_intf_to_phymod_intf(unit, data_rate, interface, &phymod_intf); 759 _SOC_IF_ERR_EXIT(rv); 760 761 rv = portmod_port_line_interface_is_valid(unit, phy_acc, port, data_rate, phymod_intf, 762 num_lanes, interface_mode, is_valid); 763 _SOC_IF_ERR_EXIT(rv); 764 765 if (!*is_valid) { 766 LOG_ERROR(BSL_LS_BCM_PORT, 767 (BSL_META_UP(unit, port, 768 "ERROR: u=%d p=%d interface type %d not supported by external PHY for this speed %d \n"), 769 unit, port, interface, data_rate)); 770 rv = SOC_E_PARAM; 771 _SOC_IF_ERR_EXIT(rv); 772 } 773 774 exit: 775 SOC_FUNC_RETURN; 776 } 777 778 STATIC 779 int _pm4x10_qtc_interface_check(int unit, int port, pm_info_t pm_info, 780 const portmod_port_interface_config_t *interface_config, 781 soc_port_if_t interface, int *is_valid) 782 { 783 int num_lanes; 784 785 *is_valid = 0; 786 num_lanes = interface_config->port_num_lanes; 787 788 switch (interface_config->speed) { 789 case 0: 790 /* When AN=1 the input speed to portmod may be 0. At 791 * this moment the speed is still undecided so there 792 * is no reason to invalidate the interface type. 793 */ 794 *is_valid = 1; 795 break; 796 case 10: 797 if (num_lanes == 1) { 798 if (SOC_PORT_IF_SGMII == interface) { 799 *is_valid = 1; 800 } 801 } 802 break; 803 case 100: 804 if (num_lanes == 1) { 805 if (SOC_PORT_IF_SGMII == interface) { 806 *is_valid = 1; 807 } 808 } 809 break; 810 case 1000: 811 if (num_lanes == 1) { 812 if ((SOC_PORT_IF_SGMII == interface) || 813 (SOC_PORT_IF_QSGMII == interface)) { 814 *is_valid = 1; 815 } 816 } 817 break; 818 case 2500: 819 if (num_lanes == 1) { 820 if (SOC_PORT_IF_SGMII == interface) { 821 *is_valid = 1; 822 } 823 } 824 break; 825 default: 826 break; 827 } 828 829 return SOC_E_NONE; 830 } 831 832 int _pm4x10_qtc_port_interface_check(int unit, int port, pm_info_t pm_info, 833 const portmod_port_interface_config_t* config, 834 int is_ext_phy, soc_port_if_t interface, 835 int* is_valid) 836 { 837 int nof_phys = 0; 838 phymod_phy_access_t phy_access[1+MAX_PHYN]; 839 SOC_INIT_FUNC_DEFS; 840 841 _SOC_IF_ERR_EXIT 842 (portmod_port_chain_phy_access_get(unit, port, pm_info, phy_access ,(1+MAX_PHYN), &nof_phys)); 843 844 if (is_ext_phy && nof_phys < 2) { 845 return SOC_E_PARAM; 846 } 847 848 if (is_ext_phy) { 849 _SOC_IF_ERR_EXIT(_pm4x10_qtc_ext_phy_interface_check(unit, port, &phy_access[nof_phys-1], config, 850 interface, is_valid)); 851 } else { 852 _SOC_IF_ERR_EXIT(_pm4x10_qtc_interface_check(unit, port, pm_info, config, interface, is_valid)); 853 } 854 855 exit: 856 SOC_FUNC_RETURN; 857 } 858 859 STATIC 860 int _pm4x10_qtc_default_interface_get(int unit, int port, 861 const portmod_port_interface_config_t *interface_config, 862 soc_port_if_t *interface) 863 { 864 *interface = SOC_PORT_IF_SGMII; 865 866 return SOC_E_NONE; 867 } 868 869 int pm4x10_qtc_port_tsc_reset_set(int unit, int port, pm_info_t pm_info, int in_reset) 870 { 871 uint32 reg_val; 872 int reg_port; 873 portmod_default_user_access_t *user_data; 874 SOC_INIT_FUNC_DEFS; 875 876 user_data = (portmod_default_user_access_t*)PM_4x10_QTC_INFO(pm_info)->int_core_access.access.user_acc; 877 reg_port = user_data->blk_id | SOC_REG_ADDR_BLOCK_ID_MASK; 878 879 /* Bring Internal Phy OOR */ 880 _SOC_IF_ERR_EXIT(READ_PMQ_XGXS0_CTRL_REGr(unit, reg_port, ®_val)); 881 soc_reg_field_set(unit, PMQ_XGXS0_CTRL_REGr, ®_val, RSTB_HWf, in_reset ? 0 : 1); 882 soc_reg_field_set(unit, PMQ_XGXS0_CTRL_REGr, ®_val, PWRDWNf, in_reset ? 1 : 0); 883 soc_reg_field_set(unit, PMQ_XGXS0_CTRL_REGr, ®_val, IDDQf, in_reset ? 1 : 0); 884 _SOC_IF_ERR_EXIT(WRITE_PMQ_XGXS0_CTRL_REGr(unit, reg_port, reg_val)); 885 886 /* Based on the feedback from SJ pmd support team, ~10-15usecs would be sufficient 887 * for the PLL/AFE to settle down out of IDDQ reset. 888 */ 889 sal_usleep(10); 890 891 exit: 892 SOC_FUNC_RETURN; 893 } 894 895 static phymod_dispatch_type_t pm4x10_qtc_serdes_list[] = 896 { 897 phymodDispatchTypeQtce, 898 phymodDispatchTypeQtce16, 899 phymodDispatchTypeInvalid 900 }; 901 902 STATIC 903 int _pm4x10_qtc_port_ecc_init(int unit, int port, pm_info_t pm_info) 904 { 905 int reg_port; 906 uint32 reg_val; 907 portmod_default_user_access_t *user_data; 908 soc_timeout_t to; 909 SOC_INIT_FUNC_DEFS; 910 911 user_data = (portmod_default_user_access_t*)PM_4x10_QTC_INFO(pm_info)->int_core_access.access.user_acc; 912 reg_port = user_data->blk_id | SOC_REG_ADDR_BLOCK_ID_MASK; 913 914 /* Init port ecc */ 915 _SOC_IF_ERR_EXIT(READ_PMQ_ECC_INIT_CTRLr(unit, reg_port, ®_val)); 916 soc_reg_field_set(unit, PMQ_ECC_INIT_CTRLr, ®_val, GMIB0_MEM_INITf, 0x1); 917 soc_reg_field_set(unit, PMQ_ECC_INIT_CTRLr, ®_val, GMIB1_MEM_INITf, 0x1); 918 soc_reg_field_set(unit, PMQ_ECC_INIT_CTRLr, ®_val, GP0_MEM_INITf, 0x1); 919 soc_reg_field_set(unit, PMQ_ECC_INIT_CTRLr, ®_val, GP1_MEM_INITf, 0x1); 920 _SOC_IF_ERR_EXIT(WRITE_PMQ_ECC_INIT_CTRLr(unit, reg_port, reg_val)); 921 922 /* Wait for GP/GMIB mem to finish init */ 923 soc_timeout_init(&to, 10, 0); 924 while (!soc_timeout_check(&to)) { 925 _SOC_IF_ERR_EXIT(READ_PMQ_ECC_INIT_STSr(unit, reg_port, ®_val)); 926 if ((reg_val & GP_GMIB_MEM_INIT_DONE_MASK) == GP_GMIB_MEM_INIT_DONE_MASK){ 927 break; 928 } 929 } 930 931 /*Mask the ECC status for each of the UNIMACs*/ 932 _SOC_IF_ERR_EXIT(READ_PMQ_ECCr(unit, reg_port, ®_val)); 933 soc_reg_field_set(unit, PMQ_ECCr, ®_val, PORTNUM_ECCSTS_MASKf, 0xffff); 934 _SOC_IF_ERR_EXIT(WRITE_PMQ_ECCr(unit, reg_port, reg_val)); 935 936 exit: 937 SOC_FUNC_RETURN; 938 } 939 940 STATIC 941 int _pm4x10_qtc_pm_core_probe(int unit, int port, pm_info_t pm_info, const portmod_port_add_info_t* add_info) 942 { 943 int rv = SOC_E_NONE; 944 int temp, phy; 945 portmod_pbmp_t port_phys_in_pm; 946 int probe =0; 947 uint32 xphy_id; 948 uint32 nof_ext_phys =0; 949 int i, is_legacy_phy; 950 portmod_xphy_lane_connection_t lane_conn; 951 phymod_core_access_t core_access; 952 int core_probed; 953 SOC_INIT_FUNC_DEFS; 954 955 sal_memset(&lane_conn,0,sizeof(portmod_xphy_lane_connection_t)); 956 957 /* probe phys (both internal and external cores. */ 958 959 /* Get the first phy related to this port */ 960 PORTMOD_PBMP_ASSIGN(port_phys_in_pm, add_info->phys); 961 PORTMOD_PBMP_AND(port_phys_in_pm, PM_4x10_QTC_INFO(pm_info)->phys); 962 963 /* if internal core is not probe, probe it. Currently checking to type to see 964 phymodDispatchTypeInvalid, later need to move to WB. */ 965 _SOC_IF_ERR_EXIT(portmod_common_serdes_probe(pm4x10_qtc_serdes_list, &PM_4x10_QTC_INFO(pm_info)->int_core_access, &probe)); 966 967 /* save probed phy type to wb. */ 968 if(probe) { 969 rv = PM4x10_QTC_PHY_TYPE_SET(unit, pm_info, PM_4x10_QTC_INFO(pm_info)->int_core_access.type); 970 _SOC_IF_ERR_EXIT(rv); 971 } 972 973 /* probe ext core related to this logical port. */ 974 temp = 0; 975 PORTMOD_PBMP_ITER(PM_4x10_QTC_INFO(pm_info)->phys, phy) { 976 if(PORTMOD_PBMP_MEMBER(port_phys_in_pm, phy)) { 977 if( PM_4x10_QTC_INFO(pm_info)->nof_phys[temp] >= 2 ){ 978 nof_ext_phys = PM_4x10_QTC_INFO(pm_info)->nof_phys[temp]-1; 979 for(i=0 ; i<nof_ext_phys ; i++) { 980 xphy_id = PM_4x10_QTC_INFO(pm_info)->lane_conn[i][temp].xphy_id; 981 if(xphy_id != PORTMOD_XPHY_ID_INVALID){ 982 _SOC_IF_ERR_EXIT(portmod_xphy_core_access_get(unit, xphy_id, &core_access, &is_legacy_phy)); 983 _SOC_IF_ERR_EXIT(portmod_common_ext_phy_probe(unit, port, &core_access, &probe)); 984 if ((probe == 0) && 985 (core_access.type == phymodDispatchTypeInvalid)){ 986 pm4x10_qtc_xphy_lane_detach_from_pm(unit, pm_info, phy, i+1, &lane_conn); 987 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 988 "Warning: EXT PHY p=%d xphy_id=%d can't be probed\n"), port, xphy_id)); 989 } else { 990 core_probed = 1; 991 _SOC_IF_ERR_EXIT(portmod_xphy_core_probed_set(unit, xphy_id, core_probed)); 992 /* Check if after the probe the ext phy is legacy, so we dont overrun the current value */ 993 _SOC_IF_ERR_EXIT(portmod_xphy_is_legacy_phy_get(unit, xphy_id, &is_legacy_phy)); 994 _SOC_IF_ERR_EXIT(portmod_xphy_core_access_set(unit, xphy_id, &core_access, is_legacy_phy)); 995 } 996 } 997 } 998 } 999 } 1000 temp++; 1001 } 1002 1003 exit: 1004 SOC_FUNC_RETURN; 1005 } 1006 1007 STATIC 1008 int _pm4x10_qtc_pm_serdes_core_init(int unit, pm_info_t pm_info, const portmod_port_add_info_t* add_info) 1009 { 1010 int rv; 1011 phymod_core_init_config_t core_conf; 1012 phymod_core_status_t core_status; 1013 const portmod_port_interface_config_t* config; 1014 uint32 core_is_initialized; 1015 soc_port_if_t interface = SOC_PORT_IF_NULL; 1016 uint32 init_flags = 0; 1017 SOC_INIT_FUNC_DEFS; 1018 1019 config = &(add_info->interface_config); 1020 1021 _SOC_IF_ERR_EXIT(phymod_core_init_config_t_init(&core_conf)); 1022 1023 core_conf.firmware_load_method = PM_4x10_QTC_INFO(pm_info)->fw_load_method; 1024 core_conf.firmware_loader = PM_4x10_QTC_INFO(pm_info)->external_fw_loader; 1025 core_conf.lane_map = PM_4x10_QTC_INFO(pm_info)->lane_map; 1026 1027 _SOC_IF_ERR_EXIT(phymod_phy_inf_config_t_init(&core_conf.interface)); 1028 _SOC_IF_ERR_EXIT(portmod_line_intf_from_config_get(config, &interface)); 1029 _SOC_IF_ERR_EXIT(portmod_intf_to_phymod_intf(unit, config->speed, 1030 interface, &core_conf.interface.interface_type)); 1031 core_conf.interface.data_rate = config->speed; 1032 core_conf.interface.interface_modes = config->interface_modes; 1033 core_conf.interface.ref_clock = PM_4x10_QTC_INFO(pm_info)->ref_clk; 1034 1035 _SOC_IF_ERR_EXIT(phymod_core_status_t_init(&core_status)); 1036 core_status.pmd_active = 0; 1037 1038 init_flags = PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info) | PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info); 1039 1040 if (PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY_GET(add_info)) { 1041 PHYMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY_SET(&core_conf); 1042 } 1043 if (PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info)) { 1044 PHYMOD_CORE_INIT_F_EXECUTE_PASS1_SET(&core_conf); 1045 } 1046 if (PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) { 1047 PHYMOD_CORE_INIT_F_EXECUTE_PASS2_SET(&core_conf); 1048 } 1049 1050 core_conf.op_datapath = add_info->phy_op_datapath; 1051 1052 rv = PM4x10_QTC_IS_INITIALIZED_GET(unit, pm_info, &core_is_initialized); 1053 _SOC_IF_ERR_EXIT(rv); 1054 1055 if (!PORTMOD_CORE_INIT_FLAG_INITIALZIED_GET(core_is_initialized)) { 1056 /* firmware load will happen after pass 1 */ 1057 if (!PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED_GET(core_is_initialized) || 1058 PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) { 1059 _SOC_IF_ERR_EXIT(phymod_core_init(&PM_4x10_QTC_INFO(pm_info)->int_core_access, 1060 &core_conf, 1061 &core_status)); 1062 1063 if (PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info) || init_flags == 0) { 1064 PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED_SET(core_is_initialized); 1065 rv = PM4x10_QTC_IS_INITIALIZED_SET(unit, pm_info, core_is_initialized); 1066 _SOC_IF_ERR_EXIT(rv); 1067 } 1068 if (PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info) || init_flags == 0) { 1069 PORTMOD_CORE_INIT_FLAG_INITIALZIED_SET(core_is_initialized); 1070 rv = PM4x10_QTC_IS_INITIALIZED_SET(unit, pm_info, core_is_initialized); 1071 _SOC_IF_ERR_EXIT(rv); 1072 } 1073 } 1074 } 1075 1076 exit: 1077 SOC_FUNC_RETURN; 1078 } 1079 1080 STATIC 1081 int _pm4x10_qtc_pm_ext_phy_core_init(int unit, pm_info_t pm_info, const portmod_port_add_info_t* add_info) 1082 { 1083 int temp, phy; 1084 phymod_core_init_config_t core_conf; 1085 phymod_core_status_t core_status; 1086 const portmod_port_interface_config_t* config; 1087 portmod_pbmp_t port_phys_in_pm; 1088 phymod_firmware_load_method_t fw_load_method; 1089 phymod_lane_map_t lane_map; 1090 phymod_core_access_t core_access; 1091 uint32 primary_core_num; 1092 soc_port_if_t interface = SOC_PORT_IF_NULL; 1093 uint32 xphy_id; 1094 int is_legacy_phy = 0; 1095 uint32 nof_ext_phys = 0; 1096 int force_fw_load, is_initialized = 0; 1097 int init_all = 0, lane, i; 1098 1099 SOC_INIT_FUNC_DEFS; 1100 1101 config = &(add_info->interface_config); 1102 1103 init_all = (!PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_GET(add_info) && 1104 !PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info) && 1105 !PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) ? 1 : 0; 1106 1107 /* Get the first phy related to this port */ 1108 PORTMOD_PBMP_ASSIGN(port_phys_in_pm, add_info->phys); 1109 PORTMOD_PBMP_AND(port_phys_in_pm, PM_4x10_QTC_INFO(pm_info)->phys); 1110 1111 _SOC_IF_ERR_EXIT(phymod_core_init_config_t_init(&core_conf)); 1112 1113 if (PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info)) { 1114 PHYMOD_CORE_INIT_F_EXECUTE_PASS1_SET(&core_conf); 1115 } 1116 1117 if (PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) { 1118 PHYMOD_CORE_INIT_F_EXECUTE_PASS2_SET(&core_conf); 1119 } 1120 1121 _SOC_IF_ERR_EXIT(phymod_phy_inf_config_t_init(&core_conf.interface)); 1122 _SOC_IF_ERR_EXIT(portmod_line_intf_from_config_get(config, &interface)); 1123 _SOC_IF_ERR_EXIT(portmod_intf_to_phymod_intf(unit, config->speed, 1124 interface, &core_conf.interface.interface_type)); 1125 core_conf.interface.data_rate = config->speed; 1126 core_conf.interface.interface_modes = config->interface_modes; 1127 core_conf.interface.ref_clock = PM_4x10_QTC_INFO(pm_info)->ref_clk; 1128 1129 core_conf.op_datapath = add_info->phy_op_datapath; 1130 1131 /* deal with ext phys now ... */ 1132 if(PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP_GET(add_info)) { 1133 return(SOC_E_NONE); 1134 } 1135 1136 core_conf.firmware_load_method = (PM_4x10_QTC_INFO(pm_info)->fw_load_method == 1137 phymodFirmwareLoadMethodNone) ? 1138 phymodFirmwareLoadMethodNone : 1139 phymodFirmwareLoadMethodInternal; 1140 core_conf.firmware_loader = NULL; 1141 1142 /* config "no swap" for external phys.set later using APIs*/ 1143 for (lane=0 ; lane < PM4X10_QTC_LANES_PER_CORE; lane++) { 1144 core_conf.lane_map.lane_map_rx[lane] = lane; 1145 core_conf.lane_map.lane_map_tx[lane] = lane; 1146 } 1147 1148 temp = 0; 1149 PORTMOD_PBMP_ITER(PM_4x10_QTC_INFO(pm_info)->phys, phy) { 1150 if (PORTMOD_PBMP_MEMBER(port_phys_in_pm, phy)) { 1151 if (PM_4x10_QTC_INFO(pm_info)->nof_phys[temp] >= 2 ) { 1152 nof_ext_phys = PM_4x10_QTC_INFO(pm_info)->nof_phys[temp]-1; 1153 for (i=0 ; i<nof_ext_phys; i++) { 1154 xphy_id = PM_4x10_QTC_INFO(pm_info)->lane_conn[i][temp].xphy_id; 1155 if (xphy_id != PORTMOD_XPHY_ID_INVALID) { 1156 _SOC_IF_ERR_EXIT(portmod_xphy_core_access_get(unit, xphy_id, &core_access, &is_legacy_phy)); 1157 _SOC_IF_ERR_EXIT(portmod_xphy_fw_load_method_get(unit, xphy_id, &fw_load_method)); 1158 _SOC_IF_ERR_EXIT(portmod_xphy_force_fw_load_get(unit, xphy_id, &force_fw_load)); 1159 _SOC_IF_ERR_EXIT(portmod_xphy_lane_map_get(unit, xphy_id, &lane_map)); 1160 _SOC_IF_ERR_EXIT(portmod_xphy_primary_core_num_get(unit, xphy_id, &primary_core_num)); 1161 1162 _SOC_IF_ERR_EXIT(phymod_core_status_t_init(&core_status)); 1163 core_status.pmd_active = 0; 1164 1165 /* for external phys, FW load method is default to Internal 1166 unless it is force to NONE. */ 1167 core_conf.firmware_load_method = fw_load_method; 1168 core_conf.firmware_loader = NULL; 1169 1170 if (force_fw_load == phymodFirmwareLoadForce) { 1171 PHYMOD_CORE_INIT_F_FW_FORCE_DOWNLOAD_SET(&core_conf); 1172 } else if (force_fw_load == phymodFirmwareLoadAuto) { 1173 PHYMOD_CORE_INIT_F_FW_AUTO_DOWNLOAD_SET(&core_conf); 1174 } 1175 1176 if ((PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info) || init_all) && 1177 (is_initialized & PHYMOD_CORE_INIT_F_EXECUTE_PASS1)) { 1178 continue; 1179 } 1180 if ((PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)|| init_all) && 1181 (is_initialized & PHYMOD_CORE_INIT_F_EXECUTE_PASS2)) { 1182 continue; 1183 } 1184 _SOC_IF_ERR_EXIT(portmod_xphy_is_legacy_phy_get(unit, xphy_id, &is_legacy_phy)); 1185 if (is_legacy_phy) { 1186 /* Dont do a core init for legacy Phys.*/ 1187 } else { 1188 _SOC_IF_ERR_EXIT(phymod_core_init(&core_access, 1189 &core_conf, 1190 &core_status)); 1191 } 1192 1193 if (init_all) { 1194 is_initialized = (PHYMOD_CORE_INIT_F_EXECUTE_PASS2 | PHYMOD_CORE_INIT_F_EXECUTE_PASS1); 1195 } else if (PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) { 1196 is_initialized |= PHYMOD_CORE_INIT_F_EXECUTE_PASS2; 1197 } else { 1198 is_initialized = PHYMOD_CORE_INIT_F_EXECUTE_PASS1; 1199 } 1200 1201 _SOC_IF_ERR_EXIT(portmod_xphy_is_initialized_set(unit, xphy_id, is_initialized)); 1202 } 1203 } 1204 } 1205 } 1206 temp++; 1207 } 1208 1209 exit: 1210 SOC_FUNC_RETURN; 1211 } 1212 1213 STATIC 1214 int _pm4x10_qtc_pm_core_init(int unit, pm_info_t pm_info, 1215 const portmod_port_add_info_t* add_info) 1216 { 1217 SOC_INIT_FUNC_DEFS; 1218 1219 _SOC_IF_ERR_EXIT(_pm4x10_qtc_pm_serdes_core_init(unit, pm_info, add_info)); 1220 _SOC_IF_ERR_EXIT(_pm4x10_qtc_pm_ext_phy_core_init(unit, pm_info, add_info)); 1221 1222 exit: 1223 SOC_FUNC_RETURN; 1224 } 1225 1226 STATIC 1227 int _pm4x10_qtc_pm_port_init(int unit, int port, pm_info_t pm_info, const portmod_port_add_info_t* add_info) 1228 { 1229 int reg_port, port_index; 1230 uint32 bitmap, reg_val, field_val; 1231 portmod_default_user_access_t *user_data; 1232 soc_timeout_t to; 1233 int flags; 1234 SOC_INIT_FUNC_DEFS; 1235 1236 user_data = (portmod_default_user_access_t*)PM_4x10_QTC_INFO(pm_info)->int_core_access.access.user_acc; 1237 reg_port = user_data->blk_id | SOC_REG_ADDR_BLOCK_ID_MASK; 1238 1239 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 1240 1241 /* Init unimac */ 1242 flags = 0; 1243 if(PORTMOD_PORT_ADD_F_RX_SRIP_CRC_GET(add_info)) { 1244 flags |= UNIMAC_INIT_F_RX_STRIP_CRC; 1245 } 1246 _SOC_IF_ERR_EXIT(unimac_init(unit, port, flags)); 1247 1248 /* Init port ecc */ 1249 _SOC_IF_ERR_EXIT(READ_PMQ_ECC_INIT_CTRLr(unit, reg_port, ®_val)); 1250 field_val = soc_reg_field_get(unit, PMQ_ECC_INIT_CTRLr, reg_val, UNIMAC_MEM_INITf); 1251 field_val |= 0x1 << port_index; 1252 soc_reg_field_set(unit, PMQ_ECC_INIT_CTRLr, ®_val, UNIMAC_MEM_INITf, field_val); 1253 _SOC_IF_ERR_EXIT(WRITE_PMQ_ECC_INIT_CTRLr(unit, reg_port, reg_val)); 1254 1255 /* Wait for UNIMAC mem to finish init */ 1256 soc_timeout_init(&to, 10, 0); 1257 while (!soc_timeout_check(&to)) { 1258 _SOC_IF_ERR_EXIT(READ_PMQ_ECC_INIT_STSr(unit, reg_port, ®_val)); 1259 if ((reg_val & UNIMAC_MEM_INIT_DONE_MASK) == (0x1 << port_index)){ 1260 break; 1261 } 1262 } 1263 1264 /*Mask the ECC status for each of the UNIMACs*/ 1265 _SOC_IF_ERR_EXIT(READ_PMQ_ECCr(unit, reg_port, ®_val)); 1266 field_val = soc_reg_field_get(unit, PMQ_ECCr, reg_val, PORTNUM_ECCSTS_MASKf); 1267 field_val &= ~(0x1 << port_index); 1268 soc_reg_field_set(unit, PMQ_ECCr, ®_val, PORTNUM_ECCSTS_MASKf, field_val); 1269 _SOC_IF_ERR_EXIT(WRITE_PMQ_ECCr(unit, reg_port, reg_val)); 1270 1271 exit: 1272 SOC_FUNC_RETURN; 1273 } 1274 1275 STATIC 1276 int _pm4x10_qtc_pmq_gport_init(int unit, int port, pm_info_t pm_info, 1277 const portmod_port_add_info_t* add_info) 1278 { 1279 int reg_port, pm_is_active; 1280 uint32 reg_val; 1281 portmod_default_user_access_t *user_data; 1282 SOC_INIT_FUNC_DEFS; 1283 1284 user_data = (portmod_default_user_access_t*)PM_4x10_QTC_INFO(pm_info)->int_core_access.access.user_acc; 1285 reg_port = user_data->blk_id | SOC_REG_ADDR_BLOCK_ID_MASK; 1286 1287 _SOC_IF_ERR_EXIT(PM4x10_QTC_IS_ACTIVE_GET(unit, pm_info, &pm_is_active)); 1288 if (pm_is_active == 0) { 1289 /* special init process for PMQ(PM4x10Q in QSGMII mode) - to release PMQ's QSGMII reset state after QSGMII-PCS and UniMAC init. */ 1290 SOC_IF_ERROR_RETURN(READ_CHIP_CONFIGr(unit, reg_port, ®_val)); 1291 soc_reg_field_set(unit, CHIP_CONFIGr, ®_val, QMODEf, 1); 1292 if ((PM_4x10_QTC_INFO(pm_info)->core_clock_khz > 325000) || (PM_4x10_QTC_INFO(pm_info)->core_clock_khz == 0)) { 1293 soc_reg_field_set(unit, CHIP_CONFIGr, ®_val, IP_TDMf, 0x3); 1294 } else { 1295 /* According to PORTMACRO-210, when clk=300M or less, ip_tdm should be 2 or less */ 1296 soc_reg_field_set(unit, CHIP_CONFIGr, ®_val, IP_TDMf, 0x1); 1297 } 1298 if (SOC_REG_FIELD_VALID(unit, CHIP_CONFIGr, PCS_USXGMII_MODE_ENf)) { 1299 if (add_info->init_config.qtc_mode == portmodQtcModeUsxgmii) { 1300 soc_reg_field_set(unit, CHIP_CONFIGr, ®_val, PCS_USXGMII_MODE_ENf, 0x1); 1301 } else { 1302 soc_reg_field_set(unit, CHIP_CONFIGr, ®_val, PCS_USXGMII_MODE_ENf, 0); 1303 } 1304 } 1305 soc_reg_field_set(unit, CHIP_CONFIGr, ®_val, PAUSE_PFC_SELf, 0x0); 1306 SOC_IF_ERROR_RETURN(WRITE_CHIP_CONFIGr(unit, reg_port, reg_val)); 1307 1308 /* Get Serdes OOR */ 1309 _SOC_IF_ERR_EXIT(pm4x10_qtc_port_tsc_reset_set(unit, port, pm_info, 1)); 1310 _SOC_IF_ERR_EXIT(pm4x10_qtc_port_tsc_reset_set(unit, port, pm_info, 0)); 1311 1312 _SOC_IF_ERR_EXIT(READ_CHIP_SWRSTr(unit, reg_port, ®_val)); 1313 soc_reg_field_set(unit, CHIP_SWRSTr, ®_val, SOFT_RESET_QSGMII_PCSf, 0x1); 1314 soc_reg_field_set(unit, CHIP_SWRSTr, ®_val, SOFT_RESET_GPORT1f, 0x1); 1315 soc_reg_field_set(unit, CHIP_SWRSTr, ®_val, SOFT_RESET_GPORT0f, 0x1); 1316 _SOC_IF_ERR_EXIT(WRITE_CHIP_SWRSTr(unit, reg_port, reg_val)); 1317 1318 _SOC_IF_ERR_EXIT(READ_CHIP_SWRSTr(unit, reg_port, ®_val)); 1319 soc_reg_field_set(unit, CHIP_SWRSTr, ®_val, SOFT_RESET_QSGMII_PCSf, 0); 1320 soc_reg_field_set(unit, CHIP_SWRSTr, ®_val, SOFT_RESET_GPORT1f, 0); 1321 soc_reg_field_set(unit, CHIP_SWRSTr, ®_val, SOFT_RESET_GPORT0f, 0); 1322 _SOC_IF_ERR_EXIT(WRITE_CHIP_SWRSTr(unit, reg_port, reg_val)); 1323 1324 /* Init port ecc */ 1325 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_ecc_init(unit, port, pm_info)); 1326 1327 pm_is_active = 1; 1328 _SOC_IF_ERR_EXIT(PM4x10_QTC_IS_ACTIVE_SET(unit, pm_info, pm_is_active)); 1329 } 1330 1331 if (add_info->flags & PORTMOD_PORT_ADD_F_EGR_1588_TIMESTAMP_MODE_48BIT) { 1332 SOC_IF_ERROR_RETURN(READ_GPORT_MODE_REGr(unit, port, ®_val)); 1333 soc_reg_field_set(unit, GPORT_MODE_REGr, ®_val, EGR_1588_TIMESTAMPING_MODEf, 0); 1334 SOC_IF_ERROR_RETURN(WRITE_GPORT_MODE_REGr(unit, port, reg_val)); 1335 } 1336 1337 /* Initialize mask for purging packet data received from the MAC */ 1338 _SOC_IF_ERR_EXIT(WRITE_GPORT_RSV_MASKr(unit, port, 0x78)); 1339 _SOC_IF_ERR_EXIT(WRITE_GPORT_STAT_UPDATE_MASKr(unit, port, 0x78)); 1340 1341 _SOC_IF_ERR_EXIT(READ_GPORT_CONFIGr(unit, port, ®_val)); 1342 soc_reg_field_set(unit, GPORT_CONFIGr, ®_val, CLR_CNTf, 1); 1343 _SOC_IF_ERR_EXIT(WRITE_GPORT_CONFIGr(unit, port, reg_val)); 1344 1345 /* Reset the clear-count bit after 64 clocks */ 1346 soc_reg_field_set(unit, GPORT_CONFIGr, ®_val, CLR_CNTf, 0); 1347 _SOC_IF_ERR_EXIT(WRITE_GPORT_CONFIGr(unit, port, reg_val)); 1348 1349 _SOC_IF_ERR_EXIT(READ_GPORT_CONFIGr(unit, port, ®_val)); 1350 soc_reg_field_set(unit, GPORT_CONFIGr, ®_val, GPORT_ENf, 1); 1351 _SOC_IF_ERR_EXIT(WRITE_GPORT_CONFIGr(unit, port, reg_val)); 1352 1353 _SOC_IF_ERR_EXIT(READ_GPORT_MODE_REGr(unit, port, ®_val)); 1354 soc_reg_field_set(unit, GPORT_MODE_REGr, ®_val, EP_TO_GP_CRC_MODES_SELf, 0x0); 1355 soc_reg_field_set(unit, GPORT_MODE_REGr, ®_val, EP_TO_GP_CRC_FWDf, 0); 1356 soc_reg_field_set(unit, GPORT_MODE_REGr, ®_val, EP_TO_GP_CRC_OWRTf, 0); 1357 _SOC_IF_ERR_EXIT(WRITE_GPORT_MODE_REGr(unit, port, reg_val)); 1358 1359 exit: 1360 SOC_FUNC_RETURN; 1361 } 1362 1363 STATIC 1364 int _pm4x10_qtc_port_attach_core_probe (int unit, int port, pm_info_t pm_info, 1365 const portmod_port_add_info_t* add_info) 1366 { 1367 int port_index = -1, rv = 0, phy, i; 1368 portmod_pbmp_t port_phys_in_pm; 1369 int prev_phy = -1; 1370 SOC_INIT_FUNC_DEFS; 1371 1372 /* Initialize PMQ and gport*/ 1373 _SOC_IF_ERR_EXIT(_pm4x10_qtc_pmq_gport_init(unit, port, pm_info, add_info)); 1374 1375 PORTMOD_PBMP_ASSIGN(port_phys_in_pm, add_info->phys); 1376 PORTMOD_PBMP_AND(port_phys_in_pm, PM_4x10_QTC_INFO(pm_info)->phys); 1377 i = 0; 1378 PORTMOD_PBMP_ITER(PM_4x10_QTC_INFO(pm_info)->phys, phy) { 1379 if (prev_phy != -1) { 1380 i += phy - prev_phy; 1381 } 1382 1383 if (PORTMOD_PBMP_MEMBER(port_phys_in_pm, phy)) { 1384 _SOC_IF_ERR_EXIT(PM4x10_QTC_PORTS_SET(unit, pm_info, port, i)); 1385 port_index = (port_index == -1) ? i : port_index; 1386 } 1387 prev_phy = phy; 1388 } 1389 1390 rv = PM4x10_QTC_SPEED_SET(unit, pm_info, add_info->interface_config.speed, port_index); 1391 _SOC_IF_ERR_EXIT(rv); 1392 1393 rv = PM4x10_QTC_MAX_SPEED_SET(unit, pm_info,add_info->interface_config.max_speed, port_index); 1394 _SOC_IF_ERR_EXIT(rv); 1395 1396 rv = PM4x10_QTC_INTERFACE_TYPE_SET(unit, pm_info, add_info->interface_config.interface, port_index); 1397 _SOC_IF_ERR_EXIT(rv); 1398 1399 rv = PM4x10_QTC_AN_MODE_SET(unit, pm_info, add_info->init_config.an_mode, port_index); 1400 _SOC_IF_ERR_EXIT(rv); 1401 1402 if (add_info->init_config.polarity_overwrite == 1) { 1403 sal_memcpy(&PM_4x10_QTC_INFO(pm_info)->polarity, 1404 &add_info->init_config.polarity[0], sizeof(phymod_polarity_t)); 1405 } 1406 if (add_info->init_config.lane_map_overwrite == 1) { 1407 sal_memcpy(&PM_4x10_QTC_INFO(pm_info)->lane_map, 1408 &add_info->init_config.lane_map[0], sizeof(phymod_lane_map_t)); 1409 } 1410 if (add_info->init_config.fw_load_method_overwrite == 1) { 1411 PM_4x10_QTC_INFO(pm_info)->fw_load_method = 1412 add_info->init_config.fw_load_method[0]; 1413 } 1414 if (add_info->init_config.ref_clk_overwrite == 1) { 1415 PM_4x10_QTC_INFO(pm_info)->ref_clk = add_info->init_config.ref_clk; 1416 } 1417 1418 /* QTC core probe */ 1419 _SOC_IF_ERR_EXIT(_pm4x10_qtc_pm_core_probe(unit, port, pm_info, add_info)); 1420 1421 exit: 1422 SOC_FUNC_RETURN; 1423 } 1424 1425 STATIC 1426 int _pm4x10_qtc_port_attach_resume_fw_load (int unit, int port, pm_info_t pm_info, 1427 const portmod_port_add_info_t* add_info) 1428 { 1429 int port_i, my_i; 1430 int i, nof_phys, usr_cfg_idx; 1431 uint32 bitmap, port_dynamic_state; 1432 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1433 int port_index = -1; 1434 phymod_phy_init_config_t init_config; 1435 phymod_interface_t phymod_serdes_interface = phymodInterfaceCount; 1436 phymod_autoneg_control_t an; 1437 1438 SOC_INIT_FUNC_DEFS; 1439 1440 phymod_autoneg_control_t_init(&an); 1441 1442 /* Initialze phys */ 1443 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 1444 if (PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index] > 0) { 1445 _SOC_IF_ERR_EXIT(phymod_phy_init_config_t_init(&init_config)); 1446 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, 1447 phy_access ,(1+MAX_PHYN), 1448 &nof_phys)); 1449 my_i = 0, usr_cfg_idx = 0; 1450 for (i = 0; i < MAX_PORTS_PER_PM4X10_QTC; i++) { 1451 _SOC_IF_ERR_EXIT(PM4x10_QTC_PORTS_GET(unit, pm_info, &port_i, i)); 1452 1453 if(port_i != port) { 1454 continue; 1455 } 1456 1457 if(SHR_BITGET(&(PM_4x10_QTC_INFO(pm_info)->polarity.tx_polarity), i)) { 1458 SHR_BITSET(&init_config.polarity.tx_polarity, my_i); 1459 } 1460 1461 if(SHR_BITGET(&(PM_4x10_QTC_INFO(pm_info)->polarity.rx_polarity), i)) { 1462 SHR_BITSET(&init_config.polarity.rx_polarity, my_i); 1463 } 1464 1465 _SOC_IF_ERR_EXIT(phymod_phy_media_type_tx_get(&phy_access[0], phymodMediaTypeChipToChip, &init_config.tx[my_i])); 1466 1467 if (PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG_GET(add_info->init_config.tx_params_user_flag[usr_cfg_idx])) { 1468 init_config.tx[my_i].pre = add_info->init_config.tx_params[usr_cfg_idx].pre; 1469 init_config.tx[my_i].main = add_info->init_config.tx_params[usr_cfg_idx].main; 1470 init_config.tx[my_i].post = add_info->init_config.tx_params[usr_cfg_idx].post; 1471 } 1472 1473 if (PORTMOD_USER_SET_TX_AMP_BY_CONFIG_GET(add_info->init_config.tx_params_user_flag[usr_cfg_idx])) { 1474 init_config.tx[my_i].amp = add_info->init_config.tx_params[usr_cfg_idx].amp; 1475 } 1476 1477 if (PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG_GET(add_info->init_config.tx_params_user_flag[usr_cfg_idx]) 1478 || PORTMOD_USER_SET_TX_AMP_BY_CONFIG_GET(add_info->init_config.tx_params_user_flag[usr_cfg_idx])) { 1479 port_dynamic_state = 0; 1480 PORTMOD_PORT_DEFAULT_TX_PARAMS_UPDATED_SET(port_dynamic_state); 1481 1482 _SOC_IF_ERR_EXIT(PM4x10_QTC_PORT_DYNAMIC_STATE_SET(unit, pm_info, port_dynamic_state, port_index)); 1483 } 1484 1485 usr_cfg_idx++; 1486 my_i++; 1487 } 1488 1489 _SOC_IF_ERR_EXIT(portmod_intf_to_phymod_intf(unit, 1490 add_info->interface_config.speed, 1491 add_info->interface_config.interface, 1492 &init_config.interface.interface_type)); 1493 init_config.interface.data_rate = add_info->interface_config.speed; 1494 init_config.interface.pll_divider_req = 1495 add_info->interface_config.pll_divider_req; 1496 init_config.interface.ref_clock = PM_4x10_QTC_INFO(pm_info)->ref_clk; 1497 1498 _SOC_IF_ERR_EXIT(portmod_port_phychain_phy_init(unit, phy_access, nof_phys, 1499 &init_config)); 1500 } 1501 1502 /* PHY interface set */ 1503 if (add_info->interface_config.serdes_interface != SOC_PORT_IF_NULL) { 1504 _SOC_IF_ERR_EXIT(portmod_intf_to_phymod_intf(unit, 1505 add_info->interface_config.speed, 1506 add_info->interface_config.serdes_interface, 1507 &phymod_serdes_interface)); 1508 } 1509 1510 /* Apply to SerDes with same interface config */ 1511 _SOC_IF_ERR_EXIT( 1512 portmod_port_phychain_interface_config_set(unit, port, phy_access, nof_phys, 1513 add_info->interface_config.flags , 1514 &init_config.interface, 1515 phymod_serdes_interface, 1516 PM_4x10_QTC_INFO(pm_info)->ref_clk, 1517 PORTMOD_INIT_F_INTERNAL_SERDES_ONLY)); 1518 1519 /* Enable SerDes AN */ 1520 an.an_mode = phymod_AN_MODE_SGMII; 1521 an.enable = 1; 1522 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_autoneg_set(unit, port, pm_info, PORTMOD_INIT_F_INTERNAL_SERDES_ONLY, &an)); 1523 1524 /* Initialize unimac and port*/ 1525 _SOC_IF_ERR_EXIT(_pm4x10_qtc_pm_port_init(unit, port, pm_info, add_info)); 1526 1527 /* Disable Internal SerDes LPI bypass */ 1528 _SOC_IF_ERR_EXIT(phymod_phy_eee_set(&phy_access[0], FALSE)); 1529 1530 exit: 1531 SOC_FUNC_RETURN; 1532 } 1533 1534 STATIC 1535 int _pm4x10_qtc_port_attach(int unit, int port, pm_info_t pm_info, const portmod_port_add_info_t* add_info) 1536 { 1537 int init_all = 0; 1538 SOC_INIT_FUNC_DEFS; 1539 1540 init_all = (!PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_GET(add_info) && 1541 !PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info) && 1542 !PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) ? 1 : 0; 1543 1544 if (PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_GET(add_info) || (init_all)) { 1545 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_attach_core_probe(unit, port, pm_info, add_info)); 1546 } 1547 1548 if (PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_GET(add_info) && 1549 !PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info)) { 1550 return (SOC_E_NONE); 1551 } 1552 1553 if (PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info) || (init_all)) { 1554 /* Core initialization */ 1555 _SOC_IF_ERR_EXIT(_pm4x10_qtc_pm_core_init(unit, pm_info, add_info)); 1556 } 1557 1558 if (PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info)) { 1559 return (SOC_E_NONE); 1560 } 1561 1562 SOC_IF_ERROR_RETURN(_pm4x10_qtc_port_attach_resume_fw_load (unit, port, pm_info, add_info)); 1563 1564 exit: 1565 SOC_FUNC_RETURN; 1566 } 1567 1568 int pm4x10_qtc_port_attach(int unit, int port, pm_info_t pm_info, const portmod_port_add_info_t* add_info) 1569 { 1570 int rv, active_port_num, current_qtc_mode = 0; 1571 portmod_qtc_mode_t qtc_mode = add_info->init_config.qtc_mode; 1572 int init_all = 0, core_is_active = 0; 1573 SOC_INIT_FUNC_DEFS; 1574 1575 PM4x10_QTC_CORE_ACTIVE_GET(core_is_active); 1576 if (!core_is_active) { 1577 _SOC_IF_ERR_EXIT(PM4x10_QTC_QTC_MODE_SET(unit, pm_info, qtc_mode)); 1578 } else { 1579 _SOC_IF_ERR_EXIT(PM4x10_QTC_QTC_MODE_GET(unit, pm_info, ¤t_qtc_mode)); 1580 if (current_qtc_mode != qtc_mode) { 1581 /*PM4x10_QTC doesn't support mixed mode*/ 1582 _SOC_IF_ERR_EXIT(SOC_E_PARAM); 1583 } 1584 } 1585 1586 if (qtc_mode == portmodQtcModeQsgmii) { 1587 PM_4x10_QTC_INFO(pm_info)->int_core_access.access.flags = PHYMOD_ACC_F_QMODE; 1588 } else if (qtc_mode == portmodQtcModeUsxgmii) { 1589 PM_4x10_QTC_INFO(pm_info)->int_core_access.access.flags = PHYMOD_ACC_F_USXMODE; 1590 } 1591 1592 init_all = (!PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_GET(add_info) && 1593 !PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info) && 1594 !PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) ? 1 : 0; 1595 if (!IS_QMOD) { 1596 _SOC_IF_ERR_EXIT( 1597 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_attach(unit, port, PM4x10_INFO(pm_info), add_info)); 1598 } else { 1599 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_attach(unit, port, pm_info, add_info)); 1600 } 1601 1602 if (PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_GET(add_info) || (init_all)) { 1603 active_port_num++; 1604 rv = PM4x10_QTC_ACTIVE_PORT_NUM_SET(unit, pm_info, active_port_num); 1605 _SOC_IF_ERR_EXIT(rv); 1606 } 1607 1608 exit: 1609 SOC_FUNC_RETURN; 1610 } 1611 1612 int _pm4x10_qtc_port_detach(int unit, int port, pm_info_t pm_info) 1613 { 1614 int enable, i, reg_port, invalid_port = -1; 1615 uint32 reg_val; 1616 portmod_default_user_access_t *user_data; 1617 int tmp_port = 0, is_last_one = TRUE; 1618 uint32 inactive = 0; 1619 SOC_INIT_FUNC_DEFS; 1620 1621 _SOC_IF_ERR_EXIT(pm4x10_qtc_port_enable_get(unit, port, pm_info, 0, &enable)); 1622 if (enable) { 1623 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("can't detach active port %d"), port)); 1624 } 1625 1626 /*remove from array and check if it was the last one*/ 1627 for (i = 0; i < MAX_PORTS_PER_PM4X10_QTC; i++) { 1628 _SOC_IF_ERR_EXIT(PM4x10_QTC_PORTS_GET(unit, pm_info, &tmp_port, i)); 1629 if (tmp_port == port) { 1630 _SOC_IF_ERR_EXIT(PM4x10_QTC_PORTS_SET(unit, pm_info, invalid_port, i)); 1631 } else if (tmp_port != -1) { 1632 is_last_one = FALSE; 1633 } 1634 } 1635 1636 user_data = (portmod_default_user_access_t*)PM_4x10_QTC_INFO(pm_info)->int_core_access.access.user_acc; 1637 reg_port = user_data->blk_id | SOC_REG_ADDR_BLOCK_ID_MASK; 1638 1639 /* deinit MAC */ 1640 _SOC_IF_ERR_EXIT(unimac_deinit(unit, port)); 1641 1642 if (is_last_one) { /*last one*/ 1643 /* Put Serdes in reset*/ 1644 _SOC_IF_ERR_EXIT(pm4x10_qtc_port_tsc_reset_set(unit, port, pm_info, 1)); 1645 1646 _SOC_IF_ERR_EXIT(PM4x10_QTC_IS_ACTIVE_SET(unit, pm_info, inactive)); 1647 1648 _SOC_IF_ERR_EXIT(PM4x10_QTC_IS_INITIALIZED_SET(unit, pm_info, inactive)); 1649 1650 _SOC_IF_ERR_EXIT(READ_CHIP_SWRSTr(unit, reg_port, ®_val)); 1651 soc_reg_field_set(unit, CHIP_SWRSTr, ®_val, SOFT_RESET_QSGMII_PCSf, 0x0); 1652 soc_reg_field_set(unit, CHIP_SWRSTr, ®_val, SOFT_RESET_GPORT1f, 0x0); 1653 soc_reg_field_set(unit, CHIP_SWRSTr, ®_val, SOFT_RESET_GPORT0f, 0x0); 1654 _SOC_IF_ERR_EXIT(WRITE_CHIP_SWRSTr(unit, reg_port, reg_val)); 1655 1656 _SOC_IF_ERR_EXIT(READ_CHIP_CONFIGr(unit, reg_port, ®_val)); 1657 soc_reg_field_set(unit, CHIP_CONFIGr, ®_val, QMODEf, 0); 1658 soc_reg_field_set(unit, CHIP_CONFIGr, ®_val, IP_TDMf, 0); 1659 soc_reg_field_set(unit, CHIP_CONFIGr, ®_val, PCS_USXGMII_MODE_ENf, 0); 1660 soc_reg_field_set(unit, CHIP_CONFIGr, ®_val, PAUSE_PFC_SELf, 0x1); 1661 _SOC_IF_ERR_EXIT(WRITE_CHIP_CONFIGr(unit, reg_port, reg_val)); 1662 } 1663 1664 exit: 1665 SOC_FUNC_RETURN; 1666 } 1667 1668 int pm4x10_qtc_port_detach(int unit, int port, pm_info_t pm_info) 1669 { 1670 int rv, active_port_num; 1671 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 1672 SOC_INIT_FUNC_DEFS; 1673 1674 PM4x10_QTC_QMOD_GET(pm_info); 1675 1676 if (!IS_QMOD) { 1677 _SOC_IF_ERR_EXIT( 1678 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_detach(unit, port, PM4x10_INFO(pm_info))); 1679 } else { 1680 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_detach(unit, port, pm_info)); 1681 } 1682 1683 rv = PM4x10_QTC_ACTIVE_PORT_NUM_GET(unit, pm_info, &active_port_num); 1684 _SOC_IF_ERR_EXIT(rv); 1685 active_port_num--; 1686 if (active_port_num <= 0) { 1687 active_port_num = 0; 1688 } 1689 rv = PM4x10_QTC_ACTIVE_PORT_NUM_SET(unit, pm_info, active_port_num); 1690 _SOC_IF_ERR_EXIT(rv); 1691 1692 if (active_port_num == 0) { 1693 qtc_mode = portmodQtcModeInvalid; 1694 rv = PM4x10_QTC_QTC_MODE_SET(unit, pm_info, qtc_mode); 1695 _SOC_IF_ERR_EXIT(rv); 1696 } 1697 1698 exit: 1699 SOC_FUNC_RETURN; 1700 } 1701 1702 int pm4x10_qtc_pm_core_info_get(int unit, pm_info_t pm_info, int phyn, portmod_pm_core_info_t* core_info) 1703 { 1704 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 1705 SOC_INIT_FUNC_DEFS; 1706 1707 PM4x10_QTC_QMOD_GET(pm_info); 1708 1709 if (!IS_QMOD) { 1710 _SOC_IF_ERR_EXIT( 1711 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_pm_core_info_get(unit, 1712 PM4x10_INFO(pm_info), phyn, core_info)); 1713 } 1714 1715 exit: 1716 SOC_FUNC_RETURN; 1717 } 1718 1719 int pm4x10_qtc_port_replace(int unit, int port, pm_info_t pm_info, int new_port) 1720 { 1721 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 1722 SOC_INIT_FUNC_DEFS; 1723 1724 PM4x10_QTC_QMOD_GET(pm_info); 1725 1726 if (!IS_QMOD) { 1727 _SOC_IF_ERR_EXIT( 1728 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_replace(unit, port, PM4x10_INFO(pm_info), new_port)); 1729 } 1730 1731 exit: 1732 SOC_FUNC_RETURN; 1733 } 1734 1735 int _pm4x10_qtc_port_enable_set(int unit, int port, pm_info_t pm_info, int flags, int enable) 1736 { 1737 int actual_flags = flags, nof_phys = 0; 1738 phymod_phy_power_t phy_power; 1739 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1740 uint32 phychain_flag; 1741 int unimac_flags = 0; 1742 SOC_INIT_FUNC_DEFS; 1743 1744 /* If no Rx/Tx flags - set both */ 1745 if ((!PORTMOD_PORT_ENABLE_TX_GET(flags)) && (!PORTMOD_PORT_ENABLE_RX_GET(flags))) { 1746 PORTMOD_PORT_ENABLE_RX_SET(actual_flags); 1747 PORTMOD_PORT_ENABLE_TX_SET(actual_flags); 1748 } 1749 1750 /* If no Mac/Phy flags - set both */ 1751 if ((!PORTMOD_PORT_ENABLE_PHY_GET(flags)) && (!PORTMOD_PORT_ENABLE_MAC_GET(flags))) { 1752 PORTMOD_PORT_ENABLE_PHY_SET(actual_flags); 1753 PORTMOD_PORT_ENABLE_MAC_SET(actual_flags); 1754 } 1755 1756 /* if MAC is set and either RX or TX set is invalid combination */ 1757 if ((PORTMOD_PORT_ENABLE_MAC_GET(actual_flags)) && (!PORTMOD_PORT_ENABLE_PHY_GET(actual_flags))) { 1758 if ((!PORTMOD_PORT_ENABLE_TX_GET(actual_flags)) || (!PORTMOD_PORT_ENABLE_RX_GET(actual_flags))) { 1759 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("MAC RX and TX can't be enabled separately"))); 1760 } 1761 } 1762 1763 /* phychain_flag is meant to be used if we want only part of the phychin to be affected*/ 1764 phychain_flag = PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY_GET(flags) ? 1765 PORTMOD_INIT_F_INTERNAL_SERDES_ONLY : 1766 PORTMOD_INIT_F_EXTERNAL_MOST_ONLY ; 1767 1768 _SOC_IF_ERR_EXIT(phymod_phy_power_t_init(&phy_power)); 1769 phy_power.rx = phymodPowerNoChange; 1770 phy_power.tx = phymodPowerNoChange; 1771 1772 if (PORTMOD_PORT_ENABLE_RX_GET(actual_flags)) { 1773 phy_power.rx = (enable) ? phymodPowerOn : phymodPowerOff; 1774 unimac_flags |= UNIMAC_ENABLE_SET_FLAGS_RX_EN; 1775 } 1776 if (PORTMOD_PORT_ENABLE_TX_GET(actual_flags)) { 1777 phy_power.tx = (enable) ? phymodPowerOn : phymodPowerOff; 1778 unimac_flags |= UNIMAC_ENABLE_SET_FLAGS_TX_EN; 1779 } 1780 1781 if (PORTMOD_PORT_ENABLE_PHY_GET(actual_flags)) { 1782 _SOC_IF_ERR_EXIT 1783 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1784 phy_access ,(1+MAX_PHYN), 1785 &nof_phys)); 1786 1787 if (enable) { 1788 if (PORTMOD_PORT_ENABLE_MAC_GET(actual_flags)) { 1789 _SOC_IF_ERR_EXIT(unimac_enable_set(unit, port, 0, enable)); 1790 } 1791 if (PORTMOD_PORT_ENABLE_PHY_GET(actual_flags)) { 1792 if (PORTMOD_PORT_ENABLE_TX_GET(actual_flags)) { 1793 _SOC_IF_ERR_EXIT(portmod_port_phychain_tx_lane_control_set( 1794 unit, port, phy_access, nof_phys, phychain_flag, phymodTxSquelchOff)); 1795 } 1796 if (PORTMOD_PORT_ENABLE_RX_GET(actual_flags)) { 1797 _SOC_IF_ERR_EXIT(portmod_port_phychain_rx_lane_control_set( 1798 unit, port, phy_access, nof_phys, phychain_flag, phymodRxSquelchOff)); 1799 } 1800 } 1801 } else { 1802 if (PORTMOD_PORT_ENABLE_PHY_GET(actual_flags)) { 1803 if (PORTMOD_PORT_ENABLE_TX_GET(actual_flags)) { 1804 _SOC_IF_ERR_EXIT(portmod_port_phychain_tx_lane_control_set( 1805 unit, port, phy_access, nof_phys, phychain_flag, phymodTxSquelchOn)); 1806 } 1807 if (PORTMOD_PORT_ENABLE_RX_GET(actual_flags)) { 1808 _SOC_IF_ERR_EXIT(portmod_port_phychain_rx_lane_control_set( 1809 unit, port, phy_access, nof_phys, phychain_flag, phymodRxSquelchOn)); 1810 } 1811 } 1812 if (PORTMOD_PORT_ENABLE_MAC_GET(actual_flags)) { 1813 _SOC_IF_ERR_EXIT(unimac_enable_set(unit, port, unimac_flags, enable)); 1814 } 1815 } 1816 } 1817 1818 exit: 1819 SOC_FUNC_RETURN; 1820 } 1821 1822 int pm4x10_qtc_port_enable_set(int unit, int port, pm_info_t pm_info, int flags, int enable) 1823 { 1824 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 1825 SOC_INIT_FUNC_DEFS; 1826 1827 PM4x10_QTC_QMOD_GET(pm_info); 1828 1829 if (!IS_QMOD) { 1830 _SOC_IF_ERR_EXIT( 1831 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_enable_set(unit, port, PM4x10_INFO(pm_info), flags, enable)); 1832 } else { 1833 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_enable_set(unit, port, pm_info, flags, enable)); 1834 } 1835 1836 exit: 1837 SOC_FUNC_RETURN; 1838 } 1839 1840 int _pm4x10_qtc_port_enable_get(int unit, int port, pm_info_t pm_info, int flags, int* enable) 1841 { 1842 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1843 int nof_phys = 0; 1844 phymod_phy_tx_lane_control_t tx_control = phymodTxSquelchOn; 1845 phymod_phy_rx_lane_control_t rx_control = phymodRxSquelchOn; 1846 int phy_enable = 1, mac_enable = 1, mac_rx_enable, mac_tx_enable; 1847 int actual_flags = flags; 1848 uint32 phychain_flag; 1849 SOC_INIT_FUNC_DEFS; 1850 SOC_NULL_CHECK(pm_info); 1851 1852 /* If no RX\TX flags - set both*/ 1853 if((!PORTMOD_PORT_ENABLE_TX_GET(flags)) && (!PORTMOD_PORT_ENABLE_RX_GET(flags))){ 1854 PORTMOD_PORT_ENABLE_RX_SET(actual_flags); 1855 PORTMOD_PORT_ENABLE_TX_SET(actual_flags); 1856 } 1857 1858 /* if no MAC\Phy flags - set both*/ 1859 if((!PORTMOD_PORT_ENABLE_PHY_GET(flags)) && (!PORTMOD_PORT_ENABLE_MAC_GET(flags))){ 1860 PORTMOD_PORT_ENABLE_PHY_SET(actual_flags); 1861 PORTMOD_PORT_ENABLE_MAC_SET(actual_flags); 1862 } 1863 1864 /* phychain_flag is meant to be used if we want only part of the phychin to be affected*/ 1865 phychain_flag = PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY_GET(flags) ? 1866 PORTMOD_INIT_F_INTERNAL_SERDES_ONLY : 1867 PORTMOD_INIT_F_EXTERNAL_MOST_ONLY ; 1868 1869 if (PORTMOD_PORT_ENABLE_MAC_GET(actual_flags)) { 1870 mac_enable = 0; 1871 1872 if (PORTMOD_PORT_ENABLE_RX_GET(actual_flags)) { 1873 _SOC_IF_ERR_EXIT(unimac_enable_get(unit, port, UNIMAC_ENABLE_SET_FLAGS_RX_EN, &mac_rx_enable)); 1874 mac_enable |= (mac_rx_enable) ? 1 : 0; 1875 } 1876 if (PORTMOD_PORT_ENABLE_TX_GET(actual_flags)) { 1877 _SOC_IF_ERR_EXIT(unimac_enable_get(unit, port, UNIMAC_ENABLE_SET_FLAGS_TX_EN, &mac_tx_enable)); 1878 mac_enable |= (mac_tx_enable) ? 1 : 0; 1879 } 1880 } 1881 1882 if (PORTMOD_PORT_ENABLE_PHY_GET(actual_flags)) { 1883 _SOC_IF_ERR_EXIT 1884 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1885 phy_access ,(1+MAX_PHYN), 1886 &nof_phys)); 1887 _SOC_IF_ERR_EXIT 1888 (portmod_port_phychain_tx_lane_control_get(unit, port, phy_access, nof_phys, phychain_flag, &tx_control)); 1889 _SOC_IF_ERR_EXIT 1890 (portmod_port_phychain_rx_lane_control_get(unit, port, phy_access, nof_phys, phychain_flag, &rx_control)); 1891 1892 phy_enable = 0; 1893 1894 if (PORTMOD_PORT_ENABLE_RX_GET(actual_flags)) { 1895 phy_enable |= (rx_control == phymodRxSquelchOn) ? 0 : 1; 1896 } 1897 if (PORTMOD_PORT_ENABLE_TX_GET(actual_flags)) { 1898 phy_enable |= (tx_control == phymodTxSquelchOn) ? 0 : 1; 1899 } 1900 } 1901 1902 *enable = (mac_enable && phy_enable); 1903 1904 exit: 1905 SOC_FUNC_RETURN; 1906 } 1907 1908 int pm4x10_qtc_port_enable_get(int unit, int port, pm_info_t pm_info, int flags, int* enable) 1909 { 1910 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 1911 SOC_INIT_FUNC_DEFS; 1912 1913 PM4x10_QTC_QMOD_GET(pm_info); 1914 1915 if (!IS_QMOD) { 1916 _SOC_IF_ERR_EXIT( 1917 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_enable_get(unit, port, PM4x10_INFO(pm_info), flags, enable)); 1918 } else { 1919 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_enable_get(unit, port, pm_info, flags, enable)); 1920 } 1921 1922 exit: 1923 SOC_FUNC_RETURN; 1924 } 1925 1926 int _pm4x10_qtc_port_interface_config_set(int unit, int port, pm_info_t pm_info, const portmod_port_interface_config_t* config, int phy_init_flags) 1927 { 1928 int nof_phys; 1929 phymod_phy_access_t phy_access[1+MAX_PHYN]; 1930 phymod_phy_inf_config_t phy_interface_config; 1931 soc_port_if_t interface = SOC_PORT_IF_NULL; 1932 int port_index; 1933 uint32 bitmap; 1934 phymod_interface_t phymod_serdes_interface = phymodInterfaceCount; 1935 portmod_port_interface_config_t config_temp; 1936 uint32 is_interface_restore = 0; 1937 int is_valid = 0, is_ext_phy = 0; 1938 SOC_INIT_FUNC_DEFS; 1939 1940 _SOC_IF_ERR_EXIT(portmod_port_interface_config_t_init(unit, &config_temp)); 1941 sal_memcpy(&config_temp, config, sizeof(portmod_port_interface_config_t)); 1942 1943 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 1944 1945 _SOC_IF_ERR_EXIT 1946 (portmod_port_chain_phy_access_get(unit, port, pm_info, 1947 phy_access ,(1+MAX_PHYN), &nof_phys)); 1948 1949 if (config->flags & PHYMOD_INTF_F_UPDATE_SPEED_LINKUP) { 1950 int mac_speed = 0, mac_only = 0; 1951 phymod_phy_inf_config_t config_tmp; 1952 1953 _SOC_IF_ERR_EXIT(phymod_phy_interface_config_get(&phy_access[0], 0,0, &config_tmp)); 1954 1955 if (config->speed == config_tmp.data_rate) { 1956 unimac_speed_get(unit, port, &mac_speed); 1957 if (config->speed == mac_speed) { 1958 SOC_FUNC_RETURN; 1959 } 1960 1961 mac_only = 1; 1962 } 1963 1964 _SOC_IF_ERR_EXIT(unimac_speed_set(unit, port, config->speed)); 1965 1966 if (mac_only) { 1967 /* line side speed and SerDes speed are equal, no need update SerDes configuration */ 1968 SOC_FUNC_RETURN; 1969 } 1970 } 1971 1972 1973 if (config->flags & PHYMOD_INTF_F_INTF_PARAM_SET_ONLY) { 1974 _SOC_IF_ERR_EXIT( 1975 PM4x10_QTC_INTERFACE_TYPE_SET(unit, pm_info, config->interface, 1976 port_index)); 1977 is_interface_restore = 1; 1978 _SOC_IF_ERR_EXIT( 1979 PM4x10_QTC_IS_INTERFACE_RESTORE_SET(unit, pm_info, 1980 is_interface_restore, port_index)); 1981 SOC_FUNC_RETURN; 1982 } 1983 1984 _SOC_IF_ERR_EXIT( 1985 PM4x10_QTC_IS_INTERFACE_RESTORE_GET(unit, pm_info, &is_interface_restore, 1986 port_index)); 1987 /* 1988 * if the interface is already set with PARAM_SET_ONLY 1989 * h/w interface needs to be updated during speed set. 1990 * So load the interface information and clear the flag; 1991 */ 1992 if (is_interface_restore) { 1993 _SOC_IF_ERR_EXIT( 1994 PM4x10_QTC_INTERFACE_TYPE_GET(unit, pm_info, &interface, port_index)); 1995 config_temp.interface = interface; 1996 1997 is_interface_restore = 0; 1998 _SOC_IF_ERR_EXIT( 1999 PM4x10_QTC_IS_INTERFACE_RESTORE_SET(unit, pm_info, 2000 is_interface_restore, port_index)); 2001 } 2002 2003 _SOC_IF_ERR_EXIT(phymod_phy_inf_config_t_init (&phy_interface_config)); 2004 _SOC_IF_ERR_EXIT(portmod_line_intf_from_config_get(&config_temp, &interface)); 2005 if (nof_phys > 1) { 2006 is_ext_phy = TRUE; 2007 } 2008 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_interface_check(unit, port, pm_info, config, is_ext_phy, interface, &is_valid)); 2009 if (!is_valid) { 2010 LOG_ERROR(BSL_LS_BCM_PORT, 2011 (BSL_META_UP(unit, port, 2012 "ERROR: u=%d p=%d interface type %d not supported by internal SERDES for this speed %d \n"), 2013 unit, port, interface, config->speed)); 2014 _SOC_IF_ERR_EXIT(SOC_E_PARAM); 2015 } 2016 2017 _SOC_IF_ERR_EXIT(portmod_intf_to_phymod_intf(unit, config->speed, 2018 interface, &phy_interface_config.interface_type)); 2019 2020 phy_interface_config.data_rate = config->speed; 2021 phy_interface_config.interface_modes = config->interface_modes; 2022 phy_interface_config.ref_clock = PM_4x10_QTC_INFO(pm_info)->ref_clk; 2023 if (config->serdes_interface != SOC_PORT_IF_NULL) { 2024 _SOC_IF_ERR_EXIT(portmod_intf_to_phymod_intf(unit, 2025 config->speed, 2026 config->serdes_interface, 2027 &phymod_serdes_interface)); 2028 } 2029 2030 _SOC_IF_ERR_EXIT 2031 (portmod_port_phychain_interface_config_set(unit, port, phy_access, nof_phys, 2032 config->flags, 2033 &phy_interface_config, 2034 phymod_serdes_interface, 2035 PM_4x10_QTC_INFO(pm_info)->ref_clk, 2036 phy_init_flags)); 2037 2038 _SOC_IF_ERR_EXIT(unimac_speed_set(unit, port, phy_interface_config.data_rate)); 2039 2040 _SOC_IF_ERR_EXIT(PM4x10_QTC_SPEED_SET(unit, pm_info, config->speed, port_index)); 2041 _SOC_IF_ERR_EXIT(PM4x10_QTC_INTERFACE_TYPE_SET(unit, pm_info, interface, port_index)); 2042 2043 exit: 2044 SOC_FUNC_RETURN; 2045 } 2046 2047 int pm4x10_qtc_port_interface_config_set(int unit, int port, pm_info_t pm_info, const portmod_port_interface_config_t* config, int phy_init_flags) 2048 { 2049 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2050 SOC_INIT_FUNC_DEFS; 2051 2052 PM4x10_QTC_QMOD_GET(pm_info); 2053 2054 if (!IS_QMOD) { 2055 _SOC_IF_ERR_EXIT( 2056 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_interface_config_set(unit, port, PM4x10_INFO(pm_info), config, phy_init_flags)); 2057 } else { 2058 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_interface_config_set(unit, port, pm_info, config, phy_init_flags)); 2059 } 2060 2061 exit: 2062 SOC_FUNC_RETURN; 2063 } 2064 2065 int _pm4x10_qtc_port_interface_config_get(int unit, int port, pm_info_t pm_info, portmod_port_interface_config_t* config, int phy_init_flags) 2066 { 2067 int nof_phys; 2068 phymod_phy_inf_config_t phy_interface_config; 2069 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2070 int port_index, max_speed; 2071 uint32 bitmap; 2072 SOC_INIT_FUNC_DEFS; 2073 2074 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 2075 _SOC_IF_ERR_EXIT(PM4x10_QTC_MAX_SPEED_GET(unit, pm_info, &max_speed, port_index)); 2076 2077 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, phy_access ,(1+MAX_PHYN), &nof_phys)); 2078 2079 _SOC_IF_ERR_EXIT(phymod_phy_inf_config_t_init (&phy_interface_config)); 2080 phy_interface_config.data_rate = max_speed; 2081 _SOC_IF_ERR_EXIT 2082 (portmod_port_phychain_interface_config_get(unit, port, phy_access, nof_phys, 2083 0, PM_4x10_QTC_INFO(pm_info)->ref_clk, 2084 &phy_interface_config, phy_init_flags)); 2085 2086 config->speed = phy_interface_config.data_rate; 2087 2088 _SOC_IF_ERR_EXIT(portmod_intf_from_phymod_intf(unit, phy_interface_config.interface_type, &config->interface)); 2089 2090 config->port_num_lanes = SOC_INFO(unit).port_num_lanes[port]; 2091 2092 exit: 2093 SOC_FUNC_RETURN; 2094 } 2095 2096 int pm4x10_qtc_port_interface_config_get(int unit, int port, pm_info_t pm_info, portmod_port_interface_config_t* config, int phy_init_flags) 2097 { 2098 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2099 SOC_INIT_FUNC_DEFS; 2100 2101 PM4x10_QTC_QMOD_GET(pm_info); 2102 2103 if (!IS_QMOD) { 2104 _SOC_IF_ERR_EXIT( 2105 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_interface_config_get(unit, port, PM4x10_INFO(pm_info), config, phy_init_flags)); 2106 } else { 2107 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_interface_config_get(unit, port, pm_info, config, phy_init_flags)); 2108 } 2109 2110 exit: 2111 SOC_FUNC_RETURN; 2112 } 2113 2114 int _pm4x10_qtc_port_default_interface_get(int unit, int port, pm_info_t pm_info, 2115 const portmod_port_interface_config_t* config, 2116 soc_port_if_t* interface) 2117 { 2118 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2119 int nof_phys = 0; 2120 int is_legacy_phy; 2121 int xphy_id; 2122 portmod_port_interface_config_t interface_config; 2123 SOC_INIT_FUNC_DEFS; 2124 2125 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, 2126 phy_access ,(1+MAX_PHYN), 2127 &nof_phys)); 2128 2129 if (nof_phys==1) { 2130 _SOC_IF_ERR_EXIT(_pm4x10_qtc_default_interface_get(unit, port, config, interface)); 2131 } else { 2132 xphy_id = phy_access[nof_phys-1].access.addr; 2133 _SOC_IF_ERR_EXIT(portmod_xphy_is_legacy_phy_get(unit, xphy_id, &is_legacy_phy)); 2134 2135 if (!is_legacy_phy) { 2136 _SOC_IF_ERR_EXIT(portmod_port_phymod_xphy_default_interface_get(unit, 2137 &(phy_access[nof_phys-1]), config, interface)); 2138 } else { 2139 interface_config = *config; 2140 _SOC_IF_ERR_EXIT(portmod_common_default_interface_get(&interface_config)); 2141 *interface = interface_config.interface; 2142 } 2143 } 2144 2145 exit: 2146 SOC_FUNC_RETURN; 2147 } 2148 2149 int pm4x10_qtc_port_default_interface_get(int unit, int port, pm_info_t pm_info, const portmod_port_interface_config_t* config, soc_port_if_t* interface) 2150 { 2151 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2152 SOC_INIT_FUNC_DEFS; 2153 2154 PM4x10_QTC_QMOD_GET(pm_info); 2155 2156 if (!IS_QMOD) { 2157 _SOC_IF_ERR_EXIT( 2158 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_default_interface_get(unit, port, PM4x10_INFO(pm_info), config, interface)); 2159 } else { 2160 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_default_interface_get(unit, port, 2161 pm_info, config, interface)); 2162 } 2163 2164 exit: 2165 SOC_FUNC_RETURN; 2166 } 2167 2168 int _pm4x10_qtc_port_loopback_set(int unit, int port, pm_info_t pm_info, portmod_loopback_mode_t loopback_type, int enable) 2169 { 2170 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2171 int nof_phys; 2172 phymod_loopback_mode_t phymod_lb_type; 2173 SOC_INIT_FUNC_DEFS; 2174 2175 switch (loopback_type) { 2176 case portmodLoopbackMacOuter: 2177 _SOC_IF_ERR_EXIT(unimac_loopback_set(unit, port, enable)); 2178 break; 2179 case portmodLoopbackPhyGloopPCS: 2180 case portmodLoopbackPhyGloopPMD: 2181 case portmodLoopbackPhyRloopPMD: 2182 _SOC_IF_ERR_EXIT(portmod_commmon_portmod_to_phymod_loopback_type(unit, 2183 loopback_type, &phymod_lb_type)); 2184 2185 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, 2186 phy_access ,(1+MAX_PHYN), 2187 &nof_phys)); 2188 2189 _SOC_IF_ERR_EXIT(portmod_port_phychain_loopback_set(unit, port, phy_access, 2190 nof_phys, 2191 phymod_lb_type, 2192 enable)); 2193 break; 2194 default: 2195 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, (_SOC_MSG("unsupported loopback type %d"), loopback_type)); 2196 } 2197 2198 exit: 2199 SOC_FUNC_RETURN; 2200 } 2201 2202 int pm4x10_qtc_port_loopback_set(int unit, int port, pm_info_t pm_info, portmod_loopback_mode_t loopback_type, int enable) 2203 { 2204 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2205 SOC_INIT_FUNC_DEFS; 2206 2207 PM4x10_QTC_QMOD_GET(pm_info); 2208 2209 if (!IS_QMOD) { 2210 _SOC_IF_ERR_EXIT( 2211 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_loopback_set(unit, port, PM4x10_INFO(pm_info), loopback_type, enable)); 2212 } else { 2213 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_loopback_set(unit, port, pm_info, loopback_type, enable)); 2214 } 2215 2216 exit: 2217 SOC_FUNC_RETURN; 2218 } 2219 2220 int _pm4x10_qtc_port_loopback_get(int unit, int port, pm_info_t pm_info, portmod_loopback_mode_t loopback_type, int* enable) 2221 { 2222 int rv, nof_phys; 2223 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2224 uint32_t tmp_enable=0; 2225 phymod_loopback_mode_t phymod_lb_type; 2226 SOC_INIT_FUNC_DEFS; 2227 2228 switch (loopback_type) { 2229 case portmodLoopbackMacOuter: 2230 _SOC_IF_ERR_EXIT(unimac_loopback_get(unit, port, enable)); 2231 break; 2232 case portmodLoopbackPhyGloopPCS: 2233 case portmodLoopbackPhyGloopPMD: 2234 case portmodLoopbackPhyRloopPMD: 2235 _SOC_IF_ERR_EXIT(portmod_commmon_portmod_to_phymod_loopback_type(unit, 2236 loopback_type, &phymod_lb_type)); 2237 _SOC_IF_ERR_EXIT 2238 (portmod_port_chain_phy_access_get(unit, port, pm_info, 2239 phy_access ,(1+MAX_PHYN), 2240 &nof_phys)); 2241 2242 rv = portmod_port_phychain_loopback_get(unit, port, phy_access, 2243 nof_phys, 2244 phymod_lb_type, 2245 &tmp_enable); 2246 if (rv == PHYMOD_E_UNAVAIL) { 2247 rv = PHYMOD_E_NONE; 2248 tmp_enable = 0; 2249 } 2250 2251 _SOC_IF_ERR_EXIT(rv); 2252 *enable = tmp_enable; 2253 2254 break; 2255 default: 2256 (*enable) = 0; 2257 } 2258 2259 exit: 2260 SOC_FUNC_RETURN; 2261 } 2262 2263 int pm4x10_qtc_port_loopback_get(int unit, int port, pm_info_t pm_info, portmod_loopback_mode_t loopback_type, int* enable) 2264 { 2265 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2266 SOC_INIT_FUNC_DEFS; 2267 2268 PM4x10_QTC_QMOD_GET(pm_info); 2269 2270 if (!IS_QMOD) { 2271 _SOC_IF_ERR_EXIT( 2272 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_loopback_get(unit, port, PM4x10_INFO(pm_info), loopback_type, enable)); 2273 } else { 2274 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_loopback_get(unit, port, pm_info, loopback_type, enable)); 2275 } 2276 2277 exit: 2278 SOC_FUNC_RETURN; 2279 } 2280 2281 int _pm4x10_qtc_port_core_access_get (int unit, int port, 2282 pm_info_t pm_info, int phyn, int max_cores, 2283 phymod_core_access_t* core_access_arr, 2284 int* nof_cores, 2285 int* is_most_ext) 2286 { 2287 int port_index; 2288 uint32 bitmap; 2289 int index; 2290 int done=0; 2291 int i,j, is_legacy_phy; 2292 uint32 xphy_id; 2293 phymod_core_access_t core_access; 2294 SOC_INIT_FUNC_DEFS; 2295 2296 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 2297 2298 if(phyn > PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index]){ 2299 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 2300 (_SOC_MSG("phyn exceeded. max allowed %d. got %d"), 2301 PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index] - 1, phyn)); 2302 } 2303 2304 if(phyn < 0) 2305 { 2306 phyn = PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index] - 1; 2307 } 2308 2309 _SOC_IF_ERR_EXIT(phymod_core_access_t_init(&core_access_arr[0])); 2310 2311 if( phyn == 0 ){ 2312 sal_memcpy(&core_access_arr[0], &(PM_4x10_QTC_INFO(pm_info)->int_core_access), 2313 sizeof(phymod_core_access_t)); 2314 *nof_cores = 1; 2315 } else { 2316 index = 0; 2317 done = 0; 2318 for(i=0 ; (i< MAX_PORTS_PER_PM4X10_QTC); i++) { 2319 if(bitmap & (0x1U << i)) { 2320 xphy_id = PM_4x10_QTC_INFO(pm_info)->lane_conn[phyn-1][i].xphy_id; 2321 if(xphy_id != PORTMOD_XPHY_ID_INVALID){ 2322 if(index == 0){ 2323 _SOC_IF_ERR_EXIT(portmod_xphy_core_access_get(unit, xphy_id, &core_access, &is_legacy_phy)); 2324 sal_memcpy(&core_access_arr[index], &core_access, 2325 sizeof(phymod_core_access_t)); 2326 index++; 2327 } else { 2328 for( j = 0 ; (j < index) &&(!done) ; j++) { 2329 if((!sal_memcmp (&core_access_arr[j], &core_access, 2330 sizeof(phymod_core_access_t)))) { /* found a match */ 2331 done = 1; 2332 } 2333 } 2334 if((!done) && (index < max_cores)){ 2335 sal_memcpy(&core_access_arr[index], &core_access, 2336 sizeof(phymod_core_access_t)); 2337 index++; 2338 } 2339 } 2340 } 2341 } 2342 } 2343 *nof_cores = index; 2344 } 2345 if (is_most_ext) { 2346 if (phyn == PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index]-1) { 2347 *is_most_ext = 1; 2348 } else { 2349 *is_most_ext = 0; 2350 } 2351 } 2352 2353 exit: 2354 SOC_FUNC_RETURN; 2355 } 2356 2357 int pm4x10_qtc_port_core_access_get(int unit, int port, pm_info_t pm_info, int phyn, int max_cores, phymod_core_access_t* core_access_arr, int* nof_cores, int* is_most_ext) 2358 { 2359 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2360 SOC_INIT_FUNC_DEFS; 2361 2362 PM4x10_QTC_QMOD_GET(pm_info); 2363 2364 if (!IS_QMOD) { 2365 _SOC_IF_ERR_EXIT( 2366 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_core_access_get(unit, port, 2367 PM4x10_INFO(pm_info), phyn, max_cores, core_access_arr, nof_cores, is_most_ext)); 2368 } else { 2369 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_core_access_get(unit, port, pm_info, 2370 phyn, max_cores, core_access_arr, nof_cores, is_most_ext)); 2371 } 2372 2373 exit: 2374 SOC_FUNC_RETURN; 2375 } 2376 2377 int _pm4x10_qtc_port_phy_lane_access_get(int unit, int port, pm_info_t pm_info, 2378 const portmod_access_get_params_t* params, 2379 int max_phys, 2380 phymod_phy_access_t* access, 2381 int* nof_phys, 2382 int* is_most_ext) 2383 { 2384 int rv; 2385 int phyn = 0; 2386 uint32 bitmap, lane_mask[MAX_NUM_CORES]; 2387 int port_index; 2388 uint32 iphy_lane_mask = 0; 2389 int serdes_lane=0; 2390 int xphy_lane_mask=0; 2391 uint32 xphy_id = 0; 2392 phymod_core_access_t core_access; 2393 phymod_port_loc_t port_loc[MAX_NUM_CORES]; 2394 int i, is_legacy_phy; 2395 uint32 xphy_idx; 2396 int num_of_phys; 2397 int done; 2398 SOC_INIT_FUNC_DEFS; 2399 2400 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 2401 2402 SHR_BITSET(&iphy_lane_mask, port_index); 2403 2404 if(params->phyn >= PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index]){ 2405 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 2406 (_SOC_MSG("phyn exceeded. max allowed %d. got %d"), 2407 PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index] - 1, params->phyn)); 2408 } 2409 2410 for( i = 0 ; i < max_phys; i++) { 2411 lane_mask[i] = 0; 2412 _SOC_IF_ERR_EXIT(phymod_phy_access_t_init(&access[i])); 2413 } 2414 2415 phyn = params->phyn; 2416 2417 /* if phyn is -1, it is looking for outer most phy. 2418 assumption is that all lane has same phy depth. */ 2419 if(phyn < 0) { 2420 phyn = PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index] - 1; 2421 } 2422 2423 if( phyn == 0 ) { 2424 /* internal core */ 2425 sal_memcpy (&access[0], &(PM_4x10_QTC_INFO(pm_info)->int_core_access), 2426 sizeof(phymod_phy_access_t)); 2427 access[0].access.lane_mask = 1 << port_index; 2428 if (params->lane != -1) { 2429 serdes_lane = port_index + params->lane; 2430 access[0].access.lane_mask &= (0x1 << serdes_lane ); 2431 if (access[0].access.lane_mask == 0) { 2432 *nof_phys = 0; 2433 } 2434 } 2435 *nof_phys = 1; 2436 access[0].port_loc = phymodPortLocLine; /* only line is availabe for internal. */ 2437 2438 /* if it is warm boot, get probed information from wb db instead of re-probing. */ 2439 if(SOC_WARM_BOOT(unit)) { 2440 rv = PM4x10_QTC_PHY_TYPE_GET(unit, pm_info, &(access[0].type)); 2441 _SOC_IF_ERR_EXIT(rv); 2442 } 2443 } else { 2444 /* external phy */ 2445 num_of_phys = 0; 2446 2447 /* xphy idx is 1 less than phyn since internal core does not count */ 2448 xphy_idx = phyn-1; 2449 2450 if (params->lane != -1) { /* specific lane */ 2451 serdes_lane = port_index + params->lane; 2452 xphy_id = PM_4x10_QTC_INFO(pm_info)->lane_conn[xphy_idx][serdes_lane].xphy_id; 2453 _SOC_IF_ERR_EXIT(portmod_xphy_core_access_get(unit, xphy_id, &core_access, &is_legacy_phy)); 2454 sal_memcpy (&access[num_of_phys], &core_access, 2455 sizeof(phymod_phy_access_t)); 2456 xphy_lane_mask = ( params->sys_side == PORTMOD_SIDE_SYSTEM)? PM_4x10_QTC_INFO(pm_info)->lane_conn[xphy_idx][serdes_lane].ss_lane_mask: 2457 PM_4x10_QTC_INFO(pm_info)->lane_conn[xphy_idx][serdes_lane].ls_lane_mask; 2458 if (xphy_lane_mask != -1) { 2459 access[0].access.lane_mask |= xphy_lane_mask; 2460 } 2461 access[0].port_loc = ( params->sys_side == PORTMOD_SIDE_SYSTEM) ? 2462 phymodPortLocSys : phymodPortLocLine; 2463 *nof_phys = 1; 2464 } else { /* all lanes */ 2465 /* go thru all the lanes related to this port. */ 2466 serdes_lane = 0; 2467 2468 for (serdes_lane = 0; serdes_lane < MAX_PORTS_PER_PM4X10_QTC; serdes_lane++) { 2469 if (iphy_lane_mask & (1U<<serdes_lane)) { 2470 xphy_id = PM_4x10_QTC_INFO(pm_info)->lane_conn[xphy_idx][serdes_lane].xphy_id; 2471 if(xphy_id != PORTMOD_XPHY_ID_INVALID) { 2472 _SOC_IF_ERR_EXIT(portmod_xphy_core_access_get(unit, xphy_id, &core_access, &is_legacy_phy)); 2473 if(num_of_phys == 0 ) {/* first one */ 2474 sal_memcpy (&access[num_of_phys], &core_access, 2475 sizeof(phymod_phy_access_t)); 2476 xphy_lane_mask = ( params->sys_side == PORTMOD_SIDE_SYSTEM)? 2477 PM_4x10_QTC_INFO(pm_info)->lane_conn[xphy_idx][serdes_lane].ss_lane_mask: 2478 PM_4x10_QTC_INFO(pm_info)->lane_conn[xphy_idx][serdes_lane].ls_lane_mask; 2479 if( xphy_lane_mask != -1) { 2480 lane_mask[num_of_phys] |= xphy_lane_mask; 2481 } 2482 port_loc[num_of_phys] = (params->sys_side == PORTMOD_SIDE_SYSTEM) ? 2483 phymodPortLocSys : phymodPortLocLine; 2484 num_of_phys++; 2485 } else { 2486 /* if not the first one, see if this one sharing core with other lanes. */ 2487 done = 0; 2488 for( i = 0 ; (i < num_of_phys) &&(!done) ; i++) { 2489 if((!sal_memcmp (&access[i], &core_access, 2490 sizeof(phymod_phy_access_t)))) { /* found a match */ 2491 /* update lane */ 2492 xphy_lane_mask = ( params->sys_side == PORTMOD_SIDE_SYSTEM)? 2493 PM_4x10_QTC_INFO(pm_info)->lane_conn[xphy_idx][serdes_lane].ss_lane_mask: 2494 PM_4x10_QTC_INFO(pm_info)->lane_conn[xphy_idx][serdes_lane].ls_lane_mask; 2495 if( xphy_lane_mask != -1) { 2496 lane_mask[i] |= xphy_lane_mask; 2497 } 2498 done = 1; 2499 } 2500 } 2501 if((!done) && (num_of_phys < max_phys)){ 2502 sal_memcpy (&access[num_of_phys], &core_access, 2503 sizeof(phymod_phy_access_t)); 2504 xphy_lane_mask = ( params->sys_side == PORTMOD_SIDE_SYSTEM)? 2505 PM_4x10_QTC_INFO(pm_info)->lane_conn[xphy_idx][serdes_lane].ss_lane_mask: 2506 PM_4x10_QTC_INFO(pm_info)->lane_conn[xphy_idx][serdes_lane].ls_lane_mask; 2507 if( xphy_lane_mask != -1) { 2508 lane_mask[num_of_phys] |= xphy_lane_mask; 2509 } 2510 port_loc[num_of_phys] = ( params->sys_side == PORTMOD_SIDE_SYSTEM)? 2511 phymodPortLocSys : phymodPortLocLine ; 2512 num_of_phys++; 2513 } 2514 } 2515 } 2516 } 2517 } 2518 *nof_phys = num_of_phys; 2519 for( i = 0 ; (i < *nof_phys) ; i++) { 2520 access[i].access.lane_mask = lane_mask[i]; 2521 access[i].port_loc = port_loc[i]; 2522 } 2523 } 2524 } 2525 2526 if (is_most_ext) { 2527 if (phyn == PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index]-1) { 2528 *is_most_ext = 1; 2529 } else { 2530 *is_most_ext = 0; 2531 } 2532 } 2533 2534 2535 exit: 2536 SOC_FUNC_RETURN; 2537 } 2538 2539 int pm4x10_qtc_port_phy_lane_access_get(int unit, int port, pm_info_t pm_info, const portmod_access_get_params_t* params, int max_phys, phymod_phy_access_t* access, int* nof_phys, int* is_most_ext) 2540 { 2541 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2542 SOC_INIT_FUNC_DEFS; 2543 2544 PM4x10_QTC_QMOD_GET(pm_info); 2545 2546 if (!IS_QMOD) { 2547 _SOC_IF_ERR_EXIT( 2548 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_lane_access_get(unit, port, 2549 PM4x10_INFO(pm_info), params, max_phys, access, nof_phys, is_most_ext)); 2550 } else { 2551 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_phy_lane_access_get(unit, port, pm_info, 2552 params, max_phys, access, nof_phys, is_most_ext)); 2553 } 2554 2555 exit: 2556 SOC_FUNC_RETURN; 2557 } 2558 2559 int _pm4x10_qtc_port_autoneg_set(int unit, int port, pm_info_t pm_info, uint32 phy_flags, const phymod_autoneg_control_t* an) 2560 { 2561 int rv; 2562 uint32 bitmap, port_dynamic_state; 2563 int port_index; 2564 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2565 int nof_phys; 2566 uint32 an_done; 2567 phymod_autoneg_control_t *pAn = (phymod_autoneg_control_t*)an; 2568 SOC_INIT_FUNC_DEFS; 2569 2570 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 2571 2572 if(PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index] == 0) { 2573 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, (_SOC_MSG("AN isn't supported"))); 2574 } else { 2575 if (pAn->num_lane_adv == 0) { 2576 pAn->num_lane_adv = 1; 2577 } 2578 2579 if (pAn->an_mode == phymod_AN_MODE_NONE) { 2580 rv = PM4x10_QTC_AN_MODE_GET(unit, pm_info, &pAn->an_mode, port_index); 2581 _SOC_IF_ERR_EXIT(rv); 2582 } 2583 2584 if (pAn->an_mode == phymod_AN_MODE_NONE) { 2585 pAn->an_mode = phymod_AN_MODE_SGMII; 2586 } 2587 2588 rv = PM4x10_QTC_PORT_DYNAMIC_STATE_GET(unit, pm_info, 2589 &port_dynamic_state, port_index); 2590 _SOC_IF_ERR_EXIT(rv); 2591 2592 if (PORTMOD_PORT_IS_AUTONEG_MODE_UPDATED(port_dynamic_state)) { 2593 rv = PM4x10_QTC_AN_MODE_GET(unit, pm_info, &pAn->an_mode, port_index); 2594 _SOC_IF_ERR_EXIT(rv); 2595 2596 PORTMOD_PORT_AUTONEG_MODE_UPDATED_CLR(port_dynamic_state); 2597 rv = PM4x10_QTC_PORT_DYNAMIC_STATE_SET(unit, pm_info, 2598 port_dynamic_state, port_index); 2599 _SOC_IF_ERR_EXIT(rv); 2600 } 2601 2602 _SOC_IF_ERR_EXIT 2603 (portmod_port_chain_phy_access_get(unit, port, pm_info, 2604 phy_access ,(1+MAX_PHYN), 2605 &nof_phys)); 2606 2607 /* In case of warm boot, get autoneg informaton from hardware */ 2608 if (SOC_WARM_BOOT(unit)) { 2609 if (pAn->an_mode >= phymod_AN_MODE_Count) { 2610 _SOC_IF_ERR_EXIT 2611 (portmod_port_phychain_autoneg_get(unit, port, phy_access, nof_phys, phy_flags, pAn, &an_done)); 2612 } 2613 } 2614 2615 rv = portmod_port_phychain_autoneg_set(unit, port, phy_access, nof_phys, phy_flags, an); 2616 /* Because the returned value PHYMOD_E_UNAVAIL is -12 from tscf phymod driver */ 2617 if (rv == PHYMOD_E_UNAVAIL) { 2618 rv = SOC_E_UNAVAIL; 2619 } 2620 _SOC_IF_ERR_EXIT(rv); 2621 } 2622 2623 exit: 2624 SOC_FUNC_RETURN; 2625 } 2626 2627 int pm4x10_qtc_port_autoneg_set(int unit, int port, pm_info_t pm_info, uint32 phy_flags, const phymod_autoneg_control_t* an) 2628 { 2629 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2630 SOC_INIT_FUNC_DEFS; 2631 2632 PM4x10_QTC_QMOD_GET(pm_info); 2633 2634 if (!IS_QMOD) { 2635 _SOC_IF_ERR_EXIT( 2636 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_autoneg_set(unit, port, 2637 PM4x10_INFO(pm_info), phy_flags, an)); 2638 } else { 2639 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_autoneg_set(unit, port, pm_info, phy_flags, an)); 2640 } 2641 2642 exit: 2643 SOC_FUNC_RETURN; 2644 } 2645 2646 int _pm4x10_qtc_port_autoneg_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, phymod_autoneg_control_t* an) 2647 { 2648 int rv; 2649 int port_index; 2650 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2651 int nof_phys; 2652 uint32 bitmap, an_done; 2653 SOC_INIT_FUNC_DEFS; 2654 2655 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 2656 2657 if (PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index] == 0) { 2658 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, (_SOC_MSG("AN isn't supported"))); 2659 } else { 2660 if (an->num_lane_adv == 0) { 2661 an->num_lane_adv = 1; 2662 } 2663 rv = PM4x10_QTC_AN_MODE_GET(unit, pm_info, &an->an_mode, port_index); 2664 _SOC_IF_ERR_EXIT(rv); 2665 2666 if (an->an_mode == phymod_AN_MODE_NONE) { 2667 an->an_mode = phymod_AN_MODE_SGMII; 2668 } 2669 2670 _SOC_IF_ERR_EXIT 2671 (portmod_port_chain_phy_access_get(unit, port, pm_info, 2672 phy_access ,(1+MAX_PHYN), 2673 &nof_phys)); 2674 _SOC_IF_ERR_EXIT 2675 (portmod_port_phychain_autoneg_get(unit, port, phy_access, nof_phys, phy_flags, an, &an_done)); 2676 } 2677 2678 exit: 2679 SOC_FUNC_RETURN; 2680 } 2681 2682 int pm4x10_qtc_port_autoneg_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, phymod_autoneg_control_t* an) 2683 { 2684 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2685 SOC_INIT_FUNC_DEFS; 2686 2687 PM4x10_QTC_QMOD_GET(pm_info); 2688 2689 if (!IS_QMOD) { 2690 _SOC_IF_ERR_EXIT( 2691 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_autoneg_get(unit, port, 2692 PM4x10_INFO(pm_info), phy_flags, an)); 2693 } else { 2694 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_autoneg_get(unit, port, pm_info, phy_flags, an)); 2695 } 2696 2697 exit: 2698 SOC_FUNC_RETURN; 2699 } 2700 2701 int _pm4x10_qtc_port_ability_local_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, portmod_port_ability_t* ability) 2702 { 2703 int port_index, rv; 2704 int max_speed; 2705 uint32 bitmap; 2706 portmod_port_ability_t legacy_phy_ability; 2707 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2708 int nof_phys, xphy_id, is_legacy_phy; 2709 SOC_INIT_FUNC_DEFS; 2710 2711 sal_memset(ability, 0, sizeof(portmod_port_ability_t)); 2712 sal_memset(&legacy_phy_ability, 0, sizeof(portmod_port_ability_t)); 2713 2714 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, 2715 phy_access, (1+MAX_PHYN), &nof_phys)); 2716 2717 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 2718 2719 rv = PM4x10_QTC_MAX_SPEED_GET(unit, pm_info, &max_speed, port_index); 2720 _SOC_IF_ERR_EXIT(rv); 2721 2722 ability->speed_half_duplex = SOC_PA_ABILITY_NONE; 2723 ability->medium = SOC_PA_MEDIUM_COPPER; 2724 ability->interface = SOC_PA_INTF_SGMII; 2725 ability->loopback = SOC_PA_LB_PHY | SOC_PA_LB_MAC; 2726 ability->fec = SOC_PA_FEC_NONE; 2727 ability->encap = SOC_PA_ENCAP_IEEE; 2728 2729 switch(max_speed) { /* must include all the supported speeds */ 2730 /* coverity[unterminated_case] */ 2731 case 2500: 2732 ability->speed_full_duplex |= SOC_PA_SPEED_2500MB; 2733 /* coverity[unterminated_case] */ 2734 case 1000: 2735 ability->speed_full_duplex |= SOC_PA_SPEED_1000MB; 2736 /* coverity[unterminated_case] */ 2737 case 100: 2738 ability->speed_full_duplex |= SOC_PA_SPEED_100MB; 2739 case 10: 2740 ability->speed_full_duplex |= SOC_PA_SPEED_10MB; 2741 default: 2742 break; 2743 } 2744 2745 /* If legacy external phy presents, retrieve the local ability from the 2746 * external phy as it has more variants and the ability might vary for each. 2747 * However, if this function is called by the legacy ext PHY driver through 2748 * the PORTMOD callback function portmod_ext_to_int_cmd_get(), the returned 2749 * data should be of the internal SERDES. portmod_ext_to_int_cmd_get() uses 2750 * PORTMOD_USER_ACC_CMD_FOR_PHY_SET() to hint its callees that the target 2751 * of data retrieving is the internal SERDES. 2752 */ 2753 if (nof_phys > 1 && !(phy_flags == PORTMOD_INIT_F_INTERNAL_SERDES_ONLY)) { 2754 /* check if the legacy phy present */ 2755 xphy_id = phy_access[nof_phys-1].access.addr; 2756 _SOC_IF_ERR_EXIT(portmod_xphy_is_legacy_phy_get(unit, xphy_id, &is_legacy_phy)); 2757 if(is_legacy_phy) { 2758 /* call portmod phy chain function to retrieve the ability */ 2759 _SOC_IF_ERR_EXIT 2760 (portmod_port_phychain_local_ability_get(unit, port, phy_access, 2761 nof_phys, &legacy_phy_ability)); 2762 /* PHY driver returns all the speeds supported by PHY 2763 * Advertise only the speeds supported by both PortMacro and the PHY 2764 */ 2765 legacy_phy_ability.speed_full_duplex &= ability->speed_full_duplex; 2766 /* PHY driver may not return all supported encap modes 2767 * Advertise encap modes supported by both PortMacro and the PHY 2768 */ 2769 legacy_phy_ability.encap |= ability->encap; 2770 *ability = legacy_phy_ability; 2771 } else { 2772 /* We might need to consider calling portmod phy chain for 2773 * non legacy phys as well*/ 2774 } 2775 } 2776 2777 exit: 2778 SOC_FUNC_RETURN; 2779 } 2780 2781 int pm4x10_qtc_port_ability_local_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, portmod_port_ability_t* ability) 2782 { 2783 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2784 SOC_INIT_FUNC_DEFS; 2785 2786 PM4x10_QTC_QMOD_GET(pm_info); 2787 2788 if (!IS_QMOD) { 2789 _SOC_IF_ERR_EXIT( 2790 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_ability_local_get(unit, port, 2791 PM4x10_INFO(pm_info), phy_flags, ability)); 2792 } else { 2793 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_ability_local_get(unit, port, pm_info, phy_flags, ability)); 2794 } 2795 2796 exit: 2797 SOC_FUNC_RETURN; 2798 } 2799 2800 int _pm4x10_qtc_port_ability_advert_set(int unit, int port, pm_info_t pm_info, uint32 phy_flags, 2801 portmod_port_ability_t* ability) 2802 { 2803 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2804 int nof_phys = 0, port_index, rv; 2805 portmod_port_ability_t port_ability; 2806 phymod_autoneg_ability_t an_ability; 2807 portmod_access_get_params_t params; 2808 int port_num_lanes = 1, line_interface, cx4_10g = 0; 2809 int an_cl72 = 0, an_fec = 0, hg_mode = 0; 2810 uint32 bitmap; 2811 SOC_INIT_FUNC_DEFS; 2812 2813 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 2814 2815 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 2816 params.lane = -1; 2817 params.phyn = 0; 2818 params.sys_side = PORTMOD_SIDE_LINE; 2819 2820 _SOC_IF_ERR_EXIT 2821 (pm4x10_qtc_port_ability_local_get(unit, port, pm_info, phy_flags, &port_ability)); 2822 2823 /* Make sure to advertise only abilities supported by the port */ 2824 port_ability.pause &= ability->pause; 2825 port_ability.interface &= ability->interface; 2826 port_ability.medium &= ability->medium; 2827 port_ability.eee &= ability->eee; 2828 port_ability.loopback &= ability->loopback; 2829 port_ability.flags &= ability->flags; 2830 port_ability.speed_half_duplex &= ability->speed_half_duplex; 2831 port_ability.speed_full_duplex &= ability->speed_full_duplex; 2832 port_ability.fec &= ability->fec; 2833 port_ability.channel &= ability->channel; 2834 2835 rv = PM4x10_QTC_INTERFACE_TYPE_GET(unit, pm_info, &line_interface, port_index); 2836 _SOC_IF_ERR_EXIT(rv); 2837 2838 portmod_common_port_to_phy_ability(&port_ability, &an_ability, 2839 port_num_lanes, line_interface, cx4_10g, 2840 an_cl72, an_fec, hg_mode); 2841 2842 _SOC_IF_ERR_EXIT 2843 (portmod_port_chain_phy_access_get(unit, port, pm_info, 2844 phy_access ,(1+MAX_PHYN), 2845 &nof_phys)); 2846 2847 _SOC_IF_ERR_EXIT 2848 (portmod_port_phychain_autoneg_ability_set(unit, port, phy_access, nof_phys, phy_flags, 2849 &an_ability, &port_ability)); 2850 2851 LOG_VERBOSE(BSL_LS_BCM_PORT, 2852 (BSL_META_U(unit, 2853 "Speed(HD=0x%08x, FD=0x%08x) Pause=0x%08x orig(HD=0x%08x, FD=0x%08x) \n" 2854 "Interface=0x%08x Medium=0x%08x Loopback=0x%08x Flags=0x%08x\n"), 2855 port_ability.speed_half_duplex, 2856 port_ability.speed_full_duplex, 2857 port_ability.pause, 2858 ability->speed_half_duplex, 2859 ability->speed_full_duplex, 2860 port_ability.interface, 2861 port_ability.medium, port_ability.loopback, 2862 port_ability.flags)); 2863 exit: 2864 SOC_FUNC_RETURN; 2865 } 2866 2867 int pm4x10_qtc_port_ability_advert_set(int unit, int port, pm_info_t pm_info, uint32 phy_flags, portmod_port_ability_t* ability) 2868 { 2869 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2870 SOC_INIT_FUNC_DEFS; 2871 2872 PM4x10_QTC_QMOD_GET(pm_info); 2873 2874 if (!IS_QMOD) { 2875 _SOC_IF_ERR_EXIT( 2876 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_ability_advert_set(unit, port, 2877 PM4x10_INFO(pm_info), phy_flags, ability)); 2878 } else { 2879 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_ability_advert_set(unit, port, pm_info, phy_flags, ability)); 2880 } 2881 2882 exit: 2883 SOC_FUNC_RETURN; 2884 } 2885 2886 int _pm4x10_qtc_port_ability_advert_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, 2887 portmod_port_ability_t* ability) 2888 { 2889 phymod_phy_access_t phy_access[1+MAX_PHYN]; 2890 int nof_phys = 0; 2891 phymod_autoneg_ability_t an_ability; 2892 portmod_port_ability_t port_ability; 2893 int phy_index, xphy_id, is_legacy_phy = 0; 2894 SOC_INIT_FUNC_DEFS; 2895 2896 _SOC_IF_ERR_EXIT 2897 (portmod_port_chain_phy_access_get(unit, port, pm_info, 2898 phy_access ,(1+MAX_PHYN), 2899 &nof_phys)); 2900 2901 _SOC_IF_ERR_EXIT 2902 (portmod_port_phychain_autoneg_ability_get(unit, port, phy_access, nof_phys, phy_flags, 2903 &an_ability, &port_ability)); 2904 2905 phy_index = nof_phys -1; 2906 if (phy_index) { 2907 xphy_id = phy_access[phy_index].access.addr; 2908 _SOC_IF_ERR_EXIT(portmod_xphy_is_legacy_phy_get(unit, xphy_id, &is_legacy_phy)); 2909 if (is_legacy_phy) { 2910 sal_memcpy(ability, &port_ability, sizeof(portmod_port_ability_t)); 2911 } 2912 } 2913 if (!is_legacy_phy) { 2914 portmod_common_phy_to_port_ability(&an_ability, ability); 2915 } 2916 2917 exit: 2918 SOC_FUNC_RETURN; 2919 } 2920 2921 2922 int pm4x10_qtc_port_ability_advert_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, portmod_port_ability_t* ability) 2923 { 2924 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2925 SOC_INIT_FUNC_DEFS; 2926 2927 PM4x10_QTC_QMOD_GET(pm_info); 2928 2929 if (!IS_QMOD) { 2930 _SOC_IF_ERR_EXIT( 2931 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_ability_advert_get(unit, port, 2932 PM4x10_INFO(pm_info), phy_flags, ability)); 2933 } else { 2934 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_ability_advert_get(unit, port, pm_info, phy_flags, ability)); 2935 } 2936 2937 exit: 2938 SOC_FUNC_RETURN; 2939 } 2940 2941 int pm4x10_qtc_port_interface_check(int unit, int port, pm_info_t pm_info, 2942 const portmod_port_interface_config_t* config, 2943 int is_ext_phy, soc_port_if_t interface, 2944 int* is_valid) 2945 { 2946 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 2947 SOC_INIT_FUNC_DEFS; 2948 2949 PM4x10_QTC_QMOD_GET(pm_info); 2950 2951 if (!IS_QMOD) { 2952 _SOC_IF_ERR_EXIT( 2953 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_interface_check(unit, port, 2954 PM4x10_INFO(pm_info), config, is_ext_phy, interface, is_valid)); 2955 } else { 2956 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_interface_check(unit, port, pm_info, config, 2957 is_ext_phy, interface, is_valid)); 2958 } 2959 2960 exit: 2961 SOC_FUNC_RETURN; 2962 } 2963 2964 int _pm4x10_qtc_port_update_dynamic_state(int unit, int port, pm_info_t pm_info, uint32_t port_dynamic_state) 2965 { 2966 int rv = 0; 2967 int port_index; 2968 phymod_an_mode_type_t an_mode; 2969 uint32 bitmap, an_updated = FALSE, tmp_state; 2970 SOC_INIT_FUNC_DEFS; 2971 2972 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get(unit, port, pm_info, &port_index, &bitmap)); 2973 2974 if (PORTMOD_PORT_IS_AUTONEG_MODE_UPDATED(port_dynamic_state)) { 2975 rv = PM4x10_QTC_PORT_DYNAMIC_STATE_GET(unit, pm_info, &tmp_state, 2976 port_index); 2977 _SOC_IF_ERR_EXIT(rv); 2978 /*we need to change the data base An_mode based on the new value */ 2979 switch (port_dynamic_state >> 16 & 0xffff) { 2980 case SOC_PHY_CONTROL_AUTONEG_MODE_CL37: 2981 an_mode = phymod_AN_MODE_CL37; 2982 an_updated = TRUE; 2983 break; 2984 case SOC_PHY_CONTROL_AUTONEG_MODE_CL37_BAM: 2985 an_mode = phymod_AN_MODE_CL37BAM; 2986 an_updated = TRUE; 2987 break; 2988 default: 2989 break; 2990 } 2991 } else if (PORTMOD_PORT_IS_DEFAULT_TX_PARAMS_UPDATED(port_dynamic_state)) { 2992 rv = PM4x10_QTC_PORT_DYNAMIC_STATE_SET(unit, pm_info, 2993 port_dynamic_state, port_index); 2994 _SOC_IF_ERR_EXIT(rv); 2995 } 2996 if (an_updated == TRUE) { 2997 rv = PM4x10_QTC_AN_MODE_SET(unit, pm_info, an_mode, port_index); 2998 _SOC_IF_ERR_EXIT(rv); 2999 PORTMOD_PORT_AUTONEG_MODE_UPDATED_SET(tmp_state); 3000 rv = PM4x10_QTC_PORT_DYNAMIC_STATE_SET(unit, pm_info, tmp_state, 3001 port_index); 3002 _SOC_IF_ERR_EXIT(rv); 3003 } 3004 3005 exit: 3006 SOC_FUNC_RETURN; 3007 } 3008 3009 int pm4x10_qtc_port_update_dynamic_state(int unit, int port, pm_info_t pm_info, uint32_t port_dynamic_state) 3010 { 3011 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3012 SOC_INIT_FUNC_DEFS; 3013 3014 PM4x10_QTC_QMOD_GET(pm_info); 3015 3016 if (!IS_QMOD) { 3017 _SOC_IF_ERR_EXIT( 3018 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_update_dynamic_state(unit, port, 3019 PM4x10_INFO(pm_info), port_dynamic_state)); 3020 } else { 3021 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_update_dynamic_state(unit, port, 3022 pm_info, port_dynamic_state)); 3023 } 3024 3025 exit: 3026 SOC_FUNC_RETURN; 3027 } 3028 3029 int pm4x10_qtc_port_tx_average_ipg_set(int unit, int port, pm_info_t pm_info, int value) 3030 { 3031 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3032 SOC_INIT_FUNC_DEFS; 3033 3034 PM4x10_QTC_QMOD_GET(pm_info); 3035 3036 if (!IS_QMOD) { 3037 _SOC_IF_ERR_EXIT( 3038 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_tx_average_ipg_set(unit, port, 3039 PM4x10_INFO(pm_info), value)); 3040 } else { 3041 _SOC_IF_ERR_EXIT(unimac_tx_average_ipg_set(unit, port, value)); 3042 } 3043 3044 exit: 3045 SOC_FUNC_RETURN; 3046 } 3047 3048 int pm4x10_qtc_port_tx_average_ipg_get(int unit, int port, pm_info_t pm_info, int* value) 3049 { 3050 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3051 SOC_INIT_FUNC_DEFS; 3052 3053 PM4x10_QTC_QMOD_GET(pm_info); 3054 3055 if (!IS_QMOD) { 3056 _SOC_IF_ERR_EXIT( 3057 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_tx_average_ipg_get(unit, port, 3058 PM4x10_INFO(pm_info), value)); 3059 } else { 3060 _SOC_IF_ERR_EXIT(unimac_tx_average_ipg_get(unit, port, value)); 3061 } 3062 3063 exit: 3064 SOC_FUNC_RETURN; 3065 } 3066 3067 int pm4x10_qtc_port_encap_set(int unit, int port, pm_info_t pm_info, int flags, portmod_encap_t encap) 3068 { 3069 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3070 SOC_INIT_FUNC_DEFS; 3071 3072 PM4x10_QTC_QMOD_GET(pm_info); 3073 3074 if (!IS_QMOD) { 3075 _SOC_IF_ERR_EXIT( 3076 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_encap_set(unit, port, 3077 PM4x10_INFO(pm_info), flags, encap)); 3078 } else { 3079 _SOC_IF_ERR_EXIT(unimac_encap_set(unit, port, encap)); 3080 } 3081 3082 exit: 3083 SOC_FUNC_RETURN; 3084 } 3085 3086 3087 int pm4x10_qtc_port_encap_get(int unit, int port, pm_info_t pm_info, int *flags, portmod_encap_t *encap) 3088 { 3089 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3090 SOC_INIT_FUNC_DEFS; 3091 3092 PM4x10_QTC_QMOD_GET(pm_info); 3093 3094 if (!IS_QMOD) { 3095 _SOC_IF_ERR_EXIT( 3096 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_encap_get(unit, port, 3097 PM4x10_INFO(pm_info), flags, encap)); 3098 } else { 3099 _SOC_IF_ERR_EXIT(unimac_encap_get(unit, port, encap)); 3100 } 3101 3102 exit: 3103 SOC_FUNC_RETURN; 3104 } 3105 3106 int pm4x10_qtc_port_eee_set(int unit, int port, pm_info_t pm_info,const portmod_eee_t* eee) 3107 { 3108 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3109 SOC_INIT_FUNC_DEFS; 3110 3111 PM4x10_QTC_QMOD_GET(pm_info); 3112 3113 if (!IS_QMOD) { 3114 _SOC_IF_ERR_EXIT( 3115 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_eee_set(unit, port, 3116 PM4x10_INFO(pm_info), eee)); 3117 } else { 3118 _SOC_IF_ERR_EXIT(unimac_eee_set(unit, port, eee)); 3119 } 3120 3121 exit: 3122 SOC_FUNC_RETURN; 3123 } 3124 3125 int pm4x10_qtc_port_eee_get(int unit, int port, pm_info_t pm_info, portmod_eee_t* eee) 3126 { 3127 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3128 SOC_INIT_FUNC_DEFS; 3129 3130 PM4x10_QTC_QMOD_GET(pm_info); 3131 3132 if (!IS_QMOD) { 3133 _SOC_IF_ERR_EXIT( 3134 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_eee_get(unit, port, 3135 PM4x10_INFO(pm_info), eee)); 3136 } else { 3137 _SOC_IF_ERR_EXIT(unimac_eee_get(unit, port, eee)); 3138 } 3139 3140 exit: 3141 SOC_FUNC_RETURN; 3142 } 3143 3144 int pm4x10_qtc_port_speed_get(int unit, int port, pm_info_t pm_info, int* speed) 3145 { 3146 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3147 SOC_INIT_FUNC_DEFS; 3148 3149 PM4x10_QTC_QMOD_GET(pm_info); 3150 3151 if (!IS_QMOD) { 3152 _SOC_IF_ERR_EXIT( 3153 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_speed_get(unit, port, 3154 PM4x10_INFO(pm_info), speed)); 3155 } else { 3156 _SOC_IF_ERR_EXIT(unimac_speed_get(unit, port, speed)); 3157 } 3158 3159 exit: 3160 SOC_FUNC_RETURN; 3161 } 3162 3163 int pm4x10_qtc_port_pfc_config_set(int unit, int port,pm_info_t pm_info, const portmod_pfc_config_t* pfc_cfg) 3164 { 3165 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3166 SOC_INIT_FUNC_DEFS; 3167 3168 PM4x10_QTC_QMOD_GET(pm_info); 3169 3170 if (!IS_QMOD) { 3171 _SOC_IF_ERR_EXIT( 3172 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_pfc_config_set(unit, port, 3173 PM4x10_INFO(pm_info), pfc_cfg)); 3174 } else { 3175 if (pfc_cfg->classes != 8) { 3176 return SOC_E_PARAM; 3177 } 3178 _SOC_IF_ERR_EXIT(unimac_pfc_config_set(unit, port, pfc_cfg)); 3179 } 3180 3181 exit: 3182 SOC_FUNC_RETURN; 3183 } 3184 3185 int pm4x10_qtc_port_pfc_config_get(int unit, int port,pm_info_t pm_info, portmod_pfc_config_t* pfc_cfg) 3186 { 3187 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3188 SOC_INIT_FUNC_DEFS; 3189 3190 PM4x10_QTC_QMOD_GET(pm_info); 3191 3192 if (!IS_QMOD) { 3193 _SOC_IF_ERR_EXIT( 3194 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_pfc_config_get(unit, port, 3195 PM4x10_INFO(pm_info), pfc_cfg)); 3196 } else { 3197 pfc_cfg->classes = 8; 3198 _SOC_IF_ERR_EXIT(unimac_pfc_config_get(unit, port, pfc_cfg)); 3199 } 3200 3201 exit: 3202 SOC_FUNC_RETURN; 3203 } 3204 3205 int pm4x10_qtc_port_pause_control_set(int unit, int port, pm_info_t pm_info, const portmod_pause_control_t* control) 3206 { 3207 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3208 SOC_INIT_FUNC_DEFS; 3209 3210 PM4x10_QTC_QMOD_GET(pm_info); 3211 3212 if (!IS_QMOD) { 3213 _SOC_IF_ERR_EXIT( 3214 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_pause_control_set(unit, port, 3215 PM4x10_INFO(pm_info), control)); 3216 } else { 3217 _SOC_IF_ERR_EXIT(unimac_pause_control_set(unit, port, control)); 3218 } 3219 3220 exit: 3221 SOC_FUNC_RETURN; 3222 } 3223 3224 int pm4x10_qtc_port_pause_control_get(int unit, int port, pm_info_t pm_info, portmod_pause_control_t* control) 3225 { 3226 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3227 SOC_INIT_FUNC_DEFS; 3228 3229 PM4x10_QTC_QMOD_GET(pm_info); 3230 3231 if (!IS_QMOD) { 3232 _SOC_IF_ERR_EXIT( 3233 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_pause_control_get(unit, port, 3234 PM4x10_INFO(pm_info), control)); 3235 } else { 3236 _SOC_IF_ERR_EXIT(unimac_pause_control_get(unit, port, control)); 3237 } 3238 3239 exit: 3240 SOC_FUNC_RETURN; 3241 } 3242 3243 int pm4x10_qtc_port_duplex_set(int unit, int port, pm_info_t pm_info,int enable) 3244 { 3245 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3246 SOC_INIT_FUNC_DEFS; 3247 3248 PM4x10_QTC_QMOD_GET(pm_info); 3249 3250 if (!IS_QMOD) { 3251 _SOC_IF_ERR_EXIT( 3252 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_duplex_set(unit, port, 3253 PM4x10_INFO(pm_info), enable)); 3254 } else { 3255 _SOC_IF_ERR_EXIT(unimac_duplex_set(unit, port, enable)); 3256 } 3257 3258 exit: 3259 SOC_FUNC_RETURN; 3260 } 3261 3262 int pm4x10_qtc_port_duplex_get(int unit, int port, pm_info_t pm_info, int* enable) 3263 { 3264 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3265 SOC_INIT_FUNC_DEFS; 3266 3267 PM4x10_QTC_QMOD_GET(pm_info); 3268 3269 if (!IS_QMOD) { 3270 _SOC_IF_ERR_EXIT( 3271 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_duplex_get(unit, port, 3272 PM4x10_INFO(pm_info), enable)); 3273 } else { 3274 _SOC_IF_ERR_EXIT(unimac_duplex_get(unit, port, enable)); 3275 } 3276 3277 exit: 3278 SOC_FUNC_RETURN; 3279 } 3280 3281 int pm4x10_qtc_port_cntmaxsize_get(int unit, int port, pm_info_t pm_info, int *val) 3282 { 3283 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3284 SOC_INIT_FUNC_DEFS; 3285 3286 PM4x10_QTC_QMOD_GET(pm_info); 3287 3288 if (!IS_QMOD) { 3289 _SOC_IF_ERR_EXIT( 3290 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_cntmaxsize_get(unit, port, 3291 PM4x10_INFO(pm_info), val)); 3292 } else { 3293 _SOC_IF_ERR_EXIT(READ_GPORT_CNTMAXSIZEr(unit, port, (uint32_t *)val)); 3294 } 3295 3296 exit: 3297 SOC_FUNC_RETURN; 3298 } 3299 3300 int pm4x10_qtc_port_cntmaxsize_set(int unit, int port, pm_info_t pm_info, int val) 3301 { 3302 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3303 SOC_INIT_FUNC_DEFS; 3304 3305 PM4x10_QTC_QMOD_GET(pm_info); 3306 3307 if (!IS_QMOD) { 3308 _SOC_IF_ERR_EXIT( 3309 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_cntmaxsize_set(unit, port, 3310 PM4x10_INFO(pm_info), val)); 3311 } else { 3312 _SOC_IF_ERR_EXIT(WRITE_GPORT_CNTMAXSIZEr(unit, port, (uint32_t)val)); 3313 } 3314 3315 exit: 3316 SOC_FUNC_RETURN; 3317 } 3318 3319 int pm4x10_qtc_port_local_fault_control_set(int unit, int port, pm_info_t pm_info, const portmod_local_fault_control_t* control) 3320 { 3321 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3322 SOC_INIT_FUNC_DEFS; 3323 3324 PM4x10_QTC_QMOD_GET(pm_info); 3325 3326 if (!IS_QMOD) { 3327 _SOC_IF_ERR_EXIT( 3328 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_local_fault_control_set(unit, port, 3329 PM4x10_INFO(pm_info), control)); 3330 } else { 3331 return (SOC_E_UNAVAIL); 3332 } 3333 3334 exit: 3335 SOC_FUNC_RETURN; 3336 } 3337 3338 int pm4x10_qtc_port_local_fault_control_get(int unit, int port, pm_info_t pm_info, portmod_local_fault_control_t* control) 3339 { 3340 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3341 SOC_INIT_FUNC_DEFS; 3342 3343 PM4x10_QTC_QMOD_GET(pm_info); 3344 3345 if (!IS_QMOD) { 3346 _SOC_IF_ERR_EXIT( 3347 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_local_fault_control_get(unit, port, 3348 PM4x10_INFO(pm_info), control)); 3349 } else { 3350 return (SOC_E_UNAVAIL); 3351 } 3352 3353 exit: 3354 SOC_FUNC_RETURN; 3355 } 3356 3357 int pm4x10_qtc_port_local_fault_status_clear(int unit, int port, pm_info_t pm_info) 3358 { 3359 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3360 SOC_INIT_FUNC_DEFS; 3361 3362 PM4x10_QTC_QMOD_GET(pm_info); 3363 3364 if (!IS_QMOD) { 3365 _SOC_IF_ERR_EXIT( 3366 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_local_fault_status_clear(unit, port, 3367 PM4x10_INFO(pm_info))); 3368 } else { 3369 return (SOC_E_UNAVAIL); 3370 } 3371 3372 exit: 3373 SOC_FUNC_RETURN; 3374 } 3375 3376 int pm4x10_qtc_port_remote_fault_control_set(int unit, int port, pm_info_t pm_info, const portmod_remote_fault_control_t* control) 3377 { 3378 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3379 SOC_INIT_FUNC_DEFS; 3380 3381 PM4x10_QTC_QMOD_GET(pm_info); 3382 3383 if (!IS_QMOD) { 3384 _SOC_IF_ERR_EXIT( 3385 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_remote_fault_control_set(unit, port, 3386 PM4x10_INFO(pm_info), control)); 3387 } else { 3388 return (SOC_E_UNAVAIL); 3389 } 3390 3391 exit: 3392 SOC_FUNC_RETURN; 3393 } 3394 3395 int pm4x10_qtc_port_remote_fault_control_get(int unit, int port, pm_info_t pm_info, portmod_remote_fault_control_t* control) 3396 { 3397 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3398 SOC_INIT_FUNC_DEFS; 3399 3400 PM4x10_QTC_QMOD_GET(pm_info); 3401 3402 if (!IS_QMOD) { 3403 _SOC_IF_ERR_EXIT( 3404 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_remote_fault_control_get(unit, port, 3405 PM4x10_INFO(pm_info), control)); 3406 } else { 3407 return (SOC_E_UNAVAIL); 3408 } 3409 3410 exit: 3411 SOC_FUNC_RETURN; 3412 } 3413 3414 int pm4x10_qtc_port_remote_fault_status_clear(int unit, int port, pm_info_t pm_info) 3415 { 3416 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3417 SOC_INIT_FUNC_DEFS; 3418 3419 PM4x10_QTC_QMOD_GET(pm_info); 3420 3421 if (!IS_QMOD) { 3422 _SOC_IF_ERR_EXIT( 3423 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_remote_fault_status_clear(unit, port, 3424 PM4x10_INFO(pm_info))); 3425 } else { 3426 return (SOC_E_UNAVAIL); 3427 } 3428 3429 exit: 3430 SOC_FUNC_RETURN; 3431 } 3432 3433 int _pm4x10_qtc_xphy_lane_attach_to_pm(int unit, pm_info_t pm_info, int iphy, int phyn, const portmod_xphy_lane_connection_t* lane_connection) 3434 { 3435 portmod_xphy_lane_connection_t *candidate_lane_conn = NULL; 3436 int lane_index = 0, phy_index = 0; 3437 int rv = 0; 3438 int nof_phys = 0; 3439 uint32 xphy_id; 3440 int lane_mask; 3441 uint32 active_lanes; 3442 SOC_INIT_FUNC_DEFS; 3443 3444 /* Validate parameters */ 3445 _SOC_IF_ERR_EXIT(portmod_xphy_lane_connection_t_validate(unit,lane_connection)); 3446 3447 if (MAX_PHYN <= phyn){ 3448 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Invalid Ext PHY location."))); 3449 } 3450 3451 /* Attaching the external phy to the phy chain of the port macro */ 3452 3453 /* find lane index corresponding to internal physical port */ 3454 lane_index = 0; 3455 PORTMOD_PBMP_ITER(PM_4x10_QTC_INFO(pm_info)->phys, phy_index) { 3456 if (phy_index == iphy) { 3457 break; 3458 } 3459 lane_index++; 3460 } 3461 3462 if (!SOC_WARM_BOOT(unit)) { 3463 rv = PM4x10_QTC_PORT_LANE_CONNECTION_DB_SET(unit, pm_info, lane_connection, phyn-1, lane_index); 3464 _SOC_IF_ERR_EXIT(rv); 3465 candidate_lane_conn = &(PM_4x10_QTC_INFO(pm_info)->lane_conn[phyn-1][lane_index]); 3466 sal_memcpy(candidate_lane_conn, lane_connection, sizeof(portmod_xphy_lane_connection_t)); 3467 3468 xphy_id = candidate_lane_conn->xphy_id; 3469 lane_mask = candidate_lane_conn->ss_lane_mask; 3470 3471 /* 3472 * Keeping track of the xphy lane usage. If the xphy lane is connected 3473 * it will set the corresponding bit to mark as lane is active. 3474 */ 3475 3476 if ((lane_mask != -1) && (xphy_id != PORTMOD_XPHY_ID_INVALID)) { 3477 _SOC_IF_ERR_EXIT(portmod_xphy_active_lane_get(unit, xphy_id, &active_lanes)); 3478 active_lanes |= lane_mask; 3479 _SOC_IF_ERR_EXIT(portmod_xphy_active_lane_set(unit,xphy_id, active_lanes)); 3480 } 3481 3482 rv = PM4x10_QTC_PORT_NUM_PHYS_GET(unit, pm_info, &nof_phys, lane_index); 3483 _SOC_IF_ERR_EXIT(rv); 3484 if (nof_phys <= phyn) { 3485 nof_phys = phyn + 1; 3486 rv = PM4x10_QTC_PORT_NUM_PHYS_SET(unit, pm_info, &nof_phys, lane_index); 3487 _SOC_IF_ERR_EXIT(rv); 3488 PM_4x10_QTC_INFO(pm_info)->nof_phys[lane_index] = phyn+1; 3489 } 3490 } 3491 3492 exit: 3493 SOC_FUNC_RETURN; 3494 } 3495 3496 int pm4x10_qtc_xphy_lane_attach_to_pm(int unit, pm_info_t pm_info, int iphy, int phyn, const portmod_xphy_lane_connection_t* lane_connection) 3497 { 3498 int phy_id_offset; 3499 SOC_INIT_FUNC_DEFS; 3500 3501 phy_id_offset = iphy - PM_4x10_QTC_INFO(pm_info)->first_phy; 3502 /* In Eth mode, there are 4 EXT PHY ids connected with the same core. */ 3503 if (phy_id_offset < PM4X10_QTC_LANES_PER_CORE) { 3504 _SOC_IF_ERR_EXIT( 3505 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_xphy_lane_attach_to_pm(unit, 3506 PM4x10_INFO(pm_info), iphy, phyn, lane_connection)); 3507 } 3508 _SOC_IF_ERR_EXIT(_pm4x10_qtc_xphy_lane_attach_to_pm(unit, pm_info, iphy, 3509 phyn, lane_connection)); 3510 3511 exit: 3512 SOC_FUNC_RETURN; 3513 } 3514 3515 int _pm4x10_qtc_xphy_lane_detach_from_pm(int unit, pm_info_t pm_info, int iphy, int phyn, portmod_xphy_lane_connection_t* lane_connection) 3516 { 3517 portmod_xphy_lane_connection_t *candidate_lane_conn = NULL; 3518 int lane_index = 0, phy_index = 0; 3519 int rv = 0; 3520 int nof_phys = 0; 3521 uint32 active_lanes; 3522 uint32 xphy_id; 3523 int lane_mask; 3524 SOC_INIT_FUNC_DEFS; 3525 3526 if (MAX_PHYN <= phyn){ 3527 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Invalid Ext PHY location."))); 3528 } 3529 3530 /* Attaching the external phy to the phy chain of the port macro */ 3531 3532 /* find lane index corresponding to internal physical port */ 3533 lane_index = 0; 3534 PORTMOD_PBMP_ITER(PM_4x10_QTC_INFO(pm_info)->phys, phy_index) { 3535 if (phy_index == iphy) { 3536 break; 3537 } 3538 lane_index++; 3539 } 3540 3541 if (!SOC_WARM_BOOT(unit)) { 3542 candidate_lane_conn = &(PM_4x10_QTC_INFO(pm_info)->lane_conn[phyn-1][lane_index]); 3543 3544 xphy_id = candidate_lane_conn->xphy_id; 3545 lane_mask = candidate_lane_conn->ss_lane_mask; 3546 3547 if ((lane_mask != -1) && (xphy_id != PORTMOD_XPHY_ID_INVALID)) { 3548 3549 /* 3550 * Keeping track of the xphy lane usage. If the xphy lane is disconnected 3551 * it will clear the corresponding bit to mark as lane is not active. 3552 * When none of the lane are active, it clear intialization status, 3553 * phy_type and probe status. When it probe again, it will re-initialize 3554 * this xphy again. 3555 */ 3556 _SOC_IF_ERR_EXIT(portmod_xphy_active_lane_get(unit, xphy_id, &active_lanes)); 3557 active_lanes &= ~lane_mask; 3558 _SOC_IF_ERR_EXIT(portmod_xphy_active_lane_set(unit, xphy_id, active_lanes)); 3559 3560 if (active_lanes == 0) { /* none of the lanes are active */ 3561 _SOC_IF_ERR_EXIT(portmod_xphy_core_probed_set(unit, xphy_id, 0)); 3562 _SOC_IF_ERR_EXIT(portmod_xphy_phy_type_set(unit,xphy_id,phymodDispatchTypeInvalid)); 3563 _SOC_IF_ERR_EXIT(portmod_xphy_is_initialized_set(unit, xphy_id,0)); 3564 } 3565 } 3566 3567 portmod_xphy_lane_connection_t_init(unit, candidate_lane_conn); 3568 rv = PM4x10_QTC_PORT_LANE_CONNECTION_DB_SET(unit, pm_info, candidate_lane_conn, phyn-1, lane_index); 3569 _SOC_IF_ERR_EXIT(rv); 3570 3571 if (phyn > 0) { 3572 nof_phys = phyn; 3573 rv = PM4x10_QTC_PORT_NUM_PHYS_SET(unit, pm_info, &nof_phys, lane_index); 3574 _SOC_IF_ERR_EXIT(rv); 3575 PM_4x10_QTC_INFO(pm_info)->nof_phys[lane_index] = nof_phys; 3576 } 3577 } 3578 3579 exit: 3580 SOC_FUNC_RETURN; 3581 } 3582 3583 int pm4x10_qtc_xphy_lane_detach_from_pm(int unit, pm_info_t pm_info, int iphy, int phyn, portmod_xphy_lane_connection_t* lane_connection) 3584 { 3585 int phy_id_offset; 3586 SOC_INIT_FUNC_DEFS; 3587 3588 phy_id_offset = iphy - PM_4x10_QTC_INFO(pm_info)->first_phy; 3589 3590 if (phy_id_offset < PM4X10_QTC_LANES_PER_CORE) { 3591 _SOC_IF_ERR_EXIT( 3592 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_xphy_lane_detach_from_pm(unit, 3593 PM4x10_INFO(pm_info), iphy, phyn, lane_connection)); 3594 } 3595 _SOC_IF_ERR_EXIT(_pm4x10_qtc_xphy_lane_detach_from_pm(unit, pm_info, iphy, 3596 phyn, lane_connection)); 3597 3598 exit: 3599 SOC_FUNC_RETURN; 3600 } 3601 3602 int pm4x10_qtc_port_diag_fifo_status_get(int unit, int port,pm_info_t pm_info, const portmod_fifo_status_t* diag_info) 3603 { 3604 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3605 SOC_INIT_FUNC_DEFS; 3606 3607 PM4x10_QTC_QMOD_GET(pm_info); 3608 3609 if (!IS_QMOD) { 3610 _SOC_IF_ERR_EXIT( 3611 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_diag_fifo_status_get(unit, port, 3612 PM4x10_INFO(pm_info), diag_info)); 3613 } else { 3614 _SOC_IF_ERR_EXIT(unimac_diag_fifo_status_get(unit, port, diag_info)); 3615 } 3616 3617 exit: 3618 SOC_FUNC_RETURN; 3619 } 3620 3621 3622 int pm4x10_qtc_port_drv_name_get(int unit, int port, pm_info_t pm_info, char* buf, int len) 3623 { 3624 strncpy(buf, "PM4X10_QTC Driver", len); 3625 return (SOC_E_NONE); 3626 } 3627 3628 int pm4x10_qtc_port_max_packet_size_set(int unit, int port, pm_info_t pm_info, int value) 3629 { 3630 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3631 SOC_INIT_FUNC_DEFS; 3632 3633 PM4x10_QTC_QMOD_GET(pm_info); 3634 3635 if (!IS_QMOD) { 3636 _SOC_IF_ERR_EXIT( 3637 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_max_packet_size_set(unit, port, 3638 PM4x10_INFO(pm_info), value)); 3639 } else { 3640 _SOC_IF_ERR_EXIT(unimac_rx_max_size_set(unit, port, value)); 3641 } 3642 3643 exit: 3644 SOC_FUNC_RETURN; 3645 } 3646 3647 int pm4x10_qtc_port_max_packet_size_get (int unit, int port, pm_info_t pm_info, int* value) 3648 { 3649 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3650 SOC_INIT_FUNC_DEFS; 3651 3652 PM4x10_QTC_QMOD_GET(pm_info); 3653 3654 if (!IS_QMOD) { 3655 _SOC_IF_ERR_EXIT( 3656 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_max_packet_size_get(unit, port, 3657 PM4x10_INFO(pm_info), value)); 3658 } else { 3659 _SOC_IF_ERR_EXIT(unimac_rx_max_size_get(unit, port, value)); 3660 } 3661 3662 exit: 3663 SOC_FUNC_RETURN; 3664 } 3665 3666 3667 int pm4x10_qtc_port_rx_mac_enable_set(int unit, int port, pm_info_t pm_info, int enable) 3668 { 3669 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3670 SOC_INIT_FUNC_DEFS; 3671 3672 PM4x10_QTC_QMOD_GET(pm_info); 3673 3674 if (!IS_QMOD) { 3675 _SOC_IF_ERR_EXIT( 3676 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_rx_mac_enable_set(unit, port, 3677 PM4x10_INFO(pm_info), enable)); 3678 } else { 3679 _SOC_IF_ERR_EXIT(unimac_rx_enable_set(unit, port, enable)); 3680 } 3681 3682 exit: 3683 SOC_FUNC_RETURN; 3684 3685 } 3686 3687 int pm4x10_qtc_port_rx_mac_enable_get(int unit, int port, pm_info_t pm_info, int* enable) 3688 { 3689 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3690 SOC_INIT_FUNC_DEFS; 3691 3692 PM4x10_QTC_QMOD_GET(pm_info); 3693 3694 if (!IS_QMOD) { 3695 _SOC_IF_ERR_EXIT( 3696 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_rx_mac_enable_get(unit, port, 3697 PM4x10_INFO(pm_info), enable)); 3698 } else { 3699 _SOC_IF_ERR_EXIT(unimac_rx_enable_get(unit, port, enable)); 3700 } 3701 3702 exit: 3703 SOC_FUNC_RETURN; 3704 3705 } 3706 3707 int pm4x10_qtc_port_vlan_tag_set(int unit, int port, pm_info_t pm_info,const portmod_vlan_tag_t* vlan_tag) 3708 { 3709 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3710 SOC_INIT_FUNC_DEFS; 3711 3712 PM4x10_QTC_QMOD_GET(pm_info); 3713 3714 if (!IS_QMOD) { 3715 _SOC_IF_ERR_EXIT( 3716 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_vlan_tag_set(unit, port, 3717 PM4x10_INFO(pm_info), vlan_tag)); 3718 } else { 3719 _SOC_IF_ERR_EXIT(unimac_rx_vlan_tag_set(unit, port, vlan_tag->outer_vlan_tag, vlan_tag->inner_vlan_tag)); 3720 } 3721 3722 exit: 3723 SOC_FUNC_RETURN; 3724 } 3725 3726 3727 int pm4x10_qtc_port_vlan_tag_get(int unit, int port, pm_info_t pm_info, portmod_vlan_tag_t* vlan_tag) 3728 { 3729 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3730 SOC_INIT_FUNC_DEFS; 3731 3732 PM4x10_QTC_QMOD_GET(pm_info); 3733 3734 if (!IS_QMOD) { 3735 _SOC_IF_ERR_EXIT( 3736 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_vlan_tag_get(unit, port, 3737 PM4x10_INFO(pm_info), vlan_tag)); 3738 } else { 3739 _SOC_IF_ERR_EXIT(unimac_rx_vlan_tag_get(unit, port, (int*)&vlan_tag->outer_vlan_tag, (int*)&vlan_tag->inner_vlan_tag)); 3740 } 3741 3742 exit: 3743 SOC_FUNC_RETURN; 3744 } 3745 3746 int pm4x10_qtc_port_pfc_control_set(int unit, int port, pm_info_t pm_info, const portmod_pfc_control_t* control) 3747 { 3748 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3749 SOC_INIT_FUNC_DEFS; 3750 3751 PM4x10_QTC_QMOD_GET(pm_info); 3752 3753 if (!IS_QMOD) { 3754 _SOC_IF_ERR_EXIT( 3755 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_pfc_control_set(unit, port, 3756 PM4x10_INFO(pm_info), control)); 3757 } else { 3758 _SOC_IF_ERR_EXIT(unimac_pfc_control_set(unit, port, control)); 3759 } 3760 3761 exit: 3762 SOC_FUNC_RETURN; 3763 } 3764 3765 int pm4x10_qtc_port_pfc_control_get(int unit, int port, pm_info_t pm_info, portmod_pfc_control_t* control) 3766 { 3767 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3768 SOC_INIT_FUNC_DEFS; 3769 3770 PM4x10_QTC_QMOD_GET(pm_info); 3771 3772 if (!IS_QMOD) { 3773 _SOC_IF_ERR_EXIT( 3774 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_pfc_control_get(unit, port, 3775 PM4x10_INFO(pm_info), control)); 3776 } else { 3777 _SOC_IF_ERR_EXIT(unimac_pfc_control_get(unit, port, control)); 3778 } 3779 3780 exit: 3781 SOC_FUNC_RETURN; 3782 } 3783 3784 int pm4x10_qtc_port_llfc_control_set(int unit, int port, pm_info_t pm_info, const portmod_llfc_control_t* control) 3785 { 3786 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3787 SOC_INIT_FUNC_DEFS; 3788 3789 PM4x10_QTC_QMOD_GET(pm_info); 3790 3791 if (!IS_QMOD) { 3792 _SOC_IF_ERR_EXIT( 3793 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_llfc_control_set(unit, port, 3794 PM4x10_INFO(pm_info), control)); 3795 } else { 3796 return (SOC_E_UNAVAIL); 3797 } 3798 3799 exit: 3800 SOC_FUNC_RETURN; 3801 } 3802 3803 int pm4x10_qtc_port_llfc_control_get(int unit, int port, pm_info_t pm_info, portmod_llfc_control_t* control) 3804 { 3805 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3806 SOC_INIT_FUNC_DEFS; 3807 3808 PM4x10_QTC_QMOD_GET(pm_info); 3809 3810 if (!IS_QMOD) { 3811 _SOC_IF_ERR_EXIT( 3812 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_llfc_control_get(unit, port, 3813 PM4x10_INFO(pm_info), control)); 3814 } else { 3815 return (SOC_E_UNAVAIL); 3816 } 3817 3818 exit: 3819 SOC_FUNC_RETURN; 3820 } 3821 3822 int _pm4x10_qtc_port_link_get(int unit, int port, pm_info_t pm_info, int flags, int* link) 3823 { 3824 phymod_phy_access_t phy_access[1+MAX_PHYN]; 3825 int nof_phys; 3826 SOC_INIT_FUNC_DEFS; 3827 3828 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, phy_access ,(1+MAX_PHYN), &nof_phys)); 3829 3830 _SOC_IF_ERR_EXIT(portmod_port_phychain_link_status_get(unit, port, phy_access, nof_phys, flags, (uint32_t*) link)); 3831 3832 exit: 3833 SOC_FUNC_RETURN; 3834 } 3835 3836 int pm4x10_qtc_port_link_get(int unit, int port, pm_info_t pm_info, int flags, int* link) 3837 { 3838 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3839 SOC_INIT_FUNC_DEFS; 3840 3841 PM4x10_QTC_QMOD_GET(pm_info); 3842 3843 if (!IS_QMOD) { 3844 _SOC_IF_ERR_EXIT( 3845 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_link_get(unit, port, 3846 PM4x10_INFO(pm_info), flags, link)); 3847 } else { 3848 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_link_get(unit, port, pm_info, flags, link)); 3849 } 3850 3851 exit: 3852 SOC_FUNC_RETURN; 3853 } 3854 3855 int pm4x10_qtc_port_tx_mac_sa_set(int unit, int port, pm_info_t pm_info, sal_mac_addr_t mac_addr) 3856 { 3857 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3858 SOC_INIT_FUNC_DEFS; 3859 3860 PM4x10_QTC_QMOD_GET(pm_info); 3861 3862 if (!IS_QMOD) { 3863 _SOC_IF_ERR_EXIT( 3864 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_tx_mac_sa_set(unit, port, 3865 PM4x10_INFO(pm_info), mac_addr)); 3866 } else { 3867 _SOC_IF_ERR_EXIT(unimac_mac_sa_set(unit, port, mac_addr)); 3868 } 3869 3870 exit: 3871 SOC_FUNC_RETURN; 3872 } 3873 3874 3875 int pm4x10_qtc_port_tx_mac_sa_get(int unit, int port, pm_info_t pm_info, sal_mac_addr_t mac_addr) 3876 { 3877 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3878 SOC_INIT_FUNC_DEFS; 3879 3880 PM4x10_QTC_QMOD_GET(pm_info); 3881 3882 if (!IS_QMOD) { 3883 _SOC_IF_ERR_EXIT( 3884 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_tx_mac_sa_get(unit, port, 3885 PM4x10_INFO(pm_info), mac_addr)); 3886 } else { 3887 _SOC_IF_ERR_EXIT(unimac_mac_sa_get(unit, port, mac_addr)); 3888 } 3889 3890 exit: 3891 SOC_FUNC_RETURN; 3892 } 3893 3894 int pm4x10_qtc_port_rx_mac_sa_set(int unit, int port, pm_info_t pm_info, sal_mac_addr_t mac_addr) 3895 { 3896 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3897 SOC_INIT_FUNC_DEFS; 3898 3899 PM4x10_QTC_QMOD_GET(pm_info); 3900 3901 if (!IS_QMOD) { 3902 _SOC_IF_ERR_EXIT( 3903 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_rx_mac_sa_set(unit, port, 3904 PM4x10_INFO(pm_info), mac_addr)); 3905 } else { 3906 _SOC_IF_ERR_EXIT(unimac_mac_sa_set(unit, port, mac_addr)); 3907 } 3908 3909 exit: 3910 SOC_FUNC_RETURN; 3911 } 3912 3913 3914 int pm4x10_qtc_port_rx_mac_sa_get(int unit, int port, pm_info_t pm_info, sal_mac_addr_t mac_addr) 3915 { 3916 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3917 SOC_INIT_FUNC_DEFS; 3918 3919 PM4x10_QTC_QMOD_GET(pm_info); 3920 3921 if (!IS_QMOD) { 3922 _SOC_IF_ERR_EXIT( 3923 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_rx_mac_sa_get(unit, port, 3924 PM4x10_INFO(pm_info), mac_addr)); 3925 } else { 3926 _SOC_IF_ERR_EXIT(unimac_mac_sa_get(unit, port, mac_addr)); 3927 } 3928 3929 exit: 3930 SOC_FUNC_RETURN; 3931 } 3932 3933 int pm4x10_qtc_port_pad_size_set(int unit, int port, pm_info_t pm_info, int value) 3934 { 3935 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3936 SOC_INIT_FUNC_DEFS; 3937 3938 PM4x10_QTC_QMOD_GET(pm_info); 3939 3940 if (!IS_QMOD) { 3941 _SOC_IF_ERR_EXIT( 3942 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_pad_size_set(unit, port, 3943 PM4x10_INFO(pm_info), value)); 3944 } else { 3945 /*Unimac tx padding is always enabled*/ 3946 } 3947 3948 exit: 3949 SOC_FUNC_RETURN; 3950 } 3951 3952 int pm4x10_qtc_port_pad_size_get(int unit, int port, pm_info_t pm_info, int* value) 3953 { 3954 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 3955 SOC_INIT_FUNC_DEFS; 3956 3957 PM4x10_QTC_QMOD_GET(pm_info); 3958 3959 if (!IS_QMOD) { 3960 _SOC_IF_ERR_EXIT( 3961 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_pad_size_get(unit, port, 3962 PM4x10_INFO(pm_info), value)); 3963 } else { 3964 /*Unimac tx padding is always enabled and min frame size is 64*/ 3965 *value = 64; 3966 } 3967 3968 exit: 3969 SOC_FUNC_RETURN; 3970 } 3971 3972 int _pm4x10_qtc_port_update(int unit, int port, pm_info_t pm_info, const portmod_port_update_control_t* update_control) 3973 { 3974 int link; 3975 phymod_phy_access_t phy_access[1+MAX_PHYN]; 3976 int nof_phys; 3977 uint32_t serdes_link_status=0; 3978 phymod_phy_rx_lane_control_t rx_control; 3979 SOC_INIT_FUNC_DEFS; 3980 3981 _SOC_IF_ERR_EXIT 3982 (portmod_port_chain_phy_access_get(unit, port, pm_info, 3983 phy_access ,(1+MAX_PHYN), 3984 &nof_phys)); 3985 3986 if(update_control->link_status == -1) { 3987 _SOC_IF_ERR_EXIT(pm4x10_qtc_port_link_get(unit, port, pm_info, PORTMOD_INIT_F_EXTERNAL_MOST_ONLY, &link)); 3988 } else { 3989 link = update_control->link_status; 3990 } 3991 3992 /* Following code applies to the phy 54290 */ 3993 if (PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK_GET(update_control)){ 3994 if (nof_phys > 1){ 3995 _SOC_IF_ERR_EXIT 3996 (phymod_phy_link_status_get(&phy_access[0],&serdes_link_status)); 3997 3998 if(link) { 3999 _SOC_IF_ERR_EXIT 4000 (phymod_phy_rx_lane_control_get(&phy_access[0],&rx_control)); 4001 if(rx_control == phymodRxSquelchOn){ 4002 phymod_phy_rx_lane_control_set(&phy_access[0], 4003 phymodRxSquelchOff); 4004 } 4005 } else { 4006 /* if external phy and link is down, internal serdes link is up, 4007 force internal SerDes link to be down. */ 4008 if(serdes_link_status){ 4009 phymod_phy_rx_lane_control_set(&phy_access[0], 4010 phymodRxSquelchOn); 4011 phymod_phy_rx_lane_control_set(&phy_access[0], 4012 phymodRxSquelchOff); 4013 } 4014 } 4015 } 4016 /* 4017 * PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK is set for XGS devices. Since XGS devices 4018 * already update their MAC registers elsewhere, there is an early return below to 4019 * avoid redundant works. 4020 */ 4021 return (SOC_E_NONE); 4022 } 4023 4024 exit: 4025 SOC_FUNC_RETURN; 4026 } 4027 4028 int pm4x10_qtc_port_update(int unit, int port, pm_info_t pm_info, 4029 const portmod_port_update_control_t* update_control) 4030 { 4031 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4032 SOC_INIT_FUNC_DEFS; 4033 4034 PM4x10_QTC_QMOD_GET(pm_info); 4035 4036 if (!IS_QMOD) { 4037 _SOC_IF_ERR_EXIT( 4038 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_update(unit, port, 4039 PM4x10_INFO(pm_info), update_control)); 4040 } else { 4041 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_update(unit, port, pm_info, update_control)); 4042 } 4043 4044 exit: 4045 SOC_FUNC_RETURN; 4046 } 4047 4048 int pm4x10_qtc_port_nof_lanes_get(int unit, int port, pm_info_t pm_info, int *nof_lanes) 4049 { 4050 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4051 SOC_INIT_FUNC_DEFS; 4052 4053 PM4x10_QTC_QMOD_GET(pm_info); 4054 4055 if (!IS_QMOD) { 4056 _SOC_IF_ERR_EXIT( 4057 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_nof_lanes_get(unit, port, 4058 PM4x10_INFO(pm_info), nof_lanes)); 4059 } else { 4060 /*QSGMII ports always occupy only one lane*/ 4061 *nof_lanes = 1; 4062 } 4063 4064 exit: 4065 SOC_FUNC_RETURN; 4066 } 4067 4068 int _pm4x10_qtc_port_diag_ctrl(int unit, soc_port_t port, pm_info_t pm_info, 4069 uint32 inst, int op_type, int op_cmd, const void *arg) 4070 { 4071 phymod_phy_access_t phy_access[1+MAX_PHYN]; 4072 phymod_tx_t ln_txparam[PM4X10_QTC_LANES_PER_CORE]; 4073 int nof_phys, i; 4074 uint32 lane_map; 4075 portmod_access_get_params_t params; 4076 4077 SOC_IF_ERROR_RETURN(portmod_access_get_params_t_init(unit, ¶ms)); 4078 4079 for (i = 0; i < PM4X10_QTC_LANES_PER_CORE; i++) { 4080 SOC_IF_ERROR_RETURN(phymod_tx_t_init(&ln_txparam[i])); 4081 } 4082 4083 if (PHY_DIAG_INST_DEV(inst) == PHY_DIAG_DEV_INT) { 4084 params.phyn = 0; 4085 } else { 4086 /* most external PHY_DIAG_DEV_DFLT and PHY_DIAG_DEV_EXT */ 4087 params.phyn = -1; 4088 } 4089 4090 if (PHY_DIAG_INST_INTF(inst) == PHY_DIAG_INTF_SYS) { 4091 params.sys_side = PORTMOD_SIDE_SYSTEM; 4092 } else { /* line side is default */ 4093 params.sys_side = PORTMOD_SIDE_LINE; 4094 } 4095 4096 params.apply_lane_mask = 1; 4097 4098 SOC_IF_ERROR_RETURN(pm4x10_qtc_port_phy_lane_access_get(unit, port, pm_info, 4099 ¶ms, 1, phy_access, &nof_phys, NULL)); 4100 4101 lane_map = phy_access[0].access.lane_mask; 4102 4103 switch (op_cmd) { 4104 case PHY_DIAG_CTRL_DSC: 4105 LOG_INFO(BSL_LS_SOC_PHY, 4106 (BSL_META_U(unit, 4107 "pm4x10_qtc_port_diag_ctrl: " 4108 "u=%d p=%d PHY_DIAG_CTRL_DSC 0x%x\n"), 4109 unit, port, PHY_DIAG_CTRL_DSC)); 4110 4111 SOC_IF_ERROR_RETURN 4112 (portmod_port_phychain_pmd_info_dump(unit, phy_access, nof_phys, 4113 (void*)arg)); 4114 break; 4115 4116 case PHY_DIAG_CTRL_PCS: 4117 LOG_INFO(BSL_LS_SOC_PHY, 4118 (BSL_META_U(unit, 4119 "pm4x10_qtc_port_diag_ctrl: " 4120 "u=%d p=%d PHY_DIAG_CTRL_PCS 0x%x\n"), 4121 unit, port, PHY_DIAG_CTRL_PCS)); 4122 4123 SOC_IF_ERROR_RETURN 4124 (portmod_port_phychain_pcs_info_dump(unit, phy_access, nof_phys, 4125 (void*)arg)); 4126 break; 4127 4128 default: 4129 if(op_type == PHY_DIAG_CTRL_SET) { 4130 LOG_INFO(BSL_LS_SOC_PHY, 4131 (BSL_META_U(unit, 4132 "pm4x10_qtc_port_diag_ctrl: " 4133 "u=%d p=%d PHY_DIAG_CTRL_SET 0x%x\n"), 4134 unit, port, PHY_DIAG_CTRL_SET)); 4135 if (!SAL_BOOT_SIMULATION) { 4136 if( !(phy_access->access.lane_mask == 0)){ 4137 SOC_IF_ERROR_RETURN(portmod_pm_phy_control_set(phy_access, nof_phys, op_cmd, ln_txparam, lane_map, PTR_TO_INT(arg))); 4138 } 4139 } 4140 } else if(op_type == PHY_DIAG_CTRL_GET) { 4141 LOG_INFO(BSL_LS_SOC_PHY, 4142 (BSL_META_U(unit, 4143 "pm4x10_qtc_port_diag_ctrl: " 4144 "u=%d p=%d PHY_DIAG_CTRL_GET 0x%x\n"), 4145 unit, port, PHY_DIAG_CTRL_GET)); 4146 if (!SAL_BOOT_SIMULATION) { 4147 if( !(phy_access->access.lane_mask == 0)){ 4148 SOC_IF_ERROR_RETURN(portmod_pm_phy_control_get(phy_access,nof_phys,op_cmd, ln_txparam, lane_map, (uint32 *)arg)); 4149 } else { 4150 *(uint32 *)arg = 0; 4151 } 4152 } 4153 } else { 4154 return (SOC_E_UNAVAIL); 4155 } 4156 break ; 4157 } 4158 return (SOC_E_NONE); 4159 } 4160 4161 int pm4x10_qtc_port_diag_ctrl(int unit, soc_port_t port, pm_info_t pm_info, 4162 uint32 inst, int op_type, int op_cmd, const void *arg) 4163 { 4164 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4165 SOC_INIT_FUNC_DEFS; 4166 4167 PM4x10_QTC_QMOD_GET(pm_info); 4168 4169 if (!IS_QMOD) { 4170 _SOC_IF_ERR_EXIT( 4171 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_diag_ctrl(unit, port, 4172 PM4x10_INFO(pm_info), inst, op_type, op_cmd, arg)); 4173 } else { 4174 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_diag_ctrl(unit, port, pm_info, inst, 4175 op_type, op_cmd, arg)); 4176 } 4177 4178 exit: 4179 SOC_FUNC_RETURN; 4180 } 4181 4182 int _pm4x10_qtc_port_autoneg_status_get(int unit, int port, pm_info_t pm_info, 4183 phymod_autoneg_status_t* an_status) 4184 { 4185 phymod_phy_access_t phy_access[1+MAX_PHYN]; 4186 int nof_phys; 4187 SOC_INIT_FUNC_DEFS; 4188 4189 _SOC_IF_ERR_EXIT 4190 (portmod_port_chain_phy_access_get(unit, port, pm_info, 4191 phy_access ,(1+MAX_PHYN), 4192 &nof_phys)); 4193 if(nof_phys == 0) { 4194 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, (_SOC_MSG("Autoneg isn't supported"))); 4195 } 4196 4197 _SOC_IF_ERR_EXIT 4198 (portmod_port_phychain_autoneg_status_get(unit, port, phy_access, nof_phys, an_status)); 4199 4200 exit: 4201 SOC_FUNC_RETURN; 4202 } 4203 4204 int pm4x10_qtc_port_autoneg_status_get (int unit, int port, pm_info_t pm_info, 4205 phymod_autoneg_status_t* an_status) 4206 { 4207 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4208 SOC_INIT_FUNC_DEFS; 4209 4210 PM4x10_QTC_QMOD_GET(pm_info); 4211 4212 if (!IS_QMOD) { 4213 _SOC_IF_ERR_EXIT( 4214 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_autoneg_status_get(unit, port, 4215 PM4x10_INFO(pm_info), an_status)); 4216 } else { 4217 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_autoneg_status_get(unit, port, pm_info, an_status)); 4218 } 4219 4220 exit: 4221 SOC_FUNC_RETURN; 4222 } 4223 4224 int _pm4x10_qtc_port_phy_link_up_event(int unit, int port, pm_info_t pm_info) 4225 { 4226 phymod_phy_access_t phy_access[1+MAX_PHYN]; 4227 int nof_phys; 4228 4229 SOC_INIT_FUNC_DEFS; 4230 4231 _SOC_IF_ERR_EXIT 4232 (portmod_port_chain_phy_access_get(unit, port, pm_info, 4233 phy_access ,(1+MAX_PHYN), 4234 &nof_phys)); 4235 _SOC_IF_ERR_EXIT 4236 (portmod_port_phychain_phy_link_up_event(unit, port, phy_access, nof_phys)); 4237 exit: 4238 SOC_FUNC_RETURN; 4239 } 4240 4241 int pm4x10_qtc_port_phy_link_up_event(int unit, int port, pm_info_t pm_info) 4242 { 4243 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4244 SOC_INIT_FUNC_DEFS; 4245 4246 PM4x10_QTC_QMOD_GET(pm_info); 4247 4248 if (!IS_QMOD) { 4249 _SOC_IF_ERR_EXIT( 4250 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_link_up_event(unit, port, 4251 PM4x10_INFO(pm_info))); 4252 } else { 4253 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_phy_link_up_event(unit, port, pm_info)); 4254 } 4255 4256 exit: 4257 SOC_FUNC_RETURN; 4258 } 4259 4260 int _pm4x10_qtc_port_phy_link_down_event(int unit, int port, pm_info_t pm_info) 4261 { 4262 phymod_phy_access_t phy_access[1+MAX_PHYN]; 4263 int nof_phys; 4264 4265 SOC_INIT_FUNC_DEFS; 4266 4267 _SOC_IF_ERR_EXIT 4268 (portmod_port_chain_phy_access_get(unit, port, pm_info, 4269 phy_access ,(1+MAX_PHYN), 4270 &nof_phys)); 4271 _SOC_IF_ERR_EXIT 4272 (portmod_port_phychain_phy_link_down_event(unit, port, phy_access, nof_phys)); 4273 exit: 4274 SOC_FUNC_RETURN; 4275 } 4276 4277 int pm4x10_qtc_port_phy_link_down_event(int unit, int port, pm_info_t pm_info) 4278 { 4279 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4280 SOC_INIT_FUNC_DEFS; 4281 4282 PM4x10_QTC_QMOD_GET(pm_info); 4283 4284 if (!IS_QMOD) { 4285 _SOC_IF_ERR_EXIT( 4286 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_link_down_event(unit, port, 4287 PM4x10_INFO(pm_info))); 4288 } else { 4289 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_phy_link_down_event(unit, port, pm_info)); 4290 } 4291 4292 exit: 4293 SOC_FUNC_RETURN; 4294 } 4295 4296 int pm4x10_qtc_port_mode_set(int unit, int port, pm_info_t pm_info, const portmod_port_mode_info_t* mode) 4297 { 4298 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4299 SOC_INIT_FUNC_DEFS; 4300 4301 PM4x10_QTC_QMOD_GET(pm_info); 4302 4303 if (!IS_QMOD) { 4304 _SOC_IF_ERR_EXIT( 4305 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mode_set(unit, port, 4306 PM4x10_INFO(pm_info), mode)); 4307 } else { 4308 return (SOC_E_UNAVAIL); 4309 } 4310 4311 exit: 4312 SOC_FUNC_RETURN; 4313 } 4314 4315 int _pm4x10_qtc_port_mode_get(int unit, int port, pm_info_t pm_info, portmod_port_mode_info_t* mode) 4316 { 4317 int port_index; 4318 uint32 bitmap; 4319 SOC_INIT_FUNC_DEFS; 4320 4321 _SOC_IF_ERR_EXIT( 4322 _pm4x10_qtc_port_index_get (unit, port, pm_info, &port_index, &bitmap)); 4323 mode->port_index = port_index; 4324 mode->cur_mode = portmodPortModeQuad; 4325 mode->lanes = 1; 4326 4327 exit: 4328 SOC_FUNC_RETURN; 4329 } 4330 4331 int pm4x10_qtc_port_mode_get(int unit, int port, pm_info_t pm_info, portmod_port_mode_info_t* mode) 4332 { 4333 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4334 SOC_INIT_FUNC_DEFS; 4335 4336 PM4x10_QTC_QMOD_GET(pm_info); 4337 4338 if (!IS_QMOD) { 4339 _SOC_IF_ERR_EXIT( 4340 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mode_get(unit, port, 4341 PM4x10_INFO(pm_info), mode)); 4342 } else { 4343 _SOC_IF_ERR_EXIT( 4344 _pm4x10_qtc_port_mode_get(unit, port, pm_info, mode)); 4345 } 4346 4347 exit: 4348 SOC_FUNC_RETURN; 4349 } 4350 4351 int pm4x10_qtc_port_mac_reset_check(int unit, int port, pm_info_t pm_info, int enable, int* reset) 4352 { 4353 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4354 SOC_INIT_FUNC_DEFS; 4355 4356 PM4x10_QTC_QMOD_GET(pm_info); 4357 4358 if (!IS_QMOD) { 4359 _SOC_IF_ERR_EXIT( 4360 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mac_reset_check(unit, port, 4361 PM4x10_INFO(pm_info), enable, reset)); 4362 } else { 4363 _SOC_IF_ERR_EXIT(unimac_reset_check(unit, port, enable, reset)); 4364 } 4365 4366 exit: 4367 SOC_FUNC_RETURN; 4368 } 4369 4370 int _pm4x10_qtc_port_check_legacy_phy(int unit, int port, pm_info_t pm_info, int *legacy_phy) 4371 { 4372 phymod_phy_access_t phy_access[1+MAX_PHYN]; 4373 int nof_phys, xphy_id, is_legacy_phy; 4374 int port_index; 4375 uint32 bitmap; 4376 4377 SOC_INIT_FUNC_DEFS; 4378 4379 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_index_get (unit, port, pm_info, &port_index, 4380 &bitmap)); 4381 4382 *legacy_phy = 0; 4383 4384 if (PM_4x10_QTC_INFO(pm_info)->nof_phys[port_index] == 0) { 4385 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, 4386 (_SOC_MSG("phy reset is not supported"))); 4387 } 4388 4389 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, 4390 phy_access ,(1+MAX_PHYN), 4391 &nof_phys)); 4392 while (nof_phys > 1) { 4393 nof_phys--; 4394 xphy_id = phy_access[nof_phys].access.addr; 4395 _SOC_IF_ERR_EXIT(portmod_xphy_is_legacy_phy_get(unit, xphy_id, &is_legacy_phy)); 4396 if (is_legacy_phy) { 4397 *legacy_phy = 1; 4398 break; 4399 } 4400 } 4401 4402 exit: 4403 SOC_FUNC_RETURN; 4404 } 4405 4406 int pm4x10_qtc_port_check_legacy_phy(int unit, int port, pm_info_t pm_info, int* legacy_phy) 4407 { 4408 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4409 SOC_INIT_FUNC_DEFS; 4410 4411 PM4x10_QTC_QMOD_GET(pm_info); 4412 4413 if (!IS_QMOD) { 4414 _SOC_IF_ERR_EXIT( 4415 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_check_legacy_phy(unit, port, 4416 PM4x10_INFO(pm_info), legacy_phy)); 4417 } else { 4418 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_check_legacy_phy(unit, port, pm_info, legacy_phy)); 4419 } 4420 4421 exit: 4422 SOC_FUNC_RETURN; 4423 } 4424 4425 int pm4x10_qtc_port_discard_set(int unit, int port, pm_info_t pm_info, int discard) 4426 { 4427 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4428 SOC_INIT_FUNC_DEFS; 4429 4430 PM4x10_QTC_QMOD_GET(pm_info); 4431 4432 if (!IS_QMOD) { 4433 _SOC_IF_ERR_EXIT( 4434 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_discard_set(unit, port, 4435 PM4x10_INFO(pm_info), discard)); 4436 } else { 4437 return (SOC_E_UNAVAIL); 4438 } 4439 4440 exit: 4441 SOC_FUNC_RETURN; 4442 } 4443 4444 int pm4x10_qtc_port_core_num_get(int unit, int port, pm_info_t pm_info, int* core_num) 4445 { 4446 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4447 SOC_INIT_FUNC_DEFS; 4448 4449 PM4x10_QTC_QMOD_GET(pm_info); 4450 4451 if (!IS_QMOD) { 4452 _SOC_IF_ERR_EXIT( 4453 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_core_num_get(unit, port, 4454 PM4x10_INFO(pm_info), core_num)); 4455 } else { 4456 *core_num = PM_4x10_QTC_INFO(pm_info)->core_num; 4457 } 4458 4459 exit: 4460 SOC_FUNC_RETURN; 4461 } 4462 4463 int pm4x10_qtc_port_ref_clk_get(int unit, int port, pm_info_t pm_info, int* ref_clk) 4464 { 4465 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4466 SOC_INIT_FUNC_DEFS; 4467 4468 PM4x10_QTC_QMOD_GET(pm_info); 4469 4470 if (!IS_QMOD) { 4471 _SOC_IF_ERR_EXIT( 4472 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_ref_clk_get(unit, port, 4473 PM4x10_INFO(pm_info), ref_clk)); 4474 } else { 4475 *ref_clk = PM_4x10_QTC_INFO(pm_info)->ref_clk; 4476 } 4477 4478 exit: 4479 SOC_FUNC_RETURN; 4480 } 4481 4482 int pm4x10_qtc_port_soft_reset_set(int unit, int port, pm_info_t pm_info, int idx, int val, int flags) 4483 { 4484 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4485 SOC_INIT_FUNC_DEFS; 4486 4487 PM4x10_QTC_QMOD_GET(pm_info); 4488 4489 if (!IS_QMOD) { 4490 _SOC_IF_ERR_EXIT( 4491 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_soft_reset_set(unit, port, 4492 PM4x10_INFO(pm_info), idx, val, flags)); 4493 } else { 4494 _SOC_IF_ERR_EXIT(unimac_soft_reset_set(unit, port, val)); 4495 } 4496 4497 exit: 4498 SOC_FUNC_RETURN; 4499 } 4500 4501 int pm4x10_qtc_port_drain_cells_rx_enable(int unit, int port, pm_info_t pm_info, int enable) 4502 { 4503 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4504 SOC_INIT_FUNC_DEFS; 4505 4506 PM4x10_QTC_QMOD_GET(pm_info); 4507 4508 if (!IS_QMOD) { 4509 _SOC_IF_ERR_EXIT( 4510 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_drain_cells_rx_enable(unit, port, 4511 PM4x10_INFO(pm_info), enable)); 4512 } else { 4513 int flags = UNIMAC_ENABLE_SET_FLAGS_RX_EN | UNIMAC_ENABLE_SET_FLAGS_TX_EN; 4514 4515 _SOC_IF_ERR_EXIT(unimac_enable_set(unit, port, flags, enable)); 4516 } 4517 4518 exit: 4519 SOC_FUNC_RETURN; 4520 } 4521 4522 int pm4x10_qtc_port_tx_down(int unit, int port, pm_info_t pm_info) 4523 { 4524 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4525 SOC_INIT_FUNC_DEFS; 4526 4527 PM4x10_QTC_QMOD_GET(pm_info); 4528 4529 if (!IS_QMOD) { 4530 _SOC_IF_ERR_EXIT( 4531 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_tx_down(unit, port, 4532 PM4x10_INFO(pm_info))); 4533 } else { 4534 int flags = UNIMAC_ENABLE_SET_FLAGS_TX_EN; 4535 4536 _SOC_IF_ERR_EXIT(unimac_enable_set(unit, port, flags, 0)); 4537 } 4538 4539 exit: 4540 SOC_FUNC_RETURN; 4541 } 4542 4543 int 4544 pm4x10_qtc_port_txfifo_cell_cnt_get(int unit, int port, pm_info_t pm_info, uint32* cnt) 4545 { 4546 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4547 SOC_INIT_FUNC_DEFS; 4548 4549 PM4x10_QTC_QMOD_GET(pm_info); 4550 4551 if (!IS_QMOD) { 4552 _SOC_IF_ERR_EXIT( 4553 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_txfifo_cell_cnt_get(unit, port, 4554 PM4x10_INFO(pm_info), cnt)); 4555 } else { 4556 *cnt = 0; 4557 } 4558 4559 exit: 4560 SOC_FUNC_RETURN; 4561 } 4562 4563 int 4564 pm4x10_qtc_port_drain_cell_get(int unit, int port, pm_info_t pm_info, portmod_drain_cells_t* drain_cells) 4565 { 4566 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4567 SOC_INIT_FUNC_DEFS; 4568 4569 PM4x10_QTC_QMOD_GET(pm_info); 4570 4571 if (!IS_QMOD) { 4572 _SOC_IF_ERR_EXIT( 4573 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_drain_cell_get(unit, port, 4574 PM4x10_INFO(pm_info), drain_cells)); 4575 } else { 4576 _SOC_IF_ERR_EXIT(unimac_drain_cell_get(unit, port, drain_cells)); 4577 } 4578 4579 exit: 4580 SOC_FUNC_RETURN; 4581 } 4582 4583 int 4584 pm4x10_qtc_port_drain_cell_start(int unit, int port, pm_info_t pm_info) 4585 { 4586 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4587 SOC_INIT_FUNC_DEFS; 4588 4589 PM4x10_QTC_QMOD_GET(pm_info); 4590 4591 if (!IS_QMOD) { 4592 _SOC_IF_ERR_EXIT( 4593 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_drain_cell_start(unit, port, 4594 PM4x10_INFO(pm_info))); 4595 } else { 4596 return (SOC_E_UNAVAIL); 4597 } 4598 4599 exit: 4600 SOC_FUNC_RETURN; 4601 } 4602 4603 int 4604 pm4x10_qtc_port_drain_cell_stop(int unit, int port, pm_info_t pm_info, const portmod_drain_cells_t* drain_cells) 4605 { 4606 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4607 SOC_INIT_FUNC_DEFS; 4608 4609 PM4x10_QTC_QMOD_GET(pm_info); 4610 4611 if (!IS_QMOD) { 4612 _SOC_IF_ERR_EXIT( 4613 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_drain_cell_stop(unit, port, 4614 PM4x10_INFO(pm_info), drain_cells)); 4615 } else { 4616 return (SOC_E_UNAVAIL); 4617 } 4618 4619 exit: 4620 SOC_FUNC_RETURN; 4621 } 4622 4623 int pm4x10_qtc_port_lag_failover_status_toggle(int unit, int port, pm_info_t pm_info) 4624 { 4625 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4626 SOC_INIT_FUNC_DEFS; 4627 4628 PM4x10_QTC_QMOD_GET(pm_info); 4629 4630 if (!IS_QMOD) { 4631 _SOC_IF_ERR_EXIT( 4632 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_lag_failover_status_toggle(unit, port, 4633 PM4x10_INFO(pm_info))); 4634 } else { 4635 return (SOC_E_UNAVAIL); 4636 } 4637 4638 exit: 4639 SOC_FUNC_RETURN; 4640 } 4641 4642 int pm4x10_qtc_port_flow_control_set (int unit, int port, pm_info_t pm_info, 4643 int merge_mode_en, int parallel_fc_en) 4644 { 4645 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4646 SOC_INIT_FUNC_DEFS; 4647 4648 PM4x10_QTC_QMOD_GET(pm_info); 4649 4650 if (!IS_QMOD) { 4651 _SOC_IF_ERR_EXIT( 4652 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_flow_control_set(unit, port, 4653 PM4x10_INFO(pm_info), merge_mode_en, parallel_fc_en)); 4654 } else { 4655 return (SOC_E_UNAVAIL); 4656 } 4657 4658 exit: 4659 SOC_FUNC_RETURN; 4660 } 4661 4662 int pm4x10_qtc_port_higig2_mode_set(int unit, int port, pm_info_t pm_info, int mode) 4663 { 4664 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4665 SOC_INIT_FUNC_DEFS; 4666 4667 PM4x10_QTC_QMOD_GET(pm_info); 4668 4669 if (!IS_QMOD) { 4670 _SOC_IF_ERR_EXIT( 4671 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_higig2_mode_set(unit, port, 4672 PM4x10_INFO(pm_info), mode)); 4673 } else { 4674 if (mode != PORTMOD_ENCAP_IEEE_MODE) { 4675 return (SOC_E_UNAVAIL); 4676 } 4677 } 4678 4679 exit: 4680 SOC_FUNC_RETURN; 4681 } 4682 4683 int pm4x10_qtc_port_higig_mode_set(int unit, int port, pm_info_t pm_info, int mode) 4684 { 4685 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4686 SOC_INIT_FUNC_DEFS; 4687 4688 PM4x10_QTC_QMOD_GET(pm_info); 4689 4690 if (!IS_QMOD) { 4691 _SOC_IF_ERR_EXIT( 4692 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_higig_mode_set(unit, port, 4693 PM4x10_INFO(pm_info), mode)); 4694 } else { 4695 if (mode != PORTMOD_ENCAP_IEEE_MODE) { 4696 return (SOC_E_UNAVAIL); 4697 } 4698 } 4699 4700 exit: 4701 SOC_FUNC_RETURN; 4702 } 4703 4704 int pm4x10_qtc_port_higig2_mode_get(int unit, int port, pm_info_t pm_info, int *mode) 4705 { 4706 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4707 SOC_INIT_FUNC_DEFS; 4708 4709 PM4x10_QTC_QMOD_GET(pm_info); 4710 4711 if (!IS_QMOD) { 4712 _SOC_IF_ERR_EXIT( 4713 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_higig2_mode_get(unit, port, 4714 PM4x10_INFO(pm_info), mode)); 4715 } else { 4716 *(mode) = PORTMOD_ENCAP_IEEE_MODE; 4717 } 4718 4719 exit: 4720 SOC_FUNC_RETURN; 4721 } 4722 4723 int pm4x10_qtc_port_higig_mode_get(int unit, int port, pm_info_t pm_info, int *mode) 4724 { 4725 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4726 SOC_INIT_FUNC_DEFS; 4727 4728 PM4x10_QTC_QMOD_GET(pm_info); 4729 4730 if (!IS_QMOD) { 4731 _SOC_IF_ERR_EXIT( 4732 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_higig_mode_get(unit, port, 4733 PM4x10_INFO(pm_info), mode)); 4734 } else { 4735 *(mode) = PORTMOD_ENCAP_IEEE_MODE; 4736 } 4737 4738 exit: 4739 SOC_FUNC_RETURN; 4740 } 4741 4742 int pm4x10_qtc_port_multi_get(int unit, int port, pm_info_t pm_info, portmod_multi_get_t* multi_get) 4743 { 4744 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4745 SOC_INIT_FUNC_DEFS; 4746 4747 PM4x10_QTC_QMOD_GET(pm_info); 4748 4749 if (!IS_QMOD) { 4750 _SOC_IF_ERR_EXIT( 4751 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_multi_get(unit, port, 4752 PM4x10_INFO(pm_info), multi_get)); 4753 } else { 4754 return (SOC_E_UNAVAIL); 4755 } 4756 4757 exit: 4758 SOC_FUNC_RETURN; 4759 } 4760 4761 int pm4x10_qtc_port_mac_rsv_mask_set(int unit, int port, pm_info_t pm_info, uint32 rsv_mask) 4762 { 4763 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4764 SOC_INIT_FUNC_DEFS; 4765 4766 PM4x10_QTC_QMOD_GET(pm_info); 4767 4768 if (!IS_QMOD) { 4769 _SOC_IF_ERR_EXIT( 4770 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mac_rsv_mask_set(unit, port, 4771 PM4x10_INFO(pm_info), rsv_mask)); 4772 } else { 4773 return (SOC_E_UNAVAIL); 4774 } 4775 4776 exit: 4777 SOC_FUNC_RETURN; 4778 } 4779 4780 int pm4x10_qtc_port_mib_reset_toggle(int unit, int port, pm_info_t pm_info, int port_index) 4781 { 4782 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4783 SOC_INIT_FUNC_DEFS; 4784 4785 PM4x10_QTC_QMOD_GET(pm_info); 4786 4787 if (!IS_QMOD) { 4788 _SOC_IF_ERR_EXIT( 4789 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mib_reset_toggle(unit, port, 4790 PM4x10_INFO(pm_info), port_index)); 4791 } else { 4792 return (SOC_E_UNAVAIL); 4793 } 4794 4795 exit: 4796 SOC_FUNC_RETURN; 4797 } 4798 4799 int _pm4x10_qtc_port_medium_config_set(int unit, int port, pm_info_t pm_info, soc_port_medium_t medium, soc_phy_config_t* config) 4800 { 4801 SOC_INIT_FUNC_DEFS; 4802 4803 _SOC_IF_ERR_EXIT 4804 (portmod_port_phychain_medium_config_set(unit, port, medium, config)); 4805 4806 exit: 4807 SOC_FUNC_RETURN; 4808 } 4809 4810 4811 int pm4x10_qtc_port_medium_config_set(int unit, int port, pm_info_t pm_info, soc_port_medium_t medium, soc_phy_config_t* config) 4812 { 4813 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4814 SOC_INIT_FUNC_DEFS; 4815 4816 PM4x10_QTC_QMOD_GET(pm_info); 4817 4818 if (!IS_QMOD) { 4819 _SOC_IF_ERR_EXIT( 4820 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_medium_config_set(unit, port, 4821 PM4x10_INFO(pm_info), medium, config)); 4822 } else { 4823 _SOC_IF_ERR_EXIT( 4824 _pm4x10_qtc_port_medium_config_set(unit, port, pm_info, medium, config)); 4825 4826 } 4827 4828 exit: 4829 SOC_FUNC_RETURN; 4830 } 4831 4832 int _pm4x10_qtc_port_medium_config_get(int unit, int port, pm_info_t pm_info, soc_port_medium_t medium, soc_phy_config_t* config) 4833 { 4834 SOC_INIT_FUNC_DEFS; 4835 4836 _SOC_IF_ERR_EXIT 4837 (portmod_port_phychain_medium_config_get(unit, port, medium, config)); 4838 4839 exit: 4840 SOC_FUNC_RETURN; 4841 } 4842 4843 int pm4x10_qtc_port_medium_config_get(int unit, int port, pm_info_t pm_info, soc_port_medium_t medium, soc_phy_config_t* config) 4844 { 4845 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4846 SOC_INIT_FUNC_DEFS; 4847 4848 PM4x10_QTC_QMOD_GET(pm_info); 4849 4850 if (!IS_QMOD) { 4851 _SOC_IF_ERR_EXIT( 4852 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_medium_config_get(unit, port, 4853 PM4x10_INFO(pm_info), medium, config)); 4854 } else { 4855 _SOC_IF_ERR_EXIT( 4856 _pm4x10_qtc_port_medium_config_get(unit, port, pm_info, medium, config)); 4857 4858 } 4859 4860 exit: 4861 SOC_FUNC_RETURN; 4862 } 4863 4864 int _pm4x10_qtc_port_medium_get(int unit, int port, pm_info_t pm_info, soc_port_medium_t* medium) 4865 { 4866 SOC_INIT_FUNC_DEFS; 4867 4868 _SOC_IF_ERR_EXIT 4869 (portmod_port_phychain_medium_get(unit, port, medium)); 4870 4871 exit: 4872 SOC_FUNC_RETURN; 4873 } 4874 4875 int pm4x10_qtc_port_medium_get(int unit, int port, pm_info_t pm_info, soc_port_medium_t* medium) 4876 { 4877 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4878 SOC_INIT_FUNC_DEFS; 4879 4880 PM4x10_QTC_QMOD_GET(pm_info); 4881 4882 if (!IS_QMOD) { 4883 _SOC_IF_ERR_EXIT( 4884 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_medium_get(unit, port, 4885 PM4x10_INFO(pm_info), medium)); 4886 } else { 4887 _SOC_IF_ERR_EXIT( 4888 _pm4x10_qtc_port_medium_get(unit, port, pm_info, medium)); 4889 4890 } 4891 4892 exit: 4893 SOC_FUNC_RETURN; 4894 } 4895 4896 int pm4x10_qtc_pm_bypass_set(int unit, pm_info_t pm_info, int enable) 4897 { 4898 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4899 SOC_INIT_FUNC_DEFS; 4900 4901 PM4x10_QTC_QMOD_GET(pm_info); 4902 4903 if (!IS_QMOD) { 4904 _SOC_IF_ERR_EXIT( 4905 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_pm_bypass_set(unit, 4906 PM4x10_INFO(pm_info), enable)); 4907 } else { 4908 return (SOC_E_UNAVAIL); 4909 } 4910 4911 exit: 4912 SOC_FUNC_RETURN; 4913 } 4914 4915 int pm4x10_qtc_pm_phys_get(int unit, pm_info_t pm_info, portmod_pbmp_t* phys) 4916 { 4917 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4918 SOC_INIT_FUNC_DEFS; 4919 4920 PM4x10_QTC_QMOD_GET(pm_info); 4921 4922 if (!IS_QMOD) { 4923 _SOC_IF_ERR_EXIT( 4924 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_pm_phys_get(unit, 4925 PM4x10_INFO(pm_info), phys)); 4926 } else { 4927 return (SOC_E_UNAVAIL); 4928 } 4929 4930 exit: 4931 SOC_FUNC_RETURN; 4932 } 4933 4934 int _pm4x10_qtc_port_cl72_set(int unit, int port, pm_info_t pm_info, uint32 enable) 4935 { 4936 phymod_phy_access_t phy_access[1+MAX_PHYN]; 4937 int nof_phys = 0; 4938 4939 SOC_INIT_FUNC_DEFS; 4940 4941 _SOC_IF_ERR_EXIT 4942 (portmod_port_chain_phy_access_get(unit, port, pm_info, 4943 phy_access ,(1+MAX_PHYN), 4944 &nof_phys)); 4945 4946 _SOC_IF_ERR_EXIT 4947 (portmod_port_phychain_cl72_set(unit, port, phy_access, nof_phys, enable)); 4948 4949 exit: 4950 SOC_FUNC_RETURN; 4951 } 4952 4953 int pm4x10_qtc_port_cl72_set(int unit, int port, pm_info_t pm_info, uint32 enable) 4954 { 4955 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4956 SOC_INIT_FUNC_DEFS; 4957 4958 PM4x10_QTC_QMOD_GET(pm_info); 4959 4960 if (!IS_QMOD) { 4961 _SOC_IF_ERR_EXIT( 4962 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_cl72_set(unit, port, 4963 PM4x10_INFO(pm_info), enable)); 4964 } else { 4965 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_cl72_set(unit, port, pm_info, enable)); 4966 } 4967 4968 exit: 4969 SOC_FUNC_RETURN; 4970 } 4971 4972 int _pm4x10_qtc_port_cl72_get(int unit, int port, pm_info_t pm_info, uint32* enable) 4973 { 4974 phymod_phy_access_t phy_access[1+MAX_PHYN]; 4975 int nof_phys = 0; 4976 4977 SOC_INIT_FUNC_DEFS; 4978 4979 _SOC_IF_ERR_EXIT 4980 (portmod_port_chain_phy_access_get(unit, port, pm_info, 4981 phy_access ,(1+MAX_PHYN), 4982 &nof_phys)); 4983 4984 _SOC_IF_ERR_EXIT 4985 (portmod_port_phychain_cl72_get(unit, phy_access, nof_phys, enable)); 4986 4987 exit: 4988 SOC_FUNC_RETURN; 4989 } 4990 4991 int pm4x10_qtc_port_cl72_get(int unit, int port, pm_info_t pm_info, uint32* enable) 4992 { 4993 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 4994 SOC_INIT_FUNC_DEFS; 4995 4996 PM4x10_QTC_QMOD_GET(pm_info); 4997 4998 if (!IS_QMOD) { 4999 _SOC_IF_ERR_EXIT( 5000 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_cl72_get(unit, port, 5001 PM4x10_INFO(pm_info), enable)); 5002 } else { 5003 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_cl72_get(unit, port, pm_info, enable)); 5004 } 5005 5006 exit: 5007 SOC_FUNC_RETURN; 5008 } 5009 5010 int _pm4x10_qtc_port_cl72_status_get(int unit, int port, pm_info_t pm_info, phymod_cl72_status_t* status) 5011 { 5012 phymod_phy_access_t phy_access[1+MAX_PHYN]; 5013 int nof_phys = 0; 5014 5015 SOC_INIT_FUNC_DEFS; 5016 5017 _SOC_IF_ERR_EXIT 5018 (portmod_port_chain_phy_access_get(unit, port, pm_info, 5019 phy_access ,(1+MAX_PHYN), 5020 &nof_phys)); 5021 5022 _SOC_IF_ERR_EXIT 5023 (portmod_port_phychain_cl72_status_get(unit, phy_access, nof_phys, status)); 5024 5025 exit: 5026 SOC_FUNC_RETURN; 5027 } 5028 5029 int pm4x10_qtc_port_cl72_status_get(int unit, int port, pm_info_t pm_info, phymod_cl72_status_t* status) 5030 { 5031 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5032 SOC_INIT_FUNC_DEFS; 5033 5034 PM4x10_QTC_QMOD_GET(pm_info); 5035 5036 if (!IS_QMOD) { 5037 _SOC_IF_ERR_EXIT( 5038 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_cl72_status_get(unit, port, 5039 PM4x10_INFO(pm_info), status)); 5040 } else { 5041 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_cl72_status_get(unit, port, pm_info, status)); 5042 } 5043 5044 exit: 5045 SOC_FUNC_RETURN; 5046 } 5047 5048 int pm4x10_qtc_port_tx_mac_enable_set(int unit, int port, pm_info_t pm_info, int enable) 5049 { 5050 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5051 SOC_INIT_FUNC_DEFS; 5052 5053 PM4x10_QTC_QMOD_GET(pm_info); 5054 5055 if (!IS_QMOD) { 5056 _SOC_IF_ERR_EXIT( 5057 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_tx_mac_enable_set(unit, port, 5058 PM4x10_INFO(pm_info), enable)); 5059 } else { 5060 _SOC_IF_ERR_EXIT(unimac_tx_enable_set(unit, port, enable)); 5061 } 5062 5063 exit: 5064 SOC_FUNC_RETURN; 5065 } 5066 5067 int pm4x10_qtc_port_tx_mac_enable_get(int unit, int port, pm_info_t pm_info, int* enable) 5068 { 5069 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5070 SOC_INIT_FUNC_DEFS; 5071 5072 PM4x10_QTC_QMOD_GET(pm_info); 5073 5074 if (!IS_QMOD) { 5075 _SOC_IF_ERR_EXIT( 5076 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_tx_mac_enable_get(unit, port, 5077 PM4x10_INFO(pm_info), enable)); 5078 } else { 5079 _SOC_IF_ERR_EXIT(unimac_tx_enable_get(unit, port, enable)); 5080 } 5081 5082 exit: 5083 SOC_FUNC_RETURN; 5084 } 5085 5086 int pm4x10_qtc_port_link_latch_down_get(int unit, int port, pm_info_t pm_info, uint32 flags, int* link) 5087 { 5088 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5089 SOC_INIT_FUNC_DEFS; 5090 5091 PM4x10_QTC_QMOD_GET(pm_info); 5092 5093 if (!IS_QMOD) { 5094 _SOC_IF_ERR_EXIT( 5095 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_link_latch_down_get(unit, port, 5096 PM4x10_INFO(pm_info), flags, link)); 5097 } else { 5098 return (SOC_E_UNAVAIL); 5099 } 5100 5101 exit: 5102 SOC_FUNC_RETURN; 5103 } 5104 5105 int pm4x10_qtc_port_prbs_config_set(int unit, int port, pm_info_t pm_info, portmod_prbs_mode_t mode, int flags, const phymod_prbs_t* config) 5106 { 5107 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5108 SOC_INIT_FUNC_DEFS; 5109 5110 PM4x10_QTC_QMOD_GET(pm_info); 5111 5112 if (!IS_QMOD) { 5113 _SOC_IF_ERR_EXIT( 5114 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_prbs_config_set(unit, port, 5115 PM4x10_INFO(pm_info), mode, flags, config)); 5116 } else { 5117 return (SOC_E_UNAVAIL); 5118 } 5119 5120 exit: 5121 SOC_FUNC_RETURN; 5122 } 5123 5124 int pm4x10_qtc_port_prbs_config_get(int unit, int port, pm_info_t pm_info, portmod_prbs_mode_t mode, int flags, phymod_prbs_t* config) 5125 { 5126 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5127 SOC_INIT_FUNC_DEFS; 5128 5129 PM4x10_QTC_QMOD_GET(pm_info); 5130 5131 if (!IS_QMOD) { 5132 _SOC_IF_ERR_EXIT( 5133 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_prbs_config_get(unit, port, 5134 PM4x10_INFO(pm_info), mode, flags, config)); 5135 } else { 5136 return (SOC_E_UNAVAIL); 5137 } 5138 5139 exit: 5140 SOC_FUNC_RETURN; 5141 } 5142 5143 int pm4x10_qtc_port_prbs_enable_set(int unit, int port, pm_info_t pm_info, portmod_prbs_mode_t mode, int flags, int enable) 5144 { 5145 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5146 SOC_INIT_FUNC_DEFS; 5147 5148 PM4x10_QTC_QMOD_GET(pm_info); 5149 5150 if (!IS_QMOD) { 5151 _SOC_IF_ERR_EXIT( 5152 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_prbs_enable_set(unit, port, 5153 PM4x10_INFO(pm_info), mode, flags, enable)); 5154 } else { 5155 return (SOC_E_UNAVAIL); 5156 } 5157 5158 exit: 5159 SOC_FUNC_RETURN; 5160 } 5161 5162 int pm4x10_qtc_port_prbs_enable_get(int unit, int port, pm_info_t pm_info, portmod_prbs_mode_t mode, int flags, int* enable) 5163 { 5164 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5165 SOC_INIT_FUNC_DEFS; 5166 5167 PM4x10_QTC_QMOD_GET(pm_info); 5168 5169 if (!IS_QMOD) { 5170 _SOC_IF_ERR_EXIT( 5171 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_prbs_enable_get(unit, port, 5172 PM4x10_INFO(pm_info), mode, flags, enable)); 5173 } else { 5174 return (SOC_E_UNAVAIL); 5175 } 5176 5177 exit: 5178 SOC_FUNC_RETURN; 5179 } 5180 5181 int pm4x10_qtc_port_prbs_status_get(int unit, int port, pm_info_t pm_info, portmod_prbs_mode_t mode, int flags, phymod_prbs_status_t* status) 5182 { 5183 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5184 SOC_INIT_FUNC_DEFS; 5185 5186 PM4x10_QTC_QMOD_GET(pm_info); 5187 5188 if (!IS_QMOD) { 5189 _SOC_IF_ERR_EXIT( 5190 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_prbs_status_get(unit, port, 5191 PM4x10_INFO(pm_info), mode, flags, status)); 5192 } else { 5193 return (SOC_E_UNAVAIL); 5194 } 5195 5196 exit: 5197 SOC_FUNC_RETURN; 5198 } 5199 5200 int pm4x10_qtc_port_firmware_mode_set(int unit, int port, pm_info_t pm_info, phymod_firmware_mode_t fw_mode) 5201 { 5202 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5203 SOC_INIT_FUNC_DEFS; 5204 5205 PM4x10_QTC_QMOD_GET(pm_info); 5206 5207 if (!IS_QMOD) { 5208 _SOC_IF_ERR_EXIT( 5209 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_firmware_mode_set(unit, port, 5210 PM4x10_INFO(pm_info), fw_mode)); 5211 } else { 5212 return (SOC_E_UNAVAIL); 5213 } 5214 5215 exit: 5216 SOC_FUNC_RETURN; 5217 } 5218 5219 int pm4x10_qtc_port_firmware_mode_get(int unit, int port, pm_info_t pm_info, phymod_firmware_mode_t* fw_mode) 5220 { 5221 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5222 SOC_INIT_FUNC_DEFS; 5223 5224 PM4x10_QTC_QMOD_GET(pm_info); 5225 5226 if (!IS_QMOD) { 5227 _SOC_IF_ERR_EXIT( 5228 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_firmware_mode_get(unit, port, 5229 PM4x10_INFO(pm_info), fw_mode)); 5230 } else { 5231 return (SOC_E_UNAVAIL); 5232 } 5233 5234 exit: 5235 SOC_FUNC_RETURN; 5236 } 5237 5238 int pm4x10_qtc_port_runt_threshold_set(int unit, int port, pm_info_t pm_info, int value) 5239 { 5240 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5241 SOC_INIT_FUNC_DEFS; 5242 5243 PM4x10_QTC_QMOD_GET(pm_info); 5244 5245 if (!IS_QMOD) { 5246 _SOC_IF_ERR_EXIT( 5247 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_runt_threshold_set(unit, port, 5248 PM4x10_INFO(pm_info), value)); 5249 } else { 5250 return (SOC_E_UNAVAIL); 5251 } 5252 5253 exit: 5254 SOC_FUNC_RETURN; 5255 } 5256 5257 int pm4x10_qtc_port_runt_threshold_get(int unit, int port, pm_info_t pm_info, int* value) 5258 { 5259 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5260 SOC_INIT_FUNC_DEFS; 5261 5262 PM4x10_QTC_QMOD_GET(pm_info); 5263 5264 if (!IS_QMOD) { 5265 _SOC_IF_ERR_EXIT( 5266 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_runt_threshold_get(unit, port, 5267 PM4x10_INFO(pm_info), value)); 5268 } else { 5269 return (SOC_E_UNAVAIL); 5270 } 5271 5272 exit: 5273 SOC_FUNC_RETURN; 5274 } 5275 5276 int pm4x10_qtc_port_local_fault_status_get(int unit, int port, pm_info_t pm_info, int* value) 5277 { 5278 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5279 SOC_INIT_FUNC_DEFS; 5280 5281 PM4x10_QTC_QMOD_GET(pm_info); 5282 5283 if (!IS_QMOD) { 5284 _SOC_IF_ERR_EXIT( 5285 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_local_fault_status_get(unit, port, 5286 PM4x10_INFO(pm_info), value)); 5287 } else { 5288 return (SOC_E_UNAVAIL); 5289 } 5290 5291 exit: 5292 SOC_FUNC_RETURN; 5293 } 5294 5295 int pm4x10_qtc_port_remote_fault_status_get(int unit, int port, pm_info_t pm_info, int* value) 5296 { 5297 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5298 SOC_INIT_FUNC_DEFS; 5299 5300 PM4x10_QTC_QMOD_GET(pm_info); 5301 5302 if (!IS_QMOD) { 5303 _SOC_IF_ERR_EXIT( 5304 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_remote_fault_status_get(unit, port, 5305 PM4x10_INFO(pm_info), value)); 5306 } else { 5307 return (SOC_E_UNAVAIL); 5308 } 5309 5310 exit: 5311 SOC_FUNC_RETURN; 5312 } 5313 5314 STATIC 5315 int _pm4x10_qtc_port_phy_reg_read(int unit, int port, pm_info_t pm_info, int lane, int flags, int reg_addr, uint32* value) 5316 { 5317 phymod_phy_access_t phy_access[1+MAX_PHYN]; 5318 int nof_phys; 5319 SOC_INIT_FUNC_DEFS; 5320 5321 _SOC_IF_ERR_EXIT 5322 (portmod_port_chain_phy_access_get(unit, port, pm_info, 5323 phy_access ,(1+MAX_PHYN), 5324 &nof_phys)); 5325 _SOC_IF_ERR_EXIT 5326 (portmod_port_phychain_reg_read(unit, port, phy_access, nof_phys, lane, flags, reg_addr,value)); 5327 5328 exit: 5329 SOC_FUNC_RETURN; 5330 } 5331 5332 STATIC 5333 int _pm4x10_qtc_port_phy_reg_write(int unit, int port, pm_info_t pm_info, int lane, int flags, int reg_addr, uint32 value) 5334 { 5335 phymod_phy_access_t phy_access[1+MAX_PHYN]; 5336 int nof_phys; 5337 SOC_INIT_FUNC_DEFS; 5338 5339 _SOC_IF_ERR_EXIT 5340 (portmod_port_chain_phy_access_get(unit, port, pm_info, 5341 phy_access ,(1+MAX_PHYN), 5342 &nof_phys)); 5343 _SOC_IF_ERR_EXIT 5344 (portmod_port_phychain_reg_write(unit, port, phy_access, nof_phys, lane, flags, reg_addr,value)); 5345 5346 exit: 5347 SOC_FUNC_RETURN; 5348 } 5349 5350 int pm4x10_qtc_port_phy_reg_read(int unit, int port, pm_info_t pm_info, int lane, int flags, int reg_addr, uint32* value) 5351 { 5352 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5353 SOC_INIT_FUNC_DEFS; 5354 5355 PM4x10_QTC_QMOD_GET(pm_info); 5356 5357 if (!IS_QMOD) { 5358 _SOC_IF_ERR_EXIT( 5359 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_reg_read(unit, port, 5360 PM4x10_INFO(pm_info), lane, flags, reg_addr, value)); 5361 } else { 5362 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_phy_reg_read(unit, port, 5363 pm_info, lane, flags, reg_addr, value)); 5364 } 5365 5366 exit: 5367 SOC_FUNC_RETURN; 5368 } 5369 5370 int pm4x10_qtc_port_phy_reg_write(int unit, int port, pm_info_t pm_info, int lane, int flags, int reg_addr, uint32 value) 5371 { 5372 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5373 SOC_INIT_FUNC_DEFS; 5374 5375 PM4x10_QTC_QMOD_GET(pm_info); 5376 5377 if (!IS_QMOD) { 5378 _SOC_IF_ERR_EXIT( 5379 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_reg_write(unit, port, 5380 PM4x10_INFO(pm_info), lane, flags, reg_addr, value)); 5381 } else { 5382 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_phy_reg_write(unit, port, 5383 pm_info, lane, flags, reg_addr, value)); 5384 } 5385 5386 exit: 5387 SOC_FUNC_RETURN; 5388 } 5389 5390 int pm4x10_qtc_port_reset_set(int unit, int port, pm_info_t pm_info, int mode, int opcode, int value) 5391 { 5392 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5393 SOC_INIT_FUNC_DEFS; 5394 5395 PM4x10_QTC_QMOD_GET(pm_info); 5396 5397 if (!IS_QMOD) { 5398 _SOC_IF_ERR_EXIT( 5399 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_reset_set(unit, port, 5400 PM4x10_INFO(pm_info), mode, opcode, value)); 5401 } else { 5402 return (SOC_E_UNAVAIL); 5403 } 5404 5405 exit: 5406 SOC_FUNC_RETURN; 5407 } 5408 5409 int pm4x10_qtc_port_reset_get(int unit, int port, pm_info_t pm_info, int mode, int opcode, int* value) 5410 { 5411 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5412 SOC_INIT_FUNC_DEFS; 5413 5414 PM4x10_QTC_QMOD_GET(pm_info); 5415 5416 if (!IS_QMOD) { 5417 _SOC_IF_ERR_EXIT( 5418 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_reset_get(unit, port, 5419 PM4x10_INFO(pm_info), mode, opcode, value)); 5420 } else { 5421 return (SOC_E_UNAVAIL); 5422 } 5423 5424 exit: 5425 SOC_FUNC_RETURN; 5426 } 5427 5428 int pm4x10_qtc_port_adv_remote_get(int unit, int port, pm_info_t pm_info, int* value) 5429 { 5430 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5431 SOC_INIT_FUNC_DEFS; 5432 5433 PM4x10_QTC_QMOD_GET(pm_info); 5434 5435 if (!IS_QMOD) { 5436 _SOC_IF_ERR_EXIT( 5437 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_adv_remote_get(unit, port, 5438 PM4x10_INFO(pm_info), value)); 5439 } else { 5440 return (SOC_E_UNAVAIL); 5441 } 5442 5443 exit: 5444 SOC_FUNC_RETURN; 5445 } 5446 5447 int _pm4x10_qtc_port_ability_remote_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, 5448 portmod_port_ability_t* ability) 5449 { 5450 phymod_phy_access_t phy_access[1+MAX_PHYN]; 5451 int nof_phys; 5452 phymod_autoneg_ability_t an_ability; 5453 int phy_index, xphy_id, is_legacy_phy = 0; 5454 SOC_INIT_FUNC_DEFS; 5455 5456 _SOC_IF_ERR_EXIT 5457 (portmod_port_chain_phy_access_get(unit, port, pm_info, phy_access, 5458 (1+MAX_PHYN), &nof_phys)); 5459 5460 phy_index = nof_phys -1; 5461 if (phy_index) { 5462 xphy_id = phy_access[phy_index].access.addr; 5463 _SOC_IF_ERR_EXIT(portmod_xphy_is_legacy_phy_get(unit, xphy_id, &is_legacy_phy)); 5464 } 5465 _SOC_IF_ERR_EXIT 5466 (portmod_port_phychain_autoneg_remote_ability_get(unit, port, 5467 phy_access, nof_phys, phy_flags, &an_ability, ability)); 5468 if (!is_legacy_phy) { 5469 portmod_common_phy_to_port_ability(&an_ability, ability); 5470 } 5471 5472 exit: 5473 SOC_FUNC_RETURN; 5474 } 5475 5476 int pm4x10_qtc_port_ability_remote_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, portmod_port_ability_t* ability) 5477 { 5478 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5479 SOC_INIT_FUNC_DEFS; 5480 5481 PM4x10_QTC_QMOD_GET(pm_info); 5482 5483 if (!IS_QMOD) { 5484 _SOC_IF_ERR_EXIT( 5485 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_ability_remote_get(unit, port, 5486 PM4x10_INFO(pm_info), phy_flags, ability)); 5487 } else { 5488 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_ability_remote_get(unit, port, pm_info, 5489 phy_flags, ability)); 5490 } 5491 5492 exit: 5493 SOC_FUNC_RETURN; 5494 } 5495 5496 int pm4x10_qtc_port_frame_spacing_stretch_set(int unit, int port, pm_info_t pm_info, int spacing) 5497 { 5498 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5499 SOC_INIT_FUNC_DEFS; 5500 5501 PM4x10_QTC_QMOD_GET(pm_info); 5502 5503 if (!IS_QMOD) { 5504 _SOC_IF_ERR_EXIT( 5505 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_frame_spacing_stretch_set(unit, port, 5506 PM4x10_INFO(pm_info), spacing)); 5507 } else { 5508 return (SOC_E_UNAVAIL); 5509 } 5510 5511 exit: 5512 SOC_FUNC_RETURN; 5513 } 5514 5515 int pm4x10_qtc_port_frame_spacing_stretch_get(int unit, int port, pm_info_t pm_info, const int* spacing) 5516 { 5517 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5518 SOC_INIT_FUNC_DEFS; 5519 5520 PM4x10_QTC_QMOD_GET(pm_info); 5521 5522 if (!IS_QMOD) { 5523 _SOC_IF_ERR_EXIT( 5524 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_frame_spacing_stretch_get(unit, port, 5525 PM4x10_INFO(pm_info), spacing)); 5526 } else { 5527 return (SOC_E_UNAVAIL); 5528 } 5529 5530 exit: 5531 SOC_FUNC_RETURN; 5532 } 5533 5534 STATIC 5535 int _pm4x10_qtc_port_rx_control_set(int unit, int port, pm_info_t pm_info, const portmod_rx_control_t* rx_ctrl) 5536 { 5537 portmod_pfc_config_t pfc_cfg; 5538 SOC_INIT_FUNC_DEFS; 5539 5540 if (rx_ctrl->flags & PORTMOD_MAC_PASS_CONTROL_FRAME) { 5541 _SOC_IF_ERR_EXIT 5542 (unimac_pass_control_frame_set(unit, port, rx_ctrl->pass_control_frames)); 5543 } 5544 5545 if (rx_ctrl->flags & PORTMOD_MAC_PASS_PFC_FRAME) { 5546 _SOC_IF_ERR_EXIT(unimac_pfc_config_get(unit, port, &pfc_cfg)); 5547 pfc_cfg.rxpass = rx_ctrl->pass_pfc_frames; 5548 _SOC_IF_ERR_EXIT(unimac_pfc_config_set(unit, port, &pfc_cfg)); 5549 } 5550 5551 if (rx_ctrl->flags & PORTMOD_MAC_PASS_PAUSE_FRAME) { 5552 _SOC_IF_ERR_EXIT 5553 (unimac_pass_pause_frame_set(unit, port, rx_ctrl->pass_pause_frames)); 5554 } 5555 5556 exit: 5557 SOC_FUNC_RETURN; 5558 } 5559 5560 int pm4x10_qtc_port_rx_control_set(int unit, int port, pm_info_t pm_info, const portmod_rx_control_t* rx_ctrl) 5561 { 5562 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5563 SOC_INIT_FUNC_DEFS; 5564 5565 PM4x10_QTC_QMOD_GET(pm_info); 5566 5567 if (!IS_QMOD) { 5568 _SOC_IF_ERR_EXIT( 5569 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_rx_control_set(unit, port, 5570 PM4x10_INFO(pm_info), rx_ctrl)); 5571 } else { 5572 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_rx_control_set(unit, port, pm_info, rx_ctrl)); 5573 } 5574 5575 exit: 5576 SOC_FUNC_RETURN; 5577 } 5578 5579 STATIC 5580 int _pm4x10_qtc_port_rx_control_get(int unit, int port, pm_info_t pm_info, portmod_rx_control_t* rx_ctrl) 5581 { 5582 portmod_pfc_config_t pfc_cfg; 5583 SOC_INIT_FUNC_DEFS; 5584 5585 _SOC_IF_ERR_EXIT 5586 (unimac_pass_control_frame_get(unit, port, (int*)&rx_ctrl->pass_control_frames)); 5587 _SOC_IF_ERR_EXIT(unimac_pfc_config_get(unit, port, &pfc_cfg)); 5588 rx_ctrl->pass_pfc_frames = pfc_cfg.rxpass; 5589 _SOC_IF_ERR_EXIT 5590 (unimac_pass_pause_frame_get(unit, port, &rx_ctrl->pass_pause_frames)); 5591 5592 exit: 5593 SOC_FUNC_RETURN; 5594 } 5595 5596 int pm4x10_qtc_port_rx_control_get(int unit, int port, pm_info_t pm_info, portmod_rx_control_t* rx_ctrl) 5597 { 5598 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5599 SOC_INIT_FUNC_DEFS; 5600 5601 PM4x10_QTC_QMOD_GET(pm_info); 5602 5603 if (!IS_QMOD) { 5604 _SOC_IF_ERR_EXIT( 5605 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_rx_control_get(unit, port, 5606 PM4x10_INFO(pm_info), rx_ctrl)); 5607 } else { 5608 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_rx_control_get(unit, port, pm_info, rx_ctrl)); 5609 } 5610 5611 exit: 5612 SOC_FUNC_RETURN; 5613 } 5614 5615 int pm4x10_qtc_port_eee_clock_set(int unit, int port, pm_info_t pm_info, const portmod_eee_clock_t* eee_clk) 5616 { 5617 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5618 SOC_INIT_FUNC_DEFS; 5619 5620 PM4x10_QTC_QMOD_GET(pm_info); 5621 5622 if (!IS_QMOD) { 5623 _SOC_IF_ERR_EXIT( 5624 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_eee_clock_set(unit, port, 5625 PM4x10_INFO(pm_info), eee_clk)); 5626 } else { 5627 return (SOC_E_UNAVAIL); 5628 } 5629 5630 exit: 5631 SOC_FUNC_RETURN; 5632 } 5633 5634 int pm4x10_qtc_port_eee_clock_get(int unit, int port, pm_info_t pm_info, portmod_eee_clock_t* eee_clk) 5635 { 5636 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5637 SOC_INIT_FUNC_DEFS; 5638 5639 PM4x10_QTC_QMOD_GET(pm_info); 5640 5641 if (!IS_QMOD) { 5642 _SOC_IF_ERR_EXIT( 5643 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_eee_clock_get(unit, port, 5644 PM4x10_INFO(pm_info), eee_clk)); 5645 } else { 5646 return (SOC_E_UNAVAIL); 5647 } 5648 5649 exit: 5650 SOC_FUNC_RETURN; 5651 } 5652 5653 int pm4x10_qtc_port_modid_set(int unit, int port, pm_info_t pm_info, int value) 5654 { 5655 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5656 SOC_INIT_FUNC_DEFS; 5657 5658 PM4x10_QTC_QMOD_GET(pm_info); 5659 5660 if (!IS_QMOD) { 5661 _SOC_IF_ERR_EXIT( 5662 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_modid_set(unit, port, 5663 PM4x10_INFO(pm_info), value)); 5664 } else { 5665 return (SOC_E_UNAVAIL); 5666 } 5667 5668 exit: 5669 SOC_FUNC_RETURN; 5670 } 5671 5672 int pm4x10_qtc_port_clear_rx_lss_status_set(int unit, int port, pm_info_t pm_info, int lcl_fault, int rmt_fault) 5673 { 5674 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5675 SOC_INIT_FUNC_DEFS; 5676 5677 PM4x10_QTC_QMOD_GET(pm_info); 5678 5679 if (!IS_QMOD) { 5680 _SOC_IF_ERR_EXIT( 5681 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_clear_rx_lss_status_set(unit, port, 5682 PM4x10_INFO(pm_info), lcl_fault, rmt_fault)); 5683 } 5684 5685 exit: 5686 SOC_FUNC_RETURN; 5687 } 5688 5689 int pm4x10_qtc_port_clear_rx_lss_status_get(int unit, int port, pm_info_t pm_info, int* lcl_fault, int* rmt_fault) 5690 { 5691 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5692 SOC_INIT_FUNC_DEFS; 5693 5694 PM4x10_QTC_QMOD_GET(pm_info); 5695 5696 if (!IS_QMOD) { 5697 _SOC_IF_ERR_EXIT( 5698 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_clear_rx_lss_status_get(unit, port, 5699 PM4x10_INFO(pm_info), lcl_fault, rmt_fault)); 5700 } else { 5701 return (SOC_E_UNAVAIL); 5702 } 5703 5704 exit: 5705 SOC_FUNC_RETURN; 5706 } 5707 5708 int pm4x10_qtc_port_lag_failover_loopback_set(int unit, int port, pm_info_t pm_info, int value) 5709 { 5710 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5711 SOC_INIT_FUNC_DEFS; 5712 5713 PM4x10_QTC_QMOD_GET(pm_info); 5714 5715 if (!IS_QMOD) { 5716 _SOC_IF_ERR_EXIT( 5717 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_lag_failover_loopback_set(unit, port, 5718 PM4x10_INFO(pm_info), value)); 5719 } else { 5720 return (SOC_E_UNAVAIL); 5721 } 5722 5723 exit: 5724 SOC_FUNC_RETURN; 5725 } 5726 5727 int pm4x10_qtc_port_lag_failover_loopback_get(int unit, int port, pm_info_t pm_info, int* value) 5728 { 5729 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5730 SOC_INIT_FUNC_DEFS; 5731 5732 PM4x10_QTC_QMOD_GET(pm_info); 5733 5734 if (!IS_QMOD) { 5735 _SOC_IF_ERR_EXIT( 5736 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_lag_failover_loopback_get(unit, port, 5737 PM4x10_INFO(pm_info), value)); 5738 } else { 5739 return (SOC_E_UNAVAIL); 5740 } 5741 5742 exit: 5743 SOC_FUNC_RETURN; 5744 } 5745 5746 int pm4x10_qtc_port_config_port_type_set(int unit, int port, pm_info_t pm_info, int type) 5747 { 5748 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5749 SOC_INIT_FUNC_DEFS; 5750 5751 PM4x10_QTC_QMOD_GET(pm_info); 5752 5753 if (!IS_QMOD) { 5754 _SOC_IF_ERR_EXIT( 5755 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_config_port_type_set(unit, port, 5756 PM4x10_INFO(pm_info), type)); 5757 } else { 5758 return (SOC_E_UNAVAIL); 5759 } 5760 5761 exit: 5762 SOC_FUNC_RETURN; 5763 } 5764 5765 int pm4x10_qtc_port_config_port_type_get(int unit, int port, pm_info_t pm_info, int* type) 5766 { 5767 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5768 SOC_INIT_FUNC_DEFS; 5769 5770 PM4x10_QTC_QMOD_GET(pm_info); 5771 5772 if (!IS_QMOD) { 5773 _SOC_IF_ERR_EXIT( 5774 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_config_port_type_get(unit, port, 5775 PM4x10_INFO(pm_info), type)); 5776 } else { 5777 return (SOC_E_UNAVAIL); 5778 } 5779 5780 exit: 5781 SOC_FUNC_RETURN; 5782 } 5783 5784 int pm4x10_qtc_port_trunk_hwfailover_config_set(int unit, int port, pm_info_t pm_info, int hw_count) 5785 { 5786 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5787 SOC_INIT_FUNC_DEFS; 5788 5789 PM4x10_QTC_QMOD_GET(pm_info); 5790 5791 if (!IS_QMOD) { 5792 _SOC_IF_ERR_EXIT( 5793 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_trunk_hwfailover_config_set(unit, port, 5794 PM4x10_INFO(pm_info), hw_count)); 5795 } else { 5796 return (SOC_E_UNAVAIL); 5797 } 5798 5799 exit: 5800 SOC_FUNC_RETURN; 5801 } 5802 5803 int pm4x10_qtc_port_trunk_hwfailover_config_get(int unit, int port, pm_info_t pm_info, int* enable) 5804 { 5805 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5806 SOC_INIT_FUNC_DEFS; 5807 5808 PM4x10_QTC_QMOD_GET(pm_info); 5809 5810 if (!IS_QMOD) { 5811 _SOC_IF_ERR_EXIT( 5812 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_trunk_hwfailover_config_get(unit, port, 5813 PM4x10_INFO(pm_info), enable)); 5814 } else { 5815 return (SOC_E_UNAVAIL); 5816 } 5817 5818 exit: 5819 SOC_FUNC_RETURN; 5820 } 5821 5822 int pm4x10_qtc_port_trunk_hwfailover_status_get(int unit, int port, pm_info_t pm_info, int* loopback) 5823 { 5824 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5825 SOC_INIT_FUNC_DEFS; 5826 5827 PM4x10_QTC_QMOD_GET(pm_info); 5828 5829 if (!IS_QMOD) { 5830 _SOC_IF_ERR_EXIT( 5831 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_trunk_hwfailover_status_get(unit, port, 5832 PM4x10_INFO(pm_info), loopback)); 5833 } else { 5834 return (SOC_E_UNAVAIL); 5835 } 5836 5837 exit: 5838 SOC_FUNC_RETURN; 5839 } 5840 5841 int pm4x10_qtc_port_lag_failover_disable(int unit, int port, pm_info_t pm_info) 5842 { 5843 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5844 SOC_INIT_FUNC_DEFS; 5845 5846 PM4x10_QTC_QMOD_GET(pm_info); 5847 5848 if (!IS_QMOD) { 5849 _SOC_IF_ERR_EXIT( 5850 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_lag_failover_disable(unit, port, 5851 PM4x10_INFO(pm_info))); 5852 } else { 5853 return (SOC_E_UNAVAIL); 5854 } 5855 5856 exit: 5857 SOC_FUNC_RETURN; 5858 } 5859 5860 int pm4x10_qtc_port_lag_remove_failover_lpbk_set(int unit, int port, pm_info_t pm_info, int val) 5861 { 5862 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5863 SOC_INIT_FUNC_DEFS; 5864 5865 PM4x10_QTC_QMOD_GET(pm_info); 5866 5867 if (!IS_QMOD) { 5868 _SOC_IF_ERR_EXIT( 5869 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_lag_remove_failover_lpbk_set(unit, port, 5870 PM4x10_INFO(pm_info), val)); 5871 } else { 5872 return (SOC_E_UNAVAIL); 5873 } 5874 5875 exit: 5876 SOC_FUNC_RETURN; 5877 } 5878 5879 int pm4x10_qtc_port_lag_remove_failover_lpbk_get(int unit, int port, pm_info_t pm_info, int* val) 5880 { 5881 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5882 SOC_INIT_FUNC_DEFS; 5883 5884 PM4x10_QTC_QMOD_GET(pm_info); 5885 5886 if (!IS_QMOD) { 5887 _SOC_IF_ERR_EXIT( 5888 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_lag_remove_failover_lpbk_get(unit, port, 5889 PM4x10_INFO(pm_info), val)); 5890 } else { 5891 return (SOC_E_UNAVAIL); 5892 } 5893 5894 exit: 5895 SOC_FUNC_RETURN; 5896 } 5897 5898 int pm4x10_qtc_port_egress_queue_drain_rx_en(int unit, int port, pm_info_t pm_info, int rx_en) 5899 { 5900 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5901 SOC_INIT_FUNC_DEFS; 5902 5903 PM4x10_QTC_QMOD_GET(pm_info); 5904 5905 if (!IS_QMOD) { 5906 _SOC_IF_ERR_EXIT( 5907 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_egress_queue_drain_rx_en(unit, port, 5908 PM4x10_INFO(pm_info), rx_en)); 5909 } else { 5910 return (SOC_E_UNAVAIL); 5911 } 5912 5913 exit: 5914 SOC_FUNC_RETURN; 5915 } 5916 5917 int pm4x10_qtc_port_mac_ctrl_set(int unit, int port, pm_info_t pm_info, uint64 ctrl) 5918 { 5919 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5920 SOC_INIT_FUNC_DEFS; 5921 5922 PM4x10_QTC_QMOD_GET(pm_info); 5923 5924 if (!IS_QMOD) { 5925 _SOC_IF_ERR_EXIT( 5926 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mac_ctrl_set(unit, port, 5927 PM4x10_INFO(pm_info), ctrl)); 5928 } else { 5929 uint32 mac_ctrl; 5930 5931 COMPILER_64_TO_32_LO(mac_ctrl, ctrl); 5932 5933 _SOC_IF_ERR_EXIT(unimac_mac_ctrl_set(unit, port, mac_ctrl)); 5934 } 5935 5936 exit: 5937 SOC_FUNC_RETURN; 5938 } 5939 5940 int pm4x10_qtc_port_egress_queue_drain_get(int unit, int port, pm_info_t pm_info, uint64* ctrl, int* rxen) 5941 { 5942 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5943 SOC_INIT_FUNC_DEFS; 5944 5945 PM4x10_QTC_QMOD_GET(pm_info); 5946 5947 if (!IS_QMOD) { 5948 _SOC_IF_ERR_EXIT( 5949 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_egress_queue_drain_get(unit, port, 5950 PM4x10_INFO(pm_info), ctrl, rxen)); 5951 } else { 5952 uint32 mac_ctrl; 5953 5954 _SOC_IF_ERR_EXIT(unimac_mac_ctrl_get(unit, port, &mac_ctrl, rxen)); 5955 COMPILER_64_SET(*ctrl, 0, mac_ctrl); 5956 } 5957 5958 exit: 5959 SOC_FUNC_RETURN; 5960 } 5961 5962 int pm4x10_qtc_port_mac_reset_set(int unit, int port, pm_info_t pm_info, int val) 5963 { 5964 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5965 SOC_INIT_FUNC_DEFS; 5966 5967 PM4x10_QTC_QMOD_GET(pm_info); 5968 5969 if (!IS_QMOD) { 5970 _SOC_IF_ERR_EXIT( 5971 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mac_reset_set(unit, port, 5972 PM4x10_INFO(pm_info), val)); 5973 } else { 5974 _SOC_IF_ERR_EXIT(unimac_soft_reset_set(unit, port, val)); 5975 } 5976 5977 exit: 5978 SOC_FUNC_RETURN; 5979 } 5980 5981 int pm4x10_qtc_port_mac_reset_get(int unit, int port, pm_info_t pm_info, int* val) 5982 { 5983 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 5984 SOC_INIT_FUNC_DEFS; 5985 5986 PM4x10_QTC_QMOD_GET(pm_info); 5987 5988 if (!IS_QMOD) { 5989 _SOC_IF_ERR_EXIT( 5990 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mac_reset_get(unit, port, 5991 PM4x10_INFO(pm_info), val)); 5992 } else { 5993 _SOC_IF_ERR_EXIT(unimac_soft_reset_get(unit, port, val)); 5994 } 5995 5996 exit: 5997 SOC_FUNC_RETURN; 5998 } 5999 6000 int _pm4x10_qtc_port_soft_reset_toggle(int unit, int port, pm_info_t pm_info, int idx) 6001 { 6002 int phy_acc = port; 6003 uint32 reg_val, old_val; 6004 SOC_INIT_FUNC_DEFS; 6005 6006 _SOC_IF_ERR_EXIT(READ_COMMAND_CONFIGr(unit, phy_acc, ®_val)); 6007 old_val = reg_val; 6008 6009 soc_reg_field_set(unit, COMMAND_CONFIGr, ®_val, SW_RESETf, 1); 6010 6011 _SOC_IF_ERR_EXIT(WRITE_COMMAND_CONFIGr(unit, phy_acc, reg_val)); 6012 _SOC_IF_ERR_EXIT(WRITE_COMMAND_CONFIGr(unit, phy_acc, old_val)); 6013 6014 exit: 6015 SOC_FUNC_RETURN; 6016 } 6017 6018 int pm4x10_qtc_port_soft_reset_toggle(int unit, int port, pm_info_t pm_info, int idx) 6019 { 6020 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6021 SOC_INIT_FUNC_DEFS; 6022 6023 PM4x10_QTC_QMOD_GET(pm_info); 6024 6025 if (!IS_QMOD) { 6026 _SOC_IF_ERR_EXIT( 6027 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mac_reset_set(unit, port, 6028 PM4x10_INFO(pm_info), idx)); 6029 } else { 6030 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_soft_reset_toggle(unit, port, pm_info, idx)); 6031 } 6032 6033 exit: 6034 SOC_FUNC_RETURN; 6035 } 6036 6037 int pm4x10_qtc_port_e2ecc_hdr_set(int unit, int port, pm_info_t pm_info, const portmod_port_higig_e2ecc_hdr_t* e2ecc_hdr) 6038 { 6039 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6040 SOC_INIT_FUNC_DEFS; 6041 6042 PM4x10_QTC_QMOD_GET(pm_info); 6043 6044 if (!IS_QMOD) { 6045 _SOC_IF_ERR_EXIT( 6046 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_e2ecc_hdr_set(unit, port, 6047 PM4x10_INFO(pm_info), e2ecc_hdr)); 6048 } else { 6049 return (SOC_E_UNAVAIL); 6050 } 6051 6052 exit: 6053 SOC_FUNC_RETURN; 6054 } 6055 6056 int pm4x10_qtc_port_e2ecc_hdr_get(int unit, int port, pm_info_t pm_info, portmod_port_higig_e2ecc_hdr_t* e2ecc_hdr) 6057 { 6058 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6059 SOC_INIT_FUNC_DEFS; 6060 6061 PM4x10_QTC_QMOD_GET(pm_info); 6062 6063 if (!IS_QMOD) { 6064 _SOC_IF_ERR_EXIT( 6065 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_e2ecc_hdr_get(unit, port, 6066 PM4x10_INFO(pm_info), e2ecc_hdr)); 6067 } else { 6068 return (SOC_E_UNAVAIL); 6069 } 6070 6071 exit: 6072 SOC_FUNC_RETURN; 6073 } 6074 6075 int pm4x10_qtc_port_e2e_enable_set(int unit, int port, pm_info_t pm_info, int enable) 6076 { 6077 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6078 SOC_INIT_FUNC_DEFS; 6079 6080 PM4x10_QTC_QMOD_GET(pm_info); 6081 6082 if (!IS_QMOD) { 6083 _SOC_IF_ERR_EXIT( 6084 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_e2e_enable_set(unit, port, 6085 PM4x10_INFO(pm_info), enable)); 6086 } else { 6087 return (SOC_E_UNAVAIL); 6088 } 6089 6090 exit: 6091 SOC_FUNC_RETURN; 6092 } 6093 6094 int pm4x10_qtc_port_e2e_enable_get(int unit, int port, pm_info_t pm_info, int* enable) 6095 { 6096 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6097 SOC_INIT_FUNC_DEFS; 6098 6099 PM4x10_QTC_QMOD_GET(pm_info); 6100 6101 if (!IS_QMOD) { 6102 _SOC_IF_ERR_EXIT( 6103 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_e2e_enable_get(unit, port, 6104 PM4x10_INFO(pm_info), enable)); 6105 } else { 6106 return (SOC_E_UNAVAIL); 6107 } 6108 6109 exit: 6110 SOC_FUNC_RETURN; 6111 } 6112 6113 int pm4x10_qtc_port_fallback_lane_get(int unit, int port, pm_info_t pm_info, int* fallback_lane) 6114 { 6115 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6116 SOC_INIT_FUNC_DEFS; 6117 6118 PM4x10_QTC_QMOD_GET(pm_info); 6119 6120 if (!IS_QMOD) { 6121 _SOC_IF_ERR_EXIT( 6122 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_fallback_lane_get(unit, port, 6123 PM4x10_INFO(pm_info), fallback_lane)); 6124 } else { 6125 return (SOC_E_UNAVAIL); 6126 } 6127 6128 exit: 6129 SOC_FUNC_RETURN; 6130 } 6131 6132 int pm4x10_qtc_port_pgw_reconfig(int unit, int port, pm_info_t pm_info, const portmod_port_mode_info_t* pmode, int phy_port, int flags) 6133 { 6134 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6135 SOC_INIT_FUNC_DEFS; 6136 6137 PM4x10_QTC_QMOD_GET(pm_info); 6138 6139 if (!IS_QMOD) { 6140 _SOC_IF_ERR_EXIT( 6141 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_pgw_reconfig(unit, port, 6142 PM4x10_INFO(pm_info), pmode, phy_port, flags)); 6143 } else { 6144 return (SOC_E_UNAVAIL); 6145 } 6146 6147 exit: 6148 SOC_FUNC_RETURN; 6149 } 6150 6151 int pm4x10_qtc_port_notify(int unit, int port, pm_info_t pm_info, int link) 6152 { 6153 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6154 SOC_INIT_FUNC_DEFS; 6155 6156 PM4x10_QTC_QMOD_GET(pm_info); 6157 6158 if (!IS_QMOD) { 6159 _SOC_IF_ERR_EXIT( 6160 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_notify(unit, port, 6161 PM4x10_INFO(pm_info), link)); 6162 } else { 6163 return (SOC_E_UNAVAIL); 6164 } 6165 6166 exit: 6167 SOC_FUNC_RETURN; 6168 } 6169 6170 int pm4x10_qtc_port_control_phy_timesync_set(int unit, int port, pm_info_t pm_info, portmod_port_control_phy_timesync_t config, uint64 value) 6171 { 6172 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6173 SOC_INIT_FUNC_DEFS; 6174 6175 PM4x10_QTC_QMOD_GET(pm_info); 6176 6177 if (!IS_QMOD) { 6178 _SOC_IF_ERR_EXIT( 6179 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_control_phy_timesync_set(unit, port, 6180 PM4x10_INFO(pm_info), config, value)); 6181 } else { 6182 return (SOC_E_UNAVAIL); 6183 } 6184 6185 exit: 6186 SOC_FUNC_RETURN; 6187 } 6188 6189 int pm4x10_qtc_port_control_phy_timesync_get(int unit, int port, pm_info_t pm_info, portmod_port_control_phy_timesync_t config, uint64* value) 6190 { 6191 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6192 SOC_INIT_FUNC_DEFS; 6193 6194 PM4x10_QTC_QMOD_GET(pm_info); 6195 6196 if (!IS_QMOD) { 6197 _SOC_IF_ERR_EXIT( 6198 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_control_phy_timesync_get(unit, port, 6199 PM4x10_INFO(pm_info), config, value)); 6200 } else { 6201 return (SOC_E_UNAVAIL); 6202 } 6203 6204 exit: 6205 SOC_FUNC_RETURN; 6206 } 6207 6208 int pm4x10_qtc_port_timesync_config_set(int unit, int port, pm_info_t pm_info, const portmod_phy_timesync_config_t* config) 6209 { 6210 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6211 SOC_INIT_FUNC_DEFS; 6212 6213 PM4x10_QTC_QMOD_GET(pm_info); 6214 6215 if (!IS_QMOD) { 6216 _SOC_IF_ERR_EXIT( 6217 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_config_set(unit, port, 6218 PM4x10_INFO(pm_info), config)); 6219 } else { 6220 return (SOC_E_UNAVAIL); 6221 } 6222 6223 exit: 6224 SOC_FUNC_RETURN; 6225 } 6226 6227 int pm4x10_qtc_port_timesync_config_get(int unit, int port, pm_info_t pm_info, portmod_phy_timesync_config_t* config) 6228 { 6229 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6230 SOC_INIT_FUNC_DEFS; 6231 6232 PM4x10_QTC_QMOD_GET(pm_info); 6233 6234 if (!IS_QMOD) { 6235 _SOC_IF_ERR_EXIT( 6236 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_config_get(unit, port, 6237 PM4x10_INFO(pm_info), config)); 6238 } else { 6239 return (SOC_E_UNAVAIL); 6240 } 6241 6242 exit: 6243 SOC_FUNC_RETURN; 6244 } 6245 6246 int pm4x10_qtc_port_timesync_enable_set(int unit, int port, pm_info_t pm_info, uint32 enable) 6247 { 6248 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6249 SOC_INIT_FUNC_DEFS; 6250 6251 PM4x10_QTC_QMOD_GET(pm_info); 6252 6253 if (!IS_QMOD) { 6254 _SOC_IF_ERR_EXIT( 6255 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_enable_set(unit, port, 6256 PM4x10_INFO(pm_info), enable)); 6257 } else { 6258 return (SOC_E_UNAVAIL); 6259 } 6260 6261 exit: 6262 SOC_FUNC_RETURN; 6263 } 6264 6265 int pm4x10_qtc_port_timesync_enable_get(int unit, int port, pm_info_t pm_info, uint32* enable) 6266 { 6267 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6268 SOC_INIT_FUNC_DEFS; 6269 6270 PM4x10_QTC_QMOD_GET(pm_info); 6271 6272 if (!IS_QMOD) { 6273 _SOC_IF_ERR_EXIT( 6274 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_enable_get(unit, port, 6275 PM4x10_INFO(pm_info), enable)); 6276 } else { 6277 return (SOC_E_UNAVAIL); 6278 } 6279 6280 exit: 6281 SOC_FUNC_RETURN; 6282 } 6283 6284 int pm4x10_qtc_port_timesync_nco_addend_set(int unit, int port, pm_info_t pm_info, uint32 freq_step) 6285 { 6286 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6287 SOC_INIT_FUNC_DEFS; 6288 6289 PM4x10_QTC_QMOD_GET(pm_info); 6290 6291 if (!IS_QMOD) { 6292 _SOC_IF_ERR_EXIT( 6293 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_nco_addend_set(unit, port, 6294 PM4x10_INFO(pm_info), freq_step)); 6295 } else { 6296 return (SOC_E_UNAVAIL); 6297 } 6298 6299 exit: 6300 SOC_FUNC_RETURN; 6301 } 6302 6303 int pm4x10_qtc_port_timesync_nco_addend_get(int unit, int port, pm_info_t pm_info, uint32* freq_step) 6304 { 6305 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6306 SOC_INIT_FUNC_DEFS; 6307 6308 PM4x10_QTC_QMOD_GET(pm_info); 6309 6310 if (!IS_QMOD) { 6311 _SOC_IF_ERR_EXIT( 6312 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_nco_addend_get(unit, port, 6313 PM4x10_INFO(pm_info), freq_step)); 6314 } else { 6315 return (SOC_E_UNAVAIL); 6316 } 6317 6318 exit: 6319 SOC_FUNC_RETURN; 6320 } 6321 6322 int pm4x10_qtc_port_timesync_framesync_mode_set(int unit, int port, pm_info_t pm_info, const portmod_timesync_framesync_t* framesync) 6323 { 6324 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6325 SOC_INIT_FUNC_DEFS; 6326 6327 PM4x10_QTC_QMOD_GET(pm_info); 6328 6329 if (!IS_QMOD) { 6330 _SOC_IF_ERR_EXIT( 6331 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_framesync_mode_set(unit, port, 6332 PM4x10_INFO(pm_info), framesync)); 6333 } else { 6334 return (SOC_E_UNAVAIL); 6335 } 6336 6337 exit: 6338 SOC_FUNC_RETURN; 6339 } 6340 6341 int pm4x10_qtc_port_timesync_framesync_mode_get(int unit, int port, pm_info_t pm_info, portmod_timesync_framesync_t* framesync) 6342 { 6343 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6344 SOC_INIT_FUNC_DEFS; 6345 6346 PM4x10_QTC_QMOD_GET(pm_info); 6347 6348 if (!IS_QMOD) { 6349 _SOC_IF_ERR_EXIT( 6350 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_framesync_mode_get(unit, port, 6351 PM4x10_INFO(pm_info), framesync)); 6352 } else { 6353 return (SOC_E_UNAVAIL); 6354 } 6355 6356 exit: 6357 SOC_FUNC_RETURN; 6358 } 6359 6360 int pm4x10_qtc_port_timesync_local_time_set(int unit, int port, pm_info_t pm_info, uint64 local_time) 6361 { 6362 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6363 SOC_INIT_FUNC_DEFS; 6364 6365 PM4x10_QTC_QMOD_GET(pm_info); 6366 6367 if (!IS_QMOD) { 6368 _SOC_IF_ERR_EXIT( 6369 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_local_time_set(unit, port, 6370 PM4x10_INFO(pm_info), local_time)); 6371 } else { 6372 return (SOC_E_UNAVAIL); 6373 } 6374 6375 exit: 6376 SOC_FUNC_RETURN; 6377 } 6378 6379 int pm4x10_qtc_port_timesync_local_time_get(int unit, int port, pm_info_t pm_info, uint64* local_time) 6380 { 6381 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6382 SOC_INIT_FUNC_DEFS; 6383 6384 PM4x10_QTC_QMOD_GET(pm_info); 6385 6386 if (!IS_QMOD) { 6387 _SOC_IF_ERR_EXIT( 6388 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_local_time_get(unit, port, 6389 PM4x10_INFO(pm_info), local_time)); 6390 } else { 6391 return (SOC_E_UNAVAIL); 6392 } 6393 6394 exit: 6395 SOC_FUNC_RETURN; 6396 } 6397 6398 int pm4x10_qtc_port_timesync_load_ctrl_set(int unit, int port, pm_info_t pm_info, uint32 load_once, uint32 load_always) 6399 { 6400 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6401 SOC_INIT_FUNC_DEFS; 6402 6403 PM4x10_QTC_QMOD_GET(pm_info); 6404 6405 if (!IS_QMOD) { 6406 _SOC_IF_ERR_EXIT( 6407 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_load_ctrl_set(unit, port, 6408 PM4x10_INFO(pm_info), load_once, load_always)); 6409 } else { 6410 return (SOC_E_UNAVAIL); 6411 } 6412 6413 exit: 6414 SOC_FUNC_RETURN; 6415 } 6416 6417 int pm4x10_qtc_port_timesync_load_ctrl_get(int unit, int port, pm_info_t pm_info, uint32* load_once, uint32* load_always) 6418 { 6419 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6420 SOC_INIT_FUNC_DEFS; 6421 6422 PM4x10_QTC_QMOD_GET(pm_info); 6423 6424 if (!IS_QMOD) { 6425 _SOC_IF_ERR_EXIT( 6426 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_load_ctrl_get(unit, port, 6427 PM4x10_INFO(pm_info), load_once, load_always)); 6428 } else { 6429 return (SOC_E_UNAVAIL); 6430 } 6431 6432 exit: 6433 SOC_FUNC_RETURN; 6434 } 6435 6436 int pm4x10_qtc_port_timesync_tx_timestamp_offset_set(int unit, int port, pm_info_t pm_info, uint32 ts_offset) 6437 { 6438 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6439 SOC_INIT_FUNC_DEFS; 6440 6441 PM4x10_QTC_QMOD_GET(pm_info); 6442 6443 if (!IS_QMOD) { 6444 _SOC_IF_ERR_EXIT( 6445 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_tx_timestamp_offset_set(unit, port, 6446 PM4x10_INFO(pm_info), ts_offset)); 6447 } else { 6448 return (SOC_E_UNAVAIL); 6449 } 6450 6451 exit: 6452 SOC_FUNC_RETURN; 6453 } 6454 6455 int pm4x10_qtc_port_timesync_tx_timestamp_offset_get(int unit, int port, pm_info_t pm_info, uint32* ts_offset) 6456 { 6457 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6458 SOC_INIT_FUNC_DEFS; 6459 6460 PM4x10_QTC_QMOD_GET(pm_info); 6461 6462 if (!IS_QMOD) { 6463 _SOC_IF_ERR_EXIT( 6464 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_tx_timestamp_offset_get(unit, port, 6465 PM4x10_INFO(pm_info), ts_offset)); 6466 } else { 6467 return (SOC_E_UNAVAIL); 6468 } 6469 6470 exit: 6471 SOC_FUNC_RETURN; 6472 } 6473 6474 int pm4x10_qtc_port_timesync_rx_timestamp_offset_set(int unit, int port, pm_info_t pm_info, uint32 ts_offset) 6475 { 6476 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6477 SOC_INIT_FUNC_DEFS; 6478 6479 PM4x10_QTC_QMOD_GET(pm_info); 6480 6481 if (!IS_QMOD) { 6482 _SOC_IF_ERR_EXIT( 6483 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_rx_timestamp_offset_set(unit, port, 6484 PM4x10_INFO(pm_info), ts_offset)); 6485 } else { 6486 return (SOC_E_UNAVAIL); 6487 } 6488 6489 exit: 6490 SOC_FUNC_RETURN; 6491 } 6492 6493 int pm4x10_qtc_port_timesync_rx_timestamp_offset_get(int unit, int port, pm_info_t pm_info, uint32* ts_offset) 6494 { 6495 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6496 SOC_INIT_FUNC_DEFS; 6497 6498 PM4x10_QTC_QMOD_GET(pm_info); 6499 6500 if (!IS_QMOD) { 6501 _SOC_IF_ERR_EXIT( 6502 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_rx_timestamp_offset_get(unit, port, 6503 PM4x10_INFO(pm_info), ts_offset)); 6504 } else { 6505 return (SOC_E_UNAVAIL); 6506 } 6507 6508 exit: 6509 SOC_FUNC_RETURN; 6510 } 6511 6512 int pm4x10_qtc_port_phy_intr_enable_set(int unit, int port, pm_info_t pm_info, uint32 intr_enable) 6513 { 6514 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6515 SOC_INIT_FUNC_DEFS; 6516 6517 PM4x10_QTC_QMOD_GET(pm_info); 6518 6519 if (!IS_QMOD) { 6520 _SOC_IF_ERR_EXIT( 6521 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_intr_enable_set(unit, port, 6522 PM4x10_INFO(pm_info), intr_enable)); 6523 } else { 6524 return (SOC_E_UNAVAIL); 6525 } 6526 6527 exit: 6528 SOC_FUNC_RETURN; 6529 } 6530 6531 int pm4x10_qtc_port_phy_intr_enable_get(int unit, int port, pm_info_t pm_info, uint32* intr_enable) 6532 { 6533 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6534 SOC_INIT_FUNC_DEFS; 6535 6536 PM4x10_QTC_QMOD_GET(pm_info); 6537 6538 if (!IS_QMOD) { 6539 _SOC_IF_ERR_EXIT( 6540 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_intr_enable_get(unit, port, 6541 PM4x10_INFO(pm_info), intr_enable)); 6542 } else { 6543 return (SOC_E_UNAVAIL); 6544 } 6545 6546 exit: 6547 SOC_FUNC_RETURN; 6548 } 6549 6550 int pm4x10_qtc_port_phy_intr_status_get(int unit, int port, pm_info_t pm_info, uint32* intr_status) 6551 { 6552 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6553 SOC_INIT_FUNC_DEFS; 6554 6555 PM4x10_QTC_QMOD_GET(pm_info); 6556 6557 if (!IS_QMOD) { 6558 _SOC_IF_ERR_EXIT( 6559 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_intr_status_get(unit, port, 6560 PM4x10_INFO(pm_info), intr_status)); 6561 } else { 6562 return (SOC_E_UNAVAIL); 6563 } 6564 6565 exit: 6566 SOC_FUNC_RETURN; 6567 } 6568 6569 int pm4x10_qtc_port_phy_intr_status_clear(int unit, int port, pm_info_t pm_info) 6570 { 6571 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6572 SOC_INIT_FUNC_DEFS; 6573 6574 PM4x10_QTC_QMOD_GET(pm_info); 6575 6576 if (!IS_QMOD) { 6577 _SOC_IF_ERR_EXIT( 6578 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_intr_status_clear(unit, port, 6579 PM4x10_INFO(pm_info))); 6580 } else { 6581 return (SOC_E_UNAVAIL); 6582 } 6583 6584 exit: 6585 SOC_FUNC_RETURN; 6586 } 6587 6588 int pm4x10_qtc_port_phy_timesync_do_sync(int unit, int port, pm_info_t pm_info) 6589 { 6590 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6591 SOC_INIT_FUNC_DEFS; 6592 6593 PM4x10_QTC_QMOD_GET(pm_info); 6594 6595 if (!IS_QMOD) { 6596 _SOC_IF_ERR_EXIT( 6597 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_timesync_do_sync(unit, port, 6598 PM4x10_INFO(pm_info))); 6599 } else { 6600 return (SOC_E_UNAVAIL); 6601 } 6602 6603 exit: 6604 SOC_FUNC_RETURN; 6605 } 6606 6607 int pm4x10_qtc_port_timesync_capture_timestamp_get(int unit, int port, pm_info_t pm_info, uint64* cap_ts) 6608 { 6609 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6610 SOC_INIT_FUNC_DEFS; 6611 6612 PM4x10_QTC_QMOD_GET(pm_info); 6613 6614 if (!IS_QMOD) { 6615 _SOC_IF_ERR_EXIT( 6616 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_capture_timestamp_get(unit, port, 6617 PM4x10_INFO(pm_info), cap_ts)); 6618 } else { 6619 return (SOC_E_UNAVAIL); 6620 } 6621 6622 exit: 6623 SOC_FUNC_RETURN; 6624 } 6625 6626 int pm4x10_qtc_port_timesync_heartbeat_timestamp_get(int unit, int port, pm_info_t pm_info, uint64* hb_ts) 6627 { 6628 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6629 SOC_INIT_FUNC_DEFS; 6630 6631 PM4x10_QTC_QMOD_GET(pm_info); 6632 6633 if (!IS_QMOD) { 6634 _SOC_IF_ERR_EXIT( 6635 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_heartbeat_timestamp_get(unit, port, 6636 PM4x10_INFO(pm_info), hb_ts)); 6637 } else { 6638 return (SOC_E_UNAVAIL); 6639 } 6640 6641 exit: 6642 SOC_FUNC_RETURN; 6643 } 6644 6645 int pm4x10_qtc_port_edc_config_set(int unit, int port, pm_info_t pm_info, const portmod_edc_config_t* config) 6646 { 6647 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6648 SOC_INIT_FUNC_DEFS; 6649 6650 PM4x10_QTC_QMOD_GET(pm_info); 6651 6652 if (!IS_QMOD) { 6653 _SOC_IF_ERR_EXIT( 6654 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_edc_config_set(unit, port, 6655 PM4x10_INFO(pm_info), config)); 6656 } else { 6657 return (SOC_E_UNAVAIL); 6658 } 6659 6660 exit: 6661 SOC_FUNC_RETURN; 6662 } 6663 6664 int pm4x10_qtc_port_edc_config_get(int unit, int port, pm_info_t pm_info, portmod_edc_config_t* config) 6665 { 6666 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6667 SOC_INIT_FUNC_DEFS; 6668 6669 PM4x10_QTC_QMOD_GET(pm_info); 6670 6671 if (!IS_QMOD) { 6672 _SOC_IF_ERR_EXIT( 6673 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_edc_config_get(unit, port, 6674 PM4x10_INFO(pm_info), config)); 6675 } else { 6676 return (SOC_E_UNAVAIL); 6677 } 6678 6679 exit: 6680 SOC_FUNC_RETURN; 6681 } 6682 6683 int pm4x10_qtc_port_interrupt_enable_set(int unit, int port, pm_info_t pm_info, int intr_type, uint32 val) 6684 { 6685 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6686 SOC_INIT_FUNC_DEFS; 6687 6688 PM4x10_QTC_QMOD_GET(pm_info); 6689 6690 if (!IS_QMOD) { 6691 _SOC_IF_ERR_EXIT( 6692 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_interrupt_enable_set(unit, port, 6693 PM4x10_INFO(pm_info), intr_type, val)); 6694 } else { 6695 return (SOC_E_UNAVAIL); 6696 } 6697 6698 exit: 6699 SOC_FUNC_RETURN; 6700 } 6701 6702 int pm4x10_qtc_port_interrupt_enable_get(int unit, int port, pm_info_t pm_info, int intr_type, uint32* val) 6703 { 6704 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6705 SOC_INIT_FUNC_DEFS; 6706 6707 PM4x10_QTC_QMOD_GET(pm_info); 6708 6709 if (!IS_QMOD) { 6710 _SOC_IF_ERR_EXIT( 6711 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_interrupt_enable_get(unit, port, 6712 PM4x10_INFO(pm_info), intr_type, val)); 6713 } else { 6714 return (SOC_E_UNAVAIL); 6715 } 6716 6717 exit: 6718 SOC_FUNC_RETURN; 6719 } 6720 6721 int pm4x10_qtc_port_interrupt_get(int unit, int port, pm_info_t pm_info, int intr_type, uint32* val) 6722 { 6723 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6724 SOC_INIT_FUNC_DEFS; 6725 6726 PM4x10_QTC_QMOD_GET(pm_info); 6727 6728 if (!IS_QMOD) { 6729 _SOC_IF_ERR_EXIT( 6730 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_interrupt_get(unit, port, 6731 PM4x10_INFO(pm_info), intr_type, val)); 6732 } else { 6733 return (SOC_E_UNAVAIL); 6734 } 6735 6736 exit: 6737 SOC_FUNC_RETURN; 6738 } 6739 6740 int pm4x10_qtc_port_interrupts_get(int unit, int port, pm_info_t pm_info, int arr_max_size, uint32* intr_arr, uint32* size) 6741 { 6742 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6743 SOC_INIT_FUNC_DEFS; 6744 6745 PM4x10_QTC_QMOD_GET(pm_info); 6746 6747 if (!IS_QMOD) { 6748 _SOC_IF_ERR_EXIT( 6749 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_interrupts_get(unit, port, 6750 PM4x10_INFO(pm_info), arr_max_size, intr_arr, size)); 6751 } else { 6752 return (SOC_E_UNAVAIL); 6753 } 6754 6755 exit: 6756 SOC_FUNC_RETURN; 6757 } 6758 6759 int pm4x10_qtc_port_failover_mode_set(int unit, int port, pm_info_t pm_info, phymod_failover_mode_t failover) 6760 { 6761 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6762 SOC_INIT_FUNC_DEFS; 6763 6764 PM4x10_QTC_QMOD_GET(pm_info); 6765 6766 if (!IS_QMOD) { 6767 _SOC_IF_ERR_EXIT( 6768 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_failover_mode_set(unit, port, 6769 PM4x10_INFO(pm_info), failover)); 6770 } else { 6771 return (SOC_E_UNAVAIL); 6772 } 6773 6774 exit: 6775 SOC_FUNC_RETURN; 6776 } 6777 6778 int pm4x10_qtc_port_failover_mode_get(int unit, int port, pm_info_t pm_info, phymod_failover_mode_t* failover) 6779 { 6780 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6781 SOC_INIT_FUNC_DEFS; 6782 6783 PM4x10_QTC_QMOD_GET(pm_info); 6784 6785 if (!IS_QMOD) { 6786 _SOC_IF_ERR_EXIT( 6787 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_failover_mode_get(unit, port, 6788 PM4x10_INFO(pm_info), failover)); 6789 } else { 6790 return (SOC_E_UNAVAIL); 6791 } 6792 6793 exit: 6794 SOC_FUNC_RETURN; 6795 } 6796 6797 int _pm4x10_qtc_port_warmboot_db_restore(int unit, int port, pm_info_t pm_info) 6798 { 6799 if (PM_4x10_QTC_INFO(pm_info)->warmboot_skip_db_restore) { 6800 return (SOC_E_NONE); 6801 } else { 6802 return (SOC_E_UNAVAIL); 6803 } 6804 6805 } 6806 6807 int pm4x10_qtc_port_warmboot_db_restore(int unit, int port, pm_info_t pm_info, const portmod_port_interface_config_t* intf_config, const portmod_port_init_config_t* init_config, phymod_operation_mode_t phy_op_mode) 6808 { 6809 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6810 SOC_INIT_FUNC_DEFS; 6811 6812 PM4x10_QTC_QMOD_GET(pm_info); 6813 6814 if (!IS_QMOD) { 6815 _SOC_IF_ERR_EXIT( 6816 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_warmboot_db_restore(unit, port, 6817 PM4x10_INFO(pm_info), intf_config, init_config, phy_op_mode)); 6818 } else { 6819 _SOC_IF_ERR_EXIT( 6820 _pm4x10_qtc_port_warmboot_db_restore(unit, port, pm_info)); 6821 } 6822 6823 exit: 6824 SOC_FUNC_RETURN; 6825 } 6826 6827 int pm4x10_qtc_port_phy_op_mode_get(int unit, int port, pm_info_t pm_info, phymod_operation_mode_t* val) 6828 { 6829 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6830 SOC_INIT_FUNC_DEFS; 6831 6832 PM4x10_QTC_QMOD_GET(pm_info); 6833 6834 if (!IS_QMOD) { 6835 _SOC_IF_ERR_EXIT( 6836 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_phy_op_mode_get(unit, port, 6837 PM4x10_INFO(pm_info), val)); 6838 } else { 6839 return (SOC_E_UNAVAIL); 6840 } 6841 6842 exit: 6843 SOC_FUNC_RETURN; 6844 } 6845 6846 int pm4x10_qtc_port_lane_map_set(int unit, int port, pm_info_t pm_info, uint32 flags, const phymod_lane_map_t* lane_map) 6847 { 6848 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6849 SOC_INIT_FUNC_DEFS; 6850 6851 PM4x10_QTC_QMOD_GET(pm_info); 6852 6853 if (!IS_QMOD) { 6854 _SOC_IF_ERR_EXIT( 6855 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_lane_map_set(unit, port, 6856 PM4x10_INFO(pm_info), flags, lane_map)); 6857 } else { 6858 return (SOC_E_UNAVAIL); 6859 } 6860 6861 exit: 6862 SOC_FUNC_RETURN; 6863 } 6864 6865 int pm4x10_qtc_port_lane_map_get(int unit, int port, pm_info_t pm_info, uint32 flags, phymod_lane_map_t* lane_map) 6866 { 6867 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6868 SOC_INIT_FUNC_DEFS; 6869 6870 PM4x10_QTC_QMOD_GET(pm_info); 6871 6872 if (!IS_QMOD) { 6873 _SOC_IF_ERR_EXIT( 6874 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_lane_map_get(unit, port, 6875 PM4x10_INFO(pm_info), flags, lane_map)); 6876 } else { 6877 return (SOC_E_UNAVAIL); 6878 } 6879 6880 exit: 6881 SOC_FUNC_RETURN; 6882 } 6883 6884 int pm4x10_qtc_port_polarity_set(int unit, int port, pm_info_t pm_info, const phymod_polarity_t* polarity) 6885 { 6886 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6887 SOC_INIT_FUNC_DEFS; 6888 6889 PM4x10_QTC_QMOD_GET(pm_info); 6890 6891 if (!IS_QMOD) { 6892 _SOC_IF_ERR_EXIT( 6893 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_polarity_set(unit, port, 6894 PM4x10_INFO(pm_info), polarity)); 6895 } else { 6896 return (SOC_E_UNAVAIL); 6897 } 6898 6899 exit: 6900 SOC_FUNC_RETURN; 6901 } 6902 6903 int pm4x10_qtc_port_polarity_get(int unit, int port, pm_info_t pm_info, phymod_polarity_t* polarity) 6904 { 6905 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6906 SOC_INIT_FUNC_DEFS; 6907 6908 PM4x10_QTC_QMOD_GET(pm_info); 6909 6910 if (!IS_QMOD) { 6911 _SOC_IF_ERR_EXIT( 6912 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_polarity_get(unit, port, 6913 PM4x10_INFO(pm_info), polarity)); 6914 } else { 6915 return (SOC_E_UNAVAIL); 6916 } 6917 6918 exit: 6919 SOC_FUNC_RETURN; 6920 } 6921 6922 int pm4x10_qtc_pm_is_in_pm12x10(int unit, pm_info_t pm_info, int* in_pm12x10) 6923 { 6924 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6925 SOC_INIT_FUNC_DEFS; 6926 6927 PM4x10_QTC_QMOD_GET(pm_info); 6928 6929 if (!IS_QMOD) { 6930 _SOC_IF_ERR_EXIT( 6931 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_pm_is_in_pm12x10(unit, 6932 PM4x10_INFO(pm_info), in_pm12x10)); 6933 } else { 6934 return (SOC_E_UNAVAIL); 6935 } 6936 6937 exit: 6938 SOC_FUNC_RETURN; 6939 } 6940 6941 int pm4x10_qtc_port_pll_div_get(int unit, int port, pm_info_t pm_info, const portmod_port_resources_t* port_resource, uint32_t* pll_div) 6942 { 6943 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6944 SOC_INIT_FUNC_DEFS; 6945 6946 PM4x10_QTC_QMOD_GET(pm_info); 6947 6948 if (!IS_QMOD) { 6949 _SOC_IF_ERR_EXIT( 6950 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_pll_div_get(unit, port, 6951 PM4x10_INFO(pm_info), port_resource, pll_div)); 6952 } else { 6953 *pll_div = (qtc_mode == portmodQtcModeUsxgmii) ? phymod_TSCE_PLL_DIV66 : phymod_TSCE_PLL_DIV64; 6954 } 6955 6956 exit: 6957 SOC_FUNC_RETURN; 6958 } 6959 6960 int pm4x10_qtc_port_master_set(int unit, int port, pm_info_t pm_info, int master_mode) 6961 { 6962 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6963 SOC_INIT_FUNC_DEFS; 6964 6965 PM4x10_QTC_QMOD_GET(pm_info); 6966 6967 if (!IS_QMOD) { 6968 _SOC_IF_ERR_EXIT( 6969 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_master_set(unit, port, 6970 PM4x10_INFO(pm_info), master_mode)); 6971 } else { 6972 _SOC_IF_ERR_EXIT(portmod_port_phychain_master_set(unit, port, pm_info, master_mode)); 6973 } 6974 6975 exit: 6976 SOC_FUNC_RETURN; 6977 } 6978 6979 int pm4x10_qtc_port_master_get(int unit, int port, pm_info_t pm_info, int* master_mode) 6980 { 6981 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 6982 SOC_INIT_FUNC_DEFS; 6983 6984 PM4x10_QTC_QMOD_GET(pm_info); 6985 6986 if (!IS_QMOD) { 6987 _SOC_IF_ERR_EXIT( 6988 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_master_get(unit, port, 6989 PM4x10_INFO(pm_info), master_mode)); 6990 } else { 6991 _SOC_IF_ERR_EXIT(portmod_port_phychain_master_get(unit, port, pm_info, master_mode)); 6992 } 6993 6994 exit: 6995 SOC_FUNC_RETURN; 6996 } 6997 6998 int pm4x10_qtc_preemption_control_set(int unit, int port, pm_info_t pm_info, portmod_preemption_control_t type, uint32 value) 6999 { 7000 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7001 SOC_INIT_FUNC_DEFS; 7002 7003 PM4x10_QTC_QMOD_GET(pm_info); 7004 7005 if (!IS_QMOD) { 7006 _SOC_IF_ERR_EXIT( 7007 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_preemption_control_set(unit, port, 7008 PM4x10_INFO(pm_info), type, value)); 7009 } else { 7010 return (SOC_E_UNAVAIL); 7011 } 7012 7013 exit: 7014 SOC_FUNC_RETURN; 7015 } 7016 7017 int pm4x10_qtc_preemption_control_get(int unit, int port, pm_info_t pm_info, portmod_preemption_control_t type, uint32* value) 7018 { 7019 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7020 SOC_INIT_FUNC_DEFS; 7021 7022 PM4x10_QTC_QMOD_GET(pm_info); 7023 7024 if (!IS_QMOD) { 7025 _SOC_IF_ERR_EXIT( 7026 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_preemption_control_get(unit, port, 7027 PM4x10_INFO(pm_info), type, value)); 7028 } else { 7029 return (SOC_E_UNAVAIL); 7030 } 7031 7032 exit: 7033 SOC_FUNC_RETURN; 7034 } 7035 7036 int pm4x10_qtc_preemption_tx_status_get(int unit, int port, pm_info_t pm_info, uint32* value) 7037 { 7038 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7039 SOC_INIT_FUNC_DEFS; 7040 7041 PM4x10_QTC_QMOD_GET(pm_info); 7042 7043 if (!IS_QMOD) { 7044 _SOC_IF_ERR_EXIT( 7045 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_preemption_tx_status_get(unit, port, 7046 PM4x10_INFO(pm_info), value)); 7047 } else { 7048 return (SOC_E_UNAVAIL); 7049 } 7050 7051 exit: 7052 SOC_FUNC_RETURN; 7053 } 7054 7055 int pm4x10_qtc_preemption_verify_status_get(int unit, int port, pm_info_t pm_info, portmod_preemption_verify_status_type_t type, uint32* value) 7056 { 7057 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7058 SOC_INIT_FUNC_DEFS; 7059 7060 PM4x10_QTC_QMOD_GET(pm_info); 7061 7062 if (!IS_QMOD) { 7063 _SOC_IF_ERR_EXIT( 7064 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_preemption_verify_status_get(unit, port, 7065 PM4x10_INFO(pm_info), type, value)); 7066 } else { 7067 return (SOC_E_UNAVAIL); 7068 } 7069 7070 exit: 7071 SOC_FUNC_RETURN; 7072 } 7073 7074 int pm4x10_qtc_preemption_rx_timeout_set(int unit, int port, pm_info_t pm_info, uint32 enable, uint32 timeout_cnt) 7075 { 7076 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7077 SOC_INIT_FUNC_DEFS; 7078 7079 PM4x10_QTC_QMOD_GET(pm_info); 7080 7081 if (!IS_QMOD) { 7082 _SOC_IF_ERR_EXIT( 7083 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_preemption_rx_timeout_set(unit, port, 7084 PM4x10_INFO(pm_info), enable, timeout_cnt)); 7085 } else { 7086 return (SOC_E_UNAVAIL); 7087 } 7088 7089 exit: 7090 SOC_FUNC_RETURN; 7091 } 7092 7093 int pm4x10_qtc_preemption_rx_timeout_get(int unit, int port, pm_info_t pm_info, uint32* enable, uint32* timeout_cnt) 7094 { 7095 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7096 SOC_INIT_FUNC_DEFS; 7097 7098 PM4x10_QTC_QMOD_GET(pm_info); 7099 7100 if (!IS_QMOD) { 7101 _SOC_IF_ERR_EXIT( 7102 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_preemption_rx_timeout_get(unit, port, 7103 PM4x10_INFO(pm_info), enable, timeout_cnt)); 7104 } else { 7105 return (SOC_E_UNAVAIL); 7106 } 7107 7108 exit: 7109 SOC_FUNC_RETURN; 7110 } 7111 7112 int pm4x10_qtc_port_lane_count_get(int unit, int port, pm_info_t pm_info, int line_side, int* num_lanes) 7113 { 7114 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7115 SOC_INIT_FUNC_DEFS; 7116 7117 PM4x10_QTC_QMOD_GET(pm_info); 7118 7119 if (!IS_QMOD) { 7120 _SOC_IF_ERR_EXIT( 7121 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_lane_count_get(unit, port, 7122 PM4x10_INFO(pm_info), line_side, num_lanes)); 7123 } else { 7124 return (SOC_E_UNAVAIL); 7125 } 7126 7127 exit: 7128 SOC_FUNC_RETURN; 7129 } 7130 7131 int pm4x10_qtc_port_timesync_tx_info_get(int unit, int port, pm_info_t pm_info, portmod_fifo_status_t* tx_info) 7132 { 7133 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7134 SOC_INIT_FUNC_DEFS; 7135 7136 PM4x10_QTC_QMOD_GET(pm_info); 7137 7138 if (!IS_QMOD) { 7139 _SOC_IF_ERR_EXIT( 7140 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_timesync_tx_info_get(unit, port, 7141 PM4x10_INFO(pm_info), tx_info)); 7142 } else { 7143 return (SOC_E_UNAVAIL); 7144 } 7145 7146 exit: 7147 SOC_FUNC_RETURN; 7148 } 7149 7150 int pm4x10_qtc_port_lane_mask_get(int unit, int port, pm_info_t pm_info, const portmod_access_get_params_t* params, int* lane_mask, int* xphy_id) 7151 { 7152 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7153 SOC_INIT_FUNC_DEFS; 7154 7155 PM4x10_QTC_QMOD_GET(pm_info); 7156 7157 if (!IS_QMOD) { 7158 _SOC_IF_ERR_EXIT( 7159 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_lane_mask_get(unit, port, 7160 PM4x10_INFO(pm_info), params, lane_mask, xphy_id)); 7161 } else { 7162 return (SOC_E_UNAVAIL); 7163 } 7164 7165 exit: 7166 SOC_FUNC_RETURN; 7167 } 7168 7169 int pm4x10_qtc_port_mac_timestamp_enable_set(int unit, int port, pm_info_t pm_info, int enable) 7170 { 7171 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7172 SOC_INIT_FUNC_DEFS; 7173 7174 PM4x10_QTC_QMOD_GET(pm_info); 7175 7176 if (!IS_QMOD) { 7177 _SOC_IF_ERR_EXIT( 7178 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mac_timestamp_enable_set(unit, port, 7179 PM4x10_INFO(pm_info), enable)); 7180 } else { 7181 return (SOC_E_UNAVAIL); 7182 } 7183 7184 exit: 7185 SOC_FUNC_RETURN; 7186 } 7187 7188 int pm4x10_qtc_port_mac_timestamp_enable_get(int unit, int port, pm_info_t pm_info, int* enable) 7189 { 7190 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7191 SOC_INIT_FUNC_DEFS; 7192 7193 PM4x10_QTC_QMOD_GET(pm_info); 7194 7195 if (!IS_QMOD) { 7196 _SOC_IF_ERR_EXIT( 7197 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_mac_timestamp_enable_get(unit, port, 7198 PM4x10_INFO(pm_info), enable)); 7199 } else { 7200 return (SOC_E_UNAVAIL); 7201 } 7202 7203 exit: 7204 SOC_FUNC_RETURN; 7205 } 7206 7207 int pm4x10_qtc_port_txpi_override_set(int unit, int port, pm_info_t pm_info, const portmod_txpi_override_t* override) 7208 { 7209 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7210 SOC_INIT_FUNC_DEFS; 7211 7212 PM4x10_QTC_QMOD_GET(pm_info); 7213 7214 if (!IS_QMOD) { 7215 _SOC_IF_ERR_EXIT( 7216 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_txpi_override_set(unit, port, 7217 PM4x10_INFO(pm_info), override)); 7218 } else { 7219 return (SOC_E_UNAVAIL); 7220 } 7221 7222 exit: 7223 SOC_FUNC_RETURN; 7224 } 7225 7226 int pm4x10_qtc_port_txpi_override_get(int unit, int port, pm_info_t pm_info, portmod_txpi_override_t* override) 7227 { 7228 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7229 SOC_INIT_FUNC_DEFS; 7230 7231 PM4x10_QTC_QMOD_GET(pm_info); 7232 7233 if (!IS_QMOD) { 7234 _SOC_IF_ERR_EXIT( 7235 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_txpi_override_get(unit, port, 7236 PM4x10_INFO(pm_info), override)); 7237 } else { 7238 return (SOC_E_UNAVAIL); 7239 } 7240 7241 exit: 7242 SOC_FUNC_RETURN; 7243 } 7244 7245 int pm4x10_qtc_port_txpi_sdm_data_get(int unit, int port, pm_info_t pm_info, int* value) 7246 { 7247 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7248 SOC_INIT_FUNC_DEFS; 7249 7250 PM4x10_QTC_QMOD_GET(pm_info); 7251 7252 if (!IS_QMOD) { 7253 _SOC_IF_ERR_EXIT( 7254 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_txpi_sdm_data_get(unit, port, 7255 PM4x10_INFO(pm_info), value)); 7256 } else { 7257 return (SOC_E_UNAVAIL); 7258 } 7259 7260 exit: 7261 SOC_FUNC_RETURN; 7262 } 7263 7264 STATIC 7265 int _pm4x10_qtc_port_synce_clk_ctrl_set(int unit, int port, pm_info_t pm_info, 7266 const portmod_port_synce_clk_ctrl_t* cfg) 7267 { 7268 phymod_synce_clk_ctrl_t phy_synce_cfg; 7269 phymod_phy_access_t phy_access[1+MAX_PHYN]; 7270 int nof_phys; 7271 SOC_INIT_FUNC_DEFS; 7272 7273 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, 7274 phy_access ,(1+MAX_PHYN), 7275 &nof_phys)); 7276 7277 phymod_synce_clk_ctrl_t_init(&phy_synce_cfg); 7278 phy_synce_cfg.stg0_mode = cfg->stg0_mode; 7279 phy_synce_cfg.stg1_mode = cfg->stg1_mode; 7280 phy_synce_cfg.sdm_val = cfg->sdm_val; 7281 7282 _SOC_IF_ERR_EXIT(phymod_phy_synce_clk_ctrl_set(&phy_access[0], phy_synce_cfg)); 7283 7284 exit: 7285 SOC_FUNC_RETURN; 7286 } 7287 7288 STATIC 7289 int _pm4x10_qtc_port_synce_clk_ctrl_get(int unit, int port, pm_info_t pm_info, 7290 portmod_port_synce_clk_ctrl_t* cfg) 7291 { 7292 phymod_synce_clk_ctrl_t phy_synce_cfg; 7293 phymod_phy_access_t phy_access[1+MAX_PHYN]; 7294 int nof_phys; 7295 SOC_INIT_FUNC_DEFS; 7296 7297 _SOC_IF_ERR_EXIT(portmod_port_chain_phy_access_get(unit, port, pm_info, 7298 phy_access ,(1+MAX_PHYN), 7299 &nof_phys)); 7300 7301 phymod_synce_clk_ctrl_t_init(&phy_synce_cfg); 7302 7303 _SOC_IF_ERR_EXIT(phymod_phy_synce_clk_ctrl_get(&phy_access[0], &phy_synce_cfg)); 7304 7305 cfg->stg0_mode = phy_synce_cfg.stg0_mode; 7306 cfg->stg1_mode = phy_synce_cfg.stg1_mode; 7307 cfg->sdm_val = phy_synce_cfg.sdm_val; 7308 7309 exit: 7310 SOC_FUNC_RETURN; 7311 } 7312 7313 int pm4x10_qtc_port_synce_clk_ctrl_set(int unit, int port, pm_info_t pm_info, 7314 const portmod_port_synce_clk_ctrl_t* cfg) 7315 { 7316 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7317 SOC_INIT_FUNC_DEFS; 7318 7319 PM4x10_QTC_QMOD_GET(pm_info); 7320 7321 if (!IS_QMOD) { 7322 _SOC_IF_ERR_EXIT( 7323 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_synce_clk_ctrl_set(unit, port, 7324 PM4x10_INFO(pm_info), cfg)); 7325 } else { 7326 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_synce_clk_ctrl_set(unit, port, pm_info, cfg)); 7327 } 7328 7329 exit: 7330 SOC_FUNC_RETURN; 7331 } 7332 7333 int pm4x10_qtc_port_synce_clk_ctrl_get(int unit, int port, pm_info_t pm_info, 7334 portmod_port_synce_clk_ctrl_t* cfg) 7335 { 7336 PM4x10_QTC_LOCAL_VARIABLE_DEFS; 7337 SOC_INIT_FUNC_DEFS; 7338 7339 PM4x10_QTC_QMOD_GET(pm_info); 7340 7341 if (!IS_QMOD) { 7342 _SOC_IF_ERR_EXIT( 7343 PM_DRIVER(PM4x10_INFO(pm_info))->f_portmod_port_synce_clk_ctrl_get(unit, port, 7344 PM4x10_INFO(pm_info), cfg)); 7345 } else { 7346 _SOC_IF_ERR_EXIT(_pm4x10_qtc_port_synce_clk_ctrl_get(unit, port, pm_info, cfg)); 7347 } 7348 7349 exit: 7350 SOC_FUNC_RETURN; 7351 } 7352 7353 #endif /* PORTMOD_PM4X10_QTC_SUPPORT */ 7354 7355 #undef _ERR_MSG_MODULE_NAME 7356