pm12x10.c (116685B)
1 2 /* 3 * 4 * 5 * 6 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 7 * 8 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 9 */ 10 11 #include <soc/drv.h> 12 #include <soc/types.h> 13 #include <soc/error.h> 14 #include <soc/phyreg.h> 15 #include <soc/portmod/portmod_internal.h> 16 #include <soc/portmod/portmod_common.h> 17 #include <soc/portmod/portmod.h> 18 #include <soc/portmod/portmod_dispatch.h> 19 #include <soc/portmod/pm4x10.h> 20 #include <soc/portmod/portmod_chain.h> 21 #include <soc/portmod/portmod_system.h> 22 23 24 #ifdef _ERR_MSG_MODULE_NAME 25 #error "_ERR_MSG_MODULE_NAME redefined" 26 #endif 27 #define _ERR_MSG_MODULE_NAME BSL_LS_SOC_PORT 28 29 #ifdef PORTMOD_PM12X10_SUPPORT 30 31 static int pm12x10_core_seq[] = {0,2,1}; 32 static int pm12x10_invert_core_seq[] = {0,2,1}; /* index by core id, output for loop index */ 33 34 #define PM_12x10_INFO(pm_info) ((pm_info)->pm_data.pm12x10_db) 35 #define PM_4X25_INFO(pm_info) (PM_12x10_INFO(pm_info)->pm4x25_info) 36 #define PM_4X10_INFO(pm_info, i) (PM_12x10_INFO(pm_info)->pm4x10_info[pm12x10_core_seq[i]]) 37 #define PM_4X25_DRIVER(pm_info) PM_DRIVER(PM_4X25_INFO(pm_info)) 38 #define PM_4X10_DRIVER(pm_info, i) PM_DRIVER(PM_4X10_INFO(pm_info, pm12x10_core_seq[i])) 39 40 41 #define TOP_BLK_ID_OFFSET (4) 42 43 #define PM12x10_INTERNAL_4x10_CNT (3) 44 45 struct pm12x10_s{ 46 int blk_id; 47 pm_info_t pm4x25_info; 48 pm_info_t pm4x10_info[PM12x10_INTERNAL_4x10_CNT]; 49 portmod_pbmp_t phys; 50 uint32 external_top_mode; 51 int refclk_source; 52 portmod_link_recovery_t link_recovery; 53 }; 54 55 STATIC 56 int 57 pm12x10_quad0_default_bus_write(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t val) 58 { 59 return portmod_common_phy_sbus_reg_write(CXX_CXXPORT_WC_UCMEM_DATA_0m, user_acc, core_addr, reg_addr, val); 60 } 61 62 STATIC 63 int 64 pm12x10_quad0_default_bus_read(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t *val) 65 { 66 return portmod_common_phy_sbus_reg_read(CXX_CXXPORT_WC_UCMEM_DATA_0m, user_acc, core_addr, reg_addr, val); 67 } 68 69 phymod_bus_t pm4x10_quad0_default_bus = { 70 "PM12x10 Quad0 Bus", 71 pm12x10_quad0_default_bus_read, 72 pm12x10_quad0_default_bus_write, 73 NULL, 74 portmod_common_mutex_take, 75 portmod_common_mutex_give, 76 NULL, 77 NULL, 78 PHYMOD_BUS_CAP_WR_MODIFY | PHYMOD_BUS_CAP_LANE_CTRL 79 }; 80 81 STATIC 82 int 83 pm12x10_quad1_default_bus_write(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t val) 84 { 85 return portmod_common_phy_sbus_reg_write(CXX_CXXPORT_WC_UCMEM_DATA_1m, user_acc, core_addr, reg_addr, val); 86 } 87 88 STATIC 89 int 90 pm12x10_quad1_default_bus_read(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t *val) 91 { 92 return portmod_common_phy_sbus_reg_read(CXX_CXXPORT_WC_UCMEM_DATA_1m, user_acc, core_addr, reg_addr, val); 93 } 94 95 phymod_bus_t pm4x10_quad1_default_bus = { 96 "PM12x10 Quad1 Bus", 97 pm12x10_quad1_default_bus_read, 98 pm12x10_quad1_default_bus_write, 99 NULL, 100 portmod_common_mutex_take, 101 portmod_common_mutex_give, 102 NULL, 103 NULL, 104 PHYMOD_BUS_CAP_WR_MODIFY | PHYMOD_BUS_CAP_LANE_CTRL 105 }; 106 107 STATIC 108 int 109 pm12x10_quad2_default_bus_write(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t val) 110 { 111 return portmod_common_phy_sbus_reg_write(CXX_CXXPORT_WC_UCMEM_DATA_2m, user_acc, core_addr, reg_addr, val); 112 } 113 114 STATIC 115 int 116 pm12x10_quad2_default_bus_read(void* user_acc, uint32_t core_addr, uint32_t reg_addr, uint32_t *val) 117 { 118 return portmod_common_phy_sbus_reg_read(CXX_CXXPORT_WC_UCMEM_DATA_2m, user_acc, core_addr, reg_addr, val); 119 } 120 121 phymod_bus_t pm4x10_quad2_default_bus = { 122 "PM12x10 Quad2 Bus", 123 pm12x10_quad2_default_bus_read, 124 pm12x10_quad2_default_bus_write, 125 NULL, 126 portmod_common_mutex_take, 127 portmod_common_mutex_give, 128 NULL, 129 NULL, 130 PHYMOD_BUS_CAP_WR_MODIFY | PHYMOD_BUS_CAP_LANE_CTRL 131 }; 132 133 STATIC portmod_ucode_buf_t pm12x10_ucode_buf[SOC_MAX_NUM_DEVICES] = {{NULL, 0}}; 134 135 STATIC int 136 pm4x10_quad0_default_fw_loader(const phymod_core_access_t* core, uint32_t length, const uint8_t* data) 137 { 138 int rv; 139 portmod_default_user_access_t *user_data; 140 int unit = ((portmod_default_user_access_t*)core->access.user_acc)->unit; 141 SOC_INIT_FUNC_DEFS; 142 143 user_data = (portmod_default_user_access_t*)core->access.user_acc; 144 145 rv = portmod_firmware_set(unit, 146 user_data->blk_id, 147 data, 148 length, 149 portmod_ucode_buf_order_reversed, 150 0, 151 &(pm12x10_ucode_buf[unit]), 152 NULL, 153 CXX_CXXPORT_WC_UCMEM_DATA_0m, 154 CXX_CXXPORT_WC_UCMEM_CTRL_0r); 155 _SOC_IF_ERR_EXIT(rv); 156 157 exit: 158 SOC_FUNC_RETURN; 159 } 160 161 STATIC int 162 pm4x10_quad1_default_fw_loader(const phymod_core_access_t* core, uint32_t length, const uint8_t* data) 163 { 164 int rv; 165 portmod_default_user_access_t *user_data; 166 int unit = ((portmod_default_user_access_t*)core->access.user_acc)->unit; 167 SOC_INIT_FUNC_DEFS; 168 169 user_data = (portmod_default_user_access_t*)core->access.user_acc; 170 171 rv = portmod_firmware_set(unit, 172 user_data->blk_id, 173 data, 174 length, 175 portmod_ucode_buf_order_reversed, 176 0, 177 &(pm12x10_ucode_buf[unit]), 178 NULL, 179 CXX_CXXPORT_WC_UCMEM_DATA_1m, 180 CXX_CXXPORT_WC_UCMEM_CTRL_1r); 181 _SOC_IF_ERR_EXIT(rv); 182 183 exit: 184 SOC_FUNC_RETURN; 185 } 186 187 STATIC int 188 pm4x10_quad2_default_fw_loader(const phymod_core_access_t* core, uint32_t length, const uint8_t* data) 189 { 190 int rv; 191 portmod_default_user_access_t *user_data; 192 int unit = ((portmod_default_user_access_t*)core->access.user_acc)->unit; 193 SOC_INIT_FUNC_DEFS; 194 195 user_data = (portmod_default_user_access_t*)core->access.user_acc; 196 197 rv = portmod_firmware_set(unit, 198 user_data->blk_id, 199 data, 200 length, 201 portmod_ucode_buf_order_reversed, 202 0, 203 &(pm12x10_ucode_buf[unit]), 204 NULL, 205 CXX_CXXPORT_WC_UCMEM_DATA_2m, 206 CXX_CXXPORT_WC_UCMEM_CTRL_2r); 207 _SOC_IF_ERR_EXIT(rv); 208 209 exit: 210 SOC_FUNC_RETURN; 211 } 212 213 214 215 int pm12x10_pm_interface_type_is_supported(int unit, soc_port_if_t interface, int* is_supported) 216 { 217 *is_supported = FALSE; 218 219 if((interface == SOC_PORT_IF_CAUI) || (interface == SOC_PORT_IF_CR10) || (interface == SOC_PORT_IF_SR10)) { 220 *is_supported = TRUE; 221 } 222 return SOC_E_NONE; 223 } 224 225 int pm12x10_pm_destroy(int unit, pm_info_t pm_info) 226 { 227 if(pm_info->pm_data.pm12x10_db != NULL){ 228 sal_free(pm_info->pm_data.pm12x10_db); 229 pm_info->pm_data.pm12x10_db = NULL; 230 } 231 232 /* free pm12x10_ucode_buf */ 233 if(pm12x10_ucode_buf[unit].ucode_dma_buf != NULL){ 234 portmod_sys_dma_free(unit, pm12x10_ucode_buf[unit].ucode_dma_buf); 235 pm12x10_ucode_buf[unit].ucode_dma_buf = NULL; 236 } 237 pm12x10_ucode_buf[unit].ucode_alloc_size = 0; 238 239 return SOC_E_NONE; 240 } 241 242 243 int pm12x10_pm_init(int unit, const portmod_pm_create_info_internal_t* pm_add_info, 244 int wb_buffer_index, pm_info_t pm_info) 245 { 246 pm12x10_t pm12x10_data = NULL; 247 int nof_phys = 0, core; 248 portmod_bus_update_t bupdate; 249 SOC_INIT_FUNC_DEFS; 250 251 PORTMOD_PBMP_COUNT(pm_add_info->phys, nof_phys); 252 if(nof_phys != 12){ 253 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("number of phys should be 12"))); 254 } 255 pm12x10_data = sal_alloc(sizeof(*(pm_info->pm_data.pm12x10_db)), "specific_db"); 256 SOC_NULL_CHECK(pm12x10_data); 257 258 /*PM12x10 Top*/ 259 pm_info->type = pm_add_info->type; 260 pm_info->unit = unit; 261 pm_info->wb_buffer_id = wb_buffer_index; 262 263 pm_info->pm_data.pm12x10_db = pm12x10_data; 264 pm_info->pm_data.pm12x10_db->blk_id = pm_add_info->pm_specific_info.pm12x10.blk_id; 265 PORTMOD_PBMP_ASSIGN(pm_info->pm_data.pm12x10_db->phys, pm_add_info->phys); 266 267 for (core = 0; core < PM12x10_INTERNAL_4x10_CNT; core++) { 268 pm_info->pm_data.pm12x10_db->pm4x10_info[core] = 269 pm_add_info->pm_specific_info.pm12x10.pm4x10[core]; 270 } 271 272 pm_info->pm_data.pm12x10_db->link_recovery.enabled = TRUE; 273 pm_info->pm_data.pm12x10_db->link_recovery.tick_cnt = 0; 274 pm_info->pm_data.pm12x10_db->link_recovery.state = PORTMOD_LINK_RECOVERY_STATE_WAIT_FOR_LINK; 275 pm_info->pm_data.pm12x10_db->pm4x25_info = pm_add_info->pm_specific_info.pm12x10.pm4x25; 276 pm_info->pm_data.pm12x10_db->refclk_source = pm_add_info->pm_specific_info.pm12x10.refclk_source; 277 pm_info->pm_data.pm12x10_db->external_top_mode = PORTMOD_PM12x10_F_EXTERNAL_TOP_MODE_GET(pm_add_info->pm_specific_info.pm12x10.flags); 278 279 if(!pm_info->pm_data.pm12x10_db->external_top_mode) { 280 /* Update Quad 0 */ 281 bupdate.blk_id = pm_info->pm_data.pm12x10_db->blk_id; 282 bupdate.default_bus = &pm4x10_quad0_default_bus; 283 bupdate.external_fw_loader = pm4x10_quad0_default_fw_loader; 284 bupdate.user_acc = NULL; /*use default user_acc */ 285 _SOC_IF_ERR_EXIT(pm4x10_default_bus_update(unit, PM_12x10_INFO(pm_info)->pm4x10_info[0], &bupdate)); 286 287 /* Update Quad 1 */ 288 bupdate.default_bus = &pm4x10_quad1_default_bus; 289 bupdate.external_fw_loader = pm4x10_quad1_default_fw_loader; 290 _SOC_IF_ERR_EXIT(pm4x10_default_bus_update(unit, PM_12x10_INFO(pm_info)->pm4x10_info[1], &bupdate)); 291 292 /* Update Quad 2 */ 293 bupdate.default_bus = &pm4x10_quad2_default_bus; 294 bupdate.external_fw_loader = pm4x10_quad2_default_fw_loader; 295 _SOC_IF_ERR_EXIT(pm4x10_default_bus_update(unit, PM_12x10_INFO(pm_info)->pm4x10_info[2], &bupdate)); 296 297 } 298 299 exit: 300 if(SOC_FUNC_ERROR){ 301 pm12x10_pm_destroy(unit, pm_info); 302 } 303 SOC_FUNC_RETURN; 304 } 305 306 int pm12x10_pm_core_info_get(int unit, pm_info_t pm_info, int phyn, portmod_pm_core_info_t* core_info) 307 { 308 /*no need*/ 309 return SOC_E_NONE; 310 } 311 312 313 /*int _pm12x10_lane_map_validate(int unit, int port, )*/ 314 315 316 int pm12x10_port_attach (int unit, int port, pm_info_t pm_info, 317 const portmod_port_add_info_t* add_info) 318 { 319 portmod_port_add_info_t lcl_add_info = *add_info; 320 uint32 nof_lanes = 0; 321 int i = 0; 322 int rv = 0; 323 int core_num=0; 324 SOC_INIT_FUNC_DEFS; 325 326 PORTMOD_PBMP_COUNT(add_info->phys, nof_lanes); 327 328 if (nof_lanes == 10) { 329 330 } else if(nof_lanes != 12){ 331 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("number of lanes should be 10 or 12"))); 332 } 333 334 lcl_add_info.interface_config.flags |= PHYMOD_INTF_F_SET_CORE_MAP_MODE; 335 336 for(i = 0 ; i < 3 ; i++) 337 { 338 /* do it before pm is active only - so skip in the second pass of multi stage init */ 339 if (PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_GET(add_info) || (lcl_add_info.flags == 0)) { 340 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_pm_bypass_set(unit, PM_4X10_INFO(pm_info,i), 1); 341 _SOC_IF_ERR_EXIT(rv); 342 } 343 344 /* If TSC12 first core is odd number, the mode between 244 and 442 need to be flip. */ 345 346 rv = PM_4X10_DRIVER(pm_info, 0)->f_portmod_port_core_num_get(unit, port, 347 PM_4X10_INFO(pm_info,0), &core_num); 348 _SOC_IF_ERR_EXIT(rv); 349 350 if(core_num%2) { 351 lcl_add_info.interface_config.flags |= PHYMOD_INTF_F_CORE_MAP_MODE_FLIP; 352 } 353 if (i) { 354 lcl_add_info.flags |= PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP; 355 } 356 357 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_attach(unit, port, PM_4X10_INFO(pm_info,i), &lcl_add_info); 358 _SOC_IF_ERR_EXIT(rv); 359 } 360 361 if (PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info) || (add_info->flags == 0)) { 362 363 364 for(i = 0 ; i < 3 ; i++) 365 { 366 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_interface_config_set(unit, 367 port, PM_4X10_INFO(pm_info,i), 368 &add_info->interface_config, 369 PORTMOD_INIT_F_ALL_PHYS); 370 _SOC_IF_ERR_EXIT(rv); 371 } 372 373 if(!pm_info->pm_data.pm12x10_db->external_top_mode) { 374 rv = WRITE_CXX_CXXPORT_MODE_REGr(unit, port, 1); 375 _SOC_IF_ERR_EXIT(rv); 376 } 377 } 378 379 /* CPORT is not connected to any PHY.., so clear the phy information before adding it */ 380 lcl_add_info = *add_info; 381 PORTMOD_PBMP_CLEAR(lcl_add_info.phys); 382 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_attach(unit, port, PM_4X25_INFO(pm_info), &lcl_add_info); 383 _SOC_IF_ERR_EXIT(rv); 384 385 exit: 386 SOC_FUNC_RETURN; 387 } 388 389 int pm12x10_port_detach(int unit, int port, pm_info_t pm_info) 390 { 391 int rv = 0; 392 int i = 0; 393 SOC_INIT_FUNC_DEFS; 394 395 for(i = 0 ; i < 3; i++){ 396 _SOC_IF_ERR_EXIT(PM_4X10_DRIVER(pm_info, i)->f_portmod_port_detach(unit, 397 port, PM_4X10_INFO(pm_info, i))); 398 } 399 400 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_detach(unit, port, PM_4X25_INFO(pm_info)); 401 _SOC_IF_ERR_EXIT(rv); 402 403 404 if(!pm_info->pm_data.pm12x10_db->external_top_mode) { 405 rv = WRITE_CXX_CXXPORT_MODE_REGr(unit, port, 0); 406 _SOC_IF_ERR_EXIT(rv); 407 } 408 409 for(i = 0 ; i < 3 ; i++) 410 { 411 PM_4X10_DRIVER(pm_info, i)->f_portmod_pm_bypass_set(unit, PM_4X10_INFO(pm_info,i), 0); 412 } 413 414 exit: 415 SOC_FUNC_RETURN; 416 } 417 418 419 int pm12x10_port_replace(int unit, int port, pm_info_t pm_info, int new_port) 420 { 421 int rv = 0; 422 int i = 0; 423 SOC_INIT_FUNC_DEFS; 424 425 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_replace(unit, port, PM_4X25_INFO(pm_info), new_port); 426 _SOC_IF_ERR_EXIT(rv); 427 428 for(i = 0 ; i < 3 ; i++) 429 { 430 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_replace(unit, port, PM_4X10_INFO(pm_info,i), new_port); 431 _SOC_IF_ERR_EXIT(rv); 432 } 433 434 exit: 435 SOC_FUNC_RETURN; 436 437 } 438 439 int pm12x10_port_enable_set (int unit, int port, pm_info_t pm_info, 440 int flags, int enable) 441 { 442 int rv = 0; 443 int i = 0; 444 SOC_INIT_FUNC_DEFS; 445 446 if(enable) { 447 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_enable_set(unit, port, 448 PM_4X25_INFO(pm_info), flags, 1); 449 _SOC_IF_ERR_EXIT(rv); 450 for(i = 0 ; i < 3; i++) { 451 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_enable_set(unit, 452 port, PM_4X10_INFO(pm_info, i), flags, 2); 453 _SOC_IF_ERR_EXIT(rv); 454 } 455 } else { 456 int flags_temp = flags; 457 458 if (flags) { /* make sure MAC is also disabled (in case it was enabled) */ 459 PORTMOD_PORT_ENABLE_MAC_SET(flags_temp); 460 } 461 462 for(i = 0 ; i < 3; i++){ 463 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_enable_set(unit, 464 port, PM_4X10_INFO(pm_info, i), flags_temp, 0); 465 _SOC_IF_ERR_EXIT(rv); 466 } 467 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_enable_set(unit, port, 468 PM_4X25_INFO(pm_info), flags, 0); 469 _SOC_IF_ERR_EXIT(rv); 470 } 471 472 exit: 473 SOC_FUNC_RETURN; 474 } 475 476 477 int pm12x10_port_enable_get (int unit, int port, pm_info_t pm_info, 478 int flags, int* enable) 479 { 480 int rv = 0; 481 SOC_INIT_FUNC_DEFS; 482 483 *enable = 0; 484 if (PORTMOD_PORT_ENABLE_PHY_GET(flags)) { 485 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_enable_get(unit, 486 port, PM_4X10_INFO(pm_info, 2), flags, enable); 487 } else { 488 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_enable_get(unit, 489 port, PM_4X25_INFO(pm_info), flags, enable); 490 } 491 _SOC_IF_ERR_EXIT(rv); 492 493 exit: 494 SOC_FUNC_RETURN; 495 } 496 497 STATIC 498 int _pm12x10_internal_if_cfg_set (int unit, int port, pm_info_t pm_info, 499 const portmod_port_interface_config_t* config, 500 int phy_init_flags) 501 { 502 int i =0, rv=0; 503 504 for(i = 0 ; !rv && (i < 3) ; i++) 505 { 506 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_interface_config_set( 507 unit, port, PM_4X10_INFO(pm_info, i), config, 508 phy_init_flags); 509 } 510 return (rv); 511 } 512 513 514 /** 515 * if_cfg->flags |= PHYMOD_INTF_F_SET_SPD_DISABLE; 516 * if_cfg->flags ^= PHYMOD_INTF_F_SET_SPD_DISABLE; 517 * 518 * if_cfg->flags |= PHYMOD_INTF_F_SET_CORE_MAP_MODE; 519 * if_cfg->flags ^= PHYMOD_INTF_F_SET_CORE_MAP_MODE; 520 * if(core_num%2) { 521 * my_config->flags |= PHYMOD_INTF_F_CORE_MAP_MODE_FLIP; 522 * } 523 * 524 * if_cfg->flags |= PHYMOD_INTF_F_SET_SPD_NO_TRIGGER ; 525 * if_cfg->flags ^= PHYMOD_INTF_F_SET_SPD_NO_TRIGGER ; 526 * 527 * if_cfg->flags |= PHYMOD_INTF_F_SET_SPD_TRIGGER; 528 * if_cfg->flags ^= PHYMOD_INTF_F_SET_SPD_TRIGGER; 529 */ 530 int pm12x10_port_interface_config_set (int unit, int port, pm_info_t pm_info, 531 const portmod_port_interface_config_t* config, 532 int phy_init_flags) 533 { 534 int rv = 0; 535 portmod_port_interface_config_t* my_config = (portmod_port_interface_config_t*)config; 536 int core_num; 537 SOC_INIT_FUNC_DEFS; 538 539 if (config->flags & PHYMOD_INTF_F_INTF_PARAM_SET_ONLY) { 540 return (_pm12x10_internal_if_cfg_set (unit, port, pm_info, my_config, phy_init_flags)); 541 } 542 543 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_interface_config_set (unit, 544 port, PM_4X25_INFO(pm_info), config, phy_init_flags); 545 _SOC_IF_ERR_EXIT(rv); 546 547 548 /* speed disable */ 549 my_config->flags |= PHYMOD_INTF_F_SET_SPD_DISABLE; 550 rv = _pm12x10_internal_if_cfg_set (unit, port, pm_info, my_config, 551 PORTMOD_INIT_F_INTERNAL_SERDES_ONLY); 552 _SOC_IF_ERR_EXIT(rv); 553 554 /* core map mode set */ 555 my_config->flags ^= PHYMOD_INTF_F_SET_SPD_DISABLE; 556 my_config->flags |= PHYMOD_INTF_F_SET_CORE_MAP_MODE; 557 558 rv = PM_4X10_DRIVER(pm_info, 0)->f_portmod_port_core_num_get(unit, port, 559 PM_4X10_INFO(pm_info,0), &core_num); 560 _SOC_IF_ERR_EXIT(rv); 561 562 if(core_num%2) { 563 my_config->flags |= PHYMOD_INTF_F_CORE_MAP_MODE_FLIP; 564 } 565 566 rv = _pm12x10_internal_if_cfg_set (unit, port, pm_info, my_config, 567 PORTMOD_INIT_F_INTERNAL_SERDES_ONLY); 568 _SOC_IF_ERR_EXIT(rv); 569 570 if (my_config->flags & PHYMOD_INTF_F_CORE_MAP_MODE_FLIP) 571 my_config->flags ^= PHYMOD_INTF_F_CORE_MAP_MODE_FLIP; 572 573 /* Speed set - no trigger */ 574 my_config->flags ^= PHYMOD_INTF_F_SET_CORE_MAP_MODE; 575 my_config->flags |= PHYMOD_INTF_F_SET_SPD_NO_TRIGGER ; 576 577 rv = _pm12x10_internal_if_cfg_set (unit, port, pm_info, my_config, 578 PORTMOD_INIT_F_INTERNAL_SERDES_ONLY); 579 _SOC_IF_ERR_EXIT(rv); 580 581 /* Speed trigger */ 582 my_config->flags ^= PHYMOD_INTF_F_SET_SPD_NO_TRIGGER ; 583 my_config->flags |= PHYMOD_INTF_F_SET_SPD_TRIGGER; 584 585 rv = _pm12x10_internal_if_cfg_set (unit, port, pm_info, my_config, phy_init_flags); 586 _SOC_IF_ERR_EXIT(rv); 587 588 my_config->flags ^= PHYMOD_INTF_F_SET_SPD_TRIGGER; 589 590 exit: 591 SOC_FUNC_RETURN; 592 } 593 594 595 int pm12x10_port_interface_config_get (int unit, int port, pm_info_t pm_info, 596 portmod_port_interface_config_t* config, int phy_init_flags) 597 { 598 int rv = 0, flags; 599 SOC_INIT_FUNC_DEFS; 600 601 /* Get Phy information from pm4x10 (Phy) */ 602 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_interface_config_get( 603 unit, port, PM_4X10_INFO(pm_info, 2), config, phy_init_flags); 604 _SOC_IF_ERR_EXIT(rv); 605 606 /* Get mac information from pm4x25 (CLMAC) */ 607 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_encap_get( unit, port, 608 PM_4X25_INFO(pm_info), &flags, &config->encap_mode); 609 _SOC_IF_ERR_EXIT(rv); 610 611 exit: 612 SOC_FUNC_RETURN; 613 } 614 615 int pm12x10_port_default_interface_get(int unit, int port, pm_info_t pm_info, 616 const portmod_port_interface_config_t* config, 617 soc_port_if_t* interface) 618 { 619 SOC_INIT_FUNC_DEFS; 620 621 _SOC_IF_ERR_EXIT 622 (PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_default_interface_get 623 (unit, port, PM_4X10_INFO(pm_info, 2), config, interface)); 624 625 exit: 626 SOC_FUNC_RETURN; 627 } 628 629 int pm12x10_port_loopback_set(int unit, int port, pm_info_t pm_info, 630 portmod_loopback_mode_t loopback_type, int enable) 631 { 632 int rv = 0, i; 633 portmod_port_interface_config_t config; 634 SOC_INIT_FUNC_DEFS; 635 636 switch(loopback_type) { 637 case portmodLoopbackMacOuter: 638 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_loopback_set (unit, port, 639 PM_4X25_INFO(pm_info), loopback_type, enable); 640 _SOC_IF_ERR_EXIT(rv); 641 break; 642 643 case portmodLoopbackPhyGloopPMD: 644 case portmodLoopbackPhyRloopPMD: /*slide*/ 645 case portmodLoopbackPhyGloopPCS: /*slide*/ 646 for (i = 0; i < 3; i++) { 647 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_loopback_set( 648 unit, port, PM_4X10_INFO(pm_info, i), loopback_type, enable); 649 _SOC_IF_ERR_EXIT(rv); 650 } 651 /* add the speed trigger */ 652 /* Get Phy information from pm4x10 (Phy) */ 653 rv = portmod_port_interface_config_t_init(unit, &config); 654 _SOC_IF_ERR_EXIT(rv); 655 656 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_interface_config_get( 657 unit, port, PM_4X10_INFO(pm_info, 2), &config, PORTMOD_INIT_F_INTERNAL_SERDES_ONLY); 658 _SOC_IF_ERR_EXIT(rv); 659 660 /* Set SPD_ID, intf and lanes on all pm4x10's without triggering speed change */ 661 config.flags = PHYMOD_INTF_F_SET_SPD_NO_TRIGGER ; 662 rv = _pm12x10_internal_if_cfg_set (unit, port, pm_info, &config, PORTMOD_INIT_F_INTERNAL_SERDES_ONLY); 663 _SOC_IF_ERR_EXIT(rv); 664 665 /* Now trigger the speed change (after all pm4x10's are configured correctly) */ 666 config.flags = PHYMOD_INTF_F_SET_SPD_TRIGGER; 667 rv = _pm12x10_internal_if_cfg_set (unit, port, pm_info, &config, PORTMOD_INIT_F_INTERNAL_SERDES_ONLY); 668 _SOC_IF_ERR_EXIT(rv); 669 670 break; 671 case portmodLoopbackPhyRloopPCS: 672 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Rloop PCS is not supported."))); 673 break; 674 default: 675 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, 676 (_SOC_MSG("unsupported loopback type %d"), loopback_type)); 677 } 678 679 if (enable) 680 _SOC_IF_ERR_EXIT(PM_4X25_DRIVER(pm_info)->f_portmod_port_lag_failover_status_toggle(unit, port, PM_4X25_INFO(pm_info))); 681 682 exit: 683 SOC_FUNC_RETURN; 684 } 685 686 687 int pm12x10_port_loopback_get(int unit, int port, pm_info_t pm_info, 688 portmod_loopback_mode_t loopback_type, int* enable) 689 { 690 int rv = 0; 691 SOC_INIT_FUNC_DEFS; 692 693 switch(loopback_type) { 694 case portmodLoopbackMacOuter: 695 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_loopback_get(unit, port, 696 PM_4X25_INFO(pm_info), loopback_type, enable); 697 _SOC_IF_ERR_EXIT(rv); 698 break; 699 700 case portmodLoopbackPhyGloopPMD: 701 case portmodLoopbackPhyRloopPMD: /*slide*/ 702 case portmodLoopbackPhyGloopPCS: /*slide*/ 703 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_loopback_get(unit, port, 704 PM_4X10_INFO(pm_info, 2), loopback_type, enable); 705 _SOC_IF_ERR_EXIT(rv); 706 break; 707 case portmodLoopbackPhyRloopPCS: 708 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Rloop PCS is not supported."))); 709 break; 710 default: 711 _SOC_EXIT_WITH_ERR(SOC_E_UNAVAIL, ( 712 _SOC_MSG("unsupported loopback type %d"), loopback_type)); 713 } 714 715 exit: 716 SOC_FUNC_RETURN; 717 } 718 719 720 int pm12x10_port_ability_local_get (int unit, int port, pm_info_t pm_info, int phy_init_flags, 721 portmod_port_ability_t* ability) 722 { 723 int rv = 0; 724 SOC_INIT_FUNC_DEFS; 725 /* CHECK IF WE SHOULD USE 4X25 or 4X10 726 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_ability_local_get(unit, port, 727 PM_4X25_INFO(pm_info), ability); */ 728 729 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_ability_local_get ( 730 unit, port, PM_4X10_INFO(pm_info,2), phy_init_flags, ability); 731 _SOC_IF_ERR_EXIT(rv); 732 733 exit: 734 SOC_FUNC_RETURN; 735 } 736 737 int pm12x10_port_autoneg_set(int unit, int port, pm_info_t pm_info, int phy_init_flags, 738 const phymod_autoneg_control_t* an) 739 { 740 int rv = 0; 741 int i = 0, port_fallback_lane, core_seq; 742 743 SOC_INIT_FUNC_DEFS; 744 if (an->enable) { 745 ((phymod_autoneg_control_t*)an)->num_lane_adv = 10 ; 746 ((phymod_autoneg_control_t*)an)->flags |= PHYMOD_AN_F_SET_PRIOR_ENABLE; 747 for ( i = 0 ; i < 3 ; i++) 748 { 749 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_autoneg_set( 750 unit, port, PM_4X10_INFO(pm_info, i), phy_init_flags, an); 751 _SOC_IF_ERR_EXIT(rv); 752 } 753 ((phymod_autoneg_control_t*)an)->flags &= ~PHYMOD_AN_F_SET_PRIOR_ENABLE; 754 } 755 756 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_fallback_lane_get( 757 unit, port, PM_4X10_INFO(pm_info, 2), &port_fallback_lane); 758 _SOC_IF_ERR_EXIT(rv); 759 760 if(port_fallback_lane>2||port_fallback_lane<0) { 761 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, (_SOC_MSG("port_fallback_lane runaway"))); 762 } 763 core_seq = pm12x10_invert_core_seq[port_fallback_lane] ; 764 765 rv = PM_4X10_DRIVER(pm_info, core_seq)->f_portmod_port_autoneg_set( 766 unit, port, PM_4X10_INFO(pm_info, core_seq), phy_init_flags, an); 767 _SOC_IF_ERR_EXIT(rv); 768 769 exit: 770 SOC_FUNC_RETURN; 771 } 772 773 int pm12x10_port_autoneg_get (int unit, int port, pm_info_t pm_info, int phy_init_flags, 774 phymod_autoneg_control_t* an) 775 { 776 int port_fallback_lane, core_seq; 777 SOC_INIT_FUNC_DEFS; 778 779 _SOC_IF_ERR_EXIT(PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_fallback_lane_get( 780 unit, port, PM_4X10_INFO(pm_info, 2), &port_fallback_lane)); 781 782 if(port_fallback_lane>2||port_fallback_lane<0) { 783 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, (_SOC_MSG("port_fallback_lane runaway"))); 784 } 785 core_seq = pm12x10_invert_core_seq[port_fallback_lane] ; 786 787 _SOC_IF_ERR_EXIT(PM_4X10_DRIVER(pm_info, core_seq)->f_portmod_port_autoneg_get( 788 unit, port, PM_4X10_INFO(pm_info, core_seq), phy_init_flags, an)); 789 790 exit: 791 SOC_FUNC_RETURN; 792 } 793 794 int pm12x10_port_autoneg_status_get (int unit, int port, pm_info_t pm_info, 795 phymod_autoneg_status_t* an) 796 { 797 return (PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_autoneg_status_get( 798 unit, port, PM_4X10_INFO(pm_info, 2), an)); 799 } 800 801 int pm12x10_port_link_get(int unit, int port, pm_info_t pm_info, int flags, int* link) 802 { 803 int all_link= 1; 804 int tmp_link; 805 int i; 806 int link_recovery_enable = 0; 807 portmod_port_interface_config_t config; 808 portmod_access_get_params_t params; 809 phymod_phy_access_t phy_access; 810 int tmp_nof_phys = 0; 811 int is_most_ext_i = 0; 812 int rv; 813 int phy_init_flags = 0; 814 uint32 signal_detect = 0; 815 uint32 all_signal_detect = 1; 816 817 SOC_INIT_FUNC_DEFS; 818 819 820 /* first check if 12 lane port */ 821 _SOC_IF_ERR_EXIT( 822 pm12x10_port_interface_config_get(unit, port, pm_info, &config, phy_init_flags)); 823 824 if (config.speed >= 120000) { 825 link_recovery_enable = 1; 826 } 827 828 /* for now not enable the 100G Sr10 link recovery */ 829 #if 0 830 /* next need to check if 100G SR10, if so, the link recovery needs to be enabled */ 831 if (config.speed == 100000) { 832 /*first get the master core phy access */ 833 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 834 params.phyn = 0; 835 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_phy_lane_access_get( 836 unit, port, PM_4X10_INFO(pm_info, 2), 837 ¶ms, 1 , &phy_access, &tmp_nof_phys, &is_most_ext_i); 838 839 _SOC_IF_ERR_EXIT(phymod_phy_firmware_lane_config_get(&phy_access, &firmware_lane_config)); 840 if (firmware_lane_config.MediaType == phymodFirmwareMediaTypeOptics) { 841 link_recovery_enable = 1; 842 } 843 } 844 #endif 845 846 for ( i = 0 ; i < 3 ; i++) 847 { 848 _SOC_IF_ERR_EXIT(PM_4X10_DRIVER(pm_info, i)->f_portmod_port_link_get( unit, port, 849 PM_4X10_INFO(pm_info, i), flags, &tmp_link)); 850 /* accumulate link status of all 3 cores. */ 851 all_link &= tmp_link; 852 } 853 854 /* next we need check if link recovery needs to be enabled */ 855 if ((link_recovery_enable) && (PM_12x10_INFO(pm_info)->link_recovery.enabled)) { 856 857 switch (PM_12x10_INFO(pm_info)->link_recovery.state) { 858 859 case PORTMOD_LINK_RECOVERY_STATE_WAIT_FOR_LINK: 860 /* link is good */ 861 if (all_link) { 862 PM_12x10_INFO(pm_info)->link_recovery.tick_cnt = 0; 863 PM_12x10_INFO(pm_info)->link_recovery.state = PORTMOD_LINK_RECOVERY_STATE_LINK_GOOD; 864 } else if ((PM_12x10_INFO(pm_info)->link_recovery.tick_cnt) > PORTMOD_LINK_RECOVERY_LINK_WAIT_CNT_LIMIT) { 865 /* no link after all the try, reset the rx patha again */ 866 PM_12x10_INFO(pm_info)->link_recovery.state = PORTMOD_LINK_RECOVERY_STATE_RESET_RX; 867 PM_12x10_INFO(pm_info)->link_recovery.tick_cnt = 0; 868 } else { 869 /* no link yet, keep wait for link */ 870 PM_12x10_INFO(pm_info)->link_recovery.tick_cnt += 1; 871 } 872 break; 873 874 case PORTMOD_LINK_RECOVERY_STATE_RESET_RX: 875 /*first check link status */ 876 if (all_link) { 877 PM_12x10_INFO(pm_info)->link_recovery.state = PORTMOD_LINK_RECOVERY_STATE_LINK_GOOD; 878 PM_12x10_INFO(pm_info)->link_recovery.tick_cnt = 0; 879 } else { 880 /* first reset the rx path */ 881 all_signal_detect = 1; 882 signal_detect = 0; 883 for ( i = 0 ; i < 3 ; i++) { 884 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 885 params.phyn = 0; 886 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_phy_lane_access_get( 887 unit, port, PM_4X10_INFO(pm_info, i), 888 ¶ms, 1 , &phy_access, &tmp_nof_phys, &is_most_ext_i); 889 _SOC_IF_ERR_EXIT(rv); 890 /* check if there is signal detect */ 891 _SOC_IF_ERR_EXIT(phymod_phy_rx_signal_detect_get(&phy_access, &signal_detect)); 892 all_signal_detect &= signal_detect; 893 signal_detect = 0; 894 } 895 /* only toggle rx reset path only if there is signal on the line */ 896 if (all_signal_detect) { 897 /* first put the rx into reset */ 898 for ( i = 0 ; i < 3 ; i++) { 899 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 900 params.phyn = 0; 901 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_phy_lane_access_get( 902 unit, port, PM_4X10_INFO(pm_info, i), 903 ¶ms, 1 , &phy_access, &tmp_nof_phys, &is_most_ext_i); 904 _SOC_IF_ERR_EXIT(rv); 905 906 _SOC_IF_ERR_EXIT(phymod_phy_rx_lane_control_set(&phy_access, phymodRxDisable)); 907 } 908 /* add some delay */ 909 sal_usleep(5000); 910 for ( i = 0 ; i < 3 ; i++) { 911 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 912 params.phyn = 0; 913 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_phy_lane_access_get( 914 unit, port, PM_4X10_INFO(pm_info, i), 915 ¶ms, 1 , &phy_access, &tmp_nof_phys, &is_most_ext_i); 916 _SOC_IF_ERR_EXIT(rv); 917 918 /* toggle CDR lock */ 919 _SOC_IF_ERR_EXIT(phymod_phy_rx_lane_control_set(&phy_access, phymodRxSquelchOn)); 920 } 921 /* add some delay */ 922 sal_usleep(5000); 923 for ( i = 0 ; i < 3 ; i++) { 924 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 925 params.phyn = 0; 926 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_phy_lane_access_get( 927 unit, port, PM_4X10_INFO(pm_info, i), 928 ¶ms, 1 , &phy_access, &tmp_nof_phys, &is_most_ext_i); 929 _SOC_IF_ERR_EXIT(rv); 930 931 _SOC_IF_ERR_EXIT(phymod_phy_rx_lane_control_set(&phy_access, phymodRxSquelchOff)); 932 } 933 sal_usleep(10000); 934 /* release the rx reset */ 935 for ( i = 0 ; i < 3 ; i++) { 936 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 937 params.phyn = 0; 938 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_phy_lane_access_get( 939 unit, port, PM_4X10_INFO(pm_info, i), 940 ¶ms, 1 , &phy_access, &tmp_nof_phys, &is_most_ext_i); 941 _SOC_IF_ERR_EXIT(rv); 942 943 _SOC_IF_ERR_EXIT(phymod_phy_rx_lane_control_set(&phy_access, phymodRxReset)); 944 } 945 sal_usleep(10000); 946 947 } 948 PM_12x10_INFO(pm_info)->link_recovery.state = PORTMOD_LINK_RECOVERY_STATE_WAIT_FOR_LINK; 949 PM_12x10_INFO(pm_info)->link_recovery.tick_cnt = 0; 950 } 951 break; 952 953 case PORTMOD_LINK_RECOVERY_STATE_LINK_GOOD: 954 /* no link, need to reset the rx path */ 955 if (!all_link) { 956 PM_12x10_INFO(pm_info)->link_recovery.state = PORTMOD_LINK_RECOVERY_STATE_RESET_RX; 957 PM_12x10_INFO(pm_info)->link_recovery.tick_cnt = 0; 958 } 959 break; 960 } 961 } 962 963 *link = all_link; 964 exit: 965 SOC_FUNC_RETURN; 966 } 967 968 int pm12x10_port_phy_link_up_event(int unit, int port, pm_info_t pm_info) 969 { 970 return SOC_E_NONE; 971 } 972 973 int pm12x10_port_phy_link_down_event(int unit, int port, pm_info_t pm_info) 974 { 975 return SOC_E_NONE; 976 } 977 978 int pm12x10_port_prbs_config_set (int unit, int port, pm_info_t pm_info, portmod_prbs_mode_t mode, 979 int flags, const phymod_prbs_t* config) 980 { 981 int i; 982 983 SOC_INIT_FUNC_DEFS; 984 985 if(mode == 0){ /*phy*/ 986 for(i = 0 ; i < 3 ; i++) 987 { 988 _SOC_IF_ERR_EXIT(PM_4X10_DRIVER(pm_info, i)->f_portmod_port_prbs_config_set(unit, port,PM_4X10_INFO(pm_info,i), mode, flags, config)); 989 } 990 } 991 else{ 992 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("MAC PRBS is not supported for PM12x10"))); 993 } 994 exit: 995 SOC_FUNC_RETURN; 996 } 997 998 999 int pm12x10_port_prbs_config_get(int unit, int port, pm_info_t pm_info, 1000 portmod_prbs_mode_t mode, int flags, phymod_prbs_t* config) 1001 { 1002 SOC_INIT_FUNC_DEFS; 1003 if(mode == 0){ /*phy*/ 1004 _SOC_IF_ERR_EXIT(PM_4X10_DRIVER(pm_info, 0)->f_portmod_port_prbs_config_get(unit, port, PM_4X10_INFO(pm_info,0),mode, flags, config)); 1005 } 1006 else{ 1007 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("MAC PRBS is not supported for PM12x10"))); 1008 } 1009 exit: 1010 SOC_FUNC_RETURN; 1011 } 1012 1013 1014 int pm12x10_port_prbs_enable_set (int unit, int port, pm_info_t pm_info, 1015 portmod_prbs_mode_t mode, int flags, int enable) 1016 { 1017 int i; 1018 1019 SOC_INIT_FUNC_DEFS; 1020 1021 if(mode == 0){ /*phy*/ 1022 for(i = 0 ; i < 3 ; i++) 1023 { 1024 _SOC_IF_ERR_EXIT 1025 (PM_4X10_DRIVER(pm_info, i)->f_portmod_port_prbs_enable_set(unit, port, 1026 PM_4X10_INFO(pm_info,i), 1027 mode, flags, enable)); 1028 } 1029 } 1030 else{ 1031 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("MAC PRBS is not supported for PM12x10"))); 1032 } 1033 exit: 1034 SOC_FUNC_RETURN; 1035 } 1036 1037 int pm12x10_port_prbs_enable_get (int unit, int port, pm_info_t pm_info, 1038 portmod_prbs_mode_t mode, int flags, int* enable) 1039 { 1040 1041 SOC_INIT_FUNC_DEFS; 1042 if(mode == 0){ /*phy*/ 1043 _SOC_IF_ERR_EXIT 1044 (PM_4X10_DRIVER(pm_info, 0)->f_portmod_port_prbs_enable_get(unit, port, 1045 PM_4X10_INFO(pm_info,0), 1046 mode, flags, enable)); 1047 } 1048 else{ 1049 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("MAC PRBS is not supported for PM12x10"))); 1050 } 1051 exit: 1052 SOC_FUNC_RETURN; 1053 } 1054 1055 1056 int pm12x10_port_prbs_status_get (int unit, int port, pm_info_t pm_info, 1057 portmod_prbs_mode_t mode, int flags, phymod_prbs_status_t* status) 1058 { 1059 1060 SOC_INIT_FUNC_DEFS; 1061 if(mode == 0){ /*phy*/ 1062 _SOC_IF_ERR_EXIT 1063 (PM_4X10_DRIVER(pm_info, 0)->f_portmod_port_prbs_status_get(unit, port, 1064 PM_4X10_INFO(pm_info,0), 1065 mode, flags, status)); 1066 } 1067 else{ 1068 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("MAC PRBS is not supported for PM12x10"))); 1069 } 1070 exit: 1071 SOC_FUNC_RETURN; 1072 } 1073 1074 1075 int pm12x10_port_firmware_mode_set (int unit, int port, pm_info_t pm_info, 1076 phymod_firmware_mode_t fw_mode) 1077 { 1078 SOC_INIT_FUNC_DEFS; 1079 1080 _SOC_IF_ERR_EXIT(portmod_common_phy_firmware_mode_set(unit, port, fw_mode)); 1081 1082 exit: 1083 SOC_FUNC_RETURN; 1084 } 1085 1086 1087 int pm12x10_port_firmware_mode_get (int unit, int port, pm_info_t pm_info, 1088 phymod_firmware_mode_t* fw_mode) 1089 { 1090 SOC_INIT_FUNC_DEFS; 1091 1092 _SOC_IF_ERR_EXIT(portmod_common_phy_firmware_mode_get(unit, port, fw_mode)); 1093 1094 exit: 1095 SOC_FUNC_RETURN; 1096 } 1097 1098 1099 int pm12x10_port_runt_threshold_set(int unit, int port, pm_info_t pm_info, int value) 1100 { 1101 int rv = 0; 1102 SOC_INIT_FUNC_DEFS; 1103 1104 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_runt_threshold_set(unit, port, 1105 PM_4X25_INFO(pm_info), value); 1106 _SOC_IF_ERR_EXIT(rv); 1107 1108 exit: 1109 SOC_FUNC_RETURN; 1110 1111 } 1112 1113 int pm12x10_port_runt_threshold_get(int unit, int port, pm_info_t pm_info, int* value) 1114 { 1115 int rv = 0; 1116 SOC_INIT_FUNC_DEFS; 1117 1118 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_runt_threshold_get(unit, port, 1119 PM_4X25_INFO(pm_info), value); 1120 _SOC_IF_ERR_EXIT(rv); 1121 1122 exit: 1123 SOC_FUNC_RETURN; 1124 } 1125 1126 1127 int pm12x10_port_max_packet_size_set (int unit, int port, 1128 pm_info_t pm_info, int value) 1129 { 1130 int rv = 0; 1131 SOC_INIT_FUNC_DEFS; 1132 1133 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_max_packet_size_set(unit, 1134 port, PM_4X25_INFO(pm_info), value); 1135 _SOC_IF_ERR_EXIT(rv); 1136 1137 exit: 1138 SOC_FUNC_RETURN; 1139 } 1140 1141 int pm12x10_port_max_packet_size_get (int unit, int port, 1142 pm_info_t pm_info, int* value) 1143 { 1144 int rv = 0; 1145 SOC_INIT_FUNC_DEFS; 1146 1147 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_max_packet_size_get(unit, 1148 port, PM_4X25_INFO(pm_info), value); 1149 _SOC_IF_ERR_EXIT(rv); 1150 1151 exit: 1152 SOC_FUNC_RETURN; 1153 } 1154 1155 1156 int pm12x10_port_pad_size_set(int unit, int port, pm_info_t pm_info, int value) 1157 { 1158 int rv = 0; 1159 SOC_INIT_FUNC_DEFS; 1160 1161 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_pad_size_set(unit, port, 1162 PM_4X25_INFO(pm_info), value); 1163 _SOC_IF_ERR_EXIT(rv); 1164 1165 exit: 1166 SOC_FUNC_RETURN; 1167 } 1168 1169 1170 int pm12x10_port_pad_size_get(int unit, int port, pm_info_t pm_info, int* value) 1171 { 1172 int rv = 0; 1173 SOC_INIT_FUNC_DEFS; 1174 1175 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_pad_size_get(unit, port, 1176 PM_4X25_INFO(pm_info), value); 1177 _SOC_IF_ERR_EXIT(rv); 1178 1179 exit: 1180 SOC_FUNC_RETURN; 1181 } 1182 1183 1184 int pm12x10_port_local_fault_status_get(int unit, int port, pm_info_t pm_info, int* value) 1185 { 1186 int rv = 0; 1187 SOC_INIT_FUNC_DEFS; 1188 1189 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_local_fault_status_get(unit, port, 1190 PM_4X25_INFO(pm_info), value); 1191 _SOC_IF_ERR_EXIT(rv); 1192 exit: 1193 SOC_FUNC_RETURN; 1194 } 1195 1196 int pm12x10_port_local_fault_control_set(int unit, int port, pm_info_t pm_info, 1197 const portmod_local_fault_control_t* control) 1198 { 1199 int rv; 1200 SOC_INIT_FUNC_DEFS; 1201 1202 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_local_fault_control_set(unit, port, 1203 PM_4X25_INFO(pm_info), control); 1204 _SOC_IF_ERR_EXIT(rv); 1205 exit: 1206 SOC_FUNC_RETURN; 1207 } 1208 1209 int pm12x10_port_local_fault_control_get(int unit, int port, pm_info_t pm_info, 1210 portmod_local_fault_control_t* control) 1211 { 1212 int rv; 1213 SOC_INIT_FUNC_DEFS; 1214 1215 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_local_fault_control_get(unit, port, 1216 PM_4X25_INFO(pm_info), control); 1217 _SOC_IF_ERR_EXIT(rv); 1218 exit: 1219 SOC_FUNC_RETURN; 1220 } 1221 1222 int pm12x10_port_remote_fault_status_get(int unit, int port, pm_info_t pm_info, int* value) 1223 { 1224 int rv = 0; 1225 SOC_INIT_FUNC_DEFS; 1226 1227 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_remote_fault_status_get(unit, port, 1228 PM_4X25_INFO(pm_info), value); 1229 _SOC_IF_ERR_EXIT(rv); 1230 1231 exit: 1232 SOC_FUNC_RETURN; 1233 } 1234 1235 int pm12x10_port_remote_fault_control_set(int unit, int port, pm_info_t pm_info, 1236 const portmod_remote_fault_control_t* control) 1237 { 1238 int rv; 1239 SOC_INIT_FUNC_DEFS; 1240 1241 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_remote_fault_control_set(unit, port, 1242 PM_4X25_INFO(pm_info), control); 1243 _SOC_IF_ERR_EXIT(rv); 1244 exit: 1245 SOC_FUNC_RETURN; 1246 } 1247 1248 int pm12x10_port_remote_fault_control_get(int unit, int port, pm_info_t pm_info, 1249 portmod_remote_fault_control_t* control) 1250 { 1251 int rv; 1252 SOC_INIT_FUNC_DEFS; 1253 1254 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_remote_fault_control_get(unit, port, 1255 PM_4X25_INFO(pm_info), control); 1256 _SOC_IF_ERR_EXIT(rv); 1257 exit: 1258 SOC_FUNC_RETURN; 1259 } 1260 1261 int pm12x10_port_pause_control_set (int unit, int port, pm_info_t pm_info, 1262 const portmod_pause_control_t* control) 1263 { 1264 int rv = 0; 1265 SOC_INIT_FUNC_DEFS; 1266 1267 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_pause_control_set(unit, port, 1268 PM_4X25_INFO(pm_info), control); 1269 _SOC_IF_ERR_EXIT(rv); 1270 1271 exit: 1272 SOC_FUNC_RETURN; 1273 } 1274 1275 1276 int pm12x10_port_pause_control_get (int unit, int port, pm_info_t pm_info, 1277 portmod_pause_control_t* control) 1278 { 1279 int rv = 0; 1280 SOC_INIT_FUNC_DEFS; 1281 1282 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_pause_control_get(unit, port, 1283 PM_4X25_INFO(pm_info), control); 1284 _SOC_IF_ERR_EXIT(rv); 1285 1286 exit: 1287 SOC_FUNC_RETURN; 1288 } 1289 1290 int pm12x10_port_pfc_control_set (int unit, int port, pm_info_t pm_info, 1291 const portmod_pfc_control_t* control) 1292 { 1293 int rv = 0; 1294 SOC_INIT_FUNC_DEFS; 1295 1296 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_pfc_control_set(unit, port, 1297 PM_4X25_INFO(pm_info), control); 1298 _SOC_IF_ERR_EXIT(rv); 1299 1300 exit: 1301 SOC_FUNC_RETURN; 1302 } 1303 1304 int pm12x10_port_pfc_control_get (int unit, int port, pm_info_t pm_info, 1305 portmod_pfc_control_t* control) 1306 { 1307 int rv = 0; 1308 SOC_INIT_FUNC_DEFS; 1309 1310 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_pfc_control_get(unit, port, 1311 PM_4X25_INFO(pm_info), control); 1312 _SOC_IF_ERR_EXIT(rv); 1313 1314 exit: 1315 SOC_FUNC_RETURN; 1316 } 1317 1318 1319 int pm12x10_port_llfc_control_set(int unit, int port, pm_info_t pm_info, 1320 const portmod_llfc_control_t* control) 1321 { 1322 int rv = 0; 1323 SOC_INIT_FUNC_DEFS; 1324 1325 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_llfc_control_set(unit, port, 1326 PM_4X25_INFO(pm_info), control); 1327 _SOC_IF_ERR_EXIT(rv); 1328 1329 exit: 1330 SOC_FUNC_RETURN; 1331 } 1332 1333 int pm12x10_port_llfc_control_get(int unit, int port, pm_info_t pm_info, 1334 portmod_llfc_control_t* control) 1335 { 1336 int rv = 0; 1337 SOC_INIT_FUNC_DEFS; 1338 1339 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_llfc_control_get(unit, port, 1340 PM_4X25_INFO(pm_info), control); 1341 _SOC_IF_ERR_EXIT(rv); 1342 1343 exit: 1344 SOC_FUNC_RETURN; 1345 } 1346 1347 1348 int pm12x10_port_core_access_get(int unit, int port, pm_info_t pm_info, 1349 int phyn, int max_cores, 1350 phymod_core_access_t* core_access_arr, 1351 int* nof_cores, 1352 int* is_most_ext) 1353 { 1354 int i = 0; 1355 int rv = 0; 1356 int tmp_nof_cores; 1357 int is_most_ext_i; 1358 SOC_INIT_FUNC_DEFS; 1359 1360 if(max_cores < 3){ 1361 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 1362 (_SOC_MSG("3 core structures are required, %d given"), 1363 max_cores)); 1364 } 1365 1366 if (is_most_ext) { 1367 *is_most_ext = 0; 1368 } 1369 1370 for( i = 0 ; i < 3 ; i++){ 1371 rv = PM_4X10_DRIVER(pm_info, 0)->f_portmod_port_core_access_get(unit, 1372 port, PM_4X10_INFO(pm_info, i), phyn, 1373 1, &core_access_arr[i], &tmp_nof_cores, &is_most_ext_i); 1374 _SOC_IF_ERR_EXIT(rv); 1375 1376 if (is_most_ext) { 1377 *is_most_ext = (*is_most_ext | is_most_ext_i ? 1 : 0); 1378 } 1379 } 1380 1381 *nof_cores = 3; 1382 1383 1384 exit: 1385 SOC_FUNC_RETURN; 1386 } 1387 1388 int pm12x10_port_phy_lane_access_get(int unit, int port, pm_info_t pm_info, 1389 const portmod_access_get_params_t* params, 1390 int max_phys, 1391 phymod_phy_access_t* access, 1392 int* nof_phys, int* is_most_ext) 1393 { 1394 int i = 0; 1395 int rv = 0; 1396 int tmp_nof_phys; 1397 int is_most_ext_i; 1398 int lane_mask, consolidated_mask, first_set_bit; 1399 int prev_xphy_id, xphy_id; 1400 SOC_INIT_FUNC_DEFS; 1401 1402 prev_xphy_id = PORTMOD_XPHY_ID_INVALID; 1403 xphy_id = PORTMOD_XPHY_ID_INVALID; 1404 lane_mask = 0; 1405 consolidated_mask = 0; 1406 1407 if(max_phys < 3){ 1408 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 1409 (_SOC_MSG("3 phy access structures are required, %d given"), 1410 max_phys)); 1411 } 1412 1413 if (is_most_ext) { 1414 *is_most_ext = 0; 1415 } 1416 1417 *nof_phys = 0; 1418 for( i = 0 ; i < 3 ; i++){ 1419 1420 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_lane_mask_get ( 1421 unit, port, /* PM_4X10_INFO(pm_info, i), */ 1422 PM_12x10_INFO(pm_info)->pm4x10_info[i], 1423 params, &lane_mask, &xphy_id ); 1424 _SOC_IF_ERR_EXIT(rv); 1425 1426 if (xphy_id != PORTMOD_XPHY_ID_INVALID) { 1427 if (!consolidated_mask) { 1428 consolidated_mask = lane_mask; 1429 } 1430 if ( prev_xphy_id == xphy_id ) { 1431 consolidated_mask |= lane_mask; 1432 } 1433 prev_xphy_id = xphy_id; 1434 } 1435 1436 1437 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_phy_lane_access_get( 1438 unit, port, /* PM_4X10_INFO(pm_info, i), */ 1439 PM_12x10_INFO(pm_info)->pm4x10_info[i], 1440 params, 1 , &access[*nof_phys], &tmp_nof_phys, &is_most_ext_i); 1441 1442 _SOC_IF_ERR_EXIT(rv); 1443 1444 if (is_most_ext) { 1445 *is_most_ext = (*is_most_ext | is_most_ext_i ? 1 : 0); 1446 } 1447 *nof_phys += tmp_nof_phys; 1448 } 1449 1450 if ((params->lane != -1) && consolidated_mask) { 1451 for(first_set_bit=0; first_set_bit<12; first_set_bit++){ 1452 if( (consolidated_mask>>first_set_bit) & 0x1) { 1453 break; 1454 } 1455 } 1456 if ((!((1 << (params->lane + first_set_bit)) & consolidated_mask))) { 1457 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 1458 (_SOC_MSG("Requested lane %d doesn't exist in lane_mask=0x%x\n") 1459 ,params->lane, consolidated_mask )); 1460 } 1461 for(i = 0 ; i < *nof_phys ; i++){ 1462 access[i].access.lane_mask = ((1 << (params->lane + first_set_bit)) & consolidated_mask); 1463 } 1464 } 1465 exit: 1466 SOC_FUNC_RETURN; 1467 1468 } 1469 1470 1471 /*! 1472 * pm12x10_port_duplex_set 1473 * 1474 * @brief duplex set. 1475 * 1476 * @param [in] unit - unit id 1477 * @param [in] port - logical port 1478 * @param [in] enable - 1479 */ 1480 int pm12x10_port_duplex_set(int unit, int port, pm_info_t pm_info, int enable) 1481 { 1482 int rv = 0; 1483 SOC_INIT_FUNC_DEFS; 1484 1485 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_duplex_set(unit, port, 1486 PM_4X25_INFO(pm_info), enable); 1487 _SOC_IF_ERR_EXIT(rv); 1488 1489 exit: 1490 SOC_FUNC_RETURN; 1491 } 1492 1493 1494 /*! 1495 * pm12x10_port_duplex_get 1496 * 1497 * @brief duplex get. 1498 * 1499 * @param [in] unit - unit id 1500 * @param [in] port - logical port 1501 * @param [in] vlan_tag - 1502 */ 1503 int pm12x10_port_duplex_get(int unit, int port, pm_info_t pm_info, int* duplex) 1504 { 1505 *duplex=1; 1506 return (0); 1507 } 1508 1509 int pm12x10_port_phy_reg_read (int unit, int port, pm_info_t pm_info, 1510 int lane, int flags, int reg_addr, uint32* value) 1511 { 1512 int core_index, rv = 0; 1513 int core_id = 2; 1514 portmod_access_get_params_t params; 1515 phymod_phy_access_t phy_access; 1516 int is_most_ext; 1517 int tmp_nof_phys; 1518 int mask = 0; 1519 1520 SOC_INIT_FUNC_DEFS; 1521 1522 if (lane >= 0) { /* lane is specified */ 1523 for (core_index = 0 ; core_index < 3 ; core_index++){ /* walk through 3 cores */ 1524 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 1525 if (flags & SOC_PHY_INTERNAL) { 1526 params.phyn = 0; 1527 } 1528 params.lane = lane; 1529 rv = PM_4X10_DRIVER(pm_info, core_index)->f_portmod_port_phy_lane_access_get( 1530 unit, port, PM_4X10_INFO(pm_info, core_index), 1531 ¶ms, 1, &phy_access, &tmp_nof_phys, &is_most_ext); 1532 _SOC_IF_ERR_EXIT(rv); 1533 if (tmp_nof_phys >= 1) { /* found the right core */ 1534 mask = phy_access.access.lane_mask; 1535 lane = 0; 1536 while (mask >0) { 1537 if (mask & 1) { 1538 break; 1539 } 1540 lane ++; 1541 mask >>= 1 ; 1542 } 1543 rv = PM_4X10_DRIVER(pm_info, core_index)->f_portmod_port_phy_reg_read(unit, 1544 port, PM_4X10_INFO(pm_info, core_index), lane, flags, reg_addr, value); 1545 break; 1546 } 1547 } 1548 } else { 1549 rv = PM_4X10_DRIVER(pm_info, core_id)->f_portmod_port_phy_reg_read(unit, 1550 port, PM_4X10_INFO(pm_info, core_id), lane, flags, reg_addr, value); 1551 } 1552 _SOC_IF_ERR_EXIT(rv); 1553 1554 exit: 1555 SOC_FUNC_RETURN; 1556 } 1557 1558 int pm12x10_port_phy_reg_write (int unit, int port, pm_info_t pm_info, 1559 int lane, int flags, int reg_addr, uint32 value) 1560 { 1561 int core_index = 0, rv = 0; 1562 portmod_access_get_params_t params; 1563 phymod_phy_access_t phy_access; 1564 int is_most_ext; 1565 int tmp_nof_phys; 1566 int mask = 0; 1567 1568 SOC_INIT_FUNC_DEFS; 1569 1570 if (lane >= 0) { /* lane is specified */ 1571 for (core_index = 0 ; core_index < 3 ; core_index++){ /* walk through 3 cores */ 1572 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 1573 if (flags & SOC_PHY_INTERNAL) { 1574 params.phyn = 0; 1575 } 1576 params.lane = lane; 1577 rv = PM_4X10_DRIVER(pm_info, core_index)->f_portmod_port_phy_lane_access_get( 1578 unit, port, PM_4X10_INFO(pm_info, core_index), 1579 ¶ms, 1, &phy_access, &tmp_nof_phys, &is_most_ext); 1580 _SOC_IF_ERR_EXIT(rv); 1581 if (tmp_nof_phys >= 1) { /* found the right core */ 1582 mask = phy_access.access.lane_mask; 1583 lane = 0; 1584 while (mask >0) { 1585 if (mask & 1) { 1586 break; 1587 } 1588 lane ++; 1589 mask >>= 1 ; 1590 } 1591 rv = PM_4X10_DRIVER(pm_info, core_index)->f_portmod_port_phy_reg_write(unit, 1592 port, PM_4X10_INFO(pm_info, core_index), lane, flags, reg_addr, value); 1593 _SOC_IF_ERR_EXIT(rv); 1594 break; 1595 } 1596 } 1597 } else { 1598 for (core_index = 0 ; core_index < 3 ; core_index++){ 1599 rv = PM_4X10_DRIVER(pm_info, core_index)->f_portmod_port_phy_reg_write(unit, 1600 port, PM_4X10_INFO(pm_info, core_index), lane, flags, reg_addr, value); 1601 _SOC_IF_ERR_EXIT(rv); 1602 } 1603 } 1604 exit: 1605 SOC_FUNC_RETURN; 1606 } 1607 1608 int pm12x10_port_reset_set (int unit, int port, pm_info_t pm_info, 1609 int mode, int opcode, int value) 1610 { 1611 int rv = 0, i = 0; 1612 SOC_INIT_FUNC_DEFS; 1613 1614 for( i = 0 ; i < 3 ; i++){ 1615 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_reset_set (unit, port, 1616 PM_4X10_INFO(pm_info, i), mode, opcode, value); 1617 _SOC_IF_ERR_EXIT(rv); 1618 } 1619 1620 exit: 1621 SOC_FUNC_RETURN; 1622 } 1623 1624 int pm12x10_port_reset_get (int unit, int port, pm_info_t pm_info, 1625 int mode, int opcode, int* value) 1626 { 1627 int rv = 0; 1628 SOC_INIT_FUNC_DEFS; 1629 1630 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_reset_get (unit, port, 1631 PM_4X10_INFO(pm_info, 2), mode, opcode, value); 1632 _SOC_IF_ERR_EXIT(rv); 1633 1634 exit: 1635 SOC_FUNC_RETURN; 1636 } 1637 1638 /*Port remote Adv get*/ 1639 int pm12x10_port_adv_remote_get (int unit, int port, pm_info_t pm_info, 1640 int* value) 1641 { 1642 return (0); 1643 } 1644 1645 /*! 1646 * pm12x10_port_frame_spacing_stretch_set 1647 * 1648 * @brief Port Mac Control Spacing Stretch 1649 * 1650 * @param [in] unit - unit id 1651 * @param [in] port - logical port 1652 * @param [in] spacing - 1653 */ 1654 int pm12x10_port_frame_spacing_stretch_set (int unit, int port, 1655 pm_info_t pm_info,int spacing) 1656 { 1657 int rv = 0; 1658 SOC_INIT_FUNC_DEFS; 1659 1660 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_frame_spacing_stretch_set(unit, 1661 port, PM_4X25_INFO(pm_info), spacing); 1662 _SOC_IF_ERR_EXIT(rv); 1663 1664 exit: 1665 SOC_FUNC_RETURN; 1666 1667 } 1668 1669 /*! 1670 * pm12x10_port_frame_spacing_stretch_get 1671 * 1672 * @brief Port Mac Control Spacing Stretch 1673 * 1674 * @param [in] unit - unit id 1675 * @param [in] port - logical port 1676 * @param [in] spacing - 1677 */ 1678 int pm12x10_port_frame_spacing_stretch_get (int unit, int port, 1679 pm_info_t pm_info, 1680 const int *spacing) 1681 { 1682 int rv = 0; 1683 SOC_INIT_FUNC_DEFS; 1684 1685 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_frame_spacing_stretch_get(unit, 1686 port, PM_4X25_INFO(pm_info), spacing); 1687 _SOC_IF_ERR_EXIT(rv); 1688 1689 exit: 1690 SOC_FUNC_RETURN; 1691 } 1692 1693 1694 /*! 1695 * pm12x10_port_diag_fifo_status_get 1696 * 1697 * @brief get port timestamps in fifo 1698 * 1699 * @param [in] unit - unit id 1700 * @param [in] port - logical port 1701 * @param [in] diag_info - 1702 */ 1703 int pm12x10_port_diag_fifo_status_get (int unit, int port,pm_info_t pm_info, 1704 const portmod_fifo_status_t* diag_info) 1705 { 1706 int rv = 0; 1707 SOC_INIT_FUNC_DEFS; 1708 1709 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_diag_fifo_status_get(unit, 1710 port, PM_4X25_INFO(pm_info), diag_info); 1711 _SOC_IF_ERR_EXIT(rv); 1712 1713 exit: 1714 SOC_FUNC_RETURN; 1715 1716 } 1717 1718 /*! 1719 * pm12x10_port_pfc_config_set 1720 * 1721 * @brief set pass control frames. 1722 * 1723 * @param [in] unit - unit id 1724 * @param [in] port - logical port 1725 * @param [in] pfc_cfg - 1726 */ 1727 int pm12x10_port_pfc_config_set (int unit, int port,pm_info_t pm_info, 1728 const portmod_pfc_config_t* pfc_cfg) 1729 { 1730 int rv = 0; 1731 SOC_INIT_FUNC_DEFS; 1732 1733 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_pfc_config_set(unit, 1734 port, PM_4X25_INFO(pm_info), pfc_cfg); 1735 _SOC_IF_ERR_EXIT(rv); 1736 1737 exit: 1738 SOC_FUNC_RETURN; 1739 1740 } 1741 1742 1743 /*! 1744 * pm12x10_port_pfc_config_get 1745 * 1746 * @brief set pass control frames. 1747 * 1748 * @param [in] unit - unit id 1749 * @param [in] port - logical port 1750 * @param [in] pfc_cfg - 1751 */ 1752 int pm12x10_port_pfc_config_get (int unit, int port,pm_info_t pm_info, 1753 portmod_pfc_config_t* pfc_cfg) 1754 { 1755 int rv = 0; 1756 SOC_INIT_FUNC_DEFS; 1757 1758 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_pfc_config_get(unit, 1759 port, PM_4X25_INFO(pm_info), pfc_cfg); 1760 _SOC_IF_ERR_EXIT(rv); 1761 1762 exit: 1763 SOC_FUNC_RETURN; 1764 1765 } 1766 1767 /*! 1768 * pm12x10_port_eee_set 1769 * 1770 * @brief set EEE control and timers 1771 * 1772 * @param [in] unit - unit id 1773 * @param [in] port - logical port 1774 * @param [in] eee - 1775 */ 1776 int pm12x10_port_eee_set(int unit, int port, pm_info_t pm_info, 1777 const portmod_eee_t* eee) 1778 { 1779 int rv = 0; 1780 SOC_INIT_FUNC_DEFS; 1781 1782 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_eee_set(unit, 1783 port, PM_4X25_INFO(pm_info), eee); 1784 _SOC_IF_ERR_EXIT(rv); 1785 1786 exit: 1787 SOC_FUNC_RETURN; 1788 1789 } 1790 1791 /*! 1792 * pm12x10_port_eee_get 1793 * 1794 * @brief get EEE control and timers 1795 * 1796 * @param [in] unit - unit id 1797 * @param [in] port - logical port 1798 * @param [in] eee - 1799 */ 1800 int pm12x10_port_eee_get (int unit, int port, pm_info_t pm_info, 1801 portmod_eee_t* eee) 1802 { 1803 int rv = 0; 1804 SOC_INIT_FUNC_DEFS; 1805 1806 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_eee_get(unit, 1807 port, PM_4X25_INFO(pm_info), eee); 1808 _SOC_IF_ERR_EXIT(rv); 1809 1810 exit: 1811 SOC_FUNC_RETURN; 1812 1813 } 1814 1815 /*! 1816 * pm12x10_port_vlan_tag_set 1817 * 1818 * @brief vlan tag set. 1819 * 1820 * @param [in] unit - unit id 1821 * @param [in] port - logical port 1822 * @param [in] vlan_tag - 1823 */ 1824 int pm12x10_port_vlan_tag_set (int unit, int port, pm_info_t pm_info, 1825 const portmod_vlan_tag_t* vlan_tag) 1826 { 1827 int rv = 0; 1828 SOC_INIT_FUNC_DEFS; 1829 1830 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_vlan_tag_set(unit, 1831 port, PM_4X25_INFO(pm_info), vlan_tag); 1832 _SOC_IF_ERR_EXIT(rv); 1833 1834 exit: 1835 SOC_FUNC_RETURN; 1836 1837 } 1838 1839 1840 /*! 1841 * pm12x10_port_vlan_tag_get 1842 * 1843 * @brief vlan tag get. 1844 * 1845 * @param [in] unit - unit id 1846 * @param [in] port - logical port 1847 * @param [in] vlan_tag - 1848 */ 1849 int pm12x10_port_vlan_tag_get(int unit, int port, pm_info_t pm_info, 1850 portmod_vlan_tag_t* vlan_tag) 1851 { 1852 int rv = 0; 1853 SOC_INIT_FUNC_DEFS; 1854 1855 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_vlan_tag_get(unit, 1856 port, PM_4X25_INFO(pm_info), vlan_tag); 1857 _SOC_IF_ERR_EXIT(rv); 1858 1859 exit: 1860 SOC_FUNC_RETURN; 1861 1862 } 1863 1864 int pm12x10_port_rx_control_set (int unit, int port, pm_info_t pm_info, 1865 const portmod_rx_control_t* rx_ctrl) 1866 { 1867 int rv = 0; 1868 SOC_INIT_FUNC_DEFS; 1869 1870 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_rx_control_set(unit, 1871 port, PM_4X25_INFO(pm_info), rx_ctrl); 1872 _SOC_IF_ERR_EXIT(rv); 1873 1874 exit: 1875 SOC_FUNC_RETURN; 1876 } 1877 1878 int pm12x10_port_rx_control_get (int unit, int port, pm_info_t pm_info, 1879 portmod_rx_control_t* rx_ctrl) 1880 { 1881 int rv = 0; 1882 SOC_INIT_FUNC_DEFS; 1883 1884 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_rx_control_get(unit, 1885 port, PM_4X25_INFO(pm_info), rx_ctrl); 1886 _SOC_IF_ERR_EXIT(rv); 1887 1888 exit: 1889 SOC_FUNC_RETURN; 1890 } 1891 1892 1893 /*! 1894 * pm12x10_port_tx_mac_sa_set 1895 * 1896 * @brief set/get Mac Addr. 1897 * 1898 * @param [in] unit - unit id 1899 * @param [in] port - logical port 1900 * @param [in] mac_addr - 1901 */ 1902 int pm12x10_port_tx_mac_sa_set(int unit, int port, pm_info_t pm_info, sal_mac_addr_t mac_addr) 1903 { 1904 int rv = 0; 1905 SOC_INIT_FUNC_DEFS; 1906 1907 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_tx_mac_sa_set(unit, 1908 port, PM_4X25_INFO(pm_info), mac_addr); 1909 _SOC_IF_ERR_EXIT(rv); 1910 1911 exit: 1912 SOC_FUNC_RETURN; 1913 } 1914 1915 /*! 1916 * pm12x10_port_tx_mac_sa_get 1917 * 1918 * @brief set/get Mac Addr. 1919 * 1920 * @param [in] unit - unit id 1921 * @param [in] port - logical port 1922 * @param [in] mac_addr - 1923 */ 1924 int pm12x10_port_tx_mac_sa_get(int unit, int port, pm_info_t pm_info, sal_mac_addr_t mac_addr) 1925 { 1926 int rv = 0; 1927 SOC_INIT_FUNC_DEFS; 1928 1929 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_tx_mac_sa_get (unit, 1930 port, PM_4X25_INFO(pm_info), mac_addr); 1931 _SOC_IF_ERR_EXIT(rv); 1932 1933 exit: 1934 SOC_FUNC_RETURN; 1935 } 1936 1937 int pm12x10_port_tx_average_ipg_set (int unit, int port, 1938 pm_info_t pm_info, int value) 1939 { 1940 int rv = 0; 1941 SOC_INIT_FUNC_DEFS; 1942 1943 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_tx_average_ipg_set(unit, 1944 port, PM_4X25_INFO(pm_info), value); 1945 _SOC_IF_ERR_EXIT(rv); 1946 1947 exit: 1948 SOC_FUNC_RETURN; 1949 } 1950 1951 1952 int pm12x10_port_tx_average_ipg_get (int unit, int port, 1953 pm_info_t pm_info, int* value) 1954 { 1955 int rv = 0; 1956 SOC_INIT_FUNC_DEFS; 1957 1958 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_tx_average_ipg_get (unit, 1959 port, PM_4X25_INFO(pm_info), value); 1960 _SOC_IF_ERR_EXIT(rv); 1961 1962 exit: 1963 SOC_FUNC_RETURN; 1964 } 1965 1966 int pm12x10_port_drv_name_get (int unit, int port, pm_info_t pm_info, 1967 char* buf, int len) 1968 { 1969 strncpy(buf, "PM12X10 Driver", len); 1970 return (SOC_E_NONE); 1971 } 1972 1973 int pm12x10_port_modid_set (int unit, int port, pm_info_t pm_info, int value) 1974 { 1975 int rv = 0; 1976 SOC_INIT_FUNC_DEFS; 1977 1978 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_modid_set(unit, 1979 port, PM_4X25_INFO(pm_info), value); 1980 _SOC_IF_ERR_EXIT(rv); 1981 1982 exit: 1983 SOC_FUNC_RETURN; 1984 } 1985 1986 1987 int pm12x10_port_led_chain_config(int unit, int port, pm_info_t pm_info, int value) 1988 { 1989 SOC_INIT_FUNC_DEFS; 1990 1991 _SOC_IF_ERR_EXIT(WRITE_CXX_CXXPORT_LED_CHAIN_CONFIGr (unit, port, value)); 1992 1993 exit: 1994 SOC_FUNC_RETURN; 1995 } 1996 1997 int pm12x10_port_clear_rx_lss_status_set (int unit, soc_port_t port, pm_info_t pm_info, 1998 int lcl_fault, int rmt_fault) 1999 { 2000 int rv = 0; 2001 SOC_INIT_FUNC_DEFS; 2002 2003 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_clear_rx_lss_status_set(unit, 2004 port, PM_4X25_INFO(pm_info), lcl_fault, rmt_fault); 2005 _SOC_IF_ERR_EXIT(rv); 2006 2007 2008 exit: 2009 SOC_FUNC_RETURN; 2010 } 2011 2012 int pm12x10_port_clear_rx_lss_status_get (int unit, soc_port_t port, pm_info_t pm_info, 2013 int *lcl_fault, int *rmt_fault) 2014 { 2015 int rv = 0; 2016 SOC_INIT_FUNC_DEFS; 2017 2018 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_clear_rx_lss_status_get(unit, 2019 port, PM_4X25_INFO(pm_info), lcl_fault, rmt_fault); 2020 _SOC_IF_ERR_EXIT(rv); 2021 2022 exit: 2023 SOC_FUNC_RETURN; 2024 } 2025 2026 int pm12x10_port_lag_failover_status_toggle (int unit, soc_port_t port, pm_info_t pm_info) 2027 { 2028 int rv = 0; 2029 SOC_INIT_FUNC_DEFS; 2030 2031 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_lag_failover_status_toggle(unit, 2032 port, PM_4X25_INFO(pm_info)); 2033 _SOC_IF_ERR_EXIT(rv); 2034 2035 exit: 2036 SOC_FUNC_RETURN; 2037 } 2038 2039 int pm12x10_port_lag_failover_loopback_get (int unit, soc_port_t port, pm_info_t pm_info, int *val) 2040 { 2041 int rv = 0; 2042 SOC_INIT_FUNC_DEFS; 2043 2044 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_lag_failover_loopback_get(unit, 2045 port, PM_4X25_INFO(pm_info), val); 2046 _SOC_IF_ERR_EXIT(rv); 2047 2048 exit: 2049 SOC_FUNC_RETURN; 2050 } 2051 2052 int pm12x10_port_lag_failover_loopback_set (int unit, soc_port_t port, pm_info_t pm_info, int val) 2053 { 2054 int rv = 0; 2055 SOC_INIT_FUNC_DEFS; 2056 2057 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_lag_failover_loopback_set(unit, 2058 port, PM_4X25_INFO(pm_info), val); 2059 _SOC_IF_ERR_EXIT(rv); 2060 2061 exit: 2062 SOC_FUNC_RETURN; 2063 } 2064 2065 int pm12x10_port_mode_set (int unit, soc_port_t port, pm_info_t pm_info, 2066 const portmod_port_mode_info_t *mode) 2067 { 2068 int rv = 0; 2069 SOC_INIT_FUNC_DEFS; 2070 2071 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_mode_set(unit, 2072 port, PM_4X25_INFO(pm_info), mode); 2073 2074 _SOC_IF_ERR_EXIT(rv); 2075 2076 exit: 2077 SOC_FUNC_RETURN; 2078 } 2079 2080 int pm12x10_port_mode_get (int unit, soc_port_t port, pm_info_t pm_info, 2081 portmod_port_mode_info_t *mode) 2082 { 2083 int rv = 0; 2084 SOC_INIT_FUNC_DEFS; 2085 /* 2086 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_mode_get(unit, 2087 port, PM_4X25_INFO(pm_info), mode); 2088 */ 2089 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_mode_get ( 2090 unit, port, PM_4X10_INFO(pm_info,2), mode); 2091 _SOC_IF_ERR_EXIT(rv); 2092 2093 exit: 2094 SOC_FUNC_RETURN; 2095 } 2096 2097 int pm12x10_port_ability_remote_get (int unit, soc_port_t port, pm_info_t pm_info, int phy_init_flags, 2098 portmod_port_ability_t *ability) 2099 { 2100 int rv = 0; 2101 SOC_INIT_FUNC_DEFS; 2102 2103 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_ability_remote_get ( 2104 unit, port, PM_4X10_INFO(pm_info,2), phy_init_flags, ability); 2105 _SOC_IF_ERR_EXIT(rv); 2106 2107 exit: 2108 SOC_FUNC_RETURN; 2109 } 2110 2111 int pm12x10_port_ability_advert_get (int unit, soc_port_t port, pm_info_t pm_info, int phy_init_flags, 2112 portmod_port_ability_t *ability) 2113 { 2114 int rv = 0; 2115 int port_fallback_lane, core_seq; 2116 SOC_INIT_FUNC_DEFS; 2117 2118 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_fallback_lane_get( 2119 unit, port, PM_4X10_INFO(pm_info, 2), &port_fallback_lane); 2120 _SOC_IF_ERR_EXIT(rv); 2121 2122 if(port_fallback_lane>2||port_fallback_lane<0) { 2123 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, (_SOC_MSG("port_fallback_lane runaway"))); 2124 } 2125 core_seq = pm12x10_invert_core_seq[port_fallback_lane] ; 2126 2127 rv = PM_4X10_DRIVER(pm_info, core_seq)->f_portmod_port_ability_advert_get ( 2128 unit, port, PM_4X10_INFO(pm_info,2), phy_init_flags, ability); 2129 _SOC_IF_ERR_EXIT(rv); 2130 2131 exit: 2132 SOC_FUNC_RETURN; 2133 } 2134 2135 int pm12x10_port_ability_advert_set (int unit, soc_port_t port, pm_info_t pm_info, int phy_init_flags, 2136 portmod_port_ability_t *ability) 2137 { 2138 int rv = 0, i=0; 2139 SOC_INIT_FUNC_DEFS; 2140 2141 for(i = 0 ; i < 3 ; i++) 2142 { 2143 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_ability_advert_set ( 2144 unit, port, PM_4X10_INFO(pm_info,i), phy_init_flags, ability); 2145 _SOC_IF_ERR_EXIT(rv); 2146 } 2147 2148 exit: 2149 SOC_FUNC_RETURN; 2150 } 2151 2152 2153 int pm12x10_port_encap_get (int unit, soc_port_t port, pm_info_t pm_info, 2154 int *flags, portmod_encap_t *encap) 2155 2156 { 2157 int rv = 0; 2158 SOC_INIT_FUNC_DEFS; 2159 2160 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_encap_get(unit, 2161 port, PM_4X25_INFO(pm_info), flags, encap); 2162 _SOC_IF_ERR_EXIT(rv); 2163 2164 exit: 2165 SOC_FUNC_RETURN; 2166 } 2167 2168 int pm12x10_port_encap_set (int unit, soc_port_t port, pm_info_t pm_info, 2169 int flags, portmod_encap_t encap) 2170 { 2171 int rv = 0; 2172 SOC_INIT_FUNC_DEFS; 2173 2174 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_encap_set(unit, 2175 port, PM_4X25_INFO(pm_info), flags, encap); 2176 _SOC_IF_ERR_EXIT(rv); 2177 2178 exit: 2179 SOC_FUNC_RETURN; 2180 } 2181 2182 2183 int pm12x10_port_higig_mode_set (int unit, soc_port_t port, pm_info_t pm_info, int mode) 2184 { 2185 int rv = 0; 2186 SOC_INIT_FUNC_DEFS; 2187 2188 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_higig_mode_set(unit, 2189 port, PM_4X25_INFO(pm_info), mode); 2190 _SOC_IF_ERR_EXIT(rv); 2191 2192 exit: 2193 SOC_FUNC_RETURN; 2194 } 2195 2196 int pm12x10_port_higig_mode_get (int unit, soc_port_t port, pm_info_t pm_info, int *mode) 2197 { 2198 int rv = 0; 2199 SOC_INIT_FUNC_DEFS; 2200 2201 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_higig_mode_get(unit, 2202 port, PM_4X25_INFO(pm_info), mode); 2203 _SOC_IF_ERR_EXIT(rv); 2204 2205 exit: 2206 SOC_FUNC_RETURN; 2207 } 2208 2209 int pm12x10_port_higig2_mode_get (int unit, soc_port_t port, pm_info_t pm_info, int *mode) 2210 { 2211 int rv = 0; 2212 SOC_INIT_FUNC_DEFS; 2213 2214 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_higig2_mode_get(unit, 2215 port, PM_4X25_INFO(pm_info), mode); 2216 _SOC_IF_ERR_EXIT(rv); 2217 2218 exit: 2219 SOC_FUNC_RETURN; 2220 } 2221 2222 int pm12x10_port_higig2_mode_set (int unit, soc_port_t port, pm_info_t pm_info, int mode) 2223 { 2224 int rv = 0; 2225 SOC_INIT_FUNC_DEFS; 2226 2227 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_higig2_mode_set(unit, 2228 port, PM_4X25_INFO(pm_info), mode); 2229 _SOC_IF_ERR_EXIT(rv); 2230 2231 exit: 2232 SOC_FUNC_RETURN; 2233 } 2234 2235 2236 int pm12x10_port_config_port_type_get (int unit, soc_port_t port, pm_info_t pm_info, int *type) 2237 2238 { 2239 int rv = 0; 2240 SOC_INIT_FUNC_DEFS; 2241 2242 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_config_port_type_get(unit, 2243 port, PM_4X25_INFO(pm_info), type); 2244 _SOC_IF_ERR_EXIT(rv); 2245 2246 exit: 2247 SOC_FUNC_RETURN; 2248 } 2249 2250 int pm12x10_port_config_port_type_set (int unit, soc_port_t port, pm_info_t pm_info, int type) 2251 { 2252 int rv = 0; 2253 SOC_INIT_FUNC_DEFS; 2254 2255 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_config_port_type_set(unit, 2256 port, PM_4X25_INFO(pm_info), type); 2257 _SOC_IF_ERR_EXIT(rv); 2258 2259 exit: 2260 SOC_FUNC_RETURN; 2261 } 2262 2263 int 2264 pm12x10_port_trunk_hwfailover_config_set (int unit, soc_port_t port, 2265 pm_info_t pm_info, int hw_count) 2266 { 2267 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_trunk_hwfailover_config_set(unit, 2268 port, PM_4X25_INFO(pm_info), hw_count)); 2269 } 2270 2271 2272 int 2273 pm12x10_port_trunk_hwfailover_config_get(int unit, soc_port_t port, pm_info_t pm_info, 2274 int *enable) 2275 { 2276 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_trunk_hwfailover_config_get(unit, 2277 port, PM_4X25_INFO(pm_info), enable)); 2278 } 2279 2280 int 2281 pm12x10_port_trunk_hwfailover_status_get(int unit, soc_port_t port, pm_info_t pm_info, 2282 int *loopback) 2283 { 2284 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_trunk_hwfailover_status_get(unit, 2285 port, PM_4X25_INFO(pm_info), loopback)); 2286 } 2287 2288 int pm12x10_port_diag_ctrl(int unit, soc_port_t port, pm_info_t pm_info, 2289 uint32 inst, int op_type, int op_cmd, const void *arg) 2290 { 2291 2292 phymod_phy_access_t phy_access_raw[1+MAX_PHYN]; 2293 phymod_phy_access_t *phy_access; 2294 phymod_tx_t ln_txparam; 2295 int nof_phys=0; 2296 int i=0; 2297 uint32 lane_map; 2298 uint32 saved_lane_mask[3]; 2299 portmod_access_get_params_t params; 2300 uint32 sum=0, value=0 ; 2301 2302 2303 SOC_IF_ERROR_RETURN(portmod_access_get_params_t_init(unit, ¶ms)); 2304 SOC_IF_ERROR_RETURN(phymod_tx_t_init(&ln_txparam)); 2305 2306 if( PHY_DIAG_INST_DEV(inst) == PHY_DIAG_DEV_INT ) { 2307 params.phyn = 0 ; 2308 } else { 2309 /* most external PHY_DIAG_DEV_DFLT and PHY_DIAG_DEV_EXT */ 2310 params.phyn = -1 ; 2311 } 2312 2313 if(PHY_DIAG_INST_INTF(inst) == PHY_DIAG_INTF_SYS ){ 2314 params.sys_side = PORTMOD_SIDE_SYSTEM; 2315 } else { /* line side is default */ 2316 params.sys_side = PORTMOD_SIDE_LINE; 2317 } 2318 2319 params.apply_lane_mask = 1; 2320 2321 SOC_IF_ERROR_RETURN(pm12x10_port_phy_lane_access_get(unit, port, pm_info, 2322 ¶ms, 3, phy_access_raw, &nof_phys, NULL)); 2323 2324 /* if the phys are identical, consolidate lane mask and run once. */ 2325 if ( nof_phys == 3 ){ 2326 for(i=0; i < nof_phys; i++) { 2327 saved_lane_mask[i] = phy_access_raw[i].access.lane_mask; 2328 phy_access_raw[i].access.lane_mask = 0; /* need this to do compare. */ 2329 } 2330 2331 if( !sal_memcmp( &phy_access_raw[0],&phy_access_raw[1], sizeof(phymod_phy_access_t)) && 2332 !sal_memcmp( &phy_access_raw[0],&phy_access_raw[2], sizeof(phymod_phy_access_t))){ 2333 phy_access_raw[0].access.lane_mask = ( saved_lane_mask[0]| saved_lane_mask[1]| saved_lane_mask[2]); 2334 phymod_access_t_init(&phy_access_raw[1].access); 2335 phymod_access_t_init(&phy_access_raw[2].access); 2336 /* cli_out("Consolidating entries.\n"); */ 2337 nof_phys = 1; 2338 } else { 2339 /* restore lane mask */ 2340 for(i=0; i < nof_phys; i++) { 2341 phy_access_raw[i].access.lane_mask = saved_lane_mask[i]; 2342 } 2343 } 2344 } 2345 2346 for(i=0; i < nof_phys; i++) { 2347 2348 phy_access = &phy_access_raw[i]; 2349 lane_map = phy_access->access.lane_mask; 2350 2351 switch(op_cmd) { 2352 case PHY_DIAG_CTRL_DSC: 2353 LOG_INFO(BSL_LS_SOC_PHY, 2354 (BSL_META_U(unit, 2355 "pm4x10_port_diag_ctrl: " 2356 "u=%d p=%d PHY_DIAG_CTRL_DSC 0x%x\n"), 2357 unit, port, PHY_DIAG_CTRL_DSC)); 2358 2359 SOC_IF_ERROR_RETURN 2360 (portmod_port_phychain_pmd_info_dump(unit, phy_access, 1, 2361 (void*)arg)); 2362 break; 2363 2364 case PHY_DIAG_CTRL_PCS: 2365 LOG_INFO(BSL_LS_SOC_PHY, 2366 (BSL_META_U(unit, 2367 "pm4x10_port_diag_ctrl: " 2368 "u=%d p=%d PHY_DIAG_CTRL_PCS 0x%x\n"), 2369 unit, port, PHY_DIAG_CTRL_PCS)); 2370 2371 SOC_IF_ERROR_RETURN 2372 (portmod_port_phychain_pcs_info_dump(unit, phy_access, 1, 2373 (void*)arg)); 2374 break; 2375 2376 case PHY_DIAG_CTRL_LINKMON_MODE: 2377 LOG_INFO(BSL_LS_SOC_PHY, 2378 (BSL_META_U(unit, 2379 "pm4x10_port_diag_ctrl: " 2380 "u=%d p=%d PHY_DIAG_CTRL_LINKMON_MODE 0x%x\n"), 2381 unit, port, PHY_DIAG_CTRL_LINKMON_MODE)); 2382 2383 if(phy_access[0].access.lane_mask){ 2384 SOC_IF_ERROR_RETURN 2385 (portmod_pm_phy_link_mon_enable_set(phy_access, 1, PTR_TO_INT(arg))); 2386 } 2387 break; 2388 2389 case PHY_DIAG_CTRL_LINKMON_STATUS: 2390 LOG_INFO(BSL_LS_SOC_PHY, 2391 (BSL_META_U(unit, 2392 "pm4x10_port_diag_ctrl: " 2393 "u=%d p=%d PHY_DIAG_CTRL_LINKMON_STATUS 0x%x\n"), 2394 unit, port, PHY_DIAG_CTRL_LINKMON_STATUS)); 2395 2396 if(phy_access[0].access.lane_mask){ 2397 SOC_IF_ERROR_RETURN 2398 (portmod_pm_phy_link_mon_status_get(phy_access, 1)); 2399 } 2400 break; 2401 2402 2403 default: 2404 if(op_type == PHY_DIAG_CTRL_SET) { 2405 LOG_INFO(BSL_LS_SOC_PHY, 2406 (BSL_META_U(unit, 2407 "pm4x10_port_diag_ctrl: " 2408 "u=%d p=%d PHY_DIAG_CTRL_SET 0x%x\n"), 2409 unit, port, PHY_DIAG_CTRL_SET)); 2410 if (!SAL_BOOT_SIMULATION) { 2411 if( !(phy_access->access.lane_mask == 0)){ 2412 SOC_IF_ERROR_RETURN(portmod_pm_phy_control_set(phy_access, 1, op_cmd, &ln_txparam, lane_map, PTR_TO_INT(arg))); 2413 } 2414 } 2415 } else if(op_type == PHY_DIAG_CTRL_GET) { 2416 LOG_INFO(BSL_LS_SOC_PHY, 2417 (BSL_META_U(unit, 2418 "pm4x10_port_diag_ctrl: " 2419 "u=%d p=%d PHY_DIAG_CTRL_GET 0x%x\n"), 2420 unit, port, PHY_DIAG_CTRL_GET)); 2421 if (!SAL_BOOT_SIMULATION) { 2422 if( !(phy_access->access.lane_mask == 0)){ 2423 SOC_IF_ERROR_RETURN(portmod_pm_phy_control_get(phy_access,1,op_cmd, &ln_txparam, lane_map, (uint32 *)arg)); 2424 } else { 2425 *(uint32 *)arg = 0; 2426 } 2427 } 2428 } else { 2429 return (SOC_E_UNAVAIL); 2430 } 2431 break ; 2432 } 2433 if(op_type == (int)PHY_DIAG_CTRL_GET) { 2434 if(op_cmd == (int)SOC_PHY_CONTROL_PRBS_RX_STATUS) { 2435 /* prbs error count/flag accumulation */ 2436 /* SDK-69842 only the center (last core) 4-lane prbs reported */ 2437 value = *(uint32 *)arg ; 2438 if((value==(uint32)(-1))||(value==(uint32)(-2))) { 2439 if(sum==(uint32)(-1)) { 2440 *(uint32 *)arg = sum ; 2441 } else { 2442 *(uint32 *)arg = value ; 2443 sum = value ; 2444 } 2445 } else { 2446 if(sum!=(uint32)(-1)&&(sum!=(uint32)(-2))) { 2447 sum = sum+ value ; 2448 } 2449 *(uint32 *)arg = sum ; 2450 } 2451 } 2452 } 2453 } /* for */ 2454 2455 return PHYMOD_E_NONE; 2456 } 2457 2458 int 2459 pm12x10_port_ref_clk_get(int unit, soc_port_t port, pm_info_t pm_info, int *ref_clk) 2460 { 2461 return (PM_4X10_DRIVER(pm_info,2)->f_portmod_port_ref_clk_get(unit, 2462 port, PM_4X10_INFO(pm_info,2), ref_clk)); 2463 } 2464 2465 int pm12x10_port_lag_remove_failover_lpbk_get(int unit, int port, pm_info_t pm_info, int *val) 2466 { 2467 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_lag_remove_failover_lpbk_get(unit, 2468 port, PM_4X25_INFO(pm_info), val)); 2469 } 2470 2471 int pm12x10_port_lag_remove_failover_lpbk_set(int unit, int port, pm_info_t pm_info, int val) 2472 { 2473 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_lag_remove_failover_lpbk_set(unit, 2474 port, PM_4X25_INFO(pm_info), val)); 2475 } 2476 2477 int pm12x10_port_lag_failover_disable(int unit, int port, pm_info_t pm_info) 2478 { 2479 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_lag_failover_disable(unit, 2480 port, PM_4X25_INFO(pm_info))); 2481 } 2482 2483 int pm12x10_port_cntmaxsize_get(int unit, int port, pm_info_t pm_info, int *val) 2484 { 2485 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_cntmaxsize_get(unit, 2486 port, PM_4X25_INFO(pm_info), val)); 2487 } 2488 2489 int pm12x10_port_cntmaxsize_set(int unit, int port, pm_info_t pm_info, int val) 2490 { 2491 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_cntmaxsize_set(unit, 2492 port, PM_4X25_INFO(pm_info), val)); 2493 } 2494 2495 2496 int pm12x10_port_mac_ctrl_set(int unit, int port, 2497 pm_info_t pm_info, uint64 ctrl) 2498 { 2499 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_mac_ctrl_set(unit, 2500 port, PM_4X25_INFO(pm_info), ctrl)); 2501 } 2502 2503 int pm12x10_port_drain_cell_get(int unit, int port, 2504 pm_info_t pm_info, portmod_drain_cells_t *drain_cells) 2505 { 2506 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_drain_cell_get(unit, 2507 port, PM_4X25_INFO(pm_info), drain_cells)); 2508 } 2509 2510 int pm12x10_port_drain_cell_stop (int unit, int port, 2511 pm_info_t pm_info, portmod_drain_cells_t *drain_cells) 2512 { 2513 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_drain_cell_stop(unit, 2514 port, PM_4X25_INFO(pm_info), drain_cells)); 2515 } 2516 2517 int pm12x10_port_drain_cell_start(int unit, int port, pm_info_t pm_info) 2518 { 2519 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_drain_cell_start(unit, 2520 port, PM_4X25_INFO(pm_info))); 2521 } 2522 2523 int pm12x10_port_txfifo_cell_cnt_get(int unit, int port, 2524 pm_info_t pm_info, uint32* fval) 2525 { 2526 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_txfifo_cell_cnt_get(unit, 2527 port, PM_4X25_INFO(pm_info), fval)); 2528 } 2529 2530 int pm12x10_port_egress_queue_drain_get(int unit, int port, 2531 pm_info_t pm_info, uint64 *ctrl, int *rx) 2532 { 2533 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_egress_queue_drain_get(unit, 2534 port, PM_4X25_INFO(pm_info), ctrl, rx)); 2535 } 2536 2537 int pm12x10_port_drain_cells_rx_enable (int unit, int port, 2538 pm_info_t pm_info, int rx_en) 2539 { 2540 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_drain_cells_rx_enable (unit, 2541 port, PM_4X25_INFO(pm_info), rx_en)); 2542 } 2543 2544 int pm12x10_port_egress_queue_drain_rx_en(int unit, int port, 2545 pm_info_t pm_info, int rx_en) 2546 { 2547 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_egress_queue_drain_rx_en (unit, 2548 port, PM_4X25_INFO(pm_info), rx_en)); 2549 } 2550 2551 int pm12x10_port_mac_reset_set(int unit, int port, 2552 pm_info_t pm_info, int val) 2553 { 2554 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_mac_reset_set (unit, 2555 port, PM_4X25_INFO(pm_info), val)); 2556 } 2557 2558 int pm12x10_port_mac_reset_get(int unit, int port, pm_info_t pm_info, int* val) 2559 { 2560 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_mac_reset_get (unit, 2561 port, PM_4X25_INFO(pm_info), val)); 2562 } 2563 2564 int pm12x10_port_soft_reset_toggle (int unit, int port, pm_info_t pm_info, int idx) 2565 { 2566 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_soft_reset_toggle (unit, 2567 port, PM_4X25_INFO(pm_info), idx)); 2568 } 2569 2570 int pm12x10_port_mac_reset_check(int unit, int port, pm_info_t pm_info, int enable, int* reset) 2571 { 2572 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_mac_reset_check(unit, 2573 port, PM_4X25_INFO(pm_info), enable, reset)); 2574 } 2575 2576 int pm12x10_pm4x10_enable(int unit, int port, uint32 phy, uint32 enable) 2577 { 2578 pm_info_t pm_info; 2579 int found = 0, quad, i, phy_i; 2580 uint32 soft_reset, power_save; 2581 soc_port_if_t if_type; 2582 SOC_INIT_FUNC_DEFS; 2583 2584 /* get PM info */ 2585 _SOC_IF_ERR_EXIT(portmod_pm_info_type_get(unit, port, portmodDispatchTypePm12x10, &pm_info)); 2586 2587 if(!pm_info->pm_data.pm12x10_db->external_top_mode) { 2588 /* get inteface type */ 2589 _SOC_IF_ERR_EXIT(portmod_port_interface_type_get(unit, port, &if_type)); 2590 2591 /* Find quad */ 2592 i=0; 2593 quad=-1; 2594 PORTMOD_PBMP_ITER(PM_12x10_INFO(pm_info)->phys, phy_i) { 2595 if(i%4 == 0) { 2596 quad++; 2597 } 2598 if(phy_i == phy) { 2599 found = 1; 2600 break; 2601 } 2602 i++; 2603 } 2604 2605 if(!found) { 2606 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, (_SOC_MSG("Phy invalid for current PM"))); 2607 } 2608 2609 /* Enable block */ 2610 _SOC_IF_ERR_EXIT(READ_CXX_CXXPORT_SOFT_RESETr(unit, port, &soft_reset)); 2611 _SOC_IF_ERR_EXIT(READ_CXX_CXXPORT_POWER_SAVEr(unit, port, &power_save)); 2612 2613 switch(quad) { 2614 case 0: 2615 soc_reg_field_set(unit, CXX_CXXPORT_SOFT_RESETr, &soft_reset, CORE0_RSTf, enable ? 0 : 1); 2616 soc_reg_field_set(unit, CXX_CXXPORT_POWER_SAVEr, &power_save, CORE0_PWRDWNf, enable ? 0 : 1); 2617 break; 2618 case 1: 2619 soc_reg_field_set(unit, CXX_CXXPORT_SOFT_RESETr, &soft_reset, CORE1_RSTf, enable ? 0 : 1); 2620 soc_reg_field_set(unit, CXX_CXXPORT_POWER_SAVEr, &power_save, CORE1_PWRDWNf, enable ? 0 : 1); 2621 break; 2622 case 2: 2623 soc_reg_field_set(unit, CXX_CXXPORT_SOFT_RESETr, &soft_reset, CORE2_RSTf, enable ? 0 : 1); 2624 soc_reg_field_set(unit, CXX_CXXPORT_POWER_SAVEr, &power_save, CORE2_PWRDWNf, enable ? 0 : 1); 2625 break; 2626 default: 2627 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, (_SOC_MSG("Invalid quad"))); 2628 } 2629 2630 /* PM4x25 reset */ 2631 if(if_type != SOC_PORT_IF_CAUI) { 2632 soc_reg_field_set(unit, CXX_CXXPORT_SOFT_RESETr, &soft_reset, CORE3_RSTf, 1); /* always in reset */ 2633 soc_reg_field_set(unit, CXX_CXXPORT_POWER_SAVEr, &power_save, CORE3_PWRDWNf, 1); /* always power down */ 2634 } else { 2635 soc_reg_field_set(unit, CXX_CXXPORT_SOFT_RESETr, &soft_reset, CORE3_RSTf, enable ? 0 : 1); 2636 soc_reg_field_set(unit, CXX_CXXPORT_POWER_SAVEr, &power_save, CORE3_PWRDWNf, enable ? 0 : 1); 2637 } 2638 2639 if(enable) { 2640 _SOC_IF_ERR_EXIT(WRITE_CXX_CXXPORT_POWER_SAVEr(unit, port, power_save)); 2641 _SOC_IF_ERR_EXIT(WRITE_CXX_CXXPORT_SOFT_RESETr(unit, port, soft_reset)); 2642 } else { 2643 _SOC_IF_ERR_EXIT(WRITE_CXX_CXXPORT_SOFT_RESETr(unit, port, soft_reset)); 2644 _SOC_IF_ERR_EXIT(WRITE_CXX_CXXPORT_POWER_SAVEr(unit, port, power_save)); 2645 } 2646 } 2647 2648 exit: 2649 SOC_FUNC_RETURN; 2650 } 2651 2652 int pm12x10_pm4x10_tsc_reset(int unit, int port, uint32 phy, uint32 in_reset) 2653 { 2654 pm_info_t pm_info; 2655 int found = 0, quad, i, phy_i; 2656 uint32 reg_val; 2657 SOC_INIT_FUNC_DEFS; 2658 2659 /* get PM info */ 2660 _SOC_IF_ERR_EXIT(portmod_pm_info_type_get(unit, port, portmodDispatchTypePm12x10, &pm_info)); 2661 2662 if(!pm_info->pm_data.pm12x10_db->external_top_mode) { 2663 /* Find quad */ 2664 i=0; 2665 quad=-1; 2666 PORTMOD_PBMP_ITER(PM_12x10_INFO(pm_info)->phys, phy_i) { 2667 if(i%4 == 0) { 2668 quad++; 2669 } 2670 if(phy_i == phy) { 2671 found = 1; 2672 break; 2673 } 2674 i++; 2675 } 2676 2677 if(!found) { 2678 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, (_SOC_MSG("Phy invalid for current PM"))); 2679 } 2680 2681 /* Enable block */ 2682 switch(quad) { 2683 case 0: 2684 _SOC_IF_ERR_EXIT(READ_CXX_CXXPORT_XGXS_0_CTRL_0_REGr(unit, port, ®_val)); 2685 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_0_REGr, ®_val, RSTB_HWf, in_reset ? 0 : 1); 2686 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_0_REGr, ®_val, PWRDWNf, in_reset ? 1 : 0); 2687 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_0_REGr, ®_val, IDDQf, in_reset ? 1 : 0); 2688 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_0_REGr, ®_val, REFOUT_ENf, 2689 (pm_info->pm_data.pm12x10_db->refclk_source == 0)? 1 : 0); 2690 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_0_REGr, ®_val, REFIN_ENf, 2691 (pm_info->pm_data.pm12x10_db->refclk_source == 0)? 0 : 1); 2692 _SOC_IF_ERR_EXIT(WRITE_CXX_CXXPORT_XGXS_0_CTRL_0_REGr(unit, port, reg_val)); 2693 break; 2694 case 1: 2695 _SOC_IF_ERR_EXIT(READ_CXX_CXXPORT_XGXS_0_CTRL_1_REGr(unit, port, ®_val)); 2696 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_1_REGr, ®_val, RSTB_HWf, in_reset ? 0 : 1); 2697 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_1_REGr, ®_val, PWRDWNf, in_reset ? 1 : 0); 2698 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_1_REGr, ®_val, IDDQf, in_reset ? 1 : 0); 2699 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_1_REGr, ®_val, REFOUT_ENf, 2700 (pm_info->pm_data.pm12x10_db->refclk_source == 1)? 1 : 0); 2701 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_1_REGr, ®_val, REFIN_ENf, 2702 (pm_info->pm_data.pm12x10_db->refclk_source == 1)? 0 : 1); 2703 _SOC_IF_ERR_EXIT(WRITE_CXX_CXXPORT_XGXS_0_CTRL_1_REGr(unit, port, reg_val)); 2704 break; 2705 case 2: 2706 _SOC_IF_ERR_EXIT(READ_CXX_CXXPORT_XGXS_0_CTRL_2_REGr(unit, port, ®_val)); 2707 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_2_REGr, ®_val, RSTB_HWf, in_reset ? 0 : 1); 2708 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_2_REGr, ®_val, PWRDWNf, in_reset ? 1 : 0); 2709 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_2_REGr, ®_val, IDDQf, in_reset ? 1 : 0); 2710 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_2_REGr, ®_val, REFOUT_ENf, 2711 (pm_info->pm_data.pm12x10_db->refclk_source == 2)? 1 : 0); 2712 soc_reg_field_set (unit, CXX_CXXPORT_XGXS_0_CTRL_2_REGr, ®_val, REFIN_ENf, 2713 (pm_info->pm_data.pm12x10_db->refclk_source == 2)? 0 : 1); 2714 _SOC_IF_ERR_EXIT(WRITE_CXX_CXXPORT_XGXS_0_CTRL_2_REGr(unit, port, reg_val)); 2715 break; 2716 default: 2717 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, (_SOC_MSG("Invalid quad"))); 2718 } 2719 } 2720 2721 exit: 2722 SOC_FUNC_RETURN; 2723 } 2724 2725 int pm12x10_port_core_num_get(int unit, int port, pm_info_t pm_info, int* core_num) 2726 { 2727 int rv = 0, i; 2728 SOC_INIT_FUNC_DEFS; 2729 2730 for(i = 0 ; i < 3 ; i++) 2731 { 2732 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_core_num_get(unit, port, 2733 PM_4X10_INFO(pm_info,i), core_num); 2734 _SOC_IF_ERR_EXIT(rv); 2735 } 2736 2737 exit: 2738 SOC_FUNC_RETURN; 2739 } 2740 2741 2742 int pm12x10_ext_phy_attach_to_pm(int unit, pm_info_t pm_info, const phymod_core_access_t* ext_phy_access, uint32 first_phy_lane) 2743 { 2744 /* empty happy function. */ 2745 return SOC_E_NONE; 2746 } 2747 2748 2749 int pm12x10_ext_phy_detach_from_pm(int unit, pm_info_t pm_info, phymod_core_access_t* ext_phy_access) 2750 { 2751 /* empty happy function. */ 2752 return SOC_E_NONE; 2753 } 2754 2755 int pm12x10_xphy_lane_attach_to_pm(int unit, pm_info_t pm_info, int iphy, int phyn, const portmod_xphy_lane_connection_t* lane_connection) 2756 { 2757 /* empty happy function. */ 2758 return SOC_E_NONE; 2759 } 2760 2761 2762 int pm12x10_xphy_lane_detach_from_pm(int unit, pm_info_t pm_info, int iphy, int phyn, portmod_xphy_lane_connection_t* lane_connection) 2763 { 2764 /* empty happy function. */ 2765 return SOC_E_NONE; 2766 } 2767 2768 /*! 2769 * pm12x10_port_speed_get 2770 * 2771 * @brief port speed get 2772 * 2773 * @param [in] unit - unit id 2774 * @param [in] port - logical port 2775 * @param [in] speed - 2776 */ 2777 int pm12x10_port_speed_get(int unit, int port, pm_info_t pm_info, int* speed) 2778 { 2779 return (PM_4X10_DRIVER(pm_info,2)->f_portmod_port_speed_get(unit, 2780 port, PM_4X10_INFO(pm_info,2), speed)); 2781 } 2782 2783 /*Port discard set*/ 2784 int pm12x10_port_discard_set(int unit, int port, pm_info_t pm_info, int discard) 2785 { 2786 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_discard_set(unit, 2787 port, PM_4X25_INFO(pm_info), discard)); 2788 } 2789 2790 /*Port soft reset set set*/ 2791 int pm12x10_port_soft_reset_set(int unit, int port, pm_info_t pm_info, int idx, 2792 int val, int flags) 2793 { 2794 int rv = 0, i; 2795 SOC_INIT_FUNC_DEFS; 2796 2797 for(i = 0 ; i < 3 ; i++) 2798 { 2799 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_soft_reset_set(unit, port, 2800 PM_4X10_INFO(pm_info,i), idx, val, flags); 2801 _SOC_IF_ERR_EXIT(rv); 2802 } 2803 exit: 2804 SOC_FUNC_RETURN; 2805 } 2806 2807 /*Port tx_en=0 and softreset mac*/ 2808 int pm12x10_port_tx_down(int unit, int port, pm_info_t pm_info) 2809 { 2810 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_tx_down(unit, 2811 port, PM_4X25_INFO(pm_info))); 2812 } 2813 2814 int pm12x10_port_rx_mac_enable_set(int unit, int port, pm_info_t pm_info, int enable) 2815 { 2816 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_rx_mac_enable_set(unit, 2817 port, PM_4X25_INFO(pm_info), enable)); 2818 } 2819 2820 int pm12x10_port_rx_mac_enable_get(int unit, int port, pm_info_t pm_info, int* enable) 2821 { 2822 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_rx_mac_enable_get(unit, 2823 port, PM_4X25_INFO(pm_info), enable)); 2824 } 2825 2826 int pm12x10_port_tx_mac_enable_set(int unit, int port, pm_info_t pm_info, int enable) 2827 { 2828 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_tx_mac_enable_set(unit, 2829 port, PM_4X25_INFO(pm_info), enable)); 2830 } 2831 2832 int pm12x10_port_tx_mac_enable_get(int unit, int port, pm_info_t pm_info, int* enable) 2833 { 2834 return (PM_4X25_DRIVER(pm_info)->f_portmod_port_tx_mac_enable_get(unit, 2835 port, PM_4X25_INFO(pm_info), enable)); 2836 } 2837 2838 /* 2839 * Flex port PGW reconfigure sequence for 100G. 2840 * 2841 * 1. XLPORT_SOFT_RESET to 1 for all 12 lanes 2842 * - pm4x10_portmod_port_soft_reset_set 2843 * (XLPORT_SOFT_RESET should be controlled by physical port basis. 2844 * flags : PORTMOD_PORT_REG_ACCESS_DIRECT) 2845 * 2846 * 2. XLPORT/XLMAC down sequence 2847 * - pm4x10_port_pgw_reconfig(flag : PORTMOD_PORT_PGW_MAC_RESET) 2848 * 2849 * 3. CPORT/CLMAC down sequence 2850 * - pm4x25td_port_pgw_reconfig(flag : PORTMOD_PORT_PGW_MAC_RESET) 2851 * 2852 * 4. XLPORT up sequence1 2853 * - pm4x10_port_pgw_reconfig(flag : PORTMOD_PORT_PGW_POWER_SAVE) 2854 * 2855 * 5. CPORT/CLMAC up sequence 2856 * - pm4x25td_port_pgw_reconfig(flag : PORTMOD_PORT_PGW_MAC_UNRESET) 2857 * 2858 * 6. XLPORT up sequence2 2859 * - pm4x10_port_pgw_reconfig(flag : PORTMOD_PORT_PGW_MAC_UNRESET) 2860 * 2861 * 7. XLPORT_SOFT_RESET to 0 for all 12 lanes 2862 * - pm4x10_portmod_port_soft_reset_set 2863 * (XLPORT_SOFT_RESET should be controlled by physical port basis. 2864 * flags : PORTMOD_PORT_REG_ACCESS_DIRECT) 2865 */ 2866 int pm12x10_port_pgw_reconfig (int unit, int port, pm_info_t pm_info, 2867 const portmod_port_mode_info_t *pmode, 2868 int first_port, int flags) 2869 { 2870 int rv = 0, i; 2871 int phy_idx, lane_idx; 2872 int phy_port; 2873 SOC_INIT_FUNC_DEFS; 2874 2875 /* phy_port is first physical port of 3 TSC Cores used by 100G */ 2876 for (phy_idx = 0; phy_idx < 3 ; ++phy_idx ) { 2877 for (lane_idx = 0; lane_idx < 4; ++lane_idx) { 2878 phy_port = first_port + 4*phy_idx+ lane_idx; 2879 rv = PM_4X10_DRIVER(pm_info, phy_idx)->f_portmod_port_soft_reset_set 2880 (unit, phy_port, PM_4X10_INFO(pm_info, phy_idx), lane_idx, 1, 2881 PORTMOD_PORT_REG_ACCESS_DIRECT); 2882 _SOC_IF_ERR_EXIT(rv); 2883 } 2884 } 2885 2886 for(i = 0 ; i < 3 ; i++) { 2887 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_pgw_reconfig(unit, port, 2888 PM_4X10_INFO(pm_info,i), pmode, first_port, 2889 PORTMOD_PORT_PGW_MAC_RESET); 2890 _SOC_IF_ERR_EXIT(rv); 2891 } 2892 2893 _SOC_IF_ERR_EXIT((PM_4X25_DRIVER(pm_info)->f_portmod_port_pgw_reconfig(unit, 2894 port, PM_4X25_INFO(pm_info), pmode, first_port, 2895 PORTMOD_PORT_PGW_MAC_RESET))); 2896 2897 for(i = 0 ; i < 3 ; i++) { 2898 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_pgw_reconfig(unit, port, 2899 PM_4X10_INFO(pm_info,i), pmode, first_port, 2900 PORTMOD_PORT_PGW_POWER_SAVE); 2901 _SOC_IF_ERR_EXIT(rv); 2902 } 2903 2904 _SOC_IF_ERR_EXIT((PM_4X25_DRIVER(pm_info)->f_portmod_port_pgw_reconfig(unit, 2905 port, PM_4X25_INFO(pm_info), pmode, first_port, 2906 PORTMOD_PORT_PGW_MAC_UNRESET))); 2907 2908 /* phy_port is first physical port of 3 TSC Cores used by 100G */ 2909 for (phy_idx = 0; phy_idx < 3 ; ++phy_idx ) { 2910 for (lane_idx = 0; lane_idx < 4; ++lane_idx) { 2911 phy_port = first_port + 4*phy_idx+ lane_idx; 2912 rv = PM_4X10_DRIVER(pm_info, phy_idx)->f_portmod_port_soft_reset_set 2913 (unit, phy_port, PM_4X10_INFO(pm_info, phy_idx), lane_idx, 0, 2914 PORTMOD_PORT_REG_ACCESS_DIRECT); 2915 _SOC_IF_ERR_EXIT(rv); 2916 } 2917 } 2918 2919 for(i = 0 ; i < 3 ; i++) { 2920 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_pgw_reconfig(unit, port, 2921 PM_4X10_INFO(pm_info,i), pmode, first_port, 2922 PORTMOD_PORT_PGW_MAC_UNRESET); 2923 _SOC_IF_ERR_EXIT(rv); 2924 } 2925 2926 exit: 2927 SOC_FUNC_RETURN; 2928 } 2929 2930 int pm12x10_port_notify(int unit, int port, pm_info_t pm_info, int link) { 2931 int i = 0; 2932 int rv = 0; 2933 int tmp_nof_phys; 2934 int is_most_ext_i; 2935 int is_change_speed = 0; 2936 portmod_access_get_params_t params; 2937 phymod_phy_access_t access[MAX_PHYN + 1]; 2938 portmod_port_interface_config_t interface_config; 2939 SOC_INIT_FUNC_DEFS; 2940 2941 for( i = 0 ; i < 3 ; i++){ 2942 _SOC_IF_ERR_EXIT(portmod_access_get_params_t_init(unit, ¶ms)); 2943 params.phyn = 0; 2944 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_phy_lane_access_get( 2945 unit, port, PM_4X10_INFO(pm_info, i), 2946 ¶ms, 1, &access[i], &tmp_nof_phys, &is_most_ext_i); 2947 _SOC_IF_ERR_EXIT(rv); 2948 2949 if (tmp_nof_phys > 1) { 2950 is_change_speed = 1; 2951 } 2952 2953 } 2954 2955 if (link && is_change_speed) { 2956 /* get the external phy interface config */ 2957 _SOC_IF_ERR_EXIT(portmod_port_interface_config_get(unit, 2958 port, 2959 &interface_config, 2960 PORTMOD_INIT_F_INTERNAL_SERDES_ONLY)); 2961 /* Set the interface config for internal phy only */ 2962 _SOC_IF_ERR_EXIT(portmod_port_interface_config_set(unit, 2963 port, 2964 &interface_config, 2965 PORTMOD_INIT_F_INTERNAL_SERDES_ONLY)); 2966 } else { 2967 /*TBD*/ 2968 } 2969 2970 exit: 2971 SOC_FUNC_RETURN; 2972 } 2973 2974 /* set interrupt value. */ 2975 int pm12x10_port_interrupt_enable_get (int unit, int port, pm_info_t pm_info, 2976 int intr_type, uint32 *val) 2977 { 2978 uint32 reg_val; 2979 SOC_INIT_FUNC_DEFS; 2980 2981 _SOC_IF_ERR_EXIT(READ_CXX_CXXPORT_INTR_ENABLEr(unit, port, ®_val)); 2982 2983 switch(intr_type) { 2984 case portmodIntrTypeCore0Intr: 2985 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_ENABLEr, reg_val, CORE0_INTf); 2986 break; 2987 case portmodIntrTypeCore1Intr: 2988 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_ENABLEr, reg_val, CORE1_INTf); 2989 break; 2990 case portmodIntrTypeCore2Intr: 2991 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_ENABLEr, reg_val, CORE2_INTf); 2992 break; 2993 case portmodIntrTypeCore3Intr: 2994 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_ENABLEr, reg_val, CORE3_INTf); 2995 break; 2996 case portmodIntrTypeTsc0Intr: 2997 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_ENABLEr, reg_val, TSC_0_INTf); 2998 break; 2999 case portmodIntrTypeTsc1Intr: 3000 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_ENABLEr, reg_val, TSC_0_INTf); 3001 break; 3002 case portmodIntrTypeTsc2Intr: 3003 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_ENABLEr, reg_val, TSC_0_INTf); 3004 break; 3005 3006 default: 3007 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Invalid interrupt type"))); 3008 break; 3009 } 3010 exit: 3011 SOC_FUNC_RETURN; 3012 } 3013 3014 /* set interrupt value. */ 3015 int pm12x10_port_interrupt_enable_set (int unit, int port, pm_info_t pm_info, 3016 int intr_type, uint32 val) 3017 { 3018 uint32 reg_val; 3019 SOC_INIT_FUNC_DEFS; 3020 3021 _SOC_IF_ERR_EXIT(READ_CXX_CXXPORT_INTR_ENABLEr(unit, port, ®_val)); 3022 3023 switch(intr_type) { 3024 case portmodIntrTypeCore0Intr: 3025 soc_reg_field_set(unit, CXX_CXXPORT_INTR_ENABLEr, ®_val, CORE0_INTf, val); 3026 break; 3027 case portmodIntrTypeCore1Intr: 3028 soc_reg_field_set(unit, CXX_CXXPORT_INTR_ENABLEr, ®_val, CORE1_INTf, val); 3029 break; 3030 case portmodIntrTypeCore2Intr: 3031 soc_reg_field_set(unit, CXX_CXXPORT_INTR_ENABLEr, ®_val, CORE2_INTf, val); 3032 break; 3033 case portmodIntrTypeCore3Intr: 3034 soc_reg_field_set(unit, CXX_CXXPORT_INTR_ENABLEr, ®_val, CORE3_INTf, val); 3035 break; 3036 case portmodIntrTypeTsc0Intr: 3037 soc_reg_field_set(unit, CXX_CXXPORT_INTR_ENABLEr, ®_val, TSC_0_INTf, val); 3038 break; 3039 case portmodIntrTypeTsc1Intr: 3040 soc_reg_field_set(unit, CXX_CXXPORT_INTR_ENABLEr, ®_val, TSC_0_INTf, val); 3041 break; 3042 case portmodIntrTypeTsc2Intr: 3043 soc_reg_field_set(unit, CXX_CXXPORT_INTR_ENABLEr, ®_val, TSC_0_INTf, val); 3044 break; 3045 3046 default: 3047 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Invalid interrupt type"))); 3048 break; 3049 } 3050 _SOC_IF_ERR_EXIT(WRITE_CXX_CXXPORT_INTR_ENABLEr(unit, port, reg_val)); 3051 exit: 3052 SOC_FUNC_RETURN; 3053 } 3054 3055 /* get interrupt value. */ 3056 int pm12x10_port_interrupt_get (int unit, int port, pm_info_t pm_info, 3057 int intr_type, uint32* val) 3058 { 3059 uint32 reg_val; 3060 SOC_INIT_FUNC_DEFS; 3061 3062 _SOC_IF_ERR_EXIT(READ_CXX_CXXPORT_INTR_STATUSr(unit, port, ®_val)); 3063 3064 switch(intr_type) { 3065 case portmodIntrTypeCore0Intr: 3066 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, CORE0_INTf); 3067 break; 3068 case portmodIntrTypeCore1Intr: 3069 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, CORE1_INTf); 3070 break; 3071 case portmodIntrTypeCore2Intr: 3072 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, CORE2_INTf); 3073 break; 3074 case portmodIntrTypeCore3Intr: 3075 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, CORE3_INTf); 3076 break; 3077 case portmodIntrTypeTsc0Intr: 3078 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, TSC_0_INTf); 3079 break; 3080 case portmodIntrTypeTsc1Intr: 3081 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, TSC_1_INTf); 3082 break; 3083 case portmodIntrTypeTsc2Intr: 3084 *val = soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, TSC_2_INTf); 3085 break; 3086 3087 default: 3088 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Invalid interrupt type"))); 3089 break; 3090 } 3091 exit: 3092 SOC_FUNC_RETURN; 3093 } 3094 3095 int pm12x10_port_interrupts_get (int unit, int port, pm_info_t pm_info, 3096 int arr_max_size, uint32* intr_arr, uint32* size) 3097 { 3098 uint32 reg_val, cnt = 0; 3099 SOC_INIT_FUNC_DEFS; 3100 3101 _SOC_IF_ERR_EXIT(READ_CXX_CXXPORT_INTR_STATUSr(unit, port, ®_val)); 3102 3103 if (soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, CORE0_INTf)) { 3104 if (cnt >= arr_max_size) { 3105 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Insufficient Array size"))); 3106 } 3107 intr_arr[cnt++] = portmodIntrTypeCore0Intr; 3108 } 3109 3110 if (soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, CORE1_INTf)) { 3111 if (cnt >= arr_max_size) { 3112 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Insufficient Array size"))); 3113 } 3114 intr_arr[cnt++] = portmodIntrTypeCore1Intr; 3115 } 3116 3117 if (soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, CORE2_INTf)) { 3118 if (cnt >= arr_max_size) { 3119 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Insufficient Array size"))); 3120 } 3121 intr_arr[cnt++] = portmodIntrTypeCore2Intr; 3122 } 3123 3124 if (soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, CORE3_INTf)) { 3125 if (cnt >= arr_max_size) { 3126 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Insufficient Array size"))); 3127 } 3128 intr_arr[cnt++] = portmodIntrTypeCore3Intr; 3129 } 3130 3131 if (soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, TSC_0_INTf)) { 3132 if (cnt >= arr_max_size) { 3133 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Insufficient Array size"))); 3134 } 3135 intr_arr[cnt++] = portmodIntrTypeTsc0Intr; 3136 } 3137 3138 if (soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, TSC_1_INTf)) { 3139 if (cnt >= arr_max_size) { 3140 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Insufficient Array size"))); 3141 } 3142 intr_arr[cnt++] = portmodIntrTypeTsc1Intr; 3143 } 3144 3145 if (soc_reg_field_get(unit, CXX_CXXPORT_INTR_STATUSr, reg_val, TSC_2_INTf)) { 3146 if (cnt >= arr_max_size) { 3147 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Insufficient Array size"))); 3148 } 3149 intr_arr[cnt++] = portmodIntrTypeTsc2Intr; 3150 } 3151 3152 *size = cnt; 3153 3154 exit: 3155 SOC_FUNC_RETURN; 3156 } 3157 3158 3159 /*! 3160 * pm12x10_port_eee_clock_set 3161 * 3162 * @brief set EEE Config. 3163 * 3164 * @param [in] unit - unit id 3165 * @param [in] port - logical port 3166 * @param [in] eee - 3167 */ 3168 int pm12x10_port_eee_clock_set(int unit, int port, pm_info_t pm_info, 3169 const portmod_eee_clock_t* eee_clk) 3170 { 3171 return(PM_4X25_DRIVER(pm_info)->f_portmod_port_eee_clock_set (unit, 3172 port, PM_4X25_INFO(pm_info), eee_clk)); 3173 } 3174 3175 3176 /*! 3177 * pm12x10_port_eee_clock_get 3178 * 3179 * @brief set EEE Config. 3180 * 3181 * @param [in] unit - unit id 3182 * @param [in] port - logical port 3183 * @param [out] eee - 3184 */ 3185 int pm12x10_port_eee_clock_get (int unit, int port, pm_info_t pm_info, 3186 portmod_eee_clock_t* eee_clk) 3187 { 3188 return(PM_4X25_DRIVER(pm_info)->f_portmod_port_eee_clock_get (unit, 3189 port, PM_4X25_INFO(pm_info), eee_clk)); 3190 } 3191 3192 /*! 3193 * pm12x10_port_check_legacy_phy 3194 * 3195 * @brief portmod check if external phy is legacy 3196 * 3197 * @param [in] unit - unit id 3198 * @param [in] port - logical port 3199 * @param [out] legacy_phy - check if phy is legacy 3200 */ 3201 int pm12x10_port_check_legacy_phy(int unit, int port, pm_info_t pm_info, int* legacy_phy) 3202 { 3203 return(PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_check_legacy_phy(unit, 3204 port, PM_4X10_INFO(pm_info, 2), legacy_phy)); 3205 } 3206 3207 3208 int pm12x10_port_failover_mode_set(int unit, int port, pm_info_t pm_info, phymod_failover_mode_t failover) 3209 { 3210 int i, rv=0; 3211 3212 for (i = 0; !rv && (i < 3); i++) { 3213 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_failover_mode_set(unit, 3214 port, PM_4X10_INFO(pm_info, i), failover); 3215 } 3216 return (rv); 3217 } 3218 3219 int pm12x10_port_failover_mode_get(int unit, int port, pm_info_t pm_info, phymod_failover_mode_t* failover) 3220 { 3221 int i, rv=0; 3222 3223 for (i = 0; !rv && (i < 3); i++) { 3224 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_failover_mode_get(unit, 3225 port, PM_4X10_INFO(pm_info, i), failover); 3226 } 3227 return (rv); 3228 } 3229 3230 int pm12x10_port_mac_rsv_mask_set(int unit, int port, pm_info_t pm_info, uint32 rsv_mask) 3231 { 3232 int i, rv=0; 3233 3234 for (i = 0; !rv && (i < 3); i++) { 3235 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_mac_rsv_mask_set(unit, 3236 port, PM_4X10_INFO(pm_info, i), rsv_mask); 3237 } 3238 return (rv); 3239 } 3240 3241 int pm12x10_port_mib_reset_toggle(int unit, int port, pm_info_t pm_info, int port_index) 3242 { 3243 int i, rv=0; 3244 3245 for (i = 0; !rv && (i < 3); i++) { 3246 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_mib_reset_toggle(unit, 3247 port, PM_4X10_INFO(pm_info, i), port_index); 3248 } 3249 return (rv); 3250 } 3251 3252 int pm12x10_port_warmboot_db_restore(int unit, int port, pm_info_t pm_info, 3253 const portmod_port_interface_config_t *f_intf_config, 3254 const portmod_port_init_config_t *f_init_config, 3255 const int phy_op_mode) 3256 3257 { 3258 int i, rv=0; 3259 3260 for (i = 0; !rv && (i < 3); i++) { 3261 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_warmboot_db_restore(unit, 3262 port, PM_4X10_INFO(pm_info, i), f_intf_config, f_init_config, phy_op_mode); 3263 } 3264 return (rv); 3265 } 3266 3267 int pm12x10_port_flow_control_set (int unit, int port, pm_info_t pm_info, 3268 int merge_mode_en, int parallel_fc_en) 3269 { 3270 int i, rv=0; 3271 3272 for (i = 0; !rv && (i < 3); i++) { 3273 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_flow_control_set(unit, 3274 port, PM_4X10_INFO(pm_info, i), merge_mode_en, parallel_fc_en); 3275 } 3276 if (SOC_FAILURE(rv)) return (rv); 3277 3278 rv = (PM_4X25_DRIVER(pm_info)->f_portmod_port_flow_control_set (unit, 3279 port, PM_4X25_INFO(pm_info), merge_mode_en, parallel_fc_en)); 3280 return (rv); 3281 } 3282 3283 int pm12x10_port_update_dynamic_state(int unit, int port, pm_info_t pm_info, uint32_t port_dynamic_state) { 3284 int rv = 0, i; 3285 SOC_INIT_FUNC_DEFS; 3286 3287 for(i = 0 ; i < 3 ; i++) 3288 { 3289 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_update_dynamic_state(unit, port, 3290 PM_4X10_INFO(pm_info,i), port_dynamic_state); 3291 _SOC_IF_ERR_EXIT(rv); 3292 } 3293 exit: 3294 SOC_FUNC_RETURN; 3295 } 3296 3297 int pm12x10_port_phy_op_mode_get(int unit, int port, pm_info_t pm_info, phymod_operation_mode_t* val) 3298 { 3299 int rv = 0; 3300 int port_fallback_lane; 3301 3302 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_fallback_lane_get( 3303 unit, port, PM_4X10_INFO(pm_info, 2), &port_fallback_lane); 3304 3305 if (SOC_FAILURE(rv)) return (rv); 3306 3307 return (PM_4X10_DRIVER(pm_info, port_fallback_lane)->f_portmod_port_phy_op_mode_get( 3308 unit, port, PM_4X10_INFO(pm_info, port_fallback_lane), val)); 3309 3310 } 3311 3312 int pm12x10_port_medium_config_set(int unit, int port, pm_info_t pm_info, soc_port_medium_t medium, soc_phy_config_t* config) 3313 { 3314 int rv, i; 3315 SOC_INIT_FUNC_DEFS; 3316 3317 for(i = 0 ; i < 3 ; i++){ 3318 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_medium_config_set(unit, port, 3319 PM_4X10_INFO(pm_info, i), medium, config); 3320 if (SOC_FAILURE(rv)) return (rv); 3321 } 3322 3323 SOC_FUNC_RETURN; 3324 } 3325 3326 int pm12x10_port_medium_config_get(int unit, int port, pm_info_t pm_info, soc_port_medium_t medium, soc_phy_config_t* config) 3327 { 3328 int rv; 3329 SOC_INIT_FUNC_DEFS; 3330 3331 rv = PM_4X10_DRIVER(pm_info, 0)->f_portmod_port_medium_config_get(unit, port, 3332 PM_4X10_INFO(pm_info, 0), medium, config); 3333 if (SOC_FAILURE(rv)) return (rv); 3334 3335 SOC_FUNC_RETURN; 3336 } 3337 3338 int pm12x10_port_medium_get(int unit, int port, pm_info_t pm_info, soc_port_medium_t* medium) 3339 { 3340 int rv; 3341 SOC_INIT_FUNC_DEFS; 3342 3343 rv = PM_4X10_DRIVER(pm_info, 0)->f_portmod_port_medium_get(unit, port, 3344 PM_4X10_INFO(pm_info, 0), medium); 3345 if (SOC_FAILURE(rv)) return (rv); 3346 3347 SOC_FUNC_RETURN; 3348 } 3349 3350 int pm12x10_port_multi_get(int unit, int port, pm_info_t pm_info, portmod_multi_get_t* multi_get) 3351 { 3352 int rv; 3353 SOC_INIT_FUNC_DEFS; 3354 3355 rv = PM_4X10_DRIVER(pm_info, 0)->f_portmod_port_multi_get(unit, port, 3356 PM_4X10_INFO(pm_info, 0), multi_get); 3357 if (SOC_FAILURE(rv)) return (rv); 3358 3359 SOC_FUNC_RETURN; 3360 } 3361 3362 int pm12x10_port_update(int unit, int port, pm_info_t pm_info, const portmod_port_update_control_t* update_control) 3363 { 3364 3365 return (SOC_E_NONE); 3366 } 3367 3368 int pm12x10_port_lane_map_get(int unit, int port, pm_info_t pm_info, uint32 flags, phymod_lane_map_t* lane_map) 3369 { 3370 int i= 0,phy_port = 0,phy_pos = 0,core_num = 0; 3371 SOC_INIT_FUNC_DEFS; 3372 3373 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3374 SOC_PBMP_ITER(pm_info->pm_data.pm12x10_db->phys, i) { 3375 if (i == phy_port) { 3376 core_num = (phy_pos % PHYMOD_MAX_LANES_PER_PORT); 3377 break; 3378 } 3379 phy_pos++; 3380 } 3381 if ((core_num<3) && (PM_4X10_DRIVER(pm_info, core_num)->f_portmod_port_lane_map_get)) { 3382 _rv = PM_4X10_DRIVER(pm_info, core_num)->f_portmod_port_lane_map_get(unit, port, 3383 PM_4X10_INFO(pm_info, core_num), flags, lane_map); 3384 } else { 3385 _rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_lane_map_get(unit, port, 3386 PM_4X25_INFO(pm_info), flags, lane_map); 3387 } 3388 SOC_FUNC_RETURN; 3389 } 3390 3391 int pm12x10_port_lane_map_set(int unit, int port, pm_info_t pm_info, uint32 flags, phymod_lane_map_t* lane_map) 3392 { 3393 return SOC_E_NONE; 3394 } 3395 3396 int pm12x10_port_pll_div_get(int unit, int port, pm_info_t pm_info, 3397 const portmod_port_resources_t* port_resource, 3398 uint32_t* pll_div) 3399 { 3400 return SOC_E_NONE; 3401 } 3402 3403 int pm12x10_port_lane_count_get (int unit, int port, pm_info_t pm_info, int line_side, int* num_lanes) 3404 { 3405 3406 int rv, i; 3407 int local_num_lanes=1; 3408 SOC_INIT_FUNC_DEFS; 3409 3410 *num_lanes = 0; 3411 for(i = 0 ; i < 3 ; i++){ 3412 if(PM_4X10_DRIVER(pm_info, i)->f_portmod_port_lane_count_get != NULL){ 3413 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_lane_count_get(unit, port, 3414 PM_4X10_INFO(pm_info, i), line_side, &local_num_lanes); 3415 if (SOC_FAILURE(rv)) return (rv); 3416 *num_lanes += local_num_lanes ; 3417 } 3418 } 3419 SOC_FUNC_RETURN; 3420 } 3421 3422 int 3423 pm12x10_port_timestamp_adjust_set(int unit, int port, pm_info_t pm_info, 3424 soc_port_timestamp_adjust_t *ts_adjust) 3425 3426 { 3427 int rv = 0; 3428 SOC_INIT_FUNC_DEFS; 3429 3430 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_timestamp_adjust_set(unit, 3431 port, PM_4X25_INFO(pm_info), ts_adjust); 3432 _SOC_IF_ERR_EXIT(rv); 3433 3434 exit: 3435 SOC_FUNC_RETURN; 3436 3437 } 3438 3439 int pm12x10_port_timestamp_adjust_get(int unit, int port, pm_info_t pm_info, 3440 soc_port_timestamp_adjust_t *ts_adjust) 3441 { 3442 int rv = 0; 3443 SOC_INIT_FUNC_DEFS; 3444 3445 rv = PM_4X25_DRIVER(pm_info)->f_portmod_port_timestamp_adjust_get(unit, 3446 port, PM_4X25_INFO(pm_info), ts_adjust); 3447 _SOC_IF_ERR_EXIT(rv); 3448 3449 exit: 3450 SOC_FUNC_RETURN; 3451 3452 } 3453 3454 int pm12x10_port_cl72_set(int unit, int port, pm_info_t pm_info, uint32 enable) 3455 { 3456 portmod_port_interface_config_t config; 3457 int i =0, rv=0; 3458 3459 SOC_INIT_FUNC_DEFS; 3460 3461 _SOC_IF_ERR_EXIT 3462 (portmod_port_interface_config_t_init(unit, &config)); 3463 rv = PM_4X10_DRIVER(pm_info, 2)->f_portmod_port_interface_config_get( 3464 unit, port, PM_4X10_INFO(pm_info, 2), &config, PORTMOD_INIT_F_INTERNAL_SERDES_ONLY); 3465 _SOC_IF_ERR_EXIT(rv); 3466 /* speed disable */ 3467 config.flags |= PHYMOD_INTF_F_SET_SPD_DISABLE; 3468 _SOC_IF_ERR_EXIT (_pm12x10_internal_if_cfg_set (unit, port, pm_info, &config, 3469 PORTMOD_INIT_F_INTERNAL_SERDES_ONLY)); 3470 3471 for (i = 0 ; !rv && (i < 3) ; i++) { 3472 if (PM_4X10_DRIVER(pm_info, i)->f_portmod_port_cl72_set != NULL) { 3473 rv = PM_4X10_DRIVER(pm_info, i)->f_portmod_port_cl72_set( 3474 unit, port, PM_4X10_INFO(pm_info, i), enable); 3475 } 3476 } 3477 _SOC_IF_ERR_EXIT(rv); 3478 3479 exit: 3480 SOC_FUNC_RETURN; 3481 } 3482 3483 int pm12x10_port_cl72_get(int unit, int port, pm_info_t pm_info, uint32* enable) 3484 { 3485 int rv=0; 3486 SOC_INIT_FUNC_DEFS; 3487 3488 rv = PM_4X10_DRIVER(pm_info, 0)->f_portmod_port_cl72_get(unit, port, 3489 PM_4X10_INFO(pm_info, 0), enable); 3490 _SOC_IF_ERR_EXIT(rv); 3491 3492 exit: 3493 SOC_FUNC_RETURN; 3494 } 3495 3496 3497 #endif /* PORTMOD_PM12X10_SUPPORT */ 3498 3499 #undef _ERR_MSG_MODULE_NAME