cpm4x25.c (226105B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <soc/types.h> 11 #include <soc/error.h> 12 #include <soc/drv.h> 13 #include <soc/wb_engine.h> 14 #include <soc/portmod/portmod_internal.h> 15 #include <soc/portmod/portmod.h> 16 #include <soc/portmod/portmod_dispatch.h> 17 #include <soc/portmod/pm4x25.h> 18 #include <soc/portmod/pm4x25_shared.h> 19 20 21 #ifdef _ERR_MSG_MODULE_NAME 22 #error "_ERR_MSG_MODULE_NAME redefined" 23 #endif 24 #define _ERR_MSG_MODULE_NAME BSL_LS_SOC_PORT 25 26 #ifdef PORTMOD_CPM4X25_SUPPORT 27 28 extern int tscf_gen3_phy_loopback_set(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t enable); 29 extern int tscf_gen3_phy_loopback_get(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t* enable); 30 31 #define CPM4x25_WB_BUFFER_VERSION (8) 32 33 #define CPM4x25_IS_ACTIVE_SET(unit, pm_info, is_active) \ 34 SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isActive], &is_active) 35 #define CPM4x25_IS_ACTIVE_GET(unit, pm_info, is_active) \ 36 SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isActive], is_active) 37 38 #define CPM4x25_IS_INITIALIZED_SET(unit, pm_info, is_initialized) \ 39 SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isInitialized], &is_initialized) 40 #define CPM4x25_IS_INITIALIZED_GET(unit, pm_info, is_initialized) \ 41 SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isInitialized], is_initialized) 42 43 #define CPM4x25_IS_BYPASSED_SET(unit, pm_info, is_bypass) \ 44 SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isBypassed], &is_bypass) 45 #define CPM4x25_IS_BYPASSED_GET(unit, pm_info, is_bypass) \ 46 SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[isBypassed], is_bypass) 47 48 #define CPM4x25_LANE2PORT_SET(unit, pm_info, lane, port) \ 49 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[lane2portMap], &port, lane) 50 #define CPM4x25_LANE2PORT_GET(unit, pm_info, lane, port) \ 51 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[lane2portMap], port, lane) 52 53 #define CPM4x25_MAX_SPEED_SET(unit, pm_info, max_speed, port_index) \ 54 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[maxSpeed], &max_speed, port_index) 55 #define CPM4x25_MAX_SPEED_GET(unit, pm_info, max_speed, port_index) \ 56 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[maxSpeed], max_speed, port_index) 57 58 #define CPM4x25_INTERFACE_TYPE_SET(unit, pm_info, interface_type, port_index) \ 59 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[interfaceType], &interface_type, port_index) 60 #define CPM4x25_INTERFACE_TYPE_GET(unit, pm_info, interface_type, port_index) \ 61 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[interfaceType], interface_type, port_index) 62 63 #define CPM4x25_INTERFACE_MODES_SET(unit, pm_info, interface_modes, port_index) \ 64 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[interfaceModes], &interface_modes, port_index) 65 #define CPM4x25_INTERFACE_MODES_GET(unit, pm_info, interface_modes, port_index) \ 66 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[interfaceModes], interface_modes, port_index) 67 68 #define CPM4x25_THREE_PORTS_MODE_SET(unit, pm_info, three_ports_mode) \ 69 SOC_WB_ENGINE_SET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[threePortsMode], &three_ports_mode) 70 #define CPM4x25_THREE_PORTS_MODE_GET(unit, pm_info, three_ports_mode) \ 71 SOC_WB_ENGINE_GET_VAR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[threePortsMode], three_ports_mode) 72 73 #define CPM4x25_CPRI_PORT_VSD_ACTIVE_GROUP_SET(unit, pm_info, group_list, port_index) \ 74 SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[cpriVsdActiveGrp], group_list, port_index) 75 #define CPM4x25_CPRI_PORT_VSD_ACTIVE_GROUP_GET(unit, pm_info, group_list, port_index) \ 76 SOC_WB_ENGINE_GET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[cpriVsdActiveGrp], group_list, port_index) 77 78 79 typedef enum pm4x25_fabric_wb_vars{ 80 isActive = 0, /* specify the PM4x25 core is active (at least one port has been attached) */ 81 isBypassed, /*specify the PM is in Bypass mode - the MAC is not in use, some configurations do not apply*/ 82 isInitialized, /* specify initialization of all SerDes have been done */ 83 lane2portMap, /* map each lane in the PM to a logical port */ 84 threePortsMode, 85 phy_type, /* Phy type in PHYMOD dispatch phymod_dispatch_type_t */ 86 interfaceConfig, /* portmod_port_interface_config_t **removed** */ 87 portInitConfig, /* portmod_port_init_config_t **removed** */ 88 nofPhys,/* keep track of nun of phys (including internal Serdes. */ 89 maxSpeed, /* Max Port Speed Supported */ 90 interfaceType, /* interface of type soc_port_if_t */ 91 interfaceModes, /* see PHYMOD_INTF_MODES_ */ 92 isInterfaceRestore, /* interface should be restored from DB (otherwise retrieved from HW), replace PHYMOD_INTF_F_INTF_PARAM_SET_ONLY */ 93 isHg, /* specify wheather the port is higig port */ 94 anMode, /* spn_PHY_AN_MODE - Specify the AN mode */ 95 fsCl72, /* spn_FORCED_INIT_CL72 - if trainig should be enabled in Forced speed mode */ 96 cx4In10G, /* see PHYMOD_BAM_CL37_CAP_10G_CX4 */ 97 anCl72, /* spn_PHY_AN_C72 - Specify if the link training should be enabled */ 98 anFec, /* spn_FORCED_INIT_FEC specify if FEC should be enabled in AN mode */ 99 anMasterLane, /* spn_PHY_AUTONEG_MASTER_LANE - Specify the AN master lane */ 100 laneConnectionDb, /* represents the physical topology of the serdes and ext phy lanes */ 101 interfaceWrittenIntoOutmostPhy, /* the interface type written into the outmost PHY */ 102 portDynamicState, 103 tsAdjust, /* the time stamp adjust setting on MAC */ 104 pllDividerReq, /*pll_divider_req setting on the port */ 105 serdes1000xAt25gVco, /*1G working at 25g*/ 106 serdes10gAt25gVco, /*10G Base-R working at 25g*/ 107 cpriVsdActiveGrp /* CPRI TX VSD active group */ 108 }pm4x25_wb_vars_t; 109 110 111 #define CPM4x25_PHY_ACCESS_GET(unit, port, pm_info, phy_acc) \ 112 do { \ 113 uint32 is_bypass; \ 114 phy_acc = 0; \ 115 _SOC_IF_ERR_EXIT(CPM4x25_IS_BYPASSED_GET(unit, pm_info, &is_bypass)); \ 116 phy_acc = (is_bypass && PM_4x25_INFO(pm_info)->first_phy != -1) ? (PM_4x25_INFO(pm_info)->first_phy | SOC_REG_ADDR_PHY_ACC_MASK) : port ; \ 117 } while (0) 118 119 extern int pm4x25_to_cpm_pm_enable(int unit, int port, pm_info_t pm_info, int port_index, const portmod_port_add_info_t* add_info, int enable); 120 extern int pm4x25_default_fw_loader(const phymod_core_access_t* core, uint32_t length, const uint8_t* data); 121 static int _cprimod_port_speed_id_to_vco(int speed_id, portmod_encap_t encap); 122 static int _cpm4x25_port_refclk_select(int unit, int port, portmod_cpm_core_mode_t core_mode); 123 static int _cpm4x25_port_pll_control_select(int unit, int port, portmod_cpm_core_mode_t core_mode); 124 125 126 STATIC 127 int _cpm4x25_pm_port_init(int unit, int port, pm_info_t pm_info, int enable) 128 { 129 int phy_acc, i, rv; 130 int tmp_port=0; 131 int first_index = -1; 132 uint32 reg_val; 133 soc_field_t port_fields[] = {PORT0f, PORT1f, PORT2f, PORT3f}; 134 SOC_INIT_FUNC_DEFS; 135 136 CPM4x25_PHY_ACCESS_GET(unit, port, pm_info, phy_acc); 137 for (i = 0 ; i < MAX_PORTS_PER_PM4X25; i++) { 138 rv = CPM4x25_LANE2PORT_GET(unit, pm_info, i, &tmp_port); 139 _SOC_IF_ERR_EXIT(rv); 140 141 if (tmp_port == port) { 142 first_index = i; 143 break; 144 } 145 } 146 147 if (first_index == -1) { 148 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, 149 (_SOC_MSG("port was not found in internal DB %d"), port)); 150 } 151 152 if (enable) { 153 /* Soft reset */ 154 _SOC_IF_ERR_EXIT(READ_CLPORT_SOFT_RESETr(unit, phy_acc, ®_val)); 155 soc_reg_field_set(unit, CLPORT_SOFT_RESETr, ®_val, port_fields[first_index], 1); 156 _SOC_IF_ERR_EXIT(WRITE_CLPORT_SOFT_RESETr(unit, phy_acc, reg_val)); 157 158 soc_reg_field_set(unit, CLPORT_SOFT_RESETr, ®_val, port_fields[first_index], 0); 159 _SOC_IF_ERR_EXIT(WRITE_CLPORT_SOFT_RESETr(unit, phy_acc, reg_val)); 160 161 /* Port enable */ 162 _SOC_IF_ERR_EXIT(READ_CLPORT_ENABLE_REGr(unit, phy_acc, ®_val)); 163 soc_reg_field_set(unit, CLPORT_ENABLE_REGr, ®_val, port_fields[first_index], 1); 164 _SOC_IF_ERR_EXIT(WRITE_CLPORT_ENABLE_REGr(unit, phy_acc, reg_val)); 165 166 } else { 167 /* Port disable */ 168 _SOC_IF_ERR_EXIT(READ_CLPORT_ENABLE_REGr(unit, phy_acc, ®_val)); 169 soc_reg_field_set(unit, CLPORT_ENABLE_REGr, ®_val, port_fields[first_index], 0); 170 _SOC_IF_ERR_EXIT(WRITE_CLPORT_ENABLE_REGr(unit, phy_acc, reg_val)); 171 172 /* Soft reset */ 173 _SOC_IF_ERR_EXIT(READ_CLPORT_SOFT_RESETr(unit, phy_acc, ®_val)); 174 soc_reg_field_set(unit, CLPORT_SOFT_RESETr, ®_val, port_fields[first_index], 1); 175 _SOC_IF_ERR_EXIT(WRITE_CLPORT_SOFT_RESETr(unit, phy_acc, reg_val)); 176 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_set(unit, port, 0)); 177 } 178 179 exit: 180 SOC_FUNC_RETURN; 181 } 182 183 184 185 int cpm4x25_port_attach(int unit, int port, pm_info_t pm_info, const portmod_port_add_info_t* add_info) 186 { 187 int port_index = -1; 188 int rv = 0; 189 int phy, i, ii; 190 int lane; 191 int pll_sel=0; 192 int pll_lock=0; 193 int port_rst =0; 194 int tmp_port=0; 195 int phys_count = 0, first_phy = -1; 196 int three_ports_mode; 197 uint32 pm_is_active = 0; 198 uint32 pm_is_bypassed = 0; 199 portmod_pbmp_t port_phys_in_pm; 200 phymod_phy_access_t phy_access; 201 phymod_core_init_config_t init_cfg; 202 phymod_core_status_t core_sts; 203 cprimod_port_init_config_t port_config; 204 uint32 core_is_initialized; 205 206 207 SOC_INIT_FUNC_DEFS; 208 _SOC_IF_ERR_EXIT(phymod_core_init_config_t_init(&init_cfg)); 209 _SOC_IF_ERR_EXIT(phymod_core_status_t_init(&core_sts)); 210 _SOC_IF_ERR_EXIT(cprimod_port_init_config_t_init(&port_config)); 211 _SOC_IF_ERR_EXIT(_cpm4x25_port_pll_control_select(unit, port, add_info->init_config.cpm_core_mode)); 212 /* select refclock for CPRI or ETH port */ 213 _SOC_IF_ERR_EXIT(_cpm4x25_port_refclk_select(unit, port, add_info->init_config.cpm_core_mode)); 214 215 if((add_info->interface_config.encap_mode != _SHR_PORT_ENCAP_CPRI) && 216 (add_info->interface_config.encap_mode != _SHR_PORT_ENCAP_RSVD4)){ 217 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_set(unit, port, 0)); 218 _rv = pm4x25_port_attach(unit, port, pm_info, add_info); 219 SOC_FUNC_RETURN; 220 } 221 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_set(unit, port, 1)); 222 rv = CPM4x25_IS_BYPASSED_GET(unit, pm_info, &pm_is_bypassed); 223 _SOC_IF_ERR_EXIT(rv); 224 /* Get the first phy related to this port */ 225 PORTMOD_PBMP_ASSIGN(port_phys_in_pm, add_info->phys); 226 PORTMOD_PBMP_AND(port_phys_in_pm, PM_4x25_INFO(pm_info)->phys); 227 PORTMOD_PBMP_COUNT(port_phys_in_pm, phys_count); 228 ii = 0; 229 PORTMOD_PBMP_ITER(PM_4x25_INFO(pm_info)->phys, phy){ 230 if(PORTMOD_PBMP_MEMBER(port_phys_in_pm, phy)){ 231 rv = CPM4x25_LANE2PORT_SET(unit, pm_info, ii, port); 232 _SOC_IF_ERR_EXIT(rv); 233 first_phy = (first_phy == -1) ? phy : first_phy; 234 port_index = (port_index == -1 ? ii : port_index); 235 } 236 ii++; 237 } 238 PM_4x25_INFO(pm_info)->first_phy = first_phy; 239 if(port_index<0 || port_index>=PM4X25_LANES_PER_CORE) { 240 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 241 (_SOC_MSG("can't attach port %d. can't find relevant phy"), port)); 242 } 243 /* init data for port configuration */ 244 /* 245 rv = CPM4x25_MAX_SPEED_SET(unit, pm_info, add_info->interface_config.max_speed, port_index); 246 _SOC_IF_ERR_EXIT(rv); 247 rv = CPM4x25_INTERFACE_TYPE_SET(unit, pm_info, add_info->interface_config.interface, port_index); 248 _SOC_IF_ERR_EXIT(rv); 249 rv = CPM4x25_INTERFACE_MODES_SET(unit, pm_info, add_info->interface_config.interface_modes, port_index); 250 _SOC_IF_ERR_EXIT(rv); 251 */ 252 if (add_info->init_config.polarity_overwrite == 1) { 253 sal_memcpy(&PM_4x25_INFO(pm_info)->polarity, 254 &add_info->init_config.polarity[0], sizeof(phymod_polarity_t)); 255 } 256 if (add_info->init_config.lane_map_overwrite == 1) { 257 sal_memcpy(&PM_4x25_INFO(pm_info)->lane_map, 258 &add_info->init_config.lane_map[0], sizeof(phymod_lane_map_t)); 259 } 260 if (add_info->init_config.fw_load_method_overwrite == 1) { 261 PM_4x25_INFO(pm_info)->fw_load_method = 262 add_info->init_config.fw_load_method[0]; 263 } 264 if (add_info->init_config.ref_clk_overwrite == 1) { 265 PM_4x25_INFO(pm_info)->ref_clk = add_info->init_config.ref_clk; 266 } 267 268 rv = CPM4x25_IS_ACTIVE_GET(unit, pm_info, &pm_is_active); 269 _SOC_IF_ERR_EXIT(rv); 270 if(!pm_is_active){ 271 three_ports_mode = (add_info->init_config.port_mode_aux_info == portmodModeInfoThreePorts) ? 1 : 0; 272 rv = CPM4x25_THREE_PORTS_MODE_SET(unit, pm_info, three_ports_mode); 273 _SOC_IF_ERR_EXIT(rv); 274 rv = pm4x25_to_cpm_pm_enable(unit, port, pm_info, port_index, add_info, 1); 275 _SOC_IF_ERR_EXIT(rv); 276 pm_is_active = 1; 277 rv = CPM4x25_IS_ACTIVE_SET(unit, pm_info, pm_is_active); 278 _SOC_IF_ERR_EXIT(rv); 279 } 280 /* 281 init_all = (!PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_GET(add_info) && 282 !PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info) && 283 !PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) ? 1 : 0; 284 */ 285 /* No probe for CPM4x25 */ 286 if (PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_GET(add_info)) { 287 return (rv); 288 } 289 if (PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info)){ 290 CPRIMOD_CORE_INIT_F_EXECUTE_PASS1_SET(&init_cfg); 291 } 292 if (PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)){ 293 CPRIMOD_CORE_INIT_F_EXECUTE_PASS2_SET(&init_cfg); 294 } 295 296 if (PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) { 297 if (add_info->init_config.cpm_core_mode == portmodCpmMixEthCpri) { 298 init_cfg.pll0_div_init_value = _cprimod_port_speed_id_to_vco(add_info->interface_config.speed, add_info->interface_config.encap_mode); 299 init_cfg.pll1_div_init_value = 0; 300 } else { 301 /* Need to add code for usage of both pll in all cpri mode */ 302 init_cfg.pll0_div_init_value = _cprimod_port_speed_id_to_vco(add_info->interface_config.speed, add_info->interface_config.encap_mode); 303 init_cfg.pll1_div_init_value = _cprimod_port_speed_id_to_vco(add_info->interface_config.speed, add_info->interface_config.encap_mode); 304 } 305 } 306 307 rv = CPM4x25_IS_INITIALIZED_GET(unit, pm_info, &core_is_initialized); 308 _SOC_IF_ERR_EXIT(rv); 309 310 if (!PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED_GET(core_is_initialized)) { 311 if(!PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED_GET(core_is_initialized) || 312 PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) { 313 if ((PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info)) || 314 (PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info))) { 315 /*init_cfg.tx_input_voltage=cprimodTxInputVoltageDefault;*/ 316 init_cfg.firmware_loader = pm4x25_default_fw_loader; 317 init_cfg.lane_map.num_of_lanes = PM_4x25_INFO(pm_info)->lane_map.num_of_lanes; 318 for(ii=0; ii<CPRIMOD_MAX_LANES_PER_CORE; ii++) { 319 init_cfg.lane_map.lane_map_rx[ii] = PM_4x25_INFO(pm_info)->lane_map.lane_map_rx[ii]; 320 init_cfg.lane_map.lane_map_tx[ii] = PM_4x25_INFO(pm_info)->lane_map.lane_map_tx[ii]; 321 } 322 } 323 324 _SOC_IF_ERR_EXIT(cprimod_core_init(unit, port, &PM_4x25_INFO(pm_info)->int_core_access, 325 &init_cfg, &core_sts)); 326 327 /* Set txpi sdm scheme */ 328 _SOC_IF_ERR_EXIT(_pm4x25_txpi_sdm_scheme_set(unit, port, pm_info, add_info->init_config.txpi_sdm_scheme)); 329 /* Set txpi lane select */ 330 _SOC_IF_ERR_EXIT(_pm4x25_txpi_lane_select_set(unit, port, pm_info, (uint32 *)add_info->init_config.lane_map[0].lane_map_tx)); 331 332 /* No phy probe, set serdes type to Falcon_dpll for phy diag commands */ 333 if (add_info->init_config.cpm_core_mode == portmodCpmAllCpri) { 334 PM_4x25_INFO(pm_info)->int_core_access.type = phymodDispatchTypeFalcon_dpll; 335 } 336 337 if (PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info)) { 338 PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED_SET(core_is_initialized); 339 rv = SOC_WB_ENGINE_SET_VAR (unit, SOC_WB_ENGINE_PORTMOD, 340 pm_info->wb_vars_ids[isInitialized], 341 &core_is_initialized); 342 _SOC_IF_ERR_EXIT(rv); 343 } 344 if (PORTMOD_PORT_ADD_F_INIT_PASS2_GET(add_info)) { 345 PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED_SET(core_is_initialized); 346 rv = SOC_WB_ENGINE_SET_VAR (unit, SOC_WB_ENGINE_PORTMOD, 347 pm_info->wb_vars_ids[isInitialized], 348 &core_is_initialized); 349 _SOC_IF_ERR_EXIT(rv); 350 } 351 } 352 } 353 if (PORTMOD_PORT_ADD_F_INIT_PASS1_GET(add_info)) { 354 return (rv); 355 } 356 /* initalize port */ 357 358 port_config.serdes_scrambler_seed = add_info->interface_config.serdes_scrambler_seed; 359 port_config.serdes_scrambler_enable = add_info->interface_config.serdes_scrambler_enable; 360 port_config.pll_in_use = cprimodInUseDefault; 361 362 for( i = 0 ; i < MAX_PORTS_PER_PM4X25; i++) { 363 rv = CPM4x25_LANE2PORT_GET(unit, pm_info, i, &tmp_port); 364 _SOC_IF_ERR_EXIT(rv); 365 if(tmp_port > 0) { 366 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 367 lane = (SOC_INFO(unit).port_l2p_mapping[tmp_port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 368 phy_access.access.lane_mask = (1<<lane); 369 _SOC_IF_ERR_EXIT(cprimod_cpri_port_reset_get(unit, tmp_port, &port_rst)); 370 if(port_rst == 0) { 371 _SOC_IF_ERR_EXIT(cprimod_cpri_pll_status_get(unit, tmp_port, &phy_access, &pll_sel, &pll_lock)); 372 } 373 if ((port_rst==0) && (pll_sel==0)) { 374 port_config.pll_in_use |= cprimodInUsePll0; 375 } 376 if ((port_rst==0) && (pll_sel==1)) { 377 port_config.pll_in_use |= cprimodInUsePll1; 378 } 379 } 380 } 381 382 rv = _cpm4x25_pm_port_init(unit, port, pm_info, 1); 383 if(add_info->interface_config.encap_mode == _SHR_PORT_ENCAP_CPRI) { 384 /* coverity[MIXED_ENUMS:FALSE]*/ 385 switch((cprimod_supported_port_speed_t)add_info->interface_config.speed) { 386 case cprimodSupportedSpd1228p8: 387 port_config.tx_cpri_speed = cprimodSpd1228p8; 388 port_config.rx_cpri_speed = cprimodSpd1228p8; 389 break; 390 case cprimodSupportedSpd2457p6: 391 port_config.tx_cpri_speed = cprimodSpd2457p6; 392 port_config.rx_cpri_speed = cprimodSpd2457p6; 393 break; 394 case cprimodSupportedSpd3072p0: 395 port_config.tx_cpri_speed = cprimodSpd3072p0; 396 port_config.rx_cpri_speed = cprimodSpd3072p0; 397 break; 398 case cprimodSupportedSpd4915p2: 399 port_config.tx_cpri_speed = cprimodSpd4915p2; 400 port_config.rx_cpri_speed = cprimodSpd4915p2; 401 break; 402 case cprimodSupportedSpd6144p0: 403 port_config.tx_cpri_speed = cprimodSpd6144p0; 404 port_config.rx_cpri_speed = cprimodSpd6144p0; 405 break; 406 case cprimodSupportedSpd9830p4: 407 port_config.tx_cpri_speed = cprimodSpd9830p4; 408 port_config.rx_cpri_speed = cprimodSpd9830p4; 409 break; 410 case cprimodSupportedSpd10137p6: 411 port_config.tx_cpri_speed = cprimodSpd10137p6; 412 port_config.rx_cpri_speed = cprimodSpd10137p6; 413 break; 414 case cprimodSupportedSpd12165p12: 415 port_config.tx_cpri_speed = cprimodSpd12165p12; 416 port_config.rx_cpri_speed = cprimodSpd12165p12; 417 break; 418 case cprimodSupportedSpd24330p24: 419 port_config.tx_cpri_speed = cprimodSpd24330p24; 420 port_config.rx_cpri_speed = cprimodSpd24330p24; 421 break; 422 default: 423 port_config.tx_cpri_speed = cprimodSpd1228p8; 424 port_config.rx_cpri_speed = cprimodSpd1228p8; 425 break; 426 } 427 port_config.tx_rsvd4_speed = cprimodRsvd4SpdMult4X; 428 port_config.rx_rsvd4_speed = cprimodRsvd4SpdMult4X; 429 } else if (add_info->interface_config.encap_mode == _SHR_PORT_ENCAP_RSVD4) { 430 /* coverity[mixed_enums:FALSE]*/ 431 switch(add_info->interface_config.speed) { 432 case cprimodRsvd4SpdMult4X: 433 port_config.tx_rsvd4_speed = cprimodRsvd4SpdMult4X; 434 port_config.rx_rsvd4_speed = cprimodRsvd4SpdMult4X; 435 port_config.tx_cpri_speed = cprimodSpd3072p0; 436 port_config.rx_cpri_speed = cprimodSpd3072p0; 437 break; 438 /* coverity[mixed_enums:FALSE]*/ 439 case cprimodRsvd4SpdMult8X: 440 port_config.tx_rsvd4_speed = cprimodRsvd4SpdMult8X; 441 port_config.rx_rsvd4_speed = cprimodRsvd4SpdMult8X; 442 port_config.tx_cpri_speed = cprimodSpd6144p0; 443 port_config.rx_cpri_speed = cprimodSpd6144p0; 444 break; 445 default: 446 port_config.tx_rsvd4_speed = cprimodRsvd4SpdMult4X; 447 port_config.rx_rsvd4_speed = cprimodRsvd4SpdMult4X; 448 port_config.tx_cpri_speed = cprimodSpd3072p0; 449 port_config.rx_cpri_speed = cprimodSpd3072p0; 450 break; 451 } 452 } 453 if (add_info->interface_config.encap_mode == _SHR_PORT_ENCAP_RSVD4) { 454 port_config.interface = cprimodRsvd4; 455 } else { 456 port_config.interface = cprimodCpri; 457 } 458 port_config.roe_stuffing_bit = add_info->init_config.roe_stuffing_bit; 459 port_config.roe_reserved_bit = add_info->init_config.roe_reserved_bit; 460 461 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 462 lane = (SOC_INFO(unit).port_l2p_mapping[port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 463 port_config.polarity_rx = ((PM_4x25_INFO(pm_info)->polarity.rx_polarity) >> lane) & 1; 464 port_config.polarity_tx = ((PM_4x25_INFO(pm_info)->polarity.tx_polarity) >> lane) & 1; 465 phy_access.access.lane_mask = (1<<lane); 466 if(add_info->init_config.cpm_core_mode == portmodCpmMixEthCpri) { 467 port_config.mix_cpri_enet = 1; 468 } else { 469 port_config.mix_cpri_enet = 0; 470 } 471 port_config.vco_for_lane = _cprimod_port_speed_id_to_vco(add_info->interface_config.speed, add_info->interface_config.encap_mode); 472 473 if (PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG_GET(add_info->init_config.tx_params_user_flag[0])) { 474 port_config.tx_params[0].pre = add_info->init_config.tx_params[0].pre; 475 port_config.tx_params[0].main = add_info->init_config.tx_params[0].main; 476 port_config.tx_params[0].post = add_info->init_config.tx_params[0].post; 477 port_config.tx_params_user_config = 1; 478 } 479 480 port_config.parity_enable = add_info->init_config.parity_enable; 481 482 _SOC_IF_ERR_EXIT(cprimod_port_init(unit, port, &phy_access, &port_config)); 483 484 /* Set PMD TXPI mode */ 485 _SOC_IF_ERR_EXIT(_pm4x25_port_phy_txpi_mode_set(unit, port, pm_info, add_info->init_config.txpi_mode)); 486 487 exit: 488 SOC_FUNC_RETURN; 489 } 490 491 int cpm4x25_pm_init(int unit, const portmod_pm_create_info_internal_t* pm_add_info, int wb_buffer_index, pm_info_t pm_info) 492 { 493 SOC_INIT_FUNC_DEFS; 494 _rv = pm4x25_pm_init(unit, pm_add_info, wb_buffer_index, pm_info); 495 496 SOC_FUNC_RETURN; 497 498 } 499 500 /* CPM core supports ETH/CPRI mixed mode, also supports flex between ETH and CPRI. 501 * CPRI port use PLL0. refclock select pll0_lc_refclk (0). 502 * ETH port use PLL0 and PLL1. refclock select pll1_lc_refclk (1). 503 * This function is used to select reference clock of PLL0. 504 */ 505 static int _cpm4x25_port_refclk_select(int unit, int port, portmod_cpm_core_mode_t core_mode) 506 { 507 uint32 rval; 508 int refclock0 = 0; 509 int refclock1 = 0; 510 511 switch(core_mode) { 512 case portmodCpmAllCpri: 513 refclock0 = 0; 514 refclock1 = 1; 515 break; 516 case portmodCpmAllIEEE: 517 case portmodCpmAllHIGIG: 518 refclock0 = 1; 519 refclock1 = 0; 520 break; 521 case portmodCpmMixEthCpri: 522 refclock0 = 0; 523 refclock1 = 0; 524 break; 525 default: 526 refclock0 = 0; 527 refclock1 = 1; 528 break; 529 } 530 531 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, CLPORT_XGXS0_CTRL_REGr, port, 0, &rval)); 532 soc_reg_field_set(unit, CLPORT_XGXS0_CTRL_REGr, &rval, PLL0_LC_REFSELf, refclock0); 533 soc_reg_field_set(unit, CLPORT_XGXS0_CTRL_REGr, &rval, PLL1_LC_REFSELf, refclock1); 534 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, CLPORT_XGXS0_CTRL_REGr, port, 0, rval)); 535 536 return SOC_E_NONE; 537 } 538 539 /* CPM core supports ETH/CPRI mixed mode, also supports flex between ETH and CPRI. 540 * in all CPRI mode both pll control through CPRI path, in all Ethernet mode both 541 * pll control through Ethernet path. In Mix mode pll0 through CPRI path and pll1 542 * through Ethernet path. 543 */ 544 static int _cpm4x25_port_pll_control_select(int unit, int port, portmod_cpm_core_mode_t core_mode) 545 { 546 uint32 data; 547 SOC_IF_ERROR_RETURN(READ_TOP_CTRL_CONFIGr(unit, port, &data)); 548 switch(core_mode) { 549 case portmodCpmAllCpri: 550 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_PLL0_CTRLf, 1); 551 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_PLL1_CTRLf, 1); 552 break; 553 case portmodCpmAllIEEE: 554 case portmodCpmAllHIGIG: 555 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_PLL0_CTRLf, 0); 556 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_PLL1_CTRLf, 0); 557 break; 558 case portmodCpmMixEthCpri: 559 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_PLL0_CTRLf, 1); 560 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_PLL1_CTRLf, 0); 561 break; 562 default: 563 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_PLL0_CTRLf, 0); 564 soc_reg_field_set(unit, TOP_CTRL_CONFIGr, &data, CIP_PLL1_CTRLf, 0); 565 break; 566 } 567 SOC_IF_ERROR_RETURN(WRITE_TOP_CTRL_CONFIGr(unit, port, data)); 568 return SOC_E_NONE; 569 } 570 571 int cpm4x25_port_phy_link_up_event(int unit, int port, pm_info_t pm_info) 572 { 573 int val; 574 SOC_INIT_FUNC_DEFS; 575 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 576 if(val == 0) { 577 _rv = pm4x25_port_phy_link_up_event(unit, port, pm_info); 578 SOC_FUNC_RETURN; 579 } else { 580 _rv = cprimod_cpri_port_link_up_event(unit, port); 581 SOC_FUNC_RETURN; 582 } 583 exit: 584 SOC_FUNC_RETURN; 585 } 586 587 int cpm4x25_port_phy_link_down_event(int unit, int port, pm_info_t pm_info) 588 { 589 int val; 590 SOC_INIT_FUNC_DEFS; 591 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 592 if(val == 0) { 593 _rv = pm4x25_port_phy_link_down_event(unit, port, pm_info); 594 SOC_FUNC_RETURN; 595 } else { 596 _rv = cprimod_cpri_port_link_down_event(unit, port); 597 SOC_FUNC_RETURN; 598 } 599 exit: 600 SOC_FUNC_RETURN; 601 } 602 603 int cpm4x25_port_enable_get(int unit, int port, pm_info_t pm_info, int flags, int* enable) 604 { 605 int val; 606 int phy_enable; 607 int actual_flags = flags; 608 SOC_INIT_FUNC_DEFS; 609 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 610 if(val == 0) { 611 _rv = pm4x25_port_enable_get(unit, port, pm_info, flags, enable); 612 SOC_FUNC_RETURN; 613 } 614 if((!PORTMOD_PORT_ENABLE_TX_GET(flags)) && (!PORTMOD_PORT_ENABLE_RX_GET(flags))){ 615 PORTMOD_PORT_ENABLE_RX_SET(actual_flags); 616 PORTMOD_PORT_ENABLE_TX_SET(actual_flags); 617 } 618 *enable = 0; 619 if (PORTMOD_PORT_ENABLE_RX_GET(actual_flags)) { 620 _SOC_IF_ERR_EXIT(cprimod_cpri_port_rx_enable_get(unit, port, &phy_enable)); 621 *enable |= phy_enable; 622 } 623 if (PORTMOD_PORT_ENABLE_TX_GET(actual_flags)) { 624 _SOC_IF_ERR_EXIT(cprimod_cpri_port_tx_enable_get(unit, port, &phy_enable)); 625 *enable |= phy_enable; 626 } 627 628 exit: 629 SOC_FUNC_RETURN; 630 } 631 632 int cpm4x25_port_detach(int unit, int port, pm_info_t pm_info) 633 { 634 int val; 635 int enable; 636 int invalid_port = -1; 637 int tmp_port; 638 int i = 0, flags = 0; 639 int rv = 0; 640 int is_last_one = TRUE; 641 int port_index = -1; 642 int phytype = 0; 643 uint32 inactive = 0; 644 SOC_INIT_FUNC_DEFS; 645 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 646 if(val == 0) { 647 _rv = pm4x25_port_detach(unit, port, pm_info); 648 SOC_FUNC_RETURN; 649 } 650 651 _SOC_IF_ERR_EXIT(cpm4x25_port_enable_get(unit, port, pm_info, flags, &enable)); 652 if(enable){ 653 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("can't detach active port %d"), port)); 654 } 655 _SOC_IF_ERR_EXIT(cprimod_cpri_port_reset_set(unit, port, 1)); 656 657 rv = _cpm4x25_pm_port_init(unit, port, pm_info, 0); 658 _SOC_IF_ERR_EXIT(rv); 659 660 /*remove from array and check if it was the last one*/ 661 for( i = 0 ; i < MAX_PORTS_PER_PM4X25; i++){ 662 rv = CPM4x25_LANE2PORT_GET(unit, pm_info, i, &tmp_port); 663 _SOC_IF_ERR_EXIT(rv); 664 if(tmp_port == port){ 665 port_index = (port_index == -1 ? i : port_index); 666 rv = CPM4x25_LANE2PORT_SET(unit, pm_info, i, invalid_port); 667 _SOC_IF_ERR_EXIT(rv); 668 } else if (tmp_port != -1){ 669 is_last_one = FALSE; 670 } 671 } 672 673 if ((PM_4x25_INFO(pm_info)->nof_phys[0]) && (port_index == -1)) { 674 _SOC_EXIT_WITH_ERR(SOC_E_PORT, (_SOC_MSG("Port %d wasn't found"), port)); 675 } 676 677 /*deinit PM in case of last one*/ 678 if(is_last_one){ 679 rv = pm4x25_to_cpm_pm_enable(unit, port, pm_info, port_index, NULL, 0); 680 _SOC_IF_ERR_EXIT(rv); 681 682 PHYMOD_DEVICE_OP_MODE_PCS_BYPASS_CLR(PM_4x25_INFO(pm_info)->int_core_access.device_op_mode); 683 684 rv = CPM4x25_IS_ACTIVE_SET(unit, pm_info, inactive); 685 _SOC_IF_ERR_EXIT(rv); 686 687 rv = CPM4x25_IS_INITIALIZED_SET(unit, pm_info, inactive); 688 _SOC_IF_ERR_EXIT(rv); 689 690 rv = CPM4x25_IS_BYPASSED_SET(unit, pm_info, inactive); 691 _SOC_IF_ERR_EXIT(rv); 692 693 /* Updating phymod type in pm_info structure and warmboot engine */ 694 phytype = phymodDispatchTypeInvalid; 695 rv = SOC_WB_ENGINE_SET_ARR(unit, SOC_WB_ENGINE_PORTMOD, pm_info->wb_vars_ids[phy_type], &phytype, 0); 696 _SOC_IF_ERR_EXIT(rv); 697 PM_4x25_INFO(pm_info)->int_core_access.type = phymodDispatchTypeInvalid; 698 } 699 700 exit: 701 SOC_FUNC_RETURN; 702 } 703 704 int cpm4x25_port_replace(int unit, int port, pm_info_t pm_info, int new_port) 705 { 706 int val; 707 int i, tmp_port; 708 int rv = 0; 709 SOC_INIT_FUNC_DEFS; 710 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 711 if(val == 0) { 712 _rv = pm4x25_port_replace(unit, port, pm_info, new_port); 713 SOC_FUNC_RETURN; 714 } 715 716 /* replace old port with new port */ 717 for(i = 0; i < MAX_PORTS_PER_PM4X25; i++) { 718 rv = CPM4x25_LANE2PORT_GET(unit, pm_info, i, &tmp_port); 719 _SOC_IF_ERR_EXIT(rv); 720 if (tmp_port == port) { 721 rv = CPM4x25_LANE2PORT_SET(unit, pm_info, i, new_port); 722 _SOC_IF_ERR_EXIT(rv); 723 } 724 } 725 726 exit: 727 SOC_FUNC_RETURN; 728 729 } 730 731 int cpm4x25_port_enable_set(int unit, int port, pm_info_t pm_info, int flags, int enable) 732 { 733 int val; 734 int actual_flags = flags; 735 SOC_INIT_FUNC_DEFS; 736 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 737 if(val == 0) { 738 _rv = pm4x25_port_enable_set(unit, port, pm_info, flags, enable); 739 SOC_FUNC_RETURN; 740 } 741 if((!PORTMOD_PORT_ENABLE_TX_GET(flags)) && (!PORTMOD_PORT_ENABLE_RX_GET(flags))){ 742 PORTMOD_PORT_ENABLE_RX_SET(actual_flags); 743 PORTMOD_PORT_ENABLE_TX_SET(actual_flags); 744 } 745 /* if no MAC\Phy flags - set both*/ 746 if((!PORTMOD_PORT_ENABLE_PHY_GET(flags)) && (!PORTMOD_PORT_ENABLE_MAC_GET(flags))){ 747 PORTMOD_PORT_ENABLE_PHY_SET(actual_flags); 748 PORTMOD_PORT_ENABLE_MAC_SET(actual_flags); 749 } 750 751 if ((PORTMOD_PORT_ENABLE_RX_GET(actual_flags)) && 752 (PORTMOD_PORT_ENABLE_MAC_GET(actual_flags))) { 753 _SOC_IF_ERR_EXIT(cprimod_cpri_port_rx_enable_set(unit, port, enable)); 754 } 755 if (PORTMOD_PORT_ENABLE_TX_GET(actual_flags)) { 756 _SOC_IF_ERR_EXIT(cprimod_cpri_port_tx_enable_set(unit, port, enable)); 757 /* 758 * if disable. disable TGEN as well. 759 */ 760 if (!enable) { 761 _SOC_IF_ERR_EXIT 762 (cprimod_tx_framer_tgen_enable(unit, port, FALSE)); 763 } 764 765 } 766 767 exit: 768 SOC_FUNC_RETURN; 769 770 } 771 772 int cpm4x25_port_link_get(int unit, int port, pm_info_t pm_info, int flags, int* link) 773 { 774 int val; 775 SOC_INIT_FUNC_DEFS; 776 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 777 if(val == 0) { 778 _rv = pm4x25_port_link_get(unit, port, pm_info, flags, link); 779 SOC_FUNC_RETURN; 780 } 781 782 /* get CPRI port link status. */ 783 _SOC_IF_ERR_EXIT 784 (cprimod_cpri_port_link_get(unit, port, link)); 785 exit: 786 787 SOC_FUNC_RETURN; 788 789 } 790 791 int cpm4x25_port_loopback_set(int unit, int port, pm_info_t pm_info, portmod_loopback_mode_t loopback_type, int enable) 792 { 793 int val; 794 int lane; 795 phymod_loopback_mode_t loopback; 796 phymod_phy_access_t phy_access; 797 798 SOC_INIT_FUNC_DEFS; 799 800 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 801 if(val == 0) { 802 803 _rv = pm4x25_port_loopback_set(unit, port, pm_info, loopback_type, enable); 804 SOC_FUNC_RETURN; 805 } else { 806 switch(loopback_type) { 807 case portmodLoopbackPhyRloopPMD: 808 loopback = phymodLoopbackRemotePMD; 809 break; 810 case portmodLoopbackPhyGloopPMD: 811 loopback = phymodLoopbackGlobalPMD; 812 break; 813 case portmodLoopbackPhyGloopPCS: /* No PCS loopback doing PMD loopback */ 814 loopback = phymodLoopbackGlobalPMD; 815 break; 816 default: 817 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 818 (_SOC_MSG("Loopback type %d. is not supported for CPRI"), loopback_type)); 819 820 } 821 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 822 lane = (SOC_INFO(unit).port_l2p_mapping[port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 823 phy_access.access.lane_mask = (1<<lane); 824 _SOC_IF_ERR_EXIT(tscf_gen3_phy_loopback_set(&phy_access, loopback, enable)); 825 } 826 827 exit: 828 SOC_FUNC_RETURN; 829 830 } 831 832 int cpm4x25_port_loopback_get(int unit, int port, pm_info_t pm_info, 833 portmod_loopback_mode_t loopback_type, int* enable) 834 { 835 int val; 836 int lane; 837 uint32_t en; 838 phymod_loopback_mode_t loopback; 839 phymod_phy_access_t phy_access; 840 SOC_INIT_FUNC_DEFS; 841 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 842 if(val == 0) { 843 _rv = pm4x25_port_loopback_get(unit, port, pm_info, loopback_type, enable); 844 SOC_FUNC_RETURN; 845 } else { 846 switch(loopback_type) { 847 case portmodLoopbackPhyRloopPMD: 848 loopback = phymodLoopbackRemotePMD; 849 break; 850 case portmodLoopbackPhyGloopPMD: 851 loopback = phymodLoopbackGlobalPMD; 852 break; 853 case portmodLoopbackPhyGloopPCS: /* No PCS loopback doing PMD loopback */ 854 loopback = phymodLoopbackGlobalPMD; 855 break; 856 default: 857 loopback = phymodLoopbackGlobal; 858 break; 859 } 860 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 861 lane = (SOC_INFO(unit).port_l2p_mapping[port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 862 phy_access.access.lane_mask = (1<<lane); 863 _SOC_IF_ERR_EXIT(tscf_gen3_phy_loopback_get(&phy_access, loopback, &en)); 864 *enable = en; 865 } 866 867 exit: 868 SOC_FUNC_RETURN; 869 870 } 871 int cpm4x25_port_autoneg_set(int unit, int port, pm_info_t pm_info, uint32 phy_flags, 872 const phymod_autoneg_control_t* an) { 873 int val; 874 SOC_INIT_FUNC_DEFS; 875 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 876 if(val == 0) { 877 _rv = pm4x25_port_autoneg_set(unit, port, pm_info, phy_flags, an); 878 SOC_FUNC_RETURN; 879 } 880 881 exit: 882 SOC_FUNC_RETURN; 883 } 884 885 int cpm4x25_port_autoneg_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, phymod_autoneg_control_t* an) { 886 int val; 887 SOC_INIT_FUNC_DEFS; 888 an->enable = 0; 889 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 890 if(val == 0) { 891 _rv = pm4x25_port_autoneg_get(unit, port, pm_info, phy_flags, an); 892 SOC_FUNC_RETURN; 893 } 894 895 exit: 896 897 SOC_FUNC_RETURN; 898 } 899 int cpm4x25_port_ability_advert_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, 900 portmod_port_ability_t* ability) { 901 int val; 902 SOC_INIT_FUNC_DEFS; 903 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 904 if(val == 0) { 905 _rv = pm4x25_port_ability_advert_get(unit, port, pm_info, phy_flags, ability); 906 SOC_FUNC_RETURN; 907 } 908 909 exit: 910 SOC_FUNC_RETURN; 911 } 912 913 int cpm4x25_port_ability_advert_set(int unit, int port, pm_info_t pm_info, uint32 phy_flags, 914 portmod_port_ability_t* ability) { 915 int val; 916 SOC_INIT_FUNC_DEFS; 917 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 918 if(val == 0) { 919 _rv = pm4x25_port_ability_advert_set(unit, port, pm_info, phy_flags, ability); 920 SOC_FUNC_RETURN; 921 } 922 923 exit: 924 SOC_FUNC_RETURN; 925 } 926 927 int cpm4x25_port_autoneg_status_get (int unit, int port, pm_info_t pm_info, 928 phymod_autoneg_status_t* an_status) { 929 int val; 930 SOC_INIT_FUNC_DEFS; 931 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 932 if(val == 0) { 933 _rv = pm4x25_port_autoneg_status_get(unit, port, pm_info, an_status); 934 SOC_FUNC_RETURN; 935 } 936 937 exit: 938 SOC_FUNC_RETURN; 939 } 940 941 int cpm4x25_port_ability_remote_get(int unit, int port, pm_info_t pm_info, uint32 phy_flags, 942 portmod_port_ability_t* ability) { 943 int val; 944 SOC_INIT_FUNC_DEFS; 945 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 946 if(val == 0) { 947 _rv = pm4x25_port_ability_remote_get(unit, port, pm_info, phy_flags, ability); 948 SOC_FUNC_RETURN; 949 } 950 951 exit: 952 SOC_FUNC_RETURN; 953 } 954 955 int cpm4x25_port_encap_set(int unit, int port, pm_info_t pm_info, int flags, portmod_encap_t encap) 956 { 957 int val; 958 SOC_INIT_FUNC_DEFS; 959 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 960 if(val == 0) { 961 _rv = pm4x25_port_encap_set(unit, port, pm_info, flags, encap); 962 SOC_FUNC_RETURN; 963 } 964 965 exit: 966 SOC_FUNC_RETURN; 967 968 } 969 970 int cpm4x25_port_encap_get(int unit, int port, pm_info_t pm_info, int* flags, portmod_encap_t* encap) 971 { 972 int val; 973 SOC_INIT_FUNC_DEFS; 974 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 975 if(val == 0) { 976 _rv = pm4x25_port_encap_get(unit, port, pm_info, flags, encap); 977 SOC_FUNC_RETURN; 978 } 979 *encap = _SHR_PORT_ENCAP_CPRI; 980 981 exit: 982 SOC_FUNC_RETURN; 983 984 } 985 986 static int 987 _cprimod_port_speed_t_to_int ( 988 cprimod_port_speed_t speedi) 989 { 990 int speedo; 991 992 switch(speedi) { 993 case cprimodSpd1228p8: 994 speedo = 1228; 995 break; 996 case cprimodSpd2457p6: 997 speedo = 2457; 998 break; 999 case cprimodSpd3072p0: 1000 speedo = 3072; 1001 break; 1002 case cprimodSpd4915p2: 1003 speedo = 4915; 1004 break; 1005 case cprimodSpd6144p0: 1006 speedo = 6144; 1007 break; 1008 case cprimodSpd9830p4: 1009 speedo = 9830; 1010 break; 1011 case cprimodSpd10137p6: 1012 speedo = 10137; 1013 break; 1014 case cprimodSpd12165p12: 1015 speedo = 12165; 1016 break; 1017 case cprimodSpd24330p24: 1018 speedo = 24330; 1019 break; 1020 default: 1021 speedo = 1228; 1022 break; 1023 } 1024 1025 return speedo; 1026 } 1027 1028 static cprimod_port_speed_t 1029 _int_to_cprimod_port_speed_t ( 1030 int speedi) 1031 { 1032 cprimod_port_speed_t speedo; 1033 switch(speedi) { 1034 case 1228: 1035 speedo = cprimodSpd1228p8; 1036 break; 1037 case 2457: 1038 speedo = cprimodSpd2457p6; 1039 break; 1040 case 3072: 1041 speedo = cprimodSpd3072p0; 1042 break; 1043 case 4915: 1044 speedo = cprimodSpd4915p2; 1045 break; 1046 case 6144: 1047 speedo = cprimodSpd6144p0; 1048 break; 1049 case 9830: 1050 speedo = cprimodSpd9830p4; 1051 break; 1052 case 10137: 1053 speedo = cprimodSpd10137p6; 1054 break; 1055 case 12165: 1056 speedo = cprimodSpd12165p12; 1057 break; 1058 case 24330: 1059 speedo = cprimodSpd24330p24; 1060 break; 1061 default: 1062 speedo = cprimodSpd1228p8; 1063 break; 1064 } 1065 1066 return speedo; 1067 } 1068 1069 static cprimod_supported_port_speed_t 1070 _int_to_cprimod_supported_port_speed_t ( 1071 int speedi) 1072 { 1073 cprimod_supported_port_speed_t speedo; 1074 switch(speedi) { 1075 case 1228: 1076 speedo = cprimodSupportedSpd1228p8; 1077 break; 1078 case 2457: 1079 speedo = cprimodSupportedSpd2457p6; 1080 break; 1081 case 3072: 1082 speedo = cprimodSupportedSpd3072p0; 1083 break; 1084 case 4915: 1085 speedo = cprimodSupportedSpd4915p2; 1086 break; 1087 case 6144: 1088 speedo = cprimodSupportedSpd6144p0; 1089 break; 1090 case 9830: 1091 speedo = cprimodSupportedSpd9830p4; 1092 break; 1093 case 10137: 1094 speedo = cprimodSupportedSpd10137p6; 1095 break; 1096 case 12165: 1097 speedo = cprimodSupportedSpd12165p12; 1098 break; 1099 case 24330: 1100 speedo = cprimodSupportedSpd24330p24; 1101 break; 1102 default: 1103 speedo = cprimodSupportedSpd1228p8; 1104 break; 1105 } 1106 1107 return speedo; 1108 } 1109 1110 static int 1111 _cprimod_port_speed_id_to_vco ( 1112 int speed_id, portmod_encap_t encap) 1113 { 1114 int vco_value; 1115 int speed_loc; 1116 if(encap == _SHR_PORT_ENCAP_CPRI) { 1117 if(speed_id >= 1228) { 1118 speed_loc = _int_to_cprimod_supported_port_speed_t(speed_id); 1119 } else { 1120 speed_loc = speed_id; 1121 } 1122 switch(speed_loc) { 1123 case cprimodSupportedSpd1228p8: 1124 vco_value = phymod_TSCF_PLL_DIV160; 1125 break; 1126 case cprimodSupportedSpd2457p6: 1127 vco_value = phymod_TSCF_PLL_DIV160; 1128 break; 1129 case cprimodSupportedSpd3072p0: 1130 vco_value = phymod_TSCF_PLL_DIV200; 1131 break; 1132 case cprimodSupportedSpd4915p2: 1133 vco_value = phymod_TSCF_PLL_DIV160; 1134 break; 1135 case cprimodSupportedSpd6144p0: 1136 vco_value = phymod_TSCF_PLL_DIV200; 1137 break; 1138 case cprimodSupportedSpd9830p4: 1139 vco_value = phymod_TSCF_PLL_DIV160; 1140 break; 1141 case cprimodSupportedSpd10137p6: 1142 vco_value = phymod_TSCF_PLL_DIV165; 1143 break; 1144 case cprimodSupportedSpd12165p12: 1145 vco_value = phymod_TSCF_PLL_DIV198; 1146 break; 1147 case cprimodSupportedSpd24330p24: 1148 vco_value = phymod_TSCF_PLL_DIV198; 1149 break; 1150 default: 1151 vco_value = phymod_TSCF_PLL_DIV160; 1152 break; 1153 } 1154 } else { 1155 vco_value = phymod_TSCF_PLL_DIV200; 1156 } 1157 1158 return vco_value; 1159 } 1160 1161 1162 int cpm4x25_port_interface_config_set(int unit, int port, pm_info_t pm_info, const portmod_port_interface_config_t* config, int phy_init_flags) 1163 { 1164 int val; 1165 int lane; 1166 phymod_phy_access_t phy_access; 1167 cprimod_port_interface_config_t config_t; 1168 SOC_INIT_FUNC_DEFS; 1169 1170 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 1171 if(val == 0) { 1172 _rv = pm4x25_port_interface_config_set(unit, port, pm_info, config, phy_init_flags); 1173 SOC_FUNC_RETURN; 1174 } 1175 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 1176 lane = (SOC_INFO(unit).port_l2p_mapping[port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 1177 phy_access.access.lane_mask = (1<<lane); 1178 config_t.speed = _int_to_cprimod_port_speed_t(config->speed); 1179 config_t.interface = cprimodCpri; 1180 if (phy_init_flags == PORTMOD_INIT_F_TX_ONLY) { 1181 _SOC_IF_ERR_EXIT(cprimod_port_tx_interface_config_set(unit, port, &phy_access, 1182 &config_t)); 1183 } 1184 if (phy_init_flags == PORTMOD_INIT_F_RX_ONLY) { 1185 _SOC_IF_ERR_EXIT(cprimod_port_rx_interface_config_set(unit, port, &phy_access, 1186 &config_t)); 1187 } 1188 1189 exit: 1190 SOC_FUNC_RETURN; 1191 } 1192 1193 int cpm4x25_port_interface_config_get(int unit, int port, pm_info_t pm_info, portmod_port_interface_config_t* config, int phy_init_flags) 1194 { 1195 int val; 1196 cprimod_port_interface_config_t config_t; 1197 SOC_INIT_FUNC_DEFS; 1198 1199 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 1200 if(val == 0) { 1201 _rv = pm4x25_port_interface_config_get(unit, port, pm_info, config, phy_init_flags); 1202 SOC_FUNC_RETURN; 1203 } 1204 if (phy_init_flags == PORTMOD_INIT_F_TX_ONLY) { 1205 _SOC_IF_ERR_EXIT(cprimod_port_tx_interface_config_get(unit, port, 1206 &config_t)); 1207 } else { 1208 _SOC_IF_ERR_EXIT(cprimod_port_rx_interface_config_get(unit, port, 1209 &config_t)); 1210 } 1211 config->speed = _cprimod_port_speed_t_to_int (config_t.speed); 1212 1213 if (config_t.interface == cprimodCpri) { 1214 config->encap_mode = _SHR_PORT_ENCAP_CPRI; 1215 config->interface = SOC_PORT_IF_CPRI; 1216 } else if (config_t.interface == cprimodRsvd4) { 1217 config->encap_mode = _SHR_PORT_ENCAP_RSVD4; 1218 config->interface = SOC_PORT_IF_RSVD4; 1219 1220 } 1221 1222 1223 exit: 1224 SOC_FUNC_RETURN; 1225 } 1226 1227 int cpm4x25_port_speed_get(int unit, int port, pm_info_t pm_info, int* speed) 1228 { 1229 int val; 1230 SOC_INIT_FUNC_DEFS; 1231 1232 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 1233 if(val == 0) { 1234 _SOC_IF_ERR_EXIT(pm4x25_port_speed_get(unit, port, pm_info, speed)); 1235 } 1236 1237 exit: 1238 SOC_FUNC_RETURN; 1239 } 1240 1241 int cpm4x25_port_rsvd4_rx_frame_optional_config_set(int unit, int port, pm_info_t pm_info, cprimod_rsvd4_rx_config_field_t field, int value) 1242 { 1243 SOC_INIT_FUNC_DEFS; 1244 1245 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_rx_frame_optional_config_set(unit, port, 1246 field, value)); 1247 1248 exit: 1249 SOC_FUNC_RETURN; 1250 1251 } 1252 1253 int cpm4x25_port_rsvd4_rx_frame_optional_config_get(int unit, int port, pm_info_t pm_info, cprimod_rsvd4_rx_config_field_t field, int* value) 1254 { 1255 SOC_INIT_FUNC_DEFS; 1256 1257 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_rx_frame_optional_config_get(unit, port, 1258 field, value)); 1259 1260 exit: 1261 SOC_FUNC_RETURN; 1262 1263 } 1264 1265 int cpm4x25_port_rsvd4_tx_frame_optional_config_set(int unit, int port, pm_info_t pm_info, cprimod_rsvd4_tx_config_field_t field, int value) 1266 { 1267 SOC_INIT_FUNC_DEFS; 1268 1269 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_tx_frame_optional_config_set(unit, port, 1270 field, value)); 1271 1272 exit: 1273 SOC_FUNC_RETURN; 1274 1275 } 1276 1277 int cpm4x25_port_rsvd4_tx_frame_optional_config_get(int unit, int port, pm_info_t pm_info, cprimod_rsvd4_tx_config_field_t field, int* value) 1278 { 1279 SOC_INIT_FUNC_DEFS; 1280 1281 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_tx_frame_optional_config_get(unit, port, 1282 field, value)); 1283 1284 exit: 1285 SOC_FUNC_RETURN; 1286 1287 } 1288 1289 1290 int cpm4x25_cpri_port_rx_frame_optional_config_set(int unit, int port, pm_info_t pm_info, cprimod_rx_config_field_t field, int value) 1291 { 1292 SOC_INIT_FUNC_DEFS; 1293 1294 _SOC_IF_ERR_EXIT(cprimod_port_rx_frame_optional_config_set(unit, port, field, 1295 value)); 1296 1297 exit: 1298 SOC_FUNC_RETURN; 1299 } 1300 1301 int cpm4x25_cpri_port_rx_frame_optional_config_get(int unit, int port, pm_info_t pm_info, cprimod_rx_config_field_t field, int* value) 1302 { 1303 SOC_INIT_FUNC_DEFS; 1304 1305 _SOC_IF_ERR_EXIT(cprimod_port_rx_frame_optional_config_get(unit, port, field, 1306 value)); 1307 1308 exit: 1309 SOC_FUNC_RETURN; 1310 } 1311 1312 int cpm4x25_cpri_port_tx_frame_optional_config_set(int unit, int port, pm_info_t pm_info, cprimod_tx_config_field_t field, uint32 value) 1313 { 1314 SOC_INIT_FUNC_DEFS; 1315 1316 _SOC_IF_ERR_EXIT(cprimod_port_tx_frame_optional_config_set(unit, port, field, 1317 value)); 1318 1319 exit: 1320 SOC_FUNC_RETURN; 1321 } 1322 1323 int cpm4x25_cpri_port_tx_frame_optional_config_get(int unit, int port, pm_info_t pm_info, cprimod_tx_config_field_t field, uint32* value) 1324 { 1325 SOC_INIT_FUNC_DEFS; 1326 1327 _SOC_IF_ERR_EXIT(cprimod_port_tx_frame_optional_config_get(unit, port, field, 1328 value)); 1329 1330 exit: 1331 SOC_FUNC_RETURN; 1332 } 1333 1334 int cpm4x25_cpri_port_stage_activate(int unit, int port, pm_info_t pm_info, portmod_cpri_stage_t stage) 1335 { 1336 cprimod_basic_frame_table_id_t table; 1337 int sync_enable = TRUE; 1338 SOC_INIT_FUNC_DEFS; 1339 1340 if (stage == portmodCpriStageRx) { 1341 _SOC_IF_ERR_EXIT 1342 (cprimod_basic_frame_parser_active_table_get(unit, port,&table)); 1343 if (table == cprimod_basic_frame_table_0) { 1344 _SOC_IF_ERR_EXIT 1345 (cprimod_basic_frame_parser_active_table_set(unit, port,cprimod_basic_frame_table_1, sync_enable)); 1346 } else { 1347 _SOC_IF_ERR_EXIT 1348 (cprimod_basic_frame_parser_active_table_set(unit, port,cprimod_basic_frame_table_0, sync_enable)); 1349 } 1350 } else { 1351 _SOC_IF_ERR_EXIT 1352 (cprimod_basic_frame_assembly_active_table_get(unit, port,&table)); 1353 if (table == cprimod_basic_frame_table_0) { 1354 _SOC_IF_ERR_EXIT 1355 (cprimod_basic_frame_assembly_active_table_set(unit, port,cprimod_basic_frame_table_1, sync_enable)); 1356 } else { 1357 _SOC_IF_ERR_EXIT 1358 (cprimod_basic_frame_assembly_active_table_set(unit, port,cprimod_basic_frame_table_0, sync_enable)); 1359 } 1360 } 1361 exit: 1362 SOC_FUNC_RETURN; 1363 1364 } 1365 1366 int cpm4x25_port_rsvd4_rx_speed_set(int unit, int port, pm_info_t pm_info, cprimod_port_rsvd4_speed_mult_t speed) 1367 { 1368 int lane; 1369 phymod_phy_access_t phy_access; 1370 SOC_INIT_FUNC_DEFS; 1371 1372 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 1373 lane = (SOC_INFO(unit).port_l2p_mapping[port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 1374 phy_access.access.lane_mask = (1<<lane); 1375 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_rx_speed_set(unit, port, &phy_access, speed)); 1376 _SOC_IF_ERR_EXIT 1377 (cprimod_basic_frame_parser_switch_active_table(unit, port)); 1378 exit: 1379 SOC_FUNC_RETURN; 1380 1381 } 1382 1383 int cpm4x25_port_rsvd4_rx_speed_get(int unit, int port, pm_info_t pm_info, cprimod_port_rsvd4_speed_mult_t* speed) 1384 { 1385 SOC_INIT_FUNC_DEFS; 1386 1387 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_rx_speed_get(unit, port, speed)); 1388 1389 exit: 1390 SOC_FUNC_RETURN; 1391 1392 } 1393 1394 1395 int cpm4x25_port_rsvd4_tx_speed_set(int unit, int port, pm_info_t pm_info, cprimod_port_rsvd4_speed_mult_t speed) 1396 { 1397 int lane; 1398 phymod_phy_access_t phy_access; 1399 SOC_INIT_FUNC_DEFS; 1400 1401 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 1402 lane = (SOC_INFO(unit).port_l2p_mapping[port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 1403 phy_access.access.lane_mask = (1<<lane); 1404 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_tx_speed_set(unit, port, &phy_access, speed)); 1405 _SOC_IF_ERR_EXIT 1406 (cprimod_basic_frame_assembly_switch_active_table(unit, port)); 1407 1408 exit: 1409 SOC_FUNC_RETURN; 1410 1411 } 1412 1413 int cpm4x25_port_rsvd4_tx_speed_get(int unit, int port, pm_info_t pm_info, cprimod_port_rsvd4_speed_mult_t* speed) 1414 { 1415 SOC_INIT_FUNC_DEFS; 1416 1417 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_tx_speed_get(unit, port, speed)); 1418 1419 exit: 1420 SOC_FUNC_RETURN; 1421 1422 } 1423 1424 1425 int cpm4x25_cpri_port_rsvd4_tx_fsm_state_set(int unit, int port, pm_info_t pm_info, cprimod_rsvd4_tx_fsm_state_t state) 1426 { 1427 SOC_INIT_FUNC_DEFS; 1428 1429 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_tx_fsm_state_set(unit, port, state)); 1430 1431 exit: 1432 SOC_FUNC_RETURN; 1433 1434 } 1435 1436 int cpm4x25_cpri_port_rsvd4_rx_fsm_state_set(int unit, int port, pm_info_t pm_info, cprimod_rsvd4_rx_fsm_state_t state) 1437 { 1438 SOC_INIT_FUNC_DEFS; 1439 1440 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_rx_fsm_state_set(unit, port, state)); 1441 1442 exit: 1443 SOC_FUNC_RETURN; 1444 1445 } 1446 1447 int cpm4x25_cpri_port_rsvd4_tx_override_set(int unit, int port, pm_info_t pm_info, cprimod_rsvd4_tx_overide_t parameter, int enable, int value) 1448 { 1449 SOC_INIT_FUNC_DEFS; 1450 1451 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_tx_overide_set(unit, port, parameter, 1452 enable, value)); 1453 1454 exit: 1455 SOC_FUNC_RETURN; 1456 1457 } 1458 1459 int cpm4x25_cpri_port_rsvd4_rx_override_set(int unit, int port, pm_info_t pm_info, cprimod_rsvd4_rx_overide_t parameter, int enable, int value) 1460 { 1461 SOC_INIT_FUNC_DEFS; 1462 1463 _SOC_IF_ERR_EXIT(cprimod_port_rsvd4_rx_overide_set(unit, port, parameter, 1464 enable, value)); 1465 1466 exit: 1467 SOC_FUNC_RETURN; 1468 1469 } 1470 1471 int cpm4x25_cpri_port_rx_axc_frame_add(int unit, int port, pm_info_t pm_info, uint32 axc_id, portmod_cpri_axc_frame_info_t* frame_info) 1472 { 1473 uint32 queue_num = 0xFF; 1474 uint32 num_axc ; 1475 uint32 num_container; 1476 uint32 num_bits_per_container; 1477 int offset; 1478 SOC_INIT_FUNC_DEFS; 1479 1480 num_axc = 1; 1481 num_container = 1; 1482 num_bits_per_container = frame_info->num_bits; 1483 1484 if (frame_info->container_info.map_method == cprimod_cpri_frame_map_method_3) { 1485 num_axc = frame_info->container_info.Na; 1486 num_container = frame_info->container_info.Nc; 1487 if (frame_info->num_bits != ( 2 * frame_info->encap_data_info.sample_size * num_container)) { 1488 return SOC_E_CONFIG; 1489 } 1490 } 1491 1492 if ((num_container > 1) && 1493 (num_axc > 1)) { 1494 if ((frame_info->num_bits % num_container) != 0) { 1495 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 1496 (_SOC_MSG("Number of Bits %d cannot be equally divided between Nc %d.\n"), 1497 frame_info->num_bits, 1498 num_container)); 1499 } 1500 1501 num_bits_per_container = frame_info->num_bits / num_container; 1502 for (offset = 0; offset < num_container; offset++) { 1503 _SOC_IF_ERR_EXIT 1504 (cprimod_rx_axc_basic_frame_add(unit, port, axc_id, 1505 frame_info->start_bit+(offset*num_bits_per_container), 1506 num_bits_per_container)); 1507 } 1508 } else { 1509 _SOC_IF_ERR_EXIT 1510 (cprimod_rx_axc_basic_frame_add(unit, port, axc_id, frame_info->start_bit, frame_info->num_bits)); 1511 } 1512 _SOC_IF_ERR_EXIT 1513 (cprimod_cpri_rx_axc_container_config_set(unit, port, axc_id, &frame_info->container_info)); 1514 1515 /* 1516 * In data AxC, the AxC number and Queue number are identical. 1517 */ 1518 queue_num = axc_id; 1519 1520 for (offset = 0; offset < num_axc ; offset++) { 1521 _SOC_IF_ERR_EXIT 1522 (cprimod_rx_roe_payload_size_set(unit, port, axc_id+offset, &frame_info->roe_payload_info)); 1523 _SOC_IF_ERR_EXIT 1524 (cprimod_cpri_encap_data_config_set(unit, port, queue_num+offset, &frame_info->encap_data_info )); 1525 } 1526 1527 /* activate the basic frame to take the new configuration. */ 1528 _SOC_IF_ERR_EXIT 1529 (cpm4x25_cpri_port_stage_activate(unit, port, pm_info, portmodCpriStageRx)); 1530 exit: 1531 SOC_FUNC_RETURN; 1532 1533 } 1534 1535 int cpm4x25_cpri_port_rx_axc_frame_delete(int unit, int port, pm_info_t pm_info, uint32 axc_id) 1536 { 1537 cprimod_cpri_container_config_t container_config; 1538 cprimod_encap_decap_data_config_t encap_data_config; 1539 cprimod_payload_size_info_t roe_payload_info; 1540 SOC_INIT_FUNC_DEFS; 1541 1542 _SOC_IF_ERR_EXIT 1543 (cprimod_rx_axc_basic_frame_delete(unit, port, axc_id)); 1544 1545 /* activate the basic frame to take the new configuration. */ 1546 _SOC_IF_ERR_EXIT 1547 (cpm4x25_cpri_port_stage_activate(unit, port, pm_info, portmodCpriStageRx)); 1548 1549 /* Flush encap memory and framer state. */ 1550 _SOC_IF_ERR_EXIT 1551 (cprimod_encap_memory_clear(unit, port, axc_id)); 1552 1553 _SOC_IF_ERR_EXIT 1554 (cprimod_cpri_rx_framer_state_clear(unit, port, axc_id)); 1555 1556 /* clear the relate container parser entry. */ 1557 _SOC_IF_ERR_EXIT 1558 (cprimod_cpri_container_config_t_init(&container_config)); 1559 1560 _SOC_IF_ERR_EXIT 1561 (cprimod_cpri_rx_axc_container_config_set(unit, port, axc_id, &container_config)); 1562 1563 /* clear encap data configuration. */ 1564 _SOC_IF_ERR_EXIT 1565 (cprimod_encap_decap_data_config_t_init(&encap_data_config)); 1566 1567 /* Need to set agnostic_mode to 1 not to run thru allocation */ 1568 encap_data_config.is_agnostic = 1; 1569 1570 _SOC_IF_ERR_EXIT 1571 (cprimod_cpri_encap_data_config_set(unit, port, axc_id, &encap_data_config )); 1572 1573 /* clear payload info. */ 1574 _SOC_IF_ERR_EXIT 1575 (cprimod_payload_size_info_t_init(&roe_payload_info)); 1576 1577 _SOC_IF_ERR_EXIT 1578 (cprimod_rx_roe_payload_size_set(unit, port, axc_id, &roe_payload_info)); 1579 1580 exit: 1581 SOC_FUNC_RETURN; 1582 1583 } 1584 1585 1586 int cpm4x25_cpri_port_rx_axc_frame_get(int unit, int port, pm_info_t pm_info, uint32 axc_id, uint32 from_get_all, portmod_cpri_axc_frame_info_t* frame_info) 1587 { 1588 uint32 queue_num = 0xFF; 1589 cprimod_basic_frame_table_id_t active_table; 1590 cprimod_basic_frame_usage_entry_t* usage_table=NULL; 1591 int num_entries = 0; 1592 uint32 start_bit = 0; 1593 uint32 num_bits = 0; 1594 uint32 Naxc = 0; 1595 uint32 num_container = 0; 1596 int i; 1597 1598 SOC_INIT_FUNC_DEFS; 1599 1600 _SOC_IF_ERR_EXIT 1601 (cprimod_basic_frame_parser_active_table_get(unit, port, &active_table)); 1602 1603 1604 usage_table = (cprimod_basic_frame_usage_entry_t *) sal_alloc 1605 ((sizeof(cprimod_basic_frame_table_id_t)*CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY), 1606 "cpm4x25"); 1607 1608 SOC_NULL_CHECK(usage_table); 1609 num_entries = CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY; 1610 1611 1612 _SOC_IF_ERR_EXIT 1613 (cprimod_rx_axc_basic_frame_get(unit, port, axc_id, active_table, usage_table, &num_entries)); 1614 1615 start_bit = usage_table[0].start_bit; 1616 1617 for (i=0;i<num_entries;i++) { 1618 num_bits = num_bits + usage_table[i].num_bits; 1619 } 1620 1621 if (num_entries == 0) { 1622 if (from_get_all) { 1623 frame_info->start_bit = 0; 1624 frame_info->num_bits = 0; 1625 } else { 1626 return SOC_E_NOT_FOUND; 1627 } 1628 } else { 1629 1630 _SOC_IF_ERR_EXIT 1631 (cprimod_cpri_rx_axc_container_config_get(unit, port, axc_id, &frame_info->container_info)); 1632 1633 frame_info->start_bit = start_bit; 1634 frame_info->num_bits = num_bits; 1635 1636 if (frame_info->container_info.map_method == cprimod_cpri_frame_map_method_1) { 1637 frame_info->container_info.Naxc = num_bits; 1638 if (num_bits != 0) { 1639 frame_info->container_info.K = frame_info->container_info.cblk_cnt / num_bits; 1640 } 1641 } 1642 1643 if (frame_info->container_info.map_method == cprimod_cpri_frame_map_method_3) { 1644 Naxc = frame_info->container_info.Naxc; 1645 num_container = num_bits / Naxc; 1646 frame_info->container_info.Nc = num_container; 1647 frame_info->container_info.K = frame_info->container_info.cblk_cnt/ (num_container * Naxc); 1648 frame_info->container_info.Nst = 0; 1649 } 1650 1651 _SOC_IF_ERR_EXIT 1652 (cprimod_rx_roe_payload_size_get(unit, port, axc_id, &frame_info->roe_payload_info)); 1653 /* 1654 * In data AxC, the AxC number and Queue number are identical. 1655 */ 1656 queue_num = axc_id; 1657 _SOC_IF_ERR_EXIT 1658 (cprimod_cpri_encap_data_config_get(unit, port, queue_num, &frame_info->encap_data_info )); 1659 } 1660 exit: 1661 sal_free(usage_table); 1662 SOC_FUNC_RETURN; 1663 1664 } 1665 1666 1667 int cpm4x25_cpri_port_tx_axc_frame_add(int unit, int port, pm_info_t pm_info, uint32 axc_id, portmod_cpri_axc_frame_info_t* frame_info) 1668 { 1669 uint32 queue_num = 0xFF; 1670 uint32 num_axc; 1671 uint32 num_container; 1672 uint32 num_bits_per_container; 1673 int offset; 1674 1675 SOC_INIT_FUNC_DEFS; 1676 1677 num_axc = 1; 1678 num_container = 1; 1679 num_bits_per_container = frame_info->num_bits; 1680 1681 if (frame_info->container_info.map_method == cprimod_cpri_frame_map_method_3) { 1682 num_axc = frame_info->container_info.Na; 1683 num_container = frame_info->container_info.Nc; 1684 if (frame_info->num_bits != (2 * frame_info->encap_data_info.sample_size * num_container)) { 1685 return SOC_E_CONFIG; 1686 } 1687 1688 } 1689 1690 if ((num_container > 1) && 1691 (num_axc > 1)) { 1692 if ((frame_info->num_bits % num_container) != 0) { 1693 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 1694 (_SOC_MSG("Number of Bits %d cannot be equally divided between Nc %d.\n"), 1695 frame_info->num_bits, 1696 num_container)); 1697 } 1698 1699 num_bits_per_container = frame_info->num_bits / num_container; 1700 for (offset = 0; offset < num_container; offset++) { 1701 _SOC_IF_ERR_EXIT 1702 (cprimod_tx_axc_basic_frame_add(unit, port, axc_id, 1703 frame_info->start_bit+ (offset*num_bits_per_container), 1704 num_bits_per_container)); 1705 } 1706 } else { 1707 _SOC_IF_ERR_EXIT 1708 (cprimod_tx_axc_basic_frame_add(unit, port, axc_id, frame_info->start_bit, frame_info->num_bits)); 1709 } 1710 _SOC_IF_ERR_EXIT 1711 (cprimod_cpri_tx_axc_container_config_set(unit, port, axc_id, &frame_info->container_info)); 1712 1713 /* 1714 * In data AxC, the AxC number and Queue number are identical. 1715 */ 1716 queue_num = axc_id; 1717 1718 for (offset = 0; offset < num_axc ; offset++) { 1719 1720 _SOC_IF_ERR_EXIT 1721 (cprimod_tx_roe_payload_size_set(unit, port, axc_id+offset, &frame_info->roe_payload_info)); 1722 _SOC_IF_ERR_EXIT 1723 (cprimod_cpri_decap_data_config_set(unit, port, queue_num+offset, &frame_info->encap_data_info )); 1724 } 1725 1726 /* activate the basic frame to take the new configuration. */ 1727 _SOC_IF_ERR_EXIT 1728 (cpm4x25_cpri_port_stage_activate(unit, port, pm_info, portmodCpriStageTx)); 1729 exit: 1730 SOC_FUNC_RETURN; 1731 } 1732 1733 int cpm4x25_cpri_port_tx_axc_frame_delete(int unit, int port, pm_info_t pm_info, uint32 axc_id) 1734 { 1735 cprimod_cpri_container_config_t container_config; 1736 cprimod_encap_decap_data_config_t decap_data_config; 1737 cprimod_payload_size_info_t roe_payload_info; 1738 SOC_INIT_FUNC_DEFS; 1739 1740 _SOC_IF_ERR_EXIT 1741 (cprimod_tx_axc_basic_frame_delete(unit, port, axc_id)); 1742 1743 _SOC_IF_ERR_EXIT 1744 (cpm4x25_cpri_port_stage_activate(unit, port, pm_info, portmodCpriStageTx)); 1745 1746 /* Flush the framer state. */ 1747 _SOC_IF_ERR_EXIT 1748 (cprimod_cpri_tx_framer_state_clear(unit, port, axc_id)); 1749 1750 _SOC_IF_ERR_EXIT 1751 (cprimod_decap_memory_clear(unit, port, axc_id)); 1752 1753 /* clear the relate container parser entry. */ 1754 _SOC_IF_ERR_EXIT 1755 (cprimod_cpri_container_config_t_init(&container_config)); 1756 1757 _SOC_IF_ERR_EXIT 1758 (cprimod_cpri_tx_axc_container_config_set(unit, port, axc_id, &container_config)); 1759 1760 /* clear encap data configuration. */ 1761 _SOC_IF_ERR_EXIT 1762 (cprimod_encap_decap_data_config_t_init(&decap_data_config)); 1763 1764 /* Need to set agnostic_mode to 1 not to run thru allocation */ 1765 decap_data_config.is_agnostic = 1; 1766 1767 _SOC_IF_ERR_EXIT 1768 (cprimod_cpri_decap_data_config_set(unit, port, axc_id, &decap_data_config )); 1769 1770 /* clear payload info. */ 1771 _SOC_IF_ERR_EXIT 1772 (cprimod_payload_size_info_t_init(&roe_payload_info)); 1773 1774 _SOC_IF_ERR_EXIT 1775 (cprimod_tx_roe_payload_size_set(unit, port, axc_id, &roe_payload_info)); 1776 1777 exit: 1778 SOC_FUNC_RETURN; 1779 1780 } 1781 1782 1783 1784 int cpm4x25_cpri_port_tx_axc_frame_get(int unit, int port, pm_info_t pm_info, uint32 axc_id, uint32 from_get_all, portmod_cpri_axc_frame_info_t* frame_info) 1785 { 1786 uint32 queue_num = 0xFF; 1787 cprimod_basic_frame_table_id_t active_table; 1788 cprimod_basic_frame_usage_entry_t* usage_table=NULL; 1789 int num_entries; 1790 uint32 start_bit = 0; 1791 uint32 num_bits = 0; 1792 uint32 Naxc = 0; 1793 uint32 num_container = 0; 1794 int i; 1795 1796 SOC_INIT_FUNC_DEFS; 1797 1798 _SOC_IF_ERR_EXIT 1799 (cprimod_basic_frame_assembly_active_table_get(unit, port, &active_table)); 1800 1801 usage_table = (cprimod_basic_frame_usage_entry_t *) sal_alloc 1802 ((sizeof(cprimod_basic_frame_table_id_t)*CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY), 1803 "cpm4x25"); 1804 1805 SOC_NULL_CHECK(usage_table); 1806 num_entries = CPRIMOD_BASIC_FRAME_MAX_NUM_ENTRY; 1807 1808 1809 _SOC_IF_ERR_EXIT 1810 (cprimod_tx_axc_basic_frame_get(unit, port, axc_id, active_table, usage_table, &num_entries)); 1811 1812 start_bit = usage_table[0].start_bit; 1813 1814 for (i=0;i<num_entries;i++) { 1815 num_bits = num_bits + usage_table[i].num_bits; 1816 } 1817 1818 if (num_entries == 0) { 1819 if (from_get_all) { 1820 frame_info->start_bit = 0; 1821 frame_info->num_bits = 0; 1822 } else { 1823 return SOC_E_NOT_FOUND; 1824 } 1825 } else { 1826 1827 1828 _SOC_IF_ERR_EXIT 1829 (cprimod_cpri_tx_axc_container_config_get(unit, port, axc_id, &frame_info->container_info)); 1830 1831 frame_info->start_bit = start_bit; 1832 frame_info->num_bits = num_bits; 1833 1834 if (frame_info->container_info.map_method == cprimod_cpri_frame_map_method_1) { 1835 frame_info->container_info.Naxc = num_bits; 1836 if (num_bits != 0) { 1837 frame_info->container_info.K = frame_info->container_info.cblk_cnt / num_bits; 1838 } 1839 } 1840 1841 if (frame_info->container_info.map_method == cprimod_cpri_frame_map_method_3) { 1842 Naxc = frame_info->container_info.Naxc; 1843 num_container = num_bits / Naxc; 1844 frame_info->container_info.Nc = num_container; 1845 frame_info->container_info.K = frame_info->container_info.cblk_cnt/ (num_container * Naxc); 1846 frame_info->container_info.Nst = 0; 1847 } 1848 1849 _SOC_IF_ERR_EXIT 1850 (cprimod_tx_roe_payload_size_get(unit, port, axc_id, &frame_info->roe_payload_info)); 1851 /* 1852 * In data AxC, the AxC number and Queue number are identical. 1853 */ 1854 queue_num = axc_id; 1855 _SOC_IF_ERR_EXIT 1856 (cprimod_cpri_decap_data_config_get(unit, port, queue_num, &frame_info->encap_data_info )); 1857 } 1858 exit: 1859 sal_free(usage_table); 1860 SOC_FUNC_RETURN; 1861 } 1862 1863 int cpm4x25_cpri_port_encap_set(int unit, int port, pm_info_t pm_info, uint32 queue_num, cprimod_encap_header_config_t* config) 1864 { 1865 SOC_INIT_FUNC_DEFS; 1866 1867 _SOC_IF_ERR_EXIT 1868 (cprimod_encap_header_config_set(unit, port, queue_num, config)); 1869 1870 exit: 1871 SOC_FUNC_RETURN; 1872 1873 } 1874 1875 int cpm4x25_cpri_port_encap_get(int unit, int port, pm_info_t pm_info, uint32 queue_num, cprimod_encap_header_config_t* config) 1876 { 1877 SOC_INIT_FUNC_DEFS; 1878 1879 _SOC_IF_ERR_EXIT 1880 (cprimod_encap_header_config_get(unit, port, queue_num, config)); 1881 1882 exit: 1883 SOC_FUNC_RETURN; 1884 1885 } 1886 1887 int cpm4x25_cpri_port_encap_roe_ordering_info_set(int unit, int port, pm_info_t pm_info, uint32 index, cprimod_encap_ordering_info_entry_t* config) 1888 { 1889 SOC_INIT_FUNC_DEFS; 1890 1891 _SOC_IF_ERR_EXIT 1892 (cprimod_encap_ordering_info_entry_set(unit, port, index, config)); 1893 1894 exit: 1895 SOC_FUNC_RETURN; 1896 1897 } 1898 1899 int cpm4x25_cpri_port_encap_roe_ordering_info_get(int unit, int port, pm_info_t pm_info, uint32 index, cprimod_encap_ordering_info_entry_t* config) 1900 { 1901 SOC_INIT_FUNC_DEFS; 1902 1903 _SOC_IF_ERR_EXIT 1904 (cprimod_encap_ordering_info_entry_get(unit, port, index, config)); 1905 1906 exit: 1907 SOC_FUNC_RETURN; 1908 1909 } 1910 1911 1912 1913 int cpm4x25_cpri_port_encap_roe_ordering_sequence_offset_set(int unit, int port, pm_info_t pm_info, 1914 uint32 queue_num, 1915 uint32 control, 1916 cprimod_cpri_ordering_info_offset_t* config) 1917 { 1918 SOC_INIT_FUNC_DEFS; 1919 1920 _SOC_IF_ERR_EXIT 1921 (cprimod_encap_ordering_info_sequence_offset_set(unit, port, queue_num, control, config)); 1922 1923 1924 exit: 1925 SOC_FUNC_RETURN; 1926 1927 } 1928 1929 int cpm4x25_cpri_port_encap_roe_ordering_sequence_offset_get(int unit, int port, pm_info_t pm_info, 1930 uint32 queue_num, 1931 uint32 control, 1932 cprimod_cpri_ordering_info_offset_t* config) 1933 { 1934 SOC_INIT_FUNC_DEFS; 1935 1936 _SOC_IF_ERR_EXIT 1937 (cprimod_encap_ordering_info_sequence_offset_get(unit, port, queue_num, control, 1938 config->p_size, config->q_size, config)); 1939 1940 1941 exit: 1942 SOC_FUNC_RETURN; 1943 1944 } 1945 1946 int cpm4x25_cpri_port_roe_encap_macda_entry_set(int unit, int port, pm_info_t pm_info, uint32 index, cprimod_mac_addr_t mac_addr) 1947 { 1948 SOC_INIT_FUNC_DEFS; 1949 1950 _SOC_IF_ERR_EXIT 1951 (cprimod_encap_mac_da_entry_set(unit, port, index, mac_addr)); 1952 exit: 1953 SOC_FUNC_RETURN; 1954 1955 } 1956 1957 int cpm4x25_cpri_port_roe_encap_macda_entry_get(int unit, int port, pm_info_t pm_info, uint32 index, cprimod_mac_addr_t mac_addr) 1958 { 1959 SOC_INIT_FUNC_DEFS; 1960 1961 _SOC_IF_ERR_EXIT 1962 (cprimod_encap_mac_da_entry_get(unit, port, index, mac_addr)); 1963 exit: 1964 SOC_FUNC_RETURN; 1965 1966 } 1967 1968 1969 int cpm4x25_cpri_port_roe_encap_macsa_entry_set(int unit, int port, pm_info_t pm_info, uint32 index, cprimod_mac_addr_t mac_addr) 1970 { 1971 SOC_INIT_FUNC_DEFS; 1972 1973 _SOC_IF_ERR_EXIT 1974 (cprimod_encap_mac_sa_entry_set(unit, port, index, mac_addr)); 1975 exit: 1976 SOC_FUNC_RETURN; 1977 1978 } 1979 1980 int cpm4x25_cpri_port_roe_encap_macsa_entry_get(int unit, int port, pm_info_t pm_info, uint32 index, cprimod_mac_addr_t mac_addr) 1981 { 1982 SOC_INIT_FUNC_DEFS; 1983 1984 _SOC_IF_ERR_EXIT 1985 (cprimod_encap_mac_sa_entry_get(unit, port, index, mac_addr)); 1986 exit: 1987 SOC_FUNC_RETURN; 1988 1989 } 1990 1991 int cpm4x25_cpri_port_roe_encap_vlan_entry_set(int unit, int port, pm_info_t pm_info, uint32 index, cprimod_vlan_table_id_t table_id, uint32 vlan_id) 1992 { 1993 SOC_INIT_FUNC_DEFS; 1994 1995 _SOC_IF_ERR_EXIT 1996 (cprimod_encap_vlan_id_entry_set(unit, port, table_id, index, vlan_id)); 1997 1998 exit: 1999 SOC_FUNC_RETURN; 2000 2001 } 2002 2003 int cpm4x25_cpri_port_roe_encap_vlan_entry_get(int unit, int port, pm_info_t pm_info, uint32 index, cprimod_vlan_table_id_t table_id, uint32* vlan_id) 2004 { 2005 SOC_INIT_FUNC_DEFS; 2006 2007 _SOC_IF_ERR_EXIT 2008 (cprimod_encap_vlan_id_entry_get(unit, port, table_id, index, vlan_id)); 2009 exit: 2010 SOC_FUNC_RETURN; 2011 2012 } 2013 2014 int cpm4x25_cpri_port_decap_ethertype_config_set(int unit, int port, pm_info_t pm_info, 2015 cprimod_ethertype_t pkt_type, 2016 uint16 ethertype) 2017 { 2018 SOC_INIT_FUNC_DEFS; 2019 2020 _SOC_IF_ERR_EXIT 2021 (cprimod_decap_ethertype_config_set(unit, port, pkt_type, ethertype)); 2022 2023 exit: 2024 SOC_FUNC_RETURN; 2025 2026 } 2027 2028 int cpm4x25_cpri_port_decap_ethertype_config_get(int unit, int port, pm_info_t pm_info, 2029 cprimod_ethertype_t pkt_type, 2030 uint16* ethertype) 2031 { 2032 SOC_INIT_FUNC_DEFS; 2033 2034 _SOC_IF_ERR_EXIT 2035 (cprimod_decap_ethertype_config_get(unit, port, pkt_type, ethertype)); 2036 2037 exit: 2038 SOC_FUNC_RETURN; 2039 2040 } 2041 2042 int cpm4x25_cpri_port_encap_ethertype_config_set(int unit, int port, pm_info_t pm_info, 2043 cprimod_ethertype_t pkt_type, 2044 uint16 ethertype) 2045 { 2046 SOC_INIT_FUNC_DEFS; 2047 2048 _SOC_IF_ERR_EXIT 2049 (cprimod_encap_ethertype_config_set(unit, port, pkt_type, ethertype)); 2050 2051 exit: 2052 SOC_FUNC_RETURN; 2053 2054 } 2055 2056 int cpm4x25_cpri_port_encap_ethertype_config_get(int unit, int port, pm_info_t pm_info, 2057 cprimod_ethertype_t pkt_type, 2058 uint16* ethertype) 2059 { 2060 SOC_INIT_FUNC_DEFS; 2061 2062 _SOC_IF_ERR_EXIT 2063 (cprimod_encap_ethertype_config_get(unit, port, pkt_type, ethertype)); 2064 2065 exit: 2066 SOC_FUNC_RETURN; 2067 2068 } 2069 2070 int cpm4x25_cpri_port_decap_flow_config_set(int unit, int port, pm_info_t pm_info, 2071 uint8 roe_subtype, 2072 uint32 queue_num, 2073 cprimod_cls_option_t cls_option, 2074 cprimod_cls_flow_type_t flow_type, 2075 uint32 ordering_info_index) 2076 { 2077 SOC_INIT_FUNC_DEFS; 2078 2079 _SOC_IF_ERR_EXIT 2080 (cprimod_decap_flow_classification_config_set(unit, port, roe_subtype, queue_num, cls_option, flow_type)); 2081 2082 2083 exit: 2084 SOC_FUNC_RETURN; 2085 2086 } 2087 2088 int cpm4x25_cpri_port_decap_flow_config_get(int unit, int port, pm_info_t pm_info, 2089 uint8 roe_subtype, 2090 uint32* queue_num, 2091 cprimod_cls_option_t* cls_option, 2092 cprimod_cls_flow_type_t* flow_type, 2093 uint32 ordering_info_index) 2094 { 2095 SOC_INIT_FUNC_DEFS; 2096 2097 _SOC_IF_ERR_EXIT 2098 (cprimod_decap_flow_classification_config_get(unit, port, roe_subtype, queue_num, cls_option, flow_type)); 2099 2100 2101 exit: 2102 SOC_FUNC_RETURN; 2103 2104 } 2105 2106 int cpm4x25_cpri_port_decap_queue_to_ordering_info_index_set(int unit, int port, pm_info_t pm_info, uint32 queue_num, uint32 ordering_info_index) 2107 { 2108 SOC_INIT_FUNC_DEFS; 2109 2110 _SOC_IF_ERR_EXIT 2111 (cprimod_decap_queue_to_ordering_info_index_mapping_set(unit, port, queue_num, ordering_info_index)); 2112 exit: 2113 SOC_FUNC_RETURN; 2114 2115 } 2116 2117 int cpm4x25_cpri_port_decap_queue_to_ordering_info_index_get(int unit, int port, pm_info_t pm_info, uint32 queue_num, uint32* ordering_info_index) 2118 { 2119 SOC_INIT_FUNC_DEFS; 2120 2121 _SOC_IF_ERR_EXIT 2122 (cprimod_decap_queue_to_ordering_info_index_mapping_get(unit, port, queue_num, ordering_info_index)); 2123 exit: 2124 SOC_FUNC_RETURN; 2125 2126 } 2127 2128 2129 int cpm4x25_cpri_port_decap_flow_to_queue_mapping_set(int unit, int port, pm_info_t pm_info, uint32 flow_id, uint32 queue_num) 2130 { 2131 SOC_INIT_FUNC_DEFS; 2132 2133 _SOC_IF_ERR_EXIT 2134 (cprimod_decap_flow_to_queue_mapping_set(unit, port, flow_id, queue_num)); 2135 exit: 2136 SOC_FUNC_RETURN; 2137 2138 } 2139 2140 int cpm4x25_cpri_port_decap_flow_to_queue_mapping_get(int unit, int port, pm_info_t pm_info, uint32 flow_id, uint32* queue_num) 2141 { 2142 SOC_INIT_FUNC_DEFS; 2143 2144 _SOC_IF_ERR_EXIT 2145 (cprimod_decap_flow_to_queue_mapping_get(unit, port, flow_id, queue_num)); 2146 exit: 2147 SOC_FUNC_RETURN; 2148 2149 } 2150 2151 int cpm4x25_cpri_port_decap_roe_ordering_info_set(int unit, int port, pm_info_t pm_info, uint32 index, cprimod_decap_ordering_info_entry_t* config) 2152 { 2153 SOC_INIT_FUNC_DEFS; 2154 2155 _SOC_IF_ERR_EXIT 2156 (cprimod_decap_ordering_info_entry_set(unit, port, index, config)); 2157 2158 exit: 2159 SOC_FUNC_RETURN; 2160 2161 } 2162 2163 int cpm4x25_cpri_port_decap_roe_ordering_info_get(int unit, int port, pm_info_t pm_info, uint32 index, cprimod_decap_ordering_info_entry_t* config) 2164 { 2165 SOC_INIT_FUNC_DEFS; 2166 2167 _SOC_IF_ERR_EXIT 2168 (cprimod_decap_ordering_info_entry_get(unit, port, index, config)); 2169 2170 exit: 2171 SOC_FUNC_RETURN; 2172 2173 } 2174 2175 2176 int cpm4x25_cpri_port_decap_roe_ordering_sequence_offset_set(int unit, int port, pm_info_t pm_info, uint32 queue_num, cprimod_cpri_ordering_info_offset_t* config) 2177 { 2178 SOC_INIT_FUNC_DEFS; 2179 2180 _SOC_IF_ERR_EXIT 2181 (cprimod_decap_ordering_info_sequence_offset_set(unit, port, queue_num, config)); 2182 2183 exit: 2184 SOC_FUNC_RETURN; 2185 2186 } 2187 2188 int cpm4x25_cpri_port_decap_roe_ordering_sequence_offset_get(int unit, int port, pm_info_t pm_info, uint32 queue_num, cprimod_cpri_ordering_info_offset_t* config) 2189 { 2190 SOC_INIT_FUNC_DEFS; 2191 2192 _SOC_IF_ERR_EXIT 2193 (cprimod_decap_ordering_info_sequence_offset_get(unit, port, queue_num, config->p_size, config->q_size, config)); 2194 exit: 2195 SOC_FUNC_RETURN; 2196 2197 } 2198 2199 int cpm4x25_cpri_port_tx_frame_tgen_config_set(int unit, int port, pm_info_t pm_info, portmod_tx_frame_tgen_config_t* config) 2200 { 2201 int val = 0; 2202 uint8 tgen_hfn = 0; 2203 uint16 tgen_bfn= 0; 2204 SOC_INIT_FUNC_DEFS; 2205 2206 2207 _SOC_IF_ERR_EXIT 2208 (cprimod_cpri_or_enet_port_get(unit, port, &val)); 2209 2210 if (val == 0) { 2211 _SOC_EXIT_WITH_ERR 2212 (SOC_E_UNAVAIL, ("Port is in Ethernet Mode.\n")); 2213 } 2214 2215 _SOC_IF_ERR_EXIT 2216 (cprimod_tx_framer_tgen_select_counter_set(unit, port, config->tx_gen_bfn_hfn_sel)); 2217 _SOC_IF_ERR_EXIT 2218 (cprimod_tx_framer_tgen_offset_set(unit, port, config->tx_tgen_ts_offset)); 2219 2220 tgen_hfn = config->tx_tgen_hfn; 2221 _SOC_IF_ERR_EXIT 2222 (cprimod_tx_framer_tgen_next_hfn_config_set(unit, port, tgen_hfn)); 2223 2224 tgen_bfn = config->tx_tgen_bfn; 2225 _SOC_IF_ERR_EXIT 2226 (cprimod_tx_framer_tgen_next_bfn_config_set(unit, port, tgen_bfn)); 2227 2228 exit: 2229 SOC_FUNC_RETURN; 2230 2231 } 2232 2233 int cpm4x25_cpri_port_tx_frame_tgen_config_get(int unit, int port, pm_info_t pm_info, portmod_tx_frame_tgen_config_t* config) 2234 { 2235 uint32 tgen_hfn = 0; 2236 uint32 tgen_bfn= 0; 2237 SOC_INIT_FUNC_DEFS; 2238 2239 _SOC_IF_ERR_EXIT 2240 (cprimod_tx_framer_tgen_select_counter_get(unit, port, &config->tx_gen_bfn_hfn_sel)); 2241 _SOC_IF_ERR_EXIT 2242 (cprimod_tx_framer_tgen_offset_get(unit, port, &config->tx_tgen_ts_offset)); 2243 2244 tgen_hfn = config->tx_tgen_hfn; 2245 _SOC_IF_ERR_EXIT 2246 (cprimod_tx_framer_tgen_next_hfn_config_get(unit, port, &tgen_hfn)); 2247 config->tx_tgen_hfn = tgen_hfn; 2248 2249 _SOC_IF_ERR_EXIT 2250 (cprimod_tx_framer_tgen_next_bfn_config_get(unit, port, &tgen_bfn)); 2251 config->tx_tgen_bfn = tgen_bfn; 2252 2253 exit: 2254 SOC_FUNC_RETURN; 2255 2256 } 2257 2258 2259 int cpm4x25_cpri_port_tx_frame_tgen_enable(int unit, int port, pm_info_t pm_info, uint32 enable) 2260 { 2261 SOC_INIT_FUNC_DEFS; 2262 2263 _SOC_IF_ERR_EXIT 2264 (cprimod_tx_framer_tgen_enable(unit, port, enable)); 2265 2266 exit: 2267 SOC_FUNC_RETURN; 2268 } 2269 2270 int cpm4x25_cpri_port_tx_frame_tgen_ts_offset_set(int unit, int port, pm_info_t pm_info, uint64 offset) 2271 { 2272 SOC_INIT_FUNC_DEFS; 2273 2274 _SOC_IF_ERR_EXIT 2275 (cprimod_tx_framer_tgen_offset_set(unit, port, offset)); 2276 exit: 2277 SOC_FUNC_RETURN; 2278 2279 } 2280 2281 int cpm4x25_cpri_port_tx_frame_tgen_ts_offset_get(int unit, int port, pm_info_t pm_info, uint64* offset) 2282 { 2283 SOC_INIT_FUNC_DEFS; 2284 2285 _SOC_IF_ERR_EXIT 2286 (cprimod_tx_framer_tgen_offset_get(unit, port, offset)); 2287 exit: 2288 SOC_FUNC_RETURN; 2289 2290 } 2291 2292 int cpm4x25_cpri_port_tx_frame_next_hfn_get(int unit, int port, pm_info_t pm_info, uint32* hfn) 2293 { 2294 SOC_INIT_FUNC_DEFS; 2295 2296 _SOC_IF_ERR_EXIT 2297 (cprimod_tx_framer_next_hfn_get(unit, port, hfn)); 2298 2299 exit: 2300 SOC_FUNC_RETURN; 2301 2302 } 2303 2304 2305 int cpm4x25_cpri_port_tx_frame_next_bfn_get(int unit, int port, pm_info_t pm_info, uint32* bfn) 2306 { 2307 SOC_INIT_FUNC_DEFS; 2308 2309 _SOC_IF_ERR_EXIT 2310 (cprimod_tx_framer_next_bfn_get(unit, port, bfn)); 2311 exit: 2312 SOC_FUNC_RETURN; 2313 2314 } 2315 2316 int cpm4x25_cpri_port_rsvd4_rx_flow_add(int unit, int port, pm_info_t pm_info, 2317 uint32 flow_id, 2318 portmod_rsvd4_rx_flow_info_t* info) 2319 { 2320 cprimod_header_compare_entry_t compare_entry; 2321 cprimod_rsvd4_container_config_t container_info; 2322 cprimod_rsvd4_encap_data_config_t encap_data_info; 2323 cprimod_payload_size_info_t payload_info; 2324 uint32 queue_num=0; 2325 2326 SOC_INIT_FUNC_DEFS; 2327 2328 cprimod_rsvd4_container_config_t_init(&container_info); 2329 container_info.axc_id = info->axc_id; 2330 container_info.stuffing_cnt = info->stuffing_cnt; 2331 container_info.msg_ts_mode = info->msg_ts_mode; 2332 container_info.msg_ts_cnt = info->msg_ts_count; 2333 container_info.frame_sync_mode = info->frame_sync_mode; 2334 container_info.master_frame_offset = info->master_frame_offset; 2335 container_info.message_number_offset = info->message_number_offset; 2336 container_info.container_block_cnt = info->container_block_count; 2337 2338 _SOC_IF_ERR_EXIT 2339 (cprimod_rsvd4_rx_axc_container_config_set(unit, port, flow_id, &container_info)); 2340 2341 cprimod_payload_size_info_t_init(&payload_info); 2342 payload_info.packet_size = info->packet_size ; 2343 payload_info.last_packet_num = info->last_packet_num ; 2344 payload_info.last_packet_size = info->last_packet_size ; 2345 2346 _SOC_IF_ERR_EXIT 2347 (cprimod_rx_roe_payload_size_set(unit, port, container_info.axc_id, &payload_info)); 2348 2349 /* 2350 * Queue number is AxC_ID for data flow. 2351 */ 2352 queue_num = container_info.axc_id; 2353 2354 cprimod_rsvd4_encap_data_config_t_init(&encap_data_info); 2355 2356 encap_data_info.buffer_size = info->queue_size; 2357 encap_data_info.priority = info->priority ; 2358 encap_data_info.gsm_pad_size = info->pad_size; 2359 encap_data_info.gsm_extra_pad_size = info->extra_pad_size ; 2360 encap_data_info.gsm_pad_enable = info->pad_enable ; 2361 encap_data_info.gsm_control_location = info->control_location ; 2362 encap_data_info.bit_reversal = 1; 2363 2364 _SOC_IF_ERR_EXIT 2365 (cprimod_rsvd4_encap_data_config_set(unit, port, queue_num, &encap_data_info)); 2366 2367 _SOC_IF_ERR_EXIT 2368 (cprimod_rx_rsvd4_gsm_tsn_bitmap_set(unit, port, queue_num, info->tsn_bitmap)); 2369 2370 cprimod_header_compare_entry_t_init(&compare_entry); 2371 compare_entry.valid = 1; 2372 compare_entry.mask = info->mask; 2373 compare_entry.match_data = info->match_data; 2374 compare_entry.flow_id = flow_id; 2375 compare_entry.flow_type = cprimodFlowTypeData; 2376 2377 _SOC_IF_ERR_EXIT 2378 (cprimod_header_compare_entry_add(unit, port, &compare_entry)); 2379 exit: 2380 SOC_FUNC_RETURN; 2381 2382 } 2383 2384 int cpm4x25_cpri_port_rsvd4_rx_flow_delete(int unit, int port, pm_info_t pm_info, uint32 flow_id) 2385 { 2386 cprimod_rsvd4_container_config_t container_config; 2387 cprimod_encap_decap_data_config_t encap_data_config; 2388 cprimod_payload_size_info_t roe_payload_info; 2389 uint32 queue_num; 2390 2391 SOC_INIT_FUNC_DEFS; 2392 2393 _SOC_IF_ERR_EXIT 2394 (cprimod_header_compare_entry_for_flow_delete(unit, port, flow_id, cprimodFlowTypeData)); 2395 2396 _SOC_IF_ERR_EXIT 2397 (cprimod_rsvd4_rx_axc_container_config_get(unit, port, flow_id, &container_config)); 2398 2399 queue_num = container_config.axc_id; 2400 2401 /* Flush encap memory and framer state. */ 2402 _SOC_IF_ERR_EXIT 2403 (cprimod_encap_memory_clear(unit, port, queue_num)); 2404 2405 _SOC_IF_ERR_EXIT 2406 (cprimod_cpri_rx_framer_state_clear(unit, port, flow_id)); 2407 2408 /* clear the relate container parser entry. */ 2409 _SOC_IF_ERR_EXIT 2410 (cprimod_rsvd4_container_config_t_init(&container_config)); 2411 2412 _SOC_IF_ERR_EXIT 2413 (cprimod_rsvd4_rx_axc_container_config_set(unit, port, flow_id, &container_config)); 2414 2415 /* clear encap data configuration. */ 2416 _SOC_IF_ERR_EXIT 2417 (cprimod_encap_decap_data_config_t_init(&encap_data_config)); 2418 2419 /* Need to set agnostic_mode to 1 not to run thru allocation */ 2420 encap_data_config.is_agnostic = 1; 2421 2422 _SOC_IF_ERR_EXIT 2423 (cprimod_cpri_encap_data_config_set(unit, port, queue_num, &encap_data_config )); 2424 2425 /* clear payload info. */ 2426 _SOC_IF_ERR_EXIT 2427 (cprimod_payload_size_info_t_init(&roe_payload_info)); 2428 2429 _SOC_IF_ERR_EXIT 2430 (cprimod_rx_roe_payload_size_set(unit, port, queue_num, &roe_payload_info)); 2431 2432 exit: 2433 SOC_FUNC_RETURN; 2434 2435 } 2436 2437 2438 int cpm4x25_cpri_port_rsvd4_tx_flow_add(int unit, int port, pm_info_t pm_info, uint32 flow_id, portmod_rsvd4_tx_flow_info_t* info) 2439 { 2440 cprimod_rsvd4_container_config_t container_info; 2441 cprimod_payload_size_info_t payload_info; 2442 cprimod_rsvd4_decap_data_config_t decap_data_info; 2443 uint32 queue_num; 2444 2445 SOC_INIT_FUNC_DEFS; 2446 2447 cprimod_rsvd4_container_config_t_init(&container_info); 2448 container_info.axc_id = info->axc_id; 2449 container_info.stuffing_cnt = info->stuffing_cnt ; 2450 container_info.msg_ts_mode = info->msg_ts_mode ; 2451 container_info.msg_ts_cnt = info->msg_ts_count ; 2452 container_info.frame_sync_mode = info->frame_sync_mode ; 2453 container_info.master_frame_offset = info->master_frame_offset ; 2454 container_info.message_number_offset = info->message_number_offset ; 2455 container_info.container_block_cnt = info->container_block_count ; 2456 container_info.use_ts_dbm = info->use_ts_dbm ; 2457 container_info.ts_dbm_prof_num = info->ts_dbm_profile_num ; 2458 container_info.num_active_slots = info->num_active_slot ; 2459 container_info.msg_addr = info->msg_addr ; 2460 container_info.msg_type = info->msg_type ; 2461 container_info.msg_ts_offset = info->msg_ts_offset ; 2462 _SOC_IF_ERR_EXIT 2463 (cprimod_rsvd4_tx_axc_container_config_set(unit, port, flow_id , &container_info)); 2464 2465 cprimod_payload_size_info_t_init(&payload_info); 2466 payload_info.packet_size = info->packet_size ; 2467 payload_info.last_packet_num = info->last_packet_num ; 2468 payload_info.last_packet_size = info->last_packet_size ; 2469 _SOC_IF_ERR_EXIT 2470 (cprimod_tx_roe_payload_size_set(unit, port, container_info.axc_id, &payload_info)); 2471 2472 /* 2473 * Queue number is AxC_ID. 2474 */ 2475 queue_num = container_info.axc_id; 2476 2477 cprimod_rsvd4_decap_data_config_t_init(&decap_data_info); 2478 decap_data_info.buffer_size = info->buffer_size ; 2479 decap_data_info.cycle_size = info->cycle_size ; 2480 decap_data_info.gsm_pad_size = info->pad_size ; 2481 decap_data_info.gsm_extra_pad_size = info->extra_pad_size ; 2482 decap_data_info.gsm_pad_enable = info->pad_enable ; 2483 decap_data_info.gsm_control_location = info->control_location ; 2484 decap_data_info.bit_reversal = 1; 2485 2486 _SOC_IF_ERR_EXIT 2487 (cprimod_rsvd4_decap_data_config_set(unit, port, queue_num, &decap_data_info)); 2488 2489 exit: 2490 SOC_FUNC_RETURN; 2491 2492 } 2493 2494 int cpm4x25_cpri_port_rsvd4_tx_flow_delete(int unit, int port, pm_info_t pm_info, uint32 flow_id) 2495 { 2496 uint32 queue_num; 2497 cprimod_rsvd4_container_config_t container_config; 2498 cprimod_rsvd4_decap_data_config_t decap_data_config; 2499 cprimod_payload_size_info_t roe_payload_info; 2500 SOC_INIT_FUNC_DEFS; 2501 2502 2503 _SOC_IF_ERR_EXIT 2504 (cprimod_rsvd4_tx_axc_container_config_get(unit, port, flow_id, &container_config)); 2505 2506 queue_num = container_config.axc_id; 2507 2508 /* Flush decap memory and framer state. */ 2509 _SOC_IF_ERR_EXIT 2510 (cprimod_decap_memory_clear(unit, port, queue_num)); 2511 2512 _SOC_IF_ERR_EXIT 2513 (cprimod_cpri_tx_framer_state_clear(unit, port, flow_id)); 2514 2515 /* clear the relate container parser entry. */ 2516 _SOC_IF_ERR_EXIT 2517 (cprimod_rsvd4_container_config_t_init(&container_config)); 2518 2519 _SOC_IF_ERR_EXIT 2520 (cprimod_rsvd4_tx_axc_container_config_set(unit, port, flow_id, &container_config)); 2521 2522 /* clear encap data configuration. */ 2523 _SOC_IF_ERR_EXIT 2524 (cprimod_rsvd4_decap_data_config_t_init(&decap_data_config)); 2525 2526 _SOC_IF_ERR_EXIT 2527 (cprimod_rsvd4_decap_data_config_set(unit, port, queue_num, &decap_data_config )); 2528 2529 /* clear payload info. */ 2530 _SOC_IF_ERR_EXIT 2531 (cprimod_payload_size_info_t_init(&roe_payload_info)); 2532 2533 _SOC_IF_ERR_EXIT 2534 (cprimod_tx_roe_payload_size_set(unit, port, queue_num, &roe_payload_info)); 2535 exit: 2536 SOC_FUNC_RETURN; 2537 2538 } 2539 2540 int cpm4x25_cpri_port_rsvd4_dbm_entry_set(int unit, int port, pm_info_t pm_info, uint32 profile_id, cprimod_dbm_rule_entry_t* profile) 2541 { 2542 SOC_INIT_FUNC_DEFS; 2543 2544 _SOC_IF_ERR_EXIT 2545 (cprimod_dual_bitmap_rule_entry_set(unit, port, profile_id, profile)); 2546 exit: 2547 SOC_FUNC_RETURN; 2548 2549 } 2550 2551 int cpm4x25_cpri_port_rsvd4_dbm_entry_get(int unit, int port, pm_info_t pm_info, uint32 profile_id, cprimod_dbm_rule_entry_t* profile) 2552 { 2553 SOC_INIT_FUNC_DEFS; 2554 2555 _SOC_IF_ERR_EXIT 2556 (cprimod_dual_bitmap_rule_entry_get(unit, port, profile_id, profile)); 2557 exit: 2558 SOC_FUNC_RETURN; 2559 2560 } 2561 2562 2563 int cpm4x25_cpri_port_rsvd4_secondary_dbm_entry_set(int unit, int port, pm_info_t pm_info, uint32 profile_id, cprimod_secondary_dbm_rule_entry_t* profile) 2564 { 2565 SOC_INIT_FUNC_DEFS; 2566 2567 _SOC_IF_ERR_EXIT 2568 (cprimod_secondary_dual_bitmap_rule_entry_set(unit, port, profile_id, profile)); 2569 2570 exit: 2571 SOC_FUNC_RETURN; 2572 2573 } 2574 2575 int cpm4x25_cpri_port_rsvd4_secondary_dbm_entry_get(int unit, int port, pm_info_t pm_info, uint32 profile_id, cprimod_secondary_dbm_rule_entry_t* profile) 2576 { 2577 SOC_INIT_FUNC_DEFS; 2578 2579 _SOC_IF_ERR_EXIT 2580 (cprimod_secondary_dual_bitmap_rule_entry_get(unit, port, profile_id, profile)); 2581 2582 exit: 2583 SOC_FUNC_RETURN; 2584 2585 } 2586 2587 int cpm4x25_cpri_port_rsvd4_modulo_rule_entry_set(int unit, int port, pm_info_t pm_info, 2588 uint32 modulo_rule_num, 2589 cprimod_transmission_rule_type_t modulo_rule_type, 2590 const cprimod_modulo_rule_entry_t* modulo_rule) 2591 { 2592 SOC_INIT_FUNC_DEFS; 2593 2594 _SOC_IF_ERR_EXIT 2595 (cprimod_modulo_rule_entry_set(unit, port, modulo_rule_num, modulo_rule_type, modulo_rule)); 2596 2597 exit: 2598 SOC_FUNC_RETURN; 2599 2600 } 2601 2602 int cpm4x25_cpri_port_rsvd4_modulo_rule_entry_get(int unit, int port, pm_info_t pm_info, 2603 uint32 modulo_rule_num, 2604 cprimod_transmission_rule_type_t modulo_rule_type, 2605 cprimod_modulo_rule_entry_t* modulo_rule) 2606 { 2607 SOC_INIT_FUNC_DEFS; 2608 2609 _SOC_IF_ERR_EXIT 2610 (cprimod_modulo_rule_entry_get(unit, port, modulo_rule_num, modulo_rule_type, modulo_rule)); 2611 2612 exit: 2613 SOC_FUNC_RETURN; 2614 2615 } 2616 2617 2618 int cpm4x25_cpri_port_rsvd4_dbm_position_entry_set(int unit, int port, pm_info_t pm_info, 2619 uint32 index, 2620 cprimod_dbm_pos_table_entry_t* pos_entry) 2621 { 2622 SOC_INIT_FUNC_DEFS; 2623 2624 _SOC_IF_ERR_EXIT 2625 (cprimod_dbm_position_entry_set(unit, port, index, pos_entry)); 2626 2627 exit: 2628 SOC_FUNC_RETURN; 2629 2630 } 2631 2632 int cpm4x25_cpri_port_rsvd4_dbm_position_entry_get(int unit, int port, pm_info_t pm_info, 2633 uint32 index, 2634 cprimod_dbm_pos_table_entry_t* pos_entry) 2635 { 2636 SOC_INIT_FUNC_DEFS; 2637 2638 _SOC_IF_ERR_EXIT 2639 (cprimod_dbm_position_entry_get(unit, port, index, pos_entry)); 2640 2641 exit: 2642 SOC_FUNC_RETURN; 2643 2644 } 2645 2646 int cpm4x25_cpri_port_rsvd4_rx_master_frame_sync_config_set(int unit, int port, pm_info_t pm_info, uint32 master_frame_number, uint64 master_frame_start_time) 2647 { 2648 SOC_INIT_FUNC_DEFS; 2649 2650 _SOC_IF_ERR_EXIT 2651 (cprimod_rsvd4_rx_master_frame_sync_config_set(unit, port, master_frame_number, master_frame_start_time)); 2652 2653 exit: 2654 SOC_FUNC_RETURN; 2655 2656 } 2657 2658 int cpm4x25_cpri_port_rsvd4_rx_master_frame_sync_config_get(int unit, int port, pm_info_t pm_info, uint32* master_frame_number, uint64* master_frame_start_time) 2659 { 2660 SOC_INIT_FUNC_DEFS; 2661 2662 _SOC_IF_ERR_EXIT 2663 (cprimod_rsvd4_rx_master_frame_sync_config_get(unit, port, master_frame_number, master_frame_start_time)); 2664 exit: 2665 SOC_FUNC_RETURN; 2666 } 2667 2668 /* 2669 * Control Word Processing. 2670 */ 2671 2672 int cpm4x25_cpri_port_rx_cw_sync_info_get(int unit, int port, pm_info_t pm_info, uint32* hyper_frame_num, uint32* radio_frame_num) 2673 { 2674 2675 SOC_INIT_FUNC_DEFS; 2676 _SOC_IF_ERR_EXIT 2677 (cprimod_cpri_rx_control_word_sync_info_get(unit, port, hyper_frame_num, radio_frame_num)); 2678 exit: 2679 SOC_FUNC_RETURN; 2680 } 2681 2682 int cpm4x25_cpri_port_rx_cw_l1_signal_info_get(int unit, int port, pm_info_t pm_info, portmod_cpri_cw_l1_protocol_info_t* l1_info) 2683 { 2684 SOC_INIT_FUNC_DEFS; 2685 2686 _SOC_IF_ERR_EXIT 2687 (cprimod_cpri_rx_control_word_l1_signal_info_get(unit, port, l1_info)); 2688 exit: 2689 SOC_FUNC_RETURN; 2690 } 2691 2692 int cpm4x25_cpri_port_rx_cw_l1_signal_signal_protection_set(int unit, int port, pm_info_t pm_info, uint32 signal_map, uint32 enable) 2693 { 2694 SOC_INIT_FUNC_DEFS; 2695 _SOC_IF_ERR_EXIT 2696 (cprimod_cpri_rx_control_word_l1_signal_signal_protection_set(unit, port, signal_map,enable)); 2697 exit: 2698 SOC_FUNC_RETURN; 2699 2700 } 2701 2702 int cpm4x25_cpri_port_rx_cw_l1_signal_signal_protection_get(int unit, int port, pm_info_t pm_info, uint32 signal_map, uint32* enable) 2703 { 2704 SOC_INIT_FUNC_DEFS; 2705 _SOC_IF_ERR_EXIT 2706 (cprimod_cpri_rx_control_word_l1_signal_signal_protection_get(unit, port, signal_map,enable)); 2707 exit: 2708 SOC_FUNC_RETURN; 2709 2710 } 2711 2712 int cpm4x25_cpri_port_cw_slow_hdlc_config_set(int unit, int port, pm_info_t pm_info, const portmod_cpri_slow_hdlc_config_info_t* config_info) 2713 { 2714 cprimod_slow_hdlc_config_info_t hdlc_config; 2715 cprimod_encap_decap_data_config_t encap_decap_data; 2716 2717 SOC_INIT_FUNC_DEFS; 2718 2719 encap_decap_data.sample_size = 16; 2720 encap_decap_data.truncation_enable = FALSE; 2721 encap_decap_data.truncation_type = 0; 2722 encap_decap_data.compression_type = cprimod_no_compress; 2723 encap_decap_data.mux_enable = 0; 2724 encap_decap_data.bit_reversal = FALSE; 2725 encap_decap_data.buffer_size = config_info->queue_size; 2726 encap_decap_data.priority = config_info->priority; 2727 encap_decap_data.cycle_size = config_info->cycle_size; 2728 encap_decap_data.is_agnostic = 0; 2729 2730 _SOC_IF_ERR_EXIT 2731 (cprimod_cpri_encap_data_config_set(unit, port, config_info->queue_num, &encap_decap_data)); 2732 2733 /* added 16 bytes to the buffer. 2734 * The extra space is required to store the RoE Header for Tx Framer 2735 */ 2736 encap_decap_data.buffer_size = config_info->buffer_size + 16; 2737 _SOC_IF_ERR_EXIT 2738 (cprimod_cpri_decap_data_config_set(unit, port, config_info->queue_num, &encap_decap_data)); 2739 2740 hdlc_config.tx_crc_mode = config_info->tx_crc_mode; 2741 hdlc_config.tx_flag_size = config_info->tx_flag_size; 2742 hdlc_config.crc_init_val = config_info->crc_init_val; 2743 hdlc_config.use_fe_mac = config_info->use_fe_mac; 2744 hdlc_config.crc_byte_swap = config_info->crc_byte_swap; 2745 hdlc_config.cw_sel = config_info->cw_sel; 2746 hdlc_config.cw_size = config_info->cw_size; 2747 hdlc_config.fcs_size = config_info->fcs_size; 2748 hdlc_config.runt_frame_drop = config_info->runt_frame_drop; 2749 hdlc_config.long_frame_drop = config_info->long_frame_drop ; 2750 hdlc_config.min_frame_size = config_info->min_frame_size; 2751 hdlc_config.max_frame_size = config_info->max_frame_size; 2752 hdlc_config.queue_num = config_info->queue_num ; 2753 2754 hdlc_config.tx_filling_flag_pattern = config_info->tx_filling_flag_pattern ; 2755 hdlc_config.no_fcs_err_check = config_info->no_fcs_err_check ; 2756 2757 _SOC_IF_ERR_EXIT 2758 (cprimod_cpri_port_cw_slow_hdlc_config_set(unit, port, &hdlc_config)); 2759 exit: 2760 SOC_FUNC_RETURN; 2761 } 2762 2763 int cpm4x25_cpri_port_cw_slow_hdlc_config_get(int unit, int port, pm_info_t pm_info, portmod_cpri_slow_hdlc_config_info_t* config_info) 2764 { 2765 cprimod_slow_hdlc_config_info_t hdlc_config; 2766 cprimod_encap_decap_data_config_t encap_decap_data; 2767 2768 SOC_INIT_FUNC_DEFS; 2769 2770 2771 _SOC_IF_ERR_EXIT 2772 (cprimod_cpri_port_cw_slow_hdlc_config_get(unit, port, &hdlc_config)); 2773 2774 2775 config_info->tx_crc_mode = hdlc_config.tx_crc_mode; 2776 config_info->tx_flag_size = hdlc_config.tx_flag_size; 2777 config_info->crc_init_val = hdlc_config.crc_init_val; 2778 config_info->use_fe_mac = hdlc_config.use_fe_mac; 2779 config_info->crc_byte_swap = hdlc_config.crc_byte_swap; 2780 config_info->cw_sel = hdlc_config.cw_sel; 2781 config_info->cw_size = hdlc_config.cw_size; 2782 config_info->fcs_size = hdlc_config.fcs_size; 2783 config_info->runt_frame_drop = hdlc_config.runt_frame_drop; 2784 config_info->long_frame_drop = hdlc_config.long_frame_drop; 2785 config_info->min_frame_size = hdlc_config.min_frame_size; 2786 config_info->max_frame_size = hdlc_config.max_frame_size; 2787 config_info->queue_num = hdlc_config.queue_num; 2788 2789 config_info->tx_filling_flag_pattern = hdlc_config.tx_filling_flag_pattern; 2790 config_info->no_fcs_err_check = hdlc_config.no_fcs_err_check; 2791 2792 _SOC_IF_ERR_EXIT 2793 (cprimod_cpri_encap_data_config_get(unit, port, config_info->queue_num, &encap_decap_data)); 2794 2795 config_info->queue_size = encap_decap_data.buffer_size; 2796 config_info->priority = encap_decap_data.priority; 2797 2798 _SOC_IF_ERR_EXIT 2799 (cprimod_cpri_decap_data_config_get(unit, port, config_info->queue_num, &encap_decap_data)); 2800 2801 config_info->cycle_size = encap_decap_data.cycle_size; 2802 config_info->buffer_size = encap_decap_data.buffer_size -16; 2803 2804 2805 2806 exit: 2807 SOC_FUNC_RETURN; 2808 2809 } 2810 2811 int cpm4x25_cpri_port_cw_fast_eth_config_set(int unit, int port, pm_info_t pm_info, const portmod_cpri_fast_eth_config_info_t* config_info) 2812 { 2813 cprimod_fast_eth_config_info_t eth_config; 2814 cprimod_encap_decap_data_config_t encap_decap_data; 2815 2816 SOC_INIT_FUNC_DEFS; 2817 2818 encap_decap_data.sample_size = 16; 2819 encap_decap_data.truncation_enable = FALSE; 2820 encap_decap_data.truncation_type = 0; 2821 encap_decap_data.compression_type = cprimod_no_compress; 2822 encap_decap_data.mux_enable = 0; 2823 encap_decap_data.bit_reversal = FALSE; 2824 encap_decap_data.buffer_size = config_info->queue_size; 2825 encap_decap_data.priority = config_info->priority; 2826 encap_decap_data.cycle_size = config_info->cycle_size; 2827 encap_decap_data.is_agnostic = 0; 2828 2829 _SOC_IF_ERR_EXIT 2830 (cprimod_cpri_encap_data_config_set(unit, port, config_info->queue_num, &encap_decap_data)); 2831 2832 /* added 16 bytes to the buffer. 2833 * The extra space is required to store the RoE Header for Tx Framer 2834 */ 2835 encap_decap_data.buffer_size = config_info->buffer_size + 16; 2836 _SOC_IF_ERR_EXIT 2837 (cprimod_cpri_decap_data_config_set(unit, port, config_info->queue_num, &encap_decap_data)); 2838 2839 eth_config.tx_crc_mode = config_info->tx_crc_mode; 2840 eth_config.schan_start = config_info->schan_start; 2841 eth_config.schan_size = config_info->schan_size; 2842 eth_config.cw_sel = config_info->cw_sel; 2843 eth_config.cw_size = config_info->cw_size; 2844 eth_config.min_packet_size = config_info->min_packet_size; 2845 eth_config.max_packet_size = config_info->max_packet_size; 2846 eth_config.min_packet_drop = config_info->min_packet_drop; 2847 eth_config.max_packet_drop = config_info->max_packet_drop; 2848 eth_config.strip_crc = config_info->strip_crc; 2849 eth_config.min_ipg = config_info->min_ipg; 2850 eth_config.queue_num = config_info->queue_num ; 2851 eth_config.no_fcs_err_check = config_info->no_fcs_err_check ; 2852 2853 _SOC_IF_ERR_EXIT 2854 (cprimod_cpri_port_cw_fast_eth_config_set(unit, port, ð_config)); 2855 exit: 2856 SOC_FUNC_RETURN; 2857 2858 } 2859 2860 int cpm4x25_cpri_port_cw_fast_eth_config_get(int unit, int port, pm_info_t pm_info, portmod_cpri_fast_eth_config_info_t* config_info) 2861 { 2862 2863 cprimod_fast_eth_config_info_t eth_config; 2864 cprimod_encap_decap_data_config_t encap_decap_data; 2865 2866 SOC_INIT_FUNC_DEFS; 2867 2868 _SOC_IF_ERR_EXIT 2869 (cprimod_cpri_port_cw_fast_eth_config_get(unit, port, ð_config)); 2870 2871 config_info->tx_crc_mode = eth_config.tx_crc_mode; 2872 config_info->schan_start = eth_config.schan_start; 2873 config_info->schan_size = eth_config.schan_size; 2874 config_info->cw_sel = eth_config.cw_sel; 2875 config_info->cw_size = eth_config.cw_size; 2876 config_info->min_packet_size = eth_config.min_packet_size; 2877 config_info->max_packet_size = eth_config.max_packet_size; 2878 config_info->min_packet_drop = eth_config.min_packet_drop; 2879 config_info->max_packet_drop = eth_config.max_packet_drop; 2880 config_info->strip_crc = eth_config.strip_crc; 2881 config_info->min_ipg = eth_config.min_ipg; 2882 config_info->queue_num = eth_config.queue_num; 2883 config_info->no_fcs_err_check = eth_config.no_fcs_err_check; 2884 2885 _SOC_IF_ERR_EXIT 2886 (cprimod_encap_decap_data_config_t_init(&encap_decap_data)); 2887 _SOC_IF_ERR_EXIT 2888 (cprimod_cpri_encap_data_config_get(unit, port, config_info->queue_num, &encap_decap_data)); 2889 2890 config_info->queue_size = encap_decap_data.buffer_size; 2891 config_info->priority = encap_decap_data.priority; 2892 2893 _SOC_IF_ERR_EXIT 2894 (cprimod_encap_decap_data_config_t_init(&encap_decap_data)); 2895 _SOC_IF_ERR_EXIT 2896 (cprimod_cpri_decap_data_config_get(unit, port, config_info->queue_num, &encap_decap_data)); 2897 2898 config_info->cycle_size = encap_decap_data.cycle_size; 2899 config_info->buffer_size = encap_decap_data.buffer_size -16; 2900 2901 exit: 2902 SOC_FUNC_RETURN; 2903 } 2904 2905 int cpm4x25_cpri_port_rx_vsd_config_set(int unit, int port, pm_info_t pm_info, const portmod_cpri_rx_vsd_config_info_t* config_info) 2906 { 2907 cprimod_cpri_rx_vsd_config_info_t vsd_config; 2908 cprimod_encap_decap_data_config_t encap_decap_data; 2909 2910 SOC_INIT_FUNC_DEFS; 2911 2912 encap_decap_data.sample_size = 16; 2913 encap_decap_data.truncation_enable = FALSE; 2914 encap_decap_data.truncation_type = 0; 2915 encap_decap_data.compression_type = cprimod_no_compress; 2916 encap_decap_data.mux_enable = 0; 2917 encap_decap_data.bit_reversal = FALSE; 2918 encap_decap_data.buffer_size = config_info->queue_size; 2919 encap_decap_data.priority = config_info->priority; 2920 encap_decap_data.cycle_size = 0; /* not used for encap */ 2921 encap_decap_data.is_agnostic = 0; 2922 2923 _SOC_IF_ERR_EXIT 2924 (cprimod_cpri_encap_data_config_set(unit, port, config_info->queue_num, &encap_decap_data)); 2925 2926 vsd_config.subchan_start = config_info->subchan_start ; 2927 vsd_config.subchan_size = config_info->subchan_size ; 2928 vsd_config.subchan_bytes = config_info->subchan_bytes ; 2929 vsd_config.subchan_steps = config_info->subchan_steps ; 2930 vsd_config.flow_bytes = config_info->flow_bytes ; 2931 vsd_config.queue_num = config_info->queue_num ; 2932 vsd_config.rsvd_sector_mask[0] = config_info->rsvd_sector_mask[0] ; 2933 vsd_config.rsvd_sector_mask[1] = config_info->rsvd_sector_mask[1] ; 2934 vsd_config.rsvd_sector_mask[2] = config_info->rsvd_sector_mask[2] ; 2935 vsd_config.rsvd_sector_mask[3] = config_info->rsvd_sector_mask[3] ; 2936 2937 _SOC_IF_ERR_EXIT 2938 (cprimod_cpri_port_rx_vsd_cw_config_set(unit, port, &vsd_config)); 2939 exit: 2940 SOC_FUNC_RETURN; 2941 2942 } 2943 2944 int cpm4x25_cpri_port_rx_vsd_config_get(int unit, int port, pm_info_t pm_info, portmod_cpri_rx_vsd_config_info_t* config_info) 2945 { 2946 cprimod_cpri_rx_vsd_config_info_t vsd_config; 2947 cprimod_encap_decap_data_config_t encap_decap_data; 2948 2949 SOC_INIT_FUNC_DEFS; 2950 2951 _SOC_IF_ERR_EXIT 2952 (cprimod_cpri_port_rx_vsd_cw_config_get(unit, port, &vsd_config)); 2953 2954 config_info->subchan_start = vsd_config.subchan_start; 2955 config_info->subchan_size = vsd_config.subchan_size; 2956 config_info->subchan_bytes = vsd_config.subchan_bytes; 2957 config_info->subchan_steps = vsd_config.subchan_steps; 2958 config_info->flow_bytes = vsd_config.flow_bytes; 2959 config_info->queue_num = vsd_config.queue_num; 2960 2961 config_info->rsvd_sector_mask[0] = vsd_config.rsvd_sector_mask[0]; 2962 config_info->rsvd_sector_mask[1] = vsd_config.rsvd_sector_mask[1]; 2963 config_info->rsvd_sector_mask[2] = vsd_config.rsvd_sector_mask[2]; 2964 config_info->rsvd_sector_mask[3] = vsd_config.rsvd_sector_mask[3]; 2965 2966 _SOC_IF_ERR_EXIT 2967 (cprimod_cpri_encap_data_config_get(unit, port, config_info->queue_num, &encap_decap_data)); 2968 config_info->queue_size = encap_decap_data.buffer_size; 2969 config_info->priority = encap_decap_data.priority; 2970 2971 exit: 2972 SOC_FUNC_RETURN; 2973 } 2974 2975 int cpm4x25_cpri_port_tx_vsd_config_set(int unit, int port, pm_info_t pm_info, const portmod_cpri_tx_vsd_config_info_t* config_info) 2976 { 2977 cprimod_cpri_tx_vsd_config_info_t vsd_config; 2978 cprimod_encap_decap_data_config_t encap_decap_data; 2979 2980 SOC_INIT_FUNC_DEFS; 2981 2982 encap_decap_data.sample_size = 16; 2983 encap_decap_data.truncation_enable = FALSE; 2984 encap_decap_data.truncation_type = 0; 2985 encap_decap_data.compression_type = cprimod_no_compress; 2986 encap_decap_data.mux_enable = 0; 2987 encap_decap_data.bit_reversal = FALSE; 2988 encap_decap_data.cycle_size = config_info->cycle_size; 2989 encap_decap_data.priority = 0; /* not used for decap */ 2990 encap_decap_data.is_agnostic = 0; 2991 2992 /* added 16 bytes to the buffer. 2993 * The extra space is required to store the RoE Header for Tx Framer 2994 */ 2995 encap_decap_data.buffer_size = config_info->buffer_size + 16; 2996 2997 _SOC_IF_ERR_EXIT 2998 (cprimod_cpri_decap_data_config_set(unit, port, config_info->queue_num, &encap_decap_data)); 2999 3000 vsd_config.subchan_start = config_info->subchan_start ; 3001 vsd_config.subchan_size = config_info->subchan_size ; 3002 vsd_config.subchan_bytes = config_info->subchan_bytes ; 3003 vsd_config.subchan_steps = config_info->subchan_steps ; 3004 vsd_config.flow_bytes = config_info->flow_bytes ; 3005 vsd_config.queue_num = config_info->queue_num ; 3006 3007 vsd_config.byte_order_swap = config_info->byte_order_swap; 3008 vsd_config.rsvd_sector_mask[0] = config_info->rsvd_sector_mask[0] ; 3009 vsd_config.rsvd_sector_mask[1] = config_info->rsvd_sector_mask[1] ; 3010 vsd_config.rsvd_sector_mask[2] = config_info->rsvd_sector_mask[2] ; 3011 vsd_config.rsvd_sector_mask[3] = config_info->rsvd_sector_mask[3] ; 3012 3013 _SOC_IF_ERR_EXIT 3014 (cprimod_cpri_port_tx_vsd_cw_config_set(unit, port, &vsd_config)); 3015 3016 exit: 3017 SOC_FUNC_RETURN; 3018 3019 } 3020 3021 int cpm4x25_cpri_port_tx_vsd_config_get(int unit, int port, pm_info_t pm_info, portmod_cpri_tx_vsd_config_info_t* config_info) 3022 { 3023 cprimod_cpri_tx_vsd_config_info_t vsd_config; 3024 cprimod_encap_decap_data_config_t encap_decap_data; 3025 3026 SOC_INIT_FUNC_DEFS; 3027 3028 _SOC_IF_ERR_EXIT 3029 (cprimod_cpri_port_tx_vsd_cw_config_get(unit, port, &vsd_config)); 3030 3031 config_info->subchan_start = vsd_config.subchan_start; 3032 config_info->subchan_size = vsd_config.subchan_size; 3033 config_info->subchan_bytes = vsd_config.subchan_bytes; 3034 config_info->subchan_steps = vsd_config.subchan_steps; 3035 config_info->flow_bytes = vsd_config.flow_bytes; 3036 config_info->queue_num = vsd_config.queue_num; 3037 config_info->byte_order_swap = vsd_config.byte_order_swap; 3038 config_info->rsvd_sector_mask[0] = vsd_config.rsvd_sector_mask[0]; 3039 config_info->rsvd_sector_mask[1] = vsd_config.rsvd_sector_mask[1]; 3040 config_info->rsvd_sector_mask[2] = vsd_config.rsvd_sector_mask[2]; 3041 config_info->rsvd_sector_mask[3] = vsd_config.rsvd_sector_mask[3]; 3042 3043 _SOC_IF_ERR_EXIT 3044 (cprimod_cpri_decap_data_config_get(unit, port, config_info->queue_num, &encap_decap_data)); 3045 3046 config_info->cycle_size = encap_decap_data.cycle_size; 3047 config_info->buffer_size = encap_decap_data.buffer_size-16; 3048 3049 3050 exit: 3051 SOC_FUNC_RETURN; 3052 3053 } 3054 3055 int cpm4x25_cpri_port_rx_vsd_flow_add(int unit, int port, pm_info_t pm_info, uint32 group_id, const portmod_cpri_rx_vsd_flow_info_t* flow_info) 3056 { 3057 SOC_INIT_FUNC_DEFS; 3058 3059 _SOC_IF_ERR_EXIT 3060 (cprimod_cpri_port_rx_vsd_ctrl_flow_add(unit, port, group_id, flow_info)); 3061 3062 exit: 3063 SOC_FUNC_RETURN; 3064 } 3065 3066 int cpm4x25_cpri_port_rx_vsd_flow_delete(int unit, int port, pm_info_t pm_info, uint32 group_id) 3067 { 3068 SOC_INIT_FUNC_DEFS; 3069 3070 _SOC_IF_ERR_EXIT 3071 (cprimod_cpri_port_rx_vsd_ctrl_flow_delete(unit, port, group_id)); 3072 3073 3074 exit: 3075 SOC_FUNC_RETURN; 3076 3077 } 3078 3079 3080 int cpm4x25_cpri_port_rx_vsd_flow_get(int unit, int port, pm_info_t pm_info, uint32 group_id, portmod_cpri_rx_vsd_flow_info_t* flow_info) 3081 { 3082 SOC_INIT_FUNC_DEFS; 3083 3084 sal_memset(flow_info, 0, sizeof(portmod_cpri_rx_vsd_flow_info_t)); 3085 3086 _SOC_IF_ERR_EXIT 3087 (cprimod_cpri_port_rx_vsd_ctrl_flow_get(unit, port, group_id, flow_info)); 3088 3089 exit: 3090 SOC_FUNC_RETURN; 3091 3092 } 3093 3094 3095 3096 STATIC 3097 int _cpm4x25_port_index_get(int unit, int port, pm_info_t pm_info, 3098 int *first_index, uint32 *bitmap) 3099 { 3100 int i, rv = 0, tmp_port = 0; 3101 3102 SOC_INIT_FUNC_DEFS; 3103 3104 *first_index = -1; 3105 *bitmap = 0; 3106 3107 for( i = 0 ; i < MAX_PORTS_PER_PM4X25; i++){ 3108 rv = CPM4x25_LANE2PORT_GET(unit, pm_info, i, &tmp_port); 3109 _SOC_IF_ERR_EXIT(rv); 3110 3111 if(tmp_port == port){ 3112 *first_index = (*first_index == -1 ? i : *first_index); 3113 *bitmap |= 0x00000001 << i; 3114 } 3115 } 3116 3117 if(*first_index == -1) { 3118 _SOC_EXIT_WITH_ERR(SOC_E_INTERNAL, 3119 (_SOC_MSG("port was not found in internal DB %d"), port)); 3120 } 3121 3122 exit: 3123 SOC_FUNC_RETURN; 3124 } 3125 3126 3127 int cpm4x25_cpri_port_tx_vsd_flow_add(int unit, int port, pm_info_t pm_info, uint32 group_id, const portmod_cpri_tx_vsd_flow_info_t* flow_info) 3128 { 3129 int lane_index; 3130 uint32 lane_map; 3131 uint32 group_list[NUM_VSD_ACTIVE_GROUP_WORD]; 3132 SOC_INIT_FUNC_DEFS; 3133 3134 _SOC_IF_ERR_EXIT 3135 (_cpm4x25_port_index_get(unit, port, pm_info, &lane_index, &lane_map)); 3136 3137 CPM4x25_CPRI_PORT_VSD_ACTIVE_GROUP_GET(unit, pm_info, group_list, lane_index); 3138 3139 _SOC_IF_ERR_EXIT 3140 (cprimod_cpri_port_tx_vsd_ctrl_flow_add(unit, port, group_id, group_list, flow_info)); 3141 3142 _SOC_IF_ERR_EXIT 3143 (CPM4x25_CPRI_PORT_VSD_ACTIVE_GROUP_SET(unit, pm_info, group_list, lane_index)); 3144 exit: 3145 SOC_FUNC_RETURN; 3146 3147 } 3148 3149 int cpm4x25_cpri_port_tx_vsd_flow_delete(int unit, int port, pm_info_t pm_info, uint32 group_id) 3150 { 3151 int lane_index; 3152 uint32 lane_map; 3153 uint32 group_list[NUM_VSD_ACTIVE_GROUP_WORD]; 3154 SOC_INIT_FUNC_DEFS; 3155 3156 _SOC_IF_ERR_EXIT 3157 (_cpm4x25_port_index_get(unit, port, pm_info, &lane_index, &lane_map)); 3158 3159 CPM4x25_CPRI_PORT_VSD_ACTIVE_GROUP_GET(unit, pm_info, group_list, lane_index); 3160 3161 _SOC_IF_ERR_EXIT 3162 (cprimod_cpri_port_tx_vsd_ctrl_flow_delete(unit, port, group_id, group_list)); 3163 3164 _SOC_IF_ERR_EXIT 3165 (CPM4x25_CPRI_PORT_VSD_ACTIVE_GROUP_SET(unit, pm_info, group_list, lane_index)); 3166 3167 exit: 3168 SOC_FUNC_RETURN; 3169 3170 } 3171 3172 int cpm4x25_cpri_port_tx_vsd_flow_get(int unit, int port, pm_info_t pm_info, uint32 group_id, portmod_cpri_tx_vsd_flow_info_t* flow_info) 3173 { 3174 int lane_index; 3175 uint32 lane_map; 3176 uint32 group_list[NUM_VSD_ACTIVE_GROUP_WORD]; 3177 SOC_INIT_FUNC_DEFS; 3178 3179 sal_memset(flow_info, 0, sizeof(portmod_cpri_tx_vsd_flow_info_t)); 3180 3181 _SOC_IF_ERR_EXIT 3182 (_cpm4x25_port_index_get(unit, port, pm_info, &lane_index, &lane_map)); 3183 3184 _SOC_IF_ERR_EXIT 3185 (CPM4x25_CPRI_PORT_VSD_ACTIVE_GROUP_GET(unit, pm_info, group_list, lane_index)); 3186 _SOC_IF_ERR_EXIT 3187 (cprimod_cpri_port_tx_vsd_ctrl_flow_get(unit, port, group_id, group_list, flow_info)); 3188 3189 exit: 3190 SOC_FUNC_RETURN; 3191 3192 } 3193 3194 int cpm4x25_cpri_port_encap_queue_control_tag_to_flow_map_set(int unit, int port, pm_info_t pm_info, uint32 tag_id, uint32 flow_id) 3195 { 3196 SOC_INIT_FUNC_DEFS; 3197 3198 _SOC_IF_ERR_EXIT 3199 (cprimod_encap_control_queue_tag_to_flow_id_map_set(unit, port, tag_id, flow_id)); 3200 exit: 3201 SOC_FUNC_RETURN; 3202 } 3203 3204 int cpm4x25_cpri_port_encap_queue_control_tag_to_flow_map_get(int unit, int port, pm_info_t pm_info, uint32 tag_id, uint32* flow_id) 3205 { 3206 SOC_INIT_FUNC_DEFS; 3207 3208 _SOC_IF_ERR_EXIT 3209 (cprimod_encap_control_queue_tag_to_flow_id_map_get(unit, port, tag_id, flow_id)); 3210 exit: 3211 SOC_FUNC_RETURN; 3212 } 3213 3214 int cpm4x25_cpri_port_rx_vsd_raw_config_set(int unit, int port, pm_info_t pm_info, uint32 index, const portmod_cpri_rx_vsd_raw_config_t* config_info) 3215 { 3216 cprimod_cpri_rx_vsd_raw_config_t vsd_config; 3217 cprimod_encap_decap_data_config_t encap_decap_data; 3218 3219 SOC_INIT_FUNC_DEFS; 3220 3221 encap_decap_data.sample_size = 16; 3222 encap_decap_data.truncation_enable = FALSE; 3223 encap_decap_data.truncation_type = 0; 3224 encap_decap_data.compression_type = cprimod_no_compress; 3225 encap_decap_data.mux_enable = 0; 3226 encap_decap_data.bit_reversal = FALSE; 3227 encap_decap_data.buffer_size = config_info->queue_size; 3228 encap_decap_data.priority = config_info->priority; 3229 encap_decap_data.cycle_size = 0; /* not used for encap */ 3230 encap_decap_data.is_agnostic = 0; 3231 3232 _SOC_IF_ERR_EXIT 3233 (cprimod_cpri_encap_data_config_set(unit, port, config_info->queue_num, &encap_decap_data)); 3234 3235 3236 vsd_config.schan_start = config_info->schan_start ; 3237 vsd_config.schan_size = config_info->schan_size ; 3238 vsd_config.cw_sel = config_info->cw_sel; 3239 vsd_config.cw_size = config_info->cw_size; 3240 vsd_config.filter_mode = config_info->filter_mode; 3241 vsd_config.hyper_frame_index = config_info->hyper_frame_index; 3242 vsd_config.hyper_frame_modulo = config_info->hyper_frame_modulo; 3243 vsd_config.match_offset = config_info->match_offset; 3244 vsd_config.match_value = config_info->match_value; 3245 vsd_config.match_mask = config_info->match_mask; 3246 vsd_config.queue_num = config_info->queue_num; 3247 3248 _SOC_IF_ERR_EXIT 3249 (cprimod_cpri_port_rx_vsd_raw_config_set(unit, port, index, &vsd_config)); 3250 exit: 3251 SOC_FUNC_RETURN; 3252 3253 } 3254 3255 int cpm4x25_cpri_port_rx_vsd_raw_config_get(int unit, int port, pm_info_t pm_info, uint32 index, portmod_cpri_rx_vsd_raw_config_t* config_info) 3256 { 3257 cprimod_cpri_rx_vsd_raw_config_t vsd_config; 3258 cprimod_encap_decap_data_config_t encap_decap_data; 3259 3260 SOC_INIT_FUNC_DEFS; 3261 3262 _SOC_IF_ERR_EXIT 3263 (cprimod_cpri_port_rx_vsd_raw_config_get(unit, port, index, &vsd_config)); 3264 3265 config_info->schan_start = vsd_config.schan_start; 3266 config_info->schan_size = vsd_config.schan_size; 3267 config_info->cw_sel = vsd_config.cw_sel; 3268 config_info->cw_size = vsd_config.cw_size; 3269 config_info->filter_mode = vsd_config.filter_mode; 3270 config_info->hyper_frame_index = vsd_config.hyper_frame_index; 3271 config_info->hyper_frame_modulo = vsd_config.hyper_frame_modulo; 3272 config_info->match_offset = vsd_config.match_offset; 3273 config_info->match_value = vsd_config.match_value; 3274 config_info->match_mask = vsd_config.match_mask; 3275 config_info->queue_num = vsd_config.queue_num; 3276 3277 _SOC_IF_ERR_EXIT 3278 (cprimod_cpri_encap_data_config_get(unit, port, config_info->queue_num, &encap_decap_data)); 3279 config_info->queue_size = encap_decap_data.buffer_size; 3280 config_info->priority = encap_decap_data.priority; 3281 3282 exit: 3283 SOC_FUNC_RETURN; 3284 3285 } 3286 3287 3288 int cpm4x25_cpri_port_tx_vsd_raw_config_set(int unit, int port, pm_info_t pm_info, uint32 index, const portmod_cpri_tx_vsd_raw_config_t* config_info) 3289 { 3290 cprimod_cpri_tx_vsd_raw_config_t vsd_config; 3291 cprimod_encap_decap_data_config_t encap_decap_data; 3292 SOC_INIT_FUNC_DEFS; 3293 3294 encap_decap_data.sample_size = 16; 3295 encap_decap_data.truncation_enable = FALSE; 3296 encap_decap_data.truncation_type = 0; 3297 encap_decap_data.compression_type = cprimod_no_compress; 3298 encap_decap_data.mux_enable = 0; 3299 encap_decap_data.bit_reversal = FALSE; 3300 encap_decap_data.cycle_size = config_info->cycle_size; 3301 encap_decap_data.priority = 0; /* not used for decap */ 3302 encap_decap_data.is_agnostic = 0; 3303 3304 /* added 16 bytes to the buffer. 3305 * The extra space is required to store the RoE Header for Tx Framer 3306 */ 3307 encap_decap_data.buffer_size = config_info->buffer_size + 16; 3308 3309 _SOC_IF_ERR_EXIT 3310 (cprimod_cpri_decap_data_config_set(unit, port, config_info->queue_num, &encap_decap_data)); 3311 3312 3313 vsd_config.schan_start = config_info->schan_start ; 3314 vsd_config.schan_size = config_info->schan_size ; 3315 vsd_config.cw_sel = config_info->cw_sel; 3316 vsd_config.cw_size = config_info->cw_size; 3317 vsd_config.map_mode = config_info->map_mode; 3318 vsd_config.hyper_frame_index = config_info->hyper_frame_index; 3319 vsd_config.hyper_frame_modulo = config_info->hyper_frame_modulo; 3320 vsd_config.repeat_enable = config_info->repeat_enable; 3321 vsd_config.bfn0_filter_enable = config_info->bfn0_filter_enable; 3322 vsd_config.bfn1_filter_enable = config_info->bfn1_filter_enable; 3323 vsd_config.queue_num = config_info->queue_num; 3324 vsd_config.idle_value = config_info->idle_value; 3325 3326 _SOC_IF_ERR_EXIT 3327 (cprimod_cpri_port_tx_vsd_raw_config_set(unit, port, index, &vsd_config)); 3328 exit: 3329 SOC_FUNC_RETURN; 3330 3331 } 3332 3333 int cpm4x25_cpri_port_tx_vsd_raw_config_get(int unit, int port, pm_info_t pm_info, uint32 index, portmod_cpri_tx_vsd_raw_config_t* config_info) 3334 { 3335 cprimod_cpri_tx_vsd_raw_config_t vsd_config; 3336 cprimod_encap_decap_data_config_t encap_decap_data; 3337 SOC_INIT_FUNC_DEFS; 3338 3339 _SOC_IF_ERR_EXIT 3340 (cprimod_cpri_port_tx_vsd_raw_config_get(unit, port, index, &vsd_config)); 3341 3342 config_info->schan_start = vsd_config.schan_start; 3343 config_info->schan_size = vsd_config.schan_size; 3344 config_info->cw_sel = vsd_config.cw_sel; 3345 config_info->cw_size = vsd_config.cw_size; 3346 config_info->map_mode = vsd_config.map_mode; 3347 config_info->hyper_frame_index = vsd_config.hyper_frame_index; 3348 config_info->hyper_frame_modulo = vsd_config.hyper_frame_modulo; 3349 config_info->repeat_enable = vsd_config.repeat_enable; 3350 config_info->bfn0_filter_enable = vsd_config.bfn0_filter_enable; 3351 config_info->bfn1_filter_enable = vsd_config.bfn1_filter_enable; 3352 config_info->queue_num = vsd_config.queue_num; 3353 config_info->idle_value = vsd_config.idle_value; 3354 3355 _SOC_IF_ERR_EXIT 3356 (cprimod_cpri_decap_data_config_get(unit, port, config_info->queue_num, &encap_decap_data)); 3357 3358 config_info->cycle_size = encap_decap_data.cycle_size; 3359 /* subtract 16 bytes from the buffer. The extra space was added when config was 3360 * added to store the RoE Header for Tx Framer 3361 */ 3362 config_info->buffer_size = encap_decap_data.buffer_size-16; 3363 3364 exit: 3365 SOC_FUNC_RETURN; 3366 3367 } 3368 3369 int cpm4x25_cpri_port_tx_vsd_raw_filter_set(int unit, int port, pm_info_t pm_info, uint32 bfn0_value, uint32 bfn0_mask, uint32 bfn1_value, uint32 bfn1_mask) 3370 { 3371 SOC_INIT_FUNC_DEFS; 3372 3373 _SOC_IF_ERR_EXIT 3374 (cprimod_cpri_port_tx_vsd_raw_filter_set(unit, port, bfn0_value, bfn0_mask, bfn1_value, bfn1_mask)); 3375 3376 exit: 3377 SOC_FUNC_RETURN; 3378 3379 } 3380 3381 int cpm4x25_cpri_port_tx_vsd_raw_filter_get(int unit, int port, pm_info_t pm_info, uint32* bfn0_value, uint32* bfn0_mask, uint32* bfn1_value, uint32* bfn1_mask) 3382 { 3383 SOC_INIT_FUNC_DEFS; 3384 3385 _SOC_IF_ERR_EXIT 3386 (cprimod_cpri_port_tx_vsd_raw_filter_get(unit, port, bfn0_value, bfn0_mask, bfn1_value, bfn1_mask)); 3387 3388 exit: 3389 SOC_FUNC_RETURN; 3390 3391 } 3392 3393 int cpm4x25_cpri_port_rx_brcm_rsvd5_config_set(int unit, int port, pm_info_t pm_info, const portmod_cpri_rx_brcm_rsvd5_config_t* config_info) 3394 { 3395 cprimod_encap_decap_data_config_t encap_decap_data; 3396 3397 SOC_INIT_FUNC_DEFS; 3398 3399 encap_decap_data.sample_size = 16; 3400 encap_decap_data.truncation_enable = FALSE; 3401 encap_decap_data.truncation_type = 0; 3402 encap_decap_data.compression_type = cprimod_no_compress; 3403 encap_decap_data.mux_enable = 0; 3404 encap_decap_data.bit_reversal = FALSE; 3405 encap_decap_data.buffer_size = config_info->queue_size; 3406 encap_decap_data.priority = config_info->priority; 3407 encap_decap_data.cycle_size = 0; /* not used for encap */ 3408 encap_decap_data.is_agnostic = 0; 3409 3410 _SOC_IF_ERR_EXIT 3411 (cprimod_cpri_encap_data_config_set(unit, port, config_info->queue_num, &encap_decap_data)); 3412 3413 _SOC_IF_ERR_EXIT 3414 (cprimod_cpri_port_rx_brcm_rsvd5_control_config_set(unit, port, 3415 config_info->schan_start, 3416 config_info->schan_size, 3417 config_info->queue_num, 3418 config_info->parity_disable)); 3419 3420 exit: 3421 SOC_FUNC_RETURN; 3422 3423 } 3424 3425 int cpm4x25_cpri_port_rx_brcm_rsvd5_config_get(int unit, int port, pm_info_t pm_info, portmod_cpri_rx_brcm_rsvd5_config_t* config_info) 3426 { 3427 cprimod_encap_decap_data_config_t encap_decap_data; 3428 SOC_INIT_FUNC_DEFS; 3429 3430 _SOC_IF_ERR_EXIT 3431 (cprimod_cpri_port_rx_brcm_rsvd5_control_config_get(unit, port, 3432 &config_info->schan_start, 3433 &config_info->schan_size, 3434 &config_info->queue_num, 3435 &config_info->parity_disable)); 3436 3437 _SOC_IF_ERR_EXIT 3438 (cprimod_cpri_encap_data_config_get(unit, port, config_info->queue_num, &encap_decap_data)); 3439 3440 config_info->queue_size = encap_decap_data.buffer_size; 3441 config_info->priority = encap_decap_data.priority; 3442 3443 exit: 3444 SOC_FUNC_RETURN; 3445 } 3446 3447 3448 int cpm4x25_cpri_port_tx_brcm_rsvd5_config_set(int unit, int port, pm_info_t pm_info, const portmod_cpri_tx_brcm_rsvd5_config_t* config_info) 3449 { 3450 cprimod_encap_decap_data_config_t encap_decap_data; 3451 SOC_INIT_FUNC_DEFS; 3452 3453 encap_decap_data.sample_size = 16; 3454 encap_decap_data.truncation_enable = FALSE; 3455 encap_decap_data.truncation_type = 0; 3456 encap_decap_data.compression_type = cprimod_no_compress; 3457 encap_decap_data.mux_enable = 0; 3458 encap_decap_data.bit_reversal = FALSE; 3459 encap_decap_data.cycle_size = config_info->cycle_size; 3460 encap_decap_data.priority = 0; /* not used for decap */ 3461 encap_decap_data.is_agnostic = 0; 3462 3463 /* added 16 bytes to the buffer. 3464 * The extra space is required to store the RoE Header for Tx Framer 3465 */ 3466 encap_decap_data.buffer_size = config_info->buffer_size + 16; 3467 3468 _SOC_IF_ERR_EXIT 3469 (cprimod_cpri_decap_data_config_set(unit, port, config_info->queue_num, &encap_decap_data)); 3470 3471 _SOC_IF_ERR_EXIT 3472 (cprimod_cpri_port_tx_brcm_rsvd5_control_config_set(unit, port, 3473 config_info->schan_start, 3474 config_info->schan_size, 3475 config_info->queue_num, 3476 config_info->crc_enable)); 3477 3478 exit: 3479 SOC_FUNC_RETURN; 3480 } 3481 3482 int cpm4x25_cpri_port_tx_brcm_rsvd5_config_get(int unit, int port, pm_info_t pm_info, portmod_cpri_tx_brcm_rsvd5_config_t* config_info) 3483 { 3484 cprimod_encap_decap_data_config_t encap_decap_data; 3485 SOC_INIT_FUNC_DEFS; 3486 3487 _SOC_IF_ERR_EXIT 3488 (cprimod_cpri_port_tx_brcm_rsvd5_control_config_get(unit, port, 3489 &config_info->schan_start, 3490 &config_info->schan_size, 3491 &config_info->queue_num, 3492 &config_info->crc_enable)); 3493 3494 _SOC_IF_ERR_EXIT 3495 (cprimod_cpri_decap_data_config_get(unit, port, config_info->queue_num, &encap_decap_data)); 3496 3497 config_info->cycle_size = encap_decap_data.cycle_size; 3498 config_info->buffer_size = encap_decap_data.buffer_size-16; 3499 3500 exit: 3501 SOC_FUNC_RETURN; 3502 3503 } 3504 3505 int cpm4x25_cpri_port_rx_gcw_config_set(int unit, int port, pm_info_t pm_info, uint32 index, const portmod_cpri_rx_gcw_config_t* config_info) 3506 { 3507 cprimod_cpri_rx_gcw_config_t gcw_config; 3508 SOC_INIT_FUNC_DEFS; 3509 3510 gcw_config.Ns = config_info->Ns; 3511 gcw_config.Xs = config_info->Xs; 3512 gcw_config.Y = config_info->Y; 3513 gcw_config.mask = config_info->mask; 3514 3515 gcw_config.filter_mode = config_info->filter_mode; 3516 gcw_config.hyper_frame_index = config_info->hyper_frame_index;; 3517 gcw_config.hyper_frame_modulo = config_info->hyper_frame_modulo;; 3518 gcw_config.match_mask = config_info->match_mask; 3519 gcw_config.match_value = config_info->match_value; 3520 3521 _SOC_IF_ERR_EXIT 3522 (cprimod_cpri_port_rx_gcw_config_set(unit, port, index, &gcw_config)); 3523 3524 3525 exit: 3526 SOC_FUNC_RETURN; 3527 3528 } 3529 3530 int cpm4x25_cpri_port_rx_gcw_config_get(int unit, int port, pm_info_t pm_info, uint32 index, portmod_cpri_rx_gcw_config_t* config_info) 3531 { 3532 cprimod_cpri_rx_gcw_config_t gcw_config; 3533 SOC_INIT_FUNC_DEFS; 3534 3535 _SOC_IF_ERR_EXIT 3536 (cprimod_cpri_port_rx_gcw_config_get(unit, port, index, &gcw_config)); 3537 3538 config_info->Ns = gcw_config.Ns; 3539 config_info->Xs = gcw_config.Xs; 3540 config_info->Y = gcw_config.Y; 3541 config_info->mask = gcw_config.mask; 3542 3543 config_info->filter_mode = gcw_config.filter_mode; 3544 config_info->hyper_frame_index = gcw_config.hyper_frame_index; 3545 config_info->hyper_frame_modulo = gcw_config.hyper_frame_modulo; 3546 config_info->match_mask = gcw_config.match_mask; 3547 config_info->match_value = gcw_config.match_value; 3548 3549 exit: 3550 SOC_FUNC_RETURN; 3551 } 3552 3553 3554 int cpm4x25_cpri_port_tx_gcw_config_set(int unit, int port, pm_info_t pm_info, uint32 index, const portmod_cpri_tx_gcw_config_t* config_info) 3555 { 3556 cprimod_cpri_tx_gcw_config_t gcw_config; 3557 SOC_INIT_FUNC_DEFS; 3558 3559 gcw_config.Ns = config_info->Ns; 3560 gcw_config.Xs = config_info->Xs; 3561 gcw_config.Y = config_info->Y; 3562 gcw_config.mask = config_info->mask; 3563 3564 gcw_config.hyper_frame_index = config_info->hyper_frame_index;; 3565 gcw_config.hyper_frame_modulo = config_info->hyper_frame_modulo;; 3566 gcw_config.repeat_enable = config_info->repeat_enable; 3567 gcw_config.bfn0_filter_enable = config_info->bfn0_filter_enable; 3568 gcw_config.bfn1_filter_enable = config_info->bfn1_filter_enable; 3569 3570 _SOC_IF_ERR_EXIT 3571 (cprimod_cpri_port_tx_gcw_config_set(unit, port, index, &gcw_config)); 3572 exit: 3573 SOC_FUNC_RETURN; 3574 3575 } 3576 3577 int cpm4x25_cpri_port_tx_gcw_config_get(int unit, int port, pm_info_t pm_info, uint32 index, portmod_cpri_tx_gcw_config_t* config_info) 3578 { 3579 cprimod_cpri_tx_gcw_config_t gcw_config; 3580 SOC_INIT_FUNC_DEFS; 3581 3582 _SOC_IF_ERR_EXIT 3583 (cprimod_cpri_port_tx_gcw_config_get(unit, port, index, &gcw_config)); 3584 3585 config_info->Ns = gcw_config.Ns; 3586 config_info->Xs = gcw_config.Xs; 3587 config_info->Y = gcw_config.Y; 3588 config_info->mask = gcw_config.mask; 3589 3590 config_info->hyper_frame_index = gcw_config.hyper_frame_index;; 3591 config_info->hyper_frame_modulo = gcw_config.hyper_frame_modulo;; 3592 config_info->repeat_enable = gcw_config.repeat_enable; 3593 config_info->bfn0_filter_enable = gcw_config.bfn0_filter_enable; 3594 config_info->bfn1_filter_enable = gcw_config.bfn1_filter_enable; 3595 3596 exit: 3597 SOC_FUNC_RETURN; 3598 3599 } 3600 3601 int cpm4x25_cpri_port_tx_gcw_filter_set(int unit, int port, pm_info_t pm_info, uint32 bfn0_value, uint32 bfn0_mask, uint32 bfn1_value, uint32 bfn1_mask) 3602 { 3603 SOC_INIT_FUNC_DEFS; 3604 3605 _SOC_IF_ERR_EXIT 3606 (cprimod_cpri_port_tx_gcw_filter_set(unit, port, bfn0_value, bfn0_mask, bfn1_value, bfn1_mask)); 3607 3608 exit: 3609 SOC_FUNC_RETURN; 3610 3611 } 3612 3613 int cpm4x25_cpri_port_tx_gcw_filter_get(int unit, int port, pm_info_t pm_info, uint32* bfn0_value, uint32* bfn0_mask, uint32* bfn1_value, uint32* bfn1_mask) 3614 { 3615 SOC_INIT_FUNC_DEFS; 3616 3617 _SOC_IF_ERR_EXIT 3618 (cprimod_cpri_port_tx_gcw_filter_get(unit, port, bfn0_value, bfn0_mask, bfn1_value, bfn1_mask)); 3619 3620 exit: 3621 SOC_FUNC_RETURN; 3622 3623 } 3624 3625 3626 int cpm4x25_cpri_port_tx_cw_sync_info_set(int unit, int port, pm_info_t pm_info, const uint32 hyper_frame_num, const uint32 radio_frame_num) 3627 { 3628 SOC_INIT_FUNC_DEFS; 3629 3630 3631 _SOC_IF_ERR_EXIT 3632 (cprimod_tx_framer_tgen_next_hfn_config_set(unit,port, hyper_frame_num)); 3633 _SOC_IF_ERR_EXIT 3634 (cprimod_tx_framer_tgen_next_bfn_config_set(unit,port, radio_frame_num)); 3635 3636 exit: 3637 SOC_FUNC_RETURN; 3638 3639 } 3640 3641 int cpm4x25_cpri_port_tx_cw_sync_info_get(int unit, int port, pm_info_t pm_info, uint32* hyper_frame_num, uint32* radio_frame_num) 3642 { 3643 SOC_INIT_FUNC_DEFS; 3644 3645 _SOC_IF_ERR_EXIT 3646 (cprimod_tx_framer_tgen_next_hfn_config_get(unit,port,hyper_frame_num)); 3647 _SOC_IF_ERR_EXIT 3648 (cprimod_tx_framer_tgen_next_bfn_config_get(unit,port,radio_frame_num)); 3649 3650 exit: 3651 SOC_FUNC_RETURN; 3652 3653 } 3654 3655 int cpm4x25_cpri_port_tx_cw_l1_config_set(int unit, int port, pm_info_t pm_info, const portmod_cpri_cw_l1_config_info_t* control_info) 3656 { 3657 SOC_INIT_FUNC_DEFS; 3658 3659 _SOC_IF_ERR_EXIT 3660 (cprimod_cpri_port_tx_control_word_set(unit, port, control_info)); 3661 3662 exit: 3663 SOC_FUNC_RETURN; 3664 3665 } 3666 3667 /* BRCM_RSVD4 */ 3668 int cpm4x25_rsvd4_rx_control_flow_add (int unit, int port, pm_info_t pm_info, uint32 flow_id, const portmod_control_flow_config_t* config) 3669 { 3670 cprimod_control_flow_config_t flow_config; 3671 cprimod_rsvd4_encap_data_config_t encap_decap_data; 3672 cprimod_header_compare_entry_t hdr_entry; 3673 cprimod_cpri_tag_option_t tag_option; 3674 SOC_INIT_FUNC_DEFS; 3675 3676 cprimod_rsvd4_encap_data_config_t_init(&encap_decap_data); 3677 3678 encap_decap_data.buffer_size = config->queue_size; 3679 encap_decap_data.priority = config->priority ; 3680 encap_decap_data.gsm_pad_size = 0; 3681 encap_decap_data.gsm_extra_pad_size = 0; 3682 encap_decap_data.gsm_pad_enable = 0; 3683 encap_decap_data.gsm_control_location = 0; 3684 if (config->proc_type == PORTMOD_CONTROL_MSG_PROC_TYPE_FE){ 3685 encap_decap_data.bit_reversal = 0; 3686 } else { 3687 encap_decap_data.bit_reversal = 1; 3688 } 3689 3690 _SOC_IF_ERR_EXIT 3691 (cprimod_rsvd4_encap_data_config_set(unit, port, config->queue_num, &encap_decap_data)); 3692 3693 flow_config.proc_type = config->proc_type; 3694 flow_config.queue_num = config->queue_num; 3695 flow_config.sync_profile = config->sync_profile; 3696 flow_config.sync_enable = config->sync_enable; 3697 3698 _SOC_IF_ERR_EXIT 3699 (cprimod_rsvd4_rx_control_flow_config_set(unit, port, flow_id, &flow_config)); 3700 3701 /* 3702 * Set tag option to use default tag or look up. 3703 */ 3704 if ((config->proc_type == PORTMOD_CONTROL_MSG_PROC_TYPE_PAYLOAD) || 3705 (config->proc_type == PORTMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE_W_TAG)) { 3706 tag_option = CPRIMOD_CPRI_TAG_LOOKUP; 3707 } else { 3708 tag_option = CPRIMOD_CPRI_TAG_DEFAULT; 3709 } 3710 3711 _SOC_IF_ERR_EXIT 3712 (cprimod_rx_control_flow_tag_option_set(unit, port, flow_id, tag_option)); 3713 3714 hdr_entry.valid = 1; 3715 hdr_entry.match_data = config->match_data; 3716 hdr_entry.mask = config->match_mask; 3717 hdr_entry.flow_id = flow_id; 3718 hdr_entry.flow_type = cprimodFlowTypeCtrl; 3719 3720 _SOC_IF_ERR_EXIT 3721 (cprimod_header_compare_entry_add(unit, port, 3722 &hdr_entry)); 3723 3724 exit: 3725 SOC_FUNC_RETURN; 3726 3727 } 3728 int cpm4x25_rsvd4_rx_control_flow_delete(int unit, int port, pm_info_t pm_info, uint32 flow_id,const portmod_control_flow_config_t* config) 3729 { 3730 cprimod_header_compare_entry_t hdr_entry; 3731 3732 SOC_INIT_FUNC_DEFS; 3733 3734 hdr_entry.valid = 1; 3735 hdr_entry.match_data = config->match_data; 3736 hdr_entry.mask = config->match_mask; 3737 hdr_entry.flow_id = flow_id; 3738 hdr_entry.flow_type = cprimodFlowTypeCtrl; 3739 3740 _SOC_IF_ERR_EXIT 3741 (cprimod_header_compare_entry_delete(unit, port, 3742 &hdr_entry)); 3743 3744 exit: 3745 SOC_FUNC_RETURN; 3746 3747 } 3748 3749 int cpm4x25_rsvd4_fast_eth_config_set(int unit, int port, pm_info_t pm_info, const portmod_cpri_fast_eth_config_t* config_info) 3750 { 3751 SOC_INIT_FUNC_DEFS; 3752 3753 _SOC_IF_ERR_EXIT 3754 (cprimod_rsvd4_fast_eth_config_set(unit, port, config_info)); 3755 3756 exit: 3757 SOC_FUNC_RETURN; 3758 3759 } 3760 3761 int cpm4x25_rsvd4_rx_sync_profile_entry_set(int unit, int port, pm_info_t pm_info, uint32 profile_id, const portmod_sync_profile_entry_t* entry) 3762 { 3763 cprimod_sync_profile_entry_t sync_profile; 3764 SOC_INIT_FUNC_DEFS; 3765 3766 sync_profile.count_cycle = entry->count_cycle; 3767 sync_profile.message_offset = entry->message_offset; 3768 sync_profile.master_frame_offset = entry->master_frame_offset; 3769 3770 _SOC_IF_ERR_EXIT 3771 (cprimod_rsvd4_rx_sync_profile_entry_set(unit, port, profile_id, &sync_profile)); 3772 3773 exit: 3774 SOC_FUNC_RETURN; 3775 3776 } 3777 3778 int cpm4x25_rsvd4_rx_sync_profile_entry_get(int unit, int port, pm_info_t pm_info, uint32 profile_id, portmod_sync_profile_entry_t* entry) 3779 { 3780 cprimod_sync_profile_entry_t sync_profile; 3781 SOC_INIT_FUNC_DEFS; 3782 3783 _SOC_IF_ERR_EXIT 3784 (cprimod_rsvd4_rx_sync_profile_entry_get(unit, port, profile_id, &sync_profile)); 3785 3786 entry->count_cycle = sync_profile.count_cycle; 3787 entry->message_offset = sync_profile.message_offset; 3788 entry->master_frame_offset = sync_profile.master_frame_offset; 3789 3790 exit: 3791 SOC_FUNC_RETURN; 3792 3793 } 3794 3795 int cpm4x25_rx_tag_config_set(int unit, int port, pm_info_t pm_info, uint32 default_tag, uint32 no_match_tag) 3796 { 3797 SOC_INIT_FUNC_DEFS; 3798 3799 _SOC_IF_ERR_EXIT 3800 (cprimod_rx_tag_config_set(unit, port, default_tag, no_match_tag)); 3801 3802 exit: 3803 SOC_FUNC_RETURN; 3804 3805 } 3806 3807 3808 int cpm4x25_rx_tag_gen_entry_add(int unit, int port, pm_info_t pm_info, const portmod_tag_gen_entry_t* entry) 3809 { 3810 SOC_INIT_FUNC_DEFS; 3811 3812 _SOC_IF_ERR_EXIT 3813 (cprimod_rx_tag_gen_entry_add(unit, port, entry)); 3814 exit: 3815 SOC_FUNC_RETURN; 3816 3817 } 3818 3819 3820 int cpm4x25_rx_tag_gen_entry_delete(int unit, int port, pm_info_t pm_info, const portmod_tag_gen_entry_t* entry) 3821 { 3822 SOC_INIT_FUNC_DEFS; 3823 3824 _SOC_IF_ERR_EXIT 3825 (cprimod_rx_tag_gen_entry_delete(unit, port, entry)); 3826 exit: 3827 SOC_FUNC_RETURN; 3828 3829 } 3830 3831 int cpm4x25_rsvd4_tx_control_flow_group_member_add(int unit, int port, pm_info_t pm_info, 3832 uint32 group_id, uint32 priority, 3833 uint32 queue_num, 3834 portmod_control_msg_proc_type_t proc_type) 3835 { 3836 SOC_INIT_FUNC_DEFS; 3837 3838 _SOC_IF_ERR_EXIT 3839 (cprimod_rsvd4_tx_control_flow_group_member_add(unit , port, group_id, 3840 priority, queue_num, 3841 proc_type)); 3842 3843 exit: 3844 SOC_FUNC_RETURN; 3845 3846 } 3847 3848 3849 int cpm4x25_rsvd4_tx_control_flow_group_member_delete(int unit, int port, pm_info_t pm_info, 3850 uint32 group_id, 3851 uint32 priority) 3852 { 3853 SOC_INIT_FUNC_DEFS; 3854 _SOC_IF_ERR_EXIT 3855 (cprimod_rsvd4_tx_control_flow_group_member_delete(unit , port, group_id, priority)); 3856 exit: 3857 SOC_FUNC_RETURN; 3858 3859 } 3860 3861 int cpm4x25_rsvd4_tx_eth_message_config_set(int unit, int port, pm_info_t pm_info, uint32 msg_node, uint32 msg_subnode, uint32 msg_type, uint32 msg_padding) 3862 { 3863 SOC_INIT_FUNC_DEFS; 3864 3865 _SOC_IF_ERR_EXIT 3866 (cprimod_rsvd4_tx_eth_message_config_set(unit, port, msg_node, msg_subnode, msg_type, msg_padding)); 3867 3868 exit: 3869 SOC_FUNC_RETURN; 3870 3871 } 3872 3873 3874 int cpm4x25_rsvd4_tx_single_raw_message_config_set(int unit, int port, pm_info_t pm_info, uint32 msg_id, uint32 msg_type) 3875 { 3876 SOC_INIT_FUNC_DEFS; 3877 3878 _SOC_IF_ERR_EXIT 3879 (cprimod_rsvd4_tx_single_raw_message_config_set(unit, port, msg_id, msg_type)); 3880 3881 exit: 3882 SOC_FUNC_RETURN; 3883 3884 } 3885 3886 int cpm4x25_rsvd4_tx_control_flow_config_set(int unit, int port, pm_info_t pm_info, uint32 flow_id, const portmod_rsvd4_tx_config_info_t* config_info) 3887 { 3888 cprimod_rsvd4_decap_data_config_t decap_data_info; 3889 cprimod_rsvd4_tx_config_info_t control_flow; 3890 SOC_INIT_FUNC_DEFS; 3891 3892 cprimod_rsvd4_decap_data_config_t_init(&decap_data_info); 3893 cprimod_rsvd4_tx_config_info_t_init(&control_flow); 3894 3895 decap_data_info.buffer_size = config_info->queue_size; 3896 decap_data_info.cycle_size = config_info->cycle_size; 3897 decap_data_info.gsm_pad_size = 0; 3898 decap_data_info.gsm_extra_pad_size = 0; 3899 decap_data_info.gsm_pad_enable = 0; 3900 decap_data_info.gsm_control_location = 0; 3901 if (config_info->proc_type == PORTMOD_CONTROL_MSG_PROC_TYPE_FE){ 3902 decap_data_info.bit_reversal = 0; 3903 } else { 3904 decap_data_info.bit_reversal = 1; 3905 } 3906 3907 _SOC_IF_ERR_EXIT 3908 (cprimod_rsvd4_decap_data_config_set(unit, port, config_info->queue_num, &decap_data_info)); 3909 3910 control_flow.proc_type = config_info->proc_type; 3911 control_flow.queue_num = config_info->queue_num; 3912 control_flow.crc_mode = config_info->crc_mode; 3913 3914 _SOC_IF_ERR_EXIT 3915 (cprimod_rsvd4_tx_control_flow_config_set(unit, port, flow_id, &control_flow)); 3916 3917 3918 exit: 3919 SOC_FUNC_RETURN; 3920 3921 } 3922 3923 int cpm4x25_rsvd4_tx_control_flow_config_get(int unit, int port, pm_info_t pm_info, uint32 flow_id, portmod_rsvd4_tx_config_info_t* config_info) 3924 { 3925 cprimod_rsvd4_decap_data_config_t encap_decap_data; 3926 cprimod_rsvd4_tx_config_info_t tx_config; 3927 SOC_INIT_FUNC_DEFS; 3928 3929 cprimod_rsvd4_decap_data_config_t_init(&encap_decap_data); 3930 3931 _SOC_IF_ERR_EXIT 3932 (cprimod_rsvd4_tx_control_flow_config_get(unit, port, flow_id, &tx_config)); 3933 3934 3935 _SOC_IF_ERR_EXIT 3936 (cprimod_rsvd4_decap_data_config_get(unit, port, tx_config.queue_num, &encap_decap_data )); 3937 3938 config_info->queue_num= tx_config.queue_num; 3939 config_info->proc_type= tx_config.proc_type; 3940 config_info->crc_mode = tx_config.crc_mode; 3941 config_info->queue_size = encap_decap_data.buffer_size; 3942 config_info->cycle_size = encap_decap_data.cycle_size; 3943 3944 3945 exit: 3946 SOC_FUNC_RETURN; 3947 3948 } 3949 3950 int cpm4x25_rsvd4_tx_control_flow_header_index_set(int unit, int port, pm_info_t pm_info, uint32 roe_flow_id, uint32 index) 3951 { 3952 SOC_INIT_FUNC_DEFS; 3953 3954 _SOC_IF_ERR_EXIT 3955 (cprimod_rsvd4_tx_control_flow_header_index_set(unit, port, roe_flow_id, index)); 3956 3957 3958 exit: 3959 SOC_FUNC_RETURN; 3960 3961 } 3962 3963 int cpm4x25_rsvd4_tx_control_flow_header_index_get(int unit, int port, pm_info_t pm_info, uint32 roe_flow_id, uint32* index) 3964 { 3965 SOC_INIT_FUNC_DEFS; 3966 3967 _SOC_IF_ERR_EXIT 3968 (cprimod_rsvd4_tx_control_flow_header_index_get(unit, port, roe_flow_id, index)); 3969 3970 exit: 3971 SOC_FUNC_RETURN; 3972 3973 } 3974 3975 int cpm4x25_rsvd4_tx_control_header_entry_set(int unit, int port, pm_info_t pm_info, uint32 index, uint32 header_node, uint32 header_subnode, uint32 payload_node) 3976 { 3977 SOC_INIT_FUNC_DEFS; 3978 3979 _SOC_IF_ERR_EXIT 3980 (cprimod_rsvd4_tx_control_header_entry_set(unit, port, index, header_node, header_subnode, payload_node)); 3981 3982 exit: 3983 SOC_FUNC_RETURN; 3984 3985 } 3986 3987 int cpm4x25_rsvd4_tx_control_header_entry_get(int unit, int port, pm_info_t pm_info, uint32 index, uint32* header_node, uint32* header_subnode, uint32* payload_node) 3988 { 3989 SOC_INIT_FUNC_DEFS; 3990 3991 _SOC_IF_ERR_EXIT 3992 (cprimod_rsvd4_tx_control_header_entry_get(unit, port, index, header_node, header_subnode, payload_node)); 3993 3994 exit: 3995 SOC_FUNC_RETURN; 3996 3997 } 3998 3999 int cpm4x25_rsvd4_tx_single_tunnel_message_config_set(int unit, int port, pm_info_t pm_info, cprimod_cpri_crc_option_t crc_option) 4000 { 4001 SOC_INIT_FUNC_DEFS; 4002 4003 _SOC_IF_ERR_EXIT 4004 (cprimod_rsvd4_tx_single_tunnel_message_config_set(unit, port, crc_option)); 4005 4006 exit: 4007 SOC_FUNC_RETURN; 4008 4009 } 4010 4011 int cpm4x25_cpri_port_interrupt_link_status_get(int unit, int port, 4012 pm_info_t pm_info, 4013 int* is_link_intr_status) 4014 { 4015 int phy, lport, ii = 0, val = 0; 4016 int tmp_link_change_status=0; 4017 SOC_INIT_FUNC_DEFS; 4018 4019 /* 4020 * Check all the CPRI port link status in core 4021 */ 4022 PORTMOD_PBMP_ITER(PM_4x25_INFO(pm_info)->phys, phy){ 4023 _SOC_IF_ERR_EXIT(CPM4x25_LANE2PORT_GET(unit, pm_info, ii, &lport)); 4024 /* skip if port is invalid */ 4025 if(lport < 0) { 4026 continue; 4027 } 4028 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, lport, &val)); 4029 /* Only if CPRI port */ 4030 if (val) { 4031 _SOC_IF_ERR_EXIT(cprimod_cpri_port_interrupt_link_status_get(unit, 4032 lport, &tmp_link_change_status)); 4033 *is_link_intr_status |= tmp_link_change_status; 4034 } 4035 ii++; 4036 } 4037 4038 exit: 4039 SOC_FUNC_RETURN; 4040 } 4041 4042 int cpm4x25_cpri_port_interrupt_enable_set(int unit, int port, 4043 pm_info_t pm_info, 4044 portmod_cpri_port_intr_type_t intr_type, 4045 int data, int enable) 4046 { 4047 SOC_INIT_FUNC_DEFS; 4048 4049 _SOC_IF_ERR_EXIT(cprimod_cpri_port_interrupt_enable_set(unit, port, 4050 intr_type, data, 4051 enable)); 4052 4053 4054 exit: 4055 SOC_FUNC_RETURN; 4056 } 4057 4058 int cpm4x25_cpri_port_interrupt_process(int unit, int port, pm_info_t pm_info) 4059 { 4060 int phy, lport, ii = 0, val = 0; 4061 SOC_INIT_FUNC_DEFS; 4062 4063 /* 4064 * Check all the CPRI port link status in core 4065 */ 4066 PORTMOD_PBMP_ITER(PM_4x25_INFO(pm_info)->phys, phy){ 4067 _SOC_IF_ERR_EXIT(CPM4x25_LANE2PORT_GET(unit, pm_info, ii, &lport)); 4068 /* skip if invalid port */ 4069 if (lport < 0) { 4070 continue; 4071 } 4072 4073 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, lport, &val)); 4074 /* Only if CPRI port */ 4075 if (val) { 4076 _SOC_IF_ERR_EXIT(cprimod_cpri_port_interrupt_process(unit, lport)); 4077 } 4078 ii++; 4079 } 4080 4081 exit: 4082 SOC_FUNC_RETURN; 4083 } 4084 4085 int cpm4x25_fast_clk_bit_time_period_set(int unit, int port, pm_info_t pm_info, uint32 bit_time_period) 4086 { 4087 SOC_INIT_FUNC_DEFS; 4088 _SOC_IF_ERR_EXIT(cprimod_fast_clk_bit_time_period_set(unit, port, bit_time_period)); 4089 4090 exit: 4091 SOC_FUNC_RETURN; 4092 4093 } 4094 4095 int cpm4x25_fast_clk_bit_time_period_get(int unit, int port, pm_info_t pm_info, uint32* bit_time_period) 4096 { 4097 SOC_INIT_FUNC_DEFS; 4098 _SOC_IF_ERR_EXIT(cprimod_fast_clk_bit_time_period_get(unit, port, bit_time_period)); 4099 4100 exit: 4101 SOC_FUNC_RETURN; 4102 4103 } 4104 4105 4106 int cpm4x25_1588_bit_time_period_set(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, cprimod_port_speed_t speed) 4107 { 4108 SOC_INIT_FUNC_DEFS; 4109 _SOC_IF_ERR_EXIT(cprimod_1588_bit_time_period_set(unit, port, direction, speed)); 4110 4111 exit: 4112 SOC_FUNC_RETURN; 4113 4114 } 4115 4116 int cpm4x25_1588_bit_time_period_get(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, uint32* bit_time_period) 4117 { 4118 SOC_INIT_FUNC_DEFS; 4119 _SOC_IF_ERR_EXIT(cprimod_1588_bit_time_period_get(unit, port, direction, bit_time_period)); 4120 4121 exit: 4122 SOC_FUNC_RETURN; 4123 4124 } 4125 4126 4127 int cpm4x25_1588_timestamp_capture_config_set(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, const cprimod_1588_capture_config_t* config) 4128 { 4129 SOC_INIT_FUNC_DEFS; 4130 _SOC_IF_ERR_EXIT(cprimod_1588_timestamp_capture_config_set(unit, port, 4131 direction, config)); 4132 exit: 4133 SOC_FUNC_RETURN; 4134 4135 } 4136 4137 int cpm4x25_1588_timestamp_capture_config_get(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, cprimod_1588_capture_config_t* config) 4138 { 4139 SOC_INIT_FUNC_DEFS; 4140 _SOC_IF_ERR_EXIT(cprimod_1588_timestamp_capture_config_get(unit, port, direction, config)); 4141 4142 exit: 4143 SOC_FUNC_RETURN; 4144 4145 } 4146 4147 4148 int cpm4x25_1588_captured_timestamp_get(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, portmod_1588_ts_type_t ts_type, uint8 mx_cnt, uint8* count, uint64* captured_time) 4149 { 4150 SOC_INIT_FUNC_DEFS; 4151 _SOC_IF_ERR_EXIT(cprimod_1588_captured_timestamp_get(unit, port, direction, ts_type, mx_cnt, count, captured_time)); 4152 4153 exit: 4154 SOC_FUNC_RETURN; 4155 4156 } 4157 4158 4159 int cpm4x25_1588_timestamp_adjust_set(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, const cprimod_1588_time_t* adjust_time) 4160 { 4161 SOC_INIT_FUNC_DEFS; 4162 _SOC_IF_ERR_EXIT(cprimod_1588_timestamp_adjust_set(unit, port, direction, adjust_time)); 4163 4164 exit: 4165 SOC_FUNC_RETURN; 4166 4167 } 4168 4169 int cpm4x25_1588_timestamp_adjust_get(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, cprimod_1588_time_t* adjust_time) 4170 { 4171 SOC_INIT_FUNC_DEFS; 4172 _SOC_IF_ERR_EXIT(cprimod_1588_timestamp_adjust_get(unit, port, direction, adjust_time)); 4173 4174 exit: 4175 SOC_FUNC_RETURN; 4176 4177 } 4178 4179 4180 int cpm4x25_1588_timestamp_fifo_config_set(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, uint16 modulo) 4181 { 4182 SOC_INIT_FUNC_DEFS; 4183 _SOC_IF_ERR_EXIT(cprimod_1588_timestamp_fifo_config_set(unit, port, direction, modulo)); 4184 4185 exit: 4186 SOC_FUNC_RETURN; 4187 4188 } 4189 4190 int cpm4x25_1588_timestamp_fifo_config_get(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, uint16* modulo) 4191 { 4192 SOC_INIT_FUNC_DEFS; 4193 _SOC_IF_ERR_EXIT(cprimod_1588_timestamp_fifo_config_get(unit, port, direction, modulo)); 4194 4195 exit: 4196 SOC_FUNC_RETURN; 4197 4198 } 4199 4200 4201 int cpm4x25_1588_timestamp_cmic_config_set(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, uint16 modulo) 4202 { 4203 SOC_INIT_FUNC_DEFS; 4204 _SOC_IF_ERR_EXIT(cprimod_1588_timestamp_cmic_config_set(unit, port, direction, modulo)); 4205 4206 exit: 4207 SOC_FUNC_RETURN; 4208 4209 } 4210 4211 int cpm4x25_1588_timestamp_cmic_config_get(int unit, int port, pm_info_t pm_info, portmod_direction_t direction, uint16* modulo) 4212 { 4213 SOC_INIT_FUNC_DEFS; 4214 _SOC_IF_ERR_EXIT(cprimod_1588_timestamp_cmic_config_get(unit, port, direction, modulo)); 4215 4216 exit: 4217 SOC_FUNC_RETURN; 4218 4219 } 4220 4221 int cpm4x25_port_vcos_get(int unit, int port, pm_info_t pm_info, const portmod_vcos_speed_config_t* speed_config_list, int size, portmod_dual_vcos_t* dual_vco) 4222 { 4223 int index = 0; 4224 int index_enet = 0; 4225 int vco = 0; 4226 int vco0 = 0; 4227 int vco1 = 0; 4228 portmod_vcos_speed_config_t vcos_speed_config[4]; 4229 SOC_INIT_FUNC_DEFS; 4230 if (size == 0) return SOC_E_NONE; 4231 for (index = 0; index < size; index++){ 4232 if ((speed_config_list[index].port_type == portmodCpmPrtEthOfMixedMode) || 4233 (speed_config_list[index].port_type == portmodCpmPrtEthMode)) { 4234 sal_memcpy(&vcos_speed_config[index_enet], &speed_config_list[index], sizeof(portmod_vcos_speed_config_t)); 4235 index_enet++; 4236 } else { 4237 switch(speed_config_list[index].port_type) { 4238 case portmodCpmPrtRsvd4Mode: 4239 if ((vco0 == 0) || (vco0 == phymod_TSCF_PLL_DIV200)) { 4240 vco0=phymod_TSCF_PLL_DIV200; 4241 } else if ((vco1 == 0) || (vco1 == phymod_TSCF_PLL_DIV200)) { 4242 vco1=phymod_TSCF_PLL_DIV200; 4243 } else { 4244 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, "fail to get vcos -- no vco matches lane %d speed %d\n"), 4245 speed_config_list[index].num_lanes, speed_config_list[index].speed)); 4246 return SOC_E_PARAM; 4247 } 4248 break; 4249 case portmodCpmPrtRsvd4OfMixedMode: 4250 if ((vco0 == 0) || (vco0 == phymod_TSCF_PLL_DIV200)) { 4251 vco0=phymod_TSCF_PLL_DIV200; 4252 } else { 4253 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, "fail to get vcos -- no vco matches lane %d speed %d\n"), 4254 speed_config_list[index].num_lanes, speed_config_list[index].speed)); 4255 return SOC_E_PARAM; 4256 } 4257 break; 4258 case portmodCpmPrtCpriMode: 4259 vco = _cprimod_port_speed_id_to_vco(speed_config_list[index].speed, _SHR_PORT_ENCAP_CPRI); 4260 if ((vco0 == 0) || (vco0 == vco)) { 4261 vco0=vco; 4262 } else if ((vco1 == 0) || (vco1 == vco)) { 4263 vco1=vco; 4264 } else { 4265 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, "fail to get vcos -- no vco matches lane %d speed %d\n"), 4266 speed_config_list[index].num_lanes, speed_config_list[index].speed)); 4267 return SOC_E_PARAM; 4268 } 4269 break; 4270 case portmodCpmPrtCpriOfMixedMode: 4271 vco = _cprimod_port_speed_id_to_vco(speed_config_list[index].speed, _SHR_PORT_ENCAP_CPRI); 4272 if ((vco0 == 0) || (vco0 == vco)) { 4273 vco0=vco; 4274 } else { 4275 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, "fail to get vcos -- no vco matches lane %d speed %d\n"), 4276 speed_config_list[index].num_lanes, speed_config_list[index].speed)); 4277 return SOC_E_PARAM; 4278 } 4279 break; 4280 default: 4281 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, "fail to get vcos -- no vco matches lane %d speed %d\n"), 4282 speed_config_list[index].num_lanes, speed_config_list[index].speed)); 4283 return SOC_E_PARAM; 4284 break; 4285 } 4286 } 4287 } 4288 if(index_enet != 0) { 4289 _rv = pm4x25_port_vcos_get(unit, port, pm_info, vcos_speed_config, index_enet, dual_vco); 4290 } 4291 if(vco0 != 0) { 4292 dual_vco->vco_0 = vco0; 4293 } 4294 if(vco1 != 0) { 4295 dual_vco->vco_1 = vco1; 4296 } 4297 SOC_FUNC_RETURN; 4298 } 4299 4300 int cpm4x25_cpri_port_rx_agnostic_config_set (int unit, int port, pm_info_t pm_info, 4301 int enable, 4302 const portmod_cpri_rx_agnostic_config_info_t* config_info) 4303 { 4304 uint32 queue_num = 0xFF; 4305 uint32 frame_len =0; 4306 uint32 cw_len = 0; 4307 uint32 roe_packet_size; 4308 cprimod_cpri_container_config_t container_info; 4309 cprimod_payload_size_info_t roe_payload_info; 4310 cprimod_encap_decap_data_config_t encap_data_info; 4311 cprimod_encap_presentation_time_config_t presentation_config; 4312 cprimod_port_interface_config_t interface_config; 4313 int lane; 4314 phymod_phy_access_t phy_access; 4315 4316 SOC_INIT_FUNC_DEFS; 4317 4318 /* 4319 * Check to see if the port is in CPRI mode. 4320 * If not, return error. 4321 */ 4322 _SOC_IF_ERR_EXIT 4323 (cprimod_port_rx_interface_config_get(unit, port, &interface_config)); 4324 4325 if(interface_config.interface != cprimodCpri) { 4326 _SOC_EXIT_WITH_ERR 4327 (SOC_E_PARAM, ("Port is not in CPRI Mode.\n")); 4328 } 4329 4330 /* 4331 * Setup the basic frame. For both enable and disable 4332 */ 4333 4334 _SOC_IF_ERR_EXIT 4335 (cprimod_cpri_agnostic_mode_basic_frame_config_set(unit, port, CPRIMOD_DIR_RX, enable)); 4336 4337 _SOC_IF_ERR_EXIT 4338 (cprimod_cpri_basic_frame_info_get(unit, port, CPRIMOD_DIR_RX, &frame_len, &cw_len)); 4339 4340 if (enable) { 4341 /* Enable */ 4342 4343 if (SOC_E_NONE != cprimod_cpri_container_config_t_init(&container_info)) { 4344 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config_info initialization failed")); 4345 } 4346 4347 container_info.map_method = cprimod_cpri_frame_map_method_1; 4348 container_info.Naxc = frame_len-cw_len; 4349 container_info.K = 1; 4350 container_info.Nst = 0; 4351 container_info.Na = 0; 4352 container_info.Nc = 0; 4353 container_info.Nv = 0; 4354 container_info.frame_sync_mode = config_info->sync_mode; 4355 container_info.basic_frame_offset = config_info->basic_frame_offset; 4356 container_info.radio_frame_offset = config_info->radio_frame_offset; 4357 container_info.hyper_frame_offset = config_info->hyper_frame_offset; 4358 4359 _SOC_IF_ERR_EXIT 4360 (cprimod_cpri_rx_axc_container_config_set(unit, port, 0 /*Agnostic AxC*/ , &container_info)); 4361 4362 switch (config_info->payload_multiple) { 4363 case CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1X: 4364 roe_packet_size = frame_len ; 4365 break; 4366 4367 case CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1P5X: 4368 roe_packet_size = (frame_len*3) /2; 4369 break; 4370 4371 case CPRIMOD_CPRI_PAYLOAD_MULTIPLE_2X: 4372 roe_packet_size = frame_len * 2; 4373 break; 4374 4375 case CPRIMOD_CPRI_PAYLOAD_MULTIPLE_4X: 4376 roe_packet_size = frame_len * 4; 4377 break; 4378 4379 case CPRIMOD_CPRI_PAYLOAD_MULTIPLE_8X: 4380 roe_packet_size = frame_len * 8; 4381 break; 4382 default: 4383 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Not Supported Multiple..")); 4384 break; 4385 4386 } 4387 roe_payload_info.packet_size = roe_packet_size; 4388 roe_payload_info.last_packet_num = 0 ; /* not used. */ 4389 roe_payload_info.last_packet_size = roe_packet_size ; /* not used. */ 4390 4391 _SOC_IF_ERR_EXIT 4392 (cprimod_rx_roe_payload_size_set(unit, port, 0 /* agnostic axc */, &roe_payload_info)); 4393 4394 queue_num = 0; /* queue # is always 0 for agnostic. */ 4395 encap_data_info.sample_size = 8; 4396 encap_data_info.truncation_enable = 0; 4397 encap_data_info.truncation_type = 0; /* Not used */ 4398 encap_data_info.compression_type = cprimod_no_compress; 4399 encap_data_info.mux_enable = 0; 4400 encap_data_info.bit_reversal = 0; 4401 encap_data_info.buffer_size = (roe_packet_size/8) * 2 ; 4402 encap_data_info.priority = 0; 4403 encap_data_info.cycle_size = 0; 4404 encap_data_info.is_agnostic = 1; 4405 4406 _SOC_IF_ERR_EXIT 4407 (cprimod_cpri_encap_data_config_set(unit, port, queue_num, &encap_data_info )); 4408 4409 4410 _SOC_IF_ERR_EXIT 4411 (cprimod_encap_presentation_time_config_t_init(&presentation_config)); 4412 4413 presentation_config.mod_count = config_info->pres_mod_count; 4414 presentation_config.frame_sync_mode = config_info->sync_mode; 4415 presentation_config.radio_frame_offset = config_info->radio_frame_offset; 4416 presentation_config.hyper_frame_offset = config_info->hyper_frame_offset; 4417 presentation_config.approx_inc_disable = FALSE; 4418 4419 _SOC_IF_ERR_EXIT 4420 (cprimod_encap_presentation_time_config_set(unit, port, &presentation_config)); 4421 4422 if (config_info->ordering_info_option == PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP) { 4423 _SOC_IF_ERR_EXIT 4424 (cprimod_encap_presentation_time_enable_set(unit, port, TRUE)); 4425 } else { 4426 _SOC_IF_ERR_EXIT 4427 (cprimod_encap_presentation_time_enable_set(unit, port, FALSE)); 4428 } 4429 4430 } else { 4431 _SOC_IF_ERR_EXIT 4432 (cprimod_encap_presentation_time_enable_set(unit, port, FALSE)); 4433 4434 /* 4435 * retrieve the interface information and restore. 4436 */ 4437 4438 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 4439 lane = (SOC_INFO(unit).port_l2p_mapping[port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 4440 phy_access.access.lane_mask = (1<<lane); 4441 4442 _SOC_IF_ERR_EXIT 4443 (cprimod_port_rx_interface_config_set(unit, port, &phy_access, &interface_config)); 4444 } 4445 4446 /* 4447 * Activate the basic frame 4448 */ 4449 4450 _SOC_IF_ERR_EXIT 4451 (cpm4x25_cpri_port_stage_activate(unit, port, pm_info, portmodCpriStageRx)); 4452 4453 exit: 4454 SOC_FUNC_RETURN; 4455 4456 } 4457 4458 int cpm4x25_cpri_port_rx_agnostic_config_get (int unit, int port, pm_info_t pm_info, 4459 int *enable, 4460 portmod_cpri_rx_agnostic_config_info_t* config_info) 4461 { 4462 uint32 frame_len; 4463 uint32 cw_len; 4464 uint32 frame_multiple; 4465 cprimod_cpri_container_config_t container_info; 4466 cprimod_payload_size_info_t roe_payload_info; 4467 cprimod_encap_presentation_time_config_t presentation_config; 4468 cprimod_agnostic_mode_type_t mode; 4469 int presentation_enable=0; 4470 4471 SOC_INIT_FUNC_DEFS; 4472 4473 4474 4475 _SOC_IF_ERR_EXIT 4476 (cprimod_cpri_port_rx_agnostic_mode_get(unit, port, enable, &mode)); 4477 4478 if (*enable && (mode == cprimod_agnostic_mode_cpri)) { 4479 4480 /* 4481 * if enabled, get the rest of the information. 4482 */ 4483 4484 _SOC_IF_ERR_EXIT 4485 (cprimod_encap_presentation_time_enable_get(unit, port, &presentation_enable)); 4486 4487 if (presentation_enable) { 4488 config_info->ordering_info_option = PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP; 4489 } else { 4490 config_info->ordering_info_option = PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_SEQ_NUM; 4491 } 4492 4493 _SOC_IF_ERR_EXIT 4494 (cprimod_cpri_basic_frame_info_get(unit, port, CPRIMOD_DIR_RX, &frame_len, &cw_len)); 4495 4496 _SOC_IF_ERR_EXIT 4497 (cprimod_rx_roe_payload_size_get(unit, port, 0 /*agnostic AxC */, &roe_payload_info)); 4498 4499 4500 _SOC_IF_ERR_EXIT 4501 (cprimod_cpri_rx_axc_container_config_get(unit, port, 0 /*agnostic axc */, &container_info)); 4502 4503 _SOC_IF_ERR_EXIT 4504 (cprimod_encap_presentation_time_config_get(unit, port, &presentation_config)); 4505 4506 4507 4508 /* to accomodate 1.5, do calculation on twice the value. */ 4509 frame_multiple = (roe_payload_info.packet_size*2)/frame_len; 4510 4511 switch (frame_multiple) { 4512 case 2: 4513 config_info->payload_multiple = CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1X; 4514 break; 4515 case 3: 4516 config_info->payload_multiple = CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1P5X; 4517 break; 4518 case 4: 4519 config_info->payload_multiple = CPRIMOD_CPRI_PAYLOAD_MULTIPLE_2X; 4520 break; 4521 case 8: 4522 config_info->payload_multiple = CPRIMOD_CPRI_PAYLOAD_MULTIPLE_4X; 4523 break; 4524 case 16: 4525 config_info->payload_multiple = CPRIMOD_CPRI_PAYLOAD_MULTIPLE_8X; 4526 break; 4527 default: 4528 break; 4529 } 4530 4531 config_info->sync_mode = container_info.frame_sync_mode; 4532 config_info->radio_frame_offset = container_info.radio_frame_offset; 4533 config_info->hyper_frame_offset = container_info.hyper_frame_offset; 4534 config_info->basic_frame_offset = container_info.basic_frame_offset; 4535 config_info->pres_mod_count = presentation_config.mod_count; 4536 } else { 4537 *enable = 0; 4538 /* 4539 * if disabled, zero out all the parameters. 4540 */ 4541 _SOC_IF_ERR_EXIT 4542 (portmod_cpri_rx_agnostic_config_info_t_init(unit, config_info)); 4543 config_info->ordering_info_option = 0; 4544 config_info->sync_mode = 0; 4545 } 4546 exit: 4547 SOC_FUNC_RETURN; 4548 } 4549 4550 int cpm4x25_cpri_port_tx_agnostic_config_set (int unit, int port, pm_info_t pm_info, 4551 int enable, 4552 const portmod_cpri_tx_agnostic_config_info_t* config_info) 4553 { 4554 uint32 queue_num = 0xFF; 4555 uint32 frame_len =0; 4556 uint32 cw_len = 0; 4557 uint32 roe_packet_size; 4558 cprimod_cpri_container_config_t container_info; 4559 cprimod_payload_size_info_t roe_payload_info; 4560 cprimod_encap_decap_data_config_t decap_data_info; 4561 cprimod_decap_agnostic_mode_config_t agnostic_config; 4562 cprimod_port_interface_config_t interface_config; 4563 4564 SOC_INIT_FUNC_DEFS; 4565 4566 /* 4567 * Check to see if the port is in CPRI mode. 4568 * If not, return error. 4569 */ 4570 _SOC_IF_ERR_EXIT 4571 (cprimod_port_tx_interface_config_get(unit, port, &interface_config)); 4572 4573 if(interface_config.interface != cprimodCpri) { 4574 _SOC_EXIT_WITH_ERR 4575 (SOC_E_PARAM, ("Port is not in CPRI Mode.\n")); 4576 } 4577 4578 _SOC_IF_ERR_EXIT 4579 (cprimod_cpri_basic_frame_info_get(unit, port, CPRIMOD_DIR_TX, &frame_len, &cw_len)); 4580 4581 /* 4582 * Program Basic Frame Assembler. 4583 */ 4584 4585 _SOC_IF_ERR_EXIT 4586 (cprimod_cpri_agnostic_mode_basic_frame_config_set(unit, port, CPRIMOD_DIR_TX, enable)); 4587 4588 if (enable ) { 4589 if (SOC_E_NONE != cprimod_cpri_container_config_t_init(&container_info)) { 4590 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config_info initialization failed")); 4591 } 4592 4593 container_info.map_method = cprimod_cpri_frame_map_method_1; 4594 container_info.Naxc = frame_len; 4595 container_info.K = 1; 4596 container_info.Nst = 0; 4597 container_info.Na = 0; 4598 container_info.Nc = 0; 4599 container_info.Nv = 0; 4600 container_info.frame_sync_mode = config_info->sync_mode; 4601 container_info.basic_frame_offset = config_info->basic_frame_offset; 4602 container_info.radio_frame_offset = config_info->radio_frame_offset; 4603 container_info.hyper_frame_offset = config_info->hyper_frame_offset; 4604 4605 _SOC_IF_ERR_EXIT 4606 (cprimod_cpri_tx_axc_container_config_set(unit, port, 0, &container_info)); 4607 4608 switch (config_info->payload_multiple) { 4609 case CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1X: 4610 roe_packet_size = frame_len ; 4611 break; 4612 4613 case CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1P5X: 4614 roe_packet_size = (frame_len*3) /2; 4615 break; 4616 4617 case CPRIMOD_CPRI_PAYLOAD_MULTIPLE_2X: 4618 roe_packet_size = frame_len * 2; 4619 break; 4620 4621 case CPRIMOD_CPRI_PAYLOAD_MULTIPLE_4X: 4622 roe_packet_size = frame_len * 4; 4623 break; 4624 4625 case CPRIMOD_CPRI_PAYLOAD_MULTIPLE_8X: 4626 roe_packet_size = frame_len * 8; 4627 break; 4628 4629 default: 4630 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("Not Supported Multiple..")); 4631 break; 4632 4633 } 4634 roe_payload_info.packet_size = roe_packet_size; 4635 roe_payload_info.last_packet_num = 0 ; /* not used. */ 4636 roe_payload_info.last_packet_size = roe_packet_size ; /* not used. */ 4637 4638 _SOC_IF_ERR_EXIT 4639 (cprimod_tx_roe_payload_size_set(unit, port, 0, &roe_payload_info)); 4640 4641 queue_num = 0; /* queue # is always 0 for agnostic. */ 4642 decap_data_info.sample_size = 8; 4643 decap_data_info.truncation_enable = 0; 4644 decap_data_info.truncation_type = 0; /* Not used */ 4645 decap_data_info.compression_type = cprimod_no_compress; 4646 decap_data_info.mux_enable = 0; 4647 decap_data_info.bit_reversal = 0; 4648 decap_data_info.buffer_size = roe_packet_size/8 ; 4649 decap_data_info.priority = 0; 4650 /* 4651 * This cycle size not used in agnostic, 4652 * it is configured in cprimod_decap_agnostic_mode_config_set 4653 * instead. 4654 */ 4655 decap_data_info.cycle_size = 0; 4656 decap_data_info.is_agnostic = 1; 4657 4658 _SOC_IF_ERR_EXIT 4659 (cprimod_cpri_decap_data_config_set(unit, port, queue_num, &decap_data_info )); 4660 4661 _SOC_IF_ERR_EXIT 4662 (cprimod_decap_agnostic_mode_config_t_init(&agnostic_config)); 4663 4664 agnostic_config.mod_count = config_info->queue_mod_count; /* cycle size */ 4665 agnostic_config.packet_size = roe_packet_size/8 ; 4666 agnostic_config.queue_num = queue_num; 4667 4668 _SOC_IF_ERR_EXIT 4669 (cprimod_decap_agnostic_mode_config_set(unit, port, &agnostic_config)); 4670 4671 _SOC_IF_ERR_EXIT 4672 (cprimod_decap_presentation_time_config_set(unit, port, config_info->pres_mod_offset, config_info->pres_mod_count)); 4673 } 4674 4675 /* 4676 * enable/disable as well as setting the timestamp or seq_num. 4677 */ 4678 4679 _SOC_IF_ERR_EXIT 4680 (cprimod_decap_agnostic_mode_enable_set(unit, port, enable, config_info->ordering_info_option)); 4681 4682 4683 /* 4684 * Activate the basic frame 4685 */ 4686 4687 _SOC_IF_ERR_EXIT 4688 (cpm4x25_cpri_port_stage_activate(unit, port, pm_info, portmodCpriStageTx)); 4689 4690 4691 exit: 4692 SOC_FUNC_RETURN; 4693 4694 } 4695 4696 int cpm4x25_cpri_port_tx_agnostic_config_get (int unit, int port, pm_info_t pm_info, 4697 int* enable, 4698 portmod_cpri_tx_agnostic_config_info_t* config_info) 4699 { 4700 uint32 frame_multiple; 4701 uint32 frame_len; 4702 uint32 cw_len; 4703 cprimod_cpri_container_config_t container_info; 4704 cprimod_payload_size_info_t roe_payload_info; 4705 cprimod_decap_agnostic_mode_config_t agnostic_config; 4706 cprimod_cpri_roe_ordering_info_option_t mode; 4707 4708 SOC_INIT_FUNC_DEFS; 4709 4710 _SOC_IF_ERR_EXIT 4711 (cprimod_cpri_basic_frame_info_get(unit, port, CPRIMOD_DIR_TX, &frame_len, &cw_len)); 4712 4713 _SOC_IF_ERR_EXIT 4714 (cprimod_decap_agnostic_mode_enable_get(unit, port, enable, &mode)); 4715 4716 if (*enable) { 4717 /* 4718 * if enabled, get the rest of the information. 4719 */ 4720 config_info->ordering_info_option = mode; 4721 4722 _SOC_IF_ERR_EXIT 4723 (cprimod_cpri_tx_axc_container_config_get(unit, port, 0, &container_info)); 4724 4725 config_info->sync_mode = container_info.frame_sync_mode ; 4726 config_info->basic_frame_offset = container_info.basic_frame_offset; 4727 config_info->radio_frame_offset = container_info.radio_frame_offset; 4728 config_info->hyper_frame_offset = container_info.hyper_frame_offset; 4729 4730 _SOC_IF_ERR_EXIT 4731 (cprimod_tx_roe_payload_size_get(unit, port, 0, &roe_payload_info)); 4732 4733 /* 4734 * calculate the double value to accomodate 1.5x case. 4735 */ 4736 frame_multiple = (roe_payload_info.packet_size *2)/frame_len; 4737 4738 switch (frame_multiple) { 4739 case 2: 4740 config_info->payload_multiple = CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1X; 4741 break; 4742 case 3: 4743 config_info->payload_multiple = CPRIMOD_CPRI_PAYLOAD_MULTIPLE_1P5X; 4744 break; 4745 case 4: 4746 config_info->payload_multiple = CPRIMOD_CPRI_PAYLOAD_MULTIPLE_2X; 4747 break; 4748 case 8: 4749 config_info->payload_multiple = CPRIMOD_CPRI_PAYLOAD_MULTIPLE_4X; 4750 break; 4751 case 16: 4752 config_info->payload_multiple = CPRIMOD_CPRI_PAYLOAD_MULTIPLE_8X; 4753 break; 4754 default: 4755 break; 4756 } 4757 _SOC_IF_ERR_EXIT 4758 (cprimod_decap_agnostic_mode_config_get(unit, port, &agnostic_config)); 4759 4760 config_info->queue_mod_count = agnostic_config.mod_count; 4761 4762 _SOC_IF_ERR_EXIT 4763 (cprimod_decap_presentation_time_config_get(unit, port, &config_info->pres_mod_offset, &config_info->pres_mod_count)); 4764 } else { 4765 /* 4766 * if disabled, zero out the parameters. 4767 */ 4768 _SOC_IF_ERR_EXIT 4769 (portmod_cpri_tx_agnostic_config_info_t_init(unit,config_info)); 4770 config_info->ordering_info_option = 0; 4771 config_info->sync_mode = 0; 4772 } 4773 4774 exit: 4775 SOC_FUNC_RETURN; 4776 } 4777 4778 int cpm4x25_cpri_port_encap_presentation_time_config_set (int unit, int port, pm_info_t pm_info, 4779 portmod_presentation_time_attribute_t attribute, 4780 portmod_presentation_time_t* time) 4781 { 4782 uint32 time_value; 4783 SOC_INIT_FUNC_DEFS; 4784 4785 time_value = time->time; 4786 switch (attribute) { 4787 case PORTMOD_ENCAP_PRESENTATION_TIME_ADJUST: 4788 _SOC_IF_ERR_EXIT 4789 (cprimod_encap_presentation_time_adjust_set(unit, port, time_value)); 4790 break; 4791 case PORTMOD_ENCAP_PRESENTATION_APPRIOX_INC: 4792 _SOC_IF_ERR_EXIT 4793 (cprimod_encap_presentation_time_approximate_increment_set(unit, port, time_value)); 4794 break; 4795 default: 4796 break; 4797 } 4798 exit: 4799 SOC_FUNC_RETURN; 4800 } 4801 4802 int cpm4x25_cpri_port_encap_presentation_time_config_get (int unit, int port, pm_info_t pm_info, 4803 portmod_presentation_time_attribute_t attribute, 4804 portmod_presentation_time_t* time) 4805 { 4806 uint32 time_value; 4807 SOC_INIT_FUNC_DEFS; 4808 4809 switch (attribute) { 4810 case PORTMOD_ENCAP_PRESENTATION_TIME_ADJUST: 4811 _SOC_IF_ERR_EXIT 4812 (cprimod_encap_presentation_time_adjust_get(unit, port, &time_value)); 4813 break; 4814 case PORTMOD_ENCAP_PRESENTATION_APPRIOX_INC: 4815 _SOC_IF_ERR_EXIT 4816 (cprimod_encap_presentation_time_approximate_increment_get(unit, port, &time_value)); 4817 break; 4818 default: 4819 break; 4820 } 4821 time->time = time_value; 4822 exit: 4823 SOC_FUNC_RETURN; 4824 } 4825 4826 int cpm4x25_cpri_port_decap_presentation_time_config_set (int unit, int port, pm_info_t pm_info, 4827 const portmod_decap_presentation_time_config_t* config) 4828 { 4829 SOC_INIT_FUNC_DEFS; 4830 4831 _SOC_IF_ERR_EXIT 4832 (cprimod_decap_presentation_time_config_set(unit, port, config->time_mod_offset, config->mod_count)); 4833 4834 exit: 4835 SOC_FUNC_RETURN; 4836 } 4837 4838 int cpm4x25_cpri_port_decap_presentation_time_config_get (int unit, int port, pm_info_t pm_info, 4839 portmod_decap_presentation_time_config_t* config) 4840 { 4841 SOC_INIT_FUNC_DEFS; 4842 4843 _SOC_IF_ERR_EXIT 4844 (cprimod_decap_presentation_time_config_get(unit, port, &(config->time_mod_offset), &(config->mod_count))); 4845 4846 exit: 4847 SOC_FUNC_RETURN; 4848 } 4849 4850 #ifdef CPRIMOD_SUPPORT 4851 int cpm4x25_cpri_port_compression_lookup_table_set(int unit, int port, pm_info_t pm_info, int table_depth, const uint32* table) 4852 { 4853 SOC_INIT_FUNC_DEFS; 4854 4855 _SOC_IF_ERR_EXIT 4856 (cprimod_compression_lookup_table_set(unit, port, table_depth, table)); 4857 4858 exit: 4859 SOC_FUNC_RETURN; 4860 4861 } 4862 4863 #endif /* CPRIMOD_SUPPORT */ 4864 #ifdef CPRIMOD_SUPPORT 4865 int cpm4x25_cpri_port_compression_lookup_table_get(int unit, int port, pm_info_t pm_info, int max_depth, int* table_depth, uint32* table) 4866 { 4867 SOC_INIT_FUNC_DEFS; 4868 4869 _SOC_IF_ERR_EXIT 4870 (cprimod_compression_lookup_table_get(unit, port, max_depth, table_depth, table)); 4871 4872 exit: 4873 SOC_FUNC_RETURN; 4874 4875 } 4876 4877 #endif /* CPRIMOD_SUPPORT */ 4878 4879 #ifdef CPRIMOD_SUPPORT 4880 int cpm4x25_cpri_port_decompression_lookup_table_set(int unit, int port, pm_info_t pm_info, int table_depth, const uint32* table) 4881 { 4882 SOC_INIT_FUNC_DEFS; 4883 _SOC_IF_ERR_EXIT 4884 (cprimod_decompression_lookup_table_set(unit, port, table_depth, table)); 4885 4886 exit: 4887 SOC_FUNC_RETURN; 4888 4889 } 4890 4891 #endif /* CPRIMOD_SUPPORT */ 4892 #ifdef CPRIMOD_SUPPORT 4893 int cpm4x25_cpri_port_decompression_lookup_table_get(int unit, int port, pm_info_t pm_info, int max_depth, int* table_depth, uint32* table) 4894 { 4895 SOC_INIT_FUNC_DEFS; 4896 4897 _SOC_IF_ERR_EXIT 4898 (cprimod_decompression_lookup_table_get(unit, port, max_depth, table_depth, table)); 4899 exit: 4900 SOC_FUNC_RETURN; 4901 4902 } 4903 4904 #endif /* CPRIMOD_SUPPORT */ 4905 #ifdef CPRIMOD_SUPPORT 4906 int cpm4x25_cpri_port_decap_queue_flow_control_set(int unit, int port, pm_info_t pm_info, uint32 queue_num, int enable, uint32_t xon_threshold, uint32_t xoff_threshold) 4907 { 4908 SOC_INIT_FUNC_DEFS; 4909 4910 _SOC_IF_ERR_EXIT 4911 (cprimod_cpri_port_decap_queue_flow_control_set(unit, port, 4912 queue_num, 4913 enable, 4914 xon_threshold, 4915 xoff_threshold)); 4916 exit: 4917 SOC_FUNC_RETURN; 4918 4919 } 4920 4921 #endif /* CPRIMOD_SUPPORT */ 4922 #ifdef CPRIMOD_SUPPORT 4923 int cpm4x25_cpri_port_decap_queue_flow_control_get(int unit, int port, pm_info_t pm_info, uint32 queue_num, int* enable, uint32_t* xon_threshold, uint32_t* xoff_threshold) 4924 { 4925 SOC_INIT_FUNC_DEFS; 4926 4927 _SOC_IF_ERR_EXIT 4928 (cprimod_cpri_port_decap_queue_flow_control_get(unit, port, 4929 queue_num, 4930 enable, 4931 xon_threshold, 4932 xoff_threshold)); 4933 exit: 4934 SOC_FUNC_RETURN; 4935 4936 } 4937 4938 #endif /* CPRIMOD_SUPPORT */ 4939 4940 #ifdef CPRIMOD_SUPPORT 4941 int cpm4x25_cpri_port_fec_enable_set(int unit, int port, pm_info_t pm_info, portmod_direction_t dir, int enable) 4942 { 4943 SOC_INIT_FUNC_DEFS; 4944 _SOC_IF_ERR_EXIT(cprimod_cpri_port_fec_enable_set(unit, port, dir, enable)); 4945 exit: 4946 SOC_FUNC_RETURN; 4947 } 4948 #endif /* CPRIMOD_SUPPORT */ 4949 4950 #ifdef CPRIMOD_SUPPORT 4951 int cpm4x25_cpri_port_fec_enable_get(int unit, int port, pm_info_t pm_info, portmod_direction_t dir, int* enable) 4952 { 4953 SOC_INIT_FUNC_DEFS; 4954 _SOC_IF_ERR_EXIT(cprimod_cpri_port_fec_enable_get(unit, port, dir, enable)); 4955 exit: 4956 SOC_FUNC_RETURN; 4957 } 4958 #endif /* CPRIMOD_SUPPORT */ 4959 4960 #ifdef CPRIMOD_SUPPORT 4961 int cpm4x25_cpri_port_fec_timestamp_config_set(int unit, int port, pm_info_t pm_info, portmod_direction_t dir, const portmod_fec_timestamp_config_t* config) 4962 { 4963 cprimod_fec_timestamp_config_t cfg; 4964 SOC_INIT_FUNC_DEFS; 4965 4966 cprimod_fec_timestamp_config_t_init(&cfg); 4967 cfg.enable = config->enable; 4968 cfg.control_bit_offset_0 = config->control_bit_offset_0; 4969 cfg.control_bit_offset_1 = config->control_bit_offset_1; 4970 cfg.control_bit_offset_2 = config->control_bit_offset_2; 4971 cfg.control_bit_offset_3 = config->control_bit_offset_3; 4972 cfg.fec_fifo_ts_source_select = config->fec_fifo_ts_source_select; 4973 cfg.fec_cmic_ts_source_select = config->fec_cmic_ts_source_select; 4974 _SOC_IF_ERR_EXIT(cprimod_cpri_port_fec_timestamp_config_set(unit, port, dir, &cfg)); 4975 exit: 4976 SOC_FUNC_RETURN; 4977 } 4978 #endif /* CPRIMOD_SUPPORT */ 4979 4980 #ifdef CPRIMOD_SUPPORT 4981 int cpm4x25_cpri_port_fec_timestamp_config_get(int unit, int port, pm_info_t pm_info, portmod_direction_t dir, portmod_fec_timestamp_config_t* config) 4982 { 4983 cprimod_fec_timestamp_config_t cfg; 4984 SOC_INIT_FUNC_DEFS; 4985 4986 cprimod_fec_timestamp_config_t_init(&cfg); 4987 _SOC_IF_ERR_EXIT(cprimod_cpri_port_fec_timestamp_config_get(unit, port, dir, &cfg)); 4988 config->enable = cfg.enable; 4989 config->control_bit_offset_0 = cfg.control_bit_offset_0; 4990 config->control_bit_offset_1 = cfg.control_bit_offset_1; 4991 config->control_bit_offset_2 = cfg.control_bit_offset_2; 4992 config->control_bit_offset_3 = cfg.control_bit_offset_3; 4993 config->fec_fifo_ts_source_select = cfg.fec_fifo_ts_source_select; 4994 config->fec_cmic_ts_source_select = cfg.fec_cmic_ts_source_select; 4995 exit: 4996 SOC_FUNC_RETURN; 4997 } 4998 #endif /* CPRIMOD_SUPPORT */ 4999 5000 #ifdef CPRIMOD_SUPPORT 5001 int cpm4x25_cpri_port_fec_aux_config_set(int unit, int port, pm_info_t pm_info, portmod_fec_aux_config_para_t parameter_id, uint32 value) 5002 { 5003 SOC_INIT_FUNC_DEFS; 5004 _SOC_IF_ERR_EXIT(cprimod_cpri_port_fec_aux_config_set(unit, port, parameter_id, value)); 5005 exit: 5006 SOC_FUNC_RETURN; 5007 } 5008 #endif /* CPRIMOD_SUPPORT */ 5009 5010 #ifdef CPRIMOD_SUPPORT 5011 int cpm4x25_cpri_port_fec_aux_config_get(int unit, int port, pm_info_t pm_info, portmod_fec_aux_config_para_t parameter_id, uint32* value) 5012 { 5013 SOC_INIT_FUNC_DEFS; 5014 _SOC_IF_ERR_EXIT(cprimod_cpri_port_fec_aux_config_get(unit, port, parameter_id, value)); 5015 exit: 5016 SOC_FUNC_RETURN; 5017 } 5018 #endif /* CPRIMOD_SUPPORT */ 5019 5020 int cpm4x25_port_timesync_enable_set(int unit, int port, pm_info_t pm_info, uint32 enable) 5021 { 5022 int val; 5023 5024 SOC_INIT_FUNC_DEFS; 5025 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 5026 if(val == 0) { 5027 _SOC_IF_ERR_EXIT(pm4x25_port_timesync_enable_set(unit, port, pm_info, enable)); 5028 } else { 5029 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 5030 (_SOC_MSG("Can't operate timesync on CRPI port %d"), port)); 5031 } 5032 5033 exit: 5034 SOC_FUNC_RETURN; 5035 } 5036 5037 int cpm4x25_port_timesync_enable_get(int unit, int port, pm_info_t pm_info, uint32* enable) 5038 { 5039 int val; 5040 5041 SOC_INIT_FUNC_DEFS; 5042 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 5043 if(val == 0) { 5044 _SOC_IF_ERR_EXIT(pm4x25_port_timesync_enable_get(unit, port, pm_info, enable)); 5045 } else { 5046 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 5047 (_SOC_MSG("Can't operate timesync on CRPI port %d"), port)); 5048 } 5049 5050 exit: 5051 SOC_FUNC_RETURN; 5052 } 5053 5054 int cpm4x25_port_timesync_config_set(int unit, int port, pm_info_t pm_info, const portmod_phy_timesync_config_t* config) 5055 { 5056 int val; 5057 5058 SOC_INIT_FUNC_DEFS; 5059 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 5060 if(val == 0) { 5061 _SOC_IF_ERR_EXIT(pm4x25_port_timesync_config_set(unit, port, pm_info, config)); 5062 } else { 5063 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 5064 (_SOC_MSG("Can't operate timesync on CRPI port %d"), port)); 5065 } 5066 5067 exit: 5068 SOC_FUNC_RETURN; 5069 } 5070 5071 int cpm4x25_port_timesync_config_get(int unit, int port, pm_info_t pm_info, portmod_phy_timesync_config_t* config) 5072 { 5073 int val; 5074 5075 SOC_INIT_FUNC_DEFS; 5076 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 5077 if(val == 0) { 5078 _SOC_IF_ERR_EXIT(pm4x25_port_timesync_config_get(unit, port, pm_info, config)); 5079 } else { 5080 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 5081 (_SOC_MSG("Can't operate timesync on CRPI port %d"), port)); 5082 } 5083 5084 exit: 5085 SOC_FUNC_RETURN; 5086 } 5087 5088 int cpm4x25_port_control_phy_timesync_set(int unit, int port, pm_info_t pm_info, const portmod_port_control_phy_timesync_t config, uint64 value) 5089 { 5090 int val; 5091 5092 SOC_INIT_FUNC_DEFS; 5093 5094 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 5095 if(val == 0) { 5096 _SOC_IF_ERR_EXIT(pm4x25_port_control_phy_timesync_set(unit, port, pm_info, config, value)); 5097 } else { 5098 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 5099 (_SOC_MSG("Can't operate timesync on CRPI port %d"), port)); 5100 } 5101 5102 exit: 5103 SOC_FUNC_RETURN; 5104 } 5105 5106 int cpm4x25_port_control_phy_timesync_get(int unit, int port, pm_info_t pm_info, const portmod_port_control_phy_timesync_t config, uint64* value) 5107 { 5108 int val; 5109 5110 SOC_INIT_FUNC_DEFS; 5111 5112 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 5113 if(val == 0) { 5114 _SOC_IF_ERR_EXIT(pm4x25_port_control_phy_timesync_get(unit, port, pm_info, config, value)); 5115 } else { 5116 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 5117 (_SOC_MSG("Can't operate timesync on CRPI port %d"), port)); 5118 } 5119 5120 exit: 5121 SOC_FUNC_RETURN; 5122 } 5123 5124 5125 int cpm4x25_cpri_port_ecc_interrupt_enable_set(int unit, int port, 5126 int enable) 5127 { 5128 int val; 5129 SOC_INIT_FUNC_DEFS; 5130 5131 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 5132 5133 if(val) { 5134 _SOC_IF_ERR_EXIT(cprimod_cpri_port_ecc_interrupt_enable_set(unit, 5135 port, enable)); 5136 } else { 5137 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 5138 (_SOC_MSG("Can't operate timesync on Non-CRPI port %d"), port)); 5139 } 5140 5141 exit: 5142 SOC_FUNC_RETURN; 5143 } 5144 5145 5146 int cpm4x25_cpri_port_ecc_interrupt_status_get(int unit, int port, 5147 pm_info_t pm_info, 5148 portmod_cpri_ecc_intr_info_t* ecc_err_info) 5149 { 5150 int val; 5151 cprimod_cpri_ecc_intr_info_t *ecc_info = 5152 (cprimod_cpri_ecc_intr_info_t *) ecc_err_info; 5153 SOC_INIT_FUNC_DEFS; 5154 5155 _SOC_IF_ERR_EXIT(cprimod_cpri_or_enet_port_get(unit, port, &val)); 5156 5157 if(val) { 5158 _SOC_IF_ERR_EXIT(cprimod_cpri_port_ecc_interrupt_status_get(unit, 5159 port, ecc_info)); 5160 } else { 5161 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, 5162 (_SOC_MSG("Can't operate on Non-CRPI port %d"), port)); 5163 } 5164 5165 exit: 5166 SOC_FUNC_RETURN; 5167 } 5168 5169 int cpm4x25_cpri_init(int unit, int port, pm_info_t pm_info) 5170 { 5171 SOC_INIT_FUNC_DEFS; 5172 5173 _SOC_IF_ERR_EXIT(cprimod_cpri_init(unit, port)); 5174 5175 exit: 5176 SOC_FUNC_RETURN; 5177 } 5178 5179 int cpm4x25_cpri_port_rx_gcw_word_get(int unit, int port, pm_info_t pm_info, int group_index, uint16* gcw_word) 5180 { 5181 SOC_INIT_FUNC_DEFS; 5182 5183 _SOC_IF_ERR_EXIT 5184 (cprimod_cpri_port_rx_gcw_word_get(unit, port, group_index, gcw_word)); 5185 5186 exit: 5187 SOC_FUNC_RETURN; 5188 5189 } 5190 5191 int cpm4x25_cpri_port_tx_gcw_word_set(int unit, int port, pm_info_t pm_info, int group_index, uint16 gcw_word) 5192 { 5193 SOC_INIT_FUNC_DEFS; 5194 5195 _SOC_IF_ERR_EXIT 5196 (cprimod_cpri_port_tx_gcw_word_set(unit, port, group_index, gcw_word)); 5197 5198 exit: 5199 SOC_FUNC_RETURN; 5200 5201 } 5202 int cpm4x25_port_rx_mac_enable_set(int unit, int port, pm_info_t pm_info, int enable) 5203 { 5204 int roe_port=0; 5205 SOC_INIT_FUNC_DEFS; 5206 5207 _SOC_IF_ERR_EXIT 5208 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5209 if (roe_port) { 5210 /* RoE port */ 5211 _SOC_IF_ERR_EXIT 5212 (cprimod_cpri_port_rx_enable_set(unit, port, enable)); 5213 } else { 5214 /* Eth Port */ 5215 _SOC_IF_ERR_EXIT 5216 (pm4x25_port_rx_mac_enable_set(unit, port, pm_info, enable)); 5217 } 5218 exit: 5219 SOC_FUNC_RETURN; 5220 5221 } 5222 5223 int cpm4x25_port_rx_mac_enable_get(int unit, int port, pm_info_t pm_info, int* enable) 5224 { 5225 int roe_port=0; 5226 SOC_INIT_FUNC_DEFS; 5227 5228 _SOC_IF_ERR_EXIT 5229 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5230 if (roe_port) { 5231 /* RoE port */ 5232 _SOC_IF_ERR_EXIT 5233 (cprimod_cpri_port_rx_enable_get(unit, port, enable)); 5234 5235 } else { 5236 /* Eth Port */ 5237 _SOC_IF_ERR_EXIT 5238 (pm4x25_port_rx_mac_enable_get(unit, port, pm_info, enable)); 5239 } 5240 exit: 5241 SOC_FUNC_RETURN; 5242 } 5243 5244 int cpm4x25_port_tx_mac_enable_set(int unit, int port, pm_info_t pm_info, int enable) 5245 { 5246 int roe_port=0; 5247 SOC_INIT_FUNC_DEFS; 5248 5249 _SOC_IF_ERR_EXIT 5250 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5251 if (roe_port) { 5252 /* RoE port */ 5253 _SOC_IF_ERR_EXIT 5254 (cprimod_cpri_port_tx_enable_set(unit, port, enable)); 5255 5256 } else { 5257 /* Eth Port */ 5258 _SOC_IF_ERR_EXIT 5259 (pm4x25_port_tx_mac_enable_set(unit, port, pm_info, enable)); 5260 } 5261 exit: 5262 SOC_FUNC_RETURN; 5263 5264 } 5265 5266 int cpm4x25_port_tx_mac_enable_get(int unit, int port, pm_info_t pm_info, int* enable) 5267 { 5268 int roe_port=0; 5269 SOC_INIT_FUNC_DEFS; 5270 5271 _SOC_IF_ERR_EXIT 5272 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5273 if (roe_port) { 5274 /* RoE port */ 5275 _SOC_IF_ERR_EXIT 5276 (cprimod_cpri_port_tx_enable_get(unit, port, enable)); 5277 5278 } else { 5279 /* Eth Port */ 5280 _SOC_IF_ERR_EXIT 5281 (pm4x25_port_tx_mac_enable_get(unit, port, pm_info, enable)); 5282 } 5283 exit: 5284 SOC_FUNC_RETURN; 5285 5286 } 5287 5288 int cpm4x25_port_drain_cell_stop(int unit, int port, pm_info_t pm_info, const portmod_drain_cells_t* drain_cells) 5289 { 5290 int roe_port=0; 5291 SOC_INIT_FUNC_DEFS; 5292 5293 _SOC_IF_ERR_EXIT 5294 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5295 if (roe_port) { 5296 /* RoE port */ 5297 _SOC_IF_ERR_EXIT 5298 (cprimod_cpri_mac_drain_stop(unit, port)); 5299 5300 } else { 5301 /* Eth Port */ 5302 _SOC_IF_ERR_EXIT 5303 (pm4x25_port_drain_cell_stop(unit, port, pm_info, drain_cells)); 5304 } 5305 exit: 5306 SOC_FUNC_RETURN; 5307 5308 } 5309 5310 int cpm4x25_port_drain_cell_start(int unit, int port, pm_info_t pm_info) 5311 { 5312 int roe_port=0; 5313 SOC_INIT_FUNC_DEFS; 5314 5315 _SOC_IF_ERR_EXIT 5316 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5317 if (roe_port) { 5318 /* RoE port */ 5319 _SOC_IF_ERR_EXIT 5320 (cprimod_cpri_mac_drain_start(unit, port)); 5321 } else { 5322 /* Eth Port */ 5323 _SOC_IF_ERR_EXIT 5324 (pm4x25_port_drain_cell_start(unit, port, pm_info)); 5325 } 5326 exit: 5327 SOC_FUNC_RETURN; 5328 5329 } 5330 5331 int cpm4x25_port_mac_reset_set(int unit, int port, pm_info_t pm_info, int val) 5332 { 5333 int roe_port=0; 5334 SOC_INIT_FUNC_DEFS; 5335 5336 _SOC_IF_ERR_EXIT 5337 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5338 if (roe_port) { 5339 /* RoE port */ 5340 _SOC_IF_ERR_EXIT 5341 (cprimod_cpri_mac_credit_reset_set(unit, port, val)); 5342 } else { 5343 /* Eth Port */ 5344 _SOC_IF_ERR_EXIT 5345 (pm4x25_port_mac_reset_set(unit, port, pm_info, val)); 5346 } 5347 exit: 5348 SOC_FUNC_RETURN; 5349 5350 } 5351 5352 int cpm4x25_port_mac_reset_get(int unit, int port, pm_info_t pm_info, int* val) 5353 { 5354 int roe_port=0; 5355 SOC_INIT_FUNC_DEFS; 5356 5357 _SOC_IF_ERR_EXIT 5358 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5359 if (roe_port) { 5360 /* RoE port */ 5361 _SOC_IF_ERR_EXIT 5362 (cprimod_cpri_mac_credit_reset_get(unit, port, val)); 5363 } else { 5364 /* Eth Port */ 5365 _SOC_IF_ERR_EXIT 5366 (pm4x25_port_mac_reset_get(unit, port, pm_info, val)); 5367 } 5368 exit: 5369 SOC_FUNC_RETURN; 5370 } 5371 5372 int cpm4x25_port_mac_reset_check(int unit, int port, pm_info_t pm_info, int enable, int* reset) 5373 { 5374 int roe_port=0; 5375 int rx_en=0; 5376 int tx_en=0; 5377 int soft_reset=0; 5378 SOC_INIT_FUNC_DEFS; 5379 5380 _SOC_IF_ERR_EXIT 5381 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5382 if (roe_port) { 5383 /* RoE port */ 5384 *reset = 1; 5385 _SOC_IF_ERR_EXIT 5386 (cprimod_cpri_port_rx_enable_get(unit, port, &rx_en)); 5387 _SOC_IF_ERR_EXIT 5388 (cprimod_cpri_port_tx_enable_get(unit, port, &tx_en)); 5389 5390 if ((rx_en == enable) && (tx_en == enable)){ 5391 if (enable) { 5392 *reset = 0; 5393 } else { 5394 _SOC_IF_ERR_EXIT 5395 (cprimod_cpri_mac_credit_reset_get(unit, port, &soft_reset)); 5396 if (soft_reset) { 5397 *reset = 0; 5398 } 5399 } 5400 } 5401 } else { 5402 /* Eth Port */ 5403 _SOC_IF_ERR_EXIT 5404 (pm4x25_port_mac_reset_check(unit, port, pm_info, enable, reset)); 5405 } 5406 5407 5408 exit: 5409 SOC_FUNC_RETURN; 5410 5411 } 5412 5413 int cpm4x25_port_tx_down(int unit, int port, pm_info_t pm_info) 5414 { 5415 int roe_port=0; 5416 SOC_INIT_FUNC_DEFS; 5417 5418 _SOC_IF_ERR_EXIT 5419 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5420 if (roe_port) { 5421 /* RoE port */ 5422 _SOC_IF_ERR_EXIT 5423 (cprimod_cpri_mac_credit_reset_set(unit, port, 1)); 5424 } else { 5425 /* Eth Port */ 5426 _SOC_IF_ERR_EXIT 5427 (pm4x25_port_tx_down(unit, port, pm_info)); 5428 } 5429 5430 exit: 5431 SOC_FUNC_RETURN; 5432 5433 } 5434 5435 int cpm4x25_port_drain_cells_rx_enable(int unit, int port, pm_info_t pm_info, int rx_en) 5436 { 5437 int roe_port=0; 5438 SOC_INIT_FUNC_DEFS; 5439 5440 _SOC_IF_ERR_EXIT 5441 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5442 if (roe_port) { 5443 /* RoE port */ 5444 _SOC_IF_ERR_EXIT 5445 (cprimod_cpri_port_tx_enable_set(unit, port, 1)); 5446 _SOC_IF_ERR_EXIT 5447 (cprimod_cpri_port_rx_enable_set(unit, port, rx_en)); 5448 /* if rx_enable , remove mac_soft_reset() */ 5449 if (rx_en) { 5450 _SOC_IF_ERR_EXIT 5451 (cprimod_cpri_mac_credit_reset_set(unit, port, 0)); 5452 } 5453 5454 } else { 5455 /* Eth Port */ 5456 _SOC_IF_ERR_EXIT 5457 (pm4x25_port_drain_cells_rx_enable(unit, port, pm_info, rx_en)); 5458 } 5459 exit: 5460 SOC_FUNC_RETURN; 5461 5462 } 5463 5464 int cpm4x25_port_egress_queue_drain_rx_en(int unit, int port, pm_info_t pm_info, int rx_en) 5465 { 5466 int roe_port=0; 5467 SOC_INIT_FUNC_DEFS; 5468 5469 _SOC_IF_ERR_EXIT 5470 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5471 if (roe_port) { 5472 /* RoE port */ 5473 _SOC_IF_ERR_EXIT 5474 (cprimod_cpri_port_rx_enable_set(unit, port, rx_en)); 5475 5476 _SOC_IF_ERR_EXIT 5477 (cprimod_cpri_mac_credit_reset_set(unit, port, 0)); 5478 5479 } else { 5480 /* Eth Port */ 5481 _SOC_IF_ERR_EXIT 5482 (pm4x25_port_egress_queue_drain_rx_en(unit, port, pm_info, rx_en)); 5483 } 5484 exit: 5485 SOC_FUNC_RETURN; 5486 5487 } 5488 5489 int cpm4x25_port_mac_ctrl_set(int unit, int port, pm_info_t pm_info, uint64 ctrl) 5490 { 5491 int roe_port=0; 5492 SOC_INIT_FUNC_DEFS; 5493 5494 _SOC_IF_ERR_EXIT 5495 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5496 if (roe_port) { 5497 /* RoE port */ 5498 /* do nothing. */ 5499 } else { 5500 /* Eth Port */ 5501 _SOC_IF_ERR_EXIT 5502 (pm4x25_port_mac_ctrl_set(unit, port, pm_info, ctrl)); 5503 } 5504 5505 exit: 5506 SOC_FUNC_RETURN; 5507 5508 } 5509 5510 int cpm4x25_port_egress_queue_drain_get(int unit, int port, pm_info_t pm_info, uint64* ctrl, int* rxen) 5511 { 5512 int roe_port=0; 5513 SOC_INIT_FUNC_DEFS; 5514 _SOC_IF_ERR_EXIT 5515 (cprimod_cpri_or_enet_port_get(unit, port, &roe_port)); 5516 if (roe_port) { 5517 /* RoE port */ 5518 _SOC_IF_ERR_EXIT 5519 (cprimod_cpri_port_rx_enable_get(unit, port, rxen)); 5520 } else { 5521 /* Eth Port */ 5522 _SOC_IF_ERR_EXIT 5523 (pm4x25_port_egress_queue_drain_get(unit, port, pm_info, ctrl, rxen)); 5524 } 5525 5526 exit: 5527 SOC_FUNC_RETURN; 5528 5529 } 5530 5531 int cpm4x25_cpri_port_rx_tunnel_mode_config_set(int unit, int port, pm_info_t pm_info, int enable, 5532 const portmod_cpri_rx_tunnel_mode_config_t* config_info) 5533 { 5534 uint32 queue_num = 0xFF; 5535 uint32 roe_payload_size; 5536 cprimod_cpri_container_config_t container_info; 5537 cprimod_payload_size_info_t roe_payload_info; 5538 cprimod_encap_decap_data_config_t encap_data_info; 5539 cprimod_encap_presentation_time_config_t presentation_config; 5540 int is_10bit_mode; 5541 cprimod_port_interface_config_t interface_config; 5542 int lane; 5543 phymod_phy_access_t phy_access; 5544 cprimod_port_rsvd4_speed_mult_t rsvd4_speed; 5545 5546 SOC_INIT_FUNC_DEFS; 5547 5548 roe_payload_size = config_info->payload_size * 8; /* convert the bytes to bits. */ 5549 5550 /* 5551 * Setup Port PCS in Tunnel Mode. 5552 */ 5553 _SOC_IF_ERR_EXIT 5554 (cprimod_cpri_port_rx_tunnel_mode_set(unit, port, enable, config_info->payload_size)); 5555 5556 /* 5557 * Setup the basic frame and framer. For both enable and disable 5558 */ 5559 _SOC_IF_ERR_EXIT 5560 (cprimod_cpri_tunnel_mode_basic_frame_config_set(unit, port, CPRIMOD_DIR_RX, enable)); 5561 5562 if (enable) { 5563 /* Enable */ 5564 _SOC_IF_ERR_EXIT 5565 (cprimod_cpri_interface_bus_width_get(unit, port, &is_10bit_mode)); 5566 5567 if (SOC_E_NONE != cprimod_cpri_container_config_t_init(&container_info)) { 5568 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config_info initialization failed")); 5569 } 5570 5571 container_info.map_method = cprimod_cpri_frame_map_method_1; 5572 container_info.Naxc = is_10bit_mode ? 10:40; 5573 container_info.K = 1; 5574 container_info.Nst = 0; 5575 container_info.Na = 0; 5576 container_info.Nc = 0; 5577 container_info.Nv = 0; 5578 container_info.frame_sync_mode = PORTMOD_CPRI_FRAME_SYNC_MODE_TUNNEL; 5579 container_info.basic_frame_offset = 0; 5580 container_info.radio_frame_offset = 0; 5581 container_info.hyper_frame_offset = 0; 5582 5583 _SOC_IF_ERR_EXIT 5584 (cprimod_cpri_rx_axc_container_config_set(unit, port, CPRIMOD_AXC_ID_AGNOSTIC , &container_info)); 5585 5586 5587 roe_payload_info.packet_size = roe_payload_size; 5588 roe_payload_info.last_packet_num = 0 ; /* not used. */ 5589 roe_payload_info.last_packet_size = roe_payload_size ; /* not used. */ 5590 5591 _SOC_IF_ERR_EXIT 5592 (cprimod_rx_roe_payload_size_set(unit, port, CPRIMOD_AXC_ID_AGNOSTIC, &roe_payload_info)); 5593 5594 queue_num = 0; /* queue # is always 0 for agnostic. */ 5595 encap_data_info.sample_size = 8; 5596 encap_data_info.truncation_enable = 0; 5597 encap_data_info.truncation_type = 0; /* Not used */ 5598 encap_data_info.compression_type = cprimod_no_compress; 5599 encap_data_info.mux_enable = 0; 5600 encap_data_info.bit_reversal = 0; 5601 encap_data_info.buffer_size = (roe_payload_size/8) * 2 ; 5602 encap_data_info.priority = 0; 5603 encap_data_info.cycle_size = 0; 5604 encap_data_info.is_agnostic = 1; 5605 5606 _SOC_IF_ERR_EXIT 5607 (cprimod_cpri_encap_data_config_set(unit, port, queue_num, &encap_data_info )); 5608 5609 5610 _SOC_IF_ERR_EXIT 5611 (cprimod_encap_presentation_time_config_t_init(&presentation_config)); 5612 5613 presentation_config.mod_count = config_info->pres_mod_count; 5614 presentation_config.frame_sync_mode = PORTMOD_CPRI_FRAME_SYNC_MODE_TUNNEL; 5615 presentation_config.radio_frame_offset = 0; 5616 presentation_config.hyper_frame_offset = 0; 5617 presentation_config.approx_inc_disable = TRUE; 5618 5619 _SOC_IF_ERR_EXIT 5620 (cprimod_encap_presentation_time_config_set(unit, port, &presentation_config)); 5621 5622 if (config_info->ordering_info_option == PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP) { 5623 _SOC_IF_ERR_EXIT 5624 (cprimod_encap_presentation_time_enable_set(unit, port, TRUE)); 5625 } else { 5626 _SOC_IF_ERR_EXIT 5627 (cprimod_encap_presentation_time_enable_set(unit, port, FALSE)); 5628 } 5629 5630 _SOC_IF_ERR_EXIT 5631 (cprimod_basic_frame_parser_switch_active_table(unit, port)); 5632 5633 } else { /* Disable */ 5634 /* Disable need to turn off presentation time. */ 5635 _SOC_IF_ERR_EXIT 5636 (cprimod_encap_presentation_time_enable_set(unit, port, FALSE)); 5637 5638 /* 5639 * retrieve the interface information and restore. 5640 */ 5641 5642 _SOC_IF_ERR_EXIT 5643 (cprimod_port_rx_interface_config_get(unit, port, &interface_config)); 5644 5645 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 5646 lane = (SOC_INFO(unit).port_l2p_mapping[port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 5647 phy_access.access.lane_mask = (1<<lane); 5648 5649 if(interface_config.interface == cprimodCpri) { 5650 _SOC_IF_ERR_EXIT 5651 (cprimod_port_rx_interface_config_set(unit, port, &phy_access, &interface_config)); 5652 5653 _SOC_IF_ERR_EXIT 5654 (cpm4x25_cpri_port_stage_activate(unit, port, pm_info, portmodCpriStageRx)); 5655 5656 } else if(interface_config.interface == cprimodRsvd4) { 5657 if(interface_config.speed == cprimodSpd3072p0){ 5658 rsvd4_speed = cprimodRsvd4SpdMult4X; 5659 } else if (interface_config.speed == cprimodSpd6144p0) { 5660 rsvd4_speed = cprimodRsvd4SpdMult8X; 5661 } else { 5662 _SOC_EXIT_WITH_ERR 5663 (SOC_E_PARAM, ("RSVD4 Unsupported Speed Detected.")); 5664 } 5665 _SOC_IF_ERR_EXIT 5666 (cprimod_port_rsvd4_rx_speed_set(unit, port, &phy_access, rsvd4_speed)); 5667 5668 _SOC_IF_ERR_EXIT 5669 (cprimod_basic_frame_parser_switch_active_table(unit, port)); 5670 5671 } 5672 } 5673 5674 exit: 5675 SOC_FUNC_RETURN; 5676 5677 } 5678 5679 int cpm4x25_cpri_port_rx_tunnel_mode_config_get(int unit, int port, pm_info_t pm_info, int* enable, portmod_cpri_rx_tunnel_mode_config_t* config_info) 5680 { 5681 int pcs_tunnel_mode_enable = 0; 5682 uint32 roe_payload_size; 5683 int presentation_enable =0; 5684 cprimod_encap_presentation_time_config_t presentation_config; 5685 SOC_INIT_FUNC_DEFS; 5686 5687 _SOC_IF_ERR_EXIT 5688 (cprimod_cpri_port_rx_tunnel_mode_get(unit, port, &pcs_tunnel_mode_enable, &roe_payload_size)); 5689 5690 if (pcs_tunnel_mode_enable) { 5691 5692 /* 5693 * if enabled, get the rest of the information. 5694 */ 5695 *enable = TRUE; 5696 config_info->payload_size = roe_payload_size; 5697 5698 /* get presenation time configuration. */ 5699 5700 _SOC_IF_ERR_EXIT 5701 (cprimod_encap_presentation_time_enable_get(unit, port, &presentation_enable)); 5702 5703 _SOC_IF_ERR_EXIT 5704 (cprimod_encap_presentation_time_config_t_init(&presentation_config)); 5705 5706 _SOC_IF_ERR_EXIT 5707 (cprimod_encap_presentation_time_config_get(unit, port, &presentation_config)); 5708 5709 config_info->pres_mod_count = presentation_config.mod_count; 5710 5711 if (presentation_enable) { 5712 config_info->ordering_info_option = PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP; 5713 } else { 5714 config_info->ordering_info_option = PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_SEQ_NUM; 5715 } 5716 } else { /* DISABLED */ 5717 *enable = FALSE; 5718 config_info->ordering_info_option = 0; 5719 } 5720 exit: 5721 SOC_FUNC_RETURN; 5722 5723 } 5724 5725 int cpm4x25_cpri_port_tx_tunnel_mode_config_set(int unit, int port, pm_info_t pm_info, int enable, const portmod_cpri_tx_tunnel_mode_config_t* config_info) 5726 { 5727 uint32 queue_num = 0xFF; 5728 uint32 roe_payload_size; 5729 cprimod_cpri_container_config_t container_info; 5730 cprimod_payload_size_info_t roe_payload_info; 5731 cprimod_encap_decap_data_config_t decap_data_info; 5732 cprimod_decap_agnostic_mode_config_t agnostic_config; 5733 uint32 divider=1; 5734 uint32 frame_tick=0; 5735 uint32 tick_bitmap=0; 5736 uint32 tick_bitmap_size=0; 5737 cprimod_port_interface_config_t interface_config; 5738 5739 SOC_INIT_FUNC_DEFS; 5740 5741 roe_payload_size = config_info->payload_size * 8; 5742 5743 /* 5744 * Setup Port PCS in Tunnel Mode. 5745 */ 5746 5747 _SOC_IF_ERR_EXIT 5748 (cprimod_cpri_port_tx_agnostic_mode_set(unit, port, enable, 5749 cprimod_agnostic_mode_tunnel, 5750 config_info->payload_size)); 5751 5752 /* 5753 * Program Basic Frame Assembler. 5754 */ 5755 5756 _SOC_IF_ERR_EXIT 5757 (cprimod_cpri_tunnel_mode_basic_frame_config_set(unit, port, CPRIMOD_DIR_TX, enable)); 5758 5759 if (enable ) { 5760 if (SOC_E_NONE != cprimod_cpri_container_config_t_init(&container_info)) { 5761 _SOC_EXIT_WITH_ERR(SOC_E_PARAM, ("config_info initialization failed")); 5762 } 5763 5764 container_info.map_method = cprimod_cpri_frame_map_method_1; 5765 container_info.Naxc = 40; /* hard coded to 40 bits. */ 5766 container_info.K = 1; 5767 container_info.Nst = 0; 5768 container_info.Na = 0; 5769 container_info.Nc = 0; 5770 container_info.Nv = 0; 5771 container_info.frame_sync_mode = PORTMOD_CPRI_FRAME_SYNC_MODE_TUNNEL; 5772 container_info.basic_frame_offset = 0; 5773 container_info.radio_frame_offset = 0; 5774 container_info.hyper_frame_offset = 0; 5775 5776 _SOC_IF_ERR_EXIT 5777 (cprimod_cpri_tx_axc_container_config_set(unit, port, 0, &container_info)); 5778 5779 roe_payload_info.packet_size = roe_payload_size; 5780 roe_payload_info.last_packet_num = 0 ; /* not used. */ 5781 roe_payload_info.last_packet_size = roe_payload_size ; /* not used. */ 5782 5783 _SOC_IF_ERR_EXIT 5784 (cprimod_tx_roe_payload_size_set(unit, port, 0, &roe_payload_info)); 5785 5786 queue_num = CPRIMOD_AXC_ID_AGNOSTIC; /* queue # is always 0 for agnostic. */ 5787 decap_data_info.sample_size = 8; 5788 decap_data_info.truncation_enable = 0; 5789 decap_data_info.truncation_type = 0; /* Not used */ 5790 decap_data_info.compression_type = cprimod_no_compress; 5791 decap_data_info.mux_enable = 0; 5792 decap_data_info.bit_reversal = 0; 5793 decap_data_info.buffer_size = roe_payload_size/8 ; 5794 decap_data_info.priority = 0; 5795 /* 5796 * This cycle size not used in agnostic, 5797 * it is configured in cprimod_decap_agnostic_mode_config_set 5798 * instead. 5799 */ 5800 decap_data_info.cycle_size = 0; 5801 decap_data_info.is_agnostic = 1; 5802 5803 _SOC_IF_ERR_EXIT 5804 (cprimod_cpri_decap_data_config_set(unit, port, queue_num, &decap_data_info )); 5805 5806 _SOC_IF_ERR_EXIT 5807 (cprimod_decap_agnostic_mode_config_t_init(&agnostic_config)); 5808 5809 agnostic_config.mod_count = config_info->queue_mod_count; /* cycle size */ 5810 agnostic_config.packet_size = roe_payload_size/8 ; 5811 agnostic_config.queue_num = queue_num; 5812 5813 _SOC_IF_ERR_EXIT 5814 (cprimod_decap_agnostic_mode_config_set(unit, port, &agnostic_config)); 5815 5816 5817 _SOC_IF_ERR_EXIT 5818 (cprimod_decap_presentation_time_config_set(unit, port, config_info->pres_mod_offset, config_info->pres_mod_count)); 5819 5820 /* 5821 * Tunnel Mode Bit Block Event Generation. 5822 * This will set Assembly FIFO for CDC at 48 entries. 5823 */ 5824 5825 divider = 1; 5826 frame_tick = 48; /* CPRIF_TUNNEL_MODE_NUM_OF_BFA_ENTRIES */ 5827 tick_bitmap = 0; 5828 tick_bitmap_size = 0; 5829 5830 _SOC_IF_ERR_EXIT 5831 (cprimod_tx_framer_tgen_tick_set(unit, port, divider, frame_tick, tick_bitmap, tick_bitmap_size)); 5832 5833 _SOC_IF_ERR_EXIT 5834 (cprimod_basic_frame_assembly_switch_active_table(unit, port)); 5835 5836 } else { 5837 /* 5838 * retrieve the interface information and restore. 5839 */ 5840 5841 _SOC_IF_ERR_EXIT 5842 (cprimod_port_tx_interface_config_get(unit, port, &interface_config)); 5843 5844 if(interface_config.interface == cprimodCpri) { 5845 _SOC_IF_ERR_EXIT 5846 (cpm4x25_cpri_port_stage_activate(unit, port, pm_info, portmodCpriStageTx)); 5847 5848 } else if(interface_config.interface == cprimodRsvd4) { 5849 _SOC_IF_ERR_EXIT 5850 (cprimod_basic_frame_assembly_switch_active_table(unit, port)); 5851 } 5852 } 5853 5854 /* 5855 * enable/disable as well as setting the timestamp or seq_num. 5856 */ 5857 5858 _SOC_IF_ERR_EXIT 5859 (cprimod_decap_agnostic_mode_enable_set(unit, port, enable, config_info->ordering_info_option)); 5860 5861 /* 5862 * Activate the basic frame 5863 */ 5864 5865 5866 exit: 5867 SOC_FUNC_RETURN; 5868 5869 } 5870 5871 int cpm4x25_cpri_port_tx_tunnel_mode_config_get(int unit, int port, pm_info_t pm_info, int* enable, portmod_cpri_tx_tunnel_mode_config_t* config_info) 5872 { 5873 uint32 roe_payload_size; 5874 int agnostic_enable=FALSE; 5875 portmod_cpri_roe_ordering_info_option_t mode; 5876 cprimod_agnostic_mode_type_t agnostic_mode; 5877 cprimod_decap_agnostic_mode_config_t agnostic_config; 5878 SOC_INIT_FUNC_DEFS; 5879 5880 _SOC_IF_ERR_EXIT 5881 (cprimod_cpri_port_tx_agnostic_mode_get(unit, port, enable, &agnostic_mode, &roe_payload_size)); 5882 5883 if ( *enable && ( agnostic_mode == cprimod_agnostic_mode_tunnel)) { 5884 *enable = TRUE; 5885 } else { 5886 *enable = FALSE; 5887 } 5888 5889 config_info->payload_size = roe_payload_size; 5890 5891 if (*enable) { 5892 _SOC_IF_ERR_EXIT 5893 (cprimod_decap_agnostic_mode_enable_get(unit, port, &agnostic_enable, &mode)); 5894 5895 config_info->ordering_info_option = mode; 5896 5897 _SOC_IF_ERR_EXIT 5898 (cprimod_decap_agnostic_mode_config_get(unit, port, &agnostic_config)); 5899 5900 config_info->queue_mod_count = agnostic_config.mod_count ; 5901 5902 _SOC_IF_ERR_EXIT 5903 (cprimod_decap_presentation_time_config_get(unit, port, &config_info->pres_mod_offset, &config_info->pres_mod_count)); 5904 } 5905 exit: 5906 SOC_FUNC_RETURN; 5907 5908 } 5909 5910 int cpm4x25_rsvd4_port_rx_agnostic_config_set(int unit, int port, pm_info_t pm_info, int enable, const portmod_rsvd4_rx_agnostic_config_t* config_info) 5911 { 5912 uint32 queue_num = 0xFF; 5913 uint32 roe_payload_size; 5914 cprimod_rsvd4_container_config_t container_info; 5915 cprimod_payload_size_info_t roe_payload_info; 5916 cprimod_encap_decap_data_config_t encap_data_info; 5917 cprimod_encap_presentation_time_config_t presentation_config; 5918 cprimod_port_interface_config_t interface_config; 5919 int lane; 5920 cprimod_port_rsvd4_speed_mult_t rsvd4_speed; 5921 phymod_phy_access_t phy_access; 5922 5923 SOC_INIT_FUNC_DEFS; 5924 5925 /* 5926 * Check to see if the port is in RSVD4 mode. 5927 * If not, return error. 5928 */ 5929 _SOC_IF_ERR_EXIT 5930 (cprimod_port_rx_interface_config_get(unit, port, &interface_config)); 5931 5932 if(interface_config.interface != cprimodRsvd4) { 5933 _SOC_EXIT_WITH_ERR 5934 (SOC_E_PARAM, ("Port is not in RSVD4 Mode.\n")); 5935 } 5936 5937 /* 5938 * convert msg group multiple to bits. 5939 * Each Msg group has 19 bytes per msg * 21 msgs N_MG + 1 K)*8 5940 */ 5941 roe_payload_size = config_info->payload_multiple * 400 *8 ; 5942 5943 /* 5944 * Setup the basic frame. For both enable and disable 5945 */ 5946 _SOC_IF_ERR_EXIT 5947 (cprimod_rsvd4_agnostic_mode_basic_frame_config_set(unit, port, CPRIMOD_DIR_RX, enable)); 5948 5949 if (enable) { 5950 /* Enable */ 5951 5952 cprimod_rsvd4_container_config_t_init(&container_info); 5953 container_info.axc_id = CPRIMOD_AXC_ID_AGNOSTIC; 5954 container_info.stuffing_cnt = 0; 5955 container_info.msg_ts_mode = CPRIMOD_RSVD4_MSG_TS_MODE_WCDMA; /* No timestamp */ 5956 container_info.msg_ts_cnt = 0; /* No timestamp */ 5957 container_info.frame_sync_mode = config_info->frame_sync_mode; 5958 container_info.master_frame_offset = config_info->master_frame_offset; 5959 container_info.message_number_offset = config_info->message_group_number*21; 5960 container_info.container_block_cnt = 3200; /* 400 Bytes * 8 bits , MG size */ 5961 5962 _SOC_IF_ERR_EXIT 5963 (cprimod_rsvd4_rx_axc_container_config_set(unit, port, CPRIMOD_AXC_ID_AGNOSTIC, &container_info)); 5964 5965 roe_payload_info.packet_size = roe_payload_size; 5966 roe_payload_info.last_packet_num = 0 ; /* not used. */ 5967 roe_payload_info.last_packet_size = roe_payload_size ; /* not used. */ 5968 5969 _SOC_IF_ERR_EXIT 5970 (cprimod_rx_roe_payload_size_set(unit, port, CPRIMOD_AXC_ID_AGNOSTIC, &roe_payload_info)); 5971 5972 queue_num = 0; /* queue # is always 0 for agnostic. */ 5973 encap_data_info.sample_size = 8; 5974 encap_data_info.truncation_enable = 0; 5975 encap_data_info.truncation_type = 0; /* Not used */ 5976 encap_data_info.compression_type = cprimod_no_compress; 5977 encap_data_info.mux_enable = 0; 5978 encap_data_info.bit_reversal = TRUE; 5979 encap_data_info.buffer_size = (roe_payload_size/8) * 2 ; 5980 encap_data_info.priority = 0; 5981 encap_data_info.cycle_size = 0; 5982 encap_data_info.is_agnostic = 1; 5983 5984 _SOC_IF_ERR_EXIT 5985 (cprimod_cpri_encap_data_config_set(unit, port, queue_num, &encap_data_info )); 5986 5987 5988 _SOC_IF_ERR_EXIT 5989 (cprimod_encap_presentation_time_config_t_init(&presentation_config)); 5990 5991 if ((config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_NO_SYNC)|| 5992 (config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_NO_SYNC)) { 5993 5994 presentation_config.frame_sync_mode = CPRIMOD_CPRI_FRAME_SYNC_MODE_HYPER; 5995 5996 } else if ((config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_OFFSET)|| 5997 (config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_OFFSET)) { 5998 5999 presentation_config.frame_sync_mode = CPRIMOD_CPRI_FRAME_SYNC_MODE_RADIO; 6000 6001 } else if ((config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_AND_MASTER_OFFSET)|| 6002 (config_info->frame_sync_mode == CPRIMOD_RSVD4_FRAME_SYNC_MODE_TS_MSG_AND_MASTER_OFFSET)) { 6003 6004 presentation_config.frame_sync_mode = CPRIMOD_CPRI_FRAME_SYNC_MODE_BASIC; 6005 6006 } 6007 6008 presentation_config.mod_count = config_info->pres_mod_count; 6009 presentation_config.radio_frame_offset = config_info->master_frame_offset; 6010 presentation_config.hyper_frame_offset = config_info->message_group_number; 6011 presentation_config.approx_inc_disable = TRUE; 6012 6013 _SOC_IF_ERR_EXIT 6014 (cprimod_encap_presentation_time_config_set(unit, port, &presentation_config)); 6015 6016 if (config_info->ordering_info_option == PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP) { 6017 _SOC_IF_ERR_EXIT 6018 (cprimod_encap_presentation_time_enable_set(unit, port, TRUE)); 6019 } else { 6020 _SOC_IF_ERR_EXIT 6021 (cprimod_encap_presentation_time_enable_set(unit, port, FALSE)); 6022 } 6023 } else { /* Disable */ 6024 /* Disable need to turn off presentation time. */ 6025 _SOC_IF_ERR_EXIT 6026 (cprimod_encap_presentation_time_enable_set(unit, port, FALSE)); 6027 6028 if(interface_config.speed == cprimodSpd3072p0){ 6029 rsvd4_speed = cprimodRsvd4SpdMult4X; 6030 } else if (interface_config.speed == cprimodSpd6144p0) { 6031 rsvd4_speed = cprimodRsvd4SpdMult8X; 6032 } else { 6033 _SOC_EXIT_WITH_ERR 6034 (SOC_E_PARAM, ("RSVD4 Unsupported Speed Detected.")); 6035 } 6036 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 6037 lane = (SOC_INFO(unit).port_l2p_mapping[port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 6038 phy_access.access.lane_mask = (1<<lane); 6039 6040 _SOC_IF_ERR_EXIT 6041 (cprimod_port_rsvd4_rx_speed_set(unit, port, &phy_access, rsvd4_speed)); 6042 6043 } 6044 /* 6045 * Fwd Ildes to framer for rsvd4 agnostic mode. 6046 */ 6047 _SOC_IF_ERR_EXIT 6048 (cprimod_port_rsvd4_rx_frame_optional_config_set(unit, port, 6049 cprimodRsvd4RxConfigFwdIdlesToFramer, 6050 enable)); 6051 /* 6052 * Swtich the basic frame 6053 */ 6054 _SOC_IF_ERR_EXIT 6055 (cprimod_basic_frame_parser_switch_active_table(unit, port)); 6056 exit: 6057 SOC_FUNC_RETURN; 6058 } 6059 6060 int cpm4x25_rsvd4_port_rx_agnostic_config_get(int unit, int port, pm_info_t pm_info, int* enable, portmod_rsvd4_rx_agnostic_config_t* config_info) 6061 { 6062 cprimod_agnostic_mode_type_t mode; 6063 cprimod_payload_size_info_t roe_payload_info; 6064 int presentation_enable =0; 6065 cprimod_encap_presentation_time_config_t presentation_config; 6066 SOC_INIT_FUNC_DEFS; 6067 6068 _SOC_IF_ERR_EXIT 6069 (cprimod_cpri_port_rx_agnostic_mode_get(unit, port, enable, &mode)); 6070 6071 if (*enable && (mode == cprimod_agnostic_mode_rsvd4)) { 6072 /* 6073 * if enabled in rsvd4 mode, get the rest of the information. 6074 */ 6075 6076 _SOC_IF_ERR_EXIT 6077 (cprimod_rx_roe_payload_size_get(unit, port, CPRIMOD_AXC_ID_AGNOSTIC, &roe_payload_info)); 6078 6079 /* 6080 * convert packet size in bits to mutliple of message group. 6081 * 400 bytes per msg grp 6082 */ 6083 config_info->payload_multiple = roe_payload_info.packet_size/3200; 6084 6085 /* get presenation time configuration. */ 6086 6087 _SOC_IF_ERR_EXIT 6088 (cprimod_encap_presentation_time_enable_get(unit, port, &presentation_enable)); 6089 6090 _SOC_IF_ERR_EXIT 6091 (cprimod_encap_presentation_time_config_t_init(&presentation_config)); 6092 6093 _SOC_IF_ERR_EXIT 6094 (cprimod_encap_presentation_time_config_get(unit, port, &presentation_config)); 6095 6096 config_info->pres_mod_count = presentation_config.mod_count; 6097 config_info->master_frame_offset = presentation_config.radio_frame_offset; 6098 config_info->message_group_number = presentation_config.hyper_frame_offset; 6099 6100 if (presentation_config.frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_HYPER) { 6101 config_info->frame_sync_mode = CPRIMOD_RSVD4_FRAME_SYNC_MODE_NO_SYNC; 6102 } else if (presentation_config.frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_RADIO) { 6103 config_info->frame_sync_mode = CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_OFFSET; 6104 } else if (presentation_config.frame_sync_mode == CPRIMOD_CPRI_FRAME_SYNC_MODE_BASIC) { 6105 config_info->frame_sync_mode = CPRIMOD_RSVD4_FRAME_SYNC_MODE_MSG_AND_MASTER_OFFSET; 6106 } 6107 6108 if (presentation_enable) { 6109 config_info->ordering_info_option = PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP; 6110 6111 } else { 6112 config_info->ordering_info_option = PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_SEQ_NUM; 6113 } 6114 } else { /* DISABLED */ 6115 *enable = FALSE; 6116 config_info->ordering_info_option = 0; 6117 } 6118 exit: 6119 SOC_FUNC_RETURN; 6120 } 6121 6122 int cpm4x25_rsvd4_port_tx_agnostic_config_set(int unit, int port, pm_info_t pm_info, int enable, const portmod_rsvd4_tx_agnostic_config_t* config_info) 6123 { 6124 uint32 queue_num = 0xFF; 6125 uint32 roe_payload_size; 6126 cprimod_rsvd4_container_config_t container_info; 6127 cprimod_payload_size_info_t roe_payload_info; 6128 cprimod_encap_decap_data_config_t decap_data_info; 6129 cprimod_decap_agnostic_mode_config_t agnostic_config; 6130 cprimod_port_interface_config_t interface_config; 6131 int lane; 6132 cprimod_port_rsvd4_speed_mult_t rsvd4_speed; 6133 phymod_phy_access_t phy_access; 6134 SOC_INIT_FUNC_DEFS; 6135 6136 /* 6137 * Check to see if the port is in RSVD4 mode. 6138 * If not, return error. 6139 */ 6140 _SOC_IF_ERR_EXIT 6141 (cprimod_port_tx_interface_config_get(unit, port, &interface_config)); 6142 6143 if(interface_config.interface != cprimodRsvd4) { 6144 _SOC_EXIT_WITH_ERR 6145 (SOC_E_PARAM, ("Port is not in RSVD4 Mode.\n")); 6146 } 6147 6148 roe_payload_size = config_info->payload_multiple * 400 *8 ; 6149 6150 /* 6151 * Setup Port PCS in Agnostic Mode. 6152 */ 6153 6154 _SOC_IF_ERR_EXIT 6155 (cprimod_cpri_port_tx_agnostic_mode_set(unit, port, enable, 6156 cprimod_agnostic_mode_rsvd4, 6157 roe_payload_size)); 6158 /* 6159 * Program Basic Frame Assembler. 6160 */ 6161 6162 _SOC_IF_ERR_EXIT 6163 (cprimod_rsvd4_agnostic_mode_basic_frame_config_set(unit, port, CPRIMOD_DIR_TX, enable)); 6164 6165 if (enable) { 6166 6167 cprimod_rsvd4_container_config_t_init(&container_info); 6168 container_info.axc_id = CPRIMOD_AXC_ID_AGNOSTIC; 6169 container_info.stuffing_cnt = 0; 6170 container_info.msg_ts_mode = CPRIMOD_RSVD4_MSG_TS_MODE_WCDMA; /* No timestamp */ 6171 container_info.msg_ts_cnt = 0; /* No timestamp */ 6172 container_info.frame_sync_mode = config_info->frame_sync_mode; 6173 container_info.master_frame_offset = config_info->master_frame_offset; 6174 container_info.message_number_offset = config_info->message_group_number*21; 6175 container_info.container_block_cnt = 3200; /* 400 Bytes * 8 bits , MG size */ 6176 container_info.use_ts_dbm = FALSE; 6177 container_info.msg_addr = 0; 6178 container_info.msg_type = 0; 6179 container_info.msg_ts_offset = 0; 6180 6181 _SOC_IF_ERR_EXIT 6182 (cprimod_rsvd4_tx_axc_container_config_set(unit, port, CPRIMOD_AXC_ID_AGNOSTIC, &container_info)); 6183 6184 roe_payload_info.packet_size = roe_payload_size; 6185 roe_payload_info.last_packet_num = 0 ; /* not used. */ 6186 roe_payload_info.last_packet_size = roe_payload_size ; /* not used. */ 6187 6188 _SOC_IF_ERR_EXIT 6189 (cprimod_tx_roe_payload_size_set(unit, port, 0, &roe_payload_info)); 6190 6191 queue_num = CPRIMOD_AXC_ID_AGNOSTIC; /* queue # is always 0 for agnostic. */ 6192 decap_data_info.sample_size = 8; 6193 decap_data_info.truncation_enable = 0; 6194 decap_data_info.truncation_type = 0; /* Not used */ 6195 decap_data_info.compression_type = cprimod_no_compress; 6196 decap_data_info.mux_enable = 0; 6197 decap_data_info.bit_reversal = 0; 6198 decap_data_info.buffer_size = roe_payload_size/8 ; 6199 decap_data_info.priority = 0; 6200 /* 6201 * This cycle size not used in agnostic, 6202 * it is configured in cprimod_decap_agnostic_mode_config_set 6203 * instead. 6204 */ 6205 decap_data_info.cycle_size = 0; 6206 decap_data_info.is_agnostic = 1; 6207 6208 _SOC_IF_ERR_EXIT 6209 (cprimod_cpri_decap_data_config_set(unit, port, queue_num, &decap_data_info)); 6210 6211 _SOC_IF_ERR_EXIT 6212 (cprimod_decap_agnostic_mode_config_t_init(&agnostic_config)); 6213 6214 agnostic_config.mod_count = config_info->queue_mod_count; /* cycle size */ 6215 agnostic_config.packet_size = roe_payload_size/8 ; 6216 agnostic_config.queue_num = queue_num; 6217 6218 _SOC_IF_ERR_EXIT 6219 (cprimod_decap_agnostic_mode_config_set(unit, port, &agnostic_config)); 6220 6221 _SOC_IF_ERR_EXIT 6222 (cprimod_decap_presentation_time_config_set(unit, port, config_info->pres_mod_offset, config_info->pres_mod_count)); 6223 6224 /* 6225 * set padding size to 0. 6226 */ 6227 _SOC_IF_ERR_EXIT 6228 (cprimod_rsvd4_tx_padding_size_set(unit, port, 0)); 6229 6230 } else { 6231 6232 if(interface_config.speed == cprimodSpd3072p0){ 6233 rsvd4_speed = cprimodRsvd4SpdMult4X; 6234 } else if (interface_config.speed == cprimodSpd6144p0) { 6235 rsvd4_speed = cprimodRsvd4SpdMult8X; 6236 } else { 6237 _SOC_EXIT_WITH_ERR 6238 (SOC_E_PARAM, ("RSVD4 Unsupported Speed Detected.")); 6239 } 6240 sal_memcpy(&phy_access, &(PM_4x25_INFO(pm_info)->int_core_access), sizeof(phymod_core_access_t)); 6241 lane = (SOC_INFO(unit).port_l2p_mapping[port]-1)%CPRIMOD_MAX_LANES_PER_CORE; 6242 phy_access.access.lane_mask = (1<<lane); 6243 6244 _SOC_IF_ERR_EXIT 6245 (cprimod_port_rsvd4_tx_speed_set(unit, port, &phy_access, rsvd4_speed)); 6246 } 6247 6248 /* 6249 * enable/disable as well as setting the timestamp or seq_num. 6250 */ 6251 6252 _SOC_IF_ERR_EXIT 6253 (cprimod_decap_agnostic_mode_enable_set(unit, port, enable, config_info->ordering_info_option)); 6254 6255 /* 6256 * switch the basic frame active table. 6257 */ 6258 _SOC_IF_ERR_EXIT 6259 (cprimod_basic_frame_assembly_switch_active_table(unit, port)); 6260 6261 exit: 6262 SOC_FUNC_RETURN; 6263 6264 } 6265 6266 int cpm4x25_rsvd4_port_tx_agnostic_config_get(int unit, int port, pm_info_t pm_info, int* enable, portmod_rsvd4_tx_agnostic_config_t* config_info) 6267 { 6268 cprimod_agnostic_mode_type_t mode; 6269 uint32 tunnel_payload=0; 6270 cprimod_payload_size_info_t roe_payload_info; 6271 cprimod_rsvd4_container_config_t container_info; 6272 int presentation_enable =0; 6273 cprimod_decap_agnostic_mode_config_t agnostic_config; 6274 SOC_INIT_FUNC_DEFS; 6275 6276 _SOC_IF_ERR_EXIT 6277 (cprimod_cpri_port_tx_agnostic_mode_get(unit, port, enable, &mode, &tunnel_payload)); 6278 6279 if (*enable && (mode == cprimod_agnostic_mode_rsvd4)) { 6280 /* 6281 * if enabled in rsvd4 mode, get the rest of the information. 6282 */ 6283 6284 _SOC_IF_ERR_EXIT 6285 (cprimod_tx_roe_payload_size_get(unit, port, CPRIMOD_AXC_ID_AGNOSTIC, &roe_payload_info)); 6286 6287 /* 6288 * convert packet size in bits to mutliple of message group. 6289 * 400 bytes per msg grp 6290 */ 6291 config_info->payload_multiple = roe_payload_info.packet_size/3200; 6292 6293 _SOC_IF_ERR_EXIT 6294 (cprimod_rsvd4_tx_axc_container_config_get(unit, port, CPRIMOD_AXC_ID_AGNOSTIC, &container_info)); 6295 6296 config_info->frame_sync_mode = container_info.frame_sync_mode; 6297 config_info->master_frame_offset = container_info.master_frame_offset; 6298 config_info->message_group_number = container_info.message_number_offset/21; 6299 6300 _SOC_IF_ERR_EXIT 6301 (cprimod_decap_agnostic_mode_config_get(unit, port, &agnostic_config)); 6302 config_info->queue_mod_count = agnostic_config.mod_count; 6303 6304 6305 /* get presenation time configuration. */ 6306 6307 _SOC_IF_ERR_EXIT 6308 (cprimod_decap_agnostic_mode_enable_get(unit, port, &presentation_enable, &config_info->ordering_info_option)); 6309 6310 _SOC_IF_ERR_EXIT 6311 (cprimod_decap_presentation_time_config_get(unit, port, &config_info->pres_mod_offset, &config_info->pres_mod_count)); 6312 6313 } else { /* DISABLED */ 6314 *enable = FALSE; 6315 config_info->ordering_info_option = 0; 6316 } 6317 exit: 6318 SOC_FUNC_RETURN; 6319 6320 } 6321 6322 int cpm4x25_cpri_port_frame_config_set(int unit, int port, pm_info_t pm_info, const portmod_cpri_port_frame_config_t* config) 6323 { 6324 cprimod_cpri_encap_header_field_mapping_t encap_map; 6325 cprimod_cpri_decap_header_field_mapping_t decap_map; 6326 int len_field_adjust = 0; 6327 int ext_hdr_enable=0; 6328 SOC_INIT_FUNC_DEFS; 6329 6330 _SOC_IF_ERR_EXIT 6331 (cprimod_cpri_encap_header_field_mapping_t_init(&encap_map)); 6332 6333 _SOC_IF_ERR_EXIT 6334 (cprimod_cpri_decap_header_field_mapping_t_init(&decap_map)); 6335 6336 switch (config->frame_type) { 6337 6338 case PORTMOD_CPRI_ROE_FRAME_FORMAT_IEEE1914: 6339 case PORTMOD_CPRI_ROE_FRAME_FORMAT_RSVD3: 6340 6341 /* default mapping */ 6342 len_field_adjust = 0; 6343 ext_hdr_enable = FALSE; 6344 break; 6345 6346 case PORTMOD_CPRI_ROE_FRAME_FORMAT_ECPRI8: 6347 6348 /* Encap mapping */ 6349 encap_map.hdr_byte0_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_31_24; 6350 encap_map.hdr_byte1_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_OPCODE; 6351 encap_map.hdr_byte2_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_15_8; 6352 encap_map.hdr_byte3_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_7_0; 6353 encap_map.hdr_byte4_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_SUBTYPE; 6354 encap_map.hdr_byte5_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_FLOW_ID; 6355 encap_map.hdr_byte6_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_15_8; 6356 encap_map.hdr_byte7_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_7_0; 6357 6358 /* Decap Mapping */ 6359 decap_map.subtype_sel = config->decap_primary_key; 6360 decap_map.flowid_sel = config->decap_secondary_key; 6361 decap_map.length_15_8_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_2; 6362 decap_map.length_7_0_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_3; 6363 decap_map.orderinginfo_31_24_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_4; /* will masked off*/ 6364 decap_map.orderinginfo_23_16_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_5; /* will nasked off*/ 6365 decap_map.orderinginfo_15_8_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_6; 6366 decap_map.orderinginfo_7_0_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_7; 6367 6368 _SOC_IF_ERR_EXIT 6369 (cprimod_cpri_decap_header_field_mask_set( unit, port, 6370 CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_31_24, 6371 0x00)); 6372 _SOC_IF_ERR_EXIT 6373 (cprimod_cpri_decap_header_field_mask_set( unit, port, 6374 CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_23_16, 6375 0x00)); 6376 6377 /* 6378 * RoE length is IQ data only, does not include the common header. 6379 * eCPRI length include PC_ID and SEQ_ID. Add Length adjust on 6380 * encap side and subtract on decap side. 6381 */ 6382 len_field_adjust = 4; 6383 ext_hdr_enable = FALSE; 6384 break; 6385 6386 case PORTMOD_CPRI_ROE_FRAME_FORMAT_ECPRI12: 6387 6388 /* Encap mapping */ 6389 encap_map.hdr_byte0_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_31_24; 6390 encap_map.hdr_byte1_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_OPCODE; 6391 encap_map.hdr_byte2_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_15_8; 6392 encap_map.hdr_byte3_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_LENGTH_7_0; 6393 encap_map.hdr_byte4_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_UNMAPPED; 6394 encap_map.hdr_byte5_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_UNMAPPED; 6395 encap_map.hdr_byte6_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_SUBTYPE ; 6396 encap_map.hdr_byte7_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_FLOW_ID; 6397 encap_map.hdr_byte8_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_UNMAPPED; 6398 encap_map.hdr_byte9_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_23_16; 6399 encap_map.hdr_byte10_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_15_8; 6400 encap_map.hdr_byte11_sel = CPRIMOD_CPRI_ROE_HEADER_FIELD_ORDER_INFO_7_0; 6401 6402 /* Decap Mapping */ 6403 decap_map.subtype_sel = config->decap_primary_key; 6404 decap_map.flowid_sel = config->decap_secondary_key; 6405 decap_map.length_15_8_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_2; 6406 decap_map.length_7_0_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_3; 6407 decap_map.orderinginfo_31_24_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_8; 6408 decap_map.orderinginfo_23_16_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_9; 6409 decap_map.orderinginfo_15_8_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_10; 6410 decap_map.orderinginfo_7_0_sel = CPRIMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_11; 6411 6412 /* 6413 * RoE length is IQ data only, does not include the common header. 6414 * eCPRI length include PC_ID and SEQ_ID. Add Length adjust on 6415 * encap side and subtract on decap side. 6416 */ 6417 len_field_adjust = 8; 6418 ext_hdr_enable = TRUE; 6419 break; 6420 6421 default: 6422 _SOC_EXIT_WITH_ERR 6423 (SOC_E_PARAM, ("UnSupported Frame Format.")); 6424 6425 } 6426 6427 _SOC_IF_ERR_EXIT 6428 (cprimod_cpri_header_field_adjustment_config_set (unit, port, CPRIMOD_DIR_RX, ext_hdr_enable , len_field_adjust)); 6429 6430 _SOC_IF_ERR_EXIT 6431 (cprimod_cpri_header_field_adjustment_config_set (unit, port, CPRIMOD_DIR_TX, ext_hdr_enable , len_field_adjust*-1)); 6432 6433 _SOC_IF_ERR_EXIT 6434 (cprimod_cpri_encap_header_field_mapping_set(unit, port, &encap_map)); 6435 6436 _SOC_IF_ERR_EXIT 6437 (cprimod_cpri_decap_header_field_mapping_set(unit, port, &decap_map)); 6438 6439 exit: 6440 SOC_FUNC_RETURN; 6441 } 6442 6443 int cpm4x25_cpri_port_compression_saturation_config_set(int unit, int port, pm_info_t pm_info, uint32 threshold_value) 6444 { 6445 SOC_INIT_FUNC_DEFS; 6446 6447 _SOC_IF_ERR_EXIT 6448 (cprimod_cpri_port_compression_saturation_config_set(unit, port, threshold_value)); 6449 exit: 6450 SOC_FUNC_RETURN; 6451 6452 } 6453 6454 int cpm4x25_cpri_port_compression_saturation_config_get(int unit, int port, pm_info_t pm_info, uint32* threshold_value) 6455 { 6456 SOC_INIT_FUNC_DEFS; 6457 6458 _SOC_IF_ERR_EXIT 6459 (cprimod_cpri_port_compression_saturation_config_get(unit, port, threshold_value)); 6460 6461 6462 exit: 6463 SOC_FUNC_RETURN; 6464 6465 } 6466 6467 6468 int cpm4x25_cpri_port_decompression_saturation_config_set(int unit, int port, pm_info_t pm_info, uint32 sat_value) 6469 { 6470 SOC_INIT_FUNC_DEFS; 6471 6472 _SOC_IF_ERR_EXIT 6473 (cprimod_cpri_port_decompression_saturation_config_set(unit, port, sat_value)); 6474 6475 6476 exit: 6477 SOC_FUNC_RETURN; 6478 6479 } 6480 6481 int cpm4x25_cpri_port_decompression_saturation_config_get(int unit, int port, pm_info_t pm_info, uint32* sat_value) 6482 { 6483 SOC_INIT_FUNC_DEFS; 6484 6485 _SOC_IF_ERR_EXIT 6486 (cprimod_cpri_port_decompression_saturation_config_get(unit, port, sat_value)); 6487 6488 6489 exit: 6490 SOC_FUNC_RETURN; 6491 6492 } 6493 #endif /* PORTMOD_CPM4X25_SUPPORT */ 6494 6495 #undef _ERR_MSG_MODULE_NAME