xgxs6.h (54725B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: xgxs6.h 8 * Purpose: 10G 802.3ae Ethernet PHY 9 */ 10 11 #ifndef _PHY_XGXS6_H_ 12 #define _PHY_XGXS6_H_ 13 14 #include <soc/phy.h> 15 16 /* 10Gig XGMII/Serdes PHY Register definitions 17 * From Broadcom XGXS6 Core Documentation 18 */ 19 20 #define XGXS6_IEEE_CTRL_SW_RST (1 << 15) /* S/W Reset */ 21 #define XGXS6_IEEE_CTRL_LB_ENA (1 << 14) /* XGXS6 Local Loopback enable */ 22 #define XGXS6_IEEE_CTRL_SW_PD (1 << 13) /* S/W Powerdown */ 23 24 #define XGXS6_BLOCK_REG_SHIFT 0x03 /* Bits 4:9 of register selects blk*/ 25 26 27 #define XGXS6_BLOCK_0_ASI 0x00 /* Standard, default regs above */ 28 #define XGXS6_BLOCK_1_ASI 0x01 29 #define XGXS6_BLOCK_2_ASI 0x02 30 #define XGXS6_BLOCK_3_ASI 0x03 31 #define XGXS6_BLOCK_4_ASI 0x04 32 33 /* Bit defines for ANA register */ 34 #define XGXS6_ANA_HD (1 << 6) 35 #define XGXS6_ANA_FD (1 << 5) 36 #define XGXS6_ANA_PAUSE_NONE (0 << 7) 37 #define XGXS6_ANA_PAUSE_SYM (1 << 7) 38 #define XGXS6_ANA_PAUSE_ASYM (1 << 8) 39 #define XGXS6_ANA_PAUSE_MASK (3 << 7) 40 41 /* Auto-Negotiation Link-Partner Ability Register */ 42 #define XGXS6_ANP_NEXT_PG (1 << 15) 43 #define XGXS6_ANP_ACK (1 << 14) 44 #define XGXS6_ANP_RF_SHFT (12) /* Remote fault */ 45 #define XGXS6_ANP_RF_MASK (0x3000) 46 #define XGXS6_ANP_PAUSE_ASYM (1 << 8) 47 #define XGXS6_ANP_PAUSE_SYM (1 << 7) 48 #define XGXS6_ANP_HD (1 << 6) 49 #define XGXS6_ANP_FD (1 << 5) 50 51 /* xgxsStatus register */ 52 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK (1 << 11) 53 54 /* If application want to use this header file for accessing PHY registers, 55 * simply redefine PHYXGXS6_REG macro to use BCM API as follows. 56 * 57 * #define SOC_PHY_REG_1000X BCM_PORT_PHY_REG_1000X 58 * 59 * #define PHYXGXS6_REG_READ(_unit, _port, _flags, _reg_bank, _reg_addr, _val) \ 60 * bcm_port_phy_get((_unit), (_port), 0, \ 61 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), \ 62 * (_val)) 63 * 64 * #define PHYXGXS6_REG_WRITE(_unit, _port, _flags, _reg_bank, \ 65 * _reg_addr, _val) \ 66 * bcm_port_phy_set((_unit), (_port), 0, \ 67 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), \ 68 * (_val)) 69 * 70 * #define PHYXGXS6_REG_MODIFY(_unit, _port, _flags, _reg_bank, \ 71 * _reg_addr, _val)\ 72 * do { \ 73 * return BCM_E_UNAVAIL; \ 74 * } while(0) 75 */ 76 77 /* XGXS6 register access */ 78 #define PHYXGXS6_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, \ 79 _reg_addr, _val) \ 80 phy_reg_xgxs6_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 81 (_reg_addr), (_val)) 82 #define PHYXGXS6_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, \ 83 _reg_addr, _val) \ 84 phy_reg_xgxs6_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 85 (_reg_addr), (_val)) 86 #define PHYXGXS6_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 87 _reg_addr, _val, _mask) \ 88 phy_reg_xgxs6_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 89 (_reg_addr), (_val), (_mask)) 90 91 /**********************************/ 92 /* SerDes IEEE Block (blk 0x0000) */ 93 /**********************************/ 94 95 /* SerDes MII Control Register (Addr 00h) */ 96 #define READ_PHYXGXS6_SERDES_MII_CTRLr(_unit, _phy_ctrl, _val) \ 97 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 98 0x0000, 0x00, (_val)) 99 #define WRITE_PHYXGXS6_SERDES_MII_CTRLr(_unit, _phy_ctrl, _val) \ 100 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 101 0x0000, 0x00, (_val)) 102 #define MODIFY_PHYXGXS6_SERDES_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 103 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 104 0x0000, 0x00, (_val), (_mask)) 105 106 /* SerDes MII Status Register (ADDR 01h) */ 107 #define READ_PHYXGXS6_SERDES_MII_STATr(_unit, _phy_ctrl, _val) \ 108 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 109 0x0000, 0x01, (_val)) 110 #define WRITE_PHYXGXS6_SERDES_MII_STATr(_unit, _phy_ctrl, _val) \ 111 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 112 0x0000, 0x01, (_val)) 113 #define MODIFY_PHYXGXS6_SERDES_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 114 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 115 0x0000, 0x01, (_val), (_mask)) 116 117 /* SerDes PHY Identifier Register (ADDR 02h) */ 118 #define READ_PHYXGXS6_SERDES_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 119 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 120 0x0000, 0x02, (_val)) 121 #define WRITE_PHYXGXS6_SERDES_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 122 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 123 0x0000, 0x02, (_val)) 124 #define MODIFY_PHYXGXS6_SERDES_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 125 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 126 0x0000, 0x02, (_val), (_mask)) 127 128 /* SerDes PHY Identifier Register (ADDR 03h) */ 129 #define READ_PHYXGXS6_SERDES_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 130 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 131 0x0000, 0x03, (_val)) 132 #define WRITE_PHYXGXS6_SERDES_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 133 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 134 0x0000, 0x03, (_val)) 135 #define MODIFY_PHYXGXS6_SERDES_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 136 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 137 0x0000, 0x03, (_val), (_mask)) 138 139 /* Auto-neg Advertisment Register (ADDR 04h) */ 140 #define READ_PHYXGXS6_SERDES_MII_ANAr(_unit, _phy_ctrl, _val) \ 141 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 142 0x0000, 0x04, (_val)) 143 #define WRITE_PHYXGXS6_SERDES_MII_ANAr(_unit, _phy_ctrl, _val) \ 144 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 145 0x0000, 0x04, (_val)) 146 #define MODIFY_PHYXGXS6_SERDES_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 147 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 148 0x0000, 0x04, (_val), (_mask)) 149 150 /* Auto-neg Link Partner Ability (ADDR 05h) */ 151 #define READ_PHYXGXS6_SERDES_MII_ANPr(_unit, _phy_ctrl, _val) \ 152 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 153 0x0000, 0x05, (_val)) 154 #define WRITE_PHYXGXS6_SERDES_MII_ANPr(_unit, _phy_ctrl, _val) \ 155 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 156 0x0000, 0x05, (_val)) 157 #define MODIFY_PHYXGXS6_SERDES_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 158 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 159 0x0000, 0x05, (_val), (_mask)) 160 161 /* Auto-neg Expansion Register (ADDR 06h) */ 162 #define READ_PHYXGXS6_SERDES_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 163 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 164 0x0000, 0x06, (_val)) 165 #define WRITE_PHYXGXS6_SERDES_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 166 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 167 0x0000, 0x06, (_val)) 168 #define MODIFY_PHYXGXS6_SERDES_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 169 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 170 0x0000, 0x06, (_val), (_mask)) 171 172 /* Next Page Transmit Register (ADDR 07h) */ 173 /* Link Partner Received Next Page (ADDR 08h) */ 174 /* Reserved (ADDR 0x09 - 0x0E) */ 175 176 /* SerDes Extended Status (ADDR 0Fh) */ 177 #define READ_PHYXGXS6_SERDES_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 178 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 179 0x0000, 0x0F, (_val)) 180 #define WRITE_PHYXGXS6_SERDES_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 181 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 182 0x0000, 0x0F, (_val)) 183 #define MODIFY_PHYXGXS6_SERDES_MII_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 184 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 185 0x0000, 0x0F, (_val), (_mask)) 186 187 /****************************************/ 188 /* XAUI IEEE PMA/PMD Block (blk 0x0000) */ 189 /****************************************/ 190 191 /* XAUI MII Control Register (Addr 00h) */ 192 #define READ_PHYXGXS6_XAUI_MII_CTRLr(_unit, _phy_ctrl, _val) \ 193 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 194 #define WRITE_PHYXGXS6_XAUI_MII_CTRLr(_unit, _phy_ctrl, _val) \ 195 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 196 #define MODIFY_PHYXGXS6_XAUI_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 197 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 198 (_val), (_mask)) 199 200 /* XAUI MII Status Register (ADDR 01h) */ 201 #define READ_PHYXGXS6_XAUI_MII_STATr(_unit, _phy_ctrl, _val) \ 202 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 203 #define WRITE_PHYXGXS6_XAUI_MII_STATr(_unit, _phy_ctrl, _val) \ 204 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 205 #define MODIFY_PHYXGXS6_XAUI_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 206 PHYXGXS6_REG_MODIFY((_unit, _phy_ctrl), 0x00, 0x0000, 0x01, \ 207 (_val), (_mask)) 208 209 /* XAUI PHY Identifier Register (ADDR 02h) */ 210 #define READ_PHYXGXS6_XAUI_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 211 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 212 #define WRITE_PHYXGXS6_XAUI_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 213 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 214 #define MODIFY_PHYXGXS6_XAUI_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 215 PHYXGXS6_REG_MODIFY((_unit, _phy_ctrl), 0x00, 0x0000, 0x02, \ 216 (_val), (_mask)) 217 218 /* XAUI PHY Identifier Register (ADDR 03h) */ 219 #define READ_PHYXGXS6_XAUI_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 220 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 221 #define WRITE_PHYXGXS6_XAUI_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 222 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 223 #define MODIFY_PHYXGXS6_XAUI_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 224 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 225 (_val), (_mask)) 226 227 /* IEEE Speed Ability (Addr 04h) */ 228 /* IEEE Dev In Package 1 (Addr 05h) */ 229 /* IEEE Dev In Package 2 (Addr 06h) */ 230 /* IEEE Control 2 (Addr 07h) */ 231 /* IEEE Status 2 (Addr 08h) */ 232 233 /* IEEE Tx Disable (Addr 09h) */ 234 #define READ_PHYXGXS6_XAUI_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 235 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 236 #define WRITE_PHYXGXS6_XAUI_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 237 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 238 #define MODIFY_PHYXGXS6_XAUI_TX_DISABLEr(_unit, _phy_ctrl, _val, _mask) \ 239 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 240 (_val), (_mask)) 241 242 /* IEEE RxSigDet (Addr 0Ah) */ 243 /* IEEE PMDExtAbil (Addr 0Bh) */ 244 /* Reserved (Addr 0Ch-0Eh) */ 245 246 /****************************/ 247 /* IEEE1 Block (blk 0x0010) */ 248 /****************************/ 249 /* Reserved (Addr 0x0010 - 0x0017) */ 250 251 /* Lane Status (Addr 0x0018) */ 252 #define READ_PHYXGXS6_IEEE1_LANE_STATr(_unit, _phy_ctrl, _val) \ 253 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 254 0x0010, 0x08, (_val)) 255 #define WRITE_PHYXGXS6_IEEE1_LANE_STATr(_unit, _phy_ctrl, _val) \ 256 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 257 0x0010, 0x08, (_val)) 258 #define MODIFY_PHYXGXS6_IEEE1_LANE_STATr(_unit, _phy_ctrl, _val, _mask) \ 259 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 260 0x0010, 0x08, (_val), (_mask)) 261 262 /* IEEE Test Control (Addr 0x0019) */ 263 /* Reserved (Addr 0x001A - 0x001E) */ 264 265 /****************************/ 266 /* XGXS6 Block 0 (blk 0x8000) */ 267 /****************************/ 268 /* XGXS6 Control (Addr 0x8000) */ 269 #define READ_PHYXGXS6_BLK0_CTRLr(_unit, _phy_ctrl, _val) \ 270 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x10, (_val)) 271 #define WRITE_PHYXGXS6_BLK0_CTRLr(_unit, _phy_ctrl, _val) \ 272 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x10, (_val)) 273 #define MODIFY_PHYXGXS6_BLK0_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 274 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x10, \ 275 (_val), (_mask)) 276 277 /* XGXS6 Status (Addr 0x8001) */ 278 #define READ_PHYXGXS6_BLK0_STATr(_unit, _phy_ctrl, _val) \ 279 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x11, (_val)) 280 #define WRITE_PHYXGXS6_BLK0_STATr(_unit, _phy_ctrl, _val) \ 281 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x11, (_val)) 282 #define MODIFY_PHYXGXS6_BLK0_STATr(_unit, _phy_ctrl, _val, _mask) \ 283 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x11, \ 284 (_val), (_mask)) 285 286 /* XGMII Idle (Addr 0x8002) */ 287 #define READ_PHYXGXS6_BLK0_XGMII_IDLEr(_unit, _phy_ctrl, _val) \ 288 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x12, (_val)) 289 #define WRITE_PHYXGXS6_BLK0_XGMII_IDLEr(_unit, _phy_ctrl, _val) \ 290 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x12, (_val)) 291 #define MODIFY_PHYXGXS6_BLK0_XGMII_IDLEr(_unit, _phy_ctrl, _val, _mask) \ 292 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x12, \ 293 (_val), (_mask)) 294 295 /* XGMII Sync (Addr 0x8003) */ 296 #define READ_PHYXGXS6_BLK0_XGMII_SYNCr(_unit, _phy_ctrl, _val) \ 297 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x13, (_val)) 298 #define WRITE_PHYXGXS6_BLK0_XGMII_SYNCr(_unit, _phy_ctrl, _val) \ 299 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x13, (_val)) 300 #define MODIFY_PHYXGXS6_BLK0_XGMII_SYNCr(_unit, _phy_ctrl, _val, _mask) \ 301 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x13, \ 302 (_val), (_mask)) 303 304 /* XGMII Skip (Addr 0x8004) */ 305 #define READ_PHYXGXS6_BLK0_XGMII_SKIPr(_unit, _phy_ctrl, _val) \ 306 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x14, (_val)) 307 #define WRITE_PHYXGXS6_BLK0_XGMII_SKIPr(_unit, _phy_ctrl, _val) \ 308 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x14, (_val)) 309 #define MODIFY_PHYXGXS6_BLK0_XGMII_SKIPr(_unit, _phy_ctrl, _val, _mask) \ 310 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x14, \ 311 (_val), (_mask)) 312 313 /* XGMII Sop Eop (Addr 0x8005) */ 314 #define READ_PHYXGXS6_BLK0_XGMII_SOP_EOPr(_unit, _phy_ctrl, _val) \ 315 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x15, (_val)) 316 #define WRITE_PHYXGXS6_BLK0_XGMII_SOP_EOPr(_unit, _phy_ctrl, _val) \ 317 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x15, (_val)) 318 #define MODIFY_PHYXGXS6_BLK0_XGMII_SOP_EOPr(_unit, _phy_ctrl, _val, _mask) \ 319 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x15, \ 320 (_val), (_mask)) 321 322 /* XGMII Align (Addr 0x8006) */ 323 #define READ_PHYXGXS6_BLK0_XGMII_ALIGNr(_unit, _phy_ctrl, _val) \ 324 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x16, (_val)) 325 #define WRITE_PHYXGXS6_BLK0_XGMII_ALIGNr(_unit, _phy_ctrl, _val) \ 326 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x16, (_val)) 327 #define MODIFY_PHYXGXS6_BLK0_XGMII_ALIGNr(_unit, _phy_ctrl, _val, _mask) \ 328 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x16, \ 329 (_val), (_mask)) 330 331 /* XGMII R Control (Addr 0x8007) */ 332 #define READ_PHYXGXS6_BLK0_XGMII_RCTRLr(_unit, _phy_ctrl, _val) \ 333 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x17, (_val)) 334 #define WRITE_PHYXGXS6_BLK0_XGMII_RCTRLr(_unit, _phy_ctrl, _val) \ 335 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x17, (_val)) 336 #define MODIFY_PHYXGXS6_BLK0_XGMII_RCTRLr(_unit, _phy_ctrl, _val, _mask) \ 337 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x17, \ 338 (_val), (_mask)) 339 340 /* XGMII T Control (Addr 0x8008) */ 341 #define READ_PHYXGXS6_BLK0_XGMII_TCTRLr(_unit, _phy_ctrl, _val) \ 342 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x18, (_val)) 343 #define WRITE_PHYXGXS6_BLK0_XGMII_TCTRLr(_unit, _phy_ctrl, _val) \ 344 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x18, (_val)) 345 #define MODIFY_PHYXGXS6_BLK0_XGMII_TCTRLr(_unit, _phy_ctrl, _val, _mask) \ 346 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x18, \ 347 (_val), (_mask)) 348 349 /* XGMII Swap (Addr 0x8009) */ 350 #define READ_PHYXGXS6_BLK0_XGMII_SWAPr(_unit, _phy_ctrl, _val) \ 351 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x19, (_val)) 352 #define WRITE_PHYXGXS6_BLK0_XGMII_SWAPr(_unit, _phy_ctrl, _val) \ 353 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x19, (_val)) 354 #define MODIFY_PHYXGXS6_BLK0_XGMII_SWAPr(_unit, _phy_ctrl, _val, _mask) \ 355 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x19, \ 356 (_val), (_mask)) 357 358 /* IssLsid (Addr 0x800A) */ 359 #define READ_PHYXGXS6_BLK0_ISS_LSIDr(_unit, _phy_ctrl, _val) \ 360 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1A, (_val)) 361 #define WRITE_PHYXGXS6_BLK0_ISS_LSIDr(_unit, _phy_ctrl, _val) \ 362 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1A, (_val)) 363 #define MODIFY_PHYXGXS6_BLK0_ISS_LSIDr(_unit, _phy_ctrl, _val, _mask) \ 364 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1A, \ 365 (_val), (_mask)) 366 367 /* IssTinfo (Addr 0x800B) */ 368 #define READ_PHYXGXS6_BLK0_ISS_TINFOr(_unit, _phy_ctrl, _val) \ 369 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1B, (_val)) 370 #define WRITE_PHYXGXS6_BLK0_ISS_TINFOr(_unit, _phy_ctrl, _val) \ 371 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1B, (_val)) 372 #define MODIFY_PHYXGXS6_BLK0_ISS_TINFOr(_unit, _phy_ctrl, _val, _mask) \ 373 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1B, \ 374 (_val), (_mask)) 375 376 /* IssRinfo (Addr 0x800C) */ 377 #define READ_PHYXGXS6_BLK0_ISS_RINFOr(_unit, _phy_ctrl, _val) \ 378 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1C, (_val)) 379 #define WRITE_PHYXGXS6_BLK0_ISS_RINFOr(_unit, _phy_ctrl, _val) \ 380 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1C, (_val)) 381 #define MODIFY_PHYXGXS6_BLK0_ISS_RINFOr(_unit, _phy_ctrl, _val, _mask) \ 382 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1C, \ 383 (_val), (_mask)) 384 385 /* CX4 SigDet Cnt (Addr 0x800D) */ 386 #define READ_PHYXGXS6_BLK0_CX4_SIGDET_COUNTERr(_unit, _phy_ctrl, _val) \ 387 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1D, (_val)) 388 #define WRITE_PHYXGXS6_BLK0_CX4_SIGDET_COUNTERr(_unit, _phy_ctrl, _val) \ 389 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1D, (_val)) 390 #define MODIFY_PHYXGXS6_BLK0_CX4_SIGDET_COUNTERr(_unit, _phy_ctrl, _val, \ 391 _mask) \ 392 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1D, \ 393 (_val), (_mask)) 394 395 /* Misc Control 1 (Addr 0x800E) */ 396 #define READ_PHYXGXS6_BLK0_MISC_CTRL1r(_unit, _phy_ctrl, _val) \ 397 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1E, (_val)) 398 #define WRITE_PHYXGXS6_BLK0_MISC_CTRL1r(_unit, _phy_ctrl, _val) \ 399 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1E, (_val)) 400 #define MODIFY_PHYXGXS6_BLK0_MISC_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 401 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1E, \ 402 (_val), (_mask)) 403 404 /*****************************/ 405 /* XGXS6 Block 1 (blk 0x8010) */ 406 /*****************************/ 407 /* deskew (Addr 0x8010) */ 408 #define READ_PHYXGXS6_BLK1_DESKEWr(_unit, _phy_ctrl, _val) \ 409 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x10, (_val)) 410 #define WRITE_PHYXGXS6_BLK1_DESKEWr(_unit, _phy_ctrl, _val) \ 411 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x10, (_val)) 412 #define MODIFY_PHYXGXS6_BLK1_DESKEWr(_unit, _phy_ctrl, _val, _mask) \ 413 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x10, \ 414 (_val), (_mask)) 415 416 /* link (Addr 0x8011) */ 417 #define READ_PHYXGXS6_BLK1_LINKr(_unit, _phy_ctrl, _val) \ 418 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x011, (_val)) 419 #define WRITE_PHYXGXS6_BLK1_LINKr(_unit, _phy_ctrl, _val) \ 420 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x011,(_val)) 421 #define MODIFY_PHYXGXS6_BLK1_LINKr(_unit, _phy_ctrl, _val, _mask) \ 422 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x011, \ 423 (_val), (_mask)) 424 425 /* testRx (Addr 0x8012) */ 426 #define READ_PHYXGXS6_BLK1_TESTRXr(_unit, _phy_ctrl, _val) \ 427 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x012, (_val)) 428 #define WRITE_PHYXGXS6_BLK1_TESTRXr(_unit, _phy_ctrl, _val) \ 429 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x012,(_val)) 430 #define MODIFY_PHYXGXS6_BLK1_TESTRXr(_unit, _phy_ctrl, _val, _mask) \ 431 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x012, \ 432 (_val), (_mask)) 433 434 /* testTx (Addr 0x8013) */ 435 436 /* testXg (Addr 0x8014) */ 437 438 /* Reserved (Addr 0x8015) */ 439 440 /* laneCtrl1 (Addr 0x8016) */ 441 #define READ_PHYXGXS6_BLK1_LANE_CTRL1r(_unit, _phy_ctrl, _val) \ 442 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x16, (_val)) 443 #define WRITE_PHYXGXS6_BLK1_LANE_CTRL1r(_unit, _phy_ctrl, _val) \ 444 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x16, (_val)) 445 #define MODIFY_PHYXGXS6_BLK1_LANE_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 446 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x16, \ 447 (_val), (_mask)) 448 449 /* laneCtrl2 (Addr 0x8017) */ 450 #define READ_PHYXGXS6_BLK1_LANE_CTRL2r(_unit, _phy_ctrl, _val) \ 451 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x17, (_val)) 452 #define WRITE_PHYXGXS6_BLK1_LANE_CTRL2r(_unit, _phy_ctrl, _val) \ 453 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x17, (_val)) 454 #define MODIFY_PHYXGXS6_BLK1_LANE_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 455 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x17, \ 456 (_val), (_mask)) 457 458 /* laneCtrl3 (Addr 0x8018) */ 459 #define READ_PHYXGXS6_BLK1_LANE_CTRL3r(_unit, _phy_ctrl, _val) \ 460 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x18, (_val)) 461 #define WRITE_PHYXGXS6_BLK1_LANE_CTRL3r(_unit, _phy_ctrl, _val) \ 462 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x18, (_val)) 463 #define MODIFY_PHYXGXS6_BLK1_LANE_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 464 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x18, \ 465 (_val), (_mask)) 466 467 /* lanePrbs (Addr 0x8019) */ 468 469 /* laneTest (Addr 0x801A) */ 470 #define READ_PHYXGXS6_BLK1_LANE_TESTr(_unit, _phy_ctrl, _val) \ 471 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x1A, (_val)) 472 #define WRITE_PHYXGXS6_BLK1_LANE_TESTr(_unit, _phy_ctrl, _val) \ 473 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x1A, (_val)) 474 #define MODIFY_PHYXGXS6_BLK1_LANE_TESTr(_unit, _phy_ctrl, _val, _mask) \ 475 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x1A, \ 476 (_val), (_mask)) 477 478 /* IssRevnt (Addr 0x801B) */ 479 480 /* dskevnt (Addr 0x801C) */ 481 482 /* Aerrevnt (Addr 0x801D) */ 483 484 /* chcmpevnt (Addr 0x801E) */ 485 486 487 /****************************/ 488 /* 10G Tx BERT (blk 0x8020) */ 489 /****************************/ 490 491 492 /****************************/ 493 /* 10G Rx BERT (blk 0x8030) */ 494 /****************************/ 495 496 /*************************/ 497 /* BcstBert (blk 0x8040) */ 498 /*************************/ 499 500 /********************/ 501 /* PLL (blk 0x8050) */ 502 /********************/ 503 504 /* PLL STATUS (Addr 0x8050) */ 505 #define READ_PHYXGXS6_PLL_STATr(_unit, _phy_ctrl, _val) \ 506 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x10, (_val)) 507 #define WRITE_PHYXGXS6_PLL_STATr(_unit, _phy_ctrl, _val) \ 508 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x10, (_val)) 509 #define MODIFY_PHYXGXS6_PLL_STATr(_unit, _phy_ctrl, _val, _mask) \ 510 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x10, \ 511 (_val), (_mask)) 512 513 /* PLL Control (Addr 0x8051) */ 514 #define READ_PHYXGXS6_PLL_CTRLr(_unit, _phy_ctrl, _val) \ 515 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x11, (_val)) 516 #define WRITE_PHYXGXS6_PLL_CTRLr(_unit, _phy_ctrl, _val) \ 517 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x11, (_val)) 518 #define MODIFY_PHYXGXS6_PLL_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 519 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x11, \ 520 (_val), (_mask)) 521 522 /* PLL Timer 1 (Addr 0x8052) */ 523 #define READ_PHYXGXS6_PLL_TIMER1r(_unit, _phy_ctrl, _val) \ 524 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x12, (_val)) 525 #define WRITE_PHYXGXS6_PLL_TIMER1r(_unit, _phy_ctrl, _val) \ 526 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x12, (_val)) 527 #define MODIFY_PHYXGXS6_PLL_TIMER1r(_unit, _phy_ctrl, _val, _mask) \ 528 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x12, \ 529 (_val), (_mask)) 530 531 /* PLL Timer 2 (Addr 0x8053) */ 532 #define READ_PHYXGXS6_PLL_TIMER2r(_unit, _phy_ctrl, _val) \ 533 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x13, (_val)) 534 #define WRITE_PHYXGXS6_PLL_TIMER2r(_unit, _phy_ctrl, _val) \ 535 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x13, (_val)) 536 #define MODIFY_PHYXGXS6_PLL_TIMER2r(_unit, _phy_ctrl, _val, _mask) \ 537 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x13, \ 538 (_val), (_mask)) 539 540 /* PLL Timer 3 (Addr 0x8054) */ 541 #define READ_PHYXGXS6_PLL_TIMER3r(_unit, _phy_ctrl, _val) \ 542 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x14, (_val)) 543 #define WRITE_PHYXGXS6_PLL_TIMER3r(_unit, _phy_ctrl, _val) \ 544 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x14, (_val)) 545 #define MODIFY_PHYXGXS6_PLL_TIMER3r(_unit, _phy_ctrl, _val, _mask) \ 546 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x14, \ 547 (_val), (_mask)) 548 549 /* CAP Control (Addr 0x8055) */ 550 #define READ_PHYXGXS6_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val) \ 551 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x15, (_val)) 552 #define WRITE_PHYXGXS6_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val) \ 553 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x15, (_val)) 554 #define MODIFY_PHYXGXS6_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 555 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x15, \ 556 (_val), (_mask)) 557 558 /* AMP Control (Addr 0x8056) */ 559 #define READ_PHYXGXS6_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val) \ 560 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x16, (_val)) 561 #define WRITE_PHYXGXS6_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val) \ 562 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x16, (_val)) 563 #define MODIFY_PHYXGXS6_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 564 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x16, \ 565 (_val), (_mask)) 566 567 /* Freq Det Counter (Addr 0x8057) */ 568 #define READ_PHYXGXS6_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val) \ 569 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x17, (_val)) 570 #define WRITE_PHYXGXS6_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val) \ 571 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x17, (_val)) 572 #define MODIFY_PHYXGXS6_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 573 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x17, \ 574 (_val), (_mask)) 575 576 /* PLL Astatus 1 (Addr 0x8058) */ 577 #define READ_PHYXGXS6_PLL_ASTAT1r(_unit, _phy_ctrl, _val) \ 578 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x18, (_val)) 579 #define WRITE_PHYXGXS6_PLL_ASTAT1r(_unit, _phy_ctrl, _val) \ 580 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x18, (_val)) 581 #define MODIFY_PHYXGXS6_PLL_ASTAT1r(_unit, _phy_ctrl, _val, _mask) \ 582 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x18, \ 583 (_val), (_mask)) 584 585 /* PLL Astatus 2 (Addr 0x8059) */ 586 #define READ_PHYXGXS6_PLL_ASTAT2r(_unit, _phy_ctrl, _val) \ 587 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x19, (_val)) 588 #define WRITE_PHYXGXS6_PLL_ASTAT2r(_unit, _phy_ctrl, _val) \ 589 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x19, (_val)) 590 #define MODIFY_PHYXGXS6_PLL_ASTAT2r(_unit, _phy_ctrl, _val, _mask) \ 591 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x19, \ 592 (_val), (_mask)) 593 594 /* PLL Clock Gen (Addr 0x805A) */ 595 #define READ_PHYXGXS6_PLL_CLK_GENr(_unit, _phy_ctrl, _val) \ 596 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1A, (_val)) 597 #define WRITE_PHYXGXS6_PLL_CLK_GENr(_unit, _phy_ctrl, _val) \ 598 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1A, (_val)) 599 #define MODIFY_PHYXGXS6_PLL_CLK_GENr(_unit, _phy_ctrl, _val, _mask) \ 600 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1A, \ 601 (_val), (_mask)) 602 603 /* PLL Ndiv (Addr 0x805B) */ 604 #define READ_PHYXGXS6_PLL_NDIVr(_unit, _phy_ctrl, _val) \ 605 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1B, (_val)) 606 #define WRITE_PHYXGXS6_PLL_NDIVr(_unit, _phy_ctrl, _val) \ 607 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1B, (_val)) 608 #define MODIFY_PHYXGXS6_PLL_NDIVr(_unit, _phy_ctrl, _val, _mask) \ 609 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1B, \ 610 (_val), (_mask)) 611 612 /* PLL Bglqp (Addr 0x805C) */ 613 #define READ_PHYXGXS6_PLL_BGLQPr(_unit, _phy_ctrl, _val) \ 614 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1C, (_val)) 615 #define WRITE_PHYXGXS6_PLL_BGLQP(_unit, _phy_ctrl, _val) \ 616 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1C, (_val)) 617 #define MODIFY_PHYXGXS6_PLL_BGLQPr(_unit, _phy_ctrl, _val, _mask) \ 618 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1C, \ 619 (_val), (_mask)) 620 621 /* PLL Test Kvh (Addr 0x805D) */ 622 #define READ_PHYXGXS6_PLL_TEST_KVHr(_unit, _phy_ctrl, _val) \ 623 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1D, (_val)) 624 #define WRITE_PHYXGXS6_PLL_TEST_KVHr(_unit, _phy_ctrl, _val) \ 625 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1D, (_val)) 626 #define MODIFY_PHYXGXS6_PLL_TEST_KVHr(_unit, _phy_ctrl, _val, _mask) \ 627 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1D, \ 628 (_val), (_mask)) 629 630 /* PLL AControl 5 (Addr 0x805E) */ 631 #define READ_PHYXGXS6_PLL_ACTRL5r(_unit, _phy_ctrl, _val) \ 632 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1E, (_val)) 633 #define WRITE_PHYXGXS6_PLL_ACTRL5r(_unit, _phy_ctrl, _val) \ 634 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1E, (_val)) 635 #define MODIFY_PHYXGXS6_PLL_ACTRL5r(_unit, _phy_ctrl, _val, _mask) \ 636 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1E, \ 637 (_val), (_mask)) 638 639 640 /********************/ 641 /* TX0 (blk 0x8060) */ 642 /********************/ 643 644 /********************/ 645 /* TX1 (blk 0x8070) */ 646 /********************/ 647 648 649 /********************/ 650 /* TX2 (blk 0x8080) */ 651 /********************/ 652 653 654 /********************/ 655 /* TX3 (blk 0x8090) */ 656 /********************/ 657 658 659 /********************/ 660 /* TX All (blk 0x80A0) */ 661 /********************/ 662 /* Tx AStatus 0 (Addr 0x80A0) */ 663 /* Tx AControl 0 (Addr 0x80A1) */ 664 #define READ_PHYXGXS6_TXALL_ACTRL0r(_unit, _phy_ctrl, _val) \ 665 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x11, (_val)) 666 #define WRITE_PHYXGXS6_TXALL_ACTRL0r(_unit, _phy_ctrl, _val) \ 667 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x11, (_val)) 668 #define MODIFY_PHYXGXS6_TXALL_ACTRL0r(_unit, _phy_ctrl, _val, _mask) \ 669 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x11, \ 670 (_val), (_mask)) 671 672 /* Tx mdata 0 (Addr 0x80A2) */ 673 /* Tx mdata 1 (Addr 0x80A3) */ 674 /* Tx AStatus 1 (Addr 0x80A4) */ 675 /* Tx BgVcm (Addr 0x80A5) */ 676 /* Tx Ibuff 1T2T (Addr 0x80A6) */ 677 678 /* Tx Driver (Addr 0x80A7) */ 679 #define READ_PHYXGXS6_TXALL_DRIVERr(_unit, _phy_ctrl, _val) \ 680 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x17, (_val)) 681 #define WRITE_PHYXGXS6_TXALL_DRIVERr(_unit, _phy_ctrl, _val) \ 682 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x17, (_val)) 683 #define MODIFY_PHYXGXS6_TXALL_DRIVERr(_unit, _phy_ctrl, _val, _mask) \ 684 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x17, \ 685 (_val), (_mask)) 686 687 /* Reserved (Addr 0x80A8 - 0x80AE) */ 688 689 /********************/ 690 /* RX0 (blk 0x80B0) */ 691 /********************/ 692 693 694 /********************/ 695 /* RX1 (blk 0x80C0) */ 696 /********************/ 697 698 699 /********************/ 700 /* RX2 (blk 0x80D0) */ 701 /********************/ 702 703 704 /********************/ 705 /* RX3 (blk 0x80E0) */ 706 /********************/ 707 708 709 /***********************/ 710 /* RX All (blk 0x80F0) */ 711 /***********************/ 712 /* Rx Status (Address 0x80F0) */ 713 #define READ_PHYXGXS6_RXALL_STATr(_unit, _phy_ctrl, _val) \ 714 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x10, (_val)) 715 #define WRITE_PHYXGXS6_RXALL_STATr(_unit, _phy_ctrl, _val) \ 716 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x10, (_val)) 717 #define MODIFY_PHYXGXS6_RXALL_STATr(_unit, _phy_ctrl, _val, _mask) \ 718 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x10, \ 719 (_val), (_mask)) 720 721 /* Rx Control (Address 0x80F1) */ 722 #define READ_PHYXGXS6_RXALL_CTRLr(_unit, _phy_ctrl, _val) \ 723 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x11, (_val)) 724 #define WRITE_PHYXGXS6_RXALL_CTRLr(_unit, _phy_ctrl, _val) \ 725 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x11, (_val)) 726 #define MODIFY_PHYXGXS6_RXALL_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 727 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x11, \ 728 (_val), (_mask)) 729 730 /* Rx Timer 1 (Address 0x80F2) */ 731 #define READ_PHYXGXS6_RXALL_TIMER1r(_unit, _phy_ctrl, _val) \ 732 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x12, (_val)) 733 #define WRITE_PHYXGXS6_RXALL_TIMER1r(_unit, _phy_ctrl, _val) \ 734 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x12, (_val)) 735 #define MODIFY_PHYXGXS6_RXALL_TIMER1r(_unit, _phy_ctrl, _val, _mask) \ 736 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x12, \ 737 (_val), (_mask)) 738 739 /* Rx Timer 2 (Address 0x80F3) */ 740 #define READ_PHYXGXS6_RXALL_TIMER2r(_unit, _phy_ctrl, _val) \ 741 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x13, (_val)) 742 #define WRITE_PHYXGXS6_RXALL_TIMER2r(_unit, _phy_ctrl, _val) \ 743 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x13, (_val)) 744 #define MODIFY_PHYXGXS6_RXALL_TIMER2r(_unit, _phy_ctrl, _val, _mask) \ 745 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x13, \ 746 (_val), (_mask)) 747 748 /* Rx SigDet (Address 0x80F4) */ 749 #define READ_PHYXGXS6_RXALL_SIG_DETr(_unit, _phy_ctrl, _val) \ 750 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x14, (_val)) 751 #define WRITE_PHYXGXS6_RXALL_SIG_DETr(_unit, _phy_ctrl, _val) \ 752 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x14, (_val)) 753 #define MODIFY_PHYXGXS6_RXALL_SIG_DETr(_unit, _phy_ctrl, _val, _mask) \ 754 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x14, \ 755 (_val), (_mask)) 756 757 /* Rx CdrPhase (Address 0x80F5) */ 758 #define READ_PHYXGXS6_RXALL_CDR_PHASEr(_unit, _phy_ctrl, _val) \ 759 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x15, (_val)) 760 #define WRITE_PHYXGXS6_RXALL_CDR_PHASEr(_unit, _phy_ctrl, _val) \ 761 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x15, (_val)) 762 #define MODIFY_PHYXGXS6_RXALL_CDR_PHASEr(_unit, _phy_ctrl, _val, _mask) \ 763 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x15, \ 764 (_val), (_mask)) 765 766 /* Rx CdrFreq (Address 0x80F6) */ 767 #define READ_PHYXGXS6_RXALL_CDR_FREQr(_unit, _phy_ctrl, _val) \ 768 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x16, (_val)) 769 #define WRITE_PHYXGXS6_RXALL_CDR_FREQr(_unit, _phy_ctrl, _val) \ 770 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x16, (_val)) 771 #define MODIFY_PHYXGXS6_RXALL_CDR_FREQr(_unit, _phy_ctrl, _val, _mask) \ 772 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x16, \ 773 (_val), (_mask)) 774 775 /* Rx EqConfig (Address 0x80F7) */ 776 #define READ_PHYXGXS6_RXALL_EQ_CONFIGr(_unit, _phy_ctrl, _val) \ 777 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x17, (_val)) 778 #define WRITE_PHYXGXS6_RXALL_EQ_CONFIGr(_unit, _phy_ctrl, _val) \ 779 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x17, (_val)) 780 #define MODIFY_PHYXGXS6_RXALL_EQ_CONFIGr(_unit, _phy_ctrl, _val, _mask) \ 781 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x17, \ 782 (_val), (_mask)) 783 784 /* Rx EqForce (Address 0x80F8) */ 785 #define READ_PHYXGXS6_RXALL_EQ_FORCEr(_unit, _phy_ctrl, _val) \ 786 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x18, (_val)) 787 #define WRITE_PHYXGXS6_RXALL_EQ_FORCEr(_unit, _phy_ctrl, _val) \ 788 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x18, (_val)) 789 #define MODIFY_PHYXGXS6_RXALL_EQ_FORCEr(_unit, _phy_ctrl, _val, _mask) \ 790 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x18, \ 791 (_val), (_mask)) 792 793 /* Rx Control 1G (Address 0x80F9) */ 794 #define READ_PHYXGXS6_RXALL_CTRL_1Gr(_unit, _phy_ctrl, _val) \ 795 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x19, (_val)) 796 #define WRITE_PHYXGXS6_RXALL_CTRL_1Gr(_unit, _phy_ctrl, _val) \ 797 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x19, (_val)) 798 #define MODIFY_PHYXGXS6_RXALL_CTRL_1Gr(_unit, _phy_ctrl, _val, _mask) \ 799 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x19, \ 800 (_val), (_mask)) 801 802 /* Rx Control PCIE (Address 0x80FA) */ 803 #define READ_PHYXGXS6_RXALL_CTRL_PCIEr(_unit, _phy_ctrl, _val) \ 804 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1A, (_val)) 805 #define WRITE_PHYXGXS6_RXALL_CTRL_PCIEr(_unit, _phy_ctrl, _val) \ 806 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1A, (_val)) 807 #define MODIFY_PHYXGXS6_RXALL_CTRL_PCIEr(_unit, _phy_ctrl, _val, _mask) \ 808 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1A, \ 809 (_val), (_mask)) 810 811 /* Rx Astatus (Address 0x80FB) */ 812 #define READ_PHYXGXS6_RXALL_ASTATr(_unit, _phy_ctrl, _val) \ 813 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1B, (_val)) 814 #define WRITE_PHYXGXS6_RXALL_ASTATr(_unit, _phy_ctrl, _val) \ 815 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1B, (_val)) 816 #define MODIFY_PHYXGXS6_RXALL_ASTATr(_unit, _phy_ctrl, _val, _mask) \ 817 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1B, \ 818 (_val), (_mask)) 819 820 /* Rx Eq Boost (Address 0x80FC) */ 821 #define READ_PHYXGXS6_RXALL_EQ_BOOSTr(_unit, _phy_ctrl, _val) \ 822 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1C, (_val)) 823 #define WRITE_PHYXGXS6_RXALL_EQ_BOOSTr(_unit, _phy_ctrl, _val) \ 824 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1C, (_val)) 825 #define MODIFY_PHYXGXS6_RXALL_EQ_BOOSTr(_unit, _phy_ctrl, _val, _mask) \ 826 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1C, \ 827 (_val), (_mask)) 828 829 /* Rx lb Data Eq (Address 0x80FD) */ 830 #define READ_PHYXGXS6_RXALL_LB_DATA_EQr(_unit, _phy_ctrl, _val) \ 831 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1D, (_val)) 832 #define WRITE_PHYXGXS6_RXALL_LB_DATA_EQr(_unit, _phy_ctrl, _val) \ 833 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1D, (_val)) 834 #define MODIFY_PHYXGXS6_RXALL_LB_DATA_EQr(_unit, _phy_ctrl, _val, _mask) \ 835 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1D, \ 836 (_val), (_mask)) 837 838 /* Rx lb ADC Buff (Address 0x80FE) */ 839 #define READ_PHYXGXS6_RXALL_LB_ADC_BUFFr(_unit, _phy_ctrl, _val) \ 840 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1E, (_val)) 841 #define WRITE_PHYXGXS6_RXALL_LB_ADC_BUFFr(_unit, _phy_ctrl, _val) \ 842 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1E, (_val)) 843 #define MODIFY_PHYXGXS6_RXALL_LB_ADC_BUFFr(_unit, _phy_ctrl, _val, _mask) \ 844 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1E, \ 845 (_val), (_mask)) 846 847 /*****************************/ 848 /* XGXS6 Block 2 (blk 0x8100) */ 849 /*****************************/ 850 /* Rx Lane Swap (Addr 0x8100) */ 851 /* Tx Lane Swap (Addr 0x8101) */ 852 #define READ_PHYXGXS6_BLK2_TX_LANE_SWAPr(_unit, _phy_ctrl, _val) \ 853 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8100, 0x11, (_val)) 854 #define WRITE_PHYXGXS6_BLK2_TX_LANE_SWAPr(_unit, _phy_ctrl, _val) \ 855 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8100, 0x11, (_val)) 856 #define MODIFY_PHYXGXS6_BLK2_TX_LANE_SWAPr(_unit, _phy_ctrl, _val, _mask) \ 857 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8100, 0x11, \ 858 (_val), (_mask)) 859 860 /* QsetLns01 (Addr 0x8102) */ 861 /* QsetLns23 (Addr 0x8103) */ 862 /* Unicore Mode 10G (Addr 0x8104) */ 863 /* Reserved (Addr 0x8105 - 0x810E) */ 864 865 /*****************************/ 866 /* In Band MDIO (blk 0x8110) */ 867 /*****************************/ 868 869 870 /**************************/ 871 /* GP Status (blk 0x8120) */ 872 /**************************/ 873 #define READ_PHYXGXS6_GPSTAT_XGXS_STAT1r(_unit, _phy_ctrl, _val) \ 874 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8120, 0x12, (_val)) 875 #define WRITE_PHYXGXS6_GPSTAT_XGXS_STAT1r(_unit, _phy_ctrl, _val) \ 876 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8120, 0x12, (_val)) 877 #define MODIFY_PHYXGXS6_GPSTAT_XGXS_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 878 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8120, 0x12, \ 879 (_val), (_mask)) 880 881 #define XGXS_STAT1_LINK_10G (1 << 9) 882 #define XGXS_STAT1_LINK_SERDES (1 << 8) 883 #define XGXS_STAT1_AUTONEG_DONE (1 << 7) 884 #define XGXS_STAT1_ACTUAL_SPEED_MASK (0xf << 0) 885 #define XGXS_STAT1_ACTUAL_SPEED_10 (0) 886 #define XGXS_STAT1_ACTUAL_SPEED_100 (1) 887 #define XGXS_STAT1_ACTUAL_SPEED_1000 (2) 888 #define XGXS_STAT1_ACTUAL_SPEED_2500 (3) 889 #define XGXS_STAT1_ACTUAL_SPEED_5000 (4) 890 #define XGXS_STAT1_ACTUAL_SPEED_6000 (5) 891 #define XGXS_STAT1_ACTUAL_SPEED_10000 (6) 892 #define XGXS_STAT1_ACTUAL_SPEED_10000CX4 (7) 893 #define XGXS_STAT1_ACTUAL_SPEED_12000 (8) 894 #define XGXS_STAT1_ACTUAL_SPEED_12500 (9) 895 #define XGXS_STAT1_ACTUAL_SPEED_13000 (0xa) 896 #define XGXS_STAT1_ACTUAL_SPEED_15000 (0xb) 897 #define XGXS_STAT1_ACTUAL_SPEED_16000 (0xc) 898 899 /*******************************/ 900 /* SerDes Digital (blk 0x8300) */ 901 /*******************************/ 902 903 /* 1000XControl1 (Addr 0x8300) */ 904 #define READ_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 905 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x10, (_val)) 906 #define WRITE_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 907 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x10, (_val)) 908 #define MODIFY_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL1r(_unit, _phy_ctrl, \ 909 _val, _mask) \ 910 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x10, \ 911 (_val), (_mask)) 912 913 /* 1000XControl2 (Addr 0x8301) */ 914 #define READ_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 915 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x11, (_val)) 916 #define WRITE_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 917 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x11, (_val)) 918 #define MODIFY_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL2r(_unit, _phy_ctrl, \ 919 _val, _mask) \ 920 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x11, \ 921 (_val), (_mask)) 922 923 /* 1000XControl3 (Addr 0x8302) */ 924 #define READ_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 925 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x12, (_val)) 926 #define WRITE_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 927 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x12, (_val)) 928 #define MODIFY_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL3r(_unit, _phy_ctrl, \ 929 _val, _mask) \ 930 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x12, \ 931 (_val), (_mask)) 932 933 /* 1000XControl4 (Addr 0x8303) */ 934 #define READ_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 935 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x13, (_val)) 936 #define WRITE_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 937 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x13, (_val)) 938 #define MODIFY_PHYXGXS6_SERDES_DIGITAL_1000X_CTRL4r(_unit, _phy_ctrl, \ 939 _val, _mask) \ 940 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x13, \ 941 (_val), (_mask)) 942 943 /* 1000XStatus1 (Addr 0x8304) */ 944 #define READ_PHYXGXS6_SERDES_DIGITAL_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 945 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x14, (_val)) 946 #define WRITE_PHYXGXS6_SERDES_DIGITAL_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 947 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x14, (_val)) 948 #define MODIFY_PHYXGXS6_SERDES_DIGITAL_1000X_STAT1r(_unit, _phy_ctrl, \ 949 _val, _mask) \ 950 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x14, \ 951 (_val), (_mask)) 952 953 /* 1000XStatus2 (Addr 0x8305) */ 954 #define READ_PHYXGXS6_SERDES_DIGITAL_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 955 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x15, (_val)) 956 #define WRITE_PHYXGXS6_SERDES_DIGITAL_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 957 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x15, (_val)) 958 #define MODIFY_PHYXGXS6_SERDES_DIGITAL_1000X_STAT2r(_unit, _phy_ctrl, \ 959 _val, _mask) \ 960 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x15, \ 961 (_val), (_mask)) 962 963 /* 1000XStatus3 (Addr 0x8306) */ 964 #define READ_PHYXGXS6_SERDES_DIGITAL_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 965 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x16, (_val)) 966 #define WRITE_PHYXGXS6_SERDES_DIGITAL_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 967 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x16, (_val)) 968 #define MODIFY_PHYXGXS6_SERDES_DIGITAL_1000X_STAT3r(_unit, _phy_ctrl, \ 969 _val, _mask) \ 970 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x16, \ 971 (_val), (_mask)) 972 973 /* CrcErr_RxPktCntr (Addr 0x8307) */ 974 975 /* Misc1 (Addr 0x8308) */ 976 #define READ_PHYXGXS6_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val) \ 977 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x18, (_val)) 978 #define WRITE_PHYXGXS6_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val) \ 979 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x18, (_val)) 980 #define MODIFY_PHYXGXS6_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val, _mask) \ 981 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x18, \ 982 (_val), (_mask)) 983 984 /* Misc2 (Addr 0x8309) */ 985 #define READ_PHYXGXS6_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val) \ 986 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x19, (_val)) 987 #define WRITE_PHYXGXS6_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val) \ 988 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x19, (_val)) 989 #define MODIFY_PHYXGXS6_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val, _mask) \ 990 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x19, \ 991 (_val), (_mask)) 992 993 /* PatGenControl (Addr 0x830A) */ 994 /* PatGenControl (Addr 0x830B) */ 995 /* TestMode (Addr 0x830C) */ 996 /* TxPktCnt (Addr 0x830D) */ 997 /* RxPktCnt (Addr 0x830E) */ 998 999 /*********************/ 1000 /* Test (blk 0x8310) */ 1001 /*********************/ 1002 1003 /************************/ 1004 /* Over 1G (blk 0x8320) */ 1005 /************************/ 1006 /* digctrl_3_0 (Addr 0x8320) */ 1007 /* digctrl_3_1 (Addr 0x8321) */ 1008 /* digctrl_3_2 (Addr 0x8322) */ 1009 /* digctrl_3_3 (Addr 0x8323) */ 1010 /* digctrl_3_4 (Addr 0x8324) */ 1011 /* digctrl_3_5 (Addr 0x8325) */ 1012 /* digctrl_3_6 (Addr 0x8326) */ 1013 /* TPOUT 1 (Addr 0x8327) */ 1014 /* TPOUT 2 (Addr 0x8328) */ 1015 1016 /* UP 1 (Addr 0x8329) */ 1017 #define READ_PHYXGXS6_OVER1G_UP1r(_unit, _phy_ctrl, _val) \ 1018 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8320, 0x19, (_val)) 1019 #define WRITE_PHYXGXS6_OVER1G_UP1r(_unit, _phy_ctrl, _val) \ 1020 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8320, 0x19, (_val)) 1021 #define MODIFY_PHYXGXS6_OVER1G_UP1r(_unit, _phy_ctrl, _val, _mask) \ 1022 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8320, 0x19, \ 1023 (_val), (_mask)) 1024 1025 /* UP 2 (Addr 0x832A) */ 1026 /* UP 3 (Addr 0x832B) */ 1027 1028 /* LP UP 1 (Addr 0x832C) */ 1029 #define READ_PHYXGXS6_OVER1G_LP_UP1r(_unit, _phy_ctrl, _val) \ 1030 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8320, 0x1C, (_val)) 1031 #define WRITE_PHYXGXS6_OVER1G_LP_UP1r(_unit, _phy_ctrl, _val) \ 1032 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8320, 0x1C, (_val)) 1033 #define MODIFY_PHYXGXS6_OVER1G_LP_UP1r(_unit, _phy_ctrl, _val, _mask) \ 1034 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8320, 0x1C, \ 1035 (_val), (_mask)) 1036 1037 /* LP UP 2 (Addr 0x832D) */ 1038 /* LP UP 3 (Addr 0x832E) */ 1039 1040 /***************************/ 1041 /* Remote PHY (blk 0x8330) */ 1042 /***************************/ 1043 1044 /************************************/ 1045 /* 10G Parallel Detect (blk 0x8340) */ 1046 /************************************/ 1047 /* parDet10GStatus (Addr 0x8340) */ 1048 #define READ_PHYXGXS6_PARDET10G_STATr(_unit, _phy_ctrl, _val) \ 1049 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x10, (_val)) 1050 #define WRITE_PHYXGXS6_PARDET10G_STATr(_unit, _phy_ctrl, _val) \ 1051 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x10, (_val)) 1052 #define MODIFY_PHYXGXS6_PARDET10G_STATr(_unit, _phy_ctrl, _val, _mask) \ 1053 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x10, \ 1054 (_val), (_mask)) 1055 1056 /* parDet10GControl (Addr 0x8341) */ 1057 #define READ_PHYXGXS6_PARDET10G_CTRLr(_unit, _phy_ctrl, _val) \ 1058 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x11, (_val)) 1059 #define WRITE_PHYXGXS6_PARDET10G_CTRLr(_unit, _phy_ctrl, _val) \ 1060 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x11, (_val)) 1061 #define MODIFY_PHYXGXS6_PARDET10G_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1062 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x11, \ 1063 (_val), (_mask)) 1064 1065 /* parDet10GSigDet (Addr 0x8342) */ 1066 #define READ_PHYXGXS6_PARDET10G_SIGDETr(_unit, _phy_ctrl, _val) \ 1067 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x12, (_val)) 1068 #define WRITE_PHYXGXS6_PARDET10G_SIGDETr(_unit, _phy_ctrl, _val) \ 1069 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x12, (_val)) 1070 #define MODIFY_PHYXGXS6_PARDET10G_SIGDETr(_unit, _phy_ctrl, _val, _mask) \ 1071 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x12, \ 1072 (_val), (_mask)) 1073 1074 /* parDet10GLink (Addr 0x8343) */ 1075 #define READ_PHYXGXS6_PARDET10G_LINKr(_unit, _phy_ctrl, _val) \ 1076 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x13, (_val)) 1077 #define WRITE_PHYXGXS6_PARDET10G_LINKr(_unit, _phy_ctrl, _val) \ 1078 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x13, (_val)) 1079 #define MODIFY_PHYXGXS6_PARDET10G_LINKr(_unit, _phy_ctrl, _val, _mask) \ 1080 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x13, \ 1081 (_val), (_mask)) 1082 1083 /* parDet10GLosLink (Addr 0x8344) */ 1084 #define READ_PHYXGXS6_PARDET10G_LOSLINKr(_unit, _phy_ctrl, _val) \ 1085 PHYXGXS6_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x14, (_val)) 1086 #define WRITE_PHYXGXS6_PARDET10G_LOSLINKr(_unit, _phy_ctrl, _val) \ 1087 PHYXGXS6_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x14, (_val)) 1088 #define MODIFY_PHYXGXS6_PARDET10G_LOSLINKr(_unit, _phy_ctrl, _val, _mask) \ 1089 PHYXGXS6_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x14, \ 1090 (_val), (_mask)) 1091 1092 /* Reserved (Addr 0x8345 - 0x834E) */ 1093 1094 /******************************/ 1095 /* BAM Next Page (blk 0x8350) */ 1096 /******************************/ 1097 1098 #endif /* _PHY_XGXS6_H_ */