xgxs5.h (48324B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: xgxs.h 8 * Purpose: 10G 802.3ae Ethernet PHY 9 */ 10 11 #ifndef _PHY_XGXS5_H_ 12 #define _PHY_XGXS5_H_ 13 14 #include <soc/phy.h> 15 16 /* 10Gig XGMII/Serdes PHY Register definitions 17 * From Broadcom XGXS5 Core Documentation 18 */ 19 20 #define XGXS5_IEEE_CTRL_SW_RST (1 << 15) /* S/W Reset */ 21 #define XGXS5_IEEE_CTRL_LB_ENA (1 << 14) /* XGXS5 Local Loopback enable */ 22 #define XGXS5_IEEE_CTRL_SW_PD (1 << 13) /* S/W Powerdown */ 23 24 #define XGXS5_BLOCK_REG_SHIFT 0x03 /* Bits 4:9 of register selects blk*/ 25 26 27 #define XGXS5_BLOCK_0_ASI 0x00 /* Standard, default regs above */ 28 #define XGXS5_BLOCK_1_ASI 0x01 29 #define XGXS5_BLOCK_2_ASI 0x02 30 #define XGXS5_BLOCK_3_ASI 0x03 31 #define XGXS5_BLOCK_4_ASI 0x04 32 33 /* Bit defines for ANA register */ 34 #define XGXS5_ANA_HD (1 << 6) 35 #define XGXS5_ANA_FD (1 << 5) 36 #define XGXS5_ANA_PAUSE_NONE (0 << 7) 37 #define XGXS5_ANA_PAUSE_SYM (1 << 7) 38 #define XGXS5_ANA_PAUSE_ASYM (1 << 8) 39 #define XGXS5_ANA_PAUSE_MASK (3 << 7) 40 41 /* Auto-Negotiation Link-Partner Ability Register */ 42 #define XGXS5_ANP_NEXT_PG (1 << 15) 43 #define XGXS5_ANP_ACK (1 << 14) 44 #define XGXS5_ANP_RF_SHFT (12) /* Remote fault */ 45 #define XGXS5_ANP_RF_MASK (0x3000) 46 #define XGXS5_ANP_PAUSE_ASYM (1 << 8) 47 #define XGXS5_ANP_PAUSE_SYM (1 << 7) 48 #define XGXS5_ANP_HD (1 << 6) 49 #define XGXS5_ANP_FD (1 << 5) 50 51 52 /* If application want to use this header file for accessing PHY registers, 53 * simply redefine PHYXGXS5_REG macro to use BCM API as follows. 54 * 55 * #define SOC_PHY_REG_1000X BCM_PORT_PHY_REG_1000X 56 * 57 * #define PHYXGXS5_REG_READ(_unit, _port, _flags, _reg_bank, _reg_addr, _val) \ 58 * bcm_port_phy_get((_unit), (_port), 0, 59 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 60 * (_val)) 61 * 62 * #define PHYXGXS5_REG_WRITE(_unit, _port, _flags, _reg_bank, _reg_addr, _val) \ 63 * bcm_port_phy_set((_unit), (_port), 0, 64 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 65 * (_val)) 66 * 67 * #define PHYXGXS5_REG_MODIFY(_unit, _port, _flags, _reg_bank, _reg_addr, _val)\ 68 * do { \ 69 * return BCM_E_UNAVAIL; \ 70 * } while(0) 71 */ 72 73 74 /* XGXS5 register access */ 75 #define PHYXGXS5_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, \ 76 _reg_addr, _val) \ 77 phy_reg_xgxs_read((_unit), (_phy_ctrl), (_reg_bank), \ 78 (_reg_addr), (_val)) 79 #define PHYXGXS5_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, \ 80 _reg_addr, _val) \ 81 phy_reg_xgxs_write((_unit), (_phy_ctrl), (_reg_bank), \ 82 (_reg_addr), (_val)) 83 #define PHYXGXS5_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 84 _reg_addr, _val, _mask) \ 85 phy_reg_xgxs_modify((_unit), (_phy_ctrl), (_reg_bank), \ 86 (_reg_addr), (_val), (_mask)) 87 88 /****************************************/ 89 /* XAUI IEEE PMA/PMD Block (blk 0x0000) */ 90 /****************************************/ 91 92 /* XAUI MII Control Register (Addr 00h) */ 93 #define READ_PHYXGXS5_XAUI_MII_CTRLr(_unit, _phy_ctrl, _val) \ 94 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 95 #define WRITE_PHYXGXS5_XAUI_MII_CTRLr(_unit, _phy_ctrl, _val) \ 96 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 97 #define MODIFY_PHYXGXS5_XAUI_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 98 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 99 (_val), (_mask)) 100 101 /* XAUI MII Status Register (ADDR 01h) */ 102 #define READ_PHYXGXS5_XAUI_MII_STATr(_unit, _phy_ctrl, _val) \ 103 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 104 #define WRITE_PHYXGXS5_XAUI_MII_STATr(_unit, _phy_ctrl, _val) \ 105 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 106 #define MODIFY_PHYXGXS5_XAUI_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 107 PHYXGXS5_REG_MODIFY((_unit, _phy_ctrl), 0x00, 0x0000, 0x01, \ 108 (_val), (_mask)) 109 110 /* XAUI PHY Identifier Register (ADDR 02h) */ 111 #define READ_PHYXGXS5_XAUI_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 112 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 113 #define WRITE_PHYXGXS5_XAUI_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 114 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 115 #define MODIFY_PHYXGXS5_XAUI_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 116 PHYXGXS5_REG_MODIFY((_unit, _phy_ctrl), 0x00, 0x0000, 0x02, \ 117 (_val), (_mask)) 118 119 /* XAUI PHY Identifier Register (ADDR 03h) */ 120 #define READ_PHYXGXS5_XAUI_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 121 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 122 #define WRITE_PHYXGXS5_XAUI_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 123 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 124 #define MODIFY_PHYXGXS5_XAUI_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 125 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 126 (_val), (_mask)) 127 128 /* IEEE Speed Ability (Addr 04h) */ 129 /* IEEE Dev In Package 1 (Addr 05h) */ 130 /* IEEE Dev In Package 2 (Addr 06h) */ 131 /* IEEE Control 2 (Addr 07h) */ 132 /* IEEE Status 2 (Addr 08h) */ 133 134 /* IEEE Tx Disable (Addr 09h) */ 135 #define READ_PHYXGXS5_XAUI_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 136 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 137 #define WRITE_PHYXGXS5_XAUI_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 138 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 139 #define MODIFY_PHYXGXS5_XAUI_TX_DISABLEr(_unit, _phy_ctrl, _val, _mask) \ 140 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 141 (_val), (_mask)) 142 143 /* IEEE RxSigDet (Addr 0Ah) */ 144 /* IEEE PMDExtAbil (Addr 0Bh) */ 145 /* Reserved (Addr 0Ch-0Eh) */ 146 147 /****************************/ 148 /* IEEE1 Block (blk 0x0010) */ 149 /****************************/ 150 /* Reserved (Addr 0x0010 - 0x0017) */ 151 152 /* Lane Status (Addr 0x0018) */ 153 #define READ_PHYXGXS5_IEEE1_LANE_STATr(_unit, _phy_ctrl, _val) \ 154 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0, \ 155 0x0010, 0x08, (_val)) 156 #define WRITE_PHYXGXS5_IEEE1_LANE_STATr(_unit, _phy_ctrl, _val) \ 157 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0, \ 158 0x0010, 0x08, (_val)) 159 #define MODIFY_PHYXGXS5_IEEE1_LANE_STATr(_unit, _phy_ctrl, _val, _mask) \ 160 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0, \ 161 0x0010, 0x08, (_val), (_mask)) 162 163 /* IEEE Test Control (Addr 0x0019) */ 164 /* Reserved (Addr 0x001A - 0x001E) */ 165 166 /****************************/ 167 /* XGXS5 Block 0 (blk 0x8000) */ 168 /****************************/ 169 /* XGXS5 Control (Addr 0x8000) */ 170 #define READ_PHYXGXS5_BLK0_CTRLr(_unit, _phy_ctrl, _val) \ 171 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x10, (_val)) 172 #define WRITE_PHYXGXS5_BLK0_CTRLr(_unit, _phy_ctrl, _val) \ 173 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x10, (_val)) 174 #define MODIFY_PHYXGXS5_BLK0_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 175 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x10, \ 176 (_val), (_mask)) 177 178 /* XGXS5 Status (Addr 0x8001) */ 179 #define READ_PHYXGXS5_BLK0_STATr(_unit, _phy_ctrl, _val) \ 180 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x11, (_val)) 181 #define WRITE_PHYXGXS5_BLK0_STATr(_unit, _phy_ctrl, _val) \ 182 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x11, (_val)) 183 #define MODIFY_PHYXGXS5_BLK0_STATr(_unit, _phy_ctrl, _val, _mask) \ 184 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x11, \ 185 (_val), (_mask)) 186 187 /* XGMII Idle (Addr 0x8002) */ 188 #define READ_PHYXGXS5_BLK0_XGMII_IDLEr(_unit, _phy_ctrl, _val) \ 189 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x12, (_val)) 190 #define WRITE_PHYXGXS5_BLK0_XGMII_IDLEr(_unit, _phy_ctrl, _val) \ 191 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x12, (_val)) 192 #define MODIFY_PHYXGXS5_BLK0_XGMII_IDLEr(_unit, _phy_ctrl, _val, _mask) \ 193 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x12, \ 194 (_val), (_mask)) 195 196 /* XGMII Sync (Addr 0x8003) */ 197 #define READ_PHYXGXS5_BLK0_XGMII_SYNCr(_unit, _phy_ctrl, _val) \ 198 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x13, (_val)) 199 #define WRITE_PHYXGXS5_BLK0_XGMII_SYNCr(_unit, _phy_ctrl, _val) \ 200 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x13, (_val)) 201 #define MODIFY_PHYXGXS5_BLK0_XGMII_SYNCr(_unit, _phy_ctrl, _val, _mask) \ 202 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x13, \ 203 (_val), (_mask)) 204 205 /* XGMII Skip (Addr 0x8004) */ 206 #define READ_PHYXGXS5_BLK0_XGMII_SKIPr(_unit, _phy_ctrl, _val) \ 207 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x14, (_val)) 208 #define WRITE_PHYXGXS5_BLK0_XGMII_SKIPr(_unit, _phy_ctrl, _val) \ 209 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x14, (_val)) 210 #define MODIFY_PHYXGXS5_BLK0_XGMII_SKIPr(_unit, _phy_ctrl, _val, _mask) \ 211 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x14, \ 212 (_val), (_mask)) 213 214 /* XGMII Sop Eop (Addr 0x8005) */ 215 #define READ_PHYXGXS5_BLK0_XGMII_SOP_EOPr(_unit, _phy_ctrl, _val) \ 216 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x15, (_val)) 217 #define WRITE_PHYXGXS5_BLK0_XGMII_SOP_EOPr(_unit, _phy_ctrl, _val) \ 218 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x15, (_val)) 219 #define MODIFY_PHYXGXS5_BLK0_XGMII_SOP_EOPr(_unit, _phy_ctrl, _val, _mask) \ 220 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x15, \ 221 (_val), (_mask)) 222 223 /* XGMII Align (Addr 0x8006) */ 224 #define READ_PHYXGXS5_BLK0_XGMII_ALIGNr(_unit, _phy_ctrl, _val) \ 225 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x16, (_val)) 226 #define WRITE_PHYXGXS5_BLK0_XGMII_ALIGNr(_unit, _phy_ctrl, _val) \ 227 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x16, (_val)) 228 #define MODIFY_PHYXGXS5_BLK0_XGMII_ALIGNr(_unit, _phy_ctrl, _val, _mask) \ 229 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x16, \ 230 (_val), (_mask)) 231 232 /* XGMII R Control (Addr 0x8007) */ 233 #define READ_PHYXGXS5_BLK0_XGMII_RCTRLr(_unit, _phy_ctrl, _val) \ 234 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x17, (_val)) 235 #define WRITE_PHYXGXS5_BLK0_XGMII_RCTRLr(_unit, _phy_ctrl, _val) \ 236 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x17, (_val)) 237 #define MODIFY_PHYXGXS5_BLK0_XGMII_RCTRLr(_unit, _phy_ctrl, _val, _mask) \ 238 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x17, \ 239 (_val), (_mask)) 240 241 /* XGMII T Control (Addr 0x8008) */ 242 #define READ_PHYXGXS5_BLK0_XGMII_TCTRLr(_unit, _phy_ctrl, _val) \ 243 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x18, (_val)) 244 #define WRITE_PHYXGXS5_BLK0_XGMII_TCTRLr(_unit, _phy_ctrl, _val) \ 245 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x18, (_val)) 246 #define MODIFY_PHYXGXS5_BLK0_XGMII_TCTRLr(_unit, _phy_ctrl, _val, _mask) \ 247 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x18, \ 248 (_val), (_mask)) 249 250 /* XGMII Swap (Addr 0x8009) */ 251 #define READ_PHYXGXS5_BLK0_XGMII_SWAPr(_unit, _phy_ctrl, _val) \ 252 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x19, (_val)) 253 #define WRITE_PHYXGXS5_BLK0_XGMII_SWAPr(_unit, _phy_ctrl, _val) \ 254 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x19, (_val)) 255 #define MODIFY_PHYXGXS5_BLK0_XGMII_SWAPr(_unit, _phy_ctrl, _val, _mask) \ 256 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x19, \ 257 (_val), (_mask)) 258 259 /* IssLsid (Addr 0x800A) */ 260 #define READ_PHYXGXS5_BLK0_ISS_LSIDr(_unit, _phy_ctrl, _val) \ 261 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1A, (_val)) 262 #define WRITE_PHYXGXS5_BLK0_ISS_LSIDr(_unit, _phy_ctrl, _val) \ 263 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1A, (_val)) 264 #define MODIFY_PHYXGXS5_BLK0_ISS_LSIDr(_unit, _phy_ctrl, _val, _mask) \ 265 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1A, \ 266 (_val), (_mask)) 267 268 /* IssTinfo (Addr 0x800B) */ 269 #define READ_PHYXGXS5_BLK0_ISS_TINFOr(_unit, _phy_ctrl, _val) \ 270 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1B, (_val)) 271 #define WRITE_PHYXGXS5_BLK0_ISS_TINFOr(_unit, _phy_ctrl, _val) \ 272 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1B, (_val)) 273 #define MODIFY_PHYXGXS5_BLK0_ISS_TINFOr(_unit, _phy_ctrl, _val, _mask) \ 274 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1B, \ 275 (_val), (_mask)) 276 277 /* IssRinfo (Addr 0x800C) */ 278 #define READ_PHYXGXS5_BLK0_ISS_RINFOr(_unit, _phy_ctrl, _val) \ 279 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1C, (_val)) 280 #define WRITE_PHYXGXS5_BLK0_ISS_RINFOr(_unit, _phy_ctrl, _val) \ 281 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1C, (_val)) 282 #define MODIFY_PHYXGXS5_BLK0_ISS_RINFOr(_unit, _phy_ctrl, _val, _mask) \ 283 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1C, \ 284 (_val), (_mask)) 285 286 /* CX4 SigDet Cnt (Addr 0x800D) */ 287 #define READ_PHYXGXS5_BLK0_CX4_SIGDET_COUNTERr(_unit, _phy_ctrl, _val) \ 288 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1D, (_val)) 289 #define WRITE_PHYXGXS5_BLK0_CX4_SIGDET_COUNTERr(_unit, _phy_ctrl, _val) \ 290 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1D, (_val)) 291 #define MODIFY_PHYXGXS5_BLK0_CX4_SIGDET_COUNTERr(_unit, _phy_ctrl, _val, \ 292 _mask) \ 293 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1D, \ 294 (_val), (_mask)) 295 296 /* Misc Control 1 (Addr 0x800E) */ 297 #define READ_PHYXGXS5_BLK0_MISC_CTRL1r(_unit, _phy_ctrl, _val) \ 298 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1E, (_val)) 299 #define WRITE_PHYXGXS5_BLK0_MISC_CTRL1r(_unit, _phy_ctrl, _val) \ 300 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1E, (_val)) 301 #define MODIFY_PHYXGXS5_BLK0_MISC_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 302 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1E, \ 303 (_val), (_mask)) 304 305 /*****************************/ 306 /* XGXS5 Block 1 (blk 0x8010) */ 307 /*****************************/ 308 /* deskew (Addr 0x8010) */ 309 #define READ_PHYXGXS5_BLK1_DESKEWr(_unit, _phy_ctrl, _val) \ 310 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x10, (_val)) 311 #define WRITE_PHYXGXS5_BLK1_DESKEWr(_unit, _phy_ctrl, _val) \ 312 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x10, (_val)) 313 #define MODIFY_PHYXGXS5_BLK1_DESKEWr(_unit, _phy_ctrl, _val, _mask) \ 314 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x10, \ 315 (_val), (_mask)) 316 317 /* link (Addr 0x8011) */ 318 #define READ_PHYXGXS5_BLK1_LINKr(_unit, _phy_ctrl, _val) \ 319 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x011, (_val)) 320 #define WRITE_PHYXGXS5_BLK1_LINKr(_unit, _phy_ctrl, _val) \ 321 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x011,(_val)) 322 #define MODIFY_PHYXGXS5_BLK1_LINKr(_unit, _phy_ctrl, _val, _mask) \ 323 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x011, \ 324 (_val), (_mask)) 325 326 /* testRx (Addr 0x8012) */ 327 #define READ_PHYXGXS5_BLK1_TESTRXr(_unit, _phy_ctrl, _val) \ 328 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x012, (_val)) 329 #define WRITE_PHYXGXS5_BLK1_TESTRXr(_unit, _phy_ctrl, _val) \ 330 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x012,(_val)) 331 #define MODIFY_PHYXGXS5_BLK1_TESTRXr(_unit, _phy_ctrl, _val, _mask) \ 332 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x012, \ 333 (_val), (_mask)) 334 335 /* testTx (Addr 0x8013) */ 336 337 /* testXg (Addr 0x8014) */ 338 339 /* Reserved (Addr 0x8015) */ 340 341 /* laneCtrl1 (Addr 0x8016) */ 342 #define READ_PHYXGXS5_BLK1_LANE_CTRL1r(_unit, _phy_ctrl, _val) \ 343 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x16, (_val)) 344 #define WRITE_PHYXGXS5_BLK1_LANE_CTRL1r(_unit, _phy_ctrl, _val) \ 345 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x16, (_val)) 346 #define MODIFY_PHYXGXS5_BLK1_LANE_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 347 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x16, \ 348 (_val), (_mask)) 349 350 /* laneCtrl2 (Addr 0x8017) */ 351 #define READ_PHYXGXS5_BLK1_LANE_CTRL2r(_unit, _phy_ctrl, _val) \ 352 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x17, (_val)) 353 #define WRITE_PHYXGXS5_BLK1_LANE_CTRL2r(_unit, _phy_ctrl, _val) \ 354 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x17, (_val)) 355 #define MODIFY_PHYXGXS5_BLK1_LANE_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 356 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x17, \ 357 (_val), (_mask)) 358 359 /* laneCtrl3 (Addr 0x8018) */ 360 #define READ_PHYXGXS5_BLK1_LANE_CTRL3r(_unit, _phy_ctrl, _val) \ 361 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x18, (_val)) 362 #define WRITE_PHYXGXS5_BLK1_LANE_CTRL3r(_unit, _phy_ctrl, _val) \ 363 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x18, (_val)) 364 #define MODIFY_PHYXGXS5_BLK1_LANE_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 365 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x18, \ 366 (_val), (_mask)) 367 368 /* lanePrbs (Addr 0x8019) */ 369 370 /* laneTest (Addr 0x801A) */ 371 #define READ_PHYXGXS5_BLK1_LANE_TESTr(_unit, _phy_ctrl, _val) \ 372 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x1A, (_val)) 373 #define WRITE_PHYXGXS5_BLK1_LANE_TESTr(_unit, _phy_ctrl, _val) \ 374 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x1A, (_val)) 375 #define MODIFY_PHYXGXS5_BLK1_LANE_TESTr(_unit, _phy_ctrl, _val, _mask) \ 376 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x1A, \ 377 (_val), (_mask)) 378 379 /* IssRevnt (Addr 0x801B) */ 380 381 /* dskevnt (Addr 0x801C) */ 382 383 /* Aerrevnt (Addr 0x801D) */ 384 385 /* chcmpevnt (Addr 0x801E) */ 386 387 388 /****************************/ 389 /* 10G Tx BERT (blk 0x8020) */ 390 /****************************/ 391 392 393 /****************************/ 394 /* 10G Rx BERT (blk 0x8030) */ 395 /****************************/ 396 397 /*************************/ 398 /* BcstBert (blk 0x8040) */ 399 /*************************/ 400 401 /********************/ 402 /* PLL (blk 0x8050) */ 403 /********************/ 404 405 /* PLL STATUS (Addr 0x8050) */ 406 #define READ_PHYXGXS5_PLL_STATr(_unit, _phy_ctrl, _val) \ 407 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x10, (_val)) 408 #define WRITE_PHYXGXS5_PLL_STATr(_unit, _phy_ctrl, _val) \ 409 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x10, (_val)) 410 #define MODIFY_PHYXGXS5_PLL_STATr(_unit, _phy_ctrl, _val, _mask) \ 411 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x10, \ 412 (_val), (_mask)) 413 414 /* PLL Control (Addr 0x8051) */ 415 #define READ_PHYXGXS5_PLL_CTRLr(_unit, _phy_ctrl, _val) \ 416 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x11, (_val)) 417 #define WRITE_PHYXGXS5_PLL_CTRLr(_unit, _phy_ctrl, _val) \ 418 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x11, (_val)) 419 #define MODIFY_PHYXGXS5_PLL_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 420 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x11, \ 421 (_val), (_mask)) 422 423 /* PLL Timer 1 (Addr 0x8052) */ 424 #define READ_PHYXGXS5_PLL_TIMER1r(_unit, _phy_ctrl, _val) \ 425 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x12, (_val)) 426 #define WRITE_PHYXGXS5_PLL_TIMER1r(_unit, _phy_ctrl, _val) \ 427 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x12, (_val)) 428 #define MODIFY_PHYXGXS5_PLL_TIMER1r(_unit, _phy_ctrl, _val, _mask) \ 429 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x12, \ 430 (_val), (_mask)) 431 432 /* PLL Timer 2 (Addr 0x8053) */ 433 #define READ_PHYXGXS5_PLL_TIMER2r(_unit, _phy_ctrl, _val) \ 434 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x13, (_val)) 435 #define WRITE_PHYXGXS5_PLL_TIMER2r(_unit, _phy_ctrl, _val) \ 436 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x13, (_val)) 437 #define MODIFY_PHYXGXS5_PLL_TIMER2r(_unit, _phy_ctrl, _val, _mask) \ 438 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x13, \ 439 (_val), (_mask)) 440 441 /* PLL Timer 3 (Addr 0x8054) */ 442 #define READ_PHYXGXS5_PLL_TIMER3r(_unit, _phy_ctrl, _val) \ 443 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x14, (_val)) 444 #define WRITE_PHYXGXS5_PLL_TIMER3r(_unit, _phy_ctrl, _val) \ 445 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x14, (_val)) 446 #define MODIFY_PHYXGXS5_PLL_TIMER3r(_unit, _phy_ctrl, _val, _mask) \ 447 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x14, \ 448 (_val), (_mask)) 449 450 /* CAP Control (Addr 0x8055) */ 451 #define READ_PHYXGXS5_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val) \ 452 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x15, (_val)) 453 #define WRITE_PHYXGXS5_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val) \ 454 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x15, (_val)) 455 #define MODIFY_PHYXGXS5_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 456 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x15, \ 457 (_val), (_mask)) 458 459 /* AMP Control (Addr 0x8056) */ 460 #define READ_PHYXGXS5_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val) \ 461 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x16, (_val)) 462 #define WRITE_PHYXGXS5_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val) \ 463 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x16, (_val)) 464 #define MODIFY_PHYXGXS5_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 465 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x16, \ 466 (_val), (_mask)) 467 468 /* Freq Det Counter (Addr 0x8057) */ 469 #define READ_PHYXGXS5_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val) \ 470 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x17, (_val)) 471 #define WRITE_PHYXGXS5_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val) \ 472 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x17, (_val)) 473 #define MODIFY_PHYXGXS5_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 474 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x17, \ 475 (_val), (_mask)) 476 477 /* PLL Astatus 1 (Addr 0x8058) */ 478 #define READ_PHYXGXS5_PLL_ASTAT1r(_unit, _phy_ctrl, _val) \ 479 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x18, (_val)) 480 #define WRITE_PHYXGXS5_PLL_ASTAT1r(_unit, _phy_ctrl, _val) \ 481 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x18, (_val)) 482 #define MODIFY_PHYXGXS5_PLL_ASTAT1r(_unit, _phy_ctrl, _val, _mask) \ 483 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x18, \ 484 (_val), (_mask)) 485 486 /* PLL Astatus 2 (Addr 0x8059) */ 487 #define READ_PHYXGXS5_PLL_ASTAT2r(_unit, _phy_ctrl, _val) \ 488 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x19, (_val)) 489 #define WRITE_PHYXGXS5_PLL_ASTAT2r(_unit, _phy_ctrl, _val) \ 490 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x19, (_val)) 491 #define MODIFY_PHYXGXS5_PLL_ASTAT2r(_unit, _phy_ctrl, _val, _mask) \ 492 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x19, \ 493 (_val), (_mask)) 494 495 /* PLL Clock Gen (Addr 0x805A) */ 496 #define READ_PHYXGXS5_PLL_CLK_GENr(_unit, _phy_ctrl, _val) \ 497 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1A, (_val)) 498 #define WRITE_PHYXGXS5_PLL_CLK_GENr(_unit, _phy_ctrl, _val) \ 499 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1A, (_val)) 500 #define MODIFY_PHYXGXS5_PLL_CLK_GENr(_unit, _phy_ctrl, _val, _mask) \ 501 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1A, \ 502 (_val), (_mask)) 503 504 /* PLL Ndiv (Addr 0x805B) */ 505 #define READ_PHYXGXS5_PLL_NDIVr(_unit, _phy_ctrl, _val) \ 506 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1B, (_val)) 507 #define WRITE_PHYXGXS5_PLL_NDIVr(_unit, _phy_ctrl, _val) \ 508 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1B, (_val)) 509 #define MODIFY_PHYXGXS5_PLL_NDIVr(_unit, _phy_ctrl, _val, _mask) \ 510 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1B, \ 511 (_val), (_mask)) 512 513 /* PLL Bglqp (Addr 0x805C) */ 514 #define READ_PHYXGXS5_PLL_BGLQPr(_unit, _phy_ctrl, _val) \ 515 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1C, (_val)) 516 #define WRITE_PHYXGXS5_PLL_BGLQP(_unit, _phy_ctrl, _val) \ 517 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1C, (_val)) 518 #define MODIFY_PHYXGXS5_PLL_BGLQPr(_unit, _phy_ctrl, _val, _mask) \ 519 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1C, \ 520 (_val), (_mask)) 521 522 /* PLL Test Kvh (Addr 0x805D) */ 523 #define READ_PHYXGXS5_PLL_TEST_KVHr(_unit, _phy_ctrl, _val) \ 524 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1D, (_val)) 525 #define WRITE_PHYXGXS5_PLL_TEST_KVHr(_unit, _phy_ctrl, _val) \ 526 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1D, (_val)) 527 #define MODIFY_PHYXGXS5_PLL_TEST_KVHr(_unit, _phy_ctrl, _val, _mask) \ 528 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1D, \ 529 (_val), (_mask)) 530 531 /* PLL AControl 5 (Addr 0x805E) */ 532 #define READ_PHYXGXS5_PLL_ACTRL5r(_unit, _phy_ctrl, _val) \ 533 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1E, (_val)) 534 #define WRITE_PHYXGXS5_PLL_ACTRL5r(_unit, _phy_ctrl, _val) \ 535 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1E, (_val)) 536 #define MODIFY_PHYXGXS5_PLL_ACTRL5r(_unit, _phy_ctrl, _val, _mask) \ 537 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1E, \ 538 (_val), (_mask)) 539 540 541 /********************/ 542 /* TX0 (blk 0x8060) */ 543 /********************/ 544 545 /********************/ 546 /* TX1 (blk 0x8070) */ 547 /********************/ 548 549 550 /********************/ 551 /* TX2 (blk 0x8080) */ 552 /********************/ 553 554 555 /********************/ 556 /* TX3 (blk 0x8090) */ 557 /********************/ 558 559 560 /********************/ 561 /* TX All (blk 0x80A0) */ 562 /********************/ 563 /* Tx AStatus 0 (Addr 0x80A0) */ 564 /* Tx AControl 0 (Addr 0x80A1) */ 565 #define READ_PHYXGXS5_TXALL_ACTRL0r(_unit, _phy_ctrl, _val) \ 566 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x11, (_val)) 567 #define WRITE_PHYXGXS5_TXALL_ACTRL0r(_unit, _phy_ctrl, _val) \ 568 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x11, (_val)) 569 #define MODIFY_PHYXGXS5_TXALL_ACTRL0r(_unit, _phy_ctrl, _val, _mask) \ 570 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x11, \ 571 (_val), (_mask)) 572 573 /* Tx mdata 0 (Addr 0x80A2) */ 574 /* Tx mdata 1 (Addr 0x80A3) */ 575 /* Tx AStatus 1 (Addr 0x80A4) */ 576 /* Tx BgVcm (Addr 0x80A5) */ 577 /* Tx Ibuff 1T2T (Addr 0x80A6) */ 578 579 /* Tx Driver (Addr 0x80A7) */ 580 #define READ_PHYXGXS5_TXALL_DRIVERr(_unit, _phy_ctrl, _val) \ 581 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x17, (_val)) 582 #define WRITE_PHYXGXS5_TXALL_DRIVERr(_unit, _phy_ctrl, _val) \ 583 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x17, (_val)) 584 #define MODIFY_PHYXGXS5_TXALL_DRIVERr(_unit, _phy_ctrl, _val, _mask) \ 585 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x17, \ 586 (_val), (_mask)) 587 588 /* Reserved (Addr 0x80A8 - 0x80AE) */ 589 590 /********************/ 591 /* RX0 (blk 0x80B0) */ 592 /********************/ 593 594 595 /********************/ 596 /* RX1 (blk 0x80C0) */ 597 /********************/ 598 599 600 /********************/ 601 /* RX2 (blk 0x80D0) */ 602 /********************/ 603 604 605 /********************/ 606 /* RX3 (blk 0x80E0) */ 607 /********************/ 608 609 610 /***********************/ 611 /* RX All (blk 0x80F0) */ 612 /***********************/ 613 /* Rx Status (Address 0x80F0) */ 614 #define READ_PHYXGXS5_RXALL_STATr(_unit, _phy_ctrl, _val) \ 615 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x10, (_val)) 616 #define WRITE_PHYXGXS5_RXALL_STATr(_unit, _phy_ctrl, _val) \ 617 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x10, (_val)) 618 #define MODIFY_PHYXGXS5_RXALL_STATr(_unit, _phy_ctrl, _val, _mask) \ 619 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x10, \ 620 (_val), (_mask)) 621 622 /* Rx Control (Address 0x80F1) */ 623 #define READ_PHYXGXS5_RXALL_CTRLr(_unit, _phy_ctrl, _val) \ 624 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x11, (_val)) 625 #define WRITE_PHYXGXS5_RXALL_CTRLr(_unit, _phy_ctrl, _val) \ 626 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x11, (_val)) 627 #define MODIFY_PHYXGXS5_RXALL_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 628 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x11, \ 629 (_val), (_mask)) 630 631 /* Rx Timer 1 (Address 0x80F2) */ 632 #define READ_PHYXGXS5_RXALL_TIMER1r(_unit, _phy_ctrl, _val) \ 633 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x12, (_val)) 634 #define WRITE_PHYXGXS5_RXALL_TIMER1r(_unit, _phy_ctrl, _val) \ 635 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x12, (_val)) 636 #define MODIFY_PHYXGXS5_RXALL_TIMER1r(_unit, _phy_ctrl, _val, _mask) \ 637 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x12, \ 638 (_val), (_mask)) 639 640 /* Rx Timer 2 (Address 0x80F3) */ 641 #define READ_PHYXGXS5_RXALL_TIMER2r(_unit, _phy_ctrl, _val) \ 642 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x13, (_val)) 643 #define WRITE_PHYXGXS5_RXALL_TIMER2r(_unit, _phy_ctrl, _val) \ 644 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x13, (_val)) 645 #define MODIFY_PHYXGXS5_RXALL_TIMER2r(_unit, _phy_ctrl, _val, _mask) \ 646 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x13, \ 647 (_val), (_mask)) 648 649 /* Rx SigDet (Address 0x80F4) */ 650 #define READ_PHYXGXS5_RXALL_SIG_DETr(_unit, _phy_ctrl, _val) \ 651 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x14, (_val)) 652 #define WRITE_PHYXGXS5_RXALL_SIG_DETr(_unit, _phy_ctrl, _val) \ 653 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x14, (_val)) 654 #define MODIFY_PHYXGXS5_RXALL_SIG_DETr(_unit, _phy_ctrl, _val, _mask) \ 655 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x14, \ 656 (_val), (_mask)) 657 658 /* Rx CdrPhase (Address 0x80F5) */ 659 #define READ_PHYXGXS5_RXALL_CDR_PHASEr(_unit, _phy_ctrl, _val) \ 660 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x15, (_val)) 661 #define WRITE_PHYXGXS5_RXALL_CDR_PHASEr(_unit, _phy_ctrl, _val) \ 662 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x15, (_val)) 663 #define MODIFY_PHYXGXS5_RXALL_CDR_PHASEr(_unit, _phy_ctrl, _val, _mask) \ 664 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x15, \ 665 (_val), (_mask)) 666 667 /* Rx CdrFreq (Address 0x80F6) */ 668 #define READ_PHYXGXS5_RXALL_CDR_FREQr(_unit, _phy_ctrl, _val) \ 669 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x16, (_val)) 670 #define WRITE_PHYXGXS5_RXALL_CDR_FREQr(_unit, _phy_ctrl, _val) \ 671 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x16, (_val)) 672 #define MODIFY_PHYXGXS5_RXALL_CDR_FREQr(_unit, _phy_ctrl, _val, _mask) \ 673 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x16, \ 674 (_val), (_mask)) 675 676 /* Rx EqConfig (Address 0x80F7) */ 677 #define READ_PHYXGXS5_RXALL_EQ_CONFIGr(_unit, _phy_ctrl, _val) \ 678 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x17, (_val)) 679 #define WRITE_PHYXGXS5_RXALL_EQ_CONFIGr(_unit, _phy_ctrl, _val) \ 680 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x17, (_val)) 681 #define MODIFY_PHYXGXS5_RXALL_EQ_CONFIGr(_unit, _phy_ctrl, _val, _mask) \ 682 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x17, \ 683 (_val), (_mask)) 684 685 /* Rx EqForce (Address 0x80F8) */ 686 #define READ_PHYXGXS5_RXALL_EQ_FORCEr(_unit, _phy_ctrl, _val) \ 687 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x18, (_val)) 688 #define WRITE_PHYXGXS5_RXALL_EQ_FORCEr(_unit, _phy_ctrl, _val) \ 689 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x18, (_val)) 690 #define MODIFY_PHYXGXS5_RXALL_EQ_FORCEr(_unit, _phy_ctrl, _val, _mask) \ 691 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x18, \ 692 (_val), (_mask)) 693 694 /* Rx Control 1G (Address 0x80F9) */ 695 #define READ_PHYXGXS5_RXALL_CTRL_1Gr(_unit, _phy_ctrl, _val) \ 696 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x19, (_val)) 697 #define WRITE_PHYXGXS5_RXALL_CTRL_1Gr(_unit, _phy_ctrl, _val) \ 698 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x19, (_val)) 699 #define MODIFY_PHYXGXS5_RXALL_CTRL_1Gr(_unit, _phy_ctrl, _val, _mask) \ 700 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x19, \ 701 (_val), (_mask)) 702 703 /* Rx Control PCIE (Address 0x80FA) */ 704 #define READ_PHYXGXS5_RXALL_CTRL_PCIEr(_unit, _phy_ctrl, _val) \ 705 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1A, (_val)) 706 #define WRITE_PHYXGXS5_RXALL_CTRL_PCIEr(_unit, _phy_ctrl, _val) \ 707 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1A, (_val)) 708 #define MODIFY_PHYXGXS5_RXALL_CTRL_PCIEr(_unit, _phy_ctrl, _val, _mask) \ 709 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1A, \ 710 (_val), (_mask)) 711 712 /* Rx Astatus (Address 0x80FB) */ 713 #define READ_PHYXGXS5_RXALL_ASTATr(_unit, _phy_ctrl, _val) \ 714 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1B, (_val)) 715 #define WRITE_PHYXGXS5_RXALL_ASTATr(_unit, _phy_ctrl, _val) \ 716 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1B, (_val)) 717 #define MODIFY_PHYXGXS5_RXALL_ASTATr(_unit, _phy_ctrl, _val, _mask) \ 718 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1B, \ 719 (_val), (_mask)) 720 721 /* Rx Eq Boost (Address 0x80FC) */ 722 #define READ_PHYXGXS5_RXALL_EQ_BOOSTr(_unit, _phy_ctrl, _val) \ 723 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1C, (_val)) 724 #define WRITE_PHYXGXS5_RXALL_EQ_BOOSTr(_unit, _phy_ctrl, _val) \ 725 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1C, (_val)) 726 #define MODIFY_PHYXGXS5_RXALL_EQ_BOOSTr(_unit, _phy_ctrl, _val, _mask) \ 727 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1C, \ 728 (_val), (_mask)) 729 730 /* Rx lb Data Eq (Address 0x80FD) */ 731 #define READ_PHYXGXS5_RXALL_LB_DATA_EQr(_unit, _phy_ctrl, _val) \ 732 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1D, (_val)) 733 #define WRITE_PHYXGXS5_RXALL_LB_DATA_EQr(_unit, _phy_ctrl, _val) \ 734 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1D, (_val)) 735 #define MODIFY_PHYXGXS5_RXALL_LB_DATA_EQr(_unit, _phy_ctrl, _val, _mask) \ 736 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1D, \ 737 (_val), (_mask)) 738 739 /* Rx lb ADC Buff (Address 0x80FE) */ 740 #define READ_PHYXGXS5_RXALL_LB_ADC_BUFFr(_unit, _phy_ctrl, _val) \ 741 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1E, (_val)) 742 #define WRITE_PHYXGXS5_RXALL_LB_ADC_BUFFr(_unit, _phy_ctrl, _val) \ 743 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1E, (_val)) 744 #define MODIFY_PHYXGXS5_RXALL_LB_ADC_BUFFr(_unit, _phy_ctrl, _val, _mask) \ 745 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1E, \ 746 (_val), (_mask)) 747 748 /*****************************/ 749 /* XGXS5 Block 2 (blk 0x8100) */ 750 /*****************************/ 751 /* Rx Lane Swap (Addr 0x8100) */ 752 #define READ_PHYXGXS5_BLK2_RX_LANE_SWAPr(_unit, _phy_ctrl, _val) \ 753 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8100, 0x10, (_val)) 754 #define WRITE_PHYXGXS5_BLK2_RX_LANE_SWAPr(_unit, _phy_ctrl, _val) \ 755 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8100, 0x10, (_val)) 756 #define MODIFY_PHYXGXS5_BLK2_RX_LANE_SWAPr(_unit, _phy_ctrl, _val, _mask) \ 757 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8100, 0x10, \ 758 (_val), (_mask)) 759 760 /* Tx Lane Swap (Addr 0x8101) */ 761 #define READ_PHYXGXS5_BLK2_TX_LANE_SWAPr(_unit, _phy_ctrl, _val) \ 762 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8100, 0x11, (_val)) 763 #define WRITE_PHYXGXS5_BLK2_TX_LANE_SWAPr(_unit, _phy_ctrl, _val) \ 764 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8100, 0x11, (_val)) 765 #define MODIFY_PHYXGXS5_BLK2_TX_LANE_SWAPr(_unit, _phy_ctrl, _val, _mask) \ 766 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8100, 0x11, \ 767 (_val), (_mask)) 768 769 /* QsetLns01 (Addr 0x8102) */ 770 /* QsetLns23 (Addr 0x8103) */ 771 /* Unicore Mode 10G (Addr 0x8104) */ 772 /* Reserved (Addr 0x8105 - 0x810E) */ 773 774 /*****************************/ 775 /* In Band MDIO (blk 0x8110) */ 776 /*****************************/ 777 778 779 /**************************/ 780 /* GP Status (blk 0x8120) */ 781 /**************************/ 782 783 784 /*******************************/ 785 /* SerDes Digital (blk 0x8300) */ 786 /*******************************/ 787 788 /* 1000XControl1 (Addr 0x8300) */ 789 #define READ_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 790 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x10, (_val)) 791 #define WRITE_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 792 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x10, (_val)) 793 #define MODIFY_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL1r(_unit, _phy_ctrl, \ 794 _val, _mask) \ 795 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x10, \ 796 (_val), (_mask)) 797 798 /* 1000XControl2 (Addr 0x8301) */ 799 #define READ_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 800 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x11, (_val)) 801 #define WRITE_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 802 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x11, (_val)) 803 #define MODIFY_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL2r(_unit, _phy_ctrl, \ 804 _val, _mask) \ 805 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x11, \ 806 (_val), (_mask)) 807 808 /* 1000XControl3 (Addr 0x8302) */ 809 #define READ_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 810 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x12, (_val)) 811 #define WRITE_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 812 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x12, (_val)) 813 #define MODIFY_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL3r(_unit, _phy_ctrl, \ 814 _val, _mask) \ 815 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x12, \ 816 (_val), (_mask)) 817 818 /* 1000XControl4 (Addr 0x8303) */ 819 #define READ_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 820 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x13, (_val)) 821 #define WRITE_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 822 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x13, (_val)) 823 #define MODIFY_PHYXGXS5_SERDES_DIGITAL_1000X_CTRL4r(_unit, _phy_ctrl, \ 824 _val, _mask) \ 825 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x13, \ 826 (_val), (_mask)) 827 828 /* 1000XStatus1 (Addr 0x8304) */ 829 #define READ_PHYXGXS5_SERDES_DIGITAL_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 830 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x14, (_val)) 831 #define WRITE_PHYXGXS5_SERDES_DIGITAL_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 832 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x14, (_val)) 833 #define MODIFY_PHYXGXS5_SERDES_DIGITAL_1000X_STAT1r(_unit, _phy_ctrl, \ 834 _val, _mask) \ 835 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x14, \ 836 (_val), (_mask)) 837 838 /* 1000XStatus2 (Addr 0x8305) */ 839 #define READ_PHYXGXS5_SERDES_DIGITAL_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 840 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x15, (_val)) 841 #define WRITE_PHYXGXS5_SERDES_DIGITAL_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 842 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x15, (_val)) 843 #define MODIFY_PHYXGXS5_SERDES_DIGITAL_1000X_STAT2r(_unit, _phy_ctrl, \ 844 _val, _mask) \ 845 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x15, \ 846 (_val), (_mask)) 847 848 /* 1000XStatus3 (Addr 0x8306) */ 849 #define READ_PHYXGXS5_SERDES_DIGITAL_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 850 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x16, (_val)) 851 #define WRITE_PHYXGXS5_SERDES_DIGITAL_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 852 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x16, (_val)) 853 #define MODIFY_PHYXGXS5_SERDES_DIGITAL_1000X_STAT3r(_unit, _phy_ctrl, \ 854 _val, _mask) \ 855 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x16, \ 856 (_val), (_mask)) 857 858 /* CrcErr_RxPktCntr (Addr 0x8307) */ 859 860 /* Misc1 (Addr 0x8308) */ 861 #define READ_PHYXGXS5_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val) \ 862 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x18, (_val)) 863 #define WRITE_PHYXGXS5_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val) \ 864 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x18, (_val)) 865 #define MODIFY_PHYXGXS5_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val, _mask) \ 866 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x18, \ 867 (_val), (_mask)) 868 869 /* Misc2 (Addr 0x8309) */ 870 #define READ_PHYXGXS5_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val) \ 871 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x19, (_val)) 872 #define WRITE_PHYXGXS5_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val) \ 873 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x19, (_val)) 874 #define MODIFY_PHYXGXS5_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val, _mask) \ 875 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x19, \ 876 (_val), (_mask)) 877 878 /* PatGenControl (Addr 0x830A) */ 879 /* PatGenControl (Addr 0x830B) */ 880 /* TestMode (Addr 0x830C) */ 881 /* TxPktCnt (Addr 0x830D) */ 882 /* RxPktCnt (Addr 0x830E) */ 883 884 /*********************/ 885 /* Test (blk 0x8310) */ 886 /*********************/ 887 888 /************************/ 889 /* Over 1G (blk 0x8320) */ 890 /************************/ 891 /* digctrl_3_0 (Addr 0x8320) */ 892 /* digctrl_3_1 (Addr 0x8321) */ 893 /* digctrl_3_2 (Addr 0x8322) */ 894 /* digctrl_3_3 (Addr 0x8323) */ 895 /* digctrl_3_4 (Addr 0x8324) */ 896 /* digctrl_3_5 (Addr 0x8325) */ 897 /* digctrl_3_6 (Addr 0x8326) */ 898 /* TPOUT 1 (Addr 0x8327) */ 899 /* TPOUT 2 (Addr 0x8328) */ 900 901 /* UP 1 (Addr 0x8329) */ 902 #define READ_PHYXGXS5_OVER1G_UP1r(_unit, _phy_ctrl, _val) \ 903 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8320, 0x19, (_val)) 904 #define WRITE_PHYXGXS5_OVER1G_UP1r(_unit, _phy_ctrl, _val) \ 905 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8320, 0x19, (_val)) 906 #define MODIFY_PHYXGXS5_OVER1G_UP1r(_unit, _phy_ctrl, _val, _mask) \ 907 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8320, 0x19, \ 908 (_val), (_mask)) 909 910 /* UP 2 (Addr 0x832A) */ 911 /* UP 3 (Addr 0x832B) */ 912 913 /* LP UP 1 (Addr 0x832C) */ 914 #define READ_PHYXGXS5_OVER1G_LP_UP1r(_unit, _phy_ctrl, _val) \ 915 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8320, 0x1C, (_val)) 916 #define WRITE_PHYXGXS5_OVER1G_LP_UP1r(_unit, _phy_ctrl, _val) \ 917 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8320, 0x1C, (_val)) 918 #define MODIFY_PHYXGXS5_OVER1G_LP_UP1r(_unit, _phy_ctrl, _val, _mask) \ 919 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8320, 0x1C, \ 920 (_val), (_mask)) 921 922 /* LP UP 2 (Addr 0x832D) */ 923 /* LP UP 3 (Addr 0x832E) */ 924 925 /***************************/ 926 /* Remote PHY (blk 0x8330) */ 927 /***************************/ 928 929 /************************************/ 930 /* 10G Parallel Detect (blk 0x8340) */ 931 /************************************/ 932 /* parDet10GStatus (Addr 0x8340) */ 933 #define READ_PHYXGXS5_PARDET10G_STATr(_unit, _phy_ctrl, _val) \ 934 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x10, (_val)) 935 #define WRITE_PHYXGXS5_PARDET10G_STATr(_unit, _phy_ctrl, _val) \ 936 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x10, (_val)) 937 #define MODIFY_PHYXGXS5_PARDET10G_STATr(_unit, _phy_ctrl, _val, _mask) \ 938 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x10, \ 939 (_val), (_mask)) 940 941 /* parDet10GControl (Addr 0x8341) */ 942 #define READ_PHYXGXS5_PARDET10G_CTRLr(_unit, _phy_ctrl, _val) \ 943 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x11, (_val)) 944 #define WRITE_PHYXGXS5_PARDET10G_CTRLr(_unit, _phy_ctrl, _val) \ 945 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x11, (_val)) 946 #define MODIFY_PHYXGXS5_PARDET10G_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 947 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x11, \ 948 (_val), (_mask)) 949 950 /* parDet10GSigDet (Addr 0x8342) */ 951 #define READ_PHYXGXS5_PARDET10G_SIGDETr(_unit, _phy_ctrl, _val) \ 952 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x12, (_val)) 953 #define WRITE_PHYXGXS5_PARDET10G_SIGDETr(_unit, _phy_ctrl, _val) \ 954 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x12, (_val)) 955 #define MODIFY_PHYXGXS5_PARDET10G_SIGDETr(_unit, _phy_ctrl, _val, _mask) \ 956 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x12, \ 957 (_val), (_mask)) 958 959 /* parDet10GLink (Addr 0x8343) */ 960 #define READ_PHYXGXS5_PARDET10G_LINKr(_unit, _phy_ctrl, _val) \ 961 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x13, (_val)) 962 #define WRITE_PHYXGXS5_PARDET10G_LINKr(_unit, _phy_ctrl, _val) \ 963 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x13, (_val)) 964 #define MODIFY_PHYXGXS5_PARDET10G_LINKr(_unit, _phy_ctrl, _val, _mask) \ 965 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x13, \ 966 (_val), (_mask)) 967 968 /* parDet10GLosLink (Addr 0x8344) */ 969 #define READ_PHYXGXS5_PARDET10G_LOSLINKr(_unit, _phy_ctrl, _val) \ 970 PHYXGXS5_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x14, (_val)) 971 #define WRITE_PHYXGXS5_PARDET10G_LOSLINKr(_unit, _phy_ctrl, _val) \ 972 PHYXGXS5_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x14, (_val)) 973 #define MODIFY_PHYXGXS5_PARDET10G_LOSLINKr(_unit, _phy_ctrl, _val, _mask) \ 974 PHYXGXS5_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x14, \ 975 (_val), (_mask)) 976 977 /* Reserved (Addr 0x8345 - 0x834E) */ 978 979 /******************************/ 980 /* BAM Next Page (blk 0x8350) */ 981 /******************************/ 982 983 #endif /* _PHY_XGXS5_H_ */