xgxs16g.h (1132325B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: xgxs16g.h 8 * Purpose: 16G 802.3ae Ethernet PHY 9 */ 10 11 #ifndef _PHY_XGXS16G_H_ 12 #define _PHY_XGXS16G_H_ 13 14 /* typedefs */ 15 #define XGXS16G_LANE_NAME_LEN 30 16 typedef struct { 17 uint16 serdes_id0; 18 uint16 serdes_id2; 19 char name[XGXS16G_LANE_NAME_LEN]; 20 } XGXS16G_DEV_DESC; 21 22 /* macros */ 23 24 /* Macros ONLY used after initialization */ 25 #define XGXS16G_16G_ID(_pc) \ 26 ((((XGXS16G_DEV_DESC *)((_pc) + 1))->serdes_id2) & SERDESID_SERDESID2_DR_16G_4L_MASK) 27 #define XGXS16G_13G_ID(_pc) \ 28 ((((((XGXS16G_DEV_DESC *)((_pc) + 1))->serdes_id2) >> 8) & 0xf) == 0x3) 29 #define XGXS16G_2p5G_ID(_pc) \ 30 (((((XGXS16G_DEV_DESC *)((_pc) + 1))->serdes_id2) & 0xff) == 0xf) 31 32 #define XGXS16G_13G_REV_B0(_pc) (XGXS16G_13G_ID(_pc) && \ 33 (((((XGXS16G_DEV_DESC *)((_pc) + 1))->serdes_id0 & SERDESID_SERDESID0_REV_LETTER_MASK) >> SERDESID_SERDESID0_REV_LETTER_SHIFT) == 0x1) && \ 34 (((((XGXS16G_DEV_DESC *)((_pc) + 1))->serdes_id0 & SERDESID_SERDESID0_REV_NUMBER_MASK) >> SERDESID_SERDESID0_REV_NUMBER_SHIFT) == 0x0)) 35 36 #define FEATURE_SPEED_100FX(_pc) (XGXS16G_13G_ID(_pc) || XGXS16G_2p5G_ID(pc)) 37 38 /* 100FX speed is not suported for asymmetric fixed speed mode in B0 */ 39 #define IF_XGXS16G_13G_B0_IS_SYMMETRIC_MODE(pc, asymm) (XGXS16G_13G_REV_B0(pc)? (!asymm): 1) 40 41 #define FEATURE_NEW_LANESWAP(_pc) (XGXS16G_13G_ID(_pc)) 42 43 #define SERDES_ID0_TECH_PROC_40NM (1 << 7) 44 45 #define XGXS16G_40NM(_pc) \ 46 (((((XGXS16G_DEV_DESC *)((_pc) + 1))->serdes_id0) & SERDESID_SERDESID0_TECH_PROC_MASK) == SERDES_ID0_TECH_PROC_40NM) 47 48 49 /****************************************************************************/ 50 /***** Starting below is auto-generated register macros from RDB files *****/ 51 /****************************************************************************/ 52 53 /** 54 * m = memory, c = core, r = register, f = field, d = data. 55 */ 56 #if !defined(GET_FIELD) && !defined(SET_FIELD) 57 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 58 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 59 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 60 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 61 62 #define GET_FIELD(m,c,r,f) \ 63 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 64 65 #define SET_FIELD(m,c,r,f,d) \ 66 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 67 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 68 ) 69 70 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 71 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 72 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 73 74 #endif /* GET & SET */ 75 76 /**************************************************************************** 77 * Core Enums. 78 */ 79 /**************************************************************************** 80 * Enums: combo_operationModes 81 */ 82 #define combo_operationModes_XGXS 0 83 #define combo_operationModes_XGXG_nCC 1 84 #define combo_operationModes_Indlanes 6 85 #define combo_operationModes_PCI 7 86 #define combo_operationModes_XGXS_nLQ 8 87 #define combo_operationModes_XGXS_nLQnCC 9 88 #define combo_operationModes_PBypass 10 89 #define combo_operationModes_PBypass_nDSK 11 90 #define combo_operationModes_ComboCoreMode 12 91 #define combo_operationModes_Clocks_off 15 92 93 /**************************************************************************** 94 * Enums: combo_actualSpeeds4 95 */ 96 #define combo_actualSpeeds4_dr_10M 0 97 #define combo_actualSpeeds4_dr_100M 1 98 #define combo_actualSpeeds4_dr_1G 2 99 #define combo_actualSpeeds4_dr_2p5G 3 100 #define combo_actualSpeeds4_dr_5G 4 101 #define combo_actualSpeeds4_dr_6G 5 102 #define combo_actualSpeeds4_dr_10G_HiG 6 103 #define combo_actualSpeeds4_dr_10G_CX4 7 104 #define combo_actualSpeeds4_dr_12G_HiG 8 105 #define combo_actualSpeeds4_dr_12p5G 9 106 #define combo_actualSpeeds4_dr_13G 10 107 #define combo_actualSpeeds4_dr_15G 11 108 #define combo_actualSpeeds4_dr_16G 12 109 110 /**************************************************************************** 111 * Enums: combo_actualSpeeds5 112 */ 113 #define combo_actualSpeeds5_dr_10M 0 114 #define combo_actualSpeeds5_dr_100M 1 115 #define combo_actualSpeeds5_dr_1G 2 116 #define combo_actualSpeeds5_dr_2p5G 3 117 #define combo_actualSpeeds5_dr_5GX4 4 118 #define combo_actualSpeeds5_dr_6GX4 5 119 #define combo_actualSpeeds5_dr_10G_HiG 6 120 #define combo_actualSpeeds5_dr_10G_CX4 7 121 #define combo_actualSpeeds5_dr_12G_HiG 8 122 #define combo_actualSpeeds5_dr_12p5GX4 9 123 #define combo_actualSpeeds5_dr_13GX4 10 124 #define combo_actualSpeeds5_dr_15GX4 11 125 #define combo_actualSpeeds5_dr_16GX4 12 126 #define combo_actualSpeeds5_dr_5G 16 127 #define combo_actualSpeeds5_dr_6p4G 17 128 #define combo_actualSpeeds5_dr_20GX4 18 129 #define combo_actualSpeeds5_dr_25GX4 19 130 131 /**************************************************************************** 132 * Enums: xgxs_operationModes 133 */ 134 #define xgxs_operationModes_XGXS 0 135 #define xgxs_operationModes_XGXG_nCC 1 136 #define xgxs_operationModes_Indlanes 6 137 #define xgxs_operationModes_PCI 7 138 #define xgxs_operationModes_XGXS_nLQ 8 139 #define xgxs_operationModes_XGXS_nLQnCC 9 140 #define xgxs_operationModes_PBypass 10 141 #define xgxs_operationModes_PBypass_nDSK 11 142 #define xgxs_operationModes_ComboCoreMode 12 143 #define xgxs_operationModes_Clocks_off 15 144 145 /**************************************************************************** 146 * Enums: xgxs_actualSpeeds4 147 */ 148 #define xgxs_actualSpeeds4_dr_10M 0 149 #define xgxs_actualSpeeds4_dr_100M 1 150 #define xgxs_actualSpeeds4_dr_1G 2 151 #define xgxs_actualSpeeds4_dr_2p5G 3 152 #define xgxs_actualSpeeds4_dr_5G 4 153 #define xgxs_actualSpeeds4_dr_6G 5 154 #define xgxs_actualSpeeds4_dr_10G_HiG 6 155 #define xgxs_actualSpeeds4_dr_10G_CX4 7 156 #define xgxs_actualSpeeds4_dr_12G_HiG 8 157 #define xgxs_actualSpeeds4_dr_12p5G 9 158 #define xgxs_actualSpeeds4_dr_13G 10 159 #define xgxs_actualSpeeds4_dr_15G 11 160 #define xgxs_actualSpeeds4_dr_16G 12 161 162 /**************************************************************************** 163 * Enums: xgxs_actualSpeeds5 164 */ 165 #define xgxs_actualSpeeds5_dr_10M 0 166 #define xgxs_actualSpeeds5_dr_100M 1 167 #define xgxs_actualSpeeds5_dr_1G 2 168 #define xgxs_actualSpeeds5_dr_2p5G 3 169 #define xgxs_actualSpeeds5_dr_5GX4 4 170 #define xgxs_actualSpeeds5_dr_6GX4 5 171 #define xgxs_actualSpeeds5_dr_10G_HiG 6 172 #define xgxs_actualSpeeds5_dr_10G_CX4 7 173 #define xgxs_actualSpeeds5_dr_12G_HiG 8 174 #define xgxs_actualSpeeds5_dr_12p5GX4 9 175 #define xgxs_actualSpeeds5_dr_13GX4 10 176 #define xgxs_actualSpeeds5_dr_15GX4 11 177 #define xgxs_actualSpeeds5_dr_16GX4 12 178 #define xgxs_actualSpeeds5_dr_5G 16 179 #define xgxs_actualSpeeds5_dr_6p4G 17 180 #define xgxs_actualSpeeds5_dr_20GX4 18 181 #define xgxs_actualSpeeds5_dr_25GX4 19 182 183 /* defines for Clause73 device */ 184 #define CL73_AN_ADVERT0_REG 0x10 185 #define CL73_AN_ADVERT1_REG 0x11 186 #define CL73_AN_LP_ABILITY0_REG 0x13 187 #define CL73_AN_LP_ABILITY1_REG 0x14 188 189 #define CL73_AN_ADV_TECH_10G_KX4 (1 << 6) 190 #define CL73_AN_ADV_TECH_1G_KX (1 << 5) 191 #define CL73_AN_ADV_TECH_SPEEDS_MASK (0x7 << 5) 192 #define CL73_AN_ADV_PAUSE (1 << 10) 193 #define CL73_AN_ADV_ASYM_PAUSE (1 << 11) 194 195 196 #define AER_MMD_CL73_AN (0x3800 << 16) 197 #define READ_XGXS16G_AN_CL73_REG(_unit, _pc, _reg,_val) \ 198 XGXS16G_REG_READ((_unit), (_pc), 0x00, AER_MMD_CL73_AN | (_reg), (_val)) 199 #define WRITE_XGXS16G_AN_CL73_REG(_unit, _pc,_reg, _val) \ 200 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, AER_MMD_CL73_AN | (_reg), (_val)) 201 #define MODIFY_XGXS16G_AN_CL73_REG(_unit, _pc, _reg, _val, _mask) \ 202 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, AER_MMD_CL73_AN | (_reg), \ 203 (_val), (_mask)) 204 205 /**************************************************************************** 206 * HXGS16G_IEEE_ieee0Blk 207 */ 208 209 /* IEEE MII control register */ 210 #define READ_XGXS16G_IEEE0BLK_IEEECONTROL0r(_unit, _pc, _val) \ 211 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00000000, (_val)) 212 #define WRITE_XGXS16G_IEEE0BLK_IEEECONTROL0r(_unit, _pc, _val) \ 213 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00000000, (_val)) 214 #define MODIFY_XGXS16G_IEEE0BLK_IEEECONTROL0r(_unit, _pc, _val, _mask) \ 215 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00000000, (_val), (_mask)) 216 217 /* IEEE MII status register */ 218 #define READ_XGXS16G_IEEE0BLK_IEEESTATUS0r(_unit, _pc, _val) \ 219 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00000001, (_val)) 220 #define WRITE_XGXS16G_IEEE0BLK_IEEESTATUS0r(_unit, _pc, _val) \ 221 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00000001, (_val)) 222 #define MODIFY_XGXS16G_IEEE0BLK_IEEESTATUS0r(_unit, _pc, _val, _mask) \ 223 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00000001, (_val), (_mask)) 224 225 /* IEEE MII TX disable register */ 226 #define READ_XGXS16G_IEEE0BLK_IEEETXDISABLEr(_unit, _pc, _val) \ 227 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00000009, (_val)) 228 #define WRITE_XGXS16G_IEEE0BLK_IEEETXDISABLEr(_unit, _pc, _val) \ 229 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00000009, (_val)) 230 #define MODIFY_XGXS16G_IEEE0BLK_IEEETXDISABLEr(_unit, _pc, _val, _mask) \ 231 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00000009, (_val), (_mask)) 232 233 234 /**************************************************************************** 235 * XGXS16G_IEEE_ieee1Blk 236 */ 237 238 /* IEEE MII control register */ 239 #define READ_XGXS16G_IEEE1BLK_IEEECONTROL1r(_unit, _pc, _val) \ 240 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00000010, (_val)) 241 #define WRITE_XGXS16G_IEEE1BLK_IEEECONTROL1r(_unit, _pc, _val) \ 242 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00000010, (_val)) 243 #define MODIFY_XGXS16G_IEEE1BLK_IEEECONTROL1r(_unit, _pc, _val, _mask) \ 244 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00000010, (_val), (_mask)) 245 246 247 /**************************************************************************** 248 * XGXS16G_USER_XgxsBlk0 249 */ 250 251 /* XGXG control register */ 252 #define READ_XGXS16G_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 253 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008000, (_val)) 254 #define WRITE_XGXS16G_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 255 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008000, (_val)) 256 #define MODIFY_XGXS16G_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val, _mask) \ 257 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008000, (_val), (_mask)) 258 259 /* XGXG status register */ 260 #define READ_XGXS16G_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \ 261 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008001, (_val)) 262 #define WRITE_XGXS16G_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \ 263 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008001, (_val)) 264 #define MODIFY_XGXS16G_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val, _mask) \ 265 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008001, (_val), (_mask)) 266 267 /* XGMII idle control character register */ 268 #define READ_XGXS16G_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val) \ 269 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008002, (_val)) 270 #define WRITE_XGXS16G_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val) \ 271 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008002, (_val)) 272 #define MODIFY_XGXS16G_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val, _mask) \ 273 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008002, (_val), (_mask)) 274 275 /* XGMII sync control character register */ 276 #define READ_XGXS16G_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val) \ 277 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008003, (_val)) 278 #define WRITE_XGXS16G_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val) \ 279 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008003, (_val)) 280 #define MODIFY_XGXS16G_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val, _mask) \ 281 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008003, (_val), (_mask)) 282 283 /* XGMII skip control character register */ 284 #define READ_XGXS16G_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val) \ 285 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008004, (_val)) 286 #define WRITE_XGXS16G_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val) \ 287 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008004, (_val)) 288 #define MODIFY_XGXS16G_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val, _mask) \ 289 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008004, (_val), (_mask)) 290 291 /* XGMII sop & eop control character register */ 292 #define READ_XGXS16G_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val) \ 293 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008005, (_val)) 294 #define WRITE_XGXS16G_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val) \ 295 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008005, (_val)) 296 #define MODIFY_XGXS16G_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val, _mask) \ 297 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008005, (_val), (_mask)) 298 299 /* XGMII alignment & eror control character register */ 300 #define READ_XGXS16G_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val) \ 301 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008006, (_val)) 302 #define WRITE_XGXS16G_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val) \ 303 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008006, (_val)) 304 #define MODIFY_XGXS16G_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val, _mask) \ 305 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008006, (_val), (_mask)) 306 307 /* XGMII receive control register */ 308 #define READ_XGXS16G_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val) \ 309 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008007, (_val)) 310 #define WRITE_XGXS16G_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val) \ 311 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008007, (_val)) 312 #define MODIFY_XGXS16G_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val, _mask) \ 313 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008007, (_val), (_mask)) 314 315 /* XGMII transmit control register */ 316 #define READ_XGXS16G_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val) \ 317 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008008, (_val)) 318 #define WRITE_XGXS16G_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val) \ 319 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008008, (_val)) 320 #define MODIFY_XGXS16G_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val, _mask) \ 321 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008008, (_val), (_mask)) 322 323 /* XGMII ||A|| minimum swap spacing */ 324 #define READ_XGXS16G_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val) \ 325 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008009, (_val)) 326 #define WRITE_XGXS16G_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val) \ 327 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008009, (_val)) 328 #define MODIFY_XGXS16G_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val, _mask) \ 329 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008009, (_val), (_mask)) 330 331 /* LSS information byte resgister */ 332 #define READ_XGXS16G_XGXSBLK0_LSSLSIDr(_unit, _pc, _val) \ 333 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800a, (_val)) 334 #define WRITE_XGXS16G_XGXSBLK0_LSSLSIDr(_unit, _pc, _val) \ 335 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800a, (_val)) 336 #define MODIFY_XGXS16G_XGXSBLK0_LSSLSIDr(_unit, _pc, _val, _mask) \ 337 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800a, (_val), (_mask)) 338 339 /* LSS transmit information byte resgister */ 340 #define READ_XGXS16G_XGXSBLK0_LSSTINFOr(_unit, _pc, _val) \ 341 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800b, (_val)) 342 #define WRITE_XGXS16G_XGXSBLK0_LSSTINFOr(_unit, _pc, _val) \ 343 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800b, (_val)) 344 #define MODIFY_XGXS16G_XGXSBLK0_LSSTINFOr(_unit, _pc, _val, _mask) \ 345 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800b, (_val), (_mask)) 346 347 /* LSS receive information byte resgister */ 348 #define READ_XGXS16G_XGXSBLK0_LSSRINFOr(_unit, _pc, _val) \ 349 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800c, (_val)) 350 #define WRITE_XGXS16G_XGXSBLK0_LSSRINFOr(_unit, _pc, _val) \ 351 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800c, (_val)) 352 #define MODIFY_XGXS16G_XGXSBLK0_LSSRINFOr(_unit, _pc, _val, _mask) \ 353 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800c, (_val), (_mask)) 354 355 /* MMD select register */ 356 #define READ_XGXS16G_XGXSBLK0_MMDSELECTr(_unit, _pc, _val) \ 357 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800d, (_val)) 358 #define WRITE_XGXS16G_XGXSBLK0_MMDSELECTr(_unit, _pc, _val) \ 359 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800d, (_val)) 360 #define MODIFY_XGXS16G_XGXSBLK0_MMDSELECTr(_unit, _pc, _val, _mask) \ 361 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800d, (_val), (_mask)) 362 363 /* Miscellaneous control 1 register */ 364 #define READ_XGXS16G_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \ 365 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800e, (_val)) 366 #define WRITE_XGXS16G_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \ 367 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800e, (_val)) 368 #define MODIFY_XGXS16G_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val, _mask) \ 369 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800e, (_val), (_mask)) 370 371 /* Block Address register */ 372 #define READ_XGXS16G_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val) \ 373 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000800f, (_val)) 374 #define WRITE_XGXS16G_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val) \ 375 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000800f, (_val)) 376 #define MODIFY_XGXS16G_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val, _mask) \ 377 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800f, (_val), (_mask)) 378 379 380 /**************************************************************************** 381 * XGXS16G_USER_XgxsBlk1 382 */ 383 384 /* Lane deskew register */ 385 #define READ_XGXS16G_XGXSBLK1_DESKEWr(_unit, _pc, _val) \ 386 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008010, (_val)) 387 #define WRITE_XGXS16G_XGXSBLK1_DESKEWr(_unit, _pc, _val) \ 388 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008010, (_val)) 389 #define MODIFY_XGXS16G_XGXSBLK1_DESKEWr(_unit, _pc, _val, _mask) \ 390 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008010, (_val), (_mask)) 391 392 /* Link ||A|| column timeout value register */ 393 #define READ_XGXS16G_XGXSBLK1_LINKr(_unit, _pc, _val) \ 394 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008011, (_val)) 395 #define WRITE_XGXS16G_XGXSBLK1_LINKr(_unit, _pc, _val) \ 396 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008011, (_val)) 397 #define MODIFY_XGXS16G_XGXSBLK1_LINKr(_unit, _pc, _val, _mask) \ 398 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008011, (_val), (_mask)) 399 400 /* Receive test control register */ 401 #define READ_XGXS16G_XGXSBLK1_TESTRXr(_unit, _pc, _val) \ 402 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008012, (_val)) 403 #define WRITE_XGXS16G_XGXSBLK1_TESTRXr(_unit, _pc, _val) \ 404 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008012, (_val)) 405 #define MODIFY_XGXS16G_XGXSBLK1_TESTRXr(_unit, _pc, _val, _mask) \ 406 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008012, (_val), (_mask)) 407 408 /* Transmit test control register */ 409 #define READ_XGXS16G_XGXSBLK1_TESTTXr(_unit, _pc, _val) \ 410 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008013, (_val)) 411 #define WRITE_XGXS16G_XGXSBLK1_TESTTXr(_unit, _pc, _val) \ 412 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008013, (_val)) 413 #define MODIFY_XGXS16G_XGXSBLK1_TESTTXr(_unit, _pc, _val, _mask) \ 414 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008013, (_val), (_mask)) 415 416 /* XGXS test control register */ 417 #define READ_XGXS16G_XGXSBLK1_TESTXGr(_unit, _pc, _val) \ 418 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008014, (_val)) 419 #define WRITE_XGXS16G_XGXSBLK1_TESTXGr(_unit, _pc, _val) \ 420 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008014, (_val)) 421 #define MODIFY_XGXS16G_XGXSBLK1_TESTXGr(_unit, _pc, _val, _mask) \ 422 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008014, (_val), (_mask)) 423 424 /* Lane control 0 register */ 425 #define READ_XGXS16G_XGXSBLK1_LANECTRL0r(_unit, _pc, _val) \ 426 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008015, (_val)) 427 #define WRITE_XGXS16G_XGXSBLK1_LANECTRL0r(_unit, _pc, _val) \ 428 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008015, (_val)) 429 #define MODIFY_XGXS16G_XGXSBLK1_LANECTRL0r(_unit, _pc, _val, _mask) \ 430 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008015, (_val), (_mask)) 431 432 /* Lane control 1 register */ 433 #define READ_XGXS16G_XGXSBLK1_LANECTRL1r(_unit, _pc, _val) \ 434 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008016, (_val)) 435 #define WRITE_XGXS16G_XGXSBLK1_LANECTRL1r(_unit, _pc, _val) \ 436 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008016, (_val)) 437 #define MODIFY_XGXS16G_XGXSBLK1_LANECTRL1r(_unit, _pc, _val, _mask) \ 438 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008016, (_val), (_mask)) 439 440 /* Lane control 2 register */ 441 #define READ_XGXS16G_XGXSBLK1_LANECTRL2r(_unit, _pc, _val) \ 442 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008017, (_val)) 443 #define WRITE_XGXS16G_XGXSBLK1_LANECTRL2r(_unit, _pc, _val) \ 444 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008017, (_val)) 445 #define MODIFY_XGXS16G_XGXSBLK1_LANECTRL2r(_unit, _pc, _val, _mask) \ 446 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008017, (_val), (_mask)) 447 448 /* Lane control 3 register */ 449 #define READ_XGXS16G_XGXSBLK1_LANECTRL3r(_unit, _pc, _val) \ 450 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008018, (_val)) 451 #define WRITE_XGXS16G_XGXSBLK1_LANECTRL3r(_unit, _pc, _val) \ 452 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008018, (_val)) 453 #define MODIFY_XGXS16G_XGXSBLK1_LANECTRL3r(_unit, _pc, _val, _mask) \ 454 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008018, (_val), (_mask)) 455 456 /* Lane PRBS control register */ 457 #define READ_XGXS16G_XGXSBLK1_LANEPRBSr(_unit, _pc, _val) \ 458 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008019, (_val)) 459 #define WRITE_XGXS16G_XGXSBLK1_LANEPRBSr(_unit, _pc, _val) \ 460 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008019, (_val)) 461 #define MODIFY_XGXS16G_XGXSBLK1_LANEPRBSr(_unit, _pc, _val, _mask) \ 462 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008019, (_val), (_mask)) 463 464 /* Lane test control register */ 465 #define READ_XGXS16G_XGXSBLK1_LANETESTr(_unit, _pc, _val) \ 466 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000801a, (_val)) 467 #define WRITE_XGXS16G_XGXSBLK1_LANETESTr(_unit, _pc, _val) \ 468 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000801a, (_val)) 469 #define MODIFY_XGXS16G_XGXSBLK1_LANETESTr(_unit, _pc, _val, _mask) \ 470 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801a, (_val), (_mask)) 471 472 /* LSS, ||Q|| column count register */ 473 #define READ_XGXS16G_XGXSBLK1_LSSREVNTr(_unit, _pc, _val) \ 474 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000801b, (_val)) 475 #define WRITE_XGXS16G_XGXSBLK1_LSSREVNTr(_unit, _pc, _val) \ 476 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000801b, (_val)) 477 #define MODIFY_XGXS16G_XGXSBLK1_LSSREVNTr(_unit, _pc, _val, _mask) \ 478 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801b, (_val), (_mask)) 479 480 /* Lane deskew event count register */ 481 #define READ_XGXS16G_XGXSBLK1_DSKEVNTr(_unit, _pc, _val) \ 482 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000801c, (_val)) 483 #define WRITE_XGXS16G_XGXSBLK1_DSKEVNTr(_unit, _pc, _val) \ 484 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000801c, (_val)) 485 #define MODIFY_XGXS16G_XGXSBLK1_DSKEVNTr(_unit, _pc, _val, _mask) \ 486 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801c, (_val), (_mask)) 487 488 /* Bad ||A|| column count register */ 489 #define READ_XGXS16G_XGXSBLK1_AERREVNTr(_unit, _pc, _val) \ 490 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000801d, (_val)) 491 #define WRITE_XGXS16G_XGXSBLK1_AERREVNTr(_unit, _pc, _val) \ 492 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000801d, (_val)) 493 #define MODIFY_XGXS16G_XGXSBLK1_AERREVNTr(_unit, _pc, _val, _mask) \ 494 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801d, (_val), (_mask)) 495 496 /* Clock compensation event count register */ 497 #define READ_XGXS16G_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val) \ 498 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000801e, (_val)) 499 #define WRITE_XGXS16G_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val) \ 500 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000801e, (_val)) 501 #define MODIFY_XGXS16G_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val, _mask) \ 502 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801e, (_val), (_mask)) 503 504 /**************************************************************************** 505 * XGXS16G_10G_TX_BERT 506 */ 507 508 /**************************************************************************** 509 * XGXS16G_10G_RX_BERT 510 */ 511 512 /**************************************************************************** 513 * XGXS16G_USER_PLL 514 */ 515 516 /* PLL status register */ 517 #define READ_XGXS16G_PLL_PLLSTATUSr(_unit, _pc, _val) \ 518 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008050, (_val)) 519 #define WRITE_XGXS16G_PLL_PLLSTATUSr(_unit, _pc, _val) \ 520 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008050, (_val)) 521 #define MODIFY_XGXS16G_PLL_PLLSTATUSr(_unit, _pc, _val, _mask) \ 522 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008050, (_val), (_mask)) 523 524 /* PLL control register */ 525 #define READ_XGXS16G_PLL_PLLCONTROLr(_unit, _pc, _val) \ 526 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008051, (_val)) 527 #define WRITE_XGXS16G_PLL_PLLCONTROLr(_unit, _pc, _val) \ 528 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008051, (_val)) 529 #define MODIFY_XGXS16G_PLL_PLLCONTROLr(_unit, _pc, _val, _mask) \ 530 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008051, (_val), (_mask)) 531 532 /* PLL start up state machine vco timers */ 533 #define READ_XGXS16G_PLL_PLLTIMER1r(_unit, _pc, _val) \ 534 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008052, (_val)) 535 #define WRITE_XGXS16G_PLL_PLLTIMER1r(_unit, _pc, _val) \ 536 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008052, (_val)) 537 #define MODIFY_XGXS16G_PLL_PLLTIMER1r(_unit, _pc, _val, _mask) \ 538 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008052, (_val), (_mask)) 539 540 /* PLL start up state machine retry timer */ 541 #define READ_XGXS16G_PLL_PLLTIMER2r(_unit, _pc, _val) \ 542 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008053, (_val)) 543 #define WRITE_XGXS16G_PLL_PLLTIMER2r(_unit, _pc, _val) \ 544 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008053, (_val)) 545 #define MODIFY_XGXS16G_PLL_PLLTIMER2r(_unit, _pc, _val, _mask) \ 546 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008053, (_val), (_mask)) 547 548 /* PLL start up state machine freq. detect timer */ 549 #define READ_XGXS16G_PLL_PLLTIMER3r(_unit, _pc, _val) \ 550 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008054, (_val)) 551 #define WRITE_XGXS16G_PLL_PLLTIMER3r(_unit, _pc, _val) \ 552 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008054, (_val)) 553 #define MODIFY_XGXS16G_PLL_PLLTIMER3r(_unit, _pc, _val, _mask) \ 554 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008054, (_val), (_mask)) 555 556 /* PLL vco range control state machine */ 557 #define READ_XGXS16G_PLL_CAPCONTROLr(_unit, _pc, _val) \ 558 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008055, (_val)) 559 #define WRITE_XGXS16G_PLL_CAPCONTROLr(_unit, _pc, _val) \ 560 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008055, (_val)) 561 #define MODIFY_XGXS16G_PLL_CAPCONTROLr(_unit, _pc, _val, _mask) \ 562 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008055, (_val), (_mask)) 563 564 /* Currently unused */ 565 #define READ_XGXS16G_PLL_AMPCONTROLr(_unit, _pc, _val) \ 566 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008056, (_val)) 567 #define WRITE_XGXS16G_PLL_AMPCONTROLr(_unit, _pc, _val) \ 568 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008056, (_val)) 569 #define MODIFY_XGXS16G_PLL_AMPCONTROLr(_unit, _pc, _val, _mask) \ 570 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008056, (_val), (_mask)) 571 572 /* Frequency detector control */ 573 #define READ_XGXS16G_PLL_FREQDETCOUNTERr(_unit, _pc, _val) \ 574 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008057, (_val)) 575 #define WRITE_XGXS16G_PLL_FREQDETCOUNTERr(_unit, _pc, _val) \ 576 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008057, (_val)) 577 #define MODIFY_XGXS16G_PLL_FREQDETCOUNTERr(_unit, _pc, _val, _mask) \ 578 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008057, (_val), (_mask)) 579 580 /* PLL analog status */ 581 #define READ_XGXS16G_PLL_PLLASTATUS1r(_unit, _pc, _val) \ 582 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008058, (_val)) 583 #define WRITE_XGXS16G_PLL_PLLASTATUS1r(_unit, _pc, _val) \ 584 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008058, (_val)) 585 #define MODIFY_XGXS16G_PLL_PLLASTATUS1r(_unit, _pc, _val, _mask) \ 586 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008058, (_val), (_mask)) 587 588 /* PLL analog controls */ 589 #define READ_XGXS16G_PLL_PLLCLOCKGENr(_unit, _pc, _val) \ 590 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000805a, (_val)) 591 #define WRITE_XGXS16G_PLL_PLLCLOCKGENr(_unit, _pc, _val) \ 592 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000805a, (_val)) 593 #define MODIFY_XGXS16G_PLL_PLLCLOCKGENr(_unit, _pc, _val, _mask) \ 594 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805a, (_val), (_mask)) 595 596 /* PLL analog controls */ 597 #define READ_XGXS16G_PLL_PLLNDIVr(_unit, _pc, _val) \ 598 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000805b, (_val)) 599 #define WRITE_XGXS16G_PLL_PLLNDIVr(_unit, _pc, _val) \ 600 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000805b, (_val)) 601 #define MODIFY_XGXS16G_PLL_PLLNDIVr(_unit, _pc, _val, _mask) \ 602 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805b, (_val), (_mask)) 603 604 /* PLL analog controls */ 605 #define READ_XGXS16G_PLL_PLLBGLQPr(_unit, _pc, _val) \ 606 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000805c, (_val)) 607 #define WRITE_XGXS16G_PLL_PLLBGLQPr(_unit, _pc, _val) \ 608 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000805c, (_val)) 609 #define MODIFY_XGXS16G_PLL_PLLBGLQPr(_unit, _pc, _val, _mask) \ 610 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805c, (_val), (_mask)) 611 612 /* PLL analog controls */ 613 #define READ_XGXS16G_PLL_PLLTESTKVHr(_unit, _pc, _val) \ 614 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000805d, (_val)) 615 #define WRITE_XGXS16G_PLL_PLLTESTKVHr(_unit, _pc, _val) \ 616 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000805d, (_val)) 617 #define MODIFY_XGXS16G_PLL_PLLTESTKVHr(_unit, _pc, _val, _mask) \ 618 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805d, (_val), (_mask)) 619 620 /* PLL analog controls */ 621 #define READ_XGXS16G_PLL_PLLACONTROL5r(_unit, _pc, _val) \ 622 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000805e, (_val)) 623 #define WRITE_XGXS16G_PLL_PLLACONTROL5r(_unit, _pc, _val) \ 624 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000805e, (_val)) 625 #define MODIFY_XGXS16G_PLL_PLLACONTROL5r(_unit, _pc, _val, _mask) \ 626 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805e, (_val), (_mask)) 627 628 629 /**************************************************************************** 630 * XGXS16G_USER_TX0 631 */ 632 633 /* Tx analog status 0 register */ 634 #define READ_XGXS16G_TX0_TX_ASTATUS0r(_unit, _pc, _val) \ 635 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008060, (_val)) 636 #define WRITE_XGXS16G_TX0_TX_ASTATUS0r(_unit, _pc, _val) \ 637 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008060, (_val)) 638 #define MODIFY_XGXS16G_TX0_TX_ASTATUS0r(_unit, _pc, _val, _mask) \ 639 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008060, (_val), (_mask)) 640 641 /* Tx analog control 0 register */ 642 #define READ_XGXS16G_TX0_TX_ACONTROL0r(_unit, _pc, _val) \ 643 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008061, (_val)) 644 #define WRITE_XGXS16G_TX0_TX_ACONTROL0r(_unit, _pc, _val) \ 645 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008061, (_val)) 646 #define MODIFY_XGXS16G_TX0_TX_ACONTROL0r(_unit, _pc, _val, _mask) \ 647 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008061, (_val), (_mask)) 648 649 /* Tx test mux data 0 register */ 650 #define READ_XGXS16G_TX0_TX_MDATA0r(_unit, _pc, _val) \ 651 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008062, (_val)) 652 #define WRITE_XGXS16G_TX0_TX_MDATA0r(_unit, _pc, _val) \ 653 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008062, (_val)) 654 #define MODIFY_XGXS16G_TX0_TX_MDATA0r(_unit, _pc, _val, _mask) \ 655 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008062, (_val), (_mask)) 656 657 /* Tx test mux data 1 register */ 658 #define READ_XGXS16G_TX0_TX_MDATA1r(_unit, _pc, _val) \ 659 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008063, (_val)) 660 #define WRITE_XGXS16G_TX0_TX_MDATA1r(_unit, _pc, _val) \ 661 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008063, (_val)) 662 #define MODIFY_XGXS16G_TX0_TX_MDATA1r(_unit, _pc, _val, _mask) \ 663 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008063, (_val), (_mask)) 664 665 /* Tx analog status 1 register */ 666 #define READ_XGXS16G_TX0_TX_ASTATUS1r(_unit, _pc, _val) \ 667 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008064, (_val)) 668 #define WRITE_XGXS16G_TX0_TX_ASTATUS1r(_unit, _pc, _val) \ 669 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008064, (_val)) 670 #define MODIFY_XGXS16G_TX0_TX_ASTATUS1r(_unit, _pc, _val, _mask) \ 671 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008064, (_val), (_mask)) 672 673 /* Tx reserved analog control register */ 674 #define READ_XGXS16G_TX0_TX_BGVCMr(_unit, _pc, _val) \ 675 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008065, (_val)) 676 #define WRITE_XGXS16G_TX0_TX_BGVCMr(_unit, _pc, _val) \ 677 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008065, (_val)) 678 #define MODIFY_XGXS16G_TX0_TX_BGVCMr(_unit, _pc, _val, _mask) \ 679 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008065, (_val), (_mask)) 680 681 /* Tx reserved analog control register */ 682 #define READ_XGXS16G_TX0_TX_IBUFF_1T2Tr(_unit, _pc, _val) \ 683 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008066, (_val)) 684 #define WRITE_XGXS16G_TX0_TX_IBUFF_1T2Tr(_unit, _pc, _val) \ 685 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008066, (_val)) 686 #define MODIFY_XGXS16G_TX0_TX_IBUFF_1T2Tr(_unit, _pc, _val, _mask) \ 687 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008066, (_val), (_mask)) 688 689 /* Tx reserved analog control register */ 690 #define READ_XGXS16G_TX0_TX_DRIVERr(_unit, _pc, _val) \ 691 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008067, (_val)) 692 #define WRITE_XGXS16G_TX0_TX_DRIVERr(_unit, _pc, _val) \ 693 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008067, (_val)) 694 #define MODIFY_XGXS16G_TX0_TX_DRIVERr(_unit, _pc, _val, _mask) \ 695 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008067, (_val), (_mask)) 696 697 698 /**************************************************************************** 699 * XGXS16G_USER_TX1 700 */ 701 702 /* Tx analog status 0 register */ 703 #define READ_XGXS16G_TX1_TX_ASTATUS0r(_unit, _pc, _val) \ 704 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008070, (_val)) 705 #define WRITE_XGXS16G_TX1_TX_ASTATUS0r(_unit, _pc, _val) \ 706 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008070, (_val)) 707 #define MODIFY_XGXS16G_TX1_TX_ASTATUS0r(_unit, _pc, _val, _mask) \ 708 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008070, (_val), (_mask)) 709 710 /* Tx analog control 0 register */ 711 #define READ_XGXS16G_TX1_TX_ACONTROL0r(_unit, _pc, _val) \ 712 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008071, (_val)) 713 #define WRITE_XGXS16G_TX1_TX_ACONTROL0r(_unit, _pc, _val) \ 714 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008071, (_val)) 715 #define MODIFY_XGXS16G_TX1_TX_ACONTROL0r(_unit, _pc, _val, _mask) \ 716 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008071, (_val), (_mask)) 717 718 /* Tx test mux data 0 register */ 719 #define READ_XGXS16G_TX1_TX_MDATA0r(_unit, _pc, _val) \ 720 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008072, (_val)) 721 #define WRITE_XGXS16G_TX1_TX_MDATA0r(_unit, _pc, _val) \ 722 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008072, (_val)) 723 #define MODIFY_XGXS16G_TX1_TX_MDATA0r(_unit, _pc, _val, _mask) \ 724 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008072, (_val), (_mask)) 725 726 /* Tx test mux data 1 register */ 727 #define READ_XGXS16G_TX1_TX_MDATA1r(_unit, _pc, _val) \ 728 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008073, (_val)) 729 #define WRITE_XGXS16G_TX1_TX_MDATA1r(_unit, _pc, _val) \ 730 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008073, (_val)) 731 #define MODIFY_XGXS16G_TX1_TX_MDATA1r(_unit, _pc, _val, _mask) \ 732 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008073, (_val), (_mask)) 733 734 /* Tx analog status 1 register */ 735 #define READ_XGXS16G_TX1_TX_ASTATUS1r(_unit, _pc, _val) \ 736 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008074, (_val)) 737 #define WRITE_XGXS16G_TX1_TX_ASTATUS1r(_unit, _pc, _val) \ 738 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008074, (_val)) 739 #define MODIFY_XGXS16G_TX1_TX_ASTATUS1r(_unit, _pc, _val, _mask) \ 740 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008074, (_val), (_mask)) 741 742 /* Tx reserved analog control register */ 743 #define READ_XGXS16G_TX1_TX_BGVCMr(_unit, _pc, _val) \ 744 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008075, (_val)) 745 #define WRITE_XGXS16G_TX1_TX_BGVCMr(_unit, _pc, _val) \ 746 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008075, (_val)) 747 #define MODIFY_XGXS16G_TX1_TX_BGVCMr(_unit, _pc, _val, _mask) \ 748 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008075, (_val), (_mask)) 749 750 /* Tx reserved analog control register */ 751 #define READ_XGXS16G_TX1_TX_IBUFF_1T2Tr(_unit, _pc, _val) \ 752 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008076, (_val)) 753 #define WRITE_XGXS16G_TX1_TX_IBUFF_1T2Tr(_unit, _pc, _val) \ 754 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008076, (_val)) 755 #define MODIFY_XGXS16G_TX1_TX_IBUFF_1T2Tr(_unit, _pc, _val, _mask) \ 756 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008076, (_val), (_mask)) 757 758 /* Tx reserved analog control register */ 759 #define READ_XGXS16G_TX1_TX_DRIVERr(_unit, _pc, _val) \ 760 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008077, (_val)) 761 #define WRITE_XGXS16G_TX1_TX_DRIVERr(_unit, _pc, _val) \ 762 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008077, (_val)) 763 #define MODIFY_XGXS16G_TX1_TX_DRIVERr(_unit, _pc, _val, _mask) \ 764 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008077, (_val), (_mask)) 765 766 767 /**************************************************************************** 768 * XGXS16G_USER_TX2 769 */ 770 771 /* Tx analog status 0 register */ 772 #define READ_XGXS16G_TX2_TX_ASTATUS0r(_unit, _pc, _val) \ 773 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008080, (_val)) 774 #define WRITE_XGXS16G_TX2_TX_ASTATUS0r(_unit, _pc, _val) \ 775 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008080, (_val)) 776 #define MODIFY_XGXS16G_TX2_TX_ASTATUS0r(_unit, _pc, _val, _mask) \ 777 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008080, (_val), (_mask)) 778 779 /* Tx analog control 0 register */ 780 #define READ_XGXS16G_TX2_TX_ACONTROL0r(_unit, _pc, _val) \ 781 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008081, (_val)) 782 #define WRITE_XGXS16G_TX2_TX_ACONTROL0r(_unit, _pc, _val) \ 783 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008081, (_val)) 784 #define MODIFY_XGXS16G_TX2_TX_ACONTROL0r(_unit, _pc, _val, _mask) \ 785 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008081, (_val), (_mask)) 786 787 /* Tx test mux data 0 register */ 788 #define READ_XGXS16G_TX2_TX_MDATA0r(_unit, _pc, _val) \ 789 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008082, (_val)) 790 #define WRITE_XGXS16G_TX2_TX_MDATA0r(_unit, _pc, _val) \ 791 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008082, (_val)) 792 #define MODIFY_XGXS16G_TX2_TX_MDATA0r(_unit, _pc, _val, _mask) \ 793 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008082, (_val), (_mask)) 794 795 /* Tx test mux data 1 register */ 796 #define READ_XGXS16G_TX2_TX_MDATA1r(_unit, _pc, _val) \ 797 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008083, (_val)) 798 #define WRITE_XGXS16G_TX2_TX_MDATA1r(_unit, _pc, _val) \ 799 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008083, (_val)) 800 #define MODIFY_XGXS16G_TX2_TX_MDATA1r(_unit, _pc, _val, _mask) \ 801 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008083, (_val), (_mask)) 802 803 /* Tx analog status 1 register */ 804 #define READ_XGXS16G_TX2_TX_ASTATUS1r(_unit, _pc, _val) \ 805 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008084, (_val)) 806 #define WRITE_XGXS16G_TX2_TX_ASTATUS1r(_unit, _pc, _val) \ 807 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008084, (_val)) 808 #define MODIFY_XGXS16G_TX2_TX_ASTATUS1r(_unit, _pc, _val, _mask) \ 809 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008084, (_val), (_mask)) 810 811 /* Tx reserved analog control register */ 812 #define READ_XGXS16G_TX2_TX_BGVCMr(_unit, _pc, _val) \ 813 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008085, (_val)) 814 #define WRITE_XGXS16G_TX2_TX_BGVCMr(_unit, _pc, _val) \ 815 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008085, (_val)) 816 #define MODIFY_XGXS16G_TX2_TX_BGVCMr(_unit, _pc, _val, _mask) \ 817 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008085, (_val), (_mask)) 818 819 /* Tx reserved analog control register */ 820 #define READ_XGXS16G_TX2_TX_IBUFF_1T2Tr(_unit, _pc, _val) \ 821 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008086, (_val)) 822 #define WRITE_XGXS16G_TX2_TX_IBUFF_1T2Tr(_unit, _pc, _val) \ 823 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008086, (_val)) 824 #define MODIFY_XGXS16G_TX2_TX_IBUFF_1T2Tr(_unit, _pc, _val, _mask) \ 825 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008086, (_val), (_mask)) 826 827 /* Tx reserved analog control register */ 828 #define READ_XGXS16G_TX2_TX_DRIVERr(_unit, _pc, _val) \ 829 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008087, (_val)) 830 #define WRITE_XGXS16G_TX2_TX_DRIVERr(_unit, _pc, _val) \ 831 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008087, (_val)) 832 #define MODIFY_XGXS16G_TX2_TX_DRIVERr(_unit, _pc, _val, _mask) \ 833 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008087, (_val), (_mask)) 834 835 836 /**************************************************************************** 837 * XGXS16G_USER_TX3 838 */ 839 840 /* Tx analog status 0 register */ 841 #define READ_XGXS16G_TX3_TX_ASTATUS0r(_unit, _pc, _val) \ 842 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008090, (_val)) 843 #define WRITE_XGXS16G_TX3_TX_ASTATUS0r(_unit, _pc, _val) \ 844 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008090, (_val)) 845 #define MODIFY_XGXS16G_TX3_TX_ASTATUS0r(_unit, _pc, _val, _mask) \ 846 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008090, (_val), (_mask)) 847 848 /* Tx analog control 0 register */ 849 #define READ_XGXS16G_TX3_TX_ACONTROL0r(_unit, _pc, _val) \ 850 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008091, (_val)) 851 #define WRITE_XGXS16G_TX3_TX_ACONTROL0r(_unit, _pc, _val) \ 852 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008091, (_val)) 853 #define MODIFY_XGXS16G_TX3_TX_ACONTROL0r(_unit, _pc, _val, _mask) \ 854 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008091, (_val), (_mask)) 855 856 /* Tx test mux data 0 register */ 857 #define READ_XGXS16G_TX3_TX_MDATA0r(_unit, _pc, _val) \ 858 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008092, (_val)) 859 #define WRITE_XGXS16G_TX3_TX_MDATA0r(_unit, _pc, _val) \ 860 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008092, (_val)) 861 #define MODIFY_XGXS16G_TX3_TX_MDATA0r(_unit, _pc, _val, _mask) \ 862 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008092, (_val), (_mask)) 863 864 /* Tx test mux data 1 register */ 865 #define READ_XGXS16G_TX3_TX_MDATA1r(_unit, _pc, _val) \ 866 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008093, (_val)) 867 #define WRITE_XGXS16G_TX3_TX_MDATA1r(_unit, _pc, _val) \ 868 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008093, (_val)) 869 #define MODIFY_XGXS16G_TX3_TX_MDATA1r(_unit, _pc, _val, _mask) \ 870 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008093, (_val), (_mask)) 871 872 /* Tx analog status 1 register */ 873 #define READ_XGXS16G_TX3_TX_ASTATUS1r(_unit, _pc, _val) \ 874 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008094, (_val)) 875 #define WRITE_XGXS16G_TX3_TX_ASTATUS1r(_unit, _pc, _val) \ 876 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008094, (_val)) 877 #define MODIFY_XGXS16G_TX3_TX_ASTATUS1r(_unit, _pc, _val, _mask) \ 878 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008094, (_val), (_mask)) 879 880 /* Tx reserved analog control register */ 881 #define READ_XGXS16G_TX3_TX_BGVCMr(_unit, _pc, _val) \ 882 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008095, (_val)) 883 #define WRITE_XGXS16G_TX3_TX_BGVCMr(_unit, _pc, _val) \ 884 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008095, (_val)) 885 #define MODIFY_XGXS16G_TX3_TX_BGVCMr(_unit, _pc, _val, _mask) \ 886 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008095, (_val), (_mask)) 887 888 /* Tx reserved analog control register */ 889 #define READ_XGXS16G_TX3_TX_IBUFF_1T2Tr(_unit, _pc, _val) \ 890 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008096, (_val)) 891 #define WRITE_XGXS16G_TX3_TX_IBUFF_1T2Tr(_unit, _pc, _val) \ 892 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008096, (_val)) 893 #define MODIFY_XGXS16G_TX3_TX_IBUFF_1T2Tr(_unit, _pc, _val, _mask) \ 894 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008096, (_val), (_mask)) 895 896 /* Tx reserved analog control register */ 897 #define READ_XGXS16G_TX3_TX_DRIVERr(_unit, _pc, _val) \ 898 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008097, (_val)) 899 #define WRITE_XGXS16G_TX3_TX_DRIVERr(_unit, _pc, _val) \ 900 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008097, (_val)) 901 #define MODIFY_XGXS16G_TX3_TX_DRIVERr(_unit, _pc, _val, _mask) \ 902 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008097, (_val), (_mask)) 903 904 905 /**************************************************************************** 906 * XGXS16G_USER_TX_All 907 */ 908 909 /* Tx analog status 0 register */ 910 #define READ_XGXS16G_TX_ALL_TX_ASTATUS0r(_unit, _pc, _val) \ 911 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a0, (_val)) 912 #define WRITE_XGXS16G_TX_ALL_TX_ASTATUS0r(_unit, _pc, _val) \ 913 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a0, (_val)) 914 #define MODIFY_XGXS16G_TX_ALL_TX_ASTATUS0r(_unit, _pc, _val, _mask) \ 915 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a0, (_val), (_mask)) 916 917 /* Tx analog control 0 register */ 918 #define READ_XGXS16G_TX_ALL_TX_ACONTROL0r(_unit, _pc, _val) \ 919 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a1, (_val)) 920 #define WRITE_XGXS16G_TX_ALL_TX_ACONTROL0r(_unit, _pc, _val) \ 921 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a1, (_val)) 922 #define MODIFY_XGXS16G_TX_ALL_TX_ACONTROL0r(_unit, _pc, _val, _mask) \ 923 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a1, (_val), (_mask)) 924 925 /* Tx test mux data 0 register */ 926 #define READ_XGXS16G_TX_ALL_TX_MDATA0r(_unit, _pc, _val) \ 927 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a2, (_val)) 928 #define WRITE_XGXS16G_TX_ALL_TX_MDATA0r(_unit, _pc, _val) \ 929 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a2, (_val)) 930 #define MODIFY_XGXS16G_TX_ALL_TX_MDATA0r(_unit, _pc, _val, _mask) \ 931 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a2, (_val), (_mask)) 932 933 /* Tx test mux data 1 register */ 934 #define READ_XGXS16G_TX_ALL_TX_MDATA1r(_unit, _pc, _val) \ 935 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a3, (_val)) 936 #define WRITE_XGXS16G_TX_ALL_TX_MDATA1r(_unit, _pc, _val) \ 937 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a3, (_val)) 938 #define MODIFY_XGXS16G_TX_ALL_TX_MDATA1r(_unit, _pc, _val, _mask) \ 939 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a3, (_val), (_mask)) 940 941 /* Tx analog status 1 register */ 942 #define READ_XGXS16G_TX_ALL_TX_ASTATUS1r(_unit, _pc, _val) \ 943 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a4, (_val)) 944 #define WRITE_XGXS16G_TX_ALL_TX_ASTATUS1r(_unit, _pc, _val) \ 945 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a4, (_val)) 946 #define MODIFY_XGXS16G_TX_ALL_TX_ASTATUS1r(_unit, _pc, _val, _mask) \ 947 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a4, (_val), (_mask)) 948 949 /* Tx reserved analog control register */ 950 #define READ_XGXS16G_TX_ALL_TX_BGVCMr(_unit, _pc, _val) \ 951 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a5, (_val)) 952 #define WRITE_XGXS16G_TX_ALL_TX_BGVCMr(_unit, _pc, _val) \ 953 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a5, (_val)) 954 #define MODIFY_XGXS16G_TX_ALL_TX_BGVCMr(_unit, _pc, _val, _mask) \ 955 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a5, (_val), (_mask)) 956 957 /* Tx reserved analog control register */ 958 #define READ_XGXS16G_TX_ALL_TX_IBUFF_1T2Tr(_unit, _pc, _val) \ 959 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a6, (_val)) 960 #define WRITE_XGXS16G_TX_ALL_TX_IBUFF_1T2Tr(_unit, _pc, _val) \ 961 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a6, (_val)) 962 #define MODIFY_XGXS16G_TX_ALL_TX_IBUFF_1T2Tr(_unit, _pc, _val, _mask) \ 963 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a6, (_val), (_mask)) 964 965 /* Tx reserved analog control register */ 966 #define READ_XGXS16G_TX_ALL_TX_DRIVERr(_unit, _pc, _val) \ 967 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a7, (_val)) 968 #define WRITE_XGXS16G_TX_ALL_TX_DRIVERr(_unit, _pc, _val) \ 969 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a7, (_val)) 970 #define MODIFY_XGXS16G_TX_ALL_TX_DRIVERr(_unit, _pc, _val, _mask) \ 971 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a7, (_val), (_mask)) 972 973 974 /**************************************************************************** 975 * XGXS16G_USER_RX0 976 */ 977 978 /* Rx lane status register */ 979 #define READ_XGXS16G_RX0_RX_STATUSr(_unit, _pc, _val) \ 980 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080b0, (_val)) 981 #define WRITE_XGXS16G_RX0_RX_STATUSr(_unit, _pc, _val) \ 982 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080b0, (_val)) 983 #define MODIFY_XGXS16G_RX0_RX_STATUSr(_unit, _pc, _val, _mask) \ 984 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b0, (_val), (_mask)) 985 986 /* Rx lane control register */ 987 #define READ_XGXS16G_RX0_RX_CONTROLr(_unit, _pc, _val) \ 988 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080b1, (_val)) 989 #define WRITE_XGXS16G_RX0_RX_CONTROLr(_unit, _pc, _val) \ 990 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080b1, (_val)) 991 #define MODIFY_XGXS16G_RX0_RX_CONTROLr(_unit, _pc, _val, _mask) \ 992 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b1, (_val), (_mask)) 993 994 /* Rx lane control register */ 995 #define READ_XGXS16G_RX0_RX_TESTr(_unit, _pc, _val) \ 996 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080b8, (_val)) 997 #define WRITE_XGXS16G_RX0_RX_TESTr(_unit, _pc, _val) \ 998 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080b8, (_val)) 999 #define MODIFY_XGXS16G_RX0_RX_TESTr(_unit, _pc, _val, _mask) \ 1000 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b8, (_val), (_mask)) 1001 1002 /* Rx 1G Control register */ 1003 #define READ_XGXS16G_RX0_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \ 1004 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080b9, (_val)) 1005 #define WRITE_XGXS16G_RX0_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \ 1006 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080b9, (_val)) 1007 #define MODIFY_XGXS16G_RX0_RX_CONTROL_1G_TYPEr(_unit, _pc, _val, _mask) \ 1008 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b9, (_val), (_mask)) 1009 1010 /* Rx analog status register */ 1011 #define READ_XGXS16G_RX0_RX_ASTATUSr(_unit, _pc, _val) \ 1012 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080bb, (_val)) 1013 #define WRITE_XGXS16G_RX0_RX_ASTATUSr(_unit, _pc, _val) \ 1014 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080bb, (_val)) 1015 #define MODIFY_XGXS16G_RX0_RX_ASTATUSr(_unit, _pc, _val, _mask) \ 1016 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bb, (_val), (_mask)) 1017 1018 /* Rx reserved analog control register */ 1019 #define READ_XGXS16G_RX0_RX_ANALOGBIAS0r(_unit, _pc, _val) \ 1020 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080bc, (_val)) 1021 #define WRITE_XGXS16G_RX0_RX_ANALOGBIAS0r(_unit, _pc, _val) \ 1022 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080bc, (_val)) 1023 #define MODIFY_XGXS16G_RX0_RX_ANALOGBIAS0r(_unit, _pc, _val, _mask) \ 1024 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bc, (_val), (_mask)) 1025 1026 /* Rx reserved analog control register */ 1027 #define READ_XGXS16G_RX0_RX_ANALOGBIAS1r(_unit, _pc, _val) \ 1028 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080bd, (_val)) 1029 #define WRITE_XGXS16G_RX0_RX_ANALOGBIAS1r(_unit, _pc, _val) \ 1030 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080bd, (_val)) 1031 #define MODIFY_XGXS16G_RX0_RX_ANALOGBIAS1r(_unit, _pc, _val, _mask) \ 1032 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bd, (_val), (_mask)) 1033 1034 /* Rx reserved analog control register */ 1035 #define READ_XGXS16G_RX0_RX_ANALOGBIAS2r(_unit, _pc, _val) \ 1036 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080be, (_val)) 1037 #define WRITE_XGXS16G_RX0_RX_ANALOGBIAS2r(_unit, _pc, _val) \ 1038 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080be, (_val)) 1039 #define MODIFY_XGXS16G_RX0_RX_ANALOGBIAS2r(_unit, _pc, _val, _mask) \ 1040 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080be, (_val), (_mask)) 1041 1042 1043 /**************************************************************************** 1044 * XGXS16G_USER_RX1 1045 */ 1046 1047 /* Rx lane status register */ 1048 #define READ_XGXS16G_RX1_RX_STATUSr(_unit, _pc, _val) \ 1049 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080c0, (_val)) 1050 #define WRITE_XGXS16G_RX1_RX_STATUSr(_unit, _pc, _val) \ 1051 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080c0, (_val)) 1052 #define MODIFY_XGXS16G_RX1_RX_STATUSr(_unit, _pc, _val, _mask) \ 1053 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c0, (_val), (_mask)) 1054 1055 /* Rx lane control register */ 1056 #define READ_XGXS16G_RX1_RX_CONTROLr(_unit, _pc, _val) \ 1057 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080c1, (_val)) 1058 #define WRITE_XGXS16G_RX1_RX_CONTROLr(_unit, _pc, _val) \ 1059 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080c1, (_val)) 1060 #define MODIFY_XGXS16G_RX1_RX_CONTROLr(_unit, _pc, _val, _mask) \ 1061 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c1, (_val), (_mask)) 1062 1063 /* Rx lane control register */ 1064 #define READ_XGXS16G_RX1_RX_TESTr(_unit, _pc, _val) \ 1065 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080c8, (_val)) 1066 #define WRITE_XGXS16G_RX1_RX_TESTr(_unit, _pc, _val) \ 1067 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080c8, (_val)) 1068 #define MODIFY_XGXS16G_RX1_RX_TESTr(_unit, _pc, _val, _mask) \ 1069 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c8, (_val), (_mask)) 1070 1071 /* Rx 1G Control register */ 1072 #define READ_XGXS16G_RX1_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \ 1073 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080c9, (_val)) 1074 #define WRITE_XGXS16G_RX1_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \ 1075 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080c9, (_val)) 1076 #define MODIFY_XGXS16G_RX1_RX_CONTROL_1G_TYPEr(_unit, _pc, _val, _mask) \ 1077 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c9, (_val), (_mask)) 1078 1079 /* Rx analog status register */ 1080 #define READ_XGXS16G_RX1_RX_ASTATUSr(_unit, _pc, _val) \ 1081 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080cb, (_val)) 1082 #define WRITE_XGXS16G_RX1_RX_ASTATUSr(_unit, _pc, _val) \ 1083 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080cb, (_val)) 1084 #define MODIFY_XGXS16G_RX1_RX_ASTATUSr(_unit, _pc, _val, _mask) \ 1085 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cb, (_val), (_mask)) 1086 1087 /* Rx reserved analog control register */ 1088 #define READ_XGXS16G_RX1_RX_ANALOGBIAS0r(_unit, _pc, _val) \ 1089 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080cc, (_val)) 1090 #define WRITE_XGXS16G_RX1_RX_ANALOGBIAS0r(_unit, _pc, _val) \ 1091 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080cc, (_val)) 1092 #define MODIFY_XGXS16G_RX1_RX_ANALOGBIAS0r(_unit, _pc, _val, _mask) \ 1093 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cc, (_val), (_mask)) 1094 1095 /* Rx reserved analog control register */ 1096 #define READ_XGXS16G_RX1_RX_ANALOGBIAS1r(_unit, _pc, _val) \ 1097 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080cd, (_val)) 1098 #define WRITE_XGXS16G_RX1_RX_ANALOGBIAS1r(_unit, _pc, _val) \ 1099 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080cd, (_val)) 1100 #define MODIFY_XGXS16G_RX1_RX_ANALOGBIAS1r(_unit, _pc, _val, _mask) \ 1101 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cd, (_val), (_mask)) 1102 1103 /* Rx reserved analog control register */ 1104 #define READ_XGXS16G_RX1_RX_ANALOGBIAS2r(_unit, _pc, _val) \ 1105 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080ce, (_val)) 1106 #define WRITE_XGXS16G_RX1_RX_ANALOGBIAS2r(_unit, _pc, _val) \ 1107 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080ce, (_val)) 1108 #define MODIFY_XGXS16G_RX1_RX_ANALOGBIAS2r(_unit, _pc, _val, _mask) \ 1109 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ce, (_val), (_mask)) 1110 1111 1112 /**************************************************************************** 1113 * XGXS16G_USER_RX2 1114 */ 1115 1116 /* Rx lane status register */ 1117 #define READ_XGXS16G_RX2_RX_STATUSr(_unit, _pc, _val) \ 1118 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080d0, (_val)) 1119 #define WRITE_XGXS16G_RX2_RX_STATUSr(_unit, _pc, _val) \ 1120 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080d0, (_val)) 1121 #define MODIFY_XGXS16G_RX2_RX_STATUSr(_unit, _pc, _val, _mask) \ 1122 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d0, (_val), (_mask)) 1123 1124 /* Rx lane control register */ 1125 #define READ_XGXS16G_RX2_RX_CONTROLr(_unit, _pc, _val) \ 1126 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080d1, (_val)) 1127 #define WRITE_XGXS16G_RX2_RX_CONTROLr(_unit, _pc, _val) \ 1128 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080d1, (_val)) 1129 #define MODIFY_XGXS16G_RX2_RX_CONTROLr(_unit, _pc, _val, _mask) \ 1130 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d1, (_val), (_mask)) 1131 1132 /* Rx lane control register */ 1133 #define READ_XGXS16G_RX2_RX_TESTr(_unit, _pc, _val) \ 1134 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080d8, (_val)) 1135 #define WRITE_XGXS16G_RX2_RX_TESTr(_unit, _pc, _val) \ 1136 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080d8, (_val)) 1137 #define MODIFY_XGXS16G_RX2_RX_TESTr(_unit, _pc, _val, _mask) \ 1138 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d8, (_val), (_mask)) 1139 1140 /* Rx 1G Control register */ 1141 #define READ_XGXS16G_RX2_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \ 1142 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080d9, (_val)) 1143 #define WRITE_XGXS16G_RX2_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \ 1144 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080d9, (_val)) 1145 #define MODIFY_XGXS16G_RX2_RX_CONTROL_1G_TYPEr(_unit, _pc, _val, _mask) \ 1146 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d9, (_val), (_mask)) 1147 1148 /* Rx analog status register */ 1149 #define READ_XGXS16G_RX2_RX_ASTATUSr(_unit, _pc, _val) \ 1150 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080db, (_val)) 1151 #define WRITE_XGXS16G_RX2_RX_ASTATUSr(_unit, _pc, _val) \ 1152 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080db, (_val)) 1153 #define MODIFY_XGXS16G_RX2_RX_ASTATUSr(_unit, _pc, _val, _mask) \ 1154 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080db, (_val), (_mask)) 1155 1156 /* Rx reserved analog control register */ 1157 #define READ_XGXS16G_RX2_RX_ANALOGBIAS0r(_unit, _pc, _val) \ 1158 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080dc, (_val)) 1159 #define WRITE_XGXS16G_RX2_RX_ANALOGBIAS0r(_unit, _pc, _val) \ 1160 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080dc, (_val)) 1161 #define MODIFY_XGXS16G_RX2_RX_ANALOGBIAS0r(_unit, _pc, _val, _mask) \ 1162 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080dc, (_val), (_mask)) 1163 1164 /* Rx reserved analog control register */ 1165 #define READ_XGXS16G_RX2_RX_ANALOGBIAS1r(_unit, _pc, _val) \ 1166 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080dd, (_val)) 1167 #define WRITE_XGXS16G_RX2_RX_ANALOGBIAS1r(_unit, _pc, _val) \ 1168 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080dd, (_val)) 1169 #define MODIFY_XGXS16G_RX2_RX_ANALOGBIAS1r(_unit, _pc, _val, _mask) \ 1170 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080dd, (_val), (_mask)) 1171 1172 /* Rx reserved analog control register */ 1173 #define READ_XGXS16G_RX2_RX_ANALOGBIAS2r(_unit, _pc, _val) \ 1174 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080de, (_val)) 1175 #define WRITE_XGXS16G_RX2_RX_ANALOGBIAS2r(_unit, _pc, _val) \ 1176 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080de, (_val)) 1177 #define MODIFY_XGXS16G_RX2_RX_ANALOGBIAS2r(_unit, _pc, _val, _mask) \ 1178 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080de, (_val), (_mask)) 1179 1180 1181 /**************************************************************************** 1182 * XGXS16G_USER_RX3 1183 */ 1184 1185 /* Rx lane status register */ 1186 #define READ_XGXS16G_RX3_RX_STATUSr(_unit, _pc, _val) \ 1187 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080e0, (_val)) 1188 #define WRITE_XGXS16G_RX3_RX_STATUSr(_unit, _pc, _val) \ 1189 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080e0, (_val)) 1190 #define MODIFY_XGXS16G_RX3_RX_STATUSr(_unit, _pc, _val, _mask) \ 1191 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e0, (_val), (_mask)) 1192 1193 /* Rx lane control register */ 1194 #define READ_XGXS16G_RX3_RX_CONTROLr(_unit, _pc, _val) \ 1195 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080e1, (_val)) 1196 #define WRITE_XGXS16G_RX3_RX_CONTROLr(_unit, _pc, _val) \ 1197 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080e1, (_val)) 1198 #define MODIFY_XGXS16G_RX3_RX_CONTROLr(_unit, _pc, _val, _mask) \ 1199 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e1, (_val), (_mask)) 1200 1201 /* Rx lane control register */ 1202 #define READ_XGXS16G_RX3_RX_TESTr(_unit, _pc, _val) \ 1203 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080e8, (_val)) 1204 #define WRITE_XGXS16G_RX3_RX_TESTr(_unit, _pc, _val) \ 1205 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080e8, (_val)) 1206 #define MODIFY_XGXS16G_RX3_RX_TESTr(_unit, _pc, _val, _mask) \ 1207 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e8, (_val), (_mask)) 1208 1209 /* Rx 1G Control register */ 1210 #define READ_XGXS16G_RX3_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \ 1211 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080e9, (_val)) 1212 #define WRITE_XGXS16G_RX3_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \ 1213 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080e9, (_val)) 1214 #define MODIFY_XGXS16G_RX3_RX_CONTROL_1G_TYPEr(_unit, _pc, _val, _mask) \ 1215 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e9, (_val), (_mask)) 1216 1217 /* Rx analog status register */ 1218 #define READ_XGXS16G_RX3_RX_ASTATUSr(_unit, _pc, _val) \ 1219 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080eb, (_val)) 1220 #define WRITE_XGXS16G_RX3_RX_ASTATUSr(_unit, _pc, _val) \ 1221 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080eb, (_val)) 1222 #define MODIFY_XGXS16G_RX3_RX_ASTATUSr(_unit, _pc, _val, _mask) \ 1223 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080eb, (_val), (_mask)) 1224 1225 /* Rx reserved analog control register */ 1226 #define READ_XGXS16G_RX3_RX_ANALOGBIAS0r(_unit, _pc, _val) \ 1227 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080ec, (_val)) 1228 #define WRITE_XGXS16G_RX3_RX_ANALOGBIAS0r(_unit, _pc, _val) \ 1229 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080ec, (_val)) 1230 #define MODIFY_XGXS16G_RX3_RX_ANALOGBIAS0r(_unit, _pc, _val, _mask) \ 1231 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ec, (_val), (_mask)) 1232 1233 /* Rx reserved analog control register */ 1234 #define READ_XGXS16G_RX3_RX_ANALOGBIAS1r(_unit, _pc, _val) \ 1235 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080ed, (_val)) 1236 #define WRITE_XGXS16G_RX3_RX_ANALOGBIAS1r(_unit, _pc, _val) \ 1237 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080ed, (_val)) 1238 #define MODIFY_XGXS16G_RX3_RX_ANALOGBIAS1r(_unit, _pc, _val, _mask) \ 1239 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ed, (_val), (_mask)) 1240 1241 /* Rx reserved analog control register */ 1242 #define READ_XGXS16G_RX3_RX_ANALOGBIAS2r(_unit, _pc, _val) \ 1243 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080ee, (_val)) 1244 #define WRITE_XGXS16G_RX3_RX_ANALOGBIAS2r(_unit, _pc, _val) \ 1245 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080ee, (_val)) 1246 #define MODIFY_XGXS16G_RX3_RX_ANALOGBIAS2r(_unit, _pc, _val, _mask) \ 1247 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ee, (_val), (_mask)) 1248 1249 1250 /**************************************************************************** 1251 * XGXS16G_USER_RX_All 1252 */ 1253 1254 /* Rx lane status register */ 1255 #define READ_XGXS16G_RX_ALL_RX_STATUSr(_unit, _pc, _val) \ 1256 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080f0, (_val)) 1257 #define WRITE_XGXS16G_RX_ALL_RX_STATUSr(_unit, _pc, _val) \ 1258 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080f0, (_val)) 1259 #define MODIFY_XGXS16G_RX_ALL_RX_STATUSr(_unit, _pc, _val, _mask) \ 1260 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f0, (_val), (_mask)) 1261 1262 /* Rx lane control register */ 1263 #define READ_XGXS16G_RX_ALL_RX_CONTROLr(_unit, _pc, _val) \ 1264 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080f1, (_val)) 1265 #define WRITE_XGXS16G_RX_ALL_RX_CONTROLr(_unit, _pc, _val) \ 1266 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080f1, (_val)) 1267 #define MODIFY_XGXS16G_RX_ALL_RX_CONTROLr(_unit, _pc, _val, _mask) \ 1268 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f1, (_val), (_mask)) 1269 1270 /* Rx lane control register */ 1271 #define READ_XGXS16G_RX_ALL_RX_TESTr(_unit, _pc, _val) \ 1272 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080f8, (_val)) 1273 #define WRITE_XGXS16G_RX_ALL_RX_TESTr(_unit, _pc, _val) \ 1274 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080f8, (_val)) 1275 #define MODIFY_XGXS16G_RX_ALL_RX_TESTr(_unit, _pc, _val, _mask) \ 1276 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f8, (_val), (_mask)) 1277 1278 /* Rx 1G Control register */ 1279 #define READ_XGXS16G_RX_ALL_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \ 1280 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080f9, (_val)) 1281 #define WRITE_XGXS16G_RX_ALL_RX_CONTROL_1G_TYPEr(_unit, _pc, _val) \ 1282 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080f9, (_val)) 1283 #define MODIFY_XGXS16G_RX_ALL_RX_CONTROL_1G_TYPEr(_unit, _pc, _val, _mask) \ 1284 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f9, (_val), (_mask)) 1285 1286 /* RX Control PCIE */ 1287 #define READ_XGXS16G_RX_CONTROL_PCIEr(_unit, _pc, _val) \ 1288 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080fa, (_val)) 1289 #define WRITE_XGXS16G_RX_CONTROL_PCIEr(_unit, _pc, _val) \ 1290 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080fa, (_val)) 1291 #define MODIFY_XGXS16G_RX_CONTROL_PCIEr(_unit, _pc, _val, _mask) \ 1292 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fa, (_val), (_mask)) 1293 1294 /* Lane0: RX Control PCIE */ 1295 #define READ_XGXS16G_RX0_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val) \ 1296 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080ba, (_val)) 1297 #define WRITE_XGXS16G_RX0_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val) \ 1298 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080ba, (_val)) 1299 #define MODIFY_XGXS16G_RX0_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val, _mask) \ 1300 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ba, (_val), (_mask)) 1301 1302 /* Lane1: RX Control PCIE */ 1303 #define READ_XGXS16G_RX1_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val) \ 1304 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080c1, (_val)) 1305 #define WRITE_XGXS16G_RX1_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val) \ 1306 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080c1, (_val)) 1307 #define MODIFY_XGXS16G_RX1_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val, _mask) \ 1308 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c1, (_val), (_mask)) 1309 1310 /* Lane2: RX Control PCIE */ 1311 #define READ_XGXS16G_RX2_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val) \ 1312 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080da, (_val)) 1313 #define WRITE_XGXS16G_RX2_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val) \ 1314 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080da, (_val)) 1315 #define MODIFY_XGXS16G_RX2_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val, _mask) \ 1316 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080da, (_val), (_mask)) 1317 1318 /* Lane3: RX Control PCIE */ 1319 #define READ_XGXS16G_RX3_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val) \ 1320 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080ea, (_val)) 1321 #define WRITE_XGXS16G_RX3_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val) \ 1322 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080ea, (_val)) 1323 #define MODIFY_XGXS16G_RX3_ANA_RX_CONTROL_PCIEr(_unit, _pc, _val, _mask) \ 1324 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ea, (_val), (_mask)) 1325 1326 1327 /* Rx analog status register */ 1328 #define READ_XGXS16G_RX_ALL_RX_ASTATUSr(_unit, _pc, _val) \ 1329 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080fb, (_val)) 1330 #define WRITE_XGXS16G_RX_ALL_RX_ASTATUSr(_unit, _pc, _val) \ 1331 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080fb, (_val)) 1332 #define MODIFY_XGXS16G_RX_ALL_RX_ASTATUSr(_unit, _pc, _val, _mask) \ 1333 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fb, (_val), (_mask)) 1334 1335 /* Rx reserved analog control register */ 1336 #define READ_XGXS16G_RX_ALL_RX_ANALOGBIAS0r(_unit, _pc, _val) \ 1337 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080fc, (_val)) 1338 #define WRITE_XGXS16G_RX_ALL_RX_ANALOGBIAS0r(_unit, _pc, _val) \ 1339 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080fc, (_val)) 1340 #define MODIFY_XGXS16G_RX_ALL_RX_ANALOGBIAS0r(_unit, _pc, _val, _mask) \ 1341 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fc, (_val), (_mask)) 1342 1343 /* Rx reserved analog control register */ 1344 #define READ_XGXS16G_RX_ALL_RX_ANALOGBIAS1r(_unit, _pc, _val) \ 1345 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080fd, (_val)) 1346 #define WRITE_XGXS16G_RX_ALL_RX_ANALOGBIAS1r(_unit, _pc, _val) \ 1347 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080fd, (_val)) 1348 #define MODIFY_XGXS16G_RX_ALL_RX_ANALOGBIAS1r(_unit, _pc, _val, _mask) \ 1349 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fd, (_val), (_mask)) 1350 1351 /* Rx reserved analog control register */ 1352 #define READ_XGXS16G_RX_ALL_RX_ANALOGBIAS2r(_unit, _pc, _val) \ 1353 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080fe, (_val)) 1354 #define WRITE_XGXS16G_RX_ALL_RX_ANALOGBIAS2r(_unit, _pc, _val) \ 1355 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080fe, (_val)) 1356 #define MODIFY_XGXS16G_RX_ALL_RX_ANALOGBIAS2r(_unit, _pc, _val, _mask) \ 1357 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fe, (_val), (_mask)) 1358 1359 1360 /**************************************************************************** 1361 * XGXS16G_USER_XgxsBlk2 1362 */ 1363 1364 /* Receiver lane swap control register */ 1365 #define READ_XGXS16G_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val) \ 1366 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008100, (_val)) 1367 #define WRITE_XGXS16G_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val) \ 1368 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008100, (_val)) 1369 #define MODIFY_XGXS16G_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val, _mask) \ 1370 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008100, (_val), (_mask)) 1371 1372 /* Transmit lane swap control register */ 1373 #define READ_XGXS16G_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val) \ 1374 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008101, (_val)) 1375 #define WRITE_XGXS16G_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val) \ 1376 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008101, (_val)) 1377 #define MODIFY_XGXS16G_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val, _mask) \ 1378 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008101, (_val), (_mask)) 1379 1380 /* ||Q|| ordered set, lanes 0 & 1 register */ 1381 #define READ_XGXS16G_XGXSBLK2_QSETLNS01r(_unit, _pc, _val) \ 1382 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008102, (_val)) 1383 #define WRITE_XGXS16G_XGXSBLK2_QSETLNS01r(_unit, _pc, _val) \ 1384 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008102, (_val)) 1385 #define MODIFY_XGXS16G_XGXSBLK2_QSETLNS01r(_unit, _pc, _val, _mask) \ 1386 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008102, (_val), (_mask)) 1387 1388 /* ||Q|| ordered set, lanes 2 & 3 register */ 1389 #define READ_XGXS16G_XGXSBLK2_QSETLNS23r(_unit, _pc, _val) \ 1390 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008103, (_val)) 1391 #define WRITE_XGXS16G_XGXSBLK2_QSETLNS23r(_unit, _pc, _val) \ 1392 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008103, (_val)) 1393 #define MODIFY_XGXS16G_XGXSBLK2_QSETLNS23r(_unit, _pc, _val, _mask) \ 1394 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008103, (_val), (_mask)) 1395 1396 /* AN 10G resolution mode control register */ 1397 #define READ_XGXS16G_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val) \ 1398 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008104, (_val)) 1399 #define WRITE_XGXS16G_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val) \ 1400 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008104, (_val)) 1401 #define MODIFY_XGXS16G_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val, _mask) \ 1402 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008104, (_val), (_mask)) 1403 1404 /* indCombCtrl register */ 1405 #define READ_XGXS16G_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val) \ 1406 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008105, (_val)) 1407 #define WRITE_XGXS16G_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val) \ 1408 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008105, (_val)) 1409 #define MODIFY_XGXS16G_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val, _mask) \ 1410 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008105, (_val), (_mask)) 1411 1412 /* Test mode lane select register */ 1413 #define READ_XGXS16G_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val) \ 1414 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008106, (_val)) 1415 #define WRITE_XGXS16G_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val) \ 1416 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008106, (_val)) 1417 #define MODIFY_XGXS16G_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val, _mask) \ 1418 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008106, (_val), (_mask)) 1419 1420 /* Test mode monitor control register */ 1421 #define READ_XGXS16G_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val) \ 1422 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008107, (_val)) 1423 #define WRITE_XGXS16G_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val) \ 1424 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008107, (_val)) 1425 #define MODIFY_XGXS16G_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val, _mask) \ 1426 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008107, (_val), (_mask)) 1427 1428 /* Test mode mux control register */ 1429 #define READ_XGXS16G_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val) \ 1430 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008108, (_val)) 1431 #define WRITE_XGXS16G_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val) \ 1432 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008108, (_val)) 1433 #define MODIFY_XGXS16G_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val, _mask) \ 1434 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008108, (_val), (_mask)) 1435 1436 /* 10GBASE-CX4 signal detect timeout value */ 1437 #define READ_XGXS16G_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val) \ 1438 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008109, (_val)) 1439 #define WRITE_XGXS16G_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val) \ 1440 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008109, (_val)) 1441 #define MODIFY_XGXS16G_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val, _mask) \ 1442 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008109, (_val), (_mask)) 1443 1444 /* Lane reset */ 1445 #define READ_XGXS16G_XGXSBLK2_LANERESETr(_unit, _pc, _val) \ 1446 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000810a, (_val)) 1447 #define WRITE_XGXS16G_XGXSBLK2_LANERESETr(_unit, _pc, _val) \ 1448 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000810a, (_val)) 1449 #define MODIFY_XGXS16G_XGXSBLK2_LANERESETr(_unit, _pc, _val, _mask) \ 1450 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810a, (_val), (_mask)) 1451 1452 1453 /**************************************************************************** 1454 * XGXS16G_IN_BAND_MDIO 1455 */ 1456 1457 /**************************************************************************** 1458 * XGXS16G_USER_GP_Status 1459 */ 1460 1461 /* Miscelaneous Rx status register */ 1462 #define READ_XGXS16G_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val) \ 1463 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008120, (_val)) 1464 #define WRITE_XGXS16G_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val) \ 1465 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008120, (_val)) 1466 #define MODIFY_XGXS16G_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val, _mask) \ 1467 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008120, (_val), (_mask)) 1468 1469 /* XGXG status register */ 1470 #define READ_XGXS16G_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val) \ 1471 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008121, (_val)) 1472 #define WRITE_XGXS16G_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val) \ 1473 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008121, (_val)) 1474 #define MODIFY_XGXS16G_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val, _mask) \ 1475 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008121, (_val), (_mask)) 1476 1477 /* XGXG status 1 register */ 1478 #define READ_XGXS16G_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \ 1479 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008122, (_val)) 1480 #define WRITE_XGXS16G_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \ 1481 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008122, (_val)) 1482 #define MODIFY_XGXS16G_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val, _mask) \ 1483 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008122, (_val), (_mask)) 1484 1485 /* XGXG status 2 register */ 1486 #define READ_XGXS16G_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val) \ 1487 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008123, (_val)) 1488 #define WRITE_XGXS16G_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val) \ 1489 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008123, (_val)) 1490 #define MODIFY_XGXS16G_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val, _mask) \ 1491 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008123, (_val), (_mask)) 1492 1493 /* 1000X status 1 register */ 1494 #define READ_XGXS16G_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \ 1495 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008124, (_val)) 1496 #define WRITE_XGXS16G_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \ 1497 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008124, (_val)) 1498 #define MODIFY_XGXS16G_GP_STATUS_STATUS1000X1r(_unit, _pc, _val, _mask) \ 1499 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008124, (_val), (_mask)) 1500 1501 /* 1000X status 2 register */ 1502 #define READ_XGXS16G_GP_STATUS_STATUS1000X2r(_unit, _pc, _val) \ 1503 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008125, (_val)) 1504 #define WRITE_XGXS16G_GP_STATUS_STATUS1000X2r(_unit, _pc, _val) \ 1505 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008125, (_val)) 1506 #define MODIFY_XGXS16G_GP_STATUS_STATUS1000X2r(_unit, _pc, _val, _mask) \ 1507 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008125, (_val), (_mask)) 1508 1509 /* 1000X status 3 register */ 1510 #define READ_XGXS16G_GP_STATUS_STATUS1000X3r(_unit, _pc, _val) \ 1511 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008126, (_val)) 1512 #define WRITE_XGXS16G_GP_STATUS_STATUS1000X3r(_unit, _pc, _val) \ 1513 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008126, (_val)) 1514 #define MODIFY_XGXS16G_GP_STATUS_STATUS1000X3r(_unit, _pc, _val, _mask) \ 1515 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008126, (_val), (_mask)) 1516 1517 /* Test port out bits 15:0, tpout[15:0] */ 1518 #define READ_XGXS16G_GP_STATUS_TPOUT_1r(_unit, _pc, _val) \ 1519 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008127, (_val)) 1520 #define WRITE_XGXS16G_GP_STATUS_TPOUT_1r(_unit, _pc, _val) \ 1521 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008127, (_val)) 1522 #define MODIFY_XGXS16G_GP_STATUS_TPOUT_1r(_unit, _pc, _val, _mask) \ 1523 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008127, (_val), (_mask)) 1524 1525 /* Test port out bits 23:8, tpout[23:8] */ 1526 #define READ_XGXS16G_GP_STATUS_TPOUT_2r(_unit, _pc, _val) \ 1527 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008128, (_val)) 1528 #define WRITE_XGXS16G_GP_STATUS_TPOUT_2r(_unit, _pc, _val) \ 1529 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008128, (_val)) 1530 #define MODIFY_XGXS16G_GP_STATUS_TPOUT_2r(_unit, _pc, _val, _mask) \ 1531 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008128, (_val), (_mask)) 1532 1533 /* XGXG status 3 register */ 1534 #define READ_XGXS16G_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \ 1535 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008129, (_val)) 1536 #define WRITE_XGXS16G_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \ 1537 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008129, (_val)) 1538 #define MODIFY_XGXS16G_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val, _mask) \ 1539 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008129, (_val), (_mask)) 1540 1541 /* 2500X status register */ 1542 #define READ_XGXS16G_GP_STATUS_X2500STATUS1r(_unit, _pc, _val) \ 1543 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000812a, (_val)) 1544 #define WRITE_XGXS16G_GP_STATUS_X2500STATUS1r(_unit, _pc, _val) \ 1545 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000812a, (_val)) 1546 #define MODIFY_XGXS16G_GP_STATUS_X2500STATUS1r(_unit, _pc, _val, _mask) \ 1547 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812a, (_val), (_mask)) 1548 1549 /* CL73 AN status 1 register */ 1550 #define READ_XGXS16G_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val) \ 1551 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000812b, (_val)) 1552 #define WRITE_XGXS16G_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val) \ 1553 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000812b, (_val)) 1554 #define MODIFY_XGXS16G_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val, _mask) \ 1555 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812b, (_val), (_mask)) 1556 1557 /* AN link partner user page 1 */ 1558 #define READ_XGXS16G_GP_STATUS_LP_UP1r(_unit, _pc, _val) \ 1559 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000812c, (_val)) 1560 #define WRITE_XGXS16G_GP_STATUS_LP_UP1r(_unit, _pc, _val) \ 1561 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000812c, (_val)) 1562 #define MODIFY_XGXS16G_GP_STATUS_LP_UP1r(_unit, _pc, _val, _mask) \ 1563 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812c, (_val), (_mask)) 1564 1565 /* AN link partner user page 2 */ 1566 #define READ_XGXS16G_GP_STATUS_LP_UP2r(_unit, _pc, _val) \ 1567 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000812d, (_val)) 1568 #define WRITE_XGXS16G_GP_STATUS_LP_UP2r(_unit, _pc, _val) \ 1569 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000812d, (_val)) 1570 #define MODIFY_XGXS16G_GP_STATUS_LP_UP2r(_unit, _pc, _val, _mask) \ 1571 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812d, (_val), (_mask)) 1572 1573 /* AN link partner user page 3 */ 1574 #define READ_XGXS16G_GP_STATUS_LP_UP3r(_unit, _pc, _val) \ 1575 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000812e, (_val)) 1576 #define WRITE_XGXS16G_GP_STATUS_LP_UP3r(_unit, _pc, _val) \ 1577 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000812e, (_val)) 1578 #define MODIFY_XGXS16G_GP_STATUS_LP_UP3r(_unit, _pc, _val, _mask) \ 1579 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812e, (_val), (_mask)) 1580 1581 1582 /**************************************************************************** 1583 * XGXS16G_USER_AN73_pdet 1584 */ 1585 1586 /* 10G parallel detect status register */ 1587 #define READ_XGXS16G_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val) \ 1588 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008130, (_val)) 1589 #define WRITE_XGXS16G_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val) \ 1590 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008130, (_val)) 1591 #define MODIFY_XGXS16G_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val, _mask) \ 1592 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008130, (_val), (_mask)) 1593 1594 /* 10G parallel detect control register */ 1595 #define READ_XGXS16G_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val) \ 1596 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008131, (_val)) 1597 #define WRITE_XGXS16G_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val) \ 1598 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008131, (_val)) 1599 #define MODIFY_XGXS16G_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val, _mask) \ 1600 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008131, (_val), (_mask)) 1601 1602 /* 10G parallel detect signal detect register */ 1603 #define READ_XGXS16G_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val) \ 1604 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008132, (_val)) 1605 #define WRITE_XGXS16G_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val) \ 1606 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008132, (_val)) 1607 #define MODIFY_XGXS16G_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val, _mask) \ 1608 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008132, (_val), (_mask)) 1609 1610 /* 10G parallel detect link register */ 1611 #define READ_XGXS16G_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val) \ 1612 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008133, (_val)) 1613 #define WRITE_XGXS16G_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val) \ 1614 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008133, (_val)) 1615 #define MODIFY_XGXS16G_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val, _mask) \ 1616 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008133, (_val), (_mask)) 1617 1618 /* 10G parallel detect lost link register */ 1619 #define READ_XGXS16G_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val) \ 1620 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008134, (_val)) 1621 #define WRITE_XGXS16G_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val) \ 1622 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008134, (_val)) 1623 #define MODIFY_XGXS16G_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val, _mask) \ 1624 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008134, (_val), (_mask)) 1625 1626 /* Clasue 73 auto-negotiation control register 1 */ 1627 #define READ_XGXS16G_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val) \ 1628 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008135, (_val)) 1629 #define WRITE_XGXS16G_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val) \ 1630 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008135, (_val)) 1631 #define MODIFY_XGXS16G_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val, _mask) \ 1632 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008135, (_val), (_mask)) 1633 1634 /* Clasue 73 auto-negotiation control register 2 */ 1635 #define READ_XGXS16G_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val) \ 1636 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008136, (_val)) 1637 #define WRITE_XGXS16G_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val) \ 1638 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008136, (_val)) 1639 #define MODIFY_XGXS16G_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val, _mask) \ 1640 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008136, (_val), (_mask)) 1641 1642 /* Clasue 73 auto-negotiation control register 3 */ 1643 #define READ_XGXS16G_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val) \ 1644 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008137, (_val)) 1645 #define WRITE_XGXS16G_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val) \ 1646 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008137, (_val)) 1647 #define MODIFY_XGXS16G_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val, _mask) \ 1648 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008137, (_val), (_mask)) 1649 1650 /* Clasue 73 auto-negotiation control register 4 */ 1651 #define READ_XGXS16G_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val) \ 1652 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008138, (_val)) 1653 #define WRITE_XGXS16G_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val) \ 1654 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008138, (_val)) 1655 #define MODIFY_XGXS16G_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val, _mask) \ 1656 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008138, (_val), (_mask)) 1657 1658 1659 /* TX Lane Swap Control 1 Register */ 1660 #define READ_XGXS16G_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _val) \ 1661 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008169, (_val)) 1662 #define WRITE_XGXS16G_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _val) \ 1663 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008169, (_val)) 1664 #define MODIFY_XGXS16G_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _val, _mask) \ 1665 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008169, (_val), (_mask)) 1666 1667 /* RX Lane Swap Control 1 Register */ 1668 #define READ_XGXS16G_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _val) \ 1669 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000816b, (_val)) 1670 #define WRITE_XGXS16G_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _val) \ 1671 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000816b, (_val)) 1672 #define MODIFY_XGXS16G_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _val, _mask) \ 1673 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000816b, (_val), (_mask)) 1674 1675 /**************************************************************************** 1676 * XGXS16G_USER_XgxsBlk7 1677 */ 1678 1679 /* Cl48 PCS EEE Control register */ 1680 #define READ_XGXS16G_XGXSBLK7_EEECONTROLr(_unit, _pc, _val) \ 1681 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008150, (_val)) 1682 #define WRITE_XGXS16G_XGXSBLK7_EEECONTROLr(_unit, _pc, _val) \ 1683 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008150, (_val)) 1684 #define MODIFY_XGXS16G_XGXSBLK7_EEECONTROLr(_unit, _pc, _val, _mask) \ 1685 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008150, (_val), (_mask)) 1686 1687 1688 /**************************************************************************** 1689 * XGXS16G_USER_SerdesDigital 1690 */ 1691 1692 /* 1000X control 1 register */ 1693 #define READ_XGXS16G_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _val) \ 1694 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008300, (_val)) 1695 #define WRITE_XGXS16G_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _val) \ 1696 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008300, (_val)) 1697 #define MODIFY_XGXS16G_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _val, _mask) \ 1698 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008300, (_val), (_mask)) 1699 1700 /* 1000X control 2 register */ 1701 #define READ_XGXS16G_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val) \ 1702 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008301, (_val)) 1703 #define WRITE_XGXS16G_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val) \ 1704 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008301, (_val)) 1705 #define MODIFY_XGXS16G_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val, _mask) \ 1706 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008301, (_val), (_mask)) 1707 1708 /* 1000X control 3 register */ 1709 #define READ_XGXS16G_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _val) \ 1710 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008302, (_val)) 1711 #define WRITE_XGXS16G_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _val) \ 1712 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008302, (_val)) 1713 #define MODIFY_XGXS16G_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _val, _mask) \ 1714 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008302, (_val), (_mask)) 1715 1716 /* 1000X control 4 register */ 1717 #define READ_XGXS16G_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _val) \ 1718 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008303, (_val)) 1719 #define WRITE_XGXS16G_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _val) \ 1720 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008303, (_val)) 1721 #define MODIFY_XGXS16G_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _val, _mask) \ 1722 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008303, (_val), (_mask)) 1723 1724 /* 1000X status 1 register */ 1725 #define READ_XGXS16G_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _val) \ 1726 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008304, (_val)) 1727 #define WRITE_XGXS16G_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _val) \ 1728 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008304, (_val)) 1729 #define MODIFY_XGXS16G_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _val, _mask) \ 1730 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008304, (_val), (_mask)) 1731 1732 /* 1000X status 2 register */ 1733 #define READ_XGXS16G_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _val) \ 1734 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008305, (_val)) 1735 #define WRITE_XGXS16G_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _val) \ 1736 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008305, (_val)) 1737 #define MODIFY_XGXS16G_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _val, _mask) \ 1738 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008305, (_val), (_mask)) 1739 1740 /* 1000X status 3 register */ 1741 #define READ_XGXS16G_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _val) \ 1742 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008306, (_val)) 1743 #define WRITE_XGXS16G_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _val) \ 1744 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008306, (_val)) 1745 #define MODIFY_XGXS16G_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _val, _mask) \ 1746 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008306, (_val), (_mask)) 1747 1748 /* CRC error & Rx byte count register */ 1749 #define READ_XGXS16G_SERDESDIGITAL_CRCERR_RXPKTr(_unit, _pc, _val) \ 1750 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008307, (_val)) 1751 #define WRITE_XGXS16G_SERDESDIGITAL_CRCERR_RXPKTr(_unit, _pc, _val) \ 1752 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008307, (_val)) 1753 #define MODIFY_XGXS16G_SERDESDIGITAL_CRCERR_RXPKTr(_unit, _pc, _val, _mask) \ 1754 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008307, (_val), (_mask)) 1755 1756 /* Miscellaneous 1 control register */ 1757 #define READ_XGXS16G_SERDESDIGITAL_MISC1r(_unit, _pc, _val) \ 1758 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008308, (_val)) 1759 #define WRITE_XGXS16G_SERDESDIGITAL_MISC1r(_unit, _pc, _val) \ 1760 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008308, (_val)) 1761 #define MODIFY_XGXS16G_SERDESDIGITAL_MISC1r(_unit, _pc, _val, _mask) \ 1762 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008308, (_val), (_mask)) 1763 1764 /* Miscellaneous 2 control register */ 1765 #define READ_XGXS16G_SERDESDIGITAL_MISC2r(_unit, _pc, _val) \ 1766 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008309, (_val)) 1767 #define WRITE_XGXS16G_SERDESDIGITAL_MISC2r(_unit, _pc, _val) \ 1768 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008309, (_val)) 1769 #define MODIFY_XGXS16G_SERDESDIGITAL_MISC2r(_unit, _pc, _val, _mask) \ 1770 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008309, (_val), (_mask)) 1771 1772 /* Pattern generator control register */ 1773 #define READ_XGXS16G_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _val) \ 1774 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000830a, (_val)) 1775 #define WRITE_XGXS16G_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _val) \ 1776 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000830a, (_val)) 1777 #define MODIFY_XGXS16G_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _val, _mask) \ 1778 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830a, (_val), (_mask)) 1779 1780 /* Pattern generator status register */ 1781 #define READ_XGXS16G_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _val) \ 1782 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000830b, (_val)) 1783 #define WRITE_XGXS16G_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _val) \ 1784 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000830b, (_val)) 1785 #define MODIFY_XGXS16G_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _val, _mask) \ 1786 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830b, (_val), (_mask)) 1787 1788 /* Test mode register */ 1789 #define READ_XGXS16G_SERDESDIGITAL_TESTMODEr(_unit, _pc, _val) \ 1790 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000830c, (_val)) 1791 #define WRITE_XGXS16G_SERDESDIGITAL_TESTMODEr(_unit, _pc, _val) \ 1792 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000830c, (_val)) 1793 #define MODIFY_XGXS16G_SERDESDIGITAL_TESTMODEr(_unit, _pc, _val, _mask) \ 1794 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830c, (_val), (_mask)) 1795 1796 /* Tx packet count register */ 1797 #define READ_XGXS16G_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _val) \ 1798 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000830d, (_val)) 1799 #define WRITE_XGXS16G_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _val) \ 1800 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000830d, (_val)) 1801 #define MODIFY_XGXS16G_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _val, _mask) \ 1802 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830d, (_val), (_mask)) 1803 1804 /* Rx packet count register */ 1805 #define READ_XGXS16G_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _val) \ 1806 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000830e, (_val)) 1807 #define WRITE_XGXS16G_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _val) \ 1808 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000830e, (_val)) 1809 #define MODIFY_XGXS16G_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _val, _mask) \ 1810 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830e, (_val), (_mask)) 1811 1812 1813 /**************************************************************************** 1814 * XGXS16G_USER_serdesID 1815 */ 1816 1817 /* Serdes ID 0 register */ 1818 #define READ_XGXS16G_SERDESID_SERDESID0r(_unit, _pc, _val) \ 1819 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008310, (_val)) 1820 #define WRITE_XGXS16G_SERDESID_SERDESID0r(_unit, _pc, _val) \ 1821 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008310, (_val)) 1822 #define MODIFY_XGXS16G_SERDESID_SERDESID0r(_unit, _pc, _val, _mask) \ 1823 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008310, (_val), (_mask)) 1824 1825 /* Serdes ID 1 register */ 1826 #define READ_XGXS16G_SERDESID_SERDESID1r(_unit, _pc, _val) \ 1827 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008311, (_val)) 1828 #define WRITE_XGXS16G_SERDESID_SERDESID1r(_unit, _pc, _val) \ 1829 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008311, (_val)) 1830 #define MODIFY_XGXS16G_SERDESID_SERDESID1r(_unit, _pc, _val, _mask) \ 1831 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008311, (_val), (_mask)) 1832 1833 /* Serdes ID 2 register */ 1834 #define READ_XGXS16G_SERDESID_SERDESID2r(_unit, _pc, _val) \ 1835 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008312, (_val)) 1836 #define WRITE_XGXS16G_SERDESID_SERDESID2r(_unit, _pc, _val) \ 1837 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008312, (_val)) 1838 #define MODIFY_XGXS16G_SERDESID_SERDESID2r(_unit, _pc, _val, _mask) \ 1839 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008312, (_val), (_mask)) 1840 1841 /* Serdes ID 3 register */ 1842 #define READ_XGXS16G_SERDESID_SERDESID3r(_unit, _pc, _val) \ 1843 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008313, (_val)) 1844 #define WRITE_XGXS16G_SERDESID_SERDESID3r(_unit, _pc, _val) \ 1845 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008313, (_val)) 1846 #define MODIFY_XGXS16G_SERDESID_SERDESID3r(_unit, _pc, _val, _mask) \ 1847 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008313, (_val), (_mask)) 1848 1849 1850 /**************************************************************************** 1851 * XGXS16G_USER_Over1G 1852 */ 1853 1854 /* AN lost link count time, bits 15:0 */ 1855 #define READ_XGXS16G_OVER1G_DIGCTL_3_0r(_unit, _pc, _val) \ 1856 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008320, (_val)) 1857 #define WRITE_XGXS16G_OVER1G_DIGCTL_3_0r(_unit, _pc, _val) \ 1858 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008320, (_val)) 1859 #define MODIFY_XGXS16G_OVER1G_DIGCTL_3_0r(_unit, _pc, _val, _mask) \ 1860 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008320, (_val), (_mask)) 1861 1862 /* AN switch count time, bits 15:0 */ 1863 #define READ_XGXS16G_OVER1G_DIGCTL_3_1r(_unit, _pc, _val) \ 1864 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008321, (_val)) 1865 #define WRITE_XGXS16G_OVER1G_DIGCTL_3_1r(_unit, _pc, _val) \ 1866 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008321, (_val)) 1867 #define MODIFY_XGXS16G_OVER1G_DIGCTL_3_1r(_unit, _pc, _val, _mask) \ 1868 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008321, (_val), (_mask)) 1869 1870 /* AN link count time, bits 15:0 */ 1871 #define READ_XGXS16G_OVER1G_DIGCTL_3_2r(_unit, _pc, _val) \ 1872 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008322, (_val)) 1873 #define WRITE_XGXS16G_OVER1G_DIGCTL_3_2r(_unit, _pc, _val) \ 1874 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008322, (_val)) 1875 #define MODIFY_XGXS16G_OVER1G_DIGCTL_3_2r(_unit, _pc, _val, _mask) \ 1876 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008322, (_val), (_mask)) 1877 1878 /* AN switch count & link count time, bits 23:16 */ 1879 #define READ_XGXS16G_OVER1G_DIGCTL_3_3r(_unit, _pc, _val) \ 1880 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008323, (_val)) 1881 #define WRITE_XGXS16G_OVER1G_DIGCTL_3_3r(_unit, _pc, _val) \ 1882 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008323, (_val)) 1883 #define MODIFY_XGXS16G_OVER1G_DIGCTL_3_3r(_unit, _pc, _val, _mask) \ 1884 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008323, (_val), (_mask)) 1885 1886 /* Over 1G message page number & AN fail count timer */ 1887 #define READ_XGXS16G_OVER1G_DIGCTL_3_4r(_unit, _pc, _val) \ 1888 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008324, (_val)) 1889 #define WRITE_XGXS16G_OVER1G_DIGCTL_3_4r(_unit, _pc, _val) \ 1890 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008324, (_val)) 1891 #define MODIFY_XGXS16G_OVER1G_DIGCTL_3_4r(_unit, _pc, _val, _mask) \ 1892 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008324, (_val), (_mask)) 1893 1894 /* AN ignore link count time, bits 15:0 */ 1895 #define READ_XGXS16G_OVER1G_DIGCTL_3_5r(_unit, _pc, _val) \ 1896 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008325, (_val)) 1897 #define WRITE_XGXS16G_OVER1G_DIGCTL_3_5r(_unit, _pc, _val) \ 1898 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008325, (_val)) 1899 #define MODIFY_XGXS16G_OVER1G_DIGCTL_3_5r(_unit, _pc, _val, _mask) \ 1900 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008325, (_val), (_mask)) 1901 1902 /* AN lost link count & ignore link count time, bits 23:16 */ 1903 #define READ_XGXS16G_OVER1G_DIGCTL_3_6r(_unit, _pc, _val) \ 1904 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008326, (_val)) 1905 #define WRITE_XGXS16G_OVER1G_DIGCTL_3_6r(_unit, _pc, _val) \ 1906 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008326, (_val)) 1907 #define MODIFY_XGXS16G_OVER1G_DIGCTL_3_6r(_unit, _pc, _val, _mask) \ 1908 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008326, (_val), (_mask)) 1909 1910 /* Test port out bits 15:0, tpout[15:0] */ 1911 #define READ_XGXS16G_OVER1G_TPOUT_1r(_unit, _pc, _val) \ 1912 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008327, (_val)) 1913 #define WRITE_XGXS16G_OVER1G_TPOUT_1r(_unit, _pc, _val) \ 1914 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008327, (_val)) 1915 #define MODIFY_XGXS16G_OVER1G_TPOUT_1r(_unit, _pc, _val, _mask) \ 1916 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008327, (_val), (_mask)) 1917 1918 /* Test port out bits 23:8, tpout[23:8] */ 1919 #define READ_XGXS16G_OVER1G_TPOUT_2r(_unit, _pc, _val) \ 1920 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008328, (_val)) 1921 #define WRITE_XGXS16G_OVER1G_TPOUT_2r(_unit, _pc, _val) \ 1922 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008328, (_val)) 1923 #define MODIFY_XGXS16G_OVER1G_TPOUT_2r(_unit, _pc, _val, _mask) \ 1924 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008328, (_val), (_mask)) 1925 1926 /* AN local device user page 1 */ 1927 #define READ_XGXS16G_OVER1G_UP1r(_unit, _pc, _val) \ 1928 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008329, (_val)) 1929 #define WRITE_XGXS16G_OVER1G_UP1r(_unit, _pc, _val) \ 1930 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008329, (_val)) 1931 #define MODIFY_XGXS16G_OVER1G_UP1r(_unit, _pc, _val, _mask) \ 1932 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008329, (_val), (_mask)) 1933 1934 /* AN local device user page 2 */ 1935 #define READ_XGXS16G_OVER1G_UP2r(_unit, _pc, _val) \ 1936 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000832a, (_val)) 1937 #define WRITE_XGXS16G_OVER1G_UP2r(_unit, _pc, _val) \ 1938 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000832a, (_val)) 1939 #define MODIFY_XGXS16G_OVER1G_UP2r(_unit, _pc, _val, _mask) \ 1940 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832a, (_val), (_mask)) 1941 1942 /* AN local device user page 3 */ 1943 #define READ_XGXS16G_OVER1G_UP3r(_unit, _pc, _val) \ 1944 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000832b, (_val)) 1945 #define WRITE_XGXS16G_OVER1G_UP3r(_unit, _pc, _val) \ 1946 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000832b, (_val)) 1947 #define MODIFY_XGXS16G_OVER1G_UP3r(_unit, _pc, _val, _mask) \ 1948 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832b, (_val), (_mask)) 1949 1950 /* AN link partner user page 1 */ 1951 #define READ_XGXS16G_OVER1G_LP_UP1r(_unit, _pc, _val) \ 1952 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000832c, (_val)) 1953 #define WRITE_XGXS16G_OVER1G_LP_UP1r(_unit, _pc, _val) \ 1954 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000832c, (_val)) 1955 #define MODIFY_XGXS16G_OVER1G_LP_UP1r(_unit, _pc, _val, _mask) \ 1956 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832c, (_val), (_mask)) 1957 1958 /* AN link partner user page 2 */ 1959 #define READ_XGXS16G_OVER1G_LP_UP2r(_unit, _pc, _val) \ 1960 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000832d, (_val)) 1961 #define WRITE_XGXS16G_OVER1G_LP_UP2r(_unit, _pc, _val) \ 1962 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000832d, (_val)) 1963 #define MODIFY_XGXS16G_OVER1G_LP_UP2r(_unit, _pc, _val, _mask) \ 1964 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832d, (_val), (_mask)) 1965 1966 /* AN link partner user page 3 */ 1967 #define READ_XGXS16G_OVER1G_LP_UP3r(_unit, _pc, _val) \ 1968 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000832e, (_val)) 1969 #define WRITE_XGXS16G_OVER1G_LP_UP3r(_unit, _pc, _val) \ 1970 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000832e, (_val)) 1971 1972 #define MODIFY_XGXS16G_OVER1G_LP_UP3r(_unit, _pc, _val, _mask) \ 1973 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832e, (_val), (_mask)) 1974 1975 1976 /**************************************************************************** 1977 * XGXS16G_USER_RemotePhy 1978 */ 1979 1980 /* Miscelaneous Rx status register */ 1981 #define READ_XGXS16G_REMOTEPHY_MISCRXSTATUSr(_unit, _pc, _val) \ 1982 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008330, (_val)) 1983 #define WRITE_XGXS16G_REMOTEPHY_MISCRXSTATUSr(_unit, _pc, _val) \ 1984 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008330, (_val)) 1985 #define MODIFY_XGXS16G_REMOTEPHY_MISCRXSTATUSr(_unit, _pc, _val, _mask) \ 1986 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008330, (_val), (_mask)) 1987 1988 1989 /* Link partner basepage register */ 1990 #define READ_XGXS16G_REMOTEPHY_LP_BASEPAGEr(_unit, _pc, _val) \ 1991 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008331, (_val)) 1992 #define WRITE_XGXS16G_REMOTEPHY_LP_BASEPAGEr(_unit, _pc, _val) \ 1993 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008331, (_val)) 1994 #define MODIFY_XGXS16G_REMOTEPHY_LP_BASEPAGEr(_unit, _pc, _val, _mask) \ 1995 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008331, (_val), (_mask)) 1996 1997 /* Link partner nextpage 0 register */ 1998 #define READ_XGXS16G_REMOTEPHY_LP_NEXTPAGE_0r(_unit, _pc, _val) \ 1999 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008332, (_val)) 2000 #define WRITE_XGXS16G_REMOTEPHY_LP_NEXTPAGE_0r(_unit, _pc, _val) \ 2001 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008332, (_val)) 2002 #define MODIFY_XGXS16G_REMOTEPHY_LP_NEXTPAGE_0r(_unit, _pc, _val, _mask) \ 2003 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008332, (_val), (_mask)) 2004 2005 /* Link partner nextpage 1 register */ 2006 #define READ_XGXS16G_REMOTEPHY_LP_NEXTPAGE_1r(_unit, _pc, _val) \ 2007 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008333, (_val)) 2008 #define WRITE_XGXS16G_REMOTEPHY_LP_NEXTPAGE_1r(_unit, _pc, _val) \ 2009 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008333, (_val)) 2010 #define MODIFY_XGXS16G_REMOTEPHY_LP_NEXTPAGE_1r(_unit, _pc, _val, _mask) \ 2011 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008333, (_val), (_mask)) 2012 2013 /* Link partner nextpage 2 register */ 2014 #define READ_XGXS16G_REMOTEPHY_LP_NEXTPAGE_2r(_unit, _pc, _val) \ 2015 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008334, (_val)) 2016 #define WRITE_XGXS16G_REMOTEPHY_LP_NEXTPAGE_2r(_unit, _pc, _val) \ 2017 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008334, (_val)) 2018 #define MODIFY_XGXS16G_REMOTEPHY_LP_NEXTPAGE_2r(_unit, _pc, _val, _mask) \ 2019 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008334, (_val), (_mask)) 2020 2021 /* Link partner nextpage 3 register */ 2022 #define READ_XGXS16G_REMOTEPHY_LP_NEXTPAGE_3r(_unit, _pc, _val) \ 2023 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008335, (_val)) 2024 #define WRITE_XGXS16G_REMOTEPHY_LP_NEXTPAGE_3r(_unit, _pc, _val) \ 2025 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008335, (_val)) 2026 #define MODIFY_XGXS16G_REMOTEPHY_LP_NEXTPAGE_3r(_unit, _pc, _val, _mask) \ 2027 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008335, (_val), (_mask)) 2028 2029 /* Link partner nextpage 4 register */ 2030 #define READ_XGXS16G_REMOTEPHY_LP_NEXTPAGE_4r(_unit, _pc, _val) \ 2031 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008336, (_val)) 2032 #define WRITE_XGXS16G_REMOTEPHY_LP_NEXTPAGE_4r(_unit, _pc, _val) \ 2033 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008336, (_val)) 2034 #define MODIFY_XGXS16G_REMOTEPHY_LP_NEXTPAGE_4r(_unit, _pc, _val, _mask) \ 2035 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008336, (_val), (_mask)) 2036 2037 /* Remote phy nextpage 0 register */ 2038 #define READ_XGXS16G_REMOTEPHY_RP_NEXTPAGE_0r(_unit, _pc, _val) \ 2039 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008337, (_val)) 2040 #define WRITE_XGXS16G_REMOTEPHY_RP_NEXTPAGE_0r(_unit, _pc, _val) \ 2041 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008337, (_val)) 2042 #define MODIFY_XGXS16G_REMOTEPHY_RP_NEXTPAGE_0r(_unit, _pc, _val, _mask) \ 2043 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008337, (_val), (_mask)) 2044 2045 /* Remote phy nextpage 1 register */ 2046 #define READ_XGXS16G_REMOTEPHY_RP_NEXTPAGE_1r(_unit, _pc, _val) \ 2047 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008338, (_val)) 2048 #define WRITE_XGXS16G_REMOTEPHY_RP_NEXTPAGE_1r(_unit, _pc, _val) \ 2049 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008338, (_val)) 2050 #define MODIFY_XGXS16G_REMOTEPHY_RP_NEXTPAGE_1r(_unit, _pc, _val, _mask) \ 2051 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008338, (_val), (_mask)) 2052 2053 /* Remote phy nextpage 2 register */ 2054 #define READ_XGXS16G_REMOTEPHY_RP_NEXTPAGE_2r(_unit, _pc, _val) \ 2055 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008339, (_val)) 2056 #define WRITE_XGXS16G_REMOTEPHY_RP_NEXTPAGE_2r(_unit, _pc, _val) \ 2057 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008339, (_val)) 2058 #define MODIFY_XGXS16G_REMOTEPHY_RP_NEXTPAGE_2r(_unit, _pc, _val, _mask) \ 2059 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008339, (_val), (_mask)) 2060 2061 /* Remote phy nextpage 3 register */ 2062 #define READ_XGXS16G_REMOTEPHY_RP_NEXTPAGE_3r(_unit, _pc, _val) \ 2063 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000833a, (_val)) 2064 #define WRITE_XGXS16G_REMOTEPHY_RP_NEXTPAGE_3r(_unit, _pc, _val) \ 2065 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000833a, (_val)) 2066 #define MODIFY_XGXS16G_REMOTEPHY_RP_NEXTPAGE_3r(_unit, _pc, _val, _mask) \ 2067 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833a, (_val), (_mask)) 2068 2069 /* Remote phy nextpage 4 register */ 2070 #define READ_XGXS16G_REMOTEPHY_RP_NEXTPAGE_4r(_unit, _pc, _val) \ 2071 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000833b, (_val)) 2072 #define WRITE_XGXS16G_REMOTEPHY_RP_NEXTPAGE_4r(_unit, _pc, _val) \ 2073 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000833b, (_val)) 2074 #define MODIFY_XGXS16G_REMOTEPHY_RP_NEXTPAGE_4r(_unit, _pc, _val, _mask) \ 2075 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833b, (_val), (_mask)) 2076 2077 /* Miscelaneous 3 control register */ 2078 #define READ_XGXS16G_REMOTEPHY_MISC3r(_unit, _pc, _val) \ 2079 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000833c, (_val)) 2080 #define WRITE_XGXS16G_REMOTEPHY_MISC3r(_unit, _pc, _val) \ 2081 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000833c, (_val)) 2082 #define MODIFY_XGXS16G_REMOTEPHY_MISC3r(_unit, _pc, _val, _mask) \ 2083 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833c, (_val), (_mask)) 2084 2085 /* Miscelaneous 5 control register */ 2086 #define READ_XGXS16G_REMOTEPHY_MISC5r(_unit, _pc, _val) \ 2087 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000833e, (_val)) 2088 #define WRITE_XGXS16G_REMOTEPHY_MISC5r(_unit, _pc, _val) \ 2089 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000833e, (_val)) 2090 #define MODIFY_XGXS16G_REMOTEPHY_MISC5r(_unit, _pc, _val, _mask) \ 2091 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833e, (_val), (_mask)) 2092 2093 2094 /**************************************************************************** 2095 * XGXS16G_USER_BAM_NextPage 2096 */ 2097 2098 /* MP5, Message Page 5, next page control register */ 2099 #define READ_XGXS16G_BAM_NEXTPAGE_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \ 2100 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008350, (_val)) 2101 #define WRITE_XGXS16G_BAM_NEXTPAGE_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \ 2102 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008350, (_val)) 2103 #define MODIFY_XGXS16G_BAM_NEXTPAGE_MP5_NEXTPAGECTRLr(_unit, _pc, _val, _mask) \ 2104 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008350, (_val), (_mask)) 2105 2106 /* sgmii & max timer offsets */ 2107 #define READ_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET1r(_unit, _pc, _val) \ 2108 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008351, (_val)) 2109 #define WRITE_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET1r(_unit, _pc, _val) \ 2110 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008351, (_val)) 2111 #define MODIFY_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET1r(_unit, _pc, _val, _mask) \ 2112 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008351, (_val), (_mask)) 2113 2114 /* link up & link down timer offsets */ 2115 #define READ_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET2r(_unit, _pc, _val) \ 2116 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008352, (_val)) 2117 #define WRITE_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET2r(_unit, _pc, _val) \ 2118 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008352, (_val)) 2119 #define MODIFY_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET2r(_unit, _pc, _val, _mask) \ 2120 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008352, (_val), (_mask)) 2121 2122 /* break link & next page link timer offsets */ 2123 #define READ_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET3r(_unit, _pc, _val) \ 2124 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008353, (_val)) 2125 #define WRITE_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET3r(_unit, _pc, _val) \ 2126 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008353, (_val)) 2127 #define MODIFY_XGXS16G_BAM_NEXTPAGE_LINK_TIMER_OFFSET3r(_unit, _pc, _val, _mask) \ 2128 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008353, (_val), (_mask)) 2129 2130 /* 11 MSbits of the oui, oui[23:13] */ 2131 #define READ_XGXS16G_BAM_NEXTPAGE_OUI_MSB_FIELDr(_unit, _pc, _val) \ 2132 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008354, (_val)) 2133 #define WRITE_XGXS16G_BAM_NEXTPAGE_OUI_MSB_FIELDr(_unit, _pc, _val) \ 2134 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008354, (_val)) 2135 #define MODIFY_XGXS16G_BAM_NEXTPAGE_OUI_MSB_FIELDr(_unit, _pc, _val, _mask) \ 2136 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008354, (_val), (_mask)) 2137 2138 /* 11 middle bits of the oui, oui[12:2] */ 2139 #define READ_XGXS16G_BAM_NEXTPAGE_OUI_LSB_FIELDr(_unit, _pc, _val) \ 2140 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008355, (_val)) 2141 #define WRITE_XGXS16G_BAM_NEXTPAGE_OUI_LSB_FIELDr(_unit, _pc, _val) \ 2142 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008355, (_val)) 2143 #define MODIFY_XGXS16G_BAM_NEXTPAGE_OUI_LSB_FIELDr(_unit, _pc, _val, _mask) \ 2144 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008355, (_val), (_mask)) 2145 2146 /* 2 LSbits of the oui, oui[1:0] */ 2147 #define READ_XGXS16G_BAM_NEXTPAGE_BAM_FIELDr(_unit, _pc, _val) \ 2148 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008356, (_val)) 2149 #define WRITE_XGXS16G_BAM_NEXTPAGE_BAM_FIELDr(_unit, _pc, _val) \ 2150 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008356, (_val)) 2151 #define MODIFY_XGXS16G_BAM_NEXTPAGE_BAM_FIELDr(_unit, _pc, _val, _mask) \ 2152 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008356, (_val), (_mask)) 2153 2154 /* User defined field of MP5 */ 2155 #define READ_XGXS16G_BAM_NEXTPAGE_UD_FIELDr(_unit, _pc, _val) \ 2156 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008357, (_val)) 2157 #define WRITE_XGXS16G_BAM_NEXTPAGE_UD_FIELDr(_unit, _pc, _val) \ 2158 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008357, (_val)) 2159 #define MODIFY_XGXS16G_BAM_NEXTPAGE_UD_FIELDr(_unit, _pc, _val, _mask) \ 2160 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008357, (_val), (_mask)) 2161 2162 /* Link partner's 11 MSbits of the oui, oui[23:13] */ 2163 #define READ_XGXS16G_BAM_NEXTPAGE_LP_OUI_MSB_FIELDr(_unit, _pc, _val) \ 2164 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008358, (_val)) 2165 #define WRITE_XGXS16G_BAM_NEXTPAGE_LP_OUI_MSB_FIELDr(_unit, _pc, _val) \ 2166 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008358, (_val)) 2167 #define MODIFY_XGXS16G_BAM_NEXTPAGE_LP_OUI_MSB_FIELDr(_unit, _pc, _val, _mask) \ 2168 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008358, (_val), (_mask)) 2169 2170 /* Link partner's 11 middle bits of the oui, oui[12:2] */ 2171 #define READ_XGXS16G_BAM_NEXTPAGE_LP_OUI_LSB_FIELDr(_unit, _pc, _val) \ 2172 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008359, (_val)) 2173 #define WRITE_XGXS16G_BAM_NEXTPAGE_LP_OUI_LSB_FIELDr(_unit, _pc, _val) \ 2174 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008359, (_val)) 2175 #define MODIFY_XGXS16G_BAM_NEXTPAGE_LP_OUI_LSB_FIELDr(_unit, _pc, _val, _mask) \ 2176 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008359, (_val), (_mask)) 2177 2178 /* Link partner's 2 LSbits of the oui, oui[1:0] */ 2179 #define READ_XGXS16G_BAM_NEXTPAGE_LP_BAM_FIELDr(_unit, _pc, _val) \ 2180 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000835a, (_val)) 2181 #define WRITE_XGXS16G_BAM_NEXTPAGE_LP_BAM_FIELDr(_unit, _pc, _val) \ 2182 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000835a, (_val)) 2183 #define MODIFY_XGXS16G_BAM_NEXTPAGE_LP_BAM_FIELDr(_unit, _pc, _val, _mask) \ 2184 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835a, (_val), (_mask)) 2185 2186 /* Link partner's User defined field of MP5 */ 2187 #define READ_XGXS16G_BAM_NEXTPAGE_LP_UD_FIELDr(_unit, _pc, _val) \ 2188 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000835b, (_val)) 2189 #define WRITE_XGXS16G_BAM_NEXTPAGE_LP_UD_FIELDr(_unit, _pc, _val) \ 2190 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000835b, (_val)) 2191 #define MODIFY_XGXS16G_BAM_NEXTPAGE_LP_UD_FIELDr(_unit, _pc, _val, _mask) \ 2192 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835b, (_val), (_mask)) 2193 2194 2195 /**************************************************************************** 2196 * XGXS16G_USER_CL73_UserB0 2197 */ 2198 2199 /* Clause 73 user control */ 2200 #define READ_XGXS16G_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val) \ 2201 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008370, (_val)) 2202 #define WRITE_XGXS16G_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val) \ 2203 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008370, (_val)) 2204 #define MODIFY_XGXS16G_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val, _mask) \ 2205 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008370, (_val), (_mask)) 2206 2207 /* Clause 73 user status */ 2208 #define READ_XGXS16G_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val) \ 2209 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008371, (_val)) 2210 #define WRITE_XGXS16G_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val) \ 2211 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008371, (_val)) 2212 #define MODIFY_XGXS16G_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val, _mask) \ 2213 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008371, (_val), (_mask)) 2214 2215 /* Clause 73 BAM control 1 */ 2216 #define READ_XGXS16G_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val) \ 2217 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008372, (_val)) 2218 #define WRITE_XGXS16G_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val) \ 2219 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008372, (_val)) 2220 #define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val, _mask) \ 2221 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008372, (_val), (_mask)) 2222 2223 /* Clause 73 BAM control 2 */ 2224 #define READ_XGXS16G_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val) \ 2225 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008373, (_val)) 2226 #define WRITE_XGXS16G_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val) \ 2227 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008373, (_val)) 2228 #define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val, _mask) \ 2229 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008373, (_val), (_mask)) 2230 2231 /* Clause 73 BAM control 3 */ 2232 #define READ_XGXS16G_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val) \ 2233 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008374, (_val)) 2234 #define WRITE_XGXS16G_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val) \ 2235 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008374, (_val)) 2236 #define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val, _mask) \ 2237 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008374, (_val), (_mask)) 2238 2239 /* Clause 73 BAM status 1 */ 2240 #define READ_XGXS16G_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val) \ 2241 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008375, (_val)) 2242 #define WRITE_XGXS16G_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val) \ 2243 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008375, (_val)) 2244 #define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val, _mask) \ 2245 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008375, (_val), (_mask)) 2246 2247 /* Clause 73 BAM status 2 */ 2248 #define READ_XGXS16G_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val) \ 2249 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008376, (_val)) 2250 #define WRITE_XGXS16G_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val) \ 2251 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008376, (_val)) 2252 #define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val, _mask) \ 2253 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008376, (_val), (_mask)) 2254 2255 /* Clause 73 BAM status 3 */ 2256 #define READ_XGXS16G_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val) \ 2257 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008377, (_val)) 2258 #define WRITE_XGXS16G_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val) \ 2259 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008377, (_val)) 2260 #define MODIFY_XGXS16G_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val, _mask) \ 2261 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008377, (_val), (_mask)) 2262 2263 /**************************************************************************** 2264 * Hypercore_USER_FX100 2265 */ 2266 2267 /* 100FX control register 1 */ 2268 #define READ_XGXS16G_FX100_CONTROL1r(_unit, _pc, _val) \ 2269 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008400, (_val)) 2270 #define WRITE_XGXS16G_FX100_CONTROL1r(_unit, _pc, _val) \ 2271 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008400, (_val)) 2272 #define MODIFY_XGXS16G_FX100_CONTROL1r(_unit, _pc, _val, _mask) \ 2273 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008400, (_val), (_mask)) 2274 2275 /* 100FX control register 2 */ 2276 #define READ_XGXS16G_FX100_CONTROL2r(_unit, _pc, _val) \ 2277 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008401, (_val)) 2278 #define WRITE_XGXS16G_FX100_CONTROL2r(_unit, _pc, _val) \ 2279 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008401, (_val)) 2280 #define MODIFY_XGXS16G_FX100_CONTROL2r(_unit, _pc, _val, _mask) \ 2281 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008401, (_val), (_mask)) 2282 2283 /* 100FX control register 3 */ 2284 #define READ_XGXS16G_FX100_CONTROL3r(_unit, _pc, _val) \ 2285 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008402, (_val)) 2286 #define WRITE_XGXS16G_FX100_CONTROL3r(_unit, _pc, _val) \ 2287 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008402, (_val)) 2288 #define MODIFY_XGXS16G_FX100_CONTROL3r(_unit, _pc, _val, _mask) \ 2289 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008402, (_val), (_mask)) 2290 2291 /* 100FX status register 1 */ 2292 #define READ_XGXS16G_FX100_STATUS1r(_unit, _pc, _val) \ 2293 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008403, (_val)) 2294 #define WRITE_XGXS16G_FX100_STATUS1r(_unit, _pc, _val) \ 2295 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008403, (_val)) 2296 #define MODIFY_XGXS16G_FX100_STATUS1r(_unit, _pc, _val, _mask) \ 2297 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008403, (_val), (_mask)) 2298 2299 /* 100FX status register 3 */ 2300 #define READ_XGXS16G_FX100_STATUS3r(_unit, _pc, _val) \ 2301 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008405, (_val)) 2302 #define WRITE_XGXS16G_FX100_STATUS3r(_unit, _pc, _val) \ 2303 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008405, (_val)) 2304 #define MODIFY_XGXS16G_FX100_STATUS3r(_unit, _pc, _val, _mask) \ 2305 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008405, (_val), (_mask)) 2306 2307 /* 100FX status register 4 */ 2308 #define READ_XGXS16G_FX100_STATUS4r(_unit, _pc, _val) \ 2309 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008406, (_val)) 2310 #define WRITE_XGXS16G_FX100_STATUS4r(_unit, _pc, _val) \ 2311 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008406, (_val)) 2312 #define MODIFY_XGXS16G_FX100_STATUS4r(_unit, _pc, _val, _mask) \ 2313 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008406, (_val), (_mask)) 2314 2315 /**************************************************************************** 2316 * XGXS16G_USER_aerBlk 2317 */ 2318 2319 /* Address Expansion Register */ 2320 #define READ_XGXS16G_AERBLK_AERr(_unit, _pc, _val) \ 2321 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffde, (_val)) 2322 #define WRITE_XGXS16G_AERBLK_AERr(_unit, _pc, _val) \ 2323 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffde, (_val)) 2324 #define MODIFY_XGXS16G_AERBLK_AERr(_unit, _pc, _val, _mask) \ 2325 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffde, (_val), (_mask)) 2326 2327 2328 /**************************************************************************** 2329 * XGXS16G_USER_Combo_IEEE0 2330 */ 2331 2332 /* IEEE MII control register */ 2333 #define READ_XGXS16G_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \ 2334 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe0, (_val)) 2335 #define WRITE_XGXS16G_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \ 2336 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe0, (_val)) 2337 #define MODIFY_XGXS16G_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val, _mask) \ 2338 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe0, (_val), (_mask)) 2339 2340 /* IEEE MII status register */ 2341 #define READ_XGXS16G_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \ 2342 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe1, (_val)) 2343 #define WRITE_XGXS16G_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \ 2344 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe1, (_val)) 2345 #define MODIFY_XGXS16G_COMBO_IEEE0_MIISTATr(_unit, _pc, _val, _mask) \ 2346 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe1, (_val), (_mask)) 2347 2348 /* IEEE phy ID LSByte register */ 2349 #define READ_XGXS16G_COMBO_IEEE0_ID1r(_unit, _pc, _val) \ 2350 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe2, (_val)) 2351 #define WRITE_XGXS16G_COMBO_IEEE0_ID1r(_unit, _pc, _val) \ 2352 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe2, (_val)) 2353 #define MODIFY_XGXS16G_COMBO_IEEE0_ID1r(_unit, _pc, _val, _mask) \ 2354 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe2, (_val), (_mask)) 2355 2356 /* IEEE phy ID MSByte register */ 2357 #define READ_XGXS16G_COMBO_IEEE0_ID2r(_unit, _pc, _val) \ 2358 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe3, (_val)) 2359 #define WRITE_XGXS16G_COMBO_IEEE0_ID2r(_unit, _pc, _val) \ 2360 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe3, (_val)) 2361 #define MODIFY_XGXS16G_COMBO_IEEE0_ID2r(_unit, _pc, _val, _mask) \ 2362 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe3, (_val), (_mask)) 2363 2364 /* IEEE auto-negotiation advertiesed abilities register */ 2365 #define READ_XGXS16G_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \ 2366 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe4, (_val)) 2367 #define WRITE_XGXS16G_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \ 2368 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe4, (_val)) 2369 #define MODIFY_XGXS16G_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val, _mask) \ 2370 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe4, (_val), (_mask)) 2371 2372 /* IEEE auto-negotiation link partner abilities register */ 2373 #define READ_XGXS16G_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \ 2374 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe5, (_val)) 2375 #define WRITE_XGXS16G_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \ 2376 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe5, (_val)) 2377 #define MODIFY_XGXS16G_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val, _mask) \ 2378 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe5, (_val), (_mask)) 2379 2380 /* IEEE auto-negotiation expansion register */ 2381 #define READ_XGXS16G_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \ 2382 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe6, (_val)) 2383 #define WRITE_XGXS16G_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \ 2384 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe6, (_val)) 2385 #define MODIFY_XGXS16G_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val, _mask) \ 2386 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe6, (_val), (_mask)) 2387 2388 /* IEEE auto-negotiation next page register */ 2389 #define READ_XGXS16G_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val) \ 2390 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe7, (_val)) 2391 #define WRITE_XGXS16G_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val) \ 2392 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe7, (_val)) 2393 #define MODIFY_XGXS16G_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val, _mask) \ 2394 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe7, (_val), (_mask)) 2395 2396 /* IEEE auto-negotiation link partner next page register */ 2397 #define READ_XGXS16G_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val) \ 2398 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffe8, (_val)) 2399 #define WRITE_XGXS16G_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val) \ 2400 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe8, (_val)) 2401 #define MODIFY_XGXS16G_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val, _mask) \ 2402 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe8, (_val), (_mask)) 2403 2404 /* IEEE MII extended status register */ 2405 #define READ_XGXS16G_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val) \ 2406 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x0000ffef, (_val)) 2407 #define WRITE_XGXS16G_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val) \ 2408 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffef, (_val)) 2409 #define MODIFY_XGXS16G_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val, _mask) \ 2410 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffef, (_val), (_mask)) 2411 2412 /**************************************************************************** 2413 * Analog parameters for the 40nm XGXS13G core 2414 */ 2415 2416 #define READ_XGXS13G_040_TX0_ACONTROL1r(_unit, _pc, _val) \ 2417 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008065, (_val)) 2418 #define WRITE_XGXS13G_040_TX0_ACONTROL1r(_unit, _pc, _val) \ 2419 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008065, (_val)) 2420 #define MODIFY_XGXS13G_040_TX0_ACONTROL1r(_unit, _pc, _val, _mask) \ 2421 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008065, (_val), (_mask)) 2422 #define READ_XGXS13G_040_TX1_ACONTROL1r(_unit, _pc, _val) \ 2423 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008075, (_val)) 2424 #define WRITE_XGXS13G_040_TX1_ACONTROL1r(_unit, _pc, _val) \ 2425 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008075, (_val)) 2426 #define MODIFY_XGXS13G_040_TX1_ACONTROL1r(_unit, _pc, _val, _mask) \ 2427 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008075, (_val), (_mask)) 2428 #define READ_XGXS13G_040_TX2_ACONTROL1r(_unit, _pc, _val) \ 2429 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008085, (_val)) 2430 #define WRITE_XGXS13G_040_TX2_ACONTROL1r(_unit, _pc, _val) \ 2431 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008085, (_val)) 2432 #define MODIFY_XGXS13G_040_TX2_ACONTROL1r(_unit, _pc, _val, _mask) \ 2433 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008085, (_val), (_mask)) 2434 #define READ_XGXS13G_040_TX3_ACONTROL1r(_unit, _pc, _val) \ 2435 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x00008095, (_val)) 2436 #define WRITE_XGXS13G_040_TX3_ACONTROL1r(_unit, _pc, _val) \ 2437 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x00008095, (_val)) 2438 #define MODIFY_XGXS13G_040_TX3_ACONTROL1r(_unit, _pc, _val, _mask) \ 2439 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x00008095, (_val), (_mask)) 2440 #define READ_XGXS13G_040_TX_ALL_ACONTROL1r(_unit, _pc, _val) \ 2441 XGXS16G_REG_READ((_unit), (_pc), 0x00, 0x000080a5, (_val)) 2442 #define WRITE_XGXS13G_040_TX_ALL_ACONTROL1r(_unit, _pc, _val) \ 2443 XGXS16G_REG_WRITE((_unit), (_pc), 0x00, 0x000080a5, (_val)) 2444 #define MODIFY_XGXS13G_040_TX_ALL_ACONTROL1r(_unit, _pc, _val, _mask) \ 2445 XGXS16G_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a5, (_val), (_mask)) 2446 #define TX0_040_TX_DRIVER_PREEMPHASIS_POST_MASK 0x7800 2447 #define TX0_040_TX_DRIVER_PREEMPHASIS_POST_ALIGN 0 2448 #define TX0_040_TX_DRIVER_PREEMPHASIS_POST_BITS 4 2449 #define TX0_040_TX_DRIVER_PREEMPHASIS_POST_SHIFT 11 2450 #define TX0_040_TX_DRIVER_IDRIVER_MASK 0x0700 2451 #define TX0_040_TX_DRIVER_IDRIVER_ALIGN 0 2452 #define TX0_040_TX_DRIVER_IDRIVER_BITS 3 2453 #define TX0_040_TX_DRIVER_IDRIVER_SHIFT 8 2454 #define TX1_040_TX_DRIVER_PREEMPHASIS_POST_MASK 0x7800 2455 #define TX1_040_TX_DRIVER_PREEMPHASIS_POST_ALIGN 0 2456 #define TX1_040_TX_DRIVER_PREEMPHASIS_POST_BITS 4 2457 #define TX1_040_TX_DRIVER_PREEMPHASIS_POST_SHIFT 11 2458 #define TX1_040_TX_DRIVER_IDRIVER_MASK 0x0700 2459 #define TX1_040_TX_DRIVER_IDRIVER_ALIGN 0 2460 #define TX1_040_TX_DRIVER_IDRIVER_BITS 3 2461 #define TX1_040_TX_DRIVER_IDRIVER_SHIFT 8 2462 #define TX2_040_TX_DRIVER_PREEMPHASIS_POST_MASK 0x7800 2463 #define TX2_040_TX_DRIVER_PREEMPHASIS_POST_ALIGN 0 2464 #define TX2_040_TX_DRIVER_PREEMPHASIS_POST_BITS 4 2465 #define TX2_040_TX_DRIVER_PREEMPHASIS_POST_SHIFT 11 2466 #define TX2_040_TX_DRIVER_IDRIVER_MASK 0x0700 2467 #define TX2_040_TX_DRIVER_IDRIVER_ALIGN 0 2468 #define TX2_040_TX_DRIVER_IDRIVER_BITS 3 2469 #define TX2_040_TX_DRIVER_IDRIVER_SHIFT 8 2470 #define TX3_040_TX_DRIVER_PREEMPHASIS_POST_MASK 0x7800 2471 #define TX3_040_TX_DRIVER_PREEMPHASIS_POST_ALIGN 0 2472 #define TX3_040_TX_DRIVER_PREEMPHASIS_POST_BITS 4 2473 #define TX3_040_TX_DRIVER_PREEMPHASIS_POST_SHIFT 11 2474 #define TX3_040_TX_DRIVER_IDRIVER_MASK 0x0700 2475 #define TX3_040_TX_DRIVER_IDRIVER_ALIGN 0 2476 #define TX3_040_TX_DRIVER_IDRIVER_BITS 3 2477 #define TX3_040_TX_DRIVER_IDRIVER_SHIFT 8 2478 #define TX_ALL_040_TX_DRIVER_PREEMPHASIS_POST_MASK 0x7800 2479 #define TX_ALL_040_TX_DRIVER_PREEMPHASIS_POST_ALIGN 0 2480 #define TX_ALL_040_TX_DRIVER_PREEMPHASIS_POST_BITS 4 2481 #define TX_ALL_040_TX_DRIVER_PREEMPHASIS_POST_SHIFT 11 2482 #define TX_ALL_040_TX_DRIVER_IDRIVER_MASK 0x0700 2483 #define TX_ALL_040_TX_DRIVER_IDRIVER_ALIGN 0 2484 #define TX_ALL_040_TX_DRIVER_IDRIVER_BITS 3 2485 #define TX_ALL_040_TX_DRIVER_IDRIVER_SHIFT 8 2486 2487 2488 2489 2490 /**************************************************************************** 2491 * XGXS16G_IEEE_ieee0Blk 2492 */ 2493 /**************************************************************************** 2494 * ieee0Blk :: ieeeControl0 2495 */ 2496 /* ieee0Blk :: ieeeControl0 :: rst_hw [15:15] */ 2497 #define IEEE0BLK_IEEECONTROL0_RST_HW_MASK 0x8000 2498 #define IEEE0BLK_IEEECONTROL0_RST_HW_ALIGN 0 2499 #define IEEE0BLK_IEEECONTROL0_RST_HW_BITS 1 2500 #define IEEE0BLK_IEEECONTROL0_RST_HW_SHIFT 15 2501 2502 /* ieee0Blk :: ieeeControl0 :: gloopback [14:14] */ 2503 #define IEEE0BLK_IEEECONTROL0_GLOOPBACK_MASK 0x4000 2504 #define IEEE0BLK_IEEECONTROL0_GLOOPBACK_ALIGN 0 2505 #define IEEE0BLK_IEEECONTROL0_GLOOPBACK_BITS 1 2506 #define IEEE0BLK_IEEECONTROL0_GLOOPBACK_SHIFT 14 2507 2508 /* ieee0Blk :: ieeeControl0 :: manual_speed0 [13:13] */ 2509 #define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED0_MASK 0x2000 2510 #define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED0_ALIGN 0 2511 #define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED0_BITS 1 2512 #define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED0_SHIFT 13 2513 2514 /* ieee0Blk :: ieeeControl0 :: autoneg_enable [12:12] */ 2515 #define IEEE0BLK_IEEECONTROL0_AUTONEG_ENABLE_MASK 0x1000 2516 #define IEEE0BLK_IEEECONTROL0_AUTONEG_ENABLE_ALIGN 0 2517 #define IEEE0BLK_IEEECONTROL0_AUTONEG_ENABLE_BITS 1 2518 #define IEEE0BLK_IEEECONTROL0_AUTONEG_ENABLE_SHIFT 12 2519 2520 /* ieee0Blk :: ieeeControl0 :: pwrdwn_sw [11:11] */ 2521 #define IEEE0BLK_IEEECONTROL0_PWRDWN_SW_MASK 0x0800 2522 #define IEEE0BLK_IEEECONTROL0_PWRDWN_SW_ALIGN 0 2523 #define IEEE0BLK_IEEECONTROL0_PWRDWN_SW_BITS 1 2524 #define IEEE0BLK_IEEECONTROL0_PWRDWN_SW_SHIFT 11 2525 2526 /* ieee0Blk :: ieeeControl0 :: reserved0 [10:10] */ 2527 #define IEEE0BLK_IEEECONTROL0_RESERVED0_MASK 0x0400 2528 #define IEEE0BLK_IEEECONTROL0_RESERVED0_ALIGN 0 2529 #define IEEE0BLK_IEEECONTROL0_RESERVED0_BITS 1 2530 #define IEEE0BLK_IEEECONTROL0_RESERVED0_SHIFT 10 2531 2532 /* ieee0Blk :: ieeeControl0 :: restart_autoneg [09:09] */ 2533 #define IEEE0BLK_IEEECONTROL0_RESTART_AUTONEG_MASK 0x0200 2534 #define IEEE0BLK_IEEECONTROL0_RESTART_AUTONEG_ALIGN 0 2535 #define IEEE0BLK_IEEECONTROL0_RESTART_AUTONEG_BITS 1 2536 #define IEEE0BLK_IEEECONTROL0_RESTART_AUTONEG_SHIFT 9 2537 2538 /* ieee0Blk :: ieeeControl0 :: full_duplex [08:08] */ 2539 #define IEEE0BLK_IEEECONTROL0_FULL_DUPLEX_MASK 0x0100 2540 #define IEEE0BLK_IEEECONTROL0_FULL_DUPLEX_ALIGN 0 2541 #define IEEE0BLK_IEEECONTROL0_FULL_DUPLEX_BITS 1 2542 #define IEEE0BLK_IEEECONTROL0_FULL_DUPLEX_SHIFT 8 2543 2544 /* ieee0Blk :: ieeeControl0 :: collision_test_en [07:07] */ 2545 #define IEEE0BLK_IEEECONTROL0_COLLISION_TEST_EN_MASK 0x0080 2546 #define IEEE0BLK_IEEECONTROL0_COLLISION_TEST_EN_ALIGN 0 2547 #define IEEE0BLK_IEEECONTROL0_COLLISION_TEST_EN_BITS 1 2548 #define IEEE0BLK_IEEECONTROL0_COLLISION_TEST_EN_SHIFT 7 2549 2550 /* ieee0Blk :: ieeeControl0 :: manual_speed1 [06:06] */ 2551 #define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED1_MASK 0x0040 2552 #define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED1_ALIGN 0 2553 #define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED1_BITS 1 2554 #define IEEE0BLK_IEEECONTROL0_MANUAL_SPEED1_SHIFT 6 2555 2556 /* ieee0Blk :: ieeeControl0 :: reserved1 [05:00] */ 2557 #define IEEE0BLK_IEEECONTROL0_RESERVED1_MASK 0x003f 2558 #define IEEE0BLK_IEEECONTROL0_RESERVED1_ALIGN 0 2559 #define IEEE0BLK_IEEECONTROL0_RESERVED1_BITS 6 2560 #define IEEE0BLK_IEEECONTROL0_RESERVED1_SHIFT 0 2561 2562 2563 /**************************************************************************** 2564 * XGXS16G_IEEE_ieee1Blk 2565 */ 2566 /**************************************************************************** 2567 * ieee1Blk :: ieeeControl1 2568 */ 2569 /* ieee1Blk :: ieeeControl1 :: rst_hw [15:15] */ 2570 #define IEEE1BLK_IEEECONTROL1_RST_HW_MASK 0x8000 2571 #define IEEE1BLK_IEEECONTROL1_RST_HW_ALIGN 0 2572 #define IEEE1BLK_IEEECONTROL1_RST_HW_BITS 1 2573 #define IEEE1BLK_IEEECONTROL1_RST_HW_SHIFT 15 2574 2575 /* ieee1Blk :: ieeeControl1 :: gloopback [14:14] */ 2576 #define IEEE1BLK_IEEECONTROL1_GLOOPBACK_MASK 0x4000 2577 #define IEEE1BLK_IEEECONTROL1_GLOOPBACK_ALIGN 0 2578 #define IEEE1BLK_IEEECONTROL1_GLOOPBACK_BITS 1 2579 #define IEEE1BLK_IEEECONTROL1_GLOOPBACK_SHIFT 14 2580 2581 /* ieee1Blk :: ieeeControl1 :: manual_speed0 [13:13] */ 2582 #define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED0_MASK 0x2000 2583 #define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED0_ALIGN 0 2584 #define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED0_BITS 1 2585 #define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED0_SHIFT 13 2586 2587 /* ieee1Blk :: ieeeControl1 :: autoneg_enable [12:12] */ 2588 #define IEEE1BLK_IEEECONTROL1_AUTONEG_ENABLE_MASK 0x1000 2589 #define IEEE1BLK_IEEECONTROL1_AUTONEG_ENABLE_ALIGN 0 2590 #define IEEE1BLK_IEEECONTROL1_AUTONEG_ENABLE_BITS 1 2591 #define IEEE1BLK_IEEECONTROL1_AUTONEG_ENABLE_SHIFT 12 2592 2593 /* ieee1Blk :: ieeeControl1 :: pwrdwn_sw [11:11] */ 2594 #define IEEE1BLK_IEEECONTROL1_PWRDWN_SW_MASK 0x0800 2595 #define IEEE1BLK_IEEECONTROL1_PWRDWN_SW_ALIGN 0 2596 #define IEEE1BLK_IEEECONTROL1_PWRDWN_SW_BITS 1 2597 #define IEEE1BLK_IEEECONTROL1_PWRDWN_SW_SHIFT 11 2598 2599 /* ieee1Blk :: ieeeControl1 :: reserved0 [10:10] */ 2600 #define IEEE1BLK_IEEECONTROL1_RESERVED0_MASK 0x0400 2601 #define IEEE1BLK_IEEECONTROL1_RESERVED0_ALIGN 0 2602 #define IEEE1BLK_IEEECONTROL1_RESERVED0_BITS 1 2603 #define IEEE1BLK_IEEECONTROL1_RESERVED0_SHIFT 10 2604 2605 /* ieee1Blk :: ieeeControl1 :: restart_autoneg [09:09] */ 2606 #define IEEE1BLK_IEEECONTROL1_RESTART_AUTONEG_MASK 0x0200 2607 #define IEEE1BLK_IEEECONTROL1_RESTART_AUTONEG_ALIGN 0 2608 #define IEEE1BLK_IEEECONTROL1_RESTART_AUTONEG_BITS 1 2609 #define IEEE1BLK_IEEECONTROL1_RESTART_AUTONEG_SHIFT 9 2610 2611 /* ieee1Blk :: ieeeControl1 :: full_duplex [08:08] */ 2612 #define IEEE1BLK_IEEECONTROL1_FULL_DUPLEX_MASK 0x0100 2613 #define IEEE1BLK_IEEECONTROL1_FULL_DUPLEX_ALIGN 0 2614 #define IEEE1BLK_IEEECONTROL1_FULL_DUPLEX_BITS 1 2615 #define IEEE1BLK_IEEECONTROL1_FULL_DUPLEX_SHIFT 8 2616 2617 /* ieee1Blk :: ieeeControl1 :: collision_test_en [07:07] */ 2618 #define IEEE1BLK_IEEECONTROL1_COLLISION_TEST_EN_MASK 0x0080 2619 #define IEEE1BLK_IEEECONTROL1_COLLISION_TEST_EN_ALIGN 0 2620 #define IEEE1BLK_IEEECONTROL1_COLLISION_TEST_EN_BITS 1 2621 #define IEEE1BLK_IEEECONTROL1_COLLISION_TEST_EN_SHIFT 7 2622 2623 /* ieee1Blk :: ieeeControl1 :: manual_speed1 [06:06] */ 2624 #define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED1_MASK 0x0040 2625 #define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED1_ALIGN 0 2626 #define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED1_BITS 1 2627 #define IEEE1BLK_IEEECONTROL1_MANUAL_SPEED1_SHIFT 6 2628 2629 /* ieee1Blk :: ieeeControl1 :: reserved1 [05:00] */ 2630 #define IEEE1BLK_IEEECONTROL1_RESERVED1_MASK 0x003f 2631 #define IEEE1BLK_IEEECONTROL1_RESERVED1_ALIGN 0 2632 #define IEEE1BLK_IEEECONTROL1_RESERVED1_BITS 6 2633 #define IEEE1BLK_IEEECONTROL1_RESERVED1_SHIFT 0 2634 2635 2636 /**************************************************************************** 2637 * XGXS16G_USER_XgxsBlk0 2638 */ 2639 /**************************************************************************** 2640 * XgxsBlk0 :: xgxsControl 2641 */ 2642 /* XgxsBlk0 :: xgxsControl :: pgen_en [15:15] */ 2643 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_MASK 0x8000 2644 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_ALIGN 0 2645 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_BITS 1 2646 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_SHIFT 15 2647 2648 /* XgxsBlk0 :: xgxsControl :: pcmp_en [14:14] */ 2649 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_MASK 0x4000 2650 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_ALIGN 0 2651 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_BITS 1 2652 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_SHIFT 14 2653 2654 /* XgxsBlk0 :: xgxsControl :: start_sequencer [13:13] */ 2655 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_MASK 0x2000 2656 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_ALIGN 0 2657 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_BITS 1 2658 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_SHIFT 13 2659 2660 /* XgxsBlk0 :: xgxsControl :: reset_anlg [12:12] */ 2661 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_MASK 0x1000 2662 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_ALIGN 0 2663 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_BITS 1 2664 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_SHIFT 12 2665 2666 /* XgxsBlk0 :: xgxsControl :: mode_10g [11:08] */ 2667 #define XGXSBLK0_XGXSCONTROL_MODE_10G_MASK 0x0f00 2668 #define XGXSBLK0_XGXSCONTROL_MODE_10G_ALIGN 0 2669 #define XGXSBLK0_XGXSCONTROL_MODE_10G_BITS 4 2670 #define XGXSBLK0_XGXSCONTROL_MODE_10G_SHIFT 8 2671 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS 0 2672 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_noCC 1 2673 #define XGXSBLK0_XGXSCONTROL_MODE_10G_IndLane 6 2674 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_noLss 8 2675 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_noLss_noCC 9 2676 #define XGXSBLK0_XGXSCONTROL_MODE_10G_protBypass 10 2677 #define XGXSBLK0_XGXSCONTROL_MODE_10G_protBypass_noDsk 11 2678 #define XGXSBLK0_XGXSCONTROL_MODE_10G_ComboCoreMode 12 2679 #define XGXSBLK0_XGXSCONTROL_MODE_10G_ClocksOff 15 2680 2681 /* XgxsBlk0 :: xgxsControl :: pll_bypass [07:07] */ 2682 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_MASK 0x0080 2683 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_ALIGN 0 2684 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_BITS 1 2685 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_SHIFT 7 2686 2687 /* XgxsBlk0 :: xgxsControl :: rloop [06:06] */ 2688 #define XGXSBLK0_XGXSCONTROL_RLOOP_MASK 0x0040 2689 #define XGXSBLK0_XGXSCONTROL_RLOOP_ALIGN 0 2690 #define XGXSBLK0_XGXSCONTROL_RLOOP_BITS 1 2691 #define XGXSBLK0_XGXSCONTROL_RLOOP_SHIFT 6 2692 2693 /* XgxsBlk0 :: xgxsControl :: hstl [05:05] */ 2694 #define XGXSBLK0_XGXSCONTROL_HSTL_MASK 0x0020 2695 #define XGXSBLK0_XGXSCONTROL_HSTL_ALIGN 0 2696 #define XGXSBLK0_XGXSCONTROL_HSTL_BITS 1 2697 #define XGXSBLK0_XGXSCONTROL_HSTL_SHIFT 5 2698 2699 /* XgxsBlk0 :: xgxsControl :: mdio_cont_en [04:04] */ 2700 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_MASK 0x0010 2701 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_ALIGN 0 2702 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_BITS 1 2703 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_SHIFT 4 2704 2705 /* XgxsBlk0 :: xgxsControl :: cdet_en [03:03] */ 2706 #define XGXSBLK0_XGXSCONTROL_CDET_EN_MASK 0x0008 2707 #define XGXSBLK0_XGXSCONTROL_CDET_EN_ALIGN 0 2708 #define XGXSBLK0_XGXSCONTROL_CDET_EN_BITS 1 2709 #define XGXSBLK0_XGXSCONTROL_CDET_EN_SHIFT 3 2710 2711 /* XgxsBlk0 :: xgxsControl :: eden [02:02] */ 2712 #define XGXSBLK0_XGXSCONTROL_EDEN_MASK 0x0004 2713 #define XGXSBLK0_XGXSCONTROL_EDEN_ALIGN 0 2714 #define XGXSBLK0_XGXSCONTROL_EDEN_BITS 1 2715 #define XGXSBLK0_XGXSCONTROL_EDEN_SHIFT 2 2716 2717 /* XgxsBlk0 :: xgxsControl :: afrst_en [01:01] */ 2718 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_MASK 0x0002 2719 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_ALIGN 0 2720 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_BITS 1 2721 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_SHIFT 1 2722 2723 /* XgxsBlk0 :: xgxsControl :: txcko_div [00:00] */ 2724 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_MASK 0x0001 2725 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_ALIGN 0 2726 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_BITS 1 2727 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_SHIFT 0 2728 2729 2730 /**************************************************************************** 2731 * XgxsBlk0 :: xgxsStatus 2732 */ 2733 /* XgxsBlk0 :: xgxsStatus :: status_en [15:15] */ 2734 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_MASK 0x8000 2735 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_ALIGN 0 2736 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_BITS 1 2737 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_SHIFT 15 2738 2739 /* XgxsBlk0 :: xgxsStatus :: reserved0 [14:14] */ 2740 #define XGXSBLK0_XGXSSTATUS_RESERVED0_MASK 0x4000 2741 #define XGXSBLK0_XGXSSTATUS_RESERVED0_ALIGN 0 2742 #define XGXSBLK0_XGXSSTATUS_RESERVED0_BITS 1 2743 #define XGXSBLK0_XGXSSTATUS_RESERVED0_SHIFT 14 2744 2745 /* XgxsBlk0 :: xgxsStatus :: tx_remote_fault [13:13] */ 2746 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_MASK 0x2000 2747 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_ALIGN 0 2748 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_BITS 1 2749 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_SHIFT 13 2750 2751 /* XgxsBlk0 :: xgxsStatus :: rx_remote_fault [12:12] */ 2752 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_MASK 0x1000 2753 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_ALIGN 0 2754 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_BITS 1 2755 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_SHIFT 12 2756 2757 /* XgxsBlk0 :: xgxsStatus :: txpll_lock [11:11] */ 2758 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_MASK 0x0800 2759 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_ALIGN 0 2760 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_BITS 1 2761 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_SHIFT 11 2762 2763 /* XgxsBlk0 :: xgxsStatus :: txd_fifo_err [10:10] */ 2764 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_MASK 0x0400 2765 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_ALIGN 0 2766 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_BITS 1 2767 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_SHIFT 10 2768 2769 /* XgxsBlk0 :: xgxsStatus :: sequencer_done [09:09] */ 2770 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_MASK 0x0200 2771 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_ALIGN 0 2772 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_BITS 1 2773 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_SHIFT 9 2774 2775 /* XgxsBlk0 :: xgxsStatus :: sequencer_pass [08:08] */ 2776 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_MASK 0x0100 2777 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_ALIGN 0 2778 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_BITS 1 2779 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_SHIFT 8 2780 2781 /* XgxsBlk0 :: xgxsStatus :: rxferr [07:04] */ 2782 #define XGXSBLK0_XGXSSTATUS_RXFERR_MASK 0x00f0 2783 #define XGXSBLK0_XGXSSTATUS_RXFERR_ALIGN 0 2784 #define XGXSBLK0_XGXSSTATUS_RXFERR_BITS 4 2785 #define XGXSBLK0_XGXSSTATUS_RXFERR_SHIFT 4 2786 2787 /* XgxsBlk0 :: xgxsStatus :: pll_mode_afe [03:03] */ 2788 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_MASK 0x0008 2789 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_ALIGN 0 2790 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_BITS 1 2791 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_SHIFT 3 2792 2793 /* XgxsBlk0 :: xgxsStatus :: ckcmp_unflow [02:02] */ 2794 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_MASK 0x0004 2795 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_ALIGN 0 2796 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_BITS 1 2797 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_SHIFT 2 2798 2799 /* XgxsBlk0 :: xgxsStatus :: ckcmp_ovflow [01:01] */ 2800 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_MASK 0x0002 2801 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_ALIGN 0 2802 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_BITS 1 2803 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_SHIFT 1 2804 2805 /* XgxsBlk0 :: xgxsStatus :: skew_status [00:00] */ 2806 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_MASK 0x0001 2807 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_ALIGN 0 2808 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_BITS 1 2809 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_SHIFT 0 2810 2811 2812 /**************************************************************************** 2813 * XgxsBlk0 :: xgmiiIdle 2814 */ 2815 /* XgxsBlk0 :: xgmiiIdle :: I [15:08] */ 2816 #define XGXSBLK0_XGMIIIDLE_I_MASK 0xff00 2817 #define XGXSBLK0_XGMIIIDLE_I_ALIGN 0 2818 #define XGXSBLK0_XGMIIIDLE_I_BITS 8 2819 #define XGXSBLK0_XGMIIIDLE_I_SHIFT 8 2820 2821 /* XgxsBlk0 :: xgmiiIdle :: Ib [07:00] */ 2822 #define XGXSBLK0_XGMIIIDLE_IB_MASK 0x00ff 2823 #define XGXSBLK0_XGMIIIDLE_IB_ALIGN 0 2824 #define XGXSBLK0_XGMIIIDLE_IB_BITS 8 2825 #define XGXSBLK0_XGMIIIDLE_IB_SHIFT 0 2826 2827 2828 /**************************************************************************** 2829 * XgxsBlk0 :: xgmiiSync 2830 */ 2831 /* XgxsBlk0 :: xgmiiSync :: K [15:08] */ 2832 #define XGXSBLK0_XGMIISYNC_K_MASK 0xff00 2833 #define XGXSBLK0_XGMIISYNC_K_ALIGN 0 2834 #define XGXSBLK0_XGMIISYNC_K_BITS 8 2835 #define XGXSBLK0_XGMIISYNC_K_SHIFT 8 2836 2837 /* XgxsBlk0 :: xgmiiSync :: Kb [07:00] */ 2838 #define XGXSBLK0_XGMIISYNC_KB_MASK 0x00ff 2839 #define XGXSBLK0_XGMIISYNC_KB_ALIGN 0 2840 #define XGXSBLK0_XGMIISYNC_KB_BITS 8 2841 #define XGXSBLK0_XGMIISYNC_KB_SHIFT 0 2842 2843 2844 /**************************************************************************** 2845 * XgxsBlk0 :: xgmiiSkip 2846 */ 2847 /* XgxsBlk0 :: xgmiiSkip :: R [15:08] */ 2848 #define XGXSBLK0_XGMIISKIP_R_MASK 0xff00 2849 #define XGXSBLK0_XGMIISKIP_R_ALIGN 0 2850 #define XGXSBLK0_XGMIISKIP_R_BITS 8 2851 #define XGXSBLK0_XGMIISKIP_R_SHIFT 8 2852 2853 /* XgxsBlk0 :: xgmiiSkip :: Rb [07:00] */ 2854 #define XGXSBLK0_XGMIISKIP_RB_MASK 0x00ff 2855 #define XGXSBLK0_XGMIISKIP_RB_ALIGN 0 2856 #define XGXSBLK0_XGMIISKIP_RB_BITS 8 2857 #define XGXSBLK0_XGMIISKIP_RB_SHIFT 0 2858 2859 2860 /**************************************************************************** 2861 * XgxsBlk0 :: xgmiiSopEop 2862 */ 2863 /* XgxsBlk0 :: xgmiiSopEop :: S [15:08] */ 2864 #define XGXSBLK0_XGMIISOPEOP_S_MASK 0xff00 2865 #define XGXSBLK0_XGMIISOPEOP_S_ALIGN 0 2866 #define XGXSBLK0_XGMIISOPEOP_S_BITS 8 2867 #define XGXSBLK0_XGMIISOPEOP_S_SHIFT 8 2868 2869 /* XgxsBlk0 :: xgmiiSopEop :: T [07:00] */ 2870 #define XGXSBLK0_XGMIISOPEOP_T_MASK 0x00ff 2871 #define XGXSBLK0_XGMIISOPEOP_T_ALIGN 0 2872 #define XGXSBLK0_XGMIISOPEOP_T_BITS 8 2873 #define XGXSBLK0_XGMIISOPEOP_T_SHIFT 0 2874 2875 2876 /**************************************************************************** 2877 * XgxsBlk0 :: xgmiiAlign 2878 */ 2879 /* XgxsBlk0 :: xgmiiAlign :: E [15:08] */ 2880 #define XGXSBLK0_XGMIIALIGN_E_MASK 0xff00 2881 #define XGXSBLK0_XGMIIALIGN_E_ALIGN 0 2882 #define XGXSBLK0_XGMIIALIGN_E_BITS 8 2883 #define XGXSBLK0_XGMIIALIGN_E_SHIFT 8 2884 2885 /* XgxsBlk0 :: xgmiiAlign :: A [07:00] */ 2886 #define XGXSBLK0_XGMIIALIGN_A_MASK 0x00ff 2887 #define XGXSBLK0_XGMIIALIGN_A_ALIGN 0 2888 #define XGXSBLK0_XGMIIALIGN_A_BITS 8 2889 #define XGXSBLK0_XGMIIALIGN_A_SHIFT 0 2890 2891 2892 /**************************************************************************** 2893 * XgxsBlk0 :: xgmiiRcontrol 2894 */ 2895 /* XgxsBlk0 :: xgmiiRcontrol :: reserved0 [15:15] */ 2896 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_MASK 0x8000 2897 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_ALIGN 0 2898 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_BITS 1 2899 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_SHIFT 15 2900 2901 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf0_en [14:14] */ 2902 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_MASK 0x4000 2903 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_ALIGN 0 2904 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_BITS 1 2905 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_SHIFT 14 2906 2907 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf1_en [13:13] */ 2908 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_MASK 0x2000 2909 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_ALIGN 0 2910 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_BITS 1 2911 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_SHIFT 13 2912 2913 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf2_en [12:12] */ 2914 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_MASK 0x1000 2915 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_ALIGN 0 2916 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_BITS 1 2917 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_SHIFT 12 2918 2919 /* XgxsBlk0 :: xgmiiRcontrol :: force_inbndls_en [11:11] */ 2920 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_MASK 0x0800 2921 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_ALIGN 0 2922 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_BITS 1 2923 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_SHIFT 11 2924 2925 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_en [10:10] */ 2926 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_MASK 0x0400 2927 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_ALIGN 0 2928 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_BITS 1 2929 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_SHIFT 10 2930 2931 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_std_en [09:09] */ 2932 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_MASK 0x0200 2933 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_ALIGN 0 2934 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_BITS 1 2935 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_SHIFT 9 2936 2937 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_force [08:08] */ 2938 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_MASK 0x0100 2939 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_ALIGN 0 2940 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_BITS 1 2941 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_SHIFT 8 2942 2943 /* XgxsBlk0 :: xgmiiRcontrol :: reserved1 [07:07] */ 2944 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_MASK 0x0080 2945 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_ALIGN 0 2946 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_BITS 1 2947 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_SHIFT 7 2948 2949 /* XgxsBlk0 :: xgmiiRcontrol :: scr_en_4lane [06:06] */ 2950 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_MASK 0x0040 2951 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_ALIGN 0 2952 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_BITS 1 2953 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_SHIFT 6 2954 2955 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_noIPG_en [05:05] */ 2956 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_MASK 0x0020 2957 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_ALIGN 0 2958 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_BITS 1 2959 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_SHIFT 5 2960 2961 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_afrst_en [04:04] */ 2962 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_MASK 0x0010 2963 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_ALIGN 0 2964 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_BITS 1 2965 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_SHIFT 4 2966 2967 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_gt1_Icol_dis [03:03] */ 2968 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_MASK 0x0008 2969 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_ALIGN 0 2970 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_BITS 1 2971 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_SHIFT 3 2972 2973 /* XgxsBlk0 :: xgmiiRcontrol :: reserved2 [02:00] */ 2974 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_MASK 0x0007 2975 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_ALIGN 0 2976 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_BITS 3 2977 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_SHIFT 0 2978 2979 2980 /**************************************************************************** 2981 * XgxsBlk0 :: xgmiiTcontrol 2982 */ 2983 /* XgxsBlk0 :: xgmiiTcontrol :: swapen [15:15] */ 2984 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_MASK 0x8000 2985 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_ALIGN 0 2986 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_BITS 1 2987 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_SHIFT 15 2988 2989 /* XgxsBlk0 :: xgmiiTcontrol :: swap_lane_ind [14:14] */ 2990 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_MASK 0x4000 2991 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_ALIGN 0 2992 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_BITS 1 2993 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_SHIFT 14 2994 2995 /* XgxsBlk0 :: xgmiiTcontrol :: pn_sel [13:13] */ 2996 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_MASK 0x2000 2997 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_ALIGN 0 2998 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_BITS 1 2999 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_SHIFT 13 3000 3001 /* XgxsBlk0 :: xgmiiTcontrol :: reserved0 [12:09] */ 3002 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_MASK 0x1e00 3003 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_ALIGN 0 3004 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_BITS 4 3005 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_SHIFT 9 3006 3007 /* XgxsBlk0 :: xgmiiTcontrol :: alignstat_rxlf_en [08:08] */ 3008 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_MASK 0x0100 3009 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_ALIGN 0 3010 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_BITS 1 3011 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_SHIFT 8 3012 3013 /* XgxsBlk0 :: xgmiiTcontrol :: flip_txrx_lf [07:07] */ 3014 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_MASK 0x0080 3015 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_ALIGN 0 3016 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_BITS 1 3017 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_SHIFT 7 3018 3019 /* XgxsBlk0 :: xgmiiTcontrol :: xenpak_lfclr_en [06:06] */ 3020 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_MASK 0x0040 3021 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_ALIGN 0 3022 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_BITS 1 3023 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_SHIFT 6 3024 3025 /* XgxsBlk0 :: xgmiiTcontrol :: tx_xgmii_Tcol_old_en [05:05] */ 3026 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_MASK 0x0020 3027 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_ALIGN 0 3028 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_BITS 1 3029 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_SHIFT 5 3030 3031 /* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_IorRF_en [04:04] */ 3032 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_MASK 0x0010 3033 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_ALIGN 0 3034 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_BITS 1 3035 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_SHIFT 4 3036 3037 /* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_I_en [03:03] */ 3038 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_MASK 0x0008 3039 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_ALIGN 0 3040 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_BITS 1 3041 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_SHIFT 3 3042 3043 /* XgxsBlk0 :: xgmiiTcontrol :: reserved1 [02:00] */ 3044 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_MASK 0x0007 3045 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_ALIGN 0 3046 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_BITS 3 3047 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_SHIFT 0 3048 3049 3050 /**************************************************************************** 3051 * XgxsBlk0 :: xgmiiSwap 3052 */ 3053 /* XgxsBlk0 :: xgmiiSwap :: swap_count [15:00] */ 3054 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_MASK 0xffff 3055 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_ALIGN 0 3056 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_BITS 16 3057 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_SHIFT 0 3058 3059 3060 /**************************************************************************** 3061 * XgxsBlk0 :: lssLsid 3062 */ 3063 /* XgxsBlk0 :: lssLsid :: lss_ls_id [15:08] */ 3064 #define XGXSBLK0_LSSLSID_LSS_LS_ID_MASK 0xff00 3065 #define XGXSBLK0_LSSLSID_LSS_LS_ID_ALIGN 0 3066 #define XGXSBLK0_LSSLSID_LSS_LS_ID_BITS 8 3067 #define XGXSBLK0_LSSLSID_LSS_LS_ID_SHIFT 8 3068 3069 /* XgxsBlk0 :: lssLsid :: lss_domain_id [07:00] */ 3070 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_MASK 0x00ff 3071 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_ALIGN 0 3072 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_BITS 8 3073 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_SHIFT 0 3074 3075 3076 /**************************************************************************** 3077 * XgxsBlk0 :: lssTinfo 3078 */ 3079 /* XgxsBlk0 :: lssTinfo :: lss_function_id [15:08] */ 3080 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_MASK 0xff00 3081 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_ALIGN 0 3082 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_BITS 8 3083 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_SHIFT 8 3084 3085 /* XgxsBlk0 :: lssTinfo :: lssL_info_byte [07:00] */ 3086 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_MASK 0x00ff 3087 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_ALIGN 0 3088 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_BITS 8 3089 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_SHIFT 0 3090 3091 3092 /**************************************************************************** 3093 * XgxsBlk0 :: lssRinfo 3094 */ 3095 /* XgxsBlk0 :: lssRinfo :: control_en [15:15] */ 3096 #define XGXSBLK0_LSSRINFO_CONTROL_EN_MASK 0x8000 3097 #define XGXSBLK0_LSSRINFO_CONTROL_EN_ALIGN 0 3098 #define XGXSBLK0_LSSRINFO_CONTROL_EN_BITS 1 3099 #define XGXSBLK0_LSSRINFO_CONTROL_EN_SHIFT 15 3100 3101 /* XgxsBlk0 :: lssRinfo :: reserved0 [14:14] */ 3102 #define XGXSBLK0_LSSRINFO_RESERVED0_MASK 0x4000 3103 #define XGXSBLK0_LSSRINFO_RESERVED0_ALIGN 0 3104 #define XGXSBLK0_LSSRINFO_RESERVED0_BITS 1 3105 #define XGXSBLK0_LSSRINFO_RESERVED0_SHIFT 14 3106 3107 /* XgxsBlk0 :: lssRinfo :: lss_ls_id8 [13:13] */ 3108 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_MASK 0x2000 3109 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_ALIGN 0 3110 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_BITS 1 3111 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_SHIFT 13 3112 3113 /* XgxsBlk0 :: lssRinfo :: lss_domain_id8 [12:12] */ 3114 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_MASK 0x1000 3115 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_ALIGN 0 3116 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_BITS 1 3117 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_SHIFT 12 3118 3119 /* XgxsBlk0 :: lssRinfo :: lss_function_id8 [11:11] */ 3120 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_MASK 0x0800 3121 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_ALIGN 0 3122 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_BITS 1 3123 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_SHIFT 11 3124 3125 /* XgxsBlk0 :: lssRinfo :: lssL_info_byte8 [10:10] */ 3126 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_MASK 0x0400 3127 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_ALIGN 0 3128 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_BITS 1 3129 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_SHIFT 10 3130 3131 /* XgxsBlk0 :: lssRinfo :: reserved1 [09:09] */ 3132 #define XGXSBLK0_LSSRINFO_RESERVED1_MASK 0x0200 3133 #define XGXSBLK0_LSSRINFO_RESERVED1_ALIGN 0 3134 #define XGXSBLK0_LSSRINFO_RESERVED1_BITS 1 3135 #define XGXSBLK0_LSSRINFO_RESERVED1_SHIFT 9 3136 3137 /* XgxsBlk0 :: lssRinfo :: lssR_info_byte [08:00] */ 3138 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_MASK 0x01ff 3139 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_ALIGN 0 3140 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_BITS 9 3141 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_SHIFT 0 3142 3143 3144 /**************************************************************************** 3145 * XgxsBlk0 :: mmdSelect 3146 */ 3147 /* XgxsBlk0 :: mmdSelect :: multiPRTs_en [15:15] */ 3148 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_MASK 0x8000 3149 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_ALIGN 0 3150 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_BITS 1 3151 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_SHIFT 15 3152 3153 /* XgxsBlk0 :: mmdSelect :: multiMMDs_en [14:14] */ 3154 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_MASK 0x4000 3155 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_ALIGN 0 3156 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_BITS 1 3157 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_SHIFT 14 3158 3159 /* XgxsBlk0 :: mmdSelect :: reserved0 [13:04] */ 3160 #define XGXSBLK0_MMDSELECT_RESERVED0_MASK 0x3ff0 3161 #define XGXSBLK0_MMDSELECT_RESERVED0_ALIGN 0 3162 #define XGXSBLK0_MMDSELECT_RESERVED0_BITS 10 3163 #define XGXSBLK0_MMDSELECT_RESERVED0_SHIFT 4 3164 3165 /* XgxsBlk0 :: mmdSelect :: devAN_en [03:03] */ 3166 #define XGXSBLK0_MMDSELECT_DEVAN_EN_MASK 0x0008 3167 #define XGXSBLK0_MMDSELECT_DEVAN_EN_ALIGN 0 3168 #define XGXSBLK0_MMDSELECT_DEVAN_EN_BITS 1 3169 #define XGXSBLK0_MMDSELECT_DEVAN_EN_SHIFT 3 3170 3171 /* XgxsBlk0 :: mmdSelect :: devPMD_en [02:02] */ 3172 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_MASK 0x0004 3173 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_ALIGN 0 3174 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_BITS 1 3175 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_SHIFT 2 3176 3177 /* XgxsBlk0 :: mmdSelect :: devDEVAD_en [01:01] */ 3178 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_MASK 0x0002 3179 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_ALIGN 0 3180 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_BITS 1 3181 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_SHIFT 1 3182 3183 /* XgxsBlk0 :: mmdSelect :: devCL22_en [00:00] */ 3184 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_MASK 0x0001 3185 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_ALIGN 0 3186 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_BITS 1 3187 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_SHIFT 0 3188 3189 3190 /**************************************************************************** 3191 * XgxsBlk0 :: miscControl1 3192 */ 3193 /* XgxsBlk0 :: miscControl1 :: PMD_Lane3_tx_disable [15:15] */ 3194 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_MASK 0x8000 3195 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_ALIGN 0 3196 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_BITS 1 3197 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_SHIFT 15 3198 3199 /* XgxsBlk0 :: miscControl1 :: PMD_Lane2_tx_disable [14:14] */ 3200 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_MASK 0x4000 3201 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_ALIGN 0 3202 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_BITS 1 3203 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_SHIFT 14 3204 3205 /* XgxsBlk0 :: miscControl1 :: PMD_Lane1_tx_disable [13:13] */ 3206 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_MASK 0x2000 3207 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_ALIGN 0 3208 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_BITS 1 3209 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_SHIFT 13 3210 3211 /* XgxsBlk0 :: miscControl1 :: PMD_Lane0_tx_disable [12:12] */ 3212 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_MASK 0x1000 3213 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_ALIGN 0 3214 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_BITS 1 3215 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_SHIFT 12 3216 3217 /* XgxsBlk0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */ 3218 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK 0x0800 3219 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN 0 3220 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS 1 3221 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT 11 3222 3223 /* XgxsBlk0 :: miscControl1 :: PCS_dev_en_override [10:10] */ 3224 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_MASK 0x0400 3225 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_ALIGN 0 3226 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_BITS 1 3227 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_SHIFT 10 3228 3229 /* XgxsBlk0 :: miscControl1 :: PMD_dev_en_override [09:09] */ 3230 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_MASK 0x0200 3231 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_ALIGN 0 3232 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_BITS 1 3233 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_SHIFT 9 3234 3235 /* XgxsBlk0 :: miscControl1 :: reserved0 [08:08] */ 3236 #define XGXSBLK0_MISCCONTROL1_RESERVED0_MASK 0x0100 3237 #define XGXSBLK0_MISCCONTROL1_RESERVED0_ALIGN 0 3238 #define XGXSBLK0_MISCCONTROL1_RESERVED0_BITS 1 3239 #define XGXSBLK0_MISCCONTROL1_RESERVED0_SHIFT 8 3240 3241 /* XgxsBlk0 :: miscControl1 :: clear_linkdown [07:07] */ 3242 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_MASK 0x0080 3243 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_ALIGN 0 3244 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_BITS 1 3245 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_SHIFT 7 3246 3247 /* XgxsBlk0 :: miscControl1 :: latch_linkdown_enable [06:06] */ 3248 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_MASK 0x0040 3249 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_ALIGN 0 3250 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_BITS 1 3251 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_SHIFT 6 3252 3253 /* XgxsBlk0 :: miscControl1 :: reserved1 [05:05] */ 3254 #define XGXSBLK0_MISCCONTROL1_RESERVED1_MASK 0x0020 3255 #define XGXSBLK0_MISCCONTROL1_RESERVED1_ALIGN 0 3256 #define XGXSBLK0_MISCCONTROL1_RESERVED1_BITS 1 3257 #define XGXSBLK0_MISCCONTROL1_RESERVED1_SHIFT 5 3258 3259 /* XgxsBlk0 :: miscControl1 :: force_div5_for_lxck25 [04:04] */ 3260 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_MASK 0x0010 3261 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_ALIGN 0 3262 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_BITS 1 3263 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_SHIFT 4 3264 3265 /* XgxsBlk0 :: miscControl1 :: pardet10g_pwrdnLink_en [03:03] */ 3266 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_MASK 0x0008 3267 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_ALIGN 0 3268 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_BITS 1 3269 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_SHIFT 3 3270 3271 /* XgxsBlk0 :: miscControl1 :: invert_rx_sigdet [02:02] */ 3272 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_MASK 0x0004 3273 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_ALIGN 0 3274 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_BITS 1 3275 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_SHIFT 2 3276 3277 /* XgxsBlk0 :: miscControl1 :: ieee_blksel_autodet [01:01] */ 3278 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_MASK 0x0002 3279 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_ALIGN 0 3280 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_BITS 1 3281 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_SHIFT 1 3282 3283 /* XgxsBlk0 :: miscControl1 :: ieee_blksel_val [00:00] */ 3284 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_MASK 0x0001 3285 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_ALIGN 0 3286 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_BITS 1 3287 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_SHIFT 0 3288 3289 3290 /**************************************************************************** 3291 * XgxsBlk0 :: BlockAddress 3292 */ 3293 /* XgxsBlk0 :: BlockAddress :: reserved0 [15:15] */ 3294 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_MASK 0x8000 3295 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_ALIGN 0 3296 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_BITS 1 3297 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_SHIFT 15 3298 3299 /* XgxsBlk0 :: BlockAddress :: BlockAddress [14:04] */ 3300 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_MASK 0x7ff0 3301 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_ALIGN 0 3302 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_BITS 11 3303 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_SHIFT 4 3304 3305 /* XgxsBlk0 :: BlockAddress :: reserved1 [03:00] */ 3306 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_MASK 0x000f 3307 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_ALIGN 0 3308 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_BITS 4 3309 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_SHIFT 0 3310 3311 3312 /**************************************************************************** 3313 * XGXS16G_USER_XgxsBlk1 3314 */ 3315 /**************************************************************************** 3316 * XgxsBlk1 :: deskew 3317 */ 3318 /* XgxsBlk1 :: deskew :: link_en [15:15] */ 3319 #define XGXSBLK1_DESKEW_LINK_EN_MASK 0x8000 3320 #define XGXSBLK1_DESKEW_LINK_EN_ALIGN 0 3321 #define XGXSBLK1_DESKEW_LINK_EN_BITS 1 3322 #define XGXSBLK1_DESKEW_LINK_EN_SHIFT 15 3323 3324 /* XgxsBlk1 :: deskew :: deskew_hyst_en [14:14] */ 3325 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_MASK 0x4000 3326 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_ALIGN 0 3327 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_BITS 1 3328 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_SHIFT 14 3329 3330 /* XgxsBlk1 :: deskew :: dswin [13:09] */ 3331 #define XGXSBLK1_DESKEW_DSWIN_MASK 0x3e00 3332 #define XGXSBLK1_DESKEW_DSWIN_ALIGN 0 3333 #define XGXSBLK1_DESKEW_DSWIN_BITS 5 3334 #define XGXSBLK1_DESKEW_DSWIN_SHIFT 9 3335 3336 /* XgxsBlk1 :: deskew :: mpwin [08:00] */ 3337 #define XGXSBLK1_DESKEW_MPWIN_MASK 0x01ff 3338 #define XGXSBLK1_DESKEW_MPWIN_ALIGN 0 3339 #define XGXSBLK1_DESKEW_MPWIN_BITS 9 3340 #define XGXSBLK1_DESKEW_MPWIN_SHIFT 0 3341 3342 3343 /**************************************************************************** 3344 * XgxsBlk1 :: link 3345 */ 3346 /* XgxsBlk1 :: link :: Acolwin [15:00] */ 3347 #define XGXSBLK1_LINK_ACOLWIN_MASK 0xffff 3348 #define XGXSBLK1_LINK_ACOLWIN_ALIGN 0 3349 #define XGXSBLK1_LINK_ACOLWIN_BITS 16 3350 #define XGXSBLK1_LINK_ACOLWIN_SHIFT 0 3351 3352 3353 /**************************************************************************** 3354 * XgxsBlk1 :: testRx 3355 */ 3356 /* XgxsBlk1 :: testRx :: reserved0 [15:08] */ 3357 #define XGXSBLK1_TESTRX_RESERVED0_MASK 0xff00 3358 #define XGXSBLK1_TESTRX_RESERVED0_ALIGN 0 3359 #define XGXSBLK1_TESTRX_RESERVED0_BITS 8 3360 #define XGXSBLK1_TESTRX_RESERVED0_SHIFT 8 3361 3362 /* XgxsBlk1 :: testRx :: rx_inBandMdio_Qfltr_en [07:07] */ 3363 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_MASK 0x0080 3364 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_ALIGN 0 3365 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_BITS 1 3366 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_SHIFT 7 3367 3368 /* XgxsBlk1 :: testRx :: link_force [06:06] */ 3369 #define XGXSBLK1_TESTRX_LINK_FORCE_MASK 0x0040 3370 #define XGXSBLK1_TESTRX_LINK_FORCE_ALIGN 0 3371 #define XGXSBLK1_TESTRX_LINK_FORCE_BITS 1 3372 #define XGXSBLK1_TESTRX_LINK_FORCE_SHIFT 6 3373 3374 /* XgxsBlk1 :: testRx :: rxtm_modsel [05:03] */ 3375 #define XGXSBLK1_TESTRX_RXTM_MODSEL_MASK 0x0038 3376 #define XGXSBLK1_TESTRX_RXTM_MODSEL_ALIGN 0 3377 #define XGXSBLK1_TESTRX_RXTM_MODSEL_BITS 3 3378 #define XGXSBLK1_TESTRX_RXTM_MODSEL_SHIFT 3 3379 3380 /* XgxsBlk1 :: testRx :: rxtm_tstsel [02:00] */ 3381 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_MASK 0x0007 3382 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_ALIGN 0 3383 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_BITS 3 3384 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_SHIFT 0 3385 3386 3387 /**************************************************************************** 3388 * XgxsBlk1 :: testTx 3389 */ 3390 /* XgxsBlk1 :: testTx :: reserved0 [15:08] */ 3391 #define XGXSBLK1_TESTTX_RESERVED0_MASK 0xff00 3392 #define XGXSBLK1_TESTTX_RESERVED0_ALIGN 0 3393 #define XGXSBLK1_TESTTX_RESERVED0_BITS 8 3394 #define XGXSBLK1_TESTTX_RESERVED0_SHIFT 8 3395 3396 /* XgxsBlk1 :: testTx :: rx_ck4x1muxsel [07:06] */ 3397 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_MASK 0x00c0 3398 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_ALIGN 0 3399 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_BITS 2 3400 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_SHIFT 6 3401 3402 /* XgxsBlk1 :: testTx :: txtm_modsel [05:03] */ 3403 #define XGXSBLK1_TESTTX_TXTM_MODSEL_MASK 0x0038 3404 #define XGXSBLK1_TESTTX_TXTM_MODSEL_ALIGN 0 3405 #define XGXSBLK1_TESTTX_TXTM_MODSEL_BITS 3 3406 #define XGXSBLK1_TESTTX_TXTM_MODSEL_SHIFT 3 3407 3408 /* XgxsBlk1 :: testTx :: txtm_tstsel [02:00] */ 3409 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_MASK 0x0007 3410 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_ALIGN 0 3411 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_BITS 3 3412 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_SHIFT 0 3413 3414 3415 /**************************************************************************** 3416 * XgxsBlk1 :: testXg 3417 */ 3418 /* XgxsBlk1 :: testXg :: evnt_cntr_sel [15:15] */ 3419 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_MASK 0x8000 3420 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_ALIGN 0 3421 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_BITS 1 3422 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_SHIFT 15 3423 3424 /* XgxsBlk1 :: testXg :: txdt_sel [14:14] */ 3425 #define XGXSBLK1_TESTXG_TXDT_SEL_MASK 0x4000 3426 #define XGXSBLK1_TESTXG_TXDT_SEL_ALIGN 0 3427 #define XGXSBLK1_TESTXG_TXDT_SEL_BITS 1 3428 #define XGXSBLK1_TESTXG_TXDT_SEL_SHIFT 14 3429 3430 /* XgxsBlk1 :: testXg :: slice_sel [13:12] */ 3431 #define XGXSBLK1_TESTXG_SLICE_SEL_MASK 0x3000 3432 #define XGXSBLK1_TESTXG_SLICE_SEL_ALIGN 0 3433 #define XGXSBLK1_TESTXG_SLICE_SEL_BITS 2 3434 #define XGXSBLK1_TESTXG_SLICE_SEL_SHIFT 12 3435 3436 /* XgxsBlk1 :: testXg :: reserved0 [11:08] */ 3437 #define XGXSBLK1_TESTXG_RESERVED0_MASK 0x0f00 3438 #define XGXSBLK1_TESTXG_RESERVED0_ALIGN 0 3439 #define XGXSBLK1_TESTXG_RESERVED0_BITS 4 3440 #define XGXSBLK1_TESTXG_RESERVED0_SHIFT 8 3441 3442 /* XgxsBlk1 :: testXg :: test_reg_sel [07:07] */ 3443 #define XGXSBLK1_TESTXG_TEST_REG_SEL_MASK 0x0080 3444 #define XGXSBLK1_TESTXG_TEST_REG_SEL_ALIGN 0 3445 #define XGXSBLK1_TESTXG_TEST_REG_SEL_BITS 1 3446 #define XGXSBLK1_TESTXG_TEST_REG_SEL_SHIFT 7 3447 3448 /* XgxsBlk1 :: testXg :: xg_txtstsel [06:04] */ 3449 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_MASK 0x0070 3450 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_ALIGN 0 3451 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_BITS 3 3452 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_SHIFT 4 3453 3454 /* XgxsBlk1 :: testXg :: xg_rxtstsel [03:00] */ 3455 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_MASK 0x000f 3456 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_ALIGN 0 3457 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_BITS 4 3458 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_SHIFT 0 3459 3460 3461 /**************************************************************************** 3462 * XgxsBlk1 :: laneCtrl0 3463 */ 3464 /* XgxsBlk1 :: laneCtrl0 :: ed66en [15:12] */ 3465 #define XGXSBLK1_LANECTRL0_ED66EN_MASK 0xf000 3466 #define XGXSBLK1_LANECTRL0_ED66EN_ALIGN 0 3467 #define XGXSBLK1_LANECTRL0_ED66EN_BITS 4 3468 #define XGXSBLK1_LANECTRL0_ED66EN_SHIFT 12 3469 3470 /* XgxsBlk1 :: laneCtrl0 :: reserved0 [11:08] */ 3471 #define XGXSBLK1_LANECTRL0_RESERVED0_MASK 0x0f00 3472 #define XGXSBLK1_LANECTRL0_RESERVED0_ALIGN 0 3473 #define XGXSBLK1_LANECTRL0_RESERVED0_BITS 4 3474 #define XGXSBLK1_LANECTRL0_RESERVED0_SHIFT 8 3475 3476 /* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_rx [07:04] */ 3477 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_MASK 0x00f0 3478 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_ALIGN 0 3479 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_BITS 4 3480 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_SHIFT 4 3481 3482 /* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_tx [03:00] */ 3483 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_MASK 0x000f 3484 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_ALIGN 0 3485 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_BITS 4 3486 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_SHIFT 0 3487 3488 3489 /**************************************************************************** 3490 * XgxsBlk1 :: laneCtrl1 3491 */ 3492 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln3 [15:14] */ 3493 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_MASK 0xc000 3494 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_ALIGN 0 3495 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_BITS 2 3496 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SHIFT 14 3497 3498 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln2 [13:12] */ 3499 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_MASK 0x3000 3500 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_ALIGN 0 3501 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_BITS 2 3502 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SHIFT 12 3503 3504 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln1 [11:10] */ 3505 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_MASK 0x0c00 3506 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_ALIGN 0 3507 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_BITS 2 3508 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SHIFT 10 3509 3510 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln0 [09:08] */ 3511 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_MASK 0x0300 3512 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_ALIGN 0 3513 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_BITS 2 3514 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SHIFT 8 3515 3516 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln3 [07:06] */ 3517 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_MASK 0x00c0 3518 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_ALIGN 0 3519 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_BITS 2 3520 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SHIFT 6 3521 3522 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln2 [05:04] */ 3523 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_MASK 0x0030 3524 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_ALIGN 0 3525 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_BITS 2 3526 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SHIFT 4 3527 3528 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln1 [03:02] */ 3529 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_MASK 0x000c 3530 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_ALIGN 0 3531 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_BITS 2 3532 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SHIFT 2 3533 3534 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln0 [01:00] */ 3535 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_MASK 0x0003 3536 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_ALIGN 0 3537 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_BITS 2 3538 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SHIFT 0 3539 3540 3541 /**************************************************************************** 3542 * XgxsBlk1 :: laneCtrl2 3543 */ 3544 /* XgxsBlk1 :: laneCtrl2 :: cdet_en1g [15:12] */ 3545 #define XGXSBLK1_LANECTRL2_CDET_EN1G_MASK 0xf000 3546 #define XGXSBLK1_LANECTRL2_CDET_EN1G_ALIGN 0 3547 #define XGXSBLK1_LANECTRL2_CDET_EN1G_BITS 4 3548 #define XGXSBLK1_LANECTRL2_CDET_EN1G_SHIFT 12 3549 3550 /* XgxsBlk1 :: laneCtrl2 :: eden1g [11:08] */ 3551 #define XGXSBLK1_LANECTRL2_EDEN1G_MASK 0x0f00 3552 #define XGXSBLK1_LANECTRL2_EDEN1G_ALIGN 0 3553 #define XGXSBLK1_LANECTRL2_EDEN1G_BITS 4 3554 #define XGXSBLK1_LANECTRL2_EDEN1G_SHIFT 8 3555 3556 /* XgxsBlk1 :: laneCtrl2 :: rloop1g [07:04] */ 3557 #define XGXSBLK1_LANECTRL2_RLOOP1G_MASK 0x00f0 3558 #define XGXSBLK1_LANECTRL2_RLOOP1G_ALIGN 0 3559 #define XGXSBLK1_LANECTRL2_RLOOP1G_BITS 4 3560 #define XGXSBLK1_LANECTRL2_RLOOP1G_SHIFT 4 3561 3562 /* XgxsBlk1 :: laneCtrl2 :: gloop1g [03:00] */ 3563 #define XGXSBLK1_LANECTRL2_GLOOP1G_MASK 0x000f 3564 #define XGXSBLK1_LANECTRL2_GLOOP1G_ALIGN 0 3565 #define XGXSBLK1_LANECTRL2_GLOOP1G_BITS 4 3566 #define XGXSBLK1_LANECTRL2_GLOOP1G_SHIFT 0 3567 3568 3569 /**************************************************************************** 3570 * XgxsBlk1 :: laneCtrl3 3571 */ 3572 /* XgxsBlk1 :: laneCtrl3 :: lock_ref [15:12] */ 3573 #define XGXSBLK1_LANECTRL3_LOCK_REF_MASK 0xf000 3574 #define XGXSBLK1_LANECTRL3_LOCK_REF_ALIGN 0 3575 #define XGXSBLK1_LANECTRL3_LOCK_REF_BITS 4 3576 #define XGXSBLK1_LANECTRL3_LOCK_REF_SHIFT 12 3577 3578 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn_force [11:11] */ 3579 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_MASK 0x0800 3580 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_ALIGN 0 3581 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_BITS 1 3582 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_SHIFT 11 3583 3584 /* XgxsBlk1 :: laneCtrl3 :: lock_ref_en [10:10] */ 3585 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_MASK 0x0400 3586 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_ALIGN 0 3587 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_BITS 1 3588 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_SHIFT 10 3589 3590 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn10g_pll_dis [09:09] */ 3591 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_MASK 0x0200 3592 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_ALIGN 0 3593 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_BITS 1 3594 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_SHIFT 9 3595 3596 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn_pll [08:08] */ 3597 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_MASK 0x0100 3598 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_ALIGN 0 3599 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_BITS 1 3600 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_SHIFT 8 3601 3602 /* XgxsBlk1 :: laneCtrl3 :: pwrdn_tx [07:04] */ 3603 #define XGXSBLK1_LANECTRL3_PWRDN_TX_MASK 0x00f0 3604 #define XGXSBLK1_LANECTRL3_PWRDN_TX_ALIGN 0 3605 #define XGXSBLK1_LANECTRL3_PWRDN_TX_BITS 4 3606 #define XGXSBLK1_LANECTRL3_PWRDN_TX_SHIFT 4 3607 3608 /* XgxsBlk1 :: laneCtrl3 :: pwrdn_rx [03:00] */ 3609 #define XGXSBLK1_LANECTRL3_PWRDN_RX_MASK 0x000f 3610 #define XGXSBLK1_LANECTRL3_PWRDN_RX_ALIGN 0 3611 #define XGXSBLK1_LANECTRL3_PWRDN_RX_BITS 4 3612 #define XGXSBLK1_LANECTRL3_PWRDN_RX_SHIFT 0 3613 3614 3615 /**************************************************************************** 3616 * XgxsBlk1 :: lanePrbs 3617 */ 3618 /* XgxsBlk1 :: lanePrbs :: prbs_en3 [15:15] */ 3619 #define XGXSBLK1_LANEPRBS_PRBS_EN3_MASK 0x8000 3620 #define XGXSBLK1_LANEPRBS_PRBS_EN3_ALIGN 0 3621 #define XGXSBLK1_LANEPRBS_PRBS_EN3_BITS 1 3622 #define XGXSBLK1_LANEPRBS_PRBS_EN3_SHIFT 15 3623 3624 /* XgxsBlk1 :: lanePrbs :: prbs_inv3 [14:14] */ 3625 #define XGXSBLK1_LANEPRBS_PRBS_INV3_MASK 0x4000 3626 #define XGXSBLK1_LANEPRBS_PRBS_INV3_ALIGN 0 3627 #define XGXSBLK1_LANEPRBS_PRBS_INV3_BITS 1 3628 #define XGXSBLK1_LANEPRBS_PRBS_INV3_SHIFT 14 3629 3630 /* XgxsBlk1 :: lanePrbs :: prbs_order3 [13:12] */ 3631 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_MASK 0x3000 3632 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_ALIGN 0 3633 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_BITS 2 3634 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_SHIFT 12 3635 3636 /* XgxsBlk1 :: lanePrbs :: prbs_en2 [11:11] */ 3637 #define XGXSBLK1_LANEPRBS_PRBS_EN2_MASK 0x0800 3638 #define XGXSBLK1_LANEPRBS_PRBS_EN2_ALIGN 0 3639 #define XGXSBLK1_LANEPRBS_PRBS_EN2_BITS 1 3640 #define XGXSBLK1_LANEPRBS_PRBS_EN2_SHIFT 11 3641 3642 /* XgxsBlk1 :: lanePrbs :: prbs_inv2 [10:10] */ 3643 #define XGXSBLK1_LANEPRBS_PRBS_INV2_MASK 0x0400 3644 #define XGXSBLK1_LANEPRBS_PRBS_INV2_ALIGN 0 3645 #define XGXSBLK1_LANEPRBS_PRBS_INV2_BITS 1 3646 #define XGXSBLK1_LANEPRBS_PRBS_INV2_SHIFT 10 3647 3648 /* XgxsBlk1 :: lanePrbs :: prbs_order2 [09:08] */ 3649 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_MASK 0x0300 3650 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_ALIGN 0 3651 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_BITS 2 3652 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_SHIFT 8 3653 3654 /* XgxsBlk1 :: lanePrbs :: prbs_en1 [07:07] */ 3655 #define XGXSBLK1_LANEPRBS_PRBS_EN1_MASK 0x0080 3656 #define XGXSBLK1_LANEPRBS_PRBS_EN1_ALIGN 0 3657 #define XGXSBLK1_LANEPRBS_PRBS_EN1_BITS 1 3658 #define XGXSBLK1_LANEPRBS_PRBS_EN1_SHIFT 7 3659 3660 /* XgxsBlk1 :: lanePrbs :: prbs_inv1 [06:06] */ 3661 #define XGXSBLK1_LANEPRBS_PRBS_INV1_MASK 0x0040 3662 #define XGXSBLK1_LANEPRBS_PRBS_INV1_ALIGN 0 3663 #define XGXSBLK1_LANEPRBS_PRBS_INV1_BITS 1 3664 #define XGXSBLK1_LANEPRBS_PRBS_INV1_SHIFT 6 3665 3666 /* XgxsBlk1 :: lanePrbs :: prbs_order1 [05:04] */ 3667 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_MASK 0x0030 3668 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_ALIGN 0 3669 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_BITS 2 3670 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_SHIFT 4 3671 3672 /* XgxsBlk1 :: lanePrbs :: prbs_en0 [03:03] */ 3673 #define XGXSBLK1_LANEPRBS_PRBS_EN0_MASK 0x0008 3674 #define XGXSBLK1_LANEPRBS_PRBS_EN0_ALIGN 0 3675 #define XGXSBLK1_LANEPRBS_PRBS_EN0_BITS 1 3676 #define XGXSBLK1_LANEPRBS_PRBS_EN0_SHIFT 3 3677 3678 /* XgxsBlk1 :: lanePrbs :: prbs_inv0 [02:02] */ 3679 #define XGXSBLK1_LANEPRBS_PRBS_INV0_MASK 0x0004 3680 #define XGXSBLK1_LANEPRBS_PRBS_INV0_ALIGN 0 3681 #define XGXSBLK1_LANEPRBS_PRBS_INV0_BITS 1 3682 #define XGXSBLK1_LANEPRBS_PRBS_INV0_SHIFT 2 3683 3684 /* XgxsBlk1 :: lanePrbs :: prbs_order0 [01:00] */ 3685 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_MASK 0x0003 3686 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_ALIGN 0 3687 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_BITS 2 3688 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_SHIFT 0 3689 3690 3691 /**************************************************************************** 3692 * XgxsBlk1 :: laneTest 3693 */ 3694 /* XgxsBlk1 :: laneTest :: tmux_sel [15:12] */ 3695 #define XGXSBLK1_LANETEST_TMUX_SEL_MASK 0xf000 3696 #define XGXSBLK1_LANETEST_TMUX_SEL_ALIGN 0 3697 #define XGXSBLK1_LANETEST_TMUX_SEL_BITS 4 3698 #define XGXSBLK1_LANETEST_TMUX_SEL_SHIFT 12 3699 3700 /* XgxsBlk1 :: laneTest :: inBandMdioRxRstEn [11:11] */ 3701 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_MASK 0x0800 3702 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_ALIGN 0 3703 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_BITS 1 3704 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_SHIFT 11 3705 3706 /* XgxsBlk1 :: laneTest :: pwrdn_ext_dis [10:10] */ 3707 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_MASK 0x0400 3708 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_ALIGN 0 3709 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_BITS 1 3710 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_SHIFT 10 3711 3712 /* XgxsBlk1 :: laneTest :: pwrdn_safe_dis [09:09] */ 3713 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_MASK 0x0200 3714 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_ALIGN 0 3715 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_BITS 1 3716 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_SHIFT 9 3717 3718 /* XgxsBlk1 :: laneTest :: pwrdwn_clks_en [08:08] */ 3719 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_MASK 0x0100 3720 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_ALIGN 0 3721 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_BITS 1 3722 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_SHIFT 8 3723 3724 /* XgxsBlk1 :: laneTest :: rxSeqStart_ext_dis [07:07] */ 3725 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_MASK 0x0080 3726 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_ALIGN 0 3727 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_BITS 1 3728 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_SHIFT 7 3729 3730 /* XgxsBlk1 :: laneTest :: pll_lock_rstb_r [06:06] */ 3731 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_MASK 0x0040 3732 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_ALIGN 0 3733 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_BITS 1 3734 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_SHIFT 6 3735 3736 /* XgxsBlk1 :: laneTest :: lfck_bypass [05:05] */ 3737 #define XGXSBLK1_LANETEST_LFCK_BYPASS_MASK 0x0020 3738 #define XGXSBLK1_LANETEST_LFCK_BYPASS_ALIGN 0 3739 #define XGXSBLK1_LANETEST_LFCK_BYPASS_BITS 1 3740 #define XGXSBLK1_LANETEST_LFCK_BYPASS_SHIFT 5 3741 3742 /* XgxsBlk1 :: laneTest :: rx_snoop_en [04:04] */ 3743 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_MASK 0x0010 3744 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_ALIGN 0 3745 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_BITS 1 3746 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_SHIFT 4 3747 3748 /* XgxsBlk1 :: laneTest :: mode_10g_snoop [03:00] */ 3749 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_MASK 0x000f 3750 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_ALIGN 0 3751 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_BITS 4 3752 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_SHIFT 0 3753 3754 3755 /**************************************************************************** 3756 * XgxsBlk1 :: lssRevnt 3757 */ 3758 /* XgxsBlk1 :: lssRevnt :: lssRevnt [15:00] */ 3759 #define XGXSBLK1_LSSREVNT_LSSREVNT_MASK 0xffff 3760 #define XGXSBLK1_LSSREVNT_LSSREVNT_ALIGN 0 3761 #define XGXSBLK1_LSSREVNT_LSSREVNT_BITS 16 3762 #define XGXSBLK1_LSSREVNT_LSSREVNT_SHIFT 0 3763 3764 3765 /**************************************************************************** 3766 * XgxsBlk1 :: dskevnt 3767 */ 3768 /* XgxsBlk1 :: dskevnt :: dskevnt [15:00] */ 3769 #define XGXSBLK1_DSKEVNT_DSKEVNT_MASK 0xffff 3770 #define XGXSBLK1_DSKEVNT_DSKEVNT_ALIGN 0 3771 #define XGXSBLK1_DSKEVNT_DSKEVNT_BITS 16 3772 #define XGXSBLK1_DSKEVNT_DSKEVNT_SHIFT 0 3773 3774 3775 /**************************************************************************** 3776 * XgxsBlk1 :: Aerrevnt 3777 */ 3778 /* XgxsBlk1 :: Aerrevnt :: Aerrevnt [15:00] */ 3779 #define XGXSBLK1_AERREVNT_AERREVNT_MASK 0xffff 3780 #define XGXSBLK1_AERREVNT_AERREVNT_ALIGN 0 3781 #define XGXSBLK1_AERREVNT_AERREVNT_BITS 16 3782 #define XGXSBLK1_AERREVNT_AERREVNT_SHIFT 0 3783 3784 3785 /**************************************************************************** 3786 * XgxsBlk1 :: ckcmpevnt 3787 */ 3788 /* XgxsBlk1 :: ckcmpevnt :: ckcmpevnt [15:00] */ 3789 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_MASK 0xffff 3790 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_ALIGN 0 3791 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_BITS 16 3792 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_SHIFT 0 3793 3794 3795 /**************************************************************************** 3796 * XGXS16G_USER_PLL 3797 */ 3798 /**************************************************************************** 3799 * PLL :: pllStatus 3800 */ 3801 /* PLL :: pllStatus :: pllSeqDone [15:15] */ 3802 #define PLL_PLLSTATUS_PLLSEQDONE_MASK 0x8000 3803 #define PLL_PLLSTATUS_PLLSEQDONE_ALIGN 0 3804 #define PLL_PLLSTATUS_PLLSEQDONE_BITS 1 3805 #define PLL_PLLSTATUS_PLLSEQDONE_SHIFT 15 3806 3807 /* PLL :: pllStatus :: freqDone [14:14] */ 3808 #define PLL_PLLSTATUS_FREQDONE_MASK 0x4000 3809 #define PLL_PLLSTATUS_FREQDONE_ALIGN 0 3810 #define PLL_PLLSTATUS_FREQDONE_BITS 1 3811 #define PLL_PLLSTATUS_FREQDONE_SHIFT 14 3812 3813 /* PLL :: pllStatus :: capDone [13:13] */ 3814 #define PLL_PLLSTATUS_CAPDONE_MASK 0x2000 3815 #define PLL_PLLSTATUS_CAPDONE_ALIGN 0 3816 #define PLL_PLLSTATUS_CAPDONE_BITS 1 3817 #define PLL_PLLSTATUS_CAPDONE_SHIFT 13 3818 3819 /* PLL :: pllStatus :: ampDone [12:12] */ 3820 #define PLL_PLLSTATUS_AMPDONE_MASK 0x1000 3821 #define PLL_PLLSTATUS_AMPDONE_ALIGN 0 3822 #define PLL_PLLSTATUS_AMPDONE_BITS 1 3823 #define PLL_PLLSTATUS_AMPDONE_SHIFT 12 3824 3825 /* PLL :: pllStatus :: pllSeqPass [11:11] */ 3826 #define PLL_PLLSTATUS_PLLSEQPASS_MASK 0x0800 3827 #define PLL_PLLSTATUS_PLLSEQPASS_ALIGN 0 3828 #define PLL_PLLSTATUS_PLLSEQPASS_BITS 1 3829 #define PLL_PLLSTATUS_PLLSEQPASS_SHIFT 11 3830 3831 /* PLL :: pllStatus :: freqPass [10:10] */ 3832 #define PLL_PLLSTATUS_FREQPASS_MASK 0x0400 3833 #define PLL_PLLSTATUS_FREQPASS_ALIGN 0 3834 #define PLL_PLLSTATUS_FREQPASS_BITS 1 3835 #define PLL_PLLSTATUS_FREQPASS_SHIFT 10 3836 3837 /* PLL :: pllStatus :: capPass [09:09] */ 3838 #define PLL_PLLSTATUS_CAPPASS_MASK 0x0200 3839 #define PLL_PLLSTATUS_CAPPASS_ALIGN 0 3840 #define PLL_PLLSTATUS_CAPPASS_BITS 1 3841 #define PLL_PLLSTATUS_CAPPASS_SHIFT 9 3842 3843 /* PLL :: pllStatus :: ampPass [08:08] */ 3844 #define PLL_PLLSTATUS_AMPPASS_MASK 0x0100 3845 #define PLL_PLLSTATUS_AMPPASS_ALIGN 0 3846 #define PLL_PLLSTATUS_AMPPASS_BITS 1 3847 #define PLL_PLLSTATUS_AMPPASS_SHIFT 8 3848 3849 /* PLL :: pllStatus :: slowdn [07:07] */ 3850 #define PLL_PLLSTATUS_SLOWDN_MASK 0x0080 3851 #define PLL_PLLSTATUS_SLOWDN_ALIGN 0 3852 #define PLL_PLLSTATUS_SLOWDN_BITS 1 3853 #define PLL_PLLSTATUS_SLOWDN_SHIFT 7 3854 3855 /* PLL :: pllStatus :: aboveVdd [06:06] */ 3856 #define PLL_PLLSTATUS_ABOVEVDD_MASK 0x0040 3857 #define PLL_PLLSTATUS_ABOVEVDD_ALIGN 0 3858 #define PLL_PLLSTATUS_ABOVEVDD_BITS 1 3859 #define PLL_PLLSTATUS_ABOVEVDD_SHIFT 6 3860 3861 /* PLL :: pllStatus :: belowVss [05:05] */ 3862 #define PLL_PLLSTATUS_BELOWVSS_MASK 0x0020 3863 #define PLL_PLLSTATUS_BELOWVSS_ALIGN 0 3864 #define PLL_PLLSTATUS_BELOWVSS_BITS 1 3865 #define PLL_PLLSTATUS_BELOWVSS_SHIFT 5 3866 3867 /* PLL :: pllStatus :: reserved0 [04:03] */ 3868 #define PLL_PLLSTATUS_RESERVED0_MASK 0x0018 3869 #define PLL_PLLSTATUS_RESERVED0_ALIGN 0 3870 #define PLL_PLLSTATUS_RESERVED0_BITS 2 3871 #define PLL_PLLSTATUS_RESERVED0_SHIFT 3 3872 3873 /* PLL :: pllStatus :: pll_mode_afe [02:00] */ 3874 #define PLL_PLLSTATUS_PLL_MODE_AFE_MASK 0x0007 3875 #define PLL_PLLSTATUS_PLL_MODE_AFE_ALIGN 0 3876 #define PLL_PLLSTATUS_PLL_MODE_AFE_BITS 3 3877 #define PLL_PLLSTATUS_PLL_MODE_AFE_SHIFT 0 3878 3879 3880 /**************************************************************************** 3881 * PLL :: pllControl 3882 */ 3883 /* PLL :: pllControl :: pllRestart [15:15] */ 3884 #define PLL_PLLCONTROL_PLLRESTART_MASK 0x8000 3885 #define PLL_PLLCONTROL_PLLRESTART_ALIGN 0 3886 #define PLL_PLLCONTROL_PLLRESTART_BITS 1 3887 #define PLL_PLLCONTROL_PLLRESTART_SHIFT 15 3888 3889 /* PLL :: pllControl :: FreqDetRetry_en [14:14] */ 3890 #define PLL_PLLCONTROL_FREQDETRETRY_EN_MASK 0x4000 3891 #define PLL_PLLCONTROL_FREQDETRETRY_EN_ALIGN 0 3892 #define PLL_PLLCONTROL_FREQDETRETRY_EN_BITS 1 3893 #define PLL_PLLCONTROL_FREQDETRETRY_EN_SHIFT 14 3894 3895 /* PLL :: pllControl :: FreqDetRestart_en [13:13] */ 3896 #define PLL_PLLCONTROL_FREQDETRESTART_EN_MASK 0x2000 3897 #define PLL_PLLCONTROL_FREQDETRESTART_EN_ALIGN 0 3898 #define PLL_PLLCONTROL_FREQDETRESTART_EN_BITS 1 3899 #define PLL_PLLCONTROL_FREQDETRESTART_EN_SHIFT 13 3900 3901 /* PLL :: pllControl :: FreqMonitor_en [12:12] */ 3902 #define PLL_PLLCONTROL_FREQMONITOR_EN_MASK 0x1000 3903 #define PLL_PLLCONTROL_FREQMONITOR_EN_ALIGN 0 3904 #define PLL_PLLCONTROL_FREQMONITOR_EN_BITS 1 3905 #define PLL_PLLCONTROL_FREQMONITOR_EN_SHIFT 12 3906 3907 /* PLL :: pllControl :: CapRetry_en [11:11] */ 3908 #define PLL_PLLCONTROL_CAPRETRY_EN_MASK 0x0800 3909 #define PLL_PLLCONTROL_CAPRETRY_EN_ALIGN 0 3910 #define PLL_PLLCONTROL_CAPRETRY_EN_BITS 1 3911 #define PLL_PLLCONTROL_CAPRETRY_EN_SHIFT 11 3912 3913 /* PLL :: pllControl :: VcoDone_en [10:10] */ 3914 #define PLL_PLLCONTROL_VCODONE_EN_MASK 0x0400 3915 #define PLL_PLLCONTROL_VCODONE_EN_ALIGN 0 3916 #define PLL_PLLCONTROL_VCODONE_EN_BITS 1 3917 #define PLL_PLLCONTROL_VCODONE_EN_SHIFT 10 3918 3919 /* PLL :: pllControl :: LinkRestart_en [09:09] */ 3920 #define PLL_PLLCONTROL_LINKRESTART_EN_MASK 0x0200 3921 #define PLL_PLLCONTROL_LINKRESTART_EN_ALIGN 0 3922 #define PLL_PLLCONTROL_LINKRESTART_EN_BITS 1 3923 #define PLL_PLLCONTROL_LINKRESTART_EN_SHIFT 9 3924 3925 /* PLL :: pllControl :: ByteSyncRestart_en [08:08] */ 3926 #define PLL_PLLCONTROL_BYTESYNCRESTART_EN_MASK 0x0100 3927 #define PLL_PLLCONTROL_BYTESYNCRESTART_EN_ALIGN 0 3928 #define PLL_PLLCONTROL_BYTESYNCRESTART_EN_BITS 1 3929 #define PLL_PLLCONTROL_BYTESYNCRESTART_EN_SHIFT 8 3930 3931 /* PLL :: pllControl :: PllForceDone_en [07:07] */ 3932 #define PLL_PLLCONTROL_PLLFORCEDONE_EN_MASK 0x0080 3933 #define PLL_PLLCONTROL_PLLFORCEDONE_EN_ALIGN 0 3934 #define PLL_PLLCONTROL_PLLFORCEDONE_EN_BITS 1 3935 #define PLL_PLLCONTROL_PLLFORCEDONE_EN_SHIFT 7 3936 3937 /* PLL :: pllControl :: PllForceDone [06:06] */ 3938 #define PLL_PLLCONTROL_PLLFORCEDONE_MASK 0x0040 3939 #define PLL_PLLCONTROL_PLLFORCEDONE_ALIGN 0 3940 #define PLL_PLLCONTROL_PLLFORCEDONE_BITS 1 3941 #define PLL_PLLCONTROL_PLLFORCEDONE_SHIFT 6 3942 3943 /* PLL :: pllControl :: PllForcePass [05:05] */ 3944 #define PLL_PLLCONTROL_PLLFORCEPASS_MASK 0x0020 3945 #define PLL_PLLCONTROL_PLLFORCEPASS_ALIGN 0 3946 #define PLL_PLLCONTROL_PLLFORCEPASS_BITS 1 3947 #define PLL_PLLCONTROL_PLLFORCEPASS_SHIFT 5 3948 3949 /* PLL :: pllControl :: PllForceCapDone_en [04:04] */ 3950 #define PLL_PLLCONTROL_PLLFORCECAPDONE_EN_MASK 0x0010 3951 #define PLL_PLLCONTROL_PLLFORCECAPDONE_EN_ALIGN 0 3952 #define PLL_PLLCONTROL_PLLFORCECAPDONE_EN_BITS 1 3953 #define PLL_PLLCONTROL_PLLFORCECAPDONE_EN_SHIFT 4 3954 3955 /* PLL :: pllControl :: PllForceCapDone [03:03] */ 3956 #define PLL_PLLCONTROL_PLLFORCECAPDONE_MASK 0x0008 3957 #define PLL_PLLCONTROL_PLLFORCECAPDONE_ALIGN 0 3958 #define PLL_PLLCONTROL_PLLFORCECAPDONE_BITS 1 3959 #define PLL_PLLCONTROL_PLLFORCECAPDONE_SHIFT 3 3960 3961 /* PLL :: pllControl :: PllForceCapPass_en [02:02] */ 3962 #define PLL_PLLCONTROL_PLLFORCECAPPASS_EN_MASK 0x0004 3963 #define PLL_PLLCONTROL_PLLFORCECAPPASS_EN_ALIGN 0 3964 #define PLL_PLLCONTROL_PLLFORCECAPPASS_EN_BITS 1 3965 #define PLL_PLLCONTROL_PLLFORCECAPPASS_EN_SHIFT 2 3966 3967 /* PLL :: pllControl :: PllForceCapPass [01:01] */ 3968 #define PLL_PLLCONTROL_PLLFORCECAPPASS_MASK 0x0002 3969 #define PLL_PLLCONTROL_PLLFORCECAPPASS_ALIGN 0 3970 #define PLL_PLLCONTROL_PLLFORCECAPPASS_BITS 1 3971 #define PLL_PLLCONTROL_PLLFORCECAPPASS_SHIFT 1 3972 3973 /* PLL :: pllControl :: PllForcePllLock [00:00] */ 3974 #define PLL_PLLCONTROL_PLLFORCEPLLLOCK_MASK 0x0001 3975 #define PLL_PLLCONTROL_PLLFORCEPLLLOCK_ALIGN 0 3976 #define PLL_PLLCONTROL_PLLFORCEPLLLOCK_BITS 1 3977 #define PLL_PLLCONTROL_PLLFORCEPLLLOCK_SHIFT 0 3978 3979 3980 /**************************************************************************** 3981 * PLL :: pllTimer1 3982 */ 3983 /* PLL :: pllTimer1 :: VcoStepTime [15:08] */ 3984 #define PLL_PLLTIMER1_VCOSTEPTIME_MASK 0xff00 3985 #define PLL_PLLTIMER1_VCOSTEPTIME_ALIGN 0 3986 #define PLL_PLLTIMER1_VCOSTEPTIME_BITS 8 3987 #define PLL_PLLTIMER1_VCOSTEPTIME_SHIFT 8 3988 3989 /* PLL :: pllTimer1 :: VcoStartTime [07:00] */ 3990 #define PLL_PLLTIMER1_VCOSTARTTIME_MASK 0x00ff 3991 #define PLL_PLLTIMER1_VCOSTARTTIME_ALIGN 0 3992 #define PLL_PLLTIMER1_VCOSTARTTIME_BITS 8 3993 #define PLL_PLLTIMER1_VCOSTARTTIME_SHIFT 0 3994 3995 3996 /**************************************************************************** 3997 * PLL :: pllTimer2 3998 */ 3999 /* PLL :: pllTimer2 :: reserved0 [15:15] */ 4000 #define PLL_PLLTIMER2_RESERVED0_MASK 0x8000 4001 #define PLL_PLLTIMER2_RESERVED0_ALIGN 0 4002 #define PLL_PLLTIMER2_RESERVED0_BITS 1 4003 #define PLL_PLLTIMER2_RESERVED0_SHIFT 15 4004 4005 /* PLL :: pllTimer2 :: lfckSingleStep_en [14:14] */ 4006 #define PLL_PLLTIMER2_LFCKSINGLESTEP_EN_MASK 0x4000 4007 #define PLL_PLLTIMER2_LFCKSINGLESTEP_EN_ALIGN 0 4008 #define PLL_PLLTIMER2_LFCKSINGLESTEP_EN_BITS 1 4009 #define PLL_PLLTIMER2_LFCKSINGLESTEP_EN_SHIFT 14 4010 4011 /* PLL :: pllTimer2 :: lfckSingleStep [13:13] */ 4012 #define PLL_PLLTIMER2_LFCKSINGLESTEP_MASK 0x2000 4013 #define PLL_PLLTIMER2_LFCKSINGLESTEP_ALIGN 0 4014 #define PLL_PLLTIMER2_LFCKSINGLESTEP_BITS 1 4015 #define PLL_PLLTIMER2_LFCKSINGLESTEP_SHIFT 13 4016 4017 /* PLL :: pllTimer2 :: testMuxSel [12:08] */ 4018 #define PLL_PLLTIMER2_TESTMUXSEL_MASK 0x1f00 4019 #define PLL_PLLTIMER2_TESTMUXSEL_ALIGN 0 4020 #define PLL_PLLTIMER2_TESTMUXSEL_BITS 5 4021 #define PLL_PLLTIMER2_TESTMUXSEL_SHIFT 8 4022 4023 /* PLL :: pllTimer2 :: retryTime [07:00] */ 4024 #define PLL_PLLTIMER2_RETRYTIME_MASK 0x00ff 4025 #define PLL_PLLTIMER2_RETRYTIME_ALIGN 0 4026 #define PLL_PLLTIMER2_RETRYTIME_BITS 8 4027 #define PLL_PLLTIMER2_RETRYTIME_SHIFT 0 4028 4029 4030 /**************************************************************************** 4031 * PLL :: pllTimer3 4032 */ 4033 /* PLL :: pllTimer3 :: reserved0 [15:08] */ 4034 #define PLL_PLLTIMER3_RESERVED0_MASK 0xff00 4035 #define PLL_PLLTIMER3_RESERVED0_ALIGN 0 4036 #define PLL_PLLTIMER3_RESERVED0_BITS 8 4037 #define PLL_PLLTIMER3_RESERVED0_SHIFT 8 4038 4039 /* PLL :: pllTimer3 :: freqDetTime [07:00] */ 4040 #define PLL_PLLTIMER3_FREQDETTIME_MASK 0x00ff 4041 #define PLL_PLLTIMER3_FREQDETTIME_ALIGN 0 4042 #define PLL_PLLTIMER3_FREQDETTIME_BITS 8 4043 #define PLL_PLLTIMER3_FREQDETTIME_SHIFT 0 4044 4045 4046 /**************************************************************************** 4047 * PLL :: capControl 4048 */ 4049 /* PLL :: capControl :: StatusControl [15:15] */ 4050 #define PLL_CAPCONTROL_STATUSCONTROL_MASK 0x8000 4051 #define PLL_CAPCONTROL_STATUSCONTROL_ALIGN 0 4052 #define PLL_CAPCONTROL_STATUSCONTROL_BITS 1 4053 #define PLL_CAPCONTROL_STATUSCONTROL_SHIFT 15 4054 4055 /* PLL :: capControl :: capRestart [14:14] */ 4056 #define PLL_CAPCONTROL_CAPRESTART_MASK 0x4000 4057 #define PLL_CAPCONTROL_CAPRESTART_ALIGN 0 4058 #define PLL_CAPCONTROL_CAPRESTART_BITS 1 4059 #define PLL_CAPCONTROL_CAPRESTART_SHIFT 14 4060 4061 /* PLL :: capControl :: capSelectM_en [13:13] */ 4062 #define PLL_CAPCONTROL_CAPSELECTM_EN_MASK 0x2000 4063 #define PLL_CAPCONTROL_CAPSELECTM_EN_ALIGN 0 4064 #define PLL_CAPCONTROL_CAPSELECTM_EN_BITS 1 4065 #define PLL_CAPCONTROL_CAPSELECTM_EN_SHIFT 13 4066 4067 /* PLL :: capControl :: capForceSlowdn_en [12:12] */ 4068 #define PLL_CAPCONTROL_CAPFORCESLOWDN_EN_MASK 0x1000 4069 #define PLL_CAPCONTROL_CAPFORCESLOWDN_EN_ALIGN 0 4070 #define PLL_CAPCONTROL_CAPFORCESLOWDN_EN_BITS 1 4071 #define PLL_CAPCONTROL_CAPFORCESLOWDN_EN_SHIFT 12 4072 4073 /* PLL :: capControl :: reserved0 [11:10] */ 4074 #define PLL_CAPCONTROL_RESERVED0_MASK 0x0c00 4075 #define PLL_CAPCONTROL_RESERVED0_ALIGN 0 4076 #define PLL_CAPCONTROL_RESERVED0_BITS 2 4077 #define PLL_CAPCONTROL_RESERVED0_SHIFT 10 4078 4079 /* PLL :: capControl :: slowdn_xor [09:09] */ 4080 #define PLL_CAPCONTROL_SLOWDN_XOR_MASK 0x0200 4081 #define PLL_CAPCONTROL_SLOWDN_XOR_ALIGN 0 4082 #define PLL_CAPCONTROL_SLOWDN_XOR_BITS 1 4083 #define PLL_CAPCONTROL_SLOWDN_XOR_SHIFT 9 4084 4085 /* union - case Status [08:00] */ 4086 /* PLL :: capControl :: Slowdn [08:08] */ 4087 #define PLL_CAPCONTROL_STATUS_SLOWDN_MASK 0x0100 4088 #define PLL_CAPCONTROL_STATUS_SLOWDN_ALIGN 0 4089 #define PLL_CAPCONTROL_STATUS_SLOWDN_BITS 1 4090 #define PLL_CAPCONTROL_STATUS_SLOWDN_SHIFT 8 4091 4092 /* PLL :: capControl :: reserved0 [07:07] */ 4093 #define PLL_CAPCONTROL_STATUS_RESERVED0_MASK 0x0080 4094 #define PLL_CAPCONTROL_STATUS_RESERVED0_ALIGN 0 4095 #define PLL_CAPCONTROL_STATUS_RESERVED0_BITS 1 4096 #define PLL_CAPCONTROL_STATUS_RESERVED0_SHIFT 7 4097 4098 /* PLL :: capControl :: capSelect [06:00] */ 4099 #define PLL_CAPCONTROL_STATUS_CAPSELECT_MASK 0x007f 4100 #define PLL_CAPCONTROL_STATUS_CAPSELECT_ALIGN 0 4101 #define PLL_CAPCONTROL_STATUS_CAPSELECT_BITS 7 4102 #define PLL_CAPCONTROL_STATUS_CAPSELECT_SHIFT 0 4103 4104 4105 /* union - case Control [08:00] */ 4106 /* PLL :: capControl :: capForceSlowdn [08:08] */ 4107 #define PLL_CAPCONTROL_CONTROL_CAPFORCESLOWDN_MASK 0x0100 4108 #define PLL_CAPCONTROL_CONTROL_CAPFORCESLOWDN_ALIGN 0 4109 #define PLL_CAPCONTROL_CONTROL_CAPFORCESLOWDN_BITS 1 4110 #define PLL_CAPCONTROL_CONTROL_CAPFORCESLOWDN_SHIFT 8 4111 4112 /* PLL :: capControl :: reserved0 [07:07] */ 4113 #define PLL_CAPCONTROL_CONTROL_RESERVED0_MASK 0x0080 4114 #define PLL_CAPCONTROL_CONTROL_RESERVED0_ALIGN 0 4115 #define PLL_CAPCONTROL_CONTROL_RESERVED0_BITS 1 4116 #define PLL_CAPCONTROL_CONTROL_RESERVED0_SHIFT 7 4117 4118 /* PLL :: capControl :: capSelectM [06:00] */ 4119 #define PLL_CAPCONTROL_CONTROL_CAPSELECTM_MASK 0x007f 4120 #define PLL_CAPCONTROL_CONTROL_CAPSELECTM_ALIGN 0 4121 #define PLL_CAPCONTROL_CONTROL_CAPSELECTM_BITS 7 4122 #define PLL_CAPCONTROL_CONTROL_CAPSELECTM_SHIFT 0 4123 4124 4125 4126 /**************************************************************************** 4127 * PLL :: ampControl 4128 */ 4129 /* PLL :: ampControl :: StatusControl [15:15] */ 4130 #define PLL_AMPCONTROL_STATUSCONTROL_MASK 0x8000 4131 #define PLL_AMPCONTROL_STATUSCONTROL_ALIGN 0 4132 #define PLL_AMPCONTROL_STATUSCONTROL_BITS 1 4133 #define PLL_AMPCONTROL_STATUSCONTROL_SHIFT 15 4134 4135 /* PLL :: ampControl :: ampRestart [14:14] */ 4136 #define PLL_AMPCONTROL_AMPRESTART_MASK 0x4000 4137 #define PLL_AMPCONTROL_AMPRESTART_ALIGN 0 4138 #define PLL_AMPCONTROL_AMPRESTART_BITS 1 4139 #define PLL_AMPCONTROL_AMPRESTART_SHIFT 14 4140 4141 /* PLL :: ampControl :: ampSelectM_en [13:13] */ 4142 #define PLL_AMPCONTROL_AMPSELECTM_EN_MASK 0x2000 4143 #define PLL_AMPCONTROL_AMPSELECTM_EN_ALIGN 0 4144 #define PLL_AMPCONTROL_AMPSELECTM_EN_BITS 1 4145 #define PLL_AMPCONTROL_AMPSELECTM_EN_SHIFT 13 4146 4147 /* PLL :: ampControl :: ampForceBvddAvss_en [12:12] */ 4148 #define PLL_AMPCONTROL_AMPFORCEBVDDAVSS_EN_MASK 0x1000 4149 #define PLL_AMPCONTROL_AMPFORCEBVDDAVSS_EN_ALIGN 0 4150 #define PLL_AMPCONTROL_AMPFORCEBVDDAVSS_EN_BITS 1 4151 #define PLL_AMPCONTROL_AMPFORCEBVDDAVSS_EN_SHIFT 12 4152 4153 /* PLL :: ampControl :: ampIgnoreFailure [11:11] */ 4154 #define PLL_AMPCONTROL_AMPIGNOREFAILURE_MASK 0x0800 4155 #define PLL_AMPCONTROL_AMPIGNOREFAILURE_ALIGN 0 4156 #define PLL_AMPCONTROL_AMPIGNOREFAILURE_BITS 1 4157 #define PLL_AMPCONTROL_AMPIGNOREFAILURE_SHIFT 11 4158 4159 /* PLL :: ampControl :: getVcoLatch [10:10] */ 4160 #define PLL_AMPCONTROL_GETVCOLATCH_MASK 0x0400 4161 #define PLL_AMPCONTROL_GETVCOLATCH_ALIGN 0 4162 #define PLL_AMPCONTROL_GETVCOLATCH_BITS 1 4163 #define PLL_AMPCONTROL_GETVCOLATCH_SHIFT 10 4164 4165 /* PLL :: ampControl :: reserved0 [09:06] */ 4166 #define PLL_AMPCONTROL_RESERVED0_MASK 0x03c0 4167 #define PLL_AMPCONTROL_RESERVED0_ALIGN 0 4168 #define PLL_AMPCONTROL_RESERVED0_BITS 4 4169 #define PLL_AMPCONTROL_RESERVED0_SHIFT 6 4170 4171 /* union - case Status [05:00] */ 4172 /* PLL :: ampControl :: belowVdd [05:05] */ 4173 #define PLL_AMPCONTROL_STATUS_BELOWVDD_MASK 0x0020 4174 #define PLL_AMPCONTROL_STATUS_BELOWVDD_ALIGN 0 4175 #define PLL_AMPCONTROL_STATUS_BELOWVDD_BITS 1 4176 #define PLL_AMPCONTROL_STATUS_BELOWVDD_SHIFT 5 4177 4178 /* PLL :: ampControl :: aboveVss [04:04] */ 4179 #define PLL_AMPCONTROL_STATUS_ABOVEVSS_MASK 0x0010 4180 #define PLL_AMPCONTROL_STATUS_ABOVEVSS_ALIGN 0 4181 #define PLL_AMPCONTROL_STATUS_ABOVEVSS_BITS 1 4182 #define PLL_AMPCONTROL_STATUS_ABOVEVSS_SHIFT 4 4183 4184 /* PLL :: ampControl :: reserved0 [03:03] */ 4185 #define PLL_AMPCONTROL_STATUS_RESERVED0_MASK 0x0008 4186 #define PLL_AMPCONTROL_STATUS_RESERVED0_ALIGN 0 4187 #define PLL_AMPCONTROL_STATUS_RESERVED0_BITS 1 4188 #define PLL_AMPCONTROL_STATUS_RESERVED0_SHIFT 3 4189 4190 /* PLL :: ampControl :: selectM [02:00] */ 4191 #define PLL_AMPCONTROL_STATUS_SELECTM_MASK 0x0007 4192 #define PLL_AMPCONTROL_STATUS_SELECTM_ALIGN 0 4193 #define PLL_AMPCONTROL_STATUS_SELECTM_BITS 3 4194 #define PLL_AMPCONTROL_STATUS_SELECTM_SHIFT 0 4195 4196 4197 /* union - case Control [05:00] */ 4198 /* PLL :: ampControl :: ampForceBelowVdd [05:05] */ 4199 #define PLL_AMPCONTROL_CONTROL_AMPFORCEBELOWVDD_MASK 0x0020 4200 #define PLL_AMPCONTROL_CONTROL_AMPFORCEBELOWVDD_ALIGN 0 4201 #define PLL_AMPCONTROL_CONTROL_AMPFORCEBELOWVDD_BITS 1 4202 #define PLL_AMPCONTROL_CONTROL_AMPFORCEBELOWVDD_SHIFT 5 4203 4204 /* PLL :: ampControl :: ampForceAboveVss [04:04] */ 4205 #define PLL_AMPCONTROL_CONTROL_AMPFORCEABOVEVSS_MASK 0x0010 4206 #define PLL_AMPCONTROL_CONTROL_AMPFORCEABOVEVSS_ALIGN 0 4207 #define PLL_AMPCONTROL_CONTROL_AMPFORCEABOVEVSS_BITS 1 4208 #define PLL_AMPCONTROL_CONTROL_AMPFORCEABOVEVSS_SHIFT 4 4209 4210 /* PLL :: ampControl :: reserved0 [03:03] */ 4211 #define PLL_AMPCONTROL_CONTROL_RESERVED0_MASK 0x0008 4212 #define PLL_AMPCONTROL_CONTROL_RESERVED0_ALIGN 0 4213 #define PLL_AMPCONTROL_CONTROL_RESERVED0_BITS 1 4214 #define PLL_AMPCONTROL_CONTROL_RESERVED0_SHIFT 3 4215 4216 /* PLL :: ampControl :: ampForceSelectM [02:00] */ 4217 #define PLL_AMPCONTROL_CONTROL_AMPFORCESELECTM_MASK 0x0007 4218 #define PLL_AMPCONTROL_CONTROL_AMPFORCESELECTM_ALIGN 0 4219 #define PLL_AMPCONTROL_CONTROL_AMPFORCESELECTM_BITS 3 4220 #define PLL_AMPCONTROL_CONTROL_AMPFORCESELECTM_SHIFT 0 4221 4222 4223 4224 /**************************************************************************** 4225 * PLL :: freqDetCounter 4226 */ 4227 /* PLL :: freqDetCounter :: resolution [15:08] */ 4228 #define PLL_FREQDETCOUNTER_RESOLUTION_MASK 0xff00 4229 #define PLL_FREQDETCOUNTER_RESOLUTION_ALIGN 0 4230 #define PLL_FREQDETCOUNTER_RESOLUTION_BITS 8 4231 #define PLL_FREQDETCOUNTER_RESOLUTION_SHIFT 8 4232 4233 /* PLL :: freqDetCounter :: window [07:00] */ 4234 #define PLL_FREQDETCOUNTER_WINDOW_MASK 0x00ff 4235 #define PLL_FREQDETCOUNTER_WINDOW_ALIGN 0 4236 #define PLL_FREQDETCOUNTER_WINDOW_BITS 8 4237 #define PLL_FREQDETCOUNTER_WINDOW_SHIFT 0 4238 4239 4240 /**************************************************************************** 4241 * PLL :: pllAstatus1 4242 */ 4243 /* PLL :: pllAstatus1 :: reserved0 [15:14] */ 4244 #define PLL_PLLASTATUS1_RESERVED0_MASK 0xc000 4245 #define PLL_PLLASTATUS1_RESERVED0_ALIGN 0 4246 #define PLL_PLLASTATUS1_RESERVED0_BITS 2 4247 #define PLL_PLLASTATUS1_RESERVED0_SHIFT 14 4248 4249 /* PLL :: pllAstatus1 :: kvh [13:12] */ 4250 #define PLL_PLLASTATUS1_KVH_MASK 0x3000 4251 #define PLL_PLLASTATUS1_KVH_ALIGN 0 4252 #define PLL_PLLASTATUS1_KVH_BITS 2 4253 #define PLL_PLLASTATUS1_KVH_SHIFT 12 4254 4255 /* PLL :: pllAstatus1 :: pll_range [11:08] */ 4256 #define PLL_PLLASTATUS1_PLL_RANGE_MASK 0x0f00 4257 #define PLL_PLLASTATUS1_PLL_RANGE_ALIGN 0 4258 #define PLL_PLLASTATUS1_PLL_RANGE_BITS 4 4259 #define PLL_PLLASTATUS1_PLL_RANGE_SHIFT 8 4260 4261 /* PLL :: pllAstatus1 :: pll_low [07:07] */ 4262 #define PLL_PLLASTATUS1_PLL_LOW_MASK 0x0080 4263 #define PLL_PLLASTATUS1_PLL_LOW_ALIGN 0 4264 #define PLL_PLLASTATUS1_PLL_LOW_BITS 1 4265 #define PLL_PLLASTATUS1_PLL_LOW_SHIFT 7 4266 4267 /* PLL :: pllAstatus1 :: reserved1 [06:04] */ 4268 #define PLL_PLLASTATUS1_RESERVED1_MASK 0x0070 4269 #define PLL_PLLASTATUS1_RESERVED1_ALIGN 0 4270 #define PLL_PLLASTATUS1_RESERVED1_BITS 3 4271 #define PLL_PLLASTATUS1_RESERVED1_SHIFT 4 4272 4273 /* PLL :: pllAstatus1 :: pll_Ndiv [03:00] */ 4274 #define PLL_PLLASTATUS1_PLL_NDIV_MASK 0x000f 4275 #define PLL_PLLASTATUS1_PLL_NDIV_ALIGN 0 4276 #define PLL_PLLASTATUS1_PLL_NDIV_BITS 4 4277 #define PLL_PLLASTATUS1_PLL_NDIV_SHIFT 0 4278 4279 4280 /**************************************************************************** 4281 * PLL :: pllClockGen 4282 */ 4283 /* PLL :: pllClockGen :: refl_clken [15:15] */ 4284 #define PLL_PLLCLOCKGEN_REFL_CLKEN_MASK 0x8000 4285 #define PLL_PLLCLOCKGEN_REFL_CLKEN_ALIGN 0 4286 #define PLL_PLLCLOCKGEN_REFL_CLKEN_BITS 1 4287 #define PLL_PLLCLOCKGEN_REFL_CLKEN_SHIFT 15 4288 4289 /* PLL :: pllClockGen :: iclkidrv1 [14:12] */ 4290 #define PLL_PLLCLOCKGEN_ICLKIDRV1_MASK 0x7000 4291 #define PLL_PLLCLOCKGEN_ICLKIDRV1_ALIGN 0 4292 #define PLL_PLLCLOCKGEN_ICLKIDRV1_BITS 3 4293 #define PLL_PLLCLOCKGEN_ICLKIDRV1_SHIFT 12 4294 4295 /* PLL :: pllClockGen :: iclkodrv1 [11:09] */ 4296 #define PLL_PLLCLOCKGEN_ICLKODRV1_MASK 0x0e00 4297 #define PLL_PLLCLOCKGEN_ICLKODRV1_ALIGN 0 4298 #define PLL_PLLCLOCKGEN_ICLKODRV1_BITS 3 4299 #define PLL_PLLCLOCKGEN_ICLKODRV1_SHIFT 9 4300 4301 /* PLL :: pllClockGen :: iclkodrv2 [08:06] */ 4302 #define PLL_PLLCLOCKGEN_ICLKODRV2_MASK 0x01c0 4303 #define PLL_PLLCLOCKGEN_ICLKODRV2_ALIGN 0 4304 #define PLL_PLLCLOCKGEN_ICLKODRV2_BITS 3 4305 #define PLL_PLLCLOCKGEN_ICLKODRV2_SHIFT 6 4306 4307 /* PLL :: pllClockGen :: iclkidrv2 [05:03] */ 4308 #define PLL_PLLCLOCKGEN_ICLKIDRV2_MASK 0x0038 4309 #define PLL_PLLCLOCKGEN_ICLKIDRV2_ALIGN 0 4310 #define PLL_PLLCLOCKGEN_ICLKIDRV2_BITS 3 4311 #define PLL_PLLCLOCKGEN_ICLKIDRV2_SHIFT 3 4312 4313 /* PLL :: pllClockGen :: reserved0 [02:02] */ 4314 #define PLL_PLLCLOCKGEN_RESERVED0_MASK 0x0004 4315 #define PLL_PLLCLOCKGEN_RESERVED0_ALIGN 0 4316 #define PLL_PLLCLOCKGEN_RESERVED0_BITS 1 4317 #define PLL_PLLCLOCKGEN_RESERVED0_SHIFT 2 4318 4319 /* PLL :: pllClockGen :: vddr_bgb [01:01] */ 4320 #define PLL_PLLCLOCKGEN_VDDR_BGB_MASK 0x0002 4321 #define PLL_PLLCLOCKGEN_VDDR_BGB_ALIGN 0 4322 #define PLL_PLLCLOCKGEN_VDDR_BGB_BITS 1 4323 #define PLL_PLLCLOCKGEN_VDDR_BGB_SHIFT 1 4324 4325 /* PLL :: pllClockGen :: clksel_halfrate [00:00] */ 4326 #define PLL_PLLCLOCKGEN_CLKSEL_HALFRATE_MASK 0x0001 4327 #define PLL_PLLCLOCKGEN_CLKSEL_HALFRATE_ALIGN 0 4328 #define PLL_PLLCLOCKGEN_CLKSEL_HALFRATE_BITS 1 4329 #define PLL_PLLCLOCKGEN_CLKSEL_HALFRATE_SHIFT 0 4330 4331 4332 /**************************************************************************** 4333 * PLL :: pllNdiv 4334 */ 4335 /* PLL :: pllNdiv :: kvhce [15:15] */ 4336 #define PLL_PLLNDIV_KVHCE_MASK 0x8000 4337 #define PLL_PLLNDIV_KVHCE_ALIGN 0 4338 #define PLL_PLLNDIV_KVHCE_BITS 1 4339 #define PLL_PLLNDIV_KVHCE_SHIFT 15 4340 4341 /* PLL :: pllNdiv :: reserved0 [14:11] */ 4342 #define PLL_PLLNDIV_RESERVED0_MASK 0x7800 4343 #define PLL_PLLNDIV_RESERVED0_ALIGN 0 4344 #define PLL_PLLNDIV_RESERVED0_BITS 4 4345 #define PLL_PLLNDIV_RESERVED0_SHIFT 11 4346 4347 /* PLL :: pllNdiv :: iclkibuf4 [10:08] */ 4348 #define PLL_PLLNDIV_ICLKIBUF4_MASK 0x0700 4349 #define PLL_PLLNDIV_ICLKIBUF4_ALIGN 0 4350 #define PLL_PLLNDIV_ICLKIBUF4_BITS 3 4351 #define PLL_PLLNDIV_ICLKIBUF4_SHIFT 8 4352 4353 /* PLL :: pllNdiv :: ibias_all [07:05] */ 4354 #define PLL_PLLNDIV_IBIAS_ALL_MASK 0x00e0 4355 #define PLL_PLLNDIV_IBIAS_ALL_ALIGN 0 4356 #define PLL_PLLNDIV_IBIAS_ALL_BITS 3 4357 #define PLL_PLLNDIV_IBIAS_ALL_SHIFT 5 4358 4359 /* PLL :: pllNdiv :: refout_en [04:04] */ 4360 #define PLL_PLLNDIV_REFOUT_EN_MASK 0x0010 4361 #define PLL_PLLNDIV_REFOUT_EN_ALIGN 0 4362 #define PLL_PLLNDIV_REFOUT_EN_BITS 1 4363 #define PLL_PLLNDIV_REFOUT_EN_SHIFT 4 4364 4365 /* PLL :: pllNdiv :: refin_en [03:03] */ 4366 #define PLL_PLLNDIV_REFIN_EN_MASK 0x0008 4367 #define PLL_PLLNDIV_REFIN_EN_ALIGN 0 4368 #define PLL_PLLNDIV_REFIN_EN_BITS 1 4369 #define PLL_PLLNDIV_REFIN_EN_SHIFT 3 4370 4371 /* PLL :: pllNdiv :: pll2rx_clkbw [02:01] */ 4372 #define PLL_PLLNDIV_PLL2RX_CLKBW_MASK 0x0006 4373 #define PLL_PLLNDIV_PLL2RX_CLKBW_ALIGN 0 4374 #define PLL_PLLNDIV_PLL2RX_CLKBW_BITS 2 4375 #define PLL_PLLNDIV_PLL2RX_CLKBW_SHIFT 1 4376 4377 /* PLL :: pllNdiv :: refh_clkgen [00:00] */ 4378 #define PLL_PLLNDIV_REFH_CLKGEN_MASK 0x0001 4379 #define PLL_PLLNDIV_REFH_CLKGEN_ALIGN 0 4380 #define PLL_PLLNDIV_REFH_CLKGEN_BITS 1 4381 #define PLL_PLLNDIV_REFH_CLKGEN_SHIFT 0 4382 4383 4384 /**************************************************************************** 4385 * PLL :: pllBglqp 4386 */ 4387 /* PLL :: pllBglqp :: ick2 [15:15] */ 4388 #define PLL_PLLBGLQP_ICK2_MASK 0x8000 4389 #define PLL_PLLBGLQP_ICK2_ALIGN 0 4390 #define PLL_PLLBGLQP_ICK2_BITS 1 4391 #define PLL_PLLBGLQP_ICK2_SHIFT 15 4392 4393 /* PLL :: pllBglqp :: ick0 [14:14] */ 4394 #define PLL_PLLBGLQP_ICK0_MASK 0x4000 4395 #define PLL_PLLBGLQP_ICK0_ALIGN 0 4396 #define PLL_PLLBGLQP_ICK0_BITS 1 4397 #define PLL_PLLBGLQP_ICK0_SHIFT 14 4398 4399 /* PLL :: pllBglqp :: ick1 [13:13] */ 4400 #define PLL_PLLBGLQP_ICK1_MASK 0x2000 4401 #define PLL_PLLBGLQP_ICK1_ALIGN 0 4402 #define PLL_PLLBGLQP_ICK1_BITS 1 4403 #define PLL_PLLBGLQP_ICK1_SHIFT 13 4404 4405 /* PLL :: pllBglqp :: icp2 [12:12] */ 4406 #define PLL_PLLBGLQP_ICP2_MASK 0x1000 4407 #define PLL_PLLBGLQP_ICP2_ALIGN 0 4408 #define PLL_PLLBGLQP_ICP2_BITS 1 4409 #define PLL_PLLBGLQP_ICP2_SHIFT 12 4410 4411 /* PLL :: pllBglqp :: icp0 [11:11] */ 4412 #define PLL_PLLBGLQP_ICP0_MASK 0x0800 4413 #define PLL_PLLBGLQP_ICP0_ALIGN 0 4414 #define PLL_PLLBGLQP_ICP0_BITS 1 4415 #define PLL_PLLBGLQP_ICP0_SHIFT 11 4416 4417 /* PLL :: pllBglqp :: icp1 [10:10] */ 4418 #define PLL_PLLBGLQP_ICP1_MASK 0x0400 4419 #define PLL_PLLBGLQP_ICP1_ALIGN 0 4420 #define PLL_PLLBGLQP_ICP1_BITS 1 4421 #define PLL_PLLBGLQP_ICP1_SHIFT 10 4422 4423 /* PLL :: pllBglqp :: ibmax [09:09] */ 4424 #define PLL_PLLBGLQP_IBMAX_MASK 0x0200 4425 #define PLL_PLLBGLQP_IBMAX_ALIGN 0 4426 #define PLL_PLLBGLQP_IBMAX_BITS 1 4427 #define PLL_PLLBGLQP_IBMAX_SHIFT 9 4428 4429 /* PLL :: pllBglqp :: ibmode [08:08] */ 4430 #define PLL_PLLBGLQP_IBMODE_MASK 0x0100 4431 #define PLL_PLLBGLQP_IBMODE_ALIGN 0 4432 #define PLL_PLLBGLQP_IBMODE_BITS 1 4433 #define PLL_PLLBGLQP_IBMODE_SHIFT 8 4434 4435 /* PLL :: pllBglqp :: ibmin [07:07] */ 4436 #define PLL_PLLBGLQP_IBMIN_MASK 0x0080 4437 #define PLL_PLLBGLQP_IBMIN_ALIGN 0 4438 #define PLL_PLLBGLQP_IBMIN_BITS 1 4439 #define PLL_PLLBGLQP_IBMIN_SHIFT 7 4440 4441 /* PLL :: pllBglqp :: refh_pll [06:06] */ 4442 #define PLL_PLLBGLQP_REFH_PLL_MASK 0x0040 4443 #define PLL_PLLBGLQP_REFH_PLL_ALIGN 0 4444 #define PLL_PLLBGLQP_REFH_PLL_BITS 1 4445 #define PLL_PLLBGLQP_REFH_PLL_SHIFT 6 4446 4447 /* PLL :: pllBglqp :: refl_pll [05:05] */ 4448 #define PLL_PLLBGLQP_REFL_PLL_MASK 0x0020 4449 #define PLL_PLLBGLQP_REFL_PLL_ALIGN 0 4450 #define PLL_PLLBGLQP_REFL_PLL_BITS 1 4451 #define PLL_PLLBGLQP_REFL_PLL_SHIFT 5 4452 4453 /* PLL :: pllBglqp :: iqp [04:02] */ 4454 #define PLL_PLLBGLQP_IQP_MASK 0x001c 4455 #define PLL_PLLBGLQP_IQP_ALIGN 0 4456 #define PLL_PLLBGLQP_IQP_BITS 3 4457 #define PLL_PLLBGLQP_IQP_SHIFT 2 4458 4459 /* PLL :: pllBglqp :: en_p3 [01:01] */ 4460 #define PLL_PLLBGLQP_EN_P3_MASK 0x0002 4461 #define PLL_PLLBGLQP_EN_P3_ALIGN 0 4462 #define PLL_PLLBGLQP_EN_P3_BITS 1 4463 #define PLL_PLLBGLQP_EN_P3_SHIFT 1 4464 4465 /* PLL :: pllBglqp :: enable_ftune [00:00] */ 4466 #define PLL_PLLBGLQP_ENABLE_FTUNE_MASK 0x0001 4467 #define PLL_PLLBGLQP_ENABLE_FTUNE_ALIGN 0 4468 #define PLL_PLLBGLQP_ENABLE_FTUNE_BITS 1 4469 #define PLL_PLLBGLQP_ENABLE_FTUNE_SHIFT 0 4470 4471 4472 /**************************************************************************** 4473 * PLL :: pllTestKvh 4474 */ 4475 /* PLL :: pllTestKvh :: test_rx [15:15] */ 4476 #define PLL_PLLTESTKVH_TEST_RX_MASK 0x8000 4477 #define PLL_PLLTESTKVH_TEST_RX_ALIGN 0 4478 #define PLL_PLLTESTKVH_TEST_RX_BITS 1 4479 #define PLL_PLLTESTKVH_TEST_RX_SHIFT 15 4480 4481 /* PLL :: pllTestKvh :: test_pll [14:14] */ 4482 #define PLL_PLLTESTKVH_TEST_PLL_MASK 0x4000 4483 #define PLL_PLLTESTKVH_TEST_PLL_ALIGN 0 4484 #define PLL_PLLTESTKVH_TEST_PLL_BITS 1 4485 #define PLL_PLLTESTKVH_TEST_PLL_SHIFT 14 4486 4487 /* PLL :: pllTestKvh :: test_vc [13:13] */ 4488 #define PLL_PLLTESTKVH_TEST_VC_MASK 0x2000 4489 #define PLL_PLLTESTKVH_TEST_VC_ALIGN 0 4490 #define PLL_PLLTESTKVH_TEST_VC_BITS 1 4491 #define PLL_PLLTESTKVH_TEST_VC_SHIFT 13 4492 4493 /* PLL :: pllTestKvh :: test_vref [12:12] */ 4494 #define PLL_PLLTESTKVH_TEST_VREF_MASK 0x1000 4495 #define PLL_PLLTESTKVH_TEST_VREF_ALIGN 0 4496 #define PLL_PLLTESTKVH_TEST_VREF_BITS 1 4497 #define PLL_PLLTESTKVH_TEST_VREF_SHIFT 12 4498 4499 /* PLL :: pllTestKvh :: iop2 [11:11] */ 4500 #define PLL_PLLTESTKVH_IOP2_MASK 0x0800 4501 #define PLL_PLLTESTKVH_IOP2_ALIGN 0 4502 #define PLL_PLLTESTKVH_IOP2_BITS 1 4503 #define PLL_PLLTESTKVH_IOP2_SHIFT 11 4504 4505 /* PLL :: pllTestKvh :: iop0 [10:10] */ 4506 #define PLL_PLLTESTKVH_IOP0_MASK 0x0400 4507 #define PLL_PLLTESTKVH_IOP0_ALIGN 0 4508 #define PLL_PLLTESTKVH_IOP0_BITS 1 4509 #define PLL_PLLTESTKVH_IOP0_SHIFT 10 4510 4511 /* PLL :: pllTestKvh :: iop1 [09:09] */ 4512 #define PLL_PLLTESTKVH_IOP1_MASK 0x0200 4513 #define PLL_PLLTESTKVH_IOP1_ALIGN 0 4514 #define PLL_PLLTESTKVH_IOP1_BITS 1 4515 #define PLL_PLLTESTKVH_IOP1_SHIFT 9 4516 4517 /* PLL :: pllTestKvh :: icomp2 [08:08] */ 4518 #define PLL_PLLTESTKVH_ICOMP2_MASK 0x0100 4519 #define PLL_PLLTESTKVH_ICOMP2_ALIGN 0 4520 #define PLL_PLLTESTKVH_ICOMP2_BITS 1 4521 #define PLL_PLLTESTKVH_ICOMP2_SHIFT 8 4522 4523 /* PLL :: pllTestKvh :: icomp0 [07:07] */ 4524 #define PLL_PLLTESTKVH_ICOMP0_MASK 0x0080 4525 #define PLL_PLLTESTKVH_ICOMP0_ALIGN 0 4526 #define PLL_PLLTESTKVH_ICOMP0_BITS 1 4527 #define PLL_PLLTESTKVH_ICOMP0_SHIFT 7 4528 4529 /* PLL :: pllTestKvh :: icomp1 [06:06] */ 4530 #define PLL_PLLTESTKVH_ICOMP1_MASK 0x0040 4531 #define PLL_PLLTESTKVH_ICOMP1_ALIGN 0 4532 #define PLL_PLLTESTKVH_ICOMP1_BITS 1 4533 #define PLL_PLLTESTKVH_ICOMP1_SHIFT 6 4534 4535 /* PLL :: pllTestKvh :: icml2 [05:05] */ 4536 #define PLL_PLLTESTKVH_ICML2_MASK 0x0020 4537 #define PLL_PLLTESTKVH_ICML2_ALIGN 0 4538 #define PLL_PLLTESTKVH_ICML2_BITS 1 4539 #define PLL_PLLTESTKVH_ICML2_SHIFT 5 4540 4541 /* PLL :: pllTestKvh :: icml0 [04:04] */ 4542 #define PLL_PLLTESTKVH_ICML0_MASK 0x0010 4543 #define PLL_PLLTESTKVH_ICML0_ALIGN 0 4544 #define PLL_PLLTESTKVH_ICML0_BITS 1 4545 #define PLL_PLLTESTKVH_ICML0_SHIFT 4 4546 4547 /* PLL :: pllTestKvh :: icml1 [03:03] */ 4548 #define PLL_PLLTESTKVH_ICML1_MASK 0x0008 4549 #define PLL_PLLTESTKVH_ICML1_ALIGN 0 4550 #define PLL_PLLTESTKVH_ICML1_BITS 1 4551 #define PLL_PLLTESTKVH_ICML1_SHIFT 3 4552 4553 /* PLL :: pllTestKvh :: ivco2 [02:02] */ 4554 #define PLL_PLLTESTKVH_IVCO2_MASK 0x0004 4555 #define PLL_PLLTESTKVH_IVCO2_ALIGN 0 4556 #define PLL_PLLTESTKVH_IVCO2_BITS 1 4557 #define PLL_PLLTESTKVH_IVCO2_SHIFT 2 4558 4559 /* PLL :: pllTestKvh :: ivco0 [01:01] */ 4560 #define PLL_PLLTESTKVH_IVCO0_MASK 0x0002 4561 #define PLL_PLLTESTKVH_IVCO0_ALIGN 0 4562 #define PLL_PLLTESTKVH_IVCO0_BITS 1 4563 #define PLL_PLLTESTKVH_IVCO0_SHIFT 1 4564 4565 /* PLL :: pllTestKvh :: ivco1 [00:00] */ 4566 #define PLL_PLLTESTKVH_IVCO1_MASK 0x0001 4567 #define PLL_PLLTESTKVH_IVCO1_ALIGN 0 4568 #define PLL_PLLTESTKVH_IVCO1_BITS 1 4569 #define PLL_PLLTESTKVH_IVCO1_SHIFT 0 4570 4571 4572 /**************************************************************************** 4573 * PLL :: pllAcontrol5 4574 */ 4575 /* PLL :: pllAcontrol5 :: en65G [15:15] */ 4576 #define PLL_PLLACONTROL5_EN65G_MASK 0x8000 4577 #define PLL_PLLACONTROL5_EN65G_ALIGN 0 4578 #define PLL_PLLACONTROL5_EN65G_BITS 1 4579 #define PLL_PLLACONTROL5_EN65G_SHIFT 15 4580 4581 /* PLL :: pllAcontrol5 :: reserved0 [14:12] */ 4582 #define PLL_PLLACONTROL5_RESERVED0_MASK 0x7000 4583 #define PLL_PLLACONTROL5_RESERVED0_ALIGN 0 4584 #define PLL_PLLACONTROL5_RESERVED0_BITS 3 4585 #define PLL_PLLACONTROL5_RESERVED0_SHIFT 12 4586 4587 /* PLL :: pllAcontrol5 :: vddr_bgb [11:11] */ 4588 #define PLL_PLLACONTROL5_VDDR_BGB_MASK 0x0800 4589 #define PLL_PLLACONTROL5_VDDR_BGB_ALIGN 0 4590 #define PLL_PLLACONTROL5_VDDR_BGB_BITS 1 4591 #define PLL_PLLACONTROL5_VDDR_BGB_SHIFT 11 4592 4593 /* PLL :: pllAcontrol5 :: comp_vth [10:10] */ 4594 #define PLL_PLLACONTROL5_COMP_VTH_MASK 0x0400 4595 #define PLL_PLLACONTROL5_COMP_VTH_ALIGN 0 4596 #define PLL_PLLACONTROL5_COMP_VTH_BITS 1 4597 #define PLL_PLLACONTROL5_COMP_VTH_SHIFT 10 4598 4599 /* PLL :: pllAcontrol5 :: actrl [09:08] */ 4600 #define PLL_PLLACONTROL5_ACTRL_MASK 0x0300 4601 #define PLL_PLLACONTROL5_ACTRL_ALIGN 0 4602 #define PLL_PLLACONTROL5_ACTRL_BITS 2 4603 #define PLL_PLLACONTROL5_ACTRL_SHIFT 8 4604 4605 /* PLL :: pllAcontrol5 :: ctatadj [07:04] */ 4606 #define PLL_PLLACONTROL5_CTATADJ_MASK 0x00f0 4607 #define PLL_PLLACONTROL5_CTATADJ_ALIGN 0 4608 #define PLL_PLLACONTROL5_CTATADJ_BITS 4 4609 #define PLL_PLLACONTROL5_CTATADJ_SHIFT 4 4610 4611 /* PLL :: pllAcontrol5 :: ptatadj [03:00] */ 4612 #define PLL_PLLACONTROL5_PTATADJ_MASK 0x000f 4613 #define PLL_PLLACONTROL5_PTATADJ_ALIGN 0 4614 #define PLL_PLLACONTROL5_PTATADJ_BITS 4 4615 #define PLL_PLLACONTROL5_PTATADJ_SHIFT 0 4616 4617 4618 /**************************************************************************** 4619 * XGXS16G_USER_TX0 4620 */ 4621 /**************************************************************************** 4622 * TX0 :: Tx_AStatus0 4623 */ 4624 /* TX0 :: Tx_AStatus0 :: reserved0 [15:03] */ 4625 #define TX0_TX_ASTATUS0_RESERVED0_MASK 0xfff8 4626 #define TX0_TX_ASTATUS0_RESERVED0_ALIGN 0 4627 #define TX0_TX_ASTATUS0_RESERVED0_BITS 13 4628 #define TX0_TX_ASTATUS0_RESERVED0_SHIFT 3 4629 4630 /* TX0 :: Tx_AStatus0 :: tx_gloopback [02:02] */ 4631 #define TX0_TX_ASTATUS0_TX_GLOOPBACK_MASK 0x0004 4632 #define TX0_TX_ASTATUS0_TX_GLOOPBACK_ALIGN 0 4633 #define TX0_TX_ASTATUS0_TX_GLOOPBACK_BITS 1 4634 #define TX0_TX_ASTATUS0_TX_GLOOPBACK_SHIFT 2 4635 4636 /* TX0 :: Tx_AStatus0 :: rltxferr [01:01] */ 4637 #define TX0_TX_ASTATUS0_RLTXFERR_MASK 0x0002 4638 #define TX0_TX_ASTATUS0_RLTXFERR_ALIGN 0 4639 #define TX0_TX_ASTATUS0_RLTXFERR_BITS 1 4640 #define TX0_TX_ASTATUS0_RLTXFERR_SHIFT 1 4641 4642 /* TX0 :: Tx_AStatus0 :: txferr [00:00] */ 4643 #define TX0_TX_ASTATUS0_TXFERR_MASK 0x0001 4644 #define TX0_TX_ASTATUS0_TXFERR_ALIGN 0 4645 #define TX0_TX_ASTATUS0_TXFERR_BITS 1 4646 #define TX0_TX_ASTATUS0_TXFERR_SHIFT 0 4647 4648 4649 /**************************************************************************** 4650 * TX0 :: Tx_AControl0 4651 */ 4652 /* TX0 :: Tx_AControl0 :: reserved0 [15:15] */ 4653 #define TX0_TX_ACONTROL0_RESERVED0_MASK 0x8000 4654 #define TX0_TX_ACONTROL0_RESERVED0_ALIGN 0 4655 #define TX0_TX_ACONTROL0_RESERVED0_BITS 1 4656 #define TX0_TX_ACONTROL0_RESERVED0_SHIFT 15 4657 4658 /* TX0 :: Tx_AControl0 :: force_txclk [14:14] */ 4659 #define TX0_TX_ACONTROL0_FORCE_TXCLK_MASK 0x4000 4660 #define TX0_TX_ACONTROL0_FORCE_TXCLK_ALIGN 0 4661 #define TX0_TX_ACONTROL0_FORCE_TXCLK_BITS 1 4662 #define TX0_TX_ACONTROL0_FORCE_TXCLK_SHIFT 14 4663 4664 /* TX0 :: Tx_AControl0 :: tx1g_fifo_rst [13:13] */ 4665 #define TX0_TX_ACONTROL0_TX1G_FIFO_RST_MASK 0x2000 4666 #define TX0_TX_ACONTROL0_TX1G_FIFO_RST_ALIGN 0 4667 #define TX0_TX_ACONTROL0_TX1G_FIFO_RST_BITS 1 4668 #define TX0_TX_ACONTROL0_TX1G_FIFO_RST_SHIFT 13 4669 4670 /* TX0 :: Tx_AControl0 :: gloopOutEn [12:12] */ 4671 #define TX0_TX_ACONTROL0_GLOOPOUTEN_MASK 0x1000 4672 #define TX0_TX_ACONTROL0_GLOOPOUTEN_ALIGN 0 4673 #define TX0_TX_ACONTROL0_GLOOPOUTEN_BITS 1 4674 #define TX0_TX_ACONTROL0_GLOOPOUTEN_SHIFT 12 4675 4676 /* TX0 :: Tx_AControl0 :: reserved1 [11:09] */ 4677 #define TX0_TX_ACONTROL0_RESERVED1_MASK 0x0e00 4678 #define TX0_TX_ACONTROL0_RESERVED1_ALIGN 0 4679 #define TX0_TX_ACONTROL0_RESERVED1_BITS 3 4680 #define TX0_TX_ACONTROL0_RESERVED1_SHIFT 9 4681 4682 /* TX0 :: Tx_AControl0 :: prbs_en [08:08] */ 4683 #define TX0_TX_ACONTROL0_PRBS_EN_MASK 0x0100 4684 #define TX0_TX_ACONTROL0_PRBS_EN_ALIGN 0 4685 #define TX0_TX_ACONTROL0_PRBS_EN_BITS 1 4686 #define TX0_TX_ACONTROL0_PRBS_EN_SHIFT 8 4687 4688 /* TX0 :: Tx_AControl0 :: pckt_en [07:07] */ 4689 #define TX0_TX_ACONTROL0_PCKT_EN_MASK 0x0080 4690 #define TX0_TX_ACONTROL0_PCKT_EN_ALIGN 0 4691 #define TX0_TX_ACONTROL0_PCKT_EN_BITS 1 4692 #define TX0_TX_ACONTROL0_PCKT_EN_SHIFT 7 4693 4694 /* TX0 :: Tx_AControl0 :: pckt_strt [06:06] */ 4695 #define TX0_TX_ACONTROL0_PCKT_STRT_MASK 0x0040 4696 #define TX0_TX_ACONTROL0_PCKT_STRT_ALIGN 0 4697 #define TX0_TX_ACONTROL0_PCKT_STRT_BITS 1 4698 #define TX0_TX_ACONTROL0_PCKT_STRT_SHIFT 6 4699 4700 /* TX0 :: Tx_AControl0 :: txpol_flip [05:05] */ 4701 #define TX0_TX_ACONTROL0_TXPOL_FLIP_MASK 0x0020 4702 #define TX0_TX_ACONTROL0_TXPOL_FLIP_ALIGN 0 4703 #define TX0_TX_ACONTROL0_TXPOL_FLIP_BITS 1 4704 #define TX0_TX_ACONTROL0_TXPOL_FLIP_SHIFT 5 4705 4706 /* TX0 :: Tx_AControl0 :: rtbi_flip [04:04] */ 4707 #define TX0_TX_ACONTROL0_RTBI_FLIP_MASK 0x0010 4708 #define TX0_TX_ACONTROL0_RTBI_FLIP_ALIGN 0 4709 #define TX0_TX_ACONTROL0_RTBI_FLIP_BITS 1 4710 #define TX0_TX_ACONTROL0_RTBI_FLIP_SHIFT 4 4711 4712 /* TX0 :: Tx_AControl0 :: eden_r [03:03] */ 4713 #define TX0_TX_ACONTROL0_EDEN_R_MASK 0x0008 4714 #define TX0_TX_ACONTROL0_EDEN_R_ALIGN 0 4715 #define TX0_TX_ACONTROL0_EDEN_R_BITS 1 4716 #define TX0_TX_ACONTROL0_EDEN_R_SHIFT 3 4717 4718 /* TX0 :: Tx_AControl0 :: eden_force_r [02:02] */ 4719 #define TX0_TX_ACONTROL0_EDEN_FORCE_R_MASK 0x0004 4720 #define TX0_TX_ACONTROL0_EDEN_FORCE_R_ALIGN 0 4721 #define TX0_TX_ACONTROL0_EDEN_FORCE_R_BITS 1 4722 #define TX0_TX_ACONTROL0_EDEN_FORCE_R_SHIFT 2 4723 4724 /* TX0 :: Tx_AControl0 :: txpat_en [01:01] */ 4725 #define TX0_TX_ACONTROL0_TXPAT_EN_MASK 0x0002 4726 #define TX0_TX_ACONTROL0_TXPAT_EN_ALIGN 0 4727 #define TX0_TX_ACONTROL0_TXPAT_EN_BITS 1 4728 #define TX0_TX_ACONTROL0_TXPAT_EN_SHIFT 1 4729 4730 /* TX0 :: Tx_AControl0 :: tx_mdata_en [00:00] */ 4731 #define TX0_TX_ACONTROL0_TX_MDATA_EN_MASK 0x0001 4732 #define TX0_TX_ACONTROL0_TX_MDATA_EN_ALIGN 0 4733 #define TX0_TX_ACONTROL0_TX_MDATA_EN_BITS 1 4734 #define TX0_TX_ACONTROL0_TX_MDATA_EN_SHIFT 0 4735 4736 4737 /**************************************************************************** 4738 * TX0 :: Tx_mdata0 4739 */ 4740 /* TX0 :: Tx_mdata0 :: txTestMuxSel [15:13] */ 4741 #define TX0_TX_MDATA0_TXTESTMUXSEL_MASK 0xe000 4742 #define TX0_TX_MDATA0_TXTESTMUXSEL_ALIGN 0 4743 #define TX0_TX_MDATA0_TXTESTMUXSEL_BITS 3 4744 #define TX0_TX_MDATA0_TXTESTMUXSEL_SHIFT 13 4745 4746 /* TX0 :: Tx_mdata0 :: rlfifo_tstsel [12:10] */ 4747 #define TX0_TX_MDATA0_RLFIFO_TSTSEL_MASK 0x1c00 4748 #define TX0_TX_MDATA0_RLFIFO_TSTSEL_ALIGN 0 4749 #define TX0_TX_MDATA0_RLFIFO_TSTSEL_BITS 3 4750 #define TX0_TX_MDATA0_RLFIFO_TSTSEL_SHIFT 10 4751 4752 /* TX0 :: Tx_mdata0 :: TxMdioTstDataL [09:00] */ 4753 #define TX0_TX_MDATA0_TXMDIOTSTDATAL_MASK 0x03ff 4754 #define TX0_TX_MDATA0_TXMDIOTSTDATAL_ALIGN 0 4755 #define TX0_TX_MDATA0_TXMDIOTSTDATAL_BITS 10 4756 #define TX0_TX_MDATA0_TXMDIOTSTDATAL_SHIFT 0 4757 4758 4759 /**************************************************************************** 4760 * TX0 :: Tx_mdata1 4761 */ 4762 /* TX0 :: Tx_mdata1 :: reserved0 [15:10] */ 4763 #define TX0_TX_MDATA1_RESERVED0_MASK 0xfc00 4764 #define TX0_TX_MDATA1_RESERVED0_ALIGN 0 4765 #define TX0_TX_MDATA1_RESERVED0_BITS 6 4766 #define TX0_TX_MDATA1_RESERVED0_SHIFT 10 4767 4768 /* TX0 :: Tx_mdata1 :: TxMdioTstDataH [09:00] */ 4769 #define TX0_TX_MDATA1_TXMDIOTSTDATAH_MASK 0x03ff 4770 #define TX0_TX_MDATA1_TXMDIOTSTDATAH_ALIGN 0 4771 #define TX0_TX_MDATA1_TXMDIOTSTDATAH_BITS 10 4772 #define TX0_TX_MDATA1_TXMDIOTSTDATAH_SHIFT 0 4773 4774 4775 /**************************************************************************** 4776 * TX0 :: Tx_AStatus1 4777 */ 4778 /* TX0 :: Tx_AStatus1 :: tx_id [15:14] */ 4779 #define TX0_TX_ASTATUS1_TX_ID_MASK 0xc000 4780 #define TX0_TX_ASTATUS1_TX_ID_ALIGN 0 4781 #define TX0_TX_ASTATUS1_TX_ID_BITS 2 4782 #define TX0_TX_ASTATUS1_TX_ID_SHIFT 14 4783 4784 /* TX0 :: Tx_AStatus1 :: reserved0 [13:00] */ 4785 #define TX0_TX_ASTATUS1_RESERVED0_MASK 0x3fff 4786 #define TX0_TX_ASTATUS1_RESERVED0_ALIGN 0 4787 #define TX0_TX_ASTATUS1_RESERVED0_BITS 14 4788 #define TX0_TX_ASTATUS1_RESERVED0_SHIFT 0 4789 4790 4791 /**************************************************************************** 4792 * TX0 :: Tx_BgVcm 4793 */ 4794 /* TX0 :: Tx_BgVcm :: id2c [15:13] */ 4795 #define TX0_TX_BGVCM_ID2C_MASK 0xe000 4796 #define TX0_TX_BGVCM_ID2C_ALIGN 0 4797 #define TX0_TX_BGVCM_ID2C_BITS 3 4798 #define TX0_TX_BGVCM_ID2C_SHIFT 13 4799 4800 /* TX0 :: Tx_BgVcm :: refl_tx [12:12] */ 4801 #define TX0_TX_BGVCM_REFL_TX_MASK 0x1000 4802 #define TX0_TX_BGVCM_REFL_TX_ALIGN 0 4803 #define TX0_TX_BGVCM_REFL_TX_BITS 1 4804 #define TX0_TX_BGVCM_REFL_TX_SHIFT 12 4805 4806 /* TX0 :: Tx_BgVcm :: refh_tx [11:11] */ 4807 #define TX0_TX_BGVCM_REFH_TX_MASK 0x0800 4808 #define TX0_TX_BGVCM_REFH_TX_ALIGN 0 4809 #define TX0_TX_BGVCM_REFH_TX_BITS 1 4810 #define TX0_TX_BGVCM_REFH_TX_SHIFT 11 4811 4812 /* TX0 :: Tx_BgVcm :: newbias_en [10:10] */ 4813 #define TX0_TX_BGVCM_NEWBIAS_EN_MASK 0x0400 4814 #define TX0_TX_BGVCM_NEWBIAS_EN_ALIGN 0 4815 #define TX0_TX_BGVCM_NEWBIAS_EN_BITS 1 4816 #define TX0_TX_BGVCM_NEWBIAS_EN_SHIFT 10 4817 4818 /* TX0 :: Tx_BgVcm :: drivermode [09:09] */ 4819 #define TX0_TX_BGVCM_DRIVERMODE_MASK 0x0200 4820 #define TX0_TX_BGVCM_DRIVERMODE_ALIGN 0 4821 #define TX0_TX_BGVCM_DRIVERMODE_BITS 1 4822 #define TX0_TX_BGVCM_DRIVERMODE_SHIFT 9 4823 4824 /* TX0 :: Tx_BgVcm :: bddr_bgb [08:08] */ 4825 #define TX0_TX_BGVCM_BDDR_BGB_MASK 0x0100 4826 #define TX0_TX_BGVCM_BDDR_BGB_ALIGN 0 4827 #define TX0_TX_BGVCM_BDDR_BGB_BITS 1 4828 #define TX0_TX_BGVCM_BDDR_BGB_SHIFT 8 4829 4830 /* TX0 :: Tx_BgVcm :: ticksel [07:06] */ 4831 #define TX0_TX_BGVCM_TICKSEL_MASK 0x00c0 4832 #define TX0_TX_BGVCM_TICKSEL_ALIGN 0 4833 #define TX0_TX_BGVCM_TICKSEL_BITS 2 4834 #define TX0_TX_BGVCM_TICKSEL_SHIFT 6 4835 4836 /* TX0 :: Tx_BgVcm :: driver_vcm [05:04] */ 4837 #define TX0_TX_BGVCM_DRIVER_VCM_MASK 0x0030 4838 #define TX0_TX_BGVCM_DRIVER_VCM_ALIGN 0 4839 #define TX0_TX_BGVCM_DRIVER_VCM_BITS 2 4840 #define TX0_TX_BGVCM_DRIVER_VCM_SHIFT 4 4841 4842 /* TX0 :: Tx_BgVcm :: tx_sel_halfrate [03:03] */ 4843 #define TX0_TX_BGVCM_TX_SEL_HALFRATE_MASK 0x0008 4844 #define TX0_TX_BGVCM_TX_SEL_HALFRATE_ALIGN 0 4845 #define TX0_TX_BGVCM_TX_SEL_HALFRATE_BITS 1 4846 #define TX0_TX_BGVCM_TX_SEL_HALFRATE_SHIFT 3 4847 4848 /* TX0 :: Tx_BgVcm :: ifullspd [02:00] */ 4849 #define TX0_TX_BGVCM_IFULLSPD_MASK 0x0007 4850 #define TX0_TX_BGVCM_IFULLSPD_ALIGN 0 4851 #define TX0_TX_BGVCM_IFULLSPD_BITS 3 4852 #define TX0_TX_BGVCM_IFULLSPD_SHIFT 0 4853 4854 4855 /**************************************************************************** 4856 * TX0 :: Tx_ibuff_1T2T 4857 */ 4858 /* TX0 :: Tx_ibuff_1T2T :: icbuf1t [15:14] */ 4859 #define TX0_TX_IBUFF_1T2T_ICBUF1T_MASK 0xc000 4860 #define TX0_TX_IBUFF_1T2T_ICBUF1T_ALIGN 0 4861 #define TX0_TX_IBUFF_1T2T_ICBUF1T_BITS 2 4862 #define TX0_TX_IBUFF_1T2T_ICBUF1T_SHIFT 14 4863 4864 /* TX0 :: Tx_ibuff_1T2T :: icbuf2t [13:11] */ 4865 #define TX0_TX_IBUFF_1T2T_ICBUF2T_MASK 0x3800 4866 #define TX0_TX_IBUFF_1T2T_ICBUF2T_ALIGN 0 4867 #define TX0_TX_IBUFF_1T2T_ICBUF2T_BITS 3 4868 #define TX0_TX_IBUFF_1T2T_ICBUF2T_SHIFT 11 4869 4870 /* TX0 :: Tx_ibuff_1T2T :: imin_predrv [10:10] */ 4871 #define TX0_TX_IBUFF_1T2T_IMIN_PREDRV_MASK 0x0400 4872 #define TX0_TX_IBUFF_1T2T_IMIN_PREDRV_ALIGN 0 4873 #define TX0_TX_IBUFF_1T2T_IMIN_PREDRV_BITS 1 4874 #define TX0_TX_IBUFF_1T2T_IMIN_PREDRV_SHIFT 10 4875 4876 /* TX0 :: Tx_ibuff_1T2T :: imax_predrv [09:09] */ 4877 #define TX0_TX_IBUFF_1T2T_IMAX_PREDRV_MASK 0x0200 4878 #define TX0_TX_IBUFF_1T2T_IMAX_PREDRV_ALIGN 0 4879 #define TX0_TX_IBUFF_1T2T_IMAX_PREDRV_BITS 1 4880 #define TX0_TX_IBUFF_1T2T_IMAX_PREDRV_SHIFT 9 4881 4882 /* TX0 :: Tx_ibuff_1T2T :: imode_predrv [08:08] */ 4883 #define TX0_TX_IBUFF_1T2T_IMODE_PREDRV_MASK 0x0100 4884 #define TX0_TX_IBUFF_1T2T_IMODE_PREDRV_ALIGN 0 4885 #define TX0_TX_IBUFF_1T2T_IMODE_PREDRV_BITS 1 4886 #define TX0_TX_IBUFF_1T2T_IMODE_PREDRV_SHIFT 8 4887 4888 /* TX0 :: Tx_ibuff_1T2T :: i21mux [07:05] */ 4889 #define TX0_TX_IBUFF_1T2T_I21MUX_MASK 0x00e0 4890 #define TX0_TX_IBUFF_1T2T_I21MUX_ALIGN 0 4891 #define TX0_TX_IBUFF_1T2T_I21MUX_BITS 3 4892 #define TX0_TX_IBUFF_1T2T_I21MUX_SHIFT 5 4893 4894 /* TX0 :: Tx_ibuff_1T2T :: imin_drvr [04:04] */ 4895 #define TX0_TX_IBUFF_1T2T_IMIN_DRVR_MASK 0x0010 4896 #define TX0_TX_IBUFF_1T2T_IMIN_DRVR_ALIGN 0 4897 #define TX0_TX_IBUFF_1T2T_IMIN_DRVR_BITS 1 4898 #define TX0_TX_IBUFF_1T2T_IMIN_DRVR_SHIFT 4 4899 4900 /* TX0 :: Tx_ibuff_1T2T :: imax_drvr [03:03] */ 4901 #define TX0_TX_IBUFF_1T2T_IMAX_DRVR_MASK 0x0008 4902 #define TX0_TX_IBUFF_1T2T_IMAX_DRVR_ALIGN 0 4903 #define TX0_TX_IBUFF_1T2T_IMAX_DRVR_BITS 1 4904 #define TX0_TX_IBUFF_1T2T_IMAX_DRVR_SHIFT 3 4905 4906 /* TX0 :: Tx_ibuff_1T2T :: imode_drvr [02:02] */ 4907 #define TX0_TX_IBUFF_1T2T_IMODE_DRVR_MASK 0x0004 4908 #define TX0_TX_IBUFF_1T2T_IMODE_DRVR_ALIGN 0 4909 #define TX0_TX_IBUFF_1T2T_IMODE_DRVR_BITS 1 4910 #define TX0_TX_IBUFF_1T2T_IMODE_DRVR_SHIFT 2 4911 4912 /* TX0 :: Tx_ibuff_1T2T :: reserved0 [01:00] */ 4913 #define TX0_TX_IBUFF_1T2T_RESERVED0_MASK 0x0003 4914 #define TX0_TX_IBUFF_1T2T_RESERVED0_ALIGN 0 4915 #define TX0_TX_IBUFF_1T2T_RESERVED0_BITS 2 4916 #define TX0_TX_IBUFF_1T2T_RESERVED0_SHIFT 0 4917 4918 4919 /**************************************************************************** 4920 * TX0 :: Tx_Driver 4921 */ 4922 /* TX0 :: Tx_Driver :: preemphasis_post [15:12] */ 4923 #define TX0_TX_DRIVER_PREEMPHASIS_POST_MASK 0xf000 4924 #define TX0_TX_DRIVER_PREEMPHASIS_POST_ALIGN 0 4925 #define TX0_TX_DRIVER_PREEMPHASIS_POST_BITS 4 4926 #define TX0_TX_DRIVER_PREEMPHASIS_POST_SHIFT 12 4927 4928 /* TX0 :: Tx_Driver :: Idriver [11:08] */ 4929 #define TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 4930 #define TX0_TX_DRIVER_IDRIVER_ALIGN 0 4931 #define TX0_TX_DRIVER_IDRIVER_BITS 4 4932 #define TX0_TX_DRIVER_IDRIVER_SHIFT 8 4933 4934 /* TX0 :: Tx_Driver :: Ipredriver [07:04] */ 4935 #define TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 4936 #define TX0_TX_DRIVER_IPREDRIVER_ALIGN 0 4937 #define TX0_TX_DRIVER_IPREDRIVER_BITS 4 4938 #define TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 4939 4940 /* TX0 :: Tx_Driver :: preemphasis_pre [03:01] */ 4941 #define TX0_TX_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 4942 #define TX0_TX_DRIVER_PREEMPHASIS_PRE_ALIGN 0 4943 #define TX0_TX_DRIVER_PREEMPHASIS_PRE_BITS 3 4944 #define TX0_TX_DRIVER_PREEMPHASIS_PRE_SHIFT 1 4945 4946 /* TX0 :: Tx_Driver :: icbuf1t0 [00:00] */ 4947 #define TX0_TX_DRIVER_ICBUF1T0_MASK 0x0001 4948 #define TX0_TX_DRIVER_ICBUF1T0_ALIGN 0 4949 #define TX0_TX_DRIVER_ICBUF1T0_BITS 1 4950 #define TX0_TX_DRIVER_ICBUF1T0_SHIFT 0 4951 4952 4953 /**************************************************************************** 4954 * XGXS16G_USER_TX1 4955 */ 4956 /**************************************************************************** 4957 * TX1 :: Tx_AStatus0 4958 */ 4959 /* TX1 :: Tx_AStatus0 :: reserved0 [15:03] */ 4960 #define TX1_TX_ASTATUS0_RESERVED0_MASK 0xfff8 4961 #define TX1_TX_ASTATUS0_RESERVED0_ALIGN 0 4962 #define TX1_TX_ASTATUS0_RESERVED0_BITS 13 4963 #define TX1_TX_ASTATUS0_RESERVED0_SHIFT 3 4964 4965 /* TX1 :: Tx_AStatus0 :: tx_gloopback [02:02] */ 4966 #define TX1_TX_ASTATUS0_TX_GLOOPBACK_MASK 0x0004 4967 #define TX1_TX_ASTATUS0_TX_GLOOPBACK_ALIGN 0 4968 #define TX1_TX_ASTATUS0_TX_GLOOPBACK_BITS 1 4969 #define TX1_TX_ASTATUS0_TX_GLOOPBACK_SHIFT 2 4970 4971 /* TX1 :: Tx_AStatus0 :: rltxferr [01:01] */ 4972 #define TX1_TX_ASTATUS0_RLTXFERR_MASK 0x0002 4973 #define TX1_TX_ASTATUS0_RLTXFERR_ALIGN 0 4974 #define TX1_TX_ASTATUS0_RLTXFERR_BITS 1 4975 #define TX1_TX_ASTATUS0_RLTXFERR_SHIFT 1 4976 4977 /* TX1 :: Tx_AStatus0 :: txferr [00:00] */ 4978 #define TX1_TX_ASTATUS0_TXFERR_MASK 0x0001 4979 #define TX1_TX_ASTATUS0_TXFERR_ALIGN 0 4980 #define TX1_TX_ASTATUS0_TXFERR_BITS 1 4981 #define TX1_TX_ASTATUS0_TXFERR_SHIFT 0 4982 4983 4984 /**************************************************************************** 4985 * TX1 :: Tx_AControl0 4986 */ 4987 /* TX1 :: Tx_AControl0 :: reserved0 [15:15] */ 4988 #define TX1_TX_ACONTROL0_RESERVED0_MASK 0x8000 4989 #define TX1_TX_ACONTROL0_RESERVED0_ALIGN 0 4990 #define TX1_TX_ACONTROL0_RESERVED0_BITS 1 4991 #define TX1_TX_ACONTROL0_RESERVED0_SHIFT 15 4992 4993 /* TX1 :: Tx_AControl0 :: force_txclk [14:14] */ 4994 #define TX1_TX_ACONTROL0_FORCE_TXCLK_MASK 0x4000 4995 #define TX1_TX_ACONTROL0_FORCE_TXCLK_ALIGN 0 4996 #define TX1_TX_ACONTROL0_FORCE_TXCLK_BITS 1 4997 #define TX1_TX_ACONTROL0_FORCE_TXCLK_SHIFT 14 4998 4999 /* TX1 :: Tx_AControl0 :: tx1g_fifo_rst [13:13] */ 5000 #define TX1_TX_ACONTROL0_TX1G_FIFO_RST_MASK 0x2000 5001 #define TX1_TX_ACONTROL0_TX1G_FIFO_RST_ALIGN 0 5002 #define TX1_TX_ACONTROL0_TX1G_FIFO_RST_BITS 1 5003 #define TX1_TX_ACONTROL0_TX1G_FIFO_RST_SHIFT 13 5004 5005 /* TX1 :: Tx_AControl0 :: gloopOutEn [12:12] */ 5006 #define TX1_TX_ACONTROL0_GLOOPOUTEN_MASK 0x1000 5007 #define TX1_TX_ACONTROL0_GLOOPOUTEN_ALIGN 0 5008 #define TX1_TX_ACONTROL0_GLOOPOUTEN_BITS 1 5009 #define TX1_TX_ACONTROL0_GLOOPOUTEN_SHIFT 12 5010 5011 /* TX1 :: Tx_AControl0 :: reserved1 [11:09] */ 5012 #define TX1_TX_ACONTROL0_RESERVED1_MASK 0x0e00 5013 #define TX1_TX_ACONTROL0_RESERVED1_ALIGN 0 5014 #define TX1_TX_ACONTROL0_RESERVED1_BITS 3 5015 #define TX1_TX_ACONTROL0_RESERVED1_SHIFT 9 5016 5017 /* TX1 :: Tx_AControl0 :: prbs_en [08:08] */ 5018 #define TX1_TX_ACONTROL0_PRBS_EN_MASK 0x0100 5019 #define TX1_TX_ACONTROL0_PRBS_EN_ALIGN 0 5020 #define TX1_TX_ACONTROL0_PRBS_EN_BITS 1 5021 #define TX1_TX_ACONTROL0_PRBS_EN_SHIFT 8 5022 5023 /* TX1 :: Tx_AControl0 :: pckt_en [07:07] */ 5024 #define TX1_TX_ACONTROL0_PCKT_EN_MASK 0x0080 5025 #define TX1_TX_ACONTROL0_PCKT_EN_ALIGN 0 5026 #define TX1_TX_ACONTROL0_PCKT_EN_BITS 1 5027 #define TX1_TX_ACONTROL0_PCKT_EN_SHIFT 7 5028 5029 /* TX1 :: Tx_AControl0 :: pckt_strt [06:06] */ 5030 #define TX1_TX_ACONTROL0_PCKT_STRT_MASK 0x0040 5031 #define TX1_TX_ACONTROL0_PCKT_STRT_ALIGN 0 5032 #define TX1_TX_ACONTROL0_PCKT_STRT_BITS 1 5033 #define TX1_TX_ACONTROL0_PCKT_STRT_SHIFT 6 5034 5035 /* TX1 :: Tx_AControl0 :: txpol_flip [05:05] */ 5036 #define TX1_TX_ACONTROL0_TXPOL_FLIP_MASK 0x0020 5037 #define TX1_TX_ACONTROL0_TXPOL_FLIP_ALIGN 0 5038 #define TX1_TX_ACONTROL0_TXPOL_FLIP_BITS 1 5039 #define TX1_TX_ACONTROL0_TXPOL_FLIP_SHIFT 5 5040 5041 /* TX1 :: Tx_AControl0 :: rtbi_flip [04:04] */ 5042 #define TX1_TX_ACONTROL0_RTBI_FLIP_MASK 0x0010 5043 #define TX1_TX_ACONTROL0_RTBI_FLIP_ALIGN 0 5044 #define TX1_TX_ACONTROL0_RTBI_FLIP_BITS 1 5045 #define TX1_TX_ACONTROL0_RTBI_FLIP_SHIFT 4 5046 5047 /* TX1 :: Tx_AControl0 :: eden_r [03:03] */ 5048 #define TX1_TX_ACONTROL0_EDEN_R_MASK 0x0008 5049 #define TX1_TX_ACONTROL0_EDEN_R_ALIGN 0 5050 #define TX1_TX_ACONTROL0_EDEN_R_BITS 1 5051 #define TX1_TX_ACONTROL0_EDEN_R_SHIFT 3 5052 5053 /* TX1 :: Tx_AControl0 :: eden_force_r [02:02] */ 5054 #define TX1_TX_ACONTROL0_EDEN_FORCE_R_MASK 0x0004 5055 #define TX1_TX_ACONTROL0_EDEN_FORCE_R_ALIGN 0 5056 #define TX1_TX_ACONTROL0_EDEN_FORCE_R_BITS 1 5057 #define TX1_TX_ACONTROL0_EDEN_FORCE_R_SHIFT 2 5058 5059 /* TX1 :: Tx_AControl0 :: txpat_en [01:01] */ 5060 #define TX1_TX_ACONTROL0_TXPAT_EN_MASK 0x0002 5061 #define TX1_TX_ACONTROL0_TXPAT_EN_ALIGN 0 5062 #define TX1_TX_ACONTROL0_TXPAT_EN_BITS 1 5063 #define TX1_TX_ACONTROL0_TXPAT_EN_SHIFT 1 5064 5065 /* TX1 :: Tx_AControl0 :: tx_mdata_en [00:00] */ 5066 #define TX1_TX_ACONTROL0_TX_MDATA_EN_MASK 0x0001 5067 #define TX1_TX_ACONTROL0_TX_MDATA_EN_ALIGN 0 5068 #define TX1_TX_ACONTROL0_TX_MDATA_EN_BITS 1 5069 #define TX1_TX_ACONTROL0_TX_MDATA_EN_SHIFT 0 5070 5071 5072 /**************************************************************************** 5073 * TX1 :: Tx_mdata0 5074 */ 5075 /* TX1 :: Tx_mdata0 :: txTestMuxSel [15:13] */ 5076 #define TX1_TX_MDATA0_TXTESTMUXSEL_MASK 0xe000 5077 #define TX1_TX_MDATA0_TXTESTMUXSEL_ALIGN 0 5078 #define TX1_TX_MDATA0_TXTESTMUXSEL_BITS 3 5079 #define TX1_TX_MDATA0_TXTESTMUXSEL_SHIFT 13 5080 5081 /* TX1 :: Tx_mdata0 :: rlfifo_tstsel [12:10] */ 5082 #define TX1_TX_MDATA0_RLFIFO_TSTSEL_MASK 0x1c00 5083 #define TX1_TX_MDATA0_RLFIFO_TSTSEL_ALIGN 0 5084 #define TX1_TX_MDATA0_RLFIFO_TSTSEL_BITS 3 5085 #define TX1_TX_MDATA0_RLFIFO_TSTSEL_SHIFT 10 5086 5087 /* TX1 :: Tx_mdata0 :: TxMdioTstDataL [09:00] */ 5088 #define TX1_TX_MDATA0_TXMDIOTSTDATAL_MASK 0x03ff 5089 #define TX1_TX_MDATA0_TXMDIOTSTDATAL_ALIGN 0 5090 #define TX1_TX_MDATA0_TXMDIOTSTDATAL_BITS 10 5091 #define TX1_TX_MDATA0_TXMDIOTSTDATAL_SHIFT 0 5092 5093 5094 /**************************************************************************** 5095 * TX1 :: Tx_mdata1 5096 */ 5097 /* TX1 :: Tx_mdata1 :: reserved0 [15:10] */ 5098 #define TX1_TX_MDATA1_RESERVED0_MASK 0xfc00 5099 #define TX1_TX_MDATA1_RESERVED0_ALIGN 0 5100 #define TX1_TX_MDATA1_RESERVED0_BITS 6 5101 #define TX1_TX_MDATA1_RESERVED0_SHIFT 10 5102 5103 /* TX1 :: Tx_mdata1 :: TxMdioTstDataH [09:00] */ 5104 #define TX1_TX_MDATA1_TXMDIOTSTDATAH_MASK 0x03ff 5105 #define TX1_TX_MDATA1_TXMDIOTSTDATAH_ALIGN 0 5106 #define TX1_TX_MDATA1_TXMDIOTSTDATAH_BITS 10 5107 #define TX1_TX_MDATA1_TXMDIOTSTDATAH_SHIFT 0 5108 5109 5110 /**************************************************************************** 5111 * TX1 :: Tx_AStatus1 5112 */ 5113 /* TX1 :: Tx_AStatus1 :: tx_id [15:14] */ 5114 #define TX1_TX_ASTATUS1_TX_ID_MASK 0xc000 5115 #define TX1_TX_ASTATUS1_TX_ID_ALIGN 0 5116 #define TX1_TX_ASTATUS1_TX_ID_BITS 2 5117 #define TX1_TX_ASTATUS1_TX_ID_SHIFT 14 5118 5119 /* TX1 :: Tx_AStatus1 :: reserved0 [13:00] */ 5120 #define TX1_TX_ASTATUS1_RESERVED0_MASK 0x3fff 5121 #define TX1_TX_ASTATUS1_RESERVED0_ALIGN 0 5122 #define TX1_TX_ASTATUS1_RESERVED0_BITS 14 5123 #define TX1_TX_ASTATUS1_RESERVED0_SHIFT 0 5124 5125 5126 /**************************************************************************** 5127 * TX1 :: Tx_BgVcm 5128 */ 5129 /* TX1 :: Tx_BgVcm :: id2c [15:13] */ 5130 #define TX1_TX_BGVCM_ID2C_MASK 0xe000 5131 #define TX1_TX_BGVCM_ID2C_ALIGN 0 5132 #define TX1_TX_BGVCM_ID2C_BITS 3 5133 #define TX1_TX_BGVCM_ID2C_SHIFT 13 5134 5135 /* TX1 :: Tx_BgVcm :: refl_tx [12:12] */ 5136 #define TX1_TX_BGVCM_REFL_TX_MASK 0x1000 5137 #define TX1_TX_BGVCM_REFL_TX_ALIGN 0 5138 #define TX1_TX_BGVCM_REFL_TX_BITS 1 5139 #define TX1_TX_BGVCM_REFL_TX_SHIFT 12 5140 5141 /* TX1 :: Tx_BgVcm :: refh_tx [11:11] */ 5142 #define TX1_TX_BGVCM_REFH_TX_MASK 0x0800 5143 #define TX1_TX_BGVCM_REFH_TX_ALIGN 0 5144 #define TX1_TX_BGVCM_REFH_TX_BITS 1 5145 #define TX1_TX_BGVCM_REFH_TX_SHIFT 11 5146 5147 /* TX1 :: Tx_BgVcm :: newbias_en [10:10] */ 5148 #define TX1_TX_BGVCM_NEWBIAS_EN_MASK 0x0400 5149 #define TX1_TX_BGVCM_NEWBIAS_EN_ALIGN 0 5150 #define TX1_TX_BGVCM_NEWBIAS_EN_BITS 1 5151 #define TX1_TX_BGVCM_NEWBIAS_EN_SHIFT 10 5152 5153 /* TX1 :: Tx_BgVcm :: drivermode [09:09] */ 5154 #define TX1_TX_BGVCM_DRIVERMODE_MASK 0x0200 5155 #define TX1_TX_BGVCM_DRIVERMODE_ALIGN 0 5156 #define TX1_TX_BGVCM_DRIVERMODE_BITS 1 5157 #define TX1_TX_BGVCM_DRIVERMODE_SHIFT 9 5158 5159 /* TX1 :: Tx_BgVcm :: bddr_bgb [08:08] */ 5160 #define TX1_TX_BGVCM_BDDR_BGB_MASK 0x0100 5161 #define TX1_TX_BGVCM_BDDR_BGB_ALIGN 0 5162 #define TX1_TX_BGVCM_BDDR_BGB_BITS 1 5163 #define TX1_TX_BGVCM_BDDR_BGB_SHIFT 8 5164 5165 /* TX1 :: Tx_BgVcm :: ticksel [07:06] */ 5166 #define TX1_TX_BGVCM_TICKSEL_MASK 0x00c0 5167 #define TX1_TX_BGVCM_TICKSEL_ALIGN 0 5168 #define TX1_TX_BGVCM_TICKSEL_BITS 2 5169 #define TX1_TX_BGVCM_TICKSEL_SHIFT 6 5170 5171 /* TX1 :: Tx_BgVcm :: driver_vcm [05:04] */ 5172 #define TX1_TX_BGVCM_DRIVER_VCM_MASK 0x0030 5173 #define TX1_TX_BGVCM_DRIVER_VCM_ALIGN 0 5174 #define TX1_TX_BGVCM_DRIVER_VCM_BITS 2 5175 #define TX1_TX_BGVCM_DRIVER_VCM_SHIFT 4 5176 5177 /* TX1 :: Tx_BgVcm :: tx_sel_halfrate [03:03] */ 5178 #define TX1_TX_BGVCM_TX_SEL_HALFRATE_MASK 0x0008 5179 #define TX1_TX_BGVCM_TX_SEL_HALFRATE_ALIGN 0 5180 #define TX1_TX_BGVCM_TX_SEL_HALFRATE_BITS 1 5181 #define TX1_TX_BGVCM_TX_SEL_HALFRATE_SHIFT 3 5182 5183 /* TX1 :: Tx_BgVcm :: ifullspd [02:00] */ 5184 #define TX1_TX_BGVCM_IFULLSPD_MASK 0x0007 5185 #define TX1_TX_BGVCM_IFULLSPD_ALIGN 0 5186 #define TX1_TX_BGVCM_IFULLSPD_BITS 3 5187 #define TX1_TX_BGVCM_IFULLSPD_SHIFT 0 5188 5189 5190 /**************************************************************************** 5191 * TX1 :: Tx_ibuff_1T2T 5192 */ 5193 /* TX1 :: Tx_ibuff_1T2T :: icbuf1t [15:14] */ 5194 #define TX1_TX_IBUFF_1T2T_ICBUF1T_MASK 0xc000 5195 #define TX1_TX_IBUFF_1T2T_ICBUF1T_ALIGN 0 5196 #define TX1_TX_IBUFF_1T2T_ICBUF1T_BITS 2 5197 #define TX1_TX_IBUFF_1T2T_ICBUF1T_SHIFT 14 5198 5199 /* TX1 :: Tx_ibuff_1T2T :: icbuf2t [13:11] */ 5200 #define TX1_TX_IBUFF_1T2T_ICBUF2T_MASK 0x3800 5201 #define TX1_TX_IBUFF_1T2T_ICBUF2T_ALIGN 0 5202 #define TX1_TX_IBUFF_1T2T_ICBUF2T_BITS 3 5203 #define TX1_TX_IBUFF_1T2T_ICBUF2T_SHIFT 11 5204 5205 /* TX1 :: Tx_ibuff_1T2T :: imin_predrv [10:10] */ 5206 #define TX1_TX_IBUFF_1T2T_IMIN_PREDRV_MASK 0x0400 5207 #define TX1_TX_IBUFF_1T2T_IMIN_PREDRV_ALIGN 0 5208 #define TX1_TX_IBUFF_1T2T_IMIN_PREDRV_BITS 1 5209 #define TX1_TX_IBUFF_1T2T_IMIN_PREDRV_SHIFT 10 5210 5211 /* TX1 :: Tx_ibuff_1T2T :: imax_predrv [09:09] */ 5212 #define TX1_TX_IBUFF_1T2T_IMAX_PREDRV_MASK 0x0200 5213 #define TX1_TX_IBUFF_1T2T_IMAX_PREDRV_ALIGN 0 5214 #define TX1_TX_IBUFF_1T2T_IMAX_PREDRV_BITS 1 5215 #define TX1_TX_IBUFF_1T2T_IMAX_PREDRV_SHIFT 9 5216 5217 /* TX1 :: Tx_ibuff_1T2T :: imode_predrv [08:08] */ 5218 #define TX1_TX_IBUFF_1T2T_IMODE_PREDRV_MASK 0x0100 5219 #define TX1_TX_IBUFF_1T2T_IMODE_PREDRV_ALIGN 0 5220 #define TX1_TX_IBUFF_1T2T_IMODE_PREDRV_BITS 1 5221 #define TX1_TX_IBUFF_1T2T_IMODE_PREDRV_SHIFT 8 5222 5223 /* TX1 :: Tx_ibuff_1T2T :: i21mux [07:05] */ 5224 #define TX1_TX_IBUFF_1T2T_I21MUX_MASK 0x00e0 5225 #define TX1_TX_IBUFF_1T2T_I21MUX_ALIGN 0 5226 #define TX1_TX_IBUFF_1T2T_I21MUX_BITS 3 5227 #define TX1_TX_IBUFF_1T2T_I21MUX_SHIFT 5 5228 5229 /* TX1 :: Tx_ibuff_1T2T :: imin_drvr [04:04] */ 5230 #define TX1_TX_IBUFF_1T2T_IMIN_DRVR_MASK 0x0010 5231 #define TX1_TX_IBUFF_1T2T_IMIN_DRVR_ALIGN 0 5232 #define TX1_TX_IBUFF_1T2T_IMIN_DRVR_BITS 1 5233 #define TX1_TX_IBUFF_1T2T_IMIN_DRVR_SHIFT 4 5234 5235 /* TX1 :: Tx_ibuff_1T2T :: imax_drvr [03:03] */ 5236 #define TX1_TX_IBUFF_1T2T_IMAX_DRVR_MASK 0x0008 5237 #define TX1_TX_IBUFF_1T2T_IMAX_DRVR_ALIGN 0 5238 #define TX1_TX_IBUFF_1T2T_IMAX_DRVR_BITS 1 5239 #define TX1_TX_IBUFF_1T2T_IMAX_DRVR_SHIFT 3 5240 5241 /* TX1 :: Tx_ibuff_1T2T :: imode_drvr [02:02] */ 5242 #define TX1_TX_IBUFF_1T2T_IMODE_DRVR_MASK 0x0004 5243 #define TX1_TX_IBUFF_1T2T_IMODE_DRVR_ALIGN 0 5244 #define TX1_TX_IBUFF_1T2T_IMODE_DRVR_BITS 1 5245 #define TX1_TX_IBUFF_1T2T_IMODE_DRVR_SHIFT 2 5246 5247 /* TX1 :: Tx_ibuff_1T2T :: reserved0 [01:00] */ 5248 #define TX1_TX_IBUFF_1T2T_RESERVED0_MASK 0x0003 5249 #define TX1_TX_IBUFF_1T2T_RESERVED0_ALIGN 0 5250 #define TX1_TX_IBUFF_1T2T_RESERVED0_BITS 2 5251 #define TX1_TX_IBUFF_1T2T_RESERVED0_SHIFT 0 5252 5253 5254 /**************************************************************************** 5255 * TX1 :: Tx_Driver 5256 */ 5257 /* TX1 :: Tx_Driver :: preemphasis_post [15:12] */ 5258 #define TX1_TX_DRIVER_PREEMPHASIS_POST_MASK 0xf000 5259 #define TX1_TX_DRIVER_PREEMPHASIS_POST_ALIGN 0 5260 #define TX1_TX_DRIVER_PREEMPHASIS_POST_BITS 4 5261 #define TX1_TX_DRIVER_PREEMPHASIS_POST_SHIFT 12 5262 5263 /* TX1 :: Tx_Driver :: Idriver [11:08] */ 5264 #define TX1_TX_DRIVER_IDRIVER_MASK 0x0f00 5265 #define TX1_TX_DRIVER_IDRIVER_ALIGN 0 5266 #define TX1_TX_DRIVER_IDRIVER_BITS 4 5267 #define TX1_TX_DRIVER_IDRIVER_SHIFT 8 5268 5269 /* TX1 :: Tx_Driver :: Ipredriver [07:04] */ 5270 #define TX1_TX_DRIVER_IPREDRIVER_MASK 0x00f0 5271 #define TX1_TX_DRIVER_IPREDRIVER_ALIGN 0 5272 #define TX1_TX_DRIVER_IPREDRIVER_BITS 4 5273 #define TX1_TX_DRIVER_IPREDRIVER_SHIFT 4 5274 5275 /* TX1 :: Tx_Driver :: preemphasis_pre [03:01] */ 5276 #define TX1_TX_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 5277 #define TX1_TX_DRIVER_PREEMPHASIS_PRE_ALIGN 0 5278 #define TX1_TX_DRIVER_PREEMPHASIS_PRE_BITS 3 5279 #define TX1_TX_DRIVER_PREEMPHASIS_PRE_SHIFT 1 5280 5281 /* TX1 :: Tx_Driver :: icbuf1t0 [00:00] */ 5282 #define TX1_TX_DRIVER_ICBUF1T0_MASK 0x0001 5283 #define TX1_TX_DRIVER_ICBUF1T0_ALIGN 0 5284 #define TX1_TX_DRIVER_ICBUF1T0_BITS 1 5285 #define TX1_TX_DRIVER_ICBUF1T0_SHIFT 0 5286 5287 5288 /**************************************************************************** 5289 * XGXS16G_USER_TX2 5290 */ 5291 /**************************************************************************** 5292 * TX2 :: Tx_AStatus0 5293 */ 5294 /* TX2 :: Tx_AStatus0 :: reserved0 [15:03] */ 5295 #define TX2_TX_ASTATUS0_RESERVED0_MASK 0xfff8 5296 #define TX2_TX_ASTATUS0_RESERVED0_ALIGN 0 5297 #define TX2_TX_ASTATUS0_RESERVED0_BITS 13 5298 #define TX2_TX_ASTATUS0_RESERVED0_SHIFT 3 5299 5300 /* TX2 :: Tx_AStatus0 :: tx_gloopback [02:02] */ 5301 #define TX2_TX_ASTATUS0_TX_GLOOPBACK_MASK 0x0004 5302 #define TX2_TX_ASTATUS0_TX_GLOOPBACK_ALIGN 0 5303 #define TX2_TX_ASTATUS0_TX_GLOOPBACK_BITS 1 5304 #define TX2_TX_ASTATUS0_TX_GLOOPBACK_SHIFT 2 5305 5306 /* TX2 :: Tx_AStatus0 :: rltxferr [01:01] */ 5307 #define TX2_TX_ASTATUS0_RLTXFERR_MASK 0x0002 5308 #define TX2_TX_ASTATUS0_RLTXFERR_ALIGN 0 5309 #define TX2_TX_ASTATUS0_RLTXFERR_BITS 1 5310 #define TX2_TX_ASTATUS0_RLTXFERR_SHIFT 1 5311 5312 /* TX2 :: Tx_AStatus0 :: txferr [00:00] */ 5313 #define TX2_TX_ASTATUS0_TXFERR_MASK 0x0001 5314 #define TX2_TX_ASTATUS0_TXFERR_ALIGN 0 5315 #define TX2_TX_ASTATUS0_TXFERR_BITS 1 5316 #define TX2_TX_ASTATUS0_TXFERR_SHIFT 0 5317 5318 5319 /**************************************************************************** 5320 * TX2 :: Tx_AControl0 5321 */ 5322 /* TX2 :: Tx_AControl0 :: reserved0 [15:15] */ 5323 #define TX2_TX_ACONTROL0_RESERVED0_MASK 0x8000 5324 #define TX2_TX_ACONTROL0_RESERVED0_ALIGN 0 5325 #define TX2_TX_ACONTROL0_RESERVED0_BITS 1 5326 #define TX2_TX_ACONTROL0_RESERVED0_SHIFT 15 5327 5328 /* TX2 :: Tx_AControl0 :: force_txclk [14:14] */ 5329 #define TX2_TX_ACONTROL0_FORCE_TXCLK_MASK 0x4000 5330 #define TX2_TX_ACONTROL0_FORCE_TXCLK_ALIGN 0 5331 #define TX2_TX_ACONTROL0_FORCE_TXCLK_BITS 1 5332 #define TX2_TX_ACONTROL0_FORCE_TXCLK_SHIFT 14 5333 5334 /* TX2 :: Tx_AControl0 :: tx1g_fifo_rst [13:13] */ 5335 #define TX2_TX_ACONTROL0_TX1G_FIFO_RST_MASK 0x2000 5336 #define TX2_TX_ACONTROL0_TX1G_FIFO_RST_ALIGN 0 5337 #define TX2_TX_ACONTROL0_TX1G_FIFO_RST_BITS 1 5338 #define TX2_TX_ACONTROL0_TX1G_FIFO_RST_SHIFT 13 5339 5340 /* TX2 :: Tx_AControl0 :: gloopOutEn [12:12] */ 5341 #define TX2_TX_ACONTROL0_GLOOPOUTEN_MASK 0x1000 5342 #define TX2_TX_ACONTROL0_GLOOPOUTEN_ALIGN 0 5343 #define TX2_TX_ACONTROL0_GLOOPOUTEN_BITS 1 5344 #define TX2_TX_ACONTROL0_GLOOPOUTEN_SHIFT 12 5345 5346 /* TX2 :: Tx_AControl0 :: reserved1 [11:09] */ 5347 #define TX2_TX_ACONTROL0_RESERVED1_MASK 0x0e00 5348 #define TX2_TX_ACONTROL0_RESERVED1_ALIGN 0 5349 #define TX2_TX_ACONTROL0_RESERVED1_BITS 3 5350 #define TX2_TX_ACONTROL0_RESERVED1_SHIFT 9 5351 5352 /* TX2 :: Tx_AControl0 :: prbs_en [08:08] */ 5353 #define TX2_TX_ACONTROL0_PRBS_EN_MASK 0x0100 5354 #define TX2_TX_ACONTROL0_PRBS_EN_ALIGN 0 5355 #define TX2_TX_ACONTROL0_PRBS_EN_BITS 1 5356 #define TX2_TX_ACONTROL0_PRBS_EN_SHIFT 8 5357 5358 /* TX2 :: Tx_AControl0 :: pckt_en [07:07] */ 5359 #define TX2_TX_ACONTROL0_PCKT_EN_MASK 0x0080 5360 #define TX2_TX_ACONTROL0_PCKT_EN_ALIGN 0 5361 #define TX2_TX_ACONTROL0_PCKT_EN_BITS 1 5362 #define TX2_TX_ACONTROL0_PCKT_EN_SHIFT 7 5363 5364 /* TX2 :: Tx_AControl0 :: pckt_strt [06:06] */ 5365 #define TX2_TX_ACONTROL0_PCKT_STRT_MASK 0x0040 5366 #define TX2_TX_ACONTROL0_PCKT_STRT_ALIGN 0 5367 #define TX2_TX_ACONTROL0_PCKT_STRT_BITS 1 5368 #define TX2_TX_ACONTROL0_PCKT_STRT_SHIFT 6 5369 5370 /* TX2 :: Tx_AControl0 :: txpol_flip [05:05] */ 5371 #define TX2_TX_ACONTROL0_TXPOL_FLIP_MASK 0x0020 5372 #define TX2_TX_ACONTROL0_TXPOL_FLIP_ALIGN 0 5373 #define TX2_TX_ACONTROL0_TXPOL_FLIP_BITS 1 5374 #define TX2_TX_ACONTROL0_TXPOL_FLIP_SHIFT 5 5375 5376 /* TX2 :: Tx_AControl0 :: rtbi_flip [04:04] */ 5377 #define TX2_TX_ACONTROL0_RTBI_FLIP_MASK 0x0010 5378 #define TX2_TX_ACONTROL0_RTBI_FLIP_ALIGN 0 5379 #define TX2_TX_ACONTROL0_RTBI_FLIP_BITS 1 5380 #define TX2_TX_ACONTROL0_RTBI_FLIP_SHIFT 4 5381 5382 /* TX2 :: Tx_AControl0 :: eden_r [03:03] */ 5383 #define TX2_TX_ACONTROL0_EDEN_R_MASK 0x0008 5384 #define TX2_TX_ACONTROL0_EDEN_R_ALIGN 0 5385 #define TX2_TX_ACONTROL0_EDEN_R_BITS 1 5386 #define TX2_TX_ACONTROL0_EDEN_R_SHIFT 3 5387 5388 /* TX2 :: Tx_AControl0 :: eden_force_r [02:02] */ 5389 #define TX2_TX_ACONTROL0_EDEN_FORCE_R_MASK 0x0004 5390 #define TX2_TX_ACONTROL0_EDEN_FORCE_R_ALIGN 0 5391 #define TX2_TX_ACONTROL0_EDEN_FORCE_R_BITS 1 5392 #define TX2_TX_ACONTROL0_EDEN_FORCE_R_SHIFT 2 5393 5394 /* TX2 :: Tx_AControl0 :: txpat_en [01:01] */ 5395 #define TX2_TX_ACONTROL0_TXPAT_EN_MASK 0x0002 5396 #define TX2_TX_ACONTROL0_TXPAT_EN_ALIGN 0 5397 #define TX2_TX_ACONTROL0_TXPAT_EN_BITS 1 5398 #define TX2_TX_ACONTROL0_TXPAT_EN_SHIFT 1 5399 5400 /* TX2 :: Tx_AControl0 :: tx_mdata_en [00:00] */ 5401 #define TX2_TX_ACONTROL0_TX_MDATA_EN_MASK 0x0001 5402 #define TX2_TX_ACONTROL0_TX_MDATA_EN_ALIGN 0 5403 #define TX2_TX_ACONTROL0_TX_MDATA_EN_BITS 1 5404 #define TX2_TX_ACONTROL0_TX_MDATA_EN_SHIFT 0 5405 5406 5407 /**************************************************************************** 5408 * TX2 :: Tx_mdata0 5409 */ 5410 /* TX2 :: Tx_mdata0 :: txTestMuxSel [15:13] */ 5411 #define TX2_TX_MDATA0_TXTESTMUXSEL_MASK 0xe000 5412 #define TX2_TX_MDATA0_TXTESTMUXSEL_ALIGN 0 5413 #define TX2_TX_MDATA0_TXTESTMUXSEL_BITS 3 5414 #define TX2_TX_MDATA0_TXTESTMUXSEL_SHIFT 13 5415 5416 /* TX2 :: Tx_mdata0 :: rlfifo_tstsel [12:10] */ 5417 #define TX2_TX_MDATA0_RLFIFO_TSTSEL_MASK 0x1c00 5418 #define TX2_TX_MDATA0_RLFIFO_TSTSEL_ALIGN 0 5419 #define TX2_TX_MDATA0_RLFIFO_TSTSEL_BITS 3 5420 #define TX2_TX_MDATA0_RLFIFO_TSTSEL_SHIFT 10 5421 5422 /* TX2 :: Tx_mdata0 :: TxMdioTstDataL [09:00] */ 5423 #define TX2_TX_MDATA0_TXMDIOTSTDATAL_MASK 0x03ff 5424 #define TX2_TX_MDATA0_TXMDIOTSTDATAL_ALIGN 0 5425 #define TX2_TX_MDATA0_TXMDIOTSTDATAL_BITS 10 5426 #define TX2_TX_MDATA0_TXMDIOTSTDATAL_SHIFT 0 5427 5428 5429 /**************************************************************************** 5430 * TX2 :: Tx_mdata1 5431 */ 5432 /* TX2 :: Tx_mdata1 :: reserved0 [15:10] */ 5433 #define TX2_TX_MDATA1_RESERVED0_MASK 0xfc00 5434 #define TX2_TX_MDATA1_RESERVED0_ALIGN 0 5435 #define TX2_TX_MDATA1_RESERVED0_BITS 6 5436 #define TX2_TX_MDATA1_RESERVED0_SHIFT 10 5437 5438 /* TX2 :: Tx_mdata1 :: TxMdioTstDataH [09:00] */ 5439 #define TX2_TX_MDATA1_TXMDIOTSTDATAH_MASK 0x03ff 5440 #define TX2_TX_MDATA1_TXMDIOTSTDATAH_ALIGN 0 5441 #define TX2_TX_MDATA1_TXMDIOTSTDATAH_BITS 10 5442 #define TX2_TX_MDATA1_TXMDIOTSTDATAH_SHIFT 0 5443 5444 5445 /**************************************************************************** 5446 * TX2 :: Tx_AStatus1 5447 */ 5448 /* TX2 :: Tx_AStatus1 :: tx_id [15:14] */ 5449 #define TX2_TX_ASTATUS1_TX_ID_MASK 0xc000 5450 #define TX2_TX_ASTATUS1_TX_ID_ALIGN 0 5451 #define TX2_TX_ASTATUS1_TX_ID_BITS 2 5452 #define TX2_TX_ASTATUS1_TX_ID_SHIFT 14 5453 5454 /* TX2 :: Tx_AStatus1 :: reserved0 [13:00] */ 5455 #define TX2_TX_ASTATUS1_RESERVED0_MASK 0x3fff 5456 #define TX2_TX_ASTATUS1_RESERVED0_ALIGN 0 5457 #define TX2_TX_ASTATUS1_RESERVED0_BITS 14 5458 #define TX2_TX_ASTATUS1_RESERVED0_SHIFT 0 5459 5460 5461 /**************************************************************************** 5462 * TX2 :: Tx_BgVcm 5463 */ 5464 /* TX2 :: Tx_BgVcm :: id2c [15:13] */ 5465 #define TX2_TX_BGVCM_ID2C_MASK 0xe000 5466 #define TX2_TX_BGVCM_ID2C_ALIGN 0 5467 #define TX2_TX_BGVCM_ID2C_BITS 3 5468 #define TX2_TX_BGVCM_ID2C_SHIFT 13 5469 5470 /* TX2 :: Tx_BgVcm :: refl_tx [12:12] */ 5471 #define TX2_TX_BGVCM_REFL_TX_MASK 0x1000 5472 #define TX2_TX_BGVCM_REFL_TX_ALIGN 0 5473 #define TX2_TX_BGVCM_REFL_TX_BITS 1 5474 #define TX2_TX_BGVCM_REFL_TX_SHIFT 12 5475 5476 /* TX2 :: Tx_BgVcm :: refh_tx [11:11] */ 5477 #define TX2_TX_BGVCM_REFH_TX_MASK 0x0800 5478 #define TX2_TX_BGVCM_REFH_TX_ALIGN 0 5479 #define TX2_TX_BGVCM_REFH_TX_BITS 1 5480 #define TX2_TX_BGVCM_REFH_TX_SHIFT 11 5481 5482 /* TX2 :: Tx_BgVcm :: newbias_en [10:10] */ 5483 #define TX2_TX_BGVCM_NEWBIAS_EN_MASK 0x0400 5484 #define TX2_TX_BGVCM_NEWBIAS_EN_ALIGN 0 5485 #define TX2_TX_BGVCM_NEWBIAS_EN_BITS 1 5486 #define TX2_TX_BGVCM_NEWBIAS_EN_SHIFT 10 5487 5488 /* TX2 :: Tx_BgVcm :: drivermode [09:09] */ 5489 #define TX2_TX_BGVCM_DRIVERMODE_MASK 0x0200 5490 #define TX2_TX_BGVCM_DRIVERMODE_ALIGN 0 5491 #define TX2_TX_BGVCM_DRIVERMODE_BITS 1 5492 #define TX2_TX_BGVCM_DRIVERMODE_SHIFT 9 5493 5494 /* TX2 :: Tx_BgVcm :: bddr_bgb [08:08] */ 5495 #define TX2_TX_BGVCM_BDDR_BGB_MASK 0x0100 5496 #define TX2_TX_BGVCM_BDDR_BGB_ALIGN 0 5497 #define TX2_TX_BGVCM_BDDR_BGB_BITS 1 5498 #define TX2_TX_BGVCM_BDDR_BGB_SHIFT 8 5499 5500 /* TX2 :: Tx_BgVcm :: ticksel [07:06] */ 5501 #define TX2_TX_BGVCM_TICKSEL_MASK 0x00c0 5502 #define TX2_TX_BGVCM_TICKSEL_ALIGN 0 5503 #define TX2_TX_BGVCM_TICKSEL_BITS 2 5504 #define TX2_TX_BGVCM_TICKSEL_SHIFT 6 5505 5506 /* TX2 :: Tx_BgVcm :: driver_vcm [05:04] */ 5507 #define TX2_TX_BGVCM_DRIVER_VCM_MASK 0x0030 5508 #define TX2_TX_BGVCM_DRIVER_VCM_ALIGN 0 5509 #define TX2_TX_BGVCM_DRIVER_VCM_BITS 2 5510 #define TX2_TX_BGVCM_DRIVER_VCM_SHIFT 4 5511 5512 /* TX2 :: Tx_BgVcm :: tx_sel_halfrate [03:03] */ 5513 #define TX2_TX_BGVCM_TX_SEL_HALFRATE_MASK 0x0008 5514 #define TX2_TX_BGVCM_TX_SEL_HALFRATE_ALIGN 0 5515 #define TX2_TX_BGVCM_TX_SEL_HALFRATE_BITS 1 5516 #define TX2_TX_BGVCM_TX_SEL_HALFRATE_SHIFT 3 5517 5518 /* TX2 :: Tx_BgVcm :: ifullspd [02:00] */ 5519 #define TX2_TX_BGVCM_IFULLSPD_MASK 0x0007 5520 #define TX2_TX_BGVCM_IFULLSPD_ALIGN 0 5521 #define TX2_TX_BGVCM_IFULLSPD_BITS 3 5522 #define TX2_TX_BGVCM_IFULLSPD_SHIFT 0 5523 5524 5525 /**************************************************************************** 5526 * TX2 :: Tx_ibuff_1T2T 5527 */ 5528 /* TX2 :: Tx_ibuff_1T2T :: icbuf1t [15:14] */ 5529 #define TX2_TX_IBUFF_1T2T_ICBUF1T_MASK 0xc000 5530 #define TX2_TX_IBUFF_1T2T_ICBUF1T_ALIGN 0 5531 #define TX2_TX_IBUFF_1T2T_ICBUF1T_BITS 2 5532 #define TX2_TX_IBUFF_1T2T_ICBUF1T_SHIFT 14 5533 5534 /* TX2 :: Tx_ibuff_1T2T :: icbuf2t [13:11] */ 5535 #define TX2_TX_IBUFF_1T2T_ICBUF2T_MASK 0x3800 5536 #define TX2_TX_IBUFF_1T2T_ICBUF2T_ALIGN 0 5537 #define TX2_TX_IBUFF_1T2T_ICBUF2T_BITS 3 5538 #define TX2_TX_IBUFF_1T2T_ICBUF2T_SHIFT 11 5539 5540 /* TX2 :: Tx_ibuff_1T2T :: imin_predrv [10:10] */ 5541 #define TX2_TX_IBUFF_1T2T_IMIN_PREDRV_MASK 0x0400 5542 #define TX2_TX_IBUFF_1T2T_IMIN_PREDRV_ALIGN 0 5543 #define TX2_TX_IBUFF_1T2T_IMIN_PREDRV_BITS 1 5544 #define TX2_TX_IBUFF_1T2T_IMIN_PREDRV_SHIFT 10 5545 5546 /* TX2 :: Tx_ibuff_1T2T :: imax_predrv [09:09] */ 5547 #define TX2_TX_IBUFF_1T2T_IMAX_PREDRV_MASK 0x0200 5548 #define TX2_TX_IBUFF_1T2T_IMAX_PREDRV_ALIGN 0 5549 #define TX2_TX_IBUFF_1T2T_IMAX_PREDRV_BITS 1 5550 #define TX2_TX_IBUFF_1T2T_IMAX_PREDRV_SHIFT 9 5551 5552 /* TX2 :: Tx_ibuff_1T2T :: imode_predrv [08:08] */ 5553 #define TX2_TX_IBUFF_1T2T_IMODE_PREDRV_MASK 0x0100 5554 #define TX2_TX_IBUFF_1T2T_IMODE_PREDRV_ALIGN 0 5555 #define TX2_TX_IBUFF_1T2T_IMODE_PREDRV_BITS 1 5556 #define TX2_TX_IBUFF_1T2T_IMODE_PREDRV_SHIFT 8 5557 5558 /* TX2 :: Tx_ibuff_1T2T :: i21mux [07:05] */ 5559 #define TX2_TX_IBUFF_1T2T_I21MUX_MASK 0x00e0 5560 #define TX2_TX_IBUFF_1T2T_I21MUX_ALIGN 0 5561 #define TX2_TX_IBUFF_1T2T_I21MUX_BITS 3 5562 #define TX2_TX_IBUFF_1T2T_I21MUX_SHIFT 5 5563 5564 /* TX2 :: Tx_ibuff_1T2T :: imin_drvr [04:04] */ 5565 #define TX2_TX_IBUFF_1T2T_IMIN_DRVR_MASK 0x0010 5566 #define TX2_TX_IBUFF_1T2T_IMIN_DRVR_ALIGN 0 5567 #define TX2_TX_IBUFF_1T2T_IMIN_DRVR_BITS 1 5568 #define TX2_TX_IBUFF_1T2T_IMIN_DRVR_SHIFT 4 5569 5570 /* TX2 :: Tx_ibuff_1T2T :: imax_drvr [03:03] */ 5571 #define TX2_TX_IBUFF_1T2T_IMAX_DRVR_MASK 0x0008 5572 #define TX2_TX_IBUFF_1T2T_IMAX_DRVR_ALIGN 0 5573 #define TX2_TX_IBUFF_1T2T_IMAX_DRVR_BITS 1 5574 #define TX2_TX_IBUFF_1T2T_IMAX_DRVR_SHIFT 3 5575 5576 /* TX2 :: Tx_ibuff_1T2T :: imode_drvr [02:02] */ 5577 #define TX2_TX_IBUFF_1T2T_IMODE_DRVR_MASK 0x0004 5578 #define TX2_TX_IBUFF_1T2T_IMODE_DRVR_ALIGN 0 5579 #define TX2_TX_IBUFF_1T2T_IMODE_DRVR_BITS 1 5580 #define TX2_TX_IBUFF_1T2T_IMODE_DRVR_SHIFT 2 5581 5582 /* TX2 :: Tx_ibuff_1T2T :: reserved0 [01:00] */ 5583 #define TX2_TX_IBUFF_1T2T_RESERVED0_MASK 0x0003 5584 #define TX2_TX_IBUFF_1T2T_RESERVED0_ALIGN 0 5585 #define TX2_TX_IBUFF_1T2T_RESERVED0_BITS 2 5586 #define TX2_TX_IBUFF_1T2T_RESERVED0_SHIFT 0 5587 5588 5589 /**************************************************************************** 5590 * TX2 :: Tx_Driver 5591 */ 5592 /* TX2 :: Tx_Driver :: preemphasis_post [15:12] */ 5593 #define TX2_TX_DRIVER_PREEMPHASIS_POST_MASK 0xf000 5594 #define TX2_TX_DRIVER_PREEMPHASIS_POST_ALIGN 0 5595 #define TX2_TX_DRIVER_PREEMPHASIS_POST_BITS 4 5596 #define TX2_TX_DRIVER_PREEMPHASIS_POST_SHIFT 12 5597 5598 /* TX2 :: Tx_Driver :: Idriver [11:08] */ 5599 #define TX2_TX_DRIVER_IDRIVER_MASK 0x0f00 5600 #define TX2_TX_DRIVER_IDRIVER_ALIGN 0 5601 #define TX2_TX_DRIVER_IDRIVER_BITS 4 5602 #define TX2_TX_DRIVER_IDRIVER_SHIFT 8 5603 5604 /* TX2 :: Tx_Driver :: Ipredriver [07:04] */ 5605 #define TX2_TX_DRIVER_IPREDRIVER_MASK 0x00f0 5606 #define TX2_TX_DRIVER_IPREDRIVER_ALIGN 0 5607 #define TX2_TX_DRIVER_IPREDRIVER_BITS 4 5608 #define TX2_TX_DRIVER_IPREDRIVER_SHIFT 4 5609 5610 /* TX2 :: Tx_Driver :: preemphasis_pre [03:01] */ 5611 #define TX2_TX_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 5612 #define TX2_TX_DRIVER_PREEMPHASIS_PRE_ALIGN 0 5613 #define TX2_TX_DRIVER_PREEMPHASIS_PRE_BITS 3 5614 #define TX2_TX_DRIVER_PREEMPHASIS_PRE_SHIFT 1 5615 5616 /* TX2 :: Tx_Driver :: icbuf1t0 [00:00] */ 5617 #define TX2_TX_DRIVER_ICBUF1T0_MASK 0x0001 5618 #define TX2_TX_DRIVER_ICBUF1T0_ALIGN 0 5619 #define TX2_TX_DRIVER_ICBUF1T0_BITS 1 5620 #define TX2_TX_DRIVER_ICBUF1T0_SHIFT 0 5621 5622 5623 /**************************************************************************** 5624 * XGXS16G_USER_TX3 5625 */ 5626 /**************************************************************************** 5627 * TX3 :: Tx_AStatus0 5628 */ 5629 /* TX3 :: Tx_AStatus0 :: reserved0 [15:03] */ 5630 #define TX3_TX_ASTATUS0_RESERVED0_MASK 0xfff8 5631 #define TX3_TX_ASTATUS0_RESERVED0_ALIGN 0 5632 #define TX3_TX_ASTATUS0_RESERVED0_BITS 13 5633 #define TX3_TX_ASTATUS0_RESERVED0_SHIFT 3 5634 5635 /* TX3 :: Tx_AStatus0 :: tx_gloopback [02:02] */ 5636 #define TX3_TX_ASTATUS0_TX_GLOOPBACK_MASK 0x0004 5637 #define TX3_TX_ASTATUS0_TX_GLOOPBACK_ALIGN 0 5638 #define TX3_TX_ASTATUS0_TX_GLOOPBACK_BITS 1 5639 #define TX3_TX_ASTATUS0_TX_GLOOPBACK_SHIFT 2 5640 5641 /* TX3 :: Tx_AStatus0 :: rltxferr [01:01] */ 5642 #define TX3_TX_ASTATUS0_RLTXFERR_MASK 0x0002 5643 #define TX3_TX_ASTATUS0_RLTXFERR_ALIGN 0 5644 #define TX3_TX_ASTATUS0_RLTXFERR_BITS 1 5645 #define TX3_TX_ASTATUS0_RLTXFERR_SHIFT 1 5646 5647 /* TX3 :: Tx_AStatus0 :: txferr [00:00] */ 5648 #define TX3_TX_ASTATUS0_TXFERR_MASK 0x0001 5649 #define TX3_TX_ASTATUS0_TXFERR_ALIGN 0 5650 #define TX3_TX_ASTATUS0_TXFERR_BITS 1 5651 #define TX3_TX_ASTATUS0_TXFERR_SHIFT 0 5652 5653 5654 /**************************************************************************** 5655 * TX3 :: Tx_AControl0 5656 */ 5657 /* TX3 :: Tx_AControl0 :: reserved0 [15:15] */ 5658 #define TX3_TX_ACONTROL0_RESERVED0_MASK 0x8000 5659 #define TX3_TX_ACONTROL0_RESERVED0_ALIGN 0 5660 #define TX3_TX_ACONTROL0_RESERVED0_BITS 1 5661 #define TX3_TX_ACONTROL0_RESERVED0_SHIFT 15 5662 5663 /* TX3 :: Tx_AControl0 :: force_txclk [14:14] */ 5664 #define TX3_TX_ACONTROL0_FORCE_TXCLK_MASK 0x4000 5665 #define TX3_TX_ACONTROL0_FORCE_TXCLK_ALIGN 0 5666 #define TX3_TX_ACONTROL0_FORCE_TXCLK_BITS 1 5667 #define TX3_TX_ACONTROL0_FORCE_TXCLK_SHIFT 14 5668 5669 /* TX3 :: Tx_AControl0 :: tx1g_fifo_rst [13:13] */ 5670 #define TX3_TX_ACONTROL0_TX1G_FIFO_RST_MASK 0x2000 5671 #define TX3_TX_ACONTROL0_TX1G_FIFO_RST_ALIGN 0 5672 #define TX3_TX_ACONTROL0_TX1G_FIFO_RST_BITS 1 5673 #define TX3_TX_ACONTROL0_TX1G_FIFO_RST_SHIFT 13 5674 5675 /* TX3 :: Tx_AControl0 :: gloopOutEn [12:12] */ 5676 #define TX3_TX_ACONTROL0_GLOOPOUTEN_MASK 0x1000 5677 #define TX3_TX_ACONTROL0_GLOOPOUTEN_ALIGN 0 5678 #define TX3_TX_ACONTROL0_GLOOPOUTEN_BITS 1 5679 #define TX3_TX_ACONTROL0_GLOOPOUTEN_SHIFT 12 5680 5681 /* TX3 :: Tx_AControl0 :: reserved1 [11:09] */ 5682 #define TX3_TX_ACONTROL0_RESERVED1_MASK 0x0e00 5683 #define TX3_TX_ACONTROL0_RESERVED1_ALIGN 0 5684 #define TX3_TX_ACONTROL0_RESERVED1_BITS 3 5685 #define TX3_TX_ACONTROL0_RESERVED1_SHIFT 9 5686 5687 /* TX3 :: Tx_AControl0 :: prbs_en [08:08] */ 5688 #define TX3_TX_ACONTROL0_PRBS_EN_MASK 0x0100 5689 #define TX3_TX_ACONTROL0_PRBS_EN_ALIGN 0 5690 #define TX3_TX_ACONTROL0_PRBS_EN_BITS 1 5691 #define TX3_TX_ACONTROL0_PRBS_EN_SHIFT 8 5692 5693 /* TX3 :: Tx_AControl0 :: pckt_en [07:07] */ 5694 #define TX3_TX_ACONTROL0_PCKT_EN_MASK 0x0080 5695 #define TX3_TX_ACONTROL0_PCKT_EN_ALIGN 0 5696 #define TX3_TX_ACONTROL0_PCKT_EN_BITS 1 5697 #define TX3_TX_ACONTROL0_PCKT_EN_SHIFT 7 5698 5699 /* TX3 :: Tx_AControl0 :: pckt_strt [06:06] */ 5700 #define TX3_TX_ACONTROL0_PCKT_STRT_MASK 0x0040 5701 #define TX3_TX_ACONTROL0_PCKT_STRT_ALIGN 0 5702 #define TX3_TX_ACONTROL0_PCKT_STRT_BITS 1 5703 #define TX3_TX_ACONTROL0_PCKT_STRT_SHIFT 6 5704 5705 /* TX3 :: Tx_AControl0 :: txpol_flip [05:05] */ 5706 #define TX3_TX_ACONTROL0_TXPOL_FLIP_MASK 0x0020 5707 #define TX3_TX_ACONTROL0_TXPOL_FLIP_ALIGN 0 5708 #define TX3_TX_ACONTROL0_TXPOL_FLIP_BITS 1 5709 #define TX3_TX_ACONTROL0_TXPOL_FLIP_SHIFT 5 5710 5711 /* TX3 :: Tx_AControl0 :: rtbi_flip [04:04] */ 5712 #define TX3_TX_ACONTROL0_RTBI_FLIP_MASK 0x0010 5713 #define TX3_TX_ACONTROL0_RTBI_FLIP_ALIGN 0 5714 #define TX3_TX_ACONTROL0_RTBI_FLIP_BITS 1 5715 #define TX3_TX_ACONTROL0_RTBI_FLIP_SHIFT 4 5716 5717 /* TX3 :: Tx_AControl0 :: eden_r [03:03] */ 5718 #define TX3_TX_ACONTROL0_EDEN_R_MASK 0x0008 5719 #define TX3_TX_ACONTROL0_EDEN_R_ALIGN 0 5720 #define TX3_TX_ACONTROL0_EDEN_R_BITS 1 5721 #define TX3_TX_ACONTROL0_EDEN_R_SHIFT 3 5722 5723 /* TX3 :: Tx_AControl0 :: eden_force_r [02:02] */ 5724 #define TX3_TX_ACONTROL0_EDEN_FORCE_R_MASK 0x0004 5725 #define TX3_TX_ACONTROL0_EDEN_FORCE_R_ALIGN 0 5726 #define TX3_TX_ACONTROL0_EDEN_FORCE_R_BITS 1 5727 #define TX3_TX_ACONTROL0_EDEN_FORCE_R_SHIFT 2 5728 5729 /* TX3 :: Tx_AControl0 :: txpat_en [01:01] */ 5730 #define TX3_TX_ACONTROL0_TXPAT_EN_MASK 0x0002 5731 #define TX3_TX_ACONTROL0_TXPAT_EN_ALIGN 0 5732 #define TX3_TX_ACONTROL0_TXPAT_EN_BITS 1 5733 #define TX3_TX_ACONTROL0_TXPAT_EN_SHIFT 1 5734 5735 /* TX3 :: Tx_AControl0 :: tx_mdata_en [00:00] */ 5736 #define TX3_TX_ACONTROL0_TX_MDATA_EN_MASK 0x0001 5737 #define TX3_TX_ACONTROL0_TX_MDATA_EN_ALIGN 0 5738 #define TX3_TX_ACONTROL0_TX_MDATA_EN_BITS 1 5739 #define TX3_TX_ACONTROL0_TX_MDATA_EN_SHIFT 0 5740 5741 5742 /**************************************************************************** 5743 * TX3 :: Tx_mdata0 5744 */ 5745 /* TX3 :: Tx_mdata0 :: txTestMuxSel [15:13] */ 5746 #define TX3_TX_MDATA0_TXTESTMUXSEL_MASK 0xe000 5747 #define TX3_TX_MDATA0_TXTESTMUXSEL_ALIGN 0 5748 #define TX3_TX_MDATA0_TXTESTMUXSEL_BITS 3 5749 #define TX3_TX_MDATA0_TXTESTMUXSEL_SHIFT 13 5750 5751 /* TX3 :: Tx_mdata0 :: rlfifo_tstsel [12:10] */ 5752 #define TX3_TX_MDATA0_RLFIFO_TSTSEL_MASK 0x1c00 5753 #define TX3_TX_MDATA0_RLFIFO_TSTSEL_ALIGN 0 5754 #define TX3_TX_MDATA0_RLFIFO_TSTSEL_BITS 3 5755 #define TX3_TX_MDATA0_RLFIFO_TSTSEL_SHIFT 10 5756 5757 /* TX3 :: Tx_mdata0 :: TxMdioTstDataL [09:00] */ 5758 #define TX3_TX_MDATA0_TXMDIOTSTDATAL_MASK 0x03ff 5759 #define TX3_TX_MDATA0_TXMDIOTSTDATAL_ALIGN 0 5760 #define TX3_TX_MDATA0_TXMDIOTSTDATAL_BITS 10 5761 #define TX3_TX_MDATA0_TXMDIOTSTDATAL_SHIFT 0 5762 5763 5764 /**************************************************************************** 5765 * TX3 :: Tx_mdata1 5766 */ 5767 /* TX3 :: Tx_mdata1 :: reserved0 [15:10] */ 5768 #define TX3_TX_MDATA1_RESERVED0_MASK 0xfc00 5769 #define TX3_TX_MDATA1_RESERVED0_ALIGN 0 5770 #define TX3_TX_MDATA1_RESERVED0_BITS 6 5771 #define TX3_TX_MDATA1_RESERVED0_SHIFT 10 5772 5773 /* TX3 :: Tx_mdata1 :: TxMdioTstDataH [09:00] */ 5774 #define TX3_TX_MDATA1_TXMDIOTSTDATAH_MASK 0x03ff 5775 #define TX3_TX_MDATA1_TXMDIOTSTDATAH_ALIGN 0 5776 #define TX3_TX_MDATA1_TXMDIOTSTDATAH_BITS 10 5777 #define TX3_TX_MDATA1_TXMDIOTSTDATAH_SHIFT 0 5778 5779 5780 /**************************************************************************** 5781 * TX3 :: Tx_AStatus1 5782 */ 5783 /* TX3 :: Tx_AStatus1 :: tx_id [15:14] */ 5784 #define TX3_TX_ASTATUS1_TX_ID_MASK 0xc000 5785 #define TX3_TX_ASTATUS1_TX_ID_ALIGN 0 5786 #define TX3_TX_ASTATUS1_TX_ID_BITS 2 5787 #define TX3_TX_ASTATUS1_TX_ID_SHIFT 14 5788 5789 /* TX3 :: Tx_AStatus1 :: reserved0 [13:00] */ 5790 #define TX3_TX_ASTATUS1_RESERVED0_MASK 0x3fff 5791 #define TX3_TX_ASTATUS1_RESERVED0_ALIGN 0 5792 #define TX3_TX_ASTATUS1_RESERVED0_BITS 14 5793 #define TX3_TX_ASTATUS1_RESERVED0_SHIFT 0 5794 5795 5796 /**************************************************************************** 5797 * TX3 :: Tx_BgVcm 5798 */ 5799 /* TX3 :: Tx_BgVcm :: id2c [15:13] */ 5800 #define TX3_TX_BGVCM_ID2C_MASK 0xe000 5801 #define TX3_TX_BGVCM_ID2C_ALIGN 0 5802 #define TX3_TX_BGVCM_ID2C_BITS 3 5803 #define TX3_TX_BGVCM_ID2C_SHIFT 13 5804 5805 /* TX3 :: Tx_BgVcm :: refl_tx [12:12] */ 5806 #define TX3_TX_BGVCM_REFL_TX_MASK 0x1000 5807 #define TX3_TX_BGVCM_REFL_TX_ALIGN 0 5808 #define TX3_TX_BGVCM_REFL_TX_BITS 1 5809 #define TX3_TX_BGVCM_REFL_TX_SHIFT 12 5810 5811 /* TX3 :: Tx_BgVcm :: refh_tx [11:11] */ 5812 #define TX3_TX_BGVCM_REFH_TX_MASK 0x0800 5813 #define TX3_TX_BGVCM_REFH_TX_ALIGN 0 5814 #define TX3_TX_BGVCM_REFH_TX_BITS 1 5815 #define TX3_TX_BGVCM_REFH_TX_SHIFT 11 5816 5817 /* TX3 :: Tx_BgVcm :: newbias_en [10:10] */ 5818 #define TX3_TX_BGVCM_NEWBIAS_EN_MASK 0x0400 5819 #define TX3_TX_BGVCM_NEWBIAS_EN_ALIGN 0 5820 #define TX3_TX_BGVCM_NEWBIAS_EN_BITS 1 5821 #define TX3_TX_BGVCM_NEWBIAS_EN_SHIFT 10 5822 5823 /* TX3 :: Tx_BgVcm :: drivermode [09:09] */ 5824 #define TX3_TX_BGVCM_DRIVERMODE_MASK 0x0200 5825 #define TX3_TX_BGVCM_DRIVERMODE_ALIGN 0 5826 #define TX3_TX_BGVCM_DRIVERMODE_BITS 1 5827 #define TX3_TX_BGVCM_DRIVERMODE_SHIFT 9 5828 5829 /* TX3 :: Tx_BgVcm :: bddr_bgb [08:08] */ 5830 #define TX3_TX_BGVCM_BDDR_BGB_MASK 0x0100 5831 #define TX3_TX_BGVCM_BDDR_BGB_ALIGN 0 5832 #define TX3_TX_BGVCM_BDDR_BGB_BITS 1 5833 #define TX3_TX_BGVCM_BDDR_BGB_SHIFT 8 5834 5835 /* TX3 :: Tx_BgVcm :: ticksel [07:06] */ 5836 #define TX3_TX_BGVCM_TICKSEL_MASK 0x00c0 5837 #define TX3_TX_BGVCM_TICKSEL_ALIGN 0 5838 #define TX3_TX_BGVCM_TICKSEL_BITS 2 5839 #define TX3_TX_BGVCM_TICKSEL_SHIFT 6 5840 5841 /* TX3 :: Tx_BgVcm :: driver_vcm [05:04] */ 5842 #define TX3_TX_BGVCM_DRIVER_VCM_MASK 0x0030 5843 #define TX3_TX_BGVCM_DRIVER_VCM_ALIGN 0 5844 #define TX3_TX_BGVCM_DRIVER_VCM_BITS 2 5845 #define TX3_TX_BGVCM_DRIVER_VCM_SHIFT 4 5846 5847 /* TX3 :: Tx_BgVcm :: tx_sel_halfrate [03:03] */ 5848 #define TX3_TX_BGVCM_TX_SEL_HALFRATE_MASK 0x0008 5849 #define TX3_TX_BGVCM_TX_SEL_HALFRATE_ALIGN 0 5850 #define TX3_TX_BGVCM_TX_SEL_HALFRATE_BITS 1 5851 #define TX3_TX_BGVCM_TX_SEL_HALFRATE_SHIFT 3 5852 5853 /* TX3 :: Tx_BgVcm :: ifullspd [02:00] */ 5854 #define TX3_TX_BGVCM_IFULLSPD_MASK 0x0007 5855 #define TX3_TX_BGVCM_IFULLSPD_ALIGN 0 5856 #define TX3_TX_BGVCM_IFULLSPD_BITS 3 5857 #define TX3_TX_BGVCM_IFULLSPD_SHIFT 0 5858 5859 5860 /**************************************************************************** 5861 * TX3 :: Tx_ibuff_1T2T 5862 */ 5863 /* TX3 :: Tx_ibuff_1T2T :: icbuf1t [15:14] */ 5864 #define TX3_TX_IBUFF_1T2T_ICBUF1T_MASK 0xc000 5865 #define TX3_TX_IBUFF_1T2T_ICBUF1T_ALIGN 0 5866 #define TX3_TX_IBUFF_1T2T_ICBUF1T_BITS 2 5867 #define TX3_TX_IBUFF_1T2T_ICBUF1T_SHIFT 14 5868 5869 /* TX3 :: Tx_ibuff_1T2T :: icbuf2t [13:11] */ 5870 #define TX3_TX_IBUFF_1T2T_ICBUF2T_MASK 0x3800 5871 #define TX3_TX_IBUFF_1T2T_ICBUF2T_ALIGN 0 5872 #define TX3_TX_IBUFF_1T2T_ICBUF2T_BITS 3 5873 #define TX3_TX_IBUFF_1T2T_ICBUF2T_SHIFT 11 5874 5875 /* TX3 :: Tx_ibuff_1T2T :: imin_predrv [10:10] */ 5876 #define TX3_TX_IBUFF_1T2T_IMIN_PREDRV_MASK 0x0400 5877 #define TX3_TX_IBUFF_1T2T_IMIN_PREDRV_ALIGN 0 5878 #define TX3_TX_IBUFF_1T2T_IMIN_PREDRV_BITS 1 5879 #define TX3_TX_IBUFF_1T2T_IMIN_PREDRV_SHIFT 10 5880 5881 /* TX3 :: Tx_ibuff_1T2T :: imax_predrv [09:09] */ 5882 #define TX3_TX_IBUFF_1T2T_IMAX_PREDRV_MASK 0x0200 5883 #define TX3_TX_IBUFF_1T2T_IMAX_PREDRV_ALIGN 0 5884 #define TX3_TX_IBUFF_1T2T_IMAX_PREDRV_BITS 1 5885 #define TX3_TX_IBUFF_1T2T_IMAX_PREDRV_SHIFT 9 5886 5887 /* TX3 :: Tx_ibuff_1T2T :: imode_predrv [08:08] */ 5888 #define TX3_TX_IBUFF_1T2T_IMODE_PREDRV_MASK 0x0100 5889 #define TX3_TX_IBUFF_1T2T_IMODE_PREDRV_ALIGN 0 5890 #define TX3_TX_IBUFF_1T2T_IMODE_PREDRV_BITS 1 5891 #define TX3_TX_IBUFF_1T2T_IMODE_PREDRV_SHIFT 8 5892 5893 /* TX3 :: Tx_ibuff_1T2T :: i21mux [07:05] */ 5894 #define TX3_TX_IBUFF_1T2T_I21MUX_MASK 0x00e0 5895 #define TX3_TX_IBUFF_1T2T_I21MUX_ALIGN 0 5896 #define TX3_TX_IBUFF_1T2T_I21MUX_BITS 3 5897 #define TX3_TX_IBUFF_1T2T_I21MUX_SHIFT 5 5898 5899 /* TX3 :: Tx_ibuff_1T2T :: imin_drvr [04:04] */ 5900 #define TX3_TX_IBUFF_1T2T_IMIN_DRVR_MASK 0x0010 5901 #define TX3_TX_IBUFF_1T2T_IMIN_DRVR_ALIGN 0 5902 #define TX3_TX_IBUFF_1T2T_IMIN_DRVR_BITS 1 5903 #define TX3_TX_IBUFF_1T2T_IMIN_DRVR_SHIFT 4 5904 5905 /* TX3 :: Tx_ibuff_1T2T :: imax_drvr [03:03] */ 5906 #define TX3_TX_IBUFF_1T2T_IMAX_DRVR_MASK 0x0008 5907 #define TX3_TX_IBUFF_1T2T_IMAX_DRVR_ALIGN 0 5908 #define TX3_TX_IBUFF_1T2T_IMAX_DRVR_BITS 1 5909 #define TX3_TX_IBUFF_1T2T_IMAX_DRVR_SHIFT 3 5910 5911 /* TX3 :: Tx_ibuff_1T2T :: imode_drvr [02:02] */ 5912 #define TX3_TX_IBUFF_1T2T_IMODE_DRVR_MASK 0x0004 5913 #define TX3_TX_IBUFF_1T2T_IMODE_DRVR_ALIGN 0 5914 #define TX3_TX_IBUFF_1T2T_IMODE_DRVR_BITS 1 5915 #define TX3_TX_IBUFF_1T2T_IMODE_DRVR_SHIFT 2 5916 5917 /* TX3 :: Tx_ibuff_1T2T :: reserved0 [01:00] */ 5918 #define TX3_TX_IBUFF_1T2T_RESERVED0_MASK 0x0003 5919 #define TX3_TX_IBUFF_1T2T_RESERVED0_ALIGN 0 5920 #define TX3_TX_IBUFF_1T2T_RESERVED0_BITS 2 5921 #define TX3_TX_IBUFF_1T2T_RESERVED0_SHIFT 0 5922 5923 5924 /**************************************************************************** 5925 * TX3 :: Tx_Driver 5926 */ 5927 /* TX3 :: Tx_Driver :: preemphasis_post [15:12] */ 5928 #define TX3_TX_DRIVER_PREEMPHASIS_POST_MASK 0xf000 5929 #define TX3_TX_DRIVER_PREEMPHASIS_POST_ALIGN 0 5930 #define TX3_TX_DRIVER_PREEMPHASIS_POST_BITS 4 5931 #define TX3_TX_DRIVER_PREEMPHASIS_POST_SHIFT 12 5932 5933 /* TX3 :: Tx_Driver :: Idriver [11:08] */ 5934 #define TX3_TX_DRIVER_IDRIVER_MASK 0x0f00 5935 #define TX3_TX_DRIVER_IDRIVER_ALIGN 0 5936 #define TX3_TX_DRIVER_IDRIVER_BITS 4 5937 #define TX3_TX_DRIVER_IDRIVER_SHIFT 8 5938 5939 /* TX3 :: Tx_Driver :: Ipredriver [07:04] */ 5940 #define TX3_TX_DRIVER_IPREDRIVER_MASK 0x00f0 5941 #define TX3_TX_DRIVER_IPREDRIVER_ALIGN 0 5942 #define TX3_TX_DRIVER_IPREDRIVER_BITS 4 5943 #define TX3_TX_DRIVER_IPREDRIVER_SHIFT 4 5944 5945 /* TX3 :: Tx_Driver :: preemphasis_pre [03:01] */ 5946 #define TX3_TX_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 5947 #define TX3_TX_DRIVER_PREEMPHASIS_PRE_ALIGN 0 5948 #define TX3_TX_DRIVER_PREEMPHASIS_PRE_BITS 3 5949 #define TX3_TX_DRIVER_PREEMPHASIS_PRE_SHIFT 1 5950 5951 /* TX3 :: Tx_Driver :: icbuf1t0 [00:00] */ 5952 #define TX3_TX_DRIVER_ICBUF1T0_MASK 0x0001 5953 #define TX3_TX_DRIVER_ICBUF1T0_ALIGN 0 5954 #define TX3_TX_DRIVER_ICBUF1T0_BITS 1 5955 #define TX3_TX_DRIVER_ICBUF1T0_SHIFT 0 5956 5957 5958 /**************************************************************************** 5959 * XGXS16G_USER_TX_All 5960 */ 5961 /**************************************************************************** 5962 * TX_All :: Tx_AStatus0 5963 */ 5964 /* TX_All :: Tx_AStatus0 :: reserved0 [15:03] */ 5965 #define TX_ALL_TX_ASTATUS0_RESERVED0_MASK 0xfff8 5966 #define TX_ALL_TX_ASTATUS0_RESERVED0_ALIGN 0 5967 #define TX_ALL_TX_ASTATUS0_RESERVED0_BITS 13 5968 #define TX_ALL_TX_ASTATUS0_RESERVED0_SHIFT 3 5969 5970 /* TX_All :: Tx_AStatus0 :: tx_gloopback [02:02] */ 5971 #define TX_ALL_TX_ASTATUS0_TX_GLOOPBACK_MASK 0x0004 5972 #define TX_ALL_TX_ASTATUS0_TX_GLOOPBACK_ALIGN 0 5973 #define TX_ALL_TX_ASTATUS0_TX_GLOOPBACK_BITS 1 5974 #define TX_ALL_TX_ASTATUS0_TX_GLOOPBACK_SHIFT 2 5975 5976 /* TX_All :: Tx_AStatus0 :: rltxferr [01:01] */ 5977 #define TX_ALL_TX_ASTATUS0_RLTXFERR_MASK 0x0002 5978 #define TX_ALL_TX_ASTATUS0_RLTXFERR_ALIGN 0 5979 #define TX_ALL_TX_ASTATUS0_RLTXFERR_BITS 1 5980 #define TX_ALL_TX_ASTATUS0_RLTXFERR_SHIFT 1 5981 5982 /* TX_All :: Tx_AStatus0 :: txferr [00:00] */ 5983 #define TX_ALL_TX_ASTATUS0_TXFERR_MASK 0x0001 5984 #define TX_ALL_TX_ASTATUS0_TXFERR_ALIGN 0 5985 #define TX_ALL_TX_ASTATUS0_TXFERR_BITS 1 5986 #define TX_ALL_TX_ASTATUS0_TXFERR_SHIFT 0 5987 5988 5989 /**************************************************************************** 5990 * TX_All :: Tx_AControl0 5991 */ 5992 /* TX_All :: Tx_AControl0 :: reserved0 [15:15] */ 5993 #define TX_ALL_TX_ACONTROL0_RESERVED0_MASK 0x8000 5994 #define TX_ALL_TX_ACONTROL0_RESERVED0_ALIGN 0 5995 #define TX_ALL_TX_ACONTROL0_RESERVED0_BITS 1 5996 #define TX_ALL_TX_ACONTROL0_RESERVED0_SHIFT 15 5997 5998 /* TX_All :: Tx_AControl0 :: force_txclk [14:14] */ 5999 #define TX_ALL_TX_ACONTROL0_FORCE_TXCLK_MASK 0x4000 6000 #define TX_ALL_TX_ACONTROL0_FORCE_TXCLK_ALIGN 0 6001 #define TX_ALL_TX_ACONTROL0_FORCE_TXCLK_BITS 1 6002 #define TX_ALL_TX_ACONTROL0_FORCE_TXCLK_SHIFT 14 6003 6004 /* TX_All :: Tx_AControl0 :: tx1g_fifo_rst [13:13] */ 6005 #define TX_ALL_TX_ACONTROL0_TX1G_FIFO_RST_MASK 0x2000 6006 #define TX_ALL_TX_ACONTROL0_TX1G_FIFO_RST_ALIGN 0 6007 #define TX_ALL_TX_ACONTROL0_TX1G_FIFO_RST_BITS 1 6008 #define TX_ALL_TX_ACONTROL0_TX1G_FIFO_RST_SHIFT 13 6009 6010 /* TX_All :: Tx_AControl0 :: gloopOutEn [12:12] */ 6011 #define TX_ALL_TX_ACONTROL0_GLOOPOUTEN_MASK 0x1000 6012 #define TX_ALL_TX_ACONTROL0_GLOOPOUTEN_ALIGN 0 6013 #define TX_ALL_TX_ACONTROL0_GLOOPOUTEN_BITS 1 6014 #define TX_ALL_TX_ACONTROL0_GLOOPOUTEN_SHIFT 12 6015 6016 /* TX_All :: Tx_AControl0 :: reserved1 [11:09] */ 6017 #define TX_ALL_TX_ACONTROL0_RESERVED1_MASK 0x0e00 6018 #define TX_ALL_TX_ACONTROL0_RESERVED1_ALIGN 0 6019 #define TX_ALL_TX_ACONTROL0_RESERVED1_BITS 3 6020 #define TX_ALL_TX_ACONTROL0_RESERVED1_SHIFT 9 6021 6022 /* TX_All :: Tx_AControl0 :: prbs_en [08:08] */ 6023 #define TX_ALL_TX_ACONTROL0_PRBS_EN_MASK 0x0100 6024 #define TX_ALL_TX_ACONTROL0_PRBS_EN_ALIGN 0 6025 #define TX_ALL_TX_ACONTROL0_PRBS_EN_BITS 1 6026 #define TX_ALL_TX_ACONTROL0_PRBS_EN_SHIFT 8 6027 6028 /* TX_All :: Tx_AControl0 :: pckt_en [07:07] */ 6029 #define TX_ALL_TX_ACONTROL0_PCKT_EN_MASK 0x0080 6030 #define TX_ALL_TX_ACONTROL0_PCKT_EN_ALIGN 0 6031 #define TX_ALL_TX_ACONTROL0_PCKT_EN_BITS 1 6032 #define TX_ALL_TX_ACONTROL0_PCKT_EN_SHIFT 7 6033 6034 /* TX_All :: Tx_AControl0 :: pckt_strt [06:06] */ 6035 #define TX_ALL_TX_ACONTROL0_PCKT_STRT_MASK 0x0040 6036 #define TX_ALL_TX_ACONTROL0_PCKT_STRT_ALIGN 0 6037 #define TX_ALL_TX_ACONTROL0_PCKT_STRT_BITS 1 6038 #define TX_ALL_TX_ACONTROL0_PCKT_STRT_SHIFT 6 6039 6040 /* TX_All :: Tx_AControl0 :: txpol_flip [05:05] */ 6041 #define TX_ALL_TX_ACONTROL0_TXPOL_FLIP_MASK 0x0020 6042 #define TX_ALL_TX_ACONTROL0_TXPOL_FLIP_ALIGN 0 6043 #define TX_ALL_TX_ACONTROL0_TXPOL_FLIP_BITS 1 6044 #define TX_ALL_TX_ACONTROL0_TXPOL_FLIP_SHIFT 5 6045 6046 /* TX_All :: Tx_AControl0 :: rtbi_flip [04:04] */ 6047 #define TX_ALL_TX_ACONTROL0_RTBI_FLIP_MASK 0x0010 6048 #define TX_ALL_TX_ACONTROL0_RTBI_FLIP_ALIGN 0 6049 #define TX_ALL_TX_ACONTROL0_RTBI_FLIP_BITS 1 6050 #define TX_ALL_TX_ACONTROL0_RTBI_FLIP_SHIFT 4 6051 6052 /* TX_All :: Tx_AControl0 :: eden_r [03:03] */ 6053 #define TX_ALL_TX_ACONTROL0_EDEN_R_MASK 0x0008 6054 #define TX_ALL_TX_ACONTROL0_EDEN_R_ALIGN 0 6055 #define TX_ALL_TX_ACONTROL0_EDEN_R_BITS 1 6056 #define TX_ALL_TX_ACONTROL0_EDEN_R_SHIFT 3 6057 6058 /* TX_All :: Tx_AControl0 :: eden_force_r [02:02] */ 6059 #define TX_ALL_TX_ACONTROL0_EDEN_FORCE_R_MASK 0x0004 6060 #define TX_ALL_TX_ACONTROL0_EDEN_FORCE_R_ALIGN 0 6061 #define TX_ALL_TX_ACONTROL0_EDEN_FORCE_R_BITS 1 6062 #define TX_ALL_TX_ACONTROL0_EDEN_FORCE_R_SHIFT 2 6063 6064 /* TX_All :: Tx_AControl0 :: txpat_en [01:01] */ 6065 #define TX_ALL_TX_ACONTROL0_TXPAT_EN_MASK 0x0002 6066 #define TX_ALL_TX_ACONTROL0_TXPAT_EN_ALIGN 0 6067 #define TX_ALL_TX_ACONTROL0_TXPAT_EN_BITS 1 6068 #define TX_ALL_TX_ACONTROL0_TXPAT_EN_SHIFT 1 6069 6070 /* TX_All :: Tx_AControl0 :: tx_mdata_en [00:00] */ 6071 #define TX_ALL_TX_ACONTROL0_TX_MDATA_EN_MASK 0x0001 6072 #define TX_ALL_TX_ACONTROL0_TX_MDATA_EN_ALIGN 0 6073 #define TX_ALL_TX_ACONTROL0_TX_MDATA_EN_BITS 1 6074 #define TX_ALL_TX_ACONTROL0_TX_MDATA_EN_SHIFT 0 6075 6076 6077 /**************************************************************************** 6078 * TX_All :: Tx_mdata0 6079 */ 6080 /* TX_All :: Tx_mdata0 :: txTestMuxSel [15:13] */ 6081 #define TX_ALL_TX_MDATA0_TXTESTMUXSEL_MASK 0xe000 6082 #define TX_ALL_TX_MDATA0_TXTESTMUXSEL_ALIGN 0 6083 #define TX_ALL_TX_MDATA0_TXTESTMUXSEL_BITS 3 6084 #define TX_ALL_TX_MDATA0_TXTESTMUXSEL_SHIFT 13 6085 6086 /* TX_All :: Tx_mdata0 :: rlfifo_tstsel [12:10] */ 6087 #define TX_ALL_TX_MDATA0_RLFIFO_TSTSEL_MASK 0x1c00 6088 #define TX_ALL_TX_MDATA0_RLFIFO_TSTSEL_ALIGN 0 6089 #define TX_ALL_TX_MDATA0_RLFIFO_TSTSEL_BITS 3 6090 #define TX_ALL_TX_MDATA0_RLFIFO_TSTSEL_SHIFT 10 6091 6092 /* TX_All :: Tx_mdata0 :: TxMdioTstDataL [09:00] */ 6093 #define TX_ALL_TX_MDATA0_TXMDIOTSTDATAL_MASK 0x03ff 6094 #define TX_ALL_TX_MDATA0_TXMDIOTSTDATAL_ALIGN 0 6095 #define TX_ALL_TX_MDATA0_TXMDIOTSTDATAL_BITS 10 6096 #define TX_ALL_TX_MDATA0_TXMDIOTSTDATAL_SHIFT 0 6097 6098 6099 /**************************************************************************** 6100 * TX_All :: Tx_mdata1 6101 */ 6102 /* TX_All :: Tx_mdata1 :: reserved0 [15:10] */ 6103 #define TX_ALL_TX_MDATA1_RESERVED0_MASK 0xfc00 6104 #define TX_ALL_TX_MDATA1_RESERVED0_ALIGN 0 6105 #define TX_ALL_TX_MDATA1_RESERVED0_BITS 6 6106 #define TX_ALL_TX_MDATA1_RESERVED0_SHIFT 10 6107 6108 /* TX_All :: Tx_mdata1 :: TxMdioTstDataH [09:00] */ 6109 #define TX_ALL_TX_MDATA1_TXMDIOTSTDATAH_MASK 0x03ff 6110 #define TX_ALL_TX_MDATA1_TXMDIOTSTDATAH_ALIGN 0 6111 #define TX_ALL_TX_MDATA1_TXMDIOTSTDATAH_BITS 10 6112 #define TX_ALL_TX_MDATA1_TXMDIOTSTDATAH_SHIFT 0 6113 6114 6115 /**************************************************************************** 6116 * TX_All :: Tx_AStatus1 6117 */ 6118 /* TX_All :: Tx_AStatus1 :: tx_id [15:14] */ 6119 #define TX_ALL_TX_ASTATUS1_TX_ID_MASK 0xc000 6120 #define TX_ALL_TX_ASTATUS1_TX_ID_ALIGN 0 6121 #define TX_ALL_TX_ASTATUS1_TX_ID_BITS 2 6122 #define TX_ALL_TX_ASTATUS1_TX_ID_SHIFT 14 6123 6124 /* TX_All :: Tx_AStatus1 :: reserved0 [13:00] */ 6125 #define TX_ALL_TX_ASTATUS1_RESERVED0_MASK 0x3fff 6126 #define TX_ALL_TX_ASTATUS1_RESERVED0_ALIGN 0 6127 #define TX_ALL_TX_ASTATUS1_RESERVED0_BITS 14 6128 #define TX_ALL_TX_ASTATUS1_RESERVED0_SHIFT 0 6129 6130 6131 /**************************************************************************** 6132 * TX_All :: Tx_BgVcm 6133 */ 6134 /* TX_All :: Tx_BgVcm :: id2c [15:13] */ 6135 #define TX_ALL_TX_BGVCM_ID2C_MASK 0xe000 6136 #define TX_ALL_TX_BGVCM_ID2C_ALIGN 0 6137 #define TX_ALL_TX_BGVCM_ID2C_BITS 3 6138 #define TX_ALL_TX_BGVCM_ID2C_SHIFT 13 6139 6140 /* TX_All :: Tx_BgVcm :: refl_tx [12:12] */ 6141 #define TX_ALL_TX_BGVCM_REFL_TX_MASK 0x1000 6142 #define TX_ALL_TX_BGVCM_REFL_TX_ALIGN 0 6143 #define TX_ALL_TX_BGVCM_REFL_TX_BITS 1 6144 #define TX_ALL_TX_BGVCM_REFL_TX_SHIFT 12 6145 6146 /* TX_All :: Tx_BgVcm :: refh_tx [11:11] */ 6147 #define TX_ALL_TX_BGVCM_REFH_TX_MASK 0x0800 6148 #define TX_ALL_TX_BGVCM_REFH_TX_ALIGN 0 6149 #define TX_ALL_TX_BGVCM_REFH_TX_BITS 1 6150 #define TX_ALL_TX_BGVCM_REFH_TX_SHIFT 11 6151 6152 /* TX_All :: Tx_BgVcm :: newbias_en [10:10] */ 6153 #define TX_ALL_TX_BGVCM_NEWBIAS_EN_MASK 0x0400 6154 #define TX_ALL_TX_BGVCM_NEWBIAS_EN_ALIGN 0 6155 #define TX_ALL_TX_BGVCM_NEWBIAS_EN_BITS 1 6156 #define TX_ALL_TX_BGVCM_NEWBIAS_EN_SHIFT 10 6157 6158 /* TX_All :: Tx_BgVcm :: drivermode [09:09] */ 6159 #define TX_ALL_TX_BGVCM_DRIVERMODE_MASK 0x0200 6160 #define TX_ALL_TX_BGVCM_DRIVERMODE_ALIGN 0 6161 #define TX_ALL_TX_BGVCM_DRIVERMODE_BITS 1 6162 #define TX_ALL_TX_BGVCM_DRIVERMODE_SHIFT 9 6163 6164 /* TX_All :: Tx_BgVcm :: bddr_bgb [08:08] */ 6165 #define TX_ALL_TX_BGVCM_BDDR_BGB_MASK 0x0100 6166 #define TX_ALL_TX_BGVCM_BDDR_BGB_ALIGN 0 6167 #define TX_ALL_TX_BGVCM_BDDR_BGB_BITS 1 6168 #define TX_ALL_TX_BGVCM_BDDR_BGB_SHIFT 8 6169 6170 /* TX_All :: Tx_BgVcm :: ticksel [07:06] */ 6171 #define TX_ALL_TX_BGVCM_TICKSEL_MASK 0x00c0 6172 #define TX_ALL_TX_BGVCM_TICKSEL_ALIGN 0 6173 #define TX_ALL_TX_BGVCM_TICKSEL_BITS 2 6174 #define TX_ALL_TX_BGVCM_TICKSEL_SHIFT 6 6175 6176 /* TX_All :: Tx_BgVcm :: driver_vcm [05:04] */ 6177 #define TX_ALL_TX_BGVCM_DRIVER_VCM_MASK 0x0030 6178 #define TX_ALL_TX_BGVCM_DRIVER_VCM_ALIGN 0 6179 #define TX_ALL_TX_BGVCM_DRIVER_VCM_BITS 2 6180 #define TX_ALL_TX_BGVCM_DRIVER_VCM_SHIFT 4 6181 6182 /* TX_All :: Tx_BgVcm :: tx_sel_halfrate [03:03] */ 6183 #define TX_ALL_TX_BGVCM_TX_SEL_HALFRATE_MASK 0x0008 6184 #define TX_ALL_TX_BGVCM_TX_SEL_HALFRATE_ALIGN 0 6185 #define TX_ALL_TX_BGVCM_TX_SEL_HALFRATE_BITS 1 6186 #define TX_ALL_TX_BGVCM_TX_SEL_HALFRATE_SHIFT 3 6187 6188 /* TX_All :: Tx_BgVcm :: ifullspd [02:00] */ 6189 #define TX_ALL_TX_BGVCM_IFULLSPD_MASK 0x0007 6190 #define TX_ALL_TX_BGVCM_IFULLSPD_ALIGN 0 6191 #define TX_ALL_TX_BGVCM_IFULLSPD_BITS 3 6192 #define TX_ALL_TX_BGVCM_IFULLSPD_SHIFT 0 6193 6194 6195 /**************************************************************************** 6196 * TX_All :: Tx_ibuff_1T2T 6197 */ 6198 /* TX_All :: Tx_ibuff_1T2T :: icbuf1t [15:14] */ 6199 #define TX_ALL_TX_IBUFF_1T2T_ICBUF1T_MASK 0xc000 6200 #define TX_ALL_TX_IBUFF_1T2T_ICBUF1T_ALIGN 0 6201 #define TX_ALL_TX_IBUFF_1T2T_ICBUF1T_BITS 2 6202 #define TX_ALL_TX_IBUFF_1T2T_ICBUF1T_SHIFT 14 6203 6204 /* TX_All :: Tx_ibuff_1T2T :: icbuf2t [13:11] */ 6205 #define TX_ALL_TX_IBUFF_1T2T_ICBUF2T_MASK 0x3800 6206 #define TX_ALL_TX_IBUFF_1T2T_ICBUF2T_ALIGN 0 6207 #define TX_ALL_TX_IBUFF_1T2T_ICBUF2T_BITS 3 6208 #define TX_ALL_TX_IBUFF_1T2T_ICBUF2T_SHIFT 11 6209 6210 /* TX_All :: Tx_ibuff_1T2T :: imin_predrv [10:10] */ 6211 #define TX_ALL_TX_IBUFF_1T2T_IMIN_PREDRV_MASK 0x0400 6212 #define TX_ALL_TX_IBUFF_1T2T_IMIN_PREDRV_ALIGN 0 6213 #define TX_ALL_TX_IBUFF_1T2T_IMIN_PREDRV_BITS 1 6214 #define TX_ALL_TX_IBUFF_1T2T_IMIN_PREDRV_SHIFT 10 6215 6216 /* TX_All :: Tx_ibuff_1T2T :: imax_predrv [09:09] */ 6217 #define TX_ALL_TX_IBUFF_1T2T_IMAX_PREDRV_MASK 0x0200 6218 #define TX_ALL_TX_IBUFF_1T2T_IMAX_PREDRV_ALIGN 0 6219 #define TX_ALL_TX_IBUFF_1T2T_IMAX_PREDRV_BITS 1 6220 #define TX_ALL_TX_IBUFF_1T2T_IMAX_PREDRV_SHIFT 9 6221 6222 /* TX_All :: Tx_ibuff_1T2T :: imode_predrv [08:08] */ 6223 #define TX_ALL_TX_IBUFF_1T2T_IMODE_PREDRV_MASK 0x0100 6224 #define TX_ALL_TX_IBUFF_1T2T_IMODE_PREDRV_ALIGN 0 6225 #define TX_ALL_TX_IBUFF_1T2T_IMODE_PREDRV_BITS 1 6226 #define TX_ALL_TX_IBUFF_1T2T_IMODE_PREDRV_SHIFT 8 6227 6228 /* TX_All :: Tx_ibuff_1T2T :: i21mux [07:05] */ 6229 #define TX_ALL_TX_IBUFF_1T2T_I21MUX_MASK 0x00e0 6230 #define TX_ALL_TX_IBUFF_1T2T_I21MUX_ALIGN 0 6231 #define TX_ALL_TX_IBUFF_1T2T_I21MUX_BITS 3 6232 #define TX_ALL_TX_IBUFF_1T2T_I21MUX_SHIFT 5 6233 6234 /* TX_All :: Tx_ibuff_1T2T :: imin_drvr [04:04] */ 6235 #define TX_ALL_TX_IBUFF_1T2T_IMIN_DRVR_MASK 0x0010 6236 #define TX_ALL_TX_IBUFF_1T2T_IMIN_DRVR_ALIGN 0 6237 #define TX_ALL_TX_IBUFF_1T2T_IMIN_DRVR_BITS 1 6238 #define TX_ALL_TX_IBUFF_1T2T_IMIN_DRVR_SHIFT 4 6239 6240 /* TX_All :: Tx_ibuff_1T2T :: imax_drvr [03:03] */ 6241 #define TX_ALL_TX_IBUFF_1T2T_IMAX_DRVR_MASK 0x0008 6242 #define TX_ALL_TX_IBUFF_1T2T_IMAX_DRVR_ALIGN 0 6243 #define TX_ALL_TX_IBUFF_1T2T_IMAX_DRVR_BITS 1 6244 #define TX_ALL_TX_IBUFF_1T2T_IMAX_DRVR_SHIFT 3 6245 6246 /* TX_All :: Tx_ibuff_1T2T :: imode_drvr [02:02] */ 6247 #define TX_ALL_TX_IBUFF_1T2T_IMODE_DRVR_MASK 0x0004 6248 #define TX_ALL_TX_IBUFF_1T2T_IMODE_DRVR_ALIGN 0 6249 #define TX_ALL_TX_IBUFF_1T2T_IMODE_DRVR_BITS 1 6250 #define TX_ALL_TX_IBUFF_1T2T_IMODE_DRVR_SHIFT 2 6251 6252 /* TX_All :: Tx_ibuff_1T2T :: reserved0 [01:00] */ 6253 #define TX_ALL_TX_IBUFF_1T2T_RESERVED0_MASK 0x0003 6254 #define TX_ALL_TX_IBUFF_1T2T_RESERVED0_ALIGN 0 6255 #define TX_ALL_TX_IBUFF_1T2T_RESERVED0_BITS 2 6256 #define TX_ALL_TX_IBUFF_1T2T_RESERVED0_SHIFT 0 6257 6258 6259 /**************************************************************************** 6260 * TX_All :: Tx_Driver 6261 */ 6262 /* TX_All :: Tx_Driver :: preemphasis_post [15:12] */ 6263 #define TX_ALL_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6264 #define TX_ALL_TX_DRIVER_PREEMPHASIS_ALIGN 0 6265 #define TX_ALL_TX_DRIVER_PREEMPHASIS_BITS 4 6266 #define TX_ALL_TX_DRIVER_PREEMPHASIS_SHIFT 12 6267 6268 /* TX_All :: Tx_Driver :: Idriver [11:08] */ 6269 #define TX_ALL_TX_DRIVER_IDRIVER_MASK 0x0f00 6270 #define TX_ALL_TX_DRIVER_IDRIVER_ALIGN 0 6271 #define TX_ALL_TX_DRIVER_IDRIVER_BITS 4 6272 #define TX_ALL_TX_DRIVER_IDRIVER_SHIFT 8 6273 6274 /* TX_All :: Tx_Driver :: Ipredriver [07:04] */ 6275 #define TX_ALL_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6276 #define TX_ALL_TX_DRIVER_IPREDRIVER_ALIGN 0 6277 #define TX_ALL_TX_DRIVER_IPREDRIVER_BITS 4 6278 #define TX_ALL_TX_DRIVER_IPREDRIVER_SHIFT 4 6279 6280 /* TX_All :: Tx_Driver :: ifull_spd [03:01] */ 6281 #define TX_ALL_TX_DRIVER_IFULLSPD_MASK 0x000e 6282 #define TX_ALL_TX_DRIVER_IFULLSPD_ALIGN 0 6283 #define TX_ALL_TX_DRIVER_IFULLSPD_BITS 3 6284 #define TX_ALL_TX_DRIVER_IFULLSPD_SHIFT 1 6285 6286 /* TX_All :: Tx_Driver :: icbuf1t0 [00:00] */ 6287 #define TX_ALL_TX_DRIVER_ICBUF1T0_MASK 0x0001 6288 #define TX_ALL_TX_DRIVER_ICBUF1T0_ALIGN 0 6289 #define TX_ALL_TX_DRIVER_ICBUF1T0_BITS 1 6290 #define TX_ALL_TX_DRIVER_ICBUF1T0_SHIFT 0 6291 6292 6293 /**************************************************************************** 6294 * XGXS16G_USER_RX0 6295 */ 6296 /**************************************************************************** 6297 * RX0 :: Rx_Status 6298 */ 6299 /* union - case sigdet_Status [15:00] */ 6300 /* RX0 :: Rx_Status :: cx4_sigdet [15:15] */ 6301 #define RX0_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 6302 #define RX0_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 6303 #define RX0_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 6304 #define RX0_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 6305 6306 /* RX0 :: Rx_Status :: reserved0 [14:13] */ 6307 #define RX0_RX_STATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 6308 #define RX0_RX_STATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 6309 #define RX0_RX_STATUS_SIGDET_STATUS_RESERVED0_BITS 2 6310 #define RX0_RX_STATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 6311 6312 /* RX0 :: Rx_Status :: rxSeqDone [12:12] */ 6313 #define RX0_RX_STATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 6314 #define RX0_RX_STATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 6315 #define RX0_RX_STATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 6316 #define RX0_RX_STATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 6317 6318 /* RX0 :: Rx_Status :: rx_sigdet_ll [11:11] */ 6319 #define RX0_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 6320 #define RX0_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 6321 #define RX0_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 6322 #define RX0_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 6323 6324 /* RX0 :: Rx_Status :: cs4_sigdet_ll [10:10] */ 6325 #define RX0_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 6326 #define RX0_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 6327 #define RX0_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 6328 #define RX0_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 6329 6330 /* RX0 :: Rx_Status :: rx_reset [09:09] */ 6331 #define RX0_RX_STATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 6332 #define RX0_RX_STATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 6333 #define RX0_RX_STATUS_SIGDET_STATUS_RX_RESET_BITS 1 6334 #define RX0_RX_STATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 6335 6336 /* RX0 :: Rx_Status :: rx_pwrdn [08:08] */ 6337 #define RX0_RX_STATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 6338 #define RX0_RX_STATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 6339 #define RX0_RX_STATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 6340 #define RX0_RX_STATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 6341 6342 /* RX0 :: Rx_Status :: reserved1 [07:00] */ 6343 #define RX0_RX_STATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 6344 #define RX0_RX_STATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 6345 #define RX0_RX_STATUS_SIGDET_STATUS_RESERVED1_BITS 8 6346 #define RX0_RX_STATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 6347 6348 6349 /* union - case sync_Status [15:00] */ 6350 /* RX0 :: Rx_Status :: reserved0 [15:11] */ 6351 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 6352 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED0_ALIGN 0 6353 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED0_BITS 5 6354 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED0_SHIFT 11 6355 6356 /* RX0 :: Rx_Status :: test_acq_en [10:10] */ 6357 #define RX0_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 6358 #define RX0_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 6359 #define RX0_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 6360 #define RX0_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 6361 6362 /* RX0 :: Rx_Status :: reserved1 [09:09] */ 6363 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 6364 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED1_ALIGN 0 6365 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED1_BITS 1 6366 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED1_SHIFT 9 6367 6368 /* RX0 :: Rx_Status :: rxSeqStart [08:08] */ 6369 #define RX0_RX_STATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 6370 #define RX0_RX_STATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 6371 #define RX0_RX_STATUS_SYNC_STATUS_RXSEQSTART_BITS 1 6372 #define RX0_RX_STATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 6373 6374 /* RX0 :: Rx_Status :: mux_comadj_sync_status [07:07] */ 6375 #define RX0_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 6376 #define RX0_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 6377 #define RX0_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 6378 #define RX0_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 6379 6380 /* RX0 :: Rx_Status :: sync_status [06:06] */ 6381 #define RX0_RX_STATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 6382 #define RX0_RX_STATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 6383 #define RX0_RX_STATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 6384 #define RX0_RX_STATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 6385 6386 /* RX0 :: Rx_Status :: rx_sigdet [05:05] */ 6387 #define RX0_RX_STATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 6388 #define RX0_RX_STATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 6389 #define RX0_RX_STATUS_SYNC_STATUS_RX_SIGDET_BITS 1 6390 #define RX0_RX_STATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 6391 6392 /* RX0 :: Rx_Status :: reserved2 [04:03] */ 6393 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 6394 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED2_ALIGN 0 6395 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED2_BITS 2 6396 #define RX0_RX_STATUS_SYNC_STATUS_RESERVED2_SHIFT 3 6397 6398 /* RX0 :: Rx_Status :: saturate_status [02:02] */ 6399 #define RX0_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 6400 #define RX0_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 6401 #define RX0_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 6402 #define RX0_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 6403 6404 /* RX0 :: Rx_Status :: cx4_sigdet [01:01] */ 6405 #define RX0_RX_STATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 6406 #define RX0_RX_STATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 6407 #define RX0_RX_STATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 6408 #define RX0_RX_STATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 6409 6410 /* RX0 :: Rx_Status :: rxSeqDone [00:00] */ 6411 #define RX0_RX_STATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 6412 #define RX0_RX_STATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 6413 #define RX0_RX_STATUS_SYNC_STATUS_RXSEQDONE_BITS 1 6414 #define RX0_RX_STATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 6415 6416 6417 /* union - case rxTestSel_0 [15:00] */ 6418 /* RX0 :: Rx_Status :: reserved0 [15:10] */ 6419 #define RX0_RX_STATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 6420 #define RX0_RX_STATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 6421 #define RX0_RX_STATUS_RXTESTSEL_0_RESERVED0_BITS 6 6422 #define RX0_RX_STATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 6423 6424 /* RX0 :: Rx_Status :: indck_mode_en [09:09] */ 6425 #define RX0_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 6426 #define RX0_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 6427 #define RX0_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 6428 #define RX0_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 6429 6430 /* RX0 :: Rx_Status :: pci_mode_en [08:08] */ 6431 #define RX0_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 6432 #define RX0_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 6433 #define RX0_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 6434 #define RX0_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 6435 6436 /* RX0 :: Rx_Status :: rx_polarity [07:07] */ 6437 #define RX0_RX_STATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 6438 #define RX0_RX_STATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 6439 #define RX0_RX_STATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 6440 #define RX0_RX_STATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 6441 6442 /* RX0 :: Rx_Status :: rxpol_flip [06:06] */ 6443 #define RX0_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 6444 #define RX0_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 6445 #define RX0_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 6446 #define RX0_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 6447 6448 /* RX0 :: Rx_Status :: comma_mask [05:05] */ 6449 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 6450 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 6451 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 6452 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 6453 6454 /* RX0 :: Rx_Status :: link_en_r [04:04] */ 6455 #define RX0_RX_STATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 6456 #define RX0_RX_STATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 6457 #define RX0_RX_STATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 6458 #define RX0_RX_STATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 6459 6460 /* RX0 :: Rx_Status :: comma_adj_en [03:03] */ 6461 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 6462 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 6463 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 6464 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 6465 6466 /* RX0 :: Rx_Status :: comma_adj_en_ext [02:02] */ 6467 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 6468 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 6469 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 6470 #define RX0_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 6471 6472 /* RX0 :: Rx_Status :: reserved1 [01:00] */ 6473 #define RX0_RX_STATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 6474 #define RX0_RX_STATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 6475 #define RX0_RX_STATUS_RXTESTSEL_0_RESERVED1_BITS 2 6476 #define RX0_RX_STATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 6477 6478 6479 /* union - case rxTestSel_1 [15:00] */ 6480 /* RX0 :: Rx_Status :: reserved0 [15:05] */ 6481 #define RX0_RX_STATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 6482 #define RX0_RX_STATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 6483 #define RX0_RX_STATUS_RXTESTSEL_1_RESERVED0_BITS 11 6484 #define RX0_RX_STATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 6485 6486 /* RX0 :: Rx_Status :: cdrAcqDone_r2 [04:04] */ 6487 #define RX0_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 6488 #define RX0_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 6489 #define RX0_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 6490 #define RX0_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 6491 6492 /* RX0 :: Rx_Status :: freq_sel_PC [03:03] */ 6493 #define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 6494 #define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 6495 #define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 6496 #define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 6497 6498 /* RX0 :: Rx_Status :: freq_sel_SM [02:02] */ 6499 #define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 6500 #define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 6501 #define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 6502 #define RX0_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 6503 6504 /* RX0 :: Rx_Status :: integ_mode_SM [01:00] */ 6505 #define RX0_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 6506 #define RX0_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 6507 #define RX0_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 6508 #define RX0_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 6509 6510 6511 /* union - case scale_Status [15:00] */ 6512 /* RX0 :: Rx_Status :: prop_scale [15:12] */ 6513 #define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 6514 #define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 6515 #define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_BITS 4 6516 #define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 6517 6518 /* RX0 :: Rx_Status :: integ_scale [11:08] */ 6519 #define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 6520 #define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 6521 #define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 6522 #define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 6523 6524 /* RX0 :: Rx_Status :: prop_scale_acq [07:04] */ 6525 #define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 6526 #define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 6527 #define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 6528 #define RX0_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 6529 6530 /* RX0 :: Rx_Status :: integ_scale_acq [03:00] */ 6531 #define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 6532 #define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 6533 #define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 6534 #define RX0_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 6535 6536 6537 /* union - case adc_CdrStatus1 [15:00] */ 6538 /* RX0 :: Rx_Status :: reserved0 [15:07] */ 6539 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 6540 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 6541 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 6542 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 6543 6544 /* RX0 :: Rx_Status :: rxMuxCkSel [06:06] */ 6545 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 6546 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 6547 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 6548 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 6549 6550 /* RX0 :: Rx_Status :: glpbk_combo [05:05] */ 6551 #define RX0_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 6552 #define RX0_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 6553 #define RX0_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 6554 #define RX0_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 6555 6556 /* RX0 :: Rx_Status :: clockSwitchSel [04:04] */ 6557 #define RX0_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 6558 #define RX0_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 6559 #define RX0_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 6560 #define RX0_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 6561 6562 /* RX0 :: Rx_Status :: rxck_tst [03:03] */ 6563 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 6564 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 6565 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 6566 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 6567 6568 /* RX0 :: Rx_Status :: rxck_i [02:02] */ 6569 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 6570 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 6571 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 6572 #define RX0_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 6573 6574 /* RX0 :: Rx_Status :: refclk [01:01] */ 6575 #define RX0_RX_STATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 6576 #define RX0_RX_STATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 6577 #define RX0_RX_STATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 6578 #define RX0_RX_STATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 6579 6580 /* RX0 :: Rx_Status :: pll_bypass [00:00] */ 6581 #define RX0_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 6582 #define RX0_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 6583 #define RX0_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 6584 #define RX0_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 6585 6586 6587 /* union - case adc_CdrStatus2 [15:00] */ 6588 /* RX0 :: Rx_Status :: reserved0 [15:06] */ 6589 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 6590 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 6591 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 6592 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 6593 6594 /* RX0 :: Rx_Status :: rxMuxCkSel [05:05] */ 6595 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 6596 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 6597 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 6598 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 6599 6600 /* RX0 :: Rx_Status :: rxSeqStart [04:04] */ 6601 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 6602 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 6603 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 6604 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 6605 6606 /* RX0 :: Rx_Status :: reserved1 [03:01] */ 6607 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 6608 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 6609 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 6610 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 6611 6612 /* RX0 :: Rx_Status :: rxSeqDone [00:00] */ 6613 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 6614 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 6615 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 6616 #define RX0_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 6617 6618 6619 /* union - case adc_CdrStatus3 [15:00] */ 6620 /* RX0 :: Rx_Status :: reserved0 [15:04] */ 6621 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 6622 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 6623 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 6624 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 6625 6626 /* RX0 :: Rx_Status :: rxSeqStart [03:03] */ 6627 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 6628 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 6629 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 6630 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 6631 6632 /* RX0 :: Rx_Status :: reserved1 [02:01] */ 6633 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 6634 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 6635 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 6636 #define RX0_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 6637 6638 /* RX0 :: Rx_Status :: allow_increment_PC [00:00] */ 6639 #define RX0_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 6640 #define RX0_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 6641 #define RX0_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 6642 #define RX0_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 6643 6644 6645 /* union - case adc_CdrStatus4 [15:00] */ 6646 /* RX0 :: Rx_Status :: reserved0 [15:08] */ 6647 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 6648 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 6649 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 6650 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 6651 6652 /* RX0 :: Rx_Status :: rx_pwrdn [07:07] */ 6653 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 6654 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 6655 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 6656 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 6657 6658 /* RX0 :: Rx_Status :: freq_sel [06:06] */ 6659 #define RX0_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 6660 #define RX0_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 6661 #define RX0_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 6662 #define RX0_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 6663 6664 /* RX0 :: Rx_Status :: pll_lock_rstb [05:05] */ 6665 #define RX0_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 6666 #define RX0_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 6667 #define RX0_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 6668 #define RX0_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 6669 6670 /* RX0 :: Rx_Status :: pwrdn [04:04] */ 6671 #define RX0_RX_STATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 6672 #define RX0_RX_STATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 6673 #define RX0_RX_STATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 6674 #define RX0_RX_STATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 6675 6676 /* RX0 :: Rx_Status :: reserved1 [03:00] */ 6677 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 6678 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 6679 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 6680 #define RX0_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 6681 6682 6683 /* union - case adc_CdrStatus5 [15:00] */ 6684 /* RX0 :: Rx_Status :: reserved0 [15:00] */ 6685 #define RX0_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 6686 #define RX0_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 6687 #define RX0_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 6688 #define RX0_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 6689 6690 6691 /* union - case adc_CdrStatus6 [15:00] */ 6692 /* RX0 :: Rx_Status :: reserved0 [15:05] */ 6693 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 6694 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 6695 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 6696 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 6697 6698 /* RX0 :: Rx_Status :: rx_reset [04:04] */ 6699 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 6700 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 6701 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 6702 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 6703 6704 /* RX0 :: Rx_Status :: rx_pwrdn [03:03] */ 6705 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 6706 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 6707 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 6708 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 6709 6710 /* RX0 :: Rx_Status :: reset_anlg [02:02] */ 6711 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 6712 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 6713 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 6714 #define RX0_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 6715 6716 /* RX0 :: Rx_Status :: pwrdn_rx [01:01] */ 6717 #define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 6718 #define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 6719 #define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 6720 #define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 6721 6722 /* RX0 :: Rx_Status :: pwrdn_pll [00:00] */ 6723 #define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 6724 #define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 6725 #define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 6726 #define RX0_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 6727 6728 6729 /* union - case adc_CdrStatus7e [15:00] */ 6730 /* RX0 :: Rx_Status :: reserved0 [15:05] */ 6731 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 6732 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 6733 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 6734 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 6735 6736 /* RX0 :: Rx_Status :: rxck0_even [04:04] */ 6737 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 6738 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 6739 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 6740 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 6741 6742 /* RX0 :: Rx_Status :: rxck1_even [03:03] */ 6743 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 6744 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 6745 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 6746 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 6747 6748 /* RX0 :: Rx_Status :: comdet_even [02:02] */ 6749 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 6750 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 6751 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 6752 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 6753 6754 /* RX0 :: Rx_Status :: en_cdet_even [01:01] */ 6755 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 6756 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 6757 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 6758 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 6759 6760 /* RX0 :: Rx_Status :: comma_adj_en_even [00:00] */ 6761 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 6762 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 6763 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 6764 #define RX0_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 6765 6766 6767 /* union - case adc_CdrStatus7o [15:00] */ 6768 /* RX0 :: Rx_Status :: reserved0 [15:05] */ 6769 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 6770 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 6771 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 6772 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 6773 6774 /* RX0 :: Rx_Status :: rxck0_odd [04:04] */ 6775 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 6776 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 6777 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 6778 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 6779 6780 /* RX0 :: Rx_Status :: rxck1_odd [03:03] */ 6781 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 6782 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 6783 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 6784 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 6785 6786 /* RX0 :: Rx_Status :: comdet_odd [02:02] */ 6787 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 6788 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 6789 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 6790 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 6791 6792 /* RX0 :: Rx_Status :: en_cdet_odd [01:01] */ 6793 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 6794 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 6795 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 6796 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 6797 6798 /* RX0 :: Rx_Status :: comma_adj_en_odd [00:00] */ 6799 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 6800 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 6801 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 6802 #define RX0_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 6803 6804 6805 /* union - case adc_CdrStatus8 [15:00] */ 6806 /* RX0 :: Rx_Status :: reserved0 [15:01] */ 6807 #define RX0_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 6808 #define RX0_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 6809 #define RX0_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 6810 #define RX0_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 6811 6812 /* RX0 :: Rx_Status :: sigdet [00:00] */ 6813 #define RX0_RX_STATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 6814 #define RX0_RX_STATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 6815 #define RX0_RX_STATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 6816 #define RX0_RX_STATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 6817 6818 6819 /* union - case adc_CdrStatus9 [15:00] */ 6820 /* RX0 :: Rx_Status :: reserved0 [15:00] */ 6821 #define RX0_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 6822 #define RX0_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 6823 #define RX0_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 6824 #define RX0_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 6825 6826 6827 /* union - case adc_CdrStatus10 [15:00] */ 6828 /* RX0 :: Rx_Status :: reserved0 [15:07] */ 6829 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 6830 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 6831 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 6832 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 6833 6834 /* RX0 :: Rx_Status :: prbs_en [06:06] */ 6835 #define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 6836 #define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 6837 #define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 6838 #define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 6839 6840 /* RX0 :: Rx_Status :: rstb_tst [05:05] */ 6841 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 6842 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 6843 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 6844 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 6845 6846 /* RX0 :: Rx_Status :: reserved1 [04:04] */ 6847 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 6848 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 6849 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 6850 #define RX0_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 6851 6852 /* RX0 :: Rx_Status :: prbs_state [03:00] */ 6853 #define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 6854 #define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 6855 #define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 6856 #define RX0_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 6857 6858 6859 /* union - case adc_CdrStatus11 [15:00] */ 6860 /* RX0 :: Rx_Status :: reserved0 [15:00] */ 6861 #define RX0_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 6862 #define RX0_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 6863 #define RX0_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 6864 #define RX0_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 6865 6866 6867 /* union - case adc_CdrStatus12_1 [15:00] */ 6868 /* RX0 :: Rx_Status :: reserved0 [15:06] */ 6869 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 6870 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 6871 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 6872 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 6873 6874 /* RX0 :: Rx_Status :: enable4 [05:05] */ 6875 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 6876 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 6877 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 6878 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 6879 6880 /* RX0 :: Rx_Status :: radr_test [04:00] */ 6881 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 6882 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 6883 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 6884 #define RX0_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 6885 6886 6887 /* union - case adc_CdrStatus12_2 [15:00] */ 6888 /* RX0 :: Rx_Status :: reserved0 [15:05] */ 6889 #define RX0_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 6890 #define RX0_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 6891 #define RX0_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 6892 #define RX0_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 6893 6894 /* RX0 :: Rx_Status :: wadr_test [04:00] */ 6895 #define RX0_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 6896 #define RX0_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 6897 #define RX0_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 6898 #define RX0_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 6899 6900 6901 /* union - case adc_CdrStatus12_3 [15:00] */ 6902 /* RX0 :: Rx_Status :: reserved0 [15:06] */ 6903 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 6904 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 6905 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 6906 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 6907 6908 /* RX0 :: Rx_Status :: rxck_66B_tmux [05:05] */ 6909 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 6910 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 6911 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 6912 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 6913 6914 /* RX0 :: Rx_Status :: rstb_66B [04:04] */ 6915 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 6916 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 6917 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 6918 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 6919 6920 /* RX0 :: Rx_Status :: prstb_66B_mux [03:03] */ 6921 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 6922 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 6923 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 6924 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 6925 6926 /* RX0 :: Rx_Status :: rxck_i66_tmux [02:02] */ 6927 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 6928 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 6929 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 6930 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 6931 6932 /* RX0 :: Rx_Status :: rstb_i66 [01:01] */ 6933 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 6934 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 6935 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 6936 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 6937 6938 /* RX0 :: Rx_Status :: prstb_i66_mux [00:00] */ 6939 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 6940 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 6941 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 6942 #define RX0_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 6943 6944 6945 /* union - case adc_CdrStatus12_4 [15:00] */ 6946 /* RX0 :: Rx_Status :: reserved0 [15:04] */ 6947 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 6948 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 6949 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 6950 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 6951 6952 /* RX0 :: Rx_Status :: rfifo_error_r [03:02] */ 6953 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 6954 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 6955 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 6956 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 6957 6958 /* RX0 :: Rx_Status :: rfifo_unflow [01:01] */ 6959 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 6960 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 6961 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 6962 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 6963 6964 /* RX0 :: Rx_Status :: rfifo_ovflow [00:00] */ 6965 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 6966 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 6967 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 6968 #define RX0_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 6969 6970 6971 /* union - case integ_Status [15:00] */ 6972 /* RX0 :: Rx_Status :: integ_status [15:00] */ 6973 #define RX0_RX_STATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 6974 #define RX0_RX_STATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 6975 #define RX0_RX_STATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 6976 #define RX0_RX_STATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 6977 6978 6979 /* union - case vco_Status [15:00] */ 6980 /* RX0 :: Rx_Status :: vco_status [15:00] */ 6981 #define RX0_RX_STATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 6982 #define RX0_RX_STATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 6983 #define RX0_RX_STATUS_VCO_STATUS_VCO_STATUS_BITS 16 6984 #define RX0_RX_STATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 6985 6986 6987 /* union - case prbs_Status [15:00] */ 6988 /* RX0 :: Rx_Status :: prbs_lock [15:15] */ 6989 #define RX0_RX_STATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 6990 #define RX0_RX_STATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 6991 #define RX0_RX_STATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 6992 #define RX0_RX_STATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 6993 6994 /* RX0 :: Rx_Status :: prbs_stky [14:14] */ 6995 #define RX0_RX_STATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 6996 #define RX0_RX_STATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 6997 #define RX0_RX_STATUS_PRBS_STATUS_PRBS_STKY_BITS 1 6998 #define RX0_RX_STATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 6999 7000 /* RX0 :: Rx_Status :: ptbs_errors [13:00] */ 7001 #define RX0_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_MASK 0x3fff 7002 #define RX0_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN 0 7003 #define RX0_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_BITS 14 7004 #define RX0_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT 0 7005 7006 7007 7008 /**************************************************************************** 7009 * RX0 :: Rx_Control 7010 */ 7011 /* RX0 :: Rx_Control :: reserved0 [15:03] */ 7012 #define RX0_RX_CONTROL_RESERVED0_MASK 0xfff8 7013 #define RX0_RX_CONTROL_RESERVED0_ALIGN 0 7014 #define RX0_RX_CONTROL_RESERVED0_BITS 13 7015 #define RX0_RX_CONTROL_RESERVED0_SHIFT 3 7016 7017 /* RX0 :: Rx_Control :: status_sel [02:00] */ 7018 #define RX0_RX_CONTROL_STATUS_SEL_MASK 0x0007 7019 #define RX0_RX_CONTROL_STATUS_SEL_ALIGN 0 7020 #define RX0_RX_CONTROL_STATUS_SEL_BITS 3 7021 #define RX0_RX_CONTROL_STATUS_SEL_SHIFT 0 7022 #define RX0_RX_CONTROL_STATUS_SEL_sigdetStatus 0 7023 #define RX0_RX_CONTROL_STATUS_SEL_syncStatus 1 7024 #define RX0_RX_CONTROL_STATUS_SEL_rxTestSel 2 7025 #define RX0_RX_CONTROL_STATUS_SEL_scaleStatus 3 7026 #define RX0_RX_CONTROL_STATUS_SEL_adcCdrStatus 4 7027 #define RX0_RX_CONTROL_STATUS_SEL_integStatus 5 7028 #define RX0_RX_CONTROL_STATUS_SEL_vcoStatus 6 7029 #define RX0_RX_CONTROL_STATUS_SEL_prbsStatus 7 7030 7031 7032 /**************************************************************************** 7033 * RX0 :: Rx_Test 7034 */ 7035 /* RX0 :: Rx_Test :: sigdet_mux_SM [15:12] */ 7036 #define RX0_RX_TEST_SIGDET_MUX_SM_MASK 0xf000 7037 #define RX0_RX_TEST_SIGDET_MUX_SM_ALIGN 0 7038 #define RX0_RX_TEST_SIGDET_MUX_SM_BITS 4 7039 #define RX0_RX_TEST_SIGDET_MUX_SM_SHIFT 12 7040 7041 /* RX0 :: Rx_Test :: reserved0 [11:09] */ 7042 #define RX0_RX_TEST_RESERVED0_MASK 0x0e00 7043 #define RX0_RX_TEST_RESERVED0_ALIGN 0 7044 #define RX0_RX_TEST_RESERVED0_BITS 3 7045 #define RX0_RX_TEST_RESERVED0_SHIFT 9 7046 7047 /* RX0 :: Rx_Test :: tpctrl_SM [08:04] */ 7048 #define RX0_RX_TEST_TPCTRL_SM_MASK 0x01f0 7049 #define RX0_RX_TEST_TPCTRL_SM_ALIGN 0 7050 #define RX0_RX_TEST_TPCTRL_SM_BITS 5 7051 #define RX0_RX_TEST_TPCTRL_SM_SHIFT 4 7052 7053 /* RX0 :: Rx_Test :: testMuxSelect_SM [03:00] */ 7054 #define RX0_RX_TEST_TESTMUXSELECT_SM_MASK 0x000f 7055 #define RX0_RX_TEST_TESTMUXSELECT_SM_ALIGN 0 7056 #define RX0_RX_TEST_TESTMUXSELECT_SM_BITS 4 7057 #define RX0_RX_TEST_TESTMUXSELECT_SM_SHIFT 0 7058 7059 7060 /**************************************************************************** 7061 * RX0 :: Rx_Control_1G_type 7062 */ 7063 /* RX0 :: Rx_Control_1G_type :: fpat_md [15:15] */ 7064 #define RX0_RX_CONTROL_1G_TYPE_FPAT_MD_MASK 0x8000 7065 #define RX0_RX_CONTROL_1G_TYPE_FPAT_MD_ALIGN 0 7066 #define RX0_RX_CONTROL_1G_TYPE_FPAT_MD_BITS 1 7067 #define RX0_RX_CONTROL_1G_TYPE_FPAT_MD_SHIFT 15 7068 7069 /* RX0 :: Rx_Control_1G_type :: pkt_count_en [14:14] */ 7070 #define RX0_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_MASK 0x4000 7071 #define RX0_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_ALIGN 0 7072 #define RX0_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_BITS 1 7073 #define RX0_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_SHIFT 14 7074 7075 /* RX0 :: Rx_Control_1G_type :: staMuxRegDis [13:13] */ 7076 #define RX0_RX_CONTROL_1G_TYPE_STAMUXREGDIS_MASK 0x2000 7077 #define RX0_RX_CONTROL_1G_TYPE_STAMUXREGDIS_ALIGN 0 7078 #define RX0_RX_CONTROL_1G_TYPE_STAMUXREGDIS_BITS 1 7079 #define RX0_RX_CONTROL_1G_TYPE_STAMUXREGDIS_SHIFT 13 7080 7081 /* RX0 :: Rx_Control_1G_type :: prbs_clr_dis [12:12] */ 7082 #define RX0_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_MASK 0x1000 7083 #define RX0_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_ALIGN 0 7084 #define RX0_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_BITS 1 7085 #define RX0_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_SHIFT 12 7086 7087 /* RX0 :: Rx_Control_1G_type :: rxd_dec_sel [11:11] */ 7088 #define RX0_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_MASK 0x0800 7089 #define RX0_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_ALIGN 0 7090 #define RX0_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_BITS 1 7091 #define RX0_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_SHIFT 11 7092 7093 /* RX0 :: Rx_Control_1G_type :: cgbad_tst [10:10] */ 7094 #define RX0_RX_CONTROL_1G_TYPE_CGBAD_TST_MASK 0x0400 7095 #define RX0_RX_CONTROL_1G_TYPE_CGBAD_TST_ALIGN 0 7096 #define RX0_RX_CONTROL_1G_TYPE_CGBAD_TST_BITS 1 7097 #define RX0_RX_CONTROL_1G_TYPE_CGBAD_TST_SHIFT 10 7098 7099 /* RX0 :: Rx_Control_1G_type :: Emon_en [09:09] */ 7100 #define RX0_RX_CONTROL_1G_TYPE_EMON_EN_MASK 0x0200 7101 #define RX0_RX_CONTROL_1G_TYPE_EMON_EN_ALIGN 0 7102 #define RX0_RX_CONTROL_1G_TYPE_EMON_EN_BITS 1 7103 #define RX0_RX_CONTROL_1G_TYPE_EMON_EN_SHIFT 9 7104 7105 /* RX0 :: Rx_Control_1G_type :: prbs_en [08:08] */ 7106 #define RX0_RX_CONTROL_1G_TYPE_PRBS_EN_MASK 0x0100 7107 #define RX0_RX_CONTROL_1G_TYPE_PRBS_EN_ALIGN 0 7108 #define RX0_RX_CONTROL_1G_TYPE_PRBS_EN_BITS 1 7109 #define RX0_RX_CONTROL_1G_TYPE_PRBS_EN_SHIFT 8 7110 7111 /* RX0 :: Rx_Control_1G_type :: cgbad_en [07:07] */ 7112 #define RX0_RX_CONTROL_1G_TYPE_CGBAD_EN_MASK 0x0080 7113 #define RX0_RX_CONTROL_1G_TYPE_CGBAD_EN_ALIGN 0 7114 #define RX0_RX_CONTROL_1G_TYPE_CGBAD_EN_BITS 1 7115 #define RX0_RX_CONTROL_1G_TYPE_CGBAD_EN_SHIFT 7 7116 7117 /* RX0 :: Rx_Control_1G_type :: cstretch [06:06] */ 7118 #define RX0_RX_CONTROL_1G_TYPE_CSTRETCH_MASK 0x0040 7119 #define RX0_RX_CONTROL_1G_TYPE_CSTRETCH_ALIGN 0 7120 #define RX0_RX_CONTROL_1G_TYPE_CSTRETCH_BITS 1 7121 #define RX0_RX_CONTROL_1G_TYPE_CSTRETCH_SHIFT 6 7122 7123 /* RX0 :: Rx_Control_1G_type :: rtbi_ckflip [05:05] */ 7124 #define RX0_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_MASK 0x0020 7125 #define RX0_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_ALIGN 0 7126 #define RX0_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_BITS 1 7127 #define RX0_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_SHIFT 5 7128 7129 /* RX0 :: Rx_Control_1G_type :: rtbi_flip [04:04] */ 7130 #define RX0_RX_CONTROL_1G_TYPE_RTBI_FLIP_MASK 0x0010 7131 #define RX0_RX_CONTROL_1G_TYPE_RTBI_FLIP_ALIGN 0 7132 #define RX0_RX_CONTROL_1G_TYPE_RTBI_FLIP_BITS 1 7133 #define RX0_RX_CONTROL_1G_TYPE_RTBI_FLIP_SHIFT 4 7134 7135 /* RX0 :: Rx_Control_1G_type :: phase_sel [03:03] */ 7136 #define RX0_RX_CONTROL_1G_TYPE_PHASE_SEL_MASK 0x0008 7137 #define RX0_RX_CONTROL_1G_TYPE_PHASE_SEL_ALIGN 0 7138 #define RX0_RX_CONTROL_1G_TYPE_PHASE_SEL_BITS 1 7139 #define RX0_RX_CONTROL_1G_TYPE_PHASE_SEL_SHIFT 3 7140 7141 /* RX0 :: Rx_Control_1G_type :: reserved0 [02:02] */ 7142 #define RX0_RX_CONTROL_1G_TYPE_RESERVED0_MASK 0x0004 7143 #define RX0_RX_CONTROL_1G_TYPE_RESERVED0_ALIGN 0 7144 #define RX0_RX_CONTROL_1G_TYPE_RESERVED0_BITS 1 7145 #define RX0_RX_CONTROL_1G_TYPE_RESERVED0_SHIFT 2 7146 7147 /* RX0 :: Rx_Control_1G_type :: freq_sel_force [01:01] */ 7148 #define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_MASK 0x0002 7149 #define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_ALIGN 0 7150 #define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_BITS 1 7151 #define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_SHIFT 1 7152 7153 /* RX0 :: Rx_Control_1G_type :: freq_sel [00:00] */ 7154 #define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_MASK 0x0001 7155 #define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_ALIGN 0 7156 #define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_BITS 1 7157 #define RX0_RX_CONTROL_1G_TYPE_FREQ_SEL_SHIFT 0 7158 7159 7160 /**************************************************************************** 7161 * RX0 :: Rx_Astatus 7162 */ 7163 /* RX0 :: Rx_Astatus :: reserved0 [15:01] */ 7164 #define RX0_RX_ASTATUS_RESERVED0_MASK 0xfffe 7165 #define RX0_RX_ASTATUS_RESERVED0_ALIGN 0 7166 #define RX0_RX_ASTATUS_RESERVED0_BITS 15 7167 #define RX0_RX_ASTATUS_RESERVED0_SHIFT 1 7168 7169 /* RX0 :: Rx_Astatus :: sigdet [00:00] */ 7170 #define RX0_RX_ASTATUS_SIGDET_MASK 0x0001 7171 #define RX0_RX_ASTATUS_SIGDET_ALIGN 0 7172 #define RX0_RX_ASTATUS_SIGDET_BITS 1 7173 #define RX0_RX_ASTATUS_SIGDET_SHIFT 0 7174 7175 7176 /**************************************************************************** 7177 * RX0 :: Rx_analogBias0 7178 */ 7179 /* RX0 :: Rx_analogBias0 :: imode_vcm [15:15] */ 7180 #define RX0_RX_ANALOGBIAS0_IMODE_VCM_MASK 0x8000 7181 #define RX0_RX_ANALOGBIAS0_IMODE_VCM_ALIGN 0 7182 #define RX0_RX_ANALOGBIAS0_IMODE_VCM_BITS 1 7183 #define RX0_RX_ANALOGBIAS0_IMODE_VCM_SHIFT 15 7184 7185 /* RX0 :: Rx_analogBias0 :: imin_vcm [14:14] */ 7186 #define RX0_RX_ANALOGBIAS0_IMIN_VCM_MASK 0x4000 7187 #define RX0_RX_ANALOGBIAS0_IMIN_VCM_ALIGN 0 7188 #define RX0_RX_ANALOGBIAS0_IMIN_VCM_BITS 1 7189 #define RX0_RX_ANALOGBIAS0_IMIN_VCM_SHIFT 14 7190 7191 /* RX0 :: Rx_analogBias0 :: imax_sigdet [13:13] */ 7192 #define RX0_RX_ANALOGBIAS0_IMAX_SIGDET_MASK 0x2000 7193 #define RX0_RX_ANALOGBIAS0_IMAX_SIGDET_ALIGN 0 7194 #define RX0_RX_ANALOGBIAS0_IMAX_SIGDET_BITS 1 7195 #define RX0_RX_ANALOGBIAS0_IMAX_SIGDET_SHIFT 13 7196 7197 /* RX0 :: Rx_analogBias0 :: imode_sigdet [12:12] */ 7198 #define RX0_RX_ANALOGBIAS0_IMODE_SIGDET_MASK 0x1000 7199 #define RX0_RX_ANALOGBIAS0_IMODE_SIGDET_ALIGN 0 7200 #define RX0_RX_ANALOGBIAS0_IMODE_SIGDET_BITS 1 7201 #define RX0_RX_ANALOGBIAS0_IMODE_SIGDET_SHIFT 12 7202 7203 /* RX0 :: Rx_analogBias0 :: imin_sigdet [11:11] */ 7204 #define RX0_RX_ANALOGBIAS0_IMIN_SIGDET_MASK 0x0800 7205 #define RX0_RX_ANALOGBIAS0_IMIN_SIGDET_ALIGN 0 7206 #define RX0_RX_ANALOGBIAS0_IMIN_SIGDET_BITS 1 7207 #define RX0_RX_ANALOGBIAS0_IMIN_SIGDET_SHIFT 11 7208 7209 /* RX0 :: Rx_analogBias0 :: refh_rx [10:10] */ 7210 #define RX0_RX_ANALOGBIAS0_REFH_RX_MASK 0x0400 7211 #define RX0_RX_ANALOGBIAS0_REFH_RX_ALIGN 0 7212 #define RX0_RX_ANALOGBIAS0_REFH_RX_BITS 1 7213 #define RX0_RX_ANALOGBIAS0_REFH_RX_SHIFT 10 7214 7215 /* RX0 :: Rx_analogBias0 :: refl_rx [09:09] */ 7216 #define RX0_RX_ANALOGBIAS0_REFL_RX_MASK 0x0200 7217 #define RX0_RX_ANALOGBIAS0_REFL_RX_ALIGN 0 7218 #define RX0_RX_ANALOGBIAS0_REFL_RX_BITS 1 7219 #define RX0_RX_ANALOGBIAS0_REFL_RX_SHIFT 9 7220 7221 /* RX0 :: Rx_analogBias0 :: tport_en [08:08] */ 7222 #define RX0_RX_ANALOGBIAS0_TPORT_EN_MASK 0x0100 7223 #define RX0_RX_ANALOGBIAS0_TPORT_EN_ALIGN 0 7224 #define RX0_RX_ANALOGBIAS0_TPORT_EN_BITS 1 7225 #define RX0_RX_ANALOGBIAS0_TPORT_EN_SHIFT 8 7226 7227 /* RX0 :: Rx_analogBias0 :: vddr_bg [07:07] */ 7228 #define RX0_RX_ANALOGBIAS0_VDDR_BG_MASK 0x0080 7229 #define RX0_RX_ANALOGBIAS0_VDDR_BG_ALIGN 0 7230 #define RX0_RX_ANALOGBIAS0_VDDR_BG_BITS 1 7231 #define RX0_RX_ANALOGBIAS0_VDDR_BG_SHIFT 7 7232 7233 /* RX0 :: Rx_analogBias0 :: sig_pwrdn [06:06] */ 7234 #define RX0_RX_ANALOGBIAS0_SIG_PWRDN_MASK 0x0040 7235 #define RX0_RX_ANALOGBIAS0_SIG_PWRDN_ALIGN 0 7236 #define RX0_RX_ANALOGBIAS0_SIG_PWRDN_BITS 1 7237 #define RX0_RX_ANALOGBIAS0_SIG_PWRDN_SHIFT 6 7238 7239 /* RX0 :: Rx_analogBias0 :: offset_ctrl [05:03] */ 7240 #define RX0_RX_ANALOGBIAS0_OFFSET_CTRL_MASK 0x0038 7241 #define RX0_RX_ANALOGBIAS0_OFFSET_CTRL_ALIGN 0 7242 #define RX0_RX_ANALOGBIAS0_OFFSET_CTRL_BITS 3 7243 #define RX0_RX_ANALOGBIAS0_OFFSET_CTRL_SHIFT 3 7244 7245 /* RX0 :: Rx_analogBias0 :: offset_sel [02:02] */ 7246 #define RX0_RX_ANALOGBIAS0_OFFSET_SEL_MASK 0x0004 7247 #define RX0_RX_ANALOGBIAS0_OFFSET_SEL_ALIGN 0 7248 #define RX0_RX_ANALOGBIAS0_OFFSET_SEL_BITS 1 7249 #define RX0_RX_ANALOGBIAS0_OFFSET_SEL_SHIFT 2 7250 7251 /* RX0 :: Rx_analogBias0 :: reserved0 [01:00] */ 7252 #define RX0_RX_ANALOGBIAS0_RESERVED0_MASK 0x0003 7253 #define RX0_RX_ANALOGBIAS0_RESERVED0_ALIGN 0 7254 #define RX0_RX_ANALOGBIAS0_RESERVED0_BITS 2 7255 #define RX0_RX_ANALOGBIAS0_RESERVED0_SHIFT 0 7256 7257 7258 /**************************************************************************** 7259 * RX0 :: Rx_analogBias1 7260 */ 7261 /* RX0 :: Rx_analogBias1 :: imax_clkbuf [15:15] */ 7262 #define RX0_RX_ANALOGBIAS1_IMAX_CLKBUF_MASK 0x8000 7263 #define RX0_RX_ANALOGBIAS1_IMAX_CLKBUF_ALIGN 0 7264 #define RX0_RX_ANALOGBIAS1_IMAX_CLKBUF_BITS 1 7265 #define RX0_RX_ANALOGBIAS1_IMAX_CLKBUF_SHIFT 15 7266 7267 /* RX0 :: Rx_analogBias1 :: imode_clkbuf [14:14] */ 7268 #define RX0_RX_ANALOGBIAS1_IMODE_CLKBUF_MASK 0x4000 7269 #define RX0_RX_ANALOGBIAS1_IMODE_CLKBUF_ALIGN 0 7270 #define RX0_RX_ANALOGBIAS1_IMODE_CLKBUF_BITS 1 7271 #define RX0_RX_ANALOGBIAS1_IMODE_CLKBUF_SHIFT 14 7272 7273 /* RX0 :: Rx_analogBias1 :: imin_clkbuf [13:13] */ 7274 #define RX0_RX_ANALOGBIAS1_IMIN_CLKBUF_MASK 0x2000 7275 #define RX0_RX_ANALOGBIAS1_IMIN_CLKBUF_ALIGN 0 7276 #define RX0_RX_ANALOGBIAS1_IMIN_CLKBUF_BITS 1 7277 #define RX0_RX_ANALOGBIAS1_IMIN_CLKBUF_SHIFT 13 7278 7279 /* RX0 :: Rx_analogBias1 :: imax_eqfl [12:12] */ 7280 #define RX0_RX_ANALOGBIAS1_IMAX_EQFL_MASK 0x1000 7281 #define RX0_RX_ANALOGBIAS1_IMAX_EQFL_ALIGN 0 7282 #define RX0_RX_ANALOGBIAS1_IMAX_EQFL_BITS 1 7283 #define RX0_RX_ANALOGBIAS1_IMAX_EQFL_SHIFT 12 7284 7285 /* RX0 :: Rx_analogBias1 :: imode_eqfl [11:11] */ 7286 #define RX0_RX_ANALOGBIAS1_IMODE_EQFL_MASK 0x0800 7287 #define RX0_RX_ANALOGBIAS1_IMODE_EQFL_ALIGN 0 7288 #define RX0_RX_ANALOGBIAS1_IMODE_EQFL_BITS 1 7289 #define RX0_RX_ANALOGBIAS1_IMODE_EQFL_SHIFT 11 7290 7291 /* RX0 :: Rx_analogBias1 :: imin_eqfl [10:10] */ 7292 #define RX0_RX_ANALOGBIAS1_IMIN_EQFL_MASK 0x0400 7293 #define RX0_RX_ANALOGBIAS1_IMIN_EQFL_ALIGN 0 7294 #define RX0_RX_ANALOGBIAS1_IMIN_EQFL_BITS 1 7295 #define RX0_RX_ANALOGBIAS1_IMIN_EQFL_SHIFT 10 7296 7297 /* RX0 :: Rx_analogBias1 :: imax_dfesum [09:09] */ 7298 #define RX0_RX_ANALOGBIAS1_IMAX_DFESUM_MASK 0x0200 7299 #define RX0_RX_ANALOGBIAS1_IMAX_DFESUM_ALIGN 0 7300 #define RX0_RX_ANALOGBIAS1_IMAX_DFESUM_BITS 1 7301 #define RX0_RX_ANALOGBIAS1_IMAX_DFESUM_SHIFT 9 7302 7303 /* RX0 :: Rx_analogBias1 :: imode_dfesum [08:08] */ 7304 #define RX0_RX_ANALOGBIAS1_IMODE_DFESUM_MASK 0x0100 7305 #define RX0_RX_ANALOGBIAS1_IMODE_DFESUM_ALIGN 0 7306 #define RX0_RX_ANALOGBIAS1_IMODE_DFESUM_BITS 1 7307 #define RX0_RX_ANALOGBIAS1_IMODE_DFESUM_SHIFT 8 7308 7309 /* RX0 :: Rx_analogBias1 :: imin_dfesum [07:07] */ 7310 #define RX0_RX_ANALOGBIAS1_IMIN_DFESUM_MASK 0x0080 7311 #define RX0_RX_ANALOGBIAS1_IMIN_DFESUM_ALIGN 0 7312 #define RX0_RX_ANALOGBIAS1_IMIN_DFESUM_BITS 1 7313 #define RX0_RX_ANALOGBIAS1_IMIN_DFESUM_SHIFT 7 7314 7315 /* RX0 :: Rx_analogBias1 :: imax_vga [06:06] */ 7316 #define RX0_RX_ANALOGBIAS1_IMAX_VGA_MASK 0x0040 7317 #define RX0_RX_ANALOGBIAS1_IMAX_VGA_ALIGN 0 7318 #define RX0_RX_ANALOGBIAS1_IMAX_VGA_BITS 1 7319 #define RX0_RX_ANALOGBIAS1_IMAX_VGA_SHIFT 6 7320 7321 /* RX0 :: Rx_analogBias1 :: imode_vga [05:05] */ 7322 #define RX0_RX_ANALOGBIAS1_IMODE_VGA_MASK 0x0020 7323 #define RX0_RX_ANALOGBIAS1_IMODE_VGA_ALIGN 0 7324 #define RX0_RX_ANALOGBIAS1_IMODE_VGA_BITS 1 7325 #define RX0_RX_ANALOGBIAS1_IMODE_VGA_SHIFT 5 7326 7327 /* RX0 :: Rx_analogBias1 :: imin_vga [04:04] */ 7328 #define RX0_RX_ANALOGBIAS1_IMIN_VGA_MASK 0x0010 7329 #define RX0_RX_ANALOGBIAS1_IMIN_VGA_ALIGN 0 7330 #define RX0_RX_ANALOGBIAS1_IMIN_VGA_BITS 1 7331 #define RX0_RX_ANALOGBIAS1_IMIN_VGA_SHIFT 4 7332 7333 /* RX0 :: Rx_analogBias1 :: imax_interp [03:03] */ 7334 #define RX0_RX_ANALOGBIAS1_IMAX_INTERP_MASK 0x0008 7335 #define RX0_RX_ANALOGBIAS1_IMAX_INTERP_ALIGN 0 7336 #define RX0_RX_ANALOGBIAS1_IMAX_INTERP_BITS 1 7337 #define RX0_RX_ANALOGBIAS1_IMAX_INTERP_SHIFT 3 7338 7339 /* RX0 :: Rx_analogBias1 :: imode_interp [02:02] */ 7340 #define RX0_RX_ANALOGBIAS1_IMODE_INTERP_MASK 0x0004 7341 #define RX0_RX_ANALOGBIAS1_IMODE_INTERP_ALIGN 0 7342 #define RX0_RX_ANALOGBIAS1_IMODE_INTERP_BITS 1 7343 #define RX0_RX_ANALOGBIAS1_IMODE_INTERP_SHIFT 2 7344 7345 /* RX0 :: Rx_analogBias1 :: imin_interp [01:01] */ 7346 #define RX0_RX_ANALOGBIAS1_IMIN_INTERP_MASK 0x0002 7347 #define RX0_RX_ANALOGBIAS1_IMIN_INTERP_ALIGN 0 7348 #define RX0_RX_ANALOGBIAS1_IMIN_INTERP_BITS 1 7349 #define RX0_RX_ANALOGBIAS1_IMIN_INTERP_SHIFT 1 7350 7351 /* RX0 :: Rx_analogBias1 :: imax_vcm [00:00] */ 7352 #define RX0_RX_ANALOGBIAS1_IMAX_VCM_MASK 0x0001 7353 #define RX0_RX_ANALOGBIAS1_IMAX_VCM_ALIGN 0 7354 #define RX0_RX_ANALOGBIAS1_IMAX_VCM_BITS 1 7355 #define RX0_RX_ANALOGBIAS1_IMAX_VCM_SHIFT 0 7356 7357 7358 /**************************************************************************** 7359 * RX0 :: Rx_analogBias2 7360 */ 7361 /* RX0 :: Rx_analogBias2 :: en_clk16 [15:15] */ 7362 #define RX0_RX_ANALOGBIAS2_EN_CLK16_MASK 0x8000 7363 #define RX0_RX_ANALOGBIAS2_EN_CLK16_ALIGN 0 7364 #define RX0_RX_ANALOGBIAS2_EN_CLK16_BITS 1 7365 #define RX0_RX_ANALOGBIAS2_EN_CLK16_SHIFT 15 7366 7367 /* RX0 :: Rx_analogBias2 :: pd_ch_p1 [14:14] */ 7368 #define RX0_RX_ANALOGBIAS2_PD_CH_P1_MASK 0x4000 7369 #define RX0_RX_ANALOGBIAS2_PD_CH_P1_ALIGN 0 7370 #define RX0_RX_ANALOGBIAS2_PD_CH_P1_BITS 1 7371 #define RX0_RX_ANALOGBIAS2_PD_CH_P1_SHIFT 14 7372 7373 /* RX0 :: Rx_analogBias2 :: en_vcctrl [13:13] */ 7374 #define RX0_RX_ANALOGBIAS2_EN_VCCTRL_MASK 0x2000 7375 #define RX0_RX_ANALOGBIAS2_EN_VCCTRL_ALIGN 0 7376 #define RX0_RX_ANALOGBIAS2_EN_VCCTRL_BITS 1 7377 #define RX0_RX_ANALOGBIAS2_EN_VCCTRL_SHIFT 13 7378 7379 /* RX0 :: Rx_analogBias2 :: en_dfeclk [12:12] */ 7380 #define RX0_RX_ANALOGBIAS2_EN_DFECLK_MASK 0x1000 7381 #define RX0_RX_ANALOGBIAS2_EN_DFECLK_ALIGN 0 7382 #define RX0_RX_ANALOGBIAS2_EN_DFECLK_BITS 1 7383 #define RX0_RX_ANALOGBIAS2_EN_DFECLK_SHIFT 12 7384 7385 /* RX0 :: Rx_analogBias2 :: en_hgain [11:11] */ 7386 #define RX0_RX_ANALOGBIAS2_EN_HGAIN_MASK 0x0800 7387 #define RX0_RX_ANALOGBIAS2_EN_HGAIN_ALIGN 0 7388 #define RX0_RX_ANALOGBIAS2_EN_HGAIN_BITS 1 7389 #define RX0_RX_ANALOGBIAS2_EN_HGAIN_SHIFT 11 7390 7391 /* RX0 :: Rx_analogBias2 :: en_dfeckpwr [10:10] */ 7392 #define RX0_RX_ANALOGBIAS2_EN_DFECKPWR_MASK 0x0400 7393 #define RX0_RX_ANALOGBIAS2_EN_DFECKPWR_ALIGN 0 7394 #define RX0_RX_ANALOGBIAS2_EN_DFECKPWR_BITS 1 7395 #define RX0_RX_ANALOGBIAS2_EN_DFECKPWR_SHIFT 10 7396 7397 /* RX0 :: Rx_analogBias2 :: offset_pd [09:09] */ 7398 #define RX0_RX_ANALOGBIAS2_OFFSET_PD_MASK 0x0200 7399 #define RX0_RX_ANALOGBIAS2_OFFSET_PD_ALIGN 0 7400 #define RX0_RX_ANALOGBIAS2_OFFSET_PD_BITS 1 7401 #define RX0_RX_ANALOGBIAS2_OFFSET_PD_SHIFT 9 7402 7403 /* RX0 :: Rx_analogBias2 :: imax_dfetap [08:08] */ 7404 #define RX0_RX_ANALOGBIAS2_IMAX_DFETAP_MASK 0x0100 7405 #define RX0_RX_ANALOGBIAS2_IMAX_DFETAP_ALIGN 0 7406 #define RX0_RX_ANALOGBIAS2_IMAX_DFETAP_BITS 1 7407 #define RX0_RX_ANALOGBIAS2_IMAX_DFETAP_SHIFT 8 7408 7409 /* RX0 :: Rx_analogBias2 :: imode_dfetap [07:07] */ 7410 #define RX0_RX_ANALOGBIAS2_IMODE_DFETAP_MASK 0x0080 7411 #define RX0_RX_ANALOGBIAS2_IMODE_DFETAP_ALIGN 0 7412 #define RX0_RX_ANALOGBIAS2_IMODE_DFETAP_BITS 1 7413 #define RX0_RX_ANALOGBIAS2_IMODE_DFETAP_SHIFT 7 7414 7415 /* RX0 :: Rx_analogBias2 :: imin_dfetap [06:06] */ 7416 #define RX0_RX_ANALOGBIAS2_IMIN_DFETAP_MASK 0x0040 7417 #define RX0_RX_ANALOGBIAS2_IMIN_DFETAP_ALIGN 0 7418 #define RX0_RX_ANALOGBIAS2_IMIN_DFETAP_BITS 1 7419 #define RX0_RX_ANALOGBIAS2_IMIN_DFETAP_SHIFT 6 7420 7421 /* RX0 :: Rx_analogBias2 :: imax_slcd2c [05:05] */ 7422 #define RX0_RX_ANALOGBIAS2_IMAX_SLCD2C_MASK 0x0020 7423 #define RX0_RX_ANALOGBIAS2_IMAX_SLCD2C_ALIGN 0 7424 #define RX0_RX_ANALOGBIAS2_IMAX_SLCD2C_BITS 1 7425 #define RX0_RX_ANALOGBIAS2_IMAX_SLCD2C_SHIFT 5 7426 7427 /* RX0 :: Rx_analogBias2 :: imode_slcd2c [04:04] */ 7428 #define RX0_RX_ANALOGBIAS2_IMODE_SLCD2C_MASK 0x0010 7429 #define RX0_RX_ANALOGBIAS2_IMODE_SLCD2C_ALIGN 0 7430 #define RX0_RX_ANALOGBIAS2_IMODE_SLCD2C_BITS 1 7431 #define RX0_RX_ANALOGBIAS2_IMODE_SLCD2C_SHIFT 4 7432 7433 /* RX0 :: Rx_analogBias2 :: imin_slcd2c [03:03] */ 7434 #define RX0_RX_ANALOGBIAS2_IMIN_SLCD2C_MASK 0x0008 7435 #define RX0_RX_ANALOGBIAS2_IMIN_SLCD2C_ALIGN 0 7436 #define RX0_RX_ANALOGBIAS2_IMIN_SLCD2C_BITS 1 7437 #define RX0_RX_ANALOGBIAS2_IMIN_SLCD2C_SHIFT 3 7438 7439 /* RX0 :: Rx_analogBias2 :: imax_dfevref [02:02] */ 7440 #define RX0_RX_ANALOGBIAS2_IMAX_DFEVREF_MASK 0x0004 7441 #define RX0_RX_ANALOGBIAS2_IMAX_DFEVREF_ALIGN 0 7442 #define RX0_RX_ANALOGBIAS2_IMAX_DFEVREF_BITS 1 7443 #define RX0_RX_ANALOGBIAS2_IMAX_DFEVREF_SHIFT 2 7444 7445 /* RX0 :: Rx_analogBias2 :: imode_dfevref [01:01] */ 7446 #define RX0_RX_ANALOGBIAS2_IMODE_DFEVREF_MASK 0x0002 7447 #define RX0_RX_ANALOGBIAS2_IMODE_DFEVREF_ALIGN 0 7448 #define RX0_RX_ANALOGBIAS2_IMODE_DFEVREF_BITS 1 7449 #define RX0_RX_ANALOGBIAS2_IMODE_DFEVREF_SHIFT 1 7450 7451 /* RX0 :: Rx_analogBias2 :: imin_dfevref [00:00] */ 7452 #define RX0_RX_ANALOGBIAS2_IMIN_DFEVREF_MASK 0x0001 7453 #define RX0_RX_ANALOGBIAS2_IMIN_DFEVREF_ALIGN 0 7454 #define RX0_RX_ANALOGBIAS2_IMIN_DFEVREF_BITS 1 7455 #define RX0_RX_ANALOGBIAS2_IMIN_DFEVREF_SHIFT 0 7456 7457 7458 /**************************************************************************** 7459 * XGXS16G_USER_RX1 7460 */ 7461 /**************************************************************************** 7462 * RX1 :: Rx_Status 7463 */ 7464 /* union - case sigdet_Status [15:00] */ 7465 /* RX1 :: Rx_Status :: cx4_sigdet [15:15] */ 7466 #define RX1_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 7467 #define RX1_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 7468 #define RX1_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 7469 #define RX1_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 7470 7471 /* RX1 :: Rx_Status :: reserved0 [14:13] */ 7472 #define RX1_RX_STATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 7473 #define RX1_RX_STATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 7474 #define RX1_RX_STATUS_SIGDET_STATUS_RESERVED0_BITS 2 7475 #define RX1_RX_STATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 7476 7477 /* RX1 :: Rx_Status :: rxSeqDone [12:12] */ 7478 #define RX1_RX_STATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 7479 #define RX1_RX_STATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 7480 #define RX1_RX_STATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 7481 #define RX1_RX_STATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 7482 7483 /* RX1 :: Rx_Status :: rx_sigdet_ll [11:11] */ 7484 #define RX1_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 7485 #define RX1_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 7486 #define RX1_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 7487 #define RX1_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 7488 7489 /* RX1 :: Rx_Status :: cs4_sigdet_ll [10:10] */ 7490 #define RX1_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 7491 #define RX1_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 7492 #define RX1_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 7493 #define RX1_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 7494 7495 /* RX1 :: Rx_Status :: rx_reset [09:09] */ 7496 #define RX1_RX_STATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 7497 #define RX1_RX_STATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 7498 #define RX1_RX_STATUS_SIGDET_STATUS_RX_RESET_BITS 1 7499 #define RX1_RX_STATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 7500 7501 /* RX1 :: Rx_Status :: rx_pwrdn [08:08] */ 7502 #define RX1_RX_STATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 7503 #define RX1_RX_STATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 7504 #define RX1_RX_STATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 7505 #define RX1_RX_STATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 7506 7507 /* RX1 :: Rx_Status :: reserved1 [07:00] */ 7508 #define RX1_RX_STATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 7509 #define RX1_RX_STATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 7510 #define RX1_RX_STATUS_SIGDET_STATUS_RESERVED1_BITS 8 7511 #define RX1_RX_STATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 7512 7513 7514 /* union - case sync_Status [15:00] */ 7515 /* RX1 :: Rx_Status :: reserved0 [15:11] */ 7516 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 7517 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED0_ALIGN 0 7518 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED0_BITS 5 7519 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED0_SHIFT 11 7520 7521 /* RX1 :: Rx_Status :: test_acq_en [10:10] */ 7522 #define RX1_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 7523 #define RX1_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 7524 #define RX1_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 7525 #define RX1_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 7526 7527 /* RX1 :: Rx_Status :: reserved1 [09:09] */ 7528 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 7529 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED1_ALIGN 0 7530 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED1_BITS 1 7531 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED1_SHIFT 9 7532 7533 /* RX1 :: Rx_Status :: rxSeqStart [08:08] */ 7534 #define RX1_RX_STATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 7535 #define RX1_RX_STATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 7536 #define RX1_RX_STATUS_SYNC_STATUS_RXSEQSTART_BITS 1 7537 #define RX1_RX_STATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 7538 7539 /* RX1 :: Rx_Status :: mux_comadj_sync_status [07:07] */ 7540 #define RX1_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 7541 #define RX1_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 7542 #define RX1_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 7543 #define RX1_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 7544 7545 /* RX1 :: Rx_Status :: sync_status [06:06] */ 7546 #define RX1_RX_STATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 7547 #define RX1_RX_STATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 7548 #define RX1_RX_STATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 7549 #define RX1_RX_STATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 7550 7551 /* RX1 :: Rx_Status :: rx_sigdet [05:05] */ 7552 #define RX1_RX_STATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 7553 #define RX1_RX_STATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 7554 #define RX1_RX_STATUS_SYNC_STATUS_RX_SIGDET_BITS 1 7555 #define RX1_RX_STATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 7556 7557 /* RX1 :: Rx_Status :: reserved2 [04:03] */ 7558 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 7559 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED2_ALIGN 0 7560 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED2_BITS 2 7561 #define RX1_RX_STATUS_SYNC_STATUS_RESERVED2_SHIFT 3 7562 7563 /* RX1 :: Rx_Status :: saturate_status [02:02] */ 7564 #define RX1_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 7565 #define RX1_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 7566 #define RX1_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 7567 #define RX1_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 7568 7569 /* RX1 :: Rx_Status :: cx4_sigdet [01:01] */ 7570 #define RX1_RX_STATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 7571 #define RX1_RX_STATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 7572 #define RX1_RX_STATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 7573 #define RX1_RX_STATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 7574 7575 /* RX1 :: Rx_Status :: rxSeqDone [00:00] */ 7576 #define RX1_RX_STATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 7577 #define RX1_RX_STATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 7578 #define RX1_RX_STATUS_SYNC_STATUS_RXSEQDONE_BITS 1 7579 #define RX1_RX_STATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 7580 7581 7582 /* union - case rxTestSel_0 [15:00] */ 7583 /* RX1 :: Rx_Status :: reserved0 [15:10] */ 7584 #define RX1_RX_STATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 7585 #define RX1_RX_STATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 7586 #define RX1_RX_STATUS_RXTESTSEL_0_RESERVED0_BITS 6 7587 #define RX1_RX_STATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 7588 7589 /* RX1 :: Rx_Status :: indck_mode_en [09:09] */ 7590 #define RX1_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 7591 #define RX1_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 7592 #define RX1_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 7593 #define RX1_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 7594 7595 /* RX1 :: Rx_Status :: pci_mode_en [08:08] */ 7596 #define RX1_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 7597 #define RX1_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 7598 #define RX1_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 7599 #define RX1_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 7600 7601 /* RX1 :: Rx_Status :: rx_polarity [07:07] */ 7602 #define RX1_RX_STATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 7603 #define RX1_RX_STATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 7604 #define RX1_RX_STATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 7605 #define RX1_RX_STATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 7606 7607 /* RX1 :: Rx_Status :: rxpol_flip [06:06] */ 7608 #define RX1_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 7609 #define RX1_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 7610 #define RX1_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 7611 #define RX1_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 7612 7613 /* RX1 :: Rx_Status :: comma_mask [05:05] */ 7614 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 7615 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 7616 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 7617 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 7618 7619 /* RX1 :: Rx_Status :: link_en_r [04:04] */ 7620 #define RX1_RX_STATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 7621 #define RX1_RX_STATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 7622 #define RX1_RX_STATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 7623 #define RX1_RX_STATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 7624 7625 /* RX1 :: Rx_Status :: comma_adj_en [03:03] */ 7626 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 7627 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 7628 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 7629 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 7630 7631 /* RX1 :: Rx_Status :: comma_adj_en_ext [02:02] */ 7632 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 7633 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 7634 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 7635 #define RX1_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 7636 7637 /* RX1 :: Rx_Status :: reserved1 [01:00] */ 7638 #define RX1_RX_STATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 7639 #define RX1_RX_STATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 7640 #define RX1_RX_STATUS_RXTESTSEL_0_RESERVED1_BITS 2 7641 #define RX1_RX_STATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 7642 7643 7644 /* union - case rxTestSel_1 [15:00] */ 7645 /* RX1 :: Rx_Status :: reserved0 [15:05] */ 7646 #define RX1_RX_STATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 7647 #define RX1_RX_STATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 7648 #define RX1_RX_STATUS_RXTESTSEL_1_RESERVED0_BITS 11 7649 #define RX1_RX_STATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 7650 7651 /* RX1 :: Rx_Status :: cdrAcqDone_r2 [04:04] */ 7652 #define RX1_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 7653 #define RX1_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 7654 #define RX1_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 7655 #define RX1_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 7656 7657 /* RX1 :: Rx_Status :: freq_sel_PC [03:03] */ 7658 #define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 7659 #define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 7660 #define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 7661 #define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 7662 7663 /* RX1 :: Rx_Status :: freq_sel_SM [02:02] */ 7664 #define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 7665 #define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 7666 #define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 7667 #define RX1_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 7668 7669 /* RX1 :: Rx_Status :: integ_mode_SM [01:00] */ 7670 #define RX1_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 7671 #define RX1_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 7672 #define RX1_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 7673 #define RX1_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 7674 7675 7676 /* union - case scale_Status [15:00] */ 7677 /* RX1 :: Rx_Status :: prop_scale [15:12] */ 7678 #define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 7679 #define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 7680 #define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_BITS 4 7681 #define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 7682 7683 /* RX1 :: Rx_Status :: integ_scale [11:08] */ 7684 #define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 7685 #define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 7686 #define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 7687 #define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 7688 7689 /* RX1 :: Rx_Status :: prop_scale_acq [07:04] */ 7690 #define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 7691 #define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 7692 #define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 7693 #define RX1_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 7694 7695 /* RX1 :: Rx_Status :: integ_scale_acq [03:00] */ 7696 #define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 7697 #define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 7698 #define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 7699 #define RX1_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 7700 7701 7702 /* union - case adc_CdrStatus1 [15:00] */ 7703 /* RX1 :: Rx_Status :: reserved0 [15:07] */ 7704 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 7705 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 7706 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 7707 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 7708 7709 /* RX1 :: Rx_Status :: rxMuxCkSel [06:06] */ 7710 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 7711 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 7712 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 7713 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 7714 7715 /* RX1 :: Rx_Status :: glpbk_combo [05:05] */ 7716 #define RX1_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 7717 #define RX1_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 7718 #define RX1_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 7719 #define RX1_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 7720 7721 /* RX1 :: Rx_Status :: clockSwitchSel [04:04] */ 7722 #define RX1_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 7723 #define RX1_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 7724 #define RX1_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 7725 #define RX1_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 7726 7727 /* RX1 :: Rx_Status :: rxck_tst [03:03] */ 7728 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 7729 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 7730 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 7731 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 7732 7733 /* RX1 :: Rx_Status :: rxck_i [02:02] */ 7734 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 7735 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 7736 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 7737 #define RX1_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 7738 7739 /* RX1 :: Rx_Status :: refclk [01:01] */ 7740 #define RX1_RX_STATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 7741 #define RX1_RX_STATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 7742 #define RX1_RX_STATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 7743 #define RX1_RX_STATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 7744 7745 /* RX1 :: Rx_Status :: pll_bypass [00:00] */ 7746 #define RX1_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 7747 #define RX1_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 7748 #define RX1_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 7749 #define RX1_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 7750 7751 7752 /* union - case adc_CdrStatus2 [15:00] */ 7753 /* RX1 :: Rx_Status :: reserved0 [15:06] */ 7754 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 7755 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 7756 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 7757 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 7758 7759 /* RX1 :: Rx_Status :: rxMuxCkSel [05:05] */ 7760 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 7761 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 7762 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 7763 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 7764 7765 /* RX1 :: Rx_Status :: rxSeqStart [04:04] */ 7766 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 7767 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 7768 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 7769 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 7770 7771 /* RX1 :: Rx_Status :: reserved1 [03:01] */ 7772 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 7773 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 7774 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 7775 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 7776 7777 /* RX1 :: Rx_Status :: rxSeqDone [00:00] */ 7778 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 7779 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 7780 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 7781 #define RX1_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 7782 7783 7784 /* union - case adc_CdrStatus3 [15:00] */ 7785 /* RX1 :: Rx_Status :: reserved0 [15:04] */ 7786 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 7787 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 7788 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 7789 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 7790 7791 /* RX1 :: Rx_Status :: rxSeqStart [03:03] */ 7792 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 7793 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 7794 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 7795 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 7796 7797 /* RX1 :: Rx_Status :: reserved1 [02:01] */ 7798 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 7799 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 7800 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 7801 #define RX1_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 7802 7803 /* RX1 :: Rx_Status :: allow_increment_PC [00:00] */ 7804 #define RX1_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 7805 #define RX1_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 7806 #define RX1_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 7807 #define RX1_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 7808 7809 7810 /* union - case adc_CdrStatus4 [15:00] */ 7811 /* RX1 :: Rx_Status :: reserved0 [15:08] */ 7812 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 7813 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 7814 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 7815 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 7816 7817 /* RX1 :: Rx_Status :: rx_pwrdn [07:07] */ 7818 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 7819 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 7820 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 7821 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 7822 7823 /* RX1 :: Rx_Status :: freq_sel [06:06] */ 7824 #define RX1_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 7825 #define RX1_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 7826 #define RX1_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 7827 #define RX1_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 7828 7829 /* RX1 :: Rx_Status :: pll_lock_rstb [05:05] */ 7830 #define RX1_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 7831 #define RX1_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 7832 #define RX1_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 7833 #define RX1_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 7834 7835 /* RX1 :: Rx_Status :: pwrdn [04:04] */ 7836 #define RX1_RX_STATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 7837 #define RX1_RX_STATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 7838 #define RX1_RX_STATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 7839 #define RX1_RX_STATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 7840 7841 /* RX1 :: Rx_Status :: reserved1 [03:00] */ 7842 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 7843 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 7844 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 7845 #define RX1_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 7846 7847 7848 /* union - case adc_CdrStatus5 [15:00] */ 7849 /* RX1 :: Rx_Status :: reserved0 [15:00] */ 7850 #define RX1_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 7851 #define RX1_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 7852 #define RX1_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 7853 #define RX1_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 7854 7855 7856 /* union - case adc_CdrStatus6 [15:00] */ 7857 /* RX1 :: Rx_Status :: reserved0 [15:05] */ 7858 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 7859 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 7860 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 7861 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 7862 7863 /* RX1 :: Rx_Status :: rx_reset [04:04] */ 7864 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 7865 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 7866 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 7867 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 7868 7869 /* RX1 :: Rx_Status :: rx_pwrdn [03:03] */ 7870 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 7871 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 7872 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 7873 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 7874 7875 /* RX1 :: Rx_Status :: reset_anlg [02:02] */ 7876 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 7877 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 7878 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 7879 #define RX1_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 7880 7881 /* RX1 :: Rx_Status :: pwrdn_rx [01:01] */ 7882 #define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 7883 #define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 7884 #define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 7885 #define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 7886 7887 /* RX1 :: Rx_Status :: pwrdn_pll [00:00] */ 7888 #define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 7889 #define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 7890 #define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 7891 #define RX1_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 7892 7893 7894 /* union - case adc_CdrStatus7e [15:00] */ 7895 /* RX1 :: Rx_Status :: reserved0 [15:05] */ 7896 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 7897 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 7898 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 7899 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 7900 7901 /* RX1 :: Rx_Status :: rxck0_even [04:04] */ 7902 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 7903 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 7904 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 7905 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 7906 7907 /* RX1 :: Rx_Status :: rxck1_even [03:03] */ 7908 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 7909 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 7910 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 7911 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 7912 7913 /* RX1 :: Rx_Status :: comdet_even [02:02] */ 7914 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 7915 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 7916 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 7917 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 7918 7919 /* RX1 :: Rx_Status :: en_cdet_even [01:01] */ 7920 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 7921 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 7922 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 7923 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 7924 7925 /* RX1 :: Rx_Status :: comma_adj_en_even [00:00] */ 7926 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 7927 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 7928 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 7929 #define RX1_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 7930 7931 7932 /* union - case adc_CdrStatus7o [15:00] */ 7933 /* RX1 :: Rx_Status :: reserved0 [15:05] */ 7934 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 7935 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 7936 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 7937 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 7938 7939 /* RX1 :: Rx_Status :: rxck0_odd [04:04] */ 7940 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 7941 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 7942 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 7943 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 7944 7945 /* RX1 :: Rx_Status :: rxck1_odd [03:03] */ 7946 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 7947 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 7948 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 7949 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 7950 7951 /* RX1 :: Rx_Status :: comdet_odd [02:02] */ 7952 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 7953 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 7954 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 7955 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 7956 7957 /* RX1 :: Rx_Status :: en_cdet_odd [01:01] */ 7958 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 7959 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 7960 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 7961 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 7962 7963 /* RX1 :: Rx_Status :: comma_adj_en_odd [00:00] */ 7964 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 7965 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 7966 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 7967 #define RX1_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 7968 7969 7970 /* union - case adc_CdrStatus8 [15:00] */ 7971 /* RX1 :: Rx_Status :: reserved0 [15:01] */ 7972 #define RX1_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 7973 #define RX1_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 7974 #define RX1_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 7975 #define RX1_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 7976 7977 /* RX1 :: Rx_Status :: sigdet [00:00] */ 7978 #define RX1_RX_STATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 7979 #define RX1_RX_STATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 7980 #define RX1_RX_STATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 7981 #define RX1_RX_STATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 7982 7983 7984 /* union - case adc_CdrStatus9 [15:00] */ 7985 /* RX1 :: Rx_Status :: reserved0 [15:00] */ 7986 #define RX1_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 7987 #define RX1_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 7988 #define RX1_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 7989 #define RX1_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 7990 7991 7992 /* union - case adc_CdrStatus10 [15:00] */ 7993 /* RX1 :: Rx_Status :: reserved0 [15:07] */ 7994 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 7995 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 7996 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 7997 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 7998 7999 /* RX1 :: Rx_Status :: prbs_en [06:06] */ 8000 #define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 8001 #define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 8002 #define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 8003 #define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 8004 8005 /* RX1 :: Rx_Status :: rstb_tst [05:05] */ 8006 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 8007 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 8008 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 8009 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 8010 8011 /* RX1 :: Rx_Status :: reserved1 [04:04] */ 8012 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 8013 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 8014 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 8015 #define RX1_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 8016 8017 /* RX1 :: Rx_Status :: prbs_state [03:00] */ 8018 #define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 8019 #define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 8020 #define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 8021 #define RX1_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 8022 8023 8024 /* union - case adc_CdrStatus11 [15:00] */ 8025 /* RX1 :: Rx_Status :: reserved0 [15:00] */ 8026 #define RX1_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 8027 #define RX1_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 8028 #define RX1_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 8029 #define RX1_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 8030 8031 8032 /* union - case adc_CdrStatus12_1 [15:00] */ 8033 /* RX1 :: Rx_Status :: reserved0 [15:06] */ 8034 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 8035 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 8036 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 8037 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 8038 8039 /* RX1 :: Rx_Status :: enable4 [05:05] */ 8040 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 8041 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 8042 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 8043 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 8044 8045 /* RX1 :: Rx_Status :: radr_test [04:00] */ 8046 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 8047 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 8048 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 8049 #define RX1_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 8050 8051 8052 /* union - case adc_CdrStatus12_2 [15:00] */ 8053 /* RX1 :: Rx_Status :: reserved0 [15:05] */ 8054 #define RX1_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 8055 #define RX1_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 8056 #define RX1_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 8057 #define RX1_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 8058 8059 /* RX1 :: Rx_Status :: wadr_test [04:00] */ 8060 #define RX1_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 8061 #define RX1_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 8062 #define RX1_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 8063 #define RX1_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 8064 8065 8066 /* union - case adc_CdrStatus12_3 [15:00] */ 8067 /* RX1 :: Rx_Status :: reserved0 [15:06] */ 8068 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 8069 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 8070 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 8071 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 8072 8073 /* RX1 :: Rx_Status :: rxck_66B_tmux [05:05] */ 8074 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 8075 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 8076 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 8077 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 8078 8079 /* RX1 :: Rx_Status :: rstb_66B [04:04] */ 8080 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 8081 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 8082 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 8083 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 8084 8085 /* RX1 :: Rx_Status :: prstb_66B_mux [03:03] */ 8086 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 8087 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 8088 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 8089 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 8090 8091 /* RX1 :: Rx_Status :: rxck_i66_tmux [02:02] */ 8092 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 8093 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 8094 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 8095 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 8096 8097 /* RX1 :: Rx_Status :: rstb_i66 [01:01] */ 8098 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 8099 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 8100 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 8101 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 8102 8103 /* RX1 :: Rx_Status :: prstb_i66_mux [00:00] */ 8104 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 8105 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 8106 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 8107 #define RX1_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 8108 8109 8110 /* union - case adc_CdrStatus12_4 [15:00] */ 8111 /* RX1 :: Rx_Status :: reserved0 [15:04] */ 8112 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 8113 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 8114 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 8115 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 8116 8117 /* RX1 :: Rx_Status :: rfifo_error_r [03:02] */ 8118 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 8119 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 8120 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 8121 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 8122 8123 /* RX1 :: Rx_Status :: rfifo_unflow [01:01] */ 8124 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 8125 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 8126 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 8127 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 8128 8129 /* RX1 :: Rx_Status :: rfifo_ovflow [00:00] */ 8130 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 8131 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 8132 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 8133 #define RX1_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 8134 8135 8136 /* union - case integ_Status [15:00] */ 8137 /* RX1 :: Rx_Status :: integ_status [15:00] */ 8138 #define RX1_RX_STATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 8139 #define RX1_RX_STATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 8140 #define RX1_RX_STATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 8141 #define RX1_RX_STATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 8142 8143 8144 /* union - case vco_Status [15:00] */ 8145 /* RX1 :: Rx_Status :: vco_status [15:00] */ 8146 #define RX1_RX_STATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 8147 #define RX1_RX_STATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 8148 #define RX1_RX_STATUS_VCO_STATUS_VCO_STATUS_BITS 16 8149 #define RX1_RX_STATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 8150 8151 8152 /* union - case prbs_Status [15:00] */ 8153 /* RX1 :: Rx_Status :: prbs_lock [15:15] */ 8154 #define RX1_RX_STATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 8155 #define RX1_RX_STATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 8156 #define RX1_RX_STATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 8157 #define RX1_RX_STATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 8158 8159 /* RX1 :: Rx_Status :: prbs_stky [14:14] */ 8160 #define RX1_RX_STATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 8161 #define RX1_RX_STATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 8162 #define RX1_RX_STATUS_PRBS_STATUS_PRBS_STKY_BITS 1 8163 #define RX1_RX_STATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 8164 8165 /* RX1 :: Rx_Status :: ptbs_errors [13:00] */ 8166 #define RX1_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_MASK 0x3fff 8167 #define RX1_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN 0 8168 #define RX1_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_BITS 14 8169 #define RX1_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT 0 8170 8171 8172 8173 /**************************************************************************** 8174 * RX1 :: Rx_Control 8175 */ 8176 /* RX1 :: Rx_Control :: reserved0 [15:03] */ 8177 #define RX1_RX_CONTROL_RESERVED0_MASK 0xfff8 8178 #define RX1_RX_CONTROL_RESERVED0_ALIGN 0 8179 #define RX1_RX_CONTROL_RESERVED0_BITS 13 8180 #define RX1_RX_CONTROL_RESERVED0_SHIFT 3 8181 8182 /* RX1 :: Rx_Control :: status_sel [02:00] */ 8183 #define RX1_RX_CONTROL_STATUS_SEL_MASK 0x0007 8184 #define RX1_RX_CONTROL_STATUS_SEL_ALIGN 0 8185 #define RX1_RX_CONTROL_STATUS_SEL_BITS 3 8186 #define RX1_RX_CONTROL_STATUS_SEL_SHIFT 0 8187 #define RX1_RX_CONTROL_STATUS_SEL_sigdetStatus 0 8188 #define RX1_RX_CONTROL_STATUS_SEL_syncStatus 1 8189 #define RX1_RX_CONTROL_STATUS_SEL_rxTestSel 2 8190 #define RX1_RX_CONTROL_STATUS_SEL_scaleStatus 3 8191 #define RX1_RX_CONTROL_STATUS_SEL_adcCdrStatus 4 8192 #define RX1_RX_CONTROL_STATUS_SEL_integStatus 5 8193 #define RX1_RX_CONTROL_STATUS_SEL_vcoStatus 6 8194 #define RX1_RX_CONTROL_STATUS_SEL_prbsStatus 7 8195 8196 8197 /**************************************************************************** 8198 * RX1 :: Rx_Test 8199 */ 8200 /* RX1 :: Rx_Test :: sigdet_mux_SM [15:12] */ 8201 #define RX1_RX_TEST_SIGDET_MUX_SM_MASK 0xf000 8202 #define RX1_RX_TEST_SIGDET_MUX_SM_ALIGN 0 8203 #define RX1_RX_TEST_SIGDET_MUX_SM_BITS 4 8204 #define RX1_RX_TEST_SIGDET_MUX_SM_SHIFT 12 8205 8206 /* RX1 :: Rx_Test :: reserved0 [11:09] */ 8207 #define RX1_RX_TEST_RESERVED0_MASK 0x0e00 8208 #define RX1_RX_TEST_RESERVED0_ALIGN 0 8209 #define RX1_RX_TEST_RESERVED0_BITS 3 8210 #define RX1_RX_TEST_RESERVED0_SHIFT 9 8211 8212 /* RX1 :: Rx_Test :: tpctrl_SM [08:04] */ 8213 #define RX1_RX_TEST_TPCTRL_SM_MASK 0x01f0 8214 #define RX1_RX_TEST_TPCTRL_SM_ALIGN 0 8215 #define RX1_RX_TEST_TPCTRL_SM_BITS 5 8216 #define RX1_RX_TEST_TPCTRL_SM_SHIFT 4 8217 8218 /* RX1 :: Rx_Test :: testMuxSelect_SM [03:00] */ 8219 #define RX1_RX_TEST_TESTMUXSELECT_SM_MASK 0x000f 8220 #define RX1_RX_TEST_TESTMUXSELECT_SM_ALIGN 0 8221 #define RX1_RX_TEST_TESTMUXSELECT_SM_BITS 4 8222 #define RX1_RX_TEST_TESTMUXSELECT_SM_SHIFT 0 8223 8224 8225 /**************************************************************************** 8226 * RX1 :: Rx_Control_1G_type 8227 */ 8228 /* RX1 :: Rx_Control_1G_type :: fpat_md [15:15] */ 8229 #define RX1_RX_CONTROL_1G_TYPE_FPAT_MD_MASK 0x8000 8230 #define RX1_RX_CONTROL_1G_TYPE_FPAT_MD_ALIGN 0 8231 #define RX1_RX_CONTROL_1G_TYPE_FPAT_MD_BITS 1 8232 #define RX1_RX_CONTROL_1G_TYPE_FPAT_MD_SHIFT 15 8233 8234 /* RX1 :: Rx_Control_1G_type :: pkt_count_en [14:14] */ 8235 #define RX1_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_MASK 0x4000 8236 #define RX1_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_ALIGN 0 8237 #define RX1_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_BITS 1 8238 #define RX1_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_SHIFT 14 8239 8240 /* RX1 :: Rx_Control_1G_type :: staMuxRegDis [13:13] */ 8241 #define RX1_RX_CONTROL_1G_TYPE_STAMUXREGDIS_MASK 0x2000 8242 #define RX1_RX_CONTROL_1G_TYPE_STAMUXREGDIS_ALIGN 0 8243 #define RX1_RX_CONTROL_1G_TYPE_STAMUXREGDIS_BITS 1 8244 #define RX1_RX_CONTROL_1G_TYPE_STAMUXREGDIS_SHIFT 13 8245 8246 /* RX1 :: Rx_Control_1G_type :: prbs_clr_dis [12:12] */ 8247 #define RX1_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_MASK 0x1000 8248 #define RX1_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_ALIGN 0 8249 #define RX1_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_BITS 1 8250 #define RX1_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_SHIFT 12 8251 8252 /* RX1 :: Rx_Control_1G_type :: rxd_dec_sel [11:11] */ 8253 #define RX1_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_MASK 0x0800 8254 #define RX1_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_ALIGN 0 8255 #define RX1_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_BITS 1 8256 #define RX1_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_SHIFT 11 8257 8258 /* RX1 :: Rx_Control_1G_type :: cgbad_tst [10:10] */ 8259 #define RX1_RX_CONTROL_1G_TYPE_CGBAD_TST_MASK 0x0400 8260 #define RX1_RX_CONTROL_1G_TYPE_CGBAD_TST_ALIGN 0 8261 #define RX1_RX_CONTROL_1G_TYPE_CGBAD_TST_BITS 1 8262 #define RX1_RX_CONTROL_1G_TYPE_CGBAD_TST_SHIFT 10 8263 8264 /* RX1 :: Rx_Control_1G_type :: Emon_en [09:09] */ 8265 #define RX1_RX_CONTROL_1G_TYPE_EMON_EN_MASK 0x0200 8266 #define RX1_RX_CONTROL_1G_TYPE_EMON_EN_ALIGN 0 8267 #define RX1_RX_CONTROL_1G_TYPE_EMON_EN_BITS 1 8268 #define RX1_RX_CONTROL_1G_TYPE_EMON_EN_SHIFT 9 8269 8270 /* RX1 :: Rx_Control_1G_type :: prbs_en [08:08] */ 8271 #define RX1_RX_CONTROL_1G_TYPE_PRBS_EN_MASK 0x0100 8272 #define RX1_RX_CONTROL_1G_TYPE_PRBS_EN_ALIGN 0 8273 #define RX1_RX_CONTROL_1G_TYPE_PRBS_EN_BITS 1 8274 #define RX1_RX_CONTROL_1G_TYPE_PRBS_EN_SHIFT 8 8275 8276 /* RX1 :: Rx_Control_1G_type :: cgbad_en [07:07] */ 8277 #define RX1_RX_CONTROL_1G_TYPE_CGBAD_EN_MASK 0x0080 8278 #define RX1_RX_CONTROL_1G_TYPE_CGBAD_EN_ALIGN 0 8279 #define RX1_RX_CONTROL_1G_TYPE_CGBAD_EN_BITS 1 8280 #define RX1_RX_CONTROL_1G_TYPE_CGBAD_EN_SHIFT 7 8281 8282 /* RX1 :: Rx_Control_1G_type :: cstretch [06:06] */ 8283 #define RX1_RX_CONTROL_1G_TYPE_CSTRETCH_MASK 0x0040 8284 #define RX1_RX_CONTROL_1G_TYPE_CSTRETCH_ALIGN 0 8285 #define RX1_RX_CONTROL_1G_TYPE_CSTRETCH_BITS 1 8286 #define RX1_RX_CONTROL_1G_TYPE_CSTRETCH_SHIFT 6 8287 8288 /* RX1 :: Rx_Control_1G_type :: rtbi_ckflip [05:05] */ 8289 #define RX1_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_MASK 0x0020 8290 #define RX1_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_ALIGN 0 8291 #define RX1_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_BITS 1 8292 #define RX1_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_SHIFT 5 8293 8294 /* RX1 :: Rx_Control_1G_type :: rtbi_flip [04:04] */ 8295 #define RX1_RX_CONTROL_1G_TYPE_RTBI_FLIP_MASK 0x0010 8296 #define RX1_RX_CONTROL_1G_TYPE_RTBI_FLIP_ALIGN 0 8297 #define RX1_RX_CONTROL_1G_TYPE_RTBI_FLIP_BITS 1 8298 #define RX1_RX_CONTROL_1G_TYPE_RTBI_FLIP_SHIFT 4 8299 8300 /* RX1 :: Rx_Control_1G_type :: phase_sel [03:03] */ 8301 #define RX1_RX_CONTROL_1G_TYPE_PHASE_SEL_MASK 0x0008 8302 #define RX1_RX_CONTROL_1G_TYPE_PHASE_SEL_ALIGN 0 8303 #define RX1_RX_CONTROL_1G_TYPE_PHASE_SEL_BITS 1 8304 #define RX1_RX_CONTROL_1G_TYPE_PHASE_SEL_SHIFT 3 8305 8306 /* RX1 :: Rx_Control_1G_type :: reserved0 [02:02] */ 8307 #define RX1_RX_CONTROL_1G_TYPE_RESERVED0_MASK 0x0004 8308 #define RX1_RX_CONTROL_1G_TYPE_RESERVED0_ALIGN 0 8309 #define RX1_RX_CONTROL_1G_TYPE_RESERVED0_BITS 1 8310 #define RX1_RX_CONTROL_1G_TYPE_RESERVED0_SHIFT 2 8311 8312 /* RX1 :: Rx_Control_1G_type :: freq_sel_force [01:01] */ 8313 #define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_MASK 0x0002 8314 #define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_ALIGN 0 8315 #define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_BITS 1 8316 #define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_SHIFT 1 8317 8318 /* RX1 :: Rx_Control_1G_type :: freq_sel [00:00] */ 8319 #define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_MASK 0x0001 8320 #define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_ALIGN 0 8321 #define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_BITS 1 8322 #define RX1_RX_CONTROL_1G_TYPE_FREQ_SEL_SHIFT 0 8323 8324 8325 /**************************************************************************** 8326 * RX1 :: Rx_Astatus 8327 */ 8328 /* RX1 :: Rx_Astatus :: reserved0 [15:01] */ 8329 #define RX1_RX_ASTATUS_RESERVED0_MASK 0xfffe 8330 #define RX1_RX_ASTATUS_RESERVED0_ALIGN 0 8331 #define RX1_RX_ASTATUS_RESERVED0_BITS 15 8332 #define RX1_RX_ASTATUS_RESERVED0_SHIFT 1 8333 8334 /* RX1 :: Rx_Astatus :: sigdet [00:00] */ 8335 #define RX1_RX_ASTATUS_SIGDET_MASK 0x0001 8336 #define RX1_RX_ASTATUS_SIGDET_ALIGN 0 8337 #define RX1_RX_ASTATUS_SIGDET_BITS 1 8338 #define RX1_RX_ASTATUS_SIGDET_SHIFT 0 8339 8340 8341 /**************************************************************************** 8342 * RX1 :: Rx_analogBias0 8343 */ 8344 /* RX1 :: Rx_analogBias0 :: imode_vcm [15:15] */ 8345 #define RX1_RX_ANALOGBIAS0_IMODE_VCM_MASK 0x8000 8346 #define RX1_RX_ANALOGBIAS0_IMODE_VCM_ALIGN 0 8347 #define RX1_RX_ANALOGBIAS0_IMODE_VCM_BITS 1 8348 #define RX1_RX_ANALOGBIAS0_IMODE_VCM_SHIFT 15 8349 8350 /* RX1 :: Rx_analogBias0 :: imin_vcm [14:14] */ 8351 #define RX1_RX_ANALOGBIAS0_IMIN_VCM_MASK 0x4000 8352 #define RX1_RX_ANALOGBIAS0_IMIN_VCM_ALIGN 0 8353 #define RX1_RX_ANALOGBIAS0_IMIN_VCM_BITS 1 8354 #define RX1_RX_ANALOGBIAS0_IMIN_VCM_SHIFT 14 8355 8356 /* RX1 :: Rx_analogBias0 :: imax_sigdet [13:13] */ 8357 #define RX1_RX_ANALOGBIAS0_IMAX_SIGDET_MASK 0x2000 8358 #define RX1_RX_ANALOGBIAS0_IMAX_SIGDET_ALIGN 0 8359 #define RX1_RX_ANALOGBIAS0_IMAX_SIGDET_BITS 1 8360 #define RX1_RX_ANALOGBIAS0_IMAX_SIGDET_SHIFT 13 8361 8362 /* RX1 :: Rx_analogBias0 :: imode_sigdet [12:12] */ 8363 #define RX1_RX_ANALOGBIAS0_IMODE_SIGDET_MASK 0x1000 8364 #define RX1_RX_ANALOGBIAS0_IMODE_SIGDET_ALIGN 0 8365 #define RX1_RX_ANALOGBIAS0_IMODE_SIGDET_BITS 1 8366 #define RX1_RX_ANALOGBIAS0_IMODE_SIGDET_SHIFT 12 8367 8368 /* RX1 :: Rx_analogBias0 :: imin_sigdet [11:11] */ 8369 #define RX1_RX_ANALOGBIAS0_IMIN_SIGDET_MASK 0x0800 8370 #define RX1_RX_ANALOGBIAS0_IMIN_SIGDET_ALIGN 0 8371 #define RX1_RX_ANALOGBIAS0_IMIN_SIGDET_BITS 1 8372 #define RX1_RX_ANALOGBIAS0_IMIN_SIGDET_SHIFT 11 8373 8374 /* RX1 :: Rx_analogBias0 :: refh_rx [10:10] */ 8375 #define RX1_RX_ANALOGBIAS0_REFH_RX_MASK 0x0400 8376 #define RX1_RX_ANALOGBIAS0_REFH_RX_ALIGN 0 8377 #define RX1_RX_ANALOGBIAS0_REFH_RX_BITS 1 8378 #define RX1_RX_ANALOGBIAS0_REFH_RX_SHIFT 10 8379 8380 /* RX1 :: Rx_analogBias0 :: refl_rx [09:09] */ 8381 #define RX1_RX_ANALOGBIAS0_REFL_RX_MASK 0x0200 8382 #define RX1_RX_ANALOGBIAS0_REFL_RX_ALIGN 0 8383 #define RX1_RX_ANALOGBIAS0_REFL_RX_BITS 1 8384 #define RX1_RX_ANALOGBIAS0_REFL_RX_SHIFT 9 8385 8386 /* RX1 :: Rx_analogBias0 :: tport_en [08:08] */ 8387 #define RX1_RX_ANALOGBIAS0_TPORT_EN_MASK 0x0100 8388 #define RX1_RX_ANALOGBIAS0_TPORT_EN_ALIGN 0 8389 #define RX1_RX_ANALOGBIAS0_TPORT_EN_BITS 1 8390 #define RX1_RX_ANALOGBIAS0_TPORT_EN_SHIFT 8 8391 8392 /* RX1 :: Rx_analogBias0 :: vddr_bg [07:07] */ 8393 #define RX1_RX_ANALOGBIAS0_VDDR_BG_MASK 0x0080 8394 #define RX1_RX_ANALOGBIAS0_VDDR_BG_ALIGN 0 8395 #define RX1_RX_ANALOGBIAS0_VDDR_BG_BITS 1 8396 #define RX1_RX_ANALOGBIAS0_VDDR_BG_SHIFT 7 8397 8398 /* RX1 :: Rx_analogBias0 :: sig_pwrdn [06:06] */ 8399 #define RX1_RX_ANALOGBIAS0_SIG_PWRDN_MASK 0x0040 8400 #define RX1_RX_ANALOGBIAS0_SIG_PWRDN_ALIGN 0 8401 #define RX1_RX_ANALOGBIAS0_SIG_PWRDN_BITS 1 8402 #define RX1_RX_ANALOGBIAS0_SIG_PWRDN_SHIFT 6 8403 8404 /* RX1 :: Rx_analogBias0 :: offset_ctrl [05:03] */ 8405 #define RX1_RX_ANALOGBIAS0_OFFSET_CTRL_MASK 0x0038 8406 #define RX1_RX_ANALOGBIAS0_OFFSET_CTRL_ALIGN 0 8407 #define RX1_RX_ANALOGBIAS0_OFFSET_CTRL_BITS 3 8408 #define RX1_RX_ANALOGBIAS0_OFFSET_CTRL_SHIFT 3 8409 8410 /* RX1 :: Rx_analogBias0 :: offset_sel [02:02] */ 8411 #define RX1_RX_ANALOGBIAS0_OFFSET_SEL_MASK 0x0004 8412 #define RX1_RX_ANALOGBIAS0_OFFSET_SEL_ALIGN 0 8413 #define RX1_RX_ANALOGBIAS0_OFFSET_SEL_BITS 1 8414 #define RX1_RX_ANALOGBIAS0_OFFSET_SEL_SHIFT 2 8415 8416 /* RX1 :: Rx_analogBias0 :: reserved0 [01:00] */ 8417 #define RX1_RX_ANALOGBIAS0_RESERVED0_MASK 0x0003 8418 #define RX1_RX_ANALOGBIAS0_RESERVED0_ALIGN 0 8419 #define RX1_RX_ANALOGBIAS0_RESERVED0_BITS 2 8420 #define RX1_RX_ANALOGBIAS0_RESERVED0_SHIFT 0 8421 8422 8423 /**************************************************************************** 8424 * RX1 :: Rx_analogBias1 8425 */ 8426 /* RX1 :: Rx_analogBias1 :: imax_clkbuf [15:15] */ 8427 #define RX1_RX_ANALOGBIAS1_IMAX_CLKBUF_MASK 0x8000 8428 #define RX1_RX_ANALOGBIAS1_IMAX_CLKBUF_ALIGN 0 8429 #define RX1_RX_ANALOGBIAS1_IMAX_CLKBUF_BITS 1 8430 #define RX1_RX_ANALOGBIAS1_IMAX_CLKBUF_SHIFT 15 8431 8432 /* RX1 :: Rx_analogBias1 :: imode_clkbuf [14:14] */ 8433 #define RX1_RX_ANALOGBIAS1_IMODE_CLKBUF_MASK 0x4000 8434 #define RX1_RX_ANALOGBIAS1_IMODE_CLKBUF_ALIGN 0 8435 #define RX1_RX_ANALOGBIAS1_IMODE_CLKBUF_BITS 1 8436 #define RX1_RX_ANALOGBIAS1_IMODE_CLKBUF_SHIFT 14 8437 8438 /* RX1 :: Rx_analogBias1 :: imin_clkbuf [13:13] */ 8439 #define RX1_RX_ANALOGBIAS1_IMIN_CLKBUF_MASK 0x2000 8440 #define RX1_RX_ANALOGBIAS1_IMIN_CLKBUF_ALIGN 0 8441 #define RX1_RX_ANALOGBIAS1_IMIN_CLKBUF_BITS 1 8442 #define RX1_RX_ANALOGBIAS1_IMIN_CLKBUF_SHIFT 13 8443 8444 /* RX1 :: Rx_analogBias1 :: imax_eqfl [12:12] */ 8445 #define RX1_RX_ANALOGBIAS1_IMAX_EQFL_MASK 0x1000 8446 #define RX1_RX_ANALOGBIAS1_IMAX_EQFL_ALIGN 0 8447 #define RX1_RX_ANALOGBIAS1_IMAX_EQFL_BITS 1 8448 #define RX1_RX_ANALOGBIAS1_IMAX_EQFL_SHIFT 12 8449 8450 /* RX1 :: Rx_analogBias1 :: imode_eqfl [11:11] */ 8451 #define RX1_RX_ANALOGBIAS1_IMODE_EQFL_MASK 0x0800 8452 #define RX1_RX_ANALOGBIAS1_IMODE_EQFL_ALIGN 0 8453 #define RX1_RX_ANALOGBIAS1_IMODE_EQFL_BITS 1 8454 #define RX1_RX_ANALOGBIAS1_IMODE_EQFL_SHIFT 11 8455 8456 /* RX1 :: Rx_analogBias1 :: imin_eqfl [10:10] */ 8457 #define RX1_RX_ANALOGBIAS1_IMIN_EQFL_MASK 0x0400 8458 #define RX1_RX_ANALOGBIAS1_IMIN_EQFL_ALIGN 0 8459 #define RX1_RX_ANALOGBIAS1_IMIN_EQFL_BITS 1 8460 #define RX1_RX_ANALOGBIAS1_IMIN_EQFL_SHIFT 10 8461 8462 /* RX1 :: Rx_analogBias1 :: imax_dfesum [09:09] */ 8463 #define RX1_RX_ANALOGBIAS1_IMAX_DFESUM_MASK 0x0200 8464 #define RX1_RX_ANALOGBIAS1_IMAX_DFESUM_ALIGN 0 8465 #define RX1_RX_ANALOGBIAS1_IMAX_DFESUM_BITS 1 8466 #define RX1_RX_ANALOGBIAS1_IMAX_DFESUM_SHIFT 9 8467 8468 /* RX1 :: Rx_analogBias1 :: imode_dfesum [08:08] */ 8469 #define RX1_RX_ANALOGBIAS1_IMODE_DFESUM_MASK 0x0100 8470 #define RX1_RX_ANALOGBIAS1_IMODE_DFESUM_ALIGN 0 8471 #define RX1_RX_ANALOGBIAS1_IMODE_DFESUM_BITS 1 8472 #define RX1_RX_ANALOGBIAS1_IMODE_DFESUM_SHIFT 8 8473 8474 /* RX1 :: Rx_analogBias1 :: imin_dfesum [07:07] */ 8475 #define RX1_RX_ANALOGBIAS1_IMIN_DFESUM_MASK 0x0080 8476 #define RX1_RX_ANALOGBIAS1_IMIN_DFESUM_ALIGN 0 8477 #define RX1_RX_ANALOGBIAS1_IMIN_DFESUM_BITS 1 8478 #define RX1_RX_ANALOGBIAS1_IMIN_DFESUM_SHIFT 7 8479 8480 /* RX1 :: Rx_analogBias1 :: imax_vga [06:06] */ 8481 #define RX1_RX_ANALOGBIAS1_IMAX_VGA_MASK 0x0040 8482 #define RX1_RX_ANALOGBIAS1_IMAX_VGA_ALIGN 0 8483 #define RX1_RX_ANALOGBIAS1_IMAX_VGA_BITS 1 8484 #define RX1_RX_ANALOGBIAS1_IMAX_VGA_SHIFT 6 8485 8486 /* RX1 :: Rx_analogBias1 :: imode_vga [05:05] */ 8487 #define RX1_RX_ANALOGBIAS1_IMODE_VGA_MASK 0x0020 8488 #define RX1_RX_ANALOGBIAS1_IMODE_VGA_ALIGN 0 8489 #define RX1_RX_ANALOGBIAS1_IMODE_VGA_BITS 1 8490 #define RX1_RX_ANALOGBIAS1_IMODE_VGA_SHIFT 5 8491 8492 /* RX1 :: Rx_analogBias1 :: imin_vga [04:04] */ 8493 #define RX1_RX_ANALOGBIAS1_IMIN_VGA_MASK 0x0010 8494 #define RX1_RX_ANALOGBIAS1_IMIN_VGA_ALIGN 0 8495 #define RX1_RX_ANALOGBIAS1_IMIN_VGA_BITS 1 8496 #define RX1_RX_ANALOGBIAS1_IMIN_VGA_SHIFT 4 8497 8498 /* RX1 :: Rx_analogBias1 :: imax_interp [03:03] */ 8499 #define RX1_RX_ANALOGBIAS1_IMAX_INTERP_MASK 0x0008 8500 #define RX1_RX_ANALOGBIAS1_IMAX_INTERP_ALIGN 0 8501 #define RX1_RX_ANALOGBIAS1_IMAX_INTERP_BITS 1 8502 #define RX1_RX_ANALOGBIAS1_IMAX_INTERP_SHIFT 3 8503 8504 /* RX1 :: Rx_analogBias1 :: imode_interp [02:02] */ 8505 #define RX1_RX_ANALOGBIAS1_IMODE_INTERP_MASK 0x0004 8506 #define RX1_RX_ANALOGBIAS1_IMODE_INTERP_ALIGN 0 8507 #define RX1_RX_ANALOGBIAS1_IMODE_INTERP_BITS 1 8508 #define RX1_RX_ANALOGBIAS1_IMODE_INTERP_SHIFT 2 8509 8510 /* RX1 :: Rx_analogBias1 :: imin_interp [01:01] */ 8511 #define RX1_RX_ANALOGBIAS1_IMIN_INTERP_MASK 0x0002 8512 #define RX1_RX_ANALOGBIAS1_IMIN_INTERP_ALIGN 0 8513 #define RX1_RX_ANALOGBIAS1_IMIN_INTERP_BITS 1 8514 #define RX1_RX_ANALOGBIAS1_IMIN_INTERP_SHIFT 1 8515 8516 /* RX1 :: Rx_analogBias1 :: imax_vcm [00:00] */ 8517 #define RX1_RX_ANALOGBIAS1_IMAX_VCM_MASK 0x0001 8518 #define RX1_RX_ANALOGBIAS1_IMAX_VCM_ALIGN 0 8519 #define RX1_RX_ANALOGBIAS1_IMAX_VCM_BITS 1 8520 #define RX1_RX_ANALOGBIAS1_IMAX_VCM_SHIFT 0 8521 8522 8523 /**************************************************************************** 8524 * RX1 :: Rx_analogBias2 8525 */ 8526 /* RX1 :: Rx_analogBias2 :: en_clk16 [15:15] */ 8527 #define RX1_RX_ANALOGBIAS2_EN_CLK16_MASK 0x8000 8528 #define RX1_RX_ANALOGBIAS2_EN_CLK16_ALIGN 0 8529 #define RX1_RX_ANALOGBIAS2_EN_CLK16_BITS 1 8530 #define RX1_RX_ANALOGBIAS2_EN_CLK16_SHIFT 15 8531 8532 /* RX1 :: Rx_analogBias2 :: pd_ch_p1 [14:14] */ 8533 #define RX1_RX_ANALOGBIAS2_PD_CH_P1_MASK 0x4000 8534 #define RX1_RX_ANALOGBIAS2_PD_CH_P1_ALIGN 0 8535 #define RX1_RX_ANALOGBIAS2_PD_CH_P1_BITS 1 8536 #define RX1_RX_ANALOGBIAS2_PD_CH_P1_SHIFT 14 8537 8538 /* RX1 :: Rx_analogBias2 :: en_vcctrl [13:13] */ 8539 #define RX1_RX_ANALOGBIAS2_EN_VCCTRL_MASK 0x2000 8540 #define RX1_RX_ANALOGBIAS2_EN_VCCTRL_ALIGN 0 8541 #define RX1_RX_ANALOGBIAS2_EN_VCCTRL_BITS 1 8542 #define RX1_RX_ANALOGBIAS2_EN_VCCTRL_SHIFT 13 8543 8544 /* RX1 :: Rx_analogBias2 :: en_dfeclk [12:12] */ 8545 #define RX1_RX_ANALOGBIAS2_EN_DFECLK_MASK 0x1000 8546 #define RX1_RX_ANALOGBIAS2_EN_DFECLK_ALIGN 0 8547 #define RX1_RX_ANALOGBIAS2_EN_DFECLK_BITS 1 8548 #define RX1_RX_ANALOGBIAS2_EN_DFECLK_SHIFT 12 8549 8550 /* RX1 :: Rx_analogBias2 :: en_hgain [11:11] */ 8551 #define RX1_RX_ANALOGBIAS2_EN_HGAIN_MASK 0x0800 8552 #define RX1_RX_ANALOGBIAS2_EN_HGAIN_ALIGN 0 8553 #define RX1_RX_ANALOGBIAS2_EN_HGAIN_BITS 1 8554 #define RX1_RX_ANALOGBIAS2_EN_HGAIN_SHIFT 11 8555 8556 /* RX1 :: Rx_analogBias2 :: en_dfeckpwr [10:10] */ 8557 #define RX1_RX_ANALOGBIAS2_EN_DFECKPWR_MASK 0x0400 8558 #define RX1_RX_ANALOGBIAS2_EN_DFECKPWR_ALIGN 0 8559 #define RX1_RX_ANALOGBIAS2_EN_DFECKPWR_BITS 1 8560 #define RX1_RX_ANALOGBIAS2_EN_DFECKPWR_SHIFT 10 8561 8562 /* RX1 :: Rx_analogBias2 :: offset_pd [09:09] */ 8563 #define RX1_RX_ANALOGBIAS2_OFFSET_PD_MASK 0x0200 8564 #define RX1_RX_ANALOGBIAS2_OFFSET_PD_ALIGN 0 8565 #define RX1_RX_ANALOGBIAS2_OFFSET_PD_BITS 1 8566 #define RX1_RX_ANALOGBIAS2_OFFSET_PD_SHIFT 9 8567 8568 /* RX1 :: Rx_analogBias2 :: imax_dfetap [08:08] */ 8569 #define RX1_RX_ANALOGBIAS2_IMAX_DFETAP_MASK 0x0100 8570 #define RX1_RX_ANALOGBIAS2_IMAX_DFETAP_ALIGN 0 8571 #define RX1_RX_ANALOGBIAS2_IMAX_DFETAP_BITS 1 8572 #define RX1_RX_ANALOGBIAS2_IMAX_DFETAP_SHIFT 8 8573 8574 /* RX1 :: Rx_analogBias2 :: imode_dfetap [07:07] */ 8575 #define RX1_RX_ANALOGBIAS2_IMODE_DFETAP_MASK 0x0080 8576 #define RX1_RX_ANALOGBIAS2_IMODE_DFETAP_ALIGN 0 8577 #define RX1_RX_ANALOGBIAS2_IMODE_DFETAP_BITS 1 8578 #define RX1_RX_ANALOGBIAS2_IMODE_DFETAP_SHIFT 7 8579 8580 /* RX1 :: Rx_analogBias2 :: imin_dfetap [06:06] */ 8581 #define RX1_RX_ANALOGBIAS2_IMIN_DFETAP_MASK 0x0040 8582 #define RX1_RX_ANALOGBIAS2_IMIN_DFETAP_ALIGN 0 8583 #define RX1_RX_ANALOGBIAS2_IMIN_DFETAP_BITS 1 8584 #define RX1_RX_ANALOGBIAS2_IMIN_DFETAP_SHIFT 6 8585 8586 /* RX1 :: Rx_analogBias2 :: imax_slcd2c [05:05] */ 8587 #define RX1_RX_ANALOGBIAS2_IMAX_SLCD2C_MASK 0x0020 8588 #define RX1_RX_ANALOGBIAS2_IMAX_SLCD2C_ALIGN 0 8589 #define RX1_RX_ANALOGBIAS2_IMAX_SLCD2C_BITS 1 8590 #define RX1_RX_ANALOGBIAS2_IMAX_SLCD2C_SHIFT 5 8591 8592 /* RX1 :: Rx_analogBias2 :: imode_slcd2c [04:04] */ 8593 #define RX1_RX_ANALOGBIAS2_IMODE_SLCD2C_MASK 0x0010 8594 #define RX1_RX_ANALOGBIAS2_IMODE_SLCD2C_ALIGN 0 8595 #define RX1_RX_ANALOGBIAS2_IMODE_SLCD2C_BITS 1 8596 #define RX1_RX_ANALOGBIAS2_IMODE_SLCD2C_SHIFT 4 8597 8598 /* RX1 :: Rx_analogBias2 :: imin_slcd2c [03:03] */ 8599 #define RX1_RX_ANALOGBIAS2_IMIN_SLCD2C_MASK 0x0008 8600 #define RX1_RX_ANALOGBIAS2_IMIN_SLCD2C_ALIGN 0 8601 #define RX1_RX_ANALOGBIAS2_IMIN_SLCD2C_BITS 1 8602 #define RX1_RX_ANALOGBIAS2_IMIN_SLCD2C_SHIFT 3 8603 8604 /* RX1 :: Rx_analogBias2 :: imax_dfevref [02:02] */ 8605 #define RX1_RX_ANALOGBIAS2_IMAX_DFEVREF_MASK 0x0004 8606 #define RX1_RX_ANALOGBIAS2_IMAX_DFEVREF_ALIGN 0 8607 #define RX1_RX_ANALOGBIAS2_IMAX_DFEVREF_BITS 1 8608 #define RX1_RX_ANALOGBIAS2_IMAX_DFEVREF_SHIFT 2 8609 8610 /* RX1 :: Rx_analogBias2 :: imode_dfevref [01:01] */ 8611 #define RX1_RX_ANALOGBIAS2_IMODE_DFEVREF_MASK 0x0002 8612 #define RX1_RX_ANALOGBIAS2_IMODE_DFEVREF_ALIGN 0 8613 #define RX1_RX_ANALOGBIAS2_IMODE_DFEVREF_BITS 1 8614 #define RX1_RX_ANALOGBIAS2_IMODE_DFEVREF_SHIFT 1 8615 8616 /* RX1 :: Rx_analogBias2 :: imin_dfevref [00:00] */ 8617 #define RX1_RX_ANALOGBIAS2_IMIN_DFEVREF_MASK 0x0001 8618 #define RX1_RX_ANALOGBIAS2_IMIN_DFEVREF_ALIGN 0 8619 #define RX1_RX_ANALOGBIAS2_IMIN_DFEVREF_BITS 1 8620 #define RX1_RX_ANALOGBIAS2_IMIN_DFEVREF_SHIFT 0 8621 8622 8623 /**************************************************************************** 8624 * XGXS16G_USER_RX2 8625 */ 8626 /**************************************************************************** 8627 * RX2 :: Rx_Status 8628 */ 8629 /* union - case sigdet_Status [15:00] */ 8630 /* RX2 :: Rx_Status :: cx4_sigdet [15:15] */ 8631 #define RX2_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 8632 #define RX2_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 8633 #define RX2_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 8634 #define RX2_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 8635 8636 /* RX2 :: Rx_Status :: reserved0 [14:13] */ 8637 #define RX2_RX_STATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 8638 #define RX2_RX_STATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 8639 #define RX2_RX_STATUS_SIGDET_STATUS_RESERVED0_BITS 2 8640 #define RX2_RX_STATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 8641 8642 /* RX2 :: Rx_Status :: rxSeqDone [12:12] */ 8643 #define RX2_RX_STATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 8644 #define RX2_RX_STATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 8645 #define RX2_RX_STATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 8646 #define RX2_RX_STATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 8647 8648 /* RX2 :: Rx_Status :: rx_sigdet_ll [11:11] */ 8649 #define RX2_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 8650 #define RX2_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 8651 #define RX2_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 8652 #define RX2_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 8653 8654 /* RX2 :: Rx_Status :: cs4_sigdet_ll [10:10] */ 8655 #define RX2_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 8656 #define RX2_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 8657 #define RX2_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 8658 #define RX2_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 8659 8660 /* RX2 :: Rx_Status :: rx_reset [09:09] */ 8661 #define RX2_RX_STATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 8662 #define RX2_RX_STATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 8663 #define RX2_RX_STATUS_SIGDET_STATUS_RX_RESET_BITS 1 8664 #define RX2_RX_STATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 8665 8666 /* RX2 :: Rx_Status :: rx_pwrdn [08:08] */ 8667 #define RX2_RX_STATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 8668 #define RX2_RX_STATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 8669 #define RX2_RX_STATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 8670 #define RX2_RX_STATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 8671 8672 /* RX2 :: Rx_Status :: reserved1 [07:00] */ 8673 #define RX2_RX_STATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 8674 #define RX2_RX_STATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 8675 #define RX2_RX_STATUS_SIGDET_STATUS_RESERVED1_BITS 8 8676 #define RX2_RX_STATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 8677 8678 8679 /* union - case sync_Status [15:00] */ 8680 /* RX2 :: Rx_Status :: reserved0 [15:11] */ 8681 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 8682 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED0_ALIGN 0 8683 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED0_BITS 5 8684 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED0_SHIFT 11 8685 8686 /* RX2 :: Rx_Status :: test_acq_en [10:10] */ 8687 #define RX2_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 8688 #define RX2_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 8689 #define RX2_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 8690 #define RX2_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 8691 8692 /* RX2 :: Rx_Status :: reserved1 [09:09] */ 8693 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 8694 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED1_ALIGN 0 8695 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED1_BITS 1 8696 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED1_SHIFT 9 8697 8698 /* RX2 :: Rx_Status :: rxSeqStart [08:08] */ 8699 #define RX2_RX_STATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 8700 #define RX2_RX_STATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 8701 #define RX2_RX_STATUS_SYNC_STATUS_RXSEQSTART_BITS 1 8702 #define RX2_RX_STATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 8703 8704 /* RX2 :: Rx_Status :: mux_comadj_sync_status [07:07] */ 8705 #define RX2_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 8706 #define RX2_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 8707 #define RX2_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 8708 #define RX2_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 8709 8710 /* RX2 :: Rx_Status :: sync_status [06:06] */ 8711 #define RX2_RX_STATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 8712 #define RX2_RX_STATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 8713 #define RX2_RX_STATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 8714 #define RX2_RX_STATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 8715 8716 /* RX2 :: Rx_Status :: rx_sigdet [05:05] */ 8717 #define RX2_RX_STATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 8718 #define RX2_RX_STATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 8719 #define RX2_RX_STATUS_SYNC_STATUS_RX_SIGDET_BITS 1 8720 #define RX2_RX_STATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 8721 8722 /* RX2 :: Rx_Status :: reserved2 [04:03] */ 8723 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 8724 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED2_ALIGN 0 8725 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED2_BITS 2 8726 #define RX2_RX_STATUS_SYNC_STATUS_RESERVED2_SHIFT 3 8727 8728 /* RX2 :: Rx_Status :: saturate_status [02:02] */ 8729 #define RX2_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 8730 #define RX2_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 8731 #define RX2_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 8732 #define RX2_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 8733 8734 /* RX2 :: Rx_Status :: cx4_sigdet [01:01] */ 8735 #define RX2_RX_STATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 8736 #define RX2_RX_STATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 8737 #define RX2_RX_STATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 8738 #define RX2_RX_STATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 8739 8740 /* RX2 :: Rx_Status :: rxSeqDone [00:00] */ 8741 #define RX2_RX_STATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 8742 #define RX2_RX_STATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 8743 #define RX2_RX_STATUS_SYNC_STATUS_RXSEQDONE_BITS 1 8744 #define RX2_RX_STATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 8745 8746 8747 /* union - case rxTestSel_0 [15:00] */ 8748 /* RX2 :: Rx_Status :: reserved0 [15:10] */ 8749 #define RX2_RX_STATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 8750 #define RX2_RX_STATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 8751 #define RX2_RX_STATUS_RXTESTSEL_0_RESERVED0_BITS 6 8752 #define RX2_RX_STATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 8753 8754 /* RX2 :: Rx_Status :: indck_mode_en [09:09] */ 8755 #define RX2_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 8756 #define RX2_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 8757 #define RX2_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 8758 #define RX2_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 8759 8760 /* RX2 :: Rx_Status :: pci_mode_en [08:08] */ 8761 #define RX2_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 8762 #define RX2_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 8763 #define RX2_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 8764 #define RX2_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 8765 8766 /* RX2 :: Rx_Status :: rx_polarity [07:07] */ 8767 #define RX2_RX_STATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 8768 #define RX2_RX_STATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 8769 #define RX2_RX_STATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 8770 #define RX2_RX_STATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 8771 8772 /* RX2 :: Rx_Status :: rxpol_flip [06:06] */ 8773 #define RX2_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 8774 #define RX2_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 8775 #define RX2_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 8776 #define RX2_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 8777 8778 /* RX2 :: Rx_Status :: comma_mask [05:05] */ 8779 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 8780 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 8781 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 8782 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 8783 8784 /* RX2 :: Rx_Status :: link_en_r [04:04] */ 8785 #define RX2_RX_STATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 8786 #define RX2_RX_STATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 8787 #define RX2_RX_STATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 8788 #define RX2_RX_STATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 8789 8790 /* RX2 :: Rx_Status :: comma_adj_en [03:03] */ 8791 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 8792 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 8793 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 8794 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 8795 8796 /* RX2 :: Rx_Status :: comma_adj_en_ext [02:02] */ 8797 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 8798 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 8799 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 8800 #define RX2_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 8801 8802 /* RX2 :: Rx_Status :: reserved1 [01:00] */ 8803 #define RX2_RX_STATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 8804 #define RX2_RX_STATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 8805 #define RX2_RX_STATUS_RXTESTSEL_0_RESERVED1_BITS 2 8806 #define RX2_RX_STATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 8807 8808 8809 /* union - case rxTestSel_1 [15:00] */ 8810 /* RX2 :: Rx_Status :: reserved0 [15:05] */ 8811 #define RX2_RX_STATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 8812 #define RX2_RX_STATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 8813 #define RX2_RX_STATUS_RXTESTSEL_1_RESERVED0_BITS 11 8814 #define RX2_RX_STATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 8815 8816 /* RX2 :: Rx_Status :: cdrAcqDone_r2 [04:04] */ 8817 #define RX2_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 8818 #define RX2_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 8819 #define RX2_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 8820 #define RX2_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 8821 8822 /* RX2 :: Rx_Status :: freq_sel_PC [03:03] */ 8823 #define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 8824 #define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 8825 #define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 8826 #define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 8827 8828 /* RX2 :: Rx_Status :: freq_sel_SM [02:02] */ 8829 #define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 8830 #define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 8831 #define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 8832 #define RX2_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 8833 8834 /* RX2 :: Rx_Status :: integ_mode_SM [01:00] */ 8835 #define RX2_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 8836 #define RX2_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 8837 #define RX2_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 8838 #define RX2_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 8839 8840 8841 /* union - case scale_Status [15:00] */ 8842 /* RX2 :: Rx_Status :: prop_scale [15:12] */ 8843 #define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 8844 #define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 8845 #define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_BITS 4 8846 #define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 8847 8848 /* RX2 :: Rx_Status :: integ_scale [11:08] */ 8849 #define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 8850 #define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 8851 #define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 8852 #define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 8853 8854 /* RX2 :: Rx_Status :: prop_scale_acq [07:04] */ 8855 #define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 8856 #define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 8857 #define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 8858 #define RX2_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 8859 8860 /* RX2 :: Rx_Status :: integ_scale_acq [03:00] */ 8861 #define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 8862 #define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 8863 #define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 8864 #define RX2_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 8865 8866 8867 /* union - case adc_CdrStatus1 [15:00] */ 8868 /* RX2 :: Rx_Status :: reserved0 [15:07] */ 8869 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 8870 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 8871 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 8872 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 8873 8874 /* RX2 :: Rx_Status :: rxMuxCkSel [06:06] */ 8875 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 8876 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 8877 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 8878 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 8879 8880 /* RX2 :: Rx_Status :: glpbk_combo [05:05] */ 8881 #define RX2_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 8882 #define RX2_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 8883 #define RX2_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 8884 #define RX2_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 8885 8886 /* RX2 :: Rx_Status :: clockSwitchSel [04:04] */ 8887 #define RX2_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 8888 #define RX2_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 8889 #define RX2_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 8890 #define RX2_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 8891 8892 /* RX2 :: Rx_Status :: rxck_tst [03:03] */ 8893 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 8894 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 8895 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 8896 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 8897 8898 /* RX2 :: Rx_Status :: rxck_i [02:02] */ 8899 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 8900 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 8901 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 8902 #define RX2_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 8903 8904 /* RX2 :: Rx_Status :: refclk [01:01] */ 8905 #define RX2_RX_STATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 8906 #define RX2_RX_STATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 8907 #define RX2_RX_STATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 8908 #define RX2_RX_STATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 8909 8910 /* RX2 :: Rx_Status :: pll_bypass [00:00] */ 8911 #define RX2_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 8912 #define RX2_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 8913 #define RX2_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 8914 #define RX2_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 8915 8916 8917 /* union - case adc_CdrStatus2 [15:00] */ 8918 /* RX2 :: Rx_Status :: reserved0 [15:06] */ 8919 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 8920 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 8921 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 8922 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 8923 8924 /* RX2 :: Rx_Status :: rxMuxCkSel [05:05] */ 8925 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 8926 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 8927 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 8928 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 8929 8930 /* RX2 :: Rx_Status :: rxSeqStart [04:04] */ 8931 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 8932 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 8933 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 8934 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 8935 8936 /* RX2 :: Rx_Status :: reserved1 [03:01] */ 8937 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 8938 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 8939 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 8940 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 8941 8942 /* RX2 :: Rx_Status :: rxSeqDone [00:00] */ 8943 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 8944 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 8945 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 8946 #define RX2_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 8947 8948 8949 /* union - case adc_CdrStatus3 [15:00] */ 8950 /* RX2 :: Rx_Status :: reserved0 [15:04] */ 8951 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 8952 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 8953 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 8954 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 8955 8956 /* RX2 :: Rx_Status :: rxSeqStart [03:03] */ 8957 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 8958 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 8959 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 8960 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 8961 8962 /* RX2 :: Rx_Status :: reserved1 [02:01] */ 8963 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 8964 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 8965 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 8966 #define RX2_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 8967 8968 /* RX2 :: Rx_Status :: allow_increment_PC [00:00] */ 8969 #define RX2_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 8970 #define RX2_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 8971 #define RX2_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 8972 #define RX2_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 8973 8974 8975 /* union - case adc_CdrStatus4 [15:00] */ 8976 /* RX2 :: Rx_Status :: reserved0 [15:08] */ 8977 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 8978 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 8979 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 8980 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 8981 8982 /* RX2 :: Rx_Status :: rx_pwrdn [07:07] */ 8983 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 8984 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 8985 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 8986 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 8987 8988 /* RX2 :: Rx_Status :: freq_sel [06:06] */ 8989 #define RX2_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 8990 #define RX2_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 8991 #define RX2_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 8992 #define RX2_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 8993 8994 /* RX2 :: Rx_Status :: pll_lock_rstb [05:05] */ 8995 #define RX2_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 8996 #define RX2_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 8997 #define RX2_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 8998 #define RX2_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 8999 9000 /* RX2 :: Rx_Status :: pwrdn [04:04] */ 9001 #define RX2_RX_STATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 9002 #define RX2_RX_STATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 9003 #define RX2_RX_STATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 9004 #define RX2_RX_STATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 9005 9006 /* RX2 :: Rx_Status :: reserved1 [03:00] */ 9007 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 9008 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 9009 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 9010 #define RX2_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 9011 9012 9013 /* union - case adc_CdrStatus5 [15:00] */ 9014 /* RX2 :: Rx_Status :: reserved0 [15:00] */ 9015 #define RX2_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 9016 #define RX2_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 9017 #define RX2_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 9018 #define RX2_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 9019 9020 9021 /* union - case adc_CdrStatus6 [15:00] */ 9022 /* RX2 :: Rx_Status :: reserved0 [15:05] */ 9023 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 9024 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 9025 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 9026 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 9027 9028 /* RX2 :: Rx_Status :: rx_reset [04:04] */ 9029 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 9030 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 9031 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 9032 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 9033 9034 /* RX2 :: Rx_Status :: rx_pwrdn [03:03] */ 9035 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 9036 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 9037 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 9038 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 9039 9040 /* RX2 :: Rx_Status :: reset_anlg [02:02] */ 9041 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 9042 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 9043 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 9044 #define RX2_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 9045 9046 /* RX2 :: Rx_Status :: pwrdn_rx [01:01] */ 9047 #define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 9048 #define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 9049 #define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 9050 #define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 9051 9052 /* RX2 :: Rx_Status :: pwrdn_pll [00:00] */ 9053 #define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 9054 #define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 9055 #define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 9056 #define RX2_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 9057 9058 9059 /* union - case adc_CdrStatus7e [15:00] */ 9060 /* RX2 :: Rx_Status :: reserved0 [15:05] */ 9061 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 9062 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 9063 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 9064 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 9065 9066 /* RX2 :: Rx_Status :: rxck0_even [04:04] */ 9067 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 9068 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 9069 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 9070 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 9071 9072 /* RX2 :: Rx_Status :: rxck1_even [03:03] */ 9073 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 9074 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 9075 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 9076 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 9077 9078 /* RX2 :: Rx_Status :: comdet_even [02:02] */ 9079 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 9080 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 9081 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 9082 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 9083 9084 /* RX2 :: Rx_Status :: en_cdet_even [01:01] */ 9085 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 9086 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 9087 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 9088 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 9089 9090 /* RX2 :: Rx_Status :: comma_adj_en_even [00:00] */ 9091 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 9092 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 9093 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 9094 #define RX2_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 9095 9096 9097 /* union - case adc_CdrStatus7o [15:00] */ 9098 /* RX2 :: Rx_Status :: reserved0 [15:05] */ 9099 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 9100 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 9101 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 9102 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 9103 9104 /* RX2 :: Rx_Status :: rxck0_odd [04:04] */ 9105 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 9106 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 9107 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 9108 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 9109 9110 /* RX2 :: Rx_Status :: rxck1_odd [03:03] */ 9111 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 9112 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 9113 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 9114 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 9115 9116 /* RX2 :: Rx_Status :: comdet_odd [02:02] */ 9117 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 9118 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 9119 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 9120 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 9121 9122 /* RX2 :: Rx_Status :: en_cdet_odd [01:01] */ 9123 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 9124 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 9125 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 9126 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 9127 9128 /* RX2 :: Rx_Status :: comma_adj_en_odd [00:00] */ 9129 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 9130 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 9131 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 9132 #define RX2_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 9133 9134 9135 /* union - case adc_CdrStatus8 [15:00] */ 9136 /* RX2 :: Rx_Status :: reserved0 [15:01] */ 9137 #define RX2_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 9138 #define RX2_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 9139 #define RX2_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 9140 #define RX2_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 9141 9142 /* RX2 :: Rx_Status :: sigdet [00:00] */ 9143 #define RX2_RX_STATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 9144 #define RX2_RX_STATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 9145 #define RX2_RX_STATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 9146 #define RX2_RX_STATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 9147 9148 9149 /* union - case adc_CdrStatus9 [15:00] */ 9150 /* RX2 :: Rx_Status :: reserved0 [15:00] */ 9151 #define RX2_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 9152 #define RX2_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 9153 #define RX2_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 9154 #define RX2_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 9155 9156 9157 /* union - case adc_CdrStatus10 [15:00] */ 9158 /* RX2 :: Rx_Status :: reserved0 [15:07] */ 9159 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 9160 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 9161 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 9162 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 9163 9164 /* RX2 :: Rx_Status :: prbs_en [06:06] */ 9165 #define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 9166 #define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 9167 #define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 9168 #define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 9169 9170 /* RX2 :: Rx_Status :: rstb_tst [05:05] */ 9171 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 9172 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 9173 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 9174 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 9175 9176 /* RX2 :: Rx_Status :: reserved1 [04:04] */ 9177 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 9178 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 9179 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 9180 #define RX2_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 9181 9182 /* RX2 :: Rx_Status :: prbs_state [03:00] */ 9183 #define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 9184 #define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 9185 #define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 9186 #define RX2_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 9187 9188 9189 /* union - case adc_CdrStatus11 [15:00] */ 9190 /* RX2 :: Rx_Status :: reserved0 [15:00] */ 9191 #define RX2_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 9192 #define RX2_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 9193 #define RX2_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 9194 #define RX2_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 9195 9196 9197 /* union - case adc_CdrStatus12_1 [15:00] */ 9198 /* RX2 :: Rx_Status :: reserved0 [15:06] */ 9199 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 9200 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 9201 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 9202 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 9203 9204 /* RX2 :: Rx_Status :: enable4 [05:05] */ 9205 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 9206 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 9207 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 9208 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 9209 9210 /* RX2 :: Rx_Status :: radr_test [04:00] */ 9211 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 9212 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 9213 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 9214 #define RX2_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 9215 9216 9217 /* union - case adc_CdrStatus12_2 [15:00] */ 9218 /* RX2 :: Rx_Status :: reserved0 [15:05] */ 9219 #define RX2_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 9220 #define RX2_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 9221 #define RX2_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 9222 #define RX2_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 9223 9224 /* RX2 :: Rx_Status :: wadr_test [04:00] */ 9225 #define RX2_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 9226 #define RX2_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 9227 #define RX2_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 9228 #define RX2_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 9229 9230 9231 /* union - case adc_CdrStatus12_3 [15:00] */ 9232 /* RX2 :: Rx_Status :: reserved0 [15:06] */ 9233 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 9234 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 9235 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 9236 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 9237 9238 /* RX2 :: Rx_Status :: rxck_66B_tmux [05:05] */ 9239 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 9240 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 9241 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 9242 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 9243 9244 /* RX2 :: Rx_Status :: rstb_66B [04:04] */ 9245 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 9246 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 9247 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 9248 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 9249 9250 /* RX2 :: Rx_Status :: prstb_66B_mux [03:03] */ 9251 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 9252 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 9253 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 9254 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 9255 9256 /* RX2 :: Rx_Status :: rxck_i66_tmux [02:02] */ 9257 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 9258 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 9259 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 9260 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 9261 9262 /* RX2 :: Rx_Status :: rstb_i66 [01:01] */ 9263 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 9264 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 9265 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 9266 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 9267 9268 /* RX2 :: Rx_Status :: prstb_i66_mux [00:00] */ 9269 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 9270 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 9271 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 9272 #define RX2_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 9273 9274 9275 /* union - case adc_CdrStatus12_4 [15:00] */ 9276 /* RX2 :: Rx_Status :: reserved0 [15:04] */ 9277 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 9278 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 9279 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 9280 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 9281 9282 /* RX2 :: Rx_Status :: rfifo_error_r [03:02] */ 9283 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 9284 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 9285 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 9286 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 9287 9288 /* RX2 :: Rx_Status :: rfifo_unflow [01:01] */ 9289 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 9290 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 9291 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 9292 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 9293 9294 /* RX2 :: Rx_Status :: rfifo_ovflow [00:00] */ 9295 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 9296 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 9297 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 9298 #define RX2_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 9299 9300 9301 /* union - case integ_Status [15:00] */ 9302 /* RX2 :: Rx_Status :: integ_status [15:00] */ 9303 #define RX2_RX_STATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 9304 #define RX2_RX_STATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 9305 #define RX2_RX_STATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 9306 #define RX2_RX_STATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 9307 9308 9309 /* union - case vco_Status [15:00] */ 9310 /* RX2 :: Rx_Status :: vco_status [15:00] */ 9311 #define RX2_RX_STATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 9312 #define RX2_RX_STATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 9313 #define RX2_RX_STATUS_VCO_STATUS_VCO_STATUS_BITS 16 9314 #define RX2_RX_STATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 9315 9316 9317 /* union - case prbs_Status [15:00] */ 9318 /* RX2 :: Rx_Status :: prbs_lock [15:15] */ 9319 #define RX2_RX_STATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 9320 #define RX2_RX_STATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 9321 #define RX2_RX_STATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 9322 #define RX2_RX_STATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 9323 9324 /* RX2 :: Rx_Status :: prbs_stky [14:14] */ 9325 #define RX2_RX_STATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 9326 #define RX2_RX_STATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 9327 #define RX2_RX_STATUS_PRBS_STATUS_PRBS_STKY_BITS 1 9328 #define RX2_RX_STATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 9329 9330 /* RX2 :: Rx_Status :: ptbs_errors [13:00] */ 9331 #define RX2_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_MASK 0x3fff 9332 #define RX2_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN 0 9333 #define RX2_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_BITS 14 9334 #define RX2_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT 0 9335 9336 9337 9338 /**************************************************************************** 9339 * RX2 :: Rx_Control 9340 */ 9341 /* RX2 :: Rx_Control :: reserved0 [15:03] */ 9342 #define RX2_RX_CONTROL_RESERVED0_MASK 0xfff8 9343 #define RX2_RX_CONTROL_RESERVED0_ALIGN 0 9344 #define RX2_RX_CONTROL_RESERVED0_BITS 13 9345 #define RX2_RX_CONTROL_RESERVED0_SHIFT 3 9346 9347 /* RX2 :: Rx_Control :: status_sel [02:00] */ 9348 #define RX2_RX_CONTROL_STATUS_SEL_MASK 0x0007 9349 #define RX2_RX_CONTROL_STATUS_SEL_ALIGN 0 9350 #define RX2_RX_CONTROL_STATUS_SEL_BITS 3 9351 #define RX2_RX_CONTROL_STATUS_SEL_SHIFT 0 9352 #define RX2_RX_CONTROL_STATUS_SEL_sigdetStatus 0 9353 #define RX2_RX_CONTROL_STATUS_SEL_syncStatus 1 9354 #define RX2_RX_CONTROL_STATUS_SEL_rxTestSel 2 9355 #define RX2_RX_CONTROL_STATUS_SEL_scaleStatus 3 9356 #define RX2_RX_CONTROL_STATUS_SEL_adcCdrStatus 4 9357 #define RX2_RX_CONTROL_STATUS_SEL_integStatus 5 9358 #define RX2_RX_CONTROL_STATUS_SEL_vcoStatus 6 9359 #define RX2_RX_CONTROL_STATUS_SEL_prbsStatus 7 9360 9361 9362 /**************************************************************************** 9363 * RX2 :: Rx_Test 9364 */ 9365 /* RX2 :: Rx_Test :: sigdet_mux_SM [15:12] */ 9366 #define RX2_RX_TEST_SIGDET_MUX_SM_MASK 0xf000 9367 #define RX2_RX_TEST_SIGDET_MUX_SM_ALIGN 0 9368 #define RX2_RX_TEST_SIGDET_MUX_SM_BITS 4 9369 #define RX2_RX_TEST_SIGDET_MUX_SM_SHIFT 12 9370 9371 /* RX2 :: Rx_Test :: reserved0 [11:09] */ 9372 #define RX2_RX_TEST_RESERVED0_MASK 0x0e00 9373 #define RX2_RX_TEST_RESERVED0_ALIGN 0 9374 #define RX2_RX_TEST_RESERVED0_BITS 3 9375 #define RX2_RX_TEST_RESERVED0_SHIFT 9 9376 9377 /* RX2 :: Rx_Test :: tpctrl_SM [08:04] */ 9378 #define RX2_RX_TEST_TPCTRL_SM_MASK 0x01f0 9379 #define RX2_RX_TEST_TPCTRL_SM_ALIGN 0 9380 #define RX2_RX_TEST_TPCTRL_SM_BITS 5 9381 #define RX2_RX_TEST_TPCTRL_SM_SHIFT 4 9382 9383 /* RX2 :: Rx_Test :: testMuxSelect_SM [03:00] */ 9384 #define RX2_RX_TEST_TESTMUXSELECT_SM_MASK 0x000f 9385 #define RX2_RX_TEST_TESTMUXSELECT_SM_ALIGN 0 9386 #define RX2_RX_TEST_TESTMUXSELECT_SM_BITS 4 9387 #define RX2_RX_TEST_TESTMUXSELECT_SM_SHIFT 0 9388 9389 9390 /**************************************************************************** 9391 * RX2 :: Rx_Control_1G_type 9392 */ 9393 /* RX2 :: Rx_Control_1G_type :: fpat_md [15:15] */ 9394 #define RX2_RX_CONTROL_1G_TYPE_FPAT_MD_MASK 0x8000 9395 #define RX2_RX_CONTROL_1G_TYPE_FPAT_MD_ALIGN 0 9396 #define RX2_RX_CONTROL_1G_TYPE_FPAT_MD_BITS 1 9397 #define RX2_RX_CONTROL_1G_TYPE_FPAT_MD_SHIFT 15 9398 9399 /* RX2 :: Rx_Control_1G_type :: pkt_count_en [14:14] */ 9400 #define RX2_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_MASK 0x4000 9401 #define RX2_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_ALIGN 0 9402 #define RX2_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_BITS 1 9403 #define RX2_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_SHIFT 14 9404 9405 /* RX2 :: Rx_Control_1G_type :: staMuxRegDis [13:13] */ 9406 #define RX2_RX_CONTROL_1G_TYPE_STAMUXREGDIS_MASK 0x2000 9407 #define RX2_RX_CONTROL_1G_TYPE_STAMUXREGDIS_ALIGN 0 9408 #define RX2_RX_CONTROL_1G_TYPE_STAMUXREGDIS_BITS 1 9409 #define RX2_RX_CONTROL_1G_TYPE_STAMUXREGDIS_SHIFT 13 9410 9411 /* RX2 :: Rx_Control_1G_type :: prbs_clr_dis [12:12] */ 9412 #define RX2_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_MASK 0x1000 9413 #define RX2_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_ALIGN 0 9414 #define RX2_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_BITS 1 9415 #define RX2_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_SHIFT 12 9416 9417 /* RX2 :: Rx_Control_1G_type :: rxd_dec_sel [11:11] */ 9418 #define RX2_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_MASK 0x0800 9419 #define RX2_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_ALIGN 0 9420 #define RX2_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_BITS 1 9421 #define RX2_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_SHIFT 11 9422 9423 /* RX2 :: Rx_Control_1G_type :: cgbad_tst [10:10] */ 9424 #define RX2_RX_CONTROL_1G_TYPE_CGBAD_TST_MASK 0x0400 9425 #define RX2_RX_CONTROL_1G_TYPE_CGBAD_TST_ALIGN 0 9426 #define RX2_RX_CONTROL_1G_TYPE_CGBAD_TST_BITS 1 9427 #define RX2_RX_CONTROL_1G_TYPE_CGBAD_TST_SHIFT 10 9428 9429 /* RX2 :: Rx_Control_1G_type :: Emon_en [09:09] */ 9430 #define RX2_RX_CONTROL_1G_TYPE_EMON_EN_MASK 0x0200 9431 #define RX2_RX_CONTROL_1G_TYPE_EMON_EN_ALIGN 0 9432 #define RX2_RX_CONTROL_1G_TYPE_EMON_EN_BITS 1 9433 #define RX2_RX_CONTROL_1G_TYPE_EMON_EN_SHIFT 9 9434 9435 /* RX2 :: Rx_Control_1G_type :: prbs_en [08:08] */ 9436 #define RX2_RX_CONTROL_1G_TYPE_PRBS_EN_MASK 0x0100 9437 #define RX2_RX_CONTROL_1G_TYPE_PRBS_EN_ALIGN 0 9438 #define RX2_RX_CONTROL_1G_TYPE_PRBS_EN_BITS 1 9439 #define RX2_RX_CONTROL_1G_TYPE_PRBS_EN_SHIFT 8 9440 9441 /* RX2 :: Rx_Control_1G_type :: cgbad_en [07:07] */ 9442 #define RX2_RX_CONTROL_1G_TYPE_CGBAD_EN_MASK 0x0080 9443 #define RX2_RX_CONTROL_1G_TYPE_CGBAD_EN_ALIGN 0 9444 #define RX2_RX_CONTROL_1G_TYPE_CGBAD_EN_BITS 1 9445 #define RX2_RX_CONTROL_1G_TYPE_CGBAD_EN_SHIFT 7 9446 9447 /* RX2 :: Rx_Control_1G_type :: cstretch [06:06] */ 9448 #define RX2_RX_CONTROL_1G_TYPE_CSTRETCH_MASK 0x0040 9449 #define RX2_RX_CONTROL_1G_TYPE_CSTRETCH_ALIGN 0 9450 #define RX2_RX_CONTROL_1G_TYPE_CSTRETCH_BITS 1 9451 #define RX2_RX_CONTROL_1G_TYPE_CSTRETCH_SHIFT 6 9452 9453 /* RX2 :: Rx_Control_1G_type :: rtbi_ckflip [05:05] */ 9454 #define RX2_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_MASK 0x0020 9455 #define RX2_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_ALIGN 0 9456 #define RX2_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_BITS 1 9457 #define RX2_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_SHIFT 5 9458 9459 /* RX2 :: Rx_Control_1G_type :: rtbi_flip [04:04] */ 9460 #define RX2_RX_CONTROL_1G_TYPE_RTBI_FLIP_MASK 0x0010 9461 #define RX2_RX_CONTROL_1G_TYPE_RTBI_FLIP_ALIGN 0 9462 #define RX2_RX_CONTROL_1G_TYPE_RTBI_FLIP_BITS 1 9463 #define RX2_RX_CONTROL_1G_TYPE_RTBI_FLIP_SHIFT 4 9464 9465 /* RX2 :: Rx_Control_1G_type :: phase_sel [03:03] */ 9466 #define RX2_RX_CONTROL_1G_TYPE_PHASE_SEL_MASK 0x0008 9467 #define RX2_RX_CONTROL_1G_TYPE_PHASE_SEL_ALIGN 0 9468 #define RX2_RX_CONTROL_1G_TYPE_PHASE_SEL_BITS 1 9469 #define RX2_RX_CONTROL_1G_TYPE_PHASE_SEL_SHIFT 3 9470 9471 /* RX2 :: Rx_Control_1G_type :: reserved0 [02:02] */ 9472 #define RX2_RX_CONTROL_1G_TYPE_RESERVED0_MASK 0x0004 9473 #define RX2_RX_CONTROL_1G_TYPE_RESERVED0_ALIGN 0 9474 #define RX2_RX_CONTROL_1G_TYPE_RESERVED0_BITS 1 9475 #define RX2_RX_CONTROL_1G_TYPE_RESERVED0_SHIFT 2 9476 9477 /* RX2 :: Rx_Control_1G_type :: freq_sel_force [01:01] */ 9478 #define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_MASK 0x0002 9479 #define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_ALIGN 0 9480 #define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_BITS 1 9481 #define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_SHIFT 1 9482 9483 /* RX2 :: Rx_Control_1G_type :: freq_sel [00:00] */ 9484 #define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_MASK 0x0001 9485 #define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_ALIGN 0 9486 #define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_BITS 1 9487 #define RX2_RX_CONTROL_1G_TYPE_FREQ_SEL_SHIFT 0 9488 9489 9490 /**************************************************************************** 9491 * RX2 :: Rx_Astatus 9492 */ 9493 /* RX2 :: Rx_Astatus :: reserved0 [15:01] */ 9494 #define RX2_RX_ASTATUS_RESERVED0_MASK 0xfffe 9495 #define RX2_RX_ASTATUS_RESERVED0_ALIGN 0 9496 #define RX2_RX_ASTATUS_RESERVED0_BITS 15 9497 #define RX2_RX_ASTATUS_RESERVED0_SHIFT 1 9498 9499 /* RX2 :: Rx_Astatus :: sigdet [00:00] */ 9500 #define RX2_RX_ASTATUS_SIGDET_MASK 0x0001 9501 #define RX2_RX_ASTATUS_SIGDET_ALIGN 0 9502 #define RX2_RX_ASTATUS_SIGDET_BITS 1 9503 #define RX2_RX_ASTATUS_SIGDET_SHIFT 0 9504 9505 9506 /**************************************************************************** 9507 * RX2 :: Rx_analogBias0 9508 */ 9509 /* RX2 :: Rx_analogBias0 :: imode_vcm [15:15] */ 9510 #define RX2_RX_ANALOGBIAS0_IMODE_VCM_MASK 0x8000 9511 #define RX2_RX_ANALOGBIAS0_IMODE_VCM_ALIGN 0 9512 #define RX2_RX_ANALOGBIAS0_IMODE_VCM_BITS 1 9513 #define RX2_RX_ANALOGBIAS0_IMODE_VCM_SHIFT 15 9514 9515 /* RX2 :: Rx_analogBias0 :: imin_vcm [14:14] */ 9516 #define RX2_RX_ANALOGBIAS0_IMIN_VCM_MASK 0x4000 9517 #define RX2_RX_ANALOGBIAS0_IMIN_VCM_ALIGN 0 9518 #define RX2_RX_ANALOGBIAS0_IMIN_VCM_BITS 1 9519 #define RX2_RX_ANALOGBIAS0_IMIN_VCM_SHIFT 14 9520 9521 /* RX2 :: Rx_analogBias0 :: imax_sigdet [13:13] */ 9522 #define RX2_RX_ANALOGBIAS0_IMAX_SIGDET_MASK 0x2000 9523 #define RX2_RX_ANALOGBIAS0_IMAX_SIGDET_ALIGN 0 9524 #define RX2_RX_ANALOGBIAS0_IMAX_SIGDET_BITS 1 9525 #define RX2_RX_ANALOGBIAS0_IMAX_SIGDET_SHIFT 13 9526 9527 /* RX2 :: Rx_analogBias0 :: imode_sigdet [12:12] */ 9528 #define RX2_RX_ANALOGBIAS0_IMODE_SIGDET_MASK 0x1000 9529 #define RX2_RX_ANALOGBIAS0_IMODE_SIGDET_ALIGN 0 9530 #define RX2_RX_ANALOGBIAS0_IMODE_SIGDET_BITS 1 9531 #define RX2_RX_ANALOGBIAS0_IMODE_SIGDET_SHIFT 12 9532 9533 /* RX2 :: Rx_analogBias0 :: imin_sigdet [11:11] */ 9534 #define RX2_RX_ANALOGBIAS0_IMIN_SIGDET_MASK 0x0800 9535 #define RX2_RX_ANALOGBIAS0_IMIN_SIGDET_ALIGN 0 9536 #define RX2_RX_ANALOGBIAS0_IMIN_SIGDET_BITS 1 9537 #define RX2_RX_ANALOGBIAS0_IMIN_SIGDET_SHIFT 11 9538 9539 /* RX2 :: Rx_analogBias0 :: refh_rx [10:10] */ 9540 #define RX2_RX_ANALOGBIAS0_REFH_RX_MASK 0x0400 9541 #define RX2_RX_ANALOGBIAS0_REFH_RX_ALIGN 0 9542 #define RX2_RX_ANALOGBIAS0_REFH_RX_BITS 1 9543 #define RX2_RX_ANALOGBIAS0_REFH_RX_SHIFT 10 9544 9545 /* RX2 :: Rx_analogBias0 :: refl_rx [09:09] */ 9546 #define RX2_RX_ANALOGBIAS0_REFL_RX_MASK 0x0200 9547 #define RX2_RX_ANALOGBIAS0_REFL_RX_ALIGN 0 9548 #define RX2_RX_ANALOGBIAS0_REFL_RX_BITS 1 9549 #define RX2_RX_ANALOGBIAS0_REFL_RX_SHIFT 9 9550 9551 /* RX2 :: Rx_analogBias0 :: tport_en [08:08] */ 9552 #define RX2_RX_ANALOGBIAS0_TPORT_EN_MASK 0x0100 9553 #define RX2_RX_ANALOGBIAS0_TPORT_EN_ALIGN 0 9554 #define RX2_RX_ANALOGBIAS0_TPORT_EN_BITS 1 9555 #define RX2_RX_ANALOGBIAS0_TPORT_EN_SHIFT 8 9556 9557 /* RX2 :: Rx_analogBias0 :: vddr_bg [07:07] */ 9558 #define RX2_RX_ANALOGBIAS0_VDDR_BG_MASK 0x0080 9559 #define RX2_RX_ANALOGBIAS0_VDDR_BG_ALIGN 0 9560 #define RX2_RX_ANALOGBIAS0_VDDR_BG_BITS 1 9561 #define RX2_RX_ANALOGBIAS0_VDDR_BG_SHIFT 7 9562 9563 /* RX2 :: Rx_analogBias0 :: sig_pwrdn [06:06] */ 9564 #define RX2_RX_ANALOGBIAS0_SIG_PWRDN_MASK 0x0040 9565 #define RX2_RX_ANALOGBIAS0_SIG_PWRDN_ALIGN 0 9566 #define RX2_RX_ANALOGBIAS0_SIG_PWRDN_BITS 1 9567 #define RX2_RX_ANALOGBIAS0_SIG_PWRDN_SHIFT 6 9568 9569 /* RX2 :: Rx_analogBias0 :: offset_ctrl [05:03] */ 9570 #define RX2_RX_ANALOGBIAS0_OFFSET_CTRL_MASK 0x0038 9571 #define RX2_RX_ANALOGBIAS0_OFFSET_CTRL_ALIGN 0 9572 #define RX2_RX_ANALOGBIAS0_OFFSET_CTRL_BITS 3 9573 #define RX2_RX_ANALOGBIAS0_OFFSET_CTRL_SHIFT 3 9574 9575 /* RX2 :: Rx_analogBias0 :: offset_sel [02:02] */ 9576 #define RX2_RX_ANALOGBIAS0_OFFSET_SEL_MASK 0x0004 9577 #define RX2_RX_ANALOGBIAS0_OFFSET_SEL_ALIGN 0 9578 #define RX2_RX_ANALOGBIAS0_OFFSET_SEL_BITS 1 9579 #define RX2_RX_ANALOGBIAS0_OFFSET_SEL_SHIFT 2 9580 9581 /* RX2 :: Rx_analogBias0 :: reserved0 [01:00] */ 9582 #define RX2_RX_ANALOGBIAS0_RESERVED0_MASK 0x0003 9583 #define RX2_RX_ANALOGBIAS0_RESERVED0_ALIGN 0 9584 #define RX2_RX_ANALOGBIAS0_RESERVED0_BITS 2 9585 #define RX2_RX_ANALOGBIAS0_RESERVED0_SHIFT 0 9586 9587 9588 /**************************************************************************** 9589 * RX2 :: Rx_analogBias1 9590 */ 9591 /* RX2 :: Rx_analogBias1 :: imax_clkbuf [15:15] */ 9592 #define RX2_RX_ANALOGBIAS1_IMAX_CLKBUF_MASK 0x8000 9593 #define RX2_RX_ANALOGBIAS1_IMAX_CLKBUF_ALIGN 0 9594 #define RX2_RX_ANALOGBIAS1_IMAX_CLKBUF_BITS 1 9595 #define RX2_RX_ANALOGBIAS1_IMAX_CLKBUF_SHIFT 15 9596 9597 /* RX2 :: Rx_analogBias1 :: imode_clkbuf [14:14] */ 9598 #define RX2_RX_ANALOGBIAS1_IMODE_CLKBUF_MASK 0x4000 9599 #define RX2_RX_ANALOGBIAS1_IMODE_CLKBUF_ALIGN 0 9600 #define RX2_RX_ANALOGBIAS1_IMODE_CLKBUF_BITS 1 9601 #define RX2_RX_ANALOGBIAS1_IMODE_CLKBUF_SHIFT 14 9602 9603 /* RX2 :: Rx_analogBias1 :: imin_clkbuf [13:13] */ 9604 #define RX2_RX_ANALOGBIAS1_IMIN_CLKBUF_MASK 0x2000 9605 #define RX2_RX_ANALOGBIAS1_IMIN_CLKBUF_ALIGN 0 9606 #define RX2_RX_ANALOGBIAS1_IMIN_CLKBUF_BITS 1 9607 #define RX2_RX_ANALOGBIAS1_IMIN_CLKBUF_SHIFT 13 9608 9609 /* RX2 :: Rx_analogBias1 :: imax_eqfl [12:12] */ 9610 #define RX2_RX_ANALOGBIAS1_IMAX_EQFL_MASK 0x1000 9611 #define RX2_RX_ANALOGBIAS1_IMAX_EQFL_ALIGN 0 9612 #define RX2_RX_ANALOGBIAS1_IMAX_EQFL_BITS 1 9613 #define RX2_RX_ANALOGBIAS1_IMAX_EQFL_SHIFT 12 9614 9615 /* RX2 :: Rx_analogBias1 :: imode_eqfl [11:11] */ 9616 #define RX2_RX_ANALOGBIAS1_IMODE_EQFL_MASK 0x0800 9617 #define RX2_RX_ANALOGBIAS1_IMODE_EQFL_ALIGN 0 9618 #define RX2_RX_ANALOGBIAS1_IMODE_EQFL_BITS 1 9619 #define RX2_RX_ANALOGBIAS1_IMODE_EQFL_SHIFT 11 9620 9621 /* RX2 :: Rx_analogBias1 :: imin_eqfl [10:10] */ 9622 #define RX2_RX_ANALOGBIAS1_IMIN_EQFL_MASK 0x0400 9623 #define RX2_RX_ANALOGBIAS1_IMIN_EQFL_ALIGN 0 9624 #define RX2_RX_ANALOGBIAS1_IMIN_EQFL_BITS 1 9625 #define RX2_RX_ANALOGBIAS1_IMIN_EQFL_SHIFT 10 9626 9627 /* RX2 :: Rx_analogBias1 :: imax_dfesum [09:09] */ 9628 #define RX2_RX_ANALOGBIAS1_IMAX_DFESUM_MASK 0x0200 9629 #define RX2_RX_ANALOGBIAS1_IMAX_DFESUM_ALIGN 0 9630 #define RX2_RX_ANALOGBIAS1_IMAX_DFESUM_BITS 1 9631 #define RX2_RX_ANALOGBIAS1_IMAX_DFESUM_SHIFT 9 9632 9633 /* RX2 :: Rx_analogBias1 :: imode_dfesum [08:08] */ 9634 #define RX2_RX_ANALOGBIAS1_IMODE_DFESUM_MASK 0x0100 9635 #define RX2_RX_ANALOGBIAS1_IMODE_DFESUM_ALIGN 0 9636 #define RX2_RX_ANALOGBIAS1_IMODE_DFESUM_BITS 1 9637 #define RX2_RX_ANALOGBIAS1_IMODE_DFESUM_SHIFT 8 9638 9639 /* RX2 :: Rx_analogBias1 :: imin_dfesum [07:07] */ 9640 #define RX2_RX_ANALOGBIAS1_IMIN_DFESUM_MASK 0x0080 9641 #define RX2_RX_ANALOGBIAS1_IMIN_DFESUM_ALIGN 0 9642 #define RX2_RX_ANALOGBIAS1_IMIN_DFESUM_BITS 1 9643 #define RX2_RX_ANALOGBIAS1_IMIN_DFESUM_SHIFT 7 9644 9645 /* RX2 :: Rx_analogBias1 :: imax_vga [06:06] */ 9646 #define RX2_RX_ANALOGBIAS1_IMAX_VGA_MASK 0x0040 9647 #define RX2_RX_ANALOGBIAS1_IMAX_VGA_ALIGN 0 9648 #define RX2_RX_ANALOGBIAS1_IMAX_VGA_BITS 1 9649 #define RX2_RX_ANALOGBIAS1_IMAX_VGA_SHIFT 6 9650 9651 /* RX2 :: Rx_analogBias1 :: imode_vga [05:05] */ 9652 #define RX2_RX_ANALOGBIAS1_IMODE_VGA_MASK 0x0020 9653 #define RX2_RX_ANALOGBIAS1_IMODE_VGA_ALIGN 0 9654 #define RX2_RX_ANALOGBIAS1_IMODE_VGA_BITS 1 9655 #define RX2_RX_ANALOGBIAS1_IMODE_VGA_SHIFT 5 9656 9657 /* RX2 :: Rx_analogBias1 :: imin_vga [04:04] */ 9658 #define RX2_RX_ANALOGBIAS1_IMIN_VGA_MASK 0x0010 9659 #define RX2_RX_ANALOGBIAS1_IMIN_VGA_ALIGN 0 9660 #define RX2_RX_ANALOGBIAS1_IMIN_VGA_BITS 1 9661 #define RX2_RX_ANALOGBIAS1_IMIN_VGA_SHIFT 4 9662 9663 /* RX2 :: Rx_analogBias1 :: imax_interp [03:03] */ 9664 #define RX2_RX_ANALOGBIAS1_IMAX_INTERP_MASK 0x0008 9665 #define RX2_RX_ANALOGBIAS1_IMAX_INTERP_ALIGN 0 9666 #define RX2_RX_ANALOGBIAS1_IMAX_INTERP_BITS 1 9667 #define RX2_RX_ANALOGBIAS1_IMAX_INTERP_SHIFT 3 9668 9669 /* RX2 :: Rx_analogBias1 :: imode_interp [02:02] */ 9670 #define RX2_RX_ANALOGBIAS1_IMODE_INTERP_MASK 0x0004 9671 #define RX2_RX_ANALOGBIAS1_IMODE_INTERP_ALIGN 0 9672 #define RX2_RX_ANALOGBIAS1_IMODE_INTERP_BITS 1 9673 #define RX2_RX_ANALOGBIAS1_IMODE_INTERP_SHIFT 2 9674 9675 /* RX2 :: Rx_analogBias1 :: imin_interp [01:01] */ 9676 #define RX2_RX_ANALOGBIAS1_IMIN_INTERP_MASK 0x0002 9677 #define RX2_RX_ANALOGBIAS1_IMIN_INTERP_ALIGN 0 9678 #define RX2_RX_ANALOGBIAS1_IMIN_INTERP_BITS 1 9679 #define RX2_RX_ANALOGBIAS1_IMIN_INTERP_SHIFT 1 9680 9681 /* RX2 :: Rx_analogBias1 :: imax_vcm [00:00] */ 9682 #define RX2_RX_ANALOGBIAS1_IMAX_VCM_MASK 0x0001 9683 #define RX2_RX_ANALOGBIAS1_IMAX_VCM_ALIGN 0 9684 #define RX2_RX_ANALOGBIAS1_IMAX_VCM_BITS 1 9685 #define RX2_RX_ANALOGBIAS1_IMAX_VCM_SHIFT 0 9686 9687 9688 /**************************************************************************** 9689 * RX2 :: Rx_analogBias2 9690 */ 9691 /* RX2 :: Rx_analogBias2 :: en_clk16 [15:15] */ 9692 #define RX2_RX_ANALOGBIAS2_EN_CLK16_MASK 0x8000 9693 #define RX2_RX_ANALOGBIAS2_EN_CLK16_ALIGN 0 9694 #define RX2_RX_ANALOGBIAS2_EN_CLK16_BITS 1 9695 #define RX2_RX_ANALOGBIAS2_EN_CLK16_SHIFT 15 9696 9697 /* RX2 :: Rx_analogBias2 :: pd_ch_p1 [14:14] */ 9698 #define RX2_RX_ANALOGBIAS2_PD_CH_P1_MASK 0x4000 9699 #define RX2_RX_ANALOGBIAS2_PD_CH_P1_ALIGN 0 9700 #define RX2_RX_ANALOGBIAS2_PD_CH_P1_BITS 1 9701 #define RX2_RX_ANALOGBIAS2_PD_CH_P1_SHIFT 14 9702 9703 /* RX2 :: Rx_analogBias2 :: en_vcctrl [13:13] */ 9704 #define RX2_RX_ANALOGBIAS2_EN_VCCTRL_MASK 0x2000 9705 #define RX2_RX_ANALOGBIAS2_EN_VCCTRL_ALIGN 0 9706 #define RX2_RX_ANALOGBIAS2_EN_VCCTRL_BITS 1 9707 #define RX2_RX_ANALOGBIAS2_EN_VCCTRL_SHIFT 13 9708 9709 /* RX2 :: Rx_analogBias2 :: en_dfeclk [12:12] */ 9710 #define RX2_RX_ANALOGBIAS2_EN_DFECLK_MASK 0x1000 9711 #define RX2_RX_ANALOGBIAS2_EN_DFECLK_ALIGN 0 9712 #define RX2_RX_ANALOGBIAS2_EN_DFECLK_BITS 1 9713 #define RX2_RX_ANALOGBIAS2_EN_DFECLK_SHIFT 12 9714 9715 /* RX2 :: Rx_analogBias2 :: en_hgain [11:11] */ 9716 #define RX2_RX_ANALOGBIAS2_EN_HGAIN_MASK 0x0800 9717 #define RX2_RX_ANALOGBIAS2_EN_HGAIN_ALIGN 0 9718 #define RX2_RX_ANALOGBIAS2_EN_HGAIN_BITS 1 9719 #define RX2_RX_ANALOGBIAS2_EN_HGAIN_SHIFT 11 9720 9721 /* RX2 :: Rx_analogBias2 :: en_dfeckpwr [10:10] */ 9722 #define RX2_RX_ANALOGBIAS2_EN_DFECKPWR_MASK 0x0400 9723 #define RX2_RX_ANALOGBIAS2_EN_DFECKPWR_ALIGN 0 9724 #define RX2_RX_ANALOGBIAS2_EN_DFECKPWR_BITS 1 9725 #define RX2_RX_ANALOGBIAS2_EN_DFECKPWR_SHIFT 10 9726 9727 /* RX2 :: Rx_analogBias2 :: offset_pd [09:09] */ 9728 #define RX2_RX_ANALOGBIAS2_OFFSET_PD_MASK 0x0200 9729 #define RX2_RX_ANALOGBIAS2_OFFSET_PD_ALIGN 0 9730 #define RX2_RX_ANALOGBIAS2_OFFSET_PD_BITS 1 9731 #define RX2_RX_ANALOGBIAS2_OFFSET_PD_SHIFT 9 9732 9733 /* RX2 :: Rx_analogBias2 :: imax_dfetap [08:08] */ 9734 #define RX2_RX_ANALOGBIAS2_IMAX_DFETAP_MASK 0x0100 9735 #define RX2_RX_ANALOGBIAS2_IMAX_DFETAP_ALIGN 0 9736 #define RX2_RX_ANALOGBIAS2_IMAX_DFETAP_BITS 1 9737 #define RX2_RX_ANALOGBIAS2_IMAX_DFETAP_SHIFT 8 9738 9739 /* RX2 :: Rx_analogBias2 :: imode_dfetap [07:07] */ 9740 #define RX2_RX_ANALOGBIAS2_IMODE_DFETAP_MASK 0x0080 9741 #define RX2_RX_ANALOGBIAS2_IMODE_DFETAP_ALIGN 0 9742 #define RX2_RX_ANALOGBIAS2_IMODE_DFETAP_BITS 1 9743 #define RX2_RX_ANALOGBIAS2_IMODE_DFETAP_SHIFT 7 9744 9745 /* RX2 :: Rx_analogBias2 :: imin_dfetap [06:06] */ 9746 #define RX2_RX_ANALOGBIAS2_IMIN_DFETAP_MASK 0x0040 9747 #define RX2_RX_ANALOGBIAS2_IMIN_DFETAP_ALIGN 0 9748 #define RX2_RX_ANALOGBIAS2_IMIN_DFETAP_BITS 1 9749 #define RX2_RX_ANALOGBIAS2_IMIN_DFETAP_SHIFT 6 9750 9751 /* RX2 :: Rx_analogBias2 :: imax_slcd2c [05:05] */ 9752 #define RX2_RX_ANALOGBIAS2_IMAX_SLCD2C_MASK 0x0020 9753 #define RX2_RX_ANALOGBIAS2_IMAX_SLCD2C_ALIGN 0 9754 #define RX2_RX_ANALOGBIAS2_IMAX_SLCD2C_BITS 1 9755 #define RX2_RX_ANALOGBIAS2_IMAX_SLCD2C_SHIFT 5 9756 9757 /* RX2 :: Rx_analogBias2 :: imode_slcd2c [04:04] */ 9758 #define RX2_RX_ANALOGBIAS2_IMODE_SLCD2C_MASK 0x0010 9759 #define RX2_RX_ANALOGBIAS2_IMODE_SLCD2C_ALIGN 0 9760 #define RX2_RX_ANALOGBIAS2_IMODE_SLCD2C_BITS 1 9761 #define RX2_RX_ANALOGBIAS2_IMODE_SLCD2C_SHIFT 4 9762 9763 /* RX2 :: Rx_analogBias2 :: imin_slcd2c [03:03] */ 9764 #define RX2_RX_ANALOGBIAS2_IMIN_SLCD2C_MASK 0x0008 9765 #define RX2_RX_ANALOGBIAS2_IMIN_SLCD2C_ALIGN 0 9766 #define RX2_RX_ANALOGBIAS2_IMIN_SLCD2C_BITS 1 9767 #define RX2_RX_ANALOGBIAS2_IMIN_SLCD2C_SHIFT 3 9768 9769 /* RX2 :: Rx_analogBias2 :: imax_dfevref [02:02] */ 9770 #define RX2_RX_ANALOGBIAS2_IMAX_DFEVREF_MASK 0x0004 9771 #define RX2_RX_ANALOGBIAS2_IMAX_DFEVREF_ALIGN 0 9772 #define RX2_RX_ANALOGBIAS2_IMAX_DFEVREF_BITS 1 9773 #define RX2_RX_ANALOGBIAS2_IMAX_DFEVREF_SHIFT 2 9774 9775 /* RX2 :: Rx_analogBias2 :: imode_dfevref [01:01] */ 9776 #define RX2_RX_ANALOGBIAS2_IMODE_DFEVREF_MASK 0x0002 9777 #define RX2_RX_ANALOGBIAS2_IMODE_DFEVREF_ALIGN 0 9778 #define RX2_RX_ANALOGBIAS2_IMODE_DFEVREF_BITS 1 9779 #define RX2_RX_ANALOGBIAS2_IMODE_DFEVREF_SHIFT 1 9780 9781 /* RX2 :: Rx_analogBias2 :: imin_dfevref [00:00] */ 9782 #define RX2_RX_ANALOGBIAS2_IMIN_DFEVREF_MASK 0x0001 9783 #define RX2_RX_ANALOGBIAS2_IMIN_DFEVREF_ALIGN 0 9784 #define RX2_RX_ANALOGBIAS2_IMIN_DFEVREF_BITS 1 9785 #define RX2_RX_ANALOGBIAS2_IMIN_DFEVREF_SHIFT 0 9786 9787 9788 /**************************************************************************** 9789 * XGXS16G_USER_RX3 9790 */ 9791 /**************************************************************************** 9792 * RX3 :: Rx_Status 9793 */ 9794 /* union - case sigdet_Status [15:00] */ 9795 /* RX3 :: Rx_Status :: cx4_sigdet [15:15] */ 9796 #define RX3_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 9797 #define RX3_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 9798 #define RX3_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 9799 #define RX3_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 9800 9801 /* RX3 :: Rx_Status :: reserved0 [14:13] */ 9802 #define RX3_RX_STATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 9803 #define RX3_RX_STATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 9804 #define RX3_RX_STATUS_SIGDET_STATUS_RESERVED0_BITS 2 9805 #define RX3_RX_STATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 9806 9807 /* RX3 :: Rx_Status :: rxSeqDone [12:12] */ 9808 #define RX3_RX_STATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 9809 #define RX3_RX_STATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 9810 #define RX3_RX_STATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 9811 #define RX3_RX_STATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 9812 9813 /* RX3 :: Rx_Status :: rx_sigdet_ll [11:11] */ 9814 #define RX3_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 9815 #define RX3_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 9816 #define RX3_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 9817 #define RX3_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 9818 9819 /* RX3 :: Rx_Status :: cs4_sigdet_ll [10:10] */ 9820 #define RX3_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 9821 #define RX3_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 9822 #define RX3_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 9823 #define RX3_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 9824 9825 /* RX3 :: Rx_Status :: rx_reset [09:09] */ 9826 #define RX3_RX_STATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 9827 #define RX3_RX_STATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 9828 #define RX3_RX_STATUS_SIGDET_STATUS_RX_RESET_BITS 1 9829 #define RX3_RX_STATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 9830 9831 /* RX3 :: Rx_Status :: rx_pwrdn [08:08] */ 9832 #define RX3_RX_STATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 9833 #define RX3_RX_STATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 9834 #define RX3_RX_STATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 9835 #define RX3_RX_STATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 9836 9837 /* RX3 :: Rx_Status :: reserved1 [07:00] */ 9838 #define RX3_RX_STATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 9839 #define RX3_RX_STATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 9840 #define RX3_RX_STATUS_SIGDET_STATUS_RESERVED1_BITS 8 9841 #define RX3_RX_STATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 9842 9843 9844 /* union - case sync_Status [15:00] */ 9845 /* RX3 :: Rx_Status :: reserved0 [15:11] */ 9846 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 9847 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED0_ALIGN 0 9848 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED0_BITS 5 9849 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED0_SHIFT 11 9850 9851 /* RX3 :: Rx_Status :: test_acq_en [10:10] */ 9852 #define RX3_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 9853 #define RX3_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 9854 #define RX3_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 9855 #define RX3_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 9856 9857 /* RX3 :: Rx_Status :: reserved1 [09:09] */ 9858 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 9859 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED1_ALIGN 0 9860 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED1_BITS 1 9861 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED1_SHIFT 9 9862 9863 /* RX3 :: Rx_Status :: rxSeqStart [08:08] */ 9864 #define RX3_RX_STATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 9865 #define RX3_RX_STATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 9866 #define RX3_RX_STATUS_SYNC_STATUS_RXSEQSTART_BITS 1 9867 #define RX3_RX_STATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 9868 9869 /* RX3 :: Rx_Status :: mux_comadj_sync_status [07:07] */ 9870 #define RX3_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 9871 #define RX3_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 9872 #define RX3_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 9873 #define RX3_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 9874 9875 /* RX3 :: Rx_Status :: sync_status [06:06] */ 9876 #define RX3_RX_STATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 9877 #define RX3_RX_STATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 9878 #define RX3_RX_STATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 9879 #define RX3_RX_STATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 9880 9881 /* RX3 :: Rx_Status :: rx_sigdet [05:05] */ 9882 #define RX3_RX_STATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 9883 #define RX3_RX_STATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 9884 #define RX3_RX_STATUS_SYNC_STATUS_RX_SIGDET_BITS 1 9885 #define RX3_RX_STATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 9886 9887 /* RX3 :: Rx_Status :: reserved2 [04:03] */ 9888 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 9889 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED2_ALIGN 0 9890 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED2_BITS 2 9891 #define RX3_RX_STATUS_SYNC_STATUS_RESERVED2_SHIFT 3 9892 9893 /* RX3 :: Rx_Status :: saturate_status [02:02] */ 9894 #define RX3_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 9895 #define RX3_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 9896 #define RX3_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 9897 #define RX3_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 9898 9899 /* RX3 :: Rx_Status :: cx4_sigdet [01:01] */ 9900 #define RX3_RX_STATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 9901 #define RX3_RX_STATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 9902 #define RX3_RX_STATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 9903 #define RX3_RX_STATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 9904 9905 /* RX3 :: Rx_Status :: rxSeqDone [00:00] */ 9906 #define RX3_RX_STATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 9907 #define RX3_RX_STATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 9908 #define RX3_RX_STATUS_SYNC_STATUS_RXSEQDONE_BITS 1 9909 #define RX3_RX_STATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 9910 9911 9912 /* union - case rxTestSel_0 [15:00] */ 9913 /* RX3 :: Rx_Status :: reserved0 [15:10] */ 9914 #define RX3_RX_STATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 9915 #define RX3_RX_STATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 9916 #define RX3_RX_STATUS_RXTESTSEL_0_RESERVED0_BITS 6 9917 #define RX3_RX_STATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 9918 9919 /* RX3 :: Rx_Status :: indck_mode_en [09:09] */ 9920 #define RX3_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 9921 #define RX3_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 9922 #define RX3_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 9923 #define RX3_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 9924 9925 /* RX3 :: Rx_Status :: pci_mode_en [08:08] */ 9926 #define RX3_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 9927 #define RX3_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 9928 #define RX3_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 9929 #define RX3_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 9930 9931 /* RX3 :: Rx_Status :: rx_polarity [07:07] */ 9932 #define RX3_RX_STATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 9933 #define RX3_RX_STATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 9934 #define RX3_RX_STATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 9935 #define RX3_RX_STATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 9936 9937 /* RX3 :: Rx_Status :: rxpol_flip [06:06] */ 9938 #define RX3_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 9939 #define RX3_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 9940 #define RX3_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 9941 #define RX3_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 9942 9943 /* RX3 :: Rx_Status :: comma_mask [05:05] */ 9944 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 9945 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 9946 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 9947 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 9948 9949 /* RX3 :: Rx_Status :: link_en_r [04:04] */ 9950 #define RX3_RX_STATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 9951 #define RX3_RX_STATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 9952 #define RX3_RX_STATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 9953 #define RX3_RX_STATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 9954 9955 /* RX3 :: Rx_Status :: comma_adj_en [03:03] */ 9956 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 9957 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 9958 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 9959 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 9960 9961 /* RX3 :: Rx_Status :: comma_adj_en_ext [02:02] */ 9962 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 9963 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 9964 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 9965 #define RX3_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 9966 9967 /* RX3 :: Rx_Status :: reserved1 [01:00] */ 9968 #define RX3_RX_STATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 9969 #define RX3_RX_STATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 9970 #define RX3_RX_STATUS_RXTESTSEL_0_RESERVED1_BITS 2 9971 #define RX3_RX_STATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 9972 9973 9974 /* union - case rxTestSel_1 [15:00] */ 9975 /* RX3 :: Rx_Status :: reserved0 [15:05] */ 9976 #define RX3_RX_STATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 9977 #define RX3_RX_STATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 9978 #define RX3_RX_STATUS_RXTESTSEL_1_RESERVED0_BITS 11 9979 #define RX3_RX_STATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 9980 9981 /* RX3 :: Rx_Status :: cdrAcqDone_r2 [04:04] */ 9982 #define RX3_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 9983 #define RX3_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 9984 #define RX3_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 9985 #define RX3_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 9986 9987 /* RX3 :: Rx_Status :: freq_sel_PC [03:03] */ 9988 #define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 9989 #define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 9990 #define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 9991 #define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 9992 9993 /* RX3 :: Rx_Status :: freq_sel_SM [02:02] */ 9994 #define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 9995 #define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 9996 #define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 9997 #define RX3_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 9998 9999 /* RX3 :: Rx_Status :: integ_mode_SM [01:00] */ 10000 #define RX3_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 10001 #define RX3_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 10002 #define RX3_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 10003 #define RX3_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 10004 10005 10006 /* union - case scale_Status [15:00] */ 10007 /* RX3 :: Rx_Status :: prop_scale [15:12] */ 10008 #define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 10009 #define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 10010 #define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_BITS 4 10011 #define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 10012 10013 /* RX3 :: Rx_Status :: integ_scale [11:08] */ 10014 #define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 10015 #define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 10016 #define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 10017 #define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 10018 10019 /* RX3 :: Rx_Status :: prop_scale_acq [07:04] */ 10020 #define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 10021 #define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 10022 #define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 10023 #define RX3_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 10024 10025 /* RX3 :: Rx_Status :: integ_scale_acq [03:00] */ 10026 #define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 10027 #define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 10028 #define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 10029 #define RX3_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 10030 10031 10032 /* union - case adc_CdrStatus1 [15:00] */ 10033 /* RX3 :: Rx_Status :: reserved0 [15:07] */ 10034 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 10035 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 10036 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 10037 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 10038 10039 /* RX3 :: Rx_Status :: rxMuxCkSel [06:06] */ 10040 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 10041 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 10042 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 10043 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 10044 10045 /* RX3 :: Rx_Status :: glpbk_combo [05:05] */ 10046 #define RX3_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 10047 #define RX3_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 10048 #define RX3_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 10049 #define RX3_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 10050 10051 /* RX3 :: Rx_Status :: clockSwitchSel [04:04] */ 10052 #define RX3_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 10053 #define RX3_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 10054 #define RX3_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 10055 #define RX3_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 10056 10057 /* RX3 :: Rx_Status :: rxck_tst [03:03] */ 10058 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 10059 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 10060 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 10061 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 10062 10063 /* RX3 :: Rx_Status :: rxck_i [02:02] */ 10064 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 10065 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 10066 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 10067 #define RX3_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 10068 10069 /* RX3 :: Rx_Status :: refclk [01:01] */ 10070 #define RX3_RX_STATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 10071 #define RX3_RX_STATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 10072 #define RX3_RX_STATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 10073 #define RX3_RX_STATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 10074 10075 /* RX3 :: Rx_Status :: pll_bypass [00:00] */ 10076 #define RX3_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 10077 #define RX3_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 10078 #define RX3_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 10079 #define RX3_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 10080 10081 10082 /* union - case adc_CdrStatus2 [15:00] */ 10083 /* RX3 :: Rx_Status :: reserved0 [15:06] */ 10084 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 10085 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 10086 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 10087 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 10088 10089 /* RX3 :: Rx_Status :: rxMuxCkSel [05:05] */ 10090 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 10091 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 10092 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 10093 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 10094 10095 /* RX3 :: Rx_Status :: rxSeqStart [04:04] */ 10096 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 10097 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 10098 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 10099 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 10100 10101 /* RX3 :: Rx_Status :: reserved1 [03:01] */ 10102 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 10103 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 10104 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 10105 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 10106 10107 /* RX3 :: Rx_Status :: rxSeqDone [00:00] */ 10108 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 10109 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 10110 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 10111 #define RX3_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 10112 10113 10114 /* union - case adc_CdrStatus3 [15:00] */ 10115 /* RX3 :: Rx_Status :: reserved0 [15:04] */ 10116 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 10117 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 10118 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 10119 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 10120 10121 /* RX3 :: Rx_Status :: rxSeqStart [03:03] */ 10122 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 10123 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 10124 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 10125 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 10126 10127 /* RX3 :: Rx_Status :: reserved1 [02:01] */ 10128 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 10129 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 10130 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 10131 #define RX3_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 10132 10133 /* RX3 :: Rx_Status :: allow_increment_PC [00:00] */ 10134 #define RX3_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 10135 #define RX3_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 10136 #define RX3_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 10137 #define RX3_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 10138 10139 10140 /* union - case adc_CdrStatus4 [15:00] */ 10141 /* RX3 :: Rx_Status :: reserved0 [15:08] */ 10142 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 10143 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 10144 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 10145 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 10146 10147 /* RX3 :: Rx_Status :: rx_pwrdn [07:07] */ 10148 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 10149 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 10150 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 10151 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 10152 10153 /* RX3 :: Rx_Status :: freq_sel [06:06] */ 10154 #define RX3_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 10155 #define RX3_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 10156 #define RX3_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 10157 #define RX3_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 10158 10159 /* RX3 :: Rx_Status :: pll_lock_rstb [05:05] */ 10160 #define RX3_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 10161 #define RX3_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 10162 #define RX3_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 10163 #define RX3_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 10164 10165 /* RX3 :: Rx_Status :: pwrdn [04:04] */ 10166 #define RX3_RX_STATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 10167 #define RX3_RX_STATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 10168 #define RX3_RX_STATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 10169 #define RX3_RX_STATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 10170 10171 /* RX3 :: Rx_Status :: reserved1 [03:00] */ 10172 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 10173 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 10174 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 10175 #define RX3_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 10176 10177 10178 /* union - case adc_CdrStatus5 [15:00] */ 10179 /* RX3 :: Rx_Status :: reserved0 [15:00] */ 10180 #define RX3_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 10181 #define RX3_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 10182 #define RX3_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 10183 #define RX3_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 10184 10185 10186 /* union - case adc_CdrStatus6 [15:00] */ 10187 /* RX3 :: Rx_Status :: reserved0 [15:05] */ 10188 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 10189 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 10190 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 10191 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 10192 10193 /* RX3 :: Rx_Status :: rx_reset [04:04] */ 10194 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 10195 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 10196 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 10197 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 10198 10199 /* RX3 :: Rx_Status :: rx_pwrdn [03:03] */ 10200 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 10201 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 10202 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 10203 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 10204 10205 /* RX3 :: Rx_Status :: reset_anlg [02:02] */ 10206 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 10207 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 10208 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 10209 #define RX3_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 10210 10211 /* RX3 :: Rx_Status :: pwrdn_rx [01:01] */ 10212 #define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 10213 #define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 10214 #define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 10215 #define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 10216 10217 /* RX3 :: Rx_Status :: pwrdn_pll [00:00] */ 10218 #define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 10219 #define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 10220 #define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 10221 #define RX3_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 10222 10223 10224 /* union - case adc_CdrStatus7e [15:00] */ 10225 /* RX3 :: Rx_Status :: reserved0 [15:05] */ 10226 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 10227 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 10228 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 10229 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 10230 10231 /* RX3 :: Rx_Status :: rxck0_even [04:04] */ 10232 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 10233 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 10234 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 10235 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 10236 10237 /* RX3 :: Rx_Status :: rxck1_even [03:03] */ 10238 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 10239 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 10240 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 10241 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 10242 10243 /* RX3 :: Rx_Status :: comdet_even [02:02] */ 10244 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 10245 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 10246 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 10247 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 10248 10249 /* RX3 :: Rx_Status :: en_cdet_even [01:01] */ 10250 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 10251 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 10252 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 10253 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 10254 10255 /* RX3 :: Rx_Status :: comma_adj_en_even [00:00] */ 10256 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 10257 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 10258 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 10259 #define RX3_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 10260 10261 10262 /* union - case adc_CdrStatus7o [15:00] */ 10263 /* RX3 :: Rx_Status :: reserved0 [15:05] */ 10264 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 10265 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 10266 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 10267 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 10268 10269 /* RX3 :: Rx_Status :: rxck0_odd [04:04] */ 10270 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 10271 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 10272 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 10273 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 10274 10275 /* RX3 :: Rx_Status :: rxck1_odd [03:03] */ 10276 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 10277 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 10278 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 10279 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 10280 10281 /* RX3 :: Rx_Status :: comdet_odd [02:02] */ 10282 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 10283 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 10284 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 10285 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 10286 10287 /* RX3 :: Rx_Status :: en_cdet_odd [01:01] */ 10288 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 10289 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 10290 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 10291 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 10292 10293 /* RX3 :: Rx_Status :: comma_adj_en_odd [00:00] */ 10294 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 10295 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 10296 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 10297 #define RX3_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 10298 10299 10300 /* union - case adc_CdrStatus8 [15:00] */ 10301 /* RX3 :: Rx_Status :: reserved0 [15:01] */ 10302 #define RX3_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 10303 #define RX3_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 10304 #define RX3_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 10305 #define RX3_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 10306 10307 /* RX3 :: Rx_Status :: sigdet [00:00] */ 10308 #define RX3_RX_STATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 10309 #define RX3_RX_STATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 10310 #define RX3_RX_STATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 10311 #define RX3_RX_STATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 10312 10313 10314 /* union - case adc_CdrStatus9 [15:00] */ 10315 /* RX3 :: Rx_Status :: reserved0 [15:00] */ 10316 #define RX3_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 10317 #define RX3_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 10318 #define RX3_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 10319 #define RX3_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 10320 10321 10322 /* union - case adc_CdrStatus10 [15:00] */ 10323 /* RX3 :: Rx_Status :: reserved0 [15:07] */ 10324 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 10325 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 10326 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 10327 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 10328 10329 /* RX3 :: Rx_Status :: prbs_en [06:06] */ 10330 #define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 10331 #define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 10332 #define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 10333 #define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 10334 10335 /* RX3 :: Rx_Status :: rstb_tst [05:05] */ 10336 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 10337 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 10338 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 10339 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 10340 10341 /* RX3 :: Rx_Status :: reserved1 [04:04] */ 10342 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 10343 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 10344 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 10345 #define RX3_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 10346 10347 /* RX3 :: Rx_Status :: prbs_state [03:00] */ 10348 #define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 10349 #define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 10350 #define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 10351 #define RX3_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 10352 10353 10354 /* union - case adc_CdrStatus11 [15:00] */ 10355 /* RX3 :: Rx_Status :: reserved0 [15:00] */ 10356 #define RX3_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 10357 #define RX3_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 10358 #define RX3_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 10359 #define RX3_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 10360 10361 10362 /* union - case adc_CdrStatus12_1 [15:00] */ 10363 /* RX3 :: Rx_Status :: reserved0 [15:06] */ 10364 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 10365 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 10366 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 10367 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 10368 10369 /* RX3 :: Rx_Status :: enable4 [05:05] */ 10370 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 10371 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 10372 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 10373 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 10374 10375 /* RX3 :: Rx_Status :: radr_test [04:00] */ 10376 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 10377 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 10378 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 10379 #define RX3_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 10380 10381 10382 /* union - case adc_CdrStatus12_2 [15:00] */ 10383 /* RX3 :: Rx_Status :: reserved0 [15:05] */ 10384 #define RX3_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 10385 #define RX3_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 10386 #define RX3_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 10387 #define RX3_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 10388 10389 /* RX3 :: Rx_Status :: wadr_test [04:00] */ 10390 #define RX3_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 10391 #define RX3_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 10392 #define RX3_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 10393 #define RX3_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 10394 10395 10396 /* union - case adc_CdrStatus12_3 [15:00] */ 10397 /* RX3 :: Rx_Status :: reserved0 [15:06] */ 10398 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 10399 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 10400 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 10401 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 10402 10403 /* RX3 :: Rx_Status :: rxck_66B_tmux [05:05] */ 10404 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 10405 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 10406 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 10407 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 10408 10409 /* RX3 :: Rx_Status :: rstb_66B [04:04] */ 10410 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 10411 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 10412 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 10413 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 10414 10415 /* RX3 :: Rx_Status :: prstb_66B_mux [03:03] */ 10416 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 10417 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 10418 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 10419 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 10420 10421 /* RX3 :: Rx_Status :: rxck_i66_tmux [02:02] */ 10422 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 10423 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 10424 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 10425 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 10426 10427 /* RX3 :: Rx_Status :: rstb_i66 [01:01] */ 10428 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 10429 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 10430 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 10431 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 10432 10433 /* RX3 :: Rx_Status :: prstb_i66_mux [00:00] */ 10434 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 10435 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 10436 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 10437 #define RX3_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 10438 10439 10440 /* union - case adc_CdrStatus12_4 [15:00] */ 10441 /* RX3 :: Rx_Status :: reserved0 [15:04] */ 10442 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 10443 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 10444 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 10445 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 10446 10447 /* RX3 :: Rx_Status :: rfifo_error_r [03:02] */ 10448 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 10449 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 10450 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 10451 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 10452 10453 /* RX3 :: Rx_Status :: rfifo_unflow [01:01] */ 10454 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 10455 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 10456 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 10457 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 10458 10459 /* RX3 :: Rx_Status :: rfifo_ovflow [00:00] */ 10460 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 10461 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 10462 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 10463 #define RX3_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 10464 10465 10466 /* union - case integ_Status [15:00] */ 10467 /* RX3 :: Rx_Status :: integ_status [15:00] */ 10468 #define RX3_RX_STATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 10469 #define RX3_RX_STATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 10470 #define RX3_RX_STATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 10471 #define RX3_RX_STATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 10472 10473 10474 /* union - case vco_Status [15:00] */ 10475 /* RX3 :: Rx_Status :: vco_status [15:00] */ 10476 #define RX3_RX_STATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 10477 #define RX3_RX_STATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 10478 #define RX3_RX_STATUS_VCO_STATUS_VCO_STATUS_BITS 16 10479 #define RX3_RX_STATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 10480 10481 10482 /* union - case prbs_Status [15:00] */ 10483 /* RX3 :: Rx_Status :: prbs_lock [15:15] */ 10484 #define RX3_RX_STATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 10485 #define RX3_RX_STATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 10486 #define RX3_RX_STATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 10487 #define RX3_RX_STATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 10488 10489 /* RX3 :: Rx_Status :: prbs_stky [14:14] */ 10490 #define RX3_RX_STATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 10491 #define RX3_RX_STATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 10492 #define RX3_RX_STATUS_PRBS_STATUS_PRBS_STKY_BITS 1 10493 #define RX3_RX_STATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 10494 10495 /* RX3 :: Rx_Status :: ptbs_errors [13:00] */ 10496 #define RX3_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_MASK 0x3fff 10497 #define RX3_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN 0 10498 #define RX3_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_BITS 14 10499 #define RX3_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT 0 10500 10501 10502 10503 /**************************************************************************** 10504 * RX3 :: Rx_Control 10505 */ 10506 /* RX3 :: Rx_Control :: reserved0 [15:03] */ 10507 #define RX3_RX_CONTROL_RESERVED0_MASK 0xfff8 10508 #define RX3_RX_CONTROL_RESERVED0_ALIGN 0 10509 #define RX3_RX_CONTROL_RESERVED0_BITS 13 10510 #define RX3_RX_CONTROL_RESERVED0_SHIFT 3 10511 10512 /* RX3 :: Rx_Control :: status_sel [02:00] */ 10513 #define RX3_RX_CONTROL_STATUS_SEL_MASK 0x0007 10514 #define RX3_RX_CONTROL_STATUS_SEL_ALIGN 0 10515 #define RX3_RX_CONTROL_STATUS_SEL_BITS 3 10516 #define RX3_RX_CONTROL_STATUS_SEL_SHIFT 0 10517 #define RX3_RX_CONTROL_STATUS_SEL_sigdetStatus 0 10518 #define RX3_RX_CONTROL_STATUS_SEL_syncStatus 1 10519 #define RX3_RX_CONTROL_STATUS_SEL_rxTestSel 2 10520 #define RX3_RX_CONTROL_STATUS_SEL_scaleStatus 3 10521 #define RX3_RX_CONTROL_STATUS_SEL_adcCdrStatus 4 10522 #define RX3_RX_CONTROL_STATUS_SEL_integStatus 5 10523 #define RX3_RX_CONTROL_STATUS_SEL_vcoStatus 6 10524 #define RX3_RX_CONTROL_STATUS_SEL_prbsStatus 7 10525 10526 10527 /**************************************************************************** 10528 * RX3 :: Rx_Test 10529 */ 10530 /* RX3 :: Rx_Test :: sigdet_mux_SM [15:12] */ 10531 #define RX3_RX_TEST_SIGDET_MUX_SM_MASK 0xf000 10532 #define RX3_RX_TEST_SIGDET_MUX_SM_ALIGN 0 10533 #define RX3_RX_TEST_SIGDET_MUX_SM_BITS 4 10534 #define RX3_RX_TEST_SIGDET_MUX_SM_SHIFT 12 10535 10536 /* RX3 :: Rx_Test :: reserved0 [11:09] */ 10537 #define RX3_RX_TEST_RESERVED0_MASK 0x0e00 10538 #define RX3_RX_TEST_RESERVED0_ALIGN 0 10539 #define RX3_RX_TEST_RESERVED0_BITS 3 10540 #define RX3_RX_TEST_RESERVED0_SHIFT 9 10541 10542 /* RX3 :: Rx_Test :: tpctrl_SM [08:04] */ 10543 #define RX3_RX_TEST_TPCTRL_SM_MASK 0x01f0 10544 #define RX3_RX_TEST_TPCTRL_SM_ALIGN 0 10545 #define RX3_RX_TEST_TPCTRL_SM_BITS 5 10546 #define RX3_RX_TEST_TPCTRL_SM_SHIFT 4 10547 10548 /* RX3 :: Rx_Test :: testMuxSelect_SM [03:00] */ 10549 #define RX3_RX_TEST_TESTMUXSELECT_SM_MASK 0x000f 10550 #define RX3_RX_TEST_TESTMUXSELECT_SM_ALIGN 0 10551 #define RX3_RX_TEST_TESTMUXSELECT_SM_BITS 4 10552 #define RX3_RX_TEST_TESTMUXSELECT_SM_SHIFT 0 10553 10554 10555 /**************************************************************************** 10556 * RX3 :: Rx_Control_1G_type 10557 */ 10558 /* RX3 :: Rx_Control_1G_type :: fpat_md [15:15] */ 10559 #define RX3_RX_CONTROL_1G_TYPE_FPAT_MD_MASK 0x8000 10560 #define RX3_RX_CONTROL_1G_TYPE_FPAT_MD_ALIGN 0 10561 #define RX3_RX_CONTROL_1G_TYPE_FPAT_MD_BITS 1 10562 #define RX3_RX_CONTROL_1G_TYPE_FPAT_MD_SHIFT 15 10563 10564 /* RX3 :: Rx_Control_1G_type :: pkt_count_en [14:14] */ 10565 #define RX3_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_MASK 0x4000 10566 #define RX3_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_ALIGN 0 10567 #define RX3_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_BITS 1 10568 #define RX3_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_SHIFT 14 10569 10570 /* RX3 :: Rx_Control_1G_type :: staMuxRegDis [13:13] */ 10571 #define RX3_RX_CONTROL_1G_TYPE_STAMUXREGDIS_MASK 0x2000 10572 #define RX3_RX_CONTROL_1G_TYPE_STAMUXREGDIS_ALIGN 0 10573 #define RX3_RX_CONTROL_1G_TYPE_STAMUXREGDIS_BITS 1 10574 #define RX3_RX_CONTROL_1G_TYPE_STAMUXREGDIS_SHIFT 13 10575 10576 /* RX3 :: Rx_Control_1G_type :: prbs_clr_dis [12:12] */ 10577 #define RX3_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_MASK 0x1000 10578 #define RX3_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_ALIGN 0 10579 #define RX3_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_BITS 1 10580 #define RX3_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_SHIFT 12 10581 10582 /* RX3 :: Rx_Control_1G_type :: rxd_dec_sel [11:11] */ 10583 #define RX3_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_MASK 0x0800 10584 #define RX3_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_ALIGN 0 10585 #define RX3_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_BITS 1 10586 #define RX3_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_SHIFT 11 10587 10588 /* RX3 :: Rx_Control_1G_type :: cgbad_tst [10:10] */ 10589 #define RX3_RX_CONTROL_1G_TYPE_CGBAD_TST_MASK 0x0400 10590 #define RX3_RX_CONTROL_1G_TYPE_CGBAD_TST_ALIGN 0 10591 #define RX3_RX_CONTROL_1G_TYPE_CGBAD_TST_BITS 1 10592 #define RX3_RX_CONTROL_1G_TYPE_CGBAD_TST_SHIFT 10 10593 10594 /* RX3 :: Rx_Control_1G_type :: Emon_en [09:09] */ 10595 #define RX3_RX_CONTROL_1G_TYPE_EMON_EN_MASK 0x0200 10596 #define RX3_RX_CONTROL_1G_TYPE_EMON_EN_ALIGN 0 10597 #define RX3_RX_CONTROL_1G_TYPE_EMON_EN_BITS 1 10598 #define RX3_RX_CONTROL_1G_TYPE_EMON_EN_SHIFT 9 10599 10600 /* RX3 :: Rx_Control_1G_type :: prbs_en [08:08] */ 10601 #define RX3_RX_CONTROL_1G_TYPE_PRBS_EN_MASK 0x0100 10602 #define RX3_RX_CONTROL_1G_TYPE_PRBS_EN_ALIGN 0 10603 #define RX3_RX_CONTROL_1G_TYPE_PRBS_EN_BITS 1 10604 #define RX3_RX_CONTROL_1G_TYPE_PRBS_EN_SHIFT 8 10605 10606 /* RX3 :: Rx_Control_1G_type :: cgbad_en [07:07] */ 10607 #define RX3_RX_CONTROL_1G_TYPE_CGBAD_EN_MASK 0x0080 10608 #define RX3_RX_CONTROL_1G_TYPE_CGBAD_EN_ALIGN 0 10609 #define RX3_RX_CONTROL_1G_TYPE_CGBAD_EN_BITS 1 10610 #define RX3_RX_CONTROL_1G_TYPE_CGBAD_EN_SHIFT 7 10611 10612 /* RX3 :: Rx_Control_1G_type :: cstretch [06:06] */ 10613 #define RX3_RX_CONTROL_1G_TYPE_CSTRETCH_MASK 0x0040 10614 #define RX3_RX_CONTROL_1G_TYPE_CSTRETCH_ALIGN 0 10615 #define RX3_RX_CONTROL_1G_TYPE_CSTRETCH_BITS 1 10616 #define RX3_RX_CONTROL_1G_TYPE_CSTRETCH_SHIFT 6 10617 10618 /* RX3 :: Rx_Control_1G_type :: rtbi_ckflip [05:05] */ 10619 #define RX3_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_MASK 0x0020 10620 #define RX3_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_ALIGN 0 10621 #define RX3_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_BITS 1 10622 #define RX3_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_SHIFT 5 10623 10624 /* RX3 :: Rx_Control_1G_type :: rtbi_flip [04:04] */ 10625 #define RX3_RX_CONTROL_1G_TYPE_RTBI_FLIP_MASK 0x0010 10626 #define RX3_RX_CONTROL_1G_TYPE_RTBI_FLIP_ALIGN 0 10627 #define RX3_RX_CONTROL_1G_TYPE_RTBI_FLIP_BITS 1 10628 #define RX3_RX_CONTROL_1G_TYPE_RTBI_FLIP_SHIFT 4 10629 10630 /* RX3 :: Rx_Control_1G_type :: phase_sel [03:03] */ 10631 #define RX3_RX_CONTROL_1G_TYPE_PHASE_SEL_MASK 0x0008 10632 #define RX3_RX_CONTROL_1G_TYPE_PHASE_SEL_ALIGN 0 10633 #define RX3_RX_CONTROL_1G_TYPE_PHASE_SEL_BITS 1 10634 #define RX3_RX_CONTROL_1G_TYPE_PHASE_SEL_SHIFT 3 10635 10636 /* RX3 :: Rx_Control_1G_type :: reserved0 [02:02] */ 10637 #define RX3_RX_CONTROL_1G_TYPE_RESERVED0_MASK 0x0004 10638 #define RX3_RX_CONTROL_1G_TYPE_RESERVED0_ALIGN 0 10639 #define RX3_RX_CONTROL_1G_TYPE_RESERVED0_BITS 1 10640 #define RX3_RX_CONTROL_1G_TYPE_RESERVED0_SHIFT 2 10641 10642 /* RX3 :: Rx_Control_1G_type :: freq_sel_force [01:01] */ 10643 #define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_MASK 0x0002 10644 #define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_ALIGN 0 10645 #define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_BITS 1 10646 #define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_SHIFT 1 10647 10648 /* RX3 :: Rx_Control_1G_type :: freq_sel [00:00] */ 10649 #define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_MASK 0x0001 10650 #define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_ALIGN 0 10651 #define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_BITS 1 10652 #define RX3_RX_CONTROL_1G_TYPE_FREQ_SEL_SHIFT 0 10653 10654 10655 /**************************************************************************** 10656 * RX3 :: Rx_Astatus 10657 */ 10658 /* RX3 :: Rx_Astatus :: reserved0 [15:01] */ 10659 #define RX3_RX_ASTATUS_RESERVED0_MASK 0xfffe 10660 #define RX3_RX_ASTATUS_RESERVED0_ALIGN 0 10661 #define RX3_RX_ASTATUS_RESERVED0_BITS 15 10662 #define RX3_RX_ASTATUS_RESERVED0_SHIFT 1 10663 10664 /* RX3 :: Rx_Astatus :: sigdet [00:00] */ 10665 #define RX3_RX_ASTATUS_SIGDET_MASK 0x0001 10666 #define RX3_RX_ASTATUS_SIGDET_ALIGN 0 10667 #define RX3_RX_ASTATUS_SIGDET_BITS 1 10668 #define RX3_RX_ASTATUS_SIGDET_SHIFT 0 10669 10670 10671 /**************************************************************************** 10672 * RX3 :: Rx_analogBias0 10673 */ 10674 /* RX3 :: Rx_analogBias0 :: imode_vcm [15:15] */ 10675 #define RX3_RX_ANALOGBIAS0_IMODE_VCM_MASK 0x8000 10676 #define RX3_RX_ANALOGBIAS0_IMODE_VCM_ALIGN 0 10677 #define RX3_RX_ANALOGBIAS0_IMODE_VCM_BITS 1 10678 #define RX3_RX_ANALOGBIAS0_IMODE_VCM_SHIFT 15 10679 10680 /* RX3 :: Rx_analogBias0 :: imin_vcm [14:14] */ 10681 #define RX3_RX_ANALOGBIAS0_IMIN_VCM_MASK 0x4000 10682 #define RX3_RX_ANALOGBIAS0_IMIN_VCM_ALIGN 0 10683 #define RX3_RX_ANALOGBIAS0_IMIN_VCM_BITS 1 10684 #define RX3_RX_ANALOGBIAS0_IMIN_VCM_SHIFT 14 10685 10686 /* RX3 :: Rx_analogBias0 :: imax_sigdet [13:13] */ 10687 #define RX3_RX_ANALOGBIAS0_IMAX_SIGDET_MASK 0x2000 10688 #define RX3_RX_ANALOGBIAS0_IMAX_SIGDET_ALIGN 0 10689 #define RX3_RX_ANALOGBIAS0_IMAX_SIGDET_BITS 1 10690 #define RX3_RX_ANALOGBIAS0_IMAX_SIGDET_SHIFT 13 10691 10692 /* RX3 :: Rx_analogBias0 :: imode_sigdet [12:12] */ 10693 #define RX3_RX_ANALOGBIAS0_IMODE_SIGDET_MASK 0x1000 10694 #define RX3_RX_ANALOGBIAS0_IMODE_SIGDET_ALIGN 0 10695 #define RX3_RX_ANALOGBIAS0_IMODE_SIGDET_BITS 1 10696 #define RX3_RX_ANALOGBIAS0_IMODE_SIGDET_SHIFT 12 10697 10698 /* RX3 :: Rx_analogBias0 :: imin_sigdet [11:11] */ 10699 #define RX3_RX_ANALOGBIAS0_IMIN_SIGDET_MASK 0x0800 10700 #define RX3_RX_ANALOGBIAS0_IMIN_SIGDET_ALIGN 0 10701 #define RX3_RX_ANALOGBIAS0_IMIN_SIGDET_BITS 1 10702 #define RX3_RX_ANALOGBIAS0_IMIN_SIGDET_SHIFT 11 10703 10704 /* RX3 :: Rx_analogBias0 :: refh_rx [10:10] */ 10705 #define RX3_RX_ANALOGBIAS0_REFH_RX_MASK 0x0400 10706 #define RX3_RX_ANALOGBIAS0_REFH_RX_ALIGN 0 10707 #define RX3_RX_ANALOGBIAS0_REFH_RX_BITS 1 10708 #define RX3_RX_ANALOGBIAS0_REFH_RX_SHIFT 10 10709 10710 /* RX3 :: Rx_analogBias0 :: refl_rx [09:09] */ 10711 #define RX3_RX_ANALOGBIAS0_REFL_RX_MASK 0x0200 10712 #define RX3_RX_ANALOGBIAS0_REFL_RX_ALIGN 0 10713 #define RX3_RX_ANALOGBIAS0_REFL_RX_BITS 1 10714 #define RX3_RX_ANALOGBIAS0_REFL_RX_SHIFT 9 10715 10716 /* RX3 :: Rx_analogBias0 :: tport_en [08:08] */ 10717 #define RX3_RX_ANALOGBIAS0_TPORT_EN_MASK 0x0100 10718 #define RX3_RX_ANALOGBIAS0_TPORT_EN_ALIGN 0 10719 #define RX3_RX_ANALOGBIAS0_TPORT_EN_BITS 1 10720 #define RX3_RX_ANALOGBIAS0_TPORT_EN_SHIFT 8 10721 10722 /* RX3 :: Rx_analogBias0 :: vddr_bg [07:07] */ 10723 #define RX3_RX_ANALOGBIAS0_VDDR_BG_MASK 0x0080 10724 #define RX3_RX_ANALOGBIAS0_VDDR_BG_ALIGN 0 10725 #define RX3_RX_ANALOGBIAS0_VDDR_BG_BITS 1 10726 #define RX3_RX_ANALOGBIAS0_VDDR_BG_SHIFT 7 10727 10728 /* RX3 :: Rx_analogBias0 :: sig_pwrdn [06:06] */ 10729 #define RX3_RX_ANALOGBIAS0_SIG_PWRDN_MASK 0x0040 10730 #define RX3_RX_ANALOGBIAS0_SIG_PWRDN_ALIGN 0 10731 #define RX3_RX_ANALOGBIAS0_SIG_PWRDN_BITS 1 10732 #define RX3_RX_ANALOGBIAS0_SIG_PWRDN_SHIFT 6 10733 10734 /* RX3 :: Rx_analogBias0 :: offset_ctrl [05:03] */ 10735 #define RX3_RX_ANALOGBIAS0_OFFSET_CTRL_MASK 0x0038 10736 #define RX3_RX_ANALOGBIAS0_OFFSET_CTRL_ALIGN 0 10737 #define RX3_RX_ANALOGBIAS0_OFFSET_CTRL_BITS 3 10738 #define RX3_RX_ANALOGBIAS0_OFFSET_CTRL_SHIFT 3 10739 10740 /* RX3 :: Rx_analogBias0 :: offset_sel [02:02] */ 10741 #define RX3_RX_ANALOGBIAS0_OFFSET_SEL_MASK 0x0004 10742 #define RX3_RX_ANALOGBIAS0_OFFSET_SEL_ALIGN 0 10743 #define RX3_RX_ANALOGBIAS0_OFFSET_SEL_BITS 1 10744 #define RX3_RX_ANALOGBIAS0_OFFSET_SEL_SHIFT 2 10745 10746 /* RX3 :: Rx_analogBias0 :: reserved0 [01:00] */ 10747 #define RX3_RX_ANALOGBIAS0_RESERVED0_MASK 0x0003 10748 #define RX3_RX_ANALOGBIAS0_RESERVED0_ALIGN 0 10749 #define RX3_RX_ANALOGBIAS0_RESERVED0_BITS 2 10750 #define RX3_RX_ANALOGBIAS0_RESERVED0_SHIFT 0 10751 10752 10753 /**************************************************************************** 10754 * RX3 :: Rx_analogBias1 10755 */ 10756 /* RX3 :: Rx_analogBias1 :: imax_clkbuf [15:15] */ 10757 #define RX3_RX_ANALOGBIAS1_IMAX_CLKBUF_MASK 0x8000 10758 #define RX3_RX_ANALOGBIAS1_IMAX_CLKBUF_ALIGN 0 10759 #define RX3_RX_ANALOGBIAS1_IMAX_CLKBUF_BITS 1 10760 #define RX3_RX_ANALOGBIAS1_IMAX_CLKBUF_SHIFT 15 10761 10762 /* RX3 :: Rx_analogBias1 :: imode_clkbuf [14:14] */ 10763 #define RX3_RX_ANALOGBIAS1_IMODE_CLKBUF_MASK 0x4000 10764 #define RX3_RX_ANALOGBIAS1_IMODE_CLKBUF_ALIGN 0 10765 #define RX3_RX_ANALOGBIAS1_IMODE_CLKBUF_BITS 1 10766 #define RX3_RX_ANALOGBIAS1_IMODE_CLKBUF_SHIFT 14 10767 10768 /* RX3 :: Rx_analogBias1 :: imin_clkbuf [13:13] */ 10769 #define RX3_RX_ANALOGBIAS1_IMIN_CLKBUF_MASK 0x2000 10770 #define RX3_RX_ANALOGBIAS1_IMIN_CLKBUF_ALIGN 0 10771 #define RX3_RX_ANALOGBIAS1_IMIN_CLKBUF_BITS 1 10772 #define RX3_RX_ANALOGBIAS1_IMIN_CLKBUF_SHIFT 13 10773 10774 /* RX3 :: Rx_analogBias1 :: imax_eqfl [12:12] */ 10775 #define RX3_RX_ANALOGBIAS1_IMAX_EQFL_MASK 0x1000 10776 #define RX3_RX_ANALOGBIAS1_IMAX_EQFL_ALIGN 0 10777 #define RX3_RX_ANALOGBIAS1_IMAX_EQFL_BITS 1 10778 #define RX3_RX_ANALOGBIAS1_IMAX_EQFL_SHIFT 12 10779 10780 /* RX3 :: Rx_analogBias1 :: imode_eqfl [11:11] */ 10781 #define RX3_RX_ANALOGBIAS1_IMODE_EQFL_MASK 0x0800 10782 #define RX3_RX_ANALOGBIAS1_IMODE_EQFL_ALIGN 0 10783 #define RX3_RX_ANALOGBIAS1_IMODE_EQFL_BITS 1 10784 #define RX3_RX_ANALOGBIAS1_IMODE_EQFL_SHIFT 11 10785 10786 /* RX3 :: Rx_analogBias1 :: imin_eqfl [10:10] */ 10787 #define RX3_RX_ANALOGBIAS1_IMIN_EQFL_MASK 0x0400 10788 #define RX3_RX_ANALOGBIAS1_IMIN_EQFL_ALIGN 0 10789 #define RX3_RX_ANALOGBIAS1_IMIN_EQFL_BITS 1 10790 #define RX3_RX_ANALOGBIAS1_IMIN_EQFL_SHIFT 10 10791 10792 /* RX3 :: Rx_analogBias1 :: imax_dfesum [09:09] */ 10793 #define RX3_RX_ANALOGBIAS1_IMAX_DFESUM_MASK 0x0200 10794 #define RX3_RX_ANALOGBIAS1_IMAX_DFESUM_ALIGN 0 10795 #define RX3_RX_ANALOGBIAS1_IMAX_DFESUM_BITS 1 10796 #define RX3_RX_ANALOGBIAS1_IMAX_DFESUM_SHIFT 9 10797 10798 /* RX3 :: Rx_analogBias1 :: imode_dfesum [08:08] */ 10799 #define RX3_RX_ANALOGBIAS1_IMODE_DFESUM_MASK 0x0100 10800 #define RX3_RX_ANALOGBIAS1_IMODE_DFESUM_ALIGN 0 10801 #define RX3_RX_ANALOGBIAS1_IMODE_DFESUM_BITS 1 10802 #define RX3_RX_ANALOGBIAS1_IMODE_DFESUM_SHIFT 8 10803 10804 /* RX3 :: Rx_analogBias1 :: imin_dfesum [07:07] */ 10805 #define RX3_RX_ANALOGBIAS1_IMIN_DFESUM_MASK 0x0080 10806 #define RX3_RX_ANALOGBIAS1_IMIN_DFESUM_ALIGN 0 10807 #define RX3_RX_ANALOGBIAS1_IMIN_DFESUM_BITS 1 10808 #define RX3_RX_ANALOGBIAS1_IMIN_DFESUM_SHIFT 7 10809 10810 /* RX3 :: Rx_analogBias1 :: imax_vga [06:06] */ 10811 #define RX3_RX_ANALOGBIAS1_IMAX_VGA_MASK 0x0040 10812 #define RX3_RX_ANALOGBIAS1_IMAX_VGA_ALIGN 0 10813 #define RX3_RX_ANALOGBIAS1_IMAX_VGA_BITS 1 10814 #define RX3_RX_ANALOGBIAS1_IMAX_VGA_SHIFT 6 10815 10816 /* RX3 :: Rx_analogBias1 :: imode_vga [05:05] */ 10817 #define RX3_RX_ANALOGBIAS1_IMODE_VGA_MASK 0x0020 10818 #define RX3_RX_ANALOGBIAS1_IMODE_VGA_ALIGN 0 10819 #define RX3_RX_ANALOGBIAS1_IMODE_VGA_BITS 1 10820 #define RX3_RX_ANALOGBIAS1_IMODE_VGA_SHIFT 5 10821 10822 /* RX3 :: Rx_analogBias1 :: imin_vga [04:04] */ 10823 #define RX3_RX_ANALOGBIAS1_IMIN_VGA_MASK 0x0010 10824 #define RX3_RX_ANALOGBIAS1_IMIN_VGA_ALIGN 0 10825 #define RX3_RX_ANALOGBIAS1_IMIN_VGA_BITS 1 10826 #define RX3_RX_ANALOGBIAS1_IMIN_VGA_SHIFT 4 10827 10828 /* RX3 :: Rx_analogBias1 :: imax_interp [03:03] */ 10829 #define RX3_RX_ANALOGBIAS1_IMAX_INTERP_MASK 0x0008 10830 #define RX3_RX_ANALOGBIAS1_IMAX_INTERP_ALIGN 0 10831 #define RX3_RX_ANALOGBIAS1_IMAX_INTERP_BITS 1 10832 #define RX3_RX_ANALOGBIAS1_IMAX_INTERP_SHIFT 3 10833 10834 /* RX3 :: Rx_analogBias1 :: imode_interp [02:02] */ 10835 #define RX3_RX_ANALOGBIAS1_IMODE_INTERP_MASK 0x0004 10836 #define RX3_RX_ANALOGBIAS1_IMODE_INTERP_ALIGN 0 10837 #define RX3_RX_ANALOGBIAS1_IMODE_INTERP_BITS 1 10838 #define RX3_RX_ANALOGBIAS1_IMODE_INTERP_SHIFT 2 10839 10840 /* RX3 :: Rx_analogBias1 :: imin_interp [01:01] */ 10841 #define RX3_RX_ANALOGBIAS1_IMIN_INTERP_MASK 0x0002 10842 #define RX3_RX_ANALOGBIAS1_IMIN_INTERP_ALIGN 0 10843 #define RX3_RX_ANALOGBIAS1_IMIN_INTERP_BITS 1 10844 #define RX3_RX_ANALOGBIAS1_IMIN_INTERP_SHIFT 1 10845 10846 /* RX3 :: Rx_analogBias1 :: imax_vcm [00:00] */ 10847 #define RX3_RX_ANALOGBIAS1_IMAX_VCM_MASK 0x0001 10848 #define RX3_RX_ANALOGBIAS1_IMAX_VCM_ALIGN 0 10849 #define RX3_RX_ANALOGBIAS1_IMAX_VCM_BITS 1 10850 #define RX3_RX_ANALOGBIAS1_IMAX_VCM_SHIFT 0 10851 10852 10853 /**************************************************************************** 10854 * RX3 :: Rx_analogBias2 10855 */ 10856 /* RX3 :: Rx_analogBias2 :: en_clk16 [15:15] */ 10857 #define RX3_RX_ANALOGBIAS2_EN_CLK16_MASK 0x8000 10858 #define RX3_RX_ANALOGBIAS2_EN_CLK16_ALIGN 0 10859 #define RX3_RX_ANALOGBIAS2_EN_CLK16_BITS 1 10860 #define RX3_RX_ANALOGBIAS2_EN_CLK16_SHIFT 15 10861 10862 /* RX3 :: Rx_analogBias2 :: pd_ch_p1 [14:14] */ 10863 #define RX3_RX_ANALOGBIAS2_PD_CH_P1_MASK 0x4000 10864 #define RX3_RX_ANALOGBIAS2_PD_CH_P1_ALIGN 0 10865 #define RX3_RX_ANALOGBIAS2_PD_CH_P1_BITS 1 10866 #define RX3_RX_ANALOGBIAS2_PD_CH_P1_SHIFT 14 10867 10868 /* RX3 :: Rx_analogBias2 :: en_vcctrl [13:13] */ 10869 #define RX3_RX_ANALOGBIAS2_EN_VCCTRL_MASK 0x2000 10870 #define RX3_RX_ANALOGBIAS2_EN_VCCTRL_ALIGN 0 10871 #define RX3_RX_ANALOGBIAS2_EN_VCCTRL_BITS 1 10872 #define RX3_RX_ANALOGBIAS2_EN_VCCTRL_SHIFT 13 10873 10874 /* RX3 :: Rx_analogBias2 :: en_dfeclk [12:12] */ 10875 #define RX3_RX_ANALOGBIAS2_EN_DFECLK_MASK 0x1000 10876 #define RX3_RX_ANALOGBIAS2_EN_DFECLK_ALIGN 0 10877 #define RX3_RX_ANALOGBIAS2_EN_DFECLK_BITS 1 10878 #define RX3_RX_ANALOGBIAS2_EN_DFECLK_SHIFT 12 10879 10880 /* RX3 :: Rx_analogBias2 :: en_hgain [11:11] */ 10881 #define RX3_RX_ANALOGBIAS2_EN_HGAIN_MASK 0x0800 10882 #define RX3_RX_ANALOGBIAS2_EN_HGAIN_ALIGN 0 10883 #define RX3_RX_ANALOGBIAS2_EN_HGAIN_BITS 1 10884 #define RX3_RX_ANALOGBIAS2_EN_HGAIN_SHIFT 11 10885 10886 /* RX3 :: Rx_analogBias2 :: en_dfeckpwr [10:10] */ 10887 #define RX3_RX_ANALOGBIAS2_EN_DFECKPWR_MASK 0x0400 10888 #define RX3_RX_ANALOGBIAS2_EN_DFECKPWR_ALIGN 0 10889 #define RX3_RX_ANALOGBIAS2_EN_DFECKPWR_BITS 1 10890 #define RX3_RX_ANALOGBIAS2_EN_DFECKPWR_SHIFT 10 10891 10892 /* RX3 :: Rx_analogBias2 :: offset_pd [09:09] */ 10893 #define RX3_RX_ANALOGBIAS2_OFFSET_PD_MASK 0x0200 10894 #define RX3_RX_ANALOGBIAS2_OFFSET_PD_ALIGN 0 10895 #define RX3_RX_ANALOGBIAS2_OFFSET_PD_BITS 1 10896 #define RX3_RX_ANALOGBIAS2_OFFSET_PD_SHIFT 9 10897 10898 /* RX3 :: Rx_analogBias2 :: imax_dfetap [08:08] */ 10899 #define RX3_RX_ANALOGBIAS2_IMAX_DFETAP_MASK 0x0100 10900 #define RX3_RX_ANALOGBIAS2_IMAX_DFETAP_ALIGN 0 10901 #define RX3_RX_ANALOGBIAS2_IMAX_DFETAP_BITS 1 10902 #define RX3_RX_ANALOGBIAS2_IMAX_DFETAP_SHIFT 8 10903 10904 /* RX3 :: Rx_analogBias2 :: imode_dfetap [07:07] */ 10905 #define RX3_RX_ANALOGBIAS2_IMODE_DFETAP_MASK 0x0080 10906 #define RX3_RX_ANALOGBIAS2_IMODE_DFETAP_ALIGN 0 10907 #define RX3_RX_ANALOGBIAS2_IMODE_DFETAP_BITS 1 10908 #define RX3_RX_ANALOGBIAS2_IMODE_DFETAP_SHIFT 7 10909 10910 /* RX3 :: Rx_analogBias2 :: imin_dfetap [06:06] */ 10911 #define RX3_RX_ANALOGBIAS2_IMIN_DFETAP_MASK 0x0040 10912 #define RX3_RX_ANALOGBIAS2_IMIN_DFETAP_ALIGN 0 10913 #define RX3_RX_ANALOGBIAS2_IMIN_DFETAP_BITS 1 10914 #define RX3_RX_ANALOGBIAS2_IMIN_DFETAP_SHIFT 6 10915 10916 /* RX3 :: Rx_analogBias2 :: imax_slcd2c [05:05] */ 10917 #define RX3_RX_ANALOGBIAS2_IMAX_SLCD2C_MASK 0x0020 10918 #define RX3_RX_ANALOGBIAS2_IMAX_SLCD2C_ALIGN 0 10919 #define RX3_RX_ANALOGBIAS2_IMAX_SLCD2C_BITS 1 10920 #define RX3_RX_ANALOGBIAS2_IMAX_SLCD2C_SHIFT 5 10921 10922 /* RX3 :: Rx_analogBias2 :: imode_slcd2c [04:04] */ 10923 #define RX3_RX_ANALOGBIAS2_IMODE_SLCD2C_MASK 0x0010 10924 #define RX3_RX_ANALOGBIAS2_IMODE_SLCD2C_ALIGN 0 10925 #define RX3_RX_ANALOGBIAS2_IMODE_SLCD2C_BITS 1 10926 #define RX3_RX_ANALOGBIAS2_IMODE_SLCD2C_SHIFT 4 10927 10928 /* RX3 :: Rx_analogBias2 :: imin_slcd2c [03:03] */ 10929 #define RX3_RX_ANALOGBIAS2_IMIN_SLCD2C_MASK 0x0008 10930 #define RX3_RX_ANALOGBIAS2_IMIN_SLCD2C_ALIGN 0 10931 #define RX3_RX_ANALOGBIAS2_IMIN_SLCD2C_BITS 1 10932 #define RX3_RX_ANALOGBIAS2_IMIN_SLCD2C_SHIFT 3 10933 10934 /* RX3 :: Rx_analogBias2 :: imax_dfevref [02:02] */ 10935 #define RX3_RX_ANALOGBIAS2_IMAX_DFEVREF_MASK 0x0004 10936 #define RX3_RX_ANALOGBIAS2_IMAX_DFEVREF_ALIGN 0 10937 #define RX3_RX_ANALOGBIAS2_IMAX_DFEVREF_BITS 1 10938 #define RX3_RX_ANALOGBIAS2_IMAX_DFEVREF_SHIFT 2 10939 10940 /* RX3 :: Rx_analogBias2 :: imode_dfevref [01:01] */ 10941 #define RX3_RX_ANALOGBIAS2_IMODE_DFEVREF_MASK 0x0002 10942 #define RX3_RX_ANALOGBIAS2_IMODE_DFEVREF_ALIGN 0 10943 #define RX3_RX_ANALOGBIAS2_IMODE_DFEVREF_BITS 1 10944 #define RX3_RX_ANALOGBIAS2_IMODE_DFEVREF_SHIFT 1 10945 10946 /* RX3 :: Rx_analogBias2 :: imin_dfevref [00:00] */ 10947 #define RX3_RX_ANALOGBIAS2_IMIN_DFEVREF_MASK 0x0001 10948 #define RX3_RX_ANALOGBIAS2_IMIN_DFEVREF_ALIGN 0 10949 #define RX3_RX_ANALOGBIAS2_IMIN_DFEVREF_BITS 1 10950 #define RX3_RX_ANALOGBIAS2_IMIN_DFEVREF_SHIFT 0 10951 10952 10953 /**************************************************************************** 10954 * XGXS16G_USER_RX_All 10955 */ 10956 /**************************************************************************** 10957 * RX_All :: Rx_Status 10958 */ 10959 /* union - case sigdet_Status [15:00] */ 10960 /* RX_All :: Rx_Status :: cx4_sigdet [15:15] */ 10961 #define RX_ALL_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 10962 #define RX_ALL_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 10963 #define RX_ALL_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 10964 #define RX_ALL_RX_STATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 10965 10966 /* RX_All :: Rx_Status :: reserved0 [14:13] */ 10967 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 10968 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 10969 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED0_BITS 2 10970 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 10971 10972 /* RX_All :: Rx_Status :: rxSeqDone [12:12] */ 10973 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 10974 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 10975 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 10976 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 10977 10978 /* RX_All :: Rx_Status :: rx_sigdet_ll [11:11] */ 10979 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 10980 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 10981 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 10982 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 10983 10984 /* RX_All :: Rx_Status :: cs4_sigdet_ll [10:10] */ 10985 #define RX_ALL_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 10986 #define RX_ALL_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 10987 #define RX_ALL_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 10988 #define RX_ALL_RX_STATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 10989 10990 /* RX_All :: Rx_Status :: rx_reset [09:09] */ 10991 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 10992 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 10993 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_RESET_BITS 1 10994 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 10995 10996 /* RX_All :: Rx_Status :: rx_pwrdn [08:08] */ 10997 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 10998 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 10999 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 11000 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 11001 11002 /* RX_All :: Rx_Status :: reserved1 [07:00] */ 11003 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 11004 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 11005 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED1_BITS 8 11006 #define RX_ALL_RX_STATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 11007 11008 11009 /* union - case sync_Status [15:00] */ 11010 /* RX_All :: Rx_Status :: reserved0 [15:11] */ 11011 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 11012 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED0_ALIGN 0 11013 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED0_BITS 5 11014 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED0_SHIFT 11 11015 11016 /* RX_All :: Rx_Status :: test_acq_en [10:10] */ 11017 #define RX_ALL_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 11018 #define RX_ALL_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 11019 #define RX_ALL_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 11020 #define RX_ALL_RX_STATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 11021 11022 /* RX_All :: Rx_Status :: reserved1 [09:09] */ 11023 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 11024 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED1_ALIGN 0 11025 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED1_BITS 1 11026 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED1_SHIFT 9 11027 11028 /* RX_All :: Rx_Status :: rxSeqStart [08:08] */ 11029 #define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 11030 #define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 11031 #define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQSTART_BITS 1 11032 #define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 11033 11034 /* RX_All :: Rx_Status :: mux_comadj_sync_status [07:07] */ 11035 #define RX_ALL_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 11036 #define RX_ALL_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 11037 #define RX_ALL_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 11038 #define RX_ALL_RX_STATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 11039 11040 /* RX_All :: Rx_Status :: sync_status [06:06] */ 11041 #define RX_ALL_RX_STATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 11042 #define RX_ALL_RX_STATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 11043 #define RX_ALL_RX_STATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 11044 #define RX_ALL_RX_STATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 11045 11046 /* RX_All :: Rx_Status :: rx_sigdet [05:05] */ 11047 #define RX_ALL_RX_STATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 11048 #define RX_ALL_RX_STATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 11049 #define RX_ALL_RX_STATUS_SYNC_STATUS_RX_SIGDET_BITS 1 11050 #define RX_ALL_RX_STATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 11051 11052 /* RX_All :: Rx_Status :: reserved2 [04:03] */ 11053 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 11054 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED2_ALIGN 0 11055 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED2_BITS 2 11056 #define RX_ALL_RX_STATUS_SYNC_STATUS_RESERVED2_SHIFT 3 11057 11058 /* RX_All :: Rx_Status :: saturate_status [02:02] */ 11059 #define RX_ALL_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 11060 #define RX_ALL_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 11061 #define RX_ALL_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 11062 #define RX_ALL_RX_STATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 11063 11064 /* RX_All :: Rx_Status :: cx4_sigdet [01:01] */ 11065 #define RX_ALL_RX_STATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 11066 #define RX_ALL_RX_STATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 11067 #define RX_ALL_RX_STATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 11068 #define RX_ALL_RX_STATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 11069 11070 /* RX_All :: Rx_Status :: rxSeqDone [00:00] */ 11071 #define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 11072 #define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 11073 #define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQDONE_BITS 1 11074 #define RX_ALL_RX_STATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 11075 11076 11077 /* union - case rxTestSel_0 [15:00] */ 11078 /* RX_All :: Rx_Status :: reserved0 [15:10] */ 11079 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 11080 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 11081 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED0_BITS 6 11082 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 11083 11084 /* RX_All :: Rx_Status :: indck_mode_en [09:09] */ 11085 #define RX_ALL_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 11086 #define RX_ALL_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 11087 #define RX_ALL_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 11088 #define RX_ALL_RX_STATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 11089 11090 /* RX_All :: Rx_Status :: pci_mode_en [08:08] */ 11091 #define RX_ALL_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 11092 #define RX_ALL_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 11093 #define RX_ALL_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 11094 #define RX_ALL_RX_STATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 11095 11096 /* RX_All :: Rx_Status :: rx_polarity [07:07] */ 11097 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 11098 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 11099 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 11100 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 11101 11102 /* RX_All :: Rx_Status :: rxpol_flip [06:06] */ 11103 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 11104 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 11105 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 11106 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 11107 11108 /* RX_All :: Rx_Status :: comma_mask [05:05] */ 11109 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 11110 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 11111 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 11112 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 11113 11114 /* RX_All :: Rx_Status :: link_en_r [04:04] */ 11115 #define RX_ALL_RX_STATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 11116 #define RX_ALL_RX_STATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 11117 #define RX_ALL_RX_STATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 11118 #define RX_ALL_RX_STATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 11119 11120 /* RX_All :: Rx_Status :: comma_adj_en [03:03] */ 11121 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 11122 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 11123 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 11124 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 11125 11126 /* RX_All :: Rx_Status :: comma_adj_en_ext [02:02] */ 11127 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 11128 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 11129 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 11130 #define RX_ALL_RX_STATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 11131 11132 /* RX_All :: Rx_Status :: reserved1 [01:00] */ 11133 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 11134 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 11135 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED1_BITS 2 11136 #define RX_ALL_RX_STATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 11137 11138 11139 /* union - case rxTestSel_1 [15:00] */ 11140 /* RX_All :: Rx_Status :: reserved0 [15:05] */ 11141 #define RX_ALL_RX_STATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 11142 #define RX_ALL_RX_STATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 11143 #define RX_ALL_RX_STATUS_RXTESTSEL_1_RESERVED0_BITS 11 11144 #define RX_ALL_RX_STATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 11145 11146 /* RX_All :: Rx_Status :: cdrAcqDone_r2 [04:04] */ 11147 #define RX_ALL_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 11148 #define RX_ALL_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 11149 #define RX_ALL_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 11150 #define RX_ALL_RX_STATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 11151 11152 /* RX_All :: Rx_Status :: freq_sel_PC [03:03] */ 11153 #define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 11154 #define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 11155 #define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 11156 #define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 11157 11158 /* RX_All :: Rx_Status :: freq_sel_SM [02:02] */ 11159 #define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 11160 #define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 11161 #define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 11162 #define RX_ALL_RX_STATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 11163 11164 /* RX_All :: Rx_Status :: integ_mode_SM [01:00] */ 11165 #define RX_ALL_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 11166 #define RX_ALL_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 11167 #define RX_ALL_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 11168 #define RX_ALL_RX_STATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 11169 11170 11171 /* union - case scale_Status [15:00] */ 11172 /* RX_All :: Rx_Status :: prop_scale [15:12] */ 11173 #define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 11174 #define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 11175 #define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_BITS 4 11176 #define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 11177 11178 /* RX_All :: Rx_Status :: integ_scale [11:08] */ 11179 #define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 11180 #define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 11181 #define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 11182 #define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 11183 11184 /* RX_All :: Rx_Status :: prop_scale_acq [07:04] */ 11185 #define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 11186 #define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 11187 #define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 11188 #define RX_ALL_RX_STATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 11189 11190 /* RX_All :: Rx_Status :: integ_scale_acq [03:00] */ 11191 #define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 11192 #define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 11193 #define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 11194 #define RX_ALL_RX_STATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 11195 11196 11197 /* union - case adc_CdrStatus1 [15:00] */ 11198 /* RX_All :: Rx_Status :: reserved0 [15:07] */ 11199 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 11200 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 11201 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 11202 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 11203 11204 /* RX_All :: Rx_Status :: rxMuxCkSel [06:06] */ 11205 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 11206 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 11207 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 11208 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 11209 11210 /* RX_All :: Rx_Status :: glpbk_combo [05:05] */ 11211 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 11212 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 11213 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 11214 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 11215 11216 /* RX_All :: Rx_Status :: clockSwitchSel [04:04] */ 11217 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 11218 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 11219 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 11220 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 11221 11222 /* RX_All :: Rx_Status :: rxck_tst [03:03] */ 11223 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 11224 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 11225 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 11226 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 11227 11228 /* RX_All :: Rx_Status :: rxck_i [02:02] */ 11229 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 11230 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 11231 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 11232 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 11233 11234 /* RX_All :: Rx_Status :: refclk [01:01] */ 11235 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 11236 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 11237 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 11238 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 11239 11240 /* RX_All :: Rx_Status :: pll_bypass [00:00] */ 11241 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 11242 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 11243 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 11244 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 11245 11246 11247 /* union - case adc_CdrStatus2 [15:00] */ 11248 /* RX_All :: Rx_Status :: reserved0 [15:06] */ 11249 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 11250 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 11251 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 11252 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 11253 11254 /* RX_All :: Rx_Status :: rxMuxCkSel [05:05] */ 11255 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 11256 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 11257 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 11258 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 11259 11260 /* RX_All :: Rx_Status :: rxSeqStart [04:04] */ 11261 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 11262 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 11263 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 11264 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 11265 11266 /* RX_All :: Rx_Status :: reserved1 [03:01] */ 11267 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 11268 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 11269 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 11270 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 11271 11272 /* RX_All :: Rx_Status :: rxSeqDone [00:00] */ 11273 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 11274 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 11275 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 11276 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 11277 11278 11279 /* union - case adc_CdrStatus3 [15:00] */ 11280 /* RX_All :: Rx_Status :: reserved0 [15:04] */ 11281 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 11282 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 11283 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 11284 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 11285 11286 /* RX_All :: Rx_Status :: rxSeqStart [03:03] */ 11287 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 11288 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 11289 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 11290 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 11291 11292 /* RX_All :: Rx_Status :: reserved1 [02:01] */ 11293 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 11294 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 11295 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 11296 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 11297 11298 /* RX_All :: Rx_Status :: allow_increment_PC [00:00] */ 11299 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 11300 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 11301 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 11302 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 11303 11304 11305 /* union - case adc_CdrStatus4 [15:00] */ 11306 /* RX_All :: Rx_Status :: reserved0 [15:08] */ 11307 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 11308 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 11309 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 11310 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 11311 11312 /* RX_All :: Rx_Status :: rx_pwrdn [07:07] */ 11313 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 11314 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 11315 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 11316 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 11317 11318 /* RX_All :: Rx_Status :: freq_sel [06:06] */ 11319 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 11320 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 11321 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 11322 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 11323 11324 /* RX_All :: Rx_Status :: pll_lock_rstb [05:05] */ 11325 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 11326 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 11327 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 11328 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 11329 11330 /* RX_All :: Rx_Status :: pwrdn [04:04] */ 11331 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 11332 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 11333 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 11334 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 11335 11336 /* RX_All :: Rx_Status :: reserved1 [03:00] */ 11337 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 11338 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 11339 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 11340 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 11341 11342 11343 /* union - case adc_CdrStatus5 [15:00] */ 11344 /* RX_All :: Rx_Status :: reserved0 [15:00] */ 11345 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 11346 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 11347 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 11348 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 11349 11350 11351 /* union - case adc_CdrStatus6 [15:00] */ 11352 /* RX_All :: Rx_Status :: reserved0 [15:05] */ 11353 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 11354 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 11355 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 11356 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 11357 11358 /* RX_All :: Rx_Status :: rx_reset [04:04] */ 11359 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 11360 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 11361 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 11362 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 11363 11364 /* RX_All :: Rx_Status :: rx_pwrdn [03:03] */ 11365 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 11366 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 11367 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 11368 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 11369 11370 /* RX_All :: Rx_Status :: reset_anlg [02:02] */ 11371 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 11372 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 11373 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 11374 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 11375 11376 /* RX_All :: Rx_Status :: pwrdn_rx [01:01] */ 11377 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 11378 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 11379 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 11380 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 11381 11382 /* RX_All :: Rx_Status :: pwrdn_pll [00:00] */ 11383 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 11384 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 11385 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 11386 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 11387 11388 11389 /* union - case adc_CdrStatus7e [15:00] */ 11390 /* RX_All :: Rx_Status :: reserved0 [15:05] */ 11391 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 11392 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 11393 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 11394 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 11395 11396 /* RX_All :: Rx_Status :: rxck0_even [04:04] */ 11397 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 11398 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 11399 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 11400 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 11401 11402 /* RX_All :: Rx_Status :: rxck1_even [03:03] */ 11403 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 11404 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 11405 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 11406 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 11407 11408 /* RX_All :: Rx_Status :: comdet_even [02:02] */ 11409 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 11410 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 11411 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 11412 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 11413 11414 /* RX_All :: Rx_Status :: en_cdet_even [01:01] */ 11415 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 11416 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 11417 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 11418 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 11419 11420 /* RX_All :: Rx_Status :: comma_adj_en_even [00:00] */ 11421 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 11422 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 11423 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 11424 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 11425 11426 11427 /* union - case adc_CdrStatus7o [15:00] */ 11428 /* RX_All :: Rx_Status :: reserved0 [15:05] */ 11429 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 11430 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 11431 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 11432 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 11433 11434 /* RX_All :: Rx_Status :: rxck0_odd [04:04] */ 11435 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 11436 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 11437 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 11438 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 11439 11440 /* RX_All :: Rx_Status :: rxck1_odd [03:03] */ 11441 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 11442 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 11443 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 11444 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 11445 11446 /* RX_All :: Rx_Status :: comdet_odd [02:02] */ 11447 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 11448 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 11449 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 11450 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 11451 11452 /* RX_All :: Rx_Status :: en_cdet_odd [01:01] */ 11453 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 11454 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 11455 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 11456 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 11457 11458 /* RX_All :: Rx_Status :: comma_adj_en_odd [00:00] */ 11459 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 11460 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 11461 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 11462 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 11463 11464 11465 /* union - case adc_CdrStatus8 [15:00] */ 11466 /* RX_All :: Rx_Status :: reserved0 [15:01] */ 11467 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 11468 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 11469 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 11470 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 11471 11472 /* RX_All :: Rx_Status :: sigdet [00:00] */ 11473 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 11474 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 11475 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 11476 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 11477 11478 11479 /* union - case adc_CdrStatus9 [15:00] */ 11480 /* RX_All :: Rx_Status :: reserved0 [15:00] */ 11481 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 11482 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 11483 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 11484 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 11485 11486 11487 /* union - case adc_CdrStatus10 [15:00] */ 11488 /* RX_All :: Rx_Status :: reserved0 [15:07] */ 11489 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 11490 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 11491 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 11492 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 11493 11494 /* RX_All :: Rx_Status :: prbs_en [06:06] */ 11495 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 11496 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 11497 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 11498 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 11499 11500 /* RX_All :: Rx_Status :: rstb_tst [05:05] */ 11501 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 11502 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 11503 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 11504 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 11505 11506 /* RX_All :: Rx_Status :: reserved1 [04:04] */ 11507 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 11508 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 11509 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 11510 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 11511 11512 /* RX_All :: Rx_Status :: prbs_state [03:00] */ 11513 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 11514 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 11515 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 11516 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 11517 11518 11519 /* union - case adc_CdrStatus11 [15:00] */ 11520 /* RX_All :: Rx_Status :: reserved0 [15:00] */ 11521 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 11522 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 11523 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 11524 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 11525 11526 11527 /* union - case adc_CdrStatus12_1 [15:00] */ 11528 /* RX_All :: Rx_Status :: reserved0 [15:06] */ 11529 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 11530 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 11531 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 11532 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 11533 11534 /* RX_All :: Rx_Status :: enable4 [05:05] */ 11535 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 11536 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 11537 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 11538 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 11539 11540 /* RX_All :: Rx_Status :: radr_test [04:00] */ 11541 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 11542 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 11543 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 11544 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 11545 11546 11547 /* union - case adc_CdrStatus12_2 [15:00] */ 11548 /* RX_All :: Rx_Status :: reserved0 [15:05] */ 11549 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 11550 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 11551 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 11552 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 11553 11554 /* RX_All :: Rx_Status :: wadr_test [04:00] */ 11555 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 11556 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 11557 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 11558 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 11559 11560 11561 /* union - case adc_CdrStatus12_3 [15:00] */ 11562 /* RX_All :: Rx_Status :: reserved0 [15:06] */ 11563 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 11564 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 11565 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 11566 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 11567 11568 /* RX_All :: Rx_Status :: rxck_66B_tmux [05:05] */ 11569 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 11570 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 11571 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 11572 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 11573 11574 /* RX_All :: Rx_Status :: rstb_66B [04:04] */ 11575 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 11576 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 11577 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 11578 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 11579 11580 /* RX_All :: Rx_Status :: prstb_66B_mux [03:03] */ 11581 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 11582 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 11583 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 11584 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 11585 11586 /* RX_All :: Rx_Status :: rxck_i66_tmux [02:02] */ 11587 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 11588 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 11589 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 11590 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 11591 11592 /* RX_All :: Rx_Status :: rstb_i66 [01:01] */ 11593 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 11594 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 11595 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 11596 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 11597 11598 /* RX_All :: Rx_Status :: prstb_i66_mux [00:00] */ 11599 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 11600 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 11601 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 11602 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 11603 11604 11605 /* union - case adc_CdrStatus12_4 [15:00] */ 11606 /* RX_All :: Rx_Status :: reserved0 [15:04] */ 11607 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 11608 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 11609 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 11610 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 11611 11612 /* RX_All :: Rx_Status :: rfifo_error_r [03:02] */ 11613 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 11614 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 11615 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 11616 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 11617 11618 /* RX_All :: Rx_Status :: rfifo_unflow [01:01] */ 11619 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 11620 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 11621 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 11622 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 11623 11624 /* RX_All :: Rx_Status :: rfifo_ovflow [00:00] */ 11625 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 11626 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 11627 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 11628 #define RX_ALL_RX_STATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 11629 11630 11631 /* union - case integ_Status [15:00] */ 11632 /* RX_All :: Rx_Status :: integ_status [15:00] */ 11633 #define RX_ALL_RX_STATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 11634 #define RX_ALL_RX_STATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 11635 #define RX_ALL_RX_STATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 11636 #define RX_ALL_RX_STATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 11637 11638 11639 /* union - case vco_Status [15:00] */ 11640 /* RX_All :: Rx_Status :: vco_status [15:00] */ 11641 #define RX_ALL_RX_STATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 11642 #define RX_ALL_RX_STATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 11643 #define RX_ALL_RX_STATUS_VCO_STATUS_VCO_STATUS_BITS 16 11644 #define RX_ALL_RX_STATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 11645 11646 11647 /* union - case prbs_Status [15:00] */ 11648 /* RX_All :: Rx_Status :: prbs_lock [15:15] */ 11649 #define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 11650 #define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 11651 #define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 11652 #define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 11653 11654 /* RX_All :: Rx_Status :: prbs_stky [14:14] */ 11655 #define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 11656 #define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 11657 #define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_STKY_BITS 1 11658 #define RX_ALL_RX_STATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 11659 11660 /* RX_All :: Rx_Status :: ptbs_errors [13:00] */ 11661 #define RX_ALL_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_MASK 0x3fff 11662 #define RX_ALL_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN 0 11663 #define RX_ALL_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_BITS 14 11664 #define RX_ALL_RX_STATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT 0 11665 11666 11667 11668 /**************************************************************************** 11669 * RX_All :: Rx_Control 11670 */ 11671 /* RX_All :: Rx_Control :: reserved0 [15:03] */ 11672 #define RX_ALL_RX_CONTROL_RESERVED0_MASK 0xfff8 11673 #define RX_ALL_RX_CONTROL_RESERVED0_ALIGN 0 11674 #define RX_ALL_RX_CONTROL_RESERVED0_BITS 13 11675 #define RX_ALL_RX_CONTROL_RESERVED0_SHIFT 3 11676 11677 /* RX_All :: Rx_Control :: status_sel [02:00] */ 11678 #define RX_ALL_RX_CONTROL_STATUS_SEL_MASK 0x0007 11679 #define RX_ALL_RX_CONTROL_STATUS_SEL_ALIGN 0 11680 #define RX_ALL_RX_CONTROL_STATUS_SEL_BITS 3 11681 #define RX_ALL_RX_CONTROL_STATUS_SEL_SHIFT 0 11682 #define RX_ALL_RX_CONTROL_STATUS_SEL_sigdetStatus 0 11683 #define RX_ALL_RX_CONTROL_STATUS_SEL_syncStatus 1 11684 #define RX_ALL_RX_CONTROL_STATUS_SEL_rxTestSel 2 11685 #define RX_ALL_RX_CONTROL_STATUS_SEL_scaleStatus 3 11686 #define RX_ALL_RX_CONTROL_STATUS_SEL_adcCdrStatus 4 11687 #define RX_ALL_RX_CONTROL_STATUS_SEL_integStatus 5 11688 #define RX_ALL_RX_CONTROL_STATUS_SEL_vcoStatus 6 11689 #define RX_ALL_RX_CONTROL_STATUS_SEL_prbsStatus 7 11690 11691 11692 /**************************************************************************** 11693 * RX_All :: Rx_Test 11694 */ 11695 /* RX_All :: Rx_Test :: sigdet_mux_SM [15:12] */ 11696 #define RX_ALL_RX_TEST_SIGDET_MUX_SM_MASK 0xf000 11697 #define RX_ALL_RX_TEST_SIGDET_MUX_SM_ALIGN 0 11698 #define RX_ALL_RX_TEST_SIGDET_MUX_SM_BITS 4 11699 #define RX_ALL_RX_TEST_SIGDET_MUX_SM_SHIFT 12 11700 11701 /* RX_All :: Rx_Test :: reserved0 [11:09] */ 11702 #define RX_ALL_RX_TEST_RESERVED0_MASK 0x0e00 11703 #define RX_ALL_RX_TEST_RESERVED0_ALIGN 0 11704 #define RX_ALL_RX_TEST_RESERVED0_BITS 3 11705 #define RX_ALL_RX_TEST_RESERVED0_SHIFT 9 11706 11707 /* RX_All :: Rx_Test :: tpctrl_SM [08:04] */ 11708 #define RX_ALL_RX_TEST_TPCTRL_SM_MASK 0x01f0 11709 #define RX_ALL_RX_TEST_TPCTRL_SM_ALIGN 0 11710 #define RX_ALL_RX_TEST_TPCTRL_SM_BITS 5 11711 #define RX_ALL_RX_TEST_TPCTRL_SM_SHIFT 4 11712 11713 /* RX_All :: Rx_Test :: testMuxSelect_SM [03:00] */ 11714 #define RX_ALL_RX_TEST_TESTMUXSELECT_SM_MASK 0x000f 11715 #define RX_ALL_RX_TEST_TESTMUXSELECT_SM_ALIGN 0 11716 #define RX_ALL_RX_TEST_TESTMUXSELECT_SM_BITS 4 11717 #define RX_ALL_RX_TEST_TESTMUXSELECT_SM_SHIFT 0 11718 11719 11720 /**************************************************************************** 11721 * RX_All :: Rx_Control_1G_type 11722 */ 11723 /* RX_All :: Rx_Control_1G_type :: fpat_md [15:15] */ 11724 #define RX_ALL_RX_CONTROL_1G_TYPE_FPAT_MD_MASK 0x8000 11725 #define RX_ALL_RX_CONTROL_1G_TYPE_FPAT_MD_ALIGN 0 11726 #define RX_ALL_RX_CONTROL_1G_TYPE_FPAT_MD_BITS 1 11727 #define RX_ALL_RX_CONTROL_1G_TYPE_FPAT_MD_SHIFT 15 11728 11729 /* RX_All :: Rx_Control_1G_type :: pkt_count_en [14:14] */ 11730 #define RX_ALL_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_MASK 0x4000 11731 #define RX_ALL_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_ALIGN 0 11732 #define RX_ALL_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_BITS 1 11733 #define RX_ALL_RX_CONTROL_1G_TYPE_PKT_COUNT_EN_SHIFT 14 11734 11735 /* RX_All :: Rx_Control_1G_type :: staMuxRegDis [13:13] */ 11736 #define RX_ALL_RX_CONTROL_1G_TYPE_STAMUXREGDIS_MASK 0x2000 11737 #define RX_ALL_RX_CONTROL_1G_TYPE_STAMUXREGDIS_ALIGN 0 11738 #define RX_ALL_RX_CONTROL_1G_TYPE_STAMUXREGDIS_BITS 1 11739 #define RX_ALL_RX_CONTROL_1G_TYPE_STAMUXREGDIS_SHIFT 13 11740 11741 /* RX_All :: Rx_Control_1G_type :: prbs_clr_dis [12:12] */ 11742 #define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_MASK 0x1000 11743 #define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_ALIGN 0 11744 #define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_BITS 1 11745 #define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_CLR_DIS_SHIFT 12 11746 11747 /* RX_All :: Rx_Control_1G_type :: rxd_dec_sel [11:11] */ 11748 #define RX_ALL_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_MASK 0x0800 11749 #define RX_ALL_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_ALIGN 0 11750 #define RX_ALL_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_BITS 1 11751 #define RX_ALL_RX_CONTROL_1G_TYPE_RXD_DEC_SEL_SHIFT 11 11752 11753 /* RX_All :: Rx_Control_1G_type :: cgbad_tst [10:10] */ 11754 #define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_TST_MASK 0x0400 11755 #define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_TST_ALIGN 0 11756 #define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_TST_BITS 1 11757 #define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_TST_SHIFT 10 11758 11759 /* RX_All :: Rx_Control_1G_type :: Emon_en [09:09] */ 11760 #define RX_ALL_RX_CONTROL_1G_TYPE_EMON_EN_MASK 0x0200 11761 #define RX_ALL_RX_CONTROL_1G_TYPE_EMON_EN_ALIGN 0 11762 #define RX_ALL_RX_CONTROL_1G_TYPE_EMON_EN_BITS 1 11763 #define RX_ALL_RX_CONTROL_1G_TYPE_EMON_EN_SHIFT 9 11764 11765 /* RX_All :: Rx_Control_1G_type :: prbs_en [08:08] */ 11766 #define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_EN_MASK 0x0100 11767 #define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_EN_ALIGN 0 11768 #define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_EN_BITS 1 11769 #define RX_ALL_RX_CONTROL_1G_TYPE_PRBS_EN_SHIFT 8 11770 11771 /* RX_All :: Rx_Control_1G_type :: cgbad_en [07:07] */ 11772 #define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_EN_MASK 0x0080 11773 #define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_EN_ALIGN 0 11774 #define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_EN_BITS 1 11775 #define RX_ALL_RX_CONTROL_1G_TYPE_CGBAD_EN_SHIFT 7 11776 11777 /* RX_All :: Rx_Control_1G_type :: cstretch [06:06] */ 11778 #define RX_ALL_RX_CONTROL_1G_TYPE_CSTRETCH_MASK 0x0040 11779 #define RX_ALL_RX_CONTROL_1G_TYPE_CSTRETCH_ALIGN 0 11780 #define RX_ALL_RX_CONTROL_1G_TYPE_CSTRETCH_BITS 1 11781 #define RX_ALL_RX_CONTROL_1G_TYPE_CSTRETCH_SHIFT 6 11782 11783 /* RX_All :: Rx_Control_1G_type :: rtbi_ckflip [05:05] */ 11784 #define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_MASK 0x0020 11785 #define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_ALIGN 0 11786 #define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_BITS 1 11787 #define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_CKFLIP_SHIFT 5 11788 11789 /* RX_All :: Rx_Control_1G_type :: rtbi_flip [04:04] */ 11790 #define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_FLIP_MASK 0x0010 11791 #define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_FLIP_ALIGN 0 11792 #define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_FLIP_BITS 1 11793 #define RX_ALL_RX_CONTROL_1G_TYPE_RTBI_FLIP_SHIFT 4 11794 11795 /* RX_All :: Rx_Control_1G_type :: phase_sel [03:03] */ 11796 #define RX_ALL_RX_CONTROL_1G_TYPE_PHASE_SEL_MASK 0x0008 11797 #define RX_ALL_RX_CONTROL_1G_TYPE_PHASE_SEL_ALIGN 0 11798 #define RX_ALL_RX_CONTROL_1G_TYPE_PHASE_SEL_BITS 1 11799 #define RX_ALL_RX_CONTROL_1G_TYPE_PHASE_SEL_SHIFT 3 11800 11801 /* RX_All :: Rx_Control_1G_type :: reserved0 [02:02] */ 11802 #define RX_ALL_RX_CONTROL_1G_TYPE_RESERVED0_MASK 0x0004 11803 #define RX_ALL_RX_CONTROL_1G_TYPE_RESERVED0_ALIGN 0 11804 #define RX_ALL_RX_CONTROL_1G_TYPE_RESERVED0_BITS 1 11805 #define RX_ALL_RX_CONTROL_1G_TYPE_RESERVED0_SHIFT 2 11806 11807 /* RX_All :: Rx_Control_1G_type :: freq_sel_force [01:01] */ 11808 #define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_MASK 0x0002 11809 #define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_ALIGN 0 11810 #define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_BITS 1 11811 #define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_FORCE_SHIFT 1 11812 11813 /* RX_All :: Rx_Control_1G_type :: freq_sel [00:00] */ 11814 #define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_MASK 0x0001 11815 #define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_ALIGN 0 11816 #define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_BITS 1 11817 #define RX_ALL_RX_CONTROL_1G_TYPE_FREQ_SEL_SHIFT 0 11818 11819 11820 /**************************************************************************** 11821 * RX_All :: Rx_Astatus 11822 */ 11823 /* RX_All :: Rx_Astatus :: reserved0 [15:01] */ 11824 #define RX_ALL_RX_ASTATUS_RESERVED0_MASK 0xfffe 11825 #define RX_ALL_RX_ASTATUS_RESERVED0_ALIGN 0 11826 #define RX_ALL_RX_ASTATUS_RESERVED0_BITS 15 11827 #define RX_ALL_RX_ASTATUS_RESERVED0_SHIFT 1 11828 11829 /* RX_All :: Rx_Astatus :: sigdet [00:00] */ 11830 #define RX_ALL_RX_ASTATUS_SIGDET_MASK 0x0001 11831 #define RX_ALL_RX_ASTATUS_SIGDET_ALIGN 0 11832 #define RX_ALL_RX_ASTATUS_SIGDET_BITS 1 11833 #define RX_ALL_RX_ASTATUS_SIGDET_SHIFT 0 11834 11835 11836 /**************************************************************************** 11837 * RX_All :: Rx_analogBias0 11838 */ 11839 /* RX_All :: Rx_analogBias0 :: imode_vcm [15:15] */ 11840 #define RX_ALL_RX_ANALOGBIAS0_IMODE_VCM_MASK 0x8000 11841 #define RX_ALL_RX_ANALOGBIAS0_IMODE_VCM_ALIGN 0 11842 #define RX_ALL_RX_ANALOGBIAS0_IMODE_VCM_BITS 1 11843 #define RX_ALL_RX_ANALOGBIAS0_IMODE_VCM_SHIFT 15 11844 11845 /* RX_All :: Rx_analogBias0 :: imin_vcm [14:14] */ 11846 #define RX_ALL_RX_ANALOGBIAS0_IMIN_VCM_MASK 0x4000 11847 #define RX_ALL_RX_ANALOGBIAS0_IMIN_VCM_ALIGN 0 11848 #define RX_ALL_RX_ANALOGBIAS0_IMIN_VCM_BITS 1 11849 #define RX_ALL_RX_ANALOGBIAS0_IMIN_VCM_SHIFT 14 11850 11851 /* RX_All :: Rx_analogBias0 :: imax_sigdet [13:13] */ 11852 #define RX_ALL_RX_ANALOGBIAS0_IMAX_SIGDET_MASK 0x2000 11853 #define RX_ALL_RX_ANALOGBIAS0_IMAX_SIGDET_ALIGN 0 11854 #define RX_ALL_RX_ANALOGBIAS0_IMAX_SIGDET_BITS 1 11855 #define RX_ALL_RX_ANALOGBIAS0_IMAX_SIGDET_SHIFT 13 11856 11857 /* RX_All :: Rx_analogBias0 :: imode_sigdet [12:12] */ 11858 #define RX_ALL_RX_ANALOGBIAS0_IMODE_SIGDET_MASK 0x1000 11859 #define RX_ALL_RX_ANALOGBIAS0_IMODE_SIGDET_ALIGN 0 11860 #define RX_ALL_RX_ANALOGBIAS0_IMODE_SIGDET_BITS 1 11861 #define RX_ALL_RX_ANALOGBIAS0_IMODE_SIGDET_SHIFT 12 11862 11863 /* RX_All :: Rx_analogBias0 :: imin_sigdet [11:11] */ 11864 #define RX_ALL_RX_ANALOGBIAS0_IMIN_SIGDET_MASK 0x0800 11865 #define RX_ALL_RX_ANALOGBIAS0_IMIN_SIGDET_ALIGN 0 11866 #define RX_ALL_RX_ANALOGBIAS0_IMIN_SIGDET_BITS 1 11867 #define RX_ALL_RX_ANALOGBIAS0_IMIN_SIGDET_SHIFT 11 11868 11869 /* RX_All :: Rx_analogBias0 :: refh_rx [10:10] */ 11870 #define RX_ALL_RX_ANALOGBIAS0_REFH_RX_MASK 0x0400 11871 #define RX_ALL_RX_ANALOGBIAS0_REFH_RX_ALIGN 0 11872 #define RX_ALL_RX_ANALOGBIAS0_REFH_RX_BITS 1 11873 #define RX_ALL_RX_ANALOGBIAS0_REFH_RX_SHIFT 10 11874 11875 /* RX_All :: Rx_analogBias0 :: refl_rx [09:09] */ 11876 #define RX_ALL_RX_ANALOGBIAS0_REFL_RX_MASK 0x0200 11877 #define RX_ALL_RX_ANALOGBIAS0_REFL_RX_ALIGN 0 11878 #define RX_ALL_RX_ANALOGBIAS0_REFL_RX_BITS 1 11879 #define RX_ALL_RX_ANALOGBIAS0_REFL_RX_SHIFT 9 11880 11881 /* RX_All :: Rx_analogBias0 :: tport_en [08:08] */ 11882 #define RX_ALL_RX_ANALOGBIAS0_TPORT_EN_MASK 0x0100 11883 #define RX_ALL_RX_ANALOGBIAS0_TPORT_EN_ALIGN 0 11884 #define RX_ALL_RX_ANALOGBIAS0_TPORT_EN_BITS 1 11885 #define RX_ALL_RX_ANALOGBIAS0_TPORT_EN_SHIFT 8 11886 11887 /* RX_All :: Rx_analogBias0 :: vddr_bg [07:07] */ 11888 #define RX_ALL_RX_ANALOGBIAS0_VDDR_BG_MASK 0x0080 11889 #define RX_ALL_RX_ANALOGBIAS0_VDDR_BG_ALIGN 0 11890 #define RX_ALL_RX_ANALOGBIAS0_VDDR_BG_BITS 1 11891 #define RX_ALL_RX_ANALOGBIAS0_VDDR_BG_SHIFT 7 11892 11893 /* RX_All :: Rx_analogBias0 :: sig_pwrdn [06:06] */ 11894 #define RX_ALL_RX_ANALOGBIAS0_SIG_PWRDN_MASK 0x0040 11895 #define RX_ALL_RX_ANALOGBIAS0_SIG_PWRDN_ALIGN 0 11896 #define RX_ALL_RX_ANALOGBIAS0_SIG_PWRDN_BITS 1 11897 #define RX_ALL_RX_ANALOGBIAS0_SIG_PWRDN_SHIFT 6 11898 11899 /* RX_All :: Rx_analogBias0 :: offset_ctrl [05:03] */ 11900 #define RX_ALL_RX_ANALOGBIAS0_OFFSET_CTRL_MASK 0x0038 11901 #define RX_ALL_RX_ANALOGBIAS0_OFFSET_CTRL_ALIGN 0 11902 #define RX_ALL_RX_ANALOGBIAS0_OFFSET_CTRL_BITS 3 11903 #define RX_ALL_RX_ANALOGBIAS0_OFFSET_CTRL_SHIFT 3 11904 11905 /* RX_All :: Rx_analogBias0 :: offset_sel [02:02] */ 11906 #define RX_ALL_RX_ANALOGBIAS0_OFFSET_SEL_MASK 0x0004 11907 #define RX_ALL_RX_ANALOGBIAS0_OFFSET_SEL_ALIGN 0 11908 #define RX_ALL_RX_ANALOGBIAS0_OFFSET_SEL_BITS 1 11909 #define RX_ALL_RX_ANALOGBIAS0_OFFSET_SEL_SHIFT 2 11910 11911 /* RX_All :: Rx_analogBias0 :: reserved0 [01:00] */ 11912 #define RX_ALL_RX_ANALOGBIAS0_RESERVED0_MASK 0x0003 11913 #define RX_ALL_RX_ANALOGBIAS0_RESERVED0_ALIGN 0 11914 #define RX_ALL_RX_ANALOGBIAS0_RESERVED0_BITS 2 11915 #define RX_ALL_RX_ANALOGBIAS0_RESERVED0_SHIFT 0 11916 11917 #define RX_ALL_RX_EQ_BOOST_EQUALIZER_CONTROL_MASK 0x7 11918 11919 /**************************************************************************** 11920 * RX_All :: Rx_analogBias1 11921 */ 11922 /* RX_All :: Rx_analogBias1 :: imax_clkbuf [15:15] */ 11923 #define RX_ALL_RX_ANALOGBIAS1_IMAX_CLKBUF_MASK 0x8000 11924 #define RX_ALL_RX_ANALOGBIAS1_IMAX_CLKBUF_ALIGN 0 11925 #define RX_ALL_RX_ANALOGBIAS1_IMAX_CLKBUF_BITS 1 11926 #define RX_ALL_RX_ANALOGBIAS1_IMAX_CLKBUF_SHIFT 15 11927 11928 /* RX_All :: Rx_analogBias1 :: imode_clkbuf [14:14] */ 11929 #define RX_ALL_RX_ANALOGBIAS1_IMODE_CLKBUF_MASK 0x4000 11930 #define RX_ALL_RX_ANALOGBIAS1_IMODE_CLKBUF_ALIGN 0 11931 #define RX_ALL_RX_ANALOGBIAS1_IMODE_CLKBUF_BITS 1 11932 #define RX_ALL_RX_ANALOGBIAS1_IMODE_CLKBUF_SHIFT 14 11933 11934 /* RX_All :: Rx_analogBias1 :: imin_clkbuf [13:13] */ 11935 #define RX_ALL_RX_ANALOGBIAS1_IMIN_CLKBUF_MASK 0x2000 11936 #define RX_ALL_RX_ANALOGBIAS1_IMIN_CLKBUF_ALIGN 0 11937 #define RX_ALL_RX_ANALOGBIAS1_IMIN_CLKBUF_BITS 1 11938 #define RX_ALL_RX_ANALOGBIAS1_IMIN_CLKBUF_SHIFT 13 11939 11940 /* RX_All :: Rx_analogBias1 :: imax_eqfl [12:12] */ 11941 #define RX_ALL_RX_ANALOGBIAS1_IMAX_EQFL_MASK 0x1000 11942 #define RX_ALL_RX_ANALOGBIAS1_IMAX_EQFL_ALIGN 0 11943 #define RX_ALL_RX_ANALOGBIAS1_IMAX_EQFL_BITS 1 11944 #define RX_ALL_RX_ANALOGBIAS1_IMAX_EQFL_SHIFT 12 11945 11946 /* RX_All :: Rx_analogBias1 :: imode_eqfl [11:11] */ 11947 #define RX_ALL_RX_ANALOGBIAS1_IMODE_EQFL_MASK 0x0800 11948 #define RX_ALL_RX_ANALOGBIAS1_IMODE_EQFL_ALIGN 0 11949 #define RX_ALL_RX_ANALOGBIAS1_IMODE_EQFL_BITS 1 11950 #define RX_ALL_RX_ANALOGBIAS1_IMODE_EQFL_SHIFT 11 11951 11952 /* RX_All :: Rx_analogBias1 :: imin_eqfl [10:10] */ 11953 #define RX_ALL_RX_ANALOGBIAS1_IMIN_EQFL_MASK 0x0400 11954 #define RX_ALL_RX_ANALOGBIAS1_IMIN_EQFL_ALIGN 0 11955 #define RX_ALL_RX_ANALOGBIAS1_IMIN_EQFL_BITS 1 11956 #define RX_ALL_RX_ANALOGBIAS1_IMIN_EQFL_SHIFT 10 11957 11958 /* RX_All :: Rx_analogBias1 :: imax_dfesum [09:09] */ 11959 #define RX_ALL_RX_ANALOGBIAS1_IMAX_DFESUM_MASK 0x0200 11960 #define RX_ALL_RX_ANALOGBIAS1_IMAX_DFESUM_ALIGN 0 11961 #define RX_ALL_RX_ANALOGBIAS1_IMAX_DFESUM_BITS 1 11962 #define RX_ALL_RX_ANALOGBIAS1_IMAX_DFESUM_SHIFT 9 11963 11964 /* RX_All :: Rx_analogBias1 :: imode_dfesum [08:08] */ 11965 #define RX_ALL_RX_ANALOGBIAS1_IMODE_DFESUM_MASK 0x0100 11966 #define RX_ALL_RX_ANALOGBIAS1_IMODE_DFESUM_ALIGN 0 11967 #define RX_ALL_RX_ANALOGBIAS1_IMODE_DFESUM_BITS 1 11968 #define RX_ALL_RX_ANALOGBIAS1_IMODE_DFESUM_SHIFT 8 11969 11970 /* RX_All :: Rx_analogBias1 :: imin_dfesum [07:07] */ 11971 #define RX_ALL_RX_ANALOGBIAS1_IMIN_DFESUM_MASK 0x0080 11972 #define RX_ALL_RX_ANALOGBIAS1_IMIN_DFESUM_ALIGN 0 11973 #define RX_ALL_RX_ANALOGBIAS1_IMIN_DFESUM_BITS 1 11974 #define RX_ALL_RX_ANALOGBIAS1_IMIN_DFESUM_SHIFT 7 11975 11976 /* RX_All :: Rx_analogBias1 :: imax_vga [06:06] */ 11977 #define RX_ALL_RX_ANALOGBIAS1_IMAX_VGA_MASK 0x0040 11978 #define RX_ALL_RX_ANALOGBIAS1_IMAX_VGA_ALIGN 0 11979 #define RX_ALL_RX_ANALOGBIAS1_IMAX_VGA_BITS 1 11980 #define RX_ALL_RX_ANALOGBIAS1_IMAX_VGA_SHIFT 6 11981 11982 /* RX_All :: Rx_analogBias1 :: imode_vga [05:05] */ 11983 #define RX_ALL_RX_ANALOGBIAS1_IMODE_VGA_MASK 0x0020 11984 #define RX_ALL_RX_ANALOGBIAS1_IMODE_VGA_ALIGN 0 11985 #define RX_ALL_RX_ANALOGBIAS1_IMODE_VGA_BITS 1 11986 #define RX_ALL_RX_ANALOGBIAS1_IMODE_VGA_SHIFT 5 11987 11988 /* RX_All :: Rx_analogBias1 :: imin_vga [04:04] */ 11989 #define RX_ALL_RX_ANALOGBIAS1_IMIN_VGA_MASK 0x0010 11990 #define RX_ALL_RX_ANALOGBIAS1_IMIN_VGA_ALIGN 0 11991 #define RX_ALL_RX_ANALOGBIAS1_IMIN_VGA_BITS 1 11992 #define RX_ALL_RX_ANALOGBIAS1_IMIN_VGA_SHIFT 4 11993 11994 /* RX_All :: Rx_analogBias1 :: imax_interp [03:03] */ 11995 #define RX_ALL_RX_ANALOGBIAS1_IMAX_INTERP_MASK 0x0008 11996 #define RX_ALL_RX_ANALOGBIAS1_IMAX_INTERP_ALIGN 0 11997 #define RX_ALL_RX_ANALOGBIAS1_IMAX_INTERP_BITS 1 11998 #define RX_ALL_RX_ANALOGBIAS1_IMAX_INTERP_SHIFT 3 11999 12000 /* RX_All :: Rx_analogBias1 :: imode_interp [02:02] */ 12001 #define RX_ALL_RX_ANALOGBIAS1_IMODE_INTERP_MASK 0x0004 12002 #define RX_ALL_RX_ANALOGBIAS1_IMODE_INTERP_ALIGN 0 12003 #define RX_ALL_RX_ANALOGBIAS1_IMODE_INTERP_BITS 1 12004 #define RX_ALL_RX_ANALOGBIAS1_IMODE_INTERP_SHIFT 2 12005 12006 /* RX_All :: Rx_analogBias1 :: imin_interp [01:01] */ 12007 #define RX_ALL_RX_ANALOGBIAS1_IMIN_INTERP_MASK 0x0002 12008 #define RX_ALL_RX_ANALOGBIAS1_IMIN_INTERP_ALIGN 0 12009 #define RX_ALL_RX_ANALOGBIAS1_IMIN_INTERP_BITS 1 12010 #define RX_ALL_RX_ANALOGBIAS1_IMIN_INTERP_SHIFT 1 12011 12012 /* RX_All :: Rx_analogBias1 :: imax_vcm [00:00] */ 12013 #define RX_ALL_RX_ANALOGBIAS1_IMAX_VCM_MASK 0x0001 12014 #define RX_ALL_RX_ANALOGBIAS1_IMAX_VCM_ALIGN 0 12015 #define RX_ALL_RX_ANALOGBIAS1_IMAX_VCM_BITS 1 12016 #define RX_ALL_RX_ANALOGBIAS1_IMAX_VCM_SHIFT 0 12017 12018 12019 /**************************************************************************** 12020 * RX_All :: Rx_analogBias2 12021 */ 12022 /* RX_All :: Rx_analogBias2 :: en_clk16 [15:15] */ 12023 #define RX_ALL_RX_ANALOGBIAS2_EN_CLK16_MASK 0x8000 12024 #define RX_ALL_RX_ANALOGBIAS2_EN_CLK16_ALIGN 0 12025 #define RX_ALL_RX_ANALOGBIAS2_EN_CLK16_BITS 1 12026 #define RX_ALL_RX_ANALOGBIAS2_EN_CLK16_SHIFT 15 12027 12028 /* RX_All :: Rx_analogBias2 :: pd_ch_p1 [14:14] */ 12029 #define RX_ALL_RX_ANALOGBIAS2_PD_CH_P1_MASK 0x4000 12030 #define RX_ALL_RX_ANALOGBIAS2_PD_CH_P1_ALIGN 0 12031 #define RX_ALL_RX_ANALOGBIAS2_PD_CH_P1_BITS 1 12032 #define RX_ALL_RX_ANALOGBIAS2_PD_CH_P1_SHIFT 14 12033 12034 /* RX_All :: Rx_analogBias2 :: en_vcctrl [13:13] */ 12035 #define RX_ALL_RX_ANALOGBIAS2_EN_VCCTRL_MASK 0x2000 12036 #define RX_ALL_RX_ANALOGBIAS2_EN_VCCTRL_ALIGN 0 12037 #define RX_ALL_RX_ANALOGBIAS2_EN_VCCTRL_BITS 1 12038 #define RX_ALL_RX_ANALOGBIAS2_EN_VCCTRL_SHIFT 13 12039 12040 /* RX_All :: Rx_analogBias2 :: en_dfeclk [12:12] */ 12041 #define RX_ALL_RX_ANALOGBIAS2_EN_DFECLK_MASK 0x1000 12042 #define RX_ALL_RX_ANALOGBIAS2_EN_DFECLK_ALIGN 0 12043 #define RX_ALL_RX_ANALOGBIAS2_EN_DFECLK_BITS 1 12044 #define RX_ALL_RX_ANALOGBIAS2_EN_DFECLK_SHIFT 12 12045 12046 /* RX_All :: Rx_analogBias2 :: en_hgain [11:11] */ 12047 #define RX_ALL_RX_ANALOGBIAS2_EN_HGAIN_MASK 0x0800 12048 #define RX_ALL_RX_ANALOGBIAS2_EN_HGAIN_ALIGN 0 12049 #define RX_ALL_RX_ANALOGBIAS2_EN_HGAIN_BITS 1 12050 #define RX_ALL_RX_ANALOGBIAS2_EN_HGAIN_SHIFT 11 12051 12052 /* RX_All :: Rx_analogBias2 :: en_dfeckpwr [10:10] */ 12053 #define RX_ALL_RX_ANALOGBIAS2_EN_DFECKPWR_MASK 0x0400 12054 #define RX_ALL_RX_ANALOGBIAS2_EN_DFECKPWR_ALIGN 0 12055 #define RX_ALL_RX_ANALOGBIAS2_EN_DFECKPWR_BITS 1 12056 #define RX_ALL_RX_ANALOGBIAS2_EN_DFECKPWR_SHIFT 10 12057 12058 /* RX_All :: Rx_analogBias2 :: offset_pd [09:09] */ 12059 #define RX_ALL_RX_ANALOGBIAS2_OFFSET_PD_MASK 0x0200 12060 #define RX_ALL_RX_ANALOGBIAS2_OFFSET_PD_ALIGN 0 12061 #define RX_ALL_RX_ANALOGBIAS2_OFFSET_PD_BITS 1 12062 #define RX_ALL_RX_ANALOGBIAS2_OFFSET_PD_SHIFT 9 12063 12064 /* RX_All :: Rx_analogBias2 :: imax_dfetap [08:08] */ 12065 #define RX_ALL_RX_ANALOGBIAS2_IMAX_DFETAP_MASK 0x0100 12066 #define RX_ALL_RX_ANALOGBIAS2_IMAX_DFETAP_ALIGN 0 12067 #define RX_ALL_RX_ANALOGBIAS2_IMAX_DFETAP_BITS 1 12068 #define RX_ALL_RX_ANALOGBIAS2_IMAX_DFETAP_SHIFT 8 12069 12070 /* RX_All :: Rx_analogBias2 :: imode_dfetap [07:07] */ 12071 #define RX_ALL_RX_ANALOGBIAS2_IMODE_DFETAP_MASK 0x0080 12072 #define RX_ALL_RX_ANALOGBIAS2_IMODE_DFETAP_ALIGN 0 12073 #define RX_ALL_RX_ANALOGBIAS2_IMODE_DFETAP_BITS 1 12074 #define RX_ALL_RX_ANALOGBIAS2_IMODE_DFETAP_SHIFT 7 12075 12076 /* RX_All :: Rx_analogBias2 :: imin_dfetap [06:06] */ 12077 #define RX_ALL_RX_ANALOGBIAS2_IMIN_DFETAP_MASK 0x0040 12078 #define RX_ALL_RX_ANALOGBIAS2_IMIN_DFETAP_ALIGN 0 12079 #define RX_ALL_RX_ANALOGBIAS2_IMIN_DFETAP_BITS 1 12080 #define RX_ALL_RX_ANALOGBIAS2_IMIN_DFETAP_SHIFT 6 12081 12082 /* RX_All :: Rx_analogBias2 :: imax_slcd2c [05:05] */ 12083 #define RX_ALL_RX_ANALOGBIAS2_IMAX_SLCD2C_MASK 0x0020 12084 #define RX_ALL_RX_ANALOGBIAS2_IMAX_SLCD2C_ALIGN 0 12085 #define RX_ALL_RX_ANALOGBIAS2_IMAX_SLCD2C_BITS 1 12086 #define RX_ALL_RX_ANALOGBIAS2_IMAX_SLCD2C_SHIFT 5 12087 12088 /* RX_All :: Rx_analogBias2 :: imode_slcd2c [04:04] */ 12089 #define RX_ALL_RX_ANALOGBIAS2_IMODE_SLCD2C_MASK 0x0010 12090 #define RX_ALL_RX_ANALOGBIAS2_IMODE_SLCD2C_ALIGN 0 12091 #define RX_ALL_RX_ANALOGBIAS2_IMODE_SLCD2C_BITS 1 12092 #define RX_ALL_RX_ANALOGBIAS2_IMODE_SLCD2C_SHIFT 4 12093 12094 /* RX_All :: Rx_analogBias2 :: imin_slcd2c [03:03] */ 12095 #define RX_ALL_RX_ANALOGBIAS2_IMIN_SLCD2C_MASK 0x0008 12096 #define RX_ALL_RX_ANALOGBIAS2_IMIN_SLCD2C_ALIGN 0 12097 #define RX_ALL_RX_ANALOGBIAS2_IMIN_SLCD2C_BITS 1 12098 #define RX_ALL_RX_ANALOGBIAS2_IMIN_SLCD2C_SHIFT 3 12099 12100 /* RX_All :: Rx_analogBias2 :: imax_dfevref [02:02] */ 12101 #define RX_ALL_RX_ANALOGBIAS2_IMAX_DFEVREF_MASK 0x0004 12102 #define RX_ALL_RX_ANALOGBIAS2_IMAX_DFEVREF_ALIGN 0 12103 #define RX_ALL_RX_ANALOGBIAS2_IMAX_DFEVREF_BITS 1 12104 #define RX_ALL_RX_ANALOGBIAS2_IMAX_DFEVREF_SHIFT 2 12105 12106 /* RX_All :: Rx_analogBias2 :: imode_dfevref [01:01] */ 12107 #define RX_ALL_RX_ANALOGBIAS2_IMODE_DFEVREF_MASK 0x0002 12108 #define RX_ALL_RX_ANALOGBIAS2_IMODE_DFEVREF_ALIGN 0 12109 #define RX_ALL_RX_ANALOGBIAS2_IMODE_DFEVREF_BITS 1 12110 #define RX_ALL_RX_ANALOGBIAS2_IMODE_DFEVREF_SHIFT 1 12111 12112 /* RX_All :: Rx_analogBias2 :: imin_dfevref [00:00] */ 12113 #define RX_ALL_RX_ANALOGBIAS2_IMIN_DFEVREF_MASK 0x0001 12114 #define RX_ALL_RX_ANALOGBIAS2_IMIN_DFEVREF_ALIGN 0 12115 #define RX_ALL_RX_ANALOGBIAS2_IMIN_DFEVREF_BITS 1 12116 #define RX_ALL_RX_ANALOGBIAS2_IMIN_DFEVREF_SHIFT 0 12117 12118 12119 /**************************************************************************** 12120 * XGXS16G_USER_XgxsBlk2 12121 */ 12122 /**************************************************************************** 12123 * XgxsBlk2 :: rxLnSwap 12124 */ 12125 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_en [15:15] */ 12126 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_MASK 0x8000 12127 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_ALIGN 0 12128 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_BITS 1 12129 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_SHIFT 15 12130 12131 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_force_en [14:14] */ 12132 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_MASK 0x4000 12133 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_ALIGN 0 12134 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_BITS 1 12135 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_SHIFT 14 12136 12137 /* XgxsBlk2 :: rxLnSwap :: Qset_prog_en [13:13] */ 12138 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_MASK 0x2000 12139 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_ALIGN 0 12140 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_BITS 1 12141 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_SHIFT 13 12142 12143 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_link_en [12:12] */ 12144 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_MASK 0x1000 12145 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_ALIGN 0 12146 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_BITS 1 12147 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_SHIFT 12 12148 12149 /* XgxsBlk2 :: rxLnSwap :: Q0_msb [11:11] */ 12150 #define XGXSBLK2_RXLNSWAP_Q0_MSB_MASK 0x0800 12151 #define XGXSBLK2_RXLNSWAP_Q0_MSB_ALIGN 0 12152 #define XGXSBLK2_RXLNSWAP_Q0_MSB_BITS 1 12153 #define XGXSBLK2_RXLNSWAP_Q0_MSB_SHIFT 11 12154 12155 /* XgxsBlk2 :: rxLnSwap :: Q1_msb [10:10] */ 12156 #define XGXSBLK2_RXLNSWAP_Q1_MSB_MASK 0x0400 12157 #define XGXSBLK2_RXLNSWAP_Q1_MSB_ALIGN 0 12158 #define XGXSBLK2_RXLNSWAP_Q1_MSB_BITS 1 12159 #define XGXSBLK2_RXLNSWAP_Q1_MSB_SHIFT 10 12160 12161 /* XgxsBlk2 :: rxLnSwap :: Q2_msb [09:09] */ 12162 #define XGXSBLK2_RXLNSWAP_Q2_MSB_MASK 0x0200 12163 #define XGXSBLK2_RXLNSWAP_Q2_MSB_ALIGN 0 12164 #define XGXSBLK2_RXLNSWAP_Q2_MSB_BITS 1 12165 #define XGXSBLK2_RXLNSWAP_Q2_MSB_SHIFT 9 12166 12167 /* XgxsBlk2 :: rxLnSwap :: Q3_msb [08:08] */ 12168 #define XGXSBLK2_RXLNSWAP_Q3_MSB_MASK 0x0100 12169 #define XGXSBLK2_RXLNSWAP_Q3_MSB_ALIGN 0 12170 #define XGXSBLK2_RXLNSWAP_Q3_MSB_BITS 1 12171 #define XGXSBLK2_RXLNSWAP_Q3_MSB_SHIFT 8 12172 12173 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force0 [07:06] */ 12174 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_MASK 0x00c0 12175 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_ALIGN 0 12176 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_BITS 2 12177 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_SHIFT 6 12178 12179 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force1 [05:04] */ 12180 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_MASK 0x0030 12181 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_ALIGN 0 12182 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_BITS 2 12183 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_SHIFT 4 12184 12185 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force2 [03:02] */ 12186 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_MASK 0x000c 12187 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_ALIGN 0 12188 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_BITS 2 12189 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_SHIFT 2 12190 12191 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force3 [01:00] */ 12192 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_MASK 0x0003 12193 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_ALIGN 0 12194 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_BITS 2 12195 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_SHIFT 0 12196 12197 12198 /**************************************************************************** 12199 * XgxsBlk2 :: txLnSwap 12200 */ 12201 /* XgxsBlk2 :: txLnSwap :: tx_lnswap_en [15:15] */ 12202 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_MASK 0x8000 12203 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_ALIGN 0 12204 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_BITS 1 12205 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_SHIFT 15 12206 12207 /* XgxsBlk2 :: txLnSwap :: reserved0 [14:08] */ 12208 #define XGXSBLK2_TXLNSWAP_RESERVED0_MASK 0x7f00 12209 #define XGXSBLK2_TXLNSWAP_RESERVED0_ALIGN 0 12210 #define XGXSBLK2_TXLNSWAP_RESERVED0_BITS 7 12211 #define XGXSBLK2_TXLNSWAP_RESERVED0_SHIFT 8 12212 12213 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force0 [07:06] */ 12214 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_MASK 0x00c0 12215 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_ALIGN 0 12216 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_BITS 2 12217 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_SHIFT 6 12218 12219 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force1 [05:04] */ 12220 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_MASK 0x0030 12221 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_ALIGN 0 12222 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_BITS 2 12223 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_SHIFT 4 12224 12225 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force2 [03:02] */ 12226 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_MASK 0x000c 12227 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_ALIGN 0 12228 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_BITS 2 12229 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_SHIFT 2 12230 12231 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force3 [01:00] */ 12232 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_MASK 0x0003 12233 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_ALIGN 0 12234 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_BITS 2 12235 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_SHIFT 0 12236 12237 12238 /**************************************************************************** 12239 * XgxsBlk2 :: QsetLns01 12240 */ 12241 /* XgxsBlk2 :: QsetLns01 :: Q1 [15:08] */ 12242 #define XGXSBLK2_QSETLNS01_Q1_MASK 0xff00 12243 #define XGXSBLK2_QSETLNS01_Q1_ALIGN 0 12244 #define XGXSBLK2_QSETLNS01_Q1_BITS 8 12245 #define XGXSBLK2_QSETLNS01_Q1_SHIFT 8 12246 12247 /* XgxsBlk2 :: QsetLns01 :: Q0 [07:00] */ 12248 #define XGXSBLK2_QSETLNS01_Q0_MASK 0x00ff 12249 #define XGXSBLK2_QSETLNS01_Q0_ALIGN 0 12250 #define XGXSBLK2_QSETLNS01_Q0_BITS 8 12251 #define XGXSBLK2_QSETLNS01_Q0_SHIFT 0 12252 12253 12254 /**************************************************************************** 12255 * XgxsBlk2 :: QsetLns23 12256 */ 12257 /* XgxsBlk2 :: QsetLns23 :: Q3 [15:08] */ 12258 #define XGXSBLK2_QSETLNS23_Q3_MASK 0xff00 12259 #define XGXSBLK2_QSETLNS23_Q3_ALIGN 0 12260 #define XGXSBLK2_QSETLNS23_Q3_BITS 8 12261 #define XGXSBLK2_QSETLNS23_Q3_SHIFT 8 12262 12263 /* XgxsBlk2 :: QsetLns23 :: Q2 [07:00] */ 12264 #define XGXSBLK2_QSETLNS23_Q2_MASK 0x00ff 12265 #define XGXSBLK2_QSETLNS23_Q2_ALIGN 0 12266 #define XGXSBLK2_QSETLNS23_Q2_BITS 8 12267 #define XGXSBLK2_QSETLNS23_Q2_SHIFT 0 12268 12269 12270 /**************************************************************************** 12271 * XgxsBlk2 :: unicoreMode10g 12272 */ 12273 /* XgxsBlk2 :: unicoreMode10g :: reserved0 [15:08] */ 12274 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_MASK 0xff00 12275 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_ALIGN 0 12276 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_BITS 8 12277 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_SHIFT 8 12278 12279 /* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gHiG [07:04] */ 12280 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_MASK 0x00f0 12281 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_ALIGN 0 12282 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_BITS 4 12283 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT 4 12284 12285 /* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gCx4 [03:00] */ 12286 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_MASK 0x000f 12287 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_ALIGN 0 12288 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_BITS 4 12289 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT 0 12290 12291 12292 /**************************************************************************** 12293 * XgxsBlk2 :: TestModeLane 12294 */ 12295 /* XgxsBlk2 :: TestModeLane :: reserved0 [15:02] */ 12296 #define XGXSBLK2_TESTMODELANE_RESERVED0_MASK 0xfffc 12297 #define XGXSBLK2_TESTMODELANE_RESERVED0_ALIGN 0 12298 #define XGXSBLK2_TESTMODELANE_RESERVED0_BITS 14 12299 #define XGXSBLK2_TESTMODELANE_RESERVED0_SHIFT 2 12300 12301 /* XgxsBlk2 :: TestModeLane :: slice_selector [01:00] */ 12302 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_MASK 0x0003 12303 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_ALIGN 0 12304 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_BITS 2 12305 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_SHIFT 0 12306 12307 12308 /**************************************************************************** 12309 * XgxsBlk2 :: TestModeCombo 12310 */ 12311 /* XgxsBlk2 :: TestModeCombo :: reserved0 [15:12] */ 12312 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_MASK 0xf000 12313 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_ALIGN 0 12314 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_BITS 4 12315 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_SHIFT 12 12316 12317 /* XgxsBlk2 :: TestModeCombo :: test_monitor_mode2 [11:06] */ 12318 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_MASK 0x0fc0 12319 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_ALIGN 0 12320 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_BITS 6 12321 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_SHIFT 6 12322 12323 /* XgxsBlk2 :: TestModeCombo :: test_monitor_mode1 [05:00] */ 12324 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_MASK 0x003f 12325 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_ALIGN 0 12326 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_BITS 6 12327 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_SHIFT 0 12328 12329 12330 /**************************************************************************** 12331 * XgxsBlk2 :: TestModeMux 12332 */ 12333 /* XgxsBlk2 :: TestModeMux :: reserved0 [15:03] */ 12334 #define XGXSBLK2_TESTMODEMUX_RESERVED0_MASK 0xfff8 12335 #define XGXSBLK2_TESTMODEMUX_RESERVED0_ALIGN 0 12336 #define XGXSBLK2_TESTMODEMUX_RESERVED0_BITS 13 12337 #define XGXSBLK2_TESTMODEMUX_RESERVED0_SHIFT 3 12338 12339 /* XgxsBlk2 :: TestModeMux :: tmux_sel [02:00] */ 12340 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_MASK 0x0007 12341 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_ALIGN 0 12342 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_BITS 3 12343 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_SHIFT 0 12344 12345 12346 /**************************************************************************** 12347 * XgxsBlk2 :: cx4SigdetCnt 12348 */ 12349 /* XgxsBlk2 :: cx4SigdetCnt :: cx4SigdetCnt [15:00] */ 12350 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_MASK 0xffff 12351 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_ALIGN 0 12352 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_BITS 16 12353 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_SHIFT 0 12354 12355 /**************************************************************************** 12356 * XgxsBlk2 :: LaneReset 12357 */ 12358 /* XgxsBlk2 :: LaneReset :: reserved[15:09] */ 12359 #define XGXSBLK2_LANERESET_RESERVED_MASK 0xfe00 12360 #define XGXSBLK2_LANERESET_RESERVED_ALIGN 0 12361 #define XGXSBLK2_LANERESET_RESERVED_BITS 7 12362 #define XGXSBLK2_LANERESET_RESERVED_SHIFT 9 12363 12364 /* XgxsBlk2 :: LaneReset :: reset_pll[08:08] */ 12365 #define XGXSBLK2_LANERESET_RESETPLL_MASK 0x0100 12366 #define XGXSBLK2_LANERESET_RESETPLL_ALIGN 0 12367 #define XGXSBLK2_LANERESET_RESETPLL_BITS 1 12368 #define XGXSBLK2_LANERESET_RESETPLL_SHIFT 8 12369 12370 /* XgxsBlk2 :: LaneReset :: reset_tx[07:04] */ 12371 #define XGXSBLK2_LANERESET_RESETTX_MASK 0x00f0 12372 #define XGXSBLK2_LANERESET_RESETTX_ALIGN 0 12373 #define XGXSBLK2_LANERESET_RESETTX_BITS 4 12374 #define XGXSBLK2_LANERESET_RESETTX_SHIFT 4 12375 12376 /* XgxsBlk2 :: LaneReset :: reset_rx[03:00] */ 12377 #define XGXSBLK2_LANERESET_RESETRX_MASK 0x000f 12378 #define XGXSBLK2_LANERESET_RESETRX_ALIGN 0 12379 #define XGXSBLK2_LANERESET_RESETRX_BITS 4 12380 #define XGXSBLK2_LANERESET_RESETRX_SHIFT 0 12381 12382 12383 /**************************************************************************** 12384 * XGXS16G_USER_GP_Status 12385 */ 12386 /**************************************************************************** 12387 * GP_Status :: MiscRxStatus 12388 */ 12389 /* union - case statusSelect0 [15:00] */ 12390 /* GP_Status :: MiscRxStatus :: capture_NP_lh [15:15] */ 12391 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK 0x8000 12392 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN 0 12393 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS 1 12394 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT 15 12395 12396 /* GP_Status :: MiscRxStatus :: teton_brk_link_lh [14:14] */ 12397 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000 12398 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0 12399 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1 12400 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14 12401 12402 /* GP_Status :: MiscRxStatus :: UP3_lh [13:13] */ 12403 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK 0x2000 12404 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN 0 12405 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS 1 12406 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT 13 12407 12408 /* GP_Status :: MiscRxStatus :: MP5_lh [12:12] */ 12409 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK 0x1000 12410 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN 0 12411 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS 1 12412 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT 12 12413 12414 /* GP_Status :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */ 12415 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800 12416 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0 12417 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1 12418 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11 12419 12420 /* GP_Status :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */ 12421 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400 12422 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0 12423 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1 12424 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10 12425 12426 /* GP_Status :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */ 12427 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200 12428 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0 12429 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1 12430 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9 12431 12432 /* GP_Status :: MiscRxStatus :: invalidSeq_lh [08:08] */ 12433 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK 0x0100 12434 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN 0 12435 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS 1 12436 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT 8 12437 12438 /* GP_Status :: MiscRxStatus :: nullMP_lh [07:07] */ 12439 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK 0x0080 12440 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN 0 12441 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS 1 12442 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT 7 12443 12444 /* GP_Status :: MiscRxStatus :: remotePhyMP_lh [06:06] */ 12445 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK 0x0040 12446 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN 0 12447 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS 1 12448 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT 6 12449 12450 /* GP_Status :: MiscRxStatus :: nonMatchingMP_lh [05:05] */ 12451 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK 0x0020 12452 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0 12453 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS 1 12454 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5 12455 12456 /* GP_Status :: MiscRxStatus :: over1gMP_lh [04:04] */ 12457 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK 0x0010 12458 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN 0 12459 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS 1 12460 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT 4 12461 12462 /* GP_Status :: MiscRxStatus :: rx_config_is_0_lh [03:03] */ 12463 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008 12464 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0 12465 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1 12466 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3 12467 12468 /* GP_Status :: MiscRxStatus :: np_toggle_err_lh [02:02] */ 12469 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK 0x0004 12470 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0 12471 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS 1 12472 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2 12473 12474 /* GP_Status :: MiscRxStatus :: mr_np_lh [01:01] */ 12475 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK 0x0002 12476 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN 0 12477 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS 1 12478 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT 1 12479 12480 /* GP_Status :: MiscRxStatus :: mr_bp_lh [00:00] */ 12481 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK 0x0001 12482 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN 0 12483 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS 1 12484 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT 0 12485 12486 12487 /* union - case statusSelect1 [15:00] */ 12488 /* GP_Status :: MiscRxStatus :: reserved0 [15:04] */ 12489 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK 0xfff0 12490 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN 0 12491 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS 12 12492 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT 4 12493 12494 /* GP_Status :: MiscRxStatus :: np_count [03:00] */ 12495 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK 0x000f 12496 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN 0 12497 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS 4 12498 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT 0 12499 12500 12501 /* union - case statusSelect2 [15:00] */ 12502 /* GP_Status :: MiscRxStatus :: reserved0 [15:06] */ 12503 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK 0xffc0 12504 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN 0 12505 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS 10 12506 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT 6 12507 12508 /* GP_Status :: MiscRxStatus :: remote_phy_enable [05:05] */ 12509 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020 12510 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0 12511 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1 12512 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5 12513 12514 /* GP_Status :: MiscRxStatus :: det_teton_mode [04:04] */ 12515 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK 0x0010 12516 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN 0 12517 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS 1 12518 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT 4 12519 12520 /* GP_Status :: MiscRxStatus :: cu_linkdown [03:03] */ 12521 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK 0x0008 12522 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN 0 12523 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS 1 12524 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT 3 12525 12526 /* GP_Status :: MiscRxStatus :: cu_resolution_error [02:02] */ 12527 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004 12528 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0 12529 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1 12530 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2 12531 12532 /* GP_Status :: MiscRxStatus :: remotePhy_autosel [01:01] */ 12533 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002 12534 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0 12535 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1 12536 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1 12537 12538 /* GP_Status :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */ 12539 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001 12540 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0 12541 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1 12542 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0 12543 12544 12545 12546 /**************************************************************************** 12547 * GP_Status :: xgxsStatus0 12548 */ 12549 /* GP_Status :: xgxsStatus0 :: status_en [15:15] */ 12550 #define GP_STATUS_XGXSSTATUS0_STATUS_EN_MASK 0x8000 12551 #define GP_STATUS_XGXSSTATUS0_STATUS_EN_ALIGN 0 12552 #define GP_STATUS_XGXSSTATUS0_STATUS_EN_BITS 1 12553 #define GP_STATUS_XGXSSTATUS0_STATUS_EN_SHIFT 15 12554 12555 /* GP_Status :: xgxsStatus0 :: reserved0 [14:14] */ 12556 #define GP_STATUS_XGXSSTATUS0_RESERVED0_MASK 0x4000 12557 #define GP_STATUS_XGXSSTATUS0_RESERVED0_ALIGN 0 12558 #define GP_STATUS_XGXSSTATUS0_RESERVED0_BITS 1 12559 #define GP_STATUS_XGXSSTATUS0_RESERVED0_SHIFT 14 12560 12561 /* GP_Status :: xgxsStatus0 :: tx_remote_fault [13:13] */ 12562 #define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_MASK 0x2000 12563 #define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_ALIGN 0 12564 #define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_BITS 1 12565 #define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_SHIFT 13 12566 12567 /* GP_Status :: xgxsStatus0 :: rx_remote_fault [12:12] */ 12568 #define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_MASK 0x1000 12569 #define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_ALIGN 0 12570 #define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_BITS 1 12571 #define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_SHIFT 12 12572 12573 /* GP_Status :: xgxsStatus0 :: txpll_lock [11:11] */ 12574 #define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_MASK 0x0800 12575 #define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_ALIGN 0 12576 #define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_BITS 1 12577 #define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_SHIFT 11 12578 12579 /* GP_Status :: xgxsStatus0 :: txd_fifo_err [10:10] */ 12580 #define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_MASK 0x0400 12581 #define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_ALIGN 0 12582 #define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_BITS 1 12583 #define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_SHIFT 10 12584 12585 /* GP_Status :: xgxsStatus0 :: sequencer_done [09:09] */ 12586 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_MASK 0x0200 12587 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_ALIGN 0 12588 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_BITS 1 12589 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_SHIFT 9 12590 12591 /* GP_Status :: xgxsStatus0 :: sequencer_pass [08:08] */ 12592 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_MASK 0x0100 12593 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_ALIGN 0 12594 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_BITS 1 12595 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_SHIFT 8 12596 12597 /* GP_Status :: xgxsStatus0 :: rxferr [07:04] */ 12598 #define GP_STATUS_XGXSSTATUS0_RXFERR_MASK 0x00f0 12599 #define GP_STATUS_XGXSSTATUS0_RXFERR_ALIGN 0 12600 #define GP_STATUS_XGXSSTATUS0_RXFERR_BITS 4 12601 #define GP_STATUS_XGXSSTATUS0_RXFERR_SHIFT 4 12602 12603 /* GP_Status :: xgxsStatus0 :: pll_mode_afe [03:03] */ 12604 #define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_MASK 0x0008 12605 #define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_ALIGN 0 12606 #define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_BITS 1 12607 #define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_SHIFT 3 12608 12609 /* GP_Status :: xgxsStatus0 :: ckcmp_unflow [02:02] */ 12610 #define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_MASK 0x0004 12611 #define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_ALIGN 0 12612 #define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_BITS 1 12613 #define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_SHIFT 2 12614 12615 /* GP_Status :: xgxsStatus0 :: ckcmp_ovflow [01:01] */ 12616 #define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_MASK 0x0002 12617 #define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_ALIGN 0 12618 #define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_BITS 1 12619 #define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_SHIFT 1 12620 12621 /* GP_Status :: xgxsStatus0 :: skew_status [00:00] */ 12622 #define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_MASK 0x0001 12623 #define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_ALIGN 0 12624 #define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_BITS 1 12625 #define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_SHIFT 0 12626 12627 12628 /**************************************************************************** 12629 * GP_Status :: xgxsStatus1 12630 */ 12631 /* GP_Status :: xgxsStatus1 :: mode_10g_tx [15:12] */ 12632 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_MASK 0xf000 12633 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_ALIGN 0 12634 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_BITS 4 12635 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_SHIFT 12 12636 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS 0 12637 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXG_nCC 1 12638 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_Indlanes 6 12639 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PCI 7 12640 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQ 8 12641 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQnCC 9 12642 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PBypass 10 12643 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PBypass_nDSK 11 12644 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_ComboCoreMode 12 12645 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_Clocks_off 15 12646 12647 /* GP_Status :: xgxsStatus1 :: serdesMode_en_tx [11:11] */ 12648 #define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_MASK 0x0800 12649 #define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_ALIGN 0 12650 #define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_BITS 1 12651 #define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_SHIFT 11 12652 12653 /* GP_Status :: xgxsStatus1 :: sgmii_mode [10:10] */ 12654 #define GP_STATUS_XGXSSTATUS1_SGMII_MODE_MASK 0x0400 12655 #define GP_STATUS_XGXSSTATUS1_SGMII_MODE_ALIGN 0 12656 #define GP_STATUS_XGXSSTATUS1_SGMII_MODE_BITS 1 12657 #define GP_STATUS_XGXSSTATUS1_SGMII_MODE_SHIFT 10 12658 12659 /* GP_Status :: xgxsStatus1 :: link10g [09:09] */ 12660 #define GP_STATUS_XGXSSTATUS1_LINK10G_MASK 0x0200 12661 #define GP_STATUS_XGXSSTATUS1_LINK10G_ALIGN 0 12662 #define GP_STATUS_XGXSSTATUS1_LINK10G_BITS 1 12663 #define GP_STATUS_XGXSSTATUS1_LINK10G_SHIFT 9 12664 12665 /* GP_Status :: xgxsStatus1 :: linkstat [08:08] */ 12666 #define GP_STATUS_XGXSSTATUS1_LINKSTAT_MASK 0x0100 12667 #define GP_STATUS_XGXSSTATUS1_LINKSTAT_ALIGN 0 12668 #define GP_STATUS_XGXSSTATUS1_LINKSTAT_BITS 1 12669 #define GP_STATUS_XGXSSTATUS1_LINKSTAT_SHIFT 8 12670 12671 /* GP_Status :: xgxsStatus1 :: autoneg_complete [07:07] */ 12672 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_MASK 0x0080 12673 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_ALIGN 0 12674 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_BITS 1 12675 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_SHIFT 7 12676 12677 /* GP_Status :: xgxsStatus1 :: reserved0 [06:06] */ 12678 #define GP_STATUS_XGXSSTATUS1_RESERVED0_MASK 0x0040 12679 #define GP_STATUS_XGXSSTATUS1_RESERVED0_ALIGN 0 12680 #define GP_STATUS_XGXSSTATUS1_RESERVED0_BITS 1 12681 #define GP_STATUS_XGXSSTATUS1_RESERVED0_SHIFT 6 12682 12683 /* GP_Status :: xgxsStatus1 :: pll_mode_afe [05:04] */ 12684 #define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_MASK 0x0030 12685 #define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_ALIGN 0 12686 #define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_BITS 2 12687 #define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_SHIFT 4 12688 12689 /* GP_Status :: xgxsStatus1 :: actual_speed_ln0 [03:00] */ 12690 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_MASK 0x000f 12691 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_ALIGN 0 12692 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_BITS 4 12693 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_SHIFT 0 12694 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10M 0 12695 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_100M 1 12696 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_1G 2 12697 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_2p5G 3 12698 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_5G 4 12699 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_6G 5 12700 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_HiG 6 12701 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_CX4 7 12702 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12G_HiG 8 12703 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12p5G 9 12704 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_13G 10 12705 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_15G 11 12706 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_16G 12 12707 12708 12709 /**************************************************************************** 12710 * GP_Status :: xgxsStatus2 12711 */ 12712 /* GP_Status :: xgxsStatus2 :: gpwrdwn_rx [15:12] */ 12713 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_MASK 0xf000 12714 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_ALIGN 0 12715 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_BITS 4 12716 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_SHIFT 12 12717 12718 /* GP_Status :: xgxsStatus2 :: gpwrdwn_tx [11:08] */ 12719 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_MASK 0x0f00 12720 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_ALIGN 0 12721 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_BITS 4 12722 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_SHIFT 8 12723 12724 /* GP_Status :: xgxsStatus2 :: freq_sel_rx [07:04] */ 12725 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_MASK 0x00f0 12726 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_ALIGN 0 12727 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_BITS 4 12728 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_SHIFT 4 12729 12730 /* GP_Status :: xgxsStatus2 :: freq_sel_tx [03:00] */ 12731 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_MASK 0x000f 12732 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_ALIGN 0 12733 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_BITS 4 12734 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_SHIFT 0 12735 12736 12737 /**************************************************************************** 12738 * GP_Status :: Status1000X1 12739 */ 12740 /* GP_Status :: Status1000X1 :: txfifo_err_detected [15:15] */ 12741 #define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK 0x8000 12742 #define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN 0 12743 #define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS 1 12744 #define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT 15 12745 12746 /* GP_Status :: Status1000X1 :: rxfifo_err_detected [14:14] */ 12747 #define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK 0x4000 12748 #define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN 0 12749 #define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS 1 12750 #define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT 14 12751 12752 /* GP_Status :: Status1000X1 :: false_carrier_detected [13:13] */ 12753 #define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK 0x2000 12754 #define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN 0 12755 #define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS 1 12756 #define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT 13 12757 12758 /* GP_Status :: Status1000X1 :: crc_err_detected [12:12] */ 12759 #define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_MASK 0x1000 12760 #define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_ALIGN 0 12761 #define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_BITS 1 12762 #define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_SHIFT 12 12763 12764 /* GP_Status :: Status1000X1 :: tx_err_detected [11:11] */ 12765 #define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_MASK 0x0800 12766 #define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_ALIGN 0 12767 #define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_BITS 1 12768 #define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_SHIFT 11 12769 12770 /* GP_Status :: Status1000X1 :: rx_err_detected [10:10] */ 12771 #define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_MASK 0x0400 12772 #define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_ALIGN 0 12773 #define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_BITS 1 12774 #define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_SHIFT 10 12775 12776 /* GP_Status :: Status1000X1 :: carrier_extend_err_detected [09:09] */ 12777 #define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200 12778 #define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0 12779 #define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1 12780 #define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9 12781 12782 /* GP_Status :: Status1000X1 :: early_end_extension_detected [08:08] */ 12783 #define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100 12784 #define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0 12785 #define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1 12786 #define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8 12787 12788 /* GP_Status :: Status1000X1 :: link_status_change [07:07] */ 12789 #define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_MASK 0x0080 12790 #define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN 0 12791 #define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_BITS 1 12792 #define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT 7 12793 12794 /* GP_Status :: Status1000X1 :: pause_resolution_rxside [06:06] */ 12795 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0040 12796 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 12797 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS 1 12798 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT 6 12799 12800 /* GP_Status :: Status1000X1 :: pause_resolution_txside [05:05] */ 12801 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0020 12802 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 12803 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS 1 12804 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT 5 12805 12806 /* GP_Status :: Status1000X1 :: speed_status [04:03] */ 12807 #define GP_STATUS_STATUS1000X1_SPEED_STATUS_MASK 0x0018 12808 #define GP_STATUS_STATUS1000X1_SPEED_STATUS_ALIGN 0 12809 #define GP_STATUS_STATUS1000X1_SPEED_STATUS_BITS 2 12810 #define GP_STATUS_STATUS1000X1_SPEED_STATUS_SHIFT 3 12811 12812 /* GP_Status :: Status1000X1 :: duplex_status [02:02] */ 12813 #define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_MASK 0x0004 12814 #define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_ALIGN 0 12815 #define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_BITS 1 12816 #define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_SHIFT 2 12817 12818 /* GP_Status :: Status1000X1 :: link_status [01:01] */ 12819 #define GP_STATUS_STATUS1000X1_LINK_STATUS_MASK 0x0002 12820 #define GP_STATUS_STATUS1000X1_LINK_STATUS_ALIGN 0 12821 #define GP_STATUS_STATUS1000X1_LINK_STATUS_BITS 1 12822 #define GP_STATUS_STATUS1000X1_LINK_STATUS_SHIFT 1 12823 12824 /* GP_Status :: Status1000X1 :: sgmii_mode [00:00] */ 12825 #define GP_STATUS_STATUS1000X1_SGMII_MODE_MASK 0x0001 12826 #define GP_STATUS_STATUS1000X1_SGMII_MODE_ALIGN 0 12827 #define GP_STATUS_STATUS1000X1_SGMII_MODE_BITS 1 12828 #define GP_STATUS_STATUS1000X1_SGMII_MODE_SHIFT 0 12829 12830 12831 /**************************************************************************** 12832 * GP_Status :: Status1000X2 12833 */ 12834 /* GP_Status :: Status1000X2 :: sgmii_mode_change [15:15] */ 12835 #define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_MASK 0x8000 12836 #define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN 0 12837 #define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_BITS 1 12838 #define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT 15 12839 12840 /* GP_Status :: Status1000X2 :: consistency_mismatch [14:14] */ 12841 #define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_MASK 0x4000 12842 #define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN 0 12843 #define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_BITS 1 12844 #define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT 14 12845 12846 /* GP_Status :: Status1000X2 :: autoneg_resolution_err [13:13] */ 12847 #define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK 0x2000 12848 #define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN 0 12849 #define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS 1 12850 #define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT 13 12851 12852 /* GP_Status :: Status1000X2 :: sgmii_selector_mismatch [12:12] */ 12853 #define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK 0x1000 12854 #define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN 0 12855 #define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS 1 12856 #define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT 12 12857 12858 /* GP_Status :: Status1000X2 :: sync_status_fail [11:11] */ 12859 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_MASK 0x0800 12860 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN 0 12861 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_BITS 1 12862 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT 11 12863 12864 /* GP_Status :: Status1000X2 :: sync_status_ok [10:10] */ 12865 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_MASK 0x0400 12866 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_ALIGN 0 12867 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_BITS 1 12868 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_SHIFT 10 12869 12870 /* GP_Status :: Status1000X2 :: rudi_c [09:09] */ 12871 #define GP_STATUS_STATUS1000X2_RUDI_C_MASK 0x0200 12872 #define GP_STATUS_STATUS1000X2_RUDI_C_ALIGN 0 12873 #define GP_STATUS_STATUS1000X2_RUDI_C_BITS 1 12874 #define GP_STATUS_STATUS1000X2_RUDI_C_SHIFT 9 12875 12876 /* GP_Status :: Status1000X2 :: rudi_I [08:08] */ 12877 #define GP_STATUS_STATUS1000X2_RUDI_I_MASK 0x0100 12878 #define GP_STATUS_STATUS1000X2_RUDI_I_ALIGN 0 12879 #define GP_STATUS_STATUS1000X2_RUDI_I_BITS 1 12880 #define GP_STATUS_STATUS1000X2_RUDI_I_SHIFT 8 12881 12882 /* GP_Status :: Status1000X2 :: rudi_invalid [07:07] */ 12883 #define GP_STATUS_STATUS1000X2_RUDI_INVALID_MASK 0x0080 12884 #define GP_STATUS_STATUS1000X2_RUDI_INVALID_ALIGN 0 12885 #define GP_STATUS_STATUS1000X2_RUDI_INVALID_BITS 1 12886 #define GP_STATUS_STATUS1000X2_RUDI_INVALID_SHIFT 7 12887 12888 /* GP_Status :: Status1000X2 :: linkDown_syncLoss [06:06] */ 12889 #define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK 0x0040 12890 #define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN 0 12891 #define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS 1 12892 #define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT 6 12893 12894 /* GP_Status :: Status1000X2 :: idle_detect_state [05:05] */ 12895 #define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_MASK 0x0020 12896 #define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_ALIGN 0 12897 #define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_BITS 1 12898 #define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_SHIFT 5 12899 12900 /* GP_Status :: Status1000X2 :: complete_acknowledge_state [04:04] */ 12901 #define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010 12902 #define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0 12903 #define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1 12904 #define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4 12905 12906 /* GP_Status :: Status1000X2 :: acknowledge_detect_state [03:03] */ 12907 #define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK 0x0008 12908 #define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0 12909 #define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS 1 12910 #define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3 12911 12912 /* GP_Status :: Status1000X2 :: ability_detect_state [02:02] */ 12913 #define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_MASK 0x0004 12914 #define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN 0 12915 #define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_BITS 1 12916 #define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT 2 12917 12918 /* union - case anError [01:01] */ 12919 /* GP_Status :: Status1000X2 :: an_error_state [01:01] */ 12920 #define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK 0x0002 12921 #define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN 0 12922 #define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS 1 12923 #define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT 1 12924 12925 12926 /* union - case anDisableLink [01:01] */ 12927 /* GP_Status :: Status1000X2 :: an_disable_link_ok_state [01:01] */ 12928 #define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002 12929 #define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0 12930 #define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1 12931 #define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1 12932 12933 12934 /* GP_Status :: Status1000X2 :: an_enable_state [00:00] */ 12935 #define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_MASK 0x0001 12936 #define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_ALIGN 0 12937 #define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_BITS 1 12938 #define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_SHIFT 0 12939 12940 12941 /**************************************************************************** 12942 * GP_Status :: Status1000X3 12943 */ 12944 /* GP_Status :: Status1000X3 :: reserved0 [15:13] */ 12945 #define GP_STATUS_STATUS1000X3_RESERVED0_MASK 0xe000 12946 #define GP_STATUS_STATUS1000X3_RESERVED0_ALIGN 0 12947 #define GP_STATUS_STATUS1000X3_RESERVED0_BITS 3 12948 #define GP_STATUS_STATUS1000X3_RESERVED0_SHIFT 13 12949 12950 /* GP_Status :: Status1000X3 :: pd_park_an [12:12] */ 12951 #define GP_STATUS_STATUS1000X3_PD_PARK_AN_MASK 0x1000 12952 #define GP_STATUS_STATUS1000X3_PD_PARK_AN_ALIGN 0 12953 #define GP_STATUS_STATUS1000X3_PD_PARK_AN_BITS 1 12954 #define GP_STATUS_STATUS1000X3_PD_PARK_AN_SHIFT 12 12955 12956 /* GP_Status :: Status1000X3 :: remotePhy_autosel [11:11] */ 12957 #define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK 0x0800 12958 #define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN 0 12959 #define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS 1 12960 #define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT 11 12961 12962 /* GP_Status :: Status1000X3 :: latch_linkdown [10:10] */ 12963 #define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_MASK 0x0400 12964 #define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_ALIGN 0 12965 #define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_BITS 1 12966 #define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_SHIFT 10 12967 12968 /* GP_Status :: Status1000X3 :: sd_filter [09:09] */ 12969 #define GP_STATUS_STATUS1000X3_SD_FILTER_MASK 0x0200 12970 #define GP_STATUS_STATUS1000X3_SD_FILTER_ALIGN 0 12971 #define GP_STATUS_STATUS1000X3_SD_FILTER_BITS 1 12972 #define GP_STATUS_STATUS1000X3_SD_FILTER_SHIFT 9 12973 12974 /* GP_Status :: Status1000X3 :: sd_mux [08:08] */ 12975 #define GP_STATUS_STATUS1000X3_SD_MUX_MASK 0x0100 12976 #define GP_STATUS_STATUS1000X3_SD_MUX_ALIGN 0 12977 #define GP_STATUS_STATUS1000X3_SD_MUX_BITS 1 12978 #define GP_STATUS_STATUS1000X3_SD_MUX_SHIFT 8 12979 12980 /* GP_Status :: Status1000X3 :: sd_filter_chg [07:07] */ 12981 #define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_MASK 0x0080 12982 #define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_ALIGN 0 12983 #define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_BITS 1 12984 #define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_SHIFT 7 12985 12986 /* GP_Status :: Status1000X3 :: reserved1 [06:00] */ 12987 #define GP_STATUS_STATUS1000X3_RESERVED1_MASK 0x007f 12988 #define GP_STATUS_STATUS1000X3_RESERVED1_ALIGN 0 12989 #define GP_STATUS_STATUS1000X3_RESERVED1_BITS 7 12990 #define GP_STATUS_STATUS1000X3_RESERVED1_SHIFT 0 12991 12992 12993 /**************************************************************************** 12994 * GP_Status :: TPOUT_1 12995 */ 12996 /* GP_Status :: TPOUT_1 :: tpout1 [15:00] */ 12997 #define GP_STATUS_TPOUT_1_TPOUT1_MASK 0xffff 12998 #define GP_STATUS_TPOUT_1_TPOUT1_ALIGN 0 12999 #define GP_STATUS_TPOUT_1_TPOUT1_BITS 16 13000 #define GP_STATUS_TPOUT_1_TPOUT1_SHIFT 0 13001 13002 13003 /**************************************************************************** 13004 * GP_Status :: TPOUT_2 13005 */ 13006 /* GP_Status :: TPOUT_2 :: tpout2 [15:00] */ 13007 #define GP_STATUS_TPOUT_2_TPOUT2_MASK 0xffff 13008 #define GP_STATUS_TPOUT_2_TPOUT2_ALIGN 0 13009 #define GP_STATUS_TPOUT_2_TPOUT2_BITS 16 13010 #define GP_STATUS_TPOUT_2_TPOUT2_SHIFT 0 13011 13012 13013 /**************************************************************************** 13014 * GP_Status :: xgxsStatus3 13015 */ 13016 /* GP_Status :: xgxsStatus3 :: link [15:15] */ 13017 #define GP_STATUS_XGXSSTATUS3_LINK_MASK 0x8000 13018 #define GP_STATUS_XGXSSTATUS3_LINK_ALIGN 0 13019 #define GP_STATUS_XGXSSTATUS3_LINK_BITS 1 13020 #define GP_STATUS_XGXSSTATUS3_LINK_SHIFT 15 13021 13022 /* GP_Status :: xgxsStatus3 :: link_latchdown [14:14] */ 13023 #define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_MASK 0x4000 13024 #define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_ALIGN 0 13025 #define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_BITS 1 13026 #define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_SHIFT 14 13027 13028 /* GP_Status :: xgxsStatus3 :: latch_linkdown_10g_o [13:13] */ 13029 #define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_MASK 0x2000 13030 #define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_ALIGN 0 13031 #define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_BITS 1 13032 #define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_SHIFT 13 13033 13034 /* GP_Status :: xgxsStatus3 :: pd_park_an [12:12] */ 13035 #define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_MASK 0x1000 13036 #define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_ALIGN 0 13037 #define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_BITS 1 13038 #define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_SHIFT 12 13039 13040 /* GP_Status :: xgxsStatus3 :: gpwrdwn_pll [11:11] */ 13041 #define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_MASK 0x0800 13042 #define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_ALIGN 0 13043 #define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_BITS 1 13044 #define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_SHIFT 11 13045 13046 /* GP_Status :: xgxsStatus3 :: hcd_over_1g [10:00] */ 13047 #define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_MASK 0x07ff 13048 #define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_ALIGN 0 13049 #define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_BITS 11 13050 #define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_SHIFT 0 13051 13052 13053 /**************************************************************************** 13054 * GP_Status :: x2500Status1 13055 */ 13056 /* GP_Status :: x2500Status1 :: hcd_over_1g_or [15:15] */ 13057 #define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_MASK 0x8000 13058 #define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_ALIGN 0 13059 #define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_BITS 1 13060 #define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_SHIFT 15 13061 13062 /* GP_Status :: x2500Status1 :: latch_hcd_over_1g [14:14] */ 13063 #define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_MASK 0x4000 13064 #define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_ALIGN 0 13065 #define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_BITS 1 13066 #define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_SHIFT 14 13067 13068 /* GP_Status :: x2500Status1 :: latchmdio [13:13] */ 13069 #define GP_STATUS_X2500STATUS1_LATCHMDIO_MASK 0x2000 13070 #define GP_STATUS_X2500STATUS1_LATCHMDIO_ALIGN 0 13071 #define GP_STATUS_X2500STATUS1_LATCHMDIO_BITS 1 13072 #define GP_STATUS_X2500STATUS1_LATCHMDIO_SHIFT 13 13073 13074 /* GP_Status :: x2500Status1 :: s_bc_reg_rst [12:12] */ 13075 #define GP_STATUS_X2500STATUS1_S_BC_REG_RST_MASK 0x1000 13076 #define GP_STATUS_X2500STATUS1_S_BC_REG_RST_ALIGN 0 13077 #define GP_STATUS_X2500STATUS1_S_BC_REG_RST_BITS 1 13078 #define GP_STATUS_X2500STATUS1_S_BC_REG_RST_SHIFT 12 13079 13080 /* GP_Status :: x2500Status1 :: s_wait2res [11:11] */ 13081 #define GP_STATUS_X2500STATUS1_S_WAIT2RES_MASK 0x0800 13082 #define GP_STATUS_X2500STATUS1_S_WAIT2RES_ALIGN 0 13083 #define GP_STATUS_X2500STATUS1_S_WAIT2RES_BITS 1 13084 #define GP_STATUS_X2500STATUS1_S_WAIT2RES_SHIFT 11 13085 13086 /* GP_Status :: x2500Status1 :: s_wait30ms [10:10] */ 13087 #define GP_STATUS_X2500STATUS1_S_WAIT30MS_MASK 0x0400 13088 #define GP_STATUS_X2500STATUS1_S_WAIT30MS_ALIGN 0 13089 #define GP_STATUS_X2500STATUS1_S_WAIT30MS_BITS 1 13090 #define GP_STATUS_X2500STATUS1_S_WAIT30MS_SHIFT 10 13091 13092 /* GP_Status :: x2500Status1 :: s_clockswit [09:09] */ 13093 #define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_MASK 0x0200 13094 #define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_ALIGN 0 13095 #define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_BITS 1 13096 #define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_SHIFT 9 13097 13098 /* GP_Status :: x2500Status1 :: s_pllswit [08:08] */ 13099 #define GP_STATUS_X2500STATUS1_S_PLLSWIT_MASK 0x0100 13100 #define GP_STATUS_X2500STATUS1_S_PLLSWIT_ALIGN 0 13101 #define GP_STATUS_X2500STATUS1_S_PLLSWIT_BITS 1 13102 #define GP_STATUS_X2500STATUS1_S_PLLSWIT_SHIFT 8 13103 13104 /* GP_Status :: x2500Status1 :: s_wait4link [07:07] */ 13105 #define GP_STATUS_X2500STATUS1_S_WAIT4LINK_MASK 0x0080 13106 #define GP_STATUS_X2500STATUS1_S_WAIT4LINK_ALIGN 0 13107 #define GP_STATUS_X2500STATUS1_S_WAIT4LINK_BITS 1 13108 #define GP_STATUS_X2500STATUS1_S_WAIT4LINK_SHIFT 7 13109 13110 /* GP_Status :: x2500Status1 :: s_complete [06:06] */ 13111 #define GP_STATUS_X2500STATUS1_S_COMPLETE_MASK 0x0040 13112 #define GP_STATUS_X2500STATUS1_S_COMPLETE_ALIGN 0 13113 #define GP_STATUS_X2500STATUS1_S_COMPLETE_BITS 1 13114 #define GP_STATUS_X2500STATUS1_S_COMPLETE_SHIFT 6 13115 13116 /* GP_Status :: x2500Status1 :: s_lostlink [05:05] */ 13117 #define GP_STATUS_X2500STATUS1_S_LOSTLINK_MASK 0x0020 13118 #define GP_STATUS_X2500STATUS1_S_LOSTLINK_ALIGN 0 13119 #define GP_STATUS_X2500STATUS1_S_LOSTLINK_BITS 1 13120 #define GP_STATUS_X2500STATUS1_S_LOSTLINK_SHIFT 5 13121 13122 /* GP_Status :: x2500Status1 :: s_dead [04:04] */ 13123 #define GP_STATUS_X2500STATUS1_S_DEAD_MASK 0x0010 13124 #define GP_STATUS_X2500STATUS1_S_DEAD_ALIGN 0 13125 #define GP_STATUS_X2500STATUS1_S_DEAD_BITS 1 13126 #define GP_STATUS_X2500STATUS1_S_DEAD_SHIFT 4 13127 13128 /* GP_Status :: x2500Status1 :: fail_cnt [03:00] */ 13129 #define GP_STATUS_X2500STATUS1_FAIL_CNT_MASK 0x000f 13130 #define GP_STATUS_X2500STATUS1_FAIL_CNT_ALIGN 0 13131 #define GP_STATUS_X2500STATUS1_FAIL_CNT_BITS 4 13132 #define GP_STATUS_X2500STATUS1_FAIL_CNT_SHIFT 0 13133 13134 13135 /**************************************************************************** 13136 * GP_Status :: topANStatus1 13137 */ 13138 /* GP_Status :: topANStatus1 :: reserved0 [15:14] */ 13139 #define GP_STATUS_TOPANSTATUS1_RESERVED0_MASK 0xc000 13140 #define GP_STATUS_TOPANSTATUS1_RESERVED0_ALIGN 0 13141 #define GP_STATUS_TOPANSTATUS1_RESERVED0_BITS 2 13142 #define GP_STATUS_TOPANSTATUS1_RESERVED0_SHIFT 14 13143 13144 /* GP_Status :: topANStatus1 :: actual_speed [13:08] */ 13145 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_MASK 0x3f00 13146 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_ALIGN 0 13147 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_BITS 6 13148 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_SHIFT 8 13149 13150 /* GP_Status :: topANStatus1 :: pause_resolution_rxside [07:07] */ 13151 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0080 13152 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 13153 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_BITS 1 13154 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_SHIFT 7 13155 13156 /* GP_Status :: topANStatus1 :: pause_resolution_txside [06:06] */ 13157 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0040 13158 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 13159 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_BITS 1 13160 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_SHIFT 6 13161 13162 /* GP_Status :: topANStatus1 :: cl73_lp_np_BAM_able [05:05] */ 13163 #define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_MASK 0x0020 13164 #define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_ALIGN 0 13165 #define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_BITS 1 13166 #define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_SHIFT 5 13167 13168 /* GP_Status :: topANStatus1 :: cl73_mr_lp_autoneg_able [04:04] */ 13169 #define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_MASK 0x0010 13170 #define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_ALIGN 0 13171 #define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_BITS 1 13172 #define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_SHIFT 4 13173 13174 /* GP_Status :: topANStatus1 :: duplex_status [03:03] */ 13175 #define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_MASK 0x0008 13176 #define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_ALIGN 0 13177 #define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_BITS 1 13178 #define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_SHIFT 3 13179 13180 /* GP_Status :: topANStatus1 :: link_status [02:02] */ 13181 #define GP_STATUS_TOPANSTATUS1_LINK_STATUS_MASK 0x0004 13182 #define GP_STATUS_TOPANSTATUS1_LINK_STATUS_ALIGN 0 13183 #define GP_STATUS_TOPANSTATUS1_LINK_STATUS_BITS 1 13184 #define GP_STATUS_TOPANSTATUS1_LINK_STATUS_SHIFT 2 13185 13186 /* GP_Status :: topANStatus1 :: cl37_autoneg_complete [01:01] */ 13187 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_MASK 0x0002 13188 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_ALIGN 0 13189 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_BITS 1 13190 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_SHIFT 1 13191 13192 /* GP_Status :: topANStatus1 :: cl73_autoneg_complete [00:00] */ 13193 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_MASK 0x0001 13194 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_ALIGN 0 13195 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_BITS 1 13196 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_SHIFT 0 13197 13198 13199 /**************************************************************************** 13200 * GP_Status :: LP_UP1 13201 */ 13202 /* GP_Status :: LP_UP1 :: reserved0 [15:11] */ 13203 #define GP_STATUS_LP_UP1_RESERVED0_MASK 0xf800 13204 #define GP_STATUS_LP_UP1_RESERVED0_ALIGN 0 13205 #define GP_STATUS_LP_UP1_RESERVED0_BITS 5 13206 #define GP_STATUS_LP_UP1_RESERVED0_SHIFT 11 13207 13208 /* GP_Status :: LP_UP1 :: dataRate_rsvd [10:10] */ 13209 #define GP_STATUS_LP_UP1_DATARATE_RSVD_MASK 0x0400 13210 #define GP_STATUS_LP_UP1_DATARATE_RSVD_ALIGN 0 13211 #define GP_STATUS_LP_UP1_DATARATE_RSVD_BITS 1 13212 #define GP_STATUS_LP_UP1_DATARATE_RSVD_SHIFT 10 13213 13214 /* GP_Status :: LP_UP1 :: dataRate_16GX4 [09:09] */ 13215 #define GP_STATUS_LP_UP1_DATARATE_16GX4_MASK 0x0200 13216 #define GP_STATUS_LP_UP1_DATARATE_16GX4_ALIGN 0 13217 #define GP_STATUS_LP_UP1_DATARATE_16GX4_BITS 1 13218 #define GP_STATUS_LP_UP1_DATARATE_16GX4_SHIFT 9 13219 13220 /* GP_Status :: LP_UP1 :: dataRate_15GX4 [08:08] */ 13221 #define GP_STATUS_LP_UP1_DATARATE_15GX4_MASK 0x0100 13222 #define GP_STATUS_LP_UP1_DATARATE_15GX4_ALIGN 0 13223 #define GP_STATUS_LP_UP1_DATARATE_15GX4_BITS 1 13224 #define GP_STATUS_LP_UP1_DATARATE_15GX4_SHIFT 8 13225 13226 /* GP_Status :: LP_UP1 :: dataRate_13GX4 [07:07] */ 13227 #define GP_STATUS_LP_UP1_DATARATE_13GX4_MASK 0x0080 13228 #define GP_STATUS_LP_UP1_DATARATE_13GX4_ALIGN 0 13229 #define GP_STATUS_LP_UP1_DATARATE_13GX4_BITS 1 13230 #define GP_STATUS_LP_UP1_DATARATE_13GX4_SHIFT 7 13231 13232 /* GP_Status :: LP_UP1 :: dataRate_12p5GX4 [06:06] */ 13233 #define GP_STATUS_LP_UP1_DATARATE_12P5GX4_MASK 0x0040 13234 #define GP_STATUS_LP_UP1_DATARATE_12P5GX4_ALIGN 0 13235 #define GP_STATUS_LP_UP1_DATARATE_12P5GX4_BITS 1 13236 #define GP_STATUS_LP_UP1_DATARATE_12P5GX4_SHIFT 6 13237 13238 /* GP_Status :: LP_UP1 :: dataRate_12GX4 [05:05] */ 13239 #define GP_STATUS_LP_UP1_DATARATE_12GX4_MASK 0x0020 13240 #define GP_STATUS_LP_UP1_DATARATE_12GX4_ALIGN 0 13241 #define GP_STATUS_LP_UP1_DATARATE_12GX4_BITS 1 13242 #define GP_STATUS_LP_UP1_DATARATE_12GX4_SHIFT 5 13243 13244 /* GP_Status :: LP_UP1 :: dataRate_10GCX4 [04:04] */ 13245 #define GP_STATUS_LP_UP1_DATARATE_10GCX4_MASK 0x0010 13246 #define GP_STATUS_LP_UP1_DATARATE_10GCX4_ALIGN 0 13247 #define GP_STATUS_LP_UP1_DATARATE_10GCX4_BITS 1 13248 #define GP_STATUS_LP_UP1_DATARATE_10GCX4_SHIFT 4 13249 13250 /* GP_Status :: LP_UP1 :: dataRate_10GX4 [03:03] */ 13251 #define GP_STATUS_LP_UP1_DATARATE_10GX4_MASK 0x0008 13252 #define GP_STATUS_LP_UP1_DATARATE_10GX4_ALIGN 0 13253 #define GP_STATUS_LP_UP1_DATARATE_10GX4_BITS 1 13254 #define GP_STATUS_LP_UP1_DATARATE_10GX4_SHIFT 3 13255 13256 /* GP_Status :: LP_UP1 :: dataRate_6GX4 [02:02] */ 13257 #define GP_STATUS_LP_UP1_DATARATE_6GX4_MASK 0x0004 13258 #define GP_STATUS_LP_UP1_DATARATE_6GX4_ALIGN 0 13259 #define GP_STATUS_LP_UP1_DATARATE_6GX4_BITS 1 13260 #define GP_STATUS_LP_UP1_DATARATE_6GX4_SHIFT 2 13261 13262 /* GP_Status :: LP_UP1 :: dataRate_5GX4 [01:01] */ 13263 #define GP_STATUS_LP_UP1_DATARATE_5GX4_MASK 0x0002 13264 #define GP_STATUS_LP_UP1_DATARATE_5GX4_ALIGN 0 13265 #define GP_STATUS_LP_UP1_DATARATE_5GX4_BITS 1 13266 #define GP_STATUS_LP_UP1_DATARATE_5GX4_SHIFT 1 13267 13268 /* GP_Status :: LP_UP1 :: dataRate_2p5GX1 [00:00] */ 13269 #define GP_STATUS_LP_UP1_DATARATE_2P5GX1_MASK 0x0001 13270 #define GP_STATUS_LP_UP1_DATARATE_2P5GX1_ALIGN 0 13271 #define GP_STATUS_LP_UP1_DATARATE_2P5GX1_BITS 1 13272 #define GP_STATUS_LP_UP1_DATARATE_2P5GX1_SHIFT 0 13273 13274 13275 /**************************************************************************** 13276 * GP_Status :: LP_UP2 13277 */ 13278 /* GP_Status :: LP_UP2 :: reserved0 [15:11] */ 13279 #define GP_STATUS_LP_UP2_RESERVED0_MASK 0xf800 13280 #define GP_STATUS_LP_UP2_RESERVED0_ALIGN 0 13281 #define GP_STATUS_LP_UP2_RESERVED0_BITS 5 13282 #define GP_STATUS_LP_UP2_RESERVED0_SHIFT 11 13283 13284 /* GP_Status :: LP_UP2 :: valid [10:10] */ 13285 #define GP_STATUS_LP_UP2_VALID_MASK 0x0400 13286 #define GP_STATUS_LP_UP2_VALID_ALIGN 0 13287 #define GP_STATUS_LP_UP2_VALID_BITS 1 13288 #define GP_STATUS_LP_UP2_VALID_SHIFT 10 13289 13290 /* GP_Status :: LP_UP2 :: preemphasis [09:06] */ 13291 #define GP_STATUS_LP_UP2_PREEMPHASIS_MASK 0x03c0 13292 #define GP_STATUS_LP_UP2_PREEMPHASIS_ALIGN 0 13293 #define GP_STATUS_LP_UP2_PREEMPHASIS_BITS 4 13294 #define GP_STATUS_LP_UP2_PREEMPHASIS_SHIFT 6 13295 13296 /* GP_Status :: LP_UP2 :: idriver [05:03] */ 13297 #define GP_STATUS_LP_UP2_IDRIVER_MASK 0x0038 13298 #define GP_STATUS_LP_UP2_IDRIVER_ALIGN 0 13299 #define GP_STATUS_LP_UP2_IDRIVER_BITS 3 13300 #define GP_STATUS_LP_UP2_IDRIVER_SHIFT 3 13301 13302 /* GP_Status :: LP_UP2 :: ipredriver [02:00] */ 13303 #define GP_STATUS_LP_UP2_IPREDRIVER_MASK 0x0007 13304 #define GP_STATUS_LP_UP2_IPREDRIVER_ALIGN 0 13305 #define GP_STATUS_LP_UP2_IPREDRIVER_BITS 3 13306 #define GP_STATUS_LP_UP2_IPREDRIVER_SHIFT 0 13307 13308 13309 /**************************************************************************** 13310 * GP_Status :: LP_UP3 13311 */ 13312 /* GP_Status :: LP_UP3 :: reserved0 [15:11] */ 13313 #define GP_STATUS_LP_UP3_RESERVED0_MASK 0xf800 13314 #define GP_STATUS_LP_UP3_RESERVED0_ALIGN 0 13315 #define GP_STATUS_LP_UP3_RESERVED0_BITS 5 13316 #define GP_STATUS_LP_UP3_RESERVED0_SHIFT 11 13317 13318 /* GP_Status :: LP_UP3 :: last [10:10] */ 13319 #define GP_STATUS_LP_UP3_LAST_MASK 0x0400 13320 #define GP_STATUS_LP_UP3_LAST_ALIGN 0 13321 #define GP_STATUS_LP_UP3_LAST_BITS 1 13322 #define GP_STATUS_LP_UP3_LAST_SHIFT 10 13323 13324 /* GP_Status :: LP_UP3 :: reserved1 [09:02] */ 13325 #define GP_STATUS_LP_UP3_RESERVED1_MASK 0x03fc 13326 #define GP_STATUS_LP_UP3_RESERVED1_ALIGN 0 13327 #define GP_STATUS_LP_UP3_RESERVED1_BITS 8 13328 #define GP_STATUS_LP_UP3_RESERVED1_SHIFT 2 13329 13330 /* GP_Status :: LP_UP3 :: scramble_8B10B [01:01] */ 13331 #define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_MASK 0x0002 13332 #define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_ALIGN 0 13333 #define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_BITS 1 13334 #define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_SHIFT 1 13335 13336 /* GP_Status :: LP_UP3 :: HiGig2 [00:00] */ 13337 #define GP_STATUS_LP_UP3_HIGIG2_MASK 0x0001 13338 #define GP_STATUS_LP_UP3_HIGIG2_ALIGN 0 13339 #define GP_STATUS_LP_UP3_HIGIG2_BITS 1 13340 #define GP_STATUS_LP_UP3_HIGIG2_SHIFT 0 13341 13342 13343 /**************************************************************************** 13344 * XGXS16G_USER_AN73_pdet 13345 */ 13346 /**************************************************************************** 13347 * AN73_pdet :: parDet10GStatus 13348 */ 13349 /* union - case pdStatus0 [15:00] */ 13350 /* AN73_pdet :: parDet10GStatus :: pd_link [15:15] */ 13351 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_MASK 0x8000 13352 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_ALIGN 0 13353 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_BITS 1 13354 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_SHIFT 15 13355 13356 /* AN73_pdet :: parDet10GStatus :: pd_CX4_en [14:14] */ 13357 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_MASK 0x4000 13358 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_ALIGN 0 13359 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_BITS 1 13360 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_SHIFT 14 13361 13362 /* AN73_pdet :: parDet10GStatus :: pd_lssFaultCount_en [13:13] */ 13363 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_MASK 0x2000 13364 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_ALIGN 0 13365 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_BITS 1 13366 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_SHIFT 13 13367 13368 /* AN73_pdet :: parDet10GStatus :: pd_tunePll12g [12:12] */ 13369 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_MASK 0x1000 13370 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_ALIGN 0 13371 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_BITS 1 13372 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_SHIFT 12 13373 13374 /* AN73_pdet :: parDet10GStatus :: pd_tunePll10g [11:11] */ 13375 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_MASK 0x0800 13376 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_ALIGN 0 13377 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_BITS 1 13378 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_SHIFT 11 13379 13380 /* AN73_pdet :: parDet10GStatus :: pd_txdLaneOff [10:10] */ 13381 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_MASK 0x0400 13382 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_ALIGN 0 13383 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_BITS 1 13384 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_SHIFT 10 13385 13386 /* AN73_pdet :: parDet10GStatus :: pd_busy [09:09] */ 13387 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_MASK 0x0200 13388 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_ALIGN 0 13389 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_BITS 1 13390 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_SHIFT 9 13391 13392 /* AN73_pdet :: parDet10GStatus :: pd_park_an [08:08] */ 13393 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_MASK 0x0100 13394 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_ALIGN 0 13395 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_BITS 1 13396 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_SHIFT 8 13397 13398 /* AN73_pdet :: parDet10GStatus :: pd_lssFaultCount [07:04] */ 13399 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_MASK 0x00f0 13400 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_ALIGN 0 13401 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_BITS 4 13402 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_SHIFT 4 13403 13404 /* AN73_pdet :: parDet10GStatus :: rxSeqDone [03:00] */ 13405 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_MASK 0x000f 13406 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_ALIGN 0 13407 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_BITS 4 13408 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_SHIFT 0 13409 13410 13411 /* union - case pdStatus1 [15:00] */ 13412 /* AN73_pdet :: parDet10GStatus :: reserved0 [15:09] */ 13413 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_MASK 0xfe00 13414 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_ALIGN 0 13415 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_BITS 7 13416 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_SHIFT 9 13417 13418 /* AN73_pdet :: parDet10GStatus :: fail_lh [08:08] */ 13419 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_MASK 0x0100 13420 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_ALIGN 0 13421 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_BITS 1 13422 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_SHIFT 8 13423 13424 /* AN73_pdet :: parDet10GStatus :: complete_lh [07:07] */ 13425 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_MASK 0x0080 13426 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_ALIGN 0 13427 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_BITS 1 13428 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_SHIFT 7 13429 13430 /* AN73_pdet :: parDet10GStatus :: link12gretry_lh [06:06] */ 13431 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_MASK 0x0040 13432 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_ALIGN 0 13433 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_BITS 1 13434 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_SHIFT 6 13435 13436 /* AN73_pdet :: parDet10GStatus :: wait4link12g_lh [05:05] */ 13437 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_MASK 0x0020 13438 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_ALIGN 0 13439 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_BITS 1 13440 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_SHIFT 5 13441 13442 /* AN73_pdet :: parDet10GStatus :: samplefault_lh [04:04] */ 13443 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_MASK 0x0010 13444 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_ALIGN 0 13445 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_BITS 1 13446 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_SHIFT 4 13447 13448 /* AN73_pdet :: parDet10GStatus :: link10gretry_lh [03:03] */ 13449 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_MASK 0x0008 13450 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_ALIGN 0 13451 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_BITS 1 13452 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_SHIFT 3 13453 13454 /* AN73_pdet :: parDet10GStatus :: wait4link10g_lh [02:02] */ 13455 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_MASK 0x0004 13456 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_ALIGN 0 13457 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_BITS 1 13458 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_SHIFT 2 13459 13460 /* AN73_pdet :: parDet10GStatus :: wait4sigdet_lh [01:01] */ 13461 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_MASK 0x0002 13462 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_ALIGN 0 13463 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_BITS 1 13464 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_SHIFT 1 13465 13466 /* AN73_pdet :: parDet10GStatus :: wait4lock_lh [00:00] */ 13467 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_MASK 0x0001 13468 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_ALIGN 0 13469 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_BITS 1 13470 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_SHIFT 0 13471 13472 13473 13474 /**************************************************************************** 13475 * AN73_pdet :: parDet10GControl 13476 */ 13477 /* AN73_pdet :: parDet10GControl :: force_parDet10g_en [15:15] */ 13478 #define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_MASK 0x8000 13479 #define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_ALIGN 0 13480 #define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_BITS 1 13481 #define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_SHIFT 15 13482 13483 /* AN73_pdet :: parDet10GControl :: pd_cx4_init [14:14] */ 13484 #define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_MASK 0x4000 13485 #define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_ALIGN 0 13486 #define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_BITS 1 13487 #define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_SHIFT 14 13488 13489 /* AN73_pdet :: parDet10GControl :: pd_sw_overide [13:13] */ 13490 #define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_MASK 0x2000 13491 #define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_ALIGN 0 13492 #define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_BITS 1 13493 #define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_SHIFT 13 13494 13495 /* AN73_pdet :: parDet10GControl :: pd_sw_busy_an [12:12] */ 13496 #define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_MASK 0x1000 13497 #define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_ALIGN 0 13498 #define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_BITS 1 13499 #define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_SHIFT 12 13500 13501 /* AN73_pdet :: parDet10GControl :: pd_sw_CX4_en [11:11] */ 13502 #define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_MASK 0x0800 13503 #define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_ALIGN 0 13504 #define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_BITS 1 13505 #define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_SHIFT 11 13506 13507 /* AN73_pdet :: parDet10GControl :: pd_sw_tunePll12g [10:10] */ 13508 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_MASK 0x0400 13509 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_ALIGN 0 13510 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_BITS 1 13511 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_SHIFT 10 13512 13513 /* AN73_pdet :: parDet10GControl :: pd_sw_tunePll10g [09:09] */ 13514 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_MASK 0x0200 13515 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_ALIGN 0 13516 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_BITS 1 13517 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_SHIFT 9 13518 13519 /* AN73_pdet :: parDet10GControl :: pd_sw_lssFaultCount_en [08:08] */ 13520 #define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_MASK 0x0100 13521 #define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_ALIGN 0 13522 #define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_BITS 1 13523 #define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_SHIFT 8 13524 13525 /* AN73_pdet :: parDet10GControl :: pd_sw_txdOff [07:07] */ 13526 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_MASK 0x0080 13527 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_ALIGN 0 13528 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_BITS 1 13529 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_SHIFT 7 13530 13531 /* AN73_pdet :: parDet10GControl :: pd_12g_txdOn_disable [06:06] */ 13532 #define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_MASK 0x0040 13533 #define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_ALIGN 0 13534 #define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_BITS 1 13535 #define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_SHIFT 6 13536 13537 /* AN73_pdet :: parDet10GControl :: pd_12g_disable [05:05] */ 13538 #define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_MASK 0x0020 13539 #define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_ALIGN 0 13540 #define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_BITS 1 13541 #define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_SHIFT 5 13542 13543 /* AN73_pdet :: parDet10GControl :: pd_10g_txdOn_disable [04:04] */ 13544 #define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_MASK 0x0010 13545 #define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_ALIGN 0 13546 #define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_BITS 1 13547 #define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_SHIFT 4 13548 13549 /* AN73_pdet :: parDet10GControl :: pd_10g_disable [03:03] */ 13550 #define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_MASK 0x0008 13551 #define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_ALIGN 0 13552 #define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_BITS 1 13553 #define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_SHIFT 3 13554 13555 /* AN73_pdet :: parDet10GControl :: pd_stat_sel [02:02] */ 13556 #define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_MASK 0x0004 13557 #define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_ALIGN 0 13558 #define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_BITS 1 13559 #define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_SHIFT 2 13560 13561 /* AN73_pdet :: parDet10GControl :: pd_fast_timer_en [01:01] */ 13562 #define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_MASK 0x0002 13563 #define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_ALIGN 0 13564 #define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_BITS 1 13565 #define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_SHIFT 1 13566 13567 /* AN73_pdet :: parDet10GControl :: parDet10g_en [00:00] */ 13568 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_MASK 0x0001 13569 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_ALIGN 0 13570 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_BITS 1 13571 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_SHIFT 0 13572 13573 13574 /**************************************************************************** 13575 * AN73_pdet :: parDet10GSigDet 13576 */ 13577 /* AN73_pdet :: parDet10GSigDet :: pd_sd_count [15:00] */ 13578 #define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_MASK 0xffff 13579 #define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_ALIGN 0 13580 #define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_BITS 16 13581 #define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_SHIFT 0 13582 13583 13584 /**************************************************************************** 13585 * AN73_pdet :: parDet10GLink 13586 */ 13587 /* AN73_pdet :: parDet10GLink :: pd_link_count [15:00] */ 13588 #define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_MASK 0xffff 13589 #define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_ALIGN 0 13590 #define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_BITS 16 13591 #define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_SHIFT 0 13592 13593 13594 /**************************************************************************** 13595 * AN73_pdet :: parDet10GLostLink 13596 */ 13597 /* AN73_pdet :: parDet10GLostLink :: pd_lostlink_count [15:00] */ 13598 #define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_MASK 0xffff 13599 #define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_ALIGN 0 13600 #define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_BITS 16 13601 #define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_SHIFT 0 13602 13603 13604 /**************************************************************************** 13605 * AN73_pdet :: cl73Control1 13606 */ 13607 /* AN73_pdet :: cl73Control1 :: reserved0 [15:08] */ 13608 #define AN73_PDET_CL73CONTROL1_RESERVED0_MASK 0xff00 13609 #define AN73_PDET_CL73CONTROL1_RESERVED0_ALIGN 0 13610 #define AN73_PDET_CL73CONTROL1_RESERVED0_BITS 8 13611 #define AN73_PDET_CL73CONTROL1_RESERVED0_SHIFT 8 13612 13613 /* AN73_pdet :: cl73Control1 :: cl73_internal_10us_timer_val [07:00] */ 13614 #define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_MASK 0x00ff 13615 #define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_ALIGN 0 13616 #define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_BITS 8 13617 #define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_SHIFT 0 13618 13619 13620 /**************************************************************************** 13621 * AN73_pdet :: cl73Control2 13622 */ 13623 /* AN73_pdet :: cl73Control2 :: reserved0 [15:13] */ 13624 #define AN73_PDET_CL73CONTROL2_RESERVED0_MASK 0xe000 13625 #define AN73_PDET_CL73CONTROL2_RESERVED0_ALIGN 0 13626 #define AN73_PDET_CL73CONTROL2_RESERVED0_BITS 3 13627 #define AN73_PDET_CL73CONTROL2_RESERVED0_SHIFT 13 13628 13629 /* AN73_pdet :: cl73Control2 :: cl73_link_fail_inhibit_timer_val [12:00] */ 13630 #define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_MASK 0x1fff 13631 #define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_ALIGN 0 13632 #define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_BITS 13 13633 #define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_SHIFT 0 13634 13635 13636 /**************************************************************************** 13637 * AN73_pdet :: cl73Control3 13638 */ 13639 /* AN73_pdet :: cl73Control3 :: reserved0 [15:13] */ 13640 #define AN73_PDET_CL73CONTROL3_RESERVED0_MASK 0xe000 13641 #define AN73_PDET_CL73CONTROL3_RESERVED0_ALIGN 0 13642 #define AN73_PDET_CL73CONTROL3_RESERVED0_BITS 3 13643 #define AN73_PDET_CL73CONTROL3_RESERVED0_SHIFT 13 13644 13645 /* AN73_pdet :: cl73Control3 :: cl73_an_wait_timer_val [12:00] */ 13646 #define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_MASK 0x1fff 13647 #define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_ALIGN 0 13648 #define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_BITS 13 13649 #define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_SHIFT 0 13650 13651 13652 /**************************************************************************** 13653 * AN73_pdet :: cl73Control4 13654 */ 13655 /* AN73_pdet :: cl73Control4 :: reserved0 [15:13] */ 13656 #define AN73_PDET_CL73CONTROL4_RESERVED0_MASK 0xe000 13657 #define AN73_PDET_CL73CONTROL4_RESERVED0_ALIGN 0 13658 #define AN73_PDET_CL73CONTROL4_RESERVED0_BITS 3 13659 #define AN73_PDET_CL73CONTROL4_RESERVED0_SHIFT 13 13660 13661 /* AN73_pdet :: cl73Control4 :: cl73_break_link_timer_val [12:00] */ 13662 #define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_MASK 0x1fff 13663 #define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_ALIGN 0 13664 #define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_BITS 13 13665 #define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_SHIFT 0 13666 13667 /**************************************************************************** 13668 * XgxsBlk8 :: txLnSwap1 13669 */ 13670 /* XgxsBlk8 :: txLnSwap1 :: reserved_for_eco0 [15:09] */ 13671 #define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_MASK 0xfe00 13672 #define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_ALIGN 0 13673 #define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_BITS 7 13674 #define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_SHIFT 9 13675 13676 /* XgxsBlk8 :: txLnSwap1 :: asymm_en [08:08] */ 13677 #define XGXSBLK8_TXLNSWAP1_ASYMM_EN_MASK 0x0100 13678 #define XGXSBLK8_TXLNSWAP1_ASYMM_EN_ALIGN 0 13679 #define XGXSBLK8_TXLNSWAP1_ASYMM_EN_BITS 1 13680 #define XGXSBLK8_TXLNSWAP1_ASYMM_EN_SHIFT 8 13681 13682 /* XgxsBlk8 :: txLnSwap1 :: tx3_lnswap_sel [07:06] */ 13683 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_MASK 0x00c0 13684 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_ALIGN 0 13685 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_BITS 2 13686 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_SHIFT 6 13687 13688 /* XgxsBlk8 :: txLnSwap1 :: tx2_lnswap_sel [05:04] */ 13689 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_MASK 0x0030 13690 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_ALIGN 0 13691 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_BITS 2 13692 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_SHIFT 4 13693 13694 /* XgxsBlk8 :: txLnSwap1 :: tx1_lnswap_sel [03:02] */ 13695 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_MASK 0x000c 13696 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_ALIGN 0 13697 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_BITS 2 13698 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_SHIFT 2 13699 13700 /* XgxsBlk8 :: txLnSwap1 :: tx0_lnswap_sel [01:00] */ 13701 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_MASK 0x0003 13702 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_ALIGN 0 13703 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_BITS 2 13704 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_SHIFT 0 13705 13706 /**************************************************************************** 13707 * XgxsBlk8 :: rxLnSwap1 13708 */ 13709 /* XgxsBlk8 :: rxLnSwap1 :: reserved_for_eco0 [15:08] */ 13710 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_MASK 0xff00 13711 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_ALIGN 0 13712 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_BITS 8 13713 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_SHIFT 8 13714 13715 /* XgxsBlk8 :: rxLnSwap1 :: rx3_lnswap_sel [07:06] */ 13716 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_MASK 0x00c0 13717 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_ALIGN 0 13718 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_BITS 2 13719 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_SHIFT 6 13720 13721 /* XgxsBlk8 :: rxLnSwap1 :: rx2_lnswap_sel [05:04] */ 13722 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_MASK 0x0030 13723 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_ALIGN 0 13724 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_BITS 2 13725 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_SHIFT 4 13726 13727 /* XgxsBlk8 :: rxLnSwap1 :: rx1_lnswap_sel [03:02] */ 13728 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_MASK 0x000c 13729 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_ALIGN 0 13730 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_BITS 2 13731 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_SHIFT 2 13732 13733 /* XgxsBlk8 :: rxLnSwap1 :: rx0_lnswap_sel [01:00] */ 13734 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_MASK 0x0003 13735 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_ALIGN 0 13736 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_BITS 2 13737 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_SHIFT 0 13738 13739 13740 /**************************************************************************** 13741 * XGXS16G_USER_dsc_1_0 13742 */ 13743 /**************************************************************************** 13744 * dsc_1_0 :: cdr_ctrl0 13745 */ 13746 /* dsc_1_0 :: cdr_ctrl0 :: reserved_for_eco0 [15:09] */ 13747 #define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO0_MASK 0xfe00 13748 #define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 13749 #define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO0_BITS 7 13750 #define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT 9 13751 13752 /* dsc_1_0 :: cdr_ctrl0 :: cdrbr_bwsel_integ [08:07] */ 13753 #define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_INTEG_MASK 0x0180 13754 #define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_INTEG_ALIGN 0 13755 #define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_INTEG_BITS 2 13756 #define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_INTEG_SHIFT 7 13757 13758 /* dsc_1_0 :: cdr_ctrl0 :: cdrbr_bwsel_prop [06:04] */ 13759 #define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_PROP_MASK 0x0070 13760 #define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_PROP_ALIGN 0 13761 #define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_PROP_BITS 3 13762 #define DSC_1_0_CDR_CTRL0_CDRBR_BWSEL_PROP_SHIFT 4 13763 13764 /* dsc_1_0 :: cdr_ctrl0 :: cdrbr_polarity [03:03] */ 13765 #define DSC_1_0_CDR_CTRL0_CDRBR_POLARITY_MASK 0x0008 13766 #define DSC_1_0_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 13767 #define DSC_1_0_CDR_CTRL0_CDRBR_POLARITY_BITS 1 13768 #define DSC_1_0_CDR_CTRL0_CDRBR_POLARITY_SHIFT 3 13769 13770 /* dsc_1_0 :: cdr_ctrl0 :: cdrbr_third_vec_en [02:02] */ 13771 #define DSC_1_0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0004 13772 #define DSC_1_0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 13773 #define DSC_1_0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 13774 #define DSC_1_0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 2 13775 13776 /* dsc_1_0 :: cdr_ctrl0 :: reserved_for_eco1 [01:00] */ 13777 #define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO1_MASK 0x0003 13778 #define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO1_ALIGN 0 13779 #define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO1_BITS 2 13780 #define DSC_1_0_CDR_CTRL0_RESERVED_FOR_ECO1_SHIFT 0 13781 13782 13783 /**************************************************************************** 13784 * dsc_1_0 :: cdr_ctrl1 13785 */ 13786 /* dsc_1_0 :: cdr_ctrl1 :: reserved_for_eco0 [15:10] */ 13787 #define DSC_1_0_CDR_CTRL1_RESERVED_FOR_ECO0_MASK 0xfc00 13788 #define DSC_1_0_CDR_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 13789 #define DSC_1_0_CDR_CTRL1_RESERVED_FOR_ECO0_BITS 6 13790 #define DSC_1_0_CDR_CTRL1_RESERVED_FOR_ECO0_SHIFT 10 13791 13792 /* dsc_1_0 :: cdr_ctrl1 :: cdr_phase_err_frz [09:09] */ 13793 #define DSC_1_0_CDR_CTRL1_CDR_PHASE_ERR_FRZ_MASK 0x0200 13794 #define DSC_1_0_CDR_CTRL1_CDR_PHASE_ERR_FRZ_ALIGN 0 13795 #define DSC_1_0_CDR_CTRL1_CDR_PHASE_ERR_FRZ_BITS 1 13796 #define DSC_1_0_CDR_CTRL1_CDR_PHASE_ERR_FRZ_SHIFT 9 13797 13798 /* dsc_1_0 :: cdr_ctrl1 :: cdr_integ_reg_clr [08:08] */ 13799 #define DSC_1_0_CDR_CTRL1_CDR_INTEG_REG_CLR_MASK 0x0100 13800 #define DSC_1_0_CDR_CTRL1_CDR_INTEG_REG_CLR_ALIGN 0 13801 #define DSC_1_0_CDR_CTRL1_CDR_INTEG_REG_CLR_BITS 1 13802 #define DSC_1_0_CDR_CTRL1_CDR_INTEG_REG_CLR_SHIFT 8 13803 13804 /* dsc_1_0 :: cdr_ctrl1 :: cdr_freq_override_val [07:03] */ 13805 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0x00f8 13806 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 13807 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 5 13808 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 3 13809 13810 /* dsc_1_0 :: cdr_ctrl1 :: cdr_freq_override_en [02:02] */ 13811 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_MASK 0x0004 13812 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_ALIGN 0 13813 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_BITS 1 13814 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_SHIFT 2 13815 13816 /* dsc_1_0 :: cdr_ctrl1 :: cdr_freq_upd_en [01:01] */ 13817 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_UPD_EN_MASK 0x0002 13818 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_UPD_EN_ALIGN 0 13819 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_UPD_EN_BITS 1 13820 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_UPD_EN_SHIFT 1 13821 13822 /* dsc_1_0 :: cdr_ctrl1 :: cdr_freq_en [00:00] */ 13823 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_EN_MASK 0x0001 13824 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_EN_ALIGN 0 13825 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_EN_BITS 1 13826 #define DSC_1_0_CDR_CTRL1_CDR_FREQ_EN_SHIFT 0 13827 13828 13829 /**************************************************************************** 13830 * dsc_1_0 :: cdr_ctrl2 13831 */ 13832 /* dsc_1_0 :: cdr_ctrl2 :: reserved_for_eco0 [15:14] */ 13833 #define DSC_1_0_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xc000 13834 #define DSC_1_0_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 13835 #define DSC_1_0_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 2 13836 #define DSC_1_0_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 14 13837 13838 /* dsc_1_0 :: cdr_ctrl2 :: cdros_bwsel_prop [13:10] */ 13839 #define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_PROP_MASK 0x3c00 13840 #define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_PROP_ALIGN 0 13841 #define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_PROP_BITS 4 13842 #define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_PROP_SHIFT 10 13843 13844 /* dsc_1_0 :: cdr_ctrl2 :: cdros_bwsel_integ [09:06] */ 13845 #define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_INTEG_MASK 0x03c0 13846 #define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_INTEG_ALIGN 0 13847 #define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_INTEG_BITS 4 13848 #define DSC_1_0_CDR_CTRL2_CDROS_BWSEL_INTEG_SHIFT 6 13849 13850 /* dsc_1_0 :: cdr_ctrl2 :: cdros_falling_edge [05:05] */ 13851 #define DSC_1_0_CDR_CTRL2_CDROS_FALLING_EDGE_MASK 0x0020 13852 #define DSC_1_0_CDR_CTRL2_CDROS_FALLING_EDGE_ALIGN 0 13853 #define DSC_1_0_CDR_CTRL2_CDROS_FALLING_EDGE_BITS 1 13854 #define DSC_1_0_CDR_CTRL2_CDROS_FALLING_EDGE_SHIFT 5 13855 13856 /* dsc_1_0 :: cdr_ctrl2 :: cdros_rising_edge [04:04] */ 13857 #define DSC_1_0_CDR_CTRL2_CDROS_RISING_EDGE_MASK 0x0010 13858 #define DSC_1_0_CDR_CTRL2_CDROS_RISING_EDGE_ALIGN 0 13859 #define DSC_1_0_CDR_CTRL2_CDROS_RISING_EDGE_BITS 1 13860 #define DSC_1_0_CDR_CTRL2_CDROS_RISING_EDGE_SHIFT 4 13861 13862 /* dsc_1_0 :: cdr_ctrl2 :: cdros_phase_sat_ctrl [03:02] */ 13863 #define DSC_1_0_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_MASK 0x000c 13864 #define DSC_1_0_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_ALIGN 0 13865 #define DSC_1_0_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_BITS 2 13866 #define DSC_1_0_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_SHIFT 2 13867 13868 /* dsc_1_0 :: cdr_ctrl2 :: cdros_peak_polarity [01:01] */ 13869 #define DSC_1_0_CDR_CTRL2_CDROS_PEAK_POLARITY_MASK 0x0002 13870 #define DSC_1_0_CDR_CTRL2_CDROS_PEAK_POLARITY_ALIGN 0 13871 #define DSC_1_0_CDR_CTRL2_CDROS_PEAK_POLARITY_BITS 1 13872 #define DSC_1_0_CDR_CTRL2_CDROS_PEAK_POLARITY_SHIFT 1 13873 13874 /* dsc_1_0 :: cdr_ctrl2 :: cdros_zero_polarity [00:00] */ 13875 #define DSC_1_0_CDR_CTRL2_CDROS_ZERO_POLARITY_MASK 0x0001 13876 #define DSC_1_0_CDR_CTRL2_CDROS_ZERO_POLARITY_ALIGN 0 13877 #define DSC_1_0_CDR_CTRL2_CDROS_ZERO_POLARITY_BITS 1 13878 #define DSC_1_0_CDR_CTRL2_CDROS_ZERO_POLARITY_SHIFT 0 13879 13880 13881 /**************************************************************************** 13882 * dsc_1_0 :: cdr_status0 13883 */ 13884 /* dsc_1_0 :: cdr_status0 :: integ_reg [15:00] */ 13885 #define DSC_1_0_CDR_STATUS0_INTEG_REG_MASK 0xffff 13886 #define DSC_1_0_CDR_STATUS0_INTEG_REG_ALIGN 0 13887 #define DSC_1_0_CDR_STATUS0_INTEG_REG_BITS 16 13888 #define DSC_1_0_CDR_STATUS0_INTEG_REG_SHIFT 0 13889 13890 13891 /**************************************************************************** 13892 * dsc_1_0 :: cdr_status1 13893 */ 13894 /* dsc_1_0 :: cdr_status1 :: reserved_for_eco0 [15:06] */ 13895 #define DSC_1_0_CDR_STATUS1_RESERVED_FOR_ECO0_MASK 0xffc0 13896 #define DSC_1_0_CDR_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 13897 #define DSC_1_0_CDR_STATUS1_RESERVED_FOR_ECO0_BITS 10 13898 #define DSC_1_0_CDR_STATUS1_RESERVED_FOR_ECO0_SHIFT 6 13899 13900 /* dsc_1_0 :: cdr_status1 :: phase_err [05:00] */ 13901 #define DSC_1_0_CDR_STATUS1_PHASE_ERR_MASK 0x003f 13902 #define DSC_1_0_CDR_STATUS1_PHASE_ERR_ALIGN 0 13903 #define DSC_1_0_CDR_STATUS1_PHASE_ERR_BITS 6 13904 #define DSC_1_0_CDR_STATUS1_PHASE_ERR_SHIFT 0 13905 13906 13907 /**************************************************************************** 13908 * dsc_1_0 :: pi_ctrl0 13909 */ 13910 /* dsc_1_0 :: pi_ctrl0 :: reserved_for_eco0 [15:11] */ 13911 #define DSC_1_0_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0xf800 13912 #define DSC_1_0_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 13913 #define DSC_1_0_PI_CTRL0_RESERVED_FOR_ECO0_BITS 5 13914 #define DSC_1_0_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 13915 13916 /* dsc_1_0 :: pi_ctrl0 :: pi_phase_invert [10:10] */ 13917 #define DSC_1_0_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0400 13918 #define DSC_1_0_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 13919 #define DSC_1_0_PI_CTRL0_PI_PHASE_INVERT_BITS 1 13920 #define DSC_1_0_PI_CTRL0_PI_PHASE_INVERT_SHIFT 10 13921 13922 /* dsc_1_0 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */ 13923 #define DSC_1_0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK 0x0200 13924 #define DSC_1_0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 13925 #define DSC_1_0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS 1 13926 #define DSC_1_0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT 9 13927 13928 /* dsc_1_0 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */ 13929 #define DSC_1_0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0100 13930 #define DSC_1_0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 13931 #define DSC_1_0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS 1 13932 #define DSC_1_0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT 8 13933 13934 /* dsc_1_0 :: pi_ctrl0 :: pi_phase_dec [07:07] */ 13935 #define DSC_1_0_PI_CTRL0_PI_PHASE_DEC_MASK 0x0080 13936 #define DSC_1_0_PI_CTRL0_PI_PHASE_DEC_ALIGN 0 13937 #define DSC_1_0_PI_CTRL0_PI_PHASE_DEC_BITS 1 13938 #define DSC_1_0_PI_CTRL0_PI_PHASE_DEC_SHIFT 7 13939 13940 /* dsc_1_0 :: pi_ctrl0 :: pi_phase_inc [06:06] */ 13941 #define DSC_1_0_PI_CTRL0_PI_PHASE_INC_MASK 0x0040 13942 #define DSC_1_0_PI_CTRL0_PI_PHASE_INC_ALIGN 0 13943 #define DSC_1_0_PI_CTRL0_PI_PHASE_INC_BITS 1 13944 #define DSC_1_0_PI_CTRL0_PI_PHASE_INC_SHIFT 6 13945 13946 /* dsc_1_0 :: pi_ctrl0 :: pi_phase_strobe [05:05] */ 13947 #define DSC_1_0_PI_CTRL0_PI_PHASE_STROBE_MASK 0x0020 13948 #define DSC_1_0_PI_CTRL0_PI_PHASE_STROBE_ALIGN 0 13949 #define DSC_1_0_PI_CTRL0_PI_PHASE_STROBE_BITS 1 13950 #define DSC_1_0_PI_CTRL0_PI_PHASE_STROBE_SHIFT 5 13951 13952 /* dsc_1_0 :: pi_ctrl0 :: pi_phase_delta [04:01] */ 13953 #define DSC_1_0_PI_CTRL0_PI_PHASE_DELTA_MASK 0x001e 13954 #define DSC_1_0_PI_CTRL0_PI_PHASE_DELTA_ALIGN 0 13955 #define DSC_1_0_PI_CTRL0_PI_PHASE_DELTA_BITS 4 13956 #define DSC_1_0_PI_CTRL0_PI_PHASE_DELTA_SHIFT 1 13957 13958 /* dsc_1_0 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 13959 #define DSC_1_0_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 13960 #define DSC_1_0_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 13961 #define DSC_1_0_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 13962 #define DSC_1_0_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 13963 13964 13965 /**************************************************************************** 13966 * dsc_1_0 :: pi_status0 13967 */ 13968 /* dsc_1_0 :: pi_status0 :: reserved_for_eco0 [15:14] */ 13969 #define DSC_1_0_PI_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 13970 #define DSC_1_0_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 13971 #define DSC_1_0_PI_STATUS0_RESERVED_FOR_ECO0_BITS 2 13972 #define DSC_1_0_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 13973 13974 /* dsc_1_0 :: pi_status0 :: clk90_phase_offset [13:07] */ 13975 #define DSC_1_0_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 13976 #define DSC_1_0_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 13977 #define DSC_1_0_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 13978 #define DSC_1_0_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 13979 13980 /* dsc_1_0 :: pi_status0 :: phase_cntr [06:00] */ 13981 #define DSC_1_0_PI_STATUS0_PHASE_CNTR_MASK 0x007f 13982 #define DSC_1_0_PI_STATUS0_PHASE_CNTR_ALIGN 0 13983 #define DSC_1_0_PI_STATUS0_PHASE_CNTR_BITS 7 13984 #define DSC_1_0_PI_STATUS0_PHASE_CNTR_SHIFT 0 13985 13986 13987 /**************************************************************************** 13988 * dsc_1_0 :: dfe_vga_ctrl0 13989 */ 13990 /* dsc_1_0 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:12] */ 13991 #define DSC_1_0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK 0xf000 13992 #define DSC_1_0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 13993 #define DSC_1_0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS 4 13994 #define DSC_1_0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT 12 13995 13996 /* dsc_1_0 :: dfe_vga_ctrl0 :: trnsum_tap0_only [11:11] */ 13997 #define DSC_1_0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0800 13998 #define DSC_1_0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 13999 #define DSC_1_0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 14000 #define DSC_1_0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 11 14001 14002 /* dsc_1_0 :: dfe_vga_ctrl0 :: sum_m1err [10:10] */ 14003 #define DSC_1_0_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0400 14004 #define DSC_1_0_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 14005 #define DSC_1_0_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 14006 #define DSC_1_0_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 10 14007 14008 /* dsc_1_0 :: dfe_vga_ctrl0 :: dfe_vga_clken [09:09] */ 14009 #define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0200 14010 #define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 14011 #define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 14012 #define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 9 14013 14014 /* dsc_1_0 :: dfe_vga_ctrl0 :: hysteresis_en [08:08] */ 14015 #define DSC_1_0_DFE_VGA_CTRL0_HYSTERESIS_EN_MASK 0x0100 14016 #define DSC_1_0_DFE_VGA_CTRL0_HYSTERESIS_EN_ALIGN 0 14017 #define DSC_1_0_DFE_VGA_CTRL0_HYSTERESIS_EN_BITS 1 14018 #define DSC_1_0_DFE_VGA_CTRL0_HYSTERESIS_EN_SHIFT 8 14019 14020 /* dsc_1_0 :: dfe_vga_ctrl0 :: dfe_vga_write_val [07:02] */ 14021 #define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_MASK 0x00fc 14022 #define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_ALIGN 0 14023 #define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_BITS 6 14024 #define DSC_1_0_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_SHIFT 2 14025 14026 /* dsc_1_0 :: dfe_vga_ctrl0 :: vga_write_en [01:01] */ 14027 #define DSC_1_0_DFE_VGA_CTRL0_VGA_WRITE_EN_MASK 0x0002 14028 #define DSC_1_0_DFE_VGA_CTRL0_VGA_WRITE_EN_ALIGN 0 14029 #define DSC_1_0_DFE_VGA_CTRL0_VGA_WRITE_EN_BITS 1 14030 #define DSC_1_0_DFE_VGA_CTRL0_VGA_WRITE_EN_SHIFT 1 14031 14032 /* dsc_1_0 :: dfe_vga_ctrl0 :: dfe_write_en [00:00] */ 14033 #define DSC_1_0_DFE_VGA_CTRL0_DFE_WRITE_EN_MASK 0x0001 14034 #define DSC_1_0_DFE_VGA_CTRL0_DFE_WRITE_EN_ALIGN 0 14035 #define DSC_1_0_DFE_VGA_CTRL0_DFE_WRITE_EN_BITS 1 14036 #define DSC_1_0_DFE_VGA_CTRL0_DFE_WRITE_EN_SHIFT 0 14037 14038 14039 /**************************************************************************** 14040 * dsc_1_0 :: dfe_vga_ctrl1 14041 */ 14042 /* dsc_1_0 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:15] */ 14043 #define DSC_1_0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 14044 #define DSC_1_0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 14045 #define DSC_1_0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 1 14046 #define DSC_1_0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 14047 14048 /* dsc_1_0 :: dfe_vga_ctrl1 :: trnsum_otap_en [14:08] */ 14049 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_MASK 0x7f00 14050 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_ALIGN 0 14051 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_BITS 7 14052 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_SHIFT 8 14053 14054 /* dsc_1_0 :: dfe_vga_ctrl1 :: trnsum_etap_en [07:01] */ 14055 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_MASK 0x00fe 14056 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_ALIGN 0 14057 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_BITS 7 14058 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_SHIFT 1 14059 14060 /* dsc_1_0 :: dfe_vga_ctrl1 :: trnsum_en [00:00] */ 14061 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_EN_MASK 0x0001 14062 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_EN_ALIGN 0 14063 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_EN_BITS 1 14064 #define DSC_1_0_DFE_VGA_CTRL1_TRNSUM_EN_SHIFT 0 14065 14066 14067 /**************************************************************************** 14068 * dsc_1_0 :: dfe_vga_ctrl2 14069 */ 14070 /* dsc_1_0 :: dfe_vga_ctrl2 :: vga_polarity [15:15] */ 14071 #define DSC_1_0_DFE_VGA_CTRL2_VGA_POLARITY_MASK 0x8000 14072 #define DSC_1_0_DFE_VGA_CTRL2_VGA_POLARITY_ALIGN 0 14073 #define DSC_1_0_DFE_VGA_CTRL2_VGA_POLARITY_BITS 1 14074 #define DSC_1_0_DFE_VGA_CTRL2_VGA_POLARITY_SHIFT 15 14075 14076 /* dsc_1_0 :: dfe_vga_ctrl2 :: dfe_polarity [14:14] */ 14077 #define DSC_1_0_DFE_VGA_CTRL2_DFE_POLARITY_MASK 0x4000 14078 #define DSC_1_0_DFE_VGA_CTRL2_DFE_POLARITY_ALIGN 0 14079 #define DSC_1_0_DFE_VGA_CTRL2_DFE_POLARITY_BITS 1 14080 #define DSC_1_0_DFE_VGA_CTRL2_DFE_POLARITY_SHIFT 14 14081 14082 /* dsc_1_0 :: dfe_vga_ctrl2 :: trnsum_otap_sign [13:07] */ 14083 #define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_MASK 0x3f80 14084 #define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_ALIGN 0 14085 #define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_BITS 7 14086 #define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_SHIFT 7 14087 14088 /* dsc_1_0 :: dfe_vga_ctrl2 :: trnsum_etap_sign [06:00] */ 14089 #define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_MASK 0x007f 14090 #define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_ALIGN 0 14091 #define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_BITS 7 14092 #define DSC_1_0_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_SHIFT 0 14093 14094 14095 /**************************************************************************** 14096 * dsc_1_0 :: dfe_vga_ctrl3 14097 */ 14098 /* dsc_1_0 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:10] */ 14099 #define DSC_1_0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK 0xfc00 14100 #define DSC_1_0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 14101 #define DSC_1_0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS 6 14102 #define DSC_1_0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT 10 14103 14104 /* dsc_1_0 :: dfe_vga_ctrl3 :: vga_cor_sel_e [09:05] */ 14105 #define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_E_MASK 0x03e0 14106 #define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_E_ALIGN 0 14107 #define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_E_BITS 5 14108 #define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_E_SHIFT 5 14109 14110 /* dsc_1_0 :: dfe_vga_ctrl3 :: vga_cor_sel_o [04:00] */ 14111 #define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_O_MASK 0x001f 14112 #define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_O_ALIGN 0 14113 #define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_O_BITS 5 14114 #define DSC_1_0_DFE_VGA_CTRL3_VGA_COR_SEL_O_SHIFT 0 14115 14116 14117 /**************************************************************************** 14118 * dsc_1_0 :: dfe_vga_ctrl4 14119 */ 14120 /* dsc_1_0 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */ 14121 #define DSC_1_0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK 0xfc00 14122 #define DSC_1_0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 14123 #define DSC_1_0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS 6 14124 #define DSC_1_0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT 10 14125 14126 /* dsc_1_0 :: dfe_vga_ctrl4 :: dfe_cor_sel_e [09:05] */ 14127 #define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_E_MASK 0x03e0 14128 #define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_E_ALIGN 0 14129 #define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_E_BITS 5 14130 #define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_E_SHIFT 5 14131 14132 /* dsc_1_0 :: dfe_vga_ctrl4 :: dfe_cor_sel_o [04:00] */ 14133 #define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_O_MASK 0x001f 14134 #define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_O_ALIGN 0 14135 #define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_O_BITS 5 14136 #define DSC_1_0_DFE_VGA_CTRL4_DFE_COR_SEL_O_SHIFT 0 14137 14138 14139 /**************************************************************************** 14140 * dsc_1_0 :: dfe_vga_status0 14141 */ 14142 /* dsc_1_0 :: dfe_vga_status0 :: vga_sum [15:11] */ 14143 #define DSC_1_0_DFE_VGA_STATUS0_VGA_SUM_MASK 0xf800 14144 #define DSC_1_0_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 14145 #define DSC_1_0_DFE_VGA_STATUS0_VGA_SUM_BITS 5 14146 #define DSC_1_0_DFE_VGA_STATUS0_VGA_SUM_SHIFT 11 14147 14148 /* dsc_1_0 :: dfe_vga_status0 :: trnsum [10:00] */ 14149 #define DSC_1_0_DFE_VGA_STATUS0_TRNSUM_MASK 0x07ff 14150 #define DSC_1_0_DFE_VGA_STATUS0_TRNSUM_ALIGN 0 14151 #define DSC_1_0_DFE_VGA_STATUS0_TRNSUM_BITS 11 14152 #define DSC_1_0_DFE_VGA_STATUS0_TRNSUM_SHIFT 0 14153 14154 14155 /**************************************************************************** 14156 * dsc_1_0 :: dfe_vga_status1 14157 */ 14158 /* dsc_1_0 :: dfe_vga_status1 :: odd_dfe_acc [15:06] */ 14159 #define DSC_1_0_DFE_VGA_STATUS1_ODD_DFE_ACC_MASK 0xffc0 14160 #define DSC_1_0_DFE_VGA_STATUS1_ODD_DFE_ACC_ALIGN 0 14161 #define DSC_1_0_DFE_VGA_STATUS1_ODD_DFE_ACC_BITS 10 14162 #define DSC_1_0_DFE_VGA_STATUS1_ODD_DFE_ACC_SHIFT 6 14163 14164 /* dsc_1_0 :: dfe_vga_status1 :: dfe_tap_bin [05:00] */ 14165 #define DSC_1_0_DFE_VGA_STATUS1_DFE_TAP_BIN_MASK 0x003f 14166 #define DSC_1_0_DFE_VGA_STATUS1_DFE_TAP_BIN_ALIGN 0 14167 #define DSC_1_0_DFE_VGA_STATUS1_DFE_TAP_BIN_BITS 6 14168 #define DSC_1_0_DFE_VGA_STATUS1_DFE_TAP_BIN_SHIFT 0 14169 14170 14171 /**************************************************************************** 14172 * dsc_1_0 :: dfe_vga_status2 14173 */ 14174 /* dsc_1_0 :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */ 14175 #define DSC_1_0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK 0xfc00 14176 #define DSC_1_0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 14177 #define DSC_1_0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS 6 14178 #define DSC_1_0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT 10 14179 14180 /* dsc_1_0 :: dfe_vga_status2 :: evn_dfe_acc [09:00] */ 14181 #define DSC_1_0_DFE_VGA_STATUS2_EVN_DFE_ACC_MASK 0x03ff 14182 #define DSC_1_0_DFE_VGA_STATUS2_EVN_DFE_ACC_ALIGN 0 14183 #define DSC_1_0_DFE_VGA_STATUS2_EVN_DFE_ACC_BITS 10 14184 #define DSC_1_0_DFE_VGA_STATUS2_EVN_DFE_ACC_SHIFT 0 14185 14186 14187 /**************************************************************************** 14188 * XGXS16G_USER_dsc_1_1 14189 */ 14190 /**************************************************************************** 14191 * dsc_1_1 :: cdr_ctrl0 14192 */ 14193 /* dsc_1_1 :: cdr_ctrl0 :: reserved_for_eco0 [15:09] */ 14194 #define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO0_MASK 0xfe00 14195 #define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 14196 #define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO0_BITS 7 14197 #define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT 9 14198 14199 /* dsc_1_1 :: cdr_ctrl0 :: cdrbr_bwsel_integ [08:07] */ 14200 #define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_INTEG_MASK 0x0180 14201 #define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_INTEG_ALIGN 0 14202 #define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_INTEG_BITS 2 14203 #define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_INTEG_SHIFT 7 14204 14205 /* dsc_1_1 :: cdr_ctrl0 :: cdrbr_bwsel_prop [06:04] */ 14206 #define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_PROP_MASK 0x0070 14207 #define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_PROP_ALIGN 0 14208 #define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_PROP_BITS 3 14209 #define DSC_1_1_CDR_CTRL0_CDRBR_BWSEL_PROP_SHIFT 4 14210 14211 /* dsc_1_1 :: cdr_ctrl0 :: cdrbr_polarity [03:03] */ 14212 #define DSC_1_1_CDR_CTRL0_CDRBR_POLARITY_MASK 0x0008 14213 #define DSC_1_1_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 14214 #define DSC_1_1_CDR_CTRL0_CDRBR_POLARITY_BITS 1 14215 #define DSC_1_1_CDR_CTRL0_CDRBR_POLARITY_SHIFT 3 14216 14217 /* dsc_1_1 :: cdr_ctrl0 :: cdrbr_third_vec_en [02:02] */ 14218 #define DSC_1_1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0004 14219 #define DSC_1_1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 14220 #define DSC_1_1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 14221 #define DSC_1_1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 2 14222 14223 /* dsc_1_1 :: cdr_ctrl0 :: reserved_for_eco1 [01:00] */ 14224 #define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO1_MASK 0x0003 14225 #define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO1_ALIGN 0 14226 #define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO1_BITS 2 14227 #define DSC_1_1_CDR_CTRL0_RESERVED_FOR_ECO1_SHIFT 0 14228 14229 14230 /**************************************************************************** 14231 * dsc_1_1 :: cdr_ctrl1 14232 */ 14233 /* dsc_1_1 :: cdr_ctrl1 :: reserved_for_eco0 [15:10] */ 14234 #define DSC_1_1_CDR_CTRL1_RESERVED_FOR_ECO0_MASK 0xfc00 14235 #define DSC_1_1_CDR_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 14236 #define DSC_1_1_CDR_CTRL1_RESERVED_FOR_ECO0_BITS 6 14237 #define DSC_1_1_CDR_CTRL1_RESERVED_FOR_ECO0_SHIFT 10 14238 14239 /* dsc_1_1 :: cdr_ctrl1 :: cdr_phase_err_frz [09:09] */ 14240 #define DSC_1_1_CDR_CTRL1_CDR_PHASE_ERR_FRZ_MASK 0x0200 14241 #define DSC_1_1_CDR_CTRL1_CDR_PHASE_ERR_FRZ_ALIGN 0 14242 #define DSC_1_1_CDR_CTRL1_CDR_PHASE_ERR_FRZ_BITS 1 14243 #define DSC_1_1_CDR_CTRL1_CDR_PHASE_ERR_FRZ_SHIFT 9 14244 14245 /* dsc_1_1 :: cdr_ctrl1 :: cdr_integ_reg_clr [08:08] */ 14246 #define DSC_1_1_CDR_CTRL1_CDR_INTEG_REG_CLR_MASK 0x0100 14247 #define DSC_1_1_CDR_CTRL1_CDR_INTEG_REG_CLR_ALIGN 0 14248 #define DSC_1_1_CDR_CTRL1_CDR_INTEG_REG_CLR_BITS 1 14249 #define DSC_1_1_CDR_CTRL1_CDR_INTEG_REG_CLR_SHIFT 8 14250 14251 /* dsc_1_1 :: cdr_ctrl1 :: cdr_freq_override_val [07:03] */ 14252 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0x00f8 14253 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 14254 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 5 14255 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 3 14256 14257 /* dsc_1_1 :: cdr_ctrl1 :: cdr_freq_override_en [02:02] */ 14258 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_MASK 0x0004 14259 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_ALIGN 0 14260 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_BITS 1 14261 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_SHIFT 2 14262 14263 /* dsc_1_1 :: cdr_ctrl1 :: cdr_freq_upd_en [01:01] */ 14264 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_UPD_EN_MASK 0x0002 14265 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_UPD_EN_ALIGN 0 14266 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_UPD_EN_BITS 1 14267 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_UPD_EN_SHIFT 1 14268 14269 /* dsc_1_1 :: cdr_ctrl1 :: cdr_freq_en [00:00] */ 14270 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_EN_MASK 0x0001 14271 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_EN_ALIGN 0 14272 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_EN_BITS 1 14273 #define DSC_1_1_CDR_CTRL1_CDR_FREQ_EN_SHIFT 0 14274 14275 14276 /**************************************************************************** 14277 * dsc_1_1 :: cdr_ctrl2 14278 */ 14279 /* dsc_1_1 :: cdr_ctrl2 :: reserved_for_eco0 [15:14] */ 14280 #define DSC_1_1_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xc000 14281 #define DSC_1_1_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 14282 #define DSC_1_1_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 2 14283 #define DSC_1_1_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 14 14284 14285 /* dsc_1_1 :: cdr_ctrl2 :: cdros_bwsel_prop [13:10] */ 14286 #define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_PROP_MASK 0x3c00 14287 #define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_PROP_ALIGN 0 14288 #define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_PROP_BITS 4 14289 #define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_PROP_SHIFT 10 14290 14291 /* dsc_1_1 :: cdr_ctrl2 :: cdros_bwsel_integ [09:06] */ 14292 #define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_INTEG_MASK 0x03c0 14293 #define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_INTEG_ALIGN 0 14294 #define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_INTEG_BITS 4 14295 #define DSC_1_1_CDR_CTRL2_CDROS_BWSEL_INTEG_SHIFT 6 14296 14297 /* dsc_1_1 :: cdr_ctrl2 :: cdros_falling_edge [05:05] */ 14298 #define DSC_1_1_CDR_CTRL2_CDROS_FALLING_EDGE_MASK 0x0020 14299 #define DSC_1_1_CDR_CTRL2_CDROS_FALLING_EDGE_ALIGN 0 14300 #define DSC_1_1_CDR_CTRL2_CDROS_FALLING_EDGE_BITS 1 14301 #define DSC_1_1_CDR_CTRL2_CDROS_FALLING_EDGE_SHIFT 5 14302 14303 /* dsc_1_1 :: cdr_ctrl2 :: cdros_rising_edge [04:04] */ 14304 #define DSC_1_1_CDR_CTRL2_CDROS_RISING_EDGE_MASK 0x0010 14305 #define DSC_1_1_CDR_CTRL2_CDROS_RISING_EDGE_ALIGN 0 14306 #define DSC_1_1_CDR_CTRL2_CDROS_RISING_EDGE_BITS 1 14307 #define DSC_1_1_CDR_CTRL2_CDROS_RISING_EDGE_SHIFT 4 14308 14309 /* dsc_1_1 :: cdr_ctrl2 :: cdros_phase_sat_ctrl [03:02] */ 14310 #define DSC_1_1_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_MASK 0x000c 14311 #define DSC_1_1_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_ALIGN 0 14312 #define DSC_1_1_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_BITS 2 14313 #define DSC_1_1_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_SHIFT 2 14314 14315 /* dsc_1_1 :: cdr_ctrl2 :: cdros_peak_polarity [01:01] */ 14316 #define DSC_1_1_CDR_CTRL2_CDROS_PEAK_POLARITY_MASK 0x0002 14317 #define DSC_1_1_CDR_CTRL2_CDROS_PEAK_POLARITY_ALIGN 0 14318 #define DSC_1_1_CDR_CTRL2_CDROS_PEAK_POLARITY_BITS 1 14319 #define DSC_1_1_CDR_CTRL2_CDROS_PEAK_POLARITY_SHIFT 1 14320 14321 /* dsc_1_1 :: cdr_ctrl2 :: cdros_zero_polarity [00:00] */ 14322 #define DSC_1_1_CDR_CTRL2_CDROS_ZERO_POLARITY_MASK 0x0001 14323 #define DSC_1_1_CDR_CTRL2_CDROS_ZERO_POLARITY_ALIGN 0 14324 #define DSC_1_1_CDR_CTRL2_CDROS_ZERO_POLARITY_BITS 1 14325 #define DSC_1_1_CDR_CTRL2_CDROS_ZERO_POLARITY_SHIFT 0 14326 14327 14328 /**************************************************************************** 14329 * dsc_1_1 :: cdr_status0 14330 */ 14331 /* dsc_1_1 :: cdr_status0 :: integ_reg [15:00] */ 14332 #define DSC_1_1_CDR_STATUS0_INTEG_REG_MASK 0xffff 14333 #define DSC_1_1_CDR_STATUS0_INTEG_REG_ALIGN 0 14334 #define DSC_1_1_CDR_STATUS0_INTEG_REG_BITS 16 14335 #define DSC_1_1_CDR_STATUS0_INTEG_REG_SHIFT 0 14336 14337 14338 /**************************************************************************** 14339 * dsc_1_1 :: cdr_status1 14340 */ 14341 /* dsc_1_1 :: cdr_status1 :: reserved_for_eco0 [15:06] */ 14342 #define DSC_1_1_CDR_STATUS1_RESERVED_FOR_ECO0_MASK 0xffc0 14343 #define DSC_1_1_CDR_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 14344 #define DSC_1_1_CDR_STATUS1_RESERVED_FOR_ECO0_BITS 10 14345 #define DSC_1_1_CDR_STATUS1_RESERVED_FOR_ECO0_SHIFT 6 14346 14347 /* dsc_1_1 :: cdr_status1 :: phase_err [05:00] */ 14348 #define DSC_1_1_CDR_STATUS1_PHASE_ERR_MASK 0x003f 14349 #define DSC_1_1_CDR_STATUS1_PHASE_ERR_ALIGN 0 14350 #define DSC_1_1_CDR_STATUS1_PHASE_ERR_BITS 6 14351 #define DSC_1_1_CDR_STATUS1_PHASE_ERR_SHIFT 0 14352 14353 14354 /**************************************************************************** 14355 * dsc_1_1 :: pi_ctrl0 14356 */ 14357 /* dsc_1_1 :: pi_ctrl0 :: reserved_for_eco0 [15:11] */ 14358 #define DSC_1_1_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0xf800 14359 #define DSC_1_1_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 14360 #define DSC_1_1_PI_CTRL0_RESERVED_FOR_ECO0_BITS 5 14361 #define DSC_1_1_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 14362 14363 /* dsc_1_1 :: pi_ctrl0 :: pi_phase_invert [10:10] */ 14364 #define DSC_1_1_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0400 14365 #define DSC_1_1_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 14366 #define DSC_1_1_PI_CTRL0_PI_PHASE_INVERT_BITS 1 14367 #define DSC_1_1_PI_CTRL0_PI_PHASE_INVERT_SHIFT 10 14368 14369 /* dsc_1_1 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */ 14370 #define DSC_1_1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK 0x0200 14371 #define DSC_1_1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 14372 #define DSC_1_1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS 1 14373 #define DSC_1_1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT 9 14374 14375 /* dsc_1_1 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */ 14376 #define DSC_1_1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0100 14377 #define DSC_1_1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 14378 #define DSC_1_1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS 1 14379 #define DSC_1_1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT 8 14380 14381 /* dsc_1_1 :: pi_ctrl0 :: pi_phase_dec [07:07] */ 14382 #define DSC_1_1_PI_CTRL0_PI_PHASE_DEC_MASK 0x0080 14383 #define DSC_1_1_PI_CTRL0_PI_PHASE_DEC_ALIGN 0 14384 #define DSC_1_1_PI_CTRL0_PI_PHASE_DEC_BITS 1 14385 #define DSC_1_1_PI_CTRL0_PI_PHASE_DEC_SHIFT 7 14386 14387 /* dsc_1_1 :: pi_ctrl0 :: pi_phase_inc [06:06] */ 14388 #define DSC_1_1_PI_CTRL0_PI_PHASE_INC_MASK 0x0040 14389 #define DSC_1_1_PI_CTRL0_PI_PHASE_INC_ALIGN 0 14390 #define DSC_1_1_PI_CTRL0_PI_PHASE_INC_BITS 1 14391 #define DSC_1_1_PI_CTRL0_PI_PHASE_INC_SHIFT 6 14392 14393 /* dsc_1_1 :: pi_ctrl0 :: pi_phase_strobe [05:05] */ 14394 #define DSC_1_1_PI_CTRL0_PI_PHASE_STROBE_MASK 0x0020 14395 #define DSC_1_1_PI_CTRL0_PI_PHASE_STROBE_ALIGN 0 14396 #define DSC_1_1_PI_CTRL0_PI_PHASE_STROBE_BITS 1 14397 #define DSC_1_1_PI_CTRL0_PI_PHASE_STROBE_SHIFT 5 14398 14399 /* dsc_1_1 :: pi_ctrl0 :: pi_phase_delta [04:01] */ 14400 #define DSC_1_1_PI_CTRL0_PI_PHASE_DELTA_MASK 0x001e 14401 #define DSC_1_1_PI_CTRL0_PI_PHASE_DELTA_ALIGN 0 14402 #define DSC_1_1_PI_CTRL0_PI_PHASE_DELTA_BITS 4 14403 #define DSC_1_1_PI_CTRL0_PI_PHASE_DELTA_SHIFT 1 14404 14405 /* dsc_1_1 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 14406 #define DSC_1_1_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 14407 #define DSC_1_1_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 14408 #define DSC_1_1_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 14409 #define DSC_1_1_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 14410 14411 14412 /**************************************************************************** 14413 * dsc_1_1 :: pi_status0 14414 */ 14415 /* dsc_1_1 :: pi_status0 :: reserved_for_eco0 [15:14] */ 14416 #define DSC_1_1_PI_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 14417 #define DSC_1_1_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 14418 #define DSC_1_1_PI_STATUS0_RESERVED_FOR_ECO0_BITS 2 14419 #define DSC_1_1_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 14420 14421 /* dsc_1_1 :: pi_status0 :: clk90_phase_offset [13:07] */ 14422 #define DSC_1_1_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 14423 #define DSC_1_1_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 14424 #define DSC_1_1_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 14425 #define DSC_1_1_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 14426 14427 /* dsc_1_1 :: pi_status0 :: phase_cntr [06:00] */ 14428 #define DSC_1_1_PI_STATUS0_PHASE_CNTR_MASK 0x007f 14429 #define DSC_1_1_PI_STATUS0_PHASE_CNTR_ALIGN 0 14430 #define DSC_1_1_PI_STATUS0_PHASE_CNTR_BITS 7 14431 #define DSC_1_1_PI_STATUS0_PHASE_CNTR_SHIFT 0 14432 14433 14434 /**************************************************************************** 14435 * dsc_1_1 :: dfe_vga_ctrl0 14436 */ 14437 /* dsc_1_1 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:12] */ 14438 #define DSC_1_1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK 0xf000 14439 #define DSC_1_1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 14440 #define DSC_1_1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS 4 14441 #define DSC_1_1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT 12 14442 14443 /* dsc_1_1 :: dfe_vga_ctrl0 :: trnsum_tap0_only [11:11] */ 14444 #define DSC_1_1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0800 14445 #define DSC_1_1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 14446 #define DSC_1_1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 14447 #define DSC_1_1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 11 14448 14449 /* dsc_1_1 :: dfe_vga_ctrl0 :: sum_m1err [10:10] */ 14450 #define DSC_1_1_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0400 14451 #define DSC_1_1_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 14452 #define DSC_1_1_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 14453 #define DSC_1_1_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 10 14454 14455 /* dsc_1_1 :: dfe_vga_ctrl0 :: dfe_vga_clken [09:09] */ 14456 #define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0200 14457 #define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 14458 #define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 14459 #define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 9 14460 14461 /* dsc_1_1 :: dfe_vga_ctrl0 :: hysteresis_en [08:08] */ 14462 #define DSC_1_1_DFE_VGA_CTRL0_HYSTERESIS_EN_MASK 0x0100 14463 #define DSC_1_1_DFE_VGA_CTRL0_HYSTERESIS_EN_ALIGN 0 14464 #define DSC_1_1_DFE_VGA_CTRL0_HYSTERESIS_EN_BITS 1 14465 #define DSC_1_1_DFE_VGA_CTRL0_HYSTERESIS_EN_SHIFT 8 14466 14467 /* dsc_1_1 :: dfe_vga_ctrl0 :: dfe_vga_write_val [07:02] */ 14468 #define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_MASK 0x00fc 14469 #define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_ALIGN 0 14470 #define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_BITS 6 14471 #define DSC_1_1_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_SHIFT 2 14472 14473 /* dsc_1_1 :: dfe_vga_ctrl0 :: vga_write_en [01:01] */ 14474 #define DSC_1_1_DFE_VGA_CTRL0_VGA_WRITE_EN_MASK 0x0002 14475 #define DSC_1_1_DFE_VGA_CTRL0_VGA_WRITE_EN_ALIGN 0 14476 #define DSC_1_1_DFE_VGA_CTRL0_VGA_WRITE_EN_BITS 1 14477 #define DSC_1_1_DFE_VGA_CTRL0_VGA_WRITE_EN_SHIFT 1 14478 14479 /* dsc_1_1 :: dfe_vga_ctrl0 :: dfe_write_en [00:00] */ 14480 #define DSC_1_1_DFE_VGA_CTRL0_DFE_WRITE_EN_MASK 0x0001 14481 #define DSC_1_1_DFE_VGA_CTRL0_DFE_WRITE_EN_ALIGN 0 14482 #define DSC_1_1_DFE_VGA_CTRL0_DFE_WRITE_EN_BITS 1 14483 #define DSC_1_1_DFE_VGA_CTRL0_DFE_WRITE_EN_SHIFT 0 14484 14485 14486 /**************************************************************************** 14487 * dsc_1_1 :: dfe_vga_ctrl1 14488 */ 14489 /* dsc_1_1 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:15] */ 14490 #define DSC_1_1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 14491 #define DSC_1_1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 14492 #define DSC_1_1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 1 14493 #define DSC_1_1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 14494 14495 /* dsc_1_1 :: dfe_vga_ctrl1 :: trnsum_otap_en [14:08] */ 14496 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_MASK 0x7f00 14497 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_ALIGN 0 14498 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_BITS 7 14499 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_SHIFT 8 14500 14501 /* dsc_1_1 :: dfe_vga_ctrl1 :: trnsum_etap_en [07:01] */ 14502 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_MASK 0x00fe 14503 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_ALIGN 0 14504 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_BITS 7 14505 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_SHIFT 1 14506 14507 /* dsc_1_1 :: dfe_vga_ctrl1 :: trnsum_en [00:00] */ 14508 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_EN_MASK 0x0001 14509 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_EN_ALIGN 0 14510 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_EN_BITS 1 14511 #define DSC_1_1_DFE_VGA_CTRL1_TRNSUM_EN_SHIFT 0 14512 14513 14514 /**************************************************************************** 14515 * dsc_1_1 :: dfe_vga_ctrl2 14516 */ 14517 /* dsc_1_1 :: dfe_vga_ctrl2 :: vga_polarity [15:15] */ 14518 #define DSC_1_1_DFE_VGA_CTRL2_VGA_POLARITY_MASK 0x8000 14519 #define DSC_1_1_DFE_VGA_CTRL2_VGA_POLARITY_ALIGN 0 14520 #define DSC_1_1_DFE_VGA_CTRL2_VGA_POLARITY_BITS 1 14521 #define DSC_1_1_DFE_VGA_CTRL2_VGA_POLARITY_SHIFT 15 14522 14523 /* dsc_1_1 :: dfe_vga_ctrl2 :: dfe_polarity [14:14] */ 14524 #define DSC_1_1_DFE_VGA_CTRL2_DFE_POLARITY_MASK 0x4000 14525 #define DSC_1_1_DFE_VGA_CTRL2_DFE_POLARITY_ALIGN 0 14526 #define DSC_1_1_DFE_VGA_CTRL2_DFE_POLARITY_BITS 1 14527 #define DSC_1_1_DFE_VGA_CTRL2_DFE_POLARITY_SHIFT 14 14528 14529 /* dsc_1_1 :: dfe_vga_ctrl2 :: trnsum_otap_sign [13:07] */ 14530 #define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_MASK 0x3f80 14531 #define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_ALIGN 0 14532 #define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_BITS 7 14533 #define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_SHIFT 7 14534 14535 /* dsc_1_1 :: dfe_vga_ctrl2 :: trnsum_etap_sign [06:00] */ 14536 #define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_MASK 0x007f 14537 #define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_ALIGN 0 14538 #define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_BITS 7 14539 #define DSC_1_1_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_SHIFT 0 14540 14541 14542 /**************************************************************************** 14543 * dsc_1_1 :: dfe_vga_ctrl3 14544 */ 14545 /* dsc_1_1 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:10] */ 14546 #define DSC_1_1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK 0xfc00 14547 #define DSC_1_1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 14548 #define DSC_1_1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS 6 14549 #define DSC_1_1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT 10 14550 14551 /* dsc_1_1 :: dfe_vga_ctrl3 :: vga_cor_sel_e [09:05] */ 14552 #define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_E_MASK 0x03e0 14553 #define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_E_ALIGN 0 14554 #define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_E_BITS 5 14555 #define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_E_SHIFT 5 14556 14557 /* dsc_1_1 :: dfe_vga_ctrl3 :: vga_cor_sel_o [04:00] */ 14558 #define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_O_MASK 0x001f 14559 #define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_O_ALIGN 0 14560 #define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_O_BITS 5 14561 #define DSC_1_1_DFE_VGA_CTRL3_VGA_COR_SEL_O_SHIFT 0 14562 14563 14564 /**************************************************************************** 14565 * dsc_1_1 :: dfe_vga_ctrl4 14566 */ 14567 /* dsc_1_1 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */ 14568 #define DSC_1_1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK 0xfc00 14569 #define DSC_1_1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 14570 #define DSC_1_1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS 6 14571 #define DSC_1_1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT 10 14572 14573 /* dsc_1_1 :: dfe_vga_ctrl4 :: dfe_cor_sel_e [09:05] */ 14574 #define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_E_MASK 0x03e0 14575 #define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_E_ALIGN 0 14576 #define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_E_BITS 5 14577 #define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_E_SHIFT 5 14578 14579 /* dsc_1_1 :: dfe_vga_ctrl4 :: dfe_cor_sel_o [04:00] */ 14580 #define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_O_MASK 0x001f 14581 #define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_O_ALIGN 0 14582 #define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_O_BITS 5 14583 #define DSC_1_1_DFE_VGA_CTRL4_DFE_COR_SEL_O_SHIFT 0 14584 14585 14586 /**************************************************************************** 14587 * dsc_1_1 :: dfe_vga_status0 14588 */ 14589 /* dsc_1_1 :: dfe_vga_status0 :: vga_sum [15:11] */ 14590 #define DSC_1_1_DFE_VGA_STATUS0_VGA_SUM_MASK 0xf800 14591 #define DSC_1_1_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 14592 #define DSC_1_1_DFE_VGA_STATUS0_VGA_SUM_BITS 5 14593 #define DSC_1_1_DFE_VGA_STATUS0_VGA_SUM_SHIFT 11 14594 14595 /* dsc_1_1 :: dfe_vga_status0 :: trnsum [10:00] */ 14596 #define DSC_1_1_DFE_VGA_STATUS0_TRNSUM_MASK 0x07ff 14597 #define DSC_1_1_DFE_VGA_STATUS0_TRNSUM_ALIGN 0 14598 #define DSC_1_1_DFE_VGA_STATUS0_TRNSUM_BITS 11 14599 #define DSC_1_1_DFE_VGA_STATUS0_TRNSUM_SHIFT 0 14600 14601 14602 /**************************************************************************** 14603 * dsc_1_1 :: dfe_vga_status1 14604 */ 14605 /* dsc_1_1 :: dfe_vga_status1 :: odd_dfe_acc [15:06] */ 14606 #define DSC_1_1_DFE_VGA_STATUS1_ODD_DFE_ACC_MASK 0xffc0 14607 #define DSC_1_1_DFE_VGA_STATUS1_ODD_DFE_ACC_ALIGN 0 14608 #define DSC_1_1_DFE_VGA_STATUS1_ODD_DFE_ACC_BITS 10 14609 #define DSC_1_1_DFE_VGA_STATUS1_ODD_DFE_ACC_SHIFT 6 14610 14611 /* dsc_1_1 :: dfe_vga_status1 :: dfe_tap_bin [05:00] */ 14612 #define DSC_1_1_DFE_VGA_STATUS1_DFE_TAP_BIN_MASK 0x003f 14613 #define DSC_1_1_DFE_VGA_STATUS1_DFE_TAP_BIN_ALIGN 0 14614 #define DSC_1_1_DFE_VGA_STATUS1_DFE_TAP_BIN_BITS 6 14615 #define DSC_1_1_DFE_VGA_STATUS1_DFE_TAP_BIN_SHIFT 0 14616 14617 14618 /**************************************************************************** 14619 * dsc_1_1 :: dfe_vga_status2 14620 */ 14621 /* dsc_1_1 :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */ 14622 #define DSC_1_1_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK 0xfc00 14623 #define DSC_1_1_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 14624 #define DSC_1_1_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS 6 14625 #define DSC_1_1_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT 10 14626 14627 /* dsc_1_1 :: dfe_vga_status2 :: evn_dfe_acc [09:00] */ 14628 #define DSC_1_1_DFE_VGA_STATUS2_EVN_DFE_ACC_MASK 0x03ff 14629 #define DSC_1_1_DFE_VGA_STATUS2_EVN_DFE_ACC_ALIGN 0 14630 #define DSC_1_1_DFE_VGA_STATUS2_EVN_DFE_ACC_BITS 10 14631 #define DSC_1_1_DFE_VGA_STATUS2_EVN_DFE_ACC_SHIFT 0 14632 14633 14634 /**************************************************************************** 14635 * XGXS16G_USER_dsc_1_2 14636 */ 14637 /**************************************************************************** 14638 * dsc_1_2 :: cdr_ctrl0 14639 */ 14640 /* dsc_1_2 :: cdr_ctrl0 :: reserved_for_eco0 [15:09] */ 14641 #define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO0_MASK 0xfe00 14642 #define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 14643 #define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO0_BITS 7 14644 #define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT 9 14645 14646 /* dsc_1_2 :: cdr_ctrl0 :: cdrbr_bwsel_integ [08:07] */ 14647 #define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_INTEG_MASK 0x0180 14648 #define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_INTEG_ALIGN 0 14649 #define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_INTEG_BITS 2 14650 #define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_INTEG_SHIFT 7 14651 14652 /* dsc_1_2 :: cdr_ctrl0 :: cdrbr_bwsel_prop [06:04] */ 14653 #define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_PROP_MASK 0x0070 14654 #define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_PROP_ALIGN 0 14655 #define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_PROP_BITS 3 14656 #define DSC_1_2_CDR_CTRL0_CDRBR_BWSEL_PROP_SHIFT 4 14657 14658 /* dsc_1_2 :: cdr_ctrl0 :: cdrbr_polarity [03:03] */ 14659 #define DSC_1_2_CDR_CTRL0_CDRBR_POLARITY_MASK 0x0008 14660 #define DSC_1_2_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 14661 #define DSC_1_2_CDR_CTRL0_CDRBR_POLARITY_BITS 1 14662 #define DSC_1_2_CDR_CTRL0_CDRBR_POLARITY_SHIFT 3 14663 14664 /* dsc_1_2 :: cdr_ctrl0 :: cdrbr_third_vec_en [02:02] */ 14665 #define DSC_1_2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0004 14666 #define DSC_1_2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 14667 #define DSC_1_2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 14668 #define DSC_1_2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 2 14669 14670 /* dsc_1_2 :: cdr_ctrl0 :: reserved_for_eco1 [01:00] */ 14671 #define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO1_MASK 0x0003 14672 #define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO1_ALIGN 0 14673 #define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO1_BITS 2 14674 #define DSC_1_2_CDR_CTRL0_RESERVED_FOR_ECO1_SHIFT 0 14675 14676 14677 /**************************************************************************** 14678 * dsc_1_2 :: cdr_ctrl1 14679 */ 14680 /* dsc_1_2 :: cdr_ctrl1 :: reserved_for_eco0 [15:10] */ 14681 #define DSC_1_2_CDR_CTRL1_RESERVED_FOR_ECO0_MASK 0xfc00 14682 #define DSC_1_2_CDR_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 14683 #define DSC_1_2_CDR_CTRL1_RESERVED_FOR_ECO0_BITS 6 14684 #define DSC_1_2_CDR_CTRL1_RESERVED_FOR_ECO0_SHIFT 10 14685 14686 /* dsc_1_2 :: cdr_ctrl1 :: cdr_phase_err_frz [09:09] */ 14687 #define DSC_1_2_CDR_CTRL1_CDR_PHASE_ERR_FRZ_MASK 0x0200 14688 #define DSC_1_2_CDR_CTRL1_CDR_PHASE_ERR_FRZ_ALIGN 0 14689 #define DSC_1_2_CDR_CTRL1_CDR_PHASE_ERR_FRZ_BITS 1 14690 #define DSC_1_2_CDR_CTRL1_CDR_PHASE_ERR_FRZ_SHIFT 9 14691 14692 /* dsc_1_2 :: cdr_ctrl1 :: cdr_integ_reg_clr [08:08] */ 14693 #define DSC_1_2_CDR_CTRL1_CDR_INTEG_REG_CLR_MASK 0x0100 14694 #define DSC_1_2_CDR_CTRL1_CDR_INTEG_REG_CLR_ALIGN 0 14695 #define DSC_1_2_CDR_CTRL1_CDR_INTEG_REG_CLR_BITS 1 14696 #define DSC_1_2_CDR_CTRL1_CDR_INTEG_REG_CLR_SHIFT 8 14697 14698 /* dsc_1_2 :: cdr_ctrl1 :: cdr_freq_override_val [07:03] */ 14699 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0x00f8 14700 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 14701 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 5 14702 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 3 14703 14704 /* dsc_1_2 :: cdr_ctrl1 :: cdr_freq_override_en [02:02] */ 14705 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_MASK 0x0004 14706 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_ALIGN 0 14707 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_BITS 1 14708 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_SHIFT 2 14709 14710 /* dsc_1_2 :: cdr_ctrl1 :: cdr_freq_upd_en [01:01] */ 14711 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_UPD_EN_MASK 0x0002 14712 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_UPD_EN_ALIGN 0 14713 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_UPD_EN_BITS 1 14714 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_UPD_EN_SHIFT 1 14715 14716 /* dsc_1_2 :: cdr_ctrl1 :: cdr_freq_en [00:00] */ 14717 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_EN_MASK 0x0001 14718 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_EN_ALIGN 0 14719 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_EN_BITS 1 14720 #define DSC_1_2_CDR_CTRL1_CDR_FREQ_EN_SHIFT 0 14721 14722 14723 /**************************************************************************** 14724 * dsc_1_2 :: cdr_ctrl2 14725 */ 14726 /* dsc_1_2 :: cdr_ctrl2 :: reserved_for_eco0 [15:14] */ 14727 #define DSC_1_2_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xc000 14728 #define DSC_1_2_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 14729 #define DSC_1_2_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 2 14730 #define DSC_1_2_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 14 14731 14732 /* dsc_1_2 :: cdr_ctrl2 :: cdros_bwsel_prop [13:10] */ 14733 #define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_PROP_MASK 0x3c00 14734 #define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_PROP_ALIGN 0 14735 #define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_PROP_BITS 4 14736 #define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_PROP_SHIFT 10 14737 14738 /* dsc_1_2 :: cdr_ctrl2 :: cdros_bwsel_integ [09:06] */ 14739 #define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_INTEG_MASK 0x03c0 14740 #define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_INTEG_ALIGN 0 14741 #define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_INTEG_BITS 4 14742 #define DSC_1_2_CDR_CTRL2_CDROS_BWSEL_INTEG_SHIFT 6 14743 14744 /* dsc_1_2 :: cdr_ctrl2 :: cdros_falling_edge [05:05] */ 14745 #define DSC_1_2_CDR_CTRL2_CDROS_FALLING_EDGE_MASK 0x0020 14746 #define DSC_1_2_CDR_CTRL2_CDROS_FALLING_EDGE_ALIGN 0 14747 #define DSC_1_2_CDR_CTRL2_CDROS_FALLING_EDGE_BITS 1 14748 #define DSC_1_2_CDR_CTRL2_CDROS_FALLING_EDGE_SHIFT 5 14749 14750 /* dsc_1_2 :: cdr_ctrl2 :: cdros_rising_edge [04:04] */ 14751 #define DSC_1_2_CDR_CTRL2_CDROS_RISING_EDGE_MASK 0x0010 14752 #define DSC_1_2_CDR_CTRL2_CDROS_RISING_EDGE_ALIGN 0 14753 #define DSC_1_2_CDR_CTRL2_CDROS_RISING_EDGE_BITS 1 14754 #define DSC_1_2_CDR_CTRL2_CDROS_RISING_EDGE_SHIFT 4 14755 14756 /* dsc_1_2 :: cdr_ctrl2 :: cdros_phase_sat_ctrl [03:02] */ 14757 #define DSC_1_2_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_MASK 0x000c 14758 #define DSC_1_2_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_ALIGN 0 14759 #define DSC_1_2_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_BITS 2 14760 #define DSC_1_2_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_SHIFT 2 14761 14762 /* dsc_1_2 :: cdr_ctrl2 :: cdros_peak_polarity [01:01] */ 14763 #define DSC_1_2_CDR_CTRL2_CDROS_PEAK_POLARITY_MASK 0x0002 14764 #define DSC_1_2_CDR_CTRL2_CDROS_PEAK_POLARITY_ALIGN 0 14765 #define DSC_1_2_CDR_CTRL2_CDROS_PEAK_POLARITY_BITS 1 14766 #define DSC_1_2_CDR_CTRL2_CDROS_PEAK_POLARITY_SHIFT 1 14767 14768 /* dsc_1_2 :: cdr_ctrl2 :: cdros_zero_polarity [00:00] */ 14769 #define DSC_1_2_CDR_CTRL2_CDROS_ZERO_POLARITY_MASK 0x0001 14770 #define DSC_1_2_CDR_CTRL2_CDROS_ZERO_POLARITY_ALIGN 0 14771 #define DSC_1_2_CDR_CTRL2_CDROS_ZERO_POLARITY_BITS 1 14772 #define DSC_1_2_CDR_CTRL2_CDROS_ZERO_POLARITY_SHIFT 0 14773 14774 14775 /**************************************************************************** 14776 * dsc_1_2 :: cdr_status0 14777 */ 14778 /* dsc_1_2 :: cdr_status0 :: integ_reg [15:00] */ 14779 #define DSC_1_2_CDR_STATUS0_INTEG_REG_MASK 0xffff 14780 #define DSC_1_2_CDR_STATUS0_INTEG_REG_ALIGN 0 14781 #define DSC_1_2_CDR_STATUS0_INTEG_REG_BITS 16 14782 #define DSC_1_2_CDR_STATUS0_INTEG_REG_SHIFT 0 14783 14784 14785 /**************************************************************************** 14786 * dsc_1_2 :: cdr_status1 14787 */ 14788 /* dsc_1_2 :: cdr_status1 :: reserved_for_eco0 [15:06] */ 14789 #define DSC_1_2_CDR_STATUS1_RESERVED_FOR_ECO0_MASK 0xffc0 14790 #define DSC_1_2_CDR_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 14791 #define DSC_1_2_CDR_STATUS1_RESERVED_FOR_ECO0_BITS 10 14792 #define DSC_1_2_CDR_STATUS1_RESERVED_FOR_ECO0_SHIFT 6 14793 14794 /* dsc_1_2 :: cdr_status1 :: phase_err [05:00] */ 14795 #define DSC_1_2_CDR_STATUS1_PHASE_ERR_MASK 0x003f 14796 #define DSC_1_2_CDR_STATUS1_PHASE_ERR_ALIGN 0 14797 #define DSC_1_2_CDR_STATUS1_PHASE_ERR_BITS 6 14798 #define DSC_1_2_CDR_STATUS1_PHASE_ERR_SHIFT 0 14799 14800 14801 /**************************************************************************** 14802 * dsc_1_2 :: pi_ctrl0 14803 */ 14804 /* dsc_1_2 :: pi_ctrl0 :: reserved_for_eco0 [15:11] */ 14805 #define DSC_1_2_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0xf800 14806 #define DSC_1_2_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 14807 #define DSC_1_2_PI_CTRL0_RESERVED_FOR_ECO0_BITS 5 14808 #define DSC_1_2_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 14809 14810 /* dsc_1_2 :: pi_ctrl0 :: pi_phase_invert [10:10] */ 14811 #define DSC_1_2_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0400 14812 #define DSC_1_2_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 14813 #define DSC_1_2_PI_CTRL0_PI_PHASE_INVERT_BITS 1 14814 #define DSC_1_2_PI_CTRL0_PI_PHASE_INVERT_SHIFT 10 14815 14816 /* dsc_1_2 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */ 14817 #define DSC_1_2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK 0x0200 14818 #define DSC_1_2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 14819 #define DSC_1_2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS 1 14820 #define DSC_1_2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT 9 14821 14822 /* dsc_1_2 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */ 14823 #define DSC_1_2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0100 14824 #define DSC_1_2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 14825 #define DSC_1_2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS 1 14826 #define DSC_1_2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT 8 14827 14828 /* dsc_1_2 :: pi_ctrl0 :: pi_phase_dec [07:07] */ 14829 #define DSC_1_2_PI_CTRL0_PI_PHASE_DEC_MASK 0x0080 14830 #define DSC_1_2_PI_CTRL0_PI_PHASE_DEC_ALIGN 0 14831 #define DSC_1_2_PI_CTRL0_PI_PHASE_DEC_BITS 1 14832 #define DSC_1_2_PI_CTRL0_PI_PHASE_DEC_SHIFT 7 14833 14834 /* dsc_1_2 :: pi_ctrl0 :: pi_phase_inc [06:06] */ 14835 #define DSC_1_2_PI_CTRL0_PI_PHASE_INC_MASK 0x0040 14836 #define DSC_1_2_PI_CTRL0_PI_PHASE_INC_ALIGN 0 14837 #define DSC_1_2_PI_CTRL0_PI_PHASE_INC_BITS 1 14838 #define DSC_1_2_PI_CTRL0_PI_PHASE_INC_SHIFT 6 14839 14840 /* dsc_1_2 :: pi_ctrl0 :: pi_phase_strobe [05:05] */ 14841 #define DSC_1_2_PI_CTRL0_PI_PHASE_STROBE_MASK 0x0020 14842 #define DSC_1_2_PI_CTRL0_PI_PHASE_STROBE_ALIGN 0 14843 #define DSC_1_2_PI_CTRL0_PI_PHASE_STROBE_BITS 1 14844 #define DSC_1_2_PI_CTRL0_PI_PHASE_STROBE_SHIFT 5 14845 14846 /* dsc_1_2 :: pi_ctrl0 :: pi_phase_delta [04:01] */ 14847 #define DSC_1_2_PI_CTRL0_PI_PHASE_DELTA_MASK 0x001e 14848 #define DSC_1_2_PI_CTRL0_PI_PHASE_DELTA_ALIGN 0 14849 #define DSC_1_2_PI_CTRL0_PI_PHASE_DELTA_BITS 4 14850 #define DSC_1_2_PI_CTRL0_PI_PHASE_DELTA_SHIFT 1 14851 14852 /* dsc_1_2 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 14853 #define DSC_1_2_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 14854 #define DSC_1_2_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 14855 #define DSC_1_2_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 14856 #define DSC_1_2_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 14857 14858 14859 /**************************************************************************** 14860 * dsc_1_2 :: pi_status0 14861 */ 14862 /* dsc_1_2 :: pi_status0 :: reserved_for_eco0 [15:14] */ 14863 #define DSC_1_2_PI_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 14864 #define DSC_1_2_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 14865 #define DSC_1_2_PI_STATUS0_RESERVED_FOR_ECO0_BITS 2 14866 #define DSC_1_2_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 14867 14868 /* dsc_1_2 :: pi_status0 :: clk90_phase_offset [13:07] */ 14869 #define DSC_1_2_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 14870 #define DSC_1_2_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 14871 #define DSC_1_2_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 14872 #define DSC_1_2_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 14873 14874 /* dsc_1_2 :: pi_status0 :: phase_cntr [06:00] */ 14875 #define DSC_1_2_PI_STATUS0_PHASE_CNTR_MASK 0x007f 14876 #define DSC_1_2_PI_STATUS0_PHASE_CNTR_ALIGN 0 14877 #define DSC_1_2_PI_STATUS0_PHASE_CNTR_BITS 7 14878 #define DSC_1_2_PI_STATUS0_PHASE_CNTR_SHIFT 0 14879 14880 14881 /**************************************************************************** 14882 * dsc_1_2 :: dfe_vga_ctrl0 14883 */ 14884 /* dsc_1_2 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:12] */ 14885 #define DSC_1_2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK 0xf000 14886 #define DSC_1_2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 14887 #define DSC_1_2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS 4 14888 #define DSC_1_2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT 12 14889 14890 /* dsc_1_2 :: dfe_vga_ctrl0 :: trnsum_tap0_only [11:11] */ 14891 #define DSC_1_2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0800 14892 #define DSC_1_2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 14893 #define DSC_1_2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 14894 #define DSC_1_2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 11 14895 14896 /* dsc_1_2 :: dfe_vga_ctrl0 :: sum_m1err [10:10] */ 14897 #define DSC_1_2_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0400 14898 #define DSC_1_2_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 14899 #define DSC_1_2_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 14900 #define DSC_1_2_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 10 14901 14902 /* dsc_1_2 :: dfe_vga_ctrl0 :: dfe_vga_clken [09:09] */ 14903 #define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0200 14904 #define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 14905 #define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 14906 #define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 9 14907 14908 /* dsc_1_2 :: dfe_vga_ctrl0 :: hysteresis_en [08:08] */ 14909 #define DSC_1_2_DFE_VGA_CTRL0_HYSTERESIS_EN_MASK 0x0100 14910 #define DSC_1_2_DFE_VGA_CTRL0_HYSTERESIS_EN_ALIGN 0 14911 #define DSC_1_2_DFE_VGA_CTRL0_HYSTERESIS_EN_BITS 1 14912 #define DSC_1_2_DFE_VGA_CTRL0_HYSTERESIS_EN_SHIFT 8 14913 14914 /* dsc_1_2 :: dfe_vga_ctrl0 :: dfe_vga_write_val [07:02] */ 14915 #define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_MASK 0x00fc 14916 #define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_ALIGN 0 14917 #define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_BITS 6 14918 #define DSC_1_2_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_SHIFT 2 14919 14920 /* dsc_1_2 :: dfe_vga_ctrl0 :: vga_write_en [01:01] */ 14921 #define DSC_1_2_DFE_VGA_CTRL0_VGA_WRITE_EN_MASK 0x0002 14922 #define DSC_1_2_DFE_VGA_CTRL0_VGA_WRITE_EN_ALIGN 0 14923 #define DSC_1_2_DFE_VGA_CTRL0_VGA_WRITE_EN_BITS 1 14924 #define DSC_1_2_DFE_VGA_CTRL0_VGA_WRITE_EN_SHIFT 1 14925 14926 /* dsc_1_2 :: dfe_vga_ctrl0 :: dfe_write_en [00:00] */ 14927 #define DSC_1_2_DFE_VGA_CTRL0_DFE_WRITE_EN_MASK 0x0001 14928 #define DSC_1_2_DFE_VGA_CTRL0_DFE_WRITE_EN_ALIGN 0 14929 #define DSC_1_2_DFE_VGA_CTRL0_DFE_WRITE_EN_BITS 1 14930 #define DSC_1_2_DFE_VGA_CTRL0_DFE_WRITE_EN_SHIFT 0 14931 14932 14933 /**************************************************************************** 14934 * dsc_1_2 :: dfe_vga_ctrl1 14935 */ 14936 /* dsc_1_2 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:15] */ 14937 #define DSC_1_2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 14938 #define DSC_1_2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 14939 #define DSC_1_2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 1 14940 #define DSC_1_2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 14941 14942 /* dsc_1_2 :: dfe_vga_ctrl1 :: trnsum_otap_en [14:08] */ 14943 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_MASK 0x7f00 14944 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_ALIGN 0 14945 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_BITS 7 14946 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_SHIFT 8 14947 14948 /* dsc_1_2 :: dfe_vga_ctrl1 :: trnsum_etap_en [07:01] */ 14949 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_MASK 0x00fe 14950 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_ALIGN 0 14951 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_BITS 7 14952 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_SHIFT 1 14953 14954 /* dsc_1_2 :: dfe_vga_ctrl1 :: trnsum_en [00:00] */ 14955 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_EN_MASK 0x0001 14956 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_EN_ALIGN 0 14957 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_EN_BITS 1 14958 #define DSC_1_2_DFE_VGA_CTRL1_TRNSUM_EN_SHIFT 0 14959 14960 14961 /**************************************************************************** 14962 * dsc_1_2 :: dfe_vga_ctrl2 14963 */ 14964 /* dsc_1_2 :: dfe_vga_ctrl2 :: vga_polarity [15:15] */ 14965 #define DSC_1_2_DFE_VGA_CTRL2_VGA_POLARITY_MASK 0x8000 14966 #define DSC_1_2_DFE_VGA_CTRL2_VGA_POLARITY_ALIGN 0 14967 #define DSC_1_2_DFE_VGA_CTRL2_VGA_POLARITY_BITS 1 14968 #define DSC_1_2_DFE_VGA_CTRL2_VGA_POLARITY_SHIFT 15 14969 14970 /* dsc_1_2 :: dfe_vga_ctrl2 :: dfe_polarity [14:14] */ 14971 #define DSC_1_2_DFE_VGA_CTRL2_DFE_POLARITY_MASK 0x4000 14972 #define DSC_1_2_DFE_VGA_CTRL2_DFE_POLARITY_ALIGN 0 14973 #define DSC_1_2_DFE_VGA_CTRL2_DFE_POLARITY_BITS 1 14974 #define DSC_1_2_DFE_VGA_CTRL2_DFE_POLARITY_SHIFT 14 14975 14976 /* dsc_1_2 :: dfe_vga_ctrl2 :: trnsum_otap_sign [13:07] */ 14977 #define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_MASK 0x3f80 14978 #define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_ALIGN 0 14979 #define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_BITS 7 14980 #define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_SHIFT 7 14981 14982 /* dsc_1_2 :: dfe_vga_ctrl2 :: trnsum_etap_sign [06:00] */ 14983 #define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_MASK 0x007f 14984 #define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_ALIGN 0 14985 #define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_BITS 7 14986 #define DSC_1_2_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_SHIFT 0 14987 14988 14989 /**************************************************************************** 14990 * dsc_1_2 :: dfe_vga_ctrl3 14991 */ 14992 /* dsc_1_2 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:10] */ 14993 #define DSC_1_2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK 0xfc00 14994 #define DSC_1_2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 14995 #define DSC_1_2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS 6 14996 #define DSC_1_2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT 10 14997 14998 /* dsc_1_2 :: dfe_vga_ctrl3 :: vga_cor_sel_e [09:05] */ 14999 #define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_E_MASK 0x03e0 15000 #define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_E_ALIGN 0 15001 #define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_E_BITS 5 15002 #define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_E_SHIFT 5 15003 15004 /* dsc_1_2 :: dfe_vga_ctrl3 :: vga_cor_sel_o [04:00] */ 15005 #define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_O_MASK 0x001f 15006 #define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_O_ALIGN 0 15007 #define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_O_BITS 5 15008 #define DSC_1_2_DFE_VGA_CTRL3_VGA_COR_SEL_O_SHIFT 0 15009 15010 15011 /**************************************************************************** 15012 * dsc_1_2 :: dfe_vga_ctrl4 15013 */ 15014 /* dsc_1_2 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */ 15015 #define DSC_1_2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK 0xfc00 15016 #define DSC_1_2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 15017 #define DSC_1_2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS 6 15018 #define DSC_1_2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT 10 15019 15020 /* dsc_1_2 :: dfe_vga_ctrl4 :: dfe_cor_sel_e [09:05] */ 15021 #define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_E_MASK 0x03e0 15022 #define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_E_ALIGN 0 15023 #define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_E_BITS 5 15024 #define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_E_SHIFT 5 15025 15026 /* dsc_1_2 :: dfe_vga_ctrl4 :: dfe_cor_sel_o [04:00] */ 15027 #define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_O_MASK 0x001f 15028 #define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_O_ALIGN 0 15029 #define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_O_BITS 5 15030 #define DSC_1_2_DFE_VGA_CTRL4_DFE_COR_SEL_O_SHIFT 0 15031 15032 15033 /**************************************************************************** 15034 * dsc_1_2 :: dfe_vga_status0 15035 */ 15036 /* dsc_1_2 :: dfe_vga_status0 :: vga_sum [15:11] */ 15037 #define DSC_1_2_DFE_VGA_STATUS0_VGA_SUM_MASK 0xf800 15038 #define DSC_1_2_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 15039 #define DSC_1_2_DFE_VGA_STATUS0_VGA_SUM_BITS 5 15040 #define DSC_1_2_DFE_VGA_STATUS0_VGA_SUM_SHIFT 11 15041 15042 /* dsc_1_2 :: dfe_vga_status0 :: trnsum [10:00] */ 15043 #define DSC_1_2_DFE_VGA_STATUS0_TRNSUM_MASK 0x07ff 15044 #define DSC_1_2_DFE_VGA_STATUS0_TRNSUM_ALIGN 0 15045 #define DSC_1_2_DFE_VGA_STATUS0_TRNSUM_BITS 11 15046 #define DSC_1_2_DFE_VGA_STATUS0_TRNSUM_SHIFT 0 15047 15048 15049 /**************************************************************************** 15050 * dsc_1_2 :: dfe_vga_status1 15051 */ 15052 /* dsc_1_2 :: dfe_vga_status1 :: odd_dfe_acc [15:06] */ 15053 #define DSC_1_2_DFE_VGA_STATUS1_ODD_DFE_ACC_MASK 0xffc0 15054 #define DSC_1_2_DFE_VGA_STATUS1_ODD_DFE_ACC_ALIGN 0 15055 #define DSC_1_2_DFE_VGA_STATUS1_ODD_DFE_ACC_BITS 10 15056 #define DSC_1_2_DFE_VGA_STATUS1_ODD_DFE_ACC_SHIFT 6 15057 15058 /* dsc_1_2 :: dfe_vga_status1 :: dfe_tap_bin [05:00] */ 15059 #define DSC_1_2_DFE_VGA_STATUS1_DFE_TAP_BIN_MASK 0x003f 15060 #define DSC_1_2_DFE_VGA_STATUS1_DFE_TAP_BIN_ALIGN 0 15061 #define DSC_1_2_DFE_VGA_STATUS1_DFE_TAP_BIN_BITS 6 15062 #define DSC_1_2_DFE_VGA_STATUS1_DFE_TAP_BIN_SHIFT 0 15063 15064 15065 /**************************************************************************** 15066 * dsc_1_2 :: dfe_vga_status2 15067 */ 15068 /* dsc_1_2 :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */ 15069 #define DSC_1_2_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK 0xfc00 15070 #define DSC_1_2_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 15071 #define DSC_1_2_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS 6 15072 #define DSC_1_2_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT 10 15073 15074 /* dsc_1_2 :: dfe_vga_status2 :: evn_dfe_acc [09:00] */ 15075 #define DSC_1_2_DFE_VGA_STATUS2_EVN_DFE_ACC_MASK 0x03ff 15076 #define DSC_1_2_DFE_VGA_STATUS2_EVN_DFE_ACC_ALIGN 0 15077 #define DSC_1_2_DFE_VGA_STATUS2_EVN_DFE_ACC_BITS 10 15078 #define DSC_1_2_DFE_VGA_STATUS2_EVN_DFE_ACC_SHIFT 0 15079 15080 15081 /**************************************************************************** 15082 * XGXS16G_USER_dsc_1_3 15083 */ 15084 /**************************************************************************** 15085 * dsc_1_3 :: cdr_ctrl0 15086 */ 15087 /* dsc_1_3 :: cdr_ctrl0 :: reserved_for_eco0 [15:09] */ 15088 #define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO0_MASK 0xfe00 15089 #define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 15090 #define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO0_BITS 7 15091 #define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT 9 15092 15093 /* dsc_1_3 :: cdr_ctrl0 :: cdrbr_bwsel_integ [08:07] */ 15094 #define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_INTEG_MASK 0x0180 15095 #define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_INTEG_ALIGN 0 15096 #define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_INTEG_BITS 2 15097 #define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_INTEG_SHIFT 7 15098 15099 /* dsc_1_3 :: cdr_ctrl0 :: cdrbr_bwsel_prop [06:04] */ 15100 #define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_PROP_MASK 0x0070 15101 #define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_PROP_ALIGN 0 15102 #define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_PROP_BITS 3 15103 #define DSC_1_3_CDR_CTRL0_CDRBR_BWSEL_PROP_SHIFT 4 15104 15105 /* dsc_1_3 :: cdr_ctrl0 :: cdrbr_polarity [03:03] */ 15106 #define DSC_1_3_CDR_CTRL0_CDRBR_POLARITY_MASK 0x0008 15107 #define DSC_1_3_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 15108 #define DSC_1_3_CDR_CTRL0_CDRBR_POLARITY_BITS 1 15109 #define DSC_1_3_CDR_CTRL0_CDRBR_POLARITY_SHIFT 3 15110 15111 /* dsc_1_3 :: cdr_ctrl0 :: cdrbr_third_vec_en [02:02] */ 15112 #define DSC_1_3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0004 15113 #define DSC_1_3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 15114 #define DSC_1_3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 15115 #define DSC_1_3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 2 15116 15117 /* dsc_1_3 :: cdr_ctrl0 :: reserved_for_eco1 [01:00] */ 15118 #define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO1_MASK 0x0003 15119 #define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO1_ALIGN 0 15120 #define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO1_BITS 2 15121 #define DSC_1_3_CDR_CTRL0_RESERVED_FOR_ECO1_SHIFT 0 15122 15123 15124 /**************************************************************************** 15125 * dsc_1_3 :: cdr_ctrl1 15126 */ 15127 /* dsc_1_3 :: cdr_ctrl1 :: reserved_for_eco0 [15:10] */ 15128 #define DSC_1_3_CDR_CTRL1_RESERVED_FOR_ECO0_MASK 0xfc00 15129 #define DSC_1_3_CDR_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 15130 #define DSC_1_3_CDR_CTRL1_RESERVED_FOR_ECO0_BITS 6 15131 #define DSC_1_3_CDR_CTRL1_RESERVED_FOR_ECO0_SHIFT 10 15132 15133 /* dsc_1_3 :: cdr_ctrl1 :: cdr_phase_err_frz [09:09] */ 15134 #define DSC_1_3_CDR_CTRL1_CDR_PHASE_ERR_FRZ_MASK 0x0200 15135 #define DSC_1_3_CDR_CTRL1_CDR_PHASE_ERR_FRZ_ALIGN 0 15136 #define DSC_1_3_CDR_CTRL1_CDR_PHASE_ERR_FRZ_BITS 1 15137 #define DSC_1_3_CDR_CTRL1_CDR_PHASE_ERR_FRZ_SHIFT 9 15138 15139 /* dsc_1_3 :: cdr_ctrl1 :: cdr_integ_reg_clr [08:08] */ 15140 #define DSC_1_3_CDR_CTRL1_CDR_INTEG_REG_CLR_MASK 0x0100 15141 #define DSC_1_3_CDR_CTRL1_CDR_INTEG_REG_CLR_ALIGN 0 15142 #define DSC_1_3_CDR_CTRL1_CDR_INTEG_REG_CLR_BITS 1 15143 #define DSC_1_3_CDR_CTRL1_CDR_INTEG_REG_CLR_SHIFT 8 15144 15145 /* dsc_1_3 :: cdr_ctrl1 :: cdr_freq_override_val [07:03] */ 15146 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0x00f8 15147 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 15148 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 5 15149 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 3 15150 15151 /* dsc_1_3 :: cdr_ctrl1 :: cdr_freq_override_en [02:02] */ 15152 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_MASK 0x0004 15153 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_ALIGN 0 15154 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_BITS 1 15155 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_SHIFT 2 15156 15157 /* dsc_1_3 :: cdr_ctrl1 :: cdr_freq_upd_en [01:01] */ 15158 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_UPD_EN_MASK 0x0002 15159 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_UPD_EN_ALIGN 0 15160 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_UPD_EN_BITS 1 15161 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_UPD_EN_SHIFT 1 15162 15163 /* dsc_1_3 :: cdr_ctrl1 :: cdr_freq_en [00:00] */ 15164 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_EN_MASK 0x0001 15165 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_EN_ALIGN 0 15166 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_EN_BITS 1 15167 #define DSC_1_3_CDR_CTRL1_CDR_FREQ_EN_SHIFT 0 15168 15169 15170 /**************************************************************************** 15171 * dsc_1_3 :: cdr_ctrl2 15172 */ 15173 /* dsc_1_3 :: cdr_ctrl2 :: reserved_for_eco0 [15:14] */ 15174 #define DSC_1_3_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xc000 15175 #define DSC_1_3_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 15176 #define DSC_1_3_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 2 15177 #define DSC_1_3_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 14 15178 15179 /* dsc_1_3 :: cdr_ctrl2 :: cdros_bwsel_prop [13:10] */ 15180 #define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_PROP_MASK 0x3c00 15181 #define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_PROP_ALIGN 0 15182 #define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_PROP_BITS 4 15183 #define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_PROP_SHIFT 10 15184 15185 /* dsc_1_3 :: cdr_ctrl2 :: cdros_bwsel_integ [09:06] */ 15186 #define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_INTEG_MASK 0x03c0 15187 #define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_INTEG_ALIGN 0 15188 #define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_INTEG_BITS 4 15189 #define DSC_1_3_CDR_CTRL2_CDROS_BWSEL_INTEG_SHIFT 6 15190 15191 /* dsc_1_3 :: cdr_ctrl2 :: cdros_falling_edge [05:05] */ 15192 #define DSC_1_3_CDR_CTRL2_CDROS_FALLING_EDGE_MASK 0x0020 15193 #define DSC_1_3_CDR_CTRL2_CDROS_FALLING_EDGE_ALIGN 0 15194 #define DSC_1_3_CDR_CTRL2_CDROS_FALLING_EDGE_BITS 1 15195 #define DSC_1_3_CDR_CTRL2_CDROS_FALLING_EDGE_SHIFT 5 15196 15197 /* dsc_1_3 :: cdr_ctrl2 :: cdros_rising_edge [04:04] */ 15198 #define DSC_1_3_CDR_CTRL2_CDROS_RISING_EDGE_MASK 0x0010 15199 #define DSC_1_3_CDR_CTRL2_CDROS_RISING_EDGE_ALIGN 0 15200 #define DSC_1_3_CDR_CTRL2_CDROS_RISING_EDGE_BITS 1 15201 #define DSC_1_3_CDR_CTRL2_CDROS_RISING_EDGE_SHIFT 4 15202 15203 /* dsc_1_3 :: cdr_ctrl2 :: cdros_phase_sat_ctrl [03:02] */ 15204 #define DSC_1_3_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_MASK 0x000c 15205 #define DSC_1_3_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_ALIGN 0 15206 #define DSC_1_3_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_BITS 2 15207 #define DSC_1_3_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_SHIFT 2 15208 15209 /* dsc_1_3 :: cdr_ctrl2 :: cdros_peak_polarity [01:01] */ 15210 #define DSC_1_3_CDR_CTRL2_CDROS_PEAK_POLARITY_MASK 0x0002 15211 #define DSC_1_3_CDR_CTRL2_CDROS_PEAK_POLARITY_ALIGN 0 15212 #define DSC_1_3_CDR_CTRL2_CDROS_PEAK_POLARITY_BITS 1 15213 #define DSC_1_3_CDR_CTRL2_CDROS_PEAK_POLARITY_SHIFT 1 15214 15215 /* dsc_1_3 :: cdr_ctrl2 :: cdros_zero_polarity [00:00] */ 15216 #define DSC_1_3_CDR_CTRL2_CDROS_ZERO_POLARITY_MASK 0x0001 15217 #define DSC_1_3_CDR_CTRL2_CDROS_ZERO_POLARITY_ALIGN 0 15218 #define DSC_1_3_CDR_CTRL2_CDROS_ZERO_POLARITY_BITS 1 15219 #define DSC_1_3_CDR_CTRL2_CDROS_ZERO_POLARITY_SHIFT 0 15220 15221 15222 /**************************************************************************** 15223 * dsc_1_3 :: cdr_status0 15224 */ 15225 /* dsc_1_3 :: cdr_status0 :: integ_reg [15:00] */ 15226 #define DSC_1_3_CDR_STATUS0_INTEG_REG_MASK 0xffff 15227 #define DSC_1_3_CDR_STATUS0_INTEG_REG_ALIGN 0 15228 #define DSC_1_3_CDR_STATUS0_INTEG_REG_BITS 16 15229 #define DSC_1_3_CDR_STATUS0_INTEG_REG_SHIFT 0 15230 15231 15232 /**************************************************************************** 15233 * dsc_1_3 :: cdr_status1 15234 */ 15235 /* dsc_1_3 :: cdr_status1 :: reserved_for_eco0 [15:06] */ 15236 #define DSC_1_3_CDR_STATUS1_RESERVED_FOR_ECO0_MASK 0xffc0 15237 #define DSC_1_3_CDR_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 15238 #define DSC_1_3_CDR_STATUS1_RESERVED_FOR_ECO0_BITS 10 15239 #define DSC_1_3_CDR_STATUS1_RESERVED_FOR_ECO0_SHIFT 6 15240 15241 /* dsc_1_3 :: cdr_status1 :: phase_err [05:00] */ 15242 #define DSC_1_3_CDR_STATUS1_PHASE_ERR_MASK 0x003f 15243 #define DSC_1_3_CDR_STATUS1_PHASE_ERR_ALIGN 0 15244 #define DSC_1_3_CDR_STATUS1_PHASE_ERR_BITS 6 15245 #define DSC_1_3_CDR_STATUS1_PHASE_ERR_SHIFT 0 15246 15247 15248 /**************************************************************************** 15249 * dsc_1_3 :: pi_ctrl0 15250 */ 15251 /* dsc_1_3 :: pi_ctrl0 :: reserved_for_eco0 [15:11] */ 15252 #define DSC_1_3_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0xf800 15253 #define DSC_1_3_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 15254 #define DSC_1_3_PI_CTRL0_RESERVED_FOR_ECO0_BITS 5 15255 #define DSC_1_3_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 15256 15257 /* dsc_1_3 :: pi_ctrl0 :: pi_phase_invert [10:10] */ 15258 #define DSC_1_3_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0400 15259 #define DSC_1_3_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 15260 #define DSC_1_3_PI_CTRL0_PI_PHASE_INVERT_BITS 1 15261 #define DSC_1_3_PI_CTRL0_PI_PHASE_INVERT_SHIFT 10 15262 15263 /* dsc_1_3 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */ 15264 #define DSC_1_3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK 0x0200 15265 #define DSC_1_3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 15266 #define DSC_1_3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS 1 15267 #define DSC_1_3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT 9 15268 15269 /* dsc_1_3 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */ 15270 #define DSC_1_3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0100 15271 #define DSC_1_3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 15272 #define DSC_1_3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS 1 15273 #define DSC_1_3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT 8 15274 15275 /* dsc_1_3 :: pi_ctrl0 :: pi_phase_dec [07:07] */ 15276 #define DSC_1_3_PI_CTRL0_PI_PHASE_DEC_MASK 0x0080 15277 #define DSC_1_3_PI_CTRL0_PI_PHASE_DEC_ALIGN 0 15278 #define DSC_1_3_PI_CTRL0_PI_PHASE_DEC_BITS 1 15279 #define DSC_1_3_PI_CTRL0_PI_PHASE_DEC_SHIFT 7 15280 15281 /* dsc_1_3 :: pi_ctrl0 :: pi_phase_inc [06:06] */ 15282 #define DSC_1_3_PI_CTRL0_PI_PHASE_INC_MASK 0x0040 15283 #define DSC_1_3_PI_CTRL0_PI_PHASE_INC_ALIGN 0 15284 #define DSC_1_3_PI_CTRL0_PI_PHASE_INC_BITS 1 15285 #define DSC_1_3_PI_CTRL0_PI_PHASE_INC_SHIFT 6 15286 15287 /* dsc_1_3 :: pi_ctrl0 :: pi_phase_strobe [05:05] */ 15288 #define DSC_1_3_PI_CTRL0_PI_PHASE_STROBE_MASK 0x0020 15289 #define DSC_1_3_PI_CTRL0_PI_PHASE_STROBE_ALIGN 0 15290 #define DSC_1_3_PI_CTRL0_PI_PHASE_STROBE_BITS 1 15291 #define DSC_1_3_PI_CTRL0_PI_PHASE_STROBE_SHIFT 5 15292 15293 /* dsc_1_3 :: pi_ctrl0 :: pi_phase_delta [04:01] */ 15294 #define DSC_1_3_PI_CTRL0_PI_PHASE_DELTA_MASK 0x001e 15295 #define DSC_1_3_PI_CTRL0_PI_PHASE_DELTA_ALIGN 0 15296 #define DSC_1_3_PI_CTRL0_PI_PHASE_DELTA_BITS 4 15297 #define DSC_1_3_PI_CTRL0_PI_PHASE_DELTA_SHIFT 1 15298 15299 /* dsc_1_3 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 15300 #define DSC_1_3_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 15301 #define DSC_1_3_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 15302 #define DSC_1_3_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 15303 #define DSC_1_3_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 15304 15305 15306 /**************************************************************************** 15307 * dsc_1_3 :: pi_status0 15308 */ 15309 /* dsc_1_3 :: pi_status0 :: reserved_for_eco0 [15:14] */ 15310 #define DSC_1_3_PI_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 15311 #define DSC_1_3_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 15312 #define DSC_1_3_PI_STATUS0_RESERVED_FOR_ECO0_BITS 2 15313 #define DSC_1_3_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 15314 15315 /* dsc_1_3 :: pi_status0 :: clk90_phase_offset [13:07] */ 15316 #define DSC_1_3_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 15317 #define DSC_1_3_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 15318 #define DSC_1_3_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 15319 #define DSC_1_3_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 15320 15321 /* dsc_1_3 :: pi_status0 :: phase_cntr [06:00] */ 15322 #define DSC_1_3_PI_STATUS0_PHASE_CNTR_MASK 0x007f 15323 #define DSC_1_3_PI_STATUS0_PHASE_CNTR_ALIGN 0 15324 #define DSC_1_3_PI_STATUS0_PHASE_CNTR_BITS 7 15325 #define DSC_1_3_PI_STATUS0_PHASE_CNTR_SHIFT 0 15326 15327 15328 /**************************************************************************** 15329 * dsc_1_3 :: dfe_vga_ctrl0 15330 */ 15331 /* dsc_1_3 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:12] */ 15332 #define DSC_1_3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK 0xf000 15333 #define DSC_1_3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 15334 #define DSC_1_3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS 4 15335 #define DSC_1_3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT 12 15336 15337 /* dsc_1_3 :: dfe_vga_ctrl0 :: trnsum_tap0_only [11:11] */ 15338 #define DSC_1_3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0800 15339 #define DSC_1_3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 15340 #define DSC_1_3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 15341 #define DSC_1_3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 11 15342 15343 /* dsc_1_3 :: dfe_vga_ctrl0 :: sum_m1err [10:10] */ 15344 #define DSC_1_3_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0400 15345 #define DSC_1_3_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 15346 #define DSC_1_3_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 15347 #define DSC_1_3_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 10 15348 15349 /* dsc_1_3 :: dfe_vga_ctrl0 :: dfe_vga_clken [09:09] */ 15350 #define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0200 15351 #define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 15352 #define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 15353 #define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 9 15354 15355 /* dsc_1_3 :: dfe_vga_ctrl0 :: hysteresis_en [08:08] */ 15356 #define DSC_1_3_DFE_VGA_CTRL0_HYSTERESIS_EN_MASK 0x0100 15357 #define DSC_1_3_DFE_VGA_CTRL0_HYSTERESIS_EN_ALIGN 0 15358 #define DSC_1_3_DFE_VGA_CTRL0_HYSTERESIS_EN_BITS 1 15359 #define DSC_1_3_DFE_VGA_CTRL0_HYSTERESIS_EN_SHIFT 8 15360 15361 /* dsc_1_3 :: dfe_vga_ctrl0 :: dfe_vga_write_val [07:02] */ 15362 #define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_MASK 0x00fc 15363 #define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_ALIGN 0 15364 #define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_BITS 6 15365 #define DSC_1_3_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_SHIFT 2 15366 15367 /* dsc_1_3 :: dfe_vga_ctrl0 :: vga_write_en [01:01] */ 15368 #define DSC_1_3_DFE_VGA_CTRL0_VGA_WRITE_EN_MASK 0x0002 15369 #define DSC_1_3_DFE_VGA_CTRL0_VGA_WRITE_EN_ALIGN 0 15370 #define DSC_1_3_DFE_VGA_CTRL0_VGA_WRITE_EN_BITS 1 15371 #define DSC_1_3_DFE_VGA_CTRL0_VGA_WRITE_EN_SHIFT 1 15372 15373 /* dsc_1_3 :: dfe_vga_ctrl0 :: dfe_write_en [00:00] */ 15374 #define DSC_1_3_DFE_VGA_CTRL0_DFE_WRITE_EN_MASK 0x0001 15375 #define DSC_1_3_DFE_VGA_CTRL0_DFE_WRITE_EN_ALIGN 0 15376 #define DSC_1_3_DFE_VGA_CTRL0_DFE_WRITE_EN_BITS 1 15377 #define DSC_1_3_DFE_VGA_CTRL0_DFE_WRITE_EN_SHIFT 0 15378 15379 15380 /**************************************************************************** 15381 * dsc_1_3 :: dfe_vga_ctrl1 15382 */ 15383 /* dsc_1_3 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:15] */ 15384 #define DSC_1_3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 15385 #define DSC_1_3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 15386 #define DSC_1_3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 1 15387 #define DSC_1_3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 15388 15389 /* dsc_1_3 :: dfe_vga_ctrl1 :: trnsum_otap_en [14:08] */ 15390 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_MASK 0x7f00 15391 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_ALIGN 0 15392 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_BITS 7 15393 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_SHIFT 8 15394 15395 /* dsc_1_3 :: dfe_vga_ctrl1 :: trnsum_etap_en [07:01] */ 15396 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_MASK 0x00fe 15397 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_ALIGN 0 15398 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_BITS 7 15399 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_SHIFT 1 15400 15401 /* dsc_1_3 :: dfe_vga_ctrl1 :: trnsum_en [00:00] */ 15402 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_EN_MASK 0x0001 15403 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_EN_ALIGN 0 15404 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_EN_BITS 1 15405 #define DSC_1_3_DFE_VGA_CTRL1_TRNSUM_EN_SHIFT 0 15406 15407 15408 /**************************************************************************** 15409 * dsc_1_3 :: dfe_vga_ctrl2 15410 */ 15411 /* dsc_1_3 :: dfe_vga_ctrl2 :: vga_polarity [15:15] */ 15412 #define DSC_1_3_DFE_VGA_CTRL2_VGA_POLARITY_MASK 0x8000 15413 #define DSC_1_3_DFE_VGA_CTRL2_VGA_POLARITY_ALIGN 0 15414 #define DSC_1_3_DFE_VGA_CTRL2_VGA_POLARITY_BITS 1 15415 #define DSC_1_3_DFE_VGA_CTRL2_VGA_POLARITY_SHIFT 15 15416 15417 /* dsc_1_3 :: dfe_vga_ctrl2 :: dfe_polarity [14:14] */ 15418 #define DSC_1_3_DFE_VGA_CTRL2_DFE_POLARITY_MASK 0x4000 15419 #define DSC_1_3_DFE_VGA_CTRL2_DFE_POLARITY_ALIGN 0 15420 #define DSC_1_3_DFE_VGA_CTRL2_DFE_POLARITY_BITS 1 15421 #define DSC_1_3_DFE_VGA_CTRL2_DFE_POLARITY_SHIFT 14 15422 15423 /* dsc_1_3 :: dfe_vga_ctrl2 :: trnsum_otap_sign [13:07] */ 15424 #define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_MASK 0x3f80 15425 #define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_ALIGN 0 15426 #define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_BITS 7 15427 #define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_SHIFT 7 15428 15429 /* dsc_1_3 :: dfe_vga_ctrl2 :: trnsum_etap_sign [06:00] */ 15430 #define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_MASK 0x007f 15431 #define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_ALIGN 0 15432 #define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_BITS 7 15433 #define DSC_1_3_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_SHIFT 0 15434 15435 15436 /**************************************************************************** 15437 * dsc_1_3 :: dfe_vga_ctrl3 15438 */ 15439 /* dsc_1_3 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:10] */ 15440 #define DSC_1_3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK 0xfc00 15441 #define DSC_1_3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 15442 #define DSC_1_3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS 6 15443 #define DSC_1_3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT 10 15444 15445 /* dsc_1_3 :: dfe_vga_ctrl3 :: vga_cor_sel_e [09:05] */ 15446 #define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_E_MASK 0x03e0 15447 #define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_E_ALIGN 0 15448 #define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_E_BITS 5 15449 #define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_E_SHIFT 5 15450 15451 /* dsc_1_3 :: dfe_vga_ctrl3 :: vga_cor_sel_o [04:00] */ 15452 #define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_O_MASK 0x001f 15453 #define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_O_ALIGN 0 15454 #define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_O_BITS 5 15455 #define DSC_1_3_DFE_VGA_CTRL3_VGA_COR_SEL_O_SHIFT 0 15456 15457 15458 /**************************************************************************** 15459 * dsc_1_3 :: dfe_vga_ctrl4 15460 */ 15461 /* dsc_1_3 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */ 15462 #define DSC_1_3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK 0xfc00 15463 #define DSC_1_3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 15464 #define DSC_1_3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS 6 15465 #define DSC_1_3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT 10 15466 15467 /* dsc_1_3 :: dfe_vga_ctrl4 :: dfe_cor_sel_e [09:05] */ 15468 #define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_E_MASK 0x03e0 15469 #define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_E_ALIGN 0 15470 #define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_E_BITS 5 15471 #define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_E_SHIFT 5 15472 15473 /* dsc_1_3 :: dfe_vga_ctrl4 :: dfe_cor_sel_o [04:00] */ 15474 #define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_O_MASK 0x001f 15475 #define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_O_ALIGN 0 15476 #define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_O_BITS 5 15477 #define DSC_1_3_DFE_VGA_CTRL4_DFE_COR_SEL_O_SHIFT 0 15478 15479 15480 /**************************************************************************** 15481 * dsc_1_3 :: dfe_vga_status0 15482 */ 15483 /* dsc_1_3 :: dfe_vga_status0 :: vga_sum [15:11] */ 15484 #define DSC_1_3_DFE_VGA_STATUS0_VGA_SUM_MASK 0xf800 15485 #define DSC_1_3_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 15486 #define DSC_1_3_DFE_VGA_STATUS0_VGA_SUM_BITS 5 15487 #define DSC_1_3_DFE_VGA_STATUS0_VGA_SUM_SHIFT 11 15488 15489 /* dsc_1_3 :: dfe_vga_status0 :: trnsum [10:00] */ 15490 #define DSC_1_3_DFE_VGA_STATUS0_TRNSUM_MASK 0x07ff 15491 #define DSC_1_3_DFE_VGA_STATUS0_TRNSUM_ALIGN 0 15492 #define DSC_1_3_DFE_VGA_STATUS0_TRNSUM_BITS 11 15493 #define DSC_1_3_DFE_VGA_STATUS0_TRNSUM_SHIFT 0 15494 15495 15496 /**************************************************************************** 15497 * dsc_1_3 :: dfe_vga_status1 15498 */ 15499 /* dsc_1_3 :: dfe_vga_status1 :: odd_dfe_acc [15:06] */ 15500 #define DSC_1_3_DFE_VGA_STATUS1_ODD_DFE_ACC_MASK 0xffc0 15501 #define DSC_1_3_DFE_VGA_STATUS1_ODD_DFE_ACC_ALIGN 0 15502 #define DSC_1_3_DFE_VGA_STATUS1_ODD_DFE_ACC_BITS 10 15503 #define DSC_1_3_DFE_VGA_STATUS1_ODD_DFE_ACC_SHIFT 6 15504 15505 /* dsc_1_3 :: dfe_vga_status1 :: dfe_tap_bin [05:00] */ 15506 #define DSC_1_3_DFE_VGA_STATUS1_DFE_TAP_BIN_MASK 0x003f 15507 #define DSC_1_3_DFE_VGA_STATUS1_DFE_TAP_BIN_ALIGN 0 15508 #define DSC_1_3_DFE_VGA_STATUS1_DFE_TAP_BIN_BITS 6 15509 #define DSC_1_3_DFE_VGA_STATUS1_DFE_TAP_BIN_SHIFT 0 15510 15511 15512 /**************************************************************************** 15513 * dsc_1_3 :: dfe_vga_status2 15514 */ 15515 /* dsc_1_3 :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */ 15516 #define DSC_1_3_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK 0xfc00 15517 #define DSC_1_3_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 15518 #define DSC_1_3_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS 6 15519 #define DSC_1_3_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT 10 15520 15521 /* dsc_1_3 :: dfe_vga_status2 :: evn_dfe_acc [09:00] */ 15522 #define DSC_1_3_DFE_VGA_STATUS2_EVN_DFE_ACC_MASK 0x03ff 15523 #define DSC_1_3_DFE_VGA_STATUS2_EVN_DFE_ACC_ALIGN 0 15524 #define DSC_1_3_DFE_VGA_STATUS2_EVN_DFE_ACC_BITS 10 15525 #define DSC_1_3_DFE_VGA_STATUS2_EVN_DFE_ACC_SHIFT 0 15526 15527 15528 /**************************************************************************** 15529 * XGXS16G_USER_dsc_1_A 15530 */ 15531 /**************************************************************************** 15532 * dsc_1_A :: cdr_ctrl0 15533 */ 15534 /* dsc_1_A :: cdr_ctrl0 :: reserved_for_eco0 [15:09] */ 15535 #define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO0_MASK 0xfe00 15536 #define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 15537 #define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO0_BITS 7 15538 #define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT 9 15539 15540 /* dsc_1_A :: cdr_ctrl0 :: cdrbr_bwsel_integ [08:07] */ 15541 #define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_INTEG_MASK 0x0180 15542 #define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_INTEG_ALIGN 0 15543 #define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_INTEG_BITS 2 15544 #define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_INTEG_SHIFT 7 15545 15546 /* dsc_1_A :: cdr_ctrl0 :: cdrbr_bwsel_prop [06:04] */ 15547 #define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_PROP_MASK 0x0070 15548 #define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_PROP_ALIGN 0 15549 #define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_PROP_BITS 3 15550 #define DSC_1_A_CDR_CTRL0_CDRBR_BWSEL_PROP_SHIFT 4 15551 15552 /* dsc_1_A :: cdr_ctrl0 :: cdrbr_polarity [03:03] */ 15553 #define DSC_1_A_CDR_CTRL0_CDRBR_POLARITY_MASK 0x0008 15554 #define DSC_1_A_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 15555 #define DSC_1_A_CDR_CTRL0_CDRBR_POLARITY_BITS 1 15556 #define DSC_1_A_CDR_CTRL0_CDRBR_POLARITY_SHIFT 3 15557 15558 /* dsc_1_A :: cdr_ctrl0 :: cdrbr_third_vec_en [02:02] */ 15559 #define DSC_1_A_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0004 15560 #define DSC_1_A_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 15561 #define DSC_1_A_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 15562 #define DSC_1_A_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 2 15563 15564 /* dsc_1_A :: cdr_ctrl0 :: reserved_for_eco1 [01:00] */ 15565 #define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO1_MASK 0x0003 15566 #define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO1_ALIGN 0 15567 #define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO1_BITS 2 15568 #define DSC_1_A_CDR_CTRL0_RESERVED_FOR_ECO1_SHIFT 0 15569 15570 15571 /**************************************************************************** 15572 * dsc_1_A :: cdr_ctrl1 15573 */ 15574 /* dsc_1_A :: cdr_ctrl1 :: reserved_for_eco0 [15:10] */ 15575 #define DSC_1_A_CDR_CTRL1_RESERVED_FOR_ECO0_MASK 0xfc00 15576 #define DSC_1_A_CDR_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 15577 #define DSC_1_A_CDR_CTRL1_RESERVED_FOR_ECO0_BITS 6 15578 #define DSC_1_A_CDR_CTRL1_RESERVED_FOR_ECO0_SHIFT 10 15579 15580 /* dsc_1_A :: cdr_ctrl1 :: cdr_phase_err_frz [09:09] */ 15581 #define DSC_1_A_CDR_CTRL1_CDR_PHASE_ERR_FRZ_MASK 0x0200 15582 #define DSC_1_A_CDR_CTRL1_CDR_PHASE_ERR_FRZ_ALIGN 0 15583 #define DSC_1_A_CDR_CTRL1_CDR_PHASE_ERR_FRZ_BITS 1 15584 #define DSC_1_A_CDR_CTRL1_CDR_PHASE_ERR_FRZ_SHIFT 9 15585 15586 /* dsc_1_A :: cdr_ctrl1 :: cdr_integ_reg_clr [08:08] */ 15587 #define DSC_1_A_CDR_CTRL1_CDR_INTEG_REG_CLR_MASK 0x0100 15588 #define DSC_1_A_CDR_CTRL1_CDR_INTEG_REG_CLR_ALIGN 0 15589 #define DSC_1_A_CDR_CTRL1_CDR_INTEG_REG_CLR_BITS 1 15590 #define DSC_1_A_CDR_CTRL1_CDR_INTEG_REG_CLR_SHIFT 8 15591 15592 /* dsc_1_A :: cdr_ctrl1 :: cdr_freq_override_val [07:03] */ 15593 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0x00f8 15594 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 15595 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 5 15596 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 3 15597 15598 /* dsc_1_A :: cdr_ctrl1 :: cdr_freq_override_en [02:02] */ 15599 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_MASK 0x0004 15600 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_ALIGN 0 15601 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_BITS 1 15602 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_OVERRIDE_EN_SHIFT 2 15603 15604 /* dsc_1_A :: cdr_ctrl1 :: cdr_freq_upd_en [01:01] */ 15605 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_UPD_EN_MASK 0x0002 15606 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_UPD_EN_ALIGN 0 15607 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_UPD_EN_BITS 1 15608 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_UPD_EN_SHIFT 1 15609 15610 /* dsc_1_A :: cdr_ctrl1 :: cdr_freq_en [00:00] */ 15611 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_EN_MASK 0x0001 15612 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_EN_ALIGN 0 15613 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_EN_BITS 1 15614 #define DSC_1_A_CDR_CTRL1_CDR_FREQ_EN_SHIFT 0 15615 15616 15617 /**************************************************************************** 15618 * dsc_1_A :: cdr_ctrl2 15619 */ 15620 /* dsc_1_A :: cdr_ctrl2 :: reserved_for_eco0 [15:14] */ 15621 #define DSC_1_A_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xc000 15622 #define DSC_1_A_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 15623 #define DSC_1_A_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 2 15624 #define DSC_1_A_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 14 15625 15626 /* dsc_1_A :: cdr_ctrl2 :: cdros_bwsel_prop [13:10] */ 15627 #define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_PROP_MASK 0x3c00 15628 #define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_PROP_ALIGN 0 15629 #define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_PROP_BITS 4 15630 #define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_PROP_SHIFT 10 15631 15632 /* dsc_1_A :: cdr_ctrl2 :: cdros_bwsel_integ [09:06] */ 15633 #define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_INTEG_MASK 0x03c0 15634 #define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_INTEG_ALIGN 0 15635 #define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_INTEG_BITS 4 15636 #define DSC_1_A_CDR_CTRL2_CDROS_BWSEL_INTEG_SHIFT 6 15637 15638 /* dsc_1_A :: cdr_ctrl2 :: cdros_falling_edge [05:05] */ 15639 #define DSC_1_A_CDR_CTRL2_CDROS_FALLING_EDGE_MASK 0x0020 15640 #define DSC_1_A_CDR_CTRL2_CDROS_FALLING_EDGE_ALIGN 0 15641 #define DSC_1_A_CDR_CTRL2_CDROS_FALLING_EDGE_BITS 1 15642 #define DSC_1_A_CDR_CTRL2_CDROS_FALLING_EDGE_SHIFT 5 15643 15644 /* dsc_1_A :: cdr_ctrl2 :: cdros_rising_edge [04:04] */ 15645 #define DSC_1_A_CDR_CTRL2_CDROS_RISING_EDGE_MASK 0x0010 15646 #define DSC_1_A_CDR_CTRL2_CDROS_RISING_EDGE_ALIGN 0 15647 #define DSC_1_A_CDR_CTRL2_CDROS_RISING_EDGE_BITS 1 15648 #define DSC_1_A_CDR_CTRL2_CDROS_RISING_EDGE_SHIFT 4 15649 15650 /* dsc_1_A :: cdr_ctrl2 :: cdros_phase_sat_ctrl [03:02] */ 15651 #define DSC_1_A_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_MASK 0x000c 15652 #define DSC_1_A_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_ALIGN 0 15653 #define DSC_1_A_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_BITS 2 15654 #define DSC_1_A_CDR_CTRL2_CDROS_PHASE_SAT_CTRL_SHIFT 2 15655 15656 /* dsc_1_A :: cdr_ctrl2 :: cdros_peak_polarity [01:01] */ 15657 #define DSC_1_A_CDR_CTRL2_CDROS_PEAK_POLARITY_MASK 0x0002 15658 #define DSC_1_A_CDR_CTRL2_CDROS_PEAK_POLARITY_ALIGN 0 15659 #define DSC_1_A_CDR_CTRL2_CDROS_PEAK_POLARITY_BITS 1 15660 #define DSC_1_A_CDR_CTRL2_CDROS_PEAK_POLARITY_SHIFT 1 15661 15662 /* dsc_1_A :: cdr_ctrl2 :: cdros_zero_polarity [00:00] */ 15663 #define DSC_1_A_CDR_CTRL2_CDROS_ZERO_POLARITY_MASK 0x0001 15664 #define DSC_1_A_CDR_CTRL2_CDROS_ZERO_POLARITY_ALIGN 0 15665 #define DSC_1_A_CDR_CTRL2_CDROS_ZERO_POLARITY_BITS 1 15666 #define DSC_1_A_CDR_CTRL2_CDROS_ZERO_POLARITY_SHIFT 0 15667 15668 15669 /**************************************************************************** 15670 * dsc_1_A :: cdr_status0 15671 */ 15672 /* dsc_1_A :: cdr_status0 :: integ_reg [15:00] */ 15673 #define DSC_1_A_CDR_STATUS0_INTEG_REG_MASK 0xffff 15674 #define DSC_1_A_CDR_STATUS0_INTEG_REG_ALIGN 0 15675 #define DSC_1_A_CDR_STATUS0_INTEG_REG_BITS 16 15676 #define DSC_1_A_CDR_STATUS0_INTEG_REG_SHIFT 0 15677 15678 15679 /**************************************************************************** 15680 * dsc_1_A :: cdr_status1 15681 */ 15682 /* dsc_1_A :: cdr_status1 :: reserved_for_eco0 [15:06] */ 15683 #define DSC_1_A_CDR_STATUS1_RESERVED_FOR_ECO0_MASK 0xffc0 15684 #define DSC_1_A_CDR_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 15685 #define DSC_1_A_CDR_STATUS1_RESERVED_FOR_ECO0_BITS 10 15686 #define DSC_1_A_CDR_STATUS1_RESERVED_FOR_ECO0_SHIFT 6 15687 15688 /* dsc_1_A :: cdr_status1 :: phase_err [05:00] */ 15689 #define DSC_1_A_CDR_STATUS1_PHASE_ERR_MASK 0x003f 15690 #define DSC_1_A_CDR_STATUS1_PHASE_ERR_ALIGN 0 15691 #define DSC_1_A_CDR_STATUS1_PHASE_ERR_BITS 6 15692 #define DSC_1_A_CDR_STATUS1_PHASE_ERR_SHIFT 0 15693 15694 15695 /**************************************************************************** 15696 * dsc_1_A :: pi_ctrl0 15697 */ 15698 /* dsc_1_A :: pi_ctrl0 :: reserved_for_eco0 [15:11] */ 15699 #define DSC_1_A_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0xf800 15700 #define DSC_1_A_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 15701 #define DSC_1_A_PI_CTRL0_RESERVED_FOR_ECO0_BITS 5 15702 #define DSC_1_A_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 15703 15704 /* dsc_1_A :: pi_ctrl0 :: pi_phase_invert [10:10] */ 15705 #define DSC_1_A_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0400 15706 #define DSC_1_A_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 15707 #define DSC_1_A_PI_CTRL0_PI_PHASE_INVERT_BITS 1 15708 #define DSC_1_A_PI_CTRL0_PI_PHASE_INVERT_SHIFT 10 15709 15710 /* dsc_1_A :: pi_ctrl0 :: pi_dual_phase_override [09:09] */ 15711 #define DSC_1_A_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK 0x0200 15712 #define DSC_1_A_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 15713 #define DSC_1_A_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS 1 15714 #define DSC_1_A_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT 9 15715 15716 /* dsc_1_A :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */ 15717 #define DSC_1_A_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0100 15718 #define DSC_1_A_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 15719 #define DSC_1_A_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS 1 15720 #define DSC_1_A_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT 8 15721 15722 /* dsc_1_A :: pi_ctrl0 :: pi_phase_dec [07:07] */ 15723 #define DSC_1_A_PI_CTRL0_PI_PHASE_DEC_MASK 0x0080 15724 #define DSC_1_A_PI_CTRL0_PI_PHASE_DEC_ALIGN 0 15725 #define DSC_1_A_PI_CTRL0_PI_PHASE_DEC_BITS 1 15726 #define DSC_1_A_PI_CTRL0_PI_PHASE_DEC_SHIFT 7 15727 15728 /* dsc_1_A :: pi_ctrl0 :: pi_phase_inc [06:06] */ 15729 #define DSC_1_A_PI_CTRL0_PI_PHASE_INC_MASK 0x0040 15730 #define DSC_1_A_PI_CTRL0_PI_PHASE_INC_ALIGN 0 15731 #define DSC_1_A_PI_CTRL0_PI_PHASE_INC_BITS 1 15732 #define DSC_1_A_PI_CTRL0_PI_PHASE_INC_SHIFT 6 15733 15734 /* dsc_1_A :: pi_ctrl0 :: pi_phase_strobe [05:05] */ 15735 #define DSC_1_A_PI_CTRL0_PI_PHASE_STROBE_MASK 0x0020 15736 #define DSC_1_A_PI_CTRL0_PI_PHASE_STROBE_ALIGN 0 15737 #define DSC_1_A_PI_CTRL0_PI_PHASE_STROBE_BITS 1 15738 #define DSC_1_A_PI_CTRL0_PI_PHASE_STROBE_SHIFT 5 15739 15740 /* dsc_1_A :: pi_ctrl0 :: pi_phase_delta [04:01] */ 15741 #define DSC_1_A_PI_CTRL0_PI_PHASE_DELTA_MASK 0x001e 15742 #define DSC_1_A_PI_CTRL0_PI_PHASE_DELTA_ALIGN 0 15743 #define DSC_1_A_PI_CTRL0_PI_PHASE_DELTA_BITS 4 15744 #define DSC_1_A_PI_CTRL0_PI_PHASE_DELTA_SHIFT 1 15745 15746 /* dsc_1_A :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 15747 #define DSC_1_A_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 15748 #define DSC_1_A_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 15749 #define DSC_1_A_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 15750 #define DSC_1_A_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 15751 15752 15753 /**************************************************************************** 15754 * dsc_1_A :: pi_status0 15755 */ 15756 /* dsc_1_A :: pi_status0 :: reserved_for_eco0 [15:14] */ 15757 #define DSC_1_A_PI_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 15758 #define DSC_1_A_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 15759 #define DSC_1_A_PI_STATUS0_RESERVED_FOR_ECO0_BITS 2 15760 #define DSC_1_A_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 15761 15762 /* dsc_1_A :: pi_status0 :: clk90_phase_offset [13:07] */ 15763 #define DSC_1_A_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 15764 #define DSC_1_A_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 15765 #define DSC_1_A_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 15766 #define DSC_1_A_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 15767 15768 /* dsc_1_A :: pi_status0 :: phase_cntr [06:00] */ 15769 #define DSC_1_A_PI_STATUS0_PHASE_CNTR_MASK 0x007f 15770 #define DSC_1_A_PI_STATUS0_PHASE_CNTR_ALIGN 0 15771 #define DSC_1_A_PI_STATUS0_PHASE_CNTR_BITS 7 15772 #define DSC_1_A_PI_STATUS0_PHASE_CNTR_SHIFT 0 15773 15774 15775 /**************************************************************************** 15776 * dsc_1_A :: dfe_vga_ctrl0 15777 */ 15778 /* dsc_1_A :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:12] */ 15779 #define DSC_1_A_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK 0xf000 15780 #define DSC_1_A_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 15781 #define DSC_1_A_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS 4 15782 #define DSC_1_A_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT 12 15783 15784 /* dsc_1_A :: dfe_vga_ctrl0 :: trnsum_tap0_only [11:11] */ 15785 #define DSC_1_A_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0800 15786 #define DSC_1_A_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 15787 #define DSC_1_A_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 15788 #define DSC_1_A_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 11 15789 15790 /* dsc_1_A :: dfe_vga_ctrl0 :: sum_m1err [10:10] */ 15791 #define DSC_1_A_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0400 15792 #define DSC_1_A_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 15793 #define DSC_1_A_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 15794 #define DSC_1_A_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 10 15795 15796 /* dsc_1_A :: dfe_vga_ctrl0 :: dfe_vga_clken [09:09] */ 15797 #define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0200 15798 #define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 15799 #define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 15800 #define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 9 15801 15802 /* dsc_1_A :: dfe_vga_ctrl0 :: hysteresis_en [08:08] */ 15803 #define DSC_1_A_DFE_VGA_CTRL0_HYSTERESIS_EN_MASK 0x0100 15804 #define DSC_1_A_DFE_VGA_CTRL0_HYSTERESIS_EN_ALIGN 0 15805 #define DSC_1_A_DFE_VGA_CTRL0_HYSTERESIS_EN_BITS 1 15806 #define DSC_1_A_DFE_VGA_CTRL0_HYSTERESIS_EN_SHIFT 8 15807 15808 /* dsc_1_A :: dfe_vga_ctrl0 :: dfe_vga_write_val [07:02] */ 15809 #define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_MASK 0x00fc 15810 #define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_ALIGN 0 15811 #define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_BITS 6 15812 #define DSC_1_A_DFE_VGA_CTRL0_DFE_VGA_WRITE_VAL_SHIFT 2 15813 15814 /* dsc_1_A :: dfe_vga_ctrl0 :: vga_write_en [01:01] */ 15815 #define DSC_1_A_DFE_VGA_CTRL0_VGA_WRITE_EN_MASK 0x0002 15816 #define DSC_1_A_DFE_VGA_CTRL0_VGA_WRITE_EN_ALIGN 0 15817 #define DSC_1_A_DFE_VGA_CTRL0_VGA_WRITE_EN_BITS 1 15818 #define DSC_1_A_DFE_VGA_CTRL0_VGA_WRITE_EN_SHIFT 1 15819 15820 /* dsc_1_A :: dfe_vga_ctrl0 :: dfe_write_en [00:00] */ 15821 #define DSC_1_A_DFE_VGA_CTRL0_DFE_WRITE_EN_MASK 0x0001 15822 #define DSC_1_A_DFE_VGA_CTRL0_DFE_WRITE_EN_ALIGN 0 15823 #define DSC_1_A_DFE_VGA_CTRL0_DFE_WRITE_EN_BITS 1 15824 #define DSC_1_A_DFE_VGA_CTRL0_DFE_WRITE_EN_SHIFT 0 15825 15826 15827 /**************************************************************************** 15828 * dsc_1_A :: dfe_vga_ctrl1 15829 */ 15830 /* dsc_1_A :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:15] */ 15831 #define DSC_1_A_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 15832 #define DSC_1_A_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 15833 #define DSC_1_A_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 1 15834 #define DSC_1_A_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 15835 15836 /* dsc_1_A :: dfe_vga_ctrl1 :: trnsum_otap_en [14:08] */ 15837 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_MASK 0x7f00 15838 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_ALIGN 0 15839 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_BITS 7 15840 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_OTAP_EN_SHIFT 8 15841 15842 /* dsc_1_A :: dfe_vga_ctrl1 :: trnsum_etap_en [07:01] */ 15843 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_MASK 0x00fe 15844 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_ALIGN 0 15845 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_BITS 7 15846 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_ETAP_EN_SHIFT 1 15847 15848 /* dsc_1_A :: dfe_vga_ctrl1 :: trnsum_en [00:00] */ 15849 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_EN_MASK 0x0001 15850 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_EN_ALIGN 0 15851 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_EN_BITS 1 15852 #define DSC_1_A_DFE_VGA_CTRL1_TRNSUM_EN_SHIFT 0 15853 15854 15855 /**************************************************************************** 15856 * dsc_1_A :: dfe_vga_ctrl2 15857 */ 15858 /* dsc_1_A :: dfe_vga_ctrl2 :: vga_polarity [15:15] */ 15859 #define DSC_1_A_DFE_VGA_CTRL2_VGA_POLARITY_MASK 0x8000 15860 #define DSC_1_A_DFE_VGA_CTRL2_VGA_POLARITY_ALIGN 0 15861 #define DSC_1_A_DFE_VGA_CTRL2_VGA_POLARITY_BITS 1 15862 #define DSC_1_A_DFE_VGA_CTRL2_VGA_POLARITY_SHIFT 15 15863 15864 /* dsc_1_A :: dfe_vga_ctrl2 :: dfe_polarity [14:14] */ 15865 #define DSC_1_A_DFE_VGA_CTRL2_DFE_POLARITY_MASK 0x4000 15866 #define DSC_1_A_DFE_VGA_CTRL2_DFE_POLARITY_ALIGN 0 15867 #define DSC_1_A_DFE_VGA_CTRL2_DFE_POLARITY_BITS 1 15868 #define DSC_1_A_DFE_VGA_CTRL2_DFE_POLARITY_SHIFT 14 15869 15870 /* dsc_1_A :: dfe_vga_ctrl2 :: trnsum_otap_sign [13:07] */ 15871 #define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_MASK 0x3f80 15872 #define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_ALIGN 0 15873 #define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_BITS 7 15874 #define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_OTAP_SIGN_SHIFT 7 15875 15876 /* dsc_1_A :: dfe_vga_ctrl2 :: trnsum_etap_sign [06:00] */ 15877 #define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_MASK 0x007f 15878 #define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_ALIGN 0 15879 #define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_BITS 7 15880 #define DSC_1_A_DFE_VGA_CTRL2_TRNSUM_ETAP_SIGN_SHIFT 0 15881 15882 15883 /**************************************************************************** 15884 * dsc_1_A :: dfe_vga_ctrl3 15885 */ 15886 /* dsc_1_A :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:10] */ 15887 #define DSC_1_A_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK 0xfc00 15888 #define DSC_1_A_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 15889 #define DSC_1_A_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS 6 15890 #define DSC_1_A_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT 10 15891 15892 /* dsc_1_A :: dfe_vga_ctrl3 :: vga_cor_sel_e [09:05] */ 15893 #define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_E_MASK 0x03e0 15894 #define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_E_ALIGN 0 15895 #define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_E_BITS 5 15896 #define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_E_SHIFT 5 15897 15898 /* dsc_1_A :: dfe_vga_ctrl3 :: vga_cor_sel_o [04:00] */ 15899 #define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_O_MASK 0x001f 15900 #define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_O_ALIGN 0 15901 #define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_O_BITS 5 15902 #define DSC_1_A_DFE_VGA_CTRL3_VGA_COR_SEL_O_SHIFT 0 15903 15904 15905 /**************************************************************************** 15906 * dsc_1_A :: dfe_vga_ctrl4 15907 */ 15908 /* dsc_1_A :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */ 15909 #define DSC_1_A_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK 0xfc00 15910 #define DSC_1_A_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 15911 #define DSC_1_A_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS 6 15912 #define DSC_1_A_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT 10 15913 15914 /* dsc_1_A :: dfe_vga_ctrl4 :: dfe_cor_sel_e [09:05] */ 15915 #define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_E_MASK 0x03e0 15916 #define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_E_ALIGN 0 15917 #define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_E_BITS 5 15918 #define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_E_SHIFT 5 15919 15920 /* dsc_1_A :: dfe_vga_ctrl4 :: dfe_cor_sel_o [04:00] */ 15921 #define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_O_MASK 0x001f 15922 #define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_O_ALIGN 0 15923 #define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_O_BITS 5 15924 #define DSC_1_A_DFE_VGA_CTRL4_DFE_COR_SEL_O_SHIFT 0 15925 15926 15927 /**************************************************************************** 15928 * dsc_1_A :: dfe_vga_status0 15929 */ 15930 /* dsc_1_A :: dfe_vga_status0 :: vga_sum [15:11] */ 15931 #define DSC_1_A_DFE_VGA_STATUS0_VGA_SUM_MASK 0xf800 15932 #define DSC_1_A_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 15933 #define DSC_1_A_DFE_VGA_STATUS0_VGA_SUM_BITS 5 15934 #define DSC_1_A_DFE_VGA_STATUS0_VGA_SUM_SHIFT 11 15935 15936 /* dsc_1_A :: dfe_vga_status0 :: trnsum [10:00] */ 15937 #define DSC_1_A_DFE_VGA_STATUS0_TRNSUM_MASK 0x07ff 15938 #define DSC_1_A_DFE_VGA_STATUS0_TRNSUM_ALIGN 0 15939 #define DSC_1_A_DFE_VGA_STATUS0_TRNSUM_BITS 11 15940 #define DSC_1_A_DFE_VGA_STATUS0_TRNSUM_SHIFT 0 15941 15942 15943 /**************************************************************************** 15944 * dsc_1_A :: dfe_vga_status1 15945 */ 15946 /* dsc_1_A :: dfe_vga_status1 :: odd_dfe_acc [15:06] */ 15947 #define DSC_1_A_DFE_VGA_STATUS1_ODD_DFE_ACC_MASK 0xffc0 15948 #define DSC_1_A_DFE_VGA_STATUS1_ODD_DFE_ACC_ALIGN 0 15949 #define DSC_1_A_DFE_VGA_STATUS1_ODD_DFE_ACC_BITS 10 15950 #define DSC_1_A_DFE_VGA_STATUS1_ODD_DFE_ACC_SHIFT 6 15951 15952 /* dsc_1_A :: dfe_vga_status1 :: dfe_tap_bin [05:00] */ 15953 #define DSC_1_A_DFE_VGA_STATUS1_DFE_TAP_BIN_MASK 0x003f 15954 #define DSC_1_A_DFE_VGA_STATUS1_DFE_TAP_BIN_ALIGN 0 15955 #define DSC_1_A_DFE_VGA_STATUS1_DFE_TAP_BIN_BITS 6 15956 #define DSC_1_A_DFE_VGA_STATUS1_DFE_TAP_BIN_SHIFT 0 15957 15958 15959 /**************************************************************************** 15960 * dsc_1_A :: dfe_vga_status2 15961 */ 15962 /* dsc_1_A :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */ 15963 #define DSC_1_A_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK 0xfc00 15964 #define DSC_1_A_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 15965 #define DSC_1_A_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS 6 15966 #define DSC_1_A_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT 10 15967 15968 /* dsc_1_A :: dfe_vga_status2 :: evn_dfe_acc [09:00] */ 15969 #define DSC_1_A_DFE_VGA_STATUS2_EVN_DFE_ACC_MASK 0x03ff 15970 #define DSC_1_A_DFE_VGA_STATUS2_EVN_DFE_ACC_ALIGN 0 15971 #define DSC_1_A_DFE_VGA_STATUS2_EVN_DFE_ACC_BITS 10 15972 #define DSC_1_A_DFE_VGA_STATUS2_EVN_DFE_ACC_SHIFT 0 15973 15974 15975 /**************************************************************************** 15976 * XGXS16G_USER_dsc_2_0 15977 */ 15978 /**************************************************************************** 15979 * dsc_2_0 :: sm_status0 15980 */ 15981 /* dsc_2_0 :: sm_status0 :: reserved_for_eco0 [15:04] */ 15982 #define DSC_2_0_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xfff0 15983 #define DSC_2_0_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 15984 #define DSC_2_0_SM_STATUS0_RESERVED_FOR_ECO0_BITS 12 15985 #define DSC_2_0_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 4 15986 15987 /* dsc_2_0 :: sm_status0 :: dsc_state [03:00] */ 15988 #define DSC_2_0_SM_STATUS0_DSC_STATE_MASK 0x000f 15989 #define DSC_2_0_SM_STATUS0_DSC_STATE_ALIGN 0 15990 #define DSC_2_0_SM_STATUS0_DSC_STATE_BITS 4 15991 #define DSC_2_0_SM_STATUS0_DSC_STATE_SHIFT 0 15992 15993 15994 /**************************************************************************** 15995 * dsc_2_0 :: sm_ctrl0 15996 */ 15997 /* dsc_2_0 :: sm_ctrl0 :: acqvga_timeout [15:11] */ 15998 #define DSC_2_0_SM_CTRL0_ACQVGA_TIMEOUT_MASK 0xf800 15999 #define DSC_2_0_SM_CTRL0_ACQVGA_TIMEOUT_ALIGN 0 16000 #define DSC_2_0_SM_CTRL0_ACQVGA_TIMEOUT_BITS 5 16001 #define DSC_2_0_SM_CTRL0_ACQVGA_TIMEOUT_SHIFT 11 16002 16003 /* dsc_2_0 :: sm_ctrl0 :: tuning_sm_en [10:10] */ 16004 #define DSC_2_0_SM_CTRL0_TUNING_SM_EN_MASK 0x0400 16005 #define DSC_2_0_SM_CTRL0_TUNING_SM_EN_ALIGN 0 16006 #define DSC_2_0_SM_CTRL0_TUNING_SM_EN_BITS 1 16007 #define DSC_2_0_SM_CTRL0_TUNING_SM_EN_SHIFT 10 16008 16009 /* dsc_2_0 :: sm_ctrl0 :: train2_req [09:09] */ 16010 #define DSC_2_0_SM_CTRL0_TRAIN2_REQ_MASK 0x0200 16011 #define DSC_2_0_SM_CTRL0_TRAIN2_REQ_ALIGN 0 16012 #define DSC_2_0_SM_CTRL0_TRAIN2_REQ_BITS 1 16013 #define DSC_2_0_SM_CTRL0_TRAIN2_REQ_SHIFT 9 16014 16015 /* dsc_2_0 :: sm_ctrl0 :: train1_req [08:08] */ 16016 #define DSC_2_0_SM_CTRL0_TRAIN1_REQ_MASK 0x0100 16017 #define DSC_2_0_SM_CTRL0_TRAIN1_REQ_ALIGN 0 16018 #define DSC_2_0_SM_CTRL0_TRAIN1_REQ_BITS 1 16019 #define DSC_2_0_SM_CTRL0_TRAIN1_REQ_SHIFT 8 16020 16021 /* dsc_2_0 :: sm_ctrl0 :: soft_ack [07:07] */ 16022 #define DSC_2_0_SM_CTRL0_SOFT_ACK_MASK 0x0080 16023 #define DSC_2_0_SM_CTRL0_SOFT_ACK_ALIGN 0 16024 #define DSC_2_0_SM_CTRL0_SOFT_ACK_BITS 1 16025 #define DSC_2_0_SM_CTRL0_SOFT_ACK_SHIFT 7 16026 16027 /* dsc_2_0 :: sm_ctrl0 :: train_mode_en [06:06] */ 16028 #define DSC_2_0_SM_CTRL0_TRAIN_MODE_EN_MASK 0x0040 16029 #define DSC_2_0_SM_CTRL0_TRAIN_MODE_EN_ALIGN 0 16030 #define DSC_2_0_SM_CTRL0_TRAIN_MODE_EN_BITS 1 16031 #define DSC_2_0_SM_CTRL0_TRAIN_MODE_EN_SHIFT 6 16032 16033 /* dsc_2_0 :: sm_ctrl0 :: vga_frzval [05:05] */ 16034 #define DSC_2_0_SM_CTRL0_VGA_FRZVAL_MASK 0x0020 16035 #define DSC_2_0_SM_CTRL0_VGA_FRZVAL_ALIGN 0 16036 #define DSC_2_0_SM_CTRL0_VGA_FRZVAL_BITS 1 16037 #define DSC_2_0_SM_CTRL0_VGA_FRZVAL_SHIFT 5 16038 16039 /* dsc_2_0 :: sm_ctrl0 :: vga_frcfrz [04:04] */ 16040 #define DSC_2_0_SM_CTRL0_VGA_FRCFRZ_MASK 0x0010 16041 #define DSC_2_0_SM_CTRL0_VGA_FRCFRZ_ALIGN 0 16042 #define DSC_2_0_SM_CTRL0_VGA_FRCFRZ_BITS 1 16043 #define DSC_2_0_SM_CTRL0_VGA_FRCFRZ_SHIFT 4 16044 16045 /* dsc_2_0 :: sm_ctrl0 :: dfe_frzval [03:03] */ 16046 #define DSC_2_0_SM_CTRL0_DFE_FRZVAL_MASK 0x0008 16047 #define DSC_2_0_SM_CTRL0_DFE_FRZVAL_ALIGN 0 16048 #define DSC_2_0_SM_CTRL0_DFE_FRZVAL_BITS 1 16049 #define DSC_2_0_SM_CTRL0_DFE_FRZVAL_SHIFT 3 16050 16051 /* dsc_2_0 :: sm_ctrl0 :: dfe_frcfrz [02:02] */ 16052 #define DSC_2_0_SM_CTRL0_DFE_FRCFRZ_MASK 0x0004 16053 #define DSC_2_0_SM_CTRL0_DFE_FRCFRZ_ALIGN 0 16054 #define DSC_2_0_SM_CTRL0_DFE_FRCFRZ_BITS 1 16055 #define DSC_2_0_SM_CTRL0_DFE_FRCFRZ_SHIFT 2 16056 16057 /* dsc_2_0 :: sm_ctrl0 :: dsc_clr_val [01:01] */ 16058 #define DSC_2_0_SM_CTRL0_DSC_CLR_VAL_MASK 0x0002 16059 #define DSC_2_0_SM_CTRL0_DSC_CLR_VAL_ALIGN 0 16060 #define DSC_2_0_SM_CTRL0_DSC_CLR_VAL_BITS 1 16061 #define DSC_2_0_SM_CTRL0_DSC_CLR_VAL_SHIFT 1 16062 16063 /* dsc_2_0 :: sm_ctrl0 :: dsc_clr_frc [00:00] */ 16064 #define DSC_2_0_SM_CTRL0_DSC_CLR_FRC_MASK 0x0001 16065 #define DSC_2_0_SM_CTRL0_DSC_CLR_FRC_ALIGN 0 16066 #define DSC_2_0_SM_CTRL0_DSC_CLR_FRC_BITS 1 16067 #define DSC_2_0_SM_CTRL0_DSC_CLR_FRC_SHIFT 0 16068 16069 16070 /**************************************************************************** 16071 * dsc_2_0 :: sm_ctrl1 16072 */ 16073 /* dsc_2_0 :: sm_ctrl1 :: fast_timer [15:15] */ 16074 #define DSC_2_0_SM_CTRL1_FAST_TIMER_MASK 0x8000 16075 #define DSC_2_0_SM_CTRL1_FAST_TIMER_ALIGN 0 16076 #define DSC_2_0_SM_CTRL1_FAST_TIMER_BITS 1 16077 #define DSC_2_0_SM_CTRL1_FAST_TIMER_SHIFT 15 16078 16079 /* dsc_2_0 :: sm_ctrl1 :: acq2_timeout [14:10] */ 16080 #define DSC_2_0_SM_CTRL1_ACQ2_TIMEOUT_MASK 0x7c00 16081 #define DSC_2_0_SM_CTRL1_ACQ2_TIMEOUT_ALIGN 0 16082 #define DSC_2_0_SM_CTRL1_ACQ2_TIMEOUT_BITS 5 16083 #define DSC_2_0_SM_CTRL1_ACQ2_TIMEOUT_SHIFT 10 16084 16085 /* dsc_2_0 :: sm_ctrl1 :: acq1_timeout [09:05] */ 16086 #define DSC_2_0_SM_CTRL1_ACQ1_TIMEOUT_MASK 0x03e0 16087 #define DSC_2_0_SM_CTRL1_ACQ1_TIMEOUT_ALIGN 0 16088 #define DSC_2_0_SM_CTRL1_ACQ1_TIMEOUT_BITS 5 16089 #define DSC_2_0_SM_CTRL1_ACQ1_TIMEOUT_SHIFT 5 16090 16091 /* dsc_2_0 :: sm_ctrl1 :: acqcdr_timeout [04:00] */ 16092 #define DSC_2_0_SM_CTRL1_ACQCDR_TIMEOUT_MASK 0x001f 16093 #define DSC_2_0_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN 0 16094 #define DSC_2_0_SM_CTRL1_ACQCDR_TIMEOUT_BITS 5 16095 #define DSC_2_0_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT 0 16096 16097 16098 /**************************************************************************** 16099 * dsc_2_0 :: sm_ctrl2 16100 */ 16101 /* dsc_2_0 :: sm_ctrl2 :: reserved_for_eco0 [15:15] */ 16102 #define DSC_2_0_SM_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 16103 #define DSC_2_0_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 16104 #define DSC_2_0_SM_CTRL2_RESERVED_FOR_ECO0_BITS 1 16105 #define DSC_2_0_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 16106 16107 /* dsc_2_0 :: sm_ctrl2 :: cdrbr_bwsel_prop_acqcdr [14:12] */ 16108 #define DSC_2_0_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x7000 16109 #define DSC_2_0_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 16110 #define DSC_2_0_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 16111 #define DSC_2_0_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 12 16112 16113 /* dsc_2_0 :: sm_ctrl2 :: dfe_gain_acq2 [11:10] */ 16114 #define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ2_MASK 0x0c00 16115 #define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ2_ALIGN 0 16116 #define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ2_BITS 2 16117 #define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ2_SHIFT 10 16118 16119 /* dsc_2_0 :: sm_ctrl2 :: dfe_gain_acq1 [09:08] */ 16120 #define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ1_MASK 0x0300 16121 #define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ1_ALIGN 0 16122 #define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ1_BITS 2 16123 #define DSC_2_0_SM_CTRL2_DFE_GAIN_ACQ1_SHIFT 8 16124 16125 /* dsc_2_0 :: sm_ctrl2 :: vga_gain_acq2 [07:06] */ 16126 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ2_MASK 0x00c0 16127 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ2_ALIGN 0 16128 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ2_BITS 2 16129 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ2_SHIFT 6 16130 16131 /* dsc_2_0 :: sm_ctrl2 :: vga_gain_acq1 [05:04] */ 16132 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ1_MASK 0x0030 16133 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ1_ALIGN 0 16134 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ1_BITS 2 16135 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQ1_SHIFT 4 16136 16137 /* dsc_2_0 :: sm_ctrl2 :: vga_gain_acqcdr [03:02] */ 16138 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQCDR_MASK 0x000c 16139 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQCDR_ALIGN 0 16140 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQCDR_BITS 2 16141 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQCDR_SHIFT 2 16142 16143 /* dsc_2_0 :: sm_ctrl2 :: vga_gain_acqvga [01:00] */ 16144 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQVGA_MASK 0x0003 16145 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQVGA_ALIGN 0 16146 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQVGA_BITS 2 16147 #define DSC_2_0_SM_CTRL2_VGA_GAIN_ACQVGA_SHIFT 0 16148 16149 16150 /**************************************************************************** 16151 * dsc_2_0 :: sm_ctrl3 16152 */ 16153 /* dsc_2_0 :: sm_ctrl3 :: reserved_for_eco0 [15:12] */ 16154 #define DSC_2_0_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0xf000 16155 #define DSC_2_0_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 16156 #define DSC_2_0_SM_CTRL3_RESERVED_FOR_ECO0_BITS 4 16157 #define DSC_2_0_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 12 16158 16159 /* dsc_2_0 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq2 [11:10] */ 16160 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0c00 16161 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 16162 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_BITS 2 16163 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 10 16164 16165 /* dsc_2_0 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq1 [09:08] */ 16166 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x0300 16167 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 16168 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_BITS 2 16169 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 8 16170 16171 /* dsc_2_0 :: sm_ctrl3 :: cdrbr_bwsel_integ_acqcdr [07:06] */ 16172 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x00c0 16173 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 16174 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_BITS 2 16175 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 6 16176 16177 /* dsc_2_0 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq2 [05:03] */ 16178 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0038 16179 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 16180 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_BITS 3 16181 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_SHIFT 3 16182 16183 /* dsc_2_0 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq1 [02:00] */ 16184 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_MASK 0x0007 16185 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 16186 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_BITS 3 16187 #define DSC_2_0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_SHIFT 0 16188 16189 16190 /**************************************************************************** 16191 * dsc_2_0 :: sm_ctrl4 16192 */ 16193 /* dsc_2_0 :: sm_ctrl4 :: cdros_bwsel_integ_acq1_2 [15:12] */ 16194 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0xf000 16195 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 16196 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 16197 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 12 16198 16199 /* dsc_2_0 :: sm_ctrl4 :: cdros_bwsel_integ_acqcdr [11:08] */ 16200 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x0f00 16201 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 16202 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 16203 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 8 16204 16205 /* dsc_2_0 :: sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [07:04] */ 16206 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x00f0 16207 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 16208 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 16209 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 4 16210 16211 /* dsc_2_0 :: sm_ctrl4 :: cdros_bwsel_prop_acqcdr [03:00] */ 16212 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK 0x000f 16213 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 16214 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS 4 16215 #define DSC_2_0_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT 0 16216 16217 16218 /**************************************************************************** 16219 * dsc_2_0 :: dsc_status0 16220 */ 16221 /* dsc_2_0 :: dsc_status0 :: data_15_to_0 [15:00] */ 16222 #define DSC_2_0_DSC_STATUS0_DATA_15_TO_0_MASK 0xffff 16223 #define DSC_2_0_DSC_STATUS0_DATA_15_TO_0_ALIGN 0 16224 #define DSC_2_0_DSC_STATUS0_DATA_15_TO_0_BITS 16 16225 #define DSC_2_0_DSC_STATUS0_DATA_15_TO_0_SHIFT 0 16226 16227 16228 /**************************************************************************** 16229 * dsc_2_0 :: dsc_status1 16230 */ 16231 /* dsc_2_0 :: dsc_status1 :: p1err_11_to_0 [15:04] */ 16232 #define DSC_2_0_DSC_STATUS1_P1ERR_11_TO_0_MASK 0xfff0 16233 #define DSC_2_0_DSC_STATUS1_P1ERR_11_TO_0_ALIGN 0 16234 #define DSC_2_0_DSC_STATUS1_P1ERR_11_TO_0_BITS 12 16235 #define DSC_2_0_DSC_STATUS1_P1ERR_11_TO_0_SHIFT 4 16236 16237 /* dsc_2_0 :: dsc_status1 :: data_19_to_16 [03:00] */ 16238 #define DSC_2_0_DSC_STATUS1_DATA_19_TO_16_MASK 0x000f 16239 #define DSC_2_0_DSC_STATUS1_DATA_19_TO_16_ALIGN 0 16240 #define DSC_2_0_DSC_STATUS1_DATA_19_TO_16_BITS 4 16241 #define DSC_2_0_DSC_STATUS1_DATA_19_TO_16_SHIFT 0 16242 16243 16244 /**************************************************************************** 16245 * dsc_2_0 :: dsc_status2 16246 */ 16247 /* dsc_2_0 :: dsc_status2 :: m1err_7_to_0 [15:08] */ 16248 #define DSC_2_0_DSC_STATUS2_M1ERR_7_TO_0_MASK 0xff00 16249 #define DSC_2_0_DSC_STATUS2_M1ERR_7_TO_0_ALIGN 0 16250 #define DSC_2_0_DSC_STATUS2_M1ERR_7_TO_0_BITS 8 16251 #define DSC_2_0_DSC_STATUS2_M1ERR_7_TO_0_SHIFT 8 16252 16253 /* dsc_2_0 :: dsc_status2 :: p1err_19_to_12 [07:00] */ 16254 #define DSC_2_0_DSC_STATUS2_P1ERR_19_TO_12_MASK 0x00ff 16255 #define DSC_2_0_DSC_STATUS2_P1ERR_19_TO_12_ALIGN 0 16256 #define DSC_2_0_DSC_STATUS2_P1ERR_19_TO_12_BITS 8 16257 #define DSC_2_0_DSC_STATUS2_P1ERR_19_TO_12_SHIFT 0 16258 16259 16260 /**************************************************************************** 16261 * dsc_2_0 :: dsc_status3 16262 */ 16263 /* dsc_2_0 :: dsc_status3 :: reserved_for_eco0 [15:12] */ 16264 #define DSC_2_0_DSC_STATUS3_RESERVED_FOR_ECO0_MASK 0xf000 16265 #define DSC_2_0_DSC_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 16266 #define DSC_2_0_DSC_STATUS3_RESERVED_FOR_ECO0_BITS 4 16267 #define DSC_2_0_DSC_STATUS3_RESERVED_FOR_ECO0_SHIFT 12 16268 16269 /* dsc_2_0 :: dsc_status3 :: m1err_19_to_8 [11:00] */ 16270 #define DSC_2_0_DSC_STATUS3_M1ERR_19_TO_8_MASK 0x0fff 16271 #define DSC_2_0_DSC_STATUS3_M1ERR_19_TO_8_ALIGN 0 16272 #define DSC_2_0_DSC_STATUS3_M1ERR_19_TO_8_BITS 12 16273 #define DSC_2_0_DSC_STATUS3_M1ERR_19_TO_8_SHIFT 0 16274 16275 16276 /**************************************************************************** 16277 * dsc_2_0 :: dsc_ctrl0 16278 */ 16279 /* dsc_2_0 :: dsc_ctrl0 :: rxSeqStart [15:15] */ 16280 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_MASK 0x8000 16281 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_ALIGN 0 16282 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_BITS 1 16283 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_SHIFT 15 16284 16285 /* dsc_2_0 :: dsc_ctrl0 :: forceRxSeqDone [14:14] */ 16286 #define DSC_2_0_DSC_CTRL0_FORCERXSEQDONE_MASK 0x4000 16287 #define DSC_2_0_DSC_CTRL0_FORCERXSEQDONE_ALIGN 0 16288 #define DSC_2_0_DSC_CTRL0_FORCERXSEQDONE_BITS 1 16289 #define DSC_2_0_DSC_CTRL0_FORCERXSEQDONE_SHIFT 14 16290 16291 /* dsc_2_0 :: dsc_ctrl0 :: test_bus_sel [13:10] */ 16292 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_MASK 0x3c00 16293 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_ALIGN 0 16294 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_BITS 4 16295 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_SHIFT 10 16296 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_Off 0 16297 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_OSx2data 1 16298 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 16299 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 16300 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 16301 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_cdrIntg 6 16302 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 16303 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 16304 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 16305 #define DSC_2_0_DSC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 16306 16307 /* dsc_2_0 :: dsc_ctrl0 :: rx_m1_thresh_zero [09:09] */ 16308 #define DSC_2_0_DSC_CTRL0_RX_M1_THRESH_ZERO_MASK 0x0200 16309 #define DSC_2_0_DSC_CTRL0_RX_M1_THRESH_ZERO_ALIGN 0 16310 #define DSC_2_0_DSC_CTRL0_RX_M1_THRESH_ZERO_BITS 1 16311 #define DSC_2_0_DSC_CTRL0_RX_M1_THRESH_ZERO_SHIFT 9 16312 16313 /* dsc_2_0 :: dsc_ctrl0 :: rx_thresh_sel [08:07] */ 16314 #define DSC_2_0_DSC_CTRL0_RX_THRESH_SEL_MASK 0x0180 16315 #define DSC_2_0_DSC_CTRL0_RX_THRESH_SEL_ALIGN 0 16316 #define DSC_2_0_DSC_CTRL0_RX_THRESH_SEL_BITS 2 16317 #define DSC_2_0_DSC_CTRL0_RX_THRESH_SEL_SHIFT 7 16318 16319 /* dsc_2_0 :: dsc_ctrl0 :: rx_pf_ctrl [06:04] */ 16320 #define DSC_2_0_DSC_CTRL0_RX_PF_CTRL_MASK 0x0070 16321 #define DSC_2_0_DSC_CTRL0_RX_PF_CTRL_ALIGN 0 16322 #define DSC_2_0_DSC_CTRL0_RX_PF_CTRL_BITS 3 16323 #define DSC_2_0_DSC_CTRL0_RX_PF_CTRL_SHIFT 4 16324 16325 /* dsc_2_0 :: dsc_ctrl0 :: cdrbr_sel [03:03] */ 16326 #define DSC_2_0_DSC_CTRL0_CDRBR_SEL_MASK 0x0008 16327 #define DSC_2_0_DSC_CTRL0_CDRBR_SEL_ALIGN 0 16328 #define DSC_2_0_DSC_CTRL0_CDRBR_SEL_BITS 1 16329 #define DSC_2_0_DSC_CTRL0_CDRBR_SEL_SHIFT 3 16330 16331 /* dsc_2_0 :: dsc_ctrl0 :: oscdr_force_mode_en [02:02] */ 16332 #define DSC_2_0_DSC_CTRL0_OSCDR_FORCE_MODE_EN_MASK 0x0004 16333 #define DSC_2_0_DSC_CTRL0_OSCDR_FORCE_MODE_EN_ALIGN 0 16334 #define DSC_2_0_DSC_CTRL0_OSCDR_FORCE_MODE_EN_BITS 1 16335 #define DSC_2_0_DSC_CTRL0_OSCDR_FORCE_MODE_EN_SHIFT 2 16336 16337 /* dsc_2_0 :: dsc_ctrl0 :: oscdr_mode [01:00] */ 16338 #define DSC_2_0_DSC_CTRL0_OSCDR_MODE_MASK 0x0003 16339 #define DSC_2_0_DSC_CTRL0_OSCDR_MODE_ALIGN 0 16340 #define DSC_2_0_DSC_CTRL0_OSCDR_MODE_BITS 2 16341 #define DSC_2_0_DSC_CTRL0_OSCDR_MODE_SHIFT 0 16342 16343 16344 /**************************************************************************** 16345 * dsc_2_0 :: dsc_ctrl1 16346 */ 16347 /* dsc_2_0 :: dsc_ctrl1 :: reserved_for_eco0 [15:15] */ 16348 #define DSC_2_0_DSC_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 16349 #define DSC_2_0_DSC_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 16350 #define DSC_2_0_DSC_CTRL1_RESERVED_FOR_ECO0_BITS 1 16351 #define DSC_2_0_DSC_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 16352 16353 /* dsc_2_0 :: dsc_ctrl1 :: p1_odd_ctrl [14:10] */ 16354 #define DSC_2_0_DSC_CTRL1_P1_ODD_CTRL_MASK 0x7c00 16355 #define DSC_2_0_DSC_CTRL1_P1_ODD_CTRL_ALIGN 0 16356 #define DSC_2_0_DSC_CTRL1_P1_ODD_CTRL_BITS 5 16357 #define DSC_2_0_DSC_CTRL1_P1_ODD_CTRL_SHIFT 10 16358 16359 /* dsc_2_0 :: dsc_ctrl1 :: p1_evn_ctrl [09:05] */ 16360 #define DSC_2_0_DSC_CTRL1_P1_EVN_CTRL_MASK 0x03e0 16361 #define DSC_2_0_DSC_CTRL1_P1_EVN_CTRL_ALIGN 0 16362 #define DSC_2_0_DSC_CTRL1_P1_EVN_CTRL_BITS 5 16363 #define DSC_2_0_DSC_CTRL1_P1_EVN_CTRL_SHIFT 5 16364 16365 /* dsc_2_0 :: dsc_ctrl1 :: d_odd_ctrl [04:00] */ 16366 #define DSC_2_0_DSC_CTRL1_D_ODD_CTRL_MASK 0x001f 16367 #define DSC_2_0_DSC_CTRL1_D_ODD_CTRL_ALIGN 0 16368 #define DSC_2_0_DSC_CTRL1_D_ODD_CTRL_BITS 5 16369 #define DSC_2_0_DSC_CTRL1_D_ODD_CTRL_SHIFT 0 16370 16371 16372 /**************************************************************************** 16373 * dsc_2_0 :: dsc_ctrl2 16374 */ 16375 /* dsc_2_0 :: dsc_ctrl2 :: reserved_for_eco0 [15:15] */ 16376 #define DSC_2_0_DSC_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 16377 #define DSC_2_0_DSC_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 16378 #define DSC_2_0_DSC_CTRL2_RESERVED_FOR_ECO0_BITS 1 16379 #define DSC_2_0_DSC_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 16380 16381 /* dsc_2_0 :: dsc_ctrl2 :: d_evn_ctrl [14:10] */ 16382 #define DSC_2_0_DSC_CTRL2_D_EVN_CTRL_MASK 0x7c00 16383 #define DSC_2_0_DSC_CTRL2_D_EVN_CTRL_ALIGN 0 16384 #define DSC_2_0_DSC_CTRL2_D_EVN_CTRL_BITS 5 16385 #define DSC_2_0_DSC_CTRL2_D_EVN_CTRL_SHIFT 10 16386 16387 /* dsc_2_0 :: dsc_ctrl2 :: m1_odd_ctrl [09:05] */ 16388 #define DSC_2_0_DSC_CTRL2_M1_ODD_CTRL_MASK 0x03e0 16389 #define DSC_2_0_DSC_CTRL2_M1_ODD_CTRL_ALIGN 0 16390 #define DSC_2_0_DSC_CTRL2_M1_ODD_CTRL_BITS 5 16391 #define DSC_2_0_DSC_CTRL2_M1_ODD_CTRL_SHIFT 5 16392 16393 /* dsc_2_0 :: dsc_ctrl2 :: m1_evn_ctrl [04:00] */ 16394 #define DSC_2_0_DSC_CTRL2_M1_EVN_CTRL_MASK 0x001f 16395 #define DSC_2_0_DSC_CTRL2_M1_EVN_CTRL_ALIGN 0 16396 #define DSC_2_0_DSC_CTRL2_M1_EVN_CTRL_BITS 5 16397 #define DSC_2_0_DSC_CTRL2_M1_EVN_CTRL_SHIFT 0 16398 16399 16400 /**************************************************************************** 16401 * XGXS16G_USER_dsc_2_1 16402 */ 16403 /**************************************************************************** 16404 * dsc_2_1 :: sm_status0 16405 */ 16406 /* dsc_2_1 :: sm_status0 :: reserved_for_eco0 [15:04] */ 16407 #define DSC_2_1_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xfff0 16408 #define DSC_2_1_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 16409 #define DSC_2_1_SM_STATUS0_RESERVED_FOR_ECO0_BITS 12 16410 #define DSC_2_1_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 4 16411 16412 /* dsc_2_1 :: sm_status0 :: dsc_state [03:00] */ 16413 #define DSC_2_1_SM_STATUS0_DSC_STATE_MASK 0x000f 16414 #define DSC_2_1_SM_STATUS0_DSC_STATE_ALIGN 0 16415 #define DSC_2_1_SM_STATUS0_DSC_STATE_BITS 4 16416 #define DSC_2_1_SM_STATUS0_DSC_STATE_SHIFT 0 16417 16418 16419 /**************************************************************************** 16420 * dsc_2_1 :: sm_ctrl0 16421 */ 16422 /* dsc_2_1 :: sm_ctrl0 :: acqvga_timeout [15:11] */ 16423 #define DSC_2_1_SM_CTRL0_ACQVGA_TIMEOUT_MASK 0xf800 16424 #define DSC_2_1_SM_CTRL0_ACQVGA_TIMEOUT_ALIGN 0 16425 #define DSC_2_1_SM_CTRL0_ACQVGA_TIMEOUT_BITS 5 16426 #define DSC_2_1_SM_CTRL0_ACQVGA_TIMEOUT_SHIFT 11 16427 16428 /* dsc_2_1 :: sm_ctrl0 :: tuning_sm_en [10:10] */ 16429 #define DSC_2_1_SM_CTRL0_TUNING_SM_EN_MASK 0x0400 16430 #define DSC_2_1_SM_CTRL0_TUNING_SM_EN_ALIGN 0 16431 #define DSC_2_1_SM_CTRL0_TUNING_SM_EN_BITS 1 16432 #define DSC_2_1_SM_CTRL0_TUNING_SM_EN_SHIFT 10 16433 16434 /* dsc_2_1 :: sm_ctrl0 :: train2_req [09:09] */ 16435 #define DSC_2_1_SM_CTRL0_TRAIN2_REQ_MASK 0x0200 16436 #define DSC_2_1_SM_CTRL0_TRAIN2_REQ_ALIGN 0 16437 #define DSC_2_1_SM_CTRL0_TRAIN2_REQ_BITS 1 16438 #define DSC_2_1_SM_CTRL0_TRAIN2_REQ_SHIFT 9 16439 16440 /* dsc_2_1 :: sm_ctrl0 :: train1_req [08:08] */ 16441 #define DSC_2_1_SM_CTRL0_TRAIN1_REQ_MASK 0x0100 16442 #define DSC_2_1_SM_CTRL0_TRAIN1_REQ_ALIGN 0 16443 #define DSC_2_1_SM_CTRL0_TRAIN1_REQ_BITS 1 16444 #define DSC_2_1_SM_CTRL0_TRAIN1_REQ_SHIFT 8 16445 16446 /* dsc_2_1 :: sm_ctrl0 :: soft_ack [07:07] */ 16447 #define DSC_2_1_SM_CTRL0_SOFT_ACK_MASK 0x0080 16448 #define DSC_2_1_SM_CTRL0_SOFT_ACK_ALIGN 0 16449 #define DSC_2_1_SM_CTRL0_SOFT_ACK_BITS 1 16450 #define DSC_2_1_SM_CTRL0_SOFT_ACK_SHIFT 7 16451 16452 /* dsc_2_1 :: sm_ctrl0 :: train_mode_en [06:06] */ 16453 #define DSC_2_1_SM_CTRL0_TRAIN_MODE_EN_MASK 0x0040 16454 #define DSC_2_1_SM_CTRL0_TRAIN_MODE_EN_ALIGN 0 16455 #define DSC_2_1_SM_CTRL0_TRAIN_MODE_EN_BITS 1 16456 #define DSC_2_1_SM_CTRL0_TRAIN_MODE_EN_SHIFT 6 16457 16458 /* dsc_2_1 :: sm_ctrl0 :: vga_frzval [05:05] */ 16459 #define DSC_2_1_SM_CTRL0_VGA_FRZVAL_MASK 0x0020 16460 #define DSC_2_1_SM_CTRL0_VGA_FRZVAL_ALIGN 0 16461 #define DSC_2_1_SM_CTRL0_VGA_FRZVAL_BITS 1 16462 #define DSC_2_1_SM_CTRL0_VGA_FRZVAL_SHIFT 5 16463 16464 /* dsc_2_1 :: sm_ctrl0 :: vga_frcfrz [04:04] */ 16465 #define DSC_2_1_SM_CTRL0_VGA_FRCFRZ_MASK 0x0010 16466 #define DSC_2_1_SM_CTRL0_VGA_FRCFRZ_ALIGN 0 16467 #define DSC_2_1_SM_CTRL0_VGA_FRCFRZ_BITS 1 16468 #define DSC_2_1_SM_CTRL0_VGA_FRCFRZ_SHIFT 4 16469 16470 /* dsc_2_1 :: sm_ctrl0 :: dfe_frzval [03:03] */ 16471 #define DSC_2_1_SM_CTRL0_DFE_FRZVAL_MASK 0x0008 16472 #define DSC_2_1_SM_CTRL0_DFE_FRZVAL_ALIGN 0 16473 #define DSC_2_1_SM_CTRL0_DFE_FRZVAL_BITS 1 16474 #define DSC_2_1_SM_CTRL0_DFE_FRZVAL_SHIFT 3 16475 16476 /* dsc_2_1 :: sm_ctrl0 :: dfe_frcfrz [02:02] */ 16477 #define DSC_2_1_SM_CTRL0_DFE_FRCFRZ_MASK 0x0004 16478 #define DSC_2_1_SM_CTRL0_DFE_FRCFRZ_ALIGN 0 16479 #define DSC_2_1_SM_CTRL0_DFE_FRCFRZ_BITS 1 16480 #define DSC_2_1_SM_CTRL0_DFE_FRCFRZ_SHIFT 2 16481 16482 /* dsc_2_1 :: sm_ctrl0 :: dsc_clr_val [01:01] */ 16483 #define DSC_2_1_SM_CTRL0_DSC_CLR_VAL_MASK 0x0002 16484 #define DSC_2_1_SM_CTRL0_DSC_CLR_VAL_ALIGN 0 16485 #define DSC_2_1_SM_CTRL0_DSC_CLR_VAL_BITS 1 16486 #define DSC_2_1_SM_CTRL0_DSC_CLR_VAL_SHIFT 1 16487 16488 /* dsc_2_1 :: sm_ctrl0 :: dsc_clr_frc [00:00] */ 16489 #define DSC_2_1_SM_CTRL0_DSC_CLR_FRC_MASK 0x0001 16490 #define DSC_2_1_SM_CTRL0_DSC_CLR_FRC_ALIGN 0 16491 #define DSC_2_1_SM_CTRL0_DSC_CLR_FRC_BITS 1 16492 #define DSC_2_1_SM_CTRL0_DSC_CLR_FRC_SHIFT 0 16493 16494 16495 /**************************************************************************** 16496 * dsc_2_1 :: sm_ctrl1 16497 */ 16498 /* dsc_2_1 :: sm_ctrl1 :: fast_timer [15:15] */ 16499 #define DSC_2_1_SM_CTRL1_FAST_TIMER_MASK 0x8000 16500 #define DSC_2_1_SM_CTRL1_FAST_TIMER_ALIGN 0 16501 #define DSC_2_1_SM_CTRL1_FAST_TIMER_BITS 1 16502 #define DSC_2_1_SM_CTRL1_FAST_TIMER_SHIFT 15 16503 16504 /* dsc_2_1 :: sm_ctrl1 :: acq2_timeout [14:10] */ 16505 #define DSC_2_1_SM_CTRL1_ACQ2_TIMEOUT_MASK 0x7c00 16506 #define DSC_2_1_SM_CTRL1_ACQ2_TIMEOUT_ALIGN 0 16507 #define DSC_2_1_SM_CTRL1_ACQ2_TIMEOUT_BITS 5 16508 #define DSC_2_1_SM_CTRL1_ACQ2_TIMEOUT_SHIFT 10 16509 16510 /* dsc_2_1 :: sm_ctrl1 :: acq1_timeout [09:05] */ 16511 #define DSC_2_1_SM_CTRL1_ACQ1_TIMEOUT_MASK 0x03e0 16512 #define DSC_2_1_SM_CTRL1_ACQ1_TIMEOUT_ALIGN 0 16513 #define DSC_2_1_SM_CTRL1_ACQ1_TIMEOUT_BITS 5 16514 #define DSC_2_1_SM_CTRL1_ACQ1_TIMEOUT_SHIFT 5 16515 16516 /* dsc_2_1 :: sm_ctrl1 :: acqcdr_timeout [04:00] */ 16517 #define DSC_2_1_SM_CTRL1_ACQCDR_TIMEOUT_MASK 0x001f 16518 #define DSC_2_1_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN 0 16519 #define DSC_2_1_SM_CTRL1_ACQCDR_TIMEOUT_BITS 5 16520 #define DSC_2_1_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT 0 16521 16522 16523 /**************************************************************************** 16524 * dsc_2_1 :: sm_ctrl2 16525 */ 16526 /* dsc_2_1 :: sm_ctrl2 :: reserved_for_eco0 [15:15] */ 16527 #define DSC_2_1_SM_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 16528 #define DSC_2_1_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 16529 #define DSC_2_1_SM_CTRL2_RESERVED_FOR_ECO0_BITS 1 16530 #define DSC_2_1_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 16531 16532 /* dsc_2_1 :: sm_ctrl2 :: cdrbr_bwsel_prop_acqcdr [14:12] */ 16533 #define DSC_2_1_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x7000 16534 #define DSC_2_1_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 16535 #define DSC_2_1_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 16536 #define DSC_2_1_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 12 16537 16538 /* dsc_2_1 :: sm_ctrl2 :: dfe_gain_acq2 [11:10] */ 16539 #define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ2_MASK 0x0c00 16540 #define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ2_ALIGN 0 16541 #define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ2_BITS 2 16542 #define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ2_SHIFT 10 16543 16544 /* dsc_2_1 :: sm_ctrl2 :: dfe_gain_acq1 [09:08] */ 16545 #define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ1_MASK 0x0300 16546 #define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ1_ALIGN 0 16547 #define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ1_BITS 2 16548 #define DSC_2_1_SM_CTRL2_DFE_GAIN_ACQ1_SHIFT 8 16549 16550 /* dsc_2_1 :: sm_ctrl2 :: vga_gain_acq2 [07:06] */ 16551 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ2_MASK 0x00c0 16552 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ2_ALIGN 0 16553 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ2_BITS 2 16554 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ2_SHIFT 6 16555 16556 /* dsc_2_1 :: sm_ctrl2 :: vga_gain_acq1 [05:04] */ 16557 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ1_MASK 0x0030 16558 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ1_ALIGN 0 16559 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ1_BITS 2 16560 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQ1_SHIFT 4 16561 16562 /* dsc_2_1 :: sm_ctrl2 :: vga_gain_acqcdr [03:02] */ 16563 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQCDR_MASK 0x000c 16564 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQCDR_ALIGN 0 16565 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQCDR_BITS 2 16566 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQCDR_SHIFT 2 16567 16568 /* dsc_2_1 :: sm_ctrl2 :: vga_gain_acqvga [01:00] */ 16569 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQVGA_MASK 0x0003 16570 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQVGA_ALIGN 0 16571 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQVGA_BITS 2 16572 #define DSC_2_1_SM_CTRL2_VGA_GAIN_ACQVGA_SHIFT 0 16573 16574 16575 /**************************************************************************** 16576 * dsc_2_1 :: sm_ctrl3 16577 */ 16578 /* dsc_2_1 :: sm_ctrl3 :: reserved_for_eco0 [15:12] */ 16579 #define DSC_2_1_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0xf000 16580 #define DSC_2_1_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 16581 #define DSC_2_1_SM_CTRL3_RESERVED_FOR_ECO0_BITS 4 16582 #define DSC_2_1_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 12 16583 16584 /* dsc_2_1 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq2 [11:10] */ 16585 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0c00 16586 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 16587 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_BITS 2 16588 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 10 16589 16590 /* dsc_2_1 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq1 [09:08] */ 16591 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x0300 16592 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 16593 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_BITS 2 16594 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 8 16595 16596 /* dsc_2_1 :: sm_ctrl3 :: cdrbr_bwsel_integ_acqcdr [07:06] */ 16597 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x00c0 16598 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 16599 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_BITS 2 16600 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 6 16601 16602 /* dsc_2_1 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq2 [05:03] */ 16603 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0038 16604 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 16605 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_BITS 3 16606 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_SHIFT 3 16607 16608 /* dsc_2_1 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq1 [02:00] */ 16609 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_MASK 0x0007 16610 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 16611 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_BITS 3 16612 #define DSC_2_1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_SHIFT 0 16613 16614 16615 /**************************************************************************** 16616 * dsc_2_1 :: sm_ctrl4 16617 */ 16618 /* dsc_2_1 :: sm_ctrl4 :: cdros_bwsel_integ_acq1_2 [15:12] */ 16619 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0xf000 16620 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 16621 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 16622 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 12 16623 16624 /* dsc_2_1 :: sm_ctrl4 :: cdros_bwsel_integ_acqcdr [11:08] */ 16625 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x0f00 16626 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 16627 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 16628 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 8 16629 16630 /* dsc_2_1 :: sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [07:04] */ 16631 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x00f0 16632 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 16633 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 16634 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 4 16635 16636 /* dsc_2_1 :: sm_ctrl4 :: cdros_bwsel_prop_acqcdr [03:00] */ 16637 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK 0x000f 16638 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 16639 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS 4 16640 #define DSC_2_1_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT 0 16641 16642 16643 /**************************************************************************** 16644 * dsc_2_1 :: dsc_status0 16645 */ 16646 /* dsc_2_1 :: dsc_status0 :: data_15_to_0 [15:00] */ 16647 #define DSC_2_1_DSC_STATUS0_DATA_15_TO_0_MASK 0xffff 16648 #define DSC_2_1_DSC_STATUS0_DATA_15_TO_0_ALIGN 0 16649 #define DSC_2_1_DSC_STATUS0_DATA_15_TO_0_BITS 16 16650 #define DSC_2_1_DSC_STATUS0_DATA_15_TO_0_SHIFT 0 16651 16652 16653 /**************************************************************************** 16654 * dsc_2_1 :: dsc_status1 16655 */ 16656 /* dsc_2_1 :: dsc_status1 :: p1err_11_to_0 [15:04] */ 16657 #define DSC_2_1_DSC_STATUS1_P1ERR_11_TO_0_MASK 0xfff0 16658 #define DSC_2_1_DSC_STATUS1_P1ERR_11_TO_0_ALIGN 0 16659 #define DSC_2_1_DSC_STATUS1_P1ERR_11_TO_0_BITS 12 16660 #define DSC_2_1_DSC_STATUS1_P1ERR_11_TO_0_SHIFT 4 16661 16662 /* dsc_2_1 :: dsc_status1 :: data_19_to_16 [03:00] */ 16663 #define DSC_2_1_DSC_STATUS1_DATA_19_TO_16_MASK 0x000f 16664 #define DSC_2_1_DSC_STATUS1_DATA_19_TO_16_ALIGN 0 16665 #define DSC_2_1_DSC_STATUS1_DATA_19_TO_16_BITS 4 16666 #define DSC_2_1_DSC_STATUS1_DATA_19_TO_16_SHIFT 0 16667 16668 16669 /**************************************************************************** 16670 * dsc_2_1 :: dsc_status2 16671 */ 16672 /* dsc_2_1 :: dsc_status2 :: m1err_7_to_0 [15:08] */ 16673 #define DSC_2_1_DSC_STATUS2_M1ERR_7_TO_0_MASK 0xff00 16674 #define DSC_2_1_DSC_STATUS2_M1ERR_7_TO_0_ALIGN 0 16675 #define DSC_2_1_DSC_STATUS2_M1ERR_7_TO_0_BITS 8 16676 #define DSC_2_1_DSC_STATUS2_M1ERR_7_TO_0_SHIFT 8 16677 16678 /* dsc_2_1 :: dsc_status2 :: p1err_19_to_12 [07:00] */ 16679 #define DSC_2_1_DSC_STATUS2_P1ERR_19_TO_12_MASK 0x00ff 16680 #define DSC_2_1_DSC_STATUS2_P1ERR_19_TO_12_ALIGN 0 16681 #define DSC_2_1_DSC_STATUS2_P1ERR_19_TO_12_BITS 8 16682 #define DSC_2_1_DSC_STATUS2_P1ERR_19_TO_12_SHIFT 0 16683 16684 16685 /**************************************************************************** 16686 * dsc_2_1 :: dsc_status3 16687 */ 16688 /* dsc_2_1 :: dsc_status3 :: reserved_for_eco0 [15:12] */ 16689 #define DSC_2_1_DSC_STATUS3_RESERVED_FOR_ECO0_MASK 0xf000 16690 #define DSC_2_1_DSC_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 16691 #define DSC_2_1_DSC_STATUS3_RESERVED_FOR_ECO0_BITS 4 16692 #define DSC_2_1_DSC_STATUS3_RESERVED_FOR_ECO0_SHIFT 12 16693 16694 /* dsc_2_1 :: dsc_status3 :: m1err_19_to_8 [11:00] */ 16695 #define DSC_2_1_DSC_STATUS3_M1ERR_19_TO_8_MASK 0x0fff 16696 #define DSC_2_1_DSC_STATUS3_M1ERR_19_TO_8_ALIGN 0 16697 #define DSC_2_1_DSC_STATUS3_M1ERR_19_TO_8_BITS 12 16698 #define DSC_2_1_DSC_STATUS3_M1ERR_19_TO_8_SHIFT 0 16699 16700 16701 /**************************************************************************** 16702 * dsc_2_1 :: dsc_ctrl0 16703 */ 16704 /* dsc_2_1 :: dsc_ctrl0 :: rxSeqStart [15:15] */ 16705 #define DSC_2_1_DSC_CTRL0_RXSEQSTART_MASK 0x8000 16706 #define DSC_2_1_DSC_CTRL0_RXSEQSTART_ALIGN 0 16707 #define DSC_2_1_DSC_CTRL0_RXSEQSTART_BITS 1 16708 #define DSC_2_1_DSC_CTRL0_RXSEQSTART_SHIFT 15 16709 16710 /* dsc_2_1 :: dsc_ctrl0 :: forceRxSeqDone [14:14] */ 16711 #define DSC_2_1_DSC_CTRL0_FORCERXSEQDONE_MASK 0x4000 16712 #define DSC_2_1_DSC_CTRL0_FORCERXSEQDONE_ALIGN 0 16713 #define DSC_2_1_DSC_CTRL0_FORCERXSEQDONE_BITS 1 16714 #define DSC_2_1_DSC_CTRL0_FORCERXSEQDONE_SHIFT 14 16715 16716 /* dsc_2_1 :: dsc_ctrl0 :: test_bus_sel [13:10] */ 16717 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_MASK 0x3c00 16718 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_ALIGN 0 16719 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_BITS 4 16720 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_SHIFT 10 16721 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_Off 0 16722 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_OSx2data 1 16723 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 16724 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 16725 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 16726 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_cdrIntg 6 16727 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 16728 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 16729 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 16730 #define DSC_2_1_DSC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 16731 16732 /* dsc_2_1 :: dsc_ctrl0 :: rx_m1_thresh_zero [09:09] */ 16733 #define DSC_2_1_DSC_CTRL0_RX_M1_THRESH_ZERO_MASK 0x0200 16734 #define DSC_2_1_DSC_CTRL0_RX_M1_THRESH_ZERO_ALIGN 0 16735 #define DSC_2_1_DSC_CTRL0_RX_M1_THRESH_ZERO_BITS 1 16736 #define DSC_2_1_DSC_CTRL0_RX_M1_THRESH_ZERO_SHIFT 9 16737 16738 /* dsc_2_1 :: dsc_ctrl0 :: rx_thresh_sel [08:07] */ 16739 #define DSC_2_1_DSC_CTRL0_RX_THRESH_SEL_MASK 0x0180 16740 #define DSC_2_1_DSC_CTRL0_RX_THRESH_SEL_ALIGN 0 16741 #define DSC_2_1_DSC_CTRL0_RX_THRESH_SEL_BITS 2 16742 #define DSC_2_1_DSC_CTRL0_RX_THRESH_SEL_SHIFT 7 16743 16744 /* dsc_2_1 :: dsc_ctrl0 :: rx_pf_ctrl [06:04] */ 16745 #define DSC_2_1_DSC_CTRL0_RX_PF_CTRL_MASK 0x0070 16746 #define DSC_2_1_DSC_CTRL0_RX_PF_CTRL_ALIGN 0 16747 #define DSC_2_1_DSC_CTRL0_RX_PF_CTRL_BITS 3 16748 #define DSC_2_1_DSC_CTRL0_RX_PF_CTRL_SHIFT 4 16749 16750 /* dsc_2_1 :: dsc_ctrl0 :: cdrbr_sel [03:03] */ 16751 #define DSC_2_1_DSC_CTRL0_CDRBR_SEL_MASK 0x0008 16752 #define DSC_2_1_DSC_CTRL0_CDRBR_SEL_ALIGN 0 16753 #define DSC_2_1_DSC_CTRL0_CDRBR_SEL_BITS 1 16754 #define DSC_2_1_DSC_CTRL0_CDRBR_SEL_SHIFT 3 16755 16756 /* dsc_2_1 :: dsc_ctrl0 :: oscdr_force_mode_en [02:02] */ 16757 #define DSC_2_1_DSC_CTRL0_OSCDR_FORCE_MODE_EN_MASK 0x0004 16758 #define DSC_2_1_DSC_CTRL0_OSCDR_FORCE_MODE_EN_ALIGN 0 16759 #define DSC_2_1_DSC_CTRL0_OSCDR_FORCE_MODE_EN_BITS 1 16760 #define DSC_2_1_DSC_CTRL0_OSCDR_FORCE_MODE_EN_SHIFT 2 16761 16762 /* dsc_2_1 :: dsc_ctrl0 :: oscdr_mode [01:00] */ 16763 #define DSC_2_1_DSC_CTRL0_OSCDR_MODE_MASK 0x0003 16764 #define DSC_2_1_DSC_CTRL0_OSCDR_MODE_ALIGN 0 16765 #define DSC_2_1_DSC_CTRL0_OSCDR_MODE_BITS 2 16766 #define DSC_2_1_DSC_CTRL0_OSCDR_MODE_SHIFT 0 16767 16768 16769 /**************************************************************************** 16770 * dsc_2_1 :: dsc_ctrl1 16771 */ 16772 /* dsc_2_1 :: dsc_ctrl1 :: reserved_for_eco0 [15:15] */ 16773 #define DSC_2_1_DSC_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 16774 #define DSC_2_1_DSC_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 16775 #define DSC_2_1_DSC_CTRL1_RESERVED_FOR_ECO0_BITS 1 16776 #define DSC_2_1_DSC_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 16777 16778 /* dsc_2_1 :: dsc_ctrl1 :: p1_odd_ctrl [14:10] */ 16779 #define DSC_2_1_DSC_CTRL1_P1_ODD_CTRL_MASK 0x7c00 16780 #define DSC_2_1_DSC_CTRL1_P1_ODD_CTRL_ALIGN 0 16781 #define DSC_2_1_DSC_CTRL1_P1_ODD_CTRL_BITS 5 16782 #define DSC_2_1_DSC_CTRL1_P1_ODD_CTRL_SHIFT 10 16783 16784 /* dsc_2_1 :: dsc_ctrl1 :: p1_evn_ctrl [09:05] */ 16785 #define DSC_2_1_DSC_CTRL1_P1_EVN_CTRL_MASK 0x03e0 16786 #define DSC_2_1_DSC_CTRL1_P1_EVN_CTRL_ALIGN 0 16787 #define DSC_2_1_DSC_CTRL1_P1_EVN_CTRL_BITS 5 16788 #define DSC_2_1_DSC_CTRL1_P1_EVN_CTRL_SHIFT 5 16789 16790 /* dsc_2_1 :: dsc_ctrl1 :: d_odd_ctrl [04:00] */ 16791 #define DSC_2_1_DSC_CTRL1_D_ODD_CTRL_MASK 0x001f 16792 #define DSC_2_1_DSC_CTRL1_D_ODD_CTRL_ALIGN 0 16793 #define DSC_2_1_DSC_CTRL1_D_ODD_CTRL_BITS 5 16794 #define DSC_2_1_DSC_CTRL1_D_ODD_CTRL_SHIFT 0 16795 16796 16797 /**************************************************************************** 16798 * dsc_2_1 :: dsc_ctrl2 16799 */ 16800 /* dsc_2_1 :: dsc_ctrl2 :: reserved_for_eco0 [15:15] */ 16801 #define DSC_2_1_DSC_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 16802 #define DSC_2_1_DSC_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 16803 #define DSC_2_1_DSC_CTRL2_RESERVED_FOR_ECO0_BITS 1 16804 #define DSC_2_1_DSC_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 16805 16806 /* dsc_2_1 :: dsc_ctrl2 :: d_evn_ctrl [14:10] */ 16807 #define DSC_2_1_DSC_CTRL2_D_EVN_CTRL_MASK 0x7c00 16808 #define DSC_2_1_DSC_CTRL2_D_EVN_CTRL_ALIGN 0 16809 #define DSC_2_1_DSC_CTRL2_D_EVN_CTRL_BITS 5 16810 #define DSC_2_1_DSC_CTRL2_D_EVN_CTRL_SHIFT 10 16811 16812 /* dsc_2_1 :: dsc_ctrl2 :: m1_odd_ctrl [09:05] */ 16813 #define DSC_2_1_DSC_CTRL2_M1_ODD_CTRL_MASK 0x03e0 16814 #define DSC_2_1_DSC_CTRL2_M1_ODD_CTRL_ALIGN 0 16815 #define DSC_2_1_DSC_CTRL2_M1_ODD_CTRL_BITS 5 16816 #define DSC_2_1_DSC_CTRL2_M1_ODD_CTRL_SHIFT 5 16817 16818 /* dsc_2_1 :: dsc_ctrl2 :: m1_evn_ctrl [04:00] */ 16819 #define DSC_2_1_DSC_CTRL2_M1_EVN_CTRL_MASK 0x001f 16820 #define DSC_2_1_DSC_CTRL2_M1_EVN_CTRL_ALIGN 0 16821 #define DSC_2_1_DSC_CTRL2_M1_EVN_CTRL_BITS 5 16822 #define DSC_2_1_DSC_CTRL2_M1_EVN_CTRL_SHIFT 0 16823 16824 16825 /**************************************************************************** 16826 * XGXS16G_USER_dsc_2_2 16827 */ 16828 /**************************************************************************** 16829 * dsc_2_2 :: sm_status0 16830 */ 16831 /* dsc_2_2 :: sm_status0 :: reserved_for_eco0 [15:04] */ 16832 #define DSC_2_2_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xfff0 16833 #define DSC_2_2_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 16834 #define DSC_2_2_SM_STATUS0_RESERVED_FOR_ECO0_BITS 12 16835 #define DSC_2_2_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 4 16836 16837 /* dsc_2_2 :: sm_status0 :: dsc_state [03:00] */ 16838 #define DSC_2_2_SM_STATUS0_DSC_STATE_MASK 0x000f 16839 #define DSC_2_2_SM_STATUS0_DSC_STATE_ALIGN 0 16840 #define DSC_2_2_SM_STATUS0_DSC_STATE_BITS 4 16841 #define DSC_2_2_SM_STATUS0_DSC_STATE_SHIFT 0 16842 16843 16844 /**************************************************************************** 16845 * dsc_2_2 :: sm_ctrl0 16846 */ 16847 /* dsc_2_2 :: sm_ctrl0 :: acqvga_timeout [15:11] */ 16848 #define DSC_2_2_SM_CTRL0_ACQVGA_TIMEOUT_MASK 0xf800 16849 #define DSC_2_2_SM_CTRL0_ACQVGA_TIMEOUT_ALIGN 0 16850 #define DSC_2_2_SM_CTRL0_ACQVGA_TIMEOUT_BITS 5 16851 #define DSC_2_2_SM_CTRL0_ACQVGA_TIMEOUT_SHIFT 11 16852 16853 /* dsc_2_2 :: sm_ctrl0 :: tuning_sm_en [10:10] */ 16854 #define DSC_2_2_SM_CTRL0_TUNING_SM_EN_MASK 0x0400 16855 #define DSC_2_2_SM_CTRL0_TUNING_SM_EN_ALIGN 0 16856 #define DSC_2_2_SM_CTRL0_TUNING_SM_EN_BITS 1 16857 #define DSC_2_2_SM_CTRL0_TUNING_SM_EN_SHIFT 10 16858 16859 /* dsc_2_2 :: sm_ctrl0 :: train2_req [09:09] */ 16860 #define DSC_2_2_SM_CTRL0_TRAIN2_REQ_MASK 0x0200 16861 #define DSC_2_2_SM_CTRL0_TRAIN2_REQ_ALIGN 0 16862 #define DSC_2_2_SM_CTRL0_TRAIN2_REQ_BITS 1 16863 #define DSC_2_2_SM_CTRL0_TRAIN2_REQ_SHIFT 9 16864 16865 /* dsc_2_2 :: sm_ctrl0 :: train1_req [08:08] */ 16866 #define DSC_2_2_SM_CTRL0_TRAIN1_REQ_MASK 0x0100 16867 #define DSC_2_2_SM_CTRL0_TRAIN1_REQ_ALIGN 0 16868 #define DSC_2_2_SM_CTRL0_TRAIN1_REQ_BITS 1 16869 #define DSC_2_2_SM_CTRL0_TRAIN1_REQ_SHIFT 8 16870 16871 /* dsc_2_2 :: sm_ctrl0 :: soft_ack [07:07] */ 16872 #define DSC_2_2_SM_CTRL0_SOFT_ACK_MASK 0x0080 16873 #define DSC_2_2_SM_CTRL0_SOFT_ACK_ALIGN 0 16874 #define DSC_2_2_SM_CTRL0_SOFT_ACK_BITS 1 16875 #define DSC_2_2_SM_CTRL0_SOFT_ACK_SHIFT 7 16876 16877 /* dsc_2_2 :: sm_ctrl0 :: train_mode_en [06:06] */ 16878 #define DSC_2_2_SM_CTRL0_TRAIN_MODE_EN_MASK 0x0040 16879 #define DSC_2_2_SM_CTRL0_TRAIN_MODE_EN_ALIGN 0 16880 #define DSC_2_2_SM_CTRL0_TRAIN_MODE_EN_BITS 1 16881 #define DSC_2_2_SM_CTRL0_TRAIN_MODE_EN_SHIFT 6 16882 16883 /* dsc_2_2 :: sm_ctrl0 :: vga_frzval [05:05] */ 16884 #define DSC_2_2_SM_CTRL0_VGA_FRZVAL_MASK 0x0020 16885 #define DSC_2_2_SM_CTRL0_VGA_FRZVAL_ALIGN 0 16886 #define DSC_2_2_SM_CTRL0_VGA_FRZVAL_BITS 1 16887 #define DSC_2_2_SM_CTRL0_VGA_FRZVAL_SHIFT 5 16888 16889 /* dsc_2_2 :: sm_ctrl0 :: vga_frcfrz [04:04] */ 16890 #define DSC_2_2_SM_CTRL0_VGA_FRCFRZ_MASK 0x0010 16891 #define DSC_2_2_SM_CTRL0_VGA_FRCFRZ_ALIGN 0 16892 #define DSC_2_2_SM_CTRL0_VGA_FRCFRZ_BITS 1 16893 #define DSC_2_2_SM_CTRL0_VGA_FRCFRZ_SHIFT 4 16894 16895 /* dsc_2_2 :: sm_ctrl0 :: dfe_frzval [03:03] */ 16896 #define DSC_2_2_SM_CTRL0_DFE_FRZVAL_MASK 0x0008 16897 #define DSC_2_2_SM_CTRL0_DFE_FRZVAL_ALIGN 0 16898 #define DSC_2_2_SM_CTRL0_DFE_FRZVAL_BITS 1 16899 #define DSC_2_2_SM_CTRL0_DFE_FRZVAL_SHIFT 3 16900 16901 /* dsc_2_2 :: sm_ctrl0 :: dfe_frcfrz [02:02] */ 16902 #define DSC_2_2_SM_CTRL0_DFE_FRCFRZ_MASK 0x0004 16903 #define DSC_2_2_SM_CTRL0_DFE_FRCFRZ_ALIGN 0 16904 #define DSC_2_2_SM_CTRL0_DFE_FRCFRZ_BITS 1 16905 #define DSC_2_2_SM_CTRL0_DFE_FRCFRZ_SHIFT 2 16906 16907 /* dsc_2_2 :: sm_ctrl0 :: dsc_clr_val [01:01] */ 16908 #define DSC_2_2_SM_CTRL0_DSC_CLR_VAL_MASK 0x0002 16909 #define DSC_2_2_SM_CTRL0_DSC_CLR_VAL_ALIGN 0 16910 #define DSC_2_2_SM_CTRL0_DSC_CLR_VAL_BITS 1 16911 #define DSC_2_2_SM_CTRL0_DSC_CLR_VAL_SHIFT 1 16912 16913 /* dsc_2_2 :: sm_ctrl0 :: dsc_clr_frc [00:00] */ 16914 #define DSC_2_2_SM_CTRL0_DSC_CLR_FRC_MASK 0x0001 16915 #define DSC_2_2_SM_CTRL0_DSC_CLR_FRC_ALIGN 0 16916 #define DSC_2_2_SM_CTRL0_DSC_CLR_FRC_BITS 1 16917 #define DSC_2_2_SM_CTRL0_DSC_CLR_FRC_SHIFT 0 16918 16919 16920 /**************************************************************************** 16921 * dsc_2_2 :: sm_ctrl1 16922 */ 16923 /* dsc_2_2 :: sm_ctrl1 :: fast_timer [15:15] */ 16924 #define DSC_2_2_SM_CTRL1_FAST_TIMER_MASK 0x8000 16925 #define DSC_2_2_SM_CTRL1_FAST_TIMER_ALIGN 0 16926 #define DSC_2_2_SM_CTRL1_FAST_TIMER_BITS 1 16927 #define DSC_2_2_SM_CTRL1_FAST_TIMER_SHIFT 15 16928 16929 /* dsc_2_2 :: sm_ctrl1 :: acq2_timeout [14:10] */ 16930 #define DSC_2_2_SM_CTRL1_ACQ2_TIMEOUT_MASK 0x7c00 16931 #define DSC_2_2_SM_CTRL1_ACQ2_TIMEOUT_ALIGN 0 16932 #define DSC_2_2_SM_CTRL1_ACQ2_TIMEOUT_BITS 5 16933 #define DSC_2_2_SM_CTRL1_ACQ2_TIMEOUT_SHIFT 10 16934 16935 /* dsc_2_2 :: sm_ctrl1 :: acq1_timeout [09:05] */ 16936 #define DSC_2_2_SM_CTRL1_ACQ1_TIMEOUT_MASK 0x03e0 16937 #define DSC_2_2_SM_CTRL1_ACQ1_TIMEOUT_ALIGN 0 16938 #define DSC_2_2_SM_CTRL1_ACQ1_TIMEOUT_BITS 5 16939 #define DSC_2_2_SM_CTRL1_ACQ1_TIMEOUT_SHIFT 5 16940 16941 /* dsc_2_2 :: sm_ctrl1 :: acqcdr_timeout [04:00] */ 16942 #define DSC_2_2_SM_CTRL1_ACQCDR_TIMEOUT_MASK 0x001f 16943 #define DSC_2_2_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN 0 16944 #define DSC_2_2_SM_CTRL1_ACQCDR_TIMEOUT_BITS 5 16945 #define DSC_2_2_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT 0 16946 16947 16948 /**************************************************************************** 16949 * dsc_2_2 :: sm_ctrl2 16950 */ 16951 /* dsc_2_2 :: sm_ctrl2 :: reserved_for_eco0 [15:15] */ 16952 #define DSC_2_2_SM_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 16953 #define DSC_2_2_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 16954 #define DSC_2_2_SM_CTRL2_RESERVED_FOR_ECO0_BITS 1 16955 #define DSC_2_2_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 16956 16957 /* dsc_2_2 :: sm_ctrl2 :: cdrbr_bwsel_prop_acqcdr [14:12] */ 16958 #define DSC_2_2_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x7000 16959 #define DSC_2_2_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 16960 #define DSC_2_2_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 16961 #define DSC_2_2_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 12 16962 16963 /* dsc_2_2 :: sm_ctrl2 :: dfe_gain_acq2 [11:10] */ 16964 #define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ2_MASK 0x0c00 16965 #define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ2_ALIGN 0 16966 #define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ2_BITS 2 16967 #define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ2_SHIFT 10 16968 16969 /* dsc_2_2 :: sm_ctrl2 :: dfe_gain_acq1 [09:08] */ 16970 #define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ1_MASK 0x0300 16971 #define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ1_ALIGN 0 16972 #define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ1_BITS 2 16973 #define DSC_2_2_SM_CTRL2_DFE_GAIN_ACQ1_SHIFT 8 16974 16975 /* dsc_2_2 :: sm_ctrl2 :: vga_gain_acq2 [07:06] */ 16976 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ2_MASK 0x00c0 16977 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ2_ALIGN 0 16978 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ2_BITS 2 16979 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ2_SHIFT 6 16980 16981 /* dsc_2_2 :: sm_ctrl2 :: vga_gain_acq1 [05:04] */ 16982 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ1_MASK 0x0030 16983 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ1_ALIGN 0 16984 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ1_BITS 2 16985 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQ1_SHIFT 4 16986 16987 /* dsc_2_2 :: sm_ctrl2 :: vga_gain_acqcdr [03:02] */ 16988 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQCDR_MASK 0x000c 16989 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQCDR_ALIGN 0 16990 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQCDR_BITS 2 16991 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQCDR_SHIFT 2 16992 16993 /* dsc_2_2 :: sm_ctrl2 :: vga_gain_acqvga [01:00] */ 16994 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQVGA_MASK 0x0003 16995 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQVGA_ALIGN 0 16996 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQVGA_BITS 2 16997 #define DSC_2_2_SM_CTRL2_VGA_GAIN_ACQVGA_SHIFT 0 16998 16999 17000 /**************************************************************************** 17001 * dsc_2_2 :: sm_ctrl3 17002 */ 17003 /* dsc_2_2 :: sm_ctrl3 :: reserved_for_eco0 [15:12] */ 17004 #define DSC_2_2_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0xf000 17005 #define DSC_2_2_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 17006 #define DSC_2_2_SM_CTRL3_RESERVED_FOR_ECO0_BITS 4 17007 #define DSC_2_2_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 12 17008 17009 /* dsc_2_2 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq2 [11:10] */ 17010 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0c00 17011 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 17012 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_BITS 2 17013 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 10 17014 17015 /* dsc_2_2 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq1 [09:08] */ 17016 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x0300 17017 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 17018 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_BITS 2 17019 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 8 17020 17021 /* dsc_2_2 :: sm_ctrl3 :: cdrbr_bwsel_integ_acqcdr [07:06] */ 17022 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x00c0 17023 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 17024 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_BITS 2 17025 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 6 17026 17027 /* dsc_2_2 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq2 [05:03] */ 17028 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0038 17029 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 17030 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_BITS 3 17031 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_SHIFT 3 17032 17033 /* dsc_2_2 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq1 [02:00] */ 17034 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_MASK 0x0007 17035 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 17036 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_BITS 3 17037 #define DSC_2_2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_SHIFT 0 17038 17039 17040 /**************************************************************************** 17041 * dsc_2_2 :: sm_ctrl4 17042 */ 17043 /* dsc_2_2 :: sm_ctrl4 :: cdros_bwsel_integ_acq1_2 [15:12] */ 17044 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0xf000 17045 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 17046 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 17047 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 12 17048 17049 /* dsc_2_2 :: sm_ctrl4 :: cdros_bwsel_integ_acqcdr [11:08] */ 17050 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x0f00 17051 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 17052 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 17053 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 8 17054 17055 /* dsc_2_2 :: sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [07:04] */ 17056 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x00f0 17057 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 17058 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 17059 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 4 17060 17061 /* dsc_2_2 :: sm_ctrl4 :: cdros_bwsel_prop_acqcdr [03:00] */ 17062 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK 0x000f 17063 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 17064 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS 4 17065 #define DSC_2_2_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT 0 17066 17067 17068 /**************************************************************************** 17069 * dsc_2_2 :: dsc_status0 17070 */ 17071 /* dsc_2_2 :: dsc_status0 :: data_15_to_0 [15:00] */ 17072 #define DSC_2_2_DSC_STATUS0_DATA_15_TO_0_MASK 0xffff 17073 #define DSC_2_2_DSC_STATUS0_DATA_15_TO_0_ALIGN 0 17074 #define DSC_2_2_DSC_STATUS0_DATA_15_TO_0_BITS 16 17075 #define DSC_2_2_DSC_STATUS0_DATA_15_TO_0_SHIFT 0 17076 17077 17078 /**************************************************************************** 17079 * dsc_2_2 :: dsc_status1 17080 */ 17081 /* dsc_2_2 :: dsc_status1 :: p1err_11_to_0 [15:04] */ 17082 #define DSC_2_2_DSC_STATUS1_P1ERR_11_TO_0_MASK 0xfff0 17083 #define DSC_2_2_DSC_STATUS1_P1ERR_11_TO_0_ALIGN 0 17084 #define DSC_2_2_DSC_STATUS1_P1ERR_11_TO_0_BITS 12 17085 #define DSC_2_2_DSC_STATUS1_P1ERR_11_TO_0_SHIFT 4 17086 17087 /* dsc_2_2 :: dsc_status1 :: data_19_to_16 [03:00] */ 17088 #define DSC_2_2_DSC_STATUS1_DATA_19_TO_16_MASK 0x000f 17089 #define DSC_2_2_DSC_STATUS1_DATA_19_TO_16_ALIGN 0 17090 #define DSC_2_2_DSC_STATUS1_DATA_19_TO_16_BITS 4 17091 #define DSC_2_2_DSC_STATUS1_DATA_19_TO_16_SHIFT 0 17092 17093 17094 /**************************************************************************** 17095 * dsc_2_2 :: dsc_status2 17096 */ 17097 /* dsc_2_2 :: dsc_status2 :: m1err_7_to_0 [15:08] */ 17098 #define DSC_2_2_DSC_STATUS2_M1ERR_7_TO_0_MASK 0xff00 17099 #define DSC_2_2_DSC_STATUS2_M1ERR_7_TO_0_ALIGN 0 17100 #define DSC_2_2_DSC_STATUS2_M1ERR_7_TO_0_BITS 8 17101 #define DSC_2_2_DSC_STATUS2_M1ERR_7_TO_0_SHIFT 8 17102 17103 /* dsc_2_2 :: dsc_status2 :: p1err_19_to_12 [07:00] */ 17104 #define DSC_2_2_DSC_STATUS2_P1ERR_19_TO_12_MASK 0x00ff 17105 #define DSC_2_2_DSC_STATUS2_P1ERR_19_TO_12_ALIGN 0 17106 #define DSC_2_2_DSC_STATUS2_P1ERR_19_TO_12_BITS 8 17107 #define DSC_2_2_DSC_STATUS2_P1ERR_19_TO_12_SHIFT 0 17108 17109 17110 /**************************************************************************** 17111 * dsc_2_2 :: dsc_status3 17112 */ 17113 /* dsc_2_2 :: dsc_status3 :: reserved_for_eco0 [15:12] */ 17114 #define DSC_2_2_DSC_STATUS3_RESERVED_FOR_ECO0_MASK 0xf000 17115 #define DSC_2_2_DSC_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 17116 #define DSC_2_2_DSC_STATUS3_RESERVED_FOR_ECO0_BITS 4 17117 #define DSC_2_2_DSC_STATUS3_RESERVED_FOR_ECO0_SHIFT 12 17118 17119 /* dsc_2_2 :: dsc_status3 :: m1err_19_to_8 [11:00] */ 17120 #define DSC_2_2_DSC_STATUS3_M1ERR_19_TO_8_MASK 0x0fff 17121 #define DSC_2_2_DSC_STATUS3_M1ERR_19_TO_8_ALIGN 0 17122 #define DSC_2_2_DSC_STATUS3_M1ERR_19_TO_8_BITS 12 17123 #define DSC_2_2_DSC_STATUS3_M1ERR_19_TO_8_SHIFT 0 17124 17125 17126 /**************************************************************************** 17127 * dsc_2_2 :: dsc_ctrl0 17128 */ 17129 /* dsc_2_2 :: dsc_ctrl0 :: rxSeqStart [15:15] */ 17130 #define DSC_2_2_DSC_CTRL0_RXSEQSTART_MASK 0x8000 17131 #define DSC_2_2_DSC_CTRL0_RXSEQSTART_ALIGN 0 17132 #define DSC_2_2_DSC_CTRL0_RXSEQSTART_BITS 1 17133 #define DSC_2_2_DSC_CTRL0_RXSEQSTART_SHIFT 15 17134 17135 /* dsc_2_2 :: dsc_ctrl0 :: forceRxSeqDone [14:14] */ 17136 #define DSC_2_2_DSC_CTRL0_FORCERXSEQDONE_MASK 0x4000 17137 #define DSC_2_2_DSC_CTRL0_FORCERXSEQDONE_ALIGN 0 17138 #define DSC_2_2_DSC_CTRL0_FORCERXSEQDONE_BITS 1 17139 #define DSC_2_2_DSC_CTRL0_FORCERXSEQDONE_SHIFT 14 17140 17141 /* dsc_2_2 :: dsc_ctrl0 :: test_bus_sel [13:10] */ 17142 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_MASK 0x3c00 17143 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_ALIGN 0 17144 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_BITS 4 17145 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_SHIFT 10 17146 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_Off 0 17147 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_OSx2data 1 17148 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 17149 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 17150 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 17151 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_cdrIntg 6 17152 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 17153 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 17154 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 17155 #define DSC_2_2_DSC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 17156 17157 /* dsc_2_2 :: dsc_ctrl0 :: rx_m1_thresh_zero [09:09] */ 17158 #define DSC_2_2_DSC_CTRL0_RX_M1_THRESH_ZERO_MASK 0x0200 17159 #define DSC_2_2_DSC_CTRL0_RX_M1_THRESH_ZERO_ALIGN 0 17160 #define DSC_2_2_DSC_CTRL0_RX_M1_THRESH_ZERO_BITS 1 17161 #define DSC_2_2_DSC_CTRL0_RX_M1_THRESH_ZERO_SHIFT 9 17162 17163 /* dsc_2_2 :: dsc_ctrl0 :: rx_thresh_sel [08:07] */ 17164 #define DSC_2_2_DSC_CTRL0_RX_THRESH_SEL_MASK 0x0180 17165 #define DSC_2_2_DSC_CTRL0_RX_THRESH_SEL_ALIGN 0 17166 #define DSC_2_2_DSC_CTRL0_RX_THRESH_SEL_BITS 2 17167 #define DSC_2_2_DSC_CTRL0_RX_THRESH_SEL_SHIFT 7 17168 17169 /* dsc_2_2 :: dsc_ctrl0 :: rx_pf_ctrl [06:04] */ 17170 #define DSC_2_2_DSC_CTRL0_RX_PF_CTRL_MASK 0x0070 17171 #define DSC_2_2_DSC_CTRL0_RX_PF_CTRL_ALIGN 0 17172 #define DSC_2_2_DSC_CTRL0_RX_PF_CTRL_BITS 3 17173 #define DSC_2_2_DSC_CTRL0_RX_PF_CTRL_SHIFT 4 17174 17175 /* dsc_2_2 :: dsc_ctrl0 :: cdrbr_sel [03:03] */ 17176 #define DSC_2_2_DSC_CTRL0_CDRBR_SEL_MASK 0x0008 17177 #define DSC_2_2_DSC_CTRL0_CDRBR_SEL_ALIGN 0 17178 #define DSC_2_2_DSC_CTRL0_CDRBR_SEL_BITS 1 17179 #define DSC_2_2_DSC_CTRL0_CDRBR_SEL_SHIFT 3 17180 17181 /* dsc_2_2 :: dsc_ctrl0 :: oscdr_force_mode_en [02:02] */ 17182 #define DSC_2_2_DSC_CTRL0_OSCDR_FORCE_MODE_EN_MASK 0x0004 17183 #define DSC_2_2_DSC_CTRL0_OSCDR_FORCE_MODE_EN_ALIGN 0 17184 #define DSC_2_2_DSC_CTRL0_OSCDR_FORCE_MODE_EN_BITS 1 17185 #define DSC_2_2_DSC_CTRL0_OSCDR_FORCE_MODE_EN_SHIFT 2 17186 17187 /* dsc_2_2 :: dsc_ctrl0 :: oscdr_mode [01:00] */ 17188 #define DSC_2_2_DSC_CTRL0_OSCDR_MODE_MASK 0x0003 17189 #define DSC_2_2_DSC_CTRL0_OSCDR_MODE_ALIGN 0 17190 #define DSC_2_2_DSC_CTRL0_OSCDR_MODE_BITS 2 17191 #define DSC_2_2_DSC_CTRL0_OSCDR_MODE_SHIFT 0 17192 17193 17194 /**************************************************************************** 17195 * dsc_2_2 :: dsc_ctrl1 17196 */ 17197 /* dsc_2_2 :: dsc_ctrl1 :: reserved_for_eco0 [15:15] */ 17198 #define DSC_2_2_DSC_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 17199 #define DSC_2_2_DSC_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 17200 #define DSC_2_2_DSC_CTRL1_RESERVED_FOR_ECO0_BITS 1 17201 #define DSC_2_2_DSC_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 17202 17203 /* dsc_2_2 :: dsc_ctrl1 :: p1_odd_ctrl [14:10] */ 17204 #define DSC_2_2_DSC_CTRL1_P1_ODD_CTRL_MASK 0x7c00 17205 #define DSC_2_2_DSC_CTRL1_P1_ODD_CTRL_ALIGN 0 17206 #define DSC_2_2_DSC_CTRL1_P1_ODD_CTRL_BITS 5 17207 #define DSC_2_2_DSC_CTRL1_P1_ODD_CTRL_SHIFT 10 17208 17209 /* dsc_2_2 :: dsc_ctrl1 :: p1_evn_ctrl [09:05] */ 17210 #define DSC_2_2_DSC_CTRL1_P1_EVN_CTRL_MASK 0x03e0 17211 #define DSC_2_2_DSC_CTRL1_P1_EVN_CTRL_ALIGN 0 17212 #define DSC_2_2_DSC_CTRL1_P1_EVN_CTRL_BITS 5 17213 #define DSC_2_2_DSC_CTRL1_P1_EVN_CTRL_SHIFT 5 17214 17215 /* dsc_2_2 :: dsc_ctrl1 :: d_odd_ctrl [04:00] */ 17216 #define DSC_2_2_DSC_CTRL1_D_ODD_CTRL_MASK 0x001f 17217 #define DSC_2_2_DSC_CTRL1_D_ODD_CTRL_ALIGN 0 17218 #define DSC_2_2_DSC_CTRL1_D_ODD_CTRL_BITS 5 17219 #define DSC_2_2_DSC_CTRL1_D_ODD_CTRL_SHIFT 0 17220 17221 17222 /**************************************************************************** 17223 * dsc_2_2 :: dsc_ctrl2 17224 */ 17225 /* dsc_2_2 :: dsc_ctrl2 :: reserved_for_eco0 [15:15] */ 17226 #define DSC_2_2_DSC_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 17227 #define DSC_2_2_DSC_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 17228 #define DSC_2_2_DSC_CTRL2_RESERVED_FOR_ECO0_BITS 1 17229 #define DSC_2_2_DSC_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 17230 17231 /* dsc_2_2 :: dsc_ctrl2 :: d_evn_ctrl [14:10] */ 17232 #define DSC_2_2_DSC_CTRL2_D_EVN_CTRL_MASK 0x7c00 17233 #define DSC_2_2_DSC_CTRL2_D_EVN_CTRL_ALIGN 0 17234 #define DSC_2_2_DSC_CTRL2_D_EVN_CTRL_BITS 5 17235 #define DSC_2_2_DSC_CTRL2_D_EVN_CTRL_SHIFT 10 17236 17237 /* dsc_2_2 :: dsc_ctrl2 :: m1_odd_ctrl [09:05] */ 17238 #define DSC_2_2_DSC_CTRL2_M1_ODD_CTRL_MASK 0x03e0 17239 #define DSC_2_2_DSC_CTRL2_M1_ODD_CTRL_ALIGN 0 17240 #define DSC_2_2_DSC_CTRL2_M1_ODD_CTRL_BITS 5 17241 #define DSC_2_2_DSC_CTRL2_M1_ODD_CTRL_SHIFT 5 17242 17243 /* dsc_2_2 :: dsc_ctrl2 :: m1_evn_ctrl [04:00] */ 17244 #define DSC_2_2_DSC_CTRL2_M1_EVN_CTRL_MASK 0x001f 17245 #define DSC_2_2_DSC_CTRL2_M1_EVN_CTRL_ALIGN 0 17246 #define DSC_2_2_DSC_CTRL2_M1_EVN_CTRL_BITS 5 17247 #define DSC_2_2_DSC_CTRL2_M1_EVN_CTRL_SHIFT 0 17248 17249 17250 /**************************************************************************** 17251 * XGXS16G_USER_dsc_2_3 17252 */ 17253 /**************************************************************************** 17254 * dsc_2_3 :: sm_status0 17255 */ 17256 /* dsc_2_3 :: sm_status0 :: reserved_for_eco0 [15:04] */ 17257 #define DSC_2_3_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xfff0 17258 #define DSC_2_3_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 17259 #define DSC_2_3_SM_STATUS0_RESERVED_FOR_ECO0_BITS 12 17260 #define DSC_2_3_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 4 17261 17262 /* dsc_2_3 :: sm_status0 :: dsc_state [03:00] */ 17263 #define DSC_2_3_SM_STATUS0_DSC_STATE_MASK 0x000f 17264 #define DSC_2_3_SM_STATUS0_DSC_STATE_ALIGN 0 17265 #define DSC_2_3_SM_STATUS0_DSC_STATE_BITS 4 17266 #define DSC_2_3_SM_STATUS0_DSC_STATE_SHIFT 0 17267 17268 17269 /**************************************************************************** 17270 * dsc_2_3 :: sm_ctrl0 17271 */ 17272 /* dsc_2_3 :: sm_ctrl0 :: acqvga_timeout [15:11] */ 17273 #define DSC_2_3_SM_CTRL0_ACQVGA_TIMEOUT_MASK 0xf800 17274 #define DSC_2_3_SM_CTRL0_ACQVGA_TIMEOUT_ALIGN 0 17275 #define DSC_2_3_SM_CTRL0_ACQVGA_TIMEOUT_BITS 5 17276 #define DSC_2_3_SM_CTRL0_ACQVGA_TIMEOUT_SHIFT 11 17277 17278 /* dsc_2_3 :: sm_ctrl0 :: tuning_sm_en [10:10] */ 17279 #define DSC_2_3_SM_CTRL0_TUNING_SM_EN_MASK 0x0400 17280 #define DSC_2_3_SM_CTRL0_TUNING_SM_EN_ALIGN 0 17281 #define DSC_2_3_SM_CTRL0_TUNING_SM_EN_BITS 1 17282 #define DSC_2_3_SM_CTRL0_TUNING_SM_EN_SHIFT 10 17283 17284 /* dsc_2_3 :: sm_ctrl0 :: train2_req [09:09] */ 17285 #define DSC_2_3_SM_CTRL0_TRAIN2_REQ_MASK 0x0200 17286 #define DSC_2_3_SM_CTRL0_TRAIN2_REQ_ALIGN 0 17287 #define DSC_2_3_SM_CTRL0_TRAIN2_REQ_BITS 1 17288 #define DSC_2_3_SM_CTRL0_TRAIN2_REQ_SHIFT 9 17289 17290 /* dsc_2_3 :: sm_ctrl0 :: train1_req [08:08] */ 17291 #define DSC_2_3_SM_CTRL0_TRAIN1_REQ_MASK 0x0100 17292 #define DSC_2_3_SM_CTRL0_TRAIN1_REQ_ALIGN 0 17293 #define DSC_2_3_SM_CTRL0_TRAIN1_REQ_BITS 1 17294 #define DSC_2_3_SM_CTRL0_TRAIN1_REQ_SHIFT 8 17295 17296 /* dsc_2_3 :: sm_ctrl0 :: soft_ack [07:07] */ 17297 #define DSC_2_3_SM_CTRL0_SOFT_ACK_MASK 0x0080 17298 #define DSC_2_3_SM_CTRL0_SOFT_ACK_ALIGN 0 17299 #define DSC_2_3_SM_CTRL0_SOFT_ACK_BITS 1 17300 #define DSC_2_3_SM_CTRL0_SOFT_ACK_SHIFT 7 17301 17302 /* dsc_2_3 :: sm_ctrl0 :: train_mode_en [06:06] */ 17303 #define DSC_2_3_SM_CTRL0_TRAIN_MODE_EN_MASK 0x0040 17304 #define DSC_2_3_SM_CTRL0_TRAIN_MODE_EN_ALIGN 0 17305 #define DSC_2_3_SM_CTRL0_TRAIN_MODE_EN_BITS 1 17306 #define DSC_2_3_SM_CTRL0_TRAIN_MODE_EN_SHIFT 6 17307 17308 /* dsc_2_3 :: sm_ctrl0 :: vga_frzval [05:05] */ 17309 #define DSC_2_3_SM_CTRL0_VGA_FRZVAL_MASK 0x0020 17310 #define DSC_2_3_SM_CTRL0_VGA_FRZVAL_ALIGN 0 17311 #define DSC_2_3_SM_CTRL0_VGA_FRZVAL_BITS 1 17312 #define DSC_2_3_SM_CTRL0_VGA_FRZVAL_SHIFT 5 17313 17314 /* dsc_2_3 :: sm_ctrl0 :: vga_frcfrz [04:04] */ 17315 #define DSC_2_3_SM_CTRL0_VGA_FRCFRZ_MASK 0x0010 17316 #define DSC_2_3_SM_CTRL0_VGA_FRCFRZ_ALIGN 0 17317 #define DSC_2_3_SM_CTRL0_VGA_FRCFRZ_BITS 1 17318 #define DSC_2_3_SM_CTRL0_VGA_FRCFRZ_SHIFT 4 17319 17320 /* dsc_2_3 :: sm_ctrl0 :: dfe_frzval [03:03] */ 17321 #define DSC_2_3_SM_CTRL0_DFE_FRZVAL_MASK 0x0008 17322 #define DSC_2_3_SM_CTRL0_DFE_FRZVAL_ALIGN 0 17323 #define DSC_2_3_SM_CTRL0_DFE_FRZVAL_BITS 1 17324 #define DSC_2_3_SM_CTRL0_DFE_FRZVAL_SHIFT 3 17325 17326 /* dsc_2_3 :: sm_ctrl0 :: dfe_frcfrz [02:02] */ 17327 #define DSC_2_3_SM_CTRL0_DFE_FRCFRZ_MASK 0x0004 17328 #define DSC_2_3_SM_CTRL0_DFE_FRCFRZ_ALIGN 0 17329 #define DSC_2_3_SM_CTRL0_DFE_FRCFRZ_BITS 1 17330 #define DSC_2_3_SM_CTRL0_DFE_FRCFRZ_SHIFT 2 17331 17332 /* dsc_2_3 :: sm_ctrl0 :: dsc_clr_val [01:01] */ 17333 #define DSC_2_3_SM_CTRL0_DSC_CLR_VAL_MASK 0x0002 17334 #define DSC_2_3_SM_CTRL0_DSC_CLR_VAL_ALIGN 0 17335 #define DSC_2_3_SM_CTRL0_DSC_CLR_VAL_BITS 1 17336 #define DSC_2_3_SM_CTRL0_DSC_CLR_VAL_SHIFT 1 17337 17338 /* dsc_2_3 :: sm_ctrl0 :: dsc_clr_frc [00:00] */ 17339 #define DSC_2_3_SM_CTRL0_DSC_CLR_FRC_MASK 0x0001 17340 #define DSC_2_3_SM_CTRL0_DSC_CLR_FRC_ALIGN 0 17341 #define DSC_2_3_SM_CTRL0_DSC_CLR_FRC_BITS 1 17342 #define DSC_2_3_SM_CTRL0_DSC_CLR_FRC_SHIFT 0 17343 17344 17345 /**************************************************************************** 17346 * dsc_2_3 :: sm_ctrl1 17347 */ 17348 /* dsc_2_3 :: sm_ctrl1 :: fast_timer [15:15] */ 17349 #define DSC_2_3_SM_CTRL1_FAST_TIMER_MASK 0x8000 17350 #define DSC_2_3_SM_CTRL1_FAST_TIMER_ALIGN 0 17351 #define DSC_2_3_SM_CTRL1_FAST_TIMER_BITS 1 17352 #define DSC_2_3_SM_CTRL1_FAST_TIMER_SHIFT 15 17353 17354 /* dsc_2_3 :: sm_ctrl1 :: acq2_timeout [14:10] */ 17355 #define DSC_2_3_SM_CTRL1_ACQ2_TIMEOUT_MASK 0x7c00 17356 #define DSC_2_3_SM_CTRL1_ACQ2_TIMEOUT_ALIGN 0 17357 #define DSC_2_3_SM_CTRL1_ACQ2_TIMEOUT_BITS 5 17358 #define DSC_2_3_SM_CTRL1_ACQ2_TIMEOUT_SHIFT 10 17359 17360 /* dsc_2_3 :: sm_ctrl1 :: acq1_timeout [09:05] */ 17361 #define DSC_2_3_SM_CTRL1_ACQ1_TIMEOUT_MASK 0x03e0 17362 #define DSC_2_3_SM_CTRL1_ACQ1_TIMEOUT_ALIGN 0 17363 #define DSC_2_3_SM_CTRL1_ACQ1_TIMEOUT_BITS 5 17364 #define DSC_2_3_SM_CTRL1_ACQ1_TIMEOUT_SHIFT 5 17365 17366 /* dsc_2_3 :: sm_ctrl1 :: acqcdr_timeout [04:00] */ 17367 #define DSC_2_3_SM_CTRL1_ACQCDR_TIMEOUT_MASK 0x001f 17368 #define DSC_2_3_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN 0 17369 #define DSC_2_3_SM_CTRL1_ACQCDR_TIMEOUT_BITS 5 17370 #define DSC_2_3_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT 0 17371 17372 17373 /**************************************************************************** 17374 * dsc_2_3 :: sm_ctrl2 17375 */ 17376 /* dsc_2_3 :: sm_ctrl2 :: reserved_for_eco0 [15:15] */ 17377 #define DSC_2_3_SM_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 17378 #define DSC_2_3_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 17379 #define DSC_2_3_SM_CTRL2_RESERVED_FOR_ECO0_BITS 1 17380 #define DSC_2_3_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 17381 17382 /* dsc_2_3 :: sm_ctrl2 :: cdrbr_bwsel_prop_acqcdr [14:12] */ 17383 #define DSC_2_3_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x7000 17384 #define DSC_2_3_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 17385 #define DSC_2_3_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 17386 #define DSC_2_3_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 12 17387 17388 /* dsc_2_3 :: sm_ctrl2 :: dfe_gain_acq2 [11:10] */ 17389 #define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ2_MASK 0x0c00 17390 #define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ2_ALIGN 0 17391 #define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ2_BITS 2 17392 #define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ2_SHIFT 10 17393 17394 /* dsc_2_3 :: sm_ctrl2 :: dfe_gain_acq1 [09:08] */ 17395 #define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ1_MASK 0x0300 17396 #define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ1_ALIGN 0 17397 #define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ1_BITS 2 17398 #define DSC_2_3_SM_CTRL2_DFE_GAIN_ACQ1_SHIFT 8 17399 17400 /* dsc_2_3 :: sm_ctrl2 :: vga_gain_acq2 [07:06] */ 17401 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ2_MASK 0x00c0 17402 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ2_ALIGN 0 17403 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ2_BITS 2 17404 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ2_SHIFT 6 17405 17406 /* dsc_2_3 :: sm_ctrl2 :: vga_gain_acq1 [05:04] */ 17407 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ1_MASK 0x0030 17408 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ1_ALIGN 0 17409 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ1_BITS 2 17410 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQ1_SHIFT 4 17411 17412 /* dsc_2_3 :: sm_ctrl2 :: vga_gain_acqcdr [03:02] */ 17413 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQCDR_MASK 0x000c 17414 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQCDR_ALIGN 0 17415 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQCDR_BITS 2 17416 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQCDR_SHIFT 2 17417 17418 /* dsc_2_3 :: sm_ctrl2 :: vga_gain_acqvga [01:00] */ 17419 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQVGA_MASK 0x0003 17420 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQVGA_ALIGN 0 17421 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQVGA_BITS 2 17422 #define DSC_2_3_SM_CTRL2_VGA_GAIN_ACQVGA_SHIFT 0 17423 17424 17425 /**************************************************************************** 17426 * dsc_2_3 :: sm_ctrl3 17427 */ 17428 /* dsc_2_3 :: sm_ctrl3 :: reserved_for_eco0 [15:12] */ 17429 #define DSC_2_3_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0xf000 17430 #define DSC_2_3_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 17431 #define DSC_2_3_SM_CTRL3_RESERVED_FOR_ECO0_BITS 4 17432 #define DSC_2_3_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 12 17433 17434 /* dsc_2_3 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq2 [11:10] */ 17435 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0c00 17436 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 17437 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_BITS 2 17438 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 10 17439 17440 /* dsc_2_3 :: sm_ctrl3 :: cdrbr_bwsel_integ_acq1 [09:08] */ 17441 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x0300 17442 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 17443 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_BITS 2 17444 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 8 17445 17446 /* dsc_2_3 :: sm_ctrl3 :: cdrbr_bwsel_integ_acqcdr [07:06] */ 17447 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x00c0 17448 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 17449 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_BITS 2 17450 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 6 17451 17452 /* dsc_2_3 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq2 [05:03] */ 17453 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0038 17454 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 17455 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_BITS 3 17456 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_SHIFT 3 17457 17458 /* dsc_2_3 :: sm_ctrl3 :: cdrbr_bwsel_prop_acq1 [02:00] */ 17459 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_MASK 0x0007 17460 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 17461 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_BITS 3 17462 #define DSC_2_3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_SHIFT 0 17463 17464 17465 /**************************************************************************** 17466 * dsc_2_3 :: sm_ctrl4 17467 */ 17468 /* dsc_2_3 :: sm_ctrl4 :: cdros_bwsel_integ_acq1_2 [15:12] */ 17469 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0xf000 17470 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 17471 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 17472 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 12 17473 17474 /* dsc_2_3 :: sm_ctrl4 :: cdros_bwsel_integ_acqcdr [11:08] */ 17475 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x0f00 17476 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 17477 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 17478 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 8 17479 17480 /* dsc_2_3 :: sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [07:04] */ 17481 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x00f0 17482 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 17483 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 17484 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 4 17485 17486 /* dsc_2_3 :: sm_ctrl4 :: cdros_bwsel_prop_acqcdr [03:00] */ 17487 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK 0x000f 17488 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 17489 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS 4 17490 #define DSC_2_3_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT 0 17491 17492 17493 /**************************************************************************** 17494 * dsc_2_3 :: dsc_status0 17495 */ 17496 /* dsc_2_3 :: dsc_status0 :: data_15_to_0 [15:00] */ 17497 #define DSC_2_3_DSC_STATUS0_DATA_15_TO_0_MASK 0xffff 17498 #define DSC_2_3_DSC_STATUS0_DATA_15_TO_0_ALIGN 0 17499 #define DSC_2_3_DSC_STATUS0_DATA_15_TO_0_BITS 16 17500 #define DSC_2_3_DSC_STATUS0_DATA_15_TO_0_SHIFT 0 17501 17502 17503 /**************************************************************************** 17504 * dsc_2_3 :: dsc_status1 17505 */ 17506 /* dsc_2_3 :: dsc_status1 :: p1err_11_to_0 [15:04] */ 17507 #define DSC_2_3_DSC_STATUS1_P1ERR_11_TO_0_MASK 0xfff0 17508 #define DSC_2_3_DSC_STATUS1_P1ERR_11_TO_0_ALIGN 0 17509 #define DSC_2_3_DSC_STATUS1_P1ERR_11_TO_0_BITS 12 17510 #define DSC_2_3_DSC_STATUS1_P1ERR_11_TO_0_SHIFT 4 17511 17512 /* dsc_2_3 :: dsc_status1 :: data_19_to_16 [03:00] */ 17513 #define DSC_2_3_DSC_STATUS1_DATA_19_TO_16_MASK 0x000f 17514 #define DSC_2_3_DSC_STATUS1_DATA_19_TO_16_ALIGN 0 17515 #define DSC_2_3_DSC_STATUS1_DATA_19_TO_16_BITS 4 17516 #define DSC_2_3_DSC_STATUS1_DATA_19_TO_16_SHIFT 0 17517 17518 17519 /**************************************************************************** 17520 * dsc_2_3 :: dsc_status2 17521 */ 17522 /* dsc_2_3 :: dsc_status2 :: m1err_7_to_0 [15:08] */ 17523 #define DSC_2_3_DSC_STATUS2_M1ERR_7_TO_0_MASK 0xff00 17524 #define DSC_2_3_DSC_STATUS2_M1ERR_7_TO_0_ALIGN 0 17525 #define DSC_2_3_DSC_STATUS2_M1ERR_7_TO_0_BITS 8 17526 #define DSC_2_3_DSC_STATUS2_M1ERR_7_TO_0_SHIFT 8 17527 17528 /* dsc_2_3 :: dsc_status2 :: p1err_19_to_12 [07:00] */ 17529 #define DSC_2_3_DSC_STATUS2_P1ERR_19_TO_12_MASK 0x00ff 17530 #define DSC_2_3_DSC_STATUS2_P1ERR_19_TO_12_ALIGN 0 17531 #define DSC_2_3_DSC_STATUS2_P1ERR_19_TO_12_BITS 8 17532 #define DSC_2_3_DSC_STATUS2_P1ERR_19_TO_12_SHIFT 0 17533 17534 17535 /**************************************************************************** 17536 * dsc_2_3 :: dsc_status3 17537 */ 17538 /* dsc_2_3 :: dsc_status3 :: reserved_for_eco0 [15:12] */ 17539 #define DSC_2_3_DSC_STATUS3_RESERVED_FOR_ECO0_MASK 0xf000 17540 #define DSC_2_3_DSC_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 17541 #define DSC_2_3_DSC_STATUS3_RESERVED_FOR_ECO0_BITS 4 17542 #define DSC_2_3_DSC_STATUS3_RESERVED_FOR_ECO0_SHIFT 12 17543 17544 /* dsc_2_3 :: dsc_status3 :: m1err_19_to_8 [11:00] */ 17545 #define DSC_2_3_DSC_STATUS3_M1ERR_19_TO_8_MASK 0x0fff 17546 #define DSC_2_3_DSC_STATUS3_M1ERR_19_TO_8_ALIGN 0 17547 #define DSC_2_3_DSC_STATUS3_M1ERR_19_TO_8_BITS 12 17548 #define DSC_2_3_DSC_STATUS3_M1ERR_19_TO_8_SHIFT 0 17549 17550 17551 /**************************************************************************** 17552 * dsc_2_3 :: dsc_ctrl0 17553 */ 17554 /* dsc_2_3 :: dsc_ctrl0 :: rxSeqStart [15:15] */ 17555 #define DSC_2_3_DSC_CTRL0_RXSEQSTART_MASK 0x8000 17556 #define DSC_2_3_DSC_CTRL0_RXSEQSTART_ALIGN 0 17557 #define DSC_2_3_DSC_CTRL0_RXSEQSTART_BITS 1 17558 #define DSC_2_3_DSC_CTRL0_RXSEQSTART_SHIFT 15 17559 17560 /* dsc_2_3 :: dsc_ctrl0 :: forceRxSeqDone [14:14] */ 17561 #define DSC_2_3_DSC_CTRL0_FORCERXSEQDONE_MASK 0x4000 17562 #define DSC_2_3_DSC_CTRL0_FORCERXSEQDONE_ALIGN 0 17563 #define DSC_2_3_DSC_CTRL0_FORCERXSEQDONE_BITS 1 17564 #define DSC_2_3_DSC_CTRL0_FORCERXSEQDONE_SHIFT 14 17565 17566 /* dsc_2_3 :: dsc_ctrl0 :: test_bus_sel [13:10] */ 17567 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_MASK 0x3c00 17568 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_ALIGN 0 17569 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_BITS 4 17570 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_SHIFT 10 17571 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_Off 0 17572 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_OSx2data 1 17573 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 17574 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 17575 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 17576 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_cdrIntg 6 17577 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 17578 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 17579 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 17580 #define DSC_2_3_DSC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 17581 17582 /* dsc_2_3 :: dsc_ctrl0 :: rx_m1_thresh_zero [09:09] */ 17583 #define DSC_2_3_DSC_CTRL0_RX_M1_THRESH_ZERO_MASK 0x0200 17584 #define DSC_2_3_DSC_CTRL0_RX_M1_THRESH_ZERO_ALIGN 0 17585 #define DSC_2_3_DSC_CTRL0_RX_M1_THRESH_ZERO_BITS 1 17586 #define DSC_2_3_DSC_CTRL0_RX_M1_THRESH_ZERO_SHIFT 9 17587 17588 /* dsc_2_3 :: dsc_ctrl0 :: rx_thresh_sel [08:07] */ 17589 #define DSC_2_3_DSC_CTRL0_RX_THRESH_SEL_MASK 0x0180 17590 #define DSC_2_3_DSC_CTRL0_RX_THRESH_SEL_ALIGN 0 17591 #define DSC_2_3_DSC_CTRL0_RX_THRESH_SEL_BITS 2 17592 #define DSC_2_3_DSC_CTRL0_RX_THRESH_SEL_SHIFT 7 17593 17594 /* dsc_2_3 :: dsc_ctrl0 :: rx_pf_ctrl [06:04] */ 17595 #define DSC_2_3_DSC_CTRL0_RX_PF_CTRL_MASK 0x0070 17596 #define DSC_2_3_DSC_CTRL0_RX_PF_CTRL_ALIGN 0 17597 #define DSC_2_3_DSC_CTRL0_RX_PF_CTRL_BITS 3 17598 #define DSC_2_3_DSC_CTRL0_RX_PF_CTRL_SHIFT 4 17599 17600 /* dsc_2_3 :: dsc_ctrl0 :: cdrbr_sel [03:03] */ 17601 #define DSC_2_3_DSC_CTRL0_CDRBR_SEL_MASK 0x0008 17602 #define DSC_2_3_DSC_CTRL0_CDRBR_SEL_ALIGN 0 17603 #define DSC_2_3_DSC_CTRL0_CDRBR_SEL_BITS 1 17604 #define DSC_2_3_DSC_CTRL0_CDRBR_SEL_SHIFT 3 17605 17606 /* dsc_2_3 :: dsc_ctrl0 :: oscdr_force_mode_en [02:02] */ 17607 #define DSC_2_3_DSC_CTRL0_OSCDR_FORCE_MODE_EN_MASK 0x0004 17608 #define DSC_2_3_DSC_CTRL0_OSCDR_FORCE_MODE_EN_ALIGN 0 17609 #define DSC_2_3_DSC_CTRL0_OSCDR_FORCE_MODE_EN_BITS 1 17610 #define DSC_2_3_DSC_CTRL0_OSCDR_FORCE_MODE_EN_SHIFT 2 17611 17612 /* dsc_2_3 :: dsc_ctrl0 :: oscdr_mode [01:00] */ 17613 #define DSC_2_3_DSC_CTRL0_OSCDR_MODE_MASK 0x0003 17614 #define DSC_2_3_DSC_CTRL0_OSCDR_MODE_ALIGN 0 17615 #define DSC_2_3_DSC_CTRL0_OSCDR_MODE_BITS 2 17616 #define DSC_2_3_DSC_CTRL0_OSCDR_MODE_SHIFT 0 17617 17618 17619 /**************************************************************************** 17620 * dsc_2_3 :: dsc_ctrl1 17621 */ 17622 /* dsc_2_3 :: dsc_ctrl1 :: reserved_for_eco0 [15:15] */ 17623 #define DSC_2_3_DSC_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 17624 #define DSC_2_3_DSC_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 17625 #define DSC_2_3_DSC_CTRL1_RESERVED_FOR_ECO0_BITS 1 17626 #define DSC_2_3_DSC_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 17627 17628 /* dsc_2_3 :: dsc_ctrl1 :: p1_odd_ctrl [14:10] */ 17629 #define DSC_2_3_DSC_CTRL1_P1_ODD_CTRL_MASK 0x7c00 17630 #define DSC_2_3_DSC_CTRL1_P1_ODD_CTRL_ALIGN 0 17631 #define DSC_2_3_DSC_CTRL1_P1_ODD_CTRL_BITS 5 17632 #define DSC_2_3_DSC_CTRL1_P1_ODD_CTRL_SHIFT 10 17633 17634 /* dsc_2_3 :: dsc_ctrl1 :: p1_evn_ctrl [09:05] */ 17635 #define DSC_2_3_DSC_CTRL1_P1_EVN_CTRL_MASK 0x03e0 17636 #define DSC_2_3_DSC_CTRL1_P1_EVN_CTRL_ALIGN 0 17637 #define DSC_2_3_DSC_CTRL1_P1_EVN_CTRL_BITS 5 17638 #define DSC_2_3_DSC_CTRL1_P1_EVN_CTRL_SHIFT 5 17639 17640 /* dsc_2_3 :: dsc_ctrl1 :: d_odd_ctrl [04:00] */ 17641 #define DSC_2_3_DSC_CTRL1_D_ODD_CTRL_MASK 0x001f 17642 #define DSC_2_3_DSC_CTRL1_D_ODD_CTRL_ALIGN 0 17643 #define DSC_2_3_DSC_CTRL1_D_ODD_CTRL_BITS 5 17644 #define DSC_2_3_DSC_CTRL1_D_ODD_CTRL_SHIFT 0 17645 17646 17647 /**************************************************************************** 17648 * dsc_2_3 :: dsc_ctrl2 17649 */ 17650 /* dsc_2_3 :: dsc_ctrl2 :: reserved_for_eco0 [15:15] */ 17651 #define DSC_2_3_DSC_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 17652 #define DSC_2_3_DSC_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 17653 #define DSC_2_3_DSC_CTRL2_RESERVED_FOR_ECO0_BITS 1 17654 #define DSC_2_3_DSC_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 17655 17656 /* dsc_2_3 :: dsc_ctrl2 :: d_evn_ctrl [14:10] */ 17657 #define DSC_2_3_DSC_CTRL2_D_EVN_CTRL_MASK 0x7c00 17658 #define DSC_2_3_DSC_CTRL2_D_EVN_CTRL_ALIGN 0 17659 #define DSC_2_3_DSC_CTRL2_D_EVN_CTRL_BITS 5 17660 #define DSC_2_3_DSC_CTRL2_D_EVN_CTRL_SHIFT 10 17661 17662 /* dsc_2_3 :: dsc_ctrl2 :: m1_odd_ctrl [09:05] */ 17663 #define DSC_2_3_DSC_CTRL2_M1_ODD_CTRL_MASK 0x03e0 17664 #define DSC_2_3_DSC_CTRL2_M1_ODD_CTRL_ALIGN 0 17665 #define DSC_2_3_DSC_CTRL2_M1_ODD_CTRL_BITS 5 17666 #define DSC_2_3_DSC_CTRL2_M1_ODD_CTRL_SHIFT 5 17667 17668 /* dsc_2_3 :: dsc_ctrl2 :: m1_evn_ctrl [04:00] */ 17669 #define DSC_2_3_DSC_CTRL2_M1_EVN_CTRL_MASK 0x001f 17670 #define DSC_2_3_DSC_CTRL2_M1_EVN_CTRL_ALIGN 0 17671 #define DSC_2_3_DSC_CTRL2_M1_EVN_CTRL_BITS 5 17672 #define DSC_2_3_DSC_CTRL2_M1_EVN_CTRL_SHIFT 0 17673 17674 17675 /**************************************************************************** 17676 * XGXS16G_USER_dsc_2_A 17677 */ 17678 /**************************************************************************** 17679 * dsc_2_A :: sm_status0 17680 */ 17681 /* dsc_2_A :: sm_status0 :: reserved_for_eco0 [15:04] */ 17682 #define DSC_2_A_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xfff0 17683 #define DSC_2_A_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 17684 #define DSC_2_A_SM_STATUS0_RESERVED_FOR_ECO0_BITS 12 17685 #define DSC_2_A_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 4 17686 17687 /* dsc_2_A :: sm_status0 :: dsc_state [03:00] */ 17688 #define DSC_2_A_SM_STATUS0_DSC_STATE_MASK 0x000f 17689 #define DSC_2_A_SM_STATUS0_DSC_STATE_ALIGN 0 17690 #define DSC_2_A_SM_STATUS0_DSC_STATE_BITS 4 17691 #define DSC_2_A_SM_STATUS0_DSC_STATE_SHIFT 0 17692 17693 17694 /**************************************************************************** 17695 * dsc_2_A :: sm_ctrl0 17696 */ 17697 /* dsc_2_A :: sm_ctrl0 :: acqvga_timeout [15:11] */ 17698 #define DSC_2_A_SM_CTRL0_ACQVGA_TIMEOUT_MASK 0xf800 17699 #define DSC_2_A_SM_CTRL0_ACQVGA_TIMEOUT_ALIGN 0 17700 #define DSC_2_A_SM_CTRL0_ACQVGA_TIMEOUT_BITS 5 17701 #define DSC_2_A_SM_CTRL0_ACQVGA_TIMEOUT_SHIFT 11 17702 17703 /* dsc_2_A :: sm_ctrl0 :: tuning_sm_en [10:10] */ 17704 #define DSC_2_A_SM_CTRL0_TUNING_SM_EN_MASK 0x0400 17705 #define DSC_2_A_SM_CTRL0_TUNING_SM_EN_ALIGN 0 17706 #define DSC_2_A_SM_CTRL0_TUNING_SM_EN_BITS 1 17707 #define DSC_2_A_SM_CTRL0_TUNING_SM_EN_SHIFT 10 17708 17709 /* dsc_2_A :: sm_ctrl0 :: train2_req [09:09] */ 17710 #define DSC_2_A_SM_CTRL0_TRAIN2_REQ_MASK 0x0200 17711 #define DSC_2_A_SM_CTRL0_TRAIN2_REQ_ALIGN 0 17712 #define DSC_2_A_SM_CTRL0_TRAIN2_REQ_BITS 1 17713 #define DSC_2_A_SM_CTRL0_TRAIN2_REQ_SHIFT 9 17714 17715 /* dsc_2_A :: sm_ctrl0 :: train1_req [08:08] */ 17716 #define DSC_2_A_SM_CTRL0_TRAIN1_REQ_MASK 0x0100 17717 #define DSC_2_A_SM_CTRL0_TRAIN1_REQ_ALIGN 0 17718 #define DSC_2_A_SM_CTRL0_TRAIN1_REQ_BITS 1 17719 #define DSC_2_A_SM_CTRL0_TRAIN1_REQ_SHIFT 8 17720 17721 /* dsc_2_A :: sm_ctrl0 :: soft_ack [07:07] */ 17722 #define DSC_2_A_SM_CTRL0_SOFT_ACK_MASK 0x0080 17723 #define DSC_2_A_SM_CTRL0_SOFT_ACK_ALIGN 0 17724 #define DSC_2_A_SM_CTRL0_SOFT_ACK_BITS 1 17725 #define DSC_2_A_SM_CTRL0_SOFT_ACK_SHIFT 7 17726 17727 /* dsc_2_A :: sm_ctrl0 :: train_mode_en [06:06] */ 17728 #define DSC_2_A_SM_CTRL0_TRAIN_MODE_EN_MASK 0x0040 17729 #define DSC_2_A_SM_CTRL0_TRAIN_MODE_EN_ALIGN 0 17730 #define DSC_2_A_SM_CTRL0_TRAIN_MODE_EN_BITS 1 17731 #define DSC_2_A_SM_CTRL0_TRAIN_MODE_EN_SHIFT 6 17732 17733 /* dsc_2_A :: sm_ctrl0 :: vga_frzval [05:05] */ 17734 #define DSC_2_A_SM_CTRL0_VGA_FRZVAL_MASK 0x0020 17735 #define DSC_2_A_SM_CTRL0_VGA_FRZVAL_ALIGN 0 17736 #define DSC_2_A_SM_CTRL0_VGA_FRZVAL_BITS 1 17737 #define DSC_2_A_SM_CTRL0_VGA_FRZVAL_SHIFT 5 17738 17739 /* dsc_2_A :: sm_ctrl0 :: vga_frcfrz [04:04] */ 17740 #define DSC_2_A_SM_CTRL0_VGA_FRCFRZ_MASK 0x0010 17741 #define DSC_2_A_SM_CTRL0_VGA_FRCFRZ_ALIGN 0 17742 #define DSC_2_A_SM_CTRL0_VGA_FRCFRZ_BITS 1 17743 #define DSC_2_A_SM_CTRL0_VGA_FRCFRZ_SHIFT 4 17744 17745 /* dsc_2_A :: sm_ctrl0 :: dfe_frzval [03:03] */ 17746 #define DSC_2_A_SM_CTRL0_DFE_FRZVAL_MASK 0x0008 17747 #define DSC_2_A_SM_CTRL0_DFE_FRZVAL_ALIGN 0 17748 #define DSC_2_A_SM_CTRL0_DFE_FRZVAL_BITS 1 17749 #define DSC_2_A_SM_CTRL0_DFE_FRZVAL_SHIFT 3 17750 17751 /* dsc_2_A :: sm_ctrl0 :: dfe_frcfrz [02:02] */ 17752 #define DSC_2_A_SM_CTRL0_DFE_FRCFRZ_MASK 0x0004 17753 #define DSC_2_A_SM_CTRL0_DFE_FRCFRZ_ALIGN 0 17754 #define DSC_2_A_SM_CTRL0_DFE_FRCFRZ_BITS 1 17755 #define DSC_2_A_SM_CTRL0_DFE_FRCFRZ_SHIFT 2 17756 17757 /* dsc_2_A :: sm_ctrl0 :: dsc_clr_val [01:01] */ 17758 #define DSC_2_A_SM_CTRL0_DSC_CLR_VAL_MASK 0x0002 17759 #define DSC_2_A_SM_CTRL0_DSC_CLR_VAL_ALIGN 0 17760 #define DSC_2_A_SM_CTRL0_DSC_CLR_VAL_BITS 1 17761 #define DSC_2_A_SM_CTRL0_DSC_CLR_VAL_SHIFT 1 17762 17763 /* dsc_2_A :: sm_ctrl0 :: dsc_clr_frc [00:00] */ 17764 #define DSC_2_A_SM_CTRL0_DSC_CLR_FRC_MASK 0x0001 17765 #define DSC_2_A_SM_CTRL0_DSC_CLR_FRC_ALIGN 0 17766 #define DSC_2_A_SM_CTRL0_DSC_CLR_FRC_BITS 1 17767 #define DSC_2_A_SM_CTRL0_DSC_CLR_FRC_SHIFT 0 17768 17769 17770 /**************************************************************************** 17771 * dsc_2_A :: sm_ctrl1 17772 */ 17773 /* dsc_2_A :: sm_ctrl1 :: fast_timer [15:15] */ 17774 #define DSC_2_A_SM_CTRL1_FAST_TIMER_MASK 0x8000 17775 #define DSC_2_A_SM_CTRL1_FAST_TIMER_ALIGN 0 17776 #define DSC_2_A_SM_CTRL1_FAST_TIMER_BITS 1 17777 #define DSC_2_A_SM_CTRL1_FAST_TIMER_SHIFT 15 17778 17779 /* dsc_2_A :: sm_ctrl1 :: acq2_timeout [14:10] */ 17780 #define DSC_2_A_SM_CTRL1_ACQ2_TIMEOUT_MASK 0x7c00 17781 #define DSC_2_A_SM_CTRL1_ACQ2_TIMEOUT_ALIGN 0 17782 #define DSC_2_A_SM_CTRL1_ACQ2_TIMEOUT_BITS 5 17783 #define DSC_2_A_SM_CTRL1_ACQ2_TIMEOUT_SHIFT 10 17784 17785 /* dsc_2_A :: sm_ctrl1 :: acq1_timeout [09:05] */ 17786 #define DSC_2_A_SM_CTRL1_ACQ1_TIMEOUT_MASK 0x03e0 17787 #define DSC_2_A_SM_CTRL1_ACQ1_TIMEOUT_ALIGN 0 17788 #define DSC_2_A_SM_CTRL1_ACQ1_TIMEOUT_BITS 5 17789 #define DSC_2_A_SM_CTRL1_ACQ1_TIMEOUT_SHIFT 5 17790 17791 /* dsc_2_A :: sm_ctrl1 :: acqcdr_timeout [04:00] */ 17792 #define DSC_2_A_SM_CTRL1_ACQCDR_TIMEOUT_MASK 0x001f 17793 #define DSC_2_A_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN 0 17794 #define DSC_2_A_SM_CTRL1_ACQCDR_TIMEOUT_BITS 5 17795 #define DSC_2_A_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT 0 17796 17797 17798 /**************************************************************************** 17799 * dsc_2_A :: sm_ctrl2 17800 */ 17801 /* dsc_2_A :: sm_ctrl2 :: reserved_for_eco0 [15:15] */ 17802 #define DSC_2_A_SM_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 17803 #define DSC_2_A_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 17804 #define DSC_2_A_SM_CTRL2_RESERVED_FOR_ECO0_BITS 1 17805 #define DSC_2_A_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 17806 17807 /* dsc_2_A :: sm_ctrl2 :: cdrbr_bwsel_prop_acqcdr [14:12] */ 17808 #define DSC_2_A_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x7000 17809 #define DSC_2_A_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 17810 #define DSC_2_A_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 17811 #define DSC_2_A_SM_CTRL2_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 12 17812 17813 /* dsc_2_A :: sm_ctrl2 :: dfe_gain_acq2 [11:10] */ 17814 #define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ2_MASK 0x0c00 17815 #define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ2_ALIGN 0 17816 #define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ2_BITS 2 17817 #define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ2_SHIFT 10 17818 17819 /* dsc_2_A :: sm_ctrl2 :: dfe_gain_acq1 [09:08] */ 17820 #define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ1_MASK 0x0300 17821 #define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ1_ALIGN 0 17822 #define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ1_BITS 2 17823 #define DSC_2_A_SM_CTRL2_DFE_GAIN_ACQ1_SHIFT 8 17824 17825 /* dsc_2_A :: sm_ctrl2 :: vga_gain_acq2 [07:06] */ 17826 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ2_MASK 0x00c0 17827 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ2_ALIGN 0 17828 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ2_BITS 2 17829 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ2_SHIFT 6 17830 17831 /* dsc_2_A :: sm_ctrl2 :: vga_gain_acq1 [05:04] */ 17832 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ1_MASK 0x0030 17833 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ1_ALIGN 0 17834 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ1_BITS 2 17835 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQ1_SHIFT 4 17836 17837 /* dsc_2_A :: sm_ctrl2 :: vga_gain_acqcdr [03:02] */ 17838 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQCDR_MASK 0x000c 17839 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQCDR_ALIGN 0 17840 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQCDR_BITS 2 17841 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQCDR_SHIFT 2 17842 17843 /* dsc_2_A :: sm_ctrl2 :: vga_gain_acqvga [01:00] */ 17844 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQVGA_MASK 0x0003 17845 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQVGA_ALIGN 0 17846 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQVGA_BITS 2 17847 #define DSC_2_A_SM_CTRL2_VGA_GAIN_ACQVGA_SHIFT 0 17848 17849 17850 /**************************************************************************** 17851 * dsc_2_A :: sm_ctrl3 17852 */ 17853 /* dsc_2_A :: sm_ctrl3 :: reserved_for_eco0 [15:12] */ 17854 #define DSC_2_A_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0xf000 17855 #define DSC_2_A_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 17856 #define DSC_2_A_SM_CTRL3_RESERVED_FOR_ECO0_BITS 4 17857 #define DSC_2_A_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 12 17858 17859 /* dsc_2_A :: sm_ctrl3 :: cdrbr_bwsel_integ_acq2 [11:10] */ 17860 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0c00 17861 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 17862 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_BITS 2 17863 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 10 17864 17865 /* dsc_2_A :: sm_ctrl3 :: cdrbr_bwsel_integ_acq1 [09:08] */ 17866 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x0300 17867 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 17868 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_BITS 2 17869 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 8 17870 17871 /* dsc_2_A :: sm_ctrl3 :: cdrbr_bwsel_integ_acqcdr [07:06] */ 17872 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x00c0 17873 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 17874 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_BITS 2 17875 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 6 17876 17877 /* dsc_2_A :: sm_ctrl3 :: cdrbr_bwsel_prop_acq2 [05:03] */ 17878 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0038 17879 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 17880 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_BITS 3 17881 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ2_SHIFT 3 17882 17883 /* dsc_2_A :: sm_ctrl3 :: cdrbr_bwsel_prop_acq1 [02:00] */ 17884 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_MASK 0x0007 17885 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 17886 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_BITS 3 17887 #define DSC_2_A_SM_CTRL3_CDRBR_BWSEL_PROP_ACQ1_SHIFT 0 17888 17889 17890 /**************************************************************************** 17891 * dsc_2_A :: sm_ctrl4 17892 */ 17893 /* dsc_2_A :: sm_ctrl4 :: cdros_bwsel_integ_acq1_2 [15:12] */ 17894 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0xf000 17895 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 17896 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 17897 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 12 17898 17899 /* dsc_2_A :: sm_ctrl4 :: cdros_bwsel_integ_acqcdr [11:08] */ 17900 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x0f00 17901 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 17902 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 17903 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 8 17904 17905 /* dsc_2_A :: sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [07:04] */ 17906 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x00f0 17907 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 17908 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 17909 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 4 17910 17911 /* dsc_2_A :: sm_ctrl4 :: cdros_bwsel_prop_acqcdr [03:00] */ 17912 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK 0x000f 17913 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 17914 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS 4 17915 #define DSC_2_A_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT 0 17916 17917 17918 /**************************************************************************** 17919 * dsc_2_A :: dsc_status0 17920 */ 17921 /* dsc_2_A :: dsc_status0 :: data_15_to_0 [15:00] */ 17922 #define DSC_2_A_DSC_STATUS0_DATA_15_TO_0_MASK 0xffff 17923 #define DSC_2_A_DSC_STATUS0_DATA_15_TO_0_ALIGN 0 17924 #define DSC_2_A_DSC_STATUS0_DATA_15_TO_0_BITS 16 17925 #define DSC_2_A_DSC_STATUS0_DATA_15_TO_0_SHIFT 0 17926 17927 17928 /**************************************************************************** 17929 * dsc_2_A :: dsc_status1 17930 */ 17931 /* dsc_2_A :: dsc_status1 :: p1err_11_to_0 [15:04] */ 17932 #define DSC_2_A_DSC_STATUS1_P1ERR_11_TO_0_MASK 0xfff0 17933 #define DSC_2_A_DSC_STATUS1_P1ERR_11_TO_0_ALIGN 0 17934 #define DSC_2_A_DSC_STATUS1_P1ERR_11_TO_0_BITS 12 17935 #define DSC_2_A_DSC_STATUS1_P1ERR_11_TO_0_SHIFT 4 17936 17937 /* dsc_2_A :: dsc_status1 :: data_19_to_16 [03:00] */ 17938 #define DSC_2_A_DSC_STATUS1_DATA_19_TO_16_MASK 0x000f 17939 #define DSC_2_A_DSC_STATUS1_DATA_19_TO_16_ALIGN 0 17940 #define DSC_2_A_DSC_STATUS1_DATA_19_TO_16_BITS 4 17941 #define DSC_2_A_DSC_STATUS1_DATA_19_TO_16_SHIFT 0 17942 17943 17944 /**************************************************************************** 17945 * dsc_2_A :: dsc_status2 17946 */ 17947 /* dsc_2_A :: dsc_status2 :: m1err_7_to_0 [15:08] */ 17948 #define DSC_2_A_DSC_STATUS2_M1ERR_7_TO_0_MASK 0xff00 17949 #define DSC_2_A_DSC_STATUS2_M1ERR_7_TO_0_ALIGN 0 17950 #define DSC_2_A_DSC_STATUS2_M1ERR_7_TO_0_BITS 8 17951 #define DSC_2_A_DSC_STATUS2_M1ERR_7_TO_0_SHIFT 8 17952 17953 /* dsc_2_A :: dsc_status2 :: p1err_19_to_12 [07:00] */ 17954 #define DSC_2_A_DSC_STATUS2_P1ERR_19_TO_12_MASK 0x00ff 17955 #define DSC_2_A_DSC_STATUS2_P1ERR_19_TO_12_ALIGN 0 17956 #define DSC_2_A_DSC_STATUS2_P1ERR_19_TO_12_BITS 8 17957 #define DSC_2_A_DSC_STATUS2_P1ERR_19_TO_12_SHIFT 0 17958 17959 17960 /**************************************************************************** 17961 * dsc_2_A :: dsc_status3 17962 */ 17963 /* dsc_2_A :: dsc_status3 :: reserved_for_eco0 [15:12] */ 17964 #define DSC_2_A_DSC_STATUS3_RESERVED_FOR_ECO0_MASK 0xf000 17965 #define DSC_2_A_DSC_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 17966 #define DSC_2_A_DSC_STATUS3_RESERVED_FOR_ECO0_BITS 4 17967 #define DSC_2_A_DSC_STATUS3_RESERVED_FOR_ECO0_SHIFT 12 17968 17969 /* dsc_2_A :: dsc_status3 :: m1err_19_to_8 [11:00] */ 17970 #define DSC_2_A_DSC_STATUS3_M1ERR_19_TO_8_MASK 0x0fff 17971 #define DSC_2_A_DSC_STATUS3_M1ERR_19_TO_8_ALIGN 0 17972 #define DSC_2_A_DSC_STATUS3_M1ERR_19_TO_8_BITS 12 17973 #define DSC_2_A_DSC_STATUS3_M1ERR_19_TO_8_SHIFT 0 17974 17975 17976 /**************************************************************************** 17977 * dsc_2_A :: dsc_ctrl0 17978 */ 17979 /* dsc_2_A :: dsc_ctrl0 :: rxSeqStart [15:15] */ 17980 #define DSC_2_A_DSC_CTRL0_RXSEQSTART_MASK 0x8000 17981 #define DSC_2_A_DSC_CTRL0_RXSEQSTART_ALIGN 0 17982 #define DSC_2_A_DSC_CTRL0_RXSEQSTART_BITS 1 17983 #define DSC_2_A_DSC_CTRL0_RXSEQSTART_SHIFT 15 17984 17985 /* dsc_2_A :: dsc_ctrl0 :: forceRxSeqDone [14:14] */ 17986 #define DSC_2_A_DSC_CTRL0_FORCERXSEQDONE_MASK 0x4000 17987 #define DSC_2_A_DSC_CTRL0_FORCERXSEQDONE_ALIGN 0 17988 #define DSC_2_A_DSC_CTRL0_FORCERXSEQDONE_BITS 1 17989 #define DSC_2_A_DSC_CTRL0_FORCERXSEQDONE_SHIFT 14 17990 17991 /* dsc_2_A :: dsc_ctrl0 :: test_bus_sel [13:10] */ 17992 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_MASK 0x3c00 17993 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_ALIGN 0 17994 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_BITS 4 17995 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_SHIFT 10 17996 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_Off 0 17997 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_OSx2data 1 17998 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 17999 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 18000 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 18001 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_cdrIntg 6 18002 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 18003 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 18004 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 18005 #define DSC_2_A_DSC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 18006 18007 /* dsc_2_A :: dsc_ctrl0 :: rx_m1_thresh_zero [09:09] */ 18008 #define DSC_2_A_DSC_CTRL0_RX_M1_THRESH_ZERO_MASK 0x0200 18009 #define DSC_2_A_DSC_CTRL0_RX_M1_THRESH_ZERO_ALIGN 0 18010 #define DSC_2_A_DSC_CTRL0_RX_M1_THRESH_ZERO_BITS 1 18011 #define DSC_2_A_DSC_CTRL0_RX_M1_THRESH_ZERO_SHIFT 9 18012 18013 /* dsc_2_A :: dsc_ctrl0 :: rx_thresh_sel [08:07] */ 18014 #define DSC_2_A_DSC_CTRL0_RX_THRESH_SEL_MASK 0x0180 18015 #define DSC_2_A_DSC_CTRL0_RX_THRESH_SEL_ALIGN 0 18016 #define DSC_2_A_DSC_CTRL0_RX_THRESH_SEL_BITS 2 18017 #define DSC_2_A_DSC_CTRL0_RX_THRESH_SEL_SHIFT 7 18018 18019 /* dsc_2_A :: dsc_ctrl0 :: rx_pf_ctrl [06:04] */ 18020 #define DSC_2_A_DSC_CTRL0_RX_PF_CTRL_MASK 0x0070 18021 #define DSC_2_A_DSC_CTRL0_RX_PF_CTRL_ALIGN 0 18022 #define DSC_2_A_DSC_CTRL0_RX_PF_CTRL_BITS 3 18023 #define DSC_2_A_DSC_CTRL0_RX_PF_CTRL_SHIFT 4 18024 18025 /* dsc_2_A :: dsc_ctrl0 :: cdrbr_sel [03:03] */ 18026 #define DSC_2_A_DSC_CTRL0_CDRBR_SEL_MASK 0x0008 18027 #define DSC_2_A_DSC_CTRL0_CDRBR_SEL_ALIGN 0 18028 #define DSC_2_A_DSC_CTRL0_CDRBR_SEL_BITS 1 18029 #define DSC_2_A_DSC_CTRL0_CDRBR_SEL_SHIFT 3 18030 18031 /* dsc_2_A :: dsc_ctrl0 :: oscdr_force_mode_en [02:02] */ 18032 #define DSC_2_A_DSC_CTRL0_OSCDR_FORCE_MODE_EN_MASK 0x0004 18033 #define DSC_2_A_DSC_CTRL0_OSCDR_FORCE_MODE_EN_ALIGN 0 18034 #define DSC_2_A_DSC_CTRL0_OSCDR_FORCE_MODE_EN_BITS 1 18035 #define DSC_2_A_DSC_CTRL0_OSCDR_FORCE_MODE_EN_SHIFT 2 18036 18037 /* dsc_2_A :: dsc_ctrl0 :: oscdr_mode [01:00] */ 18038 #define DSC_2_A_DSC_CTRL0_OSCDR_MODE_MASK 0x0003 18039 #define DSC_2_A_DSC_CTRL0_OSCDR_MODE_ALIGN 0 18040 #define DSC_2_A_DSC_CTRL0_OSCDR_MODE_BITS 2 18041 #define DSC_2_A_DSC_CTRL0_OSCDR_MODE_SHIFT 0 18042 18043 18044 /**************************************************************************** 18045 * dsc_2_A :: dsc_ctrl1 18046 */ 18047 /* dsc_2_A :: dsc_ctrl1 :: reserved_for_eco0 [15:15] */ 18048 #define DSC_2_A_DSC_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 18049 #define DSC_2_A_DSC_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 18050 #define DSC_2_A_DSC_CTRL1_RESERVED_FOR_ECO0_BITS 1 18051 #define DSC_2_A_DSC_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 18052 18053 /* dsc_2_A :: dsc_ctrl1 :: p1_odd_ctrl [14:10] */ 18054 #define DSC_2_A_DSC_CTRL1_P1_ODD_CTRL_MASK 0x7c00 18055 #define DSC_2_A_DSC_CTRL1_P1_ODD_CTRL_ALIGN 0 18056 #define DSC_2_A_DSC_CTRL1_P1_ODD_CTRL_BITS 5 18057 #define DSC_2_A_DSC_CTRL1_P1_ODD_CTRL_SHIFT 10 18058 18059 /* dsc_2_A :: dsc_ctrl1 :: p1_evn_ctrl [09:05] */ 18060 #define DSC_2_A_DSC_CTRL1_P1_EVN_CTRL_MASK 0x03e0 18061 #define DSC_2_A_DSC_CTRL1_P1_EVN_CTRL_ALIGN 0 18062 #define DSC_2_A_DSC_CTRL1_P1_EVN_CTRL_BITS 5 18063 #define DSC_2_A_DSC_CTRL1_P1_EVN_CTRL_SHIFT 5 18064 18065 /* dsc_2_A :: dsc_ctrl1 :: d_odd_ctrl [04:00] */ 18066 #define DSC_2_A_DSC_CTRL1_D_ODD_CTRL_MASK 0x001f 18067 #define DSC_2_A_DSC_CTRL1_D_ODD_CTRL_ALIGN 0 18068 #define DSC_2_A_DSC_CTRL1_D_ODD_CTRL_BITS 5 18069 #define DSC_2_A_DSC_CTRL1_D_ODD_CTRL_SHIFT 0 18070 18071 18072 /**************************************************************************** 18073 * dsc_2_A :: dsc_ctrl2 18074 */ 18075 /* dsc_2_A :: dsc_ctrl2 :: reserved_for_eco0 [15:15] */ 18076 #define DSC_2_A_DSC_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 18077 #define DSC_2_A_DSC_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 18078 #define DSC_2_A_DSC_CTRL2_RESERVED_FOR_ECO0_BITS 1 18079 #define DSC_2_A_DSC_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 18080 18081 /* dsc_2_A :: dsc_ctrl2 :: d_evn_ctrl [14:10] */ 18082 #define DSC_2_A_DSC_CTRL2_D_EVN_CTRL_MASK 0x7c00 18083 #define DSC_2_A_DSC_CTRL2_D_EVN_CTRL_ALIGN 0 18084 #define DSC_2_A_DSC_CTRL2_D_EVN_CTRL_BITS 5 18085 #define DSC_2_A_DSC_CTRL2_D_EVN_CTRL_SHIFT 10 18086 18087 /* dsc_2_A :: dsc_ctrl2 :: m1_odd_ctrl [09:05] */ 18088 #define DSC_2_A_DSC_CTRL2_M1_ODD_CTRL_MASK 0x03e0 18089 #define DSC_2_A_DSC_CTRL2_M1_ODD_CTRL_ALIGN 0 18090 #define DSC_2_A_DSC_CTRL2_M1_ODD_CTRL_BITS 5 18091 #define DSC_2_A_DSC_CTRL2_M1_ODD_CTRL_SHIFT 5 18092 18093 /* dsc_2_A :: dsc_ctrl2 :: m1_evn_ctrl [04:00] */ 18094 #define DSC_2_A_DSC_CTRL2_M1_EVN_CTRL_MASK 0x001f 18095 #define DSC_2_A_DSC_CTRL2_M1_EVN_CTRL_ALIGN 0 18096 #define DSC_2_A_DSC_CTRL2_M1_EVN_CTRL_BITS 5 18097 #define DSC_2_A_DSC_CTRL2_M1_EVN_CTRL_SHIFT 0 18098 18099 18100 /**************************************************************************** 18101 * XGXS16G_USER_SerdesDigital 18102 */ 18103 /**************************************************************************** 18104 * SerdesDigital :: Control1000X1 18105 */ 18106 /* SerdesDigital :: Control1000X1 :: reserved0 [15:15] */ 18107 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_MASK 0x8000 18108 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_ALIGN 0 18109 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_BITS 1 18110 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_SHIFT 15 18111 18112 /* SerdesDigital :: Control1000X1 :: disable_signal_detect_filter [14:14] */ 18113 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK 0x4000 18114 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN 0 18115 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS 1 18116 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT 14 18117 18118 /* SerdesDigital :: Control1000X1 :: master_mdio_phy_sel [13:13] */ 18119 #define SERDESDIGITAL_CONTROL1000X1_MASTER_MDIO_PHY_SEL_MASK 0x2000 18120 #define SERDESDIGITAL_CONTROL1000X1_MASTER_MDIO_PHY_SEL_ALIGN 0 18121 #define SERDESDIGITAL_CONTROL1000X1_MASTER_MDIO_PHY_SEL_BITS 1 18122 #define SERDESDIGITAL_CONTROL1000X1_MASTER_MDIO_PHY_SEL_SHIFT 13 18123 18124 /* SerdesDigital :: Control1000X1 :: serdes_tx_amplitude_override [12:12] */ 18125 #define SERDESDIGITAL_CONTROL1000X1_SERDES_TX_AMPLITUDE_OVERRIDE_MASK 0x1000 18126 #define SERDESDIGITAL_CONTROL1000X1_SERDES_TX_AMPLITUDE_OVERRIDE_ALIGN 0 18127 #define SERDESDIGITAL_CONTROL1000X1_SERDES_TX_AMPLITUDE_OVERRIDE_BITS 1 18128 #define SERDESDIGITAL_CONTROL1000X1_SERDES_TX_AMPLITUDE_OVERRIDE_SHIFT 12 18129 18130 /* SerdesDigital :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */ 18131 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK 0x0800 18132 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN 0 18133 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS 1 18134 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT 11 18135 18136 /* SerdesDigital :: Control1000X1 :: remote_loopback [10:10] */ 18137 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_MASK 0x0400 18138 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN 0 18139 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_BITS 1 18140 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT 10 18141 18142 /* SerdesDigital :: Control1000X1 :: zero_comma_detector_phase [09:09] */ 18143 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200 18144 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0 18145 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1 18146 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9 18147 18148 /* SerdesDigital :: Control1000X1 :: comma_det_en [08:08] */ 18149 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_MASK 0x0100 18150 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_ALIGN 0 18151 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_BITS 1 18152 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_SHIFT 8 18153 18154 /* SerdesDigital :: Control1000X1 :: crc_checker_disable [07:07] */ 18155 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK 0x0080 18156 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN 0 18157 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS 1 18158 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT 7 18159 18160 /* SerdesDigital :: Control1000X1 :: disable_pll_pwrdwn [06:06] */ 18161 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK 0x0040 18162 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN 0 18163 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS 1 18164 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT 6 18165 18166 /* SerdesDigital :: Control1000X1 :: sgmii_master_mode [05:05] */ 18167 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_MASK 0x0020 18168 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN 0 18169 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_BITS 1 18170 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT 5 18171 18172 /* SerdesDigital :: Control1000X1 :: autodet_en [04:04] */ 18173 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_MASK 0x0010 18174 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_ALIGN 0 18175 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_BITS 1 18176 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_SHIFT 4 18177 18178 /* SerdesDigital :: Control1000X1 :: invert_signal_detect [03:03] */ 18179 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK 0x0008 18180 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN 0 18181 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS 1 18182 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT 3 18183 18184 /* SerdesDigital :: Control1000X1 :: signal_detect_en [02:02] */ 18185 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_MASK 0x0004 18186 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN 0 18187 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_BITS 1 18188 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT 2 18189 18190 /* SerdesDigital :: Control1000X1 :: tbi_interface [01:01] */ 18191 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_MASK 0x0002 18192 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_ALIGN 0 18193 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_BITS 1 18194 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_SHIFT 1 18195 18196 /* SerdesDigital :: Control1000X1 :: fiber_mode_1000X [00:00] */ 18197 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_MASK 0x0001 18198 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_ALIGN 0 18199 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_BITS 1 18200 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_SHIFT 0 18201 18202 18203 /**************************************************************************** 18204 * SerdesDigital :: Control1000X2 18205 */ 18206 /* SerdesDigital :: Control1000X2 :: disable_extend_fdx_only [15:15] */ 18207 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK 0x8000 18208 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN 0 18209 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS 1 18210 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT 15 18211 18212 /* SerdesDigital :: Control1000X2 :: clear_ber_counter [14:14] */ 18213 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_MASK 0x4000 18214 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN 0 18215 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_BITS 1 18216 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT 14 18217 18218 /* SerdesDigital :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */ 18219 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK 0x2000 18220 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN 0 18221 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS 1 18222 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT 13 18223 18224 /* SerdesDigital :: Control1000X2 :: transmit_packet_seq_test [12:12] */ 18225 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK 0x1000 18226 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN 0 18227 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS 1 18228 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT 12 18229 18230 /* SerdesDigital :: Control1000X2 :: test_cntr [11:11] */ 18231 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_MASK 0x0800 18232 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_ALIGN 0 18233 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_BITS 1 18234 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_SHIFT 11 18235 18236 /* SerdesDigital :: Control1000X2 :: bypass_pcs_tx [10:10] */ 18237 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_MASK 0x0400 18238 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_ALIGN 0 18239 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_BITS 1 18240 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_SHIFT 10 18241 18242 /* SerdesDigital :: Control1000X2 :: bypass_pcs_rx [09:09] */ 18243 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_MASK 0x0200 18244 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_ALIGN 0 18245 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_BITS 1 18246 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_SHIFT 9 18247 18248 /* SerdesDigital :: Control1000X2 :: disable_TRRR_generation [08:08] */ 18249 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK 0x0100 18250 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN 0 18251 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS 1 18252 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT 8 18253 18254 /* SerdesDigital :: Control1000X2 :: disable_carrier_extend [07:07] */ 18255 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK 0x0080 18256 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN 0 18257 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS 1 18258 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT 7 18259 18260 /* SerdesDigital :: Control1000X2 :: autoneg_fast_timers [06:06] */ 18261 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK 0x0040 18262 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN 0 18263 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS 1 18264 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT 6 18265 18266 /* SerdesDigital :: Control1000X2 :: force_xmit_data_on_txside [05:05] */ 18267 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK 0x0020 18268 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN 0 18269 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS 1 18270 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT 5 18271 18272 /* SerdesDigital :: Control1000X2 :: disable_remote_fault_sensing [04:04] */ 18273 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK 0x0010 18274 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN 0 18275 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS 1 18276 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT 4 18277 18278 /* SerdesDigital :: Control1000X2 :: enable_autoneg_err_timer [03:03] */ 18279 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK 0x0008 18280 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0 18281 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS 1 18282 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3 18283 18284 /* SerdesDigital :: Control1000X2 :: filter_force_link [02:02] */ 18285 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_MASK 0x0004 18286 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN 0 18287 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_BITS 1 18288 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT 2 18289 18290 /* SerdesDigital :: Control1000X2 :: disable_false_link [01:01] */ 18291 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_MASK 0x0002 18292 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN 0 18293 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_BITS 1 18294 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT 1 18295 18296 /* SerdesDigital :: Control1000X2 :: enable_parallel_detection [00:00] */ 18297 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_MASK 0x0001 18298 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_ALIGN 0 18299 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_BITS 1 18300 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_SHIFT 0 18301 18302 18303 /**************************************************************************** 18304 * SerdesDigital :: Control1000X3 18305 */ 18306 /* SerdesDigital :: Control1000X3 :: disable_packet_misalign [15:15] */ 18307 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK 0x8000 18308 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN 0 18309 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS 1 18310 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT 15 18311 18312 /* SerdesDigital :: Control1000X3 :: rxfifo_gmii_reset [14:14] */ 18313 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_MASK 0x4000 18314 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN 0 18315 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_BITS 1 18316 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT 14 18317 18318 /* SerdesDigital :: Control1000X3 :: disable_tx_crs [13:13] */ 18319 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_MASK 0x2000 18320 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_ALIGN 0 18321 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_BITS 1 18322 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_SHIFT 13 18323 18324 /* SerdesDigital :: Control1000X3 :: invert_ext_phy_crs [12:12] */ 18325 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK 0x1000 18326 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN 0 18327 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS 1 18328 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT 12 18329 18330 /* SerdesDigital :: Control1000X3 :: ext_phy_crs_mode [11:11] */ 18331 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK 0x0800 18332 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN 0 18333 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS 1 18334 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT 11 18335 18336 /* SerdesDigital :: Control1000X3 :: jam_false_carrier_mode [10:10] */ 18337 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK 0x0400 18338 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN 0 18339 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS 1 18340 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT 10 18341 18342 /* SerdesDigital :: Control1000X3 :: block_txen_mode [09:09] */ 18343 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_MASK 0x0200 18344 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN 0 18345 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_BITS 1 18346 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT 9 18347 18348 /* SerdesDigital :: Control1000X3 :: force_txfifo_on [08:08] */ 18349 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_MASK 0x0100 18350 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN 0 18351 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_BITS 1 18352 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT 8 18353 18354 /* SerdesDigital :: Control1000X3 :: bypass_txfifo1000 [07:07] */ 18355 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_MASK 0x0080 18356 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN 0 18357 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_BITS 1 18358 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT 7 18359 18360 /* SerdesDigital :: Control1000X3 :: freq_lock_elasticity_tx [06:06] */ 18361 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_MASK 0x0040 18362 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_ALIGN 0 18363 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_BITS 1 18364 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_SHIFT 6 18365 18366 /* SerdesDigital :: Control1000X3 :: freq_lock_elasticity_rx [05:05] */ 18367 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_MASK 0x0020 18368 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_ALIGN 0 18369 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_BITS 1 18370 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_SHIFT 5 18371 18372 /* SerdesDigital :: Control1000X3 :: early_preamble_rx [04:04] */ 18373 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK 0x0010 18374 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN 0 18375 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS 1 18376 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT 4 18377 18378 /* SerdesDigital :: Control1000X3 :: early_preamble_tx [03:03] */ 18379 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK 0x0008 18380 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN 0 18381 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS 1 18382 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT 3 18383 18384 /* SerdesDigital :: Control1000X3 :: fifo_elasicity_tx_rx [02:01] */ 18385 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_MASK 0x0006 18386 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_ALIGN 0 18387 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_BITS 2 18388 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_SHIFT 1 18389 18390 /* SerdesDigital :: Control1000X3 :: tx_fifo_rst [00:00] */ 18391 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_MASK 0x0001 18392 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_ALIGN 0 18393 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_BITS 1 18394 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_SHIFT 0 18395 18396 18397 /**************************************************************************** 18398 * SerdesDigital :: Control1000X4 18399 */ 18400 /* SerdesDigital :: Control1000X4 :: reserved0 [15:14] */ 18401 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_MASK 0xc000 18402 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_ALIGN 0 18403 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_BITS 2 18404 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_SHIFT 14 18405 18406 /* SerdesDigital :: Control1000X4 :: disable_resolution_err_restart [13:13] */ 18407 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK 0x2000 18408 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0 18409 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS 1 18410 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13 18411 18412 /* SerdesDigital :: Control1000X4 :: enable_last_resolution_err [12:12] */ 18413 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK 0x1000 18414 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN 0 18415 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS 1 18416 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT 12 18417 18418 /* SerdesDigital :: Control1000X4 :: tx_config_reg_sel [11:11] */ 18419 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK 0x0800 18420 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN 0 18421 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS 1 18422 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT 11 18423 18424 /* SerdesDigital :: Control1000X4 :: zero_rxdgmii [10:10] */ 18425 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_MASK 0x0400 18426 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_ALIGN 0 18427 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_BITS 1 18428 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_SHIFT 10 18429 18430 /* SerdesDigital :: Control1000X4 :: clear_linkdown [09:09] */ 18431 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_MASK 0x0200 18432 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN 0 18433 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_BITS 1 18434 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT 9 18435 18436 /* SerdesDigital :: Control1000X4 :: latch_linkdown_enable [08:08] */ 18437 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK 0x0100 18438 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN 0 18439 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS 1 18440 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT 8 18441 18442 /* SerdesDigital :: Control1000X4 :: link_force [07:07] */ 18443 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_MASK 0x0080 18444 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_ALIGN 0 18445 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_BITS 1 18446 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_SHIFT 7 18447 18448 /* SerdesDigital :: Control1000X4 :: reserved1 [06:06] */ 18449 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_MASK 0x0040 18450 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_ALIGN 0 18451 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_BITS 1 18452 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_SHIFT 6 18453 18454 /* SerdesDigital :: Control1000X4 :: lp_next_page_sel [05:05] */ 18455 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_MASK 0x0020 18456 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_ALIGN 0 18457 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_BITS 1 18458 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_SHIFT 5 18459 18460 /* SerdesDigital :: Control1000X4 :: np_count_ClrnBp [04:04] */ 18461 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_MASK 0x0010 18462 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_ALIGN 0 18463 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_BITS 1 18464 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_SHIFT 4 18465 18466 /* SerdesDigital :: Control1000X4 :: np_count_ClrnRd [03:03] */ 18467 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_MASK 0x0008 18468 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_ALIGN 0 18469 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_BITS 1 18470 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_SHIFT 3 18471 18472 /* SerdesDigital :: Control1000X4 :: MiscRxStatus_sel [02:00] */ 18473 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_MASK 0x0007 18474 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN 0 18475 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_BITS 3 18476 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT 0 18477 18478 18479 /**************************************************************************** 18480 * SerdesDigital :: Status1000X1 18481 */ 18482 /* SerdesDigital :: Status1000X1 :: txfifo_err_detected [15:15] */ 18483 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK 0x8000 18484 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN 0 18485 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS 1 18486 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT 15 18487 18488 /* SerdesDigital :: Status1000X1 :: rxfifo_err_detected [14:14] */ 18489 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK 0x4000 18490 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN 0 18491 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS 1 18492 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT 14 18493 18494 /* SerdesDigital :: Status1000X1 :: false_carrier_detected [13:13] */ 18495 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK 0x2000 18496 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN 0 18497 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS 1 18498 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT 13 18499 18500 /* SerdesDigital :: Status1000X1 :: crc_err_detected [12:12] */ 18501 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_MASK 0x1000 18502 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_ALIGN 0 18503 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_BITS 1 18504 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_SHIFT 12 18505 18506 /* SerdesDigital :: Status1000X1 :: tx_err_detected [11:11] */ 18507 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_MASK 0x0800 18508 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_ALIGN 0 18509 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_BITS 1 18510 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_SHIFT 11 18511 18512 /* SerdesDigital :: Status1000X1 :: rx_err_detected [10:10] */ 18513 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_MASK 0x0400 18514 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_ALIGN 0 18515 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_BITS 1 18516 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_SHIFT 10 18517 18518 /* SerdesDigital :: Status1000X1 :: carrier_extend_err_detected [09:09] */ 18519 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200 18520 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0 18521 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1 18522 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9 18523 18524 /* SerdesDigital :: Status1000X1 :: early_end_extension_detected [08:08] */ 18525 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100 18526 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0 18527 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1 18528 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8 18529 18530 /* SerdesDigital :: Status1000X1 :: link_status_change [07:07] */ 18531 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_MASK 0x0080 18532 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN 0 18533 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_BITS 1 18534 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT 7 18535 18536 /* SerdesDigital :: Status1000X1 :: pause_resolution_rxside [06:06] */ 18537 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0040 18538 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 18539 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS 1 18540 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT 6 18541 18542 /* SerdesDigital :: Status1000X1 :: pause_resolution_txside [05:05] */ 18543 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0020 18544 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 18545 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS 1 18546 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT 5 18547 18548 /* SerdesDigital :: Status1000X1 :: speed_status [04:03] */ 18549 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_MASK 0x0018 18550 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_ALIGN 0 18551 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_BITS 2 18552 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_SHIFT 3 18553 18554 /* SerdesDigital :: Status1000X1 :: duplex_status [02:02] */ 18555 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_MASK 0x0004 18556 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_ALIGN 0 18557 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_BITS 1 18558 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_SHIFT 2 18559 18560 /* SerdesDigital :: Status1000X1 :: link_status [01:01] */ 18561 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_MASK 0x0002 18562 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_ALIGN 0 18563 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_BITS 1 18564 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_SHIFT 1 18565 18566 /* SerdesDigital :: Status1000X1 :: sgmii_mode [00:00] */ 18567 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_MASK 0x0001 18568 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_ALIGN 0 18569 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_BITS 1 18570 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_SHIFT 0 18571 18572 18573 /**************************************************************************** 18574 * SerdesDigital :: Status1000X2 18575 */ 18576 /* SerdesDigital :: Status1000X2 :: sgmii_mode_change [15:15] */ 18577 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_MASK 0x8000 18578 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN 0 18579 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_BITS 1 18580 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT 15 18581 18582 /* SerdesDigital :: Status1000X2 :: consistency_mismatch [14:14] */ 18583 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_MASK 0x4000 18584 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN 0 18585 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_BITS 1 18586 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT 14 18587 18588 /* SerdesDigital :: Status1000X2 :: autoneg_resolution_err [13:13] */ 18589 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK 0x2000 18590 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN 0 18591 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS 1 18592 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT 13 18593 18594 /* SerdesDigital :: Status1000X2 :: sgmii_selector_mismatch [12:12] */ 18595 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK 0x1000 18596 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN 0 18597 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS 1 18598 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT 12 18599 18600 /* SerdesDigital :: Status1000X2 :: sync_status_fail [11:11] */ 18601 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_MASK 0x0800 18602 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN 0 18603 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_BITS 1 18604 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT 11 18605 18606 /* SerdesDigital :: Status1000X2 :: sync_status_ok [10:10] */ 18607 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_MASK 0x0400 18608 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_ALIGN 0 18609 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_BITS 1 18610 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_SHIFT 10 18611 18612 /* SerdesDigital :: Status1000X2 :: rudi_c [09:09] */ 18613 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_MASK 0x0200 18614 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_ALIGN 0 18615 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_BITS 1 18616 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_SHIFT 9 18617 18618 /* SerdesDigital :: Status1000X2 :: rudi_I [08:08] */ 18619 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_MASK 0x0100 18620 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_ALIGN 0 18621 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_BITS 1 18622 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_SHIFT 8 18623 18624 /* SerdesDigital :: Status1000X2 :: rudi_invalid [07:07] */ 18625 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_MASK 0x0080 18626 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_ALIGN 0 18627 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_BITS 1 18628 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_SHIFT 7 18629 18630 /* SerdesDigital :: Status1000X2 :: linkDown_syncLoss [06:06] */ 18631 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK 0x0040 18632 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN 0 18633 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS 1 18634 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT 6 18635 18636 /* SerdesDigital :: Status1000X2 :: idle_detect_state [05:05] */ 18637 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_MASK 0x0020 18638 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_ALIGN 0 18639 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_BITS 1 18640 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_SHIFT 5 18641 18642 /* SerdesDigital :: Status1000X2 :: complete_acknowledge_state [04:04] */ 18643 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010 18644 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0 18645 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1 18646 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4 18647 18648 /* SerdesDigital :: Status1000X2 :: acknowledge_detect_state [03:03] */ 18649 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK 0x0008 18650 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0 18651 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS 1 18652 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3 18653 18654 /* SerdesDigital :: Status1000X2 :: ability_detect_state [02:02] */ 18655 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_MASK 0x0004 18656 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN 0 18657 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_BITS 1 18658 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT 2 18659 18660 /* union - case anError [01:01] */ 18661 /* SerdesDigital :: Status1000X2 :: an_error_state [01:01] */ 18662 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK 0x0002 18663 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN 0 18664 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS 1 18665 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT 1 18666 18667 18668 /* union - case anDisableLink [01:01] */ 18669 /* SerdesDigital :: Status1000X2 :: an_disable_link_ok_state [01:01] */ 18670 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002 18671 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0 18672 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1 18673 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1 18674 18675 18676 /* SerdesDigital :: Status1000X2 :: an_enable_state [00:00] */ 18677 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_MASK 0x0001 18678 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_ALIGN 0 18679 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_BITS 1 18680 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_SHIFT 0 18681 18682 18683 /**************************************************************************** 18684 * SerdesDigital :: Status1000X3 18685 */ 18686 /* SerdesDigital :: Status1000X3 :: reserved0 [15:13] */ 18687 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_MASK 0xe000 18688 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_ALIGN 0 18689 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_BITS 3 18690 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_SHIFT 13 18691 18692 /* SerdesDigital :: Status1000X3 :: pd_park_an [12:12] */ 18693 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_MASK 0x1000 18694 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_ALIGN 0 18695 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_BITS 1 18696 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_SHIFT 12 18697 18698 /* SerdesDigital :: Status1000X3 :: remotePhy_autosel [11:11] */ 18699 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK 0x0800 18700 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN 0 18701 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS 1 18702 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT 11 18703 18704 /* SerdesDigital :: Status1000X3 :: latch_linkdown [10:10] */ 18705 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_MASK 0x0400 18706 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_ALIGN 0 18707 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_BITS 1 18708 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_SHIFT 10 18709 18710 /* SerdesDigital :: Status1000X3 :: sd_filter [09:09] */ 18711 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_MASK 0x0200 18712 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_ALIGN 0 18713 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_BITS 1 18714 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_SHIFT 9 18715 18716 /* SerdesDigital :: Status1000X3 :: sd_mux [08:08] */ 18717 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_MASK 0x0100 18718 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_ALIGN 0 18719 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_BITS 1 18720 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_SHIFT 8 18721 18722 /* SerdesDigital :: Status1000X3 :: sd_filter_chg [07:07] */ 18723 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_MASK 0x0080 18724 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_ALIGN 0 18725 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_BITS 1 18726 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_SHIFT 7 18727 18728 /* SerdesDigital :: Status1000X3 :: reserved1 [06:00] */ 18729 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_MASK 0x007f 18730 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_ALIGN 0 18731 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_BITS 7 18732 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_SHIFT 0 18733 18734 18735 /**************************************************************************** 18736 * SerdesDigital :: CrcErr_RxPkt 18737 */ 18738 /* SerdesDigital :: CrcErr_RxPkt :: badCodeGroups [15:08] */ 18739 #define SERDESDIGITAL_CRCERR_RXPKT_BADCODEGROUPS_MASK 0xff00 18740 #define SERDESDIGITAL_CRCERR_RXPKT_BADCODEGROUPS_ALIGN 0 18741 #define SERDESDIGITAL_CRCERR_RXPKT_BADCODEGROUPS_BITS 8 18742 #define SERDESDIGITAL_CRCERR_RXPKT_BADCODEGROUPS_SHIFT 8 18743 18744 /* SerdesDigital :: CrcErr_RxPkt :: crcErr_rxPkt [07:00] */ 18745 #define SERDESDIGITAL_CRCERR_RXPKT_CRCERR_RXPKT_MASK 0x00ff 18746 #define SERDESDIGITAL_CRCERR_RXPKT_CRCERR_RXPKT_ALIGN 0 18747 #define SERDESDIGITAL_CRCERR_RXPKT_CRCERR_RXPKT_BITS 8 18748 #define SERDESDIGITAL_CRCERR_RXPKT_CRCERR_RXPKT_SHIFT 0 18749 18750 18751 /**************************************************************************** 18752 * SerdesDigital :: Misc1 18753 */ 18754 /* SerdesDigital :: Misc1 :: refclk_sel [15:13] */ 18755 #define SERDESDIGITAL_MISC1_REFCLK_SEL_MASK 0xe000 18756 #define SERDESDIGITAL_MISC1_REFCLK_SEL_ALIGN 0 18757 #define SERDESDIGITAL_MISC1_REFCLK_SEL_BITS 3 18758 #define SERDESDIGITAL_MISC1_REFCLK_SEL_SHIFT 13 18759 18760 /* SerdesDigital :: Misc1 :: force_pll_mode_afe_sel [12:12] */ 18761 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_MASK 0x1000 18762 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_ALIGN 0 18763 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_BITS 1 18764 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_SHIFT 12 18765 18766 /* SerdesDigital :: Misc1 :: force_pll_mode_afe [11:08] */ 18767 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_MASK 0x0f00 18768 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_ALIGN 0 18769 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_BITS 4 18770 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SHIFT 8 18771 18772 /* SerdesDigital :: Misc1 :: reserved0 [07:07] */ 18773 #define SERDESDIGITAL_MISC1_RESERVED0_MASK 0x0080 18774 #define SERDESDIGITAL_MISC1_RESERVED0_ALIGN 0 18775 #define SERDESDIGITAL_MISC1_RESERVED0_BITS 1 18776 #define SERDESDIGITAL_MISC1_RESERVED0_SHIFT 7 18777 18778 /* SerdesDigital :: Misc1 :: tx_underrun_1000_dis [06:06] */ 18779 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_MASK 0x0040 18780 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_ALIGN 0 18781 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_BITS 1 18782 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_SHIFT 6 18783 18784 /* SerdesDigital :: Misc1 :: force_ln_mode [05:05] */ 18785 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_MASK 0x0020 18786 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_ALIGN 0 18787 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_BITS 1 18788 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_SHIFT 5 18789 18790 /* SerdesDigital :: Misc1 :: force_speed_sel [04:04] */ 18791 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_MASK 0x0010 18792 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_ALIGN 0 18793 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_BITS 1 18794 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_SHIFT 4 18795 18796 /* SerdesDigital :: Misc1 :: force_speed [03:00] */ 18797 #define SERDESDIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 18798 #define SERDESDIGITAL_MISC1_FORCE_SPEED_ALIGN 0 18799 #define SERDESDIGITAL_MISC1_FORCE_SPEED_BITS 4 18800 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SHIFT 0 18801 18802 18803 /**************************************************************************** 18804 * SerdesDigital :: Misc2 18805 */ 18806 /* SerdesDigital :: Misc2 :: rxckpl_sel_combo [15:15] */ 18807 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_MASK 0x8000 18808 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_ALIGN 0 18809 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_BITS 1 18810 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_SHIFT 15 18811 18812 /* SerdesDigital :: Misc2 :: rxck_mii_gen_sel_force [14:14] */ 18813 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_MASK 0x4000 18814 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_ALIGN 0 18815 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_BITS 1 18816 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_SHIFT 14 18817 18818 /* SerdesDigital :: Misc2 :: rxck_mii_gen_sel_val [13:13] */ 18819 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_MASK 0x2000 18820 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_ALIGN 0 18821 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_BITS 1 18822 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_SHIFT 13 18823 18824 /* SerdesDigital :: Misc2 :: rlpbk_sw_force [12:12] */ 18825 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_MASK 0x1000 18826 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_ALIGN 0 18827 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_BITS 1 18828 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_SHIFT 12 18829 18830 /* SerdesDigital :: Misc2 :: rlpbk_RxRst_en [11:11] */ 18831 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_MASK 0x0800 18832 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_ALIGN 0 18833 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_BITS 1 18834 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_SHIFT 11 18835 18836 /* SerdesDigital :: Misc2 :: clkSigdet_bypass [10:10] */ 18837 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_MASK 0x0400 18838 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_ALIGN 0 18839 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_BITS 1 18840 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_SHIFT 10 18841 18842 /* SerdesDigital :: Misc2 :: clk41_bypass [09:09] */ 18843 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_MASK 0x0200 18844 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_ALIGN 0 18845 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_BITS 1 18846 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_SHIFT 9 18847 18848 /* SerdesDigital :: Misc2 :: reserved0 [08:06] */ 18849 #define SERDESDIGITAL_MISC2_RESERVED0_MASK 0x01c0 18850 #define SERDESDIGITAL_MISC2_RESERVED0_ALIGN 0 18851 #define SERDESDIGITAL_MISC2_RESERVED0_BITS 3 18852 #define SERDESDIGITAL_MISC2_RESERVED0_SHIFT 6 18853 18854 /* SerdesDigital :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */ 18855 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK 0x0020 18856 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN 0 18857 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS 1 18858 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT 5 18859 18860 /* SerdesDigital :: Misc2 :: fifo_err_cya [04:04] */ 18861 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_MASK 0x0010 18862 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_ALIGN 0 18863 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_BITS 1 18864 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_SHIFT 4 18865 18866 /* SerdesDigital :: Misc2 :: an_txdisablePhase [03:03] */ 18867 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_MASK 0x0008 18868 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_ALIGN 0 18869 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_BITS 1 18870 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_SHIFT 3 18871 18872 /* SerdesDigital :: Misc2 :: an_rxSeqStartDis [02:02] */ 18873 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_MASK 0x0004 18874 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_ALIGN 0 18875 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_BITS 1 18876 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_SHIFT 2 18877 18878 /* SerdesDigital :: Misc2 :: an_txdisable_ln [01:01] */ 18879 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_MASK 0x0002 18880 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_ALIGN 0 18881 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_BITS 1 18882 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_SHIFT 1 18883 18884 /* SerdesDigital :: Misc2 :: an_deadTrap [00:00] */ 18885 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_MASK 0x0001 18886 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_ALIGN 0 18887 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_BITS 1 18888 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_SHIFT 0 18889 18890 18891 /**************************************************************************** 18892 * SerdesDigital :: PatGenCtrl 18893 */ 18894 /* SerdesDigital :: PatGenCtrl :: reserved0 [15:15] */ 18895 #define SERDESDIGITAL_PATGENCTRL_RESERVED0_MASK 0x8000 18896 #define SERDESDIGITAL_PATGENCTRL_RESERVED0_ALIGN 0 18897 #define SERDESDIGITAL_PATGENCTRL_RESERVED0_BITS 1 18898 #define SERDESDIGITAL_PATGENCTRL_RESERVED0_SHIFT 15 18899 18900 /* SerdesDigital :: PatGenCtrl :: tx_err [14:14] */ 18901 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_MASK 0x4000 18902 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_ALIGN 0 18903 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_BITS 1 18904 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_SHIFT 14 18905 18906 /* SerdesDigital :: PatGenCtrl :: skip_crc [13:13] */ 18907 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_MASK 0x2000 18908 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_ALIGN 0 18909 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_BITS 1 18910 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_SHIFT 13 18911 18912 /* SerdesDigital :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */ 18913 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK 0x1000 18914 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN 0 18915 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS 1 18916 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT 12 18917 18918 /* SerdesDigital :: PatGenCtrl :: ipg_select [11:09] */ 18919 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_MASK 0x0e00 18920 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_ALIGN 0 18921 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_BITS 3 18922 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_SHIFT 9 18923 18924 /* SerdesDigital :: PatGenCtrl :: pkt_size [08:03] */ 18925 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_MASK 0x01f8 18926 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_ALIGN 0 18927 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_BITS 6 18928 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_SHIFT 3 18929 18930 /* SerdesDigital :: PatGenCtrl :: single_pass_mode [02:02] */ 18931 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_MASK 0x0004 18932 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_ALIGN 0 18933 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_BITS 1 18934 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_SHIFT 2 18935 18936 /* SerdesDigital :: PatGenCtrl :: run_pattern_gen [01:01] */ 18937 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_MASK 0x0002 18938 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_ALIGN 0 18939 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_BITS 1 18940 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_SHIFT 1 18941 18942 /* SerdesDigital :: PatGenCtrl :: sel_pattern_gen_data [00:00] */ 18943 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK 0x0001 18944 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN 0 18945 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS 1 18946 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT 0 18947 18948 18949 /**************************************************************************** 18950 * SerdesDigital :: PatGenStat 18951 */ 18952 /* SerdesDigital :: PatGenStat :: reserved0 [15:04] */ 18953 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_MASK 0xfff0 18954 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_ALIGN 0 18955 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_BITS 12 18956 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_SHIFT 4 18957 18958 /* SerdesDigital :: PatGenStat :: pattern_gen_active [03:03] */ 18959 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK 0x0008 18960 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN 0 18961 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS 1 18962 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT 3 18963 18964 /* SerdesDigital :: PatGenStat :: pattern_gen_fsm [02:00] */ 18965 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_MASK 0x0007 18966 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_ALIGN 0 18967 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_BITS 3 18968 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_SHIFT 0 18969 18970 18971 /**************************************************************************** 18972 * SerdesDigital :: TestMode 18973 */ 18974 /* SerdesDigital :: TestMode :: disable_reset_cnt [15:15] */ 18975 #define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_MASK 0x8000 18976 #define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_ALIGN 0 18977 #define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_BITS 1 18978 #define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_SHIFT 15 18979 18980 /* SerdesDigital :: TestMode :: clear_packet_counters [14:14] */ 18981 #define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_MASK 0x4000 18982 #define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_ALIGN 0 18983 #define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_BITS 1 18984 #define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_SHIFT 14 18985 18986 /* SerdesDigital :: TestMode :: reserved0 [13:12] */ 18987 #define SERDESDIGITAL_TESTMODE_RESERVED0_MASK 0x3000 18988 #define SERDESDIGITAL_TESTMODE_RESERVED0_ALIGN 0 18989 #define SERDESDIGITAL_TESTMODE_RESERVED0_BITS 2 18990 #define SERDESDIGITAL_TESTMODE_RESERVED0_SHIFT 12 18991 18992 /* SerdesDigital :: TestMode :: test_monitor_mode2 [11:06] */ 18993 #define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE2_MASK 0x0fc0 18994 #define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE2_ALIGN 0 18995 #define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE2_BITS 6 18996 #define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE2_SHIFT 6 18997 18998 /* SerdesDigital :: TestMode :: test_monitor_mode1 [05:00] */ 18999 #define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE1_MASK 0x003f 19000 #define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE1_ALIGN 0 19001 #define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE1_BITS 6 19002 #define SERDESDIGITAL_TESTMODE_TEST_MONITOR_MODE1_SHIFT 0 19003 19004 19005 /**************************************************************************** 19006 * SerdesDigital :: TxPktCnt 19007 */ 19008 /* SerdesDigital :: TxPktCnt :: TxPktCnt [15:00] */ 19009 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_MASK 0xffff 19010 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_ALIGN 0 19011 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_BITS 16 19012 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_SHIFT 0 19013 19014 19015 /**************************************************************************** 19016 * SerdesDigital :: RxPktCnt 19017 */ 19018 /* SerdesDigital :: RxPktCnt :: RxPktCnt [15:00] */ 19019 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_MASK 0xffff 19020 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_ALIGN 0 19021 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_BITS 16 19022 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_SHIFT 0 19023 19024 19025 /**************************************************************************** 19026 * XGXS16G_USER_serdesID 19027 */ 19028 /**************************************************************************** 19029 * serdesID :: serdesID0 19030 */ 19031 /* serdesID :: serdesID0 :: rev_letter [15:14] */ 19032 #define SERDESID_SERDESID0_REV_LETTER_MASK 0xc000 19033 #define SERDESID_SERDESID0_REV_LETTER_ALIGN 0 19034 #define SERDESID_SERDESID0_REV_LETTER_BITS 2 19035 #define SERDESID_SERDESID0_REV_LETTER_SHIFT 14 19036 19037 /* serdesID :: serdesID0 :: rev_number [13:11] */ 19038 #define SERDESID_SERDESID0_REV_NUMBER_MASK 0x3800 19039 #define SERDESID_SERDESID0_REV_NUMBER_ALIGN 0 19040 #define SERDESID_SERDESID0_REV_NUMBER_BITS 3 19041 #define SERDESID_SERDESID0_REV_NUMBER_SHIFT 11 19042 19043 /* serdesID :: serdesID0 :: bonding [10:09] */ 19044 #define SERDESID_SERDESID0_BONDING_MASK 0x0600 19045 #define SERDESID_SERDESID0_BONDING_ALIGN 0 19046 #define SERDESID_SERDESID0_BONDING_BITS 2 19047 #define SERDESID_SERDESID0_BONDING_SHIFT 9 19048 19049 /* serdesID :: serdesID0 :: tech_proc [08:06] */ 19050 #define SERDESID_SERDESID0_TECH_PROC_MASK 0x01c0 19051 #define SERDESID_SERDESID0_TECH_PROC_ALIGN 0 19052 #define SERDESID_SERDESID0_TECH_PROC_BITS 3 19053 #define SERDESID_SERDESID0_TECH_PROC_SHIFT 6 19054 19055 /* serdesID :: serdesID0 :: model_number [05:00] */ 19056 #define SERDESID_SERDESID0_MODEL_NUMBER_MASK 0x003f 19057 #define SERDESID_SERDESID0_MODEL_NUMBER_ALIGN 0 19058 #define SERDESID_SERDESID0_MODEL_NUMBER_BITS 6 19059 #define SERDESID_SERDESID0_MODEL_NUMBER_SHIFT 0 19060 19061 19062 /**************************************************************************** 19063 * serdesID :: serdesID1 19064 */ 19065 /* serdesID :: serdesID1 :: multiplicity [15:12] */ 19066 #define SERDESID_SERDESID1_MULTIPLICITY_MASK 0xf000 19067 #define SERDESID_SERDESID1_MULTIPLICITY_ALIGN 0 19068 #define SERDESID_SERDESID1_MULTIPLICITY_BITS 4 19069 #define SERDESID_SERDESID1_MULTIPLICITY_SHIFT 12 19070 19071 /* serdesID :: serdesID1 :: CL37 [11:11] */ 19072 #define SERDESID_SERDESID1_CL37_MASK 0x0800 19073 #define SERDESID_SERDESID1_CL37_ALIGN 0 19074 #define SERDESID_SERDESID1_CL37_BITS 1 19075 #define SERDESID_SERDESID1_CL37_SHIFT 11 19076 19077 /* serdesID :: serdesID1 :: CL73 [10:10] */ 19078 #define SERDESID_SERDESID1_CL73_MASK 0x0400 19079 #define SERDESID_SERDESID1_CL73_ALIGN 0 19080 #define SERDESID_SERDESID1_CL73_BITS 1 19081 #define SERDESID_SERDESID1_CL73_SHIFT 10 19082 19083 /* serdesID :: serdesID1 :: CL36 [09:09] */ 19084 #define SERDESID_SERDESID1_CL36_MASK 0x0200 19085 #define SERDESID_SERDESID1_CL36_ALIGN 0 19086 #define SERDESID_SERDESID1_CL36_BITS 1 19087 #define SERDESID_SERDESID1_CL36_SHIFT 9 19088 19089 /* serdesID :: serdesID1 :: CL48 [08:08] */ 19090 #define SERDESID_SERDESID1_CL48_MASK 0x0100 19091 #define SERDESID_SERDESID1_CL48_ALIGN 0 19092 #define SERDESID_SERDESID1_CL48_BITS 1 19093 #define SERDESID_SERDESID1_CL48_SHIFT 8 19094 19095 /* serdesID :: serdesID1 :: HiGig [07:07] */ 19096 #define SERDESID_SERDESID1_HIGIG_MASK 0x0080 19097 #define SERDESID_SERDESID1_HIGIG_ALIGN 0 19098 #define SERDESID_SERDESID1_HIGIG_BITS 1 19099 #define SERDESID_SERDESID1_HIGIG_SHIFT 7 19100 19101 /* serdesID :: serdesID1 :: HiGigII [06:06] */ 19102 #define SERDESID_SERDESID1_HIGIGII_MASK 0x0040 19103 #define SERDESID_SERDESID1_HIGIGII_ALIGN 0 19104 #define SERDESID_SERDESID1_HIGIGII_BITS 1 19105 #define SERDESID_SERDESID1_HIGIGII_SHIFT 6 19106 19107 /* serdesID :: serdesID1 :: PCIE [05:05] */ 19108 #define SERDESID_SERDESID1_PCIE_MASK 0x0020 19109 #define SERDESID_SERDESID1_PCIE_ALIGN 0 19110 #define SERDESID_SERDESID1_PCIE_BITS 1 19111 #define SERDESID_SERDESID1_PCIE_SHIFT 5 19112 19113 /* serdesID :: serdesID1 :: PCIE_II [04:04] */ 19114 #define SERDESID_SERDESID1_PCIE_II_MASK 0x0010 19115 #define SERDESID_SERDESID1_PCIE_II_ALIGN 0 19116 #define SERDESID_SERDESID1_PCIE_II_BITS 1 19117 #define SERDESID_SERDESID1_PCIE_II_SHIFT 4 19118 19119 /* serdesID :: serdesID1 :: brcm_64B66B [03:03] */ 19120 #define SERDESID_SERDESID1_BRCM_64B66B_MASK 0x0008 19121 #define SERDESID_SERDESID1_BRCM_64B66B_ALIGN 0 19122 #define SERDESID_SERDESID1_BRCM_64B66B_BITS 1 19123 #define SERDESID_SERDESID1_BRCM_64B66B_SHIFT 3 19124 19125 /* serdesID :: serdesID1 :: Scrambler [02:02] */ 19126 #define SERDESID_SERDESID1_SCRAMBLER_MASK 0x0004 19127 #define SERDESID_SERDESID1_SCRAMBLER_ALIGN 0 19128 #define SERDESID_SERDESID1_SCRAMBLER_BITS 1 19129 #define SERDESID_SERDESID1_SCRAMBLER_SHIFT 2 19130 19131 /* serdesID :: serdesID1 :: reserved0 [01:00] */ 19132 #define SERDESID_SERDESID1_RESERVED0_MASK 0x0003 19133 #define SERDESID_SERDESID1_RESERVED0_ALIGN 0 19134 #define SERDESID_SERDESID1_RESERVED0_BITS 2 19135 #define SERDESID_SERDESID1_RESERVED0_SHIFT 0 19136 19137 19138 /**************************************************************************** 19139 * serdesID :: serdesID2 19140 */ 19141 /* serdesID :: serdesID2 :: ID3present [15:15] */ 19142 #define SERDESID_SERDESID2_ID3PRESENT_MASK 0x8000 19143 #define SERDESID_SERDESID2_ID3PRESENT_ALIGN 0 19144 #define SERDESID_SERDESID2_ID3PRESENT_BITS 1 19145 #define SERDESID_SERDESID2_ID3PRESENT_SHIFT 15 19146 19147 /* serdesID :: serdesID2 :: dr_25G_4L [14:14] */ 19148 #define SERDESID_SERDESID2_DR_25G_4L_MASK 0x4000 19149 #define SERDESID_SERDESID2_DR_25G_4L_ALIGN 0 19150 #define SERDESID_SERDESID2_DR_25G_4L_BITS 1 19151 #define SERDESID_SERDESID2_DR_25G_4L_SHIFT 14 19152 19153 /* serdesID :: serdesID2 :: dr_21G_4L [13:13] */ 19154 #define SERDESID_SERDESID2_DR_21G_4L_MASK 0x2000 19155 #define SERDESID_SERDESID2_DR_21G_4L_ALIGN 0 19156 #define SERDESID_SERDESID2_DR_21G_4L_BITS 1 19157 #define SERDESID_SERDESID2_DR_21G_4L_SHIFT 13 19158 19159 /* serdesID :: serdesID2 :: dr_20G_4L [12:12] */ 19160 #define SERDESID_SERDESID2_DR_20G_4L_MASK 0x1000 19161 #define SERDESID_SERDESID2_DR_20G_4L_ALIGN 0 19162 #define SERDESID_SERDESID2_DR_20G_4L_BITS 1 19163 #define SERDESID_SERDESID2_DR_20G_4L_SHIFT 12 19164 19165 /* serdesID :: serdesID2 :: dr_16G_4L [11:11] */ 19166 #define SERDESID_SERDESID2_DR_16G_4L_MASK 0x0800 19167 #define SERDESID_SERDESID2_DR_16G_4L_ALIGN 0 19168 #define SERDESID_SERDESID2_DR_16G_4L_BITS 1 19169 #define SERDESID_SERDESID2_DR_16G_4L_SHIFT 11 19170 19171 /* serdesID :: serdesID2 :: dr_15G_4L [10:10] */ 19172 #define SERDESID_SERDESID2_DR_15G_4L_MASK 0x0400 19173 #define SERDESID_SERDESID2_DR_15G_4L_ALIGN 0 19174 #define SERDESID_SERDESID2_DR_15G_4L_BITS 1 19175 #define SERDESID_SERDESID2_DR_15G_4L_SHIFT 10 19176 19177 /* serdesID :: serdesID2 :: dr_13G_4L [09:09] */ 19178 #define SERDESID_SERDESID2_DR_13G_4L_MASK 0x0200 19179 #define SERDESID_SERDESID2_DR_13G_4L_ALIGN 0 19180 #define SERDESID_SERDESID2_DR_13G_4L_BITS 1 19181 #define SERDESID_SERDESID2_DR_13G_4L_SHIFT 9 19182 19183 /* serdesID :: serdesID2 :: dr_12_5G_4L [08:08] */ 19184 #define SERDESID_SERDESID2_DR_12_5G_4L_MASK 0x0100 19185 #define SERDESID_SERDESID2_DR_12_5G_4L_ALIGN 0 19186 #define SERDESID_SERDESID2_DR_12_5G_4L_BITS 1 19187 #define SERDESID_SERDESID2_DR_12_5G_4L_SHIFT 8 19188 19189 /* serdesID :: serdesID2 :: dr_12G_4L [07:07] */ 19190 #define SERDESID_SERDESID2_DR_12G_4L_MASK 0x0080 19191 #define SERDESID_SERDESID2_DR_12G_4L_ALIGN 0 19192 #define SERDESID_SERDESID2_DR_12G_4L_BITS 1 19193 #define SERDESID_SERDESID2_DR_12G_4L_SHIFT 7 19194 19195 /* serdesID :: serdesID2 :: dr_10G_4L [06:06] */ 19196 #define SERDESID_SERDESID2_DR_10G_4L_MASK 0x0040 19197 #define SERDESID_SERDESID2_DR_10G_4L_ALIGN 0 19198 #define SERDESID_SERDESID2_DR_10G_4L_BITS 1 19199 #define SERDESID_SERDESID2_DR_10G_4L_SHIFT 6 19200 19201 /* serdesID :: serdesID2 :: dr_6G_4L [05:05] */ 19202 #define SERDESID_SERDESID2_DR_6G_4L_MASK 0x0020 19203 #define SERDESID_SERDESID2_DR_6G_4L_ALIGN 0 19204 #define SERDESID_SERDESID2_DR_6G_4L_BITS 1 19205 #define SERDESID_SERDESID2_DR_6G_4L_SHIFT 5 19206 19207 /* serdesID :: serdesID2 :: dr_5G_4L [04:04] */ 19208 #define SERDESID_SERDESID2_DR_5G_4L_MASK 0x0010 19209 #define SERDESID_SERDESID2_DR_5G_4L_ALIGN 0 19210 #define SERDESID_SERDESID2_DR_5G_4L_BITS 1 19211 #define SERDESID_SERDESID2_DR_5G_4L_SHIFT 4 19212 19213 /* serdesID :: serdesID2 :: dr_2p5G_SL [03:03] */ 19214 #define SERDESID_SERDESID2_DR_2P5G_SL_MASK 0x0008 19215 #define SERDESID_SERDESID2_DR_2P5G_SL_ALIGN 0 19216 #define SERDESID_SERDESID2_DR_2P5G_SL_BITS 1 19217 #define SERDESID_SERDESID2_DR_2P5G_SL_SHIFT 3 19218 19219 /* serdesID :: serdesID2 :: dr_1G_SL [02:02] */ 19220 #define SERDESID_SERDESID2_DR_1G_SL_MASK 0x0004 19221 #define SERDESID_SERDESID2_DR_1G_SL_ALIGN 0 19222 #define SERDESID_SERDESID2_DR_1G_SL_BITS 1 19223 #define SERDESID_SERDESID2_DR_1G_SL_SHIFT 2 19224 19225 /* serdesID :: serdesID2 :: dr_100M_SL [01:01] */ 19226 #define SERDESID_SERDESID2_DR_100M_SL_MASK 0x0002 19227 #define SERDESID_SERDESID2_DR_100M_SL_ALIGN 0 19228 #define SERDESID_SERDESID2_DR_100M_SL_BITS 1 19229 #define SERDESID_SERDESID2_DR_100M_SL_SHIFT 1 19230 19231 /* serdesID :: serdesID2 :: dr_10M_SL [00:00] */ 19232 #define SERDESID_SERDESID2_DR_10M_SL_MASK 0x0001 19233 #define SERDESID_SERDESID2_DR_10M_SL_ALIGN 0 19234 #define SERDESID_SERDESID2_DR_10M_SL_BITS 1 19235 #define SERDESID_SERDESID2_DR_10M_SL_SHIFT 0 19236 19237 19238 /**************************************************************************** 19239 * serdesID :: serdesID3 19240 */ 19241 /* serdesID :: serdesID3 :: reserved0 [15:05] */ 19242 #define SERDESID_SERDESID3_RESERVED0_MASK 0xffe0 19243 #define SERDESID_SERDESID3_RESERVED0_ALIGN 0 19244 #define SERDESID_SERDESID3_RESERVED0_BITS 11 19245 #define SERDESID_SERDESID3_RESERVED0_SHIFT 5 19246 19247 /* serdesID :: serdesID3 :: dr_6400_SL [04:04] */ 19248 #define SERDESID_SERDESID3_DR_6400_SL_MASK 0x0010 19249 #define SERDESID_SERDESID3_DR_6400_SL_ALIGN 0 19250 #define SERDESID_SERDESID3_DR_6400_SL_BITS 1 19251 #define SERDESID_SERDESID3_DR_6400_SL_SHIFT 4 19252 19253 /* serdesID :: serdesID3 :: dr_5000_SL [03:03] */ 19254 #define SERDESID_SERDESID3_DR_5000_SL_MASK 0x0008 19255 #define SERDESID_SERDESID3_DR_5000_SL_ALIGN 0 19256 #define SERDESID_SERDESID3_DR_5000_SL_BITS 1 19257 #define SERDESID_SERDESID3_DR_5000_SL_SHIFT 3 19258 19259 /* serdesID :: serdesID3 :: dr_4000_SL [02:02] */ 19260 #define SERDESID_SERDESID3_DR_4000_SL_MASK 0x0004 19261 #define SERDESID_SERDESID3_DR_4000_SL_ALIGN 0 19262 #define SERDESID_SERDESID3_DR_4000_SL_BITS 1 19263 #define SERDESID_SERDESID3_DR_4000_SL_SHIFT 2 19264 19265 /* serdesID :: serdesID3 :: dr_2000_SL [01:01] */ 19266 #define SERDESID_SERDESID3_DR_2000_SL_MASK 0x0002 19267 #define SERDESID_SERDESID3_DR_2000_SL_ALIGN 0 19268 #define SERDESID_SERDESID3_DR_2000_SL_BITS 1 19269 #define SERDESID_SERDESID3_DR_2000_SL_SHIFT 1 19270 19271 /* serdesID :: serdesID3 :: dr_100FX [00:00] */ 19272 #define SERDESID_SERDESID3_DR_100FX_MASK 0x0001 19273 #define SERDESID_SERDESID3_DR_100FX_ALIGN 0 19274 #define SERDESID_SERDESID3_DR_100FX_BITS 1 19275 #define SERDESID_SERDESID3_DR_100FX_SHIFT 0 19276 19277 19278 /**************************************************************************** 19279 * XGXS16G_USER_Over1G 19280 */ 19281 /**************************************************************************** 19282 * Over1G :: digctl_3_0 19283 */ 19284 /* Over1G :: digctl_3_0 :: an_lostLink_cnt [15:00] */ 19285 #define OVER1G_DIGCTL_3_0_AN_LOSTLINK_CNT_MASK 0xffff 19286 #define OVER1G_DIGCTL_3_0_AN_LOSTLINK_CNT_ALIGN 0 19287 #define OVER1G_DIGCTL_3_0_AN_LOSTLINK_CNT_BITS 16 19288 #define OVER1G_DIGCTL_3_0_AN_LOSTLINK_CNT_SHIFT 0 19289 19290 19291 /**************************************************************************** 19292 * Over1G :: digctl_3_1 19293 */ 19294 /* Over1G :: digctl_3_1 :: an_switch_cnt [15:00] */ 19295 #define OVER1G_DIGCTL_3_1_AN_SWITCH_CNT_MASK 0xffff 19296 #define OVER1G_DIGCTL_3_1_AN_SWITCH_CNT_ALIGN 0 19297 #define OVER1G_DIGCTL_3_1_AN_SWITCH_CNT_BITS 16 19298 #define OVER1G_DIGCTL_3_1_AN_SWITCH_CNT_SHIFT 0 19299 19300 19301 /**************************************************************************** 19302 * Over1G :: digctl_3_2 19303 */ 19304 /* Over1G :: digctl_3_2 :: an_link_cnt [15:00] */ 19305 #define OVER1G_DIGCTL_3_2_AN_LINK_CNT_MASK 0xffff 19306 #define OVER1G_DIGCTL_3_2_AN_LINK_CNT_ALIGN 0 19307 #define OVER1G_DIGCTL_3_2_AN_LINK_CNT_BITS 16 19308 #define OVER1G_DIGCTL_3_2_AN_LINK_CNT_SHIFT 0 19309 19310 19311 /**************************************************************************** 19312 * Over1G :: digctl_3_3 19313 */ 19314 /* Over1G :: digctl_3_3 :: an_switch_cnt2 [15:08] */ 19315 #define OVER1G_DIGCTL_3_3_AN_SWITCH_CNT2_MASK 0xff00 19316 #define OVER1G_DIGCTL_3_3_AN_SWITCH_CNT2_ALIGN 0 19317 #define OVER1G_DIGCTL_3_3_AN_SWITCH_CNT2_BITS 8 19318 #define OVER1G_DIGCTL_3_3_AN_SWITCH_CNT2_SHIFT 8 19319 19320 /* Over1G :: digctl_3_3 :: an_link_cnt2 [07:00] */ 19321 #define OVER1G_DIGCTL_3_3_AN_LINK_CNT2_MASK 0x00ff 19322 #define OVER1G_DIGCTL_3_3_AN_LINK_CNT2_ALIGN 0 19323 #define OVER1G_DIGCTL_3_3_AN_LINK_CNT2_BITS 8 19324 #define OVER1G_DIGCTL_3_3_AN_LINK_CNT2_SHIFT 0 19325 19326 19327 /**************************************************************************** 19328 * Over1G :: digctl_3_4 19329 */ 19330 /* Over1G :: digctl_3_4 :: mp_number [15:05] */ 19331 #define OVER1G_DIGCTL_3_4_MP_NUMBER_MASK 0xffe0 19332 #define OVER1G_DIGCTL_3_4_MP_NUMBER_ALIGN 0 19333 #define OVER1G_DIGCTL_3_4_MP_NUMBER_BITS 11 19334 #define OVER1G_DIGCTL_3_4_MP_NUMBER_SHIFT 5 19335 19336 /* Over1G :: digctl_3_4 :: no_fail_cnt [04:04] */ 19337 #define OVER1G_DIGCTL_3_4_NO_FAIL_CNT_MASK 0x0010 19338 #define OVER1G_DIGCTL_3_4_NO_FAIL_CNT_ALIGN 0 19339 #define OVER1G_DIGCTL_3_4_NO_FAIL_CNT_BITS 1 19340 #define OVER1G_DIGCTL_3_4_NO_FAIL_CNT_SHIFT 4 19341 19342 /* Over1G :: digctl_3_4 :: an_fail_cnt [03:00] */ 19343 #define OVER1G_DIGCTL_3_4_AN_FAIL_CNT_MASK 0x000f 19344 #define OVER1G_DIGCTL_3_4_AN_FAIL_CNT_ALIGN 0 19345 #define OVER1G_DIGCTL_3_4_AN_FAIL_CNT_BITS 4 19346 #define OVER1G_DIGCTL_3_4_AN_FAIL_CNT_SHIFT 0 19347 19348 19349 /**************************************************************************** 19350 * Over1G :: digctl_3_5 19351 */ 19352 /* Over1G :: digctl_3_5 :: an_ignoreLink_cnt [15:00] */ 19353 #define OVER1G_DIGCTL_3_5_AN_IGNORELINK_CNT_MASK 0xffff 19354 #define OVER1G_DIGCTL_3_5_AN_IGNORELINK_CNT_ALIGN 0 19355 #define OVER1G_DIGCTL_3_5_AN_IGNORELINK_CNT_BITS 16 19356 #define OVER1G_DIGCTL_3_5_AN_IGNORELINK_CNT_SHIFT 0 19357 19358 19359 /**************************************************************************** 19360 * Over1G :: digctl_3_6 19361 */ 19362 /* Over1G :: digctl_3_6 :: an_lostLink_cnt2 [15:08] */ 19363 #define OVER1G_DIGCTL_3_6_AN_LOSTLINK_CNT2_MASK 0xff00 19364 #define OVER1G_DIGCTL_3_6_AN_LOSTLINK_CNT2_ALIGN 0 19365 #define OVER1G_DIGCTL_3_6_AN_LOSTLINK_CNT2_BITS 8 19366 #define OVER1G_DIGCTL_3_6_AN_LOSTLINK_CNT2_SHIFT 8 19367 19368 /* Over1G :: digctl_3_6 :: an_ingoreLink_cnt2 [07:00] */ 19369 #define OVER1G_DIGCTL_3_6_AN_INGORELINK_CNT2_MASK 0x00ff 19370 #define OVER1G_DIGCTL_3_6_AN_INGORELINK_CNT2_ALIGN 0 19371 #define OVER1G_DIGCTL_3_6_AN_INGORELINK_CNT2_BITS 8 19372 #define OVER1G_DIGCTL_3_6_AN_INGORELINK_CNT2_SHIFT 0 19373 19374 19375 /**************************************************************************** 19376 * Over1G :: TPOUT_1 19377 */ 19378 /* Over1G :: TPOUT_1 :: tpout1 [15:00] */ 19379 #define OVER1G_TPOUT_1_TPOUT1_MASK 0xffff 19380 #define OVER1G_TPOUT_1_TPOUT1_ALIGN 0 19381 #define OVER1G_TPOUT_1_TPOUT1_BITS 16 19382 #define OVER1G_TPOUT_1_TPOUT1_SHIFT 0 19383 19384 19385 /**************************************************************************** 19386 * Over1G :: TPOUT_2 19387 */ 19388 /* Over1G :: TPOUT_2 :: tpout2 [15:00] */ 19389 #define OVER1G_TPOUT_2_TPOUT2_MASK 0xffff 19390 #define OVER1G_TPOUT_2_TPOUT2_ALIGN 0 19391 #define OVER1G_TPOUT_2_TPOUT2_BITS 16 19392 #define OVER1G_TPOUT_2_TPOUT2_SHIFT 0 19393 19394 19395 /**************************************************************************** 19396 * Over1G :: UP1 19397 */ 19398 /* Over1G :: UP1 :: reserved0 [15:11] */ 19399 #define OVER1G_UP1_RESERVED0_MASK 0xf800 19400 #define OVER1G_UP1_RESERVED0_ALIGN 0 19401 #define OVER1G_UP1_RESERVED0_BITS 5 19402 #define OVER1G_UP1_RESERVED0_SHIFT 11 19403 19404 /* Over1G :: UP1 :: dataRate_rsvd [10:10] */ 19405 #define OVER1G_UP1_DATARATE_RSVD_MASK 0x0400 19406 #define OVER1G_UP1_DATARATE_RSVD_ALIGN 0 19407 #define OVER1G_UP1_DATARATE_RSVD_BITS 1 19408 #define OVER1G_UP1_DATARATE_RSVD_SHIFT 10 19409 19410 /* Over1G :: UP1 :: dataRate_16GX4 [09:09] */ 19411 #define OVER1G_UP1_DATARATE_16GX4_MASK 0x0200 19412 #define OVER1G_UP1_DATARATE_16GX4_ALIGN 0 19413 #define OVER1G_UP1_DATARATE_16GX4_BITS 1 19414 #define OVER1G_UP1_DATARATE_16GX4_SHIFT 9 19415 19416 /* Over1G :: UP1 :: dataRate_15GX4 [08:08] */ 19417 #define OVER1G_UP1_DATARATE_15GX4_MASK 0x0100 19418 #define OVER1G_UP1_DATARATE_15GX4_ALIGN 0 19419 #define OVER1G_UP1_DATARATE_15GX4_BITS 1 19420 #define OVER1G_UP1_DATARATE_15GX4_SHIFT 8 19421 19422 /* Over1G :: UP1 :: dataRate_13GX4 [07:07] */ 19423 #define OVER1G_UP1_DATARATE_13GX4_MASK 0x0080 19424 #define OVER1G_UP1_DATARATE_13GX4_ALIGN 0 19425 #define OVER1G_UP1_DATARATE_13GX4_BITS 1 19426 #define OVER1G_UP1_DATARATE_13GX4_SHIFT 7 19427 19428 /* Over1G :: UP1 :: dataRate_12p5GX4 [06:06] */ 19429 #define OVER1G_UP1_DATARATE_12P5GX4_MASK 0x0040 19430 #define OVER1G_UP1_DATARATE_12P5GX4_ALIGN 0 19431 #define OVER1G_UP1_DATARATE_12P5GX4_BITS 1 19432 #define OVER1G_UP1_DATARATE_12P5GX4_SHIFT 6 19433 19434 /* Over1G :: UP1 :: dataRate_12GX4 [05:05] */ 19435 #define OVER1G_UP1_DATARATE_12GX4_MASK 0x0020 19436 #define OVER1G_UP1_DATARATE_12GX4_ALIGN 0 19437 #define OVER1G_UP1_DATARATE_12GX4_BITS 1 19438 #define OVER1G_UP1_DATARATE_12GX4_SHIFT 5 19439 19440 /* Over1G :: UP1 :: dataRate_10GCX4 [04:04] */ 19441 #define OVER1G_UP1_DATARATE_10GCX4_MASK 0x0010 19442 #define OVER1G_UP1_DATARATE_10GCX4_ALIGN 0 19443 #define OVER1G_UP1_DATARATE_10GCX4_BITS 1 19444 #define OVER1G_UP1_DATARATE_10GCX4_SHIFT 4 19445 19446 /* Over1G :: UP1 :: dataRate_10GX4 [03:03] */ 19447 #define OVER1G_UP1_DATARATE_10GX4_MASK 0x0008 19448 #define OVER1G_UP1_DATARATE_10GX4_ALIGN 0 19449 #define OVER1G_UP1_DATARATE_10GX4_BITS 1 19450 #define OVER1G_UP1_DATARATE_10GX4_SHIFT 3 19451 19452 /* Over1G :: UP1 :: dataRate_6GX4 [02:02] */ 19453 #define OVER1G_UP1_DATARATE_6GX4_MASK 0x0004 19454 #define OVER1G_UP1_DATARATE_6GX4_ALIGN 0 19455 #define OVER1G_UP1_DATARATE_6GX4_BITS 1 19456 #define OVER1G_UP1_DATARATE_6GX4_SHIFT 2 19457 19458 /* Over1G :: UP1 :: dataRate_5GX4 [01:01] */ 19459 #define OVER1G_UP1_DATARATE_5GX4_MASK 0x0002 19460 #define OVER1G_UP1_DATARATE_5GX4_ALIGN 0 19461 #define OVER1G_UP1_DATARATE_5GX4_BITS 1 19462 #define OVER1G_UP1_DATARATE_5GX4_SHIFT 1 19463 19464 /* Over1G :: UP1 :: dataRate_2p5GX1 [00:00] */ 19465 #define OVER1G_UP1_DATARATE_2P5GX1_MASK 0x0001 19466 #define OVER1G_UP1_DATARATE_2P5GX1_ALIGN 0 19467 #define OVER1G_UP1_DATARATE_2P5GX1_BITS 1 19468 #define OVER1G_UP1_DATARATE_2P5GX1_SHIFT 0 19469 19470 19471 /**************************************************************************** 19472 * Over1G :: UP2 19473 */ 19474 /* Over1G :: UP2 :: reserved0 [15:11] */ 19475 #define OVER1G_UP2_RESERVED0_MASK 0xf800 19476 #define OVER1G_UP2_RESERVED0_ALIGN 0 19477 #define OVER1G_UP2_RESERVED0_BITS 5 19478 #define OVER1G_UP2_RESERVED0_SHIFT 11 19479 19480 /* Over1G :: UP2 :: valid [10:10] */ 19481 #define OVER1G_UP2_VALID_MASK 0x0400 19482 #define OVER1G_UP2_VALID_ALIGN 0 19483 #define OVER1G_UP2_VALID_BITS 1 19484 #define OVER1G_UP2_VALID_SHIFT 10 19485 19486 /* Over1G :: UP2 :: preemphasis [09:06] */ 19487 #define OVER1G_UP2_PREEMPHASIS_MASK 0x03c0 19488 #define OVER1G_UP2_PREEMPHASIS_ALIGN 0 19489 #define OVER1G_UP2_PREEMPHASIS_BITS 4 19490 #define OVER1G_UP2_PREEMPHASIS_SHIFT 6 19491 19492 /* Over1G :: UP2 :: idriver [05:03] */ 19493 #define OVER1G_UP2_IDRIVER_MASK 0x0038 19494 #define OVER1G_UP2_IDRIVER_ALIGN 0 19495 #define OVER1G_UP2_IDRIVER_BITS 3 19496 #define OVER1G_UP2_IDRIVER_SHIFT 3 19497 19498 /* Over1G :: UP2 :: ipredriver [02:00] */ 19499 #define OVER1G_UP2_IPREDRIVER_MASK 0x0007 19500 #define OVER1G_UP2_IPREDRIVER_ALIGN 0 19501 #define OVER1G_UP2_IPREDRIVER_BITS 3 19502 #define OVER1G_UP2_IPREDRIVER_SHIFT 0 19503 19504 19505 /**************************************************************************** 19506 * Over1G :: UP3 19507 */ 19508 /* Over1G :: UP3 :: reserved0 [15:11] */ 19509 #define OVER1G_UP3_RESERVED0_MASK 0xf800 19510 #define OVER1G_UP3_RESERVED0_ALIGN 0 19511 #define OVER1G_UP3_RESERVED0_BITS 5 19512 #define OVER1G_UP3_RESERVED0_SHIFT 11 19513 19514 /* Over1G :: UP3 :: last [10:10] */ 19515 #define OVER1G_UP3_LAST_MASK 0x0400 19516 #define OVER1G_UP3_LAST_ALIGN 0 19517 #define OVER1G_UP3_LAST_BITS 1 19518 #define OVER1G_UP3_LAST_SHIFT 10 19519 19520 /* Over1G :: UP3 :: reserved1 [09:02] */ 19521 #define OVER1G_UP3_RESERVED1_MASK 0x03fc 19522 #define OVER1G_UP3_RESERVED1_ALIGN 0 19523 #define OVER1G_UP3_RESERVED1_BITS 8 19524 #define OVER1G_UP3_RESERVED1_SHIFT 2 19525 19526 /* Over1G :: UP3 :: scramble_8B10B [01:01] */ 19527 #define OVER1G_UP3_SCRAMBLE_8B10B_MASK 0x0002 19528 #define OVER1G_UP3_SCRAMBLE_8B10B_ALIGN 0 19529 #define OVER1G_UP3_SCRAMBLE_8B10B_BITS 1 19530 #define OVER1G_UP3_SCRAMBLE_8B10B_SHIFT 1 19531 19532 /* Over1G :: UP3 :: HiGig2 [00:00] */ 19533 #define OVER1G_UP3_HIGIG2_MASK 0x0001 19534 #define OVER1G_UP3_HIGIG2_ALIGN 0 19535 #define OVER1G_UP3_HIGIG2_BITS 1 19536 #define OVER1G_UP3_HIGIG2_SHIFT 0 19537 19538 19539 /**************************************************************************** 19540 * Over1G :: LP_UP1 19541 */ 19542 /* Over1G :: LP_UP1 :: reserved0 [15:11] */ 19543 #define OVER1G_LP_UP1_RESERVED0_MASK 0xf800 19544 #define OVER1G_LP_UP1_RESERVED0_ALIGN 0 19545 #define OVER1G_LP_UP1_RESERVED0_BITS 5 19546 #define OVER1G_LP_UP1_RESERVED0_SHIFT 11 19547 19548 /* Over1G :: LP_UP1 :: dataRate_rsvd [10:10] */ 19549 #define OVER1G_LP_UP1_DATARATE_RSVD_MASK 0x0400 19550 #define OVER1G_LP_UP1_DATARATE_RSVD_ALIGN 0 19551 #define OVER1G_LP_UP1_DATARATE_RSVD_BITS 1 19552 #define OVER1G_LP_UP1_DATARATE_RSVD_SHIFT 10 19553 19554 /* Over1G :: LP_UP1 :: dataRate_16GX4 [09:09] */ 19555 #define OVER1G_LP_UP1_DATARATE_16GX4_MASK 0x0200 19556 #define OVER1G_LP_UP1_DATARATE_16GX4_ALIGN 0 19557 #define OVER1G_LP_UP1_DATARATE_16GX4_BITS 1 19558 #define OVER1G_LP_UP1_DATARATE_16GX4_SHIFT 9 19559 19560 /* Over1G :: LP_UP1 :: dataRate_15GX4 [08:08] */ 19561 #define OVER1G_LP_UP1_DATARATE_15GX4_MASK 0x0100 19562 #define OVER1G_LP_UP1_DATARATE_15GX4_ALIGN 0 19563 #define OVER1G_LP_UP1_DATARATE_15GX4_BITS 1 19564 #define OVER1G_LP_UP1_DATARATE_15GX4_SHIFT 8 19565 19566 /* Over1G :: LP_UP1 :: dataRate_13GX4 [07:07] */ 19567 #define OVER1G_LP_UP1_DATARATE_13GX4_MASK 0x0080 19568 #define OVER1G_LP_UP1_DATARATE_13GX4_ALIGN 0 19569 #define OVER1G_LP_UP1_DATARATE_13GX4_BITS 1 19570 #define OVER1G_LP_UP1_DATARATE_13GX4_SHIFT 7 19571 19572 /* Over1G :: LP_UP1 :: dataRate_12p5GX4 [06:06] */ 19573 #define OVER1G_LP_UP1_DATARATE_12P5GX4_MASK 0x0040 19574 #define OVER1G_LP_UP1_DATARATE_12P5GX4_ALIGN 0 19575 #define OVER1G_LP_UP1_DATARATE_12P5GX4_BITS 1 19576 #define OVER1G_LP_UP1_DATARATE_12P5GX4_SHIFT 6 19577 19578 /* Over1G :: LP_UP1 :: dataRate_12GX4 [05:05] */ 19579 #define OVER1G_LP_UP1_DATARATE_12GX4_MASK 0x0020 19580 #define OVER1G_LP_UP1_DATARATE_12GX4_ALIGN 0 19581 #define OVER1G_LP_UP1_DATARATE_12GX4_BITS 1 19582 #define OVER1G_LP_UP1_DATARATE_12GX4_SHIFT 5 19583 19584 /* Over1G :: LP_UP1 :: dataRate_10GCX4 [04:04] */ 19585 #define OVER1G_LP_UP1_DATARATE_10GCX4_MASK 0x0010 19586 #define OVER1G_LP_UP1_DATARATE_10GCX4_ALIGN 0 19587 #define OVER1G_LP_UP1_DATARATE_10GCX4_BITS 1 19588 #define OVER1G_LP_UP1_DATARATE_10GCX4_SHIFT 4 19589 19590 /* Over1G :: LP_UP1 :: dataRate_10GX4 [03:03] */ 19591 #define OVER1G_LP_UP1_DATARATE_10GX4_MASK 0x0008 19592 #define OVER1G_LP_UP1_DATARATE_10GX4_ALIGN 0 19593 #define OVER1G_LP_UP1_DATARATE_10GX4_BITS 1 19594 #define OVER1G_LP_UP1_DATARATE_10GX4_SHIFT 3 19595 19596 /* Over1G :: LP_UP1 :: dataRate_6GX4 [02:02] */ 19597 #define OVER1G_LP_UP1_DATARATE_6GX4_MASK 0x0004 19598 #define OVER1G_LP_UP1_DATARATE_6GX4_ALIGN 0 19599 #define OVER1G_LP_UP1_DATARATE_6GX4_BITS 1 19600 #define OVER1G_LP_UP1_DATARATE_6GX4_SHIFT 2 19601 19602 /* Over1G :: LP_UP1 :: dataRate_5GX4 [01:01] */ 19603 #define OVER1G_LP_UP1_DATARATE_5GX4_MASK 0x0002 19604 #define OVER1G_LP_UP1_DATARATE_5GX4_ALIGN 0 19605 #define OVER1G_LP_UP1_DATARATE_5GX4_BITS 1 19606 #define OVER1G_LP_UP1_DATARATE_5GX4_SHIFT 1 19607 19608 /* Over1G :: LP_UP1 :: dataRate_2p5GX1 [00:00] */ 19609 #define OVER1G_LP_UP1_DATARATE_2P5GX1_MASK 0x0001 19610 #define OVER1G_LP_UP1_DATARATE_2P5GX1_ALIGN 0 19611 #define OVER1G_LP_UP1_DATARATE_2P5GX1_BITS 1 19612 #define OVER1G_LP_UP1_DATARATE_2P5GX1_SHIFT 0 19613 19614 19615 /**************************************************************************** 19616 * Over1G :: LP_UP2 19617 */ 19618 /* Over1G :: LP_UP2 :: reserved0 [15:11] */ 19619 #define OVER1G_LP_UP2_RESERVED0_MASK 0xf800 19620 #define OVER1G_LP_UP2_RESERVED0_ALIGN 0 19621 #define OVER1G_LP_UP2_RESERVED0_BITS 5 19622 #define OVER1G_LP_UP2_RESERVED0_SHIFT 11 19623 19624 /* Over1G :: LP_UP2 :: valid [10:10] */ 19625 #define OVER1G_LP_UP2_VALID_MASK 0x0400 19626 #define OVER1G_LP_UP2_VALID_ALIGN 0 19627 #define OVER1G_LP_UP2_VALID_BITS 1 19628 #define OVER1G_LP_UP2_VALID_SHIFT 10 19629 19630 /* Over1G :: LP_UP2 :: preemphasis [09:06] */ 19631 #define OVER1G_LP_UP2_PREEMPHASIS_MASK 0x03c0 19632 #define OVER1G_LP_UP2_PREEMPHASIS_ALIGN 0 19633 #define OVER1G_LP_UP2_PREEMPHASIS_BITS 4 19634 #define OVER1G_LP_UP2_PREEMPHASIS_SHIFT 6 19635 19636 /* Over1G :: LP_UP2 :: idriver [05:03] */ 19637 #define OVER1G_LP_UP2_IDRIVER_MASK 0x0038 19638 #define OVER1G_LP_UP2_IDRIVER_ALIGN 0 19639 #define OVER1G_LP_UP2_IDRIVER_BITS 3 19640 #define OVER1G_LP_UP2_IDRIVER_SHIFT 3 19641 19642 /* Over1G :: LP_UP2 :: ipredriver [02:00] */ 19643 #define OVER1G_LP_UP2_IPREDRIVER_MASK 0x0007 19644 #define OVER1G_LP_UP2_IPREDRIVER_ALIGN 0 19645 #define OVER1G_LP_UP2_IPREDRIVER_BITS 3 19646 #define OVER1G_LP_UP2_IPREDRIVER_SHIFT 0 19647 19648 19649 /**************************************************************************** 19650 * Over1G :: LP_UP3 19651 */ 19652 /* Over1G :: LP_UP3 :: reserved0 [15:11] */ 19653 #define OVER1G_LP_UP3_RESERVED0_MASK 0xf800 19654 #define OVER1G_LP_UP3_RESERVED0_ALIGN 0 19655 #define OVER1G_LP_UP3_RESERVED0_BITS 5 19656 #define OVER1G_LP_UP3_RESERVED0_SHIFT 11 19657 19658 /* Over1G :: LP_UP3 :: last [10:10] */ 19659 #define OVER1G_LP_UP3_LAST_MASK 0x0400 19660 #define OVER1G_LP_UP3_LAST_ALIGN 0 19661 #define OVER1G_LP_UP3_LAST_BITS 1 19662 #define OVER1G_LP_UP3_LAST_SHIFT 10 19663 19664 /* Over1G :: LP_UP3 :: reserved1 [09:02] */ 19665 #define OVER1G_LP_UP3_RESERVED1_MASK 0x03fc 19666 #define OVER1G_LP_UP3_RESERVED1_ALIGN 0 19667 #define OVER1G_LP_UP3_RESERVED1_BITS 8 19668 #define OVER1G_LP_UP3_RESERVED1_SHIFT 2 19669 19670 /* Over1G :: LP_UP3 :: scramble_8B10B [01:01] */ 19671 #define OVER1G_LP_UP3_SCRAMBLE_8B10B_MASK 0x0002 19672 #define OVER1G_LP_UP3_SCRAMBLE_8B10B_ALIGN 0 19673 #define OVER1G_LP_UP3_SCRAMBLE_8B10B_BITS 1 19674 #define OVER1G_LP_UP3_SCRAMBLE_8B10B_SHIFT 1 19675 19676 /* Over1G :: LP_UP3 :: HiGig2 [00:00] */ 19677 #define OVER1G_LP_UP3_HIGIG2_MASK 0x0001 19678 #define OVER1G_LP_UP3_HIGIG2_ALIGN 0 19679 #define OVER1G_LP_UP3_HIGIG2_BITS 1 19680 #define OVER1G_LP_UP3_HIGIG2_SHIFT 0 19681 19682 19683 /**************************************************************************** 19684 * XGXS16G_USER_RemotePhy 19685 */ 19686 /**************************************************************************** 19687 * RemotePhy :: MiscRxStatus 19688 */ 19689 /* union - case statusSelect0 [15:00] */ 19690 /* RemotePhy :: MiscRxStatus :: capture_NP_lh [15:15] */ 19691 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK 0x8000 19692 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN 0 19693 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS 1 19694 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT 15 19695 19696 /* RemotePhy :: MiscRxStatus :: teton_brk_link_lh [14:14] */ 19697 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000 19698 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0 19699 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1 19700 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14 19701 19702 /* RemotePhy :: MiscRxStatus :: UP3_lh [13:13] */ 19703 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK 0x2000 19704 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN 0 19705 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS 1 19706 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT 13 19707 19708 /* RemotePhy :: MiscRxStatus :: MP5_lh [12:12] */ 19709 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK 0x1000 19710 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN 0 19711 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS 1 19712 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT 12 19713 19714 /* RemotePhy :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */ 19715 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800 19716 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0 19717 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1 19718 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11 19719 19720 /* RemotePhy :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */ 19721 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400 19722 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0 19723 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1 19724 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10 19725 19726 /* RemotePhy :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */ 19727 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200 19728 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0 19729 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1 19730 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9 19731 19732 /* RemotePhy :: MiscRxStatus :: invalidSeq_lh [08:08] */ 19733 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK 0x0100 19734 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN 0 19735 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS 1 19736 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT 8 19737 19738 /* RemotePhy :: MiscRxStatus :: nullMP_lh [07:07] */ 19739 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK 0x0080 19740 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN 0 19741 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS 1 19742 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT 7 19743 19744 /* RemotePhy :: MiscRxStatus :: remotePhyMP_lh [06:06] */ 19745 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK 0x0040 19746 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN 0 19747 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS 1 19748 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT 6 19749 19750 /* RemotePhy :: MiscRxStatus :: nonMatchingMP_lh [05:05] */ 19751 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK 0x0020 19752 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0 19753 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS 1 19754 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5 19755 19756 /* RemotePhy :: MiscRxStatus :: over1gMP_lh [04:04] */ 19757 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK 0x0010 19758 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN 0 19759 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS 1 19760 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT 4 19761 19762 /* RemotePhy :: MiscRxStatus :: rx_config_is_0_lh [03:03] */ 19763 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008 19764 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0 19765 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1 19766 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3 19767 19768 /* RemotePhy :: MiscRxStatus :: np_toggle_err_lh [02:02] */ 19769 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK 0x0004 19770 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0 19771 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS 1 19772 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2 19773 19774 /* RemotePhy :: MiscRxStatus :: mr_np_lh [01:01] */ 19775 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK 0x0002 19776 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN 0 19777 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS 1 19778 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT 1 19779 19780 /* RemotePhy :: MiscRxStatus :: mr_bp_lh [00:00] */ 19781 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK 0x0001 19782 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN 0 19783 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS 1 19784 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT 0 19785 19786 19787 /* union - case statusSelect1 [15:00] */ 19788 /* RemotePhy :: MiscRxStatus :: reserved0 [15:04] */ 19789 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK 0xfff0 19790 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN 0 19791 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS 12 19792 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT 4 19793 19794 /* RemotePhy :: MiscRxStatus :: np_count [03:00] */ 19795 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK 0x000f 19796 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN 0 19797 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS 4 19798 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT 0 19799 19800 19801 /* union - case statusSelect2 [15:00] */ 19802 /* RemotePhy :: MiscRxStatus :: reserved0 [15:06] */ 19803 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK 0xffc0 19804 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN 0 19805 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS 10 19806 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT 6 19807 19808 /* RemotePhy :: MiscRxStatus :: remote_phy_enable [05:05] */ 19809 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020 19810 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0 19811 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1 19812 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5 19813 19814 /* RemotePhy :: MiscRxStatus :: det_teton_mode [04:04] */ 19815 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK 0x0010 19816 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN 0 19817 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS 1 19818 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT 4 19819 19820 /* RemotePhy :: MiscRxStatus :: cu_linkdown [03:03] */ 19821 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK 0x0008 19822 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN 0 19823 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS 1 19824 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT 3 19825 19826 /* RemotePhy :: MiscRxStatus :: cu_resolution_error [02:02] */ 19827 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004 19828 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0 19829 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1 19830 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2 19831 19832 /* RemotePhy :: MiscRxStatus :: remotePhy_autosel [01:01] */ 19833 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002 19834 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0 19835 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1 19836 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1 19837 19838 /* RemotePhy :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */ 19839 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001 19840 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0 19841 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1 19842 #define REMOTEPHY_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0 19843 19844 19845 19846 /**************************************************************************** 19847 * RemotePhy :: lp_basePage 19848 */ 19849 /* RemotePhy :: lp_basePage :: lp_basePage [15:00] */ 19850 #define REMOTEPHY_LP_BASEPAGE_LP_BASEPAGE_MASK 0xffff 19851 #define REMOTEPHY_LP_BASEPAGE_LP_BASEPAGE_ALIGN 0 19852 #define REMOTEPHY_LP_BASEPAGE_LP_BASEPAGE_BITS 16 19853 #define REMOTEPHY_LP_BASEPAGE_LP_BASEPAGE_SHIFT 0 19854 19855 19856 /**************************************************************************** 19857 * RemotePhy :: lp_nextPage_0 19858 */ 19859 /* RemotePhy :: lp_nextPage_0 :: lp_nextPage_0 [15:00] */ 19860 #define REMOTEPHY_LP_NEXTPAGE_0_LP_NEXTPAGE_0_MASK 0xffff 19861 #define REMOTEPHY_LP_NEXTPAGE_0_LP_NEXTPAGE_0_ALIGN 0 19862 #define REMOTEPHY_LP_NEXTPAGE_0_LP_NEXTPAGE_0_BITS 16 19863 #define REMOTEPHY_LP_NEXTPAGE_0_LP_NEXTPAGE_0_SHIFT 0 19864 19865 19866 /**************************************************************************** 19867 * RemotePhy :: lp_nextPage_1 19868 */ 19869 /* RemotePhy :: lp_nextPage_1 :: lp_nextPage_1 [15:00] */ 19870 #define REMOTEPHY_LP_NEXTPAGE_1_LP_NEXTPAGE_1_MASK 0xffff 19871 #define REMOTEPHY_LP_NEXTPAGE_1_LP_NEXTPAGE_1_ALIGN 0 19872 #define REMOTEPHY_LP_NEXTPAGE_1_LP_NEXTPAGE_1_BITS 16 19873 #define REMOTEPHY_LP_NEXTPAGE_1_LP_NEXTPAGE_1_SHIFT 0 19874 19875 19876 /**************************************************************************** 19877 * RemotePhy :: lp_nextPage_2 19878 */ 19879 /* RemotePhy :: lp_nextPage_2 :: lp_nextPage_2 [15:00] */ 19880 #define REMOTEPHY_LP_NEXTPAGE_2_LP_NEXTPAGE_2_MASK 0xffff 19881 #define REMOTEPHY_LP_NEXTPAGE_2_LP_NEXTPAGE_2_ALIGN 0 19882 #define REMOTEPHY_LP_NEXTPAGE_2_LP_NEXTPAGE_2_BITS 16 19883 #define REMOTEPHY_LP_NEXTPAGE_2_LP_NEXTPAGE_2_SHIFT 0 19884 19885 19886 /**************************************************************************** 19887 * RemotePhy :: lp_nextPage_3 19888 */ 19889 /* RemotePhy :: lp_nextPage_3 :: lp_nextPage_3 [15:00] */ 19890 #define REMOTEPHY_LP_NEXTPAGE_3_LP_NEXTPAGE_3_MASK 0xffff 19891 #define REMOTEPHY_LP_NEXTPAGE_3_LP_NEXTPAGE_3_ALIGN 0 19892 #define REMOTEPHY_LP_NEXTPAGE_3_LP_NEXTPAGE_3_BITS 16 19893 #define REMOTEPHY_LP_NEXTPAGE_3_LP_NEXTPAGE_3_SHIFT 0 19894 19895 19896 /**************************************************************************** 19897 * RemotePhy :: lp_nextPage_4 19898 */ 19899 /* RemotePhy :: lp_nextPage_4 :: lp_nextPage_4 [15:00] */ 19900 #define REMOTEPHY_LP_NEXTPAGE_4_LP_NEXTPAGE_4_MASK 0xffff 19901 #define REMOTEPHY_LP_NEXTPAGE_4_LP_NEXTPAGE_4_ALIGN 0 19902 #define REMOTEPHY_LP_NEXTPAGE_4_LP_NEXTPAGE_4_BITS 16 19903 #define REMOTEPHY_LP_NEXTPAGE_4_LP_NEXTPAGE_4_SHIFT 0 19904 19905 19906 /**************************************************************************** 19907 * RemotePhy :: rp_nextPage_0 19908 */ 19909 /* RemotePhy :: rp_nextPage_0 :: reserved0 [15:15] */ 19910 #define REMOTEPHY_RP_NEXTPAGE_0_RESERVED0_MASK 0x8000 19911 #define REMOTEPHY_RP_NEXTPAGE_0_RESERVED0_ALIGN 0 19912 #define REMOTEPHY_RP_NEXTPAGE_0_RESERVED0_BITS 1 19913 #define REMOTEPHY_RP_NEXTPAGE_0_RESERVED0_SHIFT 15 19914 19915 /* RemotePhy :: rp_nextPage_0 :: extra_page_disable [14:14] */ 19916 #define REMOTEPHY_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_MASK 0x4000 19917 #define REMOTEPHY_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_ALIGN 0 19918 #define REMOTEPHY_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_BITS 1 19919 #define REMOTEPHY_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_SHIFT 14 19920 19921 /* RemotePhy :: rp_nextPage_0 :: null_page_enable [13:13] */ 19922 #define REMOTEPHY_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_MASK 0x2000 19923 #define REMOTEPHY_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_ALIGN 0 19924 #define REMOTEPHY_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_BITS 1 19925 #define REMOTEPHY_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_SHIFT 13 19926 19927 /* RemotePhy :: rp_nextPage_0 :: over_1g_disable [12:12] */ 19928 #define REMOTEPHY_RP_NEXTPAGE_0_OVER_1G_DISABLE_MASK 0x1000 19929 #define REMOTEPHY_RP_NEXTPAGE_0_OVER_1G_DISABLE_ALIGN 0 19930 #define REMOTEPHY_RP_NEXTPAGE_0_OVER_1G_DISABLE_BITS 1 19931 #define REMOTEPHY_RP_NEXTPAGE_0_OVER_1G_DISABLE_SHIFT 12 19932 19933 /* RemotePhy :: rp_nextPage_0 :: remote_phy_enable [11:11] */ 19934 #define REMOTEPHY_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_MASK 0x0800 19935 #define REMOTEPHY_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_ALIGN 0 19936 #define REMOTEPHY_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_BITS 1 19937 #define REMOTEPHY_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_SHIFT 11 19938 19939 /* RemotePhy :: rp_nextPage_0 :: rp_nextPage_0 [10:00] */ 19940 #define REMOTEPHY_RP_NEXTPAGE_0_RP_NEXTPAGE_0_MASK 0x07ff 19941 #define REMOTEPHY_RP_NEXTPAGE_0_RP_NEXTPAGE_0_ALIGN 0 19942 #define REMOTEPHY_RP_NEXTPAGE_0_RP_NEXTPAGE_0_BITS 11 19943 #define REMOTEPHY_RP_NEXTPAGE_0_RP_NEXTPAGE_0_SHIFT 0 19944 19945 19946 /**************************************************************************** 19947 * RemotePhy :: rp_nextPage_1 19948 */ 19949 /* RemotePhy :: rp_nextPage_1 :: reserved0 [15:15] */ 19950 #define REMOTEPHY_RP_NEXTPAGE_1_RESERVED0_MASK 0x8000 19951 #define REMOTEPHY_RP_NEXTPAGE_1_RESERVED0_ALIGN 0 19952 #define REMOTEPHY_RP_NEXTPAGE_1_RESERVED0_BITS 1 19953 #define REMOTEPHY_RP_NEXTPAGE_1_RESERVED0_SHIFT 15 19954 19955 /* RemotePhy :: rp_nextPage_1 :: remotePhy_linkDown_rstrt_disable [14:14] */ 19956 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_MASK 0x4000 19957 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_ALIGN 0 19958 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_BITS 1 19959 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_SHIFT 14 19960 19961 /* RemotePhy :: rp_nextPage_1 :: remotePhy_rsltn_err_rstrt_disable [13:13] */ 19962 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_MASK 0x2000 19963 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_ALIGN 0 19964 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_BITS 1 19965 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_SHIFT 13 19966 19967 /* RemotePhy :: rp_nextPage_1 :: remotePhy_resolution_disable [12:12] */ 19968 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_MASK 0x1000 19969 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_ALIGN 0 19970 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_BITS 1 19971 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_SHIFT 12 19972 19973 /* RemotePhy :: rp_nextPage_1 :: remotePhy_decode_enable [11:11] */ 19974 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_MASK 0x0800 19975 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_ALIGN 0 19976 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_BITS 1 19977 #define REMOTEPHY_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_SHIFT 11 19978 19979 /* RemotePhy :: rp_nextPage_1 :: rp_nextPage_1 [10:00] */ 19980 #define REMOTEPHY_RP_NEXTPAGE_1_RP_NEXTPAGE_1_MASK 0x07ff 19981 #define REMOTEPHY_RP_NEXTPAGE_1_RP_NEXTPAGE_1_ALIGN 0 19982 #define REMOTEPHY_RP_NEXTPAGE_1_RP_NEXTPAGE_1_BITS 11 19983 #define REMOTEPHY_RP_NEXTPAGE_1_RP_NEXTPAGE_1_SHIFT 0 19984 19985 19986 /**************************************************************************** 19987 * RemotePhy :: rp_nextPage_2 19988 */ 19989 /* RemotePhy :: rp_nextPage_2 :: reserved0 [15:12] */ 19990 #define REMOTEPHY_RP_NEXTPAGE_2_RESERVED0_MASK 0xf000 19991 #define REMOTEPHY_RP_NEXTPAGE_2_RESERVED0_ALIGN 0 19992 #define REMOTEPHY_RP_NEXTPAGE_2_RESERVED0_BITS 4 19993 #define REMOTEPHY_RP_NEXTPAGE_2_RESERVED0_SHIFT 12 19994 19995 /* RemotePhy :: rp_nextPage_2 :: remPhy_NP_clr_disable [11:11] */ 19996 #define REMOTEPHY_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_MASK 0x0800 19997 #define REMOTEPHY_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_ALIGN 0 19998 #define REMOTEPHY_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_BITS 1 19999 #define REMOTEPHY_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_SHIFT 11 20000 20001 /* RemotePhy :: rp_nextPage_2 :: rp_nextPage_2 [10:00] */ 20002 #define REMOTEPHY_RP_NEXTPAGE_2_RP_NEXTPAGE_2_MASK 0x07ff 20003 #define REMOTEPHY_RP_NEXTPAGE_2_RP_NEXTPAGE_2_ALIGN 0 20004 #define REMOTEPHY_RP_NEXTPAGE_2_RP_NEXTPAGE_2_BITS 11 20005 #define REMOTEPHY_RP_NEXTPAGE_2_RP_NEXTPAGE_2_SHIFT 0 20006 20007 20008 /**************************************************************************** 20009 * RemotePhy :: rp_nextPage_3 20010 */ 20011 /* RemotePhy :: rp_nextPage_3 :: reserved0 [15:11] */ 20012 #define REMOTEPHY_RP_NEXTPAGE_3_RESERVED0_MASK 0xf800 20013 #define REMOTEPHY_RP_NEXTPAGE_3_RESERVED0_ALIGN 0 20014 #define REMOTEPHY_RP_NEXTPAGE_3_RESERVED0_BITS 5 20015 #define REMOTEPHY_RP_NEXTPAGE_3_RESERVED0_SHIFT 11 20016 20017 /* RemotePhy :: rp_nextPage_3 :: rp_nextPage_3 [10:00] */ 20018 #define REMOTEPHY_RP_NEXTPAGE_3_RP_NEXTPAGE_3_MASK 0x07ff 20019 #define REMOTEPHY_RP_NEXTPAGE_3_RP_NEXTPAGE_3_ALIGN 0 20020 #define REMOTEPHY_RP_NEXTPAGE_3_RP_NEXTPAGE_3_BITS 11 20021 #define REMOTEPHY_RP_NEXTPAGE_3_RP_NEXTPAGE_3_SHIFT 0 20022 20023 20024 /**************************************************************************** 20025 * RemotePhy :: rp_nextPage_4 20026 */ 20027 /* RemotePhy :: rp_nextPage_4 :: reserved0 [15:11] */ 20028 #define REMOTEPHY_RP_NEXTPAGE_4_RESERVED0_MASK 0xf800 20029 #define REMOTEPHY_RP_NEXTPAGE_4_RESERVED0_ALIGN 0 20030 #define REMOTEPHY_RP_NEXTPAGE_4_RESERVED0_BITS 5 20031 #define REMOTEPHY_RP_NEXTPAGE_4_RESERVED0_SHIFT 11 20032 20033 /* RemotePhy :: rp_nextPage_4 :: rp_nextPage_4 [10:00] */ 20034 #define REMOTEPHY_RP_NEXTPAGE_4_RP_NEXTPAGE_4_MASK 0x07ff 20035 #define REMOTEPHY_RP_NEXTPAGE_4_RP_NEXTPAGE_4_ALIGN 0 20036 #define REMOTEPHY_RP_NEXTPAGE_4_RP_NEXTPAGE_4_BITS 11 20037 #define REMOTEPHY_RP_NEXTPAGE_4_RP_NEXTPAGE_4_SHIFT 0 20038 20039 20040 /**************************************************************************** 20041 * RemotePhy :: Misc3 20042 */ 20043 /* RemotePhy :: Misc3 :: reserved0 [15:02] */ 20044 #define REMOTEPHY_MISC3_RESERVED0_MASK 0xfffc 20045 #define REMOTEPHY_MISC3_RESERVED0_ALIGN 0 20046 #define REMOTEPHY_MISC3_RESERVED0_BITS 14 20047 #define REMOTEPHY_MISC3_RESERVED0_SHIFT 2 20048 20049 /* RemotePhy :: Misc3 :: rxSigdetPwrdn_override_val [01:01] */ 20050 #define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_MASK 0x0002 20051 #define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_ALIGN 0 20052 #define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_BITS 1 20053 #define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_SHIFT 1 20054 20055 /* RemotePhy :: Misc3 :: rxSigdetPwrdn_override [00:00] */ 20056 #define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_MASK 0x0001 20057 #define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_ALIGN 0 20058 #define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_BITS 1 20059 #define REMOTEPHY_MISC3_RXSIGDETPWRDN_OVERRIDE_SHIFT 0 20060 20061 20062 /**************************************************************************** 20063 * XGXS16G_USER_BAM_NextPage 20064 */ 20065 /**************************************************************************** 20066 * BAM_NextPage :: mp5_NextPageCtrl 20067 */ 20068 /* BAM_NextPage :: mp5_NextPageCtrl :: reserved0 [15:04] */ 20069 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_RESERVED0_MASK 0xfff0 20070 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_RESERVED0_ALIGN 0 20071 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_RESERVED0_BITS 12 20072 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_RESERVED0_SHIFT 4 20073 20074 /* BAM_NextPage :: mp5_NextPageCtrl :: np_sw_overRide_en [03:03] */ 20075 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_MASK 0x0008 20076 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_ALIGN 0 20077 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_BITS 1 20078 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_SHIFT 3 20079 20080 /* BAM_NextPage :: mp5_NextPageCtrl :: teton_mode_up3_en [02:02] */ 20081 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_MASK 0x0004 20082 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_ALIGN 0 20083 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_BITS 1 20084 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_SHIFT 2 20085 20086 /* BAM_NextPage :: mp5_NextPageCtrl :: teton_mode [01:01] */ 20087 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_MASK 0x0002 20088 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_ALIGN 0 20089 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_BITS 1 20090 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_TETON_MODE_SHIFT 1 20091 20092 /* BAM_NextPage :: mp5_NextPageCtrl :: bam_mode [00:00] */ 20093 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_BAM_MODE_MASK 0x0001 20094 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_BAM_MODE_ALIGN 0 20095 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_BAM_MODE_BITS 1 20096 #define BAM_NEXTPAGE_MP5_NEXTPAGECTRL_BAM_MODE_SHIFT 0 20097 20098 20099 /**************************************************************************** 20100 * BAM_NextPage :: link_timer_offset1 20101 */ 20102 /* BAM_NextPage :: link_timer_offset1 :: sgmii_offset [15:08] */ 20103 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_SGMII_OFFSET_MASK 0xff00 20104 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_SGMII_OFFSET_ALIGN 0 20105 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_SGMII_OFFSET_BITS 8 20106 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_SGMII_OFFSET_SHIFT 8 20107 20108 /* BAM_NextPage :: link_timer_offset1 :: max_offset [07:00] */ 20109 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_MAX_OFFSET_MASK 0x00ff 20110 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_MAX_OFFSET_ALIGN 0 20111 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_MAX_OFFSET_BITS 8 20112 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET1_MAX_OFFSET_SHIFT 0 20113 20114 20115 /**************************************************************************** 20116 * BAM_NextPage :: link_timer_offset2 20117 */ 20118 /* BAM_NextPage :: link_timer_offset2 :: link_up_offset [15:08] */ 20119 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_MASK 0xff00 20120 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_ALIGN 0 20121 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_BITS 8 20122 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_SHIFT 8 20123 20124 /* BAM_NextPage :: link_timer_offset2 :: link_down_offset [07:00] */ 20125 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_MASK 0x00ff 20126 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_ALIGN 0 20127 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_BITS 8 20128 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_SHIFT 0 20129 20130 20131 /**************************************************************************** 20132 * BAM_NextPage :: link_timer_offset3 20133 */ 20134 /* BAM_NextPage :: link_timer_offset3 :: break_link_offset [15:08] */ 20135 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_MASK 0xff00 20136 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_ALIGN 0 20137 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_BITS 8 20138 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_SHIFT 8 20139 20140 /* BAM_NextPage :: link_timer_offset3 :: np_link_offset [07:00] */ 20141 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_MASK 0x00ff 20142 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_ALIGN 0 20143 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_BITS 8 20144 #define BAM_NEXTPAGE_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_SHIFT 0 20145 20146 20147 /**************************************************************************** 20148 * BAM_NextPage :: oui_msb_field 20149 */ 20150 /* BAM_NextPage :: oui_msb_field :: reserved0 [15:11] */ 20151 #define BAM_NEXTPAGE_OUI_MSB_FIELD_RESERVED0_MASK 0xf800 20152 #define BAM_NEXTPAGE_OUI_MSB_FIELD_RESERVED0_ALIGN 0 20153 #define BAM_NEXTPAGE_OUI_MSB_FIELD_RESERVED0_BITS 5 20154 #define BAM_NEXTPAGE_OUI_MSB_FIELD_RESERVED0_SHIFT 11 20155 20156 /* BAM_NextPage :: oui_msb_field :: oui_msb_field [10:00] */ 20157 #define BAM_NEXTPAGE_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK 0x07ff 20158 #define BAM_NEXTPAGE_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN 0 20159 #define BAM_NEXTPAGE_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS 11 20160 #define BAM_NEXTPAGE_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT 0 20161 20162 20163 /**************************************************************************** 20164 * BAM_NextPage :: oui_lsb_field 20165 */ 20166 /* BAM_NextPage :: oui_lsb_field :: reserved0 [15:11] */ 20167 #define BAM_NEXTPAGE_OUI_LSB_FIELD_RESERVED0_MASK 0xf800 20168 #define BAM_NEXTPAGE_OUI_LSB_FIELD_RESERVED0_ALIGN 0 20169 #define BAM_NEXTPAGE_OUI_LSB_FIELD_RESERVED0_BITS 5 20170 #define BAM_NEXTPAGE_OUI_LSB_FIELD_RESERVED0_SHIFT 11 20171 20172 /* BAM_NextPage :: oui_lsb_field :: oui_lsb_field [10:00] */ 20173 #define BAM_NEXTPAGE_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK 0x07ff 20174 #define BAM_NEXTPAGE_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN 0 20175 #define BAM_NEXTPAGE_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS 11 20176 #define BAM_NEXTPAGE_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT 0 20177 20178 20179 /**************************************************************************** 20180 * BAM_NextPage :: bam_field 20181 */ 20182 /* BAM_NextPage :: bam_field :: reserved0 [15:11] */ 20183 #define BAM_NEXTPAGE_BAM_FIELD_RESERVED0_MASK 0xf800 20184 #define BAM_NEXTPAGE_BAM_FIELD_RESERVED0_ALIGN 0 20185 #define BAM_NEXTPAGE_BAM_FIELD_RESERVED0_BITS 5 20186 #define BAM_NEXTPAGE_BAM_FIELD_RESERVED0_SHIFT 11 20187 20188 /* BAM_NextPage :: bam_field :: oui_1_0 [10:09] */ 20189 #define BAM_NEXTPAGE_BAM_FIELD_OUI_1_0_MASK 0x0600 20190 #define BAM_NEXTPAGE_BAM_FIELD_OUI_1_0_ALIGN 0 20191 #define BAM_NEXTPAGE_BAM_FIELD_OUI_1_0_BITS 2 20192 #define BAM_NEXTPAGE_BAM_FIELD_OUI_1_0_SHIFT 9 20193 20194 /* BAM_NextPage :: bam_field :: bam_field [08:00] */ 20195 #define BAM_NEXTPAGE_BAM_FIELD_BAM_FIELD_MASK 0x01ff 20196 #define BAM_NEXTPAGE_BAM_FIELD_BAM_FIELD_ALIGN 0 20197 #define BAM_NEXTPAGE_BAM_FIELD_BAM_FIELD_BITS 9 20198 #define BAM_NEXTPAGE_BAM_FIELD_BAM_FIELD_SHIFT 0 20199 20200 20201 /**************************************************************************** 20202 * BAM_NextPage :: ud_field 20203 */ 20204 /* BAM_NextPage :: ud_field :: reserved0 [15:11] */ 20205 #define BAM_NEXTPAGE_UD_FIELD_RESERVED0_MASK 0xf800 20206 #define BAM_NEXTPAGE_UD_FIELD_RESERVED0_ALIGN 0 20207 #define BAM_NEXTPAGE_UD_FIELD_RESERVED0_BITS 5 20208 #define BAM_NEXTPAGE_UD_FIELD_RESERVED0_SHIFT 11 20209 20210 /* BAM_NextPage :: ud_field :: ud_reserved [10:06] */ 20211 #define BAM_NEXTPAGE_UD_FIELD_UD_RESERVED_MASK 0x07c0 20212 #define BAM_NEXTPAGE_UD_FIELD_UD_RESERVED_ALIGN 0 20213 #define BAM_NEXTPAGE_UD_FIELD_UD_RESERVED_BITS 5 20214 #define BAM_NEXTPAGE_UD_FIELD_UD_RESERVED_SHIFT 6 20215 20216 /* BAM_NextPage :: ud_field :: remote_BN_page [05:05] */ 20217 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_BN_PAGE_MASK 0x0020 20218 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_BN_PAGE_ALIGN 0 20219 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_BN_PAGE_BITS 1 20220 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_BN_PAGE_SHIFT 5 20221 20222 /* BAM_NextPage :: ud_field :: inband_MDIO [04:04] */ 20223 #define BAM_NEXTPAGE_UD_FIELD_INBAND_MDIO_MASK 0x0010 20224 #define BAM_NEXTPAGE_UD_FIELD_INBAND_MDIO_ALIGN 0 20225 #define BAM_NEXTPAGE_UD_FIELD_INBAND_MDIO_BITS 1 20226 #define BAM_NEXTPAGE_UD_FIELD_INBAND_MDIO_SHIFT 4 20227 20228 /* BAM_NextPage :: ud_field :: autoneg_MDIO [03:03] */ 20229 #define BAM_NEXTPAGE_UD_FIELD_AUTONEG_MDIO_MASK 0x0008 20230 #define BAM_NEXTPAGE_UD_FIELD_AUTONEG_MDIO_ALIGN 0 20231 #define BAM_NEXTPAGE_UD_FIELD_AUTONEG_MDIO_BITS 1 20232 #define BAM_NEXTPAGE_UD_FIELD_AUTONEG_MDIO_SHIFT 3 20233 20234 /* BAM_NextPage :: ud_field :: remote_serdes_phy [02:02] */ 20235 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_SERDES_PHY_MASK 0x0004 20236 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_SERDES_PHY_ALIGN 0 20237 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_SERDES_PHY_BITS 1 20238 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_SERDES_PHY_SHIFT 2 20239 20240 /* BAM_NextPage :: ud_field :: remote_cu_phy [01:01] */ 20241 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_CU_PHY_MASK 0x0002 20242 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_CU_PHY_ALIGN 0 20243 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_CU_PHY_BITS 1 20244 #define BAM_NEXTPAGE_UD_FIELD_REMOTE_CU_PHY_SHIFT 1 20245 20246 /* BAM_NextPage :: ud_field :: over1g [00:00] */ 20247 #define BAM_NEXTPAGE_UD_FIELD_OVER1G_MASK 0x0001 20248 #define BAM_NEXTPAGE_UD_FIELD_OVER1G_ALIGN 0 20249 #define BAM_NEXTPAGE_UD_FIELD_OVER1G_BITS 1 20250 #define BAM_NEXTPAGE_UD_FIELD_OVER1G_SHIFT 0 20251 20252 20253 /**************************************************************************** 20254 * BAM_NextPage :: lp_oui_msb_field 20255 */ 20256 /* BAM_NextPage :: lp_oui_msb_field :: reserved0 [15:11] */ 20257 #define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_RESERVED0_MASK 0xf800 20258 #define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_RESERVED0_ALIGN 0 20259 #define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_RESERVED0_BITS 5 20260 #define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_RESERVED0_SHIFT 11 20261 20262 /* BAM_NextPage :: lp_oui_msb_field :: oui_msb_field [10:00] */ 20263 #define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK 0x07ff 20264 #define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN 0 20265 #define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS 11 20266 #define BAM_NEXTPAGE_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT 0 20267 20268 20269 /**************************************************************************** 20270 * BAM_NextPage :: lp_oui_lsb_field 20271 */ 20272 /* BAM_NextPage :: lp_oui_lsb_field :: reserved0 [15:11] */ 20273 #define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_RESERVED0_MASK 0xf800 20274 #define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_RESERVED0_ALIGN 0 20275 #define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_RESERVED0_BITS 5 20276 #define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_RESERVED0_SHIFT 11 20277 20278 /* BAM_NextPage :: lp_oui_lsb_field :: oui_lsb_field [10:00] */ 20279 #define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK 0x07ff 20280 #define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN 0 20281 #define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS 11 20282 #define BAM_NEXTPAGE_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT 0 20283 20284 20285 /**************************************************************************** 20286 * BAM_NextPage :: lp_bam_field 20287 */ 20288 /* BAM_NextPage :: lp_bam_field :: reserved0 [15:11] */ 20289 #define BAM_NEXTPAGE_LP_BAM_FIELD_RESERVED0_MASK 0xf800 20290 #define BAM_NEXTPAGE_LP_BAM_FIELD_RESERVED0_ALIGN 0 20291 #define BAM_NEXTPAGE_LP_BAM_FIELD_RESERVED0_BITS 5 20292 #define BAM_NEXTPAGE_LP_BAM_FIELD_RESERVED0_SHIFT 11 20293 20294 /* BAM_NextPage :: lp_bam_field :: oui_1_0 [10:09] */ 20295 #define BAM_NEXTPAGE_LP_BAM_FIELD_OUI_1_0_MASK 0x0600 20296 #define BAM_NEXTPAGE_LP_BAM_FIELD_OUI_1_0_ALIGN 0 20297 #define BAM_NEXTPAGE_LP_BAM_FIELD_OUI_1_0_BITS 2 20298 #define BAM_NEXTPAGE_LP_BAM_FIELD_OUI_1_0_SHIFT 9 20299 20300 /* BAM_NextPage :: lp_bam_field :: bam_field [08:00] */ 20301 #define BAM_NEXTPAGE_LP_BAM_FIELD_BAM_FIELD_MASK 0x01ff 20302 #define BAM_NEXTPAGE_LP_BAM_FIELD_BAM_FIELD_ALIGN 0 20303 #define BAM_NEXTPAGE_LP_BAM_FIELD_BAM_FIELD_BITS 9 20304 #define BAM_NEXTPAGE_LP_BAM_FIELD_BAM_FIELD_SHIFT 0 20305 20306 20307 /**************************************************************************** 20308 * BAM_NextPage :: lp_ud_field 20309 */ 20310 /* BAM_NextPage :: lp_ud_field :: reserved0 [15:11] */ 20311 #define BAM_NEXTPAGE_LP_UD_FIELD_RESERVED0_MASK 0xf800 20312 #define BAM_NEXTPAGE_LP_UD_FIELD_RESERVED0_ALIGN 0 20313 #define BAM_NEXTPAGE_LP_UD_FIELD_RESERVED0_BITS 5 20314 #define BAM_NEXTPAGE_LP_UD_FIELD_RESERVED0_SHIFT 11 20315 20316 /* BAM_NextPage :: lp_ud_field :: ud_reserved [10:06] */ 20317 #define BAM_NEXTPAGE_LP_UD_FIELD_UD_RESERVED_MASK 0x07c0 20318 #define BAM_NEXTPAGE_LP_UD_FIELD_UD_RESERVED_ALIGN 0 20319 #define BAM_NEXTPAGE_LP_UD_FIELD_UD_RESERVED_BITS 5 20320 #define BAM_NEXTPAGE_LP_UD_FIELD_UD_RESERVED_SHIFT 6 20321 20322 /* BAM_NextPage :: lp_ud_field :: remote_BN_page [05:05] */ 20323 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_BN_PAGE_MASK 0x0020 20324 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_BN_PAGE_ALIGN 0 20325 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_BN_PAGE_BITS 1 20326 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_BN_PAGE_SHIFT 5 20327 20328 /* BAM_NextPage :: lp_ud_field :: inband_MDIO [04:04] */ 20329 #define BAM_NEXTPAGE_LP_UD_FIELD_INBAND_MDIO_MASK 0x0010 20330 #define BAM_NEXTPAGE_LP_UD_FIELD_INBAND_MDIO_ALIGN 0 20331 #define BAM_NEXTPAGE_LP_UD_FIELD_INBAND_MDIO_BITS 1 20332 #define BAM_NEXTPAGE_LP_UD_FIELD_INBAND_MDIO_SHIFT 4 20333 20334 /* BAM_NextPage :: lp_ud_field :: autoneg_MDIO [03:03] */ 20335 #define BAM_NEXTPAGE_LP_UD_FIELD_AUTONEG_MDIO_MASK 0x0008 20336 #define BAM_NEXTPAGE_LP_UD_FIELD_AUTONEG_MDIO_ALIGN 0 20337 #define BAM_NEXTPAGE_LP_UD_FIELD_AUTONEG_MDIO_BITS 1 20338 #define BAM_NEXTPAGE_LP_UD_FIELD_AUTONEG_MDIO_SHIFT 3 20339 20340 /* BAM_NextPage :: lp_ud_field :: remote_serdes_phy [02:02] */ 20341 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_SERDES_PHY_MASK 0x0004 20342 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_SERDES_PHY_ALIGN 0 20343 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_SERDES_PHY_BITS 1 20344 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_SERDES_PHY_SHIFT 2 20345 20346 /* BAM_NextPage :: lp_ud_field :: remote_cu_phy [01:01] */ 20347 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_CU_PHY_MASK 0x0002 20348 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_CU_PHY_ALIGN 0 20349 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_CU_PHY_BITS 1 20350 #define BAM_NEXTPAGE_LP_UD_FIELD_REMOTE_CU_PHY_SHIFT 1 20351 20352 /* BAM_NextPage :: lp_ud_field :: over1g [00:00] */ 20353 #define BAM_NEXTPAGE_LP_UD_FIELD_OVER1G_MASK 0x0001 20354 #define BAM_NEXTPAGE_LP_UD_FIELD_OVER1G_ALIGN 0 20355 #define BAM_NEXTPAGE_LP_UD_FIELD_OVER1G_BITS 1 20356 #define BAM_NEXTPAGE_LP_UD_FIELD_OVER1G_SHIFT 0 20357 20358 20359 /**************************************************************************** 20360 * XGXS16G_USER_CL73_UserB0 20361 */ 20362 /**************************************************************************** 20363 * CL73_UserB0 :: CL73_UCtrl1 20364 */ 20365 /* CL73_UserB0 :: CL73_UCtrl1 :: reserved0 [15:13] */ 20366 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_MASK 0xe000 20367 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_ALIGN 0 20368 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_BITS 3 20369 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_SHIFT 13 20370 20371 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_lossOfSyncFail_en [12:12] */ 20372 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_MASK 0x1000 20373 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_ALIGN 0 20374 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_BITS 1 20375 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_SHIFT 12 20376 20377 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_parDet_dis [11:11] */ 20378 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_MASK 0x0800 20379 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_ALIGN 0 20380 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_BITS 1 20381 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_SHIFT 11 20382 20383 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_allowCl37AN [10:10] */ 20384 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_MASK 0x0400 20385 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_ALIGN 0 20386 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_BITS 1 20387 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_SHIFT 10 20388 20389 /* CL73_UserB0 :: CL73_UCtrl1 :: longParDetTimer_dis [09:09] */ 20390 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_MASK 0x0200 20391 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_ALIGN 0 20392 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_BITS 1 20393 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_SHIFT 9 20394 20395 /* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimer_dis [08:08] */ 20396 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_MASK 0x0100 20397 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_ALIGN 0 20398 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_BITS 1 20399 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_SHIFT 8 20400 20401 /* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimerQual_en [07:07] */ 20402 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_MASK 0x0080 20403 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_ALIGN 0 20404 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_BITS 1 20405 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_SHIFT 7 20406 20407 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_over [06:06] */ 20408 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_MASK 0x0040 20409 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_ALIGN 0 20410 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_BITS 1 20411 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_SHIFT 6 20412 20413 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_val [05:05] */ 20414 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_MASK 0x0020 20415 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_ALIGN 0 20416 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_BITS 1 20417 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_SHIFT 5 20418 20419 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart_wo_link_fail [04:04] */ 20420 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_MASK 0x0010 20421 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_ALIGN 0 20422 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_BITS 1 20423 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_SHIFT 4 20424 20425 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart [03:03] */ 20426 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_MASK 0x0008 20427 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_ALIGN 0 20428 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_BITS 1 20429 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_SHIFT 3 20430 20431 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl37_restart [02:02] */ 20432 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_MASK 0x0004 20433 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_ALIGN 0 20434 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_BITS 1 20435 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_SHIFT 2 20436 20437 /* CL73_UserB0 :: CL73_UCtrl1 :: CL73_Ustat1_muxsel [01:01] */ 20438 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_MASK 0x0002 20439 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_ALIGN 0 20440 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_BITS 1 20441 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_SHIFT 1 20442 20443 /* CL73_UserB0 :: CL73_UCtrl1 :: force_cl73_tx_omux_en [00:00] */ 20444 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_MASK 0x0001 20445 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_ALIGN 0 20446 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_BITS 1 20447 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_SHIFT 0 20448 20449 20450 /**************************************************************************** 20451 * CL73_UserB0 :: CL73_Ustat1 20452 */ 20453 /* CL73_UserB0 :: CL73_Ustat1 :: reserved0 [15:10] */ 20454 #define CL73_USERB0_CL73_USTAT1_RESERVED0_MASK 0xfc00 20455 #define CL73_USERB0_CL73_USTAT1_RESERVED0_ALIGN 0 20456 #define CL73_USERB0_CL73_USTAT1_RESERVED0_BITS 6 20457 #define CL73_USERB0_CL73_USTAT1_RESERVED0_SHIFT 10 20458 20459 /* CL73_UserB0 :: CL73_Ustat1 :: arb_fsm [09:00] */ 20460 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_MASK 0x03ff 20461 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_ALIGN 0 20462 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_BITS 10 20463 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_SHIFT 0 20464 20465 20466 /**************************************************************************** 20467 * CL73_UserB0 :: CL73_BAMCtrl1 20468 */ 20469 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamEn [15:15] */ 20470 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_MASK 0x8000 20471 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_ALIGN 0 20472 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_BITS 1 20473 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_SHIFT 15 20474 20475 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_station_mngr_en [14:14] */ 20476 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_MASK 0x4000 20477 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_ALIGN 0 20478 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_BITS 1 20479 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_SHIFT 14 20480 20481 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamNP_after_bp_en [13:13] */ 20482 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_MASK 0x2000 20483 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_ALIGN 0 20484 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_BITS 1 20485 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_SHIFT 13 20486 20487 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_en [12:12] */ 20488 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_MASK 0x1000 20489 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_ALIGN 0 20490 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_BITS 1 20491 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_SHIFT 12 20492 20493 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_step [11:11] */ 20494 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_MASK 0x0800 20495 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_ALIGN 0 20496 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_BITS 1 20497 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_SHIFT 11 20498 20499 /* CL73_UserB0 :: CL73_BAMCtrl1 :: reserved0 [10:10] */ 20500 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_MASK 0x0400 20501 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_ALIGN 0 20502 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_BITS 1 20503 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_SHIFT 10 20504 20505 /* CL73_UserB0 :: CL73_BAMCtrl1 :: UD_code_field [09:00] */ 20506 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_MASK 0x03ff 20507 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_ALIGN 0 20508 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_BITS 10 20509 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_SHIFT 0 20510 20511 20512 /**************************************************************************** 20513 * CL73_UserB0 :: CL73_BAMCtrl2 20514 */ 20515 /* CL73_UserB0 :: CL73_BAMCtrl2 :: UD_code_field [15:00] */ 20516 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_MASK 0xffff 20517 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_ALIGN 0 20518 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_BITS 16 20519 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_SHIFT 0 20520 20521 20522 /**************************************************************************** 20523 * CL73_UserB0 :: CL73_BAMCtrl3 20524 */ 20525 /* CL73_UserB0 :: CL73_BAMCtrl3 :: UD_code_field [15:00] */ 20526 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_MASK 0xffff 20527 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_ALIGN 0 20528 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_BITS 16 20529 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_SHIFT 0 20530 20531 20532 /**************************************************************************** 20533 * CL73_UserB0 :: CL73_BAMStat1 20534 */ 20535 /* CL73_UserB0 :: CL73_BAMStat1 :: reserved0 [15:10] */ 20536 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_MASK 0xfc00 20537 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_ALIGN 0 20538 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_BITS 6 20539 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_SHIFT 10 20540 20541 /* CL73_UserB0 :: CL73_BAMStat1 :: LP_UD_code_field [09:00] */ 20542 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_MASK 0x03ff 20543 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_ALIGN 0 20544 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_BITS 10 20545 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_SHIFT 0 20546 20547 20548 /**************************************************************************** 20549 * CL73_UserB0 :: CL73_BAMStat2 20550 */ 20551 /* CL73_UserB0 :: CL73_BAMStat2 :: LP_UD_code_field [15:00] */ 20552 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_MASK 0xffff 20553 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_ALIGN 0 20554 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_BITS 16 20555 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_SHIFT 0 20556 20557 20558 /**************************************************************************** 20559 * CL73_UserB0 :: CL73_BAMStat3 20560 */ 20561 /* CL73_UserB0 :: CL73_BAMStat3 :: LP_UD_code_field [15:00] */ 20562 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_MASK 0xffff 20563 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_ALIGN 0 20564 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_BITS 16 20565 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_SHIFT 0 20566 20567 /**************************************************************************** 20568 * FX100 :: Control1 20569 */ 20570 /* FX100 :: Control1 :: data_sampler_en [15:15] */ 20571 #define FX100_CONTROL1_DATA_SAMPLER_EN_MASK 0x8000 20572 #define FX100_CONTROL1_DATA_SAMPLER_EN_ALIGN 0 20573 #define FX100_CONTROL1_DATA_SAMPLER_EN_BITS 1 20574 #define FX100_CONTROL1_DATA_SAMPLER_EN_SHIFT 15 20575 20576 /* FX100 :: Control1 :: fiber_autopwrdwn_wakeup [14:14] */ 20577 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_MASK 0x4000 20578 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_ALIGN 0 20579 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_BITS 1 20580 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_SHIFT 14 20581 20582 /* FX100 :: Control1 :: fiber_autopwrdwn_sleep [13:13] */ 20583 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_MASK 0x2000 20584 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_ALIGN 0 20585 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_BITS 1 20586 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_SHIFT 13 20587 20588 /* FX100 :: Control1 :: fiberautopwrdwn_en [12:12] */ 20589 #define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_MASK 0x1000 20590 #define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_ALIGN 0 20591 #define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_BITS 1 20592 #define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_SHIFT 12 20593 20594 /* FX100 :: Control1 :: fiber_autopwrdwn_dis [11:11] */ 20595 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_MASK 0x0800 20596 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_ALIGN 0 20597 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_BITS 1 20598 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_SHIFT 11 20599 20600 /* FX100 :: Control1 :: autodet_timer_sel [10:10] */ 20601 #define FX100_CONTROL1_AUTODET_TIMER_SEL_MASK 0x0400 20602 #define FX100_CONTROL1_AUTODET_TIMER_SEL_ALIGN 0 20603 #define FX100_CONTROL1_AUTODET_TIMER_SEL_BITS 1 20604 #define FX100_CONTROL1_AUTODET_TIMER_SEL_SHIFT 10 20605 20606 /* FX100 :: Control1 :: rxdata_sel [09:06] */ 20607 #define FX100_CONTROL1_RXDATA_SEL_MASK 0x03c0 20608 #define FX100_CONTROL1_RXDATA_SEL_ALIGN 0 20609 #define FX100_CONTROL1_RXDATA_SEL_BITS 4 20610 #define FX100_CONTROL1_RXDATA_SEL_SHIFT 6 20611 20612 /* FX100 :: Control1 :: disable_rx_qual [05:05] */ 20613 #define FX100_CONTROL1_DISABLE_RX_QUAL_MASK 0x0020 20614 #define FX100_CONTROL1_DISABLE_RX_QUAL_ALIGN 0 20615 #define FX100_CONTROL1_DISABLE_RX_QUAL_BITS 1 20616 #define FX100_CONTROL1_DISABLE_RX_QUAL_SHIFT 5 20617 20618 /* FX100 :: Control1 :: force_rx_qual [04:04] */ 20619 #define FX100_CONTROL1_FORCE_RX_QUAL_MASK 0x0010 20620 #define FX100_CONTROL1_FORCE_RX_QUAL_ALIGN 0 20621 #define FX100_CONTROL1_FORCE_RX_QUAL_BITS 1 20622 #define FX100_CONTROL1_FORCE_RX_QUAL_SHIFT 4 20623 20624 /* FX100 :: Control1 :: far_end_fault_en [03:03] */ 20625 #define FX100_CONTROL1_FAR_END_FAULT_EN_MASK 0x0008 20626 #define FX100_CONTROL1_FAR_END_FAULT_EN_ALIGN 0 20627 #define FX100_CONTROL1_FAR_END_FAULT_EN_BITS 1 20628 #define FX100_CONTROL1_FAR_END_FAULT_EN_SHIFT 3 20629 20630 /* FX100 :: Control1 :: autodet_en [02:02] */ 20631 #define FX100_CONTROL1_AUTODET_EN_MASK 0x0004 20632 #define FX100_CONTROL1_AUTODET_EN_ALIGN 0 20633 #define FX100_CONTROL1_AUTODET_EN_BITS 1 20634 #define FX100_CONTROL1_AUTODET_EN_SHIFT 2 20635 20636 /* FX100 :: Control1 :: full_duplex [01:01] */ 20637 #define FX100_CONTROL1_FULL_DUPLEX_MASK 0x0002 20638 #define FX100_CONTROL1_FULL_DUPLEX_ALIGN 0 20639 #define FX100_CONTROL1_FULL_DUPLEX_BITS 1 20640 #define FX100_CONTROL1_FULL_DUPLEX_SHIFT 1 20641 20642 /* FX100 :: Control1 :: enable [00:00] */ 20643 #define FX100_CONTROL1_ENABLE_MASK 0x0001 20644 #define FX100_CONTROL1_ENABLE_ALIGN 0 20645 #define FX100_CONTROL1_ENABLE_BITS 1 20646 #define FX100_CONTROL1_ENABLE_SHIFT 0 20647 20648 20649 /**************************************************************************** 20650 * FX100 :: Control2 20651 */ 20652 /* FX100 :: Control2 :: reserved0 [15:12] */ 20653 #define FX100_CONTROL2_RESERVED0_MASK 0xf000 20654 #define FX100_CONTROL2_RESERVED0_ALIGN 0 20655 #define FX100_CONTROL2_RESERVED0_BITS 4 20656 #define FX100_CONTROL2_RESERVED0_SHIFT 12 20657 20658 /* FX100 :: Control2 :: ping_pong_disable [11:11] */ 20659 #define FX100_CONTROL2_PING_PONG_DISABLE_MASK 0x0800 20660 #define FX100_CONTROL2_PING_PONG_DISABLE_ALIGN 0 20661 #define FX100_CONTROL2_PING_PONG_DISABLE_BITS 1 20662 #define FX100_CONTROL2_PING_PONG_DISABLE_SHIFT 11 20663 20664 /* FX100 :: Control2 :: pll_clk125_sw_ref [10:10] */ 20665 #define FX100_CONTROL2_PLL_CLK125_SW_REF_MASK 0x0400 20666 #define FX100_CONTROL2_PLL_CLK125_SW_REF_ALIGN 0 20667 #define FX100_CONTROL2_PLL_CLK125_SW_REF_BITS 1 20668 #define FX100_CONTROL2_PLL_CLK125_SW_REF_SHIFT 10 20669 20670 /* FX100 :: Control2 :: pll_clk125_sw_en [09:09] */ 20671 #define FX100_CONTROL2_PLL_CLK125_SW_EN_MASK 0x0200 20672 #define FX100_CONTROL2_PLL_CLK125_SW_EN_ALIGN 0 20673 #define FX100_CONTROL2_PLL_CLK125_SW_EN_BITS 1 20674 #define FX100_CONTROL2_PLL_CLK125_SW_EN_SHIFT 9 20675 20676 /* FX100 :: Control2 :: clk_out_1000_sw_def [08:08] */ 20677 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_MASK 0x0100 20678 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_ALIGN 0 20679 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_BITS 1 20680 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_SHIFT 8 20681 20682 /* FX100 :: Control2 :: clk_out_1000_sw_en [07:07] */ 20683 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_MASK 0x0080 20684 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_ALIGN 0 20685 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_BITS 1 20686 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_SHIFT 7 20687 20688 /* FX100 :: Control2 :: mii_rxc_out_sw_ref [06:06] */ 20689 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_MASK 0x0040 20690 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_ALIGN 0 20691 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_BITS 1 20692 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_SHIFT 6 20693 20694 /* FX100 :: Control2 :: mii_rxc_out_sw_en [05:05] */ 20695 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_MASK 0x0020 20696 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_ALIGN 0 20697 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_BITS 1 20698 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_SHIFT 5 20699 20700 /* FX100 :: Control2 :: mii_rxc_out_sm_rst [04:04] */ 20701 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_MASK 0x0010 20702 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_ALIGN 0 20703 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_BITS 1 20704 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_SHIFT 4 20705 20706 /* FX100 :: Control2 :: mode_chg_nrst [03:03] */ 20707 #define FX100_CONTROL2_MODE_CHG_NRST_MASK 0x0008 20708 #define FX100_CONTROL2_MODE_CHG_NRST_ALIGN 0 20709 #define FX100_CONTROL2_MODE_CHG_NRST_BITS 1 20710 #define FX100_CONTROL2_MODE_CHG_NRST_SHIFT 3 20711 20712 /* FX100 :: Control2 :: reset_rxfifo [02:02] */ 20713 #define FX100_CONTROL2_RESET_RXFIFO_MASK 0x0004 20714 #define FX100_CONTROL2_RESET_RXFIFO_ALIGN 0 20715 #define FX100_CONTROL2_RESET_RXFIFO_BITS 1 20716 #define FX100_CONTROL2_RESET_RXFIFO_SHIFT 2 20717 20718 /* FX100 :: Control2 :: bypass_rxfifo [01:01] */ 20719 #define FX100_CONTROL2_BYPASS_RXFIFO_MASK 0x0002 20720 #define FX100_CONTROL2_BYPASS_RXFIFO_ALIGN 0 20721 #define FX100_CONTROL2_BYPASS_RXFIFO_BITS 1 20722 #define FX100_CONTROL2_BYPASS_RXFIFO_SHIFT 1 20723 20724 /* FX100 :: Control2 :: extend_pkt_size [00:00] */ 20725 #define FX100_CONTROL2_EXTEND_PKT_SIZE_MASK 0x0001 20726 #define FX100_CONTROL2_EXTEND_PKT_SIZE_ALIGN 0 20727 #define FX100_CONTROL2_EXTEND_PKT_SIZE_BITS 1 20728 #define FX100_CONTROL2_EXTEND_PKT_SIZE_SHIFT 0 20729 20730 20731 /**************************************************************************** 20732 * FX100 :: Control3 20733 */ 20734 /* FX100 :: Control3 :: number_of_idle [15:08] */ 20735 #define FX100_CONTROL3_NUMBER_OF_IDLE_MASK 0xff00 20736 #define FX100_CONTROL3_NUMBER_OF_IDLE_ALIGN 0 20737 #define FX100_CONTROL3_NUMBER_OF_IDLE_BITS 8 20738 #define FX100_CONTROL3_NUMBER_OF_IDLE_SHIFT 8 20739 20740 /* FX100 :: Control3 :: correlator_disable [07:07] */ 20741 #define FX100_CONTROL3_CORRELATOR_DISABLE_MASK 0x0080 20742 #define FX100_CONTROL3_CORRELATOR_DISABLE_ALIGN 0 20743 #define FX100_CONTROL3_CORRELATOR_DISABLE_BITS 1 20744 #define FX100_CONTROL3_CORRELATOR_DISABLE_SHIFT 7 20745 20746 /* FX100 :: Control3 :: bypass_nrz [06:06] */ 20747 #define FX100_CONTROL3_BYPASS_NRZ_MASK 0x0040 20748 #define FX100_CONTROL3_BYPASS_NRZ_ALIGN 0 20749 #define FX100_CONTROL3_BYPASS_NRZ_BITS 1 20750 #define FX100_CONTROL3_BYPASS_NRZ_SHIFT 6 20751 20752 /* FX100 :: Control3 :: bypass_encoder [05:05] */ 20753 #define FX100_CONTROL3_BYPASS_ENCODER_MASK 0x0020 20754 #define FX100_CONTROL3_BYPASS_ENCODER_ALIGN 0 20755 #define FX100_CONTROL3_BYPASS_ENCODER_BITS 1 20756 #define FX100_CONTROL3_BYPASS_ENCODER_SHIFT 5 20757 20758 /* FX100 :: Control3 :: bypass_alignment [04:04] */ 20759 #define FX100_CONTROL3_BYPASS_ALIGNMENT_MASK 0x0010 20760 #define FX100_CONTROL3_BYPASS_ALIGNMENT_ALIGN 0 20761 #define FX100_CONTROL3_BYPASS_ALIGNMENT_BITS 1 20762 #define FX100_CONTROL3_BYPASS_ALIGNMENT_SHIFT 4 20763 20764 /* FX100 :: Control3 :: force_link [03:03] */ 20765 #define FX100_CONTROL3_FORCE_LINK_MASK 0x0008 20766 #define FX100_CONTROL3_FORCE_LINK_ALIGN 0 20767 #define FX100_CONTROL3_FORCE_LINK_BITS 1 20768 #define FX100_CONTROL3_FORCE_LINK_SHIFT 3 20769 20770 /* FX100 :: Control3 :: force_lock [02:02] */ 20771 #define FX100_CONTROL3_FORCE_LOCK_MASK 0x0004 20772 #define FX100_CONTROL3_FORCE_LOCK_ALIGN 0 20773 #define FX100_CONTROL3_FORCE_LOCK_BITS 1 20774 #define FX100_CONTROL3_FORCE_LOCK_SHIFT 2 20775 20776 /* FX100 :: Control3 :: fast_unlock_timer [01:01] */ 20777 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_MASK 0x0002 20778 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_ALIGN 0 20779 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_BITS 1 20780 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_SHIFT 1 20781 20782 /* FX100 :: Control3 :: fast_timers [00:00] */ 20783 #define FX100_CONTROL3_FAST_TIMERS_MASK 0x0001 20784 #define FX100_CONTROL3_FAST_TIMERS_ALIGN 0 20785 #define FX100_CONTROL3_FAST_TIMERS_BITS 1 20786 #define FX100_CONTROL3_FAST_TIMERS_SHIFT 0 20787 20788 20789 /**************************************************************************** 20790 * FX100 :: Status1 20791 */ 20792 /* FX100 :: Status1 :: mode_change [15:15] */ 20793 #define FX100_STATUS1_MODE_CHANGE_MASK 0x8000 20794 #define FX100_STATUS1_MODE_CHANGE_ALIGN 0 20795 #define FX100_STATUS1_MODE_CHANGE_BITS 1 20796 #define FX100_STATUS1_MODE_CHANGE_SHIFT 15 20797 20798 /* FX100 :: Status1 :: reserved0 [14:12] */ 20799 #define FX100_STATUS1_RESERVED0_MASK 0x7000 20800 #define FX100_STATUS1_RESERVED0_ALIGN 0 20801 #define FX100_STATUS1_RESERVED0_BITS 3 20802 #define FX100_STATUS1_RESERVED0_SHIFT 12 20803 20804 /* FX100 :: Status1 :: fiber_pwrdwn_status_chg [11:11] */ 20805 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_MASK 0x0800 20806 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_ALIGN 0 20807 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_BITS 1 20808 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_SHIFT 11 20809 20810 /* FX100 :: Status1 :: fiber_pwrdwn [10:10] */ 20811 #define FX100_STATUS1_FIBER_PWRDWN_MASK 0x0400 20812 #define FX100_STATUS1_FIBER_PWRDWN_ALIGN 0 20813 #define FX100_STATUS1_FIBER_PWRDWN_BITS 1 20814 #define FX100_STATUS1_FIBER_PWRDWN_SHIFT 10 20815 20816 /* FX100 :: Status1 :: link_status_chg [09:09] */ 20817 #define FX100_STATUS1_LINK_STATUS_CHG_MASK 0x0200 20818 #define FX100_STATUS1_LINK_STATUS_CHG_ALIGN 0 20819 #define FX100_STATUS1_LINK_STATUS_CHG_BITS 1 20820 #define FX100_STATUS1_LINK_STATUS_CHG_SHIFT 9 20821 20822 /* FX100 :: Status1 :: bad_esd_detected [08:08] */ 20823 #define FX100_STATUS1_BAD_ESD_DETECTED_MASK 0x0100 20824 #define FX100_STATUS1_BAD_ESD_DETECTED_ALIGN 0 20825 #define FX100_STATUS1_BAD_ESD_DETECTED_BITS 1 20826 #define FX100_STATUS1_BAD_ESD_DETECTED_SHIFT 8 20827 20828 /* FX100 :: Status1 :: false_carrier_detected [07:07] */ 20829 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_MASK 0x0080 20830 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_ALIGN 0 20831 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_BITS 1 20832 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_SHIFT 7 20833 20834 /* FX100 :: Status1 :: tx_err_detected [06:06] */ 20835 #define FX100_STATUS1_TX_ERR_DETECTED_MASK 0x0040 20836 #define FX100_STATUS1_TX_ERR_DETECTED_ALIGN 0 20837 #define FX100_STATUS1_TX_ERR_DETECTED_BITS 1 20838 #define FX100_STATUS1_TX_ERR_DETECTED_SHIFT 6 20839 20840 /* FX100 :: Status1 :: rx_err_detected [05:05] */ 20841 #define FX100_STATUS1_RX_ERR_DETECTED_MASK 0x0020 20842 #define FX100_STATUS1_RX_ERR_DETECTED_ALIGN 0 20843 #define FX100_STATUS1_RX_ERR_DETECTED_BITS 1 20844 #define FX100_STATUS1_RX_ERR_DETECTED_SHIFT 5 20845 20846 /* FX100 :: Status1 :: lock_timer_expired [04:04] */ 20847 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_MASK 0x0010 20848 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_ALIGN 0 20849 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_BITS 1 20850 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_SHIFT 4 20851 20852 /* FX100 :: Status1 :: lost_lock [03:03] */ 20853 #define FX100_STATUS1_LOST_LOCK_MASK 0x0008 20854 #define FX100_STATUS1_LOST_LOCK_ALIGN 0 20855 #define FX100_STATUS1_LOST_LOCK_BITS 1 20856 #define FX100_STATUS1_LOST_LOCK_SHIFT 3 20857 20858 /* FX100 :: Status1 :: faulting [02:02] */ 20859 #define FX100_STATUS1_FAULTING_MASK 0x0004 20860 #define FX100_STATUS1_FAULTING_ALIGN 0 20861 #define FX100_STATUS1_FAULTING_BITS 1 20862 #define FX100_STATUS1_FAULTING_SHIFT 2 20863 20864 /* FX100 :: Status1 :: locked [01:01] */ 20865 #define FX100_STATUS1_LOCKED_MASK 0x0002 20866 #define FX100_STATUS1_LOCKED_ALIGN 0 20867 #define FX100_STATUS1_LOCKED_BITS 1 20868 #define FX100_STATUS1_LOCKED_SHIFT 1 20869 20870 /* FX100 :: Status1 :: link [00:00] */ 20871 #define FX100_STATUS1_LINK_MASK 0x0001 20872 #define FX100_STATUS1_LINK_ALIGN 0 20873 #define FX100_STATUS1_LINK_BITS 1 20874 #define FX100_STATUS1_LINK_SHIFT 0 20875 20876 20877 /**************************************************************************** 20878 * XGXS16G_USER_aerBlk 20879 */ 20880 /**************************************************************************** 20881 * aerBlk :: aer 20882 */ 20883 /* aerBlk :: aer :: MMD_deviceType [15:10] */ 20884 #define AERBLK_AER_MMD_DEVICETYPE_MASK 0xfc00 20885 #define AERBLK_AER_MMD_DEVICETYPE_ALIGN 0 20886 #define AERBLK_AER_MMD_DEVICETYPE_BITS 6 20887 #define AERBLK_AER_MMD_DEVICETYPE_SHIFT 10 20888 20889 /* aerBlk :: aer :: MMD_port [09:00] */ 20890 #define AERBLK_AER_MMD_PORT_MASK 0x03ff 20891 #define AERBLK_AER_MMD_PORT_ALIGN 0 20892 #define AERBLK_AER_MMD_PORT_BITS 10 20893 #define AERBLK_AER_MMD_PORT_SHIFT 0 20894 20895 20896 /**************************************************************************** 20897 * XGXS16G_USER_Combo_IEEE0 20898 */ 20899 /**************************************************************************** 20900 * Combo_IEEE0 :: MIICntl 20901 */ 20902 /* Combo_IEEE0 :: MIICntl :: rst_hw [15:15] */ 20903 #define COMBO_IEEE0_MIICNTL_RST_HW_MASK 0x8000 20904 #define COMBO_IEEE0_MIICNTL_RST_HW_ALIGN 0 20905 #define COMBO_IEEE0_MIICNTL_RST_HW_BITS 1 20906 #define COMBO_IEEE0_MIICNTL_RST_HW_SHIFT 15 20907 20908 /* Combo_IEEE0 :: MIICntl :: gloopback [14:14] */ 20909 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_MASK 0x4000 20910 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_ALIGN 0 20911 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_BITS 1 20912 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_SHIFT 14 20913 20914 /* Combo_IEEE0 :: MIICntl :: manual_speed0 [13:13] */ 20915 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_MASK 0x2000 20916 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_ALIGN 0 20917 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_BITS 1 20918 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_SHIFT 13 20919 20920 /* Combo_IEEE0 :: MIICntl :: autoneg_enable [12:12] */ 20921 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_MASK 0x1000 20922 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_ALIGN 0 20923 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_BITS 1 20924 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_SHIFT 12 20925 20926 /* Combo_IEEE0 :: MIICntl :: pwrdwn_sw [11:11] */ 20927 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_MASK 0x0800 20928 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_ALIGN 0 20929 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_BITS 1 20930 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_SHIFT 11 20931 20932 /* Combo_IEEE0 :: MIICntl :: reserved0 [10:10] */ 20933 #define COMBO_IEEE0_MIICNTL_RESERVED0_MASK 0x0400 20934 #define COMBO_IEEE0_MIICNTL_RESERVED0_ALIGN 0 20935 #define COMBO_IEEE0_MIICNTL_RESERVED0_BITS 1 20936 #define COMBO_IEEE0_MIICNTL_RESERVED0_SHIFT 10 20937 20938 /* Combo_IEEE0 :: MIICntl :: restart_autoneg [09:09] */ 20939 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_MASK 0x0200 20940 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_ALIGN 0 20941 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_BITS 1 20942 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_SHIFT 9 20943 20944 /* Combo_IEEE0 :: MIICntl :: full_duplex [08:08] */ 20945 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_MASK 0x0100 20946 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_ALIGN 0 20947 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_BITS 1 20948 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_SHIFT 8 20949 20950 /* Combo_IEEE0 :: MIICntl :: collision_test_en [07:07] */ 20951 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_MASK 0x0080 20952 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_ALIGN 0 20953 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_BITS 1 20954 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_SHIFT 7 20955 20956 /* Combo_IEEE0 :: MIICntl :: manual_speed1 [06:06] */ 20957 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_MASK 0x0040 20958 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_ALIGN 0 20959 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_BITS 1 20960 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_SHIFT 6 20961 20962 /* Combo_IEEE0 :: MIICntl :: reserved1 [05:00] */ 20963 #define COMBO_IEEE0_MIICNTL_RESERVED1_MASK 0x003f 20964 #define COMBO_IEEE0_MIICNTL_RESERVED1_ALIGN 0 20965 #define COMBO_IEEE0_MIICNTL_RESERVED1_BITS 6 20966 #define COMBO_IEEE0_MIICNTL_RESERVED1_SHIFT 0 20967 20968 20969 /**************************************************************************** 20970 * Combo_IEEE0 :: MIIStat 20971 */ 20972 /* Combo_IEEE0 :: MIIStat :: s100BASE_T4_capable [15:15] */ 20973 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_MASK 0x8000 20974 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN 0 20975 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_BITS 1 20976 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT 15 20977 20978 /* Combo_IEEE0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */ 20979 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000 20980 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0 20981 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1 20982 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14 20983 20984 /* Combo_IEEE0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */ 20985 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000 20986 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0 20987 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1 20988 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13 20989 20990 /* Combo_IEEE0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */ 20991 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x1000 20992 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0 20993 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS 1 20994 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12 20995 20996 /* Combo_IEEE0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */ 20997 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x0800 20998 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0 20999 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS 1 21000 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11 21001 21002 /* Combo_IEEE0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */ 21003 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400 21004 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0 21005 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1 21006 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10 21007 21008 /* Combo_IEEE0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */ 21009 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200 21010 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0 21011 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1 21012 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9 21013 21014 /* Combo_IEEE0 :: MIIStat :: extended_status [08:08] */ 21015 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_MASK 0x0100 21016 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_ALIGN 0 21017 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_BITS 1 21018 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_SHIFT 8 21019 21020 /* Combo_IEEE0 :: MIIStat :: reserved0 [07:07] */ 21021 #define COMBO_IEEE0_MIISTAT_RESERVED0_MASK 0x0080 21022 #define COMBO_IEEE0_MIISTAT_RESERVED0_ALIGN 0 21023 #define COMBO_IEEE0_MIISTAT_RESERVED0_BITS 1 21024 #define COMBO_IEEE0_MIISTAT_RESERVED0_SHIFT 7 21025 21026 /* Combo_IEEE0 :: MIIStat :: mf_preamble_supression [06:06] */ 21027 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK 0x0040 21028 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN 0 21029 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS 1 21030 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT 6 21031 21032 /* Combo_IEEE0 :: MIIStat :: autoneg_complete [05:05] */ 21033 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_MASK 0x0020 21034 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_ALIGN 0 21035 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_BITS 1 21036 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_SHIFT 5 21037 21038 /* Combo_IEEE0 :: MIIStat :: remote_fault [04:04] */ 21039 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_MASK 0x0010 21040 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_ALIGN 0 21041 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_BITS 1 21042 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_SHIFT 4 21043 21044 /* Combo_IEEE0 :: MIIStat :: autoneg_ability [03:03] */ 21045 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_MASK 0x0008 21046 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_ALIGN 0 21047 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_BITS 1 21048 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_SHIFT 3 21049 21050 /* Combo_IEEE0 :: MIIStat :: link_status [02:02] */ 21051 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_MASK 0x0004 21052 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_ALIGN 0 21053 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_BITS 1 21054 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_SHIFT 2 21055 21056 /* Combo_IEEE0 :: MIIStat :: jabber_detect [01:01] */ 21057 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_MASK 0x0002 21058 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_ALIGN 0 21059 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_BITS 1 21060 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_SHIFT 1 21061 21062 /* Combo_IEEE0 :: MIIStat :: extended_capability [00:00] */ 21063 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_MASK 0x0001 21064 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_ALIGN 0 21065 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_BITS 1 21066 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_SHIFT 0 21067 21068 21069 /**************************************************************************** 21070 * Combo_IEEE0 :: Id1 21071 */ 21072 /* Combo_IEEE0 :: Id1 :: regid [15:00] */ 21073 #define COMBO_IEEE0_ID1_REGID_MASK 0xffff 21074 #define COMBO_IEEE0_ID1_REGID_ALIGN 0 21075 #define COMBO_IEEE0_ID1_REGID_BITS 16 21076 #define COMBO_IEEE0_ID1_REGID_SHIFT 0 21077 21078 21079 /**************************************************************************** 21080 * Combo_IEEE0 :: Id2 21081 */ 21082 /* Combo_IEEE0 :: Id2 :: regid [15:00] */ 21083 #define COMBO_IEEE0_ID2_REGID_MASK 0xffff 21084 #define COMBO_IEEE0_ID2_REGID_ALIGN 0 21085 #define COMBO_IEEE0_ID2_REGID_BITS 16 21086 #define COMBO_IEEE0_ID2_REGID_SHIFT 0 21087 21088 21089 /**************************************************************************** 21090 * Combo_IEEE0 :: AutoNegAdv 21091 */ 21092 /* Combo_IEEE0 :: AutoNegAdv :: next_page [15:15] */ 21093 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_MASK 0x8000 21094 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_ALIGN 0 21095 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_BITS 1 21096 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_SHIFT 15 21097 21098 /* Combo_IEEE0 :: AutoNegAdv :: reserved0 [14:14] */ 21099 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_MASK 0x4000 21100 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_ALIGN 0 21101 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_BITS 1 21102 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_SHIFT 14 21103 21104 /* Combo_IEEE0 :: AutoNegAdv :: remote_fault [13:12] */ 21105 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_MASK 0x3000 21106 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_ALIGN 0 21107 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_BITS 2 21108 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_SHIFT 12 21109 21110 /* Combo_IEEE0 :: AutoNegAdv :: reserved1 [11:09] */ 21111 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_MASK 0x0e00 21112 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_ALIGN 0 21113 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_BITS 3 21114 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_SHIFT 9 21115 21116 /* Combo_IEEE0 :: AutoNegAdv :: pause [08:07] */ 21117 #define COMBO_IEEE0_AUTONEGADV_PAUSE_MASK 0x0180 21118 #define COMBO_IEEE0_AUTONEGADV_PAUSE_ALIGN 0 21119 #define COMBO_IEEE0_AUTONEGADV_PAUSE_BITS 2 21120 #define COMBO_IEEE0_AUTONEGADV_PAUSE_SHIFT 7 21121 21122 /* Combo_IEEE0 :: AutoNegAdv :: half_duplex [06:06] */ 21123 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_MASK 0x0040 21124 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_ALIGN 0 21125 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_BITS 1 21126 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_SHIFT 6 21127 21128 /* Combo_IEEE0 :: AutoNegAdv :: full_duplex [05:05] */ 21129 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_MASK 0x0020 21130 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_ALIGN 0 21131 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_BITS 1 21132 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_SHIFT 5 21133 21134 /* Combo_IEEE0 :: AutoNegAdv :: reserved2 [04:00] */ 21135 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_MASK 0x001f 21136 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_ALIGN 0 21137 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_BITS 5 21138 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_SHIFT 0 21139 21140 21141 /**************************************************************************** 21142 * Combo_IEEE0 :: AutoNegLPAbil 21143 */ 21144 /* Combo_IEEE0 :: AutoNegLPAbil :: next_page [15:15] */ 21145 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_MASK 0x8000 21146 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_ALIGN 0 21147 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_BITS 1 21148 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_SHIFT 15 21149 21150 /* Combo_IEEE0 :: AutoNegLPAbil :: acknowledge [14:14] */ 21151 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_MASK 0x4000 21152 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN 0 21153 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_BITS 1 21154 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT 14 21155 21156 /* Combo_IEEE0 :: AutoNegLPAbil :: remote_fault [13:12] */ 21157 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_MASK 0x3000 21158 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN 0 21159 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_BITS 2 21160 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT 12 21161 21162 /* Combo_IEEE0 :: AutoNegLPAbil :: reserved0 [11:09] */ 21163 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_MASK 0x0e00 21164 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_ALIGN 0 21165 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_BITS 3 21166 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_SHIFT 9 21167 21168 /* Combo_IEEE0 :: AutoNegLPAbil :: pause [08:07] */ 21169 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_MASK 0x0180 21170 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_ALIGN 0 21171 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_BITS 2 21172 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_SHIFT 7 21173 21174 /* Combo_IEEE0 :: AutoNegLPAbil :: half_duplex [06:06] */ 21175 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_MASK 0x0040 21176 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN 0 21177 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_BITS 1 21178 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT 6 21179 21180 /* Combo_IEEE0 :: AutoNegLPAbil :: full_duplex [05:05] */ 21181 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_MASK 0x0020 21182 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN 0 21183 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_BITS 1 21184 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT 5 21185 21186 /* Combo_IEEE0 :: AutoNegLPAbil :: reserved1 [04:01] */ 21187 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_MASK 0x001e 21188 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_ALIGN 0 21189 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_BITS 4 21190 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_SHIFT 1 21191 21192 /* Combo_IEEE0 :: AutoNegLPAbil :: sgmii_mode [00:00] */ 21193 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_MASK 0x0001 21194 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_ALIGN 0 21195 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_BITS 1 21196 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_SHIFT 0 21197 21198 21199 /**************************************************************************** 21200 * Combo_IEEE0 :: AutoNegExp 21201 */ 21202 /* Combo_IEEE0 :: AutoNegExp :: reserved0 [15:03] */ 21203 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_MASK 0xfff8 21204 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_ALIGN 0 21205 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_BITS 13 21206 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_SHIFT 3 21207 21208 /* Combo_IEEE0 :: AutoNegExp :: next_page_ability [02:02] */ 21209 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK 0x0004 21210 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN 0 21211 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS 1 21212 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT 2 21213 21214 /* Combo_IEEE0 :: AutoNegExp :: page_received [01:01] */ 21215 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_MASK 0x0002 21216 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_ALIGN 0 21217 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_BITS 1 21218 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_SHIFT 1 21219 21220 /* Combo_IEEE0 :: AutoNegExp :: reserved1 [00:00] */ 21221 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_MASK 0x0001 21222 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_ALIGN 0 21223 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_BITS 1 21224 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_SHIFT 0 21225 21226 21227 /**************************************************************************** 21228 * Combo_IEEE0 :: AutoNegNP 21229 */ 21230 /* Combo_IEEE0 :: AutoNegNP :: Next_Page [15:15] */ 21231 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_MASK 0x8000 21232 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_ALIGN 0 21233 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_BITS 1 21234 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_SHIFT 15 21235 21236 /* Combo_IEEE0 :: AutoNegNP :: Ack [14:14] */ 21237 #define COMBO_IEEE0_AUTONEGNP_ACK_MASK 0x4000 21238 #define COMBO_IEEE0_AUTONEGNP_ACK_ALIGN 0 21239 #define COMBO_IEEE0_AUTONEGNP_ACK_BITS 1 21240 #define COMBO_IEEE0_AUTONEGNP_ACK_SHIFT 14 21241 21242 /* Combo_IEEE0 :: AutoNegNP :: Message_Page [13:13] */ 21243 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_MASK 0x2000 21244 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_ALIGN 0 21245 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_BITS 1 21246 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_SHIFT 13 21247 21248 /* Combo_IEEE0 :: AutoNegNP :: Ack2 [12:12] */ 21249 #define COMBO_IEEE0_AUTONEGNP_ACK2_MASK 0x1000 21250 #define COMBO_IEEE0_AUTONEGNP_ACK2_ALIGN 0 21251 #define COMBO_IEEE0_AUTONEGNP_ACK2_BITS 1 21252 #define COMBO_IEEE0_AUTONEGNP_ACK2_SHIFT 12 21253 21254 /* Combo_IEEE0 :: AutoNegNP :: Toggle [11:11] */ 21255 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_MASK 0x0800 21256 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_ALIGN 0 21257 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_BITS 1 21258 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_SHIFT 11 21259 21260 /* Combo_IEEE0 :: AutoNegNP :: Message [10:00] */ 21261 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_MASK 0x07ff 21262 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_ALIGN 0 21263 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_BITS 11 21264 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_SHIFT 0 21265 21266 21267 /**************************************************************************** 21268 * Combo_IEEE0 :: AutoNegLPAbil2 21269 */ 21270 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Next_Page [15:15] */ 21271 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_MASK 0x8000 21272 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN 0 21273 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_BITS 1 21274 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT 15 21275 21276 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack [14:14] */ 21277 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_MASK 0x4000 21278 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_ALIGN 0 21279 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_BITS 1 21280 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_SHIFT 14 21281 21282 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Message_Page [13:13] */ 21283 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK 0x2000 21284 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN 0 21285 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS 1 21286 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT 13 21287 21288 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack2 [12:12] */ 21289 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_MASK 0x1000 21290 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_ALIGN 0 21291 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_BITS 1 21292 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_SHIFT 12 21293 21294 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Toggle [11:11] */ 21295 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_MASK 0x0800 21296 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_ALIGN 0 21297 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_BITS 1 21298 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_SHIFT 11 21299 21300 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Message [10:00] */ 21301 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_MASK 0x07ff 21302 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_ALIGN 0 21303 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_BITS 11 21304 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_SHIFT 0 21305 21306 21307 /**************************************************************************** 21308 * Combo_IEEE0 :: MIIextStat 21309 */ 21310 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */ 21311 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000 21312 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0 21313 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1 21314 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15 21315 21316 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */ 21317 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000 21318 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0 21319 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1 21320 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14 21321 21322 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */ 21323 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000 21324 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0 21325 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1 21326 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13 21327 21328 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */ 21329 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000 21330 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0 21331 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1 21332 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12 21333 21334 /* Combo_IEEE0 :: MIIextStat :: reserved0 [11:00] */ 21335 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_MASK 0x0fff 21336 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_ALIGN 0 21337 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_BITS 12 21338 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_SHIFT 0 21339 21340 21341 /**************************************************************************** 21342 * Datatype Definitions. 21343 */ 21344 #endif /* _PHY_XGXS16G_H_ */ 21345 21346 /* End of File */ 21347