xgxs1.h (47351B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: xgxs.h 8 * Purpose: 10G 802.3ae Ethernet PHY 9 */ 10 11 #ifndef _PHY_XGXS_H_ 12 #define _PHY_XGXS_H_ 13 14 /* 10Gig XGMII/Serdes PHY Register definitions 15 * From Broadcom XGXS Core Documentation 16 */ 17 18 #define XGXS_IEEE_CTRL_SW_RST (1 << 15) /* S/W Reset */ 19 #define XGXS_IEEE_CTRL_LB_ENA (1 << 14) /* XGXS Local Loopback enable */ 20 #define XGXS_IEEE_CTRL_SW_PD (1 << 13) /* S/W Powerdown */ 21 22 #define XGXS_BLOCK_REG_SHIFT 0x03 /* Bits 4:9 of register selects blk*/ 23 24 25 #define XGXS_BLOCK_0_ASI 0x00 /* Standard, default regs above */ 26 #define XGXS_BLOCK_1_ASI 0x01 27 #define XGXS_BLOCK_2_ASI 0x02 28 #define XGXS_BLOCK_3_ASI 0x03 29 #define XGXS_BLOCK_4_ASI 0x04 30 31 /* Bit defines for ANA register */ 32 #define XGXS_ANA_HD (1 << 6) 33 #define XGXS_ANA_FD (1 << 5) 34 #define XGXS_ANA_PAUSE_NONE (0 << 7) 35 #define XGXS_ANA_PAUSE_SYM (1 << 7) 36 #define XGXS_ANA_PAUSE_ASYM (1 << 8) 37 #define XGXS_ANA_PAUSE_MASK (3 << 7) 38 39 /* Auto-Negotiation Link-Partner Ability Register */ 40 #define XGXS_ANP_NEXT_PG (1 << 15) 41 #define XGXS_ANP_ACK (1 << 14) 42 #define XGXS_ANP_RF_SHFT (12) /* Remote fault */ 43 #define XGXS_ANP_RF_MASK (0x3000) 44 #define XGXS_ANP_PAUSE_ASYM (1 << 8) 45 #define XGXS_ANP_PAUSE_SYM (1 << 7) 46 #define XGXS_ANP_HD (1 << 6) 47 #define XGXS_ANP_FD (1 << 5) 48 49 50 /* If application want to use this header file for accessing PHY registers, 51 * simply redefine PHYXGXS_REG macro to use BCM API as follows. 52 * 53 * #define SOC_PHY_REG_1000X BCM_PORT_PHY_REG_1000X 54 * 55 * #define PHYXGXS_REG_READ(_unit, _port, _flags, _reg_bank, _reg_addr, _val) \ 56 * bcm_port_phy_get((_unit), (_port), 0, 57 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 58 * (_val)) 59 * 60 * #define PHYXGXS_REG_WRITE(_unit, _port, _flags, _reg_bank, _reg_addr, _val) \ 61 * bcm_port_phy_set((_unit), (_port), 0, 62 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 63 * (_val)) 64 * 65 * #define PHYXGXS_REG_MODIFY(_unit, _port, _flags, _reg_bank, _reg_addr, _val)\ 66 * do { \ 67 * return BCM_E_UNAVAIL; \ 68 * } while(0) 69 */ 70 71 /* XGXS register access */ 72 #define PHYXGXS_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, \ 73 _reg_addr, _val) \ 74 phy_reg_xgxs_read((_unit), (_phy_ctrl), (_reg_bank), \ 75 (_reg_addr), (_val)) 76 #define PHYXGXS_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, \ 77 _reg_addr, _val) \ 78 phy_reg_xgxs_write((_unit), (_phy_ctrl), (_reg_bank), \ 79 (_reg_addr), (_val)) 80 #define PHYXGXS_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 81 _reg_addr, _val, _mask) \ 82 phy_reg_xgxs_modify((_unit), (_phy_ctrl), (_reg_bank), \ 83 (_reg_addr), (_val), (_mask)) 84 85 /****************************************/ 86 /* XAUI IEEE PMA/PMD Block (blk 0x0000) */ 87 /****************************************/ 88 89 /* XAUI MII Control Register (Addr 00h) */ 90 #define READ_PHYXGXS_XAUI_MII_CTRLr(_unit, _phy_ctrl, _val) \ 91 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 92 #define WRITE_PHYXGXS_XAUI_MII_CTRLr(_unit, _phy_ctrl, _val) \ 93 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 94 #define MODIFY_PHYXGXS_XAUI_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 95 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 96 (_val), (_mask)) 97 98 /* XAUI MII Status Register (ADDR 01h) */ 99 #define READ_PHYXGXS_XAUI_MII_STATr(_unit, _phy_ctrl, _val) \ 100 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 101 #define WRITE_PHYXGXS_XAUI_MII_STATr(_unit, _phy_ctrl, _val) \ 102 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 103 #define MODIFY_PHYXGXS_XAUI_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 104 PHYXGXS_REG_MODIFY((_unit, _phy_ctrl), 0x00, 0x0000, 0x01, \ 105 (_val), (_mask)) 106 107 /* XAUI PHY Identifier Register (ADDR 02h) */ 108 #define READ_PHYXGXS_XAUI_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 109 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 110 #define WRITE_PHYXGXS_XAUI_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 111 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 112 #define MODIFY_PHYXGXS_XAUI_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 113 PHYXGXS_REG_MODIFY((_unit, _phy_ctrl), 0x00, 0x0000, 0x02, \ 114 (_val), (_mask)) 115 116 /* XAUI PHY Identifier Register (ADDR 03h) */ 117 #define READ_PHYXGXS_XAUI_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 118 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 119 #define WRITE_PHYXGXS_XAUI_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 120 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 121 #define MODIFY_PHYXGXS_XAUI_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 122 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 123 (_val), (_mask)) 124 125 /* IEEE Speed Ability (Addr 04h) */ 126 /* IEEE Dev In Package 1 (Addr 05h) */ 127 /* IEEE Dev In Package 2 (Addr 06h) */ 128 /* IEEE Control 2 (Addr 07h) */ 129 /* IEEE Status 2 (Addr 08h) */ 130 131 /* IEEE Tx Disable (Addr 09h) */ 132 #define READ_PHYXGXS_XAUI_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 133 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 134 #define WRITE_PHYXGXS_XAUI_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 135 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 136 #define MODIFY_PHYXGXS_XAUI_TX_DISABLEr(_unit, _phy_ctrl, _val, _mask) \ 137 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 138 (_val), (_mask)) 139 140 /* IEEE RxSigDet (Addr 0Ah) */ 141 /* IEEE PMDExtAbil (Addr 0Bh) */ 142 /* Reserved (Addr 0Ch-0Eh) */ 143 144 /****************************/ 145 /* IEEE1 Block (blk 0x0010) */ 146 /****************************/ 147 /* Reserved (Addr 0x0010 - 0x0017) */ 148 149 /* Lane Status (Addr 0x0018) */ 150 #define READ_PHYXGXS_IEEE1_LANE_STATr(_unit, _phy_ctrl, _val) \ 151 PHYXGXS_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 152 0x0010, 0x08, (_val)) 153 #define WRITE_PHYXGXS_IEEE1_LANE_STATr(_unit, _phy_ctrl, _val) \ 154 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 155 0x0010, 0x08, (_val)) 156 #define MODIFY_PHYXGXS_IEEE1_LANE_STATr(_unit, _phy_ctrl, _val, _mask) \ 157 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 158 0x0010, 0x08, (_val), (_mask)) 159 160 /* IEEE Test Control (Addr 0x0019) */ 161 /* Reserved (Addr 0x001A - 0x001E) */ 162 163 /****************************/ 164 /* XGXS Block 0 (blk 0x8000) */ 165 /****************************/ 166 /* XGXS Control (Addr 0x8000) */ 167 #define READ_PHYXGXS_BLK0_CTRLr(_unit, _phy_ctrl, _val) \ 168 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x10, (_val)) 169 #define WRITE_PHYXGXS_BLK0_CTRLr(_unit, _phy_ctrl, _val) \ 170 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x10, (_val)) 171 #define MODIFY_PHYXGXS_BLK0_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 172 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x10, \ 173 (_val), (_mask)) 174 175 /* XGXS Status (Addr 0x8001) */ 176 #define READ_PHYXGXS_BLK0_STATr(_unit, _phy_ctrl, _val) \ 177 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x11, (_val)) 178 #define WRITE_PHYXGXS_BLK0_STATr(_unit, _phy_ctrl, _val) \ 179 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x11, (_val)) 180 #define MODIFY_PHYXGXS_BLK0_STATr(_unit, _phy_ctrl, _val, _mask) \ 181 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x11, \ 182 (_val), (_mask)) 183 184 /* XGMII Idle (Addr 0x8002) */ 185 #define READ_PHYXGXS_BLK0_XGMII_IDLEr(_unit, _phy_ctrl, _val) \ 186 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x12, (_val)) 187 #define WRITE_PHYXGXS_BLK0_XGMII_IDLEr(_unit, _phy_ctrl, _val) \ 188 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x12, (_val)) 189 #define MODIFY_PHYXGXS_BLK0_XGMII_IDLEr(_unit, _phy_ctrl, _val, _mask) \ 190 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x12, \ 191 (_val), (_mask)) 192 193 /* XGMII Sync (Addr 0x8003) */ 194 #define READ_PHYXGXS_BLK0_XGMII_SYNCr(_unit, _phy_ctrl, _val) \ 195 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x13, (_val)) 196 #define WRITE_PHYXGXS_BLK0_XGMII_SYNCr(_unit, _phy_ctrl, _val) \ 197 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x13, (_val)) 198 #define MODIFY_PHYXGXS_BLK0_XGMII_SYNCr(_unit, _phy_ctrl, _val, _mask) \ 199 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x13, \ 200 (_val), (_mask)) 201 202 /* XGMII Skip (Addr 0x8004) */ 203 #define READ_PHYXGXS_BLK0_XGMII_SKIPr(_unit, _phy_ctrl, _val) \ 204 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x14, (_val)) 205 #define WRITE_PHYXGXS_BLK0_XGMII_SKIPr(_unit, _phy_ctrl, _val) \ 206 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x14, (_val)) 207 #define MODIFY_PHYXGXS_BLK0_XGMII_SKIPr(_unit, _phy_ctrl, _val, _mask) \ 208 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x14, \ 209 (_val), (_mask)) 210 211 /* XGMII Sop Eop (Addr 0x8005) */ 212 #define READ_PHYXGXS_BLK0_XGMII_SOP_EOPr(_unit, _phy_ctrl, _val) \ 213 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x15, (_val)) 214 #define WRITE_PHYXGXS_BLK0_XGMII_SOP_EOPr(_unit, _phy_ctrl, _val) \ 215 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x15, (_val)) 216 #define MODIFY_PHYXGXS_BLK0_XGMII_SOP_EOPr(_unit, _phy_ctrl, _val, _mask) \ 217 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x15, \ 218 (_val), (_mask)) 219 220 /* XGMII Align (Addr 0x8006) */ 221 #define READ_PHYXGXS_BLK0_XGMII_ALIGNr(_unit, _phy_ctrl, _val) \ 222 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x16, (_val)) 223 #define WRITE_PHYXGXS_BLK0_XGMII_ALIGNr(_unit, _phy_ctrl, _val) \ 224 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x16, (_val)) 225 #define MODIFY_PHYXGXS_BLK0_XGMII_ALIGNr(_unit, _phy_ctrl, _val, _mask) \ 226 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x16, \ 227 (_val), (_mask)) 228 229 /* XGMII R Control (Addr 0x8007) */ 230 #define READ_PHYXGXS_BLK0_XGMII_RCTRLr(_unit, _phy_ctrl, _val) \ 231 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x17, (_val)) 232 #define WRITE_PHYXGXS_BLK0_XGMII_RCTRLr(_unit, _phy_ctrl, _val) \ 233 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x17, (_val)) 234 #define MODIFY_PHYXGXS_BLK0_XGMII_RCTRLr(_unit, _phy_ctrl, _val, _mask) \ 235 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x17, \ 236 (_val), (_mask)) 237 238 /* XGMII T Control (Addr 0x8008) */ 239 #define READ_PHYXGXS_BLK0_XGMII_TCTRLr(_unit, _phy_ctrl, _val) \ 240 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x18, (_val)) 241 #define WRITE_PHYXGXS_BLK0_XGMII_TCTRLr(_unit, _phy_ctrl, _val) \ 242 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x18, (_val)) 243 #define MODIFY_PHYXGXS_BLK0_XGMII_TCTRLr(_unit, _phy_ctrl, _val, _mask) \ 244 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x18, \ 245 (_val), (_mask)) 246 247 /* XGMII Swap (Addr 0x8009) */ 248 #define READ_PHYXGXS_BLK0_XGMII_SWAPr(_unit, _phy_ctrl, _val) \ 249 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x19, (_val)) 250 #define WRITE_PHYXGXS_BLK0_XGMII_SWAPr(_unit, _phy_ctrl, _val) \ 251 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x19, (_val)) 252 #define MODIFY_PHYXGXS_BLK0_XGMII_SWAPr(_unit, _phy_ctrl, _val, _mask) \ 253 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x19, \ 254 (_val), (_mask)) 255 256 /* IssLsid (Addr 0x800A) */ 257 #define READ_PHYXGXS_BLK0_ISS_LSIDr(_unit, _phy_ctrl, _val) \ 258 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1A, (_val)) 259 #define WRITE_PHYXGXS_BLK0_ISS_LSIDr(_unit, _phy_ctrl, _val) \ 260 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1A, (_val)) 261 #define MODIFY_PHYXGXS_BLK0_ISS_LSIDr(_unit, _phy_ctrl, _val, _mask) \ 262 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1A, \ 263 (_val), (_mask)) 264 265 /* IssTinfo (Addr 0x800B) */ 266 #define READ_PHYXGXS_BLK0_ISS_TINFOr(_unit, _phy_ctrl, _val) \ 267 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1B, (_val)) 268 #define WRITE_PHYXGXS_BLK0_ISS_TINFOr(_unit, _phy_ctrl, _val) \ 269 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1B, (_val)) 270 #define MODIFY_PHYXGXS_BLK0_ISS_TINFOr(_unit, _phy_ctrl, _val, _mask) \ 271 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1B, \ 272 (_val), (_mask)) 273 274 /* IssRinfo (Addr 0x800C) */ 275 #define READ_PHYXGXS_BLK0_ISS_RINFOr(_unit, _phy_ctrl, _val) \ 276 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1C, (_val)) 277 #define WRITE_PHYXGXS_BLK0_ISS_RINFOr(_unit, _phy_ctrl, _val) \ 278 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1C, (_val)) 279 #define MODIFY_PHYXGXS_BLK0_ISS_RINFOr(_unit, _phy_ctrl, _val, _mask) \ 280 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1C, \ 281 (_val), (_mask)) 282 283 /* CX4 SigDet Cnt (Addr 0x800D) */ 284 #define READ_PHYXGXS_BLK0_CX4_SIGDET_COUNTERr(_unit, _phy_ctrl, _val) \ 285 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1D, (_val)) 286 #define WRITE_PHYXGXS_BLK0_CX4_SIGDET_COUNTERr(_unit, _phy_ctrl, _val) \ 287 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1D, (_val)) 288 #define MODIFY_PHYXGXS_BLK0_CX4_SIGDET_COUNTERr(_unit, _phy_ctrl, _val, \ 289 _mask) \ 290 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1D, \ 291 (_val), (_mask)) 292 293 /* Misc Control 1 (Addr 0x800E) */ 294 #define READ_PHYXGXS_BLK0_MISC_CTRL1r(_unit, _phy_ctrl, _val) \ 295 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1E, (_val)) 296 #define WRITE_PHYXGXS_BLK0_MISC_CTRL1r(_unit, _phy_ctrl, _val) \ 297 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1E, (_val)) 298 #define MODIFY_PHYXGXS_BLK0_MISC_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 299 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8000, 0x1E, \ 300 (_val), (_mask)) 301 302 /*****************************/ 303 /* XGXS Block 1 (blk 0x8010) */ 304 /*****************************/ 305 /* deskew (Addr 0x8010) */ 306 #define READ_PHYXGXS_BLK1_DESKEWr(_unit, _phy_ctrl, _val) \ 307 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x10, (_val)) 308 #define WRITE_PHYXGXS_BLK1_DESKEWr(_unit, _phy_ctrl, _val) \ 309 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x10, (_val)) 310 #define MODIFY_PHYXGXS_BLK1_DESKEWr(_unit, _phy_ctrl, _val, _mask) \ 311 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x10, \ 312 (_val), (_mask)) 313 314 /* link (Addr 0x8011) */ 315 #define READ_PHYXGXS_BLK1_LINKr(_unit, _phy_ctrl, _val) \ 316 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x011, (_val)) 317 #define WRITE_PHYXGXS_BLK1_LINKr(_unit, _phy_ctrl, _val) \ 318 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x011,(_val)) 319 #define MODIFY_PHYXGXS_BLK1_LINKr(_unit, _phy_ctrl, _val, _mask) \ 320 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x011, \ 321 (_val), (_mask)) 322 323 /* testRx (Addr 0x8012) */ 324 #define READ_PHYXGXS_BLK1_TESTRXr(_unit, _phy_ctrl, _val) \ 325 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x012, (_val)) 326 #define WRITE_PHYXGXS_BLK1_TESTRXr(_unit, _phy_ctrl, _val) \ 327 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x012,(_val)) 328 #define MODIFY_PHYXGXS_BLK1_TESTRXr(_unit, _phy_ctrl, _val, _mask) \ 329 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x012, \ 330 (_val), (_mask)) 331 332 /* testTx (Addr 0x8013) */ 333 334 /* testXg (Addr 0x8014) */ 335 336 /* Reserved (Addr 0x8015) */ 337 338 /* laneCtrl1 (Addr 0x8016) */ 339 #define READ_PHYXGXS_BLK1_LANE_CTRL1r(_unit, _phy_ctrl, _val) \ 340 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x16, (_val)) 341 #define WRITE_PHYXGXS_BLK1_LANE_CTRL1r(_unit, _phy_ctrl, _val) \ 342 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x16, (_val)) 343 #define MODIFY_PHYXGXS_BLK1_LANE_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 344 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x16, \ 345 (_val), (_mask)) 346 347 /* laneCtrl2 (Addr 0x8017) */ 348 #define READ_PHYXGXS_BLK1_LANE_CTRL2r(_unit, _phy_ctrl, _val) \ 349 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x17, (_val)) 350 #define WRITE_PHYXGXS_BLK1_LANE_CTRL2r(_unit, _phy_ctrl, _val) \ 351 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x17, (_val)) 352 #define MODIFY_PHYXGXS_BLK1_LANE_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 353 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x17, \ 354 (_val), (_mask)) 355 356 /* laneCtrl3 (Addr 0x8018) */ 357 #define READ_PHYXGXS_BLK1_LANE_CTRL3r(_unit, _phy_ctrl, _val) \ 358 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x18, (_val)) 359 #define WRITE_PHYXGXS_BLK1_LANE_CTRL3r(_unit, _phy_ctrl, _val) \ 360 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x18, (_val)) 361 #define MODIFY_PHYXGXS_BLK1_LANE_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 362 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x18, \ 363 (_val), (_mask)) 364 365 /* lanePrbs (Addr 0x8019) */ 366 367 /* laneTest (Addr 0x801A) */ 368 #define READ_PHYXGXS_BLK1_LANE_TESTr(_unit, _phy_ctrl, _val) \ 369 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8010, 0x1A, (_val)) 370 #define WRITE_PHYXGXS_BLK1_LANE_TESTr(_unit, _phy_ctrl, _val) \ 371 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8010, 0x1A, (_val)) 372 #define MODIFY_PHYXGXS_BLK1_LANE_TESTr(_unit, _phy_ctrl, _val, _mask) \ 373 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8010, 0x1A, \ 374 (_val), (_mask)) 375 376 /* IssRevnt (Addr 0x801B) */ 377 378 /* dskevnt (Addr 0x801C) */ 379 380 /* Aerrevnt (Addr 0x801D) */ 381 382 /* chcmpevnt (Addr 0x801E) */ 383 384 385 /****************************/ 386 /* 10G Tx BERT (blk 0x8020) */ 387 /****************************/ 388 389 390 /****************************/ 391 /* 10G Rx BERT (blk 0x8030) */ 392 /****************************/ 393 394 /*************************/ 395 /* BcstBert (blk 0x8040) */ 396 /*************************/ 397 398 /********************/ 399 /* PLL (blk 0x8050) */ 400 /********************/ 401 402 /* PLL STATUS (Addr 0x8050) */ 403 #define READ_PHYXGXS_PLL_STATr(_unit, _phy_ctrl, _val) \ 404 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x10, (_val)) 405 #define WRITE_PHYXGXS_PLL_STATr(_unit, _phy_ctrl, _val) \ 406 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x10, (_val)) 407 #define MODIFY_PHYXGXS_PLL_STATr(_unit, _phy_ctrl, _val, _mask) \ 408 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x10, \ 409 (_val), (_mask)) 410 411 /* PLL Control (Addr 0x8051) */ 412 #define READ_PHYXGXS_PLL_CTRLr(_unit, _phy_ctrl, _val) \ 413 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x11, (_val)) 414 #define WRITE_PHYXGXS_PLL_CTRLr(_unit, _phy_ctrl, _val) \ 415 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x11, (_val)) 416 #define MODIFY_PHYXGXS_PLL_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 417 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x11, \ 418 (_val), (_mask)) 419 420 /* PLL Timer 1 (Addr 0x8052) */ 421 #define READ_PHYXGXS_PLL_TIMER1r(_unit, _phy_ctrl, _val) \ 422 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x12, (_val)) 423 #define WRITE_PHYXGXS_PLL_TIMER1r(_unit, _phy_ctrl, _val) \ 424 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x12, (_val)) 425 #define MODIFY_PHYXGXS_PLL_TIMER1r(_unit, _phy_ctrl, _val, _mask) \ 426 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x12, \ 427 (_val), (_mask)) 428 429 /* PLL Timer 2 (Addr 0x8053) */ 430 #define READ_PHYXGXS_PLL_TIMER2r(_unit, _phy_ctrl, _val) \ 431 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x13, (_val)) 432 #define WRITE_PHYXGXS_PLL_TIMER2r(_unit, _phy_ctrl, _val) \ 433 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x13, (_val)) 434 #define MODIFY_PHYXGXS_PLL_TIMER2r(_unit, _phy_ctrl, _val, _mask) \ 435 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x13, \ 436 (_val), (_mask)) 437 438 /* PLL Timer 3 (Addr 0x8054) */ 439 #define READ_PHYXGXS_PLL_TIMER3r(_unit, _phy_ctrl, _val) \ 440 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x14, (_val)) 441 #define WRITE_PHYXGXS_PLL_TIMER3r(_unit, _phy_ctrl, _val) \ 442 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x14, (_val)) 443 #define MODIFY_PHYXGXS_PLL_TIMER3r(_unit, _phy_ctrl, _val, _mask) \ 444 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x14, \ 445 (_val), (_mask)) 446 447 /* CAP Control (Addr 0x8055) */ 448 #define READ_PHYXGXS_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val) \ 449 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x15, (_val)) 450 #define WRITE_PHYXGXS_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val) \ 451 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x15, (_val)) 452 #define MODIFY_PHYXGXS_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 453 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x15, \ 454 (_val), (_mask)) 455 456 /* AMP Control (Addr 0x8056) */ 457 #define READ_PHYXGXS_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val) \ 458 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x16, (_val)) 459 #define WRITE_PHYXGXS_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val) \ 460 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x16, (_val)) 461 #define MODIFY_PHYXGXS_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 462 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x16, \ 463 (_val), (_mask)) 464 465 /* Freq Det Counter (Addr 0x8057) */ 466 #define READ_PHYXGXS_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val) \ 467 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x17, (_val)) 468 #define WRITE_PHYXGXS_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val) \ 469 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x17, (_val)) 470 #define MODIFY_PHYXGXS_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 471 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x17, \ 472 (_val), (_mask)) 473 474 /* PLL Astatus 1 (Addr 0x8058) */ 475 #define READ_PHYXGXS_PLL_ASTAT1r(_unit, _phy_ctrl, _val) \ 476 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x18, (_val)) 477 #define WRITE_PHYXGXS_PLL_ASTAT1r(_unit, _phy_ctrl, _val) \ 478 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x18, (_val)) 479 #define MODIFY_PHYXGXS_PLL_ASTAT1r(_unit, _phy_ctrl, _val, _mask) \ 480 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x18, \ 481 (_val), (_mask)) 482 483 /* PLL Astatus 2 (Addr 0x8059) */ 484 #define READ_PHYXGXS_PLL_ASTAT2r(_unit, _phy_ctrl, _val) \ 485 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x19, (_val)) 486 #define WRITE_PHYXGXS_PLL_ASTAT2r(_unit, _phy_ctrl, _val) \ 487 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x19, (_val)) 488 #define MODIFY_PHYXGXS_PLL_ASTAT2r(_unit, _phy_ctrl, _val, _mask) \ 489 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x19, \ 490 (_val), (_mask)) 491 492 /* PLL Clock Gen (Addr 0x805A) */ 493 #define READ_PHYXGXS_PLL_CLK_GENr(_unit, _phy_ctrl, _val) \ 494 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1A, (_val)) 495 #define WRITE_PHYXGXS_PLL_CLK_GENr(_unit, _phy_ctrl, _val) \ 496 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1A, (_val)) 497 #define MODIFY_PHYXGXS_PLL_CLK_GENr(_unit, _phy_ctrl, _val, _mask) \ 498 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1A, \ 499 (_val), (_mask)) 500 501 /* PLL Ndiv (Addr 0x805B) */ 502 #define READ_PHYXGXS_PLL_NDIVr(_unit, _phy_ctrl, _val) \ 503 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1B, (_val)) 504 #define WRITE_PHYXGXS_PLL_NDIVr(_unit, _phy_ctrl, _val) \ 505 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1B, (_val)) 506 #define MODIFY_PHYXGXS_PLL_NDIVr(_unit, _phy_ctrl, _val, _mask) \ 507 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1B, \ 508 (_val), (_mask)) 509 510 /* PLL Bglqp (Addr 0x805C) */ 511 #define READ_PHYXGXS_PLL_BGLQPr(_unit, _phy_ctrl, _val) \ 512 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1C, (_val)) 513 #define WRITE_PHYXGXS_PLL_BGLQP(_unit, _phy_ctrl, _val) \ 514 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1C, (_val)) 515 #define MODIFY_PHYXGXS_PLL_BGLQPr(_unit, _phy_ctrl, _val, _mask) \ 516 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1C, \ 517 (_val), (_mask)) 518 519 /* PLL Test Kvh (Addr 0x805D) */ 520 #define READ_PHYXGXS_PLL_TEST_KVHr(_unit, _phy_ctrl, _val) \ 521 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1D, (_val)) 522 #define WRITE_PHYXGXS_PLL_TEST_KVHr(_unit, _phy_ctrl, _val) \ 523 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1D, (_val)) 524 #define MODIFY_PHYXGXS_PLL_TEST_KVHr(_unit, _phy_ctrl, _val, _mask) \ 525 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1D, \ 526 (_val), (_mask)) 527 528 /* PLL AControl 5 (Addr 0x805E) */ 529 #define READ_PHYXGXS_PLL_ACTRL5r(_unit, _phy_ctrl, _val) \ 530 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1E, (_val)) 531 #define WRITE_PHYXGXS_PLL_ACTRL5r(_unit, _phy_ctrl, _val) \ 532 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1E, (_val)) 533 #define MODIFY_PHYXGXS_PLL_ACTRL5r(_unit, _phy_ctrl, _val, _mask) \ 534 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8050, 0x1E, \ 535 (_val), (_mask)) 536 537 538 /********************/ 539 /* TX0 (blk 0x8060) */ 540 /********************/ 541 542 /********************/ 543 /* TX1 (blk 0x8070) */ 544 /********************/ 545 546 547 /********************/ 548 /* TX2 (blk 0x8080) */ 549 /********************/ 550 551 552 /********************/ 553 /* TX3 (blk 0x8090) */ 554 /********************/ 555 556 557 /********************/ 558 /* TX All (blk 0x80A0) */ 559 /********************/ 560 /* Tx AStatus 0 (Addr 0x80A0) */ 561 /* Tx AControl 0 (Addr 0x80A1) */ 562 #define READ_PHYXGXS_TXALL_ACTRL0r(_unit, _phy_ctrl, _val) \ 563 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x11, (_val)) 564 #define WRITE_PHYXGXS_TXALL_ACTRL0r(_unit, _phy_ctrl, _val) \ 565 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x11, (_val)) 566 #define MODIFY_PHYXGXS_TXALL_ACTRL0r(_unit, _phy_ctrl, _val, _mask) \ 567 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x11, \ 568 (_val), (_mask)) 569 570 /* Tx mdata 0 (Addr 0x80A2) */ 571 /* Tx mdata 1 (Addr 0x80A3) */ 572 /* Tx AStatus 1 (Addr 0x80A4) */ 573 /* Tx BgVcm (Addr 0x80A5) */ 574 /* Tx Ibuff 1T2T (Addr 0x80A6) */ 575 576 /* Tx Driver (Addr 0x80A7) */ 577 #define READ_PHYXGXS_TXALL_DRIVERr(_unit, _phy_ctrl, _val) \ 578 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x17, (_val)) 579 #define WRITE_PHYXGXS_TXALL_DRIVERr(_unit, _phy_ctrl, _val) \ 580 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x17, (_val)) 581 #define MODIFY_PHYXGXS_TXALL_DRIVERr(_unit, _phy_ctrl, _val, _mask) \ 582 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80A0, 0x17, \ 583 (_val), (_mask)) 584 585 /* Reserved (Addr 0x80A8 - 0x80AE) */ 586 587 /********************/ 588 /* RX0 (blk 0x80B0) */ 589 /********************/ 590 591 592 /********************/ 593 /* RX1 (blk 0x80C0) */ 594 /********************/ 595 596 597 /********************/ 598 /* RX2 (blk 0x80D0) */ 599 /********************/ 600 601 602 /********************/ 603 /* RX3 (blk 0x80E0) */ 604 /********************/ 605 606 607 /***********************/ 608 /* RX All (blk 0x80F0) */ 609 /***********************/ 610 /* Rx Status (Address 0x80F0) */ 611 #define READ_PHYXGXS_RXALL_STATr(_unit, _phy_ctrl, _val) \ 612 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x10, (_val)) 613 #define WRITE_PHYXGXS_RXALL_STATr(_unit, _phy_ctrl, _val) \ 614 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x10, (_val)) 615 #define MODIFY_PHYXGXS_RXALL_STATr(_unit, _phy_ctrl, _val, _mask) \ 616 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x10, \ 617 (_val), (_mask)) 618 619 /* Rx Control (Address 0x80F1) */ 620 #define READ_PHYXGXS_RXALL_CTRLr(_unit, _phy_ctrl, _val) \ 621 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x11, (_val)) 622 #define WRITE_PHYXGXS_RXALL_CTRLr(_unit, _phy_ctrl, _val) \ 623 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x11, (_val)) 624 #define MODIFY_PHYXGXS_RXALL_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 625 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x11, \ 626 (_val), (_mask)) 627 628 /* Rx Timer 1 (Address 0x80F2) */ 629 #define READ_PHYXGXS_RXALL_TIMER1r(_unit, _phy_ctrl, _val) \ 630 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x12, (_val)) 631 #define WRITE_PHYXGXS_RXALL_TIMER1r(_unit, _phy_ctrl, _val) \ 632 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x12, (_val)) 633 #define MODIFY_PHYXGXS_RXALL_TIMER1r(_unit, _phy_ctrl, _val, _mask) \ 634 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x12, \ 635 (_val), (_mask)) 636 637 /* Rx Timer 2 (Address 0x80F3) */ 638 #define READ_PHYXGXS_RXALL_TIMER2r(_unit, _phy_ctrl, _val) \ 639 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x13, (_val)) 640 #define WRITE_PHYXGXS_RXALL_TIMER2r(_unit, _phy_ctrl, _val) \ 641 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x13, (_val)) 642 #define MODIFY_PHYXGXS_RXALL_TIMER2r(_unit, _phy_ctrl, _val, _mask) \ 643 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x13, \ 644 (_val), (_mask)) 645 646 /* Rx SigDet (Address 0x80F4) */ 647 #define READ_PHYXGXS_RXALL_SIG_DETr(_unit, _phy_ctrl, _val) \ 648 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x14, (_val)) 649 #define WRITE_PHYXGXS_RXALL_SIG_DETr(_unit, _phy_ctrl, _val) \ 650 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x14, (_val)) 651 #define MODIFY_PHYXGXS_RXALL_SIG_DETr(_unit, _phy_ctrl, _val, _mask) \ 652 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x14, \ 653 (_val), (_mask)) 654 655 /* Rx CdrPhase (Address 0x80F5) */ 656 #define READ_PHYXGXS_RXALL_CDR_PHASEr(_unit, _phy_ctrl, _val) \ 657 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x15, (_val)) 658 #define WRITE_PHYXGXS_RXALL_CDR_PHASEr(_unit, _phy_ctrl, _val) \ 659 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x15, (_val)) 660 #define MODIFY_PHYXGXS_RXALL_CDR_PHASEr(_unit, _phy_ctrl, _val, _mask) \ 661 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x15, \ 662 (_val), (_mask)) 663 664 /* Rx CdrFreq (Address 0x80F6) */ 665 #define READ_PHYXGXS_RXALL_CDR_FREQr(_unit, _phy_ctrl, _val) \ 666 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x16, (_val)) 667 #define WRITE_PHYXGXS_RXALL_CDR_FREQr(_unit, _phy_ctrl, _val) \ 668 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x16, (_val)) 669 #define MODIFY_PHYXGXS_RXALL_CDR_FREQr(_unit, _phy_ctrl, _val, _mask) \ 670 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x16, \ 671 (_val), (_mask)) 672 673 /* Rx EqConfig (Address 0x80F7) */ 674 #define READ_PHYXGXS_RXALL_EQ_CONFIGr(_unit, _phy_ctrl, _val) \ 675 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x17, (_val)) 676 #define WRITE_PHYXGXS_RXALL_EQ_CONFIGr(_unit, _phy_ctrl, _val) \ 677 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x17, (_val)) 678 #define MODIFY_PHYXGXS_RXALL_EQ_CONFIGr(_unit, _phy_ctrl, _val, _mask) \ 679 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x17, \ 680 (_val), (_mask)) 681 682 /* Rx EqForce (Address 0x80F8) */ 683 #define READ_PHYXGXS_RXALL_EQ_FORCEr(_unit, _phy_ctrl, _val) \ 684 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x18, (_val)) 685 #define WRITE_PHYXGXS_RXALL_EQ_FORCEr(_unit, _phy_ctrl, _val) \ 686 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x18, (_val)) 687 #define MODIFY_PHYXGXS_RXALL_EQ_FORCEr(_unit, _phy_ctrl, _val, _mask) \ 688 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x18, \ 689 (_val), (_mask)) 690 691 /* Rx Control 1G (Address 0x80F9) */ 692 #define READ_PHYXGXS_RXALL_CTRL_1Gr(_unit, _phy_ctrl, _val) \ 693 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x19, (_val)) 694 #define WRITE_PHYXGXS_RXALL_CTRL_1Gr(_unit, _phy_ctrl, _val) \ 695 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x19, (_val)) 696 #define MODIFY_PHYXGXS_RXALL_CTRL_1Gr(_unit, _phy_ctrl, _val, _mask) \ 697 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x19, \ 698 (_val), (_mask)) 699 700 /* Rx Control PCIE (Address 0x80FA) */ 701 #define READ_PHYXGXS_RXALL_CTRL_PCIEr(_unit, _phy_ctrl, _val) \ 702 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1A, (_val)) 703 #define WRITE_PHYXGXS_RXALL_CTRL_PCIEr(_unit, _phy_ctrl, _val) \ 704 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1A, (_val)) 705 #define MODIFY_PHYXGXS_RXALL_CTRL_PCIEr(_unit, _phy_ctrl, _val, _mask) \ 706 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1A, \ 707 (_val), (_mask)) 708 709 /* Rx Astatus (Address 0x80FB) */ 710 #define READ_PHYXGXS_RXALL_ASTATr(_unit, _phy_ctrl, _val) \ 711 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1B, (_val)) 712 #define WRITE_PHYXGXS_RXALL_ASTATr(_unit, _phy_ctrl, _val) \ 713 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1B, (_val)) 714 #define MODIFY_PHYXGXS_RXALL_ASTATr(_unit, _phy_ctrl, _val, _mask) \ 715 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1B, \ 716 (_val), (_mask)) 717 718 /* Rx Eq Boost (Address 0x80FC) */ 719 #define READ_PHYXGXS_RXALL_EQ_BOOSTr(_unit, _phy_ctrl, _val) \ 720 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1C, (_val)) 721 #define WRITE_PHYXGXS_RXALL_EQ_BOOSTr(_unit, _phy_ctrl, _val) \ 722 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1C, (_val)) 723 #define MODIFY_PHYXGXS_RXALL_EQ_BOOSTr(_unit, _phy_ctrl, _val, _mask) \ 724 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1C, \ 725 (_val), (_mask)) 726 727 /* Rx lb Data Eq (Address 0x80FD) */ 728 #define READ_PHYXGXS_RXALL_LB_DATA_EQr(_unit, _phy_ctrl, _val) \ 729 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1D, (_val)) 730 #define WRITE_PHYXGXS_RXALL_LB_DATA_EQr(_unit, _phy_ctrl, _val) \ 731 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1D, (_val)) 732 #define MODIFY_PHYXGXS_RXALL_LB_DATA_EQr(_unit, _phy_ctrl, _val, _mask) \ 733 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1D, \ 734 (_val), (_mask)) 735 736 /* Rx lb ADC Buff (Address 0x80FE) */ 737 #define READ_PHYXGXS_RXALL_LB_ADC_BUFFr(_unit, _phy_ctrl, _val) \ 738 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1E, (_val)) 739 #define WRITE_PHYXGXS_RXALL_LB_ADC_BUFFr(_unit, _phy_ctrl, _val) \ 740 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1E, (_val)) 741 #define MODIFY_PHYXGXS_RXALL_LB_ADC_BUFFr(_unit, _phy_ctrl, _val, _mask) \ 742 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x80F0, 0x1E, \ 743 (_val), (_mask)) 744 745 /*****************************/ 746 /* XGXS Block 2 (blk 0x8100) */ 747 /*****************************/ 748 /* Rx Lane Swap (Addr 0x8100) */ 749 /* Tx Lane Swap (Addr 0x8101) */ 750 #define READ_PHYXGXS_BLK2_TX_LANE_SWAPr(_unit, _phy_ctrl, _val) \ 751 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8100, 0x11, (_val)) 752 #define WRITE_PHYXGXS_BLK2_TX_LANE_SWAPr(_unit, _phy_ctrl, _val) \ 753 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8100, 0x11, (_val)) 754 #define MODIFY_PHYXGXS_BLK2_TX_LANE_SWAPr(_unit, _phy_ctrl, _val, _mask) \ 755 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8100, 0x11, \ 756 (_val), (_mask)) 757 758 /* QsetLns01 (Addr 0x8102) */ 759 /* QsetLns23 (Addr 0x8103) */ 760 /* Unicore Mode 10G (Addr 0x8104) */ 761 /* Reserved (Addr 0x8105 - 0x810E) */ 762 763 /*****************************/ 764 /* In Band MDIO (blk 0x8110) */ 765 /*****************************/ 766 767 768 /**************************/ 769 /* GP Status (blk 0x8120) */ 770 /**************************/ 771 772 773 /*******************************/ 774 /* SerDes Digital (blk 0x8300) */ 775 /*******************************/ 776 777 /* 1000XControl1 (Addr 0x8300) */ 778 #define READ_PHYXGXS_SERDES_DIGITAL_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 779 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x10, (_val)) 780 #define WRITE_PHYXGXS_SERDES_DIGITAL_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 781 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x10, (_val)) 782 #define MODIFY_PHYXGXS_SERDES_DIGITAL_1000X_CTRL1r(_unit, _phy_ctrl, \ 783 _val, _mask) \ 784 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x10, \ 785 (_val), (_mask)) 786 787 /* 1000XControl2 (Addr 0x8301) */ 788 #define READ_PHYXGXS_SERDES_DIGITAL_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 789 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x11, (_val)) 790 #define WRITE_PHYXGXS_SERDES_DIGITAL_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 791 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x11, (_val)) 792 #define MODIFY_PHYXGXS_SERDES_DIGITAL_1000X_CTRL2r(_unit, _phy_ctrl, \ 793 _val, _mask) \ 794 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x11, \ 795 (_val), (_mask)) 796 797 /* 1000XControl3 (Addr 0x8302) */ 798 #define READ_PHYXGXS_SERDES_DIGITAL_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 799 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x12, (_val)) 800 #define WRITE_PHYXGXS_SERDES_DIGITAL_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 801 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x12, (_val)) 802 #define MODIFY_PHYXGXS_SERDES_DIGITAL_1000X_CTRL3r(_unit, _phy_ctrl, \ 803 _val, _mask) \ 804 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x12, \ 805 (_val), (_mask)) 806 807 /* 1000XControl4 (Addr 0x8303) */ 808 #define READ_PHYXGXS_SERDES_DIGITAL_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 809 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x13, (_val)) 810 #define WRITE_PHYXGXS_SERDES_DIGITAL_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 811 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x13, (_val)) 812 #define MODIFY_PHYXGXS_SERDES_DIGITAL_1000X_CTRL4r(_unit, _phy_ctrl, \ 813 _val, _mask) \ 814 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x13, \ 815 (_val), (_mask)) 816 817 /* 1000XStatus1 (Addr 0x8304) */ 818 #define READ_PHYXGXS_SERDES_DIGITAL_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 819 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x14, (_val)) 820 #define WRITE_PHYXGXS_SERDES_DIGITAL_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 821 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x14, (_val)) 822 #define MODIFY_PHYXGXS_SERDES_DIGITAL_1000X_STAT1r(_unit, _phy_ctrl, \ 823 _val, _mask) \ 824 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x14, \ 825 (_val), (_mask)) 826 827 /* 1000XStatus2 (Addr 0x8305) */ 828 #define READ_PHYXGXS_SERDES_DIGITAL_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 829 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x15, (_val)) 830 #define WRITE_PHYXGXS_SERDES_DIGITAL_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 831 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x15, (_val)) 832 #define MODIFY_PHYXGXS_SERDES_DIGITAL_1000X_STAT2r(_unit, _phy_ctrl, \ 833 _val, _mask) \ 834 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x15, \ 835 (_val), (_mask)) 836 837 /* 1000XStatus3 (Addr 0x8306) */ 838 #define READ_PHYXGXS_SERDES_DIGITAL_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 839 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x16, (_val)) 840 #define WRITE_PHYXGXS_SERDES_DIGITAL_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 841 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x16, (_val)) 842 #define MODIFY_PHYXGXS_SERDES_DIGITAL_1000X_STAT3r(_unit, _phy_ctrl, \ 843 _val, _mask) \ 844 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x16, \ 845 (_val), (_mask)) 846 847 /* CrcErr_RxPktCntr (Addr 0x8307) */ 848 849 /* Misc1 (Addr 0x8308) */ 850 #define READ_PHYXGXS_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val) \ 851 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x18, (_val)) 852 #define WRITE_PHYXGXS_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val) \ 853 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x18, (_val)) 854 #define MODIFY_PHYXGXS_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val, _mask) \ 855 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x18, \ 856 (_val), (_mask)) 857 858 /* Misc2 (Addr 0x8309) */ 859 #define READ_PHYXGXS_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val) \ 860 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8300, 0x19, (_val)) 861 #define WRITE_PHYXGXS_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val) \ 862 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8300, 0x19, (_val)) 863 #define MODIFY_PHYXGXS_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val, _mask) \ 864 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, 0x19, \ 865 (_val), (_mask)) 866 867 /* PatGenControl (Addr 0x830A) */ 868 /* PatGenControl (Addr 0x830B) */ 869 /* TestMode (Addr 0x830C) */ 870 /* TxPktCnt (Addr 0x830D) */ 871 /* RxPktCnt (Addr 0x830E) */ 872 873 /*********************/ 874 /* Test (blk 0x8310) */ 875 /*********************/ 876 877 /************************/ 878 /* Over 1G (blk 0x8320) */ 879 /************************/ 880 /* digctrl_3_0 (Addr 0x8320) */ 881 /* digctrl_3_1 (Addr 0x8321) */ 882 /* digctrl_3_2 (Addr 0x8322) */ 883 /* digctrl_3_3 (Addr 0x8323) */ 884 /* digctrl_3_4 (Addr 0x8324) */ 885 /* digctrl_3_5 (Addr 0x8325) */ 886 /* digctrl_3_6 (Addr 0x8326) */ 887 /* TPOUT 1 (Addr 0x8327) */ 888 /* TPOUT 2 (Addr 0x8328) */ 889 890 /* UP 1 (Addr 0x8329) */ 891 #define READ_PHYXGXS_OVER1G_UP1r(_unit, _phy_ctrl, _val) \ 892 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8320, 0x19, (_val)) 893 #define WRITE_PHYXGXS_OVER1G_UP1r(_unit, _phy_ctrl, _val) \ 894 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8320, 0x19, (_val)) 895 #define MODIFY_PHYXGXS_OVER1G_UP1r(_unit, _phy_ctrl, _val, _mask) \ 896 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8320, 0x19, \ 897 (_val), (_mask)) 898 899 /* UP 2 (Addr 0x832A) */ 900 /* UP 3 (Addr 0x832B) */ 901 902 /* LP UP 1 (Addr 0x832C) */ 903 #define READ_PHYXGXS_OVER1G_LP_UP1r(_unit, _phy_ctrl, _val) \ 904 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8320, 0x1C, (_val)) 905 #define WRITE_PHYXGXS_OVER1G_LP_UP1r(_unit, _phy_ctrl, _val) \ 906 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8320, 0x1C, (_val)) 907 #define MODIFY_PHYXGXS_OVER1G_LP_UP1r(_unit, _phy_ctrl, _val, _mask) \ 908 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8320, 0x1C, \ 909 (_val), (_mask)) 910 911 /* LP UP 2 (Addr 0x832D) */ 912 /* LP UP 3 (Addr 0x832E) */ 913 914 /***************************/ 915 /* Remote PHY (blk 0x8330) */ 916 /***************************/ 917 918 /************************************/ 919 /* 10G Parallel Detect (blk 0x8340) */ 920 /************************************/ 921 /* parDet10GStatus (Addr 0x8340) */ 922 #define READ_PHYXGXS_PARDET10G_STATr(_unit, _phy_ctrl, _val) \ 923 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x10, (_val)) 924 #define WRITE_PHYXGXS_PARDET10G_STATr(_unit, _phy_ctrl, _val) \ 925 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x10, (_val)) 926 #define MODIFY_PHYXGXS_PARDET10G_STATr(_unit, _phy_ctrl, _val, _mask) \ 927 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x10, \ 928 (_val), (_mask)) 929 930 /* parDet10GControl (Addr 0x8341) */ 931 #define READ_PHYXGXS_PARDET10G_CTRLr(_unit, _phy_ctrl, _val) \ 932 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x11, (_val)) 933 #define WRITE_PHYXGXS_PARDET10G_CTRLr(_unit, _phy_ctrl, _val) \ 934 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x11, (_val)) 935 #define MODIFY_PHYXGXS_PARDET10G_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 936 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x11, \ 937 (_val), (_mask)) 938 939 /* parDet10GSigDet (Addr 0x8342) */ 940 #define READ_PHYXGXS_PARDET10G_SIGDETr(_unit, _phy_ctrl, _val) \ 941 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x12, (_val)) 942 #define WRITE_PHYXGXS_PARDET10G_SIGDETr(_unit, _phy_ctrl, _val) \ 943 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x12, (_val)) 944 #define MODIFY_PHYXGXS_PARDET10G_SIGDETr(_unit, _phy_ctrl, _val, _mask) \ 945 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x12, \ 946 (_val), (_mask)) 947 948 /* parDet10GLink (Addr 0x8343) */ 949 #define READ_PHYXGXS_PARDET10G_LINKr(_unit, _phy_ctrl, _val) \ 950 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x13, (_val)) 951 #define WRITE_PHYXGXS_PARDET10G_LINKr(_unit, _phy_ctrl, _val) \ 952 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x13, (_val)) 953 #define MODIFY_PHYXGXS_PARDET10G_LINKr(_unit, _phy_ctrl, _val, _mask) \ 954 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x13, \ 955 (_val), (_mask)) 956 957 /* parDet10GLosLink (Addr 0x8344) */ 958 #define READ_PHYXGXS_PARDET10G_LOSLINKr(_unit, _phy_ctrl, _val) \ 959 PHYXGXS_REG_READ((_unit), (_phy_ctrl), 0x00, 0x8340, 0x14, (_val)) 960 #define WRITE_PHYXGXS_PARDET10G_LOSLINKr(_unit, _phy_ctrl, _val) \ 961 PHYXGXS_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x8340, 0x14, (_val)) 962 #define MODIFY_PHYXGXS_PARDET10G_LOSLINKr(_unit, _phy_ctrl, _val, _mask) \ 963 PHYXGXS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8340, 0x14, \ 964 (_val), (_mask)) 965 966 /* Reserved (Addr 0x8345 - 0x834E) */ 967 968 /******************************/ 969 /* BAM Next Page (blk 0x8350) */ 970 /******************************/ 971 972 #endif /* _PHY_XGXS_H_ */