openbcm

Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM
git clone git://git.finwo.net/mirror/broadcom/openbcm
Log | Files | Refs | README

wcmod_phyreg.h (2929B)

      1 /*
      2  * 
      3  *
      4  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      5  * 
      6  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      7  */
      8 #include <sal/types.h>
      9 /* FILE: wcmod_phyreg.h */
     10 /* DATE: Mon Jun 13 10:28:56 PDT 2011 */
     11 
     12 
     13 /*!
     14 \file wcmod_phyreg.h Declares verilog interface functions.
     15 This file contains declarations of functions that are necessary to 
     16 hook up WCMod to various verilog platforms. The drivers of WCMod are
     17 hooked to verilog tasks as a first level interface to the actual drivers in the 
     18 verilog testbench. These 'C' functions and verilog tasks are attached via 
     19 a mechanism called 'DPI' (direct programming interface) supported by all
     20 verilog simulators.  Note that C platforms need no special attachments.
     21 */
     22 
     23 #ifndef   _WCMOD_PHYREG_H_
     24 #define   _WCMOD_PHYREG_H_
     25 
     26 #include "wcmod_main.h"  
     27 #include "wcmod_defines.h"
     28 
     29 #if defined (_MDK_WCMOD_)
     30 extern int cdk_xgs_miim_read(int u, uint32_t pa, uint32_t ra, uint32_t *val);
     31 extern int cdk_xgs_miim_write(int u, uint32_t pa, uint32_t ra, uint32_t val);
     32 
     33 #endif
     34 
     35 #ifndef __KERNEL__
     36 #if defined (_DV_TRIUMPH3) || (_DV_ODYSSEY) || (_DV_NATIVE)
     37 /* normally the externs are generated by irun/vcs -dpiheader. */
     38 /* Manually typing this in to reduce header files. */
     39 #ifdef CADENCE
     40 /* svdpi.h to be conditional to cadence (or irun). vcs does not have this. */
     41 #include "svdpi.h"
     42 #endif /* CADENCE */
     43 
     44 extern void dv_reg_cl45_read  (int ut,int pt,int pa,int ln,int ad,int *dt);
     45 extern void dv_reg_cl22_read  (int ut,int pt,int pa,int ln,int ad,int *dt);
     46 
     47 extern void dv_reg_cl45_write (int ut,int pt,int pa,int ln,int ad,int dt);
     48 extern void dv_reg_cl22_write (int ut,int pt,int pa,int ln,int ad,int dt);
     49 
     50 extern void dv_reg_cl45_modify(int ut,int pt,int pa,int ln,int ad,int dt,int m);
     51 extern void dv_reg_cl22_modify(int ut,int pt,int pa,int ln,int ad,int dt,int m);
     52 
     53 extern void dv_wait (int delay);
     54 
     55 extern void dv_slam_read_reg  (void *pi,  int a, int *d);
     56 extern void dv_slam_write_reg (void *pi, int addr, int d);
     57 extern void dv_slam_modify_reg(void *pi,int a,int d,int m);
     58 
     59 #endif /* triumph + odyssey + native */
     60 #endif
     61 
     62 extern int  wcmod_reg_aer_read  (uint32 u,wcmod_st* w,uint32 a,uint16 *d);
     63 extern int  wcmod_reg_aer_write (uint32 u,wcmod_st* w,uint32 a,uint16  d);
     64 extern int  wcmod_reg_aer_modify(uint32 u,wcmod_st* w,uint32 a,uint16 d,uint16 m);
     65 
     66 extern int  wcmod_cl22_read  (wcmod_st* ws,uint32 addr,uint16 *data);
     67 extern int  wcmod_cl22_write (wcmod_st* ws,uint32 addr,uint16 data);
     68 extern int  wcmod_cl45_read  (wcmod_st* ws,uint32 addr,uint16 *data);
     69 extern int  wcmod_cl45_write (wcmod_st* ws,uint32 addr,uint16 data);
     70 extern void wcmod_timeout_init(soc_timeout_t *to, uint32 usec, int min_polls);  
     71 extern int  wcmod_timeout_check(soc_timeout_t *to);  
     72 extern int  wcmod_regbit_set_wait_check(wcmod_st* w,int r,int b,int bt,int to); 
     73 #endif   /*  _WCMOD_PHYREG_H_ */