wcmod_extra.h (16678B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: wc40_extra.h 8 * Purpose: non-register Macro, data structures and function prototypes for WC driver. 9 */ 10 11 12 #ifndef WCMOD_EXTRA_H__ 13 #define WCMOD_EXTRA_H__ 14 15 /* 16 * wc40.h has definitions related to WC registers. It is automatically generated 17 * from RDB files. This file has all non-register Macro, data structures and 18 * function prototypes the WC driver. 19 */ 20 21 /* additional missed register definitions */ 22 23 #define WCMOD_XGXSBLK0_XGXSSTATUSr 0x8001 24 #define WCMOD_TX0_ANATXACONTROL0r 0x8061 25 #define WCMOD_RX0_ANARXCONTROLPCIr 0x80ba 26 #define WCMOD_COMBO_IEEE0_MIICNTLr 0xffe0 27 #define WCMOD_MICROBLK_DOWNLOAD_STATUSr 0xffc5 28 #define SERDESDIGITAL_FORCE_SPEED_dr_10G_XFI 0x25 29 #define SERDESDIGITAL_FORCE_SPEED_dr_10G_SFI 0x29 30 31 /* misc. */ 32 #define WCMOD_PLL_WAIT 400000 /* 400ms */ 33 #define WCMOD_AN_WAIT 400000 /* 400ms */ 34 #define TX_DRIVER_DFT_LN_CTRL 0x7fff 35 36 #define SERDES_ID0_MODEL_NUMBER_WARPCORE 0x9 37 #define WC_AER_BCST_OFS_STRAP 0x1ff 38 #define OVER1G_UP3_20GPLUS_MASK (DIGITAL3_UP3_DATARATE_25P45GX4_MASK | \ 39 DIGITAL3_UP3_DATARATE_21GX4_MASK | \ 40 DIGITAL3_UP3_DATARATE_31P5G_MASK | \ 41 DIGITAL3_UP3_DATARATE_40G_MASK | \ 42 DIGITAL3_UP3_LAST_MASK) 43 #define PLL_PLLACONTROL4_BIT12_MASK 0x1000 44 #define WCMOD_UCODE_MAX_LEN (32*1024) 45 #define NUM_LANES 4 46 #define MAX_NUM_LANES 24 47 48 /* no clock comp in HG combo mode */ 49 #define COMBO_HG_XGXS_nLQnCC \ 50 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQnCC << \ 51 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT) 52 #define COMBO_HG_XGXS_nCC \ 53 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXG_nCC << \ 54 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT) 55 56 /* no clock comp in XE combo mode */ 57 #define COMBO_XE_XGXG_nCC \ 58 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXG_nCC << \ 59 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT) 60 61 /* clock comp in HG combo mode */ 62 #define COMBO_HG_XGXS_nLQ \ 63 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQ << \ 64 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT) 65 66 /* clock comp in XE combo mode */ 67 #define COMBO_XE_XGXS \ 68 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS << \ 69 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT) 70 71 #define COMBO_CLOCK_COMP_DEFAULT (COMBO_HG_XGXS_nLQnCC | COMBO_XE_XGXG_nCC) 72 #define COMBO_CLOCK_COMP_MASK (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_MASK | \ 73 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_MASK) 74 #define IND_CLOCK_COMP_DEFAULT (COMBO_HG_XGXS_nLQnCC | COMBO_XE_XGXG_nCC) 75 #define IND_CLOCK_COMP_DEFAULT_REV_A (COMBO_HG_XGXS_nLQ | COMBO_XE_XGXS) 76 77 /* WC revision IDs */ 78 79 #define WCMOD_SERDES_ID0_REVID_A0 0x0000 80 #define WCMOD_SERDES_ID0_REVID_A1 0x0800 81 #define WCMOD_SERDES_ID0_REVID_A2 0x1000 82 #define WCMOD_SERDES_ID0_REVID_B0 0x4000 83 #define WCMOD_SERDES_ID0_REVID_C0 0x8000 84 #define WCMOD_SERDES_ID0_REVID_D0 0xc000 85 86 #define REV_VER_MASK (SERDESID_SERDESID0_REV_LETTER_MASK | \ 87 SERDESID_SERDESID0_REV_NUMBER_MASK) 88 #define WCMOD_REVID(_pc) \ 89 ((((WCMOD_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) 90 #define WCMOD_REVID_A0(_pc) \ 91 (((((WCMOD_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 92 WCMOD_SERDES_ID0_REVID_A0) 93 #define WCMOD_REVID_A1(_pc) \ 94 (((((WCMOD_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 95 WCMOD_SERDES_ID0_REVID_A1) 96 #define WCMOD_REVID_B0(_pc) \ 97 (((((WCMOD_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 98 WCMOD_SERDES_ID0_REVID_B0) 99 #define WCMOD_LINK_WAR_REVS(_pc) (WCMOD_REVID_A0(_pc) || WCMOD_REVID_A1(_pc)) 100 101 /* div16 and div33 clocks */ 102 103 #define CL72_MISC4_CTRL_DIV16_SHIFT 5 104 #define CL72_MISC4_CTRL_DIV33_SHIFT 3 105 #define CL72_MISC4_CTRL_DIV16_FIELD(_fd) ((_fd) << CL72_MISC4_CTRL_DIV16_SHIFT) 106 #define CL72_MISC4_CTRL_DIV33_FIELD(_fd) ((_fd) << CL72_MISC4_CTRL_DIV33_SHIFT) 107 #define CL72_MISC4_CTRL_DIV16_MASK (0xf << CL72_MISC4_CTRL_DIV16_SHIFT) 108 #define CL72_MISC4_CTRL_DIV33_MASK (0x3 << CL72_MISC4_CTRL_DIV33_SHIFT) 109 110 /* CL73 */ 111 112 #define CL73_AN_ADV_TECH_20G_KR2 (1 << 13) 113 #define CL73_AN_ADV_TECH_100G_CR10 (1 << 10) 114 #define CL73_AN_ADV_TECH_40G_CR4 (1 << 9) 115 #define CL73_AN_ADV_TECH_40G_KR4 (1 << 8) 116 #define CL73_AN_ADV_TECH_10G_KR (1 << 7) 117 #define CL73_AN_ADV_TECH_10G_KX4 (1 << 6) 118 #define CL73_AN_ADV_TECH_1G_KX (1 << 5) 119 #define CL73_AN_ADV_TECH_SPEEDS_MASK (0x3F << 5) 120 #define CL73_AN_ADV_PLUS_KR2_MASK (CL73_AN_ADV_TECH_SPEEDS_MASK | \ 121 CL73_AN_ADV_TECH_20G_KR2) 122 #define CL73_AN_ADV_PAUSE (1 << 10) 123 #define CL73_AN_ADV_ASYM_PAUSE (1 << 11) 124 125 /* VCO frequency ctrl */ 126 127 #define WCMOD_OS5_VCO_FREQ 0x7200 128 #define WCMOD_OS8_VCO_FERQ 0x7A00 129 #define WCMOD_TXCK_MASK 0x1E0 130 #define WCMOD_RXCK_OVERIDE_MASK (1 << 11) 131 #define WCMOD_TXCK_SHIFTER 5 132 133 /* WCMOD_CL73_KR2 is the HP cl73 KR2 autoneg mode. In this mode 134 * CL37,CL37BAM and CL73BAM is disabled. The autoneg is in software 135 * controlled mode. 136 */ 137 #define WCMOD_CL73_KR2_CUSTOM 4 138 #define WCMOD_CL73_KR2 3 139 #define WCMOD_CL73_WO_CL73BAM 2 140 #define WCMOD_CL73_AND_CL73BAM 1 141 142 #define WCMOD_CL37_WO_CL37BAM 2 143 #define WCMOD_CL37_AND_CL37BAM 1 144 /* lane swap functions in XGXSBLK2 are obsolete, use ones in XGXSBLK8 145 * i.e. define WCMOD_PCS_LANE_SWAP 146 */ 147 #define WCMOD_PCS_LANE_SWAP 148 #ifdef WCMOD_PCS_LANE_SWAP 149 /* For Tx lane swap 150 * bits 15-12 11-8 7-4 3-0 represents pma/pmd lane 3,2,1,0 151 * value in each field represents corresponding pcs lane number. 152 * the default map is pma/pmd lane3 maps to pcs lane3, pma lane2 153 * to pcs lane2 and so on. 154 * 155 * For Rx lane swap 156 * The same bit fields represents the pcs lane 3,2,1,0 157 * and the value corresponds the pma/pmd lane number. 158 */ 159 #define WCMOD_RX_LANE_MAP_DEFAULT 0x3210 160 #define WCMOD_TX_LANE_MAP_DEFAULT 0x3210 161 #else 162 #define WCMOD_RX_LANE_MAP_DEFAULT 0x0123 163 #define WCMOD_TX_LANE_MAP_DEFAULT 0x0123 164 #endif 165 166 /* Register lane access. fixed value, must not change */ 167 168 #define LANE0_ACCESS 1 169 #define LANE1_ACCESS 2 170 #define LANE2_ACCESS 3 171 #define LANE3_ACCESS 4 172 #define LANE_BCST 0xF 173 #define LANE_ACCESS_MASK 0xF 174 175 /* operation modes */ 176 177 #define CUSTOM1_MODE(_pc) ((_pc)->phy_mode == PHYCTRL_LANE_MODE_CUSTOM1) 178 #define CUSTOM_MODE(_pc) (((_pc)->phy_mode == PHYCTRL_LANE_MODE_CUSTOM) || \ 179 ((_pc)->phy_mode == PHYCTRL_LANE_MODE_CUSTOM_3p125MHZ)) 180 #define CUSTOMX_MODE(_pc) (CUSTOM_MODE(_pc) || CUSTOM1_MODE(_pc)) 181 #define IND_LANE_MODE(_mode) (((_mode)==xgxs_operationModes_IndLane_OS8) || \ 182 ((_mode)==xgxs_operationModes_IndLane_OS5)) 183 #define COMBO_LANE_MODE(_mode) ((_mode) == xgxs_operationModes_ComboCoreMode) 184 #define XENIA_MODE(_mode) ((_mode) == xgxs_operationModes_XGXS) 185 #define IS_DUAL_LANE_PORT(_pc) (((_pc)->phy_mode == PHYCTRL_DUAL_LANE_PORT) || \ 186 CUSTOM1_MODE(_pc)) 187 #define IS_MULTI_CORE_PORT(_pc) ((_pc)->phy_mode == PHYCTRL_MULTI_CORE_PORT) 188 189 #define DUAL_LANE_BCST_ENABLE(_pc) \ 190 do { \ 191 if (IS_DUAL_LANE_PORT(_pc)) { \ 192 DEV_CFG_PTR(_pc)->dxgxs = (_pc)->lane_num? 2 :1; \ 193 } \ 194 } while (0) 195 #define DUAL_LANE_BCST_DISABLE(_pc) \ 196 do { \ 197 if (IS_DUAL_LANE_PORT(_pc)) { \ 198 DEV_CFG_PTR(_pc)->dxgxs = 0; \ 199 } \ 200 } while (0) 201 #define AUTONEG_MODE_UNAVAIL(_pc) (CUSTOMX_MODE(_pc)) 202 203 #define WCMOD_MEM_ALLOC(_size,_name) sal_alloc(_size,_name) 204 #define WCMOD_MEM_SET(_dst,_val,_len) sal_memset(_dst,_val,_len) 205 #define WCMOD_UDELAY(_time) sal_udelay(_time) 206 #define WCMOD_USLEEP(_time) sal_usleep(_time) 207 208 #define FX100_CONTROL1_AUTODET_EN_MASK 4 209 #define WCMOD_IF_NULL (1 << SOC_PORT_IF_NULL) 210 #define WCMOD_IF_SR (1 << SOC_PORT_IF_SR) 211 #define WCMOD_IF_KR (1 << SOC_PORT_IF_KR) 212 #define WCMOD_IF_KR4 (1 << SOC_PORT_IF_KR4) 213 #define WCMOD_IF_CR (1 << SOC_PORT_IF_CR) 214 #define WCMOD_IF_CR4 (1 << SOC_PORT_IF_CR4) 215 #define WCMOD_IF_XFI (1 << SOC_PORT_IF_XFI) 216 #define WCMOD_IF_SFI (1 << SOC_PORT_IF_SFI) 217 #define WCMOD_IF_XLAUI (1 << SOC_PORT_IF_XLAUI) 218 #define WCMOD_IF_XGMII (1 << SOC_PORT_IF_XGMII) 219 #define WCMOD_IF_ILKN (1 << SOC_PORT_IF_ILKN) 220 #define WCMOD_40G_10G_INTF(_if) ((_if) == SOC_PORT_IF_KR4 || (_if) == SOC_PORT_IF_XLAUI || \ 221 (_if) == SOC_PORT_IF_CR4 || (_if) == SOC_PORT_IF_SR || \ 222 (_if) == SOC_PORT_IF_KR || (_if) == SOC_PORT_IF_CR || \ 223 (_if) == SOC_PORT_IF_XFI || (_if) == SOC_PORT_IF_SFI || \ 224 (_if) == SOC_PORT_IF_XGMII) 225 226 #define WCMOD_40G_10G_INTF_ALL (WCMOD_IF_KR4 | WCMOD_IF_XLAUI | WCMOD_IF_CR4 | WCMOD_IF_SR | \ 227 WCMOD_IF_KR | WCMOD_IF_CR | WCMOD_IF_XFI | WCMOD_IF_SFI| WCMOD_IF_XGMII) 228 229 #define WCMOD_UC_CTRL_OPT_PF_TEMP_COMP 0x8888 230 #define WCMOD_UC_CTRL_FORCE_OSDFE 0x4 231 #define WCMOD_UC_CTRL_CL72_WO_AN 0x7777 232 #define WCMOD_UC_CTRL_XLAUI 0x3333 233 #define WCMOD_UC_CTRL_SR4 0x1111 234 #define WCMOD_UC_CTRL_SFP_DAC 0x2 235 #define WCMOD_UC_CTRL_DEFAULT 0x0000 236 237 238 #define WCMOD_AN_WAIT_INTERVAL 1000000 /* 1 second */ 239 240 #define WCMOD_SP_TIME(_pc) \ 241 (DEV_CTRL_PTR(_pc)->lkwa.start_time) 242 #define WCMOD_SP_VALID(_pc) \ 243 (DEV_CTRL_PTR(_pc)->lkwa.state) 244 #define WCMOD_SP_CNT(_pc) \ 245 (DEV_CTRL_PTR(_pc)->lkwa.cnt) 246 247 #define WCMOD_SP_RECORD_TIME(_pc) \ 248 (DEV_CTRL_PTR(_pc)->lkwa.start_time) = sal_time_usecs() 249 #define WCMOD_SP_CNT_INC(_pc) \ 250 (DEV_CTRL_PTR(_pc)->lkwa.cnt)++ 251 #define WCMOD_SP_CNT_CLEAR(_pc) \ 252 (DEV_CTRL_PTR(_pc)->lkwa.cnt) = 0 253 #define WCMOD_SP_VALID_SET(_pc) \ 254 (DEV_CTRL_PTR(_pc)->lkwa.state) = TRUE 255 #define WCMOD_SP_VALID_RESET(_pc) \ 256 (DEV_CTRL_PTR(_pc)->lkwa.state) = FALSE 257 258 #define WCMOD_AN_TIME(_pc) \ 259 (DEV_CTRL_PTR(_pc)->an.start_time) 260 #define WCMOD_AN_VALID(_pc) \ 261 (DEV_CTRL_PTR(_pc)->an.state) 262 #define WCMOD_AN_RECORD_TIME(_pc) \ 263 (DEV_CTRL_PTR(_pc)->an.start_time) = sal_time_usecs() 264 #define WCMOD_AN_VALID_SET(_pc) \ 265 (DEV_CTRL_PTR(_pc)->an.state) = TRUE 266 #define WCMOD_AN_VALID_RESET(_pc) \ 267 (DEV_CTRL_PTR(_pc)->an.state) = FALSE 268 #define WCMOD_AN_CHECK_TIMEOUT(_pc) \ 269 ((uint32)SAL_USECS_SUB(sal_time_usecs(), WCMOD_AN_TIME((_pc))) \ 270 >= WCMOD_AN_WAIT_INTERVAL) 271 #define WCMOD_CL73_SOFT_KR2(_pc) ((DEV_CFG_PTR(_pc)->cl73an == WCMOD_CL73_KR2) || \ 272 (DEV_CFG_PTR(_pc)->cl73an == WCMOD_CL73_KR2_CUSTOM) ) 273 /* TX drive configuration */ 274 275 #define WCMOD_NO_CFG_VALUE (-1) 276 #define TXDRV_PREEMPH(_tdrv) (((_tdrv).force << 15) | ((_tdrv).post << 10) | \ 277 ((_tdrv).main << 4) | ((_tdrv).pre)) 278 279 /* CL49 PRBS control */ 280 281 #define WCMOD_PRBS_TYPE_STD 0 282 #define WCMOD_PRBS_TYPE_CL49 1 283 #define WCMOD_PRBS_CFG_POLY31 3 284 #define WCMOD_PRBS_CL49_POLY31 (PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_MASK | \ 285 PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_MASK) 286 #define WCMOD_PRBS_CL49_POLY9 (PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_MASK | \ 287 0x80) 288 289 /* typedefs */ 290 /* CL72 in force mode */ 291 #define WCMOD_CL72_STATE_LINK_GOOD 0 292 #define WCMOD_CL72_STATE_WAIT_FOR_LINK 1 293 #define WCMOD_CL72_STATE_RESTART_PMD 2 294 #define WCMOD_CL72_LINK_WAIT_CNT_LIMIT 6 295 296 /*serdes_rx_los defines */ 297 #define WCMOD_RX_LOS_SW_ENABLE 1 298 #define WCMOD_RX_LOS_EXT_PIN_ENABLE 2 299 #define WCMOD_RXLOS_LINK_FLAP_WAR 0x4 300 301 302 /* index to TX drive configuration table for each VCO setting. 303 */ 304 typedef enum txdrv_inxs { 305 TXDRV_6250_INX, /* 6.26G, 3.125G 1.25G */ 306 TXDRV_103125_INX, /* 10.3125G */ 307 TXDRV_109375_INX, /* 10.9375G */ 308 TXDRV_12500_INX, /* 12.5G */ 309 TXDRV_11500_INX, /* 11.5G, 6.25G 5.75G */ 310 TXDRV_XFI_INX, /* 10G XFI */ 311 TXDRV_XLAUI_INX, /* 40G XLAUI mode */ 312 TXDRV_SFI_INX, /* 10G SR fiber mode */ 313 TXDRV_SFIDAC_INX, /* 10G SFI DAC mode */ 314 TXDRV_SR4_INX, /* 40G SR4 */ 315 TXDRV_6GOS1_INX, /* BRCM 40G mode */ 316 TXDRV_6GOS2_INX, /* */ 317 TXDRV_6GOS2_CX4_INX, /* */ 318 TXDRV_AN_INX, /* a common entry for autoneg mode */ 319 TXDRV_DFT_INX, /* temp for any missing speed modes */ 320 TXDRV_ILKN, 321 TXDRV_LAST_INX /* always last */ 322 } TXDRV_INXS_t; 323 324 #define TXDRV_ENTRY_NUM (TXDRV_LAST_INX) 325 326 typedef struct 327 { 328 unsigned int force: 1; /* forced */ 329 unsigned int post : 5; /* TX post tap */ 330 unsigned int main : 6; /* TX main tap */ 331 unsigned int pre : 4; /* TX pre tap */ 332 unsigned int rsvd : 16; /* reserved */ 333 } WCMOD_TX_TAP_t; 334 335 typedef enum sw_rx_los_states { 336 RESET, 337 INITIAL_LINK, 338 LINK, 339 START_TIMER, 340 RX_RESTART, 341 IDLE 342 } SOFTWARE_RX_LOS_STATES_t; 343 344 /* The structure is only for the use 345 * for RX LOS (Loss of Signal) workaround. 346 * The workaround is to handle the situations 347 * through s/w where no reliable LOS detect 348 * is available to WC 349 */ 350 typedef struct { 351 uint8 enable; 352 uint8 sys_link; 353 uint8 link_status; 354 uint8 timer_count; 355 uint8 rf_dis; 356 SOFTWARE_RX_LOS_STATES_t state; 357 } WCMOD_SOFTWARE_RX_LOS_t; 358 359 360 361 typedef struct { 362 union { 363 WCMOD_TX_TAP_t tap; 364 uint16 preemph; 365 } u; 366 uint8 post2; /* TX post2 coeff */ 367 uint8 idrive; /* TX idrive */ 368 uint8 ipredrive; /* TX pre-idrive */ 369 } WCMOD_TX_DRIVE_t; 370 371 typedef struct { 372 int preemph[MAX_NUM_LANES]; /* pre-emphasis */ 373 int idriver[MAX_NUM_LANES]; 374 int pdriver[MAX_NUM_LANES]; 375 int post2driver[MAX_NUM_LANES]; 376 int mld_lane_swap[48]; 377 int auto_medium; 378 int fiber_pref; 379 int sgmii_mstr; 380 int pdetect10g; /* 10G paralell detect */ 381 int pdetect1000x; /* 1000X paralell detect */ 382 int cx42hg; 383 int rxlane_map[MAX_NUM_LANES/4]; 384 int txlane_map[MAX_NUM_LANES/4]; 385 int cl73an; 386 int cl37an; 387 int cl72; 388 int forced_init_cl72; 389 int lane_mode; 390 int cx4_10g; 391 int lane0_rst; 392 int rxaui; 393 int rxaui_mode; 394 int dxgxs; 395 int custom; 396 uint32 line_intf; 397 int scrambler_en; 398 int custom1; 399 int txpol; 400 int rxpol; 401 int load_mthd; 402 int uc_cksum; 403 int medium; 404 int hg_mode; /* choose HG speed mode */ 405 int refclk; 406 int vco_freq; 407 int pll_divider; 408 int oversample_mode; 409 int pcs_bypass; 410 int firmware_mode; 411 int speed; 412 int max_speed; 413 int phy_passthru; 414 int phy_sgmii_an; 415 int asymmetric_mode; /*for xenia core mixed 1G/2.5G */ 416 int rx_los_ext_enable; /*rx_los_external pin enable */ 417 int linkscan_interval; 418 int active_lane_map; 419 int serdes_1000x_at_6250_vco; 420 mac_driver_t *macd; /* Attached MAC driver */ 421 WCMOD_TX_DRIVE_t tx_drive[TXDRV_ENTRY_NUM]; 422 WCMOD_SOFTWARE_RX_LOS_t sw_rx_los; 423 int mld_war_timer_count; 424 } WCMOD_DEV_CFG_t; 425 426 #define WCMOD_LANE_NAME_LEN 30 427 428 typedef struct { 429 uint16 serdes_id0; 430 char name[WCMOD_LANE_NAME_LEN]; 431 } WCMOD_DEV_INFO_t; 432 433 typedef struct { 434 uint32 start_time; 435 uint32 state; 436 uint32 cnt; 437 } WCMOD_LINK_WAR; 438 439 typedef struct { 440 uint32 start_time; 441 uint32 state; 442 } WCMOD_AN_MODE; 443 444 typedef struct { 445 int type; 446 int poly; 447 } WCMOD_PRBS_CTRL; 448 449 typedef struct { 450 uint16 state; 451 uint16 enabled; 452 uint16 tick_cnt; 453 uint16 restart_cnt; 454 } WCMOD_FORCE_CL72_t; 455 456 typedef struct { 457 WCMOD_LINK_WAR lkwa; 458 WCMOD_AN_MODE an; 459 int clk_comp; 460 WCMOD_PRBS_CTRL prbs; 461 WCMOD_FORCE_CL72_t cl72; 462 } WCMOD_DEV_CTRL_t; 463 464 typedef struct { 465 WCMOD_DEV_CFG_t cfg; 466 WCMOD_DEV_INFO_t info; 467 WCMOD_DEV_CTRL_t ctrl; 468 } WCMOD_DEV_DESC_t; 469 470 #define DEV_CFG_PTR(_pc) (&(((WCMOD_DEV_DESC_t *)((_pc) + 1))->cfg)) 471 #define DEV_INFO_PTR(_pc) (&(((WCMOD_DEV_DESC_t *)((_pc) + 1))->info)) 472 #define DEV_CTRL_PTR(_pc) (&(((WCMOD_DEV_DESC_t *)((_pc) + 1))->ctrl)) 473 474 /* force cl72 */ 475 #define FORCE_CL72_ENABLED(_pc) (DEV_CTRL_PTR(_pc)->cl72.enabled) 476 #define FORCE_CL72_STATE(_pc) (DEV_CTRL_PTR(_pc)->cl72.state) 477 #define FORCE_CL72_TICK_CNT(_pc) (DEV_CTRL_PTR(_pc)->cl72.tick_cnt) 478 #define FORCE_CL72_RESTART_CNT(_pc) (DEV_CTRL_PTR(_pc)->cl72.restart_cnt) 479 480 481 typedef struct { 482 uint8 *pdata; 483 int *plen; 484 uint16 chip_rev; 485 } WCMOD_UCODE_DESC; 486 487 /* external functions shared within WC driver files */ 488 /* extern int phy_wc40_config_init(phy_ctrl_t *pc); */ 489 490 491 #endif /* WL_WCMOD_H__ */