wcmod.h (2293718B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 */ 8 #include <sal/types.h> 9 /*************************************************************************** 10 * Copyright (c) 1999-2011, Broadcom Corporation 11 * All Rights Reserved 12 * Confidential Property of Broadcom Corporation 13 * 14 * 15 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 16 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 17 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 18 * 19 * $brcm_Workfile: $ 20 * $brcm_Revision: $ 21 * $brcm_Date: $ 22 * 23 * Module Description: 24 * DO NOT EDIT THIS FILE DIRECTLY 25 * 26 * This module was generated magically with RDB from a source description 27 * file. You must edit the source file for changes to be made to this file. 28 * 29 * 30 * Date: Generated on Wed Mar 23 13:01:57 2011 31 * MD5 Checksum a433b61bdcdcc8e6907c47d873908d98 32 * 33 * Compiled with: RDB Utility 5.0 34 * RDB Parser 3.0 35 * rdb2macro.pm 4.0 36 * Perl Interpreter 5.008008 37 * Operating System linux 38 * 39 * Spec Versions: BAM_NextPage 1 40 * CL73_UserB0 1 41 * EEEtimerB0 1 42 * EEEuserB0 1 43 * EEEuserB1 1 44 * ETA 1 45 * GP2 1 46 * RemotePhy 1 47 * aer 1 48 * cl49user 1 49 * cl72_userBlk0 1 50 * cl72_userBlk1 1 51 * cl72ieee 1 52 * cl82user 1 53 * cl82user_b1 1 54 * comboDigital 1 55 * digital5 1 56 * dsc_1 1 57 * dsc_2 1 58 * dsc_3 1 59 * dsc_4 1 60 * dsc_5 1 61 * dsc_6 1 62 * dummy 1 63 * efecuser 1 64 * fx100 1 65 * ieee_an 1 66 * ieee_cl22 1 67 * ieee_dte 1 68 * ieee_pcs 1 69 * ieee_phy 1 70 * ieee_pmd 1 71 * micro 1 72 * micro_Tmp1 1 73 * micro_Tmp2 1 74 * over1G 1 75 * pat_gen0 1 76 * pat_gen1 1 77 * rx66 1 78 * rx66b1 1 79 * rxBert 1 80 * tx66 1 81 * txBert 1 82 * xfi_bd0 1 83 * xfi_bd1 1 84 * xgxs 1 85 * xgxsBlk0 1 86 * xgxsBlk1 1 87 * xgxsBlk10 1 88 * xgxsBlk2 1 89 * xgxsBlk3 1 90 * xgxsBlk4 1 91 * xgxsBlk5 1 92 * xgxsBlk6 1 93 * xgxsBlk7 1 94 * xgxsBlk8 1 95 * xgxsBlk9 1 96 * 97 * RDB Files: /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/wc40_ALL.rdb 98 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/ieeeBlocks.rdb 99 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/ieee_cl22Regs.rdb 100 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/ieee_cl45pmdRegs.rdb 101 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/fecieee_common.rdb 102 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/ieee_cl45pcsRegs.rdb 103 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl49ieee_common.rdb 104 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl82ieee_common.rdb 105 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/ieee_cl45phyRegs.rdb 106 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/ieee_cl45dteRegs.rdb 107 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/ieee_cl45anRegs.rdb 108 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 109 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl72_ieee_regs.rdb 110 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/wc40_userBlocks.rdb 111 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock0_regs.rdb 112 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 113 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock1_regs.rdb 114 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 115 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock2_regs.rdb 116 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 117 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/TxBert_regs.rdb 118 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/RxBert_regs.rdb 119 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock3_regs.rdb 120 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock4_regs.rdb 121 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 122 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/gpStatus_types.rdb 123 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock5_regs.rdb 124 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 125 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock6_regs.rdb 126 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock7_regs.rdb 127 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock8_regs.rdb 128 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock9_regs.rdb 129 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlock10_regs.rdb 130 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsBlocks.rdb 131 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 132 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsPll_types.rdb 133 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/analogPll_types.rdb 134 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsTx_types.rdb 135 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/analogTx_types.rdb 136 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xgxsRx_types.rdb 137 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/analogRx_types.rdb 138 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/wc_IDregs.rdb 139 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/micro_Tmp1_regs.rdb 140 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 141 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/micro_Tmp2_regs.rdb 142 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 143 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/GP2_regs.rdb 144 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 145 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/dsc_1_regs.rdb 146 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/dsc_2_regs.rdb 147 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/dsc_3_regs.rdb 148 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/dsc_4_regs.rdb 149 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/dsc_5_regs.rdb 150 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/dsc_6_regs.rdb 151 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl72_userBlk0_regs.rdb 152 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl72_userBlk1_regs.rdb 153 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/comboDigital_regs.rdb 154 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 155 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/over1G_regs.rdb 156 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/RemotePhy_regs.rdb 157 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/digital5_regs.rdb 158 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 159 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/BAM_NextPage_regs.rdb 160 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl49user_regs.rdb 161 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl49user_common.rdb 162 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/CL73_UserB0_regs.rdb 163 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/efecuser_regs.rdb 164 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/EEEuserB0_regs.rdb 165 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/EEEuserB1_regs.rdb 166 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/tx66_regs.rdb 167 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/rx66_regs.rdb 168 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/rx66b1_regs.rdb 169 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/fx100_regs.rdb 170 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/EEEtimerB0_regs.rdb 171 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl82_user_regs.rdb 172 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl82user_common.rdb 173 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl82_user_b1_regs.rdb 174 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/cl82user_common.rdb 175 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/ETA_regs.rdb 176 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xfi_CD0Block_regs.rdb 177 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/xfi_CD1Block_regs.rdb 178 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/micro_regs.rdb 179 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/aerBlock.rdb 180 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_inc.rdb 181 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/pat_gen0_256.rdb 182 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/pat_gen1_256.rdb 183 * /projects/SERDES_040_ext6/Revision/revC0/team/ravick/doc/rdb/common_userBlocks.rdb 184 * 185 * Revision History: 186 * 187 * $brcm_Log: $ 188 */ 189 190 #ifndef _WCMOD_H_ 191 #define _WCMOD_H_ 192 193 /** 194 * m = memory, c = core, r = register, f = field, d = data. 195 */ 196 #if !defined(GET_FIELD) && !defined(SET_FIELD) 197 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 198 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 199 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 200 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 201 202 #define GET_FIELD(m,c,r,f) \ 203 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 204 205 #define SET_FIELD(m,c,r,f,d) \ 206 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 207 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 208 ) 209 210 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 211 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 212 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 213 214 #endif /* GET & SET */ 215 216 /**************************************************************************** 217 * Core Enums. 218 */ 219 /**************************************************************************** 220 * Enums: CL73_UserB0_cl73_fsm 221 */ 222 #define CL73_UserB0_cl73_fsm_AN_ENABLE 1 223 #define CL73_UserB0_cl73_fsm_TRANSMIT_DISABLE 2 224 #define CL73_UserB0_cl73_fsm_ABILITY_DETECT 4 225 #define CL73_UserB0_cl73_fsm_ACKNOWLEDGE_DETECT 8 226 #define CL73_UserB0_cl73_fsm_COMPLETE_ACKNOWLEDGE 16 227 #define CL73_UserB0_cl73_fsm_NEXT_PAGE_WAIT 32 228 #define CL73_UserB0_cl73_fsm_AN_GOOD_CHECK 64 229 #define CL73_UserB0_cl73_fsm_AN_GOOD 128 230 #define CL73_UserB0_cl73_fsm_LINK_STATUS_CHECK 256 231 #define CL73_UserB0_cl73_fsm_PARALLEL_DETECTION_FAULT 512 232 #define CL73_UserB0_cl73_fsm_AN_GOOD_CHECK_BAM37 1024 233 #define CL73_UserB0_cl73_fsm_TRANSMIT_DISABLE_BAM37 2048 234 235 /**************************************************************************** 236 * Enums: EEEuserB0_cl36TxEEEStates_l 237 */ 238 #define EEEuserB0_cl36TxEEEStates_l_TX_REFRESH 8 239 #define EEEuserB0_cl36TxEEEStates_l_TX_QUIET 4 240 #define EEEuserB0_cl36TxEEEStates_l_TX_SLEEP 2 241 #define EEEuserB0_cl36TxEEEStates_l_TX_ACTIVE 1 242 243 /**************************************************************************** 244 * Enums: EEEuserB0_cl36TxEEEStates_c 245 */ 246 #define EEEuserB0_cl36TxEEEStates_c_TX_REFRESH 3 247 #define EEEuserB0_cl36TxEEEStates_c_TX_QUIET 2 248 #define EEEuserB0_cl36TxEEEStates_c_TX_SLEEP 1 249 #define EEEuserB0_cl36TxEEEStates_c_TX_ACTIVE 0 250 251 /**************************************************************************** 252 * Enums: EEEuserB0_cl49TxEEEStates_l 253 */ 254 #define EEEuserB0_cl49TxEEEStates_l_SCR_RESET_2 64 255 #define EEEuserB0_cl49TxEEEStates_l_SCR_RESET_1 32 256 #define EEEuserB0_cl49TxEEEStates_l_TX_WAKE 16 257 #define EEEuserB0_cl49TxEEEStates_l_TX_REFRESH 8 258 #define EEEuserB0_cl49TxEEEStates_l_TX_QUIET 4 259 #define EEEuserB0_cl49TxEEEStates_l_TX_SLEEP 2 260 #define EEEuserB0_cl49TxEEEStates_l_TX_ACTIVE 1 261 262 /**************************************************************************** 263 * Enums: EEEuserB0_cl49TxEEEStates_c 264 */ 265 #define EEEuserB0_cl49TxEEEStates_c_SCR_RESET_2 6 266 #define EEEuserB0_cl49TxEEEStates_c_SCR_RESET_1 5 267 #define EEEuserB0_cl49TxEEEStates_c_TX_WAKE 4 268 #define EEEuserB0_cl49TxEEEStates_c_TX_REFRESH 3 269 #define EEEuserB0_cl49TxEEEStates_c_TX_QUIET 2 270 #define EEEuserB0_cl49TxEEEStates_c_TX_SLEEP 1 271 #define EEEuserB0_cl49TxEEEStates_c_TX_ACTIVE 0 272 273 /**************************************************************************** 274 * Enums: EEEuserB0_cl36RxEEEStates_l 275 */ 276 #define EEEuserB0_cl36RxEEEStates_l_RX_LINK_FAIL 32 277 #define EEEuserB0_cl36RxEEEStates_l_RX_WTF 16 278 #define EEEuserB0_cl36RxEEEStates_l_RX_WAKE 8 279 #define EEEuserB0_cl36RxEEEStates_l_RX_QUIET 4 280 #define EEEuserB0_cl36RxEEEStates_l_RX_SLEEP 2 281 #define EEEuserB0_cl36RxEEEStates_l_RX_ACTIVE 1 282 283 /**************************************************************************** 284 * Enums: EEEuserB0_cl36RxEEEStates_c 285 */ 286 #define EEEuserB0_cl36RxEEEStates_c_RX_LINK_FAIL 5 287 #define EEEuserB0_cl36RxEEEStates_c_RX_WTF 4 288 #define EEEuserB0_cl36RxEEEStates_c_RX_WAKE 3 289 #define EEEuserB0_cl36RxEEEStates_c_RX_QUIET 2 290 #define EEEuserB0_cl36RxEEEStates_c_RX_SLEEP 1 291 #define EEEuserB0_cl36RxEEEStates_c_RX_ACTIVE 0 292 293 /**************************************************************************** 294 * Enums: EEEuserB0_cl49RxEEEStates_l 295 */ 296 #define EEEuserB0_cl49RxEEEStates_l_RX_LINK_FAIL 32 297 #define EEEuserB0_cl49RxEEEStates_l_RX_WTF 16 298 #define EEEuserB0_cl49RxEEEStates_l_RX_WAKE 8 299 #define EEEuserB0_cl49RxEEEStates_l_RX_QUIET 4 300 #define EEEuserB0_cl49RxEEEStates_l_RX_SLEEP 2 301 #define EEEuserB0_cl49RxEEEStates_l_RX_ACTIVE 1 302 303 /**************************************************************************** 304 * Enums: EEEuserB0_cl49RxEEEStates_c 305 */ 306 #define EEEuserB0_cl49RxEEEStates_c_RX_LINK_FAIL 5 307 #define EEEuserB0_cl49RxEEEStates_c_RX_WTF 4 308 #define EEEuserB0_cl49RxEEEStates_c_RX_WAKE 3 309 #define EEEuserB0_cl49RxEEEStates_c_RX_QUIET 2 310 #define EEEuserB0_cl49RxEEEStates_c_RX_SLEEP 1 311 #define EEEuserB0_cl49RxEEEStates_c_RX_ACTIVE 0 312 313 /**************************************************************************** 314 * Enums: GP2_operationModes 315 */ 316 #define GP2_operationModes_XGXS 0 317 #define GP2_operationModes_XGXG_nCC 1 318 #define GP2_operationModes_IndLane_OS8 4 319 #define GP2_operationModes_IndLane_OS5 5 320 #define GP2_operationModes_PCI 7 321 #define GP2_operationModes_XGXS_nLQ 8 322 #define GP2_operationModes_XGXS_nLQnCC 9 323 #define GP2_operationModes_PBypass 10 324 #define GP2_operationModes_PBypass_nDSK 11 325 #define GP2_operationModes_ComboCoreMode 12 326 #define GP2_operationModes_Clocks_off 15 327 328 /**************************************************************************** 329 * Enums: GP2_actualSpeeds4 330 */ 331 #define GP2_actualSpeeds4_dr_10M 0 332 #define GP2_actualSpeeds4_dr_100M 1 333 #define GP2_actualSpeeds4_dr_1G 2 334 #define GP2_actualSpeeds4_dr_2p5G 3 335 #define GP2_actualSpeeds4_dr_5G_X4 4 336 #define GP2_actualSpeeds4_dr_6G_X4 5 337 #define GP2_actualSpeeds4_dr_10G_HiG 6 338 #define GP2_actualSpeeds4_dr_10G_CX4 7 339 #define GP2_actualSpeeds4_dr_12G_HiG 8 340 #define GP2_actualSpeeds4_dr_12p5G_X4 9 341 #define GP2_actualSpeeds4_dr_13G_X4 10 342 #define GP2_actualSpeeds4_dr_15G_X4 11 343 #define GP2_actualSpeeds4_dr_16G_X4 12 344 345 /**************************************************************************** 346 * Enums: GP2_actualSpeeds5 347 */ 348 #define GP2_actualSpeeds5_dr_10M 0 349 #define GP2_actualSpeeds5_dr_100M 1 350 #define GP2_actualSpeeds5_dr_1G 2 351 #define GP2_actualSpeeds5_dr_2p5G 3 352 #define GP2_actualSpeeds5_dr_5G_X4 4 353 #define GP2_actualSpeeds5_dr_6G_X4 5 354 #define GP2_actualSpeeds5_dr_10G_HiG 6 355 #define GP2_actualSpeeds5_dr_10G_CX4 7 356 #define GP2_actualSpeeds5_dr_12G_HiG 8 357 #define GP2_actualSpeeds5_dr_12p5G_X4 9 358 #define GP2_actualSpeeds5_dr_13G_X4 10 359 #define GP2_actualSpeeds5_dr_15G_X4 11 360 #define GP2_actualSpeeds5_dr_16G_X4 12 361 #define GP2_actualSpeeds5_dr_1G_KX 13 362 #define GP2_actualSpeeds5_dr_10G_KX4 14 363 #define GP2_actualSpeeds5_dr_10G_KR 15 364 #define GP2_actualSpeeds5_dr_5G 16 365 #define GP2_actualSpeeds5_dr_6p4G 17 366 #define GP2_actualSpeeds5_dr_20G_X4 18 367 #define GP2_actualSpeeds5_dr_21G_X4 19 368 #define GP2_actualSpeeds5_dr_25G_X4 20 369 #define GP2_actualSpeeds5_dr_10G_HiG_DXGXS 21 370 #define GP2_actualSpeeds5_dr_10G_DXGXS 22 371 #define GP2_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 372 #define GP2_actualSpeeds5_dr_10p5G_DXGXS 24 373 #define GP2_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 374 #define GP2_actualSpeeds5_dr_12p773G_DXGXS 26 375 #define GP2_actualSpeeds5_dr_10G_XFI 27 376 #define GP2_actualSpeeds5_dr_40G 28 377 #define GP2_actualSpeeds5_dr_20G_HiG_DXGXS 29 378 #define GP2_actualSpeeds5_dr_20G_DXGXS 30 379 #define GP2_actualSpeeds5_dr_10G_SFI 31 380 #define GP2_actualSpeeds5_dr_31p5G 32 381 #define GP2_actualSpeeds5_dr_32p7G 33 382 #define GP2_actualSpeeds5_dr_20G_SCR 34 383 #define GP2_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 384 #define GP2_actualSpeeds5_dr_10G_DXGXS_SCR 36 385 #define GP2_actualSpeeds5_dr_12G_R2 37 386 #define GP2_actualSpeeds5_dr_10G_X2 38 387 #define GP2_actualSpeeds5_dr_40G_KR4 39 388 #define GP2_actualSpeeds5_dr_40G_CR4 40 389 #define GP2_actualSpeeds5_dr_100G_CR10 41 390 #define GP2_actualSpeeds5_dr_15p75G_DXGXS 44 391 #define GP2_actualSpeeds5_dr_20G_KR2 57 392 #define GP2_actualSpeeds5_dr_20G_CR2 58 393 394 /**************************************************************************** 395 * Enums: GP2_actualSpeedsMisc1 396 */ 397 #define GP2_actualSpeedsMisc1_dr_2500BRCM_X1 16 398 #define GP2_actualSpeedsMisc1_dr_5000BRCM_X4 17 399 #define GP2_actualSpeedsMisc1_dr_6000BRCM_X4 18 400 #define GP2_actualSpeedsMisc1_dr_10GHiGig_X4 19 401 #define GP2_actualSpeedsMisc1_dr_10GBASE_CX4 20 402 #define GP2_actualSpeedsMisc1_dr_12GHiGig_X4 21 403 #define GP2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 404 #define GP2_actualSpeedsMisc1_dr_13GHiGig_X4 23 405 #define GP2_actualSpeedsMisc1_dr_15GHiGig_X4 24 406 #define GP2_actualSpeedsMisc1_dr_16GHiGig_X4 25 407 #define GP2_actualSpeedsMisc1_dr_5000BRCM_X1 26 408 #define GP2_actualSpeedsMisc1_dr_6363BRCM_X1 27 409 #define GP2_actualSpeedsMisc1_dr_20GHiGig_X4 28 410 #define GP2_actualSpeedsMisc1_dr_21GHiGig_X4 29 411 #define GP2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 412 #define GP2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 413 414 /**************************************************************************** 415 * Enums: GP2_IndLaneModes 416 */ 417 #define GP2_IndLaneModes_SWSDR_div2 0 418 #define GP2_IndLaneModes_SWSDR_div1 1 419 #define GP2_IndLaneModes_DWSDR_div2 2 420 #define GP2_IndLaneModes_DWSDR_div1 3 421 422 /**************************************************************************** 423 * Enums: GP2_prbsSelect 424 */ 425 #define GP2_prbsSelect_prbs7 0 426 #define GP2_prbsSelect_prbs15 1 427 #define GP2_prbsSelect_prbs23 2 428 #define GP2_prbsSelect_prbs31 3 429 430 /**************************************************************************** 431 * Enums: GP2_vcoDivider 432 */ 433 #define GP2_vcoDivider_div32 0 434 #define GP2_vcoDivider_div36 1 435 #define GP2_vcoDivider_div40 2 436 #define GP2_vcoDivider_div42 3 437 #define GP2_vcoDivider_div48 4 438 #define GP2_vcoDivider_div50 5 439 #define GP2_vcoDivider_div52 6 440 #define GP2_vcoDivider_div54 7 441 #define GP2_vcoDivider_div60 8 442 #define GP2_vcoDivider_div64 9 443 #define GP2_vcoDivider_div66 10 444 #define GP2_vcoDivider_div68 11 445 #define GP2_vcoDivider_div70 12 446 #define GP2_vcoDivider_div80 13 447 #define GP2_vcoDivider_div92 14 448 #define GP2_vcoDivider_div100 15 449 450 /**************************************************************************** 451 * Enums: GP2_refClkSelect 452 */ 453 #define GP2_refClkSelect_clk_25MHz 0 454 #define GP2_refClkSelect_clk_100MHz 1 455 #define GP2_refClkSelect_clk_125MHz 2 456 #define GP2_refClkSelect_clk_156p25MHz 3 457 #define GP2_refClkSelect_clk_187p5MHz 4 458 #define GP2_refClkSelect_clk_161p25Mhz 5 459 #define GP2_refClkSelect_clk_50Mhz 6 460 #define GP2_refClkSelect_clk_106p25Mhz 7 461 462 /**************************************************************************** 463 * Enums: GP2_aerMMDdevTypeSelect 464 */ 465 #define GP2_aerMMDdevTypeSelect_combo_core 0 466 #define GP2_aerMMDdevTypeSelect_PMA_PMD 1 467 #define GP2_aerMMDdevTypeSelect_PCS 3 468 #define GP2_aerMMDdevTypeSelect_PHY 4 469 #define GP2_aerMMDdevTypeSelect_DTE 5 470 #define GP2_aerMMDdevTypeSelect_CL73_AN 7 471 472 /**************************************************************************** 473 * Enums: GP2_aerMMDportSelect 474 */ 475 #define GP2_aerMMDportSelect_ln0 0 476 #define GP2_aerMMDportSelect_ln1 1 477 #define GP2_aerMMDportSelect_ln2 2 478 #define GP2_aerMMDportSelect_ln3 3 479 #define GP2_aerMMDportSelect_BCST 511 480 481 /**************************************************************************** 482 * Enums: GP2_firmwareModeSelect 483 */ 484 #define GP2_firmwareModeSelect_DEFAULT 0 485 #define GP2_firmwareModeSelect_SFP_OPT_LR 1 486 #define GP2_firmwareModeSelect_SFP_DAC 2 487 #define GP2_firmwareModeSelect_XLAUI 3 488 #define GP2_firmwareModeSelect_LONG_CH_6G 4 489 490 /**************************************************************************** 491 * Enums: GP2_tempIdxSelect 492 */ 493 #define GP2_tempIdxSelect_LTE__22p9C 15 494 #define GP2_tempIdxSelect_LTE__12p6C 14 495 #define GP2_tempIdxSelect_LTE__3p0C 13 496 #define GP2_tempIdxSelect_LTE_6p7C 12 497 #define GP2_tempIdxSelect_LTE_16p4C 11 498 #define GP2_tempIdxSelect_LTE_26p6C 10 499 #define GP2_tempIdxSelect_LTE_36p3C 9 500 #define GP2_tempIdxSelect_LTE_46p0C 8 501 #define GP2_tempIdxSelect_LTE_56p2C 7 502 #define GP2_tempIdxSelect_LTE_65p9C 6 503 #define GP2_tempIdxSelect_LTE_75p6C 5 504 #define GP2_tempIdxSelect_LTE_85p3C 4 505 #define GP2_tempIdxSelect_LTE_95p5C 3 506 #define GP2_tempIdxSelect_LTE_105p2C 2 507 #define GP2_tempIdxSelect_LTE_114p9C 1 508 #define GP2_tempIdxSelect_LTE_125p1C 0 509 510 /**************************************************************************** 511 * Enums: aer_operationModes 512 */ 513 #define aer_operationModes_XGXS 0 514 #define aer_operationModes_XGXG_nCC 1 515 #define aer_operationModes_IndLane_OS8 4 516 #define aer_operationModes_IndLane_OS5 5 517 #define aer_operationModes_PCI 7 518 #define aer_operationModes_XGXS_nLQ 8 519 #define aer_operationModes_XGXS_nLQnCC 9 520 #define aer_operationModes_PBypass 10 521 #define aer_operationModes_PBypass_nDSK 11 522 #define aer_operationModes_ComboCoreMode 12 523 #define aer_operationModes_Clocks_off 15 524 525 /**************************************************************************** 526 * Enums: aer_actualSpeeds4 527 */ 528 #define aer_actualSpeeds4_dr_10M 0 529 #define aer_actualSpeeds4_dr_100M 1 530 #define aer_actualSpeeds4_dr_1G 2 531 #define aer_actualSpeeds4_dr_2p5G 3 532 #define aer_actualSpeeds4_dr_5G_X4 4 533 #define aer_actualSpeeds4_dr_6G_X4 5 534 #define aer_actualSpeeds4_dr_10G_HiG 6 535 #define aer_actualSpeeds4_dr_10G_CX4 7 536 #define aer_actualSpeeds4_dr_12G_HiG 8 537 #define aer_actualSpeeds4_dr_12p5G_X4 9 538 #define aer_actualSpeeds4_dr_13G_X4 10 539 #define aer_actualSpeeds4_dr_15G_X4 11 540 #define aer_actualSpeeds4_dr_16G_X4 12 541 542 /**************************************************************************** 543 * Enums: aer_actualSpeeds5 544 */ 545 #define aer_actualSpeeds5_dr_10M 0 546 #define aer_actualSpeeds5_dr_100M 1 547 #define aer_actualSpeeds5_dr_1G 2 548 #define aer_actualSpeeds5_dr_2p5G 3 549 #define aer_actualSpeeds5_dr_5G_X4 4 550 #define aer_actualSpeeds5_dr_6G_X4 5 551 #define aer_actualSpeeds5_dr_10G_HiG 6 552 #define aer_actualSpeeds5_dr_10G_CX4 7 553 #define aer_actualSpeeds5_dr_12G_HiG 8 554 #define aer_actualSpeeds5_dr_12p5G_X4 9 555 #define aer_actualSpeeds5_dr_13G_X4 10 556 #define aer_actualSpeeds5_dr_15G_X4 11 557 #define aer_actualSpeeds5_dr_16G_X4 12 558 #define aer_actualSpeeds5_dr_1G_KX 13 559 #define aer_actualSpeeds5_dr_10G_KX4 14 560 #define aer_actualSpeeds5_dr_10G_KR 15 561 #define aer_actualSpeeds5_dr_5G 16 562 #define aer_actualSpeeds5_dr_6p4G 17 563 #define aer_actualSpeeds5_dr_20G_X4 18 564 #define aer_actualSpeeds5_dr_21G_X4 19 565 #define aer_actualSpeeds5_dr_25G_X4 20 566 #define aer_actualSpeeds5_dr_10G_HiG_DXGXS 21 567 #define aer_actualSpeeds5_dr_10G_DXGXS 22 568 #define aer_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 569 #define aer_actualSpeeds5_dr_10p5G_DXGXS 24 570 #define aer_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 571 #define aer_actualSpeeds5_dr_12p773G_DXGXS 26 572 #define aer_actualSpeeds5_dr_10G_XFI 27 573 #define aer_actualSpeeds5_dr_40G 28 574 #define aer_actualSpeeds5_dr_20G_HiG_DXGXS 29 575 #define aer_actualSpeeds5_dr_20G_DXGXS 30 576 #define aer_actualSpeeds5_dr_10G_SFI 31 577 #define aer_actualSpeeds5_dr_31p5G 32 578 #define aer_actualSpeeds5_dr_32p7G 33 579 #define aer_actualSpeeds5_dr_20G_SCR 34 580 #define aer_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 581 #define aer_actualSpeeds5_dr_10G_DXGXS_SCR 36 582 #define aer_actualSpeeds5_dr_12G_R2 37 583 #define aer_actualSpeeds5_dr_10G_X2 38 584 #define aer_actualSpeeds5_dr_40G_KR4 39 585 #define aer_actualSpeeds5_dr_40G_CR4 40 586 #define aer_actualSpeeds5_dr_100G_CR10 41 587 #define aer_actualSpeeds5_dr_15p75G_DXGXS 44 588 #define aer_actualSpeeds5_dr_20G_KR2 57 589 #define aer_actualSpeeds5_dr_20G_CR2 58 590 591 /**************************************************************************** 592 * Enums: aer_actualSpeedsMisc1 593 */ 594 #define aer_actualSpeedsMisc1_dr_2500BRCM_X1 16 595 #define aer_actualSpeedsMisc1_dr_5000BRCM_X4 17 596 #define aer_actualSpeedsMisc1_dr_6000BRCM_X4 18 597 #define aer_actualSpeedsMisc1_dr_10GHiGig_X4 19 598 #define aer_actualSpeedsMisc1_dr_10GBASE_CX4 20 599 #define aer_actualSpeedsMisc1_dr_12GHiGig_X4 21 600 #define aer_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 601 #define aer_actualSpeedsMisc1_dr_13GHiGig_X4 23 602 #define aer_actualSpeedsMisc1_dr_15GHiGig_X4 24 603 #define aer_actualSpeedsMisc1_dr_16GHiGig_X4 25 604 #define aer_actualSpeedsMisc1_dr_5000BRCM_X1 26 605 #define aer_actualSpeedsMisc1_dr_6363BRCM_X1 27 606 #define aer_actualSpeedsMisc1_dr_20GHiGig_X4 28 607 #define aer_actualSpeedsMisc1_dr_21GHiGig_X4 29 608 #define aer_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 609 #define aer_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 610 611 /**************************************************************************** 612 * Enums: aer_IndLaneModes 613 */ 614 #define aer_IndLaneModes_SWSDR_div2 0 615 #define aer_IndLaneModes_SWSDR_div1 1 616 #define aer_IndLaneModes_DWSDR_div2 2 617 #define aer_IndLaneModes_DWSDR_div1 3 618 619 /**************************************************************************** 620 * Enums: aer_prbsSelect 621 */ 622 #define aer_prbsSelect_prbs7 0 623 #define aer_prbsSelect_prbs15 1 624 #define aer_prbsSelect_prbs23 2 625 #define aer_prbsSelect_prbs31 3 626 627 /**************************************************************************** 628 * Enums: aer_vcoDivider 629 */ 630 #define aer_vcoDivider_div32 0 631 #define aer_vcoDivider_div36 1 632 #define aer_vcoDivider_div40 2 633 #define aer_vcoDivider_div42 3 634 #define aer_vcoDivider_div48 4 635 #define aer_vcoDivider_div50 5 636 #define aer_vcoDivider_div52 6 637 #define aer_vcoDivider_div54 7 638 #define aer_vcoDivider_div60 8 639 #define aer_vcoDivider_div64 9 640 #define aer_vcoDivider_div66 10 641 #define aer_vcoDivider_div68 11 642 #define aer_vcoDivider_div70 12 643 #define aer_vcoDivider_div80 13 644 #define aer_vcoDivider_div92 14 645 #define aer_vcoDivider_div100 15 646 647 /**************************************************************************** 648 * Enums: aer_refClkSelect 649 */ 650 #define aer_refClkSelect_clk_25MHz 0 651 #define aer_refClkSelect_clk_100MHz 1 652 #define aer_refClkSelect_clk_125MHz 2 653 #define aer_refClkSelect_clk_156p25MHz 3 654 #define aer_refClkSelect_clk_187p5MHz 4 655 #define aer_refClkSelect_clk_161p25Mhz 5 656 #define aer_refClkSelect_clk_50Mhz 6 657 #define aer_refClkSelect_clk_106p25Mhz 7 658 659 /**************************************************************************** 660 * Enums: aer_aerMMDdevTypeSelect 661 */ 662 #define aer_aerMMDdevTypeSelect_combo_core 0 663 #define aer_aerMMDdevTypeSelect_PMA_PMD 1 664 #define aer_aerMMDdevTypeSelect_PCS 3 665 #define aer_aerMMDdevTypeSelect_PHY 4 666 #define aer_aerMMDdevTypeSelect_DTE 5 667 #define aer_aerMMDdevTypeSelect_CL73_AN 7 668 669 /**************************************************************************** 670 * Enums: aer_aerMMDportSelect 671 */ 672 #define aer_aerMMDportSelect_ln0 0 673 #define aer_aerMMDportSelect_ln1 1 674 #define aer_aerMMDportSelect_ln2 2 675 #define aer_aerMMDportSelect_ln3 3 676 #define aer_aerMMDportSelect_BCST 511 677 678 /**************************************************************************** 679 * Enums: aer_firmwareModeSelect 680 */ 681 #define aer_firmwareModeSelect_DEFAULT 0 682 #define aer_firmwareModeSelect_SFP_OPT_LR 1 683 #define aer_firmwareModeSelect_SFP_DAC 2 684 #define aer_firmwareModeSelect_XLAUI 3 685 #define aer_firmwareModeSelect_LONG_CH_6G 4 686 687 /**************************************************************************** 688 * Enums: aer_tempIdxSelect 689 */ 690 #define aer_tempIdxSelect_LTE__22p9C 15 691 #define aer_tempIdxSelect_LTE__12p6C 14 692 #define aer_tempIdxSelect_LTE__3p0C 13 693 #define aer_tempIdxSelect_LTE_6p7C 12 694 #define aer_tempIdxSelect_LTE_16p4C 11 695 #define aer_tempIdxSelect_LTE_26p6C 10 696 #define aer_tempIdxSelect_LTE_36p3C 9 697 #define aer_tempIdxSelect_LTE_46p0C 8 698 #define aer_tempIdxSelect_LTE_56p2C 7 699 #define aer_tempIdxSelect_LTE_65p9C 6 700 #define aer_tempIdxSelect_LTE_75p6C 5 701 #define aer_tempIdxSelect_LTE_85p3C 4 702 #define aer_tempIdxSelect_LTE_95p5C 3 703 #define aer_tempIdxSelect_LTE_105p2C 2 704 #define aer_tempIdxSelect_LTE_114p9C 1 705 #define aer_tempIdxSelect_LTE_125p1C 0 706 707 /**************************************************************************** 708 * Enums: comboDigital_operationModes 709 */ 710 #define comboDigital_operationModes_XGXS 0 711 #define comboDigital_operationModes_XGXG_nCC 1 712 #define comboDigital_operationModes_IndLane_OS8 4 713 #define comboDigital_operationModes_IndLane_OS5 5 714 #define comboDigital_operationModes_PCI 7 715 #define comboDigital_operationModes_XGXS_nLQ 8 716 #define comboDigital_operationModes_XGXS_nLQnCC 9 717 #define comboDigital_operationModes_PBypass 10 718 #define comboDigital_operationModes_PBypass_nDSK 11 719 #define comboDigital_operationModes_ComboCoreMode 12 720 #define comboDigital_operationModes_Clocks_off 15 721 722 /**************************************************************************** 723 * Enums: comboDigital_actualSpeeds4 724 */ 725 #define comboDigital_actualSpeeds4_dr_10M 0 726 #define comboDigital_actualSpeeds4_dr_100M 1 727 #define comboDigital_actualSpeeds4_dr_1G 2 728 #define comboDigital_actualSpeeds4_dr_2p5G 3 729 #define comboDigital_actualSpeeds4_dr_5G_X4 4 730 #define comboDigital_actualSpeeds4_dr_6G_X4 5 731 #define comboDigital_actualSpeeds4_dr_10G_HiG 6 732 #define comboDigital_actualSpeeds4_dr_10G_CX4 7 733 #define comboDigital_actualSpeeds4_dr_12G_HiG 8 734 #define comboDigital_actualSpeeds4_dr_12p5G_X4 9 735 #define comboDigital_actualSpeeds4_dr_13G_X4 10 736 #define comboDigital_actualSpeeds4_dr_15G_X4 11 737 #define comboDigital_actualSpeeds4_dr_16G_X4 12 738 739 /**************************************************************************** 740 * Enums: comboDigital_actualSpeeds5 741 */ 742 #define comboDigital_actualSpeeds5_dr_10M 0 743 #define comboDigital_actualSpeeds5_dr_100M 1 744 #define comboDigital_actualSpeeds5_dr_1G 2 745 #define comboDigital_actualSpeeds5_dr_2p5G 3 746 #define comboDigital_actualSpeeds5_dr_5G_X4 4 747 #define comboDigital_actualSpeeds5_dr_6G_X4 5 748 #define comboDigital_actualSpeeds5_dr_10G_HiG 6 749 #define comboDigital_actualSpeeds5_dr_10G_CX4 7 750 #define comboDigital_actualSpeeds5_dr_12G_HiG 8 751 #define comboDigital_actualSpeeds5_dr_12p5G_X4 9 752 #define comboDigital_actualSpeeds5_dr_13G_X4 10 753 #define comboDigital_actualSpeeds5_dr_15G_X4 11 754 #define comboDigital_actualSpeeds5_dr_16G_X4 12 755 #define comboDigital_actualSpeeds5_dr_1G_KX 13 756 #define comboDigital_actualSpeeds5_dr_10G_KX4 14 757 #define comboDigital_actualSpeeds5_dr_10G_KR 15 758 #define comboDigital_actualSpeeds5_dr_5G 16 759 #define comboDigital_actualSpeeds5_dr_6p4G 17 760 #define comboDigital_actualSpeeds5_dr_20G_X4 18 761 #define comboDigital_actualSpeeds5_dr_21G_X4 19 762 #define comboDigital_actualSpeeds5_dr_25G_X4 20 763 #define comboDigital_actualSpeeds5_dr_10G_HiG_DXGXS 21 764 #define comboDigital_actualSpeeds5_dr_10G_DXGXS 22 765 #define comboDigital_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 766 #define comboDigital_actualSpeeds5_dr_10p5G_DXGXS 24 767 #define comboDigital_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 768 #define comboDigital_actualSpeeds5_dr_12p773G_DXGXS 26 769 #define comboDigital_actualSpeeds5_dr_10G_XFI 27 770 #define comboDigital_actualSpeeds5_dr_40G 28 771 #define comboDigital_actualSpeeds5_dr_20G_HiG_DXGXS 29 772 #define comboDigital_actualSpeeds5_dr_20G_DXGXS 30 773 #define comboDigital_actualSpeeds5_dr_10G_SFI 31 774 #define comboDigital_actualSpeeds5_dr_31p5G 32 775 #define comboDigital_actualSpeeds5_dr_32p7G 33 776 #define comboDigital_actualSpeeds5_dr_20G_SCR 34 777 #define comboDigital_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 778 #define comboDigital_actualSpeeds5_dr_10G_DXGXS_SCR 36 779 #define comboDigital_actualSpeeds5_dr_12G_R2 37 780 #define comboDigital_actualSpeeds5_dr_10G_X2 38 781 #define comboDigital_actualSpeeds5_dr_40G_KR4 39 782 #define comboDigital_actualSpeeds5_dr_40G_CR4 40 783 #define comboDigital_actualSpeeds5_dr_100G_CR10 41 784 #define comboDigital_actualSpeeds5_dr_15p75G_DXGXS 44 785 #define comboDigital_actualSpeeds5_dr_20G_KR2 57 786 #define comboDigital_actualSpeeds5_dr_20G_CR2 58 787 788 /**************************************************************************** 789 * Enums: comboDigital_actualSpeedsMisc1 790 */ 791 #define comboDigital_actualSpeedsMisc1_dr_2500BRCM_X1 16 792 #define comboDigital_actualSpeedsMisc1_dr_5000BRCM_X4 17 793 #define comboDigital_actualSpeedsMisc1_dr_6000BRCM_X4 18 794 #define comboDigital_actualSpeedsMisc1_dr_10GHiGig_X4 19 795 #define comboDigital_actualSpeedsMisc1_dr_10GBASE_CX4 20 796 #define comboDigital_actualSpeedsMisc1_dr_12GHiGig_X4 21 797 #define comboDigital_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 798 #define comboDigital_actualSpeedsMisc1_dr_13GHiGig_X4 23 799 #define comboDigital_actualSpeedsMisc1_dr_15GHiGig_X4 24 800 #define comboDigital_actualSpeedsMisc1_dr_16GHiGig_X4 25 801 #define comboDigital_actualSpeedsMisc1_dr_5000BRCM_X1 26 802 #define comboDigital_actualSpeedsMisc1_dr_6363BRCM_X1 27 803 #define comboDigital_actualSpeedsMisc1_dr_20GHiGig_X4 28 804 #define comboDigital_actualSpeedsMisc1_dr_21GHiGig_X4 29 805 #define comboDigital_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 806 #define comboDigital_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 807 808 /**************************************************************************** 809 * Enums: comboDigital_IndLaneModes 810 */ 811 #define comboDigital_IndLaneModes_SWSDR_div2 0 812 #define comboDigital_IndLaneModes_SWSDR_div1 1 813 #define comboDigital_IndLaneModes_DWSDR_div2 2 814 #define comboDigital_IndLaneModes_DWSDR_div1 3 815 816 /**************************************************************************** 817 * Enums: comboDigital_prbsSelect 818 */ 819 #define comboDigital_prbsSelect_prbs7 0 820 #define comboDigital_prbsSelect_prbs15 1 821 #define comboDigital_prbsSelect_prbs23 2 822 #define comboDigital_prbsSelect_prbs31 3 823 824 /**************************************************************************** 825 * Enums: comboDigital_vcoDivider 826 */ 827 #define comboDigital_vcoDivider_div32 0 828 #define comboDigital_vcoDivider_div36 1 829 #define comboDigital_vcoDivider_div40 2 830 #define comboDigital_vcoDivider_div42 3 831 #define comboDigital_vcoDivider_div48 4 832 #define comboDigital_vcoDivider_div50 5 833 #define comboDigital_vcoDivider_div52 6 834 #define comboDigital_vcoDivider_div54 7 835 #define comboDigital_vcoDivider_div60 8 836 #define comboDigital_vcoDivider_div64 9 837 #define comboDigital_vcoDivider_div66 10 838 #define comboDigital_vcoDivider_div68 11 839 #define comboDigital_vcoDivider_div70 12 840 #define comboDigital_vcoDivider_div80 13 841 #define comboDigital_vcoDivider_div92 14 842 #define comboDigital_vcoDivider_div100 15 843 844 /**************************************************************************** 845 * Enums: comboDigital_refClkSelect 846 */ 847 #define comboDigital_refClkSelect_clk_25MHz 0 848 #define comboDigital_refClkSelect_clk_100MHz 1 849 #define comboDigital_refClkSelect_clk_125MHz 2 850 #define comboDigital_refClkSelect_clk_156p25MHz 3 851 #define comboDigital_refClkSelect_clk_187p5MHz 4 852 #define comboDigital_refClkSelect_clk_161p25Mhz 5 853 #define comboDigital_refClkSelect_clk_50Mhz 6 854 #define comboDigital_refClkSelect_clk_106p25Mhz 7 855 856 /**************************************************************************** 857 * Enums: comboDigital_aerMMDdevTypeSelect 858 */ 859 #define comboDigital_aerMMDdevTypeSelect_combo_core 0 860 #define comboDigital_aerMMDdevTypeSelect_PMA_PMD 1 861 #define comboDigital_aerMMDdevTypeSelect_PCS 3 862 #define comboDigital_aerMMDdevTypeSelect_PHY 4 863 #define comboDigital_aerMMDdevTypeSelect_DTE 5 864 #define comboDigital_aerMMDdevTypeSelect_CL73_AN 7 865 866 /**************************************************************************** 867 * Enums: comboDigital_aerMMDportSelect 868 */ 869 #define comboDigital_aerMMDportSelect_ln0 0 870 #define comboDigital_aerMMDportSelect_ln1 1 871 #define comboDigital_aerMMDportSelect_ln2 2 872 #define comboDigital_aerMMDportSelect_ln3 3 873 #define comboDigital_aerMMDportSelect_BCST 511 874 875 /**************************************************************************** 876 * Enums: comboDigital_firmwareModeSelect 877 */ 878 #define comboDigital_firmwareModeSelect_DEFAULT 0 879 #define comboDigital_firmwareModeSelect_SFP_OPT_LR 1 880 #define comboDigital_firmwareModeSelect_SFP_DAC 2 881 #define comboDigital_firmwareModeSelect_XLAUI 3 882 #define comboDigital_firmwareModeSelect_LONG_CH_6G 4 883 884 /**************************************************************************** 885 * Enums: comboDigital_tempIdxSelect 886 */ 887 #define comboDigital_tempIdxSelect_LTE__22p9C 15 888 #define comboDigital_tempIdxSelect_LTE__12p6C 14 889 #define comboDigital_tempIdxSelect_LTE__3p0C 13 890 #define comboDigital_tempIdxSelect_LTE_6p7C 12 891 #define comboDigital_tempIdxSelect_LTE_16p4C 11 892 #define comboDigital_tempIdxSelect_LTE_26p6C 10 893 #define comboDigital_tempIdxSelect_LTE_36p3C 9 894 #define comboDigital_tempIdxSelect_LTE_46p0C 8 895 #define comboDigital_tempIdxSelect_LTE_56p2C 7 896 #define comboDigital_tempIdxSelect_LTE_65p9C 6 897 #define comboDigital_tempIdxSelect_LTE_75p6C 5 898 #define comboDigital_tempIdxSelect_LTE_85p3C 4 899 #define comboDigital_tempIdxSelect_LTE_95p5C 3 900 #define comboDigital_tempIdxSelect_LTE_105p2C 2 901 #define comboDigital_tempIdxSelect_LTE_114p9C 1 902 #define comboDigital_tempIdxSelect_LTE_125p1C 0 903 904 /**************************************************************************** 905 * Enums: digital5_operationModes 906 */ 907 #define digital5_operationModes_XGXS 0 908 #define digital5_operationModes_XGXG_nCC 1 909 #define digital5_operationModes_IndLane_OS8 4 910 #define digital5_operationModes_IndLane_OS5 5 911 #define digital5_operationModes_PCI 7 912 #define digital5_operationModes_XGXS_nLQ 8 913 #define digital5_operationModes_XGXS_nLQnCC 9 914 #define digital5_operationModes_PBypass 10 915 #define digital5_operationModes_PBypass_nDSK 11 916 #define digital5_operationModes_ComboCoreMode 12 917 #define digital5_operationModes_Clocks_off 15 918 919 /**************************************************************************** 920 * Enums: digital5_actualSpeeds4 921 */ 922 #define digital5_actualSpeeds4_dr_10M 0 923 #define digital5_actualSpeeds4_dr_100M 1 924 #define digital5_actualSpeeds4_dr_1G 2 925 #define digital5_actualSpeeds4_dr_2p5G 3 926 #define digital5_actualSpeeds4_dr_5G_X4 4 927 #define digital5_actualSpeeds4_dr_6G_X4 5 928 #define digital5_actualSpeeds4_dr_10G_HiG 6 929 #define digital5_actualSpeeds4_dr_10G_CX4 7 930 #define digital5_actualSpeeds4_dr_12G_HiG 8 931 #define digital5_actualSpeeds4_dr_12p5G_X4 9 932 #define digital5_actualSpeeds4_dr_13G_X4 10 933 #define digital5_actualSpeeds4_dr_15G_X4 11 934 #define digital5_actualSpeeds4_dr_16G_X4 12 935 936 /**************************************************************************** 937 * Enums: digital5_actualSpeeds5 938 */ 939 #define digital5_actualSpeeds5_dr_10M 0 940 #define digital5_actualSpeeds5_dr_100M 1 941 #define digital5_actualSpeeds5_dr_1G 2 942 #define digital5_actualSpeeds5_dr_2p5G 3 943 #define digital5_actualSpeeds5_dr_5G_X4 4 944 #define digital5_actualSpeeds5_dr_6G_X4 5 945 #define digital5_actualSpeeds5_dr_10G_HiG 6 946 #define digital5_actualSpeeds5_dr_10G_CX4 7 947 #define digital5_actualSpeeds5_dr_12G_HiG 8 948 #define digital5_actualSpeeds5_dr_12p5G_X4 9 949 #define digital5_actualSpeeds5_dr_13G_X4 10 950 #define digital5_actualSpeeds5_dr_15G_X4 11 951 #define digital5_actualSpeeds5_dr_16G_X4 12 952 #define digital5_actualSpeeds5_dr_1G_KX 13 953 #define digital5_actualSpeeds5_dr_10G_KX4 14 954 #define digital5_actualSpeeds5_dr_10G_KR 15 955 #define digital5_actualSpeeds5_dr_5G 16 956 #define digital5_actualSpeeds5_dr_6p4G 17 957 #define digital5_actualSpeeds5_dr_20G_X4 18 958 #define digital5_actualSpeeds5_dr_21G_X4 19 959 #define digital5_actualSpeeds5_dr_25G_X4 20 960 #define digital5_actualSpeeds5_dr_10G_HiG_DXGXS 21 961 #define digital5_actualSpeeds5_dr_10G_DXGXS 22 962 #define digital5_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 963 #define digital5_actualSpeeds5_dr_10p5G_DXGXS 24 964 #define digital5_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 965 #define digital5_actualSpeeds5_dr_12p773G_DXGXS 26 966 #define digital5_actualSpeeds5_dr_10G_XFI 27 967 #define digital5_actualSpeeds5_dr_40G 28 968 #define digital5_actualSpeeds5_dr_20G_HiG_DXGXS 29 969 #define digital5_actualSpeeds5_dr_20G_DXGXS 30 970 #define digital5_actualSpeeds5_dr_10G_SFI 31 971 #define digital5_actualSpeeds5_dr_31p5G 32 972 #define digital5_actualSpeeds5_dr_32p7G 33 973 #define digital5_actualSpeeds5_dr_20G_SCR 34 974 #define digital5_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 975 #define digital5_actualSpeeds5_dr_10G_DXGXS_SCR 36 976 #define digital5_actualSpeeds5_dr_12G_R2 37 977 #define digital5_actualSpeeds5_dr_10G_X2 38 978 #define digital5_actualSpeeds5_dr_40G_KR4 39 979 #define digital5_actualSpeeds5_dr_40G_CR4 40 980 #define digital5_actualSpeeds5_dr_100G_CR10 41 981 #define digital5_actualSpeeds5_dr_15p75G_DXGXS 44 982 #define digital5_actualSpeeds5_dr_20G_KR2 57 983 #define digital5_actualSpeeds5_dr_20G_CR2 58 984 985 /**************************************************************************** 986 * Enums: digital5_actualSpeedsMisc1 987 */ 988 #define digital5_actualSpeedsMisc1_dr_2500BRCM_X1 16 989 #define digital5_actualSpeedsMisc1_dr_5000BRCM_X4 17 990 #define digital5_actualSpeedsMisc1_dr_6000BRCM_X4 18 991 #define digital5_actualSpeedsMisc1_dr_10GHiGig_X4 19 992 #define digital5_actualSpeedsMisc1_dr_10GBASE_CX4 20 993 #define digital5_actualSpeedsMisc1_dr_12GHiGig_X4 21 994 #define digital5_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 995 #define digital5_actualSpeedsMisc1_dr_13GHiGig_X4 23 996 #define digital5_actualSpeedsMisc1_dr_15GHiGig_X4 24 997 #define digital5_actualSpeedsMisc1_dr_16GHiGig_X4 25 998 #define digital5_actualSpeedsMisc1_dr_5000BRCM_X1 26 999 #define digital5_actualSpeedsMisc1_dr_6363BRCM_X1 27 1000 #define digital5_actualSpeedsMisc1_dr_20GHiGig_X4 28 1001 #define digital5_actualSpeedsMisc1_dr_21GHiGig_X4 29 1002 #define digital5_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1003 #define digital5_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1004 1005 /**************************************************************************** 1006 * Enums: digital5_IndLaneModes 1007 */ 1008 #define digital5_IndLaneModes_SWSDR_div2 0 1009 #define digital5_IndLaneModes_SWSDR_div1 1 1010 #define digital5_IndLaneModes_DWSDR_div2 2 1011 #define digital5_IndLaneModes_DWSDR_div1 3 1012 1013 /**************************************************************************** 1014 * Enums: digital5_prbsSelect 1015 */ 1016 #define digital5_prbsSelect_prbs7 0 1017 #define digital5_prbsSelect_prbs15 1 1018 #define digital5_prbsSelect_prbs23 2 1019 #define digital5_prbsSelect_prbs31 3 1020 1021 /**************************************************************************** 1022 * Enums: digital5_vcoDivider 1023 */ 1024 #define digital5_vcoDivider_div32 0 1025 #define digital5_vcoDivider_div36 1 1026 #define digital5_vcoDivider_div40 2 1027 #define digital5_vcoDivider_div42 3 1028 #define digital5_vcoDivider_div48 4 1029 #define digital5_vcoDivider_div50 5 1030 #define digital5_vcoDivider_div52 6 1031 #define digital5_vcoDivider_div54 7 1032 #define digital5_vcoDivider_div60 8 1033 #define digital5_vcoDivider_div64 9 1034 #define digital5_vcoDivider_div66 10 1035 #define digital5_vcoDivider_div68 11 1036 #define digital5_vcoDivider_div70 12 1037 #define digital5_vcoDivider_div80 13 1038 #define digital5_vcoDivider_div92 14 1039 #define digital5_vcoDivider_div100 15 1040 1041 /**************************************************************************** 1042 * Enums: digital5_refClkSelect 1043 */ 1044 #define digital5_refClkSelect_clk_25MHz 0 1045 #define digital5_refClkSelect_clk_100MHz 1 1046 #define digital5_refClkSelect_clk_125MHz 2 1047 #define digital5_refClkSelect_clk_156p25MHz 3 1048 #define digital5_refClkSelect_clk_187p5MHz 4 1049 #define digital5_refClkSelect_clk_161p25Mhz 5 1050 #define digital5_refClkSelect_clk_50Mhz 6 1051 #define digital5_refClkSelect_clk_106p25Mhz 7 1052 1053 /**************************************************************************** 1054 * Enums: digital5_aerMMDdevTypeSelect 1055 */ 1056 #define digital5_aerMMDdevTypeSelect_combo_core 0 1057 #define digital5_aerMMDdevTypeSelect_PMA_PMD 1 1058 #define digital5_aerMMDdevTypeSelect_PCS 3 1059 #define digital5_aerMMDdevTypeSelect_PHY 4 1060 #define digital5_aerMMDdevTypeSelect_DTE 5 1061 #define digital5_aerMMDdevTypeSelect_CL73_AN 7 1062 1063 /**************************************************************************** 1064 * Enums: digital5_aerMMDportSelect 1065 */ 1066 #define digital5_aerMMDportSelect_ln0 0 1067 #define digital5_aerMMDportSelect_ln1 1 1068 #define digital5_aerMMDportSelect_ln2 2 1069 #define digital5_aerMMDportSelect_ln3 3 1070 #define digital5_aerMMDportSelect_BCST 511 1071 1072 /**************************************************************************** 1073 * Enums: digital5_firmwareModeSelect 1074 */ 1075 #define digital5_firmwareModeSelect_DEFAULT 0 1076 #define digital5_firmwareModeSelect_SFP_OPT_LR 1 1077 #define digital5_firmwareModeSelect_SFP_DAC 2 1078 #define digital5_firmwareModeSelect_XLAUI 3 1079 #define digital5_firmwareModeSelect_LONG_CH_6G 4 1080 1081 /**************************************************************************** 1082 * Enums: digital5_tempIdxSelect 1083 */ 1084 #define digital5_tempIdxSelect_LTE__22p9C 15 1085 #define digital5_tempIdxSelect_LTE__12p6C 14 1086 #define digital5_tempIdxSelect_LTE__3p0C 13 1087 #define digital5_tempIdxSelect_LTE_6p7C 12 1088 #define digital5_tempIdxSelect_LTE_16p4C 11 1089 #define digital5_tempIdxSelect_LTE_26p6C 10 1090 #define digital5_tempIdxSelect_LTE_36p3C 9 1091 #define digital5_tempIdxSelect_LTE_46p0C 8 1092 #define digital5_tempIdxSelect_LTE_56p2C 7 1093 #define digital5_tempIdxSelect_LTE_65p9C 6 1094 #define digital5_tempIdxSelect_LTE_75p6C 5 1095 #define digital5_tempIdxSelect_LTE_85p3C 4 1096 #define digital5_tempIdxSelect_LTE_95p5C 3 1097 #define digital5_tempIdxSelect_LTE_105p2C 2 1098 #define digital5_tempIdxSelect_LTE_114p9C 1 1099 #define digital5_tempIdxSelect_LTE_125p1C 0 1100 1101 /**************************************************************************** 1102 * Enums: ieee_an_operationModes 1103 */ 1104 #define ieee_an_operationModes_XGXS 0 1105 #define ieee_an_operationModes_XGXG_nCC 1 1106 #define ieee_an_operationModes_IndLane_OS8 4 1107 #define ieee_an_operationModes_IndLane_OS5 5 1108 #define ieee_an_operationModes_PCI 7 1109 #define ieee_an_operationModes_XGXS_nLQ 8 1110 #define ieee_an_operationModes_XGXS_nLQnCC 9 1111 #define ieee_an_operationModes_PBypass 10 1112 #define ieee_an_operationModes_PBypass_nDSK 11 1113 #define ieee_an_operationModes_ComboCoreMode 12 1114 #define ieee_an_operationModes_Clocks_off 15 1115 1116 /**************************************************************************** 1117 * Enums: ieee_an_actualSpeeds4 1118 */ 1119 #define ieee_an_actualSpeeds4_dr_10M 0 1120 #define ieee_an_actualSpeeds4_dr_100M 1 1121 #define ieee_an_actualSpeeds4_dr_1G 2 1122 #define ieee_an_actualSpeeds4_dr_2p5G 3 1123 #define ieee_an_actualSpeeds4_dr_5G_X4 4 1124 #define ieee_an_actualSpeeds4_dr_6G_X4 5 1125 #define ieee_an_actualSpeeds4_dr_10G_HiG 6 1126 #define ieee_an_actualSpeeds4_dr_10G_CX4 7 1127 #define ieee_an_actualSpeeds4_dr_12G_HiG 8 1128 #define ieee_an_actualSpeeds4_dr_12p5G_X4 9 1129 #define ieee_an_actualSpeeds4_dr_13G_X4 10 1130 #define ieee_an_actualSpeeds4_dr_15G_X4 11 1131 #define ieee_an_actualSpeeds4_dr_16G_X4 12 1132 1133 /**************************************************************************** 1134 * Enums: ieee_an_actualSpeeds5 1135 */ 1136 #define ieee_an_actualSpeeds5_dr_10M 0 1137 #define ieee_an_actualSpeeds5_dr_100M 1 1138 #define ieee_an_actualSpeeds5_dr_1G 2 1139 #define ieee_an_actualSpeeds5_dr_2p5G 3 1140 #define ieee_an_actualSpeeds5_dr_5G_X4 4 1141 #define ieee_an_actualSpeeds5_dr_6G_X4 5 1142 #define ieee_an_actualSpeeds5_dr_10G_HiG 6 1143 #define ieee_an_actualSpeeds5_dr_10G_CX4 7 1144 #define ieee_an_actualSpeeds5_dr_12G_HiG 8 1145 #define ieee_an_actualSpeeds5_dr_12p5G_X4 9 1146 #define ieee_an_actualSpeeds5_dr_13G_X4 10 1147 #define ieee_an_actualSpeeds5_dr_15G_X4 11 1148 #define ieee_an_actualSpeeds5_dr_16G_X4 12 1149 #define ieee_an_actualSpeeds5_dr_1G_KX 13 1150 #define ieee_an_actualSpeeds5_dr_10G_KX4 14 1151 #define ieee_an_actualSpeeds5_dr_10G_KR 15 1152 #define ieee_an_actualSpeeds5_dr_5G 16 1153 #define ieee_an_actualSpeeds5_dr_6p4G 17 1154 #define ieee_an_actualSpeeds5_dr_20G_X4 18 1155 #define ieee_an_actualSpeeds5_dr_21G_X4 19 1156 #define ieee_an_actualSpeeds5_dr_25G_X4 20 1157 #define ieee_an_actualSpeeds5_dr_10G_HiG_DXGXS 21 1158 #define ieee_an_actualSpeeds5_dr_10G_DXGXS 22 1159 #define ieee_an_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 1160 #define ieee_an_actualSpeeds5_dr_10p5G_DXGXS 24 1161 #define ieee_an_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 1162 #define ieee_an_actualSpeeds5_dr_12p773G_DXGXS 26 1163 #define ieee_an_actualSpeeds5_dr_10G_XFI 27 1164 #define ieee_an_actualSpeeds5_dr_40G 28 1165 #define ieee_an_actualSpeeds5_dr_20G_HiG_DXGXS 29 1166 #define ieee_an_actualSpeeds5_dr_20G_DXGXS 30 1167 #define ieee_an_actualSpeeds5_dr_10G_SFI 31 1168 #define ieee_an_actualSpeeds5_dr_31p5G 32 1169 #define ieee_an_actualSpeeds5_dr_32p7G 33 1170 #define ieee_an_actualSpeeds5_dr_20G_SCR 34 1171 #define ieee_an_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 1172 #define ieee_an_actualSpeeds5_dr_10G_DXGXS_SCR 36 1173 #define ieee_an_actualSpeeds5_dr_12G_R2 37 1174 #define ieee_an_actualSpeeds5_dr_10G_X2 38 1175 #define ieee_an_actualSpeeds5_dr_40G_KR4 39 1176 #define ieee_an_actualSpeeds5_dr_40G_CR4 40 1177 #define ieee_an_actualSpeeds5_dr_100G_CR10 41 1178 #define ieee_an_actualSpeeds5_dr_15p75G_DXGXS 44 1179 #define ieee_an_actualSpeeds5_dr_20G_KR2 57 1180 #define ieee_an_actualSpeeds5_dr_20G_CR2 58 1181 1182 /**************************************************************************** 1183 * Enums: ieee_an_actualSpeedsMisc1 1184 */ 1185 #define ieee_an_actualSpeedsMisc1_dr_2500BRCM_X1 16 1186 #define ieee_an_actualSpeedsMisc1_dr_5000BRCM_X4 17 1187 #define ieee_an_actualSpeedsMisc1_dr_6000BRCM_X4 18 1188 #define ieee_an_actualSpeedsMisc1_dr_10GHiGig_X4 19 1189 #define ieee_an_actualSpeedsMisc1_dr_10GBASE_CX4 20 1190 #define ieee_an_actualSpeedsMisc1_dr_12GHiGig_X4 21 1191 #define ieee_an_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1192 #define ieee_an_actualSpeedsMisc1_dr_13GHiGig_X4 23 1193 #define ieee_an_actualSpeedsMisc1_dr_15GHiGig_X4 24 1194 #define ieee_an_actualSpeedsMisc1_dr_16GHiGig_X4 25 1195 #define ieee_an_actualSpeedsMisc1_dr_5000BRCM_X1 26 1196 #define ieee_an_actualSpeedsMisc1_dr_6363BRCM_X1 27 1197 #define ieee_an_actualSpeedsMisc1_dr_20GHiGig_X4 28 1198 #define ieee_an_actualSpeedsMisc1_dr_21GHiGig_X4 29 1199 #define ieee_an_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1200 #define ieee_an_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1201 1202 /**************************************************************************** 1203 * Enums: ieee_an_IndLaneModes 1204 */ 1205 #define ieee_an_IndLaneModes_SWSDR_div2 0 1206 #define ieee_an_IndLaneModes_SWSDR_div1 1 1207 #define ieee_an_IndLaneModes_DWSDR_div2 2 1208 #define ieee_an_IndLaneModes_DWSDR_div1 3 1209 1210 /**************************************************************************** 1211 * Enums: ieee_an_prbsSelect 1212 */ 1213 #define ieee_an_prbsSelect_prbs7 0 1214 #define ieee_an_prbsSelect_prbs15 1 1215 #define ieee_an_prbsSelect_prbs23 2 1216 #define ieee_an_prbsSelect_prbs31 3 1217 1218 /**************************************************************************** 1219 * Enums: ieee_an_vcoDivider 1220 */ 1221 #define ieee_an_vcoDivider_div32 0 1222 #define ieee_an_vcoDivider_div36 1 1223 #define ieee_an_vcoDivider_div40 2 1224 #define ieee_an_vcoDivider_div42 3 1225 #define ieee_an_vcoDivider_div48 4 1226 #define ieee_an_vcoDivider_div50 5 1227 #define ieee_an_vcoDivider_div52 6 1228 #define ieee_an_vcoDivider_div54 7 1229 #define ieee_an_vcoDivider_div60 8 1230 #define ieee_an_vcoDivider_div64 9 1231 #define ieee_an_vcoDivider_div66 10 1232 #define ieee_an_vcoDivider_div68 11 1233 #define ieee_an_vcoDivider_div70 12 1234 #define ieee_an_vcoDivider_div80 13 1235 #define ieee_an_vcoDivider_div92 14 1236 #define ieee_an_vcoDivider_div100 15 1237 1238 /**************************************************************************** 1239 * Enums: ieee_an_refClkSelect 1240 */ 1241 #define ieee_an_refClkSelect_clk_25MHz 0 1242 #define ieee_an_refClkSelect_clk_100MHz 1 1243 #define ieee_an_refClkSelect_clk_125MHz 2 1244 #define ieee_an_refClkSelect_clk_156p25MHz 3 1245 #define ieee_an_refClkSelect_clk_187p5MHz 4 1246 #define ieee_an_refClkSelect_clk_161p25Mhz 5 1247 #define ieee_an_refClkSelect_clk_50Mhz 6 1248 #define ieee_an_refClkSelect_clk_106p25Mhz 7 1249 1250 /**************************************************************************** 1251 * Enums: ieee_an_aerMMDdevTypeSelect 1252 */ 1253 #define ieee_an_aerMMDdevTypeSelect_combo_core 0 1254 #define ieee_an_aerMMDdevTypeSelect_PMA_PMD 1 1255 #define ieee_an_aerMMDdevTypeSelect_PCS 3 1256 #define ieee_an_aerMMDdevTypeSelect_PHY 4 1257 #define ieee_an_aerMMDdevTypeSelect_DTE 5 1258 #define ieee_an_aerMMDdevTypeSelect_CL73_AN 7 1259 1260 /**************************************************************************** 1261 * Enums: ieee_an_aerMMDportSelect 1262 */ 1263 #define ieee_an_aerMMDportSelect_ln0 0 1264 #define ieee_an_aerMMDportSelect_ln1 1 1265 #define ieee_an_aerMMDportSelect_ln2 2 1266 #define ieee_an_aerMMDportSelect_ln3 3 1267 #define ieee_an_aerMMDportSelect_BCST 511 1268 1269 /**************************************************************************** 1270 * Enums: ieee_an_firmwareModeSelect 1271 */ 1272 #define ieee_an_firmwareModeSelect_DEFAULT 0 1273 #define ieee_an_firmwareModeSelect_SFP_OPT_LR 1 1274 #define ieee_an_firmwareModeSelect_SFP_DAC 2 1275 #define ieee_an_firmwareModeSelect_XLAUI 3 1276 #define ieee_an_firmwareModeSelect_LONG_CH_6G 4 1277 1278 /**************************************************************************** 1279 * Enums: ieee_an_tempIdxSelect 1280 */ 1281 #define ieee_an_tempIdxSelect_LTE__22p9C 15 1282 #define ieee_an_tempIdxSelect_LTE__12p6C 14 1283 #define ieee_an_tempIdxSelect_LTE__3p0C 13 1284 #define ieee_an_tempIdxSelect_LTE_6p7C 12 1285 #define ieee_an_tempIdxSelect_LTE_16p4C 11 1286 #define ieee_an_tempIdxSelect_LTE_26p6C 10 1287 #define ieee_an_tempIdxSelect_LTE_36p3C 9 1288 #define ieee_an_tempIdxSelect_LTE_46p0C 8 1289 #define ieee_an_tempIdxSelect_LTE_56p2C 7 1290 #define ieee_an_tempIdxSelect_LTE_65p9C 6 1291 #define ieee_an_tempIdxSelect_LTE_75p6C 5 1292 #define ieee_an_tempIdxSelect_LTE_85p3C 4 1293 #define ieee_an_tempIdxSelect_LTE_95p5C 3 1294 #define ieee_an_tempIdxSelect_LTE_105p2C 2 1295 #define ieee_an_tempIdxSelect_LTE_114p9C 1 1296 #define ieee_an_tempIdxSelect_LTE_125p1C 0 1297 1298 /**************************************************************************** 1299 * Enums: micro_Tmp1_operationModes 1300 */ 1301 #define micro_Tmp1_operationModes_XGXS 0 1302 #define micro_Tmp1_operationModes_XGXG_nCC 1 1303 #define micro_Tmp1_operationModes_IndLane_OS8 4 1304 #define micro_Tmp1_operationModes_IndLane_OS5 5 1305 #define micro_Tmp1_operationModes_PCI 7 1306 #define micro_Tmp1_operationModes_XGXS_nLQ 8 1307 #define micro_Tmp1_operationModes_XGXS_nLQnCC 9 1308 #define micro_Tmp1_operationModes_PBypass 10 1309 #define micro_Tmp1_operationModes_PBypass_nDSK 11 1310 #define micro_Tmp1_operationModes_ComboCoreMode 12 1311 #define micro_Tmp1_operationModes_Clocks_off 15 1312 1313 /**************************************************************************** 1314 * Enums: micro_Tmp1_actualSpeeds4 1315 */ 1316 #define micro_Tmp1_actualSpeeds4_dr_10M 0 1317 #define micro_Tmp1_actualSpeeds4_dr_100M 1 1318 #define micro_Tmp1_actualSpeeds4_dr_1G 2 1319 #define micro_Tmp1_actualSpeeds4_dr_2p5G 3 1320 #define micro_Tmp1_actualSpeeds4_dr_5G_X4 4 1321 #define micro_Tmp1_actualSpeeds4_dr_6G_X4 5 1322 #define micro_Tmp1_actualSpeeds4_dr_10G_HiG 6 1323 #define micro_Tmp1_actualSpeeds4_dr_10G_CX4 7 1324 #define micro_Tmp1_actualSpeeds4_dr_12G_HiG 8 1325 #define micro_Tmp1_actualSpeeds4_dr_12p5G_X4 9 1326 #define micro_Tmp1_actualSpeeds4_dr_13G_X4 10 1327 #define micro_Tmp1_actualSpeeds4_dr_15G_X4 11 1328 #define micro_Tmp1_actualSpeeds4_dr_16G_X4 12 1329 1330 /**************************************************************************** 1331 * Enums: micro_Tmp1_actualSpeeds5 1332 */ 1333 #define micro_Tmp1_actualSpeeds5_dr_10M 0 1334 #define micro_Tmp1_actualSpeeds5_dr_100M 1 1335 #define micro_Tmp1_actualSpeeds5_dr_1G 2 1336 #define micro_Tmp1_actualSpeeds5_dr_2p5G 3 1337 #define micro_Tmp1_actualSpeeds5_dr_5G_X4 4 1338 #define micro_Tmp1_actualSpeeds5_dr_6G_X4 5 1339 #define micro_Tmp1_actualSpeeds5_dr_10G_HiG 6 1340 #define micro_Tmp1_actualSpeeds5_dr_10G_CX4 7 1341 #define micro_Tmp1_actualSpeeds5_dr_12G_HiG 8 1342 #define micro_Tmp1_actualSpeeds5_dr_12p5G_X4 9 1343 #define micro_Tmp1_actualSpeeds5_dr_13G_X4 10 1344 #define micro_Tmp1_actualSpeeds5_dr_15G_X4 11 1345 #define micro_Tmp1_actualSpeeds5_dr_16G_X4 12 1346 #define micro_Tmp1_actualSpeeds5_dr_1G_KX 13 1347 #define micro_Tmp1_actualSpeeds5_dr_10G_KX4 14 1348 #define micro_Tmp1_actualSpeeds5_dr_10G_KR 15 1349 #define micro_Tmp1_actualSpeeds5_dr_5G 16 1350 #define micro_Tmp1_actualSpeeds5_dr_6p4G 17 1351 #define micro_Tmp1_actualSpeeds5_dr_20G_X4 18 1352 #define micro_Tmp1_actualSpeeds5_dr_21G_X4 19 1353 #define micro_Tmp1_actualSpeeds5_dr_25G_X4 20 1354 #define micro_Tmp1_actualSpeeds5_dr_10G_HiG_DXGXS 21 1355 #define micro_Tmp1_actualSpeeds5_dr_10G_DXGXS 22 1356 #define micro_Tmp1_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 1357 #define micro_Tmp1_actualSpeeds5_dr_10p5G_DXGXS 24 1358 #define micro_Tmp1_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 1359 #define micro_Tmp1_actualSpeeds5_dr_12p773G_DXGXS 26 1360 #define micro_Tmp1_actualSpeeds5_dr_10G_XFI 27 1361 #define micro_Tmp1_actualSpeeds5_dr_40G 28 1362 #define micro_Tmp1_actualSpeeds5_dr_20G_HiG_DXGXS 29 1363 #define micro_Tmp1_actualSpeeds5_dr_20G_DXGXS 30 1364 #define micro_Tmp1_actualSpeeds5_dr_10G_SFI 31 1365 #define micro_Tmp1_actualSpeeds5_dr_31p5G 32 1366 #define micro_Tmp1_actualSpeeds5_dr_32p7G 33 1367 #define micro_Tmp1_actualSpeeds5_dr_20G_SCR 34 1368 #define micro_Tmp1_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 1369 #define micro_Tmp1_actualSpeeds5_dr_10G_DXGXS_SCR 36 1370 #define micro_Tmp1_actualSpeeds5_dr_12G_R2 37 1371 #define micro_Tmp1_actualSpeeds5_dr_10G_X2 38 1372 #define micro_Tmp1_actualSpeeds5_dr_40G_KR4 39 1373 #define micro_Tmp1_actualSpeeds5_dr_40G_CR4 40 1374 #define micro_Tmp1_actualSpeeds5_dr_100G_CR10 41 1375 #define micro_Tmp1_actualSpeeds5_dr_15p75G_DXGXS 44 1376 #define micro_Tmp1_actualSpeeds5_dr_20G_KR2 57 1377 #define micro_Tmp1_actualSpeeds5_dr_20G_CR2 58 1378 1379 /**************************************************************************** 1380 * Enums: micro_Tmp1_actualSpeedsMisc1 1381 */ 1382 #define micro_Tmp1_actualSpeedsMisc1_dr_2500BRCM_X1 16 1383 #define micro_Tmp1_actualSpeedsMisc1_dr_5000BRCM_X4 17 1384 #define micro_Tmp1_actualSpeedsMisc1_dr_6000BRCM_X4 18 1385 #define micro_Tmp1_actualSpeedsMisc1_dr_10GHiGig_X4 19 1386 #define micro_Tmp1_actualSpeedsMisc1_dr_10GBASE_CX4 20 1387 #define micro_Tmp1_actualSpeedsMisc1_dr_12GHiGig_X4 21 1388 #define micro_Tmp1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1389 #define micro_Tmp1_actualSpeedsMisc1_dr_13GHiGig_X4 23 1390 #define micro_Tmp1_actualSpeedsMisc1_dr_15GHiGig_X4 24 1391 #define micro_Tmp1_actualSpeedsMisc1_dr_16GHiGig_X4 25 1392 #define micro_Tmp1_actualSpeedsMisc1_dr_5000BRCM_X1 26 1393 #define micro_Tmp1_actualSpeedsMisc1_dr_6363BRCM_X1 27 1394 #define micro_Tmp1_actualSpeedsMisc1_dr_20GHiGig_X4 28 1395 #define micro_Tmp1_actualSpeedsMisc1_dr_21GHiGig_X4 29 1396 #define micro_Tmp1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1397 #define micro_Tmp1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1398 1399 /**************************************************************************** 1400 * Enums: micro_Tmp1_IndLaneModes 1401 */ 1402 #define micro_Tmp1_IndLaneModes_SWSDR_div2 0 1403 #define micro_Tmp1_IndLaneModes_SWSDR_div1 1 1404 #define micro_Tmp1_IndLaneModes_DWSDR_div2 2 1405 #define micro_Tmp1_IndLaneModes_DWSDR_div1 3 1406 1407 /**************************************************************************** 1408 * Enums: micro_Tmp1_prbsSelect 1409 */ 1410 #define micro_Tmp1_prbsSelect_prbs7 0 1411 #define micro_Tmp1_prbsSelect_prbs15 1 1412 #define micro_Tmp1_prbsSelect_prbs23 2 1413 #define micro_Tmp1_prbsSelect_prbs31 3 1414 1415 /**************************************************************************** 1416 * Enums: micro_Tmp1_vcoDivider 1417 */ 1418 #define micro_Tmp1_vcoDivider_div32 0 1419 #define micro_Tmp1_vcoDivider_div36 1 1420 #define micro_Tmp1_vcoDivider_div40 2 1421 #define micro_Tmp1_vcoDivider_div42 3 1422 #define micro_Tmp1_vcoDivider_div48 4 1423 #define micro_Tmp1_vcoDivider_div50 5 1424 #define micro_Tmp1_vcoDivider_div52 6 1425 #define micro_Tmp1_vcoDivider_div54 7 1426 #define micro_Tmp1_vcoDivider_div60 8 1427 #define micro_Tmp1_vcoDivider_div64 9 1428 #define micro_Tmp1_vcoDivider_div66 10 1429 #define micro_Tmp1_vcoDivider_div68 11 1430 #define micro_Tmp1_vcoDivider_div70 12 1431 #define micro_Tmp1_vcoDivider_div80 13 1432 #define micro_Tmp1_vcoDivider_div92 14 1433 #define micro_Tmp1_vcoDivider_div100 15 1434 1435 /**************************************************************************** 1436 * Enums: micro_Tmp1_refClkSelect 1437 */ 1438 #define micro_Tmp1_refClkSelect_clk_25MHz 0 1439 #define micro_Tmp1_refClkSelect_clk_100MHz 1 1440 #define micro_Tmp1_refClkSelect_clk_125MHz 2 1441 #define micro_Tmp1_refClkSelect_clk_156p25MHz 3 1442 #define micro_Tmp1_refClkSelect_clk_187p5MHz 4 1443 #define micro_Tmp1_refClkSelect_clk_161p25Mhz 5 1444 #define micro_Tmp1_refClkSelect_clk_50Mhz 6 1445 #define micro_Tmp1_refClkSelect_clk_106p25Mhz 7 1446 1447 /**************************************************************************** 1448 * Enums: micro_Tmp1_aerMMDdevTypeSelect 1449 */ 1450 #define micro_Tmp1_aerMMDdevTypeSelect_combo_core 0 1451 #define micro_Tmp1_aerMMDdevTypeSelect_PMA_PMD 1 1452 #define micro_Tmp1_aerMMDdevTypeSelect_PCS 3 1453 #define micro_Tmp1_aerMMDdevTypeSelect_PHY 4 1454 #define micro_Tmp1_aerMMDdevTypeSelect_DTE 5 1455 #define micro_Tmp1_aerMMDdevTypeSelect_CL73_AN 7 1456 1457 /**************************************************************************** 1458 * Enums: micro_Tmp1_aerMMDportSelect 1459 */ 1460 #define micro_Tmp1_aerMMDportSelect_ln0 0 1461 #define micro_Tmp1_aerMMDportSelect_ln1 1 1462 #define micro_Tmp1_aerMMDportSelect_ln2 2 1463 #define micro_Tmp1_aerMMDportSelect_ln3 3 1464 #define micro_Tmp1_aerMMDportSelect_BCST 511 1465 1466 /**************************************************************************** 1467 * Enums: micro_Tmp1_firmwareModeSelect 1468 */ 1469 #define micro_Tmp1_firmwareModeSelect_DEFAULT 0 1470 #define micro_Tmp1_firmwareModeSelect_SFP_OPT_LR 1 1471 #define micro_Tmp1_firmwareModeSelect_SFP_DAC 2 1472 #define micro_Tmp1_firmwareModeSelect_XLAUI 3 1473 #define micro_Tmp1_firmwareModeSelect_LONG_CH_6G 4 1474 1475 /**************************************************************************** 1476 * Enums: micro_Tmp1_tempIdxSelect 1477 */ 1478 #define micro_Tmp1_tempIdxSelect_LTE__22p9C 15 1479 #define micro_Tmp1_tempIdxSelect_LTE__12p6C 14 1480 #define micro_Tmp1_tempIdxSelect_LTE__3p0C 13 1481 #define micro_Tmp1_tempIdxSelect_LTE_6p7C 12 1482 #define micro_Tmp1_tempIdxSelect_LTE_16p4C 11 1483 #define micro_Tmp1_tempIdxSelect_LTE_26p6C 10 1484 #define micro_Tmp1_tempIdxSelect_LTE_36p3C 9 1485 #define micro_Tmp1_tempIdxSelect_LTE_46p0C 8 1486 #define micro_Tmp1_tempIdxSelect_LTE_56p2C 7 1487 #define micro_Tmp1_tempIdxSelect_LTE_65p9C 6 1488 #define micro_Tmp1_tempIdxSelect_LTE_75p6C 5 1489 #define micro_Tmp1_tempIdxSelect_LTE_85p3C 4 1490 #define micro_Tmp1_tempIdxSelect_LTE_95p5C 3 1491 #define micro_Tmp1_tempIdxSelect_LTE_105p2C 2 1492 #define micro_Tmp1_tempIdxSelect_LTE_114p9C 1 1493 #define micro_Tmp1_tempIdxSelect_LTE_125p1C 0 1494 1495 /**************************************************************************** 1496 * Enums: micro_Tmp2_operationModes 1497 */ 1498 #define micro_Tmp2_operationModes_XGXS 0 1499 #define micro_Tmp2_operationModes_XGXG_nCC 1 1500 #define micro_Tmp2_operationModes_IndLane_OS8 4 1501 #define micro_Tmp2_operationModes_IndLane_OS5 5 1502 #define micro_Tmp2_operationModes_PCI 7 1503 #define micro_Tmp2_operationModes_XGXS_nLQ 8 1504 #define micro_Tmp2_operationModes_XGXS_nLQnCC 9 1505 #define micro_Tmp2_operationModes_PBypass 10 1506 #define micro_Tmp2_operationModes_PBypass_nDSK 11 1507 #define micro_Tmp2_operationModes_ComboCoreMode 12 1508 #define micro_Tmp2_operationModes_Clocks_off 15 1509 1510 /**************************************************************************** 1511 * Enums: micro_Tmp2_actualSpeeds4 1512 */ 1513 #define micro_Tmp2_actualSpeeds4_dr_10M 0 1514 #define micro_Tmp2_actualSpeeds4_dr_100M 1 1515 #define micro_Tmp2_actualSpeeds4_dr_1G 2 1516 #define micro_Tmp2_actualSpeeds4_dr_2p5G 3 1517 #define micro_Tmp2_actualSpeeds4_dr_5G_X4 4 1518 #define micro_Tmp2_actualSpeeds4_dr_6G_X4 5 1519 #define micro_Tmp2_actualSpeeds4_dr_10G_HiG 6 1520 #define micro_Tmp2_actualSpeeds4_dr_10G_CX4 7 1521 #define micro_Tmp2_actualSpeeds4_dr_12G_HiG 8 1522 #define micro_Tmp2_actualSpeeds4_dr_12p5G_X4 9 1523 #define micro_Tmp2_actualSpeeds4_dr_13G_X4 10 1524 #define micro_Tmp2_actualSpeeds4_dr_15G_X4 11 1525 #define micro_Tmp2_actualSpeeds4_dr_16G_X4 12 1526 1527 /**************************************************************************** 1528 * Enums: micro_Tmp2_actualSpeeds5 1529 */ 1530 #define micro_Tmp2_actualSpeeds5_dr_10M 0 1531 #define micro_Tmp2_actualSpeeds5_dr_100M 1 1532 #define micro_Tmp2_actualSpeeds5_dr_1G 2 1533 #define micro_Tmp2_actualSpeeds5_dr_2p5G 3 1534 #define micro_Tmp2_actualSpeeds5_dr_5G_X4 4 1535 #define micro_Tmp2_actualSpeeds5_dr_6G_X4 5 1536 #define micro_Tmp2_actualSpeeds5_dr_10G_HiG 6 1537 #define micro_Tmp2_actualSpeeds5_dr_10G_CX4 7 1538 #define micro_Tmp2_actualSpeeds5_dr_12G_HiG 8 1539 #define micro_Tmp2_actualSpeeds5_dr_12p5G_X4 9 1540 #define micro_Tmp2_actualSpeeds5_dr_13G_X4 10 1541 #define micro_Tmp2_actualSpeeds5_dr_15G_X4 11 1542 #define micro_Tmp2_actualSpeeds5_dr_16G_X4 12 1543 #define micro_Tmp2_actualSpeeds5_dr_1G_KX 13 1544 #define micro_Tmp2_actualSpeeds5_dr_10G_KX4 14 1545 #define micro_Tmp2_actualSpeeds5_dr_10G_KR 15 1546 #define micro_Tmp2_actualSpeeds5_dr_5G 16 1547 #define micro_Tmp2_actualSpeeds5_dr_6p4G 17 1548 #define micro_Tmp2_actualSpeeds5_dr_20G_X4 18 1549 #define micro_Tmp2_actualSpeeds5_dr_21G_X4 19 1550 #define micro_Tmp2_actualSpeeds5_dr_25G_X4 20 1551 #define micro_Tmp2_actualSpeeds5_dr_10G_HiG_DXGXS 21 1552 #define micro_Tmp2_actualSpeeds5_dr_10G_DXGXS 22 1553 #define micro_Tmp2_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 1554 #define micro_Tmp2_actualSpeeds5_dr_10p5G_DXGXS 24 1555 #define micro_Tmp2_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 1556 #define micro_Tmp2_actualSpeeds5_dr_12p773G_DXGXS 26 1557 #define micro_Tmp2_actualSpeeds5_dr_10G_XFI 27 1558 #define micro_Tmp2_actualSpeeds5_dr_40G 28 1559 #define micro_Tmp2_actualSpeeds5_dr_20G_HiG_DXGXS 29 1560 #define micro_Tmp2_actualSpeeds5_dr_20G_DXGXS 30 1561 #define micro_Tmp2_actualSpeeds5_dr_10G_SFI 31 1562 #define micro_Tmp2_actualSpeeds5_dr_31p5G 32 1563 #define micro_Tmp2_actualSpeeds5_dr_32p7G 33 1564 #define micro_Tmp2_actualSpeeds5_dr_20G_SCR 34 1565 #define micro_Tmp2_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 1566 #define micro_Tmp2_actualSpeeds5_dr_10G_DXGXS_SCR 36 1567 #define micro_Tmp2_actualSpeeds5_dr_12G_R2 37 1568 #define micro_Tmp2_actualSpeeds5_dr_10G_X2 38 1569 #define micro_Tmp2_actualSpeeds5_dr_40G_KR4 39 1570 #define micro_Tmp2_actualSpeeds5_dr_40G_CR4 40 1571 #define micro_Tmp2_actualSpeeds5_dr_100G_CR10 41 1572 #define micro_Tmp2_actualSpeeds5_dr_15p75G_DXGXS 44 1573 #define micro_Tmp2_actualSpeeds5_dr_20G_KR2 57 1574 #define micro_Tmp2_actualSpeeds5_dr_20G_CR2 58 1575 1576 /**************************************************************************** 1577 * Enums: micro_Tmp2_actualSpeedsMisc1 1578 */ 1579 #define micro_Tmp2_actualSpeedsMisc1_dr_2500BRCM_X1 16 1580 #define micro_Tmp2_actualSpeedsMisc1_dr_5000BRCM_X4 17 1581 #define micro_Tmp2_actualSpeedsMisc1_dr_6000BRCM_X4 18 1582 #define micro_Tmp2_actualSpeedsMisc1_dr_10GHiGig_X4 19 1583 #define micro_Tmp2_actualSpeedsMisc1_dr_10GBASE_CX4 20 1584 #define micro_Tmp2_actualSpeedsMisc1_dr_12GHiGig_X4 21 1585 #define micro_Tmp2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1586 #define micro_Tmp2_actualSpeedsMisc1_dr_13GHiGig_X4 23 1587 #define micro_Tmp2_actualSpeedsMisc1_dr_15GHiGig_X4 24 1588 #define micro_Tmp2_actualSpeedsMisc1_dr_16GHiGig_X4 25 1589 #define micro_Tmp2_actualSpeedsMisc1_dr_5000BRCM_X1 26 1590 #define micro_Tmp2_actualSpeedsMisc1_dr_6363BRCM_X1 27 1591 #define micro_Tmp2_actualSpeedsMisc1_dr_20GHiGig_X4 28 1592 #define micro_Tmp2_actualSpeedsMisc1_dr_21GHiGig_X4 29 1593 #define micro_Tmp2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1594 #define micro_Tmp2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1595 1596 /**************************************************************************** 1597 * Enums: micro_Tmp2_IndLaneModes 1598 */ 1599 #define micro_Tmp2_IndLaneModes_SWSDR_div2 0 1600 #define micro_Tmp2_IndLaneModes_SWSDR_div1 1 1601 #define micro_Tmp2_IndLaneModes_DWSDR_div2 2 1602 #define micro_Tmp2_IndLaneModes_DWSDR_div1 3 1603 1604 /**************************************************************************** 1605 * Enums: micro_Tmp2_prbsSelect 1606 */ 1607 #define micro_Tmp2_prbsSelect_prbs7 0 1608 #define micro_Tmp2_prbsSelect_prbs15 1 1609 #define micro_Tmp2_prbsSelect_prbs23 2 1610 #define micro_Tmp2_prbsSelect_prbs31 3 1611 1612 /**************************************************************************** 1613 * Enums: micro_Tmp2_vcoDivider 1614 */ 1615 #define micro_Tmp2_vcoDivider_div32 0 1616 #define micro_Tmp2_vcoDivider_div36 1 1617 #define micro_Tmp2_vcoDivider_div40 2 1618 #define micro_Tmp2_vcoDivider_div42 3 1619 #define micro_Tmp2_vcoDivider_div48 4 1620 #define micro_Tmp2_vcoDivider_div50 5 1621 #define micro_Tmp2_vcoDivider_div52 6 1622 #define micro_Tmp2_vcoDivider_div54 7 1623 #define micro_Tmp2_vcoDivider_div60 8 1624 #define micro_Tmp2_vcoDivider_div64 9 1625 #define micro_Tmp2_vcoDivider_div66 10 1626 #define micro_Tmp2_vcoDivider_div68 11 1627 #define micro_Tmp2_vcoDivider_div70 12 1628 #define micro_Tmp2_vcoDivider_div80 13 1629 #define micro_Tmp2_vcoDivider_div92 14 1630 #define micro_Tmp2_vcoDivider_div100 15 1631 1632 /**************************************************************************** 1633 * Enums: micro_Tmp2_refClkSelect 1634 */ 1635 #define micro_Tmp2_refClkSelect_clk_25MHz 0 1636 #define micro_Tmp2_refClkSelect_clk_100MHz 1 1637 #define micro_Tmp2_refClkSelect_clk_125MHz 2 1638 #define micro_Tmp2_refClkSelect_clk_156p25MHz 3 1639 #define micro_Tmp2_refClkSelect_clk_187p5MHz 4 1640 #define micro_Tmp2_refClkSelect_clk_161p25Mhz 5 1641 #define micro_Tmp2_refClkSelect_clk_50Mhz 6 1642 #define micro_Tmp2_refClkSelect_clk_106p25Mhz 7 1643 1644 /**************************************************************************** 1645 * Enums: micro_Tmp2_aerMMDdevTypeSelect 1646 */ 1647 #define micro_Tmp2_aerMMDdevTypeSelect_combo_core 0 1648 #define micro_Tmp2_aerMMDdevTypeSelect_PMA_PMD 1 1649 #define micro_Tmp2_aerMMDdevTypeSelect_PCS 3 1650 #define micro_Tmp2_aerMMDdevTypeSelect_PHY 4 1651 #define micro_Tmp2_aerMMDdevTypeSelect_DTE 5 1652 #define micro_Tmp2_aerMMDdevTypeSelect_CL73_AN 7 1653 1654 /**************************************************************************** 1655 * Enums: micro_Tmp2_aerMMDportSelect 1656 */ 1657 #define micro_Tmp2_aerMMDportSelect_ln0 0 1658 #define micro_Tmp2_aerMMDportSelect_ln1 1 1659 #define micro_Tmp2_aerMMDportSelect_ln2 2 1660 #define micro_Tmp2_aerMMDportSelect_ln3 3 1661 #define micro_Tmp2_aerMMDportSelect_BCST 511 1662 1663 /**************************************************************************** 1664 * Enums: micro_Tmp2_firmwareModeSelect 1665 */ 1666 #define micro_Tmp2_firmwareModeSelect_DEFAULT 0 1667 #define micro_Tmp2_firmwareModeSelect_SFP_OPT_LR 1 1668 #define micro_Tmp2_firmwareModeSelect_SFP_DAC 2 1669 #define micro_Tmp2_firmwareModeSelect_XLAUI 3 1670 #define micro_Tmp2_firmwareModeSelect_LONG_CH_6G 4 1671 1672 /**************************************************************************** 1673 * Enums: micro_Tmp2_tempIdxSelect 1674 */ 1675 #define micro_Tmp2_tempIdxSelect_LTE__22p9C 15 1676 #define micro_Tmp2_tempIdxSelect_LTE__12p6C 14 1677 #define micro_Tmp2_tempIdxSelect_LTE__3p0C 13 1678 #define micro_Tmp2_tempIdxSelect_LTE_6p7C 12 1679 #define micro_Tmp2_tempIdxSelect_LTE_16p4C 11 1680 #define micro_Tmp2_tempIdxSelect_LTE_26p6C 10 1681 #define micro_Tmp2_tempIdxSelect_LTE_36p3C 9 1682 #define micro_Tmp2_tempIdxSelect_LTE_46p0C 8 1683 #define micro_Tmp2_tempIdxSelect_LTE_56p2C 7 1684 #define micro_Tmp2_tempIdxSelect_LTE_65p9C 6 1685 #define micro_Tmp2_tempIdxSelect_LTE_75p6C 5 1686 #define micro_Tmp2_tempIdxSelect_LTE_85p3C 4 1687 #define micro_Tmp2_tempIdxSelect_LTE_95p5C 3 1688 #define micro_Tmp2_tempIdxSelect_LTE_105p2C 2 1689 #define micro_Tmp2_tempIdxSelect_LTE_114p9C 1 1690 #define micro_Tmp2_tempIdxSelect_LTE_125p1C 0 1691 1692 /**************************************************************************** 1693 * Enums: xgxs_operationModes 1694 */ 1695 #define xgxs_operationModes_XGXS 0 1696 #define xgxs_operationModes_XGXG_nCC 1 1697 #define xgxs_operationModes_IndLane_OS8 4 1698 #define xgxs_operationModes_IndLane_OS5 5 1699 #define xgxs_operationModes_PCI 7 1700 #define xgxs_operationModes_XGXS_nLQ 8 1701 #define xgxs_operationModes_XGXS_nLQnCC 9 1702 #define xgxs_operationModes_PBypass 10 1703 #define xgxs_operationModes_PBypass_nDSK 11 1704 #define xgxs_operationModes_ComboCoreMode 12 1705 #define xgxs_operationModes_Clocks_off 15 1706 1707 /**************************************************************************** 1708 * Enums: xgxs_actualSpeeds4 1709 */ 1710 #define xgxs_actualSpeeds4_dr_10M 0 1711 #define xgxs_actualSpeeds4_dr_100M 1 1712 #define xgxs_actualSpeeds4_dr_1G 2 1713 #define xgxs_actualSpeeds4_dr_2p5G 3 1714 #define xgxs_actualSpeeds4_dr_5G_X4 4 1715 #define xgxs_actualSpeeds4_dr_6G_X4 5 1716 #define xgxs_actualSpeeds4_dr_10G_HiG 6 1717 #define xgxs_actualSpeeds4_dr_10G_CX4 7 1718 #define xgxs_actualSpeeds4_dr_12G_HiG 8 1719 #define xgxs_actualSpeeds4_dr_12p5G_X4 9 1720 #define xgxs_actualSpeeds4_dr_13G_X4 10 1721 #define xgxs_actualSpeeds4_dr_15G_X4 11 1722 #define xgxs_actualSpeeds4_dr_16G_X4 12 1723 1724 /**************************************************************************** 1725 * Enums: xgxs_actualSpeeds5 1726 */ 1727 #define xgxs_actualSpeeds5_dr_10M 0 1728 #define xgxs_actualSpeeds5_dr_100M 1 1729 #define xgxs_actualSpeeds5_dr_1G 2 1730 #define xgxs_actualSpeeds5_dr_2p5G 3 1731 #define xgxs_actualSpeeds5_dr_5G_X4 4 1732 #define xgxs_actualSpeeds5_dr_6G_X4 5 1733 #define xgxs_actualSpeeds5_dr_10G_HiG 6 1734 #define xgxs_actualSpeeds5_dr_10G_CX4 7 1735 #define xgxs_actualSpeeds5_dr_12G_HiG 8 1736 #define xgxs_actualSpeeds5_dr_12p5G_X4 9 1737 #define xgxs_actualSpeeds5_dr_13G_X4 10 1738 #define xgxs_actualSpeeds5_dr_15G_X4 11 1739 #define xgxs_actualSpeeds5_dr_16G_X4 12 1740 #define xgxs_actualSpeeds5_dr_1G_KX 13 1741 #define xgxs_actualSpeeds5_dr_10G_KX4 14 1742 #define xgxs_actualSpeeds5_dr_10G_KR 15 1743 #define xgxs_actualSpeeds5_dr_5G 16 1744 #define xgxs_actualSpeeds5_dr_6p4G 17 1745 #define xgxs_actualSpeeds5_dr_20G_X4 18 1746 #define xgxs_actualSpeeds5_dr_21G_X4 19 1747 #define xgxs_actualSpeeds5_dr_25G_X4 20 1748 #define xgxs_actualSpeeds5_dr_10G_HiG_DXGXS 21 1749 #define xgxs_actualSpeeds5_dr_10G_DXGXS 22 1750 #define xgxs_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 1751 #define xgxs_actualSpeeds5_dr_10p5G_DXGXS 24 1752 #define xgxs_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 1753 #define xgxs_actualSpeeds5_dr_12p773G_DXGXS 26 1754 #define xgxs_actualSpeeds5_dr_10G_XFI 27 1755 #define xgxs_actualSpeeds5_dr_40G 28 1756 #define xgxs_actualSpeeds5_dr_20G_HiG_DXGXS 29 1757 #define xgxs_actualSpeeds5_dr_20G_DXGXS 30 1758 #define xgxs_actualSpeeds5_dr_10G_SFI 31 1759 #define xgxs_actualSpeeds5_dr_31p5G 32 1760 #define xgxs_actualSpeeds5_dr_32p7G 33 1761 #define xgxs_actualSpeeds5_dr_20G_SCR 34 1762 #define xgxs_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 1763 #define xgxs_actualSpeeds5_dr_10G_DXGXS_SCR 36 1764 #define xgxs_actualSpeeds5_dr_12G_R2 37 1765 #define xgxs_actualSpeeds5_dr_10G_X2 38 1766 #define xgxs_actualSpeeds5_dr_40G_KR4 39 1767 #define xgxs_actualSpeeds5_dr_40G_CR4 40 1768 #define xgxs_actualSpeeds5_dr_100G_CR10 41 1769 #define xgxs_actualSpeeds5_dr_15p75G_DXGXS 44 1770 #define xgxs_actualSpeeds5_dr_20G_KR2 57 1771 #define xgxs_actualSpeeds5_dr_20G_CR2 58 1772 1773 /**************************************************************************** 1774 * Enums: xgxs_actualSpeedsMisc1 1775 */ 1776 #define xgxs_actualSpeedsMisc1_dr_2500BRCM_X1 16 1777 #define xgxs_actualSpeedsMisc1_dr_5000BRCM_X4 17 1778 #define xgxs_actualSpeedsMisc1_dr_6000BRCM_X4 18 1779 #define xgxs_actualSpeedsMisc1_dr_10GHiGig_X4 19 1780 #define xgxs_actualSpeedsMisc1_dr_10GBASE_CX4 20 1781 #define xgxs_actualSpeedsMisc1_dr_12GHiGig_X4 21 1782 #define xgxs_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1783 #define xgxs_actualSpeedsMisc1_dr_13GHiGig_X4 23 1784 #define xgxs_actualSpeedsMisc1_dr_15GHiGig_X4 24 1785 #define xgxs_actualSpeedsMisc1_dr_16GHiGig_X4 25 1786 #define xgxs_actualSpeedsMisc1_dr_5000BRCM_X1 26 1787 #define xgxs_actualSpeedsMisc1_dr_6363BRCM_X1 27 1788 #define xgxs_actualSpeedsMisc1_dr_20GHiGig_X4 28 1789 #define xgxs_actualSpeedsMisc1_dr_21GHiGig_X4 29 1790 #define xgxs_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1791 #define xgxs_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1792 1793 /**************************************************************************** 1794 * Enums: xgxs_IndLaneModes 1795 */ 1796 #define xgxs_IndLaneModes_SWSDR_div2 0 1797 #define xgxs_IndLaneModes_SWSDR_div1 1 1798 #define xgxs_IndLaneModes_DWSDR_div2 2 1799 #define xgxs_IndLaneModes_DWSDR_div1 3 1800 1801 /**************************************************************************** 1802 * Enums: xgxs_prbsSelect 1803 */ 1804 #define xgxs_prbsSelect_prbs7 0 1805 #define xgxs_prbsSelect_prbs15 1 1806 #define xgxs_prbsSelect_prbs23 2 1807 #define xgxs_prbsSelect_prbs31 3 1808 1809 /**************************************************************************** 1810 * Enums: xgxs_vcoDivider 1811 */ 1812 #define xgxs_vcoDivider_div32 0 1813 #define xgxs_vcoDivider_div36 1 1814 #define xgxs_vcoDivider_div40 2 1815 #define xgxs_vcoDivider_div42 3 1816 #define xgxs_vcoDivider_div48 4 1817 #define xgxs_vcoDivider_div50 5 1818 #define xgxs_vcoDivider_div52 6 1819 #define xgxs_vcoDivider_div54 7 1820 #define xgxs_vcoDivider_div60 8 1821 #define xgxs_vcoDivider_div64 9 1822 #define xgxs_vcoDivider_div66 10 1823 #define xgxs_vcoDivider_div68 11 1824 #define xgxs_vcoDivider_div70 12 1825 #define xgxs_vcoDivider_div80 13 1826 #define xgxs_vcoDivider_div92 14 1827 #define xgxs_vcoDivider_div100 15 1828 1829 /**************************************************************************** 1830 * Enums: xgxs_refClkSelect 1831 */ 1832 #define xgxs_refClkSelect_clk_25MHz 0 1833 #define xgxs_refClkSelect_clk_100MHz 1 1834 #define xgxs_refClkSelect_clk_125MHz 2 1835 #define xgxs_refClkSelect_clk_156p25MHz 3 1836 #define xgxs_refClkSelect_clk_187p5MHz 4 1837 #define xgxs_refClkSelect_clk_161p25Mhz 5 1838 #define xgxs_refClkSelect_clk_50Mhz 6 1839 #define xgxs_refClkSelect_clk_106p25Mhz 7 1840 1841 /**************************************************************************** 1842 * Enums: xgxs_aerMMDdevTypeSelect 1843 */ 1844 #define xgxs_aerMMDdevTypeSelect_combo_core 0 1845 #define xgxs_aerMMDdevTypeSelect_PMA_PMD 1 1846 #define xgxs_aerMMDdevTypeSelect_PCS 3 1847 #define xgxs_aerMMDdevTypeSelect_PHY 4 1848 #define xgxs_aerMMDdevTypeSelect_DTE 5 1849 #define xgxs_aerMMDdevTypeSelect_CL73_AN 7 1850 1851 /**************************************************************************** 1852 * Enums: xgxs_aerMMDportSelect 1853 */ 1854 #define xgxs_aerMMDportSelect_ln0 0 1855 #define xgxs_aerMMDportSelect_ln1 1 1856 #define xgxs_aerMMDportSelect_ln2 2 1857 #define xgxs_aerMMDportSelect_ln3 3 1858 #define xgxs_aerMMDportSelect_BCST 511 1859 1860 /**************************************************************************** 1861 * Enums: xgxs_firmwareModeSelect 1862 */ 1863 #define xgxs_firmwareModeSelect_DEFAULT 0 1864 #define xgxs_firmwareModeSelect_SFP_OPT_LR 1 1865 #define xgxs_firmwareModeSelect_SFP_DAC 2 1866 #define xgxs_firmwareModeSelect_XLAUI 3 1867 #define xgxs_firmwareModeSelect_LONG_CH_6G 4 1868 1869 /**************************************************************************** 1870 * Enums: xgxs_tempIdxSelect 1871 */ 1872 #define xgxs_tempIdxSelect_LTE__22p9C 15 1873 #define xgxs_tempIdxSelect_LTE__12p6C 14 1874 #define xgxs_tempIdxSelect_LTE__3p0C 13 1875 #define xgxs_tempIdxSelect_LTE_6p7C 12 1876 #define xgxs_tempIdxSelect_LTE_16p4C 11 1877 #define xgxs_tempIdxSelect_LTE_26p6C 10 1878 #define xgxs_tempIdxSelect_LTE_36p3C 9 1879 #define xgxs_tempIdxSelect_LTE_46p0C 8 1880 #define xgxs_tempIdxSelect_LTE_56p2C 7 1881 #define xgxs_tempIdxSelect_LTE_65p9C 6 1882 #define xgxs_tempIdxSelect_LTE_75p6C 5 1883 #define xgxs_tempIdxSelect_LTE_85p3C 4 1884 #define xgxs_tempIdxSelect_LTE_95p5C 3 1885 #define xgxs_tempIdxSelect_LTE_105p2C 2 1886 #define xgxs_tempIdxSelect_LTE_114p9C 1 1887 #define xgxs_tempIdxSelect_LTE_125p1C 0 1888 1889 /**************************************************************************** 1890 * Enums: xgxs_IQP_Options 1891 */ 1892 #define xgxs_IQP_Options_i50uA 0 1893 #define xgxs_IQP_Options_i100uA 1 1894 #define xgxs_IQP_Options_i150uA 2 1895 #define xgxs_IQP_Options_i200uA 3 1896 #define xgxs_IQP_Options_i250uA 4 1897 #define xgxs_IQP_Options_i300uA 5 1898 #define xgxs_IQP_Options_i350uA 6 1899 #define xgxs_IQP_Options_i400uA 7 1900 #define xgxs_IQP_Options_i450uA 8 1901 #define xgxs_IQP_Options_i500uA 9 1902 #define xgxs_IQP_Options_i550uA 10 1903 #define xgxs_IQP_Options_i600uA 11 1904 #define xgxs_IQP_Options_i650uA 12 1905 #define xgxs_IQP_Options_i700uA 13 1906 #define xgxs_IQP_Options_i750uA 14 1907 #define xgxs_IQP_Options_i800uA 15 1908 1909 /**************************************************************************** 1910 * Enums: xgxs_IDriver_Options 1911 */ 1912 #define xgxs_IDriver_Options_v680mV 0 1913 #define xgxs_IDriver_Options_v730mV 1 1914 #define xgxs_IDriver_Options_v780mV 2 1915 #define xgxs_IDriver_Options_v830mV 3 1916 #define xgxs_IDriver_Options_v880mV 4 1917 #define xgxs_IDriver_Options_v930mV 5 1918 #define xgxs_IDriver_Options_v980mV 6 1919 #define xgxs_IDriver_Options_v1010mV 7 1920 #define xgxs_IDriver_Options_v1040mV 8 1921 #define xgxs_IDriver_Options_v1060mV 9 1922 #define xgxs_IDriver_Options_v1070mV 10 1923 #define xgxs_IDriver_Options_v1080mV 11 1924 #define xgxs_IDriver_Options_v1085mV 12 1925 #define xgxs_IDriver_Options_v1090mV 13 1926 #define xgxs_IDriver_Options_v1095mV 14 1927 #define xgxs_IDriver_Options_v1100mV 15 1928 1929 /**************************************************************************** 1930 * Enums: xgxsBlk0_operationModes 1931 */ 1932 #define xgxsBlk0_operationModes_XGXS 0 1933 #define xgxsBlk0_operationModes_XGXG_nCC 1 1934 #define xgxsBlk0_operationModes_IndLane_OS8 4 1935 #define xgxsBlk0_operationModes_IndLane_OS5 5 1936 #define xgxsBlk0_operationModes_PCI 7 1937 #define xgxsBlk0_operationModes_XGXS_nLQ 8 1938 #define xgxsBlk0_operationModes_XGXS_nLQnCC 9 1939 #define xgxsBlk0_operationModes_PBypass 10 1940 #define xgxsBlk0_operationModes_PBypass_nDSK 11 1941 #define xgxsBlk0_operationModes_ComboCoreMode 12 1942 #define xgxsBlk0_operationModes_Clocks_off 15 1943 1944 /**************************************************************************** 1945 * Enums: xgxsBlk0_actualSpeeds4 1946 */ 1947 #define xgxsBlk0_actualSpeeds4_dr_10M 0 1948 #define xgxsBlk0_actualSpeeds4_dr_100M 1 1949 #define xgxsBlk0_actualSpeeds4_dr_1G 2 1950 #define xgxsBlk0_actualSpeeds4_dr_2p5G 3 1951 #define xgxsBlk0_actualSpeeds4_dr_5G_X4 4 1952 #define xgxsBlk0_actualSpeeds4_dr_6G_X4 5 1953 #define xgxsBlk0_actualSpeeds4_dr_10G_HiG 6 1954 #define xgxsBlk0_actualSpeeds4_dr_10G_CX4 7 1955 #define xgxsBlk0_actualSpeeds4_dr_12G_HiG 8 1956 #define xgxsBlk0_actualSpeeds4_dr_12p5G_X4 9 1957 #define xgxsBlk0_actualSpeeds4_dr_13G_X4 10 1958 #define xgxsBlk0_actualSpeeds4_dr_15G_X4 11 1959 #define xgxsBlk0_actualSpeeds4_dr_16G_X4 12 1960 1961 /**************************************************************************** 1962 * Enums: xgxsBlk0_actualSpeeds5 1963 */ 1964 #define xgxsBlk0_actualSpeeds5_dr_10M 0 1965 #define xgxsBlk0_actualSpeeds5_dr_100M 1 1966 #define xgxsBlk0_actualSpeeds5_dr_1G 2 1967 #define xgxsBlk0_actualSpeeds5_dr_2p5G 3 1968 #define xgxsBlk0_actualSpeeds5_dr_5G_X4 4 1969 #define xgxsBlk0_actualSpeeds5_dr_6G_X4 5 1970 #define xgxsBlk0_actualSpeeds5_dr_10G_HiG 6 1971 #define xgxsBlk0_actualSpeeds5_dr_10G_CX4 7 1972 #define xgxsBlk0_actualSpeeds5_dr_12G_HiG 8 1973 #define xgxsBlk0_actualSpeeds5_dr_12p5G_X4 9 1974 #define xgxsBlk0_actualSpeeds5_dr_13G_X4 10 1975 #define xgxsBlk0_actualSpeeds5_dr_15G_X4 11 1976 #define xgxsBlk0_actualSpeeds5_dr_16G_X4 12 1977 #define xgxsBlk0_actualSpeeds5_dr_1G_KX 13 1978 #define xgxsBlk0_actualSpeeds5_dr_10G_KX4 14 1979 #define xgxsBlk0_actualSpeeds5_dr_10G_KR 15 1980 #define xgxsBlk0_actualSpeeds5_dr_5G 16 1981 #define xgxsBlk0_actualSpeeds5_dr_6p4G 17 1982 #define xgxsBlk0_actualSpeeds5_dr_20G_X4 18 1983 #define xgxsBlk0_actualSpeeds5_dr_21G_X4 19 1984 #define xgxsBlk0_actualSpeeds5_dr_25G_X4 20 1985 #define xgxsBlk0_actualSpeeds5_dr_10G_HiG_DXGXS 21 1986 #define xgxsBlk0_actualSpeeds5_dr_10G_DXGXS 22 1987 #define xgxsBlk0_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 1988 #define xgxsBlk0_actualSpeeds5_dr_10p5G_DXGXS 24 1989 #define xgxsBlk0_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 1990 #define xgxsBlk0_actualSpeeds5_dr_12p773G_DXGXS 26 1991 #define xgxsBlk0_actualSpeeds5_dr_10G_XFI 27 1992 #define xgxsBlk0_actualSpeeds5_dr_40G 28 1993 #define xgxsBlk0_actualSpeeds5_dr_20G_HiG_DXGXS 29 1994 #define xgxsBlk0_actualSpeeds5_dr_20G_DXGXS 30 1995 #define xgxsBlk0_actualSpeeds5_dr_10G_SFI 31 1996 #define xgxsBlk0_actualSpeeds5_dr_31p5G 32 1997 #define xgxsBlk0_actualSpeeds5_dr_32p7G 33 1998 #define xgxsBlk0_actualSpeeds5_dr_20G_SCR 34 1999 #define xgxsBlk0_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 2000 #define xgxsBlk0_actualSpeeds5_dr_10G_DXGXS_SCR 36 2001 #define xgxsBlk0_actualSpeeds5_dr_12G_R2 37 2002 #define xgxsBlk0_actualSpeeds5_dr_10G_X2 38 2003 #define xgxsBlk0_actualSpeeds5_dr_40G_KR4 39 2004 #define xgxsBlk0_actualSpeeds5_dr_40G_CR4 40 2005 #define xgxsBlk0_actualSpeeds5_dr_100G_CR10 41 2006 #define xgxsBlk0_actualSpeeds5_dr_15p75G_DXGXS 44 2007 #define xgxsBlk0_actualSpeeds5_dr_20G_KR2 57 2008 #define xgxsBlk0_actualSpeeds5_dr_20G_CR2 58 2009 2010 /**************************************************************************** 2011 * Enums: xgxsBlk0_actualSpeedsMisc1 2012 */ 2013 #define xgxsBlk0_actualSpeedsMisc1_dr_2500BRCM_X1 16 2014 #define xgxsBlk0_actualSpeedsMisc1_dr_5000BRCM_X4 17 2015 #define xgxsBlk0_actualSpeedsMisc1_dr_6000BRCM_X4 18 2016 #define xgxsBlk0_actualSpeedsMisc1_dr_10GHiGig_X4 19 2017 #define xgxsBlk0_actualSpeedsMisc1_dr_10GBASE_CX4 20 2018 #define xgxsBlk0_actualSpeedsMisc1_dr_12GHiGig_X4 21 2019 #define xgxsBlk0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2020 #define xgxsBlk0_actualSpeedsMisc1_dr_13GHiGig_X4 23 2021 #define xgxsBlk0_actualSpeedsMisc1_dr_15GHiGig_X4 24 2022 #define xgxsBlk0_actualSpeedsMisc1_dr_16GHiGig_X4 25 2023 #define xgxsBlk0_actualSpeedsMisc1_dr_5000BRCM_X1 26 2024 #define xgxsBlk0_actualSpeedsMisc1_dr_6363BRCM_X1 27 2025 #define xgxsBlk0_actualSpeedsMisc1_dr_20GHiGig_X4 28 2026 #define xgxsBlk0_actualSpeedsMisc1_dr_21GHiGig_X4 29 2027 #define xgxsBlk0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2028 #define xgxsBlk0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2029 2030 /**************************************************************************** 2031 * Enums: xgxsBlk0_IndLaneModes 2032 */ 2033 #define xgxsBlk0_IndLaneModes_SWSDR_div2 0 2034 #define xgxsBlk0_IndLaneModes_SWSDR_div1 1 2035 #define xgxsBlk0_IndLaneModes_DWSDR_div2 2 2036 #define xgxsBlk0_IndLaneModes_DWSDR_div1 3 2037 2038 /**************************************************************************** 2039 * Enums: xgxsBlk0_prbsSelect 2040 */ 2041 #define xgxsBlk0_prbsSelect_prbs7 0 2042 #define xgxsBlk0_prbsSelect_prbs15 1 2043 #define xgxsBlk0_prbsSelect_prbs23 2 2044 #define xgxsBlk0_prbsSelect_prbs31 3 2045 2046 /**************************************************************************** 2047 * Enums: xgxsBlk0_vcoDivider 2048 */ 2049 #define xgxsBlk0_vcoDivider_div32 0 2050 #define xgxsBlk0_vcoDivider_div36 1 2051 #define xgxsBlk0_vcoDivider_div40 2 2052 #define xgxsBlk0_vcoDivider_div42 3 2053 #define xgxsBlk0_vcoDivider_div48 4 2054 #define xgxsBlk0_vcoDivider_div50 5 2055 #define xgxsBlk0_vcoDivider_div52 6 2056 #define xgxsBlk0_vcoDivider_div54 7 2057 #define xgxsBlk0_vcoDivider_div60 8 2058 #define xgxsBlk0_vcoDivider_div64 9 2059 #define xgxsBlk0_vcoDivider_div66 10 2060 #define xgxsBlk0_vcoDivider_div68 11 2061 #define xgxsBlk0_vcoDivider_div70 12 2062 #define xgxsBlk0_vcoDivider_div80 13 2063 #define xgxsBlk0_vcoDivider_div92 14 2064 #define xgxsBlk0_vcoDivider_div100 15 2065 2066 /**************************************************************************** 2067 * Enums: xgxsBlk0_refClkSelect 2068 */ 2069 #define xgxsBlk0_refClkSelect_clk_25MHz 0 2070 #define xgxsBlk0_refClkSelect_clk_100MHz 1 2071 #define xgxsBlk0_refClkSelect_clk_125MHz 2 2072 #define xgxsBlk0_refClkSelect_clk_156p25MHz 3 2073 #define xgxsBlk0_refClkSelect_clk_187p5MHz 4 2074 #define xgxsBlk0_refClkSelect_clk_161p25Mhz 5 2075 #define xgxsBlk0_refClkSelect_clk_50Mhz 6 2076 #define xgxsBlk0_refClkSelect_clk_106p25Mhz 7 2077 2078 /**************************************************************************** 2079 * Enums: xgxsBlk0_aerMMDdevTypeSelect 2080 */ 2081 #define xgxsBlk0_aerMMDdevTypeSelect_combo_core 0 2082 #define xgxsBlk0_aerMMDdevTypeSelect_PMA_PMD 1 2083 #define xgxsBlk0_aerMMDdevTypeSelect_PCS 3 2084 #define xgxsBlk0_aerMMDdevTypeSelect_PHY 4 2085 #define xgxsBlk0_aerMMDdevTypeSelect_DTE 5 2086 #define xgxsBlk0_aerMMDdevTypeSelect_CL73_AN 7 2087 2088 /**************************************************************************** 2089 * Enums: xgxsBlk0_aerMMDportSelect 2090 */ 2091 #define xgxsBlk0_aerMMDportSelect_ln0 0 2092 #define xgxsBlk0_aerMMDportSelect_ln1 1 2093 #define xgxsBlk0_aerMMDportSelect_ln2 2 2094 #define xgxsBlk0_aerMMDportSelect_ln3 3 2095 #define xgxsBlk0_aerMMDportSelect_BCST 511 2096 2097 /**************************************************************************** 2098 * Enums: xgxsBlk0_firmwareModeSelect 2099 */ 2100 #define xgxsBlk0_firmwareModeSelect_DEFAULT 0 2101 #define xgxsBlk0_firmwareModeSelect_SFP_OPT_LR 1 2102 #define xgxsBlk0_firmwareModeSelect_SFP_DAC 2 2103 #define xgxsBlk0_firmwareModeSelect_XLAUI 3 2104 #define xgxsBlk0_firmwareModeSelect_LONG_CH_6G 4 2105 2106 /**************************************************************************** 2107 * Enums: xgxsBlk0_tempIdxSelect 2108 */ 2109 #define xgxsBlk0_tempIdxSelect_LTE__22p9C 15 2110 #define xgxsBlk0_tempIdxSelect_LTE__12p6C 14 2111 #define xgxsBlk0_tempIdxSelect_LTE__3p0C 13 2112 #define xgxsBlk0_tempIdxSelect_LTE_6p7C 12 2113 #define xgxsBlk0_tempIdxSelect_LTE_16p4C 11 2114 #define xgxsBlk0_tempIdxSelect_LTE_26p6C 10 2115 #define xgxsBlk0_tempIdxSelect_LTE_36p3C 9 2116 #define xgxsBlk0_tempIdxSelect_LTE_46p0C 8 2117 #define xgxsBlk0_tempIdxSelect_LTE_56p2C 7 2118 #define xgxsBlk0_tempIdxSelect_LTE_65p9C 6 2119 #define xgxsBlk0_tempIdxSelect_LTE_75p6C 5 2120 #define xgxsBlk0_tempIdxSelect_LTE_85p3C 4 2121 #define xgxsBlk0_tempIdxSelect_LTE_95p5C 3 2122 #define xgxsBlk0_tempIdxSelect_LTE_105p2C 2 2123 #define xgxsBlk0_tempIdxSelect_LTE_114p9C 1 2124 #define xgxsBlk0_tempIdxSelect_LTE_125p1C 0 2125 2126 /**************************************************************************** 2127 * Enums: xgxsBlk1_operationModes 2128 */ 2129 #define xgxsBlk1_operationModes_XGXS 0 2130 #define xgxsBlk1_operationModes_XGXG_nCC 1 2131 #define xgxsBlk1_operationModes_IndLane_OS8 4 2132 #define xgxsBlk1_operationModes_IndLane_OS5 5 2133 #define xgxsBlk1_operationModes_PCI 7 2134 #define xgxsBlk1_operationModes_XGXS_nLQ 8 2135 #define xgxsBlk1_operationModes_XGXS_nLQnCC 9 2136 #define xgxsBlk1_operationModes_PBypass 10 2137 #define xgxsBlk1_operationModes_PBypass_nDSK 11 2138 #define xgxsBlk1_operationModes_ComboCoreMode 12 2139 #define xgxsBlk1_operationModes_Clocks_off 15 2140 2141 /**************************************************************************** 2142 * Enums: xgxsBlk1_actualSpeeds4 2143 */ 2144 #define xgxsBlk1_actualSpeeds4_dr_10M 0 2145 #define xgxsBlk1_actualSpeeds4_dr_100M 1 2146 #define xgxsBlk1_actualSpeeds4_dr_1G 2 2147 #define xgxsBlk1_actualSpeeds4_dr_2p5G 3 2148 #define xgxsBlk1_actualSpeeds4_dr_5G_X4 4 2149 #define xgxsBlk1_actualSpeeds4_dr_6G_X4 5 2150 #define xgxsBlk1_actualSpeeds4_dr_10G_HiG 6 2151 #define xgxsBlk1_actualSpeeds4_dr_10G_CX4 7 2152 #define xgxsBlk1_actualSpeeds4_dr_12G_HiG 8 2153 #define xgxsBlk1_actualSpeeds4_dr_12p5G_X4 9 2154 #define xgxsBlk1_actualSpeeds4_dr_13G_X4 10 2155 #define xgxsBlk1_actualSpeeds4_dr_15G_X4 11 2156 #define xgxsBlk1_actualSpeeds4_dr_16G_X4 12 2157 2158 /**************************************************************************** 2159 * Enums: xgxsBlk1_actualSpeeds5 2160 */ 2161 #define xgxsBlk1_actualSpeeds5_dr_10M 0 2162 #define xgxsBlk1_actualSpeeds5_dr_100M 1 2163 #define xgxsBlk1_actualSpeeds5_dr_1G 2 2164 #define xgxsBlk1_actualSpeeds5_dr_2p5G 3 2165 #define xgxsBlk1_actualSpeeds5_dr_5G_X4 4 2166 #define xgxsBlk1_actualSpeeds5_dr_6G_X4 5 2167 #define xgxsBlk1_actualSpeeds5_dr_10G_HiG 6 2168 #define xgxsBlk1_actualSpeeds5_dr_10G_CX4 7 2169 #define xgxsBlk1_actualSpeeds5_dr_12G_HiG 8 2170 #define xgxsBlk1_actualSpeeds5_dr_12p5G_X4 9 2171 #define xgxsBlk1_actualSpeeds5_dr_13G_X4 10 2172 #define xgxsBlk1_actualSpeeds5_dr_15G_X4 11 2173 #define xgxsBlk1_actualSpeeds5_dr_16G_X4 12 2174 #define xgxsBlk1_actualSpeeds5_dr_1G_KX 13 2175 #define xgxsBlk1_actualSpeeds5_dr_10G_KX4 14 2176 #define xgxsBlk1_actualSpeeds5_dr_10G_KR 15 2177 #define xgxsBlk1_actualSpeeds5_dr_5G 16 2178 #define xgxsBlk1_actualSpeeds5_dr_6p4G 17 2179 #define xgxsBlk1_actualSpeeds5_dr_20G_X4 18 2180 #define xgxsBlk1_actualSpeeds5_dr_21G_X4 19 2181 #define xgxsBlk1_actualSpeeds5_dr_25G_X4 20 2182 #define xgxsBlk1_actualSpeeds5_dr_10G_HiG_DXGXS 21 2183 #define xgxsBlk1_actualSpeeds5_dr_10G_DXGXS 22 2184 #define xgxsBlk1_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 2185 #define xgxsBlk1_actualSpeeds5_dr_10p5G_DXGXS 24 2186 #define xgxsBlk1_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 2187 #define xgxsBlk1_actualSpeeds5_dr_12p773G_DXGXS 26 2188 #define xgxsBlk1_actualSpeeds5_dr_10G_XFI 27 2189 #define xgxsBlk1_actualSpeeds5_dr_40G 28 2190 #define xgxsBlk1_actualSpeeds5_dr_20G_HiG_DXGXS 29 2191 #define xgxsBlk1_actualSpeeds5_dr_20G_DXGXS 30 2192 #define xgxsBlk1_actualSpeeds5_dr_10G_SFI 31 2193 #define xgxsBlk1_actualSpeeds5_dr_31p5G 32 2194 #define xgxsBlk1_actualSpeeds5_dr_32p7G 33 2195 #define xgxsBlk1_actualSpeeds5_dr_20G_SCR 34 2196 #define xgxsBlk1_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 2197 #define xgxsBlk1_actualSpeeds5_dr_10G_DXGXS_SCR 36 2198 #define xgxsBlk1_actualSpeeds5_dr_12G_R2 37 2199 #define xgxsBlk1_actualSpeeds5_dr_10G_X2 38 2200 #define xgxsBlk1_actualSpeeds5_dr_40G_KR4 39 2201 #define xgxsBlk1_actualSpeeds5_dr_40G_CR4 40 2202 #define xgxsBlk1_actualSpeeds5_dr_100G_CR10 41 2203 #define xgxsBlk1_actualSpeeds5_dr_15p75G_DXGXS 44 2204 #define xgxsBlk1_actualSpeeds5_dr_20G_KR2 57 2205 #define xgxsBlk1_actualSpeeds5_dr_20G_CR2 58 2206 2207 /**************************************************************************** 2208 * Enums: xgxsBlk1_actualSpeedsMisc1 2209 */ 2210 #define xgxsBlk1_actualSpeedsMisc1_dr_2500BRCM_X1 16 2211 #define xgxsBlk1_actualSpeedsMisc1_dr_5000BRCM_X4 17 2212 #define xgxsBlk1_actualSpeedsMisc1_dr_6000BRCM_X4 18 2213 #define xgxsBlk1_actualSpeedsMisc1_dr_10GHiGig_X4 19 2214 #define xgxsBlk1_actualSpeedsMisc1_dr_10GBASE_CX4 20 2215 #define xgxsBlk1_actualSpeedsMisc1_dr_12GHiGig_X4 21 2216 #define xgxsBlk1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2217 #define xgxsBlk1_actualSpeedsMisc1_dr_13GHiGig_X4 23 2218 #define xgxsBlk1_actualSpeedsMisc1_dr_15GHiGig_X4 24 2219 #define xgxsBlk1_actualSpeedsMisc1_dr_16GHiGig_X4 25 2220 #define xgxsBlk1_actualSpeedsMisc1_dr_5000BRCM_X1 26 2221 #define xgxsBlk1_actualSpeedsMisc1_dr_6363BRCM_X1 27 2222 #define xgxsBlk1_actualSpeedsMisc1_dr_20GHiGig_X4 28 2223 #define xgxsBlk1_actualSpeedsMisc1_dr_21GHiGig_X4 29 2224 #define xgxsBlk1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2225 #define xgxsBlk1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2226 2227 /**************************************************************************** 2228 * Enums: xgxsBlk1_IndLaneModes 2229 */ 2230 #define xgxsBlk1_IndLaneModes_SWSDR_div2 0 2231 #define xgxsBlk1_IndLaneModes_SWSDR_div1 1 2232 #define xgxsBlk1_IndLaneModes_DWSDR_div2 2 2233 #define xgxsBlk1_IndLaneModes_DWSDR_div1 3 2234 2235 /**************************************************************************** 2236 * Enums: xgxsBlk1_prbsSelect 2237 */ 2238 #define xgxsBlk1_prbsSelect_prbs7 0 2239 #define xgxsBlk1_prbsSelect_prbs15 1 2240 #define xgxsBlk1_prbsSelect_prbs23 2 2241 #define xgxsBlk1_prbsSelect_prbs31 3 2242 2243 /**************************************************************************** 2244 * Enums: xgxsBlk1_vcoDivider 2245 */ 2246 #define xgxsBlk1_vcoDivider_div32 0 2247 #define xgxsBlk1_vcoDivider_div36 1 2248 #define xgxsBlk1_vcoDivider_div40 2 2249 #define xgxsBlk1_vcoDivider_div42 3 2250 #define xgxsBlk1_vcoDivider_div48 4 2251 #define xgxsBlk1_vcoDivider_div50 5 2252 #define xgxsBlk1_vcoDivider_div52 6 2253 #define xgxsBlk1_vcoDivider_div54 7 2254 #define xgxsBlk1_vcoDivider_div60 8 2255 #define xgxsBlk1_vcoDivider_div64 9 2256 #define xgxsBlk1_vcoDivider_div66 10 2257 #define xgxsBlk1_vcoDivider_div68 11 2258 #define xgxsBlk1_vcoDivider_div70 12 2259 #define xgxsBlk1_vcoDivider_div80 13 2260 #define xgxsBlk1_vcoDivider_div92 14 2261 #define xgxsBlk1_vcoDivider_div100 15 2262 2263 /**************************************************************************** 2264 * Enums: xgxsBlk1_refClkSelect 2265 */ 2266 #define xgxsBlk1_refClkSelect_clk_25MHz 0 2267 #define xgxsBlk1_refClkSelect_clk_100MHz 1 2268 #define xgxsBlk1_refClkSelect_clk_125MHz 2 2269 #define xgxsBlk1_refClkSelect_clk_156p25MHz 3 2270 #define xgxsBlk1_refClkSelect_clk_187p5MHz 4 2271 #define xgxsBlk1_refClkSelect_clk_161p25Mhz 5 2272 #define xgxsBlk1_refClkSelect_clk_50Mhz 6 2273 #define xgxsBlk1_refClkSelect_clk_106p25Mhz 7 2274 2275 /**************************************************************************** 2276 * Enums: xgxsBlk1_aerMMDdevTypeSelect 2277 */ 2278 #define xgxsBlk1_aerMMDdevTypeSelect_combo_core 0 2279 #define xgxsBlk1_aerMMDdevTypeSelect_PMA_PMD 1 2280 #define xgxsBlk1_aerMMDdevTypeSelect_PCS 3 2281 #define xgxsBlk1_aerMMDdevTypeSelect_PHY 4 2282 #define xgxsBlk1_aerMMDdevTypeSelect_DTE 5 2283 #define xgxsBlk1_aerMMDdevTypeSelect_CL73_AN 7 2284 2285 /**************************************************************************** 2286 * Enums: xgxsBlk1_aerMMDportSelect 2287 */ 2288 #define xgxsBlk1_aerMMDportSelect_ln0 0 2289 #define xgxsBlk1_aerMMDportSelect_ln1 1 2290 #define xgxsBlk1_aerMMDportSelect_ln2 2 2291 #define xgxsBlk1_aerMMDportSelect_ln3 3 2292 #define xgxsBlk1_aerMMDportSelect_BCST 511 2293 2294 /**************************************************************************** 2295 * Enums: xgxsBlk1_firmwareModeSelect 2296 */ 2297 #define xgxsBlk1_firmwareModeSelect_DEFAULT 0 2298 #define xgxsBlk1_firmwareModeSelect_SFP_OPT_LR 1 2299 #define xgxsBlk1_firmwareModeSelect_SFP_DAC 2 2300 #define xgxsBlk1_firmwareModeSelect_XLAUI 3 2301 #define xgxsBlk1_firmwareModeSelect_LONG_CH_6G 4 2302 2303 /**************************************************************************** 2304 * Enums: xgxsBlk1_tempIdxSelect 2305 */ 2306 #define xgxsBlk1_tempIdxSelect_LTE__22p9C 15 2307 #define xgxsBlk1_tempIdxSelect_LTE__12p6C 14 2308 #define xgxsBlk1_tempIdxSelect_LTE__3p0C 13 2309 #define xgxsBlk1_tempIdxSelect_LTE_6p7C 12 2310 #define xgxsBlk1_tempIdxSelect_LTE_16p4C 11 2311 #define xgxsBlk1_tempIdxSelect_LTE_26p6C 10 2312 #define xgxsBlk1_tempIdxSelect_LTE_36p3C 9 2313 #define xgxsBlk1_tempIdxSelect_LTE_46p0C 8 2314 #define xgxsBlk1_tempIdxSelect_LTE_56p2C 7 2315 #define xgxsBlk1_tempIdxSelect_LTE_65p9C 6 2316 #define xgxsBlk1_tempIdxSelect_LTE_75p6C 5 2317 #define xgxsBlk1_tempIdxSelect_LTE_85p3C 4 2318 #define xgxsBlk1_tempIdxSelect_LTE_95p5C 3 2319 #define xgxsBlk1_tempIdxSelect_LTE_105p2C 2 2320 #define xgxsBlk1_tempIdxSelect_LTE_114p9C 1 2321 #define xgxsBlk1_tempIdxSelect_LTE_125p1C 0 2322 2323 /**************************************************************************** 2324 * Enums: xgxsBlk2_operationModes 2325 */ 2326 #define xgxsBlk2_operationModes_XGXS 0 2327 #define xgxsBlk2_operationModes_XGXG_nCC 1 2328 #define xgxsBlk2_operationModes_IndLane_OS8 4 2329 #define xgxsBlk2_operationModes_IndLane_OS5 5 2330 #define xgxsBlk2_operationModes_PCI 7 2331 #define xgxsBlk2_operationModes_XGXS_nLQ 8 2332 #define xgxsBlk2_operationModes_XGXS_nLQnCC 9 2333 #define xgxsBlk2_operationModes_PBypass 10 2334 #define xgxsBlk2_operationModes_PBypass_nDSK 11 2335 #define xgxsBlk2_operationModes_ComboCoreMode 12 2336 #define xgxsBlk2_operationModes_Clocks_off 15 2337 2338 /**************************************************************************** 2339 * Enums: xgxsBlk2_actualSpeeds4 2340 */ 2341 #define xgxsBlk2_actualSpeeds4_dr_10M 0 2342 #define xgxsBlk2_actualSpeeds4_dr_100M 1 2343 #define xgxsBlk2_actualSpeeds4_dr_1G 2 2344 #define xgxsBlk2_actualSpeeds4_dr_2p5G 3 2345 #define xgxsBlk2_actualSpeeds4_dr_5G_X4 4 2346 #define xgxsBlk2_actualSpeeds4_dr_6G_X4 5 2347 #define xgxsBlk2_actualSpeeds4_dr_10G_HiG 6 2348 #define xgxsBlk2_actualSpeeds4_dr_10G_CX4 7 2349 #define xgxsBlk2_actualSpeeds4_dr_12G_HiG 8 2350 #define xgxsBlk2_actualSpeeds4_dr_12p5G_X4 9 2351 #define xgxsBlk2_actualSpeeds4_dr_13G_X4 10 2352 #define xgxsBlk2_actualSpeeds4_dr_15G_X4 11 2353 #define xgxsBlk2_actualSpeeds4_dr_16G_X4 12 2354 2355 /**************************************************************************** 2356 * Enums: xgxsBlk2_actualSpeeds5 2357 */ 2358 #define xgxsBlk2_actualSpeeds5_dr_10M 0 2359 #define xgxsBlk2_actualSpeeds5_dr_100M 1 2360 #define xgxsBlk2_actualSpeeds5_dr_1G 2 2361 #define xgxsBlk2_actualSpeeds5_dr_2p5G 3 2362 #define xgxsBlk2_actualSpeeds5_dr_5G_X4 4 2363 #define xgxsBlk2_actualSpeeds5_dr_6G_X4 5 2364 #define xgxsBlk2_actualSpeeds5_dr_10G_HiG 6 2365 #define xgxsBlk2_actualSpeeds5_dr_10G_CX4 7 2366 #define xgxsBlk2_actualSpeeds5_dr_12G_HiG 8 2367 #define xgxsBlk2_actualSpeeds5_dr_12p5G_X4 9 2368 #define xgxsBlk2_actualSpeeds5_dr_13G_X4 10 2369 #define xgxsBlk2_actualSpeeds5_dr_15G_X4 11 2370 #define xgxsBlk2_actualSpeeds5_dr_16G_X4 12 2371 #define xgxsBlk2_actualSpeeds5_dr_1G_KX 13 2372 #define xgxsBlk2_actualSpeeds5_dr_10G_KX4 14 2373 #define xgxsBlk2_actualSpeeds5_dr_10G_KR 15 2374 #define xgxsBlk2_actualSpeeds5_dr_5G 16 2375 #define xgxsBlk2_actualSpeeds5_dr_6p4G 17 2376 #define xgxsBlk2_actualSpeeds5_dr_20G_X4 18 2377 #define xgxsBlk2_actualSpeeds5_dr_21G_X4 19 2378 #define xgxsBlk2_actualSpeeds5_dr_25G_X4 20 2379 #define xgxsBlk2_actualSpeeds5_dr_10G_HiG_DXGXS 21 2380 #define xgxsBlk2_actualSpeeds5_dr_10G_DXGXS 22 2381 #define xgxsBlk2_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 2382 #define xgxsBlk2_actualSpeeds5_dr_10p5G_DXGXS 24 2383 #define xgxsBlk2_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 2384 #define xgxsBlk2_actualSpeeds5_dr_12p773G_DXGXS 26 2385 #define xgxsBlk2_actualSpeeds5_dr_10G_XFI 27 2386 #define xgxsBlk2_actualSpeeds5_dr_40G 28 2387 #define xgxsBlk2_actualSpeeds5_dr_20G_HiG_DXGXS 29 2388 #define xgxsBlk2_actualSpeeds5_dr_20G_DXGXS 30 2389 #define xgxsBlk2_actualSpeeds5_dr_10G_SFI 31 2390 #define xgxsBlk2_actualSpeeds5_dr_31p5G 32 2391 #define xgxsBlk2_actualSpeeds5_dr_32p7G 33 2392 #define xgxsBlk2_actualSpeeds5_dr_20G_SCR 34 2393 #define xgxsBlk2_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 2394 #define xgxsBlk2_actualSpeeds5_dr_10G_DXGXS_SCR 36 2395 #define xgxsBlk2_actualSpeeds5_dr_12G_R2 37 2396 #define xgxsBlk2_actualSpeeds5_dr_10G_X2 38 2397 #define xgxsBlk2_actualSpeeds5_dr_40G_KR4 39 2398 #define xgxsBlk2_actualSpeeds5_dr_40G_CR4 40 2399 #define xgxsBlk2_actualSpeeds5_dr_100G_CR10 41 2400 #define xgxsBlk2_actualSpeeds5_dr_15p75G_DXGXS 44 2401 #define xgxsBlk2_actualSpeeds5_dr_20G_KR2 57 2402 #define xgxsBlk2_actualSpeeds5_dr_20G_CR2 58 2403 2404 /**************************************************************************** 2405 * Enums: xgxsBlk2_actualSpeedsMisc1 2406 */ 2407 #define xgxsBlk2_actualSpeedsMisc1_dr_2500BRCM_X1 16 2408 #define xgxsBlk2_actualSpeedsMisc1_dr_5000BRCM_X4 17 2409 #define xgxsBlk2_actualSpeedsMisc1_dr_6000BRCM_X4 18 2410 #define xgxsBlk2_actualSpeedsMisc1_dr_10GHiGig_X4 19 2411 #define xgxsBlk2_actualSpeedsMisc1_dr_10GBASE_CX4 20 2412 #define xgxsBlk2_actualSpeedsMisc1_dr_12GHiGig_X4 21 2413 #define xgxsBlk2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2414 #define xgxsBlk2_actualSpeedsMisc1_dr_13GHiGig_X4 23 2415 #define xgxsBlk2_actualSpeedsMisc1_dr_15GHiGig_X4 24 2416 #define xgxsBlk2_actualSpeedsMisc1_dr_16GHiGig_X4 25 2417 #define xgxsBlk2_actualSpeedsMisc1_dr_5000BRCM_X1 26 2418 #define xgxsBlk2_actualSpeedsMisc1_dr_6363BRCM_X1 27 2419 #define xgxsBlk2_actualSpeedsMisc1_dr_20GHiGig_X4 28 2420 #define xgxsBlk2_actualSpeedsMisc1_dr_21GHiGig_X4 29 2421 #define xgxsBlk2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2422 #define xgxsBlk2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2423 2424 /**************************************************************************** 2425 * Enums: xgxsBlk2_IndLaneModes 2426 */ 2427 #define xgxsBlk2_IndLaneModes_SWSDR_div2 0 2428 #define xgxsBlk2_IndLaneModes_SWSDR_div1 1 2429 #define xgxsBlk2_IndLaneModes_DWSDR_div2 2 2430 #define xgxsBlk2_IndLaneModes_DWSDR_div1 3 2431 2432 /**************************************************************************** 2433 * Enums: xgxsBlk2_prbsSelect 2434 */ 2435 #define xgxsBlk2_prbsSelect_prbs7 0 2436 #define xgxsBlk2_prbsSelect_prbs15 1 2437 #define xgxsBlk2_prbsSelect_prbs23 2 2438 #define xgxsBlk2_prbsSelect_prbs31 3 2439 2440 /**************************************************************************** 2441 * Enums: xgxsBlk2_vcoDivider 2442 */ 2443 #define xgxsBlk2_vcoDivider_div32 0 2444 #define xgxsBlk2_vcoDivider_div36 1 2445 #define xgxsBlk2_vcoDivider_div40 2 2446 #define xgxsBlk2_vcoDivider_div42 3 2447 #define xgxsBlk2_vcoDivider_div48 4 2448 #define xgxsBlk2_vcoDivider_div50 5 2449 #define xgxsBlk2_vcoDivider_div52 6 2450 #define xgxsBlk2_vcoDivider_div54 7 2451 #define xgxsBlk2_vcoDivider_div60 8 2452 #define xgxsBlk2_vcoDivider_div64 9 2453 #define xgxsBlk2_vcoDivider_div66 10 2454 #define xgxsBlk2_vcoDivider_div68 11 2455 #define xgxsBlk2_vcoDivider_div70 12 2456 #define xgxsBlk2_vcoDivider_div80 13 2457 #define xgxsBlk2_vcoDivider_div92 14 2458 #define xgxsBlk2_vcoDivider_div100 15 2459 2460 /**************************************************************************** 2461 * Enums: xgxsBlk2_refClkSelect 2462 */ 2463 #define xgxsBlk2_refClkSelect_clk_25MHz 0 2464 #define xgxsBlk2_refClkSelect_clk_100MHz 1 2465 #define xgxsBlk2_refClkSelect_clk_125MHz 2 2466 #define xgxsBlk2_refClkSelect_clk_156p25MHz 3 2467 #define xgxsBlk2_refClkSelect_clk_187p5MHz 4 2468 #define xgxsBlk2_refClkSelect_clk_161p25Mhz 5 2469 #define xgxsBlk2_refClkSelect_clk_50Mhz 6 2470 #define xgxsBlk2_refClkSelect_clk_106p25Mhz 7 2471 2472 /**************************************************************************** 2473 * Enums: xgxsBlk2_aerMMDdevTypeSelect 2474 */ 2475 #define xgxsBlk2_aerMMDdevTypeSelect_combo_core 0 2476 #define xgxsBlk2_aerMMDdevTypeSelect_PMA_PMD 1 2477 #define xgxsBlk2_aerMMDdevTypeSelect_PCS 3 2478 #define xgxsBlk2_aerMMDdevTypeSelect_PHY 4 2479 #define xgxsBlk2_aerMMDdevTypeSelect_DTE 5 2480 #define xgxsBlk2_aerMMDdevTypeSelect_CL73_AN 7 2481 2482 /**************************************************************************** 2483 * Enums: xgxsBlk2_aerMMDportSelect 2484 */ 2485 #define xgxsBlk2_aerMMDportSelect_ln0 0 2486 #define xgxsBlk2_aerMMDportSelect_ln1 1 2487 #define xgxsBlk2_aerMMDportSelect_ln2 2 2488 #define xgxsBlk2_aerMMDportSelect_ln3 3 2489 #define xgxsBlk2_aerMMDportSelect_BCST 511 2490 2491 /**************************************************************************** 2492 * Enums: xgxsBlk2_firmwareModeSelect 2493 */ 2494 #define xgxsBlk2_firmwareModeSelect_DEFAULT 0 2495 #define xgxsBlk2_firmwareModeSelect_SFP_OPT_LR 1 2496 #define xgxsBlk2_firmwareModeSelect_SFP_DAC 2 2497 #define xgxsBlk2_firmwareModeSelect_XLAUI 3 2498 #define xgxsBlk2_firmwareModeSelect_LONG_CH_6G 4 2499 2500 /**************************************************************************** 2501 * Enums: xgxsBlk2_tempIdxSelect 2502 */ 2503 #define xgxsBlk2_tempIdxSelect_LTE__22p9C 15 2504 #define xgxsBlk2_tempIdxSelect_LTE__12p6C 14 2505 #define xgxsBlk2_tempIdxSelect_LTE__3p0C 13 2506 #define xgxsBlk2_tempIdxSelect_LTE_6p7C 12 2507 #define xgxsBlk2_tempIdxSelect_LTE_16p4C 11 2508 #define xgxsBlk2_tempIdxSelect_LTE_26p6C 10 2509 #define xgxsBlk2_tempIdxSelect_LTE_36p3C 9 2510 #define xgxsBlk2_tempIdxSelect_LTE_46p0C 8 2511 #define xgxsBlk2_tempIdxSelect_LTE_56p2C 7 2512 #define xgxsBlk2_tempIdxSelect_LTE_65p9C 6 2513 #define xgxsBlk2_tempIdxSelect_LTE_75p6C 5 2514 #define xgxsBlk2_tempIdxSelect_LTE_85p3C 4 2515 #define xgxsBlk2_tempIdxSelect_LTE_95p5C 3 2516 #define xgxsBlk2_tempIdxSelect_LTE_105p2C 2 2517 #define xgxsBlk2_tempIdxSelect_LTE_114p9C 1 2518 #define xgxsBlk2_tempIdxSelect_LTE_125p1C 0 2519 2520 /**************************************************************************** 2521 * Enums: xgxsBlk4_operationModes 2522 */ 2523 #define xgxsBlk4_operationModes_XGXS 0 2524 #define xgxsBlk4_operationModes_XGXG_nCC 1 2525 #define xgxsBlk4_operationModes_LndLane_OS8 4 2526 #define xgxsBlk4_operationModes_IndLane_OS5 5 2527 #define xgxsBlk4_operationModes_PCI 7 2528 #define xgxsBlk4_operationModes_XGXS_nLQ 8 2529 #define xgxsBlk4_operationModes_XGXS_nLQnCC 9 2530 #define xgxsBlk4_operationModes_PBypass 10 2531 #define xgxsBlk4_operationModes_PBypass_nDSK 11 2532 #define xgxsBlk4_operationModes_ComboCoreMode 12 2533 #define xgxsBlk4_operationModes_Clocks_off 15 2534 2535 /**************************************************************************** 2536 * Enums: xgxsBlk4_actualSpeeds4 2537 */ 2538 #define xgxsBlk4_actualSpeeds4_dr_10M 0 2539 #define xgxsBlk4_actualSpeeds4_dr_100M 1 2540 #define xgxsBlk4_actualSpeeds4_dr_1G 2 2541 #define xgxsBlk4_actualSpeeds4_dr_2p5G 3 2542 #define xgxsBlk4_actualSpeeds4_dr_5G_X4 4 2543 #define xgxsBlk4_actualSpeeds4_dr_6G_X4 5 2544 #define xgxsBlk4_actualSpeeds4_dr_10G_HiG 6 2545 #define xgxsBlk4_actualSpeeds4_dr_10G_CX4 7 2546 #define xgxsBlk4_actualSpeeds4_dr_12G_HiG 8 2547 #define xgxsBlk4_actualSpeeds4_dr_12p5G_X4 9 2548 #define xgxsBlk4_actualSpeeds4_dr_13G_X4 10 2549 #define xgxsBlk4_actualSpeeds4_dr_15G_X4 11 2550 #define xgxsBlk4_actualSpeeds4_dr_16G_X4 12 2551 2552 /**************************************************************************** 2553 * Enums: xgxsBlk4_actualSpeeds5 2554 */ 2555 #define xgxsBlk4_actualSpeeds5_dr_10M 0 2556 #define xgxsBlk4_actualSpeeds5_dr_100M 1 2557 #define xgxsBlk4_actualSpeeds5_dr_1G 2 2558 #define xgxsBlk4_actualSpeeds5_dr_2p5G 3 2559 #define xgxsBlk4_actualSpeeds5_dr_5G_X4 4 2560 #define xgxsBlk4_actualSpeeds5_dr_6G_X4 5 2561 #define xgxsBlk4_actualSpeeds5_dr_10G_HiG 6 2562 #define xgxsBlk4_actualSpeeds5_dr_10G_CX4 7 2563 #define xgxsBlk4_actualSpeeds5_dr_12G_HiG 8 2564 #define xgxsBlk4_actualSpeeds5_dr_12p5G_X4 9 2565 #define xgxsBlk4_actualSpeeds5_dr_13G_X4 10 2566 #define xgxsBlk4_actualSpeeds5_dr_15G_X4 11 2567 #define xgxsBlk4_actualSpeeds5_dr_16G_X4 12 2568 #define xgxsBlk4_actualSpeeds5_dr_1G_KX 13 2569 #define xgxsBlk4_actualSpeeds5_dr_10G_KX4 14 2570 #define xgxsBlk4_actualSpeeds5_dr_10G_KR 15 2571 #define xgxsBlk4_actualSpeeds5_dr_5G 16 2572 #define xgxsBlk4_actualSpeeds5_dr_6p4G 17 2573 #define xgxsBlk4_actualSpeeds5_dr_20G_X4 18 2574 #define xgxsBlk4_actualSpeeds5_dr_21G_X4 19 2575 #define xgxsBlk4_actualSpeeds5_dr_25G_X4 20 2576 #define xgxsBlk4_actualSpeeds5_dr_10G_HiG_DXGXS 21 2577 #define xgxsBlk4_actualSpeeds5_dr_10G_DXGXS 22 2578 #define xgxsBlk4_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 2579 #define xgxsBlk4_actualSpeeds5_dr_10p5G_DXGXS 24 2580 #define xgxsBlk4_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 2581 #define xgxsBlk4_actualSpeeds5_dr_12p773G_DXGXS 26 2582 #define xgxsBlk4_actualSpeeds5_dr_10G_XFI 27 2583 #define xgxsBlk4_actualSpeeds5_dr_40G 28 2584 #define xgxsBlk4_actualSpeeds5_dr_20G_HiG_DXGXS 29 2585 #define xgxsBlk4_actualSpeeds5_dr_20G_DXGXS 30 2586 #define xgxsBlk4_actualSpeeds5_dr_10G_SFI 31 2587 #define xgxsBlk4_actualSpeeds5_dr_31p5G 32 2588 #define xgxsBlk4_actualSpeeds5_dr_32p7G 33 2589 #define xgxsBlk4_actualSpeeds5_dr_20G_SCR 34 2590 #define xgxsBlk4_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 2591 #define xgxsBlk4_actualSpeeds5_dr_10G_DXGXS_SCR 36 2592 #define xgxsBlk4_actualSpeeds5_dr_12G_R2 37 2593 #define xgxsBlk4_actualSpeeds5_dr_10G_X2 38 2594 #define xgxsBlk4_actualSpeeds5_dr_40G_KR4 39 2595 #define xgxsBlk4_actualSpeeds5_dr_40G_CR4 40 2596 #define xgxsBlk4_actualSpeeds5_dr_100G_CR10 41 2597 #define xgxsBlk4_actualSpeeds5_dr_15p75G_DXGXS 44 2598 #define xgxsBlk4_actualSpeeds5_dr_20G_KR2 57 2599 #define xgxsBlk4_actualSpeeds5_dr_20G_CR2 58 2600 2601 /**************************************************************************** 2602 * Enums: xgxsBlk4_actualSpeedsMisc1 2603 */ 2604 #define xgxsBlk4_actualSpeedsMisc1_dr_2500BRCM_X1 16 2605 #define xgxsBlk4_actualSpeedsMisc1_dr_5000BRCM_X4 17 2606 #define xgxsBlk4_actualSpeedsMisc1_dr_6000BRCM_X4 18 2607 #define xgxsBlk4_actualSpeedsMisc1_dr_10GHiGig_X4 19 2608 #define xgxsBlk4_actualSpeedsMisc1_dr_10GBASE_CX4 20 2609 #define xgxsBlk4_actualSpeedsMisc1_dr_12GHiGig_X4 21 2610 #define xgxsBlk4_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2611 #define xgxsBlk4_actualSpeedsMisc1_dr_13GHiGig_X4 23 2612 #define xgxsBlk4_actualSpeedsMisc1_dr_15GHiGig_X4 24 2613 #define xgxsBlk4_actualSpeedsMisc1_dr_16GHiGig_X4 25 2614 #define xgxsBlk4_actualSpeedsMisc1_dr_5000BRCM_X1 26 2615 #define xgxsBlk4_actualSpeedsMisc1_dr_6363BRCM_X1 27 2616 #define xgxsBlk4_actualSpeedsMisc1_dr_20GHiGig_X4 28 2617 #define xgxsBlk4_actualSpeedsMisc1_dr_21GHiGig_X4 29 2618 #define xgxsBlk4_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2619 #define xgxsBlk4_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2620 2621 /**************************************************************************** 2622 * Enums: xgxsBlk4_IndLaneModes 2623 */ 2624 #define xgxsBlk4_IndLaneModes_SWSDR_div2 0 2625 #define xgxsBlk4_IndLaneModes_SWSDR_div1 1 2626 #define xgxsBlk4_IndLaneModes_DWSDR_div2 2 2627 #define xgxsBlk4_IndLaneModes_DWSDR_div1 3 2628 2629 /**************************************************************************** 2630 * Enums: xgxsBlk4_prbsSelect 2631 */ 2632 #define xgxsBlk4_prbsSelect_prbs7 0 2633 #define xgxsBlk4_prbsSelect_prbs15 1 2634 #define xgxsBlk4_prbsSelect_prbs23 2 2635 #define xgxsBlk4_prbsSelect_prbs31 3 2636 2637 /**************************************************************************** 2638 * Enums: xgxsBlk4_vcoDivider 2639 */ 2640 #define xgxsBlk4_vcoDivider_div32 0 2641 #define xgxsBlk4_vcoDivider_div36 1 2642 #define xgxsBlk4_vcoDivider_div40 2 2643 #define xgxsBlk4_vcoDivider_div42 3 2644 #define xgxsBlk4_vcoDivider_div48 4 2645 #define xgxsBlk4_vcoDivider_div50 5 2646 #define xgxsBlk4_vcoDivider_div52 6 2647 #define xgxsBlk4_vcoDivider_div54 7 2648 #define xgxsBlk4_vcoDivider_div60 8 2649 #define xgxsBlk4_vcoDivider_div64 9 2650 #define xgxsBlk4_vcoDivider_div66 10 2651 #define xgxsBlk4_vcoDivider_div68 11 2652 #define xgxsBlk4_vcoDivider_div70 12 2653 #define xgxsBlk4_vcoDivider_div80 13 2654 #define xgxsBlk4_vcoDivider_div92 14 2655 #define xgxsBlk4_vcoDivider_div100 15 2656 2657 /**************************************************************************** 2658 * Enums: xgxsBlk4_refClkSelect 2659 */ 2660 #define xgxsBlk4_refClkSelect_clk_25MHz 0 2661 #define xgxsBlk4_refClkSelect_clk_100MHz 1 2662 #define xgxsBlk4_refClkSelect_clk_125MHz 2 2663 #define xgxsBlk4_refClkSelect_clk_156p25MHz 3 2664 #define xgxsBlk4_refClkSelect_clk_187p5MHz 4 2665 #define xgxsBlk4_refClkSelect_clk_161p25Mhz 5 2666 #define xgxsBlk4_refClkSelect_clk_50Mhz 6 2667 #define xgxsBlk4_refClkSelect_clk_106p25Mhz 7 2668 2669 /**************************************************************************** 2670 * Enums: xgxsBlk4_aerMMDdevTypeSelect 2671 */ 2672 #define xgxsBlk4_aerMMDdevTypeSelect_combo_core 0 2673 #define xgxsBlk4_aerMMDdevTypeSelect_PMA_PMD 1 2674 #define xgxsBlk4_aerMMDdevTypeSelect_PCS 3 2675 #define xgxsBlk4_aerMMDdevTypeSelect_PHY 4 2676 #define xgxsBlk4_aerMMDdevTypeSelect_DTE 5 2677 #define xgxsBlk4_aerMMDdevTypeSelect_CL73_AN 7 2678 2679 /**************************************************************************** 2680 * Enums: xgxsBlk4_aerMMDportSelect 2681 */ 2682 #define xgxsBlk4_aerMMDportSelect_ln0 0 2683 #define xgxsBlk4_aerMMDportSelect_ln1 1 2684 #define xgxsBlk4_aerMMDportSelect_ln2 2 2685 #define xgxsBlk4_aerMMDportSelect_ln3 3 2686 #define xgxsBlk4_aerMMDportSelect_BCST 511 2687 2688 /**************************************************************************** 2689 * Enums: xgxsBlk4_firmwareModeSelect 2690 */ 2691 #define xgxsBlk4_firmwareModeSelect_DEFAULT 0 2692 #define xgxsBlk4_firmwareModeSelect_SFP_OPT_LR 1 2693 #define xgxsBlk4_firmwareModeSelect_SFP_DAC 2 2694 #define xgxsBlk4_firmwareModeSelect_XLAUI 3 2695 #define xgxsBlk4_firmwareModeSelect_LONG_CH_6G 4 2696 2697 /**************************************************************************** 2698 * Enums: xgxsBlk4_tempIdxSelect 2699 */ 2700 #define xgxsBlk4_tempIdxSelect_LTE__22p9C 15 2701 #define xgxsBlk4_tempIdxSelect_LTE__12p6C 14 2702 #define xgxsBlk4_tempIdxSelect_LTE__3p0C 13 2703 #define xgxsBlk4_tempIdxSelect_LTE_6p7C 12 2704 #define xgxsBlk4_tempIdxSelect_LTE_16p4C 11 2705 #define xgxsBlk4_tempIdxSelect_LTE_26p6C 10 2706 #define xgxsBlk4_tempIdxSelect_LTE_36p3C 9 2707 #define xgxsBlk4_tempIdxSelect_LTE_46p0C 8 2708 #define xgxsBlk4_tempIdxSelect_LTE_56p2C 7 2709 #define xgxsBlk4_tempIdxSelect_LTE_65p9C 6 2710 #define xgxsBlk4_tempIdxSelect_LTE_75p6C 5 2711 #define xgxsBlk4_tempIdxSelect_LTE_85p3C 4 2712 #define xgxsBlk4_tempIdxSelect_LTE_95p5C 3 2713 #define xgxsBlk4_tempIdxSelect_LTE_105p2C 2 2714 #define xgxsBlk4_tempIdxSelect_LTE_114p9C 1 2715 #define xgxsBlk4_tempIdxSelect_LTE_125p1C 0 2716 2717 /**************************************************************************** 2718 * Enums: xgxsBlk5_operationModes 2719 */ 2720 #define xgxsBlk5_operationModes_XGXS 0 2721 #define xgxsBlk5_operationModes_XGXG_nCC 1 2722 #define xgxsBlk5_operationModes_IndLane_OS8 4 2723 #define xgxsBlk5_operationModes_IndLane_OS5 5 2724 #define xgxsBlk5_operationModes_PCI 7 2725 #define xgxsBlk5_operationModes_XGXS_nLQ 8 2726 #define xgxsBlk5_operationModes_XGXS_nLQnCC 9 2727 #define xgxsBlk5_operationModes_PBypass 10 2728 #define xgxsBlk5_operationModes_PBypass_nDSK 11 2729 #define xgxsBlk5_operationModes_ComboCoreMode 12 2730 #define xgxsBlk5_operationModes_Clocks_off 15 2731 2732 /**************************************************************************** 2733 * Enums: xgxsBlk5_actualSpeeds4 2734 */ 2735 #define xgxsBlk5_actualSpeeds4_dr_10M 0 2736 #define xgxsBlk5_actualSpeeds4_dr_100M 1 2737 #define xgxsBlk5_actualSpeeds4_dr_1G 2 2738 #define xgxsBlk5_actualSpeeds4_dr_2p5G 3 2739 #define xgxsBlk5_actualSpeeds4_dr_5G_X4 4 2740 #define xgxsBlk5_actualSpeeds4_dr_6G_X4 5 2741 #define xgxsBlk5_actualSpeeds4_dr_10G_HiG 6 2742 #define xgxsBlk5_actualSpeeds4_dr_10G_CX4 7 2743 #define xgxsBlk5_actualSpeeds4_dr_12G_HiG 8 2744 #define xgxsBlk5_actualSpeeds4_dr_12p5G_X4 9 2745 #define xgxsBlk5_actualSpeeds4_dr_13G_X4 10 2746 #define xgxsBlk5_actualSpeeds4_dr_15G_X4 11 2747 #define xgxsBlk5_actualSpeeds4_dr_16G_X4 12 2748 2749 /**************************************************************************** 2750 * Enums: xgxsBlk5_actualSpeeds5 2751 */ 2752 #define xgxsBlk5_actualSpeeds5_dr_10M 0 2753 #define xgxsBlk5_actualSpeeds5_dr_100M 1 2754 #define xgxsBlk5_actualSpeeds5_dr_1G 2 2755 #define xgxsBlk5_actualSpeeds5_dr_2p5G 3 2756 #define xgxsBlk5_actualSpeeds5_dr_5G_X4 4 2757 #define xgxsBlk5_actualSpeeds5_dr_6G_X4 5 2758 #define xgxsBlk5_actualSpeeds5_dr_10G_HiG 6 2759 #define xgxsBlk5_actualSpeeds5_dr_10G_CX4 7 2760 #define xgxsBlk5_actualSpeeds5_dr_12G_HiG 8 2761 #define xgxsBlk5_actualSpeeds5_dr_12p5G_X4 9 2762 #define xgxsBlk5_actualSpeeds5_dr_13G_X4 10 2763 #define xgxsBlk5_actualSpeeds5_dr_15G_X4 11 2764 #define xgxsBlk5_actualSpeeds5_dr_16G_X4 12 2765 #define xgxsBlk5_actualSpeeds5_dr_1G_KX 13 2766 #define xgxsBlk5_actualSpeeds5_dr_10G_KX4 14 2767 #define xgxsBlk5_actualSpeeds5_dr_10G_KR 15 2768 #define xgxsBlk5_actualSpeeds5_dr_5G 16 2769 #define xgxsBlk5_actualSpeeds5_dr_6p4G 17 2770 #define xgxsBlk5_actualSpeeds5_dr_20G_X4 18 2771 #define xgxsBlk5_actualSpeeds5_dr_21G_X4 19 2772 #define xgxsBlk5_actualSpeeds5_dr_25G_X4 20 2773 #define xgxsBlk5_actualSpeeds5_dr_10G_HiG_DXGXS 21 2774 #define xgxsBlk5_actualSpeeds5_dr_10G_DXGXS 22 2775 #define xgxsBlk5_actualSpeeds5_dr_10p5G_HiG_DXGXS 23 2776 #define xgxsBlk5_actualSpeeds5_dr_10p5G_DXGXS 24 2777 #define xgxsBlk5_actualSpeeds5_dr_12p773G_HiG_DXGXS 25 2778 #define xgxsBlk5_actualSpeeds5_dr_12p773G_DXGXS 26 2779 #define xgxsBlk5_actualSpeeds5_dr_10G_XFI 27 2780 #define xgxsBlk5_actualSpeeds5_dr_40G 28 2781 #define xgxsBlk5_actualSpeeds5_dr_20G_HiG_DXGXS 29 2782 #define xgxsBlk5_actualSpeeds5_dr_20G_DXGXS 30 2783 #define xgxsBlk5_actualSpeeds5_dr_10G_SFI 31 2784 #define xgxsBlk5_actualSpeeds5_dr_31p5G 32 2785 #define xgxsBlk5_actualSpeeds5_dr_32p7G 33 2786 #define xgxsBlk5_actualSpeeds5_dr_20G_SCR 34 2787 #define xgxsBlk5_actualSpeeds5_dr_10G_HiG_DXGXS_SCR 35 2788 #define xgxsBlk5_actualSpeeds5_dr_10G_DXGXS_SCR 36 2789 #define xgxsBlk5_actualSpeeds5_dr_12G_R2 37 2790 #define xgxsBlk5_actualSpeeds5_dr_10G_X2 38 2791 #define xgxsBlk5_actualSpeeds5_dr_40G_KR4 39 2792 #define xgxsBlk5_actualSpeeds5_dr_40G_CR4 40 2793 #define xgxsBlk5_actualSpeeds5_dr_100G_CR10 41 2794 #define xgxsBlk5_actualSpeeds5_dr_15p75G_DXGXS 44 2795 #define xgxsBlk5_actualSpeeds5_dr_20G_KR2 57 2796 #define xgxsBlk5_actualSpeeds5_dr_20G_CR2 58 2797 2798 /**************************************************************************** 2799 * Enums: xgxsBlk5_actualSpeedsMisc1 2800 */ 2801 #define xgxsBlk5_actualSpeedsMisc1_dr_2500BRCM_X1 16 2802 #define xgxsBlk5_actualSpeedsMisc1_dr_5000BRCM_X4 17 2803 #define xgxsBlk5_actualSpeedsMisc1_dr_6000BRCM_X4 18 2804 #define xgxsBlk5_actualSpeedsMisc1_dr_10GHiGig_X4 19 2805 #define xgxsBlk5_actualSpeedsMisc1_dr_10GBASE_CX4 20 2806 #define xgxsBlk5_actualSpeedsMisc1_dr_12GHiGig_X4 21 2807 #define xgxsBlk5_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2808 #define xgxsBlk5_actualSpeedsMisc1_dr_13GHiGig_X4 23 2809 #define xgxsBlk5_actualSpeedsMisc1_dr_15GHiGig_X4 24 2810 #define xgxsBlk5_actualSpeedsMisc1_dr_16GHiGig_X4 25 2811 #define xgxsBlk5_actualSpeedsMisc1_dr_5000BRCM_X1 26 2812 #define xgxsBlk5_actualSpeedsMisc1_dr_6363BRCM_X1 27 2813 #define xgxsBlk5_actualSpeedsMisc1_dr_20GHiGig_X4 28 2814 #define xgxsBlk5_actualSpeedsMisc1_dr_21GHiGig_X4 29 2815 #define xgxsBlk5_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2816 #define xgxsBlk5_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2817 2818 /**************************************************************************** 2819 * Enums: xgxsBlk5_IndLaneModes 2820 */ 2821 #define xgxsBlk5_IndLaneModes_SWSDR_div2 0 2822 #define xgxsBlk5_IndLaneModes_SWSDR_div1 1 2823 #define xgxsBlk5_IndLaneModes_DWSDR_div2 2 2824 #define xgxsBlk5_IndLaneModes_DWSDR_div1 3 2825 2826 /**************************************************************************** 2827 * Enums: xgxsBlk5_prbsSelect 2828 */ 2829 #define xgxsBlk5_prbsSelect_prbs7 0 2830 #define xgxsBlk5_prbsSelect_prbs15 1 2831 #define xgxsBlk5_prbsSelect_prbs23 2 2832 #define xgxsBlk5_prbsSelect_prbs31 3 2833 2834 /**************************************************************************** 2835 * Enums: xgxsBlk5_vcoDivider 2836 */ 2837 #define xgxsBlk5_vcoDivider_div32 0 2838 #define xgxsBlk5_vcoDivider_div36 1 2839 #define xgxsBlk5_vcoDivider_div40 2 2840 #define xgxsBlk5_vcoDivider_div42 3 2841 #define xgxsBlk5_vcoDivider_div48 4 2842 #define xgxsBlk5_vcoDivider_div50 5 2843 #define xgxsBlk5_vcoDivider_div52 6 2844 #define xgxsBlk5_vcoDivider_div54 7 2845 #define xgxsBlk5_vcoDivider_div60 8 2846 #define xgxsBlk5_vcoDivider_div64 9 2847 #define xgxsBlk5_vcoDivider_div66 10 2848 #define xgxsBlk5_vcoDivider_div68 11 2849 #define xgxsBlk5_vcoDivider_div70 12 2850 #define xgxsBlk5_vcoDivider_div80 13 2851 #define xgxsBlk5_vcoDivider_div92 14 2852 #define xgxsBlk5_vcoDivider_div100 15 2853 2854 /**************************************************************************** 2855 * Enums: xgxsBlk5_refClkSelect 2856 */ 2857 #define xgxsBlk5_refClkSelect_clk_25MHz 0 2858 #define xgxsBlk5_refClkSelect_clk_100MHz 1 2859 #define xgxsBlk5_refClkSelect_clk_125MHz 2 2860 #define xgxsBlk5_refClkSelect_clk_156p25MHz 3 2861 #define xgxsBlk5_refClkSelect_clk_187p5MHz 4 2862 #define xgxsBlk5_refClkSelect_clk_161p25Mhz 5 2863 #define xgxsBlk5_refClkSelect_clk_50Mhz 6 2864 #define xgxsBlk5_refClkSelect_clk_106p25Mhz 7 2865 2866 /**************************************************************************** 2867 * Enums: xgxsBlk5_aerMMDdevTypeSelect 2868 */ 2869 #define xgxsBlk5_aerMMDdevTypeSelect_combo_core 0 2870 #define xgxsBlk5_aerMMDdevTypeSelect_PMA_PMD 1 2871 #define xgxsBlk5_aerMMDdevTypeSelect_PCS 3 2872 #define xgxsBlk5_aerMMDdevTypeSelect_PHY 4 2873 #define xgxsBlk5_aerMMDdevTypeSelect_DTE 5 2874 #define xgxsBlk5_aerMMDdevTypeSelect_CL73_AN 7 2875 2876 /**************************************************************************** 2877 * Enums: xgxsBlk5_aerMMDportSelect 2878 */ 2879 #define xgxsBlk5_aerMMDportSelect_ln0 0 2880 #define xgxsBlk5_aerMMDportSelect_ln1 1 2881 #define xgxsBlk5_aerMMDportSelect_ln2 2 2882 #define xgxsBlk5_aerMMDportSelect_ln3 3 2883 #define xgxsBlk5_aerMMDportSelect_BCST 511 2884 2885 /**************************************************************************** 2886 * Enums: xgxsBlk5_firmwareModeSelect 2887 */ 2888 #define xgxsBlk5_firmwareModeSelect_DEFAULT 0 2889 #define xgxsBlk5_firmwareModeSelect_SFP_OPT_LR 1 2890 #define xgxsBlk5_firmwareModeSelect_SFP_DAC 2 2891 #define xgxsBlk5_firmwareModeSelect_XLAUI 3 2892 #define xgxsBlk5_firmwareModeSelect_LONG_CH_6G 4 2893 2894 /**************************************************************************** 2895 * Enums: xgxsBlk5_tempIdxSelect 2896 */ 2897 #define xgxsBlk5_tempIdxSelect_LTE__22p9C 15 2898 #define xgxsBlk5_tempIdxSelect_LTE__12p6C 14 2899 #define xgxsBlk5_tempIdxSelect_LTE__3p0C 13 2900 #define xgxsBlk5_tempIdxSelect_LTE_6p7C 12 2901 #define xgxsBlk5_tempIdxSelect_LTE_16p4C 11 2902 #define xgxsBlk5_tempIdxSelect_LTE_26p6C 10 2903 #define xgxsBlk5_tempIdxSelect_LTE_36p3C 9 2904 #define xgxsBlk5_tempIdxSelect_LTE_46p0C 8 2905 #define xgxsBlk5_tempIdxSelect_LTE_56p2C 7 2906 #define xgxsBlk5_tempIdxSelect_LTE_65p9C 6 2907 #define xgxsBlk5_tempIdxSelect_LTE_75p6C 5 2908 #define xgxsBlk5_tempIdxSelect_LTE_85p3C 4 2909 #define xgxsBlk5_tempIdxSelect_LTE_95p5C 3 2910 #define xgxsBlk5_tempIdxSelect_LTE_105p2C 2 2911 #define xgxsBlk5_tempIdxSelect_LTE_114p9C 1 2912 #define xgxsBlk5_tempIdxSelect_LTE_125p1C 0 2913 2914 /**************************************************************************** 2915 * Enums: xgxsBlk7_cl48TxEEEStates_l 2916 */ 2917 #define xgxsBlk7_cl48TxEEEStates_l_TX_REFRESH 8 2918 #define xgxsBlk7_cl48TxEEEStates_l_TX_QUIET 4 2919 #define xgxsBlk7_cl48TxEEEStates_l_TX_SLEEP 2 2920 #define xgxsBlk7_cl48TxEEEStates_l_TX_ACTIVE 1 2921 2922 /**************************************************************************** 2923 * Enums: xgxsBlk7_cl48TxEEEStates_c 2924 */ 2925 #define xgxsBlk7_cl48TxEEEStates_c_TX_REFRESH 3 2926 #define xgxsBlk7_cl48TxEEEStates_c_TX_QUIET 2 2927 #define xgxsBlk7_cl48TxEEEStates_c_TX_SLEEP 1 2928 #define xgxsBlk7_cl48TxEEEStates_c_TX_ACTIVE 0 2929 2930 /**************************************************************************** 2931 * Enums: xgxsBlk7_cl48RxEEEStates_l 2932 */ 2933 #define xgxsBlk7_cl48RxEEEStates_l_RX_LINK_FAIL 32 2934 #define xgxsBlk7_cl48RxEEEStates_l_RX_WAKE 16 2935 #define xgxsBlk7_cl48RxEEEStates_l_RX_QUIET 8 2936 #define xgxsBlk7_cl48RxEEEStates_l_RX_DEACT 4 2937 #define xgxsBlk7_cl48RxEEEStates_l_RX_SLEEP 2 2938 #define xgxsBlk7_cl48RxEEEStates_l_RX_ACTIVE 1 2939 2940 /**************************************************************************** 2941 * Enums: xgxsBlk7_cl48RxEEEStates_c 2942 */ 2943 #define xgxsBlk7_cl48RxEEEStates_c_RX_LINK_FAIL 5 2944 #define xgxsBlk7_cl48RxEEEStates_c_RX_WAKE 4 2945 #define xgxsBlk7_cl48RxEEEStates_c_RX_QUIET 3 2946 #define xgxsBlk7_cl48RxEEEStates_c_RX_DEACT 2 2947 #define xgxsBlk7_cl48RxEEEStates_c_RX_SLEEP 1 2948 #define xgxsBlk7_cl48RxEEEStates_c_RX_ACTIVE 0 2949 2950 /**************************************************************************** 2951 * Warpcore_IEEE_CL22_ieee0Blk 2952 */ 2953 /* IEEE MII control register */ 2954 #define READ_WC40_IEEE0BLK_MIICNTLr(_unit, _pc, _val) \ 2955 WC40_REG_READ((_unit), (_pc), 0x00, 0x00000000, (_val)) 2956 #define WRITE_WC40_IEEE0BLK_MIICNTLr(_unit, _pc, _val) \ 2957 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00000000, (_val)) 2958 #define MODIFY_WC40_IEEE0BLK_MIICNTLr(_unit, _pc, _val, _mask) \ 2959 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000000, (_val), (_mask)) 2960 2961 /* IEEE MII status register */ 2962 #define READ_WC40_IEEE0BLK_MIISTATr(_unit, _pc, _val) \ 2963 WC40_REG_READ((_unit), (_pc), 0x00, 0x00000001, (_val)) 2964 #define WRITE_WC40_IEEE0BLK_MIISTATr(_unit, _pc, _val) \ 2965 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00000001, (_val)) 2966 #define MODIFY_WC40_IEEE0BLK_MIISTATr(_unit, _pc, _val, _mask) \ 2967 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000001, (_val), (_mask)) 2968 2969 /* IEEE phy ID LSByte register */ 2970 #define READ_WC40_IEEE0BLK_ID1r(_unit, _pc, _val) \ 2971 WC40_REG_READ((_unit), (_pc), 0x00, 0x00000002, (_val)) 2972 #define WRITE_WC40_IEEE0BLK_ID1r(_unit, _pc, _val) \ 2973 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00000002, (_val)) 2974 #define MODIFY_WC40_IEEE0BLK_ID1r(_unit, _pc, _val, _mask) \ 2975 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000002, (_val), (_mask)) 2976 2977 /* IEEE phy ID MSByte register */ 2978 #define READ_WC40_IEEE0BLK_ID2r(_unit, _pc, _val) \ 2979 WC40_REG_READ((_unit), (_pc), 0x00, 0x00000003, (_val)) 2980 #define WRITE_WC40_IEEE0BLK_ID2r(_unit, _pc, _val) \ 2981 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00000003, (_val)) 2982 #define MODIFY_WC40_IEEE0BLK_ID2r(_unit, _pc, _val, _mask) \ 2983 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000003, (_val), (_mask)) 2984 2985 /* IEEE auto-negotiation advertised abilities register */ 2986 #define READ_WC40_IEEE0BLK_AUTONEGADVr(_unit, _pc, _val) \ 2987 WC40_REG_READ((_unit), (_pc), 0x00, 0x00000004, (_val)) 2988 #define WRITE_WC40_IEEE0BLK_AUTONEGADVr(_unit, _pc, _val) \ 2989 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00000004, (_val)) 2990 #define MODIFY_WC40_IEEE0BLK_AUTONEGADVr(_unit, _pc, _val, _mask) \ 2991 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000004, (_val), (_mask)) 2992 2993 /* IEEE auto-negotiation link partner abilities register */ 2994 #define READ_WC40_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _val) \ 2995 WC40_REG_READ((_unit), (_pc), 0x00, 0x00000005, (_val)) 2996 #define WRITE_WC40_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _val) \ 2997 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00000005, (_val)) 2998 #define MODIFY_WC40_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _val, _mask) \ 2999 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000005, (_val), (_mask)) 3000 3001 /* IEEE auto-negotiation expansion register */ 3002 #define READ_WC40_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _val) \ 3003 WC40_REG_READ((_unit), (_pc), 0x00, 0x00000006, (_val)) 3004 #define WRITE_WC40_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _val) \ 3005 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00000006, (_val)) 3006 #define MODIFY_WC40_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _val, _mask) \ 3007 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000006, (_val), (_mask)) 3008 3009 /* IEEE auto-negotiation next page register */ 3010 #define READ_WC40_IEEE0BLK_AUTONEGNPr(_unit, _pc, _val) \ 3011 WC40_REG_READ((_unit), (_pc), 0x00, 0x00000007, (_val)) 3012 #define WRITE_WC40_IEEE0BLK_AUTONEGNPr(_unit, _pc, _val) \ 3013 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00000007, (_val)) 3014 #define MODIFY_WC40_IEEE0BLK_AUTONEGNPr(_unit, _pc, _val, _mask) \ 3015 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000007, (_val), (_mask)) 3016 3017 /* IEEE auto-negotiation link partner next page register */ 3018 #define READ_WC40_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _val) \ 3019 WC40_REG_READ((_unit), (_pc), 0x00, 0x00000008, (_val)) 3020 #define WRITE_WC40_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _val) \ 3021 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00000008, (_val)) 3022 #define MODIFY_WC40_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _val, _mask) \ 3023 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000008, (_val), (_mask)) 3024 3025 /* IEEE MII extended status register */ 3026 #define READ_WC40_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _val) \ 3027 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000000f, (_val)) 3028 #define WRITE_WC40_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _val) \ 3029 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000000f, (_val)) 3030 #define MODIFY_WC40_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _val, _mask) \ 3031 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000000f, (_val), (_mask)) 3032 3033 3034 3035 /**************************************************************************** 3036 * Warpcore_USER_XgxsBlk0 3037 */ 3038 /* XGXS control register */ 3039 #define READ_WC40_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 3040 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008000, (_val)) 3041 #define WRITE_WC40_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 3042 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008000, (_val)) 3043 #define MODIFY_WC40_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val, _mask) \ 3044 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008000, (_val), (_mask)) 3045 3046 /* XGXS status register */ 3047 #define READ_WC40_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \ 3048 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008001, (_val)) 3049 #define WRITE_WC40_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \ 3050 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008001, (_val)) 3051 #define MODIFY_WC40_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val, _mask) \ 3052 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008001, (_val), (_mask)) 3053 3054 /* XGMII idle control character register */ 3055 #define READ_WC40_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val) \ 3056 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008002, (_val)) 3057 #define WRITE_WC40_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val) \ 3058 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008002, (_val)) 3059 #define MODIFY_WC40_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val, _mask) \ 3060 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008002, (_val), (_mask)) 3061 3062 /* XGMII sync control character register */ 3063 #define READ_WC40_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val) \ 3064 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008003, (_val)) 3065 #define WRITE_WC40_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val) \ 3066 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008003, (_val)) 3067 #define MODIFY_WC40_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val, _mask) \ 3068 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008003, (_val), (_mask)) 3069 3070 /* XGMII skip control character register */ 3071 #define READ_WC40_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val) \ 3072 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008004, (_val)) 3073 #define WRITE_WC40_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val) \ 3074 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008004, (_val)) 3075 #define MODIFY_WC40_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val, _mask) \ 3076 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008004, (_val), (_mask)) 3077 3078 /* XGMII sop & eop control character register */ 3079 #define READ_WC40_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val) \ 3080 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008005, (_val)) 3081 #define WRITE_WC40_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val) \ 3082 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008005, (_val)) 3083 #define MODIFY_WC40_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val, _mask) \ 3084 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008005, (_val), (_mask)) 3085 3086 /* XGMII alignment & eror control character register */ 3087 #define READ_WC40_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val) \ 3088 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008006, (_val)) 3089 #define WRITE_WC40_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val) \ 3090 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008006, (_val)) 3091 #define MODIFY_WC40_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val, _mask) \ 3092 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008006, (_val), (_mask)) 3093 3094 /* XGMII receive control register */ 3095 #define READ_WC40_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val) \ 3096 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008007, (_val)) 3097 #define WRITE_WC40_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val) \ 3098 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008007, (_val)) 3099 #define MODIFY_WC40_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val, _mask) \ 3100 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008007, (_val), (_mask)) 3101 3102 /* XGMII transmit control register */ 3103 #define READ_WC40_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val) \ 3104 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008008, (_val)) 3105 #define WRITE_WC40_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val) \ 3106 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008008, (_val)) 3107 #define MODIFY_WC40_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val, _mask) \ 3108 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008008, (_val), (_mask)) 3109 3110 /* XGMII ||A|| minimum swap spacing */ 3111 #define READ_WC40_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val) \ 3112 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008009, (_val)) 3113 #define WRITE_WC40_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val) \ 3114 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008009, (_val)) 3115 #define MODIFY_WC40_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val, _mask) \ 3116 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008009, (_val), (_mask)) 3117 3118 /* LSS information byte register */ 3119 #define READ_WC40_XGXSBLK0_LSSLSIDr(_unit, _pc, _val) \ 3120 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000800a, (_val)) 3121 #define WRITE_WC40_XGXSBLK0_LSSLSIDr(_unit, _pc, _val) \ 3122 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000800a, (_val)) 3123 #define MODIFY_WC40_XGXSBLK0_LSSLSIDr(_unit, _pc, _val, _mask) \ 3124 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800a, (_val), (_mask)) 3125 3126 /* LSS transmit information byte register */ 3127 #define READ_WC40_XGXSBLK0_LSSTINFOr(_unit, _pc, _val) \ 3128 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000800b, (_val)) 3129 #define WRITE_WC40_XGXSBLK0_LSSTINFOr(_unit, _pc, _val) \ 3130 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000800b, (_val)) 3131 #define MODIFY_WC40_XGXSBLK0_LSSTINFOr(_unit, _pc, _val, _mask) \ 3132 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800b, (_val), (_mask)) 3133 3134 /* LSS receive information byte register */ 3135 #define READ_WC40_XGXSBLK0_LSSRINFOr(_unit, _pc, _val) \ 3136 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000800c, (_val)) 3137 #define WRITE_WC40_XGXSBLK0_LSSRINFOr(_unit, _pc, _val) \ 3138 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000800c, (_val)) 3139 #define MODIFY_WC40_XGXSBLK0_LSSRINFOr(_unit, _pc, _val, _mask) \ 3140 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800c, (_val), (_mask)) 3141 3142 /* MMD select register */ 3143 #define READ_WC40_XGXSBLK0_MMDSELECTr(_unit, _pc, _val) \ 3144 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000800d, (_val)) 3145 #define WRITE_WC40_XGXSBLK0_MMDSELECTr(_unit, _pc, _val) \ 3146 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000800d, (_val)) 3147 #define MODIFY_WC40_XGXSBLK0_MMDSELECTr(_unit, _pc, _val, _mask) \ 3148 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800d, (_val), (_mask)) 3149 3150 /* Miscellaneous control 1 register */ 3151 #define READ_WC40_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \ 3152 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000800e, (_val)) 3153 #define WRITE_WC40_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \ 3154 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000800e, (_val)) 3155 #define MODIFY_WC40_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val, _mask) \ 3156 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800e, (_val), (_mask)) 3157 3158 /* Block Address register */ 3159 #define READ_WC40_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val) \ 3160 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000800f, (_val)) 3161 #define WRITE_WC40_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val) \ 3162 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000800f, (_val)) 3163 #define MODIFY_WC40_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val, _mask) \ 3164 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800f, (_val), (_mask)) 3165 3166 3167 3168 /**************************************************************************** 3169 * Warpcore_USER_XgxsBlk1 3170 */ 3171 /* Lane deskew register */ 3172 #define READ_WC40_XGXSBLK1_DESKEWr(_unit, _pc, _val) \ 3173 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008010, (_val)) 3174 #define WRITE_WC40_XGXSBLK1_DESKEWr(_unit, _pc, _val) \ 3175 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008010, (_val)) 3176 #define MODIFY_WC40_XGXSBLK1_DESKEWr(_unit, _pc, _val, _mask) \ 3177 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008010, (_val), (_mask)) 3178 3179 /* Link ||A|| column timeout value register */ 3180 #define READ_WC40_XGXSBLK1_LINKr(_unit, _pc, _val) \ 3181 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008011, (_val)) 3182 #define WRITE_WC40_XGXSBLK1_LINKr(_unit, _pc, _val) \ 3183 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008011, (_val)) 3184 #define MODIFY_WC40_XGXSBLK1_LINKr(_unit, _pc, _val, _mask) \ 3185 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008011, (_val), (_mask)) 3186 3187 /* Receive test control register */ 3188 #define READ_WC40_XGXSBLK1_TESTRXr(_unit, _pc, _val) \ 3189 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008012, (_val)) 3190 #define WRITE_WC40_XGXSBLK1_TESTRXr(_unit, _pc, _val) \ 3191 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008012, (_val)) 3192 #define MODIFY_WC40_XGXSBLK1_TESTRXr(_unit, _pc, _val, _mask) \ 3193 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008012, (_val), (_mask)) 3194 3195 /* Transmit test control register */ 3196 #define READ_WC40_XGXSBLK1_TESTTXr(_unit, _pc, _val) \ 3197 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008013, (_val)) 3198 #define WRITE_WC40_XGXSBLK1_TESTTXr(_unit, _pc, _val) \ 3199 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008013, (_val)) 3200 #define MODIFY_WC40_XGXSBLK1_TESTTXr(_unit, _pc, _val, _mask) \ 3201 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008013, (_val), (_mask)) 3202 3203 /* XGXS test control register */ 3204 #define READ_WC40_XGXSBLK1_TESTXGr(_unit, _pc, _val) \ 3205 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008014, (_val)) 3206 #define WRITE_WC40_XGXSBLK1_TESTXGr(_unit, _pc, _val) \ 3207 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008014, (_val)) 3208 #define MODIFY_WC40_XGXSBLK1_TESTXGr(_unit, _pc, _val, _mask) \ 3209 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008014, (_val), (_mask)) 3210 3211 /* Lane control 0 register */ 3212 #define READ_WC40_XGXSBLK1_LANECTRL0r(_unit, _pc, _val) \ 3213 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008015, (_val)) 3214 #define WRITE_WC40_XGXSBLK1_LANECTRL0r(_unit, _pc, _val) \ 3215 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008015, (_val)) 3216 #define MODIFY_WC40_XGXSBLK1_LANECTRL0r(_unit, _pc, _val, _mask) \ 3217 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008015, (_val), (_mask)) 3218 3219 /* Lane control 1 register */ 3220 #define READ_WC40_XGXSBLK1_LANECTRL1r(_unit, _pc, _val) \ 3221 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008016, (_val)) 3222 #define WRITE_WC40_XGXSBLK1_LANECTRL1r(_unit, _pc, _val) \ 3223 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008016, (_val)) 3224 #define MODIFY_WC40_XGXSBLK1_LANECTRL1r(_unit, _pc, _val, _mask) \ 3225 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008016, (_val), (_mask)) 3226 3227 /* Lane control 2 register */ 3228 #define READ_WC40_XGXSBLK1_LANECTRL2r(_unit, _pc, _val) \ 3229 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008017, (_val)) 3230 #define WRITE_WC40_XGXSBLK1_LANECTRL2r(_unit, _pc, _val) \ 3231 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008017, (_val)) 3232 #define MODIFY_WC40_XGXSBLK1_LANECTRL2r(_unit, _pc, _val, _mask) \ 3233 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008017, (_val), (_mask)) 3234 3235 /* Lane control 3 register */ 3236 #define READ_WC40_XGXSBLK1_LANECTRL3r(_unit, _pc, _val) \ 3237 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008018, (_val)) 3238 #define WRITE_WC40_XGXSBLK1_LANECTRL3r(_unit, _pc, _val) \ 3239 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008018, (_val)) 3240 #define MODIFY_WC40_XGXSBLK1_LANECTRL3r(_unit, _pc, _val, _mask) \ 3241 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008018, (_val), (_mask)) 3242 3243 /* Lane PRBS control register */ 3244 #define READ_WC40_XGXSBLK1_LANEPRBSr(_unit, _pc, _val) \ 3245 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008019, (_val)) 3246 #define WRITE_WC40_XGXSBLK1_LANEPRBSr(_unit, _pc, _val) \ 3247 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008019, (_val)) 3248 #define MODIFY_WC40_XGXSBLK1_LANEPRBSr(_unit, _pc, _val, _mask) \ 3249 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008019, (_val), (_mask)) 3250 3251 /* Lane test control register */ 3252 #define READ_WC40_XGXSBLK1_LANETESTr(_unit, _pc, _val) \ 3253 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000801a, (_val)) 3254 #define WRITE_WC40_XGXSBLK1_LANETESTr(_unit, _pc, _val) \ 3255 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000801a, (_val)) 3256 #define MODIFY_WC40_XGXSBLK1_LANETESTr(_unit, _pc, _val, _mask) \ 3257 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801a, (_val), (_mask)) 3258 3259 /* LSS, ||Q|| column count register */ 3260 #define READ_WC40_XGXSBLK1_LSSREVNTr(_unit, _pc, _val) \ 3261 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000801b, (_val)) 3262 #define WRITE_WC40_XGXSBLK1_LSSREVNTr(_unit, _pc, _val) \ 3263 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000801b, (_val)) 3264 #define MODIFY_WC40_XGXSBLK1_LSSREVNTr(_unit, _pc, _val, _mask) \ 3265 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801b, (_val), (_mask)) 3266 3267 /* Lane deskew event count register */ 3268 #define READ_WC40_XGXSBLK1_DSKEVNTr(_unit, _pc, _val) \ 3269 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000801c, (_val)) 3270 #define WRITE_WC40_XGXSBLK1_DSKEVNTr(_unit, _pc, _val) \ 3271 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000801c, (_val)) 3272 #define MODIFY_WC40_XGXSBLK1_DSKEVNTr(_unit, _pc, _val, _mask) \ 3273 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801c, (_val), (_mask)) 3274 3275 /* Bad ||A|| column count register */ 3276 #define READ_WC40_XGXSBLK1_AERREVNTr(_unit, _pc, _val) \ 3277 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000801d, (_val)) 3278 #define WRITE_WC40_XGXSBLK1_AERREVNTr(_unit, _pc, _val) \ 3279 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000801d, (_val)) 3280 #define MODIFY_WC40_XGXSBLK1_AERREVNTr(_unit, _pc, _val, _mask) \ 3281 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801d, (_val), (_mask)) 3282 3283 /* Clock compensation event count register */ 3284 #define READ_WC40_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val) \ 3285 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000801e, (_val)) 3286 #define WRITE_WC40_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val) \ 3287 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000801e, (_val)) 3288 #define MODIFY_WC40_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val, _mask) \ 3289 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801e, (_val), (_mask)) 3290 3291 /* Block Address register */ 3292 #define READ_WC40_XGXSBLK1_BLOCKADDRESSr(_unit, _pc, _val) \ 3293 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000801f, (_val)) 3294 #define WRITE_WC40_XGXSBLK1_BLOCKADDRESSr(_unit, _pc, _val) \ 3295 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000801f, (_val)) 3296 #define MODIFY_WC40_XGXSBLK1_BLOCKADDRESSr(_unit, _pc, _val, _mask) \ 3297 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801f, (_val), (_mask)) 3298 3299 3300 3301 /**************************************************************************** 3302 * Warpcore_USER_TxBert 3303 */ 3304 /* Tx Bert control register */ 3305 #define READ_WC40_TXBERT_TXBERTCTRLr(_unit, _pc, _val) \ 3306 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008020, (_val)) 3307 #define WRITE_WC40_TXBERT_TXBERTCTRLr(_unit, _pc, _val) \ 3308 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008020, (_val)) 3309 #define MODIFY_WC40_TXBERT_TXBERTCTRLr(_unit, _pc, _val, _mask) \ 3310 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008020, (_val), (_mask)) 3311 3312 /* Tx Bert SOP, EOP definition register */ 3313 #define READ_WC40_TXBERT_TXBERTSOPEOPr(_unit, _pc, _val) \ 3314 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008021, (_val)) 3315 #define WRITE_WC40_TXBERT_TXBERTSOPEOPr(_unit, _pc, _val) \ 3316 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008021, (_val)) 3317 #define MODIFY_WC40_TXBERT_TXBERTSOPEOPr(_unit, _pc, _val, _mask) \ 3318 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008021, (_val), (_mask)) 3319 3320 /* Packet size configuration 0 register */ 3321 #define READ_WC40_TXBERT_TXBERTSIZE0r(_unit, _pc, _val) \ 3322 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008022, (_val)) 3323 #define WRITE_WC40_TXBERT_TXBERTSIZE0r(_unit, _pc, _val) \ 3324 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008022, (_val)) 3325 #define MODIFY_WC40_TXBERT_TXBERTSIZE0r(_unit, _pc, _val, _mask) \ 3326 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008022, (_val), (_mask)) 3327 3328 /* Packet size configuration 1 register */ 3329 #define READ_WC40_TXBERT_TXBERTSIZE1r(_unit, _pc, _val) \ 3330 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008023, (_val)) 3331 #define WRITE_WC40_TXBERT_TXBERTSIZE1r(_unit, _pc, _val) \ 3332 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008023, (_val)) 3333 #define MODIFY_WC40_TXBERT_TXBERTSIZE1r(_unit, _pc, _val, _mask) \ 3334 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008023, (_val), (_mask)) 3335 3336 /* Packet size configuration 2 register */ 3337 #define READ_WC40_TXBERT_TXBERTSIZE2r(_unit, _pc, _val) \ 3338 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008024, (_val)) 3339 #define WRITE_WC40_TXBERT_TXBERTSIZE2r(_unit, _pc, _val) \ 3340 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008024, (_val)) 3341 #define MODIFY_WC40_TXBERT_TXBERTSIZE2r(_unit, _pc, _val, _mask) \ 3342 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008024, (_val), (_mask)) 3343 3344 /* IPG 0 definition register */ 3345 #define READ_WC40_TXBERT_TXBERTIPG0r(_unit, _pc, _val) \ 3346 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008025, (_val)) 3347 #define WRITE_WC40_TXBERT_TXBERTIPG0r(_unit, _pc, _val) \ 3348 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008025, (_val)) 3349 #define MODIFY_WC40_TXBERT_TXBERTIPG0r(_unit, _pc, _val, _mask) \ 3350 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008025, (_val), (_mask)) 3351 3352 /* IPG 1 definition register */ 3353 #define READ_WC40_TXBERT_TXBERTIPG1r(_unit, _pc, _val) \ 3354 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008026, (_val)) 3355 #define WRITE_WC40_TXBERT_TXBERTIPG1r(_unit, _pc, _val) \ 3356 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008026, (_val)) 3357 #define MODIFY_WC40_TXBERT_TXBERTIPG1r(_unit, _pc, _val, _mask) \ 3358 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008026, (_val), (_mask)) 3359 3360 /* Transmitted byte count upper 16 bits register */ 3361 #define READ_WC40_TXBERT_TXBERTBYTEUr(_unit, _pc, _val) \ 3362 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008027, (_val)) 3363 #define WRITE_WC40_TXBERT_TXBERTBYTEUr(_unit, _pc, _val) \ 3364 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008027, (_val)) 3365 #define MODIFY_WC40_TXBERT_TXBERTBYTEUr(_unit, _pc, _val, _mask) \ 3366 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008027, (_val), (_mask)) 3367 3368 /* Transmitted byte count lower 16 bits register */ 3369 #define READ_WC40_TXBERT_TXBERTBYTELr(_unit, _pc, _val) \ 3370 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008028, (_val)) 3371 #define WRITE_WC40_TXBERT_TXBERTBYTELr(_unit, _pc, _val) \ 3372 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008028, (_val)) 3373 #define MODIFY_WC40_TXBERT_TXBERTBYTELr(_unit, _pc, _val, _mask) \ 3374 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008028, (_val), (_mask)) 3375 3376 /* Transmitted packet count upper 16 bits register */ 3377 #define READ_WC40_TXBERT_TXBERTPACKETUr(_unit, _pc, _val) \ 3378 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008029, (_val)) 3379 #define WRITE_WC40_TXBERT_TXBERTPACKETUr(_unit, _pc, _val) \ 3380 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008029, (_val)) 3381 #define MODIFY_WC40_TXBERT_TXBERTPACKETUr(_unit, _pc, _val, _mask) \ 3382 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008029, (_val), (_mask)) 3383 3384 /* Transmitted packet count lower 16 bits register */ 3385 #define READ_WC40_TXBERT_TXBERTPACKETLr(_unit, _pc, _val) \ 3386 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000802a, (_val)) 3387 #define WRITE_WC40_TXBERT_TXBERTPACKETLr(_unit, _pc, _val) \ 3388 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000802a, (_val)) 3389 #define MODIFY_WC40_TXBERT_TXBERTPACKETLr(_unit, _pc, _val, _mask) \ 3390 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000802a, (_val), (_mask)) 3391 3392 /* Tx Bert control1 register */ 3393 #define READ_WC40_TXBERT_TXBERTCTRL1r(_unit, _pc, _val) \ 3394 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000802b, (_val)) 3395 #define WRITE_WC40_TXBERT_TXBERTCTRL1r(_unit, _pc, _val) \ 3396 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000802b, (_val)) 3397 #define MODIFY_WC40_TXBERT_TXBERTCTRL1r(_unit, _pc, _val, _mask) \ 3398 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000802b, (_val), (_mask)) 3399 3400 3401 3402 /**************************************************************************** 3403 * Warpcore_USER_RxBert 3404 */ 3405 /* Rx Bert control register */ 3406 #define READ_WC40_RXBERT_RXBERTCTRLr(_unit, _pc, _val) \ 3407 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008030, (_val)) 3408 #define WRITE_WC40_RXBERT_RXBERTCTRLr(_unit, _pc, _val) \ 3409 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008030, (_val)) 3410 #define MODIFY_WC40_RXBERT_RXBERTCTRLr(_unit, _pc, _val, _mask) \ 3411 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008030, (_val), (_mask)) 3412 3413 /* Rx Bert SOP, EOP definition register */ 3414 #define READ_WC40_RXBERT_RXBERTSOPEOPr(_unit, _pc, _val) \ 3415 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008031, (_val)) 3416 #define WRITE_WC40_RXBERT_RXBERTSOPEOPr(_unit, _pc, _val) \ 3417 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008031, (_val)) 3418 #define MODIFY_WC40_RXBERT_RXBERTSOPEOPr(_unit, _pc, _val, _mask) \ 3419 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008031, (_val), (_mask)) 3420 3421 /* Received byte count upper 16 bits register */ 3422 #define READ_WC40_RXBERT_RXBERTBYTEUr(_unit, _pc, _val) \ 3423 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008037, (_val)) 3424 #define WRITE_WC40_RXBERT_RXBERTBYTEUr(_unit, _pc, _val) \ 3425 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008037, (_val)) 3426 #define MODIFY_WC40_RXBERT_RXBERTBYTEUr(_unit, _pc, _val, _mask) \ 3427 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008037, (_val), (_mask)) 3428 3429 /* Received bytes count lower 16 bits register */ 3430 #define READ_WC40_RXBERT_RXBERTBYTELr(_unit, _pc, _val) \ 3431 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008038, (_val)) 3432 #define WRITE_WC40_RXBERT_RXBERTBYTELr(_unit, _pc, _val) \ 3433 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008038, (_val)) 3434 #define MODIFY_WC40_RXBERT_RXBERTBYTELr(_unit, _pc, _val, _mask) \ 3435 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008038, (_val), (_mask)) 3436 3437 /* Received packet count upper 16 bits register */ 3438 #define READ_WC40_RXBERT_RXBERTPACKETUr(_unit, _pc, _val) \ 3439 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008039, (_val)) 3440 #define WRITE_WC40_RXBERT_RXBERTPACKETUr(_unit, _pc, _val) \ 3441 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008039, (_val)) 3442 #define MODIFY_WC40_RXBERT_RXBERTPACKETUr(_unit, _pc, _val, _mask) \ 3443 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008039, (_val), (_mask)) 3444 3445 /* Received packet count lower 16 bits register */ 3446 #define READ_WC40_RXBERT_RXBERTPACKETLr(_unit, _pc, _val) \ 3447 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000803a, (_val)) 3448 #define WRITE_WC40_RXBERT_RXBERTPACKETLr(_unit, _pc, _val) \ 3449 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000803a, (_val)) 3450 #define MODIFY_WC40_RXBERT_RXBERTPACKETLr(_unit, _pc, _val, _mask) \ 3451 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803a, (_val), (_mask)) 3452 3453 /* Received bits error count */ 3454 #define READ_WC40_RXBERT_RXBERTBITERRr(_unit, _pc, _val) \ 3455 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000803b, (_val)) 3456 #define WRITE_WC40_RXBERT_RXBERTBITERRr(_unit, _pc, _val) \ 3457 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000803b, (_val)) 3458 #define MODIFY_WC40_RXBERT_RXBERTBITERRr(_unit, _pc, _val, _mask) \ 3459 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803b, (_val), (_mask)) 3460 3461 /* Received bytes error count */ 3462 #define READ_WC40_RXBERT_RXBERTBYTEERRr(_unit, _pc, _val) \ 3463 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000803c, (_val)) 3464 #define WRITE_WC40_RXBERT_RXBERTBYTEERRr(_unit, _pc, _val) \ 3465 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000803c, (_val)) 3466 #define MODIFY_WC40_RXBERT_RXBERTBYTEERRr(_unit, _pc, _val, _mask) \ 3467 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803c, (_val), (_mask)) 3468 3469 /* Received packets error count */ 3470 #define READ_WC40_RXBERT_RXBERTPKTERRr(_unit, _pc, _val) \ 3471 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000803d, (_val)) 3472 #define WRITE_WC40_RXBERT_RXBERTPKTERRr(_unit, _pc, _val) \ 3473 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000803d, (_val)) 3474 #define MODIFY_WC40_RXBERT_RXBERTPKTERRr(_unit, _pc, _val, _mask) \ 3475 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803d, (_val), (_mask)) 3476 3477 /* Receive Status */ 3478 #define READ_WC40_RXBERT_RXBERTSTATUSr(_unit, _pc, _val) \ 3479 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000803e, (_val)) 3480 #define WRITE_WC40_RXBERT_RXBERTSTATUSr(_unit, _pc, _val) \ 3481 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000803e, (_val)) 3482 #define MODIFY_WC40_RXBERT_RXBERTSTATUSr(_unit, _pc, _val, _mask) \ 3483 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803e, (_val), (_mask)) 3484 3485 3486 3487 /**************************************************************************** 3488 * Warpcore_USER_PLL 3489 */ 3490 /* PLL status register */ 3491 #define READ_WC40_PLL_ANAPLLSTATUSr(_unit, _pc, _val) \ 3492 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008050, (_val)) 3493 #define WRITE_WC40_PLL_ANAPLLSTATUSr(_unit, _pc, _val) \ 3494 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008050, (_val)) 3495 #define MODIFY_WC40_PLL_ANAPLLSTATUSr(_unit, _pc, _val, _mask) \ 3496 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008050, (_val), (_mask)) 3497 3498 /* PLL control register */ 3499 #define READ_WC40_PLL_ANAPLLCONTROLr(_unit, _pc, _val) \ 3500 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008051, (_val)) 3501 #define WRITE_WC40_PLL_ANAPLLCONTROLr(_unit, _pc, _val) \ 3502 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008051, (_val)) 3503 #define MODIFY_WC40_PLL_ANAPLLCONTROLr(_unit, _pc, _val, _mask) \ 3504 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008051, (_val), (_mask)) 3505 3506 /* PLL start up state machine vco timers */ 3507 #define READ_WC40_PLL_ANAPLLTIMER1r(_unit, _pc, _val) \ 3508 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008052, (_val)) 3509 #define WRITE_WC40_PLL_ANAPLLTIMER1r(_unit, _pc, _val) \ 3510 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008052, (_val)) 3511 #define MODIFY_WC40_PLL_ANAPLLTIMER1r(_unit, _pc, _val, _mask) \ 3512 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008052, (_val), (_mask)) 3513 3514 /* PLL start up state machine retry timer */ 3515 #define READ_WC40_PLL_ANAPLLTIMER2r(_unit, _pc, _val) \ 3516 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008053, (_val)) 3517 #define WRITE_WC40_PLL_ANAPLLTIMER2r(_unit, _pc, _val) \ 3518 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008053, (_val)) 3519 #define MODIFY_WC40_PLL_ANAPLLTIMER2r(_unit, _pc, _val, _mask) \ 3520 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008053, (_val), (_mask)) 3521 3522 /* PLL start up state machine freq. detect timer */ 3523 #define READ_WC40_PLL_ANAPLLTIMER3r(_unit, _pc, _val) \ 3524 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008054, (_val)) 3525 #define WRITE_WC40_PLL_ANAPLLTIMER3r(_unit, _pc, _val) \ 3526 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008054, (_val)) 3527 #define MODIFY_WC40_PLL_ANAPLLTIMER3r(_unit, _pc, _val, _mask) \ 3528 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008054, (_val), (_mask)) 3529 3530 /* PLL vco range control state machine */ 3531 #define READ_WC40_PLL_ANACAPCONTROLr(_unit, _pc, _val) \ 3532 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008055, (_val)) 3533 #define WRITE_WC40_PLL_ANACAPCONTROLr(_unit, _pc, _val) \ 3534 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008055, (_val)) 3535 #define MODIFY_WC40_PLL_ANACAPCONTROLr(_unit, _pc, _val, _mask) \ 3536 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008055, (_val), (_mask)) 3537 3538 /* Frequency detector control */ 3539 #define READ_WC40_PLL_ANAFREQDETCNTRr(_unit, _pc, _val) \ 3540 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008057, (_val)) 3541 #define WRITE_WC40_PLL_ANAFREQDETCNTRr(_unit, _pc, _val) \ 3542 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008057, (_val)) 3543 #define MODIFY_WC40_PLL_ANAFREQDETCNTRr(_unit, _pc, _val, _mask) \ 3544 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008057, (_val), (_mask)) 3545 3546 /* PLL analog status (AFE pll_sts[15:0], not applicable to XFICore) */ 3547 #define READ_WC40_PLL_ANAPLLASTATUS1r(_unit, _pc, _val) \ 3548 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008058, (_val)) 3549 #define WRITE_WC40_PLL_ANAPLLASTATUS1r(_unit, _pc, _val) \ 3550 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008058, (_val)) 3551 #define MODIFY_WC40_PLL_ANAPLLASTATUS1r(_unit, _pc, _val, _mask) \ 3552 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008058, (_val), (_mask)) 3553 3554 /* PLL analog controls (AFE pll_clrl[15:00], not applicable to XFICore) */ 3555 #define READ_WC40_PLL_ANAPLLACONTROL0r(_unit, _pc, _val) \ 3556 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000805a, (_val)) 3557 #define WRITE_WC40_PLL_ANAPLLACONTROL0r(_unit, _pc, _val) \ 3558 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000805a, (_val)) 3559 #define MODIFY_WC40_PLL_ANAPLLACONTROL0r(_unit, _pc, _val, _mask) \ 3560 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805a, (_val), (_mask)) 3561 3562 /* PLL analog controls (AFE pll_ctrl[31:16], not applicable to XFICore) */ 3563 #define READ_WC40_PLL_ANAPLLACONTROL1r(_unit, _pc, _val) \ 3564 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000805b, (_val)) 3565 #define WRITE_WC40_PLL_ANAPLLACONTROL1r(_unit, _pc, _val) \ 3566 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000805b, (_val)) 3567 #define MODIFY_WC40_PLL_ANAPLLACONTROL1r(_unit, _pc, _val, _mask) \ 3568 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805b, (_val), (_mask)) 3569 3570 /* PLL analog controls (AFE pll_ctrl[47:32], not applicable to XFICore) */ 3571 #define READ_WC40_PLL_ANAPLLACONTROL2r(_unit, _pc, _val) \ 3572 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000805c, (_val)) 3573 #define WRITE_WC40_PLL_ANAPLLACONTROL2r(_unit, _pc, _val) \ 3574 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000805c, (_val)) 3575 #define MODIFY_WC40_PLL_ANAPLLACONTROL2r(_unit, _pc, _val, _mask) \ 3576 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805c, (_val), (_mask)) 3577 3578 /* PLL analog controls (AFE pll_ctrl[63:48], not applicable to XFICore) */ 3579 #define READ_WC40_PLL_ANAPLLACONTROL3r(_unit, _pc, _val) \ 3580 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000805d, (_val)) 3581 #define WRITE_WC40_PLL_ANAPLLACONTROL3r(_unit, _pc, _val) \ 3582 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000805d, (_val)) 3583 #define MODIFY_WC40_PLL_ANAPLLACONTROL3r(_unit, _pc, _val, _mask) \ 3584 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805d, (_val), (_mask)) 3585 3586 /* PLL analog controls (AFE pll_ctrl[79:64], not applicable to XFICore) */ 3587 #define READ_WC40_PLL_ANAPLLACONTROL4r(_unit, _pc, _val) \ 3588 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000805e, (_val)) 3589 #define WRITE_WC40_PLL_ANAPLLACONTROL4r(_unit, _pc, _val) \ 3590 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000805e, (_val)) 3591 #define MODIFY_WC40_PLL_ANAPLLACONTROL4r(_unit, _pc, _val, _mask) \ 3592 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805e, (_val), (_mask)) 3593 3594 3595 3596 /**************************************************************************** 3597 * Warpcore_USER_Tx0 3598 */ 3599 /* Tx analog status 0 register */ 3600 #define READ_WC40_TX0_ANATXASTATUS0r(_unit, _pc, _val) \ 3601 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008060, (_val)) 3602 #define WRITE_WC40_TX0_ANATXASTATUS0r(_unit, _pc, _val) \ 3603 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008060, (_val)) 3604 #define MODIFY_WC40_TX0_ANATXASTATUS0r(_unit, _pc, _val, _mask) \ 3605 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008060, (_val), (_mask)) 3606 3607 /* Tx analog control 0 register */ 3608 #define READ_WC40_TX0_ANATXACONTROL0r(_unit, _pc, _val) \ 3609 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008061, (_val)) 3610 #define WRITE_WC40_TX0_ANATXACONTROL0r(_unit, _pc, _val) \ 3611 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008061, (_val)) 3612 #define MODIFY_WC40_TX0_ANATXACONTROL0r(_unit, _pc, _val, _mask) \ 3613 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008061, (_val), (_mask)) 3614 3615 /* Tx test mux data 0 register */ 3616 #define READ_WC40_TX0_ANATXMDATA0r(_unit, _pc, _val) \ 3617 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008062, (_val)) 3618 #define WRITE_WC40_TX0_ANATXMDATA0r(_unit, _pc, _val) \ 3619 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008062, (_val)) 3620 #define MODIFY_WC40_TX0_ANATXMDATA0r(_unit, _pc, _val, _mask) \ 3621 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008062, (_val), (_mask)) 3622 3623 /* Tx test mux data 1 register */ 3624 #define READ_WC40_TX0_ANATXMDATA1r(_unit, _pc, _val) \ 3625 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008063, (_val)) 3626 #define WRITE_WC40_TX0_ANATXMDATA1r(_unit, _pc, _val) \ 3627 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008063, (_val)) 3628 #define MODIFY_WC40_TX0_ANATXMDATA1r(_unit, _pc, _val, _mask) \ 3629 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008063, (_val), (_mask)) 3630 3631 /* Tx analog status 1 register (AFE tx_sts[15:0]) */ 3632 #define READ_WC40_TX0_ANATXASTATUS1r(_unit, _pc, _val) \ 3633 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008064, (_val)) 3634 #define WRITE_WC40_TX0_ANATXASTATUS1r(_unit, _pc, _val) \ 3635 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008064, (_val)) 3636 #define MODIFY_WC40_TX0_ANATXASTATUS1r(_unit, _pc, _val, _mask) \ 3637 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008064, (_val), (_mask)) 3638 3639 /* Tx reserved analog control register (AFE tx_ctrl[15:00], not applicable to XFICore) */ 3640 #define READ_WC40_TX0_ANATXACONTROL1r(_unit, _pc, _val) \ 3641 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008065, (_val)) 3642 #define WRITE_WC40_TX0_ANATXACONTROL1r(_unit, _pc, _val) \ 3643 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008065, (_val)) 3644 #define MODIFY_WC40_TX0_ANATXACONTROL1r(_unit, _pc, _val, _mask) \ 3645 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008065, (_val), (_mask)) 3646 3647 /* Tx reserved analog control register (AFE tx_ctrl[31:16], not applicable to XFICore) */ 3648 #define READ_WC40_TX0_ANATXACONTROL2r(_unit, _pc, _val) \ 3649 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008066, (_val)) 3650 #define WRITE_WC40_TX0_ANATXACONTROL2r(_unit, _pc, _val) \ 3651 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008066, (_val)) 3652 #define MODIFY_WC40_TX0_ANATXACONTROL2r(_unit, _pc, _val, _mask) \ 3653 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008066, (_val), (_mask)) 3654 3655 /* Tx reserved analog control register (AFE tx_ctrl[47:32], not applicable to XFICore) */ 3656 #define READ_WC40_TX0_TX_DRIVERr(_unit, _pc, _val) \ 3657 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008067, (_val)) 3658 #define WRITE_WC40_TX0_TX_DRIVERr(_unit, _pc, _val) \ 3659 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008067, (_val)) 3660 #define MODIFY_WC40_TX0_TX_DRIVERr(_unit, _pc, _val, _mask) \ 3661 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008067, (_val), (_mask)) 3662 3663 /* Tx analog control 5 register */ 3664 #define READ_WC40_TX0_ANATXACONTROL5r(_unit, _pc, _val) \ 3665 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008069, (_val)) 3666 #define WRITE_WC40_TX0_ANATXACONTROL5r(_unit, _pc, _val) \ 3667 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008069, (_val)) 3668 #define MODIFY_WC40_TX0_ANATXACONTROL5r(_unit, _pc, _val, _mask) \ 3669 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008069, (_val), (_mask)) 3670 3671 /* Tx analog control 6 register */ 3672 #define READ_WC40_TX0_ANATXACONTROL6r(_unit, _pc, _val) \ 3673 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000806a, (_val)) 3674 #define WRITE_WC40_TX0_ANATXACONTROL6r(_unit, _pc, _val) \ 3675 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000806a, (_val)) 3676 #define MODIFY_WC40_TX0_ANATXACONTROL6r(_unit, _pc, _val, _mask) \ 3677 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000806a, (_val), (_mask)) 3678 3679 3680 3681 /**************************************************************************** 3682 * Warpcore_USER_Tx1 3683 */ 3684 /* Tx analog status 0 register */ 3685 #define READ_WC40_TX1_ANATXASTATUS0r(_unit, _pc, _val) \ 3686 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008070, (_val)) 3687 #define WRITE_WC40_TX1_ANATXASTATUS0r(_unit, _pc, _val) \ 3688 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008070, (_val)) 3689 #define MODIFY_WC40_TX1_ANATXASTATUS0r(_unit, _pc, _val, _mask) \ 3690 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008070, (_val), (_mask)) 3691 3692 /* Tx analog control 0 register */ 3693 #define READ_WC40_TX1_ANATXACONTROL0r(_unit, _pc, _val) \ 3694 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008071, (_val)) 3695 #define WRITE_WC40_TX1_ANATXACONTROL0r(_unit, _pc, _val) \ 3696 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008071, (_val)) 3697 #define MODIFY_WC40_TX1_ANATXACONTROL0r(_unit, _pc, _val, _mask) \ 3698 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008071, (_val), (_mask)) 3699 3700 /* Tx test mux data 0 register */ 3701 #define READ_WC40_TX1_ANATXMDATA0r(_unit, _pc, _val) \ 3702 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008072, (_val)) 3703 #define WRITE_WC40_TX1_ANATXMDATA0r(_unit, _pc, _val) \ 3704 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008072, (_val)) 3705 #define MODIFY_WC40_TX1_ANATXMDATA0r(_unit, _pc, _val, _mask) \ 3706 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008072, (_val), (_mask)) 3707 3708 /* Tx test mux data 1 register */ 3709 #define READ_WC40_TX1_ANATXMDATA1r(_unit, _pc, _val) \ 3710 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008073, (_val)) 3711 #define WRITE_WC40_TX1_ANATXMDATA1r(_unit, _pc, _val) \ 3712 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008073, (_val)) 3713 #define MODIFY_WC40_TX1_ANATXMDATA1r(_unit, _pc, _val, _mask) \ 3714 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008073, (_val), (_mask)) 3715 3716 /* Tx analog status 1 register (AFE tx_sts[15:0]) */ 3717 #define READ_WC40_TX1_ANATXASTATUS1r(_unit, _pc, _val) \ 3718 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008074, (_val)) 3719 #define WRITE_WC40_TX1_ANATXASTATUS1r(_unit, _pc, _val) \ 3720 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008074, (_val)) 3721 #define MODIFY_WC40_TX1_ANATXASTATUS1r(_unit, _pc, _val, _mask) \ 3722 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008074, (_val), (_mask)) 3723 3724 /* Tx reserved analog control register (AFE tx_ctrl[15:00], not applicable to XFICore) */ 3725 #define READ_WC40_TX1_ANATXACONTROL1r(_unit, _pc, _val) \ 3726 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008075, (_val)) 3727 #define WRITE_WC40_TX1_ANATXACONTROL1r(_unit, _pc, _val) \ 3728 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008075, (_val)) 3729 #define MODIFY_WC40_TX1_ANATXACONTROL1r(_unit, _pc, _val, _mask) \ 3730 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008075, (_val), (_mask)) 3731 3732 /* Tx reserved analog control register (AFE tx_ctrl[31:16], not applicable to XFICore) */ 3733 #define READ_WC40_TX1_ANATXACONTROL2r(_unit, _pc, _val) \ 3734 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008076, (_val)) 3735 #define WRITE_WC40_TX1_ANATXACONTROL2r(_unit, _pc, _val) \ 3736 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008076, (_val)) 3737 #define MODIFY_WC40_TX1_ANATXACONTROL2r(_unit, _pc, _val, _mask) \ 3738 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008076, (_val), (_mask)) 3739 3740 /* Tx reserved analog control register (AFE tx_ctrl[47:32], not applicable to XFICore) */ 3741 #define READ_WC40_TX1_TX_DRIVERr(_unit, _pc, _val) \ 3742 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008077, (_val)) 3743 #define WRITE_WC40_TX1_TX_DRIVERr(_unit, _pc, _val) \ 3744 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008077, (_val)) 3745 #define MODIFY_WC40_TX1_TX_DRIVERr(_unit, _pc, _val, _mask) \ 3746 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008077, (_val), (_mask)) 3747 3748 /* Tx analog control 5 register */ 3749 #define READ_WC40_TX1_ANATXACONTROL5r(_unit, _pc, _val) \ 3750 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008079, (_val)) 3751 #define WRITE_WC40_TX1_ANATXACONTROL5r(_unit, _pc, _val) \ 3752 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008079, (_val)) 3753 #define MODIFY_WC40_TX1_ANATXACONTROL5r(_unit, _pc, _val, _mask) \ 3754 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008079, (_val), (_mask)) 3755 3756 /* Tx analog control 6 register */ 3757 #define READ_WC40_TX1_ANATXACONTROL6r(_unit, _pc, _val) \ 3758 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000807a, (_val)) 3759 #define WRITE_WC40_TX1_ANATXACONTROL6r(_unit, _pc, _val) \ 3760 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000807a, (_val)) 3761 #define MODIFY_WC40_TX1_ANATXACONTROL6r(_unit, _pc, _val, _mask) \ 3762 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000807a, (_val), (_mask)) 3763 3764 3765 3766 /**************************************************************************** 3767 * Warpcore_USER_Tx2 3768 */ 3769 /* Tx analog status 0 register */ 3770 #define READ_WC40_TX2_ANATXASTATUS0r(_unit, _pc, _val) \ 3771 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008080, (_val)) 3772 #define WRITE_WC40_TX2_ANATXASTATUS0r(_unit, _pc, _val) \ 3773 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008080, (_val)) 3774 #define MODIFY_WC40_TX2_ANATXASTATUS0r(_unit, _pc, _val, _mask) \ 3775 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008080, (_val), (_mask)) 3776 3777 /* Tx analog control 0 register */ 3778 #define READ_WC40_TX2_ANATXACONTROL0r(_unit, _pc, _val) \ 3779 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008081, (_val)) 3780 #define WRITE_WC40_TX2_ANATXACONTROL0r(_unit, _pc, _val) \ 3781 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008081, (_val)) 3782 #define MODIFY_WC40_TX2_ANATXACONTROL0r(_unit, _pc, _val, _mask) \ 3783 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008081, (_val), (_mask)) 3784 3785 /* Tx test mux data 0 register */ 3786 #define READ_WC40_TX2_ANATXMDATA0r(_unit, _pc, _val) \ 3787 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008082, (_val)) 3788 #define WRITE_WC40_TX2_ANATXMDATA0r(_unit, _pc, _val) \ 3789 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008082, (_val)) 3790 #define MODIFY_WC40_TX2_ANATXMDATA0r(_unit, _pc, _val, _mask) \ 3791 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008082, (_val), (_mask)) 3792 3793 /* Tx test mux data 1 register */ 3794 #define READ_WC40_TX2_ANATXMDATA1r(_unit, _pc, _val) \ 3795 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008083, (_val)) 3796 #define WRITE_WC40_TX2_ANATXMDATA1r(_unit, _pc, _val) \ 3797 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008083, (_val)) 3798 #define MODIFY_WC40_TX2_ANATXMDATA1r(_unit, _pc, _val, _mask) \ 3799 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008083, (_val), (_mask)) 3800 3801 /* Tx analog status 1 register (AFE tx_sts[15:0]) */ 3802 #define READ_WC40_TX2_ANATXASTATUS1r(_unit, _pc, _val) \ 3803 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008084, (_val)) 3804 #define WRITE_WC40_TX2_ANATXASTATUS1r(_unit, _pc, _val) \ 3805 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008084, (_val)) 3806 #define MODIFY_WC40_TX2_ANATXASTATUS1r(_unit, _pc, _val, _mask) \ 3807 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008084, (_val), (_mask)) 3808 3809 /* Tx reserved analog control register (AFE tx_ctrl[15:00], not applicable to XFICore) */ 3810 #define READ_WC40_TX2_ANATXACONTROL1r(_unit, _pc, _val) \ 3811 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008085, (_val)) 3812 #define WRITE_WC40_TX2_ANATXACONTROL1r(_unit, _pc, _val) \ 3813 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008085, (_val)) 3814 #define MODIFY_WC40_TX2_ANATXACONTROL1r(_unit, _pc, _val, _mask) \ 3815 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008085, (_val), (_mask)) 3816 3817 /* Tx reserved analog control register (AFE tx_ctrl[31:16], not applicable to XFICore) */ 3818 #define READ_WC40_TX2_ANATXACONTROL2r(_unit, _pc, _val) \ 3819 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008086, (_val)) 3820 #define WRITE_WC40_TX2_ANATXACONTROL2r(_unit, _pc, _val) \ 3821 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008086, (_val)) 3822 #define MODIFY_WC40_TX2_ANATXACONTROL2r(_unit, _pc, _val, _mask) \ 3823 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008086, (_val), (_mask)) 3824 3825 /* Tx reserved analog control register (AFE tx_ctrl[47:32], not applicable to XFICore) */ 3826 #define READ_WC40_TX2_TX_DRIVERr(_unit, _pc, _val) \ 3827 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008087, (_val)) 3828 #define WRITE_WC40_TX2_TX_DRIVERr(_unit, _pc, _val) \ 3829 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008087, (_val)) 3830 #define MODIFY_WC40_TX2_TX_DRIVERr(_unit, _pc, _val, _mask) \ 3831 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008087, (_val), (_mask)) 3832 3833 /* Tx analog control 5 register */ 3834 #define READ_WC40_TX2_ANATXACONTROL5r(_unit, _pc, _val) \ 3835 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008089, (_val)) 3836 #define WRITE_WC40_TX2_ANATXACONTROL5r(_unit, _pc, _val) \ 3837 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008089, (_val)) 3838 #define MODIFY_WC40_TX2_ANATXACONTROL5r(_unit, _pc, _val, _mask) \ 3839 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008089, (_val), (_mask)) 3840 3841 /* Tx analog control 6 register */ 3842 #define READ_WC40_TX2_ANATXACONTROL6r(_unit, _pc, _val) \ 3843 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000808a, (_val)) 3844 #define WRITE_WC40_TX2_ANATXACONTROL6r(_unit, _pc, _val) \ 3845 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000808a, (_val)) 3846 #define MODIFY_WC40_TX2_ANATXACONTROL6r(_unit, _pc, _val, _mask) \ 3847 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000808a, (_val), (_mask)) 3848 3849 3850 3851 /**************************************************************************** 3852 * Warpcore_USER_Tx3 3853 */ 3854 /* Tx analog status 0 register */ 3855 #define READ_WC40_TX3_ANATXASTATUS0r(_unit, _pc, _val) \ 3856 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008090, (_val)) 3857 #define WRITE_WC40_TX3_ANATXASTATUS0r(_unit, _pc, _val) \ 3858 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008090, (_val)) 3859 #define MODIFY_WC40_TX3_ANATXASTATUS0r(_unit, _pc, _val, _mask) \ 3860 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008090, (_val), (_mask)) 3861 3862 /* Tx analog control 0 register */ 3863 #define READ_WC40_TX3_ANATXACONTROL0r(_unit, _pc, _val) \ 3864 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008091, (_val)) 3865 #define WRITE_WC40_TX3_ANATXACONTROL0r(_unit, _pc, _val) \ 3866 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008091, (_val)) 3867 #define MODIFY_WC40_TX3_ANATXACONTROL0r(_unit, _pc, _val, _mask) \ 3868 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008091, (_val), (_mask)) 3869 3870 /* Tx test mux data 0 register */ 3871 #define READ_WC40_TX3_ANATXMDATA0r(_unit, _pc, _val) \ 3872 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008092, (_val)) 3873 #define WRITE_WC40_TX3_ANATXMDATA0r(_unit, _pc, _val) \ 3874 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008092, (_val)) 3875 #define MODIFY_WC40_TX3_ANATXMDATA0r(_unit, _pc, _val, _mask) \ 3876 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008092, (_val), (_mask)) 3877 3878 /* Tx test mux data 1 register */ 3879 #define READ_WC40_TX3_ANATXMDATA1r(_unit, _pc, _val) \ 3880 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008093, (_val)) 3881 #define WRITE_WC40_TX3_ANATXMDATA1r(_unit, _pc, _val) \ 3882 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008093, (_val)) 3883 #define MODIFY_WC40_TX3_ANATXMDATA1r(_unit, _pc, _val, _mask) \ 3884 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008093, (_val), (_mask)) 3885 3886 /* Tx analog status 1 register (AFE tx_sts[15:0]) */ 3887 #define READ_WC40_TX3_ANATXASTATUS1r(_unit, _pc, _val) \ 3888 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008094, (_val)) 3889 #define WRITE_WC40_TX3_ANATXASTATUS1r(_unit, _pc, _val) \ 3890 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008094, (_val)) 3891 #define MODIFY_WC40_TX3_ANATXASTATUS1r(_unit, _pc, _val, _mask) \ 3892 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008094, (_val), (_mask)) 3893 3894 /* Tx reserved analog control register (AFE tx_ctrl[15:00], not applicable to XFICore) */ 3895 #define READ_WC40_TX3_ANATXACONTROL1r(_unit, _pc, _val) \ 3896 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008095, (_val)) 3897 #define WRITE_WC40_TX3_ANATXACONTROL1r(_unit, _pc, _val) \ 3898 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008095, (_val)) 3899 #define MODIFY_WC40_TX3_ANATXACONTROL1r(_unit, _pc, _val, _mask) \ 3900 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008095, (_val), (_mask)) 3901 3902 /* Tx reserved analog control register (AFE tx_ctrl[31:16], not applicable to XFICore) */ 3903 #define READ_WC40_TX3_ANATXACONTROL2r(_unit, _pc, _val) \ 3904 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008096, (_val)) 3905 #define WRITE_WC40_TX3_ANATXACONTROL2r(_unit, _pc, _val) \ 3906 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008096, (_val)) 3907 #define MODIFY_WC40_TX3_ANATXACONTROL2r(_unit, _pc, _val, _mask) \ 3908 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008096, (_val), (_mask)) 3909 3910 /* Tx reserved analog control register (AFE tx_ctrl[47:32], not applicable to XFICore) */ 3911 #define READ_WC40_TX3_TX_DRIVERr(_unit, _pc, _val) \ 3912 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008097, (_val)) 3913 #define WRITE_WC40_TX3_TX_DRIVERr(_unit, _pc, _val) \ 3914 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008097, (_val)) 3915 #define MODIFY_WC40_TX3_TX_DRIVERr(_unit, _pc, _val, _mask) \ 3916 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008097, (_val), (_mask)) 3917 3918 /* Tx analog control 5 register */ 3919 #define READ_WC40_TX3_ANATXACONTROL5r(_unit, _pc, _val) \ 3920 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008099, (_val)) 3921 #define WRITE_WC40_TX3_ANATXACONTROL5r(_unit, _pc, _val) \ 3922 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008099, (_val)) 3923 #define MODIFY_WC40_TX3_ANATXACONTROL5r(_unit, _pc, _val, _mask) \ 3924 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008099, (_val), (_mask)) 3925 3926 /* Tx analog control 6 register */ 3927 #define READ_WC40_TX3_ANATXACONTROL6r(_unit, _pc, _val) \ 3928 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000809a, (_val)) 3929 #define WRITE_WC40_TX3_ANATXACONTROL6r(_unit, _pc, _val) \ 3930 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000809a, (_val)) 3931 #define MODIFY_WC40_TX3_ANATXACONTROL6r(_unit, _pc, _val, _mask) \ 3932 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000809a, (_val), (_mask)) 3933 3934 3935 3936 /**************************************************************************** 3937 * Warpcore_USER_TxB 3938 */ 3939 /* Tx analog status 0 register */ 3940 #define READ_WC40_TXB_ANATXASTATUS0r(_unit, _pc, _val) \ 3941 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080a0, (_val)) 3942 #define WRITE_WC40_TXB_ANATXASTATUS0r(_unit, _pc, _val) \ 3943 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080a0, (_val)) 3944 #define MODIFY_WC40_TXB_ANATXASTATUS0r(_unit, _pc, _val, _mask) \ 3945 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a0, (_val), (_mask)) 3946 3947 /* Tx analog control 0 register */ 3948 #define READ_WC40_TXB_ANATXACONTROL0r(_unit, _pc, _val) \ 3949 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080a1, (_val)) 3950 #define WRITE_WC40_TXB_ANATXACONTROL0r(_unit, _pc, _val) \ 3951 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080a1, (_val)) 3952 #define MODIFY_WC40_TXB_ANATXACONTROL0r(_unit, _pc, _val, _mask) \ 3953 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a1, (_val), (_mask)) 3954 3955 /* Tx test mux data 0 register */ 3956 #define READ_WC40_TXB_ANATXMDATA0r(_unit, _pc, _val) \ 3957 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080a2, (_val)) 3958 #define WRITE_WC40_TXB_ANATXMDATA0r(_unit, _pc, _val) \ 3959 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080a2, (_val)) 3960 #define MODIFY_WC40_TXB_ANATXMDATA0r(_unit, _pc, _val, _mask) \ 3961 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a2, (_val), (_mask)) 3962 3963 /* Tx test mux data 1 register */ 3964 #define READ_WC40_TXB_ANATXMDATA1r(_unit, _pc, _val) \ 3965 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080a3, (_val)) 3966 #define WRITE_WC40_TXB_ANATXMDATA1r(_unit, _pc, _val) \ 3967 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080a3, (_val)) 3968 #define MODIFY_WC40_TXB_ANATXMDATA1r(_unit, _pc, _val, _mask) \ 3969 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a3, (_val), (_mask)) 3970 3971 /* Tx analog status 1 register (AFE tx_sts[15:0]) */ 3972 #define READ_WC40_TXB_ANATXASTATUS1r(_unit, _pc, _val) \ 3973 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080a4, (_val)) 3974 #define WRITE_WC40_TXB_ANATXASTATUS1r(_unit, _pc, _val) \ 3975 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080a4, (_val)) 3976 #define MODIFY_WC40_TXB_ANATXASTATUS1r(_unit, _pc, _val, _mask) \ 3977 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a4, (_val), (_mask)) 3978 3979 /* Tx reserved analog control register (AFE tx_ctrl[15:00], not applicable to XFICore) */ 3980 #define READ_WC40_TXB_ANATXACONTROL1r(_unit, _pc, _val) \ 3981 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080a5, (_val)) 3982 #define WRITE_WC40_TXB_ANATXACONTROL1r(_unit, _pc, _val) \ 3983 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080a5, (_val)) 3984 #define MODIFY_WC40_TXB_ANATXACONTROL1r(_unit, _pc, _val, _mask) \ 3985 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a5, (_val), (_mask)) 3986 3987 /* Tx reserved analog control register (AFE tx_ctrl[31:16], not applicable to XFICore) */ 3988 #define READ_WC40_TXB_ANATXACONTROL2r(_unit, _pc, _val) \ 3989 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080a6, (_val)) 3990 #define WRITE_WC40_TXB_ANATXACONTROL2r(_unit, _pc, _val) \ 3991 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080a6, (_val)) 3992 #define MODIFY_WC40_TXB_ANATXACONTROL2r(_unit, _pc, _val, _mask) \ 3993 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a6, (_val), (_mask)) 3994 3995 /* Tx reserved analog control register (AFE tx_ctrl[47:32], not applicable to XFICore) */ 3996 #define READ_WC40_TXB_TX_DRIVERr(_unit, _pc, _val) \ 3997 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080a7, (_val)) 3998 #define WRITE_WC40_TXB_TX_DRIVERr(_unit, _pc, _val) \ 3999 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080a7, (_val)) 4000 #define MODIFY_WC40_TXB_TX_DRIVERr(_unit, _pc, _val, _mask) \ 4001 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a7, (_val), (_mask)) 4002 4003 /* Tx analog control 5 register */ 4004 #define READ_WC40_TXB_ANATXACONTROL5r(_unit, _pc, _val) \ 4005 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080a9, (_val)) 4006 #define WRITE_WC40_TXB_ANATXACONTROL5r(_unit, _pc, _val) \ 4007 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080a9, (_val)) 4008 #define MODIFY_WC40_TXB_ANATXACONTROL5r(_unit, _pc, _val, _mask) \ 4009 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a9, (_val), (_mask)) 4010 4011 /* Tx analog control 6 register */ 4012 #define READ_WC40_TXB_ANATXACONTROL6r(_unit, _pc, _val) \ 4013 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080aa, (_val)) 4014 #define WRITE_WC40_TXB_ANATXACONTROL6r(_unit, _pc, _val) \ 4015 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080aa, (_val)) 4016 #define MODIFY_WC40_TXB_ANATXACONTROL6r(_unit, _pc, _val, _mask) \ 4017 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080aa, (_val), (_mask)) 4018 4019 4020 4021 /**************************************************************************** 4022 * Warpcore_USER_Rx0 4023 */ 4024 /* Rx lane status register */ 4025 #define READ_WC40_RX0_ANARXSTATUSr(_unit, _pc, _val) \ 4026 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080b0, (_val)) 4027 #define WRITE_WC40_RX0_ANARXSTATUSr(_unit, _pc, _val) \ 4028 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080b0, (_val)) 4029 #define MODIFY_WC40_RX0_ANARXSTATUSr(_unit, _pc, _val, _mask) \ 4030 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b0, (_val), (_mask)) 4031 4032 /* Rx lane control register */ 4033 #define READ_WC40_RX0_ANARXCONTROLr(_unit, _pc, _val) \ 4034 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080b1, (_val)) 4035 #define WRITE_WC40_RX0_ANARXCONTROLr(_unit, _pc, _val) \ 4036 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080b1, (_val)) 4037 #define MODIFY_WC40_RX0_ANARXCONTROLr(_unit, _pc, _val, _mask) \ 4038 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b1, (_val), (_mask)) 4039 4040 /* Rx Sigdet Control */ 4041 #define READ_WC40_RX0_ANARXSIGDETr(_unit, _pc, _val) \ 4042 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080b4, (_val)) 4043 #define WRITE_WC40_RX0_ANARXSIGDETr(_unit, _pc, _val) \ 4044 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080b4, (_val)) 4045 #define MODIFY_WC40_RX0_ANARXSIGDETr(_unit, _pc, _val, _mask) \ 4046 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b4, (_val), (_mask)) 4047 4048 /* Rx reserved analog control register */ 4049 #define READ_WC40_RX0_ANARXACONTROL4r(_unit, _pc, _val) \ 4050 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080b5, (_val)) 4051 #define WRITE_WC40_RX0_ANARXACONTROL4r(_unit, _pc, _val) \ 4052 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080b5, (_val)) 4053 #define MODIFY_WC40_RX0_ANARXACONTROL4r(_unit, _pc, _val, _mask) \ 4054 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b5, (_val), (_mask)) 4055 4056 /* Rx 1G Control2 register */ 4057 #define READ_WC40_RX0_ANARXCONTROL2_1Gr(_unit, _pc, _val) \ 4058 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080b6, (_val)) 4059 #define WRITE_WC40_RX0_ANARXCONTROL2_1Gr(_unit, _pc, _val) \ 4060 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080b6, (_val)) 4061 #define MODIFY_WC40_RX0_ANARXCONTROL2_1Gr(_unit, _pc, _val, _mask) \ 4062 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b6, (_val), (_mask)) 4063 4064 /* Rx lane control register */ 4065 #define READ_WC40_RX0_ANARXTESTr(_unit, _pc, _val) \ 4066 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080b8, (_val)) 4067 #define WRITE_WC40_RX0_ANARXTESTr(_unit, _pc, _val) \ 4068 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080b8, (_val)) 4069 #define MODIFY_WC40_RX0_ANARXTESTr(_unit, _pc, _val, _mask) \ 4070 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b8, (_val), (_mask)) 4071 4072 /* Rx 1G Control register */ 4073 #define READ_WC40_RX0_ANARXCONTROL1Gr(_unit, _pc, _val) \ 4074 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080b9, (_val)) 4075 #define WRITE_WC40_RX0_ANARXCONTROL1Gr(_unit, _pc, _val) \ 4076 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080b9, (_val)) 4077 #define MODIFY_WC40_RX0_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \ 4078 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b9, (_val), (_mask)) 4079 4080 /* Rx PCI Control register */ 4081 #define READ_WC40_RX0_ANARXCONTROLPCIr(_unit, _pc, _val) \ 4082 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080ba, (_val)) 4083 #define WRITE_WC40_RX0_ANARXCONTROLPCIr(_unit, _pc, _val) \ 4084 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080ba, (_val)) 4085 #define MODIFY_WC40_RX0_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \ 4086 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ba, (_val), (_mask)) 4087 4088 /* Rx analog status register (AFE rx_sts[15:0]) */ 4089 #define READ_WC40_RX0_ANARXASTATUSr(_unit, _pc, _val) \ 4090 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080bb, (_val)) 4091 #define WRITE_WC40_RX0_ANARXASTATUSr(_unit, _pc, _val) \ 4092 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080bb, (_val)) 4093 #define MODIFY_WC40_RX0_ANARXASTATUSr(_unit, _pc, _val, _mask) \ 4094 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bb, (_val), (_mask)) 4095 4096 /* Rx reserved analog control register (AFE rx_ctrl[15:00], not applicable to XFICore) */ 4097 #define READ_WC40_RX0_ANARXACONTROL1r(_unit, _pc, _val) \ 4098 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080bc, (_val)) 4099 #define WRITE_WC40_RX0_ANARXACONTROL1r(_unit, _pc, _val) \ 4100 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080bc, (_val)) 4101 #define MODIFY_WC40_RX0_ANARXACONTROL1r(_unit, _pc, _val, _mask) \ 4102 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bc, (_val), (_mask)) 4103 4104 /* Rx reserved analog control register (AFE rx_ctrl[31:16], not applicable to XFICore) */ 4105 #define READ_WC40_RX0_ANARXACONTROL2r(_unit, _pc, _val) \ 4106 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080bd, (_val)) 4107 #define WRITE_WC40_RX0_ANARXACONTROL2r(_unit, _pc, _val) \ 4108 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080bd, (_val)) 4109 #define MODIFY_WC40_RX0_ANARXACONTROL2r(_unit, _pc, _val, _mask) \ 4110 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bd, (_val), (_mask)) 4111 4112 /* Rx reserved analog control register (AFE rx_ctrl[47:32], not applicable to XFICore) */ 4113 #define READ_WC40_RX0_ANARXACONTROL3r(_unit, _pc, _val) \ 4114 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080be, (_val)) 4115 #define WRITE_WC40_RX0_ANARXACONTROL3r(_unit, _pc, _val) \ 4116 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080be, (_val)) 4117 #define MODIFY_WC40_RX0_ANARXACONTROL3r(_unit, _pc, _val, _mask) \ 4118 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080be, (_val), (_mask)) 4119 4120 4121 4122 /**************************************************************************** 4123 * Warpcore_USER_Rx1 4124 */ 4125 /* Rx lane status register */ 4126 #define READ_WC40_RX1_ANARXSTATUSr(_unit, _pc, _val) \ 4127 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080c0, (_val)) 4128 #define WRITE_WC40_RX1_ANARXSTATUSr(_unit, _pc, _val) \ 4129 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080c0, (_val)) 4130 #define MODIFY_WC40_RX1_ANARXSTATUSr(_unit, _pc, _val, _mask) \ 4131 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c0, (_val), (_mask)) 4132 4133 /* Rx lane control register */ 4134 #define READ_WC40_RX1_ANARXCONTROLr(_unit, _pc, _val) \ 4135 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080c1, (_val)) 4136 #define WRITE_WC40_RX1_ANARXCONTROLr(_unit, _pc, _val) \ 4137 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080c1, (_val)) 4138 #define MODIFY_WC40_RX1_ANARXCONTROLr(_unit, _pc, _val, _mask) \ 4139 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c1, (_val), (_mask)) 4140 4141 /* Rx Sigdet Control */ 4142 #define READ_WC40_RX1_ANARXSIGDETr(_unit, _pc, _val) \ 4143 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080c4, (_val)) 4144 #define WRITE_WC40_RX1_ANARXSIGDETr(_unit, _pc, _val) \ 4145 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080c4, (_val)) 4146 #define MODIFY_WC40_RX1_ANARXSIGDETr(_unit, _pc, _val, _mask) \ 4147 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c4, (_val), (_mask)) 4148 4149 /* Rx reserved analog control register */ 4150 #define READ_WC40_RX1_ANARXACONTROL4r(_unit, _pc, _val) \ 4151 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080c5, (_val)) 4152 #define WRITE_WC40_RX1_ANARXACONTROL4r(_unit, _pc, _val) \ 4153 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080c5, (_val)) 4154 #define MODIFY_WC40_RX1_ANARXACONTROL4r(_unit, _pc, _val, _mask) \ 4155 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c5, (_val), (_mask)) 4156 4157 /* Rx 1G Control2 register */ 4158 #define READ_WC40_RX1_ANARXCONTROL2_1Gr(_unit, _pc, _val) \ 4159 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080c6, (_val)) 4160 #define WRITE_WC40_RX1_ANARXCONTROL2_1Gr(_unit, _pc, _val) \ 4161 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080c6, (_val)) 4162 #define MODIFY_WC40_RX1_ANARXCONTROL2_1Gr(_unit, _pc, _val, _mask) \ 4163 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c6, (_val), (_mask)) 4164 4165 /* Rx lane control register */ 4166 #define READ_WC40_RX1_ANARXTESTr(_unit, _pc, _val) \ 4167 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080c8, (_val)) 4168 #define WRITE_WC40_RX1_ANARXTESTr(_unit, _pc, _val) \ 4169 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080c8, (_val)) 4170 #define MODIFY_WC40_RX1_ANARXTESTr(_unit, _pc, _val, _mask) \ 4171 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c8, (_val), (_mask)) 4172 4173 /* Rx 1G Control register */ 4174 #define READ_WC40_RX1_ANARXCONTROL1Gr(_unit, _pc, _val) \ 4175 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080c9, (_val)) 4176 #define WRITE_WC40_RX1_ANARXCONTROL1Gr(_unit, _pc, _val) \ 4177 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080c9, (_val)) 4178 #define MODIFY_WC40_RX1_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \ 4179 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c9, (_val), (_mask)) 4180 4181 /* Rx PCI Control register */ 4182 #define READ_WC40_RX1_ANARXCONTROLPCIr(_unit, _pc, _val) \ 4183 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080ca, (_val)) 4184 #define WRITE_WC40_RX1_ANARXCONTROLPCIr(_unit, _pc, _val) \ 4185 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080ca, (_val)) 4186 #define MODIFY_WC40_RX1_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \ 4187 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ca, (_val), (_mask)) 4188 4189 /* Rx analog status register (AFE rx_sts[15:0]) */ 4190 #define READ_WC40_RX1_ANARXASTATUSr(_unit, _pc, _val) \ 4191 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080cb, (_val)) 4192 #define WRITE_WC40_RX1_ANARXASTATUSr(_unit, _pc, _val) \ 4193 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080cb, (_val)) 4194 #define MODIFY_WC40_RX1_ANARXASTATUSr(_unit, _pc, _val, _mask) \ 4195 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cb, (_val), (_mask)) 4196 4197 /* Rx reserved analog control register (AFE rx_ctrl[15:00], not applicable to XFICore) */ 4198 #define READ_WC40_RX1_ANARXACONTROL1r(_unit, _pc, _val) \ 4199 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080cc, (_val)) 4200 #define WRITE_WC40_RX1_ANARXACONTROL1r(_unit, _pc, _val) \ 4201 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080cc, (_val)) 4202 #define MODIFY_WC40_RX1_ANARXACONTROL1r(_unit, _pc, _val, _mask) \ 4203 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cc, (_val), (_mask)) 4204 4205 /* Rx reserved analog control register (AFE rx_ctrl[31:16], not applicable to XFICore) */ 4206 #define READ_WC40_RX1_ANARXACONTROL2r(_unit, _pc, _val) \ 4207 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080cd, (_val)) 4208 #define WRITE_WC40_RX1_ANARXACONTROL2r(_unit, _pc, _val) \ 4209 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080cd, (_val)) 4210 #define MODIFY_WC40_RX1_ANARXACONTROL2r(_unit, _pc, _val, _mask) \ 4211 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cd, (_val), (_mask)) 4212 4213 /* Rx reserved analog control register (AFE rx_ctrl[47:32], not applicable to XFICore) */ 4214 #define READ_WC40_RX1_ANARXACONTROL3r(_unit, _pc, _val) \ 4215 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080ce, (_val)) 4216 #define WRITE_WC40_RX1_ANARXACONTROL3r(_unit, _pc, _val) \ 4217 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080ce, (_val)) 4218 #define MODIFY_WC40_RX1_ANARXACONTROL3r(_unit, _pc, _val, _mask) \ 4219 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ce, (_val), (_mask)) 4220 4221 4222 4223 /**************************************************************************** 4224 * Warpcore_USER_Rx2 4225 */ 4226 /* Rx lane status register */ 4227 #define READ_WC40_RX2_ANARXSTATUSr(_unit, _pc, _val) \ 4228 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080d0, (_val)) 4229 #define WRITE_WC40_RX2_ANARXSTATUSr(_unit, _pc, _val) \ 4230 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080d0, (_val)) 4231 #define MODIFY_WC40_RX2_ANARXSTATUSr(_unit, _pc, _val, _mask) \ 4232 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d0, (_val), (_mask)) 4233 4234 /* Rx lane control register */ 4235 #define READ_WC40_RX2_ANARXCONTROLr(_unit, _pc, _val) \ 4236 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080d1, (_val)) 4237 #define WRITE_WC40_RX2_ANARXCONTROLr(_unit, _pc, _val) \ 4238 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080d1, (_val)) 4239 #define MODIFY_WC40_RX2_ANARXCONTROLr(_unit, _pc, _val, _mask) \ 4240 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d1, (_val), (_mask)) 4241 4242 /* Rx Sigdet Control */ 4243 #define READ_WC40_RX2_ANARXSIGDETr(_unit, _pc, _val) \ 4244 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080d4, (_val)) 4245 #define WRITE_WC40_RX2_ANARXSIGDETr(_unit, _pc, _val) \ 4246 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080d4, (_val)) 4247 #define MODIFY_WC40_RX2_ANARXSIGDETr(_unit, _pc, _val, _mask) \ 4248 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d4, (_val), (_mask)) 4249 4250 /* Rx reserved analog control register */ 4251 #define READ_WC40_RX2_ANARXACONTROL4r(_unit, _pc, _val) \ 4252 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080d5, (_val)) 4253 #define WRITE_WC40_RX2_ANARXACONTROL4r(_unit, _pc, _val) \ 4254 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080d5, (_val)) 4255 #define MODIFY_WC40_RX2_ANARXACONTROL4r(_unit, _pc, _val, _mask) \ 4256 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d5, (_val), (_mask)) 4257 4258 /* Rx 1G Control2 register */ 4259 #define READ_WC40_RX2_ANARXCONTROL2_1Gr(_unit, _pc, _val) \ 4260 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080d6, (_val)) 4261 #define WRITE_WC40_RX2_ANARXCONTROL2_1Gr(_unit, _pc, _val) \ 4262 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080d6, (_val)) 4263 #define MODIFY_WC40_RX2_ANARXCONTROL2_1Gr(_unit, _pc, _val, _mask) \ 4264 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d6, (_val), (_mask)) 4265 4266 /* Rx lane control register */ 4267 #define READ_WC40_RX2_ANARXTESTr(_unit, _pc, _val) \ 4268 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080d8, (_val)) 4269 #define WRITE_WC40_RX2_ANARXTESTr(_unit, _pc, _val) \ 4270 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080d8, (_val)) 4271 #define MODIFY_WC40_RX2_ANARXTESTr(_unit, _pc, _val, _mask) \ 4272 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d8, (_val), (_mask)) 4273 4274 /* Rx 1G Control register */ 4275 #define READ_WC40_RX2_ANARXCONTROL1Gr(_unit, _pc, _val) \ 4276 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080d9, (_val)) 4277 #define WRITE_WC40_RX2_ANARXCONTROL1Gr(_unit, _pc, _val) \ 4278 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080d9, (_val)) 4279 #define MODIFY_WC40_RX2_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \ 4280 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d9, (_val), (_mask)) 4281 4282 /* Rx PCI Control register */ 4283 #define READ_WC40_RX2_ANARXCONTROLPCIr(_unit, _pc, _val) \ 4284 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080da, (_val)) 4285 #define WRITE_WC40_RX2_ANARXCONTROLPCIr(_unit, _pc, _val) \ 4286 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080da, (_val)) 4287 #define MODIFY_WC40_RX2_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \ 4288 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080da, (_val), (_mask)) 4289 4290 /* Rx analog status register (AFE rx_sts[15:0]) */ 4291 #define READ_WC40_RX2_ANARXASTATUSr(_unit, _pc, _val) \ 4292 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080db, (_val)) 4293 #define WRITE_WC40_RX2_ANARXASTATUSr(_unit, _pc, _val) \ 4294 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080db, (_val)) 4295 #define MODIFY_WC40_RX2_ANARXASTATUSr(_unit, _pc, _val, _mask) \ 4296 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080db, (_val), (_mask)) 4297 4298 /* Rx reserved analog control register (AFE rx_ctrl[15:00], not applicable to XFICore) */ 4299 #define READ_WC40_RX2_ANARXACONTROL1r(_unit, _pc, _val) \ 4300 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080dc, (_val)) 4301 #define WRITE_WC40_RX2_ANARXACONTROL1r(_unit, _pc, _val) \ 4302 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080dc, (_val)) 4303 #define MODIFY_WC40_RX2_ANARXACONTROL1r(_unit, _pc, _val, _mask) \ 4304 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080dc, (_val), (_mask)) 4305 4306 /* Rx reserved analog control register (AFE rx_ctrl[31:16], not applicable to XFICore) */ 4307 #define READ_WC40_RX2_ANARXACONTROL2r(_unit, _pc, _val) \ 4308 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080dd, (_val)) 4309 #define WRITE_WC40_RX2_ANARXACONTROL2r(_unit, _pc, _val) \ 4310 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080dd, (_val)) 4311 #define MODIFY_WC40_RX2_ANARXACONTROL2r(_unit, _pc, _val, _mask) \ 4312 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080dd, (_val), (_mask)) 4313 4314 /* Rx reserved analog control register (AFE rx_ctrl[47:32], not applicable to XFICore) */ 4315 #define READ_WC40_RX2_ANARXACONTROL3r(_unit, _pc, _val) \ 4316 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080de, (_val)) 4317 #define WRITE_WC40_RX2_ANARXACONTROL3r(_unit, _pc, _val) \ 4318 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080de, (_val)) 4319 #define MODIFY_WC40_RX2_ANARXACONTROL3r(_unit, _pc, _val, _mask) \ 4320 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080de, (_val), (_mask)) 4321 4322 4323 4324 /**************************************************************************** 4325 * Warpcore_USER_Rx3 4326 */ 4327 /* Rx lane status register */ 4328 #define READ_WC40_RX3_ANARXSTATUSr(_unit, _pc, _val) \ 4329 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080e0, (_val)) 4330 #define WRITE_WC40_RX3_ANARXSTATUSr(_unit, _pc, _val) \ 4331 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080e0, (_val)) 4332 #define MODIFY_WC40_RX3_ANARXSTATUSr(_unit, _pc, _val, _mask) \ 4333 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e0, (_val), (_mask)) 4334 4335 /* Rx lane control register */ 4336 #define READ_WC40_RX3_ANARXCONTROLr(_unit, _pc, _val) \ 4337 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080e1, (_val)) 4338 #define WRITE_WC40_RX3_ANARXCONTROLr(_unit, _pc, _val) \ 4339 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080e1, (_val)) 4340 #define MODIFY_WC40_RX3_ANARXCONTROLr(_unit, _pc, _val, _mask) \ 4341 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e1, (_val), (_mask)) 4342 4343 /* Rx Sigdet Control */ 4344 #define READ_WC40_RX3_ANARXSIGDETr(_unit, _pc, _val) \ 4345 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080e4, (_val)) 4346 #define WRITE_WC40_RX3_ANARXSIGDETr(_unit, _pc, _val) \ 4347 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080e4, (_val)) 4348 #define MODIFY_WC40_RX3_ANARXSIGDETr(_unit, _pc, _val, _mask) \ 4349 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e4, (_val), (_mask)) 4350 4351 /* Rx reserved analog control register */ 4352 #define READ_WC40_RX3_ANARXACONTROL4r(_unit, _pc, _val) \ 4353 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080e5, (_val)) 4354 #define WRITE_WC40_RX3_ANARXACONTROL4r(_unit, _pc, _val) \ 4355 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080e5, (_val)) 4356 #define MODIFY_WC40_RX3_ANARXACONTROL4r(_unit, _pc, _val, _mask) \ 4357 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e5, (_val), (_mask)) 4358 4359 /* Rx 1G Control2 register */ 4360 #define READ_WC40_RX3_ANARXCONTROL2_1Gr(_unit, _pc, _val) \ 4361 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080e6, (_val)) 4362 #define WRITE_WC40_RX3_ANARXCONTROL2_1Gr(_unit, _pc, _val) \ 4363 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080e6, (_val)) 4364 #define MODIFY_WC40_RX3_ANARXCONTROL2_1Gr(_unit, _pc, _val, _mask) \ 4365 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e6, (_val), (_mask)) 4366 4367 /* Rx lane control register */ 4368 #define READ_WC40_RX3_ANARXTESTr(_unit, _pc, _val) \ 4369 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080e8, (_val)) 4370 #define WRITE_WC40_RX3_ANARXTESTr(_unit, _pc, _val) \ 4371 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080e8, (_val)) 4372 #define MODIFY_WC40_RX3_ANARXTESTr(_unit, _pc, _val, _mask) \ 4373 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e8, (_val), (_mask)) 4374 4375 /* Rx 1G Control register */ 4376 #define READ_WC40_RX3_ANARXCONTROL1Gr(_unit, _pc, _val) \ 4377 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080e9, (_val)) 4378 #define WRITE_WC40_RX3_ANARXCONTROL1Gr(_unit, _pc, _val) \ 4379 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080e9, (_val)) 4380 #define MODIFY_WC40_RX3_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \ 4381 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e9, (_val), (_mask)) 4382 4383 /* Rx PCI Control register */ 4384 #define READ_WC40_RX3_ANARXCONTROLPCIr(_unit, _pc, _val) \ 4385 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080ea, (_val)) 4386 #define WRITE_WC40_RX3_ANARXCONTROLPCIr(_unit, _pc, _val) \ 4387 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080ea, (_val)) 4388 #define MODIFY_WC40_RX3_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \ 4389 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ea, (_val), (_mask)) 4390 4391 /* Rx analog status register (AFE rx_sts[15:0]) */ 4392 #define READ_WC40_RX3_ANARXASTATUSr(_unit, _pc, _val) \ 4393 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080eb, (_val)) 4394 #define WRITE_WC40_RX3_ANARXASTATUSr(_unit, _pc, _val) \ 4395 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080eb, (_val)) 4396 #define MODIFY_WC40_RX3_ANARXASTATUSr(_unit, _pc, _val, _mask) \ 4397 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080eb, (_val), (_mask)) 4398 4399 /* Rx reserved analog control register (AFE rx_ctrl[15:00], not applicable to XFICore) */ 4400 #define READ_WC40_RX3_ANARXACONTROL1r(_unit, _pc, _val) \ 4401 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080ec, (_val)) 4402 #define WRITE_WC40_RX3_ANARXACONTROL1r(_unit, _pc, _val) \ 4403 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080ec, (_val)) 4404 #define MODIFY_WC40_RX3_ANARXACONTROL1r(_unit, _pc, _val, _mask) \ 4405 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ec, (_val), (_mask)) 4406 4407 /* Rx reserved analog control register (AFE rx_ctrl[31:16], not applicable to XFICore) */ 4408 #define READ_WC40_RX3_ANARXACONTROL2r(_unit, _pc, _val) \ 4409 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080ed, (_val)) 4410 #define WRITE_WC40_RX3_ANARXACONTROL2r(_unit, _pc, _val) \ 4411 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080ed, (_val)) 4412 #define MODIFY_WC40_RX3_ANARXACONTROL2r(_unit, _pc, _val, _mask) \ 4413 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ed, (_val), (_mask)) 4414 4415 /* Rx reserved analog control register (AFE rx_ctrl[47:32], not applicable to XFICore) */ 4416 #define READ_WC40_RX3_ANARXACONTROL3r(_unit, _pc, _val) \ 4417 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080ee, (_val)) 4418 #define WRITE_WC40_RX3_ANARXACONTROL3r(_unit, _pc, _val) \ 4419 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080ee, (_val)) 4420 #define MODIFY_WC40_RX3_ANARXACONTROL3r(_unit, _pc, _val, _mask) \ 4421 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ee, (_val), (_mask)) 4422 4423 4424 4425 /**************************************************************************** 4426 * Warpcore_USER_RxB 4427 */ 4428 /* Rx lane status register */ 4429 #define READ_WC40_RXB_ANARXSTATUSr(_unit, _pc, _val) \ 4430 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080f0, (_val)) 4431 #define WRITE_WC40_RXB_ANARXSTATUSr(_unit, _pc, _val) \ 4432 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080f0, (_val)) 4433 #define MODIFY_WC40_RXB_ANARXSTATUSr(_unit, _pc, _val, _mask) \ 4434 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f0, (_val), (_mask)) 4435 4436 /* Rx lane control register */ 4437 #define READ_WC40_RXB_ANARXCONTROLr(_unit, _pc, _val) \ 4438 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080f1, (_val)) 4439 #define WRITE_WC40_RXB_ANARXCONTROLr(_unit, _pc, _val) \ 4440 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080f1, (_val)) 4441 #define MODIFY_WC40_RXB_ANARXCONTROLr(_unit, _pc, _val, _mask) \ 4442 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f1, (_val), (_mask)) 4443 4444 /* Rx Sigdet Control */ 4445 #define READ_WC40_RXB_ANARXSIGDETr(_unit, _pc, _val) \ 4446 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080f4, (_val)) 4447 #define WRITE_WC40_RXB_ANARXSIGDETr(_unit, _pc, _val) \ 4448 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080f4, (_val)) 4449 #define MODIFY_WC40_RXB_ANARXSIGDETr(_unit, _pc, _val, _mask) \ 4450 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f4, (_val), (_mask)) 4451 4452 /* Rx reserved analog control register */ 4453 #define READ_WC40_RXB_ANARXACONTROL4r(_unit, _pc, _val) \ 4454 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080f5, (_val)) 4455 #define WRITE_WC40_RXB_ANARXACONTROL4r(_unit, _pc, _val) \ 4456 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080f5, (_val)) 4457 #define MODIFY_WC40_RXB_ANARXACONTROL4r(_unit, _pc, _val, _mask) \ 4458 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f5, (_val), (_mask)) 4459 4460 /* Rx 1G Control2 register */ 4461 #define READ_WC40_RXB_ANARXCONTROL2_1Gr(_unit, _pc, _val) \ 4462 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080f6, (_val)) 4463 #define WRITE_WC40_RXB_ANARXCONTROL2_1Gr(_unit, _pc, _val) \ 4464 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080f6, (_val)) 4465 #define MODIFY_WC40_RXB_ANARXCONTROL2_1Gr(_unit, _pc, _val, _mask) \ 4466 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f6, (_val), (_mask)) 4467 4468 /* Rx lane control register */ 4469 #define READ_WC40_RXB_ANARXTESTr(_unit, _pc, _val) \ 4470 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080f8, (_val)) 4471 #define WRITE_WC40_RXB_ANARXTESTr(_unit, _pc, _val) \ 4472 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080f8, (_val)) 4473 #define MODIFY_WC40_RXB_ANARXTESTr(_unit, _pc, _val, _mask) \ 4474 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f8, (_val), (_mask)) 4475 4476 /* Rx 1G Control register */ 4477 #define READ_WC40_RXB_ANARXCONTROL1Gr(_unit, _pc, _val) \ 4478 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080f9, (_val)) 4479 #define WRITE_WC40_RXB_ANARXCONTROL1Gr(_unit, _pc, _val) \ 4480 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080f9, (_val)) 4481 #define MODIFY_WC40_RXB_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \ 4482 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f9, (_val), (_mask)) 4483 4484 /* Rx PCI Control register */ 4485 #define READ_WC40_RXB_ANARXCONTROLPCIr(_unit, _pc, _val) \ 4486 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080fa, (_val)) 4487 #define WRITE_WC40_RXB_ANARXCONTROLPCIr(_unit, _pc, _val) \ 4488 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080fa, (_val)) 4489 #define MODIFY_WC40_RXB_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \ 4490 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fa, (_val), (_mask)) 4491 4492 /* Rx analog status register (AFE rx_sts[15:0]) */ 4493 #define READ_WC40_RXB_ANARXASTATUSr(_unit, _pc, _val) \ 4494 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080fb, (_val)) 4495 #define WRITE_WC40_RXB_ANARXASTATUSr(_unit, _pc, _val) \ 4496 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080fb, (_val)) 4497 #define MODIFY_WC40_RXB_ANARXASTATUSr(_unit, _pc, _val, _mask) \ 4498 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fb, (_val), (_mask)) 4499 4500 /* Rx reserved analog control register (AFE rx_ctrl[15:00], not applicable to XFICore) */ 4501 #define READ_WC40_RXB_ANARXACONTROL1r(_unit, _pc, _val) \ 4502 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080fc, (_val)) 4503 #define WRITE_WC40_RXB_ANARXACONTROL1r(_unit, _pc, _val) \ 4504 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080fc, (_val)) 4505 #define MODIFY_WC40_RXB_ANARXACONTROL1r(_unit, _pc, _val, _mask) \ 4506 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fc, (_val), (_mask)) 4507 4508 /* Rx reserved analog control register (AFE rx_ctrl[31:16], not applicable to XFICore) */ 4509 #define READ_WC40_RXB_ANARXACONTROL2r(_unit, _pc, _val) \ 4510 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080fd, (_val)) 4511 #define WRITE_WC40_RXB_ANARXACONTROL2r(_unit, _pc, _val) \ 4512 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080fd, (_val)) 4513 #define MODIFY_WC40_RXB_ANARXACONTROL2r(_unit, _pc, _val, _mask) \ 4514 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fd, (_val), (_mask)) 4515 4516 /* Rx reserved analog control register (AFE rx_ctrl[47:32], not applicable to XFICore) */ 4517 #define READ_WC40_RXB_ANARXACONTROL3r(_unit, _pc, _val) \ 4518 WC40_REG_READ((_unit), (_pc), 0x00, 0x000080fe, (_val)) 4519 #define WRITE_WC40_RXB_ANARXACONTROL3r(_unit, _pc, _val) \ 4520 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000080fe, (_val)) 4521 #define MODIFY_WC40_RXB_ANARXACONTROL3r(_unit, _pc, _val, _mask) \ 4522 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fe, (_val), (_mask)) 4523 4524 4525 4526 /**************************************************************************** 4527 * Warpcore_USER_XgxsBlk2 4528 */ 4529 /* Receiver lane swap control register */ 4530 #define READ_WC40_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val) \ 4531 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008100, (_val)) 4532 #define WRITE_WC40_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val) \ 4533 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008100, (_val)) 4534 #define MODIFY_WC40_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val, _mask) \ 4535 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008100, (_val), (_mask)) 4536 4537 /* Transmit lane swap control register */ 4538 #define READ_WC40_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val) \ 4539 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008101, (_val)) 4540 #define WRITE_WC40_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val) \ 4541 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008101, (_val)) 4542 #define MODIFY_WC40_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val, _mask) \ 4543 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008101, (_val), (_mask)) 4544 4545 /* ||Q|| ordered set, lanes 0 & 1 register */ 4546 #define READ_WC40_XGXSBLK2_QSETLNS01r(_unit, _pc, _val) \ 4547 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008102, (_val)) 4548 #define WRITE_WC40_XGXSBLK2_QSETLNS01r(_unit, _pc, _val) \ 4549 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008102, (_val)) 4550 #define MODIFY_WC40_XGXSBLK2_QSETLNS01r(_unit, _pc, _val, _mask) \ 4551 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008102, (_val), (_mask)) 4552 4553 /* ||Q|| ordered set, lanes 2 & 3 register */ 4554 #define READ_WC40_XGXSBLK2_QSETLNS23r(_unit, _pc, _val) \ 4555 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008103, (_val)) 4556 #define WRITE_WC40_XGXSBLK2_QSETLNS23r(_unit, _pc, _val) \ 4557 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008103, (_val)) 4558 #define MODIFY_WC40_XGXSBLK2_QSETLNS23r(_unit, _pc, _val, _mask) \ 4559 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008103, (_val), (_mask)) 4560 4561 /* AN 10G resolution mode control register */ 4562 #define READ_WC40_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val) \ 4563 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008104, (_val)) 4564 #define WRITE_WC40_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val) \ 4565 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008104, (_val)) 4566 #define MODIFY_WC40_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val, _mask) \ 4567 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008104, (_val), (_mask)) 4568 4569 /* Independent Combo Control register */ 4570 #define READ_WC40_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val) \ 4571 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008105, (_val)) 4572 #define WRITE_WC40_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val) \ 4573 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008105, (_val)) 4574 #define MODIFY_WC40_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val, _mask) \ 4575 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008105, (_val), (_mask)) 4576 4577 /* Test mode lane select register */ 4578 #define READ_WC40_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val) \ 4579 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008106, (_val)) 4580 #define WRITE_WC40_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val) \ 4581 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008106, (_val)) 4582 #define MODIFY_WC40_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val, _mask) \ 4583 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008106, (_val), (_mask)) 4584 4585 /* Test mode monitor control register */ 4586 #define READ_WC40_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val) \ 4587 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008107, (_val)) 4588 #define WRITE_WC40_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val) \ 4589 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008107, (_val)) 4590 #define MODIFY_WC40_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val, _mask) \ 4591 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008107, (_val), (_mask)) 4592 4593 /* Test mode mux control register */ 4594 #define READ_WC40_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val) \ 4595 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008108, (_val)) 4596 #define WRITE_WC40_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val) \ 4597 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008108, (_val)) 4598 #define MODIFY_WC40_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val, _mask) \ 4599 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008108, (_val), (_mask)) 4600 4601 /* 10GBASE-CX4 signal detect timeout value */ 4602 #define READ_WC40_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val) \ 4603 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008109, (_val)) 4604 #define WRITE_WC40_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val) \ 4605 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008109, (_val)) 4606 #define MODIFY_WC40_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val, _mask) \ 4607 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008109, (_val), (_mask)) 4608 4609 /* Lane reset register */ 4610 #define READ_WC40_XGXSBLK2_LANERESETr(_unit, _pc, _val) \ 4611 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000810a, (_val)) 4612 #define WRITE_WC40_XGXSBLK2_LANERESETr(_unit, _pc, _val) \ 4613 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000810a, (_val)) 4614 #define MODIFY_WC40_XGXSBLK2_LANERESETr(_unit, _pc, _val, _mask) \ 4615 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810a, (_val), (_mask)) 4616 4617 /* XGXS Status 6 register */ 4618 #define READ_WC40_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _val) \ 4619 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000810b, (_val)) 4620 #define WRITE_WC40_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _val) \ 4621 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000810b, (_val)) 4622 #define MODIFY_WC40_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _val, _mask) \ 4623 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810b, (_val), (_mask)) 4624 4625 /* XFI Control register */ 4626 #define READ_WC40_XGXSBLK2_XFICONTROLr(_unit, _pc, _val) \ 4627 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000810c, (_val)) 4628 #define WRITE_WC40_XGXSBLK2_XFICONTROLr(_unit, _pc, _val) \ 4629 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000810c, (_val)) 4630 #define MODIFY_WC40_XGXSBLK2_XFICONTROLr(_unit, _pc, _val, _mask) \ 4631 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810c, (_val), (_mask)) 4632 4633 /* A Swap 66 control 1 register */ 4634 #define READ_WC40_XGXSBLK2_ASWAP66CONTROL1r(_unit, _pc, _val) \ 4635 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000810d, (_val)) 4636 #define WRITE_WC40_XGXSBLK2_ASWAP66CONTROL1r(_unit, _pc, _val) \ 4637 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000810d, (_val)) 4638 #define MODIFY_WC40_XGXSBLK2_ASWAP66CONTROL1r(_unit, _pc, _val, _mask) \ 4639 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810d, (_val), (_mask)) 4640 4641 /* A Swap 66 control 2 register */ 4642 #define READ_WC40_XGXSBLK2_ASWAP66CONTROL2r(_unit, _pc, _val) \ 4643 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000810e, (_val)) 4644 #define WRITE_WC40_XGXSBLK2_ASWAP66CONTROL2r(_unit, _pc, _val) \ 4645 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000810e, (_val)) 4646 #define MODIFY_WC40_XGXSBLK2_ASWAP66CONTROL2r(_unit, _pc, _val, _mask) \ 4647 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810e, (_val), (_mask)) 4648 4649 4650 4651 /**************************************************************************** 4652 * Warpcore_USER_XgxsBlk3 4653 */ 4654 /* In Band MDIO - local status register */ 4655 #define READ_WC40_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _val) \ 4656 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008110, (_val)) 4657 #define WRITE_WC40_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _val) \ 4658 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008110, (_val)) 4659 #define MODIFY_WC40_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _val, _mask) \ 4660 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008110, (_val), (_mask)) 4661 4662 /* In Band MDIO - local control 0 register */ 4663 #define READ_WC40_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _val) \ 4664 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008111, (_val)) 4665 #define WRITE_WC40_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _val) \ 4666 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008111, (_val)) 4667 #define MODIFY_WC40_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _val, _mask) \ 4668 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008111, (_val), (_mask)) 4669 4670 /* In Band MDIO - local control 1 register */ 4671 #define READ_WC40_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _val) \ 4672 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008112, (_val)) 4673 #define WRITE_WC40_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _val) \ 4674 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008112, (_val)) 4675 #define MODIFY_WC40_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _val, _mask) \ 4676 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008112, (_val), (_mask)) 4677 4678 /* In Band MDIO - remote write ln 0 & 3 register */ 4679 #define READ_WC40_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _val) \ 4680 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008113, (_val)) 4681 #define WRITE_WC40_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _val) \ 4682 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008113, (_val)) 4683 #define MODIFY_WC40_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _val, _mask) \ 4684 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008113, (_val), (_mask)) 4685 4686 /* In Band MDIO - remote write ln 1 & 2 register */ 4687 #define READ_WC40_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _val) \ 4688 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008114, (_val)) 4689 #define WRITE_WC40_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _val) \ 4690 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008114, (_val)) 4691 #define MODIFY_WC40_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _val, _mask) \ 4692 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008114, (_val), (_mask)) 4693 4694 /* In Band MDIO - remote read ln 1 & 2 register */ 4695 #define READ_WC40_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _val) \ 4696 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008115, (_val)) 4697 #define WRITE_WC40_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _val) \ 4698 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008115, (_val)) 4699 #define MODIFY_WC40_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _val, _mask) \ 4700 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008115, (_val), (_mask)) 4701 4702 /* In Band MDIO - remote read ln 0 & 3 register */ 4703 #define READ_WC40_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _val) \ 4704 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008116, (_val)) 4705 #define WRITE_WC40_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _val) \ 4706 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008116, (_val)) 4707 #define MODIFY_WC40_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _val, _mask) \ 4708 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008116, (_val), (_mask)) 4709 4710 /* In Band MDIO - status register */ 4711 #define READ_WC40_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _val) \ 4712 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008117, (_val)) 4713 #define WRITE_WC40_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _val) \ 4714 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008117, (_val)) 4715 #define MODIFY_WC40_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _val, _mask) \ 4716 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008117, (_val), (_mask)) 4717 4718 /* In Band MDIO - local IAC register */ 4719 #define READ_WC40_XGXSBLK3_LOCALIACr(_unit, _pc, _val) \ 4720 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008118, (_val)) 4721 #define WRITE_WC40_XGXSBLK3_LOCALIACr(_unit, _pc, _val) \ 4722 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008118, (_val)) 4723 #define MODIFY_WC40_XGXSBLK3_LOCALIACr(_unit, _pc, _val, _mask) \ 4724 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008118, (_val), (_mask)) 4725 4726 /* In Band MDIO - remote IAC register */ 4727 #define READ_WC40_XGXSBLK3_REMOTEIACNr(_unit, _pc, _val) \ 4728 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008119, (_val)) 4729 #define WRITE_WC40_XGXSBLK3_REMOTEIACNr(_unit, _pc, _val) \ 4730 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008119, (_val)) 4731 #define MODIFY_WC40_XGXSBLK3_REMOTEIACNr(_unit, _pc, _val, _mask) \ 4732 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008119, (_val), (_mask)) 4733 4734 4735 4736 /**************************************************************************** 4737 * Warpcore_USER_XgxsBlk4 4738 */ 4739 /* Miscellaneous Rx status register */ 4740 #define READ_WC40_XGXSBLK4_MISCRXSTATUSr(_unit, _pc, _val) \ 4741 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008120, (_val)) 4742 #define WRITE_WC40_XGXSBLK4_MISCRXSTATUSr(_unit, _pc, _val) \ 4743 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008120, (_val)) 4744 #define MODIFY_WC40_XGXSBLK4_MISCRXSTATUSr(_unit, _pc, _val, _mask) \ 4745 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008120, (_val), (_mask)) 4746 4747 /* XGXS status register */ 4748 #define READ_WC40_XGXSBLK4_XGXSSTATUS0r(_unit, _pc, _val) \ 4749 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008121, (_val)) 4750 #define WRITE_WC40_XGXSBLK4_XGXSSTATUS0r(_unit, _pc, _val) \ 4751 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008121, (_val)) 4752 #define MODIFY_WC40_XGXSBLK4_XGXSSTATUS0r(_unit, _pc, _val, _mask) \ 4753 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008121, (_val), (_mask)) 4754 4755 /* XGXS status 1 register */ 4756 #define READ_WC40_XGXSBLK4_XGXSSTATUS1r(_unit, _pc, _val) \ 4757 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008122, (_val)) 4758 #define WRITE_WC40_XGXSBLK4_XGXSSTATUS1r(_unit, _pc, _val) \ 4759 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008122, (_val)) 4760 #define MODIFY_WC40_XGXSBLK4_XGXSSTATUS1r(_unit, _pc, _val, _mask) \ 4761 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008122, (_val), (_mask)) 4762 4763 /* XGXS status 2 register */ 4764 #define READ_WC40_XGXSBLK4_XGXSSTATUS2r(_unit, _pc, _val) \ 4765 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008123, (_val)) 4766 #define WRITE_WC40_XGXSBLK4_XGXSSTATUS2r(_unit, _pc, _val) \ 4767 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008123, (_val)) 4768 #define MODIFY_WC40_XGXSBLK4_XGXSSTATUS2r(_unit, _pc, _val, _mask) \ 4769 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008123, (_val), (_mask)) 4770 4771 /* 1000X status 1 register */ 4772 #define READ_WC40_XGXSBLK4_STATUS1000X1r(_unit, _pc, _val) \ 4773 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008124, (_val)) 4774 #define WRITE_WC40_XGXSBLK4_STATUS1000X1r(_unit, _pc, _val) \ 4775 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008124, (_val)) 4776 #define MODIFY_WC40_XGXSBLK4_STATUS1000X1r(_unit, _pc, _val, _mask) \ 4777 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008124, (_val), (_mask)) 4778 4779 /* 1000X status 2 register */ 4780 #define READ_WC40_XGXSBLK4_STATUS1000X2r(_unit, _pc, _val) \ 4781 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008125, (_val)) 4782 #define WRITE_WC40_XGXSBLK4_STATUS1000X2r(_unit, _pc, _val) \ 4783 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008125, (_val)) 4784 #define MODIFY_WC40_XGXSBLK4_STATUS1000X2r(_unit, _pc, _val, _mask) \ 4785 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008125, (_val), (_mask)) 4786 4787 /* 1000X status 3 register */ 4788 #define READ_WC40_XGXSBLK4_STATUS1000X3r(_unit, _pc, _val) \ 4789 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008126, (_val)) 4790 #define WRITE_WC40_XGXSBLK4_STATUS1000X3r(_unit, _pc, _val) \ 4791 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008126, (_val)) 4792 #define MODIFY_WC40_XGXSBLK4_STATUS1000X3r(_unit, _pc, _val, _mask) \ 4793 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008126, (_val), (_mask)) 4794 4795 /* Test port out bits 15:0, tpout[15:0] */ 4796 #define READ_WC40_XGXSBLK4_TPOUT_1r(_unit, _pc, _val) \ 4797 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008127, (_val)) 4798 #define WRITE_WC40_XGXSBLK4_TPOUT_1r(_unit, _pc, _val) \ 4799 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008127, (_val)) 4800 #define MODIFY_WC40_XGXSBLK4_TPOUT_1r(_unit, _pc, _val, _mask) \ 4801 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008127, (_val), (_mask)) 4802 4803 /* Test port out bits 23:8, tpout[23:8] */ 4804 #define READ_WC40_XGXSBLK4_TPOUT_2r(_unit, _pc, _val) \ 4805 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008128, (_val)) 4806 #define WRITE_WC40_XGXSBLK4_TPOUT_2r(_unit, _pc, _val) \ 4807 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008128, (_val)) 4808 #define MODIFY_WC40_XGXSBLK4_TPOUT_2r(_unit, _pc, _val, _mask) \ 4809 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008128, (_val), (_mask)) 4810 4811 /* XGXS status 3 register */ 4812 #define READ_WC40_XGXSBLK4_XGXSSTATUS3r(_unit, _pc, _val) \ 4813 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008129, (_val)) 4814 #define WRITE_WC40_XGXSBLK4_XGXSSTATUS3r(_unit, _pc, _val) \ 4815 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008129, (_val)) 4816 #define MODIFY_WC40_XGXSBLK4_XGXSSTATUS3r(_unit, _pc, _val, _mask) \ 4817 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008129, (_val), (_mask)) 4818 4819 /* 2500X status register */ 4820 #define READ_WC40_XGXSBLK4_X2500STATUS1r(_unit, _pc, _val) \ 4821 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000812a, (_val)) 4822 #define WRITE_WC40_XGXSBLK4_X2500STATUS1r(_unit, _pc, _val) \ 4823 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000812a, (_val)) 4824 #define MODIFY_WC40_XGXSBLK4_X2500STATUS1r(_unit, _pc, _val, _mask) \ 4825 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812a, (_val), (_mask)) 4826 4827 /* CL73 AN status 1 register */ 4828 #define READ_WC40_XGXSBLK4_TOPANSTATUS1r(_unit, _pc, _val) \ 4829 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000812b, (_val)) 4830 #define WRITE_WC40_XGXSBLK4_TOPANSTATUS1r(_unit, _pc, _val) \ 4831 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000812b, (_val)) 4832 #define MODIFY_WC40_XGXSBLK4_TOPANSTATUS1r(_unit, _pc, _val, _mask) \ 4833 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812b, (_val), (_mask)) 4834 4835 /* AN link partner user page 1 */ 4836 #define READ_WC40_XGXSBLK4_LP_UP1r(_unit, _pc, _val) \ 4837 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000812c, (_val)) 4838 #define WRITE_WC40_XGXSBLK4_LP_UP1r(_unit, _pc, _val) \ 4839 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000812c, (_val)) 4840 #define MODIFY_WC40_XGXSBLK4_LP_UP1r(_unit, _pc, _val, _mask) \ 4841 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812c, (_val), (_mask)) 4842 4843 /* AN link partner user page 2 */ 4844 #define READ_WC40_XGXSBLK4_LP_UP2r(_unit, _pc, _val) \ 4845 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000812d, (_val)) 4846 #define WRITE_WC40_XGXSBLK4_LP_UP2r(_unit, _pc, _val) \ 4847 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000812d, (_val)) 4848 #define MODIFY_WC40_XGXSBLK4_LP_UP2r(_unit, _pc, _val, _mask) \ 4849 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812d, (_val), (_mask)) 4850 4851 /* AN link partner user page 3 */ 4852 #define READ_WC40_XGXSBLK4_LP_UP3r(_unit, _pc, _val) \ 4853 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000812e, (_val)) 4854 #define WRITE_WC40_XGXSBLK4_LP_UP3r(_unit, _pc, _val) \ 4855 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000812e, (_val)) 4856 #define MODIFY_WC40_XGXSBLK4_LP_UP3r(_unit, _pc, _val, _mask) \ 4857 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812e, (_val), (_mask)) 4858 4859 4860 4861 /**************************************************************************** 4862 * Warpcore_USER_XgxsBlk5 4863 */ 4864 /* 10G parallel detect status register */ 4865 #define READ_WC40_XGXSBLK5_PARDET10GSTATUSr(_unit, _pc, _val) \ 4866 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008130, (_val)) 4867 #define WRITE_WC40_XGXSBLK5_PARDET10GSTATUSr(_unit, _pc, _val) \ 4868 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008130, (_val)) 4869 #define MODIFY_WC40_XGXSBLK5_PARDET10GSTATUSr(_unit, _pc, _val, _mask) \ 4870 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008130, (_val), (_mask)) 4871 4872 /* 10G parallel detect control register */ 4873 #define READ_WC40_XGXSBLK5_PARDET10GCONTROLr(_unit, _pc, _val) \ 4874 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008131, (_val)) 4875 #define WRITE_WC40_XGXSBLK5_PARDET10GCONTROLr(_unit, _pc, _val) \ 4876 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008131, (_val)) 4877 #define MODIFY_WC40_XGXSBLK5_PARDET10GCONTROLr(_unit, _pc, _val, _mask) \ 4878 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008131, (_val), (_mask)) 4879 4880 /* 10G parallel detect signal detect register */ 4881 #define READ_WC40_XGXSBLK5_PARDET10GSIGDETr(_unit, _pc, _val) \ 4882 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008132, (_val)) 4883 #define WRITE_WC40_XGXSBLK5_PARDET10GSIGDETr(_unit, _pc, _val) \ 4884 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008132, (_val)) 4885 #define MODIFY_WC40_XGXSBLK5_PARDET10GSIGDETr(_unit, _pc, _val, _mask) \ 4886 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008132, (_val), (_mask)) 4887 4888 /* 10G parallel detect link register */ 4889 #define READ_WC40_XGXSBLK5_PARDET10GLINKr(_unit, _pc, _val) \ 4890 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008133, (_val)) 4891 #define WRITE_WC40_XGXSBLK5_PARDET10GLINKr(_unit, _pc, _val) \ 4892 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008133, (_val)) 4893 #define MODIFY_WC40_XGXSBLK5_PARDET10GLINKr(_unit, _pc, _val, _mask) \ 4894 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008133, (_val), (_mask)) 4895 4896 /* 10G parallel detect lost link register */ 4897 #define READ_WC40_XGXSBLK5_PARDET10GLOSTLINKr(_unit, _pc, _val) \ 4898 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008134, (_val)) 4899 #define WRITE_WC40_XGXSBLK5_PARDET10GLOSTLINKr(_unit, _pc, _val) \ 4900 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008134, (_val)) 4901 #define MODIFY_WC40_XGXSBLK5_PARDET10GLOSTLINKr(_unit, _pc, _val, _mask) \ 4902 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008134, (_val), (_mask)) 4903 4904 /* Clause 73 auto-negotiation control register 1 */ 4905 #define READ_WC40_XGXSBLK5_CL73CONTROL1r(_unit, _pc, _val) \ 4906 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008135, (_val)) 4907 #define WRITE_WC40_XGXSBLK5_CL73CONTROL1r(_unit, _pc, _val) \ 4908 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008135, (_val)) 4909 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL1r(_unit, _pc, _val, _mask) \ 4910 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008135, (_val), (_mask)) 4911 4912 /* Clause 73 auto-negotiation control register 2 */ 4913 #define READ_WC40_XGXSBLK5_CL73CONTROL2r(_unit, _pc, _val) \ 4914 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008136, (_val)) 4915 #define WRITE_WC40_XGXSBLK5_CL73CONTROL2r(_unit, _pc, _val) \ 4916 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008136, (_val)) 4917 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL2r(_unit, _pc, _val, _mask) \ 4918 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008136, (_val), (_mask)) 4919 4920 /* Clause 73 auto-negotiation control register 3 */ 4921 #define READ_WC40_XGXSBLK5_CL73CONTROL3r(_unit, _pc, _val) \ 4922 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008137, (_val)) 4923 #define WRITE_WC40_XGXSBLK5_CL73CONTROL3r(_unit, _pc, _val) \ 4924 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008137, (_val)) 4925 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL3r(_unit, _pc, _val, _mask) \ 4926 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008137, (_val), (_mask)) 4927 4928 /* Clause 73 auto-negotiation control register 4 */ 4929 #define READ_WC40_XGXSBLK5_CL73CONTROL4r(_unit, _pc, _val) \ 4930 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008138, (_val)) 4931 #define WRITE_WC40_XGXSBLK5_CL73CONTROL4r(_unit, _pc, _val) \ 4932 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008138, (_val)) 4933 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL4r(_unit, _pc, _val, _mask) \ 4934 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008138, (_val), (_mask)) 4935 4936 /* Clause 73 auto-negotiation control register 5 */ 4937 #define READ_WC40_XGXSBLK5_CL73CONTROL5r(_unit, _pc, _val) \ 4938 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008139, (_val)) 4939 #define WRITE_WC40_XGXSBLK5_CL73CONTROL5r(_unit, _pc, _val) \ 4940 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008139, (_val)) 4941 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL5r(_unit, _pc, _val, _mask) \ 4942 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008139, (_val), (_mask)) 4943 4944 /* Clause 73 auto-negotiation control register 6 */ 4945 #define READ_WC40_XGXSBLK5_CL73CONTROL6r(_unit, _pc, _val) \ 4946 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000813a, (_val)) 4947 #define WRITE_WC40_XGXSBLK5_CL73CONTROL6r(_unit, _pc, _val) \ 4948 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000813a, (_val)) 4949 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL6r(_unit, _pc, _val, _mask) \ 4950 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813a, (_val), (_mask)) 4951 4952 /* Clause 73 auto-negotiation DME Timers Register */ 4953 #define READ_WC40_XGXSBLK5_CL73DMETMRSr(_unit, _pc, _val) \ 4954 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000813b, (_val)) 4955 #define WRITE_WC40_XGXSBLK5_CL73DMETMRSr(_unit, _pc, _val) \ 4956 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000813b, (_val)) 4957 #define MODIFY_WC40_XGXSBLK5_CL73DMETMRSr(_unit, _pc, _val, _mask) \ 4958 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813b, (_val), (_mask)) 4959 4960 /* XGXS Status 4 Register */ 4961 #define READ_WC40_XGXSBLK5_XGXSSTATUS4r(_unit, _pc, _val) \ 4962 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000813c, (_val)) 4963 #define WRITE_WC40_XGXSBLK5_XGXSSTATUS4r(_unit, _pc, _val) \ 4964 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000813c, (_val)) 4965 #define MODIFY_WC40_XGXSBLK5_XGXSSTATUS4r(_unit, _pc, _val, _mask) \ 4966 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813c, (_val), (_mask)) 4967 4968 /* XGXS Status 5 Register */ 4969 #define READ_WC40_XGXSBLK5_XGXSSTATUS5r(_unit, _pc, _val) \ 4970 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000813d, (_val)) 4971 #define WRITE_WC40_XGXSBLK5_XGXSSTATUS5r(_unit, _pc, _val) \ 4972 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000813d, (_val)) 4973 #define MODIFY_WC40_XGXSBLK5_XGXSSTATUS5r(_unit, _pc, _val, _mask) \ 4974 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813d, (_val), (_mask)) 4975 4976 /* 10G parallel detect control 2 register */ 4977 #define READ_WC40_XGXSBLK5_PARDET10GCONTROL2r(_unit, _pc, _val) \ 4978 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000813e, (_val)) 4979 #define WRITE_WC40_XGXSBLK5_PARDET10GCONTROL2r(_unit, _pc, _val) \ 4980 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000813e, (_val)) 4981 #define MODIFY_WC40_XGXSBLK5_PARDET10GCONTROL2r(_unit, _pc, _val, _mask) \ 4982 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813e, (_val), (_mask)) 4983 4984 4985 4986 /**************************************************************************** 4987 * Warpcore_USER_XgxsBlk6 4988 */ 4989 /* Dual-XGXS Control1 register */ 4990 #define READ_WC40_XGXSBLK6_XGXSX2CONTROL1r(_unit, _pc, _val) \ 4991 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008140, (_val)) 4992 #define WRITE_WC40_XGXSBLK6_XGXSX2CONTROL1r(_unit, _pc, _val) \ 4993 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008140, (_val)) 4994 #define MODIFY_WC40_XGXSBLK6_XGXSX2CONTROL1r(_unit, _pc, _val, _mask) \ 4995 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008140, (_val), (_mask)) 4996 4997 /* Dual-XGXS Control2 register */ 4998 #define READ_WC40_XGXSBLK6_XGXSX2CONTROL2r(_unit, _pc, _val) \ 4999 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008141, (_val)) 5000 #define WRITE_WC40_XGXSBLK6_XGXSX2CONTROL2r(_unit, _pc, _val) \ 5001 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008141, (_val)) 5002 #define MODIFY_WC40_XGXSBLK6_XGXSX2CONTROL2r(_unit, _pc, _val, _mask) \ 5003 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008141, (_val), (_mask)) 5004 5005 /* Dual-XGXS Control3 register */ 5006 #define READ_WC40_XGXSBLK6_XGXSX2CONTROL3r(_unit, _pc, _val) \ 5007 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008142, (_val)) 5008 #define WRITE_WC40_XGXSBLK6_XGXSX2CONTROL3r(_unit, _pc, _val) \ 5009 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008142, (_val)) 5010 #define MODIFY_WC40_XGXSBLK6_XGXSX2CONTROL3r(_unit, _pc, _val, _mask) \ 5011 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008142, (_val), (_mask)) 5012 5013 /* Dual-XGXS Status1 register */ 5014 #define READ_WC40_XGXSBLK6_XGXSX2STATUS1r(_unit, _pc, _val) \ 5015 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008143, (_val)) 5016 #define WRITE_WC40_XGXSBLK6_XGXSX2STATUS1r(_unit, _pc, _val) \ 5017 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008143, (_val)) 5018 #define MODIFY_WC40_XGXSBLK6_XGXSX2STATUS1r(_unit, _pc, _val, _mask) \ 5019 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008143, (_val), (_mask)) 5020 5021 /* Dual-XGXS Test1 register */ 5022 #define READ_WC40_XGXSBLK6_XGXSX2TEST1r(_unit, _pc, _val) \ 5023 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008146, (_val)) 5024 #define WRITE_WC40_XGXSBLK6_XGXSX2TEST1r(_unit, _pc, _val) \ 5025 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008146, (_val)) 5026 #define MODIFY_WC40_XGXSBLK6_XGXSX2TEST1r(_unit, _pc, _val, _mask) \ 5027 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008146, (_val), (_mask)) 5028 5029 /* BPM Control register */ 5030 #define READ_WC40_XGXSBLK6_BPMCONTROLr(_unit, _pc, _val) \ 5031 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008147, (_val)) 5032 #define WRITE_WC40_XGXSBLK6_BPMCONTROLr(_unit, _pc, _val) \ 5033 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008147, (_val)) 5034 #define MODIFY_WC40_XGXSBLK6_BPMCONTROLr(_unit, _pc, _val, _mask) \ 5035 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008147, (_val), (_mask)) 5036 5037 /* BPM Status register */ 5038 #define READ_WC40_XGXSBLK6_BPMSTATUSr(_unit, _pc, _val) \ 5039 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008148, (_val)) 5040 #define WRITE_WC40_XGXSBLK6_BPMSTATUSr(_unit, _pc, _val) \ 5041 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008148, (_val)) 5042 #define MODIFY_WC40_XGXSBLK6_BPMSTATUSr(_unit, _pc, _val, _mask) \ 5043 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008148, (_val), (_mask)) 5044 5045 /* BPM 10G Timer register */ 5046 #define READ_WC40_XGXSBLK6_BPM10GTIMERr(_unit, _pc, _val) \ 5047 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008149, (_val)) 5048 #define WRITE_WC40_XGXSBLK6_BPM10GTIMERr(_unit, _pc, _val) \ 5049 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008149, (_val)) 5050 #define MODIFY_WC40_XGXSBLK6_BPM10GTIMERr(_unit, _pc, _val, _mask) \ 5051 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008149, (_val), (_mask)) 5052 5053 /* BPM 1G Timer register */ 5054 #define READ_WC40_XGXSBLK6_BPM1GTIMERr(_unit, _pc, _val) \ 5055 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000814a, (_val)) 5056 #define WRITE_WC40_XGXSBLK6_BPM1GTIMERr(_unit, _pc, _val) \ 5057 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000814a, (_val)) 5058 #define MODIFY_WC40_XGXSBLK6_BPM1GTIMERr(_unit, _pc, _val, _mask) \ 5059 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000814a, (_val), (_mask)) 5060 5061 /* BPM Tx Disable Timer register */ 5062 #define READ_WC40_XGXSBLK6_BPMTXDISTIMERr(_unit, _pc, _val) \ 5063 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000814b, (_val)) 5064 #define WRITE_WC40_XGXSBLK6_BPMTXDISTIMERr(_unit, _pc, _val) \ 5065 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000814b, (_val)) 5066 #define MODIFY_WC40_XGXSBLK6_BPMTXDISTIMERr(_unit, _pc, _val, _mask) \ 5067 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000814b, (_val), (_mask)) 5068 5069 /* Parallel Detect IND Sig Det */ 5070 #define READ_WC40_XGXSBLK6_PARDETINDSIGDETr(_unit, _pc, _val) \ 5071 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000814c, (_val)) 5072 #define WRITE_WC40_XGXSBLK6_PARDETINDSIGDETr(_unit, _pc, _val) \ 5073 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000814c, (_val)) 5074 #define MODIFY_WC40_XGXSBLK6_PARDETINDSIGDETr(_unit, _pc, _val, _mask) \ 5075 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000814c, (_val), (_mask)) 5076 5077 /* Parallel Detect IND Link */ 5078 #define READ_WC40_XGXSBLK6_PARDETINDLINKr(_unit, _pc, _val) \ 5079 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000814d, (_val)) 5080 #define WRITE_WC40_XGXSBLK6_PARDETINDLINKr(_unit, _pc, _val) \ 5081 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000814d, (_val)) 5082 #define MODIFY_WC40_XGXSBLK6_PARDETINDLINKr(_unit, _pc, _val, _mask) \ 5083 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000814d, (_val), (_mask)) 5084 5085 /* Parallel Detect IND Lost Link */ 5086 #define READ_WC40_XGXSBLK6_PARDETINDLOSTLINKr(_unit, _pc, _val) \ 5087 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000814e, (_val)) 5088 #define WRITE_WC40_XGXSBLK6_PARDETINDLOSTLINKr(_unit, _pc, _val) \ 5089 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000814e, (_val)) 5090 #define MODIFY_WC40_XGXSBLK6_PARDETINDLOSTLINKr(_unit, _pc, _val, _mask) \ 5091 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000814e, (_val), (_mask)) 5092 5093 5094 5095 /**************************************************************************** 5096 * Warpcore_USER_XgxsBlk7 5097 */ 5098 /* Cl48 PCS EEE Control register */ 5099 #define READ_WC40_XGXSBLK7_EEECONTROLr(_unit, _pc, _val) \ 5100 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008150, (_val)) 5101 #define WRITE_WC40_XGXSBLK7_EEECONTROLr(_unit, _pc, _val) \ 5102 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008150, (_val)) 5103 #define MODIFY_WC40_XGXSBLK7_EEECONTROLr(_unit, _pc, _val, _mask) \ 5104 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008150, (_val), (_mask)) 5105 5106 /* Cl48 PCS EEE status regsiter */ 5107 #define READ_WC40_XGXSBLK7_EEESTATUSr(_unit, _pc, _val) \ 5108 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008151, (_val)) 5109 #define WRITE_WC40_XGXSBLK7_EEESTATUSr(_unit, _pc, _val) \ 5110 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008151, (_val)) 5111 #define MODIFY_WC40_XGXSBLK7_EEESTATUSr(_unit, _pc, _val, _mask) \ 5112 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008151, (_val), (_mask)) 5113 5114 /* XGMII Low power Idle chracter register */ 5115 #define READ_WC40_XGXSBLK7_XGMIILPIr(_unit, _pc, _val) \ 5116 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008152, (_val)) 5117 #define WRITE_WC40_XGXSBLK7_XGMIILPIr(_unit, _pc, _val) \ 5118 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008152, (_val)) 5119 #define MODIFY_WC40_XGXSBLK7_XGMIILPIr(_unit, _pc, _val, _mask) \ 5120 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008152, (_val), (_mask)) 5121 5122 /* LPI character for lanes1-3 at Rx xgmii interface */ 5123 #define READ_WC40_XGXSBLK7_LPILANE13r(_unit, _pc, _val) \ 5124 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008153, (_val)) 5125 #define WRITE_WC40_XGXSBLK7_LPILANE13r(_unit, _pc, _val) \ 5126 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008153, (_val)) 5127 #define MODIFY_WC40_XGXSBLK7_LPILANE13r(_unit, _pc, _val, _mask) \ 5128 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008153, (_val), (_mask)) 5129 5130 /* Lane1 character for reserved Q order set */ 5131 #define READ_WC40_XGXSBLK7_QRSVD1r(_unit, _pc, _val) \ 5132 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008154, (_val)) 5133 #define WRITE_WC40_XGXSBLK7_QRSVD1r(_unit, _pc, _val) \ 5134 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008154, (_val)) 5135 #define MODIFY_WC40_XGXSBLK7_QRSVD1r(_unit, _pc, _val, _mask) \ 5136 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008154, (_val), (_mask)) 5137 5138 /* Lane2 and 3 characters for reserved Q order set */ 5139 #define READ_WC40_XGXSBLK7_QRSVD23r(_unit, _pc, _val) \ 5140 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008155, (_val)) 5141 #define WRITE_WC40_XGXSBLK7_QRSVD23r(_unit, _pc, _val) \ 5142 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008155, (_val)) 5143 #define MODIFY_WC40_XGXSBLK7_QRSVD23r(_unit, _pc, _val, _mask) \ 5144 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008155, (_val), (_mask)) 5145 5146 /* Reserved Q order set swap control register */ 5147 #define READ_WC40_XGXSBLK7_QRSVDSWAPr(_unit, _pc, _val) \ 5148 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008156, (_val)) 5149 #define WRITE_WC40_XGXSBLK7_QRSVDSWAPr(_unit, _pc, _val) \ 5150 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008156, (_val)) 5151 #define MODIFY_WC40_XGXSBLK7_QRSVDSWAPr(_unit, _pc, _val, _mask) \ 5152 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008156, (_val), (_mask)) 5153 5154 /* Reserved Q order set status regsiter */ 5155 #define READ_WC40_XGXSBLK7_QRSVDSTATUSr(_unit, _pc, _val) \ 5156 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008157, (_val)) 5157 #define WRITE_WC40_XGXSBLK7_QRSVDSTATUSr(_unit, _pc, _val) \ 5158 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008157, (_val)) 5159 #define MODIFY_WC40_XGXSBLK7_QRSVDSTATUSr(_unit, _pc, _val, _mask) \ 5160 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008157, (_val), (_mask)) 5161 5162 /* Cl48 Tx lpi fsm status register */ 5163 #define READ_WC40_XGXSBLK7_CL48_TX_LPI_SMr(_unit, _pc, _val) \ 5164 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008158, (_val)) 5165 #define WRITE_WC40_XGXSBLK7_CL48_TX_LPI_SMr(_unit, _pc, _val) \ 5166 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008158, (_val)) 5167 #define MODIFY_WC40_XGXSBLK7_CL48_TX_LPI_SMr(_unit, _pc, _val, _mask) \ 5168 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008158, (_val), (_mask)) 5169 5170 /* Cl48 Rx lpi fsm status register */ 5171 #define READ_WC40_XGXSBLK7_CL48_RX_LPI_SMr(_unit, _pc, _val) \ 5172 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008159, (_val)) 5173 #define WRITE_WC40_XGXSBLK7_CL48_RX_LPI_SMr(_unit, _pc, _val) \ 5174 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008159, (_val)) 5175 #define MODIFY_WC40_XGXSBLK7_CL48_RX_LPI_SMr(_unit, _pc, _val, _mask) \ 5176 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008159, (_val), (_mask)) 5177 5178 /* 10G FIFO control register */ 5179 #define READ_WC40_XGXSBLK7_FIFO_CTRLr(_unit, _pc, _val) \ 5180 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000815d, (_val)) 5181 #define WRITE_WC40_XGXSBLK7_FIFO_CTRLr(_unit, _pc, _val) \ 5182 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000815d, (_val)) 5183 #define MODIFY_WC40_XGXSBLK7_FIFO_CTRLr(_unit, _pc, _val, _mask) \ 5184 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000815d, (_val), (_mask)) 5185 5186 /* 10G FIFO status register */ 5187 #define READ_WC40_XGXSBLK7_FIFO_STATUSr(_unit, _pc, _val) \ 5188 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000815e, (_val)) 5189 #define WRITE_WC40_XGXSBLK7_FIFO_STATUSr(_unit, _pc, _val) \ 5190 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000815e, (_val)) 5191 #define MODIFY_WC40_XGXSBLK7_FIFO_STATUSr(_unit, _pc, _val, _mask) \ 5192 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000815e, (_val), (_mask)) 5193 5194 5195 5196 /**************************************************************************** 5197 * Warpcore_USER_XgxsBlk8 5198 */ 5199 /* CL73 Control 7 Register */ 5200 #define READ_WC40_XGXSBLK8_CL73CONTROL7r(_unit, _pc, _val) \ 5201 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008160, (_val)) 5202 #define WRITE_WC40_XGXSBLK8_CL73CONTROL7r(_unit, _pc, _val) \ 5203 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008160, (_val)) 5204 #define MODIFY_WC40_XGXSBLK8_CL73CONTROL7r(_unit, _pc, _val, _mask) \ 5205 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008160, (_val), (_mask)) 5206 5207 /* CL73 Control 8 Register */ 5208 #define READ_WC40_XGXSBLK8_CL73CONTROL8r(_unit, _pc, _val) \ 5209 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008161, (_val)) 5210 #define WRITE_WC40_XGXSBLK8_CL73CONTROL8r(_unit, _pc, _val) \ 5211 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008161, (_val)) 5212 #define MODIFY_WC40_XGXSBLK8_CL73CONTROL8r(_unit, _pc, _val, _mask) \ 5213 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008161, (_val), (_mask)) 5214 5215 /* CL73 Control 9 Register */ 5216 #define READ_WC40_XGXSBLK8_CL73CONTROL9r(_unit, _pc, _val) \ 5217 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008162, (_val)) 5218 #define WRITE_WC40_XGXSBLK8_CL73CONTROL9r(_unit, _pc, _val) \ 5219 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008162, (_val)) 5220 #define MODIFY_WC40_XGXSBLK8_CL73CONTROL9r(_unit, _pc, _val, _mask) \ 5221 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008162, (_val), (_mask)) 5222 5223 /* CL73 Control 10 Register */ 5224 #define READ_WC40_XGXSBLK8_CL73CONTROL10r(_unit, _pc, _val) \ 5225 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008163, (_val)) 5226 #define WRITE_WC40_XGXSBLK8_CL73CONTROL10r(_unit, _pc, _val) \ 5227 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008163, (_val)) 5228 #define MODIFY_WC40_XGXSBLK8_CL73CONTROL10r(_unit, _pc, _val, _mask) \ 5229 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008163, (_val), (_mask)) 5230 5231 /* TX Phase interpolator Control 1 Register */ 5232 #define READ_WC40_XGXSBLK8_TX_PI_CONTROL1r(_unit, _pc, _val) \ 5233 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008164, (_val)) 5234 #define WRITE_WC40_XGXSBLK8_TX_PI_CONTROL1r(_unit, _pc, _val) \ 5235 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008164, (_val)) 5236 #define MODIFY_WC40_XGXSBLK8_TX_PI_CONTROL1r(_unit, _pc, _val, _mask) \ 5237 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008164, (_val), (_mask)) 5238 5239 /* TX Phase interpolator Control 2 Register */ 5240 #define READ_WC40_XGXSBLK8_TX_PI_CONTROL2r(_unit, _pc, _val) \ 5241 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008165, (_val)) 5242 #define WRITE_WC40_XGXSBLK8_TX_PI_CONTROL2r(_unit, _pc, _val) \ 5243 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008165, (_val)) 5244 #define MODIFY_WC40_XGXSBLK8_TX_PI_CONTROL2r(_unit, _pc, _val, _mask) \ 5245 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008165, (_val), (_mask)) 5246 5247 /* TX Phase interpolator Control 3 Register */ 5248 #define READ_WC40_XGXSBLK8_TX_PI_CONTROL3r(_unit, _pc, _val) \ 5249 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008166, (_val)) 5250 #define WRITE_WC40_XGXSBLK8_TX_PI_CONTROL3r(_unit, _pc, _val) \ 5251 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008166, (_val)) 5252 #define MODIFY_WC40_XGXSBLK8_TX_PI_CONTROL3r(_unit, _pc, _val, _mask) \ 5253 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008166, (_val), (_mask)) 5254 5255 /* TX Phase interpolator Status 1 Register */ 5256 #define READ_WC40_XGXSBLK8_TX_PI_STATUS1r(_unit, _pc, _val) \ 5257 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008167, (_val)) 5258 #define WRITE_WC40_XGXSBLK8_TX_PI_STATUS1r(_unit, _pc, _val) \ 5259 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008167, (_val)) 5260 #define MODIFY_WC40_XGXSBLK8_TX_PI_STATUS1r(_unit, _pc, _val, _mask) \ 5261 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008167, (_val), (_mask)) 5262 5263 /* TX Phase interpolator Status 2 Register */ 5264 #define READ_WC40_XGXSBLK8_TX_PI_STATUS2r(_unit, _pc, _val) \ 5265 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008168, (_val)) 5266 #define WRITE_WC40_XGXSBLK8_TX_PI_STATUS2r(_unit, _pc, _val) \ 5267 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008168, (_val)) 5268 #define MODIFY_WC40_XGXSBLK8_TX_PI_STATUS2r(_unit, _pc, _val, _mask) \ 5269 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008168, (_val), (_mask)) 5270 5271 /* TX Lane Swap Control 1 Register */ 5272 #define READ_WC40_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _val) \ 5273 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008169, (_val)) 5274 #define WRITE_WC40_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _val) \ 5275 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008169, (_val)) 5276 #define MODIFY_WC40_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _val, _mask) \ 5277 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008169, (_val), (_mask)) 5278 5279 /* TX Lane Swap Control 2 Register */ 5280 #define READ_WC40_XGXSBLK8_TXLNSWAP2r(_unit, _pc, _val) \ 5281 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000816a, (_val)) 5282 #define WRITE_WC40_XGXSBLK8_TXLNSWAP2r(_unit, _pc, _val) \ 5283 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000816a, (_val)) 5284 #define MODIFY_WC40_XGXSBLK8_TXLNSWAP2r(_unit, _pc, _val, _mask) \ 5285 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000816a, (_val), (_mask)) 5286 5287 /* RX Lane Swap Control 1 Register */ 5288 #define READ_WC40_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _val) \ 5289 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000816b, (_val)) 5290 #define WRITE_WC40_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _val) \ 5291 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000816b, (_val)) 5292 #define MODIFY_WC40_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _val, _mask) \ 5293 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000816b, (_val), (_mask)) 5294 5295 /* RX Lane Swap Control 2 Register */ 5296 #define READ_WC40_XGXSBLK8_RXLNSWAP2r(_unit, _pc, _val) \ 5297 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000816c, (_val)) 5298 #define WRITE_WC40_XGXSBLK8_RXLNSWAP2r(_unit, _pc, _val) \ 5299 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000816c, (_val)) 5300 #define MODIFY_WC40_XGXSBLK8_RXLNSWAP2r(_unit, _pc, _val, _mask) \ 5301 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000816c, (_val), (_mask)) 5302 5303 /* Temp Sensor 1 Register */ 5304 #define READ_WC40_XGXSBLK8_TEMP_SENSOR1r(_unit, _pc, _val) \ 5305 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000816d, (_val)) 5306 #define WRITE_WC40_XGXSBLK8_TEMP_SENSOR1r(_unit, _pc, _val) \ 5307 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000816d, (_val)) 5308 #define MODIFY_WC40_XGXSBLK8_TEMP_SENSOR1r(_unit, _pc, _val, _mask) \ 5309 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000816d, (_val), (_mask)) 5310 5311 /* Temp Sensor 2 Register */ 5312 #define READ_WC40_XGXSBLK8_TEMP_SENSOR2r(_unit, _pc, _val) \ 5313 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000816e, (_val)) 5314 #define WRITE_WC40_XGXSBLK8_TEMP_SENSOR2r(_unit, _pc, _val) \ 5315 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000816e, (_val)) 5316 #define MODIFY_WC40_XGXSBLK8_TEMP_SENSOR2r(_unit, _pc, _val, _mask) \ 5317 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000816e, (_val), (_mask)) 5318 5319 5320 5321 /**************************************************************************** 5322 * Warpcore_USER_XgxsBlk9 5323 */ 5324 /* R2 control register */ 5325 #define READ_WC40_XGXSBLK9_R2_CONTROLr(_unit, _pc, _val) \ 5326 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008170, (_val)) 5327 #define WRITE_WC40_XGXSBLK9_R2_CONTROLr(_unit, _pc, _val) \ 5328 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008170, (_val)) 5329 #define MODIFY_WC40_XGXSBLK9_R2_CONTROLr(_unit, _pc, _val, _mask) \ 5330 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008170, (_val), (_mask)) 5331 5332 /* R2 status register */ 5333 #define READ_WC40_XGXSBLK9_R2_STATUSr(_unit, _pc, _val) \ 5334 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008171, (_val)) 5335 #define WRITE_WC40_XGXSBLK9_R2_STATUSr(_unit, _pc, _val) \ 5336 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008171, (_val)) 5337 #define MODIFY_WC40_XGXSBLK9_R2_STATUSr(_unit, _pc, _val, _mask) \ 5338 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008171, (_val), (_mask)) 5339 5340 /* R2 deskew control register */ 5341 #define READ_WC40_XGXSBLK9_R2_DESKEW_CONTROLr(_unit, _pc, _val) \ 5342 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008172, (_val)) 5343 #define WRITE_WC40_XGXSBLK9_R2_DESKEW_CONTROLr(_unit, _pc, _val) \ 5344 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008172, (_val)) 5345 #define MODIFY_WC40_XGXSBLK9_R2_DESKEW_CONTROLr(_unit, _pc, _val, _mask) \ 5346 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008172, (_val), (_mask)) 5347 5348 5349 5350 /**************************************************************************** 5351 * Warpcore_USER_XgxsBlk10 5352 */ 5353 /* TX Phase interpolator Control 4 Register */ 5354 #define READ_WC40_XGXSBLK10_TX_PI_CONTROL4r(_unit, _pc, _val) \ 5355 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008190, (_val)) 5356 #define WRITE_WC40_XGXSBLK10_TX_PI_CONTROL4r(_unit, _pc, _val) \ 5357 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008190, (_val)) 5358 #define MODIFY_WC40_XGXSBLK10_TX_PI_CONTROL4r(_unit, _pc, _val, _mask) \ 5359 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008190, (_val), (_mask)) 5360 5361 /* XFI AFE Control1 Register */ 5362 #define READ_WC40_XGXSBLK10_XFI_AFE_CTL1r(_unit, _pc, _val) \ 5363 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008191, (_val)) 5364 #define WRITE_WC40_XGXSBLK10_XFI_AFE_CTL1r(_unit, _pc, _val) \ 5365 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008191, (_val)) 5366 #define MODIFY_WC40_XGXSBLK10_XFI_AFE_CTL1r(_unit, _pc, _val, _mask) \ 5367 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008191, (_val), (_mask)) 5368 5369 /* XFI AFE Control2 Registe */ 5370 #define READ_WC40_XGXSBLK10_XFI_AFE_CTL2r(_unit, _pc, _val) \ 5371 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008192, (_val)) 5372 #define WRITE_WC40_XGXSBLK10_XFI_AFE_CTL2r(_unit, _pc, _val) \ 5373 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008192, (_val)) 5374 #define MODIFY_WC40_XGXSBLK10_XFI_AFE_CTL2r(_unit, _pc, _val, _mask) \ 5375 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008192, (_val), (_mask)) 5376 5377 /* XFI AFE ACJTAG value Register */ 5378 #define READ_WC40_XGXSBLK10_XFI_AFE_ACJVALr(_unit, _pc, _val) \ 5379 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008193, (_val)) 5380 #define WRITE_WC40_XGXSBLK10_XFI_AFE_ACJVALr(_unit, _pc, _val) \ 5381 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008193, (_val)) 5382 #define MODIFY_WC40_XGXSBLK10_XFI_AFE_ACJVALr(_unit, _pc, _val, _mask) \ 5383 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008193, (_val), (_mask)) 5384 5385 /* TX Phase interpolator Status 3 Register */ 5386 #define READ_WC40_XGXSBLK10_TX_PI_STATUS3r(_unit, _pc, _val) \ 5387 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008194, (_val)) 5388 #define WRITE_WC40_XGXSBLK10_TX_PI_STATUS3r(_unit, _pc, _val) \ 5389 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008194, (_val)) 5390 #define MODIFY_WC40_XGXSBLK10_TX_PI_STATUS3r(_unit, _pc, _val, _mask) \ 5391 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008194, (_val), (_mask)) 5392 5393 /* TX Phase interpolator Status 4 Register */ 5394 #define READ_WC40_XGXSBLK10_TX_PI_STATUS4r(_unit, _pc, _val) \ 5395 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008195, (_val)) 5396 #define WRITE_WC40_XGXSBLK10_TX_PI_STATUS4r(_unit, _pc, _val) \ 5397 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008195, (_val)) 5398 #define MODIFY_WC40_XGXSBLK10_TX_PI_STATUS4r(_unit, _pc, _val, _mask) \ 5399 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008195, (_val), (_mask)) 5400 5401 /* TX Phase interpolator Control 5 Register */ 5402 #define READ_WC40_XGXSBLK10_TX_PI_CONTROL5r(_unit, _pc, _val) \ 5403 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008196, (_val)) 5404 #define WRITE_WC40_XGXSBLK10_TX_PI_CONTROL5r(_unit, _pc, _val) \ 5405 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008196, (_val)) 5406 #define MODIFY_WC40_XGXSBLK10_TX_PI_CONTROL5r(_unit, _pc, _val, _mask) \ 5407 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008196, (_val), (_mask)) 5408 5409 /* Blk10 MISC Register. Hand added */ 5410 #define READ_WC40_XGXSBLK10_MISC_CONTROLr(_unit, _pc, _val) \ 5411 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008197, (_val)) 5412 #define WRITE_WC40_XGXSBLK10_MISC_CONTROLr(_unit, _pc, _val) \ 5413 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008197, (_val)) 5414 #define MODIFY_WC40_XGXSBLK10_MISC_CONTROLr(_unit, _pc, _val, _mask) \ 5415 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008197, (_val), (_mask)) 5416 5417 /**************************************************************************** 5418 * Warpcore_USER_GP2_reg 5419 */ 5420 /* GP2 status 0 register */ 5421 #define READ_WC40_GP2_REG_GP2_0r(_unit, _pc, _val) \ 5422 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081d0, (_val)) 5423 #define WRITE_WC40_GP2_REG_GP2_0r(_unit, _pc, _val) \ 5424 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081d0, (_val)) 5425 #define MODIFY_WC40_GP2_REG_GP2_0r(_unit, _pc, _val, _mask) \ 5426 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d0, (_val), (_mask)) 5427 5428 /* GP2 status 1 register */ 5429 #define READ_WC40_GP2_REG_GP2_1r(_unit, _pc, _val) \ 5430 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081d1, (_val)) 5431 #define WRITE_WC40_GP2_REG_GP2_1r(_unit, _pc, _val) \ 5432 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081d1, (_val)) 5433 #define MODIFY_WC40_GP2_REG_GP2_1r(_unit, _pc, _val, _mask) \ 5434 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d1, (_val), (_mask)) 5435 5436 /* GP2 status 2 register */ 5437 #define READ_WC40_GP2_REG_GP2_2r(_unit, _pc, _val) \ 5438 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081d2, (_val)) 5439 #define WRITE_WC40_GP2_REG_GP2_2r(_unit, _pc, _val) \ 5440 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081d2, (_val)) 5441 #define MODIFY_WC40_GP2_REG_GP2_2r(_unit, _pc, _val, _mask) \ 5442 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d2, (_val), (_mask)) 5443 5444 /* GP2 status 3 register */ 5445 #define READ_WC40_GP2_REG_GP2_3r(_unit, _pc, _val) \ 5446 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081d3, (_val)) 5447 #define WRITE_WC40_GP2_REG_GP2_3r(_unit, _pc, _val) \ 5448 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081d3, (_val)) 5449 #define MODIFY_WC40_GP2_REG_GP2_3r(_unit, _pc, _val, _mask) \ 5450 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d3, (_val), (_mask)) 5451 5452 /* GP2 status 4 register */ 5453 #define READ_WC40_GP2_REG_GP2_4r(_unit, _pc, _val) \ 5454 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081d4, (_val)) 5455 #define WRITE_WC40_GP2_REG_GP2_4r(_unit, _pc, _val) \ 5456 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081d4, (_val)) 5457 #define MODIFY_WC40_GP2_REG_GP2_4r(_unit, _pc, _val, _mask) \ 5458 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d4, (_val), (_mask)) 5459 5460 /* GP2 status 5 register */ 5461 #define READ_WC40_GP2_REG_GP2_5r(_unit, _pc, _val) \ 5462 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081d5, (_val)) 5463 #define WRITE_WC40_GP2_REG_GP2_5r(_unit, _pc, _val) \ 5464 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081d5, (_val)) 5465 #define MODIFY_WC40_GP2_REG_GP2_5r(_unit, _pc, _val, _mask) \ 5466 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d5, (_val), (_mask)) 5467 5468 /* GP2 status 6 register */ 5469 #define READ_WC40_GP2_REG_GP2_6r(_unit, _pc, _val) \ 5470 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081d6, (_val)) 5471 #define WRITE_WC40_GP2_REG_GP2_6r(_unit, _pc, _val) \ 5472 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081d6, (_val)) 5473 #define MODIFY_WC40_GP2_REG_GP2_6r(_unit, _pc, _val, _mask) \ 5474 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d6, (_val), (_mask)) 5475 5476 /* GP2 status 7 register */ 5477 #define READ_WC40_GP2_REG_GP2_7r(_unit, _pc, _val) \ 5478 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081d7, (_val)) 5479 #define WRITE_WC40_GP2_REG_GP2_7r(_unit, _pc, _val) \ 5480 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081d7, (_val)) 5481 #define MODIFY_WC40_GP2_REG_GP2_7r(_unit, _pc, _val, _mask) \ 5482 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d7, (_val), (_mask)) 5483 5484 /* GP2 status 8 register */ 5485 #define READ_WC40_GP2_REG_GP2_8r(_unit, _pc, _val) \ 5486 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081d8, (_val)) 5487 #define WRITE_WC40_GP2_REG_GP2_8r(_unit, _pc, _val) \ 5488 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081d8, (_val)) 5489 #define MODIFY_WC40_GP2_REG_GP2_8r(_unit, _pc, _val, _mask) \ 5490 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d8, (_val), (_mask)) 5491 5492 /* GP2 status 9 register */ 5493 #define READ_WC40_GP2_REG_GP2_9r(_unit, _pc, _val) \ 5494 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081d9, (_val)) 5495 #define WRITE_WC40_GP2_REG_GP2_9r(_unit, _pc, _val) \ 5496 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081d9, (_val)) 5497 #define MODIFY_WC40_GP2_REG_GP2_9r(_unit, _pc, _val, _mask) \ 5498 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d9, (_val), (_mask)) 5499 5500 /* GP2 status A register */ 5501 #define READ_WC40_GP2_REG_GP2_Ar(_unit, _pc, _val) \ 5502 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081da, (_val)) 5503 #define WRITE_WC40_GP2_REG_GP2_Ar(_unit, _pc, _val) \ 5504 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081da, (_val)) 5505 #define MODIFY_WC40_GP2_REG_GP2_Ar(_unit, _pc, _val, _mask) \ 5506 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081da, (_val), (_mask)) 5507 5508 /* GP2 status B register */ 5509 #define READ_WC40_GP2_REG_GP2_Br(_unit, _pc, _val) \ 5510 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081db, (_val)) 5511 #define WRITE_WC40_GP2_REG_GP2_Br(_unit, _pc, _val) \ 5512 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081db, (_val)) 5513 #define MODIFY_WC40_GP2_REG_GP2_Br(_unit, _pc, _val, _mask) \ 5514 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081db, (_val), (_mask)) 5515 5516 /* GP2 status C register */ 5517 #define READ_WC40_GP2_REG_GP2_Cr(_unit, _pc, _val) \ 5518 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081dc, (_val)) 5519 #define WRITE_WC40_GP2_REG_GP2_Cr(_unit, _pc, _val) \ 5520 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081dc, (_val)) 5521 #define MODIFY_WC40_GP2_REG_GP2_Cr(_unit, _pc, _val, _mask) \ 5522 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081dc, (_val), (_mask)) 5523 5524 /* GP2 status D register */ 5525 #define READ_WC40_GP2_REG_GP2_Dr(_unit, _pc, _val) \ 5526 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081dd, (_val)) 5527 #define WRITE_WC40_GP2_REG_GP2_Dr(_unit, _pc, _val) \ 5528 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081dd, (_val)) 5529 #define MODIFY_WC40_GP2_REG_GP2_Dr(_unit, _pc, _val, _mask) \ 5530 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081dd, (_val), (_mask)) 5531 5532 /* GP2 status E register */ 5533 #define READ_WC40_GP2_REG_GP2_Er(_unit, _pc, _val) \ 5534 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081de, (_val)) 5535 #define WRITE_WC40_GP2_REG_GP2_Er(_unit, _pc, _val) \ 5536 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081de, (_val)) 5537 #define MODIFY_WC40_GP2_REG_GP2_Er(_unit, _pc, _val, _mask) \ 5538 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081de, (_val), (_mask)) 5539 5540 5541 5542 /**************************************************************************** 5543 * Warpcore_USER_uC_info_B0 5544 */ 5545 /* Micro-controller Tuning State Debug for LN0 */ 5546 #define READ_WC40_UC_INFO_B0_STATE_DEBUG_LN0r(_unit, _pc, _val) \ 5547 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081e0, (_val)) 5548 #define WRITE_WC40_UC_INFO_B0_STATE_DEBUG_LN0r(_unit, _pc, _val) \ 5549 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081e0, (_val)) 5550 #define MODIFY_WC40_UC_INFO_B0_STATE_DEBUG_LN0r(_unit, _pc, _val, _mask) \ 5551 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e0, (_val), (_mask)) 5552 5553 /* Micro-controller Tuning State Debug for LN1 */ 5554 #define READ_WC40_UC_INFO_B0_STATE_DEBUG_LN1r(_unit, _pc, _val) \ 5555 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081e1, (_val)) 5556 #define WRITE_WC40_UC_INFO_B0_STATE_DEBUG_LN1r(_unit, _pc, _val) \ 5557 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081e1, (_val)) 5558 #define MODIFY_WC40_UC_INFO_B0_STATE_DEBUG_LN1r(_unit, _pc, _val, _mask) \ 5559 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e1, (_val), (_mask)) 5560 5561 /* Micro-controller Tuning State Debug for LN2 */ 5562 #define READ_WC40_UC_INFO_B0_STATE_DEBUG_LN2r(_unit, _pc, _val) \ 5563 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081e2, (_val)) 5564 #define WRITE_WC40_UC_INFO_B0_STATE_DEBUG_LN2r(_unit, _pc, _val) \ 5565 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081e2, (_val)) 5566 #define MODIFY_WC40_UC_INFO_B0_STATE_DEBUG_LN2r(_unit, _pc, _val, _mask) \ 5567 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e2, (_val), (_mask)) 5568 5569 /* Micro-controller Tuning State Debug for LN3 */ 5570 #define READ_WC40_UC_INFO_B0_STATE_DEBUG_LN3r(_unit, _pc, _val) \ 5571 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081e3, (_val)) 5572 #define WRITE_WC40_UC_INFO_B0_STATE_DEBUG_LN3r(_unit, _pc, _val) \ 5573 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081e3, (_val)) 5574 #define MODIFY_WC40_UC_INFO_B0_STATE_DEBUG_LN3r(_unit, _pc, _val, _mask) \ 5575 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e3, (_val), (_mask)) 5576 5577 /* Micro-controller Speed/Mode Debug for LN0 */ 5578 #define READ_WC40_UC_INFO_B0_SPEED_DEBUG_LN0r(_unit, _pc, _val) \ 5579 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081e4, (_val)) 5580 #define WRITE_WC40_UC_INFO_B0_SPEED_DEBUG_LN0r(_unit, _pc, _val) \ 5581 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081e4, (_val)) 5582 #define MODIFY_WC40_UC_INFO_B0_SPEED_DEBUG_LN0r(_unit, _pc, _val, _mask) \ 5583 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e4, (_val), (_mask)) 5584 5585 /* Micro-controller Speed/Mode Debug for LN1 */ 5586 #define READ_WC40_UC_INFO_B0_SPEED_DEBUG_LN1r(_unit, _pc, _val) \ 5587 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081e5, (_val)) 5588 #define WRITE_WC40_UC_INFO_B0_SPEED_DEBUG_LN1r(_unit, _pc, _val) \ 5589 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081e5, (_val)) 5590 #define MODIFY_WC40_UC_INFO_B0_SPEED_DEBUG_LN1r(_unit, _pc, _val, _mask) \ 5591 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e5, (_val), (_mask)) 5592 5593 /* Micro-controller Speed/Mode Debug for LN2 */ 5594 #define READ_WC40_UC_INFO_B0_SPEED_DEBUG_LN2r(_unit, _pc, _val) \ 5595 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081e6, (_val)) 5596 #define WRITE_WC40_UC_INFO_B0_SPEED_DEBUG_LN2r(_unit, _pc, _val) \ 5597 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081e6, (_val)) 5598 #define MODIFY_WC40_UC_INFO_B0_SPEED_DEBUG_LN2r(_unit, _pc, _val, _mask) \ 5599 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e6, (_val), (_mask)) 5600 5601 /* Micro-controller Speed/Mode Debug for LN3 */ 5602 #define READ_WC40_UC_INFO_B0_SPEED_DEBUG_LN3r(_unit, _pc, _val) \ 5603 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081e7, (_val)) 5604 #define WRITE_WC40_UC_INFO_B0_SPEED_DEBUG_LN3r(_unit, _pc, _val) \ 5605 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081e7, (_val)) 5606 #define MODIFY_WC40_UC_INFO_B0_SPEED_DEBUG_LN3r(_unit, _pc, _val, _mask) \ 5607 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e7, (_val), (_mask)) 5608 5609 /* Micro-controller CL72 Status for LN0 */ 5610 #define READ_WC40_UC_INFO_B0_CL72_STATUS_LN0r(_unit, _pc, _val) \ 5611 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081e8, (_val)) 5612 #define WRITE_WC40_UC_INFO_B0_CL72_STATUS_LN0r(_unit, _pc, _val) \ 5613 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081e8, (_val)) 5614 #define MODIFY_WC40_UC_INFO_B0_CL72_STATUS_LN0r(_unit, _pc, _val, _mask) \ 5615 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e8, (_val), (_mask)) 5616 5617 /* Micro-controller CL72 Status for LN1 */ 5618 #define READ_WC40_UC_INFO_B0_CL72_STATUS_LN1r(_unit, _pc, _val) \ 5619 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081e9, (_val)) 5620 #define WRITE_WC40_UC_INFO_B0_CL72_STATUS_LN1r(_unit, _pc, _val) \ 5621 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081e9, (_val)) 5622 #define MODIFY_WC40_UC_INFO_B0_CL72_STATUS_LN1r(_unit, _pc, _val, _mask) \ 5623 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e9, (_val), (_mask)) 5624 5625 /* Micro-controller CL72 Status for LN2 */ 5626 #define READ_WC40_UC_INFO_B0_CL72_STATUS_LN2r(_unit, _pc, _val) \ 5627 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081ea, (_val)) 5628 #define WRITE_WC40_UC_INFO_B0_CL72_STATUS_LN2r(_unit, _pc, _val) \ 5629 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081ea, (_val)) 5630 #define MODIFY_WC40_UC_INFO_B0_CL72_STATUS_LN2r(_unit, _pc, _val, _mask) \ 5631 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ea, (_val), (_mask)) 5632 5633 /* Micro-controller CL72 Status for LN3 */ 5634 #define READ_WC40_UC_INFO_B0_CL72_STATUS_LN3r(_unit, _pc, _val) \ 5635 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081eb, (_val)) 5636 #define WRITE_WC40_UC_INFO_B0_CL72_STATUS_LN3r(_unit, _pc, _val) \ 5637 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081eb, (_val)) 5638 #define MODIFY_WC40_UC_INFO_B0_CL72_STATUS_LN3r(_unit, _pc, _val, _mask) \ 5639 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081eb, (_val), (_mask)) 5640 5641 /* Micro-controller Debug Register0 */ 5642 #define READ_WC40_UC_INFO_B0_DEBUG_REG0r(_unit, _pc, _val) \ 5643 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081ec, (_val)) 5644 #define WRITE_WC40_UC_INFO_B0_DEBUG_REG0r(_unit, _pc, _val) \ 5645 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081ec, (_val)) 5646 #define MODIFY_WC40_UC_INFO_B0_DEBUG_REG0r(_unit, _pc, _val, _mask) \ 5647 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ec, (_val), (_mask)) 5648 5649 /* Micro-controller Debug Register1 */ 5650 #define READ_WC40_UC_INFO_B0_DEBUG_REG1r(_unit, _pc, _val) \ 5651 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081ed, (_val)) 5652 #define WRITE_WC40_UC_INFO_B0_DEBUG_REG1r(_unit, _pc, _val) \ 5653 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081ed, (_val)) 5654 #define MODIFY_WC40_UC_INFO_B0_DEBUG_REG1r(_unit, _pc, _val, _mask) \ 5655 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ed, (_val), (_mask)) 5656 5657 /* Micro-controller Dead-Trap Register */ 5658 #define READ_WC40_UC_INFO_B0_DEAD_TRAPr(_unit, _pc, _val) \ 5659 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081ee, (_val)) 5660 #define WRITE_WC40_UC_INFO_B0_DEAD_TRAPr(_unit, _pc, _val) \ 5661 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081ee, (_val)) 5662 #define MODIFY_WC40_UC_INFO_B0_DEAD_TRAPr(_unit, _pc, _val, _mask) \ 5663 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ee, (_val), (_mask)) 5664 5665 5666 5667 /**************************************************************************** 5668 * Warpcore_USER_uC_info_B1 5669 */ 5670 /* Micro-controller Version Register */ 5671 #define READ_WC40_UC_INFO_B1_VERSIONr(_unit, _pc, _val) \ 5672 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081f0, (_val)) 5673 #define WRITE_WC40_UC_INFO_B1_VERSIONr(_unit, _pc, _val) \ 5674 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081f0, (_val)) 5675 #define MODIFY_WC40_UC_INFO_B1_VERSIONr(_unit, _pc, _val, _mask) \ 5676 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f0, (_val), (_mask)) 5677 5678 /* Micro-controller Target Register */ 5679 #define READ_WC40_UC_INFO_B1_TARGETr(_unit, _pc, _val) \ 5680 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081f1, (_val)) 5681 #define WRITE_WC40_UC_INFO_B1_TARGETr(_unit, _pc, _val) \ 5682 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081f1, (_val)) 5683 #define MODIFY_WC40_UC_INFO_B1_TARGETr(_unit, _pc, _val, _mask) \ 5684 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f1, (_val), (_mask)) 5685 5686 /* Micro-controller firmware_mode 2_2 Register */ 5687 #define READ_WC40_UC_INFO_B1_FIRMWARE_MODEr(_unit, _pc, _val) \ 5688 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081f2, (_val)) 5689 #define WRITE_WC40_UC_INFO_B1_FIRMWARE_MODEr(_unit, _pc, _val) \ 5690 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081f2, (_val)) 5691 #define MODIFY_WC40_UC_INFO_B1_FIRMWARE_MODEr(_unit, _pc, _val, _mask) \ 5692 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f2, (_val), (_mask)) 5693 5694 /* Micro-controller LN0 GPIO Control Register */ 5695 #define READ_WC40_UC_INFO_B1_GPIO_CTRL_LN0r(_unit, _pc, _val) \ 5696 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081f3, (_val)) 5697 #define WRITE_WC40_UC_INFO_B1_GPIO_CTRL_LN0r(_unit, _pc, _val) \ 5698 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081f3, (_val)) 5699 #define MODIFY_WC40_UC_INFO_B1_GPIO_CTRL_LN0r(_unit, _pc, _val, _mask) \ 5700 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f3, (_val), (_mask)) 5701 5702 /* Micro-controller LN1 GPIO Control Register */ 5703 #define READ_WC40_UC_INFO_B1_GPIO_CTRL_LN1r(_unit, _pc, _val) \ 5704 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081f4, (_val)) 5705 #define WRITE_WC40_UC_INFO_B1_GPIO_CTRL_LN1r(_unit, _pc, _val) \ 5706 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081f4, (_val)) 5707 #define MODIFY_WC40_UC_INFO_B1_GPIO_CTRL_LN1r(_unit, _pc, _val, _mask) \ 5708 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f4, (_val), (_mask)) 5709 5710 /* Micro-controller LN2 GPIO Control Register */ 5711 #define READ_WC40_UC_INFO_B1_GPIO_CTRL_LN2r(_unit, _pc, _val) \ 5712 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081f5, (_val)) 5713 #define WRITE_WC40_UC_INFO_B1_GPIO_CTRL_LN2r(_unit, _pc, _val) \ 5714 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081f5, (_val)) 5715 #define MODIFY_WC40_UC_INFO_B1_GPIO_CTRL_LN2r(_unit, _pc, _val, _mask) \ 5716 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f5, (_val), (_mask)) 5717 5718 /* Micro-controller LN3 GPIO Control Register */ 5719 #define READ_WC40_UC_INFO_B1_GPIO_CTRL_LN3r(_unit, _pc, _val) \ 5720 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081f6, (_val)) 5721 #define WRITE_WC40_UC_INFO_B1_GPIO_CTRL_LN3r(_unit, _pc, _val) \ 5722 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081f6, (_val)) 5723 #define MODIFY_WC40_UC_INFO_B1_GPIO_CTRL_LN3r(_unit, _pc, _val, _mask) \ 5724 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f6, (_val), (_mask)) 5725 5726 /* Micro-controller LN0 GPIO Status Register */ 5727 #define READ_WC40_UC_INFO_B1_GPIO_STS_LN0r(_unit, _pc, _val) \ 5728 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081f7, (_val)) 5729 #define WRITE_WC40_UC_INFO_B1_GPIO_STS_LN0r(_unit, _pc, _val) \ 5730 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081f7, (_val)) 5731 #define MODIFY_WC40_UC_INFO_B1_GPIO_STS_LN0r(_unit, _pc, _val, _mask) \ 5732 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f7, (_val), (_mask)) 5733 5734 /* Micro-controller LN1 GPIO Status Register */ 5735 #define READ_WC40_UC_INFO_B1_GPIO_STS_LN1r(_unit, _pc, _val) \ 5736 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081f8, (_val)) 5737 #define WRITE_WC40_UC_INFO_B1_GPIO_STS_LN1r(_unit, _pc, _val) \ 5738 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081f8, (_val)) 5739 #define MODIFY_WC40_UC_INFO_B1_GPIO_STS_LN1r(_unit, _pc, _val, _mask) \ 5740 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f8, (_val), (_mask)) 5741 5742 /* Micro-controller LN2 GPIO Status Register */ 5743 #define READ_WC40_UC_INFO_B1_GPIO_STS_LN2r(_unit, _pc, _val) \ 5744 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081f9, (_val)) 5745 #define WRITE_WC40_UC_INFO_B1_GPIO_STS_LN2r(_unit, _pc, _val) \ 5746 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081f9, (_val)) 5747 #define MODIFY_WC40_UC_INFO_B1_GPIO_STS_LN2r(_unit, _pc, _val, _mask) \ 5748 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f9, (_val), (_mask)) 5749 5750 /* Micro-controller LN3 GPIO Status Register */ 5751 #define READ_WC40_UC_INFO_B1_GPIO_STS_LN3r(_unit, _pc, _val) \ 5752 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081fa, (_val)) 5753 #define WRITE_WC40_UC_INFO_B1_GPIO_STS_LN3r(_unit, _pc, _val) \ 5754 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081fa, (_val)) 5755 #define MODIFY_WC40_UC_INFO_B1_GPIO_STS_LN3r(_unit, _pc, _val, _mask) \ 5756 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fa, (_val), (_mask)) 5757 5758 /* Micro Temp 2_B Register */ 5759 #define READ_WC40_UC_INFO_B1_REGBr(_unit, _pc, _val) \ 5760 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081fb, (_val)) 5761 #define WRITE_WC40_UC_INFO_B1_REGBr(_unit, _pc, _val) \ 5762 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081fb, (_val)) 5763 #define MODIFY_WC40_UC_INFO_B1_REGBr(_unit, _pc, _val, _mask) \ 5764 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fb, (_val), (_mask)) 5765 5766 /* Micro Tuning states Bypass Register */ 5767 #define READ_WC40_UC_INFO_B1_TUNING_STATE_BYPASSr(_unit, _pc, _val) \ 5768 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081fc, (_val)) 5769 #define WRITE_WC40_UC_INFO_B1_TUNING_STATE_BYPASSr(_unit, _pc, _val) \ 5770 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081fc, (_val)) 5771 #define MODIFY_WC40_UC_INFO_B1_TUNING_STATE_BYPASSr(_unit, _pc, _val, _mask) \ 5772 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fc, (_val), (_mask)) 5773 5774 /* Die-Temperature Register */ 5775 #define READ_WC40_UC_INFO_B1_TEMPERATUREr(_unit, _pc, _val) \ 5776 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081fd, (_val)) 5777 #define WRITE_WC40_UC_INFO_B1_TEMPERATUREr(_unit, _pc, _val) \ 5778 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081fd, (_val)) 5779 #define MODIFY_WC40_UC_INFO_B1_TEMPERATUREr(_unit, _pc, _val, _mask) \ 5780 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fd, (_val), (_mask)) 5781 5782 /* Micro-controller code-ram crc Register */ 5783 #define READ_WC40_UC_INFO_B1_CRCr(_unit, _pc, _val) \ 5784 WC40_REG_READ((_unit), (_pc), 0x00, 0x000081fe, (_val)) 5785 #define WRITE_WC40_UC_INFO_B1_CRCr(_unit, _pc, _val) \ 5786 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000081fe, (_val)) 5787 #define MODIFY_WC40_UC_INFO_B1_CRCr(_unit, _pc, _val, _mask) \ 5788 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fe, (_val), (_mask)) 5789 5790 5791 5792 /**************************************************************************** 5793 * Warpcore_USER_Dsc1b0 5794 */ 5795 /* CDR Control 0 Register */ 5796 #define READ_WC40_DSC1B0_CDR_CTRL0r(_unit, _pc, _val) \ 5797 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008200, (_val)) 5798 #define WRITE_WC40_DSC1B0_CDR_CTRL0r(_unit, _pc, _val) \ 5799 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008200, (_val)) 5800 #define MODIFY_WC40_DSC1B0_CDR_CTRL0r(_unit, _pc, _val, _mask) \ 5801 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008200, (_val), (_mask)) 5802 5803 /* CDR Control 1 Register */ 5804 #define READ_WC40_DSC1B0_CDR_CTRL1r(_unit, _pc, _val) \ 5805 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008201, (_val)) 5806 #define WRITE_WC40_DSC1B0_CDR_CTRL1r(_unit, _pc, _val) \ 5807 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008201, (_val)) 5808 #define MODIFY_WC40_DSC1B0_CDR_CTRL1r(_unit, _pc, _val, _mask) \ 5809 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008201, (_val), (_mask)) 5810 5811 /* CDR Control 2 Register */ 5812 #define READ_WC40_DSC1B0_CDR_CTRL2r(_unit, _pc, _val) \ 5813 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008202, (_val)) 5814 #define WRITE_WC40_DSC1B0_CDR_CTRL2r(_unit, _pc, _val) \ 5815 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008202, (_val)) 5816 #define MODIFY_WC40_DSC1B0_CDR_CTRL2r(_unit, _pc, _val, _mask) \ 5817 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008202, (_val), (_mask)) 5818 5819 /* Phase Interpolator Control 0 Register */ 5820 #define READ_WC40_DSC1B0_PI_CTRL0r(_unit, _pc, _val) \ 5821 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008203, (_val)) 5822 #define WRITE_WC40_DSC1B0_PI_CTRL0r(_unit, _pc, _val) \ 5823 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008203, (_val)) 5824 #define MODIFY_WC40_DSC1B0_PI_CTRL0r(_unit, _pc, _val, _mask) \ 5825 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008203, (_val), (_mask)) 5826 5827 /* Phase Interpolator Control 1 Register */ 5828 #define READ_WC40_DSC1B0_PI_CTRL1r(_unit, _pc, _val) \ 5829 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008204, (_val)) 5830 #define WRITE_WC40_DSC1B0_PI_CTRL1r(_unit, _pc, _val) \ 5831 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008204, (_val)) 5832 #define MODIFY_WC40_DSC1B0_PI_CTRL1r(_unit, _pc, _val, _mask) \ 5833 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008204, (_val), (_mask)) 5834 5835 /* DFE VGA Control 0 Register */ 5836 #define READ_WC40_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 5837 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008205, (_val)) 5838 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 5839 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008205, (_val)) 5840 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \ 5841 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008205, (_val), (_mask)) 5842 5843 /* DFE VGA Control 1 Register */ 5844 #define READ_WC40_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 5845 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008206, (_val)) 5846 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 5847 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008206, (_val)) 5848 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \ 5849 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008206, (_val), (_mask)) 5850 5851 /* DFE VGA Control 2 Register */ 5852 #define READ_WC40_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 5853 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008207, (_val)) 5854 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 5855 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008207, (_val)) 5856 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \ 5857 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008207, (_val), (_mask)) 5858 5859 /* DFE VGA Control 3 Register */ 5860 #define READ_WC40_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 5861 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008208, (_val)) 5862 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 5863 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008208, (_val)) 5864 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \ 5865 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008208, (_val), (_mask)) 5866 5867 /* DFE VGA Control 4 Register */ 5868 #define READ_WC40_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 5869 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008209, (_val)) 5870 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 5871 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008209, (_val)) 5872 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \ 5873 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008209, (_val), (_mask)) 5874 5875 /* DFE VGA Control 5 Register */ 5876 #define READ_WC40_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 5877 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000820a, (_val)) 5878 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 5879 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000820a, (_val)) 5880 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \ 5881 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000820a, (_val), (_mask)) 5882 5883 /* DFE VGA Control 6 Register */ 5884 #define READ_WC40_DSC1B0_DFE_VGA_CTRL6r(_unit, _pc, _val) \ 5885 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000820b, (_val)) 5886 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL6r(_unit, _pc, _val) \ 5887 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000820b, (_val)) 5888 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL6r(_unit, _pc, _val, _mask) \ 5889 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000820b, (_val), (_mask)) 5890 5891 /* DFE VGA Control 7 Register */ 5892 #define READ_WC40_DSC1B0_DFE_VGA_CTRL7r(_unit, _pc, _val) \ 5893 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000820c, (_val)) 5894 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL7r(_unit, _pc, _val) \ 5895 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000820c, (_val)) 5896 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL7r(_unit, _pc, _val, _mask) \ 5897 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000820c, (_val), (_mask)) 5898 5899 /* DSC Diagnostics Control 0 Register */ 5900 #define READ_WC40_DSC1B0_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 5901 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000820d, (_val)) 5902 #define WRITE_WC40_DSC1B0_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 5903 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000820d, (_val)) 5904 #define MODIFY_WC40_DSC1B0_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \ 5905 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000820d, (_val), (_mask)) 5906 5907 /* DSC to uController Control Register */ 5908 #define READ_WC40_DSC1B0_UC_CTRLr(_unit, _pc, _val) \ 5909 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000820e, (_val)) 5910 #define WRITE_WC40_DSC1B0_UC_CTRLr(_unit, _pc, _val) \ 5911 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000820e, (_val)) 5912 #define MODIFY_WC40_DSC1B0_UC_CTRLr(_unit, _pc, _val, _mask) \ 5913 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000820e, (_val), (_mask)) 5914 5915 5916 5917 /**************************************************************************** 5918 * Warpcore_USER_Dsc2b0 5919 */ 5920 /* DSC State Machine Control 0 Register */ 5921 #define READ_WC40_DSC2B0_ACQ_SM_CTRL0r(_unit, _pc, _val) \ 5922 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008210, (_val)) 5923 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL0r(_unit, _pc, _val) \ 5924 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008210, (_val)) 5925 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL0r(_unit, _pc, _val, _mask) \ 5926 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008210, (_val), (_mask)) 5927 5928 /* DSC State Machine Control 1 Register */ 5929 #define READ_WC40_DSC2B0_ACQ_SM_CTRL1r(_unit, _pc, _val) \ 5930 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008211, (_val)) 5931 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL1r(_unit, _pc, _val) \ 5932 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008211, (_val)) 5933 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL1r(_unit, _pc, _val, _mask) \ 5934 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008211, (_val), (_mask)) 5935 5936 /* DSC State Machine Control 2 Register */ 5937 #define READ_WC40_DSC2B0_ACQ_SM_CTRL2r(_unit, _pc, _val) \ 5938 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008212, (_val)) 5939 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL2r(_unit, _pc, _val) \ 5940 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008212, (_val)) 5941 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL2r(_unit, _pc, _val, _mask) \ 5942 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008212, (_val), (_mask)) 5943 5944 /* DSC State Machine Control 3 Register */ 5945 #define READ_WC40_DSC2B0_ACQ_SM_CTRL3r(_unit, _pc, _val) \ 5946 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008213, (_val)) 5947 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL3r(_unit, _pc, _val) \ 5948 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008213, (_val)) 5949 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL3r(_unit, _pc, _val, _mask) \ 5950 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008213, (_val), (_mask)) 5951 5952 /* DSC State Machine Control 4 Register */ 5953 #define READ_WC40_DSC2B0_ACQ_SM_CTRL4r(_unit, _pc, _val) \ 5954 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008214, (_val)) 5955 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL4r(_unit, _pc, _val) \ 5956 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008214, (_val)) 5957 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL4r(_unit, _pc, _val, _mask) \ 5958 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008214, (_val), (_mask)) 5959 5960 /* DSC State Machine Control 5 Register */ 5961 #define READ_WC40_DSC2B0_ACQ_SM_CTRL5r(_unit, _pc, _val) \ 5962 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008215, (_val)) 5963 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL5r(_unit, _pc, _val) \ 5964 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008215, (_val)) 5965 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL5r(_unit, _pc, _val, _mask) \ 5966 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008215, (_val), (_mask)) 5967 5968 /* DSC State Machine Control 6 Register */ 5969 #define READ_WC40_DSC2B0_ACQ_SM_CTRL6r(_unit, _pc, _val) \ 5970 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008216, (_val)) 5971 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL6r(_unit, _pc, _val) \ 5972 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008216, (_val)) 5973 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL6r(_unit, _pc, _val, _mask) \ 5974 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008216, (_val), (_mask)) 5975 5976 /* DSC State Machine Control 7 Register */ 5977 #define READ_WC40_DSC2B0_ACQ_SM_CTRL7r(_unit, _pc, _val) \ 5978 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008217, (_val)) 5979 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL7r(_unit, _pc, _val) \ 5980 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008217, (_val)) 5981 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL7r(_unit, _pc, _val, _mask) \ 5982 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008217, (_val), (_mask)) 5983 5984 /* DSC State Machine Control 8 Register */ 5985 #define READ_WC40_DSC2B0_ACQ_SM_CTRL8r(_unit, _pc, _val) \ 5986 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008218, (_val)) 5987 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL8r(_unit, _pc, _val) \ 5988 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008218, (_val)) 5989 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL8r(_unit, _pc, _val, _mask) \ 5990 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008218, (_val), (_mask)) 5991 5992 /* DSC Analog Control 0 Register */ 5993 #define READ_WC40_DSC2B0_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 5994 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008219, (_val)) 5995 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 5996 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008219, (_val)) 5997 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \ 5998 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008219, (_val), (_mask)) 5999 6000 /* DSC Analog Control 1 Register */ 6001 #define READ_WC40_DSC2B0_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 6002 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000821a, (_val)) 6003 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 6004 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000821a, (_val)) 6005 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \ 6006 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821a, (_val), (_mask)) 6007 6008 /* DSC Analog Control 2 Register */ 6009 #define READ_WC40_DSC2B0_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 6010 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000821b, (_val)) 6011 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 6012 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000821b, (_val)) 6013 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \ 6014 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821b, (_val), (_mask)) 6015 6016 /* DSC Analog Control 3 Register */ 6017 #define READ_WC40_DSC2B0_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 6018 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000821c, (_val)) 6019 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 6020 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000821c, (_val)) 6021 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \ 6022 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821c, (_val), (_mask)) 6023 6024 /* DSC Analog Control 4 Register */ 6025 #define READ_WC40_DSC2B0_DSC_ANA_CTRL4r(_unit, _pc, _val) \ 6026 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000821d, (_val)) 6027 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL4r(_unit, _pc, _val) \ 6028 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000821d, (_val)) 6029 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL4r(_unit, _pc, _val, _mask) \ 6030 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821d, (_val), (_mask)) 6031 6032 /* DSC Misc Control 0 Register */ 6033 #define READ_WC40_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 6034 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000821e, (_val)) 6035 #define WRITE_WC40_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 6036 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000821e, (_val)) 6037 #define MODIFY_WC40_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \ 6038 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821e, (_val), (_mask)) 6039 6040 6041 6042 /**************************************************************************** 6043 * Warpcore_USER_Dsc3b0 6044 */ 6045 /* CDR Status 0 Register */ 6046 #define READ_WC40_DSC3B0_CDR_STATUS0r(_unit, _pc, _val) \ 6047 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008220, (_val)) 6048 #define WRITE_WC40_DSC3B0_CDR_STATUS0r(_unit, _pc, _val) \ 6049 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008220, (_val)) 6050 #define MODIFY_WC40_DSC3B0_CDR_STATUS0r(_unit, _pc, _val, _mask) \ 6051 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008220, (_val), (_mask)) 6052 6053 /* CDR Status 1 Register */ 6054 #define READ_WC40_DSC3B0_CDR_STATUS1r(_unit, _pc, _val) \ 6055 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008221, (_val)) 6056 #define WRITE_WC40_DSC3B0_CDR_STATUS1r(_unit, _pc, _val) \ 6057 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008221, (_val)) 6058 #define MODIFY_WC40_DSC3B0_CDR_STATUS1r(_unit, _pc, _val, _mask) \ 6059 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008221, (_val), (_mask)) 6060 6061 /* CDR Status 2 Register */ 6062 #define READ_WC40_DSC3B0_CDR_STATUS2r(_unit, _pc, _val) \ 6063 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008222, (_val)) 6064 #define WRITE_WC40_DSC3B0_CDR_STATUS2r(_unit, _pc, _val) \ 6065 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008222, (_val)) 6066 #define MODIFY_WC40_DSC3B0_CDR_STATUS2r(_unit, _pc, _val, _mask) \ 6067 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008222, (_val), (_mask)) 6068 6069 /* Phase Interpolator Status 0 Register */ 6070 #define READ_WC40_DSC3B0_PI_STATUS0r(_unit, _pc, _val) \ 6071 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008223, (_val)) 6072 #define WRITE_WC40_DSC3B0_PI_STATUS0r(_unit, _pc, _val) \ 6073 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008223, (_val)) 6074 #define MODIFY_WC40_DSC3B0_PI_STATUS0r(_unit, _pc, _val, _mask) \ 6075 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008223, (_val), (_mask)) 6076 6077 /* Phase Interpolator Status 1 Register */ 6078 #define READ_WC40_DSC3B0_PI_STATUS1r(_unit, _pc, _val) \ 6079 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008224, (_val)) 6080 #define WRITE_WC40_DSC3B0_PI_STATUS1r(_unit, _pc, _val) \ 6081 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008224, (_val)) 6082 #define MODIFY_WC40_DSC3B0_PI_STATUS1r(_unit, _pc, _val, _mask) \ 6083 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008224, (_val), (_mask)) 6084 6085 /* DFE VGA Status 0 Register */ 6086 #define READ_WC40_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 6087 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008225, (_val)) 6088 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 6089 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008225, (_val)) 6090 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \ 6091 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008225, (_val), (_mask)) 6092 6093 /* DFE VGA Status 1 Register */ 6094 #define READ_WC40_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 6095 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008226, (_val)) 6096 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 6097 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008226, (_val)) 6098 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \ 6099 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008226, (_val), (_mask)) 6100 6101 /* DFE VGA Status 2 Register */ 6102 #define READ_WC40_DSC3B0_DFE_VGA_STATUS2r(_unit, _pc, _val) \ 6103 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008227, (_val)) 6104 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS2r(_unit, _pc, _val) \ 6105 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008227, (_val)) 6106 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS2r(_unit, _pc, _val, _mask) \ 6107 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008227, (_val), (_mask)) 6108 6109 /* DFE VGA Status 3 Register */ 6110 #define READ_WC40_DSC3B0_DFE_VGA_STATUS3r(_unit, _pc, _val) \ 6111 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008228, (_val)) 6112 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS3r(_unit, _pc, _val) \ 6113 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008228, (_val)) 6114 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS3r(_unit, _pc, _val, _mask) \ 6115 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008228, (_val), (_mask)) 6116 6117 /* ACQ State Machine Status 0 Register */ 6118 #define READ_WC40_DSC3B0_ACQ_SM_STATUS0r(_unit, _pc, _val) \ 6119 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008229, (_val)) 6120 #define WRITE_WC40_DSC3B0_ACQ_SM_STATUS0r(_unit, _pc, _val) \ 6121 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008229, (_val)) 6122 #define MODIFY_WC40_DSC3B0_ACQ_SM_STATUS0r(_unit, _pc, _val, _mask) \ 6123 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008229, (_val), (_mask)) 6124 6125 /* ACQ State Machine Status 1 Register */ 6126 #define READ_WC40_DSC3B0_ACQ_SM_STATUS1r(_unit, _pc, _val) \ 6127 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000822a, (_val)) 6128 #define WRITE_WC40_DSC3B0_ACQ_SM_STATUS1r(_unit, _pc, _val) \ 6129 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000822a, (_val)) 6130 #define MODIFY_WC40_DSC3B0_ACQ_SM_STATUS1r(_unit, _pc, _val, _mask) \ 6131 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822a, (_val), (_mask)) 6132 6133 /* DSC Analog Status 0 Register */ 6134 #define READ_WC40_DSC3B0_ANA_STATUS0r(_unit, _pc, _val) \ 6135 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000822b, (_val)) 6136 #define WRITE_WC40_DSC3B0_ANA_STATUS0r(_unit, _pc, _val) \ 6137 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000822b, (_val)) 6138 #define MODIFY_WC40_DSC3B0_ANA_STATUS0r(_unit, _pc, _val, _mask) \ 6139 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822b, (_val), (_mask)) 6140 6141 /* DSC Analog Status 1 Register */ 6142 #define READ_WC40_DSC3B0_ANA_STATUS1r(_unit, _pc, _val) \ 6143 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000822c, (_val)) 6144 #define WRITE_WC40_DSC3B0_ANA_STATUS1r(_unit, _pc, _val) \ 6145 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000822c, (_val)) 6146 #define MODIFY_WC40_DSC3B0_ANA_STATUS1r(_unit, _pc, _val, _mask) \ 6147 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822c, (_val), (_mask)) 6148 6149 /* DSC Analog Status 2 Register */ 6150 #define READ_WC40_DSC3B0_ANA_STATUS2r(_unit, _pc, _val) \ 6151 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000822d, (_val)) 6152 #define WRITE_WC40_DSC3B0_ANA_STATUS2r(_unit, _pc, _val) \ 6153 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000822d, (_val)) 6154 #define MODIFY_WC40_DSC3B0_ANA_STATUS2r(_unit, _pc, _val, _mask) \ 6155 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822d, (_val), (_mask)) 6156 6157 /* DSC Analog Status 3 Register */ 6158 #define READ_WC40_DSC3B0_ANA_STATUS3r(_unit, _pc, _val) \ 6159 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000822e, (_val)) 6160 #define WRITE_WC40_DSC3B0_ANA_STATUS3r(_unit, _pc, _val) \ 6161 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000822e, (_val)) 6162 #define MODIFY_WC40_DSC3B0_ANA_STATUS3r(_unit, _pc, _val, _mask) \ 6163 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822e, (_val), (_mask)) 6164 6165 6166 6167 /**************************************************************************** 6168 * Warpcore_USER_Dsc4b0 6169 */ 6170 /* State Machine Control 0 Register */ 6171 #define READ_WC40_DSC4B0_TUNING_SM_CTRL0r(_unit, _pc, _val) \ 6172 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008230, (_val)) 6173 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL0r(_unit, _pc, _val) \ 6174 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008230, (_val)) 6175 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL0r(_unit, _pc, _val, _mask) \ 6176 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008230, (_val), (_mask)) 6177 6178 /* State Machine Control 1 Register */ 6179 #define READ_WC40_DSC4B0_TUNING_SM_CTRL1r(_unit, _pc, _val) \ 6180 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008231, (_val)) 6181 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL1r(_unit, _pc, _val) \ 6182 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008231, (_val)) 6183 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL1r(_unit, _pc, _val, _mask) \ 6184 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008231, (_val), (_mask)) 6185 6186 /* State Machine Control 2 Register */ 6187 #define READ_WC40_DSC4B0_TUNING_SM_CTRL2r(_unit, _pc, _val) \ 6188 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008232, (_val)) 6189 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL2r(_unit, _pc, _val) \ 6190 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008232, (_val)) 6191 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL2r(_unit, _pc, _val, _mask) \ 6192 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008232, (_val), (_mask)) 6193 6194 /* State Machine Control 3 Register */ 6195 #define READ_WC40_DSC4B0_TUNING_SM_CTRL3r(_unit, _pc, _val) \ 6196 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008233, (_val)) 6197 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL3r(_unit, _pc, _val) \ 6198 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008233, (_val)) 6199 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL3r(_unit, _pc, _val, _mask) \ 6200 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008233, (_val), (_mask)) 6201 6202 /* State Machine Control 4 Register */ 6203 #define READ_WC40_DSC4B0_TUNING_SM_CTRL4r(_unit, _pc, _val) \ 6204 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008234, (_val)) 6205 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL4r(_unit, _pc, _val) \ 6206 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008234, (_val)) 6207 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL4r(_unit, _pc, _val, _mask) \ 6208 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008234, (_val), (_mask)) 6209 6210 /* State Machine Control 5 Register */ 6211 #define READ_WC40_DSC4B0_TUNING_SM_CTRL5r(_unit, _pc, _val) \ 6212 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008235, (_val)) 6213 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL5r(_unit, _pc, _val) \ 6214 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008235, (_val)) 6215 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL5r(_unit, _pc, _val, _mask) \ 6216 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008235, (_val), (_mask)) 6217 6218 /* State Machine Control 6 Register */ 6219 #define READ_WC40_DSC4B0_TUNING_SM_CTRL6r(_unit, _pc, _val) \ 6220 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008236, (_val)) 6221 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL6r(_unit, _pc, _val) \ 6222 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008236, (_val)) 6223 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL6r(_unit, _pc, _val, _mask) \ 6224 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008236, (_val), (_mask)) 6225 6226 /* State Machine Control 7 Register */ 6227 #define READ_WC40_DSC4B0_TUNING_SM_CTRL7r(_unit, _pc, _val) \ 6228 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008237, (_val)) 6229 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL7r(_unit, _pc, _val) \ 6230 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008237, (_val)) 6231 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL7r(_unit, _pc, _val, _mask) \ 6232 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008237, (_val), (_mask)) 6233 6234 /* State Machine Control 8 Register */ 6235 #define READ_WC40_DSC4B0_TUNING_SM_CTRL8r(_unit, _pc, _val) \ 6236 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008238, (_val)) 6237 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL8r(_unit, _pc, _val) \ 6238 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008238, (_val)) 6239 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL8r(_unit, _pc, _val, _mask) \ 6240 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008238, (_val), (_mask)) 6241 6242 /* State Machine Control 9 Register */ 6243 #define READ_WC40_DSC4B0_TUNING_SM_CTRL9r(_unit, _pc, _val) \ 6244 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008239, (_val)) 6245 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL9r(_unit, _pc, _val) \ 6246 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008239, (_val)) 6247 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL9r(_unit, _pc, _val, _mask) \ 6248 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008239, (_val), (_mask)) 6249 6250 /* State Machine Control 10 Register */ 6251 #define READ_WC40_DSC4B0_TUNING_SM_CTRL10r(_unit, _pc, _val) \ 6252 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000823a, (_val)) 6253 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL10r(_unit, _pc, _val) \ 6254 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000823a, (_val)) 6255 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL10r(_unit, _pc, _val, _mask) \ 6256 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823a, (_val), (_mask)) 6257 6258 /* State Machine Control 11 Register */ 6259 #define READ_WC40_DSC4B0_TUNING_SM_CTRL11r(_unit, _pc, _val) \ 6260 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000823b, (_val)) 6261 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL11r(_unit, _pc, _val) \ 6262 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000823b, (_val)) 6263 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL11r(_unit, _pc, _val, _mask) \ 6264 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823b, (_val), (_mask)) 6265 6266 /* Acquisition State Machine Control 9 Register */ 6267 #define READ_WC40_DSC4B0_ACQ_SM_CTRL9r(_unit, _pc, _val) \ 6268 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000823c, (_val)) 6269 #define WRITE_WC40_DSC4B0_ACQ_SM_CTRL9r(_unit, _pc, _val) \ 6270 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000823c, (_val)) 6271 #define MODIFY_WC40_DSC4B0_ACQ_SM_CTRL9r(_unit, _pc, _val, _mask) \ 6272 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823c, (_val), (_mask)) 6273 6274 /* Acquisition State Machine Control 10 Register */ 6275 #define READ_WC40_DSC4B0_ACQ_SM_CTRL10r(_unit, _pc, _val) \ 6276 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000823d, (_val)) 6277 #define WRITE_WC40_DSC4B0_ACQ_SM_CTRL10r(_unit, _pc, _val) \ 6278 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000823d, (_val)) 6279 #define MODIFY_WC40_DSC4B0_ACQ_SM_CTRL10r(_unit, _pc, _val, _mask) \ 6280 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823d, (_val), (_mask)) 6281 6282 /* Acquisition State Machine Control 11 Register */ 6283 #define READ_WC40_DSC4B0_ACQ_SM_CTRL11r(_unit, _pc, _val) \ 6284 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000823e, (_val)) 6285 #define WRITE_WC40_DSC4B0_ACQ_SM_CTRL11r(_unit, _pc, _val) \ 6286 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000823e, (_val)) 6287 #define MODIFY_WC40_DSC4B0_ACQ_SM_CTRL11r(_unit, _pc, _val, _mask) \ 6288 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823e, (_val), (_mask)) 6289 6290 6291 6292 /**************************************************************************** 6293 * Warpcore_USER_Dsc5b0 6294 */ 6295 /* State Machine Status 0 Register */ 6296 #define READ_WC40_DSC5B0_TUNING_SM_STATUS0r(_unit, _pc, _val) \ 6297 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008240, (_val)) 6298 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS0r(_unit, _pc, _val) \ 6299 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008240, (_val)) 6300 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS0r(_unit, _pc, _val, _mask) \ 6301 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008240, (_val), (_mask)) 6302 6303 /* State Machine Status 1 Register */ 6304 #define READ_WC40_DSC5B0_TUNING_SM_STATUS1r(_unit, _pc, _val) \ 6305 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008241, (_val)) 6306 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS1r(_unit, _pc, _val) \ 6307 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008241, (_val)) 6308 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS1r(_unit, _pc, _val, _mask) \ 6309 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008241, (_val), (_mask)) 6310 6311 /* State Machine Status 2 Register */ 6312 #define READ_WC40_DSC5B0_TUNING_SM_STATUS2r(_unit, _pc, _val) \ 6313 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008242, (_val)) 6314 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS2r(_unit, _pc, _val) \ 6315 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008242, (_val)) 6316 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS2r(_unit, _pc, _val, _mask) \ 6317 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008242, (_val), (_mask)) 6318 6319 /* State Machine Status 3 Register */ 6320 #define READ_WC40_DSC5B0_TUNING_SM_STATUS3r(_unit, _pc, _val) \ 6321 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008243, (_val)) 6322 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS3r(_unit, _pc, _val) \ 6323 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008243, (_val)) 6324 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS3r(_unit, _pc, _val, _mask) \ 6325 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008243, (_val), (_mask)) 6326 6327 /* State Machine Status 4 Register */ 6328 #define READ_WC40_DSC5B0_TUNING_SM_STATUS4r(_unit, _pc, _val) \ 6329 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008244, (_val)) 6330 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS4r(_unit, _pc, _val) \ 6331 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008244, (_val)) 6332 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS4r(_unit, _pc, _val, _mask) \ 6333 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008244, (_val), (_mask)) 6334 6335 /* State Machine Status 5 Register */ 6336 #define READ_WC40_DSC5B0_TUNING_SM_STATUS5r(_unit, _pc, _val) \ 6337 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008245, (_val)) 6338 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS5r(_unit, _pc, _val) \ 6339 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008245, (_val)) 6340 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS5r(_unit, _pc, _val, _mask) \ 6341 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008245, (_val), (_mask)) 6342 6343 /* State Machine Status 6 Register */ 6344 #define READ_WC40_DSC5B0_TUNING_SM_STATUS6r(_unit, _pc, _val) \ 6345 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008246, (_val)) 6346 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS6r(_unit, _pc, _val) \ 6347 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008246, (_val)) 6348 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS6r(_unit, _pc, _val, _mask) \ 6349 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008246, (_val), (_mask)) 6350 6351 6352 6353 /**************************************************************************** 6354 * Warpcore_USER_Dsc6b0 6355 */ 6356 /* CDR Lock Monitor Control 0 Register */ 6357 #define READ_WC40_DSC6B0_CDR_LM_CTRL_0r(_unit, _pc, _val) \ 6358 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008250, (_val)) 6359 #define WRITE_WC40_DSC6B0_CDR_LM_CTRL_0r(_unit, _pc, _val) \ 6360 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008250, (_val)) 6361 #define MODIFY_WC40_DSC6B0_CDR_LM_CTRL_0r(_unit, _pc, _val, _mask) \ 6362 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008250, (_val), (_mask)) 6363 6364 6365 6366 /**************************************************************************** 6367 * Warpcore_USER_CL72_UserB0 6368 */ 6369 /* CL72 TX Coefficient Update Register */ 6370 #define READ_WC40_CL72_USERB0_CL72_XMT_CONTROL_REGISTERr(_unit, _pc, _val) \ 6371 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082e0, (_val)) 6372 #define WRITE_WC40_CL72_USERB0_CL72_XMT_CONTROL_REGISTERr(_unit, _pc, _val) \ 6373 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082e0, (_val)) 6374 #define MODIFY_WC40_CL72_USERB0_CL72_XMT_CONTROL_REGISTERr(_unit, _pc, _val, _mask) \ 6375 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e0, (_val), (_mask)) 6376 6377 /* CL72 Status Report Register */ 6378 #define READ_WC40_CL72_USERB0_CL72_RCVD_STATUS_REGISTERr(_unit, _pc, _val) \ 6379 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082e1, (_val)) 6380 #define WRITE_WC40_CL72_USERB0_CL72_RCVD_STATUS_REGISTERr(_unit, _pc, _val) \ 6381 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082e1, (_val)) 6382 #define MODIFY_WC40_CL72_USERB0_CL72_RCVD_STATUS_REGISTERr(_unit, _pc, _val, _mask) \ 6383 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e1, (_val), (_mask)) 6384 6385 /* CL72 TX FIR Tap Register */ 6386 #define READ_WC40_CL72_USERB0_CL72_TX_FIR_TAP_REGISTERr(_unit, _pc, _val) \ 6387 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082e2, (_val)) 6388 #define WRITE_WC40_CL72_USERB0_CL72_TX_FIR_TAP_REGISTERr(_unit, _pc, _val) \ 6389 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082e2, (_val)) 6390 #define MODIFY_WC40_CL72_USERB0_CL72_TX_FIR_TAP_REGISTERr(_unit, _pc, _val, _mask) \ 6391 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e2, (_val), (_mask)) 6392 6393 /* CL72 Miscellaneous_1 Control Register */ 6394 #define READ_WC40_CL72_USERB0_CL72_MISC1_CONTROLr(_unit, _pc, _val) \ 6395 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082e3, (_val)) 6396 #define WRITE_WC40_CL72_USERB0_CL72_MISC1_CONTROLr(_unit, _pc, _val) \ 6397 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082e3, (_val)) 6398 #define MODIFY_WC40_CL72_USERB0_CL72_MISC1_CONTROLr(_unit, _pc, _val, _mask) \ 6399 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e3, (_val), (_mask)) 6400 6401 /* CL72 Miscellaneous_2 Control Register */ 6402 #define READ_WC40_CL72_USERB0_CL72_MISC2_CONTROLr(_unit, _pc, _val) \ 6403 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082e4, (_val)) 6404 #define WRITE_WC40_CL72_USERB0_CL72_MISC2_CONTROLr(_unit, _pc, _val) \ 6405 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082e4, (_val)) 6406 #define MODIFY_WC40_CL72_USERB0_CL72_MISC2_CONTROLr(_unit, _pc, _val, _mask) \ 6407 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e4, (_val), (_mask)) 6408 6409 /* CL72 KR Default Control Register */ 6410 #define READ_WC40_CL72_USERB0_CL72_KR_DEFAULT_CONTROLr(_unit, _pc, _val) \ 6411 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082e5, (_val)) 6412 #define WRITE_WC40_CL72_USERB0_CL72_KR_DEFAULT_CONTROLr(_unit, _pc, _val) \ 6413 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082e5, (_val)) 6414 #define MODIFY_WC40_CL72_USERB0_CL72_KR_DEFAULT_CONTROLr(_unit, _pc, _val, _mask) \ 6415 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e5, (_val), (_mask)) 6416 6417 /* CL72 OS Default Control Register */ 6418 #define READ_WC40_CL72_USERB0_CL72_OS_DEFAULT_CONTROLr(_unit, _pc, _val) \ 6419 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082e6, (_val)) 6420 #define WRITE_WC40_CL72_USERB0_CL72_OS_DEFAULT_CONTROLr(_unit, _pc, _val) \ 6421 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082e6, (_val)) 6422 #define MODIFY_WC40_CL72_USERB0_CL72_OS_DEFAULT_CONTROLr(_unit, _pc, _val, _mask) \ 6423 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e6, (_val), (_mask)) 6424 6425 /* CL72 BR Default Control Register */ 6426 #define READ_WC40_CL72_USERB0_CL72_BR_DEFAULT_CONTROLr(_unit, _pc, _val) \ 6427 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082e7, (_val)) 6428 #define WRITE_WC40_CL72_USERB0_CL72_BR_DEFAULT_CONTROLr(_unit, _pc, _val) \ 6429 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082e7, (_val)) 6430 #define MODIFY_WC40_CL72_USERB0_CL72_BR_DEFAULT_CONTROLr(_unit, _pc, _val, _mask) \ 6431 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e7, (_val), (_mask)) 6432 6433 /* CL72 2p5 Default Control Register */ 6434 #define READ_WC40_CL72_USERB0_CL72_2P5_DEFAULT_CONTROLr(_unit, _pc, _val) \ 6435 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082e8, (_val)) 6436 #define WRITE_WC40_CL72_USERB0_CL72_2P5_DEFAULT_CONTROLr(_unit, _pc, _val) \ 6437 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082e8, (_val)) 6438 #define MODIFY_WC40_CL72_USERB0_CL72_2P5_DEFAULT_CONTROLr(_unit, _pc, _val, _mask) \ 6439 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e8, (_val), (_mask)) 6440 6441 /* CL72 Tap Limit Control Register */ 6442 #define READ_WC40_CL72_USERB0_CL72_TAP_LIMIT_CONTROLr(_unit, _pc, _val) \ 6443 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082e9, (_val)) 6444 #define WRITE_WC40_CL72_USERB0_CL72_TAP_LIMIT_CONTROLr(_unit, _pc, _val) \ 6445 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082e9, (_val)) 6446 #define MODIFY_WC40_CL72_USERB0_CL72_TAP_LIMIT_CONTROLr(_unit, _pc, _val, _mask) \ 6447 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e9, (_val), (_mask)) 6448 6449 /* CL72 Miscellaneous_3 Control Register */ 6450 #define READ_WC40_CL72_USERB0_CL72_MISC3_CONTROLr(_unit, _pc, _val) \ 6451 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082ea, (_val)) 6452 #define WRITE_WC40_CL72_USERB0_CL72_MISC3_CONTROLr(_unit, _pc, _val) \ 6453 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082ea, (_val)) 6454 #define MODIFY_WC40_CL72_USERB0_CL72_MISC3_CONTROLr(_unit, _pc, _val, _mask) \ 6455 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ea, (_val), (_mask)) 6456 6457 /* CL72 Tap Present Control Register */ 6458 #define READ_WC40_CL72_USERB0_CL72_TAP_PRESET_CONTROLr(_unit, _pc, _val) \ 6459 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082eb, (_val)) 6460 #define WRITE_WC40_CL72_USERB0_CL72_TAP_PRESET_CONTROLr(_unit, _pc, _val) \ 6461 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082eb, (_val)) 6462 #define MODIFY_WC40_CL72_USERB0_CL72_TAP_PRESET_CONTROLr(_unit, _pc, _val, _mask) \ 6463 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082eb, (_val), (_mask)) 6464 6465 /* CL72 Miscellaneous_4 Control Register */ 6466 #define READ_WC40_CL72_USERB0_CL72_MISC4_CONTROLr(_unit, _pc, _val) \ 6467 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082ec, (_val)) 6468 #define WRITE_WC40_CL72_USERB0_CL72_MISC4_CONTROLr(_unit, _pc, _val) \ 6469 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082ec, (_val)) 6470 #define MODIFY_WC40_CL72_USERB0_CL72_MISC4_CONTROLr(_unit, _pc, _val, _mask) \ 6471 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ec, (_val), (_mask)) 6472 6473 6474 6475 /**************************************************************************** 6476 * Warpcore_USER_CL72_UserB1 6477 */ 6478 /* CL72 Fault Register */ 6479 #define READ_WC40_CL72_USERB1_CL72_FAULT_REGISTERr(_unit, _pc, _val) \ 6480 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082f9, (_val)) 6481 #define WRITE_WC40_CL72_USERB1_CL72_FAULT_REGISTERr(_unit, _pc, _val) \ 6482 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082f9, (_val)) 6483 #define MODIFY_WC40_CL72_USERB1_CL72_FAULT_REGISTERr(_unit, _pc, _val, _mask) \ 6484 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f9, (_val), (_mask)) 6485 6486 /* CL72 Debug 1 Register */ 6487 #define READ_WC40_CL72_USERB1_CL72_DEBUG_1_REGISTERr(_unit, _pc, _val) \ 6488 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082fb, (_val)) 6489 #define WRITE_WC40_CL72_USERB1_CL72_DEBUG_1_REGISTERr(_unit, _pc, _val) \ 6490 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082fb, (_val)) 6491 #define MODIFY_WC40_CL72_USERB1_CL72_DEBUG_1_REGISTERr(_unit, _pc, _val, _mask) \ 6492 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fb, (_val), (_mask)) 6493 6494 /* CL72 Debug 2 Register */ 6495 #define READ_WC40_CL72_USERB1_CL72_DEBUG_2_REGISTERr(_unit, _pc, _val) \ 6496 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082fc, (_val)) 6497 #define WRITE_WC40_CL72_USERB1_CL72_DEBUG_2_REGISTERr(_unit, _pc, _val) \ 6498 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082fc, (_val)) 6499 #define MODIFY_WC40_CL72_USERB1_CL72_DEBUG_2_REGISTERr(_unit, _pc, _val, _mask) \ 6500 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fc, (_val), (_mask)) 6501 6502 /* CL72 Debug 3 Register */ 6503 #define READ_WC40_CL72_USERB1_CL72_DEBUG_3_REGISTERr(_unit, _pc, _val) \ 6504 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082fd, (_val)) 6505 #define WRITE_WC40_CL72_USERB1_CL72_DEBUG_3_REGISTERr(_unit, _pc, _val) \ 6506 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082fd, (_val)) 6507 #define MODIFY_WC40_CL72_USERB1_CL72_DEBUG_3_REGISTERr(_unit, _pc, _val, _mask) \ 6508 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fd, (_val), (_mask)) 6509 6510 /* CL72 Debug 4 Register */ 6511 #define READ_WC40_CL72_USERB1_CL72_DEBUG_4_REGISTERr(_unit, _pc, _val) \ 6512 WC40_REG_READ((_unit), (_pc), 0x00, 0x000082fe, (_val)) 6513 #define WRITE_WC40_CL72_USERB1_CL72_DEBUG_4_REGISTERr(_unit, _pc, _val) \ 6514 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000082fe, (_val)) 6515 #define MODIFY_WC40_CL72_USERB1_CL72_DEBUG_4_REGISTERr(_unit, _pc, _val, _mask) \ 6516 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fe, (_val), (_mask)) 6517 6518 6519 6520 /**************************************************************************** 6521 * Warpcore_USER_SerdesDigital 6522 */ 6523 /* 1000X control 1 register */ 6524 #define READ_WC40_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _val) \ 6525 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008300, (_val)) 6526 #define WRITE_WC40_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _val) \ 6527 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008300, (_val)) 6528 #define MODIFY_WC40_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _val, _mask) \ 6529 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008300, (_val), (_mask)) 6530 6531 /* 1000X control 2 register */ 6532 #define READ_WC40_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val) \ 6533 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008301, (_val)) 6534 #define WRITE_WC40_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val) \ 6535 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008301, (_val)) 6536 #define MODIFY_WC40_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val, _mask) \ 6537 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008301, (_val), (_mask)) 6538 6539 /* 1000X control 3 register */ 6540 #define READ_WC40_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _val) \ 6541 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008302, (_val)) 6542 #define WRITE_WC40_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _val) \ 6543 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008302, (_val)) 6544 #define MODIFY_WC40_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _val, _mask) \ 6545 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008302, (_val), (_mask)) 6546 6547 /* 1000X control 4 register */ 6548 #define READ_WC40_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _val) \ 6549 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008303, (_val)) 6550 #define WRITE_WC40_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _val) \ 6551 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008303, (_val)) 6552 #define MODIFY_WC40_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _val, _mask) \ 6553 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008303, (_val), (_mask)) 6554 6555 /* 1000X status 1 register */ 6556 #define READ_WC40_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _val) \ 6557 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008304, (_val)) 6558 #define WRITE_WC40_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _val) \ 6559 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008304, (_val)) 6560 #define MODIFY_WC40_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _val, _mask) \ 6561 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008304, (_val), (_mask)) 6562 6563 /* 1000X status 2 register */ 6564 #define READ_WC40_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _val) \ 6565 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008305, (_val)) 6566 #define WRITE_WC40_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _val) \ 6567 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008305, (_val)) 6568 #define MODIFY_WC40_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _val, _mask) \ 6569 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008305, (_val), (_mask)) 6570 6571 /* 1000X status 3 register */ 6572 #define READ_WC40_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _val) \ 6573 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008306, (_val)) 6574 #define WRITE_WC40_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _val) \ 6575 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008306, (_val)) 6576 #define MODIFY_WC40_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _val, _mask) \ 6577 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008306, (_val), (_mask)) 6578 6579 /* Invalid code group count register */ 6580 #define READ_WC40_SERDESDIGITAL_BADCODEGROUPr(_unit, _pc, _val) \ 6581 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008307, (_val)) 6582 #define WRITE_WC40_SERDESDIGITAL_BADCODEGROUPr(_unit, _pc, _val) \ 6583 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008307, (_val)) 6584 #define MODIFY_WC40_SERDESDIGITAL_BADCODEGROUPr(_unit, _pc, _val, _mask) \ 6585 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008307, (_val), (_mask)) 6586 6587 /* Miscellaneous 1 control register */ 6588 #define READ_WC40_SERDESDIGITAL_MISC1r(_unit, _pc, _val) \ 6589 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008308, (_val)) 6590 #define WRITE_WC40_SERDESDIGITAL_MISC1r(_unit, _pc, _val) \ 6591 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008308, (_val)) 6592 #define MODIFY_WC40_SERDESDIGITAL_MISC1r(_unit, _pc, _val, _mask) \ 6593 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008308, (_val), (_mask)) 6594 6595 /* Miscellaneous 2 control register */ 6596 #define READ_WC40_SERDESDIGITAL_MISC2r(_unit, _pc, _val) \ 6597 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008309, (_val)) 6598 #define WRITE_WC40_SERDESDIGITAL_MISC2r(_unit, _pc, _val) \ 6599 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008309, (_val)) 6600 #define MODIFY_WC40_SERDESDIGITAL_MISC2r(_unit, _pc, _val, _mask) \ 6601 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008309, (_val), (_mask)) 6602 6603 /* Pattern generator control register */ 6604 #define READ_WC40_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _val) \ 6605 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000830a, (_val)) 6606 #define WRITE_WC40_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _val) \ 6607 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000830a, (_val)) 6608 #define MODIFY_WC40_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _val, _mask) \ 6609 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830a, (_val), (_mask)) 6610 6611 /* Pattern generator status register */ 6612 #define READ_WC40_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _val) \ 6613 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000830b, (_val)) 6614 #define WRITE_WC40_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _val) \ 6615 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000830b, (_val)) 6616 #define MODIFY_WC40_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _val, _mask) \ 6617 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830b, (_val), (_mask)) 6618 6619 /* Test mode register */ 6620 #define READ_WC40_SERDESDIGITAL_TESTMODEr(_unit, _pc, _val) \ 6621 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000830c, (_val)) 6622 #define WRITE_WC40_SERDESDIGITAL_TESTMODEr(_unit, _pc, _val) \ 6623 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000830c, (_val)) 6624 #define MODIFY_WC40_SERDESDIGITAL_TESTMODEr(_unit, _pc, _val, _mask) \ 6625 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830c, (_val), (_mask)) 6626 6627 /* Tx packet count register */ 6628 #define READ_WC40_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _val) \ 6629 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000830d, (_val)) 6630 #define WRITE_WC40_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _val) \ 6631 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000830d, (_val)) 6632 #define MODIFY_WC40_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _val, _mask) \ 6633 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830d, (_val), (_mask)) 6634 6635 /* Rx packet count register */ 6636 #define READ_WC40_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _val) \ 6637 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000830e, (_val)) 6638 #define WRITE_WC40_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _val) \ 6639 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000830e, (_val)) 6640 #define MODIFY_WC40_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _val, _mask) \ 6641 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830e, (_val), (_mask)) 6642 6643 6644 6645 /**************************************************************************** 6646 * Warpcore_USER_SerdesID 6647 */ 6648 /* Serdes ID 0 register */ 6649 #define READ_WC40_SERDESID_SERDESID0r(_unit, _pc, _val) \ 6650 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008310, (_val)) 6651 #define WRITE_WC40_SERDESID_SERDESID0r(_unit, _pc, _val) \ 6652 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008310, (_val)) 6653 #define MODIFY_WC40_SERDESID_SERDESID0r(_unit, _pc, _val, _mask) \ 6654 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008310, (_val), (_mask)) 6655 6656 /* Serdes ID 1 register */ 6657 #define READ_WC40_SERDESID_SERDESID1r(_unit, _pc, _val) \ 6658 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008311, (_val)) 6659 #define WRITE_WC40_SERDESID_SERDESID1r(_unit, _pc, _val) \ 6660 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008311, (_val)) 6661 #define MODIFY_WC40_SERDESID_SERDESID1r(_unit, _pc, _val, _mask) \ 6662 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008311, (_val), (_mask)) 6663 6664 /* Serdes ID 2 register */ 6665 #define READ_WC40_SERDESID_SERDESID2r(_unit, _pc, _val) \ 6666 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008312, (_val)) 6667 #define WRITE_WC40_SERDESID_SERDESID2r(_unit, _pc, _val) \ 6668 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008312, (_val)) 6669 #define MODIFY_WC40_SERDESID_SERDESID2r(_unit, _pc, _val, _mask) \ 6670 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008312, (_val), (_mask)) 6671 6672 /* Serdes ID 3 register */ 6673 #define READ_WC40_SERDESID_SERDESID3r(_unit, _pc, _val) \ 6674 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008313, (_val)) 6675 #define WRITE_WC40_SERDESID_SERDESID3r(_unit, _pc, _val) \ 6676 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008313, (_val)) 6677 #define MODIFY_WC40_SERDESID_SERDESID3r(_unit, _pc, _val, _mask) \ 6678 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008313, (_val), (_mask)) 6679 6680 /* Serdes ID 4 register */ 6681 #define READ_WC40_SERDESID_SERDESID4r(_unit, _pc, _val) \ 6682 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008314, (_val)) 6683 #define WRITE_WC40_SERDESID_SERDESID4r(_unit, _pc, _val) \ 6684 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008314, (_val)) 6685 #define MODIFY_WC40_SERDESID_SERDESID4r(_unit, _pc, _val, _mask) \ 6686 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008314, (_val), (_mask)) 6687 6688 6689 6690 /**************************************************************************** 6691 * Warpcore_USER_Digital3 6692 */ 6693 /* AN lost link count time, bits 15:0 */ 6694 #define READ_WC40_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _val) \ 6695 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008320, (_val)) 6696 #define WRITE_WC40_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _val) \ 6697 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008320, (_val)) 6698 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _val, _mask) \ 6699 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008320, (_val), (_mask)) 6700 6701 /* AN switch count time, bits 15:0 */ 6702 #define READ_WC40_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _val) \ 6703 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008321, (_val)) 6704 #define WRITE_WC40_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _val) \ 6705 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008321, (_val)) 6706 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _val, _mask) \ 6707 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008321, (_val), (_mask)) 6708 6709 /* AN link count time, bits 15:0 */ 6710 #define READ_WC40_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _val) \ 6711 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008322, (_val)) 6712 #define WRITE_WC40_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _val) \ 6713 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008322, (_val)) 6714 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _val, _mask) \ 6715 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008322, (_val), (_mask)) 6716 6717 /* AN switch count & link count time, bits 23:16 */ 6718 #define READ_WC40_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _val) \ 6719 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008323, (_val)) 6720 #define WRITE_WC40_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _val) \ 6721 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008323, (_val)) 6722 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _val, _mask) \ 6723 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008323, (_val), (_mask)) 6724 6725 /* Over 1G message page number & AN fail count timer */ 6726 #define READ_WC40_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _val) \ 6727 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008324, (_val)) 6728 #define WRITE_WC40_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _val) \ 6729 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008324, (_val)) 6730 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _val, _mask) \ 6731 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008324, (_val), (_mask)) 6732 6733 /* AN ignore link count time, bits 15:0 */ 6734 #define READ_WC40_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _val) \ 6735 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008325, (_val)) 6736 #define WRITE_WC40_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _val) \ 6737 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008325, (_val)) 6738 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _val, _mask) \ 6739 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008325, (_val), (_mask)) 6740 6741 /* AN lost link count & ignore link count time, bits 23:16 */ 6742 #define READ_WC40_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _val) \ 6743 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008326, (_val)) 6744 #define WRITE_WC40_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _val) \ 6745 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008326, (_val)) 6746 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _val, _mask) \ 6747 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008326, (_val), (_mask)) 6748 6749 /* Test port out bits 15:0, tpout[15:0] */ 6750 #define READ_WC40_DIGITAL3_TPOUT_1r(_unit, _pc, _val) \ 6751 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008327, (_val)) 6752 #define WRITE_WC40_DIGITAL3_TPOUT_1r(_unit, _pc, _val) \ 6753 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008327, (_val)) 6754 #define MODIFY_WC40_DIGITAL3_TPOUT_1r(_unit, _pc, _val, _mask) \ 6755 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008327, (_val), (_mask)) 6756 6757 /* Test port out bits 23:8, tpout[23:8] */ 6758 #define READ_WC40_DIGITAL3_TPOUT_2r(_unit, _pc, _val) \ 6759 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008328, (_val)) 6760 #define WRITE_WC40_DIGITAL3_TPOUT_2r(_unit, _pc, _val) \ 6761 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008328, (_val)) 6762 #define MODIFY_WC40_DIGITAL3_TPOUT_2r(_unit, _pc, _val, _mask) \ 6763 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008328, (_val), (_mask)) 6764 6765 /* AN local device user page 1 */ 6766 #define READ_WC40_DIGITAL3_UP1r(_unit, _pc, _val) \ 6767 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008329, (_val)) 6768 #define WRITE_WC40_DIGITAL3_UP1r(_unit, _pc, _val) \ 6769 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008329, (_val)) 6770 #define MODIFY_WC40_DIGITAL3_UP1r(_unit, _pc, _val, _mask) \ 6771 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008329, (_val), (_mask)) 6772 6773 /* AN local device user page 2 */ 6774 #define READ_WC40_DIGITAL3_UP2r(_unit, _pc, _val) \ 6775 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000832a, (_val)) 6776 #define WRITE_WC40_DIGITAL3_UP2r(_unit, _pc, _val) \ 6777 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000832a, (_val)) 6778 #define MODIFY_WC40_DIGITAL3_UP2r(_unit, _pc, _val, _mask) \ 6779 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832a, (_val), (_mask)) 6780 6781 /* AN local device user page 3 */ 6782 #define READ_WC40_DIGITAL3_UP3r(_unit, _pc, _val) \ 6783 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000832b, (_val)) 6784 #define WRITE_WC40_DIGITAL3_UP3r(_unit, _pc, _val) \ 6785 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000832b, (_val)) 6786 #define MODIFY_WC40_DIGITAL3_UP3r(_unit, _pc, _val, _mask) \ 6787 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832b, (_val), (_mask)) 6788 6789 /* AN link partner user page 1 */ 6790 #define READ_WC40_DIGITAL3_LP_UP1r(_unit, _pc, _val) \ 6791 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000832c, (_val)) 6792 #define WRITE_WC40_DIGITAL3_LP_UP1r(_unit, _pc, _val) \ 6793 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000832c, (_val)) 6794 #define MODIFY_WC40_DIGITAL3_LP_UP1r(_unit, _pc, _val, _mask) \ 6795 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832c, (_val), (_mask)) 6796 6797 /* AN link partner user page 2 */ 6798 #define READ_WC40_DIGITAL3_LP_UP2r(_unit, _pc, _val) \ 6799 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000832d, (_val)) 6800 #define WRITE_WC40_DIGITAL3_LP_UP2r(_unit, _pc, _val) \ 6801 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000832d, (_val)) 6802 #define MODIFY_WC40_DIGITAL3_LP_UP2r(_unit, _pc, _val, _mask) \ 6803 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832d, (_val), (_mask)) 6804 6805 /* AN link partner user page 3 */ 6806 #define READ_WC40_DIGITAL3_LP_UP3r(_unit, _pc, _val) \ 6807 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000832e, (_val)) 6808 #define WRITE_WC40_DIGITAL3_LP_UP3r(_unit, _pc, _val) \ 6809 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000832e, (_val)) 6810 #define MODIFY_WC40_DIGITAL3_LP_UP3r(_unit, _pc, _val, _mask) \ 6811 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832e, (_val), (_mask)) 6812 6813 6814 6815 /**************************************************************************** 6816 * Warpcore_USER_Digital4 6817 */ 6818 /* Miscellaneous Rx status register */ 6819 #define READ_WC40_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _val) \ 6820 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008330, (_val)) 6821 #define WRITE_WC40_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _val) \ 6822 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008330, (_val)) 6823 #define MODIFY_WC40_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _val, _mask) \ 6824 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008330, (_val), (_mask)) 6825 6826 /* Link partner basepage register */ 6827 #define READ_WC40_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _val) \ 6828 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008331, (_val)) 6829 #define WRITE_WC40_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _val) \ 6830 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008331, (_val)) 6831 #define MODIFY_WC40_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _val, _mask) \ 6832 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008331, (_val), (_mask)) 6833 6834 /* Link partner nextpage 0 register */ 6835 #define READ_WC40_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _val) \ 6836 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008332, (_val)) 6837 #define WRITE_WC40_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _val) \ 6838 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008332, (_val)) 6839 #define MODIFY_WC40_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _val, _mask) \ 6840 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008332, (_val), (_mask)) 6841 6842 /* Link partner nextpage 1 register */ 6843 #define READ_WC40_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _val) \ 6844 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008333, (_val)) 6845 #define WRITE_WC40_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _val) \ 6846 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008333, (_val)) 6847 #define MODIFY_WC40_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _val, _mask) \ 6848 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008333, (_val), (_mask)) 6849 6850 /* Link partner nextpage 2 register */ 6851 #define READ_WC40_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _val) \ 6852 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008334, (_val)) 6853 #define WRITE_WC40_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _val) \ 6854 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008334, (_val)) 6855 #define MODIFY_WC40_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _val, _mask) \ 6856 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008334, (_val), (_mask)) 6857 6858 /* Link partner nextpage 3 register */ 6859 #define READ_WC40_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _val) \ 6860 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008335, (_val)) 6861 #define WRITE_WC40_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _val) \ 6862 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008335, (_val)) 6863 #define MODIFY_WC40_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _val, _mask) \ 6864 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008335, (_val), (_mask)) 6865 6866 /* Link partner nextpage 4 register */ 6867 #define READ_WC40_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _val) \ 6868 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008336, (_val)) 6869 #define WRITE_WC40_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _val) \ 6870 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008336, (_val)) 6871 #define MODIFY_WC40_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _val, _mask) \ 6872 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008336, (_val), (_mask)) 6873 6874 /* Remote phy nextpage 0 register */ 6875 #define READ_WC40_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _val) \ 6876 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008337, (_val)) 6877 #define WRITE_WC40_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _val) \ 6878 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008337, (_val)) 6879 #define MODIFY_WC40_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _val, _mask) \ 6880 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008337, (_val), (_mask)) 6881 6882 /* Remote phy nextpage 1 register */ 6883 #define READ_WC40_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _val) \ 6884 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008338, (_val)) 6885 #define WRITE_WC40_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _val) \ 6886 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008338, (_val)) 6887 #define MODIFY_WC40_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _val, _mask) \ 6888 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008338, (_val), (_mask)) 6889 6890 /* Remote phy nextpage 2 register */ 6891 #define READ_WC40_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _val) \ 6892 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008339, (_val)) 6893 #define WRITE_WC40_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _val) \ 6894 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008339, (_val)) 6895 #define MODIFY_WC40_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _val, _mask) \ 6896 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008339, (_val), (_mask)) 6897 6898 /* Remote phy nextpage 3 register */ 6899 #define READ_WC40_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _val) \ 6900 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000833a, (_val)) 6901 #define WRITE_WC40_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _val) \ 6902 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000833a, (_val)) 6903 #define MODIFY_WC40_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _val, _mask) \ 6904 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833a, (_val), (_mask)) 6905 6906 /* Remote phy nextpage 4 register */ 6907 #define READ_WC40_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _val) \ 6908 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000833b, (_val)) 6909 #define WRITE_WC40_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _val) \ 6910 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000833b, (_val)) 6911 #define MODIFY_WC40_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _val, _mask) \ 6912 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833b, (_val), (_mask)) 6913 6914 /* Miscellaneous 3 control register */ 6915 #define READ_WC40_DIGITAL4_MISC3r(_unit, _pc, _val) \ 6916 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000833c, (_val)) 6917 #define WRITE_WC40_DIGITAL4_MISC3r(_unit, _pc, _val) \ 6918 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000833c, (_val)) 6919 #define MODIFY_WC40_DIGITAL4_MISC3r(_unit, _pc, _val, _mask) \ 6920 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833c, (_val), (_mask)) 6921 6922 /* Miscelaneous 4 control register */ 6923 #define READ_WC40_DIGITAL4_MISC4r(_unit, _pc, _val) \ 6924 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000833d, (_val)) 6925 #define WRITE_WC40_DIGITAL4_MISC4r(_unit, _pc, _val) \ 6926 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000833d, (_val)) 6927 #define MODIFY_WC40_DIGITAL4_MISC4r(_unit, _pc, _val, _mask) \ 6928 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833d, (_val), (_mask)) 6929 6930 /* Miscelaneous 5 control register */ 6931 #define READ_WC40_DIGITAL4_MISC5r(_unit, _pc, _val) \ 6932 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000833e, (_val)) 6933 #define WRITE_WC40_DIGITAL4_MISC5r(_unit, _pc, _val) \ 6934 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000833e, (_val)) 6935 #define MODIFY_WC40_DIGITAL4_MISC5r(_unit, _pc, _val, _mask) \ 6936 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833e, (_val), (_mask)) 6937 6938 6939 6940 /**************************************************************************** 6941 * Warpcore_USER_Digital5 6942 */ 6943 /* CL72 Link counter MSB [23:16] */ 6944 #define READ_WC40_DIGITAL5_LINKCNT_CL72_MSBr(_unit, _pc, _val) \ 6945 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008340, (_val)) 6946 #define WRITE_WC40_DIGITAL5_LINKCNT_CL72_MSBr(_unit, _pc, _val) \ 6947 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008340, (_val)) 6948 #define MODIFY_WC40_DIGITAL5_LINKCNT_CL72_MSBr(_unit, _pc, _val, _mask) \ 6949 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008340, (_val), (_mask)) 6950 6951 /* CL72 Link counter LSB [15:0] */ 6952 #define READ_WC40_DIGITAL5_LINKCNT_CL72_LSBr(_unit, _pc, _val) \ 6953 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008341, (_val)) 6954 #define WRITE_WC40_DIGITAL5_LINKCNT_CL72_LSBr(_unit, _pc, _val) \ 6955 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008341, (_val)) 6956 #define MODIFY_WC40_DIGITAL5_LINKCNT_CL72_LSBr(_unit, _pc, _val, _mask) \ 6957 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008341, (_val), (_mask)) 6958 6959 /* Link Partner's UP4 page */ 6960 #define READ_WC40_DIGITAL5_LP_UP4r(_unit, _pc, _val) \ 6961 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008342, (_val)) 6962 #define WRITE_WC40_DIGITAL5_LP_UP4r(_unit, _pc, _val) \ 6963 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008342, (_val)) 6964 #define MODIFY_WC40_DIGITAL5_LP_UP4r(_unit, _pc, _val, _mask) \ 6965 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008342, (_val), (_mask)) 6966 6967 /* Link Partner's UP5 page */ 6968 #define READ_WC40_DIGITAL5_LP_UP5r(_unit, _pc, _val) \ 6969 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008343, (_val)) 6970 #define WRITE_WC40_DIGITAL5_LP_UP5r(_unit, _pc, _val) \ 6971 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008343, (_val)) 6972 #define MODIFY_WC40_DIGITAL5_LP_UP5r(_unit, _pc, _val, _mask) \ 6973 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008343, (_val), (_mask)) 6974 6975 /* LPI hysteresis control */ 6976 #define READ_WC40_DIGITAL5_LPI_HYSTr(_unit, _pc, _val) \ 6977 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008344, (_val)) 6978 #define WRITE_WC40_DIGITAL5_LPI_HYSTr(_unit, _pc, _val) \ 6979 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008344, (_val)) 6980 #define MODIFY_WC40_DIGITAL5_LPI_HYSTr(_unit, _pc, _val, _mask) \ 6981 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008344, (_val), (_mask)) 6982 6983 /* Misc6 */ 6984 #define READ_WC40_DIGITAL5_MISC6r(_unit, _pc, _val) \ 6985 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008345, (_val)) 6986 #define WRITE_WC40_DIGITAL5_MISC6r(_unit, _pc, _val) \ 6987 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008345, (_val)) 6988 #define MODIFY_WC40_DIGITAL5_MISC6r(_unit, _pc, _val, _mask) \ 6989 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008345, (_val), (_mask)) 6990 6991 /* parDetINDStatus */ 6992 #define READ_WC40_DIGITAL5_PARDETINDSTATUSr(_unit, _pc, _val) \ 6993 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008346, (_val)) 6994 #define WRITE_WC40_DIGITAL5_PARDETINDSTATUSr(_unit, _pc, _val) \ 6995 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008346, (_val)) 6996 #define MODIFY_WC40_DIGITAL5_PARDETINDSTATUSr(_unit, _pc, _val, _mask) \ 6997 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008346, (_val), (_mask)) 6998 6999 /* parDetINDControl1 */ 7000 #define READ_WC40_DIGITAL5_PARDETINDCONTROL1r(_unit, _pc, _val) \ 7001 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008347, (_val)) 7002 #define WRITE_WC40_DIGITAL5_PARDETINDCONTROL1r(_unit, _pc, _val) \ 7003 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008347, (_val)) 7004 #define MODIFY_WC40_DIGITAL5_PARDETINDCONTROL1r(_unit, _pc, _val, _mask) \ 7005 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008347, (_val), (_mask)) 7006 7007 /* parDetINDControl2 */ 7008 #define READ_WC40_DIGITAL5_PARDETINDCONTROL2r(_unit, _pc, _val) \ 7009 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008348, (_val)) 7010 #define WRITE_WC40_DIGITAL5_PARDETINDCONTROL2r(_unit, _pc, _val) \ 7011 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008348, (_val)) 7012 #define MODIFY_WC40_DIGITAL5_PARDETINDCONTROL2r(_unit, _pc, _val, _mask) \ 7013 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008348, (_val), (_mask)) 7014 7015 /* Misc7 */ 7016 #define READ_WC40_DIGITAL5_MISC7r(_unit, _pc, _val) \ 7017 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008349, (_val)) 7018 #define WRITE_WC40_DIGITAL5_MISC7r(_unit, _pc, _val) \ 7019 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008349, (_val)) 7020 #define MODIFY_WC40_DIGITAL5_MISC7r(_unit, _pc, _val, _mask) \ 7021 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008349, (_val), (_mask)) 7022 7023 /* link_status */ 7024 #define READ_WC40_DIGITAL5_LINK_STATUSr(_unit, _pc, _val) \ 7025 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000834d, (_val)) 7026 #define WRITE_WC40_DIGITAL5_LINK_STATUSr(_unit, _pc, _val) \ 7027 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000834d, (_val)) 7028 #define MODIFY_WC40_DIGITAL5_LINK_STATUSr(_unit, _pc, _val, _mask) \ 7029 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000834d, (_val), (_mask)) 7030 7031 /* Actual Speed status */ 7032 #define READ_WC40_DIGITAL5_ACTUAL_SPEEDr(_unit, _pc, _val) \ 7033 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000834e, (_val)) 7034 #define WRITE_WC40_DIGITAL5_ACTUAL_SPEEDr(_unit, _pc, _val) \ 7035 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000834e, (_val)) 7036 #define MODIFY_WC40_DIGITAL5_ACTUAL_SPEEDr(_unit, _pc, _val, _mask) \ 7037 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000834e, (_val), (_mask)) 7038 7039 7040 7041 /**************************************************************************** 7042 * Warpcore_USER_Digital6 7043 */ 7044 /* MP5, Message Page 5, next page control register */ 7045 #define READ_WC40_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \ 7046 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008350, (_val)) 7047 #define WRITE_WC40_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \ 7048 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008350, (_val)) 7049 #define MODIFY_WC40_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _val, _mask) \ 7050 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008350, (_val), (_mask)) 7051 7052 /* sgmii & max timer offsets */ 7053 #define READ_WC40_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _val) \ 7054 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008351, (_val)) 7055 #define WRITE_WC40_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _val) \ 7056 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008351, (_val)) 7057 #define MODIFY_WC40_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _val, _mask) \ 7058 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008351, (_val), (_mask)) 7059 7060 /* link up & link down timer offsets */ 7061 #define READ_WC40_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _val) \ 7062 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008352, (_val)) 7063 #define WRITE_WC40_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _val) \ 7064 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008352, (_val)) 7065 #define MODIFY_WC40_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _val, _mask) \ 7066 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008352, (_val), (_mask)) 7067 7068 /* break link & next page link timer offsets */ 7069 #define READ_WC40_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _val) \ 7070 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008353, (_val)) 7071 #define WRITE_WC40_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _val) \ 7072 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008353, (_val)) 7073 #define MODIFY_WC40_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _val, _mask) \ 7074 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008353, (_val), (_mask)) 7075 7076 /* 11 MSbits of the oui, oui[23:13] */ 7077 #define READ_WC40_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _val) \ 7078 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008354, (_val)) 7079 #define WRITE_WC40_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _val) \ 7080 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008354, (_val)) 7081 #define MODIFY_WC40_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _val, _mask) \ 7082 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008354, (_val), (_mask)) 7083 7084 /* 11 middle bits of the oui, oui[12:2] */ 7085 #define READ_WC40_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _val) \ 7086 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008355, (_val)) 7087 #define WRITE_WC40_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _val) \ 7088 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008355, (_val)) 7089 #define MODIFY_WC40_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _val, _mask) \ 7090 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008355, (_val), (_mask)) 7091 7092 /* 2 LSbits of the oui, oui[1:0] */ 7093 #define READ_WC40_DIGITAL6_BAM_FIELDr(_unit, _pc, _val) \ 7094 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008356, (_val)) 7095 #define WRITE_WC40_DIGITAL6_BAM_FIELDr(_unit, _pc, _val) \ 7096 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008356, (_val)) 7097 #define MODIFY_WC40_DIGITAL6_BAM_FIELDr(_unit, _pc, _val, _mask) \ 7098 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008356, (_val), (_mask)) 7099 7100 /* User defined field of MP5 */ 7101 #define READ_WC40_DIGITAL6_UD_FIELDr(_unit, _pc, _val) \ 7102 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008357, (_val)) 7103 #define WRITE_WC40_DIGITAL6_UD_FIELDr(_unit, _pc, _val) \ 7104 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008357, (_val)) 7105 #define MODIFY_WC40_DIGITAL6_UD_FIELDr(_unit, _pc, _val, _mask) \ 7106 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008357, (_val), (_mask)) 7107 7108 /* Link partner's 11 MSbits of the oui, oui[23:13] */ 7109 #define READ_WC40_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _val) \ 7110 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008358, (_val)) 7111 #define WRITE_WC40_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _val) \ 7112 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008358, (_val)) 7113 #define MODIFY_WC40_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _val, _mask) \ 7114 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008358, (_val), (_mask)) 7115 7116 /* Link partner's 11 middle bits of the oui, oui[12:2] */ 7117 #define READ_WC40_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _val) \ 7118 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008359, (_val)) 7119 #define WRITE_WC40_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _val) \ 7120 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008359, (_val)) 7121 #define MODIFY_WC40_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _val, _mask) \ 7122 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008359, (_val), (_mask)) 7123 7124 /* Link partner's 2 LSbits of the oui, oui[1:0] */ 7125 #define READ_WC40_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _val) \ 7126 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000835a, (_val)) 7127 #define WRITE_WC40_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _val) \ 7128 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000835a, (_val)) 7129 #define MODIFY_WC40_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _val, _mask) \ 7130 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835a, (_val), (_mask)) 7131 7132 /* Link partner's User defined field of MP5 */ 7133 #define READ_WC40_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _val) \ 7134 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000835b, (_val)) 7135 #define WRITE_WC40_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _val) \ 7136 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000835b, (_val)) 7137 #define MODIFY_WC40_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _val, _mask) \ 7138 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835b, (_val), (_mask)) 7139 7140 /* AN local device user page 4 */ 7141 #define READ_WC40_DIGITAL6_UP4r(_unit, _pc, _val) \ 7142 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000835d, (_val)) 7143 #define WRITE_WC40_DIGITAL6_UP4r(_unit, _pc, _val) \ 7144 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000835d, (_val)) 7145 #define MODIFY_WC40_DIGITAL6_UP4r(_unit, _pc, _val, _mask) \ 7146 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835d, (_val), (_mask)) 7147 7148 /* AN local device user page 5 */ 7149 #define READ_WC40_DIGITAL6_UP5r(_unit, _pc, _val) \ 7150 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000835e, (_val)) 7151 #define WRITE_WC40_DIGITAL6_UP5r(_unit, _pc, _val) \ 7152 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000835e, (_val)) 7153 #define MODIFY_WC40_DIGITAL6_UP5r(_unit, _pc, _val, _mask) \ 7154 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835e, (_val), (_mask)) 7155 7156 7157 7158 /**************************************************************************** 7159 * Warpcore_USER_CL49_UserB0 7160 */ 7161 /* cl49 64/66 User Encoder Control 1 Register */ 7162 #define READ_WC40_CL49_USERB0_CONTROL1r(_unit, _pc, _val) \ 7163 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008360, (_val)) 7164 #define WRITE_WC40_CL49_USERB0_CONTROL1r(_unit, _pc, _val) \ 7165 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008360, (_val)) 7166 #define MODIFY_WC40_CL49_USERB0_CONTROL1r(_unit, _pc, _val, _mask) \ 7167 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008360, (_val), (_mask)) 7168 7169 /* cl49 64/66 User Encoder Status Register */ 7170 #define READ_WC40_CL49_USERB0_STATUS1r(_unit, _pc, _val) \ 7171 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008361, (_val)) 7172 #define WRITE_WC40_CL49_USERB0_STATUS1r(_unit, _pc, _val) \ 7173 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008361, (_val)) 7174 #define MODIFY_WC40_CL49_USERB0_STATUS1r(_unit, _pc, _val, _mask) \ 7175 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008361, (_val), (_mask)) 7176 7177 /* cl49 64/66 User Programmable symbol detected to align data in cl49 20 bit i/f mode */ 7178 #define READ_WC40_CL49_USERB0_SYMBOLDETECTr(_unit, _pc, _val) \ 7179 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008362, (_val)) 7180 #define WRITE_WC40_CL49_USERB0_SYMBOLDETECTr(_unit, _pc, _val) \ 7181 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008362, (_val)) 7182 #define MODIFY_WC40_CL49_USERB0_SYMBOLDETECTr(_unit, _pc, _val, _mask) \ 7183 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008362, (_val), (_mask)) 7184 7185 /* cl49 64/66 User Programmable symbol inserted to align data in cl49 20 bit i/f mode */ 7186 #define READ_WC40_CL49_USERB0_SYMBOLINSERTr(_unit, _pc, _val) \ 7187 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008363, (_val)) 7188 #define WRITE_WC40_CL49_USERB0_SYMBOLINSERTr(_unit, _pc, _val) \ 7189 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008363, (_val)) 7190 #define MODIFY_WC40_CL49_USERB0_SYMBOLINSERTr(_unit, _pc, _val, _mask) \ 7191 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008363, (_val), (_mask)) 7192 7193 /* cl49 64/66 User Encoder Control 2 Register */ 7194 #define READ_WC40_CL49_USERB0_CONTROL2r(_unit, _pc, _val) \ 7195 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008364, (_val)) 7196 #define WRITE_WC40_CL49_USERB0_CONTROL2r(_unit, _pc, _val) \ 7197 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008364, (_val)) 7198 #define MODIFY_WC40_CL49_USERB0_CONTROL2r(_unit, _pc, _val, _mask) \ 7199 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008364, (_val), (_mask)) 7200 7201 /* cl49 Tx fsm status register */ 7202 #define READ_WC40_CL49_USERB0_TXSM_STATUSr(_unit, _pc, _val) \ 7203 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008365, (_val)) 7204 #define WRITE_WC40_CL49_USERB0_TXSM_STATUSr(_unit, _pc, _val) \ 7205 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008365, (_val)) 7206 #define MODIFY_WC40_CL49_USERB0_TXSM_STATUSr(_unit, _pc, _val, _mask) \ 7207 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008365, (_val), (_mask)) 7208 7209 /* cl49 Rx fsm status register */ 7210 #define READ_WC40_CL49_USERB0_RXSM_STATUSr(_unit, _pc, _val) \ 7211 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008366, (_val)) 7212 #define WRITE_WC40_CL49_USERB0_RXSM_STATUSr(_unit, _pc, _val) \ 7213 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008366, (_val)) 7214 #define MODIFY_WC40_CL49_USERB0_RXSM_STATUSr(_unit, _pc, _val, _mask) \ 7215 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008366, (_val), (_mask)) 7216 7217 /* cl49 Lock fsm status register */ 7218 #define READ_WC40_CL49_USERB0_LSM_STATUSr(_unit, _pc, _val) \ 7219 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008367, (_val)) 7220 #define WRITE_WC40_CL49_USERB0_LSM_STATUSr(_unit, _pc, _val) \ 7221 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008367, (_val)) 7222 #define MODIFY_WC40_CL49_USERB0_LSM_STATUSr(_unit, _pc, _val, _mask) \ 7223 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008367, (_val), (_mask)) 7224 7225 /* 64/66 Decoder control register */ 7226 #define READ_WC40_CL49_USERB0_CONTROLr(_unit, _pc, _val) \ 7227 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008368, (_val)) 7228 #define WRITE_WC40_CL49_USERB0_CONTROLr(_unit, _pc, _val) \ 7229 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008368, (_val)) 7230 #define MODIFY_WC40_CL49_USERB0_CONTROLr(_unit, _pc, _val, _mask) \ 7231 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008368, (_val), (_mask)) 7232 7233 /* 64/66 Decoder status register */ 7234 #define READ_WC40_CL49_USERB0_STATUSr(_unit, _pc, _val) \ 7235 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008369, (_val)) 7236 #define WRITE_WC40_CL49_USERB0_STATUSr(_unit, _pc, _val) \ 7237 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008369, (_val)) 7238 #define MODIFY_WC40_CL49_USERB0_STATUSr(_unit, _pc, _val, _mask) \ 7239 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008369, (_val), (_mask)) 7240 7241 /* sync header counter value register */ 7242 #define READ_WC40_CL49_USERB0_SHCOUNTERr(_unit, _pc, _val) \ 7243 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000836a, (_val)) 7244 #define WRITE_WC40_CL49_USERB0_SHCOUNTERr(_unit, _pc, _val) \ 7245 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000836a, (_val)) 7246 #define MODIFY_WC40_CL49_USERB0_SHCOUNTERr(_unit, _pc, _val, _mask) \ 7247 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000836a, (_val), (_mask)) 7248 7249 /* BER fsm - 125us timer value register */ 7250 #define READ_WC40_CL49_USERB0_TIMER125USr(_unit, _pc, _val) \ 7251 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000836b, (_val)) 7252 #define WRITE_WC40_CL49_USERB0_TIMER125USr(_unit, _pc, _val) \ 7253 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000836b, (_val)) 7254 #define MODIFY_WC40_CL49_USERB0_TIMER125USr(_unit, _pc, _val, _mask) \ 7255 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000836b, (_val), (_mask)) 7256 7257 /* BER fsm - ber counter */ 7258 #define READ_WC40_CL49_USERB0_BERCNTr(_unit, _pc, _val) \ 7259 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000836c, (_val)) 7260 #define WRITE_WC40_CL49_USERB0_BERCNTr(_unit, _pc, _val) \ 7261 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000836c, (_val)) 7262 #define MODIFY_WC40_CL49_USERB0_BERCNTr(_unit, _pc, _val, _mask) \ 7263 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000836c, (_val), (_mask)) 7264 7265 /* cl49 BER Monitor fsm status register */ 7266 #define READ_WC40_CL49_USERB0_BERMON_STATUSr(_unit, _pc, _val) \ 7267 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000836d, (_val)) 7268 #define WRITE_WC40_CL49_USERB0_BERMON_STATUSr(_unit, _pc, _val) \ 7269 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000836d, (_val)) 7270 #define MODIFY_WC40_CL49_USERB0_BERMON_STATUSr(_unit, _pc, _val, _mask) \ 7271 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000836d, (_val), (_mask)) 7272 7273 /* test control register */ 7274 #define READ_WC40_CL49_USERB0_TSTCNT1r(_unit, _pc, _val) \ 7275 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000836e, (_val)) 7276 #define WRITE_WC40_CL49_USERB0_TSTCNT1r(_unit, _pc, _val) \ 7277 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000836e, (_val)) 7278 #define MODIFY_WC40_CL49_USERB0_TSTCNT1r(_unit, _pc, _val, _mask) \ 7279 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000836e, (_val), (_mask)) 7280 7281 7282 7283 /**************************************************************************** 7284 * Warpcore_USER_CL73_UserB0 7285 */ 7286 /* Clause 73 user control */ 7287 #define READ_WC40_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val) \ 7288 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008370, (_val)) 7289 #define WRITE_WC40_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val) \ 7290 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008370, (_val)) 7291 #define MODIFY_WC40_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val, _mask) \ 7292 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008370, (_val), (_mask)) 7293 7294 /* Clause 73 user status */ 7295 #define READ_WC40_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val) \ 7296 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008371, (_val)) 7297 #define WRITE_WC40_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val) \ 7298 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008371, (_val)) 7299 #define MODIFY_WC40_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val, _mask) \ 7300 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008371, (_val), (_mask)) 7301 7302 /* Clause 73 BAM control 1 */ 7303 #define READ_WC40_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val) \ 7304 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008372, (_val)) 7305 #define WRITE_WC40_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val) \ 7306 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008372, (_val)) 7307 #define MODIFY_WC40_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val, _mask) \ 7308 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008372, (_val), (_mask)) 7309 7310 /* Clause 73 BAM control 2 */ 7311 #define READ_WC40_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val) \ 7312 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008373, (_val)) 7313 #define WRITE_WC40_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val) \ 7314 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008373, (_val)) 7315 #define MODIFY_WC40_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val, _mask) \ 7316 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008373, (_val), (_mask)) 7317 7318 /* Clause 73 BAM control 3 */ 7319 #define READ_WC40_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val) \ 7320 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008374, (_val)) 7321 #define WRITE_WC40_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val) \ 7322 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008374, (_val)) 7323 #define MODIFY_WC40_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val, _mask) \ 7324 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008374, (_val), (_mask)) 7325 7326 /* Clause 73 BAM status 1 */ 7327 #define READ_WC40_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val) \ 7328 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008375, (_val)) 7329 #define WRITE_WC40_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val) \ 7330 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008375, (_val)) 7331 #define MODIFY_WC40_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val, _mask) \ 7332 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008375, (_val), (_mask)) 7333 7334 /* Clause 73 BAM status 2 */ 7335 #define READ_WC40_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val) \ 7336 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008376, (_val)) 7337 #define WRITE_WC40_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val) \ 7338 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008376, (_val)) 7339 #define MODIFY_WC40_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val, _mask) \ 7340 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008376, (_val), (_mask)) 7341 7342 /* Clause 73 BAM status 3 */ 7343 #define READ_WC40_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val) \ 7344 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008377, (_val)) 7345 #define WRITE_WC40_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val) \ 7346 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008377, (_val)) 7347 #define MODIFY_WC40_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val, _mask) \ 7348 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008377, (_val), (_mask)) 7349 7350 /* Clause 73 user control2 */ 7351 #define READ_WC40_CL73_USERB0_CL73_UCTRL2r(_unit, _pc, _val) \ 7352 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008378, (_val)) 7353 #define WRITE_WC40_CL73_USERB0_CL73_UCTRL2r(_unit, _pc, _val) \ 7354 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008378, (_val)) 7355 #define MODIFY_WC40_CL73_USERB0_CL73_UCTRL2r(_unit, _pc, _val, _mask) \ 7356 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008378, (_val), (_mask)) 7357 7358 /* Clause 73 user control3 */ 7359 #define READ_WC40_CL73_USERB0_CL73_UCTRL3r(_unit, _pc, _val) \ 7360 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008379, (_val)) 7361 #define WRITE_WC40_CL73_USERB0_CL73_UCTRL3r(_unit, _pc, _val) \ 7362 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008379, (_val)) 7363 #define MODIFY_WC40_CL73_USERB0_CL73_UCTRL3r(_unit, _pc, _val, _mask) \ 7364 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008379, (_val), (_mask)) 7365 7366 /* Clause 73 user control4 */ 7367 #define READ_WC40_CL73_USERB0_CL73_UCTRL4r(_unit, _pc, _val) \ 7368 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000837a, (_val)) 7369 #define WRITE_WC40_CL73_USERB0_CL73_UCTRL4r(_unit, _pc, _val) \ 7370 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000837a, (_val)) 7371 #define MODIFY_WC40_CL73_USERB0_CL73_UCTRL4r(_unit, _pc, _val, _mask) \ 7372 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000837a, (_val), (_mask)) 7373 7374 /* Clause 73 EEE control */ 7375 #define READ_WC40_CL73_USERB0_CL73_EEECTRLr(_unit, _pc, _val) \ 7376 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000837e, (_val)) 7377 #define WRITE_WC40_CL73_USERB0_CL73_EEECTRLr(_unit, _pc, _val) \ 7378 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000837e, (_val)) 7379 #define MODIFY_WC40_CL73_USERB0_CL73_EEECTRLr(_unit, _pc, _val, _mask) \ 7380 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000837e, (_val), (_mask)) 7381 7382 7383 7384 /**************************************************************************** 7385 * Warpcore_USER_CL74_UserB0 7386 */ 7387 /* "User FEC Control 1 register" */ 7388 #define READ_WC40_CL74_USERB0_UFECCONTROL1r(_unit, _pc, _val) \ 7389 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008380, (_val)) 7390 #define WRITE_WC40_CL74_USERB0_UFECCONTROL1r(_unit, _pc, _val) \ 7391 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008380, (_val)) 7392 #define MODIFY_WC40_CL74_USERB0_UFECCONTROL1r(_unit, _pc, _val, _mask) \ 7393 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008380, (_val), (_mask)) 7394 7395 /* "User FEC Control 2 register" */ 7396 #define READ_WC40_CL74_USERB0_UFECCONTROL2r(_unit, _pc, _val) \ 7397 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008381, (_val)) 7398 #define WRITE_WC40_CL74_USERB0_UFECCONTROL2r(_unit, _pc, _val) \ 7399 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008381, (_val)) 7400 #define MODIFY_WC40_CL74_USERB0_UFECCONTROL2r(_unit, _pc, _val, _mask) \ 7401 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008381, (_val), (_mask)) 7402 7403 /* "User FEC Control 3 register" */ 7404 #define READ_WC40_CL74_USERB0_UFECCONTROL3r(_unit, _pc, _val) \ 7405 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008382, (_val)) 7406 #define WRITE_WC40_CL74_USERB0_UFECCONTROL3r(_unit, _pc, _val) \ 7407 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008382, (_val)) 7408 #define MODIFY_WC40_CL74_USERB0_UFECCONTROL3r(_unit, _pc, _val, _mask) \ 7409 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008382, (_val), (_mask)) 7410 7411 /* "User FEC debug read data [15:0]" */ 7412 #define READ_WC40_CL74_USERB0_UFECDBG_EDATALr(_unit, _pc, _val) \ 7413 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008383, (_val)) 7414 #define WRITE_WC40_CL74_USERB0_UFECDBG_EDATALr(_unit, _pc, _val) \ 7415 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008383, (_val)) 7416 #define MODIFY_WC40_CL74_USERB0_UFECDBG_EDATALr(_unit, _pc, _val, _mask) \ 7417 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008383, (_val), (_mask)) 7418 7419 /* "User FEC debug read data [31:16]" */ 7420 #define READ_WC40_CL74_USERB0_UFECDBG_EDATAHr(_unit, _pc, _val) \ 7421 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008384, (_val)) 7422 #define WRITE_WC40_CL74_USERB0_UFECDBG_EDATAHr(_unit, _pc, _val) \ 7423 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008384, (_val)) 7424 #define MODIFY_WC40_CL74_USERB0_UFECDBG_EDATAHr(_unit, _pc, _val, _mask) \ 7425 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008384, (_val), (_mask)) 7426 7427 /* "User FEC Control 4 register" */ 7428 #define READ_WC40_CL74_USERB0_UFECCONTROL4r(_unit, _pc, _val) \ 7429 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008385, (_val)) 7430 #define WRITE_WC40_CL74_USERB0_UFECCONTROL4r(_unit, _pc, _val) \ 7431 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008385, (_val)) 7432 #define MODIFY_WC40_CL74_USERB0_UFECCONTROL4r(_unit, _pc, _val, _mask) \ 7433 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008385, (_val), (_mask)) 7434 7435 /* "fec burst error status lower 16 bits" */ 7436 #define READ_WC40_CL74_USERB0_UFEC_BURST_ERR_STATUSLr(_unit, _pc, _val) \ 7437 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008386, (_val)) 7438 #define WRITE_WC40_CL74_USERB0_UFEC_BURST_ERR_STATUSLr(_unit, _pc, _val) \ 7439 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008386, (_val)) 7440 #define MODIFY_WC40_CL74_USERB0_UFEC_BURST_ERR_STATUSLr(_unit, _pc, _val, _mask) \ 7441 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008386, (_val), (_mask)) 7442 7443 /* "fec burst error status lower 16 bits" */ 7444 #define READ_WC40_CL74_USERB0_UFEC_BURST_ERR_STATUSHr(_unit, _pc, _val) \ 7445 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008387, (_val)) 7446 #define WRITE_WC40_CL74_USERB0_UFEC_BURST_ERR_STATUSHr(_unit, _pc, _val) \ 7447 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008387, (_val)) 7448 #define MODIFY_WC40_CL74_USERB0_UFEC_BURST_ERR_STATUSHr(_unit, _pc, _val, _mask) \ 7449 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008387, (_val), (_mask)) 7450 7451 7452 7453 /**************************************************************************** 7454 * Warpcore_USER_EEE_UserB0 7455 */ 7456 /* EEE control register0 */ 7457 #define READ_WC40_EEE_USERB0_EEE_COMBO_CONTROL0r(_unit, _pc, _val) \ 7458 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008390, (_val)) 7459 #define WRITE_WC40_EEE_USERB0_EEE_COMBO_CONTROL0r(_unit, _pc, _val) \ 7460 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008390, (_val)) 7461 #define MODIFY_WC40_EEE_USERB0_EEE_COMBO_CONTROL0r(_unit, _pc, _val, _mask) \ 7462 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008390, (_val), (_mask)) 7463 7464 /* Cl36 Tx lpi fsm status register */ 7465 #define READ_WC40_EEE_USERB0_CL36_TX_LPI_SMr(_unit, _pc, _val) \ 7466 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008391, (_val)) 7467 #define WRITE_WC40_EEE_USERB0_CL36_TX_LPI_SMr(_unit, _pc, _val) \ 7468 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008391, (_val)) 7469 #define MODIFY_WC40_EEE_USERB0_CL36_TX_LPI_SMr(_unit, _pc, _val, _mask) \ 7470 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008391, (_val), (_mask)) 7471 7472 /* Cl36 Rx lpi fsm status register */ 7473 #define READ_WC40_EEE_USERB0_CL36_RX_LPI_SMr(_unit, _pc, _val) \ 7474 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008392, (_val)) 7475 #define WRITE_WC40_EEE_USERB0_CL36_RX_LPI_SMr(_unit, _pc, _val) \ 7476 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008392, (_val)) 7477 #define MODIFY_WC40_EEE_USERB0_CL36_RX_LPI_SMr(_unit, _pc, _val, _mask) \ 7478 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008392, (_val), (_mask)) 7479 7480 /* Cl49 Tx lpi fsm status register */ 7481 #define READ_WC40_EEE_USERB0_CL49_TX_LPI_SMr(_unit, _pc, _val) \ 7482 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008393, (_val)) 7483 #define WRITE_WC40_EEE_USERB0_CL49_TX_LPI_SMr(_unit, _pc, _val) \ 7484 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008393, (_val)) 7485 #define MODIFY_WC40_EEE_USERB0_CL49_TX_LPI_SMr(_unit, _pc, _val, _mask) \ 7486 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008393, (_val), (_mask)) 7487 7488 /* Cl49 Rx lpi fsm status register */ 7489 #define READ_WC40_EEE_USERB0_CL49_RX_LPI_SMr(_unit, _pc, _val) \ 7490 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008394, (_val)) 7491 #define WRITE_WC40_EEE_USERB0_CL49_RX_LPI_SMr(_unit, _pc, _val) \ 7492 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008394, (_val)) 7493 #define MODIFY_WC40_EEE_USERB0_CL49_RX_LPI_SMr(_unit, _pc, _val, _mask) \ 7494 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008394, (_val), (_mask)) 7495 7496 /* Transmit sleep timer count value register */ 7497 #define READ_WC40_EEE_USERB0_TX_SLEEP_TIMERr(_unit, _pc, _val) \ 7498 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008395, (_val)) 7499 #define WRITE_WC40_EEE_USERB0_TX_SLEEP_TIMERr(_unit, _pc, _val) \ 7500 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008395, (_val)) 7501 #define MODIFY_WC40_EEE_USERB0_TX_SLEEP_TIMERr(_unit, _pc, _val, _mask) \ 7502 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008395, (_val), (_mask)) 7503 7504 /* Transmit sleep timer count value register */ 7505 #define READ_WC40_EEE_USERB0_CL49_TX_SLEEP_TIMERr(_unit, _pc, _val) \ 7506 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008396, (_val)) 7507 #define WRITE_WC40_EEE_USERB0_CL49_TX_SLEEP_TIMERr(_unit, _pc, _val) \ 7508 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008396, (_val)) 7509 #define MODIFY_WC40_EEE_USERB0_CL49_TX_SLEEP_TIMERr(_unit, _pc, _val, _mask) \ 7510 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008396, (_val), (_mask)) 7511 7512 /* Transmit wake timer count value register */ 7513 #define READ_WC40_EEE_USERB0_TX_WAKE_TIMERr(_unit, _pc, _val) \ 7514 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008397, (_val)) 7515 #define WRITE_WC40_EEE_USERB0_TX_WAKE_TIMERr(_unit, _pc, _val) \ 7516 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008397, (_val)) 7517 #define MODIFY_WC40_EEE_USERB0_TX_WAKE_TIMERr(_unit, _pc, _val, _mask) \ 7518 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008397, (_val), (_mask)) 7519 7520 /* Receive Quiet timer offset count value register */ 7521 #define READ_WC40_EEE_USERB0_RX_OFFSET_TIMERr(_unit, _pc, _val) \ 7522 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008398, (_val)) 7523 #define WRITE_WC40_EEE_USERB0_RX_OFFSET_TIMERr(_unit, _pc, _val) \ 7524 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008398, (_val)) 7525 #define MODIFY_WC40_EEE_USERB0_RX_OFFSET_TIMERr(_unit, _pc, _val, _mask) \ 7526 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008398, (_val), (_mask)) 7527 7528 /* Receive Wake timer fault recovery timer count value register */ 7529 #define READ_WC40_EEE_USERB0_RX_WAKE_TIME_FAULT_TIMERr(_unit, _pc, _val) \ 7530 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008399, (_val)) 7531 #define WRITE_WC40_EEE_USERB0_RX_WAKE_TIME_FAULT_TIMERr(_unit, _pc, _val) \ 7532 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008399, (_val)) 7533 #define MODIFY_WC40_EEE_USERB0_RX_WAKE_TIME_FAULT_TIMERr(_unit, _pc, _val, _mask) \ 7534 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008399, (_val), (_mask)) 7535 7536 /* Misc timer bits register */ 7537 #define READ_WC40_EEE_USERB0_MISC_TIMERr(_unit, _pc, _val) \ 7538 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000839a, (_val)) 7539 #define WRITE_WC40_EEE_USERB0_MISC_TIMERr(_unit, _pc, _val) \ 7540 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000839a, (_val)) 7541 #define MODIFY_WC40_EEE_USERB0_MISC_TIMERr(_unit, _pc, _val, _mask) \ 7542 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000839a, (_val), (_mask)) 7543 7544 /* EEE lpi hysteresis/sigdet filter register */ 7545 #define READ_WC40_EEE_USERB0_EEE_HYST_TIMERr(_unit, _pc, _val) \ 7546 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000839b, (_val)) 7547 #define WRITE_WC40_EEE_USERB0_EEE_HYST_TIMERr(_unit, _pc, _val) \ 7548 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000839b, (_val)) 7549 #define MODIFY_WC40_EEE_USERB0_EEE_HYST_TIMERr(_unit, _pc, _val, _mask) \ 7550 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000839b, (_val), (_mask)) 7551 7552 /* EEE control override register */ 7553 #define READ_WC40_EEE_USERB0_EEE_OVERRIDE_CTRLr(_unit, _pc, _val) \ 7554 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000839c, (_val)) 7555 #define WRITE_WC40_EEE_USERB0_EEE_OVERRIDE_CTRLr(_unit, _pc, _val) \ 7556 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000839c, (_val)) 7557 #define MODIFY_WC40_EEE_USERB0_EEE_OVERRIDE_CTRLr(_unit, _pc, _val, _mask) \ 7558 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000839c, (_val), (_mask)) 7559 7560 /* EEE control register1 */ 7561 #define READ_WC40_EEE_USERB0_EEE_COMBO_CONTROL1r(_unit, _pc, _val) \ 7562 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000839d, (_val)) 7563 #define WRITE_WC40_EEE_USERB0_EEE_COMBO_CONTROL1r(_unit, _pc, _val) \ 7564 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000839d, (_val)) 7565 #define MODIFY_WC40_EEE_USERB0_EEE_COMBO_CONTROL1r(_unit, _pc, _val, _mask) \ 7566 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000839d, (_val), (_mask)) 7567 7568 /* XGMII/Cl49 LPI characters */ 7569 #define READ_WC40_EEE_USERB0_CL49_EEE_CHARr(_unit, _pc, _val) \ 7570 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000839e, (_val)) 7571 #define WRITE_WC40_EEE_USERB0_CL49_EEE_CHARr(_unit, _pc, _val) \ 7572 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000839e, (_val)) 7573 #define MODIFY_WC40_EEE_USERB0_CL49_EEE_CHARr(_unit, _pc, _val, _mask) \ 7574 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000839e, (_val), (_mask)) 7575 7576 7577 7578 /**************************************************************************** 7579 * Warpcore_USER_EEE_UserB1 7580 */ 7581 /* EEE Cl37 BAM Control Register */ 7582 #define READ_WC40_EEE_USERB1_EEE_AN_CTRLr(_unit, _pc, _val) \ 7583 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083a0, (_val)) 7584 #define WRITE_WC40_EEE_USERB1_EEE_AN_CTRLr(_unit, _pc, _val) \ 7585 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083a0, (_val)) 7586 #define MODIFY_WC40_EEE_USERB1_EEE_AN_CTRLr(_unit, _pc, _val, _mask) \ 7587 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a0, (_val), (_mask)) 7588 7589 /* EEE UP1 Register */ 7590 #define READ_WC40_EEE_USERB1_EEE_UP1r(_unit, _pc, _val) \ 7591 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083a1, (_val)) 7592 #define WRITE_WC40_EEE_USERB1_EEE_UP1r(_unit, _pc, _val) \ 7593 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083a1, (_val)) 7594 #define MODIFY_WC40_EEE_USERB1_EEE_UP1r(_unit, _pc, _val, _mask) \ 7595 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a1, (_val), (_mask)) 7596 7597 /* EEE UP2 Register */ 7598 #define READ_WC40_EEE_USERB1_EEE_UP2r(_unit, _pc, _val) \ 7599 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083a2, (_val)) 7600 #define WRITE_WC40_EEE_USERB1_EEE_UP2r(_unit, _pc, _val) \ 7601 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083a2, (_val)) 7602 #define MODIFY_WC40_EEE_USERB1_EEE_UP2r(_unit, _pc, _val, _mask) \ 7603 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a2, (_val), (_mask)) 7604 7605 /* EEE UP3 Register */ 7606 #define READ_WC40_EEE_USERB1_EEE_UP3r(_unit, _pc, _val) \ 7607 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083a3, (_val)) 7608 #define WRITE_WC40_EEE_USERB1_EEE_UP3r(_unit, _pc, _val) \ 7609 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083a3, (_val)) 7610 #define MODIFY_WC40_EEE_USERB1_EEE_UP3r(_unit, _pc, _val, _mask) \ 7611 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a3, (_val), (_mask)) 7612 7613 /* Link Partner EEE UP1 Register */ 7614 #define READ_WC40_EEE_USERB1_LP_EEE_UP1r(_unit, _pc, _val) \ 7615 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083a4, (_val)) 7616 #define WRITE_WC40_EEE_USERB1_LP_EEE_UP1r(_unit, _pc, _val) \ 7617 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083a4, (_val)) 7618 #define MODIFY_WC40_EEE_USERB1_LP_EEE_UP1r(_unit, _pc, _val, _mask) \ 7619 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a4, (_val), (_mask)) 7620 7621 /* Link Partner UP2 Register */ 7622 #define READ_WC40_EEE_USERB1_LP_EEE_UP2r(_unit, _pc, _val) \ 7623 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083a5, (_val)) 7624 #define WRITE_WC40_EEE_USERB1_LP_EEE_UP2r(_unit, _pc, _val) \ 7625 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083a5, (_val)) 7626 #define MODIFY_WC40_EEE_USERB1_LP_EEE_UP2r(_unit, _pc, _val, _mask) \ 7627 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a5, (_val), (_mask)) 7628 7629 /* Link Partner UP3 Register */ 7630 #define READ_WC40_EEE_USERB1_LP_EEE_UP3r(_unit, _pc, _val) \ 7631 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083a6, (_val)) 7632 #define WRITE_WC40_EEE_USERB1_LP_EEE_UP3r(_unit, _pc, _val) \ 7633 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083a6, (_val)) 7634 #define MODIFY_WC40_EEE_USERB1_LP_EEE_UP3r(_unit, _pc, _val, _mask) \ 7635 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a6, (_val), (_mask)) 7636 7637 /* EEE resolution status register */ 7638 #define READ_WC40_EEE_USERB1_EEE_RES_STATUSr(_unit, _pc, _val) \ 7639 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083a7, (_val)) 7640 #define WRITE_WC40_EEE_USERB1_EEE_RES_STATUSr(_unit, _pc, _val) \ 7641 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083a7, (_val)) 7642 #define MODIFY_WC40_EEE_USERB1_EEE_RES_STATUSr(_unit, _pc, _val, _mask) \ 7643 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a7, (_val), (_mask)) 7644 7645 7646 7647 /**************************************************************************** 7648 * Warpcore_USER_tx66 7649 */ 7650 /* 64/66 Encoder Control Register */ 7651 #define READ_WC40_TX66_CONTROLr(_unit, _pc, _val) \ 7652 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083b0, (_val)) 7653 #define WRITE_WC40_TX66_CONTROLr(_unit, _pc, _val) \ 7654 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083b0, (_val)) 7655 #define MODIFY_WC40_TX66_CONTROLr(_unit, _pc, _val, _mask) \ 7656 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b0, (_val), (_mask)) 7657 7658 /* 64/66 Encoder Status Register */ 7659 #define READ_WC40_TX66_STATUSr(_unit, _pc, _val) \ 7660 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083b1, (_val)) 7661 #define WRITE_WC40_TX66_STATUSr(_unit, _pc, _val) \ 7662 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083b1, (_val)) 7663 #define MODIFY_WC40_TX66_STATUSr(_unit, _pc, _val, _mask) \ 7664 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b1, (_val), (_mask)) 7665 7666 /* 64/66 Encoder programmable control character */ 7667 #define READ_WC40_TX66_PROGMMABLE_TLr(_unit, _pc, _val) \ 7668 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083b2, (_val)) 7669 #define WRITE_WC40_TX66_PROGMMABLE_TLr(_unit, _pc, _val) \ 7670 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083b2, (_val)) 7671 #define MODIFY_WC40_TX66_PROGMMABLE_TLr(_unit, _pc, _val, _mask) \ 7672 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b2, (_val), (_mask)) 7673 7674 7675 7676 /**************************************************************************** 7677 * Warpcore_USER_rx66 7678 */ 7679 /* 64/66 Decoder control register */ 7680 #define READ_WC40_RX66_CONTROLr(_unit, _pc, _val) \ 7681 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083c0, (_val)) 7682 #define WRITE_WC40_RX66_CONTROLr(_unit, _pc, _val) \ 7683 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083c0, (_val)) 7684 #define MODIFY_WC40_RX66_CONTROLr(_unit, _pc, _val, _mask) \ 7685 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c0, (_val), (_mask)) 7686 7687 /* 64/66 Decoder status register */ 7688 #define READ_WC40_RX66_STATUSr(_unit, _pc, _val) \ 7689 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083c1, (_val)) 7690 #define WRITE_WC40_RX66_STATUSr(_unit, _pc, _val) \ 7691 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083c1, (_val)) 7692 #define MODIFY_WC40_RX66_STATUSr(_unit, _pc, _val, _mask) \ 7693 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c1, (_val), (_mask)) 7694 7695 /* Sync code word bits 15:0 */ 7696 #define READ_WC40_RX66_SCW0r(_unit, _pc, _val) \ 7697 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083c2, (_val)) 7698 #define WRITE_WC40_RX66_SCW0r(_unit, _pc, _val) \ 7699 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083c2, (_val)) 7700 #define MODIFY_WC40_RX66_SCW0r(_unit, _pc, _val, _mask) \ 7701 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c2, (_val), (_mask)) 7702 7703 /* Sync code word bits 31;16 */ 7704 #define READ_WC40_RX66_SCW1r(_unit, _pc, _val) \ 7705 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083c3, (_val)) 7706 #define WRITE_WC40_RX66_SCW1r(_unit, _pc, _val) \ 7707 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083c3, (_val)) 7708 #define MODIFY_WC40_RX66_SCW1r(_unit, _pc, _val, _mask) \ 7709 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c3, (_val), (_mask)) 7710 7711 /* Sync code word bits 47:32 */ 7712 #define READ_WC40_RX66_SCW2r(_unit, _pc, _val) \ 7713 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083c4, (_val)) 7714 #define WRITE_WC40_RX66_SCW2r(_unit, _pc, _val) \ 7715 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083c4, (_val)) 7716 #define MODIFY_WC40_RX66_SCW2r(_unit, _pc, _val, _mask) \ 7717 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c4, (_val), (_mask)) 7718 7719 /* Sync code word bits 63:48 */ 7720 #define READ_WC40_RX66_SCW3r(_unit, _pc, _val) \ 7721 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083c5, (_val)) 7722 #define WRITE_WC40_RX66_SCW3r(_unit, _pc, _val) \ 7723 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083c5, (_val)) 7724 #define MODIFY_WC40_RX66_SCW3r(_unit, _pc, _val, _mask) \ 7725 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c5, (_val), (_mask)) 7726 7727 /* Sync code word mask bits 15:0 */ 7728 #define READ_WC40_RX66_SCW0_MASKr(_unit, _pc, _val) \ 7729 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083c6, (_val)) 7730 #define WRITE_WC40_RX66_SCW0_MASKr(_unit, _pc, _val) \ 7731 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083c6, (_val)) 7732 #define MODIFY_WC40_RX66_SCW0_MASKr(_unit, _pc, _val, _mask) \ 7733 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c6, (_val), (_mask)) 7734 7735 /* Sync code word mask bits 31;16 */ 7736 #define READ_WC40_RX66_SCW1_MASKr(_unit, _pc, _val) \ 7737 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083c7, (_val)) 7738 #define WRITE_WC40_RX66_SCW1_MASKr(_unit, _pc, _val) \ 7739 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083c7, (_val)) 7740 #define MODIFY_WC40_RX66_SCW1_MASKr(_unit, _pc, _val, _mask) \ 7741 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c7, (_val), (_mask)) 7742 7743 /* Sync code word mask bits 47:32 */ 7744 #define READ_WC40_RX66_SCW2_MASKr(_unit, _pc, _val) \ 7745 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083c8, (_val)) 7746 #define WRITE_WC40_RX66_SCW2_MASKr(_unit, _pc, _val) \ 7747 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083c8, (_val)) 7748 #define MODIFY_WC40_RX66_SCW2_MASKr(_unit, _pc, _val, _mask) \ 7749 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c8, (_val), (_mask)) 7750 7751 /* Sync code word mask bits 63:48 */ 7752 #define READ_WC40_RX66_SCW3_MASKr(_unit, _pc, _val) \ 7753 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083c9, (_val)) 7754 #define WRITE_WC40_RX66_SCW3_MASKr(_unit, _pc, _val) \ 7755 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083c9, (_val)) 7756 #define MODIFY_WC40_RX66_SCW3_MASKr(_unit, _pc, _val, _mask) \ 7757 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c9, (_val), (_mask)) 7758 7759 /* Sync bits and sync mask bits */ 7760 #define READ_WC40_RX66_SYNCBITSr(_unit, _pc, _val) \ 7761 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083ca, (_val)) 7762 #define WRITE_WC40_RX66_SYNCBITSr(_unit, _pc, _val) \ 7763 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083ca, (_val)) 7764 #define MODIFY_WC40_RX66_SYNCBITSr(_unit, _pc, _val, _mask) \ 7765 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083ca, (_val), (_mask)) 7766 7767 /* Sync code word statemachine control register */ 7768 #define READ_WC40_RX66_SCWCONTROLr(_unit, _pc, _val) \ 7769 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083cb, (_val)) 7770 #define WRITE_WC40_RX66_SCWCONTROLr(_unit, _pc, _val) \ 7771 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083cb, (_val)) 7772 #define MODIFY_WC40_RX66_SCWCONTROLr(_unit, _pc, _val, _mask) \ 7773 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083cb, (_val), (_mask)) 7774 7775 /* Clock Comp event counter */ 7776 #define READ_WC40_RX66_CC_EVENTCOUNTr(_unit, _pc, _val) \ 7777 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083cc, (_val)) 7778 #define WRITE_WC40_RX66_CC_EVENTCOUNTr(_unit, _pc, _val) \ 7779 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083cc, (_val)) 7780 #define MODIFY_WC40_RX66_CC_EVENTCOUNTr(_unit, _pc, _val, _mask) \ 7781 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083cc, (_val), (_mask)) 7782 7783 /* CW=SCW counter & skew position */ 7784 #define READ_WC40_RX66_SCWCOUNTr(_unit, _pc, _val) \ 7785 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083cd, (_val)) 7786 #define WRITE_WC40_RX66_SCWCOUNTr(_unit, _pc, _val) \ 7787 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083cd, (_val)) 7788 #define MODIFY_WC40_RX66_SCWCOUNTr(_unit, _pc, _val, _mask) \ 7789 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083cd, (_val), (_mask)) 7790 7791 /* scw & K-code group error counters */ 7792 #define READ_WC40_RX66_ERRCOUNTr(_unit, _pc, _val) \ 7793 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083ce, (_val)) 7794 #define WRITE_WC40_RX66_ERRCOUNTr(_unit, _pc, _val) \ 7795 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083ce, (_val)) 7796 #define MODIFY_WC40_RX66_ERRCOUNTr(_unit, _pc, _val, _mask) \ 7797 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083ce, (_val), (_mask)) 7798 7799 7800 7801 /**************************************************************************** 7802 * Warpcore_USER_LnTxBert 7803 */ 7804 /* Tx Bert control register */ 7805 #define READ_WC40_LNTXBERT_TXBERTCTRLr(_unit, _pc, _val) \ 7806 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083d0, (_val)) 7807 #define WRITE_WC40_LNTXBERT_TXBERTCTRLr(_unit, _pc, _val) \ 7808 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083d0, (_val)) 7809 #define MODIFY_WC40_LNTXBERT_TXBERTCTRLr(_unit, _pc, _val, _mask) \ 7810 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083d0, (_val), (_mask)) 7811 7812 /* Tx Bert SOP, EOP definition register */ 7813 #define READ_WC40_LNTXBERT_TXBERTSOPEOPr(_unit, _pc, _val) \ 7814 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083d1, (_val)) 7815 #define WRITE_WC40_LNTXBERT_TXBERTSOPEOPr(_unit, _pc, _val) \ 7816 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083d1, (_val)) 7817 #define MODIFY_WC40_LNTXBERT_TXBERTSOPEOPr(_unit, _pc, _val, _mask) \ 7818 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083d1, (_val), (_mask)) 7819 7820 /* Packet size configuration 0 register */ 7821 #define READ_WC40_LNTXBERT_TXBERTSIZE0r(_unit, _pc, _val) \ 7822 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083d2, (_val)) 7823 #define WRITE_WC40_LNTXBERT_TXBERTSIZE0r(_unit, _pc, _val) \ 7824 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083d2, (_val)) 7825 #define MODIFY_WC40_LNTXBERT_TXBERTSIZE0r(_unit, _pc, _val, _mask) \ 7826 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083d2, (_val), (_mask)) 7827 7828 /* Packet size configuration 1 register */ 7829 #define READ_WC40_LNTXBERT_TXBERTSIZE1r(_unit, _pc, _val) \ 7830 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083d3, (_val)) 7831 #define WRITE_WC40_LNTXBERT_TXBERTSIZE1r(_unit, _pc, _val) \ 7832 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083d3, (_val)) 7833 #define MODIFY_WC40_LNTXBERT_TXBERTSIZE1r(_unit, _pc, _val, _mask) \ 7834 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083d3, (_val), (_mask)) 7835 7836 /* Packet size configuration 2 register */ 7837 #define READ_WC40_LNTXBERT_TXBERTSIZE2r(_unit, _pc, _val) \ 7838 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083d4, (_val)) 7839 #define WRITE_WC40_LNTXBERT_TXBERTSIZE2r(_unit, _pc, _val) \ 7840 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083d4, (_val)) 7841 #define MODIFY_WC40_LNTXBERT_TXBERTSIZE2r(_unit, _pc, _val, _mask) \ 7842 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083d4, (_val), (_mask)) 7843 7844 /* IPG 0 definition register */ 7845 #define READ_WC40_LNTXBERT_TXBERTIPG0r(_unit, _pc, _val) \ 7846 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083d5, (_val)) 7847 #define WRITE_WC40_LNTXBERT_TXBERTIPG0r(_unit, _pc, _val) \ 7848 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083d5, (_val)) 7849 #define MODIFY_WC40_LNTXBERT_TXBERTIPG0r(_unit, _pc, _val, _mask) \ 7850 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083d5, (_val), (_mask)) 7851 7852 /* IPG 1 definition register */ 7853 #define READ_WC40_LNTXBERT_TXBERTIPG1r(_unit, _pc, _val) \ 7854 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083d6, (_val)) 7855 #define WRITE_WC40_LNTXBERT_TXBERTIPG1r(_unit, _pc, _val) \ 7856 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083d6, (_val)) 7857 #define MODIFY_WC40_LNTXBERT_TXBERTIPG1r(_unit, _pc, _val, _mask) \ 7858 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083d6, (_val), (_mask)) 7859 7860 /* Transmitted byte count upper 16 bits register */ 7861 #define READ_WC40_LNTXBERT_TXBERTBYTEUr(_unit, _pc, _val) \ 7862 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083d7, (_val)) 7863 #define WRITE_WC40_LNTXBERT_TXBERTBYTEUr(_unit, _pc, _val) \ 7864 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083d7, (_val)) 7865 #define MODIFY_WC40_LNTXBERT_TXBERTBYTEUr(_unit, _pc, _val, _mask) \ 7866 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083d7, (_val), (_mask)) 7867 7868 /* Transmitted byte count lower 16 bits register */ 7869 #define READ_WC40_LNTXBERT_TXBERTBYTELr(_unit, _pc, _val) \ 7870 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083d8, (_val)) 7871 #define WRITE_WC40_LNTXBERT_TXBERTBYTELr(_unit, _pc, _val) \ 7872 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083d8, (_val)) 7873 #define MODIFY_WC40_LNTXBERT_TXBERTBYTELr(_unit, _pc, _val, _mask) \ 7874 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083d8, (_val), (_mask)) 7875 7876 /* Transmitted packet count upper 16 bits register */ 7877 #define READ_WC40_LNTXBERT_TXBERTPACKETUr(_unit, _pc, _val) \ 7878 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083d9, (_val)) 7879 #define WRITE_WC40_LNTXBERT_TXBERTPACKETUr(_unit, _pc, _val) \ 7880 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083d9, (_val)) 7881 #define MODIFY_WC40_LNTXBERT_TXBERTPACKETUr(_unit, _pc, _val, _mask) \ 7882 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083d9, (_val), (_mask)) 7883 7884 /* Transmitted packet count lower 16 bits register */ 7885 #define READ_WC40_LNTXBERT_TXBERTPACKETLr(_unit, _pc, _val) \ 7886 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083da, (_val)) 7887 #define WRITE_WC40_LNTXBERT_TXBERTPACKETLr(_unit, _pc, _val) \ 7888 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083da, (_val)) 7889 #define MODIFY_WC40_LNTXBERT_TXBERTPACKETLr(_unit, _pc, _val, _mask) \ 7890 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083da, (_val), (_mask)) 7891 7892 /* Tx Bert control1 register */ 7893 #define READ_WC40_LNTXBERT_TXBERTCTRL1r(_unit, _pc, _val) \ 7894 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083db, (_val)) 7895 #define WRITE_WC40_LNTXBERT_TXBERTCTRL1r(_unit, _pc, _val) \ 7896 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083db, (_val)) 7897 #define MODIFY_WC40_LNTXBERT_TXBERTCTRL1r(_unit, _pc, _val, _mask) \ 7898 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083db, (_val), (_mask)) 7899 7900 7901 7902 /**************************************************************************** 7903 * Warpcore_USER_LnRxBert 7904 */ 7905 /* Rx Bert control register */ 7906 #define READ_WC40_LNRXBERT_RXBERTCTRLr(_unit, _pc, _val) \ 7907 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083e0, (_val)) 7908 #define WRITE_WC40_LNRXBERT_RXBERTCTRLr(_unit, _pc, _val) \ 7909 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083e0, (_val)) 7910 #define MODIFY_WC40_LNRXBERT_RXBERTCTRLr(_unit, _pc, _val, _mask) \ 7911 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083e0, (_val), (_mask)) 7912 7913 /* Rx Bert SOP, EOP definition register */ 7914 #define READ_WC40_LNRXBERT_RXBERTSOPEOPr(_unit, _pc, _val) \ 7915 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083e1, (_val)) 7916 #define WRITE_WC40_LNRXBERT_RXBERTSOPEOPr(_unit, _pc, _val) \ 7917 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083e1, (_val)) 7918 #define MODIFY_WC40_LNRXBERT_RXBERTSOPEOPr(_unit, _pc, _val, _mask) \ 7919 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083e1, (_val), (_mask)) 7920 7921 /* Received byte count upper 16 bits register */ 7922 #define READ_WC40_LNRXBERT_RXBERTBYTEUr(_unit, _pc, _val) \ 7923 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083e7, (_val)) 7924 #define WRITE_WC40_LNRXBERT_RXBERTBYTEUr(_unit, _pc, _val) \ 7925 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083e7, (_val)) 7926 #define MODIFY_WC40_LNRXBERT_RXBERTBYTEUr(_unit, _pc, _val, _mask) \ 7927 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083e7, (_val), (_mask)) 7928 7929 /* Received bytes count lower 16 bits register */ 7930 #define READ_WC40_LNRXBERT_RXBERTBYTELr(_unit, _pc, _val) \ 7931 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083e8, (_val)) 7932 #define WRITE_WC40_LNRXBERT_RXBERTBYTELr(_unit, _pc, _val) \ 7933 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083e8, (_val)) 7934 #define MODIFY_WC40_LNRXBERT_RXBERTBYTELr(_unit, _pc, _val, _mask) \ 7935 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083e8, (_val), (_mask)) 7936 7937 /* Received packet count upper 16 bits register */ 7938 #define READ_WC40_LNRXBERT_RXBERTPACKETUr(_unit, _pc, _val) \ 7939 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083e9, (_val)) 7940 #define WRITE_WC40_LNRXBERT_RXBERTPACKETUr(_unit, _pc, _val) \ 7941 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083e9, (_val)) 7942 #define MODIFY_WC40_LNRXBERT_RXBERTPACKETUr(_unit, _pc, _val, _mask) \ 7943 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083e9, (_val), (_mask)) 7944 7945 /* Received packet count lower 16 bits register */ 7946 #define READ_WC40_LNRXBERT_RXBERTPACKETLr(_unit, _pc, _val) \ 7947 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083ea, (_val)) 7948 #define WRITE_WC40_LNRXBERT_RXBERTPACKETLr(_unit, _pc, _val) \ 7949 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083ea, (_val)) 7950 #define MODIFY_WC40_LNRXBERT_RXBERTPACKETLr(_unit, _pc, _val, _mask) \ 7951 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083ea, (_val), (_mask)) 7952 7953 /* Received bits error count */ 7954 #define READ_WC40_LNRXBERT_RXBERTBITERRr(_unit, _pc, _val) \ 7955 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083eb, (_val)) 7956 #define WRITE_WC40_LNRXBERT_RXBERTBITERRr(_unit, _pc, _val) \ 7957 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083eb, (_val)) 7958 #define MODIFY_WC40_LNRXBERT_RXBERTBITERRr(_unit, _pc, _val, _mask) \ 7959 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083eb, (_val), (_mask)) 7960 7961 /* Received bytes error count */ 7962 #define READ_WC40_LNRXBERT_RXBERTBYTEERRr(_unit, _pc, _val) \ 7963 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083ec, (_val)) 7964 #define WRITE_WC40_LNRXBERT_RXBERTBYTEERRr(_unit, _pc, _val) \ 7965 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083ec, (_val)) 7966 #define MODIFY_WC40_LNRXBERT_RXBERTBYTEERRr(_unit, _pc, _val, _mask) \ 7967 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083ec, (_val), (_mask)) 7968 7969 /* Received packets error count */ 7970 #define READ_WC40_LNRXBERT_RXBERTPKTERRr(_unit, _pc, _val) \ 7971 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083ed, (_val)) 7972 #define WRITE_WC40_LNRXBERT_RXBERTPKTERRr(_unit, _pc, _val) \ 7973 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083ed, (_val)) 7974 #define MODIFY_WC40_LNRXBERT_RXBERTPKTERRr(_unit, _pc, _val, _mask) \ 7975 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083ed, (_val), (_mask)) 7976 7977 /* Receive Status */ 7978 #define READ_WC40_LNRXBERT_RXBERTSTATUSr(_unit, _pc, _val) \ 7979 WC40_REG_READ((_unit), (_pc), 0x00, 0x000083ee, (_val)) 7980 #define WRITE_WC40_LNRXBERT_RXBERTSTATUSr(_unit, _pc, _val) \ 7981 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x000083ee, (_val)) 7982 #define MODIFY_WC40_LNRXBERT_RXBERTSTATUSr(_unit, _pc, _val, _mask) \ 7983 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x000083ee, (_val), (_mask)) 7984 7985 7986 7987 /**************************************************************************** 7988 * Warpcore_USER_FX100 7989 */ 7990 /* 100FX control register 1 */ 7991 #define READ_WC40_FX100_CONTROL1r(_unit, _pc, _val) \ 7992 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008400, (_val)) 7993 #define WRITE_WC40_FX100_CONTROL1r(_unit, _pc, _val) \ 7994 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008400, (_val)) 7995 #define MODIFY_WC40_FX100_CONTROL1r(_unit, _pc, _val, _mask) \ 7996 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008400, (_val), (_mask)) 7997 7998 /* 100FX control register 2 */ 7999 #define READ_WC40_FX100_CONTROL2r(_unit, _pc, _val) \ 8000 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008401, (_val)) 8001 #define WRITE_WC40_FX100_CONTROL2r(_unit, _pc, _val) \ 8002 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008401, (_val)) 8003 #define MODIFY_WC40_FX100_CONTROL2r(_unit, _pc, _val, _mask) \ 8004 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008401, (_val), (_mask)) 8005 8006 /* 100FX control register 3 */ 8007 #define READ_WC40_FX100_CONTROL3r(_unit, _pc, _val) \ 8008 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008402, (_val)) 8009 #define WRITE_WC40_FX100_CONTROL3r(_unit, _pc, _val) \ 8010 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008402, (_val)) 8011 #define MODIFY_WC40_FX100_CONTROL3r(_unit, _pc, _val, _mask) \ 8012 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008402, (_val), (_mask)) 8013 8014 /* 100FX status register 1 */ 8015 #define READ_WC40_FX100_STATUS1r(_unit, _pc, _val) \ 8016 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008403, (_val)) 8017 #define WRITE_WC40_FX100_STATUS1r(_unit, _pc, _val) \ 8018 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008403, (_val)) 8019 #define MODIFY_WC40_FX100_STATUS1r(_unit, _pc, _val, _mask) \ 8020 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008403, (_val), (_mask)) 8021 8022 /* 100FX status register 3 */ 8023 #define READ_WC40_FX100_STATUS3r(_unit, _pc, _val) \ 8024 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008405, (_val)) 8025 #define WRITE_WC40_FX100_STATUS3r(_unit, _pc, _val) \ 8026 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008405, (_val)) 8027 #define MODIFY_WC40_FX100_STATUS3r(_unit, _pc, _val, _mask) \ 8028 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008405, (_val), (_mask)) 8029 8030 /* 100FX status register 4 */ 8031 #define READ_WC40_FX100_STATUS4r(_unit, _pc, _val) \ 8032 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008406, (_val)) 8033 #define WRITE_WC40_FX100_STATUS4r(_unit, _pc, _val) \ 8034 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008406, (_val)) 8035 #define MODIFY_WC40_FX100_STATUS4r(_unit, _pc, _val, _mask) \ 8036 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008406, (_val), (_mask)) 8037 8038 /* 100FX idle pattern register 1 */ 8039 #define READ_WC40_FX100_FX100IDLE1r(_unit, _pc, _val) \ 8040 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008407, (_val)) 8041 #define WRITE_WC40_FX100_FX100IDLE1r(_unit, _pc, _val) \ 8042 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008407, (_val)) 8043 #define MODIFY_WC40_FX100_FX100IDLE1r(_unit, _pc, _val, _mask) \ 8044 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008407, (_val), (_mask)) 8045 8046 /* 100FX idle pattern register 2 */ 8047 #define READ_WC40_FX100_FX100IDLE2r(_unit, _pc, _val) \ 8048 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008408, (_val)) 8049 #define WRITE_WC40_FX100_FX100IDLE2r(_unit, _pc, _val) \ 8050 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008408, (_val)) 8051 #define MODIFY_WC40_FX100_FX100IDLE2r(_unit, _pc, _val, _mask) \ 8052 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008408, (_val), (_mask)) 8053 8054 /* 100FX idle status register */ 8055 #define READ_WC40_FX100_FX100IDLESTATUSr(_unit, _pc, _val) \ 8056 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008409, (_val)) 8057 #define WRITE_WC40_FX100_FX100IDLESTATUSr(_unit, _pc, _val) \ 8058 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008409, (_val)) 8059 #define MODIFY_WC40_FX100_FX100IDLESTATUSr(_unit, _pc, _val, _mask) \ 8060 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008409, (_val), (_mask)) 8061 8062 /* 100FX idle threshold register */ 8063 #define READ_WC40_FX100_FX100IDLETHRESr(_unit, _pc, _val) \ 8064 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000840a, (_val)) 8065 #define WRITE_WC40_FX100_FX100IDLETHRESr(_unit, _pc, _val) \ 8066 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000840a, (_val)) 8067 #define MODIFY_WC40_FX100_FX100IDLETHRESr(_unit, _pc, _val, _mask) \ 8068 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000840a, (_val), (_mask)) 8069 8070 /* 100FX lock timer register */ 8071 #define READ_WC40_FX100_FX100LOCKTMRr(_unit, _pc, _val) \ 8072 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000840b, (_val)) 8073 #define WRITE_WC40_FX100_FX100LOCKTMRr(_unit, _pc, _val) \ 8074 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000840b, (_val)) 8075 #define MODIFY_WC40_FX100_FX100LOCKTMRr(_unit, _pc, _val, _mask) \ 8076 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000840b, (_val), (_mask)) 8077 8078 /* 100FX link timer register */ 8079 #define READ_WC40_FX100_FX100LINKTMRr(_unit, _pc, _val) \ 8080 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000840c, (_val)) 8081 #define WRITE_WC40_FX100_FX100LINKTMRr(_unit, _pc, _val) \ 8082 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000840c, (_val)) 8083 #define MODIFY_WC40_FX100_FX100LINKTMRr(_unit, _pc, _val, _mask) \ 8084 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000840c, (_val), (_mask)) 8085 8086 8087 8088 /**************************************************************************** 8089 * Warpcore_USER_EEE_TimerB0 8090 */ 8091 /* Group1 Trasnmit Refresh timer count value register */ 8092 #define READ_WC40_EEE_TIMERB0_GRP1_TX_REFRESH_TIMERr(_unit, _pc, _val) \ 8093 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008410, (_val)) 8094 #define WRITE_WC40_EEE_TIMERB0_GRP1_TX_REFRESH_TIMERr(_unit, _pc, _val) \ 8095 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008410, (_val)) 8096 #define MODIFY_WC40_EEE_TIMERB0_GRP1_TX_REFRESH_TIMERr(_unit, _pc, _val, _mask) \ 8097 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008410, (_val), (_mask)) 8098 8099 /* Group1 Trasnmit Quiet timer count value register */ 8100 #define READ_WC40_EEE_TIMERB0_GRP1_TX_QUIET_TIMERr(_unit, _pc, _val) \ 8101 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008411, (_val)) 8102 #define WRITE_WC40_EEE_TIMERB0_GRP1_TX_QUIET_TIMERr(_unit, _pc, _val) \ 8103 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008411, (_val)) 8104 #define MODIFY_WC40_EEE_TIMERB0_GRP1_TX_QUIET_TIMERr(_unit, _pc, _val, _mask) \ 8105 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008411, (_val), (_mask)) 8106 8107 /* Group1 Receive Wake timer count value register */ 8108 #define READ_WC40_EEE_TIMERB0_GRP1_RX_WAKE_TIMERr(_unit, _pc, _val) \ 8109 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008412, (_val)) 8110 #define WRITE_WC40_EEE_TIMERB0_GRP1_RX_WAKE_TIMERr(_unit, _pc, _val) \ 8111 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008412, (_val)) 8112 #define MODIFY_WC40_EEE_TIMERB0_GRP1_RX_WAKE_TIMERr(_unit, _pc, _val, _mask) \ 8113 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008412, (_val), (_mask)) 8114 8115 /* Group2 Trasnmit Refresh timer count value register */ 8116 #define READ_WC40_EEE_TIMERB0_GRP2_TX_REFRESH_TIMERr(_unit, _pc, _val) \ 8117 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008413, (_val)) 8118 #define WRITE_WC40_EEE_TIMERB0_GRP2_TX_REFRESH_TIMERr(_unit, _pc, _val) \ 8119 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008413, (_val)) 8120 #define MODIFY_WC40_EEE_TIMERB0_GRP2_TX_REFRESH_TIMERr(_unit, _pc, _val, _mask) \ 8121 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008413, (_val), (_mask)) 8122 8123 /* Group2 Trasnmit Quiet timer count value register */ 8124 #define READ_WC40_EEE_TIMERB0_GRP2_TX_QUIET_TIMERr(_unit, _pc, _val) \ 8125 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008414, (_val)) 8126 #define WRITE_WC40_EEE_TIMERB0_GRP2_TX_QUIET_TIMERr(_unit, _pc, _val) \ 8127 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008414, (_val)) 8128 #define MODIFY_WC40_EEE_TIMERB0_GRP2_TX_QUIET_TIMERr(_unit, _pc, _val, _mask) \ 8129 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008414, (_val), (_mask)) 8130 8131 /* Group2 Receive Wake timer count value register */ 8132 #define READ_WC40_EEE_TIMERB0_GRP2_RX_WAKE_TIMERr(_unit, _pc, _val) \ 8133 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008415, (_val)) 8134 #define WRITE_WC40_EEE_TIMERB0_GRP2_RX_WAKE_TIMERr(_unit, _pc, _val) \ 8135 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008415, (_val)) 8136 #define MODIFY_WC40_EEE_TIMERB0_GRP2_RX_WAKE_TIMERr(_unit, _pc, _val, _mask) \ 8137 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008415, (_val), (_mask)) 8138 8139 /* Group3 Trasnmit Refresh timer count value register */ 8140 #define READ_WC40_EEE_TIMERB0_GRP3_TX_REFRESH_TIMERr(_unit, _pc, _val) \ 8141 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008416, (_val)) 8142 #define WRITE_WC40_EEE_TIMERB0_GRP3_TX_REFRESH_TIMERr(_unit, _pc, _val) \ 8143 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008416, (_val)) 8144 #define MODIFY_WC40_EEE_TIMERB0_GRP3_TX_REFRESH_TIMERr(_unit, _pc, _val, _mask) \ 8145 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008416, (_val), (_mask)) 8146 8147 /* Group3 Trasnmit Quiet timer count value register */ 8148 #define READ_WC40_EEE_TIMERB0_GRP3_TX_QUIET_TIMERr(_unit, _pc, _val) \ 8149 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008417, (_val)) 8150 #define WRITE_WC40_EEE_TIMERB0_GRP3_TX_QUIET_TIMERr(_unit, _pc, _val) \ 8151 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008417, (_val)) 8152 #define MODIFY_WC40_EEE_TIMERB0_GRP3_TX_QUIET_TIMERr(_unit, _pc, _val, _mask) \ 8153 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008417, (_val), (_mask)) 8154 8155 /* Group3 Receive Wake timer count value register */ 8156 #define READ_WC40_EEE_TIMERB0_GRP3_RX_WAKE_TIMERr(_unit, _pc, _val) \ 8157 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008418, (_val)) 8158 #define WRITE_WC40_EEE_TIMERB0_GRP3_RX_WAKE_TIMERr(_unit, _pc, _val) \ 8159 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008418, (_val)) 8160 #define MODIFY_WC40_EEE_TIMERB0_GRP3_RX_WAKE_TIMERr(_unit, _pc, _val, _mask) \ 8161 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008418, (_val), (_mask)) 8162 8163 /* Group4 Trasnmit Refresh timer count value register */ 8164 #define READ_WC40_EEE_TIMERB0_GRP4_TX_REFRESH_TIMERr(_unit, _pc, _val) \ 8165 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008419, (_val)) 8166 #define WRITE_WC40_EEE_TIMERB0_GRP4_TX_REFRESH_TIMERr(_unit, _pc, _val) \ 8167 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008419, (_val)) 8168 #define MODIFY_WC40_EEE_TIMERB0_GRP4_TX_REFRESH_TIMERr(_unit, _pc, _val, _mask) \ 8169 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008419, (_val), (_mask)) 8170 8171 /* Group4 Trasnmit Quiet timer count value register */ 8172 #define READ_WC40_EEE_TIMERB0_GRP4_TX_QUIET_TIMERr(_unit, _pc, _val) \ 8173 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000841a, (_val)) 8174 #define WRITE_WC40_EEE_TIMERB0_GRP4_TX_QUIET_TIMERr(_unit, _pc, _val) \ 8175 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000841a, (_val)) 8176 #define MODIFY_WC40_EEE_TIMERB0_GRP4_TX_QUIET_TIMERr(_unit, _pc, _val, _mask) \ 8177 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000841a, (_val), (_mask)) 8178 8179 /* Group4 Receive Wake timer count value register */ 8180 #define READ_WC40_EEE_TIMERB0_GRP4_RX_WAKE_TIMERr(_unit, _pc, _val) \ 8181 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000841b, (_val)) 8182 #define WRITE_WC40_EEE_TIMERB0_GRP4_RX_WAKE_TIMERr(_unit, _pc, _val) \ 8183 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000841b, (_val)) 8184 #define MODIFY_WC40_EEE_TIMERB0_GRP4_RX_WAKE_TIMERr(_unit, _pc, _val, _mask) \ 8185 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000841b, (_val), (_mask)) 8186 8187 /* Group5 Trasnmit Refresh timer count value register */ 8188 #define READ_WC40_EEE_TIMERB0_GRP5_TX_REFRESH_TIMERr(_unit, _pc, _val) \ 8189 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000841c, (_val)) 8190 #define WRITE_WC40_EEE_TIMERB0_GRP5_TX_REFRESH_TIMERr(_unit, _pc, _val) \ 8191 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000841c, (_val)) 8192 #define MODIFY_WC40_EEE_TIMERB0_GRP5_TX_REFRESH_TIMERr(_unit, _pc, _val, _mask) \ 8193 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000841c, (_val), (_mask)) 8194 8195 /* Group5 Trasnmit Quiet timer count value register */ 8196 #define READ_WC40_EEE_TIMERB0_GRP5_TX_QUIET_TIMERr(_unit, _pc, _val) \ 8197 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000841d, (_val)) 8198 #define WRITE_WC40_EEE_TIMERB0_GRP5_TX_QUIET_TIMERr(_unit, _pc, _val) \ 8199 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000841d, (_val)) 8200 #define MODIFY_WC40_EEE_TIMERB0_GRP5_TX_QUIET_TIMERr(_unit, _pc, _val, _mask) \ 8201 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000841d, (_val), (_mask)) 8202 8203 /* Group5 Receive Wake timer count value register */ 8204 #define READ_WC40_EEE_TIMERB0_GRP5_RX_WAKE_TIMERr(_unit, _pc, _val) \ 8205 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000841e, (_val)) 8206 #define WRITE_WC40_EEE_TIMERB0_GRP5_RX_WAKE_TIMERr(_unit, _pc, _val) \ 8207 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000841e, (_val)) 8208 #define MODIFY_WC40_EEE_TIMERB0_GRP5_RX_WAKE_TIMERr(_unit, _pc, _val, _mask) \ 8209 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000841e, (_val), (_mask)) 8210 8211 /**************************************************************************** 8212 * Warpcore_USER_CL82_UserB0 8213 */ 8214 /* cl82 tx control 1 register */ 8215 #define READ_WC40_CL82_USERB0_TX_CONTROL_1r(_unit, _pc, _val) \ 8216 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008420, (_val)) 8217 #define WRITE_WC40_CL82_USERB0_TX_CONTROL_1r(_unit, _pc, _val) \ 8218 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008420, (_val)) 8219 #define MODIFY_WC40_CL82_USERB0_TX_CONTROL_1r(_unit, _pc, _val, _mask) \ 8220 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008420, (_val), (_mask)) 8221 8222 /* cl82 tx control 2 register */ 8223 #define READ_WC40_CL82_USERB0_TX_CONTROL_2r(_unit, _pc, _val) \ 8224 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008421, (_val)) 8225 #define WRITE_WC40_CL82_USERB0_TX_CONTROL_2r(_unit, _pc, _val) \ 8226 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008421, (_val)) 8227 #define MODIFY_WC40_CL82_USERB0_TX_CONTROL_2r(_unit, _pc, _val, _mask) \ 8228 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008421, (_val), (_mask)) 8229 8230 /* cl82 tx status 1 register */ 8231 #define READ_WC40_CL82_USERB0_TX_STATUS_1r(_unit, _pc, _val) \ 8232 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008422, (_val)) 8233 #define WRITE_WC40_CL82_USERB0_TX_STATUS_1r(_unit, _pc, _val) \ 8234 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008422, (_val)) 8235 #define MODIFY_WC40_CL82_USERB0_TX_STATUS_1r(_unit, _pc, _val, _mask) \ 8236 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008422, (_val), (_mask)) 8237 8238 /* cl82 tx status 2 register */ 8239 #define READ_WC40_CL82_USERB0_TX_STATUS_2r(_unit, _pc, _val) \ 8240 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008423, (_val)) 8241 #define WRITE_WC40_CL82_USERB0_TX_STATUS_2r(_unit, _pc, _val) \ 8242 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008423, (_val)) 8243 #define MODIFY_WC40_CL82_USERB0_TX_STATUS_2r(_unit, _pc, _val, _mask) \ 8244 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008423, (_val), (_mask)) 8245 8246 /* cl82 Rx status 1 register */ 8247 #define READ_WC40_CL82_USERB0_RX_STATUS_1r(_unit, _pc, _val) \ 8248 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008424, (_val)) 8249 #define WRITE_WC40_CL82_USERB0_RX_STATUS_1r(_unit, _pc, _val) \ 8250 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008424, (_val)) 8251 #define MODIFY_WC40_CL82_USERB0_RX_STATUS_1r(_unit, _pc, _val, _mask) \ 8252 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008424, (_val), (_mask)) 8253 8254 /* cl82 Rx status 2 register */ 8255 #define READ_WC40_CL82_USERB0_RX_STATUS_2r(_unit, _pc, _val) \ 8256 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008425, (_val)) 8257 #define WRITE_WC40_CL82_USERB0_RX_STATUS_2r(_unit, _pc, _val) \ 8258 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008425, (_val)) 8259 #define MODIFY_WC40_CL82_USERB0_RX_STATUS_2r(_unit, _pc, _val, _mask) \ 8260 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008425, (_val), (_mask)) 8261 8262 /* cl82 Rx status 3 register */ 8263 #define READ_WC40_CL82_USERB0_RX_STATUS_3r(_unit, _pc, _val) \ 8264 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008426, (_val)) 8265 #define WRITE_WC40_CL82_USERB0_RX_STATUS_3r(_unit, _pc, _val) \ 8266 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008426, (_val)) 8267 #define MODIFY_WC40_CL82_USERB0_RX_STATUS_3r(_unit, _pc, _val, _mask) \ 8268 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008426, (_val), (_mask)) 8269 8270 /* cl82 Rx control 1 register */ 8271 #define READ_WC40_CL82_USERB0_RX_CONTROL_1r(_unit, _pc, _val) \ 8272 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008427, (_val)) 8273 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_1r(_unit, _pc, _val) \ 8274 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008427, (_val)) 8275 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_1r(_unit, _pc, _val, _mask) \ 8276 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008427, (_val), (_mask)) 8277 8278 /* cl82 RX control 2 register */ 8279 #define READ_WC40_CL82_USERB0_RX_CONTROL_2r(_unit, _pc, _val) \ 8280 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008428, (_val)) 8281 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_2r(_unit, _pc, _val) \ 8282 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008428, (_val)) 8283 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_2r(_unit, _pc, _val, _mask) \ 8284 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008428, (_val), (_mask)) 8285 8286 /* cl82 RX control 3 register */ 8287 #define READ_WC40_CL82_USERB0_RX_CONTROL_3r(_unit, _pc, _val) \ 8288 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008429, (_val)) 8289 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_3r(_unit, _pc, _val) \ 8290 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008429, (_val)) 8291 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_3r(_unit, _pc, _val, _mask) \ 8292 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008429, (_val), (_mask)) 8293 8294 /* cl82 RX control 4 register */ 8295 #define READ_WC40_CL82_USERB0_RX_CONTROL_4r(_unit, _pc, _val) \ 8296 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000842a, (_val)) 8297 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_4r(_unit, _pc, _val) \ 8298 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000842a, (_val)) 8299 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_4r(_unit, _pc, _val, _mask) \ 8300 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000842a, (_val), (_mask)) 8301 8302 /* cl82 RX control 5 register */ 8303 #define READ_WC40_CL82_USERB0_RX_CONTROL_5r(_unit, _pc, _val) \ 8304 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000842b, (_val)) 8305 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_5r(_unit, _pc, _val) \ 8306 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000842b, (_val)) 8307 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_5r(_unit, _pc, _val, _mask) \ 8308 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000842b, (_val), (_mask)) 8309 8310 /* cl82 RX control 6 register */ 8311 #define READ_WC40_CL82_USERB0_RX_CONTROL_6r(_unit, _pc, _val) \ 8312 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000842c, (_val)) 8313 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_6r(_unit, _pc, _val) \ 8314 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000842c, (_val)) 8315 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_6r(_unit, _pc, _val, _mask) \ 8316 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000842c, (_val), (_mask)) 8317 8318 /* cl82 Rx status 4 register */ 8319 #define READ_WC40_CL82_USERB0_RX_STATUS_4r(_unit, _pc, _val) \ 8320 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000842d, (_val)) 8321 #define WRITE_WC40_CL82_USERB0_RX_STATUS_4r(_unit, _pc, _val) \ 8322 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000842d, (_val)) 8323 #define MODIFY_WC40_CL82_USERB0_RX_STATUS_4r(_unit, _pc, _val, _mask) \ 8324 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000842d, (_val), (_mask)) 8325 8326 8327 8328 /**************************************************************************** 8329 * Warpcore_USER_CL82_UserB1 8330 */ 8331 /* cl82 RX control 7 register */ 8332 #define READ_WC40_CL82_USERB1_RX_CONTROL_7r(_unit, _pc, _val) \ 8333 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008430, (_val)) 8334 #define WRITE_WC40_CL82_USERB1_RX_CONTROL_7r(_unit, _pc, _val) \ 8335 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008430, (_val)) 8336 #define MODIFY_WC40_CL82_USERB1_RX_CONTROL_7r(_unit, _pc, _val, _mask) \ 8337 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008430, (_val), (_mask)) 8338 8339 /* cl82 Rx status 5 register */ 8340 #define READ_WC40_CL82_USERB1_RX_STATUS_5r(_unit, _pc, _val) \ 8341 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008431, (_val)) 8342 #define WRITE_WC40_CL82_USERB1_RX_STATUS_5r(_unit, _pc, _val) \ 8343 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008431, (_val)) 8344 #define MODIFY_WC40_CL82_USERB1_RX_STATUS_5r(_unit, _pc, _val, _mask) \ 8345 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008431, (_val), (_mask)) 8346 8347 /* cl82 TX control 3 register */ 8348 #define READ_WC40_CL82_USERB1_TX_CONTROL_3r(_unit, _pc, _val) \ 8349 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008432, (_val)) 8350 #define WRITE_WC40_CL82_USERB1_TX_CONTROL_3r(_unit, _pc, _val) \ 8351 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008432, (_val)) 8352 #define MODIFY_WC40_CL82_USERB1_TX_CONTROL_3r(_unit, _pc, _val, _mask) \ 8353 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008432, (_val), (_mask)) 8354 8355 /* cl82 TX status 3 register */ 8356 #define READ_WC40_CL82_USERB1_TX_STATUS_3r(_unit, _pc, _val) \ 8357 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008433, (_val)) 8358 #define WRITE_WC40_CL82_USERB1_TX_STATUS_3r(_unit, _pc, _val) \ 8359 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008433, (_val)) 8360 #define MODIFY_WC40_CL82_USERB1_TX_STATUS_3r(_unit, _pc, _val, _mask) \ 8361 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008433, (_val), (_mask)) 8362 8363 /* cl82 TX control 4 register */ 8364 #define READ_WC40_CL82_USERB1_TX_CONTROL_4r(_unit, _pc, _val) \ 8365 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008434, (_val)) 8366 #define WRITE_WC40_CL82_USERB1_TX_CONTROL_4r(_unit, _pc, _val) \ 8367 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008434, (_val)) 8368 #define MODIFY_WC40_CL82_USERB1_TX_CONTROL_4r(_unit, _pc, _val, _mask) \ 8369 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008434, (_val), (_mask)) 8370 8371 /* cl82 RX control 8 register */ 8372 #define READ_WC40_CL82_USERB1_RX_CONTROL_8r(_unit, _pc, _val) \ 8373 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008435, (_val)) 8374 #define WRITE_WC40_CL82_USERB1_RX_CONTROL_8r(_unit, _pc, _val) \ 8375 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008435, (_val)) 8376 #define MODIFY_WC40_CL82_USERB1_RX_CONTROL_8r(_unit, _pc, _val, _mask) \ 8377 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008435, (_val), (_mask)) 8378 8379 /* cl82 TX control 5 register */ 8380 #define READ_WC40_CL82_USERB1_TX_CONTROL_5r(_unit, _pc, _val) \ 8381 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008436, (_val)) 8382 #define WRITE_WC40_CL82_USERB1_TX_CONTROL_5r(_unit, _pc, _val) \ 8383 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008436, (_val)) 8384 #define MODIFY_WC40_CL82_USERB1_TX_CONTROL_5r(_unit, _pc, _val, _mask) \ 8385 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008436, (_val), (_mask)) 8386 8387 /* cl82 TX control 6 register */ 8388 #define READ_WC40_CL82_USERB1_TX_CONTROL_6r(_unit, _pc, _val) \ 8389 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008437, (_val)) 8390 #define WRITE_WC40_CL82_USERB1_TX_CONTROL_6r(_unit, _pc, _val) \ 8391 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008437, (_val)) 8392 #define MODIFY_WC40_CL82_USERB1_TX_CONTROL_6r(_unit, _pc, _val, _mask) \ 8393 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008437, (_val), (_mask)) 8394 8395 /* cl82 TX control 7 register */ 8396 #define READ_WC40_CL82_USERB1_TX_CONTROL_7r(_unit, _pc, _val) \ 8397 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008438, (_val)) 8398 #define WRITE_WC40_CL82_USERB1_TX_CONTROL_7r(_unit, _pc, _val) \ 8399 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008438, (_val)) 8400 #define MODIFY_WC40_CL82_USERB1_TX_CONTROL_7r(_unit, _pc, _val, _mask) \ 8401 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008438, (_val), (_mask)) 8402 8403 /* cl82 RX control 9 register */ 8404 #define READ_WC40_CL82_USERB1_RX_CONTROL_9r(_unit, _pc, _val) \ 8405 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008439, (_val)) 8406 #define WRITE_WC40_CL82_USERB1_RX_CONTROL_9r(_unit, _pc, _val) \ 8407 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008439, (_val)) 8408 #define MODIFY_WC40_CL82_USERB1_RX_CONTROL_9r(_unit, _pc, _val, _mask) \ 8409 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008439, (_val), (_mask)) 8410 8411 /* cl82 RX control 10 register */ 8412 #define READ_WC40_CL82_USERB1_RX_CONTROL_10r(_unit, _pc, _val) \ 8413 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000843a, (_val)) 8414 #define WRITE_WC40_CL82_USERB1_RX_CONTROL_10r(_unit, _pc, _val) \ 8415 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000843a, (_val)) 8416 #define MODIFY_WC40_CL82_USERB1_RX_CONTROL_10r(_unit, _pc, _val, _mask) \ 8417 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000843a, (_val), (_mask)) 8418 8419 /* cl82 RX control 11 register */ 8420 #define READ_WC40_CL82_USERB1_RX_CONTROL_11r(_unit, _pc, _val) \ 8421 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000843b, (_val)) 8422 #define WRITE_WC40_CL82_USERB1_RX_CONTROL_11r(_unit, _pc, _val) \ 8423 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000843b, (_val)) 8424 #define MODIFY_WC40_CL82_USERB1_RX_CONTROL_11r(_unit, _pc, _val, _mask) \ 8425 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000843b, (_val), (_mask)) 8426 8427 8428 8429 /**************************************************************************** 8430 * Warpcore_USER_rx66b1 8431 */ 8432 /* BRCM/cl49 Control register */ 8433 #define READ_WC40_RX66B1_BRCM_CL49_CONTROLr(_unit, _pc, _val) \ 8434 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008440, (_val)) 8435 #define WRITE_WC40_RX66B1_BRCM_CL49_CONTROLr(_unit, _pc, _val) \ 8436 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008440, (_val)) 8437 #define MODIFY_WC40_RX66B1_BRCM_CL49_CONTROLr(_unit, _pc, _val, _mask) \ 8438 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008440, (_val), (_mask)) 8439 8440 /* Misc Control register */ 8441 #define READ_WC40_RX66B1_RX66B1_CONTROL1r(_unit, _pc, _val) \ 8442 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008441, (_val)) 8443 #define WRITE_WC40_RX66B1_RX66B1_CONTROL1r(_unit, _pc, _val) \ 8444 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008441, (_val)) 8445 #define MODIFY_WC40_RX66B1_RX66B1_CONTROL1r(_unit, _pc, _val, _mask) \ 8446 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008441, (_val), (_mask)) 8447 8448 8449 8450 /**************************************************************************** 8451 * Warpcore_USER_ETA 8452 */ 8453 /* ETA1 Register */ 8454 #define READ_WC40_ETA_ETA1r(_unit, _pc, _val) \ 8455 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008450, (_val)) 8456 #define WRITE_WC40_ETA_ETA1r(_unit, _pc, _val) \ 8457 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008450, (_val)) 8458 #define MODIFY_WC40_ETA_ETA1r(_unit, _pc, _val, _mask) \ 8459 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008450, (_val), (_mask)) 8460 8461 /* ETA2 Register */ 8462 #define READ_WC40_ETA_ETA2r(_unit, _pc, _val) \ 8463 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008451, (_val)) 8464 #define WRITE_WC40_ETA_ETA2r(_unit, _pc, _val) \ 8465 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008451, (_val)) 8466 #define MODIFY_WC40_ETA_ETA2r(_unit, _pc, _val, _mask) \ 8467 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008451, (_val), (_mask)) 8468 8469 /* ETA3 Register */ 8470 #define READ_WC40_ETA_ETA3r(_unit, _pc, _val) \ 8471 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008452, (_val)) 8472 #define WRITE_WC40_ETA_ETA3r(_unit, _pc, _val) \ 8473 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008452, (_val)) 8474 #define MODIFY_WC40_ETA_ETA3r(_unit, _pc, _val, _mask) \ 8475 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008452, (_val), (_mask)) 8476 8477 8478 8479 /**************************************************************************** 8480 * Warpcore_USER_PatGen256_0 8481 */ 8482 /* Pattern Genertor 0 Register */ 8483 #define READ_WC40_PATGEN256_0_REG0r(_unit, _pc, _val) \ 8484 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008500, (_val)) 8485 #define WRITE_WC40_PATGEN256_0_REG0r(_unit, _pc, _val) \ 8486 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008500, (_val)) 8487 #define MODIFY_WC40_PATGEN256_0_REG0r(_unit, _pc, _val, _mask) \ 8488 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008500, (_val), (_mask)) 8489 8490 /* Pattern Genertor 1 Register */ 8491 #define READ_WC40_PATGEN256_0_REG1r(_unit, _pc, _val) \ 8492 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008501, (_val)) 8493 #define WRITE_WC40_PATGEN256_0_REG1r(_unit, _pc, _val) \ 8494 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008501, (_val)) 8495 #define MODIFY_WC40_PATGEN256_0_REG1r(_unit, _pc, _val, _mask) \ 8496 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008501, (_val), (_mask)) 8497 8498 /* Pattern Genertor 2 Register */ 8499 #define READ_WC40_PATGEN256_0_REG2r(_unit, _pc, _val) \ 8500 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008502, (_val)) 8501 #define WRITE_WC40_PATGEN256_0_REG2r(_unit, _pc, _val) \ 8502 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008502, (_val)) 8503 #define MODIFY_WC40_PATGEN256_0_REG2r(_unit, _pc, _val, _mask) \ 8504 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008502, (_val), (_mask)) 8505 8506 /* Pattern Genertor 3 Register */ 8507 #define READ_WC40_PATGEN256_0_REG3r(_unit, _pc, _val) \ 8508 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008503, (_val)) 8509 #define WRITE_WC40_PATGEN256_0_REG3r(_unit, _pc, _val) \ 8510 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008503, (_val)) 8511 #define MODIFY_WC40_PATGEN256_0_REG3r(_unit, _pc, _val, _mask) \ 8512 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008503, (_val), (_mask)) 8513 8514 /* Pattern Genertor 4 Register */ 8515 #define READ_WC40_PATGEN256_0_REG4r(_unit, _pc, _val) \ 8516 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008504, (_val)) 8517 #define WRITE_WC40_PATGEN256_0_REG4r(_unit, _pc, _val) \ 8518 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008504, (_val)) 8519 #define MODIFY_WC40_PATGEN256_0_REG4r(_unit, _pc, _val, _mask) \ 8520 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008504, (_val), (_mask)) 8521 8522 /* Pattern Genertor 5 Register */ 8523 #define READ_WC40_PATGEN256_0_REG5r(_unit, _pc, _val) \ 8524 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008505, (_val)) 8525 #define WRITE_WC40_PATGEN256_0_REG5r(_unit, _pc, _val) \ 8526 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008505, (_val)) 8527 #define MODIFY_WC40_PATGEN256_0_REG5r(_unit, _pc, _val, _mask) \ 8528 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008505, (_val), (_mask)) 8529 8530 /* Pattern Genertor 6 Register */ 8531 #define READ_WC40_PATGEN256_0_REG6r(_unit, _pc, _val) \ 8532 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008506, (_val)) 8533 #define WRITE_WC40_PATGEN256_0_REG6r(_unit, _pc, _val) \ 8534 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008506, (_val)) 8535 #define MODIFY_WC40_PATGEN256_0_REG6r(_unit, _pc, _val, _mask) \ 8536 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008506, (_val), (_mask)) 8537 8538 /* Pattern Genertor 7 Register */ 8539 #define READ_WC40_PATGEN256_0_REG7r(_unit, _pc, _val) \ 8540 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008507, (_val)) 8541 #define WRITE_WC40_PATGEN256_0_REG7r(_unit, _pc, _val) \ 8542 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008507, (_val)) 8543 #define MODIFY_WC40_PATGEN256_0_REG7r(_unit, _pc, _val, _mask) \ 8544 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008507, (_val), (_mask)) 8545 8546 /* Pattern Genertor 8 Register */ 8547 #define READ_WC40_PATGEN256_0_REG8r(_unit, _pc, _val) \ 8548 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008508, (_val)) 8549 #define WRITE_WC40_PATGEN256_0_REG8r(_unit, _pc, _val) \ 8550 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008508, (_val)) 8551 #define MODIFY_WC40_PATGEN256_0_REG8r(_unit, _pc, _val, _mask) \ 8552 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008508, (_val), (_mask)) 8553 8554 /* Pattern Genertor 9 Register */ 8555 #define READ_WC40_PATGEN256_0_REG9r(_unit, _pc, _val) \ 8556 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008509, (_val)) 8557 #define WRITE_WC40_PATGEN256_0_REG9r(_unit, _pc, _val) \ 8558 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008509, (_val)) 8559 #define MODIFY_WC40_PATGEN256_0_REG9r(_unit, _pc, _val, _mask) \ 8560 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008509, (_val), (_mask)) 8561 8562 /* Pattern Genertor 10 Register */ 8563 #define READ_WC40_PATGEN256_0_REG10r(_unit, _pc, _val) \ 8564 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000850a, (_val)) 8565 #define WRITE_WC40_PATGEN256_0_REG10r(_unit, _pc, _val) \ 8566 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000850a, (_val)) 8567 #define MODIFY_WC40_PATGEN256_0_REG10r(_unit, _pc, _val, _mask) \ 8568 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000850a, (_val), (_mask)) 8569 8570 /* Pattern Genertor 11 Register */ 8571 #define READ_WC40_PATGEN256_0_REG11r(_unit, _pc, _val) \ 8572 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000850b, (_val)) 8573 #define WRITE_WC40_PATGEN256_0_REG11r(_unit, _pc, _val) \ 8574 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000850b, (_val)) 8575 #define MODIFY_WC40_PATGEN256_0_REG11r(_unit, _pc, _val, _mask) \ 8576 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000850b, (_val), (_mask)) 8577 8578 /* Pattern Genertor 12 Register */ 8579 #define READ_WC40_PATGEN256_0_REG12r(_unit, _pc, _val) \ 8580 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000850c, (_val)) 8581 #define WRITE_WC40_PATGEN256_0_REG12r(_unit, _pc, _val) \ 8582 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000850c, (_val)) 8583 #define MODIFY_WC40_PATGEN256_0_REG12r(_unit, _pc, _val, _mask) \ 8584 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000850c, (_val), (_mask)) 8585 8586 /* Pattern Genertor 13 Register */ 8587 #define READ_WC40_PATGEN256_0_REG13r(_unit, _pc, _val) \ 8588 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000850d, (_val)) 8589 #define WRITE_WC40_PATGEN256_0_REG13r(_unit, _pc, _val) \ 8590 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000850d, (_val)) 8591 #define MODIFY_WC40_PATGEN256_0_REG13r(_unit, _pc, _val, _mask) \ 8592 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000850d, (_val), (_mask)) 8593 8594 /* Pattern Genertor 14 Register */ 8595 #define READ_WC40_PATGEN256_0_REG14r(_unit, _pc, _val) \ 8596 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000850e, (_val)) 8597 #define WRITE_WC40_PATGEN256_0_REG14r(_unit, _pc, _val) \ 8598 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000850e, (_val)) 8599 #define MODIFY_WC40_PATGEN256_0_REG14r(_unit, _pc, _val, _mask) \ 8600 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000850e, (_val), (_mask)) 8601 8602 8603 8604 /**************************************************************************** 8605 * Warpcore_USER_PatGen256_1 8606 */ 8607 /* Pattern Genertor 15 Register */ 8608 #define READ_WC40_PATGEN256_1_REG15r(_unit, _pc, _val) \ 8609 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008510, (_val)) 8610 #define WRITE_WC40_PATGEN256_1_REG15r(_unit, _pc, _val) \ 8611 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008510, (_val)) 8612 #define MODIFY_WC40_PATGEN256_1_REG15r(_unit, _pc, _val, _mask) \ 8613 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008510, (_val), (_mask)) 8614 8615 /* Pattern Genertor Control Register */ 8616 #define READ_WC40_PATGEN256_1_CTRLr(_unit, _pc, _val) \ 8617 WC40_REG_READ((_unit), (_pc), 0x00, 0x00008511, (_val)) 8618 #define WRITE_WC40_PATGEN256_1_CTRLr(_unit, _pc, _val) \ 8619 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x00008511, (_val)) 8620 #define MODIFY_WC40_PATGEN256_1_CTRLr(_unit, _pc, _val, _mask) \ 8621 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x00008511, (_val), (_mask)) 8622 8623 8624 8625 /**************************************************************************** 8626 * Warpcore_USER_XFI_BD0 8627 */ 8628 /* PMD and PCS Status Register */ 8629 #define READ_WC40_XFI_BD0_PMD_AND_PCS_STATUS_REGISTERr(_unit, _pc, _val) \ 8630 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd04, (_val)) 8631 #define WRITE_WC40_XFI_BD0_PMD_AND_PCS_STATUS_REGISTERr(_unit, _pc, _val) \ 8632 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd04, (_val)) 8633 #define MODIFY_WC40_XFI_BD0_PMD_AND_PCS_STATUS_REGISTERr(_unit, _pc, _val, _mask) \ 8634 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd04, (_val), (_mask)) 8635 8636 /* PMD Optics Digital Control Register */ 8637 #define READ_WC40_XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTERr(_unit, _pc, _val) \ 8638 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd08, (_val)) 8639 #define WRITE_WC40_XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTERr(_unit, _pc, _val) \ 8640 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd08, (_val)) 8641 #define MODIFY_WC40_XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTERr(_unit, _pc, _val, _mask) \ 8642 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd08, (_val), (_mask)) 8643 8644 /* PMD Digital Status Register */ 8645 #define READ_WC40_XFI_BD0_PMD_DIGITAL_STATUS_REGISTERr(_unit, _pc, _val) \ 8646 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd09, (_val)) 8647 #define WRITE_WC40_XFI_BD0_PMD_DIGITAL_STATUS_REGISTERr(_unit, _pc, _val) \ 8648 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd09, (_val)) 8649 #define MODIFY_WC40_XFI_BD0_PMD_DIGITAL_STATUS_REGISTERr(_unit, _pc, _val, _mask) \ 8650 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd09, (_val), (_mask)) 8651 8652 /* PMD and PCS Test Control Register */ 8653 #define READ_WC40_XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTERr(_unit, _pc, _val) \ 8654 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd0a, (_val)) 8655 #define WRITE_WC40_XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTERr(_unit, _pc, _val) \ 8656 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd0a, (_val)) 8657 #define MODIFY_WC40_XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTERr(_unit, _pc, _val, _mask) \ 8658 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd0a, (_val), (_mask)) 8659 8660 /* PMD General Purpose TX Pattern Register 0 */ 8661 #define READ_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0r(_unit, _pc, _val) \ 8662 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd0c, (_val)) 8663 #define WRITE_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0r(_unit, _pc, _val) \ 8664 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd0c, (_val)) 8665 #define MODIFY_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0r(_unit, _pc, _val, _mask) \ 8666 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd0c, (_val), (_mask)) 8667 8668 /* PMD General Purpose TX Pattern Register 1 */ 8669 #define READ_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1r(_unit, _pc, _val) \ 8670 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd0d, (_val)) 8671 #define WRITE_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1r(_unit, _pc, _val) \ 8672 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd0d, (_val)) 8673 #define MODIFY_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1r(_unit, _pc, _val, _mask) \ 8674 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd0d, (_val), (_mask)) 8675 8676 8677 8678 /**************************************************************************** 8679 * Warpcore_USER_XFI_BD1 8680 */ 8681 /* PRBS 31 Test Window 1 Register */ 8682 #define READ_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTERr(_unit, _pc, _val) \ 8683 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd10, (_val)) 8684 #define WRITE_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTERr(_unit, _pc, _val) \ 8685 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd10, (_val)) 8686 #define MODIFY_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTERr(_unit, _pc, _val, _mask) \ 8687 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd10, (_val), (_mask)) 8688 8689 /* PRBS 31 Test Window 2 Register */ 8690 #define READ_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTERr(_unit, _pc, _val) \ 8691 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd11, (_val)) 8692 #define WRITE_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTERr(_unit, _pc, _val) \ 8693 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd11, (_val)) 8694 #define MODIFY_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTERr(_unit, _pc, _val, _mask) \ 8695 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd11, (_val), (_mask)) 8696 8697 /* User PRBS Control 0 Register */ 8698 #define READ_WC40_XFI_BD1_USER_PRBS_CONTROL_0_REGISTERr(_unit, _pc, _val) \ 8699 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd14, (_val)) 8700 #define WRITE_WC40_XFI_BD1_USER_PRBS_CONTROL_0_REGISTERr(_unit, _pc, _val) \ 8701 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd14, (_val)) 8702 #define MODIFY_WC40_XFI_BD1_USER_PRBS_CONTROL_0_REGISTERr(_unit, _pc, _val, _mask) \ 8703 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd14, (_val), (_mask)) 8704 8705 /* User PRBS Status 0 Register */ 8706 #define READ_WC40_XFI_BD1_USER_PRBS_STATUS_0_REGISTERr(_unit, _pc, _val) \ 8707 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd15, (_val)) 8708 #define WRITE_WC40_XFI_BD1_USER_PRBS_STATUS_0_REGISTERr(_unit, _pc, _val) \ 8709 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd15, (_val)) 8710 #define MODIFY_WC40_XFI_BD1_USER_PRBS_STATUS_0_REGISTERr(_unit, _pc, _val, _mask) \ 8711 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd15, (_val), (_mask)) 8712 8713 /* PRBS 31 Test Window 0 Register */ 8714 #define READ_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTERr(_unit, _pc, _val) \ 8715 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd16, (_val)) 8716 #define WRITE_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTERr(_unit, _pc, _val) \ 8717 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd16, (_val)) 8718 #define MODIFY_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTERr(_unit, _pc, _val, _mask) \ 8719 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd16, (_val), (_mask)) 8720 8721 /* Pattern insertion control register */ 8722 #define READ_WC40_XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTERr(_unit, _pc, _val) \ 8723 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000cd18, (_val)) 8724 #define WRITE_WC40_XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTERr(_unit, _pc, _val) \ 8725 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000cd18, (_val)) 8726 #define MODIFY_WC40_XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTERr(_unit, _pc, _val, _mask) \ 8727 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000cd18, (_val), (_mask)) 8728 8729 8730 8731 /**************************************************************************** 8732 * Warpcore_USER_microBlk 8733 */ 8734 /* ramWord Register */ 8735 #define READ_WC40_MICROBLK_RAMWORDr(_unit, _pc, _val) \ 8736 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffc0, (_val)) 8737 #define WRITE_WC40_MICROBLK_RAMWORDr(_unit, _pc, _val) \ 8738 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc0, (_val)) 8739 #define MODIFY_WC40_MICROBLK_RAMWORDr(_unit, _pc, _val, _mask) \ 8740 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc0, (_val), (_mask)) 8741 8742 /* Adress Register */ 8743 #define READ_WC40_MICROBLK_ADDRESSr(_unit, _pc, _val) \ 8744 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffc1, (_val)) 8745 #define WRITE_WC40_MICROBLK_ADDRESSr(_unit, _pc, _val) \ 8746 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc1, (_val)) 8747 #define MODIFY_WC40_MICROBLK_ADDRESSr(_unit, _pc, _val, _mask) \ 8748 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc1, (_val), (_mask)) 8749 8750 /* Command Register */ 8751 #define READ_WC40_MICROBLK_COMMANDr(_unit, _pc, _val) \ 8752 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffc2, (_val)) 8753 #define WRITE_WC40_MICROBLK_COMMANDr(_unit, _pc, _val) \ 8754 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc2, (_val)) 8755 #define MODIFY_WC40_MICROBLK_COMMANDr(_unit, _pc, _val, _mask) \ 8756 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc2, (_val), (_mask)) 8757 8758 /* Write Data Register */ 8759 #define READ_WC40_MICROBLK_WRDATAr(_unit, _pc, _val) \ 8760 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffc3, (_val)) 8761 #define WRITE_WC40_MICROBLK_WRDATAr(_unit, _pc, _val) \ 8762 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc3, (_val)) 8763 #define MODIFY_WC40_MICROBLK_WRDATAr(_unit, _pc, _val, _mask) \ 8764 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc3, (_val), (_mask)) 8765 8766 /* Read Data Register */ 8767 #define READ_WC40_MICROBLK_RDDATAr(_unit, _pc, _val) \ 8768 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffc4, (_val)) 8769 #define WRITE_WC40_MICROBLK_RDDATAr(_unit, _pc, _val) \ 8770 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc4, (_val)) 8771 #define MODIFY_WC40_MICROBLK_RDDATAr(_unit, _pc, _val, _mask) \ 8772 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc4, (_val), (_mask)) 8773 8774 /* MDIO to 8051 FSM Status Register */ 8775 #define READ_WC40_MICROBLK_DOWNLOAD_STATUSr(_unit, _pc, _val) \ 8776 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffc5, (_val)) 8777 #define WRITE_WC40_MICROBLK_DOWNLOAD_STATUSr(_unit, _pc, _val) \ 8778 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc5, (_val)) 8779 #define MODIFY_WC40_MICROBLK_DOWNLOAD_STATUSr(_unit, _pc, _val, _mask) \ 8780 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc5, (_val), (_mask)) 8781 8782 /* 8051 SFR FSM status */ 8783 #define READ_WC40_MICROBLK_SFR_STATUSr(_unit, _pc, _val) \ 8784 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffc6, (_val)) 8785 #define WRITE_WC40_MICROBLK_SFR_STATUSr(_unit, _pc, _val) \ 8786 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc6, (_val)) 8787 #define MODIFY_WC40_MICROBLK_SFR_STATUSr(_unit, _pc, _val, _mask) \ 8788 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc6, (_val), (_mask)) 8789 8790 /* Command Register 4 */ 8791 #define READ_WC40_MICROBLK_COMMAND4r(_unit, _pc, _val) \ 8792 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffc7, (_val)) 8793 #define WRITE_WC40_MICROBLK_COMMAND4r(_unit, _pc, _val) \ 8794 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc7, (_val)) 8795 #define MODIFY_WC40_MICROBLK_COMMAND4r(_unit, _pc, _val, _mask) \ 8796 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc7, (_val), (_mask)) 8797 8798 /* External station to uC mailbox */ 8799 #define READ_WC40_MICROBLK_MDIO_UC_MAILBOXr(_unit, _pc, _val) \ 8800 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffc8, (_val)) 8801 #define WRITE_WC40_MICROBLK_MDIO_UC_MAILBOXr(_unit, _pc, _val) \ 8802 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc8, (_val)) 8803 #define MODIFY_WC40_MICROBLK_MDIO_UC_MAILBOXr(_unit, _pc, _val, _mask) \ 8804 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc8, (_val), (_mask)) 8805 8806 /* uC to external station mailbox */ 8807 #define READ_WC40_MICROBLK_UC_MDIO_MAILBOXr(_unit, _pc, _val) \ 8808 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffc9, (_val)) 8809 #define WRITE_WC40_MICROBLK_UC_MDIO_MAILBOXr(_unit, _pc, _val) \ 8810 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc9, (_val)) 8811 #define MODIFY_WC40_MICROBLK_UC_MDIO_MAILBOXr(_unit, _pc, _val, _mask) \ 8812 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc9, (_val), (_mask)) 8813 8814 /* Command Register 2 */ 8815 #define READ_WC40_MICROBLK_COMMAND2r(_unit, _pc, _val) \ 8816 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffca, (_val)) 8817 #define WRITE_WC40_MICROBLK_COMMAND2r(_unit, _pc, _val) \ 8818 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffca, (_val)) 8819 #define MODIFY_WC40_MICROBLK_COMMAND2r(_unit, _pc, _val, _mask) \ 8820 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffca, (_val), (_mask)) 8821 8822 /* wdog_evnt_cnt Register */ 8823 #define READ_WC40_MICROBLK_WDOG_EVNT_CNTr(_unit, _pc, _val) \ 8824 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffcb, (_val)) 8825 #define WRITE_WC40_MICROBLK_WDOG_EVNT_CNTr(_unit, _pc, _val) \ 8826 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffcb, (_val)) 8827 #define MODIFY_WC40_MICROBLK_WDOG_EVNT_CNTr(_unit, _pc, _val, _mask) \ 8828 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffcb, (_val), (_mask)) 8829 8830 /* Command Register 3 */ 8831 #define READ_WC40_MICROBLK_COMMAND3r(_unit, _pc, _val) \ 8832 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffcc, (_val)) 8833 #define WRITE_WC40_MICROBLK_COMMAND3r(_unit, _pc, _val) \ 8834 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffcc, (_val)) 8835 #define MODIFY_WC40_MICROBLK_COMMAND3r(_unit, _pc, _val, _mask) \ 8836 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffcc, (_val), (_mask)) 8837 8838 /* Muxed Micro Timer (lower timer[15:0]) */ 8839 #define READ_WC40_MICROBLK_TIMER_LOWER16r(_unit, _pc, _val) \ 8840 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffcd, (_val)) 8841 #define WRITE_WC40_MICROBLK_TIMER_LOWER16r(_unit, _pc, _val) \ 8842 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffcd, (_val)) 8843 #define MODIFY_WC40_MICROBLK_TIMER_LOWER16r(_unit, _pc, _val, _mask) \ 8844 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffcd, (_val), (_mask)) 8845 8846 /* Muxed Micro Timer (upper timer[31:16]) */ 8847 #define READ_WC40_MICROBLK_TIMER_UPPER16r(_unit, _pc, _val) \ 8848 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffce, (_val)) 8849 #define WRITE_WC40_MICROBLK_TIMER_UPPER16r(_unit, _pc, _val) \ 8850 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffce, (_val)) 8851 #define MODIFY_WC40_MICROBLK_TIMER_UPPER16r(_unit, _pc, _val, _mask) \ 8852 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffce, (_val), (_mask)) 8853 8854 8855 8856 /**************************************************************************** 8857 * Warpcore_USER_aerBlk 8858 */ 8859 /* Address Expansion Register */ 8860 #define READ_WC40_AERBLK_AERr(_unit, _pc, _val) \ 8861 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffde, (_val)) 8862 #define WRITE_WC40_AERBLK_AERr(_unit, _pc, _val) \ 8863 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffde, (_val)) 8864 #define MODIFY_WC40_AERBLK_AERr(_unit, _pc, _val, _mask) \ 8865 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffde, (_val), (_mask)) 8866 8867 8868 8869 /**************************************************************************** 8870 * Warpcore_USER_Combo_IEEE0 8871 */ 8872 /* IEEE MII control register */ 8873 #define READ_WC40_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \ 8874 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffe0, (_val)) 8875 #define WRITE_WC40_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \ 8876 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe0, (_val)) 8877 #define MODIFY_WC40_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val, _mask) \ 8878 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe0, (_val), (_mask)) 8879 8880 /* IEEE MII status register */ 8881 #define READ_WC40_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \ 8882 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffe1, (_val)) 8883 #define WRITE_WC40_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \ 8884 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe1, (_val)) 8885 #define MODIFY_WC40_COMBO_IEEE0_MIISTATr(_unit, _pc, _val, _mask) \ 8886 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe1, (_val), (_mask)) 8887 8888 /* IEEE phy ID LSByte register */ 8889 #define READ_WC40_COMBO_IEEE0_ID1r(_unit, _pc, _val) \ 8890 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffe2, (_val)) 8891 #define WRITE_WC40_COMBO_IEEE0_ID1r(_unit, _pc, _val) \ 8892 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe2, (_val)) 8893 #define MODIFY_WC40_COMBO_IEEE0_ID1r(_unit, _pc, _val, _mask) \ 8894 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe2, (_val), (_mask)) 8895 8896 /* IEEE phy ID MSByte register */ 8897 #define READ_WC40_COMBO_IEEE0_ID2r(_unit, _pc, _val) \ 8898 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffe3, (_val)) 8899 #define WRITE_WC40_COMBO_IEEE0_ID2r(_unit, _pc, _val) \ 8900 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe3, (_val)) 8901 #define MODIFY_WC40_COMBO_IEEE0_ID2r(_unit, _pc, _val, _mask) \ 8902 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe3, (_val), (_mask)) 8903 8904 /* IEEE auto-negotiation advertised abilities register */ 8905 #define READ_WC40_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \ 8906 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffe4, (_val)) 8907 #define WRITE_WC40_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \ 8908 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe4, (_val)) 8909 #define MODIFY_WC40_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val, _mask) \ 8910 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe4, (_val), (_mask)) 8911 8912 /* IEEE auto-negotiation link partner abilities register */ 8913 #define READ_WC40_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \ 8914 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffe5, (_val)) 8915 #define WRITE_WC40_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \ 8916 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe5, (_val)) 8917 #define MODIFY_WC40_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val, _mask) \ 8918 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe5, (_val), (_mask)) 8919 8920 /* IEEE auto-negotiation expansion register */ 8921 #define READ_WC40_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \ 8922 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffe6, (_val)) 8923 #define WRITE_WC40_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \ 8924 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe6, (_val)) 8925 #define MODIFY_WC40_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val, _mask) \ 8926 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe6, (_val), (_mask)) 8927 8928 /* IEEE auto-negotiation next page register */ 8929 #define READ_WC40_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val) \ 8930 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffe7, (_val)) 8931 #define WRITE_WC40_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val) \ 8932 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe7, (_val)) 8933 #define MODIFY_WC40_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val, _mask) \ 8934 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe7, (_val), (_mask)) 8935 8936 /* IEEE auto-negotiation link partner next page register */ 8937 #define READ_WC40_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val) \ 8938 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffe8, (_val)) 8939 #define WRITE_WC40_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val) \ 8940 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe8, (_val)) 8941 #define MODIFY_WC40_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val, _mask) \ 8942 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe8, (_val), (_mask)) 8943 8944 /* IEEE MII extended status register */ 8945 #define READ_WC40_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val) \ 8946 WC40_REG_READ((_unit), (_pc), 0x00, 0x0000ffef, (_val)) 8947 #define WRITE_WC40_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val) \ 8948 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffef, (_val)) 8949 #define MODIFY_WC40_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val, _mask) \ 8950 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffef, (_val), (_mask)) 8951 8952 8953 8954 /**************************************************************************** 8955 * Warpcore_IEEE_PMD_PMD_ieee0Blk 8956 */ 8957 /* PMD Control 1 */ 8958 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _val) \ 8959 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000000, (_val)) 8960 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _val) \ 8961 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000000, (_val)) 8962 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _val, _mask) \ 8963 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000000, (_val), (_mask)) 8964 8965 /* PMD Status 1 */ 8966 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _val) \ 8967 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000001, (_val)) 8968 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _val) \ 8969 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000001, (_val)) 8970 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _val, _mask) \ 8971 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000001, (_val), (_mask)) 8972 8973 /* PMD Device ID [15:0] */ 8974 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _val) \ 8975 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000002, (_val)) 8976 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _val) \ 8977 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000002, (_val)) 8978 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _val, _mask) \ 8979 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000002, (_val), (_mask)) 8980 8981 /* PMD Device ID [31:16] */ 8982 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _val) \ 8983 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000003, (_val)) 8984 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _val) \ 8985 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000003, (_val)) 8986 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _val, _mask) \ 8987 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000003, (_val), (_mask)) 8988 8989 /* PMD Speed Ability */ 8990 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _val) \ 8991 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000004, (_val)) 8992 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _val) \ 8993 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000004, (_val)) 8994 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _val, _mask) \ 8995 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000004, (_val), (_mask)) 8996 8997 /* PMD Devices in Package 2 */ 8998 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _val) \ 8999 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000005, (_val)) 9000 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _val) \ 9001 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000005, (_val)) 9002 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _val, _mask) \ 9003 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000005, (_val), (_mask)) 9004 9005 /* PMD Devices in Package 1 */ 9006 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _val) \ 9007 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000006, (_val)) 9008 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _val) \ 9009 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000006, (_val)) 9010 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _val, _mask) \ 9011 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000006, (_val), (_mask)) 9012 9013 /* PMD Control 2 */ 9014 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _val) \ 9015 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000007, (_val)) 9016 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _val) \ 9017 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000007, (_val)) 9018 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _val, _mask) \ 9019 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000007, (_val), (_mask)) 9020 9021 /* PMD Status 2 */ 9022 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _val) \ 9023 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000008, (_val)) 9024 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _val) \ 9025 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000008, (_val)) 9026 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _val, _mask) \ 9027 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000008, (_val), (_mask)) 9028 9029 /* PMD Transmit Disable */ 9030 #define READ_WC40_PMD_IEEE0BLK_PMD_TXDISABLEr(_unit, _pc, _val) \ 9031 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000009, (_val)) 9032 #define WRITE_WC40_PMD_IEEE0BLK_PMD_TXDISABLEr(_unit, _pc, _val) \ 9033 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000009, (_val)) 9034 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_TXDISABLEr(_unit, _pc, _val, _mask) \ 9035 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000009, (_val), (_mask)) 9036 9037 /* PMD Receive Signal Detect */ 9038 #define READ_WC40_PMD_IEEE0BLK_PMD_RXSIGDETr(_unit, _pc, _val) \ 9039 WC40_REG_READ((_unit), (_pc), 0x00, 0x0800000a, (_val)) 9040 #define WRITE_WC40_PMD_IEEE0BLK_PMD_RXSIGDETr(_unit, _pc, _val) \ 9041 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0800000a, (_val)) 9042 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_RXSIGDETr(_unit, _pc, _val, _mask) \ 9043 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0800000a, (_val), (_mask)) 9044 9045 /* PMD Extended Ability */ 9046 #define READ_WC40_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _val) \ 9047 WC40_REG_READ((_unit), (_pc), 0x00, 0x0800000b, (_val)) 9048 #define WRITE_WC40_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _val) \ 9049 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0800000b, (_val)) 9050 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _val, _mask) \ 9051 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0800000b, (_val), (_mask)) 9052 9053 9054 9055 /**************************************************************************** 9056 * Warpcore_IEEE_PMD_PMD_ieee9Blk 9057 */ 9058 /* TenGBASE_KR PMD control register 150 */ 9059 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150r(_unit, _pc, _val) \ 9060 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000096, (_val)) 9061 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150r(_unit, _pc, _val) \ 9062 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000096, (_val)) 9063 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150r(_unit, _pc, _val, _mask) \ 9064 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000096, (_val), (_mask)) 9065 9066 /* TenGBASE_KR PMD status register 151 */ 9067 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151r(_unit, _pc, _val) \ 9068 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000097, (_val)) 9069 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151r(_unit, _pc, _val) \ 9070 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000097, (_val)) 9071 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151r(_unit, _pc, _val, _mask) \ 9072 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000097, (_val), (_mask)) 9073 9074 /* TenGBASE_KR LP coefficient upd 152 */ 9075 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152r(_unit, _pc, _val) \ 9076 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000098, (_val)) 9077 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152r(_unit, _pc, _val) \ 9078 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000098, (_val)) 9079 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152r(_unit, _pc, _val, _mask) \ 9080 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000098, (_val), (_mask)) 9081 9082 /* TenGBASE_KR LP status report reg 153 */ 9083 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153r(_unit, _pc, _val) \ 9084 WC40_REG_READ((_unit), (_pc), 0x00, 0x08000099, (_val)) 9085 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153r(_unit, _pc, _val) \ 9086 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x08000099, (_val)) 9087 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153r(_unit, _pc, _val, _mask) \ 9088 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x08000099, (_val), (_mask)) 9089 9090 /* TenGBASE_KR LD coefficient upd 154 */ 9091 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154r(_unit, _pc, _val) \ 9092 WC40_REG_READ((_unit), (_pc), 0x00, 0x0800009a, (_val)) 9093 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154r(_unit, _pc, _val) \ 9094 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0800009a, (_val)) 9095 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154r(_unit, _pc, _val, _mask) \ 9096 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0800009a, (_val), (_mask)) 9097 9098 /* TenGBASE_KR LD status report reg 155 */ 9099 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155r(_unit, _pc, _val) \ 9100 WC40_REG_READ((_unit), (_pc), 0x00, 0x0800009b, (_val)) 9101 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155r(_unit, _pc, _val) \ 9102 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x0800009b, (_val)) 9103 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155r(_unit, _pc, _val, _mask) \ 9104 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x0800009b, (_val), (_mask)) 9105 9106 9107 9108 /**************************************************************************** 9109 * Warpcore_IEEE_PMD_PMD_ieee10Blk 9110 */ 9111 /* PMD 1000BASE-KX control */ 9112 #define READ_WC40_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _val) \ 9113 WC40_REG_READ((_unit), (_pc), 0x00, 0x080000a0, (_val)) 9114 #define WRITE_WC40_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _val) \ 9115 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x080000a0, (_val)) 9116 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _val, _mask) \ 9117 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x080000a0, (_val), (_mask)) 9118 9119 /* PMD 1000BASE-KX status */ 9120 #define READ_WC40_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _val) \ 9121 WC40_REG_READ((_unit), (_pc), 0x00, 0x080000a1, (_val)) 9122 #define WRITE_WC40_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _val) \ 9123 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x080000a1, (_val)) 9124 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _val, _mask) \ 9125 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x080000a1, (_val), (_mask)) 9126 9127 /* "FEC ability register" */ 9128 #define READ_WC40_PMD_IEEE10BLK_PMD_FECABILITYr(_unit, _pc, _val) \ 9129 WC40_REG_READ((_unit), (_pc), 0x00, 0x080000aa, (_val)) 9130 #define WRITE_WC40_PMD_IEEE10BLK_PMD_FECABILITYr(_unit, _pc, _val) \ 9131 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x080000aa, (_val)) 9132 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_FECABILITYr(_unit, _pc, _val, _mask) \ 9133 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x080000aa, (_val), (_mask)) 9134 9135 /* "FEC control register" */ 9136 #define READ_WC40_PMD_IEEE10BLK_PMD_FECCONTROLr(_unit, _pc, _val) \ 9137 WC40_REG_READ((_unit), (_pc), 0x00, 0x080000ab, (_val)) 9138 #define WRITE_WC40_PMD_IEEE10BLK_PMD_FECCONTROLr(_unit, _pc, _val) \ 9139 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x080000ab, (_val)) 9140 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_FECCONTROLr(_unit, _pc, _val, _mask) \ 9141 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x080000ab, (_val), (_mask)) 9142 9143 /* "FEC corrected blocks counter [15:0]" */ 9144 #define READ_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSLr(_unit, _pc, _val) \ 9145 WC40_REG_READ((_unit), (_pc), 0x00, 0x080000ac, (_val)) 9146 #define WRITE_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSLr(_unit, _pc, _val) \ 9147 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x080000ac, (_val)) 9148 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSLr(_unit, _pc, _val, _mask) \ 9149 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x080000ac, (_val), (_mask)) 9150 9151 /* "FEC corrected blocks counter [31:16]" */ 9152 #define READ_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSHr(_unit, _pc, _val) \ 9153 WC40_REG_READ((_unit), (_pc), 0x00, 0x080000ad, (_val)) 9154 #define WRITE_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSHr(_unit, _pc, _val) \ 9155 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x080000ad, (_val)) 9156 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSHr(_unit, _pc, _val, _mask) \ 9157 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x080000ad, (_val), (_mask)) 9158 9159 /* "FEC uncorrected blocks counter [15:0]" */ 9160 #define READ_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _val) \ 9161 WC40_REG_READ((_unit), (_pc), 0x00, 0x080000ae, (_val)) 9162 #define WRITE_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _val) \ 9163 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x080000ae, (_val)) 9164 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _val, _mask) \ 9165 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x080000ae, (_val), (_mask)) 9166 9167 /* "FEC uncorrected blocks counter [31:16]" */ 9168 #define READ_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _val) \ 9169 WC40_REG_READ((_unit), (_pc), 0x00, 0x080000af, (_val)) 9170 #define WRITE_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _val) \ 9171 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x080000af, (_val)) 9172 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _val, _mask) \ 9173 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x080000af, (_val), (_mask)) 9174 9175 9176 9177 /**************************************************************************** 9178 * Warpcore_IEEE_PCS_PCS_ieee0Blk 9179 */ 9180 /* PCS Control 1 */ 9181 #define READ_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL1r(_unit, _pc, _val) \ 9182 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000000, (_val)) 9183 #define WRITE_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL1r(_unit, _pc, _val) \ 9184 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000000, (_val)) 9185 #define MODIFY_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL1r(_unit, _pc, _val, _mask) \ 9186 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000000, (_val), (_mask)) 9187 9188 /* PCS Status 1 */ 9189 #define READ_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS1r(_unit, _pc, _val) \ 9190 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000001, (_val)) 9191 #define WRITE_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS1r(_unit, _pc, _val) \ 9192 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000001, (_val)) 9193 #define MODIFY_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS1r(_unit, _pc, _val, _mask) \ 9194 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000001, (_val), (_mask)) 9195 9196 /* PCS Control 2 */ 9197 #define READ_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL2r(_unit, _pc, _val) \ 9198 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000007, (_val)) 9199 #define WRITE_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL2r(_unit, _pc, _val) \ 9200 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000007, (_val)) 9201 #define MODIFY_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL2r(_unit, _pc, _val, _mask) \ 9202 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000007, (_val), (_mask)) 9203 9204 /* P Status 2 */ 9205 #define READ_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS2r(_unit, _pc, _val) \ 9206 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000008, (_val)) 9207 #define WRITE_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS2r(_unit, _pc, _val) \ 9208 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000008, (_val)) 9209 #define MODIFY_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS2r(_unit, _pc, _val, _mask) \ 9210 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000008, (_val), (_mask)) 9211 9212 9213 9214 /**************************************************************************** 9215 * Warpcore_IEEE_PCS_PCS_ieee1Blk 9216 */ 9217 /* XGXS lane Status */ 9218 #define READ_WC40_PCS_IEEE1BLK_PCS_LANESTATUSr(_unit, _pc, _val) \ 9219 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000018, (_val)) 9220 #define WRITE_WC40_PCS_IEEE1BLK_PCS_LANESTATUSr(_unit, _pc, _val) \ 9221 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000018, (_val)) 9222 #define MODIFY_WC40_PCS_IEEE1BLK_PCS_LANESTATUSr(_unit, _pc, _val, _mask) \ 9223 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000018, (_val), (_mask)) 9224 9225 /* XGXS Test Control */ 9226 #define READ_WC40_PCS_IEEE1BLK_PCS_IEEETESTCONTROLr(_unit, _pc, _val) \ 9227 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000019, (_val)) 9228 #define WRITE_WC40_PCS_IEEE1BLK_PCS_IEEETESTCONTROLr(_unit, _pc, _val) \ 9229 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000019, (_val)) 9230 #define MODIFY_WC40_PCS_IEEE1BLK_PCS_IEEETESTCONTROLr(_unit, _pc, _val, _mask) \ 9231 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000019, (_val), (_mask)) 9232 9233 9234 9235 /**************************************************************************** 9236 * Warpcore_IEEE_PCS_PCS_ieee2Blk 9237 */ 9238 /* 10GBASE-R PCS status 1 */ 9239 #define READ_WC40_PCS_IEEE2BLK_PCS_STATUS1r(_unit, _pc, _val) \ 9240 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000020, (_val)) 9241 #define WRITE_WC40_PCS_IEEE2BLK_PCS_STATUS1r(_unit, _pc, _val) \ 9242 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000020, (_val)) 9243 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_STATUS1r(_unit, _pc, _val, _mask) \ 9244 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000020, (_val), (_mask)) 9245 9246 /* 10GBASE-R PCS status 2 */ 9247 #define READ_WC40_PCS_IEEE2BLK_PCS_STATUS2r(_unit, _pc, _val) \ 9248 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000021, (_val)) 9249 #define WRITE_WC40_PCS_IEEE2BLK_PCS_STATUS2r(_unit, _pc, _val) \ 9250 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000021, (_val)) 9251 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_STATUS2r(_unit, _pc, _val, _mask) \ 9252 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000021, (_val), (_mask)) 9253 9254 /* 10GBASE-R PCS test pattern seed A word bits 15:0 */ 9255 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDA0r(_unit, _pc, _val) \ 9256 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000022, (_val)) 9257 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDA0r(_unit, _pc, _val) \ 9258 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000022, (_val)) 9259 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDA0r(_unit, _pc, _val, _mask) \ 9260 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000022, (_val), (_mask)) 9261 9262 /* 10GBASE-R PCS test pattern seed A word bits 31;16 */ 9263 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDA1r(_unit, _pc, _val) \ 9264 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000023, (_val)) 9265 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDA1r(_unit, _pc, _val) \ 9266 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000023, (_val)) 9267 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDA1r(_unit, _pc, _val, _mask) \ 9268 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000023, (_val), (_mask)) 9269 9270 /* 10GBASE-R PCS test pattern seed A word bits 47:32 */ 9271 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDA2r(_unit, _pc, _val) \ 9272 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000024, (_val)) 9273 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDA2r(_unit, _pc, _val) \ 9274 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000024, (_val)) 9275 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDA2r(_unit, _pc, _val, _mask) \ 9276 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000024, (_val), (_mask)) 9277 9278 /* 10GBASE-R PCS test pattern seed A word bits 57:48 */ 9279 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDA3r(_unit, _pc, _val) \ 9280 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000025, (_val)) 9281 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDA3r(_unit, _pc, _val) \ 9282 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000025, (_val)) 9283 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDA3r(_unit, _pc, _val, _mask) \ 9284 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000025, (_val), (_mask)) 9285 9286 /* 10GBASE-R PCS test pattern seed B word bits 15:0 */ 9287 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDB0r(_unit, _pc, _val) \ 9288 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000026, (_val)) 9289 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDB0r(_unit, _pc, _val) \ 9290 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000026, (_val)) 9291 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDB0r(_unit, _pc, _val, _mask) \ 9292 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000026, (_val), (_mask)) 9293 9294 /* 10GBASE-R PCS test pattern seed B word bits 31;16 */ 9295 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDB1r(_unit, _pc, _val) \ 9296 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000027, (_val)) 9297 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDB1r(_unit, _pc, _val) \ 9298 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000027, (_val)) 9299 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDB1r(_unit, _pc, _val, _mask) \ 9300 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000027, (_val), (_mask)) 9301 9302 /* 10GBASE-R PCS test pattern seed B word bits 47:32 */ 9303 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDB2r(_unit, _pc, _val) \ 9304 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000028, (_val)) 9305 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDB2r(_unit, _pc, _val) \ 9306 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000028, (_val)) 9307 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDB2r(_unit, _pc, _val, _mask) \ 9308 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000028, (_val), (_mask)) 9309 9310 /* 10GBASE-R PCS test pattern seed B word bits 57:48 */ 9311 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDB3r(_unit, _pc, _val) \ 9312 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000029, (_val)) 9313 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDB3r(_unit, _pc, _val) \ 9314 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000029, (_val)) 9315 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDB3r(_unit, _pc, _val, _mask) \ 9316 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000029, (_val), (_mask)) 9317 9318 /* 10GBASE-R PCS test-pattern control */ 9319 #define READ_WC40_PCS_IEEE2BLK_PCS_TPCONTROLr(_unit, _pc, _val) \ 9320 WC40_REG_READ((_unit), (_pc), 0x00, 0x1800002a, (_val)) 9321 #define WRITE_WC40_PCS_IEEE2BLK_PCS_TPCONTROLr(_unit, _pc, _val) \ 9322 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x1800002a, (_val)) 9323 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_TPCONTROLr(_unit, _pc, _val, _mask) \ 9324 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x1800002a, (_val), (_mask)) 9325 9326 /* 10GBASE-R PCS test pattern error counter */ 9327 #define READ_WC40_PCS_IEEE2BLK_PCS_TPERRCOUNTERr(_unit, _pc, _val) \ 9328 WC40_REG_READ((_unit), (_pc), 0x00, 0x1800002b, (_val)) 9329 #define WRITE_WC40_PCS_IEEE2BLK_PCS_TPERRCOUNTERr(_unit, _pc, _val) \ 9330 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x1800002b, (_val)) 9331 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_TPERRCOUNTERr(_unit, _pc, _val, _mask) \ 9332 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x1800002b, (_val), (_mask)) 9333 9334 /* 40G/100GBASE-R BER high order counter */ 9335 #define READ_WC40_PCS_IEEE2BLK_BER_HOr(_unit, _pc, _val) \ 9336 WC40_REG_READ((_unit), (_pc), 0x00, 0x1800002c, (_val)) 9337 #define WRITE_WC40_PCS_IEEE2BLK_BER_HOr(_unit, _pc, _val) \ 9338 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x1800002c, (_val)) 9339 #define MODIFY_WC40_PCS_IEEE2BLK_BER_HOr(_unit, _pc, _val, _mask) \ 9340 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x1800002c, (_val), (_mask)) 9341 9342 /* 40G/100GBASE-R Errored blocks high order counter */ 9343 #define READ_WC40_PCS_IEEE2BLK_ERRORED_BLOCKS_HOr(_unit, _pc, _val) \ 9344 WC40_REG_READ((_unit), (_pc), 0x00, 0x1800002d, (_val)) 9345 #define WRITE_WC40_PCS_IEEE2BLK_ERRORED_BLOCKS_HOr(_unit, _pc, _val) \ 9346 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x1800002d, (_val)) 9347 #define MODIFY_WC40_PCS_IEEE2BLK_ERRORED_BLOCKS_HOr(_unit, _pc, _val, _mask) \ 9348 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x1800002d, (_val), (_mask)) 9349 9350 9351 9352 /**************************************************************************** 9353 * Warpcore_IEEE_PCS_PCS_ieee3Blk 9354 */ 9355 /* Multi-lane BASE-R PCS alignment status register 1 */ 9356 #define READ_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_1r(_unit, _pc, _val) \ 9357 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000032, (_val)) 9358 #define WRITE_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_1r(_unit, _pc, _val) \ 9359 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000032, (_val)) 9360 #define MODIFY_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_1r(_unit, _pc, _val, _mask) \ 9361 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000032, (_val), (_mask)) 9362 9363 /* Multi-lane BASE-R PCS alignment status register 3 */ 9364 #define READ_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_3r(_unit, _pc, _val) \ 9365 WC40_REG_READ((_unit), (_pc), 0x00, 0x18000034, (_val)) 9366 #define WRITE_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_3r(_unit, _pc, _val) \ 9367 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x18000034, (_val)) 9368 #define MODIFY_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_3r(_unit, _pc, _val, _mask) \ 9369 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x18000034, (_val), (_mask)) 9370 9371 9372 9373 /**************************************************************************** 9374 * Warpcore_IEEE_PCS_PCS_ieee5Blk 9375 */ 9376 /* BIP error counter, lane 0 and lane 1 */ 9377 #define READ_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01r(_unit, _pc, _val) \ 9378 WC40_REG_READ((_unit), (_pc), 0x00, 0x1800005a, (_val)) 9379 #define WRITE_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01r(_unit, _pc, _val) \ 9380 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x1800005a, (_val)) 9381 #define MODIFY_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01r(_unit, _pc, _val, _mask) \ 9382 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x1800005a, (_val), (_mask)) 9383 9384 /* BIP error counter, lane 2 and lane 3 */ 9385 #define READ_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23r(_unit, _pc, _val) \ 9386 WC40_REG_READ((_unit), (_pc), 0x00, 0x1800005b, (_val)) 9387 #define WRITE_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23r(_unit, _pc, _val) \ 9388 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x1800005b, (_val)) 9389 #define MODIFY_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23r(_unit, _pc, _val, _mask) \ 9390 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x1800005b, (_val), (_mask)) 9391 9392 9393 9394 /**************************************************************************** 9395 * Warpcore_IEEE_CL73_AN_ieee0Blk 9396 */ 9397 /* AN Control 1 */ 9398 #define READ_WC40_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _val) \ 9399 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000000, (_val)) 9400 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _val) \ 9401 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000000, (_val)) 9402 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _val, _mask) \ 9403 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000000, (_val), (_mask)) 9404 9405 /* AN Status 1 */ 9406 #define READ_WC40_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _val) \ 9407 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000001, (_val)) 9408 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _val) \ 9409 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000001, (_val)) 9410 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _val, _mask) \ 9411 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000001, (_val), (_mask)) 9412 9413 /* AN Device ID [15:0] */ 9414 #define READ_WC40_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _val) \ 9415 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000002, (_val)) 9416 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _val) \ 9417 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000002, (_val)) 9418 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _val, _mask) \ 9419 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000002, (_val), (_mask)) 9420 9421 /* AN Device ID [31:16] */ 9422 #define READ_WC40_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _val) \ 9423 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000003, (_val)) 9424 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _val) \ 9425 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000003, (_val)) 9426 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _val, _mask) \ 9427 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000003, (_val), (_mask)) 9428 9429 /* AN Devices in Package 2 */ 9430 #define READ_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _val) \ 9431 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000005, (_val)) 9432 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _val) \ 9433 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000005, (_val)) 9434 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _val, _mask) \ 9435 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000005, (_val), (_mask)) 9436 9437 /* AN Devices in Package 1 */ 9438 #define READ_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _val) \ 9439 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000006, (_val)) 9440 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _val) \ 9441 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000006, (_val)) 9442 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _val, _mask) \ 9443 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000006, (_val), (_mask)) 9444 9445 9446 9447 /**************************************************************************** 9448 * Warpcore_IEEE_CL73_AN_ieee1Blk 9449 */ 9450 /* AN advertisement 0 */ 9451 #define READ_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _val) \ 9452 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000010, (_val)) 9453 #define WRITE_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _val) \ 9454 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000010, (_val)) 9455 #define MODIFY_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _val, _mask) \ 9456 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000010, (_val), (_mask)) 9457 9458 /* AN advertisement 1 */ 9459 #define READ_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _val) \ 9460 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000011, (_val)) 9461 #define WRITE_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _val) \ 9462 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000011, (_val)) 9463 #define MODIFY_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _val, _mask) \ 9464 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000011, (_val), (_mask)) 9465 9466 /* AN advertisement 2 */ 9467 #define READ_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT2r(_unit, _pc, _val) \ 9468 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000012, (_val)) 9469 #define WRITE_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT2r(_unit, _pc, _val) \ 9470 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000012, (_val)) 9471 #define MODIFY_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT2r(_unit, _pc, _val, _mask) \ 9472 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000012, (_val), (_mask)) 9473 9474 /* AN LP base page ability 0 */ 9475 #define READ_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _val) \ 9476 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000013, (_val)) 9477 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _val) \ 9478 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000013, (_val)) 9479 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _val, _mask) \ 9480 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000013, (_val), (_mask)) 9481 9482 /* AN LP base page ability 1 */ 9483 #define READ_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _val) \ 9484 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000014, (_val)) 9485 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _val) \ 9486 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000014, (_val)) 9487 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _val, _mask) \ 9488 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000014, (_val), (_mask)) 9489 9490 /* AN LP base page ability 2 */ 9491 #define READ_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2r(_unit, _pc, _val) \ 9492 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000015, (_val)) 9493 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2r(_unit, _pc, _val) \ 9494 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000015, (_val)) 9495 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2r(_unit, _pc, _val, _mask) \ 9496 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000015, (_val), (_mask)) 9497 9498 /* AN XNP transmit 0 */ 9499 #define READ_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _val) \ 9500 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000016, (_val)) 9501 #define WRITE_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _val) \ 9502 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000016, (_val)) 9503 #define MODIFY_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _val, _mask) \ 9504 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000016, (_val), (_mask)) 9505 9506 /* AN XNP transmit 1 */ 9507 #define READ_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _val) \ 9508 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000017, (_val)) 9509 #define WRITE_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _val) \ 9510 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000017, (_val)) 9511 #define MODIFY_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _val, _mask) \ 9512 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000017, (_val), (_mask)) 9513 9514 /* AN XNP transmit 2 */ 9515 #define READ_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _val) \ 9516 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000018, (_val)) 9517 #define WRITE_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _val) \ 9518 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000018, (_val)) 9519 #define MODIFY_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _val, _mask) \ 9520 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000018, (_val), (_mask)) 9521 9522 /* AN LP XNP ability 0 */ 9523 #define READ_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _val) \ 9524 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000019, (_val)) 9525 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _val) \ 9526 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000019, (_val)) 9527 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _val, _mask) \ 9528 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000019, (_val), (_mask)) 9529 9530 /* AN LP XNP ability 1 */ 9531 #define READ_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _val) \ 9532 WC40_REG_READ((_unit), (_pc), 0x00, 0x3800001a, (_val)) 9533 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _val) \ 9534 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x3800001a, (_val)) 9535 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _val, _mask) \ 9536 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x3800001a, (_val), (_mask)) 9537 9538 /* AN LP XNP ability 2 */ 9539 #define READ_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _val) \ 9540 WC40_REG_READ((_unit), (_pc), 0x00, 0x3800001b, (_val)) 9541 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _val) \ 9542 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x3800001b, (_val)) 9543 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _val, _mask) \ 9544 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x3800001b, (_val), (_mask)) 9545 9546 9547 9548 /**************************************************************************** 9549 * Warpcore_IEEE_CL73_AN_ieee3Blk 9550 */ 9551 /* Autonegotiation Backplane Ethernet status */ 9552 #define READ_WC40_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _val) \ 9553 WC40_REG_READ((_unit), (_pc), 0x00, 0x38000030, (_val)) 9554 #define WRITE_WC40_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _val) \ 9555 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x38000030, (_val)) 9556 #define MODIFY_WC40_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _val, _mask) \ 9557 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x38000030, (_val), (_mask)) 9558 9559 /* EEE advertisement */ 9560 #define READ_WC40_AN_IEEE3BLK_EEE_ADVr(_unit, _pc, _val) \ 9561 WC40_REG_READ((_unit), (_pc), 0x00, 0x3800003c, (_val)) 9562 #define WRITE_WC40_AN_IEEE3BLK_EEE_ADVr(_unit, _pc, _val) \ 9563 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x3800003c, (_val)) 9564 #define MODIFY_WC40_AN_IEEE3BLK_EEE_ADVr(_unit, _pc, _val, _mask) \ 9565 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x3800003c, (_val), (_mask)) 9566 9567 /* LP EEE advertisement */ 9568 #define READ_WC40_AN_IEEE3BLK_EEE_LP_ADVr(_unit, _pc, _val) \ 9569 WC40_REG_READ((_unit), (_pc), 0x00, 0x3800003d, (_val)) 9570 #define WRITE_WC40_AN_IEEE3BLK_EEE_LP_ADVr(_unit, _pc, _val) \ 9571 WC40_REG_WRITE((_unit), (_pc), 0x00, 0x3800003d, (_val)) 9572 #define MODIFY_WC40_AN_IEEE3BLK_EEE_LP_ADVr(_unit, _pc, _val, _mask) \ 9573 WC40_REG_MODIFY((_unit), (_pc), 0x00, 0x3800003d, (_val), (_mask)) 9574 9575 /**************************************************************************** 9576 * Warpcore_IEEE_CL22_ieee0Blk 9577 */ 9578 /**************************************************************************** 9579 * ieee0Blk :: MIICntl 9580 */ 9581 /* ieee0Blk :: MIICntl :: rst_hw [15:15] */ 9582 #define IEEE0BLK_MIICNTL_RST_HW_MASK 0x8000 9583 #define IEEE0BLK_MIICNTL_RST_HW_ALIGN 0 9584 #define IEEE0BLK_MIICNTL_RST_HW_BITS 1 9585 #define IEEE0BLK_MIICNTL_RST_HW_SHIFT 15 9586 9587 /* ieee0Blk :: MIICntl :: gloopback [14:14] */ 9588 #define IEEE0BLK_MIICNTL_GLOOPBACK_MASK 0x4000 9589 #define IEEE0BLK_MIICNTL_GLOOPBACK_ALIGN 0 9590 #define IEEE0BLK_MIICNTL_GLOOPBACK_BITS 1 9591 #define IEEE0BLK_MIICNTL_GLOOPBACK_SHIFT 14 9592 9593 /* ieee0Blk :: MIICntl :: manual_speed0 [13:13] */ 9594 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_MASK 0x2000 9595 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_ALIGN 0 9596 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_BITS 1 9597 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_SHIFT 13 9598 9599 /* ieee0Blk :: MIICntl :: autoneg_enable [12:12] */ 9600 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_MASK 0x1000 9601 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_ALIGN 0 9602 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_BITS 1 9603 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_SHIFT 12 9604 9605 /* ieee0Blk :: MIICntl :: pwrdwn_sw [11:11] */ 9606 #define IEEE0BLK_MIICNTL_PWRDWN_SW_MASK 0x0800 9607 #define IEEE0BLK_MIICNTL_PWRDWN_SW_ALIGN 0 9608 #define IEEE0BLK_MIICNTL_PWRDWN_SW_BITS 1 9609 #define IEEE0BLK_MIICNTL_PWRDWN_SW_SHIFT 11 9610 9611 /* ieee0Blk :: MIICntl :: reserved0 [10:10] */ 9612 #define IEEE0BLK_MIICNTL_RESERVED0_MASK 0x0400 9613 #define IEEE0BLK_MIICNTL_RESERVED0_ALIGN 0 9614 #define IEEE0BLK_MIICNTL_RESERVED0_BITS 1 9615 #define IEEE0BLK_MIICNTL_RESERVED0_SHIFT 10 9616 9617 /* ieee0Blk :: MIICntl :: restart_autoneg [09:09] */ 9618 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_MASK 0x0200 9619 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_ALIGN 0 9620 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_BITS 1 9621 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_SHIFT 9 9622 9623 /* ieee0Blk :: MIICntl :: full_duplex [08:08] */ 9624 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_MASK 0x0100 9625 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_ALIGN 0 9626 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_BITS 1 9627 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_SHIFT 8 9628 9629 /* ieee0Blk :: MIICntl :: collision_test_en [07:07] */ 9630 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_MASK 0x0080 9631 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_ALIGN 0 9632 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_BITS 1 9633 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_SHIFT 7 9634 9635 /* ieee0Blk :: MIICntl :: manual_speed1 [06:06] */ 9636 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_MASK 0x0040 9637 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_ALIGN 0 9638 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_BITS 1 9639 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_SHIFT 6 9640 9641 /* ieee0Blk :: MIICntl :: reserved1 [05:00] */ 9642 #define IEEE0BLK_MIICNTL_RESERVED1_MASK 0x003f 9643 #define IEEE0BLK_MIICNTL_RESERVED1_ALIGN 0 9644 #define IEEE0BLK_MIICNTL_RESERVED1_BITS 6 9645 #define IEEE0BLK_MIICNTL_RESERVED1_SHIFT 0 9646 9647 9648 /**************************************************************************** 9649 * ieee0Blk :: MIIStat 9650 */ 9651 /* ieee0Blk :: MIIStat :: s100BASE_T4_capable [15:15] */ 9652 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_MASK 0x8000 9653 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_ALIGN 0 9654 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_BITS 1 9655 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_SHIFT 15 9656 9657 /* ieee0Blk :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */ 9658 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000 9659 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0 9660 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1 9661 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14 9662 9663 /* ieee0Blk :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */ 9664 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000 9665 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0 9666 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1 9667 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13 9668 9669 /* ieee0Blk :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */ 9670 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x1000 9671 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0 9672 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS 1 9673 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12 9674 9675 /* ieee0Blk :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */ 9676 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x0800 9677 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0 9678 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS 1 9679 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11 9680 9681 /* ieee0Blk :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */ 9682 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400 9683 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0 9684 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1 9685 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10 9686 9687 /* ieee0Blk :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */ 9688 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200 9689 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0 9690 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1 9691 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9 9692 9693 /* ieee0Blk :: MIIStat :: extended_status [08:08] */ 9694 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_MASK 0x0100 9695 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_ALIGN 0 9696 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_BITS 1 9697 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_SHIFT 8 9698 9699 /* ieee0Blk :: MIIStat :: reserved0 [07:07] */ 9700 #define IEEE0BLK_MIISTAT_RESERVED0_MASK 0x0080 9701 #define IEEE0BLK_MIISTAT_RESERVED0_ALIGN 0 9702 #define IEEE0BLK_MIISTAT_RESERVED0_BITS 1 9703 #define IEEE0BLK_MIISTAT_RESERVED0_SHIFT 7 9704 9705 /* ieee0Blk :: MIIStat :: mf_preamble_supression [06:06] */ 9706 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK 0x0040 9707 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN 0 9708 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS 1 9709 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT 6 9710 9711 /* ieee0Blk :: MIIStat :: autoneg_complete [05:05] */ 9712 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_MASK 0x0020 9713 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_ALIGN 0 9714 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_BITS 1 9715 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_SHIFT 5 9716 9717 /* ieee0Blk :: MIIStat :: remote_fault [04:04] */ 9718 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_MASK 0x0010 9719 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_ALIGN 0 9720 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_BITS 1 9721 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_SHIFT 4 9722 9723 /* ieee0Blk :: MIIStat :: autoneg_ability [03:03] */ 9724 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_MASK 0x0008 9725 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_ALIGN 0 9726 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_BITS 1 9727 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_SHIFT 3 9728 9729 /* ieee0Blk :: MIIStat :: link_status [02:02] */ 9730 #define IEEE0BLK_MIISTAT_LINK_STATUS_MASK 0x0004 9731 #define IEEE0BLK_MIISTAT_LINK_STATUS_ALIGN 0 9732 #define IEEE0BLK_MIISTAT_LINK_STATUS_BITS 1 9733 #define IEEE0BLK_MIISTAT_LINK_STATUS_SHIFT 2 9734 9735 /* ieee0Blk :: MIIStat :: jabber_detect [01:01] */ 9736 #define IEEE0BLK_MIISTAT_JABBER_DETECT_MASK 0x0002 9737 #define IEEE0BLK_MIISTAT_JABBER_DETECT_ALIGN 0 9738 #define IEEE0BLK_MIISTAT_JABBER_DETECT_BITS 1 9739 #define IEEE0BLK_MIISTAT_JABBER_DETECT_SHIFT 1 9740 9741 /* ieee0Blk :: MIIStat :: extended_capability [00:00] */ 9742 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_MASK 0x0001 9743 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_ALIGN 0 9744 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_BITS 1 9745 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_SHIFT 0 9746 9747 9748 /**************************************************************************** 9749 * ieee0Blk :: Id1 9750 */ 9751 /* ieee0Blk :: Id1 :: regid [15:00] */ 9752 #define IEEE0BLK_ID1_REGID_MASK 0xffff 9753 #define IEEE0BLK_ID1_REGID_ALIGN 0 9754 #define IEEE0BLK_ID1_REGID_BITS 16 9755 #define IEEE0BLK_ID1_REGID_SHIFT 0 9756 9757 9758 /**************************************************************************** 9759 * ieee0Blk :: Id2 9760 */ 9761 /* ieee0Blk :: Id2 :: regid [15:00] */ 9762 #define IEEE0BLK_ID2_REGID_MASK 0xffff 9763 #define IEEE0BLK_ID2_REGID_ALIGN 0 9764 #define IEEE0BLK_ID2_REGID_BITS 16 9765 #define IEEE0BLK_ID2_REGID_SHIFT 0 9766 9767 9768 /**************************************************************************** 9769 * ieee0Blk :: AutoNegAdv 9770 */ 9771 /* ieee0Blk :: AutoNegAdv :: next_page [15:15] */ 9772 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_MASK 0x8000 9773 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_ALIGN 0 9774 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_BITS 1 9775 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_SHIFT 15 9776 9777 /* ieee0Blk :: AutoNegAdv :: reserved0 [14:14] */ 9778 #define IEEE0BLK_AUTONEGADV_RESERVED0_MASK 0x4000 9779 #define IEEE0BLK_AUTONEGADV_RESERVED0_ALIGN 0 9780 #define IEEE0BLK_AUTONEGADV_RESERVED0_BITS 1 9781 #define IEEE0BLK_AUTONEGADV_RESERVED0_SHIFT 14 9782 9783 /* ieee0Blk :: AutoNegAdv :: remote_fault [13:12] */ 9784 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_MASK 0x3000 9785 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_ALIGN 0 9786 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_BITS 2 9787 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_SHIFT 12 9788 9789 /* ieee0Blk :: AutoNegAdv :: reserved1 [11:09] */ 9790 #define IEEE0BLK_AUTONEGADV_RESERVED1_MASK 0x0e00 9791 #define IEEE0BLK_AUTONEGADV_RESERVED1_ALIGN 0 9792 #define IEEE0BLK_AUTONEGADV_RESERVED1_BITS 3 9793 #define IEEE0BLK_AUTONEGADV_RESERVED1_SHIFT 9 9794 9795 /* ieee0Blk :: AutoNegAdv :: pause [08:07] */ 9796 #define IEEE0BLK_AUTONEGADV_PAUSE_MASK 0x0180 9797 #define IEEE0BLK_AUTONEGADV_PAUSE_ALIGN 0 9798 #define IEEE0BLK_AUTONEGADV_PAUSE_BITS 2 9799 #define IEEE0BLK_AUTONEGADV_PAUSE_SHIFT 7 9800 9801 /* ieee0Blk :: AutoNegAdv :: half_duplex [06:06] */ 9802 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_MASK 0x0040 9803 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_ALIGN 0 9804 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_BITS 1 9805 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_SHIFT 6 9806 9807 /* ieee0Blk :: AutoNegAdv :: full_duplex [05:05] */ 9808 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_MASK 0x0020 9809 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_ALIGN 0 9810 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_BITS 1 9811 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_SHIFT 5 9812 9813 /* ieee0Blk :: AutoNegAdv :: reserved2 [04:00] */ 9814 #define IEEE0BLK_AUTONEGADV_RESERVED2_MASK 0x001f 9815 #define IEEE0BLK_AUTONEGADV_RESERVED2_ALIGN 0 9816 #define IEEE0BLK_AUTONEGADV_RESERVED2_BITS 5 9817 #define IEEE0BLK_AUTONEGADV_RESERVED2_SHIFT 0 9818 9819 9820 /**************************************************************************** 9821 * ieee0Blk :: AutoNegLPAbil 9822 */ 9823 /* ieee0Blk :: AutoNegLPAbil :: next_page [15:15] */ 9824 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_MASK 0x8000 9825 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_ALIGN 0 9826 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_BITS 1 9827 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_SHIFT 15 9828 9829 /* ieee0Blk :: AutoNegLPAbil :: acknowledge [14:14] */ 9830 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_MASK 0x4000 9831 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN 0 9832 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_BITS 1 9833 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT 14 9834 9835 /* ieee0Blk :: AutoNegLPAbil :: remote_fault [13:12] */ 9836 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_MASK 0x3000 9837 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_ALIGN 0 9838 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_BITS 2 9839 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_SHIFT 12 9840 9841 /* ieee0Blk :: AutoNegLPAbil :: reserved0 [11:09] */ 9842 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_MASK 0x0e00 9843 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_ALIGN 0 9844 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_BITS 3 9845 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_SHIFT 9 9846 9847 /* ieee0Blk :: AutoNegLPAbil :: pause [08:07] */ 9848 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_MASK 0x0180 9849 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_ALIGN 0 9850 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_BITS 2 9851 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_SHIFT 7 9852 9853 /* ieee0Blk :: AutoNegLPAbil :: half_duplex [06:06] */ 9854 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_MASK 0x0040 9855 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_ALIGN 0 9856 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_BITS 1 9857 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_SHIFT 6 9858 9859 /* ieee0Blk :: AutoNegLPAbil :: full_duplex [05:05] */ 9860 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_MASK 0x0020 9861 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_ALIGN 0 9862 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_BITS 1 9863 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_SHIFT 5 9864 9865 /* ieee0Blk :: AutoNegLPAbil :: reserved1 [04:01] */ 9866 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_MASK 0x001e 9867 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_ALIGN 0 9868 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_BITS 4 9869 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_SHIFT 1 9870 9871 /* ieee0Blk :: AutoNegLPAbil :: sgmii_mode [00:00] */ 9872 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_MASK 0x0001 9873 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_ALIGN 0 9874 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_BITS 1 9875 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_SHIFT 0 9876 9877 9878 /**************************************************************************** 9879 * ieee0Blk :: AutoNegExp 9880 */ 9881 /* ieee0Blk :: AutoNegExp :: reserved0 [15:03] */ 9882 #define IEEE0BLK_AUTONEGEXP_RESERVED0_MASK 0xfff8 9883 #define IEEE0BLK_AUTONEGEXP_RESERVED0_ALIGN 0 9884 #define IEEE0BLK_AUTONEGEXP_RESERVED0_BITS 13 9885 #define IEEE0BLK_AUTONEGEXP_RESERVED0_SHIFT 3 9886 9887 /* ieee0Blk :: AutoNegExp :: next_page_ability [02:02] */ 9888 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK 0x0004 9889 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN 0 9890 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS 1 9891 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT 2 9892 9893 /* ieee0Blk :: AutoNegExp :: page_received [01:01] */ 9894 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_MASK 0x0002 9895 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_ALIGN 0 9896 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_BITS 1 9897 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_SHIFT 1 9898 9899 /* ieee0Blk :: AutoNegExp :: reserved1 [00:00] */ 9900 #define IEEE0BLK_AUTONEGEXP_RESERVED1_MASK 0x0001 9901 #define IEEE0BLK_AUTONEGEXP_RESERVED1_ALIGN 0 9902 #define IEEE0BLK_AUTONEGEXP_RESERVED1_BITS 1 9903 #define IEEE0BLK_AUTONEGEXP_RESERVED1_SHIFT 0 9904 9905 9906 /**************************************************************************** 9907 * ieee0Blk :: AutoNegNP 9908 */ 9909 /* ieee0Blk :: AutoNegNP :: Next_Page [15:15] */ 9910 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_MASK 0x8000 9911 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_ALIGN 0 9912 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_BITS 1 9913 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_SHIFT 15 9914 9915 /* ieee0Blk :: AutoNegNP :: Ack [14:14] */ 9916 #define IEEE0BLK_AUTONEGNP_ACK_MASK 0x4000 9917 #define IEEE0BLK_AUTONEGNP_ACK_ALIGN 0 9918 #define IEEE0BLK_AUTONEGNP_ACK_BITS 1 9919 #define IEEE0BLK_AUTONEGNP_ACK_SHIFT 14 9920 9921 /* ieee0Blk :: AutoNegNP :: Message_Page [13:13] */ 9922 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_MASK 0x2000 9923 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_ALIGN 0 9924 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_BITS 1 9925 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_SHIFT 13 9926 9927 /* ieee0Blk :: AutoNegNP :: Ack2 [12:12] */ 9928 #define IEEE0BLK_AUTONEGNP_ACK2_MASK 0x1000 9929 #define IEEE0BLK_AUTONEGNP_ACK2_ALIGN 0 9930 #define IEEE0BLK_AUTONEGNP_ACK2_BITS 1 9931 #define IEEE0BLK_AUTONEGNP_ACK2_SHIFT 12 9932 9933 /* ieee0Blk :: AutoNegNP :: Toggle [11:11] */ 9934 #define IEEE0BLK_AUTONEGNP_TOGGLE_MASK 0x0800 9935 #define IEEE0BLK_AUTONEGNP_TOGGLE_ALIGN 0 9936 #define IEEE0BLK_AUTONEGNP_TOGGLE_BITS 1 9937 #define IEEE0BLK_AUTONEGNP_TOGGLE_SHIFT 11 9938 9939 /* ieee0Blk :: AutoNegNP :: Message [10:00] */ 9940 #define IEEE0BLK_AUTONEGNP_MESSAGE_MASK 0x07ff 9941 #define IEEE0BLK_AUTONEGNP_MESSAGE_ALIGN 0 9942 #define IEEE0BLK_AUTONEGNP_MESSAGE_BITS 11 9943 #define IEEE0BLK_AUTONEGNP_MESSAGE_SHIFT 0 9944 9945 9946 /**************************************************************************** 9947 * ieee0Blk :: AutoNegLPAbil2 9948 */ 9949 /* ieee0Blk :: AutoNegLPAbil2 :: Next_Page [15:15] */ 9950 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_MASK 0x8000 9951 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_ALIGN 0 9952 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_BITS 1 9953 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_SHIFT 15 9954 9955 /* ieee0Blk :: AutoNegLPAbil2 :: Ack [14:14] */ 9956 #define IEEE0BLK_AUTONEGLPABIL2_ACK_MASK 0x4000 9957 #define IEEE0BLK_AUTONEGLPABIL2_ACK_ALIGN 0 9958 #define IEEE0BLK_AUTONEGLPABIL2_ACK_BITS 1 9959 #define IEEE0BLK_AUTONEGLPABIL2_ACK_SHIFT 14 9960 9961 /* ieee0Blk :: AutoNegLPAbil2 :: Message_Page [13:13] */ 9962 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_MASK 0x2000 9963 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN 0 9964 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_BITS 1 9965 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT 13 9966 9967 /* ieee0Blk :: AutoNegLPAbil2 :: Ack2 [12:12] */ 9968 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_MASK 0x1000 9969 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_ALIGN 0 9970 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_BITS 1 9971 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_SHIFT 12 9972 9973 /* ieee0Blk :: AutoNegLPAbil2 :: Toggle [11:11] */ 9974 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_MASK 0x0800 9975 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_ALIGN 0 9976 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_BITS 1 9977 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_SHIFT 11 9978 9979 /* ieee0Blk :: AutoNegLPAbil2 :: Message [10:00] */ 9980 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_MASK 0x07ff 9981 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_ALIGN 0 9982 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_BITS 11 9983 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_SHIFT 0 9984 9985 9986 /**************************************************************************** 9987 * ieee0Blk :: MIIextStat 9988 */ 9989 /* ieee0Blk :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */ 9990 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000 9991 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0 9992 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1 9993 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15 9994 9995 /* ieee0Blk :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */ 9996 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000 9997 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0 9998 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1 9999 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14 10000 10001 /* ieee0Blk :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */ 10002 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000 10003 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0 10004 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1 10005 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13 10006 10007 /* ieee0Blk :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */ 10008 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000 10009 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0 10010 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1 10011 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12 10012 10013 /* ieee0Blk :: MIIextStat :: reserved0 [11:00] */ 10014 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_MASK 0x0fff 10015 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_ALIGN 0 10016 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_BITS 12 10017 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_SHIFT 0 10018 10019 10020 /**************************************************************************** 10021 * Warpcore_USER_XgxsBlk0 10022 */ 10023 /**************************************************************************** 10024 * XgxsBlk0 :: xgxsControl 10025 */ 10026 /* XgxsBlk0 :: xgxsControl :: pgen_en [15:15] */ 10027 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_MASK 0x8000 10028 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_ALIGN 0 10029 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_BITS 1 10030 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_SHIFT 15 10031 10032 /* XgxsBlk0 :: xgxsControl :: pcmp_en [14:14] */ 10033 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_MASK 0x4000 10034 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_ALIGN 0 10035 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_BITS 1 10036 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_SHIFT 14 10037 10038 /* XgxsBlk0 :: xgxsControl :: start_sequencer [13:13] */ 10039 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_MASK 0x2000 10040 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_ALIGN 0 10041 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_BITS 1 10042 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_SHIFT 13 10043 10044 /* XgxsBlk0 :: xgxsControl :: reset_anlg [12:12] */ 10045 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_MASK 0x1000 10046 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_ALIGN 0 10047 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_BITS 1 10048 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_SHIFT 12 10049 10050 /* XgxsBlk0 :: xgxsControl :: mode_10g [11:08] */ 10051 #define XGXSBLK0_XGXSCONTROL_MODE_10G_MASK 0x0f00 10052 #define XGXSBLK0_XGXSCONTROL_MODE_10G_ALIGN 0 10053 #define XGXSBLK0_XGXSCONTROL_MODE_10G_BITS 4 10054 #define XGXSBLK0_XGXSCONTROL_MODE_10G_SHIFT 8 10055 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS 0 10056 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXG_nCC 1 10057 #define XGXSBLK0_XGXSCONTROL_MODE_10G_IndLane_OS8 4 10058 #define XGXSBLK0_XGXSCONTROL_MODE_10G_IndLane_OS5 5 10059 #define XGXSBLK0_XGXSCONTROL_MODE_10G_IndLane_OS6 6 10060 #define XGXSBLK0_XGXSCONTROL_MODE_10G_PCI 7 10061 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_nLQ 8 10062 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_nLQnCC 9 10063 #define XGXSBLK0_XGXSCONTROL_MODE_10G_PBypass 10 10064 #define XGXSBLK0_XGXSCONTROL_MODE_10G_PBypass_nDSK 11 10065 #define XGXSBLK0_XGXSCONTROL_MODE_10G_ComboCoreMode 12 10066 #define XGXSBLK0_XGXSCONTROL_MODE_10G_Clocks_off 15 10067 #define XGXSBLK0_XGXSCONTROL_MODE_10G_IndLane_XENIA 6 10068 10069 /* XgxsBlk0 :: xgxsControl :: pll_bypass [07:07] */ 10070 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_MASK 0x0080 10071 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_ALIGN 0 10072 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_BITS 1 10073 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_SHIFT 7 10074 10075 /* XgxsBlk0 :: xgxsControl :: rloop [06:06] */ 10076 #define XGXSBLK0_XGXSCONTROL_RLOOP_MASK 0x0040 10077 #define XGXSBLK0_XGXSCONTROL_RLOOP_ALIGN 0 10078 #define XGXSBLK0_XGXSCONTROL_RLOOP_BITS 1 10079 #define XGXSBLK0_XGXSCONTROL_RLOOP_SHIFT 6 10080 10081 /* XgxsBlk0 :: xgxsControl :: reserved0 [05:05] */ 10082 #define XGXSBLK0_XGXSCONTROL_RESERVED0_MASK 0x0020 10083 #define XGXSBLK0_XGXSCONTROL_RESERVED0_ALIGN 0 10084 #define XGXSBLK0_XGXSCONTROL_RESERVED0_BITS 1 10085 #define XGXSBLK0_XGXSCONTROL_RESERVED0_SHIFT 5 10086 10087 /* XgxsBlk0 :: xgxsControl :: mdio_cont_en [04:04] */ 10088 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_MASK 0x0010 10089 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_ALIGN 0 10090 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_BITS 1 10091 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_SHIFT 4 10092 10093 /* XgxsBlk0 :: xgxsControl :: cdet_en [03:03] */ 10094 #define XGXSBLK0_XGXSCONTROL_CDET_EN_MASK 0x0008 10095 #define XGXSBLK0_XGXSCONTROL_CDET_EN_ALIGN 0 10096 #define XGXSBLK0_XGXSCONTROL_CDET_EN_BITS 1 10097 #define XGXSBLK0_XGXSCONTROL_CDET_EN_SHIFT 3 10098 10099 /* XgxsBlk0 :: xgxsControl :: eden [02:02] */ 10100 #define XGXSBLK0_XGXSCONTROL_EDEN_MASK 0x0004 10101 #define XGXSBLK0_XGXSCONTROL_EDEN_ALIGN 0 10102 #define XGXSBLK0_XGXSCONTROL_EDEN_BITS 1 10103 #define XGXSBLK0_XGXSCONTROL_EDEN_SHIFT 2 10104 10105 /* XgxsBlk0 :: xgxsControl :: afrst_en [01:01] */ 10106 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_MASK 0x0002 10107 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_ALIGN 0 10108 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_BITS 1 10109 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_SHIFT 1 10110 10111 /* XgxsBlk0 :: xgxsControl :: txcko_div [00:00] */ 10112 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_MASK 0x0001 10113 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_ALIGN 0 10114 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_BITS 1 10115 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_SHIFT 0 10116 10117 10118 /**************************************************************************** 10119 * XgxsBlk0 :: xgxsStatus 10120 */ 10121 /* XgxsBlk0 :: xgxsStatus :: status_en [15:15] */ 10122 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_MASK 0x8000 10123 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_ALIGN 0 10124 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_BITS 1 10125 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_SHIFT 15 10126 10127 /* XgxsBlk0 :: xgxsStatus :: reserved0 [14:14] */ 10128 #define XGXSBLK0_XGXSSTATUS_RESERVED0_MASK 0x4000 10129 #define XGXSBLK0_XGXSSTATUS_RESERVED0_ALIGN 0 10130 #define XGXSBLK0_XGXSSTATUS_RESERVED0_BITS 1 10131 #define XGXSBLK0_XGXSSTATUS_RESERVED0_SHIFT 14 10132 10133 /* XgxsBlk0 :: xgxsStatus :: tx_remote_fault [13:13] */ 10134 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_MASK 0x2000 10135 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_ALIGN 0 10136 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_BITS 1 10137 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_SHIFT 13 10138 10139 /* XgxsBlk0 :: xgxsStatus :: rx_remote_fault [12:12] */ 10140 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_MASK 0x1000 10141 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_ALIGN 0 10142 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_BITS 1 10143 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_SHIFT 12 10144 10145 /* XgxsBlk0 :: xgxsStatus :: txpll_lock [11:11] */ 10146 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_MASK 0x0800 10147 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_ALIGN 0 10148 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_BITS 1 10149 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_SHIFT 11 10150 10151 /* XgxsBlk0 :: xgxsStatus :: txd_fifo_err [10:10] */ 10152 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_MASK 0x0400 10153 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_ALIGN 0 10154 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_BITS 1 10155 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_SHIFT 10 10156 10157 /* XgxsBlk0 :: xgxsStatus :: sequencer_done [09:09] */ 10158 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_MASK 0x0200 10159 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_ALIGN 0 10160 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_BITS 1 10161 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_SHIFT 9 10162 10163 /* XgxsBlk0 :: xgxsStatus :: sequencer_pass [08:08] */ 10164 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_MASK 0x0100 10165 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_ALIGN 0 10166 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_BITS 1 10167 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_SHIFT 8 10168 10169 /* XgxsBlk0 :: xgxsStatus :: rxferr [07:04] */ 10170 #define XGXSBLK0_XGXSSTATUS_RXFERR_MASK 0x00f0 10171 #define XGXSBLK0_XGXSSTATUS_RXFERR_ALIGN 0 10172 #define XGXSBLK0_XGXSSTATUS_RXFERR_BITS 4 10173 #define XGXSBLK0_XGXSSTATUS_RXFERR_SHIFT 4 10174 10175 /* XgxsBlk0 :: xgxsStatus :: pll_mode_afe [03:03] */ 10176 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_MASK 0x0008 10177 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_ALIGN 0 10178 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_BITS 1 10179 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_SHIFT 3 10180 10181 /* XgxsBlk0 :: xgxsStatus :: ckcmp_unflow [02:02] */ 10182 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_MASK 0x0004 10183 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_ALIGN 0 10184 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_BITS 1 10185 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_SHIFT 2 10186 10187 /* XgxsBlk0 :: xgxsStatus :: ckcmp_ovflow [01:01] */ 10188 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_MASK 0x0002 10189 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_ALIGN 0 10190 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_BITS 1 10191 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_SHIFT 1 10192 10193 /* XgxsBlk0 :: xgxsStatus :: skew_status [00:00] */ 10194 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_MASK 0x0001 10195 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_ALIGN 0 10196 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_BITS 1 10197 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_SHIFT 0 10198 10199 10200 /**************************************************************************** 10201 * XgxsBlk0 :: xgmiiIdle 10202 */ 10203 /* XgxsBlk0 :: xgmiiIdle :: I [15:08] */ 10204 #define XGXSBLK0_XGMIIIDLE_I_MASK 0xff00 10205 #define XGXSBLK0_XGMIIIDLE_I_ALIGN 0 10206 #define XGXSBLK0_XGMIIIDLE_I_BITS 8 10207 #define XGXSBLK0_XGMIIIDLE_I_SHIFT 8 10208 10209 /* XgxsBlk0 :: xgmiiIdle :: Ib [07:00] */ 10210 #define XGXSBLK0_XGMIIIDLE_IB_MASK 0x00ff 10211 #define XGXSBLK0_XGMIIIDLE_IB_ALIGN 0 10212 #define XGXSBLK0_XGMIIIDLE_IB_BITS 8 10213 #define XGXSBLK0_XGMIIIDLE_IB_SHIFT 0 10214 10215 10216 /**************************************************************************** 10217 * XgxsBlk0 :: xgmiiSync 10218 */ 10219 /* XgxsBlk0 :: xgmiiSync :: K [15:08] */ 10220 #define XGXSBLK0_XGMIISYNC_K_MASK 0xff00 10221 #define XGXSBLK0_XGMIISYNC_K_ALIGN 0 10222 #define XGXSBLK0_XGMIISYNC_K_BITS 8 10223 #define XGXSBLK0_XGMIISYNC_K_SHIFT 8 10224 10225 /* XgxsBlk0 :: xgmiiSync :: Kb [07:00] */ 10226 #define XGXSBLK0_XGMIISYNC_KB_MASK 0x00ff 10227 #define XGXSBLK0_XGMIISYNC_KB_ALIGN 0 10228 #define XGXSBLK0_XGMIISYNC_KB_BITS 8 10229 #define XGXSBLK0_XGMIISYNC_KB_SHIFT 0 10230 10231 10232 /**************************************************************************** 10233 * XgxsBlk0 :: xgmiiSkip 10234 */ 10235 /* XgxsBlk0 :: xgmiiSkip :: R [15:08] */ 10236 #define XGXSBLK0_XGMIISKIP_R_MASK 0xff00 10237 #define XGXSBLK0_XGMIISKIP_R_ALIGN 0 10238 #define XGXSBLK0_XGMIISKIP_R_BITS 8 10239 #define XGXSBLK0_XGMIISKIP_R_SHIFT 8 10240 10241 /* XgxsBlk0 :: xgmiiSkip :: Rb [07:00] */ 10242 #define XGXSBLK0_XGMIISKIP_RB_MASK 0x00ff 10243 #define XGXSBLK0_XGMIISKIP_RB_ALIGN 0 10244 #define XGXSBLK0_XGMIISKIP_RB_BITS 8 10245 #define XGXSBLK0_XGMIISKIP_RB_SHIFT 0 10246 10247 10248 /**************************************************************************** 10249 * XgxsBlk0 :: xgmiiSopEop 10250 */ 10251 /* XgxsBlk0 :: xgmiiSopEop :: S [15:08] */ 10252 #define XGXSBLK0_XGMIISOPEOP_S_MASK 0xff00 10253 #define XGXSBLK0_XGMIISOPEOP_S_ALIGN 0 10254 #define XGXSBLK0_XGMIISOPEOP_S_BITS 8 10255 #define XGXSBLK0_XGMIISOPEOP_S_SHIFT 8 10256 10257 /* XgxsBlk0 :: xgmiiSopEop :: T [07:00] */ 10258 #define XGXSBLK0_XGMIISOPEOP_T_MASK 0x00ff 10259 #define XGXSBLK0_XGMIISOPEOP_T_ALIGN 0 10260 #define XGXSBLK0_XGMIISOPEOP_T_BITS 8 10261 #define XGXSBLK0_XGMIISOPEOP_T_SHIFT 0 10262 10263 10264 /**************************************************************************** 10265 * XgxsBlk0 :: xgmiiAlign 10266 */ 10267 /* XgxsBlk0 :: xgmiiAlign :: E [15:08] */ 10268 #define XGXSBLK0_XGMIIALIGN_E_MASK 0xff00 10269 #define XGXSBLK0_XGMIIALIGN_E_ALIGN 0 10270 #define XGXSBLK0_XGMIIALIGN_E_BITS 8 10271 #define XGXSBLK0_XGMIIALIGN_E_SHIFT 8 10272 10273 /* XgxsBlk0 :: xgmiiAlign :: A [07:00] */ 10274 #define XGXSBLK0_XGMIIALIGN_A_MASK 0x00ff 10275 #define XGXSBLK0_XGMIIALIGN_A_ALIGN 0 10276 #define XGXSBLK0_XGMIIALIGN_A_BITS 8 10277 #define XGXSBLK0_XGMIIALIGN_A_SHIFT 0 10278 10279 10280 /**************************************************************************** 10281 * XgxsBlk0 :: xgmiiRcontrol 10282 */ 10283 /* XgxsBlk0 :: xgmiiRcontrol :: reserved0 [15:15] */ 10284 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_MASK 0x8000 10285 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_ALIGN 0 10286 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_BITS 1 10287 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_SHIFT 15 10288 10289 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf0_en [14:14] */ 10290 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_MASK 0x4000 10291 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_ALIGN 0 10292 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_BITS 1 10293 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_SHIFT 14 10294 10295 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf1_en [13:13] */ 10296 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_MASK 0x2000 10297 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_ALIGN 0 10298 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_BITS 1 10299 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_SHIFT 13 10300 10301 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf2_en [12:12] */ 10302 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_MASK 0x1000 10303 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_ALIGN 0 10304 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_BITS 1 10305 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_SHIFT 12 10306 10307 /* XgxsBlk0 :: xgmiiRcontrol :: force_inbndls_en [11:11] */ 10308 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_MASK 0x0800 10309 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_ALIGN 0 10310 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_BITS 1 10311 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_SHIFT 11 10312 10313 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_en [10:10] */ 10314 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_MASK 0x0400 10315 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_ALIGN 0 10316 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_BITS 1 10317 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_SHIFT 10 10318 10319 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_std_en [09:09] */ 10320 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_MASK 0x0200 10321 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_ALIGN 0 10322 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_BITS 1 10323 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_SHIFT 9 10324 10325 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_force [08:08] */ 10326 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_MASK 0x0100 10327 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_ALIGN 0 10328 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_BITS 1 10329 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_SHIFT 8 10330 10331 /* XgxsBlk0 :: xgmiiRcontrol :: reserved1 [07:07] */ 10332 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_MASK 0x0080 10333 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_ALIGN 0 10334 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_BITS 1 10335 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_SHIFT 7 10336 10337 /* XgxsBlk0 :: xgmiiRcontrol :: scr_en_4lane [06:06] */ 10338 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_MASK 0x0040 10339 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_ALIGN 0 10340 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_BITS 1 10341 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_SHIFT 6 10342 10343 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_noIPG_en [05:05] */ 10344 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_MASK 0x0020 10345 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_ALIGN 0 10346 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_BITS 1 10347 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_SHIFT 5 10348 10349 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_afrst_en [04:04] */ 10350 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_MASK 0x0010 10351 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_ALIGN 0 10352 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_BITS 1 10353 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_SHIFT 4 10354 10355 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_gt1_Icol_dis [03:03] */ 10356 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_MASK 0x0008 10357 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_ALIGN 0 10358 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_BITS 1 10359 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_SHIFT 3 10360 10361 /* XgxsBlk0 :: xgmiiRcontrol :: reserved2 [02:00] */ 10362 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_MASK 0x0007 10363 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_ALIGN 0 10364 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_BITS 3 10365 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_SHIFT 0 10366 10367 10368 /**************************************************************************** 10369 * XgxsBlk0 :: xgmiiTcontrol 10370 */ 10371 /* XgxsBlk0 :: xgmiiTcontrol :: swapen [15:15] */ 10372 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_MASK 0x8000 10373 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_ALIGN 0 10374 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_BITS 1 10375 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_SHIFT 15 10376 10377 /* XgxsBlk0 :: xgmiiTcontrol :: swap_lane_ind [14:14] */ 10378 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_MASK 0x4000 10379 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_ALIGN 0 10380 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_BITS 1 10381 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_SHIFT 14 10382 10383 /* XgxsBlk0 :: xgmiiTcontrol :: pn_sel [13:13] */ 10384 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_MASK 0x2000 10385 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_ALIGN 0 10386 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_BITS 1 10387 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_SHIFT 13 10388 10389 /* XgxsBlk0 :: xgmiiTcontrol :: reserved0 [12:09] */ 10390 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_MASK 0x1e00 10391 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_ALIGN 0 10392 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_BITS 4 10393 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_SHIFT 9 10394 10395 /* XgxsBlk0 :: xgmiiTcontrol :: alignstat_rxlf_en [08:08] */ 10396 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_MASK 0x0100 10397 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_ALIGN 0 10398 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_BITS 1 10399 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_SHIFT 8 10400 10401 /* XgxsBlk0 :: xgmiiTcontrol :: flip_txrx_lf [07:07] */ 10402 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_MASK 0x0080 10403 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_ALIGN 0 10404 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_BITS 1 10405 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_SHIFT 7 10406 10407 /* XgxsBlk0 :: xgmiiTcontrol :: xenpak_lfclr_en [06:06] */ 10408 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_MASK 0x0040 10409 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_ALIGN 0 10410 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_BITS 1 10411 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_SHIFT 6 10412 10413 /* XgxsBlk0 :: xgmiiTcontrol :: tx_xgmii_Tcol_old_en [05:05] */ 10414 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_MASK 0x0020 10415 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_ALIGN 0 10416 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_BITS 1 10417 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_SHIFT 5 10418 10419 /* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_IorRF_en [04:04] */ 10420 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_MASK 0x0010 10421 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_ALIGN 0 10422 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_BITS 1 10423 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_SHIFT 4 10424 10425 /* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_I_en [03:03] */ 10426 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_MASK 0x0008 10427 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_ALIGN 0 10428 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_BITS 1 10429 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_SHIFT 3 10430 10431 /* XgxsBlk0 :: xgmiiTcontrol :: reserved1 [02:00] */ 10432 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_MASK 0x0007 10433 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_ALIGN 0 10434 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_BITS 3 10435 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_SHIFT 0 10436 10437 10438 /**************************************************************************** 10439 * XgxsBlk0 :: xgmiiSwap 10440 */ 10441 /* XgxsBlk0 :: xgmiiSwap :: swap_count [15:00] */ 10442 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_MASK 0xffff 10443 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_ALIGN 0 10444 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_BITS 16 10445 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_SHIFT 0 10446 10447 10448 /**************************************************************************** 10449 * XgxsBlk0 :: lssLsid 10450 */ 10451 /* XgxsBlk0 :: lssLsid :: lss_ls_id [15:08] */ 10452 #define XGXSBLK0_LSSLSID_LSS_LS_ID_MASK 0xff00 10453 #define XGXSBLK0_LSSLSID_LSS_LS_ID_ALIGN 0 10454 #define XGXSBLK0_LSSLSID_LSS_LS_ID_BITS 8 10455 #define XGXSBLK0_LSSLSID_LSS_LS_ID_SHIFT 8 10456 10457 /* XgxsBlk0 :: lssLsid :: lss_domain_id [07:00] */ 10458 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_MASK 0x00ff 10459 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_ALIGN 0 10460 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_BITS 8 10461 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_SHIFT 0 10462 10463 10464 /**************************************************************************** 10465 * XgxsBlk0 :: lssTinfo 10466 */ 10467 /* XgxsBlk0 :: lssTinfo :: lss_function_id [15:08] */ 10468 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_MASK 0xff00 10469 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_ALIGN 0 10470 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_BITS 8 10471 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_SHIFT 8 10472 10473 /* XgxsBlk0 :: lssTinfo :: lssL_info_byte [07:00] */ 10474 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_MASK 0x00ff 10475 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_ALIGN 0 10476 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_BITS 8 10477 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_SHIFT 0 10478 10479 10480 /**************************************************************************** 10481 * XgxsBlk0 :: lssRinfo 10482 */ 10483 /* XgxsBlk0 :: lssRinfo :: control_en [15:15] */ 10484 #define XGXSBLK0_LSSRINFO_CONTROL_EN_MASK 0x8000 10485 #define XGXSBLK0_LSSRINFO_CONTROL_EN_ALIGN 0 10486 #define XGXSBLK0_LSSRINFO_CONTROL_EN_BITS 1 10487 #define XGXSBLK0_LSSRINFO_CONTROL_EN_SHIFT 15 10488 10489 /* XgxsBlk0 :: lssRinfo :: reserved0 [14:14] */ 10490 #define XGXSBLK0_LSSRINFO_RESERVED0_MASK 0x4000 10491 #define XGXSBLK0_LSSRINFO_RESERVED0_ALIGN 0 10492 #define XGXSBLK0_LSSRINFO_RESERVED0_BITS 1 10493 #define XGXSBLK0_LSSRINFO_RESERVED0_SHIFT 14 10494 10495 /* XgxsBlk0 :: lssRinfo :: lss_ls_id8 [13:13] */ 10496 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_MASK 0x2000 10497 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_ALIGN 0 10498 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_BITS 1 10499 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_SHIFT 13 10500 10501 /* XgxsBlk0 :: lssRinfo :: lss_domain_id8 [12:12] */ 10502 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_MASK 0x1000 10503 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_ALIGN 0 10504 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_BITS 1 10505 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_SHIFT 12 10506 10507 /* XgxsBlk0 :: lssRinfo :: lss_function_id8 [11:11] */ 10508 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_MASK 0x0800 10509 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_ALIGN 0 10510 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_BITS 1 10511 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_SHIFT 11 10512 10513 /* XgxsBlk0 :: lssRinfo :: lssL_info_byte8 [10:10] */ 10514 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_MASK 0x0400 10515 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_ALIGN 0 10516 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_BITS 1 10517 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_SHIFT 10 10518 10519 /* XgxsBlk0 :: lssRinfo :: reserved1 [09:09] */ 10520 #define XGXSBLK0_LSSRINFO_RESERVED1_MASK 0x0200 10521 #define XGXSBLK0_LSSRINFO_RESERVED1_ALIGN 0 10522 #define XGXSBLK0_LSSRINFO_RESERVED1_BITS 1 10523 #define XGXSBLK0_LSSRINFO_RESERVED1_SHIFT 9 10524 10525 /* XgxsBlk0 :: lssRinfo :: lssR_info_byte [08:00] */ 10526 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_MASK 0x01ff 10527 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_ALIGN 0 10528 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_BITS 9 10529 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_SHIFT 0 10530 10531 10532 /**************************************************************************** 10533 * XgxsBlk0 :: mmdSelect 10534 */ 10535 /* XgxsBlk0 :: mmdSelect :: multiPRTs_en [15:15] */ 10536 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_MASK 0x8000 10537 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_ALIGN 0 10538 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_BITS 1 10539 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_SHIFT 15 10540 10541 /* XgxsBlk0 :: mmdSelect :: multiMMDs_en [14:14] */ 10542 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_MASK 0x4000 10543 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_ALIGN 0 10544 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_BITS 1 10545 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_SHIFT 14 10546 10547 /* XgxsBlk0 :: mmdSelect :: reserved0 [13:04] */ 10548 #define XGXSBLK0_MMDSELECT_RESERVED0_MASK 0x3ff0 10549 #define XGXSBLK0_MMDSELECT_RESERVED0_ALIGN 0 10550 #define XGXSBLK0_MMDSELECT_RESERVED0_BITS 10 10551 #define XGXSBLK0_MMDSELECT_RESERVED0_SHIFT 4 10552 10553 /* XgxsBlk0 :: mmdSelect :: devAN_en [03:03] */ 10554 #define XGXSBLK0_MMDSELECT_DEVAN_EN_MASK 0x0008 10555 #define XGXSBLK0_MMDSELECT_DEVAN_EN_ALIGN 0 10556 #define XGXSBLK0_MMDSELECT_DEVAN_EN_BITS 1 10557 #define XGXSBLK0_MMDSELECT_DEVAN_EN_SHIFT 3 10558 10559 /* XgxsBlk0 :: mmdSelect :: devPMD_en [02:02] */ 10560 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_MASK 0x0004 10561 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_ALIGN 0 10562 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_BITS 1 10563 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_SHIFT 2 10564 10565 /* XgxsBlk0 :: mmdSelect :: devDEVAD_en [01:01] */ 10566 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_MASK 0x0002 10567 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_ALIGN 0 10568 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_BITS 1 10569 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_SHIFT 1 10570 10571 /* XgxsBlk0 :: mmdSelect :: devCL22_en [00:00] */ 10572 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_MASK 0x0001 10573 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_ALIGN 0 10574 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_BITS 1 10575 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_SHIFT 0 10576 10577 10578 /**************************************************************************** 10579 * XgxsBlk0 :: miscControl1 10580 */ 10581 /* XgxsBlk0 :: miscControl1 :: PMD_Lane3_tx_disable [15:15] */ 10582 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_MASK 0x8000 10583 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_ALIGN 0 10584 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_BITS 1 10585 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_SHIFT 15 10586 10587 /* XgxsBlk0 :: miscControl1 :: PMD_Lane2_tx_disable [14:14] */ 10588 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_MASK 0x4000 10589 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_ALIGN 0 10590 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_BITS 1 10591 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_SHIFT 14 10592 10593 /* XgxsBlk0 :: miscControl1 :: PMD_Lane1_tx_disable [13:13] */ 10594 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_MASK 0x2000 10595 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_ALIGN 0 10596 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_BITS 1 10597 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_SHIFT 13 10598 10599 /* XgxsBlk0 :: miscControl1 :: PMD_Lane0_tx_disable [12:12] */ 10600 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_MASK 0x1000 10601 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_ALIGN 0 10602 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_BITS 1 10603 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_SHIFT 12 10604 10605 /* XgxsBlk0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */ 10606 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK 0x0800 10607 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN 0 10608 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS 1 10609 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT 11 10610 10611 /* XgxsBlk0 :: miscControl1 :: PCS_dev_en_override [10:10] */ 10612 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_MASK 0x0400 10613 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_ALIGN 0 10614 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_BITS 1 10615 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_SHIFT 10 10616 10617 /* XgxsBlk0 :: miscControl1 :: PMD_dev_en_override [09:09] */ 10618 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_MASK 0x0200 10619 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_ALIGN 0 10620 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_BITS 1 10621 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_SHIFT 9 10622 10623 /* XgxsBlk0 :: miscControl1 :: reserved0 [08:08] */ 10624 #define XGXSBLK0_MISCCONTROL1_RESERVED0_MASK 0x0100 10625 #define XGXSBLK0_MISCCONTROL1_RESERVED0_ALIGN 0 10626 #define XGXSBLK0_MISCCONTROL1_RESERVED0_BITS 1 10627 #define XGXSBLK0_MISCCONTROL1_RESERVED0_SHIFT 8 10628 10629 /* XgxsBlk0 :: miscControl1 :: clear_linkdown [07:07] */ 10630 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_MASK 0x0080 10631 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_ALIGN 0 10632 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_BITS 1 10633 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_SHIFT 7 10634 10635 /* XgxsBlk0 :: miscControl1 :: latch_linkdown_enable [06:06] */ 10636 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_MASK 0x0040 10637 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_ALIGN 0 10638 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_BITS 1 10639 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_SHIFT 6 10640 10641 /* XgxsBlk0 :: miscControl1 :: reserved1 [05:05] */ 10642 #define XGXSBLK0_MISCCONTROL1_RESERVED1_MASK 0x0020 10643 #define XGXSBLK0_MISCCONTROL1_RESERVED1_ALIGN 0 10644 #define XGXSBLK0_MISCCONTROL1_RESERVED1_BITS 1 10645 #define XGXSBLK0_MISCCONTROL1_RESERVED1_SHIFT 5 10646 10647 /* XgxsBlk0 :: miscControl1 :: force_div5_for_lxck25 [04:04] */ 10648 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_MASK 0x0010 10649 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_ALIGN 0 10650 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_BITS 1 10651 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_SHIFT 4 10652 10653 /* XgxsBlk0 :: miscControl1 :: pardet10g_pwrdnLink_en [03:03] */ 10654 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_MASK 0x0008 10655 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_ALIGN 0 10656 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_BITS 1 10657 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_SHIFT 3 10658 10659 /* XgxsBlk0 :: miscControl1 :: invert_rx_sigdet [02:02] */ 10660 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_MASK 0x0004 10661 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_ALIGN 0 10662 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_BITS 1 10663 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_SHIFT 2 10664 10665 /* XgxsBlk0 :: miscControl1 :: ieee_blksel_autodet [01:01] */ 10666 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_MASK 0x0002 10667 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_ALIGN 0 10668 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_BITS 1 10669 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_SHIFT 1 10670 10671 /* XgxsBlk0 :: miscControl1 :: ieee_blksel_val [00:00] */ 10672 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_MASK 0x0001 10673 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_ALIGN 0 10674 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_BITS 1 10675 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_SHIFT 0 10676 10677 10678 /**************************************************************************** 10679 * XgxsBlk0 :: BlockAddress 10680 */ 10681 /* XgxsBlk0 :: BlockAddress :: reserved0 [15:15] */ 10682 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_MASK 0x8000 10683 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_ALIGN 0 10684 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_BITS 1 10685 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_SHIFT 15 10686 10687 /* XgxsBlk0 :: BlockAddress :: BlockAddress [14:04] */ 10688 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_MASK 0x7ff0 10689 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_ALIGN 0 10690 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_BITS 11 10691 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_SHIFT 4 10692 10693 /* XgxsBlk0 :: BlockAddress :: reserved1 [03:00] */ 10694 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_MASK 0x000f 10695 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_ALIGN 0 10696 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_BITS 4 10697 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_SHIFT 0 10698 10699 10700 /**************************************************************************** 10701 * Warpcore_USER_XgxsBlk1 10702 */ 10703 /**************************************************************************** 10704 * XgxsBlk1 :: deskew 10705 */ 10706 /* XgxsBlk1 :: deskew :: link_en [15:15] */ 10707 #define XGXSBLK1_DESKEW_LINK_EN_MASK 0x8000 10708 #define XGXSBLK1_DESKEW_LINK_EN_ALIGN 0 10709 #define XGXSBLK1_DESKEW_LINK_EN_BITS 1 10710 #define XGXSBLK1_DESKEW_LINK_EN_SHIFT 15 10711 10712 /* XgxsBlk1 :: deskew :: deskew_hyst_en [14:14] */ 10713 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_MASK 0x4000 10714 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_ALIGN 0 10715 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_BITS 1 10716 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_SHIFT 14 10717 10718 /* XgxsBlk1 :: deskew :: dswin [13:09] */ 10719 #define XGXSBLK1_DESKEW_DSWIN_MASK 0x3e00 10720 #define XGXSBLK1_DESKEW_DSWIN_ALIGN 0 10721 #define XGXSBLK1_DESKEW_DSWIN_BITS 5 10722 #define XGXSBLK1_DESKEW_DSWIN_SHIFT 9 10723 10724 /* XgxsBlk1 :: deskew :: mpwin [08:00] */ 10725 #define XGXSBLK1_DESKEW_MPWIN_MASK 0x01ff 10726 #define XGXSBLK1_DESKEW_MPWIN_ALIGN 0 10727 #define XGXSBLK1_DESKEW_MPWIN_BITS 9 10728 #define XGXSBLK1_DESKEW_MPWIN_SHIFT 0 10729 10730 10731 /**************************************************************************** 10732 * XgxsBlk1 :: link 10733 */ 10734 /* XgxsBlk1 :: link :: Acolwin [15:00] */ 10735 #define XGXSBLK1_LINK_ACOLWIN_MASK 0xffff 10736 #define XGXSBLK1_LINK_ACOLWIN_ALIGN 0 10737 #define XGXSBLK1_LINK_ACOLWIN_BITS 16 10738 #define XGXSBLK1_LINK_ACOLWIN_SHIFT 0 10739 10740 10741 /**************************************************************************** 10742 * XgxsBlk1 :: testRx 10743 */ 10744 /* XgxsBlk1 :: testRx :: reserved0 [15:08] */ 10745 #define XGXSBLK1_TESTRX_RESERVED0_MASK 0xff00 10746 #define XGXSBLK1_TESTRX_RESERVED0_ALIGN 0 10747 #define XGXSBLK1_TESTRX_RESERVED0_BITS 8 10748 #define XGXSBLK1_TESTRX_RESERVED0_SHIFT 8 10749 10750 /* XgxsBlk1 :: testRx :: rx_inBandMdio_Qfltr_en [07:07] */ 10751 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_MASK 0x0080 10752 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_ALIGN 0 10753 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_BITS 1 10754 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_SHIFT 7 10755 10756 /* XgxsBlk1 :: testRx :: link_force [06:06] */ 10757 #define XGXSBLK1_TESTRX_LINK_FORCE_MASK 0x0040 10758 #define XGXSBLK1_TESTRX_LINK_FORCE_ALIGN 0 10759 #define XGXSBLK1_TESTRX_LINK_FORCE_BITS 1 10760 #define XGXSBLK1_TESTRX_LINK_FORCE_SHIFT 6 10761 10762 /* XgxsBlk1 :: testRx :: rxtm_modsel [05:03] */ 10763 #define XGXSBLK1_TESTRX_RXTM_MODSEL_MASK 0x0038 10764 #define XGXSBLK1_TESTRX_RXTM_MODSEL_ALIGN 0 10765 #define XGXSBLK1_TESTRX_RXTM_MODSEL_BITS 3 10766 #define XGXSBLK1_TESTRX_RXTM_MODSEL_SHIFT 3 10767 10768 /* XgxsBlk1 :: testRx :: rxtm_tstsel [02:00] */ 10769 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_MASK 0x0007 10770 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_ALIGN 0 10771 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_BITS 3 10772 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_SHIFT 0 10773 10774 10775 /**************************************************************************** 10776 * XgxsBlk1 :: testTx 10777 */ 10778 /* XgxsBlk1 :: testTx :: reserved0 [15:08] */ 10779 #define XGXSBLK1_TESTTX_RESERVED0_MASK 0xff00 10780 #define XGXSBLK1_TESTTX_RESERVED0_ALIGN 0 10781 #define XGXSBLK1_TESTTX_RESERVED0_BITS 8 10782 #define XGXSBLK1_TESTTX_RESERVED0_SHIFT 8 10783 10784 /* XgxsBlk1 :: testTx :: rx_ck4x1muxsel [07:06] */ 10785 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_MASK 0x00c0 10786 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_ALIGN 0 10787 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_BITS 2 10788 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_SHIFT 6 10789 10790 /* XgxsBlk1 :: testTx :: txtm_modsel [05:03] */ 10791 #define XGXSBLK1_TESTTX_TXTM_MODSEL_MASK 0x0038 10792 #define XGXSBLK1_TESTTX_TXTM_MODSEL_ALIGN 0 10793 #define XGXSBLK1_TESTTX_TXTM_MODSEL_BITS 3 10794 #define XGXSBLK1_TESTTX_TXTM_MODSEL_SHIFT 3 10795 10796 /* XgxsBlk1 :: testTx :: txtm_tstsel [02:00] */ 10797 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_MASK 0x0007 10798 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_ALIGN 0 10799 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_BITS 3 10800 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_SHIFT 0 10801 10802 10803 /**************************************************************************** 10804 * XgxsBlk1 :: testXg 10805 */ 10806 /* XgxsBlk1 :: testXg :: evnt_cntr_sel [15:15] */ 10807 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_MASK 0x8000 10808 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_ALIGN 0 10809 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_BITS 1 10810 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_SHIFT 15 10811 10812 /* XgxsBlk1 :: testXg :: txdt_sel [14:14] */ 10813 #define XGXSBLK1_TESTXG_TXDT_SEL_MASK 0x4000 10814 #define XGXSBLK1_TESTXG_TXDT_SEL_ALIGN 0 10815 #define XGXSBLK1_TESTXG_TXDT_SEL_BITS 1 10816 #define XGXSBLK1_TESTXG_TXDT_SEL_SHIFT 14 10817 10818 /* XgxsBlk1 :: testXg :: slice_sel [13:12] */ 10819 #define XGXSBLK1_TESTXG_SLICE_SEL_MASK 0x3000 10820 #define XGXSBLK1_TESTXG_SLICE_SEL_ALIGN 0 10821 #define XGXSBLK1_TESTXG_SLICE_SEL_BITS 2 10822 #define XGXSBLK1_TESTXG_SLICE_SEL_SHIFT 12 10823 10824 /* XgxsBlk1 :: testXg :: reserved0 [11:08] */ 10825 #define XGXSBLK1_TESTXG_RESERVED0_MASK 0x0f00 10826 #define XGXSBLK1_TESTXG_RESERVED0_ALIGN 0 10827 #define XGXSBLK1_TESTXG_RESERVED0_BITS 4 10828 #define XGXSBLK1_TESTXG_RESERVED0_SHIFT 8 10829 10830 /* XgxsBlk1 :: testXg :: test_reg_sel [07:07] */ 10831 #define XGXSBLK1_TESTXG_TEST_REG_SEL_MASK 0x0080 10832 #define XGXSBLK1_TESTXG_TEST_REG_SEL_ALIGN 0 10833 #define XGXSBLK1_TESTXG_TEST_REG_SEL_BITS 1 10834 #define XGXSBLK1_TESTXG_TEST_REG_SEL_SHIFT 7 10835 10836 /* XgxsBlk1 :: testXg :: xg_txtstsel [06:04] */ 10837 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_MASK 0x0070 10838 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_ALIGN 0 10839 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_BITS 3 10840 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_SHIFT 4 10841 10842 /* XgxsBlk1 :: testXg :: xg_rxtstsel [03:00] */ 10843 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_MASK 0x000f 10844 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_ALIGN 0 10845 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_BITS 4 10846 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_SHIFT 0 10847 10848 10849 /**************************************************************************** 10850 * XgxsBlk1 :: laneCtrl0 10851 */ 10852 /* XgxsBlk1 :: laneCtrl0 :: ed66en [15:12] */ 10853 #define XGXSBLK1_LANECTRL0_ED66EN_MASK 0xf000 10854 #define XGXSBLK1_LANECTRL0_ED66EN_ALIGN 0 10855 #define XGXSBLK1_LANECTRL0_ED66EN_BITS 4 10856 #define XGXSBLK1_LANECTRL0_ED66EN_SHIFT 12 10857 10858 /* XgxsBlk1 :: laneCtrl0 :: reserved0 [11:08] */ 10859 #define XGXSBLK1_LANECTRL0_RESERVED0_MASK 0x0f00 10860 #define XGXSBLK1_LANECTRL0_RESERVED0_ALIGN 0 10861 #define XGXSBLK1_LANECTRL0_RESERVED0_BITS 4 10862 #define XGXSBLK1_LANECTRL0_RESERVED0_SHIFT 8 10863 10864 /* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_rx [07:04] */ 10865 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_MASK 0x00f0 10866 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_ALIGN 0 10867 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_BITS 4 10868 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_SHIFT 4 10869 10870 /* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_tx [03:00] */ 10871 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_MASK 0x000f 10872 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_ALIGN 0 10873 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_BITS 4 10874 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_SHIFT 0 10875 10876 10877 /**************************************************************************** 10878 * XgxsBlk1 :: laneCtrl1 10879 */ 10880 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln3 [15:14] */ 10881 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_MASK 0xc000 10882 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_ALIGN 0 10883 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_BITS 2 10884 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SHIFT 14 10885 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SWSDR_div2 0 10886 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SWSDR_div1 1 10887 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_DWSDR_div2 2 10888 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_DWSDR_div1 3 10889 10890 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln2 [13:12] */ 10891 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_MASK 0x3000 10892 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_ALIGN 0 10893 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_BITS 2 10894 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SHIFT 12 10895 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SWSDR_div2 0 10896 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SWSDR_div1 1 10897 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_DWSDR_div2 2 10898 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_DWSDR_div1 3 10899 10900 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln1 [11:10] */ 10901 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_MASK 0x0c00 10902 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_ALIGN 0 10903 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_BITS 2 10904 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SHIFT 10 10905 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SWSDR_div2 0 10906 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SWSDR_div1 1 10907 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_DWSDR_div2 2 10908 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_DWSDR_div1 3 10909 10910 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln0 [09:08] */ 10911 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_MASK 0x0300 10912 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_ALIGN 0 10913 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_BITS 2 10914 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SHIFT 8 10915 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SWSDR_div2 0 10916 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SWSDR_div1 1 10917 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_DWSDR_div2 2 10918 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_DWSDR_div1 3 10919 10920 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln3 [07:06] */ 10921 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_MASK 0x00c0 10922 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_ALIGN 0 10923 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_BITS 2 10924 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SHIFT 6 10925 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SWSDR_div2 0 10926 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SWSDR_div1 1 10927 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_DWSDR_div2 2 10928 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_DWSDR_div1 3 10929 10930 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln2 [05:04] */ 10931 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_MASK 0x0030 10932 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_ALIGN 0 10933 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_BITS 2 10934 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SHIFT 4 10935 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SWSDR_div2 0 10936 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SWSDR_div1 1 10937 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_DWSDR_div2 2 10938 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_DWSDR_div1 3 10939 10940 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln1 [03:02] */ 10941 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_MASK 0x000c 10942 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_ALIGN 0 10943 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_BITS 2 10944 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SHIFT 2 10945 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SWSDR_div2 0 10946 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SWSDR_div1 1 10947 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_DWSDR_div2 2 10948 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_DWSDR_div1 3 10949 10950 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln0 [01:00] */ 10951 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_MASK 0x0003 10952 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_ALIGN 0 10953 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_BITS 2 10954 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SHIFT 0 10955 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SWSDR_div2 0 10956 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SWSDR_div1 1 10957 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_DWSDR_div2 2 10958 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_DWSDR_div1 3 10959 10960 10961 /**************************************************************************** 10962 * XgxsBlk1 :: laneCtrl2 10963 */ 10964 /* XgxsBlk1 :: laneCtrl2 :: cdet_en1g [15:12] */ 10965 #define XGXSBLK1_LANECTRL2_CDET_EN1G_MASK 0xf000 10966 #define XGXSBLK1_LANECTRL2_CDET_EN1G_ALIGN 0 10967 #define XGXSBLK1_LANECTRL2_CDET_EN1G_BITS 4 10968 #define XGXSBLK1_LANECTRL2_CDET_EN1G_SHIFT 12 10969 10970 /* XgxsBlk1 :: laneCtrl2 :: eden1g [11:08] */ 10971 #define XGXSBLK1_LANECTRL2_EDEN1G_MASK 0x0f00 10972 #define XGXSBLK1_LANECTRL2_EDEN1G_ALIGN 0 10973 #define XGXSBLK1_LANECTRL2_EDEN1G_BITS 4 10974 #define XGXSBLK1_LANECTRL2_EDEN1G_SHIFT 8 10975 10976 /* XgxsBlk1 :: laneCtrl2 :: rloop1g [07:04] */ 10977 #define XGXSBLK1_LANECTRL2_RLOOP1G_MASK 0x00f0 10978 #define XGXSBLK1_LANECTRL2_RLOOP1G_ALIGN 0 10979 #define XGXSBLK1_LANECTRL2_RLOOP1G_BITS 4 10980 #define XGXSBLK1_LANECTRL2_RLOOP1G_SHIFT 4 10981 10982 /* XgxsBlk1 :: laneCtrl2 :: gloop1g [03:00] */ 10983 #define XGXSBLK1_LANECTRL2_GLOOP1G_MASK 0x000f 10984 #define XGXSBLK1_LANECTRL2_GLOOP1G_ALIGN 0 10985 #define XGXSBLK1_LANECTRL2_GLOOP1G_BITS 4 10986 #define XGXSBLK1_LANECTRL2_GLOOP1G_SHIFT 0 10987 10988 10989 /**************************************************************************** 10990 * XgxsBlk1 :: laneCtrl3 10991 */ 10992 /* XgxsBlk1 :: laneCtrl3 :: lock_ref [15:12] */ 10993 #define XGXSBLK1_LANECTRL3_LOCK_REF_MASK 0xf000 10994 #define XGXSBLK1_LANECTRL3_LOCK_REF_ALIGN 0 10995 #define XGXSBLK1_LANECTRL3_LOCK_REF_BITS 4 10996 #define XGXSBLK1_LANECTRL3_LOCK_REF_SHIFT 12 10997 10998 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn_force [11:11] */ 10999 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_MASK 0x0800 11000 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_ALIGN 0 11001 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_BITS 1 11002 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_SHIFT 11 11003 11004 /* XgxsBlk1 :: laneCtrl3 :: lock_ref_en [10:10] */ 11005 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_MASK 0x0400 11006 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_ALIGN 0 11007 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_BITS 1 11008 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_SHIFT 10 11009 11010 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn10g_pll_dis [09:09] */ 11011 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_MASK 0x0200 11012 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_ALIGN 0 11013 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_BITS 1 11014 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_SHIFT 9 11015 11016 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn_pll [08:08] */ 11017 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_MASK 0x0100 11018 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_ALIGN 0 11019 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_BITS 1 11020 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_SHIFT 8 11021 11022 /* XgxsBlk1 :: laneCtrl3 :: pwrdn_tx [07:04] */ 11023 #define XGXSBLK1_LANECTRL3_PWRDN_TX_MASK 0x00f0 11024 #define XGXSBLK1_LANECTRL3_PWRDN_TX_ALIGN 0 11025 #define XGXSBLK1_LANECTRL3_PWRDN_TX_BITS 4 11026 #define XGXSBLK1_LANECTRL3_PWRDN_TX_SHIFT 4 11027 11028 /* XgxsBlk1 :: laneCtrl3 :: pwrdn_rx [03:00] */ 11029 #define XGXSBLK1_LANECTRL3_PWRDN_RX_MASK 0x000f 11030 #define XGXSBLK1_LANECTRL3_PWRDN_RX_ALIGN 0 11031 #define XGXSBLK1_LANECTRL3_PWRDN_RX_BITS 4 11032 #define XGXSBLK1_LANECTRL3_PWRDN_RX_SHIFT 0 11033 11034 11035 /**************************************************************************** 11036 * XgxsBlk1 :: lanePrbs 11037 */ 11038 /* XgxsBlk1 :: lanePrbs :: prbs_en3 [15:15] */ 11039 #define XGXSBLK1_LANEPRBS_PRBS_EN3_MASK 0x8000 11040 #define XGXSBLK1_LANEPRBS_PRBS_EN3_ALIGN 0 11041 #define XGXSBLK1_LANEPRBS_PRBS_EN3_BITS 1 11042 #define XGXSBLK1_LANEPRBS_PRBS_EN3_SHIFT 15 11043 11044 /* XgxsBlk1 :: lanePrbs :: prbs_inv3 [14:14] */ 11045 #define XGXSBLK1_LANEPRBS_PRBS_INV3_MASK 0x4000 11046 #define XGXSBLK1_LANEPRBS_PRBS_INV3_ALIGN 0 11047 #define XGXSBLK1_LANEPRBS_PRBS_INV3_BITS 1 11048 #define XGXSBLK1_LANEPRBS_PRBS_INV3_SHIFT 14 11049 11050 /* XgxsBlk1 :: lanePrbs :: prbs_order3 [13:12] */ 11051 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_MASK 0x3000 11052 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_ALIGN 0 11053 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_BITS 2 11054 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_SHIFT 12 11055 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs7 0 11056 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs15 1 11057 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs23 2 11058 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs31 3 11059 11060 /* XgxsBlk1 :: lanePrbs :: prbs_en2 [11:11] */ 11061 #define XGXSBLK1_LANEPRBS_PRBS_EN2_MASK 0x0800 11062 #define XGXSBLK1_LANEPRBS_PRBS_EN2_ALIGN 0 11063 #define XGXSBLK1_LANEPRBS_PRBS_EN2_BITS 1 11064 #define XGXSBLK1_LANEPRBS_PRBS_EN2_SHIFT 11 11065 11066 /* XgxsBlk1 :: lanePrbs :: prbs_inv2 [10:10] */ 11067 #define XGXSBLK1_LANEPRBS_PRBS_INV2_MASK 0x0400 11068 #define XGXSBLK1_LANEPRBS_PRBS_INV2_ALIGN 0 11069 #define XGXSBLK1_LANEPRBS_PRBS_INV2_BITS 1 11070 #define XGXSBLK1_LANEPRBS_PRBS_INV2_SHIFT 10 11071 11072 /* XgxsBlk1 :: lanePrbs :: prbs_order2 [09:08] */ 11073 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_MASK 0x0300 11074 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_ALIGN 0 11075 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_BITS 2 11076 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_SHIFT 8 11077 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs7 0 11078 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs15 1 11079 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs23 2 11080 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs31 3 11081 11082 /* XgxsBlk1 :: lanePrbs :: prbs_en1 [07:07] */ 11083 #define XGXSBLK1_LANEPRBS_PRBS_EN1_MASK 0x0080 11084 #define XGXSBLK1_LANEPRBS_PRBS_EN1_ALIGN 0 11085 #define XGXSBLK1_LANEPRBS_PRBS_EN1_BITS 1 11086 #define XGXSBLK1_LANEPRBS_PRBS_EN1_SHIFT 7 11087 11088 /* XgxsBlk1 :: lanePrbs :: prbs_inv1 [06:06] */ 11089 #define XGXSBLK1_LANEPRBS_PRBS_INV1_MASK 0x0040 11090 #define XGXSBLK1_LANEPRBS_PRBS_INV1_ALIGN 0 11091 #define XGXSBLK1_LANEPRBS_PRBS_INV1_BITS 1 11092 #define XGXSBLK1_LANEPRBS_PRBS_INV1_SHIFT 6 11093 11094 /* XgxsBlk1 :: lanePrbs :: prbs_order1 [05:04] */ 11095 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_MASK 0x0030 11096 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_ALIGN 0 11097 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_BITS 2 11098 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_SHIFT 4 11099 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs7 0 11100 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs15 1 11101 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs23 2 11102 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs31 3 11103 11104 /* XgxsBlk1 :: lanePrbs :: prbs_en0 [03:03] */ 11105 #define XGXSBLK1_LANEPRBS_PRBS_EN0_MASK 0x0008 11106 #define XGXSBLK1_LANEPRBS_PRBS_EN0_ALIGN 0 11107 #define XGXSBLK1_LANEPRBS_PRBS_EN0_BITS 1 11108 #define XGXSBLK1_LANEPRBS_PRBS_EN0_SHIFT 3 11109 11110 /* XgxsBlk1 :: lanePrbs :: prbs_inv0 [02:02] */ 11111 #define XGXSBLK1_LANEPRBS_PRBS_INV0_MASK 0x0004 11112 #define XGXSBLK1_LANEPRBS_PRBS_INV0_ALIGN 0 11113 #define XGXSBLK1_LANEPRBS_PRBS_INV0_BITS 1 11114 #define XGXSBLK1_LANEPRBS_PRBS_INV0_SHIFT 2 11115 11116 /* XgxsBlk1 :: lanePrbs :: prbs_order0 [01:00] */ 11117 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_MASK 0x0003 11118 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_ALIGN 0 11119 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_BITS 2 11120 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_SHIFT 0 11121 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs7 0 11122 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs15 1 11123 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs23 2 11124 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs31 3 11125 11126 11127 /**************************************************************************** 11128 * XgxsBlk1 :: laneTest 11129 */ 11130 /* XgxsBlk1 :: laneTest :: tmux_sel [15:12] */ 11131 #define XGXSBLK1_LANETEST_TMUX_SEL_MASK 0xf000 11132 #define XGXSBLK1_LANETEST_TMUX_SEL_ALIGN 0 11133 #define XGXSBLK1_LANETEST_TMUX_SEL_BITS 4 11134 #define XGXSBLK1_LANETEST_TMUX_SEL_SHIFT 12 11135 #define XGXSBLK1_LANETEST_TMUX_SEL_off 0 11136 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln0 1 11137 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln1 2 11138 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln2 3 11139 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln3 4 11140 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln0 5 11141 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln1 6 11142 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln2 7 11143 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln3 8 11144 #define XGXSBLK1_LANETEST_TMUX_SEL_pll 11 11145 #define XGXSBLK1_LANETEST_TMUX_SEL_mdio 12 11146 #define XGXSBLK1_LANETEST_TMUX_SEL_tMux1G 15 11147 11148 /* XgxsBlk1 :: laneTest :: inBandMdioRxRstEn [11:11] */ 11149 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_MASK 0x0800 11150 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_ALIGN 0 11151 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_BITS 1 11152 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_SHIFT 11 11153 11154 /* XgxsBlk1 :: laneTest :: pwrdn_ext_dis [10:10] */ 11155 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_MASK 0x0400 11156 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_ALIGN 0 11157 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_BITS 1 11158 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_SHIFT 10 11159 11160 /* XgxsBlk1 :: laneTest :: pwrdn_safe_dis [09:09] */ 11161 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_MASK 0x0200 11162 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_ALIGN 0 11163 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_BITS 1 11164 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_SHIFT 9 11165 11166 /* XgxsBlk1 :: laneTest :: pwrdwn_clks_en [08:08] */ 11167 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_MASK 0x0100 11168 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_ALIGN 0 11169 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_BITS 1 11170 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_SHIFT 8 11171 11172 /* XgxsBlk1 :: laneTest :: rxSeqStart_ext_dis [07:07] */ 11173 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_MASK 0x0080 11174 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_ALIGN 0 11175 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_BITS 1 11176 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_SHIFT 7 11177 11178 /* XgxsBlk1 :: laneTest :: pll_lock_rstb_r [06:06] */ 11179 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_MASK 0x0040 11180 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_ALIGN 0 11181 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_BITS 1 11182 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_SHIFT 6 11183 11184 /* XgxsBlk1 :: laneTest :: lfck_bypass [05:05] */ 11185 #define XGXSBLK1_LANETEST_LFCK_BYPASS_MASK 0x0020 11186 #define XGXSBLK1_LANETEST_LFCK_BYPASS_ALIGN 0 11187 #define XGXSBLK1_LANETEST_LFCK_BYPASS_BITS 1 11188 #define XGXSBLK1_LANETEST_LFCK_BYPASS_SHIFT 5 11189 11190 /* XgxsBlk1 :: laneTest :: rx_snoop_en [04:04] */ 11191 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_MASK 0x0010 11192 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_ALIGN 0 11193 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_BITS 1 11194 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_SHIFT 4 11195 11196 /* XgxsBlk1 :: laneTest :: mode_10g_snoop [03:00] */ 11197 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_MASK 0x000f 11198 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_ALIGN 0 11199 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_BITS 4 11200 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_SHIFT 0 11201 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS 0 11202 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXG_nCC 1 11203 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_IndLane_OS8 4 11204 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_IndLane_OS5 5 11205 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PCI 7 11206 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS_nLQ 8 11207 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS_nLQnCC 9 11208 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PBypass 10 11209 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PBypass_nDSK 11 11210 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_ComboCoreMode 12 11211 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_Clocks_off 15 11212 11213 11214 /**************************************************************************** 11215 * XgxsBlk1 :: lssRevnt 11216 */ 11217 /* union - case txActive [15:00] */ 11218 /* XgxsBlk1 :: lssRevnt :: txActive [15:00] */ 11219 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_MASK 0xffff 11220 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_ALIGN 0 11221 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_BITS 16 11222 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_SHIFT 0 11223 11224 11225 /* union - case lssRevent [15:00] */ 11226 /* XgxsBlk1 :: lssRevnt :: lss_Revent [15:00] */ 11227 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_MASK 0xffff 11228 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_ALIGN 0 11229 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_BITS 16 11230 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_SHIFT 0 11231 11232 11233 11234 /**************************************************************************** 11235 * XgxsBlk1 :: dskevnt 11236 */ 11237 /* union - case rxActive [15:00] */ 11238 /* XgxsBlk1 :: dskevnt :: rxActive [15:00] */ 11239 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_MASK 0xffff 11240 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_ALIGN 0 11241 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_BITS 16 11242 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_SHIFT 0 11243 11244 11245 /* union - case deskwevent [15:00] */ 11246 /* XgxsBlk1 :: dskevnt :: deskewEvent [15:00] */ 11247 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_MASK 0xffff 11248 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_ALIGN 0 11249 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_BITS 16 11250 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_SHIFT 0 11251 11252 11253 11254 /**************************************************************************** 11255 * XgxsBlk1 :: Aerrevnt 11256 */ 11257 /* XgxsBlk1 :: Aerrevnt :: Aerrevnt [15:00] */ 11258 #define XGXSBLK1_AERREVNT_AERREVNT_MASK 0xffff 11259 #define XGXSBLK1_AERREVNT_AERREVNT_ALIGN 0 11260 #define XGXSBLK1_AERREVNT_AERREVNT_BITS 16 11261 #define XGXSBLK1_AERREVNT_AERREVNT_SHIFT 0 11262 11263 11264 /**************************************************************************** 11265 * XgxsBlk1 :: ckcmpevnt 11266 */ 11267 /* XgxsBlk1 :: ckcmpevnt :: ckcmpevnt [15:00] */ 11268 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_MASK 0xffff 11269 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_ALIGN 0 11270 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_BITS 16 11271 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_SHIFT 0 11272 11273 11274 /**************************************************************************** 11275 * XgxsBlk1 :: BlockAddress 11276 */ 11277 /* XgxsBlk1 :: BlockAddress :: reserved0 [15:15] */ 11278 #define XGXSBLK1_BLOCKADDRESS_RESERVED0_MASK 0x8000 11279 #define XGXSBLK1_BLOCKADDRESS_RESERVED0_ALIGN 0 11280 #define XGXSBLK1_BLOCKADDRESS_RESERVED0_BITS 1 11281 #define XGXSBLK1_BLOCKADDRESS_RESERVED0_SHIFT 15 11282 11283 /* XgxsBlk1 :: BlockAddress :: BlockAddress [14:04] */ 11284 #define XGXSBLK1_BLOCKADDRESS_BLOCKADDRESS_MASK 0x7ff0 11285 #define XGXSBLK1_BLOCKADDRESS_BLOCKADDRESS_ALIGN 0 11286 #define XGXSBLK1_BLOCKADDRESS_BLOCKADDRESS_BITS 11 11287 #define XGXSBLK1_BLOCKADDRESS_BLOCKADDRESS_SHIFT 4 11288 11289 /* XgxsBlk1 :: BlockAddress :: reserved1 [03:00] */ 11290 #define XGXSBLK1_BLOCKADDRESS_RESERVED1_MASK 0x000f 11291 #define XGXSBLK1_BLOCKADDRESS_RESERVED1_ALIGN 0 11292 #define XGXSBLK1_BLOCKADDRESS_RESERVED1_BITS 4 11293 #define XGXSBLK1_BLOCKADDRESS_RESERVED1_SHIFT 0 11294 11295 11296 /**************************************************************************** 11297 * Warpcore_USER_TxBert 11298 */ 11299 /**************************************************************************** 11300 * TxBert :: txBertCtrl 11301 */ 11302 /* TxBert :: txBertCtrl :: pkt_en [15:15] */ 11303 #define TXBERT_TXBERTCTRL_PKT_EN_MASK 0x8000 11304 #define TXBERT_TXBERTCTRL_PKT_EN_ALIGN 0 11305 #define TXBERT_TXBERTCTRL_PKT_EN_BITS 1 11306 #define TXBERT_TXBERTCTRL_PKT_EN_SHIFT 15 11307 11308 /* TxBert :: txBertCtrl :: seed_ld [14:14] */ 11309 #define TXBERT_TXBERTCTRL_SEED_LD_MASK 0x4000 11310 #define TXBERT_TXBERTCTRL_SEED_LD_ALIGN 0 11311 #define TXBERT_TXBERTCTRL_SEED_LD_BITS 1 11312 #define TXBERT_TXBERTCTRL_SEED_LD_SHIFT 14 11313 11314 /* TxBert :: txBertCtrl :: prbs_order [13:12] */ 11315 #define TXBERT_TXBERTCTRL_PRBS_ORDER_MASK 0x3000 11316 #define TXBERT_TXBERTCTRL_PRBS_ORDER_ALIGN 0 11317 #define TXBERT_TXBERTCTRL_PRBS_ORDER_BITS 2 11318 #define TXBERT_TXBERTCTRL_PRBS_ORDER_SHIFT 12 11319 11320 /* TxBert :: txBertCtrl :: ramp_en [11:11] */ 11321 #define TXBERT_TXBERTCTRL_RAMP_EN_MASK 0x0800 11322 #define TXBERT_TXBERTCTRL_RAMP_EN_ALIGN 0 11323 #define TXBERT_TXBERTCTRL_RAMP_EN_BITS 1 11324 #define TXBERT_TXBERTCTRL_RAMP_EN_SHIFT 11 11325 11326 /* TxBert :: txBertCtrl :: rndm_en [10:10] */ 11327 #define TXBERT_TXBERTCTRL_RNDM_EN_MASK 0x0400 11328 #define TXBERT_TXBERTCTRL_RNDM_EN_ALIGN 0 11329 #define TXBERT_TXBERTCTRL_RNDM_EN_BITS 1 11330 #define TXBERT_TXBERTCTRL_RNDM_EN_SHIFT 10 11331 11332 /* TxBert :: txBertCtrl :: Q_en [09:09] */ 11333 #define TXBERT_TXBERTCTRL_Q_EN_MASK 0x0200 11334 #define TXBERT_TXBERTCTRL_Q_EN_ALIGN 0 11335 #define TXBERT_TXBERTCTRL_Q_EN_BITS 1 11336 #define TXBERT_TXBERTCTRL_Q_EN_SHIFT 9 11337 11338 /* TxBert :: txBertCtrl :: Q_link_en [08:08] */ 11339 #define TXBERT_TXBERTCTRL_Q_LINK_EN_MASK 0x0100 11340 #define TXBERT_TXBERTCTRL_Q_LINK_EN_ALIGN 0 11341 #define TXBERT_TXBERTCTRL_Q_LINK_EN_BITS 1 11342 #define TXBERT_TXBERTCTRL_Q_LINK_EN_SHIFT 8 11343 11344 /* TxBert :: txBertCtrl :: skew_en [07:07] */ 11345 #define TXBERT_TXBERTCTRL_SKEW_EN_MASK 0x0080 11346 #define TXBERT_TXBERTCTRL_SKEW_EN_ALIGN 0 11347 #define TXBERT_TXBERTCTRL_SKEW_EN_BITS 1 11348 #define TXBERT_TXBERTCTRL_SKEW_EN_SHIFT 7 11349 11350 /* TxBert :: txBertCtrl :: cjpat_en [06:06] */ 11351 #define TXBERT_TXBERTCTRL_CJPAT_EN_MASK 0x0040 11352 #define TXBERT_TXBERTCTRL_CJPAT_EN_ALIGN 0 11353 #define TXBERT_TXBERTCTRL_CJPAT_EN_BITS 1 11354 #define TXBERT_TXBERTCTRL_CJPAT_EN_SHIFT 6 11355 11356 /* TxBert :: txBertCtrl :: crpat_en [05:05] */ 11357 #define TXBERT_TXBERTCTRL_CRPAT_EN_MASK 0x0020 11358 #define TXBERT_TXBERTCTRL_CRPAT_EN_ALIGN 0 11359 #define TXBERT_TXBERTCTRL_CRPAT_EN_BITS 1 11360 #define TXBERT_TXBERTCTRL_CRPAT_EN_SHIFT 5 11361 11362 /* TxBert :: txBertCtrl :: cjrmp_en [04:04] */ 11363 #define TXBERT_TXBERTCTRL_CJRMP_EN_MASK 0x0010 11364 #define TXBERT_TXBERTCTRL_CJRMP_EN_ALIGN 0 11365 #define TXBERT_TXBERTCTRL_CJRMP_EN_BITS 1 11366 #define TXBERT_TXBERTCTRL_CJRMP_EN_SHIFT 4 11367 11368 /* TxBert :: txBertCtrl :: txck_out_force [03:03] */ 11369 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_MASK 0x0008 11370 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_ALIGN 0 11371 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_BITS 1 11372 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_SHIFT 3 11373 11374 /* TxBert :: txBertCtrl :: fifo_rst [02:02] */ 11375 #define TXBERT_TXBERTCTRL_FIFO_RST_MASK 0x0004 11376 #define TXBERT_TXBERTCTRL_FIFO_RST_ALIGN 0 11377 #define TXBERT_TXBERTCTRL_FIFO_RST_BITS 1 11378 #define TXBERT_TXBERTCTRL_FIFO_RST_SHIFT 2 11379 11380 /* TxBert :: txBertCtrl :: countRst_dis [01:01] */ 11381 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_MASK 0x0002 11382 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_ALIGN 0 11383 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_BITS 1 11384 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_SHIFT 1 11385 11386 /* TxBert :: txBertCtrl :: count_clr [00:00] */ 11387 #define TXBERT_TXBERTCTRL_COUNT_CLR_MASK 0x0001 11388 #define TXBERT_TXBERTCTRL_COUNT_CLR_ALIGN 0 11389 #define TXBERT_TXBERTCTRL_COUNT_CLR_BITS 1 11390 #define TXBERT_TXBERTCTRL_COUNT_CLR_SHIFT 0 11391 11392 11393 /**************************************************************************** 11394 * TxBert :: txBertSopEop 11395 */ 11396 /* TxBert :: txBertSopEop :: SOP [15:08] */ 11397 #define TXBERT_TXBERTSOPEOP_SOP_MASK 0xff00 11398 #define TXBERT_TXBERTSOPEOP_SOP_ALIGN 0 11399 #define TXBERT_TXBERTSOPEOP_SOP_BITS 8 11400 #define TXBERT_TXBERTSOPEOP_SOP_SHIFT 8 11401 11402 /* TxBert :: txBertSopEop :: EOP [07:00] */ 11403 #define TXBERT_TXBERTSOPEOP_EOP_MASK 0x00ff 11404 #define TXBERT_TXBERTSOPEOP_EOP_ALIGN 0 11405 #define TXBERT_TXBERTSOPEOP_EOP_BITS 8 11406 #define TXBERT_TXBERTSOPEOP_EOP_SHIFT 0 11407 11408 11409 /**************************************************************************** 11410 * TxBert :: txBertSize0 11411 */ 11412 /* TxBert :: txBertSize0 :: ipg_size [15:10] */ 11413 #define TXBERT_TXBERTSIZE0_IPG_SIZE_MASK 0xfc00 11414 #define TXBERT_TXBERTSIZE0_IPG_SIZE_ALIGN 0 11415 #define TXBERT_TXBERTSIZE0_IPG_SIZE_BITS 6 11416 #define TXBERT_TXBERTSIZE0_IPG_SIZE_SHIFT 10 11417 11418 /* TxBert :: txBertSize0 :: pkt_size [09:00] */ 11419 #define TXBERT_TXBERTSIZE0_PKT_SIZE_MASK 0x03ff 11420 #define TXBERT_TXBERTSIZE0_PKT_SIZE_ALIGN 0 11421 #define TXBERT_TXBERTSIZE0_PKT_SIZE_BITS 10 11422 #define TXBERT_TXBERTSIZE0_PKT_SIZE_SHIFT 0 11423 11424 11425 /**************************************************************************** 11426 * TxBert :: txBertSize1 11427 */ 11428 /* TxBert :: txBertSize1 :: awin_size [15:10] */ 11429 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_MASK 0xfc00 11430 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_ALIGN 0 11431 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_BITS 6 11432 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_SHIFT 10 11433 11434 /* TxBert :: txBertSize1 :: PktStpCnt [09:00] */ 11435 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_MASK 0x03ff 11436 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_ALIGN 0 11437 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_BITS 10 11438 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_SHIFT 0 11439 11440 11441 /**************************************************************************** 11442 * TxBert :: txBertSize2 11443 */ 11444 /* TxBert :: txBertSize2 :: skew3 [15:12] */ 11445 #define TXBERT_TXBERTSIZE2_SKEW3_MASK 0xf000 11446 #define TXBERT_TXBERTSIZE2_SKEW3_ALIGN 0 11447 #define TXBERT_TXBERTSIZE2_SKEW3_BITS 4 11448 #define TXBERT_TXBERTSIZE2_SKEW3_SHIFT 12 11449 11450 /* TxBert :: txBertSize2 :: skew2 [11:08] */ 11451 #define TXBERT_TXBERTSIZE2_SKEW2_MASK 0x0f00 11452 #define TXBERT_TXBERTSIZE2_SKEW2_ALIGN 0 11453 #define TXBERT_TXBERTSIZE2_SKEW2_BITS 4 11454 #define TXBERT_TXBERTSIZE2_SKEW2_SHIFT 8 11455 11456 /* TxBert :: txBertSize2 :: skew1 [07:04] */ 11457 #define TXBERT_TXBERTSIZE2_SKEW1_MASK 0x00f0 11458 #define TXBERT_TXBERTSIZE2_SKEW1_ALIGN 0 11459 #define TXBERT_TXBERTSIZE2_SKEW1_BITS 4 11460 #define TXBERT_TXBERTSIZE2_SKEW1_SHIFT 4 11461 11462 /* TxBert :: txBertSize2 :: skew0 [03:00] */ 11463 #define TXBERT_TXBERTSIZE2_SKEW0_MASK 0x000f 11464 #define TXBERT_TXBERTSIZE2_SKEW0_ALIGN 0 11465 #define TXBERT_TXBERTSIZE2_SKEW0_BITS 4 11466 #define TXBERT_TXBERTSIZE2_SKEW0_SHIFT 0 11467 11468 11469 /**************************************************************************** 11470 * TxBert :: txBertIpg0 11471 */ 11472 /* TxBert :: txBertIpg0 :: ipg1 [15:08] */ 11473 #define TXBERT_TXBERTIPG0_IPG1_MASK 0xff00 11474 #define TXBERT_TXBERTIPG0_IPG1_ALIGN 0 11475 #define TXBERT_TXBERTIPG0_IPG1_BITS 8 11476 #define TXBERT_TXBERTIPG0_IPG1_SHIFT 8 11477 11478 /* TxBert :: txBertIpg0 :: ipg0 [07:00] */ 11479 #define TXBERT_TXBERTIPG0_IPG0_MASK 0x00ff 11480 #define TXBERT_TXBERTIPG0_IPG0_ALIGN 0 11481 #define TXBERT_TXBERTIPG0_IPG0_BITS 8 11482 #define TXBERT_TXBERTIPG0_IPG0_SHIFT 0 11483 11484 11485 /**************************************************************************** 11486 * TxBert :: txBertIpg1 11487 */ 11488 /* TxBert :: txBertIpg1 :: ipg3 [15:08] */ 11489 #define TXBERT_TXBERTIPG1_IPG3_MASK 0xff00 11490 #define TXBERT_TXBERTIPG1_IPG3_ALIGN 0 11491 #define TXBERT_TXBERTIPG1_IPG3_BITS 8 11492 #define TXBERT_TXBERTIPG1_IPG3_SHIFT 8 11493 11494 /* TxBert :: txBertIpg1 :: ipg2 [07:00] */ 11495 #define TXBERT_TXBERTIPG1_IPG2_MASK 0x00ff 11496 #define TXBERT_TXBERTIPG1_IPG2_ALIGN 0 11497 #define TXBERT_TXBERTIPG1_IPG2_BITS 8 11498 #define TXBERT_TXBERTIPG1_IPG2_SHIFT 0 11499 11500 11501 /**************************************************************************** 11502 * TxBert :: txBertByteU 11503 */ 11504 /* TxBert :: txBertByteU :: byte_count_high [15:00] */ 11505 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_MASK 0xffff 11506 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN 0 11507 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_BITS 16 11508 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT 0 11509 11510 11511 /**************************************************************************** 11512 * TxBert :: txBertByteL 11513 */ 11514 /* TxBert :: txBertByteL :: byte_count_low [15:00] */ 11515 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_MASK 0xffff 11516 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_ALIGN 0 11517 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_BITS 16 11518 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_SHIFT 0 11519 11520 11521 /**************************************************************************** 11522 * TxBert :: txBertPacketU 11523 */ 11524 /* TxBert :: txBertPacketU :: pkt_count_high [15:00] */ 11525 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_MASK 0xffff 11526 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_ALIGN 0 11527 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_BITS 16 11528 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_SHIFT 0 11529 11530 11531 /**************************************************************************** 11532 * TxBert :: txBertPacketL 11533 */ 11534 /* TxBert :: txBertPacketL :: pkt_count_low [15:00] */ 11535 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_MASK 0xffff 11536 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_ALIGN 0 11537 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_BITS 16 11538 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_SHIFT 0 11539 11540 11541 /**************************************************************************** 11542 * TxBert :: txBertCtrl1 11543 */ 11544 /* TxBert :: txBertCtrl1 :: reserved0 [15:01] */ 11545 #define TXBERT_TXBERTCTRL1_RESERVED0_MASK 0xfffe 11546 #define TXBERT_TXBERTCTRL1_RESERVED0_ALIGN 0 11547 #define TXBERT_TXBERTCTRL1_RESERVED0_BITS 15 11548 #define TXBERT_TXBERTCTRL1_RESERVED0_SHIFT 1 11549 11550 /* TxBert :: txBertCtrl1 :: lpi_en [00:00] */ 11551 #define TXBERT_TXBERTCTRL1_LPI_EN_MASK 0x0001 11552 #define TXBERT_TXBERTCTRL1_LPI_EN_ALIGN 0 11553 #define TXBERT_TXBERTCTRL1_LPI_EN_BITS 1 11554 #define TXBERT_TXBERTCTRL1_LPI_EN_SHIFT 0 11555 11556 11557 /**************************************************************************** 11558 * Warpcore_USER_RxBert 11559 */ 11560 /**************************************************************************** 11561 * RxBert :: rxBertCtrl 11562 */ 11563 /* RxBert :: rxBertCtrl :: pkt_en [15:15] */ 11564 #define RXBERT_RXBERTCTRL_PKT_EN_MASK 0x8000 11565 #define RXBERT_RXBERTCTRL_PKT_EN_ALIGN 0 11566 #define RXBERT_RXBERTCTRL_PKT_EN_BITS 1 11567 #define RXBERT_RXBERTCTRL_PKT_EN_SHIFT 15 11568 11569 /* RxBert :: rxBertCtrl :: seed_ld [14:14] */ 11570 #define RXBERT_RXBERTCTRL_SEED_LD_MASK 0x4000 11571 #define RXBERT_RXBERTCTRL_SEED_LD_ALIGN 0 11572 #define RXBERT_RXBERTCTRL_SEED_LD_BITS 1 11573 #define RXBERT_RXBERTCTRL_SEED_LD_SHIFT 14 11574 11575 /* RxBert :: rxBertCtrl :: prbs_order [13:12] */ 11576 #define RXBERT_RXBERTCTRL_PRBS_ORDER_MASK 0x3000 11577 #define RXBERT_RXBERTCTRL_PRBS_ORDER_ALIGN 0 11578 #define RXBERT_RXBERTCTRL_PRBS_ORDER_BITS 2 11579 #define RXBERT_RXBERTCTRL_PRBS_ORDER_SHIFT 12 11580 11581 /* RxBert :: rxBertCtrl :: ramp_en [11:11] */ 11582 #define RXBERT_RXBERTCTRL_RAMP_EN_MASK 0x0800 11583 #define RXBERT_RXBERTCTRL_RAMP_EN_ALIGN 0 11584 #define RXBERT_RXBERTCTRL_RAMP_EN_BITS 1 11585 #define RXBERT_RXBERTCTRL_RAMP_EN_SHIFT 11 11586 11587 /* RxBert :: rxBertCtrl :: cgbad_tst_en [10:10] */ 11588 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_MASK 0x0400 11589 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_ALIGN 0 11590 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_BITS 1 11591 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_SHIFT 10 11592 11593 /* RxBert :: rxBertCtrl :: crcChk_en [09:09] */ 11594 #define RXBERT_RXBERTCTRL_CRCCHK_EN_MASK 0x0200 11595 #define RXBERT_RXBERTCTRL_CRCCHK_EN_ALIGN 0 11596 #define RXBERT_RXBERTCTRL_CRCCHK_EN_BITS 1 11597 #define RXBERT_RXBERTCTRL_CRCCHK_EN_SHIFT 9 11598 11599 /* RxBert :: rxBertCtrl :: countRst_dis [08:08] */ 11600 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_MASK 0x0100 11601 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_ALIGN 0 11602 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_BITS 1 11603 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_SHIFT 8 11604 11605 /* RxBert :: rxBertCtrl :: rxStatSel [07:07] */ 11606 #define RXBERT_RXBERTCTRL_RXSTATSEL_MASK 0x0080 11607 #define RXBERT_RXBERTCTRL_RXSTATSEL_ALIGN 0 11608 #define RXBERT_RXBERTCTRL_RXSTATSEL_BITS 1 11609 #define RXBERT_RXBERTCTRL_RXSTATSEL_SHIFT 7 11610 11611 /* RxBert :: rxBertCtrl :: source_sel_r [06:06] */ 11612 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_MASK 0x0040 11613 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_ALIGN 0 11614 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_BITS 1 11615 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_SHIFT 6 11616 11617 /* RxBert :: rxBertCtrl :: source_sel [05:04] */ 11618 #define RXBERT_RXBERTCTRL_SOURCE_SEL_MASK 0x0030 11619 #define RXBERT_RXBERTCTRL_SOURCE_SEL_ALIGN 0 11620 #define RXBERT_RXBERTCTRL_SOURCE_SEL_BITS 2 11621 #define RXBERT_RXBERTCTRL_SOURCE_SEL_SHIFT 4 11622 11623 /* RxBert :: rxBertCtrl :: slice_sel [03:02] */ 11624 #define RXBERT_RXBERTCTRL_SLICE_SEL_MASK 0x000c 11625 #define RXBERT_RXBERTCTRL_SLICE_SEL_ALIGN 0 11626 #define RXBERT_RXBERTCTRL_SLICE_SEL_BITS 2 11627 #define RXBERT_RXBERTCTRL_SLICE_SEL_SHIFT 2 11628 11629 /* RxBert :: rxBertCtrl :: err_clr [01:01] */ 11630 #define RXBERT_RXBERTCTRL_ERR_CLR_MASK 0x0002 11631 #define RXBERT_RXBERTCTRL_ERR_CLR_ALIGN 0 11632 #define RXBERT_RXBERTCTRL_ERR_CLR_BITS 1 11633 #define RXBERT_RXBERTCTRL_ERR_CLR_SHIFT 1 11634 11635 /* RxBert :: rxBertCtrl :: count_clr [00:00] */ 11636 #define RXBERT_RXBERTCTRL_COUNT_CLR_MASK 0x0001 11637 #define RXBERT_RXBERTCTRL_COUNT_CLR_ALIGN 0 11638 #define RXBERT_RXBERTCTRL_COUNT_CLR_BITS 1 11639 #define RXBERT_RXBERTCTRL_COUNT_CLR_SHIFT 0 11640 11641 11642 /**************************************************************************** 11643 * RxBert :: rxBertSopEop 11644 */ 11645 /* RxBert :: rxBertSopEop :: SOP [15:08] */ 11646 #define RXBERT_RXBERTSOPEOP_SOP_MASK 0xff00 11647 #define RXBERT_RXBERTSOPEOP_SOP_ALIGN 0 11648 #define RXBERT_RXBERTSOPEOP_SOP_BITS 8 11649 #define RXBERT_RXBERTSOPEOP_SOP_SHIFT 8 11650 11651 /* RxBert :: rxBertSopEop :: EOP [07:00] */ 11652 #define RXBERT_RXBERTSOPEOP_EOP_MASK 0x00ff 11653 #define RXBERT_RXBERTSOPEOP_EOP_ALIGN 0 11654 #define RXBERT_RXBERTSOPEOP_EOP_BITS 8 11655 #define RXBERT_RXBERTSOPEOP_EOP_SHIFT 0 11656 11657 11658 /**************************************************************************** 11659 * RxBert :: rxBertByteU 11660 */ 11661 /* RxBert :: rxBertByteU :: byte_count_high [15:00] */ 11662 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_MASK 0xffff 11663 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN 0 11664 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_BITS 16 11665 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT 0 11666 11667 11668 /**************************************************************************** 11669 * RxBert :: rxBertByteL 11670 */ 11671 /* RxBert :: rxBertByteL :: byte_count_low [15:00] */ 11672 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_MASK 0xffff 11673 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_ALIGN 0 11674 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_BITS 16 11675 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_SHIFT 0 11676 11677 11678 /**************************************************************************** 11679 * RxBert :: rxBertPacketU 11680 */ 11681 /* RxBert :: rxBertPacketU :: pkt_count_high [15:00] */ 11682 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_MASK 0xffff 11683 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_ALIGN 0 11684 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_BITS 16 11685 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_SHIFT 0 11686 11687 11688 /**************************************************************************** 11689 * RxBert :: rxBertPacketL 11690 */ 11691 /* RxBert :: rxBertPacketL :: pkt_count_low [15:00] */ 11692 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_MASK 0xffff 11693 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_ALIGN 0 11694 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_BITS 16 11695 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_SHIFT 0 11696 11697 11698 /**************************************************************************** 11699 * RxBert :: rxBertBitErr 11700 */ 11701 /* RxBert :: rxBertBitErr :: bit_err_count [15:00] */ 11702 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_MASK 0xffff 11703 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_ALIGN 0 11704 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_BITS 16 11705 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_SHIFT 0 11706 11707 11708 /**************************************************************************** 11709 * RxBert :: rxBertByteErr 11710 */ 11711 /* RxBert :: rxBertByteErr :: byte_err_count [15:00] */ 11712 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_MASK 0xffff 11713 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_ALIGN 0 11714 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_BITS 16 11715 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_SHIFT 0 11716 11717 11718 /**************************************************************************** 11719 * RxBert :: rxBertPktErr 11720 */ 11721 /* RxBert :: rxBertPktErr :: pkt_err_count [15:00] */ 11722 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_MASK 0xffff 11723 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_ALIGN 0 11724 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_BITS 16 11725 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_SHIFT 0 11726 11727 11728 /**************************************************************************** 11729 * RxBert :: rxBertStatus 11730 */ 11731 /* union - case rxStatSel [15:00] */ 11732 /* RxBert :: rxBertStatus :: reserved0 [15:08] */ 11733 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_MASK 0xff00 11734 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_ALIGN 0 11735 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_BITS 8 11736 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_SHIFT 8 11737 11738 /* RxBert :: rxBertStatus :: rx_10g_tmux [07:00] */ 11739 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_MASK 0x00ff 11740 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_ALIGN 0 11741 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_BITS 8 11742 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_SHIFT 0 11743 11744 11745 /* union - case crcChk_en [15:00] */ 11746 /* RxBert :: rxBertStatus :: link [15:15] */ 11747 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_MASK 0x8000 11748 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_ALIGN 0 11749 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_BITS 1 11750 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_SHIFT 15 11751 11752 /* RxBert :: rxBertStatus :: prbs_stky [14:14] */ 11753 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_MASK 0x4000 11754 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_ALIGN 0 11755 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_BITS 1 11756 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_SHIFT 14 11757 11758 /* RxBert :: rxBertStatus :: reserved0 [13:00] */ 11759 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_MASK 0x3fff 11760 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_ALIGN 0 11761 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_BITS 14 11762 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_SHIFT 0 11763 11764 11765 /* union - case rxBert [15:00] */ 11766 /* RxBert :: rxBertStatus :: prbs_lock [15:15] */ 11767 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_MASK 0x8000 11768 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_ALIGN 0 11769 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_BITS 1 11770 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_SHIFT 15 11771 11772 /* RxBert :: rxBertStatus :: prbs_stky [14:14] */ 11773 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_MASK 0x4000 11774 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_ALIGN 0 11775 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_BITS 1 11776 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_SHIFT 14 11777 11778 /* RxBert :: rxBertStatus :: prbs_state [13:11] */ 11779 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_MASK 0x3800 11780 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_ALIGN 0 11781 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_BITS 3 11782 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_SHIFT 11 11783 11784 /* RxBert :: rxBertStatus :: reserved0 [10:07] */ 11785 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_MASK 0x0780 11786 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_ALIGN 0 11787 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_BITS 4 11788 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_SHIFT 7 11789 11790 /* RxBert :: rxBertStatus :: bit_err_overflow [06:06] */ 11791 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_MASK 0x0040 11792 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_ALIGN 0 11793 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_BITS 1 11794 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_SHIFT 6 11795 11796 /* RxBert :: rxBertStatus :: reserved1 [05:04] */ 11797 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_MASK 0x0030 11798 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_ALIGN 0 11799 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_BITS 2 11800 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_SHIFT 4 11801 11802 /* RxBert :: rxBertStatus :: onefe_det [03:03] */ 11803 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_MASK 0x0008 11804 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_ALIGN 0 11805 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_BITS 1 11806 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_SHIFT 3 11807 11808 /* RxBert :: rxBertStatus :: xor_comp [02:00] */ 11809 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_MASK 0x0007 11810 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_ALIGN 0 11811 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_BITS 3 11812 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_SHIFT 0 11813 11814 11815 11816 /**************************************************************************** 11817 * Warpcore_USER_PLL 11818 */ 11819 /**************************************************************************** 11820 * PLL :: anaPllStatus 11821 */ 11822 /* PLL :: anaPllStatus :: pllSeqDone [15:15] */ 11823 #define PLL_ANAPLLSTATUS_PLLSEQDONE_MASK 0x8000 11824 #define PLL_ANAPLLSTATUS_PLLSEQDONE_ALIGN 0 11825 #define PLL_ANAPLLSTATUS_PLLSEQDONE_BITS 1 11826 #define PLL_ANAPLLSTATUS_PLLSEQDONE_SHIFT 15 11827 11828 /* PLL :: anaPllStatus :: freqDone [14:14] */ 11829 #define PLL_ANAPLLSTATUS_FREQDONE_MASK 0x4000 11830 #define PLL_ANAPLLSTATUS_FREQDONE_ALIGN 0 11831 #define PLL_ANAPLLSTATUS_FREQDONE_BITS 1 11832 #define PLL_ANAPLLSTATUS_FREQDONE_SHIFT 14 11833 11834 /* PLL :: anaPllStatus :: vcoDone [13:13] */ 11835 #define PLL_ANAPLLSTATUS_VCODONE_MASK 0x2000 11836 #define PLL_ANAPLLSTATUS_VCODONE_ALIGN 0 11837 #define PLL_ANAPLLSTATUS_VCODONE_BITS 1 11838 #define PLL_ANAPLLSTATUS_VCODONE_SHIFT 13 11839 11840 /* PLL :: anaPllStatus :: reserved0 [12:12] */ 11841 #define PLL_ANAPLLSTATUS_RESERVED0_MASK 0x1000 11842 #define PLL_ANAPLLSTATUS_RESERVED0_ALIGN 0 11843 #define PLL_ANAPLLSTATUS_RESERVED0_BITS 1 11844 #define PLL_ANAPLLSTATUS_RESERVED0_SHIFT 12 11845 11846 /* PLL :: anaPllStatus :: pllSeqPass [11:11] */ 11847 #define PLL_ANAPLLSTATUS_PLLSEQPASS_MASK 0x0800 11848 #define PLL_ANAPLLSTATUS_PLLSEQPASS_ALIGN 0 11849 #define PLL_ANAPLLSTATUS_PLLSEQPASS_BITS 1 11850 #define PLL_ANAPLLSTATUS_PLLSEQPASS_SHIFT 11 11851 11852 /* PLL :: anaPllStatus :: freqPass [10:10] */ 11853 #define PLL_ANAPLLSTATUS_FREQPASS_MASK 0x0400 11854 #define PLL_ANAPLLSTATUS_FREQPASS_ALIGN 0 11855 #define PLL_ANAPLLSTATUS_FREQPASS_BITS 1 11856 #define PLL_ANAPLLSTATUS_FREQPASS_SHIFT 10 11857 11858 /* PLL :: anaPllStatus :: vcoPass [09:09] */ 11859 #define PLL_ANAPLLSTATUS_VCOPASS_MASK 0x0200 11860 #define PLL_ANAPLLSTATUS_VCOPASS_ALIGN 0 11861 #define PLL_ANAPLLSTATUS_VCOPASS_BITS 1 11862 #define PLL_ANAPLLSTATUS_VCOPASS_SHIFT 9 11863 11864 /* PLL :: anaPllStatus :: reserved1 [08:08] */ 11865 #define PLL_ANAPLLSTATUS_RESERVED1_MASK 0x0100 11866 #define PLL_ANAPLLSTATUS_RESERVED1_ALIGN 0 11867 #define PLL_ANAPLLSTATUS_RESERVED1_BITS 1 11868 #define PLL_ANAPLLSTATUS_RESERVED1_SHIFT 8 11869 11870 /* PLL :: anaPllStatus :: slowdn [07:07] */ 11871 #define PLL_ANAPLLSTATUS_SLOWDN_MASK 0x0080 11872 #define PLL_ANAPLLSTATUS_SLOWDN_ALIGN 0 11873 #define PLL_ANAPLLSTATUS_SLOWDN_BITS 1 11874 #define PLL_ANAPLLSTATUS_SLOWDN_SHIFT 7 11875 11876 /* PLL :: anaPllStatus :: lostPllLock_SM [06:06] */ 11877 #define PLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_MASK 0x0040 11878 #define PLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_ALIGN 0 11879 #define PLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_BITS 1 11880 #define PLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_SHIFT 6 11881 11882 /* PLL :: anaPllStatus :: reserved2 [05:04] */ 11883 #define PLL_ANAPLLSTATUS_RESERVED2_MASK 0x0030 11884 #define PLL_ANAPLLSTATUS_RESERVED2_ALIGN 0 11885 #define PLL_ANAPLLSTATUS_RESERVED2_BITS 2 11886 #define PLL_ANAPLLSTATUS_RESERVED2_SHIFT 4 11887 11888 /* PLL :: anaPllStatus :: pll_mode_afe [03:00] */ 11889 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_MASK 0x000f 11890 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_ALIGN 0 11891 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_BITS 4 11892 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_SHIFT 0 11893 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div32 0 11894 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div36 1 11895 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div40 2 11896 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div42 3 11897 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div48 4 11898 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div50 5 11899 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div52 6 11900 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div54 7 11901 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div60 8 11902 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div64 9 11903 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div66 10 11904 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div68 11 11905 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div70 12 11906 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div80 13 11907 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div92 14 11908 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div100 15 11909 11910 11911 /**************************************************************************** 11912 * PLL :: anaPllControl 11913 */ 11914 /* PLL :: anaPllControl :: pllRestart [15:15] */ 11915 #define PLL_ANAPLLCONTROL_PLLRESTART_MASK 0x8000 11916 #define PLL_ANAPLLCONTROL_PLLRESTART_ALIGN 0 11917 #define PLL_ANAPLLCONTROL_PLLRESTART_BITS 1 11918 #define PLL_ANAPLLCONTROL_PLLRESTART_SHIFT 15 11919 11920 /* PLL :: anaPllControl :: FreqDetRetry_en [14:14] */ 11921 #define PLL_ANAPLLCONTROL_FREQDETRETRY_EN_MASK 0x4000 11922 #define PLL_ANAPLLCONTROL_FREQDETRETRY_EN_ALIGN 0 11923 #define PLL_ANAPLLCONTROL_FREQDETRETRY_EN_BITS 1 11924 #define PLL_ANAPLLCONTROL_FREQDETRETRY_EN_SHIFT 14 11925 11926 /* PLL :: anaPllControl :: FreqDetRestart_en [13:13] */ 11927 #define PLL_ANAPLLCONTROL_FREQDETRESTART_EN_MASK 0x2000 11928 #define PLL_ANAPLLCONTROL_FREQDETRESTART_EN_ALIGN 0 11929 #define PLL_ANAPLLCONTROL_FREQDETRESTART_EN_BITS 1 11930 #define PLL_ANAPLLCONTROL_FREQDETRESTART_EN_SHIFT 13 11931 11932 /* PLL :: anaPllControl :: FreqMonitor_en [12:12] */ 11933 #define PLL_ANAPLLCONTROL_FREQMONITOR_EN_MASK 0x1000 11934 #define PLL_ANAPLLCONTROL_FREQMONITOR_EN_ALIGN 0 11935 #define PLL_ANAPLLCONTROL_FREQMONITOR_EN_BITS 1 11936 #define PLL_ANAPLLCONTROL_FREQMONITOR_EN_SHIFT 12 11937 11938 /* PLL :: anaPllControl :: VcopRetry_en [11:11] */ 11939 #define PLL_ANAPLLCONTROL_VCOPRETRY_EN_MASK 0x0800 11940 #define PLL_ANAPLLCONTROL_VCOPRETRY_EN_ALIGN 0 11941 #define PLL_ANAPLLCONTROL_VCOPRETRY_EN_BITS 1 11942 #define PLL_ANAPLLCONTROL_VCOPRETRY_EN_SHIFT 11 11943 11944 /* PLL :: anaPllControl :: VcoDone_en [10:10] */ 11945 #define PLL_ANAPLLCONTROL_VCODONE_EN_MASK 0x0400 11946 #define PLL_ANAPLLCONTROL_VCODONE_EN_ALIGN 0 11947 #define PLL_ANAPLLCONTROL_VCODONE_EN_BITS 1 11948 #define PLL_ANAPLLCONTROL_VCODONE_EN_SHIFT 10 11949 11950 /* PLL :: anaPllControl :: LinkRestart_en [09:09] */ 11951 #define PLL_ANAPLLCONTROL_LINKRESTART_EN_MASK 0x0200 11952 #define PLL_ANAPLLCONTROL_LINKRESTART_EN_ALIGN 0 11953 #define PLL_ANAPLLCONTROL_LINKRESTART_EN_BITS 1 11954 #define PLL_ANAPLLCONTROL_LINKRESTART_EN_SHIFT 9 11955 11956 /* PLL :: anaPllControl :: ByteSyncRestart_en [08:08] */ 11957 #define PLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_MASK 0x0100 11958 #define PLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_ALIGN 0 11959 #define PLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_BITS 1 11960 #define PLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_SHIFT 8 11961 11962 /* PLL :: anaPllControl :: PllForceDone_en [07:07] */ 11963 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_EN_MASK 0x0080 11964 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_EN_ALIGN 0 11965 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_EN_BITS 1 11966 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_EN_SHIFT 7 11967 11968 /* PLL :: anaPllControl :: PllForceDone [06:06] */ 11969 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_MASK 0x0040 11970 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_ALIGN 0 11971 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_BITS 1 11972 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_SHIFT 6 11973 11974 /* PLL :: anaPllControl :: PllForcePass [05:05] */ 11975 #define PLL_ANAPLLCONTROL_PLLFORCEPASS_MASK 0x0020 11976 #define PLL_ANAPLLCONTROL_PLLFORCEPASS_ALIGN 0 11977 #define PLL_ANAPLLCONTROL_PLLFORCEPASS_BITS 1 11978 #define PLL_ANAPLLCONTROL_PLLFORCEPASS_SHIFT 5 11979 11980 /* PLL :: anaPllControl :: PllForceVcoDone_en [04:04] */ 11981 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_MASK 0x0010 11982 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_ALIGN 0 11983 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_BITS 1 11984 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_SHIFT 4 11985 11986 /* PLL :: anaPllControl :: PllForceVcoDone [03:03] */ 11987 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_MASK 0x0008 11988 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_ALIGN 0 11989 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_BITS 1 11990 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_SHIFT 3 11991 11992 /* PLL :: anaPllControl :: PllForceVcoPass_en [02:02] */ 11993 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_MASK 0x0004 11994 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_ALIGN 0 11995 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_BITS 1 11996 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_SHIFT 2 11997 11998 /* PLL :: anaPllControl :: PllForceVcoPass [01:01] */ 11999 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_MASK 0x0002 12000 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_ALIGN 0 12001 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_BITS 1 12002 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_SHIFT 1 12003 12004 /* PLL :: anaPllControl :: PllForcePllLock [00:00] */ 12005 #define PLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_MASK 0x0001 12006 #define PLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_ALIGN 0 12007 #define PLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_BITS 1 12008 #define PLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_SHIFT 0 12009 12010 12011 /**************************************************************************** 12012 * PLL :: anaPllTimer1 12013 */ 12014 /* PLL :: anaPllTimer1 :: VcoStepTime [15:08] */ 12015 #define PLL_ANAPLLTIMER1_VCOSTEPTIME_MASK 0xff00 12016 #define PLL_ANAPLLTIMER1_VCOSTEPTIME_ALIGN 0 12017 #define PLL_ANAPLLTIMER1_VCOSTEPTIME_BITS 8 12018 #define PLL_ANAPLLTIMER1_VCOSTEPTIME_SHIFT 8 12019 12020 /* PLL :: anaPllTimer1 :: VcoStartTime [07:00] */ 12021 #define PLL_ANAPLLTIMER1_VCOSTARTTIME_MASK 0x00ff 12022 #define PLL_ANAPLLTIMER1_VCOSTARTTIME_ALIGN 0 12023 #define PLL_ANAPLLTIMER1_VCOSTARTTIME_BITS 8 12024 #define PLL_ANAPLLTIMER1_VCOSTARTTIME_SHIFT 0 12025 12026 12027 /**************************************************************************** 12028 * PLL :: anaPllTimer2 12029 */ 12030 /* PLL :: anaPllTimer2 :: reserved0 [15:15] */ 12031 #define PLL_ANAPLLTIMER2_RESERVED0_MASK 0x8000 12032 #define PLL_ANAPLLTIMER2_RESERVED0_ALIGN 0 12033 #define PLL_ANAPLLTIMER2_RESERVED0_BITS 1 12034 #define PLL_ANAPLLTIMER2_RESERVED0_SHIFT 15 12035 12036 /* PLL :: anaPllTimer2 :: lfckSingleStep_en [14:14] */ 12037 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_MASK 0x4000 12038 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_ALIGN 0 12039 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_BITS 1 12040 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_SHIFT 14 12041 12042 /* PLL :: anaPllTimer2 :: lfckSingleStep [13:13] */ 12043 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_MASK 0x2000 12044 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_ALIGN 0 12045 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_BITS 1 12046 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_SHIFT 13 12047 12048 /* PLL :: anaPllTimer2 :: testMuxSel [12:08] */ 12049 #define PLL_ANAPLLTIMER2_TESTMUXSEL_MASK 0x1f00 12050 #define PLL_ANAPLLTIMER2_TESTMUXSEL_ALIGN 0 12051 #define PLL_ANAPLLTIMER2_TESTMUXSEL_BITS 5 12052 #define PLL_ANAPLLTIMER2_TESTMUXSEL_SHIFT 8 12053 12054 /* PLL :: anaPllTimer2 :: retryTime [07:00] */ 12055 #define PLL_ANAPLLTIMER2_RETRYTIME_MASK 0x00ff 12056 #define PLL_ANAPLLTIMER2_RETRYTIME_ALIGN 0 12057 #define PLL_ANAPLLTIMER2_RETRYTIME_BITS 8 12058 #define PLL_ANAPLLTIMER2_RETRYTIME_SHIFT 0 12059 12060 12061 /**************************************************************************** 12062 * PLL :: anaPllTimer3 12063 */ 12064 /* PLL :: anaPllTimer3 :: reserved0 [15:08] */ 12065 #define PLL_ANAPLLTIMER3_RESERVED0_MASK 0xff00 12066 #define PLL_ANAPLLTIMER3_RESERVED0_ALIGN 0 12067 #define PLL_ANAPLLTIMER3_RESERVED0_BITS 8 12068 #define PLL_ANAPLLTIMER3_RESERVED0_SHIFT 8 12069 12070 /* PLL :: anaPllTimer3 :: freqDetTime [07:00] */ 12071 #define PLL_ANAPLLTIMER3_FREQDETTIME_MASK 0x00ff 12072 #define PLL_ANAPLLTIMER3_FREQDETTIME_ALIGN 0 12073 #define PLL_ANAPLLTIMER3_FREQDETTIME_BITS 8 12074 #define PLL_ANAPLLTIMER3_FREQDETTIME_SHIFT 0 12075 12076 12077 /**************************************************************************** 12078 * PLL :: anaCapControl 12079 */ 12080 /* PLL :: anaCapControl :: vcoSeqCYA [15:15] */ 12081 #define PLL_ANACAPCONTROL_VCOSEQCYA_MASK 0x8000 12082 #define PLL_ANACAPCONTROL_VCOSEQCYA_ALIGN 0 12083 #define PLL_ANACAPCONTROL_VCOSEQCYA_BITS 1 12084 #define PLL_ANACAPCONTROL_VCOSEQCYA_SHIFT 15 12085 12086 /* PLL :: anaCapControl :: vcoRestart [14:14] */ 12087 #define PLL_ANACAPCONTROL_VCORESTART_MASK 0x4000 12088 #define PLL_ANACAPCONTROL_VCORESTART_ALIGN 0 12089 #define PLL_ANACAPCONTROL_VCORESTART_BITS 1 12090 #define PLL_ANACAPCONTROL_VCORESTART_SHIFT 14 12091 12092 /* PLL :: anaCapControl :: vcoSelectM_en [13:13] */ 12093 #define PLL_ANACAPCONTROL_VCOSELECTM_EN_MASK 0x2000 12094 #define PLL_ANACAPCONTROL_VCOSELECTM_EN_ALIGN 0 12095 #define PLL_ANACAPCONTROL_VCOSELECTM_EN_BITS 1 12096 #define PLL_ANACAPCONTROL_VCOSELECTM_EN_SHIFT 13 12097 12098 /* PLL :: anaCapControl :: vcoForceSlowdn_en [12:12] */ 12099 #define PLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_MASK 0x1000 12100 #define PLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_ALIGN 0 12101 #define PLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_BITS 1 12102 #define PLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_SHIFT 12 12103 12104 /* PLL :: anaCapControl :: vcoRstEn [11:11] */ 12105 #define PLL_ANACAPCONTROL_VCORSTEN_MASK 0x0800 12106 #define PLL_ANACAPCONTROL_VCORSTEN_ALIGN 0 12107 #define PLL_ANACAPCONTROL_VCORSTEN_BITS 1 12108 #define PLL_ANACAPCONTROL_VCORSTEN_SHIFT 11 12109 12110 /* PLL :: anaCapControl :: vcoCntMask_en [10:10] */ 12111 #define PLL_ANACAPCONTROL_VCOCNTMASK_EN_MASK 0x0400 12112 #define PLL_ANACAPCONTROL_VCOCNTMASK_EN_ALIGN 0 12113 #define PLL_ANACAPCONTROL_VCOCNTMASK_EN_BITS 1 12114 #define PLL_ANACAPCONTROL_VCOCNTMASK_EN_SHIFT 10 12115 12116 /* PLL :: anaCapControl :: slowdn_xor [09:09] */ 12117 #define PLL_ANACAPCONTROL_SLOWDN_XOR_MASK 0x0200 12118 #define PLL_ANACAPCONTROL_SLOWDN_XOR_ALIGN 0 12119 #define PLL_ANACAPCONTROL_SLOWDN_XOR_BITS 1 12120 #define PLL_ANACAPCONTROL_SLOWDN_XOR_SHIFT 9 12121 12122 /* PLL :: anaCapControl :: vcoForceSlowDown [08:08] */ 12123 #define PLL_ANACAPCONTROL_VCOFORCESLOWDOWN_MASK 0x0100 12124 #define PLL_ANACAPCONTROL_VCOFORCESLOWDOWN_ALIGN 0 12125 #define PLL_ANACAPCONTROL_VCOFORCESLOWDOWN_BITS 1 12126 #define PLL_ANACAPCONTROL_VCOFORCESLOWDOWN_SHIFT 8 12127 12128 /* PLL :: anaCapControl :: vcoSelectM [07:00] */ 12129 #define PLL_ANACAPCONTROL_VCOSELECTM_MASK 0x00ff 12130 #define PLL_ANACAPCONTROL_VCOSELECTM_ALIGN 0 12131 #define PLL_ANACAPCONTROL_VCOSELECTM_BITS 8 12132 #define PLL_ANACAPCONTROL_VCOSELECTM_SHIFT 0 12133 12134 12135 /**************************************************************************** 12136 * PLL :: anaFreqDetCntr 12137 */ 12138 /* PLL :: anaFreqDetCntr :: resolution [15:08] */ 12139 #define PLL_ANAFREQDETCNTR_RESOLUTION_MASK 0xff00 12140 #define PLL_ANAFREQDETCNTR_RESOLUTION_ALIGN 0 12141 #define PLL_ANAFREQDETCNTR_RESOLUTION_BITS 8 12142 #define PLL_ANAFREQDETCNTR_RESOLUTION_SHIFT 8 12143 12144 /* PLL :: anaFreqDetCntr :: window [07:00] */ 12145 #define PLL_ANAFREQDETCNTR_WINDOW_MASK 0x00ff 12146 #define PLL_ANAFREQDETCNTR_WINDOW_ALIGN 0 12147 #define PLL_ANAFREQDETCNTR_WINDOW_BITS 8 12148 #define PLL_ANAFREQDETCNTR_WINDOW_SHIFT 0 12149 12150 12151 /**************************************************************************** 12152 * PLL :: anaPllAStatus1 12153 */ 12154 /* PLL :: anaPllAStatus1 :: kvh [15:14] */ 12155 #define PLL_ANAPLLASTATUS1_KVH_MASK 0xc000 12156 #define PLL_ANAPLLASTATUS1_KVH_ALIGN 0 12157 #define PLL_ANAPLLASTATUS1_KVH_BITS 2 12158 #define PLL_ANAPLLASTATUS1_KVH_SHIFT 14 12159 12160 /* PLL :: anaPllAStatus1 :: pll_range [13:06] */ 12161 #define PLL_ANAPLLASTATUS1_PLL_RANGE_MASK 0x3fc0 12162 #define PLL_ANAPLLASTATUS1_PLL_RANGE_ALIGN 0 12163 #define PLL_ANAPLLASTATUS1_PLL_RANGE_BITS 8 12164 #define PLL_ANAPLLASTATUS1_PLL_RANGE_SHIFT 6 12165 12166 /* PLL :: anaPllAStatus1 :: pll_low [05:05] */ 12167 #define PLL_ANAPLLASTATUS1_PLL_LOW_MASK 0x0020 12168 #define PLL_ANAPLLASTATUS1_PLL_LOW_ALIGN 0 12169 #define PLL_ANAPLLASTATUS1_PLL_LOW_BITS 1 12170 #define PLL_ANAPLLASTATUS1_PLL_LOW_SHIFT 5 12171 12172 /* PLL :: anaPllAStatus1 :: reserved0 [04:04] */ 12173 #define PLL_ANAPLLASTATUS1_RESERVED0_MASK 0x0010 12174 #define PLL_ANAPLLASTATUS1_RESERVED0_ALIGN 0 12175 #define PLL_ANAPLLASTATUS1_RESERVED0_BITS 1 12176 #define PLL_ANAPLLASTATUS1_RESERVED0_SHIFT 4 12177 12178 /* PLL :: anaPllAStatus1 :: pll_Ndiv [03:00] */ 12179 #define PLL_ANAPLLASTATUS1_PLL_NDIV_MASK 0x000f 12180 #define PLL_ANAPLLASTATUS1_PLL_NDIV_ALIGN 0 12181 #define PLL_ANAPLLASTATUS1_PLL_NDIV_BITS 4 12182 #define PLL_ANAPLLASTATUS1_PLL_NDIV_SHIFT 0 12183 12184 12185 /**************************************************************************** 12186 * PLL :: anaPllAControl0 12187 */ 12188 /* PLL :: anaPllAControl0 :: refl_clkgen [15:15] */ 12189 #define PLL_ANAPLLACONTROL0_REFL_CLKGEN_MASK 0x8000 12190 #define PLL_ANAPLLACONTROL0_REFL_CLKGEN_ALIGN 0 12191 #define PLL_ANAPLLACONTROL0_REFL_CLKGEN_BITS 1 12192 #define PLL_ANAPLLACONTROL0_REFL_CLKGEN_SHIFT 15 12193 12194 /* PLL :: anaPllAControl0 :: iclkidrv1 [14:12] */ 12195 #define PLL_ANAPLLACONTROL0_ICLKIDRV1_MASK 0x7000 12196 #define PLL_ANAPLLACONTROL0_ICLKIDRV1_ALIGN 0 12197 #define PLL_ANAPLLACONTROL0_ICLKIDRV1_BITS 3 12198 #define PLL_ANAPLLACONTROL0_ICLKIDRV1_SHIFT 12 12199 12200 /* PLL :: anaPllAControl0 :: iclkodrv1 [11:09] */ 12201 #define PLL_ANAPLLACONTROL0_ICLKODRV1_MASK 0x0e00 12202 #define PLL_ANAPLLACONTROL0_ICLKODRV1_ALIGN 0 12203 #define PLL_ANAPLLACONTROL0_ICLKODRV1_BITS 3 12204 #define PLL_ANAPLLACONTROL0_ICLKODRV1_SHIFT 9 12205 12206 /* PLL :: anaPllAControl0 :: iclkodrv2 [08:06] */ 12207 #define PLL_ANAPLLACONTROL0_ICLKODRV2_MASK 0x01c0 12208 #define PLL_ANAPLLACONTROL0_ICLKODRV2_ALIGN 0 12209 #define PLL_ANAPLLACONTROL0_ICLKODRV2_BITS 3 12210 #define PLL_ANAPLLACONTROL0_ICLKODRV2_SHIFT 6 12211 12212 /* PLL :: anaPllAControl0 :: iclkdiv2 [05:03] */ 12213 #define PLL_ANAPLLACONTROL0_ICLKDIV2_MASK 0x0038 12214 #define PLL_ANAPLLACONTROL0_ICLKDIV2_ALIGN 0 12215 #define PLL_ANAPLLACONTROL0_ICLKDIV2_BITS 3 12216 #define PLL_ANAPLLACONTROL0_ICLKDIV2_SHIFT 3 12217 12218 /* PLL :: anaPllAControl0 :: reserved0 [02:02] */ 12219 #define PLL_ANAPLLACONTROL0_RESERVED0_MASK 0x0004 12220 #define PLL_ANAPLLACONTROL0_RESERVED0_ALIGN 0 12221 #define PLL_ANAPLLACONTROL0_RESERVED0_BITS 1 12222 #define PLL_ANAPLLACONTROL0_RESERVED0_SHIFT 2 12223 12224 /* PLL :: anaPllAControl0 :: vddr_bgb [01:01] */ 12225 #define PLL_ANAPLLACONTROL0_VDDR_BGB_MASK 0x0002 12226 #define PLL_ANAPLLACONTROL0_VDDR_BGB_ALIGN 0 12227 #define PLL_ANAPLLACONTROL0_VDDR_BGB_BITS 1 12228 #define PLL_ANAPLLACONTROL0_VDDR_BGB_SHIFT 1 12229 12230 /* PLL :: anaPllAControl0 :: amp_ctrl [00:00] */ 12231 #define PLL_ANAPLLACONTROL0_AMP_CTRL_MASK 0x0001 12232 #define PLL_ANAPLLACONTROL0_AMP_CTRL_ALIGN 0 12233 #define PLL_ANAPLLACONTROL0_AMP_CTRL_BITS 1 12234 #define PLL_ANAPLLACONTROL0_AMP_CTRL_SHIFT 0 12235 12236 12237 /**************************************************************************** 12238 * PLL :: anaPllAControl1 12239 */ 12240 /* PLL :: anaPllAControl1 :: enable_ftune [15:15] */ 12241 #define PLL_ANAPLLACONTROL1_ENABLE_FTUNE_MASK 0x8000 12242 #define PLL_ANAPLLACONTROL1_ENABLE_FTUNE_ALIGN 0 12243 #define PLL_ANAPLLACONTROL1_ENABLE_FTUNE_BITS 1 12244 #define PLL_ANAPLLACONTROL1_ENABLE_FTUNE_SHIFT 15 12245 12246 /* PLL :: anaPllAControl1 :: pll_reset [14:14] */ 12247 #define PLL_ANAPLLACONTROL1_PLL_RESET_MASK 0x4000 12248 #define PLL_ANAPLLACONTROL1_PLL_RESET_ALIGN 0 12249 #define PLL_ANAPLLACONTROL1_PLL_RESET_BITS 1 12250 #define PLL_ANAPLLACONTROL1_PLL_RESET_SHIFT 14 12251 12252 /* PLL :: anaPllAControl1 :: reserved0 [13:11] */ 12253 #define PLL_ANAPLLACONTROL1_RESERVED0_MASK 0x3800 12254 #define PLL_ANAPLLACONTROL1_RESERVED0_ALIGN 0 12255 #define PLL_ANAPLLACONTROL1_RESERVED0_BITS 3 12256 #define PLL_ANAPLLACONTROL1_RESERVED0_SHIFT 11 12257 12258 /* PLL :: anaPllAControl1 :: iclkibuf4 [10:08] */ 12259 #define PLL_ANAPLLACONTROL1_ICLKIBUF4_MASK 0x0700 12260 #define PLL_ANAPLLACONTROL1_ICLKIBUF4_ALIGN 0 12261 #define PLL_ANAPLLACONTROL1_ICLKIBUF4_BITS 3 12262 #define PLL_ANAPLLACONTROL1_ICLKIBUF4_SHIFT 8 12263 12264 /* PLL :: anaPllAControl1 :: ibias_all [07:05] */ 12265 #define PLL_ANAPLLACONTROL1_IBIAS_ALL_MASK 0x00e0 12266 #define PLL_ANAPLLACONTROL1_IBIAS_ALL_ALIGN 0 12267 #define PLL_ANAPLLACONTROL1_IBIAS_ALL_BITS 3 12268 #define PLL_ANAPLLACONTROL1_IBIAS_ALL_SHIFT 5 12269 12270 /* PLL :: anaPllAControl1 :: refout_en [04:04] */ 12271 #define PLL_ANAPLLACONTROL1_REFOUT_EN_MASK 0x0010 12272 #define PLL_ANAPLLACONTROL1_REFOUT_EN_ALIGN 0 12273 #define PLL_ANAPLLACONTROL1_REFOUT_EN_BITS 1 12274 #define PLL_ANAPLLACONTROL1_REFOUT_EN_SHIFT 4 12275 12276 /* PLL :: anaPllAControl1 :: refin_en [03:03] */ 12277 #define PLL_ANAPLLACONTROL1_REFIN_EN_MASK 0x0008 12278 #define PLL_ANAPLLACONTROL1_REFIN_EN_ALIGN 0 12279 #define PLL_ANAPLLACONTROL1_REFIN_EN_BITS 1 12280 #define PLL_ANAPLLACONTROL1_REFIN_EN_SHIFT 3 12281 12282 /* PLL :: anaPllAControl1 :: reserved1 [02:01] */ 12283 #define PLL_ANAPLLACONTROL1_RESERVED1_MASK 0x0006 12284 #define PLL_ANAPLLACONTROL1_RESERVED1_ALIGN 0 12285 #define PLL_ANAPLLACONTROL1_RESERVED1_BITS 2 12286 #define PLL_ANAPLLACONTROL1_RESERVED1_SHIFT 1 12287 12288 /* PLL :: anaPllAControl1 :: refh_clkgen [00:00] */ 12289 #define PLL_ANAPLLACONTROL1_REFH_CLKGEN_MASK 0x0001 12290 #define PLL_ANAPLLACONTROL1_REFH_CLKGEN_ALIGN 0 12291 #define PLL_ANAPLLACONTROL1_REFH_CLKGEN_BITS 1 12292 #define PLL_ANAPLLACONTROL1_REFH_CLKGEN_SHIFT 0 12293 12294 12295 /**************************************************************************** 12296 * PLL :: anaPllAControl2 12297 */ 12298 /* PLL :: anaPllAControl2 :: ick2 [15:15] */ 12299 #define PLL_ANAPLLACONTROL2_ICK2_MASK 0x8000 12300 #define PLL_ANAPLLACONTROL2_ICK2_ALIGN 0 12301 #define PLL_ANAPLLACONTROL2_ICK2_BITS 1 12302 #define PLL_ANAPLLACONTROL2_ICK2_SHIFT 15 12303 12304 /* PLL :: anaPllAControl2 :: ick0 [14:14] */ 12305 #define PLL_ANAPLLACONTROL2_ICK0_MASK 0x4000 12306 #define PLL_ANAPLLACONTROL2_ICK0_ALIGN 0 12307 #define PLL_ANAPLLACONTROL2_ICK0_BITS 1 12308 #define PLL_ANAPLLACONTROL2_ICK0_SHIFT 14 12309 12310 /* PLL :: anaPllAControl2 :: ick1 [13:13] */ 12311 #define PLL_ANAPLLACONTROL2_ICK1_MASK 0x2000 12312 #define PLL_ANAPLLACONTROL2_ICK1_ALIGN 0 12313 #define PLL_ANAPLLACONTROL2_ICK1_BITS 1 12314 #define PLL_ANAPLLACONTROL2_ICK1_SHIFT 13 12315 12316 /* PLL :: anaPllAControl2 :: icp2 [12:12] */ 12317 #define PLL_ANAPLLACONTROL2_ICP2_MASK 0x1000 12318 #define PLL_ANAPLLACONTROL2_ICP2_ALIGN 0 12319 #define PLL_ANAPLLACONTROL2_ICP2_BITS 1 12320 #define PLL_ANAPLLACONTROL2_ICP2_SHIFT 12 12321 12322 /* PLL :: anaPllAControl2 :: icp0 [11:11] */ 12323 #define PLL_ANAPLLACONTROL2_ICP0_MASK 0x0800 12324 #define PLL_ANAPLLACONTROL2_ICP0_ALIGN 0 12325 #define PLL_ANAPLLACONTROL2_ICP0_BITS 1 12326 #define PLL_ANAPLLACONTROL2_ICP0_SHIFT 11 12327 12328 /* PLL :: anaPllAControl2 :: icp1 [10:10] */ 12329 #define PLL_ANAPLLACONTROL2_ICP1_MASK 0x0400 12330 #define PLL_ANAPLLACONTROL2_ICP1_ALIGN 0 12331 #define PLL_ANAPLLACONTROL2_ICP1_BITS 1 12332 #define PLL_ANAPLLACONTROL2_ICP1_SHIFT 10 12333 12334 /* PLL :: anaPllAControl2 :: ibmax [09:09] */ 12335 #define PLL_ANAPLLACONTROL2_IBMAX_MASK 0x0200 12336 #define PLL_ANAPLLACONTROL2_IBMAX_ALIGN 0 12337 #define PLL_ANAPLLACONTROL2_IBMAX_BITS 1 12338 #define PLL_ANAPLLACONTROL2_IBMAX_SHIFT 9 12339 12340 /* PLL :: anaPllAControl2 :: ibmode [08:08] */ 12341 #define PLL_ANAPLLACONTROL2_IBMODE_MASK 0x0100 12342 #define PLL_ANAPLLACONTROL2_IBMODE_ALIGN 0 12343 #define PLL_ANAPLLACONTROL2_IBMODE_BITS 1 12344 #define PLL_ANAPLLACONTROL2_IBMODE_SHIFT 8 12345 12346 /* PLL :: anaPllAControl2 :: ibmin [07:07] */ 12347 #define PLL_ANAPLLACONTROL2_IBMIN_MASK 0x0080 12348 #define PLL_ANAPLLACONTROL2_IBMIN_ALIGN 0 12349 #define PLL_ANAPLLACONTROL2_IBMIN_BITS 1 12350 #define PLL_ANAPLLACONTROL2_IBMIN_SHIFT 7 12351 12352 /* PLL :: anaPllAControl2 :: refh_pll [06:06] */ 12353 #define PLL_ANAPLLACONTROL2_REFH_PLL_MASK 0x0040 12354 #define PLL_ANAPLLACONTROL2_REFH_PLL_ALIGN 0 12355 #define PLL_ANAPLLACONTROL2_REFH_PLL_BITS 1 12356 #define PLL_ANAPLLACONTROL2_REFH_PLL_SHIFT 6 12357 12358 /* PLL :: anaPllAControl2 :: refl_pll [05:05] */ 12359 #define PLL_ANAPLLACONTROL2_REFL_PLL_MASK 0x0020 12360 #define PLL_ANAPLLACONTROL2_REFL_PLL_ALIGN 0 12361 #define PLL_ANAPLLACONTROL2_REFL_PLL_BITS 1 12362 #define PLL_ANAPLLACONTROL2_REFL_PLL_SHIFT 5 12363 12364 /* PLL :: anaPllAControl2 :: iqp [04:01] */ 12365 #define PLL_ANAPLLACONTROL2_IQP_MASK 0x001e 12366 #define PLL_ANAPLLACONTROL2_IQP_ALIGN 0 12367 #define PLL_ANAPLLACONTROL2_IQP_BITS 4 12368 #define PLL_ANAPLLACONTROL2_IQP_SHIFT 1 12369 #define PLL_ANAPLLACONTROL2_IQP_i50uA 0 12370 #define PLL_ANAPLLACONTROL2_IQP_i100uA 1 12371 #define PLL_ANAPLLACONTROL2_IQP_i150uA 2 12372 #define PLL_ANAPLLACONTROL2_IQP_i200uA 3 12373 #define PLL_ANAPLLACONTROL2_IQP_i250uA 4 12374 #define PLL_ANAPLLACONTROL2_IQP_i300uA 5 12375 #define PLL_ANAPLLACONTROL2_IQP_i350uA 6 12376 #define PLL_ANAPLLACONTROL2_IQP_i400uA 7 12377 #define PLL_ANAPLLACONTROL2_IQP_i450uA 8 12378 #define PLL_ANAPLLACONTROL2_IQP_i500uA 9 12379 #define PLL_ANAPLLACONTROL2_IQP_i550uA 10 12380 #define PLL_ANAPLLACONTROL2_IQP_i600uA 11 12381 #define PLL_ANAPLLACONTROL2_IQP_i650uA 12 12382 #define PLL_ANAPLLACONTROL2_IQP_i700uA 13 12383 #define PLL_ANAPLLACONTROL2_IQP_i750uA 14 12384 #define PLL_ANAPLLACONTROL2_IQP_i800uA 15 12385 12386 /* PLL :: anaPllAControl2 :: en_HRz [00:00] */ 12387 #define PLL_ANAPLLACONTROL2_EN_HRZ_MASK 0x0001 12388 #define PLL_ANAPLLACONTROL2_EN_HRZ_ALIGN 0 12389 #define PLL_ANAPLLACONTROL2_EN_HRZ_BITS 1 12390 #define PLL_ANAPLLACONTROL2_EN_HRZ_SHIFT 0 12391 12392 12393 /**************************************************************************** 12394 * PLL :: anaPllAControl3 12395 */ 12396 /* PLL :: anaPllAControl3 :: test_rx [15:15] */ 12397 #define PLL_ANAPLLACONTROL3_TEST_RX_MASK 0x8000 12398 #define PLL_ANAPLLACONTROL3_TEST_RX_ALIGN 0 12399 #define PLL_ANAPLLACONTROL3_TEST_RX_BITS 1 12400 #define PLL_ANAPLLACONTROL3_TEST_RX_SHIFT 15 12401 12402 /* PLL :: anaPllAControl3 :: test_pll [14:14] */ 12403 #define PLL_ANAPLLACONTROL3_TEST_PLL_MASK 0x4000 12404 #define PLL_ANAPLLACONTROL3_TEST_PLL_ALIGN 0 12405 #define PLL_ANAPLLACONTROL3_TEST_PLL_BITS 1 12406 #define PLL_ANAPLLACONTROL3_TEST_PLL_SHIFT 14 12407 12408 /* PLL :: anaPllAControl3 :: test_vc [13:13] */ 12409 #define PLL_ANAPLLACONTROL3_TEST_VC_MASK 0x2000 12410 #define PLL_ANAPLLACONTROL3_TEST_VC_ALIGN 0 12411 #define PLL_ANAPLLACONTROL3_TEST_VC_BITS 1 12412 #define PLL_ANAPLLACONTROL3_TEST_VC_SHIFT 13 12413 12414 /* PLL :: anaPllAControl3 :: test_vref [12:12] */ 12415 #define PLL_ANAPLLACONTROL3_TEST_VREF_MASK 0x1000 12416 #define PLL_ANAPLLACONTROL3_TEST_VREF_ALIGN 0 12417 #define PLL_ANAPLLACONTROL3_TEST_VREF_BITS 1 12418 #define PLL_ANAPLLACONTROL3_TEST_VREF_SHIFT 12 12419 12420 /* PLL :: anaPllAControl3 :: iop2 [11:11] */ 12421 #define PLL_ANAPLLACONTROL3_IOP2_MASK 0x0800 12422 #define PLL_ANAPLLACONTROL3_IOP2_ALIGN 0 12423 #define PLL_ANAPLLACONTROL3_IOP2_BITS 1 12424 #define PLL_ANAPLLACONTROL3_IOP2_SHIFT 11 12425 12426 /* PLL :: anaPllAControl3 :: iop0 [10:10] */ 12427 #define PLL_ANAPLLACONTROL3_IOP0_MASK 0x0400 12428 #define PLL_ANAPLLACONTROL3_IOP0_ALIGN 0 12429 #define PLL_ANAPLLACONTROL3_IOP0_BITS 1 12430 #define PLL_ANAPLLACONTROL3_IOP0_SHIFT 10 12431 12432 /* PLL :: anaPllAControl3 :: iop1 [09:09] */ 12433 #define PLL_ANAPLLACONTROL3_IOP1_MASK 0x0200 12434 #define PLL_ANAPLLACONTROL3_IOP1_ALIGN 0 12435 #define PLL_ANAPLLACONTROL3_IOP1_BITS 1 12436 #define PLL_ANAPLLACONTROL3_IOP1_SHIFT 9 12437 12438 /* PLL :: anaPllAControl3 :: icomp2 [08:08] */ 12439 #define PLL_ANAPLLACONTROL3_ICOMP2_MASK 0x0100 12440 #define PLL_ANAPLLACONTROL3_ICOMP2_ALIGN 0 12441 #define PLL_ANAPLLACONTROL3_ICOMP2_BITS 1 12442 #define PLL_ANAPLLACONTROL3_ICOMP2_SHIFT 8 12443 12444 /* PLL :: anaPllAControl3 :: icomp0 [07:07] */ 12445 #define PLL_ANAPLLACONTROL3_ICOMP0_MASK 0x0080 12446 #define PLL_ANAPLLACONTROL3_ICOMP0_ALIGN 0 12447 #define PLL_ANAPLLACONTROL3_ICOMP0_BITS 1 12448 #define PLL_ANAPLLACONTROL3_ICOMP0_SHIFT 7 12449 12450 /* PLL :: anaPllAControl3 :: icomp1 [06:06] */ 12451 #define PLL_ANAPLLACONTROL3_ICOMP1_MASK 0x0040 12452 #define PLL_ANAPLLACONTROL3_ICOMP1_ALIGN 0 12453 #define PLL_ANAPLLACONTROL3_ICOMP1_BITS 1 12454 #define PLL_ANAPLLACONTROL3_ICOMP1_SHIFT 6 12455 12456 /* PLL :: anaPllAControl3 :: icml2 [05:05] */ 12457 #define PLL_ANAPLLACONTROL3_ICML2_MASK 0x0020 12458 #define PLL_ANAPLLACONTROL3_ICML2_ALIGN 0 12459 #define PLL_ANAPLLACONTROL3_ICML2_BITS 1 12460 #define PLL_ANAPLLACONTROL3_ICML2_SHIFT 5 12461 12462 /* PLL :: anaPllAControl3 :: icml0 [04:04] */ 12463 #define PLL_ANAPLLACONTROL3_ICML0_MASK 0x0010 12464 #define PLL_ANAPLLACONTROL3_ICML0_ALIGN 0 12465 #define PLL_ANAPLLACONTROL3_ICML0_BITS 1 12466 #define PLL_ANAPLLACONTROL3_ICML0_SHIFT 4 12467 12468 /* PLL :: anaPllAControl3 :: icml1 [03:03] */ 12469 #define PLL_ANAPLLACONTROL3_ICML1_MASK 0x0008 12470 #define PLL_ANAPLLACONTROL3_ICML1_ALIGN 0 12471 #define PLL_ANAPLLACONTROL3_ICML1_BITS 1 12472 #define PLL_ANAPLLACONTROL3_ICML1_SHIFT 3 12473 12474 /* PLL :: anaPllAControl3 :: i10Gbuf2 [02:02] */ 12475 #define PLL_ANAPLLACONTROL3_I10GBUF2_MASK 0x0004 12476 #define PLL_ANAPLLACONTROL3_I10GBUF2_ALIGN 0 12477 #define PLL_ANAPLLACONTROL3_I10GBUF2_BITS 1 12478 #define PLL_ANAPLLACONTROL3_I10GBUF2_SHIFT 2 12479 12480 /* PLL :: anaPllAControl3 :: i10Gbuf0 [01:01] */ 12481 #define PLL_ANAPLLACONTROL3_I10GBUF0_MASK 0x0002 12482 #define PLL_ANAPLLACONTROL3_I10GBUF0_ALIGN 0 12483 #define PLL_ANAPLLACONTROL3_I10GBUF0_BITS 1 12484 #define PLL_ANAPLLACONTROL3_I10GBUF0_SHIFT 1 12485 12486 /* PLL :: anaPllAControl3 :: i10Gbuf1 [00:00] */ 12487 #define PLL_ANAPLLACONTROL3_I10GBUF1_MASK 0x0001 12488 #define PLL_ANAPLLACONTROL3_I10GBUF1_ALIGN 0 12489 #define PLL_ANAPLLACONTROL3_I10GBUF1_BITS 1 12490 #define PLL_ANAPLLACONTROL3_I10GBUF1_SHIFT 0 12491 12492 12493 /**************************************************************************** 12494 * PLL :: anaPllAControl4 12495 */ 12496 /* PLL :: anaPllAControl4 :: en40lp [15:15] */ 12497 #define PLL_ANAPLLACONTROL4_EN40LP_MASK 0x8000 12498 #define PLL_ANAPLLACONTROL4_EN40LP_ALIGN 0 12499 #define PLL_ANAPLLACONTROL4_EN40LP_BITS 1 12500 #define PLL_ANAPLLACONTROL4_EN40LP_SHIFT 15 12501 12502 /* PLL :: anaPllAControl4 :: VCO_Imax [14:14] */ 12503 #define PLL_ANAPLLACONTROL4_VCO_IMAX_MASK 0x4000 12504 #define PLL_ANAPLLACONTROL4_VCO_IMAX_ALIGN 0 12505 #define PLL_ANAPLLACONTROL4_VCO_IMAX_BITS 1 12506 #define PLL_ANAPLLACONTROL4_VCO_IMAX_SHIFT 14 12507 12508 /* PLL :: anaPllAControl4 :: kvh_force [13:12] */ 12509 #define PLL_ANAPLLACONTROL4_KVH_FORCE_MASK 0x3000 12510 #define PLL_ANAPLLACONTROL4_KVH_FORCE_ALIGN 0 12511 #define PLL_ANAPLLACONTROL4_KVH_FORCE_BITS 2 12512 #define PLL_ANAPLLACONTROL4_KVH_FORCE_SHIFT 12 12513 12514 /* PLL :: anaPllAControl4 :: vddr_bgb [11:11] */ 12515 #define PLL_ANAPLLACONTROL4_VDDR_BGB_MASK 0x0800 12516 #define PLL_ANAPLLACONTROL4_VDDR_BGB_ALIGN 0 12517 #define PLL_ANAPLLACONTROL4_VDDR_BGB_BITS 1 12518 #define PLL_ANAPLLACONTROL4_VDDR_BGB_SHIFT 11 12519 12520 /* PLL :: anaPllAControl4 :: comp_vth [10:10] */ 12521 #define PLL_ANAPLLACONTROL4_COMP_VTH_MASK 0x0400 12522 #define PLL_ANAPLLACONTROL4_COMP_VTH_ALIGN 0 12523 #define PLL_ANAPLLACONTROL4_COMP_VTH_BITS 1 12524 #define PLL_ANAPLLACONTROL4_COMP_VTH_SHIFT 10 12525 12526 /* PLL :: anaPllAControl4 :: pll2rx_clkbw [09:08] */ 12527 #define PLL_ANAPLLACONTROL4_PLL2RX_CLKBW_MASK 0x0300 12528 #define PLL_ANAPLLACONTROL4_PLL2RX_CLKBW_ALIGN 0 12529 #define PLL_ANAPLLACONTROL4_PLL2RX_CLKBW_BITS 2 12530 #define PLL_ANAPLLACONTROL4_PLL2RX_CLKBW_SHIFT 8 12531 12532 /* PLL :: anaPllAControl4 :: ctatadj [07:04] */ 12533 #define PLL_ANAPLLACONTROL4_CTATADJ_MASK 0x00f0 12534 #define PLL_ANAPLLACONTROL4_CTATADJ_ALIGN 0 12535 #define PLL_ANAPLLACONTROL4_CTATADJ_BITS 4 12536 #define PLL_ANAPLLACONTROL4_CTATADJ_SHIFT 4 12537 12538 /* PLL :: anaPllAControl4 :: ptatadj [03:00] */ 12539 #define PLL_ANAPLLACONTROL4_PTATADJ_MASK 0x000f 12540 #define PLL_ANAPLLACONTROL4_PTATADJ_ALIGN 0 12541 #define PLL_ANAPLLACONTROL4_PTATADJ_BITS 4 12542 #define PLL_ANAPLLACONTROL4_PTATADJ_SHIFT 0 12543 12544 12545 /**************************************************************************** 12546 * Warpcore_USER_Tx0 12547 */ 12548 /**************************************************************************** 12549 * Tx0 :: anaTxAStatus0 12550 */ 12551 /* union - case txStatusSelect_equals_0 [15:00] */ 12552 /* Tx0 :: anaTxAStatus0 :: reserved0 [15:11] */ 12553 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_MASK 0xf800 12554 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_ALIGN 0 12555 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_BITS 5 12556 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_SHIFT 11 12557 12558 /* Tx0 :: anaTxAStatus0 :: oscdr_mode_indch_tx [10:07] */ 12559 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_MASK 0x0780 12560 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_ALIGN 0 12561 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_BITS 4 12562 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_SHIFT 7 12563 12564 /* Tx0 :: anaTxAStatus0 :: txdisable_ln [06:06] */ 12565 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_MASK 0x0040 12566 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_ALIGN 0 12567 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_BITS 1 12568 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_SHIFT 6 12569 12570 /* Tx0 :: anaTxAStatus0 :: txferr_stky [05:05] */ 12571 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_MASK 0x0020 12572 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_ALIGN 0 12573 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_BITS 1 12574 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_SHIFT 5 12575 12576 /* Tx0 :: anaTxAStatus0 :: tbi_mode [04:04] */ 12577 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_MASK 0x0010 12578 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_ALIGN 0 12579 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_BITS 1 12580 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_SHIFT 4 12581 12582 /* Tx0 :: anaTxAStatus0 :: tx_reset [03:03] */ 12583 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_MASK 0x0008 12584 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_ALIGN 0 12585 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_BITS 1 12586 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_SHIFT 3 12587 12588 /* Tx0 :: anaTxAStatus0 :: tx_pwrdn [02:02] */ 12589 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_MASK 0x0004 12590 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_ALIGN 0 12591 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_BITS 1 12592 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_SHIFT 2 12593 12594 /* Tx0 :: anaTxAStatus0 :: rltxferr_stky [01:01] */ 12595 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_MASK 0x0002 12596 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_ALIGN 0 12597 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_BITS 1 12598 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_SHIFT 1 12599 12600 /* Tx0 :: anaTxAStatus0 :: txpll_lock [00:00] */ 12601 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_MASK 0x0001 12602 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_ALIGN 0 12603 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_BITS 1 12604 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_SHIFT 0 12605 12606 12607 /* union - case txStatusSelect_equals_1 [15:00] */ 12608 /* Tx0 :: anaTxAStatus0 :: tx_sel_halfrate [15:15] */ 12609 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_MASK 0x8000 12610 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_ALIGN 0 12611 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_BITS 1 12612 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_SHIFT 15 12613 12614 /* Tx0 :: anaTxAStatus0 :: tx_fir_tap_post [14:10] */ 12615 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_MASK 0x7c00 12616 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_ALIGN 0 12617 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_BITS 5 12618 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_SHIFT 10 12619 12620 /* Tx0 :: anaTxAStatus0 :: tx_fir_tap_main [09:04] */ 12621 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_MASK 0x03f0 12622 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_ALIGN 0 12623 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_BITS 6 12624 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_SHIFT 4 12625 12626 /* Tx0 :: anaTxAStatus0 :: tx_fir_tap_pre [03:00] */ 12627 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_MASK 0x000f 12628 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_ALIGN 0 12629 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_BITS 4 12630 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_SHIFT 0 12631 12632 12633 12634 /**************************************************************************** 12635 * Tx0 :: anaTxAControl0 12636 */ 12637 /* Tx0 :: anaTxAControl0 :: reserved0 [15:15] */ 12638 #define TX0_ANATXACONTROL0_RESERVED0_MASK 0x8000 12639 #define TX0_ANATXACONTROL0_RESERVED0_ALIGN 0 12640 #define TX0_ANATXACONTROL0_RESERVED0_BITS 1 12641 #define TX0_ANATXACONTROL0_RESERVED0_SHIFT 15 12642 12643 /* Tx0 :: anaTxAControl0 :: force_txclk [14:14] */ 12644 #define TX0_ANATXACONTROL0_FORCE_TXCLK_MASK 0x4000 12645 #define TX0_ANATXACONTROL0_FORCE_TXCLK_ALIGN 0 12646 #define TX0_ANATXACONTROL0_FORCE_TXCLK_BITS 1 12647 #define TX0_ANATXACONTROL0_FORCE_TXCLK_SHIFT 14 12648 12649 /* Tx0 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */ 12650 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_MASK 0x2000 12651 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN 0 12652 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_BITS 1 12653 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT 13 12654 12655 /* Tx0 :: anaTxAControl0 :: force_ext_frst_SM [12:12] */ 12656 #define TX0_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK 0x1000 12657 #define TX0_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN 0 12658 #define TX0_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS 1 12659 #define TX0_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT 12 12660 12661 /* Tx0 :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */ 12662 #define TX0_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK 0x0800 12663 #define TX0_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN 0 12664 #define TX0_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS 1 12665 #define TX0_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT 11 12666 12667 /* Tx0 :: anaTxAControl0 :: txck_dme_en_SM [10:10] */ 12668 #define TX0_ANATXACONTROL0_TXCK_DME_EN_SM_MASK 0x0400 12669 #define TX0_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN 0 12670 #define TX0_ANATXACONTROL0_TXCK_DME_EN_SM_BITS 1 12671 #define TX0_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT 10 12672 12673 /* Tx0 :: anaTxAControl0 :: gloopOutDis [09:09] */ 12674 #define TX0_ANATXACONTROL0_GLOOPOUTDIS_MASK 0x0200 12675 #define TX0_ANATXACONTROL0_GLOOPOUTDIS_ALIGN 0 12676 #define TX0_ANATXACONTROL0_GLOOPOUTDIS_BITS 1 12677 #define TX0_ANATXACONTROL0_GLOOPOUTDIS_SHIFT 9 12678 12679 /* Tx0 :: anaTxAControl0 :: prbs_en [08:08] */ 12680 #define TX0_ANATXACONTROL0_PRBS_EN_MASK 0x0100 12681 #define TX0_ANATXACONTROL0_PRBS_EN_ALIGN 0 12682 #define TX0_ANATXACONTROL0_PRBS_EN_BITS 1 12683 #define TX0_ANATXACONTROL0_PRBS_EN_SHIFT 8 12684 12685 /* Tx0 :: anaTxAControl0 :: pckt_en [07:07] */ 12686 #define TX0_ANATXACONTROL0_PCKT_EN_MASK 0x0080 12687 #define TX0_ANATXACONTROL0_PCKT_EN_ALIGN 0 12688 #define TX0_ANATXACONTROL0_PCKT_EN_BITS 1 12689 #define TX0_ANATXACONTROL0_PCKT_EN_SHIFT 7 12690 12691 /* Tx0 :: anaTxAControl0 :: pckt_strt [06:06] */ 12692 #define TX0_ANATXACONTROL0_PCKT_STRT_MASK 0x0040 12693 #define TX0_ANATXACONTROL0_PCKT_STRT_ALIGN 0 12694 #define TX0_ANATXACONTROL0_PCKT_STRT_BITS 1 12695 #define TX0_ANATXACONTROL0_PCKT_STRT_SHIFT 6 12696 12697 /* Tx0 :: anaTxAControl0 :: txpol_flip [05:05] */ 12698 #define TX0_ANATXACONTROL0_TXPOL_FLIP_MASK 0x0020 12699 #define TX0_ANATXACONTROL0_TXPOL_FLIP_ALIGN 0 12700 #define TX0_ANATXACONTROL0_TXPOL_FLIP_BITS 1 12701 #define TX0_ANATXACONTROL0_TXPOL_FLIP_SHIFT 5 12702 12703 /* Tx0 :: anaTxAControl0 :: rtbi_flip [04:04] */ 12704 #define TX0_ANATXACONTROL0_RTBI_FLIP_MASK 0x0010 12705 #define TX0_ANATXACONTROL0_RTBI_FLIP_ALIGN 0 12706 #define TX0_ANATXACONTROL0_RTBI_FLIP_BITS 1 12707 #define TX0_ANATXACONTROL0_RTBI_FLIP_SHIFT 4 12708 12709 /* Tx0 :: anaTxAControl0 :: eden_r [03:03] */ 12710 #define TX0_ANATXACONTROL0_EDEN_R_MASK 0x0008 12711 #define TX0_ANATXACONTROL0_EDEN_R_ALIGN 0 12712 #define TX0_ANATXACONTROL0_EDEN_R_BITS 1 12713 #define TX0_ANATXACONTROL0_EDEN_R_SHIFT 3 12714 12715 /* Tx0 :: anaTxAControl0 :: eden_force_r [02:02] */ 12716 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_MASK 0x0004 12717 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_ALIGN 0 12718 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_BITS 1 12719 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_SHIFT 2 12720 12721 /* Tx0 :: anaTxAControl0 :: txpat_en [01:01] */ 12722 #define TX0_ANATXACONTROL0_TXPAT_EN_MASK 0x0002 12723 #define TX0_ANATXACONTROL0_TXPAT_EN_ALIGN 0 12724 #define TX0_ANATXACONTROL0_TXPAT_EN_BITS 1 12725 #define TX0_ANATXACONTROL0_TXPAT_EN_SHIFT 1 12726 12727 /* Tx0 :: anaTxAControl0 :: tx_mdata_en [00:00] */ 12728 #define TX0_ANATXACONTROL0_TX_MDATA_EN_MASK 0x0001 12729 #define TX0_ANATXACONTROL0_TX_MDATA_EN_ALIGN 0 12730 #define TX0_ANATXACONTROL0_TX_MDATA_EN_BITS 1 12731 #define TX0_ANATXACONTROL0_TX_MDATA_EN_SHIFT 0 12732 12733 12734 /**************************************************************************** 12735 * Tx0 :: anaTxmdata0 12736 */ 12737 /* Tx0 :: anaTxmdata0 :: txTestMuxSel [15:13] */ 12738 #define TX0_ANATXMDATA0_TXTESTMUXSEL_MASK 0xe000 12739 #define TX0_ANATXMDATA0_TXTESTMUXSEL_ALIGN 0 12740 #define TX0_ANATXMDATA0_TXTESTMUXSEL_BITS 3 12741 #define TX0_ANATXMDATA0_TXTESTMUXSEL_SHIFT 13 12742 12743 /* Tx0 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */ 12744 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_MASK 0x1c00 12745 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN 0 12746 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_BITS 3 12747 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT 10 12748 12749 /* Tx0 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */ 12750 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_MASK 0x03ff 12751 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN 0 12752 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_BITS 10 12753 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT 0 12754 12755 12756 /**************************************************************************** 12757 * Tx0 :: anaTxmdata1 12758 */ 12759 /* Tx0 :: anaTxmdata1 :: txStatusSelect [15:14] */ 12760 #define TX0_ANATXMDATA1_TXSTATUSSELECT_MASK 0xc000 12761 #define TX0_ANATXMDATA1_TXSTATUSSELECT_ALIGN 0 12762 #define TX0_ANATXMDATA1_TXSTATUSSELECT_BITS 2 12763 #define TX0_ANATXMDATA1_TXSTATUSSELECT_SHIFT 14 12764 12765 /* Tx0 :: anaTxmdata1 :: reserved0 [13:10] */ 12766 #define TX0_ANATXMDATA1_RESERVED0_MASK 0x3c00 12767 #define TX0_ANATXMDATA1_RESERVED0_ALIGN 0 12768 #define TX0_ANATXMDATA1_RESERVED0_BITS 4 12769 #define TX0_ANATXMDATA1_RESERVED0_SHIFT 10 12770 12771 /* Tx0 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */ 12772 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_MASK 0x03ff 12773 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN 0 12774 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_BITS 10 12775 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT 0 12776 12777 #ifdef BCM_TRIUMPH3_SUPPORT 12778 /* Tx0 :: anaTxmdata1 :: tx_tap_pre [15:14] |[11:10] */ 12779 #define TX0_ANATXMDATA1_TXFIRTAPPRE_MASK 0xcc00 12780 #define TX0_ANATXMDATA1_TXFIRTAPPRE_ALIGN 0 12781 #define TX0_ANATXMDATA1_TXFIRTAPPRE_BITS 4 12782 #define TX0_ANATXMDATA1_TXFIRTAPPRE_HIGH_SHIFT 14 12783 #define TX0_ANATXMDATA1_TXFIRTAPPRE_LOW_SHIFT 10 12784 #endif 12785 /**************************************************************************** 12786 * Tx0 :: anaTxAStatus1 12787 */ 12788 /* Tx0 :: anaTxAStatus1 :: tx_id [15:14] */ 12789 #define TX0_ANATXASTATUS1_TX_ID_MASK 0xc000 12790 #define TX0_ANATXASTATUS1_TX_ID_ALIGN 0 12791 #define TX0_ANATXASTATUS1_TX_ID_BITS 2 12792 #define TX0_ANATXASTATUS1_TX_ID_SHIFT 14 12793 12794 /* Tx0 :: anaTxAStatus1 :: reserved0 [13:08] */ 12795 #define TX0_ANATXASTATUS1_RESERVED0_MASK 0x3f00 12796 #define TX0_ANATXASTATUS1_RESERVED0_ALIGN 0 12797 #define TX0_ANATXASTATUS1_RESERVED0_BITS 6 12798 #define TX0_ANATXASTATUS1_RESERVED0_SHIFT 8 12799 12800 /* Tx0 :: anaTxAStatus1 :: version_id [07:04] */ 12801 #define TX0_ANATXASTATUS1_VERSION_ID_MASK 0x00f0 12802 #define TX0_ANATXASTATUS1_VERSION_ID_ALIGN 0 12803 #define TX0_ANATXASTATUS1_VERSION_ID_BITS 4 12804 #define TX0_ANATXASTATUS1_VERSION_ID_SHIFT 4 12805 12806 /* Tx0 :: anaTxAStatus1 :: reserved1 [03:00] */ 12807 #define TX0_ANATXASTATUS1_RESERVED1_MASK 0x000f 12808 #define TX0_ANATXASTATUS1_RESERVED1_ALIGN 0 12809 #define TX0_ANATXASTATUS1_RESERVED1_BITS 4 12810 #define TX0_ANATXASTATUS1_RESERVED1_SHIFT 0 12811 12812 12813 /**************************************************************************** 12814 * Tx0 :: anaTxAControl1 12815 */ 12816 /* Tx0 :: anaTxAControl1 :: ipredrv [15:13] */ 12817 #define TX0_ANATXACONTROL1_IPREDRV_MASK 0xe000 12818 #define TX0_ANATXACONTROL1_IPREDRV_ALIGN 0 12819 #define TX0_ANATXACONTROL1_IPREDRV_BITS 3 12820 #define TX0_ANATXACONTROL1_IPREDRV_SHIFT 13 12821 12822 /* Tx0 :: anaTxAControl1 :: refl_tx [12:12] */ 12823 #define TX0_ANATXACONTROL1_REFL_TX_MASK 0x1000 12824 #define TX0_ANATXACONTROL1_REFL_TX_ALIGN 0 12825 #define TX0_ANATXACONTROL1_REFL_TX_BITS 1 12826 #define TX0_ANATXACONTROL1_REFL_TX_SHIFT 12 12827 12828 /* Tx0 :: anaTxAControl1 :: refh_tx [11:11] */ 12829 #define TX0_ANATXACONTROL1_REFH_TX_MASK 0x0800 12830 #define TX0_ANATXACONTROL1_REFH_TX_ALIGN 0 12831 #define TX0_ANATXACONTROL1_REFH_TX_BITS 1 12832 #define TX0_ANATXACONTROL1_REFH_TX_SHIFT 11 12833 12834 /* Tx0 :: anaTxAControl1 :: newbias_en [10:10] */ 12835 #define TX0_ANATXACONTROL1_NEWBIAS_EN_MASK 0x0400 12836 #define TX0_ANATXACONTROL1_NEWBIAS_EN_ALIGN 0 12837 #define TX0_ANATXACONTROL1_NEWBIAS_EN_BITS 1 12838 #define TX0_ANATXACONTROL1_NEWBIAS_EN_SHIFT 10 12839 12840 /* Tx0 :: anaTxAControl1 :: drivermode [09:09] */ 12841 #define TX0_ANATXACONTROL1_DRIVERMODE_MASK 0x0200 12842 #define TX0_ANATXACONTROL1_DRIVERMODE_ALIGN 0 12843 #define TX0_ANATXACONTROL1_DRIVERMODE_BITS 1 12844 #define TX0_ANATXACONTROL1_DRIVERMODE_SHIFT 9 12845 12846 /* Tx0 :: anaTxAControl1 :: vddr_bgb [08:08] */ 12847 #define TX0_ANATXACONTROL1_VDDR_BGB_MASK 0x0100 12848 #define TX0_ANATXACONTROL1_VDDR_BGB_ALIGN 0 12849 #define TX0_ANATXACONTROL1_VDDR_BGB_BITS 1 12850 #define TX0_ANATXACONTROL1_VDDR_BGB_SHIFT 8 12851 12852 /* Tx0 :: anaTxAControl1 :: ticksel [07:06] */ 12853 #define TX0_ANATXACONTROL1_TICKSEL_MASK 0x00c0 12854 #define TX0_ANATXACONTROL1_TICKSEL_ALIGN 0 12855 #define TX0_ANATXACONTROL1_TICKSEL_BITS 2 12856 #define TX0_ANATXACONTROL1_TICKSEL_SHIFT 6 12857 12858 /* Tx1 :: (for xenia only anaTxAControl1 :: ticksel [06:06] */ 12859 #define TX0_ANATXACONTROL1_ASYM_MODE_MASK 0x0040 12860 #define TX0_ANATXACONTROL1_ASYM_MODE_ALIGN 0 12861 #define TX0_ANATXACONTROL1_ASYM_MODE_BITS 1 12862 #define TX0_ANATXACONTROL1_ASYM_MODE_SHIFT 6 12863 12864 /* Tx0 :: anaTxAControl1 :: driver_vcm [05:04] */ 12865 #define TX0_ANATXACONTROL1_DRIVER_VCM_MASK 0x0030 12866 #define TX0_ANATXACONTROL1_DRIVER_VCM_ALIGN 0 12867 #define TX0_ANATXACONTROL1_DRIVER_VCM_BITS 2 12868 #define TX0_ANATXACONTROL1_DRIVER_VCM_SHIFT 4 12869 12870 /* Tx0 :: anaTxAControl1 :: amp_ctrl [03:03] */ 12871 #define TX0_ANATXACONTROL1_AMP_CTRL_MASK 0x0008 12872 #define TX0_ANATXACONTROL1_AMP_CTRL_ALIGN 0 12873 #define TX0_ANATXACONTROL1_AMP_CTRL_BITS 1 12874 #define TX0_ANATXACONTROL1_AMP_CTRL_SHIFT 3 12875 12876 /* Tx0 :: anaTxAControl1 :: ifullspd [02:00] */ 12877 #define TX0_ANATXACONTROL1_IFULLSPD_MASK 0x0007 12878 #define TX0_ANATXACONTROL1_IFULLSPD_ALIGN 0 12879 #define TX0_ANATXACONTROL1_IFULLSPD_BITS 3 12880 #define TX0_ANATXACONTROL1_IFULLSPD_SHIFT 0 12881 12882 12883 /**************************************************************************** 12884 * Tx0 :: anaTxAControl2 12885 */ 12886 /* Tx0 :: anaTxAControl2 :: icbuf1t [15:14] */ 12887 #define TX0_ANATXACONTROL2_ICBUF1T_MASK 0xc000 12888 #define TX0_ANATXACONTROL2_ICBUF1T_ALIGN 0 12889 #define TX0_ANATXACONTROL2_ICBUF1T_BITS 2 12890 #define TX0_ANATXACONTROL2_ICBUF1T_SHIFT 14 12891 12892 /* Tx0 :: anaTxAControl2 :: icbuf2t [13:11] */ 12893 #define TX0_ANATXACONTROL2_ICBUF2T_MASK 0x3800 12894 #define TX0_ANATXACONTROL2_ICBUF2T_ALIGN 0 12895 #define TX0_ANATXACONTROL2_ICBUF2T_BITS 3 12896 #define TX0_ANATXACONTROL2_ICBUF2T_SHIFT 11 12897 12898 /* Tx0 :: anaTxAControl2 :: imin_predrv [10:10] */ 12899 #define TX0_ANATXACONTROL2_IMIN_PREDRV_MASK 0x0400 12900 #define TX0_ANATXACONTROL2_IMIN_PREDRV_ALIGN 0 12901 #define TX0_ANATXACONTROL2_IMIN_PREDRV_BITS 1 12902 #define TX0_ANATXACONTROL2_IMIN_PREDRV_SHIFT 10 12903 12904 /* Tx0 :: anaTxAControl2 :: imax_predrv [09:09] */ 12905 #define TX0_ANATXACONTROL2_IMAX_PREDRV_MASK 0x0200 12906 #define TX0_ANATXACONTROL2_IMAX_PREDRV_ALIGN 0 12907 #define TX0_ANATXACONTROL2_IMAX_PREDRV_BITS 1 12908 #define TX0_ANATXACONTROL2_IMAX_PREDRV_SHIFT 9 12909 12910 /* Tx0 :: anaTxAControl2 :: imode_predrv [08:08] */ 12911 #define TX0_ANATXACONTROL2_IMODE_PREDRV_MASK 0x0100 12912 #define TX0_ANATXACONTROL2_IMODE_PREDRV_ALIGN 0 12913 #define TX0_ANATXACONTROL2_IMODE_PREDRV_BITS 1 12914 #define TX0_ANATXACONTROL2_IMODE_PREDRV_SHIFT 8 12915 12916 /* Tx0 :: anaTxAControl2 :: i21mux [07:05] */ 12917 #define TX0_ANATXACONTROL2_I21MUX_MASK 0x00e0 12918 #define TX0_ANATXACONTROL2_I21MUX_ALIGN 0 12919 #define TX0_ANATXACONTROL2_I21MUX_BITS 3 12920 #define TX0_ANATXACONTROL2_I21MUX_SHIFT 5 12921 12922 /* Tx0 :: anaTxAControl2 :: imin_drvr [04:04] */ 12923 #define TX0_ANATXACONTROL2_IMIN_DRVR_MASK 0x0010 12924 #define TX0_ANATXACONTROL2_IMIN_DRVR_ALIGN 0 12925 #define TX0_ANATXACONTROL2_IMIN_DRVR_BITS 1 12926 #define TX0_ANATXACONTROL2_IMIN_DRVR_SHIFT 4 12927 12928 /* Tx0 :: anaTxAControl2 :: imax_drvr [03:03] */ 12929 #define TX0_ANATXACONTROL2_IMAX_DRVR_MASK 0x0008 12930 #define TX0_ANATXACONTROL2_IMAX_DRVR_ALIGN 0 12931 #define TX0_ANATXACONTROL2_IMAX_DRVR_BITS 1 12932 #define TX0_ANATXACONTROL2_IMAX_DRVR_SHIFT 3 12933 12934 /* Tx0 :: anaTxAControl2 :: imode_drvr [02:02] */ 12935 #define TX0_ANATXACONTROL2_IMODE_DRVR_MASK 0x0004 12936 #define TX0_ANATXACONTROL2_IMODE_DRVR_ALIGN 0 12937 #define TX0_ANATXACONTROL2_IMODE_DRVR_BITS 1 12938 #define TX0_ANATXACONTROL2_IMODE_DRVR_SHIFT 2 12939 12940 /* Tx0 :: anaTxAControl2 :: reserved0 [01:00] */ 12941 #define TX0_ANATXACONTROL2_RESERVED0_MASK 0x0003 12942 #define TX0_ANATXACONTROL2_RESERVED0_ALIGN 0 12943 #define TX0_ANATXACONTROL2_RESERVED0_BITS 2 12944 #define TX0_ANATXACONTROL2_RESERVED0_SHIFT 0 12945 12946 12947 /**************************************************************************** 12948 * Tx0 :: Tx_Driver 12949 */ 12950 /* Tx0 :: Tx_Driver :: ElecIdle [15:15] */ 12951 #define TX0_TX_DRIVER_ELECIDLE_MASK 0x8000 12952 #define TX0_TX_DRIVER_ELECIDLE_ALIGN 0 12953 #define TX0_TX_DRIVER_ELECIDLE_BITS 1 12954 #define TX0_TX_DRIVER_ELECIDLE_SHIFT 15 12955 12956 /* Tx0 :: Tx_Driver :: post2_coeff [14:12] */ 12957 #define TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 12958 #define TX0_TX_DRIVER_POST2_COEFF_ALIGN 0 12959 #define TX0_TX_DRIVER_POST2_COEFF_BITS 3 12960 #define TX0_TX_DRIVER_POST2_COEFF_SHIFT 12 12961 12962 /* Tx0 :: Tx_Driver :: Idriver [11:08] */ 12963 #define TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 12964 #define TX0_TX_DRIVER_IDRIVER_ALIGN 0 12965 #define TX0_TX_DRIVER_IDRIVER_BITS 4 12966 #define TX0_TX_DRIVER_IDRIVER_SHIFT 8 12967 #define TX0_TX_DRIVER_IDRIVER_v680mV 0 12968 #define TX0_TX_DRIVER_IDRIVER_v730mV 1 12969 #define TX0_TX_DRIVER_IDRIVER_v780mV 2 12970 #define TX0_TX_DRIVER_IDRIVER_v830mV 3 12971 #define TX0_TX_DRIVER_IDRIVER_v880mV 4 12972 #define TX0_TX_DRIVER_IDRIVER_v930mV 5 12973 #define TX0_TX_DRIVER_IDRIVER_v980mV 6 12974 #define TX0_TX_DRIVER_IDRIVER_v1010mV 7 12975 #define TX0_TX_DRIVER_IDRIVER_v1040mV 8 12976 #define TX0_TX_DRIVER_IDRIVER_v1060mV 9 12977 #define TX0_TX_DRIVER_IDRIVER_v1070mV 10 12978 #define TX0_TX_DRIVER_IDRIVER_v1080mV 11 12979 #define TX0_TX_DRIVER_IDRIVER_v1085mV 12 12980 #define TX0_TX_DRIVER_IDRIVER_v1090mV 13 12981 #define TX0_TX_DRIVER_IDRIVER_v1095mV 14 12982 #define TX0_TX_DRIVER_IDRIVER_v1100mV 15 12983 12984 /* Tx0 :: Tx_Driver :: Ipredriver [07:04] */ 12985 #define TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 12986 #define TX0_TX_DRIVER_IPREDRIVER_ALIGN 0 12987 #define TX0_TX_DRIVER_IPREDRIVER_BITS 4 12988 #define TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 12989 12990 /* Tx0 :: Tx_Driver :: ifir [03:01] */ 12991 #define TX0_TX_DRIVER_IFIR_MASK 0x000e 12992 #define TX0_TX_DRIVER_IFIR_ALIGN 0 12993 #define TX0_TX_DRIVER_IFIR_BITS 3 12994 #define TX0_TX_DRIVER_IFIR_SHIFT 1 12995 12996 /* Tx0 :: Tx_Driver :: icbuf1t2 [00:00] */ 12997 #define TX0_TX_DRIVER_ICBUF1T2_MASK 0x0001 12998 #define TX0_TX_DRIVER_ICBUF1T2_ALIGN 0 12999 #define TX0_TX_DRIVER_ICBUF1T2_BITS 1 13000 #define TX0_TX_DRIVER_ICBUF1T2_SHIFT 0 13001 13002 13003 /**************************************************************************** 13004 * Tx0 :: anaTxAControl5 13005 */ 13006 /* Tx0 :: anaTxAControl5 :: reserved0 [15:15] */ 13007 #define TX0_ANATXACONTROL5_RESERVED0_MASK 0x8000 13008 #define TX0_ANATXACONTROL5_RESERVED0_ALIGN 0 13009 #define TX0_ANATXACONTROL5_RESERVED0_BITS 1 13010 #define TX0_ANATXACONTROL5_RESERVED0_SHIFT 15 13011 13012 /* Tx0 :: anaTxAControl5 :: tx_prbs_w_val [14:14] */ 13013 #define TX0_ANATXACONTROL5_TX_PRBS_W_VAL_MASK 0x4000 13014 #define TX0_ANATXACONTROL5_TX_PRBS_W_VAL_ALIGN 0 13015 #define TX0_ANATXACONTROL5_TX_PRBS_W_VAL_BITS 1 13016 #define TX0_ANATXACONTROL5_TX_PRBS_W_VAL_SHIFT 14 13017 13018 /* Tx0 :: anaTxAControl5 :: tx_prbs_w_force [13:13] */ 13019 #define TX0_ANATXACONTROL5_TX_PRBS_W_FORCE_MASK 0x2000 13020 #define TX0_ANATXACONTROL5_TX_PRBS_W_FORCE_ALIGN 0 13021 #define TX0_ANATXACONTROL5_TX_PRBS_W_FORCE_BITS 1 13022 #define TX0_ANATXACONTROL5_TX_PRBS_W_FORCE_SHIFT 13 13023 13024 /* Tx0 :: anaTxAControl5 :: tx_prbs_bswap [12:12] */ 13025 #define TX0_ANATXACONTROL5_TX_PRBS_BSWAP_MASK 0x1000 13026 #define TX0_ANATXACONTROL5_TX_PRBS_BSWAP_ALIGN 0 13027 #define TX0_ANATXACONTROL5_TX_PRBS_BSWAP_BITS 1 13028 #define TX0_ANATXACONTROL5_TX_PRBS_BSWAP_SHIFT 12 13029 13030 /* Tx0 :: anaTxAControl5 :: tx_bitswap [11:11] */ 13031 #define TX0_ANATXACONTROL5_TX_BITSWAP_MASK 0x0800 13032 #define TX0_ANATXACONTROL5_TX_BITSWAP_ALIGN 0 13033 #define TX0_ANATXACONTROL5_TX_BITSWAP_BITS 1 13034 #define TX0_ANATXACONTROL5_TX_BITSWAP_SHIFT 11 13035 13036 /* Tx0 :: anaTxAControl5 :: rst_tx_r [10:10] */ 13037 #define TX0_ANATXACONTROL5_RST_TX_R_MASK 0x0400 13038 #define TX0_ANATXACONTROL5_RST_TX_R_ALIGN 0 13039 #define TX0_ANATXACONTROL5_RST_TX_R_BITS 1 13040 #define TX0_ANATXACONTROL5_RST_TX_R_SHIFT 10 13041 13042 /* Tx0 :: anaTxAControl5 :: pwdwn_tx_r [09:09] */ 13043 #define TX0_ANATXACONTROL5_PWDWN_TX_R_MASK 0x0200 13044 #define TX0_ANATXACONTROL5_PWDWN_TX_R_ALIGN 0 13045 #define TX0_ANATXACONTROL5_PWDWN_TX_R_BITS 1 13046 #define TX0_ANATXACONTROL5_PWDWN_TX_R_SHIFT 9 13047 13048 /* Tx0 :: anaTxAControl5 :: tx_prbs_order_2 [08:08] */ 13049 #define TX0_ANATXACONTROL5_TX_PRBS_ORDER_2_MASK 0x0100 13050 #define TX0_ANATXACONTROL5_TX_PRBS_ORDER_2_ALIGN 0 13051 #define TX0_ANATXACONTROL5_TX_PRBS_ORDER_2_BITS 1 13052 #define TX0_ANATXACONTROL5_TX_PRBS_ORDER_2_SHIFT 8 13053 13054 /* Tx0 :: anaTxAControl5 :: ed8b10b_disable [07:07] */ 13055 #define TX0_ANATXACONTROL5_ED8B10B_DISABLE_MASK 0x0080 13056 #define TX0_ANATXACONTROL5_ED8B10B_DISABLE_ALIGN 0 13057 #define TX0_ANATXACONTROL5_ED8B10B_DISABLE_BITS 1 13058 #define TX0_ANATXACONTROL5_ED8B10B_DISABLE_SHIFT 7 13059 13060 /* Tx0 :: anaTxAControl5 :: tx_prbs_decouple_en [06:06] */ 13061 #define TX0_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_MASK 0x0040 13062 #define TX0_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_ALIGN 0 13063 #define TX0_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_BITS 1 13064 #define TX0_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_SHIFT 6 13065 13066 /* Tx0 :: anaTxAControl5 :: tx_prbs_en_decouple [05:05] */ 13067 #define TX0_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_MASK 0x0020 13068 #define TX0_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_ALIGN 0 13069 #define TX0_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_BITS 1 13070 #define TX0_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_SHIFT 5 13071 13072 /* Tx0 :: anaTxAControl5 :: tx_prbs_inv_decouple [04:04] */ 13073 #define TX0_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_MASK 0x0010 13074 #define TX0_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_ALIGN 0 13075 #define TX0_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_BITS 1 13076 #define TX0_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_SHIFT 4 13077 13078 /* Tx0 :: anaTxAControl5 :: tx_prbs_order_decouple [03:02] */ 13079 #define TX0_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_MASK 0x000c 13080 #define TX0_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_ALIGN 0 13081 #define TX0_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_BITS 2 13082 #define TX0_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_SHIFT 2 13083 13084 /* Tx0 :: anaTxAControl5 :: force_tx_sel_halfrate_val [01:01] */ 13085 #define TX0_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_MASK 0x0002 13086 #define TX0_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_ALIGN 0 13087 #define TX0_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_BITS 1 13088 #define TX0_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_SHIFT 1 13089 13090 /* Tx0 :: anaTxAControl5 :: force_tx_sel_halfrate [00:00] */ 13091 #define TX0_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_MASK 0x0001 13092 #define TX0_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_ALIGN 0 13093 #define TX0_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_BITS 1 13094 #define TX0_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_SHIFT 0 13095 13096 13097 /**************************************************************************** 13098 * Tx0 :: anaTxAControl6 13099 */ 13100 #ifdef BCM_TRIUMPH3_SUPPORT 13101 /* Tx1 :: anaTxAControl6 :: reserved0 [15:10] */ 13102 #define TX0_ANATXACONTROL6_TXFIRTAPMAIN_MASK 0xfc00 13103 #define TX0_ANATXACONTROL6_TXFIRTAPMAIN_ALIGN 0 13104 #define TX0_ANATXACONTROL6_TXFIRTAPMAIN_BITS 6 13105 #define TX0_ANATXACONTROL6_TXFIRTAPMAIN_SHIFT 10 13106 /* Tx1 :: anaTxAControl6 :: sel_8b10b_default_cya [09:05] */ 13107 #define TX0_ANATXACONTROL6_TXFIRTAPPOST_MASK 0x03e0 13108 #define TX0_ANATXACONTROL6_TXFIRTAPPOST_ALIGN 0 13109 #define TX0_ANATXACONTROL6_TXFIRTAPPOST_BITS 5 13110 #define TX0_ANATXACONTROL6_TXFIRTAPPOST_SHIFT 5 13111 #else 13112 /* Tx0 :: anaTxAControl6 :: reserved0 [15:06] */ 13113 #define TX0_ANATXACONTROL6_RESERVED0_MASK 0xffc0 13114 #define TX0_ANATXACONTROL6_RESERVED0_ALIGN 0 13115 #define TX0_ANATXACONTROL6_RESERVED0_BITS 10 13116 #define TX0_ANATXACONTROL6_RESERVED0_SHIFT 6 13117 13118 /* Tx0 :: anaTxAControl6 :: sel_8b10b_default_cya [05:05] */ 13119 #define TX0_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_MASK 0x0020 13120 #define TX0_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_ALIGN 0 13121 #define TX0_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_BITS 1 13122 #define TX0_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_SHIFT 5 13123 #endif 13124 /* Tx0 :: anaTxAControl6 :: ckgate_int_sel_div1_1p5_2_2p5 [04:04] */ 13125 #define TX0_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_MASK 0x0010 13126 #define TX0_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_ALIGN 0 13127 #define TX0_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_BITS 1 13128 #define TX0_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_SHIFT 4 13129 13130 /* Tx0 :: anaTxAControl6 :: gloop_r [03:03] */ 13131 #define TX0_ANATXACONTROL6_GLOOP_R_MASK 0x0008 13132 #define TX0_ANATXACONTROL6_GLOOP_R_ALIGN 0 13133 #define TX0_ANATXACONTROL6_GLOOP_R_BITS 1 13134 #define TX0_ANATXACONTROL6_GLOOP_R_SHIFT 3 13135 13136 /* Tx0 :: anaTxAControl6 :: rloop_r [02:02] */ 13137 #define TX0_ANATXACONTROL6_RLOOP_R_MASK 0x0004 13138 #define TX0_ANATXACONTROL6_RLOOP_R_ALIGN 0 13139 #define TX0_ANATXACONTROL6_RLOOP_R_BITS 1 13140 #define TX0_ANATXACONTROL6_RLOOP_R_SHIFT 2 13141 13142 /* Tx0 :: anaTxAControl6 :: ckgate_ext_sel [01:01] */ 13143 #define TX0_ANATXACONTROL6_CKGATE_EXT_SEL_MASK 0x0002 13144 #define TX0_ANATXACONTROL6_CKGATE_EXT_SEL_ALIGN 0 13145 #define TX0_ANATXACONTROL6_CKGATE_EXT_SEL_BITS 1 13146 #define TX0_ANATXACONTROL6_CKGATE_EXT_SEL_SHIFT 1 13147 13148 /* Tx0 :: anaTxAControl6 :: disable_tx_r [00:00] */ 13149 #define TX0_ANATXACONTROL6_DISABLE_TX_R_MASK 0x0001 13150 #define TX0_ANATXACONTROL6_DISABLE_TX_R_ALIGN 0 13151 #define TX0_ANATXACONTROL6_DISABLE_TX_R_BITS 1 13152 #define TX0_ANATXACONTROL6_DISABLE_TX_R_SHIFT 0 13153 13154 13155 /**************************************************************************** 13156 * Warpcore_USER_Tx1 13157 */ 13158 /**************************************************************************** 13159 * Tx1 :: anaTxAStatus0 13160 */ 13161 /* union - case txStatusSelect_equals_0 [15:00] */ 13162 /* Tx1 :: anaTxAStatus0 :: reserved0 [15:11] */ 13163 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_MASK 0xf800 13164 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_ALIGN 0 13165 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_BITS 5 13166 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_SHIFT 11 13167 13168 /* Tx1 :: anaTxAStatus0 :: oscdr_mode_indch_tx [10:07] */ 13169 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_MASK 0x0780 13170 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_ALIGN 0 13171 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_BITS 4 13172 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_SHIFT 7 13173 13174 /* Tx1 :: anaTxAStatus0 :: txdisable_ln [06:06] */ 13175 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_MASK 0x0040 13176 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_ALIGN 0 13177 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_BITS 1 13178 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_SHIFT 6 13179 13180 /* Tx1 :: anaTxAStatus0 :: txferr_stky [05:05] */ 13181 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_MASK 0x0020 13182 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_ALIGN 0 13183 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_BITS 1 13184 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_SHIFT 5 13185 13186 /* Tx1 :: anaTxAStatus0 :: tbi_mode [04:04] */ 13187 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_MASK 0x0010 13188 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_ALIGN 0 13189 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_BITS 1 13190 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_SHIFT 4 13191 13192 /* Tx1 :: anaTxAStatus0 :: tx_reset [03:03] */ 13193 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_MASK 0x0008 13194 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_ALIGN 0 13195 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_BITS 1 13196 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_SHIFT 3 13197 13198 /* Tx1 :: anaTxAStatus0 :: tx_pwrdn [02:02] */ 13199 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_MASK 0x0004 13200 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_ALIGN 0 13201 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_BITS 1 13202 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_SHIFT 2 13203 13204 /* Tx1 :: anaTxAStatus0 :: rltxferr_stky [01:01] */ 13205 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_MASK 0x0002 13206 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_ALIGN 0 13207 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_BITS 1 13208 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_SHIFT 1 13209 13210 /* Tx1 :: anaTxAStatus0 :: txpll_lock [00:00] */ 13211 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_MASK 0x0001 13212 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_ALIGN 0 13213 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_BITS 1 13214 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_SHIFT 0 13215 13216 13217 /* union - case txStatusSelect_equals_1 [15:00] */ 13218 /* Tx1 :: anaTxAStatus0 :: tx_sel_halfrate [15:15] */ 13219 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_MASK 0x8000 13220 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_ALIGN 0 13221 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_BITS 1 13222 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_SHIFT 15 13223 13224 /* Tx1 :: anaTxAStatus0 :: tx_fir_tap_post [14:10] */ 13225 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_MASK 0x7c00 13226 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_ALIGN 0 13227 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_BITS 5 13228 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_SHIFT 10 13229 13230 /* Tx1 :: anaTxAStatus0 :: tx_fir_tap_main [09:04] */ 13231 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_MASK 0x03f0 13232 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_ALIGN 0 13233 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_BITS 6 13234 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_SHIFT 4 13235 13236 /* Tx1 :: anaTxAStatus0 :: tx_fir_tap_pre [03:00] */ 13237 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_MASK 0x000f 13238 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_ALIGN 0 13239 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_BITS 4 13240 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_SHIFT 0 13241 13242 13243 13244 /**************************************************************************** 13245 * Tx1 :: anaTxAControl0 13246 */ 13247 /* Tx1 :: anaTxAControl0 :: reserved0 [15:15] */ 13248 #define TX1_ANATXACONTROL0_RESERVED0_MASK 0x8000 13249 #define TX1_ANATXACONTROL0_RESERVED0_ALIGN 0 13250 #define TX1_ANATXACONTROL0_RESERVED0_BITS 1 13251 #define TX1_ANATXACONTROL0_RESERVED0_SHIFT 15 13252 13253 /* Tx1 :: anaTxAControl0 :: force_txclk [14:14] */ 13254 #define TX1_ANATXACONTROL0_FORCE_TXCLK_MASK 0x4000 13255 #define TX1_ANATXACONTROL0_FORCE_TXCLK_ALIGN 0 13256 #define TX1_ANATXACONTROL0_FORCE_TXCLK_BITS 1 13257 #define TX1_ANATXACONTROL0_FORCE_TXCLK_SHIFT 14 13258 13259 /* Tx1 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */ 13260 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_MASK 0x2000 13261 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN 0 13262 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_BITS 1 13263 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT 13 13264 13265 /* Tx1 :: anaTxAControl0 :: force_ext_frst_SM [12:12] */ 13266 #define TX1_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK 0x1000 13267 #define TX1_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN 0 13268 #define TX1_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS 1 13269 #define TX1_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT 12 13270 13271 /* Tx1 :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */ 13272 #define TX1_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK 0x0800 13273 #define TX1_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN 0 13274 #define TX1_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS 1 13275 #define TX1_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT 11 13276 13277 /* Tx1 :: anaTxAControl0 :: txck_dme_en_SM [10:10] */ 13278 #define TX1_ANATXACONTROL0_TXCK_DME_EN_SM_MASK 0x0400 13279 #define TX1_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN 0 13280 #define TX1_ANATXACONTROL0_TXCK_DME_EN_SM_BITS 1 13281 #define TX1_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT 10 13282 13283 /* Tx1 :: anaTxAControl0 :: gloopOutDis [09:09] */ 13284 #define TX1_ANATXACONTROL0_GLOOPOUTDIS_MASK 0x0200 13285 #define TX1_ANATXACONTROL0_GLOOPOUTDIS_ALIGN 0 13286 #define TX1_ANATXACONTROL0_GLOOPOUTDIS_BITS 1 13287 #define TX1_ANATXACONTROL0_GLOOPOUTDIS_SHIFT 9 13288 13289 /* Tx1 :: anaTxAControl0 :: prbs_en [08:08] */ 13290 #define TX1_ANATXACONTROL0_PRBS_EN_MASK 0x0100 13291 #define TX1_ANATXACONTROL0_PRBS_EN_ALIGN 0 13292 #define TX1_ANATXACONTROL0_PRBS_EN_BITS 1 13293 #define TX1_ANATXACONTROL0_PRBS_EN_SHIFT 8 13294 13295 /* Tx1 :: anaTxAControl0 :: pckt_en [07:07] */ 13296 #define TX1_ANATXACONTROL0_PCKT_EN_MASK 0x0080 13297 #define TX1_ANATXACONTROL0_PCKT_EN_ALIGN 0 13298 #define TX1_ANATXACONTROL0_PCKT_EN_BITS 1 13299 #define TX1_ANATXACONTROL0_PCKT_EN_SHIFT 7 13300 13301 /* Tx1 :: anaTxAControl0 :: pckt_strt [06:06] */ 13302 #define TX1_ANATXACONTROL0_PCKT_STRT_MASK 0x0040 13303 #define TX1_ANATXACONTROL0_PCKT_STRT_ALIGN 0 13304 #define TX1_ANATXACONTROL0_PCKT_STRT_BITS 1 13305 #define TX1_ANATXACONTROL0_PCKT_STRT_SHIFT 6 13306 13307 /* Tx1 :: anaTxAControl0 :: txpol_flip [05:05] */ 13308 #define TX1_ANATXACONTROL0_TXPOL_FLIP_MASK 0x0020 13309 #define TX1_ANATXACONTROL0_TXPOL_FLIP_ALIGN 0 13310 #define TX1_ANATXACONTROL0_TXPOL_FLIP_BITS 1 13311 #define TX1_ANATXACONTROL0_TXPOL_FLIP_SHIFT 5 13312 13313 /* Tx1 :: anaTxAControl0 :: rtbi_flip [04:04] */ 13314 #define TX1_ANATXACONTROL0_RTBI_FLIP_MASK 0x0010 13315 #define TX1_ANATXACONTROL0_RTBI_FLIP_ALIGN 0 13316 #define TX1_ANATXACONTROL0_RTBI_FLIP_BITS 1 13317 #define TX1_ANATXACONTROL0_RTBI_FLIP_SHIFT 4 13318 13319 /* Tx1 :: anaTxAControl0 :: eden_r [03:03] */ 13320 #define TX1_ANATXACONTROL0_EDEN_R_MASK 0x0008 13321 #define TX1_ANATXACONTROL0_EDEN_R_ALIGN 0 13322 #define TX1_ANATXACONTROL0_EDEN_R_BITS 1 13323 #define TX1_ANATXACONTROL0_EDEN_R_SHIFT 3 13324 13325 /* Tx1 :: anaTxAControl0 :: eden_force_r [02:02] */ 13326 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_MASK 0x0004 13327 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_ALIGN 0 13328 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_BITS 1 13329 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_SHIFT 2 13330 13331 /* Tx1 :: anaTxAControl0 :: txpat_en [01:01] */ 13332 #define TX1_ANATXACONTROL0_TXPAT_EN_MASK 0x0002 13333 #define TX1_ANATXACONTROL0_TXPAT_EN_ALIGN 0 13334 #define TX1_ANATXACONTROL0_TXPAT_EN_BITS 1 13335 #define TX1_ANATXACONTROL0_TXPAT_EN_SHIFT 1 13336 13337 /* Tx1 :: anaTxAControl0 :: tx_mdata_en [00:00] */ 13338 #define TX1_ANATXACONTROL0_TX_MDATA_EN_MASK 0x0001 13339 #define TX1_ANATXACONTROL0_TX_MDATA_EN_ALIGN 0 13340 #define TX1_ANATXACONTROL0_TX_MDATA_EN_BITS 1 13341 #define TX1_ANATXACONTROL0_TX_MDATA_EN_SHIFT 0 13342 13343 13344 /**************************************************************************** 13345 * Tx1 :: anaTxmdata0 13346 */ 13347 /* Tx1 :: anaTxmdata0 :: txTestMuxSel [15:13] */ 13348 #define TX1_ANATXMDATA0_TXTESTMUXSEL_MASK 0xe000 13349 #define TX1_ANATXMDATA0_TXTESTMUXSEL_ALIGN 0 13350 #define TX1_ANATXMDATA0_TXTESTMUXSEL_BITS 3 13351 #define TX1_ANATXMDATA0_TXTESTMUXSEL_SHIFT 13 13352 13353 /* Tx1 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */ 13354 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_MASK 0x1c00 13355 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN 0 13356 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_BITS 3 13357 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT 10 13358 13359 /* Tx1 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */ 13360 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_MASK 0x03ff 13361 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN 0 13362 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_BITS 10 13363 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT 0 13364 13365 13366 /**************************************************************************** 13367 * Tx1 :: anaTxmdata1 13368 */ 13369 /* Tx1 :: anaTxmdata1 :: txStatusSelect [15:14] */ 13370 #define TX1_ANATXMDATA1_TXSTATUSSELECT_MASK 0xc000 13371 #define TX1_ANATXMDATA1_TXSTATUSSELECT_ALIGN 0 13372 #define TX1_ANATXMDATA1_TXSTATUSSELECT_BITS 2 13373 #define TX1_ANATXMDATA1_TXSTATUSSELECT_SHIFT 14 13374 13375 /* Tx1 :: anaTxmdata1 :: reserved0 [13:10] */ 13376 #define TX1_ANATXMDATA1_RESERVED0_MASK 0x3c00 13377 #define TX1_ANATXMDATA1_RESERVED0_ALIGN 0 13378 #define TX1_ANATXMDATA1_RESERVED0_BITS 4 13379 #define TX1_ANATXMDATA1_RESERVED0_SHIFT 10 13380 13381 /* Tx1 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */ 13382 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_MASK 0x03ff 13383 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN 0 13384 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_BITS 10 13385 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT 0 13386 13387 13388 /**************************************************************************** 13389 * Tx1 :: anaTxAStatus1 13390 */ 13391 /* Tx1 :: anaTxAStatus1 :: tx_id [15:14] */ 13392 #define TX1_ANATXASTATUS1_TX_ID_MASK 0xc000 13393 #define TX1_ANATXASTATUS1_TX_ID_ALIGN 0 13394 #define TX1_ANATXASTATUS1_TX_ID_BITS 2 13395 #define TX1_ANATXASTATUS1_TX_ID_SHIFT 14 13396 13397 /* Tx1 :: anaTxAStatus1 :: reserved0 [13:08] */ 13398 #define TX1_ANATXASTATUS1_RESERVED0_MASK 0x3f00 13399 #define TX1_ANATXASTATUS1_RESERVED0_ALIGN 0 13400 #define TX1_ANATXASTATUS1_RESERVED0_BITS 6 13401 #define TX1_ANATXASTATUS1_RESERVED0_SHIFT 8 13402 13403 /* Tx1 :: anaTxAStatus1 :: version_id [07:04] */ 13404 #define TX1_ANATXASTATUS1_VERSION_ID_MASK 0x00f0 13405 #define TX1_ANATXASTATUS1_VERSION_ID_ALIGN 0 13406 #define TX1_ANATXASTATUS1_VERSION_ID_BITS 4 13407 #define TX1_ANATXASTATUS1_VERSION_ID_SHIFT 4 13408 13409 /* Tx1 :: anaTxAStatus1 :: reserved1 [03:00] */ 13410 #define TX1_ANATXASTATUS1_RESERVED1_MASK 0x000f 13411 #define TX1_ANATXASTATUS1_RESERVED1_ALIGN 0 13412 #define TX1_ANATXASTATUS1_RESERVED1_BITS 4 13413 #define TX1_ANATXASTATUS1_RESERVED1_SHIFT 0 13414 13415 13416 /**************************************************************************** 13417 * Tx1 :: anaTxAControl1 13418 */ 13419 /* Tx1 :: anaTxAControl1 :: ipredrv [15:13] */ 13420 #define TX1_ANATXACONTROL1_IPREDRV_MASK 0xe000 13421 #define TX1_ANATXACONTROL1_IPREDRV_ALIGN 0 13422 #define TX1_ANATXACONTROL1_IPREDRV_BITS 3 13423 #define TX1_ANATXACONTROL1_IPREDRV_SHIFT 13 13424 13425 /* Tx1 :: anaTxAControl1 :: refl_tx [12:12] */ 13426 #define TX1_ANATXACONTROL1_REFL_TX_MASK 0x1000 13427 #define TX1_ANATXACONTROL1_REFL_TX_ALIGN 0 13428 #define TX1_ANATXACONTROL1_REFL_TX_BITS 1 13429 #define TX1_ANATXACONTROL1_REFL_TX_SHIFT 12 13430 13431 /* Tx1 :: anaTxAControl1 :: refh_tx [11:11] */ 13432 #define TX1_ANATXACONTROL1_REFH_TX_MASK 0x0800 13433 #define TX1_ANATXACONTROL1_REFH_TX_ALIGN 0 13434 #define TX1_ANATXACONTROL1_REFH_TX_BITS 1 13435 #define TX1_ANATXACONTROL1_REFH_TX_SHIFT 11 13436 13437 /* Tx1 :: anaTxAControl1 :: newbias_en [10:10] */ 13438 #define TX1_ANATXACONTROL1_NEWBIAS_EN_MASK 0x0400 13439 #define TX1_ANATXACONTROL1_NEWBIAS_EN_ALIGN 0 13440 #define TX1_ANATXACONTROL1_NEWBIAS_EN_BITS 1 13441 #define TX1_ANATXACONTROL1_NEWBIAS_EN_SHIFT 10 13442 13443 /* Tx1 :: anaTxAControl1 :: drivermode [09:09] */ 13444 #define TX1_ANATXACONTROL1_DRIVERMODE_MASK 0x0200 13445 #define TX1_ANATXACONTROL1_DRIVERMODE_ALIGN 0 13446 #define TX1_ANATXACONTROL1_DRIVERMODE_BITS 1 13447 #define TX1_ANATXACONTROL1_DRIVERMODE_SHIFT 9 13448 13449 /* Tx1 :: anaTxAControl1 :: vddr_bgb [08:08] */ 13450 #define TX1_ANATXACONTROL1_VDDR_BGB_MASK 0x0100 13451 #define TX1_ANATXACONTROL1_VDDR_BGB_ALIGN 0 13452 #define TX1_ANATXACONTROL1_VDDR_BGB_BITS 1 13453 #define TX1_ANATXACONTROL1_VDDR_BGB_SHIFT 8 13454 13455 /* Tx1 :: anaTxAControl1 :: ticksel [07:06] */ 13456 #define TX1_ANATXACONTROL1_TICKSEL_MASK 0x00c0 13457 #define TX1_ANATXACONTROL1_TICKSEL_ALIGN 0 13458 #define TX1_ANATXACONTROL1_TICKSEL_BITS 2 13459 #define TX1_ANATXACONTROL1_TICKSEL_SHIFT 6 13460 13461 /* Tx1 :: (for xenia only anaTxAControl1 :: ticksel [06:06] */ 13462 #define TX1_ANATXACONTROL1_ASYM_MODE_MASK 0x0040 13463 #define TX1_ANATXACONTROL1_ASYM_MODE_ALIGN 0 13464 #define TX1_ANATXACONTROL1_ASYM_MODE_BITS 1 13465 #define TX1_ANATXACONTROL1_ASYM_MODE_SHIFT 6 13466 13467 /* Tx1 :: anaTxAControl1 :: driver_vcm [05:04] */ 13468 #define TX1_ANATXACONTROL1_DRIVER_VCM_MASK 0x0030 13469 #define TX1_ANATXACONTROL1_DRIVER_VCM_ALIGN 0 13470 #define TX1_ANATXACONTROL1_DRIVER_VCM_BITS 2 13471 #define TX1_ANATXACONTROL1_DRIVER_VCM_SHIFT 4 13472 13473 /* Tx1 :: anaTxAControl1 :: amp_ctrl [03:03] */ 13474 #define TX1_ANATXACONTROL1_AMP_CTRL_MASK 0x0008 13475 #define TX1_ANATXACONTROL1_AMP_CTRL_ALIGN 0 13476 #define TX1_ANATXACONTROL1_AMP_CTRL_BITS 1 13477 #define TX1_ANATXACONTROL1_AMP_CTRL_SHIFT 3 13478 13479 /* Tx1 :: anaTxAControl1 :: ifullspd [02:00] */ 13480 #define TX1_ANATXACONTROL1_IFULLSPD_MASK 0x0007 13481 #define TX1_ANATXACONTROL1_IFULLSPD_ALIGN 0 13482 #define TX1_ANATXACONTROL1_IFULLSPD_BITS 3 13483 #define TX1_ANATXACONTROL1_IFULLSPD_SHIFT 0 13484 13485 13486 /**************************************************************************** 13487 * Tx1 :: anaTxAControl2 13488 */ 13489 /* Tx1 :: anaTxAControl2 :: icbuf1t [15:14] */ 13490 #define TX1_ANATXACONTROL2_ICBUF1T_MASK 0xc000 13491 #define TX1_ANATXACONTROL2_ICBUF1T_ALIGN 0 13492 #define TX1_ANATXACONTROL2_ICBUF1T_BITS 2 13493 #define TX1_ANATXACONTROL2_ICBUF1T_SHIFT 14 13494 13495 /* Tx1 :: anaTxAControl2 :: icbuf2t [13:11] */ 13496 #define TX1_ANATXACONTROL2_ICBUF2T_MASK 0x3800 13497 #define TX1_ANATXACONTROL2_ICBUF2T_ALIGN 0 13498 #define TX1_ANATXACONTROL2_ICBUF2T_BITS 3 13499 #define TX1_ANATXACONTROL2_ICBUF2T_SHIFT 11 13500 13501 /* Tx1 :: anaTxAControl2 :: imin_predrv [10:10] */ 13502 #define TX1_ANATXACONTROL2_IMIN_PREDRV_MASK 0x0400 13503 #define TX1_ANATXACONTROL2_IMIN_PREDRV_ALIGN 0 13504 #define TX1_ANATXACONTROL2_IMIN_PREDRV_BITS 1 13505 #define TX1_ANATXACONTROL2_IMIN_PREDRV_SHIFT 10 13506 13507 /* Tx1 :: anaTxAControl2 :: imax_predrv [09:09] */ 13508 #define TX1_ANATXACONTROL2_IMAX_PREDRV_MASK 0x0200 13509 #define TX1_ANATXACONTROL2_IMAX_PREDRV_ALIGN 0 13510 #define TX1_ANATXACONTROL2_IMAX_PREDRV_BITS 1 13511 #define TX1_ANATXACONTROL2_IMAX_PREDRV_SHIFT 9 13512 13513 /* Tx1 :: anaTxAControl2 :: imode_predrv [08:08] */ 13514 #define TX1_ANATXACONTROL2_IMODE_PREDRV_MASK 0x0100 13515 #define TX1_ANATXACONTROL2_IMODE_PREDRV_ALIGN 0 13516 #define TX1_ANATXACONTROL2_IMODE_PREDRV_BITS 1 13517 #define TX1_ANATXACONTROL2_IMODE_PREDRV_SHIFT 8 13518 13519 /* Tx1 :: anaTxAControl2 :: i21mux [07:05] */ 13520 #define TX1_ANATXACONTROL2_I21MUX_MASK 0x00e0 13521 #define TX1_ANATXACONTROL2_I21MUX_ALIGN 0 13522 #define TX1_ANATXACONTROL2_I21MUX_BITS 3 13523 #define TX1_ANATXACONTROL2_I21MUX_SHIFT 5 13524 13525 /* Tx1 :: anaTxAControl2 :: imin_drvr [04:04] */ 13526 #define TX1_ANATXACONTROL2_IMIN_DRVR_MASK 0x0010 13527 #define TX1_ANATXACONTROL2_IMIN_DRVR_ALIGN 0 13528 #define TX1_ANATXACONTROL2_IMIN_DRVR_BITS 1 13529 #define TX1_ANATXACONTROL2_IMIN_DRVR_SHIFT 4 13530 13531 /* Tx1 :: anaTxAControl2 :: imax_drvr [03:03] */ 13532 #define TX1_ANATXACONTROL2_IMAX_DRVR_MASK 0x0008 13533 #define TX1_ANATXACONTROL2_IMAX_DRVR_ALIGN 0 13534 #define TX1_ANATXACONTROL2_IMAX_DRVR_BITS 1 13535 #define TX1_ANATXACONTROL2_IMAX_DRVR_SHIFT 3 13536 13537 /* Tx1 :: anaTxAControl2 :: imode_drvr [02:02] */ 13538 #define TX1_ANATXACONTROL2_IMODE_DRVR_MASK 0x0004 13539 #define TX1_ANATXACONTROL2_IMODE_DRVR_ALIGN 0 13540 #define TX1_ANATXACONTROL2_IMODE_DRVR_BITS 1 13541 #define TX1_ANATXACONTROL2_IMODE_DRVR_SHIFT 2 13542 13543 /* Tx1 :: anaTxAControl2 :: reserved0 [01:00] */ 13544 #define TX1_ANATXACONTROL2_RESERVED0_MASK 0x0003 13545 #define TX1_ANATXACONTROL2_RESERVED0_ALIGN 0 13546 #define TX1_ANATXACONTROL2_RESERVED0_BITS 2 13547 #define TX1_ANATXACONTROL2_RESERVED0_SHIFT 0 13548 13549 13550 /**************************************************************************** 13551 * Tx1 :: Tx_Driver 13552 */ 13553 /* Tx1 :: Tx_Driver :: ElecIdle [15:15] */ 13554 #define TX1_TX_DRIVER_ELECIDLE_MASK 0x8000 13555 #define TX1_TX_DRIVER_ELECIDLE_ALIGN 0 13556 #define TX1_TX_DRIVER_ELECIDLE_BITS 1 13557 #define TX1_TX_DRIVER_ELECIDLE_SHIFT 15 13558 13559 /* Tx1 :: Tx_Driver :: post2_coeff [14:12] */ 13560 #define TX1_TX_DRIVER_POST2_COEFF_MASK 0x7000 13561 #define TX1_TX_DRIVER_POST2_COEFF_ALIGN 0 13562 #define TX1_TX_DRIVER_POST2_COEFF_BITS 3 13563 #define TX1_TX_DRIVER_POST2_COEFF_SHIFT 12 13564 13565 /* Tx1 :: Tx_Driver :: Idriver [11:08] */ 13566 #define TX1_TX_DRIVER_IDRIVER_MASK 0x0f00 13567 #define TX1_TX_DRIVER_IDRIVER_ALIGN 0 13568 #define TX1_TX_DRIVER_IDRIVER_BITS 4 13569 #define TX1_TX_DRIVER_IDRIVER_SHIFT 8 13570 #define TX1_TX_DRIVER_IDRIVER_v680mV 0 13571 #define TX1_TX_DRIVER_IDRIVER_v730mV 1 13572 #define TX1_TX_DRIVER_IDRIVER_v780mV 2 13573 #define TX1_TX_DRIVER_IDRIVER_v830mV 3 13574 #define TX1_TX_DRIVER_IDRIVER_v880mV 4 13575 #define TX1_TX_DRIVER_IDRIVER_v930mV 5 13576 #define TX1_TX_DRIVER_IDRIVER_v980mV 6 13577 #define TX1_TX_DRIVER_IDRIVER_v1010mV 7 13578 #define TX1_TX_DRIVER_IDRIVER_v1040mV 8 13579 #define TX1_TX_DRIVER_IDRIVER_v1060mV 9 13580 #define TX1_TX_DRIVER_IDRIVER_v1070mV 10 13581 #define TX1_TX_DRIVER_IDRIVER_v1080mV 11 13582 #define TX1_TX_DRIVER_IDRIVER_v1085mV 12 13583 #define TX1_TX_DRIVER_IDRIVER_v1090mV 13 13584 #define TX1_TX_DRIVER_IDRIVER_v1095mV 14 13585 #define TX1_TX_DRIVER_IDRIVER_v1100mV 15 13586 13587 /* Tx1 :: Tx_Driver :: Ipredriver [07:04] */ 13588 #define TX1_TX_DRIVER_IPREDRIVER_MASK 0x00f0 13589 #define TX1_TX_DRIVER_IPREDRIVER_ALIGN 0 13590 #define TX1_TX_DRIVER_IPREDRIVER_BITS 4 13591 #define TX1_TX_DRIVER_IPREDRIVER_SHIFT 4 13592 13593 /* Tx1 :: Tx_Driver :: ifir [03:01] */ 13594 #define TX1_TX_DRIVER_IFIR_MASK 0x000e 13595 #define TX1_TX_DRIVER_IFIR_ALIGN 0 13596 #define TX1_TX_DRIVER_IFIR_BITS 3 13597 #define TX1_TX_DRIVER_IFIR_SHIFT 1 13598 13599 /* Tx1 :: Tx_Driver :: icbuf1t2 [00:00] */ 13600 #define TX1_TX_DRIVER_ICBUF1T2_MASK 0x0001 13601 #define TX1_TX_DRIVER_ICBUF1T2_ALIGN 0 13602 #define TX1_TX_DRIVER_ICBUF1T2_BITS 1 13603 #define TX1_TX_DRIVER_ICBUF1T2_SHIFT 0 13604 13605 13606 /**************************************************************************** 13607 * Tx1 :: anaTxAControl5 13608 */ 13609 /* Tx1 :: anaTxAControl5 :: reserved0 [15:15] */ 13610 #define TX1_ANATXACONTROL5_RESERVED0_MASK 0x8000 13611 #define TX1_ANATXACONTROL5_RESERVED0_ALIGN 0 13612 #define TX1_ANATXACONTROL5_RESERVED0_BITS 1 13613 #define TX1_ANATXACONTROL5_RESERVED0_SHIFT 15 13614 13615 /* Tx1 :: anaTxAControl5 :: tx_prbs_w_val [14:14] */ 13616 #define TX1_ANATXACONTROL5_TX_PRBS_W_VAL_MASK 0x4000 13617 #define TX1_ANATXACONTROL5_TX_PRBS_W_VAL_ALIGN 0 13618 #define TX1_ANATXACONTROL5_TX_PRBS_W_VAL_BITS 1 13619 #define TX1_ANATXACONTROL5_TX_PRBS_W_VAL_SHIFT 14 13620 13621 /* Tx1 :: anaTxAControl5 :: tx_prbs_w_force [13:13] */ 13622 #define TX1_ANATXACONTROL5_TX_PRBS_W_FORCE_MASK 0x2000 13623 #define TX1_ANATXACONTROL5_TX_PRBS_W_FORCE_ALIGN 0 13624 #define TX1_ANATXACONTROL5_TX_PRBS_W_FORCE_BITS 1 13625 #define TX1_ANATXACONTROL5_TX_PRBS_W_FORCE_SHIFT 13 13626 13627 /* Tx1 :: anaTxAControl5 :: tx_prbs_bswap [12:12] */ 13628 #define TX1_ANATXACONTROL5_TX_PRBS_BSWAP_MASK 0x1000 13629 #define TX1_ANATXACONTROL5_TX_PRBS_BSWAP_ALIGN 0 13630 #define TX1_ANATXACONTROL5_TX_PRBS_BSWAP_BITS 1 13631 #define TX1_ANATXACONTROL5_TX_PRBS_BSWAP_SHIFT 12 13632 13633 /* Tx1 :: anaTxAControl5 :: tx_bitswap [11:11] */ 13634 #define TX1_ANATXACONTROL5_TX_BITSWAP_MASK 0x0800 13635 #define TX1_ANATXACONTROL5_TX_BITSWAP_ALIGN 0 13636 #define TX1_ANATXACONTROL5_TX_BITSWAP_BITS 1 13637 #define TX1_ANATXACONTROL5_TX_BITSWAP_SHIFT 11 13638 13639 /* Tx1 :: anaTxAControl5 :: rst_tx_r [10:10] */ 13640 #define TX1_ANATXACONTROL5_RST_TX_R_MASK 0x0400 13641 #define TX1_ANATXACONTROL5_RST_TX_R_ALIGN 0 13642 #define TX1_ANATXACONTROL5_RST_TX_R_BITS 1 13643 #define TX1_ANATXACONTROL5_RST_TX_R_SHIFT 10 13644 13645 /* Tx1 :: anaTxAControl5 :: pwdwn_tx_r [09:09] */ 13646 #define TX1_ANATXACONTROL5_PWDWN_TX_R_MASK 0x0200 13647 #define TX1_ANATXACONTROL5_PWDWN_TX_R_ALIGN 0 13648 #define TX1_ANATXACONTROL5_PWDWN_TX_R_BITS 1 13649 #define TX1_ANATXACONTROL5_PWDWN_TX_R_SHIFT 9 13650 13651 /* Tx1 :: anaTxAControl5 :: tx_prbs_order_2 [08:08] */ 13652 #define TX1_ANATXACONTROL5_TX_PRBS_ORDER_2_MASK 0x0100 13653 #define TX1_ANATXACONTROL5_TX_PRBS_ORDER_2_ALIGN 0 13654 #define TX1_ANATXACONTROL5_TX_PRBS_ORDER_2_BITS 1 13655 #define TX1_ANATXACONTROL5_TX_PRBS_ORDER_2_SHIFT 8 13656 13657 /* Tx1 :: anaTxAControl5 :: ed8b10b_disable [07:07] */ 13658 #define TX1_ANATXACONTROL5_ED8B10B_DISABLE_MASK 0x0080 13659 #define TX1_ANATXACONTROL5_ED8B10B_DISABLE_ALIGN 0 13660 #define TX1_ANATXACONTROL5_ED8B10B_DISABLE_BITS 1 13661 #define TX1_ANATXACONTROL5_ED8B10B_DISABLE_SHIFT 7 13662 13663 /* Tx1 :: anaTxAControl5 :: tx_prbs_decouple_en [06:06] */ 13664 #define TX1_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_MASK 0x0040 13665 #define TX1_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_ALIGN 0 13666 #define TX1_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_BITS 1 13667 #define TX1_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_SHIFT 6 13668 13669 /* Tx1 :: anaTxAControl5 :: tx_prbs_en_decouple [05:05] */ 13670 #define TX1_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_MASK 0x0020 13671 #define TX1_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_ALIGN 0 13672 #define TX1_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_BITS 1 13673 #define TX1_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_SHIFT 5 13674 13675 /* Tx1 :: anaTxAControl5 :: tx_prbs_inv_decouple [04:04] */ 13676 #define TX1_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_MASK 0x0010 13677 #define TX1_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_ALIGN 0 13678 #define TX1_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_BITS 1 13679 #define TX1_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_SHIFT 4 13680 13681 /* Tx1 :: anaTxAControl5 :: tx_prbs_order_decouple [03:02] */ 13682 #define TX1_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_MASK 0x000c 13683 #define TX1_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_ALIGN 0 13684 #define TX1_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_BITS 2 13685 #define TX1_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_SHIFT 2 13686 13687 /* Tx1 :: anaTxAControl5 :: force_tx_sel_halfrate_val [01:01] */ 13688 #define TX1_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_MASK 0x0002 13689 #define TX1_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_ALIGN 0 13690 #define TX1_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_BITS 1 13691 #define TX1_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_SHIFT 1 13692 13693 /* Tx1 :: anaTxAControl5 :: force_tx_sel_halfrate [00:00] */ 13694 #define TX1_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_MASK 0x0001 13695 #define TX1_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_ALIGN 0 13696 #define TX1_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_BITS 1 13697 #define TX1_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_SHIFT 0 13698 13699 13700 /**************************************************************************** 13701 * Tx1 :: anaTxAControl6 13702 */ 13703 /* Tx1 :: anaTxAControl6 :: reserved0 [15:06] */ 13704 #define TX1_ANATXACONTROL6_RESERVED0_MASK 0xffc0 13705 #define TX1_ANATXACONTROL6_RESERVED0_ALIGN 0 13706 #define TX1_ANATXACONTROL6_RESERVED0_BITS 10 13707 #define TX1_ANATXACONTROL6_RESERVED0_SHIFT 6 13708 13709 /* Tx1 :: anaTxAControl6 :: sel_8b10b_default_cya [05:05] */ 13710 #define TX1_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_MASK 0x0020 13711 #define TX1_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_ALIGN 0 13712 #define TX1_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_BITS 1 13713 #define TX1_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_SHIFT 5 13714 13715 /* Tx1 :: anaTxAControl6 :: ckgate_int_sel_div1_1p5_2_2p5 [04:04] */ 13716 #define TX1_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_MASK 0x0010 13717 #define TX1_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_ALIGN 0 13718 #define TX1_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_BITS 1 13719 #define TX1_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_SHIFT 4 13720 13721 /* Tx1 :: anaTxAControl6 :: gloop_r [03:03] */ 13722 #define TX1_ANATXACONTROL6_GLOOP_R_MASK 0x0008 13723 #define TX1_ANATXACONTROL6_GLOOP_R_ALIGN 0 13724 #define TX1_ANATXACONTROL6_GLOOP_R_BITS 1 13725 #define TX1_ANATXACONTROL6_GLOOP_R_SHIFT 3 13726 13727 /* Tx1 :: anaTxAControl6 :: rloop_r [02:02] */ 13728 #define TX1_ANATXACONTROL6_RLOOP_R_MASK 0x0004 13729 #define TX1_ANATXACONTROL6_RLOOP_R_ALIGN 0 13730 #define TX1_ANATXACONTROL6_RLOOP_R_BITS 1 13731 #define TX1_ANATXACONTROL6_RLOOP_R_SHIFT 2 13732 13733 /* Tx1 :: anaTxAControl6 :: ckgate_ext_sel [01:01] */ 13734 #define TX1_ANATXACONTROL6_CKGATE_EXT_SEL_MASK 0x0002 13735 #define TX1_ANATXACONTROL6_CKGATE_EXT_SEL_ALIGN 0 13736 #define TX1_ANATXACONTROL6_CKGATE_EXT_SEL_BITS 1 13737 #define TX1_ANATXACONTROL6_CKGATE_EXT_SEL_SHIFT 1 13738 13739 /* Tx1 :: anaTxAControl6 :: disable_tx_r [00:00] */ 13740 #define TX1_ANATXACONTROL6_DISABLE_TX_R_MASK 0x0001 13741 #define TX1_ANATXACONTROL6_DISABLE_TX_R_ALIGN 0 13742 #define TX1_ANATXACONTROL6_DISABLE_TX_R_BITS 1 13743 #define TX1_ANATXACONTROL6_DISABLE_TX_R_SHIFT 0 13744 13745 13746 /**************************************************************************** 13747 * Warpcore_USER_Tx2 13748 */ 13749 /**************************************************************************** 13750 * Tx2 :: anaTxAStatus0 13751 */ 13752 /* union - case txStatusSelect_equals_0 [15:00] */ 13753 /* Tx2 :: anaTxAStatus0 :: reserved0 [15:11] */ 13754 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_MASK 0xf800 13755 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_ALIGN 0 13756 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_BITS 5 13757 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_SHIFT 11 13758 13759 /* Tx2 :: anaTxAStatus0 :: oscdr_mode_indch_tx [10:07] */ 13760 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_MASK 0x0780 13761 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_ALIGN 0 13762 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_BITS 4 13763 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_SHIFT 7 13764 13765 /* Tx2 :: anaTxAStatus0 :: txdisable_ln [06:06] */ 13766 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_MASK 0x0040 13767 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_ALIGN 0 13768 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_BITS 1 13769 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_SHIFT 6 13770 13771 /* Tx2 :: anaTxAStatus0 :: txferr_stky [05:05] */ 13772 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_MASK 0x0020 13773 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_ALIGN 0 13774 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_BITS 1 13775 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_SHIFT 5 13776 13777 /* Tx2 :: anaTxAStatus0 :: tbi_mode [04:04] */ 13778 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_MASK 0x0010 13779 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_ALIGN 0 13780 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_BITS 1 13781 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_SHIFT 4 13782 13783 /* Tx2 :: anaTxAStatus0 :: tx_reset [03:03] */ 13784 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_MASK 0x0008 13785 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_ALIGN 0 13786 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_BITS 1 13787 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_SHIFT 3 13788 13789 /* Tx2 :: anaTxAStatus0 :: tx_pwrdn [02:02] */ 13790 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_MASK 0x0004 13791 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_ALIGN 0 13792 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_BITS 1 13793 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_SHIFT 2 13794 13795 /* Tx2 :: anaTxAStatus0 :: rltxferr_stky [01:01] */ 13796 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_MASK 0x0002 13797 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_ALIGN 0 13798 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_BITS 1 13799 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_SHIFT 1 13800 13801 /* Tx2 :: anaTxAStatus0 :: txpll_lock [00:00] */ 13802 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_MASK 0x0001 13803 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_ALIGN 0 13804 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_BITS 1 13805 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_SHIFT 0 13806 13807 13808 /* union - case txStatusSelect_equals_1 [15:00] */ 13809 /* Tx2 :: anaTxAStatus0 :: tx_sel_halfrate [15:15] */ 13810 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_MASK 0x8000 13811 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_ALIGN 0 13812 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_BITS 1 13813 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_SHIFT 15 13814 13815 /* Tx2 :: anaTxAStatus0 :: tx_fir_tap_post [14:10] */ 13816 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_MASK 0x7c00 13817 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_ALIGN 0 13818 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_BITS 5 13819 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_SHIFT 10 13820 13821 /* Tx2 :: anaTxAStatus0 :: tx_fir_tap_main [09:04] */ 13822 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_MASK 0x03f0 13823 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_ALIGN 0 13824 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_BITS 6 13825 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_SHIFT 4 13826 13827 /* Tx2 :: anaTxAStatus0 :: tx_fir_tap_pre [03:00] */ 13828 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_MASK 0x000f 13829 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_ALIGN 0 13830 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_BITS 4 13831 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_SHIFT 0 13832 13833 13834 13835 /**************************************************************************** 13836 * Tx2 :: anaTxAControl0 13837 */ 13838 /* Tx2 :: anaTxAControl0 :: reserved0 [15:15] */ 13839 #define TX2_ANATXACONTROL0_RESERVED0_MASK 0x8000 13840 #define TX2_ANATXACONTROL0_RESERVED0_ALIGN 0 13841 #define TX2_ANATXACONTROL0_RESERVED0_BITS 1 13842 #define TX2_ANATXACONTROL0_RESERVED0_SHIFT 15 13843 13844 /* Tx2 :: anaTxAControl0 :: force_txclk [14:14] */ 13845 #define TX2_ANATXACONTROL0_FORCE_TXCLK_MASK 0x4000 13846 #define TX2_ANATXACONTROL0_FORCE_TXCLK_ALIGN 0 13847 #define TX2_ANATXACONTROL0_FORCE_TXCLK_BITS 1 13848 #define TX2_ANATXACONTROL0_FORCE_TXCLK_SHIFT 14 13849 13850 /* Tx2 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */ 13851 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_MASK 0x2000 13852 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN 0 13853 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_BITS 1 13854 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT 13 13855 13856 /* Tx2 :: anaTxAControl0 :: force_ext_frst_SM [12:12] */ 13857 #define TX2_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK 0x1000 13858 #define TX2_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN 0 13859 #define TX2_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS 1 13860 #define TX2_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT 12 13861 13862 /* Tx2 :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */ 13863 #define TX2_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK 0x0800 13864 #define TX2_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN 0 13865 #define TX2_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS 1 13866 #define TX2_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT 11 13867 13868 /* Tx2 :: anaTxAControl0 :: txck_dme_en_SM [10:10] */ 13869 #define TX2_ANATXACONTROL0_TXCK_DME_EN_SM_MASK 0x0400 13870 #define TX2_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN 0 13871 #define TX2_ANATXACONTROL0_TXCK_DME_EN_SM_BITS 1 13872 #define TX2_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT 10 13873 13874 /* Tx2 :: anaTxAControl0 :: gloopOutDis [09:09] */ 13875 #define TX2_ANATXACONTROL0_GLOOPOUTDIS_MASK 0x0200 13876 #define TX2_ANATXACONTROL0_GLOOPOUTDIS_ALIGN 0 13877 #define TX2_ANATXACONTROL0_GLOOPOUTDIS_BITS 1 13878 #define TX2_ANATXACONTROL0_GLOOPOUTDIS_SHIFT 9 13879 13880 /* Tx2 :: anaTxAControl0 :: prbs_en [08:08] */ 13881 #define TX2_ANATXACONTROL0_PRBS_EN_MASK 0x0100 13882 #define TX2_ANATXACONTROL0_PRBS_EN_ALIGN 0 13883 #define TX2_ANATXACONTROL0_PRBS_EN_BITS 1 13884 #define TX2_ANATXACONTROL0_PRBS_EN_SHIFT 8 13885 13886 /* Tx2 :: anaTxAControl0 :: pckt_en [07:07] */ 13887 #define TX2_ANATXACONTROL0_PCKT_EN_MASK 0x0080 13888 #define TX2_ANATXACONTROL0_PCKT_EN_ALIGN 0 13889 #define TX2_ANATXACONTROL0_PCKT_EN_BITS 1 13890 #define TX2_ANATXACONTROL0_PCKT_EN_SHIFT 7 13891 13892 /* Tx2 :: anaTxAControl0 :: pckt_strt [06:06] */ 13893 #define TX2_ANATXACONTROL0_PCKT_STRT_MASK 0x0040 13894 #define TX2_ANATXACONTROL0_PCKT_STRT_ALIGN 0 13895 #define TX2_ANATXACONTROL0_PCKT_STRT_BITS 1 13896 #define TX2_ANATXACONTROL0_PCKT_STRT_SHIFT 6 13897 13898 /* Tx2 :: anaTxAControl0 :: txpol_flip [05:05] */ 13899 #define TX2_ANATXACONTROL0_TXPOL_FLIP_MASK 0x0020 13900 #define TX2_ANATXACONTROL0_TXPOL_FLIP_ALIGN 0 13901 #define TX2_ANATXACONTROL0_TXPOL_FLIP_BITS 1 13902 #define TX2_ANATXACONTROL0_TXPOL_FLIP_SHIFT 5 13903 13904 /* Tx2 :: anaTxAControl0 :: rtbi_flip [04:04] */ 13905 #define TX2_ANATXACONTROL0_RTBI_FLIP_MASK 0x0010 13906 #define TX2_ANATXACONTROL0_RTBI_FLIP_ALIGN 0 13907 #define TX2_ANATXACONTROL0_RTBI_FLIP_BITS 1 13908 #define TX2_ANATXACONTROL0_RTBI_FLIP_SHIFT 4 13909 13910 /* Tx2 :: anaTxAControl0 :: eden_r [03:03] */ 13911 #define TX2_ANATXACONTROL0_EDEN_R_MASK 0x0008 13912 #define TX2_ANATXACONTROL0_EDEN_R_ALIGN 0 13913 #define TX2_ANATXACONTROL0_EDEN_R_BITS 1 13914 #define TX2_ANATXACONTROL0_EDEN_R_SHIFT 3 13915 13916 /* Tx2 :: anaTxAControl0 :: eden_force_r [02:02] */ 13917 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_MASK 0x0004 13918 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_ALIGN 0 13919 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_BITS 1 13920 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_SHIFT 2 13921 13922 /* Tx2 :: anaTxAControl0 :: txpat_en [01:01] */ 13923 #define TX2_ANATXACONTROL0_TXPAT_EN_MASK 0x0002 13924 #define TX2_ANATXACONTROL0_TXPAT_EN_ALIGN 0 13925 #define TX2_ANATXACONTROL0_TXPAT_EN_BITS 1 13926 #define TX2_ANATXACONTROL0_TXPAT_EN_SHIFT 1 13927 13928 /* Tx2 :: anaTxAControl0 :: tx_mdata_en [00:00] */ 13929 #define TX2_ANATXACONTROL0_TX_MDATA_EN_MASK 0x0001 13930 #define TX2_ANATXACONTROL0_TX_MDATA_EN_ALIGN 0 13931 #define TX2_ANATXACONTROL0_TX_MDATA_EN_BITS 1 13932 #define TX2_ANATXACONTROL0_TX_MDATA_EN_SHIFT 0 13933 13934 13935 /**************************************************************************** 13936 * Tx2 :: anaTxmdata0 13937 */ 13938 /* Tx2 :: anaTxmdata0 :: txTestMuxSel [15:13] */ 13939 #define TX2_ANATXMDATA0_TXTESTMUXSEL_MASK 0xe000 13940 #define TX2_ANATXMDATA0_TXTESTMUXSEL_ALIGN 0 13941 #define TX2_ANATXMDATA0_TXTESTMUXSEL_BITS 3 13942 #define TX2_ANATXMDATA0_TXTESTMUXSEL_SHIFT 13 13943 13944 /* Tx2 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */ 13945 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_MASK 0x1c00 13946 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN 0 13947 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_BITS 3 13948 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT 10 13949 13950 /* Tx2 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */ 13951 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_MASK 0x03ff 13952 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN 0 13953 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_BITS 10 13954 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT 0 13955 13956 13957 /**************************************************************************** 13958 * Tx2 :: anaTxmdata1 13959 */ 13960 /* Tx2 :: anaTxmdata1 :: txStatusSelect [15:14] */ 13961 #define TX2_ANATXMDATA1_TXSTATUSSELECT_MASK 0xc000 13962 #define TX2_ANATXMDATA1_TXSTATUSSELECT_ALIGN 0 13963 #define TX2_ANATXMDATA1_TXSTATUSSELECT_BITS 2 13964 #define TX2_ANATXMDATA1_TXSTATUSSELECT_SHIFT 14 13965 13966 /* Tx2 :: anaTxmdata1 :: reserved0 [13:10] */ 13967 #define TX2_ANATXMDATA1_RESERVED0_MASK 0x3c00 13968 #define TX2_ANATXMDATA1_RESERVED0_ALIGN 0 13969 #define TX2_ANATXMDATA1_RESERVED0_BITS 4 13970 #define TX2_ANATXMDATA1_RESERVED0_SHIFT 10 13971 13972 /* Tx2 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */ 13973 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_MASK 0x03ff 13974 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN 0 13975 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_BITS 10 13976 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT 0 13977 13978 13979 /**************************************************************************** 13980 * Tx2 :: anaTxAStatus1 13981 */ 13982 /* Tx2 :: anaTxAStatus1 :: tx_id [15:14] */ 13983 #define TX2_ANATXASTATUS1_TX_ID_MASK 0xc000 13984 #define TX2_ANATXASTATUS1_TX_ID_ALIGN 0 13985 #define TX2_ANATXASTATUS1_TX_ID_BITS 2 13986 #define TX2_ANATXASTATUS1_TX_ID_SHIFT 14 13987 13988 /* Tx2 :: anaTxAStatus1 :: reserved0 [13:08] */ 13989 #define TX2_ANATXASTATUS1_RESERVED0_MASK 0x3f00 13990 #define TX2_ANATXASTATUS1_RESERVED0_ALIGN 0 13991 #define TX2_ANATXASTATUS1_RESERVED0_BITS 6 13992 #define TX2_ANATXASTATUS1_RESERVED0_SHIFT 8 13993 13994 /* Tx2 :: anaTxAStatus1 :: version_id [07:04] */ 13995 #define TX2_ANATXASTATUS1_VERSION_ID_MASK 0x00f0 13996 #define TX2_ANATXASTATUS1_VERSION_ID_ALIGN 0 13997 #define TX2_ANATXASTATUS1_VERSION_ID_BITS 4 13998 #define TX2_ANATXASTATUS1_VERSION_ID_SHIFT 4 13999 14000 /* Tx2 :: anaTxAStatus1 :: reserved1 [03:00] */ 14001 #define TX2_ANATXASTATUS1_RESERVED1_MASK 0x000f 14002 #define TX2_ANATXASTATUS1_RESERVED1_ALIGN 0 14003 #define TX2_ANATXASTATUS1_RESERVED1_BITS 4 14004 #define TX2_ANATXASTATUS1_RESERVED1_SHIFT 0 14005 14006 14007 /**************************************************************************** 14008 * Tx2 :: anaTxAControl1 14009 */ 14010 /* Tx2 :: anaTxAControl1 :: ipredrv [15:13] */ 14011 #define TX2_ANATXACONTROL1_IPREDRV_MASK 0xe000 14012 #define TX2_ANATXACONTROL1_IPREDRV_ALIGN 0 14013 #define TX2_ANATXACONTROL1_IPREDRV_BITS 3 14014 #define TX2_ANATXACONTROL1_IPREDRV_SHIFT 13 14015 14016 /* Tx2 :: anaTxAControl1 :: refl_tx [12:12] */ 14017 #define TX2_ANATXACONTROL1_REFL_TX_MASK 0x1000 14018 #define TX2_ANATXACONTROL1_REFL_TX_ALIGN 0 14019 #define TX2_ANATXACONTROL1_REFL_TX_BITS 1 14020 #define TX2_ANATXACONTROL1_REFL_TX_SHIFT 12 14021 14022 /* Tx2 :: anaTxAControl1 :: refh_tx [11:11] */ 14023 #define TX2_ANATXACONTROL1_REFH_TX_MASK 0x0800 14024 #define TX2_ANATXACONTROL1_REFH_TX_ALIGN 0 14025 #define TX2_ANATXACONTROL1_REFH_TX_BITS 1 14026 #define TX2_ANATXACONTROL1_REFH_TX_SHIFT 11 14027 14028 /* Tx2 :: anaTxAControl1 :: newbias_en [10:10] */ 14029 #define TX2_ANATXACONTROL1_NEWBIAS_EN_MASK 0x0400 14030 #define TX2_ANATXACONTROL1_NEWBIAS_EN_ALIGN 0 14031 #define TX2_ANATXACONTROL1_NEWBIAS_EN_BITS 1 14032 #define TX2_ANATXACONTROL1_NEWBIAS_EN_SHIFT 10 14033 14034 /* Tx2 :: anaTxAControl1 :: drivermode [09:09] */ 14035 #define TX2_ANATXACONTROL1_DRIVERMODE_MASK 0x0200 14036 #define TX2_ANATXACONTROL1_DRIVERMODE_ALIGN 0 14037 #define TX2_ANATXACONTROL1_DRIVERMODE_BITS 1 14038 #define TX2_ANATXACONTROL1_DRIVERMODE_SHIFT 9 14039 14040 /* Tx2 :: anaTxAControl1 :: vddr_bgb [08:08] */ 14041 #define TX2_ANATXACONTROL1_VDDR_BGB_MASK 0x0100 14042 #define TX2_ANATXACONTROL1_VDDR_BGB_ALIGN 0 14043 #define TX2_ANATXACONTROL1_VDDR_BGB_BITS 1 14044 #define TX2_ANATXACONTROL1_VDDR_BGB_SHIFT 8 14045 14046 /* Tx2 :: anaTxAControl1 :: ticksel [07:06] */ 14047 #define TX2_ANATXACONTROL1_TICKSEL_MASK 0x00c0 14048 #define TX2_ANATXACONTROL1_TICKSEL_ALIGN 0 14049 #define TX2_ANATXACONTROL1_TICKSEL_BITS 2 14050 #define TX2_ANATXACONTROL1_TICKSEL_SHIFT 6 14051 14052 /* Tx1 :: (for xenia only anaTxAControl1 :: ticksel [06:06] */ 14053 #define TX2_ANATXACONTROL1_ASYM_MODE_MASK 0x0040 14054 #define TX2_ANATXACONTROL1_ASYM_MODE_ALIGN 0 14055 #define TX2_ANATXACONTROL1_ASYM_MODE_BITS 1 14056 #define TX2_ANATXACONTROL1_ASYM_MODE_SHIFT 6 14057 14058 /* Tx2 :: anaTxAControl1 :: driver_vcm [05:04] */ 14059 #define TX2_ANATXACONTROL1_DRIVER_VCM_MASK 0x0030 14060 #define TX2_ANATXACONTROL1_DRIVER_VCM_ALIGN 0 14061 #define TX2_ANATXACONTROL1_DRIVER_VCM_BITS 2 14062 #define TX2_ANATXACONTROL1_DRIVER_VCM_SHIFT 4 14063 14064 /* Tx2 :: anaTxAControl1 :: amp_ctrl [03:03] */ 14065 #define TX2_ANATXACONTROL1_AMP_CTRL_MASK 0x0008 14066 #define TX2_ANATXACONTROL1_AMP_CTRL_ALIGN 0 14067 #define TX2_ANATXACONTROL1_AMP_CTRL_BITS 1 14068 #define TX2_ANATXACONTROL1_AMP_CTRL_SHIFT 3 14069 14070 /* Tx2 :: anaTxAControl1 :: ifullspd [02:00] */ 14071 #define TX2_ANATXACONTROL1_IFULLSPD_MASK 0x0007 14072 #define TX2_ANATXACONTROL1_IFULLSPD_ALIGN 0 14073 #define TX2_ANATXACONTROL1_IFULLSPD_BITS 3 14074 #define TX2_ANATXACONTROL1_IFULLSPD_SHIFT 0 14075 14076 14077 /**************************************************************************** 14078 * Tx2 :: anaTxAControl2 14079 */ 14080 /* Tx2 :: anaTxAControl2 :: icbuf1t [15:14] */ 14081 #define TX2_ANATXACONTROL2_ICBUF1T_MASK 0xc000 14082 #define TX2_ANATXACONTROL2_ICBUF1T_ALIGN 0 14083 #define TX2_ANATXACONTROL2_ICBUF1T_BITS 2 14084 #define TX2_ANATXACONTROL2_ICBUF1T_SHIFT 14 14085 14086 /* Tx2 :: anaTxAControl2 :: icbuf2t [13:11] */ 14087 #define TX2_ANATXACONTROL2_ICBUF2T_MASK 0x3800 14088 #define TX2_ANATXACONTROL2_ICBUF2T_ALIGN 0 14089 #define TX2_ANATXACONTROL2_ICBUF2T_BITS 3 14090 #define TX2_ANATXACONTROL2_ICBUF2T_SHIFT 11 14091 14092 /* Tx2 :: anaTxAControl2 :: imin_predrv [10:10] */ 14093 #define TX2_ANATXACONTROL2_IMIN_PREDRV_MASK 0x0400 14094 #define TX2_ANATXACONTROL2_IMIN_PREDRV_ALIGN 0 14095 #define TX2_ANATXACONTROL2_IMIN_PREDRV_BITS 1 14096 #define TX2_ANATXACONTROL2_IMIN_PREDRV_SHIFT 10 14097 14098 /* Tx2 :: anaTxAControl2 :: imax_predrv [09:09] */ 14099 #define TX2_ANATXACONTROL2_IMAX_PREDRV_MASK 0x0200 14100 #define TX2_ANATXACONTROL2_IMAX_PREDRV_ALIGN 0 14101 #define TX2_ANATXACONTROL2_IMAX_PREDRV_BITS 1 14102 #define TX2_ANATXACONTROL2_IMAX_PREDRV_SHIFT 9 14103 14104 /* Tx2 :: anaTxAControl2 :: imode_predrv [08:08] */ 14105 #define TX2_ANATXACONTROL2_IMODE_PREDRV_MASK 0x0100 14106 #define TX2_ANATXACONTROL2_IMODE_PREDRV_ALIGN 0 14107 #define TX2_ANATXACONTROL2_IMODE_PREDRV_BITS 1 14108 #define TX2_ANATXACONTROL2_IMODE_PREDRV_SHIFT 8 14109 14110 /* Tx2 :: anaTxAControl2 :: i21mux [07:05] */ 14111 #define TX2_ANATXACONTROL2_I21MUX_MASK 0x00e0 14112 #define TX2_ANATXACONTROL2_I21MUX_ALIGN 0 14113 #define TX2_ANATXACONTROL2_I21MUX_BITS 3 14114 #define TX2_ANATXACONTROL2_I21MUX_SHIFT 5 14115 14116 /* Tx2 :: anaTxAControl2 :: imin_drvr [04:04] */ 14117 #define TX2_ANATXACONTROL2_IMIN_DRVR_MASK 0x0010 14118 #define TX2_ANATXACONTROL2_IMIN_DRVR_ALIGN 0 14119 #define TX2_ANATXACONTROL2_IMIN_DRVR_BITS 1 14120 #define TX2_ANATXACONTROL2_IMIN_DRVR_SHIFT 4 14121 14122 /* Tx2 :: anaTxAControl2 :: imax_drvr [03:03] */ 14123 #define TX2_ANATXACONTROL2_IMAX_DRVR_MASK 0x0008 14124 #define TX2_ANATXACONTROL2_IMAX_DRVR_ALIGN 0 14125 #define TX2_ANATXACONTROL2_IMAX_DRVR_BITS 1 14126 #define TX2_ANATXACONTROL2_IMAX_DRVR_SHIFT 3 14127 14128 /* Tx2 :: anaTxAControl2 :: imode_drvr [02:02] */ 14129 #define TX2_ANATXACONTROL2_IMODE_DRVR_MASK 0x0004 14130 #define TX2_ANATXACONTROL2_IMODE_DRVR_ALIGN 0 14131 #define TX2_ANATXACONTROL2_IMODE_DRVR_BITS 1 14132 #define TX2_ANATXACONTROL2_IMODE_DRVR_SHIFT 2 14133 14134 /* Tx2 :: anaTxAControl2 :: reserved0 [01:00] */ 14135 #define TX2_ANATXACONTROL2_RESERVED0_MASK 0x0003 14136 #define TX2_ANATXACONTROL2_RESERVED0_ALIGN 0 14137 #define TX2_ANATXACONTROL2_RESERVED0_BITS 2 14138 #define TX2_ANATXACONTROL2_RESERVED0_SHIFT 0 14139 14140 14141 /**************************************************************************** 14142 * Tx2 :: Tx_Driver 14143 */ 14144 /* Tx2 :: Tx_Driver :: ElecIdle [15:15] */ 14145 #define TX2_TX_DRIVER_ELECIDLE_MASK 0x8000 14146 #define TX2_TX_DRIVER_ELECIDLE_ALIGN 0 14147 #define TX2_TX_DRIVER_ELECIDLE_BITS 1 14148 #define TX2_TX_DRIVER_ELECIDLE_SHIFT 15 14149 14150 /* Tx2 :: Tx_Driver :: post2_coeff [14:12] */ 14151 #define TX2_TX_DRIVER_POST2_COEFF_MASK 0x7000 14152 #define TX2_TX_DRIVER_POST2_COEFF_ALIGN 0 14153 #define TX2_TX_DRIVER_POST2_COEFF_BITS 3 14154 #define TX2_TX_DRIVER_POST2_COEFF_SHIFT 12 14155 14156 /* Tx2 :: Tx_Driver :: Idriver [11:08] */ 14157 #define TX2_TX_DRIVER_IDRIVER_MASK 0x0f00 14158 #define TX2_TX_DRIVER_IDRIVER_ALIGN 0 14159 #define TX2_TX_DRIVER_IDRIVER_BITS 4 14160 #define TX2_TX_DRIVER_IDRIVER_SHIFT 8 14161 #define TX2_TX_DRIVER_IDRIVER_v680mV 0 14162 #define TX2_TX_DRIVER_IDRIVER_v730mV 1 14163 #define TX2_TX_DRIVER_IDRIVER_v780mV 2 14164 #define TX2_TX_DRIVER_IDRIVER_v830mV 3 14165 #define TX2_TX_DRIVER_IDRIVER_v880mV 4 14166 #define TX2_TX_DRIVER_IDRIVER_v930mV 5 14167 #define TX2_TX_DRIVER_IDRIVER_v980mV 6 14168 #define TX2_TX_DRIVER_IDRIVER_v1010mV 7 14169 #define TX2_TX_DRIVER_IDRIVER_v1040mV 8 14170 #define TX2_TX_DRIVER_IDRIVER_v1060mV 9 14171 #define TX2_TX_DRIVER_IDRIVER_v1070mV 10 14172 #define TX2_TX_DRIVER_IDRIVER_v1080mV 11 14173 #define TX2_TX_DRIVER_IDRIVER_v1085mV 12 14174 #define TX2_TX_DRIVER_IDRIVER_v1090mV 13 14175 #define TX2_TX_DRIVER_IDRIVER_v1095mV 14 14176 #define TX2_TX_DRIVER_IDRIVER_v1100mV 15 14177 14178 /* Tx2 :: Tx_Driver :: Ipredriver [07:04] */ 14179 #define TX2_TX_DRIVER_IPREDRIVER_MASK 0x00f0 14180 #define TX2_TX_DRIVER_IPREDRIVER_ALIGN 0 14181 #define TX2_TX_DRIVER_IPREDRIVER_BITS 4 14182 #define TX2_TX_DRIVER_IPREDRIVER_SHIFT 4 14183 14184 /* Tx2 :: Tx_Driver :: ifir [03:01] */ 14185 #define TX2_TX_DRIVER_IFIR_MASK 0x000e 14186 #define TX2_TX_DRIVER_IFIR_ALIGN 0 14187 #define TX2_TX_DRIVER_IFIR_BITS 3 14188 #define TX2_TX_DRIVER_IFIR_SHIFT 1 14189 14190 /* Tx2 :: Tx_Driver :: icbuf1t2 [00:00] */ 14191 #define TX2_TX_DRIVER_ICBUF1T2_MASK 0x0001 14192 #define TX2_TX_DRIVER_ICBUF1T2_ALIGN 0 14193 #define TX2_TX_DRIVER_ICBUF1T2_BITS 1 14194 #define TX2_TX_DRIVER_ICBUF1T2_SHIFT 0 14195 14196 14197 /**************************************************************************** 14198 * Tx2 :: anaTxAControl5 14199 */ 14200 /* Tx2 :: anaTxAControl5 :: reserved0 [15:15] */ 14201 #define TX2_ANATXACONTROL5_RESERVED0_MASK 0x8000 14202 #define TX2_ANATXACONTROL5_RESERVED0_ALIGN 0 14203 #define TX2_ANATXACONTROL5_RESERVED0_BITS 1 14204 #define TX2_ANATXACONTROL5_RESERVED0_SHIFT 15 14205 14206 /* Tx2 :: anaTxAControl5 :: tx_prbs_w_val [14:14] */ 14207 #define TX2_ANATXACONTROL5_TX_PRBS_W_VAL_MASK 0x4000 14208 #define TX2_ANATXACONTROL5_TX_PRBS_W_VAL_ALIGN 0 14209 #define TX2_ANATXACONTROL5_TX_PRBS_W_VAL_BITS 1 14210 #define TX2_ANATXACONTROL5_TX_PRBS_W_VAL_SHIFT 14 14211 14212 /* Tx2 :: anaTxAControl5 :: tx_prbs_w_force [13:13] */ 14213 #define TX2_ANATXACONTROL5_TX_PRBS_W_FORCE_MASK 0x2000 14214 #define TX2_ANATXACONTROL5_TX_PRBS_W_FORCE_ALIGN 0 14215 #define TX2_ANATXACONTROL5_TX_PRBS_W_FORCE_BITS 1 14216 #define TX2_ANATXACONTROL5_TX_PRBS_W_FORCE_SHIFT 13 14217 14218 /* Tx2 :: anaTxAControl5 :: tx_prbs_bswap [12:12] */ 14219 #define TX2_ANATXACONTROL5_TX_PRBS_BSWAP_MASK 0x1000 14220 #define TX2_ANATXACONTROL5_TX_PRBS_BSWAP_ALIGN 0 14221 #define TX2_ANATXACONTROL5_TX_PRBS_BSWAP_BITS 1 14222 #define TX2_ANATXACONTROL5_TX_PRBS_BSWAP_SHIFT 12 14223 14224 /* Tx2 :: anaTxAControl5 :: tx_bitswap [11:11] */ 14225 #define TX2_ANATXACONTROL5_TX_BITSWAP_MASK 0x0800 14226 #define TX2_ANATXACONTROL5_TX_BITSWAP_ALIGN 0 14227 #define TX2_ANATXACONTROL5_TX_BITSWAP_BITS 1 14228 #define TX2_ANATXACONTROL5_TX_BITSWAP_SHIFT 11 14229 14230 /* Tx2 :: anaTxAControl5 :: rst_tx_r [10:10] */ 14231 #define TX2_ANATXACONTROL5_RST_TX_R_MASK 0x0400 14232 #define TX2_ANATXACONTROL5_RST_TX_R_ALIGN 0 14233 #define TX2_ANATXACONTROL5_RST_TX_R_BITS 1 14234 #define TX2_ANATXACONTROL5_RST_TX_R_SHIFT 10 14235 14236 /* Tx2 :: anaTxAControl5 :: pwdwn_tx_r [09:09] */ 14237 #define TX2_ANATXACONTROL5_PWDWN_TX_R_MASK 0x0200 14238 #define TX2_ANATXACONTROL5_PWDWN_TX_R_ALIGN 0 14239 #define TX2_ANATXACONTROL5_PWDWN_TX_R_BITS 1 14240 #define TX2_ANATXACONTROL5_PWDWN_TX_R_SHIFT 9 14241 14242 /* Tx2 :: anaTxAControl5 :: tx_prbs_order_2 [08:08] */ 14243 #define TX2_ANATXACONTROL5_TX_PRBS_ORDER_2_MASK 0x0100 14244 #define TX2_ANATXACONTROL5_TX_PRBS_ORDER_2_ALIGN 0 14245 #define TX2_ANATXACONTROL5_TX_PRBS_ORDER_2_BITS 1 14246 #define TX2_ANATXACONTROL5_TX_PRBS_ORDER_2_SHIFT 8 14247 14248 /* Tx2 :: anaTxAControl5 :: ed8b10b_disable [07:07] */ 14249 #define TX2_ANATXACONTROL5_ED8B10B_DISABLE_MASK 0x0080 14250 #define TX2_ANATXACONTROL5_ED8B10B_DISABLE_ALIGN 0 14251 #define TX2_ANATXACONTROL5_ED8B10B_DISABLE_BITS 1 14252 #define TX2_ANATXACONTROL5_ED8B10B_DISABLE_SHIFT 7 14253 14254 /* Tx2 :: anaTxAControl5 :: tx_prbs_decouple_en [06:06] */ 14255 #define TX2_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_MASK 0x0040 14256 #define TX2_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_ALIGN 0 14257 #define TX2_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_BITS 1 14258 #define TX2_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_SHIFT 6 14259 14260 /* Tx2 :: anaTxAControl5 :: tx_prbs_en_decouple [05:05] */ 14261 #define TX2_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_MASK 0x0020 14262 #define TX2_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_ALIGN 0 14263 #define TX2_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_BITS 1 14264 #define TX2_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_SHIFT 5 14265 14266 /* Tx2 :: anaTxAControl5 :: tx_prbs_inv_decouple [04:04] */ 14267 #define TX2_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_MASK 0x0010 14268 #define TX2_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_ALIGN 0 14269 #define TX2_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_BITS 1 14270 #define TX2_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_SHIFT 4 14271 14272 /* Tx2 :: anaTxAControl5 :: tx_prbs_order_decouple [03:02] */ 14273 #define TX2_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_MASK 0x000c 14274 #define TX2_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_ALIGN 0 14275 #define TX2_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_BITS 2 14276 #define TX2_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_SHIFT 2 14277 14278 /* Tx2 :: anaTxAControl5 :: force_tx_sel_halfrate_val [01:01] */ 14279 #define TX2_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_MASK 0x0002 14280 #define TX2_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_ALIGN 0 14281 #define TX2_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_BITS 1 14282 #define TX2_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_SHIFT 1 14283 14284 /* Tx2 :: anaTxAControl5 :: force_tx_sel_halfrate [00:00] */ 14285 #define TX2_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_MASK 0x0001 14286 #define TX2_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_ALIGN 0 14287 #define TX2_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_BITS 1 14288 #define TX2_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_SHIFT 0 14289 14290 14291 /**************************************************************************** 14292 * Tx2 :: anaTxAControl6 14293 */ 14294 /* Tx2 :: anaTxAControl6 :: reserved0 [15:06] */ 14295 #define TX2_ANATXACONTROL6_RESERVED0_MASK 0xffc0 14296 #define TX2_ANATXACONTROL6_RESERVED0_ALIGN 0 14297 #define TX2_ANATXACONTROL6_RESERVED0_BITS 10 14298 #define TX2_ANATXACONTROL6_RESERVED0_SHIFT 6 14299 14300 /* Tx2 :: anaTxAControl6 :: sel_8b10b_default_cya [05:05] */ 14301 #define TX2_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_MASK 0x0020 14302 #define TX2_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_ALIGN 0 14303 #define TX2_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_BITS 1 14304 #define TX2_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_SHIFT 5 14305 14306 /* Tx2 :: anaTxAControl6 :: ckgate_int_sel_div1_1p5_2_2p5 [04:04] */ 14307 #define TX2_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_MASK 0x0010 14308 #define TX2_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_ALIGN 0 14309 #define TX2_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_BITS 1 14310 #define TX2_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_SHIFT 4 14311 14312 /* Tx2 :: anaTxAControl6 :: gloop_r [03:03] */ 14313 #define TX2_ANATXACONTROL6_GLOOP_R_MASK 0x0008 14314 #define TX2_ANATXACONTROL6_GLOOP_R_ALIGN 0 14315 #define TX2_ANATXACONTROL6_GLOOP_R_BITS 1 14316 #define TX2_ANATXACONTROL6_GLOOP_R_SHIFT 3 14317 14318 /* Tx2 :: anaTxAControl6 :: rloop_r [02:02] */ 14319 #define TX2_ANATXACONTROL6_RLOOP_R_MASK 0x0004 14320 #define TX2_ANATXACONTROL6_RLOOP_R_ALIGN 0 14321 #define TX2_ANATXACONTROL6_RLOOP_R_BITS 1 14322 #define TX2_ANATXACONTROL6_RLOOP_R_SHIFT 2 14323 14324 /* Tx2 :: anaTxAControl6 :: ckgate_ext_sel [01:01] */ 14325 #define TX2_ANATXACONTROL6_CKGATE_EXT_SEL_MASK 0x0002 14326 #define TX2_ANATXACONTROL6_CKGATE_EXT_SEL_ALIGN 0 14327 #define TX2_ANATXACONTROL6_CKGATE_EXT_SEL_BITS 1 14328 #define TX2_ANATXACONTROL6_CKGATE_EXT_SEL_SHIFT 1 14329 14330 /* Tx2 :: anaTxAControl6 :: disable_tx_r [00:00] */ 14331 #define TX2_ANATXACONTROL6_DISABLE_TX_R_MASK 0x0001 14332 #define TX2_ANATXACONTROL6_DISABLE_TX_R_ALIGN 0 14333 #define TX2_ANATXACONTROL6_DISABLE_TX_R_BITS 1 14334 #define TX2_ANATXACONTROL6_DISABLE_TX_R_SHIFT 0 14335 14336 14337 /**************************************************************************** 14338 * Warpcore_USER_Tx3 14339 */ 14340 /**************************************************************************** 14341 * Tx3 :: anaTxAStatus0 14342 */ 14343 /* union - case txStatusSelect_equals_0 [15:00] */ 14344 /* Tx3 :: anaTxAStatus0 :: reserved0 [15:11] */ 14345 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_MASK 0xf800 14346 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_ALIGN 0 14347 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_BITS 5 14348 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_SHIFT 11 14349 14350 /* Tx3 :: anaTxAStatus0 :: oscdr_mode_indch_tx [10:07] */ 14351 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_MASK 0x0780 14352 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_ALIGN 0 14353 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_BITS 4 14354 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_SHIFT 7 14355 14356 /* Tx3 :: anaTxAStatus0 :: txdisable_ln [06:06] */ 14357 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_MASK 0x0040 14358 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_ALIGN 0 14359 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_BITS 1 14360 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_SHIFT 6 14361 14362 /* Tx3 :: anaTxAStatus0 :: txferr_stky [05:05] */ 14363 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_MASK 0x0020 14364 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_ALIGN 0 14365 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_BITS 1 14366 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_SHIFT 5 14367 14368 /* Tx3 :: anaTxAStatus0 :: tbi_mode [04:04] */ 14369 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_MASK 0x0010 14370 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_ALIGN 0 14371 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_BITS 1 14372 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_SHIFT 4 14373 14374 /* Tx3 :: anaTxAStatus0 :: tx_reset [03:03] */ 14375 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_MASK 0x0008 14376 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_ALIGN 0 14377 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_BITS 1 14378 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_SHIFT 3 14379 14380 /* Tx3 :: anaTxAStatus0 :: tx_pwrdn [02:02] */ 14381 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_MASK 0x0004 14382 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_ALIGN 0 14383 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_BITS 1 14384 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_SHIFT 2 14385 14386 /* Tx3 :: anaTxAStatus0 :: rltxferr_stky [01:01] */ 14387 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_MASK 0x0002 14388 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_ALIGN 0 14389 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_BITS 1 14390 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_SHIFT 1 14391 14392 /* Tx3 :: anaTxAStatus0 :: txpll_lock [00:00] */ 14393 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_MASK 0x0001 14394 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_ALIGN 0 14395 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_BITS 1 14396 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_SHIFT 0 14397 14398 14399 /* union - case txStatusSelect_equals_1 [15:00] */ 14400 /* Tx3 :: anaTxAStatus0 :: tx_sel_halfrate [15:15] */ 14401 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_MASK 0x8000 14402 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_ALIGN 0 14403 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_BITS 1 14404 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_SHIFT 15 14405 14406 /* Tx3 :: anaTxAStatus0 :: tx_fir_tap_post [14:10] */ 14407 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_MASK 0x7c00 14408 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_ALIGN 0 14409 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_BITS 5 14410 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_SHIFT 10 14411 14412 /* Tx3 :: anaTxAStatus0 :: tx_fir_tap_main [09:04] */ 14413 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_MASK 0x03f0 14414 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_ALIGN 0 14415 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_BITS 6 14416 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_SHIFT 4 14417 14418 /* Tx3 :: anaTxAStatus0 :: tx_fir_tap_pre [03:00] */ 14419 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_MASK 0x000f 14420 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_ALIGN 0 14421 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_BITS 4 14422 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_SHIFT 0 14423 14424 14425 14426 /**************************************************************************** 14427 * Tx3 :: anaTxAControl0 14428 */ 14429 /* Tx3 :: anaTxAControl0 :: reserved0 [15:15] */ 14430 #define TX3_ANATXACONTROL0_RESERVED0_MASK 0x8000 14431 #define TX3_ANATXACONTROL0_RESERVED0_ALIGN 0 14432 #define TX3_ANATXACONTROL0_RESERVED0_BITS 1 14433 #define TX3_ANATXACONTROL0_RESERVED0_SHIFT 15 14434 14435 /* Tx3 :: anaTxAControl0 :: force_txclk [14:14] */ 14436 #define TX3_ANATXACONTROL0_FORCE_TXCLK_MASK 0x4000 14437 #define TX3_ANATXACONTROL0_FORCE_TXCLK_ALIGN 0 14438 #define TX3_ANATXACONTROL0_FORCE_TXCLK_BITS 1 14439 #define TX3_ANATXACONTROL0_FORCE_TXCLK_SHIFT 14 14440 14441 /* Tx3 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */ 14442 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_MASK 0x2000 14443 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN 0 14444 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_BITS 1 14445 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT 13 14446 14447 /* Tx3 :: anaTxAControl0 :: force_ext_frst_SM [12:12] */ 14448 #define TX3_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK 0x1000 14449 #define TX3_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN 0 14450 #define TX3_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS 1 14451 #define TX3_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT 12 14452 14453 /* Tx3 :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */ 14454 #define TX3_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK 0x0800 14455 #define TX3_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN 0 14456 #define TX3_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS 1 14457 #define TX3_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT 11 14458 14459 /* Tx3 :: anaTxAControl0 :: txck_dme_en_SM [10:10] */ 14460 #define TX3_ANATXACONTROL0_TXCK_DME_EN_SM_MASK 0x0400 14461 #define TX3_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN 0 14462 #define TX3_ANATXACONTROL0_TXCK_DME_EN_SM_BITS 1 14463 #define TX3_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT 10 14464 14465 /* Tx3 :: anaTxAControl0 :: gloopOutDis [09:09] */ 14466 #define TX3_ANATXACONTROL0_GLOOPOUTDIS_MASK 0x0200 14467 #define TX3_ANATXACONTROL0_GLOOPOUTDIS_ALIGN 0 14468 #define TX3_ANATXACONTROL0_GLOOPOUTDIS_BITS 1 14469 #define TX3_ANATXACONTROL0_GLOOPOUTDIS_SHIFT 9 14470 14471 /* Tx3 :: anaTxAControl0 :: prbs_en [08:08] */ 14472 #define TX3_ANATXACONTROL0_PRBS_EN_MASK 0x0100 14473 #define TX3_ANATXACONTROL0_PRBS_EN_ALIGN 0 14474 #define TX3_ANATXACONTROL0_PRBS_EN_BITS 1 14475 #define TX3_ANATXACONTROL0_PRBS_EN_SHIFT 8 14476 14477 /* Tx3 :: anaTxAControl0 :: pckt_en [07:07] */ 14478 #define TX3_ANATXACONTROL0_PCKT_EN_MASK 0x0080 14479 #define TX3_ANATXACONTROL0_PCKT_EN_ALIGN 0 14480 #define TX3_ANATXACONTROL0_PCKT_EN_BITS 1 14481 #define TX3_ANATXACONTROL0_PCKT_EN_SHIFT 7 14482 14483 /* Tx3 :: anaTxAControl0 :: pckt_strt [06:06] */ 14484 #define TX3_ANATXACONTROL0_PCKT_STRT_MASK 0x0040 14485 #define TX3_ANATXACONTROL0_PCKT_STRT_ALIGN 0 14486 #define TX3_ANATXACONTROL0_PCKT_STRT_BITS 1 14487 #define TX3_ANATXACONTROL0_PCKT_STRT_SHIFT 6 14488 14489 /* Tx3 :: anaTxAControl0 :: txpol_flip [05:05] */ 14490 #define TX3_ANATXACONTROL0_TXPOL_FLIP_MASK 0x0020 14491 #define TX3_ANATXACONTROL0_TXPOL_FLIP_ALIGN 0 14492 #define TX3_ANATXACONTROL0_TXPOL_FLIP_BITS 1 14493 #define TX3_ANATXACONTROL0_TXPOL_FLIP_SHIFT 5 14494 14495 /* Tx3 :: anaTxAControl0 :: rtbi_flip [04:04] */ 14496 #define TX3_ANATXACONTROL0_RTBI_FLIP_MASK 0x0010 14497 #define TX3_ANATXACONTROL0_RTBI_FLIP_ALIGN 0 14498 #define TX3_ANATXACONTROL0_RTBI_FLIP_BITS 1 14499 #define TX3_ANATXACONTROL0_RTBI_FLIP_SHIFT 4 14500 14501 /* Tx3 :: anaTxAControl0 :: eden_r [03:03] */ 14502 #define TX3_ANATXACONTROL0_EDEN_R_MASK 0x0008 14503 #define TX3_ANATXACONTROL0_EDEN_R_ALIGN 0 14504 #define TX3_ANATXACONTROL0_EDEN_R_BITS 1 14505 #define TX3_ANATXACONTROL0_EDEN_R_SHIFT 3 14506 14507 /* Tx3 :: anaTxAControl0 :: eden_force_r [02:02] */ 14508 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_MASK 0x0004 14509 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_ALIGN 0 14510 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_BITS 1 14511 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_SHIFT 2 14512 14513 /* Tx3 :: anaTxAControl0 :: txpat_en [01:01] */ 14514 #define TX3_ANATXACONTROL0_TXPAT_EN_MASK 0x0002 14515 #define TX3_ANATXACONTROL0_TXPAT_EN_ALIGN 0 14516 #define TX3_ANATXACONTROL0_TXPAT_EN_BITS 1 14517 #define TX3_ANATXACONTROL0_TXPAT_EN_SHIFT 1 14518 14519 /* Tx3 :: anaTxAControl0 :: tx_mdata_en [00:00] */ 14520 #define TX3_ANATXACONTROL0_TX_MDATA_EN_MASK 0x0001 14521 #define TX3_ANATXACONTROL0_TX_MDATA_EN_ALIGN 0 14522 #define TX3_ANATXACONTROL0_TX_MDATA_EN_BITS 1 14523 #define TX3_ANATXACONTROL0_TX_MDATA_EN_SHIFT 0 14524 14525 14526 /**************************************************************************** 14527 * Tx3 :: anaTxmdata0 14528 */ 14529 /* Tx3 :: anaTxmdata0 :: txTestMuxSel [15:13] */ 14530 #define TX3_ANATXMDATA0_TXTESTMUXSEL_MASK 0xe000 14531 #define TX3_ANATXMDATA0_TXTESTMUXSEL_ALIGN 0 14532 #define TX3_ANATXMDATA0_TXTESTMUXSEL_BITS 3 14533 #define TX3_ANATXMDATA0_TXTESTMUXSEL_SHIFT 13 14534 14535 /* Tx3 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */ 14536 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_MASK 0x1c00 14537 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN 0 14538 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_BITS 3 14539 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT 10 14540 14541 /* Tx3 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */ 14542 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_MASK 0x03ff 14543 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN 0 14544 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_BITS 10 14545 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT 0 14546 14547 14548 /**************************************************************************** 14549 * Tx3 :: anaTxmdata1 14550 */ 14551 /* Tx3 :: anaTxmdata1 :: txStatusSelect [15:14] */ 14552 #define TX3_ANATXMDATA1_TXSTATUSSELECT_MASK 0xc000 14553 #define TX3_ANATXMDATA1_TXSTATUSSELECT_ALIGN 0 14554 #define TX3_ANATXMDATA1_TXSTATUSSELECT_BITS 2 14555 #define TX3_ANATXMDATA1_TXSTATUSSELECT_SHIFT 14 14556 14557 /* Tx3 :: anaTxmdata1 :: reserved0 [13:10] */ 14558 #define TX3_ANATXMDATA1_RESERVED0_MASK 0x3c00 14559 #define TX3_ANATXMDATA1_RESERVED0_ALIGN 0 14560 #define TX3_ANATXMDATA1_RESERVED0_BITS 4 14561 #define TX3_ANATXMDATA1_RESERVED0_SHIFT 10 14562 14563 /* Tx3 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */ 14564 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_MASK 0x03ff 14565 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN 0 14566 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_BITS 10 14567 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT 0 14568 14569 14570 /**************************************************************************** 14571 * Tx3 :: anaTxAStatus1 14572 */ 14573 /* Tx3 :: anaTxAStatus1 :: tx_id [15:14] */ 14574 #define TX3_ANATXASTATUS1_TX_ID_MASK 0xc000 14575 #define TX3_ANATXASTATUS1_TX_ID_ALIGN 0 14576 #define TX3_ANATXASTATUS1_TX_ID_BITS 2 14577 #define TX3_ANATXASTATUS1_TX_ID_SHIFT 14 14578 14579 /* Tx3 :: anaTxAStatus1 :: reserved0 [13:08] */ 14580 #define TX3_ANATXASTATUS1_RESERVED0_MASK 0x3f00 14581 #define TX3_ANATXASTATUS1_RESERVED0_ALIGN 0 14582 #define TX3_ANATXASTATUS1_RESERVED0_BITS 6 14583 #define TX3_ANATXASTATUS1_RESERVED0_SHIFT 8 14584 14585 /* Tx3 :: anaTxAStatus1 :: version_id [07:04] */ 14586 #define TX3_ANATXASTATUS1_VERSION_ID_MASK 0x00f0 14587 #define TX3_ANATXASTATUS1_VERSION_ID_ALIGN 0 14588 #define TX3_ANATXASTATUS1_VERSION_ID_BITS 4 14589 #define TX3_ANATXASTATUS1_VERSION_ID_SHIFT 4 14590 14591 /* Tx3 :: anaTxAStatus1 :: reserved1 [03:00] */ 14592 #define TX3_ANATXASTATUS1_RESERVED1_MASK 0x000f 14593 #define TX3_ANATXASTATUS1_RESERVED1_ALIGN 0 14594 #define TX3_ANATXASTATUS1_RESERVED1_BITS 4 14595 #define TX3_ANATXASTATUS1_RESERVED1_SHIFT 0 14596 14597 14598 /**************************************************************************** 14599 * Tx3 :: anaTxAControl1 14600 */ 14601 /* Tx3 :: anaTxAControl1 :: ipredrv [15:13] */ 14602 #define TX3_ANATXACONTROL1_IPREDRV_MASK 0xe000 14603 #define TX3_ANATXACONTROL1_IPREDRV_ALIGN 0 14604 #define TX3_ANATXACONTROL1_IPREDRV_BITS 3 14605 #define TX3_ANATXACONTROL1_IPREDRV_SHIFT 13 14606 14607 /* Tx3 :: anaTxAControl1 :: refl_tx [12:12] */ 14608 #define TX3_ANATXACONTROL1_REFL_TX_MASK 0x1000 14609 #define TX3_ANATXACONTROL1_REFL_TX_ALIGN 0 14610 #define TX3_ANATXACONTROL1_REFL_TX_BITS 1 14611 #define TX3_ANATXACONTROL1_REFL_TX_SHIFT 12 14612 14613 /* Tx3 :: anaTxAControl1 :: refh_tx [11:11] */ 14614 #define TX3_ANATXACONTROL1_REFH_TX_MASK 0x0800 14615 #define TX3_ANATXACONTROL1_REFH_TX_ALIGN 0 14616 #define TX3_ANATXACONTROL1_REFH_TX_BITS 1 14617 #define TX3_ANATXACONTROL1_REFH_TX_SHIFT 11 14618 14619 /* Tx3 :: anaTxAControl1 :: newbias_en [10:10] */ 14620 #define TX3_ANATXACONTROL1_NEWBIAS_EN_MASK 0x0400 14621 #define TX3_ANATXACONTROL1_NEWBIAS_EN_ALIGN 0 14622 #define TX3_ANATXACONTROL1_NEWBIAS_EN_BITS 1 14623 #define TX3_ANATXACONTROL1_NEWBIAS_EN_SHIFT 10 14624 14625 /* Tx3 :: anaTxAControl1 :: drivermode [09:09] */ 14626 #define TX3_ANATXACONTROL1_DRIVERMODE_MASK 0x0200 14627 #define TX3_ANATXACONTROL1_DRIVERMODE_ALIGN 0 14628 #define TX3_ANATXACONTROL1_DRIVERMODE_BITS 1 14629 #define TX3_ANATXACONTROL1_DRIVERMODE_SHIFT 9 14630 14631 /* Tx3 :: anaTxAControl1 :: vddr_bgb [08:08] */ 14632 #define TX3_ANATXACONTROL1_VDDR_BGB_MASK 0x0100 14633 #define TX3_ANATXACONTROL1_VDDR_BGB_ALIGN 0 14634 #define TX3_ANATXACONTROL1_VDDR_BGB_BITS 1 14635 #define TX3_ANATXACONTROL1_VDDR_BGB_SHIFT 8 14636 14637 /* Tx3 :: anaTxAControl1 :: ticksel [07:06] */ 14638 #define TX3_ANATXACONTROL1_TICKSEL_MASK 0x00c0 14639 #define TX3_ANATXACONTROL1_TICKSEL_ALIGN 0 14640 #define TX3_ANATXACONTROL1_TICKSEL_BITS 2 14641 #define TX3_ANATXACONTROL1_TICKSEL_SHIFT 6 14642 14643 /* Tx1 :: (for xenia only anaTxAControl1 :: ticksel [06:06] */ 14644 #define TX3_ANATXACONTROL1_ASYM_MODE_MASK 0x0040 14645 #define TX3_ANATXACONTROL1_ASYM_MODE_ALIGN 0 14646 #define TX3_ANATXACONTROL1_ASYM_MODE_BITS 1 14647 #define TX3_ANATXACONTROL1_ASYM_MODE_SHIFT 6 14648 14649 /* Tx3 :: anaTxAControl1 :: driver_vcm [05:04] */ 14650 #define TX3_ANATXACONTROL1_DRIVER_VCM_MASK 0x0030 14651 #define TX3_ANATXACONTROL1_DRIVER_VCM_ALIGN 0 14652 #define TX3_ANATXACONTROL1_DRIVER_VCM_BITS 2 14653 #define TX3_ANATXACONTROL1_DRIVER_VCM_SHIFT 4 14654 14655 /* Tx3 :: anaTxAControl1 :: amp_ctrl [03:03] */ 14656 #define TX3_ANATXACONTROL1_AMP_CTRL_MASK 0x0008 14657 #define TX3_ANATXACONTROL1_AMP_CTRL_ALIGN 0 14658 #define TX3_ANATXACONTROL1_AMP_CTRL_BITS 1 14659 #define TX3_ANATXACONTROL1_AMP_CTRL_SHIFT 3 14660 14661 /* Tx3 :: anaTxAControl1 :: ifullspd [02:00] */ 14662 #define TX3_ANATXACONTROL1_IFULLSPD_MASK 0x0007 14663 #define TX3_ANATXACONTROL1_IFULLSPD_ALIGN 0 14664 #define TX3_ANATXACONTROL1_IFULLSPD_BITS 3 14665 #define TX3_ANATXACONTROL1_IFULLSPD_SHIFT 0 14666 14667 14668 /**************************************************************************** 14669 * Tx3 :: anaTxAControl2 14670 */ 14671 /* Tx3 :: anaTxAControl2 :: icbuf1t [15:14] */ 14672 #define TX3_ANATXACONTROL2_ICBUF1T_MASK 0xc000 14673 #define TX3_ANATXACONTROL2_ICBUF1T_ALIGN 0 14674 #define TX3_ANATXACONTROL2_ICBUF1T_BITS 2 14675 #define TX3_ANATXACONTROL2_ICBUF1T_SHIFT 14 14676 14677 /* Tx3 :: anaTxAControl2 :: icbuf2t [13:11] */ 14678 #define TX3_ANATXACONTROL2_ICBUF2T_MASK 0x3800 14679 #define TX3_ANATXACONTROL2_ICBUF2T_ALIGN 0 14680 #define TX3_ANATXACONTROL2_ICBUF2T_BITS 3 14681 #define TX3_ANATXACONTROL2_ICBUF2T_SHIFT 11 14682 14683 /* Tx3 :: anaTxAControl2 :: imin_predrv [10:10] */ 14684 #define TX3_ANATXACONTROL2_IMIN_PREDRV_MASK 0x0400 14685 #define TX3_ANATXACONTROL2_IMIN_PREDRV_ALIGN 0 14686 #define TX3_ANATXACONTROL2_IMIN_PREDRV_BITS 1 14687 #define TX3_ANATXACONTROL2_IMIN_PREDRV_SHIFT 10 14688 14689 /* Tx3 :: anaTxAControl2 :: imax_predrv [09:09] */ 14690 #define TX3_ANATXACONTROL2_IMAX_PREDRV_MASK 0x0200 14691 #define TX3_ANATXACONTROL2_IMAX_PREDRV_ALIGN 0 14692 #define TX3_ANATXACONTROL2_IMAX_PREDRV_BITS 1 14693 #define TX3_ANATXACONTROL2_IMAX_PREDRV_SHIFT 9 14694 14695 /* Tx3 :: anaTxAControl2 :: imode_predrv [08:08] */ 14696 #define TX3_ANATXACONTROL2_IMODE_PREDRV_MASK 0x0100 14697 #define TX3_ANATXACONTROL2_IMODE_PREDRV_ALIGN 0 14698 #define TX3_ANATXACONTROL2_IMODE_PREDRV_BITS 1 14699 #define TX3_ANATXACONTROL2_IMODE_PREDRV_SHIFT 8 14700 14701 /* Tx3 :: anaTxAControl2 :: i21mux [07:05] */ 14702 #define TX3_ANATXACONTROL2_I21MUX_MASK 0x00e0 14703 #define TX3_ANATXACONTROL2_I21MUX_ALIGN 0 14704 #define TX3_ANATXACONTROL2_I21MUX_BITS 3 14705 #define TX3_ANATXACONTROL2_I21MUX_SHIFT 5 14706 14707 /* Tx3 :: anaTxAControl2 :: imin_drvr [04:04] */ 14708 #define TX3_ANATXACONTROL2_IMIN_DRVR_MASK 0x0010 14709 #define TX3_ANATXACONTROL2_IMIN_DRVR_ALIGN 0 14710 #define TX3_ANATXACONTROL2_IMIN_DRVR_BITS 1 14711 #define TX3_ANATXACONTROL2_IMIN_DRVR_SHIFT 4 14712 14713 /* Tx3 :: anaTxAControl2 :: imax_drvr [03:03] */ 14714 #define TX3_ANATXACONTROL2_IMAX_DRVR_MASK 0x0008 14715 #define TX3_ANATXACONTROL2_IMAX_DRVR_ALIGN 0 14716 #define TX3_ANATXACONTROL2_IMAX_DRVR_BITS 1 14717 #define TX3_ANATXACONTROL2_IMAX_DRVR_SHIFT 3 14718 14719 /* Tx3 :: anaTxAControl2 :: imode_drvr [02:02] */ 14720 #define TX3_ANATXACONTROL2_IMODE_DRVR_MASK 0x0004 14721 #define TX3_ANATXACONTROL2_IMODE_DRVR_ALIGN 0 14722 #define TX3_ANATXACONTROL2_IMODE_DRVR_BITS 1 14723 #define TX3_ANATXACONTROL2_IMODE_DRVR_SHIFT 2 14724 14725 /* Tx3 :: anaTxAControl2 :: reserved0 [01:00] */ 14726 #define TX3_ANATXACONTROL2_RESERVED0_MASK 0x0003 14727 #define TX3_ANATXACONTROL2_RESERVED0_ALIGN 0 14728 #define TX3_ANATXACONTROL2_RESERVED0_BITS 2 14729 #define TX3_ANATXACONTROL2_RESERVED0_SHIFT 0 14730 14731 14732 /**************************************************************************** 14733 * Tx3 :: Tx_Driver 14734 */ 14735 /* Tx3 :: Tx_Driver :: ElecIdle [15:15] */ 14736 #define TX3_TX_DRIVER_ELECIDLE_MASK 0x8000 14737 #define TX3_TX_DRIVER_ELECIDLE_ALIGN 0 14738 #define TX3_TX_DRIVER_ELECIDLE_BITS 1 14739 #define TX3_TX_DRIVER_ELECIDLE_SHIFT 15 14740 14741 /* Tx3 :: Tx_Driver :: post2_coeff [14:12] */ 14742 #define TX3_TX_DRIVER_POST2_COEFF_MASK 0x7000 14743 #define TX3_TX_DRIVER_POST2_COEFF_ALIGN 0 14744 #define TX3_TX_DRIVER_POST2_COEFF_BITS 3 14745 #define TX3_TX_DRIVER_POST2_COEFF_SHIFT 12 14746 14747 /* Tx3 :: Tx_Driver :: Idriver [11:08] */ 14748 #define TX3_TX_DRIVER_IDRIVER_MASK 0x0f00 14749 #define TX3_TX_DRIVER_IDRIVER_ALIGN 0 14750 #define TX3_TX_DRIVER_IDRIVER_BITS 4 14751 #define TX3_TX_DRIVER_IDRIVER_SHIFT 8 14752 #define TX3_TX_DRIVER_IDRIVER_v680mV 0 14753 #define TX3_TX_DRIVER_IDRIVER_v730mV 1 14754 #define TX3_TX_DRIVER_IDRIVER_v780mV 2 14755 #define TX3_TX_DRIVER_IDRIVER_v830mV 3 14756 #define TX3_TX_DRIVER_IDRIVER_v880mV 4 14757 #define TX3_TX_DRIVER_IDRIVER_v930mV 5 14758 #define TX3_TX_DRIVER_IDRIVER_v980mV 6 14759 #define TX3_TX_DRIVER_IDRIVER_v1010mV 7 14760 #define TX3_TX_DRIVER_IDRIVER_v1040mV 8 14761 #define TX3_TX_DRIVER_IDRIVER_v1060mV 9 14762 #define TX3_TX_DRIVER_IDRIVER_v1070mV 10 14763 #define TX3_TX_DRIVER_IDRIVER_v1080mV 11 14764 #define TX3_TX_DRIVER_IDRIVER_v1085mV 12 14765 #define TX3_TX_DRIVER_IDRIVER_v1090mV 13 14766 #define TX3_TX_DRIVER_IDRIVER_v1095mV 14 14767 #define TX3_TX_DRIVER_IDRIVER_v1100mV 15 14768 14769 /* Tx3 :: Tx_Driver :: Ipredriver [07:04] */ 14770 #define TX3_TX_DRIVER_IPREDRIVER_MASK 0x00f0 14771 #define TX3_TX_DRIVER_IPREDRIVER_ALIGN 0 14772 #define TX3_TX_DRIVER_IPREDRIVER_BITS 4 14773 #define TX3_TX_DRIVER_IPREDRIVER_SHIFT 4 14774 14775 /* Tx3 :: Tx_Driver :: ifir [03:01] */ 14776 #define TX3_TX_DRIVER_IFIR_MASK 0x000e 14777 #define TX3_TX_DRIVER_IFIR_ALIGN 0 14778 #define TX3_TX_DRIVER_IFIR_BITS 3 14779 #define TX3_TX_DRIVER_IFIR_SHIFT 1 14780 14781 /* Tx3 :: Tx_Driver :: icbuf1t2 [00:00] */ 14782 #define TX3_TX_DRIVER_ICBUF1T2_MASK 0x0001 14783 #define TX3_TX_DRIVER_ICBUF1T2_ALIGN 0 14784 #define TX3_TX_DRIVER_ICBUF1T2_BITS 1 14785 #define TX3_TX_DRIVER_ICBUF1T2_SHIFT 0 14786 14787 14788 /**************************************************************************** 14789 * Tx3 :: anaTxAControl5 14790 */ 14791 /* Tx3 :: anaTxAControl5 :: reserved0 [15:15] */ 14792 #define TX3_ANATXACONTROL5_RESERVED0_MASK 0x8000 14793 #define TX3_ANATXACONTROL5_RESERVED0_ALIGN 0 14794 #define TX3_ANATXACONTROL5_RESERVED0_BITS 1 14795 #define TX3_ANATXACONTROL5_RESERVED0_SHIFT 15 14796 14797 /* Tx3 :: anaTxAControl5 :: tx_prbs_w_val [14:14] */ 14798 #define TX3_ANATXACONTROL5_TX_PRBS_W_VAL_MASK 0x4000 14799 #define TX3_ANATXACONTROL5_TX_PRBS_W_VAL_ALIGN 0 14800 #define TX3_ANATXACONTROL5_TX_PRBS_W_VAL_BITS 1 14801 #define TX3_ANATXACONTROL5_TX_PRBS_W_VAL_SHIFT 14 14802 14803 /* Tx3 :: anaTxAControl5 :: tx_prbs_w_force [13:13] */ 14804 #define TX3_ANATXACONTROL5_TX_PRBS_W_FORCE_MASK 0x2000 14805 #define TX3_ANATXACONTROL5_TX_PRBS_W_FORCE_ALIGN 0 14806 #define TX3_ANATXACONTROL5_TX_PRBS_W_FORCE_BITS 1 14807 #define TX3_ANATXACONTROL5_TX_PRBS_W_FORCE_SHIFT 13 14808 14809 /* Tx3 :: anaTxAControl5 :: tx_prbs_bswap [12:12] */ 14810 #define TX3_ANATXACONTROL5_TX_PRBS_BSWAP_MASK 0x1000 14811 #define TX3_ANATXACONTROL5_TX_PRBS_BSWAP_ALIGN 0 14812 #define TX3_ANATXACONTROL5_TX_PRBS_BSWAP_BITS 1 14813 #define TX3_ANATXACONTROL5_TX_PRBS_BSWAP_SHIFT 12 14814 14815 /* Tx3 :: anaTxAControl5 :: tx_bitswap [11:11] */ 14816 #define TX3_ANATXACONTROL5_TX_BITSWAP_MASK 0x0800 14817 #define TX3_ANATXACONTROL5_TX_BITSWAP_ALIGN 0 14818 #define TX3_ANATXACONTROL5_TX_BITSWAP_BITS 1 14819 #define TX3_ANATXACONTROL5_TX_BITSWAP_SHIFT 11 14820 14821 /* Tx3 :: anaTxAControl5 :: rst_tx_r [10:10] */ 14822 #define TX3_ANATXACONTROL5_RST_TX_R_MASK 0x0400 14823 #define TX3_ANATXACONTROL5_RST_TX_R_ALIGN 0 14824 #define TX3_ANATXACONTROL5_RST_TX_R_BITS 1 14825 #define TX3_ANATXACONTROL5_RST_TX_R_SHIFT 10 14826 14827 /* Tx3 :: anaTxAControl5 :: pwdwn_tx_r [09:09] */ 14828 #define TX3_ANATXACONTROL5_PWDWN_TX_R_MASK 0x0200 14829 #define TX3_ANATXACONTROL5_PWDWN_TX_R_ALIGN 0 14830 #define TX3_ANATXACONTROL5_PWDWN_TX_R_BITS 1 14831 #define TX3_ANATXACONTROL5_PWDWN_TX_R_SHIFT 9 14832 14833 /* Tx3 :: anaTxAControl5 :: tx_prbs_order_2 [08:08] */ 14834 #define TX3_ANATXACONTROL5_TX_PRBS_ORDER_2_MASK 0x0100 14835 #define TX3_ANATXACONTROL5_TX_PRBS_ORDER_2_ALIGN 0 14836 #define TX3_ANATXACONTROL5_TX_PRBS_ORDER_2_BITS 1 14837 #define TX3_ANATXACONTROL5_TX_PRBS_ORDER_2_SHIFT 8 14838 14839 /* Tx3 :: anaTxAControl5 :: ed8b10b_disable [07:07] */ 14840 #define TX3_ANATXACONTROL5_ED8B10B_DISABLE_MASK 0x0080 14841 #define TX3_ANATXACONTROL5_ED8B10B_DISABLE_ALIGN 0 14842 #define TX3_ANATXACONTROL5_ED8B10B_DISABLE_BITS 1 14843 #define TX3_ANATXACONTROL5_ED8B10B_DISABLE_SHIFT 7 14844 14845 /* Tx3 :: anaTxAControl5 :: tx_prbs_decouple_en [06:06] */ 14846 #define TX3_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_MASK 0x0040 14847 #define TX3_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_ALIGN 0 14848 #define TX3_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_BITS 1 14849 #define TX3_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_SHIFT 6 14850 14851 /* Tx3 :: anaTxAControl5 :: tx_prbs_en_decouple [05:05] */ 14852 #define TX3_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_MASK 0x0020 14853 #define TX3_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_ALIGN 0 14854 #define TX3_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_BITS 1 14855 #define TX3_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_SHIFT 5 14856 14857 /* Tx3 :: anaTxAControl5 :: tx_prbs_inv_decouple [04:04] */ 14858 #define TX3_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_MASK 0x0010 14859 #define TX3_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_ALIGN 0 14860 #define TX3_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_BITS 1 14861 #define TX3_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_SHIFT 4 14862 14863 /* Tx3 :: anaTxAControl5 :: tx_prbs_order_decouple [03:02] */ 14864 #define TX3_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_MASK 0x000c 14865 #define TX3_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_ALIGN 0 14866 #define TX3_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_BITS 2 14867 #define TX3_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_SHIFT 2 14868 14869 /* Tx3 :: anaTxAControl5 :: force_tx_sel_halfrate_val [01:01] */ 14870 #define TX3_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_MASK 0x0002 14871 #define TX3_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_ALIGN 0 14872 #define TX3_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_BITS 1 14873 #define TX3_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_SHIFT 1 14874 14875 /* Tx3 :: anaTxAControl5 :: force_tx_sel_halfrate [00:00] */ 14876 #define TX3_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_MASK 0x0001 14877 #define TX3_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_ALIGN 0 14878 #define TX3_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_BITS 1 14879 #define TX3_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_SHIFT 0 14880 14881 14882 /**************************************************************************** 14883 * Tx3 :: anaTxAControl6 14884 */ 14885 /* Tx3 :: anaTxAControl6 :: reserved0 [15:06] */ 14886 #define TX3_ANATXACONTROL6_RESERVED0_MASK 0xffc0 14887 #define TX3_ANATXACONTROL6_RESERVED0_ALIGN 0 14888 #define TX3_ANATXACONTROL6_RESERVED0_BITS 10 14889 #define TX3_ANATXACONTROL6_RESERVED0_SHIFT 6 14890 14891 /* Tx3 :: anaTxAControl6 :: sel_8b10b_default_cya [05:05] */ 14892 #define TX3_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_MASK 0x0020 14893 #define TX3_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_ALIGN 0 14894 #define TX3_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_BITS 1 14895 #define TX3_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_SHIFT 5 14896 14897 /* Tx3 :: anaTxAControl6 :: ckgate_int_sel_div1_1p5_2_2p5 [04:04] */ 14898 #define TX3_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_MASK 0x0010 14899 #define TX3_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_ALIGN 0 14900 #define TX3_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_BITS 1 14901 #define TX3_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_SHIFT 4 14902 14903 /* Tx3 :: anaTxAControl6 :: gloop_r [03:03] */ 14904 #define TX3_ANATXACONTROL6_GLOOP_R_MASK 0x0008 14905 #define TX3_ANATXACONTROL6_GLOOP_R_ALIGN 0 14906 #define TX3_ANATXACONTROL6_GLOOP_R_BITS 1 14907 #define TX3_ANATXACONTROL6_GLOOP_R_SHIFT 3 14908 14909 /* Tx3 :: anaTxAControl6 :: rloop_r [02:02] */ 14910 #define TX3_ANATXACONTROL6_RLOOP_R_MASK 0x0004 14911 #define TX3_ANATXACONTROL6_RLOOP_R_ALIGN 0 14912 #define TX3_ANATXACONTROL6_RLOOP_R_BITS 1 14913 #define TX3_ANATXACONTROL6_RLOOP_R_SHIFT 2 14914 14915 /* Tx3 :: anaTxAControl6 :: ckgate_ext_sel [01:01] */ 14916 #define TX3_ANATXACONTROL6_CKGATE_EXT_SEL_MASK 0x0002 14917 #define TX3_ANATXACONTROL6_CKGATE_EXT_SEL_ALIGN 0 14918 #define TX3_ANATXACONTROL6_CKGATE_EXT_SEL_BITS 1 14919 #define TX3_ANATXACONTROL6_CKGATE_EXT_SEL_SHIFT 1 14920 14921 /* Tx3 :: anaTxAControl6 :: disable_tx_r [00:00] */ 14922 #define TX3_ANATXACONTROL6_DISABLE_TX_R_MASK 0x0001 14923 #define TX3_ANATXACONTROL6_DISABLE_TX_R_ALIGN 0 14924 #define TX3_ANATXACONTROL6_DISABLE_TX_R_BITS 1 14925 #define TX3_ANATXACONTROL6_DISABLE_TX_R_SHIFT 0 14926 14927 14928 /**************************************************************************** 14929 * Warpcore_USER_TxB 14930 */ 14931 /**************************************************************************** 14932 * TxB :: anaTxAStatus0 14933 */ 14934 /* union - case txStatusSelect_equals_0 [15:00] */ 14935 /* TxB :: anaTxAStatus0 :: reserved0 [15:11] */ 14936 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_MASK 0xf800 14937 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_ALIGN 0 14938 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_BITS 5 14939 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_SHIFT 11 14940 14941 /* TxB :: anaTxAStatus0 :: oscdr_mode_indch_tx [10:07] */ 14942 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_MASK 0x0780 14943 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_ALIGN 0 14944 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_BITS 4 14945 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_OSCDR_MODE_INDCH_TX_SHIFT 7 14946 14947 /* TxB :: anaTxAStatus0 :: txdisable_ln [06:06] */ 14948 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_MASK 0x0040 14949 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_ALIGN 0 14950 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_BITS 1 14951 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_SHIFT 6 14952 14953 /* TxB :: anaTxAStatus0 :: txferr_stky [05:05] */ 14954 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_MASK 0x0020 14955 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_ALIGN 0 14956 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_BITS 1 14957 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_SHIFT 5 14958 14959 /* TxB :: anaTxAStatus0 :: tbi_mode [04:04] */ 14960 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_MASK 0x0010 14961 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_ALIGN 0 14962 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_BITS 1 14963 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_SHIFT 4 14964 14965 /* TxB :: anaTxAStatus0 :: tx_reset [03:03] */ 14966 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_MASK 0x0008 14967 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_ALIGN 0 14968 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_BITS 1 14969 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_SHIFT 3 14970 14971 /* TxB :: anaTxAStatus0 :: tx_pwrdn [02:02] */ 14972 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_MASK 0x0004 14973 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_ALIGN 0 14974 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_BITS 1 14975 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_SHIFT 2 14976 14977 /* TxB :: anaTxAStatus0 :: rltxferr_stky [01:01] */ 14978 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_MASK 0x0002 14979 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_ALIGN 0 14980 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_BITS 1 14981 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_SHIFT 1 14982 14983 /* TxB :: anaTxAStatus0 :: txpll_lock [00:00] */ 14984 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_MASK 0x0001 14985 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_ALIGN 0 14986 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_BITS 1 14987 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_SHIFT 0 14988 14989 14990 /* union - case txStatusSelect_equals_1 [15:00] */ 14991 /* TxB :: anaTxAStatus0 :: tx_sel_halfrate [15:15] */ 14992 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_MASK 0x8000 14993 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_ALIGN 0 14994 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_BITS 1 14995 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_SHIFT 15 14996 14997 /* TxB :: anaTxAStatus0 :: tx_fir_tap_post [14:10] */ 14998 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_MASK 0x7c00 14999 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_ALIGN 0 15000 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_BITS 5 15001 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_SHIFT 10 15002 15003 /* TxB :: anaTxAStatus0 :: tx_fir_tap_main [09:04] */ 15004 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_MASK 0x03f0 15005 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_ALIGN 0 15006 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_BITS 6 15007 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_SHIFT 4 15008 15009 /* TxB :: anaTxAStatus0 :: tx_fir_tap_pre [03:00] */ 15010 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_MASK 0x000f 15011 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_ALIGN 0 15012 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_BITS 4 15013 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_SHIFT 0 15014 15015 15016 15017 /**************************************************************************** 15018 * TxB :: anaTxAControl0 15019 */ 15020 /* TxB :: anaTxAControl0 :: reserved0 [15:15] */ 15021 #define TXB_ANATXACONTROL0_RESERVED0_MASK 0x8000 15022 #define TXB_ANATXACONTROL0_RESERVED0_ALIGN 0 15023 #define TXB_ANATXACONTROL0_RESERVED0_BITS 1 15024 #define TXB_ANATXACONTROL0_RESERVED0_SHIFT 15 15025 15026 /* TxB :: anaTxAControl0 :: force_txclk [14:14] */ 15027 #define TXB_ANATXACONTROL0_FORCE_TXCLK_MASK 0x4000 15028 #define TXB_ANATXACONTROL0_FORCE_TXCLK_ALIGN 0 15029 #define TXB_ANATXACONTROL0_FORCE_TXCLK_BITS 1 15030 #define TXB_ANATXACONTROL0_FORCE_TXCLK_SHIFT 14 15031 15032 /* TxB :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */ 15033 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_MASK 0x2000 15034 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN 0 15035 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_BITS 1 15036 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT 13 15037 15038 /* TxB :: anaTxAControl0 :: force_ext_frst_SM [12:12] */ 15039 #define TXB_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK 0x1000 15040 #define TXB_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN 0 15041 #define TXB_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS 1 15042 #define TXB_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT 12 15043 15044 /* TxB :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */ 15045 #define TXB_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK 0x0800 15046 #define TXB_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN 0 15047 #define TXB_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS 1 15048 #define TXB_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT 11 15049 15050 /* TxB :: anaTxAControl0 :: txck_dme_en_SM [10:10] */ 15051 #define TXB_ANATXACONTROL0_TXCK_DME_EN_SM_MASK 0x0400 15052 #define TXB_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN 0 15053 #define TXB_ANATXACONTROL0_TXCK_DME_EN_SM_BITS 1 15054 #define TXB_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT 10 15055 15056 /* TxB :: anaTxAControl0 :: gloopOutDis [09:09] */ 15057 #define TXB_ANATXACONTROL0_GLOOPOUTDIS_MASK 0x0200 15058 #define TXB_ANATXACONTROL0_GLOOPOUTDIS_ALIGN 0 15059 #define TXB_ANATXACONTROL0_GLOOPOUTDIS_BITS 1 15060 #define TXB_ANATXACONTROL0_GLOOPOUTDIS_SHIFT 9 15061 15062 /* TxB :: anaTxAControl0 :: prbs_en [08:08] */ 15063 #define TXB_ANATXACONTROL0_PRBS_EN_MASK 0x0100 15064 #define TXB_ANATXACONTROL0_PRBS_EN_ALIGN 0 15065 #define TXB_ANATXACONTROL0_PRBS_EN_BITS 1 15066 #define TXB_ANATXACONTROL0_PRBS_EN_SHIFT 8 15067 15068 /* TxB :: anaTxAControl0 :: pckt_en [07:07] */ 15069 #define TXB_ANATXACONTROL0_PCKT_EN_MASK 0x0080 15070 #define TXB_ANATXACONTROL0_PCKT_EN_ALIGN 0 15071 #define TXB_ANATXACONTROL0_PCKT_EN_BITS 1 15072 #define TXB_ANATXACONTROL0_PCKT_EN_SHIFT 7 15073 15074 /* TxB :: anaTxAControl0 :: pckt_strt [06:06] */ 15075 #define TXB_ANATXACONTROL0_PCKT_STRT_MASK 0x0040 15076 #define TXB_ANATXACONTROL0_PCKT_STRT_ALIGN 0 15077 #define TXB_ANATXACONTROL0_PCKT_STRT_BITS 1 15078 #define TXB_ANATXACONTROL0_PCKT_STRT_SHIFT 6 15079 15080 /* TxB :: anaTxAControl0 :: txpol_flip [05:05] */ 15081 #define TXB_ANATXACONTROL0_TXPOL_FLIP_MASK 0x0020 15082 #define TXB_ANATXACONTROL0_TXPOL_FLIP_ALIGN 0 15083 #define TXB_ANATXACONTROL0_TXPOL_FLIP_BITS 1 15084 #define TXB_ANATXACONTROL0_TXPOL_FLIP_SHIFT 5 15085 15086 /* TxB :: anaTxAControl0 :: rtbi_flip [04:04] */ 15087 #define TXB_ANATXACONTROL0_RTBI_FLIP_MASK 0x0010 15088 #define TXB_ANATXACONTROL0_RTBI_FLIP_ALIGN 0 15089 #define TXB_ANATXACONTROL0_RTBI_FLIP_BITS 1 15090 #define TXB_ANATXACONTROL0_RTBI_FLIP_SHIFT 4 15091 15092 /* TxB :: anaTxAControl0 :: eden_r [03:03] */ 15093 #define TXB_ANATXACONTROL0_EDEN_R_MASK 0x0008 15094 #define TXB_ANATXACONTROL0_EDEN_R_ALIGN 0 15095 #define TXB_ANATXACONTROL0_EDEN_R_BITS 1 15096 #define TXB_ANATXACONTROL0_EDEN_R_SHIFT 3 15097 15098 /* TxB :: anaTxAControl0 :: eden_force_r [02:02] */ 15099 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_MASK 0x0004 15100 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_ALIGN 0 15101 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_BITS 1 15102 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_SHIFT 2 15103 15104 /* TxB :: anaTxAControl0 :: txpat_en [01:01] */ 15105 #define TXB_ANATXACONTROL0_TXPAT_EN_MASK 0x0002 15106 #define TXB_ANATXACONTROL0_TXPAT_EN_ALIGN 0 15107 #define TXB_ANATXACONTROL0_TXPAT_EN_BITS 1 15108 #define TXB_ANATXACONTROL0_TXPAT_EN_SHIFT 1 15109 15110 /* TxB :: anaTxAControl0 :: tx_mdata_en [00:00] */ 15111 #define TXB_ANATXACONTROL0_TX_MDATA_EN_MASK 0x0001 15112 #define TXB_ANATXACONTROL0_TX_MDATA_EN_ALIGN 0 15113 #define TXB_ANATXACONTROL0_TX_MDATA_EN_BITS 1 15114 #define TXB_ANATXACONTROL0_TX_MDATA_EN_SHIFT 0 15115 15116 15117 /**************************************************************************** 15118 * TxB :: anaTxmdata0 15119 */ 15120 /* TxB :: anaTxmdata0 :: txTestMuxSel [15:13] */ 15121 #define TXB_ANATXMDATA0_TXTESTMUXSEL_MASK 0xe000 15122 #define TXB_ANATXMDATA0_TXTESTMUXSEL_ALIGN 0 15123 #define TXB_ANATXMDATA0_TXTESTMUXSEL_BITS 3 15124 #define TXB_ANATXMDATA0_TXTESTMUXSEL_SHIFT 13 15125 15126 /* TxB :: anaTxmdata0 :: rlfifo_tstsel [12:10] */ 15127 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_MASK 0x1c00 15128 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN 0 15129 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_BITS 3 15130 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT 10 15131 15132 /* TxB :: anaTxmdata0 :: TxMdioTstDataL [09:00] */ 15133 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_MASK 0x03ff 15134 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN 0 15135 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_BITS 10 15136 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT 0 15137 15138 15139 /**************************************************************************** 15140 * TxB :: anaTxmdata1 15141 */ 15142 /* TxB :: anaTxmdata1 :: txStatusSelect [15:14] */ 15143 #define TXB_ANATXMDATA1_TXSTATUSSELECT_MASK 0xc000 15144 #define TXB_ANATXMDATA1_TXSTATUSSELECT_ALIGN 0 15145 #define TXB_ANATXMDATA1_TXSTATUSSELECT_BITS 2 15146 #define TXB_ANATXMDATA1_TXSTATUSSELECT_SHIFT 14 15147 15148 /* TxB :: anaTxmdata1 :: reserved0 [13:10] */ 15149 #define TXB_ANATXMDATA1_RESERVED0_MASK 0x3c00 15150 #define TXB_ANATXMDATA1_RESERVED0_ALIGN 0 15151 #define TXB_ANATXMDATA1_RESERVED0_BITS 4 15152 #define TXB_ANATXMDATA1_RESERVED0_SHIFT 10 15153 15154 /* TxB :: anaTxmdata1 :: TxMdioTstDataH [09:00] */ 15155 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_MASK 0x03ff 15156 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN 0 15157 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_BITS 10 15158 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT 0 15159 15160 15161 /**************************************************************************** 15162 * TxB :: anaTxAStatus1 15163 */ 15164 /* TxB :: anaTxAStatus1 :: tx_id [15:14] */ 15165 #define TXB_ANATXASTATUS1_TX_ID_MASK 0xc000 15166 #define TXB_ANATXASTATUS1_TX_ID_ALIGN 0 15167 #define TXB_ANATXASTATUS1_TX_ID_BITS 2 15168 #define TXB_ANATXASTATUS1_TX_ID_SHIFT 14 15169 15170 /* TxB :: anaTxAStatus1 :: reserved0 [13:08] */ 15171 #define TXB_ANATXASTATUS1_RESERVED0_MASK 0x3f00 15172 #define TXB_ANATXASTATUS1_RESERVED0_ALIGN 0 15173 #define TXB_ANATXASTATUS1_RESERVED0_BITS 6 15174 #define TXB_ANATXASTATUS1_RESERVED0_SHIFT 8 15175 15176 /* TxB :: anaTxAStatus1 :: version_id [07:04] */ 15177 #define TXB_ANATXASTATUS1_VERSION_ID_MASK 0x00f0 15178 #define TXB_ANATXASTATUS1_VERSION_ID_ALIGN 0 15179 #define TXB_ANATXASTATUS1_VERSION_ID_BITS 4 15180 #define TXB_ANATXASTATUS1_VERSION_ID_SHIFT 4 15181 15182 /* TxB :: anaTxAStatus1 :: reserved1 [03:00] */ 15183 #define TXB_ANATXASTATUS1_RESERVED1_MASK 0x000f 15184 #define TXB_ANATXASTATUS1_RESERVED1_ALIGN 0 15185 #define TXB_ANATXASTATUS1_RESERVED1_BITS 4 15186 #define TXB_ANATXASTATUS1_RESERVED1_SHIFT 0 15187 15188 15189 /**************************************************************************** 15190 * TxB :: anaTxAControl1 15191 */ 15192 /* TxB :: anaTxAControl1 :: ipredrv [15:13] */ 15193 #define TXB_ANATXACONTROL1_IPREDRV_MASK 0xe000 15194 #define TXB_ANATXACONTROL1_IPREDRV_ALIGN 0 15195 #define TXB_ANATXACONTROL1_IPREDRV_BITS 3 15196 #define TXB_ANATXACONTROL1_IPREDRV_SHIFT 13 15197 15198 /* TxB :: anaTxAControl1 :: refl_tx [12:12] */ 15199 #define TXB_ANATXACONTROL1_REFL_TX_MASK 0x1000 15200 #define TXB_ANATXACONTROL1_REFL_TX_ALIGN 0 15201 #define TXB_ANATXACONTROL1_REFL_TX_BITS 1 15202 #define TXB_ANATXACONTROL1_REFL_TX_SHIFT 12 15203 15204 /* TxB :: anaTxAControl1 :: refh_tx [11:11] */ 15205 #define TXB_ANATXACONTROL1_REFH_TX_MASK 0x0800 15206 #define TXB_ANATXACONTROL1_REFH_TX_ALIGN 0 15207 #define TXB_ANATXACONTROL1_REFH_TX_BITS 1 15208 #define TXB_ANATXACONTROL1_REFH_TX_SHIFT 11 15209 15210 /* TxB :: anaTxAControl1 :: newbias_en [10:10] */ 15211 #define TXB_ANATXACONTROL1_NEWBIAS_EN_MASK 0x0400 15212 #define TXB_ANATXACONTROL1_NEWBIAS_EN_ALIGN 0 15213 #define TXB_ANATXACONTROL1_NEWBIAS_EN_BITS 1 15214 #define TXB_ANATXACONTROL1_NEWBIAS_EN_SHIFT 10 15215 15216 /* TxB :: anaTxAControl1 :: drivermode [09:09] */ 15217 #define TXB_ANATXACONTROL1_DRIVERMODE_MASK 0x0200 15218 #define TXB_ANATXACONTROL1_DRIVERMODE_ALIGN 0 15219 #define TXB_ANATXACONTROL1_DRIVERMODE_BITS 1 15220 #define TXB_ANATXACONTROL1_DRIVERMODE_SHIFT 9 15221 15222 /* TxB :: anaTxAControl1 :: vddr_bgb [08:08] */ 15223 #define TXB_ANATXACONTROL1_VDDR_BGB_MASK 0x0100 15224 #define TXB_ANATXACONTROL1_VDDR_BGB_ALIGN 0 15225 #define TXB_ANATXACONTROL1_VDDR_BGB_BITS 1 15226 #define TXB_ANATXACONTROL1_VDDR_BGB_SHIFT 8 15227 15228 /* TxB :: anaTxAControl1 :: ticksel [07:06] */ 15229 #define TXB_ANATXACONTROL1_TICKSEL_MASK 0x00c0 15230 #define TXB_ANATXACONTROL1_TICKSEL_ALIGN 0 15231 #define TXB_ANATXACONTROL1_TICKSEL_BITS 2 15232 #define TXB_ANATXACONTROL1_TICKSEL_SHIFT 6 15233 15234 /* TxB :: anaTxAControl1 :: driver_vcm [05:04] */ 15235 #define TXB_ANATXACONTROL1_DRIVER_VCM_MASK 0x0030 15236 #define TXB_ANATXACONTROL1_DRIVER_VCM_ALIGN 0 15237 #define TXB_ANATXACONTROL1_DRIVER_VCM_BITS 2 15238 #define TXB_ANATXACONTROL1_DRIVER_VCM_SHIFT 4 15239 15240 /* TxB :: anaTxAControl1 :: amp_ctrl [03:03] */ 15241 #define TXB_ANATXACONTROL1_AMP_CTRL_MASK 0x0008 15242 #define TXB_ANATXACONTROL1_AMP_CTRL_ALIGN 0 15243 #define TXB_ANATXACONTROL1_AMP_CTRL_BITS 1 15244 #define TXB_ANATXACONTROL1_AMP_CTRL_SHIFT 3 15245 15246 /* TxB :: anaTxAControl1 :: ifullspd [02:00] */ 15247 #define TXB_ANATXACONTROL1_IFULLSPD_MASK 0x0007 15248 #define TXB_ANATXACONTROL1_IFULLSPD_ALIGN 0 15249 #define TXB_ANATXACONTROL1_IFULLSPD_BITS 3 15250 #define TXB_ANATXACONTROL1_IFULLSPD_SHIFT 0 15251 15252 15253 /**************************************************************************** 15254 * TxB :: anaTxAControl2 15255 */ 15256 /* TxB :: anaTxAControl2 :: icbuf1t [15:14] */ 15257 #define TXB_ANATXACONTROL2_ICBUF1T_MASK 0xc000 15258 #define TXB_ANATXACONTROL2_ICBUF1T_ALIGN 0 15259 #define TXB_ANATXACONTROL2_ICBUF1T_BITS 2 15260 #define TXB_ANATXACONTROL2_ICBUF1T_SHIFT 14 15261 15262 /* TxB :: anaTxAControl2 :: icbuf2t [13:11] */ 15263 #define TXB_ANATXACONTROL2_ICBUF2T_MASK 0x3800 15264 #define TXB_ANATXACONTROL2_ICBUF2T_ALIGN 0 15265 #define TXB_ANATXACONTROL2_ICBUF2T_BITS 3 15266 #define TXB_ANATXACONTROL2_ICBUF2T_SHIFT 11 15267 15268 /* TxB :: anaTxAControl2 :: imin_predrv [10:10] */ 15269 #define TXB_ANATXACONTROL2_IMIN_PREDRV_MASK 0x0400 15270 #define TXB_ANATXACONTROL2_IMIN_PREDRV_ALIGN 0 15271 #define TXB_ANATXACONTROL2_IMIN_PREDRV_BITS 1 15272 #define TXB_ANATXACONTROL2_IMIN_PREDRV_SHIFT 10 15273 15274 /* TxB :: anaTxAControl2 :: imax_predrv [09:09] */ 15275 #define TXB_ANATXACONTROL2_IMAX_PREDRV_MASK 0x0200 15276 #define TXB_ANATXACONTROL2_IMAX_PREDRV_ALIGN 0 15277 #define TXB_ANATXACONTROL2_IMAX_PREDRV_BITS 1 15278 #define TXB_ANATXACONTROL2_IMAX_PREDRV_SHIFT 9 15279 15280 /* TxB :: anaTxAControl2 :: imode_predrv [08:08] */ 15281 #define TXB_ANATXACONTROL2_IMODE_PREDRV_MASK 0x0100 15282 #define TXB_ANATXACONTROL2_IMODE_PREDRV_ALIGN 0 15283 #define TXB_ANATXACONTROL2_IMODE_PREDRV_BITS 1 15284 #define TXB_ANATXACONTROL2_IMODE_PREDRV_SHIFT 8 15285 15286 /* TxB :: anaTxAControl2 :: i21mux [07:05] */ 15287 #define TXB_ANATXACONTROL2_I21MUX_MASK 0x00e0 15288 #define TXB_ANATXACONTROL2_I21MUX_ALIGN 0 15289 #define TXB_ANATXACONTROL2_I21MUX_BITS 3 15290 #define TXB_ANATXACONTROL2_I21MUX_SHIFT 5 15291 15292 /* TxB :: anaTxAControl2 :: imin_drvr [04:04] */ 15293 #define TXB_ANATXACONTROL2_IMIN_DRVR_MASK 0x0010 15294 #define TXB_ANATXACONTROL2_IMIN_DRVR_ALIGN 0 15295 #define TXB_ANATXACONTROL2_IMIN_DRVR_BITS 1 15296 #define TXB_ANATXACONTROL2_IMIN_DRVR_SHIFT 4 15297 15298 /* TxB :: anaTxAControl2 :: imax_drvr [03:03] */ 15299 #define TXB_ANATXACONTROL2_IMAX_DRVR_MASK 0x0008 15300 #define TXB_ANATXACONTROL2_IMAX_DRVR_ALIGN 0 15301 #define TXB_ANATXACONTROL2_IMAX_DRVR_BITS 1 15302 #define TXB_ANATXACONTROL2_IMAX_DRVR_SHIFT 3 15303 15304 /* TxB :: anaTxAControl2 :: imode_drvr [02:02] */ 15305 #define TXB_ANATXACONTROL2_IMODE_DRVR_MASK 0x0004 15306 #define TXB_ANATXACONTROL2_IMODE_DRVR_ALIGN 0 15307 #define TXB_ANATXACONTROL2_IMODE_DRVR_BITS 1 15308 #define TXB_ANATXACONTROL2_IMODE_DRVR_SHIFT 2 15309 15310 /* TxB :: anaTxAControl2 :: reserved0 [01:00] */ 15311 #define TXB_ANATXACONTROL2_RESERVED0_MASK 0x0003 15312 #define TXB_ANATXACONTROL2_RESERVED0_ALIGN 0 15313 #define TXB_ANATXACONTROL2_RESERVED0_BITS 2 15314 #define TXB_ANATXACONTROL2_RESERVED0_SHIFT 0 15315 15316 15317 /**************************************************************************** 15318 * TxB :: Tx_Driver 15319 */ 15320 /* TxB :: Tx_Driver :: ElecIdle [15:15] */ 15321 #define TXB_TX_DRIVER_ELECIDLE_MASK 0x8000 15322 #define TXB_TX_DRIVER_ELECIDLE_ALIGN 0 15323 #define TXB_TX_DRIVER_ELECIDLE_BITS 1 15324 #define TXB_TX_DRIVER_ELECIDLE_SHIFT 15 15325 15326 /* TxB :: Tx_Driver :: post2_coeff [14:12] */ 15327 #define TXB_TX_DRIVER_POST2_COEFF_MASK 0x7000 15328 #define TXB_TX_DRIVER_POST2_COEFF_ALIGN 0 15329 #define TXB_TX_DRIVER_POST2_COEFF_BITS 3 15330 #define TXB_TX_DRIVER_POST2_COEFF_SHIFT 12 15331 15332 /* TxB :: Tx_Driver :: Idriver [11:08] */ 15333 #define TXB_TX_DRIVER_IDRIVER_MASK 0x0f00 15334 #define TXB_TX_DRIVER_IDRIVER_ALIGN 0 15335 #define TXB_TX_DRIVER_IDRIVER_BITS 4 15336 #define TXB_TX_DRIVER_IDRIVER_SHIFT 8 15337 #define TXB_TX_DRIVER_IDRIVER_v680mV 0 15338 #define TXB_TX_DRIVER_IDRIVER_v730mV 1 15339 #define TXB_TX_DRIVER_IDRIVER_v780mV 2 15340 #define TXB_TX_DRIVER_IDRIVER_v830mV 3 15341 #define TXB_TX_DRIVER_IDRIVER_v880mV 4 15342 #define TXB_TX_DRIVER_IDRIVER_v930mV 5 15343 #define TXB_TX_DRIVER_IDRIVER_v980mV 6 15344 #define TXB_TX_DRIVER_IDRIVER_v1010mV 7 15345 #define TXB_TX_DRIVER_IDRIVER_v1040mV 8 15346 #define TXB_TX_DRIVER_IDRIVER_v1060mV 9 15347 #define TXB_TX_DRIVER_IDRIVER_v1070mV 10 15348 #define TXB_TX_DRIVER_IDRIVER_v1080mV 11 15349 #define TXB_TX_DRIVER_IDRIVER_v1085mV 12 15350 #define TXB_TX_DRIVER_IDRIVER_v1090mV 13 15351 #define TXB_TX_DRIVER_IDRIVER_v1095mV 14 15352 #define TXB_TX_DRIVER_IDRIVER_v1100mV 15 15353 15354 /* TxB :: Tx_Driver :: Ipredriver [07:04] */ 15355 #define TXB_TX_DRIVER_IPREDRIVER_MASK 0x00f0 15356 #define TXB_TX_DRIVER_IPREDRIVER_ALIGN 0 15357 #define TXB_TX_DRIVER_IPREDRIVER_BITS 4 15358 #define TXB_TX_DRIVER_IPREDRIVER_SHIFT 4 15359 15360 /* TxB :: Tx_Driver :: ifir [03:01] */ 15361 #define TXB_TX_DRIVER_IFIR_MASK 0x000e 15362 #define TXB_TX_DRIVER_IFIR_ALIGN 0 15363 #define TXB_TX_DRIVER_IFIR_BITS 3 15364 #define TXB_TX_DRIVER_IFIR_SHIFT 1 15365 15366 /* TxB :: Tx_Driver :: icbuf1t2 [00:00] */ 15367 #define TXB_TX_DRIVER_ICBUF1T2_MASK 0x0001 15368 #define TXB_TX_DRIVER_ICBUF1T2_ALIGN 0 15369 #define TXB_TX_DRIVER_ICBUF1T2_BITS 1 15370 #define TXB_TX_DRIVER_ICBUF1T2_SHIFT 0 15371 15372 15373 /**************************************************************************** 15374 * TxB :: anaTxAControl5 15375 */ 15376 /* TxB :: anaTxAControl5 :: reserved0 [15:15] */ 15377 #define TXB_ANATXACONTROL5_RESERVED0_MASK 0x8000 15378 #define TXB_ANATXACONTROL5_RESERVED0_ALIGN 0 15379 #define TXB_ANATXACONTROL5_RESERVED0_BITS 1 15380 #define TXB_ANATXACONTROL5_RESERVED0_SHIFT 15 15381 15382 /* TxB :: anaTxAControl5 :: tx_prbs_w_val [14:14] */ 15383 #define TXB_ANATXACONTROL5_TX_PRBS_W_VAL_MASK 0x4000 15384 #define TXB_ANATXACONTROL5_TX_PRBS_W_VAL_ALIGN 0 15385 #define TXB_ANATXACONTROL5_TX_PRBS_W_VAL_BITS 1 15386 #define TXB_ANATXACONTROL5_TX_PRBS_W_VAL_SHIFT 14 15387 15388 /* TxB :: anaTxAControl5 :: tx_prbs_w_force [13:13] */ 15389 #define TXB_ANATXACONTROL5_TX_PRBS_W_FORCE_MASK 0x2000 15390 #define TXB_ANATXACONTROL5_TX_PRBS_W_FORCE_ALIGN 0 15391 #define TXB_ANATXACONTROL5_TX_PRBS_W_FORCE_BITS 1 15392 #define TXB_ANATXACONTROL5_TX_PRBS_W_FORCE_SHIFT 13 15393 15394 /* TxB :: anaTxAControl5 :: tx_prbs_bswap [12:12] */ 15395 #define TXB_ANATXACONTROL5_TX_PRBS_BSWAP_MASK 0x1000 15396 #define TXB_ANATXACONTROL5_TX_PRBS_BSWAP_ALIGN 0 15397 #define TXB_ANATXACONTROL5_TX_PRBS_BSWAP_BITS 1 15398 #define TXB_ANATXACONTROL5_TX_PRBS_BSWAP_SHIFT 12 15399 15400 /* TxB :: anaTxAControl5 :: tx_bitswap [11:11] */ 15401 #define TXB_ANATXACONTROL5_TX_BITSWAP_MASK 0x0800 15402 #define TXB_ANATXACONTROL5_TX_BITSWAP_ALIGN 0 15403 #define TXB_ANATXACONTROL5_TX_BITSWAP_BITS 1 15404 #define TXB_ANATXACONTROL5_TX_BITSWAP_SHIFT 11 15405 15406 /* TxB :: anaTxAControl5 :: rst_tx_r [10:10] */ 15407 #define TXB_ANATXACONTROL5_RST_TX_R_MASK 0x0400 15408 #define TXB_ANATXACONTROL5_RST_TX_R_ALIGN 0 15409 #define TXB_ANATXACONTROL5_RST_TX_R_BITS 1 15410 #define TXB_ANATXACONTROL5_RST_TX_R_SHIFT 10 15411 15412 /* TxB :: anaTxAControl5 :: pwdwn_tx_r [09:09] */ 15413 #define TXB_ANATXACONTROL5_PWDWN_TX_R_MASK 0x0200 15414 #define TXB_ANATXACONTROL5_PWDWN_TX_R_ALIGN 0 15415 #define TXB_ANATXACONTROL5_PWDWN_TX_R_BITS 1 15416 #define TXB_ANATXACONTROL5_PWDWN_TX_R_SHIFT 9 15417 15418 /* TxB :: anaTxAControl5 :: tx_prbs_order_2 [08:08] */ 15419 #define TXB_ANATXACONTROL5_TX_PRBS_ORDER_2_MASK 0x0100 15420 #define TXB_ANATXACONTROL5_TX_PRBS_ORDER_2_ALIGN 0 15421 #define TXB_ANATXACONTROL5_TX_PRBS_ORDER_2_BITS 1 15422 #define TXB_ANATXACONTROL5_TX_PRBS_ORDER_2_SHIFT 8 15423 15424 /* TxB :: anaTxAControl5 :: ed8b10b_disable [07:07] */ 15425 #define TXB_ANATXACONTROL5_ED8B10B_DISABLE_MASK 0x0080 15426 #define TXB_ANATXACONTROL5_ED8B10B_DISABLE_ALIGN 0 15427 #define TXB_ANATXACONTROL5_ED8B10B_DISABLE_BITS 1 15428 #define TXB_ANATXACONTROL5_ED8B10B_DISABLE_SHIFT 7 15429 15430 /* TxB :: anaTxAControl5 :: tx_prbs_decouple_en [06:06] */ 15431 #define TXB_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_MASK 0x0040 15432 #define TXB_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_ALIGN 0 15433 #define TXB_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_BITS 1 15434 #define TXB_ANATXACONTROL5_TX_PRBS_DECOUPLE_EN_SHIFT 6 15435 15436 /* TxB :: anaTxAControl5 :: tx_prbs_en_decouple [05:05] */ 15437 #define TXB_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_MASK 0x0020 15438 #define TXB_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_ALIGN 0 15439 #define TXB_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_BITS 1 15440 #define TXB_ANATXACONTROL5_TX_PRBS_EN_DECOUPLE_SHIFT 5 15441 15442 /* TxB :: anaTxAControl5 :: tx_prbs_inv_decouple [04:04] */ 15443 #define TXB_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_MASK 0x0010 15444 #define TXB_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_ALIGN 0 15445 #define TXB_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_BITS 1 15446 #define TXB_ANATXACONTROL5_TX_PRBS_INV_DECOUPLE_SHIFT 4 15447 15448 /* TxB :: anaTxAControl5 :: tx_prbs_order_decouple [03:02] */ 15449 #define TXB_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_MASK 0x000c 15450 #define TXB_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_ALIGN 0 15451 #define TXB_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_BITS 2 15452 #define TXB_ANATXACONTROL5_TX_PRBS_ORDER_DECOUPLE_SHIFT 2 15453 15454 /* TxB :: anaTxAControl5 :: force_tx_sel_halfrate_val [01:01] */ 15455 #define TXB_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_MASK 0x0002 15456 #define TXB_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_ALIGN 0 15457 #define TXB_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_BITS 1 15458 #define TXB_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_SHIFT 1 15459 15460 /* TxB :: anaTxAControl5 :: force_tx_sel_halfrate [00:00] */ 15461 #define TXB_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_MASK 0x0001 15462 #define TXB_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_ALIGN 0 15463 #define TXB_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_BITS 1 15464 #define TXB_ANATXACONTROL5_FORCE_TX_SEL_HALFRATE_SHIFT 0 15465 15466 15467 /**************************************************************************** 15468 * TxB :: anaTxAControl6 15469 */ 15470 /* TxB :: anaTxAControl6 :: reserved0 [15:06] */ 15471 #define TXB_ANATXACONTROL6_RESERVED0_MASK 0xffc0 15472 #define TXB_ANATXACONTROL6_RESERVED0_ALIGN 0 15473 #define TXB_ANATXACONTROL6_RESERVED0_BITS 10 15474 #define TXB_ANATXACONTROL6_RESERVED0_SHIFT 6 15475 15476 /* TxB :: anaTxAControl6 :: sel_8b10b_default_cya [05:05] */ 15477 #define TXB_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_MASK 0x0020 15478 #define TXB_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_ALIGN 0 15479 #define TXB_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_BITS 1 15480 #define TXB_ANATXACONTROL6_SEL_8B10B_DEFAULT_CYA_SHIFT 5 15481 15482 /* TxB :: anaTxAControl6 :: ckgate_int_sel_div1_1p5_2_2p5 [04:04] */ 15483 #define TXB_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_MASK 0x0010 15484 #define TXB_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_ALIGN 0 15485 #define TXB_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_BITS 1 15486 #define TXB_ANATXACONTROL6_CKGATE_INT_SEL_DIV1_1P5_2_2P5_SHIFT 4 15487 15488 /* TxB :: anaTxAControl6 :: gloop_r [03:03] */ 15489 #define TXB_ANATXACONTROL6_GLOOP_R_MASK 0x0008 15490 #define TXB_ANATXACONTROL6_GLOOP_R_ALIGN 0 15491 #define TXB_ANATXACONTROL6_GLOOP_R_BITS 1 15492 #define TXB_ANATXACONTROL6_GLOOP_R_SHIFT 3 15493 15494 /* TxB :: anaTxAControl6 :: rloop_r [02:02] */ 15495 #define TXB_ANATXACONTROL6_RLOOP_R_MASK 0x0004 15496 #define TXB_ANATXACONTROL6_RLOOP_R_ALIGN 0 15497 #define TXB_ANATXACONTROL6_RLOOP_R_BITS 1 15498 #define TXB_ANATXACONTROL6_RLOOP_R_SHIFT 2 15499 15500 /* TxB :: anaTxAControl6 :: ckgate_ext_sel [01:01] */ 15501 #define TXB_ANATXACONTROL6_CKGATE_EXT_SEL_MASK 0x0002 15502 #define TXB_ANATXACONTROL6_CKGATE_EXT_SEL_ALIGN 0 15503 #define TXB_ANATXACONTROL6_CKGATE_EXT_SEL_BITS 1 15504 #define TXB_ANATXACONTROL6_CKGATE_EXT_SEL_SHIFT 1 15505 15506 /* TxB :: anaTxAControl6 :: disable_tx_r [00:00] */ 15507 #define TXB_ANATXACONTROL6_DISABLE_TX_R_MASK 0x0001 15508 #define TXB_ANATXACONTROL6_DISABLE_TX_R_ALIGN 0 15509 #define TXB_ANATXACONTROL6_DISABLE_TX_R_BITS 1 15510 #define TXB_ANATXACONTROL6_DISABLE_TX_R_SHIFT 0 15511 15512 15513 /**************************************************************************** 15514 * Warpcore_USER_Rx0 15515 */ 15516 /**************************************************************************** 15517 * Rx0 :: anaRxStatus 15518 */ 15519 /* union - case sigdet_Status [15:00] */ 15520 /* Rx0 :: anaRxStatus :: cx4_sigdet [15:15] */ 15521 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 15522 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 15523 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 15524 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 15525 15526 /* Rx0 :: anaRxStatus :: reserved0 [14:13] */ 15527 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 15528 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 15529 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS 2 15530 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 15531 15532 /* Rx0 :: anaRxStatus :: rxSeqDone [12:12] */ 15533 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 15534 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 15535 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 15536 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 15537 15538 /* Rx0 :: anaRxStatus :: rx_sigdet_ll [11:11] */ 15539 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 15540 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 15541 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 15542 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 15543 15544 /* Rx0 :: anaRxStatus :: cs4_sigdet_ll [10:10] */ 15545 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 15546 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 15547 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 15548 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 15549 15550 /* Rx0 :: anaRxStatus :: rx_reset [09:09] */ 15551 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 15552 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 15553 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS 1 15554 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 15555 15556 /* Rx0 :: anaRxStatus :: rx_pwrdn [08:08] */ 15557 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 15558 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 15559 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 15560 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 15561 15562 /* Rx0 :: anaRxStatus :: reserved1 [07:00] */ 15563 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 15564 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 15565 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS 8 15566 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 15567 15568 15569 /* union - case sync_Status [15:00] */ 15570 /* Rx0 :: anaRxStatus :: reserved0 [15:11] */ 15571 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 15572 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN 0 15573 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS 5 15574 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT 11 15575 15576 /* Rx0 :: anaRxStatus :: test_acq_en [10:10] */ 15577 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 15578 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 15579 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 15580 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 15581 15582 /* Rx0 :: anaRxStatus :: reserved1 [09:09] */ 15583 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 15584 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN 0 15585 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS 1 15586 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT 9 15587 15588 /* Rx0 :: anaRxStatus :: rxSeqStart [08:08] */ 15589 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 15590 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 15591 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS 1 15592 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 15593 15594 /* Rx0 :: anaRxStatus :: mux_comadj_sync_status [07:07] */ 15595 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 15596 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 15597 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 15598 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 15599 15600 /* Rx0 :: anaRxStatus :: sync_status [06:06] */ 15601 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 15602 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 15603 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 15604 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 15605 15606 /* Rx0 :: anaRxStatus :: rx_sigdet [05:05] */ 15607 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 15608 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 15609 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS 1 15610 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 15611 15612 /* Rx0 :: anaRxStatus :: reserved2 [04:03] */ 15613 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 15614 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN 0 15615 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS 2 15616 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT 3 15617 15618 /* Rx0 :: anaRxStatus :: saturate_status [02:02] */ 15619 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 15620 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 15621 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 15622 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 15623 15624 /* Rx0 :: anaRxStatus :: cx4_sigdet [01:01] */ 15625 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 15626 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 15627 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 15628 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 15629 15630 /* Rx0 :: anaRxStatus :: rxSeqDone [00:00] */ 15631 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 15632 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 15633 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS 1 15634 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 15635 15636 15637 /* union - case rxTestSel_0 [15:00] */ 15638 /* Rx0 :: anaRxStatus :: reserved0 [15:10] */ 15639 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 15640 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 15641 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS 6 15642 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 15643 15644 /* Rx0 :: anaRxStatus :: indck_mode_en [09:09] */ 15645 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 15646 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 15647 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 15648 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 15649 15650 /* Rx0 :: anaRxStatus :: pci_mode_en [08:08] */ 15651 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 15652 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 15653 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 15654 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 15655 15656 /* Rx0 :: anaRxStatus :: rx_polarity [07:07] */ 15657 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 15658 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 15659 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 15660 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 15661 15662 /* Rx0 :: anaRxStatus :: rxpol_flip [06:06] */ 15663 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 15664 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 15665 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 15666 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 15667 15668 /* Rx0 :: anaRxStatus :: comma_mask [05:05] */ 15669 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 15670 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 15671 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 15672 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 15673 15674 /* Rx0 :: anaRxStatus :: link_en_r [04:04] */ 15675 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 15676 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 15677 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 15678 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 15679 15680 /* Rx0 :: anaRxStatus :: comma_adj_en [03:03] */ 15681 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 15682 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 15683 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 15684 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 15685 15686 /* Rx0 :: anaRxStatus :: comma_adj_en_ext [02:02] */ 15687 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 15688 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 15689 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 15690 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 15691 15692 /* Rx0 :: anaRxStatus :: reserved1 [01:00] */ 15693 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 15694 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 15695 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS 2 15696 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 15697 15698 15699 /* union - case rxTestSel_1 [15:00] */ 15700 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */ 15701 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 15702 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 15703 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS 11 15704 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 15705 15706 /* Rx0 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */ 15707 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 15708 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 15709 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 15710 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 15711 15712 /* Rx0 :: anaRxStatus :: freq_sel_PC [03:03] */ 15713 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 15714 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 15715 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 15716 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 15717 15718 /* Rx0 :: anaRxStatus :: freq_sel_SM [02:02] */ 15719 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 15720 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 15721 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 15722 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 15723 15724 /* Rx0 :: anaRxStatus :: integ_mode_SM [01:00] */ 15725 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 15726 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 15727 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 15728 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 15729 15730 15731 /* union - case scale_Status [15:00] */ 15732 /* Rx0 :: anaRxStatus :: prop_scale [15:12] */ 15733 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 15734 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 15735 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS 4 15736 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 15737 15738 /* Rx0 :: anaRxStatus :: integ_scale [11:08] */ 15739 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 15740 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 15741 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 15742 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 15743 15744 /* Rx0 :: anaRxStatus :: prop_scale_acq [07:04] */ 15745 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 15746 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 15747 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 15748 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 15749 15750 /* Rx0 :: anaRxStatus :: integ_scale_acq [03:00] */ 15751 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 15752 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 15753 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 15754 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 15755 15756 15757 /* union - case adc_CdrStatus1 [15:00] */ 15758 /* Rx0 :: anaRxStatus :: reserved0 [15:07] */ 15759 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 15760 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 15761 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 15762 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 15763 15764 /* Rx0 :: anaRxStatus :: rxMuxCkSel [06:06] */ 15765 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 15766 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 15767 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 15768 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 15769 15770 /* Rx0 :: anaRxStatus :: glpbk_combo [05:05] */ 15771 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 15772 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 15773 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 15774 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 15775 15776 /* Rx0 :: anaRxStatus :: clockSwitchSel [04:04] */ 15777 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 15778 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 15779 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 15780 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 15781 15782 /* Rx0 :: anaRxStatus :: rxck_tst [03:03] */ 15783 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 15784 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 15785 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 15786 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 15787 15788 /* Rx0 :: anaRxStatus :: rxck_i [02:02] */ 15789 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 15790 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 15791 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 15792 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 15793 15794 /* Rx0 :: anaRxStatus :: refclk [01:01] */ 15795 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 15796 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 15797 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 15798 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 15799 15800 /* Rx0 :: anaRxStatus :: pll_bypass [00:00] */ 15801 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 15802 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 15803 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 15804 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 15805 15806 15807 /* union - case adc_CdrStatus2 [15:00] */ 15808 /* Rx0 :: anaRxStatus :: reserved0 [15:06] */ 15809 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 15810 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 15811 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 15812 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 15813 15814 /* Rx0 :: anaRxStatus :: rxMuxCkSel [05:05] */ 15815 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 15816 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 15817 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 15818 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 15819 15820 /* Rx0 :: anaRxStatus :: rxSeqStart [04:04] */ 15821 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 15822 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 15823 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 15824 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 15825 15826 /* Rx0 :: anaRxStatus :: reserved1 [03:01] */ 15827 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 15828 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 15829 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 15830 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 15831 15832 /* Rx0 :: anaRxStatus :: rxSeqDone [00:00] */ 15833 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 15834 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 15835 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 15836 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 15837 15838 15839 /* union - case adc_CdrStatus3 [15:00] */ 15840 /* Rx0 :: anaRxStatus :: reserved0 [15:04] */ 15841 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 15842 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 15843 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 15844 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 15845 15846 /* Rx0 :: anaRxStatus :: rxSeqStart [03:03] */ 15847 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 15848 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 15849 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 15850 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 15851 15852 /* Rx0 :: anaRxStatus :: reserved1 [02:01] */ 15853 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 15854 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 15855 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 15856 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 15857 15858 /* Rx0 :: anaRxStatus :: allow_increment_PC [00:00] */ 15859 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 15860 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 15861 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 15862 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 15863 15864 15865 /* union - case adc_CdrStatus4 [15:00] */ 15866 /* Rx0 :: anaRxStatus :: reserved0 [15:08] */ 15867 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 15868 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 15869 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 15870 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 15871 15872 /* Rx0 :: anaRxStatus :: rx_pwrdn [07:07] */ 15873 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 15874 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 15875 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 15876 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 15877 15878 /* Rx0 :: anaRxStatus :: freq_sel [06:06] */ 15879 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 15880 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 15881 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 15882 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 15883 15884 /* Rx0 :: anaRxStatus :: pll_lock_rstb [05:05] */ 15885 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 15886 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 15887 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 15888 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 15889 15890 /* Rx0 :: anaRxStatus :: pwrdn [04:04] */ 15891 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 15892 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 15893 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 15894 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 15895 15896 /* Rx0 :: anaRxStatus :: reserved1 [03:00] */ 15897 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 15898 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 15899 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 15900 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 15901 15902 15903 /* union - case adc_CdrStatus5 [15:00] */ 15904 /* Rx0 :: anaRxStatus :: reserved0 [15:00] */ 15905 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 15906 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 15907 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 15908 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 15909 15910 15911 /* union - case adc_CdrStatus6 [15:00] */ 15912 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */ 15913 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 15914 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 15915 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 15916 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 15917 15918 /* Rx0 :: anaRxStatus :: rx_reset [04:04] */ 15919 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 15920 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 15921 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 15922 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 15923 15924 /* Rx0 :: anaRxStatus :: rx_pwrdn [03:03] */ 15925 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 15926 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 15927 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 15928 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 15929 15930 /* Rx0 :: anaRxStatus :: reset_anlg [02:02] */ 15931 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 15932 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 15933 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 15934 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 15935 15936 /* Rx0 :: anaRxStatus :: pwrdn_rx [01:01] */ 15937 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 15938 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 15939 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 15940 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 15941 15942 /* Rx0 :: anaRxStatus :: pwrdn_pll [00:00] */ 15943 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 15944 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 15945 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 15946 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 15947 15948 15949 /* union - case adc_CdrStatus7e [15:00] */ 15950 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */ 15951 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 15952 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 15953 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 15954 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 15955 15956 /* Rx0 :: anaRxStatus :: rxck0_even [04:04] */ 15957 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 15958 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 15959 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 15960 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 15961 15962 /* Rx0 :: anaRxStatus :: rxck1_even [03:03] */ 15963 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 15964 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 15965 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 15966 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 15967 15968 /* Rx0 :: anaRxStatus :: comdet_even [02:02] */ 15969 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 15970 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 15971 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 15972 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 15973 15974 /* Rx0 :: anaRxStatus :: en_cdet_even [01:01] */ 15975 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 15976 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 15977 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 15978 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 15979 15980 /* Rx0 :: anaRxStatus :: comma_adj_en_even [00:00] */ 15981 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 15982 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 15983 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 15984 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 15985 15986 15987 /* union - case adc_CdrStatus7o [15:00] */ 15988 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */ 15989 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 15990 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 15991 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 15992 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 15993 15994 /* Rx0 :: anaRxStatus :: rxck0_odd [04:04] */ 15995 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 15996 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 15997 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 15998 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 15999 16000 /* Rx0 :: anaRxStatus :: rxck1_odd [03:03] */ 16001 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 16002 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 16003 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 16004 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 16005 16006 /* Rx0 :: anaRxStatus :: comdet_odd [02:02] */ 16007 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 16008 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 16009 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 16010 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 16011 16012 /* Rx0 :: anaRxStatus :: en_cdet_odd [01:01] */ 16013 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 16014 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 16015 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 16016 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 16017 16018 /* Rx0 :: anaRxStatus :: comma_adj_en_odd [00:00] */ 16019 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 16020 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 16021 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 16022 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 16023 16024 16025 /* union - case adc_CdrStatus8 [15:00] */ 16026 /* Rx0 :: anaRxStatus :: reserved0 [15:01] */ 16027 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 16028 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 16029 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 16030 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 16031 16032 /* Rx0 :: anaRxStatus :: sigdet [00:00] */ 16033 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 16034 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 16035 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 16036 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 16037 16038 16039 /* union - case adc_CdrStatus9 [15:00] */ 16040 /* Rx0 :: anaRxStatus :: reserved0 [15:00] */ 16041 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 16042 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 16043 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 16044 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 16045 16046 16047 /* union - case adc_CdrStatus10 [15:00] */ 16048 /* Rx0 :: anaRxStatus :: reserved0 [15:07] */ 16049 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 16050 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 16051 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 16052 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 16053 16054 /* Rx0 :: anaRxStatus :: prbs_en [06:06] */ 16055 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 16056 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 16057 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 16058 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 16059 16060 /* Rx0 :: anaRxStatus :: rstb_tst [05:05] */ 16061 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 16062 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 16063 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 16064 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 16065 16066 /* Rx0 :: anaRxStatus :: reserved1 [04:04] */ 16067 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 16068 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 16069 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 16070 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 16071 16072 /* Rx0 :: anaRxStatus :: prbs_state [03:00] */ 16073 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 16074 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 16075 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 16076 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 16077 16078 16079 /* union - case adc_CdrStatus11 [15:00] */ 16080 /* Rx0 :: anaRxStatus :: reserved0 [15:00] */ 16081 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 16082 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 16083 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 16084 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 16085 16086 16087 /* union - case adc_CdrStatus12_1 [15:00] */ 16088 /* Rx0 :: anaRxStatus :: reserved0 [15:06] */ 16089 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 16090 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 16091 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 16092 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 16093 16094 /* Rx0 :: anaRxStatus :: enable4 [05:05] */ 16095 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 16096 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 16097 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 16098 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 16099 16100 /* Rx0 :: anaRxStatus :: radr_test [04:00] */ 16101 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 16102 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 16103 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 16104 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 16105 16106 16107 /* union - case adc_CdrStatus12_2 [15:00] */ 16108 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */ 16109 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 16110 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 16111 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 16112 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 16113 16114 /* Rx0 :: anaRxStatus :: wadr_test [04:00] */ 16115 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 16116 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 16117 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 16118 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 16119 16120 16121 /* union - case adc_CdrStatus12_3 [15:00] */ 16122 /* Rx0 :: anaRxStatus :: reserved0 [15:06] */ 16123 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 16124 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 16125 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 16126 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 16127 16128 /* Rx0 :: anaRxStatus :: rxck_66B_tmux [05:05] */ 16129 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 16130 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 16131 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 16132 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 16133 16134 /* Rx0 :: anaRxStatus :: rstb_66B [04:04] */ 16135 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 16136 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 16137 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 16138 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 16139 16140 /* Rx0 :: anaRxStatus :: prstb_66B_mux [03:03] */ 16141 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 16142 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 16143 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 16144 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 16145 16146 /* Rx0 :: anaRxStatus :: rxck_i66_tmux [02:02] */ 16147 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 16148 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 16149 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 16150 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 16151 16152 /* Rx0 :: anaRxStatus :: rstb_i66 [01:01] */ 16153 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 16154 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 16155 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 16156 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 16157 16158 /* Rx0 :: anaRxStatus :: prstb_i66_mux [00:00] */ 16159 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 16160 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 16161 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 16162 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 16163 16164 16165 /* union - case adc_CdrStatus12_4 [15:00] */ 16166 /* Rx0 :: anaRxStatus :: reserved0 [15:04] */ 16167 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 16168 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 16169 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 16170 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 16171 16172 /* Rx0 :: anaRxStatus :: rfifo_error_r [03:02] */ 16173 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 16174 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 16175 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 16176 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 16177 16178 /* Rx0 :: anaRxStatus :: rfifo_unflow [01:01] */ 16179 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 16180 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 16181 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 16182 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 16183 16184 /* Rx0 :: anaRxStatus :: rfifo_ovflow [00:00] */ 16185 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 16186 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 16187 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 16188 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 16189 16190 16191 /* union - case integ_Status [15:00] */ 16192 /* Rx0 :: anaRxStatus :: integ_status [15:00] */ 16193 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 16194 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 16195 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 16196 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 16197 16198 16199 /* union - case vco_Status [15:00] */ 16200 /* Rx0 :: anaRxStatus :: vco_status [15:00] */ 16201 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 16202 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 16203 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS 16 16204 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 16205 16206 16207 /* union - case prbs_Status [15:00] */ 16208 /* Rx0 :: anaRxStatus :: prbs_lock [15:15] */ 16209 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 16210 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 16211 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 16212 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 16213 16214 /* Rx0 :: anaRxStatus :: prbs_stky [14:14] */ 16215 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 16216 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 16217 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS 1 16218 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 16219 16220 /* Rx0 :: anaRxStatus :: prbs_errors [13:00] */ 16221 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_MASK 0x3fff 16222 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_ALIGN 0 16223 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_BITS 14 16224 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_SHIFT 0 16225 16226 16227 16228 /**************************************************************************** 16229 * Rx0 :: anaRxControl 16230 */ 16231 /* Rx0 :: anaRxControl :: reserved0 [15:10] */ 16232 #define RX0_ANARXCONTROL_RESERVED0_MASK 0xfc00 16233 #define RX0_ANARXCONTROL_RESERVED0_ALIGN 0 16234 #define RX0_ANARXCONTROL_RESERVED0_BITS 6 16235 #define RX0_ANARXCONTROL_RESERVED0_SHIFT 10 16236 16237 /* Rx0 :: anaRxControl :: override_sigdet_en [09:09] */ 16238 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 16239 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 16240 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 16241 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 16242 16243 /* Rx0 :: anaRxControl :: override_sigdet_val [08:08] */ 16244 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 16245 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 16246 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 16247 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 16248 16249 /* Rx0 :: anaRxControl :: reserved1 [07:03] */ 16250 #define RX0_ANARXCONTROL_RESERVED1_MASK 0x00f8 16251 #define RX0_ANARXCONTROL_RESERVED1_ALIGN 0 16252 #define RX0_ANARXCONTROL_RESERVED1_BITS 5 16253 #define RX0_ANARXCONTROL_RESERVED1_SHIFT 3 16254 16255 /* Rx0 :: anaRxControl :: status_sel [02:00] */ 16256 #define RX0_ANARXCONTROL_STATUS_SEL_MASK 0x0007 16257 #define RX0_ANARXCONTROL_STATUS_SEL_ALIGN 0 16258 #define RX0_ANARXCONTROL_STATUS_SEL_BITS 3 16259 #define RX0_ANARXCONTROL_STATUS_SEL_SHIFT 0 16260 #define RX0_ANARXCONTROL_STATUS_SEL_sigdetStatus 0 16261 #define RX0_ANARXCONTROL_STATUS_SEL_syncStatus 1 16262 #define RX0_ANARXCONTROL_STATUS_SEL_rxTestSel 2 16263 #define RX0_ANARXCONTROL_STATUS_SEL_scaleStatus 3 16264 #define RX0_ANARXCONTROL_STATUS_SEL_adcCdrStatus 4 16265 #define RX0_ANARXCONTROL_STATUS_SEL_integStatus 5 16266 #define RX0_ANARXCONTROL_STATUS_SEL_vcoStatus 6 16267 #define RX0_ANARXCONTROL_STATUS_SEL_prbsStatus 7 16268 16269 16270 /**************************************************************************** 16271 * Rx0 :: anaRxSigdet 16272 */ 16273 /* Rx0 :: anaRxSigdet :: sigdetTime_SM [15:08] */ 16274 #define RX0_ANARXSIGDET_SIGDETTIME_SM_MASK 0xff00 16275 #define RX0_ANARXSIGDET_SIGDETTIME_SM_ALIGN 0 16276 #define RX0_ANARXSIGDET_SIGDETTIME_SM_BITS 8 16277 #define RX0_ANARXSIGDET_SIGDETTIME_SM_SHIFT 8 16278 16279 /* Rx0 :: anaRxSigdet :: cx4_sigdet_cnt_ld_SM [07:07] */ 16280 #define RX0_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_MASK 0x0080 16281 #define RX0_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_ALIGN 0 16282 #define RX0_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_BITS 1 16283 #define RX0_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_SHIFT 7 16284 16285 /* Rx0 :: anaRxSigdet :: ext_sigdet_en_SM [06:06] */ 16286 #define RX0_ANARXSIGDET_EXT_SIGDET_EN_SM_MASK 0x0040 16287 #define RX0_ANARXSIGDET_EXT_SIGDET_EN_SM_ALIGN 0 16288 #define RX0_ANARXSIGDET_EXT_SIGDET_EN_SM_BITS 1 16289 #define RX0_ANARXSIGDET_EXT_SIGDET_EN_SM_SHIFT 6 16290 16291 /* Rx0 :: anaRxSigdet :: cx4_sigdet_en_SM [05:05] */ 16292 #define RX0_ANARXSIGDET_CX4_SIGDET_EN_SM_MASK 0x0020 16293 #define RX0_ANARXSIGDET_CX4_SIGDET_EN_SM_ALIGN 0 16294 #define RX0_ANARXSIGDET_CX4_SIGDET_EN_SM_BITS 1 16295 #define RX0_ANARXSIGDET_CX4_SIGDET_EN_SM_SHIFT 5 16296 16297 /* Rx0 :: anaRxSigdet :: rx_sigdet_r [04:04] */ 16298 #define RX0_ANARXSIGDET_RX_SIGDET_R_MASK 0x0010 16299 #define RX0_ANARXSIGDET_RX_SIGDET_R_ALIGN 0 16300 #define RX0_ANARXSIGDET_RX_SIGDET_R_BITS 1 16301 #define RX0_ANARXSIGDET_RX_SIGDET_R_SHIFT 4 16302 16303 /* Rx0 :: anaRxSigdet :: rx_sigdet_force_r [03:03] */ 16304 #define RX0_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK 0x0008 16305 #define RX0_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN 0 16306 #define RX0_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS 1 16307 #define RX0_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT 3 16308 16309 /* Rx0 :: anaRxSigdet :: invert_rx_sigdet [02:02] */ 16310 #define RX0_ANARXSIGDET_INVERT_RX_SIGDET_MASK 0x0004 16311 #define RX0_ANARXSIGDET_INVERT_RX_SIGDET_ALIGN 0 16312 #define RX0_ANARXSIGDET_INVERT_RX_SIGDET_BITS 1 16313 #define RX0_ANARXSIGDET_INVERT_RX_SIGDET_SHIFT 2 16314 16315 /* Rx0 :: anaRxSigdet :: reserved0 [01:00] */ 16316 #define RX0_ANARXSIGDET_RESERVED0_MASK 0x0003 16317 #define RX0_ANARXSIGDET_RESERVED0_ALIGN 0 16318 #define RX0_ANARXSIGDET_RESERVED0_BITS 2 16319 #define RX0_ANARXSIGDET_RESERVED0_SHIFT 0 16320 16321 16322 /**************************************************************************** 16323 * Rx0 :: anaRxAControl4 16324 */ 16325 /* Rx0 :: anaRxAControl4 :: ana_clt4 [15:00] */ 16326 #define RX0_ANARXACONTROL4_ANA_CLT4_MASK 0xffff 16327 #define RX0_ANARXACONTROL4_ANA_CLT4_ALIGN 0 16328 #define RX0_ANARXACONTROL4_ANA_CLT4_BITS 16 16329 #define RX0_ANARXACONTROL4_ANA_CLT4_SHIFT 0 16330 16331 16332 /**************************************************************************** 16333 * Rx0 :: anaRxControl2_1G 16334 */ 16335 /* Rx0 :: anaRxControl2_1G :: reserved0 [15:15] */ 16336 #define RX0_ANARXCONTROL2_1G_RESERVED0_MASK 0x8000 16337 #define RX0_ANARXCONTROL2_1G_RESERVED0_ALIGN 0 16338 #define RX0_ANARXCONTROL2_1G_RESERVED0_BITS 1 16339 #define RX0_ANARXCONTROL2_1G_RESERVED0_SHIFT 15 16340 16341 /* Rx0 :: anaRxControl2_1G :: rx_prbs_w_val [14:14] */ 16342 #define RX0_ANARXCONTROL2_1G_RX_PRBS_W_VAL_MASK 0x4000 16343 #define RX0_ANARXCONTROL2_1G_RX_PRBS_W_VAL_ALIGN 0 16344 #define RX0_ANARXCONTROL2_1G_RX_PRBS_W_VAL_BITS 1 16345 #define RX0_ANARXCONTROL2_1G_RX_PRBS_W_VAL_SHIFT 14 16346 16347 /* Rx0 :: anaRxControl2_1G :: rx_prbs_w_force [13:13] */ 16348 #define RX0_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_MASK 0x2000 16349 #define RX0_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_ALIGN 0 16350 #define RX0_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_BITS 1 16351 #define RX0_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_SHIFT 13 16352 16353 /* Rx0 :: anaRxControl2_1G :: rx_prbs_bswap [12:12] */ 16354 #define RX0_ANARXCONTROL2_1G_RX_PRBS_BSWAP_MASK 0x1000 16355 #define RX0_ANARXCONTROL2_1G_RX_PRBS_BSWAP_ALIGN 0 16356 #define RX0_ANARXCONTROL2_1G_RX_PRBS_BSWAP_BITS 1 16357 #define RX0_ANARXCONTROL2_1G_RX_PRBS_BSWAP_SHIFT 12 16358 16359 /* Rx0 :: anaRxControl2_1G :: rx_bitswap [11:11] */ 16360 #define RX0_ANARXCONTROL2_1G_RX_BITSWAP_MASK 0x0800 16361 #define RX0_ANARXCONTROL2_1G_RX_BITSWAP_ALIGN 0 16362 #define RX0_ANARXCONTROL2_1G_RX_BITSWAP_BITS 1 16363 #define RX0_ANARXCONTROL2_1G_RX_BITSWAP_SHIFT 11 16364 16365 /* Rx0 :: anaRxControl2_1G :: rst_rx_r [10:10] */ 16366 #define RX0_ANARXCONTROL2_1G_RST_RX_R_MASK 0x0400 16367 #define RX0_ANARXCONTROL2_1G_RST_RX_R_ALIGN 0 16368 #define RX0_ANARXCONTROL2_1G_RST_RX_R_BITS 1 16369 #define RX0_ANARXCONTROL2_1G_RST_RX_R_SHIFT 10 16370 16371 /* Rx0 :: anaRxControl2_1G :: pwdwn_rx_r [09:09] */ 16372 #define RX0_ANARXCONTROL2_1G_PWDWN_RX_R_MASK 0x0200 16373 #define RX0_ANARXCONTROL2_1G_PWDWN_RX_R_ALIGN 0 16374 #define RX0_ANARXCONTROL2_1G_PWDWN_RX_R_BITS 1 16375 #define RX0_ANARXCONTROL2_1G_PWDWN_RX_R_SHIFT 9 16376 16377 /* Rx0 :: anaRxControl2_1G :: prbs_order_rx_r_2 [08:08] */ 16378 #define RX0_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_MASK 0x0100 16379 #define RX0_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_ALIGN 0 16380 #define RX0_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_BITS 1 16381 #define RX0_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_SHIFT 8 16382 16383 /* Rx0 :: anaRxControl2_1G :: reserved1 [07:07] */ 16384 #define RX0_ANARXCONTROL2_1G_RESERVED1_MASK 0x0080 16385 #define RX0_ANARXCONTROL2_1G_RESERVED1_ALIGN 0 16386 #define RX0_ANARXCONTROL2_1G_RESERVED1_BITS 1 16387 #define RX0_ANARXCONTROL2_1G_RESERVED1_SHIFT 7 16388 16389 /* Rx0 :: anaRxControl2_1G :: prbs_sel_rx_r [06:06] */ 16390 #define RX0_ANARXCONTROL2_1G_PRBS_SEL_RX_R_MASK 0x0040 16391 #define RX0_ANARXCONTROL2_1G_PRBS_SEL_RX_R_ALIGN 0 16392 #define RX0_ANARXCONTROL2_1G_PRBS_SEL_RX_R_BITS 1 16393 #define RX0_ANARXCONTROL2_1G_PRBS_SEL_RX_R_SHIFT 6 16394 16395 /* Rx0 :: anaRxControl2_1G :: prbs_en_rx_r [05:05] */ 16396 #define RX0_ANARXCONTROL2_1G_PRBS_EN_RX_R_MASK 0x0020 16397 #define RX0_ANARXCONTROL2_1G_PRBS_EN_RX_R_ALIGN 0 16398 #define RX0_ANARXCONTROL2_1G_PRBS_EN_RX_R_BITS 1 16399 #define RX0_ANARXCONTROL2_1G_PRBS_EN_RX_R_SHIFT 5 16400 16401 /* Rx0 :: anaRxControl2_1G :: prbs_inv_rx_r [04:04] */ 16402 #define RX0_ANARXCONTROL2_1G_PRBS_INV_RX_R_MASK 0x0010 16403 #define RX0_ANARXCONTROL2_1G_PRBS_INV_RX_R_ALIGN 0 16404 #define RX0_ANARXCONTROL2_1G_PRBS_INV_RX_R_BITS 1 16405 #define RX0_ANARXCONTROL2_1G_PRBS_INV_RX_R_SHIFT 4 16406 16407 /* Rx0 :: anaRxControl2_1G :: prbs_order_rx_r [03:02] */ 16408 #define RX0_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_MASK 0x000c 16409 #define RX0_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_ALIGN 0 16410 #define RX0_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_BITS 2 16411 #define RX0_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_SHIFT 2 16412 16413 /* Rx0 :: anaRxControl2_1G :: reserved2 [01:01] */ 16414 #define RX0_ANARXCONTROL2_1G_RESERVED2_MASK 0x0002 16415 #define RX0_ANARXCONTROL2_1G_RESERVED2_ALIGN 0 16416 #define RX0_ANARXCONTROL2_1G_RESERVED2_BITS 1 16417 #define RX0_ANARXCONTROL2_1G_RESERVED2_SHIFT 1 16418 16419 /* Rx0 :: anaRxControl2_1G :: errcnt_15 [00:00] */ 16420 #define RX0_ANARXCONTROL2_1G_ERRCNT_15_MASK 0x0001 16421 #define RX0_ANARXCONTROL2_1G_ERRCNT_15_ALIGN 0 16422 #define RX0_ANARXCONTROL2_1G_ERRCNT_15_BITS 1 16423 #define RX0_ANARXCONTROL2_1G_ERRCNT_15_SHIFT 0 16424 16425 16426 /**************************************************************************** 16427 * Rx0 :: anaRxTest 16428 */ 16429 /* Rx0 :: anaRxTest :: sigdet_mux_SM [15:12] */ 16430 #define RX0_ANARXTEST_SIGDET_MUX_SM_MASK 0xf000 16431 #define RX0_ANARXTEST_SIGDET_MUX_SM_ALIGN 0 16432 #define RX0_ANARXTEST_SIGDET_MUX_SM_BITS 4 16433 #define RX0_ANARXTEST_SIGDET_MUX_SM_SHIFT 12 16434 16435 /* Rx0 :: anaRxTest :: reserved0 [11:09] */ 16436 #define RX0_ANARXTEST_RESERVED0_MASK 0x0e00 16437 #define RX0_ANARXTEST_RESERVED0_ALIGN 0 16438 #define RX0_ANARXTEST_RESERVED0_BITS 3 16439 #define RX0_ANARXTEST_RESERVED0_SHIFT 9 16440 16441 /* Rx0 :: anaRxTest :: tpctrl_SM [08:04] */ 16442 #define RX0_ANARXTEST_TPCTRL_SM_MASK 0x01f0 16443 #define RX0_ANARXTEST_TPCTRL_SM_ALIGN 0 16444 #define RX0_ANARXTEST_TPCTRL_SM_BITS 5 16445 #define RX0_ANARXTEST_TPCTRL_SM_SHIFT 4 16446 16447 /* Rx0 :: anaRxTest :: testMuxSelect_SM [03:00] */ 16448 #define RX0_ANARXTEST_TESTMUXSELECT_SM_MASK 0x000f 16449 #define RX0_ANARXTEST_TESTMUXSELECT_SM_ALIGN 0 16450 #define RX0_ANARXTEST_TESTMUXSELECT_SM_BITS 4 16451 #define RX0_ANARXTEST_TESTMUXSELECT_SM_SHIFT 0 16452 16453 16454 /**************************************************************************** 16455 * Rx0 :: anaRxControl1G 16456 */ 16457 /* Rx0 :: anaRxControl1G :: fpat_md [15:15] */ 16458 #define RX0_ANARXCONTROL1G_FPAT_MD_MASK 0x8000 16459 #define RX0_ANARXCONTROL1G_FPAT_MD_ALIGN 0 16460 #define RX0_ANARXCONTROL1G_FPAT_MD_BITS 1 16461 #define RX0_ANARXCONTROL1G_FPAT_MD_SHIFT 15 16462 16463 /* Rx0 :: anaRxControl1G :: pkt_count_en [14:14] */ 16464 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_MASK 0x4000 16465 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN 0 16466 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_BITS 1 16467 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT 14 16468 16469 /* Rx0 :: anaRxControl1G :: staMuxRegDis [13:13] */ 16470 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_MASK 0x2000 16471 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_ALIGN 0 16472 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_BITS 1 16473 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_SHIFT 13 16474 16475 /* Rx0 :: anaRxControl1G :: prbs_clr_dis [12:12] */ 16476 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_MASK 0x1000 16477 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN 0 16478 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_BITS 1 16479 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT 12 16480 16481 /* Rx0 :: anaRxControl1G :: rxd_dec_sel [11:11] */ 16482 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_MASK 0x0800 16483 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN 0 16484 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_BITS 1 16485 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT 11 16486 16487 /* Rx0 :: anaRxControl1G :: cgbad_tst [10:10] */ 16488 #define RX0_ANARXCONTROL1G_CGBAD_TST_MASK 0x0400 16489 #define RX0_ANARXCONTROL1G_CGBAD_TST_ALIGN 0 16490 #define RX0_ANARXCONTROL1G_CGBAD_TST_BITS 1 16491 #define RX0_ANARXCONTROL1G_CGBAD_TST_SHIFT 10 16492 16493 /* Rx0 :: anaRxControl1G :: Emon_en [09:09] */ 16494 #define RX0_ANARXCONTROL1G_EMON_EN_MASK 0x0200 16495 #define RX0_ANARXCONTROL1G_EMON_EN_ALIGN 0 16496 #define RX0_ANARXCONTROL1G_EMON_EN_BITS 1 16497 #define RX0_ANARXCONTROL1G_EMON_EN_SHIFT 9 16498 16499 /* Rx0 :: anaRxControl1G :: prbs_en [08:08] */ 16500 #define RX0_ANARXCONTROL1G_PRBS_EN_MASK 0x0100 16501 #define RX0_ANARXCONTROL1G_PRBS_EN_ALIGN 0 16502 #define RX0_ANARXCONTROL1G_PRBS_EN_BITS 1 16503 #define RX0_ANARXCONTROL1G_PRBS_EN_SHIFT 8 16504 16505 /* Rx0 :: anaRxControl1G :: cgbad_en [07:07] */ 16506 #define RX0_ANARXCONTROL1G_CGBAD_EN_MASK 0x0080 16507 #define RX0_ANARXCONTROL1G_CGBAD_EN_ALIGN 0 16508 #define RX0_ANARXCONTROL1G_CGBAD_EN_BITS 1 16509 #define RX0_ANARXCONTROL1G_CGBAD_EN_SHIFT 7 16510 16511 /* Rx0 :: anaRxControl1G :: cstretch [06:06] */ 16512 #define RX0_ANARXCONTROL1G_CSTRETCH_MASK 0x0040 16513 #define RX0_ANARXCONTROL1G_CSTRETCH_ALIGN 0 16514 #define RX0_ANARXCONTROL1G_CSTRETCH_BITS 1 16515 #define RX0_ANARXCONTROL1G_CSTRETCH_SHIFT 6 16516 16517 /* Rx0 :: anaRxControl1G :: comma_low_byte_SM [05:05] */ 16518 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK 0x0020 16519 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN 0 16520 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS 1 16521 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT 5 16522 16523 /* Rx0 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */ 16524 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 16525 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 16526 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS 1 16527 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 16528 16529 /* Rx0 :: anaRxControl1G :: reserved0 [03:02] */ 16530 #define RX0_ANARXCONTROL1G_RESERVED0_MASK 0x000c 16531 #define RX0_ANARXCONTROL1G_RESERVED0_ALIGN 0 16532 #define RX0_ANARXCONTROL1G_RESERVED0_BITS 2 16533 #define RX0_ANARXCONTROL1G_RESERVED0_SHIFT 2 16534 16535 /* Rx0 :: anaRxControl1G :: freq_sel_force [01:01] */ 16536 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK 0x0002 16537 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN 0 16538 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS 1 16539 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT 1 16540 16541 /* Rx0 :: anaRxControl1G :: freq_sel [00:00] */ 16542 #define RX0_ANARXCONTROL1G_FREQ_SEL_MASK 0x0001 16543 #define RX0_ANARXCONTROL1G_FREQ_SEL_ALIGN 0 16544 #define RX0_ANARXCONTROL1G_FREQ_SEL_BITS 1 16545 #define RX0_ANARXCONTROL1G_FREQ_SEL_SHIFT 0 16546 16547 16548 /**************************************************************************** 16549 * Rx0 :: anaRxControlPci 16550 */ 16551 /* Rx0 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */ 16552 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK 0x8000 16553 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN 0 16554 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS 1 16555 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT 15 16556 16557 /* Rx0 :: anaRxControlPci :: comma_mask_force_r [14:14] */ 16558 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK 0x4000 16559 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN 0 16560 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS 1 16561 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT 14 16562 16563 /* Rx0 :: anaRxControlPci :: comma_mask_r [13:13] */ 16564 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_MASK 0x2000 16565 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN 0 16566 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_BITS 1 16567 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT 13 16568 16569 /* Rx0 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */ 16570 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000 16571 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0 16572 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1 16573 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12 16574 16575 /* Rx0 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */ 16576 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK 0x0800 16577 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0 16578 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS 1 16579 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11 16580 16581 /* Rx0 :: anaRxControlPci :: sync_status_force_r [10:10] */ 16582 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK 0x0400 16583 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN 0 16584 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS 1 16585 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT 10 16586 16587 /* Rx0 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */ 16588 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200 16589 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0 16590 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1 16591 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9 16592 16593 /* Rx0 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */ 16594 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100 16595 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0 16596 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1 16597 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8 16598 16599 /* Rx0 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */ 16600 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080 16601 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0 16602 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1 16603 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7 16604 16605 /* Rx0 :: anaRxControlPci :: comma_adj_en_r [06:06] */ 16606 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK 0x0040 16607 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN 0 16608 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS 1 16609 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT 6 16610 16611 /* Rx0 :: anaRxControlPci :: link_en_force_SM [05:05] */ 16612 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK 0x0020 16613 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN 0 16614 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS 1 16615 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT 5 16616 16617 /* Rx0 :: anaRxControlPci :: link_en_r [04:04] */ 16618 #define RX0_ANARXCONTROLPCI_LINK_EN_R_MASK 0x0010 16619 #define RX0_ANARXCONTROLPCI_LINK_EN_R_ALIGN 0 16620 #define RX0_ANARXCONTROLPCI_LINK_EN_R_BITS 1 16621 #define RX0_ANARXCONTROLPCI_LINK_EN_R_SHIFT 4 16622 16623 /* Rx0 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */ 16624 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK 0x0008 16625 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN 0 16626 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS 1 16627 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT 3 16628 16629 /* Rx0 :: anaRxControlPci :: rx_polarity_r [02:02] */ 16630 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_MASK 0x0004 16631 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN 0 16632 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_BITS 1 16633 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT 2 16634 16635 /* Rx0 :: anaRxControlPci :: integ_mode_SM [01:00] */ 16636 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_MASK 0x0003 16637 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN 0 16638 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_BITS 2 16639 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT 0 16640 16641 16642 /**************************************************************************** 16643 * Rx0 :: anaRxAstatus 16644 */ 16645 /* Rx0 :: anaRxAstatus :: sigdet [15:15] */ 16646 #define RX0_ANARXASTATUS_SIGDET_MASK 0x8000 16647 #define RX0_ANARXASTATUS_SIGDET_ALIGN 0 16648 #define RX0_ANARXASTATUS_SIGDET_BITS 1 16649 #define RX0_ANARXASTATUS_SIGDET_SHIFT 15 16650 16651 /* Rx0 :: anaRxAstatus :: rx_pf [14:11] */ 16652 #define RX0_ANARXASTATUS_RX_PF_MASK 0x7800 16653 #define RX0_ANARXASTATUS_RX_PF_ALIGN 0 16654 #define RX0_ANARXASTATUS_RX_PF_BITS 4 16655 #define RX0_ANARXASTATUS_RX_PF_SHIFT 11 16656 16657 /* Rx0 :: anaRxAstatus :: tap1_dfe_gray [10:05] */ 16658 #define RX0_ANARXASTATUS_TAP1_DFE_GRAY_MASK 0x07e0 16659 #define RX0_ANARXASTATUS_TAP1_DFE_GRAY_ALIGN 0 16660 #define RX0_ANARXASTATUS_TAP1_DFE_GRAY_BITS 6 16661 #define RX0_ANARXASTATUS_TAP1_DFE_GRAY_SHIFT 5 16662 16663 /* Rx0 :: anaRxAstatus :: vga [04:00] */ 16664 #define RX0_ANARXASTATUS_VGA_MASK 0x001f 16665 #define RX0_ANARXASTATUS_VGA_ALIGN 0 16666 #define RX0_ANARXASTATUS_VGA_BITS 5 16667 #define RX0_ANARXASTATUS_VGA_SHIFT 0 16668 16669 16670 /**************************************************************************** 16671 * Rx0 :: anaRxAControl1 16672 */ 16673 /* Rx0 :: anaRxAControl1 :: imode_vcm [15:15] */ 16674 #define RX0_ANARXACONTROL1_IMODE_VCM_MASK 0x8000 16675 #define RX0_ANARXACONTROL1_IMODE_VCM_ALIGN 0 16676 #define RX0_ANARXACONTROL1_IMODE_VCM_BITS 1 16677 #define RX0_ANARXACONTROL1_IMODE_VCM_SHIFT 15 16678 16679 /* Rx0 :: anaRxAControl1 :: imin_vcm [14:14] */ 16680 #define RX0_ANARXACONTROL1_IMIN_VCM_MASK 0x4000 16681 #define RX0_ANARXACONTROL1_IMIN_VCM_ALIGN 0 16682 #define RX0_ANARXACONTROL1_IMIN_VCM_BITS 1 16683 #define RX0_ANARXACONTROL1_IMIN_VCM_SHIFT 14 16684 16685 /* Rx0 :: anaRxAControl1 :: imax_sigdet [13:13] */ 16686 #define RX0_ANARXACONTROL1_IMAX_SIGDET_MASK 0x2000 16687 #define RX0_ANARXACONTROL1_IMAX_SIGDET_ALIGN 0 16688 #define RX0_ANARXACONTROL1_IMAX_SIGDET_BITS 1 16689 #define RX0_ANARXACONTROL1_IMAX_SIGDET_SHIFT 13 16690 16691 /* Rx0 :: anaRxAControl1 :: imode_sigdet [12:12] */ 16692 #define RX0_ANARXACONTROL1_IMODE_SIGDET_MASK 0x1000 16693 #define RX0_ANARXACONTROL1_IMODE_SIGDET_ALIGN 0 16694 #define RX0_ANARXACONTROL1_IMODE_SIGDET_BITS 1 16695 #define RX0_ANARXACONTROL1_IMODE_SIGDET_SHIFT 12 16696 16697 /* Rx0 :: anaRxAControl1 :: imin_sigdet [11:11] */ 16698 #define RX0_ANARXACONTROL1_IMIN_SIGDET_MASK 0x0800 16699 #define RX0_ANARXACONTROL1_IMIN_SIGDET_ALIGN 0 16700 #define RX0_ANARXACONTROL1_IMIN_SIGDET_BITS 1 16701 #define RX0_ANARXACONTROL1_IMIN_SIGDET_SHIFT 11 16702 16703 /* Rx0 :: anaRxAControl1 :: refh_rx [10:10] */ 16704 #define RX0_ANARXACONTROL1_REFH_RX_MASK 0x0400 16705 #define RX0_ANARXACONTROL1_REFH_RX_ALIGN 0 16706 #define RX0_ANARXACONTROL1_REFH_RX_BITS 1 16707 #define RX0_ANARXACONTROL1_REFH_RX_SHIFT 10 16708 16709 /* Rx0 :: anaRxAControl1 :: refl_rx [09:09] */ 16710 #define RX0_ANARXACONTROL1_REFL_RX_MASK 0x0200 16711 #define RX0_ANARXACONTROL1_REFL_RX_ALIGN 0 16712 #define RX0_ANARXACONTROL1_REFL_RX_BITS 1 16713 #define RX0_ANARXACONTROL1_REFL_RX_SHIFT 9 16714 16715 /* Rx0 :: anaRxAControl1 :: tport_en [08:08] */ 16716 #define RX0_ANARXACONTROL1_TPORT_EN_MASK 0x0100 16717 #define RX0_ANARXACONTROL1_TPORT_EN_ALIGN 0 16718 #define RX0_ANARXACONTROL1_TPORT_EN_BITS 1 16719 #define RX0_ANARXACONTROL1_TPORT_EN_SHIFT 8 16720 16721 /* Rx0 :: anaRxAControl1 :: vddrb_bgb [07:07] */ 16722 #define RX0_ANARXACONTROL1_VDDRB_BGB_MASK 0x0080 16723 #define RX0_ANARXACONTROL1_VDDRB_BGB_ALIGN 0 16724 #define RX0_ANARXACONTROL1_VDDRB_BGB_BITS 1 16725 #define RX0_ANARXACONTROL1_VDDRB_BGB_SHIFT 7 16726 16727 /* Rx0 :: anaRxAControl1 :: sig_pwrdn [06:06] */ 16728 #define RX0_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 16729 #define RX0_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 16730 #define RX0_ANARXACONTROL1_SIG_PWRDN_BITS 1 16731 #define RX0_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 16732 16733 /* Rx0 :: anaRxAControl1 :: offset_ctrl [05:03] */ 16734 #define RX0_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 16735 #define RX0_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 16736 #define RX0_ANARXACONTROL1_OFFSET_CTRL_BITS 3 16737 #define RX0_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 16738 16739 /* Rx0 :: anaRxAControl1 :: offset_sel [02:02] */ 16740 #define RX0_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 16741 #define RX0_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 16742 #define RX0_ANARXACONTROL1_OFFSET_SEL_BITS 1 16743 #define RX0_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 16744 16745 /* Rx0 :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */ 16746 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY1_MASK 0x0002 16747 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN 0 16748 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY1_BITS 1 16749 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT 1 16750 16751 /* Rx0 :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */ 16752 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY0_MASK 0x0001 16753 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN 0 16754 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY0_BITS 1 16755 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT 0 16756 16757 16758 /**************************************************************************** 16759 * Rx0 :: anaRxAControl2 16760 */ 16761 /* Rx0 :: anaRxAControl2 :: imax_ctat [15:15] */ 16762 #define RX0_ANARXACONTROL2_IMAX_CTAT_MASK 0x8000 16763 #define RX0_ANARXACONTROL2_IMAX_CTAT_ALIGN 0 16764 #define RX0_ANARXACONTROL2_IMAX_CTAT_BITS 1 16765 #define RX0_ANARXACONTROL2_IMAX_CTAT_SHIFT 15 16766 16767 /* Rx0 :: anaRxAControl2 :: imode_ctat [14:14] */ 16768 #define RX0_ANARXACONTROL2_IMODE_CTAT_MASK 0x4000 16769 #define RX0_ANARXACONTROL2_IMODE_CTAT_ALIGN 0 16770 #define RX0_ANARXACONTROL2_IMODE_CTAT_BITS 1 16771 #define RX0_ANARXACONTROL2_IMODE_CTAT_SHIFT 14 16772 16773 /* Rx0 :: anaRxAControl2 :: imin_ctat [13:13] */ 16774 #define RX0_ANARXACONTROL2_IMIN_CTAT_MASK 0x2000 16775 #define RX0_ANARXACONTROL2_IMIN_CTAT_ALIGN 0 16776 #define RX0_ANARXACONTROL2_IMIN_CTAT_BITS 1 16777 #define RX0_ANARXACONTROL2_IMIN_CTAT_SHIFT 13 16778 16779 /* Rx0 :: anaRxAControl2 :: imax_eqfl [12:12] */ 16780 #define RX0_ANARXACONTROL2_IMAX_EQFL_MASK 0x1000 16781 #define RX0_ANARXACONTROL2_IMAX_EQFL_ALIGN 0 16782 #define RX0_ANARXACONTROL2_IMAX_EQFL_BITS 1 16783 #define RX0_ANARXACONTROL2_IMAX_EQFL_SHIFT 12 16784 16785 /* Rx0 :: anaRxAControl2 :: imode_eqfl [11:11] */ 16786 #define RX0_ANARXACONTROL2_IMODE_EQFL_MASK 0x0800 16787 #define RX0_ANARXACONTROL2_IMODE_EQFL_ALIGN 0 16788 #define RX0_ANARXACONTROL2_IMODE_EQFL_BITS 1 16789 #define RX0_ANARXACONTROL2_IMODE_EQFL_SHIFT 11 16790 16791 /* Rx0 :: anaRxAControl2 :: imin_eqfl [10:10] */ 16792 #define RX0_ANARXACONTROL2_IMIN_EQFL_MASK 0x0400 16793 #define RX0_ANARXACONTROL2_IMIN_EQFL_ALIGN 0 16794 #define RX0_ANARXACONTROL2_IMIN_EQFL_BITS 1 16795 #define RX0_ANARXACONTROL2_IMIN_EQFL_SHIFT 10 16796 16797 /* Rx0 :: anaRxAControl2 :: imax_dfesum [09:09] */ 16798 #define RX0_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 16799 #define RX0_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 16800 #define RX0_ANARXACONTROL2_IMAX_DFESUM_BITS 1 16801 #define RX0_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 16802 16803 /* Rx0 :: anaRxAControl2 :: imode_dfesum [08:08] */ 16804 #define RX0_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 16805 #define RX0_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 16806 #define RX0_ANARXACONTROL2_IMODE_DFESUM_BITS 1 16807 #define RX0_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 16808 16809 /* Rx0 :: anaRxAControl2 :: imin_dfesum [07:07] */ 16810 #define RX0_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 16811 #define RX0_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 16812 #define RX0_ANARXACONTROL2_IMIN_DFESUM_BITS 1 16813 #define RX0_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 16814 16815 /* Rx0 :: anaRxAControl2 :: imax_vga [06:06] */ 16816 #define RX0_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 16817 #define RX0_ANARXACONTROL2_IMAX_VGA_ALIGN 0 16818 #define RX0_ANARXACONTROL2_IMAX_VGA_BITS 1 16819 #define RX0_ANARXACONTROL2_IMAX_VGA_SHIFT 6 16820 16821 /* Rx0 :: anaRxAControl2 :: imode_vga [05:05] */ 16822 #define RX0_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 16823 #define RX0_ANARXACONTROL2_IMODE_VGA_ALIGN 0 16824 #define RX0_ANARXACONTROL2_IMODE_VGA_BITS 1 16825 #define RX0_ANARXACONTROL2_IMODE_VGA_SHIFT 5 16826 16827 /* Rx0 :: anaRxAControl2 :: imin_vga [04:04] */ 16828 #define RX0_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 16829 #define RX0_ANARXACONTROL2_IMIN_VGA_ALIGN 0 16830 #define RX0_ANARXACONTROL2_IMIN_VGA_BITS 1 16831 #define RX0_ANARXACONTROL2_IMIN_VGA_SHIFT 4 16832 16833 /* Rx0 :: anaRxAControl2 :: imax_interp [03:03] */ 16834 #define RX0_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 16835 #define RX0_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 16836 #define RX0_ANARXACONTROL2_IMAX_INTERP_BITS 1 16837 #define RX0_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 16838 16839 /* Rx0 :: anaRxAControl2 :: imode_interp [02:02] */ 16840 #define RX0_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 16841 #define RX0_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 16842 #define RX0_ANARXACONTROL2_IMODE_INTERP_BITS 1 16843 #define RX0_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 16844 16845 /* Rx0 :: anaRxAControl2 :: imin_interp [01:01] */ 16846 #define RX0_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 16847 #define RX0_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 16848 #define RX0_ANARXACONTROL2_IMIN_INTERP_BITS 1 16849 #define RX0_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 16850 16851 /* Rx0 :: anaRxAControl2 :: imax_vcm [00:00] */ 16852 #define RX0_ANARXACONTROL2_IMAX_VCM_MASK 0x0001 16853 #define RX0_ANARXACONTROL2_IMAX_VCM_ALIGN 0 16854 #define RX0_ANARXACONTROL2_IMAX_VCM_BITS 1 16855 #define RX0_ANARXACONTROL2_IMAX_VCM_SHIFT 0 16856 16857 16858 /**************************************************************************** 16859 * Rx0 :: anaRxAControl3 16860 */ 16861 /* Rx0 :: anaRxAControl3 :: en_clk16 [15:15] */ 16862 #define RX0_ANARXACONTROL3_EN_CLK16_MASK 0x8000 16863 #define RX0_ANARXACONTROL3_EN_CLK16_ALIGN 0 16864 #define RX0_ANARXACONTROL3_EN_CLK16_BITS 1 16865 #define RX0_ANARXACONTROL3_EN_CLK16_SHIFT 15 16866 16867 /* Rx0 :: anaRxAControl3 :: en_clk33 [14:14] */ 16868 #define RX0_ANARXACONTROL3_EN_CLK33_MASK 0x4000 16869 #define RX0_ANARXACONTROL3_EN_CLK33_ALIGN 0 16870 #define RX0_ANARXACONTROL3_EN_CLK33_BITS 1 16871 #define RX0_ANARXACONTROL3_EN_CLK33_SHIFT 14 16872 16873 /* Rx0 :: anaRxAControl3 :: en_vcctrl [13:13] */ 16874 #define RX0_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 16875 #define RX0_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 16876 #define RX0_ANARXACONTROL3_EN_VCCTRL_BITS 1 16877 #define RX0_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 16878 16879 /* Rx0 :: anaRxAControl3 :: sel_th4dfe1 [12:12] */ 16880 #define RX0_ANARXACONTROL3_SEL_TH4DFE1_MASK 0x1000 16881 #define RX0_ANARXACONTROL3_SEL_TH4DFE1_ALIGN 0 16882 #define RX0_ANARXACONTROL3_SEL_TH4DFE1_BITS 1 16883 #define RX0_ANARXACONTROL3_SEL_TH4DFE1_SHIFT 12 16884 16885 /* Rx0 :: anaRxAControl3 :: sel_th4dfe0 [11:11] */ 16886 #define RX0_ANARXACONTROL3_SEL_TH4DFE0_MASK 0x0800 16887 #define RX0_ANARXACONTROL3_SEL_TH4DFE0_ALIGN 0 16888 #define RX0_ANARXACONTROL3_SEL_TH4DFE0_BITS 1 16889 #define RX0_ANARXACONTROL3_SEL_TH4DFE0_SHIFT 11 16890 16891 /* Rx0 :: anaRxAControl3 :: selugbw1 [10:10] */ 16892 #define RX0_ANARXACONTROL3_SELUGBW1_MASK 0x0400 16893 #define RX0_ANARXACONTROL3_SELUGBW1_ALIGN 0 16894 #define RX0_ANARXACONTROL3_SELUGBW1_BITS 1 16895 #define RX0_ANARXACONTROL3_SELUGBW1_SHIFT 10 16896 16897 /* Rx0 :: anaRxAControl3 :: selugbw0 [09:09] */ 16898 #define RX0_ANARXACONTROL3_SELUGBW0_MASK 0x0200 16899 #define RX0_ANARXACONTROL3_SELUGBW0_ALIGN 0 16900 #define RX0_ANARXACONTROL3_SELUGBW0_BITS 1 16901 #define RX0_ANARXACONTROL3_SELUGBW0_SHIFT 9 16902 16903 /* Rx0 :: anaRxAControl3 :: imax_dfetap [08:08] */ 16904 #define RX0_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 16905 #define RX0_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 16906 #define RX0_ANARXACONTROL3_IMAX_DFETAP_BITS 1 16907 #define RX0_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 16908 16909 /* Rx0 :: anaRxAControl3 :: imode_dfetap [07:07] */ 16910 #define RX0_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 16911 #define RX0_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 16912 #define RX0_ANARXACONTROL3_IMODE_DFETAP_BITS 1 16913 #define RX0_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 16914 16915 /* Rx0 :: anaRxAControl3 :: imin_dfetap [06:06] */ 16916 #define RX0_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 16917 #define RX0_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 16918 #define RX0_ANARXACONTROL3_IMIN_DFETAP_BITS 1 16919 #define RX0_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 16920 16921 /* Rx0 :: anaRxAControl3 :: imax_slcd2c [05:05] */ 16922 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 16923 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 16924 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 16925 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 16926 16927 /* Rx0 :: anaRxAControl3 :: imode_slcd2c [04:04] */ 16928 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 16929 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 16930 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 16931 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 16932 16933 /* Rx0 :: anaRxAControl3 :: imin_slcd2c [03:03] */ 16934 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 16935 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 16936 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 16937 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 16938 16939 /* Rx0 :: anaRxAControl3 :: imax_dfevref [02:02] */ 16940 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 16941 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 16942 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 16943 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 16944 16945 /* Rx0 :: anaRxAControl3 :: imode_dfevref [01:01] */ 16946 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 16947 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 16948 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 16949 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 16950 16951 /* Rx0 :: anaRxAControl3 :: imin_dfevref [00:00] */ 16952 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 16953 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 16954 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 16955 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 16956 16957 16958 /**************************************************************************** 16959 * Warpcore_USER_Rx1 16960 */ 16961 /**************************************************************************** 16962 * Rx1 :: anaRxStatus 16963 */ 16964 /* union - case sigdet_Status [15:00] */ 16965 /* Rx1 :: anaRxStatus :: cx4_sigdet [15:15] */ 16966 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 16967 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 16968 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 16969 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 16970 16971 /* Rx1 :: anaRxStatus :: reserved0 [14:13] */ 16972 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 16973 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 16974 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS 2 16975 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 16976 16977 /* Rx1 :: anaRxStatus :: rxSeqDone [12:12] */ 16978 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 16979 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 16980 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 16981 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 16982 16983 /* Rx1 :: anaRxStatus :: rx_sigdet_ll [11:11] */ 16984 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 16985 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 16986 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 16987 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 16988 16989 /* Rx1 :: anaRxStatus :: cs4_sigdet_ll [10:10] */ 16990 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 16991 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 16992 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 16993 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 16994 16995 /* Rx1 :: anaRxStatus :: rx_reset [09:09] */ 16996 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 16997 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 16998 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS 1 16999 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 17000 17001 /* Rx1 :: anaRxStatus :: rx_pwrdn [08:08] */ 17002 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 17003 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 17004 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 17005 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 17006 17007 /* Rx1 :: anaRxStatus :: reserved1 [07:00] */ 17008 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 17009 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 17010 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS 8 17011 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 17012 17013 17014 /* union - case sync_Status [15:00] */ 17015 /* Rx1 :: anaRxStatus :: reserved0 [15:11] */ 17016 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 17017 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN 0 17018 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS 5 17019 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT 11 17020 17021 /* Rx1 :: anaRxStatus :: test_acq_en [10:10] */ 17022 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 17023 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 17024 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 17025 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 17026 17027 /* Rx1 :: anaRxStatus :: reserved1 [09:09] */ 17028 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 17029 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN 0 17030 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS 1 17031 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT 9 17032 17033 /* Rx1 :: anaRxStatus :: rxSeqStart [08:08] */ 17034 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 17035 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 17036 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS 1 17037 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 17038 17039 /* Rx1 :: anaRxStatus :: mux_comadj_sync_status [07:07] */ 17040 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 17041 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 17042 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 17043 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 17044 17045 /* Rx1 :: anaRxStatus :: sync_status [06:06] */ 17046 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 17047 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 17048 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 17049 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 17050 17051 /* Rx1 :: anaRxStatus :: rx_sigdet [05:05] */ 17052 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 17053 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 17054 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS 1 17055 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 17056 17057 /* Rx1 :: anaRxStatus :: reserved2 [04:03] */ 17058 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 17059 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN 0 17060 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS 2 17061 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT 3 17062 17063 /* Rx1 :: anaRxStatus :: saturate_status [02:02] */ 17064 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 17065 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 17066 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 17067 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 17068 17069 /* Rx1 :: anaRxStatus :: cx4_sigdet [01:01] */ 17070 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 17071 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 17072 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 17073 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 17074 17075 /* Rx1 :: anaRxStatus :: rxSeqDone [00:00] */ 17076 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 17077 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 17078 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS 1 17079 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 17080 17081 17082 /* union - case rxTestSel_0 [15:00] */ 17083 /* Rx1 :: anaRxStatus :: reserved0 [15:10] */ 17084 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 17085 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 17086 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS 6 17087 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 17088 17089 /* Rx1 :: anaRxStatus :: indck_mode_en [09:09] */ 17090 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 17091 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 17092 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 17093 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 17094 17095 /* Rx1 :: anaRxStatus :: pci_mode_en [08:08] */ 17096 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 17097 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 17098 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 17099 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 17100 17101 /* Rx1 :: anaRxStatus :: rx_polarity [07:07] */ 17102 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 17103 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 17104 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 17105 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 17106 17107 /* Rx1 :: anaRxStatus :: rxpol_flip [06:06] */ 17108 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 17109 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 17110 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 17111 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 17112 17113 /* Rx1 :: anaRxStatus :: comma_mask [05:05] */ 17114 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 17115 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 17116 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 17117 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 17118 17119 /* Rx1 :: anaRxStatus :: link_en_r [04:04] */ 17120 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 17121 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 17122 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 17123 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 17124 17125 /* Rx1 :: anaRxStatus :: comma_adj_en [03:03] */ 17126 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 17127 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 17128 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 17129 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 17130 17131 /* Rx1 :: anaRxStatus :: comma_adj_en_ext [02:02] */ 17132 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 17133 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 17134 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 17135 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 17136 17137 /* Rx1 :: anaRxStatus :: reserved1 [01:00] */ 17138 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 17139 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 17140 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS 2 17141 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 17142 17143 17144 /* union - case rxTestSel_1 [15:00] */ 17145 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */ 17146 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 17147 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 17148 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS 11 17149 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 17150 17151 /* Rx1 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */ 17152 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 17153 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 17154 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 17155 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 17156 17157 /* Rx1 :: anaRxStatus :: freq_sel_PC [03:03] */ 17158 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 17159 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 17160 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 17161 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 17162 17163 /* Rx1 :: anaRxStatus :: freq_sel_SM [02:02] */ 17164 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 17165 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 17166 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 17167 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 17168 17169 /* Rx1 :: anaRxStatus :: integ_mode_SM [01:00] */ 17170 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 17171 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 17172 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 17173 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 17174 17175 17176 /* union - case scale_Status [15:00] */ 17177 /* Rx1 :: anaRxStatus :: prop_scale [15:12] */ 17178 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 17179 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 17180 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS 4 17181 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 17182 17183 /* Rx1 :: anaRxStatus :: integ_scale [11:08] */ 17184 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 17185 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 17186 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 17187 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 17188 17189 /* Rx1 :: anaRxStatus :: prop_scale_acq [07:04] */ 17190 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 17191 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 17192 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 17193 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 17194 17195 /* Rx1 :: anaRxStatus :: integ_scale_acq [03:00] */ 17196 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 17197 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 17198 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 17199 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 17200 17201 17202 /* union - case adc_CdrStatus1 [15:00] */ 17203 /* Rx1 :: anaRxStatus :: reserved0 [15:07] */ 17204 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 17205 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 17206 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 17207 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 17208 17209 /* Rx1 :: anaRxStatus :: rxMuxCkSel [06:06] */ 17210 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 17211 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 17212 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 17213 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 17214 17215 /* Rx1 :: anaRxStatus :: glpbk_combo [05:05] */ 17216 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 17217 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 17218 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 17219 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 17220 17221 /* Rx1 :: anaRxStatus :: clockSwitchSel [04:04] */ 17222 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 17223 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 17224 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 17225 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 17226 17227 /* Rx1 :: anaRxStatus :: rxck_tst [03:03] */ 17228 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 17229 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 17230 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 17231 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 17232 17233 /* Rx1 :: anaRxStatus :: rxck_i [02:02] */ 17234 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 17235 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 17236 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 17237 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 17238 17239 /* Rx1 :: anaRxStatus :: refclk [01:01] */ 17240 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 17241 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 17242 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 17243 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 17244 17245 /* Rx1 :: anaRxStatus :: pll_bypass [00:00] */ 17246 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 17247 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 17248 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 17249 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 17250 17251 17252 /* union - case adc_CdrStatus2 [15:00] */ 17253 /* Rx1 :: anaRxStatus :: reserved0 [15:06] */ 17254 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 17255 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 17256 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 17257 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 17258 17259 /* Rx1 :: anaRxStatus :: rxMuxCkSel [05:05] */ 17260 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 17261 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 17262 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 17263 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 17264 17265 /* Rx1 :: anaRxStatus :: rxSeqStart [04:04] */ 17266 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 17267 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 17268 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 17269 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 17270 17271 /* Rx1 :: anaRxStatus :: reserved1 [03:01] */ 17272 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 17273 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 17274 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 17275 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 17276 17277 /* Rx1 :: anaRxStatus :: rxSeqDone [00:00] */ 17278 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 17279 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 17280 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 17281 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 17282 17283 17284 /* union - case adc_CdrStatus3 [15:00] */ 17285 /* Rx1 :: anaRxStatus :: reserved0 [15:04] */ 17286 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 17287 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 17288 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 17289 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 17290 17291 /* Rx1 :: anaRxStatus :: rxSeqStart [03:03] */ 17292 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 17293 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 17294 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 17295 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 17296 17297 /* Rx1 :: anaRxStatus :: reserved1 [02:01] */ 17298 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 17299 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 17300 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 17301 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 17302 17303 /* Rx1 :: anaRxStatus :: allow_increment_PC [00:00] */ 17304 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 17305 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 17306 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 17307 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 17308 17309 17310 /* union - case adc_CdrStatus4 [15:00] */ 17311 /* Rx1 :: anaRxStatus :: reserved0 [15:08] */ 17312 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 17313 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 17314 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 17315 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 17316 17317 /* Rx1 :: anaRxStatus :: rx_pwrdn [07:07] */ 17318 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 17319 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 17320 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 17321 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 17322 17323 /* Rx1 :: anaRxStatus :: freq_sel [06:06] */ 17324 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 17325 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 17326 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 17327 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 17328 17329 /* Rx1 :: anaRxStatus :: pll_lock_rstb [05:05] */ 17330 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 17331 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 17332 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 17333 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 17334 17335 /* Rx1 :: anaRxStatus :: pwrdn [04:04] */ 17336 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 17337 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 17338 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 17339 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 17340 17341 /* Rx1 :: anaRxStatus :: reserved1 [03:00] */ 17342 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 17343 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 17344 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 17345 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 17346 17347 17348 /* union - case adc_CdrStatus5 [15:00] */ 17349 /* Rx1 :: anaRxStatus :: reserved0 [15:00] */ 17350 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 17351 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 17352 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 17353 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 17354 17355 17356 /* union - case adc_CdrStatus6 [15:00] */ 17357 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */ 17358 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 17359 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 17360 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 17361 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 17362 17363 /* Rx1 :: anaRxStatus :: rx_reset [04:04] */ 17364 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 17365 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 17366 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 17367 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 17368 17369 /* Rx1 :: anaRxStatus :: rx_pwrdn [03:03] */ 17370 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 17371 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 17372 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 17373 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 17374 17375 /* Rx1 :: anaRxStatus :: reset_anlg [02:02] */ 17376 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 17377 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 17378 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 17379 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 17380 17381 /* Rx1 :: anaRxStatus :: pwrdn_rx [01:01] */ 17382 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 17383 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 17384 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 17385 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 17386 17387 /* Rx1 :: anaRxStatus :: pwrdn_pll [00:00] */ 17388 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 17389 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 17390 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 17391 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 17392 17393 17394 /* union - case adc_CdrStatus7e [15:00] */ 17395 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */ 17396 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 17397 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 17398 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 17399 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 17400 17401 /* Rx1 :: anaRxStatus :: rxck0_even [04:04] */ 17402 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 17403 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 17404 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 17405 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 17406 17407 /* Rx1 :: anaRxStatus :: rxck1_even [03:03] */ 17408 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 17409 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 17410 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 17411 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 17412 17413 /* Rx1 :: anaRxStatus :: comdet_even [02:02] */ 17414 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 17415 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 17416 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 17417 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 17418 17419 /* Rx1 :: anaRxStatus :: en_cdet_even [01:01] */ 17420 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 17421 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 17422 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 17423 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 17424 17425 /* Rx1 :: anaRxStatus :: comma_adj_en_even [00:00] */ 17426 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 17427 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 17428 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 17429 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 17430 17431 17432 /* union - case adc_CdrStatus7o [15:00] */ 17433 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */ 17434 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 17435 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 17436 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 17437 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 17438 17439 /* Rx1 :: anaRxStatus :: rxck0_odd [04:04] */ 17440 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 17441 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 17442 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 17443 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 17444 17445 /* Rx1 :: anaRxStatus :: rxck1_odd [03:03] */ 17446 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 17447 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 17448 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 17449 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 17450 17451 /* Rx1 :: anaRxStatus :: comdet_odd [02:02] */ 17452 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 17453 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 17454 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 17455 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 17456 17457 /* Rx1 :: anaRxStatus :: en_cdet_odd [01:01] */ 17458 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 17459 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 17460 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 17461 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 17462 17463 /* Rx1 :: anaRxStatus :: comma_adj_en_odd [00:00] */ 17464 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 17465 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 17466 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 17467 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 17468 17469 17470 /* union - case adc_CdrStatus8 [15:00] */ 17471 /* Rx1 :: anaRxStatus :: reserved0 [15:01] */ 17472 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 17473 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 17474 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 17475 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 17476 17477 /* Rx1 :: anaRxStatus :: sigdet [00:00] */ 17478 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 17479 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 17480 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 17481 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 17482 17483 17484 /* union - case adc_CdrStatus9 [15:00] */ 17485 /* Rx1 :: anaRxStatus :: reserved0 [15:00] */ 17486 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 17487 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 17488 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 17489 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 17490 17491 17492 /* union - case adc_CdrStatus10 [15:00] */ 17493 /* Rx1 :: anaRxStatus :: reserved0 [15:07] */ 17494 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 17495 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 17496 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 17497 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 17498 17499 /* Rx1 :: anaRxStatus :: prbs_en [06:06] */ 17500 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 17501 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 17502 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 17503 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 17504 17505 /* Rx1 :: anaRxStatus :: rstb_tst [05:05] */ 17506 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 17507 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 17508 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 17509 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 17510 17511 /* Rx1 :: anaRxStatus :: reserved1 [04:04] */ 17512 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 17513 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 17514 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 17515 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 17516 17517 /* Rx1 :: anaRxStatus :: prbs_state [03:00] */ 17518 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 17519 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 17520 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 17521 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 17522 17523 17524 /* union - case adc_CdrStatus11 [15:00] */ 17525 /* Rx1 :: anaRxStatus :: reserved0 [15:00] */ 17526 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 17527 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 17528 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 17529 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 17530 17531 17532 /* union - case adc_CdrStatus12_1 [15:00] */ 17533 /* Rx1 :: anaRxStatus :: reserved0 [15:06] */ 17534 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 17535 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 17536 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 17537 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 17538 17539 /* Rx1 :: anaRxStatus :: enable4 [05:05] */ 17540 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 17541 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 17542 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 17543 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 17544 17545 /* Rx1 :: anaRxStatus :: radr_test [04:00] */ 17546 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 17547 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 17548 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 17549 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 17550 17551 17552 /* union - case adc_CdrStatus12_2 [15:00] */ 17553 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */ 17554 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 17555 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 17556 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 17557 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 17558 17559 /* Rx1 :: anaRxStatus :: wadr_test [04:00] */ 17560 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 17561 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 17562 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 17563 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 17564 17565 17566 /* union - case adc_CdrStatus12_3 [15:00] */ 17567 /* Rx1 :: anaRxStatus :: reserved0 [15:06] */ 17568 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 17569 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 17570 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 17571 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 17572 17573 /* Rx1 :: anaRxStatus :: rxck_66B_tmux [05:05] */ 17574 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 17575 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 17576 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 17577 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 17578 17579 /* Rx1 :: anaRxStatus :: rstb_66B [04:04] */ 17580 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 17581 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 17582 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 17583 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 17584 17585 /* Rx1 :: anaRxStatus :: prstb_66B_mux [03:03] */ 17586 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 17587 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 17588 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 17589 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 17590 17591 /* Rx1 :: anaRxStatus :: rxck_i66_tmux [02:02] */ 17592 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 17593 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 17594 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 17595 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 17596 17597 /* Rx1 :: anaRxStatus :: rstb_i66 [01:01] */ 17598 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 17599 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 17600 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 17601 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 17602 17603 /* Rx1 :: anaRxStatus :: prstb_i66_mux [00:00] */ 17604 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 17605 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 17606 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 17607 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 17608 17609 17610 /* union - case adc_CdrStatus12_4 [15:00] */ 17611 /* Rx1 :: anaRxStatus :: reserved0 [15:04] */ 17612 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 17613 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 17614 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 17615 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 17616 17617 /* Rx1 :: anaRxStatus :: rfifo_error_r [03:02] */ 17618 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 17619 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 17620 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 17621 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 17622 17623 /* Rx1 :: anaRxStatus :: rfifo_unflow [01:01] */ 17624 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 17625 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 17626 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 17627 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 17628 17629 /* Rx1 :: anaRxStatus :: rfifo_ovflow [00:00] */ 17630 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 17631 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 17632 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 17633 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 17634 17635 17636 /* union - case integ_Status [15:00] */ 17637 /* Rx1 :: anaRxStatus :: integ_status [15:00] */ 17638 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 17639 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 17640 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 17641 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 17642 17643 17644 /* union - case vco_Status [15:00] */ 17645 /* Rx1 :: anaRxStatus :: vco_status [15:00] */ 17646 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 17647 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 17648 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS 16 17649 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 17650 17651 17652 /* union - case prbs_Status [15:00] */ 17653 /* Rx1 :: anaRxStatus :: prbs_lock [15:15] */ 17654 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 17655 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 17656 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 17657 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 17658 17659 /* Rx1 :: anaRxStatus :: prbs_stky [14:14] */ 17660 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 17661 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 17662 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS 1 17663 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 17664 17665 /* Rx1 :: anaRxStatus :: prbs_errors [13:00] */ 17666 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_MASK 0x3fff 17667 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_ALIGN 0 17668 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_BITS 14 17669 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_SHIFT 0 17670 17671 17672 17673 /**************************************************************************** 17674 * Rx1 :: anaRxControl 17675 */ 17676 /* Rx1 :: anaRxControl :: reserved0 [15:10] */ 17677 #define RX1_ANARXCONTROL_RESERVED0_MASK 0xfc00 17678 #define RX1_ANARXCONTROL_RESERVED0_ALIGN 0 17679 #define RX1_ANARXCONTROL_RESERVED0_BITS 6 17680 #define RX1_ANARXCONTROL_RESERVED0_SHIFT 10 17681 17682 /* Rx1 :: anaRxControl :: override_sigdet_en [09:09] */ 17683 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 17684 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 17685 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 17686 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 17687 17688 /* Rx1 :: anaRxControl :: override_sigdet_val [08:08] */ 17689 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 17690 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 17691 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 17692 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 17693 17694 /* Rx1 :: anaRxControl :: reserved1 [07:03] */ 17695 #define RX1_ANARXCONTROL_RESERVED1_MASK 0x00f8 17696 #define RX1_ANARXCONTROL_RESERVED1_ALIGN 0 17697 #define RX1_ANARXCONTROL_RESERVED1_BITS 5 17698 #define RX1_ANARXCONTROL_RESERVED1_SHIFT 3 17699 17700 /* Rx1 :: anaRxControl :: status_sel [02:00] */ 17701 #define RX1_ANARXCONTROL_STATUS_SEL_MASK 0x0007 17702 #define RX1_ANARXCONTROL_STATUS_SEL_ALIGN 0 17703 #define RX1_ANARXCONTROL_STATUS_SEL_BITS 3 17704 #define RX1_ANARXCONTROL_STATUS_SEL_SHIFT 0 17705 #define RX1_ANARXCONTROL_STATUS_SEL_sigdetStatus 0 17706 #define RX1_ANARXCONTROL_STATUS_SEL_syncStatus 1 17707 #define RX1_ANARXCONTROL_STATUS_SEL_rxTestSel 2 17708 #define RX1_ANARXCONTROL_STATUS_SEL_scaleStatus 3 17709 #define RX1_ANARXCONTROL_STATUS_SEL_adcCdrStatus 4 17710 #define RX1_ANARXCONTROL_STATUS_SEL_integStatus 5 17711 #define RX1_ANARXCONTROL_STATUS_SEL_vcoStatus 6 17712 #define RX1_ANARXCONTROL_STATUS_SEL_prbsStatus 7 17713 17714 17715 /**************************************************************************** 17716 * Rx1 :: anaRxSigdet 17717 */ 17718 /* Rx1 :: anaRxSigdet :: sigdetTime_SM [15:08] */ 17719 #define RX1_ANARXSIGDET_SIGDETTIME_SM_MASK 0xff00 17720 #define RX1_ANARXSIGDET_SIGDETTIME_SM_ALIGN 0 17721 #define RX1_ANARXSIGDET_SIGDETTIME_SM_BITS 8 17722 #define RX1_ANARXSIGDET_SIGDETTIME_SM_SHIFT 8 17723 17724 /* Rx1 :: anaRxSigdet :: cx4_sigdet_cnt_ld_SM [07:07] */ 17725 #define RX1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_MASK 0x0080 17726 #define RX1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_ALIGN 0 17727 #define RX1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_BITS 1 17728 #define RX1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_SHIFT 7 17729 17730 /* Rx1 :: anaRxSigdet :: ext_sigdet_en_SM [06:06] */ 17731 #define RX1_ANARXSIGDET_EXT_SIGDET_EN_SM_MASK 0x0040 17732 #define RX1_ANARXSIGDET_EXT_SIGDET_EN_SM_ALIGN 0 17733 #define RX1_ANARXSIGDET_EXT_SIGDET_EN_SM_BITS 1 17734 #define RX1_ANARXSIGDET_EXT_SIGDET_EN_SM_SHIFT 6 17735 17736 /* Rx1 :: anaRxSigdet :: cx4_sigdet_en_SM [05:05] */ 17737 #define RX1_ANARXSIGDET_CX4_SIGDET_EN_SM_MASK 0x0020 17738 #define RX1_ANARXSIGDET_CX4_SIGDET_EN_SM_ALIGN 0 17739 #define RX1_ANARXSIGDET_CX4_SIGDET_EN_SM_BITS 1 17740 #define RX1_ANARXSIGDET_CX4_SIGDET_EN_SM_SHIFT 5 17741 17742 /* Rx1 :: anaRxSigdet :: rx_sigdet_r [04:04] */ 17743 #define RX1_ANARXSIGDET_RX_SIGDET_R_MASK 0x0010 17744 #define RX1_ANARXSIGDET_RX_SIGDET_R_ALIGN 0 17745 #define RX1_ANARXSIGDET_RX_SIGDET_R_BITS 1 17746 #define RX1_ANARXSIGDET_RX_SIGDET_R_SHIFT 4 17747 17748 /* Rx1 :: anaRxSigdet :: rx_sigdet_force_r [03:03] */ 17749 #define RX1_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK 0x0008 17750 #define RX1_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN 0 17751 #define RX1_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS 1 17752 #define RX1_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT 3 17753 17754 /* Rx1 :: anaRxSigdet :: invert_rx_sigdet [02:02] */ 17755 #define RX1_ANARXSIGDET_INVERT_RX_SIGDET_MASK 0x0004 17756 #define RX1_ANARXSIGDET_INVERT_RX_SIGDET_ALIGN 0 17757 #define RX1_ANARXSIGDET_INVERT_RX_SIGDET_BITS 1 17758 #define RX1_ANARXSIGDET_INVERT_RX_SIGDET_SHIFT 2 17759 17760 /* Rx1 :: anaRxSigdet :: reserved0 [01:00] */ 17761 #define RX1_ANARXSIGDET_RESERVED0_MASK 0x0003 17762 #define RX1_ANARXSIGDET_RESERVED0_ALIGN 0 17763 #define RX1_ANARXSIGDET_RESERVED0_BITS 2 17764 #define RX1_ANARXSIGDET_RESERVED0_SHIFT 0 17765 17766 17767 /**************************************************************************** 17768 * Rx1 :: anaRxAControl4 17769 */ 17770 /* Rx1 :: anaRxAControl4 :: ana_clt4 [15:00] */ 17771 #define RX1_ANARXACONTROL4_ANA_CLT4_MASK 0xffff 17772 #define RX1_ANARXACONTROL4_ANA_CLT4_ALIGN 0 17773 #define RX1_ANARXACONTROL4_ANA_CLT4_BITS 16 17774 #define RX1_ANARXACONTROL4_ANA_CLT4_SHIFT 0 17775 17776 17777 /**************************************************************************** 17778 * Rx1 :: anaRxControl2_1G 17779 */ 17780 /* Rx1 :: anaRxControl2_1G :: reserved0 [15:15] */ 17781 #define RX1_ANARXCONTROL2_1G_RESERVED0_MASK 0x8000 17782 #define RX1_ANARXCONTROL2_1G_RESERVED0_ALIGN 0 17783 #define RX1_ANARXCONTROL2_1G_RESERVED0_BITS 1 17784 #define RX1_ANARXCONTROL2_1G_RESERVED0_SHIFT 15 17785 17786 /* Rx1 :: anaRxControl2_1G :: rx_prbs_w_val [14:14] */ 17787 #define RX1_ANARXCONTROL2_1G_RX_PRBS_W_VAL_MASK 0x4000 17788 #define RX1_ANARXCONTROL2_1G_RX_PRBS_W_VAL_ALIGN 0 17789 #define RX1_ANARXCONTROL2_1G_RX_PRBS_W_VAL_BITS 1 17790 #define RX1_ANARXCONTROL2_1G_RX_PRBS_W_VAL_SHIFT 14 17791 17792 /* Rx1 :: anaRxControl2_1G :: rx_prbs_w_force [13:13] */ 17793 #define RX1_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_MASK 0x2000 17794 #define RX1_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_ALIGN 0 17795 #define RX1_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_BITS 1 17796 #define RX1_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_SHIFT 13 17797 17798 /* Rx1 :: anaRxControl2_1G :: rx_prbs_bswap [12:12] */ 17799 #define RX1_ANARXCONTROL2_1G_RX_PRBS_BSWAP_MASK 0x1000 17800 #define RX1_ANARXCONTROL2_1G_RX_PRBS_BSWAP_ALIGN 0 17801 #define RX1_ANARXCONTROL2_1G_RX_PRBS_BSWAP_BITS 1 17802 #define RX1_ANARXCONTROL2_1G_RX_PRBS_BSWAP_SHIFT 12 17803 17804 /* Rx1 :: anaRxControl2_1G :: rx_bitswap [11:11] */ 17805 #define RX1_ANARXCONTROL2_1G_RX_BITSWAP_MASK 0x0800 17806 #define RX1_ANARXCONTROL2_1G_RX_BITSWAP_ALIGN 0 17807 #define RX1_ANARXCONTROL2_1G_RX_BITSWAP_BITS 1 17808 #define RX1_ANARXCONTROL2_1G_RX_BITSWAP_SHIFT 11 17809 17810 /* Rx1 :: anaRxControl2_1G :: rst_rx_r [10:10] */ 17811 #define RX1_ANARXCONTROL2_1G_RST_RX_R_MASK 0x0400 17812 #define RX1_ANARXCONTROL2_1G_RST_RX_R_ALIGN 0 17813 #define RX1_ANARXCONTROL2_1G_RST_RX_R_BITS 1 17814 #define RX1_ANARXCONTROL2_1G_RST_RX_R_SHIFT 10 17815 17816 /* Rx1 :: anaRxControl2_1G :: pwdwn_rx_r [09:09] */ 17817 #define RX1_ANARXCONTROL2_1G_PWDWN_RX_R_MASK 0x0200 17818 #define RX1_ANARXCONTROL2_1G_PWDWN_RX_R_ALIGN 0 17819 #define RX1_ANARXCONTROL2_1G_PWDWN_RX_R_BITS 1 17820 #define RX1_ANARXCONTROL2_1G_PWDWN_RX_R_SHIFT 9 17821 17822 /* Rx1 :: anaRxControl2_1G :: prbs_order_rx_r_2 [08:08] */ 17823 #define RX1_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_MASK 0x0100 17824 #define RX1_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_ALIGN 0 17825 #define RX1_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_BITS 1 17826 #define RX1_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_SHIFT 8 17827 17828 /* Rx1 :: anaRxControl2_1G :: reserved1 [07:07] */ 17829 #define RX1_ANARXCONTROL2_1G_RESERVED1_MASK 0x0080 17830 #define RX1_ANARXCONTROL2_1G_RESERVED1_ALIGN 0 17831 #define RX1_ANARXCONTROL2_1G_RESERVED1_BITS 1 17832 #define RX1_ANARXCONTROL2_1G_RESERVED1_SHIFT 7 17833 17834 /* Rx1 :: anaRxControl2_1G :: prbs_sel_rx_r [06:06] */ 17835 #define RX1_ANARXCONTROL2_1G_PRBS_SEL_RX_R_MASK 0x0040 17836 #define RX1_ANARXCONTROL2_1G_PRBS_SEL_RX_R_ALIGN 0 17837 #define RX1_ANARXCONTROL2_1G_PRBS_SEL_RX_R_BITS 1 17838 #define RX1_ANARXCONTROL2_1G_PRBS_SEL_RX_R_SHIFT 6 17839 17840 /* Rx1 :: anaRxControl2_1G :: prbs_en_rx_r [05:05] */ 17841 #define RX1_ANARXCONTROL2_1G_PRBS_EN_RX_R_MASK 0x0020 17842 #define RX1_ANARXCONTROL2_1G_PRBS_EN_RX_R_ALIGN 0 17843 #define RX1_ANARXCONTROL2_1G_PRBS_EN_RX_R_BITS 1 17844 #define RX1_ANARXCONTROL2_1G_PRBS_EN_RX_R_SHIFT 5 17845 17846 /* Rx1 :: anaRxControl2_1G :: prbs_inv_rx_r [04:04] */ 17847 #define RX1_ANARXCONTROL2_1G_PRBS_INV_RX_R_MASK 0x0010 17848 #define RX1_ANARXCONTROL2_1G_PRBS_INV_RX_R_ALIGN 0 17849 #define RX1_ANARXCONTROL2_1G_PRBS_INV_RX_R_BITS 1 17850 #define RX1_ANARXCONTROL2_1G_PRBS_INV_RX_R_SHIFT 4 17851 17852 /* Rx1 :: anaRxControl2_1G :: prbs_order_rx_r [03:02] */ 17853 #define RX1_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_MASK 0x000c 17854 #define RX1_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_ALIGN 0 17855 #define RX1_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_BITS 2 17856 #define RX1_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_SHIFT 2 17857 17858 /* Rx1 :: anaRxControl2_1G :: reserved2 [01:01] */ 17859 #define RX1_ANARXCONTROL2_1G_RESERVED2_MASK 0x0002 17860 #define RX1_ANARXCONTROL2_1G_RESERVED2_ALIGN 0 17861 #define RX1_ANARXCONTROL2_1G_RESERVED2_BITS 1 17862 #define RX1_ANARXCONTROL2_1G_RESERVED2_SHIFT 1 17863 17864 /* Rx1 :: anaRxControl2_1G :: errcnt_15 [00:00] */ 17865 #define RX1_ANARXCONTROL2_1G_ERRCNT_15_MASK 0x0001 17866 #define RX1_ANARXCONTROL2_1G_ERRCNT_15_ALIGN 0 17867 #define RX1_ANARXCONTROL2_1G_ERRCNT_15_BITS 1 17868 #define RX1_ANARXCONTROL2_1G_ERRCNT_15_SHIFT 0 17869 17870 17871 /**************************************************************************** 17872 * Rx1 :: anaRxTest 17873 */ 17874 /* Rx1 :: anaRxTest :: sigdet_mux_SM [15:12] */ 17875 #define RX1_ANARXTEST_SIGDET_MUX_SM_MASK 0xf000 17876 #define RX1_ANARXTEST_SIGDET_MUX_SM_ALIGN 0 17877 #define RX1_ANARXTEST_SIGDET_MUX_SM_BITS 4 17878 #define RX1_ANARXTEST_SIGDET_MUX_SM_SHIFT 12 17879 17880 /* Rx1 :: anaRxTest :: reserved0 [11:09] */ 17881 #define RX1_ANARXTEST_RESERVED0_MASK 0x0e00 17882 #define RX1_ANARXTEST_RESERVED0_ALIGN 0 17883 #define RX1_ANARXTEST_RESERVED0_BITS 3 17884 #define RX1_ANARXTEST_RESERVED0_SHIFT 9 17885 17886 /* Rx1 :: anaRxTest :: tpctrl_SM [08:04] */ 17887 #define RX1_ANARXTEST_TPCTRL_SM_MASK 0x01f0 17888 #define RX1_ANARXTEST_TPCTRL_SM_ALIGN 0 17889 #define RX1_ANARXTEST_TPCTRL_SM_BITS 5 17890 #define RX1_ANARXTEST_TPCTRL_SM_SHIFT 4 17891 17892 /* Rx1 :: anaRxTest :: testMuxSelect_SM [03:00] */ 17893 #define RX1_ANARXTEST_TESTMUXSELECT_SM_MASK 0x000f 17894 #define RX1_ANARXTEST_TESTMUXSELECT_SM_ALIGN 0 17895 #define RX1_ANARXTEST_TESTMUXSELECT_SM_BITS 4 17896 #define RX1_ANARXTEST_TESTMUXSELECT_SM_SHIFT 0 17897 17898 17899 /**************************************************************************** 17900 * Rx1 :: anaRxControl1G 17901 */ 17902 /* Rx1 :: anaRxControl1G :: fpat_md [15:15] */ 17903 #define RX1_ANARXCONTROL1G_FPAT_MD_MASK 0x8000 17904 #define RX1_ANARXCONTROL1G_FPAT_MD_ALIGN 0 17905 #define RX1_ANARXCONTROL1G_FPAT_MD_BITS 1 17906 #define RX1_ANARXCONTROL1G_FPAT_MD_SHIFT 15 17907 17908 /* Rx1 :: anaRxControl1G :: pkt_count_en [14:14] */ 17909 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_MASK 0x4000 17910 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN 0 17911 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_BITS 1 17912 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT 14 17913 17914 /* Rx1 :: anaRxControl1G :: staMuxRegDis [13:13] */ 17915 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_MASK 0x2000 17916 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_ALIGN 0 17917 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_BITS 1 17918 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_SHIFT 13 17919 17920 /* Rx1 :: anaRxControl1G :: prbs_clr_dis [12:12] */ 17921 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_MASK 0x1000 17922 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN 0 17923 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_BITS 1 17924 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT 12 17925 17926 /* Rx1 :: anaRxControl1G :: rxd_dec_sel [11:11] */ 17927 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_MASK 0x0800 17928 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN 0 17929 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_BITS 1 17930 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT 11 17931 17932 /* Rx1 :: anaRxControl1G :: cgbad_tst [10:10] */ 17933 #define RX1_ANARXCONTROL1G_CGBAD_TST_MASK 0x0400 17934 #define RX1_ANARXCONTROL1G_CGBAD_TST_ALIGN 0 17935 #define RX1_ANARXCONTROL1G_CGBAD_TST_BITS 1 17936 #define RX1_ANARXCONTROL1G_CGBAD_TST_SHIFT 10 17937 17938 /* Rx1 :: anaRxControl1G :: Emon_en [09:09] */ 17939 #define RX1_ANARXCONTROL1G_EMON_EN_MASK 0x0200 17940 #define RX1_ANARXCONTROL1G_EMON_EN_ALIGN 0 17941 #define RX1_ANARXCONTROL1G_EMON_EN_BITS 1 17942 #define RX1_ANARXCONTROL1G_EMON_EN_SHIFT 9 17943 17944 /* Rx1 :: anaRxControl1G :: prbs_en [08:08] */ 17945 #define RX1_ANARXCONTROL1G_PRBS_EN_MASK 0x0100 17946 #define RX1_ANARXCONTROL1G_PRBS_EN_ALIGN 0 17947 #define RX1_ANARXCONTROL1G_PRBS_EN_BITS 1 17948 #define RX1_ANARXCONTROL1G_PRBS_EN_SHIFT 8 17949 17950 /* Rx1 :: anaRxControl1G :: cgbad_en [07:07] */ 17951 #define RX1_ANARXCONTROL1G_CGBAD_EN_MASK 0x0080 17952 #define RX1_ANARXCONTROL1G_CGBAD_EN_ALIGN 0 17953 #define RX1_ANARXCONTROL1G_CGBAD_EN_BITS 1 17954 #define RX1_ANARXCONTROL1G_CGBAD_EN_SHIFT 7 17955 17956 /* Rx1 :: anaRxControl1G :: cstretch [06:06] */ 17957 #define RX1_ANARXCONTROL1G_CSTRETCH_MASK 0x0040 17958 #define RX1_ANARXCONTROL1G_CSTRETCH_ALIGN 0 17959 #define RX1_ANARXCONTROL1G_CSTRETCH_BITS 1 17960 #define RX1_ANARXCONTROL1G_CSTRETCH_SHIFT 6 17961 17962 /* Rx1 :: anaRxControl1G :: comma_low_byte_SM [05:05] */ 17963 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK 0x0020 17964 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN 0 17965 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS 1 17966 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT 5 17967 17968 /* Rx1 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */ 17969 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 17970 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 17971 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS 1 17972 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 17973 17974 /* Rx1 :: anaRxControl1G :: reserved0 [03:02] */ 17975 #define RX1_ANARXCONTROL1G_RESERVED0_MASK 0x000c 17976 #define RX1_ANARXCONTROL1G_RESERVED0_ALIGN 0 17977 #define RX1_ANARXCONTROL1G_RESERVED0_BITS 2 17978 #define RX1_ANARXCONTROL1G_RESERVED0_SHIFT 2 17979 17980 /* Rx1 :: anaRxControl1G :: freq_sel_force [01:01] */ 17981 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK 0x0002 17982 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN 0 17983 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS 1 17984 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT 1 17985 17986 /* Rx1 :: anaRxControl1G :: freq_sel [00:00] */ 17987 #define RX1_ANARXCONTROL1G_FREQ_SEL_MASK 0x0001 17988 #define RX1_ANARXCONTROL1G_FREQ_SEL_ALIGN 0 17989 #define RX1_ANARXCONTROL1G_FREQ_SEL_BITS 1 17990 #define RX1_ANARXCONTROL1G_FREQ_SEL_SHIFT 0 17991 17992 17993 /**************************************************************************** 17994 * Rx1 :: anaRxControlPci 17995 */ 17996 /* Rx1 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */ 17997 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK 0x8000 17998 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN 0 17999 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS 1 18000 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT 15 18001 18002 /* Rx1 :: anaRxControlPci :: comma_mask_force_r [14:14] */ 18003 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK 0x4000 18004 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN 0 18005 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS 1 18006 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT 14 18007 18008 /* Rx1 :: anaRxControlPci :: comma_mask_r [13:13] */ 18009 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_MASK 0x2000 18010 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN 0 18011 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_BITS 1 18012 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT 13 18013 18014 /* Rx1 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */ 18015 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000 18016 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0 18017 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1 18018 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12 18019 18020 /* Rx1 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */ 18021 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK 0x0800 18022 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0 18023 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS 1 18024 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11 18025 18026 /* Rx1 :: anaRxControlPci :: sync_status_force_r [10:10] */ 18027 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK 0x0400 18028 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN 0 18029 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS 1 18030 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT 10 18031 18032 /* Rx1 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */ 18033 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200 18034 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0 18035 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1 18036 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9 18037 18038 /* Rx1 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */ 18039 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100 18040 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0 18041 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1 18042 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8 18043 18044 /* Rx1 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */ 18045 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080 18046 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0 18047 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1 18048 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7 18049 18050 /* Rx1 :: anaRxControlPci :: comma_adj_en_r [06:06] */ 18051 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK 0x0040 18052 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN 0 18053 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS 1 18054 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT 6 18055 18056 /* Rx1 :: anaRxControlPci :: link_en_force_SM [05:05] */ 18057 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK 0x0020 18058 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN 0 18059 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS 1 18060 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT 5 18061 18062 /* Rx1 :: anaRxControlPci :: link_en_r [04:04] */ 18063 #define RX1_ANARXCONTROLPCI_LINK_EN_R_MASK 0x0010 18064 #define RX1_ANARXCONTROLPCI_LINK_EN_R_ALIGN 0 18065 #define RX1_ANARXCONTROLPCI_LINK_EN_R_BITS 1 18066 #define RX1_ANARXCONTROLPCI_LINK_EN_R_SHIFT 4 18067 18068 /* Rx1 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */ 18069 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK 0x0008 18070 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN 0 18071 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS 1 18072 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT 3 18073 18074 /* Rx1 :: anaRxControlPci :: rx_polarity_r [02:02] */ 18075 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_MASK 0x0004 18076 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN 0 18077 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_BITS 1 18078 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT 2 18079 18080 /* Rx1 :: anaRxControlPci :: integ_mode_SM [01:00] */ 18081 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_MASK 0x0003 18082 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN 0 18083 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_BITS 2 18084 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT 0 18085 18086 18087 /**************************************************************************** 18088 * Rx1 :: anaRxAstatus 18089 */ 18090 /* Rx1 :: anaRxAstatus :: sigdet [15:15] */ 18091 #define RX1_ANARXASTATUS_SIGDET_MASK 0x8000 18092 #define RX1_ANARXASTATUS_SIGDET_ALIGN 0 18093 #define RX1_ANARXASTATUS_SIGDET_BITS 1 18094 #define RX1_ANARXASTATUS_SIGDET_SHIFT 15 18095 18096 /* Rx1 :: anaRxAstatus :: rx_pf [14:11] */ 18097 #define RX1_ANARXASTATUS_RX_PF_MASK 0x7800 18098 #define RX1_ANARXASTATUS_RX_PF_ALIGN 0 18099 #define RX1_ANARXASTATUS_RX_PF_BITS 4 18100 #define RX1_ANARXASTATUS_RX_PF_SHIFT 11 18101 18102 /* Rx1 :: anaRxAstatus :: tap1_dfe_gray [10:05] */ 18103 #define RX1_ANARXASTATUS_TAP1_DFE_GRAY_MASK 0x07e0 18104 #define RX1_ANARXASTATUS_TAP1_DFE_GRAY_ALIGN 0 18105 #define RX1_ANARXASTATUS_TAP1_DFE_GRAY_BITS 6 18106 #define RX1_ANARXASTATUS_TAP1_DFE_GRAY_SHIFT 5 18107 18108 /* Rx1 :: anaRxAstatus :: vga [04:00] */ 18109 #define RX1_ANARXASTATUS_VGA_MASK 0x001f 18110 #define RX1_ANARXASTATUS_VGA_ALIGN 0 18111 #define RX1_ANARXASTATUS_VGA_BITS 5 18112 #define RX1_ANARXASTATUS_VGA_SHIFT 0 18113 18114 18115 /**************************************************************************** 18116 * Rx1 :: anaRxAControl1 18117 */ 18118 /* Rx1 :: anaRxAControl1 :: imode_vcm [15:15] */ 18119 #define RX1_ANARXACONTROL1_IMODE_VCM_MASK 0x8000 18120 #define RX1_ANARXACONTROL1_IMODE_VCM_ALIGN 0 18121 #define RX1_ANARXACONTROL1_IMODE_VCM_BITS 1 18122 #define RX1_ANARXACONTROL1_IMODE_VCM_SHIFT 15 18123 18124 /* Rx1 :: anaRxAControl1 :: imin_vcm [14:14] */ 18125 #define RX1_ANARXACONTROL1_IMIN_VCM_MASK 0x4000 18126 #define RX1_ANARXACONTROL1_IMIN_VCM_ALIGN 0 18127 #define RX1_ANARXACONTROL1_IMIN_VCM_BITS 1 18128 #define RX1_ANARXACONTROL1_IMIN_VCM_SHIFT 14 18129 18130 /* Rx1 :: anaRxAControl1 :: imax_sigdet [13:13] */ 18131 #define RX1_ANARXACONTROL1_IMAX_SIGDET_MASK 0x2000 18132 #define RX1_ANARXACONTROL1_IMAX_SIGDET_ALIGN 0 18133 #define RX1_ANARXACONTROL1_IMAX_SIGDET_BITS 1 18134 #define RX1_ANARXACONTROL1_IMAX_SIGDET_SHIFT 13 18135 18136 /* Rx1 :: anaRxAControl1 :: imode_sigdet [12:12] */ 18137 #define RX1_ANARXACONTROL1_IMODE_SIGDET_MASK 0x1000 18138 #define RX1_ANARXACONTROL1_IMODE_SIGDET_ALIGN 0 18139 #define RX1_ANARXACONTROL1_IMODE_SIGDET_BITS 1 18140 #define RX1_ANARXACONTROL1_IMODE_SIGDET_SHIFT 12 18141 18142 /* Rx1 :: anaRxAControl1 :: imin_sigdet [11:11] */ 18143 #define RX1_ANARXACONTROL1_IMIN_SIGDET_MASK 0x0800 18144 #define RX1_ANARXACONTROL1_IMIN_SIGDET_ALIGN 0 18145 #define RX1_ANARXACONTROL1_IMIN_SIGDET_BITS 1 18146 #define RX1_ANARXACONTROL1_IMIN_SIGDET_SHIFT 11 18147 18148 /* Rx1 :: anaRxAControl1 :: refh_rx [10:10] */ 18149 #define RX1_ANARXACONTROL1_REFH_RX_MASK 0x0400 18150 #define RX1_ANARXACONTROL1_REFH_RX_ALIGN 0 18151 #define RX1_ANARXACONTROL1_REFH_RX_BITS 1 18152 #define RX1_ANARXACONTROL1_REFH_RX_SHIFT 10 18153 18154 /* Rx1 :: anaRxAControl1 :: refl_rx [09:09] */ 18155 #define RX1_ANARXACONTROL1_REFL_RX_MASK 0x0200 18156 #define RX1_ANARXACONTROL1_REFL_RX_ALIGN 0 18157 #define RX1_ANARXACONTROL1_REFL_RX_BITS 1 18158 #define RX1_ANARXACONTROL1_REFL_RX_SHIFT 9 18159 18160 /* Rx1 :: anaRxAControl1 :: tport_en [08:08] */ 18161 #define RX1_ANARXACONTROL1_TPORT_EN_MASK 0x0100 18162 #define RX1_ANARXACONTROL1_TPORT_EN_ALIGN 0 18163 #define RX1_ANARXACONTROL1_TPORT_EN_BITS 1 18164 #define RX1_ANARXACONTROL1_TPORT_EN_SHIFT 8 18165 18166 /* Rx1 :: anaRxAControl1 :: vddrb_bgb [07:07] */ 18167 #define RX1_ANARXACONTROL1_VDDRB_BGB_MASK 0x0080 18168 #define RX1_ANARXACONTROL1_VDDRB_BGB_ALIGN 0 18169 #define RX1_ANARXACONTROL1_VDDRB_BGB_BITS 1 18170 #define RX1_ANARXACONTROL1_VDDRB_BGB_SHIFT 7 18171 18172 /* Rx1 :: anaRxAControl1 :: sig_pwrdn [06:06] */ 18173 #define RX1_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 18174 #define RX1_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 18175 #define RX1_ANARXACONTROL1_SIG_PWRDN_BITS 1 18176 #define RX1_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 18177 18178 /* Rx1 :: anaRxAControl1 :: offset_ctrl [05:03] */ 18179 #define RX1_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 18180 #define RX1_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 18181 #define RX1_ANARXACONTROL1_OFFSET_CTRL_BITS 3 18182 #define RX1_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 18183 18184 /* Rx1 :: anaRxAControl1 :: offset_sel [02:02] */ 18185 #define RX1_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 18186 #define RX1_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 18187 #define RX1_ANARXACONTROL1_OFFSET_SEL_BITS 1 18188 #define RX1_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 18189 18190 /* Rx1 :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */ 18191 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY1_MASK 0x0002 18192 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN 0 18193 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY1_BITS 1 18194 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT 1 18195 18196 /* Rx1 :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */ 18197 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY0_MASK 0x0001 18198 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN 0 18199 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY0_BITS 1 18200 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT 0 18201 18202 18203 /**************************************************************************** 18204 * Rx1 :: anaRxAControl2 18205 */ 18206 /* Rx1 :: anaRxAControl2 :: imax_ctat [15:15] */ 18207 #define RX1_ANARXACONTROL2_IMAX_CTAT_MASK 0x8000 18208 #define RX1_ANARXACONTROL2_IMAX_CTAT_ALIGN 0 18209 #define RX1_ANARXACONTROL2_IMAX_CTAT_BITS 1 18210 #define RX1_ANARXACONTROL2_IMAX_CTAT_SHIFT 15 18211 18212 /* Rx1 :: anaRxAControl2 :: imode_ctat [14:14] */ 18213 #define RX1_ANARXACONTROL2_IMODE_CTAT_MASK 0x4000 18214 #define RX1_ANARXACONTROL2_IMODE_CTAT_ALIGN 0 18215 #define RX1_ANARXACONTROL2_IMODE_CTAT_BITS 1 18216 #define RX1_ANARXACONTROL2_IMODE_CTAT_SHIFT 14 18217 18218 /* Rx1 :: anaRxAControl2 :: imin_ctat [13:13] */ 18219 #define RX1_ANARXACONTROL2_IMIN_CTAT_MASK 0x2000 18220 #define RX1_ANARXACONTROL2_IMIN_CTAT_ALIGN 0 18221 #define RX1_ANARXACONTROL2_IMIN_CTAT_BITS 1 18222 #define RX1_ANARXACONTROL2_IMIN_CTAT_SHIFT 13 18223 18224 /* Rx1 :: anaRxAControl2 :: imax_eqfl [12:12] */ 18225 #define RX1_ANARXACONTROL2_IMAX_EQFL_MASK 0x1000 18226 #define RX1_ANARXACONTROL2_IMAX_EQFL_ALIGN 0 18227 #define RX1_ANARXACONTROL2_IMAX_EQFL_BITS 1 18228 #define RX1_ANARXACONTROL2_IMAX_EQFL_SHIFT 12 18229 18230 /* Rx1 :: anaRxAControl2 :: imode_eqfl [11:11] */ 18231 #define RX1_ANARXACONTROL2_IMODE_EQFL_MASK 0x0800 18232 #define RX1_ANARXACONTROL2_IMODE_EQFL_ALIGN 0 18233 #define RX1_ANARXACONTROL2_IMODE_EQFL_BITS 1 18234 #define RX1_ANARXACONTROL2_IMODE_EQFL_SHIFT 11 18235 18236 /* Rx1 :: anaRxAControl2 :: imin_eqfl [10:10] */ 18237 #define RX1_ANARXACONTROL2_IMIN_EQFL_MASK 0x0400 18238 #define RX1_ANARXACONTROL2_IMIN_EQFL_ALIGN 0 18239 #define RX1_ANARXACONTROL2_IMIN_EQFL_BITS 1 18240 #define RX1_ANARXACONTROL2_IMIN_EQFL_SHIFT 10 18241 18242 /* Rx1 :: anaRxAControl2 :: imax_dfesum [09:09] */ 18243 #define RX1_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 18244 #define RX1_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 18245 #define RX1_ANARXACONTROL2_IMAX_DFESUM_BITS 1 18246 #define RX1_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 18247 18248 /* Rx1 :: anaRxAControl2 :: imode_dfesum [08:08] */ 18249 #define RX1_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 18250 #define RX1_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 18251 #define RX1_ANARXACONTROL2_IMODE_DFESUM_BITS 1 18252 #define RX1_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 18253 18254 /* Rx1 :: anaRxAControl2 :: imin_dfesum [07:07] */ 18255 #define RX1_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 18256 #define RX1_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 18257 #define RX1_ANARXACONTROL2_IMIN_DFESUM_BITS 1 18258 #define RX1_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 18259 18260 /* Rx1 :: anaRxAControl2 :: imax_vga [06:06] */ 18261 #define RX1_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 18262 #define RX1_ANARXACONTROL2_IMAX_VGA_ALIGN 0 18263 #define RX1_ANARXACONTROL2_IMAX_VGA_BITS 1 18264 #define RX1_ANARXACONTROL2_IMAX_VGA_SHIFT 6 18265 18266 /* Rx1 :: anaRxAControl2 :: imode_vga [05:05] */ 18267 #define RX1_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 18268 #define RX1_ANARXACONTROL2_IMODE_VGA_ALIGN 0 18269 #define RX1_ANARXACONTROL2_IMODE_VGA_BITS 1 18270 #define RX1_ANARXACONTROL2_IMODE_VGA_SHIFT 5 18271 18272 /* Rx1 :: anaRxAControl2 :: imin_vga [04:04] */ 18273 #define RX1_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 18274 #define RX1_ANARXACONTROL2_IMIN_VGA_ALIGN 0 18275 #define RX1_ANARXACONTROL2_IMIN_VGA_BITS 1 18276 #define RX1_ANARXACONTROL2_IMIN_VGA_SHIFT 4 18277 18278 /* Rx1 :: anaRxAControl2 :: imax_interp [03:03] */ 18279 #define RX1_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 18280 #define RX1_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 18281 #define RX1_ANARXACONTROL2_IMAX_INTERP_BITS 1 18282 #define RX1_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 18283 18284 /* Rx1 :: anaRxAControl2 :: imode_interp [02:02] */ 18285 #define RX1_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 18286 #define RX1_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 18287 #define RX1_ANARXACONTROL2_IMODE_INTERP_BITS 1 18288 #define RX1_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 18289 18290 /* Rx1 :: anaRxAControl2 :: imin_interp [01:01] */ 18291 #define RX1_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 18292 #define RX1_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 18293 #define RX1_ANARXACONTROL2_IMIN_INTERP_BITS 1 18294 #define RX1_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 18295 18296 /* Rx1 :: anaRxAControl2 :: imax_vcm [00:00] */ 18297 #define RX1_ANARXACONTROL2_IMAX_VCM_MASK 0x0001 18298 #define RX1_ANARXACONTROL2_IMAX_VCM_ALIGN 0 18299 #define RX1_ANARXACONTROL2_IMAX_VCM_BITS 1 18300 #define RX1_ANARXACONTROL2_IMAX_VCM_SHIFT 0 18301 18302 18303 /**************************************************************************** 18304 * Rx1 :: anaRxAControl3 18305 */ 18306 /* Rx1 :: anaRxAControl3 :: en_clk16 [15:15] */ 18307 #define RX1_ANARXACONTROL3_EN_CLK16_MASK 0x8000 18308 #define RX1_ANARXACONTROL3_EN_CLK16_ALIGN 0 18309 #define RX1_ANARXACONTROL3_EN_CLK16_BITS 1 18310 #define RX1_ANARXACONTROL3_EN_CLK16_SHIFT 15 18311 18312 /* Rx1 :: anaRxAControl3 :: en_clk33 [14:14] */ 18313 #define RX1_ANARXACONTROL3_EN_CLK33_MASK 0x4000 18314 #define RX1_ANARXACONTROL3_EN_CLK33_ALIGN 0 18315 #define RX1_ANARXACONTROL3_EN_CLK33_BITS 1 18316 #define RX1_ANARXACONTROL3_EN_CLK33_SHIFT 14 18317 18318 /* Rx1 :: anaRxAControl3 :: en_vcctrl [13:13] */ 18319 #define RX1_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 18320 #define RX1_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 18321 #define RX1_ANARXACONTROL3_EN_VCCTRL_BITS 1 18322 #define RX1_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 18323 18324 /* Rx1 :: anaRxAControl3 :: sel_th4dfe1 [12:12] */ 18325 #define RX1_ANARXACONTROL3_SEL_TH4DFE1_MASK 0x1000 18326 #define RX1_ANARXACONTROL3_SEL_TH4DFE1_ALIGN 0 18327 #define RX1_ANARXACONTROL3_SEL_TH4DFE1_BITS 1 18328 #define RX1_ANARXACONTROL3_SEL_TH4DFE1_SHIFT 12 18329 18330 /* Rx1 :: anaRxAControl3 :: sel_th4dfe0 [11:11] */ 18331 #define RX1_ANARXACONTROL3_SEL_TH4DFE0_MASK 0x0800 18332 #define RX1_ANARXACONTROL3_SEL_TH4DFE0_ALIGN 0 18333 #define RX1_ANARXACONTROL3_SEL_TH4DFE0_BITS 1 18334 #define RX1_ANARXACONTROL3_SEL_TH4DFE0_SHIFT 11 18335 18336 /* Rx1 :: anaRxAControl3 :: selugbw1 [10:10] */ 18337 #define RX1_ANARXACONTROL3_SELUGBW1_MASK 0x0400 18338 #define RX1_ANARXACONTROL3_SELUGBW1_ALIGN 0 18339 #define RX1_ANARXACONTROL3_SELUGBW1_BITS 1 18340 #define RX1_ANARXACONTROL3_SELUGBW1_SHIFT 10 18341 18342 /* Rx1 :: anaRxAControl3 :: selugbw0 [09:09] */ 18343 #define RX1_ANARXACONTROL3_SELUGBW0_MASK 0x0200 18344 #define RX1_ANARXACONTROL3_SELUGBW0_ALIGN 0 18345 #define RX1_ANARXACONTROL3_SELUGBW0_BITS 1 18346 #define RX1_ANARXACONTROL3_SELUGBW0_SHIFT 9 18347 18348 /* Rx1 :: anaRxAControl3 :: imax_dfetap [08:08] */ 18349 #define RX1_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 18350 #define RX1_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 18351 #define RX1_ANARXACONTROL3_IMAX_DFETAP_BITS 1 18352 #define RX1_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 18353 18354 /* Rx1 :: anaRxAControl3 :: imode_dfetap [07:07] */ 18355 #define RX1_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 18356 #define RX1_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 18357 #define RX1_ANARXACONTROL3_IMODE_DFETAP_BITS 1 18358 #define RX1_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 18359 18360 /* Rx1 :: anaRxAControl3 :: imin_dfetap [06:06] */ 18361 #define RX1_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 18362 #define RX1_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 18363 #define RX1_ANARXACONTROL3_IMIN_DFETAP_BITS 1 18364 #define RX1_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 18365 18366 /* Rx1 :: anaRxAControl3 :: imax_slcd2c [05:05] */ 18367 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 18368 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 18369 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 18370 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 18371 18372 /* Rx1 :: anaRxAControl3 :: imode_slcd2c [04:04] */ 18373 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 18374 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 18375 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 18376 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 18377 18378 /* Rx1 :: anaRxAControl3 :: imin_slcd2c [03:03] */ 18379 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 18380 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 18381 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 18382 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 18383 18384 /* Rx1 :: anaRxAControl3 :: imax_dfevref [02:02] */ 18385 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 18386 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 18387 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 18388 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 18389 18390 /* Rx1 :: anaRxAControl3 :: imode_dfevref [01:01] */ 18391 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 18392 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 18393 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 18394 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 18395 18396 /* Rx1 :: anaRxAControl3 :: imin_dfevref [00:00] */ 18397 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 18398 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 18399 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 18400 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 18401 18402 18403 /**************************************************************************** 18404 * Warpcore_USER_Rx2 18405 */ 18406 /**************************************************************************** 18407 * Rx2 :: anaRxStatus 18408 */ 18409 /* union - case sigdet_Status [15:00] */ 18410 /* Rx2 :: anaRxStatus :: cx4_sigdet [15:15] */ 18411 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 18412 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 18413 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 18414 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 18415 18416 /* Rx2 :: anaRxStatus :: reserved0 [14:13] */ 18417 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 18418 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 18419 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS 2 18420 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 18421 18422 /* Rx2 :: anaRxStatus :: rxSeqDone [12:12] */ 18423 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 18424 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 18425 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 18426 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 18427 18428 /* Rx2 :: anaRxStatus :: rx_sigdet_ll [11:11] */ 18429 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 18430 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 18431 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 18432 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 18433 18434 /* Rx2 :: anaRxStatus :: cs4_sigdet_ll [10:10] */ 18435 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 18436 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 18437 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 18438 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 18439 18440 /* Rx2 :: anaRxStatus :: rx_reset [09:09] */ 18441 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 18442 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 18443 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS 1 18444 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 18445 18446 /* Rx2 :: anaRxStatus :: rx_pwrdn [08:08] */ 18447 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 18448 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 18449 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 18450 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 18451 18452 /* Rx2 :: anaRxStatus :: reserved1 [07:00] */ 18453 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 18454 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 18455 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS 8 18456 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 18457 18458 18459 /* union - case sync_Status [15:00] */ 18460 /* Rx2 :: anaRxStatus :: reserved0 [15:11] */ 18461 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 18462 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN 0 18463 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS 5 18464 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT 11 18465 18466 /* Rx2 :: anaRxStatus :: test_acq_en [10:10] */ 18467 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 18468 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 18469 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 18470 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 18471 18472 /* Rx2 :: anaRxStatus :: reserved1 [09:09] */ 18473 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 18474 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN 0 18475 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS 1 18476 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT 9 18477 18478 /* Rx2 :: anaRxStatus :: rxSeqStart [08:08] */ 18479 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 18480 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 18481 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS 1 18482 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 18483 18484 /* Rx2 :: anaRxStatus :: mux_comadj_sync_status [07:07] */ 18485 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 18486 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 18487 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 18488 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 18489 18490 /* Rx2 :: anaRxStatus :: sync_status [06:06] */ 18491 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 18492 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 18493 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 18494 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 18495 18496 /* Rx2 :: anaRxStatus :: rx_sigdet [05:05] */ 18497 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 18498 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 18499 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS 1 18500 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 18501 18502 /* Rx2 :: anaRxStatus :: reserved2 [04:03] */ 18503 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 18504 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN 0 18505 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS 2 18506 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT 3 18507 18508 /* Rx2 :: anaRxStatus :: saturate_status [02:02] */ 18509 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 18510 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 18511 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 18512 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 18513 18514 /* Rx2 :: anaRxStatus :: cx4_sigdet [01:01] */ 18515 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 18516 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 18517 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 18518 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 18519 18520 /* Rx2 :: anaRxStatus :: rxSeqDone [00:00] */ 18521 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 18522 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 18523 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS 1 18524 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 18525 18526 18527 /* union - case rxTestSel_0 [15:00] */ 18528 /* Rx2 :: anaRxStatus :: reserved0 [15:10] */ 18529 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 18530 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 18531 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS 6 18532 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 18533 18534 /* Rx2 :: anaRxStatus :: indck_mode_en [09:09] */ 18535 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 18536 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 18537 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 18538 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 18539 18540 /* Rx2 :: anaRxStatus :: pci_mode_en [08:08] */ 18541 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 18542 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 18543 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 18544 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 18545 18546 /* Rx2 :: anaRxStatus :: rx_polarity [07:07] */ 18547 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 18548 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 18549 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 18550 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 18551 18552 /* Rx2 :: anaRxStatus :: rxpol_flip [06:06] */ 18553 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 18554 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 18555 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 18556 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 18557 18558 /* Rx2 :: anaRxStatus :: comma_mask [05:05] */ 18559 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 18560 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 18561 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 18562 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 18563 18564 /* Rx2 :: anaRxStatus :: link_en_r [04:04] */ 18565 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 18566 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 18567 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 18568 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 18569 18570 /* Rx2 :: anaRxStatus :: comma_adj_en [03:03] */ 18571 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 18572 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 18573 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 18574 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 18575 18576 /* Rx2 :: anaRxStatus :: comma_adj_en_ext [02:02] */ 18577 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 18578 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 18579 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 18580 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 18581 18582 /* Rx2 :: anaRxStatus :: reserved1 [01:00] */ 18583 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 18584 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 18585 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS 2 18586 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 18587 18588 18589 /* union - case rxTestSel_1 [15:00] */ 18590 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */ 18591 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 18592 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 18593 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS 11 18594 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 18595 18596 /* Rx2 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */ 18597 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 18598 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 18599 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 18600 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 18601 18602 /* Rx2 :: anaRxStatus :: freq_sel_PC [03:03] */ 18603 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 18604 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 18605 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 18606 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 18607 18608 /* Rx2 :: anaRxStatus :: freq_sel_SM [02:02] */ 18609 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 18610 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 18611 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 18612 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 18613 18614 /* Rx2 :: anaRxStatus :: integ_mode_SM [01:00] */ 18615 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 18616 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 18617 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 18618 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 18619 18620 18621 /* union - case scale_Status [15:00] */ 18622 /* Rx2 :: anaRxStatus :: prop_scale [15:12] */ 18623 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 18624 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 18625 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS 4 18626 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 18627 18628 /* Rx2 :: anaRxStatus :: integ_scale [11:08] */ 18629 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 18630 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 18631 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 18632 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 18633 18634 /* Rx2 :: anaRxStatus :: prop_scale_acq [07:04] */ 18635 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 18636 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 18637 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 18638 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 18639 18640 /* Rx2 :: anaRxStatus :: integ_scale_acq [03:00] */ 18641 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 18642 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 18643 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 18644 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 18645 18646 18647 /* union - case adc_CdrStatus1 [15:00] */ 18648 /* Rx2 :: anaRxStatus :: reserved0 [15:07] */ 18649 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 18650 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 18651 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 18652 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 18653 18654 /* Rx2 :: anaRxStatus :: rxMuxCkSel [06:06] */ 18655 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 18656 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 18657 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 18658 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 18659 18660 /* Rx2 :: anaRxStatus :: glpbk_combo [05:05] */ 18661 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 18662 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 18663 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 18664 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 18665 18666 /* Rx2 :: anaRxStatus :: clockSwitchSel [04:04] */ 18667 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 18668 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 18669 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 18670 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 18671 18672 /* Rx2 :: anaRxStatus :: rxck_tst [03:03] */ 18673 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 18674 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 18675 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 18676 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 18677 18678 /* Rx2 :: anaRxStatus :: rxck_i [02:02] */ 18679 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 18680 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 18681 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 18682 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 18683 18684 /* Rx2 :: anaRxStatus :: refclk [01:01] */ 18685 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 18686 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 18687 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 18688 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 18689 18690 /* Rx2 :: anaRxStatus :: pll_bypass [00:00] */ 18691 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 18692 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 18693 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 18694 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 18695 18696 18697 /* union - case adc_CdrStatus2 [15:00] */ 18698 /* Rx2 :: anaRxStatus :: reserved0 [15:06] */ 18699 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 18700 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 18701 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 18702 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 18703 18704 /* Rx2 :: anaRxStatus :: rxMuxCkSel [05:05] */ 18705 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 18706 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 18707 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 18708 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 18709 18710 /* Rx2 :: anaRxStatus :: rxSeqStart [04:04] */ 18711 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 18712 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 18713 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 18714 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 18715 18716 /* Rx2 :: anaRxStatus :: reserved1 [03:01] */ 18717 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 18718 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 18719 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 18720 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 18721 18722 /* Rx2 :: anaRxStatus :: rxSeqDone [00:00] */ 18723 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 18724 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 18725 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 18726 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 18727 18728 18729 /* union - case adc_CdrStatus3 [15:00] */ 18730 /* Rx2 :: anaRxStatus :: reserved0 [15:04] */ 18731 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 18732 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 18733 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 18734 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 18735 18736 /* Rx2 :: anaRxStatus :: rxSeqStart [03:03] */ 18737 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 18738 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 18739 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 18740 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 18741 18742 /* Rx2 :: anaRxStatus :: reserved1 [02:01] */ 18743 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 18744 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 18745 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 18746 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 18747 18748 /* Rx2 :: anaRxStatus :: allow_increment_PC [00:00] */ 18749 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 18750 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 18751 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 18752 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 18753 18754 18755 /* union - case adc_CdrStatus4 [15:00] */ 18756 /* Rx2 :: anaRxStatus :: reserved0 [15:08] */ 18757 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 18758 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 18759 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 18760 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 18761 18762 /* Rx2 :: anaRxStatus :: rx_pwrdn [07:07] */ 18763 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 18764 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 18765 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 18766 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 18767 18768 /* Rx2 :: anaRxStatus :: freq_sel [06:06] */ 18769 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 18770 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 18771 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 18772 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 18773 18774 /* Rx2 :: anaRxStatus :: pll_lock_rstb [05:05] */ 18775 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 18776 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 18777 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 18778 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 18779 18780 /* Rx2 :: anaRxStatus :: pwrdn [04:04] */ 18781 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 18782 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 18783 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 18784 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 18785 18786 /* Rx2 :: anaRxStatus :: reserved1 [03:00] */ 18787 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 18788 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 18789 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 18790 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 18791 18792 18793 /* union - case adc_CdrStatus5 [15:00] */ 18794 /* Rx2 :: anaRxStatus :: reserved0 [15:00] */ 18795 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 18796 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 18797 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 18798 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 18799 18800 18801 /* union - case adc_CdrStatus6 [15:00] */ 18802 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */ 18803 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 18804 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 18805 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 18806 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 18807 18808 /* Rx2 :: anaRxStatus :: rx_reset [04:04] */ 18809 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 18810 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 18811 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 18812 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 18813 18814 /* Rx2 :: anaRxStatus :: rx_pwrdn [03:03] */ 18815 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 18816 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 18817 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 18818 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 18819 18820 /* Rx2 :: anaRxStatus :: reset_anlg [02:02] */ 18821 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 18822 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 18823 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 18824 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 18825 18826 /* Rx2 :: anaRxStatus :: pwrdn_rx [01:01] */ 18827 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 18828 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 18829 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 18830 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 18831 18832 /* Rx2 :: anaRxStatus :: pwrdn_pll [00:00] */ 18833 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 18834 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 18835 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 18836 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 18837 18838 18839 /* union - case adc_CdrStatus7e [15:00] */ 18840 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */ 18841 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 18842 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 18843 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 18844 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 18845 18846 /* Rx2 :: anaRxStatus :: rxck0_even [04:04] */ 18847 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 18848 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 18849 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 18850 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 18851 18852 /* Rx2 :: anaRxStatus :: rxck1_even [03:03] */ 18853 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 18854 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 18855 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 18856 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 18857 18858 /* Rx2 :: anaRxStatus :: comdet_even [02:02] */ 18859 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 18860 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 18861 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 18862 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 18863 18864 /* Rx2 :: anaRxStatus :: en_cdet_even [01:01] */ 18865 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 18866 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 18867 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 18868 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 18869 18870 /* Rx2 :: anaRxStatus :: comma_adj_en_even [00:00] */ 18871 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 18872 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 18873 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 18874 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 18875 18876 18877 /* union - case adc_CdrStatus7o [15:00] */ 18878 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */ 18879 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 18880 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 18881 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 18882 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 18883 18884 /* Rx2 :: anaRxStatus :: rxck0_odd [04:04] */ 18885 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 18886 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 18887 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 18888 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 18889 18890 /* Rx2 :: anaRxStatus :: rxck1_odd [03:03] */ 18891 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 18892 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 18893 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 18894 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 18895 18896 /* Rx2 :: anaRxStatus :: comdet_odd [02:02] */ 18897 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 18898 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 18899 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 18900 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 18901 18902 /* Rx2 :: anaRxStatus :: en_cdet_odd [01:01] */ 18903 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 18904 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 18905 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 18906 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 18907 18908 /* Rx2 :: anaRxStatus :: comma_adj_en_odd [00:00] */ 18909 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 18910 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 18911 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 18912 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 18913 18914 18915 /* union - case adc_CdrStatus8 [15:00] */ 18916 /* Rx2 :: anaRxStatus :: reserved0 [15:01] */ 18917 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 18918 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 18919 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 18920 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 18921 18922 /* Rx2 :: anaRxStatus :: sigdet [00:00] */ 18923 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 18924 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 18925 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 18926 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 18927 18928 18929 /* union - case adc_CdrStatus9 [15:00] */ 18930 /* Rx2 :: anaRxStatus :: reserved0 [15:00] */ 18931 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 18932 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 18933 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 18934 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 18935 18936 18937 /* union - case adc_CdrStatus10 [15:00] */ 18938 /* Rx2 :: anaRxStatus :: reserved0 [15:07] */ 18939 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 18940 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 18941 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 18942 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 18943 18944 /* Rx2 :: anaRxStatus :: prbs_en [06:06] */ 18945 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 18946 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 18947 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 18948 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 18949 18950 /* Rx2 :: anaRxStatus :: rstb_tst [05:05] */ 18951 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 18952 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 18953 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 18954 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 18955 18956 /* Rx2 :: anaRxStatus :: reserved1 [04:04] */ 18957 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 18958 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 18959 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 18960 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 18961 18962 /* Rx2 :: anaRxStatus :: prbs_state [03:00] */ 18963 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 18964 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 18965 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 18966 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 18967 18968 18969 /* union - case adc_CdrStatus11 [15:00] */ 18970 /* Rx2 :: anaRxStatus :: reserved0 [15:00] */ 18971 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 18972 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 18973 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 18974 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 18975 18976 18977 /* union - case adc_CdrStatus12_1 [15:00] */ 18978 /* Rx2 :: anaRxStatus :: reserved0 [15:06] */ 18979 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 18980 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 18981 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 18982 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 18983 18984 /* Rx2 :: anaRxStatus :: enable4 [05:05] */ 18985 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 18986 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 18987 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 18988 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 18989 18990 /* Rx2 :: anaRxStatus :: radr_test [04:00] */ 18991 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 18992 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 18993 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 18994 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 18995 18996 18997 /* union - case adc_CdrStatus12_2 [15:00] */ 18998 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */ 18999 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 19000 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 19001 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 19002 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 19003 19004 /* Rx2 :: anaRxStatus :: wadr_test [04:00] */ 19005 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 19006 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 19007 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 19008 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 19009 19010 19011 /* union - case adc_CdrStatus12_3 [15:00] */ 19012 /* Rx2 :: anaRxStatus :: reserved0 [15:06] */ 19013 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 19014 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 19015 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 19016 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 19017 19018 /* Rx2 :: anaRxStatus :: rxck_66B_tmux [05:05] */ 19019 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 19020 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 19021 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 19022 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 19023 19024 /* Rx2 :: anaRxStatus :: rstb_66B [04:04] */ 19025 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 19026 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 19027 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 19028 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 19029 19030 /* Rx2 :: anaRxStatus :: prstb_66B_mux [03:03] */ 19031 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 19032 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 19033 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 19034 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 19035 19036 /* Rx2 :: anaRxStatus :: rxck_i66_tmux [02:02] */ 19037 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 19038 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 19039 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 19040 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 19041 19042 /* Rx2 :: anaRxStatus :: rstb_i66 [01:01] */ 19043 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 19044 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 19045 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 19046 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 19047 19048 /* Rx2 :: anaRxStatus :: prstb_i66_mux [00:00] */ 19049 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 19050 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 19051 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 19052 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 19053 19054 19055 /* union - case adc_CdrStatus12_4 [15:00] */ 19056 /* Rx2 :: anaRxStatus :: reserved0 [15:04] */ 19057 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 19058 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 19059 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 19060 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 19061 19062 /* Rx2 :: anaRxStatus :: rfifo_error_r [03:02] */ 19063 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 19064 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 19065 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 19066 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 19067 19068 /* Rx2 :: anaRxStatus :: rfifo_unflow [01:01] */ 19069 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 19070 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 19071 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 19072 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 19073 19074 /* Rx2 :: anaRxStatus :: rfifo_ovflow [00:00] */ 19075 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 19076 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 19077 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 19078 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 19079 19080 19081 /* union - case integ_Status [15:00] */ 19082 /* Rx2 :: anaRxStatus :: integ_status [15:00] */ 19083 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 19084 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 19085 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 19086 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 19087 19088 19089 /* union - case vco_Status [15:00] */ 19090 /* Rx2 :: anaRxStatus :: vco_status [15:00] */ 19091 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 19092 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 19093 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS 16 19094 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 19095 19096 19097 /* union - case prbs_Status [15:00] */ 19098 /* Rx2 :: anaRxStatus :: prbs_lock [15:15] */ 19099 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 19100 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 19101 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 19102 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 19103 19104 /* Rx2 :: anaRxStatus :: prbs_stky [14:14] */ 19105 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 19106 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 19107 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS 1 19108 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 19109 19110 /* Rx2 :: anaRxStatus :: prbs_errors [13:00] */ 19111 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_MASK 0x3fff 19112 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_ALIGN 0 19113 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_BITS 14 19114 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_SHIFT 0 19115 19116 19117 19118 /**************************************************************************** 19119 * Rx2 :: anaRxControl 19120 */ 19121 /* Rx2 :: anaRxControl :: reserved0 [15:10] */ 19122 #define RX2_ANARXCONTROL_RESERVED0_MASK 0xfc00 19123 #define RX2_ANARXCONTROL_RESERVED0_ALIGN 0 19124 #define RX2_ANARXCONTROL_RESERVED0_BITS 6 19125 #define RX2_ANARXCONTROL_RESERVED0_SHIFT 10 19126 19127 /* Rx2 :: anaRxControl :: override_sigdet_en [09:09] */ 19128 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 19129 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 19130 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 19131 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 19132 19133 /* Rx2 :: anaRxControl :: override_sigdet_val [08:08] */ 19134 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 19135 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 19136 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 19137 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 19138 19139 /* Rx2 :: anaRxControl :: reserved1 [07:03] */ 19140 #define RX2_ANARXCONTROL_RESERVED1_MASK 0x00f8 19141 #define RX2_ANARXCONTROL_RESERVED1_ALIGN 0 19142 #define RX2_ANARXCONTROL_RESERVED1_BITS 5 19143 #define RX2_ANARXCONTROL_RESERVED1_SHIFT 3 19144 19145 /* Rx2 :: anaRxControl :: status_sel [02:00] */ 19146 #define RX2_ANARXCONTROL_STATUS_SEL_MASK 0x0007 19147 #define RX2_ANARXCONTROL_STATUS_SEL_ALIGN 0 19148 #define RX2_ANARXCONTROL_STATUS_SEL_BITS 3 19149 #define RX2_ANARXCONTROL_STATUS_SEL_SHIFT 0 19150 #define RX2_ANARXCONTROL_STATUS_SEL_sigdetStatus 0 19151 #define RX2_ANARXCONTROL_STATUS_SEL_syncStatus 1 19152 #define RX2_ANARXCONTROL_STATUS_SEL_rxTestSel 2 19153 #define RX2_ANARXCONTROL_STATUS_SEL_scaleStatus 3 19154 #define RX2_ANARXCONTROL_STATUS_SEL_adcCdrStatus 4 19155 #define RX2_ANARXCONTROL_STATUS_SEL_integStatus 5 19156 #define RX2_ANARXCONTROL_STATUS_SEL_vcoStatus 6 19157 #define RX2_ANARXCONTROL_STATUS_SEL_prbsStatus 7 19158 19159 19160 /**************************************************************************** 19161 * Rx2 :: anaRxSigdet 19162 */ 19163 /* Rx2 :: anaRxSigdet :: sigdetTime_SM [15:08] */ 19164 #define RX2_ANARXSIGDET_SIGDETTIME_SM_MASK 0xff00 19165 #define RX2_ANARXSIGDET_SIGDETTIME_SM_ALIGN 0 19166 #define RX2_ANARXSIGDET_SIGDETTIME_SM_BITS 8 19167 #define RX2_ANARXSIGDET_SIGDETTIME_SM_SHIFT 8 19168 19169 /* Rx2 :: anaRxSigdet :: cx4_sigdet_cnt_ld_SM [07:07] */ 19170 #define RX2_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_MASK 0x0080 19171 #define RX2_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_ALIGN 0 19172 #define RX2_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_BITS 1 19173 #define RX2_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_SHIFT 7 19174 19175 /* Rx2 :: anaRxSigdet :: ext_sigdet_en_SM [06:06] */ 19176 #define RX2_ANARXSIGDET_EXT_SIGDET_EN_SM_MASK 0x0040 19177 #define RX2_ANARXSIGDET_EXT_SIGDET_EN_SM_ALIGN 0 19178 #define RX2_ANARXSIGDET_EXT_SIGDET_EN_SM_BITS 1 19179 #define RX2_ANARXSIGDET_EXT_SIGDET_EN_SM_SHIFT 6 19180 19181 /* Rx2 :: anaRxSigdet :: cx4_sigdet_en_SM [05:05] */ 19182 #define RX2_ANARXSIGDET_CX4_SIGDET_EN_SM_MASK 0x0020 19183 #define RX2_ANARXSIGDET_CX4_SIGDET_EN_SM_ALIGN 0 19184 #define RX2_ANARXSIGDET_CX4_SIGDET_EN_SM_BITS 1 19185 #define RX2_ANARXSIGDET_CX4_SIGDET_EN_SM_SHIFT 5 19186 19187 /* Rx2 :: anaRxSigdet :: rx_sigdet_r [04:04] */ 19188 #define RX2_ANARXSIGDET_RX_SIGDET_R_MASK 0x0010 19189 #define RX2_ANARXSIGDET_RX_SIGDET_R_ALIGN 0 19190 #define RX2_ANARXSIGDET_RX_SIGDET_R_BITS 1 19191 #define RX2_ANARXSIGDET_RX_SIGDET_R_SHIFT 4 19192 19193 /* Rx2 :: anaRxSigdet :: rx_sigdet_force_r [03:03] */ 19194 #define RX2_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK 0x0008 19195 #define RX2_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN 0 19196 #define RX2_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS 1 19197 #define RX2_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT 3 19198 19199 /* Rx2 :: anaRxSigdet :: invert_rx_sigdet [02:02] */ 19200 #define RX2_ANARXSIGDET_INVERT_RX_SIGDET_MASK 0x0004 19201 #define RX2_ANARXSIGDET_INVERT_RX_SIGDET_ALIGN 0 19202 #define RX2_ANARXSIGDET_INVERT_RX_SIGDET_BITS 1 19203 #define RX2_ANARXSIGDET_INVERT_RX_SIGDET_SHIFT 2 19204 19205 /* Rx2 :: anaRxSigdet :: reserved0 [01:00] */ 19206 #define RX2_ANARXSIGDET_RESERVED0_MASK 0x0003 19207 #define RX2_ANARXSIGDET_RESERVED0_ALIGN 0 19208 #define RX2_ANARXSIGDET_RESERVED0_BITS 2 19209 #define RX2_ANARXSIGDET_RESERVED0_SHIFT 0 19210 19211 19212 /**************************************************************************** 19213 * Rx2 :: anaRxAControl4 19214 */ 19215 /* Rx2 :: anaRxAControl4 :: ana_clt4 [15:00] */ 19216 #define RX2_ANARXACONTROL4_ANA_CLT4_MASK 0xffff 19217 #define RX2_ANARXACONTROL4_ANA_CLT4_ALIGN 0 19218 #define RX2_ANARXACONTROL4_ANA_CLT4_BITS 16 19219 #define RX2_ANARXACONTROL4_ANA_CLT4_SHIFT 0 19220 19221 19222 /**************************************************************************** 19223 * Rx2 :: anaRxControl2_1G 19224 */ 19225 /* Rx2 :: anaRxControl2_1G :: reserved0 [15:15] */ 19226 #define RX2_ANARXCONTROL2_1G_RESERVED0_MASK 0x8000 19227 #define RX2_ANARXCONTROL2_1G_RESERVED0_ALIGN 0 19228 #define RX2_ANARXCONTROL2_1G_RESERVED0_BITS 1 19229 #define RX2_ANARXCONTROL2_1G_RESERVED0_SHIFT 15 19230 19231 /* Rx2 :: anaRxControl2_1G :: rx_prbs_w_val [14:14] */ 19232 #define RX2_ANARXCONTROL2_1G_RX_PRBS_W_VAL_MASK 0x4000 19233 #define RX2_ANARXCONTROL2_1G_RX_PRBS_W_VAL_ALIGN 0 19234 #define RX2_ANARXCONTROL2_1G_RX_PRBS_W_VAL_BITS 1 19235 #define RX2_ANARXCONTROL2_1G_RX_PRBS_W_VAL_SHIFT 14 19236 19237 /* Rx2 :: anaRxControl2_1G :: rx_prbs_w_force [13:13] */ 19238 #define RX2_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_MASK 0x2000 19239 #define RX2_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_ALIGN 0 19240 #define RX2_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_BITS 1 19241 #define RX2_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_SHIFT 13 19242 19243 /* Rx2 :: anaRxControl2_1G :: rx_prbs_bswap [12:12] */ 19244 #define RX2_ANARXCONTROL2_1G_RX_PRBS_BSWAP_MASK 0x1000 19245 #define RX2_ANARXCONTROL2_1G_RX_PRBS_BSWAP_ALIGN 0 19246 #define RX2_ANARXCONTROL2_1G_RX_PRBS_BSWAP_BITS 1 19247 #define RX2_ANARXCONTROL2_1G_RX_PRBS_BSWAP_SHIFT 12 19248 19249 /* Rx2 :: anaRxControl2_1G :: rx_bitswap [11:11] */ 19250 #define RX2_ANARXCONTROL2_1G_RX_BITSWAP_MASK 0x0800 19251 #define RX2_ANARXCONTROL2_1G_RX_BITSWAP_ALIGN 0 19252 #define RX2_ANARXCONTROL2_1G_RX_BITSWAP_BITS 1 19253 #define RX2_ANARXCONTROL2_1G_RX_BITSWAP_SHIFT 11 19254 19255 /* Rx2 :: anaRxControl2_1G :: rst_rx_r [10:10] */ 19256 #define RX2_ANARXCONTROL2_1G_RST_RX_R_MASK 0x0400 19257 #define RX2_ANARXCONTROL2_1G_RST_RX_R_ALIGN 0 19258 #define RX2_ANARXCONTROL2_1G_RST_RX_R_BITS 1 19259 #define RX2_ANARXCONTROL2_1G_RST_RX_R_SHIFT 10 19260 19261 /* Rx2 :: anaRxControl2_1G :: pwdwn_rx_r [09:09] */ 19262 #define RX2_ANARXCONTROL2_1G_PWDWN_RX_R_MASK 0x0200 19263 #define RX2_ANARXCONTROL2_1G_PWDWN_RX_R_ALIGN 0 19264 #define RX2_ANARXCONTROL2_1G_PWDWN_RX_R_BITS 1 19265 #define RX2_ANARXCONTROL2_1G_PWDWN_RX_R_SHIFT 9 19266 19267 /* Rx2 :: anaRxControl2_1G :: prbs_order_rx_r_2 [08:08] */ 19268 #define RX2_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_MASK 0x0100 19269 #define RX2_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_ALIGN 0 19270 #define RX2_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_BITS 1 19271 #define RX2_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_SHIFT 8 19272 19273 /* Rx2 :: anaRxControl2_1G :: reserved1 [07:07] */ 19274 #define RX2_ANARXCONTROL2_1G_RESERVED1_MASK 0x0080 19275 #define RX2_ANARXCONTROL2_1G_RESERVED1_ALIGN 0 19276 #define RX2_ANARXCONTROL2_1G_RESERVED1_BITS 1 19277 #define RX2_ANARXCONTROL2_1G_RESERVED1_SHIFT 7 19278 19279 /* Rx2 :: anaRxControl2_1G :: prbs_sel_rx_r [06:06] */ 19280 #define RX2_ANARXCONTROL2_1G_PRBS_SEL_RX_R_MASK 0x0040 19281 #define RX2_ANARXCONTROL2_1G_PRBS_SEL_RX_R_ALIGN 0 19282 #define RX2_ANARXCONTROL2_1G_PRBS_SEL_RX_R_BITS 1 19283 #define RX2_ANARXCONTROL2_1G_PRBS_SEL_RX_R_SHIFT 6 19284 19285 /* Rx2 :: anaRxControl2_1G :: prbs_en_rx_r [05:05] */ 19286 #define RX2_ANARXCONTROL2_1G_PRBS_EN_RX_R_MASK 0x0020 19287 #define RX2_ANARXCONTROL2_1G_PRBS_EN_RX_R_ALIGN 0 19288 #define RX2_ANARXCONTROL2_1G_PRBS_EN_RX_R_BITS 1 19289 #define RX2_ANARXCONTROL2_1G_PRBS_EN_RX_R_SHIFT 5 19290 19291 /* Rx2 :: anaRxControl2_1G :: prbs_inv_rx_r [04:04] */ 19292 #define RX2_ANARXCONTROL2_1G_PRBS_INV_RX_R_MASK 0x0010 19293 #define RX2_ANARXCONTROL2_1G_PRBS_INV_RX_R_ALIGN 0 19294 #define RX2_ANARXCONTROL2_1G_PRBS_INV_RX_R_BITS 1 19295 #define RX2_ANARXCONTROL2_1G_PRBS_INV_RX_R_SHIFT 4 19296 19297 /* Rx2 :: anaRxControl2_1G :: prbs_order_rx_r [03:02] */ 19298 #define RX2_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_MASK 0x000c 19299 #define RX2_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_ALIGN 0 19300 #define RX2_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_BITS 2 19301 #define RX2_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_SHIFT 2 19302 19303 /* Rx2 :: anaRxControl2_1G :: reserved2 [01:01] */ 19304 #define RX2_ANARXCONTROL2_1G_RESERVED2_MASK 0x0002 19305 #define RX2_ANARXCONTROL2_1G_RESERVED2_ALIGN 0 19306 #define RX2_ANARXCONTROL2_1G_RESERVED2_BITS 1 19307 #define RX2_ANARXCONTROL2_1G_RESERVED2_SHIFT 1 19308 19309 /* Rx2 :: anaRxControl2_1G :: errcnt_15 [00:00] */ 19310 #define RX2_ANARXCONTROL2_1G_ERRCNT_15_MASK 0x0001 19311 #define RX2_ANARXCONTROL2_1G_ERRCNT_15_ALIGN 0 19312 #define RX2_ANARXCONTROL2_1G_ERRCNT_15_BITS 1 19313 #define RX2_ANARXCONTROL2_1G_ERRCNT_15_SHIFT 0 19314 19315 19316 /**************************************************************************** 19317 * Rx2 :: anaRxTest 19318 */ 19319 /* Rx2 :: anaRxTest :: sigdet_mux_SM [15:12] */ 19320 #define RX2_ANARXTEST_SIGDET_MUX_SM_MASK 0xf000 19321 #define RX2_ANARXTEST_SIGDET_MUX_SM_ALIGN 0 19322 #define RX2_ANARXTEST_SIGDET_MUX_SM_BITS 4 19323 #define RX2_ANARXTEST_SIGDET_MUX_SM_SHIFT 12 19324 19325 /* Rx2 :: anaRxTest :: reserved0 [11:09] */ 19326 #define RX2_ANARXTEST_RESERVED0_MASK 0x0e00 19327 #define RX2_ANARXTEST_RESERVED0_ALIGN 0 19328 #define RX2_ANARXTEST_RESERVED0_BITS 3 19329 #define RX2_ANARXTEST_RESERVED0_SHIFT 9 19330 19331 /* Rx2 :: anaRxTest :: tpctrl_SM [08:04] */ 19332 #define RX2_ANARXTEST_TPCTRL_SM_MASK 0x01f0 19333 #define RX2_ANARXTEST_TPCTRL_SM_ALIGN 0 19334 #define RX2_ANARXTEST_TPCTRL_SM_BITS 5 19335 #define RX2_ANARXTEST_TPCTRL_SM_SHIFT 4 19336 19337 /* Rx2 :: anaRxTest :: testMuxSelect_SM [03:00] */ 19338 #define RX2_ANARXTEST_TESTMUXSELECT_SM_MASK 0x000f 19339 #define RX2_ANARXTEST_TESTMUXSELECT_SM_ALIGN 0 19340 #define RX2_ANARXTEST_TESTMUXSELECT_SM_BITS 4 19341 #define RX2_ANARXTEST_TESTMUXSELECT_SM_SHIFT 0 19342 19343 19344 /**************************************************************************** 19345 * Rx2 :: anaRxControl1G 19346 */ 19347 /* Rx2 :: anaRxControl1G :: fpat_md [15:15] */ 19348 #define RX2_ANARXCONTROL1G_FPAT_MD_MASK 0x8000 19349 #define RX2_ANARXCONTROL1G_FPAT_MD_ALIGN 0 19350 #define RX2_ANARXCONTROL1G_FPAT_MD_BITS 1 19351 #define RX2_ANARXCONTROL1G_FPAT_MD_SHIFT 15 19352 19353 /* Rx2 :: anaRxControl1G :: pkt_count_en [14:14] */ 19354 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_MASK 0x4000 19355 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN 0 19356 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_BITS 1 19357 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT 14 19358 19359 /* Rx2 :: anaRxControl1G :: staMuxRegDis [13:13] */ 19360 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_MASK 0x2000 19361 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_ALIGN 0 19362 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_BITS 1 19363 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_SHIFT 13 19364 19365 /* Rx2 :: anaRxControl1G :: prbs_clr_dis [12:12] */ 19366 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_MASK 0x1000 19367 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN 0 19368 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_BITS 1 19369 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT 12 19370 19371 /* Rx2 :: anaRxControl1G :: rxd_dec_sel [11:11] */ 19372 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_MASK 0x0800 19373 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN 0 19374 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_BITS 1 19375 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT 11 19376 19377 /* Rx2 :: anaRxControl1G :: cgbad_tst [10:10] */ 19378 #define RX2_ANARXCONTROL1G_CGBAD_TST_MASK 0x0400 19379 #define RX2_ANARXCONTROL1G_CGBAD_TST_ALIGN 0 19380 #define RX2_ANARXCONTROL1G_CGBAD_TST_BITS 1 19381 #define RX2_ANARXCONTROL1G_CGBAD_TST_SHIFT 10 19382 19383 /* Rx2 :: anaRxControl1G :: Emon_en [09:09] */ 19384 #define RX2_ANARXCONTROL1G_EMON_EN_MASK 0x0200 19385 #define RX2_ANARXCONTROL1G_EMON_EN_ALIGN 0 19386 #define RX2_ANARXCONTROL1G_EMON_EN_BITS 1 19387 #define RX2_ANARXCONTROL1G_EMON_EN_SHIFT 9 19388 19389 /* Rx2 :: anaRxControl1G :: prbs_en [08:08] */ 19390 #define RX2_ANARXCONTROL1G_PRBS_EN_MASK 0x0100 19391 #define RX2_ANARXCONTROL1G_PRBS_EN_ALIGN 0 19392 #define RX2_ANARXCONTROL1G_PRBS_EN_BITS 1 19393 #define RX2_ANARXCONTROL1G_PRBS_EN_SHIFT 8 19394 19395 /* Rx2 :: anaRxControl1G :: cgbad_en [07:07] */ 19396 #define RX2_ANARXCONTROL1G_CGBAD_EN_MASK 0x0080 19397 #define RX2_ANARXCONTROL1G_CGBAD_EN_ALIGN 0 19398 #define RX2_ANARXCONTROL1G_CGBAD_EN_BITS 1 19399 #define RX2_ANARXCONTROL1G_CGBAD_EN_SHIFT 7 19400 19401 /* Rx2 :: anaRxControl1G :: cstretch [06:06] */ 19402 #define RX2_ANARXCONTROL1G_CSTRETCH_MASK 0x0040 19403 #define RX2_ANARXCONTROL1G_CSTRETCH_ALIGN 0 19404 #define RX2_ANARXCONTROL1G_CSTRETCH_BITS 1 19405 #define RX2_ANARXCONTROL1G_CSTRETCH_SHIFT 6 19406 19407 /* Rx2 :: anaRxControl1G :: comma_low_byte_SM [05:05] */ 19408 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK 0x0020 19409 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN 0 19410 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS 1 19411 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT 5 19412 19413 /* Rx2 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */ 19414 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 19415 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 19416 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS 1 19417 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 19418 19419 /* Rx2 :: anaRxControl1G :: reserved0 [03:02] */ 19420 #define RX2_ANARXCONTROL1G_RESERVED0_MASK 0x000c 19421 #define RX2_ANARXCONTROL1G_RESERVED0_ALIGN 0 19422 #define RX2_ANARXCONTROL1G_RESERVED0_BITS 2 19423 #define RX2_ANARXCONTROL1G_RESERVED0_SHIFT 2 19424 19425 /* Rx2 :: anaRxControl1G :: freq_sel_force [01:01] */ 19426 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK 0x0002 19427 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN 0 19428 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS 1 19429 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT 1 19430 19431 /* Rx2 :: anaRxControl1G :: freq_sel [00:00] */ 19432 #define RX2_ANARXCONTROL1G_FREQ_SEL_MASK 0x0001 19433 #define RX2_ANARXCONTROL1G_FREQ_SEL_ALIGN 0 19434 #define RX2_ANARXCONTROL1G_FREQ_SEL_BITS 1 19435 #define RX2_ANARXCONTROL1G_FREQ_SEL_SHIFT 0 19436 19437 19438 /**************************************************************************** 19439 * Rx2 :: anaRxControlPci 19440 */ 19441 /* Rx2 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */ 19442 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK 0x8000 19443 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN 0 19444 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS 1 19445 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT 15 19446 19447 /* Rx2 :: anaRxControlPci :: comma_mask_force_r [14:14] */ 19448 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK 0x4000 19449 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN 0 19450 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS 1 19451 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT 14 19452 19453 /* Rx2 :: anaRxControlPci :: comma_mask_r [13:13] */ 19454 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_MASK 0x2000 19455 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN 0 19456 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_BITS 1 19457 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT 13 19458 19459 /* Rx2 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */ 19460 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000 19461 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0 19462 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1 19463 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12 19464 19465 /* Rx2 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */ 19466 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK 0x0800 19467 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0 19468 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS 1 19469 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11 19470 19471 /* Rx2 :: anaRxControlPci :: sync_status_force_r [10:10] */ 19472 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK 0x0400 19473 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN 0 19474 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS 1 19475 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT 10 19476 19477 /* Rx2 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */ 19478 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200 19479 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0 19480 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1 19481 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9 19482 19483 /* Rx2 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */ 19484 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100 19485 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0 19486 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1 19487 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8 19488 19489 /* Rx2 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */ 19490 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080 19491 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0 19492 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1 19493 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7 19494 19495 /* Rx2 :: anaRxControlPci :: comma_adj_en_r [06:06] */ 19496 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK 0x0040 19497 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN 0 19498 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS 1 19499 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT 6 19500 19501 /* Rx2 :: anaRxControlPci :: link_en_force_SM [05:05] */ 19502 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK 0x0020 19503 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN 0 19504 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS 1 19505 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT 5 19506 19507 /* Rx2 :: anaRxControlPci :: link_en_r [04:04] */ 19508 #define RX2_ANARXCONTROLPCI_LINK_EN_R_MASK 0x0010 19509 #define RX2_ANARXCONTROLPCI_LINK_EN_R_ALIGN 0 19510 #define RX2_ANARXCONTROLPCI_LINK_EN_R_BITS 1 19511 #define RX2_ANARXCONTROLPCI_LINK_EN_R_SHIFT 4 19512 19513 /* Rx2 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */ 19514 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK 0x0008 19515 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN 0 19516 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS 1 19517 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT 3 19518 19519 /* Rx2 :: anaRxControlPci :: rx_polarity_r [02:02] */ 19520 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_MASK 0x0004 19521 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN 0 19522 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_BITS 1 19523 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT 2 19524 19525 /* Rx2 :: anaRxControlPci :: integ_mode_SM [01:00] */ 19526 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_MASK 0x0003 19527 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN 0 19528 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_BITS 2 19529 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT 0 19530 19531 19532 /**************************************************************************** 19533 * Rx2 :: anaRxAstatus 19534 */ 19535 /* Rx2 :: anaRxAstatus :: sigdet [15:15] */ 19536 #define RX2_ANARXASTATUS_SIGDET_MASK 0x8000 19537 #define RX2_ANARXASTATUS_SIGDET_ALIGN 0 19538 #define RX2_ANARXASTATUS_SIGDET_BITS 1 19539 #define RX2_ANARXASTATUS_SIGDET_SHIFT 15 19540 19541 /* Rx2 :: anaRxAstatus :: rx_pf [14:11] */ 19542 #define RX2_ANARXASTATUS_RX_PF_MASK 0x7800 19543 #define RX2_ANARXASTATUS_RX_PF_ALIGN 0 19544 #define RX2_ANARXASTATUS_RX_PF_BITS 4 19545 #define RX2_ANARXASTATUS_RX_PF_SHIFT 11 19546 19547 /* Rx2 :: anaRxAstatus :: tap1_dfe_gray [10:05] */ 19548 #define RX2_ANARXASTATUS_TAP1_DFE_GRAY_MASK 0x07e0 19549 #define RX2_ANARXASTATUS_TAP1_DFE_GRAY_ALIGN 0 19550 #define RX2_ANARXASTATUS_TAP1_DFE_GRAY_BITS 6 19551 #define RX2_ANARXASTATUS_TAP1_DFE_GRAY_SHIFT 5 19552 19553 /* Rx2 :: anaRxAstatus :: vga [04:00] */ 19554 #define RX2_ANARXASTATUS_VGA_MASK 0x001f 19555 #define RX2_ANARXASTATUS_VGA_ALIGN 0 19556 #define RX2_ANARXASTATUS_VGA_BITS 5 19557 #define RX2_ANARXASTATUS_VGA_SHIFT 0 19558 19559 19560 /**************************************************************************** 19561 * Rx2 :: anaRxAControl1 19562 */ 19563 /* Rx2 :: anaRxAControl1 :: imode_vcm [15:15] */ 19564 #define RX2_ANARXACONTROL1_IMODE_VCM_MASK 0x8000 19565 #define RX2_ANARXACONTROL1_IMODE_VCM_ALIGN 0 19566 #define RX2_ANARXACONTROL1_IMODE_VCM_BITS 1 19567 #define RX2_ANARXACONTROL1_IMODE_VCM_SHIFT 15 19568 19569 /* Rx2 :: anaRxAControl1 :: imin_vcm [14:14] */ 19570 #define RX2_ANARXACONTROL1_IMIN_VCM_MASK 0x4000 19571 #define RX2_ANARXACONTROL1_IMIN_VCM_ALIGN 0 19572 #define RX2_ANARXACONTROL1_IMIN_VCM_BITS 1 19573 #define RX2_ANARXACONTROL1_IMIN_VCM_SHIFT 14 19574 19575 /* Rx2 :: anaRxAControl1 :: imax_sigdet [13:13] */ 19576 #define RX2_ANARXACONTROL1_IMAX_SIGDET_MASK 0x2000 19577 #define RX2_ANARXACONTROL1_IMAX_SIGDET_ALIGN 0 19578 #define RX2_ANARXACONTROL1_IMAX_SIGDET_BITS 1 19579 #define RX2_ANARXACONTROL1_IMAX_SIGDET_SHIFT 13 19580 19581 /* Rx2 :: anaRxAControl1 :: imode_sigdet [12:12] */ 19582 #define RX2_ANARXACONTROL1_IMODE_SIGDET_MASK 0x1000 19583 #define RX2_ANARXACONTROL1_IMODE_SIGDET_ALIGN 0 19584 #define RX2_ANARXACONTROL1_IMODE_SIGDET_BITS 1 19585 #define RX2_ANARXACONTROL1_IMODE_SIGDET_SHIFT 12 19586 19587 /* Rx2 :: anaRxAControl1 :: imin_sigdet [11:11] */ 19588 #define RX2_ANARXACONTROL1_IMIN_SIGDET_MASK 0x0800 19589 #define RX2_ANARXACONTROL1_IMIN_SIGDET_ALIGN 0 19590 #define RX2_ANARXACONTROL1_IMIN_SIGDET_BITS 1 19591 #define RX2_ANARXACONTROL1_IMIN_SIGDET_SHIFT 11 19592 19593 /* Rx2 :: anaRxAControl1 :: refh_rx [10:10] */ 19594 #define RX2_ANARXACONTROL1_REFH_RX_MASK 0x0400 19595 #define RX2_ANARXACONTROL1_REFH_RX_ALIGN 0 19596 #define RX2_ANARXACONTROL1_REFH_RX_BITS 1 19597 #define RX2_ANARXACONTROL1_REFH_RX_SHIFT 10 19598 19599 /* Rx2 :: anaRxAControl1 :: refl_rx [09:09] */ 19600 #define RX2_ANARXACONTROL1_REFL_RX_MASK 0x0200 19601 #define RX2_ANARXACONTROL1_REFL_RX_ALIGN 0 19602 #define RX2_ANARXACONTROL1_REFL_RX_BITS 1 19603 #define RX2_ANARXACONTROL1_REFL_RX_SHIFT 9 19604 19605 /* Rx2 :: anaRxAControl1 :: tport_en [08:08] */ 19606 #define RX2_ANARXACONTROL1_TPORT_EN_MASK 0x0100 19607 #define RX2_ANARXACONTROL1_TPORT_EN_ALIGN 0 19608 #define RX2_ANARXACONTROL1_TPORT_EN_BITS 1 19609 #define RX2_ANARXACONTROL1_TPORT_EN_SHIFT 8 19610 19611 /* Rx2 :: anaRxAControl1 :: vddrb_bgb [07:07] */ 19612 #define RX2_ANARXACONTROL1_VDDRB_BGB_MASK 0x0080 19613 #define RX2_ANARXACONTROL1_VDDRB_BGB_ALIGN 0 19614 #define RX2_ANARXACONTROL1_VDDRB_BGB_BITS 1 19615 #define RX2_ANARXACONTROL1_VDDRB_BGB_SHIFT 7 19616 19617 /* Rx2 :: anaRxAControl1 :: sig_pwrdn [06:06] */ 19618 #define RX2_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 19619 #define RX2_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 19620 #define RX2_ANARXACONTROL1_SIG_PWRDN_BITS 1 19621 #define RX2_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 19622 19623 /* Rx2 :: anaRxAControl1 :: offset_ctrl [05:03] */ 19624 #define RX2_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 19625 #define RX2_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 19626 #define RX2_ANARXACONTROL1_OFFSET_CTRL_BITS 3 19627 #define RX2_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 19628 19629 /* Rx2 :: anaRxAControl1 :: offset_sel [02:02] */ 19630 #define RX2_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 19631 #define RX2_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 19632 #define RX2_ANARXACONTROL1_OFFSET_SEL_BITS 1 19633 #define RX2_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 19634 19635 /* Rx2 :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */ 19636 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY1_MASK 0x0002 19637 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN 0 19638 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY1_BITS 1 19639 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT 1 19640 19641 /* Rx2 :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */ 19642 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY0_MASK 0x0001 19643 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN 0 19644 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY0_BITS 1 19645 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT 0 19646 19647 19648 /**************************************************************************** 19649 * Rx2 :: anaRxAControl2 19650 */ 19651 /* Rx2 :: anaRxAControl2 :: imax_ctat [15:15] */ 19652 #define RX2_ANARXACONTROL2_IMAX_CTAT_MASK 0x8000 19653 #define RX2_ANARXACONTROL2_IMAX_CTAT_ALIGN 0 19654 #define RX2_ANARXACONTROL2_IMAX_CTAT_BITS 1 19655 #define RX2_ANARXACONTROL2_IMAX_CTAT_SHIFT 15 19656 19657 /* Rx2 :: anaRxAControl2 :: imode_ctat [14:14] */ 19658 #define RX2_ANARXACONTROL2_IMODE_CTAT_MASK 0x4000 19659 #define RX2_ANARXACONTROL2_IMODE_CTAT_ALIGN 0 19660 #define RX2_ANARXACONTROL2_IMODE_CTAT_BITS 1 19661 #define RX2_ANARXACONTROL2_IMODE_CTAT_SHIFT 14 19662 19663 /* Rx2 :: anaRxAControl2 :: imin_ctat [13:13] */ 19664 #define RX2_ANARXACONTROL2_IMIN_CTAT_MASK 0x2000 19665 #define RX2_ANARXACONTROL2_IMIN_CTAT_ALIGN 0 19666 #define RX2_ANARXACONTROL2_IMIN_CTAT_BITS 1 19667 #define RX2_ANARXACONTROL2_IMIN_CTAT_SHIFT 13 19668 19669 /* Rx2 :: anaRxAControl2 :: imax_eqfl [12:12] */ 19670 #define RX2_ANARXACONTROL2_IMAX_EQFL_MASK 0x1000 19671 #define RX2_ANARXACONTROL2_IMAX_EQFL_ALIGN 0 19672 #define RX2_ANARXACONTROL2_IMAX_EQFL_BITS 1 19673 #define RX2_ANARXACONTROL2_IMAX_EQFL_SHIFT 12 19674 19675 /* Rx2 :: anaRxAControl2 :: imode_eqfl [11:11] */ 19676 #define RX2_ANARXACONTROL2_IMODE_EQFL_MASK 0x0800 19677 #define RX2_ANARXACONTROL2_IMODE_EQFL_ALIGN 0 19678 #define RX2_ANARXACONTROL2_IMODE_EQFL_BITS 1 19679 #define RX2_ANARXACONTROL2_IMODE_EQFL_SHIFT 11 19680 19681 /* Rx2 :: anaRxAControl2 :: imin_eqfl [10:10] */ 19682 #define RX2_ANARXACONTROL2_IMIN_EQFL_MASK 0x0400 19683 #define RX2_ANARXACONTROL2_IMIN_EQFL_ALIGN 0 19684 #define RX2_ANARXACONTROL2_IMIN_EQFL_BITS 1 19685 #define RX2_ANARXACONTROL2_IMIN_EQFL_SHIFT 10 19686 19687 /* Rx2 :: anaRxAControl2 :: imax_dfesum [09:09] */ 19688 #define RX2_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 19689 #define RX2_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 19690 #define RX2_ANARXACONTROL2_IMAX_DFESUM_BITS 1 19691 #define RX2_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 19692 19693 /* Rx2 :: anaRxAControl2 :: imode_dfesum [08:08] */ 19694 #define RX2_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 19695 #define RX2_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 19696 #define RX2_ANARXACONTROL2_IMODE_DFESUM_BITS 1 19697 #define RX2_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 19698 19699 /* Rx2 :: anaRxAControl2 :: imin_dfesum [07:07] */ 19700 #define RX2_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 19701 #define RX2_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 19702 #define RX2_ANARXACONTROL2_IMIN_DFESUM_BITS 1 19703 #define RX2_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 19704 19705 /* Rx2 :: anaRxAControl2 :: imax_vga [06:06] */ 19706 #define RX2_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 19707 #define RX2_ANARXACONTROL2_IMAX_VGA_ALIGN 0 19708 #define RX2_ANARXACONTROL2_IMAX_VGA_BITS 1 19709 #define RX2_ANARXACONTROL2_IMAX_VGA_SHIFT 6 19710 19711 /* Rx2 :: anaRxAControl2 :: imode_vga [05:05] */ 19712 #define RX2_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 19713 #define RX2_ANARXACONTROL2_IMODE_VGA_ALIGN 0 19714 #define RX2_ANARXACONTROL2_IMODE_VGA_BITS 1 19715 #define RX2_ANARXACONTROL2_IMODE_VGA_SHIFT 5 19716 19717 /* Rx2 :: anaRxAControl2 :: imin_vga [04:04] */ 19718 #define RX2_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 19719 #define RX2_ANARXACONTROL2_IMIN_VGA_ALIGN 0 19720 #define RX2_ANARXACONTROL2_IMIN_VGA_BITS 1 19721 #define RX2_ANARXACONTROL2_IMIN_VGA_SHIFT 4 19722 19723 /* Rx2 :: anaRxAControl2 :: imax_interp [03:03] */ 19724 #define RX2_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 19725 #define RX2_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 19726 #define RX2_ANARXACONTROL2_IMAX_INTERP_BITS 1 19727 #define RX2_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 19728 19729 /* Rx2 :: anaRxAControl2 :: imode_interp [02:02] */ 19730 #define RX2_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 19731 #define RX2_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 19732 #define RX2_ANARXACONTROL2_IMODE_INTERP_BITS 1 19733 #define RX2_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 19734 19735 /* Rx2 :: anaRxAControl2 :: imin_interp [01:01] */ 19736 #define RX2_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 19737 #define RX2_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 19738 #define RX2_ANARXACONTROL2_IMIN_INTERP_BITS 1 19739 #define RX2_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 19740 19741 /* Rx2 :: anaRxAControl2 :: imax_vcm [00:00] */ 19742 #define RX2_ANARXACONTROL2_IMAX_VCM_MASK 0x0001 19743 #define RX2_ANARXACONTROL2_IMAX_VCM_ALIGN 0 19744 #define RX2_ANARXACONTROL2_IMAX_VCM_BITS 1 19745 #define RX2_ANARXACONTROL2_IMAX_VCM_SHIFT 0 19746 19747 19748 /**************************************************************************** 19749 * Rx2 :: anaRxAControl3 19750 */ 19751 /* Rx2 :: anaRxAControl3 :: en_clk16 [15:15] */ 19752 #define RX2_ANARXACONTROL3_EN_CLK16_MASK 0x8000 19753 #define RX2_ANARXACONTROL3_EN_CLK16_ALIGN 0 19754 #define RX2_ANARXACONTROL3_EN_CLK16_BITS 1 19755 #define RX2_ANARXACONTROL3_EN_CLK16_SHIFT 15 19756 19757 /* Rx2 :: anaRxAControl3 :: en_clk33 [14:14] */ 19758 #define RX2_ANARXACONTROL3_EN_CLK33_MASK 0x4000 19759 #define RX2_ANARXACONTROL3_EN_CLK33_ALIGN 0 19760 #define RX2_ANARXACONTROL3_EN_CLK33_BITS 1 19761 #define RX2_ANARXACONTROL3_EN_CLK33_SHIFT 14 19762 19763 /* Rx2 :: anaRxAControl3 :: en_vcctrl [13:13] */ 19764 #define RX2_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 19765 #define RX2_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 19766 #define RX2_ANARXACONTROL3_EN_VCCTRL_BITS 1 19767 #define RX2_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 19768 19769 /* Rx2 :: anaRxAControl3 :: sel_th4dfe1 [12:12] */ 19770 #define RX2_ANARXACONTROL3_SEL_TH4DFE1_MASK 0x1000 19771 #define RX2_ANARXACONTROL3_SEL_TH4DFE1_ALIGN 0 19772 #define RX2_ANARXACONTROL3_SEL_TH4DFE1_BITS 1 19773 #define RX2_ANARXACONTROL3_SEL_TH4DFE1_SHIFT 12 19774 19775 /* Rx2 :: anaRxAControl3 :: sel_th4dfe0 [11:11] */ 19776 #define RX2_ANARXACONTROL3_SEL_TH4DFE0_MASK 0x0800 19777 #define RX2_ANARXACONTROL3_SEL_TH4DFE0_ALIGN 0 19778 #define RX2_ANARXACONTROL3_SEL_TH4DFE0_BITS 1 19779 #define RX2_ANARXACONTROL3_SEL_TH4DFE0_SHIFT 11 19780 19781 /* Rx2 :: anaRxAControl3 :: selugbw1 [10:10] */ 19782 #define RX2_ANARXACONTROL3_SELUGBW1_MASK 0x0400 19783 #define RX2_ANARXACONTROL3_SELUGBW1_ALIGN 0 19784 #define RX2_ANARXACONTROL3_SELUGBW1_BITS 1 19785 #define RX2_ANARXACONTROL3_SELUGBW1_SHIFT 10 19786 19787 /* Rx2 :: anaRxAControl3 :: selugbw0 [09:09] */ 19788 #define RX2_ANARXACONTROL3_SELUGBW0_MASK 0x0200 19789 #define RX2_ANARXACONTROL3_SELUGBW0_ALIGN 0 19790 #define RX2_ANARXACONTROL3_SELUGBW0_BITS 1 19791 #define RX2_ANARXACONTROL3_SELUGBW0_SHIFT 9 19792 19793 /* Rx2 :: anaRxAControl3 :: imax_dfetap [08:08] */ 19794 #define RX2_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 19795 #define RX2_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 19796 #define RX2_ANARXACONTROL3_IMAX_DFETAP_BITS 1 19797 #define RX2_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 19798 19799 /* Rx2 :: anaRxAControl3 :: imode_dfetap [07:07] */ 19800 #define RX2_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 19801 #define RX2_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 19802 #define RX2_ANARXACONTROL3_IMODE_DFETAP_BITS 1 19803 #define RX2_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 19804 19805 /* Rx2 :: anaRxAControl3 :: imin_dfetap [06:06] */ 19806 #define RX2_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 19807 #define RX2_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 19808 #define RX2_ANARXACONTROL3_IMIN_DFETAP_BITS 1 19809 #define RX2_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 19810 19811 /* Rx2 :: anaRxAControl3 :: imax_slcd2c [05:05] */ 19812 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 19813 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 19814 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 19815 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 19816 19817 /* Rx2 :: anaRxAControl3 :: imode_slcd2c [04:04] */ 19818 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 19819 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 19820 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 19821 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 19822 19823 /* Rx2 :: anaRxAControl3 :: imin_slcd2c [03:03] */ 19824 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 19825 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 19826 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 19827 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 19828 19829 /* Rx2 :: anaRxAControl3 :: imax_dfevref [02:02] */ 19830 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 19831 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 19832 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 19833 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 19834 19835 /* Rx2 :: anaRxAControl3 :: imode_dfevref [01:01] */ 19836 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 19837 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 19838 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 19839 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 19840 19841 /* Rx2 :: anaRxAControl3 :: imin_dfevref [00:00] */ 19842 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 19843 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 19844 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 19845 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 19846 19847 19848 /**************************************************************************** 19849 * Warpcore_USER_Rx3 19850 */ 19851 /**************************************************************************** 19852 * Rx3 :: anaRxStatus 19853 */ 19854 /* union - case sigdet_Status [15:00] */ 19855 /* Rx3 :: anaRxStatus :: cx4_sigdet [15:15] */ 19856 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 19857 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 19858 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 19859 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 19860 19861 /* Rx3 :: anaRxStatus :: reserved0 [14:13] */ 19862 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 19863 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 19864 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS 2 19865 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 19866 19867 /* Rx3 :: anaRxStatus :: rxSeqDone [12:12] */ 19868 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 19869 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 19870 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 19871 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 19872 19873 /* Rx3 :: anaRxStatus :: rx_sigdet_ll [11:11] */ 19874 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 19875 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 19876 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 19877 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 19878 19879 /* Rx3 :: anaRxStatus :: cs4_sigdet_ll [10:10] */ 19880 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 19881 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 19882 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 19883 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 19884 19885 /* Rx3 :: anaRxStatus :: rx_reset [09:09] */ 19886 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 19887 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 19888 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS 1 19889 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 19890 19891 /* Rx3 :: anaRxStatus :: rx_pwrdn [08:08] */ 19892 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 19893 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 19894 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 19895 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 19896 19897 /* Rx3 :: anaRxStatus :: reserved1 [07:00] */ 19898 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 19899 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 19900 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS 8 19901 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 19902 19903 19904 /* union - case sync_Status [15:00] */ 19905 /* Rx3 :: anaRxStatus :: reserved0 [15:11] */ 19906 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 19907 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN 0 19908 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS 5 19909 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT 11 19910 19911 /* Rx3 :: anaRxStatus :: test_acq_en [10:10] */ 19912 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 19913 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 19914 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 19915 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 19916 19917 /* Rx3 :: anaRxStatus :: reserved1 [09:09] */ 19918 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 19919 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN 0 19920 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS 1 19921 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT 9 19922 19923 /* Rx3 :: anaRxStatus :: rxSeqStart [08:08] */ 19924 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 19925 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 19926 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS 1 19927 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 19928 19929 /* Rx3 :: anaRxStatus :: mux_comadj_sync_status [07:07] */ 19930 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 19931 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 19932 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 19933 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 19934 19935 /* Rx3 :: anaRxStatus :: sync_status [06:06] */ 19936 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 19937 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 19938 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 19939 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 19940 19941 /* Rx3 :: anaRxStatus :: rx_sigdet [05:05] */ 19942 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 19943 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 19944 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS 1 19945 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 19946 19947 /* Rx3 :: anaRxStatus :: reserved2 [04:03] */ 19948 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 19949 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN 0 19950 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS 2 19951 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT 3 19952 19953 /* Rx3 :: anaRxStatus :: saturate_status [02:02] */ 19954 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 19955 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 19956 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 19957 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 19958 19959 /* Rx3 :: anaRxStatus :: cx4_sigdet [01:01] */ 19960 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 19961 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 19962 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 19963 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 19964 19965 /* Rx3 :: anaRxStatus :: rxSeqDone [00:00] */ 19966 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 19967 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 19968 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS 1 19969 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 19970 19971 19972 /* union - case rxTestSel_0 [15:00] */ 19973 /* Rx3 :: anaRxStatus :: reserved0 [15:10] */ 19974 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 19975 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 19976 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS 6 19977 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 19978 19979 /* Rx3 :: anaRxStatus :: indck_mode_en [09:09] */ 19980 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 19981 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 19982 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 19983 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 19984 19985 /* Rx3 :: anaRxStatus :: pci_mode_en [08:08] */ 19986 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 19987 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 19988 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 19989 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 19990 19991 /* Rx3 :: anaRxStatus :: rx_polarity [07:07] */ 19992 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 19993 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 19994 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 19995 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 19996 19997 /* Rx3 :: anaRxStatus :: rxpol_flip [06:06] */ 19998 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 19999 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 20000 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 20001 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 20002 20003 /* Rx3 :: anaRxStatus :: comma_mask [05:05] */ 20004 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 20005 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 20006 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 20007 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 20008 20009 /* Rx3 :: anaRxStatus :: link_en_r [04:04] */ 20010 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 20011 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 20012 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 20013 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 20014 20015 /* Rx3 :: anaRxStatus :: comma_adj_en [03:03] */ 20016 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 20017 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 20018 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 20019 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 20020 20021 /* Rx3 :: anaRxStatus :: comma_adj_en_ext [02:02] */ 20022 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 20023 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 20024 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 20025 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 20026 20027 /* Rx3 :: anaRxStatus :: reserved1 [01:00] */ 20028 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 20029 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 20030 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS 2 20031 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 20032 20033 20034 /* union - case rxTestSel_1 [15:00] */ 20035 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */ 20036 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 20037 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 20038 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS 11 20039 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 20040 20041 /* Rx3 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */ 20042 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 20043 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 20044 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 20045 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 20046 20047 /* Rx3 :: anaRxStatus :: freq_sel_PC [03:03] */ 20048 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 20049 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 20050 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 20051 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 20052 20053 /* Rx3 :: anaRxStatus :: freq_sel_SM [02:02] */ 20054 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 20055 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 20056 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 20057 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 20058 20059 /* Rx3 :: anaRxStatus :: integ_mode_SM [01:00] */ 20060 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 20061 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 20062 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 20063 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 20064 20065 20066 /* union - case scale_Status [15:00] */ 20067 /* Rx3 :: anaRxStatus :: prop_scale [15:12] */ 20068 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 20069 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 20070 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS 4 20071 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 20072 20073 /* Rx3 :: anaRxStatus :: integ_scale [11:08] */ 20074 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 20075 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 20076 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 20077 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 20078 20079 /* Rx3 :: anaRxStatus :: prop_scale_acq [07:04] */ 20080 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 20081 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 20082 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 20083 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 20084 20085 /* Rx3 :: anaRxStatus :: integ_scale_acq [03:00] */ 20086 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 20087 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 20088 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 20089 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 20090 20091 20092 /* union - case adc_CdrStatus1 [15:00] */ 20093 /* Rx3 :: anaRxStatus :: reserved0 [15:07] */ 20094 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 20095 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 20096 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 20097 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 20098 20099 /* Rx3 :: anaRxStatus :: rxMuxCkSel [06:06] */ 20100 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 20101 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 20102 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 20103 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 20104 20105 /* Rx3 :: anaRxStatus :: glpbk_combo [05:05] */ 20106 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 20107 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 20108 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 20109 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 20110 20111 /* Rx3 :: anaRxStatus :: clockSwitchSel [04:04] */ 20112 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 20113 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 20114 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 20115 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 20116 20117 /* Rx3 :: anaRxStatus :: rxck_tst [03:03] */ 20118 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 20119 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 20120 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 20121 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 20122 20123 /* Rx3 :: anaRxStatus :: rxck_i [02:02] */ 20124 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 20125 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 20126 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 20127 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 20128 20129 /* Rx3 :: anaRxStatus :: refclk [01:01] */ 20130 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 20131 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 20132 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 20133 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 20134 20135 /* Rx3 :: anaRxStatus :: pll_bypass [00:00] */ 20136 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 20137 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 20138 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 20139 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 20140 20141 20142 /* union - case adc_CdrStatus2 [15:00] */ 20143 /* Rx3 :: anaRxStatus :: reserved0 [15:06] */ 20144 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 20145 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 20146 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 20147 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 20148 20149 /* Rx3 :: anaRxStatus :: rxMuxCkSel [05:05] */ 20150 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 20151 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 20152 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 20153 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 20154 20155 /* Rx3 :: anaRxStatus :: rxSeqStart [04:04] */ 20156 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 20157 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 20158 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 20159 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 20160 20161 /* Rx3 :: anaRxStatus :: reserved1 [03:01] */ 20162 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 20163 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 20164 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 20165 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 20166 20167 /* Rx3 :: anaRxStatus :: rxSeqDone [00:00] */ 20168 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 20169 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 20170 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 20171 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 20172 20173 20174 /* union - case adc_CdrStatus3 [15:00] */ 20175 /* Rx3 :: anaRxStatus :: reserved0 [15:04] */ 20176 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 20177 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 20178 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 20179 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 20180 20181 /* Rx3 :: anaRxStatus :: rxSeqStart [03:03] */ 20182 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 20183 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 20184 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 20185 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 20186 20187 /* Rx3 :: anaRxStatus :: reserved1 [02:01] */ 20188 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 20189 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 20190 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 20191 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 20192 20193 /* Rx3 :: anaRxStatus :: allow_increment_PC [00:00] */ 20194 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 20195 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 20196 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 20197 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 20198 20199 20200 /* union - case adc_CdrStatus4 [15:00] */ 20201 /* Rx3 :: anaRxStatus :: reserved0 [15:08] */ 20202 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 20203 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 20204 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 20205 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 20206 20207 /* Rx3 :: anaRxStatus :: rx_pwrdn [07:07] */ 20208 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 20209 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 20210 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 20211 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 20212 20213 /* Rx3 :: anaRxStatus :: freq_sel [06:06] */ 20214 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 20215 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 20216 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 20217 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 20218 20219 /* Rx3 :: anaRxStatus :: pll_lock_rstb [05:05] */ 20220 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 20221 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 20222 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 20223 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 20224 20225 /* Rx3 :: anaRxStatus :: pwrdn [04:04] */ 20226 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 20227 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 20228 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 20229 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 20230 20231 /* Rx3 :: anaRxStatus :: reserved1 [03:00] */ 20232 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 20233 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 20234 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 20235 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 20236 20237 20238 /* union - case adc_CdrStatus5 [15:00] */ 20239 /* Rx3 :: anaRxStatus :: reserved0 [15:00] */ 20240 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 20241 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 20242 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 20243 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 20244 20245 20246 /* union - case adc_CdrStatus6 [15:00] */ 20247 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */ 20248 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 20249 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 20250 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 20251 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 20252 20253 /* Rx3 :: anaRxStatus :: rx_reset [04:04] */ 20254 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 20255 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 20256 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 20257 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 20258 20259 /* Rx3 :: anaRxStatus :: rx_pwrdn [03:03] */ 20260 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 20261 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 20262 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 20263 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 20264 20265 /* Rx3 :: anaRxStatus :: reset_anlg [02:02] */ 20266 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 20267 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 20268 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 20269 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 20270 20271 /* Rx3 :: anaRxStatus :: pwrdn_rx [01:01] */ 20272 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 20273 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 20274 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 20275 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 20276 20277 /* Rx3 :: anaRxStatus :: pwrdn_pll [00:00] */ 20278 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 20279 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 20280 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 20281 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 20282 20283 20284 /* union - case adc_CdrStatus7e [15:00] */ 20285 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */ 20286 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 20287 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 20288 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 20289 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 20290 20291 /* Rx3 :: anaRxStatus :: rxck0_even [04:04] */ 20292 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 20293 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 20294 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 20295 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 20296 20297 /* Rx3 :: anaRxStatus :: rxck1_even [03:03] */ 20298 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 20299 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 20300 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 20301 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 20302 20303 /* Rx3 :: anaRxStatus :: comdet_even [02:02] */ 20304 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 20305 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 20306 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 20307 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 20308 20309 /* Rx3 :: anaRxStatus :: en_cdet_even [01:01] */ 20310 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 20311 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 20312 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 20313 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 20314 20315 /* Rx3 :: anaRxStatus :: comma_adj_en_even [00:00] */ 20316 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 20317 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 20318 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 20319 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 20320 20321 20322 /* union - case adc_CdrStatus7o [15:00] */ 20323 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */ 20324 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 20325 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 20326 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 20327 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 20328 20329 /* Rx3 :: anaRxStatus :: rxck0_odd [04:04] */ 20330 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 20331 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 20332 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 20333 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 20334 20335 /* Rx3 :: anaRxStatus :: rxck1_odd [03:03] */ 20336 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 20337 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 20338 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 20339 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 20340 20341 /* Rx3 :: anaRxStatus :: comdet_odd [02:02] */ 20342 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 20343 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 20344 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 20345 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 20346 20347 /* Rx3 :: anaRxStatus :: en_cdet_odd [01:01] */ 20348 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 20349 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 20350 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 20351 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 20352 20353 /* Rx3 :: anaRxStatus :: comma_adj_en_odd [00:00] */ 20354 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 20355 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 20356 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 20357 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 20358 20359 20360 /* union - case adc_CdrStatus8 [15:00] */ 20361 /* Rx3 :: anaRxStatus :: reserved0 [15:01] */ 20362 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 20363 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 20364 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 20365 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 20366 20367 /* Rx3 :: anaRxStatus :: sigdet [00:00] */ 20368 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 20369 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 20370 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 20371 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 20372 20373 20374 /* union - case adc_CdrStatus9 [15:00] */ 20375 /* Rx3 :: anaRxStatus :: reserved0 [15:00] */ 20376 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 20377 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 20378 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 20379 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 20380 20381 20382 /* union - case adc_CdrStatus10 [15:00] */ 20383 /* Rx3 :: anaRxStatus :: reserved0 [15:07] */ 20384 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 20385 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 20386 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 20387 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 20388 20389 /* Rx3 :: anaRxStatus :: prbs_en [06:06] */ 20390 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 20391 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 20392 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 20393 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 20394 20395 /* Rx3 :: anaRxStatus :: rstb_tst [05:05] */ 20396 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 20397 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 20398 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 20399 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 20400 20401 /* Rx3 :: anaRxStatus :: reserved1 [04:04] */ 20402 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 20403 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 20404 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 20405 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 20406 20407 /* Rx3 :: anaRxStatus :: prbs_state [03:00] */ 20408 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 20409 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 20410 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 20411 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 20412 20413 20414 /* union - case adc_CdrStatus11 [15:00] */ 20415 /* Rx3 :: anaRxStatus :: reserved0 [15:00] */ 20416 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 20417 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 20418 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 20419 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 20420 20421 20422 /* union - case adc_CdrStatus12_1 [15:00] */ 20423 /* Rx3 :: anaRxStatus :: reserved0 [15:06] */ 20424 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 20425 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 20426 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 20427 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 20428 20429 /* Rx3 :: anaRxStatus :: enable4 [05:05] */ 20430 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 20431 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 20432 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 20433 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 20434 20435 /* Rx3 :: anaRxStatus :: radr_test [04:00] */ 20436 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 20437 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 20438 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 20439 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 20440 20441 20442 /* union - case adc_CdrStatus12_2 [15:00] */ 20443 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */ 20444 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 20445 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 20446 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 20447 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 20448 20449 /* Rx3 :: anaRxStatus :: wadr_test [04:00] */ 20450 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 20451 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 20452 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 20453 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 20454 20455 20456 /* union - case adc_CdrStatus12_3 [15:00] */ 20457 /* Rx3 :: anaRxStatus :: reserved0 [15:06] */ 20458 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 20459 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 20460 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 20461 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 20462 20463 /* Rx3 :: anaRxStatus :: rxck_66B_tmux [05:05] */ 20464 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 20465 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 20466 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 20467 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 20468 20469 /* Rx3 :: anaRxStatus :: rstb_66B [04:04] */ 20470 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 20471 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 20472 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 20473 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 20474 20475 /* Rx3 :: anaRxStatus :: prstb_66B_mux [03:03] */ 20476 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 20477 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 20478 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 20479 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 20480 20481 /* Rx3 :: anaRxStatus :: rxck_i66_tmux [02:02] */ 20482 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 20483 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 20484 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 20485 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 20486 20487 /* Rx3 :: anaRxStatus :: rstb_i66 [01:01] */ 20488 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 20489 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 20490 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 20491 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 20492 20493 /* Rx3 :: anaRxStatus :: prstb_i66_mux [00:00] */ 20494 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 20495 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 20496 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 20497 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 20498 20499 20500 /* union - case adc_CdrStatus12_4 [15:00] */ 20501 /* Rx3 :: anaRxStatus :: reserved0 [15:04] */ 20502 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 20503 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 20504 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 20505 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 20506 20507 /* Rx3 :: anaRxStatus :: rfifo_error_r [03:02] */ 20508 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 20509 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 20510 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 20511 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 20512 20513 /* Rx3 :: anaRxStatus :: rfifo_unflow [01:01] */ 20514 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 20515 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 20516 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 20517 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 20518 20519 /* Rx3 :: anaRxStatus :: rfifo_ovflow [00:00] */ 20520 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 20521 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 20522 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 20523 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 20524 20525 20526 /* union - case integ_Status [15:00] */ 20527 /* Rx3 :: anaRxStatus :: integ_status [15:00] */ 20528 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 20529 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 20530 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 20531 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 20532 20533 20534 /* union - case vco_Status [15:00] */ 20535 /* Rx3 :: anaRxStatus :: vco_status [15:00] */ 20536 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 20537 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 20538 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS 16 20539 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 20540 20541 20542 /* union - case prbs_Status [15:00] */ 20543 /* Rx3 :: anaRxStatus :: prbs_lock [15:15] */ 20544 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 20545 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 20546 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 20547 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 20548 20549 /* Rx3 :: anaRxStatus :: prbs_stky [14:14] */ 20550 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 20551 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 20552 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS 1 20553 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 20554 20555 /* Rx3 :: anaRxStatus :: prbs_errors [13:00] */ 20556 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_MASK 0x3fff 20557 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_ALIGN 0 20558 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_BITS 14 20559 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_SHIFT 0 20560 20561 20562 20563 /**************************************************************************** 20564 * Rx3 :: anaRxControl 20565 */ 20566 /* Rx3 :: anaRxControl :: reserved0 [15:10] */ 20567 #define RX3_ANARXCONTROL_RESERVED0_MASK 0xfc00 20568 #define RX3_ANARXCONTROL_RESERVED0_ALIGN 0 20569 #define RX3_ANARXCONTROL_RESERVED0_BITS 6 20570 #define RX3_ANARXCONTROL_RESERVED0_SHIFT 10 20571 20572 /* Rx3 :: anaRxControl :: override_sigdet_en [09:09] */ 20573 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 20574 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 20575 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 20576 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 20577 20578 /* Rx3 :: anaRxControl :: override_sigdet_val [08:08] */ 20579 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 20580 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 20581 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 20582 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 20583 20584 /* Rx3 :: anaRxControl :: reserved1 [07:03] */ 20585 #define RX3_ANARXCONTROL_RESERVED1_MASK 0x00f8 20586 #define RX3_ANARXCONTROL_RESERVED1_ALIGN 0 20587 #define RX3_ANARXCONTROL_RESERVED1_BITS 5 20588 #define RX3_ANARXCONTROL_RESERVED1_SHIFT 3 20589 20590 /* Rx3 :: anaRxControl :: status_sel [02:00] */ 20591 #define RX3_ANARXCONTROL_STATUS_SEL_MASK 0x0007 20592 #define RX3_ANARXCONTROL_STATUS_SEL_ALIGN 0 20593 #define RX3_ANARXCONTROL_STATUS_SEL_BITS 3 20594 #define RX3_ANARXCONTROL_STATUS_SEL_SHIFT 0 20595 #define RX3_ANARXCONTROL_STATUS_SEL_sigdetStatus 0 20596 #define RX3_ANARXCONTROL_STATUS_SEL_syncStatus 1 20597 #define RX3_ANARXCONTROL_STATUS_SEL_rxTestSel 2 20598 #define RX3_ANARXCONTROL_STATUS_SEL_scaleStatus 3 20599 #define RX3_ANARXCONTROL_STATUS_SEL_adcCdrStatus 4 20600 #define RX3_ANARXCONTROL_STATUS_SEL_integStatus 5 20601 #define RX3_ANARXCONTROL_STATUS_SEL_vcoStatus 6 20602 #define RX3_ANARXCONTROL_STATUS_SEL_prbsStatus 7 20603 20604 20605 /**************************************************************************** 20606 * Rx3 :: anaRxSigdet 20607 */ 20608 /* Rx3 :: anaRxSigdet :: sigdetTime_SM [15:08] */ 20609 #define RX3_ANARXSIGDET_SIGDETTIME_SM_MASK 0xff00 20610 #define RX3_ANARXSIGDET_SIGDETTIME_SM_ALIGN 0 20611 #define RX3_ANARXSIGDET_SIGDETTIME_SM_BITS 8 20612 #define RX3_ANARXSIGDET_SIGDETTIME_SM_SHIFT 8 20613 20614 /* Rx3 :: anaRxSigdet :: cx4_sigdet_cnt_ld_SM [07:07] */ 20615 #define RX3_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_MASK 0x0080 20616 #define RX3_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_ALIGN 0 20617 #define RX3_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_BITS 1 20618 #define RX3_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_SHIFT 7 20619 20620 /* Rx3 :: anaRxSigdet :: ext_sigdet_en_SM [06:06] */ 20621 #define RX3_ANARXSIGDET_EXT_SIGDET_EN_SM_MASK 0x0040 20622 #define RX3_ANARXSIGDET_EXT_SIGDET_EN_SM_ALIGN 0 20623 #define RX3_ANARXSIGDET_EXT_SIGDET_EN_SM_BITS 1 20624 #define RX3_ANARXSIGDET_EXT_SIGDET_EN_SM_SHIFT 6 20625 20626 /* Rx3 :: anaRxSigdet :: cx4_sigdet_en_SM [05:05] */ 20627 #define RX3_ANARXSIGDET_CX4_SIGDET_EN_SM_MASK 0x0020 20628 #define RX3_ANARXSIGDET_CX4_SIGDET_EN_SM_ALIGN 0 20629 #define RX3_ANARXSIGDET_CX4_SIGDET_EN_SM_BITS 1 20630 #define RX3_ANARXSIGDET_CX4_SIGDET_EN_SM_SHIFT 5 20631 20632 /* Rx3 :: anaRxSigdet :: rx_sigdet_r [04:04] */ 20633 #define RX3_ANARXSIGDET_RX_SIGDET_R_MASK 0x0010 20634 #define RX3_ANARXSIGDET_RX_SIGDET_R_ALIGN 0 20635 #define RX3_ANARXSIGDET_RX_SIGDET_R_BITS 1 20636 #define RX3_ANARXSIGDET_RX_SIGDET_R_SHIFT 4 20637 20638 /* Rx3 :: anaRxSigdet :: rx_sigdet_force_r [03:03] */ 20639 #define RX3_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK 0x0008 20640 #define RX3_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN 0 20641 #define RX3_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS 1 20642 #define RX3_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT 3 20643 20644 /* Rx3 :: anaRxSigdet :: invert_rx_sigdet [02:02] */ 20645 #define RX3_ANARXSIGDET_INVERT_RX_SIGDET_MASK 0x0004 20646 #define RX3_ANARXSIGDET_INVERT_RX_SIGDET_ALIGN 0 20647 #define RX3_ANARXSIGDET_INVERT_RX_SIGDET_BITS 1 20648 #define RX3_ANARXSIGDET_INVERT_RX_SIGDET_SHIFT 2 20649 20650 /* Rx3 :: anaRxSigdet :: reserved0 [01:00] */ 20651 #define RX3_ANARXSIGDET_RESERVED0_MASK 0x0003 20652 #define RX3_ANARXSIGDET_RESERVED0_ALIGN 0 20653 #define RX3_ANARXSIGDET_RESERVED0_BITS 2 20654 #define RX3_ANARXSIGDET_RESERVED0_SHIFT 0 20655 20656 20657 /**************************************************************************** 20658 * Rx3 :: anaRxAControl4 20659 */ 20660 /* Rx3 :: anaRxAControl4 :: ana_clt4 [15:00] */ 20661 #define RX3_ANARXACONTROL4_ANA_CLT4_MASK 0xffff 20662 #define RX3_ANARXACONTROL4_ANA_CLT4_ALIGN 0 20663 #define RX3_ANARXACONTROL4_ANA_CLT4_BITS 16 20664 #define RX3_ANARXACONTROL4_ANA_CLT4_SHIFT 0 20665 20666 20667 /**************************************************************************** 20668 * Rx3 :: anaRxControl2_1G 20669 */ 20670 /* Rx3 :: anaRxControl2_1G :: reserved0 [15:15] */ 20671 #define RX3_ANARXCONTROL2_1G_RESERVED0_MASK 0x8000 20672 #define RX3_ANARXCONTROL2_1G_RESERVED0_ALIGN 0 20673 #define RX3_ANARXCONTROL2_1G_RESERVED0_BITS 1 20674 #define RX3_ANARXCONTROL2_1G_RESERVED0_SHIFT 15 20675 20676 /* Rx3 :: anaRxControl2_1G :: rx_prbs_w_val [14:14] */ 20677 #define RX3_ANARXCONTROL2_1G_RX_PRBS_W_VAL_MASK 0x4000 20678 #define RX3_ANARXCONTROL2_1G_RX_PRBS_W_VAL_ALIGN 0 20679 #define RX3_ANARXCONTROL2_1G_RX_PRBS_W_VAL_BITS 1 20680 #define RX3_ANARXCONTROL2_1G_RX_PRBS_W_VAL_SHIFT 14 20681 20682 /* Rx3 :: anaRxControl2_1G :: rx_prbs_w_force [13:13] */ 20683 #define RX3_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_MASK 0x2000 20684 #define RX3_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_ALIGN 0 20685 #define RX3_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_BITS 1 20686 #define RX3_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_SHIFT 13 20687 20688 /* Rx3 :: anaRxControl2_1G :: rx_prbs_bswap [12:12] */ 20689 #define RX3_ANARXCONTROL2_1G_RX_PRBS_BSWAP_MASK 0x1000 20690 #define RX3_ANARXCONTROL2_1G_RX_PRBS_BSWAP_ALIGN 0 20691 #define RX3_ANARXCONTROL2_1G_RX_PRBS_BSWAP_BITS 1 20692 #define RX3_ANARXCONTROL2_1G_RX_PRBS_BSWAP_SHIFT 12 20693 20694 /* Rx3 :: anaRxControl2_1G :: rx_bitswap [11:11] */ 20695 #define RX3_ANARXCONTROL2_1G_RX_BITSWAP_MASK 0x0800 20696 #define RX3_ANARXCONTROL2_1G_RX_BITSWAP_ALIGN 0 20697 #define RX3_ANARXCONTROL2_1G_RX_BITSWAP_BITS 1 20698 #define RX3_ANARXCONTROL2_1G_RX_BITSWAP_SHIFT 11 20699 20700 /* Rx3 :: anaRxControl2_1G :: rst_rx_r [10:10] */ 20701 #define RX3_ANARXCONTROL2_1G_RST_RX_R_MASK 0x0400 20702 #define RX3_ANARXCONTROL2_1G_RST_RX_R_ALIGN 0 20703 #define RX3_ANARXCONTROL2_1G_RST_RX_R_BITS 1 20704 #define RX3_ANARXCONTROL2_1G_RST_RX_R_SHIFT 10 20705 20706 /* Rx3 :: anaRxControl2_1G :: pwdwn_rx_r [09:09] */ 20707 #define RX3_ANARXCONTROL2_1G_PWDWN_RX_R_MASK 0x0200 20708 #define RX3_ANARXCONTROL2_1G_PWDWN_RX_R_ALIGN 0 20709 #define RX3_ANARXCONTROL2_1G_PWDWN_RX_R_BITS 1 20710 #define RX3_ANARXCONTROL2_1G_PWDWN_RX_R_SHIFT 9 20711 20712 /* Rx3 :: anaRxControl2_1G :: prbs_order_rx_r_2 [08:08] */ 20713 #define RX3_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_MASK 0x0100 20714 #define RX3_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_ALIGN 0 20715 #define RX3_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_BITS 1 20716 #define RX3_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_SHIFT 8 20717 20718 /* Rx3 :: anaRxControl2_1G :: reserved1 [07:07] */ 20719 #define RX3_ANARXCONTROL2_1G_RESERVED1_MASK 0x0080 20720 #define RX3_ANARXCONTROL2_1G_RESERVED1_ALIGN 0 20721 #define RX3_ANARXCONTROL2_1G_RESERVED1_BITS 1 20722 #define RX3_ANARXCONTROL2_1G_RESERVED1_SHIFT 7 20723 20724 /* Rx3 :: anaRxControl2_1G :: prbs_sel_rx_r [06:06] */ 20725 #define RX3_ANARXCONTROL2_1G_PRBS_SEL_RX_R_MASK 0x0040 20726 #define RX3_ANARXCONTROL2_1G_PRBS_SEL_RX_R_ALIGN 0 20727 #define RX3_ANARXCONTROL2_1G_PRBS_SEL_RX_R_BITS 1 20728 #define RX3_ANARXCONTROL2_1G_PRBS_SEL_RX_R_SHIFT 6 20729 20730 /* Rx3 :: anaRxControl2_1G :: prbs_en_rx_r [05:05] */ 20731 #define RX3_ANARXCONTROL2_1G_PRBS_EN_RX_R_MASK 0x0020 20732 #define RX3_ANARXCONTROL2_1G_PRBS_EN_RX_R_ALIGN 0 20733 #define RX3_ANARXCONTROL2_1G_PRBS_EN_RX_R_BITS 1 20734 #define RX3_ANARXCONTROL2_1G_PRBS_EN_RX_R_SHIFT 5 20735 20736 /* Rx3 :: anaRxControl2_1G :: prbs_inv_rx_r [04:04] */ 20737 #define RX3_ANARXCONTROL2_1G_PRBS_INV_RX_R_MASK 0x0010 20738 #define RX3_ANARXCONTROL2_1G_PRBS_INV_RX_R_ALIGN 0 20739 #define RX3_ANARXCONTROL2_1G_PRBS_INV_RX_R_BITS 1 20740 #define RX3_ANARXCONTROL2_1G_PRBS_INV_RX_R_SHIFT 4 20741 20742 /* Rx3 :: anaRxControl2_1G :: prbs_order_rx_r [03:02] */ 20743 #define RX3_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_MASK 0x000c 20744 #define RX3_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_ALIGN 0 20745 #define RX3_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_BITS 2 20746 #define RX3_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_SHIFT 2 20747 20748 /* Rx3 :: anaRxControl2_1G :: reserved2 [01:01] */ 20749 #define RX3_ANARXCONTROL2_1G_RESERVED2_MASK 0x0002 20750 #define RX3_ANARXCONTROL2_1G_RESERVED2_ALIGN 0 20751 #define RX3_ANARXCONTROL2_1G_RESERVED2_BITS 1 20752 #define RX3_ANARXCONTROL2_1G_RESERVED2_SHIFT 1 20753 20754 /* Rx3 :: anaRxControl2_1G :: errcnt_15 [00:00] */ 20755 #define RX3_ANARXCONTROL2_1G_ERRCNT_15_MASK 0x0001 20756 #define RX3_ANARXCONTROL2_1G_ERRCNT_15_ALIGN 0 20757 #define RX3_ANARXCONTROL2_1G_ERRCNT_15_BITS 1 20758 #define RX3_ANARXCONTROL2_1G_ERRCNT_15_SHIFT 0 20759 20760 20761 /**************************************************************************** 20762 * Rx3 :: anaRxTest 20763 */ 20764 /* Rx3 :: anaRxTest :: sigdet_mux_SM [15:12] */ 20765 #define RX3_ANARXTEST_SIGDET_MUX_SM_MASK 0xf000 20766 #define RX3_ANARXTEST_SIGDET_MUX_SM_ALIGN 0 20767 #define RX3_ANARXTEST_SIGDET_MUX_SM_BITS 4 20768 #define RX3_ANARXTEST_SIGDET_MUX_SM_SHIFT 12 20769 20770 /* Rx3 :: anaRxTest :: reserved0 [11:09] */ 20771 #define RX3_ANARXTEST_RESERVED0_MASK 0x0e00 20772 #define RX3_ANARXTEST_RESERVED0_ALIGN 0 20773 #define RX3_ANARXTEST_RESERVED0_BITS 3 20774 #define RX3_ANARXTEST_RESERVED0_SHIFT 9 20775 20776 /* Rx3 :: anaRxTest :: tpctrl_SM [08:04] */ 20777 #define RX3_ANARXTEST_TPCTRL_SM_MASK 0x01f0 20778 #define RX3_ANARXTEST_TPCTRL_SM_ALIGN 0 20779 #define RX3_ANARXTEST_TPCTRL_SM_BITS 5 20780 #define RX3_ANARXTEST_TPCTRL_SM_SHIFT 4 20781 20782 /* Rx3 :: anaRxTest :: testMuxSelect_SM [03:00] */ 20783 #define RX3_ANARXTEST_TESTMUXSELECT_SM_MASK 0x000f 20784 #define RX3_ANARXTEST_TESTMUXSELECT_SM_ALIGN 0 20785 #define RX3_ANARXTEST_TESTMUXSELECT_SM_BITS 4 20786 #define RX3_ANARXTEST_TESTMUXSELECT_SM_SHIFT 0 20787 20788 20789 /**************************************************************************** 20790 * Rx3 :: anaRxControl1G 20791 */ 20792 /* Rx3 :: anaRxControl1G :: fpat_md [15:15] */ 20793 #define RX3_ANARXCONTROL1G_FPAT_MD_MASK 0x8000 20794 #define RX3_ANARXCONTROL1G_FPAT_MD_ALIGN 0 20795 #define RX3_ANARXCONTROL1G_FPAT_MD_BITS 1 20796 #define RX3_ANARXCONTROL1G_FPAT_MD_SHIFT 15 20797 20798 /* Rx3 :: anaRxControl1G :: pkt_count_en [14:14] */ 20799 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_MASK 0x4000 20800 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN 0 20801 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_BITS 1 20802 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT 14 20803 20804 /* Rx3 :: anaRxControl1G :: staMuxRegDis [13:13] */ 20805 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_MASK 0x2000 20806 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_ALIGN 0 20807 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_BITS 1 20808 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_SHIFT 13 20809 20810 /* Rx3 :: anaRxControl1G :: prbs_clr_dis [12:12] */ 20811 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_MASK 0x1000 20812 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN 0 20813 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_BITS 1 20814 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT 12 20815 20816 /* Rx3 :: anaRxControl1G :: rxd_dec_sel [11:11] */ 20817 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_MASK 0x0800 20818 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN 0 20819 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_BITS 1 20820 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT 11 20821 20822 /* Rx3 :: anaRxControl1G :: cgbad_tst [10:10] */ 20823 #define RX3_ANARXCONTROL1G_CGBAD_TST_MASK 0x0400 20824 #define RX3_ANARXCONTROL1G_CGBAD_TST_ALIGN 0 20825 #define RX3_ANARXCONTROL1G_CGBAD_TST_BITS 1 20826 #define RX3_ANARXCONTROL1G_CGBAD_TST_SHIFT 10 20827 20828 /* Rx3 :: anaRxControl1G :: Emon_en [09:09] */ 20829 #define RX3_ANARXCONTROL1G_EMON_EN_MASK 0x0200 20830 #define RX3_ANARXCONTROL1G_EMON_EN_ALIGN 0 20831 #define RX3_ANARXCONTROL1G_EMON_EN_BITS 1 20832 #define RX3_ANARXCONTROL1G_EMON_EN_SHIFT 9 20833 20834 /* Rx3 :: anaRxControl1G :: prbs_en [08:08] */ 20835 #define RX3_ANARXCONTROL1G_PRBS_EN_MASK 0x0100 20836 #define RX3_ANARXCONTROL1G_PRBS_EN_ALIGN 0 20837 #define RX3_ANARXCONTROL1G_PRBS_EN_BITS 1 20838 #define RX3_ANARXCONTROL1G_PRBS_EN_SHIFT 8 20839 20840 /* Rx3 :: anaRxControl1G :: cgbad_en [07:07] */ 20841 #define RX3_ANARXCONTROL1G_CGBAD_EN_MASK 0x0080 20842 #define RX3_ANARXCONTROL1G_CGBAD_EN_ALIGN 0 20843 #define RX3_ANARXCONTROL1G_CGBAD_EN_BITS 1 20844 #define RX3_ANARXCONTROL1G_CGBAD_EN_SHIFT 7 20845 20846 /* Rx3 :: anaRxControl1G :: cstretch [06:06] */ 20847 #define RX3_ANARXCONTROL1G_CSTRETCH_MASK 0x0040 20848 #define RX3_ANARXCONTROL1G_CSTRETCH_ALIGN 0 20849 #define RX3_ANARXCONTROL1G_CSTRETCH_BITS 1 20850 #define RX3_ANARXCONTROL1G_CSTRETCH_SHIFT 6 20851 20852 /* Rx3 :: anaRxControl1G :: comma_low_byte_SM [05:05] */ 20853 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK 0x0020 20854 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN 0 20855 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS 1 20856 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT 5 20857 20858 /* Rx3 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */ 20859 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 20860 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 20861 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS 1 20862 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 20863 20864 /* Rx3 :: anaRxControl1G :: reserved0 [03:02] */ 20865 #define RX3_ANARXCONTROL1G_RESERVED0_MASK 0x000c 20866 #define RX3_ANARXCONTROL1G_RESERVED0_ALIGN 0 20867 #define RX3_ANARXCONTROL1G_RESERVED0_BITS 2 20868 #define RX3_ANARXCONTROL1G_RESERVED0_SHIFT 2 20869 20870 /* Rx3 :: anaRxControl1G :: freq_sel_force [01:01] */ 20871 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK 0x0002 20872 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN 0 20873 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS 1 20874 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT 1 20875 20876 /* Rx3 :: anaRxControl1G :: freq_sel [00:00] */ 20877 #define RX3_ANARXCONTROL1G_FREQ_SEL_MASK 0x0001 20878 #define RX3_ANARXCONTROL1G_FREQ_SEL_ALIGN 0 20879 #define RX3_ANARXCONTROL1G_FREQ_SEL_BITS 1 20880 #define RX3_ANARXCONTROL1G_FREQ_SEL_SHIFT 0 20881 20882 20883 /**************************************************************************** 20884 * Rx3 :: anaRxControlPci 20885 */ 20886 /* Rx3 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */ 20887 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK 0x8000 20888 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN 0 20889 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS 1 20890 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT 15 20891 20892 /* Rx3 :: anaRxControlPci :: comma_mask_force_r [14:14] */ 20893 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK 0x4000 20894 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN 0 20895 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS 1 20896 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT 14 20897 20898 /* Rx3 :: anaRxControlPci :: comma_mask_r [13:13] */ 20899 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_MASK 0x2000 20900 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN 0 20901 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_BITS 1 20902 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT 13 20903 20904 /* Rx3 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */ 20905 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000 20906 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0 20907 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1 20908 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12 20909 20910 /* Rx3 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */ 20911 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK 0x0800 20912 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0 20913 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS 1 20914 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11 20915 20916 /* Rx3 :: anaRxControlPci :: sync_status_force_r [10:10] */ 20917 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK 0x0400 20918 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN 0 20919 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS 1 20920 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT 10 20921 20922 /* Rx3 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */ 20923 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200 20924 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0 20925 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1 20926 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9 20927 20928 /* Rx3 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */ 20929 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100 20930 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0 20931 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1 20932 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8 20933 20934 /* Rx3 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */ 20935 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080 20936 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0 20937 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1 20938 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7 20939 20940 /* Rx3 :: anaRxControlPci :: comma_adj_en_r [06:06] */ 20941 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK 0x0040 20942 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN 0 20943 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS 1 20944 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT 6 20945 20946 /* Rx3 :: anaRxControlPci :: link_en_force_SM [05:05] */ 20947 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK 0x0020 20948 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN 0 20949 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS 1 20950 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT 5 20951 20952 /* Rx3 :: anaRxControlPci :: link_en_r [04:04] */ 20953 #define RX3_ANARXCONTROLPCI_LINK_EN_R_MASK 0x0010 20954 #define RX3_ANARXCONTROLPCI_LINK_EN_R_ALIGN 0 20955 #define RX3_ANARXCONTROLPCI_LINK_EN_R_BITS 1 20956 #define RX3_ANARXCONTROLPCI_LINK_EN_R_SHIFT 4 20957 20958 /* Rx3 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */ 20959 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK 0x0008 20960 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN 0 20961 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS 1 20962 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT 3 20963 20964 /* Rx3 :: anaRxControlPci :: rx_polarity_r [02:02] */ 20965 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_MASK 0x0004 20966 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN 0 20967 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_BITS 1 20968 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT 2 20969 20970 /* Rx3 :: anaRxControlPci :: integ_mode_SM [01:00] */ 20971 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_MASK 0x0003 20972 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN 0 20973 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_BITS 2 20974 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT 0 20975 20976 20977 /**************************************************************************** 20978 * Rx3 :: anaRxAstatus 20979 */ 20980 /* Rx3 :: anaRxAstatus :: sigdet [15:15] */ 20981 #define RX3_ANARXASTATUS_SIGDET_MASK 0x8000 20982 #define RX3_ANARXASTATUS_SIGDET_ALIGN 0 20983 #define RX3_ANARXASTATUS_SIGDET_BITS 1 20984 #define RX3_ANARXASTATUS_SIGDET_SHIFT 15 20985 20986 /* Rx3 :: anaRxAstatus :: rx_pf [14:11] */ 20987 #define RX3_ANARXASTATUS_RX_PF_MASK 0x7800 20988 #define RX3_ANARXASTATUS_RX_PF_ALIGN 0 20989 #define RX3_ANARXASTATUS_RX_PF_BITS 4 20990 #define RX3_ANARXASTATUS_RX_PF_SHIFT 11 20991 20992 /* Rx3 :: anaRxAstatus :: tap1_dfe_gray [10:05] */ 20993 #define RX3_ANARXASTATUS_TAP1_DFE_GRAY_MASK 0x07e0 20994 #define RX3_ANARXASTATUS_TAP1_DFE_GRAY_ALIGN 0 20995 #define RX3_ANARXASTATUS_TAP1_DFE_GRAY_BITS 6 20996 #define RX3_ANARXASTATUS_TAP1_DFE_GRAY_SHIFT 5 20997 20998 /* Rx3 :: anaRxAstatus :: vga [04:00] */ 20999 #define RX3_ANARXASTATUS_VGA_MASK 0x001f 21000 #define RX3_ANARXASTATUS_VGA_ALIGN 0 21001 #define RX3_ANARXASTATUS_VGA_BITS 5 21002 #define RX3_ANARXASTATUS_VGA_SHIFT 0 21003 21004 21005 /**************************************************************************** 21006 * Rx3 :: anaRxAControl1 21007 */ 21008 /* Rx3 :: anaRxAControl1 :: imode_vcm [15:15] */ 21009 #define RX3_ANARXACONTROL1_IMODE_VCM_MASK 0x8000 21010 #define RX3_ANARXACONTROL1_IMODE_VCM_ALIGN 0 21011 #define RX3_ANARXACONTROL1_IMODE_VCM_BITS 1 21012 #define RX3_ANARXACONTROL1_IMODE_VCM_SHIFT 15 21013 21014 /* Rx3 :: anaRxAControl1 :: imin_vcm [14:14] */ 21015 #define RX3_ANARXACONTROL1_IMIN_VCM_MASK 0x4000 21016 #define RX3_ANARXACONTROL1_IMIN_VCM_ALIGN 0 21017 #define RX3_ANARXACONTROL1_IMIN_VCM_BITS 1 21018 #define RX3_ANARXACONTROL1_IMIN_VCM_SHIFT 14 21019 21020 /* Rx3 :: anaRxAControl1 :: imax_sigdet [13:13] */ 21021 #define RX3_ANARXACONTROL1_IMAX_SIGDET_MASK 0x2000 21022 #define RX3_ANARXACONTROL1_IMAX_SIGDET_ALIGN 0 21023 #define RX3_ANARXACONTROL1_IMAX_SIGDET_BITS 1 21024 #define RX3_ANARXACONTROL1_IMAX_SIGDET_SHIFT 13 21025 21026 /* Rx3 :: anaRxAControl1 :: imode_sigdet [12:12] */ 21027 #define RX3_ANARXACONTROL1_IMODE_SIGDET_MASK 0x1000 21028 #define RX3_ANARXACONTROL1_IMODE_SIGDET_ALIGN 0 21029 #define RX3_ANARXACONTROL1_IMODE_SIGDET_BITS 1 21030 #define RX3_ANARXACONTROL1_IMODE_SIGDET_SHIFT 12 21031 21032 /* Rx3 :: anaRxAControl1 :: imin_sigdet [11:11] */ 21033 #define RX3_ANARXACONTROL1_IMIN_SIGDET_MASK 0x0800 21034 #define RX3_ANARXACONTROL1_IMIN_SIGDET_ALIGN 0 21035 #define RX3_ANARXACONTROL1_IMIN_SIGDET_BITS 1 21036 #define RX3_ANARXACONTROL1_IMIN_SIGDET_SHIFT 11 21037 21038 /* Rx3 :: anaRxAControl1 :: refh_rx [10:10] */ 21039 #define RX3_ANARXACONTROL1_REFH_RX_MASK 0x0400 21040 #define RX3_ANARXACONTROL1_REFH_RX_ALIGN 0 21041 #define RX3_ANARXACONTROL1_REFH_RX_BITS 1 21042 #define RX3_ANARXACONTROL1_REFH_RX_SHIFT 10 21043 21044 /* Rx3 :: anaRxAControl1 :: refl_rx [09:09] */ 21045 #define RX3_ANARXACONTROL1_REFL_RX_MASK 0x0200 21046 #define RX3_ANARXACONTROL1_REFL_RX_ALIGN 0 21047 #define RX3_ANARXACONTROL1_REFL_RX_BITS 1 21048 #define RX3_ANARXACONTROL1_REFL_RX_SHIFT 9 21049 21050 /* Rx3 :: anaRxAControl1 :: tport_en [08:08] */ 21051 #define RX3_ANARXACONTROL1_TPORT_EN_MASK 0x0100 21052 #define RX3_ANARXACONTROL1_TPORT_EN_ALIGN 0 21053 #define RX3_ANARXACONTROL1_TPORT_EN_BITS 1 21054 #define RX3_ANARXACONTROL1_TPORT_EN_SHIFT 8 21055 21056 /* Rx3 :: anaRxAControl1 :: vddrb_bgb [07:07] */ 21057 #define RX3_ANARXACONTROL1_VDDRB_BGB_MASK 0x0080 21058 #define RX3_ANARXACONTROL1_VDDRB_BGB_ALIGN 0 21059 #define RX3_ANARXACONTROL1_VDDRB_BGB_BITS 1 21060 #define RX3_ANARXACONTROL1_VDDRB_BGB_SHIFT 7 21061 21062 /* Rx3 :: anaRxAControl1 :: sig_pwrdn [06:06] */ 21063 #define RX3_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 21064 #define RX3_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 21065 #define RX3_ANARXACONTROL1_SIG_PWRDN_BITS 1 21066 #define RX3_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 21067 21068 /* Rx3 :: anaRxAControl1 :: offset_ctrl [05:03] */ 21069 #define RX3_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 21070 #define RX3_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 21071 #define RX3_ANARXACONTROL1_OFFSET_CTRL_BITS 3 21072 #define RX3_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 21073 21074 /* Rx3 :: anaRxAControl1 :: offset_sel [02:02] */ 21075 #define RX3_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 21076 #define RX3_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 21077 #define RX3_ANARXACONTROL1_OFFSET_SEL_BITS 1 21078 #define RX3_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 21079 21080 /* Rx3 :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */ 21081 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY1_MASK 0x0002 21082 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN 0 21083 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY1_BITS 1 21084 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT 1 21085 21086 /* Rx3 :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */ 21087 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY0_MASK 0x0001 21088 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN 0 21089 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY0_BITS 1 21090 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT 0 21091 21092 21093 /**************************************************************************** 21094 * Rx3 :: anaRxAControl2 21095 */ 21096 /* Rx3 :: anaRxAControl2 :: imax_ctat [15:15] */ 21097 #define RX3_ANARXACONTROL2_IMAX_CTAT_MASK 0x8000 21098 #define RX3_ANARXACONTROL2_IMAX_CTAT_ALIGN 0 21099 #define RX3_ANARXACONTROL2_IMAX_CTAT_BITS 1 21100 #define RX3_ANARXACONTROL2_IMAX_CTAT_SHIFT 15 21101 21102 /* Rx3 :: anaRxAControl2 :: imode_ctat [14:14] */ 21103 #define RX3_ANARXACONTROL2_IMODE_CTAT_MASK 0x4000 21104 #define RX3_ANARXACONTROL2_IMODE_CTAT_ALIGN 0 21105 #define RX3_ANARXACONTROL2_IMODE_CTAT_BITS 1 21106 #define RX3_ANARXACONTROL2_IMODE_CTAT_SHIFT 14 21107 21108 /* Rx3 :: anaRxAControl2 :: imin_ctat [13:13] */ 21109 #define RX3_ANARXACONTROL2_IMIN_CTAT_MASK 0x2000 21110 #define RX3_ANARXACONTROL2_IMIN_CTAT_ALIGN 0 21111 #define RX3_ANARXACONTROL2_IMIN_CTAT_BITS 1 21112 #define RX3_ANARXACONTROL2_IMIN_CTAT_SHIFT 13 21113 21114 /* Rx3 :: anaRxAControl2 :: imax_eqfl [12:12] */ 21115 #define RX3_ANARXACONTROL2_IMAX_EQFL_MASK 0x1000 21116 #define RX3_ANARXACONTROL2_IMAX_EQFL_ALIGN 0 21117 #define RX3_ANARXACONTROL2_IMAX_EQFL_BITS 1 21118 #define RX3_ANARXACONTROL2_IMAX_EQFL_SHIFT 12 21119 21120 /* Rx3 :: anaRxAControl2 :: imode_eqfl [11:11] */ 21121 #define RX3_ANARXACONTROL2_IMODE_EQFL_MASK 0x0800 21122 #define RX3_ANARXACONTROL2_IMODE_EQFL_ALIGN 0 21123 #define RX3_ANARXACONTROL2_IMODE_EQFL_BITS 1 21124 #define RX3_ANARXACONTROL2_IMODE_EQFL_SHIFT 11 21125 21126 /* Rx3 :: anaRxAControl2 :: imin_eqfl [10:10] */ 21127 #define RX3_ANARXACONTROL2_IMIN_EQFL_MASK 0x0400 21128 #define RX3_ANARXACONTROL2_IMIN_EQFL_ALIGN 0 21129 #define RX3_ANARXACONTROL2_IMIN_EQFL_BITS 1 21130 #define RX3_ANARXACONTROL2_IMIN_EQFL_SHIFT 10 21131 21132 /* Rx3 :: anaRxAControl2 :: imax_dfesum [09:09] */ 21133 #define RX3_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 21134 #define RX3_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 21135 #define RX3_ANARXACONTROL2_IMAX_DFESUM_BITS 1 21136 #define RX3_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 21137 21138 /* Rx3 :: anaRxAControl2 :: imode_dfesum [08:08] */ 21139 #define RX3_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 21140 #define RX3_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 21141 #define RX3_ANARXACONTROL2_IMODE_DFESUM_BITS 1 21142 #define RX3_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 21143 21144 /* Rx3 :: anaRxAControl2 :: imin_dfesum [07:07] */ 21145 #define RX3_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 21146 #define RX3_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 21147 #define RX3_ANARXACONTROL2_IMIN_DFESUM_BITS 1 21148 #define RX3_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 21149 21150 /* Rx3 :: anaRxAControl2 :: imax_vga [06:06] */ 21151 #define RX3_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 21152 #define RX3_ANARXACONTROL2_IMAX_VGA_ALIGN 0 21153 #define RX3_ANARXACONTROL2_IMAX_VGA_BITS 1 21154 #define RX3_ANARXACONTROL2_IMAX_VGA_SHIFT 6 21155 21156 /* Rx3 :: anaRxAControl2 :: imode_vga [05:05] */ 21157 #define RX3_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 21158 #define RX3_ANARXACONTROL2_IMODE_VGA_ALIGN 0 21159 #define RX3_ANARXACONTROL2_IMODE_VGA_BITS 1 21160 #define RX3_ANARXACONTROL2_IMODE_VGA_SHIFT 5 21161 21162 /* Rx3 :: anaRxAControl2 :: imin_vga [04:04] */ 21163 #define RX3_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 21164 #define RX3_ANARXACONTROL2_IMIN_VGA_ALIGN 0 21165 #define RX3_ANARXACONTROL2_IMIN_VGA_BITS 1 21166 #define RX3_ANARXACONTROL2_IMIN_VGA_SHIFT 4 21167 21168 /* Rx3 :: anaRxAControl2 :: imax_interp [03:03] */ 21169 #define RX3_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 21170 #define RX3_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 21171 #define RX3_ANARXACONTROL2_IMAX_INTERP_BITS 1 21172 #define RX3_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 21173 21174 /* Rx3 :: anaRxAControl2 :: imode_interp [02:02] */ 21175 #define RX3_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 21176 #define RX3_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 21177 #define RX3_ANARXACONTROL2_IMODE_INTERP_BITS 1 21178 #define RX3_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 21179 21180 /* Rx3 :: anaRxAControl2 :: imin_interp [01:01] */ 21181 #define RX3_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 21182 #define RX3_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 21183 #define RX3_ANARXACONTROL2_IMIN_INTERP_BITS 1 21184 #define RX3_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 21185 21186 /* Rx3 :: anaRxAControl2 :: imax_vcm [00:00] */ 21187 #define RX3_ANARXACONTROL2_IMAX_VCM_MASK 0x0001 21188 #define RX3_ANARXACONTROL2_IMAX_VCM_ALIGN 0 21189 #define RX3_ANARXACONTROL2_IMAX_VCM_BITS 1 21190 #define RX3_ANARXACONTROL2_IMAX_VCM_SHIFT 0 21191 21192 21193 /**************************************************************************** 21194 * Rx3 :: anaRxAControl3 21195 */ 21196 /* Rx3 :: anaRxAControl3 :: en_clk16 [15:15] */ 21197 #define RX3_ANARXACONTROL3_EN_CLK16_MASK 0x8000 21198 #define RX3_ANARXACONTROL3_EN_CLK16_ALIGN 0 21199 #define RX3_ANARXACONTROL3_EN_CLK16_BITS 1 21200 #define RX3_ANARXACONTROL3_EN_CLK16_SHIFT 15 21201 21202 /* Rx3 :: anaRxAControl3 :: en_clk33 [14:14] */ 21203 #define RX3_ANARXACONTROL3_EN_CLK33_MASK 0x4000 21204 #define RX3_ANARXACONTROL3_EN_CLK33_ALIGN 0 21205 #define RX3_ANARXACONTROL3_EN_CLK33_BITS 1 21206 #define RX3_ANARXACONTROL3_EN_CLK33_SHIFT 14 21207 21208 /* Rx3 :: anaRxAControl3 :: en_vcctrl [13:13] */ 21209 #define RX3_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 21210 #define RX3_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 21211 #define RX3_ANARXACONTROL3_EN_VCCTRL_BITS 1 21212 #define RX3_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 21213 21214 /* Rx3 :: anaRxAControl3 :: sel_th4dfe1 [12:12] */ 21215 #define RX3_ANARXACONTROL3_SEL_TH4DFE1_MASK 0x1000 21216 #define RX3_ANARXACONTROL3_SEL_TH4DFE1_ALIGN 0 21217 #define RX3_ANARXACONTROL3_SEL_TH4DFE1_BITS 1 21218 #define RX3_ANARXACONTROL3_SEL_TH4DFE1_SHIFT 12 21219 21220 /* Rx3 :: anaRxAControl3 :: sel_th4dfe0 [11:11] */ 21221 #define RX3_ANARXACONTROL3_SEL_TH4DFE0_MASK 0x0800 21222 #define RX3_ANARXACONTROL3_SEL_TH4DFE0_ALIGN 0 21223 #define RX3_ANARXACONTROL3_SEL_TH4DFE0_BITS 1 21224 #define RX3_ANARXACONTROL3_SEL_TH4DFE0_SHIFT 11 21225 21226 /* Rx3 :: anaRxAControl3 :: selugbw1 [10:10] */ 21227 #define RX3_ANARXACONTROL3_SELUGBW1_MASK 0x0400 21228 #define RX3_ANARXACONTROL3_SELUGBW1_ALIGN 0 21229 #define RX3_ANARXACONTROL3_SELUGBW1_BITS 1 21230 #define RX3_ANARXACONTROL3_SELUGBW1_SHIFT 10 21231 21232 /* Rx3 :: anaRxAControl3 :: selugbw0 [09:09] */ 21233 #define RX3_ANARXACONTROL3_SELUGBW0_MASK 0x0200 21234 #define RX3_ANARXACONTROL3_SELUGBW0_ALIGN 0 21235 #define RX3_ANARXACONTROL3_SELUGBW0_BITS 1 21236 #define RX3_ANARXACONTROL3_SELUGBW0_SHIFT 9 21237 21238 /* Rx3 :: anaRxAControl3 :: imax_dfetap [08:08] */ 21239 #define RX3_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 21240 #define RX3_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 21241 #define RX3_ANARXACONTROL3_IMAX_DFETAP_BITS 1 21242 #define RX3_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 21243 21244 /* Rx3 :: anaRxAControl3 :: imode_dfetap [07:07] */ 21245 #define RX3_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 21246 #define RX3_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 21247 #define RX3_ANARXACONTROL3_IMODE_DFETAP_BITS 1 21248 #define RX3_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 21249 21250 /* Rx3 :: anaRxAControl3 :: imin_dfetap [06:06] */ 21251 #define RX3_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 21252 #define RX3_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 21253 #define RX3_ANARXACONTROL3_IMIN_DFETAP_BITS 1 21254 #define RX3_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 21255 21256 /* Rx3 :: anaRxAControl3 :: imax_slcd2c [05:05] */ 21257 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 21258 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 21259 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 21260 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 21261 21262 /* Rx3 :: anaRxAControl3 :: imode_slcd2c [04:04] */ 21263 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 21264 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 21265 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 21266 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 21267 21268 /* Rx3 :: anaRxAControl3 :: imin_slcd2c [03:03] */ 21269 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 21270 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 21271 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 21272 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 21273 21274 /* Rx3 :: anaRxAControl3 :: imax_dfevref [02:02] */ 21275 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 21276 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 21277 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 21278 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 21279 21280 /* Rx3 :: anaRxAControl3 :: imode_dfevref [01:01] */ 21281 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 21282 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 21283 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 21284 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 21285 21286 /* Rx3 :: anaRxAControl3 :: imin_dfevref [00:00] */ 21287 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 21288 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 21289 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 21290 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 21291 21292 21293 /**************************************************************************** 21294 * Warpcore_USER_RxB 21295 */ 21296 /**************************************************************************** 21297 * RxB :: anaRxStatus 21298 */ 21299 /* union - case sigdet_Status [15:00] */ 21300 /* RxB :: anaRxStatus :: cx4_sigdet [15:15] */ 21301 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 21302 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 21303 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 21304 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 21305 21306 /* RxB :: anaRxStatus :: reserved0 [14:13] */ 21307 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 21308 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 21309 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS 2 21310 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 21311 21312 /* RxB :: anaRxStatus :: rxSeqDone [12:12] */ 21313 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 21314 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 21315 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 21316 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 21317 21318 /* RxB :: anaRxStatus :: rx_sigdet_ll [11:11] */ 21319 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 21320 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 21321 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 21322 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 21323 21324 /* RxB :: anaRxStatus :: cs4_sigdet_ll [10:10] */ 21325 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 21326 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 21327 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 21328 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 21329 21330 /* RxB :: anaRxStatus :: rx_reset [09:09] */ 21331 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 21332 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 21333 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS 1 21334 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 21335 21336 /* RxB :: anaRxStatus :: rx_pwrdn [08:08] */ 21337 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 21338 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 21339 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 21340 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 21341 21342 /* RxB :: anaRxStatus :: reserved1 [07:00] */ 21343 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 21344 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 21345 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS 8 21346 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 21347 21348 21349 /* union - case sync_Status [15:00] */ 21350 /* RxB :: anaRxStatus :: reserved0 [15:11] */ 21351 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 21352 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN 0 21353 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS 5 21354 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT 11 21355 21356 /* RxB :: anaRxStatus :: test_acq_en [10:10] */ 21357 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 21358 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 21359 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 21360 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 21361 21362 /* RxB :: anaRxStatus :: reserved1 [09:09] */ 21363 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 21364 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN 0 21365 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS 1 21366 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT 9 21367 21368 /* RxB :: anaRxStatus :: rxSeqStart [08:08] */ 21369 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 21370 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 21371 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS 1 21372 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 21373 21374 /* RxB :: anaRxStatus :: mux_comadj_sync_status [07:07] */ 21375 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 21376 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 21377 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 21378 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 21379 21380 /* RxB :: anaRxStatus :: sync_status [06:06] */ 21381 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 21382 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 21383 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 21384 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 21385 21386 /* RxB :: anaRxStatus :: rx_sigdet [05:05] */ 21387 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 21388 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 21389 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS 1 21390 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 21391 21392 /* RxB :: anaRxStatus :: reserved2 [04:03] */ 21393 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 21394 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN 0 21395 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS 2 21396 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT 3 21397 21398 /* RxB :: anaRxStatus :: saturate_status [02:02] */ 21399 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 21400 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 21401 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 21402 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 21403 21404 /* RxB :: anaRxStatus :: cx4_sigdet [01:01] */ 21405 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 21406 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 21407 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 21408 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 21409 21410 /* RxB :: anaRxStatus :: rxSeqDone [00:00] */ 21411 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 21412 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 21413 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS 1 21414 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 21415 21416 21417 /* union - case rxTestSel_0 [15:00] */ 21418 /* RxB :: anaRxStatus :: reserved0 [15:10] */ 21419 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 21420 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 21421 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS 6 21422 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 21423 21424 /* RxB :: anaRxStatus :: indck_mode_en [09:09] */ 21425 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 21426 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 21427 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 21428 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 21429 21430 /* RxB :: anaRxStatus :: pci_mode_en [08:08] */ 21431 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 21432 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 21433 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 21434 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 21435 21436 /* RxB :: anaRxStatus :: rx_polarity [07:07] */ 21437 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 21438 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 21439 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 21440 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 21441 21442 /* RxB :: anaRxStatus :: rxpol_flip [06:06] */ 21443 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 21444 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 21445 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 21446 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 21447 21448 /* RxB :: anaRxStatus :: comma_mask [05:05] */ 21449 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 21450 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 21451 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 21452 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 21453 21454 /* RxB :: anaRxStatus :: link_en_r [04:04] */ 21455 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 21456 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 21457 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 21458 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 21459 21460 /* RxB :: anaRxStatus :: comma_adj_en [03:03] */ 21461 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 21462 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 21463 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 21464 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 21465 21466 /* RxB :: anaRxStatus :: comma_adj_en_ext [02:02] */ 21467 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 21468 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 21469 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 21470 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 21471 21472 /* RxB :: anaRxStatus :: reserved1 [01:00] */ 21473 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 21474 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 21475 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS 2 21476 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 21477 21478 21479 /* union - case rxTestSel_1 [15:00] */ 21480 /* RxB :: anaRxStatus :: reserved0 [15:05] */ 21481 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 21482 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 21483 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS 11 21484 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 21485 21486 /* RxB :: anaRxStatus :: cdrAcqDone_r2 [04:04] */ 21487 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 21488 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 21489 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 21490 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 21491 21492 /* RxB :: anaRxStatus :: freq_sel_PC [03:03] */ 21493 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 21494 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 21495 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 21496 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 21497 21498 /* RxB :: anaRxStatus :: freq_sel_SM [02:02] */ 21499 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 21500 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 21501 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 21502 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 21503 21504 /* RxB :: anaRxStatus :: integ_mode_SM [01:00] */ 21505 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 21506 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 21507 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 21508 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 21509 21510 21511 /* union - case scale_Status [15:00] */ 21512 /* RxB :: anaRxStatus :: prop_scale [15:12] */ 21513 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 21514 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 21515 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS 4 21516 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 21517 21518 /* RxB :: anaRxStatus :: integ_scale [11:08] */ 21519 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 21520 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 21521 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 21522 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 21523 21524 /* RxB :: anaRxStatus :: prop_scale_acq [07:04] */ 21525 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 21526 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 21527 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 21528 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 21529 21530 /* RxB :: anaRxStatus :: integ_scale_acq [03:00] */ 21531 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 21532 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 21533 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 21534 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 21535 21536 21537 /* union - case adc_CdrStatus1 [15:00] */ 21538 /* RxB :: anaRxStatus :: reserved0 [15:07] */ 21539 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 21540 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 21541 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 21542 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 21543 21544 /* RxB :: anaRxStatus :: rxMuxCkSel [06:06] */ 21545 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 21546 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 21547 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 21548 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 21549 21550 /* RxB :: anaRxStatus :: glpbk_combo [05:05] */ 21551 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 21552 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 21553 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 21554 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 21555 21556 /* RxB :: anaRxStatus :: clockSwitchSel [04:04] */ 21557 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 21558 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 21559 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 21560 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 21561 21562 /* RxB :: anaRxStatus :: rxck_tst [03:03] */ 21563 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 21564 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 21565 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 21566 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 21567 21568 /* RxB :: anaRxStatus :: rxck_i [02:02] */ 21569 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 21570 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 21571 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 21572 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 21573 21574 /* RxB :: anaRxStatus :: refclk [01:01] */ 21575 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 21576 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 21577 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 21578 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 21579 21580 /* RxB :: anaRxStatus :: pll_bypass [00:00] */ 21581 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 21582 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 21583 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 21584 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 21585 21586 21587 /* union - case adc_CdrStatus2 [15:00] */ 21588 /* RxB :: anaRxStatus :: reserved0 [15:06] */ 21589 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 21590 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 21591 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 21592 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 21593 21594 /* RxB :: anaRxStatus :: rxMuxCkSel [05:05] */ 21595 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 21596 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 21597 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 21598 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 21599 21600 /* RxB :: anaRxStatus :: rxSeqStart [04:04] */ 21601 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 21602 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 21603 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 21604 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 21605 21606 /* RxB :: anaRxStatus :: reserved1 [03:01] */ 21607 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 21608 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 21609 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 21610 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 21611 21612 /* RxB :: anaRxStatus :: rxSeqDone [00:00] */ 21613 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 21614 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 21615 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 21616 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 21617 21618 21619 /* union - case adc_CdrStatus3 [15:00] */ 21620 /* RxB :: anaRxStatus :: reserved0 [15:04] */ 21621 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 21622 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 21623 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 21624 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 21625 21626 /* RxB :: anaRxStatus :: rxSeqStart [03:03] */ 21627 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 21628 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 21629 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 21630 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 21631 21632 /* RxB :: anaRxStatus :: reserved1 [02:01] */ 21633 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 21634 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 21635 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 21636 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 21637 21638 /* RxB :: anaRxStatus :: allow_increment_PC [00:00] */ 21639 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 21640 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 21641 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 21642 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 21643 21644 21645 /* union - case adc_CdrStatus4 [15:00] */ 21646 /* RxB :: anaRxStatus :: reserved0 [15:08] */ 21647 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 21648 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 21649 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 21650 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 21651 21652 /* RxB :: anaRxStatus :: rx_pwrdn [07:07] */ 21653 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 21654 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 21655 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 21656 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 21657 21658 /* RxB :: anaRxStatus :: freq_sel [06:06] */ 21659 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 21660 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 21661 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 21662 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 21663 21664 /* RxB :: anaRxStatus :: pll_lock_rstb [05:05] */ 21665 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 21666 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 21667 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 21668 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 21669 21670 /* RxB :: anaRxStatus :: pwrdn [04:04] */ 21671 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 21672 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 21673 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 21674 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 21675 21676 /* RxB :: anaRxStatus :: reserved1 [03:00] */ 21677 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 21678 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 21679 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 21680 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 21681 21682 21683 /* union - case adc_CdrStatus5 [15:00] */ 21684 /* RxB :: anaRxStatus :: reserved0 [15:00] */ 21685 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 21686 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 21687 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 21688 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 21689 21690 21691 /* union - case adc_CdrStatus6 [15:00] */ 21692 /* RxB :: anaRxStatus :: reserved0 [15:05] */ 21693 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 21694 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 21695 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 21696 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 21697 21698 /* RxB :: anaRxStatus :: rx_reset [04:04] */ 21699 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 21700 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 21701 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 21702 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 21703 21704 /* RxB :: anaRxStatus :: rx_pwrdn [03:03] */ 21705 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 21706 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 21707 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 21708 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 21709 21710 /* RxB :: anaRxStatus :: reset_anlg [02:02] */ 21711 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 21712 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 21713 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 21714 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 21715 21716 /* RxB :: anaRxStatus :: pwrdn_rx [01:01] */ 21717 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 21718 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 21719 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 21720 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 21721 21722 /* RxB :: anaRxStatus :: pwrdn_pll [00:00] */ 21723 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 21724 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 21725 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 21726 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 21727 21728 21729 /* union - case adc_CdrStatus7e [15:00] */ 21730 /* RxB :: anaRxStatus :: reserved0 [15:05] */ 21731 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 21732 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 21733 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 21734 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 21735 21736 /* RxB :: anaRxStatus :: rxck0_even [04:04] */ 21737 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 21738 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 21739 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 21740 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 21741 21742 /* RxB :: anaRxStatus :: rxck1_even [03:03] */ 21743 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 21744 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 21745 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 21746 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 21747 21748 /* RxB :: anaRxStatus :: comdet_even [02:02] */ 21749 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 21750 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 21751 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 21752 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 21753 21754 /* RxB :: anaRxStatus :: en_cdet_even [01:01] */ 21755 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 21756 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 21757 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 21758 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 21759 21760 /* RxB :: anaRxStatus :: comma_adj_en_even [00:00] */ 21761 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 21762 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 21763 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 21764 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 21765 21766 21767 /* union - case adc_CdrStatus7o [15:00] */ 21768 /* RxB :: anaRxStatus :: reserved0 [15:05] */ 21769 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 21770 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 21771 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 21772 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 21773 21774 /* RxB :: anaRxStatus :: rxck0_odd [04:04] */ 21775 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 21776 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 21777 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 21778 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 21779 21780 /* RxB :: anaRxStatus :: rxck1_odd [03:03] */ 21781 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 21782 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 21783 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 21784 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 21785 21786 /* RxB :: anaRxStatus :: comdet_odd [02:02] */ 21787 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 21788 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 21789 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 21790 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 21791 21792 /* RxB :: anaRxStatus :: en_cdet_odd [01:01] */ 21793 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 21794 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 21795 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 21796 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 21797 21798 /* RxB :: anaRxStatus :: comma_adj_en_odd [00:00] */ 21799 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 21800 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 21801 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 21802 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 21803 21804 21805 /* union - case adc_CdrStatus8 [15:00] */ 21806 /* RxB :: anaRxStatus :: reserved0 [15:01] */ 21807 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 21808 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 21809 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 21810 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 21811 21812 /* RxB :: anaRxStatus :: sigdet [00:00] */ 21813 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 21814 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 21815 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 21816 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 21817 21818 21819 /* union - case adc_CdrStatus9 [15:00] */ 21820 /* RxB :: anaRxStatus :: reserved0 [15:00] */ 21821 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 21822 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 21823 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 21824 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 21825 21826 21827 /* union - case adc_CdrStatus10 [15:00] */ 21828 /* RxB :: anaRxStatus :: reserved0 [15:07] */ 21829 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 21830 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 21831 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 21832 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 21833 21834 /* RxB :: anaRxStatus :: prbs_en [06:06] */ 21835 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 21836 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 21837 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 21838 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 21839 21840 /* RxB :: anaRxStatus :: rstb_tst [05:05] */ 21841 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 21842 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 21843 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 21844 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 21845 21846 /* RxB :: anaRxStatus :: reserved1 [04:04] */ 21847 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 21848 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 21849 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 21850 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 21851 21852 /* RxB :: anaRxStatus :: prbs_state [03:00] */ 21853 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 21854 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 21855 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 21856 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 21857 21858 21859 /* union - case adc_CdrStatus11 [15:00] */ 21860 /* RxB :: anaRxStatus :: reserved0 [15:00] */ 21861 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 21862 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 21863 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 21864 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 21865 21866 21867 /* union - case adc_CdrStatus12_1 [15:00] */ 21868 /* RxB :: anaRxStatus :: reserved0 [15:06] */ 21869 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 21870 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 21871 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 21872 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 21873 21874 /* RxB :: anaRxStatus :: enable4 [05:05] */ 21875 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 21876 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 21877 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 21878 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 21879 21880 /* RxB :: anaRxStatus :: radr_test [04:00] */ 21881 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 21882 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 21883 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 21884 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 21885 21886 21887 /* union - case adc_CdrStatus12_2 [15:00] */ 21888 /* RxB :: anaRxStatus :: reserved0 [15:05] */ 21889 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 21890 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 21891 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 21892 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 21893 21894 /* RxB :: anaRxStatus :: wadr_test [04:00] */ 21895 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 21896 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 21897 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 21898 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 21899 21900 21901 /* union - case adc_CdrStatus12_3 [15:00] */ 21902 /* RxB :: anaRxStatus :: reserved0 [15:06] */ 21903 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 21904 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 21905 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 21906 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 21907 21908 /* RxB :: anaRxStatus :: rxck_66B_tmux [05:05] */ 21909 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 21910 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 21911 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 21912 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 21913 21914 /* RxB :: anaRxStatus :: rstb_66B [04:04] */ 21915 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 21916 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 21917 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 21918 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 21919 21920 /* RxB :: anaRxStatus :: prstb_66B_mux [03:03] */ 21921 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 21922 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 21923 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 21924 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 21925 21926 /* RxB :: anaRxStatus :: rxck_i66_tmux [02:02] */ 21927 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 21928 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 21929 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 21930 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 21931 21932 /* RxB :: anaRxStatus :: rstb_i66 [01:01] */ 21933 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 21934 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 21935 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 21936 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 21937 21938 /* RxB :: anaRxStatus :: prstb_i66_mux [00:00] */ 21939 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 21940 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 21941 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 21942 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 21943 21944 21945 /* union - case adc_CdrStatus12_4 [15:00] */ 21946 /* RxB :: anaRxStatus :: reserved0 [15:04] */ 21947 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 21948 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 21949 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 21950 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 21951 21952 /* RxB :: anaRxStatus :: rfifo_error_r [03:02] */ 21953 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 21954 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 21955 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 21956 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 21957 21958 /* RxB :: anaRxStatus :: rfifo_unflow [01:01] */ 21959 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 21960 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 21961 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 21962 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 21963 21964 /* RxB :: anaRxStatus :: rfifo_ovflow [00:00] */ 21965 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 21966 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 21967 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 21968 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 21969 21970 21971 /* union - case integ_Status [15:00] */ 21972 /* RxB :: anaRxStatus :: integ_status [15:00] */ 21973 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 21974 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 21975 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 21976 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 21977 21978 21979 /* union - case vco_Status [15:00] */ 21980 /* RxB :: anaRxStatus :: vco_status [15:00] */ 21981 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 21982 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 21983 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS 16 21984 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 21985 21986 21987 /* union - case prbs_Status [15:00] */ 21988 /* RxB :: anaRxStatus :: prbs_lock [15:15] */ 21989 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 21990 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 21991 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 21992 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 21993 21994 /* RxB :: anaRxStatus :: prbs_stky [14:14] */ 21995 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 21996 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 21997 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS 1 21998 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 21999 22000 /* RxB :: anaRxStatus :: prbs_errors [13:00] */ 22001 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_MASK 0x3fff 22002 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_ALIGN 0 22003 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_BITS 14 22004 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_SHIFT 0 22005 22006 22007 22008 /**************************************************************************** 22009 * RxB :: anaRxControl 22010 */ 22011 /* RxB :: anaRxControl :: reserved0 [15:10] */ 22012 #define RXB_ANARXCONTROL_RESERVED0_MASK 0xfc00 22013 #define RXB_ANARXCONTROL_RESERVED0_ALIGN 0 22014 #define RXB_ANARXCONTROL_RESERVED0_BITS 6 22015 #define RXB_ANARXCONTROL_RESERVED0_SHIFT 10 22016 22017 /* RxB :: anaRxControl :: override_sigdet_en [09:09] */ 22018 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 22019 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 22020 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 22021 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 22022 22023 /* RxB :: anaRxControl :: override_sigdet_val [08:08] */ 22024 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 22025 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 22026 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 22027 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 22028 22029 /* RxB :: anaRxControl :: reserved1 [07:03] */ 22030 #define RXB_ANARXCONTROL_RESERVED1_MASK 0x00f8 22031 #define RXB_ANARXCONTROL_RESERVED1_ALIGN 0 22032 #define RXB_ANARXCONTROL_RESERVED1_BITS 5 22033 #define RXB_ANARXCONTROL_RESERVED1_SHIFT 3 22034 22035 /* RxB :: anaRxControl :: status_sel [02:00] */ 22036 #define RXB_ANARXCONTROL_STATUS_SEL_MASK 0x0007 22037 #define RXB_ANARXCONTROL_STATUS_SEL_ALIGN 0 22038 #define RXB_ANARXCONTROL_STATUS_SEL_BITS 3 22039 #define RXB_ANARXCONTROL_STATUS_SEL_SHIFT 0 22040 #define RXB_ANARXCONTROL_STATUS_SEL_sigdetStatus 0 22041 #define RXB_ANARXCONTROL_STATUS_SEL_syncStatus 1 22042 #define RXB_ANARXCONTROL_STATUS_SEL_rxTestSel 2 22043 #define RXB_ANARXCONTROL_STATUS_SEL_scaleStatus 3 22044 #define RXB_ANARXCONTROL_STATUS_SEL_adcCdrStatus 4 22045 #define RXB_ANARXCONTROL_STATUS_SEL_integStatus 5 22046 #define RXB_ANARXCONTROL_STATUS_SEL_vcoStatus 6 22047 #define RXB_ANARXCONTROL_STATUS_SEL_prbsStatus 7 22048 22049 22050 /**************************************************************************** 22051 * RxB :: anaRxSigdet 22052 */ 22053 /* RxB :: anaRxSigdet :: sigdetTime_SM [15:08] */ 22054 #define RXB_ANARXSIGDET_SIGDETTIME_SM_MASK 0xff00 22055 #define RXB_ANARXSIGDET_SIGDETTIME_SM_ALIGN 0 22056 #define RXB_ANARXSIGDET_SIGDETTIME_SM_BITS 8 22057 #define RXB_ANARXSIGDET_SIGDETTIME_SM_SHIFT 8 22058 22059 /* RxB :: anaRxSigdet :: cx4_sigdet_cnt_ld_SM [07:07] */ 22060 #define RXB_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_MASK 0x0080 22061 #define RXB_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_ALIGN 0 22062 #define RXB_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_BITS 1 22063 #define RXB_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_SHIFT 7 22064 22065 /* RxB :: anaRxSigdet :: ext_sigdet_en_SM [06:06] */ 22066 #define RXB_ANARXSIGDET_EXT_SIGDET_EN_SM_MASK 0x0040 22067 #define RXB_ANARXSIGDET_EXT_SIGDET_EN_SM_ALIGN 0 22068 #define RXB_ANARXSIGDET_EXT_SIGDET_EN_SM_BITS 1 22069 #define RXB_ANARXSIGDET_EXT_SIGDET_EN_SM_SHIFT 6 22070 22071 /* RxB :: anaRxSigdet :: cx4_sigdet_en_SM [05:05] */ 22072 #define RXB_ANARXSIGDET_CX4_SIGDET_EN_SM_MASK 0x0020 22073 #define RXB_ANARXSIGDET_CX4_SIGDET_EN_SM_ALIGN 0 22074 #define RXB_ANARXSIGDET_CX4_SIGDET_EN_SM_BITS 1 22075 #define RXB_ANARXSIGDET_CX4_SIGDET_EN_SM_SHIFT 5 22076 22077 /* RxB :: anaRxSigdet :: rx_sigdet_r [04:04] */ 22078 #define RXB_ANARXSIGDET_RX_SIGDET_R_MASK 0x0010 22079 #define RXB_ANARXSIGDET_RX_SIGDET_R_ALIGN 0 22080 #define RXB_ANARXSIGDET_RX_SIGDET_R_BITS 1 22081 #define RXB_ANARXSIGDET_RX_SIGDET_R_SHIFT 4 22082 22083 /* RxB :: anaRxSigdet :: rx_sigdet_force_r [03:03] */ 22084 #define RXB_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK 0x0008 22085 #define RXB_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN 0 22086 #define RXB_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS 1 22087 #define RXB_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT 3 22088 22089 /* RxB :: anaRxSigdet :: invert_rx_sigdet [02:02] */ 22090 #define RXB_ANARXSIGDET_INVERT_RX_SIGDET_MASK 0x0004 22091 #define RXB_ANARXSIGDET_INVERT_RX_SIGDET_ALIGN 0 22092 #define RXB_ANARXSIGDET_INVERT_RX_SIGDET_BITS 1 22093 #define RXB_ANARXSIGDET_INVERT_RX_SIGDET_SHIFT 2 22094 22095 /* RxB :: anaRxSigdet :: reserved0 [01:00] */ 22096 #define RXB_ANARXSIGDET_RESERVED0_MASK 0x0003 22097 #define RXB_ANARXSIGDET_RESERVED0_ALIGN 0 22098 #define RXB_ANARXSIGDET_RESERVED0_BITS 2 22099 #define RXB_ANARXSIGDET_RESERVED0_SHIFT 0 22100 22101 22102 /**************************************************************************** 22103 * RxB :: anaRxAControl4 22104 */ 22105 /* RxB :: anaRxAControl4 :: ana_clt4 [15:00] */ 22106 #define RXB_ANARXACONTROL4_ANA_CLT4_MASK 0xffff 22107 #define RXB_ANARXACONTROL4_ANA_CLT4_ALIGN 0 22108 #define RXB_ANARXACONTROL4_ANA_CLT4_BITS 16 22109 #define RXB_ANARXACONTROL4_ANA_CLT4_SHIFT 0 22110 22111 22112 /**************************************************************************** 22113 * RxB :: anaRxControl2_1G 22114 */ 22115 /* RxB :: anaRxControl2_1G :: reserved0 [15:15] */ 22116 #define RXB_ANARXCONTROL2_1G_RESERVED0_MASK 0x8000 22117 #define RXB_ANARXCONTROL2_1G_RESERVED0_ALIGN 0 22118 #define RXB_ANARXCONTROL2_1G_RESERVED0_BITS 1 22119 #define RXB_ANARXCONTROL2_1G_RESERVED0_SHIFT 15 22120 22121 /* RxB :: anaRxControl2_1G :: rx_prbs_w_val [14:14] */ 22122 #define RXB_ANARXCONTROL2_1G_RX_PRBS_W_VAL_MASK 0x4000 22123 #define RXB_ANARXCONTROL2_1G_RX_PRBS_W_VAL_ALIGN 0 22124 #define RXB_ANARXCONTROL2_1G_RX_PRBS_W_VAL_BITS 1 22125 #define RXB_ANARXCONTROL2_1G_RX_PRBS_W_VAL_SHIFT 14 22126 22127 /* RxB :: anaRxControl2_1G :: rx_prbs_w_force [13:13] */ 22128 #define RXB_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_MASK 0x2000 22129 #define RXB_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_ALIGN 0 22130 #define RXB_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_BITS 1 22131 #define RXB_ANARXCONTROL2_1G_RX_PRBS_W_FORCE_SHIFT 13 22132 22133 /* RxB :: anaRxControl2_1G :: rx_prbs_bswap [12:12] */ 22134 #define RXB_ANARXCONTROL2_1G_RX_PRBS_BSWAP_MASK 0x1000 22135 #define RXB_ANARXCONTROL2_1G_RX_PRBS_BSWAP_ALIGN 0 22136 #define RXB_ANARXCONTROL2_1G_RX_PRBS_BSWAP_BITS 1 22137 #define RXB_ANARXCONTROL2_1G_RX_PRBS_BSWAP_SHIFT 12 22138 22139 /* RxB :: anaRxControl2_1G :: rx_bitswap [11:11] */ 22140 #define RXB_ANARXCONTROL2_1G_RX_BITSWAP_MASK 0x0800 22141 #define RXB_ANARXCONTROL2_1G_RX_BITSWAP_ALIGN 0 22142 #define RXB_ANARXCONTROL2_1G_RX_BITSWAP_BITS 1 22143 #define RXB_ANARXCONTROL2_1G_RX_BITSWAP_SHIFT 11 22144 22145 /* RxB :: anaRxControl2_1G :: rst_rx_r [10:10] */ 22146 #define RXB_ANARXCONTROL2_1G_RST_RX_R_MASK 0x0400 22147 #define RXB_ANARXCONTROL2_1G_RST_RX_R_ALIGN 0 22148 #define RXB_ANARXCONTROL2_1G_RST_RX_R_BITS 1 22149 #define RXB_ANARXCONTROL2_1G_RST_RX_R_SHIFT 10 22150 22151 /* RxB :: anaRxControl2_1G :: pwdwn_rx_r [09:09] */ 22152 #define RXB_ANARXCONTROL2_1G_PWDWN_RX_R_MASK 0x0200 22153 #define RXB_ANARXCONTROL2_1G_PWDWN_RX_R_ALIGN 0 22154 #define RXB_ANARXCONTROL2_1G_PWDWN_RX_R_BITS 1 22155 #define RXB_ANARXCONTROL2_1G_PWDWN_RX_R_SHIFT 9 22156 22157 /* RxB :: anaRxControl2_1G :: prbs_order_rx_r_2 [08:08] */ 22158 #define RXB_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_MASK 0x0100 22159 #define RXB_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_ALIGN 0 22160 #define RXB_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_BITS 1 22161 #define RXB_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_2_SHIFT 8 22162 22163 /* RxB :: anaRxControl2_1G :: reserved1 [07:07] */ 22164 #define RXB_ANARXCONTROL2_1G_RESERVED1_MASK 0x0080 22165 #define RXB_ANARXCONTROL2_1G_RESERVED1_ALIGN 0 22166 #define RXB_ANARXCONTROL2_1G_RESERVED1_BITS 1 22167 #define RXB_ANARXCONTROL2_1G_RESERVED1_SHIFT 7 22168 22169 /* RxB :: anaRxControl2_1G :: prbs_sel_rx_r [06:06] */ 22170 #define RXB_ANARXCONTROL2_1G_PRBS_SEL_RX_R_MASK 0x0040 22171 #define RXB_ANARXCONTROL2_1G_PRBS_SEL_RX_R_ALIGN 0 22172 #define RXB_ANARXCONTROL2_1G_PRBS_SEL_RX_R_BITS 1 22173 #define RXB_ANARXCONTROL2_1G_PRBS_SEL_RX_R_SHIFT 6 22174 22175 /* RxB :: anaRxControl2_1G :: prbs_en_rx_r [05:05] */ 22176 #define RXB_ANARXCONTROL2_1G_PRBS_EN_RX_R_MASK 0x0020 22177 #define RXB_ANARXCONTROL2_1G_PRBS_EN_RX_R_ALIGN 0 22178 #define RXB_ANARXCONTROL2_1G_PRBS_EN_RX_R_BITS 1 22179 #define RXB_ANARXCONTROL2_1G_PRBS_EN_RX_R_SHIFT 5 22180 22181 /* RxB :: anaRxControl2_1G :: prbs_inv_rx_r [04:04] */ 22182 #define RXB_ANARXCONTROL2_1G_PRBS_INV_RX_R_MASK 0x0010 22183 #define RXB_ANARXCONTROL2_1G_PRBS_INV_RX_R_ALIGN 0 22184 #define RXB_ANARXCONTROL2_1G_PRBS_INV_RX_R_BITS 1 22185 #define RXB_ANARXCONTROL2_1G_PRBS_INV_RX_R_SHIFT 4 22186 22187 /* RxB :: anaRxControl2_1G :: prbs_order_rx_r [03:02] */ 22188 #define RXB_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_MASK 0x000c 22189 #define RXB_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_ALIGN 0 22190 #define RXB_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_BITS 2 22191 #define RXB_ANARXCONTROL2_1G_PRBS_ORDER_RX_R_SHIFT 2 22192 22193 /* RxB :: anaRxControl2_1G :: reserved2 [01:01] */ 22194 #define RXB_ANARXCONTROL2_1G_RESERVED2_MASK 0x0002 22195 #define RXB_ANARXCONTROL2_1G_RESERVED2_ALIGN 0 22196 #define RXB_ANARXCONTROL2_1G_RESERVED2_BITS 1 22197 #define RXB_ANARXCONTROL2_1G_RESERVED2_SHIFT 1 22198 22199 /* RxB :: anaRxControl2_1G :: errcnt_15 [00:00] */ 22200 #define RXB_ANARXCONTROL2_1G_ERRCNT_15_MASK 0x0001 22201 #define RXB_ANARXCONTROL2_1G_ERRCNT_15_ALIGN 0 22202 #define RXB_ANARXCONTROL2_1G_ERRCNT_15_BITS 1 22203 #define RXB_ANARXCONTROL2_1G_ERRCNT_15_SHIFT 0 22204 22205 22206 /**************************************************************************** 22207 * RxB :: anaRxTest 22208 */ 22209 /* RxB :: anaRxTest :: sigdet_mux_SM [15:12] */ 22210 #define RXB_ANARXTEST_SIGDET_MUX_SM_MASK 0xf000 22211 #define RXB_ANARXTEST_SIGDET_MUX_SM_ALIGN 0 22212 #define RXB_ANARXTEST_SIGDET_MUX_SM_BITS 4 22213 #define RXB_ANARXTEST_SIGDET_MUX_SM_SHIFT 12 22214 22215 /* RxB :: anaRxTest :: reserved0 [11:09] */ 22216 #define RXB_ANARXTEST_RESERVED0_MASK 0x0e00 22217 #define RXB_ANARXTEST_RESERVED0_ALIGN 0 22218 #define RXB_ANARXTEST_RESERVED0_BITS 3 22219 #define RXB_ANARXTEST_RESERVED0_SHIFT 9 22220 22221 /* RxB :: anaRxTest :: tpctrl_SM [08:04] */ 22222 #define RXB_ANARXTEST_TPCTRL_SM_MASK 0x01f0 22223 #define RXB_ANARXTEST_TPCTRL_SM_ALIGN 0 22224 #define RXB_ANARXTEST_TPCTRL_SM_BITS 5 22225 #define RXB_ANARXTEST_TPCTRL_SM_SHIFT 4 22226 22227 /* RxB :: anaRxTest :: testMuxSelect_SM [03:00] */ 22228 #define RXB_ANARXTEST_TESTMUXSELECT_SM_MASK 0x000f 22229 #define RXB_ANARXTEST_TESTMUXSELECT_SM_ALIGN 0 22230 #define RXB_ANARXTEST_TESTMUXSELECT_SM_BITS 4 22231 #define RXB_ANARXTEST_TESTMUXSELECT_SM_SHIFT 0 22232 22233 22234 /**************************************************************************** 22235 * RxB :: anaRxControl1G 22236 */ 22237 /* RxB :: anaRxControl1G :: fpat_md [15:15] */ 22238 #define RXB_ANARXCONTROL1G_FPAT_MD_MASK 0x8000 22239 #define RXB_ANARXCONTROL1G_FPAT_MD_ALIGN 0 22240 #define RXB_ANARXCONTROL1G_FPAT_MD_BITS 1 22241 #define RXB_ANARXCONTROL1G_FPAT_MD_SHIFT 15 22242 22243 /* RxB :: anaRxControl1G :: pkt_count_en [14:14] */ 22244 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_MASK 0x4000 22245 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN 0 22246 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_BITS 1 22247 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT 14 22248 22249 /* RxB :: anaRxControl1G :: staMuxRegDis [13:13] */ 22250 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_MASK 0x2000 22251 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_ALIGN 0 22252 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_BITS 1 22253 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_SHIFT 13 22254 22255 /* RxB :: anaRxControl1G :: prbs_clr_dis [12:12] */ 22256 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_MASK 0x1000 22257 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN 0 22258 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_BITS 1 22259 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT 12 22260 22261 /* RxB :: anaRxControl1G :: rxd_dec_sel [11:11] */ 22262 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_MASK 0x0800 22263 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN 0 22264 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_BITS 1 22265 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT 11 22266 22267 /* RxB :: anaRxControl1G :: cgbad_tst [10:10] */ 22268 #define RXB_ANARXCONTROL1G_CGBAD_TST_MASK 0x0400 22269 #define RXB_ANARXCONTROL1G_CGBAD_TST_ALIGN 0 22270 #define RXB_ANARXCONTROL1G_CGBAD_TST_BITS 1 22271 #define RXB_ANARXCONTROL1G_CGBAD_TST_SHIFT 10 22272 22273 /* RxB :: anaRxControl1G :: Emon_en [09:09] */ 22274 #define RXB_ANARXCONTROL1G_EMON_EN_MASK 0x0200 22275 #define RXB_ANARXCONTROL1G_EMON_EN_ALIGN 0 22276 #define RXB_ANARXCONTROL1G_EMON_EN_BITS 1 22277 #define RXB_ANARXCONTROL1G_EMON_EN_SHIFT 9 22278 22279 /* RxB :: anaRxControl1G :: prbs_en [08:08] */ 22280 #define RXB_ANARXCONTROL1G_PRBS_EN_MASK 0x0100 22281 #define RXB_ANARXCONTROL1G_PRBS_EN_ALIGN 0 22282 #define RXB_ANARXCONTROL1G_PRBS_EN_BITS 1 22283 #define RXB_ANARXCONTROL1G_PRBS_EN_SHIFT 8 22284 22285 /* RxB :: anaRxControl1G :: cgbad_en [07:07] */ 22286 #define RXB_ANARXCONTROL1G_CGBAD_EN_MASK 0x0080 22287 #define RXB_ANARXCONTROL1G_CGBAD_EN_ALIGN 0 22288 #define RXB_ANARXCONTROL1G_CGBAD_EN_BITS 1 22289 #define RXB_ANARXCONTROL1G_CGBAD_EN_SHIFT 7 22290 22291 /* RxB :: anaRxControl1G :: cstretch [06:06] */ 22292 #define RXB_ANARXCONTROL1G_CSTRETCH_MASK 0x0040 22293 #define RXB_ANARXCONTROL1G_CSTRETCH_ALIGN 0 22294 #define RXB_ANARXCONTROL1G_CSTRETCH_BITS 1 22295 #define RXB_ANARXCONTROL1G_CSTRETCH_SHIFT 6 22296 22297 /* RxB :: anaRxControl1G :: comma_low_byte_SM [05:05] */ 22298 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK 0x0020 22299 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN 0 22300 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS 1 22301 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT 5 22302 22303 /* RxB :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */ 22304 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 22305 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 22306 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS 1 22307 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 22308 22309 /* RxB :: anaRxControl1G :: reserved0 [03:02] */ 22310 #define RXB_ANARXCONTROL1G_RESERVED0_MASK 0x000c 22311 #define RXB_ANARXCONTROL1G_RESERVED0_ALIGN 0 22312 #define RXB_ANARXCONTROL1G_RESERVED0_BITS 2 22313 #define RXB_ANARXCONTROL1G_RESERVED0_SHIFT 2 22314 22315 /* RxB :: anaRxControl1G :: freq_sel_force [01:01] */ 22316 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK 0x0002 22317 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN 0 22318 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS 1 22319 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT 1 22320 22321 /* RxB :: anaRxControl1G :: freq_sel [00:00] */ 22322 #define RXB_ANARXCONTROL1G_FREQ_SEL_MASK 0x0001 22323 #define RXB_ANARXCONTROL1G_FREQ_SEL_ALIGN 0 22324 #define RXB_ANARXCONTROL1G_FREQ_SEL_BITS 1 22325 #define RXB_ANARXCONTROL1G_FREQ_SEL_SHIFT 0 22326 22327 22328 /**************************************************************************** 22329 * RxB :: anaRxControlPci 22330 */ 22331 /* RxB :: anaRxControlPci :: comma_adj_sync_sel [15:15] */ 22332 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK 0x8000 22333 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN 0 22334 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS 1 22335 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT 15 22336 22337 /* RxB :: anaRxControlPci :: comma_mask_force_r [14:14] */ 22338 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK 0x4000 22339 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN 0 22340 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS 1 22341 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT 14 22342 22343 /* RxB :: anaRxControlPci :: comma_mask_r [13:13] */ 22344 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_MASK 0x2000 22345 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN 0 22346 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_BITS 1 22347 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT 13 22348 22349 /* RxB :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */ 22350 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000 22351 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0 22352 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1 22353 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12 22354 22355 /* RxB :: anaRxControlPci :: sync_status_force_r_SM [11:11] */ 22356 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK 0x0800 22357 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0 22358 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS 1 22359 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11 22360 22361 /* RxB :: anaRxControlPci :: sync_status_force_r [10:10] */ 22362 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK 0x0400 22363 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN 0 22364 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS 1 22365 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT 10 22366 22367 /* RxB :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */ 22368 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200 22369 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0 22370 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1 22371 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9 22372 22373 /* RxB :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */ 22374 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100 22375 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0 22376 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1 22377 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8 22378 22379 /* RxB :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */ 22380 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080 22381 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0 22382 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1 22383 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7 22384 22385 /* RxB :: anaRxControlPci :: comma_adj_en_r [06:06] */ 22386 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK 0x0040 22387 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN 0 22388 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS 1 22389 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT 6 22390 22391 /* RxB :: anaRxControlPci :: link_en_force_SM [05:05] */ 22392 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK 0x0020 22393 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN 0 22394 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS 1 22395 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT 5 22396 22397 /* RxB :: anaRxControlPci :: link_en_r [04:04] */ 22398 #define RXB_ANARXCONTROLPCI_LINK_EN_R_MASK 0x0010 22399 #define RXB_ANARXCONTROLPCI_LINK_EN_R_ALIGN 0 22400 #define RXB_ANARXCONTROLPCI_LINK_EN_R_BITS 1 22401 #define RXB_ANARXCONTROLPCI_LINK_EN_R_SHIFT 4 22402 22403 /* RxB :: anaRxControlPci :: rx_polarity_force_SM [03:03] */ 22404 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK 0x0008 22405 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN 0 22406 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS 1 22407 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT 3 22408 22409 /* RxB :: anaRxControlPci :: rx_polarity_r [02:02] */ 22410 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_MASK 0x0004 22411 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN 0 22412 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_BITS 1 22413 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT 2 22414 22415 /* RxB :: anaRxControlPci :: integ_mode_SM [01:00] */ 22416 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_MASK 0x0003 22417 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN 0 22418 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_BITS 2 22419 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT 0 22420 22421 22422 /**************************************************************************** 22423 * RxB :: anaRxAstatus 22424 */ 22425 /* RxB :: anaRxAstatus :: sigdet [15:15] */ 22426 #define RXB_ANARXASTATUS_SIGDET_MASK 0x8000 22427 #define RXB_ANARXASTATUS_SIGDET_ALIGN 0 22428 #define RXB_ANARXASTATUS_SIGDET_BITS 1 22429 #define RXB_ANARXASTATUS_SIGDET_SHIFT 15 22430 22431 /* RxB :: anaRxAstatus :: rx_pf [14:11] */ 22432 #define RXB_ANARXASTATUS_RX_PF_MASK 0x7800 22433 #define RXB_ANARXASTATUS_RX_PF_ALIGN 0 22434 #define RXB_ANARXASTATUS_RX_PF_BITS 4 22435 #define RXB_ANARXASTATUS_RX_PF_SHIFT 11 22436 22437 /* RxB :: anaRxAstatus :: tap1_dfe_gray [10:05] */ 22438 #define RXB_ANARXASTATUS_TAP1_DFE_GRAY_MASK 0x07e0 22439 #define RXB_ANARXASTATUS_TAP1_DFE_GRAY_ALIGN 0 22440 #define RXB_ANARXASTATUS_TAP1_DFE_GRAY_BITS 6 22441 #define RXB_ANARXASTATUS_TAP1_DFE_GRAY_SHIFT 5 22442 22443 /* RxB :: anaRxAstatus :: vga [04:00] */ 22444 #define RXB_ANARXASTATUS_VGA_MASK 0x001f 22445 #define RXB_ANARXASTATUS_VGA_ALIGN 0 22446 #define RXB_ANARXASTATUS_VGA_BITS 5 22447 #define RXB_ANARXASTATUS_VGA_SHIFT 0 22448 22449 22450 /**************************************************************************** 22451 * RxB :: anaRxAControl1 22452 */ 22453 /* RxB :: anaRxAControl1 :: imode_vcm [15:15] */ 22454 #define RXB_ANARXACONTROL1_IMODE_VCM_MASK 0x8000 22455 #define RXB_ANARXACONTROL1_IMODE_VCM_ALIGN 0 22456 #define RXB_ANARXACONTROL1_IMODE_VCM_BITS 1 22457 #define RXB_ANARXACONTROL1_IMODE_VCM_SHIFT 15 22458 22459 /* RxB :: anaRxAControl1 :: imin_vcm [14:14] */ 22460 #define RXB_ANARXACONTROL1_IMIN_VCM_MASK 0x4000 22461 #define RXB_ANARXACONTROL1_IMIN_VCM_ALIGN 0 22462 #define RXB_ANARXACONTROL1_IMIN_VCM_BITS 1 22463 #define RXB_ANARXACONTROL1_IMIN_VCM_SHIFT 14 22464 22465 /* RxB :: anaRxAControl1 :: imax_sigdet [13:13] */ 22466 #define RXB_ANARXACONTROL1_IMAX_SIGDET_MASK 0x2000 22467 #define RXB_ANARXACONTROL1_IMAX_SIGDET_ALIGN 0 22468 #define RXB_ANARXACONTROL1_IMAX_SIGDET_BITS 1 22469 #define RXB_ANARXACONTROL1_IMAX_SIGDET_SHIFT 13 22470 22471 /* RxB :: anaRxAControl1 :: imode_sigdet [12:12] */ 22472 #define RXB_ANARXACONTROL1_IMODE_SIGDET_MASK 0x1000 22473 #define RXB_ANARXACONTROL1_IMODE_SIGDET_ALIGN 0 22474 #define RXB_ANARXACONTROL1_IMODE_SIGDET_BITS 1 22475 #define RXB_ANARXACONTROL1_IMODE_SIGDET_SHIFT 12 22476 22477 /* RxB :: anaRxAControl1 :: imin_sigdet [11:11] */ 22478 #define RXB_ANARXACONTROL1_IMIN_SIGDET_MASK 0x0800 22479 #define RXB_ANARXACONTROL1_IMIN_SIGDET_ALIGN 0 22480 #define RXB_ANARXACONTROL1_IMIN_SIGDET_BITS 1 22481 #define RXB_ANARXACONTROL1_IMIN_SIGDET_SHIFT 11 22482 22483 /* RxB :: anaRxAControl1 :: refh_rx [10:10] */ 22484 #define RXB_ANARXACONTROL1_REFH_RX_MASK 0x0400 22485 #define RXB_ANARXACONTROL1_REFH_RX_ALIGN 0 22486 #define RXB_ANARXACONTROL1_REFH_RX_BITS 1 22487 #define RXB_ANARXACONTROL1_REFH_RX_SHIFT 10 22488 22489 /* RxB :: anaRxAControl1 :: refl_rx [09:09] */ 22490 #define RXB_ANARXACONTROL1_REFL_RX_MASK 0x0200 22491 #define RXB_ANARXACONTROL1_REFL_RX_ALIGN 0 22492 #define RXB_ANARXACONTROL1_REFL_RX_BITS 1 22493 #define RXB_ANARXACONTROL1_REFL_RX_SHIFT 9 22494 22495 /* RxB :: anaRxAControl1 :: tport_en [08:08] */ 22496 #define RXB_ANARXACONTROL1_TPORT_EN_MASK 0x0100 22497 #define RXB_ANARXACONTROL1_TPORT_EN_ALIGN 0 22498 #define RXB_ANARXACONTROL1_TPORT_EN_BITS 1 22499 #define RXB_ANARXACONTROL1_TPORT_EN_SHIFT 8 22500 22501 /* RxB :: anaRxAControl1 :: vddrb_bgb [07:07] */ 22502 #define RXB_ANARXACONTROL1_VDDRB_BGB_MASK 0x0080 22503 #define RXB_ANARXACONTROL1_VDDRB_BGB_ALIGN 0 22504 #define RXB_ANARXACONTROL1_VDDRB_BGB_BITS 1 22505 #define RXB_ANARXACONTROL1_VDDRB_BGB_SHIFT 7 22506 22507 /* RxB :: anaRxAControl1 :: sig_pwrdn [06:06] */ 22508 #define RXB_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 22509 #define RXB_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 22510 #define RXB_ANARXACONTROL1_SIG_PWRDN_BITS 1 22511 #define RXB_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 22512 22513 /* RxB :: anaRxAControl1 :: offset_ctrl [05:03] */ 22514 #define RXB_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 22515 #define RXB_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 22516 #define RXB_ANARXACONTROL1_OFFSET_CTRL_BITS 3 22517 #define RXB_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 22518 22519 /* RxB :: anaRxAControl1 :: offset_sel [02:02] */ 22520 #define RXB_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 22521 #define RXB_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 22522 #define RXB_ANARXACONTROL1_OFFSET_SEL_BITS 1 22523 #define RXB_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 22524 22525 /* RxB :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */ 22526 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY1_MASK 0x0002 22527 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN 0 22528 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY1_BITS 1 22529 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT 1 22530 22531 /* RxB :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */ 22532 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY0_MASK 0x0001 22533 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN 0 22534 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY0_BITS 1 22535 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT 0 22536 22537 22538 /**************************************************************************** 22539 * RxB :: anaRxAControl2 22540 */ 22541 /* RxB :: anaRxAControl2 :: imax_ctat [15:15] */ 22542 #define RXB_ANARXACONTROL2_IMAX_CTAT_MASK 0x8000 22543 #define RXB_ANARXACONTROL2_IMAX_CTAT_ALIGN 0 22544 #define RXB_ANARXACONTROL2_IMAX_CTAT_BITS 1 22545 #define RXB_ANARXACONTROL2_IMAX_CTAT_SHIFT 15 22546 22547 /* RxB :: anaRxAControl2 :: imode_ctat [14:14] */ 22548 #define RXB_ANARXACONTROL2_IMODE_CTAT_MASK 0x4000 22549 #define RXB_ANARXACONTROL2_IMODE_CTAT_ALIGN 0 22550 #define RXB_ANARXACONTROL2_IMODE_CTAT_BITS 1 22551 #define RXB_ANARXACONTROL2_IMODE_CTAT_SHIFT 14 22552 22553 /* RxB :: anaRxAControl2 :: imin_ctat [13:13] */ 22554 #define RXB_ANARXACONTROL2_IMIN_CTAT_MASK 0x2000 22555 #define RXB_ANARXACONTROL2_IMIN_CTAT_ALIGN 0 22556 #define RXB_ANARXACONTROL2_IMIN_CTAT_BITS 1 22557 #define RXB_ANARXACONTROL2_IMIN_CTAT_SHIFT 13 22558 22559 /* RxB :: anaRxAControl2 :: imax_eqfl [12:12] */ 22560 #define RXB_ANARXACONTROL2_IMAX_EQFL_MASK 0x1000 22561 #define RXB_ANARXACONTROL2_IMAX_EQFL_ALIGN 0 22562 #define RXB_ANARXACONTROL2_IMAX_EQFL_BITS 1 22563 #define RXB_ANARXACONTROL2_IMAX_EQFL_SHIFT 12 22564 22565 /* RxB :: anaRxAControl2 :: imode_eqfl [11:11] */ 22566 #define RXB_ANARXACONTROL2_IMODE_EQFL_MASK 0x0800 22567 #define RXB_ANARXACONTROL2_IMODE_EQFL_ALIGN 0 22568 #define RXB_ANARXACONTROL2_IMODE_EQFL_BITS 1 22569 #define RXB_ANARXACONTROL2_IMODE_EQFL_SHIFT 11 22570 22571 /* RxB :: anaRxAControl2 :: imin_eqfl [10:10] */ 22572 #define RXB_ANARXACONTROL2_IMIN_EQFL_MASK 0x0400 22573 #define RXB_ANARXACONTROL2_IMIN_EQFL_ALIGN 0 22574 #define RXB_ANARXACONTROL2_IMIN_EQFL_BITS 1 22575 #define RXB_ANARXACONTROL2_IMIN_EQFL_SHIFT 10 22576 22577 /* RxB :: anaRxAControl2 :: imax_dfesum [09:09] */ 22578 #define RXB_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 22579 #define RXB_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 22580 #define RXB_ANARXACONTROL2_IMAX_DFESUM_BITS 1 22581 #define RXB_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 22582 22583 /* RxB :: anaRxAControl2 :: imode_dfesum [08:08] */ 22584 #define RXB_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 22585 #define RXB_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 22586 #define RXB_ANARXACONTROL2_IMODE_DFESUM_BITS 1 22587 #define RXB_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 22588 22589 /* RxB :: anaRxAControl2 :: imin_dfesum [07:07] */ 22590 #define RXB_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 22591 #define RXB_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 22592 #define RXB_ANARXACONTROL2_IMIN_DFESUM_BITS 1 22593 #define RXB_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 22594 22595 /* RxB :: anaRxAControl2 :: imax_vga [06:06] */ 22596 #define RXB_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 22597 #define RXB_ANARXACONTROL2_IMAX_VGA_ALIGN 0 22598 #define RXB_ANARXACONTROL2_IMAX_VGA_BITS 1 22599 #define RXB_ANARXACONTROL2_IMAX_VGA_SHIFT 6 22600 22601 /* RxB :: anaRxAControl2 :: imode_vga [05:05] */ 22602 #define RXB_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 22603 #define RXB_ANARXACONTROL2_IMODE_VGA_ALIGN 0 22604 #define RXB_ANARXACONTROL2_IMODE_VGA_BITS 1 22605 #define RXB_ANARXACONTROL2_IMODE_VGA_SHIFT 5 22606 22607 /* RxB :: anaRxAControl2 :: imin_vga [04:04] */ 22608 #define RXB_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 22609 #define RXB_ANARXACONTROL2_IMIN_VGA_ALIGN 0 22610 #define RXB_ANARXACONTROL2_IMIN_VGA_BITS 1 22611 #define RXB_ANARXACONTROL2_IMIN_VGA_SHIFT 4 22612 22613 /* RxB :: anaRxAControl2 :: imax_interp [03:03] */ 22614 #define RXB_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 22615 #define RXB_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 22616 #define RXB_ANARXACONTROL2_IMAX_INTERP_BITS 1 22617 #define RXB_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 22618 22619 /* RxB :: anaRxAControl2 :: imode_interp [02:02] */ 22620 #define RXB_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 22621 #define RXB_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 22622 #define RXB_ANARXACONTROL2_IMODE_INTERP_BITS 1 22623 #define RXB_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 22624 22625 /* RxB :: anaRxAControl2 :: imin_interp [01:01] */ 22626 #define RXB_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 22627 #define RXB_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 22628 #define RXB_ANARXACONTROL2_IMIN_INTERP_BITS 1 22629 #define RXB_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 22630 22631 /* RxB :: anaRxAControl2 :: imax_vcm [00:00] */ 22632 #define RXB_ANARXACONTROL2_IMAX_VCM_MASK 0x0001 22633 #define RXB_ANARXACONTROL2_IMAX_VCM_ALIGN 0 22634 #define RXB_ANARXACONTROL2_IMAX_VCM_BITS 1 22635 #define RXB_ANARXACONTROL2_IMAX_VCM_SHIFT 0 22636 22637 22638 /**************************************************************************** 22639 * RxB :: anaRxAControl3 22640 */ 22641 /* RxB :: anaRxAControl3 :: en_clk16 [15:15] */ 22642 #define RXB_ANARXACONTROL3_EN_CLK16_MASK 0x8000 22643 #define RXB_ANARXACONTROL3_EN_CLK16_ALIGN 0 22644 #define RXB_ANARXACONTROL3_EN_CLK16_BITS 1 22645 #define RXB_ANARXACONTROL3_EN_CLK16_SHIFT 15 22646 22647 /* RxB :: anaRxAControl3 :: en_clk33 [14:14] */ 22648 #define RXB_ANARXACONTROL3_EN_CLK33_MASK 0x4000 22649 #define RXB_ANARXACONTROL3_EN_CLK33_ALIGN 0 22650 #define RXB_ANARXACONTROL3_EN_CLK33_BITS 1 22651 #define RXB_ANARXACONTROL3_EN_CLK33_SHIFT 14 22652 22653 /* RxB :: anaRxAControl3 :: en_vcctrl [13:13] */ 22654 #define RXB_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 22655 #define RXB_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 22656 #define RXB_ANARXACONTROL3_EN_VCCTRL_BITS 1 22657 #define RXB_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 22658 22659 /* RxB :: anaRxAControl3 :: sel_th4dfe1 [12:12] */ 22660 #define RXB_ANARXACONTROL3_SEL_TH4DFE1_MASK 0x1000 22661 #define RXB_ANARXACONTROL3_SEL_TH4DFE1_ALIGN 0 22662 #define RXB_ANARXACONTROL3_SEL_TH4DFE1_BITS 1 22663 #define RXB_ANARXACONTROL3_SEL_TH4DFE1_SHIFT 12 22664 22665 /* RxB :: anaRxAControl3 :: sel_th4dfe0 [11:11] */ 22666 #define RXB_ANARXACONTROL3_SEL_TH4DFE0_MASK 0x0800 22667 #define RXB_ANARXACONTROL3_SEL_TH4DFE0_ALIGN 0 22668 #define RXB_ANARXACONTROL3_SEL_TH4DFE0_BITS 1 22669 #define RXB_ANARXACONTROL3_SEL_TH4DFE0_SHIFT 11 22670 22671 /* RxB :: anaRxAControl3 :: selugbw1 [10:10] */ 22672 #define RXB_ANARXACONTROL3_SELUGBW1_MASK 0x0400 22673 #define RXB_ANARXACONTROL3_SELUGBW1_ALIGN 0 22674 #define RXB_ANARXACONTROL3_SELUGBW1_BITS 1 22675 #define RXB_ANARXACONTROL3_SELUGBW1_SHIFT 10 22676 22677 /* RxB :: anaRxAControl3 :: selugbw0 [09:09] */ 22678 #define RXB_ANARXACONTROL3_SELUGBW0_MASK 0x0200 22679 #define RXB_ANARXACONTROL3_SELUGBW0_ALIGN 0 22680 #define RXB_ANARXACONTROL3_SELUGBW0_BITS 1 22681 #define RXB_ANARXACONTROL3_SELUGBW0_SHIFT 9 22682 22683 /* RxB :: anaRxAControl3 :: imax_dfetap [08:08] */ 22684 #define RXB_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 22685 #define RXB_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 22686 #define RXB_ANARXACONTROL3_IMAX_DFETAP_BITS 1 22687 #define RXB_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 22688 22689 /* RxB :: anaRxAControl3 :: imode_dfetap [07:07] */ 22690 #define RXB_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 22691 #define RXB_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 22692 #define RXB_ANARXACONTROL3_IMODE_DFETAP_BITS 1 22693 #define RXB_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 22694 22695 /* RxB :: anaRxAControl3 :: imin_dfetap [06:06] */ 22696 #define RXB_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 22697 #define RXB_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 22698 #define RXB_ANARXACONTROL3_IMIN_DFETAP_BITS 1 22699 #define RXB_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 22700 22701 /* RxB :: anaRxAControl3 :: imax_slcd2c [05:05] */ 22702 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 22703 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 22704 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 22705 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 22706 22707 /* RxB :: anaRxAControl3 :: imode_slcd2c [04:04] */ 22708 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 22709 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 22710 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 22711 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 22712 22713 /* RxB :: anaRxAControl3 :: imin_slcd2c [03:03] */ 22714 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 22715 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 22716 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 22717 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 22718 22719 /* RxB :: anaRxAControl3 :: imax_dfevref [02:02] */ 22720 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 22721 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 22722 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 22723 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 22724 22725 /* RxB :: anaRxAControl3 :: imode_dfevref [01:01] */ 22726 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 22727 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 22728 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 22729 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 22730 22731 /* RxB :: anaRxAControl3 :: imin_dfevref [00:00] */ 22732 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 22733 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 22734 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 22735 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 22736 22737 22738 /**************************************************************************** 22739 * Warpcore_USER_XgxsBlk2 22740 */ 22741 /**************************************************************************** 22742 * XgxsBlk2 :: rxLnSwap 22743 */ 22744 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_en [15:15] */ 22745 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_MASK 0x8000 22746 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_ALIGN 0 22747 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_BITS 1 22748 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_SHIFT 15 22749 22750 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_force_en [14:14] */ 22751 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_MASK 0x4000 22752 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_ALIGN 0 22753 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_BITS 1 22754 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_SHIFT 14 22755 22756 /* XgxsBlk2 :: rxLnSwap :: Qset_prog_en [13:13] */ 22757 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_MASK 0x2000 22758 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_ALIGN 0 22759 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_BITS 1 22760 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_SHIFT 13 22761 22762 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_link_en [12:12] */ 22763 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_MASK 0x1000 22764 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_ALIGN 0 22765 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_BITS 1 22766 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_SHIFT 12 22767 22768 /* XgxsBlk2 :: rxLnSwap :: Q0_msb [11:11] */ 22769 #define XGXSBLK2_RXLNSWAP_Q0_MSB_MASK 0x0800 22770 #define XGXSBLK2_RXLNSWAP_Q0_MSB_ALIGN 0 22771 #define XGXSBLK2_RXLNSWAP_Q0_MSB_BITS 1 22772 #define XGXSBLK2_RXLNSWAP_Q0_MSB_SHIFT 11 22773 22774 /* XgxsBlk2 :: rxLnSwap :: Q1_msb [10:10] */ 22775 #define XGXSBLK2_RXLNSWAP_Q1_MSB_MASK 0x0400 22776 #define XGXSBLK2_RXLNSWAP_Q1_MSB_ALIGN 0 22777 #define XGXSBLK2_RXLNSWAP_Q1_MSB_BITS 1 22778 #define XGXSBLK2_RXLNSWAP_Q1_MSB_SHIFT 10 22779 22780 /* XgxsBlk2 :: rxLnSwap :: Q2_msb [09:09] */ 22781 #define XGXSBLK2_RXLNSWAP_Q2_MSB_MASK 0x0200 22782 #define XGXSBLK2_RXLNSWAP_Q2_MSB_ALIGN 0 22783 #define XGXSBLK2_RXLNSWAP_Q2_MSB_BITS 1 22784 #define XGXSBLK2_RXLNSWAP_Q2_MSB_SHIFT 9 22785 22786 /* XgxsBlk2 :: rxLnSwap :: Q3_msb [08:08] */ 22787 #define XGXSBLK2_RXLNSWAP_Q3_MSB_MASK 0x0100 22788 #define XGXSBLK2_RXLNSWAP_Q3_MSB_ALIGN 0 22789 #define XGXSBLK2_RXLNSWAP_Q3_MSB_BITS 1 22790 #define XGXSBLK2_RXLNSWAP_Q3_MSB_SHIFT 8 22791 22792 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force0 [07:06] */ 22793 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_MASK 0x00c0 22794 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_ALIGN 0 22795 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_BITS 2 22796 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_SHIFT 6 22797 22798 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force1 [05:04] */ 22799 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_MASK 0x0030 22800 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_ALIGN 0 22801 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_BITS 2 22802 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_SHIFT 4 22803 22804 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force2 [03:02] */ 22805 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_MASK 0x000c 22806 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_ALIGN 0 22807 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_BITS 2 22808 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_SHIFT 2 22809 22810 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force3 [01:00] */ 22811 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_MASK 0x0003 22812 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_ALIGN 0 22813 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_BITS 2 22814 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_SHIFT 0 22815 22816 22817 /**************************************************************************** 22818 * XgxsBlk2 :: txLnSwap 22819 */ 22820 /* XgxsBlk2 :: txLnSwap :: tx_lnswap_en [15:15] */ 22821 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_MASK 0x8000 22822 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_ALIGN 0 22823 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_BITS 1 22824 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_SHIFT 15 22825 22826 /* XgxsBlk2 :: txLnSwap :: reserved0 [14:08] */ 22827 #define XGXSBLK2_TXLNSWAP_RESERVED0_MASK 0x7f00 22828 #define XGXSBLK2_TXLNSWAP_RESERVED0_ALIGN 0 22829 #define XGXSBLK2_TXLNSWAP_RESERVED0_BITS 7 22830 #define XGXSBLK2_TXLNSWAP_RESERVED0_SHIFT 8 22831 22832 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force0 [07:06] */ 22833 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_MASK 0x00c0 22834 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_ALIGN 0 22835 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_BITS 2 22836 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_SHIFT 6 22837 22838 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force1 [05:04] */ 22839 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_MASK 0x0030 22840 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_ALIGN 0 22841 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_BITS 2 22842 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_SHIFT 4 22843 22844 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force2 [03:02] */ 22845 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_MASK 0x000c 22846 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_ALIGN 0 22847 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_BITS 2 22848 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_SHIFT 2 22849 22850 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force3 [01:00] */ 22851 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_MASK 0x0003 22852 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_ALIGN 0 22853 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_BITS 2 22854 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_SHIFT 0 22855 22856 22857 /**************************************************************************** 22858 * XgxsBlk2 :: QsetLns01 22859 */ 22860 /* XgxsBlk2 :: QsetLns01 :: Q1 [15:08] */ 22861 #define XGXSBLK2_QSETLNS01_Q1_MASK 0xff00 22862 #define XGXSBLK2_QSETLNS01_Q1_ALIGN 0 22863 #define XGXSBLK2_QSETLNS01_Q1_BITS 8 22864 #define XGXSBLK2_QSETLNS01_Q1_SHIFT 8 22865 22866 /* XgxsBlk2 :: QsetLns01 :: Q0 [07:00] */ 22867 #define XGXSBLK2_QSETLNS01_Q0_MASK 0x00ff 22868 #define XGXSBLK2_QSETLNS01_Q0_ALIGN 0 22869 #define XGXSBLK2_QSETLNS01_Q0_BITS 8 22870 #define XGXSBLK2_QSETLNS01_Q0_SHIFT 0 22871 22872 22873 /**************************************************************************** 22874 * XgxsBlk2 :: QsetLns23 22875 */ 22876 /* XgxsBlk2 :: QsetLns23 :: Q3 [15:08] */ 22877 #define XGXSBLK2_QSETLNS23_Q3_MASK 0xff00 22878 #define XGXSBLK2_QSETLNS23_Q3_ALIGN 0 22879 #define XGXSBLK2_QSETLNS23_Q3_BITS 8 22880 #define XGXSBLK2_QSETLNS23_Q3_SHIFT 8 22881 22882 /* XgxsBlk2 :: QsetLns23 :: Q2 [07:00] */ 22883 #define XGXSBLK2_QSETLNS23_Q2_MASK 0x00ff 22884 #define XGXSBLK2_QSETLNS23_Q2_ALIGN 0 22885 #define XGXSBLK2_QSETLNS23_Q2_BITS 8 22886 #define XGXSBLK2_QSETLNS23_Q2_SHIFT 0 22887 22888 22889 /**************************************************************************** 22890 * XgxsBlk2 :: unicoreMode10g 22891 */ 22892 /* XgxsBlk2 :: unicoreMode10g :: reserved0 [15:08] */ 22893 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_MASK 0xff00 22894 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_ALIGN 0 22895 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_BITS 8 22896 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_SHIFT 8 22897 22898 /* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gHiG [07:04] */ 22899 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_MASK 0x00f0 22900 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_ALIGN 0 22901 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_BITS 4 22902 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT 4 22903 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS 0 22904 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXG_nCC 1 22905 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_IndLane_OS8 4 22906 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_IndLane_OS5 5 22907 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PCI 7 22908 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQ 8 22909 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQnCC 9 22910 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PBypass 10 22911 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PBypass_nDSK 11 22912 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_ComboCoreMode 12 22913 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_Clocks_off 15 22914 22915 /* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gCx4 [03:00] */ 22916 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_MASK 0x000f 22917 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_ALIGN 0 22918 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_BITS 4 22919 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT 0 22920 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS 0 22921 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXG_nCC 1 22922 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_IndLane_OS8 4 22923 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_IndLane_OS5 5 22924 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PCI 7 22925 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS_nLQ 8 22926 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS_nLQnCC 9 22927 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PBypass 10 22928 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PBypass_nDSK 11 22929 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_ComboCoreMode 12 22930 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_Clocks_off 15 22931 22932 22933 /**************************************************************************** 22934 * XgxsBlk2 :: indCombCtrl 22935 */ 22936 /* XgxsBlk2 :: indCombCtrl :: reserved0 [15:02] */ 22937 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_MASK 0xfffc 22938 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_ALIGN 0 22939 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_BITS 14 22940 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_SHIFT 2 22941 22942 /* XgxsBlk2 :: indCombCtrl :: masterLn_indx [01:00] */ 22943 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_MASK 0x0003 22944 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_ALIGN 0 22945 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_BITS 2 22946 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_SHIFT 0 22947 22948 22949 /**************************************************************************** 22950 * XgxsBlk2 :: TestModeLane 22951 */ 22952 /* XgxsBlk2 :: TestModeLane :: eee_fast_timer_en [15:15] */ 22953 #define XGXSBLK2_TESTMODELANE_EEE_FAST_TIMER_EN_MASK 0x8000 22954 #define XGXSBLK2_TESTMODELANE_EEE_FAST_TIMER_EN_ALIGN 0 22955 #define XGXSBLK2_TESTMODELANE_EEE_FAST_TIMER_EN_BITS 1 22956 #define XGXSBLK2_TESTMODELANE_EEE_FAST_TIMER_EN_SHIFT 15 22957 22958 /* XgxsBlk2 :: TestModeLane :: eee_gateclk_en [14:14] */ 22959 #define XGXSBLK2_TESTMODELANE_EEE_GATECLK_EN_MASK 0x4000 22960 #define XGXSBLK2_TESTMODELANE_EEE_GATECLK_EN_ALIGN 0 22961 #define XGXSBLK2_TESTMODELANE_EEE_GATECLK_EN_BITS 1 22962 #define XGXSBLK2_TESTMODELANE_EEE_GATECLK_EN_SHIFT 14 22963 22964 /* XgxsBlk2 :: TestModeLane :: eee_gateoutclk_en [13:13] */ 22965 #define XGXSBLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_MASK 0x2000 22966 #define XGXSBLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_ALIGN 0 22967 #define XGXSBLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_BITS 1 22968 #define XGXSBLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_SHIFT 13 22969 22970 /* XgxsBlk2 :: TestModeLane :: tx_lowpwr_6g_over_val [12:12] */ 22971 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_VAL_MASK 0x1000 22972 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_VAL_ALIGN 0 22973 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_VAL_BITS 1 22974 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_VAL_SHIFT 12 22975 22976 /* XgxsBlk2 :: TestModeLane :: tx_lowpwr_6g_over [11:11] */ 22977 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_MASK 0x0800 22978 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_ALIGN 0 22979 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_BITS 1 22980 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_SHIFT 11 22981 22982 /* XgxsBlk2 :: TestModeLane :: reserved0 [10:02] */ 22983 #define XGXSBLK2_TESTMODELANE_RESERVED0_MASK 0x07fc 22984 #define XGXSBLK2_TESTMODELANE_RESERVED0_ALIGN 0 22985 #define XGXSBLK2_TESTMODELANE_RESERVED0_BITS 9 22986 #define XGXSBLK2_TESTMODELANE_RESERVED0_SHIFT 2 22987 22988 /* XgxsBlk2 :: TestModeLane :: slice_selector [01:00] */ 22989 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_MASK 0x0003 22990 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_ALIGN 0 22991 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_BITS 2 22992 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_SHIFT 0 22993 22994 22995 /**************************************************************************** 22996 * XgxsBlk2 :: TestModeCombo 22997 */ 22998 /* XgxsBlk2 :: TestModeCombo :: reserved0 [15:12] */ 22999 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_MASK 0xf000 23000 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_ALIGN 0 23001 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_BITS 4 23002 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_SHIFT 12 23003 23004 /* XgxsBlk2 :: TestModeCombo :: test_monitor_mode2 [11:06] */ 23005 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_MASK 0x0fc0 23006 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_ALIGN 0 23007 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_BITS 6 23008 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_SHIFT 6 23009 23010 /* XgxsBlk2 :: TestModeCombo :: test_monitor_mode1 [05:00] */ 23011 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_MASK 0x003f 23012 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_ALIGN 0 23013 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_BITS 6 23014 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_SHIFT 0 23015 23016 23017 /**************************************************************************** 23018 * XgxsBlk2 :: TestModeMux 23019 */ 23020 /* XgxsBlk2 :: TestModeMux :: to_dig_mux_ovr3 [15:14] */ 23021 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR3_MASK 0xc000 23022 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR3_ALIGN 0 23023 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR3_BITS 2 23024 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR3_SHIFT 14 23025 23026 /* XgxsBlk2 :: TestModeMux :: to_dig_mux_ovr2 [13:12] */ 23027 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR2_MASK 0x3000 23028 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR2_ALIGN 0 23029 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR2_BITS 2 23030 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR2_SHIFT 12 23031 23032 /* XgxsBlk2 :: TestModeMux :: to_dig_mux_ovr1 [11:10] */ 23033 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR1_MASK 0x0c00 23034 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR1_ALIGN 0 23035 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR1_BITS 2 23036 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR1_SHIFT 10 23037 23038 /* XgxsBlk2 :: TestModeMux :: to_dig_mux_ovr0 [09:08] */ 23039 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR0_MASK 0x0300 23040 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR0_ALIGN 0 23041 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR0_BITS 2 23042 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR0_SHIFT 8 23043 23044 /* XgxsBlk2 :: TestModeMux :: to_dig_mux_ovr_en [07:07] */ 23045 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR_EN_MASK 0x0080 23046 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR_EN_ALIGN 0 23047 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR_EN_BITS 1 23048 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR_EN_SHIFT 7 23049 23050 /* XgxsBlk2 :: TestModeMux :: reserved0 [06:04] */ 23051 #define XGXSBLK2_TESTMODEMUX_RESERVED0_MASK 0x0070 23052 #define XGXSBLK2_TESTMODEMUX_RESERVED0_ALIGN 0 23053 #define XGXSBLK2_TESTMODEMUX_RESERVED0_BITS 3 23054 #define XGXSBLK2_TESTMODEMUX_RESERVED0_SHIFT 4 23055 23056 /* XgxsBlk2 :: TestModeMux :: tmux_sel [03:01] */ 23057 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_MASK 0x000e 23058 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_ALIGN 0 23059 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_BITS 3 23060 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_SHIFT 1 23061 23062 /* XgxsBlk2 :: TestModeMux :: tmux_en [00:00] */ 23063 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_MASK 0x0001 23064 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_ALIGN 0 23065 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_BITS 1 23066 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_SHIFT 0 23067 23068 23069 /**************************************************************************** 23070 * XgxsBlk2 :: cx4SigdetCnt 23071 */ 23072 /* XgxsBlk2 :: cx4SigdetCnt :: cx4SigdetCnt [15:00] */ 23073 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_MASK 0xffff 23074 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_ALIGN 0 23075 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_BITS 16 23076 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_SHIFT 0 23077 23078 23079 /**************************************************************************** 23080 * XgxsBlk2 :: laneReset 23081 */ 23082 /* XgxsBlk2 :: laneReset :: reset_mdio [15:15] */ 23083 #define XGXSBLK2_LANERESET_RESET_MDIO_MASK 0x8000 23084 #define XGXSBLK2_LANERESET_RESET_MDIO_ALIGN 0 23085 #define XGXSBLK2_LANERESET_RESET_MDIO_BITS 1 23086 #define XGXSBLK2_LANERESET_RESET_MDIO_SHIFT 15 23087 23088 /* XgxsBlk2 :: laneReset :: reserved0 [14:09] */ 23089 #define XGXSBLK2_LANERESET_RESERVED0_MASK 0x7e00 23090 #define XGXSBLK2_LANERESET_RESERVED0_ALIGN 0 23091 #define XGXSBLK2_LANERESET_RESERVED0_BITS 6 23092 #define XGXSBLK2_LANERESET_RESERVED0_SHIFT 9 23093 23094 /* XgxsBlk2 :: laneReset :: reset_pll [08:08] */ 23095 #define XGXSBLK2_LANERESET_RESET_PLL_MASK 0x0100 23096 #define XGXSBLK2_LANERESET_RESET_PLL_ALIGN 0 23097 #define XGXSBLK2_LANERESET_RESET_PLL_BITS 1 23098 #define XGXSBLK2_LANERESET_RESET_PLL_SHIFT 8 23099 23100 /* XgxsBlk2 :: laneReset :: reset_tx [07:04] */ 23101 #define XGXSBLK2_LANERESET_RESET_TX_MASK 0x00f0 23102 #define XGXSBLK2_LANERESET_RESET_TX_ALIGN 0 23103 #define XGXSBLK2_LANERESET_RESET_TX_BITS 4 23104 #define XGXSBLK2_LANERESET_RESET_TX_SHIFT 4 23105 23106 /* XgxsBlk2 :: laneReset :: reset_rx [03:00] */ 23107 #define XGXSBLK2_LANERESET_RESET_RX_MASK 0x000f 23108 #define XGXSBLK2_LANERESET_RESET_RX_ALIGN 0 23109 #define XGXSBLK2_LANERESET_RESET_RX_BITS 4 23110 #define XGXSBLK2_LANERESET_RESET_RX_SHIFT 0 23111 23112 23113 /**************************************************************************** 23114 * XgxsBlk2 :: xgxsStatus6 23115 */ 23116 /* XgxsBlk2 :: xgxsStatus6 :: reserved0 [15:15] */ 23117 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_MASK 0x8000 23118 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_ALIGN 0 23119 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_BITS 1 23120 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_SHIFT 15 23121 23122 /* XgxsBlk2 :: xgxsStatus6 :: hcd_over_1g [14:00] */ 23123 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_MASK 0x7fff 23124 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_ALIGN 0 23125 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_BITS 15 23126 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_SHIFT 0 23127 23128 23129 /**************************************************************************** 23130 * XgxsBlk2 :: XFIcontrol 23131 */ 23132 /* XgxsBlk2 :: XFIcontrol :: reserved0 [15:06] */ 23133 #define XGXSBLK2_XFICONTROL_RESERVED0_MASK 0xffc0 23134 #define XGXSBLK2_XFICONTROL_RESERVED0_ALIGN 0 23135 #define XGXSBLK2_XFICONTROL_RESERVED0_BITS 10 23136 #define XGXSBLK2_XFICONTROL_RESERVED0_SHIFT 6 23137 23138 /* XgxsBlk2 :: XFIcontrol :: fc_mode_disable [05:05] */ 23139 #define XGXSBLK2_XFICONTROL_FC_MODE_DISABLE_MASK 0x0020 23140 #define XGXSBLK2_XFICONTROL_FC_MODE_DISABLE_ALIGN 0 23141 #define XGXSBLK2_XFICONTROL_FC_MODE_DISABLE_BITS 1 23142 #define XGXSBLK2_XFICONTROL_FC_MODE_DISABLE_SHIFT 5 23143 23144 /* XgxsBlk2 :: XFIcontrol :: xfipcs_pwrdown [04:04] */ 23145 #define XGXSBLK2_XFICONTROL_XFIPCS_PWRDOWN_MASK 0x0010 23146 #define XGXSBLK2_XFICONTROL_XFIPCS_PWRDOWN_ALIGN 0 23147 #define XGXSBLK2_XFICONTROL_XFIPCS_PWRDOWN_BITS 1 23148 #define XGXSBLK2_XFICONTROL_XFIPCS_PWRDOWN_SHIFT 4 23149 23150 /* XgxsBlk2 :: XFIcontrol :: xfi_rx_bypass_val [03:03] */ 23151 #define XGXSBLK2_XFICONTROL_XFI_RX_BYPASS_VAL_MASK 0x0008 23152 #define XGXSBLK2_XFICONTROL_XFI_RX_BYPASS_VAL_ALIGN 0 23153 #define XGXSBLK2_XFICONTROL_XFI_RX_BYPASS_VAL_BITS 1 23154 #define XGXSBLK2_XFICONTROL_XFI_RX_BYPASS_VAL_SHIFT 3 23155 23156 /* XgxsBlk2 :: XFIcontrol :: xfi_rx_bypass_force [02:02] */ 23157 #define XGXSBLK2_XFICONTROL_XFI_RX_BYPASS_FORCE_MASK 0x0004 23158 #define XGXSBLK2_XFICONTROL_XFI_RX_BYPASS_FORCE_ALIGN 0 23159 #define XGXSBLK2_XFICONTROL_XFI_RX_BYPASS_FORCE_BITS 1 23160 #define XGXSBLK2_XFICONTROL_XFI_RX_BYPASS_FORCE_SHIFT 2 23161 23162 /* XgxsBlk2 :: XFIcontrol :: xfi_tx_bypass_val [01:01] */ 23163 #define XGXSBLK2_XFICONTROL_XFI_TX_BYPASS_VAL_MASK 0x0002 23164 #define XGXSBLK2_XFICONTROL_XFI_TX_BYPASS_VAL_ALIGN 0 23165 #define XGXSBLK2_XFICONTROL_XFI_TX_BYPASS_VAL_BITS 1 23166 #define XGXSBLK2_XFICONTROL_XFI_TX_BYPASS_VAL_SHIFT 1 23167 23168 /* XgxsBlk2 :: XFIcontrol :: xfi_tx_bypass_force [00:00] */ 23169 #define XGXSBLK2_XFICONTROL_XFI_TX_BYPASS_FORCE_MASK 0x0001 23170 #define XGXSBLK2_XFICONTROL_XFI_TX_BYPASS_FORCE_ALIGN 0 23171 #define XGXSBLK2_XFICONTROL_XFI_TX_BYPASS_FORCE_BITS 1 23172 #define XGXSBLK2_XFICONTROL_XFI_TX_BYPASS_FORCE_SHIFT 0 23173 23174 23175 /**************************************************************************** 23176 * XgxsBlk2 :: Aswap66Control1 23177 */ 23178 /* XgxsBlk2 :: Aswap66Control1 :: swap_count64B66B [15:00] */ 23179 #define XGXSBLK2_ASWAP66CONTROL1_SWAP_COUNT64B66B_MASK 0xffff 23180 #define XGXSBLK2_ASWAP66CONTROL1_SWAP_COUNT64B66B_ALIGN 0 23181 #define XGXSBLK2_ASWAP66CONTROL1_SWAP_COUNT64B66B_BITS 16 23182 #define XGXSBLK2_ASWAP66CONTROL1_SWAP_COUNT64B66B_SHIFT 0 23183 23184 23185 /**************************************************************************** 23186 * XgxsBlk2 :: Aswap66Control2 23187 */ 23188 /* XgxsBlk2 :: Aswap66Control2 :: reserved0 [15:12] */ 23189 #define XGXSBLK2_ASWAP66CONTROL2_RESERVED0_MASK 0xf000 23190 #define XGXSBLK2_ASWAP66CONTROL2_RESERVED0_ALIGN 0 23191 #define XGXSBLK2_ASWAP66CONTROL2_RESERVED0_BITS 4 23192 #define XGXSBLK2_ASWAP66CONTROL2_RESERVED0_SHIFT 12 23193 23194 /* XgxsBlk2 :: Aswap66Control2 :: prst_by_bypass_en [11:11] */ 23195 #define XGXSBLK2_ASWAP66CONTROL2_PRST_BY_BYPASS_EN_MASK 0x0800 23196 #define XGXSBLK2_ASWAP66CONTROL2_PRST_BY_BYPASS_EN_ALIGN 0 23197 #define XGXSBLK2_ASWAP66CONTROL2_PRST_BY_BYPASS_EN_BITS 1 23198 #define XGXSBLK2_ASWAP66CONTROL2_PRST_BY_BYPASS_EN_SHIFT 11 23199 23200 /* XgxsBlk2 :: Aswap66Control2 :: rx10_fifo_bypass_override_en [10:10] */ 23201 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_EN_MASK 0x0400 23202 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_EN_ALIGN 0 23203 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_EN_BITS 1 23204 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_EN_SHIFT 10 23205 23206 /* XgxsBlk2 :: Aswap66Control2 :: rx10_fifo_bypass_override_val [09:09] */ 23207 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_VAL_MASK 0x0200 23208 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_VAL_ALIGN 0 23209 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_VAL_BITS 1 23210 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_VAL_SHIFT 9 23211 23212 /* XgxsBlk2 :: Aswap66Control2 :: swap_count_sel_override_en [08:08] */ 23213 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_EN_MASK 0x0100 23214 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_EN_ALIGN 0 23215 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_EN_BITS 1 23216 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_EN_SHIFT 8 23217 23218 /* XgxsBlk2 :: Aswap66Control2 :: swap_count_sel_override_val [07:07] */ 23219 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_VAL_MASK 0x0080 23220 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_VAL_ALIGN 0 23221 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_VAL_BITS 1 23222 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_VAL_SHIFT 7 23223 23224 /* XgxsBlk2 :: Aswap66Control2 :: dswin_sel_override_en [06:06] */ 23225 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_EN_MASK 0x0040 23226 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_EN_ALIGN 0 23227 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_EN_BITS 1 23228 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_EN_SHIFT 6 23229 23230 /* XgxsBlk2 :: Aswap66Control2 :: dswin_sel_override_val [05:05] */ 23231 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_VAL_MASK 0x0020 23232 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_VAL_ALIGN 0 23233 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_VAL_BITS 1 23234 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_VAL_SHIFT 5 23235 23236 /* XgxsBlk2 :: Aswap66Control2 :: dswin64B66B [04:00] */ 23237 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN64B66B_MASK 0x001f 23238 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN64B66B_ALIGN 0 23239 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN64B66B_BITS 5 23240 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN64B66B_SHIFT 0 23241 23242 23243 /**************************************************************************** 23244 * Warpcore_USER_XgxsBlk3 23245 */ 23246 /**************************************************************************** 23247 * XgxsBlk3 :: localStatus 23248 */ 23249 /* XgxsBlk3 :: localStatus :: reserved0 [15:03] */ 23250 #define XGXSBLK3_LOCALSTATUS_RESERVED0_MASK 0xfff8 23251 #define XGXSBLK3_LOCALSTATUS_RESERVED0_ALIGN 0 23252 #define XGXSBLK3_LOCALSTATUS_RESERVED0_BITS 13 23253 #define XGXSBLK3_LOCALSTATUS_RESERVED0_SHIFT 3 23254 23255 /* XgxsBlk3 :: localStatus :: localIACRdy [02:02] */ 23256 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_MASK 0x0004 23257 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_ALIGN 0 23258 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_BITS 1 23259 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_SHIFT 2 23260 23261 /* XgxsBlk3 :: localStatus :: localRdDataRdy [01:01] */ 23262 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_MASK 0x0002 23263 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_ALIGN 0 23264 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_BITS 1 23265 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_SHIFT 1 23266 23267 /* XgxsBlk3 :: localStatus :: localMdioEn [00:00] */ 23268 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_MASK 0x0001 23269 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_ALIGN 0 23270 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_BITS 1 23271 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_SHIFT 0 23272 23273 23274 /**************************************************************************** 23275 * XgxsBlk3 :: localControl0 23276 */ 23277 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln3_msb [15:15] */ 23278 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_MASK 0x8000 23279 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_ALIGN 0 23280 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_BITS 1 23281 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_SHIFT 15 23282 23283 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln2_msb [14:14] */ 23284 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_MASK 0x4000 23285 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_ALIGN 0 23286 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_BITS 1 23287 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_SHIFT 14 23288 23289 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln1_msb [13:13] */ 23290 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_MASK 0x2000 23291 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_ALIGN 0 23292 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_BITS 1 23293 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_SHIFT 13 23294 23295 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln0_msb [12:12] */ 23296 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_MASK 0x1000 23297 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_ALIGN 0 23298 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_BITS 1 23299 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_SHIFT 12 23300 23301 /* XgxsBlk3 :: localControl0 :: reserved0 [11:08] */ 23302 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_MASK 0x0f00 23303 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_ALIGN 0 23304 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_BITS 4 23305 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_SHIFT 8 23306 23307 /* XgxsBlk3 :: localControl0 :: Q0_DetDis [07:07] */ 23308 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_MASK 0x0080 23309 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_ALIGN 0 23310 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_BITS 1 23311 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_SHIFT 7 23312 23313 /* XgxsBlk3 :: localControl0 :: remoteMdioPassThru [06:06] */ 23314 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_MASK 0x0040 23315 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_ALIGN 0 23316 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_BITS 1 23317 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_SHIFT 6 23318 23319 /* XgxsBlk3 :: localControl0 :: remoteMdioEndPnt [05:05] */ 23320 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_MASK 0x0020 23321 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_ALIGN 0 23322 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_BITS 1 23323 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_SHIFT 5 23324 23325 /* XgxsBlk3 :: localControl0 :: extRemoteMdioEn [04:04] */ 23326 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_MASK 0x0010 23327 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_ALIGN 0 23328 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_BITS 1 23329 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_SHIFT 4 23330 23331 /* XgxsBlk3 :: localControl0 :: rx_inBandMdio_rst [03:03] */ 23332 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_MASK 0x0008 23333 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_ALIGN 0 23334 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_BITS 1 23335 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_SHIFT 3 23336 23337 /* XgxsBlk3 :: localControl0 :: tx_inBandMdio_rst [02:02] */ 23338 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_MASK 0x0004 23339 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_ALIGN 0 23340 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_BITS 1 23341 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_SHIFT 2 23342 23343 /* XgxsBlk3 :: localControl0 :: localWriteReq [01:01] */ 23344 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_MASK 0x0002 23345 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_ALIGN 0 23346 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_BITS 1 23347 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_SHIFT 1 23348 23349 /* XgxsBlk3 :: localControl0 :: remoteMdioEn_reg [00:00] */ 23350 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_MASK 0x0001 23351 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_ALIGN 0 23352 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_BITS 1 23353 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_SHIFT 0 23354 23355 23356 /**************************************************************************** 23357 * XgxsBlk3 :: localControl1 23358 */ 23359 /* XgxsBlk3 :: localControl1 :: rx_inBandMdio_Q0 [15:08] */ 23360 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_MASK 0xff00 23361 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_ALIGN 0 23362 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_BITS 8 23363 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_SHIFT 8 23364 23365 /* XgxsBlk3 :: localControl1 :: reserved0 [07:04] */ 23366 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_MASK 0x00f0 23367 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_ALIGN 0 23368 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_BITS 4 23369 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_SHIFT 4 23370 23371 /* XgxsBlk3 :: localControl1 :: localRemoteErrorClr [03:03] */ 23372 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_MASK 0x0008 23373 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_ALIGN 0 23374 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_BITS 1 23375 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_SHIFT 3 23376 23377 /* XgxsBlk3 :: localControl1 :: rx_inBandMdioStatSel [02:00] */ 23378 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_MASK 0x0007 23379 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_ALIGN 0 23380 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_BITS 3 23381 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_SHIFT 0 23382 23383 23384 /**************************************************************************** 23385 * XgxsBlk3 :: remoteWrite03 23386 */ 23387 /* XgxsBlk3 :: remoteWrite03 :: localWrite_ln0_lsb [15:08] */ 23388 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_MASK 0xff00 23389 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_ALIGN 0 23390 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_BITS 8 23391 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_SHIFT 8 23392 23393 /* XgxsBlk3 :: remoteWrite03 :: localWrite_ln3_lsb [07:00] */ 23394 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_MASK 0x00ff 23395 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_ALIGN 0 23396 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_BITS 8 23397 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_SHIFT 0 23398 23399 23400 /**************************************************************************** 23401 * XgxsBlk3 :: remoteWrite12 23402 */ 23403 /* XgxsBlk3 :: remoteWrite12 :: localWrite_ln1_lsb [15:08] */ 23404 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_MASK 0xff00 23405 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_ALIGN 0 23406 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_BITS 8 23407 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_SHIFT 8 23408 23409 /* XgxsBlk3 :: remoteWrite12 :: localWrite_ln2_lsb [07:00] */ 23410 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_MASK 0x00ff 23411 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_ALIGN 0 23412 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_BITS 8 23413 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_SHIFT 0 23414 23415 23416 /**************************************************************************** 23417 * XgxsBlk3 :: remoteRead12 23418 */ 23419 /* XgxsBlk3 :: remoteRead12 :: localRdData [15:00] */ 23420 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_MASK 0xffff 23421 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_ALIGN 0 23422 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_BITS 16 23423 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_SHIFT 0 23424 23425 23426 /**************************************************************************** 23427 * XgxsBlk3 :: remoteReadx3 23428 */ 23429 /* XgxsBlk3 :: remoteReadx3 :: reserved0 [15:08] */ 23430 #define XGXSBLK3_REMOTEREADX3_RESERVED0_MASK 0xff00 23431 #define XGXSBLK3_REMOTEREADX3_RESERVED0_ALIGN 0 23432 #define XGXSBLK3_REMOTEREADX3_RESERVED0_BITS 8 23433 #define XGXSBLK3_REMOTEREADX3_RESERVED0_SHIFT 8 23434 23435 /* XgxsBlk3 :: remoteReadx3 :: localRdDataId [07:00] */ 23436 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_MASK 0x00ff 23437 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_ALIGN 0 23438 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_BITS 8 23439 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_SHIFT 0 23440 23441 23442 /**************************************************************************** 23443 * XgxsBlk3 :: rx_inBandMdioStat 23444 */ 23445 /* union - case remoteStatus [15:00] */ 23446 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteStatus [15:00] */ 23447 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_MASK 0xffff 23448 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_ALIGN 0 23449 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_BITS 16 23450 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_SHIFT 0 23451 23452 23453 /* union - case remoteControl [15:00] */ 23454 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteControl [15:00] */ 23455 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_MASK 0xffff 23456 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_ALIGN 0 23457 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_BITS 16 23458 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_SHIFT 0 23459 23460 23461 /* union - case remoteAddr [15:00] */ 23462 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteAddr [15:00] */ 23463 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_MASK 0xffff 23464 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_ALIGN 0 23465 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_BITS 16 23466 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_SHIFT 0 23467 23468 23469 /* union - case remoteWrtData [15:00] */ 23470 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteWrtData [15:00] */ 23471 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_MASK 0xffff 23472 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_ALIGN 0 23473 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_BITS 16 23474 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_SHIFT 0 23475 23476 23477 /* union - case remoteIACn_sel [15:00] */ 23478 /* XgxsBlk3 :: rx_inBandMdioStat :: reserved0 [15:08] */ 23479 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_MASK 0xff00 23480 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_ALIGN 0 23481 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_BITS 8 23482 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_SHIFT 8 23483 23484 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteIACn [07:00] */ 23485 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_MASK 0x00ff 23486 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_ALIGN 0 23487 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_BITS 8 23488 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_SHIFT 0 23489 23490 23491 /* union - case rx_inBandTestBus [15:00] */ 23492 /* XgxsBlk3 :: rx_inBandMdioStat :: rx_inBandTestBus [15:00] */ 23493 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_MASK 0xffff 23494 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_ALIGN 0 23495 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_BITS 16 23496 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_SHIFT 0 23497 23498 23499 /* union - case StatusOff [15:00] */ 23500 /* XgxsBlk3 :: rx_inBandMdioStat :: reserved0 [15:00] */ 23501 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_MASK 0xffff 23502 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_ALIGN 0 23503 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_BITS 16 23504 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_SHIFT 0 23505 23506 23507 23508 /**************************************************************************** 23509 * XgxsBlk3 :: localIAC 23510 */ 23511 /* XgxsBlk3 :: localIAC :: IAC_ln1_ln2 [15:08] */ 23512 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_MASK 0xff00 23513 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_ALIGN 0 23514 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_BITS 8 23515 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_SHIFT 8 23516 23517 /* XgxsBlk3 :: localIAC :: reserved0 [07:01] */ 23518 #define XGXSBLK3_LOCALIAC_RESERVED0_MASK 0x00fe 23519 #define XGXSBLK3_LOCALIAC_RESERVED0_ALIGN 0 23520 #define XGXSBLK3_LOCALIAC_RESERVED0_BITS 7 23521 #define XGXSBLK3_LOCALIAC_RESERVED0_SHIFT 1 23522 23523 /* XgxsBlk3 :: localIAC :: localIACReq [00:00] */ 23524 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_MASK 0x0001 23525 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_ALIGN 0 23526 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_BITS 1 23527 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_SHIFT 0 23528 23529 23530 /**************************************************************************** 23531 * XgxsBlk3 :: remoteIACn 23532 */ 23533 /* XgxsBlk3 :: remoteIACn :: reserved0 [15:08] */ 23534 #define XGXSBLK3_REMOTEIACN_RESERVED0_MASK 0xff00 23535 #define XGXSBLK3_REMOTEIACN_RESERVED0_ALIGN 0 23536 #define XGXSBLK3_REMOTEIACN_RESERVED0_BITS 8 23537 #define XGXSBLK3_REMOTEIACN_RESERVED0_SHIFT 8 23538 23539 /* XgxsBlk3 :: remoteIACn :: localIACn [07:00] */ 23540 #define XGXSBLK3_REMOTEIACN_LOCALIACN_MASK 0x00ff 23541 #define XGXSBLK3_REMOTEIACN_LOCALIACN_ALIGN 0 23542 #define XGXSBLK3_REMOTEIACN_LOCALIACN_BITS 8 23543 #define XGXSBLK3_REMOTEIACN_LOCALIACN_SHIFT 0 23544 23545 23546 /**************************************************************************** 23547 * Warpcore_USER_XgxsBlk4 23548 */ 23549 /**************************************************************************** 23550 * XgxsBlk4 :: MiscRxStatus 23551 */ 23552 /* union - case statusSelect0 [15:00] */ 23553 /* XgxsBlk4 :: MiscRxStatus :: capture_NP_lh [15:15] */ 23554 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK 0x8000 23555 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN 0 23556 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS 1 23557 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT 15 23558 23559 /* XgxsBlk4 :: MiscRxStatus :: teton_brk_link_lh [14:14] */ 23560 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000 23561 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0 23562 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1 23563 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14 23564 23565 /* XgxsBlk4 :: MiscRxStatus :: UP3_lh [13:13] */ 23566 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK 0x2000 23567 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN 0 23568 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS 1 23569 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT 13 23570 23571 /* XgxsBlk4 :: MiscRxStatus :: MP5_lh [12:12] */ 23572 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK 0x1000 23573 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN 0 23574 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS 1 23575 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT 12 23576 23577 /* XgxsBlk4 :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */ 23578 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800 23579 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0 23580 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1 23581 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11 23582 23583 /* XgxsBlk4 :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */ 23584 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400 23585 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0 23586 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1 23587 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10 23588 23589 /* XgxsBlk4 :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */ 23590 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200 23591 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0 23592 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1 23593 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9 23594 23595 /* XgxsBlk4 :: MiscRxStatus :: invalidSeq_lh [08:08] */ 23596 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK 0x0100 23597 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN 0 23598 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS 1 23599 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT 8 23600 23601 /* XgxsBlk4 :: MiscRxStatus :: nullMP_lh [07:07] */ 23602 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK 0x0080 23603 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN 0 23604 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS 1 23605 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT 7 23606 23607 /* XgxsBlk4 :: MiscRxStatus :: remotePhyMP_lh [06:06] */ 23608 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK 0x0040 23609 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN 0 23610 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS 1 23611 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT 6 23612 23613 /* XgxsBlk4 :: MiscRxStatus :: nonMatchingMP_lh [05:05] */ 23614 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK 0x0020 23615 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0 23616 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS 1 23617 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5 23618 23619 /* XgxsBlk4 :: MiscRxStatus :: over1gMP_lh [04:04] */ 23620 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK 0x0010 23621 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN 0 23622 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS 1 23623 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT 4 23624 23625 /* XgxsBlk4 :: MiscRxStatus :: rx_config_is_0_lh [03:03] */ 23626 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008 23627 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0 23628 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1 23629 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3 23630 23631 /* XgxsBlk4 :: MiscRxStatus :: np_toggle_err_lh [02:02] */ 23632 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK 0x0004 23633 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0 23634 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS 1 23635 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2 23636 23637 /* XgxsBlk4 :: MiscRxStatus :: mr_np_lh [01:01] */ 23638 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK 0x0002 23639 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN 0 23640 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS 1 23641 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT 1 23642 23643 /* XgxsBlk4 :: MiscRxStatus :: mr_bp_lh [00:00] */ 23644 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK 0x0001 23645 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN 0 23646 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS 1 23647 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT 0 23648 23649 23650 /* union - case statusSelect1 [15:00] */ 23651 /* XgxsBlk4 :: MiscRxStatus :: reserved0 [15:04] */ 23652 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK 0xfff0 23653 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN 0 23654 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS 12 23655 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT 4 23656 23657 /* XgxsBlk4 :: MiscRxStatus :: np_count [03:00] */ 23658 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK 0x000f 23659 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN 0 23660 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS 4 23661 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT 0 23662 23663 23664 /* union - case statusSelect2 [15:00] */ 23665 /* XgxsBlk4 :: MiscRxStatus :: reserved0 [15:06] */ 23666 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK 0xffc0 23667 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN 0 23668 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS 10 23669 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT 6 23670 23671 /* XgxsBlk4 :: MiscRxStatus :: remote_phy_enable [05:05] */ 23672 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020 23673 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0 23674 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1 23675 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5 23676 23677 /* XgxsBlk4 :: MiscRxStatus :: det_teton_mode [04:04] */ 23678 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK 0x0010 23679 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN 0 23680 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS 1 23681 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT 4 23682 23683 /* XgxsBlk4 :: MiscRxStatus :: cu_linkdown [03:03] */ 23684 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK 0x0008 23685 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN 0 23686 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS 1 23687 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT 3 23688 23689 /* XgxsBlk4 :: MiscRxStatus :: cu_resolution_error [02:02] */ 23690 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004 23691 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0 23692 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1 23693 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2 23694 23695 /* XgxsBlk4 :: MiscRxStatus :: remotePhy_autosel [01:01] */ 23696 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002 23697 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0 23698 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1 23699 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1 23700 23701 /* XgxsBlk4 :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */ 23702 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001 23703 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0 23704 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1 23705 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0 23706 23707 23708 /* union - case statusSelect3 [15:00] */ 23709 /* XgxsBlk4 :: MiscRxStatus :: reserved0 [15:06] */ 23710 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_MASK 0xffc0 23711 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_ALIGN 0 23712 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_BITS 10 23713 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_SHIFT 6 23714 23715 /* XgxsBlk4 :: MiscRxStatus :: sgmii_selector_mismatch [05:05] */ 23716 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_MASK 0x0020 23717 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_ALIGN 0 23718 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_BITS 1 23719 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_SHIFT 5 23720 23721 /* XgxsBlk4 :: MiscRxStatus :: autoneg_enable_ov [04:04] */ 23722 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_MASK 0x0010 23723 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_ALIGN 0 23724 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_BITS 1 23725 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_SHIFT 4 23726 23727 /* XgxsBlk4 :: MiscRxStatus :: s_mr_an_enable [03:03] */ 23728 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_MASK 0x0008 23729 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_ALIGN 0 23730 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_BITS 1 23731 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_SHIFT 3 23732 23733 /* XgxsBlk4 :: MiscRxStatus :: s_cl73_rslv_KX4 [02:02] */ 23734 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_MASK 0x0004 23735 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_ALIGN 0 23736 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_BITS 1 23737 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_SHIFT 2 23738 23739 /* XgxsBlk4 :: MiscRxStatus :: s_cl73_rslv_KX [01:01] */ 23740 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_MASK 0x0002 23741 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_ALIGN 0 23742 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_BITS 1 23743 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_SHIFT 1 23744 23745 /* XgxsBlk4 :: MiscRxStatus :: KX_detect [00:00] */ 23746 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_MASK 0x0001 23747 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_ALIGN 0 23748 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_BITS 1 23749 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_SHIFT 0 23750 23751 23752 23753 /**************************************************************************** 23754 * XgxsBlk4 :: xgxsStatus0 23755 */ 23756 /* XgxsBlk4 :: xgxsStatus0 :: status_en [15:15] */ 23757 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_MASK 0x8000 23758 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_ALIGN 0 23759 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_BITS 1 23760 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_SHIFT 15 23761 23762 /* XgxsBlk4 :: xgxsStatus0 :: reserved0 [14:14] */ 23763 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_MASK 0x4000 23764 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_ALIGN 0 23765 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_BITS 1 23766 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_SHIFT 14 23767 23768 /* XgxsBlk4 :: xgxsStatus0 :: tx_remote_fault [13:13] */ 23769 #define XGXSBLK4_XGXSSTATUS0_TX_REMOTE_FAULT_MASK 0x2000 23770 #define XGXSBLK4_XGXSSTATUS0_TX_REMOTE_FAULT_ALIGN 0 23771 #define XGXSBLK4_XGXSSTATUS0_TX_REMOTE_FAULT_BITS 1 23772 #define XGXSBLK4_XGXSSTATUS0_TX_REMOTE_FAULT_SHIFT 13 23773 23774 /* XgxsBlk4 :: xgxsStatus0 :: rx_remote_fault [12:12] */ 23775 #define XGXSBLK4_XGXSSTATUS0_RX_REMOTE_FAULT_MASK 0x1000 23776 #define XGXSBLK4_XGXSSTATUS0_RX_REMOTE_FAULT_ALIGN 0 23777 #define XGXSBLK4_XGXSSTATUS0_RX_REMOTE_FAULT_BITS 1 23778 #define XGXSBLK4_XGXSSTATUS0_RX_REMOTE_FAULT_SHIFT 12 23779 23780 /* XgxsBlk4 :: xgxsStatus0 :: txpll_lock [11:11] */ 23781 #define XGXSBLK4_XGXSSTATUS0_TXPLL_LOCK_MASK 0x0800 23782 #define XGXSBLK4_XGXSSTATUS0_TXPLL_LOCK_ALIGN 0 23783 #define XGXSBLK4_XGXSSTATUS0_TXPLL_LOCK_BITS 1 23784 #define XGXSBLK4_XGXSSTATUS0_TXPLL_LOCK_SHIFT 11 23785 23786 /* XgxsBlk4 :: xgxsStatus0 :: txd_fifo_err [10:10] */ 23787 #define XGXSBLK4_XGXSSTATUS0_TXD_FIFO_ERR_MASK 0x0400 23788 #define XGXSBLK4_XGXSSTATUS0_TXD_FIFO_ERR_ALIGN 0 23789 #define XGXSBLK4_XGXSSTATUS0_TXD_FIFO_ERR_BITS 1 23790 #define XGXSBLK4_XGXSSTATUS0_TXD_FIFO_ERR_SHIFT 10 23791 23792 /* XgxsBlk4 :: xgxsStatus0 :: sequencer_done [09:09] */ 23793 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_DONE_MASK 0x0200 23794 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_DONE_ALIGN 0 23795 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_DONE_BITS 1 23796 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_DONE_SHIFT 9 23797 23798 /* XgxsBlk4 :: xgxsStatus0 :: sequencer_pass [08:08] */ 23799 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_PASS_MASK 0x0100 23800 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_PASS_ALIGN 0 23801 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_PASS_BITS 1 23802 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_PASS_SHIFT 8 23803 23804 /* XgxsBlk4 :: xgxsStatus0 :: rxferr [07:04] */ 23805 #define XGXSBLK4_XGXSSTATUS0_RXFERR_MASK 0x00f0 23806 #define XGXSBLK4_XGXSSTATUS0_RXFERR_ALIGN 0 23807 #define XGXSBLK4_XGXSSTATUS0_RXFERR_BITS 4 23808 #define XGXSBLK4_XGXSSTATUS0_RXFERR_SHIFT 4 23809 23810 /* XgxsBlk4 :: xgxsStatus0 :: pll_mode_afe [03:03] */ 23811 #define XGXSBLK4_XGXSSTATUS0_PLL_MODE_AFE_MASK 0x0008 23812 #define XGXSBLK4_XGXSSTATUS0_PLL_MODE_AFE_ALIGN 0 23813 #define XGXSBLK4_XGXSSTATUS0_PLL_MODE_AFE_BITS 1 23814 #define XGXSBLK4_XGXSSTATUS0_PLL_MODE_AFE_SHIFT 3 23815 23816 /* XgxsBlk4 :: xgxsStatus0 :: ckcmp_unflow [02:02] */ 23817 #define XGXSBLK4_XGXSSTATUS0_CKCMP_UNFLOW_MASK 0x0004 23818 #define XGXSBLK4_XGXSSTATUS0_CKCMP_UNFLOW_ALIGN 0 23819 #define XGXSBLK4_XGXSSTATUS0_CKCMP_UNFLOW_BITS 1 23820 #define XGXSBLK4_XGXSSTATUS0_CKCMP_UNFLOW_SHIFT 2 23821 23822 /* XgxsBlk4 :: xgxsStatus0 :: ckcmp_ovflow [01:01] */ 23823 #define XGXSBLK4_XGXSSTATUS0_CKCMP_OVFLOW_MASK 0x0002 23824 #define XGXSBLK4_XGXSSTATUS0_CKCMP_OVFLOW_ALIGN 0 23825 #define XGXSBLK4_XGXSSTATUS0_CKCMP_OVFLOW_BITS 1 23826 #define XGXSBLK4_XGXSSTATUS0_CKCMP_OVFLOW_SHIFT 1 23827 23828 /* XgxsBlk4 :: xgxsStatus0 :: skew_status [00:00] */ 23829 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_MASK 0x0001 23830 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_ALIGN 0 23831 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_BITS 1 23832 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_SHIFT 0 23833 23834 23835 /**************************************************************************** 23836 * XgxsBlk4 :: xgxsStatus1 23837 */ 23838 /* XgxsBlk4 :: xgxsStatus1 :: mode_10g_tx [15:12] */ 23839 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_MASK 0xf000 23840 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_ALIGN 0 23841 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_BITS 4 23842 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_SHIFT 12 23843 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_XGXS 0 23844 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_XGXG_nCC 1 23845 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_IndLane_OS8 4 23846 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_IndLane_OS5 5 23847 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_PCI 7 23848 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQ 8 23849 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQnCC 9 23850 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_PBypass 10 23851 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_PBypass_nDSK 11 23852 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_ComboCoreMode 12 23853 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_Clocks_off 15 23854 23855 /* XgxsBlk4 :: xgxsStatus1 :: serdesMode_en_tx [11:11] */ 23856 #define XGXSBLK4_XGXSSTATUS1_SERDESMODE_EN_TX_MASK 0x0800 23857 #define XGXSBLK4_XGXSSTATUS1_SERDESMODE_EN_TX_ALIGN 0 23858 #define XGXSBLK4_XGXSSTATUS1_SERDESMODE_EN_TX_BITS 1 23859 #define XGXSBLK4_XGXSSTATUS1_SERDESMODE_EN_TX_SHIFT 11 23860 23861 /* XgxsBlk4 :: xgxsStatus1 :: sgmii_mode [10:10] */ 23862 #define XGXSBLK4_XGXSSTATUS1_SGMII_MODE_MASK 0x0400 23863 #define XGXSBLK4_XGXSSTATUS1_SGMII_MODE_ALIGN 0 23864 #define XGXSBLK4_XGXSSTATUS1_SGMII_MODE_BITS 1 23865 #define XGXSBLK4_XGXSSTATUS1_SGMII_MODE_SHIFT 10 23866 23867 /* XgxsBlk4 :: xgxsStatus1 :: link10g [09:09] */ 23868 #define XGXSBLK4_XGXSSTATUS1_LINK10G_MASK 0x0200 23869 #define XGXSBLK4_XGXSSTATUS1_LINK10G_ALIGN 0 23870 #define XGXSBLK4_XGXSSTATUS1_LINK10G_BITS 1 23871 #define XGXSBLK4_XGXSSTATUS1_LINK10G_SHIFT 9 23872 23873 /* XgxsBlk4 :: xgxsStatus1 :: linkstat [08:08] */ 23874 #define XGXSBLK4_XGXSSTATUS1_LINKSTAT_MASK 0x0100 23875 #define XGXSBLK4_XGXSSTATUS1_LINKSTAT_ALIGN 0 23876 #define XGXSBLK4_XGXSSTATUS1_LINKSTAT_BITS 1 23877 #define XGXSBLK4_XGXSSTATUS1_LINKSTAT_SHIFT 8 23878 23879 /* XgxsBlk4 :: xgxsStatus1 :: autoneg_complete [07:07] */ 23880 #define XGXSBLK4_XGXSSTATUS1_AUTONEG_COMPLETE_MASK 0x0080 23881 #define XGXSBLK4_XGXSSTATUS1_AUTONEG_COMPLETE_ALIGN 0 23882 #define XGXSBLK4_XGXSSTATUS1_AUTONEG_COMPLETE_BITS 1 23883 #define XGXSBLK4_XGXSSTATUS1_AUTONEG_COMPLETE_SHIFT 7 23884 23885 /* XgxsBlk4 :: xgxsStatus1 :: reserved0 [06:06] */ 23886 #define XGXSBLK4_XGXSSTATUS1_RESERVED0_MASK 0x0040 23887 #define XGXSBLK4_XGXSSTATUS1_RESERVED0_ALIGN 0 23888 #define XGXSBLK4_XGXSSTATUS1_RESERVED0_BITS 1 23889 #define XGXSBLK4_XGXSSTATUS1_RESERVED0_SHIFT 6 23890 23891 /* XgxsBlk4 :: xgxsStatus1 :: pll_mode_afe [05:04] */ 23892 #define XGXSBLK4_XGXSSTATUS1_PLL_MODE_AFE_MASK 0x0030 23893 #define XGXSBLK4_XGXSSTATUS1_PLL_MODE_AFE_ALIGN 0 23894 #define XGXSBLK4_XGXSSTATUS1_PLL_MODE_AFE_BITS 2 23895 #define XGXSBLK4_XGXSSTATUS1_PLL_MODE_AFE_SHIFT 4 23896 23897 /* XgxsBlk4 :: xgxsStatus1 :: actual_speed_ln0 [03:00] */ 23898 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_MASK 0x000f 23899 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_ALIGN 0 23900 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_BITS 4 23901 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_SHIFT 0 23902 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10M 0 23903 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_100M 1 23904 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_1G 2 23905 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_2p5G 3 23906 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_5G_X4 4 23907 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_6G_X4 5 23908 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_HiG 6 23909 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_CX4 7 23910 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12G_HiG 8 23911 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12p5G_X4 9 23912 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_13G_X4 10 23913 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_15G_X4 11 23914 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_16G_X4 12 23915 23916 23917 /**************************************************************************** 23918 * XgxsBlk4 :: xgxsStatus2 23919 */ 23920 /* XgxsBlk4 :: xgxsStatus2 :: gpwrdwn_rx [15:12] */ 23921 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_RX_MASK 0xf000 23922 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_RX_ALIGN 0 23923 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_RX_BITS 4 23924 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_RX_SHIFT 12 23925 23926 /* XgxsBlk4 :: xgxsStatus2 :: gpwrdwn_tx [11:08] */ 23927 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_TX_MASK 0x0f00 23928 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_TX_ALIGN 0 23929 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_TX_BITS 4 23930 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_TX_SHIFT 8 23931 23932 /* XgxsBlk4 :: xgxsStatus2 :: freq_sel_rx [07:04] */ 23933 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_RX_MASK 0x00f0 23934 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_RX_ALIGN 0 23935 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_RX_BITS 4 23936 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_RX_SHIFT 4 23937 23938 /* XgxsBlk4 :: xgxsStatus2 :: freq_sel_tx [03:00] */ 23939 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_TX_MASK 0x000f 23940 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_TX_ALIGN 0 23941 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_TX_BITS 4 23942 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_TX_SHIFT 0 23943 23944 23945 /**************************************************************************** 23946 * XgxsBlk4 :: Status1000X1 23947 */ 23948 /* XgxsBlk4 :: Status1000X1 :: txfifo_err_detected [15:15] */ 23949 #define XGXSBLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK 0x8000 23950 #define XGXSBLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN 0 23951 #define XGXSBLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS 1 23952 #define XGXSBLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT 15 23953 23954 /* XgxsBlk4 :: Status1000X1 :: rxfifo_err_detected [14:14] */ 23955 #define XGXSBLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK 0x4000 23956 #define XGXSBLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN 0 23957 #define XGXSBLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS 1 23958 #define XGXSBLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT 14 23959 23960 /* XgxsBlk4 :: Status1000X1 :: false_carrier_detected [13:13] */ 23961 #define XGXSBLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK 0x2000 23962 #define XGXSBLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN 0 23963 #define XGXSBLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS 1 23964 #define XGXSBLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT 13 23965 23966 /* XgxsBlk4 :: Status1000X1 :: crc_err_detected [12:12] */ 23967 #define XGXSBLK4_STATUS1000X1_CRC_ERR_DETECTED_MASK 0x1000 23968 #define XGXSBLK4_STATUS1000X1_CRC_ERR_DETECTED_ALIGN 0 23969 #define XGXSBLK4_STATUS1000X1_CRC_ERR_DETECTED_BITS 1 23970 #define XGXSBLK4_STATUS1000X1_CRC_ERR_DETECTED_SHIFT 12 23971 23972 /* XgxsBlk4 :: Status1000X1 :: tx_err_detected [11:11] */ 23973 #define XGXSBLK4_STATUS1000X1_TX_ERR_DETECTED_MASK 0x0800 23974 #define XGXSBLK4_STATUS1000X1_TX_ERR_DETECTED_ALIGN 0 23975 #define XGXSBLK4_STATUS1000X1_TX_ERR_DETECTED_BITS 1 23976 #define XGXSBLK4_STATUS1000X1_TX_ERR_DETECTED_SHIFT 11 23977 23978 /* XgxsBlk4 :: Status1000X1 :: rx_err_detected [10:10] */ 23979 #define XGXSBLK4_STATUS1000X1_RX_ERR_DETECTED_MASK 0x0400 23980 #define XGXSBLK4_STATUS1000X1_RX_ERR_DETECTED_ALIGN 0 23981 #define XGXSBLK4_STATUS1000X1_RX_ERR_DETECTED_BITS 1 23982 #define XGXSBLK4_STATUS1000X1_RX_ERR_DETECTED_SHIFT 10 23983 23984 /* XgxsBlk4 :: Status1000X1 :: carrier_extend_err_detected [09:09] */ 23985 #define XGXSBLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200 23986 #define XGXSBLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0 23987 #define XGXSBLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1 23988 #define XGXSBLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9 23989 23990 /* XgxsBlk4 :: Status1000X1 :: early_end_extension_detected [08:08] */ 23991 #define XGXSBLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100 23992 #define XGXSBLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0 23993 #define XGXSBLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1 23994 #define XGXSBLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8 23995 23996 /* XgxsBlk4 :: Status1000X1 :: link_status_change [07:07] */ 23997 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_CHANGE_MASK 0x0080 23998 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN 0 23999 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_CHANGE_BITS 1 24000 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT 7 24001 24002 /* XgxsBlk4 :: Status1000X1 :: pause_resolution_rxside [06:06] */ 24003 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0040 24004 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 24005 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS 1 24006 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT 6 24007 24008 /* XgxsBlk4 :: Status1000X1 :: pause_resolution_txside [05:05] */ 24009 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0020 24010 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 24011 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS 1 24012 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT 5 24013 24014 /* XgxsBlk4 :: Status1000X1 :: speed_status [04:03] */ 24015 #define XGXSBLK4_STATUS1000X1_SPEED_STATUS_MASK 0x0018 24016 #define XGXSBLK4_STATUS1000X1_SPEED_STATUS_ALIGN 0 24017 #define XGXSBLK4_STATUS1000X1_SPEED_STATUS_BITS 2 24018 #define XGXSBLK4_STATUS1000X1_SPEED_STATUS_SHIFT 3 24019 24020 /* XgxsBlk4 :: Status1000X1 :: duplex_status [02:02] */ 24021 #define XGXSBLK4_STATUS1000X1_DUPLEX_STATUS_MASK 0x0004 24022 #define XGXSBLK4_STATUS1000X1_DUPLEX_STATUS_ALIGN 0 24023 #define XGXSBLK4_STATUS1000X1_DUPLEX_STATUS_BITS 1 24024 #define XGXSBLK4_STATUS1000X1_DUPLEX_STATUS_SHIFT 2 24025 24026 /* XgxsBlk4 :: Status1000X1 :: link_status [01:01] */ 24027 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_MASK 0x0002 24028 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_ALIGN 0 24029 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_BITS 1 24030 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_SHIFT 1 24031 24032 /* XgxsBlk4 :: Status1000X1 :: sgmii_mode [00:00] */ 24033 #define XGXSBLK4_STATUS1000X1_SGMII_MODE_MASK 0x0001 24034 #define XGXSBLK4_STATUS1000X1_SGMII_MODE_ALIGN 0 24035 #define XGXSBLK4_STATUS1000X1_SGMII_MODE_BITS 1 24036 #define XGXSBLK4_STATUS1000X1_SGMII_MODE_SHIFT 0 24037 24038 24039 /**************************************************************************** 24040 * XgxsBlk4 :: Status1000X2 24041 */ 24042 /* XgxsBlk4 :: Status1000X2 :: sgmii_mode_change [15:15] */ 24043 #define XGXSBLK4_STATUS1000X2_SGMII_MODE_CHANGE_MASK 0x8000 24044 #define XGXSBLK4_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN 0 24045 #define XGXSBLK4_STATUS1000X2_SGMII_MODE_CHANGE_BITS 1 24046 #define XGXSBLK4_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT 15 24047 24048 /* XgxsBlk4 :: Status1000X2 :: consistency_mismatch [14:14] */ 24049 #define XGXSBLK4_STATUS1000X2_CONSISTENCY_MISMATCH_MASK 0x4000 24050 #define XGXSBLK4_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN 0 24051 #define XGXSBLK4_STATUS1000X2_CONSISTENCY_MISMATCH_BITS 1 24052 #define XGXSBLK4_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT 14 24053 24054 /* XgxsBlk4 :: Status1000X2 :: autoneg_resolution_err [13:13] */ 24055 #define XGXSBLK4_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK 0x2000 24056 #define XGXSBLK4_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN 0 24057 #define XGXSBLK4_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS 1 24058 #define XGXSBLK4_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT 13 24059 24060 /* XgxsBlk4 :: Status1000X2 :: sgmii_selector_mismatch [12:12] */ 24061 #define XGXSBLK4_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK 0x1000 24062 #define XGXSBLK4_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN 0 24063 #define XGXSBLK4_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS 1 24064 #define XGXSBLK4_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT 12 24065 24066 /* XgxsBlk4 :: Status1000X2 :: sync_status_fail [11:11] */ 24067 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_FAIL_MASK 0x0800 24068 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN 0 24069 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_FAIL_BITS 1 24070 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT 11 24071 24072 /* XgxsBlk4 :: Status1000X2 :: sync_status_ok [10:10] */ 24073 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_OK_MASK 0x0400 24074 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_OK_ALIGN 0 24075 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_OK_BITS 1 24076 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_OK_SHIFT 10 24077 24078 /* XgxsBlk4 :: Status1000X2 :: rudi_c [09:09] */ 24079 #define XGXSBLK4_STATUS1000X2_RUDI_C_MASK 0x0200 24080 #define XGXSBLK4_STATUS1000X2_RUDI_C_ALIGN 0 24081 #define XGXSBLK4_STATUS1000X2_RUDI_C_BITS 1 24082 #define XGXSBLK4_STATUS1000X2_RUDI_C_SHIFT 9 24083 24084 /* XgxsBlk4 :: Status1000X2 :: rudi_I [08:08] */ 24085 #define XGXSBLK4_STATUS1000X2_RUDI_I_MASK 0x0100 24086 #define XGXSBLK4_STATUS1000X2_RUDI_I_ALIGN 0 24087 #define XGXSBLK4_STATUS1000X2_RUDI_I_BITS 1 24088 #define XGXSBLK4_STATUS1000X2_RUDI_I_SHIFT 8 24089 24090 /* XgxsBlk4 :: Status1000X2 :: rudi_invalid [07:07] */ 24091 #define XGXSBLK4_STATUS1000X2_RUDI_INVALID_MASK 0x0080 24092 #define XGXSBLK4_STATUS1000X2_RUDI_INVALID_ALIGN 0 24093 #define XGXSBLK4_STATUS1000X2_RUDI_INVALID_BITS 1 24094 #define XGXSBLK4_STATUS1000X2_RUDI_INVALID_SHIFT 7 24095 24096 /* XgxsBlk4 :: Status1000X2 :: linkDown_syncLoss [06:06] */ 24097 #define XGXSBLK4_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK 0x0040 24098 #define XGXSBLK4_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN 0 24099 #define XGXSBLK4_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS 1 24100 #define XGXSBLK4_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT 6 24101 24102 /* XgxsBlk4 :: Status1000X2 :: idle_detect_state [05:05] */ 24103 #define XGXSBLK4_STATUS1000X2_IDLE_DETECT_STATE_MASK 0x0020 24104 #define XGXSBLK4_STATUS1000X2_IDLE_DETECT_STATE_ALIGN 0 24105 #define XGXSBLK4_STATUS1000X2_IDLE_DETECT_STATE_BITS 1 24106 #define XGXSBLK4_STATUS1000X2_IDLE_DETECT_STATE_SHIFT 5 24107 24108 /* XgxsBlk4 :: Status1000X2 :: complete_acknowledge_state [04:04] */ 24109 #define XGXSBLK4_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010 24110 #define XGXSBLK4_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0 24111 #define XGXSBLK4_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1 24112 #define XGXSBLK4_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4 24113 24114 /* XgxsBlk4 :: Status1000X2 :: acknowledge_detect_state [03:03] */ 24115 #define XGXSBLK4_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK 0x0008 24116 #define XGXSBLK4_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0 24117 #define XGXSBLK4_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS 1 24118 #define XGXSBLK4_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3 24119 24120 /* XgxsBlk4 :: Status1000X2 :: ability_detect_state [02:02] */ 24121 #define XGXSBLK4_STATUS1000X2_ABILITY_DETECT_STATE_MASK 0x0004 24122 #define XGXSBLK4_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN 0 24123 #define XGXSBLK4_STATUS1000X2_ABILITY_DETECT_STATE_BITS 1 24124 #define XGXSBLK4_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT 2 24125 24126 /* union - case anError [01:01] */ 24127 /* XgxsBlk4 :: Status1000X2 :: an_error_state [01:01] */ 24128 #define XGXSBLK4_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK 0x0002 24129 #define XGXSBLK4_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN 0 24130 #define XGXSBLK4_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS 1 24131 #define XGXSBLK4_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT 1 24132 24133 24134 /* union - case anDisableLink [01:01] */ 24135 /* XgxsBlk4 :: Status1000X2 :: an_disable_link_ok_state [01:01] */ 24136 #define XGXSBLK4_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002 24137 #define XGXSBLK4_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0 24138 #define XGXSBLK4_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1 24139 #define XGXSBLK4_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1 24140 24141 24142 /* XgxsBlk4 :: Status1000X2 :: an_enable_state [00:00] */ 24143 #define XGXSBLK4_STATUS1000X2_AN_ENABLE_STATE_MASK 0x0001 24144 #define XGXSBLK4_STATUS1000X2_AN_ENABLE_STATE_ALIGN 0 24145 #define XGXSBLK4_STATUS1000X2_AN_ENABLE_STATE_BITS 1 24146 #define XGXSBLK4_STATUS1000X2_AN_ENABLE_STATE_SHIFT 0 24147 24148 24149 /**************************************************************************** 24150 * XgxsBlk4 :: Status1000X3 24151 */ 24152 /* XgxsBlk4 :: Status1000X3 :: reserved0 [15:13] */ 24153 #define XGXSBLK4_STATUS1000X3_RESERVED0_MASK 0xe000 24154 #define XGXSBLK4_STATUS1000X3_RESERVED0_ALIGN 0 24155 #define XGXSBLK4_STATUS1000X3_RESERVED0_BITS 3 24156 #define XGXSBLK4_STATUS1000X3_RESERVED0_SHIFT 13 24157 24158 /* XgxsBlk4 :: Status1000X3 :: pd_park_an [12:12] */ 24159 #define XGXSBLK4_STATUS1000X3_PD_PARK_AN_MASK 0x1000 24160 #define XGXSBLK4_STATUS1000X3_PD_PARK_AN_ALIGN 0 24161 #define XGXSBLK4_STATUS1000X3_PD_PARK_AN_BITS 1 24162 #define XGXSBLK4_STATUS1000X3_PD_PARK_AN_SHIFT 12 24163 24164 /* XgxsBlk4 :: Status1000X3 :: remotePhy_autosel [11:11] */ 24165 #define XGXSBLK4_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK 0x0800 24166 #define XGXSBLK4_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN 0 24167 #define XGXSBLK4_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS 1 24168 #define XGXSBLK4_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT 11 24169 24170 /* XgxsBlk4 :: Status1000X3 :: latch_linkdown [10:10] */ 24171 #define XGXSBLK4_STATUS1000X3_LATCH_LINKDOWN_MASK 0x0400 24172 #define XGXSBLK4_STATUS1000X3_LATCH_LINKDOWN_ALIGN 0 24173 #define XGXSBLK4_STATUS1000X3_LATCH_LINKDOWN_BITS 1 24174 #define XGXSBLK4_STATUS1000X3_LATCH_LINKDOWN_SHIFT 10 24175 24176 /* XgxsBlk4 :: Status1000X3 :: sd_filter [09:09] */ 24177 #define XGXSBLK4_STATUS1000X3_SD_FILTER_MASK 0x0200 24178 #define XGXSBLK4_STATUS1000X3_SD_FILTER_ALIGN 0 24179 #define XGXSBLK4_STATUS1000X3_SD_FILTER_BITS 1 24180 #define XGXSBLK4_STATUS1000X3_SD_FILTER_SHIFT 9 24181 24182 /* XgxsBlk4 :: Status1000X3 :: sd_mux [08:08] */ 24183 #define XGXSBLK4_STATUS1000X3_SD_MUX_MASK 0x0100 24184 #define XGXSBLK4_STATUS1000X3_SD_MUX_ALIGN 0 24185 #define XGXSBLK4_STATUS1000X3_SD_MUX_BITS 1 24186 #define XGXSBLK4_STATUS1000X3_SD_MUX_SHIFT 8 24187 24188 /* XgxsBlk4 :: Status1000X3 :: sd_filter_chg [07:07] */ 24189 #define XGXSBLK4_STATUS1000X3_SD_FILTER_CHG_MASK 0x0080 24190 #define XGXSBLK4_STATUS1000X3_SD_FILTER_CHG_ALIGN 0 24191 #define XGXSBLK4_STATUS1000X3_SD_FILTER_CHG_BITS 1 24192 #define XGXSBLK4_STATUS1000X3_SD_FILTER_CHG_SHIFT 7 24193 24194 /* XgxsBlk4 :: Status1000X3 :: reserved1 [06:00] */ 24195 #define XGXSBLK4_STATUS1000X3_RESERVED1_MASK 0x007f 24196 #define XGXSBLK4_STATUS1000X3_RESERVED1_ALIGN 0 24197 #define XGXSBLK4_STATUS1000X3_RESERVED1_BITS 7 24198 #define XGXSBLK4_STATUS1000X3_RESERVED1_SHIFT 0 24199 24200 24201 /**************************************************************************** 24202 * XgxsBlk4 :: TPOUT_1 24203 */ 24204 /* XgxsBlk4 :: TPOUT_1 :: tpout1 [15:00] */ 24205 #define XGXSBLK4_TPOUT_1_TPOUT1_MASK 0xffff 24206 #define XGXSBLK4_TPOUT_1_TPOUT1_ALIGN 0 24207 #define XGXSBLK4_TPOUT_1_TPOUT1_BITS 16 24208 #define XGXSBLK4_TPOUT_1_TPOUT1_SHIFT 0 24209 24210 24211 /**************************************************************************** 24212 * XgxsBlk4 :: TPOUT_2 24213 */ 24214 /* XgxsBlk4 :: TPOUT_2 :: tpout2 [15:00] */ 24215 #define XGXSBLK4_TPOUT_2_TPOUT2_MASK 0xffff 24216 #define XGXSBLK4_TPOUT_2_TPOUT2_ALIGN 0 24217 #define XGXSBLK4_TPOUT_2_TPOUT2_BITS 16 24218 #define XGXSBLK4_TPOUT_2_TPOUT2_SHIFT 0 24219 24220 24221 /**************************************************************************** 24222 * XgxsBlk4 :: xgxsStatus3 24223 */ 24224 /* XgxsBlk4 :: xgxsStatus3 :: link [15:15] */ 24225 #define XGXSBLK4_XGXSSTATUS3_LINK_MASK 0x8000 24226 #define XGXSBLK4_XGXSSTATUS3_LINK_ALIGN 0 24227 #define XGXSBLK4_XGXSSTATUS3_LINK_BITS 1 24228 #define XGXSBLK4_XGXSSTATUS3_LINK_SHIFT 15 24229 24230 /* XgxsBlk4 :: xgxsStatus3 :: link_latchdown [14:14] */ 24231 #define XGXSBLK4_XGXSSTATUS3_LINK_LATCHDOWN_MASK 0x4000 24232 #define XGXSBLK4_XGXSSTATUS3_LINK_LATCHDOWN_ALIGN 0 24233 #define XGXSBLK4_XGXSSTATUS3_LINK_LATCHDOWN_BITS 1 24234 #define XGXSBLK4_XGXSSTATUS3_LINK_LATCHDOWN_SHIFT 14 24235 24236 /* XgxsBlk4 :: xgxsStatus3 :: latch_linkdown_10g_o [13:13] */ 24237 #define XGXSBLK4_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_MASK 0x2000 24238 #define XGXSBLK4_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_ALIGN 0 24239 #define XGXSBLK4_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_BITS 1 24240 #define XGXSBLK4_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_SHIFT 13 24241 24242 /* XgxsBlk4 :: xgxsStatus3 :: pd_park_an [12:12] */ 24243 #define XGXSBLK4_XGXSSTATUS3_PD_PARK_AN_MASK 0x1000 24244 #define XGXSBLK4_XGXSSTATUS3_PD_PARK_AN_ALIGN 0 24245 #define XGXSBLK4_XGXSSTATUS3_PD_PARK_AN_BITS 1 24246 #define XGXSBLK4_XGXSSTATUS3_PD_PARK_AN_SHIFT 12 24247 24248 /* XgxsBlk4 :: xgxsStatus3 :: gpwrdwn_pll [11:11] */ 24249 #define XGXSBLK4_XGXSSTATUS3_GPWRDWN_PLL_MASK 0x0800 24250 #define XGXSBLK4_XGXSSTATUS3_GPWRDWN_PLL_ALIGN 0 24251 #define XGXSBLK4_XGXSSTATUS3_GPWRDWN_PLL_BITS 1 24252 #define XGXSBLK4_XGXSSTATUS3_GPWRDWN_PLL_SHIFT 11 24253 24254 /* XgxsBlk4 :: xgxsStatus3 :: hcd_over_1g [10:00] */ 24255 #define XGXSBLK4_XGXSSTATUS3_HCD_OVER_1G_MASK 0x07ff 24256 #define XGXSBLK4_XGXSSTATUS3_HCD_OVER_1G_ALIGN 0 24257 #define XGXSBLK4_XGXSSTATUS3_HCD_OVER_1G_BITS 11 24258 #define XGXSBLK4_XGXSSTATUS3_HCD_OVER_1G_SHIFT 0 24259 24260 24261 /**************************************************************************** 24262 * XgxsBlk4 :: x2500Status1 24263 */ 24264 /* XgxsBlk4 :: x2500Status1 :: hcd_over_1g_or [15:15] */ 24265 #define XGXSBLK4_X2500STATUS1_HCD_OVER_1G_OR_MASK 0x8000 24266 #define XGXSBLK4_X2500STATUS1_HCD_OVER_1G_OR_ALIGN 0 24267 #define XGXSBLK4_X2500STATUS1_HCD_OVER_1G_OR_BITS 1 24268 #define XGXSBLK4_X2500STATUS1_HCD_OVER_1G_OR_SHIFT 15 24269 24270 /* XgxsBlk4 :: x2500Status1 :: latch_hcd_over_1g [14:14] */ 24271 #define XGXSBLK4_X2500STATUS1_LATCH_HCD_OVER_1G_MASK 0x4000 24272 #define XGXSBLK4_X2500STATUS1_LATCH_HCD_OVER_1G_ALIGN 0 24273 #define XGXSBLK4_X2500STATUS1_LATCH_HCD_OVER_1G_BITS 1 24274 #define XGXSBLK4_X2500STATUS1_LATCH_HCD_OVER_1G_SHIFT 14 24275 24276 /* XgxsBlk4 :: x2500Status1 :: latchmdio [13:13] */ 24277 #define XGXSBLK4_X2500STATUS1_LATCHMDIO_MASK 0x2000 24278 #define XGXSBLK4_X2500STATUS1_LATCHMDIO_ALIGN 0 24279 #define XGXSBLK4_X2500STATUS1_LATCHMDIO_BITS 1 24280 #define XGXSBLK4_X2500STATUS1_LATCHMDIO_SHIFT 13 24281 24282 /* XgxsBlk4 :: x2500Status1 :: s_bc_reg_rst [12:12] */ 24283 #define XGXSBLK4_X2500STATUS1_S_BC_REG_RST_MASK 0x1000 24284 #define XGXSBLK4_X2500STATUS1_S_BC_REG_RST_ALIGN 0 24285 #define XGXSBLK4_X2500STATUS1_S_BC_REG_RST_BITS 1 24286 #define XGXSBLK4_X2500STATUS1_S_BC_REG_RST_SHIFT 12 24287 24288 /* XgxsBlk4 :: x2500Status1 :: s_wait2res [11:11] */ 24289 #define XGXSBLK4_X2500STATUS1_S_WAIT2RES_MASK 0x0800 24290 #define XGXSBLK4_X2500STATUS1_S_WAIT2RES_ALIGN 0 24291 #define XGXSBLK4_X2500STATUS1_S_WAIT2RES_BITS 1 24292 #define XGXSBLK4_X2500STATUS1_S_WAIT2RES_SHIFT 11 24293 24294 /* XgxsBlk4 :: x2500Status1 :: s_wait30ms [10:10] */ 24295 #define XGXSBLK4_X2500STATUS1_S_WAIT30MS_MASK 0x0400 24296 #define XGXSBLK4_X2500STATUS1_S_WAIT30MS_ALIGN 0 24297 #define XGXSBLK4_X2500STATUS1_S_WAIT30MS_BITS 1 24298 #define XGXSBLK4_X2500STATUS1_S_WAIT30MS_SHIFT 10 24299 24300 /* XgxsBlk4 :: x2500Status1 :: s_clockswit [09:09] */ 24301 #define XGXSBLK4_X2500STATUS1_S_CLOCKSWIT_MASK 0x0200 24302 #define XGXSBLK4_X2500STATUS1_S_CLOCKSWIT_ALIGN 0 24303 #define XGXSBLK4_X2500STATUS1_S_CLOCKSWIT_BITS 1 24304 #define XGXSBLK4_X2500STATUS1_S_CLOCKSWIT_SHIFT 9 24305 24306 /* XgxsBlk4 :: x2500Status1 :: s_pllswit [08:08] */ 24307 #define XGXSBLK4_X2500STATUS1_S_PLLSWIT_MASK 0x0100 24308 #define XGXSBLK4_X2500STATUS1_S_PLLSWIT_ALIGN 0 24309 #define XGXSBLK4_X2500STATUS1_S_PLLSWIT_BITS 1 24310 #define XGXSBLK4_X2500STATUS1_S_PLLSWIT_SHIFT 8 24311 24312 /* XgxsBlk4 :: x2500Status1 :: s_wait4link [07:07] */ 24313 #define XGXSBLK4_X2500STATUS1_S_WAIT4LINK_MASK 0x0080 24314 #define XGXSBLK4_X2500STATUS1_S_WAIT4LINK_ALIGN 0 24315 #define XGXSBLK4_X2500STATUS1_S_WAIT4LINK_BITS 1 24316 #define XGXSBLK4_X2500STATUS1_S_WAIT4LINK_SHIFT 7 24317 24318 /* XgxsBlk4 :: x2500Status1 :: s_complete [06:06] */ 24319 #define XGXSBLK4_X2500STATUS1_S_COMPLETE_MASK 0x0040 24320 #define XGXSBLK4_X2500STATUS1_S_COMPLETE_ALIGN 0 24321 #define XGXSBLK4_X2500STATUS1_S_COMPLETE_BITS 1 24322 #define XGXSBLK4_X2500STATUS1_S_COMPLETE_SHIFT 6 24323 24324 /* XgxsBlk4 :: x2500Status1 :: s_lostlink [05:05] */ 24325 #define XGXSBLK4_X2500STATUS1_S_LOSTLINK_MASK 0x0020 24326 #define XGXSBLK4_X2500STATUS1_S_LOSTLINK_ALIGN 0 24327 #define XGXSBLK4_X2500STATUS1_S_LOSTLINK_BITS 1 24328 #define XGXSBLK4_X2500STATUS1_S_LOSTLINK_SHIFT 5 24329 24330 /* XgxsBlk4 :: x2500Status1 :: s_dead [04:04] */ 24331 #define XGXSBLK4_X2500STATUS1_S_DEAD_MASK 0x0010 24332 #define XGXSBLK4_X2500STATUS1_S_DEAD_ALIGN 0 24333 #define XGXSBLK4_X2500STATUS1_S_DEAD_BITS 1 24334 #define XGXSBLK4_X2500STATUS1_S_DEAD_SHIFT 4 24335 24336 /* XgxsBlk4 :: x2500Status1 :: fail_cnt [03:00] */ 24337 #define XGXSBLK4_X2500STATUS1_FAIL_CNT_MASK 0x000f 24338 #define XGXSBLK4_X2500STATUS1_FAIL_CNT_ALIGN 0 24339 #define XGXSBLK4_X2500STATUS1_FAIL_CNT_BITS 4 24340 #define XGXSBLK4_X2500STATUS1_FAIL_CNT_SHIFT 0 24341 24342 24343 /**************************************************************************** 24344 * XgxsBlk4 :: topANStatus1 24345 */ 24346 /* XgxsBlk4 :: topANStatus1 :: reserved0 [15:14] */ 24347 #define XGXSBLK4_TOPANSTATUS1_RESERVED0_MASK 0xc000 24348 #define XGXSBLK4_TOPANSTATUS1_RESERVED0_ALIGN 0 24349 #define XGXSBLK4_TOPANSTATUS1_RESERVED0_BITS 2 24350 #define XGXSBLK4_TOPANSTATUS1_RESERVED0_SHIFT 14 24351 24352 /* XgxsBlk4 :: topANStatus1 :: actual_speed [13:08] */ 24353 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_MASK 0x3f00 24354 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_ALIGN 0 24355 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_BITS 6 24356 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_SHIFT 8 24357 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10M 0 24358 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_100M 1 24359 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_1G 2 24360 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_2p5G 3 24361 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_5G_X4 4 24362 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_6G_X4 5 24363 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_HiG 6 24364 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_CX4 7 24365 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_12G_HiG 8 24366 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_12p5G_X4 9 24367 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_13G_X4 10 24368 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_15G_X4 11 24369 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_16G_X4 12 24370 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_1G_KX 13 24371 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_KX4 14 24372 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_KR 15 24373 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_5G 16 24374 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_6p4G 17 24375 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_X4 18 24376 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_21G_X4 19 24377 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_25G_X4 20 24378 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_HiG_DXGXS 21 24379 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_DXGXS 22 24380 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10p5G_HiG_DXGXS 23 24381 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10p5G_DXGXS 24 24382 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_12p773G_HiG_DXGXS 25 24383 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_12p773G_DXGXS 26 24384 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_XFI 27 24385 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_40G 28 24386 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_HiG_DXGXS 29 24387 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_DXGXS 30 24388 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_SFI 31 24389 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_31p5G 32 24390 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_32p7G 33 24391 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_SCR 34 24392 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_HiG_DXGXS_SCR 35 24393 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_DXGXS_SCR 36 24394 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_12G_R2 37 24395 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_X2 38 24396 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_40G_KR4 39 24397 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_40G_CR4 40 24398 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_100G_CR10 41 24399 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_15p75G_DXGXS 44 24400 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_KR2 57 24401 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_CR2 58 24402 24403 /* XgxsBlk4 :: topANStatus1 :: pause_resolution_rxside [07:07] */ 24404 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0080 24405 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 24406 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_BITS 1 24407 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_SHIFT 7 24408 24409 /* XgxsBlk4 :: topANStatus1 :: pause_resolution_txside [06:06] */ 24410 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0040 24411 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 24412 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_BITS 1 24413 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_SHIFT 6 24414 24415 /* XgxsBlk4 :: topANStatus1 :: cl73_lp_np_BAM_able [05:05] */ 24416 #define XGXSBLK4_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_MASK 0x0020 24417 #define XGXSBLK4_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_ALIGN 0 24418 #define XGXSBLK4_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_BITS 1 24419 #define XGXSBLK4_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_SHIFT 5 24420 24421 /* XgxsBlk4 :: topANStatus1 :: cl73_mr_lp_autoneg_able [04:04] */ 24422 #define XGXSBLK4_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_MASK 0x0010 24423 #define XGXSBLK4_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_ALIGN 0 24424 #define XGXSBLK4_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_BITS 1 24425 #define XGXSBLK4_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_SHIFT 4 24426 24427 /* XgxsBlk4 :: topANStatus1 :: duplex_status [03:03] */ 24428 #define XGXSBLK4_TOPANSTATUS1_DUPLEX_STATUS_MASK 0x0008 24429 #define XGXSBLK4_TOPANSTATUS1_DUPLEX_STATUS_ALIGN 0 24430 #define XGXSBLK4_TOPANSTATUS1_DUPLEX_STATUS_BITS 1 24431 #define XGXSBLK4_TOPANSTATUS1_DUPLEX_STATUS_SHIFT 3 24432 24433 /* XgxsBlk4 :: topANStatus1 :: link_status [02:02] */ 24434 #define XGXSBLK4_TOPANSTATUS1_LINK_STATUS_MASK 0x0004 24435 #define XGXSBLK4_TOPANSTATUS1_LINK_STATUS_ALIGN 0 24436 #define XGXSBLK4_TOPANSTATUS1_LINK_STATUS_BITS 1 24437 #define XGXSBLK4_TOPANSTATUS1_LINK_STATUS_SHIFT 2 24438 24439 /* XgxsBlk4 :: topANStatus1 :: cl37_autoneg_complete [01:01] */ 24440 #define XGXSBLK4_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_MASK 0x0002 24441 #define XGXSBLK4_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_ALIGN 0 24442 #define XGXSBLK4_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_BITS 1 24443 #define XGXSBLK4_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_SHIFT 1 24444 24445 /* XgxsBlk4 :: topANStatus1 :: cl73_autoneg_complete [00:00] */ 24446 #define XGXSBLK4_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_MASK 0x0001 24447 #define XGXSBLK4_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_ALIGN 0 24448 #define XGXSBLK4_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_BITS 1 24449 #define XGXSBLK4_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_SHIFT 0 24450 24451 24452 /**************************************************************************** 24453 * XgxsBlk4 :: LP_UP1 24454 */ 24455 /* XgxsBlk4 :: LP_UP1 :: reserved0 [15:11] */ 24456 #define XGXSBLK4_LP_UP1_RESERVED0_MASK 0xf800 24457 #define XGXSBLK4_LP_UP1_RESERVED0_ALIGN 0 24458 #define XGXSBLK4_LP_UP1_RESERVED0_BITS 5 24459 #define XGXSBLK4_LP_UP1_RESERVED0_SHIFT 11 24460 24461 /* XgxsBlk4 :: LP_UP1 :: dataRate_20GX4 [10:10] */ 24462 #define XGXSBLK4_LP_UP1_DATARATE_20GX4_MASK 0x0400 24463 #define XGXSBLK4_LP_UP1_DATARATE_20GX4_ALIGN 0 24464 #define XGXSBLK4_LP_UP1_DATARATE_20GX4_BITS 1 24465 #define XGXSBLK4_LP_UP1_DATARATE_20GX4_SHIFT 10 24466 24467 /* XgxsBlk4 :: LP_UP1 :: dataRate_16GX4 [09:09] */ 24468 #define XGXSBLK4_LP_UP1_DATARATE_16GX4_MASK 0x0200 24469 #define XGXSBLK4_LP_UP1_DATARATE_16GX4_ALIGN 0 24470 #define XGXSBLK4_LP_UP1_DATARATE_16GX4_BITS 1 24471 #define XGXSBLK4_LP_UP1_DATARATE_16GX4_SHIFT 9 24472 24473 /* XgxsBlk4 :: LP_UP1 :: dataRate_15GX4 [08:08] */ 24474 #define XGXSBLK4_LP_UP1_DATARATE_15GX4_MASK 0x0100 24475 #define XGXSBLK4_LP_UP1_DATARATE_15GX4_ALIGN 0 24476 #define XGXSBLK4_LP_UP1_DATARATE_15GX4_BITS 1 24477 #define XGXSBLK4_LP_UP1_DATARATE_15GX4_SHIFT 8 24478 24479 /* XgxsBlk4 :: LP_UP1 :: dataRate_13GX4 [07:07] */ 24480 #define XGXSBLK4_LP_UP1_DATARATE_13GX4_MASK 0x0080 24481 #define XGXSBLK4_LP_UP1_DATARATE_13GX4_ALIGN 0 24482 #define XGXSBLK4_LP_UP1_DATARATE_13GX4_BITS 1 24483 #define XGXSBLK4_LP_UP1_DATARATE_13GX4_SHIFT 7 24484 24485 /* XgxsBlk4 :: LP_UP1 :: dataRate_12p5GX4 [06:06] */ 24486 #define XGXSBLK4_LP_UP1_DATARATE_12P5GX4_MASK 0x0040 24487 #define XGXSBLK4_LP_UP1_DATARATE_12P5GX4_ALIGN 0 24488 #define XGXSBLK4_LP_UP1_DATARATE_12P5GX4_BITS 1 24489 #define XGXSBLK4_LP_UP1_DATARATE_12P5GX4_SHIFT 6 24490 24491 /* XgxsBlk4 :: LP_UP1 :: dataRate_12GX4 [05:05] */ 24492 #define XGXSBLK4_LP_UP1_DATARATE_12GX4_MASK 0x0020 24493 #define XGXSBLK4_LP_UP1_DATARATE_12GX4_ALIGN 0 24494 #define XGXSBLK4_LP_UP1_DATARATE_12GX4_BITS 1 24495 #define XGXSBLK4_LP_UP1_DATARATE_12GX4_SHIFT 5 24496 24497 /* XgxsBlk4 :: LP_UP1 :: dataRate_10GCX4 [04:04] */ 24498 #define XGXSBLK4_LP_UP1_DATARATE_10GCX4_MASK 0x0010 24499 #define XGXSBLK4_LP_UP1_DATARATE_10GCX4_ALIGN 0 24500 #define XGXSBLK4_LP_UP1_DATARATE_10GCX4_BITS 1 24501 #define XGXSBLK4_LP_UP1_DATARATE_10GCX4_SHIFT 4 24502 24503 /* XgxsBlk4 :: LP_UP1 :: dataRate_10GX4 [03:03] */ 24504 #define XGXSBLK4_LP_UP1_DATARATE_10GX4_MASK 0x0008 24505 #define XGXSBLK4_LP_UP1_DATARATE_10GX4_ALIGN 0 24506 #define XGXSBLK4_LP_UP1_DATARATE_10GX4_BITS 1 24507 #define XGXSBLK4_LP_UP1_DATARATE_10GX4_SHIFT 3 24508 24509 /* XgxsBlk4 :: LP_UP1 :: dataRate_6GX4 [02:02] */ 24510 #define XGXSBLK4_LP_UP1_DATARATE_6GX4_MASK 0x0004 24511 #define XGXSBLK4_LP_UP1_DATARATE_6GX4_ALIGN 0 24512 #define XGXSBLK4_LP_UP1_DATARATE_6GX4_BITS 1 24513 #define XGXSBLK4_LP_UP1_DATARATE_6GX4_SHIFT 2 24514 24515 /* XgxsBlk4 :: LP_UP1 :: dataRate_5GX4 [01:01] */ 24516 #define XGXSBLK4_LP_UP1_DATARATE_5GX4_MASK 0x0002 24517 #define XGXSBLK4_LP_UP1_DATARATE_5GX4_ALIGN 0 24518 #define XGXSBLK4_LP_UP1_DATARATE_5GX4_BITS 1 24519 #define XGXSBLK4_LP_UP1_DATARATE_5GX4_SHIFT 1 24520 24521 /* XgxsBlk4 :: LP_UP1 :: dataRate_2p5GX1 [00:00] */ 24522 #define XGXSBLK4_LP_UP1_DATARATE_2P5GX1_MASK 0x0001 24523 #define XGXSBLK4_LP_UP1_DATARATE_2P5GX1_ALIGN 0 24524 #define XGXSBLK4_LP_UP1_DATARATE_2P5GX1_BITS 1 24525 #define XGXSBLK4_LP_UP1_DATARATE_2P5GX1_SHIFT 0 24526 24527 24528 /**************************************************************************** 24529 * XgxsBlk4 :: LP_UP2 24530 */ 24531 /* XgxsBlk4 :: LP_UP2 :: reserved0 [15:11] */ 24532 #define XGXSBLK4_LP_UP2_RESERVED0_MASK 0xf800 24533 #define XGXSBLK4_LP_UP2_RESERVED0_ALIGN 0 24534 #define XGXSBLK4_LP_UP2_RESERVED0_BITS 5 24535 #define XGXSBLK4_LP_UP2_RESERVED0_SHIFT 11 24536 24537 /* XgxsBlk4 :: LP_UP2 :: valid [10:10] */ 24538 #define XGXSBLK4_LP_UP2_VALID_MASK 0x0400 24539 #define XGXSBLK4_LP_UP2_VALID_ALIGN 0 24540 #define XGXSBLK4_LP_UP2_VALID_BITS 1 24541 #define XGXSBLK4_LP_UP2_VALID_SHIFT 10 24542 24543 /* XgxsBlk4 :: LP_UP2 :: preemphasis [09:06] */ 24544 #define XGXSBLK4_LP_UP2_PREEMPHASIS_MASK 0x03c0 24545 #define XGXSBLK4_LP_UP2_PREEMPHASIS_ALIGN 0 24546 #define XGXSBLK4_LP_UP2_PREEMPHASIS_BITS 4 24547 #define XGXSBLK4_LP_UP2_PREEMPHASIS_SHIFT 6 24548 24549 /* XgxsBlk4 :: LP_UP2 :: idriver [05:03] */ 24550 #define XGXSBLK4_LP_UP2_IDRIVER_MASK 0x0038 24551 #define XGXSBLK4_LP_UP2_IDRIVER_ALIGN 0 24552 #define XGXSBLK4_LP_UP2_IDRIVER_BITS 3 24553 #define XGXSBLK4_LP_UP2_IDRIVER_SHIFT 3 24554 24555 /* XgxsBlk4 :: LP_UP2 :: ipredriver [02:00] */ 24556 #define XGXSBLK4_LP_UP2_IPREDRIVER_MASK 0x0007 24557 #define XGXSBLK4_LP_UP2_IPREDRIVER_ALIGN 0 24558 #define XGXSBLK4_LP_UP2_IPREDRIVER_BITS 3 24559 #define XGXSBLK4_LP_UP2_IPREDRIVER_SHIFT 0 24560 24561 24562 /**************************************************************************** 24563 * XgxsBlk4 :: LP_UP3 24564 */ 24565 /* XgxsBlk4 :: LP_UP3 :: reserved0 [15:11] */ 24566 #define XGXSBLK4_LP_UP3_RESERVED0_MASK 0xf800 24567 #define XGXSBLK4_LP_UP3_RESERVED0_ALIGN 0 24568 #define XGXSBLK4_LP_UP3_RESERVED0_BITS 5 24569 #define XGXSBLK4_LP_UP3_RESERVED0_SHIFT 11 24570 24571 /* XgxsBlk4 :: LP_UP3 :: last [10:10] */ 24572 #define XGXSBLK4_LP_UP3_LAST_MASK 0x0400 24573 #define XGXSBLK4_LP_UP3_LAST_ALIGN 0 24574 #define XGXSBLK4_LP_UP3_LAST_BITS 1 24575 #define XGXSBLK4_LP_UP3_LAST_SHIFT 10 24576 24577 /* XgxsBlk4 :: LP_UP3 :: dataRate_21GX4 [09:09] */ 24578 #define XGXSBLK4_LP_UP3_DATARATE_21GX4_MASK 0x0200 24579 #define XGXSBLK4_LP_UP3_DATARATE_21GX4_ALIGN 0 24580 #define XGXSBLK4_LP_UP3_DATARATE_21GX4_BITS 1 24581 #define XGXSBLK4_LP_UP3_DATARATE_21GX4_SHIFT 9 24582 24583 /* XgxsBlk4 :: LP_UP3 :: dataRate_25p45GX4 [08:08] */ 24584 #define XGXSBLK4_LP_UP3_DATARATE_25P45GX4_MASK 0x0100 24585 #define XGXSBLK4_LP_UP3_DATARATE_25P45GX4_ALIGN 0 24586 #define XGXSBLK4_LP_UP3_DATARATE_25P45GX4_BITS 1 24587 #define XGXSBLK4_LP_UP3_DATARATE_25P45GX4_SHIFT 8 24588 24589 /* XgxsBlk4 :: LP_UP3 :: reserved1 [07:02] */ 24590 #define XGXSBLK4_LP_UP3_RESERVED1_MASK 0x00fc 24591 #define XGXSBLK4_LP_UP3_RESERVED1_ALIGN 0 24592 #define XGXSBLK4_LP_UP3_RESERVED1_BITS 6 24593 #define XGXSBLK4_LP_UP3_RESERVED1_SHIFT 2 24594 24595 /* XgxsBlk4 :: LP_UP3 :: scramble_8B10B [01:01] */ 24596 #define XGXSBLK4_LP_UP3_SCRAMBLE_8B10B_MASK 0x0002 24597 #define XGXSBLK4_LP_UP3_SCRAMBLE_8B10B_ALIGN 0 24598 #define XGXSBLK4_LP_UP3_SCRAMBLE_8B10B_BITS 1 24599 #define XGXSBLK4_LP_UP3_SCRAMBLE_8B10B_SHIFT 1 24600 24601 /* XgxsBlk4 :: LP_UP3 :: HiGig2 [00:00] */ 24602 #define XGXSBLK4_LP_UP3_HIGIG2_MASK 0x0001 24603 #define XGXSBLK4_LP_UP3_HIGIG2_ALIGN 0 24604 #define XGXSBLK4_LP_UP3_HIGIG2_BITS 1 24605 #define XGXSBLK4_LP_UP3_HIGIG2_SHIFT 0 24606 24607 24608 /**************************************************************************** 24609 * Warpcore_USER_XgxsBlk5 24610 */ 24611 /**************************************************************************** 24612 * XgxsBlk5 :: parDet10GStatus 24613 */ 24614 /* union - case pdStatus0 [15:00] */ 24615 /* XgxsBlk5 :: parDet10GStatus :: pd_link [15:15] */ 24616 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LINK_MASK 0x8000 24617 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LINK_ALIGN 0 24618 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LINK_BITS 1 24619 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LINK_SHIFT 15 24620 24621 /* XgxsBlk5 :: parDet10GStatus :: pd_CX4_en [14:14] */ 24622 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_MASK 0x4000 24623 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_ALIGN 0 24624 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_BITS 1 24625 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_SHIFT 14 24626 24627 /* XgxsBlk5 :: parDet10GStatus :: pd_lssFaultCount_en [13:13] */ 24628 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_MASK 0x2000 24629 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_ALIGN 0 24630 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_BITS 1 24631 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_SHIFT 13 24632 24633 /* XgxsBlk5 :: parDet10GStatus :: pd_tunePll12g [12:12] */ 24634 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_MASK 0x1000 24635 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_ALIGN 0 24636 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_BITS 1 24637 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_SHIFT 12 24638 24639 /* XgxsBlk5 :: parDet10GStatus :: pd_tunePll10g [11:11] */ 24640 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_MASK 0x0800 24641 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_ALIGN 0 24642 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_BITS 1 24643 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_SHIFT 11 24644 24645 /* XgxsBlk5 :: parDet10GStatus :: pd_txdLaneOff [10:10] */ 24646 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_MASK 0x0400 24647 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_ALIGN 0 24648 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_BITS 1 24649 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_SHIFT 10 24650 24651 /* XgxsBlk5 :: parDet10GStatus :: pd_busy [09:09] */ 24652 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_MASK 0x0200 24653 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_ALIGN 0 24654 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_BITS 1 24655 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_SHIFT 9 24656 24657 /* XgxsBlk5 :: parDet10GStatus :: pd_park_an [08:08] */ 24658 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_MASK 0x0100 24659 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_ALIGN 0 24660 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_BITS 1 24661 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_SHIFT 8 24662 24663 /* XgxsBlk5 :: parDet10GStatus :: pd_lssFaultCount [07:04] */ 24664 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_MASK 0x00f0 24665 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_ALIGN 0 24666 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_BITS 4 24667 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_SHIFT 4 24668 24669 /* XgxsBlk5 :: parDet10GStatus :: rxSeqDone [03:00] */ 24670 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_MASK 0x000f 24671 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_ALIGN 0 24672 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_BITS 4 24673 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_SHIFT 0 24674 24675 24676 /* union - case pdStatus1 [15:00] */ 24677 /* XgxsBlk5 :: parDet10GStatus :: reserved0 [15:09] */ 24678 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_RESERVED0_MASK 0xfe00 24679 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_RESERVED0_ALIGN 0 24680 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_RESERVED0_BITS 7 24681 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_RESERVED0_SHIFT 9 24682 24683 /* XgxsBlk5 :: parDet10GStatus :: fail_lh [08:08] */ 24684 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_MASK 0x0100 24685 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_ALIGN 0 24686 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_BITS 1 24687 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_SHIFT 8 24688 24689 /* XgxsBlk5 :: parDet10GStatus :: complete_lh [07:07] */ 24690 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_MASK 0x0080 24691 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_ALIGN 0 24692 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_BITS 1 24693 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_SHIFT 7 24694 24695 /* XgxsBlk5 :: parDet10GStatus :: link12gretry_lh [06:06] */ 24696 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_MASK 0x0040 24697 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_ALIGN 0 24698 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_BITS 1 24699 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_SHIFT 6 24700 24701 /* XgxsBlk5 :: parDet10GStatus :: wait4link12g_lh [05:05] */ 24702 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_MASK 0x0020 24703 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_ALIGN 0 24704 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_BITS 1 24705 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_SHIFT 5 24706 24707 /* XgxsBlk5 :: parDet10GStatus :: samplefault_lh [04:04] */ 24708 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_MASK 0x0010 24709 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_ALIGN 0 24710 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_BITS 1 24711 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_SHIFT 4 24712 24713 /* XgxsBlk5 :: parDet10GStatus :: link10gretry_lh [03:03] */ 24714 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_MASK 0x0008 24715 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_ALIGN 0 24716 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_BITS 1 24717 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_SHIFT 3 24718 24719 /* XgxsBlk5 :: parDet10GStatus :: wait4link10g_lh [02:02] */ 24720 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_MASK 0x0004 24721 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_ALIGN 0 24722 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_BITS 1 24723 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_SHIFT 2 24724 24725 /* XgxsBlk5 :: parDet10GStatus :: wait4sigdet_lh [01:01] */ 24726 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_MASK 0x0002 24727 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_ALIGN 0 24728 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_BITS 1 24729 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_SHIFT 1 24730 24731 /* XgxsBlk5 :: parDet10GStatus :: wait4lock_lh [00:00] */ 24732 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_MASK 0x0001 24733 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_ALIGN 0 24734 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_BITS 1 24735 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_SHIFT 0 24736 24737 24738 24739 /**************************************************************************** 24740 * XgxsBlk5 :: parDet10GControl 24741 */ 24742 /* XgxsBlk5 :: parDet10GControl :: force_parDet10g_en [15:15] */ 24743 #define XGXSBLK5_PARDET10GCONTROL_FORCE_PARDET10G_EN_MASK 0x8000 24744 #define XGXSBLK5_PARDET10GCONTROL_FORCE_PARDET10G_EN_ALIGN 0 24745 #define XGXSBLK5_PARDET10GCONTROL_FORCE_PARDET10G_EN_BITS 1 24746 #define XGXSBLK5_PARDET10GCONTROL_FORCE_PARDET10G_EN_SHIFT 15 24747 24748 /* XgxsBlk5 :: parDet10GControl :: pd_cx4_init [14:14] */ 24749 #define XGXSBLK5_PARDET10GCONTROL_PD_CX4_INIT_MASK 0x4000 24750 #define XGXSBLK5_PARDET10GCONTROL_PD_CX4_INIT_ALIGN 0 24751 #define XGXSBLK5_PARDET10GCONTROL_PD_CX4_INIT_BITS 1 24752 #define XGXSBLK5_PARDET10GCONTROL_PD_CX4_INIT_SHIFT 14 24753 24754 /* XgxsBlk5 :: parDet10GControl :: pd_sw_overide [13:13] */ 24755 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_OVERIDE_MASK 0x2000 24756 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_OVERIDE_ALIGN 0 24757 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_OVERIDE_BITS 1 24758 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_OVERIDE_SHIFT 13 24759 24760 /* XgxsBlk5 :: parDet10GControl :: pd_sw_busy_an [12:12] */ 24761 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_BUSY_AN_MASK 0x1000 24762 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_BUSY_AN_ALIGN 0 24763 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_BUSY_AN_BITS 1 24764 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_BUSY_AN_SHIFT 12 24765 24766 /* XgxsBlk5 :: parDet10GControl :: pd_sw_CX4_en [11:11] */ 24767 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_CX4_EN_MASK 0x0800 24768 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_CX4_EN_ALIGN 0 24769 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_CX4_EN_BITS 1 24770 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_CX4_EN_SHIFT 11 24771 24772 /* XgxsBlk5 :: parDet10GControl :: pd_sw_tunePll12g [10:10] */ 24773 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL12G_MASK 0x0400 24774 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL12G_ALIGN 0 24775 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL12G_BITS 1 24776 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL12G_SHIFT 10 24777 24778 /* XgxsBlk5 :: parDet10GControl :: pd_sw_tunePll10g [09:09] */ 24779 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL10G_MASK 0x0200 24780 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL10G_ALIGN 0 24781 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL10G_BITS 1 24782 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL10G_SHIFT 9 24783 24784 /* XgxsBlk5 :: parDet10GControl :: pd_sw_lssFaultCount_en [08:08] */ 24785 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_MASK 0x0100 24786 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_ALIGN 0 24787 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_BITS 1 24788 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_SHIFT 8 24789 24790 /* XgxsBlk5 :: parDet10GControl :: pd_sw_txdOff [07:07] */ 24791 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TXDOFF_MASK 0x0080 24792 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TXDOFF_ALIGN 0 24793 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TXDOFF_BITS 1 24794 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TXDOFF_SHIFT 7 24795 24796 /* XgxsBlk5 :: parDet10GControl :: pd_12g_txdOn_disable [06:06] */ 24797 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_MASK 0x0040 24798 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_ALIGN 0 24799 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_BITS 1 24800 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_SHIFT 6 24801 24802 /* XgxsBlk5 :: parDet10GControl :: pd_12g_disable [05:05] */ 24803 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_DISABLE_MASK 0x0020 24804 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_DISABLE_ALIGN 0 24805 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_DISABLE_BITS 1 24806 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_DISABLE_SHIFT 5 24807 24808 /* XgxsBlk5 :: parDet10GControl :: pd_10g_txdOn_disable [04:04] */ 24809 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_MASK 0x0010 24810 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_ALIGN 0 24811 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_BITS 1 24812 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_SHIFT 4 24813 24814 /* XgxsBlk5 :: parDet10GControl :: pd_10g_disable [03:03] */ 24815 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_DISABLE_MASK 0x0008 24816 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_DISABLE_ALIGN 0 24817 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_DISABLE_BITS 1 24818 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_DISABLE_SHIFT 3 24819 24820 /* XgxsBlk5 :: parDet10GControl :: pd_stat_sel [02:02] */ 24821 #define XGXSBLK5_PARDET10GCONTROL_PD_STAT_SEL_MASK 0x0004 24822 #define XGXSBLK5_PARDET10GCONTROL_PD_STAT_SEL_ALIGN 0 24823 #define XGXSBLK5_PARDET10GCONTROL_PD_STAT_SEL_BITS 1 24824 #define XGXSBLK5_PARDET10GCONTROL_PD_STAT_SEL_SHIFT 2 24825 24826 /* XgxsBlk5 :: parDet10GControl :: pd_fast_timer_en [01:01] */ 24827 #define XGXSBLK5_PARDET10GCONTROL_PD_FAST_TIMER_EN_MASK 0x0002 24828 #define XGXSBLK5_PARDET10GCONTROL_PD_FAST_TIMER_EN_ALIGN 0 24829 #define XGXSBLK5_PARDET10GCONTROL_PD_FAST_TIMER_EN_BITS 1 24830 #define XGXSBLK5_PARDET10GCONTROL_PD_FAST_TIMER_EN_SHIFT 1 24831 24832 /* XgxsBlk5 :: parDet10GControl :: parDet10g_en [00:00] */ 24833 #define XGXSBLK5_PARDET10GCONTROL_PARDET10G_EN_MASK 0x0001 24834 #define XGXSBLK5_PARDET10GCONTROL_PARDET10G_EN_ALIGN 0 24835 #define XGXSBLK5_PARDET10GCONTROL_PARDET10G_EN_BITS 1 24836 #define XGXSBLK5_PARDET10GCONTROL_PARDET10G_EN_SHIFT 0 24837 24838 24839 /**************************************************************************** 24840 * XgxsBlk5 :: parDet10GSigDet 24841 */ 24842 /* XgxsBlk5 :: parDet10GSigDet :: pd_sd_count [15:00] */ 24843 #define XGXSBLK5_PARDET10GSIGDET_PD_SD_COUNT_MASK 0xffff 24844 #define XGXSBLK5_PARDET10GSIGDET_PD_SD_COUNT_ALIGN 0 24845 #define XGXSBLK5_PARDET10GSIGDET_PD_SD_COUNT_BITS 16 24846 #define XGXSBLK5_PARDET10GSIGDET_PD_SD_COUNT_SHIFT 0 24847 24848 24849 /**************************************************************************** 24850 * XgxsBlk5 :: parDet10GLink 24851 */ 24852 /* XgxsBlk5 :: parDet10GLink :: pd_link_count [15:00] */ 24853 #define XGXSBLK5_PARDET10GLINK_PD_LINK_COUNT_MASK 0xffff 24854 #define XGXSBLK5_PARDET10GLINK_PD_LINK_COUNT_ALIGN 0 24855 #define XGXSBLK5_PARDET10GLINK_PD_LINK_COUNT_BITS 16 24856 #define XGXSBLK5_PARDET10GLINK_PD_LINK_COUNT_SHIFT 0 24857 24858 24859 /**************************************************************************** 24860 * XgxsBlk5 :: parDet10GLostLink 24861 */ 24862 /* XgxsBlk5 :: parDet10GLostLink :: pd_lostlink_count [15:00] */ 24863 #define XGXSBLK5_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_MASK 0xffff 24864 #define XGXSBLK5_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_ALIGN 0 24865 #define XGXSBLK5_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_BITS 16 24866 #define XGXSBLK5_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_SHIFT 0 24867 24868 24869 /**************************************************************************** 24870 * XgxsBlk5 :: cl73Control1 24871 */ 24872 /* XgxsBlk5 :: cl73Control1 :: reserved0 [15:08] */ 24873 #define XGXSBLK5_CL73CONTROL1_RESERVED0_MASK 0xff00 24874 #define XGXSBLK5_CL73CONTROL1_RESERVED0_ALIGN 0 24875 #define XGXSBLK5_CL73CONTROL1_RESERVED0_BITS 8 24876 #define XGXSBLK5_CL73CONTROL1_RESERVED0_SHIFT 8 24877 24878 /* XgxsBlk5 :: cl73Control1 :: cl73_internal_10us_timer_val [07:00] */ 24879 #define XGXSBLK5_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_MASK 0x00ff 24880 #define XGXSBLK5_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_ALIGN 0 24881 #define XGXSBLK5_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_BITS 8 24882 #define XGXSBLK5_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_SHIFT 0 24883 24884 24885 /**************************************************************************** 24886 * XgxsBlk5 :: cl73Control2 24887 */ 24888 /* XgxsBlk5 :: cl73Control2 :: reserved0 [15:13] */ 24889 #define XGXSBLK5_CL73CONTROL2_RESERVED0_MASK 0xe000 24890 #define XGXSBLK5_CL73CONTROL2_RESERVED0_ALIGN 0 24891 #define XGXSBLK5_CL73CONTROL2_RESERVED0_BITS 3 24892 #define XGXSBLK5_CL73CONTROL2_RESERVED0_SHIFT 13 24893 24894 /* XgxsBlk5 :: cl73Control2 :: cl73_link_fail_inhibit_timer_val [12:00] */ 24895 #define XGXSBLK5_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_MASK 0x1fff 24896 #define XGXSBLK5_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_ALIGN 0 24897 #define XGXSBLK5_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_BITS 13 24898 #define XGXSBLK5_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_SHIFT 0 24899 24900 24901 /**************************************************************************** 24902 * XgxsBlk5 :: cl73Control3 24903 */ 24904 /* XgxsBlk5 :: cl73Control3 :: reserved0 [15:13] */ 24905 #define XGXSBLK5_CL73CONTROL3_RESERVED0_MASK 0xe000 24906 #define XGXSBLK5_CL73CONTROL3_RESERVED0_ALIGN 0 24907 #define XGXSBLK5_CL73CONTROL3_RESERVED0_BITS 3 24908 #define XGXSBLK5_CL73CONTROL3_RESERVED0_SHIFT 13 24909 24910 /* XgxsBlk5 :: cl73Control3 :: cl73_an_wait_timer_val [12:00] */ 24911 #define XGXSBLK5_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_MASK 0x1fff 24912 #define XGXSBLK5_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_ALIGN 0 24913 #define XGXSBLK5_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_BITS 13 24914 #define XGXSBLK5_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_SHIFT 0 24915 24916 24917 /**************************************************************************** 24918 * XgxsBlk5 :: cl73Control4 24919 */ 24920 /* XgxsBlk5 :: cl73Control4 :: reserved0 [15:13] */ 24921 #define XGXSBLK5_CL73CONTROL4_RESERVED0_MASK 0xe000 24922 #define XGXSBLK5_CL73CONTROL4_RESERVED0_ALIGN 0 24923 #define XGXSBLK5_CL73CONTROL4_RESERVED0_BITS 3 24924 #define XGXSBLK5_CL73CONTROL4_RESERVED0_SHIFT 13 24925 24926 /* XgxsBlk5 :: cl73Control4 :: cl73_break_link_timer_val [12:00] */ 24927 #define XGXSBLK5_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_MASK 0x1fff 24928 #define XGXSBLK5_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_ALIGN 0 24929 #define XGXSBLK5_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_BITS 13 24930 #define XGXSBLK5_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_SHIFT 0 24931 24932 24933 /**************************************************************************** 24934 * XgxsBlk5 :: cl73Control5 24935 */ 24936 /* XgxsBlk5 :: cl73Control5 :: reserved0 [15:13] */ 24937 #define XGXSBLK5_CL73CONTROL5_RESERVED0_MASK 0xe000 24938 #define XGXSBLK5_CL73CONTROL5_RESERVED0_ALIGN 0 24939 #define XGXSBLK5_CL73CONTROL5_RESERVED0_BITS 3 24940 #define XGXSBLK5_CL73CONTROL5_RESERVED0_SHIFT 13 24941 24942 /* XgxsBlk5 :: cl73Control5 :: cl73_link_fail_inhibit_timer_bam_val [12:00] */ 24943 #define XGXSBLK5_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_MASK 0x1fff 24944 #define XGXSBLK5_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_ALIGN 0 24945 #define XGXSBLK5_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_BITS 13 24946 #define XGXSBLK5_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_SHIFT 0 24947 24948 24949 /**************************************************************************** 24950 * XgxsBlk5 :: cl73Control6 24951 */ 24952 /* XgxsBlk5 :: cl73Control6 :: reserved0 [15:13] */ 24953 #define XGXSBLK5_CL73CONTROL6_RESERVED0_MASK 0xe000 24954 #define XGXSBLK5_CL73CONTROL6_RESERVED0_ALIGN 0 24955 #define XGXSBLK5_CL73CONTROL6_RESERVED0_BITS 3 24956 #define XGXSBLK5_CL73CONTROL6_RESERVED0_SHIFT 13 24957 24958 /* XgxsBlk5 :: cl73Control6 :: cl73_ignore_link_timer_val [12:00] */ 24959 #define XGXSBLK5_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_MASK 0x1fff 24960 #define XGXSBLK5_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_ALIGN 0 24961 #define XGXSBLK5_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_BITS 13 24962 #define XGXSBLK5_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_SHIFT 0 24963 24964 24965 /**************************************************************************** 24966 * XgxsBlk5 :: cl73DmeTmrs 24967 */ 24968 /* XgxsBlk5 :: cl73DmeTmrs :: cl73_dme_page_test_max_cnt_val [15:08] */ 24969 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_MASK 0xff00 24970 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_ALIGN 0 24971 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_BITS 8 24972 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_SHIFT 8 24973 24974 /* XgxsBlk5 :: cl73DmeTmrs :: cl73_dme_page_test_min_cnt_val [07:00] */ 24975 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_MASK 0x00ff 24976 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_ALIGN 0 24977 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_BITS 8 24978 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_SHIFT 0 24979 24980 24981 /**************************************************************************** 24982 * XgxsBlk5 :: xgxsStatus4 24983 */ 24984 /* XgxsBlk5 :: xgxsStatus4 :: reserved0 [15:15] */ 24985 #define XGXSBLK5_XGXSSTATUS4_RESERVED0_MASK 0x8000 24986 #define XGXSBLK5_XGXSSTATUS4_RESERVED0_ALIGN 0 24987 #define XGXSBLK5_XGXSSTATUS4_RESERVED0_BITS 1 24988 #define XGXSBLK5_XGXSSTATUS4_RESERVED0_SHIFT 15 24989 24990 /* XgxsBlk5 :: xgxsStatus4 :: sgmii_mode [14:14] */ 24991 #define XGXSBLK5_XGXSSTATUS4_SGMII_MODE_MASK 0x4000 24992 #define XGXSBLK5_XGXSSTATUS4_SGMII_MODE_ALIGN 0 24993 #define XGXSBLK5_XGXSSTATUS4_SGMII_MODE_BITS 1 24994 #define XGXSBLK5_XGXSSTATUS4_SGMII_MODE_SHIFT 14 24995 24996 /* XgxsBlk5 :: xgxsStatus4 :: link10g [13:13] */ 24997 #define XGXSBLK5_XGXSSTATUS4_LINK10G_MASK 0x2000 24998 #define XGXSBLK5_XGXSSTATUS4_LINK10G_ALIGN 0 24999 #define XGXSBLK5_XGXSSTATUS4_LINK10G_BITS 1 25000 #define XGXSBLK5_XGXSSTATUS4_LINK10G_SHIFT 13 25001 25002 /* XgxsBlk5 :: xgxsStatus4 :: link_status [12:12] */ 25003 #define XGXSBLK5_XGXSSTATUS4_LINK_STATUS_MASK 0x1000 25004 #define XGXSBLK5_XGXSSTATUS4_LINK_STATUS_ALIGN 0 25005 #define XGXSBLK5_XGXSSTATUS4_LINK_STATUS_BITS 1 25006 #define XGXSBLK5_XGXSSTATUS4_LINK_STATUS_SHIFT 12 25007 25008 /* XgxsBlk5 :: xgxsStatus4 :: pll_mode_afe [11:08] */ 25009 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_MASK 0x0f00 25010 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_ALIGN 0 25011 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_BITS 4 25012 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_SHIFT 8 25013 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div32 0 25014 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div36 1 25015 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div40 2 25016 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div42 3 25017 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div48 4 25018 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div50 5 25019 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div52 6 25020 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div54 7 25021 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div60 8 25022 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div64 9 25023 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div66 10 25024 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div68 11 25025 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div70 12 25026 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div80 13 25027 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div92 14 25028 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div100 15 25029 25030 /* XgxsBlk5 :: xgxsStatus4 :: reserved1 [07:06] */ 25031 #define XGXSBLK5_XGXSSTATUS4_RESERVED1_MASK 0x00c0 25032 #define XGXSBLK5_XGXSSTATUS4_RESERVED1_ALIGN 0 25033 #define XGXSBLK5_XGXSSTATUS4_RESERVED1_BITS 2 25034 #define XGXSBLK5_XGXSSTATUS4_RESERVED1_SHIFT 6 25035 25036 /* XgxsBlk5 :: xgxsStatus4 :: actual_speed_ln0 [05:00] */ 25037 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_MASK 0x003f 25038 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_ALIGN 0 25039 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_BITS 6 25040 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_SHIFT 0 25041 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10M 0 25042 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_100M 1 25043 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_1G 2 25044 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_2p5G 3 25045 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G_X4 4 25046 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_6G_X4 5 25047 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_HiG 6 25048 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_CX4 7 25049 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12G_HiG 8 25050 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p5G_X4 9 25051 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_13G_X4 10 25052 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_15G_X4 11 25053 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_16G_X4 12 25054 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_1G_KX 13 25055 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_KX4 14 25056 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_KR 15 25057 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G 16 25058 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_6p4G 17 25059 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_X4 18 25060 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_21G_X4 19 25061 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_25G_X4 20 25062 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_HiG_DXGXS 21 25063 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_DXGXS 22 25064 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10p5G_HiG_DXGXS 23 25065 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10p5G_DXGXS 24 25066 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p773G_HiG_DXGXS 25 25067 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p773G_DXGXS 26 25068 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_XFI 27 25069 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_40G 28 25070 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_HiG_DXGXS 29 25071 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_DXGXS 30 25072 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_SFI 31 25073 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_31p5G 32 25074 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_32p7G 33 25075 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_SCR 34 25076 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_HiG_DXGXS_SCR 35 25077 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_DXGXS_SCR 36 25078 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12G_R2 37 25079 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_X2 38 25080 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_40G_KR4 39 25081 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_40G_CR4 40 25082 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_100G_CR10 41 25083 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_15p75G_DXGXS 44 25084 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_KR2 57 25085 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_CR2 58 25086 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_3125_PCSBYPASS 60 25087 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_6250_PCSBYPASS 61 25088 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10p3125_PCSBYPASS 62 25089 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10p9375_PCSBYPASS 63 25090 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12500_PCSBYPASS 64 25091 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_11500_PCSBYPASS 65 25092 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_1250_PCSBYPASS 66 25093 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5750_PCSBYPASS 67 25094 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_NON_CANNED_PCSBYPASS 68 25095 25096 /**************************************************************************** 25097 * XgxsBlk5 :: xgxsStatus5 25098 */ 25099 /* XgxsBlk5 :: xgxsStatus5 :: tx1g_mode_ln3 [15:14] */ 25100 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_MASK 0xc000 25101 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_ALIGN 0 25102 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_BITS 2 25103 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_SHIFT 14 25104 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_SWSDR_div2 0 25105 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_SWSDR_div1 1 25106 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_DWSDR_div2 2 25107 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_DWSDR_div1 3 25108 25109 /* XgxsBlk5 :: xgxsStatus5 :: tx1g_mode_ln2 [13:12] */ 25110 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_MASK 0x3000 25111 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_ALIGN 0 25112 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_BITS 2 25113 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_SHIFT 12 25114 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_SWSDR_div2 0 25115 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_SWSDR_div1 1 25116 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_DWSDR_div2 2 25117 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_DWSDR_div1 3 25118 25119 /* XgxsBlk5 :: xgxsStatus5 :: tx1g_mode_ln1 [11:10] */ 25120 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_MASK 0x0c00 25121 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_ALIGN 0 25122 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_BITS 2 25123 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_SHIFT 10 25124 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_SWSDR_div2 0 25125 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_SWSDR_div1 1 25126 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_DWSDR_div2 2 25127 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_DWSDR_div1 3 25128 25129 /* XgxsBlk5 :: xgxsStatus5 :: tx1g_mode_ln0 [09:08] */ 25130 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_MASK 0x0300 25131 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_ALIGN 0 25132 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_BITS 2 25133 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_SHIFT 8 25134 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_SWSDR_div2 0 25135 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_SWSDR_div1 1 25136 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_DWSDR_div2 2 25137 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_DWSDR_div1 3 25138 25139 /* XgxsBlk5 :: xgxsStatus5 :: rx1g_mode_ln3 [07:06] */ 25140 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_MASK 0x00c0 25141 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_ALIGN 0 25142 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_BITS 2 25143 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_SHIFT 6 25144 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_SWSDR_div2 0 25145 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_SWSDR_div1 1 25146 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_DWSDR_div2 2 25147 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_DWSDR_div1 3 25148 25149 /* XgxsBlk5 :: xgxsStatus5 :: rx1g_mode_ln2 [05:04] */ 25150 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_MASK 0x0030 25151 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_ALIGN 0 25152 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_BITS 2 25153 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_SHIFT 4 25154 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_SWSDR_div2 0 25155 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_SWSDR_div1 1 25156 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_DWSDR_div2 2 25157 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_DWSDR_div1 3 25158 25159 /* XgxsBlk5 :: xgxsStatus5 :: rx1g_mode_ln1 [03:02] */ 25160 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_MASK 0x000c 25161 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_ALIGN 0 25162 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_BITS 2 25163 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_SHIFT 2 25164 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_SWSDR_div2 0 25165 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_SWSDR_div1 1 25166 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_DWSDR_div2 2 25167 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_DWSDR_div1 3 25168 25169 /* XgxsBlk5 :: xgxsStatus5 :: rx1g_mode_ln0 [01:00] */ 25170 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_MASK 0x0003 25171 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_ALIGN 0 25172 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_BITS 2 25173 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_SHIFT 0 25174 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_SWSDR_div2 0 25175 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_SWSDR_div1 1 25176 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_DWSDR_div2 2 25177 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_DWSDR_div1 3 25178 25179 25180 /**************************************************************************** 25181 * XgxsBlk5 :: parDet10GControl2 25182 */ 25183 /* XgxsBlk5 :: parDet10GControl2 :: reserved0 [15:04] */ 25184 #define XGXSBLK5_PARDET10GCONTROL2_RESERVED0_MASK 0xfff0 25185 #define XGXSBLK5_PARDET10GCONTROL2_RESERVED0_ALIGN 0 25186 #define XGXSBLK5_PARDET10GCONTROL2_RESERVED0_BITS 12 25187 #define XGXSBLK5_PARDET10GCONTROL2_RESERVED0_SHIFT 4 25188 25189 /* XgxsBlk5 :: parDet10GControl2 :: pd_parkFail [03:03] */ 25190 #define XGXSBLK5_PARDET10GCONTROL2_PD_PARKFAIL_MASK 0x0008 25191 #define XGXSBLK5_PARDET10GCONTROL2_PD_PARKFAIL_ALIGN 0 25192 #define XGXSBLK5_PARDET10GCONTROL2_PD_PARKFAIL_BITS 1 25193 #define XGXSBLK5_PARDET10GCONTROL2_PD_PARKFAIL_SHIFT 3 25194 25195 /* XgxsBlk5 :: parDet10GControl2 :: pd_useLinkStatus [02:02] */ 25196 #define XGXSBLK5_PARDET10GCONTROL2_PD_USELINKSTATUS_MASK 0x0004 25197 #define XGXSBLK5_PARDET10GCONTROL2_PD_USELINKSTATUS_ALIGN 0 25198 #define XGXSBLK5_PARDET10GCONTROL2_PD_USELINKSTATUS_BITS 1 25199 #define XGXSBLK5_PARDET10GCONTROL2_PD_USELINKSTATUS_SHIFT 2 25200 25201 /* XgxsBlk5 :: parDet10GControl2 :: pd_cl73_couple_dis [01:01] */ 25202 #define XGXSBLK5_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_MASK 0x0002 25203 #define XGXSBLK5_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_ALIGN 0 25204 #define XGXSBLK5_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_BITS 1 25205 #define XGXSBLK5_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_SHIFT 1 25206 25207 /* XgxsBlk5 :: parDet10GControl2 :: pd_IgnoreLink_dis [00:00] */ 25208 #define XGXSBLK5_PARDET10GCONTROL2_PD_IGNORELINK_DIS_MASK 0x0001 25209 #define XGXSBLK5_PARDET10GCONTROL2_PD_IGNORELINK_DIS_ALIGN 0 25210 #define XGXSBLK5_PARDET10GCONTROL2_PD_IGNORELINK_DIS_BITS 1 25211 #define XGXSBLK5_PARDET10GCONTROL2_PD_IGNORELINK_DIS_SHIFT 0 25212 25213 25214 /**************************************************************************** 25215 * Warpcore_USER_XgxsBlk6 25216 */ 25217 /**************************************************************************** 25218 * XgxsBlk6 :: xgxsX2Control1 25219 */ 25220 /* XgxsBlk6 :: xgxsX2Control1 :: dual_xgxs_mode [15:14] */ 25221 #define XGXSBLK6_XGXSX2CONTROL1_DUAL_XGXS_MODE_MASK 0xc000 25222 #define XGXSBLK6_XGXSX2CONTROL1_DUAL_XGXS_MODE_ALIGN 0 25223 #define XGXSBLK6_XGXSX2CONTROL1_DUAL_XGXS_MODE_BITS 2 25224 #define XGXSBLK6_XGXSX2CONTROL1_DUAL_XGXS_MODE_SHIFT 14 25225 25226 /* XgxsBlk6 :: xgxsX2Control1 :: reserved0 [13:07] */ 25227 #define XGXSBLK6_XGXSX2CONTROL1_RESERVED0_MASK 0x3f80 25228 #define XGXSBLK6_XGXSX2CONTROL1_RESERVED0_ALIGN 0 25229 #define XGXSBLK6_XGXSX2CONTROL1_RESERVED0_BITS 7 25230 #define XGXSBLK6_XGXSX2CONTROL1_RESERVED0_SHIFT 7 25231 25232 /* XgxsBlk6 :: xgxsX2Control1 :: tx10g_fifo_manual_reset [06:05] */ 25233 #define XGXSBLK6_XGXSX2CONTROL1_TX10G_FIFO_MANUAL_RESET_MASK 0x0060 25234 #define XGXSBLK6_XGXSX2CONTROL1_TX10G_FIFO_MANUAL_RESET_ALIGN 0 25235 #define XGXSBLK6_XGXSX2CONTROL1_TX10G_FIFO_MANUAL_RESET_BITS 2 25236 #define XGXSBLK6_XGXSX2CONTROL1_TX10G_FIFO_MANUAL_RESET_SHIFT 5 25237 25238 /* XgxsBlk6 :: xgxsX2Control1 :: xgxsX2_outdiv_ctrl_override [04:04] */ 25239 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_OVERRIDE_MASK 0x0010 25240 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_OVERRIDE_ALIGN 0 25241 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_OVERRIDE_BITS 1 25242 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_OVERRIDE_SHIFT 4 25243 25244 /* XgxsBlk6 :: xgxsX2Control1 :: xgxsX2_outdiv_ctrl_val [03:03] */ 25245 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_VAL_MASK 0x0008 25246 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_VAL_ALIGN 0 25247 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_VAL_BITS 1 25248 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_VAL_SHIFT 3 25249 25250 /* XgxsBlk6 :: xgxsX2Control1 :: xgxsX2_1_en_mdio_ctrl [02:02] */ 25251 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_1_EN_MDIO_CTRL_MASK 0x0004 25252 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_1_EN_MDIO_CTRL_ALIGN 0 25253 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_1_EN_MDIO_CTRL_BITS 1 25254 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_1_EN_MDIO_CTRL_SHIFT 2 25255 25256 /* XgxsBlk6 :: xgxsX2Control1 :: xgxsX2_en_override [01:01] */ 25257 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_OVERRIDE_MASK 0x0002 25258 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_OVERRIDE_ALIGN 0 25259 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_OVERRIDE_BITS 1 25260 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_OVERRIDE_SHIFT 1 25261 25262 /* XgxsBlk6 :: xgxsX2Control1 :: xgxsX2_en_value [00:00] */ 25263 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_VALUE_MASK 0x0001 25264 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_VALUE_ALIGN 0 25265 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_VALUE_BITS 1 25266 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_VALUE_SHIFT 0 25267 25268 25269 /**************************************************************************** 25270 * XgxsBlk6 :: xgxsX2Control2 25271 */ 25272 /* XgxsBlk6 :: xgxsX2Control2 :: reserved0 [15:14] */ 25273 #define XGXSBLK6_XGXSX2CONTROL2_RESERVED0_MASK 0xc000 25274 #define XGXSBLK6_XGXSX2CONTROL2_RESERVED0_ALIGN 0 25275 #define XGXSBLK6_XGXSX2CONTROL2_RESERVED0_BITS 2 25276 #define XGXSBLK6_XGXSX2CONTROL2_RESERVED0_SHIFT 14 25277 25278 /* XgxsBlk6 :: xgxsX2Control2 :: reserved0 [14] */ 25279 #define XGXSBLK6_XGXSX2CONTROL2_100G_BIT_MASK 0x4000 25280 #define XGXSBLK6_XGXSX2CONTROL2_100G_BIT_ALIGN 0 25281 #define XGXSBLK6_XGXSX2CONTROL2_100G_BIT_BITS 1 25282 #define XGXSBLK6_XGXSX2CONTROL2_100G_BIT_SHIFT 14 25283 25284 /* XgxsBlk6 :: xgxsX2Control2 :: txckout33_override [13:13] */ 25285 #define XGXSBLK6_XGXSX2CONTROL2_TXCKOUT33_OVERRIDE_MASK 0x2000 25286 #define XGXSBLK6_XGXSX2CONTROL2_TXCKOUT33_OVERRIDE_ALIGN 0 25287 #define XGXSBLK6_XGXSX2CONTROL2_TXCKOUT33_OVERRIDE_BITS 1 25288 #define XGXSBLK6_XGXSX2CONTROL2_TXCKOUT33_OVERRIDE_SHIFT 13 25289 25290 /* XgxsBlk6 :: xgxsX2Control2 :: rx_wclk20_sel [12:12] */ 25291 #define XGXSBLK6_XGXSX2CONTROL2_RX_WCLK20_SEL_MASK 0x1000 25292 #define XGXSBLK6_XGXSX2CONTROL2_RX_WCLK20_SEL_ALIGN 0 25293 #define XGXSBLK6_XGXSX2CONTROL2_RX_WCLK20_SEL_BITS 1 25294 #define XGXSBLK6_XGXSX2CONTROL2_RX_WCLK20_SEL_SHIFT 12 25295 25296 /* XgxsBlk6 :: xgxsX2Control2 :: mac_inf_rxck_override [11:11] */ 25297 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_RXCK_OVERRIDE_MASK 0x0800 25298 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_RXCK_OVERRIDE_ALIGN 0 25299 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_RXCK_OVERRIDE_BITS 1 25300 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_RXCK_OVERRIDE_SHIFT 11 25301 25302 /* XgxsBlk6 :: xgxsX2Control2 :: mac_inf_rxck_sel [10:09] */ 25303 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_RXCK_SEL_MASK 0x0600 25304 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_RXCK_SEL_ALIGN 0 25305 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_RXCK_SEL_BITS 2 25306 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_RXCK_SEL_SHIFT 9 25307 25308 /* XgxsBlk6 :: xgxsX2Control2 :: mac_inf_txck_sel [08:05] */ 25309 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_TXCK_SEL_MASK 0x01e0 25310 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_TXCK_SEL_ALIGN 0 25311 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_TXCK_SEL_BITS 4 25312 #define XGXSBLK6_XGXSX2CONTROL2_MAC_INF_TXCK_SEL_SHIFT 5 25313 25314 /* XgxsBlk6 :: xgxsX2Control2 :: xgxsX2_ba_dataout_cya [04:04] */ 25315 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_DATAOUT_CYA_MASK 0x0010 25316 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_DATAOUT_CYA_ALIGN 0 25317 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_DATAOUT_CYA_BITS 1 25318 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_DATAOUT_CYA_SHIFT 4 25319 25320 /* XgxsBlk6 :: xgxsX2Control2 :: xgxsX2_ba_sync_status_cya [03:03] */ 25321 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_SYNC_STATUS_CYA_MASK 0x0008 25322 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_SYNC_STATUS_CYA_ALIGN 0 25323 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_SYNC_STATUS_CYA_BITS 1 25324 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_SYNC_STATUS_CYA_SHIFT 3 25325 25326 /* XgxsBlk6 :: xgxsX2Control2 :: xgxs_ba_link_force [02:02] */ 25327 #define XGXSBLK6_XGXSX2CONTROL2_XGXS_BA_LINK_FORCE_MASK 0x0004 25328 #define XGXSBLK6_XGXSX2CONTROL2_XGXS_BA_LINK_FORCE_ALIGN 0 25329 #define XGXSBLK6_XGXSX2CONTROL2_XGXS_BA_LINK_FORCE_BITS 1 25330 #define XGXSBLK6_XGXSX2CONTROL2_XGXS_BA_LINK_FORCE_SHIFT 2 25331 25332 /* XgxsBlk6 :: xgxsX2Control2 :: xgxsX2_ba_link_en [01:01] */ 25333 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_LINK_EN_MASK 0x0002 25334 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_LINK_EN_ALIGN 0 25335 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_LINK_EN_BITS 1 25336 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_LINK_EN_SHIFT 1 25337 25338 /* XgxsBlk6 :: xgxsX2Control2 :: xgxsX2_ba_hyst_en [00:00] */ 25339 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_HYST_EN_MASK 0x0001 25340 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_HYST_EN_ALIGN 0 25341 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_HYST_EN_BITS 1 25342 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_HYST_EN_SHIFT 0 25343 25344 25345 /**************************************************************************** 25346 * XgxsBlk6 :: xgxsX2Control3 25347 */ 25348 /* XgxsBlk6 :: xgxsX2Control3 :: reserved0 [15:03] */ 25349 #define XGXSBLK6_XGXSX2CONTROL3_RESERVED0_MASK 0xfff8 25350 #define XGXSBLK6_XGXSX2CONTROL3_RESERVED0_ALIGN 0 25351 #define XGXSBLK6_XGXSX2CONTROL3_RESERVED0_BITS 13 25352 #define XGXSBLK6_XGXSX2CONTROL3_RESERVED0_SHIFT 3 25353 25354 /* XgxsBlk6 :: xgxsX2Control3 :: port_mode_sel [02:00] */ 25355 #define XGXSBLK6_XGXSX2CONTROL3_PORT_MODE_SEL_MASK 0x0007 25356 #define XGXSBLK6_XGXSX2CONTROL3_PORT_MODE_SEL_ALIGN 0 25357 #define XGXSBLK6_XGXSX2CONTROL3_PORT_MODE_SEL_BITS 3 25358 #define XGXSBLK6_XGXSX2CONTROL3_PORT_MODE_SEL_SHIFT 0 25359 25360 25361 /**************************************************************************** 25362 * XgxsBlk6 :: xgxsX2Status1 25363 */ 25364 /* XgxsBlk6 :: xgxsX2Status1 :: reserved0 [15:04] */ 25365 #define XGXSBLK6_XGXSX2STATUS1_RESERVED0_MASK 0xfff0 25366 #define XGXSBLK6_XGXSX2STATUS1_RESERVED0_ALIGN 0 25367 #define XGXSBLK6_XGXSX2STATUS1_RESERVED0_BITS 12 25368 #define XGXSBLK6_XGXSX2STATUS1_RESERVED0_SHIFT 4 25369 25370 /* XgxsBlk6 :: xgxsX2Status1 :: xgxsX2_ba_skew_status [03:00] */ 25371 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_MASK 0x000f 25372 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_ALIGN 0 25373 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_BITS 4 25374 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_SHIFT 0 25375 25376 25377 /**************************************************************************** 25378 * XgxsBlk6 :: xgxsX2Test1 25379 */ 25380 /* XgxsBlk6 :: xgxsX2Test1 :: reserved0 [15:06] */ 25381 #define XGXSBLK6_XGXSX2TEST1_RESERVED0_MASK 0xffc0 25382 #define XGXSBLK6_XGXSX2TEST1_RESERVED0_ALIGN 0 25383 #define XGXSBLK6_XGXSX2TEST1_RESERVED0_BITS 10 25384 #define XGXSBLK6_XGXSX2TEST1_RESERVED0_SHIFT 6 25385 25386 /* XgxsBlk6 :: xgxsX2Test1 :: xgxsX2_ba_blkln_sel [05:03] */ 25387 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_BLKLN_SEL_MASK 0x0038 25388 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_BLKLN_SEL_ALIGN 0 25389 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_BLKLN_SEL_BITS 3 25390 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_BLKLN_SEL_SHIFT 3 25391 25392 /* XgxsBlk6 :: xgxsX2Test1 :: xgxsX2_ba_tstsel [02:00] */ 25393 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_TSTSEL_MASK 0x0007 25394 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_TSTSEL_ALIGN 0 25395 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_TSTSEL_BITS 3 25396 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_TSTSEL_SHIFT 0 25397 25398 25399 /**************************************************************************** 25400 * XgxsBlk6 :: bpmControl 25401 */ 25402 /* XgxsBlk6 :: bpmControl :: bpm_link_stable_timer_val [15:09] */ 25403 #define XGXSBLK6_BPMCONTROL_BPM_LINK_STABLE_TIMER_VAL_MASK 0xfe00 25404 #define XGXSBLK6_BPMCONTROL_BPM_LINK_STABLE_TIMER_VAL_ALIGN 0 25405 #define XGXSBLK6_BPMCONTROL_BPM_LINK_STABLE_TIMER_VAL_BITS 7 25406 #define XGXSBLK6_BPMCONTROL_BPM_LINK_STABLE_TIMER_VAL_SHIFT 9 25407 25408 /* XgxsBlk6 :: bpmControl :: reserved0 [08:02] */ 25409 #define XGXSBLK6_BPMCONTROL_RESERVED0_MASK 0x01fc 25410 #define XGXSBLK6_BPMCONTROL_RESERVED0_ALIGN 0 25411 #define XGXSBLK6_BPMCONTROL_RESERVED0_BITS 7 25412 #define XGXSBLK6_BPMCONTROL_RESERVED0_SHIFT 2 25413 25414 /* XgxsBlk6 :: bpmControl :: bpm_tx_squelch_en [01:01] */ 25415 #define XGXSBLK6_BPMCONTROL_BPM_TX_SQUELCH_EN_MASK 0x0002 25416 #define XGXSBLK6_BPMCONTROL_BPM_TX_SQUELCH_EN_ALIGN 0 25417 #define XGXSBLK6_BPMCONTROL_BPM_TX_SQUELCH_EN_BITS 1 25418 #define XGXSBLK6_BPMCONTROL_BPM_TX_SQUELCH_EN_SHIFT 1 25419 25420 /* XgxsBlk6 :: bpmControl :: bpm_mode [00:00] */ 25421 #define XGXSBLK6_BPMCONTROL_BPM_MODE_MASK 0x0001 25422 #define XGXSBLK6_BPMCONTROL_BPM_MODE_ALIGN 0 25423 #define XGXSBLK6_BPMCONTROL_BPM_MODE_BITS 1 25424 #define XGXSBLK6_BPMCONTROL_BPM_MODE_SHIFT 0 25425 25426 25427 /**************************************************************************** 25428 * XgxsBlk6 :: bpmStatus 25429 */ 25430 /* XgxsBlk6 :: bpmStatus :: reserved0 [15:02] */ 25431 #define XGXSBLK6_BPMSTATUS_RESERVED0_MASK 0xfffc 25432 #define XGXSBLK6_BPMSTATUS_RESERVED0_ALIGN 0 25433 #define XGXSBLK6_BPMSTATUS_RESERVED0_BITS 14 25434 #define XGXSBLK6_BPMSTATUS_RESERVED0_SHIFT 2 25435 25436 /* XgxsBlk6 :: bpmStatus :: bpm_link10g_status [01:01] */ 25437 #define XGXSBLK6_BPMSTATUS_BPM_LINK10G_STATUS_MASK 0x0002 25438 #define XGXSBLK6_BPMSTATUS_BPM_LINK10G_STATUS_ALIGN 0 25439 #define XGXSBLK6_BPMSTATUS_BPM_LINK10G_STATUS_BITS 1 25440 #define XGXSBLK6_BPMSTATUS_BPM_LINK10G_STATUS_SHIFT 1 25441 25442 /* XgxsBlk6 :: bpmStatus :: bpm_pd_fault [00:00] */ 25443 #define XGXSBLK6_BPMSTATUS_BPM_PD_FAULT_MASK 0x0001 25444 #define XGXSBLK6_BPMSTATUS_BPM_PD_FAULT_ALIGN 0 25445 #define XGXSBLK6_BPMSTATUS_BPM_PD_FAULT_BITS 1 25446 #define XGXSBLK6_BPMSTATUS_BPM_PD_FAULT_SHIFT 0 25447 25448 25449 /**************************************************************************** 25450 * XgxsBlk6 :: bpm10GTimer 25451 */ 25452 /* XgxsBlk6 :: bpm10GTimer :: bpm_10g_timer_val [15:00] */ 25453 #define XGXSBLK6_BPM10GTIMER_BPM_10G_TIMER_VAL_MASK 0xffff 25454 #define XGXSBLK6_BPM10GTIMER_BPM_10G_TIMER_VAL_ALIGN 0 25455 #define XGXSBLK6_BPM10GTIMER_BPM_10G_TIMER_VAL_BITS 16 25456 #define XGXSBLK6_BPM10GTIMER_BPM_10G_TIMER_VAL_SHIFT 0 25457 25458 25459 /**************************************************************************** 25460 * XgxsBlk6 :: bpm1GTimer 25461 */ 25462 /* XgxsBlk6 :: bpm1GTimer :: bpm_1g_timer_val [15:00] */ 25463 #define XGXSBLK6_BPM1GTIMER_BPM_1G_TIMER_VAL_MASK 0xffff 25464 #define XGXSBLK6_BPM1GTIMER_BPM_1G_TIMER_VAL_ALIGN 0 25465 #define XGXSBLK6_BPM1GTIMER_BPM_1G_TIMER_VAL_BITS 16 25466 #define XGXSBLK6_BPM1GTIMER_BPM_1G_TIMER_VAL_SHIFT 0 25467 25468 25469 /**************************************************************************** 25470 * XgxsBlk6 :: bpmTxDisTimer 25471 */ 25472 /* XgxsBlk6 :: bpmTxDisTimer :: reserved0 [15:13] */ 25473 #define XGXSBLK6_BPMTXDISTIMER_RESERVED0_MASK 0xe000 25474 #define XGXSBLK6_BPMTXDISTIMER_RESERVED0_ALIGN 0 25475 #define XGXSBLK6_BPMTXDISTIMER_RESERVED0_BITS 3 25476 #define XGXSBLK6_BPMTXDISTIMER_RESERVED0_SHIFT 13 25477 25478 /* XgxsBlk6 :: bpmTxDisTimer :: bpm_txdis_timer_val [12:00] */ 25479 #define XGXSBLK6_BPMTXDISTIMER_BPM_TXDIS_TIMER_VAL_MASK 0x1fff 25480 #define XGXSBLK6_BPMTXDISTIMER_BPM_TXDIS_TIMER_VAL_ALIGN 0 25481 #define XGXSBLK6_BPMTXDISTIMER_BPM_TXDIS_TIMER_VAL_BITS 13 25482 #define XGXSBLK6_BPMTXDISTIMER_BPM_TXDIS_TIMER_VAL_SHIFT 0 25483 25484 25485 /**************************************************************************** 25486 * XgxsBlk6 :: parDetINDSigDet 25487 */ 25488 /* XgxsBlk6 :: parDetINDSigDet :: pd_ind_sd_count [15:00] */ 25489 #define XGXSBLK6_PARDETINDSIGDET_PD_IND_SD_COUNT_MASK 0xffff 25490 #define XGXSBLK6_PARDETINDSIGDET_PD_IND_SD_COUNT_ALIGN 0 25491 #define XGXSBLK6_PARDETINDSIGDET_PD_IND_SD_COUNT_BITS 16 25492 #define XGXSBLK6_PARDETINDSIGDET_PD_IND_SD_COUNT_SHIFT 0 25493 25494 25495 /**************************************************************************** 25496 * XgxsBlk6 :: parDetINDLink 25497 */ 25498 /* XgxsBlk6 :: parDetINDLink :: pd_ind_link_count [15:00] */ 25499 #define XGXSBLK6_PARDETINDLINK_PD_IND_LINK_COUNT_MASK 0xffff 25500 #define XGXSBLK6_PARDETINDLINK_PD_IND_LINK_COUNT_ALIGN 0 25501 #define XGXSBLK6_PARDETINDLINK_PD_IND_LINK_COUNT_BITS 16 25502 #define XGXSBLK6_PARDETINDLINK_PD_IND_LINK_COUNT_SHIFT 0 25503 25504 25505 /**************************************************************************** 25506 * XgxsBlk6 :: parDetINDLostLink 25507 */ 25508 /* XgxsBlk6 :: parDetINDLostLink :: pd_ind_sd_count [15:00] */ 25509 #define XGXSBLK6_PARDETINDLOSTLINK_PD_IND_SD_COUNT_MASK 0xffff 25510 #define XGXSBLK6_PARDETINDLOSTLINK_PD_IND_SD_COUNT_ALIGN 0 25511 #define XGXSBLK6_PARDETINDLOSTLINK_PD_IND_SD_COUNT_BITS 16 25512 #define XGXSBLK6_PARDETINDLOSTLINK_PD_IND_SD_COUNT_SHIFT 0 25513 25514 25515 /**************************************************************************** 25516 * Warpcore_USER_XgxsBlk7 25517 */ 25518 /**************************************************************************** 25519 * XgxsBlk7 :: EEEControl 25520 */ 25521 /* XgxsBlk7 :: EEEControl :: reserved_for_eco0 [15:08] */ 25522 #define XGXSBLK7_EEECONTROL_RESERVED_FOR_ECO0_MASK 0xff00 25523 #define XGXSBLK7_EEECONTROL_RESERVED_FOR_ECO0_ALIGN 0 25524 #define XGXSBLK7_EEECONTROL_RESERVED_FOR_ECO0_BITS 8 25525 #define XGXSBLK7_EEECONTROL_RESERVED_FOR_ECO0_SHIFT 8 25526 25527 /* XgxsBlk7 :: EEEControl :: brcm_66_ll_swap_cya [07:07] */ 25528 #define XGXSBLK7_EEECONTROL_BRCM_66_LL_SWAP_CYA_MASK 0x0080 25529 #define XGXSBLK7_EEECONTROL_BRCM_66_LL_SWAP_CYA_ALIGN 0 25530 #define XGXSBLK7_EEECONTROL_BRCM_66_LL_SWAP_CYA_BITS 1 25531 #define XGXSBLK7_EEECONTROL_BRCM_66_LL_SWAP_CYA_SHIFT 7 25532 25533 /* XgxsBlk7 :: EEEControl :: LPI_hyst_cnt_10g [06:04] */ 25534 #define XGXSBLK7_EEECONTROL_LPI_HYST_CNT_10G_MASK 0x0070 25535 #define XGXSBLK7_EEECONTROL_LPI_HYST_CNT_10G_ALIGN 0 25536 #define XGXSBLK7_EEECONTROL_LPI_HYST_CNT_10G_BITS 3 25537 #define XGXSBLK7_EEECONTROL_LPI_HYST_CNT_10G_SHIFT 4 25538 25539 /* XgxsBlk7 :: EEEControl :: LPI_hyst_en_10g [03:03] */ 25540 #define XGXSBLK7_EEECONTROL_LPI_HYST_EN_10G_MASK 0x0008 25541 #define XGXSBLK7_EEECONTROL_LPI_HYST_EN_10G_ALIGN 0 25542 #define XGXSBLK7_EEECONTROL_LPI_HYST_EN_10G_BITS 1 25543 #define XGXSBLK7_EEECONTROL_LPI_HYST_EN_10G_SHIFT 3 25544 25545 /* XgxsBlk7 :: EEEControl :: LPI_col_det_en [02:02] */ 25546 #define XGXSBLK7_EEECONTROL_LPI_COL_DET_EN_MASK 0x0004 25547 #define XGXSBLK7_EEECONTROL_LPI_COL_DET_EN_ALIGN 0 25548 #define XGXSBLK7_EEECONTROL_LPI_COL_DET_EN_BITS 1 25549 #define XGXSBLK7_EEECONTROL_LPI_COL_DET_EN_SHIFT 2 25550 25551 /* XgxsBlk7 :: EEEControl :: LPI_en_rx [01:01] */ 25552 #define XGXSBLK7_EEECONTROL_LPI_EN_RX_MASK 0x0002 25553 #define XGXSBLK7_EEECONTROL_LPI_EN_RX_ALIGN 0 25554 #define XGXSBLK7_EEECONTROL_LPI_EN_RX_BITS 1 25555 #define XGXSBLK7_EEECONTROL_LPI_EN_RX_SHIFT 1 25556 25557 /* XgxsBlk7 :: EEEControl :: LPI_en_tx [00:00] */ 25558 #define XGXSBLK7_EEECONTROL_LPI_EN_TX_MASK 0x0001 25559 #define XGXSBLK7_EEECONTROL_LPI_EN_TX_ALIGN 0 25560 #define XGXSBLK7_EEECONTROL_LPI_EN_TX_BITS 1 25561 #define XGXSBLK7_EEECONTROL_LPI_EN_TX_SHIFT 0 25562 25563 25564 /**************************************************************************** 25565 * XgxsBlk7 :: EEEstatus 25566 */ 25567 /* XgxsBlk7 :: EEEstatus :: reserved_for_eco0 [15:04] */ 25568 #define XGXSBLK7_EEESTATUS_RESERVED_FOR_ECO0_MASK 0xfff0 25569 #define XGXSBLK7_EEESTATUS_RESERVED_FOR_ECO0_ALIGN 0 25570 #define XGXSBLK7_EEESTATUS_RESERVED_FOR_ECO0_BITS 12 25571 #define XGXSBLK7_EEESTATUS_RESERVED_FOR_ECO0_SHIFT 4 25572 25573 /* XgxsBlk7 :: EEEstatus :: rx10g_LPI_ind [03:03] */ 25574 #define XGXSBLK7_EEESTATUS_RX10G_LPI_IND_MASK 0x0008 25575 #define XGXSBLK7_EEESTATUS_RX10G_LPI_IND_ALIGN 0 25576 #define XGXSBLK7_EEESTATUS_RX10G_LPI_IND_BITS 1 25577 #define XGXSBLK7_EEESTATUS_RX10G_LPI_IND_SHIFT 3 25578 25579 /* XgxsBlk7 :: EEEstatus :: tx10g_LPI_ind [02:02] */ 25580 #define XGXSBLK7_EEESTATUS_TX10G_LPI_IND_MASK 0x0004 25581 #define XGXSBLK7_EEESTATUS_TX10G_LPI_IND_ALIGN 0 25582 #define XGXSBLK7_EEESTATUS_TX10G_LPI_IND_BITS 1 25583 #define XGXSBLK7_EEESTATUS_TX10G_LPI_IND_SHIFT 2 25584 25585 /* XgxsBlk7 :: EEEstatus :: LPI_tx_det [01:01] */ 25586 #define XGXSBLK7_EEESTATUS_LPI_TX_DET_MASK 0x0002 25587 #define XGXSBLK7_EEESTATUS_LPI_TX_DET_ALIGN 0 25588 #define XGXSBLK7_EEESTATUS_LPI_TX_DET_BITS 1 25589 #define XGXSBLK7_EEESTATUS_LPI_TX_DET_SHIFT 1 25590 25591 /* XgxsBlk7 :: EEEstatus :: LPI_rx_det [00:00] */ 25592 #define XGXSBLK7_EEESTATUS_LPI_RX_DET_MASK 0x0001 25593 #define XGXSBLK7_EEESTATUS_LPI_RX_DET_ALIGN 0 25594 #define XGXSBLK7_EEESTATUS_LPI_RX_DET_BITS 1 25595 #define XGXSBLK7_EEESTATUS_LPI_RX_DET_SHIFT 0 25596 25597 25598 /**************************************************************************** 25599 * XgxsBlk7 :: xgmiiLPI 25600 */ 25601 /* XgxsBlk7 :: xgmiiLPI :: Quiet [15:08] */ 25602 #define XGXSBLK7_XGMIILPI_QUIET_MASK 0xff00 25603 #define XGXSBLK7_XGMIILPI_QUIET_ALIGN 0 25604 #define XGXSBLK7_XGMIILPI_QUIET_BITS 8 25605 #define XGXSBLK7_XGMIILPI_QUIET_SHIFT 8 25606 25607 /* XgxsBlk7 :: xgmiiLPI :: LPI [07:00] */ 25608 #define XGXSBLK7_XGMIILPI_LPI_MASK 0x00ff 25609 #define XGXSBLK7_XGMIILPI_LPI_ALIGN 0 25610 #define XGXSBLK7_XGMIILPI_LPI_BITS 8 25611 #define XGXSBLK7_XGMIILPI_LPI_SHIFT 0 25612 25613 25614 /**************************************************************************** 25615 * XgxsBlk7 :: LPIlane13 25616 */ 25617 /* XgxsBlk7 :: LPIlane13 :: reserved_for_eco0 [15:09] */ 25618 #define XGXSBLK7_LPILANE13_RESERVED_FOR_ECO0_MASK 0xfe00 25619 #define XGXSBLK7_LPILANE13_RESERVED_FOR_ECO0_ALIGN 0 25620 #define XGXSBLK7_LPILANE13_RESERVED_FOR_ECO0_BITS 7 25621 #define XGXSBLK7_LPILANE13_RESERVED_FOR_ECO0_SHIFT 9 25622 25623 /* XgxsBlk7 :: LPIlane13 :: LPI_lane13 [08:00] */ 25624 #define XGXSBLK7_LPILANE13_LPI_LANE13_MASK 0x01ff 25625 #define XGXSBLK7_LPILANE13_LPI_LANE13_ALIGN 0 25626 #define XGXSBLK7_LPILANE13_LPI_LANE13_BITS 9 25627 #define XGXSBLK7_LPILANE13_LPI_LANE13_SHIFT 0 25628 25629 25630 /**************************************************************************** 25631 * XgxsBlk7 :: Qrsvd1 25632 */ 25633 /* XgxsBlk7 :: Qrsvd1 :: reserved_for_eco0 [15:11] */ 25634 #define XGXSBLK7_QRSVD1_RESERVED_FOR_ECO0_MASK 0xf800 25635 #define XGXSBLK7_QRSVD1_RESERVED_FOR_ECO0_ALIGN 0 25636 #define XGXSBLK7_QRSVD1_RESERVED_FOR_ECO0_BITS 5 25637 #define XGXSBLK7_QRSVD1_RESERVED_FOR_ECO0_SHIFT 11 25638 25639 /* XgxsBlk7 :: Qrsvd1 :: Qrsvd3_msb [10:10] */ 25640 #define XGXSBLK7_QRSVD1_QRSVD3_MSB_MASK 0x0400 25641 #define XGXSBLK7_QRSVD1_QRSVD3_MSB_ALIGN 0 25642 #define XGXSBLK7_QRSVD1_QRSVD3_MSB_BITS 1 25643 #define XGXSBLK7_QRSVD1_QRSVD3_MSB_SHIFT 10 25644 25645 /* XgxsBlk7 :: Qrsvd1 :: Qrsvd2_msb [09:09] */ 25646 #define XGXSBLK7_QRSVD1_QRSVD2_MSB_MASK 0x0200 25647 #define XGXSBLK7_QRSVD1_QRSVD2_MSB_ALIGN 0 25648 #define XGXSBLK7_QRSVD1_QRSVD2_MSB_BITS 1 25649 #define XGXSBLK7_QRSVD1_QRSVD2_MSB_SHIFT 9 25650 25651 /* XgxsBlk7 :: Qrsvd1 :: Qrsvd1 [08:00] */ 25652 #define XGXSBLK7_QRSVD1_QRSVD1_MASK 0x01ff 25653 #define XGXSBLK7_QRSVD1_QRSVD1_ALIGN 0 25654 #define XGXSBLK7_QRSVD1_QRSVD1_BITS 9 25655 #define XGXSBLK7_QRSVD1_QRSVD1_SHIFT 0 25656 25657 25658 /**************************************************************************** 25659 * XgxsBlk7 :: Qrsvd23 25660 */ 25661 /* XgxsBlk7 :: Qrsvd23 :: Qrsvd2 [15:08] */ 25662 #define XGXSBLK7_QRSVD23_QRSVD2_MASK 0xff00 25663 #define XGXSBLK7_QRSVD23_QRSVD2_ALIGN 0 25664 #define XGXSBLK7_QRSVD23_QRSVD2_BITS 8 25665 #define XGXSBLK7_QRSVD23_QRSVD2_SHIFT 8 25666 25667 /* XgxsBlk7 :: Qrsvd23 :: Qrsvd3 [07:00] */ 25668 #define XGXSBLK7_QRSVD23_QRSVD3_MASK 0x00ff 25669 #define XGXSBLK7_QRSVD23_QRSVD3_ALIGN 0 25670 #define XGXSBLK7_QRSVD23_QRSVD3_BITS 8 25671 #define XGXSBLK7_QRSVD23_QRSVD3_SHIFT 0 25672 25673 25674 /**************************************************************************** 25675 * XgxsBlk7 :: Qrsvdswap 25676 */ 25677 /* XgxsBlk7 :: Qrsvdswap :: reserved_for_eco0 [15:15] */ 25678 #define XGXSBLK7_QRSVDSWAP_RESERVED_FOR_ECO0_MASK 0x8000 25679 #define XGXSBLK7_QRSVDSWAP_RESERVED_FOR_ECO0_ALIGN 0 25680 #define XGXSBLK7_QRSVDSWAP_RESERVED_FOR_ECO0_BITS 1 25681 #define XGXSBLK7_QRSVDSWAP_RESERVED_FOR_ECO0_SHIFT 15 25682 25683 /* XgxsBlk7 :: Qrsvdswap :: lf_rf_swap_cya [14:14] */ 25684 #define XGXSBLK7_QRSVDSWAP_LF_RF_SWAP_CYA_MASK 0x4000 25685 #define XGXSBLK7_QRSVDSWAP_LF_RF_SWAP_CYA_ALIGN 0 25686 #define XGXSBLK7_QRSVDSWAP_LF_RF_SWAP_CYA_BITS 1 25687 #define XGXSBLK7_QRSVDSWAP_LF_RF_SWAP_CYA_SHIFT 14 25688 25689 /* XgxsBlk7 :: Qrsvdswap :: Qrsvdswap_ctrl [13:10] */ 25690 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_CTRL_MASK 0x3c00 25691 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_CTRL_ALIGN 0 25692 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_CTRL_BITS 4 25693 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_CTRL_SHIFT 10 25694 25695 /* XgxsBlk7 :: Qrsvdswap :: Qrsvdswap [09:00] */ 25696 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_MASK 0x03ff 25697 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_ALIGN 0 25698 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_BITS 10 25699 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_SHIFT 0 25700 25701 25702 /**************************************************************************** 25703 * XgxsBlk7 :: Qrsvdstatus 25704 */ 25705 /* XgxsBlk7 :: Qrsvdstatus :: rx_Q_char3 [15:07] */ 25706 #define XGXSBLK7_QRSVDSTATUS_RX_Q_CHAR3_MASK 0xff80 25707 #define XGXSBLK7_QRSVDSTATUS_RX_Q_CHAR3_ALIGN 0 25708 #define XGXSBLK7_QRSVDSTATUS_RX_Q_CHAR3_BITS 9 25709 #define XGXSBLK7_QRSVDSTATUS_RX_Q_CHAR3_SHIFT 7 25710 25711 /* XgxsBlk7 :: Qrsvdstatus :: reserved_for_eco0 [06:05] */ 25712 #define XGXSBLK7_QRSVDSTATUS_RESERVED_FOR_ECO0_MASK 0x0060 25713 #define XGXSBLK7_QRSVDSTATUS_RESERVED_FOR_ECO0_ALIGN 0 25714 #define XGXSBLK7_QRSVDSTATUS_RESERVED_FOR_ECO0_BITS 2 25715 #define XGXSBLK7_QRSVDSTATUS_RESERVED_FOR_ECO0_SHIFT 5 25716 25717 /* XgxsBlk7 :: Qrsvdstatus :: rx_undef_Q_det [04:04] */ 25718 #define XGXSBLK7_QRSVDSTATUS_RX_UNDEF_Q_DET_MASK 0x0010 25719 #define XGXSBLK7_QRSVDSTATUS_RX_UNDEF_Q_DET_ALIGN 0 25720 #define XGXSBLK7_QRSVDSTATUS_RX_UNDEF_Q_DET_BITS 1 25721 #define XGXSBLK7_QRSVDSTATUS_RX_UNDEF_Q_DET_SHIFT 4 25722 25723 /* XgxsBlk7 :: Qrsvdstatus :: xaui_rx_rf_det [03:03] */ 25724 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_RF_DET_MASK 0x0008 25725 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_RF_DET_ALIGN 0 25726 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_RF_DET_BITS 1 25727 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_RF_DET_SHIFT 3 25728 25729 /* XgxsBlk7 :: Qrsvdstatus :: xaui_rx_lf_det [02:02] */ 25730 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_LF_DET_MASK 0x0004 25731 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_LF_DET_ALIGN 0 25732 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_LF_DET_BITS 1 25733 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_LF_DET_SHIFT 2 25734 25735 /* XgxsBlk7 :: Qrsvdstatus :: Qrsvd_rx_det [01:01] */ 25736 #define XGXSBLK7_QRSVDSTATUS_QRSVD_RX_DET_MASK 0x0002 25737 #define XGXSBLK7_QRSVDSTATUS_QRSVD_RX_DET_ALIGN 0 25738 #define XGXSBLK7_QRSVDSTATUS_QRSVD_RX_DET_BITS 1 25739 #define XGXSBLK7_QRSVDSTATUS_QRSVD_RX_DET_SHIFT 1 25740 25741 /* XgxsBlk7 :: Qrsvdstatus :: Qrsvd_tx_det [00:00] */ 25742 #define XGXSBLK7_QRSVDSTATUS_QRSVD_TX_DET_MASK 0x0001 25743 #define XGXSBLK7_QRSVDSTATUS_QRSVD_TX_DET_ALIGN 0 25744 #define XGXSBLK7_QRSVDSTATUS_QRSVD_TX_DET_BITS 1 25745 #define XGXSBLK7_QRSVDSTATUS_QRSVD_TX_DET_SHIFT 0 25746 25747 25748 /**************************************************************************** 25749 * XgxsBlk7 :: cl48_tx_lpi_sm 25750 */ 25751 /* XgxsBlk7 :: cl48_tx_lpi_sm :: reserved_for_eco0 [15:07] */ 25752 #define XGXSBLK7_CL48_TX_LPI_SM_RESERVED_FOR_ECO0_MASK 0xff80 25753 #define XGXSBLK7_CL48_TX_LPI_SM_RESERVED_FOR_ECO0_ALIGN 0 25754 #define XGXSBLK7_CL48_TX_LPI_SM_RESERVED_FOR_ECO0_BITS 9 25755 #define XGXSBLK7_CL48_TX_LPI_SM_RESERVED_FOR_ECO0_SHIFT 7 25756 25757 /* XgxsBlk7 :: cl48_tx_lpi_sm :: cl48_tx_lpi_state_l [06:03] */ 25758 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_MASK 0x0078 25759 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_ALIGN 0 25760 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_BITS 4 25761 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_SHIFT 3 25762 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_TX_REFRESH 8 25763 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_TX_QUIET 4 25764 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_TX_SLEEP 2 25765 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_TX_ACTIVE 1 25766 25767 /* XgxsBlk7 :: cl48_tx_lpi_sm :: cl48_tx_lpi_state_c [02:00] */ 25768 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_MASK 0x0007 25769 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_ALIGN 0 25770 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_BITS 3 25771 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_SHIFT 0 25772 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_TX_REFRESH 3 25773 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_TX_QUIET 2 25774 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_TX_SLEEP 1 25775 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_TX_ACTIVE 0 25776 25777 25778 /**************************************************************************** 25779 * XgxsBlk7 :: cl48_rx_lpi_sm 25780 */ 25781 /* XgxsBlk7 :: cl48_rx_lpi_sm :: reserved_for_eco0 [15:09] */ 25782 #define XGXSBLK7_CL48_RX_LPI_SM_RESERVED_FOR_ECO0_MASK 0xfe00 25783 #define XGXSBLK7_CL48_RX_LPI_SM_RESERVED_FOR_ECO0_ALIGN 0 25784 #define XGXSBLK7_CL48_RX_LPI_SM_RESERVED_FOR_ECO0_BITS 7 25785 #define XGXSBLK7_CL48_RX_LPI_SM_RESERVED_FOR_ECO0_SHIFT 9 25786 25787 /* XgxsBlk7 :: cl48_rx_lpi_sm :: cl48_rx_lpi_state_l [08:03] */ 25788 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_MASK 0x01f8 25789 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_ALIGN 0 25790 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_BITS 6 25791 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_SHIFT 3 25792 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_LINK_FAIL 32 25793 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_WAKE 16 25794 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_QUIET 8 25795 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_DEACT 4 25796 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_SLEEP 2 25797 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_ACTIVE 1 25798 25799 /* XgxsBlk7 :: cl48_rx_lpi_sm :: cl48_rx_lpi_state_c [02:00] */ 25800 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_MASK 0x0007 25801 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_ALIGN 0 25802 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_BITS 3 25803 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_SHIFT 0 25804 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_LINK_FAIL 5 25805 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_WAKE 4 25806 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_QUIET 3 25807 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_DEACT 2 25808 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_SLEEP 1 25809 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_ACTIVE 0 25810 25811 25812 /**************************************************************************** 25813 * XgxsBlk7 :: fifo_ctrl 25814 */ 25815 /* XgxsBlk7 :: fifo_ctrl :: reserved_for_eco0 [15:10] */ 25816 #define XGXSBLK7_FIFO_CTRL_RESERVED_FOR_ECO0_MASK 0xfc00 25817 #define XGXSBLK7_FIFO_CTRL_RESERVED_FOR_ECO0_ALIGN 0 25818 #define XGXSBLK7_FIFO_CTRL_RESERVED_FOR_ECO0_BITS 6 25819 #define XGXSBLK7_FIFO_CTRL_RESERVED_FOR_ECO0_SHIFT 10 25820 25821 /* XgxsBlk7 :: fifo_ctrl :: txfifo_chk_cya [09:09] */ 25822 #define XGXSBLK7_FIFO_CTRL_TXFIFO_CHK_CYA_MASK 0x0200 25823 #define XGXSBLK7_FIFO_CTRL_TXFIFO_CHK_CYA_ALIGN 0 25824 #define XGXSBLK7_FIFO_CTRL_TXFIFO_CHK_CYA_BITS 1 25825 #define XGXSBLK7_FIFO_CTRL_TXFIFO_CHK_CYA_SHIFT 9 25826 25827 /* XgxsBlk7 :: fifo_ctrl :: eee_txfifo_ckgate_en [08:08] */ 25828 #define XGXSBLK7_FIFO_CTRL_EEE_TXFIFO_CKGATE_EN_MASK 0x0100 25829 #define XGXSBLK7_FIFO_CTRL_EEE_TXFIFO_CKGATE_EN_ALIGN 0 25830 #define XGXSBLK7_FIFO_CTRL_EEE_TXFIFO_CKGATE_EN_BITS 1 25831 #define XGXSBLK7_FIFO_CTRL_EEE_TXFIFO_CKGATE_EN_SHIFT 8 25832 25833 /* XgxsBlk7 :: fifo_ctrl :: force_rxfifo_mode_en [07:07] */ 25834 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_EN_MASK 0x0080 25835 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_EN_ALIGN 0 25836 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_EN_BITS 1 25837 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_EN_SHIFT 7 25838 25839 /* XgxsBlk7 :: fifo_ctrl :: force_rxfifo_mode_value [06:04] */ 25840 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_VALUE_MASK 0x0070 25841 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_VALUE_ALIGN 0 25842 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_VALUE_BITS 3 25843 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_VALUE_SHIFT 4 25844 25845 /* XgxsBlk7 :: fifo_ctrl :: force_txfifo_mode_en [03:03] */ 25846 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_EN_MASK 0x0008 25847 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_EN_ALIGN 0 25848 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_EN_BITS 1 25849 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_EN_SHIFT 3 25850 25851 /* XgxsBlk7 :: fifo_ctrl :: force_txfifo_mode_value [02:00] */ 25852 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_VALUE_MASK 0x0007 25853 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_VALUE_ALIGN 0 25854 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_VALUE_BITS 3 25855 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_VALUE_SHIFT 0 25856 25857 25858 /**************************************************************************** 25859 * XgxsBlk7 :: fifo_status 25860 */ 25861 /* XgxsBlk7 :: fifo_status :: reserved_for_eco0 [15:06] */ 25862 #define XGXSBLK7_FIFO_STATUS_RESERVED_FOR_ECO0_MASK 0xffc0 25863 #define XGXSBLK7_FIFO_STATUS_RESERVED_FOR_ECO0_ALIGN 0 25864 #define XGXSBLK7_FIFO_STATUS_RESERVED_FOR_ECO0_BITS 10 25865 #define XGXSBLK7_FIFO_STATUS_RESERVED_FOR_ECO0_SHIFT 6 25866 25867 /* XgxsBlk7 :: fifo_status :: txfifo_mode [05:03] */ 25868 #define XGXSBLK7_FIFO_STATUS_TXFIFO_MODE_MASK 0x0038 25869 #define XGXSBLK7_FIFO_STATUS_TXFIFO_MODE_ALIGN 0 25870 #define XGXSBLK7_FIFO_STATUS_TXFIFO_MODE_BITS 3 25871 #define XGXSBLK7_FIFO_STATUS_TXFIFO_MODE_SHIFT 3 25872 25873 /* XgxsBlk7 :: fifo_status :: rxfifo_mode [02:00] */ 25874 #define XGXSBLK7_FIFO_STATUS_RXFIFO_MODE_MASK 0x0007 25875 #define XGXSBLK7_FIFO_STATUS_RXFIFO_MODE_ALIGN 0 25876 #define XGXSBLK7_FIFO_STATUS_RXFIFO_MODE_BITS 3 25877 #define XGXSBLK7_FIFO_STATUS_RXFIFO_MODE_SHIFT 0 25878 25879 25880 /**************************************************************************** 25881 * Warpcore_USER_XgxsBlk8 25882 */ 25883 /**************************************************************************** 25884 * XgxsBlk8 :: cl73Control7 25885 */ 25886 /* XgxsBlk8 :: cl73Control7 :: cl73_an_switch_cntL [15:00] */ 25887 #define XGXSBLK8_CL73CONTROL7_CL73_AN_SWITCH_CNTL_MASK 0xffff 25888 #define XGXSBLK8_CL73CONTROL7_CL73_AN_SWITCH_CNTL_ALIGN 0 25889 #define XGXSBLK8_CL73CONTROL7_CL73_AN_SWITCH_CNTL_BITS 16 25890 #define XGXSBLK8_CL73CONTROL7_CL73_AN_SWITCH_CNTL_SHIFT 0 25891 25892 25893 /**************************************************************************** 25894 * XgxsBlk8 :: cl73Control8 25895 */ 25896 /* XgxsBlk8 :: cl73Control8 :: cl73_refclk_161_offset_cnt [15:08] */ 25897 #define XGXSBLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_MASK 0xff00 25898 #define XGXSBLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_ALIGN 0 25899 #define XGXSBLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_BITS 8 25900 #define XGXSBLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_SHIFT 8 25901 25902 /* XgxsBlk8 :: cl73Control8 :: cl73_an_switch_cntH [07:00] */ 25903 #define XGXSBLK8_CL73CONTROL8_CL73_AN_SWITCH_CNTH_MASK 0x00ff 25904 #define XGXSBLK8_CL73CONTROL8_CL73_AN_SWITCH_CNTH_ALIGN 0 25905 #define XGXSBLK8_CL73CONTROL8_CL73_AN_SWITCH_CNTH_BITS 8 25906 #define XGXSBLK8_CL73CONTROL8_CL73_AN_SWITCH_CNTH_SHIFT 0 25907 25908 25909 /**************************************************************************** 25910 * XgxsBlk8 :: cl73Control9 25911 */ 25912 /* XgxsBlk8 :: cl73Control9 :: reserved0 [15:15] */ 25913 #define XGXSBLK8_CL73CONTROL9_RESERVED0_MASK 0x8000 25914 #define XGXSBLK8_CL73CONTROL9_RESERVED0_ALIGN 0 25915 #define XGXSBLK8_CL73CONTROL9_RESERVED0_BITS 1 25916 #define XGXSBLK8_CL73CONTROL9_RESERVED0_SHIFT 15 25917 25918 /* XgxsBlk8 :: cl73Control9 :: rxSeqDone_cya [14:14] */ 25919 #define XGXSBLK8_CL73CONTROL9_RXSEQDONE_CYA_MASK 0x4000 25920 #define XGXSBLK8_CL73CONTROL9_RXSEQDONE_CYA_ALIGN 0 25921 #define XGXSBLK8_CL73CONTROL9_RXSEQDONE_CYA_BITS 1 25922 #define XGXSBLK8_CL73CONTROL9_RXSEQDONE_CYA_SHIFT 14 25923 25924 /* XgxsBlk8 :: cl73Control9 :: cl73_link_fail_inhibit_timer_kr_val [13:00] */ 25925 #define XGXSBLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_MASK 0x3fff 25926 #define XGXSBLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_ALIGN 0 25927 #define XGXSBLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_BITS 14 25928 #define XGXSBLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_SHIFT 0 25929 25930 25931 /**************************************************************************** 25932 * XgxsBlk8 :: cl73Control10 25933 */ 25934 /* XgxsBlk8 :: cl73Control10 :: reserved0 [15:14] */ 25935 #define XGXSBLK8_CL73CONTROL10_RESERVED0_MASK 0xc000 25936 #define XGXSBLK8_CL73CONTROL10_RESERVED0_ALIGN 0 25937 #define XGXSBLK8_CL73CONTROL10_RESERVED0_BITS 2 25938 #define XGXSBLK8_CL73CONTROL10_RESERVED0_SHIFT 14 25939 25940 /* XgxsBlk8 :: cl73Control10 :: cl73_link_fail_inhibit_timer_cl72_val [13:00] */ 25941 #define XGXSBLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_MASK 0x3fff 25942 #define XGXSBLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_ALIGN 0 25943 #define XGXSBLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_BITS 14 25944 #define XGXSBLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_SHIFT 0 25945 25946 25947 /**************************************************************************** 25948 * XgxsBlk8 :: tx_pi_control1 25949 */ 25950 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_integ_sat_sel [15:15] */ 25951 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_MASK 0x8000 25952 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_ALIGN 0 25953 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_BITS 1 25954 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_SHIFT 15 25955 25956 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_integ_sat_1_or_2 [14:14] */ 25957 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_MASK 0x4000 25958 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_ALIGN 0 25959 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_BITS 1 25960 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_SHIFT 14 25961 25962 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_invert [13:13] */ 25963 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_MASK 0x2000 25964 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_ALIGN 0 25965 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_BITS 1 25966 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_SHIFT 13 25967 25968 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_step_mult [12:12] */ 25969 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_MASK 0x1000 25970 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_ALIGN 0 25971 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_BITS 1 25972 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_SHIFT 12 25973 25974 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_step_dir [11:11] */ 25975 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_MASK 0x0800 25976 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_ALIGN 0 25977 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_BITS 1 25978 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_SHIFT 11 25979 25980 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_step [10:09] */ 25981 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MASK 0x0600 25982 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_ALIGN 0 25983 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_BITS 2 25984 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_SHIFT 9 25985 25986 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_delta [08:04] */ 25987 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_MASK 0x01f0 25988 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_ALIGN 0 25989 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_BITS 5 25990 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_SHIFT 4 25991 25992 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_strobe [03:03] */ 25993 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_MASK 0x0008 25994 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_ALIGN 0 25995 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_BITS 1 25996 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_SHIFT 3 25997 25998 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_override [02:02] */ 25999 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_MASK 0x0004 26000 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_ALIGN 0 26001 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_BITS 1 26002 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_SHIFT 2 26003 26004 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_bypass_mode [01:01] */ 26005 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_MASK 0x0002 26006 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_ALIGN 0 26007 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_BITS 1 26008 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_SHIFT 1 26009 26010 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_en [00:00] */ 26011 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_EN_MASK 0x0001 26012 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_EN_ALIGN 0 26013 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_EN_BITS 1 26014 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_EN_SHIFT 0 26015 26016 26017 /**************************************************************************** 26018 * XgxsBlk8 :: tx_pi_control2 26019 */ 26020 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_sm_timer_sel [15:14] */ 26021 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_MASK 0xc000 26022 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_ALIGN 0 26023 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_BITS 2 26024 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_SHIFT 14 26025 26026 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_sm_done_override [13:13] */ 26027 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_MASK 0x2000 26028 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_ALIGN 0 26029 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_BITS 1 26030 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_SHIFT 13 26031 26032 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_sm_en_override [12:12] */ 26033 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_MASK 0x1000 26034 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_ALIGN 0 26035 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_BITS 1 26036 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_SHIFT 12 26037 26038 /* XgxsBlk8 :: tx_pi_control2 :: reserved_for_eco0 [11:09] */ 26039 #define XGXSBLK8_TX_PI_CONTROL2_RESERVED_FOR_ECO0_MASK 0x0e00 26040 #define XGXSBLK8_TX_PI_CONTROL2_RESERVED_FOR_ECO0_ALIGN 0 26041 #define XGXSBLK8_TX_PI_CONTROL2_RESERVED_FOR_ECO0_BITS 3 26042 #define XGXSBLK8_TX_PI_CONTROL2_RESERVED_FOR_ECO0_SHIFT 9 26043 26044 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_ckgate_en [08:08] */ 26045 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_CKGATE_EN_MASK 0x0100 26046 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_CKGATE_EN_ALIGN 0 26047 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_CKGATE_EN_BITS 1 26048 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_CKGATE_EN_SHIFT 8 26049 26050 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_loopback_mode [07:07] */ 26051 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_MASK 0x0080 26052 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_ALIGN 0 26053 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_BITS 1 26054 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_SHIFT 7 26055 26056 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_sm_bypass [06:06] */ 26057 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_BYPASS_MASK 0x0040 26058 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_BYPASS_ALIGN 0 26059 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_BYPASS_BITS 1 26060 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_BYPASS_SHIFT 6 26061 26062 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_integ_reg_clr [05:05] */ 26063 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_MASK 0x0020 26064 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_ALIGN 0 26065 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_BITS 1 26066 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_SHIFT 5 26067 26068 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_bwsel_integ [04:02] */ 26069 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_MASK 0x001c 26070 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_ALIGN 0 26071 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_BITS 3 26072 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_SHIFT 2 26073 26074 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_rx_lane_sel [01:00] */ 26075 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_MASK 0x0003 26076 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_ALIGN 0 26077 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_BITS 2 26078 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_SHIFT 0 26079 26080 26081 /**************************************************************************** 26082 * XgxsBlk8 :: tx_pi_control3 26083 */ 26084 /* XgxsBlk8 :: tx_pi_control3 :: tx_pi_freq_override_val [15:01] */ 26085 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_MASK 0xfffe 26086 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_ALIGN 0 26087 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_BITS 15 26088 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_SHIFT 1 26089 26090 /* XgxsBlk8 :: tx_pi_control3 :: tx_pi_freq_override_en [00:00] */ 26091 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_MASK 0x0001 26092 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_ALIGN 0 26093 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_BITS 1 26094 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_SHIFT 0 26095 26096 26097 /**************************************************************************** 26098 * XgxsBlk8 :: tx_pi_status1 26099 */ 26100 /* XgxsBlk8 :: tx_pi_status1 :: reserved_for_eco0 [15:15] */ 26101 #define XGXSBLK8_TX_PI_STATUS1_RESERVED_FOR_ECO0_MASK 0x8000 26102 #define XGXSBLK8_TX_PI_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 26103 #define XGXSBLK8_TX_PI_STATUS1_RESERVED_FOR_ECO0_BITS 1 26104 #define XGXSBLK8_TX_PI_STATUS1_RESERVED_FOR_ECO0_SHIFT 15 26105 26106 /* XgxsBlk8 :: tx_pi_status1 :: tx_pi_integ_reg [14:00] */ 26107 #define XGXSBLK8_TX_PI_STATUS1_TX_PI_INTEG_REG_MASK 0x7fff 26108 #define XGXSBLK8_TX_PI_STATUS1_TX_PI_INTEG_REG_ALIGN 0 26109 #define XGXSBLK8_TX_PI_STATUS1_TX_PI_INTEG_REG_BITS 15 26110 #define XGXSBLK8_TX_PI_STATUS1_TX_PI_INTEG_REG_SHIFT 0 26111 26112 26113 /**************************************************************************** 26114 * XgxsBlk8 :: tx_pi_status2 26115 */ 26116 /* XgxsBlk8 :: tx_pi_status2 :: reserved_for_eco0 [15:07] */ 26117 #define XGXSBLK8_TX_PI_STATUS2_RESERVED_FOR_ECO0_MASK 0xff80 26118 #define XGXSBLK8_TX_PI_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 26119 #define XGXSBLK8_TX_PI_STATUS2_RESERVED_FOR_ECO0_BITS 9 26120 #define XGXSBLK8_TX_PI_STATUS2_RESERVED_FOR_ECO0_SHIFT 7 26121 26122 /* XgxsBlk8 :: tx_pi_status2 :: tx_pi_phase_cntr [06:00] */ 26123 #define XGXSBLK8_TX_PI_STATUS2_TX_PI_PHASE_CNTR_MASK 0x007f 26124 #define XGXSBLK8_TX_PI_STATUS2_TX_PI_PHASE_CNTR_ALIGN 0 26125 #define XGXSBLK8_TX_PI_STATUS2_TX_PI_PHASE_CNTR_BITS 7 26126 #define XGXSBLK8_TX_PI_STATUS2_TX_PI_PHASE_CNTR_SHIFT 0 26127 26128 26129 /**************************************************************************** 26130 * XgxsBlk8 :: txLnSwap1 26131 */ 26132 /* XgxsBlk8 :: txLnSwap1 :: force_GB_bypass_val [15:12] */ 26133 #define XGXSBLK8_TXLNSWAP1_FORCE_GB_BYPASS_VAL_MASK 0xf000 26134 #define XGXSBLK8_TXLNSWAP1_FORCE_GB_BYPASS_VAL_ALIGN 0 26135 #define XGXSBLK8_TXLNSWAP1_FORCE_GB_BYPASS_VAL_BITS 4 26136 #define XGXSBLK8_TXLNSWAP1_FORCE_GB_BYPASS_VAL_SHIFT 12 26137 26138 /* XgxsBlk8 :: txLnSwap1 :: force_GB_bypass_en [11:08] */ 26139 #define XGXSBLK8_TXLNSWAP1_FORCE_GB_BYPASS_EN_MASK 0x0f00 26140 #define XGXSBLK8_TXLNSWAP1_FORCE_GB_BYPASS_EN_ALIGN 0 26141 #define XGXSBLK8_TXLNSWAP1_FORCE_GB_BYPASS_EN_BITS 4 26142 #define XGXSBLK8_TXLNSWAP1_FORCE_GB_BYPASS_EN_SHIFT 8 26143 26144 /* XgxsBlk8 :: txLnSwap1 :: asymmetric mode enable [08:08],xgxs_13g only */ 26145 #define XGXSBLK8_TXLNSWAP1_ASYMMETRIC_MODE_EN_MASK 0x0100 26146 #define XGXSBLK8_TXLNSWAP1_ASYMMETRIC_MODE_EN_ALIGN 0 26147 #define XGXSBLK8_TXLNSWAP1_ASYMMETRIC_MODE_EN_BITS 1 26148 #define XGXSBLK8_TXLNSWAP1_ASYMMETRIC_MODE_EN_SHIFT 8 26149 26150 /* XgxsBlk8 :: txLnSwap1 :: tx3_lnswap_sel [07:06] */ 26151 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_MASK 0x00c0 26152 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_ALIGN 0 26153 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_BITS 2 26154 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_SHIFT 6 26155 26156 /* XgxsBlk8 :: txLnSwap1 :: tx2_lnswap_sel [05:04] */ 26157 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_MASK 0x0030 26158 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_ALIGN 0 26159 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_BITS 2 26160 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_SHIFT 4 26161 26162 /* XgxsBlk8 :: txLnSwap1 :: tx1_lnswap_sel [03:02] */ 26163 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_MASK 0x000c 26164 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_ALIGN 0 26165 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_BITS 2 26166 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_SHIFT 2 26167 26168 /* XgxsBlk8 :: txLnSwap1 :: tx0_lnswap_sel [01:00] */ 26169 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_MASK 0x0003 26170 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_ALIGN 0 26171 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_BITS 2 26172 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_SHIFT 0 26173 26174 26175 /**************************************************************************** 26176 * XgxsBlk8 :: txLnSwap2 26177 */ 26178 /* XgxsBlk8 :: txLnSwap2 :: reserved_for_eco0 [15:09] */ 26179 #define XGXSBLK8_TXLNSWAP2_RESERVED_FOR_ECO0_MASK 0xfe00 26180 #define XGXSBLK8_TXLNSWAP2_RESERVED_FOR_ECO0_ALIGN 0 26181 #define XGXSBLK8_TXLNSWAP2_RESERVED_FOR_ECO0_BITS 7 26182 #define XGXSBLK8_TXLNSWAP2_RESERVED_FOR_ECO0_SHIFT 9 26183 26184 /* XgxsBlk8 :: txLnSwap2 :: force_tx_ana_lnswap_sel [08:08] */ 26185 #define XGXSBLK8_TXLNSWAP2_FORCE_TX_ANA_LNSWAP_SEL_MASK 0x0100 26186 #define XGXSBLK8_TXLNSWAP2_FORCE_TX_ANA_LNSWAP_SEL_ALIGN 0 26187 #define XGXSBLK8_TXLNSWAP2_FORCE_TX_ANA_LNSWAP_SEL_BITS 1 26188 #define XGXSBLK8_TXLNSWAP2_FORCE_TX_ANA_LNSWAP_SEL_SHIFT 8 26189 26190 /* XgxsBlk8 :: txLnSwap2 :: tx3_ana_lnswap_sel [07:06] */ 26191 #define XGXSBLK8_TXLNSWAP2_TX3_ANA_LNSWAP_SEL_MASK 0x00c0 26192 #define XGXSBLK8_TXLNSWAP2_TX3_ANA_LNSWAP_SEL_ALIGN 0 26193 #define XGXSBLK8_TXLNSWAP2_TX3_ANA_LNSWAP_SEL_BITS 2 26194 #define XGXSBLK8_TXLNSWAP2_TX3_ANA_LNSWAP_SEL_SHIFT 6 26195 26196 /* XgxsBlk8 :: txLnSwap2 :: tx2_ana_lnswap_sel [05:04] */ 26197 #define XGXSBLK8_TXLNSWAP2_TX2_ANA_LNSWAP_SEL_MASK 0x0030 26198 #define XGXSBLK8_TXLNSWAP2_TX2_ANA_LNSWAP_SEL_ALIGN 0 26199 #define XGXSBLK8_TXLNSWAP2_TX2_ANA_LNSWAP_SEL_BITS 2 26200 #define XGXSBLK8_TXLNSWAP2_TX2_ANA_LNSWAP_SEL_SHIFT 4 26201 26202 /* XgxsBlk8 :: txLnSwap2 :: tx1_ana_lnswap_sel [03:02] */ 26203 #define XGXSBLK8_TXLNSWAP2_TX1_ANA_LNSWAP_SEL_MASK 0x000c 26204 #define XGXSBLK8_TXLNSWAP2_TX1_ANA_LNSWAP_SEL_ALIGN 0 26205 #define XGXSBLK8_TXLNSWAP2_TX1_ANA_LNSWAP_SEL_BITS 2 26206 #define XGXSBLK8_TXLNSWAP2_TX1_ANA_LNSWAP_SEL_SHIFT 2 26207 26208 /* XgxsBlk8 :: txLnSwap2 :: tx0_ana_lnswap_sel [01:00] */ 26209 #define XGXSBLK8_TXLNSWAP2_TX0_ANA_LNSWAP_SEL_MASK 0x0003 26210 #define XGXSBLK8_TXLNSWAP2_TX0_ANA_LNSWAP_SEL_ALIGN 0 26211 #define XGXSBLK8_TXLNSWAP2_TX0_ANA_LNSWAP_SEL_BITS 2 26212 #define XGXSBLK8_TXLNSWAP2_TX0_ANA_LNSWAP_SEL_SHIFT 0 26213 26214 26215 /**************************************************************************** 26216 * XgxsBlk8 :: rxLnSwap1 26217 */ 26218 /* XgxsBlk8 :: rxLnSwap1 :: reserved_for_eco0 [15:12] */ 26219 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_MASK 0xf000 26220 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_ALIGN 0 26221 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_BITS 4 26222 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_SHIFT 12 26223 26224 /* XgxsBlk8 :: rxLnSwap1 :: rfifo_20to20_ptr_sw_rst [11:08] */ 26225 #define XGXSBLK8_RXLNSWAP1_RFIFO_20TO20_PTR_SW_RST_MASK 0x0f00 26226 #define XGXSBLK8_RXLNSWAP1_RFIFO_20TO20_PTR_SW_RST_ALIGN 0 26227 #define XGXSBLK8_RXLNSWAP1_RFIFO_20TO20_PTR_SW_RST_BITS 4 26228 #define XGXSBLK8_RXLNSWAP1_RFIFO_20TO20_PTR_SW_RST_SHIFT 8 26229 26230 /* XgxsBlk8 :: rxLnSwap1 :: rx3_lnswap_sel [07:06] */ 26231 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_MASK 0x00c0 26232 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_ALIGN 0 26233 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_BITS 2 26234 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_SHIFT 6 26235 26236 /* XgxsBlk8 :: rxLnSwap1 :: rx2_lnswap_sel [05:04] */ 26237 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_MASK 0x0030 26238 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_ALIGN 0 26239 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_BITS 2 26240 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_SHIFT 4 26241 26242 /* XgxsBlk8 :: rxLnSwap1 :: rx1_lnswap_sel [03:02] */ 26243 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_MASK 0x000c 26244 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_ALIGN 0 26245 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_BITS 2 26246 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_SHIFT 2 26247 26248 /* XgxsBlk8 :: rxLnSwap1 :: rx0_lnswap_sel [01:00] */ 26249 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_MASK 0x0003 26250 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_ALIGN 0 26251 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_BITS 2 26252 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_SHIFT 0 26253 26254 26255 /**************************************************************************** 26256 * XgxsBlk8 :: rxLnSwap2 26257 */ 26258 /* XgxsBlk8 :: rxLnSwap2 :: reserved_for_eco0 [15:09] */ 26259 #define XGXSBLK8_RXLNSWAP2_RESERVED_FOR_ECO0_MASK 0xfe00 26260 #define XGXSBLK8_RXLNSWAP2_RESERVED_FOR_ECO0_ALIGN 0 26261 #define XGXSBLK8_RXLNSWAP2_RESERVED_FOR_ECO0_BITS 7 26262 #define XGXSBLK8_RXLNSWAP2_RESERVED_FOR_ECO0_SHIFT 9 26263 26264 /* XgxsBlk8 :: rxLnSwap2 :: force_rx_dig_lnswap_sel [08:08] */ 26265 #define XGXSBLK8_RXLNSWAP2_FORCE_RX_DIG_LNSWAP_SEL_MASK 0x0100 26266 #define XGXSBLK8_RXLNSWAP2_FORCE_RX_DIG_LNSWAP_SEL_ALIGN 0 26267 #define XGXSBLK8_RXLNSWAP2_FORCE_RX_DIG_LNSWAP_SEL_BITS 1 26268 #define XGXSBLK8_RXLNSWAP2_FORCE_RX_DIG_LNSWAP_SEL_SHIFT 8 26269 26270 /* XgxsBlk8 :: rxLnSwap2 :: rx3_dig_lnswap_sel [07:06] */ 26271 #define XGXSBLK8_RXLNSWAP2_RX3_DIG_LNSWAP_SEL_MASK 0x00c0 26272 #define XGXSBLK8_RXLNSWAP2_RX3_DIG_LNSWAP_SEL_ALIGN 0 26273 #define XGXSBLK8_RXLNSWAP2_RX3_DIG_LNSWAP_SEL_BITS 2 26274 #define XGXSBLK8_RXLNSWAP2_RX3_DIG_LNSWAP_SEL_SHIFT 6 26275 26276 /* XgxsBlk8 :: rxLnSwap2 :: rx2_dig_lnswap_sel [05:04] */ 26277 #define XGXSBLK8_RXLNSWAP2_RX2_DIG_LNSWAP_SEL_MASK 0x0030 26278 #define XGXSBLK8_RXLNSWAP2_RX2_DIG_LNSWAP_SEL_ALIGN 0 26279 #define XGXSBLK8_RXLNSWAP2_RX2_DIG_LNSWAP_SEL_BITS 2 26280 #define XGXSBLK8_RXLNSWAP2_RX2_DIG_LNSWAP_SEL_SHIFT 4 26281 26282 /* XgxsBlk8 :: rxLnSwap2 :: rx1_dig_lnswap_sel [03:02] */ 26283 #define XGXSBLK8_RXLNSWAP2_RX1_DIG_LNSWAP_SEL_MASK 0x000c 26284 #define XGXSBLK8_RXLNSWAP2_RX1_DIG_LNSWAP_SEL_ALIGN 0 26285 #define XGXSBLK8_RXLNSWAP2_RX1_DIG_LNSWAP_SEL_BITS 2 26286 #define XGXSBLK8_RXLNSWAP2_RX1_DIG_LNSWAP_SEL_SHIFT 2 26287 26288 /* XgxsBlk8 :: rxLnSwap2 :: rx0_dig_lnswap_sel [01:00] */ 26289 #define XGXSBLK8_RXLNSWAP2_RX0_DIG_LNSWAP_SEL_MASK 0x0003 26290 #define XGXSBLK8_RXLNSWAP2_RX0_DIG_LNSWAP_SEL_ALIGN 0 26291 #define XGXSBLK8_RXLNSWAP2_RX0_DIG_LNSWAP_SEL_BITS 2 26292 #define XGXSBLK8_RXLNSWAP2_RX0_DIG_LNSWAP_SEL_SHIFT 0 26293 26294 26295 /**************************************************************************** 26296 * XgxsBlk8 :: temp_sensor1 26297 */ 26298 /* XgxsBlk8 :: temp_sensor1 :: reserved0 [15:03] */ 26299 #define XGXSBLK8_TEMP_SENSOR1_RESERVED0_MASK 0xfff8 26300 #define XGXSBLK8_TEMP_SENSOR1_RESERVED0_ALIGN 0 26301 #define XGXSBLK8_TEMP_SENSOR1_RESERVED0_BITS 13 26302 #define XGXSBLK8_TEMP_SENSOR1_RESERVED0_SHIFT 3 26303 26304 /* XgxsBlk8 :: temp_sensor1 :: temp_sensor_resetb [02:02] */ 26305 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_RESETB_MASK 0x0004 26306 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_RESETB_ALIGN 0 26307 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_RESETB_BITS 1 26308 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_RESETB_SHIFT 2 26309 26310 /* XgxsBlk8 :: temp_sensor1 :: temp_sensor_pwrdn [01:01] */ 26311 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_PWRDN_MASK 0x0002 26312 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_PWRDN_ALIGN 0 26313 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_PWRDN_BITS 1 26314 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_PWRDN_SHIFT 1 26315 26316 /* XgxsBlk8 :: temp_sensor1 :: temp_sensor_bg_pwrdn [00:00] */ 26317 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_BG_PWRDN_MASK 0x0001 26318 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_BG_PWRDN_ALIGN 0 26319 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_BG_PWRDN_BITS 1 26320 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_BG_PWRDN_SHIFT 0 26321 26322 26323 /**************************************************************************** 26324 * XgxsBlk8 :: temp_sensor2 26325 */ 26326 /* XgxsBlk8 :: temp_sensor2 :: temp_sensor_control [15:00] */ 26327 #define XGXSBLK8_TEMP_SENSOR2_TEMP_SENSOR_CONTROL_MASK 0xffff 26328 #define XGXSBLK8_TEMP_SENSOR2_TEMP_SENSOR_CONTROL_ALIGN 0 26329 #define XGXSBLK8_TEMP_SENSOR2_TEMP_SENSOR_CONTROL_BITS 16 26330 #define XGXSBLK8_TEMP_SENSOR2_TEMP_SENSOR_CONTROL_SHIFT 0 26331 26332 26333 /**************************************************************************** 26334 * Warpcore_USER_XgxsBlk9 26335 */ 26336 /**************************************************************************** 26337 * XgxsBlk9 :: R2_control 26338 */ 26339 /* XgxsBlk9 :: R2_control :: R2_rloop_en [15:15] */ 26340 #define XGXSBLK9_R2_CONTROL_R2_RLOOP_EN_MASK 0x8000 26341 #define XGXSBLK9_R2_CONTROL_R2_RLOOP_EN_ALIGN 0 26342 #define XGXSBLK9_R2_CONTROL_R2_RLOOP_EN_BITS 1 26343 #define XGXSBLK9_R2_CONTROL_R2_RLOOP_EN_SHIFT 15 26344 26345 /* XgxsBlk9 :: R2_control :: btf_cnt_max_SM [14:10] */ 26346 #define XGXSBLK9_R2_CONTROL_BTF_CNT_MAX_SM_MASK 0x7c00 26347 #define XGXSBLK9_R2_CONTROL_BTF_CNT_MAX_SM_ALIGN 0 26348 #define XGXSBLK9_R2_CONTROL_BTF_CNT_MAX_SM_BITS 5 26349 #define XGXSBLK9_R2_CONTROL_BTF_CNT_MAX_SM_SHIFT 10 26350 26351 /* XgxsBlk9 :: R2_control :: btf_invalid_cnt_max_SM [09:05] */ 26352 #define XGXSBLK9_R2_CONTROL_BTF_INVALID_CNT_MAX_SM_MASK 0x03e0 26353 #define XGXSBLK9_R2_CONTROL_BTF_INVALID_CNT_MAX_SM_ALIGN 0 26354 #define XGXSBLK9_R2_CONTROL_BTF_INVALID_CNT_MAX_SM_BITS 5 26355 #define XGXSBLK9_R2_CONTROL_BTF_INVALID_CNT_MAX_SM_SHIFT 5 26356 26357 /* XgxsBlk9 :: R2_control :: rx66_R2_tstsel [04:01] */ 26358 #define XGXSBLK9_R2_CONTROL_RX66_R2_TSTSEL_MASK 0x001e 26359 #define XGXSBLK9_R2_CONTROL_RX66_R2_TSTSEL_ALIGN 0 26360 #define XGXSBLK9_R2_CONTROL_RX66_R2_TSTSEL_BITS 4 26361 #define XGXSBLK9_R2_CONTROL_RX66_R2_TSTSEL_SHIFT 1 26362 26363 /* XgxsBlk9 :: R2_control :: rx66_R2_deskew_en [00:00] */ 26364 #define XGXSBLK9_R2_CONTROL_RX66_R2_DESKEW_EN_MASK 0x0001 26365 #define XGXSBLK9_R2_CONTROL_RX66_R2_DESKEW_EN_ALIGN 0 26366 #define XGXSBLK9_R2_CONTROL_RX66_R2_DESKEW_EN_BITS 1 26367 #define XGXSBLK9_R2_CONTROL_RX66_R2_DESKEW_EN_SHIFT 0 26368 26369 26370 /**************************************************************************** 26371 * XgxsBlk9 :: R2_status 26372 */ 26373 /* XgxsBlk9 :: R2_status :: reserved_for_eco0 [15:06] */ 26374 #define XGXSBLK9_R2_STATUS_RESERVED_FOR_ECO0_MASK 0xffc0 26375 #define XGXSBLK9_R2_STATUS_RESERVED_FOR_ECO0_ALIGN 0 26376 #define XGXSBLK9_R2_STATUS_RESERVED_FOR_ECO0_BITS 10 26377 #define XGXSBLK9_R2_STATUS_RESERVED_FOR_ECO0_SHIFT 6 26378 26379 /* XgxsBlk9 :: R2_status :: rx66_R2_frame_lock_1_lost [05:05] */ 26380 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_LOST_MASK 0x0020 26381 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_LOST_ALIGN 0 26382 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_LOST_BITS 1 26383 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_LOST_SHIFT 5 26384 26385 /* XgxsBlk9 :: R2_status :: rx66_R2_frame_lock_0_lost [04:04] */ 26386 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_LOST_MASK 0x0010 26387 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_LOST_ALIGN 0 26388 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_LOST_BITS 1 26389 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_LOST_SHIFT 4 26390 26391 /* XgxsBlk9 :: R2_status :: rx66_R2_deskew_lock_lost [03:03] */ 26392 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_LOST_MASK 0x0008 26393 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_LOST_ALIGN 0 26394 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_LOST_BITS 1 26395 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_LOST_SHIFT 3 26396 26397 /* XgxsBlk9 :: R2_status :: rx66_R2_frame_lock_1 [02:02] */ 26398 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_MASK 0x0004 26399 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_ALIGN 0 26400 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_BITS 1 26401 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_SHIFT 2 26402 26403 /* XgxsBlk9 :: R2_status :: rx66_R2_frame_lock_0 [01:01] */ 26404 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_MASK 0x0002 26405 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_ALIGN 0 26406 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_BITS 1 26407 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_SHIFT 1 26408 26409 /* XgxsBlk9 :: R2_status :: rx66_R2_deskew_lock [00:00] */ 26410 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_MASK 0x0001 26411 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_ALIGN 0 26412 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_BITS 1 26413 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_SHIFT 0 26414 26415 26416 /**************************************************************************** 26417 * XgxsBlk9 :: R2_deskew_control 26418 */ 26419 /* XgxsBlk9 :: R2_deskew_control :: reserved_for_eco0 [15:08] */ 26420 #define XGXSBLK9_R2_DESKEW_CONTROL_RESERVED_FOR_ECO0_MASK 0xff00 26421 #define XGXSBLK9_R2_DESKEW_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 26422 #define XGXSBLK9_R2_DESKEW_CONTROL_RESERVED_FOR_ECO0_BITS 8 26423 #define XGXSBLK9_R2_DESKEW_CONTROL_RESERVED_FOR_ECO0_SHIFT 8 26424 26425 /* XgxsBlk9 :: R2_deskew_control :: R2_link_block_lock_cya [07:07] */ 26426 #define XGXSBLK9_R2_DESKEW_CONTROL_R2_LINK_BLOCK_LOCK_CYA_MASK 0x0080 26427 #define XGXSBLK9_R2_DESKEW_CONTROL_R2_LINK_BLOCK_LOCK_CYA_ALIGN 0 26428 #define XGXSBLK9_R2_DESKEW_CONTROL_R2_LINK_BLOCK_LOCK_CYA_BITS 1 26429 #define XGXSBLK9_R2_DESKEW_CONTROL_R2_LINK_BLOCK_LOCK_CYA_SHIFT 7 26430 26431 /* XgxsBlk9 :: R2_deskew_control :: xgxsBlk9_mdio_R2_mode_strap [06:06] */ 26432 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_MODE_STRAP_MASK 0x0040 26433 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_MODE_STRAP_ALIGN 0 26434 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_MODE_STRAP_BITS 1 26435 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_MODE_STRAP_SHIFT 6 26436 26437 /* XgxsBlk9 :: R2_deskew_control :: xgxsBlk9_mdio_R2_deskew_ovr [05:00] */ 26438 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_DESKEW_OVR_MASK 0x003f 26439 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_DESKEW_OVR_ALIGN 0 26440 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_DESKEW_OVR_BITS 6 26441 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_DESKEW_OVR_SHIFT 0 26442 26443 26444 /**************************************************************************** 26445 * Warpcore_USER_XgxsBlk10 26446 */ 26447 /**************************************************************************** 26448 * XgxsBlk10 :: tx_pi_control4 26449 */ 26450 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_sm_enable_override [15:15] */ 26451 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_MASK 0x8000 26452 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_ALIGN 0 26453 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_BITS 1 26454 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_SHIFT 15 26455 26456 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_sm_enable_override_value [14:14] */ 26457 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_MASK 0x4000 26458 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_ALIGN 0 26459 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_BITS 1 26460 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_SHIFT 14 26461 26462 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_cdr_lkdt_override [13:13] */ 26463 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_MASK 0x2000 26464 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_ALIGN 0 26465 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_BITS 1 26466 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_SHIFT 13 26467 26468 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_cdr_lkdt_override_value [12:12] */ 26469 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_MASK 0x1000 26470 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_ALIGN 0 26471 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_BITS 1 26472 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_SHIFT 12 26473 26474 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_halfSpd_override_ctl [11:11] */ 26475 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_MASK 0x0800 26476 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_ALIGN 0 26477 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_BITS 1 26478 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_SHIFT 11 26479 26480 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_halfSpd_ctl [10:10] */ 26481 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_MASK 0x0400 26482 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_ALIGN 0 26483 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_BITS 1 26484 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_SHIFT 10 26485 26486 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_loopback_mode_override_ctl [09:09] */ 26487 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_MASK 0x0200 26488 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_ALIGN 0 26489 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_BITS 1 26490 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_SHIFT 9 26491 26492 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_loopback_mode_ctl [08:08] */ 26493 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_MASK 0x0100 26494 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_ALIGN 0 26495 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_BITS 1 26496 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_SHIFT 8 26497 26498 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_status3_mux_sel [07:06] */ 26499 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_MASK 0x00c0 26500 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_ALIGN 0 26501 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_BITS 2 26502 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_SHIFT 6 26503 26504 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_status_latch [05:05] */ 26505 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_MASK 0x0020 26506 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_ALIGN 0 26507 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_BITS 1 26508 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_SHIFT 5 26509 26510 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_prop_bypass [04:04] */ 26511 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_MASK 0x0010 26512 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_ALIGN 0 26513 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_BITS 1 26514 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_SHIFT 4 26515 26516 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_prop_gain [03:01] */ 26517 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_GAIN_MASK 0x000e 26518 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_GAIN_ALIGN 0 26519 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_GAIN_BITS 3 26520 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_GAIN_SHIFT 1 26521 26522 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_prop_acq [00:00] */ 26523 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_ACQ_MASK 0x0001 26524 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_ACQ_ALIGN 0 26525 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_ACQ_BITS 1 26526 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_ACQ_SHIFT 0 26527 26528 26529 /**************************************************************************** 26530 * XgxsBlk10 :: xfi_afe_ctl1 26531 */ 26532 /* XgxsBlk10 :: xfi_afe_ctl1 :: xfi_afe_ctl1 [15:00] */ 26533 #define XGXSBLK10_XFI_AFE_CTL1_XFI_AFE_CTL1_MASK 0xffff 26534 #define XGXSBLK10_XFI_AFE_CTL1_XFI_AFE_CTL1_ALIGN 0 26535 #define XGXSBLK10_XFI_AFE_CTL1_XFI_AFE_CTL1_BITS 16 26536 #define XGXSBLK10_XFI_AFE_CTL1_XFI_AFE_CTL1_SHIFT 0 26537 26538 26539 /**************************************************************************** 26540 * XgxsBlk10 :: xfi_afe_ctl2 26541 */ 26542 /* XgxsBlk10 :: xfi_afe_ctl2 :: xfi_afe_ctl2 [15:00] */ 26543 #define XGXSBLK10_XFI_AFE_CTL2_XFI_AFE_CTL2_MASK 0xffff 26544 #define XGXSBLK10_XFI_AFE_CTL2_XFI_AFE_CTL2_ALIGN 0 26545 #define XGXSBLK10_XFI_AFE_CTL2_XFI_AFE_CTL2_BITS 16 26546 #define XGXSBLK10_XFI_AFE_CTL2_XFI_AFE_CTL2_SHIFT 0 26547 26548 26549 /**************************************************************************** 26550 * XgxsBlk10 :: xfi_afe_acjval 26551 */ 26552 /* XgxsBlk10 :: xfi_afe_acjval :: xfi_afe_acjval [15:00] */ 26553 #define XGXSBLK10_XFI_AFE_ACJVAL_XFI_AFE_ACJVAL_MASK 0xffff 26554 #define XGXSBLK10_XFI_AFE_ACJVAL_XFI_AFE_ACJVAL_ALIGN 0 26555 #define XGXSBLK10_XFI_AFE_ACJVAL_XFI_AFE_ACJVAL_BITS 16 26556 #define XGXSBLK10_XFI_AFE_ACJVAL_XFI_AFE_ACJVAL_SHIFT 0 26557 26558 26559 /**************************************************************************** 26560 * XgxsBlk10 :: tx_pi_status3 26561 */ 26562 /* XgxsBlk10 :: tx_pi_status3 :: tx_pi_phase_ctrl [15:00] */ 26563 #define XGXSBLK10_TX_PI_STATUS3_TX_PI_PHASE_CTRL_MASK 0xffff 26564 #define XGXSBLK10_TX_PI_STATUS3_TX_PI_PHASE_CTRL_ALIGN 0 26565 #define XGXSBLK10_TX_PI_STATUS3_TX_PI_PHASE_CTRL_BITS 16 26566 #define XGXSBLK10_TX_PI_STATUS3_TX_PI_PHASE_CTRL_SHIFT 0 26567 26568 26569 /**************************************************************************** 26570 * XgxsBlk10 :: tx_pi_status4 26571 */ 26572 /* XgxsBlk10 :: tx_pi_status4 :: reserved_for_eco0 [15:02] */ 26573 #define XGXSBLK10_TX_PI_STATUS4_RESERVED_FOR_ECO0_MASK 0xfffc 26574 #define XGXSBLK10_TX_PI_STATUS4_RESERVED_FOR_ECO0_ALIGN 0 26575 #define XGXSBLK10_TX_PI_STATUS4_RESERVED_FOR_ECO0_BITS 14 26576 #define XGXSBLK10_TX_PI_STATUS4_RESERVED_FOR_ECO0_SHIFT 2 26577 26578 /* XgxsBlk10 :: tx_pi_status4 :: tx_pi_sm_en [01:01] */ 26579 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_EN_MASK 0x0002 26580 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_EN_ALIGN 0 26581 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_EN_BITS 1 26582 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_EN_SHIFT 1 26583 26584 /* XgxsBlk10 :: tx_pi_status4 :: tx_pi_sm_done [00:00] */ 26585 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_DONE_MASK 0x0001 26586 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_DONE_ALIGN 0 26587 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_DONE_BITS 1 26588 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_DONE_SHIFT 0 26589 26590 26591 /**************************************************************************** 26592 * XgxsBlk10 :: tx_pi_control5 26593 */ 26594 /* XgxsBlk10 :: tx_pi_control5 :: reserved_for_eco0 [15:05] */ 26595 #define XGXSBLK10_TX_PI_CONTROL5_RESERVED_FOR_ECO0_MASK 0xffe0 26596 #define XGXSBLK10_TX_PI_CONTROL5_RESERVED_FOR_ECO0_ALIGN 0 26597 #define XGXSBLK10_TX_PI_CONTROL5_RESERVED_FOR_ECO0_BITS 11 26598 #define XGXSBLK10_TX_PI_CONTROL5_RESERVED_FOR_ECO0_SHIFT 5 26599 26600 /* XgxsBlk10 :: tx_pi_control5 :: rxfifo_depth_sel [04:01] */ 26601 #define XGXSBLK10_TX_PI_CONTROL5_RXFIFO_DEPTH_SEL_MASK 0x001e 26602 #define XGXSBLK10_TX_PI_CONTROL5_RXFIFO_DEPTH_SEL_ALIGN 0 26603 #define XGXSBLK10_TX_PI_CONTROL5_RXFIFO_DEPTH_SEL_BITS 4 26604 #define XGXSBLK10_TX_PI_CONTROL5_RXFIFO_DEPTH_SEL_SHIFT 1 26605 26606 /* XgxsBlk10 :: tx_pi_control5 :: tx_pi_sm_rst [00:00] */ 26607 #define XGXSBLK10_TX_PI_CONTROL5_TX_PI_SM_RST_MASK 0x0001 26608 #define XGXSBLK10_TX_PI_CONTROL5_TX_PI_SM_RST_ALIGN 0 26609 #define XGXSBLK10_TX_PI_CONTROL5_TX_PI_SM_RST_BITS 1 26610 #define XGXSBLK10_TX_PI_CONTROL5_TX_PI_SM_RST_SHIFT 0 26611 26612 26613 /**************************************************************************** 26614 * XgxsBlk10 :: misc_control 26615 */ 26616 /* XgxsBlk10 :: misc_control :: master_slave_lanes_override [15:15] */ 26617 #define XGXSBLK10_MISC_CONTROL_MASTER_SLAVE_LANES_OVERRIDE_MASK 0x8000 26618 #define XGXSBLK10_MISC_CONTROL_MASTER_SLAVE_LANES_OVERRIDE_ALIGN 0 26619 #define XGXSBLK10_MISC_CONTROL_MASTER_SLAVE_LANES_OVERRIDE_BITS 1 26620 #define XGXSBLK10_MISC_CONTROL_MASTER_SLAVE_LANES_OVERRIDE_SHIFT 15 26621 26622 /* XgxsBlk10 :: misc_control :: master_slave_lanes_override_value [14:12] */ 26623 #define XGXSBLK10_MISC_CONTROL_MASTER_SLAVE_LANES_OVERRIDE_VALUE_MASK 0x7000 26624 #define XGXSBLK10_MISC_CONTROL_MASTER_SLAVE_LANES_OVERRIDE_VALUE_ALIGN 0 26625 #define XGXSBLK10_MISC_CONTROL_MASTER_SLAVE_LANES_OVERRIDE_VALUE_BITS 3 26626 #define XGXSBLK10_MISC_CONTROL_MASTER_SLAVE_LANES_OVERRIDE_VALUE_SHIFT 12 26627 26628 /* XgxsBlk10 :: misc_control :: slave_wakeup_override [11:11] */ 26629 #define XGXSBLK10_MISC_CONTROL_SLAVE_WAKEUP_OVERRIDE_MASK 0x0800 26630 #define XGXSBLK10_MISC_CONTROL_SLAVE_WAKEUP_OVERRIDE_ALIGN 0 26631 #define XGXSBLK10_MISC_CONTROL_SLAVE_WAKEUP_OVERRIDE_BITS 1 26632 #define XGXSBLK10_MISC_CONTROL_SLAVE_WAKEUP_OVERRIDE_SHIFT 11 26633 26634 /* XgxsBlk10 :: misc_control :: slave_wakeup_override_value [10:10] */ 26635 #define XGXSBLK10_MISC_CONTROL_SLAVE_WAKEUP_OVERRIDE_VALUE_MASK 0x0400 26636 #define XGXSBLK10_MISC_CONTROL_SLAVE_WAKEUP_OVERRIDE_VALUE_ALIGN 0 26637 #define XGXSBLK10_MISC_CONTROL_SLAVE_WAKEUP_OVERRIDE_VALUE_BITS 1 26638 #define XGXSBLK10_MISC_CONTROL_SLAVE_WAKEUP_OVERRIDE_VALUE_SHIFT 10 26639 26640 /* XgxsBlk10 :: misc_control :: pwrdwn_slave_disable [09:09] */ 26641 #define XGXSBLK10_MISC_CONTROL_PWRDWN_SLAVE_DISABLE_MASK 0x0200 26642 #define XGXSBLK10_MISC_CONTROL_PWRDWN_SLAVE_DISABLE_ALIGN 0 26643 #define XGXSBLK10_MISC_CONTROL_PWRDWN_SLAVE_DISABLE_BITS 1 26644 #define XGXSBLK10_MISC_CONTROL_PWRDWN_SLAVE_DISABLE_SHIFT 9 26645 26646 /* XgxsBlk10 :: misc_control :: reserved_for_eco0 [08:03] */ 26647 #define XGXSBLK10_MISC_CONTROL_RESERVED_FOR_ECO0_MASK 0x01f8 26648 #define XGXSBLK10_MISC_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 26649 #define XGXSBLK10_MISC_CONTROL_RESERVED_FOR_ECO0_BITS 6 26650 #define XGXSBLK10_MISC_CONTROL_RESERVED_FOR_ECO0_SHIFT 3 26651 26652 /* XgxsBlk10 :: misc_control :: clk16_disable [02:02] */ 26653 #define XGXSBLK10_MISC_CONTROL_CLK16_DISABLE_MASK 0x0004 26654 #define XGXSBLK10_MISC_CONTROL_CLK16_DISABLE_ALIGN 0 26655 #define XGXSBLK10_MISC_CONTROL_CLK16_DISABLE_BITS 1 26656 #define XGXSBLK10_MISC_CONTROL_CLK16_DISABLE_SHIFT 2 26657 26658 /* XgxsBlk10 :: misc_control :: clk30_disable [01:01] */ 26659 #define XGXSBLK10_MISC_CONTROL_CLK30_DISABLE_MASK 0x0002 26660 #define XGXSBLK10_MISC_CONTROL_CLK30_DISABLE_ALIGN 0 26661 #define XGXSBLK10_MISC_CONTROL_CLK30_DISABLE_BITS 1 26662 #define XGXSBLK10_MISC_CONTROL_CLK30_DISABLE_SHIFT 1 26663 26664 /* XgxsBlk10 :: misc_control :: force_pcb_en_sync [00:00] */ 26665 #define XGXSBLK10_MISC_CONTROL_FORCE_PCB_EN_SYNC_MASK 0x0001 26666 #define XGXSBLK10_MISC_CONTROL_FORCE_PCB_EN_SYNC_ALIGN 0 26667 #define XGXSBLK10_MISC_CONTROL_FORCE_PCB_EN_SYNC_BITS 1 26668 #define XGXSBLK10_MISC_CONTROL_FORCE_PCB_EN_SYNC_SHIFT 0 26669 26670 26671 /**************************************************************************** 26672 * Warpcore_USER_GP2_reg 26673 */ 26674 /**************************************************************************** 26675 * GP2_reg :: GP2_0 26676 */ 26677 /* GP2_reg :: GP2_0 :: pll_mode [15:12] */ 26678 #define GP2_REG_GP2_0_PLL_MODE_MASK 0xf000 26679 #define GP2_REG_GP2_0_PLL_MODE_ALIGN 0 26680 #define GP2_REG_GP2_0_PLL_MODE_BITS 4 26681 #define GP2_REG_GP2_0_PLL_MODE_SHIFT 12 26682 26683 /* GP2_reg :: GP2_0 :: sigdet [11:08] */ 26684 #define GP2_REG_GP2_0_SIGDET_MASK 0x0f00 26685 #define GP2_REG_GP2_0_SIGDET_ALIGN 0 26686 #define GP2_REG_GP2_0_SIGDET_BITS 4 26687 #define GP2_REG_GP2_0_SIGDET_SHIFT 8 26688 26689 /* GP2_reg :: GP2_0 :: pll_lock_1g [07:04] */ 26690 #define GP2_REG_GP2_0_PLL_LOCK_1G_MASK 0x00f0 26691 #define GP2_REG_GP2_0_PLL_LOCK_1G_ALIGN 0 26692 #define GP2_REG_GP2_0_PLL_LOCK_1G_BITS 4 26693 #define GP2_REG_GP2_0_PLL_LOCK_1G_SHIFT 4 26694 26695 /* GP2_reg :: GP2_0 :: sync_status_combo [03:00] */ 26696 #define GP2_REG_GP2_0_SYNC_STATUS_COMBO_MASK 0x000f 26697 #define GP2_REG_GP2_0_SYNC_STATUS_COMBO_ALIGN 0 26698 #define GP2_REG_GP2_0_SYNC_STATUS_COMBO_BITS 4 26699 #define GP2_REG_GP2_0_SYNC_STATUS_COMBO_SHIFT 0 26700 26701 26702 /**************************************************************************** 26703 * GP2_reg :: GP2_1 26704 */ 26705 /* GP2_reg :: GP2_1 :: link_KR [15:12] */ 26706 #define GP2_REG_GP2_1_LINK_KR_MASK 0xf000 26707 #define GP2_REG_GP2_1_LINK_KR_ALIGN 0 26708 #define GP2_REG_GP2_1_LINK_KR_BITS 4 26709 #define GP2_REG_GP2_1_LINK_KR_SHIFT 12 26710 26711 /* GP2_reg :: GP2_1 :: link_status [11:08] */ 26712 #define GP2_REG_GP2_1_LINK_STATUS_MASK 0x0f00 26713 #define GP2_REG_GP2_1_LINK_STATUS_ALIGN 0 26714 #define GP2_REG_GP2_1_LINK_STATUS_BITS 4 26715 #define GP2_REG_GP2_1_LINK_STATUS_SHIFT 8 26716 26717 /* GP2_reg :: GP2_1 :: link_100fx [07:04] */ 26718 #define GP2_REG_GP2_1_LINK_100FX_MASK 0x00f0 26719 #define GP2_REG_GP2_1_LINK_100FX_ALIGN 0 26720 #define GP2_REG_GP2_1_LINK_100FX_BITS 4 26721 #define GP2_REG_GP2_1_LINK_100FX_SHIFT 4 26722 26723 /* GP2_reg :: GP2_1 :: link_an [03:00] */ 26724 #define GP2_REG_GP2_1_LINK_AN_MASK 0x000f 26725 #define GP2_REG_GP2_1_LINK_AN_ALIGN 0 26726 #define GP2_REG_GP2_1_LINK_AN_BITS 4 26727 #define GP2_REG_GP2_1_LINK_AN_SHIFT 0 26728 26729 26730 /**************************************************************************** 26731 * GP2_reg :: GP2_2 26732 */ 26733 /* GP2_reg :: GP2_2 :: reserved0 [15:14] */ 26734 #define GP2_REG_GP2_2_RESERVED0_MASK 0xc000 26735 #define GP2_REG_GP2_2_RESERVED0_ALIGN 0 26736 #define GP2_REG_GP2_2_RESERVED0_BITS 2 26737 #define GP2_REG_GP2_2_RESERVED0_SHIFT 14 26738 26739 /* manually added */ 26740 #define WL_GP2_REG_GP2_2_ACTUAL_SPEED_LN1_MASK 0x7f00 26741 26742 26743 /* GP2_reg :: GP2_2 :: actual_speed_ln1 [13:08] */ 26744 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_MASK 0x3f00 26745 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_ALIGN 0 26746 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_BITS 6 26747 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_SHIFT 8 26748 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10M 0 26749 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_100M 1 26750 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_1G 2 26751 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_2p5G 3 26752 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_5G_X4 4 26753 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_6G_X4 5 26754 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_HiG 6 26755 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_CX4 7 26756 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_12G_HiG 8 26757 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_12p5G_X4 9 26758 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_13G_X4 10 26759 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_15G_X4 11 26760 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_16G_X4 12 26761 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_1G_KX 13 26762 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_KX4 14 26763 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_KR 15 26764 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_5G 16 26765 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_6p4G 17 26766 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_20G_X4 18 26767 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_21G_X4 19 26768 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_25G_X4 20 26769 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_HiG_DXGXS 21 26770 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_DXGXS 22 26771 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10p5G_HiG_DXGXS 23 26772 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10p5G_DXGXS 24 26773 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_12p773G_HiG_DXGXS 25 26774 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_12p773G_DXGXS 26 26775 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_XFI 27 26776 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_40G 28 26777 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_20G_HiG_DXGXS 29 26778 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_20G_DXGXS 30 26779 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_SFI 31 26780 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_31p5G 32 26781 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_32p7G 33 26782 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_20G_SCR 34 26783 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_HiG_DXGXS_SCR 35 26784 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_DXGXS_SCR 36 26785 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_12G_R2 37 26786 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_10G_X2 38 26787 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_40G_KR4 39 26788 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_40G_CR4 40 26789 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_100G_CR10 41 26790 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_15p75G_DXGXS 44 26791 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_20G_KR2 57 26792 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_dr_20G_CR2 58 26793 26794 /* GP2_reg :: GP2_2 :: reserved1 [07:06] */ 26795 #define GP2_REG_GP2_2_RESERVED1_MASK 0x00c0 26796 #define GP2_REG_GP2_2_RESERVED1_ALIGN 0 26797 #define GP2_REG_GP2_2_RESERVED1_BITS 2 26798 #define GP2_REG_GP2_2_RESERVED1_SHIFT 6 26799 26800 /* manually added for WL */ 26801 #define WL_GP2_REG_GP2_2_ACTUAL_SPEED_LN0_MASK 0x007f 26802 26803 26804 /* GP2_reg :: GP2_2 :: actual_speed_ln0 [05:00] */ 26805 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_MASK 0x003f 26806 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_ALIGN 0 26807 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_BITS 6 26808 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_SHIFT 0 26809 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10M 0 26810 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_100M 1 26811 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_1G 2 26812 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_2p5G 3 26813 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_5G_X4 4 26814 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_6G_X4 5 26815 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_HiG 6 26816 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_CX4 7 26817 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_12G_HiG 8 26818 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_12p5G_X4 9 26819 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_13G_X4 10 26820 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_15G_X4 11 26821 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_16G_X4 12 26822 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_1G_KX 13 26823 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_KX4 14 26824 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_KR 15 26825 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_5G 16 26826 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_6p4G 17 26827 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_20G_X4 18 26828 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_21G_X4 19 26829 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_25G_X4 20 26830 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_HiG_DXGXS 21 26831 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_DXGXS 22 26832 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10p5G_HiG_DXGXS 23 26833 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10p5G_DXGXS 24 26834 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_12p773G_HiG_DXGXS 25 26835 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_12p773G_DXGXS 26 26836 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_XFI 27 26837 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_40G 28 26838 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_20G_HiG_DXGXS 29 26839 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_20G_DXGXS 30 26840 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_SFI 31 26841 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_31p5G 32 26842 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_32p7G 33 26843 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_20G_SCR 34 26844 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_HiG_DXGXS_SCR 35 26845 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_DXGXS_SCR 36 26846 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_12G_R2 37 26847 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_10G_X2 38 26848 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_40G_KR4 39 26849 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_40G_CR4 40 26850 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_100G_CR10 41 26851 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_15p75G_DXGXS 44 26852 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_20G_KR2 57 26853 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_dr_20G_CR2 58 26854 26855 26856 /**************************************************************************** 26857 * GP2_reg :: GP2_3 26858 */ 26859 /* GP2_reg :: GP2_3 :: reserved0 [15:14] */ 26860 #define GP2_REG_GP2_3_RESERVED0_MASK 0xc000 26861 #define GP2_REG_GP2_3_RESERVED0_ALIGN 0 26862 #define GP2_REG_GP2_3_RESERVED0_BITS 2 26863 #define GP2_REG_GP2_3_RESERVED0_SHIFT 14 26864 26865 /* manually added */ 26866 #define WL_GP2_REG_GP2_3_ACTUAL_SPEED_LN3_MASK 0x7f00 26867 26868 26869 /* GP2_reg :: GP2_3 :: actual_speed_ln3 [13:08] */ 26870 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_MASK 0x3f00 26871 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_ALIGN 0 26872 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_BITS 6 26873 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_SHIFT 8 26874 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10M 0 26875 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_100M 1 26876 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_1G 2 26877 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_2p5G 3 26878 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_5G_X4 4 26879 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_6G_X4 5 26880 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_HiG 6 26881 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_CX4 7 26882 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_12G_HiG 8 26883 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_12p5G_X4 9 26884 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_13G_X4 10 26885 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_15G_X4 11 26886 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_16G_X4 12 26887 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_1G_KX 13 26888 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_KX4 14 26889 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_KR 15 26890 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_5G 16 26891 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_6p4G 17 26892 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_20G_X4 18 26893 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_21G_X4 19 26894 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_25G_X4 20 26895 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_HiG_DXGXS 21 26896 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_DXGXS 22 26897 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10p5G_HiG_DXGXS 23 26898 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10p5G_DXGXS 24 26899 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_12p773G_HiG_DXGXS 25 26900 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_12p773G_DXGXS 26 26901 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_XFI 27 26902 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_40G 28 26903 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_20G_HiG_DXGXS 29 26904 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_20G_DXGXS 30 26905 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_SFI 31 26906 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_31p5G 32 26907 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_32p7G 33 26908 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_20G_SCR 34 26909 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_HiG_DXGXS_SCR 35 26910 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_DXGXS_SCR 36 26911 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_12G_R2 37 26912 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_10G_X2 38 26913 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_40G_KR4 39 26914 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_40G_CR4 40 26915 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_100G_CR10 41 26916 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_15p75G_DXGXS 44 26917 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_20G_KR2 57 26918 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_dr_20G_CR2 58 26919 26920 /* GP2_reg :: GP2_3 :: reserved1 [07:06] */ 26921 #define GP2_REG_GP2_3_RESERVED1_MASK 0x00c0 26922 #define GP2_REG_GP2_3_RESERVED1_ALIGN 0 26923 #define GP2_REG_GP2_3_RESERVED1_BITS 2 26924 #define GP2_REG_GP2_3_RESERVED1_SHIFT 6 26925 26926 /* manually added */ 26927 #define WL_GP2_REG_GP2_3_ACTUAL_SPEED_LN2_MASK 0x007f 26928 26929 26930 /* GP2_reg :: GP2_3 :: actual_speed_ln2 [05:00] */ 26931 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_MASK 0x003f 26932 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_ALIGN 0 26933 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_BITS 6 26934 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_SHIFT 0 26935 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10M 0 26936 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_100M 1 26937 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_1G 2 26938 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_2p5G 3 26939 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_5G_X4 4 26940 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_6G_X4 5 26941 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_HiG 6 26942 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_CX4 7 26943 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_12G_HiG 8 26944 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_12p5G_X4 9 26945 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_13G_X4 10 26946 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_15G_X4 11 26947 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_16G_X4 12 26948 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_1G_KX 13 26949 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_KX4 14 26950 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_KR 15 26951 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_5G 16 26952 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_6p4G 17 26953 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_20G_X4 18 26954 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_21G_X4 19 26955 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_25G_X4 20 26956 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_HiG_DXGXS 21 26957 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_DXGXS 22 26958 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10p5G_HiG_DXGXS 23 26959 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10p5G_DXGXS 24 26960 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_12p773G_HiG_DXGXS 25 26961 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_12p773G_DXGXS 26 26962 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_XFI 27 26963 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_40G 28 26964 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_20G_HiG_DXGXS 29 26965 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_20G_DXGXS 30 26966 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_SFI 31 26967 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_31p5G 32 26968 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_32p7G 33 26969 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_20G_SCR 34 26970 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_HiG_DXGXS_SCR 35 26971 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_DXGXS_SCR 36 26972 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_12G_R2 37 26973 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_10G_X2 38 26974 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_40G_KR4 39 26975 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_40G_CR4 40 26976 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_100G_CR10 41 26977 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_15p75G_DXGXS 44 26978 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_20G_KR2 57 26979 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_dr_20G_CR2 58 26980 26981 26982 /**************************************************************************** 26983 * GP2_reg :: GP2_4 26984 */ 26985 /* GP2_reg :: GP2_4 :: cl73_autoneg_complete [15:12] */ 26986 #define GP2_REG_GP2_4_CL73_AUTONEG_COMPLETE_MASK 0xf000 26987 #define GP2_REG_GP2_4_CL73_AUTONEG_COMPLETE_ALIGN 0 26988 #define GP2_REG_GP2_4_CL73_AUTONEG_COMPLETE_BITS 4 26989 #define GP2_REG_GP2_4_CL73_AUTONEG_COMPLETE_SHIFT 12 26990 26991 /* GP2_reg :: GP2_4 :: autoneg_complete [11:08] */ 26992 #define GP2_REG_GP2_4_AUTONEG_COMPLETE_MASK 0x0f00 26993 #define GP2_REG_GP2_4_AUTONEG_COMPLETE_ALIGN 0 26994 #define GP2_REG_GP2_4_AUTONEG_COMPLETE_BITS 4 26995 #define GP2_REG_GP2_4_AUTONEG_COMPLETE_SHIFT 8 26996 26997 /* GP2_reg :: GP2_4 :: cl73_mr_lp_autoneg_able [07:04] */ 26998 #define GP2_REG_GP2_4_CL73_MR_LP_AUTONEG_ABLE_MASK 0x00f0 26999 #define GP2_REG_GP2_4_CL73_MR_LP_AUTONEG_ABLE_ALIGN 0 27000 #define GP2_REG_GP2_4_CL73_MR_LP_AUTONEG_ABLE_BITS 4 27001 #define GP2_REG_GP2_4_CL73_MR_LP_AUTONEG_ABLE_SHIFT 4 27002 27003 /* GP2_reg :: GP2_4 :: cl73_mr_autoneg_able [03:00] */ 27004 #define GP2_REG_GP2_4_CL73_MR_AUTONEG_ABLE_MASK 0x000f 27005 #define GP2_REG_GP2_4_CL73_MR_AUTONEG_ABLE_ALIGN 0 27006 #define GP2_REG_GP2_4_CL73_MR_AUTONEG_ABLE_BITS 4 27007 #define GP2_REG_GP2_4_CL73_MR_AUTONEG_ABLE_SHIFT 0 27008 27009 27010 /**************************************************************************** 27011 * GP2_reg :: GP2_5 27012 */ 27013 /* GP2_reg :: GP2_5 :: Cl73_BAMStat1_ln0 [15:00] */ 27014 #define GP2_REG_GP2_5_CL73_BAMSTAT1_LN0_MASK 0xffff 27015 #define GP2_REG_GP2_5_CL73_BAMSTAT1_LN0_ALIGN 0 27016 #define GP2_REG_GP2_5_CL73_BAMSTAT1_LN0_BITS 16 27017 #define GP2_REG_GP2_5_CL73_BAMSTAT1_LN0_SHIFT 0 27018 27019 27020 /**************************************************************************** 27021 * GP2_reg :: GP2_6 27022 */ 27023 /* GP2_reg :: GP2_6 :: Cl73_BAMStat2_ln0 [15:00] */ 27024 #define GP2_REG_GP2_6_CL73_BAMSTAT2_LN0_MASK 0xffff 27025 #define GP2_REG_GP2_6_CL73_BAMSTAT2_LN0_ALIGN 0 27026 #define GP2_REG_GP2_6_CL73_BAMSTAT2_LN0_BITS 16 27027 #define GP2_REG_GP2_6_CL73_BAMSTAT2_LN0_SHIFT 0 27028 27029 27030 /**************************************************************************** 27031 * GP2_reg :: GP2_7 27032 */ 27033 /* GP2_reg :: GP2_7 :: Cl73_BAMStat3_ln0 [15:00] */ 27034 #define GP2_REG_GP2_7_CL73_BAMSTAT3_LN0_MASK 0xffff 27035 #define GP2_REG_GP2_7_CL73_BAMSTAT3_LN0_ALIGN 0 27036 #define GP2_REG_GP2_7_CL73_BAMSTAT3_LN0_BITS 16 27037 #define GP2_REG_GP2_7_CL73_BAMSTAT3_LN0_SHIFT 0 27038 27039 27040 /**************************************************************************** 27041 * GP2_reg :: GP2_8 27042 */ 27043 /* GP2_reg :: GP2_8 :: reserved0 [15:09] */ 27044 #define GP2_REG_GP2_8_RESERVED0_MASK 0xfe00 27045 #define GP2_REG_GP2_8_RESERVED0_ALIGN 0 27046 #define GP2_REG_GP2_8_RESERVED0_BITS 7 27047 #define GP2_REG_GP2_8_RESERVED0_SHIFT 9 27048 27049 /* GP2_reg :: GP2_8 :: micro_init_done [08:08] */ 27050 #define GP2_REG_GP2_8_MICRO_INIT_DONE_MASK 0x0100 27051 #define GP2_REG_GP2_8_MICRO_INIT_DONE_ALIGN 0 27052 #define GP2_REG_GP2_8_MICRO_INIT_DONE_BITS 1 27053 #define GP2_REG_GP2_8_MICRO_INIT_DONE_SHIFT 8 27054 27055 /* GP2_reg :: GP2_8 :: micro_fsm [07:04] */ 27056 #define GP2_REG_GP2_8_MICRO_FSM_MASK 0x00f0 27057 #define GP2_REG_GP2_8_MICRO_FSM_ALIGN 0 27058 #define GP2_REG_GP2_8_MICRO_FSM_BITS 4 27059 #define GP2_REG_GP2_8_MICRO_FSM_SHIFT 4 27060 27061 /* GP2_reg :: GP2_8 :: micro_err [03:02] */ 27062 #define GP2_REG_GP2_8_MICRO_ERR_MASK 0x000c 27063 #define GP2_REG_GP2_8_MICRO_ERR_ALIGN 0 27064 #define GP2_REG_GP2_8_MICRO_ERR_BITS 2 27065 #define GP2_REG_GP2_8_MICRO_ERR_SHIFT 2 27066 27067 /* GP2_reg :: GP2_8 :: micro_wdog [01:00] */ 27068 #define GP2_REG_GP2_8_MICRO_WDOG_MASK 0x0003 27069 #define GP2_REG_GP2_8_MICRO_WDOG_ALIGN 0 27070 #define GP2_REG_GP2_8_MICRO_WDOG_BITS 2 27071 #define GP2_REG_GP2_8_MICRO_WDOG_SHIFT 0 27072 27073 27074 /**************************************************************************** 27075 * GP2_reg :: GP2_9 27076 */ 27077 /* GP2_reg :: GP2_9 :: prbs_lock_ln0 [15:15] */ 27078 #define GP2_REG_GP2_9_PRBS_LOCK_LN0_MASK 0x8000 27079 #define GP2_REG_GP2_9_PRBS_LOCK_LN0_ALIGN 0 27080 #define GP2_REG_GP2_9_PRBS_LOCK_LN0_BITS 1 27081 #define GP2_REG_GP2_9_PRBS_LOCK_LN0_SHIFT 15 27082 27083 /* GP2_reg :: GP2_9 :: tx0_fir_tap_main [14:09] */ 27084 #define GP2_REG_GP2_9_TX0_FIR_TAP_MAIN_MASK 0x7e00 27085 #define GP2_REG_GP2_9_TX0_FIR_TAP_MAIN_ALIGN 0 27086 #define GP2_REG_GP2_9_TX0_FIR_TAP_MAIN_BITS 6 27087 #define GP2_REG_GP2_9_TX0_FIR_TAP_MAIN_SHIFT 9 27088 27089 /* GP2_reg :: GP2_9 :: tx0_fir_tap_pre [08:05] */ 27090 #define GP2_REG_GP2_9_TX0_FIR_TAP_PRE_MASK 0x01e0 27091 #define GP2_REG_GP2_9_TX0_FIR_TAP_PRE_ALIGN 0 27092 #define GP2_REG_GP2_9_TX0_FIR_TAP_PRE_BITS 4 27093 #define GP2_REG_GP2_9_TX0_FIR_TAP_PRE_SHIFT 5 27094 27095 /* GP2_reg :: GP2_9 :: tx0_fir_tap_post [04:00] */ 27096 #define GP2_REG_GP2_9_TX0_FIR_TAP_POST_MASK 0x001f 27097 #define GP2_REG_GP2_9_TX0_FIR_TAP_POST_ALIGN 0 27098 #define GP2_REG_GP2_9_TX0_FIR_TAP_POST_BITS 5 27099 #define GP2_REG_GP2_9_TX0_FIR_TAP_POST_SHIFT 0 27100 27101 27102 /**************************************************************************** 27103 * GP2_reg :: GP2_A 27104 */ 27105 /* GP2_reg :: GP2_A :: prbs_lock_ln1 [15:15] */ 27106 #define GP2_REG_GP2_A_PRBS_LOCK_LN1_MASK 0x8000 27107 #define GP2_REG_GP2_A_PRBS_LOCK_LN1_ALIGN 0 27108 #define GP2_REG_GP2_A_PRBS_LOCK_LN1_BITS 1 27109 #define GP2_REG_GP2_A_PRBS_LOCK_LN1_SHIFT 15 27110 27111 /* GP2_reg :: GP2_A :: tx1_fir_tap_main [14:09] */ 27112 #define GP2_REG_GP2_A_TX1_FIR_TAP_MAIN_MASK 0x7e00 27113 #define GP2_REG_GP2_A_TX1_FIR_TAP_MAIN_ALIGN 0 27114 #define GP2_REG_GP2_A_TX1_FIR_TAP_MAIN_BITS 6 27115 #define GP2_REG_GP2_A_TX1_FIR_TAP_MAIN_SHIFT 9 27116 27117 /* GP2_reg :: GP2_A :: tx1_fir_tap_pre [08:05] */ 27118 #define GP2_REG_GP2_A_TX1_FIR_TAP_PRE_MASK 0x01e0 27119 #define GP2_REG_GP2_A_TX1_FIR_TAP_PRE_ALIGN 0 27120 #define GP2_REG_GP2_A_TX1_FIR_TAP_PRE_BITS 4 27121 #define GP2_REG_GP2_A_TX1_FIR_TAP_PRE_SHIFT 5 27122 27123 /* GP2_reg :: GP2_A :: tx1_fir_tap_post [04:00] */ 27124 #define GP2_REG_GP2_A_TX1_FIR_TAP_POST_MASK 0x001f 27125 #define GP2_REG_GP2_A_TX1_FIR_TAP_POST_ALIGN 0 27126 #define GP2_REG_GP2_A_TX1_FIR_TAP_POST_BITS 5 27127 #define GP2_REG_GP2_A_TX1_FIR_TAP_POST_SHIFT 0 27128 27129 27130 /**************************************************************************** 27131 * GP2_reg :: GP2_B 27132 */ 27133 /* GP2_reg :: GP2_B :: prbs_lock_ln2 [15:15] */ 27134 #define GP2_REG_GP2_B_PRBS_LOCK_LN2_MASK 0x8000 27135 #define GP2_REG_GP2_B_PRBS_LOCK_LN2_ALIGN 0 27136 #define GP2_REG_GP2_B_PRBS_LOCK_LN2_BITS 1 27137 #define GP2_REG_GP2_B_PRBS_LOCK_LN2_SHIFT 15 27138 27139 /* GP2_reg :: GP2_B :: tx2_fir_tap_main [14:09] */ 27140 #define GP2_REG_GP2_B_TX2_FIR_TAP_MAIN_MASK 0x7e00 27141 #define GP2_REG_GP2_B_TX2_FIR_TAP_MAIN_ALIGN 0 27142 #define GP2_REG_GP2_B_TX2_FIR_TAP_MAIN_BITS 6 27143 #define GP2_REG_GP2_B_TX2_FIR_TAP_MAIN_SHIFT 9 27144 27145 /* GP2_reg :: GP2_B :: tx2_fir_tap_pre [08:05] */ 27146 #define GP2_REG_GP2_B_TX2_FIR_TAP_PRE_MASK 0x01e0 27147 #define GP2_REG_GP2_B_TX2_FIR_TAP_PRE_ALIGN 0 27148 #define GP2_REG_GP2_B_TX2_FIR_TAP_PRE_BITS 4 27149 #define GP2_REG_GP2_B_TX2_FIR_TAP_PRE_SHIFT 5 27150 27151 /* GP2_reg :: GP2_B :: tx2_fir_tap_post [04:00] */ 27152 #define GP2_REG_GP2_B_TX2_FIR_TAP_POST_MASK 0x001f 27153 #define GP2_REG_GP2_B_TX2_FIR_TAP_POST_ALIGN 0 27154 #define GP2_REG_GP2_B_TX2_FIR_TAP_POST_BITS 5 27155 #define GP2_REG_GP2_B_TX2_FIR_TAP_POST_SHIFT 0 27156 27157 27158 /**************************************************************************** 27159 * GP2_reg :: GP2_C 27160 */ 27161 /* GP2_reg :: GP2_C :: prbs_lock_ln3 [15:15] */ 27162 #define GP2_REG_GP2_C_PRBS_LOCK_LN3_MASK 0x8000 27163 #define GP2_REG_GP2_C_PRBS_LOCK_LN3_ALIGN 0 27164 #define GP2_REG_GP2_C_PRBS_LOCK_LN3_BITS 1 27165 #define GP2_REG_GP2_C_PRBS_LOCK_LN3_SHIFT 15 27166 27167 /* GP2_reg :: GP2_C :: tx3_fir_tap_main [14:09] */ 27168 #define GP2_REG_GP2_C_TX3_FIR_TAP_MAIN_MASK 0x7e00 27169 #define GP2_REG_GP2_C_TX3_FIR_TAP_MAIN_ALIGN 0 27170 #define GP2_REG_GP2_C_TX3_FIR_TAP_MAIN_BITS 6 27171 #define GP2_REG_GP2_C_TX3_FIR_TAP_MAIN_SHIFT 9 27172 27173 /* GP2_reg :: GP2_C :: tx3_fir_tap_pre [08:05] */ 27174 #define GP2_REG_GP2_C_TX3_FIR_TAP_PRE_MASK 0x01e0 27175 #define GP2_REG_GP2_C_TX3_FIR_TAP_PRE_ALIGN 0 27176 #define GP2_REG_GP2_C_TX3_FIR_TAP_PRE_BITS 4 27177 #define GP2_REG_GP2_C_TX3_FIR_TAP_PRE_SHIFT 5 27178 27179 /* GP2_reg :: GP2_C :: tx3_fir_tap_post [04:00] */ 27180 #define GP2_REG_GP2_C_TX3_FIR_TAP_POST_MASK 0x001f 27181 #define GP2_REG_GP2_C_TX3_FIR_TAP_POST_ALIGN 0 27182 #define GP2_REG_GP2_C_TX3_FIR_TAP_POST_BITS 5 27183 #define GP2_REG_GP2_C_TX3_FIR_TAP_POST_SHIFT 0 27184 27185 27186 /**************************************************************************** 27187 * GP2_reg :: GP2_D 27188 */ 27189 /* GP2_reg :: GP2_D :: reserved0 [15:08] */ 27190 #define GP2_REG_GP2_D_RESERVED0_MASK 0xff00 27191 #define GP2_REG_GP2_D_RESERVED0_ALIGN 0 27192 #define GP2_REG_GP2_D_RESERVED0_BITS 8 27193 #define GP2_REG_GP2_D_RESERVED0_SHIFT 8 27194 27195 /* GP2_reg :: GP2_D :: rx_LPI_rcvd [07:04] */ 27196 #define GP2_REG_GP2_D_RX_LPI_RCVD_MASK 0x00f0 27197 #define GP2_REG_GP2_D_RX_LPI_RCVD_ALIGN 0 27198 #define GP2_REG_GP2_D_RX_LPI_RCVD_BITS 4 27199 #define GP2_REG_GP2_D_RX_LPI_RCVD_SHIFT 4 27200 27201 /* GP2_reg :: GP2_D :: tx_LPI_rcvd [03:00] */ 27202 #define GP2_REG_GP2_D_TX_LPI_RCVD_MASK 0x000f 27203 #define GP2_REG_GP2_D_TX_LPI_RCVD_ALIGN 0 27204 #define GP2_REG_GP2_D_TX_LPI_RCVD_BITS 4 27205 #define GP2_REG_GP2_D_TX_LPI_RCVD_SHIFT 0 27206 27207 27208 /**************************************************************************** 27209 * GP2_reg :: GP2_E 27210 */ 27211 /* GP2_reg :: GP2_E :: cl49_en [15:12] */ 27212 #define GP2_REG_GP2_E_CL49_EN_MASK 0xf000 27213 #define GP2_REG_GP2_E_CL49_EN_ALIGN 0 27214 #define GP2_REG_GP2_E_CL49_EN_BITS 4 27215 #define GP2_REG_GP2_E_CL49_EN_SHIFT 12 27216 27217 /* GP2_reg :: GP2_E :: ed66en [11:08] */ 27218 #define GP2_REG_GP2_E_ED66EN_MASK 0x0f00 27219 #define GP2_REG_GP2_E_ED66EN_ALIGN 0 27220 #define GP2_REG_GP2_E_ED66EN_BITS 4 27221 #define GP2_REG_GP2_E_ED66EN_SHIFT 8 27222 27223 /* GP2_reg :: GP2_E :: fec_enable [07:04] */ 27224 #define GP2_REG_GP2_E_FEC_ENABLE_MASK 0x00f0 27225 #define GP2_REG_GP2_E_FEC_ENABLE_ALIGN 0 27226 #define GP2_REG_GP2_E_FEC_ENABLE_BITS 4 27227 #define GP2_REG_GP2_E_FEC_ENABLE_SHIFT 4 27228 27229 /* GP2_reg :: GP2_E :: fec_signal_Ok [03:00] */ 27230 #define GP2_REG_GP2_E_FEC_SIGNAL_OK_MASK 0x000f 27231 #define GP2_REG_GP2_E_FEC_SIGNAL_OK_ALIGN 0 27232 #define GP2_REG_GP2_E_FEC_SIGNAL_OK_BITS 4 27233 #define GP2_REG_GP2_E_FEC_SIGNAL_OK_SHIFT 0 27234 27235 27236 /**************************************************************************** 27237 * Warpcore_USER_uC_info_B0 27238 */ 27239 /**************************************************************************** 27240 * uC_info_B0 :: state_debug_ln0 27241 */ 27242 /* uC_info_B0 :: state_debug_ln0 :: CDR_LOCK_CORR [15:15] */ 27243 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_CORR_MASK 0x8000 27244 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_CORR_ALIGN 0 27245 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_CORR_BITS 1 27246 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_CORR_SHIFT 15 27247 27248 /* uC_info_B0 :: state_debug_ln0 :: DSC_DONE [14:14] */ 27249 #define UC_INFO_B0_STATE_DEBUG_LN0_DSC_DONE_MASK 0x4000 27250 #define UC_INFO_B0_STATE_DEBUG_LN0_DSC_DONE_ALIGN 0 27251 #define UC_INFO_B0_STATE_DEBUG_LN0_DSC_DONE_BITS 1 27252 #define UC_INFO_B0_STATE_DEBUG_LN0_DSC_DONE_SHIFT 14 27253 27254 /* uC_info_B0 :: state_debug_ln0 :: TUNING_DONE [13:13] */ 27255 #define UC_INFO_B0_STATE_DEBUG_LN0_TUNING_DONE_MASK 0x2000 27256 #define UC_INFO_B0_STATE_DEBUG_LN0_TUNING_DONE_ALIGN 0 27257 #define UC_INFO_B0_STATE_DEBUG_LN0_TUNING_DONE_BITS 1 27258 #define UC_INFO_B0_STATE_DEBUG_LN0_TUNING_DONE_SHIFT 13 27259 27260 /* uC_info_B0 :: state_debug_ln0 :: KR4_DIV16CK_BCST [12:12] */ 27261 #define UC_INFO_B0_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_MASK 0x1000 27262 #define UC_INFO_B0_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_ALIGN 0 27263 #define UC_INFO_B0_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_BITS 1 27264 #define UC_INFO_B0_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_SHIFT 12 27265 27266 /* uC_info_B0 :: state_debug_ln0 :: DCD_DFE_TUNING [11:11] */ 27267 #define UC_INFO_B0_STATE_DEBUG_LN0_DCD_DFE_TUNING_MASK 0x0800 27268 #define UC_INFO_B0_STATE_DEBUG_LN0_DCD_DFE_TUNING_ALIGN 0 27269 #define UC_INFO_B0_STATE_DEBUG_LN0_DCD_DFE_TUNING_BITS 1 27270 #define UC_INFO_B0_STATE_DEBUG_LN0_DCD_DFE_TUNING_SHIFT 11 27271 27272 /* uC_info_B0 :: state_debug_ln0 :: OSDFE_P1_TUNING [10:10] */ 27273 #define UC_INFO_B0_STATE_DEBUG_LN0_OSDFE_P1_TUNING_MASK 0x0400 27274 #define UC_INFO_B0_STATE_DEBUG_LN0_OSDFE_P1_TUNING_ALIGN 0 27275 #define UC_INFO_B0_STATE_DEBUG_LN0_OSDFE_P1_TUNING_BITS 1 27276 #define UC_INFO_B0_STATE_DEBUG_LN0_OSDFE_P1_TUNING_SHIFT 10 27277 27278 /* uC_info_B0 :: state_debug_ln0 :: SLICER_OFFSET_TUNING [09:09] */ 27279 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_MASK 0x0200 27280 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_ALIGN 0 27281 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_BITS 1 27282 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_SHIFT 9 27283 27284 /* uC_info_B0 :: state_debug_ln0 :: CL72_REMOTE_TUNING [08:08] */ 27285 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_MASK 0x0100 27286 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_ALIGN 0 27287 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_BITS 1 27288 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_SHIFT 8 27289 27290 /* uC_info_B0 :: state_debug_ln0 :: CL72_TUNING [07:07] */ 27291 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_TUNING_MASK 0x0080 27292 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_TUNING_ALIGN 0 27293 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_TUNING_BITS 1 27294 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_TUNING_SHIFT 7 27295 27296 /* uC_info_B0 :: state_debug_ln0 :: SLICER_TARGET_TUNING [06:06] */ 27297 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_MASK 0x0040 27298 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_ALIGN 0 27299 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_BITS 1 27300 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_SHIFT 6 27301 27302 /* uC_info_B0 :: state_debug_ln0 :: VGA_BIAS_TUNING [05:05] */ 27303 #define UC_INFO_B0_STATE_DEBUG_LN0_VGA_BIAS_TUNING_MASK 0x0020 27304 #define UC_INFO_B0_STATE_DEBUG_LN0_VGA_BIAS_TUNING_ALIGN 0 27305 #define UC_INFO_B0_STATE_DEBUG_LN0_VGA_BIAS_TUNING_BITS 1 27306 #define UC_INFO_B0_STATE_DEBUG_LN0_VGA_BIAS_TUNING_SHIFT 5 27307 27308 /* uC_info_B0 :: state_debug_ln0 :: PF_TUNING [04:04] */ 27309 #define UC_INFO_B0_STATE_DEBUG_LN0_PF_TUNING_MASK 0x0010 27310 #define UC_INFO_B0_STATE_DEBUG_LN0_PF_TUNING_ALIGN 0 27311 #define UC_INFO_B0_STATE_DEBUG_LN0_PF_TUNING_BITS 1 27312 #define UC_INFO_B0_STATE_DEBUG_LN0_PF_TUNING_SHIFT 4 27313 27314 /* uC_info_B0 :: state_debug_ln0 :: CLK90_OFFSET_TUNING [03:03] */ 27315 #define UC_INFO_B0_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_MASK 0x0008 27316 #define UC_INFO_B0_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_ALIGN 0 27317 #define UC_INFO_B0_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_BITS 1 27318 #define UC_INFO_B0_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_SHIFT 3 27319 27320 /* uC_info_B0 :: state_debug_ln0 :: OS_VGA_TUNING [02:02] */ 27321 #define UC_INFO_B0_STATE_DEBUG_LN0_OS_VGA_TUNING_MASK 0x0004 27322 #define UC_INFO_B0_STATE_DEBUG_LN0_OS_VGA_TUNING_ALIGN 0 27323 #define UC_INFO_B0_STATE_DEBUG_LN0_OS_VGA_TUNING_BITS 1 27324 #define UC_INFO_B0_STATE_DEBUG_LN0_OS_VGA_TUNING_SHIFT 2 27325 27326 /* uC_info_B0 :: state_debug_ln0 :: DFE_TAPS_2_5_EN [01:01] */ 27327 #define UC_INFO_B0_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_MASK 0x0002 27328 #define UC_INFO_B0_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_ALIGN 0 27329 #define UC_INFO_B0_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_BITS 1 27330 #define UC_INFO_B0_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_SHIFT 1 27331 27332 /* uC_info_B0 :: state_debug_ln0 :: CDR_LOCK [00:00] */ 27333 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_MASK 0x0001 27334 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_ALIGN 0 27335 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_BITS 1 27336 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_SHIFT 0 27337 27338 27339 /**************************************************************************** 27340 * uC_info_B0 :: state_debug_ln1 27341 */ 27342 /* uC_info_B0 :: state_debug_ln1 :: CDR_LOCK_CORR [15:15] */ 27343 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_CORR_MASK 0x8000 27344 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_CORR_ALIGN 0 27345 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_CORR_BITS 1 27346 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_CORR_SHIFT 15 27347 27348 /* uC_info_B0 :: state_debug_ln1 :: DSC_DONE [14:14] */ 27349 #define UC_INFO_B0_STATE_DEBUG_LN1_DSC_DONE_MASK 0x4000 27350 #define UC_INFO_B0_STATE_DEBUG_LN1_DSC_DONE_ALIGN 0 27351 #define UC_INFO_B0_STATE_DEBUG_LN1_DSC_DONE_BITS 1 27352 #define UC_INFO_B0_STATE_DEBUG_LN1_DSC_DONE_SHIFT 14 27353 27354 /* uC_info_B0 :: state_debug_ln1 :: TUNING_DONE [13:13] */ 27355 #define UC_INFO_B0_STATE_DEBUG_LN1_TUNING_DONE_MASK 0x2000 27356 #define UC_INFO_B0_STATE_DEBUG_LN1_TUNING_DONE_ALIGN 0 27357 #define UC_INFO_B0_STATE_DEBUG_LN1_TUNING_DONE_BITS 1 27358 #define UC_INFO_B0_STATE_DEBUG_LN1_TUNING_DONE_SHIFT 13 27359 27360 /* uC_info_B0 :: state_debug_ln1 :: KR4_DIV16CK_BCST [12:12] */ 27361 #define UC_INFO_B0_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_MASK 0x1000 27362 #define UC_INFO_B0_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_ALIGN 0 27363 #define UC_INFO_B0_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_BITS 1 27364 #define UC_INFO_B0_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_SHIFT 12 27365 27366 /* uC_info_B0 :: state_debug_ln1 :: DCD_DFE_TUNING [11:11] */ 27367 #define UC_INFO_B0_STATE_DEBUG_LN1_DCD_DFE_TUNING_MASK 0x0800 27368 #define UC_INFO_B0_STATE_DEBUG_LN1_DCD_DFE_TUNING_ALIGN 0 27369 #define UC_INFO_B0_STATE_DEBUG_LN1_DCD_DFE_TUNING_BITS 1 27370 #define UC_INFO_B0_STATE_DEBUG_LN1_DCD_DFE_TUNING_SHIFT 11 27371 27372 /* uC_info_B0 :: state_debug_ln1 :: OSDFE_P1_TUNING [10:10] */ 27373 #define UC_INFO_B0_STATE_DEBUG_LN1_OSDFE_P1_TUNING_MASK 0x0400 27374 #define UC_INFO_B0_STATE_DEBUG_LN1_OSDFE_P1_TUNING_ALIGN 0 27375 #define UC_INFO_B0_STATE_DEBUG_LN1_OSDFE_P1_TUNING_BITS 1 27376 #define UC_INFO_B0_STATE_DEBUG_LN1_OSDFE_P1_TUNING_SHIFT 10 27377 27378 /* uC_info_B0 :: state_debug_ln1 :: SLICER_OFFSET_TUNING [09:09] */ 27379 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_MASK 0x0200 27380 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_ALIGN 0 27381 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_BITS 1 27382 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_SHIFT 9 27383 27384 /* uC_info_B0 :: state_debug_ln1 :: CL72_REMOTE_TUNING [08:08] */ 27385 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_MASK 0x0100 27386 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_ALIGN 0 27387 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_BITS 1 27388 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_SHIFT 8 27389 27390 /* uC_info_B0 :: state_debug_ln1 :: CL72_TUNING [07:07] */ 27391 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_TUNING_MASK 0x0080 27392 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_TUNING_ALIGN 0 27393 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_TUNING_BITS 1 27394 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_TUNING_SHIFT 7 27395 27396 /* uC_info_B0 :: state_debug_ln1 :: SLICER_TARGET_TUNING [06:06] */ 27397 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_MASK 0x0040 27398 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_ALIGN 0 27399 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_BITS 1 27400 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_SHIFT 6 27401 27402 /* uC_info_B0 :: state_debug_ln1 :: VGA_BIAS_TUNING [05:05] */ 27403 #define UC_INFO_B0_STATE_DEBUG_LN1_VGA_BIAS_TUNING_MASK 0x0020 27404 #define UC_INFO_B0_STATE_DEBUG_LN1_VGA_BIAS_TUNING_ALIGN 0 27405 #define UC_INFO_B0_STATE_DEBUG_LN1_VGA_BIAS_TUNING_BITS 1 27406 #define UC_INFO_B0_STATE_DEBUG_LN1_VGA_BIAS_TUNING_SHIFT 5 27407 27408 /* uC_info_B0 :: state_debug_ln1 :: PF_TUNING [04:04] */ 27409 #define UC_INFO_B0_STATE_DEBUG_LN1_PF_TUNING_MASK 0x0010 27410 #define UC_INFO_B0_STATE_DEBUG_LN1_PF_TUNING_ALIGN 0 27411 #define UC_INFO_B0_STATE_DEBUG_LN1_PF_TUNING_BITS 1 27412 #define UC_INFO_B0_STATE_DEBUG_LN1_PF_TUNING_SHIFT 4 27413 27414 /* uC_info_B0 :: state_debug_ln1 :: CLK90_OFFSET_TUNING [03:03] */ 27415 #define UC_INFO_B0_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_MASK 0x0008 27416 #define UC_INFO_B0_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_ALIGN 0 27417 #define UC_INFO_B0_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_BITS 1 27418 #define UC_INFO_B0_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_SHIFT 3 27419 27420 /* uC_info_B0 :: state_debug_ln1 :: OS_VGA_TUNING [02:02] */ 27421 #define UC_INFO_B0_STATE_DEBUG_LN1_OS_VGA_TUNING_MASK 0x0004 27422 #define UC_INFO_B0_STATE_DEBUG_LN1_OS_VGA_TUNING_ALIGN 0 27423 #define UC_INFO_B0_STATE_DEBUG_LN1_OS_VGA_TUNING_BITS 1 27424 #define UC_INFO_B0_STATE_DEBUG_LN1_OS_VGA_TUNING_SHIFT 2 27425 27426 /* uC_info_B0 :: state_debug_ln1 :: DFE_TAPS_2_5_EN [01:01] */ 27427 #define UC_INFO_B0_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_MASK 0x0002 27428 #define UC_INFO_B0_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_ALIGN 0 27429 #define UC_INFO_B0_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_BITS 1 27430 #define UC_INFO_B0_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_SHIFT 1 27431 27432 /* uC_info_B0 :: state_debug_ln1 :: CDR_LOCK [00:00] */ 27433 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_MASK 0x0001 27434 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_ALIGN 0 27435 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_BITS 1 27436 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_SHIFT 0 27437 27438 27439 /**************************************************************************** 27440 * uC_info_B0 :: state_debug_ln2 27441 */ 27442 /* uC_info_B0 :: state_debug_ln2 :: CDR_LOCK_CORR [15:15] */ 27443 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_CORR_MASK 0x8000 27444 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_CORR_ALIGN 0 27445 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_CORR_BITS 1 27446 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_CORR_SHIFT 15 27447 27448 /* uC_info_B0 :: state_debug_ln2 :: DSC_DONE [14:14] */ 27449 #define UC_INFO_B0_STATE_DEBUG_LN2_DSC_DONE_MASK 0x4000 27450 #define UC_INFO_B0_STATE_DEBUG_LN2_DSC_DONE_ALIGN 0 27451 #define UC_INFO_B0_STATE_DEBUG_LN2_DSC_DONE_BITS 1 27452 #define UC_INFO_B0_STATE_DEBUG_LN2_DSC_DONE_SHIFT 14 27453 27454 /* uC_info_B0 :: state_debug_ln2 :: TUNING_DONE [13:13] */ 27455 #define UC_INFO_B0_STATE_DEBUG_LN2_TUNING_DONE_MASK 0x2000 27456 #define UC_INFO_B0_STATE_DEBUG_LN2_TUNING_DONE_ALIGN 0 27457 #define UC_INFO_B0_STATE_DEBUG_LN2_TUNING_DONE_BITS 1 27458 #define UC_INFO_B0_STATE_DEBUG_LN2_TUNING_DONE_SHIFT 13 27459 27460 /* uC_info_B0 :: state_debug_ln2 :: KR4_DIV16CK_BCST [12:12] */ 27461 #define UC_INFO_B0_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_MASK 0x1000 27462 #define UC_INFO_B0_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_ALIGN 0 27463 #define UC_INFO_B0_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_BITS 1 27464 #define UC_INFO_B0_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_SHIFT 12 27465 27466 /* uC_info_B0 :: state_debug_ln2 :: DCD_DFE_TUNING [11:11] */ 27467 #define UC_INFO_B0_STATE_DEBUG_LN2_DCD_DFE_TUNING_MASK 0x0800 27468 #define UC_INFO_B0_STATE_DEBUG_LN2_DCD_DFE_TUNING_ALIGN 0 27469 #define UC_INFO_B0_STATE_DEBUG_LN2_DCD_DFE_TUNING_BITS 1 27470 #define UC_INFO_B0_STATE_DEBUG_LN2_DCD_DFE_TUNING_SHIFT 11 27471 27472 /* uC_info_B0 :: state_debug_ln2 :: OSDFE_P1_TUNING [10:10] */ 27473 #define UC_INFO_B0_STATE_DEBUG_LN2_OSDFE_P1_TUNING_MASK 0x0400 27474 #define UC_INFO_B0_STATE_DEBUG_LN2_OSDFE_P1_TUNING_ALIGN 0 27475 #define UC_INFO_B0_STATE_DEBUG_LN2_OSDFE_P1_TUNING_BITS 1 27476 #define UC_INFO_B0_STATE_DEBUG_LN2_OSDFE_P1_TUNING_SHIFT 10 27477 27478 /* uC_info_B0 :: state_debug_ln2 :: SLICER_OFFSET_TUNING [09:09] */ 27479 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_MASK 0x0200 27480 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_ALIGN 0 27481 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_BITS 1 27482 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_SHIFT 9 27483 27484 /* uC_info_B0 :: state_debug_ln2 :: CL72_REMOTE_TUNING [08:08] */ 27485 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_MASK 0x0100 27486 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_ALIGN 0 27487 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_BITS 1 27488 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_SHIFT 8 27489 27490 /* uC_info_B0 :: state_debug_ln2 :: CL72_TUNING [07:07] */ 27491 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_TUNING_MASK 0x0080 27492 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_TUNING_ALIGN 0 27493 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_TUNING_BITS 1 27494 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_TUNING_SHIFT 7 27495 27496 /* uC_info_B0 :: state_debug_ln2 :: SLICER_TARGET_TUNING [06:06] */ 27497 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_MASK 0x0040 27498 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_ALIGN 0 27499 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_BITS 1 27500 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_SHIFT 6 27501 27502 /* uC_info_B0 :: state_debug_ln2 :: VGA_BIAS_TUNING [05:05] */ 27503 #define UC_INFO_B0_STATE_DEBUG_LN2_VGA_BIAS_TUNING_MASK 0x0020 27504 #define UC_INFO_B0_STATE_DEBUG_LN2_VGA_BIAS_TUNING_ALIGN 0 27505 #define UC_INFO_B0_STATE_DEBUG_LN2_VGA_BIAS_TUNING_BITS 1 27506 #define UC_INFO_B0_STATE_DEBUG_LN2_VGA_BIAS_TUNING_SHIFT 5 27507 27508 /* uC_info_B0 :: state_debug_ln2 :: PF_TUNING [04:04] */ 27509 #define UC_INFO_B0_STATE_DEBUG_LN2_PF_TUNING_MASK 0x0010 27510 #define UC_INFO_B0_STATE_DEBUG_LN2_PF_TUNING_ALIGN 0 27511 #define UC_INFO_B0_STATE_DEBUG_LN2_PF_TUNING_BITS 1 27512 #define UC_INFO_B0_STATE_DEBUG_LN2_PF_TUNING_SHIFT 4 27513 27514 /* uC_info_B0 :: state_debug_ln2 :: CLK90_OFFSET_TUNING [03:03] */ 27515 #define UC_INFO_B0_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_MASK 0x0008 27516 #define UC_INFO_B0_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_ALIGN 0 27517 #define UC_INFO_B0_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_BITS 1 27518 #define UC_INFO_B0_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_SHIFT 3 27519 27520 /* uC_info_B0 :: state_debug_ln2 :: OS_VGA_TUNING [02:02] */ 27521 #define UC_INFO_B0_STATE_DEBUG_LN2_OS_VGA_TUNING_MASK 0x0004 27522 #define UC_INFO_B0_STATE_DEBUG_LN2_OS_VGA_TUNING_ALIGN 0 27523 #define UC_INFO_B0_STATE_DEBUG_LN2_OS_VGA_TUNING_BITS 1 27524 #define UC_INFO_B0_STATE_DEBUG_LN2_OS_VGA_TUNING_SHIFT 2 27525 27526 /* uC_info_B0 :: state_debug_ln2 :: DFE_TAPS_2_5_EN [01:01] */ 27527 #define UC_INFO_B0_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_MASK 0x0002 27528 #define UC_INFO_B0_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_ALIGN 0 27529 #define UC_INFO_B0_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_BITS 1 27530 #define UC_INFO_B0_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_SHIFT 1 27531 27532 /* uC_info_B0 :: state_debug_ln2 :: CDR_LOCK [00:00] */ 27533 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_MASK 0x0001 27534 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_ALIGN 0 27535 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_BITS 1 27536 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_SHIFT 0 27537 27538 27539 /**************************************************************************** 27540 * uC_info_B0 :: state_debug_ln3 27541 */ 27542 /* uC_info_B0 :: state_debug_ln3 :: CDR_LOCK_CORR [15:15] */ 27543 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_CORR_MASK 0x8000 27544 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_CORR_ALIGN 0 27545 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_CORR_BITS 1 27546 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_CORR_SHIFT 15 27547 27548 /* uC_info_B0 :: state_debug_ln3 :: DSC_DONE [14:14] */ 27549 #define UC_INFO_B0_STATE_DEBUG_LN3_DSC_DONE_MASK 0x4000 27550 #define UC_INFO_B0_STATE_DEBUG_LN3_DSC_DONE_ALIGN 0 27551 #define UC_INFO_B0_STATE_DEBUG_LN3_DSC_DONE_BITS 1 27552 #define UC_INFO_B0_STATE_DEBUG_LN3_DSC_DONE_SHIFT 14 27553 27554 /* uC_info_B0 :: state_debug_ln3 :: TUNING_DONE [13:13] */ 27555 #define UC_INFO_B0_STATE_DEBUG_LN3_TUNING_DONE_MASK 0x2000 27556 #define UC_INFO_B0_STATE_DEBUG_LN3_TUNING_DONE_ALIGN 0 27557 #define UC_INFO_B0_STATE_DEBUG_LN3_TUNING_DONE_BITS 1 27558 #define UC_INFO_B0_STATE_DEBUG_LN3_TUNING_DONE_SHIFT 13 27559 27560 /* uC_info_B0 :: state_debug_ln3 :: KR4_DIV16CK_BCST [12:12] */ 27561 #define UC_INFO_B0_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_MASK 0x1000 27562 #define UC_INFO_B0_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_ALIGN 0 27563 #define UC_INFO_B0_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_BITS 1 27564 #define UC_INFO_B0_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_SHIFT 12 27565 27566 /* uC_info_B0 :: state_debug_ln3 :: DCD_DFE_TUNING [11:11] */ 27567 #define UC_INFO_B0_STATE_DEBUG_LN3_DCD_DFE_TUNING_MASK 0x0800 27568 #define UC_INFO_B0_STATE_DEBUG_LN3_DCD_DFE_TUNING_ALIGN 0 27569 #define UC_INFO_B0_STATE_DEBUG_LN3_DCD_DFE_TUNING_BITS 1 27570 #define UC_INFO_B0_STATE_DEBUG_LN3_DCD_DFE_TUNING_SHIFT 11 27571 27572 /* uC_info_B0 :: state_debug_ln3 :: OSDFE_P1_TUNING [10:10] */ 27573 #define UC_INFO_B0_STATE_DEBUG_LN3_OSDFE_P1_TUNING_MASK 0x0400 27574 #define UC_INFO_B0_STATE_DEBUG_LN3_OSDFE_P1_TUNING_ALIGN 0 27575 #define UC_INFO_B0_STATE_DEBUG_LN3_OSDFE_P1_TUNING_BITS 1 27576 #define UC_INFO_B0_STATE_DEBUG_LN3_OSDFE_P1_TUNING_SHIFT 10 27577 27578 /* uC_info_B0 :: state_debug_ln3 :: SLICER_OFFSET_TUNING [09:09] */ 27579 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_MASK 0x0200 27580 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_ALIGN 0 27581 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_BITS 1 27582 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_SHIFT 9 27583 27584 /* uC_info_B0 :: state_debug_ln3 :: CL72_REMOTE_TUNING [08:08] */ 27585 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_MASK 0x0100 27586 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_ALIGN 0 27587 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_BITS 1 27588 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_SHIFT 8 27589 27590 /* uC_info_B0 :: state_debug_ln3 :: CL72_TUNING [07:07] */ 27591 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_TUNING_MASK 0x0080 27592 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_TUNING_ALIGN 0 27593 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_TUNING_BITS 1 27594 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_TUNING_SHIFT 7 27595 27596 /* uC_info_B0 :: state_debug_ln3 :: SLICER_TARGET_TUNING [06:06] */ 27597 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_MASK 0x0040 27598 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_ALIGN 0 27599 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_BITS 1 27600 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_SHIFT 6 27601 27602 /* uC_info_B0 :: state_debug_ln3 :: VGA_BIAS_TUNING [05:05] */ 27603 #define UC_INFO_B0_STATE_DEBUG_LN3_VGA_BIAS_TUNING_MASK 0x0020 27604 #define UC_INFO_B0_STATE_DEBUG_LN3_VGA_BIAS_TUNING_ALIGN 0 27605 #define UC_INFO_B0_STATE_DEBUG_LN3_VGA_BIAS_TUNING_BITS 1 27606 #define UC_INFO_B0_STATE_DEBUG_LN3_VGA_BIAS_TUNING_SHIFT 5 27607 27608 /* uC_info_B0 :: state_debug_ln3 :: PF_TUNING [04:04] */ 27609 #define UC_INFO_B0_STATE_DEBUG_LN3_PF_TUNING_MASK 0x0010 27610 #define UC_INFO_B0_STATE_DEBUG_LN3_PF_TUNING_ALIGN 0 27611 #define UC_INFO_B0_STATE_DEBUG_LN3_PF_TUNING_BITS 1 27612 #define UC_INFO_B0_STATE_DEBUG_LN3_PF_TUNING_SHIFT 4 27613 27614 /* uC_info_B0 :: state_debug_ln3 :: CLK90_OFFSET_TUNING [03:03] */ 27615 #define UC_INFO_B0_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_MASK 0x0008 27616 #define UC_INFO_B0_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_ALIGN 0 27617 #define UC_INFO_B0_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_BITS 1 27618 #define UC_INFO_B0_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_SHIFT 3 27619 27620 /* uC_info_B0 :: state_debug_ln3 :: OS_VGA_TUNING [02:02] */ 27621 #define UC_INFO_B0_STATE_DEBUG_LN3_OS_VGA_TUNING_MASK 0x0004 27622 #define UC_INFO_B0_STATE_DEBUG_LN3_OS_VGA_TUNING_ALIGN 0 27623 #define UC_INFO_B0_STATE_DEBUG_LN3_OS_VGA_TUNING_BITS 1 27624 #define UC_INFO_B0_STATE_DEBUG_LN3_OS_VGA_TUNING_SHIFT 2 27625 27626 /* uC_info_B0 :: state_debug_ln3 :: DFE_TAPS_2_5_EN [01:01] */ 27627 #define UC_INFO_B0_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_MASK 0x0002 27628 #define UC_INFO_B0_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_ALIGN 0 27629 #define UC_INFO_B0_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_BITS 1 27630 #define UC_INFO_B0_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_SHIFT 1 27631 27632 /* uC_info_B0 :: state_debug_ln3 :: CDR_LOCK [00:00] */ 27633 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_MASK 0x0001 27634 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_ALIGN 0 27635 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_BITS 1 27636 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_SHIFT 0 27637 27638 27639 /**************************************************************************** 27640 * uC_info_B0 :: speed_debug_ln0 27641 */ 27642 /* uC_info_B0 :: speed_debug_ln0 :: LOS_counter [15:12] */ 27643 #define UC_INFO_B0_SPEED_DEBUG_LN0_LOS_COUNTER_MASK 0xf000 27644 #define UC_INFO_B0_SPEED_DEBUG_LN0_LOS_COUNTER_ALIGN 0 27645 #define UC_INFO_B0_SPEED_DEBUG_LN0_LOS_COUNTER_BITS 4 27646 #define UC_INFO_B0_SPEED_DEBUG_LN0_LOS_COUNTER_SHIFT 12 27647 27648 /* uC_info_B0 :: speed_debug_ln0 :: need_br_dfe [11:11] */ 27649 #define UC_INFO_B0_SPEED_DEBUG_LN0_NEED_BR_DFE_MASK 0x0800 27650 #define UC_INFO_B0_SPEED_DEBUG_LN0_NEED_BR_DFE_ALIGN 0 27651 #define UC_INFO_B0_SPEED_DEBUG_LN0_NEED_BR_DFE_BITS 1 27652 #define UC_INFO_B0_SPEED_DEBUG_LN0_NEED_BR_DFE_SHIFT 11 27653 27654 /* uC_info_B0 :: speed_debug_ln0 :: br_dfe_enabled [10:10] */ 27655 #define UC_INFO_B0_SPEED_DEBUG_LN0_BR_DFE_ENABLED_MASK 0x0400 27656 #define UC_INFO_B0_SPEED_DEBUG_LN0_BR_DFE_ENABLED_ALIGN 0 27657 #define UC_INFO_B0_SPEED_DEBUG_LN0_BR_DFE_ENABLED_BITS 1 27658 #define UC_INFO_B0_SPEED_DEBUG_LN0_BR_DFE_ENABLED_SHIFT 10 27659 27660 /* uC_info_B0 :: speed_debug_ln0 :: os_dfe_enabled [09:09] */ 27661 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_DFE_ENABLED_MASK 0x0200 27662 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_DFE_ENABLED_ALIGN 0 27663 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_DFE_ENABLED_BITS 1 27664 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_DFE_ENABLED_SHIFT 9 27665 27666 /* uC_info_B0 :: speed_debug_ln0 :: os_enabled [08:08] */ 27667 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_ENABLED_MASK 0x0100 27668 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_ENABLED_ALIGN 0 27669 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_ENABLED_BITS 1 27670 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_ENABLED_SHIFT 8 27671 27672 /* uC_info_B0 :: speed_debug_ln0 :: actual_speed [07:00] */ 27673 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_MASK 0x00ff 27674 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_ALIGN 0 27675 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_BITS 8 27676 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_SHIFT 0 27677 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10M 0 27678 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_100M 1 27679 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_1G 2 27680 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_2p5G 3 27681 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_5G_X4 4 27682 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_6G_X4 5 27683 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_HiG 6 27684 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_CX4 7 27685 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_12G_HiG 8 27686 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_12p5G_X4 9 27687 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_13G_X4 10 27688 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_15G_X4 11 27689 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_16G_X4 12 27690 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_1G_KX 13 27691 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_KX4 14 27692 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_KR 15 27693 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_5G 16 27694 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_6p4G 17 27695 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_20G_X4 18 27696 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_21G_X4 19 27697 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_25G_X4 20 27698 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_HiG_DXGXS 21 27699 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_DXGXS 22 27700 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10p5G_HiG_DXGXS 23 27701 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10p5G_DXGXS 24 27702 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_12p773G_HiG_DXGXS 25 27703 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_12p773G_DXGXS 26 27704 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_XFI 27 27705 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_40G 28 27706 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_20G_HiG_DXGXS 29 27707 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_20G_DXGXS 30 27708 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_SFI 31 27709 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_31p5G 32 27710 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_32p7G 33 27711 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_20G_SCR 34 27712 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_HiG_DXGXS_SCR 35 27713 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_DXGXS_SCR 36 27714 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_12G_R2 37 27715 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_X2 38 27716 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_40G_KR4 39 27717 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_40G_CR4 40 27718 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_100G_CR10 41 27719 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_15p75G_DXGXS 44 27720 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_20G_KR2 57 27721 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_20G_CR2 58 27722 27723 27724 /**************************************************************************** 27725 * uC_info_B0 :: speed_debug_ln1 27726 */ 27727 /* uC_info_B0 :: speed_debug_ln1 :: LOS_counter [15:12] */ 27728 #define UC_INFO_B0_SPEED_DEBUG_LN1_LOS_COUNTER_MASK 0xf000 27729 #define UC_INFO_B0_SPEED_DEBUG_LN1_LOS_COUNTER_ALIGN 0 27730 #define UC_INFO_B0_SPEED_DEBUG_LN1_LOS_COUNTER_BITS 4 27731 #define UC_INFO_B0_SPEED_DEBUG_LN1_LOS_COUNTER_SHIFT 12 27732 27733 /* uC_info_B0 :: speed_debug_ln1 :: need_br_dfe [11:11] */ 27734 #define UC_INFO_B0_SPEED_DEBUG_LN1_NEED_BR_DFE_MASK 0x0800 27735 #define UC_INFO_B0_SPEED_DEBUG_LN1_NEED_BR_DFE_ALIGN 0 27736 #define UC_INFO_B0_SPEED_DEBUG_LN1_NEED_BR_DFE_BITS 1 27737 #define UC_INFO_B0_SPEED_DEBUG_LN1_NEED_BR_DFE_SHIFT 11 27738 27739 /* uC_info_B0 :: speed_debug_ln1 :: br_dfe_enabled [10:10] */ 27740 #define UC_INFO_B0_SPEED_DEBUG_LN1_BR_DFE_ENABLED_MASK 0x0400 27741 #define UC_INFO_B0_SPEED_DEBUG_LN1_BR_DFE_ENABLED_ALIGN 0 27742 #define UC_INFO_B0_SPEED_DEBUG_LN1_BR_DFE_ENABLED_BITS 1 27743 #define UC_INFO_B0_SPEED_DEBUG_LN1_BR_DFE_ENABLED_SHIFT 10 27744 27745 /* uC_info_B0 :: speed_debug_ln1 :: os_dfe_enabled [09:09] */ 27746 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_DFE_ENABLED_MASK 0x0200 27747 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_DFE_ENABLED_ALIGN 0 27748 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_DFE_ENABLED_BITS 1 27749 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_DFE_ENABLED_SHIFT 9 27750 27751 /* uC_info_B0 :: speed_debug_ln1 :: os_enabled [08:08] */ 27752 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_ENABLED_MASK 0x0100 27753 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_ENABLED_ALIGN 0 27754 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_ENABLED_BITS 1 27755 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_ENABLED_SHIFT 8 27756 27757 /* uC_info_B0 :: speed_debug_ln1 :: actual_speed [07:00] */ 27758 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_MASK 0x00ff 27759 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_ALIGN 0 27760 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_BITS 8 27761 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_SHIFT 0 27762 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10M 0 27763 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_100M 1 27764 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_1G 2 27765 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_2p5G 3 27766 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_5G_X4 4 27767 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_6G_X4 5 27768 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_HiG 6 27769 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_CX4 7 27770 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_12G_HiG 8 27771 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_12p5G_X4 9 27772 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_13G_X4 10 27773 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_15G_X4 11 27774 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_16G_X4 12 27775 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_1G_KX 13 27776 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_KX4 14 27777 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_KR 15 27778 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_5G 16 27779 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_6p4G 17 27780 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_20G_X4 18 27781 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_21G_X4 19 27782 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_25G_X4 20 27783 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_HiG_DXGXS 21 27784 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_DXGXS 22 27785 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10p5G_HiG_DXGXS 23 27786 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10p5G_DXGXS 24 27787 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_12p773G_HiG_DXGXS 25 27788 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_12p773G_DXGXS 26 27789 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_XFI 27 27790 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_40G 28 27791 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_20G_HiG_DXGXS 29 27792 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_20G_DXGXS 30 27793 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_SFI 31 27794 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_31p5G 32 27795 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_32p7G 33 27796 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_20G_SCR 34 27797 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_HiG_DXGXS_SCR 35 27798 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_DXGXS_SCR 36 27799 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_12G_R2 37 27800 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_X2 38 27801 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_40G_KR4 39 27802 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_40G_CR4 40 27803 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_100G_CR10 41 27804 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_15p75G_DXGXS 44 27805 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_20G_KR2 57 27806 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_20G_CR2 58 27807 27808 27809 /**************************************************************************** 27810 * uC_info_B0 :: speed_debug_ln2 27811 */ 27812 /* uC_info_B0 :: speed_debug_ln2 :: LOS_counter [15:12] */ 27813 #define UC_INFO_B0_SPEED_DEBUG_LN2_LOS_COUNTER_MASK 0xf000 27814 #define UC_INFO_B0_SPEED_DEBUG_LN2_LOS_COUNTER_ALIGN 0 27815 #define UC_INFO_B0_SPEED_DEBUG_LN2_LOS_COUNTER_BITS 4 27816 #define UC_INFO_B0_SPEED_DEBUG_LN2_LOS_COUNTER_SHIFT 12 27817 27818 /* uC_info_B0 :: speed_debug_ln2 :: need_br_dfe [11:11] */ 27819 #define UC_INFO_B0_SPEED_DEBUG_LN2_NEED_BR_DFE_MASK 0x0800 27820 #define UC_INFO_B0_SPEED_DEBUG_LN2_NEED_BR_DFE_ALIGN 0 27821 #define UC_INFO_B0_SPEED_DEBUG_LN2_NEED_BR_DFE_BITS 1 27822 #define UC_INFO_B0_SPEED_DEBUG_LN2_NEED_BR_DFE_SHIFT 11 27823 27824 /* uC_info_B0 :: speed_debug_ln2 :: br_dfe_enabled [10:10] */ 27825 #define UC_INFO_B0_SPEED_DEBUG_LN2_BR_DFE_ENABLED_MASK 0x0400 27826 #define UC_INFO_B0_SPEED_DEBUG_LN2_BR_DFE_ENABLED_ALIGN 0 27827 #define UC_INFO_B0_SPEED_DEBUG_LN2_BR_DFE_ENABLED_BITS 1 27828 #define UC_INFO_B0_SPEED_DEBUG_LN2_BR_DFE_ENABLED_SHIFT 10 27829 27830 /* uC_info_B0 :: speed_debug_ln2 :: os_dfe_enabled [09:09] */ 27831 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_DFE_ENABLED_MASK 0x0200 27832 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_DFE_ENABLED_ALIGN 0 27833 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_DFE_ENABLED_BITS 1 27834 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_DFE_ENABLED_SHIFT 9 27835 27836 /* uC_info_B0 :: speed_debug_ln2 :: os_enabled [08:08] */ 27837 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_ENABLED_MASK 0x0100 27838 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_ENABLED_ALIGN 0 27839 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_ENABLED_BITS 1 27840 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_ENABLED_SHIFT 8 27841 27842 /* uC_info_B0 :: speed_debug_ln2 :: actual_speed [07:00] */ 27843 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_MASK 0x00ff 27844 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_ALIGN 0 27845 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_BITS 8 27846 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_SHIFT 0 27847 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10M 0 27848 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_100M 1 27849 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_1G 2 27850 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_2p5G 3 27851 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_5G_X4 4 27852 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_6G_X4 5 27853 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_HiG 6 27854 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_CX4 7 27855 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_12G_HiG 8 27856 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_12p5G_X4 9 27857 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_13G_X4 10 27858 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_15G_X4 11 27859 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_16G_X4 12 27860 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_1G_KX 13 27861 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_KX4 14 27862 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_KR 15 27863 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_5G 16 27864 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_6p4G 17 27865 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_20G_X4 18 27866 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_21G_X4 19 27867 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_25G_X4 20 27868 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_HiG_DXGXS 21 27869 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_DXGXS 22 27870 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10p5G_HiG_DXGXS 23 27871 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10p5G_DXGXS 24 27872 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_12p773G_HiG_DXGXS 25 27873 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_12p773G_DXGXS 26 27874 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_XFI 27 27875 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_40G 28 27876 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_20G_HiG_DXGXS 29 27877 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_20G_DXGXS 30 27878 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_SFI 31 27879 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_31p5G 32 27880 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_32p7G 33 27881 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_20G_SCR 34 27882 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_HiG_DXGXS_SCR 35 27883 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_DXGXS_SCR 36 27884 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_12G_R2 37 27885 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_X2 38 27886 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_40G_KR4 39 27887 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_40G_CR4 40 27888 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_100G_CR10 41 27889 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_15p75G_DXGXS 44 27890 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_20G_KR2 57 27891 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_20G_CR2 58 27892 27893 27894 /**************************************************************************** 27895 * uC_info_B0 :: speed_debug_ln3 27896 */ 27897 /* uC_info_B0 :: speed_debug_ln3 :: LOS_counter [15:12] */ 27898 #define UC_INFO_B0_SPEED_DEBUG_LN3_LOS_COUNTER_MASK 0xf000 27899 #define UC_INFO_B0_SPEED_DEBUG_LN3_LOS_COUNTER_ALIGN 0 27900 #define UC_INFO_B0_SPEED_DEBUG_LN3_LOS_COUNTER_BITS 4 27901 #define UC_INFO_B0_SPEED_DEBUG_LN3_LOS_COUNTER_SHIFT 12 27902 27903 /* uC_info_B0 :: speed_debug_ln3 :: need_br_dfe [11:11] */ 27904 #define UC_INFO_B0_SPEED_DEBUG_LN3_NEED_BR_DFE_MASK 0x0800 27905 #define UC_INFO_B0_SPEED_DEBUG_LN3_NEED_BR_DFE_ALIGN 0 27906 #define UC_INFO_B0_SPEED_DEBUG_LN3_NEED_BR_DFE_BITS 1 27907 #define UC_INFO_B0_SPEED_DEBUG_LN3_NEED_BR_DFE_SHIFT 11 27908 27909 /* uC_info_B0 :: speed_debug_ln3 :: br_dfe_enabled [10:10] */ 27910 #define UC_INFO_B0_SPEED_DEBUG_LN3_BR_DFE_ENABLED_MASK 0x0400 27911 #define UC_INFO_B0_SPEED_DEBUG_LN3_BR_DFE_ENABLED_ALIGN 0 27912 #define UC_INFO_B0_SPEED_DEBUG_LN3_BR_DFE_ENABLED_BITS 1 27913 #define UC_INFO_B0_SPEED_DEBUG_LN3_BR_DFE_ENABLED_SHIFT 10 27914 27915 /* uC_info_B0 :: speed_debug_ln3 :: os_dfe_enabled [09:09] */ 27916 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_DFE_ENABLED_MASK 0x0200 27917 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_DFE_ENABLED_ALIGN 0 27918 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_DFE_ENABLED_BITS 1 27919 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_DFE_ENABLED_SHIFT 9 27920 27921 /* uC_info_B0 :: speed_debug_ln3 :: os_enabled [08:08] */ 27922 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_ENABLED_MASK 0x0100 27923 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_ENABLED_ALIGN 0 27924 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_ENABLED_BITS 1 27925 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_ENABLED_SHIFT 8 27926 27927 /* uC_info_B0 :: speed_debug_ln3 :: actual_speed [07:00] */ 27928 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_MASK 0x00ff 27929 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_ALIGN 0 27930 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_BITS 8 27931 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_SHIFT 0 27932 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10M 0 27933 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_100M 1 27934 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_1G 2 27935 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_2p5G 3 27936 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_5G_X4 4 27937 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_6G_X4 5 27938 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_HiG 6 27939 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_CX4 7 27940 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_12G_HiG 8 27941 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_12p5G_X4 9 27942 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_13G_X4 10 27943 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_15G_X4 11 27944 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_16G_X4 12 27945 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_1G_KX 13 27946 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_KX4 14 27947 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_KR 15 27948 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_5G 16 27949 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_6p4G 17 27950 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_20G_X4 18 27951 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_21G_X4 19 27952 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_25G_X4 20 27953 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_HiG_DXGXS 21 27954 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_DXGXS 22 27955 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10p5G_HiG_DXGXS 23 27956 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10p5G_DXGXS 24 27957 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_12p773G_HiG_DXGXS 25 27958 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_12p773G_DXGXS 26 27959 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_XFI 27 27960 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_40G 28 27961 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_20G_HiG_DXGXS 29 27962 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_20G_DXGXS 30 27963 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_SFI 31 27964 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_31p5G 32 27965 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_32p7G 33 27966 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_20G_SCR 34 27967 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_HiG_DXGXS_SCR 35 27968 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_DXGXS_SCR 36 27969 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_12G_R2 37 27970 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_X2 38 27971 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_40G_KR4 39 27972 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_40G_CR4 40 27973 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_100G_CR10 41 27974 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_15p75G_DXGXS 44 27975 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_20G_KR2 57 27976 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_20G_CR2 58 27977 27978 27979 /**************************************************************************** 27980 * uC_info_B0 :: cl72_status_ln0 27981 */ 27982 /* uC_info_B0 :: cl72_status_ln0 :: temp_idx [15:12] */ 27983 #define UC_INFO_B0_CL72_STATUS_LN0_TEMP_IDX_MASK 0xf000 27984 #define UC_INFO_B0_CL72_STATUS_LN0_TEMP_IDX_ALIGN 0 27985 #define UC_INFO_B0_CL72_STATUS_LN0_TEMP_IDX_BITS 4 27986 #define UC_INFO_B0_CL72_STATUS_LN0_TEMP_IDX_SHIFT 12 27987 27988 /* uC_info_B0 :: cl72_status_ln0 :: dfe_tap1 [11:06] */ 27989 #define UC_INFO_B0_CL72_STATUS_LN0_DFE_TAP1_MASK 0x0fc0 27990 #define UC_INFO_B0_CL72_STATUS_LN0_DFE_TAP1_ALIGN 0 27991 #define UC_INFO_B0_CL72_STATUS_LN0_DFE_TAP1_BITS 6 27992 #define UC_INFO_B0_CL72_STATUS_LN0_DFE_TAP1_SHIFT 6 27993 27994 /* uC_info_B0 :: cl72_status_ln0 :: vga [05:00] */ 27995 #define UC_INFO_B0_CL72_STATUS_LN0_VGA_MASK 0x003f 27996 #define UC_INFO_B0_CL72_STATUS_LN0_VGA_ALIGN 0 27997 #define UC_INFO_B0_CL72_STATUS_LN0_VGA_BITS 6 27998 #define UC_INFO_B0_CL72_STATUS_LN0_VGA_SHIFT 0 27999 28000 28001 /**************************************************************************** 28002 * uC_info_B0 :: cl72_status_ln1 28003 */ 28004 /* uC_info_B0 :: cl72_status_ln1 :: temp_idx [15:12] */ 28005 #define UC_INFO_B0_CL72_STATUS_LN1_TEMP_IDX_MASK 0xf000 28006 #define UC_INFO_B0_CL72_STATUS_LN1_TEMP_IDX_ALIGN 0 28007 #define UC_INFO_B0_CL72_STATUS_LN1_TEMP_IDX_BITS 4 28008 #define UC_INFO_B0_CL72_STATUS_LN1_TEMP_IDX_SHIFT 12 28009 28010 /* uC_info_B0 :: cl72_status_ln1 :: dfe_tap1 [11:06] */ 28011 #define UC_INFO_B0_CL72_STATUS_LN1_DFE_TAP1_MASK 0x0fc0 28012 #define UC_INFO_B0_CL72_STATUS_LN1_DFE_TAP1_ALIGN 0 28013 #define UC_INFO_B0_CL72_STATUS_LN1_DFE_TAP1_BITS 6 28014 #define UC_INFO_B0_CL72_STATUS_LN1_DFE_TAP1_SHIFT 6 28015 28016 /* uC_info_B0 :: cl72_status_ln1 :: vga [05:00] */ 28017 #define UC_INFO_B0_CL72_STATUS_LN1_VGA_MASK 0x003f 28018 #define UC_INFO_B0_CL72_STATUS_LN1_VGA_ALIGN 0 28019 #define UC_INFO_B0_CL72_STATUS_LN1_VGA_BITS 6 28020 #define UC_INFO_B0_CL72_STATUS_LN1_VGA_SHIFT 0 28021 28022 28023 /**************************************************************************** 28024 * uC_info_B0 :: cl72_status_ln2 28025 */ 28026 /* uC_info_B0 :: cl72_status_ln2 :: temp_idx [15:12] */ 28027 #define UC_INFO_B0_CL72_STATUS_LN2_TEMP_IDX_MASK 0xf000 28028 #define UC_INFO_B0_CL72_STATUS_LN2_TEMP_IDX_ALIGN 0 28029 #define UC_INFO_B0_CL72_STATUS_LN2_TEMP_IDX_BITS 4 28030 #define UC_INFO_B0_CL72_STATUS_LN2_TEMP_IDX_SHIFT 12 28031 28032 /* uC_info_B0 :: cl72_status_ln2 :: dfe_tap1 [11:06] */ 28033 #define UC_INFO_B0_CL72_STATUS_LN2_DFE_TAP1_MASK 0x0fc0 28034 #define UC_INFO_B0_CL72_STATUS_LN2_DFE_TAP1_ALIGN 0 28035 #define UC_INFO_B0_CL72_STATUS_LN2_DFE_TAP1_BITS 6 28036 #define UC_INFO_B0_CL72_STATUS_LN2_DFE_TAP1_SHIFT 6 28037 28038 /* uC_info_B0 :: cl72_status_ln2 :: vga [05:00] */ 28039 #define UC_INFO_B0_CL72_STATUS_LN2_VGA_MASK 0x003f 28040 #define UC_INFO_B0_CL72_STATUS_LN2_VGA_ALIGN 0 28041 #define UC_INFO_B0_CL72_STATUS_LN2_VGA_BITS 6 28042 #define UC_INFO_B0_CL72_STATUS_LN2_VGA_SHIFT 0 28043 28044 28045 /**************************************************************************** 28046 * uC_info_B0 :: cl72_status_ln3 28047 */ 28048 /* uC_info_B0 :: cl72_status_ln3 :: temp_idx [15:12] */ 28049 #define UC_INFO_B0_CL72_STATUS_LN3_TEMP_IDX_MASK 0xf000 28050 #define UC_INFO_B0_CL72_STATUS_LN3_TEMP_IDX_ALIGN 0 28051 #define UC_INFO_B0_CL72_STATUS_LN3_TEMP_IDX_BITS 4 28052 #define UC_INFO_B0_CL72_STATUS_LN3_TEMP_IDX_SHIFT 12 28053 28054 /* uC_info_B0 :: cl72_status_ln3 :: dfe_tap1 [11:06] */ 28055 #define UC_INFO_B0_CL72_STATUS_LN3_DFE_TAP1_MASK 0x0fc0 28056 #define UC_INFO_B0_CL72_STATUS_LN3_DFE_TAP1_ALIGN 0 28057 #define UC_INFO_B0_CL72_STATUS_LN3_DFE_TAP1_BITS 6 28058 #define UC_INFO_B0_CL72_STATUS_LN3_DFE_TAP1_SHIFT 6 28059 28060 /* uC_info_B0 :: cl72_status_ln3 :: vga [05:00] */ 28061 #define UC_INFO_B0_CL72_STATUS_LN3_VGA_MASK 0x003f 28062 #define UC_INFO_B0_CL72_STATUS_LN3_VGA_ALIGN 0 28063 #define UC_INFO_B0_CL72_STATUS_LN3_VGA_BITS 6 28064 #define UC_INFO_B0_CL72_STATUS_LN3_VGA_SHIFT 0 28065 28066 28067 /**************************************************************************** 28068 * uC_info_B0 :: debug_reg0 28069 */ 28070 /* uC_info_B0 :: debug_reg0 :: reserved_for_eco0 [15:00] */ 28071 #define UC_INFO_B0_DEBUG_REG0_RESERVED_FOR_ECO0_MASK 0xffff 28072 #define UC_INFO_B0_DEBUG_REG0_RESERVED_FOR_ECO0_ALIGN 0 28073 #define UC_INFO_B0_DEBUG_REG0_RESERVED_FOR_ECO0_BITS 16 28074 #define UC_INFO_B0_DEBUG_REG0_RESERVED_FOR_ECO0_SHIFT 0 28075 28076 28077 /**************************************************************************** 28078 * uC_info_B0 :: debug_reg1 28079 */ 28080 /* uC_info_B0 :: debug_reg1 :: reserved_for_eco0 [15:00] */ 28081 #define UC_INFO_B0_DEBUG_REG1_RESERVED_FOR_ECO0_MASK 0xffff 28082 #define UC_INFO_B0_DEBUG_REG1_RESERVED_FOR_ECO0_ALIGN 0 28083 #define UC_INFO_B0_DEBUG_REG1_RESERVED_FOR_ECO0_BITS 16 28084 #define UC_INFO_B0_DEBUG_REG1_RESERVED_FOR_ECO0_SHIFT 0 28085 28086 28087 /**************************************************************************** 28088 * uC_info_B0 :: dead_trap 28089 */ 28090 /* uC_info_B0 :: dead_trap :: dead_code_trap [15:15] */ 28091 #define UC_INFO_B0_DEAD_TRAP_DEAD_CODE_TRAP_MASK 0x8000 28092 #define UC_INFO_B0_DEAD_TRAP_DEAD_CODE_TRAP_ALIGN 0 28093 #define UC_INFO_B0_DEAD_TRAP_DEAD_CODE_TRAP_BITS 1 28094 #define UC_INFO_B0_DEAD_TRAP_DEAD_CODE_TRAP_SHIFT 15 28095 28096 /* uC_info_B0 :: dead_trap :: reserved_for_eco0 [14:08] */ 28097 #define UC_INFO_B0_DEAD_TRAP_RESERVED_FOR_ECO0_MASK 0x7f00 28098 #define UC_INFO_B0_DEAD_TRAP_RESERVED_FOR_ECO0_ALIGN 0 28099 #define UC_INFO_B0_DEAD_TRAP_RESERVED_FOR_ECO0_BITS 7 28100 #define UC_INFO_B0_DEAD_TRAP_RESERVED_FOR_ECO0_SHIFT 8 28101 28102 /* uC_info_B0 :: dead_trap :: micro_reset_counter [07:00] */ 28103 #define UC_INFO_B0_DEAD_TRAP_MICRO_RESET_COUNTER_MASK 0x00ff 28104 #define UC_INFO_B0_DEAD_TRAP_MICRO_RESET_COUNTER_ALIGN 0 28105 #define UC_INFO_B0_DEAD_TRAP_MICRO_RESET_COUNTER_BITS 8 28106 #define UC_INFO_B0_DEAD_TRAP_MICRO_RESET_COUNTER_SHIFT 0 28107 28108 28109 /**************************************************************************** 28110 * Warpcore_USER_uC_info_B1 28111 */ 28112 /**************************************************************************** 28113 * uC_info_B1 :: version 28114 */ 28115 /* uC_info_B1 :: version :: version [15:00] */ 28116 #define UC_INFO_B1_VERSION_VERSION_MASK 0xffff 28117 #define UC_INFO_B1_VERSION_VERSION_ALIGN 0 28118 #define UC_INFO_B1_VERSION_VERSION_BITS 16 28119 #define UC_INFO_B1_VERSION_VERSION_SHIFT 0 28120 28121 28122 /**************************************************************************** 28123 * uC_info_B1 :: target 28124 */ 28125 /* uC_info_B1 :: target :: target [15:00] */ 28126 #define UC_INFO_B1_TARGET_TARGET_MASK 0xffff 28127 #define UC_INFO_B1_TARGET_TARGET_ALIGN 0 28128 #define UC_INFO_B1_TARGET_TARGET_BITS 16 28129 #define UC_INFO_B1_TARGET_TARGET_SHIFT 0 28130 28131 28132 /**************************************************************************** 28133 * uC_info_B1 :: firmware_mode 28134 */ 28135 /* uC_info_B1 :: firmware_mode :: LN3_mode [15:12] */ 28136 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_MASK 0xf000 28137 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_ALIGN 0 28138 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_BITS 4 28139 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_SHIFT 12 28140 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_DEFAULT 0 28141 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_SFP_OPT_LR 1 28142 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_SFP_DAC 2 28143 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_XLAUI 3 28144 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_LONG_CH_6G 4 28145 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_BRDFE 5 28146 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_SW_3_TAP_TXFIR_TUNING 6 28147 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_CL72_NO_AN 7 28148 28149 /* uC_info_B1 :: firmware_mode :: LN2_mode [11:08] */ 28150 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_MASK 0x0f00 28151 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_ALIGN 0 28152 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_BITS 4 28153 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_SHIFT 8 28154 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_DEFAULT 0 28155 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_SFP_OPT_LR 1 28156 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_SFP_DAC 2 28157 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_XLAUI 3 28158 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_LONG_CH_6G 4 28159 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_BRDFE 5 28160 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_SW_3_TAP_TXFIR_TUNING 6 28161 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_CL72_NO_AN 7 28162 28163 /* uC_info_B1 :: firmware_mode :: LN1_mode [07:04] */ 28164 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_MASK 0x00f0 28165 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_ALIGN 0 28166 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_BITS 4 28167 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_SHIFT 4 28168 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_DEFAULT 0 28169 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_SFP_OPT_LR 1 28170 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_SFP_DAC 2 28171 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_XLAUI 3 28172 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_LONG_CH_6G 4 28173 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_BRDFE 5 28174 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_SW_3_TAP_TXFIR_TUNING 6 28175 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_CL72_NO_AN 7 28176 28177 /* uC_info_B1 :: firmware_mode :: LN0_mode [03:00] */ 28178 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_MASK 0x000f 28179 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_ALIGN 0 28180 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_BITS 4 28181 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_SHIFT 0 28182 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_DEFAULT 0 28183 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_SFP_OPT_LR 1 28184 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_SFP_DAC 2 28185 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_XLAUI 3 28186 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_LONG_CH_6G 4 28187 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_BRDFE 5 28188 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_SW_3_TAP_TXFIR_TUNING 6 28189 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_CL72_NO_AN 7 28190 28191 28192 /**************************************************************************** 28193 * uC_info_B1 :: gpio_ctrl_ln0 28194 */ 28195 /* uC_info_B1 :: gpio_ctrl_ln0 :: GPIO_CTRL_LN0 [15:00] */ 28196 #define UC_INFO_B1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_MASK 0xffff 28197 #define UC_INFO_B1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_ALIGN 0 28198 #define UC_INFO_B1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_BITS 16 28199 #define UC_INFO_B1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_SHIFT 0 28200 28201 28202 /**************************************************************************** 28203 * uC_info_B1 :: gpio_ctrl_ln1 28204 */ 28205 /* uC_info_B1 :: gpio_ctrl_ln1 :: GPIO_CTRL_LN1 [15:00] */ 28206 #define UC_INFO_B1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_MASK 0xffff 28207 #define UC_INFO_B1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_ALIGN 0 28208 #define UC_INFO_B1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_BITS 16 28209 #define UC_INFO_B1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_SHIFT 0 28210 28211 28212 /**************************************************************************** 28213 * uC_info_B1 :: gpio_ctrl_ln2 28214 */ 28215 /* uC_info_B1 :: gpio_ctrl_ln2 :: GPIO_CTRL_LN2 [15:00] */ 28216 #define UC_INFO_B1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_MASK 0xffff 28217 #define UC_INFO_B1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_ALIGN 0 28218 #define UC_INFO_B1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_BITS 16 28219 #define UC_INFO_B1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_SHIFT 0 28220 28221 28222 /**************************************************************************** 28223 * uC_info_B1 :: gpio_ctrl_ln3 28224 */ 28225 /* uC_info_B1 :: gpio_ctrl_ln3 :: GPIO_CTRL_LN3 [15:00] */ 28226 #define UC_INFO_B1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_MASK 0xffff 28227 #define UC_INFO_B1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_ALIGN 0 28228 #define UC_INFO_B1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_BITS 16 28229 #define UC_INFO_B1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_SHIFT 0 28230 28231 28232 /**************************************************************************** 28233 * uC_info_B1 :: gpio_sts_ln0 28234 */ 28235 /* uC_info_B1 :: gpio_sts_ln0 :: GPIO_STS_LN0 [15:00] */ 28236 #define UC_INFO_B1_GPIO_STS_LN0_GPIO_STS_LN0_MASK 0xffff 28237 #define UC_INFO_B1_GPIO_STS_LN0_GPIO_STS_LN0_ALIGN 0 28238 #define UC_INFO_B1_GPIO_STS_LN0_GPIO_STS_LN0_BITS 16 28239 #define UC_INFO_B1_GPIO_STS_LN0_GPIO_STS_LN0_SHIFT 0 28240 28241 28242 /**************************************************************************** 28243 * uC_info_B1 :: gpio_sts_ln1 28244 */ 28245 /* uC_info_B1 :: gpio_sts_ln1 :: GPIO_STS_LN1 [15:00] */ 28246 #define UC_INFO_B1_GPIO_STS_LN1_GPIO_STS_LN1_MASK 0xffff 28247 #define UC_INFO_B1_GPIO_STS_LN1_GPIO_STS_LN1_ALIGN 0 28248 #define UC_INFO_B1_GPIO_STS_LN1_GPIO_STS_LN1_BITS 16 28249 #define UC_INFO_B1_GPIO_STS_LN1_GPIO_STS_LN1_SHIFT 0 28250 28251 28252 /**************************************************************************** 28253 * uC_info_B1 :: gpio_sts_ln2 28254 */ 28255 /* uC_info_B1 :: gpio_sts_ln2 :: GPIO_STS_LN2 [15:00] */ 28256 #define UC_INFO_B1_GPIO_STS_LN2_GPIO_STS_LN2_MASK 0xffff 28257 #define UC_INFO_B1_GPIO_STS_LN2_GPIO_STS_LN2_ALIGN 0 28258 #define UC_INFO_B1_GPIO_STS_LN2_GPIO_STS_LN2_BITS 16 28259 #define UC_INFO_B1_GPIO_STS_LN2_GPIO_STS_LN2_SHIFT 0 28260 28261 28262 /**************************************************************************** 28263 * uC_info_B1 :: gpio_sts_ln3 28264 */ 28265 /* uC_info_B1 :: gpio_sts_ln3 :: GPIO_STS_LN3 [15:00] */ 28266 #define UC_INFO_B1_GPIO_STS_LN3_GPIO_STS_LN3_MASK 0xffff 28267 #define UC_INFO_B1_GPIO_STS_LN3_GPIO_STS_LN3_ALIGN 0 28268 #define UC_INFO_B1_GPIO_STS_LN3_GPIO_STS_LN3_BITS 16 28269 #define UC_INFO_B1_GPIO_STS_LN3_GPIO_STS_LN3_SHIFT 0 28270 28271 28272 /**************************************************************************** 28273 * uC_info_B1 :: regB 28274 */ 28275 /* uC_info_B1 :: regB :: reserved_for_eco0 [15:00] */ 28276 #define UC_INFO_B1_REGB_RESERVED_FOR_ECO0_MASK 0xffff 28277 #define UC_INFO_B1_REGB_RESERVED_FOR_ECO0_ALIGN 0 28278 #define UC_INFO_B1_REGB_RESERVED_FOR_ECO0_BITS 16 28279 #define UC_INFO_B1_REGB_RESERVED_FOR_ECO0_SHIFT 0 28280 28281 #define UC_INFO_B1_REGB_REFCLK_FREQ_MASK 0x007f 28282 #define UC_INFO_B1_REGB_REFCLK_FREQ_ALIGN 0 28283 #define UC_INFO_B1_REGB_REFCLK_FREQ_BITS 7 28284 #define UC_INFO_B1_REGB_REFCLK_FREQ_SHIFT 0 28285 28286 /**************************************************************************** 28287 * uC_info_B1 :: misc_ctrl 28288 */ 28289 /* uC_info_B1 :: misc_ctrl :: SerDes_pll_rate [11:07] */ 28290 #define UC_INFO_B1_MISC_CTRL_SERDES_PLL_RATE_MASK 0x0f80 28291 #define UC_INFO_B1_MISC_CTRL_SERDES_PLL_RATE_ALIGN 0 28292 #define UC_INFO_B1_MISC_CTRL_SERDES_PLL_RATE_BITS 5 28293 #define UC_INFO_B1_MISC_CTRL_SERDES_PLL_RATE_SHIFT 7 28294 28295 /**************************************************************************** 28296 * uC_info_B1 :: tuning_state_bypass 28297 */ 28298 /* uC_info_B1 :: tuning_state_bypass :: reserved_for_eco0 [15:09] */ 28299 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_MASK 0xfe00 28300 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_ALIGN 0 28301 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_BITS 7 28302 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_SHIFT 9 28303 28304 /* uC_info_B1 :: tuning_state_bypass :: bypass_steady_state_tuning [08:08] */ 28305 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_MASK 0x0100 28306 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_ALIGN 0 28307 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_BITS 1 28308 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_SHIFT 8 28309 28310 /* uC_info_B1 :: tuning_state_bypass :: bypass_cdr_lock_monitor [07:07] */ 28311 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_MASK 0x0080 28312 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_ALIGN 0 28313 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_BITS 1 28314 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_SHIFT 7 28315 28316 /* uC_info_B1 :: tuning_state_bypass :: bypass_dcd_tuning [06:06] */ 28317 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_MASK 0x0040 28318 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_ALIGN 0 28319 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_BITS 1 28320 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_SHIFT 6 28321 28322 /* uC_info_B1 :: tuning_state_bypass :: bypass_slicer_offset_tuning [05:05] */ 28323 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_MASK 0x0020 28324 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_ALIGN 0 28325 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_BITS 1 28326 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_SHIFT 5 28327 28328 /* uC_info_B1 :: tuning_state_bypass :: bypass_slicer_target_tuning [04:04] */ 28329 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_MASK 0x0010 28330 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_ALIGN 0 28331 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_BITS 1 28332 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_SHIFT 4 28333 28334 /* uC_info_B1 :: tuning_state_bypass :: bypass_vga_bias_tuning [03:03] */ 28335 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_MASK 0x0008 28336 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_ALIGN 0 28337 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_BITS 1 28338 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_SHIFT 3 28339 28340 /* uC_info_B1 :: tuning_state_bypass :: bypass_pf_tuning [02:02] */ 28341 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_MASK 0x0004 28342 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_ALIGN 0 28343 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_BITS 1 28344 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_SHIFT 2 28345 28346 /* uC_info_B1 :: tuning_state_bypass :: bypass_clk90_tuning [01:01] */ 28347 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_MASK 0x0002 28348 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_ALIGN 0 28349 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_BITS 1 28350 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_SHIFT 1 28351 28352 /* uC_info_B1 :: tuning_state_bypass :: bypass_os_vga_tuning [00:00] */ 28353 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_MASK 0x0001 28354 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_ALIGN 0 28355 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_BITS 1 28356 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_SHIFT 0 28357 28358 28359 /**************************************************************************** 28360 * uC_info_B1 :: temperature 28361 */ 28362 /* uC_info_B1 :: temperature :: force_temperature [15:15] */ 28363 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_MASK 0x8000 28364 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_ALIGN 0 28365 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_BITS 1 28366 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_SHIFT 15 28367 28368 /* uC_info_B1 :: temperature :: reserved_for_eco0 [14:14] */ 28369 #define UC_INFO_B1_TEMPERATURE_RESERVED_FOR_ECO0_MASK 0x4000 28370 #define UC_INFO_B1_TEMPERATURE_RESERVED_FOR_ECO0_ALIGN 0 28371 #define UC_INFO_B1_TEMPERATURE_RESERVED_FOR_ECO0_BITS 1 28372 #define UC_INFO_B1_TEMPERATURE_RESERVED_FOR_ECO0_SHIFT 14 28373 28374 /* uC_info_B1 :: temperature :: temp_idx [13:10] */ 28375 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_MASK 0x3c00 28376 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_ALIGN 0 28377 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_BITS 4 28378 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_SHIFT 10 28379 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE__22p9C 15 28380 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE__12p6C 14 28381 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE__3p0C 13 28382 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_6p7C 12 28383 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_16p4C 11 28384 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_26p6C 10 28385 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_36p3C 9 28386 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_46p0C 8 28387 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_56p2C 7 28388 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_65p9C 6 28389 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_75p6C 5 28390 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_85p3C 4 28391 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_95p5C 3 28392 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_105p2C 2 28393 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_114p9C 1 28394 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_125p1C 0 28395 28396 /* uC_info_B1 :: temperature :: temperature [09:00] */ 28397 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_MASK 0x03ff 28398 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_ALIGN 0 28399 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_BITS 10 28400 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_SHIFT 0 28401 28402 28403 /**************************************************************************** 28404 * uC_info_B1 :: crc 28405 */ 28406 /* uC_info_B1 :: crc :: crc [15:00] */ 28407 #define UC_INFO_B1_CRC_CRC_MASK 0xffff 28408 #define UC_INFO_B1_CRC_CRC_ALIGN 0 28409 #define UC_INFO_B1_CRC_CRC_BITS 16 28410 #define UC_INFO_B1_CRC_CRC_SHIFT 0 28411 28412 28413 /**************************************************************************** 28414 * Warpcore_USER_Dsc1b0 28415 */ 28416 /**************************************************************************** 28417 * Dsc1b0 :: cdr_ctrl0 28418 */ 28419 /* Dsc1b0 :: cdr_ctrl0 :: cdros_xfi_integ_sat_sel [15:15] */ 28420 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_MASK 0x8000 28421 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_ALIGN 0 28422 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_BITS 1 28423 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_SHIFT 15 28424 28425 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_m1_slicer_only [14:14] */ 28426 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_MASK 0x4000 28427 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_ALIGN 0 28428 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_BITS 1 28429 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_SHIFT 14 28430 28431 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_p1_slicer_only [13:13] */ 28432 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_MASK 0x2000 28433 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_ALIGN 0 28434 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_BITS 1 28435 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_SHIFT 13 28436 28437 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */ 28438 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_MASK 0x1000 28439 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 28440 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_BITS 1 28441 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_SHIFT 12 28442 28443 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */ 28444 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0800 28445 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 28446 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 28447 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 11 28448 28449 /* Dsc1b0 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */ 28450 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_MASK 0x0400 28451 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN 0 28452 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_BITS 1 28453 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT 10 28454 28455 /* Dsc1b0 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */ 28456 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_MASK 0x0200 28457 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN 0 28458 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_BITS 1 28459 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT 9 28460 28461 /* Dsc1b0 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */ 28462 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK 0x0180 28463 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN 0 28464 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS 2 28465 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT 7 28466 28467 /* Dsc1b0 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */ 28468 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK 0x0040 28469 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN 0 28470 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS 1 28471 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT 6 28472 28473 /* Dsc1b0 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */ 28474 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK 0x0020 28475 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN 0 28476 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS 1 28477 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT 5 28478 28479 /* Dsc1b0 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */ 28480 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK 0x0010 28481 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN 0 28482 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS 1 28483 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT 4 28484 28485 /* Dsc1b0 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */ 28486 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK 0x0008 28487 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN 0 28488 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS 1 28489 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT 3 28490 28491 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */ 28492 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK 0x0004 28493 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN 0 28494 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS 1 28495 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT 2 28496 28497 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_en [01:01] */ 28498 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_MASK 0x0002 28499 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_ALIGN 0 28500 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_BITS 1 28501 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_SHIFT 1 28502 28503 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */ 28504 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK 0x0001 28505 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 28506 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS 1 28507 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT 0 28508 28509 28510 /**************************************************************************** 28511 * Dsc1b0 :: cdr_ctrl1 28512 */ 28513 /* Dsc1b0 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */ 28514 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 28515 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 28516 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 16 28517 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 28518 28519 28520 /**************************************************************************** 28521 * Dsc1b0 :: cdr_ctrl2 28522 */ 28523 /* Dsc1b0 :: cdr_ctrl2 :: reserved_for_eco0 [15:10] */ 28524 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xfc00 28525 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 28526 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 6 28527 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 10 28528 28529 /* Dsc1b0 :: cdr_ctrl2 :: cdros_phase_err_offset [09:06] */ 28530 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_MASK 0x03c0 28531 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_ALIGN 0 28532 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_BITS 4 28533 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_SHIFT 6 28534 28535 /* Dsc1b0 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */ 28536 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK 0x003f 28537 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN 0 28538 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS 6 28539 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT 0 28540 28541 28542 /**************************************************************************** 28543 * Dsc1b0 :: pi_ctrl0 28544 */ 28545 /* Dsc1b0 :: pi_ctrl0 :: pi_cw_rst [15:15] */ 28546 #define DSC1B0_PI_CTRL0_PI_CW_RST_MASK 0x8000 28547 #define DSC1B0_PI_CTRL0_PI_CW_RST_ALIGN 0 28548 #define DSC1B0_PI_CTRL0_PI_CW_RST_BITS 1 28549 #define DSC1B0_PI_CTRL0_PI_CW_RST_SHIFT 15 28550 28551 /* Dsc1b0 :: pi_ctrl0 :: interp_ctrl_dsel [14:12] */ 28552 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_MASK 0x7000 28553 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_ALIGN 0 28554 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_BITS 3 28555 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_SHIFT 12 28556 28557 /* Dsc1b0 :: pi_ctrl0 :: interp_ctrl_cap [11:11] */ 28558 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_MASK 0x0800 28559 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_ALIGN 0 28560 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_BITS 1 28561 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_SHIFT 11 28562 28563 /* Dsc1b0 :: pi_ctrl0 :: reserved_for_eco0 [10:06] */ 28564 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0x07c0 28565 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 28566 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_BITS 5 28567 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 6 28568 28569 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult_os8 [05:05] */ 28570 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_MASK 0x0020 28571 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_ALIGN 0 28572 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_BITS 1 28573 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_SHIFT 5 28574 28575 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult_os4 [04:04] */ 28576 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_MASK 0x0010 28577 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_ALIGN 0 28578 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_BITS 1 28579 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_SHIFT 4 28580 28581 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult_os3 [03:03] */ 28582 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_MASK 0x0008 28583 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_ALIGN 0 28584 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_BITS 1 28585 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_SHIFT 3 28586 28587 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult_os2 [02:02] */ 28588 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_MASK 0x0004 28589 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_ALIGN 0 28590 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_BITS 1 28591 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_SHIFT 2 28592 28593 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_invert [01:01] */ 28594 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0002 28595 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 28596 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_BITS 1 28597 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_SHIFT 1 28598 28599 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 28600 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 28601 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 28602 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 28603 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 28604 28605 28606 /**************************************************************************** 28607 * Dsc1b0 :: pi_ctrl1 28608 */ 28609 /* Dsc1b0 :: pi_ctrl1 :: reserved_for_eco0 [15:12] */ 28610 #define DSC1B0_PI_CTRL1_RESERVED_FOR_ECO0_MASK 0xf000 28611 #define DSC1B0_PI_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 28612 #define DSC1B0_PI_CTRL1_RESERVED_FOR_ECO0_BITS 4 28613 #define DSC1B0_PI_CTRL1_RESERVED_FOR_ECO0_SHIFT 12 28614 28615 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_step_dir [11:11] */ 28616 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_MASK 0x0800 28617 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_ALIGN 0 28618 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_BITS 1 28619 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_SHIFT 11 28620 28621 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_step [10:09] */ 28622 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_MASK 0x0600 28623 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_ALIGN 0 28624 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_BITS 2 28625 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_SHIFT 9 28626 28627 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_delta [08:04] */ 28628 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_MASK 0x01f0 28629 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_ALIGN 0 28630 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_BITS 5 28631 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_SHIFT 4 28632 28633 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_strobe [03:03] */ 28634 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_MASK 0x0008 28635 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_ALIGN 0 28636 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_BITS 1 28637 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_SHIFT 3 28638 28639 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_rotate_override [02:02] */ 28640 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_MASK 0x0004 28641 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_ALIGN 0 28642 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_BITS 1 28643 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_SHIFT 2 28644 28645 /* Dsc1b0 :: pi_ctrl1 :: pi_clk90_offset_override [01:01] */ 28646 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0002 28647 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 28648 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_BITS 1 28649 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_SHIFT 1 28650 28651 /* Dsc1b0 :: pi_ctrl1 :: pi_dual_phase_override [00:00] */ 28652 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_MASK 0x0001 28653 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 28654 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_BITS 1 28655 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_SHIFT 0 28656 28657 28658 /**************************************************************************** 28659 * Dsc1b0 :: dfe_vga_ctrl0 28660 */ 28661 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_abs_sum_max [15:09] */ 28662 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_MASK 0xfe00 28663 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_ALIGN 0 28664 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_BITS 7 28665 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_SHIFT 9 28666 28667 /* Dsc1b0 :: dfe_vga_ctrl0 :: random_tapsel_disable [08:08] */ 28668 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_MASK 0x0100 28669 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_ALIGN 0 28670 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_BITS 1 28671 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_SHIFT 8 28672 28673 /* Dsc1b0 :: dfe_vga_ctrl0 :: cor_neg2_en [07:07] */ 28674 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_MASK 0x0080 28675 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_ALIGN 0 28676 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_BITS 1 28677 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_SHIFT 7 28678 28679 /* Dsc1b0 :: dfe_vga_ctrl0 :: cor_neg1_en [06:06] */ 28680 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_MASK 0x0040 28681 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_ALIGN 0 28682 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_BITS 1 28683 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_SHIFT 6 28684 28685 /* Dsc1b0 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */ 28686 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_MASK 0x0020 28687 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN 0 28688 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_BITS 1 28689 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT 5 28690 28691 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */ 28692 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_MASK 0x0010 28693 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN 0 28694 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_BITS 1 28695 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT 4 28696 28697 /* Dsc1b0 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */ 28698 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0008 28699 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 28700 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 28701 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 3 28702 28703 /* Dsc1b0 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */ 28704 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0004 28705 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 28706 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 28707 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 2 28708 28709 /* Dsc1b0 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */ 28710 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_MASK 0x0002 28711 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN 0 28712 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_BITS 1 28713 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT 1 28714 28715 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */ 28716 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0001 28717 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 28718 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 28719 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 0 28720 28721 28722 /**************************************************************************** 28723 * Dsc1b0 :: dfe_vga_ctrl1 28724 */ 28725 /* Dsc1b0 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:14] */ 28726 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0xc000 28727 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 28728 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 2 28729 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 14 28730 28731 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_llms_update_count_sel [13:12] */ 28732 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_MASK 0x3000 28733 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_ALIGN 0 28734 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_BITS 2 28735 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_SHIFT 12 28736 28737 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_llms_en [11:11] */ 28738 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_MASK 0x0800 28739 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_ALIGN 0 28740 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_BITS 1 28741 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_SHIFT 11 28742 28743 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_cdros_qphase_mult_en [10:10] */ 28744 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_MASK 0x0400 28745 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_ALIGN 0 28746 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_BITS 1 28747 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_SHIFT 10 28748 28749 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_tap_2_dcd [09:06] */ 28750 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_MASK 0x03c0 28751 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_ALIGN 0 28752 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_BITS 4 28753 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_SHIFT 6 28754 28755 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_tap_1_do [05:03] */ 28756 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_MASK 0x0038 28757 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_ALIGN 0 28758 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_BITS 3 28759 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_SHIFT 3 28760 28761 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_tap_1_de [02:00] */ 28762 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_MASK 0x0007 28763 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_ALIGN 0 28764 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_BITS 3 28765 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_SHIFT 0 28766 28767 28768 /**************************************************************************** 28769 * Dsc1b0 :: dfe_vga_ctrl2 28770 */ 28771 /* Dsc1b0 :: dfe_vga_ctrl2 :: vga3_override_val [15:12] */ 28772 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_MASK 0xf000 28773 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_ALIGN 0 28774 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_BITS 4 28775 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_SHIFT 12 28776 28777 /* Dsc1b0 :: dfe_vga_ctrl2 :: vga3_override_en [11:11] */ 28778 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_MASK 0x0800 28779 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_ALIGN 0 28780 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_BITS 1 28781 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_SHIFT 11 28782 28783 /* Dsc1b0 :: dfe_vga_ctrl2 :: reserved_for_eco0 [10:10] */ 28784 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK 0x0400 28785 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 28786 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS 1 28787 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT 10 28788 28789 /* Dsc1b0 :: dfe_vga_ctrl2 :: dfe_vga_write_tapsel [09:07] */ 28790 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_MASK 0x0380 28791 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_ALIGN 0 28792 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_BITS 3 28793 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_SHIFT 7 28794 28795 /* Dsc1b0 :: dfe_vga_ctrl2 :: dfe_vga_write_val [06:01] */ 28796 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_MASK 0x007e 28797 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_ALIGN 0 28798 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_BITS 6 28799 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_SHIFT 1 28800 28801 /* Dsc1b0 :: dfe_vga_ctrl2 :: dfe_vga_write_en [00:00] */ 28802 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_MASK 0x0001 28803 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_ALIGN 0 28804 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_BITS 1 28805 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_SHIFT 0 28806 28807 28808 /**************************************************************************** 28809 * Dsc1b0 :: dfe_vga_ctrl3 28810 */ 28811 /* Dsc1b0 :: dfe_vga_ctrl3 :: trnsum_otap_en [15:08] */ 28812 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_MASK 0xff00 28813 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_ALIGN 0 28814 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_BITS 8 28815 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_SHIFT 8 28816 28817 /* Dsc1b0 :: dfe_vga_ctrl3 :: trnsum_etap_en [07:00] */ 28818 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_MASK 0x00ff 28819 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_ALIGN 0 28820 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_BITS 8 28821 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_SHIFT 0 28822 28823 28824 /**************************************************************************** 28825 * Dsc1b0 :: dfe_vga_ctrl4 28826 */ 28827 /* Dsc1b0 :: dfe_vga_ctrl4 :: trnsum_otap_sign [15:08] */ 28828 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_MASK 0xff00 28829 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_ALIGN 0 28830 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_BITS 8 28831 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_SHIFT 8 28832 28833 /* Dsc1b0 :: dfe_vga_ctrl4 :: trnsum_etap_sign [07:00] */ 28834 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_MASK 0x00ff 28835 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_ALIGN 0 28836 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_BITS 8 28837 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_SHIFT 0 28838 28839 28840 /**************************************************************************** 28841 * Dsc1b0 :: dfe_vga_ctrl5 28842 */ 28843 /* Dsc1b0 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */ 28844 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK 0xfc00 28845 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN 0 28846 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS 6 28847 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT 10 28848 28849 /* Dsc1b0 :: dfe_vga_ctrl5 :: vga_cor_sel_e [09:05] */ 28850 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_MASK 0x03e0 28851 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_ALIGN 0 28852 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_BITS 5 28853 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_SHIFT 5 28854 28855 /* Dsc1b0 :: dfe_vga_ctrl5 :: vga_cor_sel_o [04:00] */ 28856 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_MASK 0x001f 28857 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_ALIGN 0 28858 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_BITS 5 28859 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_SHIFT 0 28860 28861 28862 /**************************************************************************** 28863 * Dsc1b0 :: dfe_vga_ctrl6 28864 */ 28865 /* Dsc1b0 :: dfe_vga_ctrl6 :: reserved_for_eco0 [15:10] */ 28866 #define DSC1B0_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_MASK 0xfc00 28867 #define DSC1B0_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 28868 #define DSC1B0_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_BITS 6 28869 #define DSC1B0_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_SHIFT 10 28870 28871 /* Dsc1b0 :: dfe_vga_ctrl6 :: dfe_cor_sel_e [09:05] */ 28872 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_MASK 0x03e0 28873 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_ALIGN 0 28874 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_BITS 5 28875 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_SHIFT 5 28876 28877 /* Dsc1b0 :: dfe_vga_ctrl6 :: dfe_cor_sel_o [04:00] */ 28878 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_MASK 0x001f 28879 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_ALIGN 0 28880 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_BITS 5 28881 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_SHIFT 0 28882 28883 28884 /**************************************************************************** 28885 * Dsc1b0 :: dfe_vga_ctrl7 28886 */ 28887 /* Dsc1b0 :: dfe_vga_ctrl7 :: disable_cl72_rcving_ctrl_frame [15:15] */ 28888 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_MASK 0x8000 28889 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_ALIGN 0 28890 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_BITS 1 28891 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_SHIFT 15 28892 28893 /* Dsc1b0 :: dfe_vga_ctrl7 :: pattern [14:08] */ 28894 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_MASK 0x7f00 28895 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_ALIGN 0 28896 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BITS 7 28897 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_SHIFT 8 28898 28899 /* Dsc1b0 :: dfe_vga_ctrl7 :: pattern_bit_en [07:01] */ 28900 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_MASK 0x00fe 28901 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_ALIGN 0 28902 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_BITS 7 28903 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_SHIFT 1 28904 28905 /* Dsc1b0 :: dfe_vga_ctrl7 :: pattern_en [00:00] */ 28906 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_MASK 0x0001 28907 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_ALIGN 0 28908 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_BITS 1 28909 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_SHIFT 0 28910 28911 28912 /**************************************************************************** 28913 * Dsc1b0 :: dsc_diag_ctrl0 28914 */ 28915 /* Dsc1b0 :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:12] */ 28916 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK 0xf000 28917 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 28918 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS 4 28919 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT 12 28920 28921 /* Dsc1b0 :: dsc_diag_ctrl0 :: osx2_diag_ctrl [11:11] */ 28922 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_MASK 0x0800 28923 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_ALIGN 0 28924 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_BITS 1 28925 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_SHIFT 11 28926 28927 /* Dsc1b0 :: dsc_diag_ctrl0 :: voffset [10:07] */ 28928 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_MASK 0x0780 28929 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_ALIGN 0 28930 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_BITS 4 28931 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_SHIFT 7 28932 28933 /* Dsc1b0 :: dsc_diag_ctrl0 :: hoffset [06:01] */ 28934 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_MASK 0x007e 28935 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_ALIGN 0 28936 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_BITS 6 28937 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_SHIFT 1 28938 28939 /* Dsc1b0 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */ 28940 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK 0x0001 28941 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN 0 28942 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS 1 28943 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT 0 28944 28945 28946 /**************************************************************************** 28947 * Dsc1b0 :: uC_ctrl 28948 */ 28949 /* Dsc1b0 :: uC_ctrl :: supplement_info [15:08] */ 28950 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_MASK 0xff00 28951 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_ALIGN 0 28952 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_BITS 8 28953 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_SHIFT 8 28954 28955 /* Dsc1b0 :: uC_ctrl :: ready_for_cmd [07:07] */ 28956 #define DSC1B0_UC_CTRL_READY_FOR_CMD_MASK 0x0080 28957 #define DSC1B0_UC_CTRL_READY_FOR_CMD_ALIGN 0 28958 #define DSC1B0_UC_CTRL_READY_FOR_CMD_BITS 1 28959 #define DSC1B0_UC_CTRL_READY_FOR_CMD_SHIFT 7 28960 28961 /* Dsc1b0 :: uC_ctrl :: error_found [06:06] */ 28962 #define DSC1B0_UC_CTRL_ERROR_FOUND_MASK 0x0040 28963 #define DSC1B0_UC_CTRL_ERROR_FOUND_ALIGN 0 28964 #define DSC1B0_UC_CTRL_ERROR_FOUND_BITS 1 28965 #define DSC1B0_UC_CTRL_ERROR_FOUND_SHIFT 6 28966 28967 /* Dsc1b0 :: uC_ctrl :: cmd_info [05:04] */ 28968 #define DSC1B0_UC_CTRL_CMD_INFO_MASK 0x0030 28969 #define DSC1B0_UC_CTRL_CMD_INFO_ALIGN 0 28970 #define DSC1B0_UC_CTRL_CMD_INFO_BITS 2 28971 #define DSC1B0_UC_CTRL_CMD_INFO_SHIFT 4 28972 28973 /* Dsc1b0 :: uC_ctrl :: gp_uC_req [03:00] */ 28974 #define DSC1B0_UC_CTRL_GP_UC_REQ_MASK 0x000f 28975 #define DSC1B0_UC_CTRL_GP_UC_REQ_ALIGN 0 28976 #define DSC1B0_UC_CTRL_GP_UC_REQ_BITS 4 28977 #define DSC1B0_UC_CTRL_GP_UC_REQ_SHIFT 0 28978 28979 28980 /**************************************************************************** 28981 * Warpcore_USER_Dsc2b0 28982 */ 28983 /**************************************************************************** 28984 * Dsc2b0 :: acq_sm_ctrl0 28985 */ 28986 /* Dsc2b0 :: acq_sm_ctrl0 :: cl72_timer_en [15:15] */ 28987 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_MASK 0x8000 28988 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_ALIGN 0 28989 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_BITS 1 28990 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_SHIFT 15 28991 28992 /* Dsc2b0 :: acq_sm_ctrl0 :: acq2_timeout [14:10] */ 28993 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_MASK 0x7c00 28994 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_ALIGN 0 28995 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_BITS 5 28996 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_SHIFT 10 28997 28998 /* Dsc2b0 :: acq_sm_ctrl0 :: acq1_timeout [09:05] */ 28999 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_MASK 0x03e0 29000 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_ALIGN 0 29001 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_BITS 5 29002 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_SHIFT 5 29003 29004 /* Dsc2b0 :: acq_sm_ctrl0 :: acqcdr_timeout [04:00] */ 29005 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_MASK 0x001f 29006 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_ALIGN 0 29007 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_BITS 5 29008 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_SHIFT 0 29009 29010 29011 /**************************************************************************** 29012 * Dsc2b0 :: acq_sm_ctrl1 29013 */ 29014 /* Dsc2b0 :: acq_sm_ctrl1 :: acqvga_timeout [15:11] */ 29015 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_MASK 0xf800 29016 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_ALIGN 0 29017 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_BITS 5 29018 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_SHIFT 11 29019 29020 /* Dsc2b0 :: acq_sm_ctrl1 :: bypass_os_integ_xfer [10:10] */ 29021 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_MASK 0x0400 29022 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_ALIGN 0 29023 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_BITS 1 29024 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_SHIFT 10 29025 29026 /* Dsc2b0 :: acq_sm_ctrl1 :: dfe_frzval [09:05] */ 29027 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_MASK 0x03e0 29028 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_ALIGN 0 29029 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_BITS 5 29030 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_SHIFT 5 29031 29032 /* Dsc2b0 :: acq_sm_ctrl1 :: dfe_frcfrz [04:04] */ 29033 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_MASK 0x0010 29034 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_ALIGN 0 29035 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_BITS 1 29036 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_SHIFT 4 29037 29038 /* Dsc2b0 :: acq_sm_ctrl1 :: vga_frzval [03:03] */ 29039 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_MASK 0x0008 29040 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_ALIGN 0 29041 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_BITS 1 29042 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_SHIFT 3 29043 29044 /* Dsc2b0 :: acq_sm_ctrl1 :: vga_frcfrz [02:02] */ 29045 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_MASK 0x0004 29046 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_ALIGN 0 29047 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_BITS 1 29048 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_SHIFT 2 29049 29050 /* Dsc2b0 :: acq_sm_ctrl1 :: dsc_clr_val [01:01] */ 29051 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_MASK 0x0002 29052 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_ALIGN 0 29053 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_BITS 1 29054 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_SHIFT 1 29055 29056 /* Dsc2b0 :: acq_sm_ctrl1 :: dsc_clr_frc [00:00] */ 29057 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_MASK 0x0001 29058 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_ALIGN 0 29059 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_BITS 1 29060 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_SHIFT 0 29061 29062 29063 /**************************************************************************** 29064 * Dsc2b0 :: acq_sm_ctrl2 29065 */ 29066 /* Dsc2b0 :: acq_sm_ctrl2 :: sw_handover [15:15] */ 29067 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_MASK 0x8000 29068 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_ALIGN 0 29069 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_BITS 1 29070 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_SHIFT 15 29071 29072 /* Dsc2b0 :: acq_sm_ctrl2 :: eee_acq_2_timeout [14:10] */ 29073 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_MASK 0x7c00 29074 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_ALIGN 0 29075 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_BITS 5 29076 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_SHIFT 10 29077 29078 /* Dsc2b0 :: acq_sm_ctrl2 :: eee_acq_phase_timeout [09:05] */ 29079 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_MASK 0x03e0 29080 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_ALIGN 0 29081 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_BITS 5 29082 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_SHIFT 5 29083 29084 /* Dsc2b0 :: acq_sm_ctrl2 :: skip_acq [04:04] */ 29085 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_MASK 0x0010 29086 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_ALIGN 0 29087 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_BITS 1 29088 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_SHIFT 4 29089 29090 /* Dsc2b0 :: acq_sm_ctrl2 :: train2_req [03:03] */ 29091 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_MASK 0x0008 29092 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_ALIGN 0 29093 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_BITS 1 29094 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_SHIFT 3 29095 29096 /* Dsc2b0 :: acq_sm_ctrl2 :: train1_req [02:02] */ 29097 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_MASK 0x0004 29098 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_ALIGN 0 29099 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_BITS 1 29100 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_SHIFT 2 29101 29102 /* Dsc2b0 :: acq_sm_ctrl2 :: soft_ack [01:01] */ 29103 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_MASK 0x0002 29104 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_ALIGN 0 29105 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_BITS 1 29106 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_SHIFT 1 29107 29108 /* Dsc2b0 :: acq_sm_ctrl2 :: train_mode_en [00:00] */ 29109 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_MASK 0x0001 29110 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_ALIGN 0 29111 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_BITS 1 29112 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_SHIFT 0 29113 29114 29115 /**************************************************************************** 29116 * Dsc2b0 :: acq_sm_ctrl3 29117 */ 29118 /* Dsc2b0 :: acq_sm_ctrl3 :: pause_level_trigger_en [15:15] */ 29119 #define DSC2B0_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_MASK 0x8000 29120 #define DSC2B0_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_ALIGN 0 29121 #define DSC2B0_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_BITS 1 29122 #define DSC2B0_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_SHIFT 15 29123 29124 /* Dsc2b0 :: acq_sm_ctrl3 :: reserved_for_eco0 [14:14] */ 29125 #define DSC2B0_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0x4000 29126 #define DSC2B0_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 29127 #define DSC2B0_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_BITS 1 29128 #define DSC2B0_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 14 29129 29130 /* Dsc2b0 :: acq_sm_ctrl3 :: os_dfe_en [13:13] */ 29131 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_MASK 0x2000 29132 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_ALIGN 0 29133 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_BITS 1 29134 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_SHIFT 13 29135 29136 /* Dsc2b0 :: acq_sm_ctrl3 :: dfe_taps2_5_en [12:12] */ 29137 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_MASK 0x1000 29138 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_ALIGN 0 29139 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_BITS 1 29140 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_SHIFT 12 29141 29142 /* Dsc2b0 :: acq_sm_ctrl3 :: dfe_gain_acq2 [11:10] */ 29143 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_MASK 0x0c00 29144 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN 0 29145 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_BITS 2 29146 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT 10 29147 29148 /* Dsc2b0 :: acq_sm_ctrl3 :: dfe_gain_acq1 [09:08] */ 29149 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_MASK 0x0300 29150 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN 0 29151 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_BITS 2 29152 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT 8 29153 29154 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acq2 [07:06] */ 29155 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_MASK 0x00c0 29156 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN 0 29157 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_BITS 2 29158 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT 6 29159 29160 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acq1 [05:04] */ 29161 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_MASK 0x0030 29162 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN 0 29163 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_BITS 2 29164 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT 4 29165 29166 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acqcdr [03:02] */ 29167 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_MASK 0x000c 29168 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN 0 29169 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_BITS 2 29170 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT 2 29171 29172 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acqvga [01:00] */ 29173 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_MASK 0x0003 29174 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN 0 29175 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_BITS 2 29176 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT 0 29177 29178 29179 /**************************************************************************** 29180 * Dsc2b0 :: acq_sm_ctrl4 29181 */ 29182 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */ 29183 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK 0xc000 29184 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN 0 29185 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS 2 29186 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT 14 29187 29188 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros38_bwsel_prop_offset [13:12] */ 29189 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_MASK 0x3000 29190 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_ALIGN 0 29191 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_BITS 2 29192 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_SHIFT 12 29193 29194 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [11:08] */ 29195 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x0f00 29196 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 29197 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 29198 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 8 29199 29200 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acqcdr [07:04] */ 29201 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK 0x00f0 29202 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 29203 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS 4 29204 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT 4 29205 29206 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acqvga [03:00] */ 29207 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_MASK 0x000f 29208 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_ALIGN 0 29209 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_BITS 4 29210 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_SHIFT 0 29211 29212 29213 /**************************************************************************** 29214 * Dsc2b0 :: acq_sm_ctrl5 29215 */ 29216 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_eee_acq2 [15:12] */ 29217 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_MASK 0xf000 29218 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_ALIGN 0 29219 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_BITS 4 29220 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_SHIFT 12 29221 29222 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [11:08] */ 29223 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0x0f00 29224 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 29225 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 29226 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 8 29227 29228 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acqcdr [07:04] */ 29229 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x00f0 29230 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 29231 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 29232 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 4 29233 29234 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acqvga [03:00] */ 29235 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_MASK 0x000f 29236 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_ALIGN 0 29237 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_BITS 4 29238 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_SHIFT 0 29239 29240 29241 /**************************************************************************** 29242 * Dsc2b0 :: acq_sm_ctrl6 29243 */ 29244 /* Dsc2b0 :: acq_sm_ctrl6 :: reserved_for_eco0 [15:12] */ 29245 #define DSC2B0_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_MASK 0xf000 29246 #define DSC2B0_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 29247 #define DSC2B0_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_BITS 4 29248 #define DSC2B0_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT 12 29249 29250 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acq2 [11:09] */ 29251 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0e00 29252 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 29253 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_BITS 3 29254 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_SHIFT 9 29255 29256 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acq1 [08:06] */ 29257 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_MASK 0x01c0 29258 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 29259 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_BITS 3 29260 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_SHIFT 6 29261 29262 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acqcdr [05:03] */ 29263 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x0038 29264 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 29265 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 29266 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 3 29267 29268 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [02:00] */ 29269 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK 0x0007 29270 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN 0 29271 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS 3 29272 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT 0 29273 29274 29275 /**************************************************************************** 29276 * Dsc2b0 :: acq_sm_ctrl7 29277 */ 29278 /* Dsc2b0 :: acq_sm_ctrl7 :: reserved_for_eco0 [15:12] */ 29279 #define DSC2B0_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_MASK 0xf000 29280 #define DSC2B0_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN 0 29281 #define DSC2B0_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_BITS 4 29282 #define DSC2B0_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT 12 29283 29284 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acq2 [11:09] */ 29285 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0e00 29286 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 29287 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_BITS 3 29288 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 9 29289 29290 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acq1 [08:06] */ 29291 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x01c0 29292 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 29293 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_BITS 3 29294 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 6 29295 29296 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acqcdr [05:03] */ 29297 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x0038 29298 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 29299 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_BITS 3 29300 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 3 29301 29302 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acqphase [02:00] */ 29303 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_MASK 0x0007 29304 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN 0 29305 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_BITS 3 29306 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT 0 29307 29308 29309 /**************************************************************************** 29310 * Dsc2b0 :: acq_sm_ctrl8 29311 */ 29312 /* Dsc2b0 :: acq_sm_ctrl8 :: reserved_for_eco0 [15:15] */ 29313 #define DSC2B0_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_MASK 0x8000 29314 #define DSC2B0_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN 0 29315 #define DSC2B0_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_BITS 1 29316 #define DSC2B0_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT 15 29317 29318 /* Dsc2b0 :: acq_sm_ctrl8 :: cdros_bwsel_prop_eee_acqphase [14:11] */ 29319 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_MASK 0x7800 29320 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_ALIGN 0 29321 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_BITS 4 29322 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_SHIFT 11 29323 29324 /* Dsc2b0 :: acq_sm_ctrl8 :: phase_sat_ctrl_100fx [10:09] */ 29325 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_MASK 0x0600 29326 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_ALIGN 0 29327 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_BITS 2 29328 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_SHIFT 9 29329 29330 /* Dsc2b0 :: acq_sm_ctrl8 :: pi_phase_step_mult_100fx [08:08] */ 29331 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_MASK 0x0100 29332 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_ALIGN 0 29333 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_BITS 1 29334 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_SHIFT 8 29335 29336 /* Dsc2b0 :: acq_sm_ctrl8 :: cdros_bwsel_integ_100fx [07:04] */ 29337 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_MASK 0x00f0 29338 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_ALIGN 0 29339 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_BITS 4 29340 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_SHIFT 4 29341 29342 /* Dsc2b0 :: acq_sm_ctrl8 :: cdros_bwsel_prop_100fx [03:00] */ 29343 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_MASK 0x000f 29344 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_ALIGN 0 29345 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_BITS 4 29346 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_SHIFT 0 29347 29348 29349 /**************************************************************************** 29350 * Dsc2b0 :: dsc_ana_ctrl0 29351 */ 29352 /* Dsc2b0 :: dsc_ana_ctrl0 :: reserved_for_eco0 [15:15] */ 29353 #define DSC2B0_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_MASK 0x8000 29354 #define DSC2B0_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 29355 #define DSC2B0_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_BITS 1 29356 #define DSC2B0_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_SHIFT 15 29357 29358 /* Dsc2b0 :: dsc_ana_ctrl0 :: force_p1_ctrl_strobe [14:14] */ 29359 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_MASK 0x4000 29360 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_ALIGN 0 29361 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_BITS 1 29362 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_SHIFT 14 29363 29364 /* Dsc2b0 :: dsc_ana_ctrl0 :: force_p1_odd_ctrl [13:13] */ 29365 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_MASK 0x2000 29366 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_ALIGN 0 29367 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_BITS 1 29368 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_SHIFT 13 29369 29370 /* Dsc2b0 :: dsc_ana_ctrl0 :: force_p1_evn_ctrl [12:12] */ 29371 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_MASK 0x1000 29372 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_ALIGN 0 29373 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_BITS 1 29374 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_SHIFT 12 29375 29376 /* Dsc2b0 :: dsc_ana_ctrl0 :: p1_odd_ctrl [11:06] */ 29377 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK 0x0fc0 29378 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN 0 29379 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS 6 29380 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT 6 29381 29382 /* Dsc2b0 :: dsc_ana_ctrl0 :: p1_evn_ctrl [05:00] */ 29383 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_MASK 0x003f 29384 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_ALIGN 0 29385 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_BITS 6 29386 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_SHIFT 0 29387 29388 29389 /**************************************************************************** 29390 * Dsc2b0 :: dsc_ana_ctrl1 29391 */ 29392 /* Dsc2b0 :: dsc_ana_ctrl1 :: reserved_for_eco0 [15:15] */ 29393 #define DSC2B0_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 29394 #define DSC2B0_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 29395 #define DSC2B0_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_BITS 1 29396 #define DSC2B0_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 29397 29398 /* Dsc2b0 :: dsc_ana_ctrl1 :: force_d_ctrl_strobe [14:14] */ 29399 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_MASK 0x4000 29400 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_ALIGN 0 29401 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_BITS 1 29402 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_SHIFT 14 29403 29404 /* Dsc2b0 :: dsc_ana_ctrl1 :: force_d_odd_ctrl [13:13] */ 29405 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_MASK 0x2000 29406 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_ALIGN 0 29407 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_BITS 1 29408 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_SHIFT 13 29409 29410 /* Dsc2b0 :: dsc_ana_ctrl1 :: force_d_evn_ctrl [12:12] */ 29411 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_MASK 0x1000 29412 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_ALIGN 0 29413 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_BITS 1 29414 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_SHIFT 12 29415 29416 /* Dsc2b0 :: dsc_ana_ctrl1 :: d_odd_ctrl [11:06] */ 29417 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_MASK 0x0fc0 29418 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_ALIGN 0 29419 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_BITS 6 29420 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_SHIFT 6 29421 29422 /* Dsc2b0 :: dsc_ana_ctrl1 :: d_evn_ctrl [05:00] */ 29423 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_MASK 0x003f 29424 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN 0 29425 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_BITS 6 29426 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT 0 29427 29428 29429 /**************************************************************************** 29430 * Dsc2b0 :: dsc_ana_ctrl2 29431 */ 29432 /* Dsc2b0 :: dsc_ana_ctrl2 :: reserved_for_eco0 [15:15] */ 29433 #define DSC2B0_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 29434 #define DSC2B0_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 29435 #define DSC2B0_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_BITS 1 29436 #define DSC2B0_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 29437 29438 /* Dsc2b0 :: dsc_ana_ctrl2 :: force_m1_ctrl_strobe [14:14] */ 29439 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_MASK 0x4000 29440 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_ALIGN 0 29441 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_BITS 1 29442 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_SHIFT 14 29443 29444 /* Dsc2b0 :: dsc_ana_ctrl2 :: force_m1_odd_ctrl [13:13] */ 29445 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_MASK 0x2000 29446 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_ALIGN 0 29447 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_BITS 1 29448 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_SHIFT 13 29449 29450 /* Dsc2b0 :: dsc_ana_ctrl2 :: force_m1_evn_ctrl [12:12] */ 29451 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_MASK 0x1000 29452 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_ALIGN 0 29453 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_BITS 1 29454 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_SHIFT 12 29455 29456 /* Dsc2b0 :: dsc_ana_ctrl2 :: m1_odd_ctrl [11:06] */ 29457 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_MASK 0x0fc0 29458 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_ALIGN 0 29459 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_BITS 6 29460 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_SHIFT 6 29461 29462 /* Dsc2b0 :: dsc_ana_ctrl2 :: m1_evn_ctrl [05:00] */ 29463 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_MASK 0x003f 29464 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_ALIGN 0 29465 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_BITS 6 29466 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_SHIFT 0 29467 29468 29469 /**************************************************************************** 29470 * Dsc2b0 :: dsc_ana_ctrl3 29471 */ 29472 /* Dsc2b0 :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:10] */ 29473 #define DSC2B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK 0xfc00 29474 #define DSC2B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 29475 #define DSC2B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS 6 29476 #define DSC2B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT 10 29477 29478 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_pf_hiz [09:09] */ 29479 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_MASK 0x0200 29480 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_ALIGN 0 29481 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_BITS 1 29482 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_SHIFT 9 29483 29484 /* Dsc2b0 :: dsc_ana_ctrl3 :: force_rx_m1_thresh_zero [08:08] */ 29485 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_MASK 0x0100 29486 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_ALIGN 0 29487 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_BITS 1 29488 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_SHIFT 8 29489 29490 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_m1_thresh_zero [07:07] */ 29491 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_MASK 0x0080 29492 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_ALIGN 0 29493 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_BITS 1 29494 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_SHIFT 7 29495 29496 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_thresh_sel [06:05] */ 29497 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_MASK 0x0060 29498 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_ALIGN 0 29499 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_BITS 2 29500 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_SHIFT 5 29501 29502 /* Dsc2b0 :: dsc_ana_ctrl3 :: force_rx_pf_ctrl [04:04] */ 29503 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_MASK 0x0010 29504 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_ALIGN 0 29505 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_BITS 1 29506 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_SHIFT 4 29507 29508 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_pf_ctrl [03:00] */ 29509 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_MASK 0x000f 29510 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_ALIGN 0 29511 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_BITS 4 29512 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_SHIFT 0 29513 29514 29515 /**************************************************************************** 29516 * Dsc2b0 :: dsc_ana_ctrl4 29517 */ 29518 /* Dsc2b0 :: dsc_ana_ctrl4 :: reserved_for_eco0 [15:15] */ 29519 #define DSC2B0_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_MASK 0x8000 29520 #define DSC2B0_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 29521 #define DSC2B0_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_BITS 1 29522 #define DSC2B0_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_SHIFT 15 29523 29524 /* Dsc2b0 :: dsc_ana_ctrl4 :: rx_dfe_os2x_mode [14:14] */ 29525 #define DSC2B0_DSC_ANA_CTRL4_RX_DFE_OS2X_MODE_MASK 0x4000 29526 #define DSC2B0_DSC_ANA_CTRL4_RX_DFE_OS2X_MODE_ALIGN 0 29527 #define DSC2B0_DSC_ANA_CTRL4_RX_DFE_OS2X_MODE_BITS 1 29528 #define DSC2B0_DSC_ANA_CTRL4_RX_DFE_OS2X_MODE_SHIFT 14 29529 29530 29531 /* Dsc2b0 :: dsc_ana_ctrl4 :: rx_pf2_allp_ctrl [13:11] */ 29532 #define DSC2B0_DSC_ANA_CTRL4_RX_PF2_ALLP_CTRL_MASK 0x3800 29533 #define DSC2B0_DSC_ANA_CTRL4_RX_PF2_ALLP_CTRL_ALIGN 0 29534 #define DSC2B0_DSC_ANA_CTRL4_RX_PF2_ALLP_CTRL_BITS 3 29535 #define DSC2B0_DSC_ANA_CTRL4_RX_PF2_ALLP_CTRL_SHIFT 11 29536 29537 29538 /* Dsc2b0 :: dsc_ana_ctrl4 :: rx_pf2_lowp_ctrl [10:08] */ 29539 #define DSC2B0_DSC_ANA_CTRL4_RX_PF2_LOWP_CTRL_MASK 0x0700 29540 #define DSC2B0_DSC_ANA_CTRL4_RX_PF2_LOWP_CTRL_ALIGN 0 29541 #define DSC2B0_DSC_ANA_CTRL4_RX_PF2_LOWP_CTRL_BITS 3 29542 #define DSC2B0_DSC_ANA_CTRL4_RX_PF2_LOWP_CTRL_SHIFT 8 29543 29544 /* Dsc2b0 :: dsc_ana_ctrl4 :: reserved [07:04] */ 29545 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_MASK 0x00f0 29546 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_ALIGN 0 29547 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_BITS 4 29548 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_SHIFT 4 29549 29550 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_offset_pd [03:03] */ 29551 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_MASK 0x0008 29552 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_ALIGN 0 29553 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_BITS 1 29554 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_SHIFT 3 29555 29556 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_en_hgain [02:02] */ 29557 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_MASK 0x0004 29558 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_ALIGN 0 29559 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_BITS 1 29560 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_SHIFT 2 29561 29562 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_en_dfe_clk [01:01] */ 29563 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_MASK 0x0002 29564 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_ALIGN 0 29565 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_BITS 1 29566 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_SHIFT 1 29567 29568 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_pd_ch_p1 [00:00] */ 29569 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_MASK 0x0001 29570 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_ALIGN 0 29571 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_BITS 1 29572 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_SHIFT 0 29573 29574 29575 /**************************************************************************** 29576 * Dsc2b0 :: dsc_misc_ctrl0 29577 */ 29578 /* Dsc2b0 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */ 29579 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_MASK 0x8000 29580 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_ALIGN 0 29581 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_BITS 1 29582 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_SHIFT 15 29583 29584 /* Dsc2b0 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */ 29585 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK 0x4000 29586 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN 0 29587 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS 1 29588 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT 14 29589 29590 /* Dsc2b0 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */ 29591 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK 0x2000 29592 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN 0 29593 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS 1 29594 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT 13 29595 29596 /* Dsc2b0 :: dsc_misc_ctrl0 :: forceRxSeqDone_val [12:12] */ 29597 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_MASK 0x1000 29598 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_ALIGN 0 29599 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_BITS 1 29600 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_SHIFT 12 29601 29602 /* Dsc2b0 :: dsc_misc_ctrl0 :: reserved_for_eco0 [11:11] */ 29603 #define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK 0x0800 29604 #define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 29605 #define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS 1 29606 #define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 29607 29608 /* Dsc2b0 :: dsc_misc_ctrl0 :: test_bus_sel_bit4 [10:10] */ 29609 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_MASK 0x0400 29610 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_ALIGN 0 29611 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_BITS 1 29612 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_SHIFT 10 29613 29614 /* Dsc2b0 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */ 29615 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK 0x0200 29616 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN 0 29617 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS 1 29618 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT 9 29619 29620 /* Dsc2b0 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */ 29621 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK 0x0100 29622 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN 0 29623 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS 1 29624 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT 8 29625 29626 /* Dsc2b0 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */ 29627 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK 0x0080 29628 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN 0 29629 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS 1 29630 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT 7 29631 29632 /* Dsc2b0 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */ 29633 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK 0x0070 29634 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN 0 29635 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS 3 29636 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT 4 29637 29638 /* Dsc2b0 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */ 29639 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK 0x000f 29640 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN 0 29641 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS 4 29642 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT 0 29643 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_Off 0 29644 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data 1 29645 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 29646 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 29647 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 29648 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg 6 29649 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 29650 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 29651 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 29652 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 29653 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe1 12 29654 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe2 13 29655 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe3 14 29656 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe4 15 29657 29658 29659 /**************************************************************************** 29660 * Warpcore_USER_Dsc3b0 29661 */ 29662 /**************************************************************************** 29663 * Dsc3b0 :: cdr_status0 29664 */ 29665 /* Dsc3b0 :: cdr_status0 :: integ_reg [15:00] */ 29666 #define DSC3B0_CDR_STATUS0_INTEG_REG_MASK 0xffff 29667 #define DSC3B0_CDR_STATUS0_INTEG_REG_ALIGN 0 29668 #define DSC3B0_CDR_STATUS0_INTEG_REG_BITS 16 29669 #define DSC3B0_CDR_STATUS0_INTEG_REG_SHIFT 0 29670 29671 29672 /**************************************************************************** 29673 * Dsc3b0 :: cdr_status1 29674 */ 29675 /* Dsc3b0 :: cdr_status1 :: integ_reg_xfer [15:00] */ 29676 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_MASK 0xffff 29677 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_ALIGN 0 29678 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_BITS 16 29679 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_SHIFT 0 29680 29681 29682 /**************************************************************************** 29683 * Dsc3b0 :: cdr_status2 29684 */ 29685 /* Dsc3b0 :: cdr_status2 :: reserved_for_eco0 [15:11] */ 29686 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_MASK 0xf800 29687 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 29688 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_BITS 5 29689 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT 11 29690 29691 /* Dsc3b0 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */ 29692 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK 0x0400 29693 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN 0 29694 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS 1 29695 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT 10 29696 29697 /* Dsc3b0 :: cdr_status2 :: br_cdr_enabled [09:09] */ 29698 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_MASK 0x0200 29699 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_ALIGN 0 29700 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_BITS 1 29701 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_SHIFT 9 29702 29703 /* Dsc3b0 :: cdr_status2 :: oscdr_mode [08:06] */ 29704 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_MASK 0x01c0 29705 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_ALIGN 0 29706 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_BITS 3 29707 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_SHIFT 6 29708 29709 /* Dsc3b0 :: cdr_status2 :: phase_err [05:00] */ 29710 #define DSC3B0_CDR_STATUS2_PHASE_ERR_MASK 0x003f 29711 #define DSC3B0_CDR_STATUS2_PHASE_ERR_ALIGN 0 29712 #define DSC3B0_CDR_STATUS2_PHASE_ERR_BITS 6 29713 #define DSC3B0_CDR_STATUS2_PHASE_ERR_SHIFT 0 29714 29715 29716 /**************************************************************************** 29717 * Dsc3b0 :: pi_status0 29718 */ 29719 /* Dsc3b0 :: pi_status0 :: reserved_for_eco0 [15:14] */ 29720 #define DSC3B0_PI_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 29721 #define DSC3B0_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 29722 #define DSC3B0_PI_STATUS0_RESERVED_FOR_ECO0_BITS 2 29723 #define DSC3B0_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 29724 29725 /* Dsc3b0 :: pi_status0 :: clk90_phase_offset [13:07] */ 29726 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 29727 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 29728 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 29729 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 29730 29731 /* Dsc3b0 :: pi_status0 :: phase_cntr [06:00] */ 29732 #define DSC3B0_PI_STATUS0_PHASE_CNTR_MASK 0x007f 29733 #define DSC3B0_PI_STATUS0_PHASE_CNTR_ALIGN 0 29734 #define DSC3B0_PI_STATUS0_PHASE_CNTR_BITS 7 29735 #define DSC3B0_PI_STATUS0_PHASE_CNTR_SHIFT 0 29736 29737 29738 /**************************************************************************** 29739 * Dsc3b0 :: pi_status1 29740 */ 29741 /* Dsc3b0 :: pi_status1 :: phs_interp_status [15:00] */ 29742 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_MASK 0xffff 29743 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_ALIGN 0 29744 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_BITS 16 29745 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_SHIFT 0 29746 29747 29748 /**************************************************************************** 29749 * Dsc3b0 :: dfe_vga_status0 29750 */ 29751 /* Dsc3b0 :: dfe_vga_status0 :: reserved_for_eco0 [15:12] */ 29752 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK 0xf000 29753 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 29754 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS 4 29755 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT 12 29756 29757 /* Dsc3b0 :: dfe_vga_status0 :: dfe_tap_1_bin [11:06] */ 29758 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_MASK 0x0fc0 29759 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_ALIGN 0 29760 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_BITS 6 29761 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_SHIFT 6 29762 29763 /* Dsc3b0 :: dfe_vga_status0 :: vga_sum [05:00] */ 29764 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_MASK 0x003f 29765 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 29766 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_BITS 6 29767 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_SHIFT 0 29768 29769 29770 /**************************************************************************** 29771 * Dsc3b0 :: dfe_vga_status1 29772 */ 29773 /* Dsc3b0 :: dfe_vga_status1 :: reserved_for_eco0 [15:12] */ 29774 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK 0xf000 29775 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 29776 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS 4 29777 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT 12 29778 29779 /* Dsc3b0 :: dfe_vga_status1 :: dfe_tap_3_bin [11:06] */ 29780 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_MASK 0x0fc0 29781 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_ALIGN 0 29782 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_BITS 6 29783 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_SHIFT 6 29784 29785 /* Dsc3b0 :: dfe_vga_status1 :: dfe_tap_2_bin [05:00] */ 29786 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_MASK 0x003f 29787 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_ALIGN 0 29788 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_BITS 6 29789 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_SHIFT 0 29790 29791 29792 /**************************************************************************** 29793 * Dsc3b0 :: dfe_vga_status2 29794 */ 29795 /* Dsc3b0 :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */ 29796 #define DSC3B0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK 0xfc00 29797 #define DSC3B0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 29798 #define DSC3B0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS 6 29799 #define DSC3B0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT 10 29800 29801 /* Dsc3b0 :: dfe_vga_status2 :: dfe_tap_5_bin [09:05] */ 29802 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_MASK 0x03e0 29803 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_ALIGN 0 29804 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_BITS 5 29805 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_SHIFT 5 29806 29807 /* Dsc3b0 :: dfe_vga_status2 :: dfe_tap_4_bin [04:00] */ 29808 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_MASK 0x001f 29809 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_ALIGN 0 29810 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_BITS 5 29811 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_SHIFT 0 29812 29813 29814 /**************************************************************************** 29815 * Dsc3b0 :: dfe_vga_status3 29816 */ 29817 /* Dsc3b0 :: dfe_vga_status3 :: reserved_for_eco0 [15:11] */ 29818 #define DSC3B0_DFE_VGA_STATUS3_RESERVED_FOR_ECO0_MASK 0xf800 29819 #define DSC3B0_DFE_VGA_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 29820 #define DSC3B0_DFE_VGA_STATUS3_RESERVED_FOR_ECO0_BITS 5 29821 #define DSC3B0_DFE_VGA_STATUS3_RESERVED_FOR_ECO0_SHIFT 11 29822 29823 /* Dsc3b0 :: dfe_vga_status3 :: trnsum [10:00] */ 29824 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_MASK 0x07ff 29825 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_ALIGN 0 29826 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_BITS 11 29827 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_SHIFT 0 29828 29829 29830 /**************************************************************************** 29831 * Dsc3b0 :: acq_sm_status0 29832 */ 29833 /* Dsc3b0 :: acq_sm_status0 :: reserved_for_eco0 [15:09] */ 29834 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xfe00 29835 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 29836 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO0_BITS 7 29837 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 9 29838 29839 /* Dsc3b0 :: acq_sm_status0 :: dsc_state_eee_acq_2 [08:08] */ 29840 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_MASK 0x0100 29841 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_ALIGN 0 29842 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_BITS 1 29843 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_SHIFT 8 29844 29845 /* Dsc3b0 :: acq_sm_status0 :: reserved_for_eco1 [07:05] */ 29846 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO1_MASK 0x00e0 29847 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO1_ALIGN 0 29848 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO1_BITS 3 29849 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO1_SHIFT 5 29850 29851 /* Dsc3b0 :: acq_sm_status0 :: dsc_state [04:00] */ 29852 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_MASK 0x001f 29853 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_ALIGN 0 29854 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_BITS 5 29855 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_SHIFT 0 29856 29857 29858 /**************************************************************************** 29859 * Dsc3b0 :: acq_sm_status1 29860 */ 29861 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_eee_acq_cdr_phase [15:15] */ 29862 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_MASK 0x8000 29863 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_ALIGN 0 29864 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_BITS 1 29865 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_SHIFT 15 29866 29867 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_eee_quiet [14:14] */ 29868 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_MASK 0x4000 29869 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_ALIGN 0 29870 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_BITS 1 29871 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_SHIFT 14 29872 29873 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_done [13:13] */ 29874 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_MASK 0x2000 29875 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_ALIGN 0 29876 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_BITS 1 29877 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_SHIFT 13 29878 29879 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_measure [12:12] */ 29880 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_MASK 0x1000 29881 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_ALIGN 0 29882 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_BITS 1 29883 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_SHIFT 12 29884 29885 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_train_2 [11:11] */ 29886 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_MASK 0x0800 29887 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_ALIGN 0 29888 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_BITS 1 29889 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_SHIFT 11 29890 29891 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_train_1 [10:10] */ 29892 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_MASK 0x0400 29893 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_ALIGN 0 29894 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_BITS 1 29895 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_SHIFT 10 29896 29897 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_soft_ack [09:09] */ 29898 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_MASK 0x0200 29899 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_ALIGN 0 29900 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_BITS 1 29901 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_SHIFT 9 29902 29903 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_2 [08:08] */ 29904 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_MASK 0x0100 29905 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_ALIGN 0 29906 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_BITS 1 29907 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_SHIFT 8 29908 29909 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_1 [07:07] */ 29910 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_MASK 0x0080 29911 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_ALIGN 0 29912 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_BITS 1 29913 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_SHIFT 7 29914 29915 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_cdr [06:06] */ 29916 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_MASK 0x0040 29917 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_ALIGN 0 29918 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_BITS 1 29919 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_SHIFT 6 29920 29921 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_cdrbr_phase [05:05] */ 29922 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_MASK 0x0020 29923 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_ALIGN 0 29924 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_BITS 1 29925 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_SHIFT 5 29926 29927 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_os_integ_xfer [04:04] */ 29928 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_MASK 0x0010 29929 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_ALIGN 0 29930 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_BITS 1 29931 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_SHIFT 4 29932 29933 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_vga [03:03] */ 29934 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_MASK 0x0008 29935 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_ALIGN 0 29936 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_BITS 1 29937 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_SHIFT 3 29938 29939 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_setup [02:02] */ 29940 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_MASK 0x0004 29941 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_ALIGN 0 29942 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_BITS 1 29943 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_SHIFT 2 29944 29945 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_pause [01:01] */ 29946 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_MASK 0x0002 29947 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_ALIGN 0 29948 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_BITS 1 29949 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_SHIFT 1 29950 29951 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_init [00:00] */ 29952 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_MASK 0x0001 29953 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_ALIGN 0 29954 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_BITS 1 29955 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_SHIFT 0 29956 29957 29958 /**************************************************************************** 29959 * Dsc3b0 :: ana_status0 29960 */ 29961 /* Dsc3b0 :: ana_status0 :: reserved_for_eco0 [15:08] */ 29962 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_MASK 0xff00 29963 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 29964 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_BITS 8 29965 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT 8 29966 29967 /* Dsc3b0 :: ana_status0 :: pd_ch_p1 [07:07] */ 29968 #define DSC3B0_ANA_STATUS0_PD_CH_P1_MASK 0x0080 29969 #define DSC3B0_ANA_STATUS0_PD_CH_P1_ALIGN 0 29970 #define DSC3B0_ANA_STATUS0_PD_CH_P1_BITS 1 29971 #define DSC3B0_ANA_STATUS0_PD_CH_P1_SHIFT 7 29972 29973 /* Dsc3b0 :: ana_status0 :: en_dfe_clk [06:06] */ 29974 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_MASK 0x0040 29975 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_ALIGN 0 29976 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_BITS 1 29977 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_SHIFT 6 29978 29979 /* Dsc3b0 :: ana_status0 :: en_hgain [05:05] */ 29980 #define DSC3B0_ANA_STATUS0_EN_HGAIN_MASK 0x0020 29981 #define DSC3B0_ANA_STATUS0_EN_HGAIN_ALIGN 0 29982 #define DSC3B0_ANA_STATUS0_EN_HGAIN_BITS 1 29983 #define DSC3B0_ANA_STATUS0_EN_HGAIN_SHIFT 5 29984 29985 /* Dsc3b0 :: ana_status0 :: offset_pd [04:04] */ 29986 #define DSC3B0_ANA_STATUS0_OFFSET_PD_MASK 0x0010 29987 #define DSC3B0_ANA_STATUS0_OFFSET_PD_ALIGN 0 29988 #define DSC3B0_ANA_STATUS0_OFFSET_PD_BITS 1 29989 #define DSC3B0_ANA_STATUS0_OFFSET_PD_SHIFT 4 29990 29991 /* Dsc3b0 :: ana_status0 :: pf_ctrl_bin [03:00] */ 29992 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_MASK 0x000f 29993 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_ALIGN 0 29994 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_BITS 4 29995 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_SHIFT 0 29996 29997 29998 /**************************************************************************** 29999 * Dsc3b0 :: ana_status1 30000 */ 30001 /* Dsc3b0 :: ana_status1 :: reserved_for_eco0 [15:12] */ 30002 #define DSC3B0_ANA_STATUS1_RESERVED_FOR_ECO0_MASK 0xf000 30003 #define DSC3B0_ANA_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 30004 #define DSC3B0_ANA_STATUS1_RESERVED_FOR_ECO0_BITS 4 30005 #define DSC3B0_ANA_STATUS1_RESERVED_FOR_ECO0_SHIFT 12 30006 30007 /* Dsc3b0 :: ana_status1 :: slicer_offset_po [11:06] */ 30008 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_MASK 0x0fc0 30009 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_ALIGN 0 30010 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_BITS 6 30011 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_SHIFT 6 30012 30013 /* Dsc3b0 :: ana_status1 :: slicer_offset_pe [05:00] */ 30014 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_MASK 0x003f 30015 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_ALIGN 0 30016 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_BITS 6 30017 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_SHIFT 0 30018 30019 30020 /**************************************************************************** 30021 * Dsc3b0 :: ana_status2 30022 */ 30023 /* Dsc3b0 :: ana_status2 :: reserved_for_eco0 [15:12] */ 30024 #define DSC3B0_ANA_STATUS2_RESERVED_FOR_ECO0_MASK 0xf000 30025 #define DSC3B0_ANA_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 30026 #define DSC3B0_ANA_STATUS2_RESERVED_FOR_ECO0_BITS 4 30027 #define DSC3B0_ANA_STATUS2_RESERVED_FOR_ECO0_SHIFT 12 30028 30029 /* Dsc3b0 :: ana_status2 :: slicer_offset_zo [11:06] */ 30030 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_MASK 0x0fc0 30031 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_ALIGN 0 30032 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_BITS 6 30033 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_SHIFT 6 30034 30035 /* Dsc3b0 :: ana_status2 :: slicer_offset_ze [05:00] */ 30036 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_MASK 0x003f 30037 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_ALIGN 0 30038 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_BITS 6 30039 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_SHIFT 0 30040 30041 30042 /**************************************************************************** 30043 * Dsc3b0 :: ana_status3 30044 */ 30045 /* Dsc3b0 :: ana_status3 :: reserved_for_eco0 [15:12] */ 30046 #define DSC3B0_ANA_STATUS3_RESERVED_FOR_ECO0_MASK 0xf000 30047 #define DSC3B0_ANA_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 30048 #define DSC3B0_ANA_STATUS3_RESERVED_FOR_ECO0_BITS 4 30049 #define DSC3B0_ANA_STATUS3_RESERVED_FOR_ECO0_SHIFT 12 30050 30051 /* Dsc3b0 :: ana_status3 :: slicer_offset_mo [11:06] */ 30052 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_MASK 0x0fc0 30053 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_ALIGN 0 30054 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_BITS 6 30055 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_SHIFT 6 30056 30057 /* Dsc3b0 :: ana_status3 :: slicer_offset_me [05:00] */ 30058 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_MASK 0x003f 30059 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_ALIGN 0 30060 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_BITS 6 30061 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_SHIFT 0 30062 30063 30064 /**************************************************************************** 30065 * Warpcore_USER_Dsc4b0 30066 */ 30067 /**************************************************************************** 30068 * Dsc4b0 :: tuning_sm_ctrl0 30069 */ 30070 /* Dsc4b0 :: tuning_sm_ctrl0 :: reserved_for_eco0 [15:15] */ 30071 #define DSC4B0_TUNING_SM_CTRL0_RESERVED_FOR_ECO0_MASK 0x8000 30072 #define DSC4B0_TUNING_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 30073 #define DSC4B0_TUNING_SM_CTRL0_RESERVED_FOR_ECO0_BITS 1 30074 #define DSC4B0_TUNING_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT 15 30075 30076 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_tx_postc_cal [14:14] */ 30077 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK 0x4000 30078 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN 0 30079 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS 1 30080 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT 14 30081 30082 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_br_vga [13:13] */ 30083 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_MASK 0x2000 30084 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_ALIGN 0 30085 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_BITS 1 30086 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_SHIFT 13 30087 30088 /* Dsc4b0 :: tuning_sm_ctrl0 :: postc_metric_ctrl [12:12] */ 30089 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_MASK 0x1000 30090 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN 0 30091 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_BITS 1 30092 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT 12 30093 30094 /* Dsc4b0 :: tuning_sm_ctrl0 :: hysteresis_en [11:11] */ 30095 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_MASK 0x0800 30096 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_ALIGN 0 30097 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_BITS 1 30098 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_SHIFT 11 30099 30100 /* Dsc4b0 :: tuning_sm_ctrl0 :: slicer_cal_linear_srch [10:10] */ 30101 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK 0x0400 30102 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN 0 30103 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS 1 30104 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT 10 30105 30106 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_br_pf_cal [09:09] */ 30107 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_MASK 0x0200 30108 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN 0 30109 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_BITS 1 30110 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT 9 30111 30112 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */ 30113 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK 0x0100 30114 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN 0 30115 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS 1 30116 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT 8 30117 30118 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */ 30119 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK 0x0080 30120 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN 0 30121 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS 1 30122 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT 7 30123 30124 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_data_slicer_recal [06:06] */ 30125 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK 0x0040 30126 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN 0 30127 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS 1 30128 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT 6 30129 30130 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */ 30131 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK 0x0020 30132 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN 0 30133 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS 1 30134 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT 5 30135 30136 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */ 30137 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK 0x0010 30138 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN 0 30139 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS 1 30140 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT 4 30141 30142 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */ 30143 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK 0x0008 30144 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN 0 30145 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS 1 30146 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT 3 30147 30148 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */ 30149 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK 0x0004 30150 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN 0 30151 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS 1 30152 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT 2 30153 30154 /* Dsc4b0 :: tuning_sm_ctrl0 :: restart_tuning [01:01] */ 30155 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_MASK 0x0002 30156 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_ALIGN 0 30157 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_BITS 1 30158 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_SHIFT 1 30159 30160 /* Dsc4b0 :: tuning_sm_ctrl0 :: tuning_sm_en [00:00] */ 30161 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_MASK 0x0001 30162 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_ALIGN 0 30163 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_BITS 1 30164 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_SHIFT 0 30165 30166 30167 /**************************************************************************** 30168 * Dsc4b0 :: tuning_sm_ctrl1 30169 */ 30170 /* Dsc4b0 :: tuning_sm_ctrl1 :: reserved_for_eco0 [15:15] */ 30171 #define DSC4B0_TUNING_SM_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 30172 #define DSC4B0_TUNING_SM_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 30173 #define DSC4B0_TUNING_SM_CTRL1_RESERVED_FOR_ECO0_BITS 1 30174 #define DSC4B0_TUNING_SM_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 30175 30176 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_br_offset [14:12] */ 30177 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_MASK 0x7000 30178 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_ALIGN 0 30179 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_BITS 3 30180 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_SHIFT 12 30181 30182 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_osx1_offset [11:09] */ 30183 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_MASK 0x0e00 30184 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_ALIGN 0 30185 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_BITS 3 30186 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_SHIFT 9 30187 30188 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_osx2_offset [08:06] */ 30189 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_MASK 0x01c0 30190 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_ALIGN 0 30191 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_BITS 3 30192 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_SHIFT 6 30193 30194 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_br_init [05:03] */ 30195 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_MASK 0x0038 30196 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_ALIGN 0 30197 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_BITS 3 30198 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_SHIFT 3 30199 30200 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_os_init [02:00] */ 30201 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_MASK 0x0007 30202 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_ALIGN 0 30203 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_BITS 3 30204 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_SHIFT 0 30205 30206 30207 /**************************************************************************** 30208 * Dsc4b0 :: tuning_sm_ctrl2 30209 */ 30210 /* Dsc4b0 :: tuning_sm_ctrl2 :: reserved_for_eco0 [15:12] */ 30211 #define DSC4B0_TUNING_SM_CTRL2_RESERVED_FOR_ECO0_MASK 0xf000 30212 #define DSC4B0_TUNING_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 30213 #define DSC4B0_TUNING_SM_CTRL2_RESERVED_FOR_ECO0_BITS 4 30214 #define DSC4B0_TUNING_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT 12 30215 30216 /* Dsc4b0 :: tuning_sm_ctrl2 :: vga_max_val [11:06] */ 30217 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_MASK 0x0fc0 30218 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_ALIGN 0 30219 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_BITS 6 30220 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_SHIFT 6 30221 30222 /* Dsc4b0 :: tuning_sm_ctrl2 :: vga_min_val [05:00] */ 30223 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_MASK 0x003f 30224 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_ALIGN 0 30225 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_BITS 6 30226 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_SHIFT 0 30227 30228 30229 /**************************************************************************** 30230 * Dsc4b0 :: tuning_sm_ctrl3 30231 */ 30232 /* Dsc4b0 :: tuning_sm_ctrl3 :: reserved_for_eco0 [15:12] */ 30233 #define DSC4B0_TUNING_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0xf000 30234 #define DSC4B0_TUNING_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 30235 #define DSC4B0_TUNING_SM_CTRL3_RESERVED_FOR_ECO0_BITS 4 30236 #define DSC4B0_TUNING_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 12 30237 30238 /* Dsc4b0 :: tuning_sm_ctrl3 :: dfe_max_val [11:06] */ 30239 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_MASK 0x0fc0 30240 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_ALIGN 0 30241 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_BITS 6 30242 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_SHIFT 6 30243 30244 /* Dsc4b0 :: tuning_sm_ctrl3 :: dfe_min_val [05:00] */ 30245 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_MASK 0x003f 30246 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_ALIGN 0 30247 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_BITS 6 30248 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_SHIFT 0 30249 30250 30251 /**************************************************************************** 30252 * Dsc4b0 :: tuning_sm_ctrl4 30253 */ 30254 /* Dsc4b0 :: tuning_sm_ctrl4 :: reserved_for_eco0 [15:14] */ 30255 #define DSC4B0_TUNING_SM_CTRL4_RESERVED_FOR_ECO0_MASK 0xc000 30256 #define DSC4B0_TUNING_SM_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 30257 #define DSC4B0_TUNING_SM_CTRL4_RESERVED_FOR_ECO0_BITS 2 30258 #define DSC4B0_TUNING_SM_CTRL4_RESERVED_FOR_ECO0_SHIFT 14 30259 30260 /* Dsc4b0 :: tuning_sm_ctrl4 :: br_pf_tap_en [13:07] */ 30261 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_MASK 0x3f80 30262 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_ALIGN 0 30263 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_BITS 7 30264 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_SHIFT 7 30265 30266 /* Dsc4b0 :: tuning_sm_ctrl4 :: osx1_pf_tap_en [06:00] */ 30267 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_MASK 0x007f 30268 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_ALIGN 0 30269 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_BITS 7 30270 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_SHIFT 0 30271 30272 30273 /**************************************************************************** 30274 * Dsc4b0 :: tuning_sm_ctrl5 30275 */ 30276 /* Dsc4b0 :: tuning_sm_ctrl5 :: reserved_for_eco0 [15:15] */ 30277 #define DSC4B0_TUNING_SM_CTRL5_RESERVED_FOR_ECO0_MASK 0x8000 30278 #define DSC4B0_TUNING_SM_CTRL5_RESERVED_FOR_ECO0_ALIGN 0 30279 #define DSC4B0_TUNING_SM_CTRL5_RESERVED_FOR_ECO0_BITS 1 30280 #define DSC4B0_TUNING_SM_CTRL5_RESERVED_FOR_ECO0_SHIFT 15 30281 30282 /* Dsc4b0 :: tuning_sm_ctrl5 :: msr_br_vga_timeout [14:10] */ 30283 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_MASK 0x7c00 30284 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_ALIGN 0 30285 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_BITS 5 30286 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_SHIFT 10 30287 30288 /* Dsc4b0 :: tuning_sm_ctrl5 :: hysteresis_timeout [09:05] */ 30289 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_MASK 0x03e0 30290 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_ALIGN 0 30291 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_BITS 5 30292 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_SHIFT 5 30293 30294 /* Dsc4b0 :: tuning_sm_ctrl5 :: msr_postc_timeout [04:00] */ 30295 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_MASK 0x001f 30296 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_ALIGN 0 30297 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_BITS 5 30298 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_SHIFT 0 30299 30300 30301 /**************************************************************************** 30302 * Dsc4b0 :: tuning_sm_ctrl6 30303 */ 30304 /* Dsc4b0 :: tuning_sm_ctrl6 :: reserved_for_eco0 [15:14] */ 30305 #define DSC4B0_TUNING_SM_CTRL6_RESERVED_FOR_ECO0_MASK 0xc000 30306 #define DSC4B0_TUNING_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 30307 #define DSC4B0_TUNING_SM_CTRL6_RESERVED_FOR_ECO0_BITS 2 30308 #define DSC4B0_TUNING_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT 14 30309 30310 /* Dsc4b0 :: tuning_sm_ctrl6 :: br_vga_lms_gain [13:12] */ 30311 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_MASK 0x3000 30312 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_ALIGN 0 30313 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_BITS 2 30314 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_SHIFT 12 30315 30316 /* Dsc4b0 :: tuning_sm_ctrl6 :: postc_dfe_lms_gain [11:10] */ 30317 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_MASK 0x0c00 30318 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_ALIGN 0 30319 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_BITS 2 30320 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_SHIFT 10 30321 30322 /* Dsc4b0 :: tuning_sm_ctrl6 :: cdr_phase_inversion_timeout [09:05] */ 30323 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_MASK 0x03e0 30324 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_ALIGN 0 30325 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_BITS 5 30326 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_SHIFT 5 30327 30328 /* Dsc4b0 :: tuning_sm_ctrl6 :: msr_pf_timeout [04:00] */ 30329 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_MASK 0x001f 30330 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_ALIGN 0 30331 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_BITS 5 30332 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_SHIFT 0 30333 30334 30335 /**************************************************************************** 30336 * Dsc4b0 :: tuning_sm_ctrl7 30337 */ 30338 /* Dsc4b0 :: tuning_sm_ctrl7 :: reserved0 [15:15] */ 30339 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_MASK 0x8000 30340 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_ALIGN 0 30341 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_BITS 1 30342 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_SHIFT 15 30343 30344 /* Dsc4b0 :: tuning_sm_ctrl7 :: br_vga_trn2_timeout [14:10] */ 30345 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_MASK 0x7c00 30346 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_ALIGN 0 30347 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_BITS 5 30348 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_SHIFT 10 30349 30350 /* Dsc4b0 :: tuning_sm_ctrl7 :: br_pf_trn2_timeout [09:05] */ 30351 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_MASK 0x03e0 30352 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_ALIGN 0 30353 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_BITS 5 30354 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_SHIFT 5 30355 30356 /* Dsc4b0 :: tuning_sm_ctrl7 :: br_pf_trn1_timeout [04:00] */ 30357 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_MASK 0x001f 30358 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_ALIGN 0 30359 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_BITS 5 30360 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_SHIFT 0 30361 30362 30363 /**************************************************************************** 30364 * Dsc4b0 :: tuning_sm_ctrl8 30365 */ 30366 /* Dsc4b0 :: tuning_sm_ctrl8 :: reserved0 [15:14] */ 30367 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_MASK 0xc000 30368 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_ALIGN 0 30369 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_BITS 2 30370 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_SHIFT 14 30371 30372 /* Dsc4b0 :: tuning_sm_ctrl8 :: br_postc_tap_en [13:07] */ 30373 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_MASK 0x3f80 30374 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_ALIGN 0 30375 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_BITS 7 30376 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_SHIFT 7 30377 30378 /* Dsc4b0 :: tuning_sm_ctrl8 :: osx2_pf_tap_en [06:00] */ 30379 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_MASK 0x007f 30380 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_ALIGN 0 30381 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_BITS 7 30382 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_SHIFT 0 30383 30384 30385 /**************************************************************************** 30386 * Dsc4b0 :: tuning_sm_ctrl9 30387 */ 30388 /* Dsc4b0 :: tuning_sm_ctrl9 :: reserved0 [15:14] */ 30389 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_MASK 0xc000 30390 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_ALIGN 0 30391 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_BITS 2 30392 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_SHIFT 14 30393 30394 /* Dsc4b0 :: tuning_sm_ctrl9 :: osx2_postc_tap_en [13:07] */ 30395 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_MASK 0x3f80 30396 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_ALIGN 0 30397 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_BITS 7 30398 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_SHIFT 7 30399 30400 /* Dsc4b0 :: tuning_sm_ctrl9 :: osx1_postc_tap_en [06:00] */ 30401 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_MASK 0x007f 30402 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_ALIGN 0 30403 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_BITS 7 30404 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_SHIFT 0 30405 30406 30407 /**************************************************************************** 30408 * Dsc4b0 :: tuning_sm_ctrl10 30409 */ 30410 /* Dsc4b0 :: tuning_sm_ctrl10 :: reserved0 [15:15] */ 30411 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_MASK 0x8000 30412 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_ALIGN 0 30413 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_BITS 1 30414 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_SHIFT 15 30415 30416 /* Dsc4b0 :: tuning_sm_ctrl10 :: msr_slicer_slow_timeout [14:10] */ 30417 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_MASK 0x7c00 30418 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_ALIGN 0 30419 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_BITS 5 30420 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_SHIFT 10 30421 30422 /* Dsc4b0 :: tuning_sm_ctrl10 :: msr_slicer_fast_timeout [09:05] */ 30423 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_MASK 0x03e0 30424 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_ALIGN 0 30425 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_BITS 5 30426 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_SHIFT 5 30427 30428 /* Dsc4b0 :: tuning_sm_ctrl10 :: default_trn2_timeout [04:00] */ 30429 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_MASK 0x001f 30430 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_ALIGN 0 30431 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_BITS 5 30432 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_SHIFT 0 30433 30434 30435 /**************************************************************************** 30436 * Dsc4b0 :: tuning_sm_ctrl11 30437 */ 30438 /* Dsc4b0 :: tuning_sm_ctrl11 :: phase_sat_ctrl_os8 [15:14] */ 30439 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS8_MASK 0xc000 30440 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS8_ALIGN 0 30441 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS8_BITS 2 30442 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS8_SHIFT 14 30443 30444 /* Dsc4b0 :: tuning_sm_ctrl11 :: phase_sat_ctrl_os4 [13:12] */ 30445 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS4_MASK 0x3000 30446 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS4_ALIGN 0 30447 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS4_BITS 2 30448 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS4_SHIFT 12 30449 30450 /* Dsc4b0 :: tuning_sm_ctrl11 :: phase_sat_ctrl_os3 [11:10] */ 30451 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS3_MASK 0x0c00 30452 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS3_ALIGN 0 30453 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS3_BITS 2 30454 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS3_SHIFT 10 30455 30456 /* Dsc4b0 :: tuning_sm_ctrl11 :: phase_sat_ctrl_os2 [09:08] */ 30457 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS2_MASK 0x0300 30458 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS2_ALIGN 0 30459 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS2_BITS 2 30460 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS2_SHIFT 8 30461 30462 /* Dsc4b0 :: tuning_sm_ctrl11 :: pf_fine_en [07:07] */ 30463 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_MASK 0x0080 30464 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_ALIGN 0 30465 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_BITS 1 30466 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_SHIFT 7 30467 30468 /* Dsc4b0 :: tuning_sm_ctrl11 :: reserved0 [06:06] */ 30469 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_MASK 0x0040 30470 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_ALIGN 0 30471 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_BITS 1 30472 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_SHIFT 6 30473 30474 /* Dsc4b0 :: tuning_sm_ctrl11 :: pf_max_val [05:02] */ 30475 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_MASK 0x003c 30476 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_ALIGN 0 30477 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_BITS 4 30478 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_SHIFT 2 30479 30480 /* Dsc4b0 :: tuning_sm_ctrl11 :: bypass_osx1_slicer_cal [01:01] */ 30481 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_MASK 0x0002 30482 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_ALIGN 0 30483 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_BITS 1 30484 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_SHIFT 1 30485 30486 /* Dsc4b0 :: tuning_sm_ctrl11 :: bypass_osx2_slicer_cal [00:00] */ 30487 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_MASK 0x0001 30488 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_ALIGN 0 30489 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_BITS 1 30490 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_SHIFT 0 30491 30492 30493 /**************************************************************************** 30494 * Dsc4b0 :: acq_sm_ctrl9 30495 */ 30496 /* Dsc4b0 :: acq_sm_ctrl9 :: integ_sat_sel_os8 [15:15] */ 30497 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS8_MASK 0x8000 30498 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS8_ALIGN 0 30499 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS8_BITS 1 30500 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS8_SHIFT 15 30501 30502 /* Dsc4b0 :: acq_sm_ctrl9 :: integ_sat_sel_os4 [14:14] */ 30503 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS4_MASK 0x4000 30504 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS4_ALIGN 0 30505 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS4_BITS 1 30506 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS4_SHIFT 14 30507 30508 /* Dsc4b0 :: acq_sm_ctrl9 :: reserved_for_eco0 [13:13] */ 30509 #define DSC4B0_ACQ_SM_CTRL9_RESERVED_FOR_ECO0_MASK 0x2000 30510 #define DSC4B0_ACQ_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN 0 30511 #define DSC4B0_ACQ_SM_CTRL9_RESERVED_FOR_ECO0_BITS 1 30512 #define DSC4B0_ACQ_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT 13 30513 30514 /* Dsc4b0 :: acq_sm_ctrl9 :: eee_lfsr_cnt [12:00] */ 30515 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_MASK 0x1fff 30516 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_ALIGN 0 30517 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_BITS 13 30518 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_SHIFT 0 30519 30520 30521 /**************************************************************************** 30522 * Dsc4b0 :: acq_sm_ctrl10 30523 */ 30524 /* Dsc4b0 :: acq_sm_ctrl10 :: integ_sat_sel_os3 [15:15] */ 30525 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS3_MASK 0x8000 30526 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS3_ALIGN 0 30527 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS3_BITS 1 30528 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS3_SHIFT 15 30529 30530 /* Dsc4b0 :: acq_sm_ctrl10 :: integ_sat_sel_os2 [14:14] */ 30531 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS2_MASK 0x4000 30532 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS2_ALIGN 0 30533 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS2_BITS 1 30534 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS2_SHIFT 14 30535 30536 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros8_bwsel_prop_acq12_offset [13:12] */ 30537 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_ACQ12_OFFSET_MASK 0x3000 30538 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_ACQ12_OFFSET_ALIGN 0 30539 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_ACQ12_OFFSET_BITS 2 30540 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_ACQ12_OFFSET_SHIFT 12 30541 30542 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros4_bwsel_prop_acq12_offset [11:10] */ 30543 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_ACQ12_OFFSET_MASK 0x0c00 30544 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_ACQ12_OFFSET_ALIGN 0 30545 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_ACQ12_OFFSET_BITS 2 30546 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_ACQ12_OFFSET_SHIFT 10 30547 30548 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros3_bwsel_prop_acq12_offset [09:08] */ 30549 #define DSC4B0_ACQ_SM_CTRL10_CDROS3_BWSEL_PROP_ACQ12_OFFSET_MASK 0x0300 30550 #define DSC4B0_ACQ_SM_CTRL10_CDROS3_BWSEL_PROP_ACQ12_OFFSET_ALIGN 0 30551 #define DSC4B0_ACQ_SM_CTRL10_CDROS3_BWSEL_PROP_ACQ12_OFFSET_BITS 2 30552 #define DSC4B0_ACQ_SM_CTRL10_CDROS3_BWSEL_PROP_ACQ12_OFFSET_SHIFT 8 30553 30554 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros2_bwsel_prop_acq12_offset [07:06] */ 30555 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_ACQ12_OFFSET_MASK 0x00c0 30556 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_ACQ12_OFFSET_ALIGN 0 30557 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_ACQ12_OFFSET_BITS 2 30558 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_ACQ12_OFFSET_SHIFT 6 30559 30560 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros8_bwsel_prop_offset [05:04] */ 30561 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_OFFSET_MASK 0x0030 30562 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_OFFSET_ALIGN 0 30563 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_OFFSET_BITS 2 30564 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_OFFSET_SHIFT 4 30565 30566 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros4_bwsel_prop_offset [03:02] */ 30567 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_OFFSET_MASK 0x000c 30568 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_OFFSET_ALIGN 0 30569 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_OFFSET_BITS 2 30570 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_OFFSET_SHIFT 2 30571 30572 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros2_bwsel_prop_offset [01:00] */ 30573 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_OFFSET_MASK 0x0003 30574 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_OFFSET_ALIGN 0 30575 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_OFFSET_BITS 2 30576 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_OFFSET_SHIFT 0 30577 30578 30579 /**************************************************************************** 30580 * Dsc4b0 :: acq_sm_ctrl11 30581 */ 30582 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros8_bwsel_integ_acq12_offset [15:14] */ 30583 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_ACQ12_OFFSET_MASK 0xc000 30584 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_ACQ12_OFFSET_ALIGN 0 30585 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_ACQ12_OFFSET_BITS 2 30586 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_ACQ12_OFFSET_SHIFT 14 30587 30588 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros4_bwsel_integ_acq12_offset [13:12] */ 30589 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_ACQ12_OFFSET_MASK 0x3000 30590 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_ACQ12_OFFSET_ALIGN 0 30591 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_ACQ12_OFFSET_BITS 2 30592 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_ACQ12_OFFSET_SHIFT 12 30593 30594 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros3_bwsel_integ_acq12_offset [11:10] */ 30595 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_ACQ12_OFFSET_MASK 0x0c00 30596 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_ACQ12_OFFSET_ALIGN 0 30597 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_ACQ12_OFFSET_BITS 2 30598 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_ACQ12_OFFSET_SHIFT 10 30599 30600 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros2_bwsel_integ_acq12_offset [09:08] */ 30601 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_ACQ12_OFFSET_MASK 0x0300 30602 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_ACQ12_OFFSET_ALIGN 0 30603 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_ACQ12_OFFSET_BITS 2 30604 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_ACQ12_OFFSET_SHIFT 8 30605 30606 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros8_bwsel_integ_offset [07:06] */ 30607 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_OFFSET_MASK 0x00c0 30608 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_OFFSET_ALIGN 0 30609 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_OFFSET_BITS 2 30610 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_OFFSET_SHIFT 6 30611 30612 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros4_bwsel_integ_offset [05:04] */ 30613 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_OFFSET_MASK 0x0030 30614 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_OFFSET_ALIGN 0 30615 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_OFFSET_BITS 2 30616 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_OFFSET_SHIFT 4 30617 30618 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros3_bwsel_integ_offset [03:02] */ 30619 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_OFFSET_MASK 0x000c 30620 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_OFFSET_ALIGN 0 30621 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_OFFSET_BITS 2 30622 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_OFFSET_SHIFT 2 30623 30624 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros2_bwsel_integ_offset [01:00] */ 30625 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_OFFSET_MASK 0x0003 30626 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_OFFSET_ALIGN 0 30627 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_OFFSET_BITS 2 30628 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_OFFSET_SHIFT 0 30629 30630 30631 /**************************************************************************** 30632 * Warpcore_USER_Dsc5b0 30633 */ 30634 /**************************************************************************** 30635 * Dsc5b0 :: tuning_sm_status0 30636 */ 30637 /* Dsc5b0 :: tuning_sm_status0 :: reserved_for_eco0 [15:14] */ 30638 #define DSC5B0_TUNING_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 30639 #define DSC5B0_TUNING_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 30640 #define DSC5B0_TUNING_SM_STATUS0_RESERVED_FOR_ECO0_BITS 2 30641 #define DSC5B0_TUNING_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 30642 30643 /* Dsc5b0 :: tuning_sm_status0 :: tuning_done [13:13] */ 30644 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_MASK 0x2000 30645 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_ALIGN 0 30646 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_BITS 1 30647 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_SHIFT 13 30648 30649 /* Dsc5b0 :: tuning_sm_status0 :: srch_state [12:09] */ 30650 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_MASK 0x1e00 30651 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_ALIGN 0 30652 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_BITS 4 30653 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_SHIFT 9 30654 30655 /* Dsc5b0 :: tuning_sm_status0 :: tuning_state [08:04] */ 30656 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_MASK 0x01f0 30657 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_ALIGN 0 30658 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_BITS 5 30659 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_SHIFT 4 30660 30661 /* Dsc5b0 :: tuning_sm_status0 :: dsc_state [03:00] */ 30662 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_MASK 0x000f 30663 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_ALIGN 0 30664 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_BITS 4 30665 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_SHIFT 0 30666 30667 30668 /**************************************************************************** 30669 * Dsc5b0 :: tuning_sm_status1 30670 */ 30671 /* Dsc5b0 :: tuning_sm_status1 :: reserved_for_eco0 [15:11] */ 30672 #define DSC5B0_TUNING_SM_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 30673 #define DSC5B0_TUNING_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 30674 #define DSC5B0_TUNING_SM_STATUS1_RESERVED_FOR_ECO0_BITS 5 30675 #define DSC5B0_TUNING_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 30676 30677 /* Dsc5b0 :: tuning_sm_status1 :: postc_metric [10:00] */ 30678 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_MASK 0x07ff 30679 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_ALIGN 0 30680 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_BITS 11 30681 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_SHIFT 0 30682 30683 30684 /**************************************************************************** 30685 * Dsc5b0 :: tuning_sm_status2 30686 */ 30687 /* Dsc5b0 :: tuning_sm_status2 :: reserved_for_eco0 [15:06] */ 30688 #define DSC5B0_TUNING_SM_STATUS2_RESERVED_FOR_ECO0_MASK 0xffc0 30689 #define DSC5B0_TUNING_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 30690 #define DSC5B0_TUNING_SM_STATUS2_RESERVED_FOR_ECO0_BITS 10 30691 #define DSC5B0_TUNING_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT 6 30692 30693 /* Dsc5b0 :: tuning_sm_status2 :: dfe_max [05:05] */ 30694 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_MASK 0x0020 30695 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_ALIGN 0 30696 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_BITS 1 30697 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_SHIFT 5 30698 30699 /* Dsc5b0 :: tuning_sm_status2 :: dfe_min [04:04] */ 30700 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_MASK 0x0010 30701 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_ALIGN 0 30702 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_BITS 1 30703 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_SHIFT 4 30704 30705 /* Dsc5b0 :: tuning_sm_status2 :: vga_max [03:03] */ 30706 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_MASK 0x0008 30707 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_ALIGN 0 30708 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_BITS 1 30709 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_SHIFT 3 30710 30711 /* Dsc5b0 :: tuning_sm_status2 :: vga_min [02:02] */ 30712 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_MASK 0x0004 30713 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_ALIGN 0 30714 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_BITS 1 30715 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_SHIFT 2 30716 30717 /* Dsc5b0 :: tuning_sm_status2 :: pf_max [01:01] */ 30718 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_MASK 0x0002 30719 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_ALIGN 0 30720 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_BITS 1 30721 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_SHIFT 1 30722 30723 /* Dsc5b0 :: tuning_sm_status2 :: pf_min [00:00] */ 30724 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_MASK 0x0001 30725 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_ALIGN 0 30726 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_BITS 1 30727 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_SHIFT 0 30728 30729 30730 /**************************************************************************** 30731 * Dsc5b0 :: tuning_sm_status3 30732 */ 30733 /* Dsc5b0 :: tuning_sm_status3 :: reserved_for_eco0 [15:11] */ 30734 #define DSC5B0_TUNING_SM_STATUS3_RESERVED_FOR_ECO0_MASK 0xf800 30735 #define DSC5B0_TUNING_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 30736 #define DSC5B0_TUNING_SM_STATUS3_RESERVED_FOR_ECO0_BITS 5 30737 #define DSC5B0_TUNING_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT 11 30738 30739 /* Dsc5b0 :: tuning_sm_status3 :: trnsum_br_vga [10:00] */ 30740 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_MASK 0x07ff 30741 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_ALIGN 0 30742 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_BITS 11 30743 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_SHIFT 0 30744 30745 30746 /**************************************************************************** 30747 * Dsc5b0 :: tuning_sm_status4 30748 */ 30749 /* Dsc5b0 :: tuning_sm_status4 :: reserved_for_eco0 [15:11] */ 30750 #define DSC5B0_TUNING_SM_STATUS4_RESERVED_FOR_ECO0_MASK 0xf800 30751 #define DSC5B0_TUNING_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN 0 30752 #define DSC5B0_TUNING_SM_STATUS4_RESERVED_FOR_ECO0_BITS 5 30753 #define DSC5B0_TUNING_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT 11 30754 30755 /* Dsc5b0 :: tuning_sm_status4 :: trnsum_pf [10:00] */ 30756 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_MASK 0x07ff 30757 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_ALIGN 0 30758 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_BITS 11 30759 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_SHIFT 0 30760 30761 30762 /**************************************************************************** 30763 * Dsc5b0 :: tuning_sm_status5 30764 */ 30765 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_tx_postc [15:15] */ 30766 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_MASK 0x8000 30767 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_ALIGN 0 30768 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_BITS 1 30769 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_SHIFT 15 30770 30771 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_pf [14:14] */ 30772 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_MASK 0x4000 30773 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_ALIGN 0 30774 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_BITS 1 30775 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_SHIFT 14 30776 30777 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_vga [13:13] */ 30778 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_MASK 0x2000 30779 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_ALIGN 0 30780 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_BITS 1 30781 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_SHIFT 13 30782 30783 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_po [12:12] */ 30784 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_MASK 0x1000 30785 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_ALIGN 0 30786 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_BITS 1 30787 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_SHIFT 12 30788 30789 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_pe [11:11] */ 30790 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_MASK 0x0800 30791 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_ALIGN 0 30792 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_BITS 1 30793 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_SHIFT 11 30794 30795 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_mo [10:10] */ 30796 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_MASK 0x0400 30797 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_ALIGN 0 30798 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_BITS 1 30799 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_SHIFT 10 30800 30801 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_me [09:09] */ 30802 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_MASK 0x0200 30803 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_ALIGN 0 30804 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_BITS 1 30805 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_SHIFT 9 30806 30807 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_do [08:08] */ 30808 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_MASK 0x0100 30809 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_ALIGN 0 30810 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_BITS 1 30811 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_SHIFT 8 30812 30813 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_de [07:07] */ 30814 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_MASK 0x0080 30815 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_ALIGN 0 30816 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_BITS 1 30817 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_SHIFT 7 30818 30819 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_tx_postc [06:06] */ 30820 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_MASK 0x0040 30821 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_ALIGN 0 30822 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_BITS 1 30823 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_SHIFT 6 30824 30825 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_pf [05:05] */ 30826 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_MASK 0x0020 30827 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_ALIGN 0 30828 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_BITS 1 30829 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_SHIFT 5 30830 30831 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_mo [04:04] */ 30832 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_MASK 0x0010 30833 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_ALIGN 0 30834 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_BITS 1 30835 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_SHIFT 4 30836 30837 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_me [03:03] */ 30838 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_MASK 0x0008 30839 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_ALIGN 0 30840 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_BITS 1 30841 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_SHIFT 3 30842 30843 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_do [02:02] */ 30844 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_MASK 0x0004 30845 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_ALIGN 0 30846 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_BITS 1 30847 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_SHIFT 2 30848 30849 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_de [01:01] */ 30850 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_MASK 0x0002 30851 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_ALIGN 0 30852 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_BITS 1 30853 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_SHIFT 1 30854 30855 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_wait_for_lock [00:00] */ 30856 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_MASK 0x0001 30857 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_ALIGN 0 30858 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_BITS 1 30859 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_SHIFT 0 30860 30861 30862 /**************************************************************************** 30863 * Dsc5b0 :: tuning_sm_status6 30864 */ 30865 /* Dsc5b0 :: tuning_sm_status6 :: reserved_for_eco0 [15:12] */ 30866 #define DSC5B0_TUNING_SM_STATUS6_RESERVED_FOR_ECO0_MASK 0xf000 30867 #define DSC5B0_TUNING_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN 0 30868 #define DSC5B0_TUNING_SM_STATUS6_RESERVED_FOR_ECO0_BITS 4 30869 #define DSC5B0_TUNING_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT 12 30870 30871 /* Dsc5b0 :: tuning_sm_status6 :: tuning_state_hysteresis [11:11] */ 30872 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_MASK 0x0800 30873 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_ALIGN 0 30874 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_BITS 1 30875 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_SHIFT 11 30876 30877 /* Dsc5b0 :: tuning_sm_status6 :: tuning_state_tuning_done [10:10] */ 30878 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_MASK 0x0400 30879 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_ALIGN 0 30880 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_BITS 1 30881 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_SHIFT 10 30882 30883 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_done [09:09] */ 30884 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_MASK 0x0200 30885 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_ALIGN 0 30886 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_BITS 1 30887 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_SHIFT 9 30888 30889 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait_undo_setup [08:08] */ 30890 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_MASK 0x0100 30891 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_ALIGN 0 30892 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_BITS 1 30893 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_SHIFT 8 30894 30895 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_undo_setup [07:07] */ 30896 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_MASK 0x0080 30897 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_ALIGN 0 30898 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_BITS 1 30899 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_SHIFT 7 30900 30901 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait_msr [06:06] */ 30902 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_MASK 0x0040 30903 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_ALIGN 0 30904 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_BITS 1 30905 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_SHIFT 6 30906 30907 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_set_msr [05:05] */ 30908 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_MASK 0x0020 30909 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_ALIGN 0 30910 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_BITS 1 30911 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_SHIFT 5 30912 30913 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait_trn [04:04] */ 30914 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_MASK 0x0010 30915 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_ALIGN 0 30916 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_BITS 1 30917 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_SHIFT 4 30918 30919 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_set_trn [03:03] */ 30920 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_MASK 0x0008 30921 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_ALIGN 0 30922 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_BITS 1 30923 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_SHIFT 3 30924 30925 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait [02:02] */ 30926 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MASK 0x0004 30927 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_ALIGN 0 30928 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_BITS 1 30929 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_SHIFT 2 30930 30931 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_setup [01:01] */ 30932 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_MASK 0x0002 30933 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_ALIGN 0 30934 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_BITS 1 30935 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_SHIFT 1 30936 30937 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_disable [00:00] */ 30938 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_MASK 0x0001 30939 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_ALIGN 0 30940 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_BITS 1 30941 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_SHIFT 0 30942 30943 30944 /**************************************************************************** 30945 * Warpcore_USER_Dsc6b0 30946 */ 30947 /**************************************************************************** 30948 * Dsc6b0 :: cdr_lm_ctrl_0 30949 */ 30950 /* Dsc6b0 :: cdr_lm_ctrl_0 :: reserved_for_eco0 [15:06] */ 30951 #define DSC6B0_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_MASK 0xffc0 30952 #define DSC6B0_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_ALIGN 0 30953 #define DSC6B0_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_BITS 10 30954 #define DSC6B0_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_SHIFT 6 30955 30956 /* Dsc6b0 :: cdr_lm_ctrl_0 :: force_pcs_clken [05:05] */ 30957 #define DSC6B0_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_MASK 0x0020 30958 #define DSC6B0_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_ALIGN 0 30959 #define DSC6B0_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_BITS 1 30960 #define DSC6B0_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_SHIFT 5 30961 30962 /* Dsc6b0 :: cdr_lm_ctrl_0 :: force_pcs_clken_val [04:04] */ 30963 #define DSC6B0_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_MASK 0x0010 30964 #define DSC6B0_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_ALIGN 0 30965 #define DSC6B0_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_BITS 1 30966 #define DSC6B0_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_SHIFT 4 30967 30968 /* Dsc6b0 :: cdr_lm_ctrl_0 :: cdr_lm_thr_sel [03:01] */ 30969 #define DSC6B0_CDR_LM_CTRL_0_CDR_LM_THR_SEL_MASK 0x000e 30970 #define DSC6B0_CDR_LM_CTRL_0_CDR_LM_THR_SEL_ALIGN 0 30971 #define DSC6B0_CDR_LM_CTRL_0_CDR_LM_THR_SEL_BITS 3 30972 #define DSC6B0_CDR_LM_CTRL_0_CDR_LM_THR_SEL_SHIFT 1 30973 30974 /* Dsc6b0 :: cdr_lm_ctrl_0 :: cdr_lm_en [00:00] */ 30975 #define DSC6B0_CDR_LM_CTRL_0_CDR_LM_EN_MASK 0x0001 30976 #define DSC6B0_CDR_LM_CTRL_0_CDR_LM_EN_ALIGN 0 30977 #define DSC6B0_CDR_LM_CTRL_0_CDR_LM_EN_BITS 1 30978 #define DSC6B0_CDR_LM_CTRL_0_CDR_LM_EN_SHIFT 0 30979 30980 30981 /**************************************************************************** 30982 * Warpcore_USER_CL72_UserB0 30983 */ 30984 /**************************************************************************** 30985 * CL72_UserB0 :: cl72_xmt_control_register 30986 */ 30987 /* CL72_UserB0 :: cl72_xmt_control_register :: xmt_control_page [15:00] */ 30988 #define CL72_USERB0_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_MASK 0xffff 30989 #define CL72_USERB0_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_ALIGN 0 30990 #define CL72_USERB0_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_BITS 16 30991 #define CL72_USERB0_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_SHIFT 0 30992 30993 30994 /**************************************************************************** 30995 * CL72_UserB0 :: cl72_rcvd_status_register 30996 */ 30997 /* CL72_UserB0 :: cl72_rcvd_status_register :: rcvd_status_page [15:00] */ 30998 #define CL72_USERB0_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_MASK 0xffff 30999 #define CL72_USERB0_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_ALIGN 0 31000 #define CL72_USERB0_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_BITS 16 31001 #define CL72_USERB0_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_SHIFT 0 31002 31003 31004 /**************************************************************************** 31005 * CL72_UserB0 :: cl72_tx_fir_tap_register 31006 */ 31007 /* CL72_UserB0 :: cl72_tx_fir_tap_register :: tx_fir_tap_force [15:15] */ 31008 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_MASK 0x8000 31009 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_ALIGN 0 31010 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_BITS 1 31011 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_SHIFT 15 31012 31013 /* CL72_UserB0 :: cl72_tx_fir_tap_register :: tx_fir_tap_post [14:10] */ 31014 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_MASK 0x7c00 31015 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_ALIGN 0 31016 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_BITS 5 31017 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_SHIFT 10 31018 31019 /* CL72_UserB0 :: cl72_tx_fir_tap_register :: tx_fir_tap_main [09:04] */ 31020 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_MASK 0x03f0 31021 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_ALIGN 0 31022 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_BITS 6 31023 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_SHIFT 4 31024 31025 /* CL72_UserB0 :: cl72_tx_fir_tap_register :: tx_fir_tap_pre [03:00] */ 31026 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_MASK 0x000f 31027 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_ALIGN 0 31028 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_BITS 4 31029 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_SHIFT 0 31030 31031 31032 /**************************************************************************** 31033 * CL72_UserB0 :: cl72_misc1_control 31034 */ 31035 /* CL72_UserB0 :: cl72_misc1_control :: link_control_force [15:15] */ 31036 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_MASK 0x8000 31037 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_ALIGN 0 31038 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_BITS 1 31039 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_SHIFT 15 31040 31041 /* CL72_UserB0 :: cl72_misc1_control :: link_control_forceval [14:14] */ 31042 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_MASK 0x4000 31043 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_ALIGN 0 31044 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_BITS 1 31045 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_SHIFT 14 31046 31047 /* CL72_UserB0 :: cl72_misc1_control :: tx_fir_tap_main_kx_init_val [13:08] */ 31048 #define CL72_USERB0_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_MASK 0x3f00 31049 #define CL72_USERB0_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_ALIGN 0 31050 #define CL72_USERB0_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_BITS 6 31051 #define CL72_USERB0_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_SHIFT 8 31052 31053 /* CL72_UserB0 :: cl72_misc1_control :: tap_default_muxsel_force [07:07] */ 31054 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_MASK 0x0080 31055 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_ALIGN 0 31056 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_BITS 1 31057 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_SHIFT 7 31058 31059 /* CL72_UserB0 :: cl72_misc1_control :: tap_default_muxsel_forceval [06:04] */ 31060 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_MASK 0x0070 31061 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_ALIGN 0 31062 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_BITS 3 31063 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_SHIFT 4 31064 31065 /* CL72_UserB0 :: cl72_misc1_control :: reserved0 [03:02] */ 31066 #define CL72_USERB0_CL72_MISC1_CONTROL_RESERVED0_MASK 0x000c 31067 #define CL72_USERB0_CL72_MISC1_CONTROL_RESERVED0_ALIGN 0 31068 #define CL72_USERB0_CL72_MISC1_CONTROL_RESERVED0_BITS 2 31069 #define CL72_USERB0_CL72_MISC1_CONTROL_RESERVED0_SHIFT 2 31070 31071 /* CL72_UserB0 :: cl72_misc1_control :: tr_coarse_lock [01:01] */ 31072 #define CL72_USERB0_CL72_MISC1_CONTROL_TR_COARSE_LOCK_MASK 0x0002 31073 #define CL72_USERB0_CL72_MISC1_CONTROL_TR_COARSE_LOCK_ALIGN 0 31074 #define CL72_USERB0_CL72_MISC1_CONTROL_TR_COARSE_LOCK_BITS 1 31075 #define CL72_USERB0_CL72_MISC1_CONTROL_TR_COARSE_LOCK_SHIFT 1 31076 31077 /* CL72_UserB0 :: cl72_misc1_control :: rx_trained [00:00] */ 31078 #define CL72_USERB0_CL72_MISC1_CONTROL_RX_TRAINED_MASK 0x0001 31079 #define CL72_USERB0_CL72_MISC1_CONTROL_RX_TRAINED_ALIGN 0 31080 #define CL72_USERB0_CL72_MISC1_CONTROL_RX_TRAINED_BITS 1 31081 #define CL72_USERB0_CL72_MISC1_CONTROL_RX_TRAINED_SHIFT 0 31082 31083 31084 /**************************************************************************** 31085 * CL72_UserB0 :: cl72_misc2_control 31086 */ 31087 /* CL72_UserB0 :: cl72_misc2_control :: reserved0 [15:14] */ 31088 #define CL72_USERB0_CL72_MISC2_CONTROL_RESERVED0_MASK 0xc000 31089 #define CL72_USERB0_CL72_MISC2_CONTROL_RESERVED0_ALIGN 0 31090 #define CL72_USERB0_CL72_MISC2_CONTROL_RESERVED0_BITS 2 31091 #define CL72_USERB0_CL72_MISC2_CONTROL_RESERVED0_SHIFT 14 31092 31093 /* CL72_UserB0 :: cl72_misc2_control :: rxfifo_data_swap_r20clk [13:13] */ 31094 #define CL72_USERB0_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_MASK 0x2000 31095 #define CL72_USERB0_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_ALIGN 0 31096 #define CL72_USERB0_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_BITS 1 31097 #define CL72_USERB0_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_SHIFT 13 31098 31099 /* CL72_UserB0 :: cl72_misc2_control :: txfifo_data_swap_t20clk [12:12] */ 31100 #define CL72_USERB0_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_MASK 0x1000 31101 #define CL72_USERB0_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_ALIGN 0 31102 #define CL72_USERB0_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_BITS 1 31103 #define CL72_USERB0_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_SHIFT 12 31104 31105 /* CL72_UserB0 :: cl72_misc2_control :: signal_detect_fec_sel [11:11] */ 31106 #define CL72_USERB0_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_MASK 0x0800 31107 #define CL72_USERB0_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_ALIGN 0 31108 #define CL72_USERB0_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_BITS 1 31109 #define CL72_USERB0_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_SHIFT 11 31110 31111 /* CL72_UserB0 :: cl72_misc2_control :: wait_timer_frame_inc_en [10:10] */ 31112 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_MASK 0x0400 31113 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_ALIGN 0 31114 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_BITS 1 31115 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_SHIFT 10 31116 31117 /* CL72_UserB0 :: cl72_misc2_control :: wait_timer_frame_cnt_init_sel [09:08] */ 31118 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_MASK 0x0300 31119 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_ALIGN 0 31120 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_BITS 2 31121 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_SHIFT 8 31122 31123 /* CL72_UserB0 :: cl72_misc2_control :: main_tap_adjust_force [07:07] */ 31124 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_MASK 0x0080 31125 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_ALIGN 0 31126 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_BITS 1 31127 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_SHIFT 7 31128 31129 /* CL72_UserB0 :: cl72_misc2_control :: main_tap_adjust_forceval [06:06] */ 31130 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_MASK 0x0040 31131 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_ALIGN 0 31132 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_BITS 1 31133 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_SHIFT 6 31134 31135 /* CL72_UserB0 :: cl72_misc2_control :: main_tap_adjust_en [05:05] */ 31136 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_MASK 0x0020 31137 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_ALIGN 0 31138 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_BITS 1 31139 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_SHIFT 5 31140 31141 /* CL72_UserB0 :: cl72_misc2_control :: newpg_rcvd_override [04:04] */ 31142 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_MASK 0x0010 31143 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_ALIGN 0 31144 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_BITS 1 31145 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_SHIFT 4 31146 31147 /* CL72_UserB0 :: cl72_misc2_control :: newpg_rcvd_load [03:03] */ 31148 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_MASK 0x0008 31149 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_ALIGN 0 31150 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_BITS 1 31151 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_SHIFT 3 31152 31153 /* CL72_UserB0 :: cl72_misc2_control :: inc_dec_val_sel [02:02] */ 31154 #define CL72_USERB0_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_MASK 0x0004 31155 #define CL72_USERB0_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_ALIGN 0 31156 #define CL72_USERB0_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_BITS 1 31157 #define CL72_USERB0_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_SHIFT 2 31158 31159 /* CL72_UserB0 :: cl72_misc2_control :: dis_max_wait_timer_force [01:01] */ 31160 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_MASK 0x0002 31161 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_ALIGN 0 31162 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_BITS 1 31163 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_SHIFT 1 31164 31165 /* CL72_UserB0 :: cl72_misc2_control :: dis_max_wait_timer_forceval [00:00] */ 31166 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_MASK 0x0001 31167 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_ALIGN 0 31168 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_BITS 1 31169 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_SHIFT 0 31170 31171 31172 /**************************************************************************** 31173 * CL72_UserB0 :: cl72_kr_default_control 31174 */ 31175 /* CL72_UserB0 :: cl72_kr_default_control :: reserved0 [15:15] */ 31176 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 31177 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_RESERVED0_ALIGN 0 31178 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_RESERVED0_BITS 1 31179 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_RESERVED0_SHIFT 15 31180 31181 /* CL72_UserB0 :: cl72_kr_default_control :: tx_fir_tap_post_kr_init_val [14:10] */ 31182 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_MASK 0x7c00 31183 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_ALIGN 0 31184 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_BITS 5 31185 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_SHIFT 10 31186 31187 /* CL72_UserB0 :: cl72_kr_default_control :: tx_fir_tap_main_kr_init_val [09:04] */ 31188 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_MASK 0x03f0 31189 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_ALIGN 0 31190 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_BITS 6 31191 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_SHIFT 4 31192 31193 /* CL72_UserB0 :: cl72_kr_default_control :: tx_fir_tap_pre_kr_init_val [03:00] */ 31194 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_MASK 0x000f 31195 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_ALIGN 0 31196 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_BITS 4 31197 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_SHIFT 0 31198 31199 31200 /**************************************************************************** 31201 * CL72_UserB0 :: cl72_os_default_control 31202 */ 31203 /* CL72_UserB0 :: cl72_os_default_control :: reserved0 [15:15] */ 31204 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 31205 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_RESERVED0_ALIGN 0 31206 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_RESERVED0_BITS 1 31207 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_RESERVED0_SHIFT 15 31208 31209 /* CL72_UserB0 :: cl72_os_default_control :: tx_fir_tap_post_os_init_val [14:10] */ 31210 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_MASK 0x7c00 31211 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_ALIGN 0 31212 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_BITS 5 31213 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_SHIFT 10 31214 31215 /* CL72_UserB0 :: cl72_os_default_control :: tx_fir_tap_main_os_init_val [09:04] */ 31216 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_MASK 0x03f0 31217 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_ALIGN 0 31218 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_BITS 6 31219 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_SHIFT 4 31220 31221 /* CL72_UserB0 :: cl72_os_default_control :: tx_fir_tap_pre_os_init_val [03:00] */ 31222 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_MASK 0x000f 31223 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_ALIGN 0 31224 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_BITS 4 31225 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_SHIFT 0 31226 31227 31228 /**************************************************************************** 31229 * CL72_UserB0 :: cl72_br_default_control 31230 */ 31231 /* CL72_UserB0 :: cl72_br_default_control :: reserved0 [15:15] */ 31232 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 31233 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_RESERVED0_ALIGN 0 31234 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_RESERVED0_BITS 1 31235 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_RESERVED0_SHIFT 15 31236 31237 /* CL72_UserB0 :: cl72_br_default_control :: tx_fir_tap_post_br_init_val [14:10] */ 31238 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_MASK 0x7c00 31239 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_ALIGN 0 31240 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_BITS 5 31241 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_SHIFT 10 31242 31243 /* CL72_UserB0 :: cl72_br_default_control :: tx_fir_tap_main_br_init_val [09:04] */ 31244 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_MASK 0x03f0 31245 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_ALIGN 0 31246 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_BITS 6 31247 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_SHIFT 4 31248 31249 /* CL72_UserB0 :: cl72_br_default_control :: tx_fir_tap_pre_br_init_val [03:00] */ 31250 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_MASK 0x000f 31251 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_ALIGN 0 31252 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_BITS 4 31253 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_SHIFT 0 31254 31255 31256 /**************************************************************************** 31257 * CL72_UserB0 :: cl72_2p5_default_control 31258 */ 31259 /* CL72_UserB0 :: cl72_2p5_default_control :: reserved0 [15:15] */ 31260 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 31261 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_RESERVED0_ALIGN 0 31262 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_RESERVED0_BITS 1 31263 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_RESERVED0_SHIFT 15 31264 31265 /* CL72_UserB0 :: cl72_2p5_default_control :: tx_fir_tap_post_2p5_init_val [14:10] */ 31266 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_MASK 0x7c00 31267 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_ALIGN 0 31268 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_BITS 5 31269 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_SHIFT 10 31270 31271 /* CL72_UserB0 :: cl72_2p5_default_control :: tx_fir_tap_main_2p5_init_val [09:04] */ 31272 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_MASK 0x03f0 31273 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_ALIGN 0 31274 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_BITS 6 31275 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_SHIFT 4 31276 31277 /* CL72_UserB0 :: cl72_2p5_default_control :: tx_fir_tap_pre_2p5_init_val [03:00] */ 31278 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_MASK 0x000f 31279 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_ALIGN 0 31280 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_BITS 4 31281 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_SHIFT 0 31282 31283 31284 /**************************************************************************** 31285 * CL72_UserB0 :: cl72_tap_limit_control 31286 */ 31287 /* CL72_UserB0 :: cl72_tap_limit_control :: reserved0 [15:15] */ 31288 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_RESERVED0_MASK 0x8000 31289 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_RESERVED0_ALIGN 0 31290 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_RESERVED0_BITS 1 31291 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_RESERVED0_SHIFT 15 31292 31293 /* CL72_UserB0 :: cl72_tap_limit_control :: post_tap_limit [14:10] */ 31294 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_MASK 0x7c00 31295 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_ALIGN 0 31296 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_BITS 5 31297 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_SHIFT 10 31298 31299 /* CL72_UserB0 :: cl72_tap_limit_control :: main_tap_limit [09:04] */ 31300 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_MASK 0x03f0 31301 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_ALIGN 0 31302 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_BITS 6 31303 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_SHIFT 4 31304 31305 /* CL72_UserB0 :: cl72_tap_limit_control :: pre_tap_limit [03:00] */ 31306 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_MASK 0x000f 31307 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_ALIGN 0 31308 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_BITS 4 31309 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_SHIFT 0 31310 31311 31312 /**************************************************************************** 31313 * CL72_UserB0 :: cl72_misc3_control 31314 */ 31315 /* CL72_UserB0 :: cl72_misc3_control :: cl72_en_mask [15:00] */ 31316 #define CL72_USERB0_CL72_MISC3_CONTROL_CL72_EN_MASK_MASK 0xffff 31317 #define CL72_USERB0_CL72_MISC3_CONTROL_CL72_EN_MASK_ALIGN 0 31318 #define CL72_USERB0_CL72_MISC3_CONTROL_CL72_EN_MASK_BITS 16 31319 #define CL72_USERB0_CL72_MISC3_CONTROL_CL72_EN_MASK_SHIFT 0 31320 31321 31322 /**************************************************************************** 31323 * CL72_UserB0 :: cl72_tap_preset_control 31324 */ 31325 /* CL72_UserB0 :: cl72_tap_preset_control :: reserved0 [15:09] */ 31326 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_RESERVED0_MASK 0xfe00 31327 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_RESERVED0_ALIGN 0 31328 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_RESERVED0_BITS 7 31329 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_RESERVED0_SHIFT 9 31330 31331 /* CL72_UserB0 :: cl72_tap_preset_control :: pre_init_val [08:05] */ 31332 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_MASK 0x01e0 31333 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_ALIGN 0 31334 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_BITS 4 31335 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_SHIFT 5 31336 31337 /* CL72_UserB0 :: cl72_tap_preset_control :: post_init_val [04:00] */ 31338 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_MASK 0x001f 31339 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_ALIGN 0 31340 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_BITS 5 31341 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_SHIFT 0 31342 31343 31344 /**************************************************************************** 31345 * CL72_UserB0 :: cl72_misc4_control 31346 */ 31347 /* CL72_UserB0 :: cl72_misc4_control :: reserved0 [15:12] */ 31348 #define CL72_USERB0_CL72_MISC4_CONTROL_RESERVED0_MASK 0xf000 31349 #define CL72_USERB0_CL72_MISC4_CONTROL_RESERVED0_ALIGN 0 31350 #define CL72_USERB0_CL72_MISC4_CONTROL_RESERVED0_BITS 4 31351 #define CL72_USERB0_CL72_MISC4_CONTROL_RESERVED0_SHIFT 12 31352 31353 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk_20_mode_sel [11:10] */ 31354 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_MASK 0x0c00 31355 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_ALIGN 0 31356 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_BITS 2 31357 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_SHIFT 10 31358 31359 /* hand added */ 31360 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_20_LEGACY_MODE 0 31361 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_20_SINGLE_MODE 1 31362 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_20_DUAL_MODE 2 31363 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_20_QUAD_MODE 3 31364 31365 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk16_ckgate_off [09:09] */ 31366 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_MASK 0x0200 31367 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_ALIGN 0 31368 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_BITS 1 31369 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_SHIFT 9 31370 31371 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk16_legacy_clkmode [08:08] */ 31372 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_MASK 0x0100 31373 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_ALIGN 0 31374 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_BITS 1 31375 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_SHIFT 8 31376 31377 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk16_wclk20_per_lane [07:07] */ 31378 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_MASK 0x0080 31379 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_ALIGN 0 31380 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_BITS 1 31381 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_SHIFT 7 31382 31383 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk_16_mode_sel [06:05] */ 31384 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_MASK 0x0060 31385 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_ALIGN 0 31386 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_BITS 2 31387 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_SHIFT 5 31388 31389 /* hand added */ 31390 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_LEGACY_MODE 0 31391 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_SINGLE_MODE 1 31392 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_DUAL_MODE 2 31393 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_QUAD_MODE 3 31394 31395 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk33_mode_sel [04:03] */ 31396 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_MASK 0x0018 31397 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_ALIGN 0 31398 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_BITS 2 31399 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_SHIFT 3 31400 31401 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_LEGACY_MODE 0 31402 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_SINGLE_MODE 1 31403 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_DUAL_MODE 2 31404 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_QUAD_MODE 3 31405 31406 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk_cl72_rst_sw [02:02] */ 31407 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_MASK 0x0004 31408 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_ALIGN 0 31409 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_BITS 1 31410 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_SHIFT 2 31411 31412 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk_cl72_ckgate_sw [01:01] */ 31413 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_MASK 0x0002 31414 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_ALIGN 0 31415 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_BITS 1 31416 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_SHIFT 1 31417 31418 /* CL72_UserB0 :: cl72_misc4_control :: cl72_en_mask [00:00] */ 31419 #define CL72_USERB0_CL72_MISC4_CONTROL_CL72_EN_MASK_MASK 0x0001 31420 #define CL72_USERB0_CL72_MISC4_CONTROL_CL72_EN_MASK_ALIGN 0 31421 #define CL72_USERB0_CL72_MISC4_CONTROL_CL72_EN_MASK_BITS 1 31422 #define CL72_USERB0_CL72_MISC4_CONTROL_CL72_EN_MASK_SHIFT 0 31423 31424 31425 /**************************************************************************** 31426 * Warpcore_USER_CL72_UserB1 31427 */ 31428 /**************************************************************************** 31429 * CL72_UserB1 :: cl72_fault_register 31430 */ 31431 /* CL72_UserB1 :: cl72_fault_register :: reserved0 [15:04] */ 31432 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED0_MASK 0xfff0 31433 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED0_ALIGN 0 31434 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED0_BITS 12 31435 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED0_SHIFT 4 31436 31437 /* CL72_UserB1 :: cl72_fault_register :: frame_lock [03:03] */ 31438 #define CL72_USERB1_CL72_FAULT_REGISTER_FRAME_LOCK_MASK 0x0008 31439 #define CL72_USERB1_CL72_FAULT_REGISTER_FRAME_LOCK_ALIGN 0 31440 #define CL72_USERB1_CL72_FAULT_REGISTER_FRAME_LOCK_BITS 1 31441 #define CL72_USERB1_CL72_FAULT_REGISTER_FRAME_LOCK_SHIFT 3 31442 31443 /* CL72_UserB1 :: cl72_fault_register :: reserved1 [02:00] */ 31444 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED1_MASK 0x0007 31445 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED1_ALIGN 0 31446 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED1_BITS 3 31447 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED1_SHIFT 0 31448 31449 31450 /**************************************************************************** 31451 * CL72_UserB1 :: cl72_debug_1_register 31452 */ 31453 /* CL72_UserB1 :: cl72_debug_1_register :: reserved0 [15:12] */ 31454 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_RESERVED0_MASK 0xf000 31455 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_RESERVED0_ALIGN 0 31456 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_RESERVED0_BITS 4 31457 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_RESERVED0_SHIFT 12 31458 31459 /* CL72_UserB1 :: cl72_debug_1_register :: tap_max_val [11:06] */ 31460 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_MASK 0x0fc0 31461 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_ALIGN 0 31462 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_BITS 6 31463 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_SHIFT 6 31464 31465 /* CL72_UserB1 :: cl72_debug_1_register :: tap_min_val [05:00] */ 31466 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_MASK 0x003f 31467 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_ALIGN 0 31468 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_BITS 6 31469 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_SHIFT 0 31470 31471 31472 /**************************************************************************** 31473 * CL72_UserB1 :: cl72_debug_2_register 31474 */ 31475 /* CL72_UserB1 :: cl72_debug_2_register :: pmd_data_swap [15:15] */ 31476 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_MASK 0x8000 31477 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_ALIGN 0 31478 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_BITS 1 31479 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_SHIFT 15 31480 31481 /* CL72_UserB1 :: cl72_debug_2_register :: brk_ring_osc_ [14:14] */ 31482 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC__MASK 0x4000 31483 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC__ALIGN 0 31484 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC__BITS 1 31485 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC__SHIFT 14 31486 31487 /* CL72_UserB1 :: cl72_debug_2_register :: strict_marker_chk [13:13] */ 31488 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_MASK 0x2000 31489 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_ALIGN 0 31490 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_BITS 1 31491 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_SHIFT 13 31492 31493 /* CL72_UserB1 :: cl72_debug_2_register :: strict_dme_chk [12:12] */ 31494 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_MASK 0x1000 31495 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_ALIGN 0 31496 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_BITS 1 31497 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_SHIFT 12 31498 31499 /* CL72_UserB1 :: cl72_debug_2_register :: dis_max_wait_timer [11:11] */ 31500 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_MASK 0x0800 31501 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_ALIGN 0 31502 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_BITS 1 31503 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_SHIFT 11 31504 31505 /* CL72_UserB1 :: cl72_debug_2_register :: max_wait_timer_val [10:09] */ 31506 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_MASK 0x0600 31507 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_ALIGN 0 31508 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_BITS 2 31509 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_SHIFT 9 31510 31511 /* CL72_UserB1 :: cl72_debug_2_register :: signal_det_force [08:08] */ 31512 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_MASK 0x0100 31513 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_ALIGN 0 31514 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_BITS 1 31515 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_SHIFT 8 31516 31517 /* CL72_UserB1 :: cl72_debug_2_register :: tr_coarse_lock_force [07:07] */ 31518 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_MASK 0x0080 31519 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_ALIGN 0 31520 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_BITS 1 31521 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_SHIFT 7 31522 31523 /* CL72_UserB1 :: cl72_debug_2_register :: clk_gate_force_ [06:06] */ 31524 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__MASK 0x0040 31525 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__ALIGN 0 31526 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__BITS 1 31527 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__SHIFT 6 31528 31529 /* CL72_UserB1 :: cl72_debug_2_register :: clk_gate_forceval [05:05] */ 31530 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_MASK 0x0020 31531 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_ALIGN 0 31532 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_BITS 1 31533 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_SHIFT 5 31534 31535 /* CL72_UserB1 :: cl72_debug_2_register :: bad_marker_cnt [04:02] */ 31536 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_MASK 0x001c 31537 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_ALIGN 0 31538 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_BITS 3 31539 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_SHIFT 2 31540 31541 /* CL72_UserB1 :: cl72_debug_2_register :: good_marker_cnt [01:00] */ 31542 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_MASK 0x0003 31543 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_ALIGN 0 31544 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_BITS 2 31545 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_SHIFT 0 31546 31547 31548 /**************************************************************************** 31549 * CL72_UserB1 :: cl72_debug_3_register 31550 */ 31551 /* CL72_UserB1 :: cl72_debug_3_register :: signal_ok_force [15:15] */ 31552 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_MASK 0x8000 31553 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_ALIGN 0 31554 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_BITS 1 31555 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_SHIFT 15 31556 31557 /* CL72_UserB1 :: cl72_debug_3_register :: ctrl_frame_dly [14:11] */ 31558 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_MASK 0x7800 31559 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_ALIGN 0 31560 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_BITS 4 31561 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_SHIFT 11 31562 31563 /* CL72_UserB1 :: cl72_debug_3_register :: random_seed [10:00] */ 31564 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_MASK 0x07ff 31565 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_ALIGN 0 31566 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_BITS 11 31567 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_SHIFT 0 31568 31569 31570 /**************************************************************************** 31571 * CL72_UserB1 :: cl72_debug_4_register 31572 */ 31573 /* CL72_UserB1 :: cl72_debug_4_register :: reserved0 [15:14] */ 31574 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_RESERVED0_MASK 0xc000 31575 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_RESERVED0_ALIGN 0 31576 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_RESERVED0_BITS 2 31577 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_RESERVED0_SHIFT 14 31578 31579 /* CL72_UserB1 :: cl72_debug_4_register :: brcm_mode_force [13:13] */ 31580 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_MASK 0x2000 31581 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_ALIGN 0 31582 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_BITS 1 31583 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_SHIFT 13 31584 31585 /* CL72_UserB1 :: cl72_debug_4_register :: brcm_mode_forceval [12:12] */ 31586 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_MASK 0x1000 31587 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_ALIGN 0 31588 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_BITS 1 31589 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_SHIFT 12 31590 31591 /* CL72_UserB1 :: cl72_debug_4_register :: v2_constraint_dis [11:11] */ 31592 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_MASK 0x0800 31593 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_ALIGN 0 31594 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_BITS 1 31595 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_SHIFT 11 31596 31597 /* CL72_UserB1 :: cl72_debug_4_register :: tap_v2_val [10:06] */ 31598 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_MASK 0x07c0 31599 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_ALIGN 0 31600 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_BITS 5 31601 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_SHIFT 6 31602 31603 /* CL72_UserB1 :: cl72_debug_4_register :: micro_reg_reset [05:05] */ 31604 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_MASK 0x0020 31605 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_ALIGN 0 31606 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_BITS 1 31607 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_SHIFT 5 31608 31609 /* CL72_UserB1 :: cl72_debug_4_register :: sigdet_forceval [04:04] */ 31610 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_MASK 0x0010 31611 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_ALIGN 0 31612 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_BITS 1 31613 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_SHIFT 4 31614 31615 /* CL72_UserB1 :: cl72_debug_4_register :: sigdet_force [03:03] */ 31616 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_MASK 0x0008 31617 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_ALIGN 0 31618 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_BITS 1 31619 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_SHIFT 3 31620 31621 /* CL72_UserB1 :: cl72_debug_4_register :: trnpat_en_forceval [02:02] */ 31622 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_MASK 0x0004 31623 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_ALIGN 0 31624 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_BITS 1 31625 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_SHIFT 2 31626 31627 /* CL72_UserB1 :: cl72_debug_4_register :: trnpat_en_force [01:01] */ 31628 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_MASK 0x0002 31629 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_ALIGN 0 31630 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_BITS 1 31631 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_SHIFT 1 31632 31633 /* CL72_UserB1 :: cl72_debug_4_register :: ppm_offset_en [00:00] */ 31634 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_MASK 0x0001 31635 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_ALIGN 0 31636 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_BITS 1 31637 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_SHIFT 0 31638 31639 31640 /**************************************************************************** 31641 * Warpcore_USER_SerdesDigital 31642 */ 31643 /**************************************************************************** 31644 * SerdesDigital :: Control1000X1 31645 */ 31646 /* SerdesDigital :: Control1000X1 :: reserved0 [15:15] */ 31647 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_MASK 0x8000 31648 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_ALIGN 0 31649 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_BITS 1 31650 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_SHIFT 15 31651 31652 /* SerdesDigital :: Control1000X1 :: disable_signal_detect_filter [14:14] */ 31653 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK 0x4000 31654 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN 0 31655 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS 1 31656 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT 14 31657 31658 /* SerdesDigital :: Control1000X1 :: reserved1 [13:12] */ 31659 #define SERDESDIGITAL_CONTROL1000X1_RESERVED1_MASK 0x3000 31660 #define SERDESDIGITAL_CONTROL1000X1_RESERVED1_ALIGN 0 31661 #define SERDESDIGITAL_CONTROL1000X1_RESERVED1_BITS 2 31662 #define SERDESDIGITAL_CONTROL1000X1_RESERVED1_SHIFT 12 31663 31664 /* SerdesDigital :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */ 31665 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK 0x0800 31666 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN 0 31667 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS 1 31668 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT 11 31669 31670 /* SerdesDigital :: Control1000X1 :: remote_loopback [10:10] */ 31671 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_MASK 0x0400 31672 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN 0 31673 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_BITS 1 31674 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT 10 31675 31676 /* SerdesDigital :: Control1000X1 :: zero_comma_detector_phase [09:09] */ 31677 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200 31678 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0 31679 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1 31680 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9 31681 31682 /* SerdesDigital :: Control1000X1 :: comma_det_en [08:08] */ 31683 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_MASK 0x0100 31684 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_ALIGN 0 31685 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_BITS 1 31686 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_SHIFT 8 31687 31688 /* SerdesDigital :: Control1000X1 :: crc_checker_disable [07:07] */ 31689 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK 0x0080 31690 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN 0 31691 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS 1 31692 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT 7 31693 31694 /* SerdesDigital :: Control1000X1 :: disable_pll_pwrdwn [06:06] */ 31695 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK 0x0040 31696 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN 0 31697 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS 1 31698 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT 6 31699 31700 /* SerdesDigital :: Control1000X1 :: sgmii_master_mode [05:05] */ 31701 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_MASK 0x0020 31702 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN 0 31703 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_BITS 1 31704 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT 5 31705 31706 /* SerdesDigital :: Control1000X1 :: autodet_en [04:04] */ 31707 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_MASK 0x0010 31708 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_ALIGN 0 31709 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_BITS 1 31710 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_SHIFT 4 31711 31712 /* SerdesDigital :: Control1000X1 :: invert_signal_detect [03:03] */ 31713 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK 0x0008 31714 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN 0 31715 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS 1 31716 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT 3 31717 31718 /* SerdesDigital :: Control1000X1 :: signal_detect_en [02:02] */ 31719 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_MASK 0x0004 31720 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN 0 31721 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_BITS 1 31722 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT 2 31723 31724 /* SerdesDigital :: Control1000X1 :: tbi_interface [01:01] */ 31725 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_MASK 0x0002 31726 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_ALIGN 0 31727 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_BITS 1 31728 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_SHIFT 1 31729 31730 /* SerdesDigital :: Control1000X1 :: fiber_mode_1000X [00:00] */ 31731 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_MASK 0x0001 31732 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_ALIGN 0 31733 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_BITS 1 31734 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_SHIFT 0 31735 31736 31737 /**************************************************************************** 31738 * SerdesDigital :: Control1000X2 31739 */ 31740 /* SerdesDigital :: Control1000X2 :: disable_extend_fdx_only [15:15] */ 31741 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK 0x8000 31742 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN 0 31743 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS 1 31744 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT 15 31745 31746 /* SerdesDigital :: Control1000X2 :: clear_ber_counter [14:14] */ 31747 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_MASK 0x4000 31748 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN 0 31749 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_BITS 1 31750 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT 14 31751 31752 /* SerdesDigital :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */ 31753 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK 0x2000 31754 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN 0 31755 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS 1 31756 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT 13 31757 31758 /* SerdesDigital :: Control1000X2 :: transmit_packet_seq_test [12:12] */ 31759 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK 0x1000 31760 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN 0 31761 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS 1 31762 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT 12 31763 31764 /* SerdesDigital :: Control1000X2 :: test_cntr [11:11] */ 31765 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_MASK 0x0800 31766 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_ALIGN 0 31767 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_BITS 1 31768 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_SHIFT 11 31769 31770 /* SerdesDigital :: Control1000X2 :: bypass_pcs_tx [10:10] */ 31771 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_MASK 0x0400 31772 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_ALIGN 0 31773 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_BITS 1 31774 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_SHIFT 10 31775 31776 /* SerdesDigital :: Control1000X2 :: bypass_pcs_rx [09:09] */ 31777 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_MASK 0x0200 31778 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_ALIGN 0 31779 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_BITS 1 31780 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_SHIFT 9 31781 31782 /* SerdesDigital :: Control1000X2 :: disable_TRRR_generation [08:08] */ 31783 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK 0x0100 31784 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN 0 31785 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS 1 31786 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT 8 31787 31788 /* SerdesDigital :: Control1000X2 :: disable_carrier_extend [07:07] */ 31789 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK 0x0080 31790 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN 0 31791 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS 1 31792 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT 7 31793 31794 /* SerdesDigital :: Control1000X2 :: autoneg_fast_timers [06:06] */ 31795 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK 0x0040 31796 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN 0 31797 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS 1 31798 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT 6 31799 31800 /* SerdesDigital :: Control1000X2 :: force_xmit_data_on_txside [05:05] */ 31801 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK 0x0020 31802 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN 0 31803 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS 1 31804 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT 5 31805 31806 /* SerdesDigital :: Control1000X2 :: disable_remote_fault_sensing [04:04] */ 31807 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK 0x0010 31808 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN 0 31809 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS 1 31810 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT 4 31811 31812 /* SerdesDigital :: Control1000X2 :: enable_autoneg_err_timer [03:03] */ 31813 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK 0x0008 31814 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0 31815 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS 1 31816 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3 31817 31818 /* SerdesDigital :: Control1000X2 :: filter_force_link [02:02] */ 31819 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_MASK 0x0004 31820 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN 0 31821 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_BITS 1 31822 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT 2 31823 31824 /* SerdesDigital :: Control1000X2 :: disable_false_link [01:01] */ 31825 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_MASK 0x0002 31826 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN 0 31827 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_BITS 1 31828 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT 1 31829 31830 /* SerdesDigital :: Control1000X2 :: enable_parallel_detection [00:00] */ 31831 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_MASK 0x0001 31832 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_ALIGN 0 31833 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_BITS 1 31834 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_SHIFT 0 31835 31836 31837 /**************************************************************************** 31838 * SerdesDigital :: Control1000X3 31839 */ 31840 /* SerdesDigital :: Control1000X3 :: disable_packet_misalign [15:15] */ 31841 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK 0x8000 31842 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN 0 31843 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS 1 31844 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT 15 31845 31846 /* SerdesDigital :: Control1000X3 :: rxfifo_gmii_reset [14:14] */ 31847 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_MASK 0x4000 31848 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN 0 31849 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_BITS 1 31850 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT 14 31851 31852 /* SerdesDigital :: Control1000X3 :: disable_tx_crs [13:13] */ 31853 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_MASK 0x2000 31854 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_ALIGN 0 31855 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_BITS 1 31856 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_SHIFT 13 31857 31858 /* SerdesDigital :: Control1000X3 :: invert_ext_phy_crs [12:12] */ 31859 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK 0x1000 31860 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN 0 31861 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS 1 31862 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT 12 31863 31864 /* SerdesDigital :: Control1000X3 :: ext_phy_crs_mode [11:11] */ 31865 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK 0x0800 31866 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN 0 31867 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS 1 31868 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT 11 31869 31870 /* SerdesDigital :: Control1000X3 :: jam_false_carrier_mode [10:10] */ 31871 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK 0x0400 31872 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN 0 31873 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS 1 31874 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT 10 31875 31876 /* SerdesDigital :: Control1000X3 :: block_txen_mode [09:09] */ 31877 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_MASK 0x0200 31878 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN 0 31879 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_BITS 1 31880 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT 9 31881 31882 /* SerdesDigital :: Control1000X3 :: force_txfifo_on [08:08] */ 31883 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_MASK 0x0100 31884 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN 0 31885 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_BITS 1 31886 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT 8 31887 31888 /* SerdesDigital :: Control1000X3 :: bypass_txfifo1000 [07:07] */ 31889 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_MASK 0x0080 31890 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN 0 31891 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_BITS 1 31892 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT 7 31893 31894 /* SerdesDigital :: Control1000X3 :: freq_lock_elasticity_tx [06:06] */ 31895 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_MASK 0x0040 31896 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_ALIGN 0 31897 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_BITS 1 31898 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_SHIFT 6 31899 31900 /* SerdesDigital :: Control1000X3 :: freq_lock_elasticity_rx [05:05] */ 31901 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_MASK 0x0020 31902 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_ALIGN 0 31903 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_BITS 1 31904 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_SHIFT 5 31905 31906 /* SerdesDigital :: Control1000X3 :: early_preamble_rx [04:04] */ 31907 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK 0x0010 31908 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN 0 31909 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS 1 31910 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT 4 31911 31912 /* SerdesDigital :: Control1000X3 :: early_preamble_tx [03:03] */ 31913 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK 0x0008 31914 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN 0 31915 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS 1 31916 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT 3 31917 31918 /* SerdesDigital :: Control1000X3 :: fifo_elasicity_tx [02:01] */ 31919 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_MASK 0x0006 31920 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_ALIGN 0 31921 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_BITS 2 31922 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_SHIFT 1 31923 31924 /* add */ 31925 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_5KB 0 31926 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_10KB 1 31927 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_13p5KB 2 31928 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_18p5KB 3 31929 31930 /* SerdesDigital :: Control1000X3 :: tx_fifo_rst [00:00] */ 31931 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_MASK 0x0001 31932 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_ALIGN 0 31933 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_BITS 1 31934 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_SHIFT 0 31935 31936 31937 /**************************************************************************** 31938 * SerdesDigital :: Control1000X4 31939 */ 31940 /* SerdesDigital :: Control1000X4 :: reserved0 [15:14] */ 31941 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_MASK 0xc000 31942 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_ALIGN 0 31943 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_BITS 2 31944 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_SHIFT 14 31945 31946 /* SerdesDigital :: Control1000X4 :: disable_resolution_err_restart [13:13] */ 31947 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK 0x2000 31948 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0 31949 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS 1 31950 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13 31951 31952 /* SerdesDigital :: Control1000X4 :: enable_last_resolution_err [12:12] */ 31953 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK 0x1000 31954 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN 0 31955 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS 1 31956 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT 12 31957 31958 /* SerdesDigital :: Control1000X4 :: tx_config_reg_sel [11:11] */ 31959 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK 0x0800 31960 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN 0 31961 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS 1 31962 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT 11 31963 31964 /* SerdesDigital :: Control1000X4 :: zero_rxdgmii [10:10] */ 31965 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_MASK 0x0400 31966 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_ALIGN 0 31967 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_BITS 1 31968 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_SHIFT 10 31969 31970 /* SerdesDigital :: Control1000X4 :: clear_linkdown [09:09] */ 31971 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_MASK 0x0200 31972 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN 0 31973 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_BITS 1 31974 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT 9 31975 31976 /* SerdesDigital :: Control1000X4 :: latch_linkdown_enable [08:08] */ 31977 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK 0x0100 31978 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN 0 31979 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS 1 31980 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT 8 31981 31982 /* SerdesDigital :: Control1000X4 :: link_force [07:07] */ 31983 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_MASK 0x0080 31984 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_ALIGN 0 31985 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_BITS 1 31986 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_SHIFT 7 31987 31988 /* SerdesDigital :: Control1000X4 :: reserved1 [06:06] */ 31989 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_MASK 0x0040 31990 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_ALIGN 0 31991 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_BITS 1 31992 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_SHIFT 6 31993 31994 /* SerdesDigital :: Control1000X4 :: lp_next_page_sel [05:05] */ 31995 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_MASK 0x0020 31996 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_ALIGN 0 31997 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_BITS 1 31998 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_SHIFT 5 31999 32000 /* SerdesDigital :: Control1000X4 :: np_count_ClrnBp [04:04] */ 32001 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_MASK 0x0010 32002 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_ALIGN 0 32003 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_BITS 1 32004 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_SHIFT 4 32005 32006 /* SerdesDigital :: Control1000X4 :: np_count_ClrnRd [03:03] */ 32007 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_MASK 0x0008 32008 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_ALIGN 0 32009 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_BITS 1 32010 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_SHIFT 3 32011 32012 /* SerdesDigital :: Control1000X4 :: MiscRxStatus_sel [02:00] */ 32013 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_MASK 0x0007 32014 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN 0 32015 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_BITS 3 32016 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT 0 32017 32018 32019 /**************************************************************************** 32020 * SerdesDigital :: Status1000X1 32021 */ 32022 /* SerdesDigital :: Status1000X1 :: txfifo_err_detected [15:15] */ 32023 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK 0x8000 32024 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN 0 32025 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS 1 32026 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT 15 32027 32028 /* SerdesDigital :: Status1000X1 :: rxfifo_err_detected [14:14] */ 32029 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK 0x4000 32030 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN 0 32031 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS 1 32032 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT 14 32033 32034 /* SerdesDigital :: Status1000X1 :: false_carrier_detected [13:13] */ 32035 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK 0x2000 32036 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN 0 32037 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS 1 32038 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT 13 32039 32040 /* SerdesDigital :: Status1000X1 :: crc_err_detected [12:12] */ 32041 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_MASK 0x1000 32042 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_ALIGN 0 32043 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_BITS 1 32044 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_SHIFT 12 32045 32046 /* SerdesDigital :: Status1000X1 :: tx_err_detected [11:11] */ 32047 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_MASK 0x0800 32048 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_ALIGN 0 32049 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_BITS 1 32050 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_SHIFT 11 32051 32052 /* SerdesDigital :: Status1000X1 :: rx_err_detected [10:10] */ 32053 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_MASK 0x0400 32054 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_ALIGN 0 32055 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_BITS 1 32056 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_SHIFT 10 32057 32058 /* SerdesDigital :: Status1000X1 :: carrier_extend_err_detected [09:09] */ 32059 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200 32060 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0 32061 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1 32062 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9 32063 32064 /* SerdesDigital :: Status1000X1 :: early_end_extension_detected [08:08] */ 32065 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100 32066 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0 32067 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1 32068 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8 32069 32070 /* SerdesDigital :: Status1000X1 :: link_status_change [07:07] */ 32071 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_MASK 0x0080 32072 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN 0 32073 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_BITS 1 32074 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT 7 32075 32076 /* SerdesDigital :: Status1000X1 :: pause_resolution_rxside [06:06] */ 32077 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0040 32078 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 32079 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS 1 32080 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT 6 32081 32082 /* SerdesDigital :: Status1000X1 :: pause_resolution_txside [05:05] */ 32083 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0020 32084 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 32085 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS 1 32086 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT 5 32087 32088 /* SerdesDigital :: Status1000X1 :: speed_status [04:03] */ 32089 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_MASK 0x0018 32090 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_ALIGN 0 32091 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_BITS 2 32092 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_SHIFT 3 32093 32094 /* SerdesDigital :: Status1000X1 :: duplex_status [02:02] */ 32095 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_MASK 0x0004 32096 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_ALIGN 0 32097 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_BITS 1 32098 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_SHIFT 2 32099 32100 /* SerdesDigital :: Status1000X1 :: link_status [01:01] */ 32101 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_MASK 0x0002 32102 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_ALIGN 0 32103 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_BITS 1 32104 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_SHIFT 1 32105 32106 /* SerdesDigital :: Status1000X1 :: sgmii_mode [00:00] */ 32107 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_MASK 0x0001 32108 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_ALIGN 0 32109 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_BITS 1 32110 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_SHIFT 0 32111 32112 32113 /**************************************************************************** 32114 * SerdesDigital :: Status1000X2 32115 */ 32116 /* SerdesDigital :: Status1000X2 :: sgmii_mode_change [15:15] */ 32117 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_MASK 0x8000 32118 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN 0 32119 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_BITS 1 32120 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT 15 32121 32122 /* SerdesDigital :: Status1000X2 :: consistency_mismatch [14:14] */ 32123 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_MASK 0x4000 32124 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN 0 32125 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_BITS 1 32126 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT 14 32127 32128 /* SerdesDigital :: Status1000X2 :: autoneg_resolution_err [13:13] */ 32129 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK 0x2000 32130 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN 0 32131 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS 1 32132 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT 13 32133 32134 /* SerdesDigital :: Status1000X2 :: sgmii_selector_mismatch [12:12] */ 32135 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK 0x1000 32136 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN 0 32137 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS 1 32138 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT 12 32139 32140 /* SerdesDigital :: Status1000X2 :: sync_status_fail [11:11] */ 32141 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_MASK 0x0800 32142 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN 0 32143 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_BITS 1 32144 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT 11 32145 32146 /* SerdesDigital :: Status1000X2 :: sync_status_ok [10:10] */ 32147 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_MASK 0x0400 32148 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_ALIGN 0 32149 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_BITS 1 32150 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_SHIFT 10 32151 32152 /* SerdesDigital :: Status1000X2 :: rudi_c [09:09] */ 32153 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_MASK 0x0200 32154 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_ALIGN 0 32155 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_BITS 1 32156 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_SHIFT 9 32157 32158 /* SerdesDigital :: Status1000X2 :: rudi_I [08:08] */ 32159 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_MASK 0x0100 32160 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_ALIGN 0 32161 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_BITS 1 32162 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_SHIFT 8 32163 32164 /* SerdesDigital :: Status1000X2 :: rudi_invalid [07:07] */ 32165 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_MASK 0x0080 32166 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_ALIGN 0 32167 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_BITS 1 32168 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_SHIFT 7 32169 32170 /* SerdesDigital :: Status1000X2 :: linkDown_syncLoss [06:06] */ 32171 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK 0x0040 32172 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN 0 32173 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS 1 32174 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT 6 32175 32176 /* SerdesDigital :: Status1000X2 :: idle_detect_state [05:05] */ 32177 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_MASK 0x0020 32178 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_ALIGN 0 32179 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_BITS 1 32180 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_SHIFT 5 32181 32182 /* SerdesDigital :: Status1000X2 :: complete_acknowledge_state [04:04] */ 32183 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010 32184 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0 32185 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1 32186 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4 32187 32188 /* SerdesDigital :: Status1000X2 :: acknowledge_detect_state [03:03] */ 32189 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK 0x0008 32190 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0 32191 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS 1 32192 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3 32193 32194 /* SerdesDigital :: Status1000X2 :: ability_detect_state [02:02] */ 32195 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_MASK 0x0004 32196 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN 0 32197 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_BITS 1 32198 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT 2 32199 32200 /* union - case anError [01:01] */ 32201 /* SerdesDigital :: Status1000X2 :: an_error_state [01:01] */ 32202 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK 0x0002 32203 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN 0 32204 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS 1 32205 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT 1 32206 32207 32208 /* union - case anDisableLink [01:01] */ 32209 /* SerdesDigital :: Status1000X2 :: an_disable_link_ok_state [01:01] */ 32210 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002 32211 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0 32212 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1 32213 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1 32214 32215 32216 /* SerdesDigital :: Status1000X2 :: an_enable_state [00:00] */ 32217 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_MASK 0x0001 32218 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_ALIGN 0 32219 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_BITS 1 32220 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_SHIFT 0 32221 32222 32223 /**************************************************************************** 32224 * SerdesDigital :: Status1000X3 32225 */ 32226 /* SerdesDigital :: Status1000X3 :: reserved0 [15:13] */ 32227 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_MASK 0xe000 32228 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_ALIGN 0 32229 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_BITS 3 32230 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_SHIFT 13 32231 32232 /* SerdesDigital :: Status1000X3 :: pd_park_an [12:12] */ 32233 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_MASK 0x1000 32234 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_ALIGN 0 32235 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_BITS 1 32236 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_SHIFT 12 32237 32238 /* SerdesDigital :: Status1000X3 :: remotePhy_autosel [11:11] */ 32239 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK 0x0800 32240 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN 0 32241 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS 1 32242 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT 11 32243 32244 /* SerdesDigital :: Status1000X3 :: latch_linkdown [10:10] */ 32245 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_MASK 0x0400 32246 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_ALIGN 0 32247 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_BITS 1 32248 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_SHIFT 10 32249 32250 /* SerdesDigital :: Status1000X3 :: sd_filter [09:09] */ 32251 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_MASK 0x0200 32252 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_ALIGN 0 32253 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_BITS 1 32254 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_SHIFT 9 32255 32256 /* SerdesDigital :: Status1000X3 :: sd_mux [08:08] */ 32257 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_MASK 0x0100 32258 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_ALIGN 0 32259 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_BITS 1 32260 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_SHIFT 8 32261 32262 /* SerdesDigital :: Status1000X3 :: sd_filter_chg [07:07] */ 32263 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_MASK 0x0080 32264 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_ALIGN 0 32265 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_BITS 1 32266 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_SHIFT 7 32267 32268 /* SerdesDigital :: Status1000X3 :: reserved1 [06:00] */ 32269 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_MASK 0x007f 32270 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_ALIGN 0 32271 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_BITS 7 32272 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_SHIFT 0 32273 32274 32275 /**************************************************************************** 32276 * SerdesDigital :: BadCodeGroup 32277 */ 32278 /* SerdesDigital :: BadCodeGroup :: badCodeGroups [15:08] */ 32279 #define SERDESDIGITAL_BADCODEGROUP_BADCODEGROUPS_MASK 0xff00 32280 #define SERDESDIGITAL_BADCODEGROUP_BADCODEGROUPS_ALIGN 0 32281 #define SERDESDIGITAL_BADCODEGROUP_BADCODEGROUPS_BITS 8 32282 #define SERDESDIGITAL_BADCODEGROUP_BADCODEGROUPS_SHIFT 8 32283 32284 /* SerdesDigital :: BadCodeGroup :: reserved0 [07:00] */ 32285 #define SERDESDIGITAL_BADCODEGROUP_RESERVED0_MASK 0x00ff 32286 #define SERDESDIGITAL_BADCODEGROUP_RESERVED0_ALIGN 0 32287 #define SERDESDIGITAL_BADCODEGROUP_RESERVED0_BITS 8 32288 #define SERDESDIGITAL_BADCODEGROUP_RESERVED0_SHIFT 0 32289 32290 32291 /**************************************************************************** 32292 * SerdesDigital :: Misc1 32293 */ 32294 /* SerdesDigital :: Misc1 :: refclk_sel [15:13] */ 32295 #define SERDESDIGITAL_MISC1_REFCLK_SEL_MASK 0xe000 32296 #define SERDESDIGITAL_MISC1_REFCLK_SEL_ALIGN 0 32297 #define SERDESDIGITAL_MISC1_REFCLK_SEL_BITS 3 32298 #define SERDESDIGITAL_MISC1_REFCLK_SEL_SHIFT 13 32299 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_25MHz 0 32300 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_100MHz 1 32301 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_125MHz 2 32302 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_156p25MHz 3 32303 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_187p5MHz 4 32304 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_161p25Mhz 5 32305 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_50Mhz 6 32306 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_106p25Mhz 7 32307 32308 /* SerdesDigital :: Misc1 :: force_pll_mode_afe_sel [12:12] */ 32309 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_MASK 0x1000 32310 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_ALIGN 0 32311 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_BITS 1 32312 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_SHIFT 12 32313 32314 /* SerdesDigital :: Misc1 :: force_pll_mode_afe [11:08] */ 32315 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_MASK 0x0f00 32316 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_ALIGN 0 32317 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_BITS 4 32318 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SHIFT 8 32319 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div32 0 32320 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div36 1 32321 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div40 2 32322 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div42 3 32323 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div48 4 32324 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div50 5 32325 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div52 6 32326 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div54 7 32327 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div60 8 32328 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div64 9 32329 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div66 10 32330 /* added for EPON serdes */ 32331 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div20 10 32332 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div68 11 32333 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div70 12 32334 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div80 13 32335 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div92 14 32336 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div100 15 32337 32338 /* SerdesDigital :: Misc1 :: force_tick0_sw2 [07:07] */ 32339 #define SERDESDIGITAL_MISC1_FORCE_TICK0_SW2_MASK 0x0080 32340 #define SERDESDIGITAL_MISC1_FORCE_TICK0_SW2_ALIGN 0 32341 #define SERDESDIGITAL_MISC1_FORCE_TICK0_SW2_BITS 1 32342 #define SERDESDIGITAL_MISC1_FORCE_TICK0_SW2_SHIFT 7 32343 32344 /* SerdesDigital :: Misc1 :: tx_underrun_1000_dis [06:06] */ 32345 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_MASK 0x0040 32346 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_ALIGN 0 32347 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_BITS 1 32348 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_SHIFT 6 32349 32350 /* SerdesDigital :: Misc1 :: force_ln_mode [05:05] */ 32351 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_MASK 0x0020 32352 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_ALIGN 0 32353 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_BITS 1 32354 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_SHIFT 5 32355 32356 /* SerdesDigital :: Misc1 :: force_speed [04:00] */ 32357 #define SERDESDIGITAL_MISC1_FORCE_SPEED_MASK 0x001f 32358 #define SERDESDIGITAL_MISC1_FORCE_SPEED_ALIGN 0 32359 #define SERDESDIGITAL_MISC1_FORCE_SPEED_BITS 5 32360 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SHIFT 0 32361 32362 /* add wc force_speed[5]=1 */ 32363 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10G_DXGXS 0 32364 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10p5G_HiG_DXGXS 1 32365 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10p5G_DXGXS 2 32366 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_12p773G_HiG_DXGXS 3 32367 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_12p773G_DXGXS 4 32368 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10G_XFI 5 32369 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_40G_X4 6 32370 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_20G_HiG_DXGXS 7 32371 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_20G_DXGXS 8 32372 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10G_SFI 9 32373 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_31p5G 10 32374 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_32p7G 11 32375 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_20G_SCR 12 32376 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10G_HiG_DXGXS_SCR 13 32377 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10G_DXGXS_SCR 14 32378 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_12G_R2 15 32379 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10G_X2 16 32380 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_40G_KR4 17 32381 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_40G_CR4 18 32382 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_100G_CR10 19 32383 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_5G_HiG_DXGXS 20 32384 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_5G_DXGXS 21 32385 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_15p75_HiG_DXGXS 22 32386 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_20G_KR2 31 32387 32388 /* add wl force_speed[7:5]=0x2 */ 32389 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_20G_CR2 0 32390 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_3p125G 2 32391 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_6p25G 3 32392 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10p3125G 4 32393 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10p9375G 5 32394 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_12p5G 6 32395 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_11p5G 7 32396 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_1p25G 8 32397 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_5p75G 9 32398 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_pcs_bypass 10 32399 32400 /* force_speed[5]=0 */ 32401 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_11500_X1 07 32402 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_5750_X1 10 32403 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_2500BRCM_X1 16 32404 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X4 17 32405 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_6000BRCM_X4 18 32406 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10GHiGig_X4 19 32407 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10GBASE_CX4 20 32408 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_12GHiGig_X4 21 32409 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_12p5GHiGig_X4 22 32410 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_13GHiGig_X4 23 32411 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_15GHiGig_X4 24 32412 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_16GHiGig_X4 25 32413 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X1 26 32414 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_6363BRCM_X1 27 32415 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_20GHiGig_X4 28 32416 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_21GHiGig_X4 29 32417 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_25p45GHiGig_X4 30 32418 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10G_HiG_DXGXS 31 32419 32420 32421 /**************************************************************************** 32422 * SerdesDigital :: Misc2 32423 */ 32424 /* SerdesDigital :: Misc2 :: rxckpl_sel_combo [15:15] */ 32425 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_MASK 0x8000 32426 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_ALIGN 0 32427 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_BITS 1 32428 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_SHIFT 15 32429 32430 /* SerdesDigital :: Misc2 :: rxck_mii_gen_sel_force [14:14] */ 32431 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_MASK 0x4000 32432 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_ALIGN 0 32433 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_BITS 1 32434 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_SHIFT 14 32435 32436 /* SerdesDigital :: Misc2 :: rxck_mii_gen_sel_val [13:13] */ 32437 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_MASK 0x2000 32438 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_ALIGN 0 32439 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_BITS 1 32440 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_SHIFT 13 32441 32442 /* SerdesDigital :: Misc2 :: rlpbk_sw_force [12:12] */ 32443 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_MASK 0x1000 32444 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_ALIGN 0 32445 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_BITS 1 32446 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_SHIFT 12 32447 32448 /* SerdesDigital :: Misc2 :: rlpbk_RxRst_en [11:11] */ 32449 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_MASK 0x0800 32450 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_ALIGN 0 32451 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_BITS 1 32452 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_SHIFT 11 32453 32454 /* SerdesDigital :: Misc2 :: clkSigdet_bypass [10:10] */ 32455 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_MASK 0x0400 32456 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_ALIGN 0 32457 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_BITS 1 32458 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_SHIFT 10 32459 32460 /* SerdesDigital :: Misc2 :: clk41_bypass [09:09] */ 32461 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_MASK 0x0200 32462 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_ALIGN 0 32463 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_BITS 1 32464 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_SHIFT 9 32465 32466 /* SerdesDigital :: Misc2 :: miiGmiiDly_en [08:08] */ 32467 #define SERDESDIGITAL_MISC2_MIIGMIIDLY_EN_MASK 0x0100 32468 #define SERDESDIGITAL_MISC2_MIIGMIIDLY_EN_ALIGN 0 32469 #define SERDESDIGITAL_MISC2_MIIGMIIDLY_EN_BITS 1 32470 #define SERDESDIGITAL_MISC2_MIIGMIIDLY_EN_SHIFT 8 32471 32472 /* SerdesDigital :: Misc2 :: miiGmiiMux_en [07:07] */ 32473 #define SERDESDIGITAL_MISC2_MIIGMIIMUX_EN_MASK 0x0080 32474 #define SERDESDIGITAL_MISC2_MIIGMIIMUX_EN_ALIGN 0 32475 #define SERDESDIGITAL_MISC2_MIIGMIIMUX_EN_BITS 1 32476 #define SERDESDIGITAL_MISC2_MIIGMIIMUX_EN_SHIFT 7 32477 32478 /* SerdesDigital :: Misc2 :: KX_cl73_an_en [06:06] */ 32479 #define SERDESDIGITAL_MISC2_KX_CL73_AN_EN_MASK 0x0040 32480 #define SERDESDIGITAL_MISC2_KX_CL73_AN_EN_ALIGN 0 32481 #define SERDESDIGITAL_MISC2_KX_CL73_AN_EN_BITS 1 32482 #define SERDESDIGITAL_MISC2_KX_CL73_AN_EN_SHIFT 6 32483 32484 /* SerdesDigital :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */ 32485 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK 0x0020 32486 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN 0 32487 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS 1 32488 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT 5 32489 32490 /* SerdesDigital :: Misc2 :: fifo_err_cya [04:04] */ 32491 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_MASK 0x0010 32492 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_ALIGN 0 32493 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_BITS 1 32494 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_SHIFT 4 32495 32496 /* SerdesDigital :: Misc2 :: an_txdisablePhase [03:03] */ 32497 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_MASK 0x0008 32498 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_ALIGN 0 32499 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_BITS 1 32500 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_SHIFT 3 32501 32502 /* SerdesDigital :: Misc2 :: an_rxSeqStartDis [02:02] */ 32503 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_MASK 0x0004 32504 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_ALIGN 0 32505 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_BITS 1 32506 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_SHIFT 2 32507 32508 /* SerdesDigital :: Misc2 :: an_txdisable_ln [01:01] */ 32509 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_MASK 0x0002 32510 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_ALIGN 0 32511 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_BITS 1 32512 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_SHIFT 1 32513 32514 /* SerdesDigital :: Misc2 :: an_deadTrap [00:00] */ 32515 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_MASK 0x0001 32516 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_ALIGN 0 32517 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_BITS 1 32518 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_SHIFT 0 32519 32520 32521 /**************************************************************************** 32522 * SerdesDigital :: PatGenCtrl 32523 */ 32524 /* SerdesDigital :: PatGenCtrl :: patgen_lpi_en [15:15] */ 32525 #define SERDESDIGITAL_PATGENCTRL_PATGEN_LPI_EN_MASK 0x8000 32526 #define SERDESDIGITAL_PATGENCTRL_PATGEN_LPI_EN_ALIGN 0 32527 #define SERDESDIGITAL_PATGENCTRL_PATGEN_LPI_EN_BITS 1 32528 #define SERDESDIGITAL_PATGENCTRL_PATGEN_LPI_EN_SHIFT 15 32529 32530 /* SerdesDigital :: PatGenCtrl :: tx_err [14:14] */ 32531 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_MASK 0x4000 32532 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_ALIGN 0 32533 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_BITS 1 32534 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_SHIFT 14 32535 32536 /* SerdesDigital :: PatGenCtrl :: skip_crc [13:13] */ 32537 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_MASK 0x2000 32538 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_ALIGN 0 32539 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_BITS 1 32540 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_SHIFT 13 32541 32542 /* SerdesDigital :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */ 32543 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK 0x1000 32544 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN 0 32545 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS 1 32546 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT 12 32547 32548 /* SerdesDigital :: PatGenCtrl :: ipg_select [11:09] */ 32549 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_MASK 0x0e00 32550 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_ALIGN 0 32551 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_BITS 3 32552 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_SHIFT 9 32553 32554 /* SerdesDigital :: PatGenCtrl :: pkt_size [08:03] */ 32555 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_MASK 0x01f8 32556 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_ALIGN 0 32557 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_BITS 6 32558 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_SHIFT 3 32559 32560 /* SerdesDigital :: PatGenCtrl :: single_pass_mode [02:02] */ 32561 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_MASK 0x0004 32562 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_ALIGN 0 32563 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_BITS 1 32564 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_SHIFT 2 32565 32566 /* SerdesDigital :: PatGenCtrl :: run_pattern_gen [01:01] */ 32567 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_MASK 0x0002 32568 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_ALIGN 0 32569 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_BITS 1 32570 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_SHIFT 1 32571 32572 /* SerdesDigital :: PatGenCtrl :: sel_pattern_gen_data [00:00] */ 32573 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK 0x0001 32574 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN 0 32575 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS 1 32576 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT 0 32577 32578 32579 /**************************************************************************** 32580 * SerdesDigital :: PatGenStat 32581 */ 32582 /* SerdesDigital :: PatGenStat :: reserved0 [15:04] */ 32583 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_MASK 0xfff0 32584 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_ALIGN 0 32585 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_BITS 12 32586 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_SHIFT 4 32587 32588 /* SerdesDigital :: PatGenStat :: pattern_gen_active [03:03] */ 32589 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK 0x0008 32590 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN 0 32591 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS 1 32592 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT 3 32593 32594 /* SerdesDigital :: PatGenStat :: pattern_gen_fsm [02:00] */ 32595 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_MASK 0x0007 32596 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_ALIGN 0 32597 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_BITS 3 32598 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_SHIFT 0 32599 32600 32601 /**************************************************************************** 32602 * SerdesDigital :: TestMode 32603 */ 32604 /* SerdesDigital :: TestMode :: to_dig_mux_ovr [15:08] */ 32605 #define SERDESDIGITAL_TESTMODE_TO_DIG_MUX_OVR_MASK 0xff00 32606 #define SERDESDIGITAL_TESTMODE_TO_DIG_MUX_OVR_ALIGN 0 32607 #define SERDESDIGITAL_TESTMODE_TO_DIG_MUX_OVR_BITS 8 32608 #define SERDESDIGITAL_TESTMODE_TO_DIG_MUX_OVR_SHIFT 8 32609 32610 /* SerdesDigital :: TestMode :: to_dig_mux_ovr_en [07:07] */ 32611 #define SERDESDIGITAL_TESTMODE_TO_DIG_MUX_OVR_EN_MASK 0x0080 32612 #define SERDESDIGITAL_TESTMODE_TO_DIG_MUX_OVR_EN_ALIGN 0 32613 #define SERDESDIGITAL_TESTMODE_TO_DIG_MUX_OVR_EN_BITS 1 32614 #define SERDESDIGITAL_TESTMODE_TO_DIG_MUX_OVR_EN_SHIFT 7 32615 32616 /* SerdesDigital :: TestMode :: chip_tmux_half_sel [06:06] */ 32617 #define SERDESDIGITAL_TESTMODE_CHIP_TMUX_HALF_SEL_MASK 0x0040 32618 #define SERDESDIGITAL_TESTMODE_CHIP_TMUX_HALF_SEL_ALIGN 0 32619 #define SERDESDIGITAL_TESTMODE_CHIP_TMUX_HALF_SEL_BITS 1 32620 #define SERDESDIGITAL_TESTMODE_CHIP_TMUX_HALF_SEL_SHIFT 6 32621 32622 /* SerdesDigital :: TestMode :: chip_tmux_sel [05:05] */ 32623 #define SERDESDIGITAL_TESTMODE_CHIP_TMUX_SEL_MASK 0x0020 32624 #define SERDESDIGITAL_TESTMODE_CHIP_TMUX_SEL_ALIGN 0 32625 #define SERDESDIGITAL_TESTMODE_CHIP_TMUX_SEL_BITS 1 32626 #define SERDESDIGITAL_TESTMODE_CHIP_TMUX_SEL_SHIFT 5 32627 32628 /* SerdesDigital :: TestMode :: IP_tmux_sel [04:01] */ 32629 #define SERDESDIGITAL_TESTMODE_IP_TMUX_SEL_MASK 0x001e 32630 #define SERDESDIGITAL_TESTMODE_IP_TMUX_SEL_ALIGN 0 32631 #define SERDESDIGITAL_TESTMODE_IP_TMUX_SEL_BITS 4 32632 #define SERDESDIGITAL_TESTMODE_IP_TMUX_SEL_SHIFT 1 32633 32634 /* SerdesDigital :: TestMode :: IP_tmux_en [00:00] */ 32635 #define SERDESDIGITAL_TESTMODE_IP_TMUX_EN_MASK 0x0001 32636 #define SERDESDIGITAL_TESTMODE_IP_TMUX_EN_ALIGN 0 32637 #define SERDESDIGITAL_TESTMODE_IP_TMUX_EN_BITS 1 32638 #define SERDESDIGITAL_TESTMODE_IP_TMUX_EN_SHIFT 0 32639 32640 32641 /**************************************************************************** 32642 * SerdesDigital :: TxPktCnt 32643 */ 32644 /* SerdesDigital :: TxPktCnt :: TxPktCnt [15:00] */ 32645 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_MASK 0xffff 32646 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_ALIGN 0 32647 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_BITS 16 32648 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_SHIFT 0 32649 32650 32651 /**************************************************************************** 32652 * SerdesDigital :: RxPktCnt 32653 */ 32654 /* SerdesDigital :: RxPktCnt :: RxPktCnt [15:00] */ 32655 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_MASK 0xffff 32656 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_ALIGN 0 32657 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_BITS 16 32658 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_SHIFT 0 32659 32660 32661 /**************************************************************************** 32662 * Warpcore_USER_SerdesID 32663 */ 32664 /**************************************************************************** 32665 * SerdesID :: serdesID0 32666 */ 32667 /* SerdesID :: serdesID0 :: rev_letter [15:14] */ 32668 #define SERDESID_SERDESID0_REV_LETTER_MASK 0xc000 32669 #define SERDESID_SERDESID0_REV_LETTER_ALIGN 0 32670 #define SERDESID_SERDESID0_REV_LETTER_BITS 2 32671 #define SERDESID_SERDESID0_REV_LETTER_SHIFT 14 32672 32673 /* SerdesID :: serdesID0 :: rev_number [13:11] */ 32674 #define SERDESID_SERDESID0_REV_NUMBER_MASK 0x3800 32675 #define SERDESID_SERDESID0_REV_NUMBER_ALIGN 0 32676 #define SERDESID_SERDESID0_REV_NUMBER_BITS 3 32677 #define SERDESID_SERDESID0_REV_NUMBER_SHIFT 11 32678 32679 /* SerdesID :: serdesID0 :: bonding [10:09] */ 32680 #define SERDESID_SERDESID0_BONDING_MASK 0x0600 32681 #define SERDESID_SERDESID0_BONDING_ALIGN 0 32682 #define SERDESID_SERDESID0_BONDING_BITS 2 32683 #define SERDESID_SERDESID0_BONDING_SHIFT 9 32684 32685 /* SerdesID :: serdesID0 :: tech_proc [08:06] */ 32686 #define SERDESID_SERDESID0_TECH_PROC_MASK 0x01c0 32687 #define SERDESID_SERDESID0_TECH_PROC_ALIGN 0 32688 #define SERDESID_SERDESID0_TECH_PROC_BITS 3 32689 #define SERDESID_SERDESID0_TECH_PROC_SHIFT 6 32690 32691 /* SerdesID :: serdesID0 :: model_number [05:00] */ 32692 #define SERDESID_SERDESID0_MODEL_NUMBER_MASK 0x003f 32693 #define SERDESID_SERDESID0_MODEL_NUMBER_ALIGN 0 32694 #define SERDESID_SERDESID0_MODEL_NUMBER_BITS 6 32695 #define SERDESID_SERDESID0_MODEL_NUMBER_SHIFT 0 32696 32697 32698 /**************************************************************************** 32699 * SerdesID :: serdesID1 32700 */ 32701 /* SerdesID :: serdesID1 :: multiplicity [15:12] */ 32702 #define SERDESID_SERDESID1_MULTIPLICITY_MASK 0xf000 32703 #define SERDESID_SERDESID1_MULTIPLICITY_ALIGN 0 32704 #define SERDESID_SERDESID1_MULTIPLICITY_BITS 4 32705 #define SERDESID_SERDESID1_MULTIPLICITY_SHIFT 12 32706 32707 /* SerdesID :: serdesID1 :: CL37 [11:11] */ 32708 #define SERDESID_SERDESID1_CL37_MASK 0x0800 32709 #define SERDESID_SERDESID1_CL37_ALIGN 0 32710 #define SERDESID_SERDESID1_CL37_BITS 1 32711 #define SERDESID_SERDESID1_CL37_SHIFT 11 32712 32713 /* SerdesID :: serdesID1 :: CL73 [10:10] */ 32714 #define SERDESID_SERDESID1_CL73_MASK 0x0400 32715 #define SERDESID_SERDESID1_CL73_ALIGN 0 32716 #define SERDESID_SERDESID1_CL73_BITS 1 32717 #define SERDESID_SERDESID1_CL73_SHIFT 10 32718 32719 /* SerdesID :: serdesID1 :: CL36 [09:09] */ 32720 #define SERDESID_SERDESID1_CL36_MASK 0x0200 32721 #define SERDESID_SERDESID1_CL36_ALIGN 0 32722 #define SERDESID_SERDESID1_CL36_BITS 1 32723 #define SERDESID_SERDESID1_CL36_SHIFT 9 32724 32725 /* SerdesID :: serdesID1 :: CL48 [08:08] */ 32726 #define SERDESID_SERDESID1_CL48_MASK 0x0100 32727 #define SERDESID_SERDESID1_CL48_ALIGN 0 32728 #define SERDESID_SERDESID1_CL48_BITS 1 32729 #define SERDESID_SERDESID1_CL48_SHIFT 8 32730 32731 /* SerdesID :: serdesID1 :: HiGig [07:07] */ 32732 #define SERDESID_SERDESID1_HIGIG_MASK 0x0080 32733 #define SERDESID_SERDESID1_HIGIG_ALIGN 0 32734 #define SERDESID_SERDESID1_HIGIG_BITS 1 32735 #define SERDESID_SERDESID1_HIGIG_SHIFT 7 32736 32737 /* SerdesID :: serdesID1 :: HiGigII [06:06] */ 32738 #define SERDESID_SERDESID1_HIGIGII_MASK 0x0040 32739 #define SERDESID_SERDESID1_HIGIGII_ALIGN 0 32740 #define SERDESID_SERDESID1_HIGIGII_BITS 1 32741 #define SERDESID_SERDESID1_HIGIGII_SHIFT 6 32742 32743 /* SerdesID :: serdesID1 :: PCIE [05:05] */ 32744 #define SERDESID_SERDESID1_PCIE_MASK 0x0020 32745 #define SERDESID_SERDESID1_PCIE_ALIGN 0 32746 #define SERDESID_SERDESID1_PCIE_BITS 1 32747 #define SERDESID_SERDESID1_PCIE_SHIFT 5 32748 32749 /* SerdesID :: serdesID1 :: PCIE_II [04:04] */ 32750 #define SERDESID_SERDESID1_PCIE_II_MASK 0x0010 32751 #define SERDESID_SERDESID1_PCIE_II_ALIGN 0 32752 #define SERDESID_SERDESID1_PCIE_II_BITS 1 32753 #define SERDESID_SERDESID1_PCIE_II_SHIFT 4 32754 32755 /* SerdesID :: serdesID1 :: brcm_64B66B [03:03] */ 32756 #define SERDESID_SERDESID1_BRCM_64B66B_MASK 0x0008 32757 #define SERDESID_SERDESID1_BRCM_64B66B_ALIGN 0 32758 #define SERDESID_SERDESID1_BRCM_64B66B_BITS 1 32759 #define SERDESID_SERDESID1_BRCM_64B66B_SHIFT 3 32760 32761 /* SerdesID :: serdesID1 :: Scrambler [02:02] */ 32762 #define SERDESID_SERDESID1_SCRAMBLER_MASK 0x0004 32763 #define SERDESID_SERDESID1_SCRAMBLER_ALIGN 0 32764 #define SERDESID_SERDESID1_SCRAMBLER_BITS 1 32765 #define SERDESID_SERDESID1_SCRAMBLER_SHIFT 2 32766 32767 /* SerdesID :: serdesID1 :: reserved0 [01:00] */ 32768 #define SERDESID_SERDESID1_RESERVED0_MASK 0x0003 32769 #define SERDESID_SERDESID1_RESERVED0_ALIGN 0 32770 #define SERDESID_SERDESID1_RESERVED0_BITS 2 32771 #define SERDESID_SERDESID1_RESERVED0_SHIFT 0 32772 32773 32774 /**************************************************************************** 32775 * SerdesID :: serdesID2 32776 */ 32777 /* SerdesID :: serdesID2 :: ID3present [15:15] */ 32778 #define SERDESID_SERDESID2_ID3PRESENT_MASK 0x8000 32779 #define SERDESID_SERDESID2_ID3PRESENT_ALIGN 0 32780 #define SERDESID_SERDESID2_ID3PRESENT_BITS 1 32781 #define SERDESID_SERDESID2_ID3PRESENT_SHIFT 15 32782 32783 /* SerdesID :: serdesID2 :: dr_25G_4L [14:14] */ 32784 #define SERDESID_SERDESID2_DR_25G_4L_MASK 0x4000 32785 #define SERDESID_SERDESID2_DR_25G_4L_ALIGN 0 32786 #define SERDESID_SERDESID2_DR_25G_4L_BITS 1 32787 #define SERDESID_SERDESID2_DR_25G_4L_SHIFT 14 32788 32789 /* SerdesID :: serdesID2 :: dr_21G_4L [13:13] */ 32790 #define SERDESID_SERDESID2_DR_21G_4L_MASK 0x2000 32791 #define SERDESID_SERDESID2_DR_21G_4L_ALIGN 0 32792 #define SERDESID_SERDESID2_DR_21G_4L_BITS 1 32793 #define SERDESID_SERDESID2_DR_21G_4L_SHIFT 13 32794 32795 /* SerdesID :: serdesID2 :: dr_20G_4L [12:12] */ 32796 #define SERDESID_SERDESID2_DR_20G_4L_MASK 0x1000 32797 #define SERDESID_SERDESID2_DR_20G_4L_ALIGN 0 32798 #define SERDESID_SERDESID2_DR_20G_4L_BITS 1 32799 #define SERDESID_SERDESID2_DR_20G_4L_SHIFT 12 32800 32801 /* SerdesID :: serdesID2 :: dr_16G_4L [11:11] */ 32802 #define SERDESID_SERDESID2_DR_16G_4L_MASK 0x0800 32803 #define SERDESID_SERDESID2_DR_16G_4L_ALIGN 0 32804 #define SERDESID_SERDESID2_DR_16G_4L_BITS 1 32805 #define SERDESID_SERDESID2_DR_16G_4L_SHIFT 11 32806 32807 /* SerdesID :: serdesID2 :: dr_15G_4L [10:10] */ 32808 #define SERDESID_SERDESID2_DR_15G_4L_MASK 0x0400 32809 #define SERDESID_SERDESID2_DR_15G_4L_ALIGN 0 32810 #define SERDESID_SERDESID2_DR_15G_4L_BITS 1 32811 #define SERDESID_SERDESID2_DR_15G_4L_SHIFT 10 32812 32813 /* SerdesID :: serdesID2 :: dr_13G_4L [09:09] */ 32814 #define SERDESID_SERDESID2_DR_13G_4L_MASK 0x0200 32815 #define SERDESID_SERDESID2_DR_13G_4L_ALIGN 0 32816 #define SERDESID_SERDESID2_DR_13G_4L_BITS 1 32817 #define SERDESID_SERDESID2_DR_13G_4L_SHIFT 9 32818 32819 /* SerdesID :: serdesID2 :: dr_12_5G_4L [08:08] */ 32820 #define SERDESID_SERDESID2_DR_12_5G_4L_MASK 0x0100 32821 #define SERDESID_SERDESID2_DR_12_5G_4L_ALIGN 0 32822 #define SERDESID_SERDESID2_DR_12_5G_4L_BITS 1 32823 #define SERDESID_SERDESID2_DR_12_5G_4L_SHIFT 8 32824 32825 /* SerdesID :: serdesID2 :: dr_12G_4L [07:07] */ 32826 #define SERDESID_SERDESID2_DR_12G_4L_MASK 0x0080 32827 #define SERDESID_SERDESID2_DR_12G_4L_ALIGN 0 32828 #define SERDESID_SERDESID2_DR_12G_4L_BITS 1 32829 #define SERDESID_SERDESID2_DR_12G_4L_SHIFT 7 32830 32831 /* SerdesID :: serdesID2 :: dr_10G_4L [06:06] */ 32832 #define SERDESID_SERDESID2_DR_10G_4L_MASK 0x0040 32833 #define SERDESID_SERDESID2_DR_10G_4L_ALIGN 0 32834 #define SERDESID_SERDESID2_DR_10G_4L_BITS 1 32835 #define SERDESID_SERDESID2_DR_10G_4L_SHIFT 6 32836 32837 /* SerdesID :: serdesID2 :: dr_6G_4L [05:05] */ 32838 #define SERDESID_SERDESID2_DR_6G_4L_MASK 0x0020 32839 #define SERDESID_SERDESID2_DR_6G_4L_ALIGN 0 32840 #define SERDESID_SERDESID2_DR_6G_4L_BITS 1 32841 #define SERDESID_SERDESID2_DR_6G_4L_SHIFT 5 32842 32843 /* SerdesID :: serdesID2 :: dr_5G_4L [04:04] */ 32844 #define SERDESID_SERDESID2_DR_5G_4L_MASK 0x0010 32845 #define SERDESID_SERDESID2_DR_5G_4L_ALIGN 0 32846 #define SERDESID_SERDESID2_DR_5G_4L_BITS 1 32847 #define SERDESID_SERDESID2_DR_5G_4L_SHIFT 4 32848 32849 /* SerdesID :: serdesID2 :: dr_2p5G_SL [03:03] */ 32850 #define SERDESID_SERDESID2_DR_2P5G_SL_MASK 0x0008 32851 #define SERDESID_SERDESID2_DR_2P5G_SL_ALIGN 0 32852 #define SERDESID_SERDESID2_DR_2P5G_SL_BITS 1 32853 #define SERDESID_SERDESID2_DR_2P5G_SL_SHIFT 3 32854 32855 /* SerdesID :: serdesID2 :: dr_1G_SL [02:02] */ 32856 #define SERDESID_SERDESID2_DR_1G_SL_MASK 0x0004 32857 #define SERDESID_SERDESID2_DR_1G_SL_ALIGN 0 32858 #define SERDESID_SERDESID2_DR_1G_SL_BITS 1 32859 #define SERDESID_SERDESID2_DR_1G_SL_SHIFT 2 32860 32861 /* SerdesID :: serdesID2 :: dr_100M_SL [01:01] */ 32862 #define SERDESID_SERDESID2_DR_100M_SL_MASK 0x0002 32863 #define SERDESID_SERDESID2_DR_100M_SL_ALIGN 0 32864 #define SERDESID_SERDESID2_DR_100M_SL_BITS 1 32865 #define SERDESID_SERDESID2_DR_100M_SL_SHIFT 1 32866 32867 /* SerdesID :: serdesID2 :: dr_10M_SL [00:00] */ 32868 #define SERDESID_SERDESID2_DR_10M_SL_MASK 0x0001 32869 #define SERDESID_SERDESID2_DR_10M_SL_ALIGN 0 32870 #define SERDESID_SERDESID2_DR_10M_SL_BITS 1 32871 #define SERDESID_SERDESID2_DR_10M_SL_SHIFT 0 32872 32873 32874 /**************************************************************************** 32875 * SerdesID :: serdesID3 32876 */ 32877 /* SerdesID :: serdesID3 :: ID4present [15:15] */ 32878 #define SERDESID_SERDESID3_ID4PRESENT_MASK 0x8000 32879 #define SERDESID_SERDESID3_ID4PRESENT_ALIGN 0 32880 #define SERDESID_SERDESID3_ID4PRESENT_BITS 1 32881 #define SERDESID_SERDESID3_ID4PRESENT_SHIFT 15 32882 32883 /* SerdesID :: serdesID3 :: reserved0 [14:10] */ 32884 #define SERDESID_SERDESID3_RESERVED0_MASK 0x7c00 32885 #define SERDESID_SERDESID3_RESERVED0_ALIGN 0 32886 #define SERDESID_SERDESID3_RESERVED0_BITS 5 32887 #define SERDESID_SERDESID3_RESERVED0_SHIFT 10 32888 32889 /* SerdesID :: serdesID3 :: dr_40000_4L [09:09] */ 32890 #define SERDESID_SERDESID3_DR_40000_4L_MASK 0x0200 32891 #define SERDESID_SERDESID3_DR_40000_4L_ALIGN 0 32892 #define SERDESID_SERDESID3_DR_40000_4L_BITS 1 32893 #define SERDESID_SERDESID3_DR_40000_4L_SHIFT 9 32894 32895 /* SerdesID :: serdesID3 :: dr_32700_4L [08:08] */ 32896 #define SERDESID_SERDESID3_DR_32700_4L_MASK 0x0100 32897 #define SERDESID_SERDESID3_DR_32700_4L_ALIGN 0 32898 #define SERDESID_SERDESID3_DR_32700_4L_BITS 1 32899 #define SERDESID_SERDESID3_DR_32700_4L_SHIFT 8 32900 32901 /* SerdesID :: serdesID3 :: dr_31500_4L [07:07] */ 32902 #define SERDESID_SERDESID3_DR_31500_4L_MASK 0x0080 32903 #define SERDESID_SERDESID3_DR_31500_4L_ALIGN 0 32904 #define SERDESID_SERDESID3_DR_31500_4L_BITS 1 32905 #define SERDESID_SERDESID3_DR_31500_4L_SHIFT 7 32906 32907 /* SerdesID :: serdesID3 :: dr_2400_SL [06:06] */ 32908 #define SERDESID_SERDESID3_DR_2400_SL_MASK 0x0040 32909 #define SERDESID_SERDESID3_DR_2400_SL_ALIGN 0 32910 #define SERDESID_SERDESID3_DR_2400_SL_BITS 1 32911 #define SERDESID_SERDESID3_DR_2400_SL_SHIFT 6 32912 32913 /* SerdesID :: serdesID3 :: dr_1200_SL [05:05] */ 32914 #define SERDESID_SERDESID3_DR_1200_SL_MASK 0x0020 32915 #define SERDESID_SERDESID3_DR_1200_SL_ALIGN 0 32916 #define SERDESID_SERDESID3_DR_1200_SL_BITS 1 32917 #define SERDESID_SERDESID3_DR_1200_SL_SHIFT 5 32918 32919 /* SerdesID :: serdesID3 :: dr_6400_SL [04:04] */ 32920 #define SERDESID_SERDESID3_DR_6400_SL_MASK 0x0010 32921 #define SERDESID_SERDESID3_DR_6400_SL_ALIGN 0 32922 #define SERDESID_SERDESID3_DR_6400_SL_BITS 1 32923 #define SERDESID_SERDESID3_DR_6400_SL_SHIFT 4 32924 32925 /* SerdesID :: serdesID3 :: dr_5000_SL [03:03] */ 32926 #define SERDESID_SERDESID3_DR_5000_SL_MASK 0x0008 32927 #define SERDESID_SERDESID3_DR_5000_SL_ALIGN 0 32928 #define SERDESID_SERDESID3_DR_5000_SL_BITS 1 32929 #define SERDESID_SERDESID3_DR_5000_SL_SHIFT 3 32930 32931 /* SerdesID :: serdesID3 :: dr_4000_SL [02:02] */ 32932 #define SERDESID_SERDESID3_DR_4000_SL_MASK 0x0004 32933 #define SERDESID_SERDESID3_DR_4000_SL_ALIGN 0 32934 #define SERDESID_SERDESID3_DR_4000_SL_BITS 1 32935 #define SERDESID_SERDESID3_DR_4000_SL_SHIFT 2 32936 32937 /* SerdesID :: serdesID3 :: dr_2000_SL [01:01] */ 32938 #define SERDESID_SERDESID3_DR_2000_SL_MASK 0x0002 32939 #define SERDESID_SERDESID3_DR_2000_SL_ALIGN 0 32940 #define SERDESID_SERDESID3_DR_2000_SL_BITS 1 32941 #define SERDESID_SERDESID3_DR_2000_SL_SHIFT 1 32942 32943 /* SerdesID :: serdesID3 :: dr_100FX [00:00] */ 32944 #define SERDESID_SERDESID3_DR_100FX_MASK 0x0001 32945 #define SERDESID_SERDESID3_DR_100FX_ALIGN 0 32946 #define SERDESID_SERDESID3_DR_100FX_BITS 1 32947 #define SERDESID_SERDESID3_DR_100FX_SHIFT 0 32948 32949 32950 /**************************************************************************** 32951 * SerdesID :: serdesID4 32952 */ 32953 /* SerdesID :: serdesID4 :: ID5present [15:15] */ 32954 #define SERDESID_SERDESID4_ID5PRESENT_MASK 0x8000 32955 #define SERDESID_SERDESID4_ID5PRESENT_ALIGN 0 32956 #define SERDESID_SERDESID4_ID5PRESENT_BITS 1 32957 #define SERDESID_SERDESID4_ID5PRESENT_SHIFT 15 32958 32959 /* SerdesID :: serdesID4 :: process [14:13] */ 32960 #define SERDESID_SERDESID4_PROCESS_MASK 0x6000 32961 #define SERDESID_SERDESID4_PROCESS_ALIGN 0 32962 #define SERDESID_SERDESID4_PROCESS_BITS 2 32963 #define SERDESID_SERDESID4_PROCESS_SHIFT 13 32964 32965 /* SerdesID :: serdesID4 :: CL82 [12:12] */ 32966 #define SERDESID_SERDESID4_CL82_MASK 0x1000 32967 #define SERDESID_SERDESID4_CL82_ALIGN 0 32968 #define SERDESID_SERDESID4_CL82_BITS 1 32969 #define SERDESID_SERDESID4_CL82_SHIFT 12 32970 32971 /* SerdesID :: serdesID4 :: CL78 [11:11] */ 32972 #define SERDESID_SERDESID4_CL78_MASK 0x0800 32973 #define SERDESID_SERDESID4_CL78_ALIGN 0 32974 #define SERDESID_SERDESID4_CL78_BITS 1 32975 #define SERDESID_SERDESID4_CL78_SHIFT 11 32976 32977 /* SerdesID :: serdesID4 :: CL74 [10:10] */ 32978 #define SERDESID_SERDESID4_CL74_MASK 0x0400 32979 #define SERDESID_SERDESID4_CL74_ALIGN 0 32980 #define SERDESID_SERDESID4_CL74_BITS 1 32981 #define SERDESID_SERDESID4_CL74_SHIFT 10 32982 32983 /* SerdesID :: serdesID4 :: CL72 [09:09] */ 32984 #define SERDESID_SERDESID4_CL72_MASK 0x0200 32985 #define SERDESID_SERDESID4_CL72_ALIGN 0 32986 #define SERDESID_SERDESID4_CL72_BITS 1 32987 #define SERDESID_SERDESID4_CL72_SHIFT 9 32988 32989 /* SerdesID :: serdesID4 :: CL49 [08:08] */ 32990 #define SERDESID_SERDESID4_CL49_MASK 0x0100 32991 #define SERDESID_SERDESID4_CL49_ALIGN 0 32992 #define SERDESID_SERDESID4_CL49_BITS 1 32993 #define SERDESID_SERDESID4_CL49_SHIFT 8 32994 32995 /* SerdesID :: serdesID4 :: DXGXS [07:07] */ 32996 #define SERDESID_SERDESID4_DXGXS_MASK 0x0080 32997 #define SERDESID_SERDESID4_DXGXS_ALIGN 0 32998 #define SERDESID_SERDESID4_DXGXS_BITS 1 32999 #define SERDESID_SERDESID4_DXGXS_SHIFT 7 33000 33001 /* SerdesID :: serdesID4 :: X2 [06:06] */ 33002 #define SERDESID_SERDESID4_X2_MASK 0x0040 33003 #define SERDESID_SERDESID4_X2_ALIGN 0 33004 #define SERDESID_SERDESID4_X2_BITS 1 33005 #define SERDESID_SERDESID4_X2_SHIFT 6 33006 33007 /* SerdesID :: serdesID4 :: R2 [05:05] */ 33008 #define SERDESID_SERDESID4_R2_MASK 0x0020 33009 #define SERDESID_SERDESID4_R2_ALIGN 0 33010 #define SERDESID_SERDESID4_R2_BITS 1 33011 #define SERDESID_SERDESID4_R2_SHIFT 5 33012 33013 /* SerdesID :: serdesID4 :: UC [04:04] */ 33014 #define SERDESID_SERDESID4_UC_MASK 0x0010 33015 #define SERDESID_SERDESID4_UC_ALIGN 0 33016 #define SERDESID_SERDESID4_UC_BITS 1 33017 #define SERDESID_SERDESID4_UC_SHIFT 4 33018 33019 /* SerdesID :: serdesID4 :: reserved0 [03:00] */ 33020 #define SERDESID_SERDESID4_RESERVED0_MASK 0x000f 33021 #define SERDESID_SERDESID4_RESERVED0_ALIGN 0 33022 #define SERDESID_SERDESID4_RESERVED0_BITS 4 33023 #define SERDESID_SERDESID4_RESERVED0_SHIFT 0 33024 33025 33026 /**************************************************************************** 33027 * Warpcore_USER_Digital3 33028 */ 33029 /**************************************************************************** 33030 * Digital3 :: digctl_3_0 33031 */ 33032 /* Digital3 :: digctl_3_0 :: an_lostLink_cnt [15:00] */ 33033 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_MASK 0xffff 33034 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_ALIGN 0 33035 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_BITS 16 33036 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_SHIFT 0 33037 33038 33039 /**************************************************************************** 33040 * Digital3 :: digctl_3_1 33041 */ 33042 /* Digital3 :: digctl_3_1 :: an_switch_cnt [15:00] */ 33043 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_MASK 0xffff 33044 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_ALIGN 0 33045 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_BITS 16 33046 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_SHIFT 0 33047 33048 33049 /**************************************************************************** 33050 * Digital3 :: digctl_3_2 33051 */ 33052 /* Digital3 :: digctl_3_2 :: an_link_cnt [15:00] */ 33053 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_MASK 0xffff 33054 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_ALIGN 0 33055 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_BITS 16 33056 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_SHIFT 0 33057 33058 33059 /**************************************************************************** 33060 * Digital3 :: digctl_3_3 33061 */ 33062 /* Digital3 :: digctl_3_3 :: an_switch_cnt2 [15:08] */ 33063 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_MASK 0xff00 33064 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_ALIGN 0 33065 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_BITS 8 33066 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_SHIFT 8 33067 33068 /* Digital3 :: digctl_3_3 :: an_link_cnt2 [07:00] */ 33069 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_MASK 0x00ff 33070 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_ALIGN 0 33071 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_BITS 8 33072 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_SHIFT 0 33073 33074 33075 /**************************************************************************** 33076 * Digital3 :: digctl_3_4 33077 */ 33078 /* Digital3 :: digctl_3_4 :: mp_number [15:05] */ 33079 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_MASK 0xffe0 33080 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_ALIGN 0 33081 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_BITS 11 33082 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_SHIFT 5 33083 33084 /* Digital3 :: digctl_3_4 :: no_fail_cnt [04:04] */ 33085 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_MASK 0x0010 33086 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_ALIGN 0 33087 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_BITS 1 33088 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_SHIFT 4 33089 33090 /* Digital3 :: digctl_3_4 :: an_fail_cnt [03:00] */ 33091 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_MASK 0x000f 33092 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_ALIGN 0 33093 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_BITS 4 33094 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_SHIFT 0 33095 33096 33097 /**************************************************************************** 33098 * Digital3 :: digctl_3_5 33099 */ 33100 /* Digital3 :: digctl_3_5 :: an_ignoreLink_cnt [15:00] */ 33101 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_MASK 0xffff 33102 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_ALIGN 0 33103 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_BITS 16 33104 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_SHIFT 0 33105 33106 33107 /**************************************************************************** 33108 * Digital3 :: digctl_3_6 33109 */ 33110 /* Digital3 :: digctl_3_6 :: an_lostLink_cnt2 [15:08] */ 33111 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_MASK 0xff00 33112 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_ALIGN 0 33113 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_BITS 8 33114 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_SHIFT 8 33115 33116 /* Digital3 :: digctl_3_6 :: an_ingoreLink_cnt2 [07:00] */ 33117 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_MASK 0x00ff 33118 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_ALIGN 0 33119 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_BITS 8 33120 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_SHIFT 0 33121 33122 33123 /**************************************************************************** 33124 * Digital3 :: TPOUT_1 33125 */ 33126 /* Digital3 :: TPOUT_1 :: tpout1 [15:00] */ 33127 #define DIGITAL3_TPOUT_1_TPOUT1_MASK 0xffff 33128 #define DIGITAL3_TPOUT_1_TPOUT1_ALIGN 0 33129 #define DIGITAL3_TPOUT_1_TPOUT1_BITS 16 33130 #define DIGITAL3_TPOUT_1_TPOUT1_SHIFT 0 33131 33132 33133 /**************************************************************************** 33134 * Digital3 :: TPOUT_2 33135 */ 33136 /* Digital3 :: TPOUT_2 :: tpout2 [15:00] */ 33137 #define DIGITAL3_TPOUT_2_TPOUT2_MASK 0xffff 33138 #define DIGITAL3_TPOUT_2_TPOUT2_ALIGN 0 33139 #define DIGITAL3_TPOUT_2_TPOUT2_BITS 16 33140 #define DIGITAL3_TPOUT_2_TPOUT2_SHIFT 0 33141 33142 33143 /**************************************************************************** 33144 * Digital3 :: UP1 33145 */ 33146 /* Digital3 :: UP1 :: reserved0 [15:11] */ 33147 #define DIGITAL3_UP1_RESERVED0_MASK 0xf800 33148 #define DIGITAL3_UP1_RESERVED0_ALIGN 0 33149 #define DIGITAL3_UP1_RESERVED0_BITS 5 33150 #define DIGITAL3_UP1_RESERVED0_SHIFT 11 33151 33152 /* Digital3 :: UP1 :: dataRate_20GX4 [10:10] */ 33153 #define DIGITAL3_UP1_DATARATE_20GX4_MASK 0x0400 33154 #define DIGITAL3_UP1_DATARATE_20GX4_ALIGN 0 33155 #define DIGITAL3_UP1_DATARATE_20GX4_BITS 1 33156 #define DIGITAL3_UP1_DATARATE_20GX4_SHIFT 10 33157 33158 /* Digital3 :: UP1 :: dataRate_16GX4 [09:09] */ 33159 #define DIGITAL3_UP1_DATARATE_16GX4_MASK 0x0200 33160 #define DIGITAL3_UP1_DATARATE_16GX4_ALIGN 0 33161 #define DIGITAL3_UP1_DATARATE_16GX4_BITS 1 33162 #define DIGITAL3_UP1_DATARATE_16GX4_SHIFT 9 33163 33164 /* Digital3 :: UP1 :: dataRate_15GX4 [08:08] */ 33165 #define DIGITAL3_UP1_DATARATE_15GX4_MASK 0x0100 33166 #define DIGITAL3_UP1_DATARATE_15GX4_ALIGN 0 33167 #define DIGITAL3_UP1_DATARATE_15GX4_BITS 1 33168 #define DIGITAL3_UP1_DATARATE_15GX4_SHIFT 8 33169 33170 /* Digital3 :: UP1 :: dataRate_13GX4 [07:07] */ 33171 #define DIGITAL3_UP1_DATARATE_13GX4_MASK 0x0080 33172 #define DIGITAL3_UP1_DATARATE_13GX4_ALIGN 0 33173 #define DIGITAL3_UP1_DATARATE_13GX4_BITS 1 33174 #define DIGITAL3_UP1_DATARATE_13GX4_SHIFT 7 33175 33176 /* Digital3 :: UP1 :: dataRate_12p5GX4 [06:06] */ 33177 #define DIGITAL3_UP1_DATARATE_12P5GX4_MASK 0x0040 33178 #define DIGITAL3_UP1_DATARATE_12P5GX4_ALIGN 0 33179 #define DIGITAL3_UP1_DATARATE_12P5GX4_BITS 1 33180 #define DIGITAL3_UP1_DATARATE_12P5GX4_SHIFT 6 33181 33182 /* Digital3 :: UP1 :: dataRate_12GX4 [05:05] */ 33183 #define DIGITAL3_UP1_DATARATE_12GX4_MASK 0x0020 33184 #define DIGITAL3_UP1_DATARATE_12GX4_ALIGN 0 33185 #define DIGITAL3_UP1_DATARATE_12GX4_BITS 1 33186 #define DIGITAL3_UP1_DATARATE_12GX4_SHIFT 5 33187 33188 /* Digital3 :: UP1 :: dataRate_10GCX4 [04:04] */ 33189 #define DIGITAL3_UP1_DATARATE_10GCX4_MASK 0x0010 33190 #define DIGITAL3_UP1_DATARATE_10GCX4_ALIGN 0 33191 #define DIGITAL3_UP1_DATARATE_10GCX4_BITS 1 33192 #define DIGITAL3_UP1_DATARATE_10GCX4_SHIFT 4 33193 33194 /* Digital3 :: UP1 :: dataRate_10GX4 [03:03] */ 33195 #define DIGITAL3_UP1_DATARATE_10GX4_MASK 0x0008 33196 #define DIGITAL3_UP1_DATARATE_10GX4_ALIGN 0 33197 #define DIGITAL3_UP1_DATARATE_10GX4_BITS 1 33198 #define DIGITAL3_UP1_DATARATE_10GX4_SHIFT 3 33199 33200 /* Digital3 :: UP1 :: dataRate_6GX4 [02:02] */ 33201 #define DIGITAL3_UP1_DATARATE_6GX4_MASK 0x0004 33202 #define DIGITAL3_UP1_DATARATE_6GX4_ALIGN 0 33203 #define DIGITAL3_UP1_DATARATE_6GX4_BITS 1 33204 #define DIGITAL3_UP1_DATARATE_6GX4_SHIFT 2 33205 33206 /* Digital3 :: UP1 :: dataRate_5GX4 [01:01] */ 33207 #define DIGITAL3_UP1_DATARATE_5GX4_MASK 0x0002 33208 #define DIGITAL3_UP1_DATARATE_5GX4_ALIGN 0 33209 #define DIGITAL3_UP1_DATARATE_5GX4_BITS 1 33210 #define DIGITAL3_UP1_DATARATE_5GX4_SHIFT 1 33211 33212 /* Digital3 :: UP1 :: dataRate_2p5GX1 [00:00] */ 33213 #define DIGITAL3_UP1_DATARATE_2P5GX1_MASK 0x0001 33214 #define DIGITAL3_UP1_DATARATE_2P5GX1_ALIGN 0 33215 #define DIGITAL3_UP1_DATARATE_2P5GX1_BITS 1 33216 #define DIGITAL3_UP1_DATARATE_2P5GX1_SHIFT 0 33217 33218 33219 /**************************************************************************** 33220 * Digital3 :: UP2 33221 */ 33222 /* Digital3 :: UP2 :: reserved0 [15:11] */ 33223 #define DIGITAL3_UP2_RESERVED0_MASK 0xf800 33224 #define DIGITAL3_UP2_RESERVED0_ALIGN 0 33225 #define DIGITAL3_UP2_RESERVED0_BITS 5 33226 #define DIGITAL3_UP2_RESERVED0_SHIFT 11 33227 33228 /* Digital3 :: UP2 :: valid [10:10] */ 33229 #define DIGITAL3_UP2_VALID_MASK 0x0400 33230 #define DIGITAL3_UP2_VALID_ALIGN 0 33231 #define DIGITAL3_UP2_VALID_BITS 1 33232 #define DIGITAL3_UP2_VALID_SHIFT 10 33233 33234 /* Digital3 :: UP2 :: preemphasis [09:06] */ 33235 #define DIGITAL3_UP2_PREEMPHASIS_MASK 0x03c0 33236 #define DIGITAL3_UP2_PREEMPHASIS_ALIGN 0 33237 #define DIGITAL3_UP2_PREEMPHASIS_BITS 4 33238 #define DIGITAL3_UP2_PREEMPHASIS_SHIFT 6 33239 33240 /* Digital3 :: UP2 :: idriver [05:03] */ 33241 #define DIGITAL3_UP2_IDRIVER_MASK 0x0038 33242 #define DIGITAL3_UP2_IDRIVER_ALIGN 0 33243 #define DIGITAL3_UP2_IDRIVER_BITS 3 33244 #define DIGITAL3_UP2_IDRIVER_SHIFT 3 33245 33246 /* Digital3 :: UP2 :: ipredriver [02:00] */ 33247 #define DIGITAL3_UP2_IPREDRIVER_MASK 0x0007 33248 #define DIGITAL3_UP2_IPREDRIVER_ALIGN 0 33249 #define DIGITAL3_UP2_IPREDRIVER_BITS 3 33250 #define DIGITAL3_UP2_IPREDRIVER_SHIFT 0 33251 33252 33253 /**************************************************************************** 33254 * Digital3 :: UP3 33255 */ 33256 /* Digital3 :: UP3 :: reserved0 [15:11] */ 33257 #define DIGITAL3_UP3_RESERVED0_MASK 0xf800 33258 #define DIGITAL3_UP3_RESERVED0_ALIGN 0 33259 #define DIGITAL3_UP3_RESERVED0_BITS 5 33260 #define DIGITAL3_UP3_RESERVED0_SHIFT 11 33261 33262 /* Digital3 :: UP3 :: last [10:10] */ 33263 #define DIGITAL3_UP3_LAST_MASK 0x0400 33264 #define DIGITAL3_UP3_LAST_ALIGN 0 33265 #define DIGITAL3_UP3_LAST_BITS 1 33266 #define DIGITAL3_UP3_LAST_SHIFT 10 33267 33268 /* Digital3 :: UP3 :: dataRate_21GX4 [09:09] */ 33269 #define DIGITAL3_UP3_DATARATE_21GX4_MASK 0x0200 33270 #define DIGITAL3_UP3_DATARATE_21GX4_ALIGN 0 33271 #define DIGITAL3_UP3_DATARATE_21GX4_BITS 1 33272 #define DIGITAL3_UP3_DATARATE_21GX4_SHIFT 9 33273 33274 /* Digital3 :: UP3 :: dataRate_25p45GX4 [08:08] */ 33275 #define DIGITAL3_UP3_DATARATE_25P45GX4_MASK 0x0100 33276 #define DIGITAL3_UP3_DATARATE_25P45GX4_ALIGN 0 33277 #define DIGITAL3_UP3_DATARATE_25P45GX4_BITS 1 33278 #define DIGITAL3_UP3_DATARATE_25P45GX4_SHIFT 8 33279 33280 /* Digital3 :: UP3 :: dataRate_31p5G [07:07] */ 33281 #define DIGITAL3_UP3_DATARATE_31P5G_MASK 0x0080 33282 #define DIGITAL3_UP3_DATARATE_31P5G_ALIGN 0 33283 #define DIGITAL3_UP3_DATARATE_31P5G_BITS 1 33284 #define DIGITAL3_UP3_DATARATE_31P5G_SHIFT 7 33285 33286 /* Digital3 :: UP3 :: reserved1 [06:06] */ 33287 #define DIGITAL3_UP3_RESERVED1_MASK 0x0040 33288 #define DIGITAL3_UP3_RESERVED1_ALIGN 0 33289 #define DIGITAL3_UP3_RESERVED1_BITS 1 33290 #define DIGITAL3_UP3_RESERVED1_SHIFT 6 33291 33292 /* Digital3 :: UP3 :: dataRate_40G [05:05] */ 33293 #define DIGITAL3_UP3_DATARATE_40G_MASK 0x0020 33294 #define DIGITAL3_UP3_DATARATE_40G_ALIGN 0 33295 #define DIGITAL3_UP3_DATARATE_40G_BITS 1 33296 #define DIGITAL3_UP3_DATARATE_40G_SHIFT 5 33297 33298 /* Digital3 :: UP3 :: reserved2 [04:03] */ 33299 #define DIGITAL3_UP3_RESERVED2_MASK 0x0018 33300 #define DIGITAL3_UP3_RESERVED2_ALIGN 0 33301 #define DIGITAL3_UP3_RESERVED2_BITS 2 33302 #define DIGITAL3_UP3_RESERVED2_SHIFT 3 33303 33304 /* Digital3 :: UP3 :: Cl72 [02:02] */ 33305 #define DIGITAL3_UP3_CL72_MASK 0x0004 33306 #define DIGITAL3_UP3_CL72_ALIGN 0 33307 #define DIGITAL3_UP3_CL72_BITS 1 33308 #define DIGITAL3_UP3_CL72_SHIFT 2 33309 33310 /* Digital3 :: UP3 :: FEC [01:01] */ 33311 #define DIGITAL3_UP3_FEC_MASK 0x0002 33312 #define DIGITAL3_UP3_FEC_ALIGN 0 33313 #define DIGITAL3_UP3_FEC_BITS 1 33314 #define DIGITAL3_UP3_FEC_SHIFT 1 33315 33316 /* Digital3 :: UP3 :: HiGig2 [00:00] */ 33317 #define DIGITAL3_UP3_HIGIG2_MASK 0x0001 33318 #define DIGITAL3_UP3_HIGIG2_ALIGN 0 33319 #define DIGITAL3_UP3_HIGIG2_BITS 1 33320 #define DIGITAL3_UP3_HIGIG2_SHIFT 0 33321 33322 33323 /**************************************************************************** 33324 * Digital3 :: LP_UP1 33325 */ 33326 /* Digital3 :: LP_UP1 :: reserved0 [15:11] */ 33327 #define DIGITAL3_LP_UP1_RESERVED0_MASK 0xf800 33328 #define DIGITAL3_LP_UP1_RESERVED0_ALIGN 0 33329 #define DIGITAL3_LP_UP1_RESERVED0_BITS 5 33330 #define DIGITAL3_LP_UP1_RESERVED0_SHIFT 11 33331 33332 /* Digital3 :: LP_UP1 :: dataRate_20GX4 [10:10] */ 33333 #define DIGITAL3_LP_UP1_DATARATE_20GX4_MASK 0x0400 33334 #define DIGITAL3_LP_UP1_DATARATE_20GX4_ALIGN 0 33335 #define DIGITAL3_LP_UP1_DATARATE_20GX4_BITS 1 33336 #define DIGITAL3_LP_UP1_DATARATE_20GX4_SHIFT 10 33337 33338 /* Digital3 :: LP_UP1 :: dataRate_16GX4 [09:09] */ 33339 #define DIGITAL3_LP_UP1_DATARATE_16GX4_MASK 0x0200 33340 #define DIGITAL3_LP_UP1_DATARATE_16GX4_ALIGN 0 33341 #define DIGITAL3_LP_UP1_DATARATE_16GX4_BITS 1 33342 #define DIGITAL3_LP_UP1_DATARATE_16GX4_SHIFT 9 33343 33344 /* Digital3 :: LP_UP1 :: dataRate_15GX4 [08:08] */ 33345 #define DIGITAL3_LP_UP1_DATARATE_15GX4_MASK 0x0100 33346 #define DIGITAL3_LP_UP1_DATARATE_15GX4_ALIGN 0 33347 #define DIGITAL3_LP_UP1_DATARATE_15GX4_BITS 1 33348 #define DIGITAL3_LP_UP1_DATARATE_15GX4_SHIFT 8 33349 33350 /* Digital3 :: LP_UP1 :: dataRate_13GX4 [07:07] */ 33351 #define DIGITAL3_LP_UP1_DATARATE_13GX4_MASK 0x0080 33352 #define DIGITAL3_LP_UP1_DATARATE_13GX4_ALIGN 0 33353 #define DIGITAL3_LP_UP1_DATARATE_13GX4_BITS 1 33354 #define DIGITAL3_LP_UP1_DATARATE_13GX4_SHIFT 7 33355 33356 /* Digital3 :: LP_UP1 :: dataRate_12p5GX4 [06:06] */ 33357 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_MASK 0x0040 33358 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_ALIGN 0 33359 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_BITS 1 33360 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_SHIFT 6 33361 33362 /* Digital3 :: LP_UP1 :: dataRate_12GX4 [05:05] */ 33363 #define DIGITAL3_LP_UP1_DATARATE_12GX4_MASK 0x0020 33364 #define DIGITAL3_LP_UP1_DATARATE_12GX4_ALIGN 0 33365 #define DIGITAL3_LP_UP1_DATARATE_12GX4_BITS 1 33366 #define DIGITAL3_LP_UP1_DATARATE_12GX4_SHIFT 5 33367 33368 /* Digital3 :: LP_UP1 :: dataRate_10GCX4 [04:04] */ 33369 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_MASK 0x0010 33370 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_ALIGN 0 33371 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_BITS 1 33372 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_SHIFT 4 33373 33374 /* Digital3 :: LP_UP1 :: dataRate_10GX4 [03:03] */ 33375 #define DIGITAL3_LP_UP1_DATARATE_10GX4_MASK 0x0008 33376 #define DIGITAL3_LP_UP1_DATARATE_10GX4_ALIGN 0 33377 #define DIGITAL3_LP_UP1_DATARATE_10GX4_BITS 1 33378 #define DIGITAL3_LP_UP1_DATARATE_10GX4_SHIFT 3 33379 33380 /* Digital3 :: LP_UP1 :: dataRate_6GX4 [02:02] */ 33381 #define DIGITAL3_LP_UP1_DATARATE_6GX4_MASK 0x0004 33382 #define DIGITAL3_LP_UP1_DATARATE_6GX4_ALIGN 0 33383 #define DIGITAL3_LP_UP1_DATARATE_6GX4_BITS 1 33384 #define DIGITAL3_LP_UP1_DATARATE_6GX4_SHIFT 2 33385 33386 /* Digital3 :: LP_UP1 :: dataRate_5GX4 [01:01] */ 33387 #define DIGITAL3_LP_UP1_DATARATE_5GX4_MASK 0x0002 33388 #define DIGITAL3_LP_UP1_DATARATE_5GX4_ALIGN 0 33389 #define DIGITAL3_LP_UP1_DATARATE_5GX4_BITS 1 33390 #define DIGITAL3_LP_UP1_DATARATE_5GX4_SHIFT 1 33391 33392 /* Digital3 :: LP_UP1 :: dataRate_2p5GX1 [00:00] */ 33393 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_MASK 0x0001 33394 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_ALIGN 0 33395 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_BITS 1 33396 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_SHIFT 0 33397 33398 33399 /**************************************************************************** 33400 * Digital3 :: LP_UP2 33401 */ 33402 /* Digital3 :: LP_UP2 :: reserved0 [15:11] */ 33403 #define DIGITAL3_LP_UP2_RESERVED0_MASK 0xf800 33404 #define DIGITAL3_LP_UP2_RESERVED0_ALIGN 0 33405 #define DIGITAL3_LP_UP2_RESERVED0_BITS 5 33406 #define DIGITAL3_LP_UP2_RESERVED0_SHIFT 11 33407 33408 /* Digital3 :: LP_UP2 :: valid [10:10] */ 33409 #define DIGITAL3_LP_UP2_VALID_MASK 0x0400 33410 #define DIGITAL3_LP_UP2_VALID_ALIGN 0 33411 #define DIGITAL3_LP_UP2_VALID_BITS 1 33412 #define DIGITAL3_LP_UP2_VALID_SHIFT 10 33413 33414 /* Digital3 :: LP_UP2 :: preemphasis [09:06] */ 33415 #define DIGITAL3_LP_UP2_PREEMPHASIS_MASK 0x03c0 33416 #define DIGITAL3_LP_UP2_PREEMPHASIS_ALIGN 0 33417 #define DIGITAL3_LP_UP2_PREEMPHASIS_BITS 4 33418 #define DIGITAL3_LP_UP2_PREEMPHASIS_SHIFT 6 33419 33420 /* Digital3 :: LP_UP2 :: idriver [05:03] */ 33421 #define DIGITAL3_LP_UP2_IDRIVER_MASK 0x0038 33422 #define DIGITAL3_LP_UP2_IDRIVER_ALIGN 0 33423 #define DIGITAL3_LP_UP2_IDRIVER_BITS 3 33424 #define DIGITAL3_LP_UP2_IDRIVER_SHIFT 3 33425 33426 /* Digital3 :: LP_UP2 :: ipredriver [02:00] */ 33427 #define DIGITAL3_LP_UP2_IPREDRIVER_MASK 0x0007 33428 #define DIGITAL3_LP_UP2_IPREDRIVER_ALIGN 0 33429 #define DIGITAL3_LP_UP2_IPREDRIVER_BITS 3 33430 #define DIGITAL3_LP_UP2_IPREDRIVER_SHIFT 0 33431 33432 33433 /**************************************************************************** 33434 * Digital3 :: LP_UP3 33435 */ 33436 /* Digital3 :: LP_UP3 :: reserved0 [15:11] */ 33437 #define DIGITAL3_LP_UP3_RESERVED0_MASK 0xf800 33438 #define DIGITAL3_LP_UP3_RESERVED0_ALIGN 0 33439 #define DIGITAL3_LP_UP3_RESERVED0_BITS 5 33440 #define DIGITAL3_LP_UP3_RESERVED0_SHIFT 11 33441 33442 /* Digital3 :: LP_UP3 :: last [10:10] */ 33443 #define DIGITAL3_LP_UP3_LAST_MASK 0x0400 33444 #define DIGITAL3_LP_UP3_LAST_ALIGN 0 33445 #define DIGITAL3_LP_UP3_LAST_BITS 1 33446 #define DIGITAL3_LP_UP3_LAST_SHIFT 10 33447 33448 /* Digital3 :: LP_UP3 :: dataRate_21GX4 [09:09] */ 33449 #define DIGITAL3_LP_UP3_DATARATE_21GX4_MASK 0x0200 33450 #define DIGITAL3_LP_UP3_DATARATE_21GX4_ALIGN 0 33451 #define DIGITAL3_LP_UP3_DATARATE_21GX4_BITS 1 33452 #define DIGITAL3_LP_UP3_DATARATE_21GX4_SHIFT 9 33453 33454 /* Digital3 :: LP_UP3 :: dataRate_25p45GX4 [08:08] */ 33455 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_MASK 0x0100 33456 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_ALIGN 0 33457 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_BITS 1 33458 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_SHIFT 8 33459 33460 /* Digital3 :: LP_UP3 :: dataRate_31p5G [07:07] */ 33461 #define DIGITAL3_LP_UP3_DATARATE_31P5G_MASK 0x0080 33462 #define DIGITAL3_LP_UP3_DATARATE_31P5G_ALIGN 0 33463 #define DIGITAL3_LP_UP3_DATARATE_31P5G_BITS 1 33464 #define DIGITAL3_LP_UP3_DATARATE_31P5G_SHIFT 7 33465 33466 /* Digital3 :: LP_UP3 :: reserved1 [06:06] */ 33467 #define DIGITAL3_LP_UP3_RESERVED1_MASK 0x0040 33468 #define DIGITAL3_LP_UP3_RESERVED1_ALIGN 0 33469 #define DIGITAL3_LP_UP3_RESERVED1_BITS 1 33470 #define DIGITAL3_LP_UP3_RESERVED1_SHIFT 6 33471 33472 /* Digital3 :: LP_UP3 :: dataRate_40G [05:05] */ 33473 #define DIGITAL3_LP_UP3_DATARATE_40G_MASK 0x0020 33474 #define DIGITAL3_LP_UP3_DATARATE_40G_ALIGN 0 33475 #define DIGITAL3_LP_UP3_DATARATE_40G_BITS 1 33476 #define DIGITAL3_LP_UP3_DATARATE_40G_SHIFT 5 33477 33478 /* Digital3 :: LP_UP3 :: reserved2 [04:03] */ 33479 #define DIGITAL3_LP_UP3_RESERVED2_MASK 0x0018 33480 #define DIGITAL3_LP_UP3_RESERVED2_ALIGN 0 33481 #define DIGITAL3_LP_UP3_RESERVED2_BITS 2 33482 #define DIGITAL3_LP_UP3_RESERVED2_SHIFT 3 33483 33484 /* Digital3 :: LP_UP3 :: Cl72 [02:02] */ 33485 #define DIGITAL3_LP_UP3_CL72_MASK 0x0004 33486 #define DIGITAL3_LP_UP3_CL72_ALIGN 0 33487 #define DIGITAL3_LP_UP3_CL72_BITS 1 33488 #define DIGITAL3_LP_UP3_CL72_SHIFT 2 33489 33490 /* Digital3 :: LP_UP3 :: FEC [01:01] */ 33491 #define DIGITAL3_LP_UP3_FEC_MASK 0x0002 33492 #define DIGITAL3_LP_UP3_FEC_ALIGN 0 33493 #define DIGITAL3_LP_UP3_FEC_BITS 1 33494 #define DIGITAL3_LP_UP3_FEC_SHIFT 1 33495 33496 /* Digital3 :: LP_UP3 :: HiGig2 [00:00] */ 33497 #define DIGITAL3_LP_UP3_HIGIG2_MASK 0x0001 33498 #define DIGITAL3_LP_UP3_HIGIG2_ALIGN 0 33499 #define DIGITAL3_LP_UP3_HIGIG2_BITS 1 33500 #define DIGITAL3_LP_UP3_HIGIG2_SHIFT 0 33501 33502 33503 /**************************************************************************** 33504 * Warpcore_USER_Digital4 33505 */ 33506 /**************************************************************************** 33507 * Digital4 :: MiscRxStatus 33508 */ 33509 /* union - case statusSelect0 [15:00] */ 33510 /* Digital4 :: MiscRxStatus :: capture_NP_lh [15:15] */ 33511 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK 0x8000 33512 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN 0 33513 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS 1 33514 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT 15 33515 33516 /* Digital4 :: MiscRxStatus :: teton_brk_link_lh [14:14] */ 33517 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000 33518 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0 33519 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1 33520 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14 33521 33522 /* Digital4 :: MiscRxStatus :: UP3_lh [13:13] */ 33523 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK 0x2000 33524 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN 0 33525 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS 1 33526 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT 13 33527 33528 /* Digital4 :: MiscRxStatus :: MP5_lh [12:12] */ 33529 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK 0x1000 33530 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN 0 33531 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS 1 33532 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT 12 33533 33534 /* Digital4 :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */ 33535 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800 33536 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0 33537 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1 33538 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11 33539 33540 /* Digital4 :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */ 33541 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400 33542 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0 33543 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1 33544 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10 33545 33546 /* Digital4 :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */ 33547 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200 33548 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0 33549 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1 33550 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9 33551 33552 /* Digital4 :: MiscRxStatus :: invalidSeq_lh [08:08] */ 33553 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK 0x0100 33554 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN 0 33555 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS 1 33556 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT 8 33557 33558 /* Digital4 :: MiscRxStatus :: nullMP_lh [07:07] */ 33559 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK 0x0080 33560 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN 0 33561 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS 1 33562 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT 7 33563 33564 /* Digital4 :: MiscRxStatus :: remotePhyMP_lh [06:06] */ 33565 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK 0x0040 33566 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN 0 33567 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS 1 33568 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT 6 33569 33570 /* Digital4 :: MiscRxStatus :: nonMatchingMP_lh [05:05] */ 33571 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK 0x0020 33572 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0 33573 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS 1 33574 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5 33575 33576 /* Digital4 :: MiscRxStatus :: over1gMP_lh [04:04] */ 33577 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK 0x0010 33578 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN 0 33579 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS 1 33580 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT 4 33581 33582 /* Digital4 :: MiscRxStatus :: rx_config_is_0_lh [03:03] */ 33583 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008 33584 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0 33585 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1 33586 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3 33587 33588 /* Digital4 :: MiscRxStatus :: np_toggle_err_lh [02:02] */ 33589 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK 0x0004 33590 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0 33591 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS 1 33592 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2 33593 33594 /* Digital4 :: MiscRxStatus :: mr_np_lh [01:01] */ 33595 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK 0x0002 33596 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN 0 33597 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS 1 33598 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT 1 33599 33600 /* Digital4 :: MiscRxStatus :: mr_bp_lh [00:00] */ 33601 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK 0x0001 33602 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN 0 33603 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS 1 33604 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT 0 33605 33606 33607 /* union - case statusSelect1 [15:00] */ 33608 /* Digital4 :: MiscRxStatus :: reserved0 [15:04] */ 33609 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK 0xfff0 33610 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN 0 33611 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS 12 33612 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT 4 33613 33614 /* Digital4 :: MiscRxStatus :: np_count [03:00] */ 33615 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK 0x000f 33616 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN 0 33617 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS 4 33618 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT 0 33619 33620 33621 /* union - case statusSelect2 [15:00] */ 33622 /* Digital4 :: MiscRxStatus :: reserved0 [15:06] */ 33623 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK 0xffc0 33624 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN 0 33625 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS 10 33626 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT 6 33627 33628 /* Digital4 :: MiscRxStatus :: remote_phy_enable [05:05] */ 33629 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020 33630 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0 33631 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1 33632 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5 33633 33634 /* Digital4 :: MiscRxStatus :: det_teton_mode [04:04] */ 33635 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK 0x0010 33636 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN 0 33637 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS 1 33638 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT 4 33639 33640 /* Digital4 :: MiscRxStatus :: cu_linkdown [03:03] */ 33641 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK 0x0008 33642 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN 0 33643 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS 1 33644 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT 3 33645 33646 /* Digital4 :: MiscRxStatus :: cu_resolution_error [02:02] */ 33647 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004 33648 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0 33649 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1 33650 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2 33651 33652 /* Digital4 :: MiscRxStatus :: remotePhy_autosel [01:01] */ 33653 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002 33654 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0 33655 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1 33656 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1 33657 33658 /* Digital4 :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */ 33659 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001 33660 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0 33661 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1 33662 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0 33663 33664 33665 /* union - case statusSelect3 [15:00] */ 33666 /* Digital4 :: MiscRxStatus :: reserved0 [15:06] */ 33667 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_MASK 0xffc0 33668 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_ALIGN 0 33669 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_BITS 10 33670 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_SHIFT 6 33671 33672 /* Digital4 :: MiscRxStatus :: sgmii_selector_mismatch [05:05] */ 33673 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_MASK 0x0020 33674 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_ALIGN 0 33675 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_BITS 1 33676 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_SHIFT 5 33677 33678 /* Digital4 :: MiscRxStatus :: autoneg_enable_ov [04:04] */ 33679 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_MASK 0x0010 33680 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_ALIGN 0 33681 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_BITS 1 33682 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_SHIFT 4 33683 33684 /* Digital4 :: MiscRxStatus :: s_mr_an_enable [03:03] */ 33685 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_MASK 0x0008 33686 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_ALIGN 0 33687 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_BITS 1 33688 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_SHIFT 3 33689 33690 /* Digital4 :: MiscRxStatus :: s_cl73_rslv_KX4 [02:02] */ 33691 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_MASK 0x0004 33692 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_ALIGN 0 33693 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_BITS 1 33694 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_SHIFT 2 33695 33696 /* Digital4 :: MiscRxStatus :: s_cl73_rslv_KX [01:01] */ 33697 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_MASK 0x0002 33698 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_ALIGN 0 33699 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_BITS 1 33700 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_SHIFT 1 33701 33702 /* Digital4 :: MiscRxStatus :: KX_detect [00:00] */ 33703 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_MASK 0x0001 33704 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_ALIGN 0 33705 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_BITS 1 33706 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_SHIFT 0 33707 33708 33709 33710 /**************************************************************************** 33711 * Digital4 :: lp_basePage 33712 */ 33713 /* Digital4 :: lp_basePage :: lp_basePage [15:00] */ 33714 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_MASK 0xffff 33715 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_ALIGN 0 33716 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_BITS 16 33717 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_SHIFT 0 33718 33719 33720 /**************************************************************************** 33721 * Digital4 :: lp_nextPage_0 33722 */ 33723 /* Digital4 :: lp_nextPage_0 :: lp_nextPage_0 [15:00] */ 33724 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_MASK 0xffff 33725 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_ALIGN 0 33726 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_BITS 16 33727 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_SHIFT 0 33728 33729 33730 /**************************************************************************** 33731 * Digital4 :: lp_nextPage_1 33732 */ 33733 /* Digital4 :: lp_nextPage_1 :: lp_nextPage_1 [15:00] */ 33734 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_MASK 0xffff 33735 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_ALIGN 0 33736 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_BITS 16 33737 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_SHIFT 0 33738 33739 33740 /**************************************************************************** 33741 * Digital4 :: lp_nextPage_2 33742 */ 33743 /* Digital4 :: lp_nextPage_2 :: lp_nextPage_2 [15:00] */ 33744 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_MASK 0xffff 33745 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_ALIGN 0 33746 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_BITS 16 33747 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_SHIFT 0 33748 33749 33750 /**************************************************************************** 33751 * Digital4 :: lp_nextPage_3 33752 */ 33753 /* Digital4 :: lp_nextPage_3 :: lp_nextPage_3 [15:00] */ 33754 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_MASK 0xffff 33755 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_ALIGN 0 33756 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_BITS 16 33757 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_SHIFT 0 33758 33759 33760 /**************************************************************************** 33761 * Digital4 :: lp_nextPage_4 33762 */ 33763 /* Digital4 :: lp_nextPage_4 :: lp_nextPage_4 [15:00] */ 33764 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_MASK 0xffff 33765 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_ALIGN 0 33766 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_BITS 16 33767 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_SHIFT 0 33768 33769 33770 /**************************************************************************** 33771 * Digital4 :: rp_nextPage_0 33772 */ 33773 /* Digital4 :: rp_nextPage_0 :: reserved0 [15:15] */ 33774 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_MASK 0x8000 33775 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_ALIGN 0 33776 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_BITS 1 33777 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_SHIFT 15 33778 33779 /* Digital4 :: rp_nextPage_0 :: extra_page_disable [14:14] */ 33780 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_MASK 0x4000 33781 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_ALIGN 0 33782 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_BITS 1 33783 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_SHIFT 14 33784 33785 /* Digital4 :: rp_nextPage_0 :: null_page_enable [13:13] */ 33786 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_MASK 0x2000 33787 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_ALIGN 0 33788 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_BITS 1 33789 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_SHIFT 13 33790 33791 /* Digital4 :: rp_nextPage_0 :: over_1g_disable [12:12] */ 33792 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_MASK 0x1000 33793 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_ALIGN 0 33794 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_BITS 1 33795 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_SHIFT 12 33796 33797 /* Digital4 :: rp_nextPage_0 :: remote_phy_enable [11:11] */ 33798 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_MASK 0x0800 33799 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_ALIGN 0 33800 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_BITS 1 33801 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_SHIFT 11 33802 33803 /* Digital4 :: rp_nextPage_0 :: rp_nextPage_0 [10:00] */ 33804 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_MASK 0x07ff 33805 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_ALIGN 0 33806 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_BITS 11 33807 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_SHIFT 0 33808 33809 33810 /**************************************************************************** 33811 * Digital4 :: rp_nextPage_1 33812 */ 33813 /* Digital4 :: rp_nextPage_1 :: reserved0 [15:15] */ 33814 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_MASK 0x8000 33815 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_ALIGN 0 33816 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_BITS 1 33817 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_SHIFT 15 33818 33819 /* Digital4 :: rp_nextPage_1 :: remotePhy_linkDown_rstrt_disable [14:14] */ 33820 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_MASK 0x4000 33821 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_ALIGN 0 33822 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_BITS 1 33823 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_SHIFT 14 33824 33825 /* Digital4 :: rp_nextPage_1 :: remotePhy_rsltn_err_rstrt_disable [13:13] */ 33826 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_MASK 0x2000 33827 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_ALIGN 0 33828 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_BITS 1 33829 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_SHIFT 13 33830 33831 /* Digital4 :: rp_nextPage_1 :: remotePhy_resolution_disable [12:12] */ 33832 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_MASK 0x1000 33833 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_ALIGN 0 33834 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_BITS 1 33835 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_SHIFT 12 33836 33837 /* Digital4 :: rp_nextPage_1 :: remotePhy_decode_enable [11:11] */ 33838 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_MASK 0x0800 33839 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_ALIGN 0 33840 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_BITS 1 33841 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_SHIFT 11 33842 33843 /* Digital4 :: rp_nextPage_1 :: rp_nextPage_1 [10:00] */ 33844 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_MASK 0x07ff 33845 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_ALIGN 0 33846 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_BITS 11 33847 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_SHIFT 0 33848 33849 33850 /**************************************************************************** 33851 * Digital4 :: rp_nextPage_2 33852 */ 33853 /* Digital4 :: rp_nextPage_2 :: reserved0 [15:12] */ 33854 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_MASK 0xf000 33855 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_ALIGN 0 33856 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_BITS 4 33857 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_SHIFT 12 33858 33859 /* Digital4 :: rp_nextPage_2 :: remPhy_NP_clr_disable [11:11] */ 33860 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_MASK 0x0800 33861 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_ALIGN 0 33862 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_BITS 1 33863 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_SHIFT 11 33864 33865 /* Digital4 :: rp_nextPage_2 :: rp_nextPage_2 [10:00] */ 33866 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_MASK 0x07ff 33867 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_ALIGN 0 33868 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_BITS 11 33869 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_SHIFT 0 33870 33871 33872 /**************************************************************************** 33873 * Digital4 :: rp_nextPage_3 33874 */ 33875 /* Digital4 :: rp_nextPage_3 :: reserved0 [15:11] */ 33876 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_MASK 0xf800 33877 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_ALIGN 0 33878 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_BITS 5 33879 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_SHIFT 11 33880 33881 /* Digital4 :: rp_nextPage_3 :: rp_nextPage_3 [10:00] */ 33882 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_MASK 0x07ff 33883 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_ALIGN 0 33884 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_BITS 11 33885 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_SHIFT 0 33886 33887 33888 /**************************************************************************** 33889 * Digital4 :: rp_nextPage_4 33890 */ 33891 /* Digital4 :: rp_nextPage_4 :: reserved0 [15:11] */ 33892 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_MASK 0xf800 33893 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_ALIGN 0 33894 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_BITS 5 33895 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_SHIFT 11 33896 33897 /* Digital4 :: rp_nextPage_4 :: rp_nextPage_4 [10:00] */ 33898 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_MASK 0x07ff 33899 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_ALIGN 0 33900 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_BITS 11 33901 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_SHIFT 0 33902 33903 33904 /**************************************************************************** 33905 * Digital4 :: Misc3 33906 */ 33907 /* Digital4 :: Misc3 :: ind_40bitif [15:15] */ 33908 #define DIGITAL4_MISC3_IND_40BITIF_MASK 0x8000 33909 #define DIGITAL4_MISC3_IND_40BITIF_ALIGN 0 33910 #define DIGITAL4_MISC3_IND_40BITIF_BITS 1 33911 #define DIGITAL4_MISC3_IND_40BITIF_SHIFT 15 33912 33913 /* Digital4 :: Misc3 :: cl49_ed66_en_override [14:14] */ 33914 #define DIGITAL4_MISC3_CL49_ED66_EN_OVERRIDE_MASK 0x4000 33915 #define DIGITAL4_MISC3_CL49_ED66_EN_OVERRIDE_ALIGN 0 33916 #define DIGITAL4_MISC3_CL49_ED66_EN_OVERRIDE_BITS 1 33917 #define DIGITAL4_MISC3_CL49_ED66_EN_OVERRIDE_SHIFT 14 33918 33919 /* Digital4 :: Misc3 :: cl49_ed66_en_val [13:13] */ 33920 #define DIGITAL4_MISC3_CL49_ED66_EN_VAL_MASK 0x2000 33921 #define DIGITAL4_MISC3_CL49_ED66_EN_VAL_ALIGN 0 33922 #define DIGITAL4_MISC3_CL49_ED66_EN_VAL_BITS 1 33923 #define DIGITAL4_MISC3_CL49_ED66_EN_VAL_SHIFT 13 33924 33925 /* Digital4 :: Misc3 :: fifo_fsm_cya [12:12] */ 33926 #define DIGITAL4_MISC3_FIFO_FSM_CYA_MASK 0x1000 33927 #define DIGITAL4_MISC3_FIFO_FSM_CYA_ALIGN 0 33928 #define DIGITAL4_MISC3_FIFO_FSM_CYA_BITS 1 33929 #define DIGITAL4_MISC3_FIFO_FSM_CYA_SHIFT 12 33930 33931 /* Digital4 :: Misc3 :: rxck_mii_override_val [11:11] */ 33932 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_MASK 0x0800 33933 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_ALIGN 0 33934 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_BITS 1 33935 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_SHIFT 11 33936 33937 /* Digital4 :: Misc3 :: rxck_mii_override [10:10] */ 33938 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_MASK 0x0400 33939 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_ALIGN 0 33940 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_BITS 1 33941 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_SHIFT 10 33942 33943 /* Digital4 :: Misc3 :: fifo_ipg_cya [09:09] */ 33944 #define DIGITAL4_MISC3_FIFO_IPG_CYA_MASK 0x0200 33945 #define DIGITAL4_MISC3_FIFO_IPG_CYA_ALIGN 0 33946 #define DIGITAL4_MISC3_FIFO_IPG_CYA_BITS 1 33947 #define DIGITAL4_MISC3_FIFO_IPG_CYA_SHIFT 9 33948 33949 /* Digital4 :: Misc3 :: scr_en_per_lane [08:08] */ 33950 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_MASK 0x0100 33951 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_ALIGN 0 33952 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_BITS 1 33953 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_SHIFT 8 33954 33955 /* Digital4 :: Misc3 :: force_speed_b5 [07:07] */ 33956 #define DIGITAL4_MISC3_FORCE_SPEED_B5_MASK 0x0080 33957 #define DIGITAL4_MISC3_FORCE_SPEED_B5_ALIGN 0 33958 #define DIGITAL4_MISC3_FORCE_SPEED_B5_BITS 1 33959 #define DIGITAL4_MISC3_FORCE_SPEED_B5_SHIFT 7 33960 33961 /* Digital4 :: Misc3 :: laneDisable [06:06] */ 33962 #define DIGITAL4_MISC3_LANEDISABLE_MASK 0x0040 33963 #define DIGITAL4_MISC3_LANEDISABLE_ALIGN 0 33964 #define DIGITAL4_MISC3_LANEDISABLE_BITS 1 33965 #define DIGITAL4_MISC3_LANEDISABLE_SHIFT 6 33966 33967 /* Digital4 :: Misc3 :: fifo_err_cya2 [05:05] */ 33968 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_MASK 0x0020 33969 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_ALIGN 0 33970 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_BITS 1 33971 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_SHIFT 5 33972 33973 /* Digital4 :: Misc3 :: disable_pcs_tx_r [04:04] */ 33974 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_MASK 0x0010 33975 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_ALIGN 0 33976 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_BITS 1 33977 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_SHIFT 4 33978 33979 /* Digital4 :: Misc3 :: disable_pcs_tx_force_r [03:03] */ 33980 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_MASK 0x0008 33981 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_ALIGN 0 33982 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_BITS 1 33983 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_SHIFT 3 33984 33985 /* Digital4 :: Misc3 :: tbi_mode_force_r [02:02] */ 33986 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_MASK 0x0004 33987 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_ALIGN 0 33988 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_BITS 1 33989 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_SHIFT 2 33990 33991 /* Digital4 :: Misc3 :: rxSigdetPwrdn_override_val [01:01] */ 33992 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_MASK 0x0002 33993 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_ALIGN 0 33994 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_BITS 1 33995 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_SHIFT 1 33996 33997 /* Digital4 :: Misc3 :: rxSigdetPwrdn_override [00:00] */ 33998 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_MASK 0x0001 33999 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_ALIGN 0 34000 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_BITS 1 34001 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_SHIFT 0 34002 34003 34004 /**************************************************************************** 34005 * Digital4 :: Misc4 34006 */ 34007 /* Digital4 :: Misc4 :: auto_pcs_type_sel_en [15:15] */ 34008 #define DIGITAL4_MISC4_AUTO_PCS_TYPE_SEL_EN_MASK 0x8000 34009 #define DIGITAL4_MISC4_AUTO_PCS_TYPE_SEL_EN_ALIGN 0 34010 #define DIGITAL4_MISC4_AUTO_PCS_TYPE_SEL_EN_BITS 1 34011 #define DIGITAL4_MISC4_AUTO_PCS_TYPE_SEL_EN_SHIFT 15 34012 34013 /* Digital4 :: Misc4 :: scr_en_over [14:14] */ 34014 #define DIGITAL4_MISC4_SCR_EN_OVER_MASK 0x4000 34015 #define DIGITAL4_MISC4_SCR_EN_OVER_ALIGN 0 34016 #define DIGITAL4_MISC4_SCR_EN_OVER_BITS 1 34017 #define DIGITAL4_MISC4_SCR_EN_OVER_SHIFT 14 34018 34019 /* Digital4 :: Misc4 :: div33_clk_use_cya [13:13] */ 34020 #define DIGITAL4_MISC4_DIV33_CLK_USE_CYA_MASK 0x2000 34021 #define DIGITAL4_MISC4_DIV33_CLK_USE_CYA_ALIGN 0 34022 #define DIGITAL4_MISC4_DIV33_CLK_USE_CYA_BITS 1 34023 #define DIGITAL4_MISC4_DIV33_CLK_USE_CYA_SHIFT 13 34024 34025 /* Digital4 :: Misc4 :: os3_en_val [12:12] */ 34026 #define DIGITAL4_MISC4_OS3_EN_VAL_MASK 0x1000 34027 #define DIGITAL4_MISC4_OS3_EN_VAL_ALIGN 0 34028 #define DIGITAL4_MISC4_OS3_EN_VAL_BITS 1 34029 #define DIGITAL4_MISC4_OS3_EN_VAL_SHIFT 12 34030 34031 /* Digital4 :: Misc4 :: os3_en_override [11:11] */ 34032 #define DIGITAL4_MISC4_OS3_EN_OVERRIDE_MASK 0x0800 34033 #define DIGITAL4_MISC4_OS3_EN_OVERRIDE_ALIGN 0 34034 #define DIGITAL4_MISC4_OS3_EN_OVERRIDE_BITS 1 34035 #define DIGITAL4_MISC4_OS3_EN_OVERRIDE_SHIFT 11 34036 34037 /* Digital4 :: Misc4 :: decouple_actual_speed [10:10] */ 34038 #define DIGITAL4_MISC4_DECOUPLE_ACTUAL_SPEED_MASK 0x0400 34039 #define DIGITAL4_MISC4_DECOUPLE_ACTUAL_SPEED_ALIGN 0 34040 #define DIGITAL4_MISC4_DECOUPLE_ACTUAL_SPEED_BITS 1 34041 #define DIGITAL4_MISC4_DECOUPLE_ACTUAL_SPEED_SHIFT 10 34042 34043 /* Digital4 :: Misc4 :: fx_mode_rx_pre [09:09] */ 34044 #define DIGITAL4_MISC4_FX_MODE_RX_PRE_MASK 0x0200 34045 #define DIGITAL4_MISC4_FX_MODE_RX_PRE_ALIGN 0 34046 #define DIGITAL4_MISC4_FX_MODE_RX_PRE_BITS 1 34047 #define DIGITAL4_MISC4_FX_MODE_RX_PRE_SHIFT 9 34048 34049 /* Digital4 :: Misc4 :: fiber_select_rx_pre [08:08] */ 34050 #define DIGITAL4_MISC4_FIBER_SELECT_RX_PRE_MASK 0x0100 34051 #define DIGITAL4_MISC4_FIBER_SELECT_RX_PRE_ALIGN 0 34052 #define DIGITAL4_MISC4_FIBER_SELECT_RX_PRE_BITS 1 34053 #define DIGITAL4_MISC4_FIBER_SELECT_RX_PRE_SHIFT 8 34054 34055 /* Digital4 :: Misc4 :: force_speed_rx_pre [07:02] */ 34056 #define DIGITAL4_MISC4_FORCE_SPEED_RX_PRE_MASK 0x00fc 34057 #define DIGITAL4_MISC4_FORCE_SPEED_RX_PRE_ALIGN 0 34058 #define DIGITAL4_MISC4_FORCE_SPEED_RX_PRE_BITS 6 34059 #define DIGITAL4_MISC4_FORCE_SPEED_RX_PRE_SHIFT 2 34060 34061 /* Digital4 :: Misc4 :: reg0_forced_speed_rx_pre [01:00] */ 34062 #define DIGITAL4_MISC4_REG0_FORCED_SPEED_RX_PRE_MASK 0x0003 34063 #define DIGITAL4_MISC4_REG0_FORCED_SPEED_RX_PRE_ALIGN 0 34064 #define DIGITAL4_MISC4_REG0_FORCED_SPEED_RX_PRE_BITS 2 34065 #define DIGITAL4_MISC4_REG0_FORCED_SPEED_RX_PRE_SHIFT 0 34066 34067 34068 /**************************************************************************** 34069 * Digital4 :: Misc5 34070 */ 34071 /* Digital4 :: Misc5 :: LPI_en_rx [15:15] */ 34072 #define DIGITAL4_MISC5_LPI_EN_RX_MASK 0x8000 34073 #define DIGITAL4_MISC5_LPI_EN_RX_ALIGN 0 34074 #define DIGITAL4_MISC5_LPI_EN_RX_BITS 1 34075 #define DIGITAL4_MISC5_LPI_EN_RX_SHIFT 15 34076 34077 /* Digital4 :: Misc5 :: LPI_en_tx [14:14] */ 34078 #define DIGITAL4_MISC5_LPI_EN_TX_MASK 0x4000 34079 #define DIGITAL4_MISC5_LPI_EN_TX_ALIGN 0 34080 #define DIGITAL4_MISC5_LPI_EN_TX_BITS 1 34081 #define DIGITAL4_MISC5_LPI_EN_TX_SHIFT 14 34082 34083 /* Digital4 :: Misc5 :: tgen_data_sel [13:13] */ 34084 #define DIGITAL4_MISC5_TGEN_DATA_SEL_MASK 0x2000 34085 #define DIGITAL4_MISC5_TGEN_DATA_SEL_ALIGN 0 34086 #define DIGITAL4_MISC5_TGEN_DATA_SEL_BITS 1 34087 #define DIGITAL4_MISC5_TGEN_DATA_SEL_SHIFT 13 34088 34089 /* Digital4 :: Misc5 :: tgen_cx4 [12:12] */ 34090 #define DIGITAL4_MISC5_TGEN_CX4_MASK 0x1000 34091 #define DIGITAL4_MISC5_TGEN_CX4_ALIGN 0 34092 #define DIGITAL4_MISC5_TGEN_CX4_BITS 1 34093 #define DIGITAL4_MISC5_TGEN_CX4_SHIFT 12 34094 34095 /* Digital4 :: Misc5 :: tgen_link [11:11] */ 34096 #define DIGITAL4_MISC5_TGEN_LINK_MASK 0x0800 34097 #define DIGITAL4_MISC5_TGEN_LINK_ALIGN 0 34098 #define DIGITAL4_MISC5_TGEN_LINK_BITS 1 34099 #define DIGITAL4_MISC5_TGEN_LINK_SHIFT 11 34100 34101 /* Digital4 :: Misc5 :: tgen_tmsel [10:08] */ 34102 #define DIGITAL4_MISC5_TGEN_TMSEL_MASK 0x0700 34103 #define DIGITAL4_MISC5_TGEN_TMSEL_ALIGN 0 34104 #define DIGITAL4_MISC5_TGEN_TMSEL_BITS 3 34105 #define DIGITAL4_MISC5_TGEN_TMSEL_SHIFT 8 34106 34107 /* Digital4 :: Misc5 :: force_speed_b7 [07:07] */ 34108 #define DIGITAL4_MISC5_FORCE_SPEED_B7_MASK 0x0080 34109 #define DIGITAL4_MISC5_FORCE_SPEED_B7_ALIGN 0 34110 #define DIGITAL4_MISC5_FORCE_SPEED_B7_BITS 1 34111 #define DIGITAL4_MISC5_FORCE_SPEED_B7_SHIFT 7 34112 34113 /* Digital4 :: Misc5 :: force_speed_b6 [06:06] */ 34114 #define DIGITAL4_MISC5_FORCE_SPEED_B6_MASK 0x0040 34115 #define DIGITAL4_MISC5_FORCE_SPEED_B6_ALIGN 0 34116 #define DIGITAL4_MISC5_FORCE_SPEED_B6_BITS 1 34117 #define DIGITAL4_MISC5_FORCE_SPEED_B6_SHIFT 6 34118 34119 /* Digital4 :: Misc5 :: r2_cl49_ed66_en_val [05:05] */ 34120 #define DIGITAL4_MISC5_R2_CL49_ED66_EN_VAL_MASK 0x0020 34121 #define DIGITAL4_MISC5_R2_CL49_ED66_EN_VAL_ALIGN 0 34122 #define DIGITAL4_MISC5_R2_CL49_ED66_EN_VAL_BITS 1 34123 #define DIGITAL4_MISC5_R2_CL49_ED66_EN_VAL_SHIFT 5 34124 34125 /* Digital4 :: Misc5 :: r2_cl49_ed66_en_override [04:04] */ 34126 #define DIGITAL4_MISC5_R2_CL49_ED66_EN_OVERRIDE_MASK 0x0010 34127 #define DIGITAL4_MISC5_R2_CL49_ED66_EN_OVERRIDE_ALIGN 0 34128 #define DIGITAL4_MISC5_R2_CL49_ED66_EN_OVERRIDE_BITS 1 34129 #define DIGITAL4_MISC5_R2_CL49_ED66_EN_OVERRIDE_SHIFT 4 34130 34131 /* Digital4 :: Misc5 :: rchk_en [03:03] */ 34132 #define DIGITAL4_MISC5_RCHK_EN_MASK 0x0008 34133 #define DIGITAL4_MISC5_RCHK_EN_ALIGN 0 34134 #define DIGITAL4_MISC5_RCHK_EN_BITS 1 34135 #define DIGITAL4_MISC5_RCHK_EN_SHIFT 3 34136 34137 /* Digital4 :: Misc5 :: rchk_tmsel [02:00] */ 34138 #define DIGITAL4_MISC5_RCHK_TMSEL_MASK 0x0007 34139 #define DIGITAL4_MISC5_RCHK_TMSEL_ALIGN 0 34140 #define DIGITAL4_MISC5_RCHK_TMSEL_BITS 3 34141 #define DIGITAL4_MISC5_RCHK_TMSEL_SHIFT 0 34142 34143 34144 /**************************************************************************** 34145 * Warpcore_USER_Digital5 34146 */ 34147 /**************************************************************************** 34148 * Digital5 :: linkcnt_cl72_msb 34149 */ 34150 /* Digital5 :: linkcnt_cl72_msb :: reserved_for_eco0 [15:08] */ 34151 #define DIGITAL5_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_MASK 0xff00 34152 #define DIGITAL5_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_ALIGN 0 34153 #define DIGITAL5_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_BITS 8 34154 #define DIGITAL5_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_SHIFT 8 34155 34156 /* Digital5 :: linkcnt_cl72_msb :: link_cnt_cl72_msbB [07:00] */ 34157 #define DIGITAL5_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_MASK 0x00ff 34158 #define DIGITAL5_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_ALIGN 0 34159 #define DIGITAL5_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_BITS 8 34160 #define DIGITAL5_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_SHIFT 0 34161 34162 34163 /**************************************************************************** 34164 * Digital5 :: linkcnt_cl72_lsb 34165 */ 34166 /* Digital5 :: linkcnt_cl72_lsb :: link_cnt_cl72_lsbB [15:00] */ 34167 #define DIGITAL5_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_MASK 0xffff 34168 #define DIGITAL5_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_ALIGN 0 34169 #define DIGITAL5_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_BITS 16 34170 #define DIGITAL5_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_SHIFT 0 34171 34172 34173 /**************************************************************************** 34174 * Digital5 :: LP_UP4 34175 */ 34176 /* Digital5 :: LP_UP4 :: reserved0 [15:11] */ 34177 #define DIGITAL5_LP_UP4_RESERVED0_MASK 0xf800 34178 #define DIGITAL5_LP_UP4_RESERVED0_ALIGN 0 34179 #define DIGITAL5_LP_UP4_RESERVED0_BITS 5 34180 #define DIGITAL5_LP_UP4_RESERVED0_SHIFT 11 34181 34182 /* Digital5 :: LP_UP4 :: last [10:10] */ 34183 #define DIGITAL5_LP_UP4_LAST_MASK 0x0400 34184 #define DIGITAL5_LP_UP4_LAST_ALIGN 0 34185 #define DIGITAL5_LP_UP4_LAST_BITS 1 34186 #define DIGITAL5_LP_UP4_LAST_SHIFT 10 34187 34188 /* Digital5 :: LP_UP4 :: reserved1 [09:08] */ 34189 #define DIGITAL5_LP_UP4_RESERVED1_MASK 0x0300 34190 #define DIGITAL5_LP_UP4_RESERVED1_ALIGN 0 34191 #define DIGITAL5_LP_UP4_RESERVED1_BITS 2 34192 #define DIGITAL5_LP_UP4_RESERVED1_SHIFT 8 34193 34194 /* Digital5 :: LP_UP4 :: dataRate_15p75G_dxgxs [07:07] */ 34195 #define DIGITAL5_LP_UP4_DATARATE_15P75G_DXGXS_MASK 0x0080 34196 #define DIGITAL5_LP_UP4_DATARATE_15P75G_DXGXS_ALIGN 0 34197 #define DIGITAL5_LP_UP4_DATARATE_15P75G_DXGXS_BITS 1 34198 #define DIGITAL5_LP_UP4_DATARATE_15P75G_DXGXS_SHIFT 7 34199 34200 /* Digital5 :: LP_UP4 :: dataRate_20G_dxgxs [06:06] */ 34201 #define DIGITAL5_LP_UP4_DATARATE_20G_DXGXS_MASK 0x0040 34202 #define DIGITAL5_LP_UP4_DATARATE_20G_DXGXS_ALIGN 0 34203 #define DIGITAL5_LP_UP4_DATARATE_20G_DXGXS_BITS 1 34204 #define DIGITAL5_LP_UP4_DATARATE_20G_DXGXS_SHIFT 6 34205 34206 /* Digital5 :: LP_UP4 :: dataRate_20Gh_dxgxs [05:05] */ 34207 #define DIGITAL5_LP_UP4_DATARATE_20GH_DXGXS_MASK 0x0020 34208 #define DIGITAL5_LP_UP4_DATARATE_20GH_DXGXS_ALIGN 0 34209 #define DIGITAL5_LP_UP4_DATARATE_20GH_DXGXS_BITS 1 34210 #define DIGITAL5_LP_UP4_DATARATE_20GH_DXGXS_SHIFT 5 34211 34212 /* Digital5 :: LP_UP4 :: dataRate_12p7G_dxgxs [04:04] */ 34213 #define DIGITAL5_LP_UP4_DATARATE_12P7G_DXGXS_MASK 0x0010 34214 #define DIGITAL5_LP_UP4_DATARATE_12P7G_DXGXS_ALIGN 0 34215 #define DIGITAL5_LP_UP4_DATARATE_12P7G_DXGXS_BITS 1 34216 #define DIGITAL5_LP_UP4_DATARATE_12P7G_DXGXS_SHIFT 4 34217 34218 /* Digital5 :: LP_UP4 :: dataRate_10p5G_dxgxs [03:03] */ 34219 #define DIGITAL5_LP_UP4_DATARATE_10P5G_DXGXS_MASK 0x0008 34220 #define DIGITAL5_LP_UP4_DATARATE_10P5G_DXGXS_ALIGN 0 34221 #define DIGITAL5_LP_UP4_DATARATE_10P5G_DXGXS_BITS 1 34222 #define DIGITAL5_LP_UP4_DATARATE_10P5G_DXGXS_SHIFT 3 34223 34224 /* Digital5 :: LP_UP4 :: dataRate_10G_dxgxs [02:02] */ 34225 #define DIGITAL5_LP_UP4_DATARATE_10G_DXGXS_MASK 0x0004 34226 #define DIGITAL5_LP_UP4_DATARATE_10G_DXGXS_ALIGN 0 34227 #define DIGITAL5_LP_UP4_DATARATE_10G_DXGXS_BITS 1 34228 #define DIGITAL5_LP_UP4_DATARATE_10G_DXGXS_SHIFT 2 34229 34230 /* Digital5 :: LP_UP4 :: dataRate_10Gh_dxgxs [01:01] */ 34231 #define DIGITAL5_LP_UP4_DATARATE_10GH_DXGXS_MASK 0x0002 34232 #define DIGITAL5_LP_UP4_DATARATE_10GH_DXGXS_ALIGN 0 34233 #define DIGITAL5_LP_UP4_DATARATE_10GH_DXGXS_BITS 1 34234 #define DIGITAL5_LP_UP4_DATARATE_10GH_DXGXS_SHIFT 1 34235 34236 /* Digital5 :: LP_UP4 :: dataRate_20G [00:00] */ 34237 #define DIGITAL5_LP_UP4_DATARATE_20G_MASK 0x0001 34238 #define DIGITAL5_LP_UP4_DATARATE_20G_ALIGN 0 34239 #define DIGITAL5_LP_UP4_DATARATE_20G_BITS 1 34240 #define DIGITAL5_LP_UP4_DATARATE_20G_SHIFT 0 34241 34242 34243 /**************************************************************************** 34244 * Digital5 :: LP_UP5 34245 */ 34246 /* Digital5 :: LP_UP5 :: reserved0 [15:11] */ 34247 #define DIGITAL5_LP_UP5_RESERVED0_MASK 0xf800 34248 #define DIGITAL5_LP_UP5_RESERVED0_ALIGN 0 34249 #define DIGITAL5_LP_UP5_RESERVED0_BITS 5 34250 #define DIGITAL5_LP_UP5_RESERVED0_SHIFT 11 34251 34252 /* Digital5 :: LP_UP5 :: last [10:10] */ 34253 #define DIGITAL5_LP_UP5_LAST_MASK 0x0400 34254 #define DIGITAL5_LP_UP5_LAST_ALIGN 0 34255 #define DIGITAL5_LP_UP5_LAST_BITS 1 34256 #define DIGITAL5_LP_UP5_LAST_SHIFT 10 34257 34258 /* Digital5 :: LP_UP5 :: reserved1 [09:00] */ 34259 #define DIGITAL5_LP_UP5_RESERVED1_MASK 0x03ff 34260 #define DIGITAL5_LP_UP5_RESERVED1_ALIGN 0 34261 #define DIGITAL5_LP_UP5_RESERVED1_BITS 10 34262 #define DIGITAL5_LP_UP5_RESERVED1_SHIFT 0 34263 34264 34265 /**************************************************************************** 34266 * Digital5 :: LPI_hyst 34267 */ 34268 /* Digital5 :: LPI_hyst :: reserved_for_eco0 [15:04] */ 34269 #define DIGITAL5_LPI_HYST_RESERVED_FOR_ECO0_MASK 0xfff0 34270 #define DIGITAL5_LPI_HYST_RESERVED_FOR_ECO0_ALIGN 0 34271 #define DIGITAL5_LPI_HYST_RESERVED_FOR_ECO0_BITS 12 34272 #define DIGITAL5_LPI_HYST_RESERVED_FOR_ECO0_SHIFT 4 34273 34274 /* Digital5 :: LPI_hyst :: LPI_hyst_cnt [03:01] */ 34275 #define DIGITAL5_LPI_HYST_LPI_HYST_CNT_MASK 0x000e 34276 #define DIGITAL5_LPI_HYST_LPI_HYST_CNT_ALIGN 0 34277 #define DIGITAL5_LPI_HYST_LPI_HYST_CNT_BITS 3 34278 #define DIGITAL5_LPI_HYST_LPI_HYST_CNT_SHIFT 1 34279 34280 /* Digital5 :: LPI_hyst :: LPI_hyst_en [00:00] */ 34281 #define DIGITAL5_LPI_HYST_LPI_HYST_EN_MASK 0x0001 34282 #define DIGITAL5_LPI_HYST_LPI_HYST_EN_ALIGN 0 34283 #define DIGITAL5_LPI_HYST_LPI_HYST_EN_BITS 1 34284 #define DIGITAL5_LPI_HYST_LPI_HYST_EN_SHIFT 0 34285 34286 34287 /**************************************************************************** 34288 * Digital5 :: Misc6 34289 */ 34290 /* Digital5 :: Misc6 :: reset_rx_asic [15:15] */ 34291 #define DIGITAL5_MISC6_RESET_RX_ASIC_MASK 0x8000 34292 #define DIGITAL5_MISC6_RESET_RX_ASIC_ALIGN 0 34293 #define DIGITAL5_MISC6_RESET_RX_ASIC_BITS 1 34294 #define DIGITAL5_MISC6_RESET_RX_ASIC_SHIFT 15 34295 34296 /* Digital5 :: Misc6 :: reset_tx_asic [14:14] */ 34297 #define DIGITAL5_MISC6_RESET_TX_ASIC_MASK 0x4000 34298 #define DIGITAL5_MISC6_RESET_TX_ASIC_ALIGN 0 34299 #define DIGITAL5_MISC6_RESET_TX_ASIC_BITS 1 34300 #define DIGITAL5_MISC6_RESET_TX_ASIC_SHIFT 14 34301 34302 /* Digital5 :: Misc6 :: pmd_energy_detect_dgltch_en [13:13] */ 34303 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_EN_MASK 0x2000 34304 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_EN_ALIGN 0 34305 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_EN_BITS 1 34306 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_EN_SHIFT 13 34307 34308 /* Digital5 :: Misc6 :: pmd_energy_detect_dgltch_sel [12:11] */ 34309 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_SEL_MASK 0x1800 34310 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_SEL_ALIGN 0 34311 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_SEL_BITS 2 34312 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_SEL_SHIFT 11 34313 34314 /* Digital5 :: Misc6 :: pcs1g_ckgate_en [10:10] */ 34315 #define DIGITAL5_MISC6_PCS1G_CKGATE_EN_MASK 0x0400 34316 #define DIGITAL5_MISC6_PCS1G_CKGATE_EN_ALIGN 0 34317 #define DIGITAL5_MISC6_PCS1G_CKGATE_EN_BITS 1 34318 #define DIGITAL5_MISC6_PCS1G_CKGATE_EN_SHIFT 10 34319 34320 /* Digital5 :: Misc6 :: ind_80bitif [09:09] */ 34321 #define DIGITAL5_MISC6_IND_80BITIF_MASK 0x0200 34322 #define DIGITAL5_MISC6_IND_80BITIF_ALIGN 0 34323 #define DIGITAL5_MISC6_IND_80BITIF_BITS 1 34324 #define DIGITAL5_MISC6_IND_80BITIF_SHIFT 9 34325 34326 /* Digital5 :: Misc6 :: rx_os8_frst_SM [08:08] */ 34327 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_MASK 0x0100 34328 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_ALIGN 0 34329 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_BITS 1 34330 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_SHIFT 8 34331 34332 /* Digital5 :: Misc6 :: use_brcm6466_31500_cya [07:07] */ 34333 #define DIGITAL5_MISC6_USE_BRCM6466_31500_CYA_MASK 0x0080 34334 #define DIGITAL5_MISC6_USE_BRCM6466_31500_CYA_ALIGN 0 34335 #define DIGITAL5_MISC6_USE_BRCM6466_31500_CYA_BITS 1 34336 #define DIGITAL5_MISC6_USE_BRCM6466_31500_CYA_SHIFT 7 34337 34338 /* Digital5 :: Misc6 :: cx4_sigdet_filt_all_speed [06:06] */ 34339 #define DIGITAL5_MISC6_CX4_SIGDET_FILT_ALL_SPEED_MASK 0x0040 34340 #define DIGITAL5_MISC6_CX4_SIGDET_FILT_ALL_SPEED_ALIGN 0 34341 #define DIGITAL5_MISC6_CX4_SIGDET_FILT_ALL_SPEED_BITS 1 34342 #define DIGITAL5_MISC6_CX4_SIGDET_FILT_ALL_SPEED_SHIFT 6 34343 34344 /* Digital5 :: Misc6 :: pcs_type_sel_1000x_cya [05:05] */ 34345 #define DIGITAL5_MISC6_PCS_TYPE_SEL_1000X_CYA_MASK 0x0020 34346 #define DIGITAL5_MISC6_PCS_TYPE_SEL_1000X_CYA_ALIGN 0 34347 #define DIGITAL5_MISC6_PCS_TYPE_SEL_1000X_CYA_BITS 1 34348 #define DIGITAL5_MISC6_PCS_TYPE_SEL_1000X_CYA_SHIFT 5 34349 34350 /* Digital5 :: Misc6 :: rx_os8_os3_alt_bits_cya [04:04] */ 34351 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_MASK 0x0010 34352 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_ALIGN 0 34353 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_BITS 1 34354 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_SHIFT 4 34355 34356 /* Digital5 :: Misc6 :: an_completeTrap [03:03] */ 34357 #define DIGITAL5_MISC6_AN_COMPLETETRAP_MASK 0x0008 34358 #define DIGITAL5_MISC6_AN_COMPLETETRAP_ALIGN 0 34359 #define DIGITAL5_MISC6_AN_COMPLETETRAP_BITS 1 34360 #define DIGITAL5_MISC6_AN_COMPLETETRAP_SHIFT 3 34361 34362 /* Digital5 :: Misc6 :: an_wait4linkTrap [02:02] */ 34363 #define DIGITAL5_MISC6_AN_WAIT4LINKTRAP_MASK 0x0004 34364 #define DIGITAL5_MISC6_AN_WAIT4LINKTRAP_ALIGN 0 34365 #define DIGITAL5_MISC6_AN_WAIT4LINKTRAP_BITS 1 34366 #define DIGITAL5_MISC6_AN_WAIT4LINKTRAP_SHIFT 2 34367 34368 /* Digital5 :: Misc6 :: tx_os8_afrst_en [01:01] */ 34369 #define DIGITAL5_MISC6_TX_OS8_AFRST_EN_MASK 0x0002 34370 #define DIGITAL5_MISC6_TX_OS8_AFRST_EN_ALIGN 0 34371 #define DIGITAL5_MISC6_TX_OS8_AFRST_EN_BITS 1 34372 #define DIGITAL5_MISC6_TX_OS8_AFRST_EN_SHIFT 1 34373 34374 /* Digital5 :: Misc6 :: tx_os8_frst_SM [00:00] */ 34375 #define DIGITAL5_MISC6_TX_OS8_FRST_SM_MASK 0x0001 34376 #define DIGITAL5_MISC6_TX_OS8_FRST_SM_ALIGN 0 34377 #define DIGITAL5_MISC6_TX_OS8_FRST_SM_BITS 1 34378 #define DIGITAL5_MISC6_TX_OS8_FRST_SM_SHIFT 0 34379 34380 34381 /**************************************************************************** 34382 * Digital5 :: parDetINDStatus 34383 */ 34384 /* union - case pd_stat_sel_equals_0 [15:00] */ 34385 /* Digital5 :: parDetINDStatus :: rcv100fx_lh [15:15] */ 34386 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RCV100FX_LH_MASK 0x8000 34387 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RCV100FX_LH_ALIGN 0 34388 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RCV100FX_LH_BITS 1 34389 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RCV100FX_LH_SHIFT 15 34390 34391 /* Digital5 :: parDetINDStatus :: wait4link_100fx_lh [14:14] */ 34392 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_WAIT4LINK_100FX_LH_MASK 0x4000 34393 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_WAIT4LINK_100FX_LH_ALIGN 0 34394 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_WAIT4LINK_100FX_LH_BITS 1 34395 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_WAIT4LINK_100FX_LH_SHIFT 14 34396 34397 /* Digital5 :: parDetINDStatus :: txdon_100fx_lh [13:13] */ 34398 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_TXDON_100FX_LH_MASK 0x2000 34399 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_TXDON_100FX_LH_ALIGN 0 34400 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_TXDON_100FX_LH_BITS 1 34401 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_TXDON_100FX_LH_SHIFT 13 34402 34403 /* Digital5 :: parDetINDStatus :: link_100fx_retry_lh [12:12] */ 34404 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_LINK_100FX_RETRY_LH_MASK 0x1000 34405 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_LINK_100FX_RETRY_LH_ALIGN 0 34406 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_LINK_100FX_RETRY_LH_BITS 1 34407 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_LINK_100FX_RETRY_LH_SHIFT 12 34408 34409 /* Digital5 :: parDetINDStatus :: reserved0 [11:11] */ 34410 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RESERVED0_MASK 0x0800 34411 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RESERVED0_ALIGN 0 34412 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RESERVED0_BITS 1 34413 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RESERVED0_SHIFT 11 34414 34415 /* Digital5 :: parDetINDStatus :: pd_xfi_en_rx [10:10] */ 34416 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_RX_MASK 0x0400 34417 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_RX_ALIGN 0 34418 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_RX_BITS 1 34419 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_RX_SHIFT 10 34420 34421 /* Digital5 :: parDetINDStatus :: pd_2p5g_en_rx [09:09] */ 34422 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_RX_MASK 0x0200 34423 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_RX_ALIGN 0 34424 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_RX_BITS 1 34425 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_RX_SHIFT 9 34426 34427 /* Digital5 :: parDetINDStatus :: pd_100fx_en_rx [08:08] */ 34428 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_RX_MASK 0x0100 34429 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_RX_ALIGN 0 34430 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_RX_BITS 1 34431 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_RX_SHIFT 8 34432 34433 /* Digital5 :: parDetINDStatus :: pd_link_ind [07:07] */ 34434 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_LINK_IND_MASK 0x0080 34435 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_LINK_IND_ALIGN 0 34436 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_LINK_IND_BITS 1 34437 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_LINK_IND_SHIFT 7 34438 34439 /* Digital5 :: parDetINDStatus :: pd_xfi_en_tx [06:06] */ 34440 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_TX_MASK 0x0040 34441 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_TX_ALIGN 0 34442 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_TX_BITS 1 34443 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_TX_SHIFT 6 34444 34445 /* Digital5 :: parDetINDStatus :: pd_2p5g_en_tx [05:05] */ 34446 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_TX_MASK 0x0020 34447 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_TX_ALIGN 0 34448 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_TX_BITS 1 34449 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_TX_SHIFT 5 34450 34451 /* Digital5 :: parDetINDStatus :: pd_100fx_en_tx [04:04] */ 34452 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_TX_MASK 0x0010 34453 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_TX_ALIGN 0 34454 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_TX_BITS 1 34455 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_TX_SHIFT 4 34456 34457 /* Digital5 :: parDetINDStatus :: pd_ind_txdLaneOff [03:03] */ 34458 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_IND_TXDLANEOFF_MASK 0x0008 34459 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_IND_TXDLANEOFF_ALIGN 0 34460 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_IND_TXDLANEOFF_BITS 1 34461 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_IND_TXDLANEOFF_SHIFT 3 34462 34463 /* Digital5 :: parDetINDStatus :: pd_busy [02:02] */ 34464 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_BUSY_MASK 0x0004 34465 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_BUSY_ALIGN 0 34466 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_BUSY_BITS 1 34467 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_BUSY_SHIFT 2 34468 34469 /* Digital5 :: parDetINDStatus :: pd_park_IND_an [01:01] */ 34470 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_PARK_IND_AN_MASK 0x0002 34471 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_PARK_IND_AN_ALIGN 0 34472 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_PARK_IND_AN_BITS 1 34473 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_PARK_IND_AN_SHIFT 1 34474 34475 /* Digital5 :: parDetINDStatus :: rxSeqDone [00:00] */ 34476 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RXSEQDONE_MASK 0x0001 34477 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RXSEQDONE_ALIGN 0 34478 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RXSEQDONE_BITS 1 34479 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RXSEQDONE_SHIFT 0 34480 34481 34482 /* union - case pd_stat_sel_equals_1 [15:00] */ 34483 /* Digital5 :: parDetINDStatus :: wait4lock_lh [15:15] */ 34484 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LOCK_LH_MASK 0x8000 34485 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LOCK_LH_ALIGN 0 34486 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LOCK_LH_BITS 1 34487 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LOCK_LH_SHIFT 15 34488 34489 /* Digital5 :: parDetINDStatus :: wait4sigdet_lh [14:14] */ 34490 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4SIGDET_LH_MASK 0x4000 34491 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4SIGDET_LH_ALIGN 0 34492 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4SIGDET_LH_BITS 1 34493 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4SIGDET_LH_SHIFT 14 34494 34495 /* Digital5 :: parDetINDStatus :: txdfreeze_lh [13:13] */ 34496 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDFREEZE_LH_MASK 0x2000 34497 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDFREEZE_LH_ALIGN 0 34498 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDFREEZE_LH_BITS 1 34499 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDFREEZE_LH_SHIFT 13 34500 34501 /* Digital5 :: parDetINDStatus :: rcvxfi_lh [12:12] */ 34502 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCVXFI_LH_MASK 0x1000 34503 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCVXFI_LH_ALIGN 0 34504 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCVXFI_LH_BITS 1 34505 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCVXFI_LH_SHIFT 12 34506 34507 /* Digital5 :: parDetINDStatus :: rcv2p5g_lh [11:11] */ 34508 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCV2P5G_LH_MASK 0x0800 34509 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCV2P5G_LH_ALIGN 0 34510 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCV2P5G_LH_BITS 1 34511 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCV2P5G_LH_SHIFT 11 34512 34513 /* Digital5 :: parDetINDStatus :: wait4link_xfi_lh [10:10] */ 34514 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_XFI_LH_MASK 0x0400 34515 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_XFI_LH_ALIGN 0 34516 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_XFI_LH_BITS 1 34517 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_XFI_LH_SHIFT 10 34518 34519 /* Digital5 :: parDetINDStatus :: wait4link_2p5g_lh [09:09] */ 34520 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_2P5G_LH_MASK 0x0200 34521 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_2P5G_LH_ALIGN 0 34522 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_2P5G_LH_BITS 1 34523 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_2P5G_LH_SHIFT 9 34524 34525 /* Digital5 :: parDetINDStatus :: link_xfi_retry_lh [08:08] */ 34526 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_XFI_RETRY_LH_MASK 0x0100 34527 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_XFI_RETRY_LH_ALIGN 0 34528 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_XFI_RETRY_LH_BITS 1 34529 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_XFI_RETRY_LH_SHIFT 8 34530 34531 /* Digital5 :: parDetINDStatus :: txdon_xfi_lh [07:07] */ 34532 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_XFI_LH_MASK 0x0080 34533 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_XFI_LH_ALIGN 0 34534 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_XFI_LH_BITS 1 34535 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_XFI_LH_SHIFT 7 34536 34537 /* Digital5 :: parDetINDStatus :: txdon_2p5g_lh [06:06] */ 34538 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_2P5G_LH_MASK 0x0040 34539 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_2P5G_LH_ALIGN 0 34540 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_2P5G_LH_BITS 1 34541 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_2P5G_LH_SHIFT 6 34542 34543 /* Digital5 :: parDetINDStatus :: txdon_lh [05:05] */ 34544 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_LH_MASK 0x0020 34545 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_LH_ALIGN 0 34546 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_LH_BITS 1 34547 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_LH_SHIFT 5 34548 34549 /* Digital5 :: parDetINDStatus :: lostlink_lh [04:04] */ 34550 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LOSTLINK_LH_MASK 0x0010 34551 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LOSTLINK_LH_ALIGN 0 34552 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LOSTLINK_LH_BITS 1 34553 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LOSTLINK_LH_SHIFT 4 34554 34555 /* Digital5 :: parDetINDStatus :: link_2p5g_retry_lh [03:03] */ 34556 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_2P5G_RETRY_LH_MASK 0x0008 34557 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_2P5G_RETRY_LH_ALIGN 0 34558 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_2P5G_RETRY_LH_BITS 1 34559 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_2P5G_RETRY_LH_SHIFT 3 34560 34561 /* Digital5 :: parDetINDStatus :: complete_lh [02:02] */ 34562 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_COMPLETE_LH_MASK 0x0004 34563 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_COMPLETE_LH_ALIGN 0 34564 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_COMPLETE_LH_BITS 1 34565 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_COMPLETE_LH_SHIFT 2 34566 34567 /* Digital5 :: parDetINDStatus :: fail_lh [01:01] */ 34568 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_FAIL_LH_MASK 0x0002 34569 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_FAIL_LH_ALIGN 0 34570 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_FAIL_LH_BITS 1 34571 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_FAIL_LH_SHIFT 1 34572 34573 /* Digital5 :: parDetINDStatus :: s_parDet_ind_en [00:00] */ 34574 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_S_PARDET_IND_EN_MASK 0x0001 34575 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_S_PARDET_IND_EN_ALIGN 0 34576 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_S_PARDET_IND_EN_BITS 1 34577 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_S_PARDET_IND_EN_SHIFT 0 34578 34579 34580 34581 /**************************************************************************** 34582 * Digital5 :: parDetINDControl1 34583 */ 34584 /* Digital5 :: parDetINDControl1 :: pd_parkFail [15:15] */ 34585 #define DIGITAL5_PARDETINDCONTROL1_PD_PARKFAIL_MASK 0x8000 34586 #define DIGITAL5_PARDETINDCONTROL1_PD_PARKFAIL_ALIGN 0 34587 #define DIGITAL5_PARDETINDCONTROL1_PD_PARKFAIL_BITS 1 34588 #define DIGITAL5_PARDETINDCONTROL1_PD_PARKFAIL_SHIFT 15 34589 34590 /* Digital5 :: parDetINDControl1 :: pd_sw_overide [14:14] */ 34591 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_OVERIDE_MASK 0x4000 34592 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_OVERIDE_ALIGN 0 34593 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_OVERIDE_BITS 1 34594 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_OVERIDE_SHIFT 14 34595 34596 /* Digital5 :: parDetINDControl1 :: pd_txdfreeze_en [13:13] */ 34597 #define DIGITAL5_PARDETINDCONTROL1_PD_TXDFREEZE_EN_MASK 0x2000 34598 #define DIGITAL5_PARDETINDCONTROL1_PD_TXDFREEZE_EN_ALIGN 0 34599 #define DIGITAL5_PARDETINDCONTROL1_PD_TXDFREEZE_EN_BITS 1 34600 #define DIGITAL5_PARDETINDCONTROL1_PD_TXDFREEZE_EN_SHIFT 13 34601 34602 /* Digital5 :: parDetINDControl1 :: pd_sw_xfi_en_tx [12:12] */ 34603 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_TX_MASK 0x1000 34604 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_TX_ALIGN 0 34605 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_TX_BITS 1 34606 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_TX_SHIFT 12 34607 34608 /* Digital5 :: parDetINDControl1 :: pd_sw_2p5g_en_tx [11:11] */ 34609 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_TX_MASK 0x0800 34610 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_TX_ALIGN 0 34611 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_TX_BITS 1 34612 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_TX_SHIFT 11 34613 34614 /* Digital5 :: parDetINDControl1 :: pd_sw_100fx_en_tx [10:10] */ 34615 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_TX_MASK 0x0400 34616 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_TX_ALIGN 0 34617 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_TX_BITS 1 34618 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_TX_SHIFT 10 34619 34620 /* Digital5 :: parDetINDControl1 :: pd_sw_txdOff [09:09] */ 34621 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_TXDOFF_MASK 0x0200 34622 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_TXDOFF_ALIGN 0 34623 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_TXDOFF_BITS 1 34624 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_TXDOFF_SHIFT 9 34625 34626 /* Digital5 :: parDetINDControl1 :: pd_sw_100fx_en_rx [08:08] */ 34627 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_RX_MASK 0x0100 34628 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_RX_ALIGN 0 34629 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_RX_BITS 1 34630 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_RX_SHIFT 8 34631 34632 /* Digital5 :: parDetINDControl1 :: pd_100fx_disable [07:07] */ 34633 #define DIGITAL5_PARDETINDCONTROL1_PD_100FX_DISABLE_MASK 0x0080 34634 #define DIGITAL5_PARDETINDCONTROL1_PD_100FX_DISABLE_ALIGN 0 34635 #define DIGITAL5_PARDETINDCONTROL1_PD_100FX_DISABLE_BITS 1 34636 #define DIGITAL5_PARDETINDCONTROL1_PD_100FX_DISABLE_SHIFT 7 34637 34638 /* Digital5 :: parDetINDControl1 :: pd_sw_2p5g_en_rx [06:06] */ 34639 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_RX_MASK 0x0040 34640 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_RX_ALIGN 0 34641 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_RX_BITS 1 34642 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_RX_SHIFT 6 34643 34644 /* Digital5 :: parDetINDControl1 :: pd_2p5g_disable [05:05] */ 34645 #define DIGITAL5_PARDETINDCONTROL1_PD_2P5G_DISABLE_MASK 0x0020 34646 #define DIGITAL5_PARDETINDCONTROL1_PD_2P5G_DISABLE_ALIGN 0 34647 #define DIGITAL5_PARDETINDCONTROL1_PD_2P5G_DISABLE_BITS 1 34648 #define DIGITAL5_PARDETINDCONTROL1_PD_2P5G_DISABLE_SHIFT 5 34649 34650 /* Digital5 :: parDetINDControl1 :: pd_sw_xfi_en_rx [04:04] */ 34651 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_RX_MASK 0x0010 34652 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_RX_ALIGN 0 34653 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_RX_BITS 1 34654 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_RX_SHIFT 4 34655 34656 /* Digital5 :: parDetINDControl1 :: pd_xfi_disable [03:03] */ 34657 #define DIGITAL5_PARDETINDCONTROL1_PD_XFI_DISABLE_MASK 0x0008 34658 #define DIGITAL5_PARDETINDCONTROL1_PD_XFI_DISABLE_ALIGN 0 34659 #define DIGITAL5_PARDETINDCONTROL1_PD_XFI_DISABLE_BITS 1 34660 #define DIGITAL5_PARDETINDCONTROL1_PD_XFI_DISABLE_SHIFT 3 34661 34662 /* Digital5 :: parDetINDControl1 :: pd_stat_sel [02:02] */ 34663 #define DIGITAL5_PARDETINDCONTROL1_PD_STAT_SEL_MASK 0x0004 34664 #define DIGITAL5_PARDETINDCONTROL1_PD_STAT_SEL_ALIGN 0 34665 #define DIGITAL5_PARDETINDCONTROL1_PD_STAT_SEL_BITS 1 34666 #define DIGITAL5_PARDETINDCONTROL1_PD_STAT_SEL_SHIFT 2 34667 34668 /* Digital5 :: parDetINDControl1 :: pd_fast_timer_en [01:01] */ 34669 #define DIGITAL5_PARDETINDCONTROL1_PD_FAST_TIMER_EN_MASK 0x0002 34670 #define DIGITAL5_PARDETINDCONTROL1_PD_FAST_TIMER_EN_ALIGN 0 34671 #define DIGITAL5_PARDETINDCONTROL1_PD_FAST_TIMER_EN_BITS 1 34672 #define DIGITAL5_PARDETINDCONTROL1_PD_FAST_TIMER_EN_SHIFT 1 34673 34674 /* Digital5 :: parDetINDControl1 :: parDetind_en [00:00] */ 34675 #define DIGITAL5_PARDETINDCONTROL1_PARDETIND_EN_MASK 0x0001 34676 #define DIGITAL5_PARDETINDCONTROL1_PARDETIND_EN_ALIGN 0 34677 #define DIGITAL5_PARDETINDCONTROL1_PARDETIND_EN_BITS 1 34678 #define DIGITAL5_PARDETINDCONTROL1_PARDETIND_EN_SHIFT 0 34679 34680 34681 /**************************************************************************** 34682 * Digital5 :: parDetINDControl2 34683 */ 34684 /* Digital5 :: parDetINDControl2 :: reserved0 [15:04] */ 34685 #define DIGITAL5_PARDETINDCONTROL2_RESERVED0_MASK 0xfff0 34686 #define DIGITAL5_PARDETINDCONTROL2_RESERVED0_ALIGN 0 34687 #define DIGITAL5_PARDETINDCONTROL2_RESERVED0_BITS 12 34688 #define DIGITAL5_PARDETINDCONTROL2_RESERVED0_SHIFT 4 34689 34690 /* Digital5 :: parDetINDControl2 :: pd_xfi_init [03:03] */ 34691 #define DIGITAL5_PARDETINDCONTROL2_PD_XFI_INIT_MASK 0x0008 34692 #define DIGITAL5_PARDETINDCONTROL2_PD_XFI_INIT_ALIGN 0 34693 #define DIGITAL5_PARDETINDCONTROL2_PD_XFI_INIT_BITS 1 34694 #define DIGITAL5_PARDETINDCONTROL2_PD_XFI_INIT_SHIFT 3 34695 34696 /* Digital5 :: parDetINDControl2 :: pd_sw_busy_an [02:02] */ 34697 #define DIGITAL5_PARDETINDCONTROL2_PD_SW_BUSY_AN_MASK 0x0004 34698 #define DIGITAL5_PARDETINDCONTROL2_PD_SW_BUSY_AN_ALIGN 0 34699 #define DIGITAL5_PARDETINDCONTROL2_PD_SW_BUSY_AN_BITS 1 34700 #define DIGITAL5_PARDETINDCONTROL2_PD_SW_BUSY_AN_SHIFT 2 34701 34702 /* Digital5 :: parDetINDControl2 :: pd_cl73_couple_dis [01:01] */ 34703 #define DIGITAL5_PARDETINDCONTROL2_PD_CL73_COUPLE_DIS_MASK 0x0002 34704 #define DIGITAL5_PARDETINDCONTROL2_PD_CL73_COUPLE_DIS_ALIGN 0 34705 #define DIGITAL5_PARDETINDCONTROL2_PD_CL73_COUPLE_DIS_BITS 1 34706 #define DIGITAL5_PARDETINDCONTROL2_PD_CL73_COUPLE_DIS_SHIFT 1 34707 34708 /* Digital5 :: parDetINDControl2 :: pd_IgnoreLink_dis [00:00] */ 34709 #define DIGITAL5_PARDETINDCONTROL2_PD_IGNORELINK_DIS_MASK 0x0001 34710 #define DIGITAL5_PARDETINDCONTROL2_PD_IGNORELINK_DIS_ALIGN 0 34711 #define DIGITAL5_PARDETINDCONTROL2_PD_IGNORELINK_DIS_BITS 1 34712 #define DIGITAL5_PARDETINDCONTROL2_PD_IGNORELINK_DIS_SHIFT 0 34713 34714 34715 /**************************************************************************** 34716 * Digital5 :: Misc7 34717 */ 34718 /* Digital5 :: Misc7 :: reserved0 [15:14] */ 34719 #define DIGITAL5_MISC7_RESERVED0_MASK 0xc000 34720 #define DIGITAL5_MISC7_RESERVED0_ALIGN 0 34721 #define DIGITAL5_MISC7_RESERVED0_BITS 14 34722 #define DIGITAL5_MISC7_RESERVED0_SHIFT 14 34723 34724 /* Digital5 :: Misc7 :: force_oscdr_mode_val [13:10] */ 34725 #define DIGITAL5_MISC7_FORCE_OSCDR_MODE_VAL_MASK 0x3c00 34726 #define DIGITAL5_MISC7_FORCE_OSCDR_MODE_VAL_ALIGN 0 34727 #define DIGITAL5_MISC7_FORCE_OSCDR_MODE_VAL_BITS 4 34728 #define DIGITAL5_MISC7_FORCE_OSCDR_MODE_VAL_SHIFT 10 34729 34730 /* Digital5 :: Misc7 :: force_oscdr_mode_en [9:9] */ 34731 #define DIGITAL5_MISC7_FORCE_OSCDR_MODE_MASK 0x200 34732 #define DIGITAL5_MISC7_FORCE_OSCDR_MODE_EN_ALIGN 0 34733 #define DIGITAL5_MISC7_FORCE_OSCDR_MODE_EN_BITS 1 34734 #define DIGITAL5_MISC7_FORCE_OSCDR_MODE_EN_SHIFT 9 34735 34736 34737 /* Digital5 :: Misc7 :: force_speed_rx_pre_7_6 [07:06] */ 34738 #define DIGITAL5_MISC7_FORCE_SPEED_RX_PRE_7_6_MASK 0x00c0 34739 #define DIGITAL5_MISC7_FORCE_SPEED_RX_PRE_7_6_ALIGN 0 34740 #define DIGITAL5_MISC7_FORCE_SPEED_RX_PRE_7_6_BITS 2 34741 #define DIGITAL5_MISC7_FORCE_SPEED_RX_PRE_7_6_SHIFT 6 34742 34743 /* Digital5 :: Misc7 :: brcm6466_cl49_in_all_mode_cya [05:05] */ 34744 #define DIGITAL5_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_MASK 0x0020 34745 #define DIGITAL5_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_ALIGN 0 34746 #define DIGITAL5_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_BITS 1 34747 #define DIGITAL5_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_SHIFT 5 34748 34749 /* Digital5 :: Misc7 :: xfi_txfault_pll_cya [04:04] */ 34750 #define DIGITAL5_MISC7_XFI_TXFAULT_PLL_CYA_MASK 0x0010 34751 #define DIGITAL5_MISC7_XFI_TXFAULT_PLL_CYA_ALIGN 0 34752 #define DIGITAL5_MISC7_XFI_TXFAULT_PLL_CYA_BITS 1 34753 #define DIGITAL5_MISC7_XFI_TXFAULT_PLL_CYA_SHIFT 4 34754 34755 /* Digital5 :: Misc7 :: xfi_txfault_ext_cya [03:03] */ 34756 #define DIGITAL5_MISC7_XFI_TXFAULT_EXT_CYA_MASK 0x0008 34757 #define DIGITAL5_MISC7_XFI_TXFAULT_EXT_CYA_ALIGN 0 34758 #define DIGITAL5_MISC7_XFI_TXFAULT_EXT_CYA_BITS 1 34759 #define DIGITAL5_MISC7_XFI_TXFAULT_EXT_CYA_SHIFT 3 34760 34761 /* Digital5 :: Misc7 :: xfi_txfault_det_cya [02:02] */ 34762 #define DIGITAL5_MISC7_XFI_TXFAULT_DET_CYA_MASK 0x0004 34763 #define DIGITAL5_MISC7_XFI_TXFAULT_DET_CYA_ALIGN 0 34764 #define DIGITAL5_MISC7_XFI_TXFAULT_DET_CYA_BITS 1 34765 #define DIGITAL5_MISC7_XFI_TXFAULT_DET_CYA_SHIFT 2 34766 34767 /* Digital5 :: Misc7 :: xfi_rxfault_link_cya [01:01] */ 34768 #define DIGITAL5_MISC7_XFI_RXFAULT_LINK_CYA_MASK 0x0002 34769 #define DIGITAL5_MISC7_XFI_RXFAULT_LINK_CYA_ALIGN 0 34770 #define DIGITAL5_MISC7_XFI_RXFAULT_LINK_CYA_BITS 1 34771 #define DIGITAL5_MISC7_XFI_RXFAULT_LINK_CYA_SHIFT 1 34772 34773 /* Digital5 :: Misc7 :: xfi_rxfault_det_cya [00:00] */ 34774 #define DIGITAL5_MISC7_XFI_RXFAULT_DET_CYA_MASK 0x0001 34775 #define DIGITAL5_MISC7_XFI_RXFAULT_DET_CYA_ALIGN 0 34776 #define DIGITAL5_MISC7_XFI_RXFAULT_DET_CYA_BITS 1 34777 #define DIGITAL5_MISC7_XFI_RXFAULT_DET_CYA_SHIFT 0 34778 34779 34780 /**************************************************************************** 34781 * Digital5 :: link_status 34782 */ 34783 /* Digital5 :: link_status :: reserved0 [15:06] */ 34784 #define DIGITAL5_LINK_STATUS_RESERVED0_MASK 0xffc0 34785 #define DIGITAL5_LINK_STATUS_RESERVED0_ALIGN 0 34786 #define DIGITAL5_LINK_STATUS_RESERVED0_BITS 10 34787 #define DIGITAL5_LINK_STATUS_RESERVED0_SHIFT 6 34788 34789 /* Digital5 :: link_status :: ll_link [05:05] */ 34790 #define DIGITAL5_LINK_STATUS_LL_LINK_MASK 0x0020 34791 #define DIGITAL5_LINK_STATUS_LL_LINK_ALIGN 0 34792 #define DIGITAL5_LINK_STATUS_LL_LINK_BITS 1 34793 #define DIGITAL5_LINK_STATUS_LL_LINK_SHIFT 5 34794 34795 /* Digital5 :: link_status :: l_an_link [04:04] */ 34796 #define DIGITAL5_LINK_STATUS_L_AN_LINK_MASK 0x0010 34797 #define DIGITAL5_LINK_STATUS_L_AN_LINK_ALIGN 0 34798 #define DIGITAL5_LINK_STATUS_L_AN_LINK_BITS 1 34799 #define DIGITAL5_LINK_STATUS_L_AN_LINK_SHIFT 4 34800 34801 /* Digital5 :: link_status :: l_link_kr [03:03] */ 34802 #define DIGITAL5_LINK_STATUS_L_LINK_KR_MASK 0x0008 34803 #define DIGITAL5_LINK_STATUS_L_LINK_KR_ALIGN 0 34804 #define DIGITAL5_LINK_STATUS_L_LINK_KR_BITS 1 34805 #define DIGITAL5_LINK_STATUS_L_LINK_KR_SHIFT 3 34806 34807 /* Digital5 :: link_status :: l_link10g [02:02] */ 34808 #define DIGITAL5_LINK_STATUS_L_LINK10G_MASK 0x0004 34809 #define DIGITAL5_LINK_STATUS_L_LINK10G_ALIGN 0 34810 #define DIGITAL5_LINK_STATUS_L_LINK10G_BITS 1 34811 #define DIGITAL5_LINK_STATUS_L_LINK10G_SHIFT 2 34812 34813 /* Digital5 :: link_status :: l_link_status [01:01] */ 34814 #define DIGITAL5_LINK_STATUS_L_LINK_STATUS_MASK 0x0002 34815 #define DIGITAL5_LINK_STATUS_L_LINK_STATUS_ALIGN 0 34816 #define DIGITAL5_LINK_STATUS_L_LINK_STATUS_BITS 1 34817 #define DIGITAL5_LINK_STATUS_L_LINK_STATUS_SHIFT 1 34818 34819 /* Digital5 :: link_status :: l_link [00:00] */ 34820 #define DIGITAL5_LINK_STATUS_L_LINK_MASK 0x0001 34821 #define DIGITAL5_LINK_STATUS_L_LINK_ALIGN 0 34822 #define DIGITAL5_LINK_STATUS_L_LINK_BITS 1 34823 #define DIGITAL5_LINK_STATUS_L_LINK_SHIFT 0 34824 34825 34826 /**************************************************************************** 34827 * Digital5 :: actual_speed 34828 */ 34829 /* Digital5 :: actual_speed :: reserved_for_eco0 [15:14] */ 34830 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO0_MASK 0xc000 34831 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO0_ALIGN 0 34832 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO0_BITS 2 34833 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO0_SHIFT 14 34834 34835 /* Digital5 :: actual_speed :: actual_speed_rx [13:08] */ 34836 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_MASK 0x3f00 34837 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_ALIGN 0 34838 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_BITS 6 34839 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_SHIFT 8 34840 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10M 0 34841 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_100M 1 34842 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_1G 2 34843 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_2p5G 3 34844 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_5G_X4 4 34845 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_6G_X4 5 34846 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_HiG 6 34847 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_CX4 7 34848 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_12G_HiG 8 34849 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_12p5G_X4 9 34850 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_13G_X4 10 34851 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_15G_X4 11 34852 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_16G_X4 12 34853 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_1G_KX 13 34854 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_KX4 14 34855 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_KR 15 34856 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_5G 16 34857 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_6p4G 17 34858 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_20G_X4 18 34859 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_21G_X4 19 34860 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_25G_X4 20 34861 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_HiG_DXGXS 21 34862 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_DXGXS 22 34863 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10p5G_HiG_DXGXS 23 34864 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10p5G_DXGXS 24 34865 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_12p773G_HiG_DXGXS 25 34866 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_12p773G_DXGXS 26 34867 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_XFI 27 34868 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_40G 28 34869 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_20G_HiG_DXGXS 29 34870 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_20G_DXGXS 30 34871 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_SFI 31 34872 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_31p5G 32 34873 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_32p7G 33 34874 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_20G_SCR 34 34875 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_HiG_DXGXS_SCR 35 34876 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_DXGXS_SCR 36 34877 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_12G_R2 37 34878 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_X2 38 34879 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_40G_KR4 39 34880 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_40G_CR4 40 34881 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_100G_CR10 41 34882 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_15p75G_DXGXS 44 34883 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_20G_KR2 57 34884 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_20G_CR2 58 34885 34886 /* Digital5 :: actual_speed :: reserved_for_eco1 [07:06] */ 34887 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO1_MASK 0x00c0 34888 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO1_ALIGN 0 34889 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO1_BITS 2 34890 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO1_SHIFT 6 34891 34892 /* Digital5 :: actual_speed :: actual_speed_tx [05:00] */ 34893 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_MASK 0x003f 34894 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_ALIGN 0 34895 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_BITS 6 34896 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_SHIFT 0 34897 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10M 0 34898 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_100M 1 34899 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_1G 2 34900 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_2p5G 3 34901 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_5G_X4 4 34902 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_6G_X4 5 34903 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_HiG 6 34904 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_CX4 7 34905 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_12G_HiG 8 34906 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_12p5G_X4 9 34907 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_13G_X4 10 34908 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_15G_X4 11 34909 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_16G_X4 12 34910 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_1G_KX 13 34911 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_KX4 14 34912 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_KR 15 34913 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_5G 16 34914 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_6p4G 17 34915 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_20G_X4 18 34916 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_21G_X4 19 34917 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_25G_X4 20 34918 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_HiG_DXGXS 21 34919 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_DXGXS 22 34920 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10p5G_HiG_DXGXS 23 34921 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10p5G_DXGXS 24 34922 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_12p773G_HiG_DXGXS 25 34923 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_12p773G_DXGXS 26 34924 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_XFI 27 34925 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_40G 28 34926 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_20G_HiG_DXGXS 29 34927 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_20G_DXGXS 30 34928 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_SFI 31 34929 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_31p5G 32 34930 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_32p7G 33 34931 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_20G_SCR 34 34932 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_HiG_DXGXS_SCR 35 34933 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_DXGXS_SCR 36 34934 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_12G_R2 37 34935 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_X2 38 34936 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_40G_KR4 39 34937 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_40G_CR4 40 34938 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_100G_CR10 41 34939 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_15p75G_DXGXS 44 34940 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_20G_KR2 57 34941 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_20G_CR2 58 34942 34943 34944 /**************************************************************************** 34945 * Warpcore_USER_Digital6 34946 */ 34947 /**************************************************************************** 34948 * Digital6 :: mp5_NextPageCtrl 34949 */ 34950 /* Digital6 :: mp5_NextPageCtrl :: reserved0 [15:04] */ 34951 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_MASK 0xfff0 34952 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_ALIGN 0 34953 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_BITS 12 34954 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_SHIFT 4 34955 34956 /* Digital6 :: mp5_NextPageCtrl :: np_sw_overRide_en [03:03] */ 34957 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_MASK 0x0008 34958 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_ALIGN 0 34959 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_BITS 1 34960 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_SHIFT 3 34961 34962 /* Digital6 :: mp5_NextPageCtrl :: teton_mode_up3_en [02:02] */ 34963 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_MASK 0x0004 34964 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_ALIGN 0 34965 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_BITS 1 34966 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_SHIFT 2 34967 34968 /* Digital6 :: mp5_NextPageCtrl :: teton_mode [01:01] */ 34969 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_MASK 0x0002 34970 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_ALIGN 0 34971 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_BITS 1 34972 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_SHIFT 1 34973 34974 /* Digital6 :: mp5_NextPageCtrl :: bam_mode [00:00] */ 34975 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_MASK 0x0001 34976 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_ALIGN 0 34977 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_BITS 1 34978 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_SHIFT 0 34979 34980 34981 /**************************************************************************** 34982 * Digital6 :: link_timer_offset1 34983 */ 34984 /* Digital6 :: link_timer_offset1 :: sgmii_offset [15:08] */ 34985 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_MASK 0xff00 34986 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_ALIGN 0 34987 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_BITS 8 34988 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_SHIFT 8 34989 34990 /* Digital6 :: link_timer_offset1 :: max_offset [07:00] */ 34991 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_MASK 0x00ff 34992 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_ALIGN 0 34993 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_BITS 8 34994 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_SHIFT 0 34995 34996 34997 /**************************************************************************** 34998 * Digital6 :: link_timer_offset2 34999 */ 35000 /* Digital6 :: link_timer_offset2 :: link_up_offset [15:08] */ 35001 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_MASK 0xff00 35002 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_ALIGN 0 35003 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_BITS 8 35004 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_SHIFT 8 35005 35006 /* Digital6 :: link_timer_offset2 :: link_down_offset [07:00] */ 35007 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_MASK 0x00ff 35008 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_ALIGN 0 35009 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_BITS 8 35010 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_SHIFT 0 35011 35012 35013 /**************************************************************************** 35014 * Digital6 :: link_timer_offset3 35015 */ 35016 /* Digital6 :: link_timer_offset3 :: break_link_offset [15:08] */ 35017 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_MASK 0xff00 35018 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_ALIGN 0 35019 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_BITS 8 35020 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_SHIFT 8 35021 35022 /* Digital6 :: link_timer_offset3 :: np_link_offset [07:00] */ 35023 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_MASK 0x00ff 35024 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_ALIGN 0 35025 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_BITS 8 35026 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_SHIFT 0 35027 35028 35029 /**************************************************************************** 35030 * Digital6 :: oui_msb_field 35031 */ 35032 /* Digital6 :: oui_msb_field :: reserved0 [15:11] */ 35033 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_MASK 0xf800 35034 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_ALIGN 0 35035 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_BITS 5 35036 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_SHIFT 11 35037 35038 /* Digital6 :: oui_msb_field :: oui_msb_field [10:00] */ 35039 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK 0x07ff 35040 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN 0 35041 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS 11 35042 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT 0 35043 35044 35045 /**************************************************************************** 35046 * Digital6 :: oui_lsb_field 35047 */ 35048 /* Digital6 :: oui_lsb_field :: reserved0 [15:11] */ 35049 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_MASK 0xf800 35050 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_ALIGN 0 35051 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_BITS 5 35052 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_SHIFT 11 35053 35054 /* Digital6 :: oui_lsb_field :: oui_lsb_field [10:00] */ 35055 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK 0x07ff 35056 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN 0 35057 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS 11 35058 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT 0 35059 35060 35061 /**************************************************************************** 35062 * Digital6 :: bam_field 35063 */ 35064 /* Digital6 :: bam_field :: reserved0 [15:11] */ 35065 #define DIGITAL6_BAM_FIELD_RESERVED0_MASK 0xf800 35066 #define DIGITAL6_BAM_FIELD_RESERVED0_ALIGN 0 35067 #define DIGITAL6_BAM_FIELD_RESERVED0_BITS 5 35068 #define DIGITAL6_BAM_FIELD_RESERVED0_SHIFT 11 35069 35070 /* Digital6 :: bam_field :: oui_1_0 [10:09] */ 35071 #define DIGITAL6_BAM_FIELD_OUI_1_0_MASK 0x0600 35072 #define DIGITAL6_BAM_FIELD_OUI_1_0_ALIGN 0 35073 #define DIGITAL6_BAM_FIELD_OUI_1_0_BITS 2 35074 #define DIGITAL6_BAM_FIELD_OUI_1_0_SHIFT 9 35075 35076 /* Digital6 :: bam_field :: bam_field [08:00] */ 35077 #define DIGITAL6_BAM_FIELD_BAM_FIELD_MASK 0x01ff 35078 #define DIGITAL6_BAM_FIELD_BAM_FIELD_ALIGN 0 35079 #define DIGITAL6_BAM_FIELD_BAM_FIELD_BITS 9 35080 #define DIGITAL6_BAM_FIELD_BAM_FIELD_SHIFT 0 35081 35082 35083 /**************************************************************************** 35084 * Digital6 :: ud_field 35085 */ 35086 /* Digital6 :: ud_field :: reserved0 [15:11] */ 35087 #define DIGITAL6_UD_FIELD_RESERVED0_MASK 0xf800 35088 #define DIGITAL6_UD_FIELD_RESERVED0_ALIGN 0 35089 #define DIGITAL6_UD_FIELD_RESERVED0_BITS 5 35090 #define DIGITAL6_UD_FIELD_RESERVED0_SHIFT 11 35091 35092 /* Digital6 :: ud_field :: ud_reserved [10:06] */ 35093 #define DIGITAL6_UD_FIELD_UD_RESERVED_MASK 0x07c0 35094 #define DIGITAL6_UD_FIELD_UD_RESERVED_ALIGN 0 35095 #define DIGITAL6_UD_FIELD_UD_RESERVED_BITS 5 35096 #define DIGITAL6_UD_FIELD_UD_RESERVED_SHIFT 6 35097 35098 /* Digital6 :: ud_field :: remote_BN_page [05:05] */ 35099 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_MASK 0x0020 35100 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_ALIGN 0 35101 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_BITS 1 35102 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_SHIFT 5 35103 35104 /* Digital6 :: ud_field :: inband_MDIO [04:04] */ 35105 #define DIGITAL6_UD_FIELD_INBAND_MDIO_MASK 0x0010 35106 #define DIGITAL6_UD_FIELD_INBAND_MDIO_ALIGN 0 35107 #define DIGITAL6_UD_FIELD_INBAND_MDIO_BITS 1 35108 #define DIGITAL6_UD_FIELD_INBAND_MDIO_SHIFT 4 35109 35110 /* Digital6 :: ud_field :: autoneg_MDIO [03:03] */ 35111 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_MASK 0x0008 35112 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_ALIGN 0 35113 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_BITS 1 35114 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_SHIFT 3 35115 35116 /* Digital6 :: ud_field :: remote_serdes_phy [02:02] */ 35117 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_MASK 0x0004 35118 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_ALIGN 0 35119 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_BITS 1 35120 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_SHIFT 2 35121 35122 /* Digital6 :: ud_field :: remote_cu_phy [01:01] */ 35123 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_MASK 0x0002 35124 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_ALIGN 0 35125 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_BITS 1 35126 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_SHIFT 1 35127 35128 /* Digital6 :: ud_field :: over1g [00:00] */ 35129 #define DIGITAL6_UD_FIELD_OVER1G_MASK 0x0001 35130 #define DIGITAL6_UD_FIELD_OVER1G_ALIGN 0 35131 #define DIGITAL6_UD_FIELD_OVER1G_BITS 1 35132 #define DIGITAL6_UD_FIELD_OVER1G_SHIFT 0 35133 35134 35135 /**************************************************************************** 35136 * Digital6 :: lp_oui_msb_field 35137 */ 35138 /* Digital6 :: lp_oui_msb_field :: reserved0 [15:11] */ 35139 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_MASK 0xf800 35140 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_ALIGN 0 35141 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_BITS 5 35142 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_SHIFT 11 35143 35144 /* Digital6 :: lp_oui_msb_field :: oui_msb_field [10:00] */ 35145 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK 0x07ff 35146 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN 0 35147 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS 11 35148 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT 0 35149 35150 35151 /**************************************************************************** 35152 * Digital6 :: lp_oui_lsb_field 35153 */ 35154 /* Digital6 :: lp_oui_lsb_field :: reserved0 [15:11] */ 35155 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_MASK 0xf800 35156 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_ALIGN 0 35157 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_BITS 5 35158 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_SHIFT 11 35159 35160 /* Digital6 :: lp_oui_lsb_field :: oui_lsb_field [10:00] */ 35161 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK 0x07ff 35162 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN 0 35163 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS 11 35164 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT 0 35165 35166 35167 /**************************************************************************** 35168 * Digital6 :: lp_bam_field 35169 */ 35170 /* Digital6 :: lp_bam_field :: reserved0 [15:11] */ 35171 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_MASK 0xf800 35172 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_ALIGN 0 35173 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_BITS 5 35174 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_SHIFT 11 35175 35176 /* Digital6 :: lp_bam_field :: oui_1_0 [10:09] */ 35177 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_MASK 0x0600 35178 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_ALIGN 0 35179 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_BITS 2 35180 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_SHIFT 9 35181 35182 /* Digital6 :: lp_bam_field :: bam_field [08:00] */ 35183 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_MASK 0x01ff 35184 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_ALIGN 0 35185 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_BITS 9 35186 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_SHIFT 0 35187 35188 35189 /**************************************************************************** 35190 * Digital6 :: lp_ud_field 35191 */ 35192 /* Digital6 :: lp_ud_field :: reserved0 [15:11] */ 35193 #define DIGITAL6_LP_UD_FIELD_RESERVED0_MASK 0xf800 35194 #define DIGITAL6_LP_UD_FIELD_RESERVED0_ALIGN 0 35195 #define DIGITAL6_LP_UD_FIELD_RESERVED0_BITS 5 35196 #define DIGITAL6_LP_UD_FIELD_RESERVED0_SHIFT 11 35197 35198 /* Digital6 :: lp_ud_field :: ud_reserved [10:06] */ 35199 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_MASK 0x07c0 35200 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_ALIGN 0 35201 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_BITS 5 35202 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_SHIFT 6 35203 35204 /* Digital6 :: lp_ud_field :: remote_BN_page [05:05] */ 35205 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_MASK 0x0020 35206 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_ALIGN 0 35207 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_BITS 1 35208 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_SHIFT 5 35209 35210 /* Digital6 :: lp_ud_field :: inband_MDIO [04:04] */ 35211 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_MASK 0x0010 35212 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_ALIGN 0 35213 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_BITS 1 35214 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_SHIFT 4 35215 35216 /* Digital6 :: lp_ud_field :: autoneg_MDIO [03:03] */ 35217 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_MASK 0x0008 35218 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_ALIGN 0 35219 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_BITS 1 35220 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_SHIFT 3 35221 35222 /* Digital6 :: lp_ud_field :: remote_serdes_phy [02:02] */ 35223 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_MASK 0x0004 35224 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_ALIGN 0 35225 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_BITS 1 35226 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_SHIFT 2 35227 35228 /* Digital6 :: lp_ud_field :: remote_cu_phy [01:01] */ 35229 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_MASK 0x0002 35230 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_ALIGN 0 35231 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_BITS 1 35232 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_SHIFT 1 35233 35234 /* Digital6 :: lp_ud_field :: over1g [00:00] */ 35235 #define DIGITAL6_LP_UD_FIELD_OVER1G_MASK 0x0001 35236 #define DIGITAL6_LP_UD_FIELD_OVER1G_ALIGN 0 35237 #define DIGITAL6_LP_UD_FIELD_OVER1G_BITS 1 35238 #define DIGITAL6_LP_UD_FIELD_OVER1G_SHIFT 0 35239 35240 35241 /**************************************************************************** 35242 * Digital6 :: UP4 35243 */ 35244 /* Digital6 :: UP4 :: reserved0 [15:11] */ 35245 #define DIGITAL6_UP4_RESERVED0_MASK 0xf800 35246 #define DIGITAL6_UP4_RESERVED0_ALIGN 0 35247 #define DIGITAL6_UP4_RESERVED0_BITS 5 35248 #define DIGITAL6_UP4_RESERVED0_SHIFT 11 35249 35250 /* Digital6 :: UP4 :: last [10:10] */ 35251 #define DIGITAL6_UP4_LAST_MASK 0x0400 35252 #define DIGITAL6_UP4_LAST_ALIGN 0 35253 #define DIGITAL6_UP4_LAST_BITS 1 35254 #define DIGITAL6_UP4_LAST_SHIFT 10 35255 35256 /* Digital6 :: UP4 :: reserved1 [09:08] */ 35257 #define DIGITAL6_UP4_RESERVED1_MASK 0x0300 35258 #define DIGITAL6_UP4_RESERVED1_ALIGN 0 35259 #define DIGITAL6_UP4_RESERVED1_BITS 2 35260 #define DIGITAL6_UP4_RESERVED1_SHIFT 8 35261 35262 /* Digital6 :: UP4 :: dataRate_15p75G_dxgxs [07:07] */ 35263 #define DIGITAL6_UP4_DATARATE_15P75G_DXGXS_MASK 0x0080 35264 #define DIGITAL6_UP4_DATARATE_15P75G_DXGXS_ALIGN 0 35265 #define DIGITAL6_UP4_DATARATE_15P75G_DXGXS_BITS 1 35266 #define DIGITAL6_UP4_DATARATE_15P75G_DXGXS_SHIFT 7 35267 35268 /* Digital6 :: UP4 :: dataRate_20G_dxgxs [06:06] */ 35269 #define DIGITAL6_UP4_DATARATE_20G_DXGXS_MASK 0x0040 35270 #define DIGITAL6_UP4_DATARATE_20G_DXGXS_ALIGN 0 35271 #define DIGITAL6_UP4_DATARATE_20G_DXGXS_BITS 1 35272 #define DIGITAL6_UP4_DATARATE_20G_DXGXS_SHIFT 6 35273 35274 /* Digital6 :: UP4 :: dataRate_20Gh_dxgxs [05:05] */ 35275 #define DIGITAL6_UP4_DATARATE_20GH_DXGXS_MASK 0x0020 35276 #define DIGITAL6_UP4_DATARATE_20GH_DXGXS_ALIGN 0 35277 #define DIGITAL6_UP4_DATARATE_20GH_DXGXS_BITS 1 35278 #define DIGITAL6_UP4_DATARATE_20GH_DXGXS_SHIFT 5 35279 35280 /* Digital6 :: UP4 :: dataRate_12p7G_dxgxs [04:04] */ 35281 #define DIGITAL6_UP4_DATARATE_12P7G_DXGXS_MASK 0x0010 35282 #define DIGITAL6_UP4_DATARATE_12P7G_DXGXS_ALIGN 0 35283 #define DIGITAL6_UP4_DATARATE_12P7G_DXGXS_BITS 1 35284 #define DIGITAL6_UP4_DATARATE_12P7G_DXGXS_SHIFT 4 35285 35286 /* Digital6 :: UP4 :: dataRate_10p5G_dxgxs [03:03] */ 35287 #define DIGITAL6_UP4_DATARATE_10P5G_DXGXS_MASK 0x0008 35288 #define DIGITAL6_UP4_DATARATE_10P5G_DXGXS_ALIGN 0 35289 #define DIGITAL6_UP4_DATARATE_10P5G_DXGXS_BITS 1 35290 #define DIGITAL6_UP4_DATARATE_10P5G_DXGXS_SHIFT 3 35291 35292 /* Digital6 :: UP4 :: dataRate_10G_dxgxs [02:02] */ 35293 #define DIGITAL6_UP4_DATARATE_10G_DXGXS_MASK 0x0004 35294 #define DIGITAL6_UP4_DATARATE_10G_DXGXS_ALIGN 0 35295 #define DIGITAL6_UP4_DATARATE_10G_DXGXS_BITS 1 35296 #define DIGITAL6_UP4_DATARATE_10G_DXGXS_SHIFT 2 35297 35298 /* Digital6 :: UP4 :: dataRate_10Gh_dxgxs [01:01] */ 35299 #define DIGITAL6_UP4_DATARATE_10GH_DXGXS_MASK 0x0002 35300 #define DIGITAL6_UP4_DATARATE_10GH_DXGXS_ALIGN 0 35301 #define DIGITAL6_UP4_DATARATE_10GH_DXGXS_BITS 1 35302 #define DIGITAL6_UP4_DATARATE_10GH_DXGXS_SHIFT 1 35303 35304 /* Digital6 :: UP4 :: dataRate_20G [00:00] */ 35305 #define DIGITAL6_UP4_DATARATE_20G_MASK 0x0001 35306 #define DIGITAL6_UP4_DATARATE_20G_ALIGN 0 35307 #define DIGITAL6_UP4_DATARATE_20G_BITS 1 35308 #define DIGITAL6_UP4_DATARATE_20G_SHIFT 0 35309 35310 35311 /**************************************************************************** 35312 * Digital6 :: UP5 35313 */ 35314 /* Digital6 :: UP5 :: reserved0 [15:11] */ 35315 #define DIGITAL6_UP5_RESERVED0_MASK 0xf800 35316 #define DIGITAL6_UP5_RESERVED0_ALIGN 0 35317 #define DIGITAL6_UP5_RESERVED0_BITS 5 35318 #define DIGITAL6_UP5_RESERVED0_SHIFT 11 35319 35320 /* Digital6 :: UP5 :: last [10:10] */ 35321 #define DIGITAL6_UP5_LAST_MASK 0x0400 35322 #define DIGITAL6_UP5_LAST_ALIGN 0 35323 #define DIGITAL6_UP5_LAST_BITS 1 35324 #define DIGITAL6_UP5_LAST_SHIFT 10 35325 35326 /* Digital6 :: UP5 :: reserved1 [09:00] */ 35327 #define DIGITAL6_UP5_RESERVED1_MASK 0x03ff 35328 #define DIGITAL6_UP5_RESERVED1_ALIGN 0 35329 #define DIGITAL6_UP5_RESERVED1_BITS 10 35330 #define DIGITAL6_UP5_RESERVED1_SHIFT 0 35331 35332 35333 /**************************************************************************** 35334 * Warpcore_USER_CL49_UserB0 35335 */ 35336 /**************************************************************************** 35337 * CL49_UserB0 :: Control1 35338 */ 35339 /* CL49_UserB0 :: Control1 :: reserved0 [15:13] */ 35340 #define CL49_USERB0_CONTROL1_RESERVED0_MASK 0xe000 35341 #define CL49_USERB0_CONTROL1_RESERVED0_ALIGN 0 35342 #define CL49_USERB0_CONTROL1_RESERVED0_BITS 3 35343 #define CL49_USERB0_CONTROL1_RESERVED0_SHIFT 13 35344 35345 /* CL49_UserB0 :: Control1 :: bypass_R2_cl49txsm [12:12] */ 35346 #define CL49_USERB0_CONTROL1_BYPASS_R2_CL49TXSM_MASK 0x1000 35347 #define CL49_USERB0_CONTROL1_BYPASS_R2_CL49TXSM_ALIGN 0 35348 #define CL49_USERB0_CONTROL1_BYPASS_R2_CL49TXSM_BITS 1 35349 #define CL49_USERB0_CONTROL1_BYPASS_R2_CL49TXSM_SHIFT 12 35350 35351 /* CL49_UserB0 :: Control1 :: bypass_cl49txsm [11:11] */ 35352 #define CL49_USERB0_CONTROL1_BYPASS_CL49TXSM_MASK 0x0800 35353 #define CL49_USERB0_CONTROL1_BYPASS_CL49TXSM_ALIGN 0 35354 #define CL49_USERB0_CONTROL1_BYPASS_CL49TXSM_BITS 1 35355 #define CL49_USERB0_CONTROL1_BYPASS_CL49TXSM_SHIFT 11 35356 35357 /* CL49_UserB0 :: Control1 :: r2_tx_msg_len_32bytes [10:10] */ 35358 #define CL49_USERB0_CONTROL1_R2_TX_MSG_LEN_32BYTES_MASK 0x0400 35359 #define CL49_USERB0_CONTROL1_R2_TX_MSG_LEN_32BYTES_ALIGN 0 35360 #define CL49_USERB0_CONTROL1_R2_TX_MSG_LEN_32BYTES_BITS 1 35361 #define CL49_USERB0_CONTROL1_R2_TX_MSG_LEN_32BYTES_SHIFT 10 35362 35363 /* CL49_UserB0 :: Control1 :: r2_tx_HiGig2_TB_en [09:09] */ 35364 #define CL49_USERB0_CONTROL1_R2_TX_HIGIG2_TB_EN_MASK 0x0200 35365 #define CL49_USERB0_CONTROL1_R2_TX_HIGIG2_TB_EN_ALIGN 0 35366 #define CL49_USERB0_CONTROL1_R2_TX_HIGIG2_TB_EN_BITS 1 35367 #define CL49_USERB0_CONTROL1_R2_TX_HIGIG2_TB_EN_SHIFT 9 35368 35369 /* CL49_UserB0 :: Control1 :: r2_tx_HiGig2_en [08:08] */ 35370 #define CL49_USERB0_CONTROL1_R2_TX_HIGIG2_EN_MASK 0x0100 35371 #define CL49_USERB0_CONTROL1_R2_TX_HIGIG2_EN_ALIGN 0 35372 #define CL49_USERB0_CONTROL1_R2_TX_HIGIG2_EN_BITS 1 35373 #define CL49_USERB0_CONTROL1_R2_TX_HIGIG2_EN_SHIFT 8 35374 35375 /* CL49_UserB0 :: Control1 :: tx_msg_len_32bytes [07:07] */ 35376 #define CL49_USERB0_CONTROL1_TX_MSG_LEN_32BYTES_MASK 0x0080 35377 #define CL49_USERB0_CONTROL1_TX_MSG_LEN_32BYTES_ALIGN 0 35378 #define CL49_USERB0_CONTROL1_TX_MSG_LEN_32BYTES_BITS 1 35379 #define CL49_USERB0_CONTROL1_TX_MSG_LEN_32BYTES_SHIFT 7 35380 35381 /* CL49_UserB0 :: Control1 :: tx_HiGig2_TB_en [06:06] */ 35382 #define CL49_USERB0_CONTROL1_TX_HIGIG2_TB_EN_MASK 0x0040 35383 #define CL49_USERB0_CONTROL1_TX_HIGIG2_TB_EN_ALIGN 0 35384 #define CL49_USERB0_CONTROL1_TX_HIGIG2_TB_EN_BITS 1 35385 #define CL49_USERB0_CONTROL1_TX_HIGIG2_TB_EN_SHIFT 6 35386 35387 /* CL49_UserB0 :: Control1 :: tx_HiGig2_en [05:05] */ 35388 #define CL49_USERB0_CONTROL1_TX_HIGIG2_EN_MASK 0x0020 35389 #define CL49_USERB0_CONTROL1_TX_HIGIG2_EN_ALIGN 0 35390 #define CL49_USERB0_CONTROL1_TX_HIGIG2_EN_BITS 1 35391 #define CL49_USERB0_CONTROL1_TX_HIGIG2_EN_SHIFT 5 35392 35393 /* CL49_UserB0 :: Control1 :: cl49_txsm_init_lpi_cya [04:04] */ 35394 #define CL49_USERB0_CONTROL1_CL49_TXSM_INIT_LPI_CYA_MASK 0x0010 35395 #define CL49_USERB0_CONTROL1_CL49_TXSM_INIT_LPI_CYA_ALIGN 0 35396 #define CL49_USERB0_CONTROL1_CL49_TXSM_INIT_LPI_CYA_BITS 1 35397 #define CL49_USERB0_CONTROL1_CL49_TXSM_INIT_LPI_CYA_SHIFT 4 35398 35399 /* CL49_UserB0 :: Control1 :: scramblerControl [03:02] */ 35400 #define CL49_USERB0_CONTROL1_SCRAMBLERCONTROL_MASK 0x000c 35401 #define CL49_USERB0_CONTROL1_SCRAMBLERCONTROL_ALIGN 0 35402 #define CL49_USERB0_CONTROL1_SCRAMBLERCONTROL_BITS 2 35403 #define CL49_USERB0_CONTROL1_SCRAMBLERCONTROL_SHIFT 2 35404 35405 /* CL49_UserB0 :: Control1 :: reserved1 [01:00] */ 35406 #define CL49_USERB0_CONTROL1_RESERVED1_MASK 0x0003 35407 #define CL49_USERB0_CONTROL1_RESERVED1_ALIGN 0 35408 #define CL49_USERB0_CONTROL1_RESERVED1_BITS 2 35409 #define CL49_USERB0_CONTROL1_RESERVED1_SHIFT 0 35410 35411 35412 /**************************************************************************** 35413 * CL49_UserB0 :: Status1 35414 */ 35415 /* CL49_UserB0 :: Status1 :: reserved_for_eco0 [15:00] */ 35416 #define CL49_USERB0_STATUS1_RESERVED_FOR_ECO0_MASK 0xffff 35417 #define CL49_USERB0_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 35418 #define CL49_USERB0_STATUS1_RESERVED_FOR_ECO0_BITS 16 35419 #define CL49_USERB0_STATUS1_RESERVED_FOR_ECO0_SHIFT 0 35420 35421 35422 /**************************************************************************** 35423 * CL49_UserB0 :: symboldetect 35424 */ 35425 /* CL49_UserB0 :: symboldetect :: reserved_for_eco0 [15:09] */ 35426 #define CL49_USERB0_SYMBOLDETECT_RESERVED_FOR_ECO0_MASK 0xfe00 35427 #define CL49_USERB0_SYMBOLDETECT_RESERVED_FOR_ECO0_ALIGN 0 35428 #define CL49_USERB0_SYMBOLDETECT_RESERVED_FOR_ECO0_BITS 7 35429 #define CL49_USERB0_SYMBOLDETECT_RESERVED_FOR_ECO0_SHIFT 9 35430 35431 /* CL49_UserB0 :: symboldetect :: symboldetect [08:00] */ 35432 #define CL49_USERB0_SYMBOLDETECT_SYMBOLDETECT_MASK 0x01ff 35433 #define CL49_USERB0_SYMBOLDETECT_SYMBOLDETECT_ALIGN 0 35434 #define CL49_USERB0_SYMBOLDETECT_SYMBOLDETECT_BITS 9 35435 #define CL49_USERB0_SYMBOLDETECT_SYMBOLDETECT_SHIFT 0 35436 35437 35438 /**************************************************************************** 35439 * CL49_UserB0 :: symbolinsert 35440 */ 35441 /* CL49_UserB0 :: symbolinsert :: reserved_for_eco0 [15:09] */ 35442 #define CL49_USERB0_SYMBOLINSERT_RESERVED_FOR_ECO0_MASK 0xfe00 35443 #define CL49_USERB0_SYMBOLINSERT_RESERVED_FOR_ECO0_ALIGN 0 35444 #define CL49_USERB0_SYMBOLINSERT_RESERVED_FOR_ECO0_BITS 7 35445 #define CL49_USERB0_SYMBOLINSERT_RESERVED_FOR_ECO0_SHIFT 9 35446 35447 /* CL49_UserB0 :: symbolinsert :: symbolinsert [08:00] */ 35448 #define CL49_USERB0_SYMBOLINSERT_SYMBOLINSERT_MASK 0x01ff 35449 #define CL49_USERB0_SYMBOLINSERT_SYMBOLINSERT_ALIGN 0 35450 #define CL49_USERB0_SYMBOLINSERT_SYMBOLINSERT_BITS 9 35451 #define CL49_USERB0_SYMBOLINSERT_SYMBOLINSERT_SHIFT 0 35452 35453 35454 /**************************************************************************** 35455 * CL49_UserB0 :: Control2 35456 */ 35457 /* CL49_UserB0 :: Control2 :: reserved_for_eco0 [15:04] */ 35458 #define CL49_USERB0_CONTROL2_RESERVED_FOR_ECO0_MASK 0xfff0 35459 #define CL49_USERB0_CONTROL2_RESERVED_FOR_ECO0_ALIGN 0 35460 #define CL49_USERB0_CONTROL2_RESERVED_FOR_ECO0_BITS 12 35461 #define CL49_USERB0_CONTROL2_RESERVED_FOR_ECO0_SHIFT 4 35462 35463 /* CL49_UserB0 :: Control2 :: sqwbitcount_SM [03:00] */ 35464 #define CL49_USERB0_CONTROL2_SQWBITCOUNT_SM_MASK 0x000f 35465 #define CL49_USERB0_CONTROL2_SQWBITCOUNT_SM_ALIGN 0 35466 #define CL49_USERB0_CONTROL2_SQWBITCOUNT_SM_BITS 4 35467 #define CL49_USERB0_CONTROL2_SQWBITCOUNT_SM_SHIFT 0 35468 35469 35470 /**************************************************************************** 35471 * CL49_UserB0 :: txsm_status 35472 */ 35473 /* CL49_UserB0 :: txsm_status :: t_type_coded [15:12] */ 35474 #define CL49_USERB0_TXSM_STATUS_T_TYPE_CODED_MASK 0xf000 35475 #define CL49_USERB0_TXSM_STATUS_T_TYPE_CODED_ALIGN 0 35476 #define CL49_USERB0_TXSM_STATUS_T_TYPE_CODED_BITS 4 35477 #define CL49_USERB0_TXSM_STATUS_T_TYPE_CODED_SHIFT 12 35478 35479 /* CL49_UserB0 :: txsm_status :: reserved0 [11:11] */ 35480 #define CL49_USERB0_TXSM_STATUS_RESERVED0_MASK 0x0800 35481 #define CL49_USERB0_TXSM_STATUS_RESERVED0_ALIGN 0 35482 #define CL49_USERB0_TXSM_STATUS_RESERVED0_BITS 1 35483 #define CL49_USERB0_TXSM_STATUS_RESERVED0_SHIFT 11 35484 35485 /* CL49_UserB0 :: txsm_status :: ltxsm_state [10:03] */ 35486 #define CL49_USERB0_TXSM_STATUS_LTXSM_STATE_MASK 0x07f8 35487 #define CL49_USERB0_TXSM_STATUS_LTXSM_STATE_ALIGN 0 35488 #define CL49_USERB0_TXSM_STATUS_LTXSM_STATE_BITS 8 35489 #define CL49_USERB0_TXSM_STATUS_LTXSM_STATE_SHIFT 3 35490 35491 /* CL49_UserB0 :: txsm_status :: txsm_state [02:00] */ 35492 #define CL49_USERB0_TXSM_STATUS_TXSM_STATE_MASK 0x0007 35493 #define CL49_USERB0_TXSM_STATUS_TXSM_STATE_ALIGN 0 35494 #define CL49_USERB0_TXSM_STATUS_TXSM_STATE_BITS 3 35495 #define CL49_USERB0_TXSM_STATUS_TXSM_STATE_SHIFT 0 35496 35497 35498 /**************************************************************************** 35499 * CL49_UserB0 :: rxsm_status 35500 */ 35501 /* CL49_UserB0 :: rxsm_status :: r_type_coded [15:12] */ 35502 #define CL49_USERB0_RXSM_STATUS_R_TYPE_CODED_MASK 0xf000 35503 #define CL49_USERB0_RXSM_STATUS_R_TYPE_CODED_ALIGN 0 35504 #define CL49_USERB0_RXSM_STATUS_R_TYPE_CODED_BITS 4 35505 #define CL49_USERB0_RXSM_STATUS_R_TYPE_CODED_SHIFT 12 35506 35507 /* CL49_UserB0 :: rxsm_status :: reserved0 [11:11] */ 35508 #define CL49_USERB0_RXSM_STATUS_RESERVED0_MASK 0x0800 35509 #define CL49_USERB0_RXSM_STATUS_RESERVED0_ALIGN 0 35510 #define CL49_USERB0_RXSM_STATUS_RESERVED0_BITS 1 35511 #define CL49_USERB0_RXSM_STATUS_RESERVED0_SHIFT 11 35512 35513 /* CL49_UserB0 :: rxsm_status :: lrxsm_state [10:03] */ 35514 #define CL49_USERB0_RXSM_STATUS_LRXSM_STATE_MASK 0x07f8 35515 #define CL49_USERB0_RXSM_STATUS_LRXSM_STATE_ALIGN 0 35516 #define CL49_USERB0_RXSM_STATUS_LRXSM_STATE_BITS 8 35517 #define CL49_USERB0_RXSM_STATUS_LRXSM_STATE_SHIFT 3 35518 35519 /* CL49_UserB0 :: rxsm_status :: rxsm_state [02:00] */ 35520 #define CL49_USERB0_RXSM_STATUS_RXSM_STATE_MASK 0x0007 35521 #define CL49_USERB0_RXSM_STATUS_RXSM_STATE_ALIGN 0 35522 #define CL49_USERB0_RXSM_STATUS_RXSM_STATE_BITS 3 35523 #define CL49_USERB0_RXSM_STATUS_RXSM_STATE_SHIFT 0 35524 35525 35526 /**************************************************************************** 35527 * CL49_UserB0 :: lsm_status 35528 */ 35529 /* CL49_UserB0 :: lsm_status :: block_lock [15:15] */ 35530 #define CL49_USERB0_LSM_STATUS_BLOCK_LOCK_MASK 0x8000 35531 #define CL49_USERB0_LSM_STATUS_BLOCK_LOCK_ALIGN 0 35532 #define CL49_USERB0_LSM_STATUS_BLOCK_LOCK_BITS 1 35533 #define CL49_USERB0_LSM_STATUS_BLOCK_LOCK_SHIFT 15 35534 35535 /* CL49_UserB0 :: lsm_status :: signal_ok [14:14] */ 35536 #define CL49_USERB0_LSM_STATUS_SIGNAL_OK_MASK 0x4000 35537 #define CL49_USERB0_LSM_STATUS_SIGNAL_OK_ALIGN 0 35538 #define CL49_USERB0_LSM_STATUS_SIGNAL_OK_BITS 1 35539 #define CL49_USERB0_LSM_STATUS_SIGNAL_OK_SHIFT 14 35540 35541 /* CL49_UserB0 :: lsm_status :: reserved0 [13:13] */ 35542 #define CL49_USERB0_LSM_STATUS_RESERVED0_MASK 0x2000 35543 #define CL49_USERB0_LSM_STATUS_RESERVED0_ALIGN 0 35544 #define CL49_USERB0_LSM_STATUS_RESERVED0_BITS 1 35545 #define CL49_USERB0_LSM_STATUS_RESERVED0_SHIFT 13 35546 35547 /* CL49_UserB0 :: lsm_status :: llsm_state [12:04] */ 35548 #define CL49_USERB0_LSM_STATUS_LLSM_STATE_MASK 0x1ff0 35549 #define CL49_USERB0_LSM_STATUS_LLSM_STATE_ALIGN 0 35550 #define CL49_USERB0_LSM_STATUS_LLSM_STATE_BITS 9 35551 #define CL49_USERB0_LSM_STATUS_LLSM_STATE_SHIFT 4 35552 35553 /* CL49_UserB0 :: lsm_status :: lsm_state [03:00] */ 35554 #define CL49_USERB0_LSM_STATUS_LSM_STATE_MASK 0x000f 35555 #define CL49_USERB0_LSM_STATUS_LSM_STATE_ALIGN 0 35556 #define CL49_USERB0_LSM_STATUS_LSM_STATE_BITS 4 35557 #define CL49_USERB0_LSM_STATUS_LSM_STATE_SHIFT 0 35558 35559 35560 /**************************************************************************** 35561 * CL49_UserB0 :: Control 35562 */ 35563 /* CL49_UserB0 :: Control :: r2_rx_msg_len_32bytes [15:15] */ 35564 #define CL49_USERB0_CONTROL_R2_RX_MSG_LEN_32BYTES_MASK 0x8000 35565 #define CL49_USERB0_CONTROL_R2_RX_MSG_LEN_32BYTES_ALIGN 0 35566 #define CL49_USERB0_CONTROL_R2_RX_MSG_LEN_32BYTES_BITS 1 35567 #define CL49_USERB0_CONTROL_R2_RX_MSG_LEN_32BYTES_SHIFT 15 35568 35569 /* CL49_UserB0 :: Control :: r2_rx_HiGig2_TB_en [14:14] */ 35570 #define CL49_USERB0_CONTROL_R2_RX_HIGIG2_TB_EN_MASK 0x4000 35571 #define CL49_USERB0_CONTROL_R2_RX_HIGIG2_TB_EN_ALIGN 0 35572 #define CL49_USERB0_CONTROL_R2_RX_HIGIG2_TB_EN_BITS 1 35573 #define CL49_USERB0_CONTROL_R2_RX_HIGIG2_TB_EN_SHIFT 14 35574 35575 /* CL49_UserB0 :: Control :: r2_rx_HiGig2_en [13:13] */ 35576 #define CL49_USERB0_CONTROL_R2_RX_HIGIG2_EN_MASK 0x2000 35577 #define CL49_USERB0_CONTROL_R2_RX_HIGIG2_EN_ALIGN 0 35578 #define CL49_USERB0_CONTROL_R2_RX_HIGIG2_EN_BITS 1 35579 #define CL49_USERB0_CONTROL_R2_RX_HIGIG2_EN_SHIFT 13 35580 35581 /* CL49_UserB0 :: Control :: rx_msg_len_32bytes [12:12] */ 35582 #define CL49_USERB0_CONTROL_RX_MSG_LEN_32BYTES_MASK 0x1000 35583 #define CL49_USERB0_CONTROL_RX_MSG_LEN_32BYTES_ALIGN 0 35584 #define CL49_USERB0_CONTROL_RX_MSG_LEN_32BYTES_BITS 1 35585 #define CL49_USERB0_CONTROL_RX_MSG_LEN_32BYTES_SHIFT 12 35586 35587 /* CL49_UserB0 :: Control :: rx_HiGig2_TB_en [11:11] */ 35588 #define CL49_USERB0_CONTROL_RX_HIGIG2_TB_EN_MASK 0x0800 35589 #define CL49_USERB0_CONTROL_RX_HIGIG2_TB_EN_ALIGN 0 35590 #define CL49_USERB0_CONTROL_RX_HIGIG2_TB_EN_BITS 1 35591 #define CL49_USERB0_CONTROL_RX_HIGIG2_TB_EN_SHIFT 11 35592 35593 /* CL49_UserB0 :: Control :: rx_HiGig2_en [10:10] */ 35594 #define CL49_USERB0_CONTROL_RX_HIGIG2_EN_MASK 0x0400 35595 #define CL49_USERB0_CONTROL_RX_HIGIG2_EN_ALIGN 0 35596 #define CL49_USERB0_CONTROL_RX_HIGIG2_EN_BITS 1 35597 #define CL49_USERB0_CONTROL_RX_HIGIG2_EN_SHIFT 10 35598 35599 /* CL49_UserB0 :: Control :: r2_ckgate_en_ovr_value [09:09] */ 35600 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_VALUE_MASK 0x0200 35601 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_VALUE_ALIGN 0 35602 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_VALUE_BITS 1 35603 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_VALUE_SHIFT 9 35604 35605 /* CL49_UserB0 :: Control :: r2_ckgate_en_ovr_ctrl [08:08] */ 35606 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_CTRL_MASK 0x0100 35607 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_CTRL_ALIGN 0 35608 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_CTRL_BITS 1 35609 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_CTRL_SHIFT 8 35610 35611 /* CL49_UserB0 :: Control :: cl82_ckgate_en_ovr_value [07:07] */ 35612 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_VALUE_MASK 0x0080 35613 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_VALUE_ALIGN 0 35614 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_VALUE_BITS 1 35615 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_VALUE_SHIFT 7 35616 35617 /* CL49_UserB0 :: Control :: cl82_ckgate_en_ovr_ctrl [06:06] */ 35618 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_CTRL_MASK 0x0040 35619 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_CTRL_ALIGN 0 35620 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_CTRL_BITS 1 35621 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_CTRL_SHIFT 6 35622 35623 /* CL49_UserB0 :: Control :: fast_lock_cya [05:05] */ 35624 #define CL49_USERB0_CONTROL_FAST_LOCK_CYA_MASK 0x0020 35625 #define CL49_USERB0_CONTROL_FAST_LOCK_CYA_ALIGN 0 35626 #define CL49_USERB0_CONTROL_FAST_LOCK_CYA_BITS 1 35627 #define CL49_USERB0_CONTROL_FAST_LOCK_CYA_SHIFT 5 35628 35629 /* CL49_UserB0 :: Control :: prbs9rx_en [04:04] */ 35630 #define CL49_USERB0_CONTROL_PRBS9RX_EN_MASK 0x0010 35631 #define CL49_USERB0_CONTROL_PRBS9RX_EN_ALIGN 0 35632 #define CL49_USERB0_CONTROL_PRBS9RX_EN_BITS 1 35633 #define CL49_USERB0_CONTROL_PRBS9RX_EN_SHIFT 4 35634 35635 /* CL49_UserB0 :: Control :: descramblerControl [03:02] */ 35636 #define CL49_USERB0_CONTROL_DESCRAMBLERCONTROL_MASK 0x000c 35637 #define CL49_USERB0_CONTROL_DESCRAMBLERCONTROL_ALIGN 0 35638 #define CL49_USERB0_CONTROL_DESCRAMBLERCONTROL_BITS 2 35639 #define CL49_USERB0_CONTROL_DESCRAMBLERCONTROL_SHIFT 2 35640 35641 /* CL49_UserB0 :: Control :: reserved_for_eco0 [01:00] */ 35642 #define CL49_USERB0_CONTROL_RESERVED_FOR_ECO0_MASK 0x0003 35643 #define CL49_USERB0_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 35644 #define CL49_USERB0_CONTROL_RESERVED_FOR_ECO0_BITS 2 35645 #define CL49_USERB0_CONTROL_RESERVED_FOR_ECO0_SHIFT 0 35646 35647 35648 /**************************************************************************** 35649 * CL49_UserB0 :: Status 35650 */ 35651 /* CL49_UserB0 :: Status :: reserved0 [15:05] */ 35652 #define CL49_USERB0_STATUS_RESERVED0_MASK 0xffe0 35653 #define CL49_USERB0_STATUS_RESERVED0_ALIGN 0 35654 #define CL49_USERB0_STATUS_RESERVED0_BITS 11 35655 #define CL49_USERB0_STATUS_RESERVED0_SHIFT 5 35656 35657 /* CL49_UserB0 :: Status :: pseudo_lock [04:04] */ 35658 #define CL49_USERB0_STATUS_PSEUDO_LOCK_MASK 0x0010 35659 #define CL49_USERB0_STATUS_PSEUDO_LOCK_ALIGN 0 35660 #define CL49_USERB0_STATUS_PSEUDO_LOCK_BITS 1 35661 #define CL49_USERB0_STATUS_PSEUDO_LOCK_SHIFT 4 35662 35663 /* CL49_UserB0 :: Status :: prbs_lock [03:03] */ 35664 #define CL49_USERB0_STATUS_PRBS_LOCK_MASK 0x0008 35665 #define CL49_USERB0_STATUS_PRBS_LOCK_ALIGN 0 35666 #define CL49_USERB0_STATUS_PRBS_LOCK_BITS 1 35667 #define CL49_USERB0_STATUS_PRBS_LOCK_SHIFT 3 35668 35669 /* CL49_UserB0 :: Status :: reserved_for_eco1 [02:00] */ 35670 #define CL49_USERB0_STATUS_RESERVED_FOR_ECO1_MASK 0x0007 35671 #define CL49_USERB0_STATUS_RESERVED_FOR_ECO1_ALIGN 0 35672 #define CL49_USERB0_STATUS_RESERVED_FOR_ECO1_BITS 3 35673 #define CL49_USERB0_STATUS_RESERVED_FOR_ECO1_SHIFT 0 35674 35675 35676 /**************************************************************************** 35677 * CL49_UserB0 :: shcounter 35678 */ 35679 /* CL49_UserB0 :: shcounter :: valid_sh_cnt [15:08] */ 35680 #define CL49_USERB0_SHCOUNTER_VALID_SH_CNT_MASK 0xff00 35681 #define CL49_USERB0_SHCOUNTER_VALID_SH_CNT_ALIGN 0 35682 #define CL49_USERB0_SHCOUNTER_VALID_SH_CNT_BITS 8 35683 #define CL49_USERB0_SHCOUNTER_VALID_SH_CNT_SHIFT 8 35684 35685 /* CL49_UserB0 :: shcounter :: invalid_sh_cnt [07:00] */ 35686 #define CL49_USERB0_SHCOUNTER_INVALID_SH_CNT_MASK 0x00ff 35687 #define CL49_USERB0_SHCOUNTER_INVALID_SH_CNT_ALIGN 0 35688 #define CL49_USERB0_SHCOUNTER_INVALID_SH_CNT_BITS 8 35689 #define CL49_USERB0_SHCOUNTER_INVALID_SH_CNT_SHIFT 0 35690 35691 35692 /**************************************************************************** 35693 * CL49_UserB0 :: timer125us 35694 */ 35695 /* CL49_UserB0 :: timer125us :: timer125us [15:00] */ 35696 #define CL49_USERB0_TIMER125US_TIMER125US_MASK 0xffff 35697 #define CL49_USERB0_TIMER125US_TIMER125US_ALIGN 0 35698 #define CL49_USERB0_TIMER125US_TIMER125US_BITS 16 35699 #define CL49_USERB0_TIMER125US_TIMER125US_SHIFT 0 35700 35701 35702 /**************************************************************************** 35703 * CL49_UserB0 :: bercnt 35704 */ 35705 /* CL49_UserB0 :: bercnt :: reserved0 [15:15] */ 35706 #define CL49_USERB0_BERCNT_RESERVED0_MASK 0x8000 35707 #define CL49_USERB0_BERCNT_RESERVED0_ALIGN 0 35708 #define CL49_USERB0_BERCNT_RESERVED0_BITS 1 35709 #define CL49_USERB0_BERCNT_RESERVED0_SHIFT 15 35710 35711 /* CL49_UserB0 :: bercnt :: dis_RX_E_cya [14:14] */ 35712 #define CL49_USERB0_BERCNT_DIS_RX_E_CYA_MASK 0x4000 35713 #define CL49_USERB0_BERCNT_DIS_RX_E_CYA_ALIGN 0 35714 #define CL49_USERB0_BERCNT_DIS_RX_E_CYA_BITS 1 35715 #define CL49_USERB0_BERCNT_DIS_RX_E_CYA_SHIFT 14 35716 35717 /* CL49_UserB0 :: bercnt :: bypass_R2_cl49rxsm [13:13] */ 35718 #define CL49_USERB0_BERCNT_BYPASS_R2_CL49RXSM_MASK 0x2000 35719 #define CL49_USERB0_BERCNT_BYPASS_R2_CL49RXSM_ALIGN 0 35720 #define CL49_USERB0_BERCNT_BYPASS_R2_CL49RXSM_BITS 1 35721 #define CL49_USERB0_BERCNT_BYPASS_R2_CL49RXSM_SHIFT 13 35722 35723 /* CL49_UserB0 :: bercnt :: bypass_cl49rxsm [12:12] */ 35724 #define CL49_USERB0_BERCNT_BYPASS_CL49RXSM_MASK 0x1000 35725 #define CL49_USERB0_BERCNT_BYPASS_CL49RXSM_ALIGN 0 35726 #define CL49_USERB0_BERCNT_BYPASS_CL49RXSM_BITS 1 35727 #define CL49_USERB0_BERCNT_BYPASS_CL49RXSM_SHIFT 12 35728 35729 /* CL49_UserB0 :: bercnt :: dis_cl49R2_bermon [11:11] */ 35730 #define CL49_USERB0_BERCNT_DIS_CL49R2_BERMON_MASK 0x0800 35731 #define CL49_USERB0_BERCNT_DIS_CL49R2_BERMON_ALIGN 0 35732 #define CL49_USERB0_BERCNT_DIS_CL49R2_BERMON_BITS 1 35733 #define CL49_USERB0_BERCNT_DIS_CL49R2_BERMON_SHIFT 11 35734 35735 /* CL49_UserB0 :: bercnt :: IdleErrorCount_en [10:10] */ 35736 #define CL49_USERB0_BERCNT_IDLEERRORCOUNT_EN_MASK 0x0400 35737 #define CL49_USERB0_BERCNT_IDLEERRORCOUNT_EN_ALIGN 0 35738 #define CL49_USERB0_BERCNT_IDLEERRORCOUNT_EN_BITS 1 35739 #define CL49_USERB0_BERCNT_IDLEERRORCOUNT_EN_SHIFT 10 35740 35741 /* CL49_UserB0 :: bercnt :: match_cnt [09:06] */ 35742 #define CL49_USERB0_BERCNT_MATCH_CNT_MASK 0x03c0 35743 #define CL49_USERB0_BERCNT_MATCH_CNT_ALIGN 0 35744 #define CL49_USERB0_BERCNT_MATCH_CNT_BITS 4 35745 #define CL49_USERB0_BERCNT_MATCH_CNT_SHIFT 6 35746 35747 /* CL49_UserB0 :: bercnt :: bercnt [05:00] */ 35748 #define CL49_USERB0_BERCNT_BERCNT_MASK 0x003f 35749 #define CL49_USERB0_BERCNT_BERCNT_ALIGN 0 35750 #define CL49_USERB0_BERCNT_BERCNT_BITS 6 35751 #define CL49_USERB0_BERCNT_BERCNT_SHIFT 0 35752 35753 35754 /**************************************************************************** 35755 * CL49_UserB0 :: bermon_status 35756 */ 35757 /* CL49_UserB0 :: bermon_status :: reserved0 [15:14] */ 35758 #define CL49_USERB0_BERMON_STATUS_RESERVED0_MASK 0xc000 35759 #define CL49_USERB0_BERMON_STATUS_RESERVED0_ALIGN 0 35760 #define CL49_USERB0_BERMON_STATUS_RESERVED0_BITS 2 35761 #define CL49_USERB0_BERMON_STATUS_RESERVED0_SHIFT 14 35762 35763 /* CL49_UserB0 :: bermon_status :: hi_ber [13:13] */ 35764 #define CL49_USERB0_BERMON_STATUS_HI_BER_MASK 0x2000 35765 #define CL49_USERB0_BERMON_STATUS_HI_BER_ALIGN 0 35766 #define CL49_USERB0_BERMON_STATUS_HI_BER_BITS 1 35767 #define CL49_USERB0_BERMON_STATUS_HI_BER_SHIFT 13 35768 35769 /* CL49_UserB0 :: bermon_status :: t125us_done [12:12] */ 35770 #define CL49_USERB0_BERMON_STATUS_T125US_DONE_MASK 0x1000 35771 #define CL49_USERB0_BERMON_STATUS_T125US_DONE_ALIGN 0 35772 #define CL49_USERB0_BERMON_STATUS_T125US_DONE_BITS 1 35773 #define CL49_USERB0_BERMON_STATUS_T125US_DONE_SHIFT 12 35774 35775 /* CL49_UserB0 :: bermon_status :: lbermon_state [11:06] */ 35776 #define CL49_USERB0_BERMON_STATUS_LBERMON_STATE_MASK 0x0fc0 35777 #define CL49_USERB0_BERMON_STATUS_LBERMON_STATE_ALIGN 0 35778 #define CL49_USERB0_BERMON_STATUS_LBERMON_STATE_BITS 6 35779 #define CL49_USERB0_BERMON_STATUS_LBERMON_STATE_SHIFT 6 35780 35781 /* CL49_UserB0 :: bermon_status :: bermon_state [05:00] */ 35782 #define CL49_USERB0_BERMON_STATUS_BERMON_STATE_MASK 0x003f 35783 #define CL49_USERB0_BERMON_STATUS_BERMON_STATE_ALIGN 0 35784 #define CL49_USERB0_BERMON_STATUS_BERMON_STATE_BITS 6 35785 #define CL49_USERB0_BERMON_STATUS_BERMON_STATE_SHIFT 0 35786 35787 35788 /**************************************************************************** 35789 * CL49_UserB0 :: tstcnt1 35790 */ 35791 /* CL49_UserB0 :: tstcnt1 :: sync_cnt [15:08] */ 35792 #define CL49_USERB0_TSTCNT1_SYNC_CNT_MASK 0xff00 35793 #define CL49_USERB0_TSTCNT1_SYNC_CNT_ALIGN 0 35794 #define CL49_USERB0_TSTCNT1_SYNC_CNT_BITS 8 35795 #define CL49_USERB0_TSTCNT1_SYNC_CNT_SHIFT 8 35796 35797 /* CL49_UserB0 :: tstcnt1 :: block_cnt [07:00] */ 35798 #define CL49_USERB0_TSTCNT1_BLOCK_CNT_MASK 0x00ff 35799 #define CL49_USERB0_TSTCNT1_BLOCK_CNT_ALIGN 0 35800 #define CL49_USERB0_TSTCNT1_BLOCK_CNT_BITS 8 35801 #define CL49_USERB0_TSTCNT1_BLOCK_CNT_SHIFT 0 35802 35803 35804 /**************************************************************************** 35805 * Warpcore_USER_CL73_UserB0 35806 */ 35807 /**************************************************************************** 35808 * CL73_UserB0 :: CL73_UCtrl1 35809 */ 35810 /* CL73_UserB0 :: CL73_UCtrl1 :: reserved0 [15:13] */ 35811 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_MASK 0xe000 35812 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_ALIGN 0 35813 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_BITS 3 35814 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_SHIFT 13 35815 35816 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_lossOfSyncFail_en [12:12] */ 35817 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_MASK 0x1000 35818 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_ALIGN 0 35819 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_BITS 1 35820 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_SHIFT 12 35821 35822 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_parDet_dis [11:11] */ 35823 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_MASK 0x0800 35824 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_ALIGN 0 35825 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_BITS 1 35826 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_SHIFT 11 35827 35828 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_allowCl37AN [10:10] */ 35829 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_MASK 0x0400 35830 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_ALIGN 0 35831 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_BITS 1 35832 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_SHIFT 10 35833 35834 /* CL73_UserB0 :: CL73_UCtrl1 :: longParDetTimer_dis [09:09] */ 35835 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_MASK 0x0200 35836 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_ALIGN 0 35837 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_BITS 1 35838 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_SHIFT 9 35839 35840 /* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimer_dis [08:08] */ 35841 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_MASK 0x0100 35842 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_ALIGN 0 35843 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_BITS 1 35844 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_SHIFT 8 35845 35846 /* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimerQual_en [07:07] */ 35847 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_MASK 0x0080 35848 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_ALIGN 0 35849 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_BITS 1 35850 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_SHIFT 7 35851 35852 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_over [06:06] */ 35853 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_MASK 0x0040 35854 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_ALIGN 0 35855 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_BITS 1 35856 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_SHIFT 6 35857 35858 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_val [05:05] */ 35859 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_MASK 0x0020 35860 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_ALIGN 0 35861 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_BITS 1 35862 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_SHIFT 5 35863 35864 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart_wo_link_fail [04:04] */ 35865 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_MASK 0x0010 35866 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_ALIGN 0 35867 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_BITS 1 35868 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_SHIFT 4 35869 35870 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart [03:03] */ 35871 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_MASK 0x0008 35872 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_ALIGN 0 35873 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_BITS 1 35874 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_SHIFT 3 35875 35876 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl37_restart [02:02] */ 35877 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_MASK 0x0004 35878 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_ALIGN 0 35879 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_BITS 1 35880 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_SHIFT 2 35881 35882 /* CL73_UserB0 :: CL73_UCtrl1 :: CL73_Ustat1_muxsel [01:01] */ 35883 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_MASK 0x0002 35884 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_ALIGN 0 35885 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_BITS 1 35886 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_SHIFT 1 35887 35888 /* CL73_UserB0 :: CL73_UCtrl1 :: force_cl73_tx_omux_en [00:00] */ 35889 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_MASK 0x0001 35890 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_ALIGN 0 35891 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_BITS 1 35892 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_SHIFT 0 35893 35894 35895 /**************************************************************************** 35896 * CL73_UserB0 :: CL73_Ustat1 35897 */ 35898 /* CL73_UserB0 :: CL73_Ustat1 :: reserved0 [15:12] */ 35899 #define CL73_USERB0_CL73_USTAT1_RESERVED0_MASK 0xf000 35900 #define CL73_USERB0_CL73_USTAT1_RESERVED0_ALIGN 0 35901 #define CL73_USERB0_CL73_USTAT1_RESERVED0_BITS 4 35902 #define CL73_USERB0_CL73_USTAT1_RESERVED0_SHIFT 12 35903 35904 /* CL73_UserB0 :: CL73_Ustat1 :: arb_fsm [11:00] */ 35905 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_MASK 0x0fff 35906 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_ALIGN 0 35907 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_BITS 12 35908 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_SHIFT 0 35909 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_AN_ENABLE 1 35910 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_TRANSMIT_DISABLE 2 35911 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_ABILITY_DETECT 4 35912 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_ACKNOWLEDGE_DETECT 8 35913 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_COMPLETE_ACKNOWLEDGE 16 35914 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_NEXT_PAGE_WAIT 32 35915 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_AN_GOOD_CHECK 64 35916 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_AN_GOOD 128 35917 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_LINK_STATUS_CHECK 256 35918 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_PARALLEL_DETECTION_FAULT 512 35919 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_AN_GOOD_CHECK_BAM37 1024 35920 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_TRANSMIT_DISABLE_BAM37 2048 35921 35922 35923 /**************************************************************************** 35924 * CL73_UserB0 :: CL73_BAMCtrl1 35925 */ 35926 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamEn [15:15] */ 35927 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_MASK 0x8000 35928 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_ALIGN 0 35929 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_BITS 1 35930 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_SHIFT 15 35931 35932 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_station_mngr_en [14:14] */ 35933 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_MASK 0x4000 35934 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_ALIGN 0 35935 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_BITS 1 35936 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_SHIFT 14 35937 35938 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamNP_after_bp_en [13:13] */ 35939 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_MASK 0x2000 35940 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_ALIGN 0 35941 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_BITS 1 35942 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_SHIFT 13 35943 35944 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_en [12:12] */ 35945 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_MASK 0x1000 35946 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_ALIGN 0 35947 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_BITS 1 35948 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_SHIFT 12 35949 35950 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_step [11:11] */ 35951 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_MASK 0x0800 35952 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_ALIGN 0 35953 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_BITS 1 35954 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_SHIFT 11 35955 35956 /* CL73_UserB0 :: CL73_BAMCtrl1 :: reserved0 [10:10] */ 35957 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_MASK 0x0400 35958 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_ALIGN 0 35959 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_BITS 1 35960 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_SHIFT 10 35961 35962 /* CL73_UserB0 :: CL73_BAMCtrl1 :: UD_code_field [09:00] */ 35963 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_MASK 0x03ff 35964 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_ALIGN 0 35965 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_BITS 10 35966 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_SHIFT 0 35967 35968 35969 /**************************************************************************** 35970 * CL73_UserB0 :: CL73_BAMCtrl2 35971 */ 35972 /* CL73_UserB0 :: CL73_BAMCtrl2 :: UD_code_field [15:00] */ 35973 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_MASK 0xffff 35974 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_ALIGN 0 35975 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_BITS 16 35976 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_SHIFT 0 35977 35978 35979 /**************************************************************************** 35980 * CL73_UserB0 :: CL73_BAMCtrl3 35981 */ 35982 /* CL73_UserB0 :: CL73_BAMCtrl3 :: UD_code_field [15:00] */ 35983 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_MASK 0xffff 35984 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_ALIGN 0 35985 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_BITS 16 35986 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_SHIFT 0 35987 35988 35989 /**************************************************************************** 35990 * CL73_UserB0 :: CL73_BAMStat1 35991 */ 35992 /* CL73_UserB0 :: CL73_BAMStat1 :: reserved0 [15:10] */ 35993 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_MASK 0xfc00 35994 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_ALIGN 0 35995 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_BITS 6 35996 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_SHIFT 10 35997 35998 /* CL73_UserB0 :: CL73_BAMStat1 :: LP_UD_code_field [09:00] */ 35999 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_MASK 0x03ff 36000 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_ALIGN 0 36001 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_BITS 10 36002 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_SHIFT 0 36003 36004 36005 /**************************************************************************** 36006 * CL73_UserB0 :: CL73_BAMStat2 36007 */ 36008 /* CL73_UserB0 :: CL73_BAMStat2 :: LP_UD_code_field [15:00] */ 36009 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_MASK 0xffff 36010 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_ALIGN 0 36011 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_BITS 16 36012 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_SHIFT 0 36013 36014 36015 /**************************************************************************** 36016 * CL73_UserB0 :: CL73_BAMStat3 36017 */ 36018 /* CL73_UserB0 :: CL73_BAMStat3 :: LP_UD_code_field [15:00] */ 36019 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_MASK 0xffff 36020 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_ALIGN 0 36021 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_BITS 16 36022 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_SHIFT 0 36023 36024 36025 /**************************************************************************** 36026 * CL73_UserB0 :: CL73_UCtrl2 36027 */ 36028 /* CL73_UserB0 :: CL73_UCtrl2 :: reserved0 [15:12] */ 36029 #define CL73_USERB0_CL73_UCTRL2_RESERVED0_MASK 0xf000 36030 #define CL73_USERB0_CL73_UCTRL2_RESERVED0_ALIGN 0 36031 #define CL73_USERB0_CL73_UCTRL2_RESERVED0_BITS 4 36032 #define CL73_USERB0_CL73_UCTRL2_RESERVED0_SHIFT 12 36033 36034 /* CL73_UserB0 :: CL73_UCtrl2 :: useLink [11:11] */ 36035 #define CL73_USERB0_CL73_UCTRL2_USELINK_MASK 0x0800 36036 #define CL73_USERB0_CL73_UCTRL2_USELINK_ALIGN 0 36037 #define CL73_USERB0_CL73_UCTRL2_USELINK_BITS 1 36038 #define CL73_USERB0_CL73_UCTRL2_USELINK_SHIFT 11 36039 36040 /* CL73_UserB0 :: CL73_UCtrl2 :: rx_dme_status_sel [10:09] */ 36041 #define CL73_USERB0_CL73_UCTRL2_RX_DME_STATUS_SEL_MASK 0x0600 36042 #define CL73_USERB0_CL73_UCTRL2_RX_DME_STATUS_SEL_ALIGN 0 36043 #define CL73_USERB0_CL73_UCTRL2_RX_DME_STATUS_SEL_BITS 2 36044 #define CL73_USERB0_CL73_UCTRL2_RX_DME_STATUS_SEL_SHIFT 9 36045 36046 /* CL73_UserB0 :: CL73_UCtrl2 :: cl73_suppress_mr_page_rx_dis [08:08] */ 36047 #define CL73_USERB0_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_MASK 0x0100 36048 #define CL73_USERB0_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_ALIGN 0 36049 #define CL73_USERB0_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_BITS 1 36050 #define CL73_USERB0_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_SHIFT 8 36051 36052 /* CL73_UserB0 :: CL73_UCtrl2 :: cl73_record_2NP_after_BP_en [07:07] */ 36053 #define CL73_USERB0_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_MASK 0x0080 36054 #define CL73_USERB0_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_ALIGN 0 36055 #define CL73_USERB0_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_BITS 1 36056 #define CL73_USERB0_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_SHIFT 7 36057 36058 /* CL73_UserB0 :: CL73_UCtrl2 :: cl73_BAMStat123_sel [06:04] */ 36059 #define CL73_USERB0_CL73_UCTRL2_CL73_BAMSTAT123_SEL_MASK 0x0070 36060 #define CL73_USERB0_CL73_UCTRL2_CL73_BAMSTAT123_SEL_ALIGN 0 36061 #define CL73_USERB0_CL73_UCTRL2_CL73_BAMSTAT123_SEL_BITS 3 36062 #define CL73_USERB0_CL73_UCTRL2_CL73_BAMSTAT123_SEL_SHIFT 4 36063 36064 /* CL73_UserB0 :: CL73_UCtrl2 :: sigdet_timer_dis [03:03] */ 36065 #define CL73_USERB0_CL73_UCTRL2_SIGDET_TIMER_DIS_MASK 0x0008 36066 #define CL73_USERB0_CL73_UCTRL2_SIGDET_TIMER_DIS_ALIGN 0 36067 #define CL73_USERB0_CL73_UCTRL2_SIGDET_TIMER_DIS_BITS 1 36068 #define CL73_USERB0_CL73_UCTRL2_SIGDET_TIMER_DIS_SHIFT 3 36069 36070 /* CL73_UserB0 :: CL73_UCtrl2 :: an_good_check_bam37_dis [02:02] */ 36071 #define CL73_USERB0_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_MASK 0x0004 36072 #define CL73_USERB0_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_ALIGN 0 36073 #define CL73_USERB0_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_BITS 1 36074 #define CL73_USERB0_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_SHIFT 2 36075 36076 /* CL73_UserB0 :: CL73_UCtrl2 :: config_match_dis [01:01] */ 36077 #define CL73_USERB0_CL73_UCTRL2_CONFIG_MATCH_DIS_MASK 0x0002 36078 #define CL73_USERB0_CL73_UCTRL2_CONFIG_MATCH_DIS_ALIGN 0 36079 #define CL73_USERB0_CL73_UCTRL2_CONFIG_MATCH_DIS_BITS 1 36080 #define CL73_USERB0_CL73_UCTRL2_CONFIG_MATCH_DIS_SHIFT 1 36081 36082 /* CL73_UserB0 :: CL73_UCtrl2 :: hold_lp_ability [00:00] */ 36083 #define CL73_USERB0_CL73_UCTRL2_HOLD_LP_ABILITY_MASK 0x0001 36084 #define CL73_USERB0_CL73_UCTRL2_HOLD_LP_ABILITY_ALIGN 0 36085 #define CL73_USERB0_CL73_UCTRL2_HOLD_LP_ABILITY_BITS 1 36086 #define CL73_USERB0_CL73_UCTRL2_HOLD_LP_ABILITY_SHIFT 0 36087 36088 36089 /**************************************************************************** 36090 * CL73_UserB0 :: CL73_UCtrl3 36091 */ 36092 /* CL73_UserB0 :: CL73_UCtrl3 :: anerr_max [15:00] */ 36093 #define CL73_USERB0_CL73_UCTRL3_ANERR_MAX_MASK 0xffff 36094 #define CL73_USERB0_CL73_UCTRL3_ANERR_MAX_ALIGN 0 36095 #define CL73_USERB0_CL73_UCTRL3_ANERR_MAX_BITS 16 36096 #define CL73_USERB0_CL73_UCTRL3_ANERR_MAX_SHIFT 0 36097 36098 36099 /**************************************************************************** 36100 * CL73_UserB0 :: CL73_UCtrl4 36101 */ 36102 /* CL73_UserB0 :: CL73_UCtrl4 :: reserved0 [15:09] */ 36103 #define CL73_USERB0_CL73_UCTRL4_RESERVED0_MASK 0xfe00 36104 #define CL73_USERB0_CL73_UCTRL4_RESERVED0_ALIGN 0 36105 #define CL73_USERB0_CL73_UCTRL4_RESERVED0_BITS 7 36106 #define CL73_USERB0_CL73_UCTRL4_RESERVED0_SHIFT 9 36107 36108 /* CL73_UserB0 :: CL73_UCtrl4 :: anerr_timer_mask [08:03] */ 36109 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_MASK_MASK 0x01f8 36110 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_MASK_ALIGN 0 36111 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_MASK_BITS 6 36112 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_MASK_SHIFT 3 36113 36114 /* CL73_UserB0 :: CL73_UCtrl4 :: disable_sigdet_timer [02:02] */ 36115 #define CL73_USERB0_CL73_UCTRL4_DISABLE_SIGDET_TIMER_MASK 0x0004 36116 #define CL73_USERB0_CL73_UCTRL4_DISABLE_SIGDET_TIMER_ALIGN 0 36117 #define CL73_USERB0_CL73_UCTRL4_DISABLE_SIGDET_TIMER_BITS 1 36118 #define CL73_USERB0_CL73_UCTRL4_DISABLE_SIGDET_TIMER_SHIFT 2 36119 36120 /* CL73_UserB0 :: CL73_UCtrl4 :: cl73_anerr_status_sel [01:01] */ 36121 #define CL73_USERB0_CL73_UCTRL4_CL73_ANERR_STATUS_SEL_MASK 0x0002 36122 #define CL73_USERB0_CL73_UCTRL4_CL73_ANERR_STATUS_SEL_ALIGN 0 36123 #define CL73_USERB0_CL73_UCTRL4_CL73_ANERR_STATUS_SEL_BITS 1 36124 #define CL73_USERB0_CL73_UCTRL4_CL73_ANERR_STATUS_SEL_SHIFT 1 36125 36126 /* CL73_UserB0 :: CL73_UCtrl4 :: anerr_timer_en [00:00] */ 36127 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_EN_MASK 0x0001 36128 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_EN_ALIGN 0 36129 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_EN_BITS 1 36130 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_EN_SHIFT 0 36131 36132 36133 /**************************************************************************** 36134 * CL73_UserB0 :: CL73_EEECtrl 36135 */ 36136 /* CL73_UserB0 :: CL73_EEECtrl :: CL73_eeeEn [15:15] */ 36137 #define CL73_USERB0_CL73_EEECTRL_CL73_EEEEN_MASK 0x8000 36138 #define CL73_USERB0_CL73_EEECTRL_CL73_EEEEN_ALIGN 0 36139 #define CL73_USERB0_CL73_EEECTRL_CL73_EEEEN_BITS 1 36140 #define CL73_USERB0_CL73_EEECTRL_CL73_EEEEN_SHIFT 15 36141 36142 /* CL73_UserB0 :: CL73_EEECtrl :: CL73_eeeNP_after_bp_en [14:14] */ 36143 #define CL73_USERB0_CL73_EEECTRL_CL73_EEENP_AFTER_BP_EN_MASK 0x4000 36144 #define CL73_USERB0_CL73_EEECTRL_CL73_EEENP_AFTER_BP_EN_ALIGN 0 36145 #define CL73_USERB0_CL73_EEECTRL_CL73_EEENP_AFTER_BP_EN_BITS 1 36146 #define CL73_USERB0_CL73_EEECTRL_CL73_EEENP_AFTER_BP_EN_SHIFT 14 36147 36148 /* CL73_UserB0 :: CL73_EEECtrl :: hold_eee_lp_ability [13:13] */ 36149 #define CL73_USERB0_CL73_EEECTRL_HOLD_EEE_LP_ABILITY_MASK 0x2000 36150 #define CL73_USERB0_CL73_EEECTRL_HOLD_EEE_LP_ABILITY_ALIGN 0 36151 #define CL73_USERB0_CL73_EEECTRL_HOLD_EEE_LP_ABILITY_BITS 1 36152 #define CL73_USERB0_CL73_EEECTRL_HOLD_EEE_LP_ABILITY_SHIFT 13 36153 36154 /* CL73_UserB0 :: CL73_EEECtrl :: reserved0 [12:00] */ 36155 #define CL73_USERB0_CL73_EEECTRL_RESERVED0_MASK 0x1fff 36156 #define CL73_USERB0_CL73_EEECTRL_RESERVED0_ALIGN 0 36157 #define CL73_USERB0_CL73_EEECTRL_RESERVED0_BITS 13 36158 #define CL73_USERB0_CL73_EEECTRL_RESERVED0_SHIFT 0 36159 36160 36161 /**************************************************************************** 36162 * Warpcore_USER_CL74_UserB0 36163 */ 36164 /**************************************************************************** 36165 * CL74_UserB0 :: uFecControl1 36166 */ 36167 /* CL74_UserB0 :: uFecControl1 :: dbg_enable [15:15] */ 36168 #define CL74_USERB0_UFECCONTROL1_DBG_ENABLE_MASK 0x8000 36169 #define CL74_USERB0_UFECCONTROL1_DBG_ENABLE_ALIGN 0 36170 #define CL74_USERB0_UFECCONTROL1_DBG_ENABLE_BITS 1 36171 #define CL74_USERB0_UFECCONTROL1_DBG_ENABLE_SHIFT 15 36172 36173 /* CL74_UserB0 :: uFecControl1 :: invParityCnt [14:11] */ 36174 #define CL74_USERB0_UFECCONTROL1_INVPARITYCNT_MASK 0x7800 36175 #define CL74_USERB0_UFECCONTROL1_INVPARITYCNT_ALIGN 0 36176 #define CL74_USERB0_UFECCONTROL1_INVPARITYCNT_BITS 4 36177 #define CL74_USERB0_UFECCONTROL1_INVPARITYCNT_SHIFT 11 36178 36179 /* CL74_UserB0 :: uFecControl1 :: good_parity_cnt [10:08] */ 36180 #define CL74_USERB0_UFECCONTROL1_GOOD_PARITY_CNT_MASK 0x0700 36181 #define CL74_USERB0_UFECCONTROL1_GOOD_PARITY_CNT_ALIGN 0 36182 #define CL74_USERB0_UFECCONTROL1_GOOD_PARITY_CNT_BITS 3 36183 #define CL74_USERB0_UFECCONTROL1_GOOD_PARITY_CNT_SHIFT 8 36184 36185 /* CL74_UserB0 :: uFecControl1 :: fec_dec_max_pm [07:02] */ 36186 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_MAX_PM_MASK 0x00fc 36187 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_MAX_PM_ALIGN 0 36188 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_MAX_PM_BITS 6 36189 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_MAX_PM_SHIFT 2 36190 36191 /* CL74_UserB0 :: uFecControl1 :: fec_enc_data_swap [01:01] */ 36192 #define CL74_USERB0_UFECCONTROL1_FEC_ENC_DATA_SWAP_MASK 0x0002 36193 #define CL74_USERB0_UFECCONTROL1_FEC_ENC_DATA_SWAP_ALIGN 0 36194 #define CL74_USERB0_UFECCONTROL1_FEC_ENC_DATA_SWAP_BITS 1 36195 #define CL74_USERB0_UFECCONTROL1_FEC_ENC_DATA_SWAP_SHIFT 1 36196 36197 /* CL74_UserB0 :: uFecControl1 :: fec_dec_data_swap [00:00] */ 36198 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_DATA_SWAP_MASK 0x0001 36199 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_DATA_SWAP_ALIGN 0 36200 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_DATA_SWAP_BITS 1 36201 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_DATA_SWAP_SHIFT 0 36202 36203 36204 /**************************************************************************** 36205 * CL74_UserB0 :: uFecControl2 36206 */ 36207 /* CL74_UserB0 :: uFecControl2 :: fec_dec_gap_count_mode [15:15] */ 36208 #define CL74_USERB0_UFECCONTROL2_FEC_DEC_GAP_COUNT_MODE_MASK 0x8000 36209 #define CL74_USERB0_UFECCONTROL2_FEC_DEC_GAP_COUNT_MODE_ALIGN 0 36210 #define CL74_USERB0_UFECCONTROL2_FEC_DEC_GAP_COUNT_MODE_BITS 1 36211 #define CL74_USERB0_UFECCONTROL2_FEC_DEC_GAP_COUNT_MODE_SHIFT 15 36212 36213 /* CL74_UserB0 :: uFecControl2 :: reserved0 [14:09] */ 36214 #define CL74_USERB0_UFECCONTROL2_RESERVED0_MASK 0x7e00 36215 #define CL74_USERB0_UFECCONTROL2_RESERVED0_ALIGN 0 36216 #define CL74_USERB0_UFECCONTROL2_RESERVED0_BITS 6 36217 #define CL74_USERB0_UFECCONTROL2_RESERVED0_SHIFT 9 36218 36219 /* CL74_UserB0 :: uFecControl2 :: fec_dec_pm_mode [08:04] */ 36220 #define CL74_USERB0_UFECCONTROL2_FEC_DEC_PM_MODE_MASK 0x01f0 36221 #define CL74_USERB0_UFECCONTROL2_FEC_DEC_PM_MODE_ALIGN 0 36222 #define CL74_USERB0_UFECCONTROL2_FEC_DEC_PM_MODE_BITS 5 36223 #define CL74_USERB0_UFECCONTROL2_FEC_DEC_PM_MODE_SHIFT 4 36224 36225 /* CL74_UserB0 :: uFecControl2 :: dbg_err_mode [03:03] */ 36226 #define CL74_USERB0_UFECCONTROL2_DBG_ERR_MODE_MASK 0x0008 36227 #define CL74_USERB0_UFECCONTROL2_DBG_ERR_MODE_ALIGN 0 36228 #define CL74_USERB0_UFECCONTROL2_DBG_ERR_MODE_BITS 1 36229 #define CL74_USERB0_UFECCONTROL2_DBG_ERR_MODE_SHIFT 3 36230 36231 /* CL74_UserB0 :: uFecControl2 :: reserved_for_eco1 [02:00] */ 36232 #define CL74_USERB0_UFECCONTROL2_RESERVED_FOR_ECO1_MASK 0x0007 36233 #define CL74_USERB0_UFECCONTROL2_RESERVED_FOR_ECO1_ALIGN 0 36234 #define CL74_USERB0_UFECCONTROL2_RESERVED_FOR_ECO1_BITS 3 36235 #define CL74_USERB0_UFECCONTROL2_RESERVED_FOR_ECO1_SHIFT 0 36236 36237 36238 /**************************************************************************** 36239 * CL74_UserB0 :: uFecControl3 36240 */ 36241 /* CL74_UserB0 :: uFecControl3 :: reserved0 [15:15] */ 36242 #define CL74_USERB0_UFECCONTROL3_RESERVED0_MASK 0x8000 36243 #define CL74_USERB0_UFECCONTROL3_RESERVED0_ALIGN 0 36244 #define CL74_USERB0_UFECCONTROL3_RESERVED0_BITS 1 36245 #define CL74_USERB0_UFECCONTROL3_RESERVED0_SHIFT 15 36246 36247 /* CL74_UserB0 :: uFecControl3 :: fec_dec_19b_burst_gap_count [14:12] */ 36248 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_19B_BURST_GAP_COUNT_MASK 0x7000 36249 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_19B_BURST_GAP_COUNT_ALIGN 0 36250 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_19B_BURST_GAP_COUNT_BITS 3 36251 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_19B_BURST_GAP_COUNT_SHIFT 12 36252 36253 /* CL74_UserB0 :: uFecControl3 :: reserved1 [11:11] */ 36254 #define CL74_USERB0_UFECCONTROL3_RESERVED1_MASK 0x0800 36255 #define CL74_USERB0_UFECCONTROL3_RESERVED1_ALIGN 0 36256 #define CL74_USERB0_UFECCONTROL3_RESERVED1_BITS 1 36257 #define CL74_USERB0_UFECCONTROL3_RESERVED1_SHIFT 11 36258 36259 /* CL74_UserB0 :: uFecControl3 :: fec_dec_18b_burst_gap_count [10:08] */ 36260 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_18B_BURST_GAP_COUNT_MASK 0x0700 36261 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_18B_BURST_GAP_COUNT_ALIGN 0 36262 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_18B_BURST_GAP_COUNT_BITS 3 36263 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_18B_BURST_GAP_COUNT_SHIFT 8 36264 36265 /* CL74_UserB0 :: uFecControl3 :: reserved2 [07:07] */ 36266 #define CL74_USERB0_UFECCONTROL3_RESERVED2_MASK 0x0080 36267 #define CL74_USERB0_UFECCONTROL3_RESERVED2_ALIGN 0 36268 #define CL74_USERB0_UFECCONTROL3_RESERVED2_BITS 1 36269 #define CL74_USERB0_UFECCONTROL3_RESERVED2_SHIFT 7 36270 36271 /* CL74_UserB0 :: uFecControl3 :: fec_dec_17b_burst_gap_count [06:04] */ 36272 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_17B_BURST_GAP_COUNT_MASK 0x0070 36273 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_17B_BURST_GAP_COUNT_ALIGN 0 36274 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_17B_BURST_GAP_COUNT_BITS 3 36275 #define CL74_USERB0_UFECCONTROL3_FEC_DEC_17B_BURST_GAP_COUNT_SHIFT 4 36276 36277 /* CL74_UserB0 :: uFecControl3 :: fec_error_en_ovr [03:03] */ 36278 #define CL74_USERB0_UFECCONTROL3_FEC_ERROR_EN_OVR_MASK 0x0008 36279 #define CL74_USERB0_UFECCONTROL3_FEC_ERROR_EN_OVR_ALIGN 0 36280 #define CL74_USERB0_UFECCONTROL3_FEC_ERROR_EN_OVR_BITS 1 36281 #define CL74_USERB0_UFECCONTROL3_FEC_ERROR_EN_OVR_SHIFT 3 36282 36283 /* CL74_UserB0 :: uFecControl3 :: fec_error_en_ovr_val [02:02] */ 36284 #define CL74_USERB0_UFECCONTROL3_FEC_ERROR_EN_OVR_VAL_MASK 0x0004 36285 #define CL74_USERB0_UFECCONTROL3_FEC_ERROR_EN_OVR_VAL_ALIGN 0 36286 #define CL74_USERB0_UFECCONTROL3_FEC_ERROR_EN_OVR_VAL_BITS 1 36287 #define CL74_USERB0_UFECCONTROL3_FEC_ERROR_EN_OVR_VAL_SHIFT 2 36288 36289 /* CL74_UserB0 :: uFecControl3 :: fec_enable_ovr [01:01] */ 36290 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_MASK 0x0002 36291 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_ALIGN 0 36292 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_BITS 1 36293 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_SHIFT 1 36294 36295 /* CL74_UserB0 :: uFecControl3 :: fec_enable_ovr_val [00:00] */ 36296 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_VAL_MASK 0x0001 36297 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_VAL_ALIGN 0 36298 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_VAL_BITS 1 36299 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_VAL_SHIFT 0 36300 36301 36302 /**************************************************************************** 36303 * CL74_UserB0 :: uFecdbg_edataL 36304 */ 36305 /* CL74_UserB0 :: uFecdbg_edataL :: uFecdbg_edataL [15:00] */ 36306 #define CL74_USERB0_UFECDBG_EDATAL_UFECDBG_EDATAL_MASK 0xffff 36307 #define CL74_USERB0_UFECDBG_EDATAL_UFECDBG_EDATAL_ALIGN 0 36308 #define CL74_USERB0_UFECDBG_EDATAL_UFECDBG_EDATAL_BITS 16 36309 #define CL74_USERB0_UFECDBG_EDATAL_UFECDBG_EDATAL_SHIFT 0 36310 36311 36312 /**************************************************************************** 36313 * CL74_UserB0 :: uFecdbg_edataH 36314 */ 36315 /* CL74_UserB0 :: uFecdbg_edataH :: uFecdbg_edataH [15:00] */ 36316 #define CL74_USERB0_UFECDBG_EDATAH_UFECDBG_EDATAH_MASK 0xffff 36317 #define CL74_USERB0_UFECDBG_EDATAH_UFECDBG_EDATAH_ALIGN 0 36318 #define CL74_USERB0_UFECDBG_EDATAH_UFECDBG_EDATAH_BITS 16 36319 #define CL74_USERB0_UFECDBG_EDATAH_UFECDBG_EDATAH_SHIFT 0 36320 36321 36322 /**************************************************************************** 36323 * CL74_UserB0 :: uFecControl4 36324 */ 36325 /* CL74_UserB0 :: uFecControl4 :: reserved0 [15:01] */ 36326 #define CL74_USERB0_UFECCONTROL4_RESERVED0_MASK 0xfffe 36327 #define CL74_USERB0_UFECCONTROL4_RESERVED0_ALIGN 0 36328 #define CL74_USERB0_UFECCONTROL4_RESERVED0_BITS 15 36329 #define CL74_USERB0_UFECCONTROL4_RESERVED0_SHIFT 1 36330 36331 /* CL74_UserB0 :: uFecControl4 :: fec_burst_err_status_mode [00:00] */ 36332 #define CL74_USERB0_UFECCONTROL4_FEC_BURST_ERR_STATUS_MODE_MASK 0x0001 36333 #define CL74_USERB0_UFECCONTROL4_FEC_BURST_ERR_STATUS_MODE_ALIGN 0 36334 #define CL74_USERB0_UFECCONTROL4_FEC_BURST_ERR_STATUS_MODE_BITS 1 36335 #define CL74_USERB0_UFECCONTROL4_FEC_BURST_ERR_STATUS_MODE_SHIFT 0 36336 36337 36338 /**************************************************************************** 36339 * CL74_UserB0 :: uFec_burst_err_statusL 36340 */ 36341 /* CL74_UserB0 :: uFec_burst_err_statusL :: fec_burst_err_status_lsw [15:00] */ 36342 #define CL74_USERB0_UFEC_BURST_ERR_STATUSL_FEC_BURST_ERR_STATUS_LSW_MASK 0xffff 36343 #define CL74_USERB0_UFEC_BURST_ERR_STATUSL_FEC_BURST_ERR_STATUS_LSW_ALIGN 0 36344 #define CL74_USERB0_UFEC_BURST_ERR_STATUSL_FEC_BURST_ERR_STATUS_LSW_BITS 16 36345 #define CL74_USERB0_UFEC_BURST_ERR_STATUSL_FEC_BURST_ERR_STATUS_LSW_SHIFT 0 36346 36347 36348 /**************************************************************************** 36349 * CL74_UserB0 :: uFec_burst_err_statusH 36350 */ 36351 /* CL74_UserB0 :: uFec_burst_err_statusH :: fec_burst_err_status_msw [15:00] */ 36352 #define CL74_USERB0_UFEC_BURST_ERR_STATUSH_FEC_BURST_ERR_STATUS_MSW_MASK 0xffff 36353 #define CL74_USERB0_UFEC_BURST_ERR_STATUSH_FEC_BURST_ERR_STATUS_MSW_ALIGN 0 36354 #define CL74_USERB0_UFEC_BURST_ERR_STATUSH_FEC_BURST_ERR_STATUS_MSW_BITS 16 36355 #define CL74_USERB0_UFEC_BURST_ERR_STATUSH_FEC_BURST_ERR_STATUS_MSW_SHIFT 0 36356 36357 36358 /**************************************************************************** 36359 * Warpcore_USER_EEE_UserB0 36360 */ 36361 /**************************************************************************** 36362 * EEE_UserB0 :: eee_combo_control0 36363 */ 36364 /* EEE_UserB0 :: eee_combo_control0 :: R2_eee_en [15:15] */ 36365 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_EEE_EN_MASK 0x8000 36366 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_EEE_EN_ALIGN 0 36367 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_EEE_EN_BITS 1 36368 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_EEE_EN_SHIFT 15 36369 36370 /* EEE_UserB0 :: eee_combo_control0 :: R2_LPI_en_rx [14:14] */ 36371 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_RX_MASK 0x4000 36372 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_RX_ALIGN 0 36373 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_RX_BITS 1 36374 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_RX_SHIFT 14 36375 36376 /* EEE_UserB0 :: eee_combo_control0 :: R2_LPI_en_tx [13:13] */ 36377 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_TX_MASK 0x2000 36378 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_TX_ALIGN 0 36379 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_TX_BITS 1 36380 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_TX_SHIFT 13 36381 36382 /* EEE_UserB0 :: eee_combo_control0 :: reserved_for_eco0 [12:08] */ 36383 #define EEE_USERB0_EEE_COMBO_CONTROL0_RESERVED_FOR_ECO0_MASK 0x1f00 36384 #define EEE_USERB0_EEE_COMBO_CONTROL0_RESERVED_FOR_ECO0_ALIGN 0 36385 #define EEE_USERB0_EEE_COMBO_CONTROL0_RESERVED_FOR_ECO0_BITS 5 36386 #define EEE_USERB0_EEE_COMBO_CONTROL0_RESERVED_FOR_ECO0_SHIFT 8 36387 36388 /* EEE_UserB0 :: eee_combo_control0 :: afe_rx_quiet_en [07:07] */ 36389 #define EEE_USERB0_EEE_COMBO_CONTROL0_AFE_RX_QUIET_EN_MASK 0x0080 36390 #define EEE_USERB0_EEE_COMBO_CONTROL0_AFE_RX_QUIET_EN_ALIGN 0 36391 #define EEE_USERB0_EEE_COMBO_CONTROL0_AFE_RX_QUIET_EN_BITS 1 36392 #define EEE_USERB0_EEE_COMBO_CONTROL0_AFE_RX_QUIET_EN_SHIFT 7 36393 36394 /* EEE_UserB0 :: eee_combo_control0 :: eee_bypass_sigdet_filt [06:06] */ 36395 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_BYPASS_SIGDET_FILT_MASK 0x0040 36396 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_BYPASS_SIGDET_FILT_ALIGN 0 36397 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_BYPASS_SIGDET_FILT_BITS 1 36398 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_BYPASS_SIGDET_FILT_SHIFT 6 36399 36400 /* EEE_UserB0 :: eee_combo_control0 :: cl36_eee_rx_os8_afrst_en [05:05] */ 36401 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_RX_OS8_AFRST_EN_MASK 0x0020 36402 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_RX_OS8_AFRST_EN_ALIGN 0 36403 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_RX_OS8_AFRST_EN_BITS 1 36404 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_RX_OS8_AFRST_EN_SHIFT 5 36405 36406 /* EEE_UserB0 :: eee_combo_control0 :: cl36_eee_tx_os8_afrst_en [04:04] */ 36407 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_TX_OS8_AFRST_EN_MASK 0x0010 36408 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_TX_OS8_AFRST_EN_ALIGN 0 36409 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_TX_OS8_AFRST_EN_BITS 1 36410 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_TX_OS8_AFRST_EN_SHIFT 4 36411 36412 /* EEE_UserB0 :: eee_combo_control0 :: cl49_eee_txfifo_ckgate_en [03:03] */ 36413 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL49_EEE_TXFIFO_CKGATE_EN_MASK 0x0008 36414 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL49_EEE_TXFIFO_CKGATE_EN_ALIGN 0 36415 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL49_EEE_TXFIFO_CKGATE_EN_BITS 1 36416 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL49_EEE_TXFIFO_CKGATE_EN_SHIFT 3 36417 36418 /* EEE_UserB0 :: eee_combo_control0 :: lpi_en_force [02:02] */ 36419 #define EEE_USERB0_EEE_COMBO_CONTROL0_LPI_EN_FORCE_MASK 0x0004 36420 #define EEE_USERB0_EEE_COMBO_CONTROL0_LPI_EN_FORCE_ALIGN 0 36421 #define EEE_USERB0_EEE_COMBO_CONTROL0_LPI_EN_FORCE_BITS 1 36422 #define EEE_USERB0_EEE_COMBO_CONTROL0_LPI_EN_FORCE_SHIFT 2 36423 36424 /* EEE_UserB0 :: eee_combo_control0 :: eee_en_force_val [01:01] */ 36425 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_VAL_MASK 0x0002 36426 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_VAL_ALIGN 0 36427 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_VAL_BITS 1 36428 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_VAL_SHIFT 1 36429 36430 /* EEE_UserB0 :: eee_combo_control0 :: eee_en_force [00:00] */ 36431 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_MASK 0x0001 36432 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_ALIGN 0 36433 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_BITS 1 36434 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_SHIFT 0 36435 36436 36437 /**************************************************************************** 36438 * EEE_UserB0 :: cl36_tx_lpi_sm 36439 */ 36440 /* EEE_UserB0 :: cl36_tx_lpi_sm :: tx1g_LPI_rcvd [15:15] */ 36441 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_RCVD_MASK 0x8000 36442 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_RCVD_ALIGN 0 36443 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_RCVD_BITS 1 36444 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_RCVD_SHIFT 15 36445 36446 /* EEE_UserB0 :: cl36_tx_lpi_sm :: tx1g_LPI_detect [14:14] */ 36447 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_DETECT_MASK 0x4000 36448 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_DETECT_ALIGN 0 36449 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_DETECT_BITS 1 36450 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_DETECT_SHIFT 14 36451 36452 /* EEE_UserB0 :: cl36_tx_lpi_sm :: reserved_for_eco0 [13:07] */ 36453 #define EEE_USERB0_CL36_TX_LPI_SM_RESERVED_FOR_ECO0_MASK 0x3f80 36454 #define EEE_USERB0_CL36_TX_LPI_SM_RESERVED_FOR_ECO0_ALIGN 0 36455 #define EEE_USERB0_CL36_TX_LPI_SM_RESERVED_FOR_ECO0_BITS 7 36456 #define EEE_USERB0_CL36_TX_LPI_SM_RESERVED_FOR_ECO0_SHIFT 7 36457 36458 /* EEE_UserB0 :: cl36_tx_lpi_sm :: cl36_tx_lpi_state_l [06:03] */ 36459 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_MASK 0x0078 36460 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_ALIGN 0 36461 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_BITS 4 36462 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_SHIFT 3 36463 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_TX_REFRESH 8 36464 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_TX_QUIET 4 36465 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_TX_SLEEP 2 36466 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_TX_ACTIVE 1 36467 36468 /* EEE_UserB0 :: cl36_tx_lpi_sm :: cl36_tx_lpi_state_c [02:00] */ 36469 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_MASK 0x0007 36470 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_ALIGN 0 36471 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_BITS 3 36472 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_SHIFT 0 36473 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_TX_REFRESH 3 36474 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_TX_QUIET 2 36475 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_TX_SLEEP 1 36476 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_TX_ACTIVE 0 36477 36478 36479 /**************************************************************************** 36480 * EEE_UserB0 :: cl36_rx_lpi_sm 36481 */ 36482 /* EEE_UserB0 :: cl36_rx_lpi_sm :: rx1g_LPI_rcvd [15:15] */ 36483 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_RCVD_MASK 0x8000 36484 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_RCVD_ALIGN 0 36485 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_RCVD_BITS 1 36486 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_RCVD_SHIFT 15 36487 36488 /* EEE_UserB0 :: cl36_rx_lpi_sm :: rx1g_LPI_detect [14:14] */ 36489 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_DETECT_MASK 0x4000 36490 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_DETECT_ALIGN 0 36491 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_DETECT_BITS 1 36492 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_DETECT_SHIFT 14 36493 36494 /* EEE_UserB0 :: cl36_rx_lpi_sm :: reserved_for_eco0 [13:09] */ 36495 #define EEE_USERB0_CL36_RX_LPI_SM_RESERVED_FOR_ECO0_MASK 0x3e00 36496 #define EEE_USERB0_CL36_RX_LPI_SM_RESERVED_FOR_ECO0_ALIGN 0 36497 #define EEE_USERB0_CL36_RX_LPI_SM_RESERVED_FOR_ECO0_BITS 5 36498 #define EEE_USERB0_CL36_RX_LPI_SM_RESERVED_FOR_ECO0_SHIFT 9 36499 36500 /* EEE_UserB0 :: cl36_rx_lpi_sm :: cl36_rx_lpi_state_l [08:03] */ 36501 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_MASK 0x01f8 36502 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_ALIGN 0 36503 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_BITS 6 36504 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_SHIFT 3 36505 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_LINK_FAIL 32 36506 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_WTF 16 36507 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_WAKE 8 36508 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_QUIET 4 36509 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_SLEEP 2 36510 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_ACTIVE 1 36511 36512 /* EEE_UserB0 :: cl36_rx_lpi_sm :: cl36_rx_lpi_state_c [02:00] */ 36513 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_MASK 0x0007 36514 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_ALIGN 0 36515 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_BITS 3 36516 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_SHIFT 0 36517 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_LINK_FAIL 5 36518 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_WTF 4 36519 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_WAKE 3 36520 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_QUIET 2 36521 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_SLEEP 1 36522 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_ACTIVE 0 36523 36524 36525 /**************************************************************************** 36526 * EEE_UserB0 :: cl49_tx_lpi_sm 36527 */ 36528 /* EEE_UserB0 :: cl49_tx_lpi_sm :: cl49_tx_LPI_rcvd [15:15] */ 36529 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_RCVD_MASK 0x8000 36530 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_RCVD_ALIGN 0 36531 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_RCVD_BITS 1 36532 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_RCVD_SHIFT 15 36533 36534 /* EEE_UserB0 :: cl49_tx_lpi_sm :: cl49_tx_LPI_detect [14:14] */ 36535 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_DETECT_MASK 0x4000 36536 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_DETECT_ALIGN 0 36537 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_DETECT_BITS 1 36538 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_DETECT_SHIFT 14 36539 36540 /* EEE_UserB0 :: cl49_tx_lpi_sm :: reserved_for_eco0 [13:10] */ 36541 #define EEE_USERB0_CL49_TX_LPI_SM_RESERVED_FOR_ECO0_MASK 0x3c00 36542 #define EEE_USERB0_CL49_TX_LPI_SM_RESERVED_FOR_ECO0_ALIGN 0 36543 #define EEE_USERB0_CL49_TX_LPI_SM_RESERVED_FOR_ECO0_BITS 4 36544 #define EEE_USERB0_CL49_TX_LPI_SM_RESERVED_FOR_ECO0_SHIFT 10 36545 36546 /* EEE_UserB0 :: cl49_tx_lpi_sm :: cl49_tx_lpi_state_l [09:03] */ 36547 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_MASK 0x03f8 36548 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_ALIGN 0 36549 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_BITS 7 36550 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_SHIFT 3 36551 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_SCR_RESET_2 64 36552 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_SCR_RESET_1 32 36553 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_TX_WAKE 16 36554 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_TX_REFRESH 8 36555 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_TX_QUIET 4 36556 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_TX_SLEEP 2 36557 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_TX_ACTIVE 1 36558 36559 /* EEE_UserB0 :: cl49_tx_lpi_sm :: cl49_tx_lpi_state_c [02:00] */ 36560 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_MASK 0x0007 36561 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_ALIGN 0 36562 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_BITS 3 36563 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_SHIFT 0 36564 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_SCR_RESET_2 6 36565 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_SCR_RESET_1 5 36566 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_TX_WAKE 4 36567 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_TX_REFRESH 3 36568 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_TX_QUIET 2 36569 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_TX_SLEEP 1 36570 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_TX_ACTIVE 0 36571 36572 36573 /**************************************************************************** 36574 * EEE_UserB0 :: cl49_rx_lpi_sm 36575 */ 36576 /* EEE_UserB0 :: cl49_rx_lpi_sm :: cl49_rx_LPI_rcvd [15:15] */ 36577 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_RCVD_MASK 0x8000 36578 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_RCVD_ALIGN 0 36579 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_RCVD_BITS 1 36580 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_RCVD_SHIFT 15 36581 36582 /* EEE_UserB0 :: cl49_rx_lpi_sm :: cl49_rx_LPI_detect [14:14] */ 36583 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_DETECT_MASK 0x4000 36584 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_DETECT_ALIGN 0 36585 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_DETECT_BITS 1 36586 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_DETECT_SHIFT 14 36587 36588 /* EEE_UserB0 :: cl49_rx_lpi_sm :: reserved_for_eco0 [13:09] */ 36589 #define EEE_USERB0_CL49_RX_LPI_SM_RESERVED_FOR_ECO0_MASK 0x3e00 36590 #define EEE_USERB0_CL49_RX_LPI_SM_RESERVED_FOR_ECO0_ALIGN 0 36591 #define EEE_USERB0_CL49_RX_LPI_SM_RESERVED_FOR_ECO0_BITS 5 36592 #define EEE_USERB0_CL49_RX_LPI_SM_RESERVED_FOR_ECO0_SHIFT 9 36593 36594 /* EEE_UserB0 :: cl49_rx_lpi_sm :: cl49_rx_lpi_state_l [08:03] */ 36595 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_MASK 0x01f8 36596 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_ALIGN 0 36597 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_BITS 6 36598 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_SHIFT 3 36599 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_LINK_FAIL 32 36600 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_WTF 16 36601 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_WAKE 8 36602 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_QUIET 4 36603 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_SLEEP 2 36604 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_ACTIVE 1 36605 36606 /* EEE_UserB0 :: cl49_rx_lpi_sm :: cl49_rx_lpi_state_c [02:00] */ 36607 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_MASK 0x0007 36608 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_ALIGN 0 36609 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_BITS 3 36610 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_SHIFT 0 36611 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_LINK_FAIL 5 36612 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_WTF 4 36613 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_WAKE 3 36614 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_QUIET 2 36615 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_SLEEP 1 36616 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_ACTIVE 0 36617 36618 36619 /**************************************************************************** 36620 * EEE_UserB0 :: tx_sleep_timer 36621 */ 36622 /* EEE_UserB0 :: tx_sleep_timer :: tx_ts_cnt_mdio [15:00] */ 36623 #define EEE_USERB0_TX_SLEEP_TIMER_TX_TS_CNT_MDIO_MASK 0xffff 36624 #define EEE_USERB0_TX_SLEEP_TIMER_TX_TS_CNT_MDIO_ALIGN 0 36625 #define EEE_USERB0_TX_SLEEP_TIMER_TX_TS_CNT_MDIO_BITS 16 36626 #define EEE_USERB0_TX_SLEEP_TIMER_TX_TS_CNT_MDIO_SHIFT 0 36627 36628 36629 /**************************************************************************** 36630 * EEE_UserB0 :: cl49_tx_sleep_timer 36631 */ 36632 /* EEE_UserB0 :: cl49_tx_sleep_timer :: cl49_tx_ts_cnt_mdio [15:00] */ 36633 #define EEE_USERB0_CL49_TX_SLEEP_TIMER_CL49_TX_TS_CNT_MDIO_MASK 0xffff 36634 #define EEE_USERB0_CL49_TX_SLEEP_TIMER_CL49_TX_TS_CNT_MDIO_ALIGN 0 36635 #define EEE_USERB0_CL49_TX_SLEEP_TIMER_CL49_TX_TS_CNT_MDIO_BITS 16 36636 #define EEE_USERB0_CL49_TX_SLEEP_TIMER_CL49_TX_TS_CNT_MDIO_SHIFT 0 36637 36638 36639 /**************************************************************************** 36640 * EEE_UserB0 :: tx_wake_timer 36641 */ 36642 /* EEE_UserB0 :: tx_wake_timer :: tx_tw_cnt_mdio [15:00] */ 36643 #define EEE_USERB0_TX_WAKE_TIMER_TX_TW_CNT_MDIO_MASK 0xffff 36644 #define EEE_USERB0_TX_WAKE_TIMER_TX_TW_CNT_MDIO_ALIGN 0 36645 #define EEE_USERB0_TX_WAKE_TIMER_TX_TW_CNT_MDIO_BITS 16 36646 #define EEE_USERB0_TX_WAKE_TIMER_TX_TW_CNT_MDIO_SHIFT 0 36647 36648 36649 /**************************************************************************** 36650 * EEE_UserB0 :: rx_offset_timer 36651 */ 36652 /* EEE_UserB0 :: rx_offset_timer :: rx_tq_offset_mdio [15:00] */ 36653 #define EEE_USERB0_RX_OFFSET_TIMER_RX_TQ_OFFSET_MDIO_MASK 0xffff 36654 #define EEE_USERB0_RX_OFFSET_TIMER_RX_TQ_OFFSET_MDIO_ALIGN 0 36655 #define EEE_USERB0_RX_OFFSET_TIMER_RX_TQ_OFFSET_MDIO_BITS 16 36656 #define EEE_USERB0_RX_OFFSET_TIMER_RX_TQ_OFFSET_MDIO_SHIFT 0 36657 36658 36659 /**************************************************************************** 36660 * EEE_UserB0 :: rx_wake_time_fault_timer 36661 */ 36662 /* EEE_UserB0 :: rx_wake_time_fault_timer :: rx_wtf_cnt_mdio [15:00] */ 36663 #define EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER_RX_WTF_CNT_MDIO_MASK 0xffff 36664 #define EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER_RX_WTF_CNT_MDIO_ALIGN 0 36665 #define EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER_RX_WTF_CNT_MDIO_BITS 16 36666 #define EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER_RX_WTF_CNT_MDIO_SHIFT 0 36667 36668 36669 /**************************************************************************** 36670 * EEE_UserB0 :: misc_timer 36671 */ 36672 /* EEE_UserB0 :: misc_timer :: reserved_for_eco0 [15:10] */ 36673 #define EEE_USERB0_MISC_TIMER_RESERVED_FOR_ECO0_MASK 0xfc00 36674 #define EEE_USERB0_MISC_TIMER_RESERVED_FOR_ECO0_ALIGN 0 36675 #define EEE_USERB0_MISC_TIMER_RESERVED_FOR_ECO0_BITS 6 36676 #define EEE_USERB0_MISC_TIMER_RESERVED_FOR_ECO0_SHIFT 10 36677 36678 /* EEE_UserB0 :: misc_timer :: grp5_tx_tq_cnt_msb_mdio [09:08] */ 36679 #define EEE_USERB0_MISC_TIMER_GRP5_TX_TQ_CNT_MSB_MDIO_MASK 0x0300 36680 #define EEE_USERB0_MISC_TIMER_GRP5_TX_TQ_CNT_MSB_MDIO_ALIGN 0 36681 #define EEE_USERB0_MISC_TIMER_GRP5_TX_TQ_CNT_MSB_MDIO_BITS 2 36682 #define EEE_USERB0_MISC_TIMER_GRP5_TX_TQ_CNT_MSB_MDIO_SHIFT 8 36683 36684 /* EEE_UserB0 :: misc_timer :: grp4_tx_tq_cnt_msb_mdio [07:06] */ 36685 #define EEE_USERB0_MISC_TIMER_GRP4_TX_TQ_CNT_MSB_MDIO_MASK 0x00c0 36686 #define EEE_USERB0_MISC_TIMER_GRP4_TX_TQ_CNT_MSB_MDIO_ALIGN 0 36687 #define EEE_USERB0_MISC_TIMER_GRP4_TX_TQ_CNT_MSB_MDIO_BITS 2 36688 #define EEE_USERB0_MISC_TIMER_GRP4_TX_TQ_CNT_MSB_MDIO_SHIFT 6 36689 36690 /* EEE_UserB0 :: misc_timer :: grp3_tx_tq_cnt_msb_mdio [05:04] */ 36691 #define EEE_USERB0_MISC_TIMER_GRP3_TX_TQ_CNT_MSB_MDIO_MASK 0x0030 36692 #define EEE_USERB0_MISC_TIMER_GRP3_TX_TQ_CNT_MSB_MDIO_ALIGN 0 36693 #define EEE_USERB0_MISC_TIMER_GRP3_TX_TQ_CNT_MSB_MDIO_BITS 2 36694 #define EEE_USERB0_MISC_TIMER_GRP3_TX_TQ_CNT_MSB_MDIO_SHIFT 4 36695 36696 /* EEE_UserB0 :: misc_timer :: grp2_tx_tq_cnt_msb_mdio [03:02] */ 36697 #define EEE_USERB0_MISC_TIMER_GRP2_TX_TQ_CNT_MSB_MDIO_MASK 0x000c 36698 #define EEE_USERB0_MISC_TIMER_GRP2_TX_TQ_CNT_MSB_MDIO_ALIGN 0 36699 #define EEE_USERB0_MISC_TIMER_GRP2_TX_TQ_CNT_MSB_MDIO_BITS 2 36700 #define EEE_USERB0_MISC_TIMER_GRP2_TX_TQ_CNT_MSB_MDIO_SHIFT 2 36701 36702 /* EEE_UserB0 :: misc_timer :: grp1_tx_tq_cnt_msb_mdio [01:00] */ 36703 #define EEE_USERB0_MISC_TIMER_GRP1_TX_TQ_CNT_MSB_MDIO_MASK 0x0003 36704 #define EEE_USERB0_MISC_TIMER_GRP1_TX_TQ_CNT_MSB_MDIO_ALIGN 0 36705 #define EEE_USERB0_MISC_TIMER_GRP1_TX_TQ_CNT_MSB_MDIO_BITS 2 36706 #define EEE_USERB0_MISC_TIMER_GRP1_TX_TQ_CNT_MSB_MDIO_SHIFT 0 36707 36708 36709 /**************************************************************************** 36710 * EEE_UserB0 :: eee_hyst_timer 36711 */ 36712 /* EEE_UserB0 :: eee_hyst_timer :: cl49_tx_us_cnt [15:09] */ 36713 #define EEE_USERB0_EEE_HYST_TIMER_CL49_TX_US_CNT_MASK 0xfe00 36714 #define EEE_USERB0_EEE_HYST_TIMER_CL49_TX_US_CNT_ALIGN 0 36715 #define EEE_USERB0_EEE_HYST_TIMER_CL49_TX_US_CNT_BITS 7 36716 #define EEE_USERB0_EEE_HYST_TIMER_CL49_TX_US_CNT_SHIFT 9 36717 36718 /* EEE_UserB0 :: eee_hyst_timer :: LPI_hyst_cnt [08:06] */ 36719 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_CNT_MASK 0x01c0 36720 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_CNT_ALIGN 0 36721 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_CNT_BITS 3 36722 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_CNT_SHIFT 6 36723 36724 /* EEE_UserB0 :: eee_hyst_timer :: LPI_hyst_en [05:05] */ 36725 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_EN_MASK 0x0020 36726 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_EN_ALIGN 0 36727 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_EN_BITS 1 36728 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_EN_SHIFT 5 36729 36730 /* EEE_UserB0 :: eee_hyst_timer :: eee_sigdet_cnt [04:00] */ 36731 #define EEE_USERB0_EEE_HYST_TIMER_EEE_SIGDET_CNT_MASK 0x001f 36732 #define EEE_USERB0_EEE_HYST_TIMER_EEE_SIGDET_CNT_ALIGN 0 36733 #define EEE_USERB0_EEE_HYST_TIMER_EEE_SIGDET_CNT_BITS 5 36734 #define EEE_USERB0_EEE_HYST_TIMER_EEE_SIGDET_CNT_SHIFT 0 36735 36736 36737 /**************************************************************************** 36738 * EEE_UserB0 :: eee_override_ctrl 36739 */ 36740 /* EEE_UserB0 :: eee_override_ctrl :: reserved_for_eco0 [15:10] */ 36741 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RESERVED_FOR_ECO0_MASK 0xfc00 36742 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RESERVED_FOR_ECO0_ALIGN 0 36743 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RESERVED_FOR_ECO0_BITS 6 36744 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RESERVED_FOR_ECO0_SHIFT 10 36745 36746 /* EEE_UserB0 :: eee_override_ctrl :: rx_wake_dis [09:09] */ 36747 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_WAKE_DIS_MASK 0x0200 36748 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_WAKE_DIS_ALIGN 0 36749 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_WAKE_DIS_BITS 1 36750 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_WAKE_DIS_SHIFT 9 36751 36752 /* EEE_UserB0 :: eee_override_ctrl :: tx_refresh_dis [08:08] */ 36753 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_REFRESH_DIS_MASK 0x0100 36754 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_REFRESH_DIS_ALIGN 0 36755 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_REFRESH_DIS_BITS 1 36756 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_REFRESH_DIS_SHIFT 8 36757 36758 /* EEE_UserB0 :: eee_override_ctrl :: TxElectIdle_force_val [07:07] */ 36759 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_VAL_MASK 0x0080 36760 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_VAL_ALIGN 0 36761 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_VAL_BITS 1 36762 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_VAL_SHIFT 7 36763 36764 /* EEE_UserB0 :: eee_override_ctrl :: TxElectIdle_force [06:06] */ 36765 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_MASK 0x0040 36766 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_ALIGN 0 36767 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_BITS 1 36768 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_SHIFT 6 36769 36770 /* EEE_UserB0 :: eee_override_ctrl :: rx_lpi_active_force_val [05:05] */ 36771 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_VAL_MASK 0x0020 36772 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_VAL_ALIGN 0 36773 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_VAL_BITS 1 36774 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_VAL_SHIFT 5 36775 36776 /* EEE_UserB0 :: eee_override_ctrl :: rx_lpi_active_force [04:04] */ 36777 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_MASK 0x0010 36778 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_ALIGN 0 36779 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_BITS 1 36780 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_SHIFT 4 36781 36782 /* EEE_UserB0 :: eee_override_ctrl :: rx_quiet_force_val [03:03] */ 36783 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_VAL_MASK 0x0008 36784 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_VAL_ALIGN 0 36785 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_VAL_BITS 1 36786 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_VAL_SHIFT 3 36787 36788 /* EEE_UserB0 :: eee_override_ctrl :: rx_quiet_force [02:02] */ 36789 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_MASK 0x0004 36790 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_ALIGN 0 36791 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_BITS 1 36792 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_SHIFT 2 36793 36794 /* EEE_UserB0 :: eee_override_ctrl :: tx_quiet_force_val [01:01] */ 36795 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_VAL_MASK 0x0002 36796 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_VAL_ALIGN 0 36797 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_VAL_BITS 1 36798 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_VAL_SHIFT 1 36799 36800 /* EEE_UserB0 :: eee_override_ctrl :: tx_quiet_force [00:00] */ 36801 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_MASK 0x0001 36802 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_ALIGN 0 36803 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_BITS 1 36804 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_SHIFT 0 36805 36806 36807 /**************************************************************************** 36808 * EEE_UserB0 :: eee_combo_control1 36809 */ 36810 /* EEE_UserB0 :: eee_combo_control1 :: reserved_for_eco0 [15:07] */ 36811 #define EEE_USERB0_EEE_COMBO_CONTROL1_RESERVED_FOR_ECO0_MASK 0xff80 36812 #define EEE_USERB0_EEE_COMBO_CONTROL1_RESERVED_FOR_ECO0_ALIGN 0 36813 #define EEE_USERB0_EEE_COMBO_CONTROL1_RESERVED_FOR_ECO0_BITS 9 36814 #define EEE_USERB0_EEE_COMBO_CONTROL1_RESERVED_FOR_ECO0_SHIFT 7 36815 36816 /* EEE_UserB0 :: eee_combo_control1 :: eee_sigdet_cnt_msb [06:05] */ 36817 #define EEE_USERB0_EEE_COMBO_CONTROL1_EEE_SIGDET_CNT_MSB_MASK 0x0060 36818 #define EEE_USERB0_EEE_COMBO_CONTROL1_EEE_SIGDET_CNT_MSB_ALIGN 0 36819 #define EEE_USERB0_EEE_COMBO_CONTROL1_EEE_SIGDET_CNT_MSB_BITS 2 36820 #define EEE_USERB0_EEE_COMBO_CONTROL1_EEE_SIGDET_CNT_MSB_SHIFT 5 36821 36822 /* EEE_UserB0 :: eee_combo_control1 :: tx_elec_idle_dly_cnt [04:00] */ 36823 #define EEE_USERB0_EEE_COMBO_CONTROL1_TX_ELEC_IDLE_DLY_CNT_MASK 0x001f 36824 #define EEE_USERB0_EEE_COMBO_CONTROL1_TX_ELEC_IDLE_DLY_CNT_ALIGN 0 36825 #define EEE_USERB0_EEE_COMBO_CONTROL1_TX_ELEC_IDLE_DLY_CNT_BITS 5 36826 #define EEE_USERB0_EEE_COMBO_CONTROL1_TX_ELEC_IDLE_DLY_CNT_SHIFT 0 36827 36828 36829 /**************************************************************************** 36830 * EEE_UserB0 :: cl49_eee_char 36831 */ 36832 /* EEE_UserB0 :: cl49_eee_char :: reserved_for_eco0 [15:15] */ 36833 #define EEE_USERB0_CL49_EEE_CHAR_RESERVED_FOR_ECO0_MASK 0x8000 36834 #define EEE_USERB0_CL49_EEE_CHAR_RESERVED_FOR_ECO0_ALIGN 0 36835 #define EEE_USERB0_CL49_EEE_CHAR_RESERVED_FOR_ECO0_BITS 1 36836 #define EEE_USERB0_CL49_EEE_CHAR_RESERVED_FOR_ECO0_SHIFT 15 36837 36838 /* EEE_UserB0 :: cl49_eee_char :: cl49_lpi [14:08] */ 36839 #define EEE_USERB0_CL49_EEE_CHAR_CL49_LPI_MASK 0x7f00 36840 #define EEE_USERB0_CL49_EEE_CHAR_CL49_LPI_ALIGN 0 36841 #define EEE_USERB0_CL49_EEE_CHAR_CL49_LPI_BITS 7 36842 #define EEE_USERB0_CL49_EEE_CHAR_CL49_LPI_SHIFT 8 36843 36844 /* EEE_UserB0 :: cl49_eee_char :: xgmii_lpi [07:00] */ 36845 #define EEE_USERB0_CL49_EEE_CHAR_XGMII_LPI_MASK 0x00ff 36846 #define EEE_USERB0_CL49_EEE_CHAR_XGMII_LPI_ALIGN 0 36847 #define EEE_USERB0_CL49_EEE_CHAR_XGMII_LPI_BITS 8 36848 #define EEE_USERB0_CL49_EEE_CHAR_XGMII_LPI_SHIFT 0 36849 36850 36851 /**************************************************************************** 36852 * Warpcore_USER_EEE_UserB1 36853 */ 36854 /**************************************************************************** 36855 * EEE_UserB1 :: EEE_AN_Ctrl 36856 */ 36857 /* EEE_UserB1 :: EEE_AN_Ctrl :: EEE_res_status_CL_sel [15:14] */ 36858 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_CL_SEL_MASK 0xc000 36859 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_CL_SEL_ALIGN 0 36860 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_CL_SEL_BITS 2 36861 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_CL_SEL_SHIFT 14 36862 36863 /* EEE_UserB1 :: EEE_AN_Ctrl :: EEE_res_status_Timer_sel [13:12] */ 36864 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_TIMER_SEL_MASK 0x3000 36865 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_TIMER_SEL_ALIGN 0 36866 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_TIMER_SEL_BITS 2 36867 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_TIMER_SEL_SHIFT 12 36868 36869 /* EEE_UserB1 :: EEE_AN_Ctrl :: reserved0 [11:11] */ 36870 #define EEE_USERB1_EEE_AN_CTRL_RESERVED0_MASK 0x0800 36871 #define EEE_USERB1_EEE_AN_CTRL_RESERVED0_ALIGN 0 36872 #define EEE_USERB1_EEE_AN_CTRL_RESERVED0_BITS 1 36873 #define EEE_USERB1_EEE_AN_CTRL_RESERVED0_SHIFT 11 36874 36875 /* EEE_UserB1 :: EEE_AN_Ctrl :: EEE_page_number [10:00] */ 36876 #define EEE_USERB1_EEE_AN_CTRL_EEE_PAGE_NUMBER_MASK 0x07ff 36877 #define EEE_USERB1_EEE_AN_CTRL_EEE_PAGE_NUMBER_ALIGN 0 36878 #define EEE_USERB1_EEE_AN_CTRL_EEE_PAGE_NUMBER_BITS 11 36879 #define EEE_USERB1_EEE_AN_CTRL_EEE_PAGE_NUMBER_SHIFT 0 36880 36881 36882 /**************************************************************************** 36883 * EEE_UserB1 :: EEE_UP1 36884 */ 36885 /* EEE_UserB1 :: EEE_UP1 :: reserved0 [15:11] */ 36886 #define EEE_USERB1_EEE_UP1_RESERVED0_MASK 0xf800 36887 #define EEE_USERB1_EEE_UP1_RESERVED0_ALIGN 0 36888 #define EEE_USERB1_EEE_UP1_RESERVED0_BITS 5 36889 #define EEE_USERB1_EEE_UP1_RESERVED0_SHIFT 11 36890 36891 /* EEE_UserB1 :: EEE_UP1 :: Group2_Level [10:07] */ 36892 #define EEE_USERB1_EEE_UP1_GROUP2_LEVEL_MASK 0x0780 36893 #define EEE_USERB1_EEE_UP1_GROUP2_LEVEL_ALIGN 0 36894 #define EEE_USERB1_EEE_UP1_GROUP2_LEVEL_BITS 4 36895 #define EEE_USERB1_EEE_UP1_GROUP2_LEVEL_SHIFT 7 36896 36897 /* EEE_UserB1 :: EEE_UP1 :: Group1_Level [06:03] */ 36898 #define EEE_USERB1_EEE_UP1_GROUP1_LEVEL_MASK 0x0078 36899 #define EEE_USERB1_EEE_UP1_GROUP1_LEVEL_ALIGN 0 36900 #define EEE_USERB1_EEE_UP1_GROUP1_LEVEL_BITS 4 36901 #define EEE_USERB1_EEE_UP1_GROUP1_LEVEL_SHIFT 3 36902 36903 /* EEE_UserB1 :: EEE_UP1 :: cl73_override [02:02] */ 36904 #define EEE_USERB1_EEE_UP1_CL73_OVERRIDE_MASK 0x0004 36905 #define EEE_USERB1_EEE_UP1_CL73_OVERRIDE_ALIGN 0 36906 #define EEE_USERB1_EEE_UP1_CL73_OVERRIDE_BITS 1 36907 #define EEE_USERB1_EEE_UP1_CL73_OVERRIDE_SHIFT 2 36908 36909 /* EEE_UserB1 :: EEE_UP1 :: Pwrdn [01:01] */ 36910 #define EEE_USERB1_EEE_UP1_PWRDN_MASK 0x0002 36911 #define EEE_USERB1_EEE_UP1_PWRDN_ALIGN 0 36912 #define EEE_USERB1_EEE_UP1_PWRDN_BITS 1 36913 #define EEE_USERB1_EEE_UP1_PWRDN_SHIFT 1 36914 36915 /* EEE_UserB1 :: EEE_UP1 :: EEE [00:00] */ 36916 #define EEE_USERB1_EEE_UP1_EEE_MASK 0x0001 36917 #define EEE_USERB1_EEE_UP1_EEE_ALIGN 0 36918 #define EEE_USERB1_EEE_UP1_EEE_BITS 1 36919 #define EEE_USERB1_EEE_UP1_EEE_SHIFT 0 36920 36921 36922 /**************************************************************************** 36923 * EEE_UserB1 :: EEE_UP2 36924 */ 36925 /* EEE_UserB1 :: EEE_UP2 :: reserved0 [15:08] */ 36926 #define EEE_USERB1_EEE_UP2_RESERVED0_MASK 0xff00 36927 #define EEE_USERB1_EEE_UP2_RESERVED0_ALIGN 0 36928 #define EEE_USERB1_EEE_UP2_RESERVED0_BITS 8 36929 #define EEE_USERB1_EEE_UP2_RESERVED0_SHIFT 8 36930 36931 /* EEE_UserB1 :: EEE_UP2 :: Group4_Level [07:04] */ 36932 #define EEE_USERB1_EEE_UP2_GROUP4_LEVEL_MASK 0x00f0 36933 #define EEE_USERB1_EEE_UP2_GROUP4_LEVEL_ALIGN 0 36934 #define EEE_USERB1_EEE_UP2_GROUP4_LEVEL_BITS 4 36935 #define EEE_USERB1_EEE_UP2_GROUP4_LEVEL_SHIFT 4 36936 36937 /* EEE_UserB1 :: EEE_UP2 :: Group3_Level [03:00] */ 36938 #define EEE_USERB1_EEE_UP2_GROUP3_LEVEL_MASK 0x000f 36939 #define EEE_USERB1_EEE_UP2_GROUP3_LEVEL_ALIGN 0 36940 #define EEE_USERB1_EEE_UP2_GROUP3_LEVEL_BITS 4 36941 #define EEE_USERB1_EEE_UP2_GROUP3_LEVEL_SHIFT 0 36942 36943 36944 /**************************************************************************** 36945 * EEE_UserB1 :: EEE_UP3 36946 */ 36947 /* EEE_UserB1 :: EEE_UP3 :: reserved0 [15:04] */ 36948 #define EEE_USERB1_EEE_UP3_RESERVED0_MASK 0xfff0 36949 #define EEE_USERB1_EEE_UP3_RESERVED0_ALIGN 0 36950 #define EEE_USERB1_EEE_UP3_RESERVED0_BITS 12 36951 #define EEE_USERB1_EEE_UP3_RESERVED0_SHIFT 4 36952 36953 /* EEE_UserB1 :: EEE_UP3 :: Group5_Level [03:00] */ 36954 #define EEE_USERB1_EEE_UP3_GROUP5_LEVEL_MASK 0x000f 36955 #define EEE_USERB1_EEE_UP3_GROUP5_LEVEL_ALIGN 0 36956 #define EEE_USERB1_EEE_UP3_GROUP5_LEVEL_BITS 4 36957 #define EEE_USERB1_EEE_UP3_GROUP5_LEVEL_SHIFT 0 36958 36959 36960 /**************************************************************************** 36961 * EEE_UserB1 :: LP_EEE_UP1 36962 */ 36963 /* EEE_UserB1 :: LP_EEE_UP1 :: reserved0 [15:11] */ 36964 #define EEE_USERB1_LP_EEE_UP1_RESERVED0_MASK 0xf800 36965 #define EEE_USERB1_LP_EEE_UP1_RESERVED0_ALIGN 0 36966 #define EEE_USERB1_LP_EEE_UP1_RESERVED0_BITS 5 36967 #define EEE_USERB1_LP_EEE_UP1_RESERVED0_SHIFT 11 36968 36969 /* EEE_UserB1 :: LP_EEE_UP1 :: LP_Group2_Level [10:07] */ 36970 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP2_LEVEL_MASK 0x0780 36971 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP2_LEVEL_ALIGN 0 36972 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP2_LEVEL_BITS 4 36973 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP2_LEVEL_SHIFT 7 36974 36975 /* EEE_UserB1 :: LP_EEE_UP1 :: LP_Group1_Level [06:03] */ 36976 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP1_LEVEL_MASK 0x0078 36977 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP1_LEVEL_ALIGN 0 36978 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP1_LEVEL_BITS 4 36979 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP1_LEVEL_SHIFT 3 36980 36981 /* EEE_UserB1 :: LP_EEE_UP1 :: LP_cl73_override [02:02] */ 36982 #define EEE_USERB1_LP_EEE_UP1_LP_CL73_OVERRIDE_MASK 0x0004 36983 #define EEE_USERB1_LP_EEE_UP1_LP_CL73_OVERRIDE_ALIGN 0 36984 #define EEE_USERB1_LP_EEE_UP1_LP_CL73_OVERRIDE_BITS 1 36985 #define EEE_USERB1_LP_EEE_UP1_LP_CL73_OVERRIDE_SHIFT 2 36986 36987 /* EEE_UserB1 :: LP_EEE_UP1 :: LP_Pwrdn [01:01] */ 36988 #define EEE_USERB1_LP_EEE_UP1_LP_PWRDN_MASK 0x0002 36989 #define EEE_USERB1_LP_EEE_UP1_LP_PWRDN_ALIGN 0 36990 #define EEE_USERB1_LP_EEE_UP1_LP_PWRDN_BITS 1 36991 #define EEE_USERB1_LP_EEE_UP1_LP_PWRDN_SHIFT 1 36992 36993 /* EEE_UserB1 :: LP_EEE_UP1 :: LP_EEE [00:00] */ 36994 #define EEE_USERB1_LP_EEE_UP1_LP_EEE_MASK 0x0001 36995 #define EEE_USERB1_LP_EEE_UP1_LP_EEE_ALIGN 0 36996 #define EEE_USERB1_LP_EEE_UP1_LP_EEE_BITS 1 36997 #define EEE_USERB1_LP_EEE_UP1_LP_EEE_SHIFT 0 36998 36999 37000 /**************************************************************************** 37001 * EEE_UserB1 :: LP_EEE_UP2 37002 */ 37003 /* EEE_UserB1 :: LP_EEE_UP2 :: reserved0 [15:08] */ 37004 #define EEE_USERB1_LP_EEE_UP2_RESERVED0_MASK 0xff00 37005 #define EEE_USERB1_LP_EEE_UP2_RESERVED0_ALIGN 0 37006 #define EEE_USERB1_LP_EEE_UP2_RESERVED0_BITS 8 37007 #define EEE_USERB1_LP_EEE_UP2_RESERVED0_SHIFT 8 37008 37009 /* EEE_UserB1 :: LP_EEE_UP2 :: LP_Group4_Level [07:04] */ 37010 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP4_LEVEL_MASK 0x00f0 37011 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP4_LEVEL_ALIGN 0 37012 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP4_LEVEL_BITS 4 37013 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP4_LEVEL_SHIFT 4 37014 37015 /* EEE_UserB1 :: LP_EEE_UP2 :: LP_Group3_Level [03:00] */ 37016 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP3_LEVEL_MASK 0x000f 37017 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP3_LEVEL_ALIGN 0 37018 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP3_LEVEL_BITS 4 37019 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP3_LEVEL_SHIFT 0 37020 37021 37022 /**************************************************************************** 37023 * EEE_UserB1 :: LP_EEE_UP3 37024 */ 37025 /* EEE_UserB1 :: LP_EEE_UP3 :: reserved0 [15:04] */ 37026 #define EEE_USERB1_LP_EEE_UP3_RESERVED0_MASK 0xfff0 37027 #define EEE_USERB1_LP_EEE_UP3_RESERVED0_ALIGN 0 37028 #define EEE_USERB1_LP_EEE_UP3_RESERVED0_BITS 12 37029 #define EEE_USERB1_LP_EEE_UP3_RESERVED0_SHIFT 4 37030 37031 /* EEE_UserB1 :: LP_EEE_UP3 :: LP_Group5_Level [03:00] */ 37032 #define EEE_USERB1_LP_EEE_UP3_LP_GROUP5_LEVEL_MASK 0x000f 37033 #define EEE_USERB1_LP_EEE_UP3_LP_GROUP5_LEVEL_ALIGN 0 37034 #define EEE_USERB1_LP_EEE_UP3_LP_GROUP5_LEVEL_BITS 4 37035 #define EEE_USERB1_LP_EEE_UP3_LP_GROUP5_LEVEL_SHIFT 0 37036 37037 37038 /**************************************************************************** 37039 * EEE_UserB1 :: EEE_RES_STATUS 37040 */ 37041 /* EEE_UserB1 :: EEE_RES_STATUS :: EEE_RES_STATUS [15:00] */ 37042 #define EEE_USERB1_EEE_RES_STATUS_EEE_RES_STATUS_MASK 0xffff 37043 #define EEE_USERB1_EEE_RES_STATUS_EEE_RES_STATUS_ALIGN 0 37044 #define EEE_USERB1_EEE_RES_STATUS_EEE_RES_STATUS_BITS 16 37045 #define EEE_USERB1_EEE_RES_STATUS_EEE_RES_STATUS_SHIFT 0 37046 37047 37048 /**************************************************************************** 37049 * Warpcore_USER_tx66 37050 */ 37051 /**************************************************************************** 37052 * tx66 :: Control 37053 */ 37054 /* tx66 :: Control :: fifo_spc_cya [15:15] */ 37055 #define TX66_CONTROL_FIFO_SPC_CYA_MASK 0x8000 37056 #define TX66_CONTROL_FIFO_SPC_CYA_ALIGN 0 37057 #define TX66_CONTROL_FIFO_SPC_CYA_BITS 1 37058 #define TX66_CONTROL_FIFO_SPC_CYA_SHIFT 15 37059 37060 /* tx66 :: Control :: scramblerControl_ovr [14:14] */ 37061 #define TX66_CONTROL_SCRAMBLERCONTROL_OVR_MASK 0x4000 37062 #define TX66_CONTROL_SCRAMBLERCONTROL_OVR_ALIGN 0 37063 #define TX66_CONTROL_SCRAMBLERCONTROL_OVR_BITS 1 37064 #define TX66_CONTROL_SCRAMBLERCONTROL_OVR_SHIFT 14 37065 37066 /* tx66 :: Control :: reserved0 [13:11] */ 37067 #define TX66_CONTROL_RESERVED0_MASK 0x3800 37068 #define TX66_CONTROL_RESERVED0_ALIGN 0 37069 #define TX66_CONTROL_RESERVED0_BITS 3 37070 #define TX66_CONTROL_RESERVED0_SHIFT 11 37071 37072 /* tx66 :: Control :: use_local_afrst [10:10] */ 37073 #define TX66_CONTROL_USE_LOCAL_AFRST_MASK 0x0400 37074 #define TX66_CONTROL_USE_LOCAL_AFRST_ALIGN 0 37075 #define TX66_CONTROL_USE_LOCAL_AFRST_BITS 1 37076 #define TX66_CONTROL_USE_LOCAL_AFRST_SHIFT 10 37077 37078 /* tx66 :: Control :: use_local_prst [09:09] */ 37079 #define TX66_CONTROL_USE_LOCAL_PRST_MASK 0x0200 37080 #define TX66_CONTROL_USE_LOCAL_PRST_ALIGN 0 37081 #define TX66_CONTROL_USE_LOCAL_PRST_BITS 1 37082 #define TX66_CONTROL_USE_LOCAL_PRST_SHIFT 9 37083 37084 /* tx66 :: Control :: force_cl72_tfifo_fprst_val [08:08] */ 37085 #define TX66_CONTROL_FORCE_CL72_TFIFO_FPRST_VAL_MASK 0x0100 37086 #define TX66_CONTROL_FORCE_CL72_TFIFO_FPRST_VAL_ALIGN 0 37087 #define TX66_CONTROL_FORCE_CL72_TFIFO_FPRST_VAL_BITS 1 37088 #define TX66_CONTROL_FORCE_CL72_TFIFO_FPRST_VAL_SHIFT 8 37089 37090 /* tx66 :: Control :: force_cl72_tfifo_fprst_en [07:07] */ 37091 #define TX66_CONTROL_FORCE_CL72_TFIFO_FPRST_EN_MASK 0x0080 37092 #define TX66_CONTROL_FORCE_CL72_TFIFO_FPRST_EN_ALIGN 0 37093 #define TX66_CONTROL_FORCE_CL72_TFIFO_FPRST_EN_BITS 1 37094 #define TX66_CONTROL_FORCE_CL72_TFIFO_FPRST_EN_SHIFT 7 37095 37096 /* tx66 :: Control :: tfifo_ptr_sw_rst [06:06] */ 37097 #define TX66_CONTROL_TFIFO_PTR_SW_RST_MASK 0x0040 37098 #define TX66_CONTROL_TFIFO_PTR_SW_RST_ALIGN 0 37099 #define TX66_CONTROL_TFIFO_PTR_SW_RST_BITS 1 37100 #define TX66_CONTROL_TFIFO_PTR_SW_RST_SHIFT 6 37101 37102 /* tx66 :: Control :: brcm_cl49_tx_fault_en [05:05] */ 37103 #define TX66_CONTROL_BRCM_CL49_TX_FAULT_EN_MASK 0x0020 37104 #define TX66_CONTROL_BRCM_CL49_TX_FAULT_EN_ALIGN 0 37105 #define TX66_CONTROL_BRCM_CL49_TX_FAULT_EN_BITS 1 37106 #define TX66_CONTROL_BRCM_CL49_TX_FAULT_EN_SHIFT 5 37107 37108 /* tx66 :: Control :: rloop_en [04:04] */ 37109 #define TX66_CONTROL_RLOOP_EN_MASK 0x0010 37110 #define TX66_CONTROL_RLOOP_EN_ALIGN 0 37111 #define TX66_CONTROL_RLOOP_EN_BITS 1 37112 #define TX66_CONTROL_RLOOP_EN_SHIFT 4 37113 37114 /* tx66 :: Control :: scramblerControl [03:02] */ 37115 #define TX66_CONTROL_SCRAMBLERCONTROL_MASK 0x000c 37116 #define TX66_CONTROL_SCRAMBLERCONTROL_ALIGN 0 37117 #define TX66_CONTROL_SCRAMBLERCONTROL_BITS 2 37118 #define TX66_CONTROL_SCRAMBLERCONTROL_SHIFT 2 37119 37120 /* tx66 :: Control :: tfifo_sbitclr [01:01] */ 37121 #define TX66_CONTROL_TFIFO_SBITCLR_MASK 0x0002 37122 #define TX66_CONTROL_TFIFO_SBITCLR_ALIGN 0 37123 #define TX66_CONTROL_TFIFO_SBITCLR_BITS 1 37124 #define TX66_CONTROL_TFIFO_SBITCLR_SHIFT 1 37125 37126 /* tx66 :: Control :: tfifo_afrst_en [00:00] */ 37127 #define TX66_CONTROL_TFIFO_AFRST_EN_MASK 0x0001 37128 #define TX66_CONTROL_TFIFO_AFRST_EN_ALIGN 0 37129 #define TX66_CONTROL_TFIFO_AFRST_EN_BITS 1 37130 #define TX66_CONTROL_TFIFO_AFRST_EN_SHIFT 0 37131 37132 37133 /**************************************************************************** 37134 * tx66 :: Status 37135 */ 37136 /* tx66 :: Status :: reserved_for_eco0 [15:03] */ 37137 #define TX66_STATUS_RESERVED_FOR_ECO0_MASK 0xfff8 37138 #define TX66_STATUS_RESERVED_FOR_ECO0_ALIGN 0 37139 #define TX66_STATUS_RESERVED_FOR_ECO0_BITS 13 37140 #define TX66_STATUS_RESERVED_FOR_ECO0_SHIFT 3 37141 37142 /* tx66 :: Status :: ovflow [02:02] */ 37143 #define TX66_STATUS_OVFLOW_MASK 0x0004 37144 #define TX66_STATUS_OVFLOW_ALIGN 0 37145 #define TX66_STATUS_OVFLOW_BITS 1 37146 #define TX66_STATUS_OVFLOW_SHIFT 2 37147 37148 /* tx66 :: Status :: unflow [01:01] */ 37149 #define TX66_STATUS_UNFLOW_MASK 0x0002 37150 #define TX66_STATUS_UNFLOW_ALIGN 0 37151 #define TX66_STATUS_UNFLOW_BITS 1 37152 #define TX66_STATUS_UNFLOW_SHIFT 1 37153 37154 /* tx66 :: Status :: ferr [00:00] */ 37155 #define TX66_STATUS_FERR_MASK 0x0001 37156 #define TX66_STATUS_FERR_ALIGN 0 37157 #define TX66_STATUS_FERR_BITS 1 37158 #define TX66_STATUS_FERR_SHIFT 0 37159 37160 37161 /**************************************************************************** 37162 * tx66 :: Progmmable_TL 37163 */ 37164 /* tx66 :: Progmmable_TL :: reserved_for_eco0 [15:09] */ 37165 #define TX66_PROGMMABLE_TL_RESERVED_FOR_ECO0_MASK 0xfe00 37166 #define TX66_PROGMMABLE_TL_RESERVED_FOR_ECO0_ALIGN 0 37167 #define TX66_PROGMMABLE_TL_RESERVED_FOR_ECO0_BITS 7 37168 #define TX66_PROGMMABLE_TL_RESERVED_FOR_ECO0_SHIFT 9 37169 37170 /* tx66 :: Progmmable_TL :: prog_tl_en [08:08] */ 37171 #define TX66_PROGMMABLE_TL_PROG_TL_EN_MASK 0x0100 37172 #define TX66_PROGMMABLE_TL_PROG_TL_EN_ALIGN 0 37173 #define TX66_PROGMMABLE_TL_PROG_TL_EN_BITS 1 37174 #define TX66_PROGMMABLE_TL_PROG_TL_EN_SHIFT 8 37175 37176 /* tx66 :: Progmmable_TL :: prog_tl_char [07:00] */ 37177 #define TX66_PROGMMABLE_TL_PROG_TL_CHAR_MASK 0x00ff 37178 #define TX66_PROGMMABLE_TL_PROG_TL_CHAR_ALIGN 0 37179 #define TX66_PROGMMABLE_TL_PROG_TL_CHAR_BITS 8 37180 #define TX66_PROGMMABLE_TL_PROG_TL_CHAR_SHIFT 0 37181 37182 37183 /**************************************************************************** 37184 * Warpcore_USER_rx66 37185 */ 37186 /**************************************************************************** 37187 * rx66 :: Control 37188 */ 37189 /* rx66 :: Control :: fifo_spc_cya [15:15] */ 37190 #define RX66_CONTROL_FIFO_SPC_CYA_MASK 0x8000 37191 #define RX66_CONTROL_FIFO_SPC_CYA_ALIGN 0 37192 #define RX66_CONTROL_FIFO_SPC_CYA_BITS 1 37193 #define RX66_CONTROL_FIFO_SPC_CYA_SHIFT 15 37194 37195 /* rx66 :: Control :: cc_data_sel [14:14] */ 37196 #define RX66_CONTROL_CC_DATA_SEL_MASK 0x4000 37197 #define RX66_CONTROL_CC_DATA_SEL_ALIGN 0 37198 #define RX66_CONTROL_CC_DATA_SEL_BITS 1 37199 #define RX66_CONTROL_CC_DATA_SEL_SHIFT 14 37200 37201 /* rx66 :: Control :: cc_en [13:13] */ 37202 #define RX66_CONTROL_CC_EN_MASK 0x2000 37203 #define RX66_CONTROL_CC_EN_ALIGN 0 37204 #define RX66_CONTROL_CC_EN_BITS 1 37205 #define RX66_CONTROL_CC_EN_SHIFT 13 37206 37207 /* rx66 :: Control :: cc_afrst_en [12:12] */ 37208 #define RX66_CONTROL_CC_AFRST_EN_MASK 0x1000 37209 #define RX66_CONTROL_CC_AFRST_EN_ALIGN 0 37210 #define RX66_CONTROL_CC_AFRST_EN_BITS 1 37211 #define RX66_CONTROL_CC_AFRST_EN_SHIFT 12 37212 37213 /* rx66 :: Control :: cc_noIPG_en [11:11] */ 37214 #define RX66_CONTROL_CC_NOIPG_EN_MASK 0x0800 37215 #define RX66_CONTROL_CC_NOIPG_EN_ALIGN 0 37216 #define RX66_CONTROL_CC_NOIPG_EN_BITS 1 37217 #define RX66_CONTROL_CC_NOIPG_EN_SHIFT 11 37218 37219 /* rx66 :: Control :: cc_gt1_I_dis [10:10] */ 37220 #define RX66_CONTROL_CC_GT1_I_DIS_MASK 0x0400 37221 #define RX66_CONTROL_CC_GT1_I_DIS_ALIGN 0 37222 #define RX66_CONTROL_CC_GT1_I_DIS_BITS 1 37223 #define RX66_CONTROL_CC_GT1_I_DIS_SHIFT 10 37224 37225 /* rx66 :: Control :: rxSeqDoneMask [09:09] */ 37226 #define RX66_CONTROL_RXSEQDONEMASK_MASK 0x0200 37227 #define RX66_CONTROL_RXSEQDONEMASK_ALIGN 0 37228 #define RX66_CONTROL_RXSEQDONEMASK_BITS 1 37229 #define RX66_CONTROL_RXSEQDONEMASK_SHIFT 9 37230 37231 /* rx66 :: Control :: cwCount_sel [08:08] */ 37232 #define RX66_CONTROL_CWCOUNT_SEL_MASK 0x0100 37233 #define RX66_CONTROL_CWCOUNT_SEL_ALIGN 0 37234 #define RX66_CONTROL_CWCOUNT_SEL_BITS 1 37235 #define RX66_CONTROL_CWCOUNT_SEL_SHIFT 8 37236 37237 /* rx66 :: Control :: cwCount_en [07:07] */ 37238 #define RX66_CONTROL_CWCOUNT_EN_MASK 0x0080 37239 #define RX66_CONTROL_CWCOUNT_EN_ALIGN 0 37240 #define RX66_CONTROL_CWCOUNT_EN_BITS 1 37241 #define RX66_CONTROL_CWCOUNT_EN_SHIFT 7 37242 37243 /* rx66 :: Control :: sync66ErrCount_en [06:06] */ 37244 #define RX66_CONTROL_SYNC66ERRCOUNT_EN_MASK 0x0040 37245 #define RX66_CONTROL_SYNC66ERRCOUNT_EN_ALIGN 0 37246 #define RX66_CONTROL_SYNC66ERRCOUNT_EN_BITS 1 37247 #define RX66_CONTROL_SYNC66ERRCOUNT_EN_SHIFT 6 37248 37249 /* rx66 :: Control :: kcode66ErrCount_en [05:05] */ 37250 #define RX66_CONTROL_KCODE66ERRCOUNT_EN_MASK 0x0020 37251 #define RX66_CONTROL_KCODE66ERRCOUNT_EN_ALIGN 0 37252 #define RX66_CONTROL_KCODE66ERRCOUNT_EN_BITS 1 37253 #define RX66_CONTROL_KCODE66ERRCOUNT_EN_SHIFT 5 37254 37255 /* rx66 :: Control :: cgbad_kcode66Err_en [04:04] */ 37256 #define RX66_CONTROL_CGBAD_KCODE66ERR_EN_MASK 0x0010 37257 #define RX66_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN 0 37258 #define RX66_CONTROL_CGBAD_KCODE66ERR_EN_BITS 1 37259 #define RX66_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT 4 37260 37261 /* rx66 :: Control :: descramblerControl [03:02] */ 37262 #define RX66_CONTROL_DESCRAMBLERCONTROL_MASK 0x000c 37263 #define RX66_CONTROL_DESCRAMBLERCONTROL_ALIGN 0 37264 #define RX66_CONTROL_DESCRAMBLERCONTROL_BITS 2 37265 #define RX66_CONTROL_DESCRAMBLERCONTROL_SHIFT 2 37266 37267 /* rx66 :: Control :: rfifo_sbitclr [01:01] */ 37268 #define RX66_CONTROL_RFIFO_SBITCLR_MASK 0x0002 37269 #define RX66_CONTROL_RFIFO_SBITCLR_ALIGN 0 37270 #define RX66_CONTROL_RFIFO_SBITCLR_BITS 1 37271 #define RX66_CONTROL_RFIFO_SBITCLR_SHIFT 1 37272 37273 /* rx66 :: Control :: rfifo_afrst_en [00:00] */ 37274 #define RX66_CONTROL_RFIFO_AFRST_EN_MASK 0x0001 37275 #define RX66_CONTROL_RFIFO_AFRST_EN_ALIGN 0 37276 #define RX66_CONTROL_RFIFO_AFRST_EN_BITS 1 37277 #define RX66_CONTROL_RFIFO_AFRST_EN_SHIFT 0 37278 37279 37280 /**************************************************************************** 37281 * rx66 :: Status 37282 */ 37283 /* rx66 :: Status :: LOSS_OF_SYNC [15:15] */ 37284 #define RX66_STATUS_LOSS_OF_SYNC_MASK 0x8000 37285 #define RX66_STATUS_LOSS_OF_SYNC_ALIGN 0 37286 #define RX66_STATUS_LOSS_OF_SYNC_BITS 1 37287 #define RX66_STATUS_LOSS_OF_SYNC_SHIFT 15 37288 37289 /* rx66 :: Status :: COMMA_DETECT [14:14] */ 37290 #define RX66_STATUS_COMMA_DETECT_MASK 0x4000 37291 #define RX66_STATUS_COMMA_DETECT_ALIGN 0 37292 #define RX66_STATUS_COMMA_DETECT_BITS 1 37293 #define RX66_STATUS_COMMA_DETECT_SHIFT 14 37294 37295 /* rx66 :: Status :: SYNC_ACQD1 [13:13] */ 37296 #define RX66_STATUS_SYNC_ACQD1_MASK 0x2000 37297 #define RX66_STATUS_SYNC_ACQD1_ALIGN 0 37298 #define RX66_STATUS_SYNC_ACQD1_BITS 1 37299 #define RX66_STATUS_SYNC_ACQD1_SHIFT 13 37300 37301 /* rx66 :: Status :: SYNC_ACQD2 [12:12] */ 37302 #define RX66_STATUS_SYNC_ACQD2_MASK 0x1000 37303 #define RX66_STATUS_SYNC_ACQD2_ALIGN 0 37304 #define RX66_STATUS_SYNC_ACQD2_BITS 1 37305 #define RX66_STATUS_SYNC_ACQD2_SHIFT 12 37306 37307 /* rx66 :: Status :: reserved0 [11:06] */ 37308 #define RX66_STATUS_RESERVED0_MASK 0x0fc0 37309 #define RX66_STATUS_RESERVED0_ALIGN 0 37310 #define RX66_STATUS_RESERVED0_BITS 6 37311 #define RX66_STATUS_RESERVED0_SHIFT 6 37312 37313 /* rx66 :: Status :: cc_ovflow [05:05] */ 37314 #define RX66_STATUS_CC_OVFLOW_MASK 0x0020 37315 #define RX66_STATUS_CC_OVFLOW_ALIGN 0 37316 #define RX66_STATUS_CC_OVFLOW_BITS 1 37317 #define RX66_STATUS_CC_OVFLOW_SHIFT 5 37318 37319 /* rx66 :: Status :: cc_unflow [04:04] */ 37320 #define RX66_STATUS_CC_UNFLOW_MASK 0x0010 37321 #define RX66_STATUS_CC_UNFLOW_ALIGN 0 37322 #define RX66_STATUS_CC_UNFLOW_BITS 1 37323 #define RX66_STATUS_CC_UNFLOW_SHIFT 4 37324 37325 /* rx66 :: Status :: syncDone [03:03] */ 37326 #define RX66_STATUS_SYNCDONE_MASK 0x0008 37327 #define RX66_STATUS_SYNCDONE_ALIGN 0 37328 #define RX66_STATUS_SYNCDONE_BITS 1 37329 #define RX66_STATUS_SYNCDONE_SHIFT 3 37330 37331 /* rx66 :: Status :: unflow [02:02] */ 37332 #define RX66_STATUS_UNFLOW_MASK 0x0004 37333 #define RX66_STATUS_UNFLOW_ALIGN 0 37334 #define RX66_STATUS_UNFLOW_BITS 1 37335 #define RX66_STATUS_UNFLOW_SHIFT 2 37336 37337 /* rx66 :: Status :: ovflow [01:01] */ 37338 #define RX66_STATUS_OVFLOW_MASK 0x0002 37339 #define RX66_STATUS_OVFLOW_ALIGN 0 37340 #define RX66_STATUS_OVFLOW_BITS 1 37341 #define RX66_STATUS_OVFLOW_SHIFT 1 37342 37343 /* rx66 :: Status :: ferr [00:00] */ 37344 #define RX66_STATUS_FERR_MASK 0x0001 37345 #define RX66_STATUS_FERR_ALIGN 0 37346 #define RX66_STATUS_FERR_BITS 1 37347 #define RX66_STATUS_FERR_SHIFT 0 37348 37349 37350 /**************************************************************************** 37351 * rx66 :: scw0 37352 */ 37353 /* rx66 :: scw0 :: scw0 [15:00] */ 37354 #define RX66_SCW0_SCW0_MASK 0xffff 37355 #define RX66_SCW0_SCW0_ALIGN 0 37356 #define RX66_SCW0_SCW0_BITS 16 37357 #define RX66_SCW0_SCW0_SHIFT 0 37358 37359 37360 /**************************************************************************** 37361 * rx66 :: scw1 37362 */ 37363 /* rx66 :: scw1 :: scw1 [15:00] */ 37364 #define RX66_SCW1_SCW1_MASK 0xffff 37365 #define RX66_SCW1_SCW1_ALIGN 0 37366 #define RX66_SCW1_SCW1_BITS 16 37367 #define RX66_SCW1_SCW1_SHIFT 0 37368 37369 37370 /**************************************************************************** 37371 * rx66 :: scw2 37372 */ 37373 /* rx66 :: scw2 :: scw2 [15:00] */ 37374 #define RX66_SCW2_SCW2_MASK 0xffff 37375 #define RX66_SCW2_SCW2_ALIGN 0 37376 #define RX66_SCW2_SCW2_BITS 16 37377 #define RX66_SCW2_SCW2_SHIFT 0 37378 37379 37380 /**************************************************************************** 37381 * rx66 :: scw3 37382 */ 37383 /* rx66 :: scw3 :: scw3 [15:00] */ 37384 #define RX66_SCW3_SCW3_MASK 0xffff 37385 #define RX66_SCW3_SCW3_ALIGN 0 37386 #define RX66_SCW3_SCW3_BITS 16 37387 #define RX66_SCW3_SCW3_SHIFT 0 37388 37389 37390 /**************************************************************************** 37391 * rx66 :: scw0_mask 37392 */ 37393 /* rx66 :: scw0_mask :: scw0_mask [15:00] */ 37394 #define RX66_SCW0_MASK_SCW0_MASK_MASK 0xffff 37395 #define RX66_SCW0_MASK_SCW0_MASK_ALIGN 0 37396 #define RX66_SCW0_MASK_SCW0_MASK_BITS 16 37397 #define RX66_SCW0_MASK_SCW0_MASK_SHIFT 0 37398 37399 37400 /**************************************************************************** 37401 * rx66 :: scw1_mask 37402 */ 37403 /* rx66 :: scw1_mask :: scw1_mask [15:00] */ 37404 #define RX66_SCW1_MASK_SCW1_MASK_MASK 0xffff 37405 #define RX66_SCW1_MASK_SCW1_MASK_ALIGN 0 37406 #define RX66_SCW1_MASK_SCW1_MASK_BITS 16 37407 #define RX66_SCW1_MASK_SCW1_MASK_SHIFT 0 37408 37409 37410 /**************************************************************************** 37411 * rx66 :: scw2_mask 37412 */ 37413 /* rx66 :: scw2_mask :: scw2_mask [15:00] */ 37414 #define RX66_SCW2_MASK_SCW2_MASK_MASK 0xffff 37415 #define RX66_SCW2_MASK_SCW2_MASK_ALIGN 0 37416 #define RX66_SCW2_MASK_SCW2_MASK_BITS 16 37417 #define RX66_SCW2_MASK_SCW2_MASK_SHIFT 0 37418 37419 37420 /**************************************************************************** 37421 * rx66 :: scw3_mask 37422 */ 37423 /* rx66 :: scw3_mask :: scw3_mask [15:00] */ 37424 #define RX66_SCW3_MASK_SCW3_MASK_MASK 0xffff 37425 #define RX66_SCW3_MASK_SCW3_MASK_ALIGN 0 37426 #define RX66_SCW3_MASK_SCW3_MASK_BITS 16 37427 #define RX66_SCW3_MASK_SCW3_MASK_SHIFT 0 37428 37429 37430 /**************************************************************************** 37431 * rx66 :: syncbits 37432 */ 37433 /* rx66 :: syncbits :: cc_tmsel [15:13] */ 37434 #define RX66_SYNCBITS_CC_TMSEL_MASK 0xe000 37435 #define RX66_SYNCBITS_CC_TMSEL_ALIGN 0 37436 #define RX66_SYNCBITS_CC_TMSEL_BITS 3 37437 #define RX66_SYNCBITS_CC_TMSEL_SHIFT 13 37438 37439 /* rx66 :: syncbits :: prog_tl_en [12:12] */ 37440 #define RX66_SYNCBITS_PROG_TL_EN_MASK 0x1000 37441 #define RX66_SYNCBITS_PROG_TL_EN_ALIGN 0 37442 #define RX66_SYNCBITS_PROG_TL_EN_BITS 1 37443 #define RX66_SYNCBITS_PROG_TL_EN_SHIFT 12 37444 37445 /* rx66 :: syncbits :: prog_tl_char [11:04] */ 37446 #define RX66_SYNCBITS_PROG_TL_CHAR_MASK 0x0ff0 37447 #define RX66_SYNCBITS_PROG_TL_CHAR_ALIGN 0 37448 #define RX66_SYNCBITS_PROG_TL_CHAR_BITS 8 37449 #define RX66_SYNCBITS_PROG_TL_CHAR_SHIFT 4 37450 37451 /* rx66 :: syncbits :: syncbits [03:02] */ 37452 #define RX66_SYNCBITS_SYNCBITS_MASK 0x000c 37453 #define RX66_SYNCBITS_SYNCBITS_ALIGN 0 37454 #define RX66_SYNCBITS_SYNCBITS_BITS 2 37455 #define RX66_SYNCBITS_SYNCBITS_SHIFT 2 37456 37457 /* rx66 :: syncbits :: syncbits_mask [01:00] */ 37458 #define RX66_SYNCBITS_SYNCBITS_MASK_MASK 0x0003 37459 #define RX66_SYNCBITS_SYNCBITS_MASK_ALIGN 0 37460 #define RX66_SYNCBITS_SYNCBITS_MASK_BITS 2 37461 #define RX66_SYNCBITS_SYNCBITS_MASK_SHIFT 0 37462 37463 37464 /**************************************************************************** 37465 * rx66 :: scwControl 37466 */ 37467 /* rx66 :: scwControl :: descramblerControl_ovr [15:15] */ 37468 #define RX66_SCWCONTROL_DESCRAMBLERCONTROL_OVR_MASK 0x8000 37469 #define RX66_SCWCONTROL_DESCRAMBLERCONTROL_OVR_ALIGN 0 37470 #define RX66_SCWCONTROL_DESCRAMBLERCONTROL_OVR_BITS 1 37471 #define RX66_SCWCONTROL_DESCRAMBLERCONTROL_OVR_SHIFT 15 37472 37473 /* rx66 :: scwControl :: scwCount [14:10] */ 37474 #define RX66_SCWCONTROL_SCWCOUNT_MASK 0x7c00 37475 #define RX66_SCWCONTROL_SCWCOUNT_ALIGN 0 37476 #define RX66_SCWCONTROL_SCWCOUNT_BITS 5 37477 #define RX66_SCWCONTROL_SCWCOUNT_SHIFT 10 37478 37479 /* rx66 :: scwControl :: gcwCount [09:05] */ 37480 #define RX66_SCWCONTROL_GCWCOUNT_MASK 0x03e0 37481 #define RX66_SCWCONTROL_GCWCOUNT_ALIGN 0 37482 #define RX66_SCWCONTROL_GCWCOUNT_BITS 5 37483 #define RX66_SCWCONTROL_GCWCOUNT_SHIFT 5 37484 37485 /* rx66 :: scwControl :: hystCount [04:00] */ 37486 #define RX66_SCWCONTROL_HYSTCOUNT_MASK 0x001f 37487 #define RX66_SCWCONTROL_HYSTCOUNT_ALIGN 0 37488 #define RX66_SCWCONTROL_HYSTCOUNT_BITS 5 37489 #define RX66_SCWCONTROL_HYSTCOUNT_SHIFT 0 37490 37491 37492 /**************************************************************************** 37493 * rx66 :: cc_eventCount 37494 */ 37495 /* rx66 :: cc_eventCount :: cc_event_count [15:00] */ 37496 #define RX66_CC_EVENTCOUNT_CC_EVENT_COUNT_MASK 0xffff 37497 #define RX66_CC_EVENTCOUNT_CC_EVENT_COUNT_ALIGN 0 37498 #define RX66_CC_EVENTCOUNT_CC_EVENT_COUNT_BITS 16 37499 #define RX66_CC_EVENTCOUNT_CC_EVENT_COUNT_SHIFT 0 37500 37501 37502 /**************************************************************************** 37503 * rx66 :: scwCount 37504 */ 37505 /* rx66 :: scwCount :: reserved0 [15:15] */ 37506 #define RX66_SCWCOUNT_RESERVED0_MASK 0x8000 37507 #define RX66_SCWCOUNT_RESERVED0_ALIGN 0 37508 #define RX66_SCWCOUNT_RESERVED0_BITS 1 37509 #define RX66_SCWCOUNT_RESERVED0_SHIFT 15 37510 37511 /* rx66 :: scwCount :: scwShift [14:08] */ 37512 #define RX66_SCWCOUNT_SCWSHIFT_MASK 0x7f00 37513 #define RX66_SCWCOUNT_SCWSHIFT_ALIGN 0 37514 #define RX66_SCWCOUNT_SCWSHIFT_BITS 7 37515 #define RX66_SCWCOUNT_SCWSHIFT_SHIFT 8 37516 37517 /* union - case COMMA_DETECT [07:00] */ 37518 /* rx66 :: scwCount :: cwCount [07:00] */ 37519 #define RX66_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK 0x00ff 37520 #define RX66_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN 0 37521 #define RX66_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS 8 37522 #define RX66_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT 0 37523 37524 37525 /* union - case SYNC_ACQD2 [07:00] */ 37526 /* rx66 :: scwCount :: cwCount [07:00] */ 37527 #define RX66_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK 0x00ff 37528 #define RX66_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN 0 37529 #define RX66_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS 8 37530 #define RX66_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT 0 37531 37532 37533 37534 /**************************************************************************** 37535 * rx66 :: errCount 37536 */ 37537 /* rx66 :: errCount :: sync66ErrCount [15:08] */ 37538 #define RX66_ERRCOUNT_SYNC66ERRCOUNT_MASK 0xff00 37539 #define RX66_ERRCOUNT_SYNC66ERRCOUNT_ALIGN 0 37540 #define RX66_ERRCOUNT_SYNC66ERRCOUNT_BITS 8 37541 #define RX66_ERRCOUNT_SYNC66ERRCOUNT_SHIFT 8 37542 37543 /* rx66 :: errCount :: kcode66ErrCount [07:00] */ 37544 #define RX66_ERRCOUNT_KCODE66ERRCOUNT_MASK 0x00ff 37545 #define RX66_ERRCOUNT_KCODE66ERRCOUNT_ALIGN 0 37546 #define RX66_ERRCOUNT_KCODE66ERRCOUNT_BITS 8 37547 #define RX66_ERRCOUNT_KCODE66ERRCOUNT_SHIFT 0 37548 37549 37550 /**************************************************************************** 37551 * Warpcore_USER_LnTxBert 37552 */ 37553 /**************************************************************************** 37554 * LnTxBert :: txBertCtrl 37555 */ 37556 /* LnTxBert :: txBertCtrl :: pkt_en [15:15] */ 37557 #define LNTXBERT_TXBERTCTRL_PKT_EN_MASK 0x8000 37558 #define LNTXBERT_TXBERTCTRL_PKT_EN_ALIGN 0 37559 #define LNTXBERT_TXBERTCTRL_PKT_EN_BITS 1 37560 #define LNTXBERT_TXBERTCTRL_PKT_EN_SHIFT 15 37561 37562 /* LnTxBert :: txBertCtrl :: seed_ld [14:14] */ 37563 #define LNTXBERT_TXBERTCTRL_SEED_LD_MASK 0x4000 37564 #define LNTXBERT_TXBERTCTRL_SEED_LD_ALIGN 0 37565 #define LNTXBERT_TXBERTCTRL_SEED_LD_BITS 1 37566 #define LNTXBERT_TXBERTCTRL_SEED_LD_SHIFT 14 37567 37568 /* LnTxBert :: txBertCtrl :: prbs_order [13:12] */ 37569 #define LNTXBERT_TXBERTCTRL_PRBS_ORDER_MASK 0x3000 37570 #define LNTXBERT_TXBERTCTRL_PRBS_ORDER_ALIGN 0 37571 #define LNTXBERT_TXBERTCTRL_PRBS_ORDER_BITS 2 37572 #define LNTXBERT_TXBERTCTRL_PRBS_ORDER_SHIFT 12 37573 37574 /* LnTxBert :: txBertCtrl :: ramp_en [11:11] */ 37575 #define LNTXBERT_TXBERTCTRL_RAMP_EN_MASK 0x0800 37576 #define LNTXBERT_TXBERTCTRL_RAMP_EN_ALIGN 0 37577 #define LNTXBERT_TXBERTCTRL_RAMP_EN_BITS 1 37578 #define LNTXBERT_TXBERTCTRL_RAMP_EN_SHIFT 11 37579 37580 /* LnTxBert :: txBertCtrl :: rndm_en [10:10] */ 37581 #define LNTXBERT_TXBERTCTRL_RNDM_EN_MASK 0x0400 37582 #define LNTXBERT_TXBERTCTRL_RNDM_EN_ALIGN 0 37583 #define LNTXBERT_TXBERTCTRL_RNDM_EN_BITS 1 37584 #define LNTXBERT_TXBERTCTRL_RNDM_EN_SHIFT 10 37585 37586 /* LnTxBert :: txBertCtrl :: Q_en [09:09] */ 37587 #define LNTXBERT_TXBERTCTRL_Q_EN_MASK 0x0200 37588 #define LNTXBERT_TXBERTCTRL_Q_EN_ALIGN 0 37589 #define LNTXBERT_TXBERTCTRL_Q_EN_BITS 1 37590 #define LNTXBERT_TXBERTCTRL_Q_EN_SHIFT 9 37591 37592 /* LnTxBert :: txBertCtrl :: Q_link_en [08:08] */ 37593 #define LNTXBERT_TXBERTCTRL_Q_LINK_EN_MASK 0x0100 37594 #define LNTXBERT_TXBERTCTRL_Q_LINK_EN_ALIGN 0 37595 #define LNTXBERT_TXBERTCTRL_Q_LINK_EN_BITS 1 37596 #define LNTXBERT_TXBERTCTRL_Q_LINK_EN_SHIFT 8 37597 37598 /* LnTxBert :: txBertCtrl :: skew_en [07:07] */ 37599 #define LNTXBERT_TXBERTCTRL_SKEW_EN_MASK 0x0080 37600 #define LNTXBERT_TXBERTCTRL_SKEW_EN_ALIGN 0 37601 #define LNTXBERT_TXBERTCTRL_SKEW_EN_BITS 1 37602 #define LNTXBERT_TXBERTCTRL_SKEW_EN_SHIFT 7 37603 37604 /* LnTxBert :: txBertCtrl :: cjpat_en [06:06] */ 37605 #define LNTXBERT_TXBERTCTRL_CJPAT_EN_MASK 0x0040 37606 #define LNTXBERT_TXBERTCTRL_CJPAT_EN_ALIGN 0 37607 #define LNTXBERT_TXBERTCTRL_CJPAT_EN_BITS 1 37608 #define LNTXBERT_TXBERTCTRL_CJPAT_EN_SHIFT 6 37609 37610 /* LnTxBert :: txBertCtrl :: crpat_en [05:05] */ 37611 #define LNTXBERT_TXBERTCTRL_CRPAT_EN_MASK 0x0020 37612 #define LNTXBERT_TXBERTCTRL_CRPAT_EN_ALIGN 0 37613 #define LNTXBERT_TXBERTCTRL_CRPAT_EN_BITS 1 37614 #define LNTXBERT_TXBERTCTRL_CRPAT_EN_SHIFT 5 37615 37616 /* LnTxBert :: txBertCtrl :: cjrmp_en [04:04] */ 37617 #define LNTXBERT_TXBERTCTRL_CJRMP_EN_MASK 0x0010 37618 #define LNTXBERT_TXBERTCTRL_CJRMP_EN_ALIGN 0 37619 #define LNTXBERT_TXBERTCTRL_CJRMP_EN_BITS 1 37620 #define LNTXBERT_TXBERTCTRL_CJRMP_EN_SHIFT 4 37621 37622 /* LnTxBert :: txBertCtrl :: txck_out_force [03:03] */ 37623 #define LNTXBERT_TXBERTCTRL_TXCK_OUT_FORCE_MASK 0x0008 37624 #define LNTXBERT_TXBERTCTRL_TXCK_OUT_FORCE_ALIGN 0 37625 #define LNTXBERT_TXBERTCTRL_TXCK_OUT_FORCE_BITS 1 37626 #define LNTXBERT_TXBERTCTRL_TXCK_OUT_FORCE_SHIFT 3 37627 37628 /* LnTxBert :: txBertCtrl :: fifo_rst [02:02] */ 37629 #define LNTXBERT_TXBERTCTRL_FIFO_RST_MASK 0x0004 37630 #define LNTXBERT_TXBERTCTRL_FIFO_RST_ALIGN 0 37631 #define LNTXBERT_TXBERTCTRL_FIFO_RST_BITS 1 37632 #define LNTXBERT_TXBERTCTRL_FIFO_RST_SHIFT 2 37633 37634 /* LnTxBert :: txBertCtrl :: countRst_dis [01:01] */ 37635 #define LNTXBERT_TXBERTCTRL_COUNTRST_DIS_MASK 0x0002 37636 #define LNTXBERT_TXBERTCTRL_COUNTRST_DIS_ALIGN 0 37637 #define LNTXBERT_TXBERTCTRL_COUNTRST_DIS_BITS 1 37638 #define LNTXBERT_TXBERTCTRL_COUNTRST_DIS_SHIFT 1 37639 37640 /* LnTxBert :: txBertCtrl :: count_clr [00:00] */ 37641 #define LNTXBERT_TXBERTCTRL_COUNT_CLR_MASK 0x0001 37642 #define LNTXBERT_TXBERTCTRL_COUNT_CLR_ALIGN 0 37643 #define LNTXBERT_TXBERTCTRL_COUNT_CLR_BITS 1 37644 #define LNTXBERT_TXBERTCTRL_COUNT_CLR_SHIFT 0 37645 37646 37647 /**************************************************************************** 37648 * LnTxBert :: txBertSopEop 37649 */ 37650 /* LnTxBert :: txBertSopEop :: SOP [15:08] */ 37651 #define LNTXBERT_TXBERTSOPEOP_SOP_MASK 0xff00 37652 #define LNTXBERT_TXBERTSOPEOP_SOP_ALIGN 0 37653 #define LNTXBERT_TXBERTSOPEOP_SOP_BITS 8 37654 #define LNTXBERT_TXBERTSOPEOP_SOP_SHIFT 8 37655 37656 /* LnTxBert :: txBertSopEop :: EOP [07:00] */ 37657 #define LNTXBERT_TXBERTSOPEOP_EOP_MASK 0x00ff 37658 #define LNTXBERT_TXBERTSOPEOP_EOP_ALIGN 0 37659 #define LNTXBERT_TXBERTSOPEOP_EOP_BITS 8 37660 #define LNTXBERT_TXBERTSOPEOP_EOP_SHIFT 0 37661 37662 37663 /**************************************************************************** 37664 * LnTxBert :: txBertSize0 37665 */ 37666 /* LnTxBert :: txBertSize0 :: ipg_size [15:10] */ 37667 #define LNTXBERT_TXBERTSIZE0_IPG_SIZE_MASK 0xfc00 37668 #define LNTXBERT_TXBERTSIZE0_IPG_SIZE_ALIGN 0 37669 #define LNTXBERT_TXBERTSIZE0_IPG_SIZE_BITS 6 37670 #define LNTXBERT_TXBERTSIZE0_IPG_SIZE_SHIFT 10 37671 37672 /* LnTxBert :: txBertSize0 :: pkt_size [09:00] */ 37673 #define LNTXBERT_TXBERTSIZE0_PKT_SIZE_MASK 0x03ff 37674 #define LNTXBERT_TXBERTSIZE0_PKT_SIZE_ALIGN 0 37675 #define LNTXBERT_TXBERTSIZE0_PKT_SIZE_BITS 10 37676 #define LNTXBERT_TXBERTSIZE0_PKT_SIZE_SHIFT 0 37677 37678 37679 /**************************************************************************** 37680 * LnTxBert :: txBertSize1 37681 */ 37682 /* LnTxBert :: txBertSize1 :: awin_size [15:10] */ 37683 #define LNTXBERT_TXBERTSIZE1_AWIN_SIZE_MASK 0xfc00 37684 #define LNTXBERT_TXBERTSIZE1_AWIN_SIZE_ALIGN 0 37685 #define LNTXBERT_TXBERTSIZE1_AWIN_SIZE_BITS 6 37686 #define LNTXBERT_TXBERTSIZE1_AWIN_SIZE_SHIFT 10 37687 37688 /* LnTxBert :: txBertSize1 :: PktStpCnt [09:00] */ 37689 #define LNTXBERT_TXBERTSIZE1_PKTSTPCNT_MASK 0x03ff 37690 #define LNTXBERT_TXBERTSIZE1_PKTSTPCNT_ALIGN 0 37691 #define LNTXBERT_TXBERTSIZE1_PKTSTPCNT_BITS 10 37692 #define LNTXBERT_TXBERTSIZE1_PKTSTPCNT_SHIFT 0 37693 37694 37695 /**************************************************************************** 37696 * LnTxBert :: txBertSize2 37697 */ 37698 /* LnTxBert :: txBertSize2 :: skew3 [15:12] */ 37699 #define LNTXBERT_TXBERTSIZE2_SKEW3_MASK 0xf000 37700 #define LNTXBERT_TXBERTSIZE2_SKEW3_ALIGN 0 37701 #define LNTXBERT_TXBERTSIZE2_SKEW3_BITS 4 37702 #define LNTXBERT_TXBERTSIZE2_SKEW3_SHIFT 12 37703 37704 /* LnTxBert :: txBertSize2 :: skew2 [11:08] */ 37705 #define LNTXBERT_TXBERTSIZE2_SKEW2_MASK 0x0f00 37706 #define LNTXBERT_TXBERTSIZE2_SKEW2_ALIGN 0 37707 #define LNTXBERT_TXBERTSIZE2_SKEW2_BITS 4 37708 #define LNTXBERT_TXBERTSIZE2_SKEW2_SHIFT 8 37709 37710 /* LnTxBert :: txBertSize2 :: skew1 [07:04] */ 37711 #define LNTXBERT_TXBERTSIZE2_SKEW1_MASK 0x00f0 37712 #define LNTXBERT_TXBERTSIZE2_SKEW1_ALIGN 0 37713 #define LNTXBERT_TXBERTSIZE2_SKEW1_BITS 4 37714 #define LNTXBERT_TXBERTSIZE2_SKEW1_SHIFT 4 37715 37716 /* LnTxBert :: txBertSize2 :: skew0 [03:00] */ 37717 #define LNTXBERT_TXBERTSIZE2_SKEW0_MASK 0x000f 37718 #define LNTXBERT_TXBERTSIZE2_SKEW0_ALIGN 0 37719 #define LNTXBERT_TXBERTSIZE2_SKEW0_BITS 4 37720 #define LNTXBERT_TXBERTSIZE2_SKEW0_SHIFT 0 37721 37722 37723 /**************************************************************************** 37724 * LnTxBert :: txBertIpg0 37725 */ 37726 /* LnTxBert :: txBertIpg0 :: ipg1 [15:08] */ 37727 #define LNTXBERT_TXBERTIPG0_IPG1_MASK 0xff00 37728 #define LNTXBERT_TXBERTIPG0_IPG1_ALIGN 0 37729 #define LNTXBERT_TXBERTIPG0_IPG1_BITS 8 37730 #define LNTXBERT_TXBERTIPG0_IPG1_SHIFT 8 37731 37732 /* LnTxBert :: txBertIpg0 :: ipg0 [07:00] */ 37733 #define LNTXBERT_TXBERTIPG0_IPG0_MASK 0x00ff 37734 #define LNTXBERT_TXBERTIPG0_IPG0_ALIGN 0 37735 #define LNTXBERT_TXBERTIPG0_IPG0_BITS 8 37736 #define LNTXBERT_TXBERTIPG0_IPG0_SHIFT 0 37737 37738 37739 /**************************************************************************** 37740 * LnTxBert :: txBertIpg1 37741 */ 37742 /* LnTxBert :: txBertIpg1 :: ipg3 [15:08] */ 37743 #define LNTXBERT_TXBERTIPG1_IPG3_MASK 0xff00 37744 #define LNTXBERT_TXBERTIPG1_IPG3_ALIGN 0 37745 #define LNTXBERT_TXBERTIPG1_IPG3_BITS 8 37746 #define LNTXBERT_TXBERTIPG1_IPG3_SHIFT 8 37747 37748 /* LnTxBert :: txBertIpg1 :: ipg2 [07:00] */ 37749 #define LNTXBERT_TXBERTIPG1_IPG2_MASK 0x00ff 37750 #define LNTXBERT_TXBERTIPG1_IPG2_ALIGN 0 37751 #define LNTXBERT_TXBERTIPG1_IPG2_BITS 8 37752 #define LNTXBERT_TXBERTIPG1_IPG2_SHIFT 0 37753 37754 37755 /**************************************************************************** 37756 * LnTxBert :: txBertByteU 37757 */ 37758 /* LnTxBert :: txBertByteU :: byte_count_high [15:00] */ 37759 #define LNTXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_MASK 0xffff 37760 #define LNTXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN 0 37761 #define LNTXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_BITS 16 37762 #define LNTXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT 0 37763 37764 37765 /**************************************************************************** 37766 * LnTxBert :: txBertByteL 37767 */ 37768 /* LnTxBert :: txBertByteL :: byte_count_low [15:00] */ 37769 #define LNTXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_MASK 0xffff 37770 #define LNTXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_ALIGN 0 37771 #define LNTXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_BITS 16 37772 #define LNTXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_SHIFT 0 37773 37774 37775 /**************************************************************************** 37776 * LnTxBert :: txBertPacketU 37777 */ 37778 /* LnTxBert :: txBertPacketU :: pkt_count_high [15:00] */ 37779 #define LNTXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_MASK 0xffff 37780 #define LNTXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_ALIGN 0 37781 #define LNTXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_BITS 16 37782 #define LNTXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_SHIFT 0 37783 37784 37785 /**************************************************************************** 37786 * LnTxBert :: txBertPacketL 37787 */ 37788 /* LnTxBert :: txBertPacketL :: pkt_count_low [15:00] */ 37789 #define LNTXBERT_TXBERTPACKETL_PKT_COUNT_LOW_MASK 0xffff 37790 #define LNTXBERT_TXBERTPACKETL_PKT_COUNT_LOW_ALIGN 0 37791 #define LNTXBERT_TXBERTPACKETL_PKT_COUNT_LOW_BITS 16 37792 #define LNTXBERT_TXBERTPACKETL_PKT_COUNT_LOW_SHIFT 0 37793 37794 37795 /**************************************************************************** 37796 * LnTxBert :: txBertCtrl1 37797 */ 37798 /* LnTxBert :: txBertCtrl1 :: reserved0 [15:01] */ 37799 #define LNTXBERT_TXBERTCTRL1_RESERVED0_MASK 0xfffe 37800 #define LNTXBERT_TXBERTCTRL1_RESERVED0_ALIGN 0 37801 #define LNTXBERT_TXBERTCTRL1_RESERVED0_BITS 15 37802 #define LNTXBERT_TXBERTCTRL1_RESERVED0_SHIFT 1 37803 37804 /* LnTxBert :: txBertCtrl1 :: lpi_en [00:00] */ 37805 #define LNTXBERT_TXBERTCTRL1_LPI_EN_MASK 0x0001 37806 #define LNTXBERT_TXBERTCTRL1_LPI_EN_ALIGN 0 37807 #define LNTXBERT_TXBERTCTRL1_LPI_EN_BITS 1 37808 #define LNTXBERT_TXBERTCTRL1_LPI_EN_SHIFT 0 37809 37810 37811 /**************************************************************************** 37812 * Warpcore_USER_LnRxBert 37813 */ 37814 /**************************************************************************** 37815 * LnRxBert :: rxBertCtrl 37816 */ 37817 /* LnRxBert :: rxBertCtrl :: pkt_en [15:15] */ 37818 #define LNRXBERT_RXBERTCTRL_PKT_EN_MASK 0x8000 37819 #define LNRXBERT_RXBERTCTRL_PKT_EN_ALIGN 0 37820 #define LNRXBERT_RXBERTCTRL_PKT_EN_BITS 1 37821 #define LNRXBERT_RXBERTCTRL_PKT_EN_SHIFT 15 37822 37823 /* LnRxBert :: rxBertCtrl :: seed_ld [14:14] */ 37824 #define LNRXBERT_RXBERTCTRL_SEED_LD_MASK 0x4000 37825 #define LNRXBERT_RXBERTCTRL_SEED_LD_ALIGN 0 37826 #define LNRXBERT_RXBERTCTRL_SEED_LD_BITS 1 37827 #define LNRXBERT_RXBERTCTRL_SEED_LD_SHIFT 14 37828 37829 /* LnRxBert :: rxBertCtrl :: prbs_order [13:12] */ 37830 #define LNRXBERT_RXBERTCTRL_PRBS_ORDER_MASK 0x3000 37831 #define LNRXBERT_RXBERTCTRL_PRBS_ORDER_ALIGN 0 37832 #define LNRXBERT_RXBERTCTRL_PRBS_ORDER_BITS 2 37833 #define LNRXBERT_RXBERTCTRL_PRBS_ORDER_SHIFT 12 37834 37835 /* LnRxBert :: rxBertCtrl :: ramp_en [11:11] */ 37836 #define LNRXBERT_RXBERTCTRL_RAMP_EN_MASK 0x0800 37837 #define LNRXBERT_RXBERTCTRL_RAMP_EN_ALIGN 0 37838 #define LNRXBERT_RXBERTCTRL_RAMP_EN_BITS 1 37839 #define LNRXBERT_RXBERTCTRL_RAMP_EN_SHIFT 11 37840 37841 /* LnRxBert :: rxBertCtrl :: cgbad_tst_en [10:10] */ 37842 #define LNRXBERT_RXBERTCTRL_CGBAD_TST_EN_MASK 0x0400 37843 #define LNRXBERT_RXBERTCTRL_CGBAD_TST_EN_ALIGN 0 37844 #define LNRXBERT_RXBERTCTRL_CGBAD_TST_EN_BITS 1 37845 #define LNRXBERT_RXBERTCTRL_CGBAD_TST_EN_SHIFT 10 37846 37847 /* LnRxBert :: rxBertCtrl :: crcChk_en [09:09] */ 37848 #define LNRXBERT_RXBERTCTRL_CRCCHK_EN_MASK 0x0200 37849 #define LNRXBERT_RXBERTCTRL_CRCCHK_EN_ALIGN 0 37850 #define LNRXBERT_RXBERTCTRL_CRCCHK_EN_BITS 1 37851 #define LNRXBERT_RXBERTCTRL_CRCCHK_EN_SHIFT 9 37852 37853 /* LnRxBert :: rxBertCtrl :: countRst_dis [08:08] */ 37854 #define LNRXBERT_RXBERTCTRL_COUNTRST_DIS_MASK 0x0100 37855 #define LNRXBERT_RXBERTCTRL_COUNTRST_DIS_ALIGN 0 37856 #define LNRXBERT_RXBERTCTRL_COUNTRST_DIS_BITS 1 37857 #define LNRXBERT_RXBERTCTRL_COUNTRST_DIS_SHIFT 8 37858 37859 /* LnRxBert :: rxBertCtrl :: rxStatSel [07:07] */ 37860 #define LNRXBERT_RXBERTCTRL_RXSTATSEL_MASK 0x0080 37861 #define LNRXBERT_RXBERTCTRL_RXSTATSEL_ALIGN 0 37862 #define LNRXBERT_RXBERTCTRL_RXSTATSEL_BITS 1 37863 #define LNRXBERT_RXBERTCTRL_RXSTATSEL_SHIFT 7 37864 37865 /* LnRxBert :: rxBertCtrl :: source_sel_r [06:06] */ 37866 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_R_MASK 0x0040 37867 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_R_ALIGN 0 37868 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_R_BITS 1 37869 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_R_SHIFT 6 37870 37871 /* LnRxBert :: rxBertCtrl :: source_sel [05:04] */ 37872 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_MASK 0x0030 37873 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_ALIGN 0 37874 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_BITS 2 37875 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_SHIFT 4 37876 37877 /* LnRxBert :: rxBertCtrl :: slice_sel [03:02] */ 37878 #define LNRXBERT_RXBERTCTRL_SLICE_SEL_MASK 0x000c 37879 #define LNRXBERT_RXBERTCTRL_SLICE_SEL_ALIGN 0 37880 #define LNRXBERT_RXBERTCTRL_SLICE_SEL_BITS 2 37881 #define LNRXBERT_RXBERTCTRL_SLICE_SEL_SHIFT 2 37882 37883 /* LnRxBert :: rxBertCtrl :: err_clr [01:01] */ 37884 #define LNRXBERT_RXBERTCTRL_ERR_CLR_MASK 0x0002 37885 #define LNRXBERT_RXBERTCTRL_ERR_CLR_ALIGN 0 37886 #define LNRXBERT_RXBERTCTRL_ERR_CLR_BITS 1 37887 #define LNRXBERT_RXBERTCTRL_ERR_CLR_SHIFT 1 37888 37889 /* LnRxBert :: rxBertCtrl :: count_clr [00:00] */ 37890 #define LNRXBERT_RXBERTCTRL_COUNT_CLR_MASK 0x0001 37891 #define LNRXBERT_RXBERTCTRL_COUNT_CLR_ALIGN 0 37892 #define LNRXBERT_RXBERTCTRL_COUNT_CLR_BITS 1 37893 #define LNRXBERT_RXBERTCTRL_COUNT_CLR_SHIFT 0 37894 37895 37896 /**************************************************************************** 37897 * LnRxBert :: rxBertSopEop 37898 */ 37899 /* LnRxBert :: rxBertSopEop :: SOP [15:08] */ 37900 #define LNRXBERT_RXBERTSOPEOP_SOP_MASK 0xff00 37901 #define LNRXBERT_RXBERTSOPEOP_SOP_ALIGN 0 37902 #define LNRXBERT_RXBERTSOPEOP_SOP_BITS 8 37903 #define LNRXBERT_RXBERTSOPEOP_SOP_SHIFT 8 37904 37905 /* LnRxBert :: rxBertSopEop :: EOP [07:00] */ 37906 #define LNRXBERT_RXBERTSOPEOP_EOP_MASK 0x00ff 37907 #define LNRXBERT_RXBERTSOPEOP_EOP_ALIGN 0 37908 #define LNRXBERT_RXBERTSOPEOP_EOP_BITS 8 37909 #define LNRXBERT_RXBERTSOPEOP_EOP_SHIFT 0 37910 37911 37912 /**************************************************************************** 37913 * LnRxBert :: rxBertByteU 37914 */ 37915 /* LnRxBert :: rxBertByteU :: byte_count_high [15:00] */ 37916 #define LNRXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_MASK 0xffff 37917 #define LNRXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN 0 37918 #define LNRXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_BITS 16 37919 #define LNRXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT 0 37920 37921 37922 /**************************************************************************** 37923 * LnRxBert :: rxBertByteL 37924 */ 37925 /* LnRxBert :: rxBertByteL :: byte_count_low [15:00] */ 37926 #define LNRXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_MASK 0xffff 37927 #define LNRXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_ALIGN 0 37928 #define LNRXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_BITS 16 37929 #define LNRXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_SHIFT 0 37930 37931 37932 /**************************************************************************** 37933 * LnRxBert :: rxBertPacketU 37934 */ 37935 /* LnRxBert :: rxBertPacketU :: pkt_count_high [15:00] */ 37936 #define LNRXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_MASK 0xffff 37937 #define LNRXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_ALIGN 0 37938 #define LNRXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_BITS 16 37939 #define LNRXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_SHIFT 0 37940 37941 37942 /**************************************************************************** 37943 * LnRxBert :: rxBertPacketL 37944 */ 37945 /* LnRxBert :: rxBertPacketL :: pkt_count_low [15:00] */ 37946 #define LNRXBERT_RXBERTPACKETL_PKT_COUNT_LOW_MASK 0xffff 37947 #define LNRXBERT_RXBERTPACKETL_PKT_COUNT_LOW_ALIGN 0 37948 #define LNRXBERT_RXBERTPACKETL_PKT_COUNT_LOW_BITS 16 37949 #define LNRXBERT_RXBERTPACKETL_PKT_COUNT_LOW_SHIFT 0 37950 37951 37952 /**************************************************************************** 37953 * LnRxBert :: rxBertBitErr 37954 */ 37955 /* LnRxBert :: rxBertBitErr :: bit_err_count [15:00] */ 37956 #define LNRXBERT_RXBERTBITERR_BIT_ERR_COUNT_MASK 0xffff 37957 #define LNRXBERT_RXBERTBITERR_BIT_ERR_COUNT_ALIGN 0 37958 #define LNRXBERT_RXBERTBITERR_BIT_ERR_COUNT_BITS 16 37959 #define LNRXBERT_RXBERTBITERR_BIT_ERR_COUNT_SHIFT 0 37960 37961 37962 /**************************************************************************** 37963 * LnRxBert :: rxBertByteErr 37964 */ 37965 /* LnRxBert :: rxBertByteErr :: byte_err_count [15:00] */ 37966 #define LNRXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_MASK 0xffff 37967 #define LNRXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_ALIGN 0 37968 #define LNRXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_BITS 16 37969 #define LNRXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_SHIFT 0 37970 37971 37972 /**************************************************************************** 37973 * LnRxBert :: rxBertPktErr 37974 */ 37975 /* LnRxBert :: rxBertPktErr :: pkt_err_count [15:00] */ 37976 #define LNRXBERT_RXBERTPKTERR_PKT_ERR_COUNT_MASK 0xffff 37977 #define LNRXBERT_RXBERTPKTERR_PKT_ERR_COUNT_ALIGN 0 37978 #define LNRXBERT_RXBERTPKTERR_PKT_ERR_COUNT_BITS 16 37979 #define LNRXBERT_RXBERTPKTERR_PKT_ERR_COUNT_SHIFT 0 37980 37981 37982 /**************************************************************************** 37983 * LnRxBert :: rxBertStatus 37984 */ 37985 /* union - case rxStatSel [15:00] */ 37986 /* LnRxBert :: rxBertStatus :: reserved0 [15:08] */ 37987 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_MASK 0xff00 37988 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_ALIGN 0 37989 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_BITS 8 37990 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_SHIFT 8 37991 37992 /* LnRxBert :: rxBertStatus :: rx_10g_tmux [07:00] */ 37993 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_MASK 0x00ff 37994 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_ALIGN 0 37995 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_BITS 8 37996 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_SHIFT 0 37997 37998 37999 /* union - case crcChk_en [15:00] */ 38000 /* LnRxBert :: rxBertStatus :: link [15:15] */ 38001 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_MASK 0x8000 38002 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_ALIGN 0 38003 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_BITS 1 38004 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_SHIFT 15 38005 38006 /* LnRxBert :: rxBertStatus :: prbs_stky [14:14] */ 38007 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_MASK 0x4000 38008 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_ALIGN 0 38009 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_BITS 1 38010 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_SHIFT 14 38011 38012 /* LnRxBert :: rxBertStatus :: reserved0 [13:00] */ 38013 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_MASK 0x3fff 38014 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_ALIGN 0 38015 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_BITS 14 38016 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_SHIFT 0 38017 38018 38019 /* union - case rxBert [15:00] */ 38020 /* LnRxBert :: rxBertStatus :: prbs_lock [15:15] */ 38021 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_MASK 0x8000 38022 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_ALIGN 0 38023 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_BITS 1 38024 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_SHIFT 15 38025 38026 /* LnRxBert :: rxBertStatus :: prbs_stky [14:14] */ 38027 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_MASK 0x4000 38028 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_ALIGN 0 38029 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_BITS 1 38030 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_SHIFT 14 38031 38032 /* LnRxBert :: rxBertStatus :: prbs_state [13:11] */ 38033 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_MASK 0x3800 38034 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_ALIGN 0 38035 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_BITS 3 38036 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_SHIFT 11 38037 38038 /* LnRxBert :: rxBertStatus :: reserved0 [10:07] */ 38039 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED0_MASK 0x0780 38040 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED0_ALIGN 0 38041 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED0_BITS 4 38042 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED0_SHIFT 7 38043 38044 /* LnRxBert :: rxBertStatus :: bit_err_overflow [06:06] */ 38045 #define LNRXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_MASK 0x0040 38046 #define LNRXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_ALIGN 0 38047 #define LNRXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_BITS 1 38048 #define LNRXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_SHIFT 6 38049 38050 /* LnRxBert :: rxBertStatus :: reserved1 [05:04] */ 38051 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED1_MASK 0x0030 38052 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED1_ALIGN 0 38053 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED1_BITS 2 38054 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED1_SHIFT 4 38055 38056 /* LnRxBert :: rxBertStatus :: onefe_det [03:03] */ 38057 #define LNRXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_MASK 0x0008 38058 #define LNRXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_ALIGN 0 38059 #define LNRXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_BITS 1 38060 #define LNRXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_SHIFT 3 38061 38062 /* LnRxBert :: rxBertStatus :: xor_comp [02:00] */ 38063 #define LNRXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_MASK 0x0007 38064 #define LNRXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_ALIGN 0 38065 #define LNRXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_BITS 3 38066 #define LNRXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_SHIFT 0 38067 38068 38069 38070 /**************************************************************************** 38071 * Warpcore_USER_FX100 38072 */ 38073 /**************************************************************************** 38074 * FX100 :: Control1 38075 */ 38076 /* FX100 :: Control1 :: data_sampler_en [15:15] */ 38077 #define FX100_CONTROL1_DATA_SAMPLER_EN_MASK 0x8000 38078 #define FX100_CONTROL1_DATA_SAMPLER_EN_ALIGN 0 38079 #define FX100_CONTROL1_DATA_SAMPLER_EN_BITS 1 38080 #define FX100_CONTROL1_DATA_SAMPLER_EN_SHIFT 15 38081 38082 /* FX100 :: Control1 :: reserved0 [14:10] */ 38083 #define FX100_CONTROL1_RESERVED0_MASK 0x7c00 38084 #define FX100_CONTROL1_RESERVED0_ALIGN 0 38085 #define FX100_CONTROL1_RESERVED0_BITS 5 38086 #define FX100_CONTROL1_RESERVED0_SHIFT 10 38087 38088 /* FX100 :: Control1 :: rxdata_sel [09:06] */ 38089 #define FX100_CONTROL1_RXDATA_SEL_MASK 0x03c0 38090 #define FX100_CONTROL1_RXDATA_SEL_ALIGN 0 38091 #define FX100_CONTROL1_RXDATA_SEL_BITS 4 38092 #define FX100_CONTROL1_RXDATA_SEL_SHIFT 6 38093 38094 /* FX100 :: Control1 :: disable_rx_qual [05:05] */ 38095 #define FX100_CONTROL1_DISABLE_RX_QUAL_MASK 0x0020 38096 #define FX100_CONTROL1_DISABLE_RX_QUAL_ALIGN 0 38097 #define FX100_CONTROL1_DISABLE_RX_QUAL_BITS 1 38098 #define FX100_CONTROL1_DISABLE_RX_QUAL_SHIFT 5 38099 38100 /* FX100 :: Control1 :: force_rx_qual [04:04] */ 38101 #define FX100_CONTROL1_FORCE_RX_QUAL_MASK 0x0010 38102 #define FX100_CONTROL1_FORCE_RX_QUAL_ALIGN 0 38103 #define FX100_CONTROL1_FORCE_RX_QUAL_BITS 1 38104 #define FX100_CONTROL1_FORCE_RX_QUAL_SHIFT 4 38105 38106 /* FX100 :: Control1 :: far_end_fault_en [03:03] */ 38107 #define FX100_CONTROL1_FAR_END_FAULT_EN_MASK 0x0008 38108 #define FX100_CONTROL1_FAR_END_FAULT_EN_ALIGN 0 38109 #define FX100_CONTROL1_FAR_END_FAULT_EN_BITS 1 38110 #define FX100_CONTROL1_FAR_END_FAULT_EN_SHIFT 3 38111 38112 /* FX100 :: Control1 :: auto_detect_fx_mode [02:02] */ 38113 #define FX100_CONTROL1_AUTO_DETECT_FX_MODE_MASK 0x0004 38114 #define FX100_CONTROL1_AUTO_DETECT_FX_MODE_ALIGN 0 38115 #define FX100_CONTROL1_AUTO_DETECT_FX_MODE_BITS 1 38116 #define FX100_CONTROL1_AUTO_DETECT_FX_MODE_SHIFT 2 38117 38118 /* FX100 :: Control1 :: full_duplex [01:01] */ 38119 #define FX100_CONTROL1_FULL_DUPLEX_MASK 0x0002 38120 #define FX100_CONTROL1_FULL_DUPLEX_ALIGN 0 38121 #define FX100_CONTROL1_FULL_DUPLEX_BITS 1 38122 #define FX100_CONTROL1_FULL_DUPLEX_SHIFT 1 38123 38124 /* FX100 :: Control1 :: enable [00:00] */ 38125 #define FX100_CONTROL1_ENABLE_MASK 0x0001 38126 #define FX100_CONTROL1_ENABLE_ALIGN 0 38127 #define FX100_CONTROL1_ENABLE_BITS 1 38128 #define FX100_CONTROL1_ENABLE_SHIFT 0 38129 38130 38131 /**************************************************************************** 38132 * FX100 :: Control2 38133 */ 38134 /* FX100 :: Control2 :: reserved0 [15:12] */ 38135 #define FX100_CONTROL2_RESERVED0_MASK 0xf000 38136 #define FX100_CONTROL2_RESERVED0_ALIGN 0 38137 #define FX100_CONTROL2_RESERVED0_BITS 4 38138 #define FX100_CONTROL2_RESERVED0_SHIFT 12 38139 38140 /* FX100 :: Control2 :: ping_pong_disable [11:11] */ 38141 #define FX100_CONTROL2_PING_PONG_DISABLE_MASK 0x0800 38142 #define FX100_CONTROL2_PING_PONG_DISABLE_ALIGN 0 38143 #define FX100_CONTROL2_PING_PONG_DISABLE_BITS 1 38144 #define FX100_CONTROL2_PING_PONG_DISABLE_SHIFT 11 38145 38146 /* FX100 :: Control2 :: pll_clk125_sw_ref [10:10] */ 38147 #define FX100_CONTROL2_PLL_CLK125_SW_REF_MASK 0x0400 38148 #define FX100_CONTROL2_PLL_CLK125_SW_REF_ALIGN 0 38149 #define FX100_CONTROL2_PLL_CLK125_SW_REF_BITS 1 38150 #define FX100_CONTROL2_PLL_CLK125_SW_REF_SHIFT 10 38151 38152 /* FX100 :: Control2 :: pll_clk125_sw_en [09:09] */ 38153 #define FX100_CONTROL2_PLL_CLK125_SW_EN_MASK 0x0200 38154 #define FX100_CONTROL2_PLL_CLK125_SW_EN_ALIGN 0 38155 #define FX100_CONTROL2_PLL_CLK125_SW_EN_BITS 1 38156 #define FX100_CONTROL2_PLL_CLK125_SW_EN_SHIFT 9 38157 38158 /* FX100 :: Control2 :: clk_out_1000_sw_def [08:08] */ 38159 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_MASK 0x0100 38160 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_ALIGN 0 38161 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_BITS 1 38162 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_SHIFT 8 38163 38164 /* FX100 :: Control2 :: clk_out_1000_sw_en [07:07] */ 38165 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_MASK 0x0080 38166 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_ALIGN 0 38167 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_BITS 1 38168 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_SHIFT 7 38169 38170 /* FX100 :: Control2 :: mii_rxc_out_sw_ref [06:06] */ 38171 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_MASK 0x0040 38172 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_ALIGN 0 38173 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_BITS 1 38174 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_SHIFT 6 38175 38176 /* FX100 :: Control2 :: mii_rxc_out_sw_en [05:05] */ 38177 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_MASK 0x0020 38178 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_ALIGN 0 38179 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_BITS 1 38180 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_SHIFT 5 38181 38182 /* FX100 :: Control2 :: mii_rxc_out_sm_rst [04:04] */ 38183 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_MASK 0x0010 38184 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_ALIGN 0 38185 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_BITS 1 38186 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_SHIFT 4 38187 38188 /* FX100 :: Control2 :: mode_chg_nrst [03:03] */ 38189 #define FX100_CONTROL2_MODE_CHG_NRST_MASK 0x0008 38190 #define FX100_CONTROL2_MODE_CHG_NRST_ALIGN 0 38191 #define FX100_CONTROL2_MODE_CHG_NRST_BITS 1 38192 #define FX100_CONTROL2_MODE_CHG_NRST_SHIFT 3 38193 38194 /* FX100 :: Control2 :: reset_rxfifo [02:02] */ 38195 #define FX100_CONTROL2_RESET_RXFIFO_MASK 0x0004 38196 #define FX100_CONTROL2_RESET_RXFIFO_ALIGN 0 38197 #define FX100_CONTROL2_RESET_RXFIFO_BITS 1 38198 #define FX100_CONTROL2_RESET_RXFIFO_SHIFT 2 38199 38200 /* FX100 :: Control2 :: bypass_rxfifo [01:01] */ 38201 #define FX100_CONTROL2_BYPASS_RXFIFO_MASK 0x0002 38202 #define FX100_CONTROL2_BYPASS_RXFIFO_ALIGN 0 38203 #define FX100_CONTROL2_BYPASS_RXFIFO_BITS 1 38204 #define FX100_CONTROL2_BYPASS_RXFIFO_SHIFT 1 38205 38206 /* FX100 :: Control2 :: extend_pkt_size [00:00] */ 38207 #define FX100_CONTROL2_EXTEND_PKT_SIZE_MASK 0x0001 38208 #define FX100_CONTROL2_EXTEND_PKT_SIZE_ALIGN 0 38209 #define FX100_CONTROL2_EXTEND_PKT_SIZE_BITS 1 38210 #define FX100_CONTROL2_EXTEND_PKT_SIZE_SHIFT 0 38211 38212 38213 /**************************************************************************** 38214 * FX100 :: Control3 38215 */ 38216 /* FX100 :: Control3 :: number_of_idle [15:08] */ 38217 #define FX100_CONTROL3_NUMBER_OF_IDLE_MASK 0xff00 38218 #define FX100_CONTROL3_NUMBER_OF_IDLE_ALIGN 0 38219 #define FX100_CONTROL3_NUMBER_OF_IDLE_BITS 8 38220 #define FX100_CONTROL3_NUMBER_OF_IDLE_SHIFT 8 38221 38222 /* FX100 :: Control3 :: correlator_disable [07:07] */ 38223 #define FX100_CONTROL3_CORRELATOR_DISABLE_MASK 0x0080 38224 #define FX100_CONTROL3_CORRELATOR_DISABLE_ALIGN 0 38225 #define FX100_CONTROL3_CORRELATOR_DISABLE_BITS 1 38226 #define FX100_CONTROL3_CORRELATOR_DISABLE_SHIFT 7 38227 38228 /* FX100 :: Control3 :: bypass_nrz [06:06] */ 38229 #define FX100_CONTROL3_BYPASS_NRZ_MASK 0x0040 38230 #define FX100_CONTROL3_BYPASS_NRZ_ALIGN 0 38231 #define FX100_CONTROL3_BYPASS_NRZ_BITS 1 38232 #define FX100_CONTROL3_BYPASS_NRZ_SHIFT 6 38233 38234 /* FX100 :: Control3 :: bypass_encoder [05:05] */ 38235 #define FX100_CONTROL3_BYPASS_ENCODER_MASK 0x0020 38236 #define FX100_CONTROL3_BYPASS_ENCODER_ALIGN 0 38237 #define FX100_CONTROL3_BYPASS_ENCODER_BITS 1 38238 #define FX100_CONTROL3_BYPASS_ENCODER_SHIFT 5 38239 38240 /* FX100 :: Control3 :: bypass_alignment [04:04] */ 38241 #define FX100_CONTROL3_BYPASS_ALIGNMENT_MASK 0x0010 38242 #define FX100_CONTROL3_BYPASS_ALIGNMENT_ALIGN 0 38243 #define FX100_CONTROL3_BYPASS_ALIGNMENT_BITS 1 38244 #define FX100_CONTROL3_BYPASS_ALIGNMENT_SHIFT 4 38245 38246 /* FX100 :: Control3 :: force_link [03:03] */ 38247 #define FX100_CONTROL3_FORCE_LINK_MASK 0x0008 38248 #define FX100_CONTROL3_FORCE_LINK_ALIGN 0 38249 #define FX100_CONTROL3_FORCE_LINK_BITS 1 38250 #define FX100_CONTROL3_FORCE_LINK_SHIFT 3 38251 38252 /* FX100 :: Control3 :: force_lock [02:02] */ 38253 #define FX100_CONTROL3_FORCE_LOCK_MASK 0x0004 38254 #define FX100_CONTROL3_FORCE_LOCK_ALIGN 0 38255 #define FX100_CONTROL3_FORCE_LOCK_BITS 1 38256 #define FX100_CONTROL3_FORCE_LOCK_SHIFT 2 38257 38258 /* FX100 :: Control3 :: fast_unlock_timer [01:01] */ 38259 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_MASK 0x0002 38260 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_ALIGN 0 38261 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_BITS 1 38262 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_SHIFT 1 38263 38264 /* FX100 :: Control3 :: fast_timers [00:00] */ 38265 #define FX100_CONTROL3_FAST_TIMERS_MASK 0x0001 38266 #define FX100_CONTROL3_FAST_TIMERS_ALIGN 0 38267 #define FX100_CONTROL3_FAST_TIMERS_BITS 1 38268 #define FX100_CONTROL3_FAST_TIMERS_SHIFT 0 38269 38270 38271 /**************************************************************************** 38272 * FX100 :: Status1 38273 */ 38274 /* FX100 :: Status1 :: mode_change [15:15] */ 38275 #define FX100_STATUS1_MODE_CHANGE_MASK 0x8000 38276 #define FX100_STATUS1_MODE_CHANGE_ALIGN 0 38277 #define FX100_STATUS1_MODE_CHANGE_BITS 1 38278 #define FX100_STATUS1_MODE_CHANGE_SHIFT 15 38279 38280 /* FX100 :: Status1 :: reserved0 [14:12] */ 38281 #define FX100_STATUS1_RESERVED0_MASK 0x7000 38282 #define FX100_STATUS1_RESERVED0_ALIGN 0 38283 #define FX100_STATUS1_RESERVED0_BITS 3 38284 #define FX100_STATUS1_RESERVED0_SHIFT 12 38285 38286 /* FX100 :: Status1 :: fiber_pwrdwn_status_chg [11:11] */ 38287 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_MASK 0x0800 38288 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_ALIGN 0 38289 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_BITS 1 38290 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_SHIFT 11 38291 38292 /* FX100 :: Status1 :: fiber_pwrdwn [10:10] */ 38293 #define FX100_STATUS1_FIBER_PWRDWN_MASK 0x0400 38294 #define FX100_STATUS1_FIBER_PWRDWN_ALIGN 0 38295 #define FX100_STATUS1_FIBER_PWRDWN_BITS 1 38296 #define FX100_STATUS1_FIBER_PWRDWN_SHIFT 10 38297 38298 /* FX100 :: Status1 :: link_status_chg [09:09] */ 38299 #define FX100_STATUS1_LINK_STATUS_CHG_MASK 0x0200 38300 #define FX100_STATUS1_LINK_STATUS_CHG_ALIGN 0 38301 #define FX100_STATUS1_LINK_STATUS_CHG_BITS 1 38302 #define FX100_STATUS1_LINK_STATUS_CHG_SHIFT 9 38303 38304 /* FX100 :: Status1 :: bad_esd_detected [08:08] */ 38305 #define FX100_STATUS1_BAD_ESD_DETECTED_MASK 0x0100 38306 #define FX100_STATUS1_BAD_ESD_DETECTED_ALIGN 0 38307 #define FX100_STATUS1_BAD_ESD_DETECTED_BITS 1 38308 #define FX100_STATUS1_BAD_ESD_DETECTED_SHIFT 8 38309 38310 /* FX100 :: Status1 :: false_carrier_detected [07:07] */ 38311 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_MASK 0x0080 38312 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_ALIGN 0 38313 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_BITS 1 38314 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_SHIFT 7 38315 38316 /* FX100 :: Status1 :: tx_err_detected [06:06] */ 38317 #define FX100_STATUS1_TX_ERR_DETECTED_MASK 0x0040 38318 #define FX100_STATUS1_TX_ERR_DETECTED_ALIGN 0 38319 #define FX100_STATUS1_TX_ERR_DETECTED_BITS 1 38320 #define FX100_STATUS1_TX_ERR_DETECTED_SHIFT 6 38321 38322 /* FX100 :: Status1 :: rx_err_detected [05:05] */ 38323 #define FX100_STATUS1_RX_ERR_DETECTED_MASK 0x0020 38324 #define FX100_STATUS1_RX_ERR_DETECTED_ALIGN 0 38325 #define FX100_STATUS1_RX_ERR_DETECTED_BITS 1 38326 #define FX100_STATUS1_RX_ERR_DETECTED_SHIFT 5 38327 38328 /* FX100 :: Status1 :: lock_timer_expired [04:04] */ 38329 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_MASK 0x0010 38330 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_ALIGN 0 38331 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_BITS 1 38332 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_SHIFT 4 38333 38334 /* FX100 :: Status1 :: lost_lock [03:03] */ 38335 #define FX100_STATUS1_LOST_LOCK_MASK 0x0008 38336 #define FX100_STATUS1_LOST_LOCK_ALIGN 0 38337 #define FX100_STATUS1_LOST_LOCK_BITS 1 38338 #define FX100_STATUS1_LOST_LOCK_SHIFT 3 38339 38340 /* FX100 :: Status1 :: faulting [02:02] */ 38341 #define FX100_STATUS1_FAULTING_MASK 0x0004 38342 #define FX100_STATUS1_FAULTING_ALIGN 0 38343 #define FX100_STATUS1_FAULTING_BITS 1 38344 #define FX100_STATUS1_FAULTING_SHIFT 2 38345 38346 /* FX100 :: Status1 :: locked [01:01] */ 38347 #define FX100_STATUS1_LOCKED_MASK 0x0002 38348 #define FX100_STATUS1_LOCKED_ALIGN 0 38349 #define FX100_STATUS1_LOCKED_BITS 1 38350 #define FX100_STATUS1_LOCKED_SHIFT 1 38351 38352 /* FX100 :: Status1 :: link [00:00] */ 38353 #define FX100_STATUS1_LINK_MASK 0x0001 38354 #define FX100_STATUS1_LINK_ALIGN 0 38355 #define FX100_STATUS1_LINK_BITS 1 38356 #define FX100_STATUS1_LINK_SHIFT 0 38357 38358 38359 /**************************************************************************** 38360 * FX100 :: Status3 38361 */ 38362 /* FX100 :: Status3 :: linkmon_cntr [15:08] */ 38363 #define FX100_STATUS3_LINKMON_CNTR_MASK 0xff00 38364 #define FX100_STATUS3_LINKMON_CNTR_ALIGN 0 38365 #define FX100_STATUS3_LINKMON_CNTR_BITS 8 38366 #define FX100_STATUS3_LINKMON_CNTR_SHIFT 8 38367 38368 /* FX100 :: Status3 :: reserved0 [07:07] */ 38369 #define FX100_STATUS3_RESERVED0_MASK 0x0080 38370 #define FX100_STATUS3_RESERVED0_ALIGN 0 38371 #define FX100_STATUS3_RESERVED0_BITS 1 38372 #define FX100_STATUS3_RESERVED0_SHIFT 7 38373 38374 /* FX100 :: Status3 :: idles_detected_5b [06:06] */ 38375 #define FX100_STATUS3_IDLES_DETECTED_5B_MASK 0x0040 38376 #define FX100_STATUS3_IDLES_DETECTED_5B_ALIGN 0 38377 #define FX100_STATUS3_IDLES_DETECTED_5B_BITS 1 38378 #define FX100_STATUS3_IDLES_DETECTED_5B_SHIFT 6 38379 38380 /* FX100 :: Status3 :: crs_ind_detected [05:05] */ 38381 #define FX100_STATUS3_CRS_IND_DETECTED_MASK 0x0020 38382 #define FX100_STATUS3_CRS_IND_DETECTED_ALIGN 0 38383 #define FX100_STATUS3_CRS_IND_DETECTED_BITS 1 38384 #define FX100_STATUS3_CRS_IND_DETECTED_SHIFT 5 38385 38386 /* FX100 :: Status3 :: err_detected [04:04] */ 38387 #define FX100_STATUS3_ERR_DETECTED_MASK 0x0010 38388 #define FX100_STATUS3_ERR_DETECTED_ALIGN 0 38389 #define FX100_STATUS3_ERR_DETECTED_BITS 1 38390 #define FX100_STATUS3_ERR_DETECTED_SHIFT 4 38391 38392 /* FX100 :: Status3 :: esd_detected [03:03] */ 38393 #define FX100_STATUS3_ESD_DETECTED_MASK 0x0008 38394 #define FX100_STATUS3_ESD_DETECTED_ALIGN 0 38395 #define FX100_STATUS3_ESD_DETECTED_BITS 1 38396 #define FX100_STATUS3_ESD_DETECTED_SHIFT 3 38397 38398 /* FX100 :: Status3 :: ssd_detected [02:02] */ 38399 #define FX100_STATUS3_SSD_DETECTED_MASK 0x0004 38400 #define FX100_STATUS3_SSD_DETECTED_ALIGN 0 38401 #define FX100_STATUS3_SSD_DETECTED_BITS 1 38402 #define FX100_STATUS3_SSD_DETECTED_SHIFT 2 38403 38404 /* FX100 :: Status3 :: ij_detected [01:01] */ 38405 #define FX100_STATUS3_IJ_DETECTED_MASK 0x0002 38406 #define FX100_STATUS3_IJ_DETECTED_ALIGN 0 38407 #define FX100_STATUS3_IJ_DETECTED_BITS 1 38408 #define FX100_STATUS3_IJ_DETECTED_SHIFT 1 38409 38410 /* FX100 :: Status3 :: idles_detected [00:00] */ 38411 #define FX100_STATUS3_IDLES_DETECTED_MASK 0x0001 38412 #define FX100_STATUS3_IDLES_DETECTED_ALIGN 0 38413 #define FX100_STATUS3_IDLES_DETECTED_BITS 1 38414 #define FX100_STATUS3_IDLES_DETECTED_SHIFT 0 38415 38416 38417 /**************************************************************************** 38418 * FX100 :: Status4 38419 */ 38420 /* FX100 :: Status4 :: reserved0 [15:15] */ 38421 #define FX100_STATUS4_RESERVED0_MASK 0x8000 38422 #define FX100_STATUS4_RESERVED0_ALIGN 0 38423 #define FX100_STATUS4_RESERVED0_BITS 1 38424 #define FX100_STATUS4_RESERVED0_SHIFT 15 38425 38426 /* FX100 :: Status4 :: rx_badend [14:14] */ 38427 #define FX100_STATUS4_RX_BADEND_MASK 0x4000 38428 #define FX100_STATUS4_RX_BADEND_ALIGN 0 38429 #define FX100_STATUS4_RX_BADEND_BITS 1 38430 #define FX100_STATUS4_RX_BADEND_SHIFT 14 38431 38432 /* FX100 :: Status4 :: rx_data [13:13] */ 38433 #define FX100_STATUS4_RX_DATA_MASK 0x2000 38434 #define FX100_STATUS4_RX_DATA_ALIGN 0 38435 #define FX100_STATUS4_RX_DATA_BITS 1 38436 #define FX100_STATUS4_RX_DATA_SHIFT 13 38437 38438 /* FX100 :: Status4 :: rx_ssk [12:12] */ 38439 #define FX100_STATUS4_RX_SSK_MASK 0x1000 38440 #define FX100_STATUS4_RX_SSK_ALIGN 0 38441 #define FX100_STATUS4_RX_SSK_BITS 1 38442 #define FX100_STATUS4_RX_SSK_SHIFT 12 38443 38444 /* FX100 :: Status4 :: rx_ssj [11:11] */ 38445 #define FX100_STATUS4_RX_SSJ_MASK 0x0800 38446 #define FX100_STATUS4_RX_SSJ_ALIGN 0 38447 #define FX100_STATUS4_RX_SSJ_BITS 1 38448 #define FX100_STATUS4_RX_SSJ_SHIFT 11 38449 38450 /* FX100 :: Status4 :: rx_confirmk [10:10] */ 38451 #define FX100_STATUS4_RX_CONFIRMK_MASK 0x0400 38452 #define FX100_STATUS4_RX_CONFIRMK_ALIGN 0 38453 #define FX100_STATUS4_RX_CONFIRMK_BITS 1 38454 #define FX100_STATUS4_RX_CONFIRMK_SHIFT 10 38455 38456 /* FX100 :: Status4 :: rx_badssd [09:09] */ 38457 #define FX100_STATUS4_RX_BADSSD_MASK 0x0200 38458 #define FX100_STATUS4_RX_BADSSD_ALIGN 0 38459 #define FX100_STATUS4_RX_BADSSD_BITS 1 38460 #define FX100_STATUS4_RX_BADSSD_SHIFT 9 38461 38462 /* FX100 :: Status4 :: fx_linkfail [08:08] */ 38463 #define FX100_STATUS4_FX_LINKFAIL_MASK 0x0100 38464 #define FX100_STATUS4_FX_LINKFAIL_ALIGN 0 38465 #define FX100_STATUS4_FX_LINKFAIL_BITS 1 38466 #define FX100_STATUS4_FX_LINKFAIL_SHIFT 8 38467 38468 /* FX100 :: Status4 :: tx_esr [07:07] */ 38469 #define FX100_STATUS4_TX_ESR_MASK 0x0080 38470 #define FX100_STATUS4_TX_ESR_ALIGN 0 38471 #define FX100_STATUS4_TX_ESR_BITS 1 38472 #define FX100_STATUS4_TX_ESR_SHIFT 7 38473 38474 /* FX100 :: Status4 :: tx_est [06:06] */ 38475 #define FX100_STATUS4_TX_EST_MASK 0x0040 38476 #define FX100_STATUS4_TX_EST_ALIGN 0 38477 #define FX100_STATUS4_TX_EST_BITS 1 38478 #define FX100_STATUS4_TX_EST_SHIFT 6 38479 38480 /* FX100 :: Status4 :: tx_terror [05:05] */ 38481 #define FX100_STATUS4_TX_TERROR_MASK 0x0020 38482 #define FX100_STATUS4_TX_TERROR_ALIGN 0 38483 #define FX100_STATUS4_TX_TERROR_BITS 1 38484 #define FX100_STATUS4_TX_TERROR_SHIFT 5 38485 38486 /* FX100 :: Status4 :: tx_tdata [04:04] */ 38487 #define FX100_STATUS4_TX_TDATA_MASK 0x0010 38488 #define FX100_STATUS4_TX_TDATA_ALIGN 0 38489 #define FX100_STATUS4_TX_TDATA_BITS 1 38490 #define FX100_STATUS4_TX_TDATA_SHIFT 4 38491 38492 /* FX100 :: Status4 :: tx_ssk [03:03] */ 38493 #define FX100_STATUS4_TX_SSK_MASK 0x0008 38494 #define FX100_STATUS4_TX_SSK_ALIGN 0 38495 #define FX100_STATUS4_TX_SSK_BITS 1 38496 #define FX100_STATUS4_TX_SSK_SHIFT 3 38497 38498 /* FX100 :: Status4 :: tx_sek [02:02] */ 38499 #define FX100_STATUS4_TX_SEK_MASK 0x0004 38500 #define FX100_STATUS4_TX_SEK_ALIGN 0 38501 #define FX100_STATUS4_TX_SEK_BITS 1 38502 #define FX100_STATUS4_TX_SEK_SHIFT 2 38503 38504 /* FX100 :: Status4 :: tx_ssj [01:01] */ 38505 #define FX100_STATUS4_TX_SSJ_MASK 0x0002 38506 #define FX100_STATUS4_TX_SSJ_ALIGN 0 38507 #define FX100_STATUS4_TX_SSJ_BITS 1 38508 #define FX100_STATUS4_TX_SSJ_SHIFT 1 38509 38510 /* FX100 :: Status4 :: tx_sej [00:00] */ 38511 #define FX100_STATUS4_TX_SEJ_MASK 0x0001 38512 #define FX100_STATUS4_TX_SEJ_ALIGN 0 38513 #define FX100_STATUS4_TX_SEJ_BITS 1 38514 #define FX100_STATUS4_TX_SEJ_SHIFT 0 38515 38516 38517 /**************************************************************************** 38518 * FX100 :: fx100Idle1 38519 */ 38520 /* FX100 :: fx100Idle1 :: reserved0 [15:10] */ 38521 #define FX100_FX100IDLE1_RESERVED0_MASK 0xfc00 38522 #define FX100_FX100IDLE1_RESERVED0_ALIGN 0 38523 #define FX100_FX100IDLE1_RESERVED0_BITS 6 38524 #define FX100_FX100IDLE1_RESERVED0_SHIFT 10 38525 38526 /* FX100 :: fx100Idle1 :: fx100_idle1 [09:00] */ 38527 #define FX100_FX100IDLE1_FX100_IDLE1_MASK 0x03ff 38528 #define FX100_FX100IDLE1_FX100_IDLE1_ALIGN 0 38529 #define FX100_FX100IDLE1_FX100_IDLE1_BITS 10 38530 #define FX100_FX100IDLE1_FX100_IDLE1_SHIFT 0 38531 38532 38533 /**************************************************************************** 38534 * FX100 :: fx100idle2 38535 */ 38536 /* FX100 :: fx100idle2 :: reserved0 [15:10] */ 38537 #define FX100_FX100IDLE2_RESERVED0_MASK 0xfc00 38538 #define FX100_FX100IDLE2_RESERVED0_ALIGN 0 38539 #define FX100_FX100IDLE2_RESERVED0_BITS 6 38540 #define FX100_FX100IDLE2_RESERVED0_SHIFT 10 38541 38542 /* FX100 :: fx100idle2 :: fx100_idle2 [09:00] */ 38543 #define FX100_FX100IDLE2_FX100_IDLE2_MASK 0x03ff 38544 #define FX100_FX100IDLE2_FX100_IDLE2_ALIGN 0 38545 #define FX100_FX100IDLE2_FX100_IDLE2_BITS 10 38546 #define FX100_FX100IDLE2_FX100_IDLE2_SHIFT 0 38547 38548 38549 /**************************************************************************** 38550 * FX100 :: fx100IdleStatus 38551 */ 38552 /* FX100 :: fx100IdleStatus :: reserved0 [15:07] */ 38553 #define FX100_FX100IDLESTATUS_RESERVED0_MASK 0xff80 38554 #define FX100_FX100IDLESTATUS_RESERVED0_ALIGN 0 38555 #define FX100_FX100IDLESTATUS_RESERVED0_BITS 9 38556 #define FX100_FX100IDLESTATUS_RESERVED0_SHIFT 7 38557 38558 /* FX100 :: fx100IdleStatus :: fx100_idleCorr_cnt [06:00] */ 38559 #define FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_MASK 0x007f 38560 #define FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_ALIGN 0 38561 #define FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_BITS 7 38562 #define FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_SHIFT 0 38563 38564 38565 /**************************************************************************** 38566 * FX100 :: fx100IdleThres 38567 */ 38568 /* FX100 :: fx100IdleThres :: reserved0 [15:14] */ 38569 #define FX100_FX100IDLETHRES_RESERVED0_MASK 0xc000 38570 #define FX100_FX100IDLETHRES_RESERVED0_ALIGN 0 38571 #define FX100_FX100IDLETHRES_RESERVED0_BITS 2 38572 #define FX100_FX100IDLETHRES_RESERVED0_SHIFT 14 38573 38574 /* FX100 :: fx100IdleThres :: fx100_idle_min_thres [13:07] */ 38575 #define FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_MASK 0x3f80 38576 #define FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_ALIGN 0 38577 #define FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_BITS 7 38578 #define FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_SHIFT 7 38579 38580 /* FX100 :: fx100IdleThres :: fx100_idle_max_thres [06:00] */ 38581 #define FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_MASK 0x007f 38582 #define FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_ALIGN 0 38583 #define FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_BITS 7 38584 #define FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_SHIFT 0 38585 38586 38587 /**************************************************************************** 38588 * FX100 :: fx100LockTmr 38589 */ 38590 /* FX100 :: fx100LockTmr :: fx100_lock_thres [15:12] */ 38591 #define FX100_FX100LOCKTMR_FX100_LOCK_THRES_MASK 0xf000 38592 #define FX100_FX100LOCKTMR_FX100_LOCK_THRES_ALIGN 0 38593 #define FX100_FX100LOCKTMR_FX100_LOCK_THRES_BITS 4 38594 #define FX100_FX100LOCKTMR_FX100_LOCK_THRES_SHIFT 12 38595 38596 /* FX100 :: fx100LockTmr :: fx100_unlock_thres [11:08] */ 38597 #define FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_MASK 0x0f00 38598 #define FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_ALIGN 0 38599 #define FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_BITS 4 38600 #define FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_SHIFT 8 38601 38602 /* FX100 :: fx100LockTmr :: fx100_lock_maxtime [07:00] */ 38603 #define FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_MASK 0x00ff 38604 #define FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_ALIGN 0 38605 #define FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_BITS 8 38606 #define FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_SHIFT 0 38607 38608 38609 /**************************************************************************** 38610 * FX100 :: fx100LinkTmr 38611 */ 38612 /* FX100 :: fx100LinkTmr :: fx100_linkup_count [15:08] */ 38613 #define FX100_FX100LINKTMR_FX100_LINKUP_COUNT_MASK 0xff00 38614 #define FX100_FX100LINKTMR_FX100_LINKUP_COUNT_ALIGN 0 38615 #define FX100_FX100LINKTMR_FX100_LINKUP_COUNT_BITS 8 38616 #define FX100_FX100LINKTMR_FX100_LINKUP_COUNT_SHIFT 8 38617 38618 /* FX100 :: fx100LinkTmr :: fx100_linkdn_count [07:00] */ 38619 #define FX100_FX100LINKTMR_FX100_LINKDN_COUNT_MASK 0x00ff 38620 #define FX100_FX100LINKTMR_FX100_LINKDN_COUNT_ALIGN 0 38621 #define FX100_FX100LINKTMR_FX100_LINKDN_COUNT_BITS 8 38622 #define FX100_FX100LINKTMR_FX100_LINKDN_COUNT_SHIFT 0 38623 38624 38625 /**************************************************************************** 38626 * Warpcore_USER_EEE_TimerB0 38627 */ 38628 /**************************************************************************** 38629 * EEE_TimerB0 :: grp1_tx_refresh_timer 38630 */ 38631 /* EEE_TimerB0 :: grp1_tx_refresh_timer :: grp1_tx_tr_cnt_mdio [15:00] */ 38632 #define EEE_TIMERB0_GRP1_TX_REFRESH_TIMER_GRP1_TX_TR_CNT_MDIO_MASK 0xffff 38633 #define EEE_TIMERB0_GRP1_TX_REFRESH_TIMER_GRP1_TX_TR_CNT_MDIO_ALIGN 0 38634 #define EEE_TIMERB0_GRP1_TX_REFRESH_TIMER_GRP1_TX_TR_CNT_MDIO_BITS 16 38635 #define EEE_TIMERB0_GRP1_TX_REFRESH_TIMER_GRP1_TX_TR_CNT_MDIO_SHIFT 0 38636 38637 38638 /**************************************************************************** 38639 * EEE_TimerB0 :: grp1_tx_quiet_timer 38640 */ 38641 /* EEE_TimerB0 :: grp1_tx_quiet_timer :: grp1_tx_tq_cnt_mdio [15:00] */ 38642 #define EEE_TIMERB0_GRP1_TX_QUIET_TIMER_GRP1_TX_TQ_CNT_MDIO_MASK 0xffff 38643 #define EEE_TIMERB0_GRP1_TX_QUIET_TIMER_GRP1_TX_TQ_CNT_MDIO_ALIGN 0 38644 #define EEE_TIMERB0_GRP1_TX_QUIET_TIMER_GRP1_TX_TQ_CNT_MDIO_BITS 16 38645 #define EEE_TIMERB0_GRP1_TX_QUIET_TIMER_GRP1_TX_TQ_CNT_MDIO_SHIFT 0 38646 38647 38648 /**************************************************************************** 38649 * EEE_TimerB0 :: grp1_rx_wake_timer 38650 */ 38651 /* EEE_TimerB0 :: grp1_rx_wake_timer :: grp1_rx_tw_cnt_mdio [15:00] */ 38652 #define EEE_TIMERB0_GRP1_RX_WAKE_TIMER_GRP1_RX_TW_CNT_MDIO_MASK 0xffff 38653 #define EEE_TIMERB0_GRP1_RX_WAKE_TIMER_GRP1_RX_TW_CNT_MDIO_ALIGN 0 38654 #define EEE_TIMERB0_GRP1_RX_WAKE_TIMER_GRP1_RX_TW_CNT_MDIO_BITS 16 38655 #define EEE_TIMERB0_GRP1_RX_WAKE_TIMER_GRP1_RX_TW_CNT_MDIO_SHIFT 0 38656 38657 38658 /**************************************************************************** 38659 * EEE_TimerB0 :: grp2_tx_refresh_timer 38660 */ 38661 /* EEE_TimerB0 :: grp2_tx_refresh_timer :: grp2_tx_tr_cnt_mdio [15:00] */ 38662 #define EEE_TIMERB0_GRP2_TX_REFRESH_TIMER_GRP2_TX_TR_CNT_MDIO_MASK 0xffff 38663 #define EEE_TIMERB0_GRP2_TX_REFRESH_TIMER_GRP2_TX_TR_CNT_MDIO_ALIGN 0 38664 #define EEE_TIMERB0_GRP2_TX_REFRESH_TIMER_GRP2_TX_TR_CNT_MDIO_BITS 16 38665 #define EEE_TIMERB0_GRP2_TX_REFRESH_TIMER_GRP2_TX_TR_CNT_MDIO_SHIFT 0 38666 38667 38668 /**************************************************************************** 38669 * EEE_TimerB0 :: grp2_tx_quiet_timer 38670 */ 38671 /* EEE_TimerB0 :: grp2_tx_quiet_timer :: grp2_tx_tq_cnt_mdio [15:00] */ 38672 #define EEE_TIMERB0_GRP2_TX_QUIET_TIMER_GRP2_TX_TQ_CNT_MDIO_MASK 0xffff 38673 #define EEE_TIMERB0_GRP2_TX_QUIET_TIMER_GRP2_TX_TQ_CNT_MDIO_ALIGN 0 38674 #define EEE_TIMERB0_GRP2_TX_QUIET_TIMER_GRP2_TX_TQ_CNT_MDIO_BITS 16 38675 #define EEE_TIMERB0_GRP2_TX_QUIET_TIMER_GRP2_TX_TQ_CNT_MDIO_SHIFT 0 38676 38677 38678 /**************************************************************************** 38679 * EEE_TimerB0 :: grp2_rx_wake_timer 38680 */ 38681 /* EEE_TimerB0 :: grp2_rx_wake_timer :: grp2_rx_tw_cnt_mdio [15:00] */ 38682 #define EEE_TIMERB0_GRP2_RX_WAKE_TIMER_GRP2_RX_TW_CNT_MDIO_MASK 0xffff 38683 #define EEE_TIMERB0_GRP2_RX_WAKE_TIMER_GRP2_RX_TW_CNT_MDIO_ALIGN 0 38684 #define EEE_TIMERB0_GRP2_RX_WAKE_TIMER_GRP2_RX_TW_CNT_MDIO_BITS 16 38685 #define EEE_TIMERB0_GRP2_RX_WAKE_TIMER_GRP2_RX_TW_CNT_MDIO_SHIFT 0 38686 38687 38688 /**************************************************************************** 38689 * EEE_TimerB0 :: grp3_tx_refresh_timer 38690 */ 38691 /* EEE_TimerB0 :: grp3_tx_refresh_timer :: grp3_tx_tr_cnt_mdio [15:00] */ 38692 #define EEE_TIMERB0_GRP3_TX_REFRESH_TIMER_GRP3_TX_TR_CNT_MDIO_MASK 0xffff 38693 #define EEE_TIMERB0_GRP3_TX_REFRESH_TIMER_GRP3_TX_TR_CNT_MDIO_ALIGN 0 38694 #define EEE_TIMERB0_GRP3_TX_REFRESH_TIMER_GRP3_TX_TR_CNT_MDIO_BITS 16 38695 #define EEE_TIMERB0_GRP3_TX_REFRESH_TIMER_GRP3_TX_TR_CNT_MDIO_SHIFT 0 38696 38697 38698 /**************************************************************************** 38699 * EEE_TimerB0 :: grp3_tx_quiet_timer 38700 */ 38701 /* EEE_TimerB0 :: grp3_tx_quiet_timer :: grp3_tx_tq_cnt_mdio [15:00] */ 38702 #define EEE_TIMERB0_GRP3_TX_QUIET_TIMER_GRP3_TX_TQ_CNT_MDIO_MASK 0xffff 38703 #define EEE_TIMERB0_GRP3_TX_QUIET_TIMER_GRP3_TX_TQ_CNT_MDIO_ALIGN 0 38704 #define EEE_TIMERB0_GRP3_TX_QUIET_TIMER_GRP3_TX_TQ_CNT_MDIO_BITS 16 38705 #define EEE_TIMERB0_GRP3_TX_QUIET_TIMER_GRP3_TX_TQ_CNT_MDIO_SHIFT 0 38706 38707 38708 /**************************************************************************** 38709 * EEE_TimerB0 :: grp3_rx_wake_timer 38710 */ 38711 /* EEE_TimerB0 :: grp3_rx_wake_timer :: grp3_rx_tw_cnt_mdio [15:00] */ 38712 #define EEE_TIMERB0_GRP3_RX_WAKE_TIMER_GRP3_RX_TW_CNT_MDIO_MASK 0xffff 38713 #define EEE_TIMERB0_GRP3_RX_WAKE_TIMER_GRP3_RX_TW_CNT_MDIO_ALIGN 0 38714 #define EEE_TIMERB0_GRP3_RX_WAKE_TIMER_GRP3_RX_TW_CNT_MDIO_BITS 16 38715 #define EEE_TIMERB0_GRP3_RX_WAKE_TIMER_GRP3_RX_TW_CNT_MDIO_SHIFT 0 38716 38717 38718 /**************************************************************************** 38719 * EEE_TimerB0 :: grp4_tx_refresh_timer 38720 */ 38721 /* EEE_TimerB0 :: grp4_tx_refresh_timer :: grp4_tx_tr_cnt_mdio [15:00] */ 38722 #define EEE_TIMERB0_GRP4_TX_REFRESH_TIMER_GRP4_TX_TR_CNT_MDIO_MASK 0xffff 38723 #define EEE_TIMERB0_GRP4_TX_REFRESH_TIMER_GRP4_TX_TR_CNT_MDIO_ALIGN 0 38724 #define EEE_TIMERB0_GRP4_TX_REFRESH_TIMER_GRP4_TX_TR_CNT_MDIO_BITS 16 38725 #define EEE_TIMERB0_GRP4_TX_REFRESH_TIMER_GRP4_TX_TR_CNT_MDIO_SHIFT 0 38726 38727 38728 /**************************************************************************** 38729 * EEE_TimerB0 :: grp4_tx_quiet_timer 38730 */ 38731 /* EEE_TimerB0 :: grp4_tx_quiet_timer :: grp4_tx_tq_cnt_mdio [15:00] */ 38732 #define EEE_TIMERB0_GRP4_TX_QUIET_TIMER_GRP4_TX_TQ_CNT_MDIO_MASK 0xffff 38733 #define EEE_TIMERB0_GRP4_TX_QUIET_TIMER_GRP4_TX_TQ_CNT_MDIO_ALIGN 0 38734 #define EEE_TIMERB0_GRP4_TX_QUIET_TIMER_GRP4_TX_TQ_CNT_MDIO_BITS 16 38735 #define EEE_TIMERB0_GRP4_TX_QUIET_TIMER_GRP4_TX_TQ_CNT_MDIO_SHIFT 0 38736 38737 38738 /**************************************************************************** 38739 * EEE_TimerB0 :: grp4_rx_wake_timer 38740 */ 38741 /* EEE_TimerB0 :: grp4_rx_wake_timer :: grp4_rx_tw_cnt_mdio [15:00] */ 38742 #define EEE_TIMERB0_GRP4_RX_WAKE_TIMER_GRP4_RX_TW_CNT_MDIO_MASK 0xffff 38743 #define EEE_TIMERB0_GRP4_RX_WAKE_TIMER_GRP4_RX_TW_CNT_MDIO_ALIGN 0 38744 #define EEE_TIMERB0_GRP4_RX_WAKE_TIMER_GRP4_RX_TW_CNT_MDIO_BITS 16 38745 #define EEE_TIMERB0_GRP4_RX_WAKE_TIMER_GRP4_RX_TW_CNT_MDIO_SHIFT 0 38746 38747 38748 /**************************************************************************** 38749 * EEE_TimerB0 :: grp5_tx_refresh_timer 38750 */ 38751 /* EEE_TimerB0 :: grp5_tx_refresh_timer :: grp5_tx_tr_cnt_mdio [15:00] */ 38752 #define EEE_TIMERB0_GRP5_TX_REFRESH_TIMER_GRP5_TX_TR_CNT_MDIO_MASK 0xffff 38753 #define EEE_TIMERB0_GRP5_TX_REFRESH_TIMER_GRP5_TX_TR_CNT_MDIO_ALIGN 0 38754 #define EEE_TIMERB0_GRP5_TX_REFRESH_TIMER_GRP5_TX_TR_CNT_MDIO_BITS 16 38755 #define EEE_TIMERB0_GRP5_TX_REFRESH_TIMER_GRP5_TX_TR_CNT_MDIO_SHIFT 0 38756 38757 38758 /**************************************************************************** 38759 * EEE_TimerB0 :: grp5_tx_quiet_timer 38760 */ 38761 /* EEE_TimerB0 :: grp5_tx_quiet_timer :: grp5_tx_tq_cnt_mdio [15:00] */ 38762 #define EEE_TIMERB0_GRP5_TX_QUIET_TIMER_GRP5_TX_TQ_CNT_MDIO_MASK 0xffff 38763 #define EEE_TIMERB0_GRP5_TX_QUIET_TIMER_GRP5_TX_TQ_CNT_MDIO_ALIGN 0 38764 #define EEE_TIMERB0_GRP5_TX_QUIET_TIMER_GRP5_TX_TQ_CNT_MDIO_BITS 16 38765 #define EEE_TIMERB0_GRP5_TX_QUIET_TIMER_GRP5_TX_TQ_CNT_MDIO_SHIFT 0 38766 38767 38768 /**************************************************************************** 38769 * EEE_TimerB0 :: grp5_rx_wake_timer 38770 */ 38771 /* EEE_TimerB0 :: grp5_rx_wake_timer :: grp5_rx_tw_cnt_mdio [15:00] */ 38772 #define EEE_TIMERB0_GRP5_RX_WAKE_TIMER_GRP5_RX_TW_CNT_MDIO_MASK 0xffff 38773 #define EEE_TIMERB0_GRP5_RX_WAKE_TIMER_GRP5_RX_TW_CNT_MDIO_ALIGN 0 38774 #define EEE_TIMERB0_GRP5_RX_WAKE_TIMER_GRP5_RX_TW_CNT_MDIO_BITS 16 38775 #define EEE_TIMERB0_GRP5_RX_WAKE_TIMER_GRP5_RX_TW_CNT_MDIO_SHIFT 0 38776 38777 38778 /**************************************************************************** 38779 * Warpcore_USER_CL82_UserB0 38780 */ 38781 /**************************************************************************** 38782 * CL82_UserB0 :: tx_control_1 38783 */ 38784 /* CL82_UserB0 :: tx_control_1 :: reserved0 [15:10] */ 38785 #define CL82_USERB0_TX_CONTROL_1_RESERVED0_MASK 0xfc00 38786 #define CL82_USERB0_TX_CONTROL_1_RESERVED0_ALIGN 0 38787 #define CL82_USERB0_TX_CONTROL_1_RESERVED0_BITS 6 38788 #define CL82_USERB0_TX_CONTROL_1_RESERVED0_SHIFT 10 38789 38790 /* CL82_UserB0 :: tx_control_1 :: bypass_cl82txsm [09:09] */ 38791 #define CL82_USERB0_TX_CONTROL_1_BYPASS_CL82TXSM_MASK 0x0200 38792 #define CL82_USERB0_TX_CONTROL_1_BYPASS_CL82TXSM_ALIGN 0 38793 #define CL82_USERB0_TX_CONTROL_1_BYPASS_CL82TXSM_BITS 1 38794 #define CL82_USERB0_TX_CONTROL_1_BYPASS_CL82TXSM_SHIFT 9 38795 38796 /* CL82_UserB0 :: tx_control_1 :: cl82_20g_en_val [08:08] */ 38797 #define CL82_USERB0_TX_CONTROL_1_CL82_20G_EN_VAL_MASK 0x0100 38798 #define CL82_USERB0_TX_CONTROL_1_CL82_20G_EN_VAL_ALIGN 0 38799 #define CL82_USERB0_TX_CONTROL_1_CL82_20G_EN_VAL_BITS 1 38800 #define CL82_USERB0_TX_CONTROL_1_CL82_20G_EN_VAL_SHIFT 8 38801 38802 /* CL82_UserB0 :: tx_control_1 :: cl82_20g_en_override [07:07] */ 38803 #define CL82_USERB0_TX_CONTROL_1_CL82_20G_EN_OVERRIDE_MASK 0x0080 38804 #define CL82_USERB0_TX_CONTROL_1_CL82_20G_EN_OVERRIDE_ALIGN 0 38805 #define CL82_USERB0_TX_CONTROL_1_CL82_20G_EN_OVERRIDE_BITS 1 38806 #define CL82_USERB0_TX_CONTROL_1_CL82_20G_EN_OVERRIDE_SHIFT 7 38807 38808 /* CL82_UserB0 :: tx_control_1 :: scr_bypass [06:06] */ 38809 #define CL82_USERB0_TX_CONTROL_1_SCR_BYPASS_MASK 0x0040 38810 #define CL82_USERB0_TX_CONTROL_1_SCR_BYPASS_ALIGN 0 38811 #define CL82_USERB0_TX_CONTROL_1_SCR_BYPASS_BITS 1 38812 #define CL82_USERB0_TX_CONTROL_1_SCR_BYPASS_SHIFT 6 38813 38814 /* CL82_UserB0 :: tx_control_1 :: am_timer_init_val_tx_HI [05:03] */ 38815 #define CL82_USERB0_TX_CONTROL_1_AM_TIMER_INIT_VAL_TX_HI_MASK 0x0038 38816 #define CL82_USERB0_TX_CONTROL_1_AM_TIMER_INIT_VAL_TX_HI_ALIGN 0 38817 #define CL82_USERB0_TX_CONTROL_1_AM_TIMER_INIT_VAL_TX_HI_BITS 3 38818 #define CL82_USERB0_TX_CONTROL_1_AM_TIMER_INIT_VAL_TX_HI_SHIFT 3 38819 38820 /* CL82_UserB0 :: tx_control_1 :: ctrl_100G_en [02:02] */ 38821 #define CL82_USERB0_TX_CONTROL_1_CTRL_100G_EN_MASK 0x0004 38822 #define CL82_USERB0_TX_CONTROL_1_CTRL_100G_EN_ALIGN 0 38823 #define CL82_USERB0_TX_CONTROL_1_CTRL_100G_EN_BITS 1 38824 #define CL82_USERB0_TX_CONTROL_1_CTRL_100G_EN_SHIFT 2 38825 38826 /* CL82_UserB0 :: tx_control_1 :: cl82_en_val [01:01] */ 38827 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_VAL_MASK 0x0002 38828 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_VAL_ALIGN 0 38829 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_VAL_BITS 1 38830 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_VAL_SHIFT 1 38831 38832 /* CL82_UserB0 :: tx_control_1 :: cl82_en_override [00:00] */ 38833 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_OVERRIDE_MASK 0x0001 38834 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_OVERRIDE_ALIGN 0 38835 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_OVERRIDE_BITS 1 38836 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_OVERRIDE_SHIFT 0 38837 38838 38839 /**************************************************************************** 38840 * CL82_UserB0 :: tx_control_2 38841 */ 38842 /* CL82_UserB0 :: tx_control_2 :: am_timer_init_val_tx_LO [15:00] */ 38843 #define CL82_USERB0_TX_CONTROL_2_AM_TIMER_INIT_VAL_TX_LO_MASK 0xffff 38844 #define CL82_USERB0_TX_CONTROL_2_AM_TIMER_INIT_VAL_TX_LO_ALIGN 0 38845 #define CL82_USERB0_TX_CONTROL_2_AM_TIMER_INIT_VAL_TX_LO_BITS 16 38846 #define CL82_USERB0_TX_CONTROL_2_AM_TIMER_INIT_VAL_TX_LO_SHIFT 0 38847 38848 38849 /**************************************************************************** 38850 * CL82_UserB0 :: tx_status_1 38851 */ 38852 /* CL82_UserB0 :: tx_status_1 :: reserved0 [15:13] */ 38853 #define CL82_USERB0_TX_STATUS_1_RESERVED0_MASK 0xe000 38854 #define CL82_USERB0_TX_STATUS_1_RESERVED0_ALIGN 0 38855 #define CL82_USERB0_TX_STATUS_1_RESERVED0_BITS 3 38856 #define CL82_USERB0_TX_STATUS_1_RESERVED0_SHIFT 13 38857 38858 /* CL82_UserB0 :: tx_status_1 :: t_type_coded [12:10] */ 38859 #define CL82_USERB0_TX_STATUS_1_T_TYPE_CODED_MASK 0x1c00 38860 #define CL82_USERB0_TX_STATUS_1_T_TYPE_CODED_ALIGN 0 38861 #define CL82_USERB0_TX_STATUS_1_T_TYPE_CODED_BITS 3 38862 #define CL82_USERB0_TX_STATUS_1_T_TYPE_CODED_SHIFT 10 38863 38864 /* CL82_UserB0 :: tx_status_1 :: ltxsm_state [09:03] */ 38865 #define CL82_USERB0_TX_STATUS_1_LTXSM_STATE_MASK 0x03f8 38866 #define CL82_USERB0_TX_STATUS_1_LTXSM_STATE_ALIGN 0 38867 #define CL82_USERB0_TX_STATUS_1_LTXSM_STATE_BITS 7 38868 #define CL82_USERB0_TX_STATUS_1_LTXSM_STATE_SHIFT 3 38869 38870 /* CL82_UserB0 :: tx_status_1 :: txsm_state [02:00] */ 38871 #define CL82_USERB0_TX_STATUS_1_TXSM_STATE_MASK 0x0007 38872 #define CL82_USERB0_TX_STATUS_1_TXSM_STATE_ALIGN 0 38873 #define CL82_USERB0_TX_STATUS_1_TXSM_STATE_BITS 3 38874 #define CL82_USERB0_TX_STATUS_1_TXSM_STATE_SHIFT 0 38875 38876 38877 /**************************************************************************** 38878 * CL82_UserB0 :: tx_status_2 38879 */ 38880 /* CL82_UserB0 :: tx_status_2 :: reserved0 [15:02] */ 38881 #define CL82_USERB0_TX_STATUS_2_RESERVED0_MASK 0xfffc 38882 #define CL82_USERB0_TX_STATUS_2_RESERVED0_ALIGN 0 38883 #define CL82_USERB0_TX_STATUS_2_RESERVED0_BITS 14 38884 #define CL82_USERB0_TX_STATUS_2_RESERVED0_SHIFT 2 38885 38886 /* CL82_UserB0 :: tx_status_2 :: tx_cl82_fptr_err_latch [01:01] */ 38887 #define CL82_USERB0_TX_STATUS_2_TX_CL82_FPTR_ERR_LATCH_MASK 0x0002 38888 #define CL82_USERB0_TX_STATUS_2_TX_CL82_FPTR_ERR_LATCH_ALIGN 0 38889 #define CL82_USERB0_TX_STATUS_2_TX_CL82_FPTR_ERR_LATCH_BITS 1 38890 #define CL82_USERB0_TX_STATUS_2_TX_CL82_FPTR_ERR_LATCH_SHIFT 1 38891 38892 /* CL82_UserB0 :: tx_status_2 :: PCS_lane_num_not_synced_err_latch [00:00] */ 38893 #define CL82_USERB0_TX_STATUS_2_PCS_LANE_NUM_NOT_SYNCED_ERR_LATCH_MASK 0x0001 38894 #define CL82_USERB0_TX_STATUS_2_PCS_LANE_NUM_NOT_SYNCED_ERR_LATCH_ALIGN 0 38895 #define CL82_USERB0_TX_STATUS_2_PCS_LANE_NUM_NOT_SYNCED_ERR_LATCH_BITS 1 38896 #define CL82_USERB0_TX_STATUS_2_PCS_LANE_NUM_NOT_SYNCED_ERR_LATCH_SHIFT 0 38897 38898 38899 /**************************************************************************** 38900 * CL82_UserB0 :: rx_status_1 38901 */ 38902 /* CL82_UserB0 :: rx_status_1 :: mode_strap [15:15] */ 38903 #define CL82_USERB0_RX_STATUS_1_MODE_STRAP_MASK 0x8000 38904 #define CL82_USERB0_RX_STATUS_1_MODE_STRAP_ALIGN 0 38905 #define CL82_USERB0_RX_STATUS_1_MODE_STRAP_BITS 1 38906 #define CL82_USERB0_RX_STATUS_1_MODE_STRAP_SHIFT 15 38907 38908 /* CL82_UserB0 :: rx_status_1 :: reserved0 [14:13] */ 38909 #define CL82_USERB0_RX_STATUS_1_RESERVED0_MASK 0x6000 38910 #define CL82_USERB0_RX_STATUS_1_RESERVED0_ALIGN 0 38911 #define CL82_USERB0_RX_STATUS_1_RESERVED0_BITS 2 38912 #define CL82_USERB0_RX_STATUS_1_RESERVED0_SHIFT 13 38913 38914 /* CL82_UserB0 :: rx_status_1 :: r_type_coded [12:10] */ 38915 #define CL82_USERB0_RX_STATUS_1_R_TYPE_CODED_MASK 0x1c00 38916 #define CL82_USERB0_RX_STATUS_1_R_TYPE_CODED_ALIGN 0 38917 #define CL82_USERB0_RX_STATUS_1_R_TYPE_CODED_BITS 3 38918 #define CL82_USERB0_RX_STATUS_1_R_TYPE_CODED_SHIFT 10 38919 38920 /* CL82_UserB0 :: rx_status_1 :: lrxsm_state [09:03] */ 38921 #define CL82_USERB0_RX_STATUS_1_LRXSM_STATE_MASK 0x03f8 38922 #define CL82_USERB0_RX_STATUS_1_LRXSM_STATE_ALIGN 0 38923 #define CL82_USERB0_RX_STATUS_1_LRXSM_STATE_BITS 7 38924 #define CL82_USERB0_RX_STATUS_1_LRXSM_STATE_SHIFT 3 38925 38926 /* CL82_UserB0 :: rx_status_1 :: rxsm_state [02:00] */ 38927 #define CL82_USERB0_RX_STATUS_1_RXSM_STATE_MASK 0x0007 38928 #define CL82_USERB0_RX_STATUS_1_RXSM_STATE_ALIGN 0 38929 #define CL82_USERB0_RX_STATUS_1_RXSM_STATE_BITS 3 38930 #define CL82_USERB0_RX_STATUS_1_RXSM_STATE_SHIFT 0 38931 38932 38933 /**************************************************************************** 38934 * CL82_UserB0 :: rx_status_2 38935 */ 38936 /* CL82_UserB0 :: rx_status_2 :: pseudo_lock [15:15] */ 38937 #define CL82_USERB0_RX_STATUS_2_PSEUDO_LOCK_MASK 0x8000 38938 #define CL82_USERB0_RX_STATUS_2_PSEUDO_LOCK_ALIGN 0 38939 #define CL82_USERB0_RX_STATUS_2_PSEUDO_LOCK_BITS 1 38940 #define CL82_USERB0_RX_STATUS_2_PSEUDO_LOCK_SHIFT 15 38941 38942 /* CL82_UserB0 :: rx_status_2 :: deskew_state [14:14] */ 38943 #define CL82_USERB0_RX_STATUS_2_DESKEW_STATE_MASK 0x4000 38944 #define CL82_USERB0_RX_STATUS_2_DESKEW_STATE_ALIGN 0 38945 #define CL82_USERB0_RX_STATUS_2_DESKEW_STATE_BITS 1 38946 #define CL82_USERB0_RX_STATUS_2_DESKEW_STATE_SHIFT 14 38947 38948 /* CL82_UserB0 :: rx_status_2 :: deskew_his_state [13:12] */ 38949 #define CL82_USERB0_RX_STATUS_2_DESKEW_HIS_STATE_MASK 0x3000 38950 #define CL82_USERB0_RX_STATUS_2_DESKEW_HIS_STATE_ALIGN 0 38951 #define CL82_USERB0_RX_STATUS_2_DESKEW_HIS_STATE_BITS 2 38952 #define CL82_USERB0_RX_STATUS_2_DESKEW_HIS_STATE_SHIFT 12 38953 38954 /* CL82_UserB0 :: rx_status_2 :: lbermon_state [11:06] */ 38955 #define CL82_USERB0_RX_STATUS_2_LBERMON_STATE_MASK 0x0fc0 38956 #define CL82_USERB0_RX_STATUS_2_LBERMON_STATE_ALIGN 0 38957 #define CL82_USERB0_RX_STATUS_2_LBERMON_STATE_BITS 6 38958 #define CL82_USERB0_RX_STATUS_2_LBERMON_STATE_SHIFT 6 38959 38960 /* CL82_UserB0 :: rx_status_2 :: bermon_state [05:00] */ 38961 #define CL82_USERB0_RX_STATUS_2_BERMON_STATE_MASK 0x003f 38962 #define CL82_USERB0_RX_STATUS_2_BERMON_STATE_ALIGN 0 38963 #define CL82_USERB0_RX_STATUS_2_BERMON_STATE_BITS 6 38964 #define CL82_USERB0_RX_STATUS_2_BERMON_STATE_SHIFT 0 38965 38966 38967 /**************************************************************************** 38968 * CL82_UserB0 :: rx_status_3 38969 */ 38970 /* CL82_UserB0 :: rx_status_3 :: non_unique_Amrkr_err_mux [15:15] */ 38971 #define CL82_USERB0_RX_STATUS_3_NON_UNIQUE_AMRKR_ERR_MUX_MASK 0x8000 38972 #define CL82_USERB0_RX_STATUS_3_NON_UNIQUE_AMRKR_ERR_MUX_ALIGN 0 38973 #define CL82_USERB0_RX_STATUS_3_NON_UNIQUE_AMRKR_ERR_MUX_BITS 1 38974 #define CL82_USERB0_RX_STATUS_3_NON_UNIQUE_AMRKR_ERR_MUX_SHIFT 15 38975 38976 /* CL82_UserB0 :: rx_status_3 :: amrkr_spacing_err_latch_mux [14:14] */ 38977 #define CL82_USERB0_RX_STATUS_3_AMRKR_SPACING_ERR_LATCH_MUX_MASK 0x4000 38978 #define CL82_USERB0_RX_STATUS_3_AMRKR_SPACING_ERR_LATCH_MUX_ALIGN 0 38979 #define CL82_USERB0_RX_STATUS_3_AMRKR_SPACING_ERR_LATCH_MUX_BITS 1 38980 #define CL82_USERB0_RX_STATUS_3_AMRKR_SPACING_ERR_LATCH_MUX_SHIFT 14 38981 38982 /* CL82_UserB0 :: rx_status_3 :: am_lock_state [13:10] */ 38983 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_STATE_MASK 0x3c00 38984 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_STATE_ALIGN 0 38985 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_STATE_BITS 4 38986 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_STATE_SHIFT 10 38987 38988 /* CL82_UserB0 :: rx_status_3 :: am_lock_his_state [09:00] */ 38989 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_HIS_STATE_MASK 0x03ff 38990 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_HIS_STATE_ALIGN 0 38991 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_HIS_STATE_BITS 10 38992 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_HIS_STATE_SHIFT 0 38993 38994 38995 /**************************************************************************** 38996 * CL82_UserB0 :: rx_control_1 38997 */ 38998 /* CL82_UserB0 :: rx_control_1 :: timer125us [15:00] */ 38999 #define CL82_USERB0_RX_CONTROL_1_TIMER125US_MASK 0xffff 39000 #define CL82_USERB0_RX_CONTROL_1_TIMER125US_ALIGN 0 39001 #define CL82_USERB0_RX_CONTROL_1_TIMER125US_BITS 16 39002 #define CL82_USERB0_RX_CONTROL_1_TIMER125US_SHIFT 0 39003 39004 39005 /**************************************************************************** 39006 * CL82_UserB0 :: rx_control_2 39007 */ 39008 /* CL82_UserB0 :: rx_control_2 :: bercnt [15:08] */ 39009 #define CL82_USERB0_RX_CONTROL_2_BERCNT_MASK 0xff00 39010 #define CL82_USERB0_RX_CONTROL_2_BERCNT_ALIGN 0 39011 #define CL82_USERB0_RX_CONTROL_2_BERCNT_BITS 8 39012 #define CL82_USERB0_RX_CONTROL_2_BERCNT_SHIFT 8 39013 39014 /* CL82_UserB0 :: rx_control_2 :: reserved0 [07:06] */ 39015 #define CL82_USERB0_RX_CONTROL_2_RESERVED0_MASK 0x00c0 39016 #define CL82_USERB0_RX_CONTROL_2_RESERVED0_ALIGN 0 39017 #define CL82_USERB0_RX_CONTROL_2_RESERVED0_BITS 2 39018 #define CL82_USERB0_RX_CONTROL_2_RESERVED0_SHIFT 6 39019 39020 /* CL82_UserB0 :: rx_control_2 :: am_lane_sel [05:04] */ 39021 #define CL82_USERB0_RX_CONTROL_2_AM_LANE_SEL_MASK 0x0030 39022 #define CL82_USERB0_RX_CONTROL_2_AM_LANE_SEL_ALIGN 0 39023 #define CL82_USERB0_RX_CONTROL_2_AM_LANE_SEL_BITS 2 39024 #define CL82_USERB0_RX_CONTROL_2_AM_LANE_SEL_SHIFT 4 39025 39026 /* CL82_UserB0 :: rx_control_2 :: timer125us_ho [03:00] */ 39027 #define CL82_USERB0_RX_CONTROL_2_TIMER125US_HO_MASK 0x000f 39028 #define CL82_USERB0_RX_CONTROL_2_TIMER125US_HO_ALIGN 0 39029 #define CL82_USERB0_RX_CONTROL_2_TIMER125US_HO_BITS 4 39030 #define CL82_USERB0_RX_CONTROL_2_TIMER125US_HO_SHIFT 0 39031 39032 39033 /**************************************************************************** 39034 * CL82_UserB0 :: rx_control_3 39035 */ 39036 /* CL82_UserB0 :: rx_control_3 :: am_timer_init_val [15:00] */ 39037 #define CL82_USERB0_RX_CONTROL_3_AM_TIMER_INIT_VAL_MASK 0xffff 39038 #define CL82_USERB0_RX_CONTROL_3_AM_TIMER_INIT_VAL_ALIGN 0 39039 #define CL82_USERB0_RX_CONTROL_3_AM_TIMER_INIT_VAL_BITS 16 39040 #define CL82_USERB0_RX_CONTROL_3_AM_TIMER_INIT_VAL_SHIFT 0 39041 39042 39043 /**************************************************************************** 39044 * CL82_UserB0 :: rx_control_4 39045 */ 39046 /* CL82_UserB0 :: rx_control_4 :: mode_sel [15:15] */ 39047 #define CL82_USERB0_RX_CONTROL_4_MODE_SEL_MASK 0x8000 39048 #define CL82_USERB0_RX_CONTROL_4_MODE_SEL_ALIGN 0 39049 #define CL82_USERB0_RX_CONTROL_4_MODE_SEL_BITS 1 39050 #define CL82_USERB0_RX_CONTROL_4_MODE_SEL_SHIFT 15 39051 39052 /* CL82_UserB0 :: rx_control_4 :: reserved0 [14:10] */ 39053 #define CL82_USERB0_RX_CONTROL_4_RESERVED0_MASK 0x7c00 39054 #define CL82_USERB0_RX_CONTROL_4_RESERVED0_ALIGN 0 39055 #define CL82_USERB0_RX_CONTROL_4_RESERVED0_BITS 5 39056 #define CL82_USERB0_RX_CONTROL_4_RESERVED0_SHIFT 10 39057 39058 /* CL82_UserB0 :: rx_control_4 :: descr_bypass [09:09] */ 39059 #define CL82_USERB0_RX_CONTROL_4_DESCR_BYPASS_MASK 0x0200 39060 #define CL82_USERB0_RX_CONTROL_4_DESCR_BYPASS_ALIGN 0 39061 #define CL82_USERB0_RX_CONTROL_4_DESCR_BYPASS_BITS 1 39062 #define CL82_USERB0_RX_CONTROL_4_DESCR_BYPASS_SHIFT 9 39063 39064 /* CL82_UserB0 :: rx_control_4 :: rf_det_en_cya [08:08] */ 39065 #define CL82_USERB0_RX_CONTROL_4_RF_DET_EN_CYA_MASK 0x0100 39066 #define CL82_USERB0_RX_CONTROL_4_RF_DET_EN_CYA_ALIGN 0 39067 #define CL82_USERB0_RX_CONTROL_4_RF_DET_EN_CYA_BITS 1 39068 #define CL82_USERB0_RX_CONTROL_4_RF_DET_EN_CYA_SHIFT 8 39069 39070 /* CL82_UserB0 :: rx_control_4 :: lf_det_en_cya [07:07] */ 39071 #define CL82_USERB0_RX_CONTROL_4_LF_DET_EN_CYA_MASK 0x0080 39072 #define CL82_USERB0_RX_CONTROL_4_LF_DET_EN_CYA_ALIGN 0 39073 #define CL82_USERB0_RX_CONTROL_4_LF_DET_EN_CYA_BITS 1 39074 #define CL82_USERB0_RX_CONTROL_4_LF_DET_EN_CYA_SHIFT 7 39075 39076 /* CL82_UserB0 :: rx_control_4 :: linkdown_as_fault_cya [06:06] */ 39077 #define CL82_USERB0_RX_CONTROL_4_LINKDOWN_AS_FAULT_CYA_MASK 0x0040 39078 #define CL82_USERB0_RX_CONTROL_4_LINKDOWN_AS_FAULT_CYA_ALIGN 0 39079 #define CL82_USERB0_RX_CONTROL_4_LINKDOWN_AS_FAULT_CYA_BITS 1 39080 #define CL82_USERB0_RX_CONTROL_4_LINKDOWN_AS_FAULT_CYA_SHIFT 6 39081 39082 /* CL82_UserB0 :: rx_control_4 :: outidle_def_cya [05:05] */ 39083 #define CL82_USERB0_RX_CONTROL_4_OUTIDLE_DEF_CYA_MASK 0x0020 39084 #define CL82_USERB0_RX_CONTROL_4_OUTIDLE_DEF_CYA_ALIGN 0 39085 #define CL82_USERB0_RX_CONTROL_4_OUTIDLE_DEF_CYA_BITS 1 39086 #define CL82_USERB0_RX_CONTROL_4_OUTIDLE_DEF_CYA_SHIFT 5 39087 39088 /* CL82_UserB0 :: rx_control_4 :: deskew_win [04:00] */ 39089 #define CL82_USERB0_RX_CONTROL_4_DESKEW_WIN_MASK 0x001f 39090 #define CL82_USERB0_RX_CONTROL_4_DESKEW_WIN_ALIGN 0 39091 #define CL82_USERB0_RX_CONTROL_4_DESKEW_WIN_BITS 5 39092 #define CL82_USERB0_RX_CONTROL_4_DESKEW_WIN_SHIFT 0 39093 39094 39095 /**************************************************************************** 39096 * CL82_UserB0 :: rx_control_5 39097 */ 39098 /* CL82_UserB0 :: rx_control_5 :: reserved0 [15:15] */ 39099 #define CL82_USERB0_RX_CONTROL_5_RESERVED0_MASK 0x8000 39100 #define CL82_USERB0_RX_CONTROL_5_RESERVED0_ALIGN 0 39101 #define CL82_USERB0_RX_CONTROL_5_RESERVED0_BITS 1 39102 #define CL82_USERB0_RX_CONTROL_5_RESERVED0_SHIFT 15 39103 39104 /* CL82_UserB0 :: rx_control_5 :: bypass_cl82rxsm [14:14] */ 39105 #define CL82_USERB0_RX_CONTROL_5_BYPASS_CL82RXSM_MASK 0x4000 39106 #define CL82_USERB0_RX_CONTROL_5_BYPASS_CL82RXSM_ALIGN 0 39107 #define CL82_USERB0_RX_CONTROL_5_BYPASS_CL82RXSM_BITS 1 39108 #define CL82_USERB0_RX_CONTROL_5_BYPASS_CL82RXSM_SHIFT 14 39109 39110 /* CL82_UserB0 :: rx_control_5 :: dis_cl82_bermon [13:13] */ 39111 #define CL82_USERB0_RX_CONTROL_5_DIS_CL82_BERMON_MASK 0x2000 39112 #define CL82_USERB0_RX_CONTROL_5_DIS_CL82_BERMON_ALIGN 0 39113 #define CL82_USERB0_RX_CONTROL_5_DIS_CL82_BERMON_BITS 1 39114 #define CL82_USERB0_RX_CONTROL_5_DIS_CL82_BERMON_SHIFT 13 39115 39116 /* CL82_UserB0 :: rx_control_5 :: use_cl49_lsm_for_cl82_cya [12:12] */ 39117 #define CL82_USERB0_RX_CONTROL_5_USE_CL49_LSM_FOR_CL82_CYA_MASK 0x1000 39118 #define CL82_USERB0_RX_CONTROL_5_USE_CL49_LSM_FOR_CL82_CYA_ALIGN 0 39119 #define CL82_USERB0_RX_CONTROL_5_USE_CL49_LSM_FOR_CL82_CYA_BITS 1 39120 #define CL82_USERB0_RX_CONTROL_5_USE_CL49_LSM_FOR_CL82_CYA_SHIFT 12 39121 39122 /* CL82_UserB0 :: rx_control_5 :: sh_cnt_cl82_ext [11:00] */ 39123 #define CL82_USERB0_RX_CONTROL_5_SH_CNT_CL82_EXT_MASK 0x0fff 39124 #define CL82_USERB0_RX_CONTROL_5_SH_CNT_CL82_EXT_ALIGN 0 39125 #define CL82_USERB0_RX_CONTROL_5_SH_CNT_CL82_EXT_BITS 12 39126 #define CL82_USERB0_RX_CONTROL_5_SH_CNT_CL82_EXT_SHIFT 0 39127 39128 39129 /**************************************************************************** 39130 * CL82_UserB0 :: rx_control_6 39131 */ 39132 /* CL82_UserB0 :: rx_control_6 :: reserved0 [15:12] */ 39133 #define CL82_USERB0_RX_CONTROL_6_RESERVED0_MASK 0xf000 39134 #define CL82_USERB0_RX_CONTROL_6_RESERVED0_ALIGN 0 39135 #define CL82_USERB0_RX_CONTROL_6_RESERVED0_BITS 4 39136 #define CL82_USERB0_RX_CONTROL_6_RESERVED0_SHIFT 12 39137 39138 /* CL82_UserB0 :: rx_control_6 :: invalid_sh_cnt_cl82_ext [11:00] */ 39139 #define CL82_USERB0_RX_CONTROL_6_INVALID_SH_CNT_CL82_EXT_MASK 0x0fff 39140 #define CL82_USERB0_RX_CONTROL_6_INVALID_SH_CNT_CL82_EXT_ALIGN 0 39141 #define CL82_USERB0_RX_CONTROL_6_INVALID_SH_CNT_CL82_EXT_BITS 12 39142 #define CL82_USERB0_RX_CONTROL_6_INVALID_SH_CNT_CL82_EXT_SHIFT 0 39143 39144 39145 /**************************************************************************** 39146 * CL82_UserB0 :: rx_status_4 39147 */ 39148 /* CL82_UserB0 :: rx_status_4 :: reserved0 [15:10] */ 39149 #define CL82_USERB0_RX_STATUS_4_RESERVED0_MASK 0xfc00 39150 #define CL82_USERB0_RX_STATUS_4_RESERVED0_ALIGN 0 39151 #define CL82_USERB0_RX_STATUS_4_RESERVED0_BITS 6 39152 #define CL82_USERB0_RX_STATUS_4_RESERVED0_SHIFT 10 39153 39154 /* CL82_UserB0 :: rx_status_4 :: am_status [09:09] */ 39155 #define CL82_USERB0_RX_STATUS_4_AM_STATUS_MASK 0x0200 39156 #define CL82_USERB0_RX_STATUS_4_AM_STATUS_ALIGN 0 39157 #define CL82_USERB0_RX_STATUS_4_AM_STATUS_BITS 1 39158 #define CL82_USERB0_RX_STATUS_4_AM_STATUS_SHIFT 9 39159 39160 /* CL82_UserB0 :: rx_status_4 :: am_rmfifo_overflow [08:08] */ 39161 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_OVERFLOW_MASK 0x0100 39162 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_OVERFLOW_ALIGN 0 39163 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_OVERFLOW_BITS 1 39164 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_OVERFLOW_SHIFT 8 39165 39166 /* CL82_UserB0 :: rx_status_4 :: am_rmfifo_underflow [07:07] */ 39167 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_UNDERFLOW_MASK 0x0080 39168 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_UNDERFLOW_ALIGN 0 39169 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_UNDERFLOW_BITS 1 39170 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_UNDERFLOW_SHIFT 7 39171 39172 /* CL82_UserB0 :: rx_status_4 :: am_rmfifo_fptr_err [06:06] */ 39173 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_FPTR_ERR_MASK 0x0040 39174 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_FPTR_ERR_ALIGN 0 39175 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_FPTR_ERR_BITS 1 39176 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_FPTR_ERR_SHIFT 6 39177 39178 /* CL82_UserB0 :: rx_status_4 :: am_rmfifo_state [05:04] */ 39179 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_STATE_MASK 0x0030 39180 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_STATE_ALIGN 0 39181 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_STATE_BITS 2 39182 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_STATE_SHIFT 4 39183 39184 /* CL82_UserB0 :: rx_status_4 :: am_rmfifo_his_state [03:00] */ 39185 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_HIS_STATE_MASK 0x000f 39186 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_HIS_STATE_ALIGN 0 39187 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_HIS_STATE_BITS 4 39188 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_HIS_STATE_SHIFT 0 39189 39190 39191 /**************************************************************************** 39192 * Warpcore_USER_CL82_UserB1 39193 */ 39194 /**************************************************************************** 39195 * CL82_UserB1 :: rx_control_7 39196 */ 39197 /* CL82_UserB1 :: rx_control_7 :: rx_misc_control [15:08] */ 39198 #define CL82_USERB1_RX_CONTROL_7_RX_MISC_CONTROL_MASK 0xff00 39199 #define CL82_USERB1_RX_CONTROL_7_RX_MISC_CONTROL_ALIGN 0 39200 #define CL82_USERB1_RX_CONTROL_7_RX_MISC_CONTROL_BITS 8 39201 #define CL82_USERB1_RX_CONTROL_7_RX_MISC_CONTROL_SHIFT 8 39202 39203 /* CL82_UserB1 :: rx_control_7 :: rx_test_block_sel [07:04] */ 39204 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_BLOCK_SEL_MASK 0x00f0 39205 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_BLOCK_SEL_ALIGN 0 39206 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_BLOCK_SEL_BITS 4 39207 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_BLOCK_SEL_SHIFT 4 39208 39209 /* CL82_UserB1 :: rx_control_7 :: rx_test_data_sel [03:00] */ 39210 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_DATA_SEL_MASK 0x000f 39211 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_DATA_SEL_ALIGN 0 39212 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_DATA_SEL_BITS 4 39213 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_DATA_SEL_SHIFT 0 39214 39215 39216 /**************************************************************************** 39217 * CL82_UserB1 :: rx_status_5 39218 */ 39219 /* CL82_UserB1 :: rx_status_5 :: rx_misc_status_data [15:08] */ 39220 #define CL82_USERB1_RX_STATUS_5_RX_MISC_STATUS_DATA_MASK 0xff00 39221 #define CL82_USERB1_RX_STATUS_5_RX_MISC_STATUS_DATA_ALIGN 0 39222 #define CL82_USERB1_RX_STATUS_5_RX_MISC_STATUS_DATA_BITS 8 39223 #define CL82_USERB1_RX_STATUS_5_RX_MISC_STATUS_DATA_SHIFT 8 39224 39225 /* CL82_UserB1 :: rx_status_5 :: rx_test_status_data [07:00] */ 39226 #define CL82_USERB1_RX_STATUS_5_RX_TEST_STATUS_DATA_MASK 0x00ff 39227 #define CL82_USERB1_RX_STATUS_5_RX_TEST_STATUS_DATA_ALIGN 0 39228 #define CL82_USERB1_RX_STATUS_5_RX_TEST_STATUS_DATA_BITS 8 39229 #define CL82_USERB1_RX_STATUS_5_RX_TEST_STATUS_DATA_SHIFT 0 39230 39231 39232 /**************************************************************************** 39233 * CL82_UserB1 :: tx_control_3 39234 */ 39235 /* CL82_UserB1 :: tx_control_3 :: tx_misc_control [15:08] */ 39236 #define CL82_USERB1_TX_CONTROL_3_TX_MISC_CONTROL_MASK 0xff00 39237 #define CL82_USERB1_TX_CONTROL_3_TX_MISC_CONTROL_ALIGN 0 39238 #define CL82_USERB1_TX_CONTROL_3_TX_MISC_CONTROL_BITS 8 39239 #define CL82_USERB1_TX_CONTROL_3_TX_MISC_CONTROL_SHIFT 8 39240 39241 /* CL82_UserB1 :: tx_control_3 :: tx_test_block_sel [07:04] */ 39242 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_BLOCK_SEL_MASK 0x00f0 39243 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_BLOCK_SEL_ALIGN 0 39244 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_BLOCK_SEL_BITS 4 39245 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_BLOCK_SEL_SHIFT 4 39246 39247 /* CL82_UserB1 :: tx_control_3 :: tx_test_data_sel [03:00] */ 39248 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_DATA_SEL_MASK 0x000f 39249 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_DATA_SEL_ALIGN 0 39250 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_DATA_SEL_BITS 4 39251 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_DATA_SEL_SHIFT 0 39252 39253 39254 /**************************************************************************** 39255 * CL82_UserB1 :: tx_status_3 39256 */ 39257 /* CL82_UserB1 :: tx_status_3 :: tx_misc_status_data [15:08] */ 39258 #define CL82_USERB1_TX_STATUS_3_TX_MISC_STATUS_DATA_MASK 0xff00 39259 #define CL82_USERB1_TX_STATUS_3_TX_MISC_STATUS_DATA_ALIGN 0 39260 #define CL82_USERB1_TX_STATUS_3_TX_MISC_STATUS_DATA_BITS 8 39261 #define CL82_USERB1_TX_STATUS_3_TX_MISC_STATUS_DATA_SHIFT 8 39262 39263 /* CL82_UserB1 :: tx_status_3 :: tx_test_status_data [07:00] */ 39264 #define CL82_USERB1_TX_STATUS_3_TX_TEST_STATUS_DATA_MASK 0x00ff 39265 #define CL82_USERB1_TX_STATUS_3_TX_TEST_STATUS_DATA_ALIGN 0 39266 #define CL82_USERB1_TX_STATUS_3_TX_TEST_STATUS_DATA_BITS 8 39267 #define CL82_USERB1_TX_STATUS_3_TX_TEST_STATUS_DATA_SHIFT 0 39268 39269 39270 /**************************************************************************** 39271 * CL82_UserB1 :: tx_control_4 39272 */ 39273 /* CL82_UserB1 :: tx_control_4 :: reserved0 [15:02] */ 39274 #define CL82_USERB1_TX_CONTROL_4_RESERVED0_MASK 0xfffc 39275 #define CL82_USERB1_TX_CONTROL_4_RESERVED0_ALIGN 0 39276 #define CL82_USERB1_TX_CONTROL_4_RESERVED0_BITS 14 39277 #define CL82_USERB1_TX_CONTROL_4_RESERVED0_SHIFT 2 39278 39279 /* CL82_UserB1 :: tx_control_4 :: tx_msg_len_32bytes [01:01] */ 39280 #define CL82_USERB1_TX_CONTROL_4_TX_MSG_LEN_32BYTES_MASK 0x0002 39281 #define CL82_USERB1_TX_CONTROL_4_TX_MSG_LEN_32BYTES_ALIGN 0 39282 #define CL82_USERB1_TX_CONTROL_4_TX_MSG_LEN_32BYTES_BITS 1 39283 #define CL82_USERB1_TX_CONTROL_4_TX_MSG_LEN_32BYTES_SHIFT 1 39284 39285 /* CL82_UserB1 :: tx_control_4 :: tx_HiGig2_en [00:00] */ 39286 #define CL82_USERB1_TX_CONTROL_4_TX_HIGIG2_EN_MASK 0x0001 39287 #define CL82_USERB1_TX_CONTROL_4_TX_HIGIG2_EN_ALIGN 0 39288 #define CL82_USERB1_TX_CONTROL_4_TX_HIGIG2_EN_BITS 1 39289 #define CL82_USERB1_TX_CONTROL_4_TX_HIGIG2_EN_SHIFT 0 39290 39291 39292 /**************************************************************************** 39293 * CL82_UserB1 :: rx_control_8 39294 */ 39295 /* CL82_UserB1 :: rx_control_8 :: reserved0 [15:03] */ 39296 #define CL82_USERB1_RX_CONTROL_8_RESERVED0_MASK 0xfff8 39297 #define CL82_USERB1_RX_CONTROL_8_RESERVED0_ALIGN 0 39298 #define CL82_USERB1_RX_CONTROL_8_RESERVED0_BITS 13 39299 #define CL82_USERB1_RX_CONTROL_8_RESERVED0_SHIFT 3 39300 39301 /* CL82_UserB1 :: rx_control_8 :: dis_RX_E_cya [02:02] */ 39302 #define CL82_USERB1_RX_CONTROL_8_DIS_RX_E_CYA_MASK 0x0004 39303 #define CL82_USERB1_RX_CONTROL_8_DIS_RX_E_CYA_ALIGN 0 39304 #define CL82_USERB1_RX_CONTROL_8_DIS_RX_E_CYA_BITS 1 39305 #define CL82_USERB1_RX_CONTROL_8_DIS_RX_E_CYA_SHIFT 2 39306 39307 /* CL82_UserB1 :: rx_control_8 :: rx_msg_len_32bytes [01:01] */ 39308 #define CL82_USERB1_RX_CONTROL_8_RX_MSG_LEN_32BYTES_MASK 0x0002 39309 #define CL82_USERB1_RX_CONTROL_8_RX_MSG_LEN_32BYTES_ALIGN 0 39310 #define CL82_USERB1_RX_CONTROL_8_RX_MSG_LEN_32BYTES_BITS 1 39311 #define CL82_USERB1_RX_CONTROL_8_RX_MSG_LEN_32BYTES_SHIFT 1 39312 39313 /* CL82_UserB1 :: rx_control_8 :: rx_HiGig2_en [00:00] */ 39314 #define CL82_USERB1_RX_CONTROL_8_RX_HIGIG2_EN_MASK 0x0001 39315 #define CL82_USERB1_RX_CONTROL_8_RX_HIGIG2_EN_ALIGN 0 39316 #define CL82_USERB1_RX_CONTROL_8_RX_HIGIG2_EN_BITS 1 39317 #define CL82_USERB1_RX_CONTROL_8_RX_HIGIG2_EN_SHIFT 0 39318 39319 39320 /**************************************************************************** 39321 * CL82_UserB1 :: tx_control_5 39322 */ 39323 /* CL82_UserB1 :: tx_control_5 :: cl82_20g_AM_PCSL0_tx_bytes_1_0 [15:00] */ 39324 #define CL82_USERB1_TX_CONTROL_5_CL82_20G_AM_PCSL0_TX_BYTES_1_0_MASK 0xffff 39325 #define CL82_USERB1_TX_CONTROL_5_CL82_20G_AM_PCSL0_TX_BYTES_1_0_ALIGN 0 39326 #define CL82_USERB1_TX_CONTROL_5_CL82_20G_AM_PCSL0_TX_BYTES_1_0_BITS 16 39327 #define CL82_USERB1_TX_CONTROL_5_CL82_20G_AM_PCSL0_TX_BYTES_1_0_SHIFT 0 39328 39329 39330 /**************************************************************************** 39331 * CL82_UserB1 :: tx_control_6 39332 */ 39333 /* CL82_UserB1 :: tx_control_6 :: cl82_20g_AM_PCSL1_tx_bytes_1_0 [15:00] */ 39334 #define CL82_USERB1_TX_CONTROL_6_CL82_20G_AM_PCSL1_TX_BYTES_1_0_MASK 0xffff 39335 #define CL82_USERB1_TX_CONTROL_6_CL82_20G_AM_PCSL1_TX_BYTES_1_0_ALIGN 0 39336 #define CL82_USERB1_TX_CONTROL_6_CL82_20G_AM_PCSL1_TX_BYTES_1_0_BITS 16 39337 #define CL82_USERB1_TX_CONTROL_6_CL82_20G_AM_PCSL1_TX_BYTES_1_0_SHIFT 0 39338 39339 39340 /**************************************************************************** 39341 * CL82_UserB1 :: tx_control_7 39342 */ 39343 /* CL82_UserB1 :: tx_control_7 :: cl82_20g_AM_PCSL1_tx_bytes_2 [15:08] */ 39344 #define CL82_USERB1_TX_CONTROL_7_CL82_20G_AM_PCSL1_TX_BYTES_2_MASK 0xff00 39345 #define CL82_USERB1_TX_CONTROL_7_CL82_20G_AM_PCSL1_TX_BYTES_2_ALIGN 0 39346 #define CL82_USERB1_TX_CONTROL_7_CL82_20G_AM_PCSL1_TX_BYTES_2_BITS 8 39347 #define CL82_USERB1_TX_CONTROL_7_CL82_20G_AM_PCSL1_TX_BYTES_2_SHIFT 8 39348 39349 /* CL82_UserB1 :: tx_control_7 :: cl82_20g_AM_PCSL0_tx_bytes_2 [07:00] */ 39350 #define CL82_USERB1_TX_CONTROL_7_CL82_20G_AM_PCSL0_TX_BYTES_2_MASK 0x00ff 39351 #define CL82_USERB1_TX_CONTROL_7_CL82_20G_AM_PCSL0_TX_BYTES_2_ALIGN 0 39352 #define CL82_USERB1_TX_CONTROL_7_CL82_20G_AM_PCSL0_TX_BYTES_2_BITS 8 39353 #define CL82_USERB1_TX_CONTROL_7_CL82_20G_AM_PCSL0_TX_BYTES_2_SHIFT 0 39354 39355 39356 /**************************************************************************** 39357 * CL82_UserB1 :: rx_control_9 39358 */ 39359 /* CL82_UserB1 :: rx_control_9 :: cl82_20g_AM_PCSL0_rx_bytes_1_0 [15:00] */ 39360 #define CL82_USERB1_RX_CONTROL_9_CL82_20G_AM_PCSL0_RX_BYTES_1_0_MASK 0xffff 39361 #define CL82_USERB1_RX_CONTROL_9_CL82_20G_AM_PCSL0_RX_BYTES_1_0_ALIGN 0 39362 #define CL82_USERB1_RX_CONTROL_9_CL82_20G_AM_PCSL0_RX_BYTES_1_0_BITS 16 39363 #define CL82_USERB1_RX_CONTROL_9_CL82_20G_AM_PCSL0_RX_BYTES_1_0_SHIFT 0 39364 39365 39366 /**************************************************************************** 39367 * CL82_UserB1 :: rx_control_10 39368 */ 39369 /* CL82_UserB1 :: rx_control_10 :: cl82_20g_AM_PCSL1_rx_bytes_1_0 [15:00] */ 39370 #define CL82_USERB1_RX_CONTROL_10_CL82_20G_AM_PCSL1_RX_BYTES_1_0_MASK 0xffff 39371 #define CL82_USERB1_RX_CONTROL_10_CL82_20G_AM_PCSL1_RX_BYTES_1_0_ALIGN 0 39372 #define CL82_USERB1_RX_CONTROL_10_CL82_20G_AM_PCSL1_RX_BYTES_1_0_BITS 16 39373 #define CL82_USERB1_RX_CONTROL_10_CL82_20G_AM_PCSL1_RX_BYTES_1_0_SHIFT 0 39374 39375 39376 /**************************************************************************** 39377 * CL82_UserB1 :: rx_control_11 39378 */ 39379 /* CL82_UserB1 :: rx_control_11 :: cl82_20g_AM_PCSL1_rx_bytes_2 [15:08] */ 39380 #define CL82_USERB1_RX_CONTROL_11_CL82_20G_AM_PCSL1_RX_BYTES_2_MASK 0xff00 39381 #define CL82_USERB1_RX_CONTROL_11_CL82_20G_AM_PCSL1_RX_BYTES_2_ALIGN 0 39382 #define CL82_USERB1_RX_CONTROL_11_CL82_20G_AM_PCSL1_RX_BYTES_2_BITS 8 39383 #define CL82_USERB1_RX_CONTROL_11_CL82_20G_AM_PCSL1_RX_BYTES_2_SHIFT 8 39384 39385 /* CL82_UserB1 :: rx_control_11 :: cl82_20g_AM_PCSL0_rx_bytes_2 [07:00] */ 39386 #define CL82_USERB1_RX_CONTROL_11_CL82_20G_AM_PCSL0_RX_BYTES_2_MASK 0x00ff 39387 #define CL82_USERB1_RX_CONTROL_11_CL82_20G_AM_PCSL0_RX_BYTES_2_ALIGN 0 39388 #define CL82_USERB1_RX_CONTROL_11_CL82_20G_AM_PCSL0_RX_BYTES_2_BITS 8 39389 #define CL82_USERB1_RX_CONTROL_11_CL82_20G_AM_PCSL0_RX_BYTES_2_SHIFT 0 39390 39391 39392 /**************************************************************************** 39393 * Warpcore_USER_rx66b1 39394 */ 39395 /**************************************************************************** 39396 * rx66b1 :: brcm_cl49_Control 39397 */ 39398 /* rx66b1 :: brcm_cl49_Control :: reserved0 [15:04] */ 39399 #define RX66B1_BRCM_CL49_CONTROL_RESERVED0_MASK 0xfff0 39400 #define RX66B1_BRCM_CL49_CONTROL_RESERVED0_ALIGN 0 39401 #define RX66B1_BRCM_CL49_CONTROL_RESERVED0_BITS 12 39402 #define RX66B1_BRCM_CL49_CONTROL_RESERVED0_SHIFT 4 39403 39404 /* rx66b1 :: brcm_cl49_Control :: mdio_brcmfault_det_en [03:03] */ 39405 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCMFAULT_DET_EN_MASK 0x0008 39406 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCMFAULT_DET_EN_ALIGN 0 39407 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCMFAULT_DET_EN_BITS 1 39408 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCMFAULT_DET_EN_SHIFT 3 39409 39410 /* rx66b1 :: brcm_cl49_Control :: brcm_cl49_dout_ctrl [02:01] */ 39411 #define RX66B1_BRCM_CL49_CONTROL_BRCM_CL49_DOUT_CTRL_MASK 0x0006 39412 #define RX66B1_BRCM_CL49_CONTROL_BRCM_CL49_DOUT_CTRL_ALIGN 0 39413 #define RX66B1_BRCM_CL49_CONTROL_BRCM_CL49_DOUT_CTRL_BITS 2 39414 #define RX66B1_BRCM_CL49_CONTROL_BRCM_CL49_DOUT_CTRL_SHIFT 1 39415 39416 /* rx66b1 :: brcm_cl49_Control :: mdio_brcm6466_cl49_en [00:00] */ 39417 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCM6466_CL49_EN_MASK 0x0001 39418 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCM6466_CL49_EN_ALIGN 0 39419 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCM6466_CL49_EN_BITS 1 39420 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCM6466_CL49_EN_SHIFT 0 39421 39422 39423 /**************************************************************************** 39424 * rx66b1 :: rx66b1_Control1 39425 */ 39426 /* rx66b1 :: rx66b1_Control1 :: reserved_for_eco0 [15:01] */ 39427 #define RX66B1_RX66B1_CONTROL1_RESERVED_FOR_ECO0_MASK 0xfffe 39428 #define RX66B1_RX66B1_CONTROL1_RESERVED_FOR_ECO0_ALIGN 0 39429 #define RX66B1_RX66B1_CONTROL1_RESERVED_FOR_ECO0_BITS 15 39430 #define RX66B1_RX66B1_CONTROL1_RESERVED_FOR_ECO0_SHIFT 1 39431 39432 /* rx66b1 :: rx66b1_Control1 :: rfifo_ptr_sw_rst [00:00] */ 39433 #define RX66B1_RX66B1_CONTROL1_RFIFO_PTR_SW_RST_MASK 0x0001 39434 #define RX66B1_RX66B1_CONTROL1_RFIFO_PTR_SW_RST_ALIGN 0 39435 #define RX66B1_RX66B1_CONTROL1_RFIFO_PTR_SW_RST_BITS 1 39436 #define RX66B1_RX66B1_CONTROL1_RFIFO_PTR_SW_RST_SHIFT 0 39437 39438 39439 /**************************************************************************** 39440 * Warpcore_USER_ETA 39441 */ 39442 /**************************************************************************** 39443 * ETA :: ETA1 39444 */ 39445 /* ETA :: ETA1 :: reserved0 [15:02] */ 39446 #define ETA_ETA1_RESERVED0_MASK 0xfffc 39447 #define ETA_ETA1_RESERVED0_ALIGN 0 39448 #define ETA_ETA1_RESERVED0_BITS 14 39449 #define ETA_ETA1_RESERVED0_SHIFT 2 39450 39451 /* ETA :: ETA1 :: CR2_common_ETA [01:01] */ 39452 #define ETA_ETA1_CR2_COMMON_ETA_MASK 0x0002 39453 #define ETA_ETA1_CR2_COMMON_ETA_ALIGN 0 39454 #define ETA_ETA1_CR2_COMMON_ETA_BITS 1 39455 #define ETA_ETA1_CR2_COMMON_ETA_SHIFT 1 39456 39457 /* ETA :: ETA1 :: KR2_common_ETA [00:00] */ 39458 #define ETA_ETA1_KR2_COMMON_ETA_MASK 0x0001 39459 #define ETA_ETA1_KR2_COMMON_ETA_ALIGN 0 39460 #define ETA_ETA1_KR2_COMMON_ETA_BITS 1 39461 #define ETA_ETA1_KR2_COMMON_ETA_SHIFT 0 39462 39463 39464 /**************************************************************************** 39465 * ETA :: ETA2 39466 */ 39467 /* ETA :: ETA2 :: reserved0 [15:02] */ 39468 #define ETA_ETA2_RESERVED0_MASK 0xfffc 39469 #define ETA_ETA2_RESERVED0_ALIGN 0 39470 #define ETA_ETA2_RESERVED0_BITS 14 39471 #define ETA_ETA2_RESERVED0_SHIFT 2 39472 39473 /* ETA :: ETA2 :: CR2_ld_ETA [01:01] */ 39474 #define ETA_ETA2_CR2_LD_ETA_MASK 0x0002 39475 #define ETA_ETA2_CR2_LD_ETA_ALIGN 0 39476 #define ETA_ETA2_CR2_LD_ETA_BITS 1 39477 #define ETA_ETA2_CR2_LD_ETA_SHIFT 1 39478 39479 /* ETA :: ETA2 :: KR2_ld_ETA [00:00] */ 39480 #define ETA_ETA2_KR2_LD_ETA_MASK 0x0001 39481 #define ETA_ETA2_KR2_LD_ETA_ALIGN 0 39482 #define ETA_ETA2_KR2_LD_ETA_BITS 1 39483 #define ETA_ETA2_KR2_LD_ETA_SHIFT 0 39484 39485 39486 /**************************************************************************** 39487 * ETA :: ETA3 39488 */ 39489 /* ETA :: ETA3 :: reserved0 [15:02] */ 39490 #define ETA_ETA3_RESERVED0_MASK 0xfffc 39491 #define ETA_ETA3_RESERVED0_ALIGN 0 39492 #define ETA_ETA3_RESERVED0_BITS 14 39493 #define ETA_ETA3_RESERVED0_SHIFT 2 39494 39495 /* ETA :: ETA3 :: customer_AN_eta_enable [01:01] */ 39496 #define ETA_ETA3_CUSTOMER_AN_ETA_ENABLE_MASK 0x0002 39497 #define ETA_ETA3_CUSTOMER_AN_ETA_ENABLE_ALIGN 0 39498 #define ETA_ETA3_CUSTOMER_AN_ETA_ENABLE_BITS 1 39499 #define ETA_ETA3_CUSTOMER_AN_ETA_ENABLE_SHIFT 1 39500 39501 /* ETA :: ETA3 :: BAM73_eta_enable [00:00] */ 39502 #define ETA_ETA3_BAM73_ETA_ENABLE_MASK 0x0001 39503 #define ETA_ETA3_BAM73_ETA_ENABLE_ALIGN 0 39504 #define ETA_ETA3_BAM73_ETA_ENABLE_BITS 1 39505 #define ETA_ETA3_BAM73_ETA_ENABLE_SHIFT 0 39506 39507 39508 /**************************************************************************** 39509 * Warpcore_USER_PatGen256_0 39510 */ 39511 /**************************************************************************** 39512 * PatGen256_0 :: reg0 39513 */ 39514 /* PatGen256_0 :: reg0 :: reg0 [15:00] */ 39515 #define PATGEN256_0_REG0_REG0_MASK 0xffff 39516 #define PATGEN256_0_REG0_REG0_ALIGN 0 39517 #define PATGEN256_0_REG0_REG0_BITS 16 39518 #define PATGEN256_0_REG0_REG0_SHIFT 0 39519 39520 39521 /**************************************************************************** 39522 * PatGen256_0 :: reg1 39523 */ 39524 /* PatGen256_0 :: reg1 :: reg1 [15:00] */ 39525 #define PATGEN256_0_REG1_REG1_MASK 0xffff 39526 #define PATGEN256_0_REG1_REG1_ALIGN 0 39527 #define PATGEN256_0_REG1_REG1_BITS 16 39528 #define PATGEN256_0_REG1_REG1_SHIFT 0 39529 39530 39531 /**************************************************************************** 39532 * PatGen256_0 :: reg2 39533 */ 39534 /* PatGen256_0 :: reg2 :: reg2 [15:00] */ 39535 #define PATGEN256_0_REG2_REG2_MASK 0xffff 39536 #define PATGEN256_0_REG2_REG2_ALIGN 0 39537 #define PATGEN256_0_REG2_REG2_BITS 16 39538 #define PATGEN256_0_REG2_REG2_SHIFT 0 39539 39540 39541 /**************************************************************************** 39542 * PatGen256_0 :: reg3 39543 */ 39544 /* PatGen256_0 :: reg3 :: reg3 [15:00] */ 39545 #define PATGEN256_0_REG3_REG3_MASK 0xffff 39546 #define PATGEN256_0_REG3_REG3_ALIGN 0 39547 #define PATGEN256_0_REG3_REG3_BITS 16 39548 #define PATGEN256_0_REG3_REG3_SHIFT 0 39549 39550 39551 /**************************************************************************** 39552 * PatGen256_0 :: reg4 39553 */ 39554 /* PatGen256_0 :: reg4 :: reg4 [15:00] */ 39555 #define PATGEN256_0_REG4_REG4_MASK 0xffff 39556 #define PATGEN256_0_REG4_REG4_ALIGN 0 39557 #define PATGEN256_0_REG4_REG4_BITS 16 39558 #define PATGEN256_0_REG4_REG4_SHIFT 0 39559 39560 39561 /**************************************************************************** 39562 * PatGen256_0 :: reg5 39563 */ 39564 /* PatGen256_0 :: reg5 :: reg5 [15:00] */ 39565 #define PATGEN256_0_REG5_REG5_MASK 0xffff 39566 #define PATGEN256_0_REG5_REG5_ALIGN 0 39567 #define PATGEN256_0_REG5_REG5_BITS 16 39568 #define PATGEN256_0_REG5_REG5_SHIFT 0 39569 39570 39571 /**************************************************************************** 39572 * PatGen256_0 :: reg6 39573 */ 39574 /* PatGen256_0 :: reg6 :: reg6 [15:00] */ 39575 #define PATGEN256_0_REG6_REG6_MASK 0xffff 39576 #define PATGEN256_0_REG6_REG6_ALIGN 0 39577 #define PATGEN256_0_REG6_REG6_BITS 16 39578 #define PATGEN256_0_REG6_REG6_SHIFT 0 39579 39580 39581 /**************************************************************************** 39582 * PatGen256_0 :: reg7 39583 */ 39584 /* PatGen256_0 :: reg7 :: reg7 [15:00] */ 39585 #define PATGEN256_0_REG7_REG7_MASK 0xffff 39586 #define PATGEN256_0_REG7_REG7_ALIGN 0 39587 #define PATGEN256_0_REG7_REG7_BITS 16 39588 #define PATGEN256_0_REG7_REG7_SHIFT 0 39589 39590 39591 /**************************************************************************** 39592 * PatGen256_0 :: reg8 39593 */ 39594 /* PatGen256_0 :: reg8 :: reg8 [15:00] */ 39595 #define PATGEN256_0_REG8_REG8_MASK 0xffff 39596 #define PATGEN256_0_REG8_REG8_ALIGN 0 39597 #define PATGEN256_0_REG8_REG8_BITS 16 39598 #define PATGEN256_0_REG8_REG8_SHIFT 0 39599 39600 39601 /**************************************************************************** 39602 * PatGen256_0 :: reg9 39603 */ 39604 /* PatGen256_0 :: reg9 :: reg9 [15:00] */ 39605 #define PATGEN256_0_REG9_REG9_MASK 0xffff 39606 #define PATGEN256_0_REG9_REG9_ALIGN 0 39607 #define PATGEN256_0_REG9_REG9_BITS 16 39608 #define PATGEN256_0_REG9_REG9_SHIFT 0 39609 39610 39611 /**************************************************************************** 39612 * PatGen256_0 :: reg10 39613 */ 39614 /* PatGen256_0 :: reg10 :: reg10 [15:00] */ 39615 #define PATGEN256_0_REG10_REG10_MASK 0xffff 39616 #define PATGEN256_0_REG10_REG10_ALIGN 0 39617 #define PATGEN256_0_REG10_REG10_BITS 16 39618 #define PATGEN256_0_REG10_REG10_SHIFT 0 39619 39620 39621 /**************************************************************************** 39622 * PatGen256_0 :: reg11 39623 */ 39624 /* PatGen256_0 :: reg11 :: reg11 [15:00] */ 39625 #define PATGEN256_0_REG11_REG11_MASK 0xffff 39626 #define PATGEN256_0_REG11_REG11_ALIGN 0 39627 #define PATGEN256_0_REG11_REG11_BITS 16 39628 #define PATGEN256_0_REG11_REG11_SHIFT 0 39629 39630 39631 /**************************************************************************** 39632 * PatGen256_0 :: reg12 39633 */ 39634 /* PatGen256_0 :: reg12 :: reg12 [15:00] */ 39635 #define PATGEN256_0_REG12_REG12_MASK 0xffff 39636 #define PATGEN256_0_REG12_REG12_ALIGN 0 39637 #define PATGEN256_0_REG12_REG12_BITS 16 39638 #define PATGEN256_0_REG12_REG12_SHIFT 0 39639 39640 39641 /**************************************************************************** 39642 * PatGen256_0 :: reg13 39643 */ 39644 /* PatGen256_0 :: reg13 :: reg13 [15:00] */ 39645 #define PATGEN256_0_REG13_REG13_MASK 0xffff 39646 #define PATGEN256_0_REG13_REG13_ALIGN 0 39647 #define PATGEN256_0_REG13_REG13_BITS 16 39648 #define PATGEN256_0_REG13_REG13_SHIFT 0 39649 39650 39651 /**************************************************************************** 39652 * PatGen256_0 :: reg14 39653 */ 39654 /* PatGen256_0 :: reg14 :: reg14 [15:00] */ 39655 #define PATGEN256_0_REG14_REG14_MASK 0xffff 39656 #define PATGEN256_0_REG14_REG14_ALIGN 0 39657 #define PATGEN256_0_REG14_REG14_BITS 16 39658 #define PATGEN256_0_REG14_REG14_SHIFT 0 39659 39660 39661 /**************************************************************************** 39662 * Warpcore_USER_PatGen256_1 39663 */ 39664 /**************************************************************************** 39665 * PatGen256_1 :: reg15 39666 */ 39667 /* PatGen256_1 :: reg15 :: reg15 [15:00] */ 39668 #define PATGEN256_1_REG15_REG15_MASK 0xffff 39669 #define PATGEN256_1_REG15_REG15_ALIGN 0 39670 #define PATGEN256_1_REG15_REG15_BITS 16 39671 #define PATGEN256_1_REG15_REG15_SHIFT 0 39672 39673 39674 /**************************************************************************** 39675 * PatGen256_1 :: ctrl 39676 */ 39677 /* PatGen256_1 :: ctrl :: reserved0 [15:01] */ 39678 #define PATGEN256_1_CTRL_RESERVED0_MASK 0xfffe 39679 #define PATGEN256_1_CTRL_RESERVED0_ALIGN 0 39680 #define PATGEN256_1_CTRL_RESERVED0_BITS 15 39681 #define PATGEN256_1_CTRL_RESERVED0_SHIFT 1 39682 39683 /* PatGen256_1 :: ctrl :: gen_ena [00:00] */ 39684 #define PATGEN256_1_CTRL_GEN_ENA_MASK 0x0001 39685 #define PATGEN256_1_CTRL_GEN_ENA_ALIGN 0 39686 #define PATGEN256_1_CTRL_GEN_ENA_BITS 1 39687 #define PATGEN256_1_CTRL_GEN_ENA_SHIFT 0 39688 39689 39690 /**************************************************************************** 39691 * Warpcore_USER_XFI_BD0 39692 */ 39693 /**************************************************************************** 39694 * XFI_BD0 :: pmd_and_pcs_status_register 39695 */ 39696 /* XFI_BD0 :: pmd_and_pcs_status_register :: reserved0 [15:15] */ 39697 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED0_MASK 0x8000 39698 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED0_ALIGN 0 39699 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED0_BITS 1 39700 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED0_SHIFT 15 39701 39702 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_losbi_bar [14:14] */ 39703 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_BAR_MASK 0x4000 39704 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_BAR_ALIGN 0 39705 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_BAR_BITS 1 39706 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_BAR_SHIFT 14 39707 39708 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_losb_bar [13:13] */ 39709 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_BAR_MASK 0x2000 39710 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_BAR_ALIGN 0 39711 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_BAR_BITS 1 39712 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_BAR_SHIFT 13 39713 39714 /* XFI_BD0 :: pmd_and_pcs_status_register :: reserved1 [12:12] */ 39715 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED1_MASK 0x1000 39716 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED1_ALIGN 0 39717 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED1_BITS 1 39718 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED1_SHIFT 12 39719 39720 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdtcmu_bar [11:11] */ 39721 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_BAR_MASK 0x0800 39722 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_BAR_ALIGN 0 39723 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_BAR_BITS 1 39724 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_BAR_SHIFT 11 39725 39726 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdtcdr_bar [10:10] */ 39727 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_BAR_MASK 0x0400 39728 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_BAR_ALIGN 0 39729 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_BAR_BITS 1 39730 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_BAR_SHIFT 10 39731 39732 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdt_ep_bar [09:09] */ 39733 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_BAR_MASK 0x0200 39734 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_BAR_ALIGN 0 39735 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_BAR_BITS 1 39736 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_BAR_SHIFT 9 39737 39738 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_linelpbk_cls [08:08] */ 39739 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LINELPBK_CLS_MASK 0x0100 39740 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LINELPBK_CLS_ALIGN 0 39741 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LINELPBK_CLS_BITS 1 39742 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LINELPBK_CLS_SHIFT 8 39743 39744 /* XFI_BD0 :: pmd_and_pcs_status_register :: reserved2 [07:07] */ 39745 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED2_MASK 0x0080 39746 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED2_ALIGN 0 39747 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED2_BITS 1 39748 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED2_SHIFT 7 39749 39750 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_losbi [06:06] */ 39751 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_MASK 0x0040 39752 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_ALIGN 0 39753 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_BITS 1 39754 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_SHIFT 6 39755 39756 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_losb [05:05] */ 39757 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_MASK 0x0020 39758 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_ALIGN 0 39759 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_BITS 1 39760 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_SHIFT 5 39761 39762 /* XFI_BD0 :: pmd_and_pcs_status_register :: reserved3 [04:04] */ 39763 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED3_MASK 0x0010 39764 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED3_ALIGN 0 39765 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED3_BITS 1 39766 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED3_SHIFT 4 39767 39768 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdtcmu [03:03] */ 39769 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_MASK 0x0008 39770 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_ALIGN 0 39771 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_BITS 1 39772 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_SHIFT 3 39773 39774 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdtcdr [02:02] */ 39775 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_MASK 0x0004 39776 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_ALIGN 0 39777 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_BITS 1 39778 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_SHIFT 2 39779 39780 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdt_ep [01:01] */ 39781 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_MASK 0x0002 39782 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_ALIGN 0 39783 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_BITS 1 39784 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_SHIFT 1 39785 39786 /* XFI_BD0 :: pmd_and_pcs_status_register :: reserved4 [00:00] */ 39787 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED4_MASK 0x0001 39788 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED4_ALIGN 0 39789 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED4_BITS 1 39790 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED4_SHIFT 0 39791 39792 39793 /**************************************************************************** 39794 * XFI_BD0 :: pmd_optics_digital_control_register 39795 */ 39796 /* XFI_BD0 :: pmd_optics_digital_control_register :: cl73_txdis_en [15:15] */ 39797 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_CL73_TXDIS_EN_MASK 0x8000 39798 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_CL73_TXDIS_EN_ALIGN 0 39799 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_CL73_TXDIS_EN_BITS 1 39800 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_CL73_TXDIS_EN_SHIFT 15 39801 39802 /* XFI_BD0 :: pmd_optics_digital_control_register :: reserved0 [14:13] */ 39803 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED0_MASK 0x6000 39804 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED0_ALIGN 0 39805 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED0_BITS 2 39806 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED0_SHIFT 13 39807 39808 /* XFI_BD0 :: pmd_optics_digital_control_register :: pcs_rx_order [12:12] */ 39809 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_ORDER_MASK 0x1000 39810 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_ORDER_ALIGN 0 39811 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_ORDER_BITS 1 39812 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_ORDER_SHIFT 12 39813 39814 /* XFI_BD0 :: pmd_optics_digital_control_register :: pcs_tx_order [11:11] */ 39815 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_ORDER_MASK 0x0800 39816 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_ORDER_ALIGN 0 39817 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_ORDER_BITS 1 39818 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_ORDER_SHIFT 11 39819 39820 /* XFI_BD0 :: pmd_optics_digital_control_register :: pcs_tx_inv [10:10] */ 39821 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_INV_MASK 0x0400 39822 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_INV_ALIGN 0 39823 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_INV_BITS 1 39824 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_INV_SHIFT 10 39825 39826 /* XFI_BD0 :: pmd_optics_digital_control_register :: pcs_rx_inv [09:09] */ 39827 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_INV_MASK 0x0200 39828 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_INV_ALIGN 0 39829 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_INV_BITS 1 39830 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_INV_SHIFT 9 39831 39832 /* XFI_BD0 :: pmd_optics_digital_control_register :: higig2_ent [08:08] */ 39833 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_ENT_MASK 0x0100 39834 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_ENT_ALIGN 0 39835 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_ENT_BITS 1 39836 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_ENT_SHIFT 8 39837 39838 /* XFI_BD0 :: pmd_optics_digital_control_register :: higig2_size [07:07] */ 39839 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_SIZE_MASK 0x0080 39840 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_SIZE_ALIGN 0 39841 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_SIZE_BITS 1 39842 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_SIZE_SHIFT 7 39843 39844 /* XFI_BD0 :: pmd_optics_digital_control_register :: reserved1 [06:04] */ 39845 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED1_MASK 0x0070 39846 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED1_ALIGN 0 39847 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED1_BITS 3 39848 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED1_SHIFT 4 39849 39850 /* XFI_BD0 :: pmd_optics_digital_control_register :: lpbk_err_dis [03:03] */ 39851 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_LPBK_ERR_DIS_MASK 0x0008 39852 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_LPBK_ERR_DIS_ALIGN 0 39853 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_LPBK_ERR_DIS_BITS 1 39854 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_LPBK_ERR_DIS_SHIFT 3 39855 39856 /* XFI_BD0 :: pmd_optics_digital_control_register :: reserved2 [02:00] */ 39857 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED2_MASK 0x0007 39858 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED2_ALIGN 0 39859 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED2_BITS 3 39860 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED2_SHIFT 0 39861 39862 39863 /**************************************************************************** 39864 * XFI_BD0 :: pmd_digital_status_register 39865 */ 39866 /* XFI_BD0 :: pmd_digital_status_register :: t64_gbox_ovf [15:15] */ 39867 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_GBOX_OVF_MASK 0x8000 39868 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_GBOX_OVF_ALIGN 0 39869 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_GBOX_OVF_BITS 1 39870 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_GBOX_OVF_SHIFT 15 39871 39872 /* XFI_BD0 :: pmd_digital_status_register :: t64_init_error [14:14] */ 39873 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_INIT_ERROR_MASK 0x4000 39874 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_INIT_ERROR_ALIGN 0 39875 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_INIT_ERROR_BITS 1 39876 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_INIT_ERROR_SHIFT 14 39877 39878 /* XFI_BD0 :: pmd_digital_status_register :: t64_c_error [13:13] */ 39879 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_C_ERROR_MASK 0x2000 39880 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_C_ERROR_ALIGN 0 39881 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_C_ERROR_BITS 1 39882 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_C_ERROR_SHIFT 13 39883 39884 /* XFI_BD0 :: pmd_digital_status_register :: t64_d_error [12:12] */ 39885 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_D_ERROR_MASK 0x1000 39886 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_D_ERROR_ALIGN 0 39887 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_D_ERROR_BITS 1 39888 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_D_ERROR_SHIFT 12 39889 39890 /* XFI_BD0 :: pmd_digital_status_register :: t64_t_error [11:11] */ 39891 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_T_ERROR_MASK 0x0800 39892 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_T_ERROR_ALIGN 0 39893 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_T_ERROR_BITS 1 39894 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_T_ERROR_SHIFT 11 39895 39896 /* XFI_BD0 :: pmd_digital_status_register :: r64_gbox_ovf [10:10] */ 39897 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_GBOX_OVF_MASK 0x0400 39898 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_GBOX_OVF_ALIGN 0 39899 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_GBOX_OVF_BITS 1 39900 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_GBOX_OVF_SHIFT 10 39901 39902 /* XFI_BD0 :: pmd_digital_status_register :: r64_sync_acq [09:09] */ 39903 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_SYNC_ACQ_MASK 0x0200 39904 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_SYNC_ACQ_ALIGN 0 39905 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_SYNC_ACQ_BITS 1 39906 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_SYNC_ACQ_SHIFT 9 39907 39908 /* XFI_BD0 :: pmd_digital_status_register :: r64_los [08:08] */ 39909 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_LOS_MASK 0x0100 39910 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_LOS_ALIGN 0 39911 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_LOS_BITS 1 39912 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_LOS_SHIFT 8 39913 39914 /* XFI_BD0 :: pmd_digital_status_register :: r64_init_error [07:07] */ 39915 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_INIT_ERROR_MASK 0x0080 39916 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_INIT_ERROR_ALIGN 0 39917 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_INIT_ERROR_BITS 1 39918 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_INIT_ERROR_SHIFT 7 39919 39920 /* XFI_BD0 :: pmd_digital_status_register :: r64_c_error [06:06] */ 39921 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_C_ERROR_MASK 0x0040 39922 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_C_ERROR_ALIGN 0 39923 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_C_ERROR_BITS 1 39924 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_C_ERROR_SHIFT 6 39925 39926 /* XFI_BD0 :: pmd_digital_status_register :: r64_d_error [05:05] */ 39927 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_D_ERROR_MASK 0x0020 39928 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_D_ERROR_ALIGN 0 39929 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_D_ERROR_BITS 1 39930 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_D_ERROR_SHIFT 5 39931 39932 /* XFI_BD0 :: pmd_digital_status_register :: r64_t_error [04:04] */ 39933 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_T_ERROR_MASK 0x0010 39934 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_T_ERROR_ALIGN 0 39935 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_T_ERROR_BITS 1 39936 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_T_ERROR_SHIFT 4 39937 39938 /* XFI_BD0 :: pmd_digital_status_register :: reserved0 [03:01] */ 39939 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_RESERVED0_MASK 0x000e 39940 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_RESERVED0_ALIGN 0 39941 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_RESERVED0_BITS 3 39942 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_RESERVED0_SHIFT 1 39943 39944 /* XFI_BD0 :: pmd_digital_status_register :: r64_jitt_pat_det [00:00] */ 39945 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_JITT_PAT_DET_MASK 0x0001 39946 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_JITT_PAT_DET_ALIGN 0 39947 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_JITT_PAT_DET_BITS 1 39948 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_JITT_PAT_DET_SHIFT 0 39949 39950 39951 /**************************************************************************** 39952 * XFI_BD0 :: pmd_and_pcs_test_control_register 39953 */ 39954 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: tx_gptpat_ent [15:15] */ 39955 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_GPTPAT_ENT_MASK 0x8000 39956 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_GPTPAT_ENT_ALIGN 0 39957 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_GPTPAT_ENT_BITS 1 39958 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_GPTPAT_ENT_SHIFT 15 39959 39960 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: tx_6sqwave_ent [14:14] */ 39961 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_6SQWAVE_ENT_MASK 0x4000 39962 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_6SQWAVE_ENT_ALIGN 0 39963 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_6SQWAVE_ENT_BITS 1 39964 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_6SQWAVE_ENT_SHIFT 14 39965 39966 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: bist_ierr [13:13] */ 39967 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_BIST_IERR_MASK 0x2000 39968 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_BIST_IERR_ALIGN 0 39969 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_BIST_IERR_BITS 1 39970 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_BIST_IERR_SHIFT 13 39971 39972 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: tx_prbs7_en [12:12] */ 39973 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_PRBS7_EN_MASK 0x1000 39974 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_PRBS7_EN_ALIGN 0 39975 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_PRBS7_EN_BITS 1 39976 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_PRBS7_EN_SHIFT 12 39977 39978 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: tx_scrb_dis [11:11] */ 39979 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_SCRB_DIS_MASK 0x0800 39980 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_SCRB_DIS_ALIGN 0 39981 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_SCRB_DIS_BITS 1 39982 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_SCRB_DIS_SHIFT 11 39983 39984 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: rx_descrb_dis [10:10] */ 39985 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_DESCRB_DIS_MASK 0x0400 39986 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_DESCRB_DIS_ALIGN 0 39987 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_DESCRB_DIS_BITS 1 39988 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_DESCRB_DIS_SHIFT 10 39989 39990 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: rx_buf_rd_on [09:09] */ 39991 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_ON_MASK 0x0200 39992 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_ON_ALIGN 0 39993 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_ON_BITS 1 39994 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_ON_SHIFT 9 39995 39996 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: rx_buf_rd_sel [08:07] */ 39997 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_SEL_MASK 0x0180 39998 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_SEL_ALIGN 0 39999 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_SEL_BITS 2 40000 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_SEL_SHIFT 7 40001 40002 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: reserved0 [06:04] */ 40003 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED0_MASK 0x0070 40004 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED0_ALIGN 0 40005 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED0_BITS 3 40006 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED0_SHIFT 4 40007 40008 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: fec_dbg_err_mode [03:03] */ 40009 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_FEC_DBG_ERR_MODE_MASK 0x0008 40010 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_FEC_DBG_ERR_MODE_ALIGN 0 40011 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_FEC_DBG_ERR_MODE_BITS 1 40012 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_FEC_DBG_ERR_MODE_SHIFT 3 40013 40014 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: reserved1 [02:01] */ 40015 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED1_MASK 0x0006 40016 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED1_ALIGN 0 40017 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED1_BITS 2 40018 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED1_SHIFT 1 40019 40020 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: pmd_pma_lineloopback [00:00] */ 40021 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_PMD_PMA_LINELOOPBACK_MASK 0x0001 40022 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_PMD_PMA_LINELOOPBACK_ALIGN 0 40023 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_PMD_PMA_LINELOOPBACK_BITS 1 40024 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_PMD_PMA_LINELOOPBACK_SHIFT 0 40025 40026 40027 /**************************************************************************** 40028 * XFI_BD0 :: pmd_general_purpose_tx_pattern_register_0 40029 */ 40030 /* XFI_BD0 :: pmd_general_purpose_tx_pattern_register_0 :: pmd_tx_gprpat15_0 [15:00] */ 40031 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0_PMD_TX_GPRPAT15_0_MASK 0xffff 40032 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0_PMD_TX_GPRPAT15_0_ALIGN 0 40033 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0_PMD_TX_GPRPAT15_0_BITS 16 40034 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0_PMD_TX_GPRPAT15_0_SHIFT 0 40035 40036 40037 /**************************************************************************** 40038 * XFI_BD0 :: pmd_general_purpose_tx_pattern_register_1 40039 */ 40040 /* XFI_BD0 :: pmd_general_purpose_tx_pattern_register_1 :: pmd_tx_gprpat31_16 [15:00] */ 40041 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1_PMD_TX_GPRPAT31_16_MASK 0xffff 40042 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1_PMD_TX_GPRPAT31_16_ALIGN 0 40043 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1_PMD_TX_GPRPAT31_16_BITS 16 40044 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1_PMD_TX_GPRPAT31_16_SHIFT 0 40045 40046 40047 /**************************************************************************** 40048 * Warpcore_USER_XFI_BD1 40049 */ 40050 /**************************************************************************** 40051 * XFI_BD1 :: prbs_31_test_window_1_register 40052 */ 40053 /* XFI_BD1 :: prbs_31_test_window_1_register :: prbs31_win31_16 [15:00] */ 40054 #define XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTER_PRBS31_WIN31_16_MASK 0xffff 40055 #define XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTER_PRBS31_WIN31_16_ALIGN 0 40056 #define XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTER_PRBS31_WIN31_16_BITS 16 40057 #define XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTER_PRBS31_WIN31_16_SHIFT 0 40058 40059 40060 /**************************************************************************** 40061 * XFI_BD1 :: prbs_31_test_window_2_register 40062 */ 40063 /* XFI_BD1 :: prbs_31_test_window_2_register :: reserved0 [15:13] */ 40064 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_RESERVED0_MASK 0xe000 40065 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_RESERVED0_ALIGN 0 40066 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_RESERVED0_BITS 3 40067 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_RESERVED0_SHIFT 13 40068 40069 /* XFI_BD1 :: prbs_31_test_window_2_register :: prbs31_win44_32 [12:00] */ 40070 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_PRBS31_WIN44_32_MASK 0x1fff 40071 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_PRBS31_WIN44_32_ALIGN 0 40072 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_PRBS31_WIN44_32_BITS 13 40073 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_PRBS31_WIN44_32_SHIFT 0 40074 40075 40076 /**************************************************************************** 40077 * XFI_BD1 :: user_prbs_control_0_register 40078 */ 40079 /* XFI_BD1 :: user_prbs_control_0_register :: prbs_inv_rx [15:15] */ 40080 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_RX_MASK 0x8000 40081 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_RX_ALIGN 0 40082 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_RX_BITS 1 40083 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_RX_SHIFT 15 40084 40085 /* XFI_BD1 :: user_prbs_control_0_register :: prbs_sel_rx [14:12] */ 40086 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_RX_MASK 0x7000 40087 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_RX_ALIGN 0 40088 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_RX_BITS 3 40089 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_RX_SHIFT 12 40090 40091 /* XFI_BD1 :: user_prbs_control_0_register :: reserved0 [11:05] */ 40092 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED0_MASK 0x0fe0 40093 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED0_ALIGN 0 40094 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED0_BITS 7 40095 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED0_SHIFT 5 40096 40097 /* XFI_BD1 :: user_prbs_control_0_register :: prbs_inv_tx [04:04] */ 40098 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_TX_MASK 0x0010 40099 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_TX_ALIGN 0 40100 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_TX_BITS 1 40101 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_TX_SHIFT 4 40102 40103 /* XFI_BD1 :: user_prbs_control_0_register :: reserved1 [03:03] */ 40104 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED1_MASK 0x0008 40105 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED1_ALIGN 0 40106 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED1_BITS 1 40107 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED1_SHIFT 3 40108 40109 /* XFI_BD1 :: user_prbs_control_0_register :: prbs_sel_tx [02:00] */ 40110 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_TX_MASK 0x0007 40111 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_TX_ALIGN 0 40112 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_TX_BITS 3 40113 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_TX_SHIFT 0 40114 40115 40116 /**************************************************************************** 40117 * XFI_BD1 :: user_prbs_status_0_register 40118 */ 40119 /* XFI_BD1 :: user_prbs_status_0_register :: prbs_lock [15:15] */ 40120 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_LOCK_MASK 0x8000 40121 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_LOCK_ALIGN 0 40122 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_LOCK_BITS 1 40123 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_LOCK_SHIFT 15 40124 40125 /* XFI_BD1 :: user_prbs_status_0_register :: prbs_rx_errors [14:00] */ 40126 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_RX_ERRORS_MASK 0x7fff 40127 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_RX_ERRORS_ALIGN 0 40128 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_RX_ERRORS_BITS 15 40129 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_RX_ERRORS_SHIFT 0 40130 40131 40132 /**************************************************************************** 40133 * XFI_BD1 :: prbs_31_test_window_0_register 40134 */ 40135 /* XFI_BD1 :: prbs_31_test_window_0_register :: prbs31_win15_0 [15:00] */ 40136 #define XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTER_PRBS31_WIN15_0_MASK 0xffff 40137 #define XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTER_PRBS31_WIN15_0_ALIGN 0 40138 #define XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTER_PRBS31_WIN15_0_BITS 16 40139 #define XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTER_PRBS31_WIN15_0_SHIFT 0 40140 40141 40142 /**************************************************************************** 40143 * XFI_BD1 :: pattern_insertion_control_register 40144 */ 40145 /* XFI_BD1 :: pattern_insertion_control_register :: pattern_insertion_control [15:00] */ 40146 #define XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTER_PATTERN_INSERTION_CONTROL_MASK 0xffff 40147 #define XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTER_PATTERN_INSERTION_CONTROL_ALIGN 0 40148 #define XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTER_PATTERN_INSERTION_CONTROL_BITS 16 40149 #define XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTER_PATTERN_INSERTION_CONTROL_SHIFT 0 40150 40151 40152 /**************************************************************************** 40153 * Warpcore_USER_microBlk 40154 */ 40155 /**************************************************************************** 40156 * microBlk :: ramword 40157 */ 40158 /* microBlk :: ramword :: ram_count [15:00] */ 40159 #define MICROBLK_RAMWORD_RAM_COUNT_MASK 0xffff 40160 #define MICROBLK_RAMWORD_RAM_COUNT_ALIGN 0 40161 #define MICROBLK_RAMWORD_RAM_COUNT_BITS 16 40162 #define MICROBLK_RAMWORD_RAM_COUNT_SHIFT 0 40163 40164 40165 /**************************************************************************** 40166 * microBlk :: address 40167 */ 40168 /* microBlk :: address :: ram_address [15:00] */ 40169 #define MICROBLK_ADDRESS_RAM_ADDRESS_MASK 0xffff 40170 #define MICROBLK_ADDRESS_RAM_ADDRESS_ALIGN 0 40171 #define MICROBLK_ADDRESS_RAM_ADDRESS_BITS 16 40172 #define MICROBLK_ADDRESS_RAM_ADDRESS_SHIFT 0 40173 40174 40175 /**************************************************************************** 40176 * microBlk :: command 40177 */ 40178 /* microBlk :: command :: init_cmd [15:15] */ 40179 #define MICROBLK_COMMAND_INIT_CMD_MASK 0x8000 40180 #define MICROBLK_COMMAND_INIT_CMD_ALIGN 0 40181 #define MICROBLK_COMMAND_INIT_CMD_BITS 1 40182 #define MICROBLK_COMMAND_INIT_CMD_SHIFT 15 40183 40184 /* microBlk :: command :: uc_md_en_override [14:14] */ 40185 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_MASK 0x4000 40186 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_ALIGN 0 40187 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_BITS 1 40188 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_SHIFT 14 40189 40190 /* microBlk :: command :: uc_md_en_override_value [13:13] */ 40191 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_VALUE_MASK 0x2000 40192 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_VALUE_ALIGN 0 40193 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_VALUE_BITS 1 40194 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_VALUE_SHIFT 13 40195 40196 /* microBlk :: command :: mdio_ram_cs_force_val [12:12] */ 40197 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_VAL_MASK 0x1000 40198 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_VAL_ALIGN 0 40199 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_VAL_BITS 1 40200 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_VAL_SHIFT 12 40201 40202 /* microBlk :: command :: mdio_ram_cs_force [11:11] */ 40203 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_MASK 0x0800 40204 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_ALIGN 0 40205 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_BITS 1 40206 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_SHIFT 11 40207 40208 /* microBlk :: command :: mdio_autowakeup [10:10] */ 40209 #define MICROBLK_COMMAND_MDIO_AUTOWAKEUP_MASK 0x0400 40210 #define MICROBLK_COMMAND_MDIO_AUTOWAKEUP_ALIGN 0 40211 #define MICROBLK_COMMAND_MDIO_AUTOWAKEUP_BITS 1 40212 #define MICROBLK_COMMAND_MDIO_AUTOWAKEUP_SHIFT 10 40213 40214 /* microBlk :: command :: byte_mode [09:09] */ 40215 #define MICROBLK_COMMAND_BYTE_MODE_MASK 0x0200 40216 #define MICROBLK_COMMAND_BYTE_MODE_ALIGN 0 40217 #define MICROBLK_COMMAND_BYTE_MODE_BITS 1 40218 #define MICROBLK_COMMAND_BYTE_MODE_SHIFT 9 40219 40220 /* microBlk :: command :: refdiv4_en_int [08:08] */ 40221 #define MICROBLK_COMMAND_REFDIV4_EN_INT_MASK 0x0100 40222 #define MICROBLK_COMMAND_REFDIV4_EN_INT_ALIGN 0 40223 #define MICROBLK_COMMAND_REFDIV4_EN_INT_BITS 1 40224 #define MICROBLK_COMMAND_REFDIV4_EN_INT_SHIFT 8 40225 40226 /* microBlk :: command :: refdiv2_en_int [07:07] */ 40227 #define MICROBLK_COMMAND_REFDIV2_EN_INT_MASK 0x0080 40228 #define MICROBLK_COMMAND_REFDIV2_EN_INT_ALIGN 0 40229 #define MICROBLK_COMMAND_REFDIV2_EN_INT_BITS 1 40230 #define MICROBLK_COMMAND_REFDIV2_EN_INT_SHIFT 7 40231 40232 /* microBlk :: command :: mdio_disable_ucclk [06:06] */ 40233 #define MICROBLK_COMMAND_MDIO_DISABLE_UCCLK_MASK 0x0040 40234 #define MICROBLK_COMMAND_MDIO_DISABLE_UCCLK_ALIGN 0 40235 #define MICROBLK_COMMAND_MDIO_DISABLE_UCCLK_BITS 1 40236 #define MICROBLK_COMMAND_MDIO_DISABLE_UCCLK_SHIFT 6 40237 40238 /* microBlk :: command :: reserved_for_eco0 [05:05] */ 40239 #define MICROBLK_COMMAND_RESERVED_FOR_ECO0_MASK 0x0020 40240 #define MICROBLK_COMMAND_RESERVED_FOR_ECO0_ALIGN 0 40241 #define MICROBLK_COMMAND_RESERVED_FOR_ECO0_BITS 1 40242 #define MICROBLK_COMMAND_RESERVED_FOR_ECO0_SHIFT 5 40243 40244 /* microBlk :: command :: mdio_uC_reset_n [04:04] */ 40245 #define MICROBLK_COMMAND_MDIO_UC_RESET_N_MASK 0x0010 40246 #define MICROBLK_COMMAND_MDIO_UC_RESET_N_ALIGN 0 40247 #define MICROBLK_COMMAND_MDIO_UC_RESET_N_BITS 1 40248 #define MICROBLK_COMMAND_MDIO_UC_RESET_N_SHIFT 4 40249 40250 /* microBlk :: command :: write [03:03] */ 40251 #define MICROBLK_COMMAND_WRITE_MASK 0x0008 40252 #define MICROBLK_COMMAND_WRITE_ALIGN 0 40253 #define MICROBLK_COMMAND_WRITE_BITS 1 40254 #define MICROBLK_COMMAND_WRITE_SHIFT 3 40255 40256 /* microBlk :: command :: read [02:02] */ 40257 #define MICROBLK_COMMAND_READ_MASK 0x0004 40258 #define MICROBLK_COMMAND_READ_ALIGN 0 40259 #define MICROBLK_COMMAND_READ_BITS 1 40260 #define MICROBLK_COMMAND_READ_SHIFT 2 40261 40262 /* microBlk :: command :: stop [01:01] */ 40263 #define MICROBLK_COMMAND_STOP_MASK 0x0002 40264 #define MICROBLK_COMMAND_STOP_ALIGN 0 40265 #define MICROBLK_COMMAND_STOP_BITS 1 40266 #define MICROBLK_COMMAND_STOP_SHIFT 1 40267 40268 /* microBlk :: command :: run [00:00] */ 40269 #define MICROBLK_COMMAND_RUN_MASK 0x0001 40270 #define MICROBLK_COMMAND_RUN_ALIGN 0 40271 #define MICROBLK_COMMAND_RUN_BITS 1 40272 #define MICROBLK_COMMAND_RUN_SHIFT 0 40273 40274 40275 /**************************************************************************** 40276 * microBlk :: wrdata 40277 */ 40278 /* microBlk :: wrdata :: wrdata [15:00] */ 40279 #define MICROBLK_WRDATA_WRDATA_MASK 0xffff 40280 #define MICROBLK_WRDATA_WRDATA_ALIGN 0 40281 #define MICROBLK_WRDATA_WRDATA_BITS 16 40282 #define MICROBLK_WRDATA_WRDATA_SHIFT 0 40283 40284 40285 /**************************************************************************** 40286 * microBlk :: rddata 40287 */ 40288 /* microBlk :: rddata :: rddata [15:00] */ 40289 #define MICROBLK_RDDATA_RDDATA_MASK 0xffff 40290 #define MICROBLK_RDDATA_RDDATA_ALIGN 0 40291 #define MICROBLK_RDDATA_RDDATA_BITS 16 40292 #define MICROBLK_RDDATA_RDDATA_SHIFT 0 40293 40294 40295 /**************************************************************************** 40296 * microBlk :: download_status 40297 */ 40298 /* microBlk :: download_status :: init_done [15:15] */ 40299 #define MICROBLK_DOWNLOAD_STATUS_INIT_DONE_MASK 0x8000 40300 #define MICROBLK_DOWNLOAD_STATUS_INIT_DONE_ALIGN 0 40301 #define MICROBLK_DOWNLOAD_STATUS_INIT_DONE_BITS 1 40302 #define MICROBLK_DOWNLOAD_STATUS_INIT_DONE_SHIFT 15 40303 40304 /* microBlk :: download_status :: reserved0 [14:06] */ 40305 #define MICROBLK_DOWNLOAD_STATUS_RESERVED0_MASK 0x7fc0 40306 #define MICROBLK_DOWNLOAD_STATUS_RESERVED0_ALIGN 0 40307 #define MICROBLK_DOWNLOAD_STATUS_RESERVED0_BITS 9 40308 #define MICROBLK_DOWNLOAD_STATUS_RESERVED0_SHIFT 6 40309 40310 /* microBlk :: download_status :: FSM [05:02] */ 40311 #define MICROBLK_DOWNLOAD_STATUS_FSM_MASK 0x003c 40312 #define MICROBLK_DOWNLOAD_STATUS_FSM_ALIGN 0 40313 #define MICROBLK_DOWNLOAD_STATUS_FSM_BITS 4 40314 #define MICROBLK_DOWNLOAD_STATUS_FSM_SHIFT 2 40315 40316 /* microBlk :: download_status :: ERR1 [01:01] */ 40317 #define MICROBLK_DOWNLOAD_STATUS_ERR1_MASK 0x0002 40318 #define MICROBLK_DOWNLOAD_STATUS_ERR1_ALIGN 0 40319 #define MICROBLK_DOWNLOAD_STATUS_ERR1_BITS 1 40320 #define MICROBLK_DOWNLOAD_STATUS_ERR1_SHIFT 1 40321 40322 /* microBlk :: download_status :: ERR0 [00:00] */ 40323 #define MICROBLK_DOWNLOAD_STATUS_ERR0_MASK 0x0001 40324 #define MICROBLK_DOWNLOAD_STATUS_ERR0_ALIGN 0 40325 #define MICROBLK_DOWNLOAD_STATUS_ERR0_BITS 1 40326 #define MICROBLK_DOWNLOAD_STATUS_ERR0_SHIFT 0 40327 40328 40329 /**************************************************************************** 40330 * microBlk :: sfr_status 40331 */ 40332 /* union - case ecc_error_counters [15:00] */ 40333 /* microBlk :: sfr_status :: ecc_error_counters [15:00] */ 40334 #define MICROBLK_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_MASK 0xffff 40335 #define MICROBLK_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_ALIGN 0 40336 #define MICROBLK_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_BITS 16 40337 #define MICROBLK_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_SHIFT 0 40338 40339 40340 /* union - case dw8051_to_pcb_fsm_L [15:00] */ 40341 /* microBlk :: sfr_status :: dw8051_to_pcb_fsm_L [15:00] */ 40342 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_MASK 0xffff 40343 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_ALIGN 0 40344 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_BITS 16 40345 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_SHIFT 0 40346 40347 40348 /* union - case dw8051_to_pcb_fsm_U [15:00] */ 40349 /* microBlk :: sfr_status :: dw8051_to_pcb_fsm_U [15:00] */ 40350 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_MASK 0xffff 40351 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_ALIGN 0 40352 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_BITS 16 40353 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_SHIFT 0 40354 40355 40356 40357 /**************************************************************************** 40358 * microBlk :: command4 40359 */ 40360 /* microBlk :: command4 :: reserved_for_eco0 [15:06] */ 40361 #define MICROBLK_COMMAND4_RESERVED_FOR_ECO0_MASK 0xffc0 40362 #define MICROBLK_COMMAND4_RESERVED_FOR_ECO0_ALIGN 0 40363 #define MICROBLK_COMMAND4_RESERVED_FOR_ECO0_BITS 10 40364 #define MICROBLK_COMMAND4_RESERVED_FOR_ECO0_SHIFT 6 40365 40366 /* microBlk :: command4 :: mdio_eitu_int5 [05:05] */ 40367 #define MICROBLK_COMMAND4_MDIO_EITU_INT5_MASK 0x0020 40368 #define MICROBLK_COMMAND4_MDIO_EITU_INT5_ALIGN 0 40369 #define MICROBLK_COMMAND4_MDIO_EITU_INT5_BITS 1 40370 #define MICROBLK_COMMAND4_MDIO_EITU_INT5_SHIFT 5 40371 40372 /* microBlk :: command4 :: mdio_eitu_int4 [04:04] */ 40373 #define MICROBLK_COMMAND4_MDIO_EITU_INT4_MASK 0x0010 40374 #define MICROBLK_COMMAND4_MDIO_EITU_INT4_ALIGN 0 40375 #define MICROBLK_COMMAND4_MDIO_EITU_INT4_BITS 1 40376 #define MICROBLK_COMMAND4_MDIO_EITU_INT4_SHIFT 4 40377 40378 /* microBlk :: command4 :: mdio_eitu_int3 [03:03] */ 40379 #define MICROBLK_COMMAND4_MDIO_EITU_INT3_MASK 0x0008 40380 #define MICROBLK_COMMAND4_MDIO_EITU_INT3_ALIGN 0 40381 #define MICROBLK_COMMAND4_MDIO_EITU_INT3_BITS 1 40382 #define MICROBLK_COMMAND4_MDIO_EITU_INT3_SHIFT 3 40383 40384 /* microBlk :: command4 :: mdio_eitu_int2 [02:02] */ 40385 #define MICROBLK_COMMAND4_MDIO_EITU_INT2_MASK 0x0004 40386 #define MICROBLK_COMMAND4_MDIO_EITU_INT2_ALIGN 0 40387 #define MICROBLK_COMMAND4_MDIO_EITU_INT2_BITS 1 40388 #define MICROBLK_COMMAND4_MDIO_EITU_INT2_SHIFT 2 40389 40390 /* microBlk :: command4 :: mdio_eitu_int1 [01:01] */ 40391 #define MICROBLK_COMMAND4_MDIO_EITU_INT1_MASK 0x0002 40392 #define MICROBLK_COMMAND4_MDIO_EITU_INT1_ALIGN 0 40393 #define MICROBLK_COMMAND4_MDIO_EITU_INT1_BITS 1 40394 #define MICROBLK_COMMAND4_MDIO_EITU_INT1_SHIFT 1 40395 40396 /* microBlk :: command4 :: mdio_eitu_int0 [00:00] */ 40397 #define MICROBLK_COMMAND4_MDIO_EITU_INT0_MASK 0x0001 40398 #define MICROBLK_COMMAND4_MDIO_EITU_INT0_ALIGN 0 40399 #define MICROBLK_COMMAND4_MDIO_EITU_INT0_BITS 1 40400 #define MICROBLK_COMMAND4_MDIO_EITU_INT0_SHIFT 0 40401 40402 40403 /**************************************************************************** 40404 * microBlk :: mdio_uC_mailbox 40405 */ 40406 /* microBlk :: mdio_uC_mailbox :: mdio_uC_mailbox [15:00] */ 40407 #define MICROBLK_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_MASK 0xffff 40408 #define MICROBLK_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_ALIGN 0 40409 #define MICROBLK_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_BITS 16 40410 #define MICROBLK_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_SHIFT 0 40411 40412 40413 /**************************************************************************** 40414 * microBlk :: uC_mdio_mailbox 40415 */ 40416 /* microBlk :: uC_mdio_mailbox :: uC_mdio_mailbox [15:00] */ 40417 #define MICROBLK_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_MASK 0xffff 40418 #define MICROBLK_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_ALIGN 0 40419 #define MICROBLK_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_BITS 16 40420 #define MICROBLK_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_SHIFT 0 40421 40422 40423 /**************************************************************************** 40424 * microBlk :: command2 40425 */ 40426 /* microBlk :: command2 :: mdio_to_8051_reset [15:15] */ 40427 #define MICROBLK_COMMAND2_MDIO_TO_8051_RESET_MASK 0x8000 40428 #define MICROBLK_COMMAND2_MDIO_TO_8051_RESET_ALIGN 0 40429 #define MICROBLK_COMMAND2_MDIO_TO_8051_RESET_BITS 1 40430 #define MICROBLK_COMMAND2_MDIO_TO_8051_RESET_SHIFT 15 40431 40432 /* microBlk :: command2 :: m8051_to_pcb_reset [14:14] */ 40433 #define MICROBLK_COMMAND2_M8051_TO_PCB_RESET_MASK 0x4000 40434 #define MICROBLK_COMMAND2_M8051_TO_PCB_RESET_ALIGN 0 40435 #define MICROBLK_COMMAND2_M8051_TO_PCB_RESET_BITS 1 40436 #define MICROBLK_COMMAND2_M8051_TO_PCB_RESET_SHIFT 14 40437 40438 /* microBlk :: command2 :: firmware_reset_disable [13:13] */ 40439 #define MICROBLK_COMMAND2_FIRMWARE_RESET_DISABLE_MASK 0x2000 40440 #define MICROBLK_COMMAND2_FIRMWARE_RESET_DISABLE_ALIGN 0 40441 #define MICROBLK_COMMAND2_FIRMWARE_RESET_DISABLE_BITS 1 40442 #define MICROBLK_COMMAND2_FIRMWARE_RESET_DISABLE_SHIFT 13 40443 40444 /* microBlk :: command2 :: zero_rom_dataout [12:12] */ 40445 #define MICROBLK_COMMAND2_ZERO_ROM_DATAOUT_MASK 0x1000 40446 #define MICROBLK_COMMAND2_ZERO_ROM_DATAOUT_ALIGN 0 40447 #define MICROBLK_COMMAND2_ZERO_ROM_DATAOUT_BITS 1 40448 #define MICROBLK_COMMAND2_ZERO_ROM_DATAOUT_SHIFT 12 40449 40450 /* microBlk :: command2 :: reserved_for_eco0 [11:10] */ 40451 #define MICROBLK_COMMAND2_RESERVED_FOR_ECO0_MASK 0x0c00 40452 #define MICROBLK_COMMAND2_RESERVED_FOR_ECO0_ALIGN 0 40453 #define MICROBLK_COMMAND2_RESERVED_FOR_ECO0_BITS 2 40454 #define MICROBLK_COMMAND2_RESERVED_FOR_ECO0_SHIFT 10 40455 40456 /* microBlk :: command2 :: timer_mux_sel [09:08] */ 40457 #define MICROBLK_COMMAND2_TIMER_MUX_SEL_MASK 0x0300 40458 #define MICROBLK_COMMAND2_TIMER_MUX_SEL_ALIGN 0 40459 #define MICROBLK_COMMAND2_TIMER_MUX_SEL_BITS 2 40460 #define MICROBLK_COMMAND2_TIMER_MUX_SEL_SHIFT 8 40461 40462 /* microBlk :: command2 :: wdog_disable [07:07] */ 40463 #define MICROBLK_COMMAND2_WDOG_DISABLE_MASK 0x0080 40464 #define MICROBLK_COMMAND2_WDOG_DISABLE_ALIGN 0 40465 #define MICROBLK_COMMAND2_WDOG_DISABLE_BITS 1 40466 #define MICROBLK_COMMAND2_WDOG_DISABLE_SHIFT 7 40467 40468 /* microBlk :: command2 :: refdiv4_tmr_en [06:06] */ 40469 #define MICROBLK_COMMAND2_REFDIV4_TMR_EN_MASK 0x0040 40470 #define MICROBLK_COMMAND2_REFDIV4_TMR_EN_ALIGN 0 40471 #define MICROBLK_COMMAND2_REFDIV4_TMR_EN_BITS 1 40472 #define MICROBLK_COMMAND2_REFDIV4_TMR_EN_SHIFT 6 40473 40474 /* microBlk :: command2 :: refdiv2_tmr_en [05:05] */ 40475 #define MICROBLK_COMMAND2_REFDIV2_TMR_EN_MASK 0x0020 40476 #define MICROBLK_COMMAND2_REFDIV2_TMR_EN_ALIGN 0 40477 #define MICROBLK_COMMAND2_REFDIV2_TMR_EN_BITS 1 40478 #define MICROBLK_COMMAND2_REFDIV2_TMR_EN_SHIFT 5 40479 40480 /* microBlk :: command2 :: wdog_en [04:04] */ 40481 #define MICROBLK_COMMAND2_WDOG_EN_MASK 0x0010 40482 #define MICROBLK_COMMAND2_WDOG_EN_ALIGN 0 40483 #define MICROBLK_COMMAND2_WDOG_EN_BITS 1 40484 #define MICROBLK_COMMAND2_WDOG_EN_SHIFT 4 40485 40486 /* microBlk :: command2 :: tmr_en [03:00] */ 40487 #define MICROBLK_COMMAND2_TMR_EN_MASK 0x000f 40488 #define MICROBLK_COMMAND2_TMR_EN_ALIGN 0 40489 #define MICROBLK_COMMAND2_TMR_EN_BITS 4 40490 #define MICROBLK_COMMAND2_TMR_EN_SHIFT 0 40491 40492 40493 /**************************************************************************** 40494 * microBlk :: wdog_evnt_cnt 40495 */ 40496 /* microBlk :: wdog_evnt_cnt :: wdog_evnt_cnt [15:00] */ 40497 #define MICROBLK_WDOG_EVNT_CNT_WDOG_EVNT_CNT_MASK 0xffff 40498 #define MICROBLK_WDOG_EVNT_CNT_WDOG_EVNT_CNT_ALIGN 0 40499 #define MICROBLK_WDOG_EVNT_CNT_WDOG_EVNT_CNT_BITS 16 40500 #define MICROBLK_WDOG_EVNT_CNT_WDOG_EVNT_CNT_SHIFT 0 40501 40502 40503 /**************************************************************************** 40504 * microBlk :: command3 40505 */ 40506 /* microBlk :: command3 :: gen_status_sel [15:12] */ 40507 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_MASK 0xf000 40508 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_ALIGN 0 40509 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_BITS 4 40510 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_SHIFT 12 40511 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_ecc_error_counters 0 40512 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_dw8051_to_pcb_fsm_L 1 40513 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_dw8051_to_pcb_fsm_U 2 40514 40515 /* microBlk :: command3 :: disable_ecc [11:11] */ 40516 #define MICROBLK_COMMAND3_DISABLE_ECC_MASK 0x0800 40517 #define MICROBLK_COMMAND3_DISABLE_ECC_ALIGN 0 40518 #define MICROBLK_COMMAND3_DISABLE_ECC_BITS 1 40519 #define MICROBLK_COMMAND3_DISABLE_ECC_SHIFT 11 40520 40521 /* microBlk :: command3 :: out_staging_flop_bypass [10:10] */ 40522 #define MICROBLK_COMMAND3_OUT_STAGING_FLOP_BYPASS_MASK 0x0400 40523 #define MICROBLK_COMMAND3_OUT_STAGING_FLOP_BYPASS_ALIGN 0 40524 #define MICROBLK_COMMAND3_OUT_STAGING_FLOP_BYPASS_BITS 1 40525 #define MICROBLK_COMMAND3_OUT_STAGING_FLOP_BYPASS_SHIFT 10 40526 40527 /* microBlk :: command3 :: tm [09:05] */ 40528 #define MICROBLK_COMMAND3_TM_MASK 0x03e0 40529 #define MICROBLK_COMMAND3_TM_ALIGN 0 40530 #define MICROBLK_COMMAND3_TM_BITS 5 40531 #define MICROBLK_COMMAND3_TM_SHIFT 5 40532 40533 /* microBlk :: command3 :: pm_override_value [04:04] */ 40534 #define MICROBLK_COMMAND3_PM_OVERRIDE_VALUE_MASK 0x0010 40535 #define MICROBLK_COMMAND3_PM_OVERRIDE_VALUE_ALIGN 0 40536 #define MICROBLK_COMMAND3_PM_OVERRIDE_VALUE_BITS 1 40537 #define MICROBLK_COMMAND3_PM_OVERRIDE_VALUE_SHIFT 4 40538 40539 /* microBlk :: command3 :: enable_pm_override [03:03] */ 40540 #define MICROBLK_COMMAND3_ENABLE_PM_OVERRIDE_MASK 0x0008 40541 #define MICROBLK_COMMAND3_ENABLE_PM_OVERRIDE_ALIGN 0 40542 #define MICROBLK_COMMAND3_ENABLE_PM_OVERRIDE_BITS 1 40543 #define MICROBLK_COMMAND3_ENABLE_PM_OVERRIDE_SHIFT 3 40544 40545 /* microBlk :: command3 :: in_staging_flop_bypass [02:02] */ 40546 #define MICROBLK_COMMAND3_IN_STAGING_FLOP_BYPASS_MASK 0x0004 40547 #define MICROBLK_COMMAND3_IN_STAGING_FLOP_BYPASS_ALIGN 0 40548 #define MICROBLK_COMMAND3_IN_STAGING_FLOP_BYPASS_BITS 1 40549 #define MICROBLK_COMMAND3_IN_STAGING_FLOP_BYPASS_SHIFT 2 40550 40551 /* microBlk :: command3 :: ext_clk_enable [01:01] */ 40552 #define MICROBLK_COMMAND3_EXT_CLK_ENABLE_MASK 0x0002 40553 #define MICROBLK_COMMAND3_EXT_CLK_ENABLE_ALIGN 0 40554 #define MICROBLK_COMMAND3_EXT_CLK_ENABLE_BITS 1 40555 #define MICROBLK_COMMAND3_EXT_CLK_ENABLE_SHIFT 1 40556 40557 /* microBlk :: command3 :: ext_mem_enable [00:00] */ 40558 #define MICROBLK_COMMAND3_EXT_MEM_ENABLE_MASK 0x0001 40559 #define MICROBLK_COMMAND3_EXT_MEM_ENABLE_ALIGN 0 40560 #define MICROBLK_COMMAND3_EXT_MEM_ENABLE_BITS 1 40561 #define MICROBLK_COMMAND3_EXT_MEM_ENABLE_SHIFT 0 40562 40563 40564 /**************************************************************************** 40565 * microBlk :: timer_lower16 40566 */ 40567 /* microBlk :: timer_lower16 :: timer_lower16bits [15:00] */ 40568 #define MICROBLK_TIMER_LOWER16_TIMER_LOWER16BITS_MASK 0xffff 40569 #define MICROBLK_TIMER_LOWER16_TIMER_LOWER16BITS_ALIGN 0 40570 #define MICROBLK_TIMER_LOWER16_TIMER_LOWER16BITS_BITS 16 40571 #define MICROBLK_TIMER_LOWER16_TIMER_LOWER16BITS_SHIFT 0 40572 40573 40574 /**************************************************************************** 40575 * microBlk :: timer_upper16 40576 */ 40577 /* microBlk :: timer_upper16 :: timer_upper16bits [15:00] */ 40578 #define MICROBLK_TIMER_UPPER16_TIMER_UPPER16BITS_MASK 0xffff 40579 #define MICROBLK_TIMER_UPPER16_TIMER_UPPER16BITS_ALIGN 0 40580 #define MICROBLK_TIMER_UPPER16_TIMER_UPPER16BITS_BITS 16 40581 #define MICROBLK_TIMER_UPPER16_TIMER_UPPER16BITS_SHIFT 0 40582 40583 40584 /**************************************************************************** 40585 * Warpcore_USER_aerBlk 40586 */ 40587 /**************************************************************************** 40588 * aerBlk :: aer 40589 */ 40590 /* aerBlk :: aer :: MMD_deviceType [15:11] */ 40591 #define AERBLK_AER_MMD_DEVICETYPE_MASK 0xf800 40592 #define AERBLK_AER_MMD_DEVICETYPE_ALIGN 0 40593 #define AERBLK_AER_MMD_DEVICETYPE_BITS 5 40594 #define AERBLK_AER_MMD_DEVICETYPE_SHIFT 11 40595 #define AERBLK_AER_MMD_DEVICETYPE_combo_core 0 40596 #define AERBLK_AER_MMD_DEVICETYPE_PMA_PMD 1 40597 #define AERBLK_AER_MMD_DEVICETYPE_PCS 3 40598 #define AERBLK_AER_MMD_DEVICETYPE_PHY 4 40599 #define AERBLK_AER_MMD_DEVICETYPE_DTE 5 40600 #define AERBLK_AER_MMD_DEVICETYPE_CL73_AN 7 40601 40602 /* aerBlk :: aer :: MMD_port [10:00] */ 40603 #define AERBLK_AER_MMD_PORT_MASK 0x07ff 40604 #define AERBLK_AER_MMD_PORT_ALIGN 0 40605 #define AERBLK_AER_MMD_PORT_BITS 11 40606 #define AERBLK_AER_MMD_PORT_SHIFT 0 40607 #define AERBLK_AER_MMD_PORT_ln0 0 40608 #define AERBLK_AER_MMD_PORT_ln1 1 40609 #define AERBLK_AER_MMD_PORT_ln2 2 40610 #define AERBLK_AER_MMD_PORT_ln3 3 40611 #define AERBLK_AER_MMD_PORT_BCST 511 40612 40613 #ifdef BCM_TRIUMPH3_SUPPORT 40614 /* aerBlk :: aer :: ANALOG_TX [16:00] */ 40615 #define AERBLK_AER_ANALOG_TX_MASK 0xffff 40616 #define AERBLK_AER_ANALOG_TX_ALIGN 0 40617 #define AERBLK_AER_ANALOG_TX_BITS 16 40618 #define AERBLK_AER_ANALOG_TX_SHIFT 0 40619 #endif 40620 /**************************************************************************** 40621 * Warpcore_USER_Combo_IEEE0 40622 */ 40623 /**************************************************************************** 40624 * Combo_IEEE0 :: MIICntl 40625 */ 40626 /* Combo_IEEE0 :: MIICntl :: rst_hw [15:15] */ 40627 #define COMBO_IEEE0_MIICNTL_RST_HW_MASK 0x8000 40628 #define COMBO_IEEE0_MIICNTL_RST_HW_ALIGN 0 40629 #define COMBO_IEEE0_MIICNTL_RST_HW_BITS 1 40630 #define COMBO_IEEE0_MIICNTL_RST_HW_SHIFT 15 40631 40632 /* Combo_IEEE0 :: MIICntl :: gloopback [14:14] */ 40633 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_MASK 0x4000 40634 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_ALIGN 0 40635 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_BITS 1 40636 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_SHIFT 14 40637 40638 /* Combo_IEEE0 :: MIICntl :: manual_speed0 [13:13] */ 40639 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_MASK 0x2000 40640 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_ALIGN 0 40641 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_BITS 1 40642 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_SHIFT 13 40643 40644 /* Combo_IEEE0 :: MIICntl :: autoneg_enable [12:12] */ 40645 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_MASK 0x1000 40646 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_ALIGN 0 40647 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_BITS 1 40648 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_SHIFT 12 40649 40650 /* Combo_IEEE0 :: MIICntl :: pwrdwn_sw [11:11] */ 40651 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_MASK 0x0800 40652 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_ALIGN 0 40653 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_BITS 1 40654 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_SHIFT 11 40655 40656 /* Combo_IEEE0 :: MIICntl :: reserved0 [10:10] */ 40657 #define COMBO_IEEE0_MIICNTL_RESERVED0_MASK 0x0400 40658 #define COMBO_IEEE0_MIICNTL_RESERVED0_ALIGN 0 40659 #define COMBO_IEEE0_MIICNTL_RESERVED0_BITS 1 40660 #define COMBO_IEEE0_MIICNTL_RESERVED0_SHIFT 10 40661 40662 /* Combo_IEEE0 :: MIICntl :: restart_autoneg [09:09] */ 40663 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_MASK 0x0200 40664 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_ALIGN 0 40665 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_BITS 1 40666 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_SHIFT 9 40667 40668 /* Combo_IEEE0 :: MIICntl :: full_duplex [08:08] */ 40669 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_MASK 0x0100 40670 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_ALIGN 0 40671 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_BITS 1 40672 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_SHIFT 8 40673 40674 /* Combo_IEEE0 :: MIICntl :: collision_test_en [07:07] */ 40675 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_MASK 0x0080 40676 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_ALIGN 0 40677 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_BITS 1 40678 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_SHIFT 7 40679 40680 /* Combo_IEEE0 :: MIICntl :: manual_speed1 [06:06] */ 40681 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_MASK 0x0040 40682 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_ALIGN 0 40683 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_BITS 1 40684 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_SHIFT 6 40685 40686 /* Combo_IEEE0 :: MIICntl :: reserved1 [05:00] */ 40687 #define COMBO_IEEE0_MIICNTL_RESERVED1_MASK 0x003f 40688 #define COMBO_IEEE0_MIICNTL_RESERVED1_ALIGN 0 40689 #define COMBO_IEEE0_MIICNTL_RESERVED1_BITS 6 40690 #define COMBO_IEEE0_MIICNTL_RESERVED1_SHIFT 0 40691 40692 40693 /**************************************************************************** 40694 * Combo_IEEE0 :: MIIStat 40695 */ 40696 /* Combo_IEEE0 :: MIIStat :: s100BASE_T4_capable [15:15] */ 40697 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_MASK 0x8000 40698 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN 0 40699 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_BITS 1 40700 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT 15 40701 40702 /* Combo_IEEE0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */ 40703 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000 40704 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0 40705 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1 40706 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14 40707 40708 /* Combo_IEEE0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */ 40709 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000 40710 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0 40711 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1 40712 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13 40713 40714 /* Combo_IEEE0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */ 40715 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x1000 40716 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0 40717 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS 1 40718 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12 40719 40720 /* Combo_IEEE0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */ 40721 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x0800 40722 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0 40723 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS 1 40724 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11 40725 40726 /* Combo_IEEE0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */ 40727 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400 40728 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0 40729 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1 40730 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10 40731 40732 /* Combo_IEEE0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */ 40733 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200 40734 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0 40735 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1 40736 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9 40737 40738 /* Combo_IEEE0 :: MIIStat :: extended_status [08:08] */ 40739 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_MASK 0x0100 40740 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_ALIGN 0 40741 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_BITS 1 40742 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_SHIFT 8 40743 40744 /* Combo_IEEE0 :: MIIStat :: reserved0 [07:07] */ 40745 #define COMBO_IEEE0_MIISTAT_RESERVED0_MASK 0x0080 40746 #define COMBO_IEEE0_MIISTAT_RESERVED0_ALIGN 0 40747 #define COMBO_IEEE0_MIISTAT_RESERVED0_BITS 1 40748 #define COMBO_IEEE0_MIISTAT_RESERVED0_SHIFT 7 40749 40750 /* Combo_IEEE0 :: MIIStat :: mf_preamble_supression [06:06] */ 40751 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK 0x0040 40752 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN 0 40753 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS 1 40754 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT 6 40755 40756 /* Combo_IEEE0 :: MIIStat :: autoneg_complete [05:05] */ 40757 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_MASK 0x0020 40758 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_ALIGN 0 40759 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_BITS 1 40760 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_SHIFT 5 40761 40762 /* Combo_IEEE0 :: MIIStat :: remote_fault [04:04] */ 40763 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_MASK 0x0010 40764 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_ALIGN 0 40765 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_BITS 1 40766 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_SHIFT 4 40767 40768 /* Combo_IEEE0 :: MIIStat :: autoneg_ability [03:03] */ 40769 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_MASK 0x0008 40770 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_ALIGN 0 40771 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_BITS 1 40772 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_SHIFT 3 40773 40774 /* Combo_IEEE0 :: MIIStat :: link_status [02:02] */ 40775 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_MASK 0x0004 40776 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_ALIGN 0 40777 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_BITS 1 40778 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_SHIFT 2 40779 40780 /* Combo_IEEE0 :: MIIStat :: jabber_detect [01:01] */ 40781 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_MASK 0x0002 40782 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_ALIGN 0 40783 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_BITS 1 40784 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_SHIFT 1 40785 40786 /* Combo_IEEE0 :: MIIStat :: extended_capability [00:00] */ 40787 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_MASK 0x0001 40788 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_ALIGN 0 40789 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_BITS 1 40790 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_SHIFT 0 40791 40792 40793 /**************************************************************************** 40794 * Combo_IEEE0 :: Id1 40795 */ 40796 /* Combo_IEEE0 :: Id1 :: regid [15:00] */ 40797 #define COMBO_IEEE0_ID1_REGID_MASK 0xffff 40798 #define COMBO_IEEE0_ID1_REGID_ALIGN 0 40799 #define COMBO_IEEE0_ID1_REGID_BITS 16 40800 #define COMBO_IEEE0_ID1_REGID_SHIFT 0 40801 40802 40803 /**************************************************************************** 40804 * Combo_IEEE0 :: Id2 40805 */ 40806 /* Combo_IEEE0 :: Id2 :: regid [15:00] */ 40807 #define COMBO_IEEE0_ID2_REGID_MASK 0xffff 40808 #define COMBO_IEEE0_ID2_REGID_ALIGN 0 40809 #define COMBO_IEEE0_ID2_REGID_BITS 16 40810 #define COMBO_IEEE0_ID2_REGID_SHIFT 0 40811 40812 40813 /**************************************************************************** 40814 * Combo_IEEE0 :: AutoNegAdv 40815 */ 40816 /* Combo_IEEE0 :: AutoNegAdv :: next_page [15:15] */ 40817 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_MASK 0x8000 40818 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_ALIGN 0 40819 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_BITS 1 40820 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_SHIFT 15 40821 40822 /* Combo_IEEE0 :: AutoNegAdv :: reserved0 [14:14] */ 40823 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_MASK 0x4000 40824 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_ALIGN 0 40825 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_BITS 1 40826 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_SHIFT 14 40827 40828 /* Combo_IEEE0 :: AutoNegAdv :: remote_fault [13:12] */ 40829 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_MASK 0x3000 40830 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_ALIGN 0 40831 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_BITS 2 40832 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_SHIFT 12 40833 40834 /* Combo_IEEE0 :: AutoNegAdv :: reserved1 [11:09] */ 40835 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_MASK 0x0e00 40836 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_ALIGN 0 40837 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_BITS 3 40838 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_SHIFT 9 40839 40840 /* Combo_IEEE0 :: AutoNegAdv :: pause [08:07] */ 40841 #define COMBO_IEEE0_AUTONEGADV_PAUSE_MASK 0x0180 40842 #define COMBO_IEEE0_AUTONEGADV_PAUSE_ALIGN 0 40843 #define COMBO_IEEE0_AUTONEGADV_PAUSE_BITS 2 40844 #define COMBO_IEEE0_AUTONEGADV_PAUSE_SHIFT 7 40845 40846 /* Combo_IEEE0 :: AutoNegAdv :: half_duplex [06:06] */ 40847 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_MASK 0x0040 40848 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_ALIGN 0 40849 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_BITS 1 40850 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_SHIFT 6 40851 40852 /* Combo_IEEE0 :: AutoNegAdv :: full_duplex [05:05] */ 40853 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_MASK 0x0020 40854 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_ALIGN 0 40855 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_BITS 1 40856 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_SHIFT 5 40857 40858 /* Combo_IEEE0 :: AutoNegAdv :: reserved2 [04:00] */ 40859 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_MASK 0x001f 40860 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_ALIGN 0 40861 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_BITS 5 40862 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_SHIFT 0 40863 40864 40865 /**************************************************************************** 40866 * Combo_IEEE0 :: AutoNegLPAbil 40867 */ 40868 /* Combo_IEEE0 :: AutoNegLPAbil :: next_page [15:15] */ 40869 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_MASK 0x8000 40870 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_ALIGN 0 40871 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_BITS 1 40872 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_SHIFT 15 40873 40874 /* Combo_IEEE0 :: AutoNegLPAbil :: acknowledge [14:14] */ 40875 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_MASK 0x4000 40876 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN 0 40877 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_BITS 1 40878 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT 14 40879 40880 /* Combo_IEEE0 :: AutoNegLPAbil :: remote_fault [13:12] */ 40881 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_MASK 0x3000 40882 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN 0 40883 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_BITS 2 40884 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT 12 40885 40886 /* Combo_IEEE0 :: AutoNegLPAbil :: reserved0 [11:09] */ 40887 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_MASK 0x0e00 40888 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_ALIGN 0 40889 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_BITS 3 40890 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_SHIFT 9 40891 40892 /* Combo_IEEE0 :: AutoNegLPAbil :: pause [08:07] */ 40893 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_MASK 0x0180 40894 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_ALIGN 0 40895 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_BITS 2 40896 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_SHIFT 7 40897 40898 /* Combo_IEEE0 :: AutoNegLPAbil :: half_duplex [06:06] */ 40899 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_MASK 0x0040 40900 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN 0 40901 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_BITS 1 40902 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT 6 40903 40904 /* Combo_IEEE0 :: AutoNegLPAbil :: full_duplex [05:05] */ 40905 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_MASK 0x0020 40906 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN 0 40907 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_BITS 1 40908 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT 5 40909 40910 /* Combo_IEEE0 :: AutoNegLPAbil :: reserved1 [04:01] */ 40911 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_MASK 0x001e 40912 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_ALIGN 0 40913 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_BITS 4 40914 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_SHIFT 1 40915 40916 /* Combo_IEEE0 :: AutoNegLPAbil :: sgmii_mode [00:00] */ 40917 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_MASK 0x0001 40918 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_ALIGN 0 40919 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_BITS 1 40920 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_SHIFT 0 40921 40922 40923 /**************************************************************************** 40924 * Combo_IEEE0 :: AutoNegExp 40925 */ 40926 /* Combo_IEEE0 :: AutoNegExp :: reserved0 [15:03] */ 40927 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_MASK 0xfff8 40928 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_ALIGN 0 40929 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_BITS 13 40930 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_SHIFT 3 40931 40932 /* Combo_IEEE0 :: AutoNegExp :: next_page_ability [02:02] */ 40933 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK 0x0004 40934 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN 0 40935 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS 1 40936 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT 2 40937 40938 /* Combo_IEEE0 :: AutoNegExp :: page_received [01:01] */ 40939 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_MASK 0x0002 40940 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_ALIGN 0 40941 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_BITS 1 40942 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_SHIFT 1 40943 40944 /* Combo_IEEE0 :: AutoNegExp :: reserved1 [00:00] */ 40945 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_MASK 0x0001 40946 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_ALIGN 0 40947 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_BITS 1 40948 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_SHIFT 0 40949 40950 40951 /**************************************************************************** 40952 * Combo_IEEE0 :: AutoNegNP 40953 */ 40954 /* Combo_IEEE0 :: AutoNegNP :: Next_Page [15:15] */ 40955 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_MASK 0x8000 40956 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_ALIGN 0 40957 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_BITS 1 40958 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_SHIFT 15 40959 40960 /* Combo_IEEE0 :: AutoNegNP :: Ack [14:14] */ 40961 #define COMBO_IEEE0_AUTONEGNP_ACK_MASK 0x4000 40962 #define COMBO_IEEE0_AUTONEGNP_ACK_ALIGN 0 40963 #define COMBO_IEEE0_AUTONEGNP_ACK_BITS 1 40964 #define COMBO_IEEE0_AUTONEGNP_ACK_SHIFT 14 40965 40966 /* Combo_IEEE0 :: AutoNegNP :: Message_Page [13:13] */ 40967 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_MASK 0x2000 40968 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_ALIGN 0 40969 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_BITS 1 40970 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_SHIFT 13 40971 40972 /* Combo_IEEE0 :: AutoNegNP :: Ack2 [12:12] */ 40973 #define COMBO_IEEE0_AUTONEGNP_ACK2_MASK 0x1000 40974 #define COMBO_IEEE0_AUTONEGNP_ACK2_ALIGN 0 40975 #define COMBO_IEEE0_AUTONEGNP_ACK2_BITS 1 40976 #define COMBO_IEEE0_AUTONEGNP_ACK2_SHIFT 12 40977 40978 /* Combo_IEEE0 :: AutoNegNP :: Toggle [11:11] */ 40979 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_MASK 0x0800 40980 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_ALIGN 0 40981 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_BITS 1 40982 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_SHIFT 11 40983 40984 /* Combo_IEEE0 :: AutoNegNP :: Message [10:00] */ 40985 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_MASK 0x07ff 40986 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_ALIGN 0 40987 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_BITS 11 40988 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_SHIFT 0 40989 40990 40991 /**************************************************************************** 40992 * Combo_IEEE0 :: AutoNegLPAbil2 40993 */ 40994 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Next_Page [15:15] */ 40995 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_MASK 0x8000 40996 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN 0 40997 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_BITS 1 40998 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT 15 40999 41000 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack [14:14] */ 41001 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_MASK 0x4000 41002 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_ALIGN 0 41003 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_BITS 1 41004 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_SHIFT 14 41005 41006 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Message_Page [13:13] */ 41007 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK 0x2000 41008 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN 0 41009 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS 1 41010 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT 13 41011 41012 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack2 [12:12] */ 41013 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_MASK 0x1000 41014 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_ALIGN 0 41015 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_BITS 1 41016 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_SHIFT 12 41017 41018 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Toggle [11:11] */ 41019 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_MASK 0x0800 41020 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_ALIGN 0 41021 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_BITS 1 41022 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_SHIFT 11 41023 41024 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Message [10:00] */ 41025 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_MASK 0x07ff 41026 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_ALIGN 0 41027 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_BITS 11 41028 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_SHIFT 0 41029 41030 41031 /**************************************************************************** 41032 * Combo_IEEE0 :: MIIextStat 41033 */ 41034 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */ 41035 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000 41036 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0 41037 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1 41038 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15 41039 41040 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */ 41041 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000 41042 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0 41043 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1 41044 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14 41045 41046 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */ 41047 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000 41048 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0 41049 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1 41050 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13 41051 41052 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */ 41053 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000 41054 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0 41055 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1 41056 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12 41057 41058 /* Combo_IEEE0 :: MIIextStat :: reserved0 [11:00] */ 41059 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_MASK 0x0fff 41060 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_ALIGN 0 41061 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_BITS 12 41062 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_SHIFT 0 41063 41064 41065 /**************************************************************************** 41066 * Warpcore_IEEE_PMD_PMD_ieee0Blk 41067 */ 41068 /**************************************************************************** 41069 * PMD_ieee0Blk :: PMD_ieeeControl1 41070 */ 41071 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: rst_sw [15:15] */ 41072 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_MASK 0x8000 41073 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_ALIGN 0 41074 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_BITS 1 41075 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_SHIFT 15 41076 41077 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved0 [14:14] */ 41078 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_MASK 0x4000 41079 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_ALIGN 0 41080 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_BITS 1 41081 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_SHIFT 14 41082 41083 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection0 [13:13] */ 41084 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_MASK 0x2000 41085 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_ALIGN 0 41086 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_BITS 1 41087 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_SHIFT 13 41088 41089 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved1 [12:12] */ 41090 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_MASK 0x1000 41091 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_ALIGN 0 41092 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_BITS 1 41093 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_SHIFT 12 41094 41095 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: pwrdwn_sw_10g [11:11] */ 41096 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_MASK 0x0800 41097 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_ALIGN 0 41098 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_BITS 1 41099 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_SHIFT 11 41100 41101 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved2 [10:07] */ 41102 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_MASK 0x0780 41103 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_ALIGN 0 41104 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_BITS 4 41105 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_SHIFT 7 41106 41107 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection1 [06:06] */ 41108 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_MASK 0x0040 41109 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_ALIGN 0 41110 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_BITS 1 41111 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_SHIFT 6 41112 41113 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection2 [05:02] */ 41114 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_MASK 0x003c 41115 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_ALIGN 0 41116 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_BITS 4 41117 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_SHIFT 2 41118 41119 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved3 [01:01] */ 41120 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_MASK 0x0002 41121 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_ALIGN 0 41122 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_BITS 1 41123 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_SHIFT 1 41124 41125 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: gloop10g [00:00] */ 41126 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_MASK 0x0001 41127 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_ALIGN 0 41128 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_BITS 1 41129 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_SHIFT 0 41130 41131 41132 /**************************************************************************** 41133 * PMD_ieee0Blk :: PMD_ieeeStatus1 41134 */ 41135 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved0 [15:08] */ 41136 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_MASK 0xff00 41137 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_ALIGN 0 41138 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_BITS 8 41139 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_SHIFT 8 41140 41141 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: Fault [07:07] */ 41142 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_MASK 0x0080 41143 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_ALIGN 0 41144 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_BITS 1 41145 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_SHIFT 7 41146 41147 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved1 [06:03] */ 41148 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_MASK 0x0078 41149 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_ALIGN 0 41150 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_BITS 4 41151 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_SHIFT 3 41152 41153 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: Rx_linkStatus [02:02] */ 41154 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_MASK 0x0004 41155 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_ALIGN 0 41156 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_BITS 1 41157 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_SHIFT 2 41158 41159 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: lowPoerwAbility [01:01] */ 41160 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_MASK 0x0002 41161 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_ALIGN 0 41162 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_BITS 1 41163 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_SHIFT 1 41164 41165 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved2 [00:00] */ 41166 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_MASK 0x0001 41167 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_ALIGN 0 41168 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_BITS 1 41169 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_SHIFT 0 41170 41171 41172 /**************************************************************************** 41173 * PMD_ieee0Blk :: PMD_ieeeId1 41174 */ 41175 /* PMD_ieee0Blk :: PMD_ieeeId1 :: IEEEID1 [15:00] */ 41176 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_MASK 0xffff 41177 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_ALIGN 0 41178 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_BITS 16 41179 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_SHIFT 0 41180 41181 41182 /**************************************************************************** 41183 * PMD_ieee0Blk :: PMD_ieeeId2 41184 */ 41185 /* PMD_ieee0Blk :: PMD_ieeeId2 :: IEEEID2 [15:00] */ 41186 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_MASK 0xffff 41187 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_ALIGN 0 41188 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_BITS 16 41189 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_SHIFT 0 41190 41191 41192 /**************************************************************************** 41193 * PMD_ieee0Blk :: PMD_ieeeSpeedAbility 41194 */ 41195 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: reserved0 [15:07] */ 41196 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_MASK 0xff80 41197 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_ALIGN 0 41198 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_BITS 9 41199 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_SHIFT 7 41200 41201 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10M [06:06] */ 41202 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_MASK 0x0040 41203 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_ALIGN 0 41204 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_BITS 1 41205 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_SHIFT 6 41206 41207 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed100M [05:05] */ 41208 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_MASK 0x0020 41209 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_ALIGN 0 41210 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_BITS 1 41211 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_SHIFT 5 41212 41213 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed1000B [04:04] */ 41214 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_MASK 0x0010 41215 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_ALIGN 0 41216 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_BITS 1 41217 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_SHIFT 4 41218 41219 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: reserved1 [03:03] */ 41220 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_MASK 0x0008 41221 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_ALIGN 0 41222 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_BITS 1 41223 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_SHIFT 3 41224 41225 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10PASS_TS [02:02] */ 41226 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_MASK 0x0004 41227 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_ALIGN 0 41228 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_BITS 1 41229 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_SHIFT 2 41230 41231 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed2BASE_TL [01:01] */ 41232 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_MASK 0x0002 41233 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_ALIGN 0 41234 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_BITS 1 41235 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_SHIFT 1 41236 41237 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10G [00:00] */ 41238 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_MASK 0x0001 41239 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_ALIGN 0 41240 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_BITS 1 41241 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_SHIFT 0 41242 41243 41244 /**************************************************************************** 41245 * PMD_ieee0Blk :: PMD_ieeeDevInPkg2 41246 */ 41247 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: reserved0 [15:08] */ 41248 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_MASK 0xff00 41249 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_ALIGN 0 41250 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_BITS 8 41251 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_SHIFT 8 41252 41253 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: AN [07:07] */ 41254 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_AN_MASK 0x0080 41255 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_AN_ALIGN 0 41256 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_AN_BITS 1 41257 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_AN_SHIFT 7 41258 41259 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: TC [06:06] */ 41260 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_TC_MASK 0x0040 41261 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_TC_ALIGN 0 41262 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_TC_BITS 1 41263 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_TC_SHIFT 6 41264 41265 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: DTE_XS [05:05] */ 41266 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_DTE_XS_MASK 0x0020 41267 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_DTE_XS_ALIGN 0 41268 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_DTE_XS_BITS 1 41269 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_DTE_XS_SHIFT 5 41270 41271 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: PHY_XS [04:04] */ 41272 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PHY_XS_MASK 0x0010 41273 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PHY_XS_ALIGN 0 41274 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PHY_XS_BITS 1 41275 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PHY_XS_SHIFT 4 41276 41277 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: PCS_XS [03:03] */ 41278 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PCS_XS_MASK 0x0008 41279 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PCS_XS_ALIGN 0 41280 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PCS_XS_BITS 1 41281 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PCS_XS_SHIFT 3 41282 41283 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: WIS [02:02] */ 41284 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_WIS_MASK 0x0004 41285 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_WIS_ALIGN 0 41286 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_WIS_BITS 1 41287 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_WIS_SHIFT 2 41288 41289 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: PMA_PMD [01:01] */ 41290 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PMA_PMD_MASK 0x0002 41291 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PMA_PMD_ALIGN 0 41292 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PMA_PMD_BITS 1 41293 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PMA_PMD_SHIFT 1 41294 41295 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: Clause22 [00:00] */ 41296 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CLAUSE22_MASK 0x0001 41297 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CLAUSE22_ALIGN 0 41298 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CLAUSE22_BITS 1 41299 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CLAUSE22_SHIFT 0 41300 41301 41302 /**************************************************************************** 41303 * PMD_ieee0Blk :: PMD_ieeeDevInPkg1 41304 */ 41305 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: Vendor2 [15:15] */ 41306 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR2_MASK 0x8000 41307 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR2_ALIGN 0 41308 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR2_BITS 1 41309 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR2_SHIFT 15 41310 41311 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: Vendor1 [14:14] */ 41312 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR1_MASK 0x4000 41313 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR1_ALIGN 0 41314 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR1_BITS 1 41315 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR1_SHIFT 14 41316 41317 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: CL22ext [13:13] */ 41318 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CL22EXT_MASK 0x2000 41319 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CL22EXT_ALIGN 0 41320 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CL22EXT_BITS 1 41321 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CL22EXT_SHIFT 13 41322 41323 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: reserved0 [12:00] */ 41324 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_MASK 0x1fff 41325 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_ALIGN 0 41326 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_BITS 13 41327 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_SHIFT 0 41328 41329 41330 /**************************************************************************** 41331 * PMD_ieee0Blk :: PMD_ieeeControl2 41332 */ 41333 /* PMD_ieee0Blk :: PMD_ieeeControl2 :: reserved0 [15:04] */ 41334 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_MASK 0xfff0 41335 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_ALIGN 0 41336 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_BITS 12 41337 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_SHIFT 4 41338 41339 /* PMD_ieee0Blk :: PMD_ieeeControl2 :: PMA_PMD_typeSel [03:00] */ 41340 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_MASK 0x000f 41341 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_ALIGN 0 41342 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_BITS 4 41343 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_SHIFT 0 41344 41345 41346 /**************************************************************************** 41347 * PMD_ieee0Blk :: PMD_ieeeStatus2 41348 */ 41349 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: devPresent [15:14] */ 41350 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_MASK 0xc000 41351 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_ALIGN 0 41352 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_BITS 2 41353 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_SHIFT 14 41354 41355 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: txFaultAbility [13:13] */ 41356 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_MASK 0x2000 41357 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_ALIGN 0 41358 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_BITS 1 41359 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_SHIFT 13 41360 41361 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: rxFaultAbility [12:12] */ 41362 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_MASK 0x1000 41363 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_ALIGN 0 41364 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_BITS 1 41365 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_SHIFT 12 41366 41367 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: txFault [11:11] */ 41368 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_MASK 0x0800 41369 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_ALIGN 0 41370 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_BITS 1 41371 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_SHIFT 11 41372 41373 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: rxFault [10:10] */ 41374 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_MASK 0x0400 41375 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_ALIGN 0 41376 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_BITS 1 41377 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_SHIFT 10 41378 41379 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: extAbilities [09:09] */ 41380 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_MASK 0x0200 41381 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_ALIGN 0 41382 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_BITS 1 41383 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_SHIFT 9 41384 41385 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_txDisableAble [08:08] */ 41386 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_MASK 0x0100 41387 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_ALIGN 0 41388 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_BITS 1 41389 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_SHIFT 8 41390 41391 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_SR_able [07:07] */ 41392 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_MASK 0x0080 41393 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_ALIGN 0 41394 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_BITS 1 41395 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_SHIFT 7 41396 41397 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LR_able [06:06] */ 41398 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_MASK 0x0040 41399 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_ALIGN 0 41400 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_BITS 1 41401 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_SHIFT 6 41402 41403 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_ER_able [05:05] */ 41404 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_MASK 0x0020 41405 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_ALIGN 0 41406 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_BITS 1 41407 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_SHIFT 5 41408 41409 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LX4_able [04:04] */ 41410 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_MASK 0x0010 41411 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_ALIGN 0 41412 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_BITS 1 41413 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_SHIFT 4 41414 41415 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_SW_able [03:03] */ 41416 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_MASK 0x0008 41417 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_ALIGN 0 41418 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_BITS 1 41419 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_SHIFT 3 41420 41421 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LW_able [02:02] */ 41422 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_MASK 0x0004 41423 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_ALIGN 0 41424 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_BITS 1 41425 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_SHIFT 2 41426 41427 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_EW_able [01:01] */ 41428 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_MASK 0x0002 41429 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_ALIGN 0 41430 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_BITS 1 41431 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_SHIFT 1 41432 41433 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMA_loopback_able [00:00] */ 41434 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_MASK 0x0001 41435 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_ALIGN 0 41436 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_BITS 1 41437 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_SHIFT 0 41438 41439 41440 /**************************************************************************** 41441 * PMD_ieee0Blk :: PMD_txDisable 41442 */ 41443 /* PMD_ieee0Blk :: PMD_txDisable :: reserved0 [15:05] */ 41444 #define PMD_IEEE0BLK_PMD_TXDISABLE_RESERVED0_MASK 0xffe0 41445 #define PMD_IEEE0BLK_PMD_TXDISABLE_RESERVED0_ALIGN 0 41446 #define PMD_IEEE0BLK_PMD_TXDISABLE_RESERVED0_BITS 11 41447 #define PMD_IEEE0BLK_PMD_TXDISABLE_RESERVED0_SHIFT 5 41448 41449 /* PMD_ieee0Blk :: PMD_txDisable :: tx_disable_ln3 [04:04] */ 41450 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN3_MASK 0x0010 41451 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN3_ALIGN 0 41452 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN3_BITS 1 41453 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN3_SHIFT 4 41454 41455 /* PMD_ieee0Blk :: PMD_txDisable :: tx_disable_ln2 [03:03] */ 41456 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN2_MASK 0x0008 41457 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN2_ALIGN 0 41458 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN2_BITS 1 41459 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN2_SHIFT 3 41460 41461 /* PMD_ieee0Blk :: PMD_txDisable :: tx_disable_ln1 [02:02] */ 41462 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN1_MASK 0x0004 41463 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN1_ALIGN 0 41464 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN1_BITS 1 41465 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN1_SHIFT 2 41466 41467 /* PMD_ieee0Blk :: PMD_txDisable :: tx_disable_ln0 [01:01] */ 41468 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN0_MASK 0x0002 41469 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN0_ALIGN 0 41470 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN0_BITS 1 41471 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN0_SHIFT 1 41472 41473 /* PMD_ieee0Blk :: PMD_txDisable :: tx_disable_global [00:00] */ 41474 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_GLOBAL_MASK 0x0001 41475 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_GLOBAL_ALIGN 0 41476 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_GLOBAL_BITS 1 41477 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_GLOBAL_SHIFT 0 41478 41479 41480 /**************************************************************************** 41481 * PMD_ieee0Blk :: PMD_rxSigDet 41482 */ 41483 /* PMD_ieee0Blk :: PMD_rxSigDet :: reserved0 [15:05] */ 41484 #define PMD_IEEE0BLK_PMD_RXSIGDET_RESERVED0_MASK 0xffe0 41485 #define PMD_IEEE0BLK_PMD_RXSIGDET_RESERVED0_ALIGN 0 41486 #define PMD_IEEE0BLK_PMD_RXSIGDET_RESERVED0_BITS 11 41487 #define PMD_IEEE0BLK_PMD_RXSIGDET_RESERVED0_SHIFT 5 41488 41489 /* PMD_ieee0Blk :: PMD_rxSigDet :: rxSigdet_ln3 [04:04] */ 41490 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN3_MASK 0x0010 41491 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN3_ALIGN 0 41492 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN3_BITS 1 41493 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN3_SHIFT 4 41494 41495 /* PMD_ieee0Blk :: PMD_rxSigDet :: rxSigdet_ln2 [03:03] */ 41496 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN2_MASK 0x0008 41497 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN2_ALIGN 0 41498 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN2_BITS 1 41499 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN2_SHIFT 3 41500 41501 /* PMD_ieee0Blk :: PMD_rxSigDet :: rxSigdet_ln1 [02:02] */ 41502 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN1_MASK 0x0004 41503 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN1_ALIGN 0 41504 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN1_BITS 1 41505 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN1_SHIFT 2 41506 41507 /* PMD_ieee0Blk :: PMD_rxSigDet :: rxSigdet_ln0 [01:01] */ 41508 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN0_MASK 0x0002 41509 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN0_ALIGN 0 41510 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN0_BITS 1 41511 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN0_SHIFT 1 41512 41513 /* PMD_ieee0Blk :: PMD_rxSigDet :: rxSigdet_global [00:00] */ 41514 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_GLOBAL_MASK 0x0001 41515 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_GLOBAL_ALIGN 0 41516 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_GLOBAL_BITS 1 41517 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_GLOBAL_SHIFT 0 41518 41519 41520 /**************************************************************************** 41521 * PMD_ieee0Blk :: PMD_extendedAbility 41522 */ 41523 /* PMD_ieee0Blk :: PMD_extendedAbility :: reserved0 [15:09] */ 41524 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_MASK 0xfe00 41525 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_ALIGN 0 41526 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_BITS 7 41527 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_SHIFT 9 41528 41529 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10BASE_T_Ability [08:08] */ 41530 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_MASK 0x0100 41531 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_ALIGN 0 41532 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_BITS 1 41533 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_SHIFT 8 41534 41535 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_100BASE_TX_Ability [07:07] */ 41536 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_MASK 0x0080 41537 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_ALIGN 0 41538 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_BITS 1 41539 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_SHIFT 7 41540 41541 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_1000BASE_KX_Ability [06:06] */ 41542 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_MASK 0x0040 41543 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_ALIGN 0 41544 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_BITS 1 41545 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_SHIFT 6 41546 41547 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_1000BASE_T_Ability [05:05] */ 41548 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_MASK 0x0020 41549 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_ALIGN 0 41550 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_BITS 1 41551 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_SHIFT 5 41552 41553 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_KR_Ability [04:04] */ 41554 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_MASK 0x0010 41555 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_ALIGN 0 41556 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_BITS 1 41557 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_SHIFT 4 41558 41559 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_KX4_Ability [03:03] */ 41560 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_MASK 0x0008 41561 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_ALIGN 0 41562 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_BITS 1 41563 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_SHIFT 3 41564 41565 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_T_Ability [02:02] */ 41566 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_MASK 0x0004 41567 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_ALIGN 0 41568 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_BITS 1 41569 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_SHIFT 2 41570 41571 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_LRM_Ability [01:01] */ 41572 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_MASK 0x0002 41573 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_ALIGN 0 41574 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_BITS 1 41575 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_SHIFT 1 41576 41577 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_CX4_Ability [00:00] */ 41578 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_MASK 0x0001 41579 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_ALIGN 0 41580 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_BITS 1 41581 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_SHIFT 0 41582 41583 41584 /**************************************************************************** 41585 * Warpcore_IEEE_PMD_PMD_ieee9Blk 41586 */ 41587 /**************************************************************************** 41588 * PMD_ieee9Blk :: tengbase_kr_pmd_control_register_150 41589 */ 41590 /* PMD_ieee9Blk :: tengbase_kr_pmd_control_register_150 :: reserved0 [15:02] */ 41591 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_MASK 0xfffc 41592 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_ALIGN 0 41593 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_BITS 14 41594 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_SHIFT 2 41595 41596 /* PMD_ieee9Blk :: tengbase_kr_pmd_control_register_150 :: training_enable [01:01] */ 41597 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_MASK 0x0002 41598 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_ALIGN 0 41599 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_BITS 1 41600 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_SHIFT 1 41601 41602 /* PMD_ieee9Blk :: tengbase_kr_pmd_control_register_150 :: restart_training [00:00] */ 41603 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_MASK 0x0001 41604 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_ALIGN 0 41605 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_BITS 1 41606 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_SHIFT 0 41607 41608 41609 /**************************************************************************** 41610 * PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 41611 */ 41612 /* PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 :: reserved0 [15:04] */ 41613 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_MASK 0xfff0 41614 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_ALIGN 0 41615 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_BITS 12 41616 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_SHIFT 4 41617 41618 /* PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 :: training_failure [03:03] */ 41619 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_MASK 0x0008 41620 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_ALIGN 0 41621 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_BITS 1 41622 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_SHIFT 3 41623 41624 /* PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 :: training_status [02:02] */ 41625 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_MASK 0x0004 41626 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_ALIGN 0 41627 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_BITS 1 41628 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_SHIFT 2 41629 41630 /* PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 :: frame_lock [01:01] */ 41631 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_MASK 0x0002 41632 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_ALIGN 0 41633 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_BITS 1 41634 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_SHIFT 1 41635 41636 /* PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 :: receiver_status [00:00] */ 41637 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_MASK 0x0001 41638 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_ALIGN 0 41639 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_BITS 1 41640 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_SHIFT 0 41641 41642 41643 /**************************************************************************** 41644 * PMD_ieee9Blk :: tengbase_kr_lp_coefficient_upd_152 41645 */ 41646 /* PMD_ieee9Blk :: tengbase_kr_lp_coefficient_upd_152 :: lp_coeff_upd_reg [15:00] */ 41647 #define PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_MASK 0xffff 41648 #define PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_ALIGN 0 41649 #define PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_BITS 16 41650 #define PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_SHIFT 0 41651 41652 41653 /**************************************************************************** 41654 * PMD_ieee9Blk :: tengbase_kr_lp_status_report_reg_153 41655 */ 41656 /* PMD_ieee9Blk :: tengbase_kr_lp_status_report_reg_153 :: lp_coeff_status_reg [15:00] */ 41657 #define PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_MASK 0xffff 41658 #define PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_ALIGN 0 41659 #define PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_BITS 16 41660 #define PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_SHIFT 0 41661 41662 41663 /**************************************************************************** 41664 * PMD_ieee9Blk :: tengbase_kr_ld_coefficient_upd_154 41665 */ 41666 /* PMD_ieee9Blk :: tengbase_kr_ld_coefficient_upd_154 :: ld_coeff_upd_reg [15:00] */ 41667 #define PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_MASK 0xffff 41668 #define PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_ALIGN 0 41669 #define PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_BITS 16 41670 #define PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_SHIFT 0 41671 41672 41673 /**************************************************************************** 41674 * PMD_ieee9Blk :: tengbase_kr_ld_status_report_reg_155 41675 */ 41676 /* PMD_ieee9Blk :: tengbase_kr_ld_status_report_reg_155 :: ld_coeff_status_reg [15:00] */ 41677 #define PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_MASK 0xffff 41678 #define PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_ALIGN 0 41679 #define PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_BITS 16 41680 #define PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_SHIFT 0 41681 41682 41683 /**************************************************************************** 41684 * Warpcore_IEEE_PMD_PMD_ieee10Blk 41685 */ 41686 /**************************************************************************** 41687 * PMD_ieee10Blk :: PMD_KX_control 41688 */ 41689 /* PMD_ieee10Blk :: PMD_KX_control :: reserved0 [15:01] */ 41690 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_MASK 0xfffe 41691 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_ALIGN 0 41692 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_BITS 15 41693 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_SHIFT 1 41694 41695 /* PMD_ieee10Blk :: PMD_KX_control :: tx_disable [00:00] */ 41696 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_MASK 0x0001 41697 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_ALIGN 0 41698 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_BITS 1 41699 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_SHIFT 0 41700 41701 41702 /**************************************************************************** 41703 * PMD_ieee10Blk :: PMD_KX_status 41704 */ 41705 /* PMD_ieee10Blk :: PMD_KX_status :: reserved0 [15:14] */ 41706 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_MASK 0xc000 41707 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_ALIGN 0 41708 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_BITS 2 41709 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_SHIFT 14 41710 41711 /* PMD_ieee10Blk :: PMD_KX_status :: KX_txFaultAbility [13:13] */ 41712 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_MASK 0x2000 41713 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_ALIGN 0 41714 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_BITS 1 41715 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_SHIFT 13 41716 41717 /* PMD_ieee10Blk :: PMD_KX_status :: KX_rxFaultAbility [12:12] */ 41718 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_MASK 0x1000 41719 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_ALIGN 0 41720 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_BITS 1 41721 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_SHIFT 12 41722 41723 /* PMD_ieee10Blk :: PMD_KX_status :: KX_txFault [11:11] */ 41724 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_MASK 0x0800 41725 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_ALIGN 0 41726 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_BITS 1 41727 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_SHIFT 11 41728 41729 /* PMD_ieee10Blk :: PMD_KX_status :: KX_rsFault [10:10] */ 41730 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_MASK 0x0400 41731 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_ALIGN 0 41732 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_BITS 1 41733 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_SHIFT 10 41734 41735 /* PMD_ieee10Blk :: PMD_KX_status :: reserved1 [09:09] */ 41736 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_MASK 0x0200 41737 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_ALIGN 0 41738 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_BITS 1 41739 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_SHIFT 9 41740 41741 /* PMD_ieee10Blk :: PMD_KX_status :: txDisableAbility [08:08] */ 41742 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_MASK 0x0100 41743 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_ALIGN 0 41744 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_BITS 1 41745 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_SHIFT 8 41746 41747 /* PMD_ieee10Blk :: PMD_KX_status :: reserved2 [07:01] */ 41748 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_MASK 0x00fe 41749 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_ALIGN 0 41750 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_BITS 7 41751 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_SHIFT 1 41752 41753 /* PMD_ieee10Blk :: PMD_KX_status :: PMD_sigdet [00:00] */ 41754 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_MASK 0x0001 41755 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_ALIGN 0 41756 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_BITS 1 41757 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_SHIFT 0 41758 41759 41760 /**************************************************************************** 41761 * PMD_ieee10Blk :: PMD_fecAbility 41762 */ 41763 /* PMD_ieee10Blk :: PMD_fecAbility :: reserved0 [15:02] */ 41764 #define PMD_IEEE10BLK_PMD_FECABILITY_RESERVED0_MASK 0xfffc 41765 #define PMD_IEEE10BLK_PMD_FECABILITY_RESERVED0_ALIGN 0 41766 #define PMD_IEEE10BLK_PMD_FECABILITY_RESERVED0_BITS 14 41767 #define PMD_IEEE10BLK_PMD_FECABILITY_RESERVED0_SHIFT 2 41768 41769 /* PMD_ieee10Blk :: PMD_fecAbility :: errorCnt_able [01:01] */ 41770 #define PMD_IEEE10BLK_PMD_FECABILITY_ERRORCNT_ABLE_MASK 0x0002 41771 #define PMD_IEEE10BLK_PMD_FECABILITY_ERRORCNT_ABLE_ALIGN 0 41772 #define PMD_IEEE10BLK_PMD_FECABILITY_ERRORCNT_ABLE_BITS 1 41773 #define PMD_IEEE10BLK_PMD_FECABILITY_ERRORCNT_ABLE_SHIFT 1 41774 41775 /* PMD_ieee10Blk :: PMD_fecAbility :: fec_able [00:00] */ 41776 #define PMD_IEEE10BLK_PMD_FECABILITY_FEC_ABLE_MASK 0x0001 41777 #define PMD_IEEE10BLK_PMD_FECABILITY_FEC_ABLE_ALIGN 0 41778 #define PMD_IEEE10BLK_PMD_FECABILITY_FEC_ABLE_BITS 1 41779 #define PMD_IEEE10BLK_PMD_FECABILITY_FEC_ABLE_SHIFT 0 41780 41781 41782 /**************************************************************************** 41783 * PMD_ieee10Blk :: PMD_fecControl 41784 */ 41785 /* PMD_ieee10Blk :: PMD_fecControl :: reserved0 [15:02] */ 41786 #define PMD_IEEE10BLK_PMD_FECCONTROL_RESERVED0_MASK 0xfffc 41787 #define PMD_IEEE10BLK_PMD_FECCONTROL_RESERVED0_ALIGN 0 41788 #define PMD_IEEE10BLK_PMD_FECCONTROL_RESERVED0_BITS 14 41789 #define PMD_IEEE10BLK_PMD_FECCONTROL_RESERVED0_SHIFT 2 41790 41791 /* PMD_ieee10Blk :: PMD_fecControl :: errorCnt_en [01:01] */ 41792 #define PMD_IEEE10BLK_PMD_FECCONTROL_ERRORCNT_EN_MASK 0x0002 41793 #define PMD_IEEE10BLK_PMD_FECCONTROL_ERRORCNT_EN_ALIGN 0 41794 #define PMD_IEEE10BLK_PMD_FECCONTROL_ERRORCNT_EN_BITS 1 41795 #define PMD_IEEE10BLK_PMD_FECCONTROL_ERRORCNT_EN_SHIFT 1 41796 41797 /* PMD_ieee10Blk :: PMD_fecControl :: fec_en [00:00] */ 41798 #define PMD_IEEE10BLK_PMD_FECCONTROL_FEC_EN_MASK 0x0001 41799 #define PMD_IEEE10BLK_PMD_FECCONTROL_FEC_EN_ALIGN 0 41800 #define PMD_IEEE10BLK_PMD_FECCONTROL_FEC_EN_BITS 1 41801 #define PMD_IEEE10BLK_PMD_FECCONTROL_FEC_EN_SHIFT 0 41802 41803 41804 /**************************************************************************** 41805 * PMD_ieee10Blk :: PMD_CorrectedBlksL 41806 */ 41807 /* PMD_ieee10Blk :: PMD_CorrectedBlksL :: corCountL [15:00] */ 41808 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSL_CORCOUNTL_MASK 0xffff 41809 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSL_CORCOUNTL_ALIGN 0 41810 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSL_CORCOUNTL_BITS 16 41811 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSL_CORCOUNTL_SHIFT 0 41812 41813 41814 /**************************************************************************** 41815 * PMD_ieee10Blk :: PMD_CorrectedBlksH 41816 */ 41817 /* PMD_ieee10Blk :: PMD_CorrectedBlksH :: corCountH [15:00] */ 41818 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSH_CORCOUNTH_MASK 0xffff 41819 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSH_CORCOUNTH_ALIGN 0 41820 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSH_CORCOUNTH_BITS 16 41821 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSH_CORCOUNTH_SHIFT 0 41822 41823 41824 /**************************************************************************** 41825 * PMD_ieee10Blk :: PMD_UncorrectedBlksL 41826 */ 41827 /* PMD_ieee10Blk :: PMD_UncorrectedBlksL :: uncorCountL [15:00] */ 41828 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_MASK 0xffff 41829 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_ALIGN 0 41830 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_BITS 16 41831 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_SHIFT 0 41832 41833 41834 /**************************************************************************** 41835 * PMD_ieee10Blk :: PMD_UncorrectedBlksH 41836 */ 41837 /* PMD_ieee10Blk :: PMD_UncorrectedBlksH :: uncorCountH [15:00] */ 41838 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_MASK 0xffff 41839 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_ALIGN 0 41840 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_BITS 16 41841 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_SHIFT 0 41842 41843 41844 /**************************************************************************** 41845 * Warpcore_IEEE_PCS_PCS_ieee0Blk 41846 */ 41847 /**************************************************************************** 41848 * PCS_ieee0Blk :: PCS_ieeeControl1 41849 */ 41850 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: rst_sw [15:15] */ 41851 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RST_SW_MASK 0x8000 41852 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RST_SW_ALIGN 0 41853 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RST_SW_BITS 1 41854 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RST_SW_SHIFT 15 41855 41856 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: gloop10g [14:14] */ 41857 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_GLOOP10G_MASK 0x4000 41858 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_GLOOP10G_ALIGN 0 41859 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_GLOOP10G_BITS 1 41860 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_GLOOP10G_SHIFT 14 41861 41862 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: SpeedSelection0 [13:13] */ 41863 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION0_MASK 0x2000 41864 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION0_ALIGN 0 41865 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION0_BITS 1 41866 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION0_SHIFT 13 41867 41868 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: reserved0 [12:12] */ 41869 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED0_MASK 0x1000 41870 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED0_ALIGN 0 41871 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED0_BITS 1 41872 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED0_SHIFT 12 41873 41874 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: pwrdwn_sw_10g [11:11] */ 41875 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_PWRDWN_SW_10G_MASK 0x0800 41876 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_PWRDWN_SW_10G_ALIGN 0 41877 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_PWRDWN_SW_10G_BITS 1 41878 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_PWRDWN_SW_10G_SHIFT 11 41879 41880 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: clockStoppable [10:10] */ 41881 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_CLOCKSTOPPABLE_MASK 0x0400 41882 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_CLOCKSTOPPABLE_ALIGN 0 41883 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_CLOCKSTOPPABLE_BITS 1 41884 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_CLOCKSTOPPABLE_SHIFT 10 41885 41886 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: reserved1 [09:07] */ 41887 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED1_MASK 0x0380 41888 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED1_ALIGN 0 41889 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED1_BITS 3 41890 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED1_SHIFT 7 41891 41892 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: SpeedSelection1 [06:06] */ 41893 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION1_MASK 0x0040 41894 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION1_ALIGN 0 41895 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION1_BITS 1 41896 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION1_SHIFT 6 41897 41898 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: SpeedSelection2 [05:02] */ 41899 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION2_MASK 0x003c 41900 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION2_ALIGN 0 41901 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION2_BITS 4 41902 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION2_SHIFT 2 41903 41904 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: reserved2 [01:00] */ 41905 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED2_MASK 0x0003 41906 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED2_ALIGN 0 41907 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED2_BITS 2 41908 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED2_SHIFT 0 41909 41910 41911 /**************************************************************************** 41912 * PCS_ieee0Blk :: PCS_ieeeStatus1 41913 */ 41914 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: reserved0 [15:12] */ 41915 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED0_MASK 0xf000 41916 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED0_ALIGN 0 41917 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED0_BITS 4 41918 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED0_SHIFT 12 41919 41920 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Tx_LPI_received [11:11] */ 41921 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_RECEIVED_MASK 0x0800 41922 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_RECEIVED_ALIGN 0 41923 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_RECEIVED_BITS 1 41924 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_RECEIVED_SHIFT 11 41925 41926 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Rx_LPI_received [10:10] */ 41927 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_RECEIVED_MASK 0x0400 41928 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_RECEIVED_ALIGN 0 41929 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_RECEIVED_BITS 1 41930 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_RECEIVED_SHIFT 10 41931 41932 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Tx_LPI_indication [09:09] */ 41933 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_INDICATION_MASK 0x0200 41934 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_INDICATION_ALIGN 0 41935 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_INDICATION_BITS 1 41936 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_INDICATION_SHIFT 9 41937 41938 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Rx_LPI_indication [08:08] */ 41939 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_INDICATION_MASK 0x0100 41940 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_INDICATION_ALIGN 0 41941 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_INDICATION_BITS 1 41942 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_INDICATION_SHIFT 8 41943 41944 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Fault [07:07] */ 41945 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_FAULT_MASK 0x0080 41946 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_FAULT_ALIGN 0 41947 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_FAULT_BITS 1 41948 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_FAULT_SHIFT 7 41949 41950 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: reserved1 [06:03] */ 41951 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED1_MASK 0x0078 41952 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED1_ALIGN 0 41953 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED1_BITS 4 41954 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED1_SHIFT 3 41955 41956 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Rx_linkStatus [02:02] */ 41957 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LINKSTATUS_MASK 0x0004 41958 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LINKSTATUS_ALIGN 0 41959 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LINKSTATUS_BITS 1 41960 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LINKSTATUS_SHIFT 2 41961 41962 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: lowPowerAbility [01:01] */ 41963 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_LOWPOWERABILITY_MASK 0x0002 41964 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_LOWPOWERABILITY_ALIGN 0 41965 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_LOWPOWERABILITY_BITS 1 41966 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_LOWPOWERABILITY_SHIFT 1 41967 41968 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: reserved2 [00:00] */ 41969 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED2_MASK 0x0001 41970 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED2_ALIGN 0 41971 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED2_BITS 1 41972 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED2_SHIFT 0 41973 41974 41975 /**************************************************************************** 41976 * PCS_ieee0Blk :: PCS_ieeeControl2 41977 */ 41978 /* PCS_ieee0Blk :: PCS_ieeeControl2 :: reserved0 [15:03] */ 41979 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_RESERVED0_MASK 0xfff8 41980 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_RESERVED0_ALIGN 0 41981 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_RESERVED0_BITS 13 41982 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_RESERVED0_SHIFT 3 41983 41984 /* PCS_ieee0Blk :: PCS_ieeeControl2 :: PCS_typeSel [02:00] */ 41985 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_PCS_TYPESEL_MASK 0x0007 41986 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_PCS_TYPESEL_ALIGN 0 41987 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_PCS_TYPESEL_BITS 3 41988 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_PCS_TYPESEL_SHIFT 0 41989 41990 41991 /**************************************************************************** 41992 * PCS_ieee0Blk :: PCS_ieeeStatus2 41993 */ 41994 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: devPresent [15:14] */ 41995 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_DEVPRESENT_MASK 0xc000 41996 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_DEVPRESENT_ALIGN 0 41997 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_DEVPRESENT_BITS 2 41998 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_DEVPRESENT_SHIFT 14 41999 42000 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: reserved0 [13:12] */ 42001 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED0_MASK 0x3000 42002 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED0_ALIGN 0 42003 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED0_BITS 2 42004 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED0_SHIFT 12 42005 42006 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_txFault [11:11] */ 42007 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_TXFAULT_MASK 0x0800 42008 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_TXFAULT_ALIGN 0 42009 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_TXFAULT_BITS 1 42010 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_TXFAULT_SHIFT 11 42011 42012 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_rxFault [10:10] */ 42013 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_RXFAULT_MASK 0x0400 42014 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_RXFAULT_ALIGN 0 42015 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_RXFAULT_BITS 1 42016 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_RXFAULT_SHIFT 10 42017 42018 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: reserved1 [09:06] */ 42019 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED1_MASK 0x03c0 42020 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED1_ALIGN 0 42021 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED1_BITS 4 42022 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED1_SHIFT 6 42023 42024 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_100GBASE_R_able [05:05] */ 42025 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_100GBASE_R_ABLE_MASK 0x0020 42026 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_100GBASE_R_ABLE_ALIGN 0 42027 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_100GBASE_R_ABLE_BITS 1 42028 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_100GBASE_R_ABLE_SHIFT 5 42029 42030 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_40GBASE_R_able [04:04] */ 42031 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_40GBASE_R_ABLE_MASK 0x0010 42032 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_40GBASE_R_ABLE_ALIGN 0 42033 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_40GBASE_R_ABLE_BITS 1 42034 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_40GBASE_R_ABLE_SHIFT 4 42035 42036 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_10GBASE_T_able [03:03] */ 42037 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_T_ABLE_MASK 0x0008 42038 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_T_ABLE_ALIGN 0 42039 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_T_ABLE_BITS 1 42040 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_T_ABLE_SHIFT 3 42041 42042 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_10GBASE_W_able [02:02] */ 42043 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_W_ABLE_MASK 0x0004 42044 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_W_ABLE_ALIGN 0 42045 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_W_ABLE_BITS 1 42046 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_W_ABLE_SHIFT 2 42047 42048 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_10GBASE_X_able [01:01] */ 42049 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_X_ABLE_MASK 0x0002 42050 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_X_ABLE_ALIGN 0 42051 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_X_ABLE_BITS 1 42052 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_X_ABLE_SHIFT 1 42053 42054 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_10GBASE_R_able [00:00] */ 42055 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_R_ABLE_MASK 0x0001 42056 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_R_ABLE_ALIGN 0 42057 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_R_ABLE_BITS 1 42058 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_R_ABLE_SHIFT 0 42059 42060 42061 /**************************************************************************** 42062 * Warpcore_IEEE_PCS_PCS_ieee1Blk 42063 */ 42064 /**************************************************************************** 42065 * PCS_ieee1Blk :: PCS_laneStatus 42066 */ 42067 /* PCS_ieee1Blk :: PCS_laneStatus :: reserved0 [15:13] */ 42068 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED0_MASK 0xe000 42069 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED0_ALIGN 0 42070 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED0_BITS 3 42071 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED0_SHIFT 13 42072 42073 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_alignStatus [12:12] */ 42074 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_ALIGNSTATUS_MASK 0x1000 42075 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_ALIGNSTATUS_ALIGN 0 42076 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_ALIGNSTATUS_BITS 1 42077 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_ALIGNSTATUS_SHIFT 12 42078 42079 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_PatTestAbility [11:11] */ 42080 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_PATTESTABILITY_MASK 0x0800 42081 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_PATTESTABILITY_ALIGN 0 42082 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_PATTESTABILITY_BITS 1 42083 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_PATTESTABILITY_SHIFT 11 42084 42085 /* PCS_ieee1Blk :: PCS_laneStatus :: reserved1 [10:04] */ 42086 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED1_MASK 0x07f0 42087 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED1_ALIGN 0 42088 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED1_BITS 7 42089 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED1_SHIFT 4 42090 42091 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_lane3Sync [03:03] */ 42092 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE3SYNC_MASK 0x0008 42093 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE3SYNC_ALIGN 0 42094 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE3SYNC_BITS 1 42095 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE3SYNC_SHIFT 3 42096 42097 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_lane2Sync [02:02] */ 42098 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE2SYNC_MASK 0x0004 42099 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE2SYNC_ALIGN 0 42100 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE2SYNC_BITS 1 42101 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE2SYNC_SHIFT 2 42102 42103 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_lane1Sync [01:01] */ 42104 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE1SYNC_MASK 0x0002 42105 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE1SYNC_ALIGN 0 42106 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE1SYNC_BITS 1 42107 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE1SYNC_SHIFT 1 42108 42109 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_lane0Sync [00:00] */ 42110 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE0SYNC_MASK 0x0001 42111 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE0SYNC_ALIGN 0 42112 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE0SYNC_BITS 1 42113 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE0SYNC_SHIFT 0 42114 42115 42116 /**************************************************************************** 42117 * PCS_ieee1Blk :: PCS_ieeeTestControl 42118 */ 42119 /* PCS_ieee1Blk :: PCS_ieeeTestControl :: reserved0 [15:03] */ 42120 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_RESERVED0_MASK 0xfff8 42121 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_RESERVED0_ALIGN 0 42122 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_RESERVED0_BITS 13 42123 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_RESERVED0_SHIFT 3 42124 42125 /* PCS_ieee1Blk :: PCS_ieeeTestControl :: PCS_txTestPatEn [02:02] */ 42126 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TXTESTPATEN_MASK 0x0004 42127 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TXTESTPATEN_ALIGN 0 42128 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TXTESTPATEN_BITS 1 42129 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TXTESTPATEN_SHIFT 2 42130 42131 /* PCS_ieee1Blk :: PCS_ieeeTestControl :: PCS_testPatSel [01:00] */ 42132 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TESTPATSEL_MASK 0x0003 42133 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TESTPATSEL_ALIGN 0 42134 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TESTPATSEL_BITS 2 42135 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TESTPATSEL_SHIFT 0 42136 42137 42138 /**************************************************************************** 42139 * Warpcore_IEEE_PCS_PCS_ieee2Blk 42140 */ 42141 /**************************************************************************** 42142 * PCS_ieee2Blk :: PCS_Status1 42143 */ 42144 /* PCS_ieee2Blk :: PCS_Status1 :: reserved0 [15:13] */ 42145 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED0_MASK 0xe000 42146 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED0_ALIGN 0 42147 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED0_BITS 3 42148 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED0_SHIFT 13 42149 42150 /* PCS_ieee2Blk :: PCS_Status1 :: PCS_link_status [12:12] */ 42151 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_LINK_STATUS_MASK 0x1000 42152 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_LINK_STATUS_ALIGN 0 42153 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_LINK_STATUS_BITS 1 42154 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_LINK_STATUS_SHIFT 12 42155 42156 /* PCS_ieee2Blk :: PCS_Status1 :: reserved1 [11:04] */ 42157 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED1_MASK 0x0ff0 42158 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED1_ALIGN 0 42159 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED1_BITS 8 42160 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED1_SHIFT 4 42161 42162 /* PCS_ieee2Blk :: PCS_Status1 :: PRBS9_ability [03:03] */ 42163 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS9_ABILITY_MASK 0x0008 42164 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS9_ABILITY_ALIGN 0 42165 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS9_ABILITY_BITS 1 42166 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS9_ABILITY_SHIFT 3 42167 42168 /* PCS_ieee2Blk :: PCS_Status1 :: PRBS31_ability [02:02] */ 42169 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS31_ABILITY_MASK 0x0004 42170 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS31_ABILITY_ALIGN 0 42171 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS31_ABILITY_BITS 1 42172 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS31_ABILITY_SHIFT 2 42173 42174 /* PCS_ieee2Blk :: PCS_Status1 :: PCS_hi_BER [01:01] */ 42175 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_HI_BER_MASK 0x0002 42176 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_HI_BER_ALIGN 0 42177 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_HI_BER_BITS 1 42178 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_HI_BER_SHIFT 1 42179 42180 /* PCS_ieee2Blk :: PCS_Status1 :: PCS_block_lock [00:00] */ 42181 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_BLOCK_LOCK_MASK 0x0001 42182 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_BLOCK_LOCK_ALIGN 0 42183 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_BLOCK_LOCK_BITS 1 42184 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_BLOCK_LOCK_SHIFT 0 42185 42186 42187 /**************************************************************************** 42188 * PCS_ieee2Blk :: PCS_Status2 42189 */ 42190 /* PCS_ieee2Blk :: PCS_Status2 :: latch_block_lock [15:15] */ 42191 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_BLOCK_LOCK_MASK 0x8000 42192 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_BLOCK_LOCK_ALIGN 0 42193 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_BLOCK_LOCK_BITS 1 42194 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_BLOCK_LOCK_SHIFT 15 42195 42196 /* PCS_ieee2Blk :: PCS_Status2 :: latch_hi_BER [14:14] */ 42197 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_HI_BER_MASK 0x4000 42198 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_HI_BER_ALIGN 0 42199 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_HI_BER_BITS 1 42200 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_HI_BER_SHIFT 14 42201 42202 /* PCS_ieee2Blk :: PCS_Status2 :: BER [13:08] */ 42203 #define PCS_IEEE2BLK_PCS_STATUS2_BER_MASK 0x3f00 42204 #define PCS_IEEE2BLK_PCS_STATUS2_BER_ALIGN 0 42205 #define PCS_IEEE2BLK_PCS_STATUS2_BER_BITS 6 42206 #define PCS_IEEE2BLK_PCS_STATUS2_BER_SHIFT 8 42207 42208 /* PCS_ieee2Blk :: PCS_Status2 :: errored_blocks [07:00] */ 42209 #define PCS_IEEE2BLK_PCS_STATUS2_ERRORED_BLOCKS_MASK 0x00ff 42210 #define PCS_IEEE2BLK_PCS_STATUS2_ERRORED_BLOCKS_ALIGN 0 42211 #define PCS_IEEE2BLK_PCS_STATUS2_ERRORED_BLOCKS_BITS 8 42212 #define PCS_IEEE2BLK_PCS_STATUS2_ERRORED_BLOCKS_SHIFT 0 42213 42214 42215 /**************************************************************************** 42216 * PCS_ieee2Blk :: PCS_seedA0 42217 */ 42218 /* PCS_ieee2Blk :: PCS_seedA0 :: seedA0 [15:00] */ 42219 #define PCS_IEEE2BLK_PCS_SEEDA0_SEEDA0_MASK 0xffff 42220 #define PCS_IEEE2BLK_PCS_SEEDA0_SEEDA0_ALIGN 0 42221 #define PCS_IEEE2BLK_PCS_SEEDA0_SEEDA0_BITS 16 42222 #define PCS_IEEE2BLK_PCS_SEEDA0_SEEDA0_SHIFT 0 42223 42224 42225 /**************************************************************************** 42226 * PCS_ieee2Blk :: PCS_seedA1 42227 */ 42228 /* PCS_ieee2Blk :: PCS_seedA1 :: seedA1 [15:00] */ 42229 #define PCS_IEEE2BLK_PCS_SEEDA1_SEEDA1_MASK 0xffff 42230 #define PCS_IEEE2BLK_PCS_SEEDA1_SEEDA1_ALIGN 0 42231 #define PCS_IEEE2BLK_PCS_SEEDA1_SEEDA1_BITS 16 42232 #define PCS_IEEE2BLK_PCS_SEEDA1_SEEDA1_SHIFT 0 42233 42234 42235 /**************************************************************************** 42236 * PCS_ieee2Blk :: PCS_seedA2 42237 */ 42238 /* PCS_ieee2Blk :: PCS_seedA2 :: seedA2 [15:00] */ 42239 #define PCS_IEEE2BLK_PCS_SEEDA2_SEEDA2_MASK 0xffff 42240 #define PCS_IEEE2BLK_PCS_SEEDA2_SEEDA2_ALIGN 0 42241 #define PCS_IEEE2BLK_PCS_SEEDA2_SEEDA2_BITS 16 42242 #define PCS_IEEE2BLK_PCS_SEEDA2_SEEDA2_SHIFT 0 42243 42244 42245 /**************************************************************************** 42246 * PCS_ieee2Blk :: PCS_seedA3 42247 */ 42248 /* PCS_ieee2Blk :: PCS_seedA3 :: reserved0 [15:10] */ 42249 #define PCS_IEEE2BLK_PCS_SEEDA3_RESERVED0_MASK 0xfc00 42250 #define PCS_IEEE2BLK_PCS_SEEDA3_RESERVED0_ALIGN 0 42251 #define PCS_IEEE2BLK_PCS_SEEDA3_RESERVED0_BITS 6 42252 #define PCS_IEEE2BLK_PCS_SEEDA3_RESERVED0_SHIFT 10 42253 42254 /* PCS_ieee2Blk :: PCS_seedA3 :: seedA3 [09:00] */ 42255 #define PCS_IEEE2BLK_PCS_SEEDA3_SEEDA3_MASK 0x03ff 42256 #define PCS_IEEE2BLK_PCS_SEEDA3_SEEDA3_ALIGN 0 42257 #define PCS_IEEE2BLK_PCS_SEEDA3_SEEDA3_BITS 10 42258 #define PCS_IEEE2BLK_PCS_SEEDA3_SEEDA3_SHIFT 0 42259 42260 42261 /**************************************************************************** 42262 * PCS_ieee2Blk :: PCS_seedB0 42263 */ 42264 /* PCS_ieee2Blk :: PCS_seedB0 :: seedB0 [15:00] */ 42265 #define PCS_IEEE2BLK_PCS_SEEDB0_SEEDB0_MASK 0xffff 42266 #define PCS_IEEE2BLK_PCS_SEEDB0_SEEDB0_ALIGN 0 42267 #define PCS_IEEE2BLK_PCS_SEEDB0_SEEDB0_BITS 16 42268 #define PCS_IEEE2BLK_PCS_SEEDB0_SEEDB0_SHIFT 0 42269 42270 42271 /**************************************************************************** 42272 * PCS_ieee2Blk :: PCS_seedB1 42273 */ 42274 /* PCS_ieee2Blk :: PCS_seedB1 :: seedB1 [15:00] */ 42275 #define PCS_IEEE2BLK_PCS_SEEDB1_SEEDB1_MASK 0xffff 42276 #define PCS_IEEE2BLK_PCS_SEEDB1_SEEDB1_ALIGN 0 42277 #define PCS_IEEE2BLK_PCS_SEEDB1_SEEDB1_BITS 16 42278 #define PCS_IEEE2BLK_PCS_SEEDB1_SEEDB1_SHIFT 0 42279 42280 42281 /**************************************************************************** 42282 * PCS_ieee2Blk :: PCS_seedB2 42283 */ 42284 /* PCS_ieee2Blk :: PCS_seedB2 :: seedB2 [15:00] */ 42285 #define PCS_IEEE2BLK_PCS_SEEDB2_SEEDB2_MASK 0xffff 42286 #define PCS_IEEE2BLK_PCS_SEEDB2_SEEDB2_ALIGN 0 42287 #define PCS_IEEE2BLK_PCS_SEEDB2_SEEDB2_BITS 16 42288 #define PCS_IEEE2BLK_PCS_SEEDB2_SEEDB2_SHIFT 0 42289 42290 42291 /**************************************************************************** 42292 * PCS_ieee2Blk :: PCS_seedB3 42293 */ 42294 /* PCS_ieee2Blk :: PCS_seedB3 :: reserved0 [15:10] */ 42295 #define PCS_IEEE2BLK_PCS_SEEDB3_RESERVED0_MASK 0xfc00 42296 #define PCS_IEEE2BLK_PCS_SEEDB3_RESERVED0_ALIGN 0 42297 #define PCS_IEEE2BLK_PCS_SEEDB3_RESERVED0_BITS 6 42298 #define PCS_IEEE2BLK_PCS_SEEDB3_RESERVED0_SHIFT 10 42299 42300 /* PCS_ieee2Blk :: PCS_seedB3 :: seedB3 [09:00] */ 42301 #define PCS_IEEE2BLK_PCS_SEEDB3_SEEDB3_MASK 0x03ff 42302 #define PCS_IEEE2BLK_PCS_SEEDB3_SEEDB3_ALIGN 0 42303 #define PCS_IEEE2BLK_PCS_SEEDB3_SEEDB3_BITS 10 42304 #define PCS_IEEE2BLK_PCS_SEEDB3_SEEDB3_SHIFT 0 42305 42306 42307 /**************************************************************************** 42308 * PCS_ieee2Blk :: PCS_tpControl 42309 */ 42310 /* PCS_ieee2Blk :: PCS_tpControl :: reserved0 [15:07] */ 42311 #define PCS_IEEE2BLK_PCS_TPCONTROL_RESERVED0_MASK 0xff80 42312 #define PCS_IEEE2BLK_PCS_TPCONTROL_RESERVED0_ALIGN 0 42313 #define PCS_IEEE2BLK_PCS_TPCONTROL_RESERVED0_BITS 9 42314 #define PCS_IEEE2BLK_PCS_TPCONTROL_RESERVED0_SHIFT 7 42315 42316 /* PCS_ieee2Blk :: PCS_tpControl :: prbs9tx_en [06:06] */ 42317 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_MASK 0x0040 42318 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_ALIGN 0 42319 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_BITS 1 42320 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_SHIFT 6 42321 42322 /* PCS_ieee2Blk :: PCS_tpControl :: prbs31rx_en [05:05] */ 42323 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_MASK 0x0020 42324 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_ALIGN 0 42325 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_BITS 1 42326 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_SHIFT 5 42327 42328 /* PCS_ieee2Blk :: PCS_tpControl :: prbs31tx_en [04:04] */ 42329 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_MASK 0x0010 42330 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_ALIGN 0 42331 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_BITS 1 42332 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_SHIFT 4 42333 42334 /* PCS_ieee2Blk :: PCS_tpControl :: tptx_en [03:03] */ 42335 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPTX_EN_MASK 0x0008 42336 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPTX_EN_ALIGN 0 42337 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPTX_EN_BITS 1 42338 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPTX_EN_SHIFT 3 42339 42340 /* PCS_ieee2Blk :: PCS_tpControl :: tprx_en [02:02] */ 42341 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPRX_EN_MASK 0x0004 42342 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPRX_EN_ALIGN 0 42343 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPRX_EN_BITS 1 42344 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPRX_EN_SHIFT 2 42345 42346 /* PCS_ieee2Blk :: PCS_tpControl :: tp_sel [01:01] */ 42347 #define PCS_IEEE2BLK_PCS_TPCONTROL_TP_SEL_MASK 0x0002 42348 #define PCS_IEEE2BLK_PCS_TPCONTROL_TP_SEL_ALIGN 0 42349 #define PCS_IEEE2BLK_PCS_TPCONTROL_TP_SEL_BITS 1 42350 #define PCS_IEEE2BLK_PCS_TPCONTROL_TP_SEL_SHIFT 1 42351 42352 /* PCS_ieee2Blk :: PCS_tpControl :: dp_sel [00:00] */ 42353 #define PCS_IEEE2BLK_PCS_TPCONTROL_DP_SEL_MASK 0x0001 42354 #define PCS_IEEE2BLK_PCS_TPCONTROL_DP_SEL_ALIGN 0 42355 #define PCS_IEEE2BLK_PCS_TPCONTROL_DP_SEL_BITS 1 42356 #define PCS_IEEE2BLK_PCS_TPCONTROL_DP_SEL_SHIFT 0 42357 42358 42359 /**************************************************************************** 42360 * PCS_ieee2Blk :: PCS_tpErrCounter 42361 */ 42362 /* PCS_ieee2Blk :: PCS_tpErrCounter :: tpErrCounter [15:00] */ 42363 #define PCS_IEEE2BLK_PCS_TPERRCOUNTER_TPERRCOUNTER_MASK 0xffff 42364 #define PCS_IEEE2BLK_PCS_TPERRCOUNTER_TPERRCOUNTER_ALIGN 0 42365 #define PCS_IEEE2BLK_PCS_TPERRCOUNTER_TPERRCOUNTER_BITS 16 42366 #define PCS_IEEE2BLK_PCS_TPERRCOUNTER_TPERRCOUNTER_SHIFT 0 42367 42368 42369 /**************************************************************************** 42370 * PCS_ieee2Blk :: BER_ho 42371 */ 42372 /* PCS_ieee2Blk :: BER_ho :: BER_ho_present [15:15] */ 42373 #define PCS_IEEE2BLK_BER_HO_BER_HO_PRESENT_MASK 0x8000 42374 #define PCS_IEEE2BLK_BER_HO_BER_HO_PRESENT_ALIGN 0 42375 #define PCS_IEEE2BLK_BER_HO_BER_HO_PRESENT_BITS 1 42376 #define PCS_IEEE2BLK_BER_HO_BER_HO_PRESENT_SHIFT 15 42377 42378 /* PCS_ieee2Blk :: BER_ho :: reserved0 [14:14] */ 42379 #define PCS_IEEE2BLK_BER_HO_RESERVED0_MASK 0x4000 42380 #define PCS_IEEE2BLK_BER_HO_RESERVED0_ALIGN 0 42381 #define PCS_IEEE2BLK_BER_HO_RESERVED0_BITS 1 42382 #define PCS_IEEE2BLK_BER_HO_RESERVED0_SHIFT 14 42383 42384 /* PCS_ieee2Blk :: BER_ho :: BER_ho [13:00] */ 42385 #define PCS_IEEE2BLK_BER_HO_BER_HO_MASK 0x3fff 42386 #define PCS_IEEE2BLK_BER_HO_BER_HO_ALIGN 0 42387 #define PCS_IEEE2BLK_BER_HO_BER_HO_BITS 14 42388 #define PCS_IEEE2BLK_BER_HO_BER_HO_SHIFT 0 42389 42390 42391 /**************************************************************************** 42392 * PCS_ieee2Blk :: errored_blocks_ho 42393 */ 42394 /* PCS_ieee2Blk :: errored_blocks_ho :: errored_blocks_ho_present [15:15] */ 42395 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_MASK 0x8000 42396 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_ALIGN 0 42397 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_BITS 1 42398 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_SHIFT 15 42399 42400 /* PCS_ieee2Blk :: errored_blocks_ho :: reserved0 [14:14] */ 42401 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_RESERVED0_MASK 0x4000 42402 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_RESERVED0_ALIGN 0 42403 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_RESERVED0_BITS 1 42404 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_RESERVED0_SHIFT 14 42405 42406 /* PCS_ieee2Blk :: errored_blocks_ho :: errored_blocks_ho [13:00] */ 42407 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_MASK 0x3fff 42408 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_ALIGN 0 42409 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_BITS 14 42410 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_SHIFT 0 42411 42412 42413 /**************************************************************************** 42414 * Warpcore_IEEE_PCS_PCS_ieee3Blk 42415 */ 42416 /**************************************************************************** 42417 * PCS_ieee3Blk :: multi_lane_status_1 42418 */ 42419 /* PCS_ieee3Blk :: multi_lane_status_1 :: reserved0 [15:13] */ 42420 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED0_MASK 0xe000 42421 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED0_ALIGN 0 42422 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED0_BITS 3 42423 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED0_SHIFT 13 42424 42425 /* PCS_ieee3Blk :: multi_lane_status_1 :: align_status [12:12] */ 42426 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_ALIGN_STATUS_MASK 0x1000 42427 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_ALIGN_STATUS_ALIGN 0 42428 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_ALIGN_STATUS_BITS 1 42429 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_ALIGN_STATUS_SHIFT 12 42430 42431 /* PCS_ieee3Blk :: multi_lane_status_1 :: reserved1 [11:04] */ 42432 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED1_MASK 0x0ff0 42433 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED1_ALIGN 0 42434 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED1_BITS 8 42435 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED1_SHIFT 4 42436 42437 /* PCS_ieee3Blk :: multi_lane_status_1 :: lane_3_lock [03:03] */ 42438 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_3_LOCK_MASK 0x0008 42439 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_3_LOCK_ALIGN 0 42440 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_3_LOCK_BITS 1 42441 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_3_LOCK_SHIFT 3 42442 42443 /* PCS_ieee3Blk :: multi_lane_status_1 :: lane_2_lock [02:02] */ 42444 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_2_LOCK_MASK 0x0004 42445 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_2_LOCK_ALIGN 0 42446 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_2_LOCK_BITS 1 42447 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_2_LOCK_SHIFT 2 42448 42449 /* PCS_ieee3Blk :: multi_lane_status_1 :: lane_1_lock [01:01] */ 42450 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_1_LOCK_MASK 0x0002 42451 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_1_LOCK_ALIGN 0 42452 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_1_LOCK_BITS 1 42453 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_1_LOCK_SHIFT 1 42454 42455 /* PCS_ieee3Blk :: multi_lane_status_1 :: lane_0_lock [00:00] */ 42456 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_0_LOCK_MASK 0x0001 42457 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_0_LOCK_ALIGN 0 42458 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_0_LOCK_BITS 1 42459 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_0_LOCK_SHIFT 0 42460 42461 42462 /**************************************************************************** 42463 * PCS_ieee3Blk :: multi_lane_status_3 42464 */ 42465 /* PCS_ieee3Blk :: multi_lane_status_3 :: reserved0 [15:04] */ 42466 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_RESERVED0_MASK 0xfff0 42467 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_RESERVED0_ALIGN 0 42468 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_RESERVED0_BITS 12 42469 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_RESERVED0_SHIFT 4 42470 42471 /* PCS_ieee3Blk :: multi_lane_status_3 :: am_3_lock [03:03] */ 42472 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_3_LOCK_MASK 0x0008 42473 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_3_LOCK_ALIGN 0 42474 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_3_LOCK_BITS 1 42475 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_3_LOCK_SHIFT 3 42476 42477 /* PCS_ieee3Blk :: multi_lane_status_3 :: am_2_lock [02:02] */ 42478 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_2_LOCK_MASK 0x0004 42479 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_2_LOCK_ALIGN 0 42480 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_2_LOCK_BITS 1 42481 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_2_LOCK_SHIFT 2 42482 42483 /* PCS_ieee3Blk :: multi_lane_status_3 :: am_1_lock [01:01] */ 42484 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_1_LOCK_MASK 0x0002 42485 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_1_LOCK_ALIGN 0 42486 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_1_LOCK_BITS 1 42487 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_1_LOCK_SHIFT 1 42488 42489 /* PCS_ieee3Blk :: multi_lane_status_3 :: am_0_lock [00:00] */ 42490 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_0_LOCK_MASK 0x0001 42491 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_0_LOCK_ALIGN 0 42492 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_0_LOCK_BITS 1 42493 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_0_LOCK_SHIFT 0 42494 42495 42496 /**************************************************************************** 42497 * Warpcore_IEEE_PCS_PCS_ieee5Blk 42498 */ 42499 /**************************************************************************** 42500 * PCS_ieee5Blk :: BIP_error_counter_ln01 42501 */ 42502 /* PCS_ieee5Blk :: BIP_error_counter_ln01 :: BIP_err_count_ln1 [15:08] */ 42503 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN1_MASK 0xff00 42504 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN1_ALIGN 0 42505 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN1_BITS 8 42506 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN1_SHIFT 8 42507 42508 /* PCS_ieee5Blk :: BIP_error_counter_ln01 :: BIP_err_count_ln0 [07:00] */ 42509 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN0_MASK 0x00ff 42510 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN0_ALIGN 0 42511 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN0_BITS 8 42512 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN0_SHIFT 0 42513 42514 42515 /**************************************************************************** 42516 * PCS_ieee5Blk :: BIP_error_counter_ln23 42517 */ 42518 /* PCS_ieee5Blk :: BIP_error_counter_ln23 :: BIP_err_count_ln3 [15:08] */ 42519 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN3_MASK 0xff00 42520 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN3_ALIGN 0 42521 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN3_BITS 8 42522 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN3_SHIFT 8 42523 42524 /* PCS_ieee5Blk :: BIP_error_counter_ln23 :: BIP_err_count_ln2 [07:00] */ 42525 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN2_MASK 0x00ff 42526 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN2_ALIGN 0 42527 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN2_BITS 8 42528 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN2_SHIFT 0 42529 42530 42531 /**************************************************************************** 42532 * Warpcore_IEEE_CL73_AN_ieee0Blk 42533 */ 42534 /**************************************************************************** 42535 * AN_ieee0Blk :: AN_ieeeControl1 42536 */ 42537 /* AN_ieee0Blk :: AN_ieeeControl1 :: rst_sw [15:15] */ 42538 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_MASK 0x8000 42539 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_ALIGN 0 42540 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_BITS 1 42541 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_SHIFT 15 42542 42543 /* AN_ieee0Blk :: AN_ieeeControl1 :: gloop10g [14:14] */ 42544 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_MASK 0x4000 42545 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_ALIGN 0 42546 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_BITS 1 42547 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_SHIFT 14 42548 42549 /* AN_ieee0Blk :: AN_ieeeControl1 :: ExtendNPen [13:13] */ 42550 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_MASK 0x2000 42551 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_ALIGN 0 42552 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_BITS 1 42553 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_SHIFT 13 42554 42555 /* AN_ieee0Blk :: AN_ieeeControl1 :: AN_enable [12:12] */ 42556 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_MASK 0x1000 42557 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_ALIGN 0 42558 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_BITS 1 42559 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_SHIFT 12 42560 42561 /* AN_ieee0Blk :: AN_ieeeControl1 :: reserved0 [11:10] */ 42562 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_MASK 0x0c00 42563 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_ALIGN 0 42564 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_BITS 2 42565 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_SHIFT 10 42566 42567 /* AN_ieee0Blk :: AN_ieeeControl1 :: restartAN [09:09] */ 42568 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_MASK 0x0200 42569 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_ALIGN 0 42570 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_BITS 1 42571 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_SHIFT 9 42572 42573 /* AN_ieee0Blk :: AN_ieeeControl1 :: reserved1 [08:00] */ 42574 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_MASK 0x01ff 42575 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_ALIGN 0 42576 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_BITS 9 42577 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_SHIFT 0 42578 42579 42580 /**************************************************************************** 42581 * AN_ieee0Blk :: AN_ieeeStatus1 42582 */ 42583 /* AN_ieee0Blk :: AN_ieeeStatus1 :: reserved0 [15:08] */ 42584 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_MASK 0xff00 42585 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_ALIGN 0 42586 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_BITS 8 42587 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_SHIFT 8 42588 42589 /* AN_ieee0Blk :: AN_ieeeStatus1 :: ExtendedNP_able [07:07] */ 42590 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_MASK 0x0080 42591 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_ALIGN 0 42592 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_BITS 1 42593 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_SHIFT 7 42594 42595 /* AN_ieee0Blk :: AN_ieeeStatus1 :: pageReceived [06:06] */ 42596 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_MASK 0x0040 42597 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_ALIGN 0 42598 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_BITS 1 42599 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_SHIFT 6 42600 42601 /* AN_ieee0Blk :: AN_ieeeStatus1 :: ANcomplete [05:05] */ 42602 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_MASK 0x0020 42603 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_ALIGN 0 42604 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_BITS 1 42605 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_SHIFT 5 42606 42607 /* AN_ieee0Blk :: AN_ieeeStatus1 :: remoteFault [04:04] */ 42608 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_MASK 0x0010 42609 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_ALIGN 0 42610 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_BITS 1 42611 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_SHIFT 4 42612 42613 /* AN_ieee0Blk :: AN_ieeeStatus1 :: ANability [03:03] */ 42614 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_MASK 0x0008 42615 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_ALIGN 0 42616 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_BITS 1 42617 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_SHIFT 3 42618 42619 /* AN_ieee0Blk :: AN_ieeeStatus1 :: linkStatus [02:02] */ 42620 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_MASK 0x0004 42621 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_ALIGN 0 42622 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_BITS 1 42623 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_SHIFT 2 42624 42625 /* AN_ieee0Blk :: AN_ieeeStatus1 :: reserved1 [01:01] */ 42626 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_MASK 0x0002 42627 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_ALIGN 0 42628 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_BITS 1 42629 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_SHIFT 1 42630 42631 /* AN_ieee0Blk :: AN_ieeeStatus1 :: LP_ANability [00:00] */ 42632 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_MASK 0x0001 42633 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_ALIGN 0 42634 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_BITS 1 42635 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_SHIFT 0 42636 42637 42638 /**************************************************************************** 42639 * AN_ieee0Blk :: AN_ieeeId1 42640 */ 42641 /* AN_ieee0Blk :: AN_ieeeId1 :: IEEEID1 [15:00] */ 42642 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_MASK 0xffff 42643 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_ALIGN 0 42644 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_BITS 16 42645 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_SHIFT 0 42646 42647 42648 /**************************************************************************** 42649 * AN_ieee0Blk :: AN_ieeeId2 42650 */ 42651 /* AN_ieee0Blk :: AN_ieeeId2 :: IEEEID2 [15:00] */ 42652 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_MASK 0xffff 42653 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_ALIGN 0 42654 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_BITS 16 42655 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_SHIFT 0 42656 42657 42658 /**************************************************************************** 42659 * AN_ieee0Blk :: AN_ieeeDevInPkg2 42660 */ 42661 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: reserved0 [15:08] */ 42662 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_MASK 0xff00 42663 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_ALIGN 0 42664 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_BITS 8 42665 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_SHIFT 8 42666 42667 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: AN [07:07] */ 42668 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_AN_MASK 0x0080 42669 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_AN_ALIGN 0 42670 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_AN_BITS 1 42671 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_AN_SHIFT 7 42672 42673 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: TC [06:06] */ 42674 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_TC_MASK 0x0040 42675 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_TC_ALIGN 0 42676 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_TC_BITS 1 42677 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_TC_SHIFT 6 42678 42679 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: DTE_XS [05:05] */ 42680 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_DTE_XS_MASK 0x0020 42681 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_DTE_XS_ALIGN 0 42682 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_DTE_XS_BITS 1 42683 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_DTE_XS_SHIFT 5 42684 42685 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: PHY_XS [04:04] */ 42686 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PHY_XS_MASK 0x0010 42687 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PHY_XS_ALIGN 0 42688 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PHY_XS_BITS 1 42689 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PHY_XS_SHIFT 4 42690 42691 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: PCS_XS [03:03] */ 42692 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PCS_XS_MASK 0x0008 42693 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PCS_XS_ALIGN 0 42694 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PCS_XS_BITS 1 42695 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PCS_XS_SHIFT 3 42696 42697 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: WIS [02:02] */ 42698 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_WIS_MASK 0x0004 42699 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_WIS_ALIGN 0 42700 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_WIS_BITS 1 42701 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_WIS_SHIFT 2 42702 42703 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: PMA_PMD [01:01] */ 42704 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PMA_PMD_MASK 0x0002 42705 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PMA_PMD_ALIGN 0 42706 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PMA_PMD_BITS 1 42707 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_PMA_PMD_SHIFT 1 42708 42709 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: Clause22 [00:00] */ 42710 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CLAUSE22_MASK 0x0001 42711 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CLAUSE22_ALIGN 0 42712 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CLAUSE22_BITS 1 42713 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CLAUSE22_SHIFT 0 42714 42715 42716 /**************************************************************************** 42717 * AN_ieee0Blk :: AN_ieeeDevInPkg1 42718 */ 42719 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: Vendor2 [15:15] */ 42720 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_VENDOR2_MASK 0x8000 42721 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_VENDOR2_ALIGN 0 42722 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_VENDOR2_BITS 1 42723 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_VENDOR2_SHIFT 15 42724 42725 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: Vendor1 [14:14] */ 42726 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_VENDOR1_MASK 0x4000 42727 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_VENDOR1_ALIGN 0 42728 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_VENDOR1_BITS 1 42729 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_VENDOR1_SHIFT 14 42730 42731 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: CL22ext [13:13] */ 42732 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CL22EXT_MASK 0x2000 42733 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CL22EXT_ALIGN 0 42734 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CL22EXT_BITS 1 42735 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CL22EXT_SHIFT 13 42736 42737 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: reserved0 [12:00] */ 42738 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_MASK 0x1fff 42739 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_ALIGN 0 42740 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_BITS 13 42741 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_SHIFT 0 42742 42743 42744 /**************************************************************************** 42745 * Warpcore_IEEE_CL73_AN_ieee1Blk 42746 */ 42747 /**************************************************************************** 42748 * AN_ieee1Blk :: AN_advertisement0 42749 */ 42750 /* AN_ieee1Blk :: AN_advertisement0 :: NP [15:15] */ 42751 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_MASK 0x8000 42752 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_ALIGN 0 42753 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_BITS 1 42754 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_SHIFT 15 42755 42756 /* AN_ieee1Blk :: AN_advertisement0 :: Ack [14:14] */ 42757 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_MASK 0x4000 42758 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_ALIGN 0 42759 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_BITS 1 42760 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_SHIFT 14 42761 42762 /* AN_ieee1Blk :: AN_advertisement0 :: RF [13:13] */ 42763 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_MASK 0x2000 42764 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_ALIGN 0 42765 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_BITS 1 42766 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_SHIFT 13 42767 42768 /* AN_ieee1Blk :: AN_advertisement0 :: pause [12:10] */ 42769 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_PAUSE_MASK 0x1c00 42770 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_PAUSE_ALIGN 0 42771 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_PAUSE_BITS 3 42772 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_PAUSE_SHIFT 10 42773 42774 /* AN advertisement 0 pause fields. hand added */ 42775 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_PAUSE_pause_MASK 0x0800 42776 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_PAUSE_asm_dir_MASK 0x0400 42777 42778 /* AN_ieee1Blk :: AN_advertisement0 :: echoed_nonce [09:05] */ 42779 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ECHOED_NONCE_MASK 0x03e0 42780 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ECHOED_NONCE_ALIGN 0 42781 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ECHOED_NONCE_BITS 5 42782 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ECHOED_NONCE_SHIFT 5 42783 42784 /* AN_ieee1Blk :: AN_advertisement0 :: selector [04:00] */ 42785 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_MASK 0x001f 42786 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_ALIGN 0 42787 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_BITS 5 42788 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_SHIFT 0 42789 42790 42791 /**************************************************************************** 42792 * AN_ieee1Blk :: AN_advertisement1 42793 */ 42794 /* AN_ieee1Blk :: AN_advertisement1 :: techAbility [15:05] */ 42795 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECHABILITY_MASK 0xffe0 42796 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECHABILITY_ALIGN 0 42797 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECHABILITY_BITS 11 42798 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECHABILITY_SHIFT 5 42799 42800 /* hand added */ 42801 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECH_ABILITY_100G_CR10_MASK 0x0400 42802 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECH_ABILITY_40G_CR4_MASK 0x0200 42803 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECH_ABILITY_40G_KR4_MASK 0x0100 42804 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECH_ABILITY_10G_KR_MASK 0x0080 42805 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECH_ABILITY_10G_KX4_MASK 0x0040 42806 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECH_ABILITY_1G_KX_MASK 0x0020 42807 42808 /* AN_ieee1Blk :: AN_advertisement1 :: transmitted_nonce [04:00] */ 42809 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TRANSMITTED_NONCE_MASK 0x001f 42810 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TRANSMITTED_NONCE_ALIGN 0 42811 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TRANSMITTED_NONCE_BITS 5 42812 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TRANSMITTED_NONCE_SHIFT 0 42813 42814 42815 /**************************************************************************** 42816 * AN_ieee1Blk :: AN_advertisement2 42817 */ 42818 /* AN_ieee1Blk :: AN_advertisement2 :: fec_requested [15:14] */ 42819 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_FEC_REQUESTED_MASK 0xc000 42820 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_FEC_REQUESTED_ALIGN 0 42821 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_FEC_REQUESTED_BITS 2 42822 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_FEC_REQUESTED_SHIFT 14 42823 42824 /* AN advertisement 2 fec fields */ 42825 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_FEC_REQUESTED_fec_requested_MASK 0x8000 42826 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_FEC_REQUESTED_fec_ability_MASK 0x8000 42827 42828 /* AN_ieee1Blk :: AN_advertisement2 :: reserved0 [13:00] */ 42829 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_RESERVED0_MASK 0x3fff 42830 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_RESERVED0_ALIGN 0 42831 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_RESERVED0_BITS 14 42832 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_RESERVED0_SHIFT 0 42833 42834 42835 /**************************************************************************** 42836 * AN_ieee1Blk :: AN_LP_basePageAbility0 42837 */ 42838 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: NP [15:15] */ 42839 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_MASK 0x8000 42840 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_ALIGN 0 42841 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_BITS 1 42842 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_SHIFT 15 42843 42844 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: Ack [14:14] */ 42845 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_MASK 0x4000 42846 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_ALIGN 0 42847 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_BITS 1 42848 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_SHIFT 14 42849 42850 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: RF [13:13] */ 42851 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_MASK 0x2000 42852 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_ALIGN 0 42853 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_BITS 1 42854 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_SHIFT 13 42855 42856 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: pause [12:10] */ 42857 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_PAUSE_MASK 0x1c00 42858 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_PAUSE_ALIGN 0 42859 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_PAUSE_BITS 3 42860 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_PAUSE_SHIFT 10 42861 42862 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: echoed_nonce [09:05] */ 42863 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ECHOED_NONCE_MASK 0x03e0 42864 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ECHOED_NONCE_ALIGN 0 42865 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ECHOED_NONCE_BITS 5 42866 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ECHOED_NONCE_SHIFT 5 42867 42868 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: selector [04:00] */ 42869 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_MASK 0x001f 42870 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_ALIGN 0 42871 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_BITS 5 42872 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_SHIFT 0 42873 42874 42875 /**************************************************************************** 42876 * AN_ieee1Blk :: AN_LP_basePageAbility1 42877 */ 42878 /* AN_ieee1Blk :: AN_LP_basePageAbility1 :: techAbility [15:05] */ 42879 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TECHABILITY_MASK 0xffe0 42880 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TECHABILITY_ALIGN 0 42881 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TECHABILITY_BITS 11 42882 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TECHABILITY_SHIFT 5 42883 42884 /* AN_ieee1Blk :: AN_LP_basePageAbility1 :: transmitted_nonce [04:00] */ 42885 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TRANSMITTED_NONCE_MASK 0x001f 42886 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TRANSMITTED_NONCE_ALIGN 0 42887 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TRANSMITTED_NONCE_BITS 5 42888 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TRANSMITTED_NONCE_SHIFT 0 42889 42890 42891 /**************************************************************************** 42892 * AN_ieee1Blk :: AN_LP_basePageAbility2 42893 */ 42894 /* AN_ieee1Blk :: AN_LP_basePageAbility2 :: fec_requested [15:14] */ 42895 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_FEC_REQUESTED_MASK 0xc000 42896 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_FEC_REQUESTED_ALIGN 0 42897 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_FEC_REQUESTED_BITS 2 42898 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_FEC_REQUESTED_SHIFT 14 42899 42900 /* AN_ieee1Blk :: AN_LP_basePageAbility2 :: reserved0 [13:00] */ 42901 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_RESERVED0_MASK 0x3fff 42902 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_RESERVED0_ALIGN 0 42903 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_RESERVED0_BITS 14 42904 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_RESERVED0_SHIFT 0 42905 42906 42907 /**************************************************************************** 42908 * AN_ieee1Blk :: AN_XNP_transmit0 42909 */ 42910 /* AN_ieee1Blk :: AN_XNP_transmit0 :: NP [15:15] */ 42911 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_MASK 0x8000 42912 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_ALIGN 0 42913 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_BITS 1 42914 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_SHIFT 15 42915 42916 /* AN_ieee1Blk :: AN_XNP_transmit0 :: reserved0 [14:14] */ 42917 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_MASK 0x4000 42918 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_ALIGN 0 42919 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_BITS 1 42920 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_SHIFT 14 42921 42922 /* AN_ieee1Blk :: AN_XNP_transmit0 :: MP [13:13] */ 42923 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_MASK 0x2000 42924 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_ALIGN 0 42925 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_BITS 1 42926 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_SHIFT 13 42927 42928 /* AN_ieee1Blk :: AN_XNP_transmit0 :: Ack2 [12:12] */ 42929 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_MASK 0x1000 42930 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_ALIGN 0 42931 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_BITS 1 42932 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_SHIFT 12 42933 42934 /* AN_ieee1Blk :: AN_XNP_transmit0 :: Toggle [11:11] */ 42935 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_MASK 0x0800 42936 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_ALIGN 0 42937 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_BITS 1 42938 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_SHIFT 11 42939 42940 /* AN_ieee1Blk :: AN_XNP_transmit0 :: MSG [10:00] */ 42941 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_MASK 0x07ff 42942 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_ALIGN 0 42943 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_BITS 11 42944 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_SHIFT 0 42945 42946 42947 /**************************************************************************** 42948 * AN_ieee1Blk :: AN_XNP_transmit1 42949 */ 42950 /* AN_ieee1Blk :: AN_XNP_transmit1 :: UCF1 [15:00] */ 42951 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_MASK 0xffff 42952 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_ALIGN 0 42953 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_BITS 16 42954 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_SHIFT 0 42955 42956 42957 /**************************************************************************** 42958 * AN_ieee1Blk :: AN_XNP_transmit2 42959 */ 42960 /* AN_ieee1Blk :: AN_XNP_transmit2 :: UCF2 [15:00] */ 42961 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_MASK 0xffff 42962 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_ALIGN 0 42963 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_BITS 16 42964 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_SHIFT 0 42965 42966 42967 /**************************************************************************** 42968 * AN_ieee1Blk :: AN_LP_XNP_ability0 42969 */ 42970 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: NP [15:15] */ 42971 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_MASK 0x8000 42972 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_ALIGN 0 42973 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_BITS 1 42974 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_SHIFT 15 42975 42976 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: reserved0 [14:14] */ 42977 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_MASK 0x4000 42978 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_ALIGN 0 42979 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_BITS 1 42980 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_SHIFT 14 42981 42982 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: MP [13:13] */ 42983 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_MASK 0x2000 42984 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_ALIGN 0 42985 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_BITS 1 42986 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_SHIFT 13 42987 42988 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: Ack2 [12:12] */ 42989 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_MASK 0x1000 42990 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_ALIGN 0 42991 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_BITS 1 42992 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_SHIFT 12 42993 42994 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: Toggle [11:11] */ 42995 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_MASK 0x0800 42996 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_ALIGN 0 42997 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_BITS 1 42998 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_SHIFT 11 42999 43000 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: MSG [10:00] */ 43001 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_MASK 0x07ff 43002 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_ALIGN 0 43003 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_BITS 11 43004 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_SHIFT 0 43005 43006 43007 /**************************************************************************** 43008 * AN_ieee1Blk :: AN_LP_XNP_ability1 43009 */ 43010 /* AN_ieee1Blk :: AN_LP_XNP_ability1 :: UCF1 [15:00] */ 43011 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_MASK 0xffff 43012 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_ALIGN 0 43013 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_BITS 16 43014 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_SHIFT 0 43015 43016 43017 /**************************************************************************** 43018 * AN_ieee1Blk :: AN_LP_XNP_ability2 43019 */ 43020 /* AN_ieee1Blk :: AN_LP_XNP_ability2 :: UCF2 [15:00] */ 43021 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_MASK 0xffff 43022 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_ALIGN 0 43023 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_BITS 16 43024 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_SHIFT 0 43025 43026 43027 /**************************************************************************** 43028 * Warpcore_IEEE_CL73_AN_ieee3Blk 43029 */ 43030 /**************************************************************************** 43031 * AN_ieee3Blk :: AN_BPstatus 43032 */ 43033 /* AN_ieee3Blk :: AN_BPstatus :: reserved0 [15:09] */ 43034 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_MASK 0xfe00 43035 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_ALIGN 0 43036 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_BITS 7 43037 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_SHIFT 9 43038 43039 /* AN_ieee3Blk :: AN_BPstatus :: CR10 [08:08] */ 43040 #define AN_IEEE3BLK_AN_BPSTATUS_CR10_MASK 0x0100 43041 #define AN_IEEE3BLK_AN_BPSTATUS_CR10_ALIGN 0 43042 #define AN_IEEE3BLK_AN_BPSTATUS_CR10_BITS 1 43043 #define AN_IEEE3BLK_AN_BPSTATUS_CR10_SHIFT 8 43044 43045 /* AN_ieee3Blk :: AN_BPstatus :: reserved1 [07:07] */ 43046 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_MASK 0x0080 43047 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_ALIGN 0 43048 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_BITS 1 43049 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_SHIFT 7 43050 43051 /* AN_ieee3Blk :: AN_BPstatus :: CR4 [06:06] */ 43052 #define AN_IEEE3BLK_AN_BPSTATUS_CR4_MASK 0x0040 43053 #define AN_IEEE3BLK_AN_BPSTATUS_CR4_ALIGN 0 43054 #define AN_IEEE3BLK_AN_BPSTATUS_CR4_BITS 1 43055 #define AN_IEEE3BLK_AN_BPSTATUS_CR4_SHIFT 6 43056 43057 /* AN_ieee3Blk :: AN_BPstatus :: KR4 [05:05] */ 43058 #define AN_IEEE3BLK_AN_BPSTATUS_KR4_MASK 0x0020 43059 #define AN_IEEE3BLK_AN_BPSTATUS_KR4_ALIGN 0 43060 #define AN_IEEE3BLK_AN_BPSTATUS_KR4_BITS 1 43061 #define AN_IEEE3BLK_AN_BPSTATUS_KR4_SHIFT 5 43062 43063 /* AN_ieee3Blk :: AN_BPstatus :: R_with_FEC [04:04] */ 43064 #define AN_IEEE3BLK_AN_BPSTATUS_R_WITH_FEC_MASK 0x0010 43065 #define AN_IEEE3BLK_AN_BPSTATUS_R_WITH_FEC_ALIGN 0 43066 #define AN_IEEE3BLK_AN_BPSTATUS_R_WITH_FEC_BITS 1 43067 #define AN_IEEE3BLK_AN_BPSTATUS_R_WITH_FEC_SHIFT 4 43068 43069 /* AN_ieee3Blk :: AN_BPstatus :: KR [03:03] */ 43070 #define AN_IEEE3BLK_AN_BPSTATUS_KR_MASK 0x0008 43071 #define AN_IEEE3BLK_AN_BPSTATUS_KR_ALIGN 0 43072 #define AN_IEEE3BLK_AN_BPSTATUS_KR_BITS 1 43073 #define AN_IEEE3BLK_AN_BPSTATUS_KR_SHIFT 3 43074 43075 /* AN_ieee3Blk :: AN_BPstatus :: KX4 [02:02] */ 43076 #define AN_IEEE3BLK_AN_BPSTATUS_KX4_MASK 0x0004 43077 #define AN_IEEE3BLK_AN_BPSTATUS_KX4_ALIGN 0 43078 #define AN_IEEE3BLK_AN_BPSTATUS_KX4_BITS 1 43079 #define AN_IEEE3BLK_AN_BPSTATUS_KX4_SHIFT 2 43080 43081 /* AN_ieee3Blk :: AN_BPstatus :: KX [01:01] */ 43082 #define AN_IEEE3BLK_AN_BPSTATUS_KX_MASK 0x0002 43083 #define AN_IEEE3BLK_AN_BPSTATUS_KX_ALIGN 0 43084 #define AN_IEEE3BLK_AN_BPSTATUS_KX_BITS 1 43085 #define AN_IEEE3BLK_AN_BPSTATUS_KX_SHIFT 1 43086 43087 /* AN_ieee3Blk :: AN_BPstatus :: BP_AN_ability [00:00] */ 43088 #define AN_IEEE3BLK_AN_BPSTATUS_BP_AN_ABILITY_MASK 0x0001 43089 #define AN_IEEE3BLK_AN_BPSTATUS_BP_AN_ABILITY_ALIGN 0 43090 #define AN_IEEE3BLK_AN_BPSTATUS_BP_AN_ABILITY_BITS 1 43091 #define AN_IEEE3BLK_AN_BPSTATUS_BP_AN_ABILITY_SHIFT 0 43092 43093 43094 /**************************************************************************** 43095 * AN_ieee3Blk :: EEE_adv 43096 */ 43097 /* AN_ieee3Blk :: EEE_adv :: reserved0 [15:07] */ 43098 #define AN_IEEE3BLK_EEE_ADV_RESERVED0_MASK 0xff80 43099 #define AN_IEEE3BLK_EEE_ADV_RESERVED0_ALIGN 0 43100 #define AN_IEEE3BLK_EEE_ADV_RESERVED0_BITS 9 43101 #define AN_IEEE3BLK_EEE_ADV_RESERVED0_SHIFT 7 43102 43103 /* AN_ieee3Blk :: EEE_adv :: EEE_10G_KR [06:06] */ 43104 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KR_MASK 0x0040 43105 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KR_ALIGN 0 43106 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KR_BITS 1 43107 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KR_SHIFT 6 43108 43109 /* AN_ieee3Blk :: EEE_adv :: EEE_10G_KX4 [05:05] */ 43110 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KX4_MASK 0x0020 43111 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KX4_ALIGN 0 43112 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KX4_BITS 1 43113 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KX4_SHIFT 5 43114 43115 /* AN_ieee3Blk :: EEE_adv :: EEE_1G_KX [04:04] */ 43116 #define AN_IEEE3BLK_EEE_ADV_EEE_1G_KX_MASK 0x0010 43117 #define AN_IEEE3BLK_EEE_ADV_EEE_1G_KX_ALIGN 0 43118 #define AN_IEEE3BLK_EEE_ADV_EEE_1G_KX_BITS 1 43119 #define AN_IEEE3BLK_EEE_ADV_EEE_1G_KX_SHIFT 4 43120 43121 /* AN_ieee3Blk :: EEE_adv :: reserved1 [03:00] */ 43122 #define AN_IEEE3BLK_EEE_ADV_RESERVED1_MASK 0x000f 43123 #define AN_IEEE3BLK_EEE_ADV_RESERVED1_ALIGN 0 43124 #define AN_IEEE3BLK_EEE_ADV_RESERVED1_BITS 4 43125 #define AN_IEEE3BLK_EEE_ADV_RESERVED1_SHIFT 0 43126 43127 43128 /**************************************************************************** 43129 * AN_ieee3Blk :: EEE_lp_adv 43130 */ 43131 /* AN_ieee3Blk :: EEE_lp_adv :: reserved0 [15:07] */ 43132 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED0_MASK 0xff80 43133 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED0_ALIGN 0 43134 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED0_BITS 9 43135 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED0_SHIFT 7 43136 43137 /* AN_ieee3Blk :: EEE_lp_adv :: EEE_10G_KR [06:06] */ 43138 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KR_MASK 0x0040 43139 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KR_ALIGN 0 43140 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KR_BITS 1 43141 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KR_SHIFT 6 43142 43143 /* AN_ieee3Blk :: EEE_lp_adv :: EEE_10G_KX4 [05:05] */ 43144 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KX4_MASK 0x0020 43145 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KX4_ALIGN 0 43146 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KX4_BITS 1 43147 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KX4_SHIFT 5 43148 43149 /* AN_ieee3Blk :: EEE_lp_adv :: EEE_1G_KX [04:04] */ 43150 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_1G_KX_MASK 0x0010 43151 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_1G_KX_ALIGN 0 43152 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_1G_KX_BITS 1 43153 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_1G_KX_SHIFT 4 43154 43155 /* AN_ieee3Blk :: EEE_lp_adv :: reserved1 [03:00] */ 43156 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED1_MASK 0x000f 43157 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED1_ALIGN 0 43158 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED1_BITS 4 43159 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED1_SHIFT 0 43160 43161 /**************************************************************************** 43162 * Datatype Definitions. 43163 */ 43164 #endif /* #ifndef _WCMOD_H_ */ 43165 43166 /* End of File */ 43167