wc40_extra.h (23023B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: wc40_extra.h 8 * Purpose: non-register Macro, data structures and function prototypes for WC driver. 9 */ 10 11 #ifndef WC40_EXTRA_H__ 12 #define WC40_EXTRA_H__ 13 14 /* 15 * wc40.h has definitions related to WC registers. It is automatically generated 16 * from RDB files. This file has all non-register Macro, data structures and 17 * function prototypes the WC driver. 18 */ 19 20 /* additional missed register definitions */ 21 22 #define WC40_XGXSBLK0_XGXSSTATUSr 0x8001 23 #define WC40_TX0_ANATXACONTROL0r 0x8061 24 #define WC40_RX0_ANARXCONTROLPCIr 0x80ba 25 #define WC40_COMBO_IEEE0_MIICNTLr 0xffe0 26 #define WC40_MICROBLK_DOWNLOAD_STATUSr 0xffc5 27 #define SERDESDIGITAL_FORCE_SPEED_dr_10G_XFI 0x25 28 #define SERDESDIGITAL_FORCE_SPEED_dr_10G_SFI 0x29 29 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_KR2 0x39 30 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_CR2 0x3a 31 #define DIGITAL4_MISC4_PCS_TYPE_AUTO_SELECT_MASK 0x8000 32 #define WC40_PER_LANE_TX_DRIVERr(lane) (0x8067 + (0x10*lane)) 33 34 /* misc. */ 35 36 #define WC40_PLL_WAIT 250000 37 #define WC40_AN_WAIT 400000 /* 400ms */ 38 #define TX_DRIVER_DFT_LN_CTRL 0x7fff 39 40 #define SERDES_ID0_MODEL_NUMBER_WARPCORE 0x9 41 #define WC_AER_BCST_OFS_STRAP 0x1ff 42 #define OVER1G_UP3_20GPLUS_MASK (DIGITAL3_UP3_DATARATE_25P45GX4_MASK | \ 43 DIGITAL3_UP3_DATARATE_21GX4_MASK | \ 44 DIGITAL3_UP3_DATARATE_31P5G_MASK | \ 45 DIGITAL3_UP3_DATARATE_40G_MASK | \ 46 DIGITAL3_UP3_LAST_MASK) 47 #define PLL_PLLACONTROL4_BIT12_MASK 0x1000 48 #define WC40_UCODE_MAX_LEN (32*1024) 49 #define NUM_LANES 4 50 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_40G_KR4 0x11 51 52 /* no clock comp in HG combo mode */ 53 #define COMBO_HG_XGXS_nLQnCC \ 54 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQnCC << \ 55 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT) 56 #define COMBO_HG_XGXS_nCC \ 57 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXG_nCC << \ 58 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT) 59 60 /* no clock comp in XE combo mode */ 61 #define COMBO_XE_XGXG_nCC \ 62 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXG_nCC << \ 63 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT) 64 65 /* clock comp in HG combo mode */ 66 #define COMBO_HG_XGXS_nLQ \ 67 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQ << \ 68 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT) 69 70 /* clock comp in XE combo mode */ 71 #define COMBO_XE_XGXS \ 72 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS << \ 73 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT) 74 75 #define COMBO_CLOCK_COMP_DEFAULT (COMBO_HG_XGXS_nLQnCC | COMBO_XE_XGXG_nCC) 76 #define COMBO_CLOCK_COMP_MASK (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_MASK | \ 77 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_MASK) 78 #define IND_CLOCK_COMP_DEFAULT (COMBO_HG_XGXS_nLQnCC | COMBO_XE_XGXG_nCC) 79 #define IND_CLOCK_COMP_DEFAULT_REV_A (COMBO_HG_XGXS_nLQ | COMBO_XE_XGXS) 80 81 /* WC revision IDs */ 82 83 #define WC40_SERDES_ID0_REVID_A0 0x0000 84 #define WC40_SERDES_ID0_REVID_A1 0x0800 85 #define WC40_SERDES_ID0_REVID_A2 0x1000 86 #define WC40_SERDES_ID0_REVID_A3 0x1800 87 #define WC40_SERDES_ID0_REVID_A4 0x2000 88 #define WC40_SERDES_ID0_REVID_B0 0x4000 89 #define WC40_SERDES_ID0_REVID_B1 0x4800 90 #define WC40_SERDES_ID0_REVID_C0 0x8000 91 #define WC40_SERDES_ID0_REVID_D0 0xc000 92 93 #define REV_VER_MASK (SERDESID_SERDESID0_REV_LETTER_MASK | \ 94 SERDESID_SERDESID0_REV_NUMBER_MASK) 95 #define WC40_REVID(_pc) \ 96 ((((WC40_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) 97 #define WC40_REVID_A0(_pc) \ 98 (((((WC40_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 99 WC40_SERDES_ID0_REVID_A0) 100 #define WC40_REVID_A1(_pc) \ 101 (((((WC40_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 102 WC40_SERDES_ID0_REVID_A1) 103 #define WC40_REVID_A2(_pc) \ 104 (((((WC40_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 105 WC40_SERDES_ID0_REVID_A2) 106 #define WC40_REVID_A3(_pc) \ 107 (((((WC40_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 108 WC40_SERDES_ID0_REVID_A3) 109 #define WC40_REVID_A4(_pc) \ 110 (((((WC40_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 111 WC40_SERDES_ID0_REVID_A4) 112 113 #define WC40_REVID_B0(_pc) \ 114 (((((WC40_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 115 WC40_SERDES_ID0_REVID_B0) 116 #define WC40_REVID_B1(_pc) \ 117 (((((WC40_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 118 WC40_SERDES_ID0_REVID_B1) 119 #define WC40_REVID_B(_pc) (WC40_REVID_B0(_pc) || WC40_REVID_B1(_pc)) 120 121 #define WC40_LINK_WAR_REVS(_pc) (WC40_REVID_A0(_pc) || WC40_REVID_A1(_pc)) 122 123 #define WC40_REVID_A(_pc) (WC40_REVID_A0(_pc) || WC40_REVID_A1(_pc) \ 124 || WC40_REVID_A2(_pc) || WC40_REVID_A3(_pc) \ 125 || WC40_REVID_A2(_pc)) 126 127 /* div16 and div33 clocks */ 128 129 #define CL72_MISC4_CTRL_DIV16_SHIFT 5 130 #define CL72_MISC4_CTRL_DIV33_SHIFT 3 131 #define CL72_MISC4_CTRL_DIV16_FIELD(_fd) ((_fd) << CL72_MISC4_CTRL_DIV16_SHIFT) 132 #define CL72_MISC4_CTRL_DIV33_FIELD(_fd) ((_fd) << CL72_MISC4_CTRL_DIV33_SHIFT) 133 #define CL72_MISC4_CTRL_DIV16_MASK (0xf << CL72_MISC4_CTRL_DIV16_SHIFT) 134 #define CL72_MISC4_CTRL_DIV33_MASK (0x3 << CL72_MISC4_CTRL_DIV33_SHIFT) 135 136 /* CL73 */ 137 138 #define CL73_AN_ADV_TECH_20G_KR2 (1 << 13) 139 #define CL73_AN_ADV_TECH_100G_CR10 (1 << 10) 140 #define CL73_AN_ADV_TECH_40G_CR4 (1 << 9) 141 #define CL73_AN_ADV_TECH_40G_KR4 (1 << 8) 142 #define CL73_AN_ADV_TECH_10G_KR (1 << 7) 143 #define CL73_AN_ADV_TECH_10G_KX4 (1 << 6) 144 #define CL73_AN_ADV_TECH_1G_KX (1 << 5) 145 #define CL73_AN_ADV_TECH_SPEEDS_MASK (0x3F << 5) 146 #define CL73_AN_ADV_PLUS_KR2_MASK (CL73_AN_ADV_TECH_SPEEDS_MASK | \ 147 CL73_AN_ADV_TECH_20G_KR2) 148 #define CL73_AN_ADV_PAUSE (1 << 10) 149 #define CL73_AN_ADV_ASYM_PAUSE (1 << 11) 150 #define DIGITAL6_UD_FIELD_UD_ADV_ID_MASK (3 << 9) 151 #define DIGITAL6_UD_FIELD_UD_ADV_ID_WC (1 << 10) 152 153 /* VCO frequency ctrl */ 154 155 #define WC40_OS5_VCO_FREQ 0x7200 156 #define WC40_OS8_VCO_FERQ 0x7A00 157 #define WC40_TXCK_MASK 0x1E0 158 #define WC40_RXCK_OVERIDE_MASK (1 << 11) 159 #define WC40_TXCK_SHIFTER 5 160 161 /* WC40_CL73_KR2 is the cl73 KR2 autoneg mode. In this mode 162 * CL37,CL37BAM and CL73BAM is disabled. The autoneg is in software 163 * controlled mode. 164 * 165 * WC40_CL73_KR2_CUSTOM_WAR: 166 * To workaroud the interop issue with legacy devices 167 * such as 8073. 8073 goes into lockup state if 168 * a base page with next page (KR2_CUSTOM) bit set 169 * is sent to it. It is a WAR placed on top of 170 * WC40_CL73_KR2_CUSTOM implementation of SOFT KR2. 171 * Similarly, WC40_CL73_KR2_WAR is for WC40_CL73_KR2. 172 * 173 * STATE_TIMER & STATE_WAIT_4_BP are added under this WAR 174 * STATE_TIMER: It starts the timer to squelch the tx for 175 * a fixed amount of time. 176 * STATE_WAIT_4_BP: It handles the base page received 177 * following the release of tx squelch. Drops it on 178 * the floor since h/w resolves the speed in that state. 179 */ 180 #define WC40_CL73_KR2_CUSTOM_WAR 6 181 #define WC40_CL73_KR2_WAR 5 182 #define WC40_CL73_KR2_CUSTOM 4 183 #define WC40_CL73_KR2 3 184 #define WC40_CL73_WO_CL73BAM 2 185 #define WC40_CL73_AND_CL73BAM 1 186 187 #define WC40_CL37_WO_CL37BAM 2 188 #define WC40_CL37_AND_CL37BAM 1 189 190 /* KR2 control */ 191 #define WC40_SOFT_KR2_STATE_INIT 0 192 #define WC40_SOFT_KR2_STATE_BASE_PAGE 1 193 #define WC40_SOFT_KR2_STATE_MP5 2 194 #define WC40_SOFT_KR2_STATE_UP1 3 195 #define WC40_SOFT_KR2_STATE_DONE 4 196 #define WC40_SOFT_KR2_STATE_TIMER 5 197 #define WC40_SOFT_KR2_STATE_WAIT_4_BP 6 198 #define WC40_SOFT_KR2_STATE_WAIT_4_NP 7 199 200 #define WC40_AUTONEG_MSG_MP5 0x5 201 #define WC40_AUTONEG_MSG_NULL 0x1 202 #define WC40_BRCM_OUI0 0 203 #define WC40_BRCM_OUI1 0x2bd 204 #define WC40_BRCM_CODE_BAM3 0x603 205 #define WC40_BRCM_ETA_KR2 0x1 206 207 /* lane swap functions in XGXSBLK2 are obsolete, use ones in XGXSBLK8 208 * i.e. define WC40_PCS_LANE_SWAP 209 */ 210 #define WC40_PCS_LANE_SWAP 211 #ifdef WC40_PCS_LANE_SWAP 212 /* For Tx lane swap 213 * bits 15-12 11-8 7-4 3-0 represents pma/pmd lane 3,2,1,0 214 * value in each field represents corresponding pcs lane number. 215 * the default map is pma/pmd lane3 maps to pcs lane3, pma lane2 216 * to pcs lane2 and so on. 217 * 218 * For Rx lane swap 219 * The same bit fields represents the pcs lane 3,2,1,0 220 * and the value corresponds the pma/pmd lane number. 221 */ 222 #define WC40_RX_LANE_MAP_DEFAULT 0x3210 223 #define WC40_TX_LANE_MAP_DEFAULT 0x3210 224 #else 225 #define WC40_RX_LANE_MAP_DEFAULT 0x0123 226 #define WC40_TX_LANE_MAP_DEFAULT 0x0123 227 #endif 228 229 /* Register lane access. fixed value, must not change */ 230 231 #define LANE0_ACCESS 1 232 #define LANE1_ACCESS 2 233 #define LANE2_ACCESS 3 234 #define LANE3_ACCESS 4 235 #define LANE_BCST 0xF 236 #define LANE_ACCESS_MASK 0xF 237 238 /* operation modes */ 239 240 #define CUSTOM1_MODE(_pc) ((_pc)->phy_mode == PHYCTRL_LANE_MODE_CUSTOM1) 241 #define CUSTOM_MODE(_pc) (((_pc)->phy_mode == PHYCTRL_LANE_MODE_CUSTOM) || \ 242 ((_pc)->phy_mode == PHYCTRL_LANE_MODE_CUSTOM_3p125MHZ)) 243 #define CUSTOMX_MODE(_pc) (CUSTOM_MODE(_pc) || CUSTOM1_MODE(_pc)) 244 #define IND_LANE_MODE(_mode) (((_mode)==xgxs_operationModes_Indlane_OS8) || \ 245 ((_mode)==xgxs_operationModes_IndLane_OS5)) 246 #define COMBO_LANE_MODE(_mode) ((_mode) == xgxs_operationModes_ComboCoreMode) 247 #define IS_SINGLE_LANE_IN_DUAL_PORT_MODE(_pc) ((_pc)->phy_mode == PHYCTRL_SINGLE_LANE_IN_DUAL_PORT_MODE) 248 #define IS_DUAL_LANE_PORT(_pc) (((_pc)->phy_mode == PHYCTRL_DUAL_LANE_PORT) || \ 249 CUSTOM1_MODE(_pc)) 250 #define DUAL_LANE_BCST_ENABLE(_pc) \ 251 do { \ 252 if (IS_DUAL_LANE_PORT(_pc)) { \ 253 DEV_CFG_PTR(_pc)->dxgxs = (_pc)->lane_num? 2 :1; \ 254 } \ 255 } while (0) 256 #define DUAL_LANE_BCST_DISABLE(_pc) \ 257 do { \ 258 if (IS_DUAL_LANE_PORT(_pc)) { \ 259 DEV_CFG_PTR(_pc)->dxgxs = 0; \ 260 } \ 261 } while (0) 262 #define AUTONEG_MODE_UNAVAIL(_pc) (CUSTOMX_MODE(_pc)) 263 264 #define WC40_REG_READ(_unit, _pc, _flags, _reg_addr, _val) \ 265 phy_wc40_reg_aer_read((_unit), (_pc),(_flags), (_reg_addr), (_val)) 266 267 #define WC40_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \ 268 phy_wc40_reg_aer_write((_unit), (_pc),(_flags), (_reg_addr), (_val)) 269 270 #define WC40_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \ 271 phy_wc40_reg_aer_modify((_unit), (_pc),(_flags), (_reg_addr), (_val),(_mask)) 272 273 #define WC40_MEM_ALLOC(_size,_name) sal_alloc(_size,_name) 274 #define WC40_MEM_SET(_dst,_val,_len) sal_memset(_dst,_val,_len) 275 #define WC40_UDELAY(_time) sal_udelay(_time) 276 #define WC40_USLEEP(_time) sal_usleep(_time) 277 278 #define FX100_CONTROL1_AUTODET_EN_MASK 4 279 #define WC40_IF_SR (1 << SOC_PORT_IF_SR) 280 #define WC40_IF_KR (1 << SOC_PORT_IF_KR) 281 #define WC40_IF_KR4 (1 << SOC_PORT_IF_KR4) 282 #define WC40_IF_CR (1 << SOC_PORT_IF_CR) 283 #define WC40_IF_CR4 (1 << SOC_PORT_IF_CR4) 284 #define WC40_IF_XFI (1 << SOC_PORT_IF_XFI) 285 #define WC40_IF_SFI (1 << SOC_PORT_IF_SFI) 286 #define WC40_IF_XLAUI (1 << SOC_PORT_IF_XLAUI) 287 #define WC40_IF_XGMII (1 << SOC_PORT_IF_XGMII) 288 289 290 #define WC40_40G_10G_INTF(_if) ((_if) == SOC_PORT_IF_KR4 || (_if) == SOC_PORT_IF_XLAUI || \ 291 (_if) == SOC_PORT_IF_CR4 || (_if) == SOC_PORT_IF_SR || \ 292 (_if) == SOC_PORT_IF_KR || (_if) == SOC_PORT_IF_CR || \ 293 (_if) == SOC_PORT_IF_XFI || (_if) == SOC_PORT_IF_SFI || \ 294 (_if) == SOC_PORT_IF_XGMII) 295 296 #define WC40_40G_10G_INTF_ALL (WC40_IF_KR4 | WC40_IF_XLAUI | WC40_IF_CR4 | WC40_IF_SR | \ 297 WC40_IF_KR | WC40_IF_CR | WC40_IF_XFI | WC40_IF_SFI | WC40_IF_XGMII) 298 299 #define WC40_UC_CTRL_OPT_PF_TEMP_COMP 0x8888 300 #define WC40_UC_CTRL_OPT_PF_TEMP_COMP_PER_LANE 0x8 301 #define WC40_UC_CTRL_CL72_WO_AN 0x7777 302 #define WC40_UC_CTRL_XLAUI 0x3333 303 #define WC40_UC_CTRL_SR4 0x1111 304 #define WC40_UC_CTRL_SFP_DAC 0x2 305 #define WC40_UC_CTRL_DEFAULT 0x0000 306 307 #define WC40_AN_WAIT_INTERVAL 1000000 /* 1 second */ 308 309 #define WC40_SP_TIME(_pc) \ 310 (DEV_CTRL_PTR(_pc)->lkwa.start_time) 311 #define WC40_SP_VALID(_pc) \ 312 (DEV_CTRL_PTR(_pc)->lkwa.state) 313 #define WC40_SP_CNT(_pc) \ 314 (DEV_CTRL_PTR(_pc)->lkwa.cnt) 315 316 #define WC40_SP_RECORD_TIME(_pc) \ 317 (DEV_CTRL_PTR(_pc)->lkwa.start_time) = sal_time_usecs() 318 #define WC40_SP_CNT_INC(_pc) \ 319 (DEV_CTRL_PTR(_pc)->lkwa.cnt)++ 320 #define WC40_SP_CNT_CLEAR(_pc) \ 321 (DEV_CTRL_PTR(_pc)->lkwa.cnt) = 0 322 #define WC40_SP_VALID_SET(_pc) \ 323 (DEV_CTRL_PTR(_pc)->lkwa.state) = TRUE 324 #define WC40_SP_VALID_RESET(_pc) \ 325 (DEV_CTRL_PTR(_pc)->lkwa.state) = FALSE 326 327 #define WC40_AN_TIME(_pc) \ 328 (DEV_CTRL_PTR(_pc)->an.start_time) 329 #define WC40_AN_VALID(_pc) \ 330 (DEV_CTRL_PTR(_pc)->an.state) 331 #define WC40_AN_RECORD_TIME(_pc) \ 332 (DEV_CTRL_PTR(_pc)->an.start_time) = sal_time_usecs() 333 #define WC40_AN_VALID_SET(_pc) \ 334 (DEV_CTRL_PTR(_pc)->an.state) = TRUE 335 #define WC40_AN_VALID_RESET(_pc) \ 336 (DEV_CTRL_PTR(_pc)->an.state) = FALSE 337 #define WC40_AN_CHECK_TIMEOUT(_pc) \ 338 ((uint32)SAL_USECS_SUB(sal_time_usecs(), WC40_AN_TIME((_pc))) \ 339 >= WC40_AN_WAIT_INTERVAL) 340 341 /* TX drive configuration */ 342 343 #define WC40_NO_CFG_VALUE (-1) 344 #define TXDRV_PREEMPH(_tdrv) (((_tdrv).force << 15) | ((_tdrv).post << 10) | \ 345 ((_tdrv).main << 4) | ((_tdrv).pre)) 346 347 /* CL49 PRBS control */ 348 349 #define WC40_PRBS_TYPE_STD 0 350 #define WC40_PRBS_TYPE_CL49 1 351 #define WC40_PRBS_CFG_POLY31 3 352 #define WC40_PRBS_CL49_POLY31 (PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_MASK | \ 353 PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_MASK) 354 #define WC40_PRBS_CL49_POLY9 (PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_MASK | \ 355 0x80) 356 357 /* CL72 in force mode */ 358 #define WC40_CL72_STATE_TX_DISABLED 0 359 #define WC40_CL72_STATE_INIT_CL72 1 360 #define WC40_CL72_STATE_LINK_CHECK 2 361 #define WC40_CL72_STATE_LINK_GOOD 3 362 #define WC40_CL72_LINK_WAIT_CNT_LIMIT 6 363 364 /* CL72 in force mode (firmware) */ 365 #define WC40_FORCED_CL72_STATE_RESET 1 366 #define WC40_FORCED_CL72_STATE_WAIT_4_LINK 2 367 #define WC40_FORCED_CL72_STATE_LINK_GOOD 3 368 #define WC40_FORCED_CL72_LINK_WAIT_CNT_LIMIT 6 369 /* typedefs */ 370 371 /* index to TX drive configuration table for each PMD type. 372 */ 373 typedef enum txdrv_inxs { 374 TXDRV_XFI_INX, /* 10G XFI */ 375 TXDRV_XLAUI_INX, /* 40G XLAUI mode */ 376 TXDRV_SFI_INX, /* 10G SR fiber mode */ 377 TXDRV_SFIDAC_INX, /* 10G SFI DAC mode */ 378 TXDRV_SR4_INX, /* 40G SR4 */ 379 TXDRV_6GOS1_INX, /* BRCM 40G mode */ 380 TXDRV_6GOS2_INX, /* */ 381 TXDRV_6GOS2_CX4_INX, /* */ 382 TXDRV_AN_INX, /* a common entry for autoneg mode */ 383 TXDRV_DFT_INX, /* temp for any missing speed modes */ 384 TXDRV_LAST_INX /* always last */ 385 } TXDRV_INXS_t; 386 387 #define TXDRV_ENTRY_NUM (TXDRV_LAST_INX) 388 389 typedef struct 390 { 391 unsigned int force: 1; /* forced */ 392 unsigned int post : 5; /* TX post tap */ 393 unsigned int main : 6; /* TX main tap */ 394 unsigned int pre : 4; /* TX pre tap */ 395 unsigned int rsvd : 16; /* reserved */ 396 } WC40_TX_TAP_t; 397 398 typedef enum sw_rx_los_states { 399 RESET, 400 INITIAL_LINK, 401 LINK, 402 START_TIMER, 403 RX_RESTART, 404 IDLE 405 } SOFTWARE_RX_LOS_STATES_t; 406 407 /* The structure is only for the use 408 * for RX LOS (Loss of Signal) workaround. 409 * The workaround is to handle the situations 410 * through s/w where no reliable LOS detect 411 * is available to WC 412 */ 413 typedef struct { 414 uint8 enable; 415 uint8 sys_link; 416 uint8 link_status; 417 uint8 fault_report_dis; 418 SOFTWARE_RX_LOS_STATES_t state; 419 } WC40_SOFTWARE_RX_LOS_t; 420 421 422 423 typedef struct { 424 union { 425 WC40_TX_TAP_t tap; 426 uint16 preemph; 427 } u; 428 uint8 post2; /* TX post2 coeff */ 429 uint8 idrive; /* TX idrive */ 430 uint8 ipredrive; /* TX pre-idrive */ 431 } WC40_TX_DRIVE_t; 432 433 typedef struct { 434 /* Enable the cl73 fsm auto 435 recovery feature */ 436 uint8 enable; 437 438 /* Store FSM previous state */ 439 uint16 fsm_state_prev; 440 441 /* Tracks how many times we've seen the 442 port in the particular state. */ 443 int fsm_state_count; 444 445 /* Statistics counter for how many times 446 the patch recovery action was taken 447 for each of the FSM states. */ 448 uint32 action_count_state02; 449 uint32 action_count_state04; 450 uint32 action_count_state08; 451 uint32 action_count_state10; 452 uint32 action_count_state20; 453 } WC40_CL73_AUTO_RECOVER_t; 454 455 /* WC40_CL73_AUTO_RECOVER feature addresses a link issue 456 found with WarpCore connected to a certain Broadcom PHY, 457 primarily BCM8073. Following autoneg FSM states are 458 known to be symptoms of the issue: 459 0x002: Transmit Disable 460 0x004: Ability Detect 461 0x008: Acknowledge 462 0x010: Acknowledge Complete 463 0x020: Next Page Wait 464 465 All states except 0x008 has some dependencies on the 466 Link Partner (LP); therefore, we allow more time for 467 a port to be in those states. These constants define 468 how many times we're allowed to see these FSM states 469 before taking recovery action. 470 */ 471 #define CL73_AUTO_RECOVER_STATE08_WAIT_COUNT 1 472 #define CL73_AUTO_RECOVER_LP_STATE_WAIT_COUNT 8 473 474 /* 475 In f/w ver 0103 war_tx_os8_fifo_reset routine is added. 476 The purpose of this routine is to ensure that the txfifo 477 (in OS8.25 mode) gets a reset when the clocks are stable, 478 and while the reset cannot cause a link flap in the LP. 479 480 This routine is the f/w WAR that performs a targeted reset 481 of the tx_os8_fifo whenever, the CL73 Arbitration FSM 482 enters either the TX_DISABLE or the AN_GOOD_CHECK states. 483 Only perform WAR routine when mode10g = 0x4 (i.e. Independent 484 0s8.25 channel mode), AND when CL73 AN is enabled. 485 486 'cl73an_tx_fifo_reset_enable' field is used manage/setup 487 the required condition for the f/w war. 488 489 Watch out for register access of these registers as these 490 are also used by the war when active. 491 0x8061, 0x8378, 0x8345 492 */ 493 typedef enum cl73an_tx_fifo_reset_status{ 494 DISABLE, 495 ENABLE, 496 ACTIVE, 497 REACTIVATE 498 } CL73AN_TX_FIFO_RESET_STATUS_t; 499 500 typedef struct { 501 int preemph[NUM_LANES]; /* pre-emphasis */ 502 int idriver[NUM_LANES]; 503 int pdriver[NUM_LANES]; 504 int post2driver[NUM_LANES]; 505 int auto_medium; 506 int fiber_pref; 507 int sgmii_mstr; 508 int pdetect10g; /* 10G paralell detect */ 509 int pdetect1000x; /* 1000X paralell detect */ 510 int cx42hg; 511 int rxlane_map; 512 int txlane_map; 513 int cl73an; 514 int cl37an; 515 int lane_mode; 516 int cx4_10g; 517 int lane0_rst; 518 int rxaui; 519 int dxgxs; 520 int custom; 521 uint32 line_intf; 522 int scrambler_en; 523 int custom1; 524 int txpol; 525 int rxpol; 526 int load_mthd; 527 int uc_cksum; 528 529 int medium; 530 int hg_mode; /* choose HG speed mode */ 531 int refclk; 532 int rx_los; 533 int rx_los_invert; 534 int phy_passthru; 535 WC40_TX_DRIVE_t tx_drive[TXDRV_ENTRY_NUM]; 536 WC40_SOFTWARE_RX_LOS_t sw_rx_los; 537 WC40_CL73_AUTO_RECOVER_t cl73_fsm_auto_recover; 538 int force_cl72_fw; /* Select firmware based forced cl72 implementation */ 539 int force_cl72; /* Enable/disable forced cl72 */ 540 int fw_dfe; 541 mac_driver_t *macd; /* Attached MAC driver */ 542 CL73AN_TX_FIFO_RESET_STATUS_t cl73an_tx_fifo_reset_status; 543 uint8 *scache_ptr ; 544 uint16 scache_ver ; 545 int scache_size ; 546 } WC40_DEV_CFG_t; 547 548 #define WC40_LANE_NAME_LEN 30 549 550 typedef struct { 551 uint16 serdes_id0; 552 char name[WC40_LANE_NAME_LEN]; 553 } WC40_DEV_INFO_t; 554 555 typedef struct { 556 uint32 start_time; 557 uint32 state; 558 uint32 cnt; 559 } WC40_LINK_WAR; 560 561 typedef struct { 562 uint32 start_time; 563 uint32 state; 564 } WC40_AN_MODE; 565 566 typedef struct { 567 int type; 568 int poly; 569 } WC40_PRBS_CTRL; 570 571 typedef struct { 572 uint16 state; 573 uint16 lp_adv; 574 uint16 ld_kr2; 575 uint16 timer_state; 576 uint32 start_time; 577 uint16 attempt; 578 } WC40_SOFT_KR2; 579 580 typedef struct { 581 uint16 state; 582 uint16 enabled; 583 uint16 tick_cnt; 584 } WC40_FORCE_CL72_t; 585 586 typedef struct { 587 WC40_LINK_WAR lkwa; 588 WC40_AN_MODE an; 589 WC40_PRBS_CTRL prbs; 590 int clk_comp; 591 WC40_SOFT_KR2 soft_kr2; 592 WC40_FORCE_CL72_t cl72; 593 } WC40_DEV_CTRL_t; 594 595 typedef struct { 596 WC40_DEV_CFG_t cfg; 597 WC40_DEV_INFO_t info; 598 WC40_DEV_CTRL_t ctrl; 599 } WC40_DEV_DESC_t; 600 601 #define DEV_CFG_PTR(_pc) (&(((WC40_DEV_DESC_t *)((_pc) + 1))->cfg)) 602 #define DEV_INFO_PTR(_pc) (&(((WC40_DEV_DESC_t *)((_pc) + 1))->info)) 603 #define DEV_CTRL_PTR(_pc) (&(((WC40_DEV_DESC_t *)((_pc) + 1))->ctrl)) 604 605 /* force cl72 */ 606 #define FORCE_CL72_IS_ENABLED(_pc) (DEV_CTRL_PTR(_pc)->cl72.enabled \ 607 && DEV_CFG_PTR(_pc)->force_cl72) 608 #define FORCE_CL72_ENABLE(_pc) (DEV_CTRL_PTR(_pc)->cl72.enabled) 609 #define FORCE_CL72_STATE(_pc) (DEV_CTRL_PTR(_pc)->cl72.state) 610 #define FORCE_CL72_TICK_CNT(_pc) (DEV_CTRL_PTR(_pc)->cl72.tick_cnt) 611 612 613 #define SOFT_KR2_TX_SQUELCH_WAR_INTERVAL (750000) 614 #define SOFT_KR2_TIME(_pc) \ 615 (DEV_CTRL_PTR(_pc)->soft_kr2.start_time) 616 #define SOFT_KR2_TIMER_VALID(_pc) \ 617 (DEV_CTRL_PTR(_pc)->soft_kr2.timer_state) 618 #define SOFT_KR2_TIMER_EN(_pc) \ 619 (DEV_CTRL_PTR(_pc)->soft_kr2.timer_state) = TRUE 620 #define SOFT_KR2_TIMER_DIS(_pc) \ 621 (DEV_CTRL_PTR(_pc)->soft_kr2.timer_state) = FALSE 622 #define SOFT_KR2_RECORD_TIME(_pc) \ 623 (DEV_CTRL_PTR(_pc)->soft_kr2.start_time) = sal_time_usecs() 624 #define SOFT_KR2_CHECK_TIMEOUT(_pc) \ 625 ((uint32)SAL_USECS_SUB(sal_time_usecs(), SOFT_KR2_TIME((_pc))) \ 626 >= SOFT_KR2_TX_SQUELCH_WAR_INTERVAL) 627 628 629 typedef struct { 630 uint8 *pdata; 631 int *plen; 632 uint16 chip_rev; 633 } WC40_UCODE_DESC; 634 635 /* external functions shared within WC driver files */ 636 extern int phy_wc40_config_init(phy_ctrl_t *pc); 637 638 /* (*_offset_p) and _size will accumulate by the sizeof(_var) */ 639 #define WC40_WB_ID_CMD(_ptr, _var, _t, _offset_p,_size_p) \ 640 do { \ 641 uint8 *_vptr_ ; \ 642 int _vsize_ ; \ 643 _vptr_ = (_ptr) + (*(_offset_p)) ; \ 644 _vsize_ = sizeof((_var)) ; \ 645 if((_t)==WC40_WB_SC_UPDATE){ \ 646 sal_memcpy(_vptr_,(&(_var)),_vsize_) ; \ 647 } else if((_t)==WC40_WB_SC_RETRIEVE) { \ 648 sal_memcpy((&(_var)),_vptr_,_vsize_); \ 649 } \ 650 (*(_size_p)) = (*(_size_p)) + _vsize_ ; \ 651 (*(_offset_p)) += _vsize_ ; \ 652 } while(0) 653 654 typedef enum wc40_wb_handler_type { 655 WC40_WB_SC_COUNT, 656 WC40_WB_SC_RETRIEVE, 657 WC40_WB_SC_UPDATE 658 } WC40_WB_HANDLER_TYPE_t ; 659 660 typedef enum wc40_wb_data_id { 661 WC40_WB_SC_VER=0, 662 WC40_WB_RXLOS, 663 WC40_WB_SC_LAST 664 } WC40_WB_DATA_ID_t ; 665 666 #endif /* WC40_EXTRA_H__ */