wc40_config.c (28293B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: wc40_config.c 8 * Purpose: Perform configuration for Warpcore device. 9 */ 10 11 #include <sal/types.h> 12 #include <sal/core/spl.h> 13 #include <shared/bsl.h> 14 #include <soc/drv.h> 15 #include <soc/debug.h> 16 #include <soc/error.h> 17 #include <soc/phyreg.h> 18 #include <soc/port_ability.h> 19 #include <soc/phyctrl.h> 20 21 #include <soc/phy.h> 22 #include <soc/phy/phyctrl.h> 23 #include <soc/phy/drv.h> 24 25 #include "phydefs.h" /* Must include before other phy related includes */ 26 27 #if defined(INCLUDE_XGXS_WC40) 28 #include "phyconfig.h" /* Must include before other phy related includes */ 29 #include "phyreg.h" 30 #include "phyfege.h" 31 #include "phynull.h" 32 #include "serdesid.h" 33 #include "wc40.h" 34 #include "wc40_extra.h" 35 36 /* 37 * Function: 38 * phy_wc40_config_init 39 * Purpose: 40 * Obtain switch chip and board specific configuration information for the Warpcore device to 41 * allow driver to put the device in the right operation mode. This function should be 42 * called first in the driver's initialization sequence. 43 * Parameters: 44 * pc - device descriptor. 45 * Returns: 46 * SOC_E_NONE 47 */ 48 49 int 50 phy_wc40_config_init(phy_ctrl_t *pc) 51 { 52 WC40_DEV_CFG_t *pCfg; 53 WC40_DEV_INFO_t *pInfo; 54 WC40_DEV_DESC_t *pDesc; 55 soc_phy_info_t *pi; 56 int len; 57 uint16 serdes_id0; 58 int unit; 59 int port; 60 int i; 61 WC40_TX_DRIVE_t *p_tx; 62 63 pDesc = (WC40_DEV_DESC_t *)(pc + 1); 64 pCfg = &pDesc->cfg; 65 pInfo = &pDesc->info; 66 unit = pc->unit; 67 port = pc->port; 68 69 70 if (SOC_IS_HELIX4(unit)) { 71 soc_info_t *si; 72 int phy_port; /* physical port number */ 73 74 si = &SOC_INFO(unit); 75 phy_port = si->port_l2p_mapping[port]; 76 pc->lane_num = SOC_PORT_BINDEX(unit, phy_port); 77 pc->chip_num = SOC_BLOCK_NUMBER(unit, SOC_PORT_BLOCK(unit, phy_port)); 78 79 /* convert to phy_ctrl macros */ 80 if (si->port_num_lanes[port] == 4) { 81 pc->phy_mode = PHYCTRL_QUAD_LANE_PORT; 82 } else if (si->port_num_lanes[port] == 2) { 83 pc->phy_mode = PHYCTRL_DUAL_LANE_PORT; 84 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 85 } else if (si->port_num_lanes[port] == 1) { 86 pc->phy_mode = PHYCTRL_ONE_LANE_PORT; 87 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 88 } 89 90 pc->lane_num = (phy_port-1) % 4; 91 pc->chip_num = (phy_port-1) / 4; 92 } 93 94 95 #if defined(BCM_TRIDENT_SUPPORT) 96 if (SOC_IS_TD_TT(unit)) { 97 soc_info_t *si; 98 int phy_port; /* physical port number */ 99 100 si = &SOC_INFO(unit); 101 phy_port = si->port_l2p_mapping[port]; 102 pc->lane_num = SOC_PORT_BINDEX(unit, phy_port); 103 pc->chip_num = SOC_BLOCK_NUMBER(unit, SOC_PORT_BLOCK(unit, phy_port)); 104 105 /* convert to phy_ctrl macros */ 106 if (si->port_num_lanes[port] == 4) { 107 pc->phy_mode = PHYCTRL_QUAD_LANE_PORT; 108 } else if (si->port_num_lanes[port] == 2) { 109 pc->phy_mode = PHYCTRL_DUAL_LANE_PORT; 110 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 111 } else if (si->port_num_lanes[port] == 1) { 112 pc->phy_mode = PHYCTRL_ONE_LANE_PORT; 113 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 114 } 115 /* warpcore intstance number and lane number */ 116 pc->lane_num = (phy_port - 1) % 4; 117 pc->chip_num = (phy_port - 1) / 4; 118 } 119 #endif 120 #ifdef BCM_SHADOW_SUPPORT 121 if (SOC_IS_SHADOW(unit)) { 122 soc_info_t *si; 123 int phy_port; /* physical port number */ 124 125 si = &SOC_INFO(unit); 126 if (soc_feature(unit, soc_feature_logical_port_num)) { 127 phy_port = si->port_l2p_mapping[port]; 128 } else { 129 phy_port = port; 130 } 131 pc->lane_num = SOC_PORT_BINDEX(unit, phy_port); 132 pc->chip_num = SOC_BLOCK_NUMBER(unit, SOC_PORT_BLOCK(unit, phy_port)); 133 134 /* convert to phy_ctrl macros */ 135 if (si->port_num_lanes[port] == 4) { 136 pc->phy_mode = PHYCTRL_QUAD_LANE_PORT; 137 } else if (si->port_num_lanes[port] == 2) { 138 pc->phy_mode = PHYCTRL_DUAL_LANE_PORT; 139 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 140 } else if (si->port_num_lanes[port] == 1) { 141 pc->phy_mode = PHYCTRL_ONE_LANE_PORT; 142 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 143 } 144 145 if (phy_port > 8) { 146 if ((soc_property_get(unit, spn_BCM88732_2X40_1X40, 0)) || 147 (soc_property_get(unit, spn_BCM88732_2X40_2X40, 0)) || 148 (soc_property_get(unit, spn_BCM88732_8X10_1X40, 0)) || 149 (soc_property_get(unit, spn_BCM88732_8X10_2X40, 0))) { 150 pc->phy_mode = PHYCTRL_LANE_MODE_CUSTOM; 151 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 152 } else if (soc_property_get(unit, 153 spn_BCM88732_2X40_2X40,0)) { 154 pc->phy_mode = PHYCTRL_LANE_MODE_CUSTOM; 155 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 156 } else if ((soc_property_get(unit,spn_BCM88732_1X40_4X10,0)) || 157 (soc_property_get(unit, spn_BCM88732_4X10_4X10, 0))) { 158 pc->phy_mode = PHYCTRL_QUAD_LANE_PORT; 159 } else if ((soc_property_get(unit,spn_BCM88732_2X40_8X12,0)) || 160 (soc_property_get(unit, spn_BCM88732_1X40_4X10_8X12, 0)) || 161 (soc_property_get(unit, spn_BCM88732_4X10_1X40_8X12, 0)) || 162 (soc_property_get(unit, spn_BCM88732_8X10_8X12, 0)) || 163 (soc_property_get(unit, spn_BCM88732_8X10_4X12, 0)) || 164 (soc_property_get(unit, spn_BCM88732_6X10_2X12, 0)) || 165 (soc_property_get(unit, spn_BCM88732_8X10_2X12, 0))) { 166 pc->phy_mode = PHYCTRL_LANE_MODE_CUSTOM1; 167 } else if (soc_property_get(unit, spn_BCM88732_2X40_8X10, 0) || 168 soc_property_get(unit, spn_BCM88732_8X10_8X10, 0)) { 169 pc->phy_mode = PHYCTRL_ONE_LANE_PORT; 170 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 171 } else { 172 LOG_WARN(BSL_LS_SOC_PHY, 173 (BSL_META_U(unit, 174 "Board configuration not found: u=%d p=%d\n"), unit,port)); 175 } 176 } else { 177 /* convert to phy_ctrl macros */ 178 if (si->port_num_lanes[port] == 4) { 179 pc->phy_mode = PHYCTRL_QUAD_LANE_PORT; 180 } else if (si->port_num_lanes[port] == 2) { 181 pc->phy_mode = PHYCTRL_DUAL_LANE_PORT; 182 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 183 } else if (si->port_num_lanes[port] == 1) { 184 pc->phy_mode = PHYCTRL_ONE_LANE_PORT; 185 pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 186 } 187 } 188 189 if (phy_port > 8) { 190 if (soc_property_get(unit, "IL3125", 0)) { 191 pc->phy_mode |= PHYCTRL_LANE_MODE_CUSTOM_3p125MHZ; 192 } 193 } 194 } 195 #endif 196 197 /* retrieve chip level information for warpcore */ 198 199 pi = &SOC_PHY_INFO(unit, port); 200 201 serdes_id0 = pInfo->serdes_id0; 202 /* 203 * COVERITY 204 * 205 * Buffer overflow will not happen as destination string is of length 30. 206 */ 207 /* coverity[secure_coding] */ 208 209 sal_strcpy(pInfo->name,"WC-"); 210 len = sal_strlen(pInfo->name); 211 /* add rev letter */ 212 pInfo->name[len++] = 'A' + ((serdes_id0 >> 213 SERDESID_SERDESID0_REV_LETTER_SHIFT) & 0x3); 214 215 /* add rev number */ 216 pInfo->name[len++] = '0' + ((serdes_id0 >> 217 SERDESID_SERDESID0_REV_NUMBER_SHIFT) & 0x7); 218 pInfo->name[len++] = '/'; 219 pInfo->name[len++] = (pc->chip_num/10)%10 + '0'; 220 pInfo->name[len++] = pc->chip_num%10 + '0'; 221 pInfo->name[len++] = '/'; 222 223 /* phy_mode: 0 single port mode, port uses all four lanes of Warpcore 224 * 1 dual port mode, port uses 2 lanes 225 * 2 quad port mode, port uses 1 lane 226 */ 227 if (IS_DUAL_LANE_PORT(pc)) { /* dual-xgxs mode */ 228 if (pc->lane_num < 2) { /* the first dual-xgxs port */ 229 pInfo->name[len++] = '0'; 230 pInfo->name[len++] = '-'; 231 pInfo->name[len++] = '1'; 232 } else { 233 pInfo->name[len++] = '2'; 234 pInfo->name[len++] = '-'; 235 pInfo->name[len++] = '3'; 236 } 237 PHY_FLAGS_SET(unit, port, PHY_FLAGS_INDEPENDENT_LANE); 238 } else if (pc->phy_mode == PHYCTRL_ONE_LANE_PORT || CUSTOM_MODE(pc) || 239 pc->phy_mode == PHYCTRL_SINGLE_LANE_IN_DUAL_PORT_MODE) { 240 PHY_FLAGS_SET(unit, port, PHY_FLAGS_INDEPENDENT_LANE); 241 pInfo->name[len++] = pc->lane_num + '0'; 242 } else { 243 pInfo->name[len++] = '4'; 244 PHY_FLAGS_CLR(unit, port, PHY_FLAGS_INDEPENDENT_LANE); 245 } 246 pInfo->name[len] = 0; /* string terminator */ 247 248 if (len > WC40_LANE_NAME_LEN) { 249 LOG_ERROR(BSL_LS_SOC_PHY, 250 (BSL_META_U(unit, 251 "WC info string length %d exceeds max length 0x%x: u=%d p=%d\n"), 252 len,WC40_LANE_NAME_LEN,unit, port)); 253 return SOC_E_MEMORY; 254 } 255 256 if (!PHY_EXTERNAL_MODE(unit, port)) { 257 pi->phy_name = pInfo->name; 258 } 259 260 if (CUSTOM_MODE(pc)) { 261 pCfg->custom = pc->phy_mode; 262 } 263 if (CUSTOM1_MODE(pc)) { 264 pCfg->custom1 = pc->phy_mode; 265 } 266 267 if (PHY_INDEPENDENT_LANE_MODE(unit, port)) { 268 if (PHY_EXTERNAL_MODE(unit, port)) { 269 pCfg->line_intf = WC40_IF_XFI; 270 } else { 271 pCfg->line_intf = WC40_IF_SFI; 272 } 273 pCfg->auto_medium = FALSE; 274 if (CUSTOM_MODE(pc) || CUSTOM1_MODE(pc)) { 275 pCfg->lane_mode = xgxs_operationModes_IndLane_OS5; 276 } else { 277 pCfg->lane_mode = xgxs_operationModes_Indlane_OS8; 278 } 279 } else { 280 pCfg->line_intf = WC40_IF_XLAUI; 281 pCfg->auto_medium = TRUE; 282 pCfg->lane_mode = xgxs_operationModes_ComboCoreMode; 283 pc->lane_num = 0; /* make sure lane_num is 0 */ 284 } 285 286 if ((PHY_FIBER_MODE(unit, port) && !PHY_EXTERNAL_MODE(unit, port)) || 287 (PHY_PASSTHRU_MODE(unit, port)) || 288 (!PHY_INDEPENDENT_LANE_MODE(unit, port)) || 289 (pc->speed_max >= 10000)) { 290 pCfg->fiber_pref = TRUE; 291 } else { 292 pCfg->fiber_pref = FALSE; 293 } 294 pCfg->fw_dfe = SOC_PHY_DFE_AUTO; 295 296 if (PHY_INDEPENDENT_LANE_MODE(unit, port)) { 297 pCfg->cl73an = WC40_CL73_AND_CL73BAM; /*WC40_CL73_WO_CL73BAM; */ 298 } else { 299 if (IS_HG_PORT(unit, port)) { 300 pCfg->cl73an = FALSE; 301 } else { 302 pCfg->cl73an = WC40_CL73_AND_CL73BAM; 303 } 304 } 305 306 /* Default setting for CL37 */ 307 pCfg->cl37an = WC40_CL37_AND_CL37BAM; 308 309 if ((PHY_FIBER_MODE(unit, port) && !PHY_EXTERNAL_MODE(unit, port)) || 310 PHY_PASSTHRU_MODE(unit, port) || 311 PHY_SGMII_AUTONEG_MODE(unit, port)) { 312 pCfg->pdetect1000x = TRUE; 313 } else { 314 pCfg->pdetect1000x = FALSE; 315 } 316 317 /* populate the default TX drive value for each speed mode */ 318 #if defined(BCM_TRIDENT_SUPPORT) 319 if (SOC_IS_TD_TT(unit)) { 320 321 /* XFI */ 322 p_tx = &pCfg->tx_drive[TXDRV_XFI_INX]; 323 p_tx->u.tap.post = 0x08; 324 p_tx->u.tap.main = 0x37; 325 p_tx->u.tap.pre = 0x00; 326 p_tx->u.tap.force = 0x01; 327 p_tx->post2 = 0x00; 328 p_tx->idrive = 0x02; 329 p_tx->ipredrive = 0x03; 330 331 /* SFI SR */ 332 p_tx = &pCfg->tx_drive[TXDRV_SFI_INX]; 333 p_tx->u.tap.post = 0x12; 334 p_tx->u.tap.main = 0x2d; 335 p_tx->u.tap.pre = 0x00; 336 p_tx->u.tap.force = 0x01; 337 p_tx->post2 = 0x02; 338 p_tx->idrive = 0x02; 339 p_tx->ipredrive = 0x02; 340 341 /* SFI DAC */ 342 p_tx = &pCfg->tx_drive[TXDRV_SFIDAC_INX]; 343 p_tx->u.tap.post = 0x12; 344 p_tx->u.tap.main = 0x2d; 345 p_tx->u.tap.pre = 0x00; 346 p_tx->u.tap.force = 0x01; 347 p_tx->post2 = 0x02; 348 p_tx->idrive = 0x02; 349 p_tx->ipredrive = 0x02; 350 351 /* SR4 */ 352 p_tx = &pCfg->tx_drive[TXDRV_SR4_INX]; 353 p_tx->u.tap.post = 0x13; 354 p_tx->u.tap.main = 0x2c; 355 p_tx->u.tap.pre = 0x00; 356 p_tx->u.tap.force = 0x01; 357 p_tx->post2 = 0x02; 358 p_tx->idrive = 0x05; 359 p_tx->ipredrive = 0x05; 360 361 /* XLAUI */ 362 p_tx = &pCfg->tx_drive[TXDRV_XLAUI_INX]; 363 p_tx->u.tap.post = 0x18; 364 p_tx->u.tap.main = 0x27; 365 p_tx->u.tap.pre = 0x00; 366 p_tx->u.tap.force = 0x01; 367 p_tx->post2 = 0x02; 368 p_tx->idrive = 0x04; 369 p_tx->ipredrive = 0x04; 370 371 /* TXDRV_6GOS1_INX */ 372 p_tx = &pCfg->tx_drive[TXDRV_6GOS1_INX]; 373 p_tx->u.tap.post = 0x00; 374 p_tx->u.tap.main = 0x00; 375 p_tx->u.tap.pre = 0x00; 376 p_tx->u.tap.force = 0x01; 377 p_tx->post2 = 0x00; 378 p_tx->idrive = 0x09; 379 p_tx->ipredrive = 0x09; 380 381 /* TXDRV_6GOS2_INX */ 382 p_tx = &pCfg->tx_drive[TXDRV_6GOS2_INX]; 383 p_tx->u.tap.post = 0x00; 384 p_tx->u.tap.main = 0x3f; 385 p_tx->u.tap.pre = 0x00; 386 p_tx->u.tap.force = 0x01; 387 p_tx->post2 = 0x00; 388 p_tx->idrive = 0x09; 389 p_tx->ipredrive = 0x09; 390 391 /* TXDRV_6GOS2_CX4_INX */ 392 p_tx = &pCfg->tx_drive[TXDRV_6GOS2_CX4_INX]; 393 p_tx->u.tap.post = 0x0e; 394 p_tx->u.tap.main = 0x31; 395 p_tx->u.tap.pre = 0x00; 396 p_tx->u.tap.force = 0x01; 397 p_tx->post2 = 0x00; 398 p_tx->idrive = 0x08; 399 p_tx->ipredrive = 0x08; 400 401 /* Autoneg */ 402 p_tx = &pCfg->tx_drive[TXDRV_AN_INX]; 403 p_tx->u.tap.post = 0x00; 404 p_tx->u.tap.main = 0x00; 405 p_tx->u.tap.pre = 0x00; 406 p_tx->u.tap.force = 0x00; 407 p_tx->post2 = 0x02; 408 p_tx->idrive = 0x06; 409 p_tx->ipredrive = 0x09; 410 411 /* default */ 412 p_tx = &pCfg->tx_drive[TXDRV_DFT_INX]; 413 p_tx->u.tap.post = 0x00; 414 p_tx->u.tap.main = 0x00; 415 p_tx->u.tap.pre = 0x00; 416 p_tx->u.tap.force = 0x00; 417 p_tx->post2 = 0x00; 418 p_tx->idrive = 0x09; 419 p_tx->ipredrive = 0x09; 420 } 421 #endif 422 /* populate the default TX drive value for each speed mode */ 423 #if defined(BCM_TRIUMPH3_SUPPORT) 424 if (SOC_IS_HELIX4(unit)) { 425 426 /* XFI */ 427 p_tx = &pCfg->tx_drive[TXDRV_XFI_INX]; 428 p_tx->u.tap.post = 0x08; 429 p_tx->u.tap.main = 0x37; 430 p_tx->u.tap.pre = 0x00; 431 p_tx->u.tap.force = 0x01; 432 p_tx->post2 = 0x00; 433 p_tx->idrive = 0x02; 434 p_tx->ipredrive = 0x03; 435 436 /* SFI SR */ 437 p_tx = &pCfg->tx_drive[TXDRV_SFI_INX]; 438 p_tx->u.tap.post = 0x12; 439 p_tx->u.tap.main = 0x2d; 440 p_tx->u.tap.pre = 0x00; 441 p_tx->u.tap.force = 0x01; 442 p_tx->post2 = 0x02; 443 p_tx->idrive = 0x02; 444 p_tx->ipredrive = 0x02; 445 446 /* SFI DAC */ 447 p_tx = &pCfg->tx_drive[TXDRV_SFIDAC_INX]; 448 p_tx->u.tap.post = 0x12; 449 p_tx->u.tap.main = 0x2d; 450 p_tx->u.tap.pre = 0x00; 451 p_tx->u.tap.force = 0x01; 452 p_tx->post2 = 0x02; 453 p_tx->idrive = 0x02; 454 p_tx->ipredrive = 0x02; 455 456 /* SR4 */ 457 p_tx = &pCfg->tx_drive[TXDRV_SR4_INX]; 458 p_tx->u.tap.post = 0x13; 459 p_tx->u.tap.main = 0x2c; 460 p_tx->u.tap.pre = 0x00; 461 p_tx->u.tap.force = 0x01; 462 p_tx->post2 = 0x02; 463 p_tx->idrive = 0x05; 464 p_tx->ipredrive = 0x05; 465 466 /* XLAUI */ 467 p_tx = &pCfg->tx_drive[TXDRV_XLAUI_INX]; 468 p_tx->u.tap.post = 0x18; 469 p_tx->u.tap.main = 0x27; 470 p_tx->u.tap.pre = 0x00; 471 p_tx->u.tap.force = 0x01; 472 p_tx->post2 = 0x02; 473 p_tx->idrive = 0x04; 474 p_tx->ipredrive = 0x04; 475 476 /* TXDRV_6GOS1_INX */ 477 p_tx = &pCfg->tx_drive[TXDRV_6GOS1_INX]; 478 p_tx->u.tap.post = 0x00; 479 p_tx->u.tap.main = 0x00; 480 p_tx->u.tap.pre = 0x00; 481 p_tx->u.tap.force = 0x01; 482 p_tx->post2 = 0x00; 483 p_tx->idrive = 0x09; 484 p_tx->ipredrive = 0x09; 485 486 /* TXDRV_6GOS2_INX */ 487 p_tx = &pCfg->tx_drive[TXDRV_6GOS2_INX]; 488 p_tx->u.tap.post = 0x00; 489 p_tx->u.tap.main = 0x3f; 490 p_tx->u.tap.pre = 0x00; 491 p_tx->u.tap.force = 0x01; 492 p_tx->post2 = 0x00; 493 p_tx->idrive = 0x09; 494 p_tx->ipredrive = 0x09; 495 496 /* TXDRV_6GOS2_CX4_INX */ 497 p_tx = &pCfg->tx_drive[TXDRV_6GOS2_CX4_INX]; 498 p_tx->u.tap.post = 0x0e; 499 p_tx->u.tap.main = 0x31; 500 p_tx->u.tap.pre = 0x00; 501 p_tx->u.tap.force = 0x01; 502 p_tx->post2 = 0x00; 503 p_tx->idrive = 0x08; 504 p_tx->ipredrive = 0x08; 505 506 /* Autoneg */ 507 p_tx = &pCfg->tx_drive[TXDRV_AN_INX]; 508 p_tx->u.tap.post = 0x00; 509 p_tx->u.tap.main = 0x00; 510 p_tx->u.tap.pre = 0x00; 511 p_tx->u.tap.force = 0x00; 512 p_tx->post2 = 0x02; 513 p_tx->idrive = 0x06; 514 p_tx->ipredrive = 0x09; 515 516 /* default */ 517 p_tx = &pCfg->tx_drive[TXDRV_DFT_INX]; 518 p_tx->u.tap.post = 0x00; 519 p_tx->u.tap.main = 0x00; 520 p_tx->u.tap.pre = 0x00; 521 p_tx->u.tap.force = 0x00; 522 p_tx->post2 = 0x00; 523 p_tx->idrive = 0x09; 524 p_tx->ipredrive = 0x09; 525 } 526 #endif 527 #if defined(BCM_KATANA2_SUPPORT) 528 if (SOC_IS_KATANA2(unit)) { 529 530 /* XFI */ 531 p_tx = &pCfg->tx_drive[TXDRV_XFI_INX]; 532 p_tx->u.tap.post = 0x08; 533 p_tx->u.tap.main = 0x37; 534 p_tx->u.tap.pre = 0x00; 535 p_tx->u.tap.force = 0x01; 536 p_tx->post2 = 0x00; 537 p_tx->idrive = 0x02; 538 p_tx->ipredrive = 0x03; 539 540 /* SFI SR */ 541 p_tx = &pCfg->tx_drive[TXDRV_SFI_INX]; 542 p_tx->u.tap.post = 0x12; 543 p_tx->u.tap.main = 0x2d; 544 p_tx->u.tap.pre = 0x00; 545 p_tx->u.tap.force = 0x01; 546 p_tx->post2 = 0x02; 547 p_tx->idrive = 0x02; 548 p_tx->ipredrive = 0x02; 549 550 /* SFI DAC */ 551 p_tx = &pCfg->tx_drive[TXDRV_SFIDAC_INX]; 552 p_tx->u.tap.post = 0x12; 553 p_tx->u.tap.main = 0x2d; 554 p_tx->u.tap.pre = 0x00; 555 p_tx->u.tap.force = 0x01; 556 p_tx->post2 = 0x02; 557 p_tx->idrive = 0x02; 558 p_tx->ipredrive = 0x02; 559 560 /* SR4 */ 561 p_tx = &pCfg->tx_drive[TXDRV_SR4_INX]; 562 p_tx->u.tap.post = 0x13; 563 p_tx->u.tap.main = 0x2c; 564 p_tx->u.tap.pre = 0x00; 565 p_tx->u.tap.force = 0x01; 566 p_tx->post2 = 0x02; 567 p_tx->idrive = 0x05; 568 p_tx->ipredrive = 0x05; 569 570 /* XLAUI */ 571 p_tx = &pCfg->tx_drive[TXDRV_XLAUI_INX]; 572 p_tx->u.tap.post = 0x18; 573 p_tx->u.tap.main = 0x27; 574 p_tx->u.tap.pre = 0x00; 575 p_tx->u.tap.force = 0x01; 576 p_tx->post2 = 0x02; 577 p_tx->idrive = 0x04; 578 p_tx->ipredrive = 0x04; 579 580 /* TXDRV_6GOS1_INX */ 581 p_tx = &pCfg->tx_drive[TXDRV_6GOS1_INX]; 582 p_tx->u.tap.post = 0x00; 583 p_tx->u.tap.main = 0x00; 584 p_tx->u.tap.pre = 0x00; 585 p_tx->u.tap.force = 0x01; 586 p_tx->post2 = 0x00; 587 p_tx->idrive = 0x09; 588 p_tx->ipredrive = 0x09; 589 590 /* TXDRV_6GOS2_INX */ 591 p_tx = &pCfg->tx_drive[TXDRV_6GOS2_INX]; 592 p_tx->u.tap.post = 0x00; 593 p_tx->u.tap.main = 0x3f; 594 p_tx->u.tap.pre = 0x00; 595 p_tx->u.tap.force = 0x01; 596 p_tx->post2 = 0x00; 597 p_tx->idrive = 0x09; 598 p_tx->ipredrive = 0x09; 599 600 /* TXDRV_6GOS2_CX4_INX */ 601 p_tx = &pCfg->tx_drive[TXDRV_6GOS2_CX4_INX]; 602 p_tx->u.tap.post = 0x0e; 603 p_tx->u.tap.main = 0x31; 604 p_tx->u.tap.pre = 0x00; 605 p_tx->u.tap.force = 0x01; 606 p_tx->post2 = 0x00; 607 p_tx->idrive = 0x08; 608 p_tx->ipredrive = 0x08; 609 610 /* Autoneg */ 611 p_tx = &pCfg->tx_drive[TXDRV_AN_INX]; 612 p_tx->u.tap.post = 0x00; 613 p_tx->u.tap.main = 0x00; 614 p_tx->u.tap.pre = 0x00; 615 p_tx->u.tap.force = 0x00; 616 p_tx->post2 = 0x02; 617 p_tx->idrive = 0x06; 618 p_tx->ipredrive = 0x09; 619 620 /* default */ 621 p_tx = &pCfg->tx_drive[TXDRV_DFT_INX]; 622 p_tx->u.tap.post = 0x00; 623 p_tx->u.tap.main = 0x00; 624 p_tx->u.tap.pre = 0x00; 625 p_tx->u.tap.force = 0x00; 626 p_tx->post2 = 0x00; 627 p_tx->idrive = 0x09; 628 p_tx->ipredrive = 0x09; 629 } 630 #endif 631 632 #ifdef BCM_SHADOW_SUPPORT 633 if (SOC_IS_SHADOW(unit)) { 634 635 /* XFI */ 636 p_tx = &pCfg->tx_drive[TXDRV_XFI_INX]; 637 p_tx->u.tap.post = 0x06; 638 p_tx->u.tap.main = 0x39; 639 p_tx->u.tap.pre = 0x00; 640 p_tx->u.tap.force = 0x01; 641 p_tx->post2 = 0x00; 642 p_tx->idrive = 0x01; 643 p_tx->ipredrive = 0x03; 644 645 /* SFI SR */ 646 p_tx = &pCfg->tx_drive[TXDRV_SFI_INX]; 647 p_tx->u.tap.post = 0x12; 648 p_tx->u.tap.main = 0x2d; 649 p_tx->u.tap.pre = 0x00; 650 p_tx->u.tap.force = 0x01; 651 p_tx->post2 = 0x02; 652 p_tx->idrive = 0x02; 653 p_tx->ipredrive = 0x02; 654 655 /* SFI DAC */ 656 p_tx = &pCfg->tx_drive[TXDRV_SFIDAC_INX]; 657 p_tx->u.tap.post = 0x12; 658 p_tx->u.tap.main = 0x2d; 659 p_tx->u.tap.pre = 0x00; 660 p_tx->u.tap.force = 0x01; 661 p_tx->post2 = 0x02; 662 p_tx->idrive = 0x02; 663 p_tx->ipredrive = 0x02; 664 665 /* SR4 */ 666 p_tx = &pCfg->tx_drive[TXDRV_SR4_INX]; 667 p_tx->u.tap.post = 0x00; 668 p_tx->u.tap.main = 0x00; 669 p_tx->u.tap.pre = 0x00; 670 p_tx->u.tap.force = 0x01; 671 p_tx->post2 = 0x02; 672 p_tx->idrive = 0x06; 673 p_tx->ipredrive = 0x09; 674 675 /* XLAUI */ 676 p_tx = &pCfg->tx_drive[TXDRV_XLAUI_INX]; 677 p_tx->u.tap.post = 0x18; 678 p_tx->u.tap.main = 0x27; 679 p_tx->u.tap.pre = 0x00; 680 p_tx->u.tap.force = 0x01; 681 p_tx->post2 = 0x00; 682 p_tx->idrive = 0x01; 683 p_tx->ipredrive = 0x03; 684 685 /* TXDRV_6GOS1_INX */ 686 p_tx = &pCfg->tx_drive[TXDRV_6GOS1_INX]; 687 p_tx->u.tap.post = 0x08; 688 p_tx->u.tap.main = 0x37; 689 p_tx->u.tap.pre = 0x00; 690 p_tx->u.tap.force = 0x01; 691 p_tx->post2 = 0x00; 692 p_tx->idrive = 0x00; 693 p_tx->ipredrive = 0x01; 694 695 /* TXDRV_6GOS2_INX */ 696 p_tx = &pCfg->tx_drive[TXDRV_6GOS2_INX]; 697 p_tx->u.tap.post = 0x00; 698 p_tx->u.tap.main = 0x3f; 699 p_tx->u.tap.pre = 0x00; 700 p_tx->u.tap.force = 0x01; 701 p_tx->post2 = 0x00; 702 p_tx->idrive = 0x09; 703 p_tx->ipredrive = 0x09; 704 705 /* TXDRV_6GOS2_CX4_INX */ 706 p_tx = &pCfg->tx_drive[TXDRV_6GOS2_CX4_INX]; 707 p_tx->u.tap.post = 0x00; 708 p_tx->u.tap.main = 0x00; 709 p_tx->u.tap.pre = 0x00; 710 p_tx->u.tap.force = 0x01; 711 p_tx->post2 = 0x02; 712 p_tx->idrive = 0x06; 713 p_tx->ipredrive = 0x09; 714 715 /* Autoneg */ 716 p_tx = &pCfg->tx_drive[TXDRV_AN_INX]; 717 p_tx->u.tap.post = 0x00; 718 p_tx->u.tap.main = 0x00; 719 p_tx->u.tap.pre = 0x00; 720 p_tx->u.tap.force = 0x00; 721 p_tx->post2 = 0x02; 722 p_tx->idrive = 0x06; 723 p_tx->ipredrive = 0x09; 724 725 /* default */ 726 p_tx = &pCfg->tx_drive[TXDRV_DFT_INX]; 727 p_tx->u.tap.post = 0x00; 728 p_tx->u.tap.main = 0x00; 729 p_tx->u.tap.pre = 0x00; 730 p_tx->u.tap.force = 0x00; 731 p_tx->post2 = 0x00; 732 p_tx->idrive = 0x09; 733 p_tx->ipredrive = 0x09; 734 } 735 #endif 736 737 /* config property overrides */ 738 for (i = 0; i < NUM_LANES; i++) { 739 pCfg->preemph[i] = soc_property_port_get(unit, port, 740 spn_SERDES_PREEMPHASIS, pCfg->preemph[i]); 741 pCfg->idriver[i] = soc_property_port_get(unit, port, 742 spn_SERDES_DRIVER_CURRENT, pCfg->idriver[i]); 743 pCfg->pdriver[i] = soc_property_port_get(unit, port, 744 spn_SERDES_PRE_DRIVER_CURRENT, pCfg->pdriver[i]); 745 pCfg->post2driver[i] = soc_property_port_get(unit, port, 746 spn_SERDES_POST2_DRIVER_CURRENT,pCfg->post2driver[i]); 747 } 748 pCfg->auto_medium = soc_property_port_get(unit, port, 749 spn_SERDES_AUTOMEDIUM, pCfg->auto_medium); 750 pCfg->fiber_pref = soc_property_port_get(unit, port, 751 spn_SERDES_FIBER_PREF, pCfg->fiber_pref); 752 pCfg->sgmii_mstr = soc_property_port_get(unit, port, 753 spn_SERDES_SGMII_MASTER, pCfg->sgmii_mstr); 754 pCfg->pdetect10g = soc_property_port_get(unit, port, 755 spn_XGXS_PDETECT_10G, pCfg->pdetect10g); 756 pCfg->cx42hg = soc_property_port_get(unit, port, 757 spn_CX4_TO_HIGIG, pCfg->cx42hg); 758 pCfg->rxlane_map = soc_property_port_get(unit, port, 759 spn_XGXS_RX_LANE_MAP, pCfg->rxlane_map); 760 pCfg->txlane_map = soc_property_port_get(unit, port, 761 spn_XGXS_TX_LANE_MAP, pCfg->txlane_map); 762 pCfg->cl73an = soc_property_port_get(unit, port, 763 spn_PHY_AN_C73, pCfg->cl73an); 764 pCfg->cl37an = soc_property_port_get(unit, port, 765 spn_PHY_AN_C37, pCfg->cl37an); 766 pCfg->rxaui = soc_property_port_get(unit, port, 767 spn_SERDES_2WIRE_XAUI, FALSE); 768 pCfg->txpol = soc_property_port_get(unit, port, 769 spn_PHY_XAUI_TX_POLARITY_FLIP, pCfg->txpol); 770 pCfg->rxpol = soc_property_port_get(unit, port, 771 spn_PHY_XAUI_RX_POLARITY_FLIP, pCfg->rxpol); 772 pCfg->rx_los = soc_property_port_get(unit, port, 773 spn_SERDES_RX_LOS, pCfg->rx_los); 774 pCfg->rx_los_invert = soc_property_port_get(unit, port, 775 spn_SERDES_RX_LOS_INVERT, pCfg->rx_los_invert); 776 if (PHY_EXTERNAL_MODE(unit, port)) { 777 PHY_FLAGS_CLR(unit, port, PHY_FLAGS_PASSTHRU); 778 pCfg->phy_passthru = soc_property_port_get(unit, port, 779 spn_PHY_PCS_REPEATER, pCfg->phy_passthru); 780 if (pCfg->phy_passthru) { 781 PHY_FLAGS_SET(unit, port, PHY_FLAGS_PASSTHRU); 782 } 783 } 784 if (PHY_INDEPENDENT_LANE_MODE(unit, port)) { 785 pCfg->lane_mode = soc_property_port_get(unit, port, 786 spn_PHY_HL65_1LANE_MODE, pCfg->lane_mode); 787 } 788 pCfg->cx4_10g = soc_property_port_get(unit, port, 789 spn_10G_IS_CX4, pCfg->cx4_10g); 790 pCfg->lane0_rst = soc_property_get(unit, 791 spn_SERDES_LANE0_RESET, pCfg->lane0_rst); 792 /* XXX internal use for now */ 793 pCfg->refclk = soc_property_port_get(unit,port, 794 "wc_refclk_speed", pCfg->refclk); 795 796 pCfg->hg_mode = IS_HG_PORT(unit,port); 797 if (PHY_EXTERNAL_MODE(unit, port)) { 798 /* default: always IEEE speed mode if connected with an external PHY */ 799 pCfg->hg_mode = FALSE; 800 801 /* exception: combo mode && passthru */ 802 if ((!PHY_INDEPENDENT_LANE_MODE(unit, port)) && pCfg->phy_passthru) { 803 pCfg->hg_mode = IS_HG_PORT(unit,port); 804 } 805 } 806 807 if (!PHY_EXTERNAL_MODE(unit, port)) { 808 809 if (pCfg->fiber_pref) { 810 PHY_FLAGS_SET(unit, port, PHY_FLAGS_FIBER); 811 } else { 812 PHY_FLAGS_CLR(unit, port, PHY_FLAGS_FIBER); 813 } 814 815 if (pCfg->cl73an) { 816 PHY_FLAGS_SET(unit, port, PHY_FLAGS_C73); 817 } 818 } 819 820 /* For HG mode or BAM mode, cl37 BAM should be enabled 821 WARN if not 822 */ 823 if((pCfg->cl37an != WC40_CL37_AND_CL37BAM) && 824 ((pCfg->hg_mode) || (pCfg->cl73an == WC40_CL73_AND_CL73BAM))) { 825 LOG_WARN(BSL_LS_SOC_PHY, 826 (BSL_META_U(unit, 827 "WC config init, CL37 BAM is not enabled with HG/BAM mode: u=%d p=%d\n"), unit,port)); 828 829 } 830 831 832 return SOC_E_NONE; 833 } 834 835 #else /* INCLUDE_XGXS_WC40 */ 836 int _xgxs_wc40_config_not_empty; 837 #endif /* INCLUDE_XGXS_WC40 */ 838