openbcm

wc40.h (2141734B)

---

 /***************************************************************************
  * 
  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
  * 
  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
  *
  * $brcm_Workfile: $
  * $brcm_Revision: $
  * $brcm_Date: $
  *
  * Module Description:
  *                     DO NOT EDIT THIS FILE DIRECTLY
  *
  * This module was generated magically with RDB from a source description
  * file. You must edit the source file for changes to be made to this file.
  *
  *
  * Date:           Generated on         Tue Aug 24 14:06:06 2010
  *                 MD5 Checksum         a7188d6d4cf83e4a3e1e6fe73bb6de35
  *
  * Compiled with:  RDB Utility          5.0
  *                 RDB Parser           3.0
  *                 rdb2macro.pm         4.0
  *                 Perl Interpreter     5.008008
  *                 Operating System     linux
  *
  * Spec Versions:  BAM_NextPage         1
  *                 CL73_UserB0          1
  *                 EEEtimerB0           1
  *                 EEEuserB0            1
  *                 EEEuserB1            1
  *                 GP2                  1
  *                 RemotePhy            1
  *                 aer                  1
  *                 cl49user             1
  *                 cl72_userBlk0        1
  *                 cl72_userBlk1        1
  *                 cl72ieee             1
  *                 cl82user             1
  *                 cl82user_b1          1
  *                 comboDigital         1
  *                 digital5             1
  *                 dsc_1                1
  *                 dsc_2                1
  *                 dsc_3                1
  *                 dsc_4                1
  *                 dsc_5                1
  *                 fecuser              1
  *                 fx100                1
  *                 ieee_an              1
  *                 ieee_cl22            1
  *                 ieee_dte             1
  *                 ieee_pcs             1
  *                 ieee_phy             1
  *                 ieee_pmd             1
  *                 micro                1
  *                 micro_Tmp1           1
  *                 micro_Tmp2           1
  *                 over1G               1
  *                 rx66                 1
  *                 rx66b1               1
  *                 rxBert               1
  *                 tx66                 1
  *                 txBert               1
  *                 xfi_bd0              1
  *                 xfi_bd1              1
  *                 xgxs                 1
  *                 xgxsBlk0             1
  *                 xgxsBlk1             1
  *                 xgxsBlk10            1
  *                 xgxsBlk2             1
  *                 xgxsBlk3             1
  *                 xgxsBlk4             1
  *                 xgxsBlk5             1
  *                 xgxsBlk6             1
  *                 xgxsBlk7             1
  *                 xgxsBlk8             1
  *                 xgxsBlk9             1
  *
  * Revision History:
  *
  * $brcm_Log: $
  */
 
 #ifndef WC40_H__
 #define WC40_H__
 
 /**
  * m = memory, c = core, r = register, f = field, d = data.
  */
 #if !defined(GET_FIELD) && !defined(SET_FIELD)
 #define BRCM_ALIGN(c,r,f)   c##_##r##_##f##_ALIGN
 #define BRCM_BITS(c,r,f)    c##_##r##_##f##_BITS
 #define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
 #define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
 
 #define GET_FIELD(m,c,r,f) \
 	((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f))
 
 #define SET_FIELD(m,c,r,f,d) \
 	((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \
 	 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \
 	)
 
 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
 
 #endif /* GET & SET */
 
 /****************************************************************************
  * Core Enums.
  */
 /****************************************************************************
  * Enums: EEEuserB0_cl36TxEEEStates_l
  */
 #define EEEuserB0_cl36TxEEEStates_l_TX_REFRESH             8
 #define EEEuserB0_cl36TxEEEStates_l_TX_QUIET               4
 #define EEEuserB0_cl36TxEEEStates_l_TX_SLEEP               2
 #define EEEuserB0_cl36TxEEEStates_l_TX_ACTIVE              1
 
 /****************************************************************************
  * Enums: EEEuserB0_cl36TxEEEStates_c
  */
 #define EEEuserB0_cl36TxEEEStates_c_TX_REFRESH             3
 #define EEEuserB0_cl36TxEEEStates_c_TX_QUIET               2
 #define EEEuserB0_cl36TxEEEStates_c_TX_SLEEP               1
 #define EEEuserB0_cl36TxEEEStates_c_TX_ACTIVE              0
 
 /****************************************************************************
  * Enums: EEEuserB0_cl49TxEEEStates_l
  */
 #define EEEuserB0_cl49TxEEEStates_l_SCR_RESET_2            64
 #define EEEuserB0_cl49TxEEEStates_l_SCR_RESET_1            32
 #define EEEuserB0_cl49TxEEEStates_l_TX_WAKE                16
 #define EEEuserB0_cl49TxEEEStates_l_TX_REFRESH             8
 #define EEEuserB0_cl49TxEEEStates_l_TX_QUIET               4
 #define EEEuserB0_cl49TxEEEStates_l_TX_SLEEP               2
 #define EEEuserB0_cl49TxEEEStates_l_TX_ACTIVE              1
 
 /****************************************************************************
  * Enums: EEEuserB0_cl49TxEEEStates_c
  */
 #define EEEuserB0_cl49TxEEEStates_c_SCR_RESET_2            6
 #define EEEuserB0_cl49TxEEEStates_c_SCR_RESET_1            5
 #define EEEuserB0_cl49TxEEEStates_c_TX_WAKE                4
 #define EEEuserB0_cl49TxEEEStates_c_TX_REFRESH             3
 #define EEEuserB0_cl49TxEEEStates_c_TX_QUIET               2
 #define EEEuserB0_cl49TxEEEStates_c_TX_SLEEP               1
 #define EEEuserB0_cl49TxEEEStates_c_TX_ACTIVE              0
 
 /****************************************************************************
  * Enums: EEEuserB0_cl36RxEEEStates_l
  */
 #define EEEuserB0_cl36RxEEEStates_l_RX_LINK_FAIL           32
 #define EEEuserB0_cl36RxEEEStates_l_RX_WTF                 16
 #define EEEuserB0_cl36RxEEEStates_l_RX_WAKE                8
 #define EEEuserB0_cl36RxEEEStates_l_RX_QUIET               4
 #define EEEuserB0_cl36RxEEEStates_l_RX_SLEEP               2
 #define EEEuserB0_cl36RxEEEStates_l_RX_ACTIVE              1
 
 /****************************************************************************
  * Enums: EEEuserB0_cl36RxEEEStates_c
  */
 #define EEEuserB0_cl36RxEEEStates_c_RX_LINK_FAIL           5
 #define EEEuserB0_cl36RxEEEStates_c_RX_WTF                 4
 #define EEEuserB0_cl36RxEEEStates_c_RX_WAKE                3
 #define EEEuserB0_cl36RxEEEStates_c_RX_QUIET               2
 #define EEEuserB0_cl36RxEEEStates_c_RX_SLEEP               1
 #define EEEuserB0_cl36RxEEEStates_c_RX_ACTIVE              0
 
 /****************************************************************************
  * Enums: EEEuserB0_cl49RxEEEStates_l
  */
 #define EEEuserB0_cl49RxEEEStates_l_RX_LINK_FAIL           32
 #define EEEuserB0_cl49RxEEEStates_l_RX_WTF                 16
 #define EEEuserB0_cl49RxEEEStates_l_RX_WAKE                8
 #define EEEuserB0_cl49RxEEEStates_l_RX_QUIET               4
 #define EEEuserB0_cl49RxEEEStates_l_RX_SLEEP               2
 #define EEEuserB0_cl49RxEEEStates_l_RX_ACTIVE              1
 
 /****************************************************************************
  * Enums: EEEuserB0_cl49RxEEEStates_c
  */
 #define EEEuserB0_cl49RxEEEStates_c_RX_LINK_FAIL           5
 #define EEEuserB0_cl49RxEEEStates_c_RX_WTF                 4
 #define EEEuserB0_cl49RxEEEStates_c_RX_WAKE                3
 #define EEEuserB0_cl49RxEEEStates_c_RX_QUIET               2
 #define EEEuserB0_cl49RxEEEStates_c_RX_SLEEP               1
 #define EEEuserB0_cl49RxEEEStates_c_RX_ACTIVE              0
 
 /****************************************************************************
  * Enums: aer_operationModes
  */
 #define aer_operationModes_XGXS                            0
 #define aer_operationModes_XGXG_nCC                        1
 #define aer_operationModes_Indlane_OS8                     4
 #define aer_operationModes_IndLane_OS5                     5
 #define aer_operationModes_PCI                             7
 #define aer_operationModes_XGXS_nLQ                        8
 #define aer_operationModes_XGXS_nLQnCC                     9
 #define aer_operationModes_PBypass                         10
 #define aer_operationModes_PBypass_nDSK                    11
 #define aer_operationModes_ComboCoreMode                   12
 #define aer_operationModes_Clocks_off                      15
 
 /****************************************************************************
  * Enums: aer_actualSpeeds4
  */
 #define aer_actualSpeeds4_dr_10M                           0
 #define aer_actualSpeeds4_dr_100M                          1
 #define aer_actualSpeeds4_dr_1G                            2
 #define aer_actualSpeeds4_dr_2p5G                          3
 #define aer_actualSpeeds4_dr_5G_X4                         4
 #define aer_actualSpeeds4_dr_6G_X4                         5
 #define aer_actualSpeeds4_dr_10G_HiG                       6
 #define aer_actualSpeeds4_dr_10G_CX4                       7
 #define aer_actualSpeeds4_dr_12G_HiG                       8
 #define aer_actualSpeeds4_dr_12p5G_X4                      9
 #define aer_actualSpeeds4_dr_13G_X4                        10
 #define aer_actualSpeeds4_dr_15G_X4                        11
 #define aer_actualSpeeds4_dr_16G_X4                        12
 
 /****************************************************************************
  * Enums: aer_actualSpeeds5
  */
 #define aer_actualSpeeds5_dr_10M                           0
 #define aer_actualSpeeds5_dr_100M                          1
 #define aer_actualSpeeds5_dr_1G                            2
 #define aer_actualSpeeds5_dr_2p5G                          3
 #define aer_actualSpeeds5_dr_5G_X4                         4
 #define aer_actualSpeeds5_dr_6G_X4                         5
 #define aer_actualSpeeds5_dr_10G_HiG                       6
 #define aer_actualSpeeds5_dr_10G_CX4                       7
 #define aer_actualSpeeds5_dr_12G_HiG                       8
 #define aer_actualSpeeds5_dr_12p5G_X4                      9
 #define aer_actualSpeeds5_dr_13G_X4                        10
 #define aer_actualSpeeds5_dr_15G_X4                        11
 #define aer_actualSpeeds5_dr_16G_X4                        12
 #define aer_actualSpeeds5_dr_1G_KX                         13
 #define aer_actualSpeeds5_dr_10G_KX4                       14
 #define aer_actualSpeeds5_dr_10G_KR                        15
 #define aer_actualSpeeds5_dr_5G                            16
 #define aer_actualSpeeds5_dr_6p4G                          17
 #define aer_actualSpeeds5_dr_20G_X4                        18
 #define aer_actualSpeeds5_dr_21G_X4                        19
 #define aer_actualSpeeds5_dr_25G_X4                        20
 #define aer_actualSpeeds5_dr_10G_HiG_DXGXS                 21
 #define aer_actualSpeeds5_dr_10G_DXGXS                     22
 #define aer_actualSpeeds5_dr_10p5G_HiG_DXGXS               23
 #define aer_actualSpeeds5_dr_10p5G_DXGXS                   24
 #define aer_actualSpeeds5_dr_12p773G_HiG_DXGXS             25
 #define aer_actualSpeeds5_dr_12p773G_DXGXS                 26
 #define aer_actualSpeeds5_dr_10G_XFI                       27
 #define aer_actualSpeeds5_dr_40G                           28
 #define aer_actualSpeeds5_dr_20G_HiG_DXGXS                 29
 #define aer_actualSpeeds5_dr_20G_DXGXS                     30
 #define aer_actualSpeeds5_dr_10G_SFI                       31
 #define aer_actualSpeeds5_dr_31p5G                         32
 #define aer_actualSpeeds5_dr_32p7G                         33
 #define aer_actualSpeeds5_dr_20G_SCR                       34
 #define aer_actualSpeeds5_dr_10G_HiG_DXGXS_SCR             35
 #define aer_actualSpeeds5_dr_10G_DXGXS_SCR                 36
 #define aer_actualSpeeds5_dr_12G_R2                        37
 #define aer_actualSpeeds5_dr_10G_X2                        38
 #define aer_actualSpeeds5_dr_40G_KR4                       39
 #define aer_actualSpeeds5_dr_40G_CR4                       40
 #define aer_actualSpeeds5_dr_100G_CR10                     41
 
 /****************************************************************************
  * Enums: aer_actualSpeedsMisc1
  */
 #define aer_actualSpeedsMisc1_dr_2500BRCM_X1               16
 #define aer_actualSpeedsMisc1_dr_5000BRCM_X4               17
 #define aer_actualSpeedsMisc1_dr_6000BRCM_X4               18
 #define aer_actualSpeedsMisc1_dr_10GHiGig_X4               19
 #define aer_actualSpeedsMisc1_dr_10GBASE_CX4               20
 #define aer_actualSpeedsMisc1_dr_12GHiGig_X4               21
 #define aer_actualSpeedsMisc1_dr_12p5GHiGig_X4             22
 #define aer_actualSpeedsMisc1_dr_13GHiGig_X4               23
 #define aer_actualSpeedsMisc1_dr_15GHiGig_X4               24
 #define aer_actualSpeedsMisc1_dr_16GHiGig_X4               25
 #define aer_actualSpeedsMisc1_dr_5000BRCM_X1               26
 #define aer_actualSpeedsMisc1_dr_6363BRCM_X1               27
 #define aer_actualSpeedsMisc1_dr_20GHiGig_X4               28
 #define aer_actualSpeedsMisc1_dr_21GHiGig_X4               29
 #define aer_actualSpeedsMisc1_dr_25p45GHiGig_X4            30
 #define aer_actualSpeedsMisc1_dr_10G_HiG_DXGXS             31
 
 /****************************************************************************
  * Enums: aer_IndLaneModes
  */
 #define aer_IndLaneModes_SWSDR_div2                        0
 #define aer_IndLaneModes_SWSDR_div1                        1
 #define aer_IndLaneModes_DWSDR_div2                        2
 #define aer_IndLaneModes_DWSDR_div1                        3
 
 /****************************************************************************
  * Enums: aer_prbsSelect
  */
 #define aer_prbsSelect_prbs7                               0
 #define aer_prbsSelect_prbs15                              1
 #define aer_prbsSelect_prbs23                              2
 #define aer_prbsSelect_prbs31                              3
 
 /****************************************************************************
  * Enums: aer_vcoDivider
  */
 #define aer_vcoDivider_div32                               0
 #define aer_vcoDivider_div36                               1
 #define aer_vcoDivider_div40                               2
 #define aer_vcoDivider_div42                               3
 #define aer_vcoDivider_div48                               4
 #define aer_vcoDivider_div50                               5
 #define aer_vcoDivider_div52                               6
 #define aer_vcoDivider_div54                               7
 #define aer_vcoDivider_div60                               8
 #define aer_vcoDivider_div64                               9
 #define aer_vcoDivider_div66                               10
 #define aer_vcoDivider_div68                               11
 #define aer_vcoDivider_div80                               12
 #define aer_vcoDivider_div120                              13
 #define aer_vcoDivider_div200                              14
 #define aer_vcoDivider_div240                              15
 
 /****************************************************************************
  * Enums: aer_refClkSelect
  */
 #define aer_refClkSelect_clk_25MHz                         0
 #define aer_refClkSelect_clk_100MHz                        1
 #define aer_refClkSelect_clk_125MHz                        2
 #define aer_refClkSelect_clk_156p25MHz                     3
 #define aer_refClkSelect_clk_187p5MHz                      4
 #define aer_refClkSelect_clk_161p25Mhz                     5
 #define aer_refClkSelect_clk_50Mhz                         6
 #define aer_refClkSelect_clk_106p25Mhz                     7
 
 /****************************************************************************
  * Enums: aer_aerMMDdevTypeSelect
  */
 #define aer_aerMMDdevTypeSelect_combo_core                 0
 #define aer_aerMMDdevTypeSelect_PMA_PMD                    1
 #define aer_aerMMDdevTypeSelect_PCS                        3
 #define aer_aerMMDdevTypeSelect_PHY                        4
 #define aer_aerMMDdevTypeSelect_DTE                        5
 #define aer_aerMMDdevTypeSelect_CL73_AN                    7
 
 /****************************************************************************
  * Enums: aer_aerMMDportSelect
  */
 #define aer_aerMMDportSelect_ln0                           0
 #define aer_aerMMDportSelect_ln1                           1
 #define aer_aerMMDportSelect_ln2                           2
 #define aer_aerMMDportSelect_ln3                           3
 #define aer_aerMMDportSelect_BCST                          511
 
 /****************************************************************************
  * Enums: aer_firmwareModeSelect
  */
 #define aer_firmwareModeSelect_DEFAULT                     0
 #define aer_firmwareModeSelect_SFP_OPT_LR                  1
 #define aer_firmwareModeSelect_SFP_DAC                     2
 #define aer_firmwareModeSelect_XLAUI                       3
 #define aer_firmwareModeSelect_LONG_CH_6G                  4
 
 /****************************************************************************
  * Enums: aer_tempIdxSelect
  */
 #define aer_tempIdxSelect_LTE__22p9C                       15
 #define aer_tempIdxSelect_LTE__12p6C                       14
 #define aer_tempIdxSelect_LTE__3p0C                        13
 #define aer_tempIdxSelect_LTE_6p7C                         12
 #define aer_tempIdxSelect_LTE_16p4C                        11
 #define aer_tempIdxSelect_LTE_26p6C                        10
 #define aer_tempIdxSelect_LTE_36p3C                        9
 #define aer_tempIdxSelect_LTE_46p0C                        8
 #define aer_tempIdxSelect_LTE_56p2C                        7
 #define aer_tempIdxSelect_LTE_65p9C                        6
 #define aer_tempIdxSelect_LTE_75p6C                        5
 #define aer_tempIdxSelect_LTE_85p3C                        4
 #define aer_tempIdxSelect_LTE_95p5C                        3
 #define aer_tempIdxSelect_LTE_105p2C                       2
 #define aer_tempIdxSelect_LTE_114p9C                       1
 #define aer_tempIdxSelect_LTE_125p1C                       0
 
 /****************************************************************************
  * Enums: comboDigital_operationModes
  */
 #define comboDigital_operationModes_XGXS                   0
 #define comboDigital_operationModes_XGXG_nCC               1
 #define comboDigital_operationModes_Indlane_OS8            4
 #define comboDigital_operationModes_IndLane_OS5            5
 #define comboDigital_operationModes_PCI                    7
 #define comboDigital_operationModes_XGXS_nLQ               8
 #define comboDigital_operationModes_XGXS_nLQnCC            9
 #define comboDigital_operationModes_PBypass                10
 #define comboDigital_operationModes_PBypass_nDSK           11
 #define comboDigital_operationModes_ComboCoreMode          12
 #define comboDigital_operationModes_Clocks_off             15
 
 /****************************************************************************
  * Enums: comboDigital_actualSpeeds4
  */
 #define comboDigital_actualSpeeds4_dr_10M                  0
 #define comboDigital_actualSpeeds4_dr_100M                 1
 #define comboDigital_actualSpeeds4_dr_1G                   2
 #define comboDigital_actualSpeeds4_dr_2p5G                 3
 #define comboDigital_actualSpeeds4_dr_5G_X4                4
 #define comboDigital_actualSpeeds4_dr_6G_X4                5
 #define comboDigital_actualSpeeds4_dr_10G_HiG              6
 #define comboDigital_actualSpeeds4_dr_10G_CX4              7
 #define comboDigital_actualSpeeds4_dr_12G_HiG              8
 #define comboDigital_actualSpeeds4_dr_12p5G_X4             9
 #define comboDigital_actualSpeeds4_dr_13G_X4               10
 #define comboDigital_actualSpeeds4_dr_15G_X4               11
 #define comboDigital_actualSpeeds4_dr_16G_X4               12
 
 /****************************************************************************
  * Enums: comboDigital_actualSpeeds5
  */
 #define comboDigital_actualSpeeds5_dr_10M                  0
 #define comboDigital_actualSpeeds5_dr_100M                 1
 #define comboDigital_actualSpeeds5_dr_1G                   2
 #define comboDigital_actualSpeeds5_dr_2p5G                 3
 #define comboDigital_actualSpeeds5_dr_5G_X4                4
 #define comboDigital_actualSpeeds5_dr_6G_X4                5
 #define comboDigital_actualSpeeds5_dr_10G_HiG              6
 #define comboDigital_actualSpeeds5_dr_10G_CX4              7
 #define comboDigital_actualSpeeds5_dr_12G_HiG              8
 #define comboDigital_actualSpeeds5_dr_12p5G_X4             9
 #define comboDigital_actualSpeeds5_dr_13G_X4               10
 #define comboDigital_actualSpeeds5_dr_15G_X4               11
 #define comboDigital_actualSpeeds5_dr_16G_X4               12
 #define comboDigital_actualSpeeds5_dr_1G_KX                13
 #define comboDigital_actualSpeeds5_dr_10G_KX4              14
 #define comboDigital_actualSpeeds5_dr_10G_KR               15
 #define comboDigital_actualSpeeds5_dr_5G                   16
 #define comboDigital_actualSpeeds5_dr_6p4G                 17
 #define comboDigital_actualSpeeds5_dr_20G_X4               18
 #define comboDigital_actualSpeeds5_dr_21G_X4               19
 #define comboDigital_actualSpeeds5_dr_25G_X4               20
 #define comboDigital_actualSpeeds5_dr_10G_HiG_DXGXS        21
 #define comboDigital_actualSpeeds5_dr_10G_DXGXS            22
 #define comboDigital_actualSpeeds5_dr_10p5G_HiG_DXGXS      23
 #define comboDigital_actualSpeeds5_dr_10p5G_DXGXS          24
 #define comboDigital_actualSpeeds5_dr_12p773G_HiG_DXGXS    25
 #define comboDigital_actualSpeeds5_dr_12p773G_DXGXS        26
 #define comboDigital_actualSpeeds5_dr_10G_XFI              27
 #define comboDigital_actualSpeeds5_dr_40G                  28
 #define comboDigital_actualSpeeds5_dr_20G_HiG_DXGXS        29
 #define comboDigital_actualSpeeds5_dr_20G_DXGXS            30
 #define comboDigital_actualSpeeds5_dr_10G_SFI              31
 #define comboDigital_actualSpeeds5_dr_31p5G                32
 #define comboDigital_actualSpeeds5_dr_32p7G                33
 #define comboDigital_actualSpeeds5_dr_20G_SCR              34
 #define comboDigital_actualSpeeds5_dr_10G_HiG_DXGXS_SCR    35
 #define comboDigital_actualSpeeds5_dr_10G_DXGXS_SCR        36
 #define comboDigital_actualSpeeds5_dr_12G_R2               37
 #define comboDigital_actualSpeeds5_dr_10G_X2               38
 #define comboDigital_actualSpeeds5_dr_40G_KR4              39
 #define comboDigital_actualSpeeds5_dr_40G_CR4              40
 #define comboDigital_actualSpeeds5_dr_100G_CR10            41
 
 /****************************************************************************
  * Enums: comboDigital_actualSpeedsMisc1
  */
 #define comboDigital_actualSpeedsMisc1_dr_2500BRCM_X1      16
 #define comboDigital_actualSpeedsMisc1_dr_5000BRCM_X4      17
 #define comboDigital_actualSpeedsMisc1_dr_6000BRCM_X4      18
 #define comboDigital_actualSpeedsMisc1_dr_10GHiGig_X4      19
 #define comboDigital_actualSpeedsMisc1_dr_10GBASE_CX4      20
 #define comboDigital_actualSpeedsMisc1_dr_12GHiGig_X4      21
 #define comboDigital_actualSpeedsMisc1_dr_12p5GHiGig_X4    22
 #define comboDigital_actualSpeedsMisc1_dr_13GHiGig_X4      23
 #define comboDigital_actualSpeedsMisc1_dr_15GHiGig_X4      24
 #define comboDigital_actualSpeedsMisc1_dr_16GHiGig_X4      25
 #define comboDigital_actualSpeedsMisc1_dr_5000BRCM_X1      26
 #define comboDigital_actualSpeedsMisc1_dr_6363BRCM_X1      27
 #define comboDigital_actualSpeedsMisc1_dr_20GHiGig_X4      28
 #define comboDigital_actualSpeedsMisc1_dr_21GHiGig_X4      29
 #define comboDigital_actualSpeedsMisc1_dr_25p45GHiGig_X4   30
 #define comboDigital_actualSpeedsMisc1_dr_10G_HiG_DXGXS    31
 
 /****************************************************************************
  * Enums: comboDigital_IndLaneModes
  */
 #define comboDigital_IndLaneModes_SWSDR_div2               0
 #define comboDigital_IndLaneModes_SWSDR_div1               1
 #define comboDigital_IndLaneModes_DWSDR_div2               2
 #define comboDigital_IndLaneModes_DWSDR_div1               3
 
 /****************************************************************************
  * Enums: comboDigital_prbsSelect
  */
 #define comboDigital_prbsSelect_prbs7                      0
 #define comboDigital_prbsSelect_prbs15                     1
 #define comboDigital_prbsSelect_prbs23                     2
 #define comboDigital_prbsSelect_prbs31                     3
 
 /****************************************************************************
  * Enums: comboDigital_vcoDivider
  */
 #define comboDigital_vcoDivider_div32                      0
 #define comboDigital_vcoDivider_div36                      1
 #define comboDigital_vcoDivider_div40                      2
 #define comboDigital_vcoDivider_div42                      3
 #define comboDigital_vcoDivider_div48                      4
 #define comboDigital_vcoDivider_div50                      5
 #define comboDigital_vcoDivider_div52                      6
 #define comboDigital_vcoDivider_div54                      7
 #define comboDigital_vcoDivider_div60                      8
 #define comboDigital_vcoDivider_div64                      9
 #define comboDigital_vcoDivider_div66                      10
 #define comboDigital_vcoDivider_div68                      11
 #define comboDigital_vcoDivider_div80                      12
 #define comboDigital_vcoDivider_div120                     13
 #define comboDigital_vcoDivider_div200                     14
 #define comboDigital_vcoDivider_div240                     15
 
 /****************************************************************************
  * Enums: comboDigital_refClkSelect
  */
 #define comboDigital_refClkSelect_clk_25MHz                0
 #define comboDigital_refClkSelect_clk_100MHz               1
 #define comboDigital_refClkSelect_clk_125MHz               2
 #define comboDigital_refClkSelect_clk_156p25MHz            3
 #define comboDigital_refClkSelect_clk_187p5MHz             4
 #define comboDigital_refClkSelect_clk_161p25Mhz            5
 #define comboDigital_refClkSelect_clk_50Mhz                6
 #define comboDigital_refClkSelect_clk_106p25Mhz            7
 
 /****************************************************************************
  * Enums: comboDigital_aerMMDdevTypeSelect
  */
 #define comboDigital_aerMMDdevTypeSelect_combo_core        0
 #define comboDigital_aerMMDdevTypeSelect_PMA_PMD           1
 #define comboDigital_aerMMDdevTypeSelect_PCS               3
 #define comboDigital_aerMMDdevTypeSelect_PHY               4
 #define comboDigital_aerMMDdevTypeSelect_DTE               5
 #define comboDigital_aerMMDdevTypeSelect_CL73_AN           7
 
 /****************************************************************************
  * Enums: comboDigital_aerMMDportSelect
  */
 #define comboDigital_aerMMDportSelect_ln0                  0
 #define comboDigital_aerMMDportSelect_ln1                  1
 #define comboDigital_aerMMDportSelect_ln2                  2
 #define comboDigital_aerMMDportSelect_ln3                  3
 #define comboDigital_aerMMDportSelect_BCST                 511
 
 /****************************************************************************
  * Enums: comboDigital_firmwareModeSelect
  */
 #define comboDigital_firmwareModeSelect_DEFAULT            0
 #define comboDigital_firmwareModeSelect_SFP_OPT_LR         1
 #define comboDigital_firmwareModeSelect_SFP_DAC            2
 #define comboDigital_firmwareModeSelect_XLAUI              3
 #define comboDigital_firmwareModeSelect_LONG_CH_6G         4
 
 /****************************************************************************
  * Enums: comboDigital_tempIdxSelect
  */
 #define comboDigital_tempIdxSelect_LTE__22p9C              15
 #define comboDigital_tempIdxSelect_LTE__12p6C              14
 #define comboDigital_tempIdxSelect_LTE__3p0C               13
 #define comboDigital_tempIdxSelect_LTE_6p7C                12
 #define comboDigital_tempIdxSelect_LTE_16p4C               11
 #define comboDigital_tempIdxSelect_LTE_26p6C               10
 #define comboDigital_tempIdxSelect_LTE_36p3C               9
 #define comboDigital_tempIdxSelect_LTE_46p0C               8
 #define comboDigital_tempIdxSelect_LTE_56p2C               7
 #define comboDigital_tempIdxSelect_LTE_65p9C               6
 #define comboDigital_tempIdxSelect_LTE_75p6C               5
 #define comboDigital_tempIdxSelect_LTE_85p3C               4
 #define comboDigital_tempIdxSelect_LTE_95p5C               3
 #define comboDigital_tempIdxSelect_LTE_105p2C              2
 #define comboDigital_tempIdxSelect_LTE_114p9C              1
 #define comboDigital_tempIdxSelect_LTE_125p1C              0
 
 /****************************************************************************
  * Enums: digital5_operationModes
  */
 #define digital5_operationModes_XGXS                       0
 #define digital5_operationModes_XGXG_nCC                   1
 #define digital5_operationModes_Indlane_OS8                4
 #define digital5_operationModes_IndLane_OS5                5
 #define digital5_operationModes_PCI                        7
 #define digital5_operationModes_XGXS_nLQ                   8
 #define digital5_operationModes_XGXS_nLQnCC                9
 #define digital5_operationModes_PBypass                    10
 #define digital5_operationModes_PBypass_nDSK               11
 #define digital5_operationModes_ComboCoreMode              12
 #define digital5_operationModes_Clocks_off                 15
 
 /****************************************************************************
  * Enums: digital5_actualSpeeds4
  */
 #define digital5_actualSpeeds4_dr_10M                      0
 #define digital5_actualSpeeds4_dr_100M                     1
 #define digital5_actualSpeeds4_dr_1G                       2
 #define digital5_actualSpeeds4_dr_2p5G                     3
 #define digital5_actualSpeeds4_dr_5G_X4                    4
 #define digital5_actualSpeeds4_dr_6G_X4                    5
 #define digital5_actualSpeeds4_dr_10G_HiG                  6
 #define digital5_actualSpeeds4_dr_10G_CX4                  7
 #define digital5_actualSpeeds4_dr_12G_HiG                  8
 #define digital5_actualSpeeds4_dr_12p5G_X4                 9
 #define digital5_actualSpeeds4_dr_13G_X4                   10
 #define digital5_actualSpeeds4_dr_15G_X4                   11
 #define digital5_actualSpeeds4_dr_16G_X4                   12
 
 /****************************************************************************
  * Enums: digital5_actualSpeeds5
  */
 #define digital5_actualSpeeds5_dr_10M                      0
 #define digital5_actualSpeeds5_dr_100M                     1
 #define digital5_actualSpeeds5_dr_1G                       2
 #define digital5_actualSpeeds5_dr_2p5G                     3
 #define digital5_actualSpeeds5_dr_5G_X4                    4
 #define digital5_actualSpeeds5_dr_6G_X4                    5
 #define digital5_actualSpeeds5_dr_10G_HiG                  6
 #define digital5_actualSpeeds5_dr_10G_CX4                  7
 #define digital5_actualSpeeds5_dr_12G_HiG                  8
 #define digital5_actualSpeeds5_dr_12p5G_X4                 9
 #define digital5_actualSpeeds5_dr_13G_X4                   10
 #define digital5_actualSpeeds5_dr_15G_X4                   11
 #define digital5_actualSpeeds5_dr_16G_X4                   12
 #define digital5_actualSpeeds5_dr_1G_KX                    13
 #define digital5_actualSpeeds5_dr_10G_KX4                  14
 #define digital5_actualSpeeds5_dr_10G_KR                   15
 #define digital5_actualSpeeds5_dr_5G                       16
 #define digital5_actualSpeeds5_dr_6p4G                     17
 #define digital5_actualSpeeds5_dr_20G_X4                   18
 #define digital5_actualSpeeds5_dr_21G_X4                   19
 #define digital5_actualSpeeds5_dr_25G_X4                   20
 #define digital5_actualSpeeds5_dr_10G_HiG_DXGXS            21
 #define digital5_actualSpeeds5_dr_10G_DXGXS                22
 #define digital5_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
 #define digital5_actualSpeeds5_dr_10p5G_DXGXS              24
 #define digital5_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
 #define digital5_actualSpeeds5_dr_12p773G_DXGXS            26
 #define digital5_actualSpeeds5_dr_10G_XFI                  27
 #define digital5_actualSpeeds5_dr_40G                      28
 #define digital5_actualSpeeds5_dr_20G_HiG_DXGXS            29
 #define digital5_actualSpeeds5_dr_20G_DXGXS                30
 #define digital5_actualSpeeds5_dr_10G_SFI                  31
 #define digital5_actualSpeeds5_dr_31p5G                    32
 #define digital5_actualSpeeds5_dr_32p7G                    33
 #define digital5_actualSpeeds5_dr_20G_SCR                  34
 #define digital5_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
 #define digital5_actualSpeeds5_dr_10G_DXGXS_SCR            36
 #define digital5_actualSpeeds5_dr_12G_R2                   37
 #define digital5_actualSpeeds5_dr_10G_X2                   38
 #define digital5_actualSpeeds5_dr_40G_KR4                  39
 #define digital5_actualSpeeds5_dr_40G_CR4                  40
 #define digital5_actualSpeeds5_dr_100G_CR10                41
 
 /****************************************************************************
  * Enums: digital5_actualSpeedsMisc1
  */
 #define digital5_actualSpeedsMisc1_dr_2500BRCM_X1          16
 #define digital5_actualSpeedsMisc1_dr_5000BRCM_X4          17
 #define digital5_actualSpeedsMisc1_dr_6000BRCM_X4          18
 #define digital5_actualSpeedsMisc1_dr_10GHiGig_X4          19
 #define digital5_actualSpeedsMisc1_dr_10GBASE_CX4          20
 #define digital5_actualSpeedsMisc1_dr_12GHiGig_X4          21
 #define digital5_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
 #define digital5_actualSpeedsMisc1_dr_13GHiGig_X4          23
 #define digital5_actualSpeedsMisc1_dr_15GHiGig_X4          24
 #define digital5_actualSpeedsMisc1_dr_16GHiGig_X4          25
 #define digital5_actualSpeedsMisc1_dr_5000BRCM_X1          26
 #define digital5_actualSpeedsMisc1_dr_6363BRCM_X1          27
 #define digital5_actualSpeedsMisc1_dr_20GHiGig_X4          28
 #define digital5_actualSpeedsMisc1_dr_21GHiGig_X4          29
 #define digital5_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
 #define digital5_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31
 
 /****************************************************************************
  * Enums: digital5_IndLaneModes
  */
 #define digital5_IndLaneModes_SWSDR_div2                   0
 #define digital5_IndLaneModes_SWSDR_div1                   1
 #define digital5_IndLaneModes_DWSDR_div2                   2
 #define digital5_IndLaneModes_DWSDR_div1                   3
 
 /****************************************************************************
  * Enums: digital5_prbsSelect
  */
 #define digital5_prbsSelect_prbs7                          0
 #define digital5_prbsSelect_prbs15                         1
 #define digital5_prbsSelect_prbs23                         2
 #define digital5_prbsSelect_prbs31                         3
 
 /****************************************************************************
  * Enums: digital5_vcoDivider
  */
 #define digital5_vcoDivider_div32                          0
 #define digital5_vcoDivider_div36                          1
 #define digital5_vcoDivider_div40                          2
 #define digital5_vcoDivider_div42                          3
 #define digital5_vcoDivider_div48                          4
 #define digital5_vcoDivider_div50                          5
 #define digital5_vcoDivider_div52                          6
 #define digital5_vcoDivider_div54                          7
 #define digital5_vcoDivider_div60                          8
 #define digital5_vcoDivider_div64                          9
 #define digital5_vcoDivider_div66                          10
 #define digital5_vcoDivider_div68                          11
 #define digital5_vcoDivider_div80                          12
 #define digital5_vcoDivider_div120                         13
 #define digital5_vcoDivider_div200                         14
 #define digital5_vcoDivider_div240                         15
 
 /****************************************************************************
  * Enums: digital5_refClkSelect
  */
 #define digital5_refClkSelect_clk_25MHz                    0
 #define digital5_refClkSelect_clk_100MHz                   1
 #define digital5_refClkSelect_clk_125MHz                   2
 #define digital5_refClkSelect_clk_156p25MHz                3
 #define digital5_refClkSelect_clk_187p5MHz                 4
 #define digital5_refClkSelect_clk_161p25Mhz                5
 #define digital5_refClkSelect_clk_50Mhz                    6
 #define digital5_refClkSelect_clk_106p25Mhz                7
 
 /****************************************************************************
  * Enums: digital5_aerMMDdevTypeSelect
  */
 #define digital5_aerMMDdevTypeSelect_combo_core            0
 #define digital5_aerMMDdevTypeSelect_PMA_PMD               1
 #define digital5_aerMMDdevTypeSelect_PCS                   3
 #define digital5_aerMMDdevTypeSelect_PHY                   4
 #define digital5_aerMMDdevTypeSelect_DTE                   5
 #define digital5_aerMMDdevTypeSelect_CL73_AN               7
 
 /****************************************************************************
  * Enums: digital5_aerMMDportSelect
  */
 #define digital5_aerMMDportSelect_ln0                      0
 #define digital5_aerMMDportSelect_ln1                      1
 #define digital5_aerMMDportSelect_ln2                      2
 #define digital5_aerMMDportSelect_ln3                      3
 #define digital5_aerMMDportSelect_BCST                     511
 
 /****************************************************************************
  * Enums: digital5_firmwareModeSelect
  */
 #define digital5_firmwareModeSelect_DEFAULT                0
 #define digital5_firmwareModeSelect_SFP_OPT_LR             1
 #define digital5_firmwareModeSelect_SFP_DAC                2
 #define digital5_firmwareModeSelect_XLAUI                  3
 #define digital5_firmwareModeSelect_LONG_CH_6G             4
 
 /****************************************************************************
  * Enums: digital5_tempIdxSelect
  */
 #define digital5_tempIdxSelect_LTE__22p9C                  15
 #define digital5_tempIdxSelect_LTE__12p6C                  14
 #define digital5_tempIdxSelect_LTE__3p0C                   13
 #define digital5_tempIdxSelect_LTE_6p7C                    12
 #define digital5_tempIdxSelect_LTE_16p4C                   11
 #define digital5_tempIdxSelect_LTE_26p6C                   10
 #define digital5_tempIdxSelect_LTE_36p3C                   9
 #define digital5_tempIdxSelect_LTE_46p0C                   8
 #define digital5_tempIdxSelect_LTE_56p2C                   7
 #define digital5_tempIdxSelect_LTE_65p9C                   6
 #define digital5_tempIdxSelect_LTE_75p6C                   5
 #define digital5_tempIdxSelect_LTE_85p3C                   4
 #define digital5_tempIdxSelect_LTE_95p5C                   3
 #define digital5_tempIdxSelect_LTE_105p2C                  2
 #define digital5_tempIdxSelect_LTE_114p9C                  1
 #define digital5_tempIdxSelect_LTE_125p1C                  0
 
 /****************************************************************************
  * Enums: ieee_an_operationModes
  */
 #define ieee_an_operationModes_XGXS                        0
 #define ieee_an_operationModes_XGXG_nCC                    1
 #define ieee_an_operationModes_Indlane_OS8                 4
 #define ieee_an_operationModes_IndLane_OS5                 5
 #define ieee_an_operationModes_PCI                         7
 #define ieee_an_operationModes_XGXS_nLQ                    8
 #define ieee_an_operationModes_XGXS_nLQnCC                 9
 #define ieee_an_operationModes_PBypass                     10
 #define ieee_an_operationModes_PBypass_nDSK                11
 #define ieee_an_operationModes_ComboCoreMode               12
 #define ieee_an_operationModes_Clocks_off                  15
 
 /****************************************************************************
  * Enums: ieee_an_actualSpeeds4
  */
 #define ieee_an_actualSpeeds4_dr_10M                       0
 #define ieee_an_actualSpeeds4_dr_100M                      1
 #define ieee_an_actualSpeeds4_dr_1G                        2
 #define ieee_an_actualSpeeds4_dr_2p5G                      3
 #define ieee_an_actualSpeeds4_dr_5G_X4                     4
 #define ieee_an_actualSpeeds4_dr_6G_X4                     5
 #define ieee_an_actualSpeeds4_dr_10G_HiG                   6
 #define ieee_an_actualSpeeds4_dr_10G_CX4                   7
 #define ieee_an_actualSpeeds4_dr_12G_HiG                   8
 #define ieee_an_actualSpeeds4_dr_12p5G_X4                  9
 #define ieee_an_actualSpeeds4_dr_13G_X4                    10
 #define ieee_an_actualSpeeds4_dr_15G_X4                    11
 #define ieee_an_actualSpeeds4_dr_16G_X4                    12
 
 /****************************************************************************
  * Enums: ieee_an_actualSpeeds5
  */
 #define ieee_an_actualSpeeds5_dr_10M                       0
 #define ieee_an_actualSpeeds5_dr_100M                      1
 #define ieee_an_actualSpeeds5_dr_1G                        2
 #define ieee_an_actualSpeeds5_dr_2p5G                      3
 #define ieee_an_actualSpeeds5_dr_5G_X4                     4
 #define ieee_an_actualSpeeds5_dr_6G_X4                     5
 #define ieee_an_actualSpeeds5_dr_10G_HiG                   6
 #define ieee_an_actualSpeeds5_dr_10G_CX4                   7
 #define ieee_an_actualSpeeds5_dr_12G_HiG                   8
 #define ieee_an_actualSpeeds5_dr_12p5G_X4                  9
 #define ieee_an_actualSpeeds5_dr_13G_X4                    10
 #define ieee_an_actualSpeeds5_dr_15G_X4                    11
 #define ieee_an_actualSpeeds5_dr_16G_X4                    12
 #define ieee_an_actualSpeeds5_dr_1G_KX                     13
 #define ieee_an_actualSpeeds5_dr_10G_KX4                   14
 #define ieee_an_actualSpeeds5_dr_10G_KR                    15
 #define ieee_an_actualSpeeds5_dr_5G                        16
 #define ieee_an_actualSpeeds5_dr_6p4G                      17
 #define ieee_an_actualSpeeds5_dr_20G_X4                    18
 #define ieee_an_actualSpeeds5_dr_21G_X4                    19
 #define ieee_an_actualSpeeds5_dr_25G_X4                    20
 #define ieee_an_actualSpeeds5_dr_10G_HiG_DXGXS             21
 #define ieee_an_actualSpeeds5_dr_10G_DXGXS                 22
 #define ieee_an_actualSpeeds5_dr_10p5G_HiG_DXGXS           23
 #define ieee_an_actualSpeeds5_dr_10p5G_DXGXS               24
 #define ieee_an_actualSpeeds5_dr_12p773G_HiG_DXGXS         25
 #define ieee_an_actualSpeeds5_dr_12p773G_DXGXS             26
 #define ieee_an_actualSpeeds5_dr_10G_XFI                   27
 #define ieee_an_actualSpeeds5_dr_40G                       28
 #define ieee_an_actualSpeeds5_dr_20G_HiG_DXGXS             29
 #define ieee_an_actualSpeeds5_dr_20G_DXGXS                 30
 #define ieee_an_actualSpeeds5_dr_10G_SFI                   31
 #define ieee_an_actualSpeeds5_dr_31p5G                     32
 #define ieee_an_actualSpeeds5_dr_32p7G                     33
 #define ieee_an_actualSpeeds5_dr_20G_SCR                   34
 #define ieee_an_actualSpeeds5_dr_10G_HiG_DXGXS_SCR         35
 #define ieee_an_actualSpeeds5_dr_10G_DXGXS_SCR             36
 #define ieee_an_actualSpeeds5_dr_12G_R2                    37
 #define ieee_an_actualSpeeds5_dr_10G_X2                    38
 #define ieee_an_actualSpeeds5_dr_40G_KR4                   39
 #define ieee_an_actualSpeeds5_dr_40G_CR4                   40
 #define ieee_an_actualSpeeds5_dr_100G_CR10                 41
 
 /****************************************************************************
  * Enums: ieee_an_actualSpeedsMisc1
  */
 #define ieee_an_actualSpeedsMisc1_dr_2500BRCM_X1           16
 #define ieee_an_actualSpeedsMisc1_dr_5000BRCM_X4           17
 #define ieee_an_actualSpeedsMisc1_dr_6000BRCM_X4           18
 #define ieee_an_actualSpeedsMisc1_dr_10GHiGig_X4           19
 #define ieee_an_actualSpeedsMisc1_dr_10GBASE_CX4           20
 #define ieee_an_actualSpeedsMisc1_dr_12GHiGig_X4           21
 #define ieee_an_actualSpeedsMisc1_dr_12p5GHiGig_X4         22
 #define ieee_an_actualSpeedsMisc1_dr_13GHiGig_X4           23
 #define ieee_an_actualSpeedsMisc1_dr_15GHiGig_X4           24
 #define ieee_an_actualSpeedsMisc1_dr_16GHiGig_X4           25
 #define ieee_an_actualSpeedsMisc1_dr_5000BRCM_X1           26
 #define ieee_an_actualSpeedsMisc1_dr_6363BRCM_X1           27
 #define ieee_an_actualSpeedsMisc1_dr_20GHiGig_X4           28
 #define ieee_an_actualSpeedsMisc1_dr_21GHiGig_X4           29
 #define ieee_an_actualSpeedsMisc1_dr_25p45GHiGig_X4        30
 #define ieee_an_actualSpeedsMisc1_dr_10G_HiG_DXGXS         31
 
 /****************************************************************************
  * Enums: ieee_an_IndLaneModes
  */
 #define ieee_an_IndLaneModes_SWSDR_div2                    0
 #define ieee_an_IndLaneModes_SWSDR_div1                    1
 #define ieee_an_IndLaneModes_DWSDR_div2                    2
 #define ieee_an_IndLaneModes_DWSDR_div1                    3
 
 /****************************************************************************
  * Enums: ieee_an_prbsSelect
  */
 #define ieee_an_prbsSelect_prbs7                           0
 #define ieee_an_prbsSelect_prbs15                          1
 #define ieee_an_prbsSelect_prbs23                          2
 #define ieee_an_prbsSelect_prbs31                          3
 
 /****************************************************************************
  * Enums: ieee_an_vcoDivider
  */
 #define ieee_an_vcoDivider_div32                           0
 #define ieee_an_vcoDivider_div36                           1
 #define ieee_an_vcoDivider_div40                           2
 #define ieee_an_vcoDivider_div42                           3
 #define ieee_an_vcoDivider_div48                           4
 #define ieee_an_vcoDivider_div50                           5
 #define ieee_an_vcoDivider_div52                           6
 #define ieee_an_vcoDivider_div54                           7
 #define ieee_an_vcoDivider_div60                           8
 #define ieee_an_vcoDivider_div64                           9
 #define ieee_an_vcoDivider_div66                           10
 #define ieee_an_vcoDivider_div68                           11
 #define ieee_an_vcoDivider_div80                           12
 #define ieee_an_vcoDivider_div120                          13
 #define ieee_an_vcoDivider_div200                          14
 #define ieee_an_vcoDivider_div240                          15
 
 /****************************************************************************
  * Enums: ieee_an_refClkSelect
  */
 #define ieee_an_refClkSelect_clk_25MHz                     0
 #define ieee_an_refClkSelect_clk_100MHz                    1
 #define ieee_an_refClkSelect_clk_125MHz                    2
 #define ieee_an_refClkSelect_clk_156p25MHz                 3
 #define ieee_an_refClkSelect_clk_187p5MHz                  4
 #define ieee_an_refClkSelect_clk_161p25Mhz                 5
 #define ieee_an_refClkSelect_clk_50Mhz                     6
 #define ieee_an_refClkSelect_clk_106p25Mhz                 7
 
 /****************************************************************************
  * Enums: ieee_an_aerMMDdevTypeSelect
  */
 #define ieee_an_aerMMDdevTypeSelect_combo_core             0
 #define ieee_an_aerMMDdevTypeSelect_PMA_PMD                1
 #define ieee_an_aerMMDdevTypeSelect_PCS                    3
 #define ieee_an_aerMMDdevTypeSelect_PHY                    4
 #define ieee_an_aerMMDdevTypeSelect_DTE                    5
 #define ieee_an_aerMMDdevTypeSelect_CL73_AN                7
 
 /****************************************************************************
  * Enums: ieee_an_aerMMDportSelect
  */
 #define ieee_an_aerMMDportSelect_ln0                       0
 #define ieee_an_aerMMDportSelect_ln1                       1
 #define ieee_an_aerMMDportSelect_ln2                       2
 #define ieee_an_aerMMDportSelect_ln3                       3
 #define ieee_an_aerMMDportSelect_BCST                      511
 
 /****************************************************************************
  * Enums: ieee_an_firmwareModeSelect
  */
 #define ieee_an_firmwareModeSelect_DEFAULT                 0
 #define ieee_an_firmwareModeSelect_SFP_OPT_LR              1
 #define ieee_an_firmwareModeSelect_SFP_DAC                 2
 #define ieee_an_firmwareModeSelect_XLAUI                   3
 #define ieee_an_firmwareModeSelect_LONG_CH_6G              4
 
 /****************************************************************************
  * Enums: ieee_an_tempIdxSelect
  */
 #define ieee_an_tempIdxSelect_LTE__22p9C                   15
 #define ieee_an_tempIdxSelect_LTE__12p6C                   14
 #define ieee_an_tempIdxSelect_LTE__3p0C                    13
 #define ieee_an_tempIdxSelect_LTE_6p7C                     12
 #define ieee_an_tempIdxSelect_LTE_16p4C                    11
 #define ieee_an_tempIdxSelect_LTE_26p6C                    10
 #define ieee_an_tempIdxSelect_LTE_36p3C                    9
 #define ieee_an_tempIdxSelect_LTE_46p0C                    8
 #define ieee_an_tempIdxSelect_LTE_56p2C                    7
 #define ieee_an_tempIdxSelect_LTE_65p9C                    6
 #define ieee_an_tempIdxSelect_LTE_75p6C                    5
 #define ieee_an_tempIdxSelect_LTE_85p3C                    4
 #define ieee_an_tempIdxSelect_LTE_95p5C                    3
 #define ieee_an_tempIdxSelect_LTE_105p2C                   2
 #define ieee_an_tempIdxSelect_LTE_114p9C                   1
 #define ieee_an_tempIdxSelect_LTE_125p1C                   0
 
 /****************************************************************************
  * Enums: micro_Tmp1_operationModes
  */
 #define micro_Tmp1_operationModes_XGXS                     0
 #define micro_Tmp1_operationModes_XGXG_nCC                 1
 #define micro_Tmp1_operationModes_Indlane_OS8              4
 #define micro_Tmp1_operationModes_IndLane_OS5              5
 #define micro_Tmp1_operationModes_PCI                      7
 #define micro_Tmp1_operationModes_XGXS_nLQ                 8
 #define micro_Tmp1_operationModes_XGXS_nLQnCC              9
 #define micro_Tmp1_operationModes_PBypass                  10
 #define micro_Tmp1_operationModes_PBypass_nDSK             11
 #define micro_Tmp1_operationModes_ComboCoreMode            12
 #define micro_Tmp1_operationModes_Clocks_off               15
 
 /****************************************************************************
  * Enums: micro_Tmp1_actualSpeeds4
  */
 #define micro_Tmp1_actualSpeeds4_dr_10M                    0
 #define micro_Tmp1_actualSpeeds4_dr_100M                   1
 #define micro_Tmp1_actualSpeeds4_dr_1G                     2
 #define micro_Tmp1_actualSpeeds4_dr_2p5G                   3
 #define micro_Tmp1_actualSpeeds4_dr_5G_X4                  4
 #define micro_Tmp1_actualSpeeds4_dr_6G_X4                  5
 #define micro_Tmp1_actualSpeeds4_dr_10G_HiG                6
 #define micro_Tmp1_actualSpeeds4_dr_10G_CX4                7
 #define micro_Tmp1_actualSpeeds4_dr_12G_HiG                8
 #define micro_Tmp1_actualSpeeds4_dr_12p5G_X4               9
 #define micro_Tmp1_actualSpeeds4_dr_13G_X4                 10
 #define micro_Tmp1_actualSpeeds4_dr_15G_X4                 11
 #define micro_Tmp1_actualSpeeds4_dr_16G_X4                 12
 
 /****************************************************************************
  * Enums: micro_Tmp1_actualSpeeds5
  */
 #define micro_Tmp1_actualSpeeds5_dr_10M                    0
 #define micro_Tmp1_actualSpeeds5_dr_100M                   1
 #define micro_Tmp1_actualSpeeds5_dr_1G                     2
 #define micro_Tmp1_actualSpeeds5_dr_2p5G                   3
 #define micro_Tmp1_actualSpeeds5_dr_5G_X4                  4
 #define micro_Tmp1_actualSpeeds5_dr_6G_X4                  5
 #define micro_Tmp1_actualSpeeds5_dr_10G_HiG                6
 #define micro_Tmp1_actualSpeeds5_dr_10G_CX4                7
 #define micro_Tmp1_actualSpeeds5_dr_12G_HiG                8
 #define micro_Tmp1_actualSpeeds5_dr_12p5G_X4               9
 #define micro_Tmp1_actualSpeeds5_dr_13G_X4                 10
 #define micro_Tmp1_actualSpeeds5_dr_15G_X4                 11
 #define micro_Tmp1_actualSpeeds5_dr_16G_X4                 12
 #define micro_Tmp1_actualSpeeds5_dr_1G_KX                  13
 #define micro_Tmp1_actualSpeeds5_dr_10G_KX4                14
 #define micro_Tmp1_actualSpeeds5_dr_10G_KR                 15
 #define micro_Tmp1_actualSpeeds5_dr_5G                     16
 #define micro_Tmp1_actualSpeeds5_dr_6p4G                   17
 #define micro_Tmp1_actualSpeeds5_dr_20G_X4                 18
 #define micro_Tmp1_actualSpeeds5_dr_21G_X4                 19
 #define micro_Tmp1_actualSpeeds5_dr_25G_X4                 20
 #define micro_Tmp1_actualSpeeds5_dr_10G_HiG_DXGXS          21
 #define micro_Tmp1_actualSpeeds5_dr_10G_DXGXS              22
 #define micro_Tmp1_actualSpeeds5_dr_10p5G_HiG_DXGXS        23
 #define micro_Tmp1_actualSpeeds5_dr_10p5G_DXGXS            24
 #define micro_Tmp1_actualSpeeds5_dr_12p773G_HiG_DXGXS      25
 #define micro_Tmp1_actualSpeeds5_dr_12p773G_DXGXS          26
 #define micro_Tmp1_actualSpeeds5_dr_10G_XFI                27
 #define micro_Tmp1_actualSpeeds5_dr_40G                    28
 #define micro_Tmp1_actualSpeeds5_dr_20G_HiG_DXGXS          29
 #define micro_Tmp1_actualSpeeds5_dr_20G_DXGXS              30
 #define micro_Tmp1_actualSpeeds5_dr_10G_SFI                31
 #define micro_Tmp1_actualSpeeds5_dr_31p5G                  32
 #define micro_Tmp1_actualSpeeds5_dr_32p7G                  33
 #define micro_Tmp1_actualSpeeds5_dr_20G_SCR                34
 #define micro_Tmp1_actualSpeeds5_dr_10G_HiG_DXGXS_SCR      35
 #define micro_Tmp1_actualSpeeds5_dr_10G_DXGXS_SCR          36
 #define micro_Tmp1_actualSpeeds5_dr_12G_R2                 37
 #define micro_Tmp1_actualSpeeds5_dr_10G_X2                 38
 #define micro_Tmp1_actualSpeeds5_dr_40G_KR4                39
 #define micro_Tmp1_actualSpeeds5_dr_40G_CR4                40
 #define micro_Tmp1_actualSpeeds5_dr_100G_CR10              41
 
 /****************************************************************************
  * Enums: micro_Tmp1_actualSpeedsMisc1
  */
 #define micro_Tmp1_actualSpeedsMisc1_dr_2500BRCM_X1        16
 #define micro_Tmp1_actualSpeedsMisc1_dr_5000BRCM_X4        17
 #define micro_Tmp1_actualSpeedsMisc1_dr_6000BRCM_X4        18
 #define micro_Tmp1_actualSpeedsMisc1_dr_10GHiGig_X4        19
 #define micro_Tmp1_actualSpeedsMisc1_dr_10GBASE_CX4        20
 #define micro_Tmp1_actualSpeedsMisc1_dr_12GHiGig_X4        21
 #define micro_Tmp1_actualSpeedsMisc1_dr_12p5GHiGig_X4      22
 #define micro_Tmp1_actualSpeedsMisc1_dr_13GHiGig_X4        23
 #define micro_Tmp1_actualSpeedsMisc1_dr_15GHiGig_X4        24
 #define micro_Tmp1_actualSpeedsMisc1_dr_16GHiGig_X4        25
 #define micro_Tmp1_actualSpeedsMisc1_dr_5000BRCM_X1        26
 #define micro_Tmp1_actualSpeedsMisc1_dr_6363BRCM_X1        27
 #define micro_Tmp1_actualSpeedsMisc1_dr_20GHiGig_X4        28
 #define micro_Tmp1_actualSpeedsMisc1_dr_21GHiGig_X4        29
 #define micro_Tmp1_actualSpeedsMisc1_dr_25p45GHiGig_X4     30
 #define micro_Tmp1_actualSpeedsMisc1_dr_10G_HiG_DXGXS      31
 
 /****************************************************************************
  * Enums: micro_Tmp1_IndLaneModes
  */
 #define micro_Tmp1_IndLaneModes_SWSDR_div2                 0
 #define micro_Tmp1_IndLaneModes_SWSDR_div1                 1
 #define micro_Tmp1_IndLaneModes_DWSDR_div2                 2
 #define micro_Tmp1_IndLaneModes_DWSDR_div1                 3
 
 /****************************************************************************
  * Enums: micro_Tmp1_prbsSelect
  */
 #define micro_Tmp1_prbsSelect_prbs7                        0
 #define micro_Tmp1_prbsSelect_prbs15                       1
 #define micro_Tmp1_prbsSelect_prbs23                       2
 #define micro_Tmp1_prbsSelect_prbs31                       3
 
 /****************************************************************************
  * Enums: micro_Tmp1_vcoDivider
  */
 #define micro_Tmp1_vcoDivider_div32                        0
 #define micro_Tmp1_vcoDivider_div36                        1
 #define micro_Tmp1_vcoDivider_div40                        2
 #define micro_Tmp1_vcoDivider_div42                        3
 #define micro_Tmp1_vcoDivider_div48                        4
 #define micro_Tmp1_vcoDivider_div50                        5
 #define micro_Tmp1_vcoDivider_div52                        6
 #define micro_Tmp1_vcoDivider_div54                        7
 #define micro_Tmp1_vcoDivider_div60                        8
 #define micro_Tmp1_vcoDivider_div64                        9
 #define micro_Tmp1_vcoDivider_div66                        10
 #define micro_Tmp1_vcoDivider_div68                        11
 #define micro_Tmp1_vcoDivider_div80                        12
 #define micro_Tmp1_vcoDivider_div120                       13
 #define micro_Tmp1_vcoDivider_div200                       14
 #define micro_Tmp1_vcoDivider_div240                       15
 
 /****************************************************************************
  * Enums: micro_Tmp1_refClkSelect
  */
 #define micro_Tmp1_refClkSelect_clk_25MHz                  0
 #define micro_Tmp1_refClkSelect_clk_100MHz                 1
 #define micro_Tmp1_refClkSelect_clk_125MHz                 2
 #define micro_Tmp1_refClkSelect_clk_156p25MHz              3
 #define micro_Tmp1_refClkSelect_clk_187p5MHz               4
 #define micro_Tmp1_refClkSelect_clk_161p25Mhz              5
 #define micro_Tmp1_refClkSelect_clk_50Mhz                  6
 #define micro_Tmp1_refClkSelect_clk_106p25Mhz              7
 
 /****************************************************************************
  * Enums: micro_Tmp1_aerMMDdevTypeSelect
  */
 #define micro_Tmp1_aerMMDdevTypeSelect_combo_core          0
 #define micro_Tmp1_aerMMDdevTypeSelect_PMA_PMD             1
 #define micro_Tmp1_aerMMDdevTypeSelect_PCS                 3
 #define micro_Tmp1_aerMMDdevTypeSelect_PHY                 4
 #define micro_Tmp1_aerMMDdevTypeSelect_DTE                 5
 #define micro_Tmp1_aerMMDdevTypeSelect_CL73_AN             7
 
 /****************************************************************************
  * Enums: micro_Tmp1_aerMMDportSelect
  */
 #define micro_Tmp1_aerMMDportSelect_ln0                    0
 #define micro_Tmp1_aerMMDportSelect_ln1                    1
 #define micro_Tmp1_aerMMDportSelect_ln2                    2
 #define micro_Tmp1_aerMMDportSelect_ln3                    3
 #define micro_Tmp1_aerMMDportSelect_BCST                   511
 
 /****************************************************************************
  * Enums: micro_Tmp1_firmwareModeSelect
  */
 #define micro_Tmp1_firmwareModeSelect_DEFAULT              0
 #define micro_Tmp1_firmwareModeSelect_SFP_OPT_LR           1
 #define micro_Tmp1_firmwareModeSelect_SFP_DAC              2
 #define micro_Tmp1_firmwareModeSelect_XLAUI                3
 #define micro_Tmp1_firmwareModeSelect_LONG_CH_6G           4
 
 /****************************************************************************
  * Enums: micro_Tmp1_tempIdxSelect
  */
 #define micro_Tmp1_tempIdxSelect_LTE__22p9C                15
 #define micro_Tmp1_tempIdxSelect_LTE__12p6C                14
 #define micro_Tmp1_tempIdxSelect_LTE__3p0C                 13
 #define micro_Tmp1_tempIdxSelect_LTE_6p7C                  12
 #define micro_Tmp1_tempIdxSelect_LTE_16p4C                 11
 #define micro_Tmp1_tempIdxSelect_LTE_26p6C                 10
 #define micro_Tmp1_tempIdxSelect_LTE_36p3C                 9
 #define micro_Tmp1_tempIdxSelect_LTE_46p0C                 8
 #define micro_Tmp1_tempIdxSelect_LTE_56p2C                 7
 #define micro_Tmp1_tempIdxSelect_LTE_65p9C                 6
 #define micro_Tmp1_tempIdxSelect_LTE_75p6C                 5
 #define micro_Tmp1_tempIdxSelect_LTE_85p3C                 4
 #define micro_Tmp1_tempIdxSelect_LTE_95p5C                 3
 #define micro_Tmp1_tempIdxSelect_LTE_105p2C                2
 #define micro_Tmp1_tempIdxSelect_LTE_114p9C                1
 #define micro_Tmp1_tempIdxSelect_LTE_125p1C                0
 
 /****************************************************************************
  * Enums: micro_Tmp2_operationModes
  */
 #define micro_Tmp2_operationModes_XGXS                     0
 #define micro_Tmp2_operationModes_XGXG_nCC                 1
 #define micro_Tmp2_operationModes_Indlane_OS8              4
 #define micro_Tmp2_operationModes_IndLane_OS5              5
 #define micro_Tmp2_operationModes_PCI                      7
 #define micro_Tmp2_operationModes_XGXS_nLQ                 8
 #define micro_Tmp2_operationModes_XGXS_nLQnCC              9
 #define micro_Tmp2_operationModes_PBypass                  10
 #define micro_Tmp2_operationModes_PBypass_nDSK             11
 #define micro_Tmp2_operationModes_ComboCoreMode            12
 #define micro_Tmp2_operationModes_Clocks_off               15
 
 /****************************************************************************
  * Enums: micro_Tmp2_actualSpeeds4
  */
 #define micro_Tmp2_actualSpeeds4_dr_10M                    0
 #define micro_Tmp2_actualSpeeds4_dr_100M                   1
 #define micro_Tmp2_actualSpeeds4_dr_1G                     2
 #define micro_Tmp2_actualSpeeds4_dr_2p5G                   3
 #define micro_Tmp2_actualSpeeds4_dr_5G_X4                  4
 #define micro_Tmp2_actualSpeeds4_dr_6G_X4                  5
 #define micro_Tmp2_actualSpeeds4_dr_10G_HiG                6
 #define micro_Tmp2_actualSpeeds4_dr_10G_CX4                7
 #define micro_Tmp2_actualSpeeds4_dr_12G_HiG                8
 #define micro_Tmp2_actualSpeeds4_dr_12p5G_X4               9
 #define micro_Tmp2_actualSpeeds4_dr_13G_X4                 10
 #define micro_Tmp2_actualSpeeds4_dr_15G_X4                 11
 #define micro_Tmp2_actualSpeeds4_dr_16G_X4                 12
 
 /****************************************************************************
  * Enums: micro_Tmp2_actualSpeeds5
  */
 #define micro_Tmp2_actualSpeeds5_dr_10M                    0
 #define micro_Tmp2_actualSpeeds5_dr_100M                   1
 #define micro_Tmp2_actualSpeeds5_dr_1G                     2
 #define micro_Tmp2_actualSpeeds5_dr_2p5G                   3
 #define micro_Tmp2_actualSpeeds5_dr_5G_X4                  4
 #define micro_Tmp2_actualSpeeds5_dr_6G_X4                  5
 #define micro_Tmp2_actualSpeeds5_dr_10G_HiG                6
 #define micro_Tmp2_actualSpeeds5_dr_10G_CX4                7
 #define micro_Tmp2_actualSpeeds5_dr_12G_HiG                8
 #define micro_Tmp2_actualSpeeds5_dr_12p5G_X4               9
 #define micro_Tmp2_actualSpeeds5_dr_13G_X4                 10
 #define micro_Tmp2_actualSpeeds5_dr_15G_X4                 11
 #define micro_Tmp2_actualSpeeds5_dr_16G_X4                 12
 #define micro_Tmp2_actualSpeeds5_dr_1G_KX                  13
 #define micro_Tmp2_actualSpeeds5_dr_10G_KX4                14
 #define micro_Tmp2_actualSpeeds5_dr_10G_KR                 15
 #define micro_Tmp2_actualSpeeds5_dr_5G                     16
 #define micro_Tmp2_actualSpeeds5_dr_6p4G                   17
 #define micro_Tmp2_actualSpeeds5_dr_20G_X4                 18
 #define micro_Tmp2_actualSpeeds5_dr_21G_X4                 19
 #define micro_Tmp2_actualSpeeds5_dr_25G_X4                 20
 #define micro_Tmp2_actualSpeeds5_dr_10G_HiG_DXGXS          21
 #define micro_Tmp2_actualSpeeds5_dr_10G_DXGXS              22
 #define micro_Tmp2_actualSpeeds5_dr_10p5G_HiG_DXGXS        23
 #define micro_Tmp2_actualSpeeds5_dr_10p5G_DXGXS            24
 #define micro_Tmp2_actualSpeeds5_dr_12p773G_HiG_DXGXS      25
 #define micro_Tmp2_actualSpeeds5_dr_12p773G_DXGXS          26
 #define micro_Tmp2_actualSpeeds5_dr_10G_XFI                27
 #define micro_Tmp2_actualSpeeds5_dr_40G                    28
 #define micro_Tmp2_actualSpeeds5_dr_20G_HiG_DXGXS          29
 #define micro_Tmp2_actualSpeeds5_dr_20G_DXGXS              30
 #define micro_Tmp2_actualSpeeds5_dr_10G_SFI                31
 #define micro_Tmp2_actualSpeeds5_dr_31p5G                  32
 #define micro_Tmp2_actualSpeeds5_dr_32p7G                  33
 #define micro_Tmp2_actualSpeeds5_dr_20G_SCR                34
 #define micro_Tmp2_actualSpeeds5_dr_10G_HiG_DXGXS_SCR      35
 #define micro_Tmp2_actualSpeeds5_dr_10G_DXGXS_SCR          36
 #define micro_Tmp2_actualSpeeds5_dr_12G_R2                 37
 #define micro_Tmp2_actualSpeeds5_dr_10G_X2                 38
 #define micro_Tmp2_actualSpeeds5_dr_40G_KR4                39
 #define micro_Tmp2_actualSpeeds5_dr_40G_CR4                40
 #define micro_Tmp2_actualSpeeds5_dr_100G_CR10              41
 
 /****************************************************************************
  * Enums: micro_Tmp2_actualSpeedsMisc1
  */
 #define micro_Tmp2_actualSpeedsMisc1_dr_2500BRCM_X1        16
 #define micro_Tmp2_actualSpeedsMisc1_dr_5000BRCM_X4        17
 #define micro_Tmp2_actualSpeedsMisc1_dr_6000BRCM_X4        18
 #define micro_Tmp2_actualSpeedsMisc1_dr_10GHiGig_X4        19
 #define micro_Tmp2_actualSpeedsMisc1_dr_10GBASE_CX4        20
 #define micro_Tmp2_actualSpeedsMisc1_dr_12GHiGig_X4        21
 #define micro_Tmp2_actualSpeedsMisc1_dr_12p5GHiGig_X4      22
 #define micro_Tmp2_actualSpeedsMisc1_dr_13GHiGig_X4        23
 #define micro_Tmp2_actualSpeedsMisc1_dr_15GHiGig_X4        24
 #define micro_Tmp2_actualSpeedsMisc1_dr_16GHiGig_X4        25
 #define micro_Tmp2_actualSpeedsMisc1_dr_5000BRCM_X1        26
 #define micro_Tmp2_actualSpeedsMisc1_dr_6363BRCM_X1        27
 #define micro_Tmp2_actualSpeedsMisc1_dr_20GHiGig_X4        28
 #define micro_Tmp2_actualSpeedsMisc1_dr_21GHiGig_X4        29
 #define micro_Tmp2_actualSpeedsMisc1_dr_25p45GHiGig_X4     30
 #define micro_Tmp2_actualSpeedsMisc1_dr_10G_HiG_DXGXS      31
 
 /****************************************************************************
  * Enums: micro_Tmp2_IndLaneModes
  */
 #define micro_Tmp2_IndLaneModes_SWSDR_div2                 0
 #define micro_Tmp2_IndLaneModes_SWSDR_div1                 1
 #define micro_Tmp2_IndLaneModes_DWSDR_div2                 2
 #define micro_Tmp2_IndLaneModes_DWSDR_div1                 3
 
 /****************************************************************************
  * Enums: micro_Tmp2_prbsSelect
  */
 #define micro_Tmp2_prbsSelect_prbs7                        0
 #define micro_Tmp2_prbsSelect_prbs15                       1
 #define micro_Tmp2_prbsSelect_prbs23                       2
 #define micro_Tmp2_prbsSelect_prbs31                       3
 
 /****************************************************************************
  * Enums: micro_Tmp2_vcoDivider
  */
 #define micro_Tmp2_vcoDivider_div32                        0
 #define micro_Tmp2_vcoDivider_div36                        1
 #define micro_Tmp2_vcoDivider_div40                        2
 #define micro_Tmp2_vcoDivider_div42                        3
 #define micro_Tmp2_vcoDivider_div48                        4
 #define micro_Tmp2_vcoDivider_div50                        5
 #define micro_Tmp2_vcoDivider_div52                        6
 #define micro_Tmp2_vcoDivider_div54                        7
 #define micro_Tmp2_vcoDivider_div60                        8
 #define micro_Tmp2_vcoDivider_div64                        9
 #define micro_Tmp2_vcoDivider_div66                        10
 #define micro_Tmp2_vcoDivider_div68                        11
 #define micro_Tmp2_vcoDivider_div80                        12
 #define micro_Tmp2_vcoDivider_div120                       13
 #define micro_Tmp2_vcoDivider_div200                       14
 #define micro_Tmp2_vcoDivider_div240                       15
 
 /****************************************************************************
  * Enums: micro_Tmp2_refClkSelect
  */
 #define micro_Tmp2_refClkSelect_clk_25MHz                  0
 #define micro_Tmp2_refClkSelect_clk_100MHz                 1
 #define micro_Tmp2_refClkSelect_clk_125MHz                 2
 #define micro_Tmp2_refClkSelect_clk_156p25MHz              3
 #define micro_Tmp2_refClkSelect_clk_187p5MHz               4
 #define micro_Tmp2_refClkSelect_clk_161p25Mhz              5
 #define micro_Tmp2_refClkSelect_clk_50Mhz                  6
 #define micro_Tmp2_refClkSelect_clk_106p25Mhz              7
 
 /****************************************************************************
  * Enums: micro_Tmp2_aerMMDdevTypeSelect
  */
 #define micro_Tmp2_aerMMDdevTypeSelect_combo_core          0
 #define micro_Tmp2_aerMMDdevTypeSelect_PMA_PMD             1
 #define micro_Tmp2_aerMMDdevTypeSelect_PCS                 3
 #define micro_Tmp2_aerMMDdevTypeSelect_PHY                 4
 #define micro_Tmp2_aerMMDdevTypeSelect_DTE                 5
 #define micro_Tmp2_aerMMDdevTypeSelect_CL73_AN             7
 
 /****************************************************************************
  * Enums: micro_Tmp2_aerMMDportSelect
  */
 #define micro_Tmp2_aerMMDportSelect_ln0                    0
 #define micro_Tmp2_aerMMDportSelect_ln1                    1
 #define micro_Tmp2_aerMMDportSelect_ln2                    2
 #define micro_Tmp2_aerMMDportSelect_ln3                    3
 #define micro_Tmp2_aerMMDportSelect_BCST                   511
 
 /****************************************************************************
  * Enums: micro_Tmp2_firmwareModeSelect
  */
 #define micro_Tmp2_firmwareModeSelect_DEFAULT              0
 #define micro_Tmp2_firmwareModeSelect_SFP_OPT_LR           1
 #define micro_Tmp2_firmwareModeSelect_SFP_DAC              2
 #define micro_Tmp2_firmwareModeSelect_XLAUI                3
 #define micro_Tmp2_firmwareModeSelect_LONG_CH_6G           4
 
 /****************************************************************************
  * Enums: micro_Tmp2_tempIdxSelect
  */
 #define micro_Tmp2_tempIdxSelect_LTE__22p9C                15
 #define micro_Tmp2_tempIdxSelect_LTE__12p6C                14
 #define micro_Tmp2_tempIdxSelect_LTE__3p0C                 13
 #define micro_Tmp2_tempIdxSelect_LTE_6p7C                  12
 #define micro_Tmp2_tempIdxSelect_LTE_16p4C                 11
 #define micro_Tmp2_tempIdxSelect_LTE_26p6C                 10
 #define micro_Tmp2_tempIdxSelect_LTE_36p3C                 9
 #define micro_Tmp2_tempIdxSelect_LTE_46p0C                 8
 #define micro_Tmp2_tempIdxSelect_LTE_56p2C                 7
 #define micro_Tmp2_tempIdxSelect_LTE_65p9C                 6
 #define micro_Tmp2_tempIdxSelect_LTE_75p6C                 5
 #define micro_Tmp2_tempIdxSelect_LTE_85p3C                 4
 #define micro_Tmp2_tempIdxSelect_LTE_95p5C                 3
 #define micro_Tmp2_tempIdxSelect_LTE_105p2C                2
 #define micro_Tmp2_tempIdxSelect_LTE_114p9C                1
 #define micro_Tmp2_tempIdxSelect_LTE_125p1C                0
 
 /****************************************************************************
  * Enums: xgxs_operationModes
  */
 #define xgxs_operationModes_XGXS                           0
 #define xgxs_operationModes_XGXG_nCC                       1
 #define xgxs_operationModes_Indlane_OS8                    4
 #define xgxs_operationModes_IndLane_OS5                    5
 #define xgxs_operationModes_PCI                            7
 #define xgxs_operationModes_XGXS_nLQ                       8
 #define xgxs_operationModes_XGXS_nLQnCC                    9
 #define xgxs_operationModes_PBypass                        10
 #define xgxs_operationModes_PBypass_nDSK                   11
 #define xgxs_operationModes_ComboCoreMode                  12
 #define xgxs_operationModes_Clocks_off                     15
 
 /****************************************************************************
  * Enums: xgxs_actualSpeeds4
  */
 #define xgxs_actualSpeeds4_dr_10M                          0
 #define xgxs_actualSpeeds4_dr_100M                         1
 #define xgxs_actualSpeeds4_dr_1G                           2
 #define xgxs_actualSpeeds4_dr_2p5G                         3
 #define xgxs_actualSpeeds4_dr_5G_X4                        4
 #define xgxs_actualSpeeds4_dr_6G_X4                        5
 #define xgxs_actualSpeeds4_dr_10G_HiG                      6
 #define xgxs_actualSpeeds4_dr_10G_CX4                      7
 #define xgxs_actualSpeeds4_dr_12G_HiG                      8
 #define xgxs_actualSpeeds4_dr_12p5G_X4                     9
 #define xgxs_actualSpeeds4_dr_13G_X4                       10
 #define xgxs_actualSpeeds4_dr_15G_X4                       11
 #define xgxs_actualSpeeds4_dr_16G_X4                       12
 
 /****************************************************************************
  * Enums: xgxs_actualSpeeds5
  */
 #define xgxs_actualSpeeds5_dr_10M                          0
 #define xgxs_actualSpeeds5_dr_100M                         1
 #define xgxs_actualSpeeds5_dr_1G                           2
 #define xgxs_actualSpeeds5_dr_2p5G                         3
 #define xgxs_actualSpeeds5_dr_5G_X4                        4
 #define xgxs_actualSpeeds5_dr_6G_X4                        5
 #define xgxs_actualSpeeds5_dr_10G_HiG                      6
 #define xgxs_actualSpeeds5_dr_10G_CX4                      7
 #define xgxs_actualSpeeds5_dr_12G_HiG                      8
 #define xgxs_actualSpeeds5_dr_12p5G_X4                     9
 #define xgxs_actualSpeeds5_dr_13G_X4                       10
 #define xgxs_actualSpeeds5_dr_15G_X4                       11
 #define xgxs_actualSpeeds5_dr_16G_X4                       12
 #define xgxs_actualSpeeds5_dr_1G_KX                        13
 #define xgxs_actualSpeeds5_dr_10G_KX4                      14
 #define xgxs_actualSpeeds5_dr_10G_KR                       15
 #define xgxs_actualSpeeds5_dr_5G                           16
 #define xgxs_actualSpeeds5_dr_6p4G                         17
 #define xgxs_actualSpeeds5_dr_20G_X4                       18
 #define xgxs_actualSpeeds5_dr_21G_X4                       19
 #define xgxs_actualSpeeds5_dr_25G_X4                       20
 #define xgxs_actualSpeeds5_dr_10G_HiG_DXGXS                21
 #define xgxs_actualSpeeds5_dr_10G_DXGXS                    22
 #define xgxs_actualSpeeds5_dr_10p5G_HiG_DXGXS              23
 #define xgxs_actualSpeeds5_dr_10p5G_DXGXS                  24
 #define xgxs_actualSpeeds5_dr_12p773G_HiG_DXGXS            25
 #define xgxs_actualSpeeds5_dr_12p773G_DXGXS                26
 #define xgxs_actualSpeeds5_dr_10G_XFI                      27
 #define xgxs_actualSpeeds5_dr_40G                          28
 #define xgxs_actualSpeeds5_dr_20G_HiG_DXGXS                29
 #define xgxs_actualSpeeds5_dr_20G_DXGXS                    30
 #define xgxs_actualSpeeds5_dr_10G_SFI                      31
 #define xgxs_actualSpeeds5_dr_31p5G                        32
 #define xgxs_actualSpeeds5_dr_32p7G                        33
 #define xgxs_actualSpeeds5_dr_20G_SCR                      34
 #define xgxs_actualSpeeds5_dr_10G_HiG_DXGXS_SCR            35
 #define xgxs_actualSpeeds5_dr_10G_DXGXS_SCR                36
 #define xgxs_actualSpeeds5_dr_12G_R2                       37
 #define xgxs_actualSpeeds5_dr_10G_X2                       38
 #define xgxs_actualSpeeds5_dr_40G_KR4                      39
 #define xgxs_actualSpeeds5_dr_40G_CR4                      40
 #define xgxs_actualSpeeds5_dr_100G_CR10                    41
 
 /****************************************************************************
  * Enums: xgxs_actualSpeedsMisc1
  */
 #define xgxs_actualSpeedsMisc1_dr_2500BRCM_X1              16
 #define xgxs_actualSpeedsMisc1_dr_5000BRCM_X4              17
 #define xgxs_actualSpeedsMisc1_dr_6000BRCM_X4              18
 #define xgxs_actualSpeedsMisc1_dr_10GHiGig_X4              19
 #define xgxs_actualSpeedsMisc1_dr_10GBASE_CX4              20
 #define xgxs_actualSpeedsMisc1_dr_12GHiGig_X4              21
 #define xgxs_actualSpeedsMisc1_dr_12p5GHiGig_X4            22
 #define xgxs_actualSpeedsMisc1_dr_13GHiGig_X4              23
 #define xgxs_actualSpeedsMisc1_dr_15GHiGig_X4              24
 #define xgxs_actualSpeedsMisc1_dr_16GHiGig_X4              25
 #define xgxs_actualSpeedsMisc1_dr_5000BRCM_X1              26
 #define xgxs_actualSpeedsMisc1_dr_6363BRCM_X1              27
 #define xgxs_actualSpeedsMisc1_dr_20GHiGig_X4              28
 #define xgxs_actualSpeedsMisc1_dr_21GHiGig_X4              29
 #define xgxs_actualSpeedsMisc1_dr_25p45GHiGig_X4           30
 #define xgxs_actualSpeedsMisc1_dr_10G_HiG_DXGXS            31
 
 /****************************************************************************
  * Enums: xgxs_IndLaneModes
  */
 #define xgxs_IndLaneModes_SWSDR_div2                       0
 #define xgxs_IndLaneModes_SWSDR_div1                       1
 #define xgxs_IndLaneModes_DWSDR_div2                       2
 #define xgxs_IndLaneModes_DWSDR_div1                       3
 
 /****************************************************************************
  * Enums: xgxs_prbsSelect
  */
 #define xgxs_prbsSelect_prbs7                              0
 #define xgxs_prbsSelect_prbs15                             1
 #define xgxs_prbsSelect_prbs23                             2
 #define xgxs_prbsSelect_prbs31                             3
 
 /****************************************************************************
  * Enums: xgxs_vcoDivider
  */
 #define xgxs_vcoDivider_div32                              0
 #define xgxs_vcoDivider_div36                              1
 #define xgxs_vcoDivider_div40                              2
 #define xgxs_vcoDivider_div42                              3
 #define xgxs_vcoDivider_div48                              4
 #define xgxs_vcoDivider_div50                              5
 #define xgxs_vcoDivider_div52                              6
 #define xgxs_vcoDivider_div54                              7
 #define xgxs_vcoDivider_div60                              8
 #define xgxs_vcoDivider_div64                              9
 #define xgxs_vcoDivider_div66                              10
 #define xgxs_vcoDivider_div68                              11
 #define xgxs_vcoDivider_div80                              12
 #define xgxs_vcoDivider_div120                             13
 #define xgxs_vcoDivider_div200                             14
 #define xgxs_vcoDivider_div240                             15
 
 /****************************************************************************
  * Enums: xgxs_refClkSelect
  */
 #define xgxs_refClkSelect_clk_25MHz                        0
 #define xgxs_refClkSelect_clk_100MHz                       1
 #define xgxs_refClkSelect_clk_125MHz                       2
 #define xgxs_refClkSelect_clk_156p25MHz                    3
 #define xgxs_refClkSelect_clk_187p5MHz                     4
 #define xgxs_refClkSelect_clk_161p25Mhz                    5
 #define xgxs_refClkSelect_clk_50Mhz                        6
 #define xgxs_refClkSelect_clk_106p25Mhz                    7
 
 /****************************************************************************
  * Enums: xgxs_aerMMDdevTypeSelect
  */
 #define xgxs_aerMMDdevTypeSelect_combo_core                0
 #define xgxs_aerMMDdevTypeSelect_PMA_PMD                   1
 #define xgxs_aerMMDdevTypeSelect_PCS                       3
 #define xgxs_aerMMDdevTypeSelect_PHY                       4
 #define xgxs_aerMMDdevTypeSelect_DTE                       5
 #define xgxs_aerMMDdevTypeSelect_CL73_AN                   7
 
 /****************************************************************************
  * Enums: xgxs_aerMMDportSelect
  */
 #define xgxs_aerMMDportSelect_ln0                          0
 #define xgxs_aerMMDportSelect_ln1                          1
 #define xgxs_aerMMDportSelect_ln2                          2
 #define xgxs_aerMMDportSelect_ln3                          3
 #define xgxs_aerMMDportSelect_BCST                         511
 
 /****************************************************************************
  * Enums: xgxs_firmwareModeSelect
  */
 #define xgxs_firmwareModeSelect_DEFAULT                    0
 #define xgxs_firmwareModeSelect_SFP_OPT_LR                 1
 #define xgxs_firmwareModeSelect_SFP_DAC                    2
 #define xgxs_firmwareModeSelect_XLAUI                      3
 #define xgxs_firmwareModeSelect_LONG_CH_6G                 4
 
 /****************************************************************************
  * Enums: xgxs_tempIdxSelect
  */
 #define xgxs_tempIdxSelect_LTE__22p9C                      15
 #define xgxs_tempIdxSelect_LTE__12p6C                      14
 #define xgxs_tempIdxSelect_LTE__3p0C                       13
 #define xgxs_tempIdxSelect_LTE_6p7C                        12
 #define xgxs_tempIdxSelect_LTE_16p4C                       11
 #define xgxs_tempIdxSelect_LTE_26p6C                       10
 #define xgxs_tempIdxSelect_LTE_36p3C                       9
 #define xgxs_tempIdxSelect_LTE_46p0C                       8
 #define xgxs_tempIdxSelect_LTE_56p2C                       7
 #define xgxs_tempIdxSelect_LTE_65p9C                       6
 #define xgxs_tempIdxSelect_LTE_75p6C                       5
 #define xgxs_tempIdxSelect_LTE_85p3C                       4
 #define xgxs_tempIdxSelect_LTE_95p5C                       3
 #define xgxs_tempIdxSelect_LTE_105p2C                      2
 #define xgxs_tempIdxSelect_LTE_114p9C                      1
 #define xgxs_tempIdxSelect_LTE_125p1C                      0
 
 /****************************************************************************
  * Enums: xgxs_IQP_Options
  */
 #define xgxs_IQP_Options_i50uA                             0
 #define xgxs_IQP_Options_i100uA                            1
 #define xgxs_IQP_Options_i150uA                            2
 #define xgxs_IQP_Options_i200uA                            3
 #define xgxs_IQP_Options_i250uA                            4
 #define xgxs_IQP_Options_i300uA                            5
 #define xgxs_IQP_Options_i350uA                            6
 #define xgxs_IQP_Options_i400uA                            7
 #define xgxs_IQP_Options_i450uA                            8
 #define xgxs_IQP_Options_i500uA                            9
 #define xgxs_IQP_Options_i550uA                            10
 #define xgxs_IQP_Options_i600uA                            11
 #define xgxs_IQP_Options_i650uA                            12
 #define xgxs_IQP_Options_i700uA                            13
 #define xgxs_IQP_Options_i750uA                            14
 #define xgxs_IQP_Options_i800uA                            15
 
 /****************************************************************************
  * Enums: xgxs_IDriver_Options
  */
 #define xgxs_IDriver_Options_v680mV                        0
 #define xgxs_IDriver_Options_v730mV                        1
 #define xgxs_IDriver_Options_v780mV                        2
 #define xgxs_IDriver_Options_v830mV                        3
 #define xgxs_IDriver_Options_v880mV                        4
 #define xgxs_IDriver_Options_v930mV                        5
 #define xgxs_IDriver_Options_v980mV                        6
 #define xgxs_IDriver_Options_v1010mV                       7
 #define xgxs_IDriver_Options_v1040mV                       8
 #define xgxs_IDriver_Options_v1060mV                       9
 #define xgxs_IDriver_Options_v1070mV                       10
 #define xgxs_IDriver_Options_v1080mV                       11
 #define xgxs_IDriver_Options_v1085mV                       12
 #define xgxs_IDriver_Options_v1090mV                       13
 #define xgxs_IDriver_Options_v1095mV                       14
 #define xgxs_IDriver_Options_v1100mV                       15
 
 /****************************************************************************
  * Enums: xgxsBlk0_operationModes
  */
 #define xgxsBlk0_operationModes_XGXS                       0
 #define xgxsBlk0_operationModes_XGXG_nCC                   1
 #define xgxsBlk0_operationModes_Indlane_OS8                4
 #define xgxsBlk0_operationModes_IndLane_OS5                5
 #define xgxsBlk0_operationModes_PCI                        7
 #define xgxsBlk0_operationModes_XGXS_nLQ                   8
 #define xgxsBlk0_operationModes_XGXS_nLQnCC                9
 #define xgxsBlk0_operationModes_PBypass                    10
 #define xgxsBlk0_operationModes_PBypass_nDSK               11
 #define xgxsBlk0_operationModes_ComboCoreMode              12
 #define xgxsBlk0_operationModes_Clocks_off                 15
 
 /****************************************************************************
  * Enums: xgxsBlk0_actualSpeeds4
  */
 #define xgxsBlk0_actualSpeeds4_dr_10M                      0
 #define xgxsBlk0_actualSpeeds4_dr_100M                     1
 #define xgxsBlk0_actualSpeeds4_dr_1G                       2
 #define xgxsBlk0_actualSpeeds4_dr_2p5G                     3
 #define xgxsBlk0_actualSpeeds4_dr_5G_X4                    4
 #define xgxsBlk0_actualSpeeds4_dr_6G_X4                    5
 #define xgxsBlk0_actualSpeeds4_dr_10G_HiG                  6
 #define xgxsBlk0_actualSpeeds4_dr_10G_CX4                  7
 #define xgxsBlk0_actualSpeeds4_dr_12G_HiG                  8
 #define xgxsBlk0_actualSpeeds4_dr_12p5G_X4                 9
 #define xgxsBlk0_actualSpeeds4_dr_13G_X4                   10
 #define xgxsBlk0_actualSpeeds4_dr_15G_X4                   11
 #define xgxsBlk0_actualSpeeds4_dr_16G_X4                   12
 
 /****************************************************************************
  * Enums: xgxsBlk0_actualSpeeds5
  */
 #define xgxsBlk0_actualSpeeds5_dr_10M                      0
 #define xgxsBlk0_actualSpeeds5_dr_100M                     1
 #define xgxsBlk0_actualSpeeds5_dr_1G                       2
 #define xgxsBlk0_actualSpeeds5_dr_2p5G                     3
 #define xgxsBlk0_actualSpeeds5_dr_5G_X4                    4
 #define xgxsBlk0_actualSpeeds5_dr_6G_X4                    5
 #define xgxsBlk0_actualSpeeds5_dr_10G_HiG                  6
 #define xgxsBlk0_actualSpeeds5_dr_10G_CX4                  7
 #define xgxsBlk0_actualSpeeds5_dr_12G_HiG                  8
 #define xgxsBlk0_actualSpeeds5_dr_12p5G_X4                 9
 #define xgxsBlk0_actualSpeeds5_dr_13G_X4                   10
 #define xgxsBlk0_actualSpeeds5_dr_15G_X4                   11
 #define xgxsBlk0_actualSpeeds5_dr_16G_X4                   12
 #define xgxsBlk0_actualSpeeds5_dr_1G_KX                    13
 #define xgxsBlk0_actualSpeeds5_dr_10G_KX4                  14
 #define xgxsBlk0_actualSpeeds5_dr_10G_KR                   15
 #define xgxsBlk0_actualSpeeds5_dr_5G                       16
 #define xgxsBlk0_actualSpeeds5_dr_6p4G                     17
 #define xgxsBlk0_actualSpeeds5_dr_20G_X4                   18
 #define xgxsBlk0_actualSpeeds5_dr_21G_X4                   19
 #define xgxsBlk0_actualSpeeds5_dr_25G_X4                   20
 #define xgxsBlk0_actualSpeeds5_dr_10G_HiG_DXGXS            21
 #define xgxsBlk0_actualSpeeds5_dr_10G_DXGXS                22
 #define xgxsBlk0_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
 #define xgxsBlk0_actualSpeeds5_dr_10p5G_DXGXS              24
 #define xgxsBlk0_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
 #define xgxsBlk0_actualSpeeds5_dr_12p773G_DXGXS            26
 #define xgxsBlk0_actualSpeeds5_dr_10G_XFI                  27
 #define xgxsBlk0_actualSpeeds5_dr_40G                      28
 #define xgxsBlk0_actualSpeeds5_dr_20G_HiG_DXGXS            29
 #define xgxsBlk0_actualSpeeds5_dr_20G_DXGXS                30
 #define xgxsBlk0_actualSpeeds5_dr_10G_SFI                  31
 #define xgxsBlk0_actualSpeeds5_dr_31p5G                    32
 #define xgxsBlk0_actualSpeeds5_dr_32p7G                    33
 #define xgxsBlk0_actualSpeeds5_dr_20G_SCR                  34
 #define xgxsBlk0_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
 #define xgxsBlk0_actualSpeeds5_dr_10G_DXGXS_SCR            36
 #define xgxsBlk0_actualSpeeds5_dr_12G_R2                   37
 #define xgxsBlk0_actualSpeeds5_dr_10G_X2                   38
 #define xgxsBlk0_actualSpeeds5_dr_40G_KR4                  39
 #define xgxsBlk0_actualSpeeds5_dr_40G_CR4                  40
 #define xgxsBlk0_actualSpeeds5_dr_100G_CR10                41
 
 /****************************************************************************
  * Enums: xgxsBlk0_actualSpeedsMisc1
  */
 #define xgxsBlk0_actualSpeedsMisc1_dr_2500BRCM_X1          16
 #define xgxsBlk0_actualSpeedsMisc1_dr_5000BRCM_X4          17
 #define xgxsBlk0_actualSpeedsMisc1_dr_6000BRCM_X4          18
 #define xgxsBlk0_actualSpeedsMisc1_dr_10GHiGig_X4          19
 #define xgxsBlk0_actualSpeedsMisc1_dr_10GBASE_CX4          20
 #define xgxsBlk0_actualSpeedsMisc1_dr_12GHiGig_X4          21
 #define xgxsBlk0_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
 #define xgxsBlk0_actualSpeedsMisc1_dr_13GHiGig_X4          23
 #define xgxsBlk0_actualSpeedsMisc1_dr_15GHiGig_X4          24
 #define xgxsBlk0_actualSpeedsMisc1_dr_16GHiGig_X4          25
 #define xgxsBlk0_actualSpeedsMisc1_dr_5000BRCM_X1          26
 #define xgxsBlk0_actualSpeedsMisc1_dr_6363BRCM_X1          27
 #define xgxsBlk0_actualSpeedsMisc1_dr_20GHiGig_X4          28
 #define xgxsBlk0_actualSpeedsMisc1_dr_21GHiGig_X4          29
 #define xgxsBlk0_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
 #define xgxsBlk0_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31
 
 /****************************************************************************
  * Enums: xgxsBlk0_IndLaneModes
  */
 #define xgxsBlk0_IndLaneModes_SWSDR_div2                   0
 #define xgxsBlk0_IndLaneModes_SWSDR_div1                   1
 #define xgxsBlk0_IndLaneModes_DWSDR_div2                   2
 #define xgxsBlk0_IndLaneModes_DWSDR_div1                   3
 
 /****************************************************************************
  * Enums: xgxsBlk0_prbsSelect
  */
 #define xgxsBlk0_prbsSelect_prbs7                          0
 #define xgxsBlk0_prbsSelect_prbs15                         1
 #define xgxsBlk0_prbsSelect_prbs23                         2
 #define xgxsBlk0_prbsSelect_prbs31                         3
 
 /****************************************************************************
  * Enums: xgxsBlk0_vcoDivider
  */
 #define xgxsBlk0_vcoDivider_div32                          0
 #define xgxsBlk0_vcoDivider_div36                          1
 #define xgxsBlk0_vcoDivider_div40                          2
 #define xgxsBlk0_vcoDivider_div42                          3
 #define xgxsBlk0_vcoDivider_div48                          4
 #define xgxsBlk0_vcoDivider_div50                          5
 #define xgxsBlk0_vcoDivider_div52                          6
 #define xgxsBlk0_vcoDivider_div54                          7
 #define xgxsBlk0_vcoDivider_div60                          8
 #define xgxsBlk0_vcoDivider_div64                          9
 #define xgxsBlk0_vcoDivider_div66                          10
 #define xgxsBlk0_vcoDivider_div68                          11
 #define xgxsBlk0_vcoDivider_div80                          12
 #define xgxsBlk0_vcoDivider_div120                         13
 #define xgxsBlk0_vcoDivider_div200                         14
 #define xgxsBlk0_vcoDivider_div240                         15
 
 /****************************************************************************
  * Enums: xgxsBlk0_refClkSelect
  */
 #define xgxsBlk0_refClkSelect_clk_25MHz                    0
 #define xgxsBlk0_refClkSelect_clk_100MHz                   1
 #define xgxsBlk0_refClkSelect_clk_125MHz                   2
 #define xgxsBlk0_refClkSelect_clk_156p25MHz                3
 #define xgxsBlk0_refClkSelect_clk_187p5MHz                 4
 #define xgxsBlk0_refClkSelect_clk_161p25Mhz                5
 #define xgxsBlk0_refClkSelect_clk_50Mhz                    6
 #define xgxsBlk0_refClkSelect_clk_106p25Mhz                7
 
 /****************************************************************************
  * Enums: xgxsBlk0_aerMMDdevTypeSelect
  */
 #define xgxsBlk0_aerMMDdevTypeSelect_combo_core            0
 #define xgxsBlk0_aerMMDdevTypeSelect_PMA_PMD               1
 #define xgxsBlk0_aerMMDdevTypeSelect_PCS                   3
 #define xgxsBlk0_aerMMDdevTypeSelect_PHY                   4
 #define xgxsBlk0_aerMMDdevTypeSelect_DTE                   5
 #define xgxsBlk0_aerMMDdevTypeSelect_CL73_AN               7
 
 /****************************************************************************
  * Enums: xgxsBlk0_aerMMDportSelect
  */
 #define xgxsBlk0_aerMMDportSelect_ln0                      0
 #define xgxsBlk0_aerMMDportSelect_ln1                      1
 #define xgxsBlk0_aerMMDportSelect_ln2                      2
 #define xgxsBlk0_aerMMDportSelect_ln3                      3
 #define xgxsBlk0_aerMMDportSelect_BCST                     511
 
 /****************************************************************************
  * Enums: xgxsBlk0_firmwareModeSelect
  */
 #define xgxsBlk0_firmwareModeSelect_DEFAULT                0
 #define xgxsBlk0_firmwareModeSelect_SFP_OPT_LR             1
 #define xgxsBlk0_firmwareModeSelect_SFP_DAC                2
 #define xgxsBlk0_firmwareModeSelect_XLAUI                  3
 #define xgxsBlk0_firmwareModeSelect_LONG_CH_6G             4
 
 /****************************************************************************
  * Enums: xgxsBlk0_tempIdxSelect
  */
 #define xgxsBlk0_tempIdxSelect_LTE__22p9C                  15
 #define xgxsBlk0_tempIdxSelect_LTE__12p6C                  14
 #define xgxsBlk0_tempIdxSelect_LTE__3p0C                   13
 #define xgxsBlk0_tempIdxSelect_LTE_6p7C                    12
 #define xgxsBlk0_tempIdxSelect_LTE_16p4C                   11
 #define xgxsBlk0_tempIdxSelect_LTE_26p6C                   10
 #define xgxsBlk0_tempIdxSelect_LTE_36p3C                   9
 #define xgxsBlk0_tempIdxSelect_LTE_46p0C                   8
 #define xgxsBlk0_tempIdxSelect_LTE_56p2C                   7
 #define xgxsBlk0_tempIdxSelect_LTE_65p9C                   6
 #define xgxsBlk0_tempIdxSelect_LTE_75p6C                   5
 #define xgxsBlk0_tempIdxSelect_LTE_85p3C                   4
 #define xgxsBlk0_tempIdxSelect_LTE_95p5C                   3
 #define xgxsBlk0_tempIdxSelect_LTE_105p2C                  2
 #define xgxsBlk0_tempIdxSelect_LTE_114p9C                  1
 #define xgxsBlk0_tempIdxSelect_LTE_125p1C                  0
 
 /****************************************************************************
  * Enums: xgxsBlk1_operationModes
  */
 #define xgxsBlk1_operationModes_XGXS                       0
 #define xgxsBlk1_operationModes_XGXG_nCC                   1
 #define xgxsBlk1_operationModes_Indlane_OS8                4
 #define xgxsBlk1_operationModes_IndLane_OS5                5
 #define xgxsBlk1_operationModes_PCI                        7
 #define xgxsBlk1_operationModes_XGXS_nLQ                   8
 #define xgxsBlk1_operationModes_XGXS_nLQnCC                9
 #define xgxsBlk1_operationModes_PBypass                    10
 #define xgxsBlk1_operationModes_PBypass_nDSK               11
 #define xgxsBlk1_operationModes_ComboCoreMode              12
 #define xgxsBlk1_operationModes_Clocks_off                 15
 
 /****************************************************************************
  * Enums: xgxsBlk1_actualSpeeds4
  */
 #define xgxsBlk1_actualSpeeds4_dr_10M                      0
 #define xgxsBlk1_actualSpeeds4_dr_100M                     1
 #define xgxsBlk1_actualSpeeds4_dr_1G                       2
 #define xgxsBlk1_actualSpeeds4_dr_2p5G                     3
 #define xgxsBlk1_actualSpeeds4_dr_5G_X4                    4
 #define xgxsBlk1_actualSpeeds4_dr_6G_X4                    5
 #define xgxsBlk1_actualSpeeds4_dr_10G_HiG                  6
 #define xgxsBlk1_actualSpeeds4_dr_10G_CX4                  7
 #define xgxsBlk1_actualSpeeds4_dr_12G_HiG                  8
 #define xgxsBlk1_actualSpeeds4_dr_12p5G_X4                 9
 #define xgxsBlk1_actualSpeeds4_dr_13G_X4                   10
 #define xgxsBlk1_actualSpeeds4_dr_15G_X4                   11
 #define xgxsBlk1_actualSpeeds4_dr_16G_X4                   12
 
 /****************************************************************************
  * Enums: xgxsBlk1_actualSpeeds5
  */
 #define xgxsBlk1_actualSpeeds5_dr_10M                      0
 #define xgxsBlk1_actualSpeeds5_dr_100M                     1
 #define xgxsBlk1_actualSpeeds5_dr_1G                       2
 #define xgxsBlk1_actualSpeeds5_dr_2p5G                     3
 #define xgxsBlk1_actualSpeeds5_dr_5G_X4                    4
 #define xgxsBlk1_actualSpeeds5_dr_6G_X4                    5
 #define xgxsBlk1_actualSpeeds5_dr_10G_HiG                  6
 #define xgxsBlk1_actualSpeeds5_dr_10G_CX4                  7
 #define xgxsBlk1_actualSpeeds5_dr_12G_HiG                  8
 #define xgxsBlk1_actualSpeeds5_dr_12p5G_X4                 9
 #define xgxsBlk1_actualSpeeds5_dr_13G_X4                   10
 #define xgxsBlk1_actualSpeeds5_dr_15G_X4                   11
 #define xgxsBlk1_actualSpeeds5_dr_16G_X4                   12
 #define xgxsBlk1_actualSpeeds5_dr_1G_KX                    13
 #define xgxsBlk1_actualSpeeds5_dr_10G_KX4                  14
 #define xgxsBlk1_actualSpeeds5_dr_10G_KR                   15
 #define xgxsBlk1_actualSpeeds5_dr_5G                       16
 #define xgxsBlk1_actualSpeeds5_dr_6p4G                     17
 #define xgxsBlk1_actualSpeeds5_dr_20G_X4                   18
 #define xgxsBlk1_actualSpeeds5_dr_21G_X4                   19
 #define xgxsBlk1_actualSpeeds5_dr_25G_X4                   20
 #define xgxsBlk1_actualSpeeds5_dr_10G_HiG_DXGXS            21
 #define xgxsBlk1_actualSpeeds5_dr_10G_DXGXS                22
 #define xgxsBlk1_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
 #define xgxsBlk1_actualSpeeds5_dr_10p5G_DXGXS              24
 #define xgxsBlk1_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
 #define xgxsBlk1_actualSpeeds5_dr_12p773G_DXGXS            26
 #define xgxsBlk1_actualSpeeds5_dr_10G_XFI                  27
 #define xgxsBlk1_actualSpeeds5_dr_40G                      28
 #define xgxsBlk1_actualSpeeds5_dr_20G_HiG_DXGXS            29
 #define xgxsBlk1_actualSpeeds5_dr_20G_DXGXS                30
 #define xgxsBlk1_actualSpeeds5_dr_10G_SFI                  31
 #define xgxsBlk1_actualSpeeds5_dr_31p5G                    32
 #define xgxsBlk1_actualSpeeds5_dr_32p7G                    33
 #define xgxsBlk1_actualSpeeds5_dr_20G_SCR                  34
 #define xgxsBlk1_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
 #define xgxsBlk1_actualSpeeds5_dr_10G_DXGXS_SCR            36
 #define xgxsBlk1_actualSpeeds5_dr_12G_R2                   37
 #define xgxsBlk1_actualSpeeds5_dr_10G_X2                   38
 #define xgxsBlk1_actualSpeeds5_dr_40G_KR4                  39
 #define xgxsBlk1_actualSpeeds5_dr_40G_CR4                  40
 #define xgxsBlk1_actualSpeeds5_dr_100G_CR10                41
 
 /****************************************************************************
  * Enums: xgxsBlk1_actualSpeedsMisc1
  */
 #define xgxsBlk1_actualSpeedsMisc1_dr_2500BRCM_X1          16
 #define xgxsBlk1_actualSpeedsMisc1_dr_5000BRCM_X4          17
 #define xgxsBlk1_actualSpeedsMisc1_dr_6000BRCM_X4          18
 #define xgxsBlk1_actualSpeedsMisc1_dr_10GHiGig_X4          19
 #define xgxsBlk1_actualSpeedsMisc1_dr_10GBASE_CX4          20
 #define xgxsBlk1_actualSpeedsMisc1_dr_12GHiGig_X4          21
 #define xgxsBlk1_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
 #define xgxsBlk1_actualSpeedsMisc1_dr_13GHiGig_X4          23
 #define xgxsBlk1_actualSpeedsMisc1_dr_15GHiGig_X4          24
 #define xgxsBlk1_actualSpeedsMisc1_dr_16GHiGig_X4          25
 #define xgxsBlk1_actualSpeedsMisc1_dr_5000BRCM_X1          26
 #define xgxsBlk1_actualSpeedsMisc1_dr_6363BRCM_X1          27
 #define xgxsBlk1_actualSpeedsMisc1_dr_20GHiGig_X4          28
 #define xgxsBlk1_actualSpeedsMisc1_dr_21GHiGig_X4          29
 #define xgxsBlk1_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
 #define xgxsBlk1_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31
 
 /****************************************************************************
  * Enums: xgxsBlk1_IndLaneModes
  */
 #define xgxsBlk1_IndLaneModes_SWSDR_div2                   0
 #define xgxsBlk1_IndLaneModes_SWSDR_div1                   1
 #define xgxsBlk1_IndLaneModes_DWSDR_div2                   2
 #define xgxsBlk1_IndLaneModes_DWSDR_div1                   3
 
 /****************************************************************************
  * Enums: xgxsBlk1_prbsSelect
  */
 #define xgxsBlk1_prbsSelect_prbs7                          0
 #define xgxsBlk1_prbsSelect_prbs15                         1
 #define xgxsBlk1_prbsSelect_prbs23                         2
 #define xgxsBlk1_prbsSelect_prbs31                         3
 
 /****************************************************************************
  * Enums: xgxsBlk1_vcoDivider
  */
 #define xgxsBlk1_vcoDivider_div32                          0
 #define xgxsBlk1_vcoDivider_div36                          1
 #define xgxsBlk1_vcoDivider_div40                          2
 #define xgxsBlk1_vcoDivider_div42                          3
 #define xgxsBlk1_vcoDivider_div48                          4
 #define xgxsBlk1_vcoDivider_div50                          5
 #define xgxsBlk1_vcoDivider_div52                          6
 #define xgxsBlk1_vcoDivider_div54                          7
 #define xgxsBlk1_vcoDivider_div60                          8
 #define xgxsBlk1_vcoDivider_div64                          9
 #define xgxsBlk1_vcoDivider_div66                          10
 #define xgxsBlk1_vcoDivider_div68                          11
 #define xgxsBlk1_vcoDivider_div80                          12
 #define xgxsBlk1_vcoDivider_div120                         13
 #define xgxsBlk1_vcoDivider_div200                         14
 #define xgxsBlk1_vcoDivider_div240                         15
 
 /****************************************************************************
  * Enums: xgxsBlk1_refClkSelect
  */
 #define xgxsBlk1_refClkSelect_clk_25MHz                    0
 #define xgxsBlk1_refClkSelect_clk_100MHz                   1
 #define xgxsBlk1_refClkSelect_clk_125MHz                   2
 #define xgxsBlk1_refClkSelect_clk_156p25MHz                3
 #define xgxsBlk1_refClkSelect_clk_187p5MHz                 4
 #define xgxsBlk1_refClkSelect_clk_161p25Mhz                5
 #define xgxsBlk1_refClkSelect_clk_50Mhz                    6
 #define xgxsBlk1_refClkSelect_clk_106p25Mhz                7
 
 /****************************************************************************
  * Enums: xgxsBlk1_aerMMDdevTypeSelect
  */
 #define xgxsBlk1_aerMMDdevTypeSelect_combo_core            0
 #define xgxsBlk1_aerMMDdevTypeSelect_PMA_PMD               1
 #define xgxsBlk1_aerMMDdevTypeSelect_PCS                   3
 #define xgxsBlk1_aerMMDdevTypeSelect_PHY                   4
 #define xgxsBlk1_aerMMDdevTypeSelect_DTE                   5
 #define xgxsBlk1_aerMMDdevTypeSelect_CL73_AN               7
 
 /****************************************************************************
  * Enums: xgxsBlk1_aerMMDportSelect
  */
 #define xgxsBlk1_aerMMDportSelect_ln0                      0
 #define xgxsBlk1_aerMMDportSelect_ln1                      1
 #define xgxsBlk1_aerMMDportSelect_ln2                      2
 #define xgxsBlk1_aerMMDportSelect_ln3                      3
 #define xgxsBlk1_aerMMDportSelect_BCST                     511
 
 /****************************************************************************
  * Enums: xgxsBlk1_firmwareModeSelect
  */
 #define xgxsBlk1_firmwareModeSelect_DEFAULT                0
 #define xgxsBlk1_firmwareModeSelect_SFP_OPT_LR             1
 #define xgxsBlk1_firmwareModeSelect_SFP_DAC                2
 #define xgxsBlk1_firmwareModeSelect_XLAUI                  3
 #define xgxsBlk1_firmwareModeSelect_LONG_CH_6G             4
 
 /****************************************************************************
  * Enums: xgxsBlk1_tempIdxSelect
  */
 #define xgxsBlk1_tempIdxSelect_LTE__22p9C                  15
 #define xgxsBlk1_tempIdxSelect_LTE__12p6C                  14
 #define xgxsBlk1_tempIdxSelect_LTE__3p0C                   13
 #define xgxsBlk1_tempIdxSelect_LTE_6p7C                    12
 #define xgxsBlk1_tempIdxSelect_LTE_16p4C                   11
 #define xgxsBlk1_tempIdxSelect_LTE_26p6C                   10
 #define xgxsBlk1_tempIdxSelect_LTE_36p3C                   9
 #define xgxsBlk1_tempIdxSelect_LTE_46p0C                   8
 #define xgxsBlk1_tempIdxSelect_LTE_56p2C                   7
 #define xgxsBlk1_tempIdxSelect_LTE_65p9C                   6
 #define xgxsBlk1_tempIdxSelect_LTE_75p6C                   5
 #define xgxsBlk1_tempIdxSelect_LTE_85p3C                   4
 #define xgxsBlk1_tempIdxSelect_LTE_95p5C                   3
 #define xgxsBlk1_tempIdxSelect_LTE_105p2C                  2
 #define xgxsBlk1_tempIdxSelect_LTE_114p9C                  1
 #define xgxsBlk1_tempIdxSelect_LTE_125p1C                  0
 
 /****************************************************************************
  * Enums: xgxsBlk2_operationModes
  */
 #define xgxsBlk2_operationModes_XGXS                       0
 #define xgxsBlk2_operationModes_XGXG_nCC                   1
 #define xgxsBlk2_operationModes_Indlane_OS8                4
 #define xgxsBlk2_operationModes_IndLane_OS5                5
 #define xgxsBlk2_operationModes_PCI                        7
 #define xgxsBlk2_operationModes_XGXS_nLQ                   8
 #define xgxsBlk2_operationModes_XGXS_nLQnCC                9
 #define xgxsBlk2_operationModes_PBypass                    10
 #define xgxsBlk2_operationModes_PBypass_nDSK               11
 #define xgxsBlk2_operationModes_ComboCoreMode              12
 #define xgxsBlk2_operationModes_Clocks_off                 15
 
 /****************************************************************************
  * Enums: xgxsBlk2_actualSpeeds4
  */
 #define xgxsBlk2_actualSpeeds4_dr_10M                      0
 #define xgxsBlk2_actualSpeeds4_dr_100M                     1
 #define xgxsBlk2_actualSpeeds4_dr_1G                       2
 #define xgxsBlk2_actualSpeeds4_dr_2p5G                     3
 #define xgxsBlk2_actualSpeeds4_dr_5G_X4                    4
 #define xgxsBlk2_actualSpeeds4_dr_6G_X4                    5
 #define xgxsBlk2_actualSpeeds4_dr_10G_HiG                  6
 #define xgxsBlk2_actualSpeeds4_dr_10G_CX4                  7
 #define xgxsBlk2_actualSpeeds4_dr_12G_HiG                  8
 #define xgxsBlk2_actualSpeeds4_dr_12p5G_X4                 9
 #define xgxsBlk2_actualSpeeds4_dr_13G_X4                   10
 #define xgxsBlk2_actualSpeeds4_dr_15G_X4                   11
 #define xgxsBlk2_actualSpeeds4_dr_16G_X4                   12
 
 /****************************************************************************
  * Enums: xgxsBlk2_actualSpeeds5
  */
 #define xgxsBlk2_actualSpeeds5_dr_10M                      0
 #define xgxsBlk2_actualSpeeds5_dr_100M                     1
 #define xgxsBlk2_actualSpeeds5_dr_1G                       2
 #define xgxsBlk2_actualSpeeds5_dr_2p5G                     3
 #define xgxsBlk2_actualSpeeds5_dr_5G_X4                    4
 #define xgxsBlk2_actualSpeeds5_dr_6G_X4                    5
 #define xgxsBlk2_actualSpeeds5_dr_10G_HiG                  6
 #define xgxsBlk2_actualSpeeds5_dr_10G_CX4                  7
 #define xgxsBlk2_actualSpeeds5_dr_12G_HiG                  8
 #define xgxsBlk2_actualSpeeds5_dr_12p5G_X4                 9
 #define xgxsBlk2_actualSpeeds5_dr_13G_X4                   10
 #define xgxsBlk2_actualSpeeds5_dr_15G_X4                   11
 #define xgxsBlk2_actualSpeeds5_dr_16G_X4                   12
 #define xgxsBlk2_actualSpeeds5_dr_1G_KX                    13
 #define xgxsBlk2_actualSpeeds5_dr_10G_KX4                  14
 #define xgxsBlk2_actualSpeeds5_dr_10G_KR                   15
 #define xgxsBlk2_actualSpeeds5_dr_5G                       16
 #define xgxsBlk2_actualSpeeds5_dr_6p4G                     17
 #define xgxsBlk2_actualSpeeds5_dr_20G_X4                   18
 #define xgxsBlk2_actualSpeeds5_dr_21G_X4                   19
 #define xgxsBlk2_actualSpeeds5_dr_25G_X4                   20
 #define xgxsBlk2_actualSpeeds5_dr_10G_HiG_DXGXS            21
 #define xgxsBlk2_actualSpeeds5_dr_10G_DXGXS                22
 #define xgxsBlk2_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
 #define xgxsBlk2_actualSpeeds5_dr_10p5G_DXGXS              24
 #define xgxsBlk2_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
 #define xgxsBlk2_actualSpeeds5_dr_12p773G_DXGXS            26
 #define xgxsBlk2_actualSpeeds5_dr_10G_XFI                  27
 #define xgxsBlk2_actualSpeeds5_dr_40G                      28
 #define xgxsBlk2_actualSpeeds5_dr_20G_HiG_DXGXS            29
 #define xgxsBlk2_actualSpeeds5_dr_20G_DXGXS                30
 #define xgxsBlk2_actualSpeeds5_dr_10G_SFI                  31
 #define xgxsBlk2_actualSpeeds5_dr_31p5G                    32
 #define xgxsBlk2_actualSpeeds5_dr_32p7G                    33
 #define xgxsBlk2_actualSpeeds5_dr_20G_SCR                  34
 #define xgxsBlk2_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
 #define xgxsBlk2_actualSpeeds5_dr_10G_DXGXS_SCR            36
 #define xgxsBlk2_actualSpeeds5_dr_12G_R2                   37
 #define xgxsBlk2_actualSpeeds5_dr_10G_X2                   38
 #define xgxsBlk2_actualSpeeds5_dr_40G_KR4                  39
 #define xgxsBlk2_actualSpeeds5_dr_40G_CR4                  40
 #define xgxsBlk2_actualSpeeds5_dr_100G_CR10                41
 
 /****************************************************************************
  * Enums: xgxsBlk2_actualSpeedsMisc1
  */
 #define xgxsBlk2_actualSpeedsMisc1_dr_2500BRCM_X1          16
 #define xgxsBlk2_actualSpeedsMisc1_dr_5000BRCM_X4          17
 #define xgxsBlk2_actualSpeedsMisc1_dr_6000BRCM_X4          18
 #define xgxsBlk2_actualSpeedsMisc1_dr_10GHiGig_X4          19
 #define xgxsBlk2_actualSpeedsMisc1_dr_10GBASE_CX4          20
 #define xgxsBlk2_actualSpeedsMisc1_dr_12GHiGig_X4          21
 #define xgxsBlk2_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
 #define xgxsBlk2_actualSpeedsMisc1_dr_13GHiGig_X4          23
 #define xgxsBlk2_actualSpeedsMisc1_dr_15GHiGig_X4          24
 #define xgxsBlk2_actualSpeedsMisc1_dr_16GHiGig_X4          25
 #define xgxsBlk2_actualSpeedsMisc1_dr_5000BRCM_X1          26
 #define xgxsBlk2_actualSpeedsMisc1_dr_6363BRCM_X1          27
 #define xgxsBlk2_actualSpeedsMisc1_dr_20GHiGig_X4          28
 #define xgxsBlk2_actualSpeedsMisc1_dr_21GHiGig_X4          29
 #define xgxsBlk2_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
 #define xgxsBlk2_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31
 
 /****************************************************************************
  * Enums: xgxsBlk2_IndLaneModes
  */
 #define xgxsBlk2_IndLaneModes_SWSDR_div2                   0
 #define xgxsBlk2_IndLaneModes_SWSDR_div1                   1
 #define xgxsBlk2_IndLaneModes_DWSDR_div2                   2
 #define xgxsBlk2_IndLaneModes_DWSDR_div1                   3
 
 /****************************************************************************
  * Enums: xgxsBlk2_prbsSelect
  */
 #define xgxsBlk2_prbsSelect_prbs7                          0
 #define xgxsBlk2_prbsSelect_prbs15                         1
 #define xgxsBlk2_prbsSelect_prbs23                         2
 #define xgxsBlk2_prbsSelect_prbs31                         3
 
 /****************************************************************************
  * Enums: xgxsBlk2_vcoDivider
  */
 #define xgxsBlk2_vcoDivider_div32                          0
 #define xgxsBlk2_vcoDivider_div36                          1
 #define xgxsBlk2_vcoDivider_div40                          2
 #define xgxsBlk2_vcoDivider_div42                          3
 #define xgxsBlk2_vcoDivider_div48                          4
 #define xgxsBlk2_vcoDivider_div50                          5
 #define xgxsBlk2_vcoDivider_div52                          6
 #define xgxsBlk2_vcoDivider_div54                          7
 #define xgxsBlk2_vcoDivider_div60                          8
 #define xgxsBlk2_vcoDivider_div64                          9
 #define xgxsBlk2_vcoDivider_div66                          10
 #define xgxsBlk2_vcoDivider_div68                          11
 #define xgxsBlk2_vcoDivider_div80                          12
 #define xgxsBlk2_vcoDivider_div120                         13
 #define xgxsBlk2_vcoDivider_div200                         14
 #define xgxsBlk2_vcoDivider_div240                         15
 
 /****************************************************************************
  * Enums: xgxsBlk2_refClkSelect
  */
 #define xgxsBlk2_refClkSelect_clk_25MHz                    0
 #define xgxsBlk2_refClkSelect_clk_100MHz                   1
 #define xgxsBlk2_refClkSelect_clk_125MHz                   2
 #define xgxsBlk2_refClkSelect_clk_156p25MHz                3
 #define xgxsBlk2_refClkSelect_clk_187p5MHz                 4
 #define xgxsBlk2_refClkSelect_clk_161p25Mhz                5
 #define xgxsBlk2_refClkSelect_clk_50Mhz                    6
 #define xgxsBlk2_refClkSelect_clk_106p25Mhz                7
 
 /****************************************************************************
  * Enums: xgxsBlk2_aerMMDdevTypeSelect
  */
 #define xgxsBlk2_aerMMDdevTypeSelect_combo_core            0
 #define xgxsBlk2_aerMMDdevTypeSelect_PMA_PMD               1
 #define xgxsBlk2_aerMMDdevTypeSelect_PCS                   3
 #define xgxsBlk2_aerMMDdevTypeSelect_PHY                   4
 #define xgxsBlk2_aerMMDdevTypeSelect_DTE                   5
 #define xgxsBlk2_aerMMDdevTypeSelect_CL73_AN               7
 
 /****************************************************************************
  * Enums: xgxsBlk2_aerMMDportSelect
  */
 #define xgxsBlk2_aerMMDportSelect_ln0                      0
 #define xgxsBlk2_aerMMDportSelect_ln1                      1
 #define xgxsBlk2_aerMMDportSelect_ln2                      2
 #define xgxsBlk2_aerMMDportSelect_ln3                      3
 #define xgxsBlk2_aerMMDportSelect_BCST                     511
 
 /****************************************************************************
  * Enums: xgxsBlk2_firmwareModeSelect
  */
 #define xgxsBlk2_firmwareModeSelect_DEFAULT                0
 #define xgxsBlk2_firmwareModeSelect_SFP_OPT_LR             1
 #define xgxsBlk2_firmwareModeSelect_SFP_DAC                2
 #define xgxsBlk2_firmwareModeSelect_XLAUI                  3
 #define xgxsBlk2_firmwareModeSelect_LONG_CH_6G             4
 
 /****************************************************************************
  * Enums: xgxsBlk2_tempIdxSelect
  */
 #define xgxsBlk2_tempIdxSelect_LTE__22p9C                  15
 #define xgxsBlk2_tempIdxSelect_LTE__12p6C                  14
 #define xgxsBlk2_tempIdxSelect_LTE__3p0C                   13
 #define xgxsBlk2_tempIdxSelect_LTE_6p7C                    12
 #define xgxsBlk2_tempIdxSelect_LTE_16p4C                   11
 #define xgxsBlk2_tempIdxSelect_LTE_26p6C                   10
 #define xgxsBlk2_tempIdxSelect_LTE_36p3C                   9
 #define xgxsBlk2_tempIdxSelect_LTE_46p0C                   8
 #define xgxsBlk2_tempIdxSelect_LTE_56p2C                   7
 #define xgxsBlk2_tempIdxSelect_LTE_65p9C                   6
 #define xgxsBlk2_tempIdxSelect_LTE_75p6C                   5
 #define xgxsBlk2_tempIdxSelect_LTE_85p3C                   4
 #define xgxsBlk2_tempIdxSelect_LTE_95p5C                   3
 #define xgxsBlk2_tempIdxSelect_LTE_105p2C                  2
 #define xgxsBlk2_tempIdxSelect_LTE_114p9C                  1
 #define xgxsBlk2_tempIdxSelect_LTE_125p1C                  0
 
 /****************************************************************************
  * Enums: xgxsBlk4_operationModes
  */
 #define xgxsBlk4_operationModes_XGXS                       0
 #define xgxsBlk4_operationModes_XGXG_nCC                   1
 #define xgxsBlk4_operationModes_Indlane_OS8                4
 #define xgxsBlk4_operationModes_IndLane_OS5                5
 #define xgxsBlk4_operationModes_PCI                        7
 #define xgxsBlk4_operationModes_XGXS_nLQ                   8
 #define xgxsBlk4_operationModes_XGXS_nLQnCC                9
 #define xgxsBlk4_operationModes_PBypass                    10
 #define xgxsBlk4_operationModes_PBypass_nDSK               11
 #define xgxsBlk4_operationModes_ComboCoreMode              12
 #define xgxsBlk4_operationModes_Clocks_off                 15
 
 /****************************************************************************
  * Enums: xgxsBlk4_actualSpeeds4
  */
 #define xgxsBlk4_actualSpeeds4_dr_10M                      0
 #define xgxsBlk4_actualSpeeds4_dr_100M                     1
 #define xgxsBlk4_actualSpeeds4_dr_1G                       2
 #define xgxsBlk4_actualSpeeds4_dr_2p5G                     3
 #define xgxsBlk4_actualSpeeds4_dr_5G_X4                    4
 #define xgxsBlk4_actualSpeeds4_dr_6G_X4                    5
 #define xgxsBlk4_actualSpeeds4_dr_10G_HiG                  6
 #define xgxsBlk4_actualSpeeds4_dr_10G_CX4                  7
 #define xgxsBlk4_actualSpeeds4_dr_12G_HiG                  8
 #define xgxsBlk4_actualSpeeds4_dr_12p5G_X4                 9
 #define xgxsBlk4_actualSpeeds4_dr_13G_X4                   10
 #define xgxsBlk4_actualSpeeds4_dr_15G_X4                   11
 #define xgxsBlk4_actualSpeeds4_dr_16G_X4                   12
 
 /****************************************************************************
  * Enums: xgxsBlk4_actualSpeeds5
  */
 #define xgxsBlk4_actualSpeeds5_dr_10M                      0
 #define xgxsBlk4_actualSpeeds5_dr_100M                     1
 #define xgxsBlk4_actualSpeeds5_dr_1G                       2
 #define xgxsBlk4_actualSpeeds5_dr_2p5G                     3
 #define xgxsBlk4_actualSpeeds5_dr_5G_X4                    4
 #define xgxsBlk4_actualSpeeds5_dr_6G_X4                    5
 #define xgxsBlk4_actualSpeeds5_dr_10G_HiG                  6
 #define xgxsBlk4_actualSpeeds5_dr_10G_CX4                  7
 #define xgxsBlk4_actualSpeeds5_dr_12G_HiG                  8
 #define xgxsBlk4_actualSpeeds5_dr_12p5G_X4                 9
 #define xgxsBlk4_actualSpeeds5_dr_13G_X4                   10
 #define xgxsBlk4_actualSpeeds5_dr_15G_X4                   11
 #define xgxsBlk4_actualSpeeds5_dr_16G_X4                   12
 #define xgxsBlk4_actualSpeeds5_dr_1G_KX                    13
 #define xgxsBlk4_actualSpeeds5_dr_10G_KX4                  14
 #define xgxsBlk4_actualSpeeds5_dr_10G_KR                   15
 #define xgxsBlk4_actualSpeeds5_dr_5G                       16
 #define xgxsBlk4_actualSpeeds5_dr_6p4G                     17
 #define xgxsBlk4_actualSpeeds5_dr_20G_X4                   18
 #define xgxsBlk4_actualSpeeds5_dr_21G_X4                   19
 #define xgxsBlk4_actualSpeeds5_dr_25G_X4                   20
 #define xgxsBlk4_actualSpeeds5_dr_10G_HiG_DXGXS            21
 #define xgxsBlk4_actualSpeeds5_dr_10G_DXGXS                22
 #define xgxsBlk4_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
 #define xgxsBlk4_actualSpeeds5_dr_10p5G_DXGXS              24
 #define xgxsBlk4_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
 #define xgxsBlk4_actualSpeeds5_dr_12p773G_DXGXS            26
 #define xgxsBlk4_actualSpeeds5_dr_10G_XFI                  27
 #define xgxsBlk4_actualSpeeds5_dr_40G                      28
 #define xgxsBlk4_actualSpeeds5_dr_20G_HiG_DXGXS            29
 #define xgxsBlk4_actualSpeeds5_dr_20G_DXGXS                30
 #define xgxsBlk4_actualSpeeds5_dr_10G_SFI                  31
 #define xgxsBlk4_actualSpeeds5_dr_31p5G                    32
 #define xgxsBlk4_actualSpeeds5_dr_32p7G                    33
 #define xgxsBlk4_actualSpeeds5_dr_20G_SCR                  34
 #define xgxsBlk4_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
 #define xgxsBlk4_actualSpeeds5_dr_10G_DXGXS_SCR            36
 #define xgxsBlk4_actualSpeeds5_dr_12G_R2                   37
 #define xgxsBlk4_actualSpeeds5_dr_10G_X2                   38
 #define xgxsBlk4_actualSpeeds5_dr_40G_KR4                  39
 #define xgxsBlk4_actualSpeeds5_dr_40G_CR4                  40
 #define xgxsBlk4_actualSpeeds5_dr_100G_CR10                41
 
 /****************************************************************************
  * Enums: xgxsBlk4_actualSpeedsMisc1
  */
 #define xgxsBlk4_actualSpeedsMisc1_dr_2500BRCM_X1          16
 #define xgxsBlk4_actualSpeedsMisc1_dr_5000BRCM_X4          17
 #define xgxsBlk4_actualSpeedsMisc1_dr_6000BRCM_X4          18
 #define xgxsBlk4_actualSpeedsMisc1_dr_10GHiGig_X4          19
 #define xgxsBlk4_actualSpeedsMisc1_dr_10GBASE_CX4          20
 #define xgxsBlk4_actualSpeedsMisc1_dr_12GHiGig_X4          21
 #define xgxsBlk4_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
 #define xgxsBlk4_actualSpeedsMisc1_dr_13GHiGig_X4          23
 #define xgxsBlk4_actualSpeedsMisc1_dr_15GHiGig_X4          24
 #define xgxsBlk4_actualSpeedsMisc1_dr_16GHiGig_X4          25
 #define xgxsBlk4_actualSpeedsMisc1_dr_5000BRCM_X1          26
 #define xgxsBlk4_actualSpeedsMisc1_dr_6363BRCM_X1          27
 #define xgxsBlk4_actualSpeedsMisc1_dr_20GHiGig_X4          28
 #define xgxsBlk4_actualSpeedsMisc1_dr_21GHiGig_X4          29
 #define xgxsBlk4_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
 #define xgxsBlk4_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31
 
 /****************************************************************************
  * Enums: xgxsBlk4_IndLaneModes
  */
 #define xgxsBlk4_IndLaneModes_SWSDR_div2                   0
 #define xgxsBlk4_IndLaneModes_SWSDR_div1                   1
 #define xgxsBlk4_IndLaneModes_DWSDR_div2                   2
 #define xgxsBlk4_IndLaneModes_DWSDR_div1                   3
 
 /****************************************************************************
  * Enums: xgxsBlk4_prbsSelect
  */
 #define xgxsBlk4_prbsSelect_prbs7                          0
 #define xgxsBlk4_prbsSelect_prbs15                         1
 #define xgxsBlk4_prbsSelect_prbs23                         2
 #define xgxsBlk4_prbsSelect_prbs31                         3
 
 /****************************************************************************
  * Enums: xgxsBlk4_vcoDivider
  */
 #define xgxsBlk4_vcoDivider_div32                          0
 #define xgxsBlk4_vcoDivider_div36                          1
 #define xgxsBlk4_vcoDivider_div40                          2
 #define xgxsBlk4_vcoDivider_div42                          3
 #define xgxsBlk4_vcoDivider_div48                          4
 #define xgxsBlk4_vcoDivider_div50                          5
 #define xgxsBlk4_vcoDivider_div52                          6
 #define xgxsBlk4_vcoDivider_div54                          7
 #define xgxsBlk4_vcoDivider_div60                          8
 #define xgxsBlk4_vcoDivider_div64                          9
 #define xgxsBlk4_vcoDivider_div66                          10
 #define xgxsBlk4_vcoDivider_div68                          11
 #define xgxsBlk4_vcoDivider_div80                          12
 #define xgxsBlk4_vcoDivider_div120                         13
 #define xgxsBlk4_vcoDivider_div200                         14
 #define xgxsBlk4_vcoDivider_div240                         15
 
 /****************************************************************************
  * Enums: xgxsBlk4_refClkSelect
  */
 #define xgxsBlk4_refClkSelect_clk_25MHz                    0
 #define xgxsBlk4_refClkSelect_clk_100MHz                   1
 #define xgxsBlk4_refClkSelect_clk_125MHz                   2
 #define xgxsBlk4_refClkSelect_clk_156p25MHz                3
 #define xgxsBlk4_refClkSelect_clk_187p5MHz                 4
 #define xgxsBlk4_refClkSelect_clk_161p25Mhz                5
 #define xgxsBlk4_refClkSelect_clk_50Mhz                    6
 #define xgxsBlk4_refClkSelect_clk_106p25Mhz                7
 
 /****************************************************************************
  * Enums: xgxsBlk4_aerMMDdevTypeSelect
  */
 #define xgxsBlk4_aerMMDdevTypeSelect_combo_core            0
 #define xgxsBlk4_aerMMDdevTypeSelect_PMA_PMD               1
 #define xgxsBlk4_aerMMDdevTypeSelect_PCS                   3
 #define xgxsBlk4_aerMMDdevTypeSelect_PHY                   4
 #define xgxsBlk4_aerMMDdevTypeSelect_DTE                   5
 #define xgxsBlk4_aerMMDdevTypeSelect_CL73_AN               7
 
 /****************************************************************************
  * Enums: xgxsBlk4_aerMMDportSelect
  */
 #define xgxsBlk4_aerMMDportSelect_ln0                      0
 #define xgxsBlk4_aerMMDportSelect_ln1                      1
 #define xgxsBlk4_aerMMDportSelect_ln2                      2
 #define xgxsBlk4_aerMMDportSelect_ln3                      3
 #define xgxsBlk4_aerMMDportSelect_BCST                     511
 
 /****************************************************************************
  * Enums: xgxsBlk4_firmwareModeSelect
  */
 #define xgxsBlk4_firmwareModeSelect_DEFAULT                0
 #define xgxsBlk4_firmwareModeSelect_SFP_OPT_LR             1
 #define xgxsBlk4_firmwareModeSelect_SFP_DAC                2
 #define xgxsBlk4_firmwareModeSelect_XLAUI                  3
 #define xgxsBlk4_firmwareModeSelect_LONG_CH_6G             4
 
 /****************************************************************************
  * Enums: xgxsBlk4_tempIdxSelect
  */
 #define xgxsBlk4_tempIdxSelect_LTE__22p9C                  15
 #define xgxsBlk4_tempIdxSelect_LTE__12p6C                  14
 #define xgxsBlk4_tempIdxSelect_LTE__3p0C                   13
 #define xgxsBlk4_tempIdxSelect_LTE_6p7C                    12
 #define xgxsBlk4_tempIdxSelect_LTE_16p4C                   11
 #define xgxsBlk4_tempIdxSelect_LTE_26p6C                   10
 #define xgxsBlk4_tempIdxSelect_LTE_36p3C                   9
 #define xgxsBlk4_tempIdxSelect_LTE_46p0C                   8
 #define xgxsBlk4_tempIdxSelect_LTE_56p2C                   7
 #define xgxsBlk4_tempIdxSelect_LTE_65p9C                   6
 #define xgxsBlk4_tempIdxSelect_LTE_75p6C                   5
 #define xgxsBlk4_tempIdxSelect_LTE_85p3C                   4
 #define xgxsBlk4_tempIdxSelect_LTE_95p5C                   3
 #define xgxsBlk4_tempIdxSelect_LTE_105p2C                  2
 #define xgxsBlk4_tempIdxSelect_LTE_114p9C                  1
 #define xgxsBlk4_tempIdxSelect_LTE_125p1C                  0
 
 /****************************************************************************
  * Enums: xgxsBlk5_operationModes
  */
 #define xgxsBlk5_operationModes_XGXS                       0
 #define xgxsBlk5_operationModes_XGXG_nCC                   1
 #define xgxsBlk5_operationModes_Indlane_OS8                4
 #define xgxsBlk5_operationModes_IndLane_OS5                5
 #define xgxsBlk5_operationModes_PCI                        7
 #define xgxsBlk5_operationModes_XGXS_nLQ                   8
 #define xgxsBlk5_operationModes_XGXS_nLQnCC                9
 #define xgxsBlk5_operationModes_PBypass                    10
 #define xgxsBlk5_operationModes_PBypass_nDSK               11
 #define xgxsBlk5_operationModes_ComboCoreMode              12
 #define xgxsBlk5_operationModes_Clocks_off                 15
 
 /****************************************************************************
  * Enums: xgxsBlk5_actualSpeeds4
  */
 #define xgxsBlk5_actualSpeeds4_dr_10M                      0
 #define xgxsBlk5_actualSpeeds4_dr_100M                     1
 #define xgxsBlk5_actualSpeeds4_dr_1G                       2
 #define xgxsBlk5_actualSpeeds4_dr_2p5G                     3
 #define xgxsBlk5_actualSpeeds4_dr_5G_X4                    4
 #define xgxsBlk5_actualSpeeds4_dr_6G_X4                    5
 #define xgxsBlk5_actualSpeeds4_dr_10G_HiG                  6
 #define xgxsBlk5_actualSpeeds4_dr_10G_CX4                  7
 #define xgxsBlk5_actualSpeeds4_dr_12G_HiG                  8
 #define xgxsBlk5_actualSpeeds4_dr_12p5G_X4                 9
 #define xgxsBlk5_actualSpeeds4_dr_13G_X4                   10
 #define xgxsBlk5_actualSpeeds4_dr_15G_X4                   11
 #define xgxsBlk5_actualSpeeds4_dr_16G_X4                   12
 
 /****************************************************************************
  * Enums: xgxsBlk5_actualSpeeds5
  */
 #define xgxsBlk5_actualSpeeds5_dr_10M                      0
 #define xgxsBlk5_actualSpeeds5_dr_100M                     1
 #define xgxsBlk5_actualSpeeds5_dr_1G                       2
 #define xgxsBlk5_actualSpeeds5_dr_2p5G                     3
 #define xgxsBlk5_actualSpeeds5_dr_5G_X4                    4
 #define xgxsBlk5_actualSpeeds5_dr_6G_X4                    5
 #define xgxsBlk5_actualSpeeds5_dr_10G_HiG                  6
 #define xgxsBlk5_actualSpeeds5_dr_10G_CX4                  7
 #define xgxsBlk5_actualSpeeds5_dr_12G_HiG                  8
 #define xgxsBlk5_actualSpeeds5_dr_12p5G_X4                 9
 #define xgxsBlk5_actualSpeeds5_dr_13G_X4                   10
 #define xgxsBlk5_actualSpeeds5_dr_15G_X4                   11
 #define xgxsBlk5_actualSpeeds5_dr_16G_X4                   12
 #define xgxsBlk5_actualSpeeds5_dr_1G_KX                    13
 #define xgxsBlk5_actualSpeeds5_dr_10G_KX4                  14
 #define xgxsBlk5_actualSpeeds5_dr_10G_KR                   15
 #define xgxsBlk5_actualSpeeds5_dr_5G                       16
 #define xgxsBlk5_actualSpeeds5_dr_6p4G                     17
 #define xgxsBlk5_actualSpeeds5_dr_20G_X4                   18
 #define xgxsBlk5_actualSpeeds5_dr_21G_X4                   19
 #define xgxsBlk5_actualSpeeds5_dr_25G_X4                   20
 #define xgxsBlk5_actualSpeeds5_dr_10G_HiG_DXGXS            21
 #define xgxsBlk5_actualSpeeds5_dr_10G_DXGXS                22
 #define xgxsBlk5_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
 #define xgxsBlk5_actualSpeeds5_dr_10p5G_DXGXS              24
 #define xgxsBlk5_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
 #define xgxsBlk5_actualSpeeds5_dr_12p773G_DXGXS            26
 #define xgxsBlk5_actualSpeeds5_dr_10G_XFI                  27
 #define xgxsBlk5_actualSpeeds5_dr_40G                      28
 #define xgxsBlk5_actualSpeeds5_dr_20G_HiG_DXGXS            29
 #define xgxsBlk5_actualSpeeds5_dr_20G_DXGXS                30
 #define xgxsBlk5_actualSpeeds5_dr_10G_SFI                  31
 #define xgxsBlk5_actualSpeeds5_dr_31p5G                    32
 #define xgxsBlk5_actualSpeeds5_dr_32p7G                    33
 #define xgxsBlk5_actualSpeeds5_dr_20G_SCR                  34
 #define xgxsBlk5_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
 #define xgxsBlk5_actualSpeeds5_dr_10G_DXGXS_SCR            36
 #define xgxsBlk5_actualSpeeds5_dr_12G_R2                   37
 #define xgxsBlk5_actualSpeeds5_dr_10G_X2                   38
 #define xgxsBlk5_actualSpeeds5_dr_40G_KR4                  39
 #define xgxsBlk5_actualSpeeds5_dr_40G_CR4                  40
 #define xgxsBlk5_actualSpeeds5_dr_100G_CR10                41
 
 /****************************************************************************
  * Enums: xgxsBlk5_actualSpeedsMisc1
  */
 #define xgxsBlk5_actualSpeedsMisc1_dr_2500BRCM_X1          16
 #define xgxsBlk5_actualSpeedsMisc1_dr_5000BRCM_X4          17
 #define xgxsBlk5_actualSpeedsMisc1_dr_6000BRCM_X4          18
 #define xgxsBlk5_actualSpeedsMisc1_dr_10GHiGig_X4          19
 #define xgxsBlk5_actualSpeedsMisc1_dr_10GBASE_CX4          20
 #define xgxsBlk5_actualSpeedsMisc1_dr_12GHiGig_X4          21
 #define xgxsBlk5_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
 #define xgxsBlk5_actualSpeedsMisc1_dr_13GHiGig_X4          23
 #define xgxsBlk5_actualSpeedsMisc1_dr_15GHiGig_X4          24
 #define xgxsBlk5_actualSpeedsMisc1_dr_16GHiGig_X4          25
 #define xgxsBlk5_actualSpeedsMisc1_dr_5000BRCM_X1          26
 #define xgxsBlk5_actualSpeedsMisc1_dr_6363BRCM_X1          27
 #define xgxsBlk5_actualSpeedsMisc1_dr_20GHiGig_X4          28
 #define xgxsBlk5_actualSpeedsMisc1_dr_21GHiGig_X4          29
 #define xgxsBlk5_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
 #define xgxsBlk5_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31
 
 /****************************************************************************
  * Enums: xgxsBlk5_IndLaneModes
  */
 #define xgxsBlk5_IndLaneModes_SWSDR_div2                   0
 #define xgxsBlk5_IndLaneModes_SWSDR_div1                   1
 #define xgxsBlk5_IndLaneModes_DWSDR_div2                   2
 #define xgxsBlk5_IndLaneModes_DWSDR_div1                   3
 
 /****************************************************************************
  * Enums: xgxsBlk5_prbsSelect
  */
 #define xgxsBlk5_prbsSelect_prbs7                          0
 #define xgxsBlk5_prbsSelect_prbs15                         1
 #define xgxsBlk5_prbsSelect_prbs23                         2
 #define xgxsBlk5_prbsSelect_prbs31                         3
 
 /****************************************************************************
  * Enums: xgxsBlk5_vcoDivider
  */
 #define xgxsBlk5_vcoDivider_div32                          0
 #define xgxsBlk5_vcoDivider_div36                          1
 #define xgxsBlk5_vcoDivider_div40                          2
 #define xgxsBlk5_vcoDivider_div42                          3
 #define xgxsBlk5_vcoDivider_div48                          4
 #define xgxsBlk5_vcoDivider_div50                          5
 #define xgxsBlk5_vcoDivider_div52                          6
 #define xgxsBlk5_vcoDivider_div54                          7
 #define xgxsBlk5_vcoDivider_div60                          8
 #define xgxsBlk5_vcoDivider_div64                          9
 #define xgxsBlk5_vcoDivider_div66                          10
 #define xgxsBlk5_vcoDivider_div68                          11
 #define xgxsBlk5_vcoDivider_div80                          12
 #define xgxsBlk5_vcoDivider_div120                         13
 #define xgxsBlk5_vcoDivider_div200                         14
 #define xgxsBlk5_vcoDivider_div240                         15
 
 /****************************************************************************
  * Enums: xgxsBlk5_refClkSelect
  */
 #define xgxsBlk5_refClkSelect_clk_25MHz                    0
 #define xgxsBlk5_refClkSelect_clk_100MHz                   1
 #define xgxsBlk5_refClkSelect_clk_125MHz                   2
 #define xgxsBlk5_refClkSelect_clk_156p25MHz                3
 #define xgxsBlk5_refClkSelect_clk_187p5MHz                 4
 #define xgxsBlk5_refClkSelect_clk_161p25Mhz                5
 #define xgxsBlk5_refClkSelect_clk_50Mhz                    6
 #define xgxsBlk5_refClkSelect_clk_106p25Mhz                7
 
 /****************************************************************************
  * Enums: xgxsBlk5_aerMMDdevTypeSelect
  */
 #define xgxsBlk5_aerMMDdevTypeSelect_combo_core            0
 #define xgxsBlk5_aerMMDdevTypeSelect_PMA_PMD               1
 #define xgxsBlk5_aerMMDdevTypeSelect_PCS                   3
 #define xgxsBlk5_aerMMDdevTypeSelect_PHY                   4
 #define xgxsBlk5_aerMMDdevTypeSelect_DTE                   5
 #define xgxsBlk5_aerMMDdevTypeSelect_CL73_AN               7
 
 /****************************************************************************
  * Enums: xgxsBlk5_aerMMDportSelect
  */
 #define xgxsBlk5_aerMMDportSelect_ln0                      0
 #define xgxsBlk5_aerMMDportSelect_ln1                      1
 #define xgxsBlk5_aerMMDportSelect_ln2                      2
 #define xgxsBlk5_aerMMDportSelect_ln3                      3
 #define xgxsBlk5_aerMMDportSelect_BCST                     511
 
 /****************************************************************************
  * Enums: xgxsBlk5_firmwareModeSelect
  */
 #define xgxsBlk5_firmwareModeSelect_DEFAULT                0
 #define xgxsBlk5_firmwareModeSelect_SFP_OPT_LR             1
 #define xgxsBlk5_firmwareModeSelect_SFP_DAC                2
 #define xgxsBlk5_firmwareModeSelect_XLAUI                  3
 #define xgxsBlk5_firmwareModeSelect_LONG_CH_6G             4
 
 /****************************************************************************
  * Enums: xgxsBlk5_tempIdxSelect
  */
 #define xgxsBlk5_tempIdxSelect_LTE__22p9C                  15
 #define xgxsBlk5_tempIdxSelect_LTE__12p6C                  14
 #define xgxsBlk5_tempIdxSelect_LTE__3p0C                   13
 #define xgxsBlk5_tempIdxSelect_LTE_6p7C                    12
 #define xgxsBlk5_tempIdxSelect_LTE_16p4C                   11
 #define xgxsBlk5_tempIdxSelect_LTE_26p6C                   10
 #define xgxsBlk5_tempIdxSelect_LTE_36p3C                   9
 #define xgxsBlk5_tempIdxSelect_LTE_46p0C                   8
 #define xgxsBlk5_tempIdxSelect_LTE_56p2C                   7
 #define xgxsBlk5_tempIdxSelect_LTE_65p9C                   6
 #define xgxsBlk5_tempIdxSelect_LTE_75p6C                   5
 #define xgxsBlk5_tempIdxSelect_LTE_85p3C                   4
 #define xgxsBlk5_tempIdxSelect_LTE_95p5C                   3
 #define xgxsBlk5_tempIdxSelect_LTE_105p2C                  2
 #define xgxsBlk5_tempIdxSelect_LTE_114p9C                  1
 #define xgxsBlk5_tempIdxSelect_LTE_125p1C                  0
 
 /****************************************************************************
  * Enums: xgxsBlk7_cl48TxEEEStates_l
  */
 #define xgxsBlk7_cl48TxEEEStates_l_TX_REFRESH              8
 #define xgxsBlk7_cl48TxEEEStates_l_TX_QUIET                4
 #define xgxsBlk7_cl48TxEEEStates_l_TX_SLEEP                2
 #define xgxsBlk7_cl48TxEEEStates_l_TX_ACTIVE               1
 
 /****************************************************************************
  * Enums: xgxsBlk7_cl48TxEEEStates_c
  */
 #define xgxsBlk7_cl48TxEEEStates_c_TX_REFRESH              3
 #define xgxsBlk7_cl48TxEEEStates_c_TX_QUIET                2
 #define xgxsBlk7_cl48TxEEEStates_c_TX_SLEEP                1
 #define xgxsBlk7_cl48TxEEEStates_c_TX_ACTIVE               0
 
 /****************************************************************************
  * Enums: xgxsBlk7_cl48RxEEEStates_l
  */
 #define xgxsBlk7_cl48RxEEEStates_l_RX_LINK_FAIL            32
 #define xgxsBlk7_cl48RxEEEStates_l_RX_WAKE                 16
 #define xgxsBlk7_cl48RxEEEStates_l_RX_QUIET                8
 #define xgxsBlk7_cl48RxEEEStates_l_RX_DEACT                4
 #define xgxsBlk7_cl48RxEEEStates_l_RX_SLEEP                2
 #define xgxsBlk7_cl48RxEEEStates_l_RX_ACTIVE               1
 
 /****************************************************************************
  * Enums: xgxsBlk7_cl48RxEEEStates_c
  */
 #define xgxsBlk7_cl48RxEEEStates_c_RX_LINK_FAIL            5
 #define xgxsBlk7_cl48RxEEEStates_c_RX_WAKE                 4
 #define xgxsBlk7_cl48RxEEEStates_c_RX_QUIET                3
 #define xgxsBlk7_cl48RxEEEStates_c_RX_DEACT                2
 #define xgxsBlk7_cl48RxEEEStates_c_RX_SLEEP                1
 #define xgxsBlk7_cl48RxEEEStates_c_RX_ACTIVE               0
 
 /****************************************************************************
  * Warpcore_IEEE_CL22_ieee0Blk
  */
 
 /* IEEE MII control register */
 #define READ_WC40_IEEE0BLK_MIICNTLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00000000, (_val))
 #define WRITE_WC40_IEEE0BLK_MIICNTLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00000000, (_val))
 #define MODIFY_WC40_IEEE0BLK_MIICNTLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00000000, (_val), (_mask))
 
 /* IEEE MII status register */
 #define READ_WC40_IEEE0BLK_MIISTATr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00000001, (_val))
 #define WRITE_WC40_IEEE0BLK_MIISTATr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00000001, (_val))
 #define MODIFY_WC40_IEEE0BLK_MIISTATr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00000001, (_val), (_mask))
 
 /* IEEE phy ID LSByte register */
 #define READ_WC40_IEEE0BLK_ID1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00000002, (_val))
 #define WRITE_WC40_IEEE0BLK_ID1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00000002, (_val))
 #define MODIFY_WC40_IEEE0BLK_ID1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00000002, (_val), (_mask))
 
 /* IEEE phy ID MSByte register */
 #define READ_WC40_IEEE0BLK_ID2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00000003, (_val))
 #define WRITE_WC40_IEEE0BLK_ID2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00000003, (_val))
 #define MODIFY_WC40_IEEE0BLK_ID2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00000003, (_val), (_mask))
 
 /* IEEE auto-negotiation advertised abilities register */
 #define READ_WC40_IEEE0BLK_AUTONEGADVr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00000004, (_val))
 #define WRITE_WC40_IEEE0BLK_AUTONEGADVr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00000004, (_val))
 #define MODIFY_WC40_IEEE0BLK_AUTONEGADVr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00000004, (_val), (_mask))
 
 /* IEEE auto-negotiation link partner abilities register */
 #define READ_WC40_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00000005, (_val))
 #define WRITE_WC40_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00000005, (_val))
 #define MODIFY_WC40_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00000005, (_val), (_mask))
 
 /* IEEE auto-negotiation expansion register */
 #define READ_WC40_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00000006, (_val))
 #define WRITE_WC40_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00000006, (_val))
 #define MODIFY_WC40_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00000006, (_val), (_mask))
 
 /* IEEE auto-negotiation next page register */
 #define READ_WC40_IEEE0BLK_AUTONEGNPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00000007, (_val))
 #define WRITE_WC40_IEEE0BLK_AUTONEGNPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00000007, (_val))
 #define MODIFY_WC40_IEEE0BLK_AUTONEGNPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00000007, (_val), (_mask))
 
 /* IEEE auto-negotiation link partner next page register */
 #define READ_WC40_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00000008, (_val))
 #define WRITE_WC40_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00000008, (_val))
 #define MODIFY_WC40_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00000008, (_val), (_mask))
 
 /* IEEE MII extended status register */
 #define READ_WC40_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000000f, (_val))
 #define WRITE_WC40_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000000f, (_val))
 #define MODIFY_WC40_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000000f, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk0
  */
 
 /* XGXS control register */
 #define READ_WC40_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008000, (_val))
 #define WRITE_WC40_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008000, (_val))
 #define MODIFY_WC40_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008000, (_val), (_mask))
 
 /* XGXS status register */
 #define READ_WC40_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008001, (_val))
 #define WRITE_WC40_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008001, (_val))
 #define MODIFY_WC40_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008001, (_val), (_mask))
 
 /* XGMII idle control character register */
 #define READ_WC40_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008002, (_val))
 #define WRITE_WC40_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008002, (_val))
 #define MODIFY_WC40_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008002, (_val), (_mask))
 
 /* XGMII sync control character register */
 #define READ_WC40_XGXSBLK0_XGMIISYNCr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008003, (_val))
 #define WRITE_WC40_XGXSBLK0_XGMIISYNCr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008003, (_val))
 #define MODIFY_WC40_XGXSBLK0_XGMIISYNCr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008003, (_val), (_mask))
 
 /* XGMII skip control character register */
 #define READ_WC40_XGXSBLK0_XGMIISKIPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008004, (_val))
 #define WRITE_WC40_XGXSBLK0_XGMIISKIPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008004, (_val))
 #define MODIFY_WC40_XGXSBLK0_XGMIISKIPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008004, (_val), (_mask))
 
 /* XGMII sop & eop control character register */
 #define READ_WC40_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008005, (_val))
 #define WRITE_WC40_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008005, (_val))
 #define MODIFY_WC40_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008005, (_val), (_mask))
 
 /* XGMII alignment & eror control character register */
 #define READ_WC40_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008006, (_val))
 #define WRITE_WC40_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008006, (_val))
 #define MODIFY_WC40_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008006, (_val), (_mask))
 
 /* XGMII receive control register */
 #define READ_WC40_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008007, (_val))
 #define WRITE_WC40_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008007, (_val))
 #define MODIFY_WC40_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008007, (_val), (_mask))
 
 /* XGMII transmit control register */
 #define READ_WC40_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008008, (_val))
 #define WRITE_WC40_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008008, (_val))
 #define MODIFY_WC40_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008008, (_val), (_mask))
 
 /* XGMII ||A|| minimum swap spacing */
 #define READ_WC40_XGXSBLK0_XGMIISWAPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008009, (_val))
 #define WRITE_WC40_XGXSBLK0_XGMIISWAPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008009, (_val))
 #define MODIFY_WC40_XGXSBLK0_XGMIISWAPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008009, (_val), (_mask))
 
 /* LSS information byte register */
 #define READ_WC40_XGXSBLK0_LSSLSIDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000800a, (_val))
 #define WRITE_WC40_XGXSBLK0_LSSLSIDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000800a, (_val))
 #define MODIFY_WC40_XGXSBLK0_LSSLSIDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000800a, (_val), (_mask))
 
 /* LSS transmit information byte register */
 #define READ_WC40_XGXSBLK0_LSSTINFOr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000800b, (_val))
 #define WRITE_WC40_XGXSBLK0_LSSTINFOr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000800b, (_val))
 #define MODIFY_WC40_XGXSBLK0_LSSTINFOr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000800b, (_val), (_mask))
 
 /* LSS receive information byte register */
 #define READ_WC40_XGXSBLK0_LSSRINFOr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000800c, (_val))
 #define WRITE_WC40_XGXSBLK0_LSSRINFOr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000800c, (_val))
 #define MODIFY_WC40_XGXSBLK0_LSSRINFOr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000800c, (_val), (_mask))
 
 /* MMD select register */
 #define READ_WC40_XGXSBLK0_MMDSELECTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000800d, (_val))
 #define WRITE_WC40_XGXSBLK0_MMDSELECTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000800d, (_val))
 #define MODIFY_WC40_XGXSBLK0_MMDSELECTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000800d, (_val), (_mask))
 
 /* Miscellaneous control 1 register */
 #define READ_WC40_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000800e, (_val))
 #define WRITE_WC40_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000800e, (_val))
 #define MODIFY_WC40_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000800e, (_val), (_mask))
 
 /* Block Address register */
 #define READ_WC40_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000800f, (_val))
 #define WRITE_WC40_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000800f, (_val))
 #define MODIFY_WC40_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000800f, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk1
  */
 
 /* Lane deskew register */
 #define READ_WC40_XGXSBLK1_DESKEWr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008010, (_val))
 #define WRITE_WC40_XGXSBLK1_DESKEWr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008010, (_val))
 #define MODIFY_WC40_XGXSBLK1_DESKEWr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008010, (_val), (_mask))
 
 /* Link ||A|| column timeout value register */
 #define READ_WC40_XGXSBLK1_LINKr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008011, (_val))
 #define WRITE_WC40_XGXSBLK1_LINKr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008011, (_val))
 #define MODIFY_WC40_XGXSBLK1_LINKr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008011, (_val), (_mask))
 
 /* Receive test control register */
 #define READ_WC40_XGXSBLK1_TESTRXr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008012, (_val))
 #define WRITE_WC40_XGXSBLK1_TESTRXr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008012, (_val))
 #define MODIFY_WC40_XGXSBLK1_TESTRXr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008012, (_val), (_mask))
 
 /* Transmit test control register */
 #define READ_WC40_XGXSBLK1_TESTTXr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008013, (_val))
 #define WRITE_WC40_XGXSBLK1_TESTTXr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008013, (_val))
 #define MODIFY_WC40_XGXSBLK1_TESTTXr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008013, (_val), (_mask))
 
 /* XGXS test control register */
 #define READ_WC40_XGXSBLK1_TESTXGr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008014, (_val))
 #define WRITE_WC40_XGXSBLK1_TESTXGr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008014, (_val))
 #define MODIFY_WC40_XGXSBLK1_TESTXGr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008014, (_val), (_mask))
 
 /* Lane control 0 register */
 #define READ_WC40_XGXSBLK1_LANECTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008015, (_val))
 #define WRITE_WC40_XGXSBLK1_LANECTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008015, (_val))
 #define MODIFY_WC40_XGXSBLK1_LANECTRL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008015, (_val), (_mask))
 
 /* Lane control 1 register */
 #define READ_WC40_XGXSBLK1_LANECTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008016, (_val))
 #define WRITE_WC40_XGXSBLK1_LANECTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008016, (_val))
 #define MODIFY_WC40_XGXSBLK1_LANECTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008016, (_val), (_mask))
 
 /* Lane control 2 register */
 #define READ_WC40_XGXSBLK1_LANECTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008017, (_val))
 #define WRITE_WC40_XGXSBLK1_LANECTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008017, (_val))
 #define MODIFY_WC40_XGXSBLK1_LANECTRL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008017, (_val), (_mask))
 
 /* Lane control 3 register */
 #define READ_WC40_XGXSBLK1_LANECTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008018, (_val))
 #define WRITE_WC40_XGXSBLK1_LANECTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008018, (_val))
 #define MODIFY_WC40_XGXSBLK1_LANECTRL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008018, (_val), (_mask))
 
 /* Lane PRBS control register */
 #define READ_WC40_XGXSBLK1_LANEPRBSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008019, (_val))
 #define WRITE_WC40_XGXSBLK1_LANEPRBSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008019, (_val))
 #define MODIFY_WC40_XGXSBLK1_LANEPRBSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008019, (_val), (_mask))
 
 /* Lane test control register */
 #define READ_WC40_XGXSBLK1_LANETESTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000801a, (_val))
 #define WRITE_WC40_XGXSBLK1_LANETESTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000801a, (_val))
 #define MODIFY_WC40_XGXSBLK1_LANETESTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000801a, (_val), (_mask))
 
 /* LSS, ||Q|| column count register */
 #define READ_WC40_XGXSBLK1_LSSREVNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000801b, (_val))
 #define WRITE_WC40_XGXSBLK1_LSSREVNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000801b, (_val))
 #define MODIFY_WC40_XGXSBLK1_LSSREVNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000801b, (_val), (_mask))
 
 /* Lane deskew event count register */
 #define READ_WC40_XGXSBLK1_DSKEVNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000801c, (_val))
 #define WRITE_WC40_XGXSBLK1_DSKEVNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000801c, (_val))
 #define MODIFY_WC40_XGXSBLK1_DSKEVNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000801c, (_val), (_mask))
 
 /* Bad ||A|| column count register */
 #define READ_WC40_XGXSBLK1_AERREVNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000801d, (_val))
 #define WRITE_WC40_XGXSBLK1_AERREVNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000801d, (_val))
 #define MODIFY_WC40_XGXSBLK1_AERREVNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000801d, (_val), (_mask))
 
 /* Clock compensation event count register */
 #define READ_WC40_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000801e, (_val))
 #define WRITE_WC40_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000801e, (_val))
 #define MODIFY_WC40_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000801e, (_val), (_mask))
 
 /* Block Address register */
 #define READ_WC40_XGXSBLK1_BLOCKADDRESSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000801f, (_val))
 #define WRITE_WC40_XGXSBLK1_BLOCKADDRESSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000801f, (_val))
 #define MODIFY_WC40_XGXSBLK1_BLOCKADDRESSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000801f, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_TxBert
  */
 
 /* Tx Bert control register */
 #define READ_WC40_TXBERT_TXBERTCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008020, (_val))
 #define WRITE_WC40_TXBERT_TXBERTCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008020, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTCTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008020, (_val), (_mask))
 
 /* Tx Bert SOP, EOP definition register */
 #define READ_WC40_TXBERT_TXBERTSOPEOPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008021, (_val))
 #define WRITE_WC40_TXBERT_TXBERTSOPEOPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008021, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTSOPEOPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008021, (_val), (_mask))
 
 /* Packet size configuration 0 register */
 #define READ_WC40_TXBERT_TXBERTSIZE0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008022, (_val))
 #define WRITE_WC40_TXBERT_TXBERTSIZE0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008022, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTSIZE0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008022, (_val), (_mask))
 
 /* Packet size configuration 1 register */
 #define READ_WC40_TXBERT_TXBERTSIZE1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008023, (_val))
 #define WRITE_WC40_TXBERT_TXBERTSIZE1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008023, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTSIZE1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008023, (_val), (_mask))
 
 /* Packet size configuration 2 register */
 #define READ_WC40_TXBERT_TXBERTSIZE2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008024, (_val))
 #define WRITE_WC40_TXBERT_TXBERTSIZE2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008024, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTSIZE2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008024, (_val), (_mask))
 
 /* IPG 0 definition register */
 #define READ_WC40_TXBERT_TXBERTIPG0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008025, (_val))
 #define WRITE_WC40_TXBERT_TXBERTIPG0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008025, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTIPG0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008025, (_val), (_mask))
 
 /* IPG 1 definition register */
 #define READ_WC40_TXBERT_TXBERTIPG1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008026, (_val))
 #define WRITE_WC40_TXBERT_TXBERTIPG1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008026, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTIPG1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008026, (_val), (_mask))
 
 /* Transmitted byte count upper 16 bits register */
 #define READ_WC40_TXBERT_TXBERTBYTEUr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008027, (_val))
 #define WRITE_WC40_TXBERT_TXBERTBYTEUr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008027, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTBYTEUr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008027, (_val), (_mask))
 
 /* Transmitted byte count lower 16 bits register */
 #define READ_WC40_TXBERT_TXBERTBYTELr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008028, (_val))
 #define WRITE_WC40_TXBERT_TXBERTBYTELr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008028, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTBYTELr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008028, (_val), (_mask))
 
 /* Transmitted packet count upper 16 bits register */
 #define READ_WC40_TXBERT_TXBERTPACKETUr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008029, (_val))
 #define WRITE_WC40_TXBERT_TXBERTPACKETUr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008029, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTPACKETUr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008029, (_val), (_mask))
 
 /* Transmitted packet count lower 16 bits register */
 #define READ_WC40_TXBERT_TXBERTPACKETLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000802a, (_val))
 #define WRITE_WC40_TXBERT_TXBERTPACKETLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000802a, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTPACKETLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000802a, (_val), (_mask))
 
 /* Tx Bert control1 register */
 #define READ_WC40_TXBERT_TXBERTCTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000802b, (_val))
 #define WRITE_WC40_TXBERT_TXBERTCTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000802b, (_val))
 #define MODIFY_WC40_TXBERT_TXBERTCTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000802b, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_RxBert
  */
 
 /* Rx Bert control register */
 #define READ_WC40_RXBERT_RXBERTCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008030, (_val))
 #define WRITE_WC40_RXBERT_RXBERTCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008030, (_val))
 #define MODIFY_WC40_RXBERT_RXBERTCTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008030, (_val), (_mask))
 
 /* Rx Bert SOP, EOP definition register */
 #define READ_WC40_RXBERT_RXBERTSOPEOPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008031, (_val))
 #define WRITE_WC40_RXBERT_RXBERTSOPEOPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008031, (_val))
 #define MODIFY_WC40_RXBERT_RXBERTSOPEOPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008031, (_val), (_mask))
 
 /* Received byte count upper 16 bits register */
 #define READ_WC40_RXBERT_RXBERTBYTEUr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008037, (_val))
 #define WRITE_WC40_RXBERT_RXBERTBYTEUr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008037, (_val))
 #define MODIFY_WC40_RXBERT_RXBERTBYTEUr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008037, (_val), (_mask))
 
 /* Received bytes count lower 16 bits register */
 #define READ_WC40_RXBERT_RXBERTBYTELr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008038, (_val))
 #define WRITE_WC40_RXBERT_RXBERTBYTELr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008038, (_val))
 #define MODIFY_WC40_RXBERT_RXBERTBYTELr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008038, (_val), (_mask))
 
 /* Received packet count upper 16 bits register */
 #define READ_WC40_RXBERT_RXBERTPACKETUr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008039, (_val))
 #define WRITE_WC40_RXBERT_RXBERTPACKETUr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008039, (_val))
 #define MODIFY_WC40_RXBERT_RXBERTPACKETUr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008039, (_val), (_mask))
 
 /* Received packet count lower 16 bits register */
 #define READ_WC40_RXBERT_RXBERTPACKETLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000803a, (_val))
 #define WRITE_WC40_RXBERT_RXBERTPACKETLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000803a, (_val))
 #define MODIFY_WC40_RXBERT_RXBERTPACKETLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000803a, (_val), (_mask))
 
 /* Received bits error count */
 #define READ_WC40_RXBERT_RXBERTBITERRr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000803b, (_val))
 #define WRITE_WC40_RXBERT_RXBERTBITERRr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000803b, (_val))
 #define MODIFY_WC40_RXBERT_RXBERTBITERRr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000803b, (_val), (_mask))
 
 /* Received bytes error count */
 #define READ_WC40_RXBERT_RXBERTBYTEERRr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000803c, (_val))
 #define WRITE_WC40_RXBERT_RXBERTBYTEERRr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000803c, (_val))
 #define MODIFY_WC40_RXBERT_RXBERTBYTEERRr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000803c, (_val), (_mask))
 
 /* Received packets error count */
 #define READ_WC40_RXBERT_RXBERTPKTERRr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000803d, (_val))
 #define WRITE_WC40_RXBERT_RXBERTPKTERRr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000803d, (_val))
 #define MODIFY_WC40_RXBERT_RXBERTPKTERRr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000803d, (_val), (_mask))
 
 /* Receive Status */
 #define READ_WC40_RXBERT_RXBERTSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000803e, (_val))
 #define WRITE_WC40_RXBERT_RXBERTSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000803e, (_val))
 #define MODIFY_WC40_RXBERT_RXBERTSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000803e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_PLL
  */
 
 /* PLL status register */
 #define READ_WC40_PLL_ANAPLLSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008050, (_val))
 #define WRITE_WC40_PLL_ANAPLLSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008050, (_val))
 #define MODIFY_WC40_PLL_ANAPLLSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008050, (_val), (_mask))
 
 /* PLL control register */
 #define READ_WC40_PLL_ANAPLLCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008051, (_val))
 #define WRITE_WC40_PLL_ANAPLLCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008051, (_val))
 #define MODIFY_WC40_PLL_ANAPLLCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008051, (_val), (_mask))
 
 /* PLL start up state machine vco timers */
 #define READ_WC40_PLL_ANAPLLTIMER1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008052, (_val))
 #define WRITE_WC40_PLL_ANAPLLTIMER1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008052, (_val))
 #define MODIFY_WC40_PLL_ANAPLLTIMER1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008052, (_val), (_mask))
 
 /* PLL start up state machine retry timer */
 #define READ_WC40_PLL_ANAPLLTIMER2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008053, (_val))
 #define WRITE_WC40_PLL_ANAPLLTIMER2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008053, (_val))
 #define MODIFY_WC40_PLL_ANAPLLTIMER2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008053, (_val), (_mask))
 
 /* PLL start up state machine freq. detect timer */
 #define READ_WC40_PLL_ANAPLLTIMER3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008054, (_val))
 #define WRITE_WC40_PLL_ANAPLLTIMER3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008054, (_val))
 #define MODIFY_WC40_PLL_ANAPLLTIMER3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008054, (_val), (_mask))
 
 /* PLL vco range control state machine */
 #define READ_WC40_PLL_ANACAPCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008055, (_val))
 #define WRITE_WC40_PLL_ANACAPCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008055, (_val))
 #define MODIFY_WC40_PLL_ANACAPCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008055, (_val), (_mask))
 
 /* Frequency detector control */
 #define READ_WC40_PLL_ANAFREQDETCNTRr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008057, (_val))
 #define WRITE_WC40_PLL_ANAFREQDETCNTRr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008057, (_val))
 #define MODIFY_WC40_PLL_ANAFREQDETCNTRr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008057, (_val), (_mask))
 
 /* PLL analog status */
 #define READ_WC40_PLL_ANAPLLASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008058, (_val))
 #define WRITE_WC40_PLL_ANAPLLASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008058, (_val))
 #define MODIFY_WC40_PLL_ANAPLLASTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008058, (_val), (_mask))
 
 /* PLL analog controls */
 #define READ_WC40_PLL_ANAPLLACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000805a, (_val))
 #define WRITE_WC40_PLL_ANAPLLACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000805a, (_val))
 #define MODIFY_WC40_PLL_ANAPLLACONTROL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000805a, (_val), (_mask))
 
 /* PLL analog controls */
 #define READ_WC40_PLL_ANAPLLACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000805b, (_val))
 #define WRITE_WC40_PLL_ANAPLLACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000805b, (_val))
 #define MODIFY_WC40_PLL_ANAPLLACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000805b, (_val), (_mask))
 
 /* PLL analog controls */
 #define READ_WC40_PLL_ANAPLLACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000805c, (_val))
 #define WRITE_WC40_PLL_ANAPLLACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000805c, (_val))
 #define MODIFY_WC40_PLL_ANAPLLACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000805c, (_val), (_mask))
 
 /* PLL analog controls */
 #define READ_WC40_PLL_ANAPLLACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000805d, (_val))
 #define WRITE_WC40_PLL_ANAPLLACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000805d, (_val))
 #define MODIFY_WC40_PLL_ANAPLLACONTROL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000805d, (_val), (_mask))
 
 /* PLL analog controls */
 #define READ_WC40_PLL_ANAPLLACONTROL4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000805e, (_val))
 #define WRITE_WC40_PLL_ANAPLLACONTROL4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000805e, (_val))
 #define MODIFY_WC40_PLL_ANAPLLACONTROL4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000805e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Tx0
  */
 
 /* Tx analog status 0 register */
 #define READ_WC40_TX0_ANATXASTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008060, (_val))
 #define WRITE_WC40_TX0_ANATXASTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008060, (_val))
 #define MODIFY_WC40_TX0_ANATXASTATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008060, (_val), (_mask))
 
 /* Tx analog control 0 register */
 #define READ_WC40_TX0_ANATXACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008061, (_val))
 #define WRITE_WC40_TX0_ANATXACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008061, (_val))
 #define MODIFY_WC40_TX0_ANATXACONTROL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008061, (_val), (_mask))
 
 /* Tx test mux data 0 register */
 #define READ_WC40_TX0_ANATXMDATA0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008062, (_val))
 #define WRITE_WC40_TX0_ANATXMDATA0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008062, (_val))
 #define MODIFY_WC40_TX0_ANATXMDATA0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008062, (_val), (_mask))
 
 /* Tx test mux data 1 register */
 #define READ_WC40_TX0_ANATXMDATA1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008063, (_val))
 #define WRITE_WC40_TX0_ANATXMDATA1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008063, (_val))
 #define MODIFY_WC40_TX0_ANATXMDATA1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008063, (_val), (_mask))
 
 /* Tx analog status 1 register */
 #define READ_WC40_TX0_ANATXASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008064, (_val))
 #define WRITE_WC40_TX0_ANATXASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008064, (_val))
 #define MODIFY_WC40_TX0_ANATXASTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008064, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX0_ANATXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008065, (_val))
 #define WRITE_WC40_TX0_ANATXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008065, (_val))
 #define MODIFY_WC40_TX0_ANATXACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008065, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX0_ANATXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008066, (_val))
 #define WRITE_WC40_TX0_ANATXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008066, (_val))
 #define MODIFY_WC40_TX0_ANATXACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008066, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX0_TX_DRIVERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008067, (_val))
 #define WRITE_WC40_TX0_TX_DRIVERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008067, (_val))
 #define MODIFY_WC40_TX0_TX_DRIVERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008067, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Tx1
  */
 
 /* Tx analog status 0 register */
 #define READ_WC40_TX1_ANATXASTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008070, (_val))
 #define WRITE_WC40_TX1_ANATXASTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008070, (_val))
 #define MODIFY_WC40_TX1_ANATXASTATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008070, (_val), (_mask))
 
 /* Tx analog control 0 register */
 #define READ_WC40_TX1_ANATXACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008071, (_val))
 #define WRITE_WC40_TX1_ANATXACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008071, (_val))
 #define MODIFY_WC40_TX1_ANATXACONTROL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008071, (_val), (_mask))
 
 /* Tx test mux data 0 register */
 #define READ_WC40_TX1_ANATXMDATA0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008072, (_val))
 #define WRITE_WC40_TX1_ANATXMDATA0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008072, (_val))
 #define MODIFY_WC40_TX1_ANATXMDATA0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008072, (_val), (_mask))
 
 /* Tx test mux data 1 register */
 #define READ_WC40_TX1_ANATXMDATA1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008073, (_val))
 #define WRITE_WC40_TX1_ANATXMDATA1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008073, (_val))
 #define MODIFY_WC40_TX1_ANATXMDATA1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008073, (_val), (_mask))
 
 /* Tx analog status 1 register */
 #define READ_WC40_TX1_ANATXASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008074, (_val))
 #define WRITE_WC40_TX1_ANATXASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008074, (_val))
 #define MODIFY_WC40_TX1_ANATXASTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008074, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX1_ANATXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008075, (_val))
 #define WRITE_WC40_TX1_ANATXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008075, (_val))
 #define MODIFY_WC40_TX1_ANATXACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008075, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX1_ANATXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008076, (_val))
 #define WRITE_WC40_TX1_ANATXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008076, (_val))
 #define MODIFY_WC40_TX1_ANATXACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008076, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX1_TX_DRIVERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008077, (_val))
 #define WRITE_WC40_TX1_TX_DRIVERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008077, (_val))
 #define MODIFY_WC40_TX1_TX_DRIVERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008077, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Tx2
  */
 
 /* Tx analog status 0 register */
 #define READ_WC40_TX2_ANATXASTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008080, (_val))
 #define WRITE_WC40_TX2_ANATXASTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008080, (_val))
 #define MODIFY_WC40_TX2_ANATXASTATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008080, (_val), (_mask))
 
 /* Tx analog control 0 register */
 #define READ_WC40_TX2_ANATXACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008081, (_val))
 #define WRITE_WC40_TX2_ANATXACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008081, (_val))
 #define MODIFY_WC40_TX2_ANATXACONTROL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008081, (_val), (_mask))
 
 /* Tx test mux data 0 register */
 #define READ_WC40_TX2_ANATXMDATA0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008082, (_val))
 #define WRITE_WC40_TX2_ANATXMDATA0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008082, (_val))
 #define MODIFY_WC40_TX2_ANATXMDATA0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008082, (_val), (_mask))
 
 /* Tx test mux data 1 register */
 #define READ_WC40_TX2_ANATXMDATA1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008083, (_val))
 #define WRITE_WC40_TX2_ANATXMDATA1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008083, (_val))
 #define MODIFY_WC40_TX2_ANATXMDATA1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008083, (_val), (_mask))
 
 /* Tx analog status 1 register */
 #define READ_WC40_TX2_ANATXASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008084, (_val))
 #define WRITE_WC40_TX2_ANATXASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008084, (_val))
 #define MODIFY_WC40_TX2_ANATXASTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008084, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX2_ANATXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008085, (_val))
 #define WRITE_WC40_TX2_ANATXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008085, (_val))
 #define MODIFY_WC40_TX2_ANATXACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008085, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX2_ANATXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008086, (_val))
 #define WRITE_WC40_TX2_ANATXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008086, (_val))
 #define MODIFY_WC40_TX2_ANATXACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008086, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX2_TX_DRIVERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008087, (_val))
 #define WRITE_WC40_TX2_TX_DRIVERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008087, (_val))
 #define MODIFY_WC40_TX2_TX_DRIVERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008087, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Tx3
  */
 
 /* Tx analog status 0 register */
 #define READ_WC40_TX3_ANATXASTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008090, (_val))
 #define WRITE_WC40_TX3_ANATXASTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008090, (_val))
 #define MODIFY_WC40_TX3_ANATXASTATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008090, (_val), (_mask))
 
 /* Tx analog control 0 register */
 #define READ_WC40_TX3_ANATXACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008091, (_val))
 #define WRITE_WC40_TX3_ANATXACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008091, (_val))
 #define MODIFY_WC40_TX3_ANATXACONTROL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008091, (_val), (_mask))
 
 /* Tx test mux data 0 register */
 #define READ_WC40_TX3_ANATXMDATA0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008092, (_val))
 #define WRITE_WC40_TX3_ANATXMDATA0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008092, (_val))
 #define MODIFY_WC40_TX3_ANATXMDATA0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008092, (_val), (_mask))
 
 /* Tx test mux data 1 register */
 #define READ_WC40_TX3_ANATXMDATA1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008093, (_val))
 #define WRITE_WC40_TX3_ANATXMDATA1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008093, (_val))
 #define MODIFY_WC40_TX3_ANATXMDATA1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008093, (_val), (_mask))
 
 /* Tx analog status 1 register */
 #define READ_WC40_TX3_ANATXASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008094, (_val))
 #define WRITE_WC40_TX3_ANATXASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008094, (_val))
 #define MODIFY_WC40_TX3_ANATXASTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008094, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX3_ANATXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008095, (_val))
 #define WRITE_WC40_TX3_ANATXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008095, (_val))
 #define MODIFY_WC40_TX3_ANATXACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008095, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX3_ANATXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008096, (_val))
 #define WRITE_WC40_TX3_ANATXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008096, (_val))
 #define MODIFY_WC40_TX3_ANATXACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008096, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TX3_TX_DRIVERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008097, (_val))
 #define WRITE_WC40_TX3_TX_DRIVERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008097, (_val))
 #define MODIFY_WC40_TX3_TX_DRIVERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008097, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_TxB
  */
 
 /* Tx analog status 0 register */
 #define READ_WC40_TXB_ANATXASTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080a0, (_val))
 #define WRITE_WC40_TXB_ANATXASTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080a0, (_val))
 #define MODIFY_WC40_TXB_ANATXASTATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080a0, (_val), (_mask))
 
 /* Tx analog control 0 register */
 #define READ_WC40_TXB_ANATXACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080a1, (_val))
 #define WRITE_WC40_TXB_ANATXACONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080a1, (_val))
 #define MODIFY_WC40_TXB_ANATXACONTROL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080a1, (_val), (_mask))
 
 /* Tx test mux data 0 register */
 #define READ_WC40_TXB_ANATXMDATA0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080a2, (_val))
 #define WRITE_WC40_TXB_ANATXMDATA0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080a2, (_val))
 #define MODIFY_WC40_TXB_ANATXMDATA0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080a2, (_val), (_mask))
 
 /* Tx test mux data 1 register */
 #define READ_WC40_TXB_ANATXMDATA1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080a3, (_val))
 #define WRITE_WC40_TXB_ANATXMDATA1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080a3, (_val))
 #define MODIFY_WC40_TXB_ANATXMDATA1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080a3, (_val), (_mask))
 
 /* Tx analog status 1 register */
 #define READ_WC40_TXB_ANATXASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080a4, (_val))
 #define WRITE_WC40_TXB_ANATXASTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080a4, (_val))
 #define MODIFY_WC40_TXB_ANATXASTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080a4, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TXB_ANATXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080a5, (_val))
 #define WRITE_WC40_TXB_ANATXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080a5, (_val))
 #define MODIFY_WC40_TXB_ANATXACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080a5, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TXB_ANATXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080a6, (_val))
 #define WRITE_WC40_TXB_ANATXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080a6, (_val))
 #define MODIFY_WC40_TXB_ANATXACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080a6, (_val), (_mask))
 
 /* Tx reserved analog control register */
 #define READ_WC40_TXB_TX_DRIVERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080a7, (_val))
 #define WRITE_WC40_TXB_TX_DRIVERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080a7, (_val))
 #define MODIFY_WC40_TXB_TX_DRIVERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080a7, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Rx0
  */
 
 /* Rx lane status register */
 #define READ_WC40_RX0_ANARXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080b0, (_val))
 #define WRITE_WC40_RX0_ANARXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080b0, (_val))
 #define MODIFY_WC40_RX0_ANARXSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080b0, (_val), (_mask))
 
 /* Rx lane control register */
 #define READ_WC40_RX0_ANARXCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080b1, (_val))
 #define WRITE_WC40_RX0_ANARXCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080b1, (_val))
 #define MODIFY_WC40_RX0_ANARXCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080b1, (_val), (_mask))
 
 /* Rx lane control register */
 #define READ_WC40_RX0_ANARXTESTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080b8, (_val))
 #define WRITE_WC40_RX0_ANARXTESTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080b8, (_val))
 #define MODIFY_WC40_RX0_ANARXTESTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080b8, (_val), (_mask))
 
 /* Rx 1G Control register */
 #define READ_WC40_RX0_ANARXCONTROL1Gr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080b9, (_val))
 #define WRITE_WC40_RX0_ANARXCONTROL1Gr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080b9, (_val))
 #define MODIFY_WC40_RX0_ANARXCONTROL1Gr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080b9, (_val), (_mask))
 
 /* Rx PCI Control register */
 #define READ_WC40_RX0_ANARXCONTROLPCIr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080ba, (_val))
 #define WRITE_WC40_RX0_ANARXCONTROLPCIr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080ba, (_val))
 #define MODIFY_WC40_RX0_ANARXCONTROLPCIr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080ba, (_val), (_mask))
 
 /* Rx analog status register */
 #define READ_WC40_RX0_ANARXASTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080bb, (_val))
 #define WRITE_WC40_RX0_ANARXASTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080bb, (_val))
 #define MODIFY_WC40_RX0_ANARXASTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080bb, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX0_ANARXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080bc, (_val))
 #define WRITE_WC40_RX0_ANARXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080bc, (_val))
 #define MODIFY_WC40_RX0_ANARXACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080bc, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX0_ANARXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080bd, (_val))
 #define WRITE_WC40_RX0_ANARXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080bd, (_val))
 #define MODIFY_WC40_RX0_ANARXACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080bd, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX0_ANARXACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080be, (_val))
 #define WRITE_WC40_RX0_ANARXACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080be, (_val))
 #define MODIFY_WC40_RX0_ANARXACONTROL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080be, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Rx1
  */
 
 /* Rx lane status register */
 #define READ_WC40_RX1_ANARXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080c0, (_val))
 #define WRITE_WC40_RX1_ANARXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080c0, (_val))
 #define MODIFY_WC40_RX1_ANARXSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080c0, (_val), (_mask))
 
 /* Rx lane control register */
 #define READ_WC40_RX1_ANARXCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080c1, (_val))
 #define WRITE_WC40_RX1_ANARXCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080c1, (_val))
 #define MODIFY_WC40_RX1_ANARXCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080c1, (_val), (_mask))
 
 /* Rx lane control register */
 #define READ_WC40_RX1_ANARXTESTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080c8, (_val))
 #define WRITE_WC40_RX1_ANARXTESTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080c8, (_val))
 #define MODIFY_WC40_RX1_ANARXTESTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080c8, (_val), (_mask))
 
 /* Rx 1G Control register */
 #define READ_WC40_RX1_ANARXCONTROL1Gr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080c9, (_val))
 #define WRITE_WC40_RX1_ANARXCONTROL1Gr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080c9, (_val))
 #define MODIFY_WC40_RX1_ANARXCONTROL1Gr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080c9, (_val), (_mask))
 
 /* Rx PCI Control register */
 #define READ_WC40_RX1_ANARXCONTROLPCIr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080ca, (_val))
 #define WRITE_WC40_RX1_ANARXCONTROLPCIr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080ca, (_val))
 #define MODIFY_WC40_RX1_ANARXCONTROLPCIr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080ca, (_val), (_mask))
 
 /* Rx analog status register */
 #define READ_WC40_RX1_ANARXASTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080cb, (_val))
 #define WRITE_WC40_RX1_ANARXASTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080cb, (_val))
 #define MODIFY_WC40_RX1_ANARXASTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080cb, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX1_ANARXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080cc, (_val))
 #define WRITE_WC40_RX1_ANARXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080cc, (_val))
 #define MODIFY_WC40_RX1_ANARXACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080cc, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX1_ANARXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080cd, (_val))
 #define WRITE_WC40_RX1_ANARXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080cd, (_val))
 #define MODIFY_WC40_RX1_ANARXACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080cd, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX1_ANARXACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080ce, (_val))
 #define WRITE_WC40_RX1_ANARXACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080ce, (_val))
 #define MODIFY_WC40_RX1_ANARXACONTROL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080ce, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Rx2
  */
 
 /* Rx lane status register */
 #define READ_WC40_RX2_ANARXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080d0, (_val))
 #define WRITE_WC40_RX2_ANARXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080d0, (_val))
 #define MODIFY_WC40_RX2_ANARXSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080d0, (_val), (_mask))
 
 /* Rx lane control register */
 #define READ_WC40_RX2_ANARXCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080d1, (_val))
 #define WRITE_WC40_RX2_ANARXCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080d1, (_val))
 #define MODIFY_WC40_RX2_ANARXCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080d1, (_val), (_mask))
 
 /* Rx lane control register */
 #define READ_WC40_RX2_ANARXTESTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080d8, (_val))
 #define WRITE_WC40_RX2_ANARXTESTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080d8, (_val))
 #define MODIFY_WC40_RX2_ANARXTESTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080d8, (_val), (_mask))
 
 /* Rx 1G Control register */
 #define READ_WC40_RX2_ANARXCONTROL1Gr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080d9, (_val))
 #define WRITE_WC40_RX2_ANARXCONTROL1Gr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080d9, (_val))
 #define MODIFY_WC40_RX2_ANARXCONTROL1Gr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080d9, (_val), (_mask))
 
 /* Rx PCI Control register */
 #define READ_WC40_RX2_ANARXCONTROLPCIr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080da, (_val))
 #define WRITE_WC40_RX2_ANARXCONTROLPCIr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080da, (_val))
 #define MODIFY_WC40_RX2_ANARXCONTROLPCIr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080da, (_val), (_mask))
 
 /* Rx analog status register */
 #define READ_WC40_RX2_ANARXASTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080db, (_val))
 #define WRITE_WC40_RX2_ANARXASTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080db, (_val))
 #define MODIFY_WC40_RX2_ANARXASTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080db, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX2_ANARXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080dc, (_val))
 #define WRITE_WC40_RX2_ANARXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080dc, (_val))
 #define MODIFY_WC40_RX2_ANARXACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080dc, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX2_ANARXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080dd, (_val))
 #define WRITE_WC40_RX2_ANARXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080dd, (_val))
 #define MODIFY_WC40_RX2_ANARXACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080dd, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX2_ANARXACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080de, (_val))
 #define WRITE_WC40_RX2_ANARXACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080de, (_val))
 #define MODIFY_WC40_RX2_ANARXACONTROL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080de, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Rx3
  */
 
 /* Rx lane status register */
 #define READ_WC40_RX3_ANARXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080e0, (_val))
 #define WRITE_WC40_RX3_ANARXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080e0, (_val))
 #define MODIFY_WC40_RX3_ANARXSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080e0, (_val), (_mask))
 
 /* Rx lane control register */
 #define READ_WC40_RX3_ANARXCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080e1, (_val))
 #define WRITE_WC40_RX3_ANARXCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080e1, (_val))
 #define MODIFY_WC40_RX3_ANARXCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080e1, (_val), (_mask))
 
 /* Rx lane control register */
 #define READ_WC40_RX3_ANARXTESTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080e8, (_val))
 #define WRITE_WC40_RX3_ANARXTESTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080e8, (_val))
 #define MODIFY_WC40_RX3_ANARXTESTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080e8, (_val), (_mask))
 
 /* Rx 1G Control register */
 #define READ_WC40_RX3_ANARXCONTROL1Gr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080e9, (_val))
 #define WRITE_WC40_RX3_ANARXCONTROL1Gr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080e9, (_val))
 #define MODIFY_WC40_RX3_ANARXCONTROL1Gr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080e9, (_val), (_mask))
 
 /* Rx PCI Control register */
 #define READ_WC40_RX3_ANARXCONTROLPCIr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080ea, (_val))
 #define WRITE_WC40_RX3_ANARXCONTROLPCIr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080ea, (_val))
 #define MODIFY_WC40_RX3_ANARXCONTROLPCIr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080ea, (_val), (_mask))
 
 /* Rx analog status register */
 #define READ_WC40_RX3_ANARXASTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080eb, (_val))
 #define WRITE_WC40_RX3_ANARXASTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080eb, (_val))
 #define MODIFY_WC40_RX3_ANARXASTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080eb, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX3_ANARXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080ec, (_val))
 #define WRITE_WC40_RX3_ANARXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080ec, (_val))
 #define MODIFY_WC40_RX3_ANARXACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080ec, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX3_ANARXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080ed, (_val))
 #define WRITE_WC40_RX3_ANARXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080ed, (_val))
 #define MODIFY_WC40_RX3_ANARXACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080ed, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RX3_ANARXACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080ee, (_val))
 #define WRITE_WC40_RX3_ANARXACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080ee, (_val))
 #define MODIFY_WC40_RX3_ANARXACONTROL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080ee, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_RxB
  */
 
 /* Rx lane status register */
 #define READ_WC40_RXB_ANARXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080f0, (_val))
 #define WRITE_WC40_RXB_ANARXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080f0, (_val))
 #define MODIFY_WC40_RXB_ANARXSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080f0, (_val), (_mask))
 
 /* Rx lane control register */
 #define READ_WC40_RXB_ANARXCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080f1, (_val))
 #define WRITE_WC40_RXB_ANARXCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080f1, (_val))
 #define MODIFY_WC40_RXB_ANARXCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080f1, (_val), (_mask))
 
 /* Rx lane control register */
 #define READ_WC40_RXB_ANARXTESTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080f8, (_val))
 #define WRITE_WC40_RXB_ANARXTESTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080f8, (_val))
 #define MODIFY_WC40_RXB_ANARXTESTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080f8, (_val), (_mask))
 
 /* Rx 1G Control register */
 #define READ_WC40_RXB_ANARXCONTROL1Gr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080f9, (_val))
 #define WRITE_WC40_RXB_ANARXCONTROL1Gr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080f9, (_val))
 #define MODIFY_WC40_RXB_ANARXCONTROL1Gr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080f9, (_val), (_mask))
 
 /* Rx PCI Control register */
 #define READ_WC40_RXB_ANARXCONTROLPCIr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080fa, (_val))
 #define WRITE_WC40_RXB_ANARXCONTROLPCIr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080fa, (_val))
 #define MODIFY_WC40_RXB_ANARXCONTROLPCIr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080fa, (_val), (_mask))
 
 /* Rx analog status register */
 #define READ_WC40_RXB_ANARXASTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080fb, (_val))
 #define WRITE_WC40_RXB_ANARXASTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080fb, (_val))
 #define MODIFY_WC40_RXB_ANARXASTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080fb, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RXB_ANARXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080fc, (_val))
 #define WRITE_WC40_RXB_ANARXACONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080fc, (_val))
 #define MODIFY_WC40_RXB_ANARXACONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080fc, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RXB_ANARXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080fd, (_val))
 #define WRITE_WC40_RXB_ANARXACONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080fd, (_val))
 #define MODIFY_WC40_RXB_ANARXACONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080fd, (_val), (_mask))
 
 /* Rx reserved analog control register */
 #define READ_WC40_RXB_ANARXACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000080fe, (_val))
 #define WRITE_WC40_RXB_ANARXACONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000080fe, (_val))
 #define MODIFY_WC40_RXB_ANARXACONTROL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000080fe, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk2
  */
 
 /* Receiver lane swap control register */
 #define READ_WC40_XGXSBLK2_RXLNSWAPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008100, (_val))
 #define WRITE_WC40_XGXSBLK2_RXLNSWAPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008100, (_val))
 #define MODIFY_WC40_XGXSBLK2_RXLNSWAPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008100, (_val), (_mask))
 
 /* Transmit lane swap control register */
 #define READ_WC40_XGXSBLK2_TXLNSWAPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008101, (_val))
 #define WRITE_WC40_XGXSBLK2_TXLNSWAPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008101, (_val))
 #define MODIFY_WC40_XGXSBLK2_TXLNSWAPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008101, (_val), (_mask))
 
 /* ||Q|| ordered set, lanes 0 & 1 register */
 #define READ_WC40_XGXSBLK2_QSETLNS01r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008102, (_val))
 #define WRITE_WC40_XGXSBLK2_QSETLNS01r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008102, (_val))
 #define MODIFY_WC40_XGXSBLK2_QSETLNS01r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008102, (_val), (_mask))
 
 /* ||Q|| ordered set, lanes 2 & 3 register */
 #define READ_WC40_XGXSBLK2_QSETLNS23r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008103, (_val))
 #define WRITE_WC40_XGXSBLK2_QSETLNS23r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008103, (_val))
 #define MODIFY_WC40_XGXSBLK2_QSETLNS23r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008103, (_val), (_mask))
 
 /* AN 10G resolution mode control register */
 #define READ_WC40_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008104, (_val))
 #define WRITE_WC40_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008104, (_val))
 #define MODIFY_WC40_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008104, (_val), (_mask))
 
 /* Independent Combo Control register */
 #define READ_WC40_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008105, (_val))
 #define WRITE_WC40_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008105, (_val))
 #define MODIFY_WC40_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008105, (_val), (_mask))
 
 /* Test mode lane select register */
 #define READ_WC40_XGXSBLK2_TESTMODELANEr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008106, (_val))
 #define WRITE_WC40_XGXSBLK2_TESTMODELANEr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008106, (_val))
 #define MODIFY_WC40_XGXSBLK2_TESTMODELANEr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008106, (_val), (_mask))
 
 /* Test mode monitor control register */
 #define READ_WC40_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008107, (_val))
 #define WRITE_WC40_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008107, (_val))
 #define MODIFY_WC40_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008107, (_val), (_mask))
 
 /* Test mode mux control register */
 #define READ_WC40_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008108, (_val))
 #define WRITE_WC40_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008108, (_val))
 #define MODIFY_WC40_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008108, (_val), (_mask))
 
 /* 10GBASE-CX4 signal detect timeout value */
 #define READ_WC40_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008109, (_val))
 #define WRITE_WC40_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008109, (_val))
 #define MODIFY_WC40_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008109, (_val), (_mask))
 
 /* Lane reset register */
 #define READ_WC40_XGXSBLK2_LANERESETr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000810a, (_val))
 #define WRITE_WC40_XGXSBLK2_LANERESETr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000810a, (_val))
 #define MODIFY_WC40_XGXSBLK2_LANERESETr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000810a, (_val), (_mask))
 
 /* XGXS Status 6 register */
 #define READ_WC40_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000810b, (_val))
 #define WRITE_WC40_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000810b, (_val))
 #define MODIFY_WC40_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000810b, (_val), (_mask))
 
 /* A Swap 66 control 1 register */
 #define READ_WC40_XGXSBLK2_ASWAP66CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000810d, (_val))
 #define WRITE_WC40_XGXSBLK2_ASWAP66CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000810d, (_val))
 #define MODIFY_WC40_XGXSBLK2_ASWAP66CONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000810d, (_val), (_mask))
 
 /* A Swap 66 control 2 register */
 #define READ_WC40_XGXSBLK2_ASWAP66CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000810e, (_val))
 #define WRITE_WC40_XGXSBLK2_ASWAP66CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000810e, (_val))
 #define MODIFY_WC40_XGXSBLK2_ASWAP66CONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000810e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk3
  */
 
 /* In Band MDIO - local status register */
 #define READ_WC40_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008110, (_val))
 #define WRITE_WC40_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008110, (_val))
 #define MODIFY_WC40_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008110, (_val), (_mask))
 
 /* In Band MDIO - local control 0 register */
 #define READ_WC40_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008111, (_val))
 #define WRITE_WC40_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008111, (_val))
 #define MODIFY_WC40_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008111, (_val), (_mask))
 
 /* In Band MDIO - local control 1 register */
 #define READ_WC40_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008112, (_val))
 #define WRITE_WC40_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008112, (_val))
 #define MODIFY_WC40_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008112, (_val), (_mask))
 
 /* In Band MDIO - remote write ln 0 & 3 register */
 #define READ_WC40_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008113, (_val))
 #define WRITE_WC40_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008113, (_val))
 #define MODIFY_WC40_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008113, (_val), (_mask))
 
 /* In Band MDIO - remote write ln 1 & 2 register */
 #define READ_WC40_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008114, (_val))
 #define WRITE_WC40_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008114, (_val))
 #define MODIFY_WC40_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008114, (_val), (_mask))
 
 /* In Band MDIO - remote read ln 1 & 2 register */
 #define READ_WC40_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008115, (_val))
 #define WRITE_WC40_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008115, (_val))
 #define MODIFY_WC40_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008115, (_val), (_mask))
 
 /* In Band MDIO - remote read ln 0 & 3 register */
 #define READ_WC40_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008116, (_val))
 #define WRITE_WC40_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008116, (_val))
 #define MODIFY_WC40_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008116, (_val), (_mask))
 
 /* In Band MDIO - status register */
 #define READ_WC40_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008117, (_val))
 #define WRITE_WC40_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008117, (_val))
 #define MODIFY_WC40_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008117, (_val), (_mask))
 
 /* In Band MDIO - local IAC register */
 #define READ_WC40_XGXSBLK3_LOCALIACr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008118, (_val))
 #define WRITE_WC40_XGXSBLK3_LOCALIACr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008118, (_val))
 #define MODIFY_WC40_XGXSBLK3_LOCALIACr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008118, (_val), (_mask))
 
 /* In Band MDIO - remote IAC register */
 #define READ_WC40_XGXSBLK3_REMOTEIACNr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008119, (_val))
 #define WRITE_WC40_XGXSBLK3_REMOTEIACNr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008119, (_val))
 #define MODIFY_WC40_XGXSBLK3_REMOTEIACNr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008119, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk4
  */
 
 /* Miscellaneous Rx status register */
 #define READ_WC40_XGXSBLK4_MISCRXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008120, (_val))
 #define WRITE_WC40_XGXSBLK4_MISCRXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008120, (_val))
 #define MODIFY_WC40_XGXSBLK4_MISCRXSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008120, (_val), (_mask))
 
 /* XGXS status register */
 #define READ_WC40_XGXSBLK4_XGXSSTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008121, (_val))
 #define WRITE_WC40_XGXSBLK4_XGXSSTATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008121, (_val))
 #define MODIFY_WC40_XGXSBLK4_XGXSSTATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008121, (_val), (_mask))
 
 /* XGXS status 1 register */
 #define READ_WC40_XGXSBLK4_XGXSSTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008122, (_val))
 #define WRITE_WC40_XGXSBLK4_XGXSSTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008122, (_val))
 #define MODIFY_WC40_XGXSBLK4_XGXSSTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008122, (_val), (_mask))
 
 /* XGXS status 2 register */
 #define READ_WC40_XGXSBLK4_XGXSSTATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008123, (_val))
 #define WRITE_WC40_XGXSBLK4_XGXSSTATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008123, (_val))
 #define MODIFY_WC40_XGXSBLK4_XGXSSTATUS2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008123, (_val), (_mask))
 
 /* 1000X status 1 register */
 #define READ_WC40_XGXSBLK4_STATUS1000X1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008124, (_val))
 #define WRITE_WC40_XGXSBLK4_STATUS1000X1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008124, (_val))
 #define MODIFY_WC40_XGXSBLK4_STATUS1000X1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008124, (_val), (_mask))
 
 /* 1000X status 2 register */
 #define READ_WC40_XGXSBLK4_STATUS1000X2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008125, (_val))
 #define WRITE_WC40_XGXSBLK4_STATUS1000X2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008125, (_val))
 #define MODIFY_WC40_XGXSBLK4_STATUS1000X2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008125, (_val), (_mask))
 
 /* 1000X status 3 register */
 #define READ_WC40_XGXSBLK4_STATUS1000X3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008126, (_val))
 #define WRITE_WC40_XGXSBLK4_STATUS1000X3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008126, (_val))
 #define MODIFY_WC40_XGXSBLK4_STATUS1000X3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008126, (_val), (_mask))
 
 /* Test port out bits 15:0, tpout[15:0] */
 #define READ_WC40_XGXSBLK4_TPOUT_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008127, (_val))
 #define WRITE_WC40_XGXSBLK4_TPOUT_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008127, (_val))
 #define MODIFY_WC40_XGXSBLK4_TPOUT_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008127, (_val), (_mask))
 
 /* Test port out bits 23:8, tpout[23:8] */
 #define READ_WC40_XGXSBLK4_TPOUT_2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008128, (_val))
 #define WRITE_WC40_XGXSBLK4_TPOUT_2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008128, (_val))
 #define MODIFY_WC40_XGXSBLK4_TPOUT_2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008128, (_val), (_mask))
 
 /* XGXS status 3 register */
 #define READ_WC40_XGXSBLK4_XGXSSTATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008129, (_val))
 #define WRITE_WC40_XGXSBLK4_XGXSSTATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008129, (_val))
 #define MODIFY_WC40_XGXSBLK4_XGXSSTATUS3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008129, (_val), (_mask))
 
 /* 2500X status register */
 #define READ_WC40_XGXSBLK4_X2500STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000812a, (_val))
 #define WRITE_WC40_XGXSBLK4_X2500STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000812a, (_val))
 #define MODIFY_WC40_XGXSBLK4_X2500STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000812a, (_val), (_mask))
 
 /* CL73 AN status 1 register */
 #define READ_WC40_XGXSBLK4_TOPANSTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000812b, (_val))
 #define WRITE_WC40_XGXSBLK4_TOPANSTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000812b, (_val))
 #define MODIFY_WC40_XGXSBLK4_TOPANSTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000812b, (_val), (_mask))
 
 /* AN link partner user page 1 */
 #define READ_WC40_XGXSBLK4_LP_UP1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000812c, (_val))
 #define WRITE_WC40_XGXSBLK4_LP_UP1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000812c, (_val))
 #define MODIFY_WC40_XGXSBLK4_LP_UP1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000812c, (_val), (_mask))
 
 /* AN link partner user page 2 */
 #define READ_WC40_XGXSBLK4_LP_UP2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000812d, (_val))
 #define WRITE_WC40_XGXSBLK4_LP_UP2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000812d, (_val))
 #define MODIFY_WC40_XGXSBLK4_LP_UP2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000812d, (_val), (_mask))
 
 /* AN link partner user page 3 */
 #define READ_WC40_XGXSBLK4_LP_UP3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000812e, (_val))
 #define WRITE_WC40_XGXSBLK4_LP_UP3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000812e, (_val))
 #define MODIFY_WC40_XGXSBLK4_LP_UP3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000812e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk5
  */
 
 /* 10G parallel detect status register */
 #define READ_WC40_XGXSBLK5_PARDET10GSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008130, (_val))
 #define WRITE_WC40_XGXSBLK5_PARDET10GSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008130, (_val))
 #define MODIFY_WC40_XGXSBLK5_PARDET10GSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008130, (_val), (_mask))
 
 /* 10G parallel detect control register */
 #define READ_WC40_XGXSBLK5_PARDET10GCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008131, (_val))
 #define WRITE_WC40_XGXSBLK5_PARDET10GCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008131, (_val))
 #define MODIFY_WC40_XGXSBLK5_PARDET10GCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008131, (_val), (_mask))
 
 /* 10G parallel detect signal detect register */
 #define READ_WC40_XGXSBLK5_PARDET10GSIGDETr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008132, (_val))
 #define WRITE_WC40_XGXSBLK5_PARDET10GSIGDETr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008132, (_val))
 #define MODIFY_WC40_XGXSBLK5_PARDET10GSIGDETr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008132, (_val), (_mask))
 
 /* 10G parallel detect link register */
 #define READ_WC40_XGXSBLK5_PARDET10GLINKr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008133, (_val))
 #define WRITE_WC40_XGXSBLK5_PARDET10GLINKr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008133, (_val))
 #define MODIFY_WC40_XGXSBLK5_PARDET10GLINKr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008133, (_val), (_mask))
 
 /* 10G parallel detect lost link register */
 #define READ_WC40_XGXSBLK5_PARDET10GLOSTLINKr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008134, (_val))
 #define WRITE_WC40_XGXSBLK5_PARDET10GLOSTLINKr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008134, (_val))
 #define MODIFY_WC40_XGXSBLK5_PARDET10GLOSTLINKr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008134, (_val), (_mask))
 
 /* Clause 73 auto-negotiation control register 1 */
 #define READ_WC40_XGXSBLK5_CL73CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008135, (_val))
 #define WRITE_WC40_XGXSBLK5_CL73CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008135, (_val))
 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008135, (_val), (_mask))
 
 /* Clause 73 auto-negotiation control register 2 */
 #define READ_WC40_XGXSBLK5_CL73CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008136, (_val))
 #define WRITE_WC40_XGXSBLK5_CL73CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008136, (_val))
 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008136, (_val), (_mask))
 
 /* Clause 73 auto-negotiation control register 3 */
 #define READ_WC40_XGXSBLK5_CL73CONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008137, (_val))
 #define WRITE_WC40_XGXSBLK5_CL73CONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008137, (_val))
 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008137, (_val), (_mask))
 
 /* Clause 73 auto-negotiation control register 4 */
 #define READ_WC40_XGXSBLK5_CL73CONTROL4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008138, (_val))
 #define WRITE_WC40_XGXSBLK5_CL73CONTROL4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008138, (_val))
 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008138, (_val), (_mask))
 
 /* Clause 73 auto-negotiation control register 5 */
 #define READ_WC40_XGXSBLK5_CL73CONTROL5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008139, (_val))
 #define WRITE_WC40_XGXSBLK5_CL73CONTROL5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008139, (_val))
 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008139, (_val), (_mask))
 
 /* Clause 73 auto-negotiation control register 6 */
 #define READ_WC40_XGXSBLK5_CL73CONTROL6r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000813a, (_val))
 #define WRITE_WC40_XGXSBLK5_CL73CONTROL6r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000813a, (_val))
 #define MODIFY_WC40_XGXSBLK5_CL73CONTROL6r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000813a, (_val), (_mask))
 
 /* Clause 73 auto-negotiation DME Timers Register */
 #define READ_WC40_XGXSBLK5_CL73DMETMRSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000813b, (_val))
 #define WRITE_WC40_XGXSBLK5_CL73DMETMRSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000813b, (_val))
 #define MODIFY_WC40_XGXSBLK5_CL73DMETMRSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000813b, (_val), (_mask))
 
 /* XGXS Status 4 Register */
 #define READ_WC40_XGXSBLK5_XGXSSTATUS4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000813c, (_val))
 #define WRITE_WC40_XGXSBLK5_XGXSSTATUS4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000813c, (_val))
 #define MODIFY_WC40_XGXSBLK5_XGXSSTATUS4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000813c, (_val), (_mask))
 
 /* XGXS Status 5 Register */
 #define READ_WC40_XGXSBLK5_XGXSSTATUS5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000813d, (_val))
 #define WRITE_WC40_XGXSBLK5_XGXSSTATUS5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000813d, (_val))
 #define MODIFY_WC40_XGXSBLK5_XGXSSTATUS5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000813d, (_val), (_mask))
 
 /* 10G parallel detect control 2 register */
 #define READ_WC40_XGXSBLK5_PARDET10GCONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000813e, (_val))
 #define WRITE_WC40_XGXSBLK5_PARDET10GCONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000813e, (_val))
 #define MODIFY_WC40_XGXSBLK5_PARDET10GCONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000813e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk6
  */
 
 /* Dual-XGXS Control1 register */
 #define READ_WC40_XGXSBLK6_XGXSX2CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008140, (_val))
 #define WRITE_WC40_XGXSBLK6_XGXSX2CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008140, (_val))
 #define MODIFY_WC40_XGXSBLK6_XGXSX2CONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008140, (_val), (_mask))
 
 /* Dual-XGXS Control2 register */
 #define READ_WC40_XGXSBLK6_XGXSX2CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008141, (_val))
 #define WRITE_WC40_XGXSBLK6_XGXSX2CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008141, (_val))
 #define MODIFY_WC40_XGXSBLK6_XGXSX2CONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008141, (_val), (_mask))
 
 /* Dual-XGXS Test1 register */
 #define READ_WC40_XGXSBLK6_XGXSX2TEST1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008143, (_val))
 #define WRITE_WC40_XGXSBLK6_XGXSX2TEST1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008143, (_val))
 #define MODIFY_WC40_XGXSBLK6_XGXSX2TEST1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008143, (_val), (_mask))
 
 /* Dual-XGXS Status1 register */
 #define READ_WC40_XGXSBLK6_XGXSX2STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008144, (_val))
 #define WRITE_WC40_XGXSBLK6_XGXSX2STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008144, (_val))
 #define MODIFY_WC40_XGXSBLK6_XGXSX2STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008144, (_val), (_mask))
 
 /* BPM Control register */
 #define READ_WC40_XGXSBLK6_BPMCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008147, (_val))
 #define WRITE_WC40_XGXSBLK6_BPMCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008147, (_val))
 #define MODIFY_WC40_XGXSBLK6_BPMCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008147, (_val), (_mask))
 
 /* BPM Status register */
 #define READ_WC40_XGXSBLK6_BPMSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008148, (_val))
 #define WRITE_WC40_XGXSBLK6_BPMSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008148, (_val))
 #define MODIFY_WC40_XGXSBLK6_BPMSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008148, (_val), (_mask))
 
 /* BPM 10G Timer register */
 #define READ_WC40_XGXSBLK6_BPM10GTIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008149, (_val))
 #define WRITE_WC40_XGXSBLK6_BPM10GTIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008149, (_val))
 #define MODIFY_WC40_XGXSBLK6_BPM10GTIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008149, (_val), (_mask))
 
 /* BPM 1G Timer register */
 #define READ_WC40_XGXSBLK6_BPM1GTIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000814a, (_val))
 #define WRITE_WC40_XGXSBLK6_BPM1GTIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000814a, (_val))
 #define MODIFY_WC40_XGXSBLK6_BPM1GTIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000814a, (_val), (_mask))
 
 /* BPM Tx Disable Timer register */
 #define READ_WC40_XGXSBLK6_BPMTXDISTIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000814b, (_val))
 #define WRITE_WC40_XGXSBLK6_BPMTXDISTIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000814b, (_val))
 #define MODIFY_WC40_XGXSBLK6_BPMTXDISTIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000814b, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk7
  */
 
 /* Cl48 PCS EEE Control register */
 #define READ_WC40_XGXSBLK7_EEECONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008150, (_val))
 #define WRITE_WC40_XGXSBLK7_EEECONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008150, (_val))
 #define MODIFY_WC40_XGXSBLK7_EEECONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008150, (_val), (_mask))
 
 /* Cl48 PCS EEE status regsiter */
 #define READ_WC40_XGXSBLK7_EEESTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008151, (_val))
 #define WRITE_WC40_XGXSBLK7_EEESTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008151, (_val))
 #define MODIFY_WC40_XGXSBLK7_EEESTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008151, (_val), (_mask))
 
 /* XGMII Low power Idle chracter register */
 #define READ_WC40_XGXSBLK7_XGMIILPIr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008152, (_val))
 #define WRITE_WC40_XGXSBLK7_XGMIILPIr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008152, (_val))
 #define MODIFY_WC40_XGXSBLK7_XGMIILPIr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008152, (_val), (_mask))
 
 /* LPI character for lanes1-3 at Rx xgmii interface */
 #define READ_WC40_XGXSBLK7_LPILANE13r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008153, (_val))
 #define WRITE_WC40_XGXSBLK7_LPILANE13r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008153, (_val))
 #define MODIFY_WC40_XGXSBLK7_LPILANE13r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008153, (_val), (_mask))
 
 /* Lane1 character for reserved Q order set */
 #define READ_WC40_XGXSBLK7_QRSVD1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008154, (_val))
 #define WRITE_WC40_XGXSBLK7_QRSVD1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008154, (_val))
 #define MODIFY_WC40_XGXSBLK7_QRSVD1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008154, (_val), (_mask))
 
 /* Lane2 and 3 characters for reserved Q order set */
 #define READ_WC40_XGXSBLK7_QRSVD23r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008155, (_val))
 #define WRITE_WC40_XGXSBLK7_QRSVD23r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008155, (_val))
 #define MODIFY_WC40_XGXSBLK7_QRSVD23r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008155, (_val), (_mask))
 
 /* Reserved Q order set swap control register */
 #define READ_WC40_XGXSBLK7_QRSVDSWAPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008156, (_val))
 #define WRITE_WC40_XGXSBLK7_QRSVDSWAPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008156, (_val))
 #define MODIFY_WC40_XGXSBLK7_QRSVDSWAPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008156, (_val), (_mask))
 
 /* Reserved Q order set status regsiter */
 #define READ_WC40_XGXSBLK7_QRSVDSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008157, (_val))
 #define WRITE_WC40_XGXSBLK7_QRSVDSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008157, (_val))
 #define MODIFY_WC40_XGXSBLK7_QRSVDSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008157, (_val), (_mask))
 
 /* Cl48 Tx lpi fsm status register */
 #define READ_WC40_XGXSBLK7_CL48_TX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008158, (_val))
 #define WRITE_WC40_XGXSBLK7_CL48_TX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008158, (_val))
 #define MODIFY_WC40_XGXSBLK7_CL48_TX_LPI_SMr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008158, (_val), (_mask))
 
 /* Cl48 Rx lpi fsm status register */
 #define READ_WC40_XGXSBLK7_CL48_RX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008159, (_val))
 #define WRITE_WC40_XGXSBLK7_CL48_RX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008159, (_val))
 #define MODIFY_WC40_XGXSBLK7_CL48_RX_LPI_SMr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008159, (_val), (_mask))
 
 /* 10G FIFO control register */
 #define READ_WC40_XGXSBLK7_FIFO_CTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000815d, (_val))
 #define WRITE_WC40_XGXSBLK7_FIFO_CTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000815d, (_val))
 #define MODIFY_WC40_XGXSBLK7_FIFO_CTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000815d, (_val), (_mask))
 
 /* 10G FIFO status register */
 #define READ_WC40_XGXSBLK7_FIFO_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000815e, (_val))
 #define WRITE_WC40_XGXSBLK7_FIFO_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000815e, (_val))
 #define MODIFY_WC40_XGXSBLK7_FIFO_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000815e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk8
  */
 
 /* CL73 Control 7 Register */
 #define READ_WC40_XGXSBLK8_CL73CONTROL7r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008160, (_val))
 #define WRITE_WC40_XGXSBLK8_CL73CONTROL7r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008160, (_val))
 #define MODIFY_WC40_XGXSBLK8_CL73CONTROL7r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008160, (_val), (_mask))
 
 /* CL73 Control 8 Register */
 #define READ_WC40_XGXSBLK8_CL73CONTROL8r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008161, (_val))
 #define WRITE_WC40_XGXSBLK8_CL73CONTROL8r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008161, (_val))
 #define MODIFY_WC40_XGXSBLK8_CL73CONTROL8r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008161, (_val), (_mask))
 
 /* CL73 Control 9 Register */
 #define READ_WC40_XGXSBLK8_CL73CONTROL9r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008162, (_val))
 #define WRITE_WC40_XGXSBLK8_CL73CONTROL9r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008162, (_val))
 #define MODIFY_WC40_XGXSBLK8_CL73CONTROL9r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008162, (_val), (_mask))
 
 /* CL73 Control 10 Register */
 #define READ_WC40_XGXSBLK8_CL73CONTROL10r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008163, (_val))
 #define WRITE_WC40_XGXSBLK8_CL73CONTROL10r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008163, (_val))
 #define MODIFY_WC40_XGXSBLK8_CL73CONTROL10r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008163, (_val), (_mask))
 
 /* TX Phase interpolator Control 1 Register */
 #define READ_WC40_XGXSBLK8_TX_PI_CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008164, (_val))
 #define WRITE_WC40_XGXSBLK8_TX_PI_CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008164, (_val))
 #define MODIFY_WC40_XGXSBLK8_TX_PI_CONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008164, (_val), (_mask))
 
 /* TX Phase interpolator Control 2 Register */
 #define READ_WC40_XGXSBLK8_TX_PI_CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008165, (_val))
 #define WRITE_WC40_XGXSBLK8_TX_PI_CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008165, (_val))
 #define MODIFY_WC40_XGXSBLK8_TX_PI_CONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008165, (_val), (_mask))
 
 /* TX Phase interpolator Control 3 Register */
 #define READ_WC40_XGXSBLK8_TX_PI_CONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008166, (_val))
 #define WRITE_WC40_XGXSBLK8_TX_PI_CONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008166, (_val))
 #define MODIFY_WC40_XGXSBLK8_TX_PI_CONTROL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008166, (_val), (_mask))
 
 /* TX Phase interpolator Status 1 Register */
 #define READ_WC40_XGXSBLK8_TX_PI_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008167, (_val))
 #define WRITE_WC40_XGXSBLK8_TX_PI_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008167, (_val))
 #define MODIFY_WC40_XGXSBLK8_TX_PI_STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008167, (_val), (_mask))
 
 /* TX Phase interpolator Status 2 Register */
 #define READ_WC40_XGXSBLK8_TX_PI_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008168, (_val))
 #define WRITE_WC40_XGXSBLK8_TX_PI_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008168, (_val))
 #define MODIFY_WC40_XGXSBLK8_TX_PI_STATUS2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008168, (_val), (_mask))
 
 /* TX Lane Swap Control 1 Register */
 #define READ_WC40_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008169, (_val))
 #define WRITE_WC40_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008169, (_val))
 #define MODIFY_WC40_XGXSBLK8_TXLNSWAP1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008169, (_val), (_mask))
 
 /* TX Lane Swap Control 2 Register */
 #define READ_WC40_XGXSBLK8_TXLNSWAP2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000816a, (_val))
 #define WRITE_WC40_XGXSBLK8_TXLNSWAP2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000816a, (_val))
 #define MODIFY_WC40_XGXSBLK8_TXLNSWAP2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000816a, (_val), (_mask))
 
 /* RX Lane Swap Control 1 Register */
 #define READ_WC40_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000816b, (_val))
 #define WRITE_WC40_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000816b, (_val))
 #define MODIFY_WC40_XGXSBLK8_RXLNSWAP1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000816b, (_val), (_mask))
 
 /* RX Lane Swap Control 2 Register */
 #define READ_WC40_XGXSBLK8_RXLNSWAP2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000816c, (_val))
 #define WRITE_WC40_XGXSBLK8_RXLNSWAP2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000816c, (_val))
 #define MODIFY_WC40_XGXSBLK8_RXLNSWAP2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000816c, (_val), (_mask))
 
 /* Temp Sensor 1 Register */
 #define READ_WC40_XGXSBLK8_TEMP_SENSOR1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000816d, (_val))
 #define WRITE_WC40_XGXSBLK8_TEMP_SENSOR1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000816d, (_val))
 #define MODIFY_WC40_XGXSBLK8_TEMP_SENSOR1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000816d, (_val), (_mask))
 
 /* Temp Sensor 2 Register */
 #define READ_WC40_XGXSBLK8_TEMP_SENSOR2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000816e, (_val))
 #define WRITE_WC40_XGXSBLK8_TEMP_SENSOR2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000816e, (_val))
 #define MODIFY_WC40_XGXSBLK8_TEMP_SENSOR2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000816e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk9
  */
 
 /* R2 control register */
 #define READ_WC40_XGXSBLK9_R2_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008170, (_val))
 #define WRITE_WC40_XGXSBLK9_R2_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008170, (_val))
 #define MODIFY_WC40_XGXSBLK9_R2_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008170, (_val), (_mask))
 
 /* R2 status register */
 #define READ_WC40_XGXSBLK9_R2_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008171, (_val))
 #define WRITE_WC40_XGXSBLK9_R2_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008171, (_val))
 #define MODIFY_WC40_XGXSBLK9_R2_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008171, (_val), (_mask))
 
 /* R2 deskew control register */
 #define READ_WC40_XGXSBLK9_R2_DESKEW_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008172, (_val))
 #define WRITE_WC40_XGXSBLK9_R2_DESKEW_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008172, (_val))
 #define MODIFY_WC40_XGXSBLK9_R2_DESKEW_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008172, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk10
  */
 
 /* TX Phase interpolator Control 4 Register */
 #define READ_WC40_XGXSBLK10_TX_PI_CONTROL4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008190, (_val))
 #define WRITE_WC40_XGXSBLK10_TX_PI_CONTROL4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008190, (_val))
 #define MODIFY_WC40_XGXSBLK10_TX_PI_CONTROL4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008190, (_val), (_mask))
 
 /* XFI AFE Control1 Register */
 #define READ_WC40_XGXSBLK10_XFI_AFE_CTL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008191, (_val))
 #define WRITE_WC40_XGXSBLK10_XFI_AFE_CTL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008191, (_val))
 #define MODIFY_WC40_XGXSBLK10_XFI_AFE_CTL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008191, (_val), (_mask))
 
 /* XFI AFE Control2 Registe */
 #define READ_WC40_XGXSBLK10_XFI_AFE_CTL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008192, (_val))
 #define WRITE_WC40_XGXSBLK10_XFI_AFE_CTL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008192, (_val))
 #define MODIFY_WC40_XGXSBLK10_XFI_AFE_CTL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008192, (_val), (_mask))
 
 /* XFI AFE ACJTAG value Register */
 #define READ_WC40_XGXSBLK10_XFI_AFE_ACJVALr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008193, (_val))
 #define WRITE_WC40_XGXSBLK10_XFI_AFE_ACJVALr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008193, (_val))
 #define MODIFY_WC40_XGXSBLK10_XFI_AFE_ACJVALr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008193, (_val), (_mask))
 
 /* TX Phase interpolator Status 3 Register */
 #define READ_WC40_XGXSBLK10_TX_PI_STATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008194, (_val))
 #define WRITE_WC40_XGXSBLK10_TX_PI_STATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008194, (_val))
 #define MODIFY_WC40_XGXSBLK10_TX_PI_STATUS3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008194, (_val), (_mask))
 
 /* TX Phase interpolator Status 4 Register */
 #define READ_WC40_XGXSBLK10_TX_PI_STATUS4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008195, (_val))
 #define WRITE_WC40_XGXSBLK10_TX_PI_STATUS4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008195, (_val))
 #define MODIFY_WC40_XGXSBLK10_TX_PI_STATUS4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008195, (_val), (_mask))
 
 /* TX Phase interpolator Control 5 Register */
 #define READ_WC40_XGXSBLK10_TX_PI_CONTROL5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008196, (_val))
 #define WRITE_WC40_XGXSBLK10_TX_PI_CONTROL5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008196, (_val))
 #define MODIFY_WC40_XGXSBLK10_TX_PI_CONTROL5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008196, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_GP2_reg
  */
 
 /* GP2 status 0 register */
 #define READ_WC40_GP2_REG_GP2_0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081d0, (_val))
 #define WRITE_WC40_GP2_REG_GP2_0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081d0, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081d0, (_val), (_mask))
 
 /* GP2 status 1 register */
 #define READ_WC40_GP2_REG_GP2_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081d1, (_val))
 #define WRITE_WC40_GP2_REG_GP2_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081d1, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081d1, (_val), (_mask))
 
 /* GP2 status 2 register */
 #define READ_WC40_GP2_REG_GP2_2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081d2, (_val))
 #define WRITE_WC40_GP2_REG_GP2_2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081d2, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081d2, (_val), (_mask))
 
 /* GP2 status 3 register */
 #define READ_WC40_GP2_REG_GP2_3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081d3, (_val))
 #define WRITE_WC40_GP2_REG_GP2_3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081d3, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081d3, (_val), (_mask))
 
 /* GP2 status 4 register */
 #define READ_WC40_GP2_REG_GP2_4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081d4, (_val))
 #define WRITE_WC40_GP2_REG_GP2_4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081d4, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081d4, (_val), (_mask))
 
 /* GP2 status 5 register */
 #define READ_WC40_GP2_REG_GP2_5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081d5, (_val))
 #define WRITE_WC40_GP2_REG_GP2_5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081d5, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081d5, (_val), (_mask))
 
 /* GP2 status 6 register */
 #define READ_WC40_GP2_REG_GP2_6r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081d6, (_val))
 #define WRITE_WC40_GP2_REG_GP2_6r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081d6, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_6r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081d6, (_val), (_mask))
 
 /* GP2 status 7 register */
 #define READ_WC40_GP2_REG_GP2_7r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081d7, (_val))
 #define WRITE_WC40_GP2_REG_GP2_7r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081d7, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_7r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081d7, (_val), (_mask))
 
 /* GP2 status 8 register */
 #define READ_WC40_GP2_REG_GP2_8r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081d8, (_val))
 #define WRITE_WC40_GP2_REG_GP2_8r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081d8, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_8r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081d8, (_val), (_mask))
 
 /* GP2 status 9 register */
 #define READ_WC40_GP2_REG_GP2_9r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081d9, (_val))
 #define WRITE_WC40_GP2_REG_GP2_9r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081d9, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_9r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081d9, (_val), (_mask))
 
 /* GP2 status A register */
 #define READ_WC40_GP2_REG_GP2_Ar(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081da, (_val))
 #define WRITE_WC40_GP2_REG_GP2_Ar(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081da, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_Ar(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081da, (_val), (_mask))
 
 /* GP2 status B register */
 #define READ_WC40_GP2_REG_GP2_Br(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081db, (_val))
 #define WRITE_WC40_GP2_REG_GP2_Br(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081db, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_Br(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081db, (_val), (_mask))
 
 /* GP2 status C register */
 #define READ_WC40_GP2_REG_GP2_Cr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081dc, (_val))
 #define WRITE_WC40_GP2_REG_GP2_Cr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081dc, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_Cr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081dc, (_val), (_mask))
 
 /* GP2 status D register */
 #define READ_WC40_GP2_REG_GP2_Dr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081dd, (_val))
 #define WRITE_WC40_GP2_REG_GP2_Dr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081dd, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_Dr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081dd, (_val), (_mask))
 
 /* GP2 status E register */
 #define READ_WC40_GP2_REG_GP2_Er(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081de, (_val))
 #define WRITE_WC40_GP2_REG_GP2_Er(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081de, (_val))
 #define MODIFY_WC40_GP2_REG_GP2_Er(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081de, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_uC_info_B0
  */
 
 /* Micro-controller Tuning State Debug for LN0 */
 #define READ_WC40_UC_INFO_B0_STATE_DEBUG_LN0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081e0, (_val))
 #define WRITE_WC40_UC_INFO_B0_STATE_DEBUG_LN0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081e0, (_val))
 #define MODIFY_WC40_UC_INFO_B0_STATE_DEBUG_LN0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081e0, (_val), (_mask))
 
 /* Micro-controller Tuning State Debug for LN1 */
 #define READ_WC40_UC_INFO_B0_STATE_DEBUG_LN1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081e1, (_val))
 #define WRITE_WC40_UC_INFO_B0_STATE_DEBUG_LN1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081e1, (_val))
 #define MODIFY_WC40_UC_INFO_B0_STATE_DEBUG_LN1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081e1, (_val), (_mask))
 
 /* Micro-controller Tuning State Debug for LN2 */
 #define READ_WC40_UC_INFO_B0_STATE_DEBUG_LN2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081e2, (_val))
 #define WRITE_WC40_UC_INFO_B0_STATE_DEBUG_LN2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081e2, (_val))
 #define MODIFY_WC40_UC_INFO_B0_STATE_DEBUG_LN2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081e2, (_val), (_mask))
 
 /* Micro-controller Tuning State Debug for LN3 */
 #define READ_WC40_UC_INFO_B0_STATE_DEBUG_LN3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081e3, (_val))
 #define WRITE_WC40_UC_INFO_B0_STATE_DEBUG_LN3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081e3, (_val))
 #define MODIFY_WC40_UC_INFO_B0_STATE_DEBUG_LN3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081e3, (_val), (_mask))
 
 /* Micro-controller Speed/Mode Debug for LN0 */
 #define READ_WC40_UC_INFO_B0_SPEED_DEBUG_LN0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081e4, (_val))
 #define WRITE_WC40_UC_INFO_B0_SPEED_DEBUG_LN0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081e4, (_val))
 #define MODIFY_WC40_UC_INFO_B0_SPEED_DEBUG_LN0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081e4, (_val), (_mask))
 
 /* Micro-controller Speed/Mode Debug for LN1 */
 #define READ_WC40_UC_INFO_B0_SPEED_DEBUG_LN1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081e5, (_val))
 #define WRITE_WC40_UC_INFO_B0_SPEED_DEBUG_LN1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081e5, (_val))
 #define MODIFY_WC40_UC_INFO_B0_SPEED_DEBUG_LN1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081e5, (_val), (_mask))
 
 /* Micro-controller Speed/Mode Debug for LN2 */
 #define READ_WC40_UC_INFO_B0_SPEED_DEBUG_LN2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081e6, (_val))
 #define WRITE_WC40_UC_INFO_B0_SPEED_DEBUG_LN2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081e6, (_val))
 #define MODIFY_WC40_UC_INFO_B0_SPEED_DEBUG_LN2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081e6, (_val), (_mask))
 
 /* Micro-controller Speed/Mode Debug for LN3 */
 #define READ_WC40_UC_INFO_B0_SPEED_DEBUG_LN3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081e7, (_val))
 #define WRITE_WC40_UC_INFO_B0_SPEED_DEBUG_LN3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081e7, (_val))
 #define MODIFY_WC40_UC_INFO_B0_SPEED_DEBUG_LN3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081e7, (_val), (_mask))
 
 /* Micro-controller CL72 Status for LN0 */
 #define READ_WC40_UC_INFO_B0_CL72_STATUS_LN0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081e8, (_val))
 #define WRITE_WC40_UC_INFO_B0_CL72_STATUS_LN0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081e8, (_val))
 #define MODIFY_WC40_UC_INFO_B0_CL72_STATUS_LN0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081e8, (_val), (_mask))
 
 /* Micro-controller CL72 Status for LN1 */
 #define READ_WC40_UC_INFO_B0_CL72_STATUS_LN1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081e9, (_val))
 #define WRITE_WC40_UC_INFO_B0_CL72_STATUS_LN1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081e9, (_val))
 #define MODIFY_WC40_UC_INFO_B0_CL72_STATUS_LN1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081e9, (_val), (_mask))
 
 /* Micro-controller CL72 Status for LN2 */
 #define READ_WC40_UC_INFO_B0_CL72_STATUS_LN2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081ea, (_val))
 #define WRITE_WC40_UC_INFO_B0_CL72_STATUS_LN2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081ea, (_val))
 #define MODIFY_WC40_UC_INFO_B0_CL72_STATUS_LN2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081ea, (_val), (_mask))
 
 /* Micro-controller CL72 Status for LN3 */
 #define READ_WC40_UC_INFO_B0_CL72_STATUS_LN3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081eb, (_val))
 #define WRITE_WC40_UC_INFO_B0_CL72_STATUS_LN3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081eb, (_val))
 #define MODIFY_WC40_UC_INFO_B0_CL72_STATUS_LN3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081eb, (_val), (_mask))
 
 /* Micro-controller Debug Register0 */
 #define READ_WC40_UC_INFO_B0_DEBUG_REG0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081ec, (_val))
 #define WRITE_WC40_UC_INFO_B0_DEBUG_REG0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081ec, (_val))
 #define MODIFY_WC40_UC_INFO_B0_DEBUG_REG0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081ec, (_val), (_mask))
 
 /* Micro-controller Debug Register1 */
 #define READ_WC40_UC_INFO_B0_DEBUG_REG1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081ed, (_val))
 #define WRITE_WC40_UC_INFO_B0_DEBUG_REG1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081ed, (_val))
 #define MODIFY_WC40_UC_INFO_B0_DEBUG_REG1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081ed, (_val), (_mask))
 
 /* Micro-controller Dead-Trap Register */
 #define READ_WC40_UC_INFO_B0_DEAD_TRAPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081ee, (_val))
 #define WRITE_WC40_UC_INFO_B0_DEAD_TRAPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081ee, (_val))
 #define MODIFY_WC40_UC_INFO_B0_DEAD_TRAPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081ee, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_uC_info_B1
  */
 
 /* Micro-controller Version Register */
 #define READ_WC40_UC_INFO_B1_VERSIONr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081f0, (_val))
 #define WRITE_WC40_UC_INFO_B1_VERSIONr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081f0, (_val))
 #define MODIFY_WC40_UC_INFO_B1_VERSIONr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081f0, (_val), (_mask))
 
 /* Micro-controller Target Register */
 #define READ_WC40_UC_INFO_B1_TARGETr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081f1, (_val))
 #define WRITE_WC40_UC_INFO_B1_TARGETr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081f1, (_val))
 #define MODIFY_WC40_UC_INFO_B1_TARGETr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081f1, (_val), (_mask))
 
 /* Micro-controller firmware_mode 2_2 Register */
 #define READ_WC40_UC_INFO_B1_FIRMWARE_MODEr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081f2, (_val))
 #define WRITE_WC40_UC_INFO_B1_FIRMWARE_MODEr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081f2, (_val))
 #define MODIFY_WC40_UC_INFO_B1_FIRMWARE_MODEr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081f2, (_val), (_mask))
 
 /* Micro-controller LN0 GPIO Control Register */
 #define READ_WC40_UC_INFO_B1_GPIO_CTRL_LN0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081f3, (_val))
 #define WRITE_WC40_UC_INFO_B1_GPIO_CTRL_LN0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081f3, (_val))
 #define MODIFY_WC40_UC_INFO_B1_GPIO_CTRL_LN0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081f3, (_val), (_mask))
 
 /* Micro-controller LN1 GPIO Control Register */
 #define READ_WC40_UC_INFO_B1_GPIO_CTRL_LN1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081f4, (_val))
 #define WRITE_WC40_UC_INFO_B1_GPIO_CTRL_LN1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081f4, (_val))
 #define MODIFY_WC40_UC_INFO_B1_GPIO_CTRL_LN1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081f4, (_val), (_mask))
 
 /* Micro-controller LN2 GPIO Control Register */
 #define READ_WC40_UC_INFO_B1_GPIO_CTRL_LN2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081f5, (_val))
 #define WRITE_WC40_UC_INFO_B1_GPIO_CTRL_LN2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081f5, (_val))
 #define MODIFY_WC40_UC_INFO_B1_GPIO_CTRL_LN2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081f5, (_val), (_mask))
 
 /* Micro-controller LN3 GPIO Control Register */
 #define READ_WC40_UC_INFO_B1_GPIO_CTRL_LN3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081f6, (_val))
 #define WRITE_WC40_UC_INFO_B1_GPIO_CTRL_LN3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081f6, (_val))
 #define MODIFY_WC40_UC_INFO_B1_GPIO_CTRL_LN3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081f6, (_val), (_mask))
 
 /* Micro-controller LN0 GPIO Status Register */
 #define READ_WC40_UC_INFO_B1_GPIO_STS_LN0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081f7, (_val))
 #define WRITE_WC40_UC_INFO_B1_GPIO_STS_LN0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081f7, (_val))
 #define MODIFY_WC40_UC_INFO_B1_GPIO_STS_LN0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081f7, (_val), (_mask))
 
 /* Micro-controller LN1 GPIO Status Register */
 #define READ_WC40_UC_INFO_B1_GPIO_STS_LN1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081f8, (_val))
 #define WRITE_WC40_UC_INFO_B1_GPIO_STS_LN1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081f8, (_val))
 #define MODIFY_WC40_UC_INFO_B1_GPIO_STS_LN1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081f8, (_val), (_mask))
 
 /* Micro-controller LN2 GPIO Status Register */
 #define READ_WC40_UC_INFO_B1_GPIO_STS_LN2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081f9, (_val))
 #define WRITE_WC40_UC_INFO_B1_GPIO_STS_LN2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081f9, (_val))
 #define MODIFY_WC40_UC_INFO_B1_GPIO_STS_LN2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081f9, (_val), (_mask))
 
 /* Micro-controller LN3 GPIO Status Register */
 #define READ_WC40_UC_INFO_B1_GPIO_STS_LN3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081fa, (_val))
 #define WRITE_WC40_UC_INFO_B1_GPIO_STS_LN3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081fa, (_val))
 #define MODIFY_WC40_UC_INFO_B1_GPIO_STS_LN3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081fa, (_val), (_mask))
 
 /* Micro Temp 2_B Register */
 #define READ_WC40_UC_INFO_B1_REGBr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081fb, (_val))
 #define WRITE_WC40_UC_INFO_B1_REGBr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081fb, (_val))
 #define MODIFY_WC40_UC_INFO_B1_REGBr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081fb, (_val), (_mask))
 
 /* Micro Tuning states Bypass Register */
 #define READ_WC40_UC_INFO_B1_TUNING_STATE_BYPASSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081fc, (_val))
 #define WRITE_WC40_UC_INFO_B1_TUNING_STATE_BYPASSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081fc, (_val))
 #define MODIFY_WC40_UC_INFO_B1_TUNING_STATE_BYPASSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081fc, (_val), (_mask))
 
 /* Die-Temperature Register */
 #define READ_WC40_UC_INFO_B1_TEMPERATUREr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081fd, (_val))
 #define WRITE_WC40_UC_INFO_B1_TEMPERATUREr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081fd, (_val))
 #define MODIFY_WC40_UC_INFO_B1_TEMPERATUREr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081fd, (_val), (_mask))
 
 /* Micro-controller code-ram crc Register */
 #define READ_WC40_UC_INFO_B1_CRCr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000081fe, (_val))
 #define WRITE_WC40_UC_INFO_B1_CRCr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000081fe, (_val))
 #define MODIFY_WC40_UC_INFO_B1_CRCr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000081fe, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Dsc1b0
  */
 
 /* CDR Control 0 Register */
 #define READ_WC40_DSC1B0_CDR_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008200, (_val))
 #define WRITE_WC40_DSC1B0_CDR_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008200, (_val))
 #define MODIFY_WC40_DSC1B0_CDR_CTRL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008200, (_val), (_mask))
 
 /* CDR Control 1 Register */
 #define READ_WC40_DSC1B0_CDR_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008201, (_val))
 #define WRITE_WC40_DSC1B0_CDR_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008201, (_val))
 #define MODIFY_WC40_DSC1B0_CDR_CTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008201, (_val), (_mask))
 
 /* CDR Control 2 Register */
 #define READ_WC40_DSC1B0_CDR_CTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008202, (_val))
 #define WRITE_WC40_DSC1B0_CDR_CTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008202, (_val))
 #define MODIFY_WC40_DSC1B0_CDR_CTRL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008202, (_val), (_mask))
 
 /* Phase Interpolator Control 0 Register */
 #define READ_WC40_DSC1B0_PI_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008203, (_val))
 #define WRITE_WC40_DSC1B0_PI_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008203, (_val))
 #define MODIFY_WC40_DSC1B0_PI_CTRL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008203, (_val), (_mask))
 
 /* Phase Interpolator Control 1 Register */
 #define READ_WC40_DSC1B0_PI_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008204, (_val))
 #define WRITE_WC40_DSC1B0_PI_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008204, (_val))
 #define MODIFY_WC40_DSC1B0_PI_CTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008204, (_val), (_mask))
 
 /* DFE VGA Control 0 Register */
 #define READ_WC40_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008205, (_val))
 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008205, (_val))
 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008205, (_val), (_mask))
 
 /* DFE VGA Control 1 Register */
 #define READ_WC40_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008206, (_val))
 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008206, (_val))
 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008206, (_val), (_mask))
 
 /* DFE VGA Control 2 Register */
 #define READ_WC40_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008207, (_val))
 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008207, (_val))
 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008207, (_val), (_mask))
 
 /* DFE VGA Control 3 Register */
 #define READ_WC40_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008208, (_val))
 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008208, (_val))
 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008208, (_val), (_mask))
 
 /* DFE VGA Control 4 Register */
 #define READ_WC40_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008209, (_val))
 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008209, (_val))
 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008209, (_val), (_mask))
 
 /* DFE VGA Control 5 Register */
 #define READ_WC40_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000820a, (_val))
 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000820a, (_val))
 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000820a, (_val), (_mask))
 
 /* DFE VGA Control 6 Register */
 #define READ_WC40_DSC1B0_DFE_VGA_CTRL6r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000820b, (_val))
 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL6r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000820b, (_val))
 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL6r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000820b, (_val), (_mask))
 
 /* DFE VGA Control 7 Register */
 #define READ_WC40_DSC1B0_DFE_VGA_CTRL7r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000820c, (_val))
 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL7r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000820c, (_val))
 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL7r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000820c, (_val), (_mask))
 
 /* DSC Diagnostics Control 0 Register */
 #define READ_WC40_DSC1B0_DSC_DIAG_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000820d, (_val))
 #define WRITE_WC40_DSC1B0_DSC_DIAG_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000820d, (_val))
 #define MODIFY_WC40_DSC1B0_DSC_DIAG_CTRL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000820d, (_val), (_mask))
 
 /* DSC to uController Control Register */
 #define READ_WC40_DSC1B0_UC_CTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000820e, (_val))
 #define WRITE_WC40_DSC1B0_UC_CTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000820e, (_val))
 #define MODIFY_WC40_DSC1B0_UC_CTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000820e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Dsc2b0
  */
 
 /* DSC State Machine Control 0 Register */
 #define READ_WC40_DSC2B0_ACQ_SM_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008210, (_val))
 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008210, (_val))
 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008210, (_val), (_mask))
 
 /* DSC State Machine Control 1 Register */
 #define READ_WC40_DSC2B0_ACQ_SM_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008211, (_val))
 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008211, (_val))
 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008211, (_val), (_mask))
 
 /* DSC State Machine Control 2 Register */
 #define READ_WC40_DSC2B0_ACQ_SM_CTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008212, (_val))
 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008212, (_val))
 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008212, (_val), (_mask))
 
 /* DSC State Machine Control 3 Register */
 #define READ_WC40_DSC2B0_ACQ_SM_CTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008213, (_val))
 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008213, (_val))
 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008213, (_val), (_mask))
 
 /* DSC State Machine Control 4 Register */
 #define READ_WC40_DSC2B0_ACQ_SM_CTRL4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008214, (_val))
 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008214, (_val))
 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008214, (_val), (_mask))
 
 /* DSC State Machine Control 5 Register */
 #define READ_WC40_DSC2B0_ACQ_SM_CTRL5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008215, (_val))
 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008215, (_val))
 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008215, (_val), (_mask))
 
 /* DSC State Machine Control 6 Register */
 #define READ_WC40_DSC2B0_ACQ_SM_CTRL6r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008216, (_val))
 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL6r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008216, (_val))
 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL6r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008216, (_val), (_mask))
 
 /* DSC State Machine Control 7 Register */
 #define READ_WC40_DSC2B0_ACQ_SM_CTRL7r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008217, (_val))
 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL7r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008217, (_val))
 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL7r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008217, (_val), (_mask))
 
 /* DSC State Machine Control 8 Register */
 #define READ_WC40_DSC2B0_ACQ_SM_CTRL8r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008218, (_val))
 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL8r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008218, (_val))
 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL8r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008218, (_val), (_mask))
 
 /* DSC Analog Control 0 Register */
 #define READ_WC40_DSC2B0_DSC_ANA_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008219, (_val))
 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008219, (_val))
 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008219, (_val), (_mask))
 
 /* DSC Analog Control 1 Register */
 #define READ_WC40_DSC2B0_DSC_ANA_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000821a, (_val))
 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000821a, (_val))
 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000821a, (_val), (_mask))
 
 /* DSC Analog Control 2 Register */
 #define READ_WC40_DSC2B0_DSC_ANA_CTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000821b, (_val))
 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000821b, (_val))
 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000821b, (_val), (_mask))
 
 /* DSC Analog Control 3 Register */
 #define READ_WC40_DSC2B0_DSC_ANA_CTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000821c, (_val))
 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000821c, (_val))
 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000821c, (_val), (_mask))
 
 /* DSC Analog Control 4 Register */
 #define READ_WC40_DSC2B0_DSC_ANA_CTRL4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000821d, (_val))
 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000821d, (_val))
 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000821d, (_val), (_mask))
 
 /* DSC Misc Control 0 Register */
 #define READ_WC40_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000821e, (_val))
 #define WRITE_WC40_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000821e, (_val))
 #define MODIFY_WC40_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000821e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Dsc3b0
  */
 
 /* CDR Status 0 Register */
 #define READ_WC40_DSC3B0_CDR_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008220, (_val))
 #define WRITE_WC40_DSC3B0_CDR_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008220, (_val))
 #define MODIFY_WC40_DSC3B0_CDR_STATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008220, (_val), (_mask))
 
 /* CDR Status 1 Register */
 #define READ_WC40_DSC3B0_CDR_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008221, (_val))
 #define WRITE_WC40_DSC3B0_CDR_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008221, (_val))
 #define MODIFY_WC40_DSC3B0_CDR_STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008221, (_val), (_mask))
 
 /* CDR Status 2 Register */
 #define READ_WC40_DSC3B0_CDR_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008222, (_val))
 #define WRITE_WC40_DSC3B0_CDR_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008222, (_val))
 #define MODIFY_WC40_DSC3B0_CDR_STATUS2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008222, (_val), (_mask))
 
 /* Phase Interpolator Status 0 Register */
 #define READ_WC40_DSC3B0_PI_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008223, (_val))
 #define WRITE_WC40_DSC3B0_PI_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008223, (_val))
 #define MODIFY_WC40_DSC3B0_PI_STATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008223, (_val), (_mask))
 
 /* Phase Interpolator Status 1 Register */
 #define READ_WC40_DSC3B0_PI_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008224, (_val))
 #define WRITE_WC40_DSC3B0_PI_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008224, (_val))
 #define MODIFY_WC40_DSC3B0_PI_STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008224, (_val), (_mask))
 
 /* DFE VGA Status 0 Register */
 #define READ_WC40_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008225, (_val))
 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008225, (_val))
 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008225, (_val), (_mask))
 
 /* DFE VGA Status 1 Register */
 #define READ_WC40_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008226, (_val))
 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008226, (_val))
 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008226, (_val), (_mask))
 
 /* DFE VGA Status 2 Register */
 #define READ_WC40_DSC3B0_DFE_VGA_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008227, (_val))
 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008227, (_val))
 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008227, (_val), (_mask))
 
 /* DFE VGA Status 3 Register */
 #define READ_WC40_DSC3B0_DFE_VGA_STATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008228, (_val))
 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008228, (_val))
 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008228, (_val), (_mask))
 
 /* ACQ State Machine Status 0 Register */
 #define READ_WC40_DSC3B0_ACQ_SM_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008229, (_val))
 #define WRITE_WC40_DSC3B0_ACQ_SM_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008229, (_val))
 #define MODIFY_WC40_DSC3B0_ACQ_SM_STATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008229, (_val), (_mask))
 
 /* ACQ State Machine Status 1 Register */
 #define READ_WC40_DSC3B0_ACQ_SM_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000822a, (_val))
 #define WRITE_WC40_DSC3B0_ACQ_SM_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000822a, (_val))
 #define MODIFY_WC40_DSC3B0_ACQ_SM_STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000822a, (_val), (_mask))
 
 /* DSC Analog Status 0 Register */
 #define READ_WC40_DSC3B0_ANA_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000822b, (_val))
 #define WRITE_WC40_DSC3B0_ANA_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000822b, (_val))
 #define MODIFY_WC40_DSC3B0_ANA_STATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000822b, (_val), (_mask))
 
 /* DSC Analog Status 1 Register */
 #define READ_WC40_DSC3B0_ANA_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000822c, (_val))
 #define WRITE_WC40_DSC3B0_ANA_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000822c, (_val))
 #define MODIFY_WC40_DSC3B0_ANA_STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000822c, (_val), (_mask))
 
 /* DSC Analog Status 2 Register */
 #define READ_WC40_DSC3B0_ANA_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000822d, (_val))
 #define WRITE_WC40_DSC3B0_ANA_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000822d, (_val))
 #define MODIFY_WC40_DSC3B0_ANA_STATUS2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000822d, (_val), (_mask))
 
 /* DSC Analog Status 3 Register */
 #define READ_WC40_DSC3B0_ANA_STATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000822e, (_val))
 #define WRITE_WC40_DSC3B0_ANA_STATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000822e, (_val))
 #define MODIFY_WC40_DSC3B0_ANA_STATUS3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000822e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Dsc4b0
  */
 
 /* State Machine Control 0 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008230, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008230, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008230, (_val), (_mask))
 
 /* State Machine Control 1 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008231, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008231, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008231, (_val), (_mask))
 
 /* State Machine Control 2 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008232, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008232, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008232, (_val), (_mask))
 
 /* State Machine Control 3 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008233, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008233, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008233, (_val), (_mask))
 
 /* State Machine Control 4 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008234, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008234, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008234, (_val), (_mask))
 
 /* State Machine Control 5 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008235, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008235, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008235, (_val), (_mask))
 
 /* State Machine Control 6 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL6r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008236, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL6r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008236, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL6r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008236, (_val), (_mask))
 
 /* State Machine Control 7 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL7r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008237, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL7r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008237, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL7r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008237, (_val), (_mask))
 
 /* State Machine Control 8 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL8r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008238, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL8r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008238, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL8r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008238, (_val), (_mask))
 
 /* State Machine Control 9 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL9r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008239, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL9r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008239, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL9r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008239, (_val), (_mask))
 
 /* State Machine Control 10 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL10r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000823a, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL10r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000823a, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL10r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000823a, (_val), (_mask))
 
 /* State Machine Control 11 Register */
 #define READ_WC40_DSC4B0_TUNING_SM_CTRL11r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000823b, (_val))
 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL11r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000823b, (_val))
 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL11r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000823b, (_val), (_mask))
 
 /* Acquisition State Machine Control 9 Register */
 #define READ_WC40_DSC4B0_ACQ_SM_CTRL9r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000823c, (_val))
 #define WRITE_WC40_DSC4B0_ACQ_SM_CTRL9r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000823c, (_val))
 #define MODIFY_WC40_DSC4B0_ACQ_SM_CTRL9r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000823c, (_val), (_mask))
 
 /* Acquisition State Machine Control 10 Register */
 #define READ_WC40_DSC4B0_ACQ_SM_CTRL10r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000823d, (_val))
 #define WRITE_WC40_DSC4B0_ACQ_SM_CTRL10r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000823d, (_val))
 #define MODIFY_WC40_DSC4B0_ACQ_SM_CTRL10r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000823d, (_val), (_mask))
 
 /* Acquisition State Machine Control 11 Register */
 #define READ_WC40_DSC4B0_ACQ_SM_CTRL11r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000823e, (_val))
 #define WRITE_WC40_DSC4B0_ACQ_SM_CTRL11r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000823e, (_val))
 #define MODIFY_WC40_DSC4B0_ACQ_SM_CTRL11r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000823e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Dsc5b0
  */
 
 /* State Machine Status 0 Register */
 #define READ_WC40_DSC5B0_TUNING_SM_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008240, (_val))
 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008240, (_val))
 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008240, (_val), (_mask))
 
 /* State Machine Status 1 Register */
 #define READ_WC40_DSC5B0_TUNING_SM_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008241, (_val))
 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008241, (_val))
 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008241, (_val), (_mask))
 
 /* State Machine Status 2 Register */
 #define READ_WC40_DSC5B0_TUNING_SM_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008242, (_val))
 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008242, (_val))
 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008242, (_val), (_mask))
 
 /* State Machine Status 3 Register */
 #define READ_WC40_DSC5B0_TUNING_SM_STATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008243, (_val))
 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008243, (_val))
 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008243, (_val), (_mask))
 
 /* State Machine Status 4 Register */
 #define READ_WC40_DSC5B0_TUNING_SM_STATUS4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008244, (_val))
 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008244, (_val))
 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008244, (_val), (_mask))
 
 /* State Machine Status 5 Register */
 #define READ_WC40_DSC5B0_TUNING_SM_STATUS5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008245, (_val))
 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008245, (_val))
 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008245, (_val), (_mask))
 
 /* State Machine Status 6 Register */
 #define READ_WC40_DSC5B0_TUNING_SM_STATUS6r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008246, (_val))
 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS6r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008246, (_val))
 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS6r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008246, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_CL72_UserB0
  */
 
 /* CL72 TX Coefficient Update Register */
 #define READ_WC40_CL72_USERB0_CL72_XMT_CONTROL_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082e0, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_XMT_CONTROL_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082e0, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_XMT_CONTROL_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082e0, (_val), (_mask))
 
 /* CL72 Status Report Register */
 #define READ_WC40_CL72_USERB0_CL72_RCVD_STATUS_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082e1, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_RCVD_STATUS_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082e1, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_RCVD_STATUS_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082e1, (_val), (_mask))
 
 /* CL72 TX FIR Tap Register */
 #define READ_WC40_CL72_USERB0_CL72_TX_FIR_TAP_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082e2, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_TX_FIR_TAP_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082e2, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_TX_FIR_TAP_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082e2, (_val), (_mask))
 
 /* CL72 Miscellaneous_1 Control Register */
 #define READ_WC40_CL72_USERB0_CL72_MISC1_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082e3, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_MISC1_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082e3, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_MISC1_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082e3, (_val), (_mask))
 
 /* CL72 Miscellaneous_2 Control Register */
 #define READ_WC40_CL72_USERB0_CL72_MISC2_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082e4, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_MISC2_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082e4, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_MISC2_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082e4, (_val), (_mask))
 
 /* CL72 KR Default Control Register */
 #define READ_WC40_CL72_USERB0_CL72_KR_DEFAULT_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082e5, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_KR_DEFAULT_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082e5, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_KR_DEFAULT_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082e5, (_val), (_mask))
 
 /* CL72 OS Default Control Register */
 #define READ_WC40_CL72_USERB0_CL72_OS_DEFAULT_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082e6, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_OS_DEFAULT_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082e6, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_OS_DEFAULT_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082e6, (_val), (_mask))
 
 /* CL72 BR Default Control Register */
 #define READ_WC40_CL72_USERB0_CL72_BR_DEFAULT_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082e7, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_BR_DEFAULT_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082e7, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_BR_DEFAULT_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082e7, (_val), (_mask))
 
 /* CL72 2p5 Default Control Register */
 #define READ_WC40_CL72_USERB0_CL72_2P5_DEFAULT_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082e8, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_2P5_DEFAULT_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082e8, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_2P5_DEFAULT_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082e8, (_val), (_mask))
 
 /* CL72 Tap Limit Control Register */
 #define READ_WC40_CL72_USERB0_CL72_TAP_LIMIT_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082e9, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_TAP_LIMIT_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082e9, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_TAP_LIMIT_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082e9, (_val), (_mask))
 
 /* CL72 Miscellaneous_3 Control Register */
 #define READ_WC40_CL72_USERB0_CL72_MISC3_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082ea, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_MISC3_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082ea, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_MISC3_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082ea, (_val), (_mask))
 
 /* CL72 Tap Present Control Register */
 #define READ_WC40_CL72_USERB0_CL72_TAP_PRESET_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082eb, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_TAP_PRESET_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082eb, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_TAP_PRESET_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082eb, (_val), (_mask))
 
 /* CL72 Miscellaneous_4 Control Register */
 #define READ_WC40_CL72_USERB0_CL72_MISC4_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082ec, (_val))
 #define WRITE_WC40_CL72_USERB0_CL72_MISC4_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082ec, (_val))
 #define MODIFY_WC40_CL72_USERB0_CL72_MISC4_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082ec, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_CL72_UserB1
  */
 
 /* CL72 Fault Register */
 #define READ_WC40_CL72_USERB1_CL72_FAULT_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082f9, (_val))
 #define WRITE_WC40_CL72_USERB1_CL72_FAULT_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082f9, (_val))
 #define MODIFY_WC40_CL72_USERB1_CL72_FAULT_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082f9, (_val), (_mask))
 
 /* CL72 Debug 1 Register */
 #define READ_WC40_CL72_USERB1_CL72_DEBUG_1_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082fb, (_val))
 #define WRITE_WC40_CL72_USERB1_CL72_DEBUG_1_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082fb, (_val))
 #define MODIFY_WC40_CL72_USERB1_CL72_DEBUG_1_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082fb, (_val), (_mask))
 
 /* CL72 Debug 2 Register */
 #define READ_WC40_CL72_USERB1_CL72_DEBUG_2_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082fc, (_val))
 #define WRITE_WC40_CL72_USERB1_CL72_DEBUG_2_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082fc, (_val))
 #define MODIFY_WC40_CL72_USERB1_CL72_DEBUG_2_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082fc, (_val), (_mask))
 
 /* CL72 Debug 3 Register */
 #define READ_WC40_CL72_USERB1_CL72_DEBUG_3_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082fd, (_val))
 #define WRITE_WC40_CL72_USERB1_CL72_DEBUG_3_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082fd, (_val))
 #define MODIFY_WC40_CL72_USERB1_CL72_DEBUG_3_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082fd, (_val), (_mask))
 
 /* CL72 Debug 4 Register */
 #define READ_WC40_CL72_USERB1_CL72_DEBUG_4_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000082fe, (_val))
 #define WRITE_WC40_CL72_USERB1_CL72_DEBUG_4_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000082fe, (_val))
 #define MODIFY_WC40_CL72_USERB1_CL72_DEBUG_4_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000082fe, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_SerdesDigital
  */
 
 /* 1000X control 1 register */
 #define READ_WC40_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008300, (_val))
 #define WRITE_WC40_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008300, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_CONTROL1000X1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008300, (_val), (_mask))
 
 /* 1000X control 2 register */
 #define READ_WC40_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008301, (_val))
 #define WRITE_WC40_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008301, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008301, (_val), (_mask))
 
 /* 1000X control 3 register */
 #define READ_WC40_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008302, (_val))
 #define WRITE_WC40_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008302, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_CONTROL1000X3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008302, (_val), (_mask))
 
 /* 1000X control 4 register */
 #define READ_WC40_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008303, (_val))
 #define WRITE_WC40_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008303, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_CONTROL1000X4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008303, (_val), (_mask))
 
 /* 1000X status 1 register */
 #define READ_WC40_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008304, (_val))
 #define WRITE_WC40_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008304, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_STATUS1000X1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008304, (_val), (_mask))
 
 /* 1000X status 2 register */
 #define READ_WC40_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008305, (_val))
 #define WRITE_WC40_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008305, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_STATUS1000X2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008305, (_val), (_mask))
 
 /* 1000X status 3 register */
 #define READ_WC40_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008306, (_val))
 #define WRITE_WC40_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008306, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_STATUS1000X3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008306, (_val), (_mask))
 
 /* Invalid code group count register */
 #define READ_WC40_SERDESDIGITAL_BADCODEGROUPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008307, (_val))
 #define WRITE_WC40_SERDESDIGITAL_BADCODEGROUPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008307, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_BADCODEGROUPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008307, (_val), (_mask))
 
 /* Miscellaneous 1 control register */
 #define READ_WC40_SERDESDIGITAL_MISC1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008308, (_val))
 #define WRITE_WC40_SERDESDIGITAL_MISC1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008308, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_MISC1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008308, (_val), (_mask))
 
 /* Miscellaneous 2 control register */
 #define READ_WC40_SERDESDIGITAL_MISC2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008309, (_val))
 #define WRITE_WC40_SERDESDIGITAL_MISC2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008309, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_MISC2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008309, (_val), (_mask))
 
 /* Pattern generator control register */
 #define READ_WC40_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000830a, (_val))
 #define WRITE_WC40_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000830a, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_PATGENCTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000830a, (_val), (_mask))
 
 /* Pattern generator status register */
 #define READ_WC40_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000830b, (_val))
 #define WRITE_WC40_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000830b, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_PATGENSTATr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000830b, (_val), (_mask))
 
 /* Test mode register */
 #define READ_WC40_SERDESDIGITAL_TESTMODEr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000830c, (_val))
 #define WRITE_WC40_SERDESDIGITAL_TESTMODEr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000830c, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_TESTMODEr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000830c, (_val), (_mask))
 
 /* Tx packet count register */
 #define READ_WC40_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000830d, (_val))
 #define WRITE_WC40_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000830d, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_TXPKTCNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000830d, (_val), (_mask))
 
 /* Rx packet count register */
 #define READ_WC40_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000830e, (_val))
 #define WRITE_WC40_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000830e, (_val))
 #define MODIFY_WC40_SERDESDIGITAL_RXPKTCNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000830e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_SerdesID
  */
 
 /* Serdes ID 0 register */
 #define READ_WC40_SERDESID_SERDESID0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008310, (_val))
 #define WRITE_WC40_SERDESID_SERDESID0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008310, (_val))
 #define MODIFY_WC40_SERDESID_SERDESID0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008310, (_val), (_mask))
 
 /* Serdes ID 1 register */
 #define READ_WC40_SERDESID_SERDESID1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008311, (_val))
 #define WRITE_WC40_SERDESID_SERDESID1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008311, (_val))
 #define MODIFY_WC40_SERDESID_SERDESID1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008311, (_val), (_mask))
 
 /* Serdes ID 2 register */
 #define READ_WC40_SERDESID_SERDESID2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008312, (_val))
 #define WRITE_WC40_SERDESID_SERDESID2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008312, (_val))
 #define MODIFY_WC40_SERDESID_SERDESID2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008312, (_val), (_mask))
 
 /* Serdes ID 3 register */
 #define READ_WC40_SERDESID_SERDESID3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008313, (_val))
 #define WRITE_WC40_SERDESID_SERDESID3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008313, (_val))
 #define MODIFY_WC40_SERDESID_SERDESID3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008313, (_val), (_mask))
 
 /* Serdes ID 4 register */
 #define READ_WC40_SERDESID_SERDESID4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008314, (_val))
 #define WRITE_WC40_SERDESID_SERDESID4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008314, (_val))
 #define MODIFY_WC40_SERDESID_SERDESID4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008314, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Digital3
  */
 
 /* AN lost link count time, bits 15:0 */
 #define READ_WC40_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008320, (_val))
 #define WRITE_WC40_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008320, (_val))
 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008320, (_val), (_mask))
 
 /* AN switch count time, bits 15:0 */
 #define READ_WC40_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008321, (_val))
 #define WRITE_WC40_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008321, (_val))
 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008321, (_val), (_mask))
 
 /* AN link count time, bits 15:0 */
 #define READ_WC40_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008322, (_val))
 #define WRITE_WC40_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008322, (_val))
 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008322, (_val), (_mask))
 
 /* AN switch count & link count time, bits 23:16 */
 #define READ_WC40_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008323, (_val))
 #define WRITE_WC40_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008323, (_val))
 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008323, (_val), (_mask))
 
 /* Over 1G message page number & AN fail count timer */
 #define READ_WC40_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008324, (_val))
 #define WRITE_WC40_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008324, (_val))
 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008324, (_val), (_mask))
 
 /* AN ignore link count time, bits 15:0 */
 #define READ_WC40_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008325, (_val))
 #define WRITE_WC40_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008325, (_val))
 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008325, (_val), (_mask))
 
 /* AN lost link count & ignore link count time, bits 23:16 */
 #define READ_WC40_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008326, (_val))
 #define WRITE_WC40_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008326, (_val))
 #define MODIFY_WC40_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008326, (_val), (_mask))
 
 /* Test port out bits 15:0, tpout[15:0] */
 #define READ_WC40_DIGITAL3_TPOUT_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008327, (_val))
 #define WRITE_WC40_DIGITAL3_TPOUT_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008327, (_val))
 #define MODIFY_WC40_DIGITAL3_TPOUT_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008327, (_val), (_mask))
 
 /* Test port out bits 23:8, tpout[23:8] */
 #define READ_WC40_DIGITAL3_TPOUT_2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008328, (_val))
 #define WRITE_WC40_DIGITAL3_TPOUT_2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008328, (_val))
 #define MODIFY_WC40_DIGITAL3_TPOUT_2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008328, (_val), (_mask))
 
 /* AN local device user page 1 */
 #define READ_WC40_DIGITAL3_UP1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008329, (_val))
 #define WRITE_WC40_DIGITAL3_UP1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008329, (_val))
 #define MODIFY_WC40_DIGITAL3_UP1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008329, (_val), (_mask))
 
 /* AN local device user page 2 */
 #define READ_WC40_DIGITAL3_UP2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000832a, (_val))
 #define WRITE_WC40_DIGITAL3_UP2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000832a, (_val))
 #define MODIFY_WC40_DIGITAL3_UP2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000832a, (_val), (_mask))
 
 /* AN local device user page 3 */
 #define READ_WC40_DIGITAL3_UP3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000832b, (_val))
 #define WRITE_WC40_DIGITAL3_UP3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000832b, (_val))
 #define MODIFY_WC40_DIGITAL3_UP3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000832b, (_val), (_mask))
 
 /* AN link partner user page 1 */
 #define READ_WC40_DIGITAL3_LP_UP1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000832c, (_val))
 #define WRITE_WC40_DIGITAL3_LP_UP1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000832c, (_val))
 #define MODIFY_WC40_DIGITAL3_LP_UP1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000832c, (_val), (_mask))
 
 /* AN link partner user page 2 */
 #define READ_WC40_DIGITAL3_LP_UP2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000832d, (_val))
 #define WRITE_WC40_DIGITAL3_LP_UP2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000832d, (_val))
 #define MODIFY_WC40_DIGITAL3_LP_UP2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000832d, (_val), (_mask))
 
 /* AN link partner user page 3 */
 #define READ_WC40_DIGITAL3_LP_UP3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000832e, (_val))
 #define WRITE_WC40_DIGITAL3_LP_UP3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000832e, (_val))
 #define MODIFY_WC40_DIGITAL3_LP_UP3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000832e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Digital4
  */
 
 /* Miscellaneous Rx status register */
 #define READ_WC40_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008330, (_val))
 #define WRITE_WC40_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008330, (_val))
 #define MODIFY_WC40_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008330, (_val), (_mask))
 
 /* Link partner basepage register */
 #define READ_WC40_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008331, (_val))
 #define WRITE_WC40_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008331, (_val))
 #define MODIFY_WC40_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008331, (_val), (_mask))
 
 /* Link partner nextpage 0 register */
 #define READ_WC40_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008332, (_val))
 #define WRITE_WC40_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008332, (_val))
 #define MODIFY_WC40_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008332, (_val), (_mask))
 
 /* Link partner nextpage 1 register */
 #define READ_WC40_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008333, (_val))
 #define WRITE_WC40_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008333, (_val))
 #define MODIFY_WC40_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008333, (_val), (_mask))
 
 /* Link partner nextpage 2 register */
 #define READ_WC40_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008334, (_val))
 #define WRITE_WC40_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008334, (_val))
 #define MODIFY_WC40_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008334, (_val), (_mask))
 
 /* Link partner nextpage 3 register */
 #define READ_WC40_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008335, (_val))
 #define WRITE_WC40_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008335, (_val))
 #define MODIFY_WC40_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008335, (_val), (_mask))
 
 /* Link partner nextpage 4 register */
 #define READ_WC40_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008336, (_val))
 #define WRITE_WC40_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008336, (_val))
 #define MODIFY_WC40_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008336, (_val), (_mask))
 
 /* Remote phy nextpage 0 register */
 #define READ_WC40_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008337, (_val))
 #define WRITE_WC40_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008337, (_val))
 #define MODIFY_WC40_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008337, (_val), (_mask))
 
 /* Remote phy nextpage 1 register */
 #define READ_WC40_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008338, (_val))
 #define WRITE_WC40_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008338, (_val))
 #define MODIFY_WC40_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008338, (_val), (_mask))
 
 /* Remote phy nextpage 2 register */
 #define READ_WC40_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008339, (_val))
 #define WRITE_WC40_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008339, (_val))
 #define MODIFY_WC40_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008339, (_val), (_mask))
 
 /* Remote phy nextpage 3 register */
 #define READ_WC40_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000833a, (_val))
 #define WRITE_WC40_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000833a, (_val))
 #define MODIFY_WC40_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000833a, (_val), (_mask))
 
 /* Remote phy nextpage 4 register */
 #define READ_WC40_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000833b, (_val))
 #define WRITE_WC40_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000833b, (_val))
 #define MODIFY_WC40_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000833b, (_val), (_mask))
 
 /* Miscellaneous 3 control register */
 #define READ_WC40_DIGITAL4_MISC3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000833c, (_val))
 #define WRITE_WC40_DIGITAL4_MISC3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000833c, (_val))
 #define MODIFY_WC40_DIGITAL4_MISC3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000833c, (_val), (_mask))
 
 /* Miscelaneous 4 control register */
 #define READ_WC40_DIGITAL4_MISC4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000833d, (_val))
 #define WRITE_WC40_DIGITAL4_MISC4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000833d, (_val))
 #define MODIFY_WC40_DIGITAL4_MISC4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000833d, (_val), (_mask))
 
 /* Miscelaneous 5 control register */
 #define READ_WC40_DIGITAL4_MISC5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000833e, (_val))
 #define WRITE_WC40_DIGITAL4_MISC5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000833e, (_val))
 #define MODIFY_WC40_DIGITAL4_MISC5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000833e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Digital5
  */
 
 /* CL72 Link counter MSB [23:16] */
 #define READ_WC40_DIGITAL5_LINKCNT_CL72_MSBr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008340, (_val))
 #define WRITE_WC40_DIGITAL5_LINKCNT_CL72_MSBr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008340, (_val))
 #define MODIFY_WC40_DIGITAL5_LINKCNT_CL72_MSBr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008340, (_val), (_mask))
 
 /* CL72 Link counter LSB [15:0] */
 #define READ_WC40_DIGITAL5_LINKCNT_CL72_LSBr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008341, (_val))
 #define WRITE_WC40_DIGITAL5_LINKCNT_CL72_LSBr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008341, (_val))
 #define MODIFY_WC40_DIGITAL5_LINKCNT_CL72_LSBr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008341, (_val), (_mask))
 
 /* Link Partner's UP4 page */
 #define READ_WC40_DIGITAL5_LP_UP4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008342, (_val))
 #define WRITE_WC40_DIGITAL5_LP_UP4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008342, (_val))
 #define MODIFY_WC40_DIGITAL5_LP_UP4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008342, (_val), (_mask))
 
 /* Link Partner's UP5 page */
 #define READ_WC40_DIGITAL5_LP_UP5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008343, (_val))
 #define WRITE_WC40_DIGITAL5_LP_UP5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008343, (_val))
 #define MODIFY_WC40_DIGITAL5_LP_UP5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008343, (_val), (_mask))
 
 /* LPI hysteresis control */
 #define READ_WC40_DIGITAL5_LPI_HYSTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008344, (_val))
 #define WRITE_WC40_DIGITAL5_LPI_HYSTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008344, (_val))
 #define MODIFY_WC40_DIGITAL5_LPI_HYSTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008344, (_val), (_mask))
 
 /* Misc6 */
 #define READ_WC40_DIGITAL5_MISC6r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008345, (_val))
 #define WRITE_WC40_DIGITAL5_MISC6r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008345, (_val))
 #define MODIFY_WC40_DIGITAL5_MISC6r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008345, (_val), (_mask))
 
 /* parDetINDStatus */
 #define READ_WC40_DIGITAL5_PARDETINDSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008346, (_val))
 #define WRITE_WC40_DIGITAL5_PARDETINDSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008346, (_val))
 #define MODIFY_WC40_DIGITAL5_PARDETINDSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008346, (_val), (_mask))
 
 /* parDetINDControl1 */
 #define READ_WC40_DIGITAL5_PARDETINDCONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008347, (_val))
 #define WRITE_WC40_DIGITAL5_PARDETINDCONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008347, (_val))
 #define MODIFY_WC40_DIGITAL5_PARDETINDCONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008347, (_val), (_mask))
 
 /* parDetINDControl2 */
 #define READ_WC40_DIGITAL5_PARDETINDCONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008348, (_val))
 #define WRITE_WC40_DIGITAL5_PARDETINDCONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008348, (_val))
 #define MODIFY_WC40_DIGITAL5_PARDETINDCONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008348, (_val), (_mask))
 
 /* Misc7 */
 #define READ_WC40_DIGITAL5_MISC7r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008349, (_val))
 #define WRITE_WC40_DIGITAL5_MISC7r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008349, (_val))
 #define MODIFY_WC40_DIGITAL5_MISC7r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008349, (_val), (_mask))
 
 /* link_status */
 #define READ_WC40_DIGITAL5_LINK_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000834d, (_val))
 #define WRITE_WC40_DIGITAL5_LINK_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000834d, (_val))
 #define MODIFY_WC40_DIGITAL5_LINK_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000834d, (_val), (_mask))
 
 /* Actual Speed status */
 #define READ_WC40_DIGITAL5_ACTUAL_SPEEDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000834e, (_val))
 #define WRITE_WC40_DIGITAL5_ACTUAL_SPEEDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000834e, (_val))
 #define MODIFY_WC40_DIGITAL5_ACTUAL_SPEEDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000834e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Digital6
  */
 
 /* MP5, Message Page 5, next page control register */
 #define READ_WC40_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008350, (_val))
 #define WRITE_WC40_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008350, (_val))
 #define MODIFY_WC40_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008350, (_val), (_mask))
 
 /* sgmii & max timer offsets */
 #define READ_WC40_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008351, (_val))
 #define WRITE_WC40_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008351, (_val))
 #define MODIFY_WC40_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008351, (_val), (_mask))
 
 /* link up & link down timer offsets */
 #define READ_WC40_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008352, (_val))
 #define WRITE_WC40_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008352, (_val))
 #define MODIFY_WC40_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008352, (_val), (_mask))
 
 /* break link & next page link timer offsets */
 #define READ_WC40_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008353, (_val))
 #define WRITE_WC40_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008353, (_val))
 #define MODIFY_WC40_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008353, (_val), (_mask))
 
 /* 11 MSbits of the oui, oui[23:13] */
 #define READ_WC40_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008354, (_val))
 #define WRITE_WC40_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008354, (_val))
 #define MODIFY_WC40_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008354, (_val), (_mask))
 
 /* 11 middle bits of the oui, oui[12:2] */
 #define READ_WC40_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008355, (_val))
 #define WRITE_WC40_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008355, (_val))
 #define MODIFY_WC40_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008355, (_val), (_mask))
 
 /* 2 LSbits of the oui, oui[1:0] */
 #define READ_WC40_DIGITAL6_BAM_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008356, (_val))
 #define WRITE_WC40_DIGITAL6_BAM_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008356, (_val))
 #define MODIFY_WC40_DIGITAL6_BAM_FIELDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008356, (_val), (_mask))
 
 /* User defined field of MP5 */
 #define READ_WC40_DIGITAL6_UD_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008357, (_val))
 #define WRITE_WC40_DIGITAL6_UD_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008357, (_val))
 #define MODIFY_WC40_DIGITAL6_UD_FIELDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008357, (_val), (_mask))
 
 /* Link partner's 11 MSbits of the oui, oui[23:13] */
 #define READ_WC40_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008358, (_val))
 #define WRITE_WC40_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008358, (_val))
 #define MODIFY_WC40_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008358, (_val), (_mask))
 
 /* Link partner's 11 middle bits of the oui, oui[12:2] */
 #define READ_WC40_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008359, (_val))
 #define WRITE_WC40_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008359, (_val))
 #define MODIFY_WC40_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008359, (_val), (_mask))
 
 /* Link partner's 2 LSbits of the oui, oui[1:0] */
 #define READ_WC40_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000835a, (_val))
 #define WRITE_WC40_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000835a, (_val))
 #define MODIFY_WC40_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000835a, (_val), (_mask))
 
 /* Link partner's User defined field of MP5 */
 #define READ_WC40_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000835b, (_val))
 #define WRITE_WC40_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000835b, (_val))
 #define MODIFY_WC40_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000835b, (_val), (_mask))
 
 /* AN local device user page 4 */
 #define READ_WC40_DIGITAL6_UP4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000835d, (_val))
 #define WRITE_WC40_DIGITAL6_UP4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000835d, (_val))
 #define MODIFY_WC40_DIGITAL6_UP4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000835d, (_val), (_mask))
 
 /* AN local device user page 5 */
 #define READ_WC40_DIGITAL6_UP5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000835e, (_val))
 #define WRITE_WC40_DIGITAL6_UP5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000835e, (_val))
 #define MODIFY_WC40_DIGITAL6_UP5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000835e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_CL49_UserB0
  */
 
 /* cl49 64/66 User Encoder Control 1 Register */
 #define READ_WC40_CL49_USERB0_CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008360, (_val))
 #define WRITE_WC40_CL49_USERB0_CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008360, (_val))
 #define MODIFY_WC40_CL49_USERB0_CONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008360, (_val), (_mask))
 
 /* cl49 64/66 User Encoder Status Register */
 #define READ_WC40_CL49_USERB0_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008361, (_val))
 #define WRITE_WC40_CL49_USERB0_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008361, (_val))
 #define MODIFY_WC40_CL49_USERB0_STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008361, (_val), (_mask))
 
 /* cl49 64/66 User Programmable symbol detected to align data in cl49 20 bit i/f mode */
 #define READ_WC40_CL49_USERB0_SYMBOLDETECTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008362, (_val))
 #define WRITE_WC40_CL49_USERB0_SYMBOLDETECTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008362, (_val))
 #define MODIFY_WC40_CL49_USERB0_SYMBOLDETECTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008362, (_val), (_mask))
 
 /* cl49 64/66 User Programmable symbol inserted to align data in cl49 20 bit i/f mode */
 #define READ_WC40_CL49_USERB0_SYMBOLINSERTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008363, (_val))
 #define WRITE_WC40_CL49_USERB0_SYMBOLINSERTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008363, (_val))
 #define MODIFY_WC40_CL49_USERB0_SYMBOLINSERTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008363, (_val), (_mask))
 
 /* cl49 64/66 User Encoder Control 2 Register */
 #define READ_WC40_CL49_USERB0_CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008364, (_val))
 #define WRITE_WC40_CL49_USERB0_CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008364, (_val))
 #define MODIFY_WC40_CL49_USERB0_CONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008364, (_val), (_mask))
 
 /* cl49 Tx fsm status register */
 #define READ_WC40_CL49_USERB0_TXSM_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008365, (_val))
 #define WRITE_WC40_CL49_USERB0_TXSM_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008365, (_val))
 #define MODIFY_WC40_CL49_USERB0_TXSM_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008365, (_val), (_mask))
 
 /* cl49 Rx fsm status register */
 #define READ_WC40_CL49_USERB0_RXSM_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008366, (_val))
 #define WRITE_WC40_CL49_USERB0_RXSM_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008366, (_val))
 #define MODIFY_WC40_CL49_USERB0_RXSM_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008366, (_val), (_mask))
 
 /* cl49 Lock fsm status register */
 #define READ_WC40_CL49_USERB0_LSM_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008367, (_val))
 #define WRITE_WC40_CL49_USERB0_LSM_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008367, (_val))
 #define MODIFY_WC40_CL49_USERB0_LSM_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008367, (_val), (_mask))
 
 /* 64/66 Decoder control register */
 #define READ_WC40_CL49_USERB0_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008368, (_val))
 #define WRITE_WC40_CL49_USERB0_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008368, (_val))
 #define MODIFY_WC40_CL49_USERB0_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008368, (_val), (_mask))
 
 /* 64/66 Decoder status register */
 #define READ_WC40_CL49_USERB0_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008369, (_val))
 #define WRITE_WC40_CL49_USERB0_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008369, (_val))
 #define MODIFY_WC40_CL49_USERB0_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008369, (_val), (_mask))
 
 /* sync header counter value register */
 #define READ_WC40_CL49_USERB0_SHCOUNTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000836a, (_val))
 #define WRITE_WC40_CL49_USERB0_SHCOUNTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000836a, (_val))
 #define MODIFY_WC40_CL49_USERB0_SHCOUNTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000836a, (_val), (_mask))
 
 /* BER fsm - 125us timer value register */
 #define READ_WC40_CL49_USERB0_TIMER125USr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000836b, (_val))
 #define WRITE_WC40_CL49_USERB0_TIMER125USr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000836b, (_val))
 #define MODIFY_WC40_CL49_USERB0_TIMER125USr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000836b, (_val), (_mask))
 
 /* BER fsm - ber counter */
 #define READ_WC40_CL49_USERB0_BERCNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000836c, (_val))
 #define WRITE_WC40_CL49_USERB0_BERCNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000836c, (_val))
 #define MODIFY_WC40_CL49_USERB0_BERCNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000836c, (_val), (_mask))
 
 /* cl49 BER Monitor fsm status register */
 #define READ_WC40_CL49_USERB0_BERMON_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000836d, (_val))
 #define WRITE_WC40_CL49_USERB0_BERMON_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000836d, (_val))
 #define MODIFY_WC40_CL49_USERB0_BERMON_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000836d, (_val), (_mask))
 
 /* test control register */
 #define READ_WC40_CL49_USERB0_TSTCNT1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000836e, (_val))
 #define WRITE_WC40_CL49_USERB0_TSTCNT1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000836e, (_val))
 #define MODIFY_WC40_CL49_USERB0_TSTCNT1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000836e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_CL73_UserB0
  */
 
 /* Clause 73 user control */
 #define READ_WC40_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008370, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008370, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008370, (_val), (_mask))
 
 /* Clause 73 user status */
 #define READ_WC40_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008371, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008371, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008371, (_val), (_mask))
 
 /* Clause 73 BAM control 1 */
 #define READ_WC40_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008372, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008372, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008372, (_val), (_mask))
 
 /* Clause 73 BAM control 2 */
 #define READ_WC40_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008373, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008373, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008373, (_val), (_mask))
 
 /* Clause 73 BAM control 3 */
 #define READ_WC40_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008374, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008374, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008374, (_val), (_mask))
 
 /* Clause 73 BAM status 1 */
 #define READ_WC40_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008375, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008375, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008375, (_val), (_mask))
 
 /* Clause 73 BAM status 2 */
 #define READ_WC40_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008376, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008376, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008376, (_val), (_mask))
 
 /* Clause 73 BAM status 3 */
 #define READ_WC40_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008377, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008377, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008377, (_val), (_mask))
 
 /* Clause 73 user control2 */
 #define READ_WC40_CL73_USERB0_CL73_UCTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008378, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_UCTRL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008378, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_UCTRL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008378, (_val), (_mask))
 
 /* Clause 73 user control3 */
 #define READ_WC40_CL73_USERB0_CL73_UCTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008379, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_UCTRL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008379, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_UCTRL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008379, (_val), (_mask))
 
 /* Clause 73 user control4 */
 #define READ_WC40_CL73_USERB0_CL73_UCTRL4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000837a, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_UCTRL4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000837a, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_UCTRL4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000837a, (_val), (_mask))
 
 /* Clause 73 EEE control */
 #define READ_WC40_CL73_USERB0_CL73_EEECTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000837e, (_val))
 #define WRITE_WC40_CL73_USERB0_CL73_EEECTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000837e, (_val))
 #define MODIFY_WC40_CL73_USERB0_CL73_EEECTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000837e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_CL74_UserB0
  */
 
 /* "User FEC Control 1 register" */
 #define READ_WC40_CL74_USERB0_UFECCONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008380, (_val))
 #define WRITE_WC40_CL74_USERB0_UFECCONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008380, (_val))
 #define MODIFY_WC40_CL74_USERB0_UFECCONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008380, (_val), (_mask))
 
 /* "User FEC Control 2 register" */
 #define READ_WC40_CL74_USERB0_UFECCONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008381, (_val))
 #define WRITE_WC40_CL74_USERB0_UFECCONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008381, (_val))
 #define MODIFY_WC40_CL74_USERB0_UFECCONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008381, (_val), (_mask))
 
 /* "User FEC Control 3 register" */
 #define READ_WC40_CL74_USERB0_UFECCONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008382, (_val))
 #define WRITE_WC40_CL74_USERB0_UFECCONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008382, (_val))
 #define MODIFY_WC40_CL74_USERB0_UFECCONTROL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008382, (_val), (_mask))
 
 /* "User FEC debug read data [15:0]" */
 #define READ_WC40_CL74_USERB0_UFECDBG_EDATALr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008383, (_val))
 #define WRITE_WC40_CL74_USERB0_UFECDBG_EDATALr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008383, (_val))
 #define MODIFY_WC40_CL74_USERB0_UFECDBG_EDATALr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008383, (_val), (_mask))
 
 /* "User FEC debug read data [31:16]" */
 #define READ_WC40_CL74_USERB0_UFECDBG_EDATAHr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008384, (_val))
 #define WRITE_WC40_CL74_USERB0_UFECDBG_EDATAHr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008384, (_val))
 #define MODIFY_WC40_CL74_USERB0_UFECDBG_EDATAHr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008384, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_EEE_UserB0
  */
 
 /* EEE control register0 */
 #define READ_WC40_EEE_USERB0_EEE_COMBO_CONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008390, (_val))
 #define WRITE_WC40_EEE_USERB0_EEE_COMBO_CONTROL0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008390, (_val))
 #define MODIFY_WC40_EEE_USERB0_EEE_COMBO_CONTROL0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008390, (_val), (_mask))
 
 /* Cl36 Tx lpi fsm status register */
 #define READ_WC40_EEE_USERB0_CL36_TX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008391, (_val))
 #define WRITE_WC40_EEE_USERB0_CL36_TX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008391, (_val))
 #define MODIFY_WC40_EEE_USERB0_CL36_TX_LPI_SMr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008391, (_val), (_mask))
 
 /* Cl36 Rx lpi fsm status register */
 #define READ_WC40_EEE_USERB0_CL36_RX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008392, (_val))
 #define WRITE_WC40_EEE_USERB0_CL36_RX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008392, (_val))
 #define MODIFY_WC40_EEE_USERB0_CL36_RX_LPI_SMr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008392, (_val), (_mask))
 
 /* Cl49 Tx lpi fsm status register */
 #define READ_WC40_EEE_USERB0_CL49_TX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008393, (_val))
 #define WRITE_WC40_EEE_USERB0_CL49_TX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008393, (_val))
 #define MODIFY_WC40_EEE_USERB0_CL49_TX_LPI_SMr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008393, (_val), (_mask))
 
 /* Cl49 Rx lpi fsm status register */
 #define READ_WC40_EEE_USERB0_CL49_RX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008394, (_val))
 #define WRITE_WC40_EEE_USERB0_CL49_RX_LPI_SMr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008394, (_val))
 #define MODIFY_WC40_EEE_USERB0_CL49_RX_LPI_SMr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008394, (_val), (_mask))
 
 /* Transmit sleep timer count value register */
 #define READ_WC40_EEE_USERB0_TX_SLEEP_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008395, (_val))
 #define WRITE_WC40_EEE_USERB0_TX_SLEEP_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008395, (_val))
 #define MODIFY_WC40_EEE_USERB0_TX_SLEEP_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008395, (_val), (_mask))
 
 /* Transmit sleep timer count value register */
 #define READ_WC40_EEE_USERB0_CL49_TX_SLEEP_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008396, (_val))
 #define WRITE_WC40_EEE_USERB0_CL49_TX_SLEEP_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008396, (_val))
 #define MODIFY_WC40_EEE_USERB0_CL49_TX_SLEEP_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008396, (_val), (_mask))
 
 /* Transmit wake timer count value register */
 #define READ_WC40_EEE_USERB0_TX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008397, (_val))
 #define WRITE_WC40_EEE_USERB0_TX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008397, (_val))
 #define MODIFY_WC40_EEE_USERB0_TX_WAKE_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008397, (_val), (_mask))
 
 /* Receive Quiet timer offset count value register */
 #define READ_WC40_EEE_USERB0_RX_OFFSET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008398, (_val))
 #define WRITE_WC40_EEE_USERB0_RX_OFFSET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008398, (_val))
 #define MODIFY_WC40_EEE_USERB0_RX_OFFSET_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008398, (_val), (_mask))
 
 /* Receive Wake timer fault recovery timer count value register */
 #define READ_WC40_EEE_USERB0_RX_WAKE_TIME_FAULT_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008399, (_val))
 #define WRITE_WC40_EEE_USERB0_RX_WAKE_TIME_FAULT_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008399, (_val))
 #define MODIFY_WC40_EEE_USERB0_RX_WAKE_TIME_FAULT_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008399, (_val), (_mask))
 
 /* Misc timer bits register */
 #define READ_WC40_EEE_USERB0_MISC_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000839a, (_val))
 #define WRITE_WC40_EEE_USERB0_MISC_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000839a, (_val))
 #define MODIFY_WC40_EEE_USERB0_MISC_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000839a, (_val), (_mask))
 
 /* EEE lpi hysteresis/sigdet filter register */
 #define READ_WC40_EEE_USERB0_EEE_HYST_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000839b, (_val))
 #define WRITE_WC40_EEE_USERB0_EEE_HYST_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000839b, (_val))
 #define MODIFY_WC40_EEE_USERB0_EEE_HYST_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000839b, (_val), (_mask))
 
 /* EEE control override register */
 #define READ_WC40_EEE_USERB0_EEE_OVERRIDE_CTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000839c, (_val))
 #define WRITE_WC40_EEE_USERB0_EEE_OVERRIDE_CTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000839c, (_val))
 #define MODIFY_WC40_EEE_USERB0_EEE_OVERRIDE_CTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000839c, (_val), (_mask))
 
 /* EEE control register1 */
 #define READ_WC40_EEE_USERB0_EEE_COMBO_CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000839d, (_val))
 #define WRITE_WC40_EEE_USERB0_EEE_COMBO_CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000839d, (_val))
 #define MODIFY_WC40_EEE_USERB0_EEE_COMBO_CONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000839d, (_val), (_mask))
 
 /* XGMII/Cl49 LPI characters */
 #define READ_WC40_EEE_USERB0_CL49_EEE_CHARr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000839e, (_val))
 #define WRITE_WC40_EEE_USERB0_CL49_EEE_CHARr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000839e, (_val))
 #define MODIFY_WC40_EEE_USERB0_CL49_EEE_CHARr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000839e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_EEE_UserB1
  */
 
 /* EEE Cl37 BAM Control Register */
 #define READ_WC40_EEE_USERB1_EEE_AN_CTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083a0, (_val))
 #define WRITE_WC40_EEE_USERB1_EEE_AN_CTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083a0, (_val))
 #define MODIFY_WC40_EEE_USERB1_EEE_AN_CTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083a0, (_val), (_mask))
 
 /* EEE UP1 Register */
 #define READ_WC40_EEE_USERB1_EEE_UP1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083a1, (_val))
 #define WRITE_WC40_EEE_USERB1_EEE_UP1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083a1, (_val))
 #define MODIFY_WC40_EEE_USERB1_EEE_UP1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083a1, (_val), (_mask))
 
 /* EEE UP2 Register */
 #define READ_WC40_EEE_USERB1_EEE_UP2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083a2, (_val))
 #define WRITE_WC40_EEE_USERB1_EEE_UP2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083a2, (_val))
 #define MODIFY_WC40_EEE_USERB1_EEE_UP2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083a2, (_val), (_mask))
 
 /* EEE UP3 Register */
 #define READ_WC40_EEE_USERB1_EEE_UP3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083a3, (_val))
 #define WRITE_WC40_EEE_USERB1_EEE_UP3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083a3, (_val))
 #define MODIFY_WC40_EEE_USERB1_EEE_UP3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083a3, (_val), (_mask))
 
 /* Link Partner EEE UP1 Register */
 #define READ_WC40_EEE_USERB1_LP_EEE_UP1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083a4, (_val))
 #define WRITE_WC40_EEE_USERB1_LP_EEE_UP1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083a4, (_val))
 #define MODIFY_WC40_EEE_USERB1_LP_EEE_UP1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083a4, (_val), (_mask))
 
 /* Link Partner UP2 Register */
 #define READ_WC40_EEE_USERB1_LP_EEE_UP2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083a5, (_val))
 #define WRITE_WC40_EEE_USERB1_LP_EEE_UP2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083a5, (_val))
 #define MODIFY_WC40_EEE_USERB1_LP_EEE_UP2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083a5, (_val), (_mask))
 
 /* Link Partner UP3 Register */
 #define READ_WC40_EEE_USERB1_LP_EEE_UP3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083a6, (_val))
 #define WRITE_WC40_EEE_USERB1_LP_EEE_UP3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083a6, (_val))
 #define MODIFY_WC40_EEE_USERB1_LP_EEE_UP3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083a6, (_val), (_mask))
 
 /* EEE resolution status register */
 #define READ_WC40_EEE_USERB1_EEE_RES_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083a7, (_val))
 #define WRITE_WC40_EEE_USERB1_EEE_RES_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083a7, (_val))
 #define MODIFY_WC40_EEE_USERB1_EEE_RES_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083a7, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_tx66
  */
 
 /* 64/66 Encoder Control Register */
 #define READ_WC40_TX66_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083b0, (_val))
 #define WRITE_WC40_TX66_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083b0, (_val))
 #define MODIFY_WC40_TX66_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083b0, (_val), (_mask))
 
 /* 64/66 Encoder Status Register */
 #define READ_WC40_TX66_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083b1, (_val))
 #define WRITE_WC40_TX66_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083b1, (_val))
 #define MODIFY_WC40_TX66_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083b1, (_val), (_mask))
 
 /* 64/66 Encoder programmable control character */
 #define READ_WC40_TX66_PROGMMABLE_TLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083b2, (_val))
 #define WRITE_WC40_TX66_PROGMMABLE_TLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083b2, (_val))
 #define MODIFY_WC40_TX66_PROGMMABLE_TLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083b2, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_rx66
  */
 
 /* 64/66 Decoder control register */
 #define READ_WC40_RX66_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083c0, (_val))
 #define WRITE_WC40_RX66_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083c0, (_val))
 #define MODIFY_WC40_RX66_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083c0, (_val), (_mask))
 
 /* 64/66 Decoder status register */
 #define READ_WC40_RX66_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083c1, (_val))
 #define WRITE_WC40_RX66_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083c1, (_val))
 #define MODIFY_WC40_RX66_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083c1, (_val), (_mask))
 
 /* Sync code word bits 15:0 */
 #define READ_WC40_RX66_SCW0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083c2, (_val))
 #define WRITE_WC40_RX66_SCW0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083c2, (_val))
 #define MODIFY_WC40_RX66_SCW0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083c2, (_val), (_mask))
 
 /* Sync code word bits 31;16 */
 #define READ_WC40_RX66_SCW1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083c3, (_val))
 #define WRITE_WC40_RX66_SCW1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083c3, (_val))
 #define MODIFY_WC40_RX66_SCW1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083c3, (_val), (_mask))
 
 /* Sync code word bits 47:32 */
 #define READ_WC40_RX66_SCW2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083c4, (_val))
 #define WRITE_WC40_RX66_SCW2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083c4, (_val))
 #define MODIFY_WC40_RX66_SCW2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083c4, (_val), (_mask))
 
 /* Sync code word bits 63:48 */
 #define READ_WC40_RX66_SCW3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083c5, (_val))
 #define WRITE_WC40_RX66_SCW3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083c5, (_val))
 #define MODIFY_WC40_RX66_SCW3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083c5, (_val), (_mask))
 
 /* Sync code word mask bits 15:0 */
 #define READ_WC40_RX66_SCW0_MASKr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083c6, (_val))
 #define WRITE_WC40_RX66_SCW0_MASKr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083c6, (_val))
 #define MODIFY_WC40_RX66_SCW0_MASKr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083c6, (_val), (_mask))
 
 /* Sync code word mask bits 31;16 */
 #define READ_WC40_RX66_SCW1_MASKr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083c7, (_val))
 #define WRITE_WC40_RX66_SCW1_MASKr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083c7, (_val))
 #define MODIFY_WC40_RX66_SCW1_MASKr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083c7, (_val), (_mask))
 
 /* Sync code word mask bits 47:32 */
 #define READ_WC40_RX66_SCW2_MASKr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083c8, (_val))
 #define WRITE_WC40_RX66_SCW2_MASKr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083c8, (_val))
 #define MODIFY_WC40_RX66_SCW2_MASKr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083c8, (_val), (_mask))
 
 /* Sync code word mask bits 63:48 */
 #define READ_WC40_RX66_SCW3_MASKr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083c9, (_val))
 #define WRITE_WC40_RX66_SCW3_MASKr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083c9, (_val))
 #define MODIFY_WC40_RX66_SCW3_MASKr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083c9, (_val), (_mask))
 
 /* Sync bits and sync mask bits */
 #define READ_WC40_RX66_SYNCBITSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083ca, (_val))
 #define WRITE_WC40_RX66_SYNCBITSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083ca, (_val))
 #define MODIFY_WC40_RX66_SYNCBITSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083ca, (_val), (_mask))
 
 /* Sync code word statemachine control register */
 #define READ_WC40_RX66_SCWCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083cb, (_val))
 #define WRITE_WC40_RX66_SCWCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083cb, (_val))
 #define MODIFY_WC40_RX66_SCWCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083cb, (_val), (_mask))
 
 /* Clock Comp event counter */
 #define READ_WC40_RX66_CC_EVENTCOUNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083cc, (_val))
 #define WRITE_WC40_RX66_CC_EVENTCOUNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083cc, (_val))
 #define MODIFY_WC40_RX66_CC_EVENTCOUNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083cc, (_val), (_mask))
 
 /* CW=SCW counter & skew position */
 #define READ_WC40_RX66_SCWCOUNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083cd, (_val))
 #define WRITE_WC40_RX66_SCWCOUNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083cd, (_val))
 #define MODIFY_WC40_RX66_SCWCOUNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083cd, (_val), (_mask))
 
 /* scw & K-code group error counters */
 #define READ_WC40_RX66_ERRCOUNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083ce, (_val))
 #define WRITE_WC40_RX66_ERRCOUNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083ce, (_val))
 #define MODIFY_WC40_RX66_ERRCOUNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083ce, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_LnTxBert
  */
 
 /* Tx Bert control register */
 #define READ_WC40_LNTXBERT_TXBERTCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083d0, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083d0, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTCTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083d0, (_val), (_mask))
 
 /* Tx Bert SOP, EOP definition register */
 #define READ_WC40_LNTXBERT_TXBERTSOPEOPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083d1, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTSOPEOPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083d1, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTSOPEOPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083d1, (_val), (_mask))
 
 /* Packet size configuration 0 register */
 #define READ_WC40_LNTXBERT_TXBERTSIZE0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083d2, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTSIZE0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083d2, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTSIZE0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083d2, (_val), (_mask))
 
 /* Packet size configuration 1 register */
 #define READ_WC40_LNTXBERT_TXBERTSIZE1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083d3, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTSIZE1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083d3, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTSIZE1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083d3, (_val), (_mask))
 
 /* Packet size configuration 2 register */
 #define READ_WC40_LNTXBERT_TXBERTSIZE2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083d4, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTSIZE2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083d4, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTSIZE2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083d4, (_val), (_mask))
 
 /* IPG 0 definition register */
 #define READ_WC40_LNTXBERT_TXBERTIPG0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083d5, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTIPG0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083d5, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTIPG0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083d5, (_val), (_mask))
 
 /* IPG 1 definition register */
 #define READ_WC40_LNTXBERT_TXBERTIPG1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083d6, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTIPG1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083d6, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTIPG1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083d6, (_val), (_mask))
 
 /* Transmitted byte count upper 16 bits register */
 #define READ_WC40_LNTXBERT_TXBERTBYTEUr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083d7, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTBYTEUr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083d7, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTBYTEUr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083d7, (_val), (_mask))
 
 /* Transmitted byte count lower 16 bits register */
 #define READ_WC40_LNTXBERT_TXBERTBYTELr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083d8, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTBYTELr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083d8, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTBYTELr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083d8, (_val), (_mask))
 
 /* Transmitted packet count upper 16 bits register */
 #define READ_WC40_LNTXBERT_TXBERTPACKETUr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083d9, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTPACKETUr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083d9, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTPACKETUr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083d9, (_val), (_mask))
 
 /* Transmitted packet count lower 16 bits register */
 #define READ_WC40_LNTXBERT_TXBERTPACKETLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083da, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTPACKETLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083da, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTPACKETLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083da, (_val), (_mask))
 
 /* Tx Bert control1 register */
 #define READ_WC40_LNTXBERT_TXBERTCTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083db, (_val))
 #define WRITE_WC40_LNTXBERT_TXBERTCTRL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083db, (_val))
 #define MODIFY_WC40_LNTXBERT_TXBERTCTRL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083db, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_LnRxBert
  */
 
 /* Rx Bert control register */
 #define READ_WC40_LNRXBERT_RXBERTCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083e0, (_val))
 #define WRITE_WC40_LNRXBERT_RXBERTCTRLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083e0, (_val))
 #define MODIFY_WC40_LNRXBERT_RXBERTCTRLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083e0, (_val), (_mask))
 
 /* Rx Bert SOP, EOP definition register */
 #define READ_WC40_LNRXBERT_RXBERTSOPEOPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083e1, (_val))
 #define WRITE_WC40_LNRXBERT_RXBERTSOPEOPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083e1, (_val))
 #define MODIFY_WC40_LNRXBERT_RXBERTSOPEOPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083e1, (_val), (_mask))
 
 /* Received byte count upper 16 bits register */
 #define READ_WC40_LNRXBERT_RXBERTBYTEUr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083e7, (_val))
 #define WRITE_WC40_LNRXBERT_RXBERTBYTEUr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083e7, (_val))
 #define MODIFY_WC40_LNRXBERT_RXBERTBYTEUr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083e7, (_val), (_mask))
 
 /* Received bytes count lower 16 bits register */
 #define READ_WC40_LNRXBERT_RXBERTBYTELr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083e8, (_val))
 #define WRITE_WC40_LNRXBERT_RXBERTBYTELr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083e8, (_val))
 #define MODIFY_WC40_LNRXBERT_RXBERTBYTELr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083e8, (_val), (_mask))
 
 /* Received packet count upper 16 bits register */
 #define READ_WC40_LNRXBERT_RXBERTPACKETUr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083e9, (_val))
 #define WRITE_WC40_LNRXBERT_RXBERTPACKETUr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083e9, (_val))
 #define MODIFY_WC40_LNRXBERT_RXBERTPACKETUr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083e9, (_val), (_mask))
 
 /* Received packet count lower 16 bits register */
 #define READ_WC40_LNRXBERT_RXBERTPACKETLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083ea, (_val))
 #define WRITE_WC40_LNRXBERT_RXBERTPACKETLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083ea, (_val))
 #define MODIFY_WC40_LNRXBERT_RXBERTPACKETLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083ea, (_val), (_mask))
 
 /* Received bits error count */
 #define READ_WC40_LNRXBERT_RXBERTBITERRr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083eb, (_val))
 #define WRITE_WC40_LNRXBERT_RXBERTBITERRr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083eb, (_val))
 #define MODIFY_WC40_LNRXBERT_RXBERTBITERRr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083eb, (_val), (_mask))
 
 /* Received bytes error count */
 #define READ_WC40_LNRXBERT_RXBERTBYTEERRr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083ec, (_val))
 #define WRITE_WC40_LNRXBERT_RXBERTBYTEERRr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083ec, (_val))
 #define MODIFY_WC40_LNRXBERT_RXBERTBYTEERRr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083ec, (_val), (_mask))
 
 /* Received packets error count */
 #define READ_WC40_LNRXBERT_RXBERTPKTERRr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083ed, (_val))
 #define WRITE_WC40_LNRXBERT_RXBERTPKTERRr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083ed, (_val))
 #define MODIFY_WC40_LNRXBERT_RXBERTPKTERRr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083ed, (_val), (_mask))
 
 /* Receive Status */
 #define READ_WC40_LNRXBERT_RXBERTSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x000083ee, (_val))
 #define WRITE_WC40_LNRXBERT_RXBERTSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x000083ee, (_val))
 #define MODIFY_WC40_LNRXBERT_RXBERTSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x000083ee, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_FX100
  */
 
 /* 100FX control register 1 */
 #define READ_WC40_FX100_CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008400, (_val))
 #define WRITE_WC40_FX100_CONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008400, (_val))
 #define MODIFY_WC40_FX100_CONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008400, (_val), (_mask))
 
 /* 100FX control register 2 */
 #define READ_WC40_FX100_CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008401, (_val))
 #define WRITE_WC40_FX100_CONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008401, (_val))
 #define MODIFY_WC40_FX100_CONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008401, (_val), (_mask))
 
 /* 100FX control register 3 */
 #define READ_WC40_FX100_CONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008402, (_val))
 #define WRITE_WC40_FX100_CONTROL3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008402, (_val))
 #define MODIFY_WC40_FX100_CONTROL3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008402, (_val), (_mask))
 
 /* 100FX status register 1 */
 #define READ_WC40_FX100_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008403, (_val))
 #define WRITE_WC40_FX100_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008403, (_val))
 #define MODIFY_WC40_FX100_STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008403, (_val), (_mask))
 
 /* 100FX status register 3 */
 #define READ_WC40_FX100_STATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008405, (_val))
 #define WRITE_WC40_FX100_STATUS3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008405, (_val))
 #define MODIFY_WC40_FX100_STATUS3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008405, (_val), (_mask))
 
 /* 100FX status register 4 */
 #define READ_WC40_FX100_STATUS4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008406, (_val))
 #define WRITE_WC40_FX100_STATUS4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008406, (_val))
 #define MODIFY_WC40_FX100_STATUS4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008406, (_val), (_mask))
 
 /* 100FX idle pattern register 1 */
 #define READ_WC40_FX100_FX100IDLE1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008407, (_val))
 #define WRITE_WC40_FX100_FX100IDLE1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008407, (_val))
 #define MODIFY_WC40_FX100_FX100IDLE1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008407, (_val), (_mask))
 
 /* 100FX idle pattern register 2 */
 #define READ_WC40_FX100_FX100IDLE2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008408, (_val))
 #define WRITE_WC40_FX100_FX100IDLE2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008408, (_val))
 #define MODIFY_WC40_FX100_FX100IDLE2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008408, (_val), (_mask))
 
 /* 100FX idle status register */
 #define READ_WC40_FX100_FX100IDLESTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008409, (_val))
 #define WRITE_WC40_FX100_FX100IDLESTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008409, (_val))
 #define MODIFY_WC40_FX100_FX100IDLESTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008409, (_val), (_mask))
 
 /* 100FX idle threshold register */
 #define READ_WC40_FX100_FX100IDLETHRESr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000840a, (_val))
 #define WRITE_WC40_FX100_FX100IDLETHRESr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000840a, (_val))
 #define MODIFY_WC40_FX100_FX100IDLETHRESr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000840a, (_val), (_mask))
 
 /* 100FX lock timer register */
 #define READ_WC40_FX100_FX100LOCKTMRr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000840b, (_val))
 #define WRITE_WC40_FX100_FX100LOCKTMRr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000840b, (_val))
 #define MODIFY_WC40_FX100_FX100LOCKTMRr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000840b, (_val), (_mask))
 
 /* 100FX link timer register */
 #define READ_WC40_FX100_FX100LINKTMRr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000840c, (_val))
 #define WRITE_WC40_FX100_FX100LINKTMRr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000840c, (_val))
 #define MODIFY_WC40_FX100_FX100LINKTMRr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000840c, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_EEE_TimerB0
  */
 
 /* Group1 Trasnmit Refresh timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP1_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008410, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP1_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008410, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP1_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008410, (_val), (_mask))
 
 /* Group1 Trasnmit Quiet timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP1_TX_QUIET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008411, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP1_TX_QUIET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008411, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP1_TX_QUIET_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008411, (_val), (_mask))
 
 /* Group1 Receive Wake timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP1_RX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008412, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP1_RX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008412, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP1_RX_WAKE_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008412, (_val), (_mask))
 
 /* Group2 Trasnmit Refresh timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP2_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008413, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP2_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008413, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP2_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008413, (_val), (_mask))
 
 /* Group2 Trasnmit Quiet timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP2_TX_QUIET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008414, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP2_TX_QUIET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008414, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP2_TX_QUIET_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008414, (_val), (_mask))
 
 /* Group2 Receive Wake timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP2_RX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008415, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP2_RX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008415, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP2_RX_WAKE_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008415, (_val), (_mask))
 
 /* Group3 Trasnmit Refresh timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP3_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008416, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP3_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008416, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP3_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008416, (_val), (_mask))
 
 /* Group3 Trasnmit Quiet timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP3_TX_QUIET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008417, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP3_TX_QUIET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008417, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP3_TX_QUIET_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008417, (_val), (_mask))
 
 /* Group3 Receive Wake timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP3_RX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008418, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP3_RX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008418, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP3_RX_WAKE_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008418, (_val), (_mask))
 
 /* Group4 Trasnmit Refresh timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP4_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008419, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP4_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008419, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP4_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008419, (_val), (_mask))
 
 /* Group4 Trasnmit Quiet timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP4_TX_QUIET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000841a, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP4_TX_QUIET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000841a, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP4_TX_QUIET_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000841a, (_val), (_mask))
 
 /* Group4 Receive Wake timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP4_RX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000841b, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP4_RX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000841b, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP4_RX_WAKE_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000841b, (_val), (_mask))
 
 /* Group5 Trasnmit Refresh timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP5_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000841c, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP5_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000841c, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP5_TX_REFRESH_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000841c, (_val), (_mask))
 
 /* Group5 Trasnmit Quiet timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP5_TX_QUIET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000841d, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP5_TX_QUIET_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000841d, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP5_TX_QUIET_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000841d, (_val), (_mask))
 
 /* Group5 Receive Wake timer count value register */
 #define READ_WC40_EEE_TIMERB0_GRP5_RX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000841e, (_val))
 #define WRITE_WC40_EEE_TIMERB0_GRP5_RX_WAKE_TIMERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000841e, (_val))
 #define MODIFY_WC40_EEE_TIMERB0_GRP5_RX_WAKE_TIMERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000841e, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_CL82_UserB0
  */
 
 /* cl82 tx control 1 register */
 #define READ_WC40_CL82_USERB0_TX_CONTROL_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008420, (_val))
 #define WRITE_WC40_CL82_USERB0_TX_CONTROL_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008420, (_val))
 #define MODIFY_WC40_CL82_USERB0_TX_CONTROL_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008420, (_val), (_mask))
 
 /* cl82 tx control 2 register */
 #define READ_WC40_CL82_USERB0_TX_CONTROL_2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008421, (_val))
 #define WRITE_WC40_CL82_USERB0_TX_CONTROL_2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008421, (_val))
 #define MODIFY_WC40_CL82_USERB0_TX_CONTROL_2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008421, (_val), (_mask))
 
 /* cl82 tx status 1 register */
 #define READ_WC40_CL82_USERB0_TX_STATUS_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008422, (_val))
 #define WRITE_WC40_CL82_USERB0_TX_STATUS_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008422, (_val))
 #define MODIFY_WC40_CL82_USERB0_TX_STATUS_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008422, (_val), (_mask))
 
 /* cl82 tx status 2 register */
 #define READ_WC40_CL82_USERB0_TX_STATUS_2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008423, (_val))
 #define WRITE_WC40_CL82_USERB0_TX_STATUS_2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008423, (_val))
 #define MODIFY_WC40_CL82_USERB0_TX_STATUS_2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008423, (_val), (_mask))
 
 /* cl82 Rx status 1 register */
 #define READ_WC40_CL82_USERB0_RX_STATUS_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008424, (_val))
 #define WRITE_WC40_CL82_USERB0_RX_STATUS_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008424, (_val))
 #define MODIFY_WC40_CL82_USERB0_RX_STATUS_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008424, (_val), (_mask))
 
 /* cl82 Rx status 2 register */
 #define READ_WC40_CL82_USERB0_RX_STATUS_2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008425, (_val))
 #define WRITE_WC40_CL82_USERB0_RX_STATUS_2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008425, (_val))
 #define MODIFY_WC40_CL82_USERB0_RX_STATUS_2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008425, (_val), (_mask))
 
 /* cl82 Rx status 3 register */
 #define READ_WC40_CL82_USERB0_RX_STATUS_3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008426, (_val))
 #define WRITE_WC40_CL82_USERB0_RX_STATUS_3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008426, (_val))
 #define MODIFY_WC40_CL82_USERB0_RX_STATUS_3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008426, (_val), (_mask))
 
 /* cl82 Rx control 1 register */
 #define READ_WC40_CL82_USERB0_RX_CONTROL_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008427, (_val))
 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008427, (_val))
 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008427, (_val), (_mask))
 
 /* cl82 RX control 2 register */
 #define READ_WC40_CL82_USERB0_RX_CONTROL_2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008428, (_val))
 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008428, (_val))
 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008428, (_val), (_mask))
 
 /* cl82 RX control 3 register */
 #define READ_WC40_CL82_USERB0_RX_CONTROL_3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008429, (_val))
 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008429, (_val))
 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008429, (_val), (_mask))
 
 /* cl82 RX control 4 register */
 #define READ_WC40_CL82_USERB0_RX_CONTROL_4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000842a, (_val))
 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000842a, (_val))
 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000842a, (_val), (_mask))
 
 /* cl82 RX control 5 register */
 #define READ_WC40_CL82_USERB0_RX_CONTROL_5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000842b, (_val))
 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000842b, (_val))
 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000842b, (_val), (_mask))
 
 /* cl82 RX control 6 register */
 #define READ_WC40_CL82_USERB0_RX_CONTROL_6r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000842c, (_val))
 #define WRITE_WC40_CL82_USERB0_RX_CONTROL_6r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000842c, (_val))
 #define MODIFY_WC40_CL82_USERB0_RX_CONTROL_6r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000842c, (_val), (_mask))
 
 /* cl82 Rx status 4 register */
 #define READ_WC40_CL82_USERB0_RX_STATUS_4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000842d, (_val))
 #define WRITE_WC40_CL82_USERB0_RX_STATUS_4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000842d, (_val))
 #define MODIFY_WC40_CL82_USERB0_RX_STATUS_4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000842d, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_CL82_UserB1
  */
 
 /* cl82 RX control 7 register */
 #define READ_WC40_CL82_USERB1_RX_CONTROL_7r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008430, (_val))
 #define WRITE_WC40_CL82_USERB1_RX_CONTROL_7r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008430, (_val))
 #define MODIFY_WC40_CL82_USERB1_RX_CONTROL_7r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008430, (_val), (_mask))
 
 /* cl82 Rx status 5 register */
 #define READ_WC40_CL82_USERB1_RX_STATUS_5r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008431, (_val))
 #define WRITE_WC40_CL82_USERB1_RX_STATUS_5r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008431, (_val))
 #define MODIFY_WC40_CL82_USERB1_RX_STATUS_5r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008431, (_val), (_mask))
 
 /* cl82 TX control 3 register */
 #define READ_WC40_CL82_USERB1_TX_CONTROL_3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008432, (_val))
 #define WRITE_WC40_CL82_USERB1_TX_CONTROL_3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008432, (_val))
 #define MODIFY_WC40_CL82_USERB1_TX_CONTROL_3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008432, (_val), (_mask))
 
 /* cl82 TX status 3 register */
 #define READ_WC40_CL82_USERB1_TX_STATUS_3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008433, (_val))
 #define WRITE_WC40_CL82_USERB1_TX_STATUS_3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008433, (_val))
 #define MODIFY_WC40_CL82_USERB1_TX_STATUS_3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008433, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_rx66b1
  */
 
 /* BRCM/cl49 Control register */
 #define READ_WC40_RX66B1_BRCM_CL49_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x00008440, (_val))
 #define WRITE_WC40_RX66B1_BRCM_CL49_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x00008440, (_val))
 #define MODIFY_WC40_RX66B1_BRCM_CL49_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x00008440, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XFI_BD0
  */
 
 /* PMD and PCS Status Register */
 #define READ_WC40_XFI_BD0_PMD_AND_PCS_STATUS_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd04, (_val))
 #define WRITE_WC40_XFI_BD0_PMD_AND_PCS_STATUS_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd04, (_val))
 #define MODIFY_WC40_XFI_BD0_PMD_AND_PCS_STATUS_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd04, (_val), (_mask))
 
 /* PMD Optics Digital Control Register */
 #define READ_WC40_XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd08, (_val))
 #define WRITE_WC40_XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd08, (_val))
 #define MODIFY_WC40_XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd08, (_val), (_mask))
 
 /* PMD Digital Status Register */
 #define READ_WC40_XFI_BD0_PMD_DIGITAL_STATUS_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd09, (_val))
 #define WRITE_WC40_XFI_BD0_PMD_DIGITAL_STATUS_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd09, (_val))
 #define MODIFY_WC40_XFI_BD0_PMD_DIGITAL_STATUS_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd09, (_val), (_mask))
 
 /* PMD and PCS Test Control Register */
 #define READ_WC40_XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd0a, (_val))
 #define WRITE_WC40_XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd0a, (_val))
 #define MODIFY_WC40_XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd0a, (_val), (_mask))
 
 /* PMD General Purpose TX Pattern Register 0 */
 #define READ_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd0c, (_val))
 #define WRITE_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd0c, (_val))
 #define MODIFY_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd0c, (_val), (_mask))
 
 /* PMD General Purpose TX Pattern Register 1 */
 #define READ_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd0d, (_val))
 #define WRITE_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd0d, (_val))
 #define MODIFY_WC40_XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd0d, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_XFI_BD1
  */
 
 /* PRBS 31 Test Window 1 Register */
 #define READ_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd20, (_val))
 #define WRITE_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd20, (_val))
 #define MODIFY_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd20, (_val), (_mask))
 
 /* PRBS 31 Test Window 2 Register */
 #define READ_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd21, (_val))
 #define WRITE_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd21, (_val))
 #define MODIFY_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd21, (_val), (_mask))
 
 /* User PRBS Control 0 Register */
 #define READ_WC40_XFI_BD1_USER_PRBS_CONTROL_0_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd24, (_val))
 #define WRITE_WC40_XFI_BD1_USER_PRBS_CONTROL_0_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd24, (_val))
 #define MODIFY_WC40_XFI_BD1_USER_PRBS_CONTROL_0_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd24, (_val), (_mask))
 
 /* User PRBS Status 0 Register */
 #define READ_WC40_XFI_BD1_USER_PRBS_STATUS_0_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd25, (_val))
 #define WRITE_WC40_XFI_BD1_USER_PRBS_STATUS_0_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd25, (_val))
 #define MODIFY_WC40_XFI_BD1_USER_PRBS_STATUS_0_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd25, (_val), (_mask))
 
 /* PRBS 31 Test Window 0 Register */
 #define READ_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd26, (_val))
 #define WRITE_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd26, (_val))
 #define MODIFY_WC40_XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd26, (_val), (_mask))
 
 /* Pattern insertion control register */
 #define READ_WC40_XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000cd28, (_val))
 #define WRITE_WC40_XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000cd28, (_val))
 #define MODIFY_WC40_XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000cd28, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_microBlk
  */
 
 /* ramWord Register */
 #define READ_WC40_MICROBLK_RAMWORDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffc0, (_val))
 #define WRITE_WC40_MICROBLK_RAMWORDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffc0, (_val))
 #define MODIFY_WC40_MICROBLK_RAMWORDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffc0, (_val), (_mask))
 
 /* Adress Register */
 #define READ_WC40_MICROBLK_ADDRESSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffc1, (_val))
 #define WRITE_WC40_MICROBLK_ADDRESSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffc1, (_val))
 #define MODIFY_WC40_MICROBLK_ADDRESSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffc1, (_val), (_mask))
 
 /* Command Register */
 #define READ_WC40_MICROBLK_COMMANDr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffc2, (_val))
 #define WRITE_WC40_MICROBLK_COMMANDr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffc2, (_val))
 #define MODIFY_WC40_MICROBLK_COMMANDr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffc2, (_val), (_mask))
 
 /* Write Data Register */
 #define READ_WC40_MICROBLK_WRDATAr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffc3, (_val))
 #define WRITE_WC40_MICROBLK_WRDATAr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffc3, (_val))
 #define MODIFY_WC40_MICROBLK_WRDATAr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffc3, (_val), (_mask))
 
 /* Read Data Register */
 #define READ_WC40_MICROBLK_RDDATAr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffc4, (_val))
 #define WRITE_WC40_MICROBLK_RDDATAr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffc4, (_val))
 #define MODIFY_WC40_MICROBLK_RDDATAr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffc4, (_val), (_mask))
 
 /* MDIO to 8051 FSM Status Register */
 #define READ_WC40_MICROBLK_DOWNLOAD_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffc5, (_val))
 #define WRITE_WC40_MICROBLK_DOWNLOAD_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffc5, (_val))
 #define MODIFY_WC40_MICROBLK_DOWNLOAD_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffc5, (_val), (_mask))
 
 /* 8051 SFR FSM status */
 #define READ_WC40_MICROBLK_SFR_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffc6, (_val))
 #define WRITE_WC40_MICROBLK_SFR_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffc6, (_val))
 #define MODIFY_WC40_MICROBLK_SFR_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffc6, (_val), (_mask))
 
 /* Command Register 4 */
 #define READ_WC40_MICROBLK_COMMAND4r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffc7, (_val))
 #define WRITE_WC40_MICROBLK_COMMAND4r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffc7, (_val))
 #define MODIFY_WC40_MICROBLK_COMMAND4r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffc7, (_val), (_mask))
 
 /* External station to uC mailbox */
 #define READ_WC40_MICROBLK_MDIO_UC_MAILBOXr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffc8, (_val))
 #define WRITE_WC40_MICROBLK_MDIO_UC_MAILBOXr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffc8, (_val))
 #define MODIFY_WC40_MICROBLK_MDIO_UC_MAILBOXr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffc8, (_val), (_mask))
 
 /* uC to external station mailbox */
 #define READ_WC40_MICROBLK_UC_MDIO_MAILBOXr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffc9, (_val))
 #define WRITE_WC40_MICROBLK_UC_MDIO_MAILBOXr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffc9, (_val))
 #define MODIFY_WC40_MICROBLK_UC_MDIO_MAILBOXr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffc9, (_val), (_mask))
 
 /* Command Register 2 */
 #define READ_WC40_MICROBLK_COMMAND2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffca, (_val))
 #define WRITE_WC40_MICROBLK_COMMAND2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffca, (_val))
 #define MODIFY_WC40_MICROBLK_COMMAND2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffca, (_val), (_mask))
 
 /* wdog_evnt_cnt Register */
 #define READ_WC40_MICROBLK_WDOG_EVNT_CNTr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffcb, (_val))
 #define WRITE_WC40_MICROBLK_WDOG_EVNT_CNTr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffcb, (_val))
 #define MODIFY_WC40_MICROBLK_WDOG_EVNT_CNTr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffcb, (_val), (_mask))
 
 /* Command Register 3 */
 #define READ_WC40_MICROBLK_COMMAND3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffcc, (_val))
 #define WRITE_WC40_MICROBLK_COMMAND3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffcc, (_val))
 #define MODIFY_WC40_MICROBLK_COMMAND3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffcc, (_val), (_mask))
 
 /* Muxed Micro Timer (lower timer[15:0]) */
 #define READ_WC40_MICROBLK_TIMER_LOWER16r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffcd, (_val))
 #define WRITE_WC40_MICROBLK_TIMER_LOWER16r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffcd, (_val))
 #define MODIFY_WC40_MICROBLK_TIMER_LOWER16r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffcd, (_val), (_mask))
 
 /* Muxed Micro Timer (upper timer[31:16]) */
 #define READ_WC40_MICROBLK_TIMER_UPPER16r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffce, (_val))
 #define WRITE_WC40_MICROBLK_TIMER_UPPER16r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffce, (_val))
 #define MODIFY_WC40_MICROBLK_TIMER_UPPER16r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffce, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_aerBlk
  */
 
 /* Address Expansion Register */
 #define READ_WC40_AERBLK_AERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffde, (_val))
 #define WRITE_WC40_AERBLK_AERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffde, (_val))
 #define MODIFY_WC40_AERBLK_AERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffde, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_USER_Combo_IEEE0
  */
 
 /* IEEE MII control register */
 #define READ_WC40_COMBO_IEEE0_MIICNTLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffe0, (_val))
 #define WRITE_WC40_COMBO_IEEE0_MIICNTLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffe0, (_val))
 #define MODIFY_WC40_COMBO_IEEE0_MIICNTLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffe0, (_val), (_mask))
 
 /* IEEE MII status register */
 #define READ_WC40_COMBO_IEEE0_MIISTATr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffe1, (_val))
 #define WRITE_WC40_COMBO_IEEE0_MIISTATr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffe1, (_val))
 #define MODIFY_WC40_COMBO_IEEE0_MIISTATr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffe1, (_val), (_mask))
 
 /* IEEE phy ID LSByte register */
 #define READ_WC40_COMBO_IEEE0_ID1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffe2, (_val))
 #define WRITE_WC40_COMBO_IEEE0_ID1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffe2, (_val))
 #define MODIFY_WC40_COMBO_IEEE0_ID1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffe2, (_val), (_mask))
 
 /* IEEE phy ID MSByte register */
 #define READ_WC40_COMBO_IEEE0_ID2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffe3, (_val))
 #define WRITE_WC40_COMBO_IEEE0_ID2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffe3, (_val))
 #define MODIFY_WC40_COMBO_IEEE0_ID2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffe3, (_val), (_mask))
 
 /* IEEE auto-negotiation advertised abilities register */
 #define READ_WC40_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffe4, (_val))
 #define WRITE_WC40_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffe4, (_val))
 #define MODIFY_WC40_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffe4, (_val), (_mask))
 
 /* IEEE auto-negotiation link partner abilities register */
 #define READ_WC40_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffe5, (_val))
 #define WRITE_WC40_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffe5, (_val))
 #define MODIFY_WC40_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffe5, (_val), (_mask))
 
 /* IEEE auto-negotiation expansion register */
 #define READ_WC40_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffe6, (_val))
 #define WRITE_WC40_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffe6, (_val))
 #define MODIFY_WC40_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffe6, (_val), (_mask))
 
 /* IEEE auto-negotiation next page register */
 #define READ_WC40_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffe7, (_val))
 #define WRITE_WC40_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffe7, (_val))
 #define MODIFY_WC40_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffe7, (_val), (_mask))
 
 /* IEEE auto-negotiation link partner next page register */
 #define READ_WC40_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffe8, (_val))
 #define WRITE_WC40_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffe8, (_val))
 #define MODIFY_WC40_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffe8, (_val), (_mask))
 
 /* IEEE MII extended status register */
 #define READ_WC40_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0000ffef, (_val))
 #define WRITE_WC40_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0000ffef, (_val))
 #define MODIFY_WC40_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0000ffef, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_PMD_PMD_ieee0Blk
  */
 
 /* PMD Control 1 */
 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000000, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000000, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000000, (_val), (_mask))
 
 /* PMD Status 1 */
 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000001, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000001, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000001, (_val), (_mask))
 
 /* PMD Device ID [15:0] */
 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000002, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000002, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000002, (_val), (_mask))
 
 /* PMD Device ID [31:16] */
 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000003, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000003, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000003, (_val), (_mask))
 
 /* PMD Speed Ability */
 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000004, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000004, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000004, (_val), (_mask))
 
 /* PMD Devices in Package 1 */
 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000005, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000005, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000005, (_val), (_mask))
 
 /* PMD Devices in Package 2 */
 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000006, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000006, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000006, (_val), (_mask))
 
 /* PMD Control 2 */
 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000007, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000007, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000007, (_val), (_mask))
 
 /* PMD Status 2 */
 #define READ_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000008, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000008, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000008, (_val), (_mask))
 
 /* PMD Transmit Disable */
 #define READ_WC40_PMD_IEEE0BLK_PMD_TXDISABLEr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000009, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_TXDISABLEr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000009, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_TXDISABLEr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000009, (_val), (_mask))
 
 /* PMD Receive Signal Detect */
 #define READ_WC40_PMD_IEEE0BLK_PMD_RXSIGDETr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0800000a, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_RXSIGDETr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0800000a, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_RXSIGDETr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0800000a, (_val), (_mask))
 
 /* PMD Extended Ability */
 #define READ_WC40_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0800000b, (_val))
 #define WRITE_WC40_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0800000b, (_val))
 #define MODIFY_WC40_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0800000b, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_PMD_PMD_ieee9Blk
  */
 
 /* TenGBASE_KR PMD control register 150 */
 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000096, (_val))
 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000096, (_val))
 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000096, (_val), (_mask))
 
 /* TenGBASE_KR PMD status register 151 */
 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000097, (_val))
 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000097, (_val))
 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000097, (_val), (_mask))
 
 /* TenGBASE_KR LP coefficient upd 152 */
 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000098, (_val))
 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000098, (_val))
 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000098, (_val), (_mask))
 
 /* TenGBASE_KR LP status report reg 153 */
 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x08000099, (_val))
 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x08000099, (_val))
 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x08000099, (_val), (_mask))
 
 /* TenGBASE_KR LD coefficient upd 154 */
 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0800009a, (_val))
 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0800009a, (_val))
 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0800009a, (_val), (_mask))
 
 /* TenGBASE_KR LD status report reg 155 */
 #define READ_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x0800009b, (_val))
 #define WRITE_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x0800009b, (_val))
 #define MODIFY_WC40_PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x0800009b, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_PMD_PMD_ieee10Blk
  */
 
 /* PMD 1000BASE-KX control */
 #define READ_WC40_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x080000a0, (_val))
 #define WRITE_WC40_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x080000a0, (_val))
 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x080000a0, (_val), (_mask))
 
 /* PMD 1000BASE-KX status */
 #define READ_WC40_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x080000a1, (_val))
 #define WRITE_WC40_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x080000a1, (_val))
 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x080000a1, (_val), (_mask))
 
 /* "FEC ability register" */
 #define READ_WC40_PMD_IEEE10BLK_PMD_FECABILITYr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x080000aa, (_val))
 #define WRITE_WC40_PMD_IEEE10BLK_PMD_FECABILITYr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x080000aa, (_val))
 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_FECABILITYr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x080000aa, (_val), (_mask))
 
 /* "FEC control register" */
 #define READ_WC40_PMD_IEEE10BLK_PMD_FECCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x080000ab, (_val))
 #define WRITE_WC40_PMD_IEEE10BLK_PMD_FECCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x080000ab, (_val))
 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_FECCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x080000ab, (_val), (_mask))
 
 /* "FEC corrected blocks counter [15:0]" */
 #define READ_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x080000ac, (_val))
 #define WRITE_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x080000ac, (_val))
 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x080000ac, (_val), (_mask))
 
 /* "FEC corrected blocks counter [31:16]" */
 #define READ_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSHr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x080000ad, (_val))
 #define WRITE_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSHr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x080000ad, (_val))
 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_CORRECTEDBLKSHr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x080000ad, (_val), (_mask))
 
 /* "FEC uncorrected blocks counter [15:0]" */
 #define READ_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x080000ae, (_val))
 #define WRITE_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x080000ae, (_val))
 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x080000ae, (_val), (_mask))
 
 /* "FEC uncorrected blocks counter [31:16]" */
 #define READ_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x080000af, (_val))
 #define WRITE_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x080000af, (_val))
 #define MODIFY_WC40_PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x080000af, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_PCS_PCS_ieee0Blk
  */
 
 /* PCS Control 1 */
 #define READ_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000000, (_val))
 #define WRITE_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000000, (_val))
 #define MODIFY_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000000, (_val), (_mask))
 
 /* PCS Status 1 */
 #define READ_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000001, (_val))
 #define WRITE_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000001, (_val))
 #define MODIFY_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000001, (_val), (_mask))
 
 /* PCS Control 2 */
 #define READ_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000007, (_val))
 #define WRITE_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000007, (_val))
 #define MODIFY_WC40_PCS_IEEE0BLK_PCS_IEEECONTROL2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000007, (_val), (_mask))
 
 /* P Status 2 */
 #define READ_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000008, (_val))
 #define WRITE_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000008, (_val))
 #define MODIFY_WC40_PCS_IEEE0BLK_PCS_IEEESTATUS2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000008, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_PCS_PCS_ieee1Blk
  */
 
 /* XGXS lane Status */
 #define READ_WC40_PCS_IEEE1BLK_PCS_LANESTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000018, (_val))
 #define WRITE_WC40_PCS_IEEE1BLK_PCS_LANESTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000018, (_val))
 #define MODIFY_WC40_PCS_IEEE1BLK_PCS_LANESTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000018, (_val), (_mask))
 
 /* XGXS Test Control */
 #define READ_WC40_PCS_IEEE1BLK_PCS_IEEETESTCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000019, (_val))
 #define WRITE_WC40_PCS_IEEE1BLK_PCS_IEEETESTCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000019, (_val))
 #define MODIFY_WC40_PCS_IEEE1BLK_PCS_IEEETESTCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000019, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_PCS_PCS_ieee2Blk
  */
 
 /* 10GBASE-R PCS status 1 */
 #define READ_WC40_PCS_IEEE2BLK_PCS_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000020, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_STATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000020, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_STATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000020, (_val), (_mask))
 
 /* 10GBASE-R PCS status 2 */
 #define READ_WC40_PCS_IEEE2BLK_PCS_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000021, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_STATUS2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000021, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_STATUS2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000021, (_val), (_mask))
 
 /* 10GBASE-R PCS test pattern seed A word bits 15:0 */
 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDA0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000022, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDA0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000022, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDA0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000022, (_val), (_mask))
 
 /* 10GBASE-R PCS test pattern seed A word bits 31;16 */
 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDA1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000023, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDA1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000023, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDA1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000023, (_val), (_mask))
 
 /* 10GBASE-R PCS test pattern seed A word bits 47:32 */
 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDA2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000024, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDA2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000024, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDA2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000024, (_val), (_mask))
 
 /* 10GBASE-R PCS test pattern seed A word bits 57:48 */
 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDA3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000025, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDA3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000025, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDA3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000025, (_val), (_mask))
 
 /* 10GBASE-R PCS test pattern seed B word bits 15:0 */
 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDB0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000026, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDB0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000026, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDB0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000026, (_val), (_mask))
 
 /* 10GBASE-R PCS test pattern seed B word bits 31;16 */
 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDB1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000027, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDB1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000027, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDB1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000027, (_val), (_mask))
 
 /* 10GBASE-R PCS test pattern seed B word bits 47:32 */
 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDB2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000028, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDB2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000028, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDB2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000028, (_val), (_mask))
 
 /* 10GBASE-R PCS test pattern seed B word bits 57:48 */
 #define READ_WC40_PCS_IEEE2BLK_PCS_SEEDB3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000029, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_SEEDB3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000029, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_SEEDB3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000029, (_val), (_mask))
 
 /* 10GBASE-R PCS test-pattern control */
 #define READ_WC40_PCS_IEEE2BLK_PCS_TPCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x1800002a, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_TPCONTROLr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x1800002a, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_TPCONTROLr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x1800002a, (_val), (_mask))
 
 /* 10GBASE-R PCS test pattern error counter */
 #define READ_WC40_PCS_IEEE2BLK_PCS_TPERRCOUNTERr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x1800002b, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_PCS_TPERRCOUNTERr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x1800002b, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_PCS_TPERRCOUNTERr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x1800002b, (_val), (_mask))
 
 /* 40G/100GBASE-R BER high order counter */
 #define READ_WC40_PCS_IEEE2BLK_BER_HOr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x1800002c, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_BER_HOr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x1800002c, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_BER_HOr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x1800002c, (_val), (_mask))
 
 /* 40G/100GBASE-R Errored blocks high order counter */
 #define READ_WC40_PCS_IEEE2BLK_ERRORED_BLOCKS_HOr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x1800002d, (_val))
 #define WRITE_WC40_PCS_IEEE2BLK_ERRORED_BLOCKS_HOr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x1800002d, (_val))
 #define MODIFY_WC40_PCS_IEEE2BLK_ERRORED_BLOCKS_HOr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x1800002d, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_PCS_PCS_ieee3Blk
  */
 
 /* Multi-lane BASE-R PCS alignment status register 1 */
 #define READ_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000032, (_val))
 #define WRITE_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000032, (_val))
 #define MODIFY_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000032, (_val), (_mask))
 
 /* Multi-lane BASE-R PCS alignment status register 3 */
 #define READ_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_3r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x18000034, (_val))
 #define WRITE_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_3r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x18000034, (_val))
 #define MODIFY_WC40_PCS_IEEE3BLK_MULTI_LANE_STATUS_3r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x18000034, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_PCS_PCS_ieee5Blk
  */
 
 /* BIP error counter, lane 0 and lane 1 */
 #define READ_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x1800005a, (_val))
 #define WRITE_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x1800005a, (_val))
 #define MODIFY_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x1800005a, (_val), (_mask))
 
 /* BIP error counter, lane 2 and lane 3 */
 #define READ_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x1800005b, (_val))
 #define WRITE_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x1800005b, (_val))
 #define MODIFY_WC40_PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x1800005b, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_CL73_AN_ieee0Blk
  */
 
 /* AN Control 1 */
 #define READ_WC40_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000000, (_val))
 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000000, (_val))
 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000000, (_val), (_mask))
 
 /* AN Status 1 */
 #define READ_WC40_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000001, (_val))
 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000001, (_val))
 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000001, (_val), (_mask))
 
 /* AN Device ID [15:0] */
 #define READ_WC40_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000002, (_val))
 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000002, (_val))
 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000002, (_val), (_mask))
 
 /* AN Device ID [31:16] */
 #define READ_WC40_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000003, (_val))
 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000003, (_val))
 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000003, (_val), (_mask))
 
 /* AN Devices in Package 1 */
 #define READ_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000005, (_val))
 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000005, (_val))
 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000005, (_val), (_mask))
 
 /* AN Devices in Package 2 */
 #define READ_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000006, (_val))
 #define WRITE_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000006, (_val))
 #define MODIFY_WC40_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000006, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_CL73_AN_ieee1Blk
  */
 
 /* AN advertisement 0 */
 #define READ_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000010, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000010, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000010, (_val), (_mask))
 
 /* AN advertisement 1 */
 #define READ_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000011, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000011, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000011, (_val), (_mask))
 
 /* AN advertisement 2 */
 #define READ_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000012, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000012, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_ADVERTISEMENT2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000012, (_val), (_mask))
 
 /* AN LP base page ability 0 */
 #define READ_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000013, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000013, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000013, (_val), (_mask))
 
 /* AN LP base page ability 1 */
 #define READ_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000014, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000014, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000014, (_val), (_mask))
 
 /* AN LP base page ability 2 */
 #define READ_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000015, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000015, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000015, (_val), (_mask))
 
 /* AN XNP transmit 0 */
 #define READ_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000016, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000016, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000016, (_val), (_mask))
 
 /* AN XNP transmit 1 */
 #define READ_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000017, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000017, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000017, (_val), (_mask))
 
 /* AN XNP transmit 2 */
 #define READ_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000018, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000018, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000018, (_val), (_mask))
 
 /* AN LP XNP ability 0 */
 #define READ_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000019, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000019, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000019, (_val), (_mask))
 
 /* AN LP XNP ability 1 */
 #define READ_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x3800001a, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x3800001a, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x3800001a, (_val), (_mask))
 
 /* AN LP XNP ability 2 */
 #define READ_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x3800001b, (_val))
 #define WRITE_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x3800001b, (_val))
 #define MODIFY_WC40_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x3800001b, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_CL73_AN_ieee3Blk
  */
 
 /* Autonegotiation Backplane Ethernet status */
 #define READ_WC40_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x38000030, (_val))
 #define WRITE_WC40_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x38000030, (_val))
 #define MODIFY_WC40_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x38000030, (_val), (_mask))
 
 /* EEE advertisement */
 #define READ_WC40_AN_IEEE3BLK_EEE_ADVr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x3800003c, (_val))
 #define WRITE_WC40_AN_IEEE3BLK_EEE_ADVr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x3800003c, (_val))
 #define MODIFY_WC40_AN_IEEE3BLK_EEE_ADVr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x3800003c, (_val), (_mask))
 
 /* LP EEE advertisement */
 #define READ_WC40_AN_IEEE3BLK_EEE_LP_ADVr(_unit, _pc, _flags, _val) \
              WC40_REG_READ((_unit), (_pc), (_flags), 0x3800003d, (_val))
 #define WRITE_WC40_AN_IEEE3BLK_EEE_LP_ADVr(_unit, _pc, _flags, _val) \
              WC40_REG_WRITE((_unit), (_pc), (_flags), 0x3800003d, (_val))
 #define MODIFY_WC40_AN_IEEE3BLK_EEE_LP_ADVr(_unit, _pc, _flags, _val, _mask) \
              WC40_REG_MODIFY((_unit), (_pc), (_flags), 0x3800003d, (_val), (_mask))
 
 
 /****************************************************************************
  * Warpcore_IEEE_CL22_ieee0Blk
  */
 /****************************************************************************
  * ieee0Blk :: MIICntl
  */
 /* ieee0Blk :: MIICntl :: rst_hw [15:15] */
 #define IEEE0BLK_MIICNTL_RST_HW_MASK                               0x8000
 #define IEEE0BLK_MIICNTL_RST_HW_ALIGN                              0
 #define IEEE0BLK_MIICNTL_RST_HW_BITS                               1
 #define IEEE0BLK_MIICNTL_RST_HW_SHIFT                              15
 
 /* ieee0Blk :: MIICntl :: gloopback [14:14] */
 #define IEEE0BLK_MIICNTL_GLOOPBACK_MASK                            0x4000
 #define IEEE0BLK_MIICNTL_GLOOPBACK_ALIGN                           0
 #define IEEE0BLK_MIICNTL_GLOOPBACK_BITS                            1
 #define IEEE0BLK_MIICNTL_GLOOPBACK_SHIFT                           14
 
 /* ieee0Blk :: MIICntl :: manual_speed0 [13:13] */
 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_MASK                        0x2000
 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_ALIGN                       0
 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_BITS                        1
 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_SHIFT                       13
 
 /* ieee0Blk :: MIICntl :: autoneg_enable [12:12] */
 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_MASK                       0x1000
 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_ALIGN                      0
 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_BITS                       1
 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_SHIFT                      12
 
 /* ieee0Blk :: MIICntl :: pwrdwn_sw [11:11] */
 #define IEEE0BLK_MIICNTL_PWRDWN_SW_MASK                            0x0800
 #define IEEE0BLK_MIICNTL_PWRDWN_SW_ALIGN                           0
 #define IEEE0BLK_MIICNTL_PWRDWN_SW_BITS                            1
 #define IEEE0BLK_MIICNTL_PWRDWN_SW_SHIFT                           11
 
 /* ieee0Blk :: MIICntl :: reserved0 [10:10] */
 #define IEEE0BLK_MIICNTL_RESERVED0_MASK                            0x0400
 #define IEEE0BLK_MIICNTL_RESERVED0_ALIGN                           0
 #define IEEE0BLK_MIICNTL_RESERVED0_BITS                            1
 #define IEEE0BLK_MIICNTL_RESERVED0_SHIFT                           10
 
 /* ieee0Blk :: MIICntl :: restart_autoneg [09:09] */
 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_MASK                      0x0200
 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_ALIGN                     0
 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_BITS                      1
 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_SHIFT                     9
 
 /* ieee0Blk :: MIICntl :: full_duplex [08:08] */
 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_MASK                          0x0100
 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_ALIGN                         0
 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_BITS                          1
 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_SHIFT                         8
 
 /* ieee0Blk :: MIICntl :: collision_test_en [07:07] */
 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_MASK                    0x0080
 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_ALIGN                   0
 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_BITS                    1
 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_SHIFT                   7
 
 /* ieee0Blk :: MIICntl :: manual_speed1 [06:06] */
 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_MASK                        0x0040
 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_ALIGN                       0
 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_BITS                        1
 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_SHIFT                       6
 
 /* ieee0Blk :: MIICntl :: reserved1 [05:00] */
 #define IEEE0BLK_MIICNTL_RESERVED1_MASK                            0x003f
 #define IEEE0BLK_MIICNTL_RESERVED1_ALIGN                           0
 #define IEEE0BLK_MIICNTL_RESERVED1_BITS                            6
 #define IEEE0BLK_MIICNTL_RESERVED1_SHIFT                           0
 
 
 /****************************************************************************
  * ieee0Blk :: MIIStat
  */
 /* ieee0Blk :: MIIStat :: s100BASE_T4_capable [15:15] */
 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_MASK                  0x8000
 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_ALIGN                 0
 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_BITS                  1
 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_SHIFT                 15
 
 /* ieee0Blk :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK       0x4000
 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN      0
 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS       1
 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT      14
 
 /* ieee0Blk :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK       0x2000
 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN      0
 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS       1
 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT      13
 
 /* ieee0Blk :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK        0x1000
 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN       0
 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS        1
 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT       12
 
 /* ieee0Blk :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK        0x0800
 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN       0
 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS        1
 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT       11
 
 /* ieee0Blk :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK      0x0400
 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN     0
 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS      1
 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT     10
 
 /* ieee0Blk :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK      0x0200
 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN     0
 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS      1
 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT     9
 
 /* ieee0Blk :: MIIStat :: extended_status [08:08] */
 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_MASK                      0x0100
 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_ALIGN                     0
 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_BITS                      1
 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_SHIFT                     8
 
 /* ieee0Blk :: MIIStat :: reserved0 [07:07] */
 #define IEEE0BLK_MIISTAT_RESERVED0_MASK                            0x0080
 #define IEEE0BLK_MIISTAT_RESERVED0_ALIGN                           0
 #define IEEE0BLK_MIISTAT_RESERVED0_BITS                            1
 #define IEEE0BLK_MIISTAT_RESERVED0_SHIFT                           7
 
 /* ieee0Blk :: MIIStat :: mf_preamble_supression [06:06] */
 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK               0x0040
 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN              0
 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS               1
 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT              6
 
 /* ieee0Blk :: MIIStat :: autoneg_complete [05:05] */
 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_MASK                     0x0020
 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_ALIGN                    0
 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_BITS                     1
 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_SHIFT                    5
 
 /* ieee0Blk :: MIIStat :: remote_fault [04:04] */
 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_MASK                         0x0010
 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_ALIGN                        0
 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_BITS                         1
 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_SHIFT                        4
 
 /* ieee0Blk :: MIIStat :: autoneg_ability [03:03] */
 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_MASK                      0x0008
 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_ALIGN                     0
 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_BITS                      1
 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_SHIFT                     3
 
 /* ieee0Blk :: MIIStat :: link_status [02:02] */
 #define IEEE0BLK_MIISTAT_LINK_STATUS_MASK                          0x0004
 #define IEEE0BLK_MIISTAT_LINK_STATUS_ALIGN                         0
 #define IEEE0BLK_MIISTAT_LINK_STATUS_BITS                          1
 #define IEEE0BLK_MIISTAT_LINK_STATUS_SHIFT                         2
 
 /* ieee0Blk :: MIIStat :: jabber_detect [01:01] */
 #define IEEE0BLK_MIISTAT_JABBER_DETECT_MASK                        0x0002
 #define IEEE0BLK_MIISTAT_JABBER_DETECT_ALIGN                       0
 #define IEEE0BLK_MIISTAT_JABBER_DETECT_BITS                        1
 #define IEEE0BLK_MIISTAT_JABBER_DETECT_SHIFT                       1
 
 /* ieee0Blk :: MIIStat :: extended_capability [00:00] */
 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_MASK                  0x0001
 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_ALIGN                 0
 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_BITS                  1
 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_SHIFT                 0
 
 
 /****************************************************************************
  * ieee0Blk :: Id1
  */
 /* ieee0Blk :: Id1 :: regid [15:00] */
 #define IEEE0BLK_ID1_REGID_MASK                                    0xffff
 #define IEEE0BLK_ID1_REGID_ALIGN                                   0
 #define IEEE0BLK_ID1_REGID_BITS                                    16
 #define IEEE0BLK_ID1_REGID_SHIFT                                   0
 
 
 /****************************************************************************
  * ieee0Blk :: Id2
  */
 /* ieee0Blk :: Id2 :: regid [15:00] */
 #define IEEE0BLK_ID2_REGID_MASK                                    0xffff
 #define IEEE0BLK_ID2_REGID_ALIGN                                   0
 #define IEEE0BLK_ID2_REGID_BITS                                    16
 #define IEEE0BLK_ID2_REGID_SHIFT                                   0
 
 
 /****************************************************************************
  * ieee0Blk :: AutoNegAdv
  */
 /* ieee0Blk :: AutoNegAdv :: next_page [15:15] */
 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_MASK                         0x8000
 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_ALIGN                        0
 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_BITS                         1
 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_SHIFT                        15
 
 /* ieee0Blk :: AutoNegAdv :: reserved0 [14:14] */
 #define IEEE0BLK_AUTONEGADV_RESERVED0_MASK                         0x4000
 #define IEEE0BLK_AUTONEGADV_RESERVED0_ALIGN                        0
 #define IEEE0BLK_AUTONEGADV_RESERVED0_BITS                         1
 #define IEEE0BLK_AUTONEGADV_RESERVED0_SHIFT                        14
 
 /* ieee0Blk :: AutoNegAdv :: remote_fault [13:12] */
 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_MASK                      0x3000
 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_ALIGN                     0
 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_BITS                      2
 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_SHIFT                     12
 
 /* ieee0Blk :: AutoNegAdv :: reserved1 [11:09] */
 #define IEEE0BLK_AUTONEGADV_RESERVED1_MASK                         0x0e00
 #define IEEE0BLK_AUTONEGADV_RESERVED1_ALIGN                        0
 #define IEEE0BLK_AUTONEGADV_RESERVED1_BITS                         3
 #define IEEE0BLK_AUTONEGADV_RESERVED1_SHIFT                        9
 
 /* ieee0Blk :: AutoNegAdv :: pause [08:07] */
 #define IEEE0BLK_AUTONEGADV_PAUSE_MASK                             0x0180
 #define IEEE0BLK_AUTONEGADV_PAUSE_ALIGN                            0
 #define IEEE0BLK_AUTONEGADV_PAUSE_BITS                             2
 #define IEEE0BLK_AUTONEGADV_PAUSE_SHIFT                            7
 
 /* ieee0Blk :: AutoNegAdv :: half_duplex [06:06] */
 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_MASK                       0x0040
 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_ALIGN                      0
 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_BITS                       1
 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_SHIFT                      6
 
 /* ieee0Blk :: AutoNegAdv :: full_duplex [05:05] */
 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_MASK                       0x0020
 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_ALIGN                      0
 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_BITS                       1
 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_SHIFT                      5
 
 /* ieee0Blk :: AutoNegAdv :: reserved2 [04:00] */
 #define IEEE0BLK_AUTONEGADV_RESERVED2_MASK                         0x001f
 #define IEEE0BLK_AUTONEGADV_RESERVED2_ALIGN                        0
 #define IEEE0BLK_AUTONEGADV_RESERVED2_BITS                         5
 #define IEEE0BLK_AUTONEGADV_RESERVED2_SHIFT                        0
 
 
 /****************************************************************************
  * ieee0Blk :: AutoNegLPAbil
  */
 /* ieee0Blk :: AutoNegLPAbil :: next_page [15:15] */
 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_MASK                      0x8000
 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_ALIGN                     0
 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_BITS                      1
 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_SHIFT                     15
 
 /* ieee0Blk :: AutoNegLPAbil :: acknowledge [14:14] */
 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_MASK                    0x4000
 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN                   0
 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_BITS                    1
 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT                   14
 
 /* ieee0Blk :: AutoNegLPAbil :: remote_fault [13:12] */
 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_MASK                   0x3000
 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_ALIGN                  0
 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_BITS                   2
 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_SHIFT                  12
 
 /* ieee0Blk :: AutoNegLPAbil :: reserved0 [11:09] */
 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_MASK                      0x0e00
 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_ALIGN                     0
 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_BITS                      3
 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_SHIFT                     9
 
 /* ieee0Blk :: AutoNegLPAbil :: pause [08:07] */
 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_MASK                          0x0180
 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_ALIGN                         0
 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_BITS                          2
 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_SHIFT                         7
 
 /* ieee0Blk :: AutoNegLPAbil :: half_duplex [06:06] */
 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_MASK                    0x0040
 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_ALIGN                   0
 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_BITS                    1
 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_SHIFT                   6
 
 /* ieee0Blk :: AutoNegLPAbil :: full_duplex [05:05] */
 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_MASK                    0x0020
 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_ALIGN                   0
 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_BITS                    1
 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_SHIFT                   5
 
 /* ieee0Blk :: AutoNegLPAbil :: reserved1 [04:01] */
 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_MASK                      0x001e
 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_ALIGN                     0
 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_BITS                      4
 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_SHIFT                     1
 
 /* ieee0Blk :: AutoNegLPAbil :: sgmii_mode [00:00] */
 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_MASK                     0x0001
 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_ALIGN                    0
 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_BITS                     1
 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_SHIFT                    0
 
 
 /****************************************************************************
  * ieee0Blk :: AutoNegExp
  */
 /* ieee0Blk :: AutoNegExp :: reserved0 [15:03] */
 #define IEEE0BLK_AUTONEGEXP_RESERVED0_MASK                         0xfff8
 #define IEEE0BLK_AUTONEGEXP_RESERVED0_ALIGN                        0
 #define IEEE0BLK_AUTONEGEXP_RESERVED0_BITS                         13
 #define IEEE0BLK_AUTONEGEXP_RESERVED0_SHIFT                        3
 
 /* ieee0Blk :: AutoNegExp :: next_page_ability [02:02] */
 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK                 0x0004
 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN                0
 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS                 1
 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT                2
 
 /* ieee0Blk :: AutoNegExp :: page_received [01:01] */
 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_MASK                     0x0002
 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_ALIGN                    0
 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_BITS                     1
 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_SHIFT                    1
 
 /* ieee0Blk :: AutoNegExp :: reserved1 [00:00] */
 #define IEEE0BLK_AUTONEGEXP_RESERVED1_MASK                         0x0001
 #define IEEE0BLK_AUTONEGEXP_RESERVED1_ALIGN                        0
 #define IEEE0BLK_AUTONEGEXP_RESERVED1_BITS                         1
 #define IEEE0BLK_AUTONEGEXP_RESERVED1_SHIFT                        0
 
 
 /****************************************************************************
  * ieee0Blk :: AutoNegNP
  */
 /* ieee0Blk :: AutoNegNP :: Next_Page [15:15] */
 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_MASK                          0x8000
 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_ALIGN                         0
 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_BITS                          1
 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_SHIFT                         15
 
 /* ieee0Blk :: AutoNegNP :: Ack [14:14] */
 #define IEEE0BLK_AUTONEGNP_ACK_MASK                                0x4000
 #define IEEE0BLK_AUTONEGNP_ACK_ALIGN                               0
 #define IEEE0BLK_AUTONEGNP_ACK_BITS                                1
 #define IEEE0BLK_AUTONEGNP_ACK_SHIFT                               14
 
 /* ieee0Blk :: AutoNegNP :: Message_Page [13:13] */
 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_MASK                       0x2000
 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_ALIGN                      0
 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_BITS                       1
 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_SHIFT                      13
 
 /* ieee0Blk :: AutoNegNP :: Ack2 [12:12] */
 #define IEEE0BLK_AUTONEGNP_ACK2_MASK                               0x1000
 #define IEEE0BLK_AUTONEGNP_ACK2_ALIGN                              0
 #define IEEE0BLK_AUTONEGNP_ACK2_BITS                               1
 #define IEEE0BLK_AUTONEGNP_ACK2_SHIFT                              12
 
 /* ieee0Blk :: AutoNegNP :: Toggle [11:11] */
 #define IEEE0BLK_AUTONEGNP_TOGGLE_MASK                             0x0800
 #define IEEE0BLK_AUTONEGNP_TOGGLE_ALIGN                            0
 #define IEEE0BLK_AUTONEGNP_TOGGLE_BITS                             1
 #define IEEE0BLK_AUTONEGNP_TOGGLE_SHIFT                            11
 
 /* ieee0Blk :: AutoNegNP :: Message [10:00] */
 #define IEEE0BLK_AUTONEGNP_MESSAGE_MASK                            0x07ff
 #define IEEE0BLK_AUTONEGNP_MESSAGE_ALIGN                           0
 #define IEEE0BLK_AUTONEGNP_MESSAGE_BITS                            11
 #define IEEE0BLK_AUTONEGNP_MESSAGE_SHIFT                           0
 
 
 /****************************************************************************
  * ieee0Blk :: AutoNegLPAbil2
  */
 /* ieee0Blk :: AutoNegLPAbil2 :: Next_Page [15:15] */
 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_MASK                     0x8000
 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_ALIGN                    0
 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_BITS                     1
 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_SHIFT                    15
 
 /* ieee0Blk :: AutoNegLPAbil2 :: Ack [14:14] */
 #define IEEE0BLK_AUTONEGLPABIL2_ACK_MASK                           0x4000
 #define IEEE0BLK_AUTONEGLPABIL2_ACK_ALIGN                          0
 #define IEEE0BLK_AUTONEGLPABIL2_ACK_BITS                           1
 #define IEEE0BLK_AUTONEGLPABIL2_ACK_SHIFT                          14
 
 /* ieee0Blk :: AutoNegLPAbil2 :: Message_Page [13:13] */
 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_MASK                  0x2000
 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN                 0
 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_BITS                  1
 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT                 13
 
 /* ieee0Blk :: AutoNegLPAbil2 :: Ack2 [12:12] */
 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_MASK                          0x1000
 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_ALIGN                         0
 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_BITS                          1
 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_SHIFT                         12
 
 /* ieee0Blk :: AutoNegLPAbil2 :: Toggle [11:11] */
 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_MASK                        0x0800
 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_ALIGN                       0
 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_BITS                        1
 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_SHIFT                       11
 
 /* ieee0Blk :: AutoNegLPAbil2 :: Message [10:00] */
 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_MASK                       0x07ff
 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_ALIGN                      0
 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_BITS                       11
 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_SHIFT                      0
 
 
 /****************************************************************************
  * ieee0Blk :: MIIextStat
  */
 /* ieee0Blk :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK   0x8000
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN  0
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS   1
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT  15
 
 /* ieee0Blk :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK   0x4000
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN  0
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS   1
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT  14
 
 /* ieee0Blk :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK   0x2000
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN  0
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS   1
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT  13
 
 /* ieee0Blk :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK   0x1000
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN  0
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS   1
 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT  12
 
 /* ieee0Blk :: MIIextStat :: reserved0 [11:00] */
 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_MASK                         0x0fff
 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_ALIGN                        0
 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_BITS                         12
 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_SHIFT                        0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk0
  */
 /****************************************************************************
  * XgxsBlk0 :: xgxsControl
  */
 /* XgxsBlk0 :: xgxsControl :: pgen_en [15:15] */
 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_MASK                          0x8000
 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_ALIGN                         0
 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_BITS                          1
 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_SHIFT                         15
 
 /* XgxsBlk0 :: xgxsControl :: pcmp_en [14:14] */
 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_MASK                          0x4000
 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_ALIGN                         0
 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_BITS                          1
 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_SHIFT                         14
 
 /* XgxsBlk0 :: xgxsControl :: start_sequencer [13:13] */
 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_MASK                  0x2000
 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_ALIGN                 0
 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_BITS                  1
 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_SHIFT                 13
 
 /* XgxsBlk0 :: xgxsControl :: reset_anlg [12:12] */
 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_MASK                       0x1000
 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_ALIGN                      0
 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_BITS                       1
 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_SHIFT                      12
 
 /* XgxsBlk0 :: xgxsControl :: mode_10g [11:08] */
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_MASK                         0x0f00
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_ALIGN                        0
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_BITS                         4
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_SHIFT                        8
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS                         0
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXG_nCC                     1
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_Indlane_OS8                  4
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_IndLane_OS5                  5
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_PCI                          7
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_nLQ                     8
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_nLQnCC                  9
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_PBypass                      10
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_PBypass_nDSK                 11
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_ComboCoreMode                12
 #define XGXSBLK0_XGXSCONTROL_MODE_10G_Clocks_off                   15
 
 /* XgxsBlk0 :: xgxsControl :: pll_bypass [07:07] */
 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_MASK                       0x0080
 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_ALIGN                      0
 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_BITS                       1
 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_SHIFT                      7
 
 /* XgxsBlk0 :: xgxsControl :: rloop [06:06] */
 #define XGXSBLK0_XGXSCONTROL_RLOOP_MASK                            0x0040
 #define XGXSBLK0_XGXSCONTROL_RLOOP_ALIGN                           0
 #define XGXSBLK0_XGXSCONTROL_RLOOP_BITS                            1
 #define XGXSBLK0_XGXSCONTROL_RLOOP_SHIFT                           6
 
 /* XgxsBlk0 :: xgxsControl :: reserved0 [05:05] */
 #define XGXSBLK0_XGXSCONTROL_RESERVED0_MASK                        0x0020
 #define XGXSBLK0_XGXSCONTROL_RESERVED0_ALIGN                       0
 #define XGXSBLK0_XGXSCONTROL_RESERVED0_BITS                        1
 #define XGXSBLK0_XGXSCONTROL_RESERVED0_SHIFT                       5
 
 /* XgxsBlk0 :: xgxsControl :: mdio_cont_en [04:04] */
 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_MASK                     0x0010
 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_ALIGN                    0
 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_BITS                     1
 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_SHIFT                    4
 
 /* XgxsBlk0 :: xgxsControl :: cdet_en [03:03] */
 #define XGXSBLK0_XGXSCONTROL_CDET_EN_MASK                          0x0008
 #define XGXSBLK0_XGXSCONTROL_CDET_EN_ALIGN                         0
 #define XGXSBLK0_XGXSCONTROL_CDET_EN_BITS                          1
 #define XGXSBLK0_XGXSCONTROL_CDET_EN_SHIFT                         3
 
 /* XgxsBlk0 :: xgxsControl :: eden [02:02] */
 #define XGXSBLK0_XGXSCONTROL_EDEN_MASK                             0x0004
 #define XGXSBLK0_XGXSCONTROL_EDEN_ALIGN                            0
 #define XGXSBLK0_XGXSCONTROL_EDEN_BITS                             1
 #define XGXSBLK0_XGXSCONTROL_EDEN_SHIFT                            2
 
 /* XgxsBlk0 :: xgxsControl :: afrst_en [01:01] */
 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_MASK                         0x0002
 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_ALIGN                        0
 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_BITS                         1
 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_SHIFT                        1
 
 /* XgxsBlk0 :: xgxsControl :: txcko_div [00:00] */
 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_MASK                        0x0001
 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_ALIGN                       0
 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_BITS                        1
 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_SHIFT                       0
 
 
 /****************************************************************************
  * XgxsBlk0 :: xgxsStatus
  */
 /* XgxsBlk0 :: xgxsStatus :: status_en [15:15] */
 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_MASK                         0x8000
 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_ALIGN                        0
 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_BITS                         1
 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_SHIFT                        15
 
 /* XgxsBlk0 :: xgxsStatus :: reserved0 [14:14] */
 #define XGXSBLK0_XGXSSTATUS_RESERVED0_MASK                         0x4000
 #define XGXSBLK0_XGXSSTATUS_RESERVED0_ALIGN                        0
 #define XGXSBLK0_XGXSSTATUS_RESERVED0_BITS                         1
 #define XGXSBLK0_XGXSSTATUS_RESERVED0_SHIFT                        14
 
 /* XgxsBlk0 :: xgxsStatus :: tx_remote_fault [13:13] */
 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_MASK                   0x2000
 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_ALIGN                  0
 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_BITS                   1
 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_SHIFT                  13
 
 /* XgxsBlk0 :: xgxsStatus :: rx_remote_fault [12:12] */
 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_MASK                   0x1000
 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_ALIGN                  0
 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_BITS                   1
 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_SHIFT                  12
 
 /* XgxsBlk0 :: xgxsStatus :: txpll_lock [11:11] */
 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_MASK                        0x0800
 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_ALIGN                       0
 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_BITS                        1
 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_SHIFT                       11
 
 /* XgxsBlk0 :: xgxsStatus :: txd_fifo_err [10:10] */
 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_MASK                      0x0400
 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_ALIGN                     0
 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_BITS                      1
 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_SHIFT                     10
 
 /* XgxsBlk0 :: xgxsStatus :: sequencer_done [09:09] */
 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_MASK                    0x0200
 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_ALIGN                   0
 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_BITS                    1
 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_SHIFT                   9
 
 /* XgxsBlk0 :: xgxsStatus :: sequencer_pass [08:08] */
 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_MASK                    0x0100
 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_ALIGN                   0
 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_BITS                    1
 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_SHIFT                   8
 
 /* XgxsBlk0 :: xgxsStatus :: rxferr [07:04] */
 #define XGXSBLK0_XGXSSTATUS_RXFERR_MASK                            0x00f0
 #define XGXSBLK0_XGXSSTATUS_RXFERR_ALIGN                           0
 #define XGXSBLK0_XGXSSTATUS_RXFERR_BITS                            4
 #define XGXSBLK0_XGXSSTATUS_RXFERR_SHIFT                           4
 
 /* XgxsBlk0 :: xgxsStatus :: pll_mode_afe [03:03] */
 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_MASK                      0x0008
 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_ALIGN                     0
 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_BITS                      1
 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_SHIFT                     3
 
 /* XgxsBlk0 :: xgxsStatus :: ckcmp_unflow [02:02] */
 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_MASK                      0x0004
 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_ALIGN                     0
 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_BITS                      1
 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_SHIFT                     2
 
 /* XgxsBlk0 :: xgxsStatus :: ckcmp_ovflow [01:01] */
 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_MASK                      0x0002
 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_ALIGN                     0
 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_BITS                      1
 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_SHIFT                     1
 
 /* XgxsBlk0 :: xgxsStatus :: skew_status [00:00] */
 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_MASK                       0x0001
 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_ALIGN                      0
 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_BITS                       1
 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_SHIFT                      0
 
 
 /****************************************************************************
  * XgxsBlk0 :: xgmiiIdle
  */
 /* XgxsBlk0 :: xgmiiIdle :: I [15:08] */
 #define XGXSBLK0_XGMIIIDLE_I_MASK                                  0xff00
 #define XGXSBLK0_XGMIIIDLE_I_ALIGN                                 0
 #define XGXSBLK0_XGMIIIDLE_I_BITS                                  8
 #define XGXSBLK0_XGMIIIDLE_I_SHIFT                                 8
 
 /* XgxsBlk0 :: xgmiiIdle :: Ib [07:00] */
 #define XGXSBLK0_XGMIIIDLE_IB_MASK                                 0x00ff
 #define XGXSBLK0_XGMIIIDLE_IB_ALIGN                                0
 #define XGXSBLK0_XGMIIIDLE_IB_BITS                                 8
 #define XGXSBLK0_XGMIIIDLE_IB_SHIFT                                0
 
 
 /****************************************************************************
  * XgxsBlk0 :: xgmiiSync
  */
 /* XgxsBlk0 :: xgmiiSync :: K [15:08] */
 #define XGXSBLK0_XGMIISYNC_K_MASK                                  0xff00
 #define XGXSBLK0_XGMIISYNC_K_ALIGN                                 0
 #define XGXSBLK0_XGMIISYNC_K_BITS                                  8
 #define XGXSBLK0_XGMIISYNC_K_SHIFT                                 8
 
 /* XgxsBlk0 :: xgmiiSync :: Kb [07:00] */
 #define XGXSBLK0_XGMIISYNC_KB_MASK                                 0x00ff
 #define XGXSBLK0_XGMIISYNC_KB_ALIGN                                0
 #define XGXSBLK0_XGMIISYNC_KB_BITS                                 8
 #define XGXSBLK0_XGMIISYNC_KB_SHIFT                                0
 
 
 /****************************************************************************
  * XgxsBlk0 :: xgmiiSkip
  */
 /* XgxsBlk0 :: xgmiiSkip :: R [15:08] */
 #define XGXSBLK0_XGMIISKIP_R_MASK                                  0xff00
 #define XGXSBLK0_XGMIISKIP_R_ALIGN                                 0
 #define XGXSBLK0_XGMIISKIP_R_BITS                                  8
 #define XGXSBLK0_XGMIISKIP_R_SHIFT                                 8
 
 /* XgxsBlk0 :: xgmiiSkip :: Rb [07:00] */
 #define XGXSBLK0_XGMIISKIP_RB_MASK                                 0x00ff
 #define XGXSBLK0_XGMIISKIP_RB_ALIGN                                0
 #define XGXSBLK0_XGMIISKIP_RB_BITS                                 8
 #define XGXSBLK0_XGMIISKIP_RB_SHIFT                                0
 
 
 /****************************************************************************
  * XgxsBlk0 :: xgmiiSopEop
  */
 /* XgxsBlk0 :: xgmiiSopEop :: S [15:08] */
 #define XGXSBLK0_XGMIISOPEOP_S_MASK                                0xff00
 #define XGXSBLK0_XGMIISOPEOP_S_ALIGN                               0
 #define XGXSBLK0_XGMIISOPEOP_S_BITS                                8
 #define XGXSBLK0_XGMIISOPEOP_S_SHIFT                               8
 
 /* XgxsBlk0 :: xgmiiSopEop :: T [07:00] */
 #define XGXSBLK0_XGMIISOPEOP_T_MASK                                0x00ff
 #define XGXSBLK0_XGMIISOPEOP_T_ALIGN                               0
 #define XGXSBLK0_XGMIISOPEOP_T_BITS                                8
 #define XGXSBLK0_XGMIISOPEOP_T_SHIFT                               0
 
 
 /****************************************************************************
  * XgxsBlk0 :: xgmiiAlign
  */
 /* XgxsBlk0 :: xgmiiAlign :: E [15:08] */
 #define XGXSBLK0_XGMIIALIGN_E_MASK                                 0xff00
 #define XGXSBLK0_XGMIIALIGN_E_ALIGN                                0
 #define XGXSBLK0_XGMIIALIGN_E_BITS                                 8
 #define XGXSBLK0_XGMIIALIGN_E_SHIFT                                8
 
 /* XgxsBlk0 :: xgmiiAlign :: A [07:00] */
 #define XGXSBLK0_XGMIIALIGN_A_MASK                                 0x00ff
 #define XGXSBLK0_XGMIIALIGN_A_ALIGN                                0
 #define XGXSBLK0_XGMIIALIGN_A_BITS                                 8
 #define XGXSBLK0_XGMIIALIGN_A_SHIFT                                0
 
 
 /****************************************************************************
  * XgxsBlk0 :: xgmiiRcontrol
  */
 /* XgxsBlk0 :: xgmiiRcontrol :: reserved0 [15:15] */
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_MASK                      0x8000
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_ALIGN                     0
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_BITS                      1
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_SHIFT                     15
 
 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf0_en [14:14] */
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_MASK                      0x4000
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_ALIGN                     0
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_BITS                      1
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_SHIFT                     14
 
 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf1_en [13:13] */
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_MASK                      0x2000
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_ALIGN                     0
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_BITS                      1
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_SHIFT                     13
 
 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf2_en [12:12] */
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_MASK                      0x1000
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_ALIGN                     0
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_BITS                      1
 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_SHIFT                     12
 
 /* XgxsBlk0 :: xgmiiRcontrol :: force_inbndls_en [11:11] */
 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_MASK               0x0800
 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_ALIGN              0
 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_BITS               1
 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_SHIFT              11
 
 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_en [10:10] */
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_MASK                     0x0400
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_ALIGN                    0
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_BITS                     1
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_SHIFT                    10
 
 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_std_en [09:09] */
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_MASK                 0x0200
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_ALIGN                0
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_BITS                 1
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_SHIFT                9
 
 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_force [08:08] */
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_MASK                  0x0100
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_ALIGN                 0
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_BITS                  1
 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_SHIFT                 8
 
 /* XgxsBlk0 :: xgmiiRcontrol :: reserved1 [07:07] */
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_MASK                      0x0080
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_ALIGN                     0
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_BITS                      1
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_SHIFT                     7
 
 /* XgxsBlk0 :: xgmiiRcontrol :: scr_en_4lane [06:06] */
 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_MASK                   0x0040
 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_ALIGN                  0
 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_BITS                   1
 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_SHIFT                  6
 
 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_noIPG_en [05:05] */
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_MASK                 0x0020
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_ALIGN                0
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_BITS                 1
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_SHIFT                5
 
 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_afrst_en [04:04] */
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_MASK                 0x0010
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_ALIGN                0
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_BITS                 1
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_SHIFT                4
 
 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_gt1_Icol_dis [03:03] */
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_MASK             0x0008
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_ALIGN            0
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_BITS             1
 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_SHIFT            3
 
 /* XgxsBlk0 :: xgmiiRcontrol :: reserved2 [02:00] */
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_MASK                      0x0007
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_ALIGN                     0
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_BITS                      3
 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk0 :: xgmiiTcontrol
  */
 /* XgxsBlk0 :: xgmiiTcontrol :: swapen [15:15] */
 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_MASK                         0x8000
 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_ALIGN                        0
 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_BITS                         1
 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_SHIFT                        15
 
 /* XgxsBlk0 :: xgmiiTcontrol :: swap_lane_ind [14:14] */
 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_MASK                  0x4000
 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_ALIGN                 0
 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_BITS                  1
 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_SHIFT                 14
 
 /* XgxsBlk0 :: xgmiiTcontrol :: pn_sel [13:13] */
 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_MASK                         0x2000
 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_ALIGN                        0
 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_BITS                         1
 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_SHIFT                        13
 
 /* XgxsBlk0 :: xgmiiTcontrol :: reserved0 [12:09] */
 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_MASK                      0x1e00
 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_ALIGN                     0
 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_BITS                      4
 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_SHIFT                     9
 
 /* XgxsBlk0 :: xgmiiTcontrol :: alignstat_rxlf_en [08:08] */
 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_MASK              0x0100
 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_ALIGN             0
 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_BITS              1
 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_SHIFT             8
 
 /* XgxsBlk0 :: xgmiiTcontrol :: flip_txrx_lf [07:07] */
 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_MASK                   0x0080
 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_ALIGN                  0
 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_BITS                   1
 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_SHIFT                  7
 
 /* XgxsBlk0 :: xgmiiTcontrol :: xenpak_lfclr_en [06:06] */
 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_MASK                0x0040
 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_ALIGN               0
 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_BITS                1
 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_SHIFT               6
 
 /* XgxsBlk0 :: xgmiiTcontrol :: tx_xgmii_Tcol_old_en [05:05] */
 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_MASK           0x0020
 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_ALIGN          0
 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_BITS           1
 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_SHIFT          5
 
 /* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_IorRF_en [04:04] */
 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_MASK        0x0010
 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_ALIGN       0
 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_BITS        1
 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_SHIFT       4
 
 /* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_I_en [03:03] */
 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_MASK            0x0008
 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_ALIGN           0
 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_BITS            1
 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_SHIFT           3
 
 /* XgxsBlk0 :: xgmiiTcontrol :: reserved1 [02:00] */
 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_MASK                      0x0007
 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_ALIGN                     0
 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_BITS                      3
 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk0 :: xgmiiSwap
  */
 /* XgxsBlk0 :: xgmiiSwap :: swap_count [15:00] */
 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_MASK                         0xffff
 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_ALIGN                        0
 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_BITS                         16
 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_SHIFT                        0
 
 
 /****************************************************************************
  * XgxsBlk0 :: lssLsid
  */
 /* XgxsBlk0 :: lssLsid :: lss_ls_id [15:08] */
 #define XGXSBLK0_LSSLSID_LSS_LS_ID_MASK                            0xff00
 #define XGXSBLK0_LSSLSID_LSS_LS_ID_ALIGN                           0
 #define XGXSBLK0_LSSLSID_LSS_LS_ID_BITS                            8
 #define XGXSBLK0_LSSLSID_LSS_LS_ID_SHIFT                           8
 
 /* XgxsBlk0 :: lssLsid :: lss_domain_id [07:00] */
 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_MASK                        0x00ff
 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_ALIGN                       0
 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_BITS                        8
 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_SHIFT                       0
 
 
 /****************************************************************************
  * XgxsBlk0 :: lssTinfo
  */
 /* XgxsBlk0 :: lssTinfo :: lss_function_id [15:08] */
 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_MASK                     0xff00
 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_ALIGN                    0
 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_BITS                     8
 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_SHIFT                    8
 
 /* XgxsBlk0 :: lssTinfo :: lssL_info_byte [07:00] */
 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_MASK                      0x00ff
 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_ALIGN                     0
 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_BITS                      8
 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk0 :: lssRinfo
  */
 /* XgxsBlk0 :: lssRinfo :: control_en [15:15] */
 #define XGXSBLK0_LSSRINFO_CONTROL_EN_MASK                          0x8000
 #define XGXSBLK0_LSSRINFO_CONTROL_EN_ALIGN                         0
 #define XGXSBLK0_LSSRINFO_CONTROL_EN_BITS                          1
 #define XGXSBLK0_LSSRINFO_CONTROL_EN_SHIFT                         15
 
 /* XgxsBlk0 :: lssRinfo :: reserved0 [14:14] */
 #define XGXSBLK0_LSSRINFO_RESERVED0_MASK                           0x4000
 #define XGXSBLK0_LSSRINFO_RESERVED0_ALIGN                          0
 #define XGXSBLK0_LSSRINFO_RESERVED0_BITS                           1
 #define XGXSBLK0_LSSRINFO_RESERVED0_SHIFT                          14
 
 /* XgxsBlk0 :: lssRinfo :: lss_ls_id8 [13:13] */
 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_MASK                          0x2000
 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_ALIGN                         0
 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_BITS                          1
 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_SHIFT                         13
 
 /* XgxsBlk0 :: lssRinfo :: lss_domain_id8 [12:12] */
 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_MASK                      0x1000
 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_ALIGN                     0
 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_BITS                      1
 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_SHIFT                     12
 
 /* XgxsBlk0 :: lssRinfo :: lss_function_id8 [11:11] */
 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_MASK                    0x0800
 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_ALIGN                   0
 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_BITS                    1
 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_SHIFT                   11
 
 /* XgxsBlk0 :: lssRinfo :: lssL_info_byte8 [10:10] */
 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_MASK                     0x0400
 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_ALIGN                    0
 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_BITS                     1
 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_SHIFT                    10
 
 /* XgxsBlk0 :: lssRinfo :: reserved1 [09:09] */
 #define XGXSBLK0_LSSRINFO_RESERVED1_MASK                           0x0200
 #define XGXSBLK0_LSSRINFO_RESERVED1_ALIGN                          0
 #define XGXSBLK0_LSSRINFO_RESERVED1_BITS                           1
 #define XGXSBLK0_LSSRINFO_RESERVED1_SHIFT                          9
 
 /* XgxsBlk0 :: lssRinfo :: lssR_info_byte [08:00] */
 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_MASK                      0x01ff
 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_ALIGN                     0
 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_BITS                      9
 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk0 :: mmdSelect
  */
 /* XgxsBlk0 :: mmdSelect :: multiPRTs_en [15:15] */
 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_MASK                       0x8000
 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_ALIGN                      0
 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_BITS                       1
 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_SHIFT                      15
 
 /* XgxsBlk0 :: mmdSelect :: multiMMDs_en [14:14] */
 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_MASK                       0x4000
 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_ALIGN                      0
 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_BITS                       1
 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_SHIFT                      14
 
 /* XgxsBlk0 :: mmdSelect :: reserved0 [13:04] */
 #define XGXSBLK0_MMDSELECT_RESERVED0_MASK                          0x3ff0
 #define XGXSBLK0_MMDSELECT_RESERVED0_ALIGN                         0
 #define XGXSBLK0_MMDSELECT_RESERVED0_BITS                          10
 #define XGXSBLK0_MMDSELECT_RESERVED0_SHIFT                         4
 
 /* XgxsBlk0 :: mmdSelect :: devAN_en [03:03] */
 #define XGXSBLK0_MMDSELECT_DEVAN_EN_MASK                           0x0008
 #define XGXSBLK0_MMDSELECT_DEVAN_EN_ALIGN                          0
 #define XGXSBLK0_MMDSELECT_DEVAN_EN_BITS                           1
 #define XGXSBLK0_MMDSELECT_DEVAN_EN_SHIFT                          3
 
 /* XgxsBlk0 :: mmdSelect :: devPMD_en [02:02] */
 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_MASK                          0x0004
 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_ALIGN                         0
 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_BITS                          1
 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_SHIFT                         2
 
 /* XgxsBlk0 :: mmdSelect :: devDEVAD_en [01:01] */
 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_MASK                        0x0002
 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_ALIGN                       0
 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_BITS                        1
 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_SHIFT                       1
 
 /* XgxsBlk0 :: mmdSelect :: devCL22_en [00:00] */
 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_MASK                         0x0001
 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_ALIGN                        0
 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_BITS                         1
 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_SHIFT                        0
 
 
 /****************************************************************************
  * XgxsBlk0 :: miscControl1
  */
 /* XgxsBlk0 :: miscControl1 :: PMD_Lane3_tx_disable [15:15] */
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_MASK            0x8000
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_ALIGN           0
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_BITS            1
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_SHIFT           15
 
 /* XgxsBlk0 :: miscControl1 :: PMD_Lane2_tx_disable [14:14] */
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_MASK            0x4000
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_ALIGN           0
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_BITS            1
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_SHIFT           14
 
 /* XgxsBlk0 :: miscControl1 :: PMD_Lane1_tx_disable [13:13] */
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_MASK            0x2000
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_ALIGN           0
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_BITS            1
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_SHIFT           13
 
 /* XgxsBlk0 :: miscControl1 :: PMD_Lane0_tx_disable [12:12] */
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_MASK            0x1000
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_ALIGN           0
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_BITS            1
 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_SHIFT           12
 
 /* XgxsBlk0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */
 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK           0x0800
 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN          0
 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS           1
 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT          11
 
 /* XgxsBlk0 :: miscControl1 :: PCS_dev_en_override [10:10] */
 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_MASK             0x0400
 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_ALIGN            0
 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_BITS             1
 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_SHIFT            10
 
 /* XgxsBlk0 :: miscControl1 :: PMD_dev_en_override [09:09] */
 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_MASK             0x0200
 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_ALIGN            0
 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_BITS             1
 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_SHIFT            9
 
 /* XgxsBlk0 :: miscControl1 :: reserved0 [08:08] */
 #define XGXSBLK0_MISCCONTROL1_RESERVED0_MASK                       0x0100
 #define XGXSBLK0_MISCCONTROL1_RESERVED0_ALIGN                      0
 #define XGXSBLK0_MISCCONTROL1_RESERVED0_BITS                       1
 #define XGXSBLK0_MISCCONTROL1_RESERVED0_SHIFT                      8
 
 /* XgxsBlk0 :: miscControl1 :: clear_linkdown [07:07] */
 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_MASK                  0x0080
 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_ALIGN                 0
 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_BITS                  1
 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_SHIFT                 7
 
 /* XgxsBlk0 :: miscControl1 :: latch_linkdown_enable [06:06] */
 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_MASK           0x0040
 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_ALIGN          0
 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_BITS           1
 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_SHIFT          6
 
 /* XgxsBlk0 :: miscControl1 :: reserved1 [05:05] */
 #define XGXSBLK0_MISCCONTROL1_RESERVED1_MASK                       0x0020
 #define XGXSBLK0_MISCCONTROL1_RESERVED1_ALIGN                      0
 #define XGXSBLK0_MISCCONTROL1_RESERVED1_BITS                       1
 #define XGXSBLK0_MISCCONTROL1_RESERVED1_SHIFT                      5
 
 /* XgxsBlk0 :: miscControl1 :: force_div5_for_lxck25 [04:04] */
 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_MASK           0x0010
 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_ALIGN          0
 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_BITS           1
 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_SHIFT          4
 
 /* XgxsBlk0 :: miscControl1 :: pardet10g_pwrdnLink_en [03:03] */
 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_MASK          0x0008
 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_ALIGN         0
 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_BITS          1
 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_SHIFT         3
 
 /* XgxsBlk0 :: miscControl1 :: invert_rx_sigdet [02:02] */
 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_MASK                0x0004
 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_ALIGN               0
 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_BITS                1
 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_SHIFT               2
 
 /* XgxsBlk0 :: miscControl1 :: ieee_blksel_autodet [01:01] */
 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_MASK             0x0002
 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_ALIGN            0
 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_BITS             1
 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_SHIFT            1
 
 /* XgxsBlk0 :: miscControl1 :: ieee_blksel_val [00:00] */
 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_MASK                 0x0001
 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_ALIGN                0
 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_BITS                 1
 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_SHIFT                0
 
 
 /****************************************************************************
  * XgxsBlk0 :: BlockAddress
  */
 /* XgxsBlk0 :: BlockAddress :: reserved0 [15:15] */
 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_MASK                       0x8000
 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_ALIGN                      0
 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_BITS                       1
 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_SHIFT                      15
 
 /* XgxsBlk0 :: BlockAddress :: BlockAddress [14:04] */
 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_MASK                    0x7ff0
 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_ALIGN                   0
 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_BITS                    11
 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_SHIFT                   4
 
 /* XgxsBlk0 :: BlockAddress :: reserved1 [03:00] */
 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_MASK                       0x000f
 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_ALIGN                      0
 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_BITS                       4
 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_SHIFT                      0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk1
  */
 /****************************************************************************
  * XgxsBlk1 :: deskew
  */
 /* XgxsBlk1 :: deskew :: link_en [15:15] */
 #define XGXSBLK1_DESKEW_LINK_EN_MASK                               0x8000
 #define XGXSBLK1_DESKEW_LINK_EN_ALIGN                              0
 #define XGXSBLK1_DESKEW_LINK_EN_BITS                               1
 #define XGXSBLK1_DESKEW_LINK_EN_SHIFT                              15
 
 /* XgxsBlk1 :: deskew :: deskew_hyst_en [14:14] */
 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_MASK                        0x4000
 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_ALIGN                       0
 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_BITS                        1
 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_SHIFT                       14
 
 /* XgxsBlk1 :: deskew :: dswin [13:09] */
 #define XGXSBLK1_DESKEW_DSWIN_MASK                                 0x3e00
 #define XGXSBLK1_DESKEW_DSWIN_ALIGN                                0
 #define XGXSBLK1_DESKEW_DSWIN_BITS                                 5
 #define XGXSBLK1_DESKEW_DSWIN_SHIFT                                9
 
 /* XgxsBlk1 :: deskew :: mpwin [08:00] */
 #define XGXSBLK1_DESKEW_MPWIN_MASK                                 0x01ff
 #define XGXSBLK1_DESKEW_MPWIN_ALIGN                                0
 #define XGXSBLK1_DESKEW_MPWIN_BITS                                 9
 #define XGXSBLK1_DESKEW_MPWIN_SHIFT                                0
 
 
 /****************************************************************************
  * XgxsBlk1 :: link
  */
 /* XgxsBlk1 :: link :: Acolwin [15:00] */
 #define XGXSBLK1_LINK_ACOLWIN_MASK                                 0xffff
 #define XGXSBLK1_LINK_ACOLWIN_ALIGN                                0
 #define XGXSBLK1_LINK_ACOLWIN_BITS                                 16
 #define XGXSBLK1_LINK_ACOLWIN_SHIFT                                0
 
 
 /****************************************************************************
  * XgxsBlk1 :: testRx
  */
 /* XgxsBlk1 :: testRx :: reserved0 [15:08] */
 #define XGXSBLK1_TESTRX_RESERVED0_MASK                             0xff00
 #define XGXSBLK1_TESTRX_RESERVED0_ALIGN                            0
 #define XGXSBLK1_TESTRX_RESERVED0_BITS                             8
 #define XGXSBLK1_TESTRX_RESERVED0_SHIFT                            8
 
 /* XgxsBlk1 :: testRx :: rx_inBandMdio_Qfltr_en [07:07] */
 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_MASK                0x0080
 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_ALIGN               0
 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_BITS                1
 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_SHIFT               7
 
 /* XgxsBlk1 :: testRx :: link_force [06:06] */
 #define XGXSBLK1_TESTRX_LINK_FORCE_MASK                            0x0040
 #define XGXSBLK1_TESTRX_LINK_FORCE_ALIGN                           0
 #define XGXSBLK1_TESTRX_LINK_FORCE_BITS                            1
 #define XGXSBLK1_TESTRX_LINK_FORCE_SHIFT                           6
 
 /* XgxsBlk1 :: testRx :: rxtm_modsel [05:03] */
 #define XGXSBLK1_TESTRX_RXTM_MODSEL_MASK                           0x0038
 #define XGXSBLK1_TESTRX_RXTM_MODSEL_ALIGN                          0
 #define XGXSBLK1_TESTRX_RXTM_MODSEL_BITS                           3
 #define XGXSBLK1_TESTRX_RXTM_MODSEL_SHIFT                          3
 
 /* XgxsBlk1 :: testRx :: rxtm_tstsel [02:00] */
 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_MASK                           0x0007
 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_ALIGN                          0
 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_BITS                           3
 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_SHIFT                          0
 
 
 /****************************************************************************
  * XgxsBlk1 :: testTx
  */
 /* XgxsBlk1 :: testTx :: reserved0 [15:08] */
 #define XGXSBLK1_TESTTX_RESERVED0_MASK                             0xff00
 #define XGXSBLK1_TESTTX_RESERVED0_ALIGN                            0
 #define XGXSBLK1_TESTTX_RESERVED0_BITS                             8
 #define XGXSBLK1_TESTTX_RESERVED0_SHIFT                            8
 
 /* XgxsBlk1 :: testTx :: rx_ck4x1muxsel [07:06] */
 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_MASK                        0x00c0
 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_ALIGN                       0
 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_BITS                        2
 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_SHIFT                       6
 
 /* XgxsBlk1 :: testTx :: txtm_modsel [05:03] */
 #define XGXSBLK1_TESTTX_TXTM_MODSEL_MASK                           0x0038
 #define XGXSBLK1_TESTTX_TXTM_MODSEL_ALIGN                          0
 #define XGXSBLK1_TESTTX_TXTM_MODSEL_BITS                           3
 #define XGXSBLK1_TESTTX_TXTM_MODSEL_SHIFT                          3
 
 /* XgxsBlk1 :: testTx :: txtm_tstsel [02:00] */
 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_MASK                           0x0007
 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_ALIGN                          0
 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_BITS                           3
 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_SHIFT                          0
 
 
 /****************************************************************************
  * XgxsBlk1 :: testXg
  */
 /* XgxsBlk1 :: testXg :: evnt_cntr_sel [15:15] */
 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_MASK                         0x8000
 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_ALIGN                        0
 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_BITS                         1
 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_SHIFT                        15
 
 /* XgxsBlk1 :: testXg :: txdt_sel [14:14] */
 #define XGXSBLK1_TESTXG_TXDT_SEL_MASK                              0x4000
 #define XGXSBLK1_TESTXG_TXDT_SEL_ALIGN                             0
 #define XGXSBLK1_TESTXG_TXDT_SEL_BITS                              1
 #define XGXSBLK1_TESTXG_TXDT_SEL_SHIFT                             14
 
 /* XgxsBlk1 :: testXg :: slice_sel [13:12] */
 #define XGXSBLK1_TESTXG_SLICE_SEL_MASK                             0x3000
 #define XGXSBLK1_TESTXG_SLICE_SEL_ALIGN                            0
 #define XGXSBLK1_TESTXG_SLICE_SEL_BITS                             2
 #define XGXSBLK1_TESTXG_SLICE_SEL_SHIFT                            12
 
 /* XgxsBlk1 :: testXg :: reserved0 [11:08] */
 #define XGXSBLK1_TESTXG_RESERVED0_MASK                             0x0f00
 #define XGXSBLK1_TESTXG_RESERVED0_ALIGN                            0
 #define XGXSBLK1_TESTXG_RESERVED0_BITS                             4
 #define XGXSBLK1_TESTXG_RESERVED0_SHIFT                            8
 
 /* XgxsBlk1 :: testXg :: test_reg_sel [07:07] */
 #define XGXSBLK1_TESTXG_TEST_REG_SEL_MASK                          0x0080
 #define XGXSBLK1_TESTXG_TEST_REG_SEL_ALIGN                         0
 #define XGXSBLK1_TESTXG_TEST_REG_SEL_BITS                          1
 #define XGXSBLK1_TESTXG_TEST_REG_SEL_SHIFT                         7
 
 /* XgxsBlk1 :: testXg :: xg_txtstsel [06:04] */
 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_MASK                           0x0070
 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_ALIGN                          0
 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_BITS                           3
 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_SHIFT                          4
 
 /* XgxsBlk1 :: testXg :: xg_rxtstsel [03:00] */
 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_MASK                           0x000f
 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_ALIGN                          0
 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_BITS                           4
 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_SHIFT                          0
 
 
 /****************************************************************************
  * XgxsBlk1 :: laneCtrl0
  */
 /* XgxsBlk1 :: laneCtrl0 :: ed66en [15:12] */
 #define XGXSBLK1_LANECTRL0_ED66EN_MASK                             0xf000
 #define XGXSBLK1_LANECTRL0_ED66EN_ALIGN                            0
 #define XGXSBLK1_LANECTRL0_ED66EN_BITS                             4
 #define XGXSBLK1_LANECTRL0_ED66EN_SHIFT                            12
 
 /* XgxsBlk1 :: laneCtrl0 :: reserved0 [11:08] */
 #define XGXSBLK1_LANECTRL0_RESERVED0_MASK                          0x0f00
 #define XGXSBLK1_LANECTRL0_RESERVED0_ALIGN                         0
 #define XGXSBLK1_LANECTRL0_RESERVED0_BITS                          4
 #define XGXSBLK1_LANECTRL0_RESERVED0_SHIFT                         8
 
 /* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_rx [07:04] */
 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_MASK                     0x00f0
 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_ALIGN                    0
 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_BITS                     4
 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_SHIFT                    4
 
 /* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_tx [03:00] */
 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_MASK                     0x000f
 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_ALIGN                    0
 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_BITS                     4
 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_SHIFT                    0
 
 
 /****************************************************************************
  * XgxsBlk1 :: laneCtrl1
  */
 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln3 [15:14] */
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_MASK                      0xc000
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_ALIGN                     0
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_BITS                      2
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SHIFT                     14
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SWSDR_div2                0
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SWSDR_div1                1
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_DWSDR_div2                2
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_DWSDR_div1                3
 
 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln2 [13:12] */
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_MASK                      0x3000
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_ALIGN                     0
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_BITS                      2
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SHIFT                     12
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SWSDR_div2                0
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SWSDR_div1                1
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_DWSDR_div2                2
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_DWSDR_div1                3
 
 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln1 [11:10] */
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_MASK                      0x0c00
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_ALIGN                     0
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_BITS                      2
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SHIFT                     10
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SWSDR_div2                0
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SWSDR_div1                1
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_DWSDR_div2                2
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_DWSDR_div1                3
 
 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln0 [09:08] */
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_MASK                      0x0300
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_ALIGN                     0
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_BITS                      2
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SHIFT                     8
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SWSDR_div2                0
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SWSDR_div1                1
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_DWSDR_div2                2
 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_DWSDR_div1                3
 
 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln3 [07:06] */
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_MASK                      0x00c0
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_ALIGN                     0
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_BITS                      2
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SHIFT                     6
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SWSDR_div2                0
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SWSDR_div1                1
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_DWSDR_div2                2
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_DWSDR_div1                3
 
 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln2 [05:04] */
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_MASK                      0x0030
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_ALIGN                     0
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_BITS                      2
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SHIFT                     4
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SWSDR_div2                0
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SWSDR_div1                1
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_DWSDR_div2                2
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_DWSDR_div1                3
 
 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln1 [03:02] */
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_MASK                      0x000c
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_ALIGN                     0
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_BITS                      2
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SHIFT                     2
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SWSDR_div2                0
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SWSDR_div1                1
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_DWSDR_div2                2
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_DWSDR_div1                3
 
 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln0 [01:00] */
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_MASK                      0x0003
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_ALIGN                     0
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_BITS                      2
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SHIFT                     0
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SWSDR_div2                0
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SWSDR_div1                1
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_DWSDR_div2                2
 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_DWSDR_div1                3
 
 
 /****************************************************************************
  * XgxsBlk1 :: laneCtrl2
  */
 /* XgxsBlk1 :: laneCtrl2 :: cdet_en1g [15:12] */
 #define XGXSBLK1_LANECTRL2_CDET_EN1G_MASK                          0xf000
 #define XGXSBLK1_LANECTRL2_CDET_EN1G_ALIGN                         0
 #define XGXSBLK1_LANECTRL2_CDET_EN1G_BITS                          4
 #define XGXSBLK1_LANECTRL2_CDET_EN1G_SHIFT                         12
 
 /* XgxsBlk1 :: laneCtrl2 :: eden1g [11:08] */
 #define XGXSBLK1_LANECTRL2_EDEN1G_MASK                             0x0f00
 #define XGXSBLK1_LANECTRL2_EDEN1G_ALIGN                            0
 #define XGXSBLK1_LANECTRL2_EDEN1G_BITS                             4
 #define XGXSBLK1_LANECTRL2_EDEN1G_SHIFT                            8
 
 /* XgxsBlk1 :: laneCtrl2 :: rloop1g [07:04] */
 #define XGXSBLK1_LANECTRL2_RLOOP1G_MASK                            0x00f0
 #define XGXSBLK1_LANECTRL2_RLOOP1G_ALIGN                           0
 #define XGXSBLK1_LANECTRL2_RLOOP1G_BITS                            4
 #define XGXSBLK1_LANECTRL2_RLOOP1G_SHIFT                           4
 
 /* XgxsBlk1 :: laneCtrl2 :: gloop1g [03:00] */
 #define XGXSBLK1_LANECTRL2_GLOOP1G_MASK                            0x000f
 #define XGXSBLK1_LANECTRL2_GLOOP1G_ALIGN                           0
 #define XGXSBLK1_LANECTRL2_GLOOP1G_BITS                            4
 #define XGXSBLK1_LANECTRL2_GLOOP1G_SHIFT                           0
 
 
 /****************************************************************************
  * XgxsBlk1 :: laneCtrl3
  */
 /* XgxsBlk1 :: laneCtrl3 :: lock_ref [15:12] */
 #define XGXSBLK1_LANECTRL3_LOCK_REF_MASK                           0xf000
 #define XGXSBLK1_LANECTRL3_LOCK_REF_ALIGN                          0
 #define XGXSBLK1_LANECTRL3_LOCK_REF_BITS                           4
 #define XGXSBLK1_LANECTRL3_LOCK_REF_SHIFT                          12
 
 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn_force [11:11] */
 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_MASK                       0x0800
 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_ALIGN                      0
 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_BITS                       1
 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_SHIFT                      11
 
 /* XgxsBlk1 :: laneCtrl3 :: lock_ref_en [10:10] */
 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_MASK                        0x0400
 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_ALIGN                       0
 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_BITS                        1
 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_SHIFT                       10
 
 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn10g_pll_dis [09:09] */
 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_MASK                  0x0200
 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_ALIGN                 0
 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_BITS                  1
 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_SHIFT                 9
 
 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn_pll [08:08] */
 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_MASK                         0x0100
 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_ALIGN                        0
 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_BITS                         1
 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_SHIFT                        8
 
 /* XgxsBlk1 :: laneCtrl3 :: pwrdn_tx [07:04] */
 #define XGXSBLK1_LANECTRL3_PWRDN_TX_MASK                           0x00f0
 #define XGXSBLK1_LANECTRL3_PWRDN_TX_ALIGN                          0
 #define XGXSBLK1_LANECTRL3_PWRDN_TX_BITS                           4
 #define XGXSBLK1_LANECTRL3_PWRDN_TX_SHIFT                          4
 
 /* XgxsBlk1 :: laneCtrl3 :: pwrdn_rx [03:00] */
 #define XGXSBLK1_LANECTRL3_PWRDN_RX_MASK                           0x000f
 #define XGXSBLK1_LANECTRL3_PWRDN_RX_ALIGN                          0
 #define XGXSBLK1_LANECTRL3_PWRDN_RX_BITS                           4
 #define XGXSBLK1_LANECTRL3_PWRDN_RX_SHIFT                          0
 
 
 /****************************************************************************
  * XgxsBlk1 :: lanePrbs
  */
 /* XgxsBlk1 :: lanePrbs :: prbs_en3 [15:15] */
 #define XGXSBLK1_LANEPRBS_PRBS_EN3_MASK                            0x8000
 #define XGXSBLK1_LANEPRBS_PRBS_EN3_ALIGN                           0
 #define XGXSBLK1_LANEPRBS_PRBS_EN3_BITS                            1
 #define XGXSBLK1_LANEPRBS_PRBS_EN3_SHIFT                           15
 
 /* XgxsBlk1 :: lanePrbs :: prbs_inv3 [14:14] */
 #define XGXSBLK1_LANEPRBS_PRBS_INV3_MASK                           0x4000
 #define XGXSBLK1_LANEPRBS_PRBS_INV3_ALIGN                          0
 #define XGXSBLK1_LANEPRBS_PRBS_INV3_BITS                           1
 #define XGXSBLK1_LANEPRBS_PRBS_INV3_SHIFT                          14
 
 /* XgxsBlk1 :: lanePrbs :: prbs_order3 [13:12] */
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_MASK                         0x3000
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_ALIGN                        0
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_BITS                         2
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_SHIFT                        12
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs7                        0
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs15                       1
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs23                       2
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs31                       3
 
 /* XgxsBlk1 :: lanePrbs :: prbs_en2 [11:11] */
 #define XGXSBLK1_LANEPRBS_PRBS_EN2_MASK                            0x0800
 #define XGXSBLK1_LANEPRBS_PRBS_EN2_ALIGN                           0
 #define XGXSBLK1_LANEPRBS_PRBS_EN2_BITS                            1
 #define XGXSBLK1_LANEPRBS_PRBS_EN2_SHIFT                           11
 
 /* XgxsBlk1 :: lanePrbs :: prbs_inv2 [10:10] */
 #define XGXSBLK1_LANEPRBS_PRBS_INV2_MASK                           0x0400
 #define XGXSBLK1_LANEPRBS_PRBS_INV2_ALIGN                          0
 #define XGXSBLK1_LANEPRBS_PRBS_INV2_BITS                           1
 #define XGXSBLK1_LANEPRBS_PRBS_INV2_SHIFT                          10
 
 /* XgxsBlk1 :: lanePrbs :: prbs_order2 [09:08] */
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_MASK                         0x0300
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_ALIGN                        0
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_BITS                         2
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_SHIFT                        8
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs7                        0
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs15                       1
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs23                       2
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs31                       3
 
 /* XgxsBlk1 :: lanePrbs :: prbs_en1 [07:07] */
 #define XGXSBLK1_LANEPRBS_PRBS_EN1_MASK                            0x0080
 #define XGXSBLK1_LANEPRBS_PRBS_EN1_ALIGN                           0
 #define XGXSBLK1_LANEPRBS_PRBS_EN1_BITS                            1
 #define XGXSBLK1_LANEPRBS_PRBS_EN1_SHIFT                           7
 
 /* XgxsBlk1 :: lanePrbs :: prbs_inv1 [06:06] */
 #define XGXSBLK1_LANEPRBS_PRBS_INV1_MASK                           0x0040
 #define XGXSBLK1_LANEPRBS_PRBS_INV1_ALIGN                          0
 #define XGXSBLK1_LANEPRBS_PRBS_INV1_BITS                           1
 #define XGXSBLK1_LANEPRBS_PRBS_INV1_SHIFT                          6
 
 /* XgxsBlk1 :: lanePrbs :: prbs_order1 [05:04] */
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_MASK                         0x0030
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_ALIGN                        0
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_BITS                         2
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_SHIFT                        4
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs7                        0
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs15                       1
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs23                       2
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs31                       3
 
 /* XgxsBlk1 :: lanePrbs :: prbs_en0 [03:03] */
 #define XGXSBLK1_LANEPRBS_PRBS_EN0_MASK                            0x0008
 #define XGXSBLK1_LANEPRBS_PRBS_EN0_ALIGN                           0
 #define XGXSBLK1_LANEPRBS_PRBS_EN0_BITS                            1
 #define XGXSBLK1_LANEPRBS_PRBS_EN0_SHIFT                           3
 
 /* XgxsBlk1 :: lanePrbs :: prbs_inv0 [02:02] */
 #define XGXSBLK1_LANEPRBS_PRBS_INV0_MASK                           0x0004
 #define XGXSBLK1_LANEPRBS_PRBS_INV0_ALIGN                          0
 #define XGXSBLK1_LANEPRBS_PRBS_INV0_BITS                           1
 #define XGXSBLK1_LANEPRBS_PRBS_INV0_SHIFT                          2
 
 /* XgxsBlk1 :: lanePrbs :: prbs_order0 [01:00] */
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_MASK                         0x0003
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_ALIGN                        0
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_BITS                         2
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_SHIFT                        0
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs7                        0
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs15                       1
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs23                       2
 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs31                       3
 
 
 /****************************************************************************
  * XgxsBlk1 :: laneTest
  */
 /* XgxsBlk1 :: laneTest :: tmux_sel [15:12] */
 #define XGXSBLK1_LANETEST_TMUX_SEL_MASK                            0xf000
 #define XGXSBLK1_LANETEST_TMUX_SEL_ALIGN                           0
 #define XGXSBLK1_LANETEST_TMUX_SEL_BITS                            4
 #define XGXSBLK1_LANETEST_TMUX_SEL_SHIFT                           12
 #define XGXSBLK1_LANETEST_TMUX_SEL_off                             0
 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln0                          1
 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln1                          2
 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln2                          3
 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln3                          4
 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln0                          5
 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln1                          6
 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln2                          7
 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln3                          8
 #define XGXSBLK1_LANETEST_TMUX_SEL_pll                             11
 #define XGXSBLK1_LANETEST_TMUX_SEL_mdio                            12
 #define XGXSBLK1_LANETEST_TMUX_SEL_tMux1G                          15
 
 /* XgxsBlk1 :: laneTest :: inBandMdioRxRstEn [11:11] */
 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_MASK                   0x0800
 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_ALIGN                  0
 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_BITS                   1
 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_SHIFT                  11
 
 /* XgxsBlk1 :: laneTest :: pwrdn_ext_dis [10:10] */
 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_MASK                       0x0400
 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_ALIGN                      0
 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_BITS                       1
 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_SHIFT                      10
 
 /* XgxsBlk1 :: laneTest :: pwrdn_safe_dis [09:09] */
 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_MASK                      0x0200
 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_ALIGN                     0
 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_BITS                      1
 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_SHIFT                     9
 
 /* XgxsBlk1 :: laneTest :: pwrdwn_clks_en [08:08] */
 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_MASK                      0x0100
 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_ALIGN                     0
 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_BITS                      1
 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_SHIFT                     8
 
 /* XgxsBlk1 :: laneTest :: rxSeqStart_ext_dis [07:07] */
 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_MASK                  0x0080
 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_ALIGN                 0
 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_BITS                  1
 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_SHIFT                 7
 
 /* XgxsBlk1 :: laneTest :: pll_lock_rstb_r [06:06] */
 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_MASK                     0x0040
 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_ALIGN                    0
 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_BITS                     1
 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_SHIFT                    6
 
 /* XgxsBlk1 :: laneTest :: lfck_bypass [05:05] */
 #define XGXSBLK1_LANETEST_LFCK_BYPASS_MASK                         0x0020
 #define XGXSBLK1_LANETEST_LFCK_BYPASS_ALIGN                        0
 #define XGXSBLK1_LANETEST_LFCK_BYPASS_BITS                         1
 #define XGXSBLK1_LANETEST_LFCK_BYPASS_SHIFT                        5
 
 /* XgxsBlk1 :: laneTest :: rx_snoop_en [04:04] */
 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_MASK                         0x0010
 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_ALIGN                        0
 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_BITS                         1
 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_SHIFT                        4
 
 /* XgxsBlk1 :: laneTest :: mode_10g_snoop [03:00] */
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_MASK                      0x000f
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_ALIGN                     0
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_BITS                      4
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_SHIFT                     0
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS                      0
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXG_nCC                  1
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_Indlane_OS8               4
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_IndLane_OS5               5
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PCI                       7
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS_nLQ                  8
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS_nLQnCC               9
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PBypass                   10
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PBypass_nDSK              11
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_ComboCoreMode             12
 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_Clocks_off                15
 
 
 /****************************************************************************
  * XgxsBlk1 :: lssRevnt
  */
 /* union - case txActive [15:00] */
 /* XgxsBlk1 :: lssRevnt :: txActive [15:00] */
 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_MASK                   0xffff
 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_ALIGN                  0
 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_BITS                   16
 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_SHIFT                  0
 
 
 /* union - case lssRevent [15:00] */
 /* XgxsBlk1 :: lssRevnt :: lss_Revent [15:00] */
 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_MASK                0xffff
 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_ALIGN               0
 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_BITS                16
 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_SHIFT               0
 
 
 
 /****************************************************************************
  * XgxsBlk1 :: dskevnt
  */
 /* union - case rxActive [15:00] */
 /* XgxsBlk1 :: dskevnt :: rxActive [15:00] */
 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_MASK                    0xffff
 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_ALIGN                   0
 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_BITS                    16
 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_SHIFT                   0
 
 
 /* union - case deskwevent [15:00] */
 /* XgxsBlk1 :: dskevnt :: deskewEvent [15:00] */
 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_MASK               0xffff
 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_ALIGN              0
 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_BITS               16
 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_SHIFT              0
 
 
 
 /****************************************************************************
  * XgxsBlk1 :: Aerrevnt
  */
 /* XgxsBlk1 :: Aerrevnt :: Aerrevnt [15:00] */
 #define XGXSBLK1_AERREVNT_AERREVNT_MASK                            0xffff
 #define XGXSBLK1_AERREVNT_AERREVNT_ALIGN                           0
 #define XGXSBLK1_AERREVNT_AERREVNT_BITS                            16
 #define XGXSBLK1_AERREVNT_AERREVNT_SHIFT                           0
 
 
 /****************************************************************************
  * XgxsBlk1 :: ckcmpevnt
  */
 /* XgxsBlk1 :: ckcmpevnt :: ckcmpevnt [15:00] */
 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_MASK                          0xffff
 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_ALIGN                         0
 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_BITS                          16
 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_SHIFT                         0
 
 
 /****************************************************************************
  * XgxsBlk1 :: BlockAddress
  */
 /* XgxsBlk1 :: BlockAddress :: reserved0 [15:15] */
 #define XGXSBLK1_BLOCKADDRESS_RESERVED0_MASK                       0x8000
 #define XGXSBLK1_BLOCKADDRESS_RESERVED0_ALIGN                      0
 #define XGXSBLK1_BLOCKADDRESS_RESERVED0_BITS                       1
 #define XGXSBLK1_BLOCKADDRESS_RESERVED0_SHIFT                      15
 
 /* XgxsBlk1 :: BlockAddress :: BlockAddress [14:04] */
 #define XGXSBLK1_BLOCKADDRESS_BLOCKADDRESS_MASK                    0x7ff0
 #define XGXSBLK1_BLOCKADDRESS_BLOCKADDRESS_ALIGN                   0
 #define XGXSBLK1_BLOCKADDRESS_BLOCKADDRESS_BITS                    11
 #define XGXSBLK1_BLOCKADDRESS_BLOCKADDRESS_SHIFT                   4
 
 /* XgxsBlk1 :: BlockAddress :: reserved1 [03:00] */
 #define XGXSBLK1_BLOCKADDRESS_RESERVED1_MASK                       0x000f
 #define XGXSBLK1_BLOCKADDRESS_RESERVED1_ALIGN                      0
 #define XGXSBLK1_BLOCKADDRESS_RESERVED1_BITS                       4
 #define XGXSBLK1_BLOCKADDRESS_RESERVED1_SHIFT                      0
 
 
 /****************************************************************************
  * Warpcore_USER_TxBert
  */
 /****************************************************************************
  * TxBert :: txBertCtrl
  */
 /* TxBert :: txBertCtrl :: pkt_en [15:15] */
 #define TXBERT_TXBERTCTRL_PKT_EN_MASK                              0x8000
 #define TXBERT_TXBERTCTRL_PKT_EN_ALIGN                             0
 #define TXBERT_TXBERTCTRL_PKT_EN_BITS                              1
 #define TXBERT_TXBERTCTRL_PKT_EN_SHIFT                             15
 
 /* TxBert :: txBertCtrl :: seed_ld [14:14] */
 #define TXBERT_TXBERTCTRL_SEED_LD_MASK                             0x4000
 #define TXBERT_TXBERTCTRL_SEED_LD_ALIGN                            0
 #define TXBERT_TXBERTCTRL_SEED_LD_BITS                             1
 #define TXBERT_TXBERTCTRL_SEED_LD_SHIFT                            14
 
 /* TxBert :: txBertCtrl :: prbs_order [13:12] */
 #define TXBERT_TXBERTCTRL_PRBS_ORDER_MASK                          0x3000
 #define TXBERT_TXBERTCTRL_PRBS_ORDER_ALIGN                         0
 #define TXBERT_TXBERTCTRL_PRBS_ORDER_BITS                          2
 #define TXBERT_TXBERTCTRL_PRBS_ORDER_SHIFT                         12
 
 /* TxBert :: txBertCtrl :: ramp_en [11:11] */
 #define TXBERT_TXBERTCTRL_RAMP_EN_MASK                             0x0800
 #define TXBERT_TXBERTCTRL_RAMP_EN_ALIGN                            0
 #define TXBERT_TXBERTCTRL_RAMP_EN_BITS                             1
 #define TXBERT_TXBERTCTRL_RAMP_EN_SHIFT                            11
 
 /* TxBert :: txBertCtrl :: rndm_en [10:10] */
 #define TXBERT_TXBERTCTRL_RNDM_EN_MASK                             0x0400
 #define TXBERT_TXBERTCTRL_RNDM_EN_ALIGN                            0
 #define TXBERT_TXBERTCTRL_RNDM_EN_BITS                             1
 #define TXBERT_TXBERTCTRL_RNDM_EN_SHIFT                            10
 
 /* TxBert :: txBertCtrl :: Q_en [09:09] */
 #define TXBERT_TXBERTCTRL_Q_EN_MASK                                0x0200
 #define TXBERT_TXBERTCTRL_Q_EN_ALIGN                               0
 #define TXBERT_TXBERTCTRL_Q_EN_BITS                                1
 #define TXBERT_TXBERTCTRL_Q_EN_SHIFT                               9
 
 /* TxBert :: txBertCtrl :: Q_link_en [08:08] */
 #define TXBERT_TXBERTCTRL_Q_LINK_EN_MASK                           0x0100
 #define TXBERT_TXBERTCTRL_Q_LINK_EN_ALIGN                          0
 #define TXBERT_TXBERTCTRL_Q_LINK_EN_BITS                           1
 #define TXBERT_TXBERTCTRL_Q_LINK_EN_SHIFT                          8
 
 /* TxBert :: txBertCtrl :: skew_en [07:07] */
 #define TXBERT_TXBERTCTRL_SKEW_EN_MASK                             0x0080
 #define TXBERT_TXBERTCTRL_SKEW_EN_ALIGN                            0
 #define TXBERT_TXBERTCTRL_SKEW_EN_BITS                             1
 #define TXBERT_TXBERTCTRL_SKEW_EN_SHIFT                            7
 
 /* TxBert :: txBertCtrl :: cjpat_en [06:06] */
 #define TXBERT_TXBERTCTRL_CJPAT_EN_MASK                            0x0040
 #define TXBERT_TXBERTCTRL_CJPAT_EN_ALIGN                           0
 #define TXBERT_TXBERTCTRL_CJPAT_EN_BITS                            1
 #define TXBERT_TXBERTCTRL_CJPAT_EN_SHIFT                           6
 
 /* TxBert :: txBertCtrl :: crpat_en [05:05] */
 #define TXBERT_TXBERTCTRL_CRPAT_EN_MASK                            0x0020
 #define TXBERT_TXBERTCTRL_CRPAT_EN_ALIGN                           0
 #define TXBERT_TXBERTCTRL_CRPAT_EN_BITS                            1
 #define TXBERT_TXBERTCTRL_CRPAT_EN_SHIFT                           5
 
 /* TxBert :: txBertCtrl :: cjrmp_en [04:04] */
 #define TXBERT_TXBERTCTRL_CJRMP_EN_MASK                            0x0010
 #define TXBERT_TXBERTCTRL_CJRMP_EN_ALIGN                           0
 #define TXBERT_TXBERTCTRL_CJRMP_EN_BITS                            1
 #define TXBERT_TXBERTCTRL_CJRMP_EN_SHIFT                           4
 
 /* TxBert :: txBertCtrl :: txck_out_force [03:03] */
 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_MASK                      0x0008
 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_ALIGN                     0
 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_BITS                      1
 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_SHIFT                     3
 
 /* TxBert :: txBertCtrl :: fifo_rst [02:02] */
 #define TXBERT_TXBERTCTRL_FIFO_RST_MASK                            0x0004
 #define TXBERT_TXBERTCTRL_FIFO_RST_ALIGN                           0
 #define TXBERT_TXBERTCTRL_FIFO_RST_BITS                            1
 #define TXBERT_TXBERTCTRL_FIFO_RST_SHIFT                           2
 
 /* TxBert :: txBertCtrl :: countRst_dis [01:01] */
 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_MASK                        0x0002
 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_ALIGN                       0
 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_BITS                        1
 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_SHIFT                       1
 
 /* TxBert :: txBertCtrl :: count_clr [00:00] */
 #define TXBERT_TXBERTCTRL_COUNT_CLR_MASK                           0x0001
 #define TXBERT_TXBERTCTRL_COUNT_CLR_ALIGN                          0
 #define TXBERT_TXBERTCTRL_COUNT_CLR_BITS                           1
 #define TXBERT_TXBERTCTRL_COUNT_CLR_SHIFT                          0
 
 
 /****************************************************************************
  * TxBert :: txBertSopEop
  */
 /* TxBert :: txBertSopEop :: SOP [15:08] */
 #define TXBERT_TXBERTSOPEOP_SOP_MASK                               0xff00
 #define TXBERT_TXBERTSOPEOP_SOP_ALIGN                              0
 #define TXBERT_TXBERTSOPEOP_SOP_BITS                               8
 #define TXBERT_TXBERTSOPEOP_SOP_SHIFT                              8
 
 /* TxBert :: txBertSopEop :: EOP [07:00] */
 #define TXBERT_TXBERTSOPEOP_EOP_MASK                               0x00ff
 #define TXBERT_TXBERTSOPEOP_EOP_ALIGN                              0
 #define TXBERT_TXBERTSOPEOP_EOP_BITS                               8
 #define TXBERT_TXBERTSOPEOP_EOP_SHIFT                              0
 
 
 /****************************************************************************
  * TxBert :: txBertSize0
  */
 /* TxBert :: txBertSize0 :: ipg_size [15:10] */
 #define TXBERT_TXBERTSIZE0_IPG_SIZE_MASK                           0xfc00
 #define TXBERT_TXBERTSIZE0_IPG_SIZE_ALIGN                          0
 #define TXBERT_TXBERTSIZE0_IPG_SIZE_BITS                           6
 #define TXBERT_TXBERTSIZE0_IPG_SIZE_SHIFT                          10
 
 /* TxBert :: txBertSize0 :: pkt_size [09:00] */
 #define TXBERT_TXBERTSIZE0_PKT_SIZE_MASK                           0x03ff
 #define TXBERT_TXBERTSIZE0_PKT_SIZE_ALIGN                          0
 #define TXBERT_TXBERTSIZE0_PKT_SIZE_BITS                           10
 #define TXBERT_TXBERTSIZE0_PKT_SIZE_SHIFT                          0
 
 
 /****************************************************************************
  * TxBert :: txBertSize1
  */
 /* TxBert :: txBertSize1 :: awin_size [15:10] */
 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_MASK                          0xfc00
 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_ALIGN                         0
 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_BITS                          6
 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_SHIFT                         10
 
 /* TxBert :: txBertSize1 :: PktStpCnt [09:00] */
 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_MASK                          0x03ff
 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_ALIGN                         0
 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_BITS                          10
 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_SHIFT                         0
 
 
 /****************************************************************************
  * TxBert :: txBertSize2
  */
 /* TxBert :: txBertSize2 :: skew3 [15:12] */
 #define TXBERT_TXBERTSIZE2_SKEW3_MASK                              0xf000
 #define TXBERT_TXBERTSIZE2_SKEW3_ALIGN                             0
 #define TXBERT_TXBERTSIZE2_SKEW3_BITS                              4
 #define TXBERT_TXBERTSIZE2_SKEW3_SHIFT                             12
 
 /* TxBert :: txBertSize2 :: skew2 [11:08] */
 #define TXBERT_TXBERTSIZE2_SKEW2_MASK                              0x0f00
 #define TXBERT_TXBERTSIZE2_SKEW2_ALIGN                             0
 #define TXBERT_TXBERTSIZE2_SKEW2_BITS                              4
 #define TXBERT_TXBERTSIZE2_SKEW2_SHIFT                             8
 
 /* TxBert :: txBertSize2 :: skew1 [07:04] */
 #define TXBERT_TXBERTSIZE2_SKEW1_MASK                              0x00f0
 #define TXBERT_TXBERTSIZE2_SKEW1_ALIGN                             0
 #define TXBERT_TXBERTSIZE2_SKEW1_BITS                              4
 #define TXBERT_TXBERTSIZE2_SKEW1_SHIFT                             4
 
 /* TxBert :: txBertSize2 :: skew0 [03:00] */
 #define TXBERT_TXBERTSIZE2_SKEW0_MASK                              0x000f
 #define TXBERT_TXBERTSIZE2_SKEW0_ALIGN                             0
 #define TXBERT_TXBERTSIZE2_SKEW0_BITS                              4
 #define TXBERT_TXBERTSIZE2_SKEW0_SHIFT                             0
 
 
 /****************************************************************************
  * TxBert :: txBertIpg0
  */
 /* TxBert :: txBertIpg0 :: ipg1 [15:08] */
 #define TXBERT_TXBERTIPG0_IPG1_MASK                                0xff00
 #define TXBERT_TXBERTIPG0_IPG1_ALIGN                               0
 #define TXBERT_TXBERTIPG0_IPG1_BITS                                8
 #define TXBERT_TXBERTIPG0_IPG1_SHIFT                               8
 
 /* TxBert :: txBertIpg0 :: ipg0 [07:00] */
 #define TXBERT_TXBERTIPG0_IPG0_MASK                                0x00ff
 #define TXBERT_TXBERTIPG0_IPG0_ALIGN                               0
 #define TXBERT_TXBERTIPG0_IPG0_BITS                                8
 #define TXBERT_TXBERTIPG0_IPG0_SHIFT                               0
 
 
 /****************************************************************************
  * TxBert :: txBertIpg1
  */
 /* TxBert :: txBertIpg1 :: ipg3 [15:08] */
 #define TXBERT_TXBERTIPG1_IPG3_MASK                                0xff00
 #define TXBERT_TXBERTIPG1_IPG3_ALIGN                               0
 #define TXBERT_TXBERTIPG1_IPG3_BITS                                8
 #define TXBERT_TXBERTIPG1_IPG3_SHIFT                               8
 
 /* TxBert :: txBertIpg1 :: ipg2 [07:00] */
 #define TXBERT_TXBERTIPG1_IPG2_MASK                                0x00ff
 #define TXBERT_TXBERTIPG1_IPG2_ALIGN                               0
 #define TXBERT_TXBERTIPG1_IPG2_BITS                                8
 #define TXBERT_TXBERTIPG1_IPG2_SHIFT                               0
 
 
 /****************************************************************************
  * TxBert :: txBertByteU
  */
 /* TxBert :: txBertByteU :: byte_count_high [15:00] */
 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_MASK                    0xffff
 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN                   0
 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_BITS                    16
 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT                   0
 
 
 /****************************************************************************
  * TxBert :: txBertByteL
  */
 /* TxBert :: txBertByteL :: byte_count_low [15:00] */
 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_MASK                     0xffff
 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_ALIGN                    0
 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_BITS                     16
 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_SHIFT                    0
 
 
 /****************************************************************************
  * TxBert :: txBertPacketU
  */
 /* TxBert :: txBertPacketU :: pkt_count_high [15:00] */
 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_MASK                   0xffff
 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_ALIGN                  0
 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_BITS                   16
 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_SHIFT                  0
 
 
 /****************************************************************************
  * TxBert :: txBertPacketL
  */
 /* TxBert :: txBertPacketL :: pkt_count_low [15:00] */
 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_MASK                    0xffff
 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_ALIGN                   0
 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_BITS                    16
 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_SHIFT                   0
 
 
 /****************************************************************************
  * TxBert :: txBertCtrl1
  */
 /* TxBert :: txBertCtrl1 :: reserved0 [15:01] */
 #define TXBERT_TXBERTCTRL1_RESERVED0_MASK                          0xfffe
 #define TXBERT_TXBERTCTRL1_RESERVED0_ALIGN                         0
 #define TXBERT_TXBERTCTRL1_RESERVED0_BITS                          15
 #define TXBERT_TXBERTCTRL1_RESERVED0_SHIFT                         1
 
 /* TxBert :: txBertCtrl1 :: lpi_en [00:00] */
 #define TXBERT_TXBERTCTRL1_LPI_EN_MASK                             0x0001
 #define TXBERT_TXBERTCTRL1_LPI_EN_ALIGN                            0
 #define TXBERT_TXBERTCTRL1_LPI_EN_BITS                             1
 #define TXBERT_TXBERTCTRL1_LPI_EN_SHIFT                            0
 
 
 /****************************************************************************
  * Warpcore_USER_RxBert
  */
 /****************************************************************************
  * RxBert :: rxBertCtrl
  */
 /* RxBert :: rxBertCtrl :: pkt_en [15:15] */
 #define RXBERT_RXBERTCTRL_PKT_EN_MASK                              0x8000
 #define RXBERT_RXBERTCTRL_PKT_EN_ALIGN                             0
 #define RXBERT_RXBERTCTRL_PKT_EN_BITS                              1
 #define RXBERT_RXBERTCTRL_PKT_EN_SHIFT                             15
 
 /* RxBert :: rxBertCtrl :: seed_ld [14:14] */
 #define RXBERT_RXBERTCTRL_SEED_LD_MASK                             0x4000
 #define RXBERT_RXBERTCTRL_SEED_LD_ALIGN                            0
 #define RXBERT_RXBERTCTRL_SEED_LD_BITS                             1
 #define RXBERT_RXBERTCTRL_SEED_LD_SHIFT                            14
 
 /* RxBert :: rxBertCtrl :: prbs_order [13:12] */
 #define RXBERT_RXBERTCTRL_PRBS_ORDER_MASK                          0x3000
 #define RXBERT_RXBERTCTRL_PRBS_ORDER_ALIGN                         0
 #define RXBERT_RXBERTCTRL_PRBS_ORDER_BITS                          2
 #define RXBERT_RXBERTCTRL_PRBS_ORDER_SHIFT                         12
 
 /* RxBert :: rxBertCtrl :: ramp_en [11:11] */
 #define RXBERT_RXBERTCTRL_RAMP_EN_MASK                             0x0800
 #define RXBERT_RXBERTCTRL_RAMP_EN_ALIGN                            0
 #define RXBERT_RXBERTCTRL_RAMP_EN_BITS                             1
 #define RXBERT_RXBERTCTRL_RAMP_EN_SHIFT                            11
 
 /* RxBert :: rxBertCtrl :: cgbad_tst_en [10:10] */
 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_MASK                        0x0400
 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_ALIGN                       0
 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_BITS                        1
 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_SHIFT                       10
 
 /* RxBert :: rxBertCtrl :: crcChk_en [09:09] */
 #define RXBERT_RXBERTCTRL_CRCCHK_EN_MASK                           0x0200
 #define RXBERT_RXBERTCTRL_CRCCHK_EN_ALIGN                          0
 #define RXBERT_RXBERTCTRL_CRCCHK_EN_BITS                           1
 #define RXBERT_RXBERTCTRL_CRCCHK_EN_SHIFT                          9
 
 /* RxBert :: rxBertCtrl :: countRst_dis [08:08] */
 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_MASK                        0x0100
 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_ALIGN                       0
 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_BITS                        1
 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_SHIFT                       8
 
 /* RxBert :: rxBertCtrl :: rxStatSel [07:07] */
 #define RXBERT_RXBERTCTRL_RXSTATSEL_MASK                           0x0080
 #define RXBERT_RXBERTCTRL_RXSTATSEL_ALIGN                          0
 #define RXBERT_RXBERTCTRL_RXSTATSEL_BITS                           1
 #define RXBERT_RXBERTCTRL_RXSTATSEL_SHIFT                          7
 
 /* RxBert :: rxBertCtrl :: source_sel_r [06:06] */
 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_MASK                        0x0040
 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_ALIGN                       0
 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_BITS                        1
 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_SHIFT                       6
 
 /* RxBert :: rxBertCtrl :: source_sel [05:04] */
 #define RXBERT_RXBERTCTRL_SOURCE_SEL_MASK                          0x0030
 #define RXBERT_RXBERTCTRL_SOURCE_SEL_ALIGN                         0
 #define RXBERT_RXBERTCTRL_SOURCE_SEL_BITS                          2
 #define RXBERT_RXBERTCTRL_SOURCE_SEL_SHIFT                         4
 
 /* RxBert :: rxBertCtrl :: slice_sel [03:02] */
 #define RXBERT_RXBERTCTRL_SLICE_SEL_MASK                           0x000c
 #define RXBERT_RXBERTCTRL_SLICE_SEL_ALIGN                          0
 #define RXBERT_RXBERTCTRL_SLICE_SEL_BITS                           2
 #define RXBERT_RXBERTCTRL_SLICE_SEL_SHIFT                          2
 
 /* RxBert :: rxBertCtrl :: err_clr [01:01] */
 #define RXBERT_RXBERTCTRL_ERR_CLR_MASK                             0x0002
 #define RXBERT_RXBERTCTRL_ERR_CLR_ALIGN                            0
 #define RXBERT_RXBERTCTRL_ERR_CLR_BITS                             1
 #define RXBERT_RXBERTCTRL_ERR_CLR_SHIFT                            1
 
 /* RxBert :: rxBertCtrl :: count_clr [00:00] */
 #define RXBERT_RXBERTCTRL_COUNT_CLR_MASK                           0x0001
 #define RXBERT_RXBERTCTRL_COUNT_CLR_ALIGN                          0
 #define RXBERT_RXBERTCTRL_COUNT_CLR_BITS                           1
 #define RXBERT_RXBERTCTRL_COUNT_CLR_SHIFT                          0
 
 
 /****************************************************************************
  * RxBert :: rxBertSopEop
  */
 /* RxBert :: rxBertSopEop :: SOP [15:08] */
 #define RXBERT_RXBERTSOPEOP_SOP_MASK                               0xff00
 #define RXBERT_RXBERTSOPEOP_SOP_ALIGN                              0
 #define RXBERT_RXBERTSOPEOP_SOP_BITS                               8
 #define RXBERT_RXBERTSOPEOP_SOP_SHIFT                              8
 
 /* RxBert :: rxBertSopEop :: EOP [07:00] */
 #define RXBERT_RXBERTSOPEOP_EOP_MASK                               0x00ff
 #define RXBERT_RXBERTSOPEOP_EOP_ALIGN                              0
 #define RXBERT_RXBERTSOPEOP_EOP_BITS                               8
 #define RXBERT_RXBERTSOPEOP_EOP_SHIFT                              0
 
 
 /****************************************************************************
  * RxBert :: rxBertByteU
  */
 /* RxBert :: rxBertByteU :: byte_count_high [15:00] */
 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_MASK                    0xffff
 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN                   0
 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_BITS                    16
 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT                   0
 
 
 /****************************************************************************
  * RxBert :: rxBertByteL
  */
 /* RxBert :: rxBertByteL :: byte_count_low [15:00] */
 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_MASK                     0xffff
 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_ALIGN                    0
 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_BITS                     16
 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_SHIFT                    0
 
 
 /****************************************************************************
  * RxBert :: rxBertPacketU
  */
 /* RxBert :: rxBertPacketU :: pkt_count_high [15:00] */
 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_MASK                   0xffff
 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_ALIGN                  0
 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_BITS                   16
 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_SHIFT                  0
 
 
 /****************************************************************************
  * RxBert :: rxBertPacketL
  */
 /* RxBert :: rxBertPacketL :: pkt_count_low [15:00] */
 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_MASK                    0xffff
 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_ALIGN                   0
 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_BITS                    16
 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_SHIFT                   0
 
 
 /****************************************************************************
  * RxBert :: rxBertBitErr
  */
 /* RxBert :: rxBertBitErr :: bit_err_count [15:00] */
 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_MASK                     0xffff
 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_ALIGN                    0
 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_BITS                     16
 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_SHIFT                    0
 
 
 /****************************************************************************
  * RxBert :: rxBertByteErr
  */
 /* RxBert :: rxBertByteErr :: byte_err_count [15:00] */
 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_MASK                   0xffff
 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_ALIGN                  0
 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_BITS                   16
 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_SHIFT                  0
 
 
 /****************************************************************************
  * RxBert :: rxBertPktErr
  */
 /* RxBert :: rxBertPktErr :: pkt_err_count [15:00] */
 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_MASK                     0xffff
 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_ALIGN                    0
 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_BITS                     16
 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_SHIFT                    0
 
 
 /****************************************************************************
  * RxBert :: rxBertStatus
  */
 /* union - case rxStatSel [15:00] */
 /* RxBert :: rxBertStatus :: reserved0 [15:08] */
 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_MASK               0xff00
 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_ALIGN              0
 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_BITS               8
 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_SHIFT              8
 
 /* RxBert :: rxBertStatus :: rx_10g_tmux [07:00] */
 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_MASK             0x00ff
 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_ALIGN            0
 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_BITS             8
 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_SHIFT            0
 
 
 /* union - case crcChk_en [15:00] */
 /* RxBert :: rxBertStatus :: link [15:15] */
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_MASK                    0x8000
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_ALIGN                   0
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_BITS                    1
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_SHIFT                   15
 
 /* RxBert :: rxBertStatus :: prbs_stky [14:14] */
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_MASK               0x4000
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_ALIGN              0
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_BITS               1
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_SHIFT              14
 
 /* RxBert :: rxBertStatus :: reserved0 [13:00] */
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_MASK               0x3fff
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_ALIGN              0
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_BITS               14
 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_SHIFT              0
 
 
 /* union - case rxBert [15:00] */
 /* RxBert :: rxBertStatus :: prbs_lock [15:15] */
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_MASK                  0x8000
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_ALIGN                 0
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_BITS                  1
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_SHIFT                 15
 
 /* RxBert :: rxBertStatus :: prbs_stky [14:14] */
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_MASK                  0x4000
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_ALIGN                 0
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_BITS                  1
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_SHIFT                 14
 
 /* RxBert :: rxBertStatus :: prbs_state [13:11] */
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_MASK                 0x3800
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_ALIGN                0
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_BITS                 3
 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_SHIFT                11
 
 /* RxBert :: rxBertStatus :: reserved0 [10:07] */
 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_MASK                  0x0780
 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_ALIGN                 0
 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_BITS                  4
 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_SHIFT                 7
 
 /* RxBert :: rxBertStatus :: bit_err_overflow [06:06] */
 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_MASK           0x0040
 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_ALIGN          0
 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_BITS           1
 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_SHIFT          6
 
 /* RxBert :: rxBertStatus :: reserved1 [05:04] */
 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_MASK                  0x0030
 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_ALIGN                 0
 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_BITS                  2
 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_SHIFT                 4
 
 /* RxBert :: rxBertStatus :: onefe_det [03:03] */
 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_MASK                  0x0008
 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_ALIGN                 0
 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_BITS                  1
 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_SHIFT                 3
 
 /* RxBert :: rxBertStatus :: xor_comp [02:00] */
 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_MASK                   0x0007
 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_ALIGN                  0
 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_BITS                   3
 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_SHIFT                  0
 
 
 
 /****************************************************************************
  * Warpcore_USER_PLL
  */
 /****************************************************************************
  * PLL :: anaPllStatus
  */
 /* PLL :: anaPllStatus :: pllSeqDone [15:15] */
 #define PLL_ANAPLLSTATUS_PLLSEQDONE_MASK                           0x8000
 #define PLL_ANAPLLSTATUS_PLLSEQDONE_ALIGN                          0
 #define PLL_ANAPLLSTATUS_PLLSEQDONE_BITS                           1
 #define PLL_ANAPLLSTATUS_PLLSEQDONE_SHIFT                          15
 
 /* PLL :: anaPllStatus :: freqDone [14:14] */
 #define PLL_ANAPLLSTATUS_FREQDONE_MASK                             0x4000
 #define PLL_ANAPLLSTATUS_FREQDONE_ALIGN                            0
 #define PLL_ANAPLLSTATUS_FREQDONE_BITS                             1
 #define PLL_ANAPLLSTATUS_FREQDONE_SHIFT                            14
 
 /* PLL :: anaPllStatus :: vcoDone [13:13] */
 #define PLL_ANAPLLSTATUS_VCODONE_MASK                              0x2000
 #define PLL_ANAPLLSTATUS_VCODONE_ALIGN                             0
 #define PLL_ANAPLLSTATUS_VCODONE_BITS                              1
 #define PLL_ANAPLLSTATUS_VCODONE_SHIFT                             13
 
 /* PLL :: anaPllStatus :: reserved0 [12:12] */
 #define PLL_ANAPLLSTATUS_RESERVED0_MASK                            0x1000
 #define PLL_ANAPLLSTATUS_RESERVED0_ALIGN                           0
 #define PLL_ANAPLLSTATUS_RESERVED0_BITS                            1
 #define PLL_ANAPLLSTATUS_RESERVED0_SHIFT                           12
 
 /* PLL :: anaPllStatus :: pllSeqPass [11:11] */
 #define PLL_ANAPLLSTATUS_PLLSEQPASS_MASK                           0x0800
 #define PLL_ANAPLLSTATUS_PLLSEQPASS_ALIGN                          0
 #define PLL_ANAPLLSTATUS_PLLSEQPASS_BITS                           1
 #define PLL_ANAPLLSTATUS_PLLSEQPASS_SHIFT                          11
 
 /* PLL :: anaPllStatus :: freqPass [10:10] */
 #define PLL_ANAPLLSTATUS_FREQPASS_MASK                             0x0400
 #define PLL_ANAPLLSTATUS_FREQPASS_ALIGN                            0
 #define PLL_ANAPLLSTATUS_FREQPASS_BITS                             1
 #define PLL_ANAPLLSTATUS_FREQPASS_SHIFT                            10
 
 /* PLL :: anaPllStatus :: vcoPass [09:09] */
 #define PLL_ANAPLLSTATUS_VCOPASS_MASK                              0x0200
 #define PLL_ANAPLLSTATUS_VCOPASS_ALIGN                             0
 #define PLL_ANAPLLSTATUS_VCOPASS_BITS                              1
 #define PLL_ANAPLLSTATUS_VCOPASS_SHIFT                             9
 
 /* PLL :: anaPllStatus :: reserved1 [08:08] */
 #define PLL_ANAPLLSTATUS_RESERVED1_MASK                            0x0100
 #define PLL_ANAPLLSTATUS_RESERVED1_ALIGN                           0
 #define PLL_ANAPLLSTATUS_RESERVED1_BITS                            1
 #define PLL_ANAPLLSTATUS_RESERVED1_SHIFT                           8
 
 /* PLL :: anaPllStatus :: slowdn [07:07] */
 #define PLL_ANAPLLSTATUS_SLOWDN_MASK                               0x0080
 #define PLL_ANAPLLSTATUS_SLOWDN_ALIGN                              0
 #define PLL_ANAPLLSTATUS_SLOWDN_BITS                               1
 #define PLL_ANAPLLSTATUS_SLOWDN_SHIFT                              7
 
 /* PLL :: anaPllStatus :: lostPllLock_SM [06:06] */
 #define PLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_MASK                       0x0040
 #define PLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_ALIGN                      0
 #define PLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_BITS                       1
 #define PLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_SHIFT                      6
 
 /* PLL :: anaPllStatus :: reserved2 [05:04] */
 #define PLL_ANAPLLSTATUS_RESERVED2_MASK                            0x0030
 #define PLL_ANAPLLSTATUS_RESERVED2_ALIGN                           0
 #define PLL_ANAPLLSTATUS_RESERVED2_BITS                            2
 #define PLL_ANAPLLSTATUS_RESERVED2_SHIFT                           4
 
 /* PLL :: anaPllStatus :: pll_mode_afe [03:00] */
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_MASK                         0x000f
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_ALIGN                        0
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_BITS                         4
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_SHIFT                        0
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div32                        0
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div36                        1
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div40                        2
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div42                        3
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div48                        4
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div50                        5
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div52                        6
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div54                        7
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div60                        8
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div64                        9
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div66                        10
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div68                        11
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div80                        12
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div120                       13
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div200                       14
 #define PLL_ANAPLLSTATUS_PLL_MODE_AFE_div240                       15
 
 
 /****************************************************************************
  * PLL :: anaPllControl
  */
 /* PLL :: anaPllControl :: pllRestart [15:15] */
 #define PLL_ANAPLLCONTROL_PLLRESTART_MASK                          0x8000
 #define PLL_ANAPLLCONTROL_PLLRESTART_ALIGN                         0
 #define PLL_ANAPLLCONTROL_PLLRESTART_BITS                          1
 #define PLL_ANAPLLCONTROL_PLLRESTART_SHIFT                         15
 
 /* PLL :: anaPllControl :: FreqDetRetry_en [14:14] */
 #define PLL_ANAPLLCONTROL_FREQDETRETRY_EN_MASK                     0x4000
 #define PLL_ANAPLLCONTROL_FREQDETRETRY_EN_ALIGN                    0
 #define PLL_ANAPLLCONTROL_FREQDETRETRY_EN_BITS                     1
 #define PLL_ANAPLLCONTROL_FREQDETRETRY_EN_SHIFT                    14
 
 /* PLL :: anaPllControl :: FreqDetRestart_en [13:13] */
 #define PLL_ANAPLLCONTROL_FREQDETRESTART_EN_MASK                   0x2000
 #define PLL_ANAPLLCONTROL_FREQDETRESTART_EN_ALIGN                  0
 #define PLL_ANAPLLCONTROL_FREQDETRESTART_EN_BITS                   1
 #define PLL_ANAPLLCONTROL_FREQDETRESTART_EN_SHIFT                  13
 
 /* PLL :: anaPllControl :: FreqMonitor_en [12:12] */
 #define PLL_ANAPLLCONTROL_FREQMONITOR_EN_MASK                      0x1000
 #define PLL_ANAPLLCONTROL_FREQMONITOR_EN_ALIGN                     0
 #define PLL_ANAPLLCONTROL_FREQMONITOR_EN_BITS                      1
 #define PLL_ANAPLLCONTROL_FREQMONITOR_EN_SHIFT                     12
 
 /* PLL :: anaPllControl :: VcopRetry_en [11:11] */
 #define PLL_ANAPLLCONTROL_VCOPRETRY_EN_MASK                        0x0800
 #define PLL_ANAPLLCONTROL_VCOPRETRY_EN_ALIGN                       0
 #define PLL_ANAPLLCONTROL_VCOPRETRY_EN_BITS                        1
 #define PLL_ANAPLLCONTROL_VCOPRETRY_EN_SHIFT                       11
 
 /* PLL :: anaPllControl :: VcoDone_en [10:10] */
 #define PLL_ANAPLLCONTROL_VCODONE_EN_MASK                          0x0400
 #define PLL_ANAPLLCONTROL_VCODONE_EN_ALIGN                         0
 #define PLL_ANAPLLCONTROL_VCODONE_EN_BITS                          1
 #define PLL_ANAPLLCONTROL_VCODONE_EN_SHIFT                         10
 
 /* PLL :: anaPllControl :: LinkRestart_en [09:09] */
 #define PLL_ANAPLLCONTROL_LINKRESTART_EN_MASK                      0x0200
 #define PLL_ANAPLLCONTROL_LINKRESTART_EN_ALIGN                     0
 #define PLL_ANAPLLCONTROL_LINKRESTART_EN_BITS                      1
 #define PLL_ANAPLLCONTROL_LINKRESTART_EN_SHIFT                     9
 
 /* PLL :: anaPllControl :: ByteSyncRestart_en [08:08] */
 #define PLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_MASK                  0x0100
 #define PLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_ALIGN                 0
 #define PLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_BITS                  1
 #define PLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_SHIFT                 8
 
 /* PLL :: anaPllControl :: PllForceDone_en [07:07] */
 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_EN_MASK                     0x0080
 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_EN_ALIGN                    0
 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_EN_BITS                     1
 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_EN_SHIFT                    7
 
 /* PLL :: anaPllControl :: PllForceDone [06:06] */
 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_MASK                        0x0040
 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_ALIGN                       0
 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_BITS                        1
 #define PLL_ANAPLLCONTROL_PLLFORCEDONE_SHIFT                       6
 
 /* PLL :: anaPllControl :: PllForcePass [05:05] */
 #define PLL_ANAPLLCONTROL_PLLFORCEPASS_MASK                        0x0020
 #define PLL_ANAPLLCONTROL_PLLFORCEPASS_ALIGN                       0
 #define PLL_ANAPLLCONTROL_PLLFORCEPASS_BITS                        1
 #define PLL_ANAPLLCONTROL_PLLFORCEPASS_SHIFT                       5
 
 /* PLL :: anaPllControl :: PllForceVcoDone_en [04:04] */
 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_MASK                  0x0010
 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_ALIGN                 0
 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_BITS                  1
 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_SHIFT                 4
 
 /* PLL :: anaPllControl :: PllForceVcoDone [03:03] */
 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_MASK                     0x0008
 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_ALIGN                    0
 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_BITS                     1
 #define PLL_ANAPLLCONTROL_PLLFORCEVCODONE_SHIFT                    3
 
 /* PLL :: anaPllControl :: PllForceVcoPass_en [02:02] */
 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_MASK                  0x0004
 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_ALIGN                 0
 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_BITS                  1
 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_SHIFT                 2
 
 /* PLL :: anaPllControl :: PllForceVcoPass [01:01] */
 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_MASK                     0x0002
 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_ALIGN                    0
 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_BITS                     1
 #define PLL_ANAPLLCONTROL_PLLFORCEVCOPASS_SHIFT                    1
 
 /* PLL :: anaPllControl :: PllForcePllLock [00:00] */
 #define PLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_MASK                     0x0001
 #define PLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_ALIGN                    0
 #define PLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_BITS                     1
 #define PLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_SHIFT                    0
 
 
 /****************************************************************************
  * PLL :: anaPllTimer1
  */
 /* PLL :: anaPllTimer1 :: VcoStepTime [15:08] */
 #define PLL_ANAPLLTIMER1_VCOSTEPTIME_MASK                          0xff00
 #define PLL_ANAPLLTIMER1_VCOSTEPTIME_ALIGN                         0
 #define PLL_ANAPLLTIMER1_VCOSTEPTIME_BITS                          8
 #define PLL_ANAPLLTIMER1_VCOSTEPTIME_SHIFT                         8
 
 /* PLL :: anaPllTimer1 :: VcoStartTime [07:00] */
 #define PLL_ANAPLLTIMER1_VCOSTARTTIME_MASK                         0x00ff
 #define PLL_ANAPLLTIMER1_VCOSTARTTIME_ALIGN                        0
 #define PLL_ANAPLLTIMER1_VCOSTARTTIME_BITS                         8
 #define PLL_ANAPLLTIMER1_VCOSTARTTIME_SHIFT                        0
 
 
 /****************************************************************************
  * PLL :: anaPllTimer2
  */
 /* PLL :: anaPllTimer2 :: reserved0 [15:15] */
 #define PLL_ANAPLLTIMER2_RESERVED0_MASK                            0x8000
 #define PLL_ANAPLLTIMER2_RESERVED0_ALIGN                           0
 #define PLL_ANAPLLTIMER2_RESERVED0_BITS                            1
 #define PLL_ANAPLLTIMER2_RESERVED0_SHIFT                           15
 
 /* PLL :: anaPllTimer2 :: lfckSingleStep_en [14:14] */
 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_MASK                    0x4000
 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_ALIGN                   0
 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_BITS                    1
 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_SHIFT                   14
 
 /* PLL :: anaPllTimer2 :: lfckSingleStep [13:13] */
 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_MASK                       0x2000
 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_ALIGN                      0
 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_BITS                       1
 #define PLL_ANAPLLTIMER2_LFCKSINGLESTEP_SHIFT                      13
 
 /* PLL :: anaPllTimer2 :: testMuxSel [12:08] */
 #define PLL_ANAPLLTIMER2_TESTMUXSEL_MASK                           0x1f00
 #define PLL_ANAPLLTIMER2_TESTMUXSEL_ALIGN                          0
 #define PLL_ANAPLLTIMER2_TESTMUXSEL_BITS                           5
 #define PLL_ANAPLLTIMER2_TESTMUXSEL_SHIFT                          8
 
 /* PLL :: anaPllTimer2 :: retryTime [07:00] */
 #define PLL_ANAPLLTIMER2_RETRYTIME_MASK                            0x00ff
 #define PLL_ANAPLLTIMER2_RETRYTIME_ALIGN                           0
 #define PLL_ANAPLLTIMER2_RETRYTIME_BITS                            8
 #define PLL_ANAPLLTIMER2_RETRYTIME_SHIFT                           0
 
 
 /****************************************************************************
  * PLL :: anaPllTimer3
  */
 /* PLL :: anaPllTimer3 :: reserved0 [15:08] */
 #define PLL_ANAPLLTIMER3_RESERVED0_MASK                            0xff00
 #define PLL_ANAPLLTIMER3_RESERVED0_ALIGN                           0
 #define PLL_ANAPLLTIMER3_RESERVED0_BITS                            8
 #define PLL_ANAPLLTIMER3_RESERVED0_SHIFT                           8
 
 /* PLL :: anaPllTimer3 :: freqDetTime [07:00] */
 #define PLL_ANAPLLTIMER3_FREQDETTIME_MASK                          0x00ff
 #define PLL_ANAPLLTIMER3_FREQDETTIME_ALIGN                         0
 #define PLL_ANAPLLTIMER3_FREQDETTIME_BITS                          8
 #define PLL_ANAPLLTIMER3_FREQDETTIME_SHIFT                         0
 
 
 /****************************************************************************
  * PLL :: anaCapControl
  */
 /* PLL :: anaCapControl :: vcoSeqCYA [15:15] */
 #define PLL_ANACAPCONTROL_VCOSEQCYA_MASK                           0x8000
 #define PLL_ANACAPCONTROL_VCOSEQCYA_ALIGN                          0
 #define PLL_ANACAPCONTROL_VCOSEQCYA_BITS                           1
 #define PLL_ANACAPCONTROL_VCOSEQCYA_SHIFT                          15
 
 /* PLL :: anaCapControl :: vcoRestart [14:14] */
 #define PLL_ANACAPCONTROL_VCORESTART_MASK                          0x4000
 #define PLL_ANACAPCONTROL_VCORESTART_ALIGN                         0
 #define PLL_ANACAPCONTROL_VCORESTART_BITS                          1
 #define PLL_ANACAPCONTROL_VCORESTART_SHIFT                         14
 
 /* PLL :: anaCapControl :: vcoSelectM_en [13:13] */
 #define PLL_ANACAPCONTROL_VCOSELECTM_EN_MASK                       0x2000
 #define PLL_ANACAPCONTROL_VCOSELECTM_EN_ALIGN                      0
 #define PLL_ANACAPCONTROL_VCOSELECTM_EN_BITS                       1
 #define PLL_ANACAPCONTROL_VCOSELECTM_EN_SHIFT                      13
 
 /* PLL :: anaCapControl :: vcoForceSlowdn_en [12:12] */
 #define PLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_MASK                   0x1000
 #define PLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_ALIGN                  0
 #define PLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_BITS                   1
 #define PLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_SHIFT                  12
 
 /* PLL :: anaCapControl :: vcoRstEn [11:11] */
 #define PLL_ANACAPCONTROL_VCORSTEN_MASK                            0x0800
 #define PLL_ANACAPCONTROL_VCORSTEN_ALIGN                           0
 #define PLL_ANACAPCONTROL_VCORSTEN_BITS                            1
 #define PLL_ANACAPCONTROL_VCORSTEN_SHIFT                           11
 
 /* PLL :: anaCapControl :: vcoCntMask_en [10:10] */
 #define PLL_ANACAPCONTROL_VCOCNTMASK_EN_MASK                       0x0400
 #define PLL_ANACAPCONTROL_VCOCNTMASK_EN_ALIGN                      0
 #define PLL_ANACAPCONTROL_VCOCNTMASK_EN_BITS                       1
 #define PLL_ANACAPCONTROL_VCOCNTMASK_EN_SHIFT                      10
 
 /* PLL :: anaCapControl :: slowdn_xor [09:09] */
 #define PLL_ANACAPCONTROL_SLOWDN_XOR_MASK                          0x0200
 #define PLL_ANACAPCONTROL_SLOWDN_XOR_ALIGN                         0
 #define PLL_ANACAPCONTROL_SLOWDN_XOR_BITS                          1
 #define PLL_ANACAPCONTROL_SLOWDN_XOR_SHIFT                         9
 
 /* PLL :: anaCapControl :: vcoForceSlowDown [08:08] */
 #define PLL_ANACAPCONTROL_VCOFORCESLOWDOWN_MASK                    0x0100
 #define PLL_ANACAPCONTROL_VCOFORCESLOWDOWN_ALIGN                   0
 #define PLL_ANACAPCONTROL_VCOFORCESLOWDOWN_BITS                    1
 #define PLL_ANACAPCONTROL_VCOFORCESLOWDOWN_SHIFT                   8
 
 /* PLL :: anaCapControl :: vcoSelectM [07:00] */
 #define PLL_ANACAPCONTROL_VCOSELECTM_MASK                          0x00ff
 #define PLL_ANACAPCONTROL_VCOSELECTM_ALIGN                         0
 #define PLL_ANACAPCONTROL_VCOSELECTM_BITS                          8
 #define PLL_ANACAPCONTROL_VCOSELECTM_SHIFT                         0
 
 
 /****************************************************************************
  * PLL :: anaFreqDetCntr
  */
 /* PLL :: anaFreqDetCntr :: resolution [15:08] */
 #define PLL_ANAFREQDETCNTR_RESOLUTION_MASK                         0xff00
 #define PLL_ANAFREQDETCNTR_RESOLUTION_ALIGN                        0
 #define PLL_ANAFREQDETCNTR_RESOLUTION_BITS                         8
 #define PLL_ANAFREQDETCNTR_RESOLUTION_SHIFT                        8
 
 /* PLL :: anaFreqDetCntr :: window [07:00] */
 #define PLL_ANAFREQDETCNTR_WINDOW_MASK                             0x00ff
 #define PLL_ANAFREQDETCNTR_WINDOW_ALIGN                            0
 #define PLL_ANAFREQDETCNTR_WINDOW_BITS                             8
 #define PLL_ANAFREQDETCNTR_WINDOW_SHIFT                            0
 
 
 /****************************************************************************
  * PLL :: anaPllAStatus1
  */
 /* PLL :: anaPllAStatus1 :: kvh [15:14] */
 #define PLL_ANAPLLASTATUS1_KVH_MASK                                0xc000
 #define PLL_ANAPLLASTATUS1_KVH_ALIGN                               0
 #define PLL_ANAPLLASTATUS1_KVH_BITS                                2
 #define PLL_ANAPLLASTATUS1_KVH_SHIFT                               14
 
 /* PLL :: anaPllAStatus1 :: pll_range [13:06] */
 #define PLL_ANAPLLASTATUS1_PLL_RANGE_MASK                          0x3fc0
 #define PLL_ANAPLLASTATUS1_PLL_RANGE_ALIGN                         0
 #define PLL_ANAPLLASTATUS1_PLL_RANGE_BITS                          8
 #define PLL_ANAPLLASTATUS1_PLL_RANGE_SHIFT                         6
 
 /* PLL :: anaPllAStatus1 :: pll_low [05:05] */
 #define PLL_ANAPLLASTATUS1_PLL_LOW_MASK                            0x0020
 #define PLL_ANAPLLASTATUS1_PLL_LOW_ALIGN                           0
 #define PLL_ANAPLLASTATUS1_PLL_LOW_BITS                            1
 #define PLL_ANAPLLASTATUS1_PLL_LOW_SHIFT                           5
 
 /* PLL :: anaPllAStatus1 :: reserved0 [04:04] */
 #define PLL_ANAPLLASTATUS1_RESERVED0_MASK                          0x0010
 #define PLL_ANAPLLASTATUS1_RESERVED0_ALIGN                         0
 #define PLL_ANAPLLASTATUS1_RESERVED0_BITS                          1
 #define PLL_ANAPLLASTATUS1_RESERVED0_SHIFT                         4
 
 /* PLL :: anaPllAStatus1 :: pll_Ndiv [03:00] */
 #define PLL_ANAPLLASTATUS1_PLL_NDIV_MASK                           0x000f
 #define PLL_ANAPLLASTATUS1_PLL_NDIV_ALIGN                          0
 #define PLL_ANAPLLASTATUS1_PLL_NDIV_BITS                           4
 #define PLL_ANAPLLASTATUS1_PLL_NDIV_SHIFT                          0
 
 
 /****************************************************************************
  * PLL :: anaPllAControl0
  */
 /* PLL :: anaPllAControl0 :: refl_clkgen [15:15] */
 #define PLL_ANAPLLACONTROL0_REFL_CLKGEN_MASK                       0x8000
 #define PLL_ANAPLLACONTROL0_REFL_CLKGEN_ALIGN                      0
 #define PLL_ANAPLLACONTROL0_REFL_CLKGEN_BITS                       1
 #define PLL_ANAPLLACONTROL0_REFL_CLKGEN_SHIFT                      15
 
 /* PLL :: anaPllAControl0 :: iclkidrv1 [14:12] */
 #define PLL_ANAPLLACONTROL0_ICLKIDRV1_MASK                         0x7000
 #define PLL_ANAPLLACONTROL0_ICLKIDRV1_ALIGN                        0
 #define PLL_ANAPLLACONTROL0_ICLKIDRV1_BITS                         3
 #define PLL_ANAPLLACONTROL0_ICLKIDRV1_SHIFT                        12
 
 /* PLL :: anaPllAControl0 :: iclkodrv1 [11:09] */
 #define PLL_ANAPLLACONTROL0_ICLKODRV1_MASK                         0x0e00
 #define PLL_ANAPLLACONTROL0_ICLKODRV1_ALIGN                        0
 #define PLL_ANAPLLACONTROL0_ICLKODRV1_BITS                         3
 #define PLL_ANAPLLACONTROL0_ICLKODRV1_SHIFT                        9
 
 /* PLL :: anaPllAControl0 :: iclkodrv2 [08:06] */
 #define PLL_ANAPLLACONTROL0_ICLKODRV2_MASK                         0x01c0
 #define PLL_ANAPLLACONTROL0_ICLKODRV2_ALIGN                        0
 #define PLL_ANAPLLACONTROL0_ICLKODRV2_BITS                         3
 #define PLL_ANAPLLACONTROL0_ICLKODRV2_SHIFT                        6
 
 /* PLL :: anaPllAControl0 :: iclkdiv2 [05:03] */
 #define PLL_ANAPLLACONTROL0_ICLKDIV2_MASK                          0x0038
 #define PLL_ANAPLLACONTROL0_ICLKDIV2_ALIGN                         0
 #define PLL_ANAPLLACONTROL0_ICLKDIV2_BITS                          3
 #define PLL_ANAPLLACONTROL0_ICLKDIV2_SHIFT                         3
 
 /* PLL :: anaPllAControl0 :: reserved0 [02:02] */
 #define PLL_ANAPLLACONTROL0_RESERVED0_MASK                         0x0004
 #define PLL_ANAPLLACONTROL0_RESERVED0_ALIGN                        0
 #define PLL_ANAPLLACONTROL0_RESERVED0_BITS                         1
 #define PLL_ANAPLLACONTROL0_RESERVED0_SHIFT                        2
 
 /* PLL :: anaPllAControl0 :: vddr_bgb [01:01] */
 #define PLL_ANAPLLACONTROL0_VDDR_BGB_MASK                          0x0002
 #define PLL_ANAPLLACONTROL0_VDDR_BGB_ALIGN                         0
 #define PLL_ANAPLLACONTROL0_VDDR_BGB_BITS                          1
 #define PLL_ANAPLLACONTROL0_VDDR_BGB_SHIFT                         1
 
 /* PLL :: anaPllAControl0 :: amp_ctrl [00:00] */
 #define PLL_ANAPLLACONTROL0_AMP_CTRL_MASK                          0x0001
 #define PLL_ANAPLLACONTROL0_AMP_CTRL_ALIGN                         0
 #define PLL_ANAPLLACONTROL0_AMP_CTRL_BITS                          1
 #define PLL_ANAPLLACONTROL0_AMP_CTRL_SHIFT                         0
 
 
 /****************************************************************************
  * PLL :: anaPllAControl1
  */
 /* PLL :: anaPllAControl1 :: enable_ftune [15:15] */
 #define PLL_ANAPLLACONTROL1_ENABLE_FTUNE_MASK                      0x8000
 #define PLL_ANAPLLACONTROL1_ENABLE_FTUNE_ALIGN                     0
 #define PLL_ANAPLLACONTROL1_ENABLE_FTUNE_BITS                      1
 #define PLL_ANAPLLACONTROL1_ENABLE_FTUNE_SHIFT                     15
 
 /* PLL :: anaPllAControl1 :: pll_reset [14:14] */
 #define PLL_ANAPLLACONTROL1_PLL_RESET_MASK                         0x4000
 #define PLL_ANAPLLACONTROL1_PLL_RESET_ALIGN                        0
 #define PLL_ANAPLLACONTROL1_PLL_RESET_BITS                         1
 #define PLL_ANAPLLACONTROL1_PLL_RESET_SHIFT                        14
 
 /* PLL :: anaPllAControl1 :: reserved0 [13:11] */
 #define PLL_ANAPLLACONTROL1_RESERVED0_MASK                         0x3800
 #define PLL_ANAPLLACONTROL1_RESERVED0_ALIGN                        0
 #define PLL_ANAPLLACONTROL1_RESERVED0_BITS                         3
 #define PLL_ANAPLLACONTROL1_RESERVED0_SHIFT                        11
 
 /* PLL :: anaPllAControl1 :: iclkibuf4 [10:08] */
 #define PLL_ANAPLLACONTROL1_ICLKIBUF4_MASK                         0x0700
 #define PLL_ANAPLLACONTROL1_ICLKIBUF4_ALIGN                        0
 #define PLL_ANAPLLACONTROL1_ICLKIBUF4_BITS                         3
 #define PLL_ANAPLLACONTROL1_ICLKIBUF4_SHIFT                        8
 
 /* PLL :: anaPllAControl1 :: ibias_all [07:05] */
 #define PLL_ANAPLLACONTROL1_IBIAS_ALL_MASK                         0x00e0
 #define PLL_ANAPLLACONTROL1_IBIAS_ALL_ALIGN                        0
 #define PLL_ANAPLLACONTROL1_IBIAS_ALL_BITS                         3
 #define PLL_ANAPLLACONTROL1_IBIAS_ALL_SHIFT                        5
 
 /* PLL :: anaPllAControl1 :: refout_en [04:04] */
 #define PLL_ANAPLLACONTROL1_REFOUT_EN_MASK                         0x0010
 #define PLL_ANAPLLACONTROL1_REFOUT_EN_ALIGN                        0
 #define PLL_ANAPLLACONTROL1_REFOUT_EN_BITS                         1
 #define PLL_ANAPLLACONTROL1_REFOUT_EN_SHIFT                        4
 
 /* PLL :: anaPllAControl1 :: refin_en [03:03] */
 #define PLL_ANAPLLACONTROL1_REFIN_EN_MASK                          0x0008
 #define PLL_ANAPLLACONTROL1_REFIN_EN_ALIGN                         0
 #define PLL_ANAPLLACONTROL1_REFIN_EN_BITS                          1
 #define PLL_ANAPLLACONTROL1_REFIN_EN_SHIFT                         3
 
 /* PLL :: anaPllAControl1 :: reserved1 [02:01] */
 #define PLL_ANAPLLACONTROL1_RESERVED1_MASK                         0x0006
 #define PLL_ANAPLLACONTROL1_RESERVED1_ALIGN                        0
 #define PLL_ANAPLLACONTROL1_RESERVED1_BITS                         2
 #define PLL_ANAPLLACONTROL1_RESERVED1_SHIFT                        1
 
 /* PLL :: anaPllAControl1 :: refh_clkgen [00:00] */
 #define PLL_ANAPLLACONTROL1_REFH_CLKGEN_MASK                       0x0001
 #define PLL_ANAPLLACONTROL1_REFH_CLKGEN_ALIGN                      0
 #define PLL_ANAPLLACONTROL1_REFH_CLKGEN_BITS                       1
 #define PLL_ANAPLLACONTROL1_REFH_CLKGEN_SHIFT                      0
 
 
 /****************************************************************************
  * PLL :: anaPllAControl2
  */
 /* PLL :: anaPllAControl2 :: ick2 [15:15] */
 #define PLL_ANAPLLACONTROL2_ICK2_MASK                              0x8000
 #define PLL_ANAPLLACONTROL2_ICK2_ALIGN                             0
 #define PLL_ANAPLLACONTROL2_ICK2_BITS                              1
 #define PLL_ANAPLLACONTROL2_ICK2_SHIFT                             15
 
 /* PLL :: anaPllAControl2 :: ick0 [14:14] */
 #define PLL_ANAPLLACONTROL2_ICK0_MASK                              0x4000
 #define PLL_ANAPLLACONTROL2_ICK0_ALIGN                             0
 #define PLL_ANAPLLACONTROL2_ICK0_BITS                              1
 #define PLL_ANAPLLACONTROL2_ICK0_SHIFT                             14
 
 /* PLL :: anaPllAControl2 :: ick1 [13:13] */
 #define PLL_ANAPLLACONTROL2_ICK1_MASK                              0x2000
 #define PLL_ANAPLLACONTROL2_ICK1_ALIGN                             0
 #define PLL_ANAPLLACONTROL2_ICK1_BITS                              1
 #define PLL_ANAPLLACONTROL2_ICK1_SHIFT                             13
 
 /* PLL :: anaPllAControl2 :: icp2 [12:12] */
 #define PLL_ANAPLLACONTROL2_ICP2_MASK                              0x1000
 #define PLL_ANAPLLACONTROL2_ICP2_ALIGN                             0
 #define PLL_ANAPLLACONTROL2_ICP2_BITS                              1
 #define PLL_ANAPLLACONTROL2_ICP2_SHIFT                             12
 
 /* PLL :: anaPllAControl2 :: icp0 [11:11] */
 #define PLL_ANAPLLACONTROL2_ICP0_MASK                              0x0800
 #define PLL_ANAPLLACONTROL2_ICP0_ALIGN                             0
 #define PLL_ANAPLLACONTROL2_ICP0_BITS                              1
 #define PLL_ANAPLLACONTROL2_ICP0_SHIFT                             11
 
 /* PLL :: anaPllAControl2 :: icp1 [10:10] */
 #define PLL_ANAPLLACONTROL2_ICP1_MASK                              0x0400
 #define PLL_ANAPLLACONTROL2_ICP1_ALIGN                             0
 #define PLL_ANAPLLACONTROL2_ICP1_BITS                              1
 #define PLL_ANAPLLACONTROL2_ICP1_SHIFT                             10
 
 /* PLL :: anaPllAControl2 :: ibmax [09:09] */
 #define PLL_ANAPLLACONTROL2_IBMAX_MASK                             0x0200
 #define PLL_ANAPLLACONTROL2_IBMAX_ALIGN                            0
 #define PLL_ANAPLLACONTROL2_IBMAX_BITS                             1
 #define PLL_ANAPLLACONTROL2_IBMAX_SHIFT                            9
 
 /* PLL :: anaPllAControl2 :: ibmode [08:08] */
 #define PLL_ANAPLLACONTROL2_IBMODE_MASK                            0x0100
 #define PLL_ANAPLLACONTROL2_IBMODE_ALIGN                           0
 #define PLL_ANAPLLACONTROL2_IBMODE_BITS                            1
 #define PLL_ANAPLLACONTROL2_IBMODE_SHIFT                           8
 
 /* PLL :: anaPllAControl2 :: ibmin [07:07] */
 #define PLL_ANAPLLACONTROL2_IBMIN_MASK                             0x0080
 #define PLL_ANAPLLACONTROL2_IBMIN_ALIGN                            0
 #define PLL_ANAPLLACONTROL2_IBMIN_BITS                             1
 #define PLL_ANAPLLACONTROL2_IBMIN_SHIFT                            7
 
 /* PLL :: anaPllAControl2 :: refh_pll [06:06] */
 #define PLL_ANAPLLACONTROL2_REFH_PLL_MASK                          0x0040
 #define PLL_ANAPLLACONTROL2_REFH_PLL_ALIGN                         0
 #define PLL_ANAPLLACONTROL2_REFH_PLL_BITS                          1
 #define PLL_ANAPLLACONTROL2_REFH_PLL_SHIFT                         6
 
 /* PLL :: anaPllAControl2 :: refl_pll [05:05] */
 #define PLL_ANAPLLACONTROL2_REFL_PLL_MASK                          0x0020
 #define PLL_ANAPLLACONTROL2_REFL_PLL_ALIGN                         0
 #define PLL_ANAPLLACONTROL2_REFL_PLL_BITS                          1
 #define PLL_ANAPLLACONTROL2_REFL_PLL_SHIFT                         5
 
 /* PLL :: anaPllAControl2 :: iqp [04:01] */
 #define PLL_ANAPLLACONTROL2_IQP_MASK                               0x001e
 #define PLL_ANAPLLACONTROL2_IQP_ALIGN                              0
 #define PLL_ANAPLLACONTROL2_IQP_BITS                               4
 #define PLL_ANAPLLACONTROL2_IQP_SHIFT                              1
 #define PLL_ANAPLLACONTROL2_IQP_i50uA                              0
 #define PLL_ANAPLLACONTROL2_IQP_i100uA                             1
 #define PLL_ANAPLLACONTROL2_IQP_i150uA                             2
 #define PLL_ANAPLLACONTROL2_IQP_i200uA                             3
 #define PLL_ANAPLLACONTROL2_IQP_i250uA                             4
 #define PLL_ANAPLLACONTROL2_IQP_i300uA                             5
 #define PLL_ANAPLLACONTROL2_IQP_i350uA                             6
 #define PLL_ANAPLLACONTROL2_IQP_i400uA                             7
 #define PLL_ANAPLLACONTROL2_IQP_i450uA                             8
 #define PLL_ANAPLLACONTROL2_IQP_i500uA                             9
 #define PLL_ANAPLLACONTROL2_IQP_i550uA                             10
 #define PLL_ANAPLLACONTROL2_IQP_i600uA                             11
 #define PLL_ANAPLLACONTROL2_IQP_i650uA                             12
 #define PLL_ANAPLLACONTROL2_IQP_i700uA                             13
 #define PLL_ANAPLLACONTROL2_IQP_i750uA                             14
 #define PLL_ANAPLLACONTROL2_IQP_i800uA                             15
 
 /* PLL :: anaPllAControl2 :: en_HRz [00:00] */
 #define PLL_ANAPLLACONTROL2_EN_HRZ_MASK                            0x0001
 #define PLL_ANAPLLACONTROL2_EN_HRZ_ALIGN                           0
 #define PLL_ANAPLLACONTROL2_EN_HRZ_BITS                            1
 #define PLL_ANAPLLACONTROL2_EN_HRZ_SHIFT                           0
 
 
 /****************************************************************************
  * PLL :: anaPllAControl3
  */
 /* PLL :: anaPllAControl3 :: test_rx [15:15] */
 #define PLL_ANAPLLACONTROL3_TEST_RX_MASK                           0x8000
 #define PLL_ANAPLLACONTROL3_TEST_RX_ALIGN                          0
 #define PLL_ANAPLLACONTROL3_TEST_RX_BITS                           1
 #define PLL_ANAPLLACONTROL3_TEST_RX_SHIFT                          15
 
 /* PLL :: anaPllAControl3 :: test_pll [14:14] */
 #define PLL_ANAPLLACONTROL3_TEST_PLL_MASK                          0x4000
 #define PLL_ANAPLLACONTROL3_TEST_PLL_ALIGN                         0
 #define PLL_ANAPLLACONTROL3_TEST_PLL_BITS                          1
 #define PLL_ANAPLLACONTROL3_TEST_PLL_SHIFT                         14
 
 /* PLL :: anaPllAControl3 :: test_vc [13:13] */
 #define PLL_ANAPLLACONTROL3_TEST_VC_MASK                           0x2000
 #define PLL_ANAPLLACONTROL3_TEST_VC_ALIGN                          0
 #define PLL_ANAPLLACONTROL3_TEST_VC_BITS                           1
 #define PLL_ANAPLLACONTROL3_TEST_VC_SHIFT                          13
 
 /* PLL :: anaPllAControl3 :: test_vref [12:12] */
 #define PLL_ANAPLLACONTROL3_TEST_VREF_MASK                         0x1000
 #define PLL_ANAPLLACONTROL3_TEST_VREF_ALIGN                        0
 #define PLL_ANAPLLACONTROL3_TEST_VREF_BITS                         1
 #define PLL_ANAPLLACONTROL3_TEST_VREF_SHIFT                        12
 
 /* PLL :: anaPllAControl3 :: iop2 [11:11] */
 #define PLL_ANAPLLACONTROL3_IOP2_MASK                              0x0800
 #define PLL_ANAPLLACONTROL3_IOP2_ALIGN                             0
 #define PLL_ANAPLLACONTROL3_IOP2_BITS                              1
 #define PLL_ANAPLLACONTROL3_IOP2_SHIFT                             11
 
 /* PLL :: anaPllAControl3 :: iop0 [10:10] */
 #define PLL_ANAPLLACONTROL3_IOP0_MASK                              0x0400
 #define PLL_ANAPLLACONTROL3_IOP0_ALIGN                             0
 #define PLL_ANAPLLACONTROL3_IOP0_BITS                              1
 #define PLL_ANAPLLACONTROL3_IOP0_SHIFT                             10
 
 /* PLL :: anaPllAControl3 :: iop1 [09:09] */
 #define PLL_ANAPLLACONTROL3_IOP1_MASK                              0x0200
 #define PLL_ANAPLLACONTROL3_IOP1_ALIGN                             0
 #define PLL_ANAPLLACONTROL3_IOP1_BITS                              1
 #define PLL_ANAPLLACONTROL3_IOP1_SHIFT                             9
 
 /* PLL :: anaPllAControl3 :: icomp2 [08:08] */
 #define PLL_ANAPLLACONTROL3_ICOMP2_MASK                            0x0100
 #define PLL_ANAPLLACONTROL3_ICOMP2_ALIGN                           0
 #define PLL_ANAPLLACONTROL3_ICOMP2_BITS                            1
 #define PLL_ANAPLLACONTROL3_ICOMP2_SHIFT                           8
 
 /* PLL :: anaPllAControl3 :: icomp0 [07:07] */
 #define PLL_ANAPLLACONTROL3_ICOMP0_MASK                            0x0080
 #define PLL_ANAPLLACONTROL3_ICOMP0_ALIGN                           0
 #define PLL_ANAPLLACONTROL3_ICOMP0_BITS                            1
 #define PLL_ANAPLLACONTROL3_ICOMP0_SHIFT                           7
 
 /* PLL :: anaPllAControl3 :: icomp1 [06:06] */
 #define PLL_ANAPLLACONTROL3_ICOMP1_MASK                            0x0040
 #define PLL_ANAPLLACONTROL3_ICOMP1_ALIGN                           0
 #define PLL_ANAPLLACONTROL3_ICOMP1_BITS                            1
 #define PLL_ANAPLLACONTROL3_ICOMP1_SHIFT                           6
 
 /* PLL :: anaPllAControl3 :: icml2 [05:05] */
 #define PLL_ANAPLLACONTROL3_ICML2_MASK                             0x0020
 #define PLL_ANAPLLACONTROL3_ICML2_ALIGN                            0
 #define PLL_ANAPLLACONTROL3_ICML2_BITS                             1
 #define PLL_ANAPLLACONTROL3_ICML2_SHIFT                            5
 
 /* PLL :: anaPllAControl3 :: icml0 [04:04] */
 #define PLL_ANAPLLACONTROL3_ICML0_MASK                             0x0010
 #define PLL_ANAPLLACONTROL3_ICML0_ALIGN                            0
 #define PLL_ANAPLLACONTROL3_ICML0_BITS                             1
 #define PLL_ANAPLLACONTROL3_ICML0_SHIFT                            4
 
 /* PLL :: anaPllAControl3 :: icml1 [03:03] */
 #define PLL_ANAPLLACONTROL3_ICML1_MASK                             0x0008
 #define PLL_ANAPLLACONTROL3_ICML1_ALIGN                            0
 #define PLL_ANAPLLACONTROL3_ICML1_BITS                             1
 #define PLL_ANAPLLACONTROL3_ICML1_SHIFT                            3
 
 /* PLL :: anaPllAControl3 :: i10Gbuf2 [02:02] */
 #define PLL_ANAPLLACONTROL3_I10GBUF2_MASK                          0x0004
 #define PLL_ANAPLLACONTROL3_I10GBUF2_ALIGN                         0
 #define PLL_ANAPLLACONTROL3_I10GBUF2_BITS                          1
 #define PLL_ANAPLLACONTROL3_I10GBUF2_SHIFT                         2
 
 /* PLL :: anaPllAControl3 :: i10Gbuf0 [01:01] */
 #define PLL_ANAPLLACONTROL3_I10GBUF0_MASK                          0x0002
 #define PLL_ANAPLLACONTROL3_I10GBUF0_ALIGN                         0
 #define PLL_ANAPLLACONTROL3_I10GBUF0_BITS                          1
 #define PLL_ANAPLLACONTROL3_I10GBUF0_SHIFT                         1
 
 /* PLL :: anaPllAControl3 :: i10Gbuf1 [00:00] */
 #define PLL_ANAPLLACONTROL3_I10GBUF1_MASK                          0x0001
 #define PLL_ANAPLLACONTROL3_I10GBUF1_ALIGN                         0
 #define PLL_ANAPLLACONTROL3_I10GBUF1_BITS                          1
 #define PLL_ANAPLLACONTROL3_I10GBUF1_SHIFT                         0
 
 
 /****************************************************************************
  * PLL :: anaPllAControl4
  */
 /* PLL :: anaPllAControl4 :: en40lp [15:15] */
 #define PLL_ANAPLLACONTROL4_EN40LP_MASK                            0x8000
 #define PLL_ANAPLLACONTROL4_EN40LP_ALIGN                           0
 #define PLL_ANAPLLACONTROL4_EN40LP_BITS                            1
 #define PLL_ANAPLLACONTROL4_EN40LP_SHIFT                           15
 
 /* PLL :: anaPllAControl4 :: VCO_Imax [14:14] */
 #define PLL_ANAPLLACONTROL4_VCO_IMAX_MASK                          0x4000
 #define PLL_ANAPLLACONTROL4_VCO_IMAX_ALIGN                         0
 #define PLL_ANAPLLACONTROL4_VCO_IMAX_BITS                          1
 #define PLL_ANAPLLACONTROL4_VCO_IMAX_SHIFT                         14
 
 /* PLL :: anaPllAControl4 :: kvh_force [13:12] */
 #define PLL_ANAPLLACONTROL4_KVH_FORCE_MASK                         0x3000
 #define PLL_ANAPLLACONTROL4_KVH_FORCE_ALIGN                        0
 #define PLL_ANAPLLACONTROL4_KVH_FORCE_BITS                         2
 #define PLL_ANAPLLACONTROL4_KVH_FORCE_SHIFT                        12
 
 /* PLL :: anaPllAControl4 :: vddr_bgb [11:11] */
 #define PLL_ANAPLLACONTROL4_VDDR_BGB_MASK                          0x0800
 #define PLL_ANAPLLACONTROL4_VDDR_BGB_ALIGN                         0
 #define PLL_ANAPLLACONTROL4_VDDR_BGB_BITS                          1
 #define PLL_ANAPLLACONTROL4_VDDR_BGB_SHIFT                         11
 
 /* PLL :: anaPllAControl4 :: comp_vth [10:10] */
 #define PLL_ANAPLLACONTROL4_COMP_VTH_MASK                          0x0400
 #define PLL_ANAPLLACONTROL4_COMP_VTH_ALIGN                         0
 #define PLL_ANAPLLACONTROL4_COMP_VTH_BITS                          1
 #define PLL_ANAPLLACONTROL4_COMP_VTH_SHIFT                         10
 
 /* PLL :: anaPllAControl4 :: pll2rx_clkbw [09:08] */
 #define PLL_ANAPLLACONTROL4_PLL2RX_CLKBW_MASK                      0x0300
 #define PLL_ANAPLLACONTROL4_PLL2RX_CLKBW_ALIGN                     0
 #define PLL_ANAPLLACONTROL4_PLL2RX_CLKBW_BITS                      2
 #define PLL_ANAPLLACONTROL4_PLL2RX_CLKBW_SHIFT                     8
 
 /* PLL :: anaPllAControl4 :: ctatadj [07:04] */
 #define PLL_ANAPLLACONTROL4_CTATADJ_MASK                           0x00f0
 #define PLL_ANAPLLACONTROL4_CTATADJ_ALIGN                          0
 #define PLL_ANAPLLACONTROL4_CTATADJ_BITS                           4
 #define PLL_ANAPLLACONTROL4_CTATADJ_SHIFT                          4
 
 /* PLL :: anaPllAControl4 :: ptatadj [03:00] */
 #define PLL_ANAPLLACONTROL4_PTATADJ_MASK                           0x000f
 #define PLL_ANAPLLACONTROL4_PTATADJ_ALIGN                          0
 #define PLL_ANAPLLACONTROL4_PTATADJ_BITS                           4
 #define PLL_ANAPLLACONTROL4_PTATADJ_SHIFT                          0
 
 
 /****************************************************************************
  * Warpcore_USER_Tx0
  */
 /****************************************************************************
  * Tx0 :: anaTxAStatus0
  */
 /* union - case txStatusSelect_equals_0 [15:00] */
 /* Tx0 :: anaTxAStatus0 :: reserved0 [15:07] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_MASK   0xff80
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_ALIGN  0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_BITS   9
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_SHIFT  7
 
 /* Tx0 :: anaTxAStatus0 :: txdisable_ln [06:06] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_MASK 0x0040
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_ALIGN 0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_BITS 1
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_SHIFT 6
 
 /* Tx0 :: anaTxAStatus0 :: txferr_stky [05:05] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_MASK 0x0020
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_ALIGN 0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_BITS 1
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_SHIFT 5
 
 /* Tx0 :: anaTxAStatus0 :: tbi_mode [04:04] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_MASK    0x0010
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_ALIGN   0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_BITS    1
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_SHIFT   4
 
 /* Tx0 :: anaTxAStatus0 :: tx_reset [03:03] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_MASK    0x0008
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_ALIGN   0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_BITS    1
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_SHIFT   3
 
 /* Tx0 :: anaTxAStatus0 :: tx_pwrdn [02:02] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_MASK    0x0004
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_ALIGN   0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_BITS    1
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_SHIFT   2
 
 /* Tx0 :: anaTxAStatus0 :: rltxferr_stky [01:01] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_MASK 0x0002
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_ALIGN 0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_BITS 1
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_SHIFT 1
 
 /* Tx0 :: anaTxAStatus0 :: txpll_lock [00:00] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_MASK  0x0001
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_ALIGN 0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_BITS  1
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_SHIFT 0
 
 
 /* union - case txStatusSelect_equals_1 [15:00] */
 /* Tx0 :: anaTxAStatus0 :: tx_sel_halfrate [15:15] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_MASK 0x8000
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_ALIGN 0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_BITS 1
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_SHIFT 15
 
 /* Tx0 :: anaTxAStatus0 :: tx_fir_tap_post [14:10] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_MASK 0x7c00
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_ALIGN 0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_BITS 5
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_SHIFT 10
 
 /* Tx0 :: anaTxAStatus0 :: tx_fir_tap_main [09:04] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_MASK 0x03f0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_ALIGN 0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_BITS 6
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_SHIFT 4
 
 /* Tx0 :: anaTxAStatus0 :: tx_fir_tap_pre [03:00] */
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_MASK 0x000f
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_ALIGN 0
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_BITS 4
 #define TX0_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_SHIFT 0
 
 
 
 /****************************************************************************
  * Tx0 :: anaTxAControl0
  */
 /* Tx0 :: anaTxAControl0 :: reserved0 [15:15] */
 #define TX0_ANATXACONTROL0_RESERVED0_MASK                          0x8000
 #define TX0_ANATXACONTROL0_RESERVED0_ALIGN                         0
 #define TX0_ANATXACONTROL0_RESERVED0_BITS                          1
 #define TX0_ANATXACONTROL0_RESERVED0_SHIFT                         15
 
 /* Tx0 :: anaTxAControl0 :: force_txclk [14:14] */
 #define TX0_ANATXACONTROL0_FORCE_TXCLK_MASK                        0x4000
 #define TX0_ANATXACONTROL0_FORCE_TXCLK_ALIGN                       0
 #define TX0_ANATXACONTROL0_FORCE_TXCLK_BITS                        1
 #define TX0_ANATXACONTROL0_FORCE_TXCLK_SHIFT                       14
 
 /* Tx0 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_MASK                      0x2000
 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN                     0
 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_BITS                      1
 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT                     13
 
 /* Tx0 :: anaTxAControl0 :: force_ext_frst_SM [12:12] */
 #define TX0_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK                  0x1000
 #define TX0_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN                 0
 #define TX0_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS                  1
 #define TX0_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT                 12
 
 /* Tx0 :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */
 #define TX0_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK                0x0800
 #define TX0_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN               0
 #define TX0_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS                1
 #define TX0_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT               11
 
 /* Tx0 :: anaTxAControl0 :: txck_dme_en_SM [10:10] */
 #define TX0_ANATXACONTROL0_TXCK_DME_EN_SM_MASK                     0x0400
 #define TX0_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN                    0
 #define TX0_ANATXACONTROL0_TXCK_DME_EN_SM_BITS                     1
 #define TX0_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT                    10
 
 /* Tx0 :: anaTxAControl0 :: gloopOutDis [09:09] */
 #define TX0_ANATXACONTROL0_GLOOPOUTDIS_MASK                        0x0200
 #define TX0_ANATXACONTROL0_GLOOPOUTDIS_ALIGN                       0
 #define TX0_ANATXACONTROL0_GLOOPOUTDIS_BITS                        1
 #define TX0_ANATXACONTROL0_GLOOPOUTDIS_SHIFT                       9
 
 /* Tx0 :: anaTxAControl0 :: prbs_en [08:08] */
 #define TX0_ANATXACONTROL0_PRBS_EN_MASK                            0x0100
 #define TX0_ANATXACONTROL0_PRBS_EN_ALIGN                           0
 #define TX0_ANATXACONTROL0_PRBS_EN_BITS                            1
 #define TX0_ANATXACONTROL0_PRBS_EN_SHIFT                           8
 
 /* Tx0 :: anaTxAControl0 :: pckt_en [07:07] */
 #define TX0_ANATXACONTROL0_PCKT_EN_MASK                            0x0080
 #define TX0_ANATXACONTROL0_PCKT_EN_ALIGN                           0
 #define TX0_ANATXACONTROL0_PCKT_EN_BITS                            1
 #define TX0_ANATXACONTROL0_PCKT_EN_SHIFT                           7
 
 /* Tx0 :: anaTxAControl0 :: pckt_strt [06:06] */
 #define TX0_ANATXACONTROL0_PCKT_STRT_MASK                          0x0040
 #define TX0_ANATXACONTROL0_PCKT_STRT_ALIGN                         0
 #define TX0_ANATXACONTROL0_PCKT_STRT_BITS                          1
 #define TX0_ANATXACONTROL0_PCKT_STRT_SHIFT                         6
 
 /* Tx0 :: anaTxAControl0 :: txpol_flip [05:05] */
 #define TX0_ANATXACONTROL0_TXPOL_FLIP_MASK                         0x0020
 #define TX0_ANATXACONTROL0_TXPOL_FLIP_ALIGN                        0
 #define TX0_ANATXACONTROL0_TXPOL_FLIP_BITS                         1
 #define TX0_ANATXACONTROL0_TXPOL_FLIP_SHIFT                        5
 
 /* Tx0 :: anaTxAControl0 :: rtbi_flip [04:04] */
 #define TX0_ANATXACONTROL0_RTBI_FLIP_MASK                          0x0010
 #define TX0_ANATXACONTROL0_RTBI_FLIP_ALIGN                         0
 #define TX0_ANATXACONTROL0_RTBI_FLIP_BITS                          1
 #define TX0_ANATXACONTROL0_RTBI_FLIP_SHIFT                         4
 
 /* Tx0 :: anaTxAControl0 :: eden_r [03:03] */
 #define TX0_ANATXACONTROL0_EDEN_R_MASK                             0x0008
 #define TX0_ANATXACONTROL0_EDEN_R_ALIGN                            0
 #define TX0_ANATXACONTROL0_EDEN_R_BITS                             1
 #define TX0_ANATXACONTROL0_EDEN_R_SHIFT                            3
 
 /* Tx0 :: anaTxAControl0 :: eden_force_r [02:02] */
 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_MASK                       0x0004
 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_ALIGN                      0
 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_BITS                       1
 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_SHIFT                      2
 
 /* Tx0 :: anaTxAControl0 :: txpat_en [01:01] */
 #define TX0_ANATXACONTROL0_TXPAT_EN_MASK                           0x0002
 #define TX0_ANATXACONTROL0_TXPAT_EN_ALIGN                          0
 #define TX0_ANATXACONTROL0_TXPAT_EN_BITS                           1
 #define TX0_ANATXACONTROL0_TXPAT_EN_SHIFT                          1
 
 /* Tx0 :: anaTxAControl0 :: tx_mdata_en [00:00] */
 #define TX0_ANATXACONTROL0_TX_MDATA_EN_MASK                        0x0001
 #define TX0_ANATXACONTROL0_TX_MDATA_EN_ALIGN                       0
 #define TX0_ANATXACONTROL0_TX_MDATA_EN_BITS                        1
 #define TX0_ANATXACONTROL0_TX_MDATA_EN_SHIFT                       0
 
 
 /****************************************************************************
  * Tx0 :: anaTxmdata0
  */
 /* Tx0 :: anaTxmdata0 :: txTestMuxSel [15:13] */
 #define TX0_ANATXMDATA0_TXTESTMUXSEL_MASK                          0xe000
 #define TX0_ANATXMDATA0_TXTESTMUXSEL_ALIGN                         0
 #define TX0_ANATXMDATA0_TXTESTMUXSEL_BITS                          3
 #define TX0_ANATXMDATA0_TXTESTMUXSEL_SHIFT                         13
 
 /* Tx0 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_MASK                         0x1c00
 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN                        0
 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_BITS                         3
 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT                        10
 
 /* Tx0 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_MASK                        0x03ff
 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN                       0
 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_BITS                        10
 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT                       0
 
 
 /****************************************************************************
  * Tx0 :: anaTxmdata1
  */
 /* Tx0 :: anaTxmdata1 :: txStatusSelect [15:14] */
 #define TX0_ANATXMDATA1_TXSTATUSSELECT_MASK                        0xc000
 #define TX0_ANATXMDATA1_TXSTATUSSELECT_ALIGN                       0
 #define TX0_ANATXMDATA1_TXSTATUSSELECT_BITS                        2
 #define TX0_ANATXMDATA1_TXSTATUSSELECT_SHIFT                       14
 
 /* Tx0 :: anaTxmdata1 :: reserved0 [13:10] */
 #define TX0_ANATXMDATA1_RESERVED0_MASK                             0x3c00
 #define TX0_ANATXMDATA1_RESERVED0_ALIGN                            0
 #define TX0_ANATXMDATA1_RESERVED0_BITS                             4
 #define TX0_ANATXMDATA1_RESERVED0_SHIFT                            10
 
 /* Tx0 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_MASK                        0x03ff
 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN                       0
 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_BITS                        10
 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT                       0
 
 
 /****************************************************************************
  * Tx0 :: anaTxAStatus1
  */
 /* Tx0 :: anaTxAStatus1 :: tx_id [15:14] */
 #define TX0_ANATXASTATUS1_TX_ID_MASK                               0xc000
 #define TX0_ANATXASTATUS1_TX_ID_ALIGN                              0
 #define TX0_ANATXASTATUS1_TX_ID_BITS                               2
 #define TX0_ANATXASTATUS1_TX_ID_SHIFT                              14
 
 /* Tx0 :: anaTxAStatus1 :: reserved0 [13:08] */
 #define TX0_ANATXASTATUS1_RESERVED0_MASK                           0x3f00
 #define TX0_ANATXASTATUS1_RESERVED0_ALIGN                          0
 #define TX0_ANATXASTATUS1_RESERVED0_BITS                           6
 #define TX0_ANATXASTATUS1_RESERVED0_SHIFT                          8
 
 /* Tx0 :: anaTxAStatus1 :: version_id [07:04] */
 #define TX0_ANATXASTATUS1_VERSION_ID_MASK                          0x00f0
 #define TX0_ANATXASTATUS1_VERSION_ID_ALIGN                         0
 #define TX0_ANATXASTATUS1_VERSION_ID_BITS                          4
 #define TX0_ANATXASTATUS1_VERSION_ID_SHIFT                         4
 
 /* Tx0 :: anaTxAStatus1 :: reserved1 [03:00] */
 #define TX0_ANATXASTATUS1_RESERVED1_MASK                           0x000f
 #define TX0_ANATXASTATUS1_RESERVED1_ALIGN                          0
 #define TX0_ANATXASTATUS1_RESERVED1_BITS                           4
 #define TX0_ANATXASTATUS1_RESERVED1_SHIFT                          0
 
 
 /****************************************************************************
  * Tx0 :: anaTxAControl1
  */
 /* Tx0 :: anaTxAControl1 :: ipredrv [15:13] */
 #define TX0_ANATXACONTROL1_IPREDRV_MASK                            0xe000
 #define TX0_ANATXACONTROL1_IPREDRV_ALIGN                           0
 #define TX0_ANATXACONTROL1_IPREDRV_BITS                            3
 #define TX0_ANATXACONTROL1_IPREDRV_SHIFT                           13
 
 /* Tx0 :: anaTxAControl1 :: refl_tx [12:12] */
 #define TX0_ANATXACONTROL1_REFL_TX_MASK                            0x1000
 #define TX0_ANATXACONTROL1_REFL_TX_ALIGN                           0
 #define TX0_ANATXACONTROL1_REFL_TX_BITS                            1
 #define TX0_ANATXACONTROL1_REFL_TX_SHIFT                           12
 
 /* Tx0 :: anaTxAControl1 :: refh_tx [11:11] */
 #define TX0_ANATXACONTROL1_REFH_TX_MASK                            0x0800
 #define TX0_ANATXACONTROL1_REFH_TX_ALIGN                           0
 #define TX0_ANATXACONTROL1_REFH_TX_BITS                            1
 #define TX0_ANATXACONTROL1_REFH_TX_SHIFT                           11
 
 /* Tx0 :: anaTxAControl1 :: newbias_en [10:10] */
 #define TX0_ANATXACONTROL1_NEWBIAS_EN_MASK                         0x0400
 #define TX0_ANATXACONTROL1_NEWBIAS_EN_ALIGN                        0
 #define TX0_ANATXACONTROL1_NEWBIAS_EN_BITS                         1
 #define TX0_ANATXACONTROL1_NEWBIAS_EN_SHIFT                        10
 
 /* Tx0 :: anaTxAControl1 :: drivermode [09:09] */
 #define TX0_ANATXACONTROL1_DRIVERMODE_MASK                         0x0200
 #define TX0_ANATXACONTROL1_DRIVERMODE_ALIGN                        0
 #define TX0_ANATXACONTROL1_DRIVERMODE_BITS                         1
 #define TX0_ANATXACONTROL1_DRIVERMODE_SHIFT                        9
 
 /* Tx0 :: anaTxAControl1 :: vddr_bgb [08:08] */
 #define TX0_ANATXACONTROL1_VDDR_BGB_MASK                           0x0100
 #define TX0_ANATXACONTROL1_VDDR_BGB_ALIGN                          0
 #define TX0_ANATXACONTROL1_VDDR_BGB_BITS                           1
 #define TX0_ANATXACONTROL1_VDDR_BGB_SHIFT                          8
 
 /* Tx0 :: anaTxAControl1 :: ticksel [07:06] */
 #define TX0_ANATXACONTROL1_TICKSEL_MASK                            0x00c0
 #define TX0_ANATXACONTROL1_TICKSEL_ALIGN                           0
 #define TX0_ANATXACONTROL1_TICKSEL_BITS                            2
 #define TX0_ANATXACONTROL1_TICKSEL_SHIFT                           6
 
 /* Tx0 :: anaTxAControl1 :: driver_vcm [05:04] */
 #define TX0_ANATXACONTROL1_DRIVER_VCM_MASK                         0x0030
 #define TX0_ANATXACONTROL1_DRIVER_VCM_ALIGN                        0
 #define TX0_ANATXACONTROL1_DRIVER_VCM_BITS                         2
 #define TX0_ANATXACONTROL1_DRIVER_VCM_SHIFT                        4
 
 /* Tx0 :: anaTxAControl1 :: amp_ctrl [03:03] */
 #define TX0_ANATXACONTROL1_AMP_CTRL_MASK                           0x0008
 #define TX0_ANATXACONTROL1_AMP_CTRL_ALIGN                          0
 #define TX0_ANATXACONTROL1_AMP_CTRL_BITS                           1
 #define TX0_ANATXACONTROL1_AMP_CTRL_SHIFT                          3
 
 /* Tx0 :: anaTxAControl1 :: ifullspd [02:00] */
 #define TX0_ANATXACONTROL1_IFULLSPD_MASK                           0x0007
 #define TX0_ANATXACONTROL1_IFULLSPD_ALIGN                          0
 #define TX0_ANATXACONTROL1_IFULLSPD_BITS                           3
 #define TX0_ANATXACONTROL1_IFULLSPD_SHIFT                          0
 
 
 /****************************************************************************
  * Tx0 :: anaTxAControl2
  */
 /* Tx0 :: anaTxAControl2 :: icbuf1t [15:14] */
 #define TX0_ANATXACONTROL2_ICBUF1T_MASK                            0xc000
 #define TX0_ANATXACONTROL2_ICBUF1T_ALIGN                           0
 #define TX0_ANATXACONTROL2_ICBUF1T_BITS                            2
 #define TX0_ANATXACONTROL2_ICBUF1T_SHIFT                           14
 
 /* Tx0 :: anaTxAControl2 :: icbuf2t [13:11] */
 #define TX0_ANATXACONTROL2_ICBUF2T_MASK                            0x3800
 #define TX0_ANATXACONTROL2_ICBUF2T_ALIGN                           0
 #define TX0_ANATXACONTROL2_ICBUF2T_BITS                            3
 #define TX0_ANATXACONTROL2_ICBUF2T_SHIFT                           11
 
 /* Tx0 :: anaTxAControl2 :: imin_predrv [10:10] */
 #define TX0_ANATXACONTROL2_IMIN_PREDRV_MASK                        0x0400
 #define TX0_ANATXACONTROL2_IMIN_PREDRV_ALIGN                       0
 #define TX0_ANATXACONTROL2_IMIN_PREDRV_BITS                        1
 #define TX0_ANATXACONTROL2_IMIN_PREDRV_SHIFT                       10
 
 /* Tx0 :: anaTxAControl2 :: imax_predrv [09:09] */
 #define TX0_ANATXACONTROL2_IMAX_PREDRV_MASK                        0x0200
 #define TX0_ANATXACONTROL2_IMAX_PREDRV_ALIGN                       0
 #define TX0_ANATXACONTROL2_IMAX_PREDRV_BITS                        1
 #define TX0_ANATXACONTROL2_IMAX_PREDRV_SHIFT                       9
 
 /* Tx0 :: anaTxAControl2 :: imode_predrv [08:08] */
 #define TX0_ANATXACONTROL2_IMODE_PREDRV_MASK                       0x0100
 #define TX0_ANATXACONTROL2_IMODE_PREDRV_ALIGN                      0
 #define TX0_ANATXACONTROL2_IMODE_PREDRV_BITS                       1
 #define TX0_ANATXACONTROL2_IMODE_PREDRV_SHIFT                      8
 
 /* Tx0 :: anaTxAControl2 :: i21mux [07:05] */
 #define TX0_ANATXACONTROL2_I21MUX_MASK                             0x00e0
 #define TX0_ANATXACONTROL2_I21MUX_ALIGN                            0
 #define TX0_ANATXACONTROL2_I21MUX_BITS                             3
 #define TX0_ANATXACONTROL2_I21MUX_SHIFT                            5
 
 /* Tx0 :: anaTxAControl2 :: imin_drvr [04:04] */
 #define TX0_ANATXACONTROL2_IMIN_DRVR_MASK                          0x0010
 #define TX0_ANATXACONTROL2_IMIN_DRVR_ALIGN                         0
 #define TX0_ANATXACONTROL2_IMIN_DRVR_BITS                          1
 #define TX0_ANATXACONTROL2_IMIN_DRVR_SHIFT                         4
 
 /* Tx0 :: anaTxAControl2 :: imax_drvr [03:03] */
 #define TX0_ANATXACONTROL2_IMAX_DRVR_MASK                          0x0008
 #define TX0_ANATXACONTROL2_IMAX_DRVR_ALIGN                         0
 #define TX0_ANATXACONTROL2_IMAX_DRVR_BITS                          1
 #define TX0_ANATXACONTROL2_IMAX_DRVR_SHIFT                         3
 
 /* Tx0 :: anaTxAControl2 :: imode_drvr [02:02] */
 #define TX0_ANATXACONTROL2_IMODE_DRVR_MASK                         0x0004
 #define TX0_ANATXACONTROL2_IMODE_DRVR_ALIGN                        0
 #define TX0_ANATXACONTROL2_IMODE_DRVR_BITS                         1
 #define TX0_ANATXACONTROL2_IMODE_DRVR_SHIFT                        2
 
 /* Tx0 :: anaTxAControl2 :: reserved0 [01:00] */
 #define TX0_ANATXACONTROL2_RESERVED0_MASK                          0x0003
 #define TX0_ANATXACONTROL2_RESERVED0_ALIGN                         0
 #define TX0_ANATXACONTROL2_RESERVED0_BITS                          2
 #define TX0_ANATXACONTROL2_RESERVED0_SHIFT                         0
 
 
 /****************************************************************************
  * Tx0 :: Tx_Driver
  */
 /* Tx0 :: Tx_Driver :: ElecIdle [15:15] */
 #define TX0_TX_DRIVER_ELECIDLE_MASK                                0x8000
 #define TX0_TX_DRIVER_ELECIDLE_ALIGN                               0
 #define TX0_TX_DRIVER_ELECIDLE_BITS                                1
 #define TX0_TX_DRIVER_ELECIDLE_SHIFT                               15
 
 /* Tx0 :: Tx_Driver :: post2_coeff [14:12] */
 #define TX0_TX_DRIVER_POST2_COEFF_MASK                             0x7000
 #define TX0_TX_DRIVER_POST2_COEFF_ALIGN                            0
 #define TX0_TX_DRIVER_POST2_COEFF_BITS                             3
 #define TX0_TX_DRIVER_POST2_COEFF_SHIFT                            12
 
 /* Tx0 :: Tx_Driver :: Idriver [11:08] */
 #define TX0_TX_DRIVER_IDRIVER_MASK                                 0x0f00
 #define TX0_TX_DRIVER_IDRIVER_ALIGN                                0
 #define TX0_TX_DRIVER_IDRIVER_BITS                                 4
 #define TX0_TX_DRIVER_IDRIVER_SHIFT                                8
 #define TX0_TX_DRIVER_IDRIVER_v680mV                               0
 #define TX0_TX_DRIVER_IDRIVER_v730mV                               1
 #define TX0_TX_DRIVER_IDRIVER_v780mV                               2
 #define TX0_TX_DRIVER_IDRIVER_v830mV                               3
 #define TX0_TX_DRIVER_IDRIVER_v880mV                               4
 #define TX0_TX_DRIVER_IDRIVER_v930mV                               5
 #define TX0_TX_DRIVER_IDRIVER_v980mV                               6
 #define TX0_TX_DRIVER_IDRIVER_v1010mV                              7
 #define TX0_TX_DRIVER_IDRIVER_v1040mV                              8
 #define TX0_TX_DRIVER_IDRIVER_v1060mV                              9
 #define TX0_TX_DRIVER_IDRIVER_v1070mV                              10
 #define TX0_TX_DRIVER_IDRIVER_v1080mV                              11
 #define TX0_TX_DRIVER_IDRIVER_v1085mV                              12
 #define TX0_TX_DRIVER_IDRIVER_v1090mV                              13
 #define TX0_TX_DRIVER_IDRIVER_v1095mV                              14
 #define TX0_TX_DRIVER_IDRIVER_v1100mV                              15
 
 /* Tx0 :: Tx_Driver :: Ipredriver [07:04] */
 #define TX0_TX_DRIVER_IPREDRIVER_MASK                              0x00f0
 #define TX0_TX_DRIVER_IPREDRIVER_ALIGN                             0
 #define TX0_TX_DRIVER_IPREDRIVER_BITS                              4
 #define TX0_TX_DRIVER_IPREDRIVER_SHIFT                             4
 
 /* Tx0 :: Tx_Driver :: ifir [03:01] */
 #define TX0_TX_DRIVER_IFIR_MASK                                    0x000e
 #define TX0_TX_DRIVER_IFIR_ALIGN                                   0
 #define TX0_TX_DRIVER_IFIR_BITS                                    3
 #define TX0_TX_DRIVER_IFIR_SHIFT                                   1
 
 /* Tx0 :: Tx_Driver :: icbuf1t2 [00:00] */
 #define TX0_TX_DRIVER_ICBUF1T2_MASK                                0x0001
 #define TX0_TX_DRIVER_ICBUF1T2_ALIGN                               0
 #define TX0_TX_DRIVER_ICBUF1T2_BITS                                1
 #define TX0_TX_DRIVER_ICBUF1T2_SHIFT                               0
 
 
 /****************************************************************************
  * Warpcore_USER_Tx1
  */
 /****************************************************************************
  * Tx1 :: anaTxAStatus0
  */
 /* union - case txStatusSelect_equals_0 [15:00] */
 /* Tx1 :: anaTxAStatus0 :: reserved0 [15:07] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_MASK   0xff80
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_ALIGN  0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_BITS   9
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_SHIFT  7
 
 /* Tx1 :: anaTxAStatus0 :: txdisable_ln [06:06] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_MASK 0x0040
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_ALIGN 0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_BITS 1
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_SHIFT 6
 
 /* Tx1 :: anaTxAStatus0 :: txferr_stky [05:05] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_MASK 0x0020
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_ALIGN 0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_BITS 1
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_SHIFT 5
 
 /* Tx1 :: anaTxAStatus0 :: tbi_mode [04:04] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_MASK    0x0010
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_ALIGN   0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_BITS    1
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_SHIFT   4
 
 /* Tx1 :: anaTxAStatus0 :: tx_reset [03:03] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_MASK    0x0008
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_ALIGN   0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_BITS    1
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_SHIFT   3
 
 /* Tx1 :: anaTxAStatus0 :: tx_pwrdn [02:02] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_MASK    0x0004
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_ALIGN   0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_BITS    1
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_SHIFT   2
 
 /* Tx1 :: anaTxAStatus0 :: rltxferr_stky [01:01] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_MASK 0x0002
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_ALIGN 0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_BITS 1
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_SHIFT 1
 
 /* Tx1 :: anaTxAStatus0 :: txpll_lock [00:00] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_MASK  0x0001
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_ALIGN 0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_BITS  1
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_SHIFT 0
 
 
 /* union - case txStatusSelect_equals_1 [15:00] */
 /* Tx1 :: anaTxAStatus0 :: tx_sel_halfrate [15:15] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_MASK 0x8000
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_ALIGN 0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_BITS 1
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_SHIFT 15
 
 /* Tx1 :: anaTxAStatus0 :: tx_fir_tap_post [14:10] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_MASK 0x7c00
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_ALIGN 0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_BITS 5
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_SHIFT 10
 
 /* Tx1 :: anaTxAStatus0 :: tx_fir_tap_main [09:04] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_MASK 0x03f0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_ALIGN 0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_BITS 6
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_SHIFT 4
 
 /* Tx1 :: anaTxAStatus0 :: tx_fir_tap_pre [03:00] */
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_MASK 0x000f
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_ALIGN 0
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_BITS 4
 #define TX1_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_SHIFT 0
 
 
 
 /****************************************************************************
  * Tx1 :: anaTxAControl0
  */
 /* Tx1 :: anaTxAControl0 :: reserved0 [15:15] */
 #define TX1_ANATXACONTROL0_RESERVED0_MASK                          0x8000
 #define TX1_ANATXACONTROL0_RESERVED0_ALIGN                         0
 #define TX1_ANATXACONTROL0_RESERVED0_BITS                          1
 #define TX1_ANATXACONTROL0_RESERVED0_SHIFT                         15
 
 /* Tx1 :: anaTxAControl0 :: force_txclk [14:14] */
 #define TX1_ANATXACONTROL0_FORCE_TXCLK_MASK                        0x4000
 #define TX1_ANATXACONTROL0_FORCE_TXCLK_ALIGN                       0
 #define TX1_ANATXACONTROL0_FORCE_TXCLK_BITS                        1
 #define TX1_ANATXACONTROL0_FORCE_TXCLK_SHIFT                       14
 
 /* Tx1 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_MASK                      0x2000
 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN                     0
 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_BITS                      1
 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT                     13
 
 /* Tx1 :: anaTxAControl0 :: force_ext_frst_SM [12:12] */
 #define TX1_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK                  0x1000
 #define TX1_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN                 0
 #define TX1_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS                  1
 #define TX1_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT                 12
 
 /* Tx1 :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */
 #define TX1_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK                0x0800
 #define TX1_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN               0
 #define TX1_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS                1
 #define TX1_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT               11
 
 /* Tx1 :: anaTxAControl0 :: txck_dme_en_SM [10:10] */
 #define TX1_ANATXACONTROL0_TXCK_DME_EN_SM_MASK                     0x0400
 #define TX1_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN                    0
 #define TX1_ANATXACONTROL0_TXCK_DME_EN_SM_BITS                     1
 #define TX1_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT                    10
 
 /* Tx1 :: anaTxAControl0 :: gloopOutDis [09:09] */
 #define TX1_ANATXACONTROL0_GLOOPOUTDIS_MASK                        0x0200
 #define TX1_ANATXACONTROL0_GLOOPOUTDIS_ALIGN                       0
 #define TX1_ANATXACONTROL0_GLOOPOUTDIS_BITS                        1
 #define TX1_ANATXACONTROL0_GLOOPOUTDIS_SHIFT                       9
 
 /* Tx1 :: anaTxAControl0 :: prbs_en [08:08] */
 #define TX1_ANATXACONTROL0_PRBS_EN_MASK                            0x0100
 #define TX1_ANATXACONTROL0_PRBS_EN_ALIGN                           0
 #define TX1_ANATXACONTROL0_PRBS_EN_BITS                            1
 #define TX1_ANATXACONTROL0_PRBS_EN_SHIFT                           8
 
 /* Tx1 :: anaTxAControl0 :: pckt_en [07:07] */
 #define TX1_ANATXACONTROL0_PCKT_EN_MASK                            0x0080
 #define TX1_ANATXACONTROL0_PCKT_EN_ALIGN                           0
 #define TX1_ANATXACONTROL0_PCKT_EN_BITS                            1
 #define TX1_ANATXACONTROL0_PCKT_EN_SHIFT                           7
 
 /* Tx1 :: anaTxAControl0 :: pckt_strt [06:06] */
 #define TX1_ANATXACONTROL0_PCKT_STRT_MASK                          0x0040
 #define TX1_ANATXACONTROL0_PCKT_STRT_ALIGN                         0
 #define TX1_ANATXACONTROL0_PCKT_STRT_BITS                          1
 #define TX1_ANATXACONTROL0_PCKT_STRT_SHIFT                         6
 
 /* Tx1 :: anaTxAControl0 :: txpol_flip [05:05] */
 #define TX1_ANATXACONTROL0_TXPOL_FLIP_MASK                         0x0020
 #define TX1_ANATXACONTROL0_TXPOL_FLIP_ALIGN                        0
 #define TX1_ANATXACONTROL0_TXPOL_FLIP_BITS                         1
 #define TX1_ANATXACONTROL0_TXPOL_FLIP_SHIFT                        5
 
 /* Tx1 :: anaTxAControl0 :: rtbi_flip [04:04] */
 #define TX1_ANATXACONTROL0_RTBI_FLIP_MASK                          0x0010
 #define TX1_ANATXACONTROL0_RTBI_FLIP_ALIGN                         0
 #define TX1_ANATXACONTROL0_RTBI_FLIP_BITS                          1
 #define TX1_ANATXACONTROL0_RTBI_FLIP_SHIFT                         4
 
 /* Tx1 :: anaTxAControl0 :: eden_r [03:03] */
 #define TX1_ANATXACONTROL0_EDEN_R_MASK                             0x0008
 #define TX1_ANATXACONTROL0_EDEN_R_ALIGN                            0
 #define TX1_ANATXACONTROL0_EDEN_R_BITS                             1
 #define TX1_ANATXACONTROL0_EDEN_R_SHIFT                            3
 
 /* Tx1 :: anaTxAControl0 :: eden_force_r [02:02] */
 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_MASK                       0x0004
 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_ALIGN                      0
 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_BITS                       1
 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_SHIFT                      2
 
 /* Tx1 :: anaTxAControl0 :: txpat_en [01:01] */
 #define TX1_ANATXACONTROL0_TXPAT_EN_MASK                           0x0002
 #define TX1_ANATXACONTROL0_TXPAT_EN_ALIGN                          0
 #define TX1_ANATXACONTROL0_TXPAT_EN_BITS                           1
 #define TX1_ANATXACONTROL0_TXPAT_EN_SHIFT                          1
 
 /* Tx1 :: anaTxAControl0 :: tx_mdata_en [00:00] */
 #define TX1_ANATXACONTROL0_TX_MDATA_EN_MASK                        0x0001
 #define TX1_ANATXACONTROL0_TX_MDATA_EN_ALIGN                       0
 #define TX1_ANATXACONTROL0_TX_MDATA_EN_BITS                        1
 #define TX1_ANATXACONTROL0_TX_MDATA_EN_SHIFT                       0
 
 
 /****************************************************************************
  * Tx1 :: anaTxmdata0
  */
 /* Tx1 :: anaTxmdata0 :: txTestMuxSel [15:13] */
 #define TX1_ANATXMDATA0_TXTESTMUXSEL_MASK                          0xe000
 #define TX1_ANATXMDATA0_TXTESTMUXSEL_ALIGN                         0
 #define TX1_ANATXMDATA0_TXTESTMUXSEL_BITS                          3
 #define TX1_ANATXMDATA0_TXTESTMUXSEL_SHIFT                         13
 
 /* Tx1 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_MASK                         0x1c00
 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN                        0
 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_BITS                         3
 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT                        10
 
 /* Tx1 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_MASK                        0x03ff
 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN                       0
 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_BITS                        10
 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT                       0
 
 
 /****************************************************************************
  * Tx1 :: anaTxmdata1
  */
 /* Tx1 :: anaTxmdata1 :: txStatusSelect [15:14] */
 #define TX1_ANATXMDATA1_TXSTATUSSELECT_MASK                        0xc000
 #define TX1_ANATXMDATA1_TXSTATUSSELECT_ALIGN                       0
 #define TX1_ANATXMDATA1_TXSTATUSSELECT_BITS                        2
 #define TX1_ANATXMDATA1_TXSTATUSSELECT_SHIFT                       14
 
 /* Tx1 :: anaTxmdata1 :: reserved0 [13:10] */
 #define TX1_ANATXMDATA1_RESERVED0_MASK                             0x3c00
 #define TX1_ANATXMDATA1_RESERVED0_ALIGN                            0
 #define TX1_ANATXMDATA1_RESERVED0_BITS                             4
 #define TX1_ANATXMDATA1_RESERVED0_SHIFT                            10
 
 /* Tx1 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_MASK                        0x03ff
 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN                       0
 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_BITS                        10
 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT                       0
 
 
 /****************************************************************************
  * Tx1 :: anaTxAStatus1
  */
 /* Tx1 :: anaTxAStatus1 :: tx_id [15:14] */
 #define TX1_ANATXASTATUS1_TX_ID_MASK                               0xc000
 #define TX1_ANATXASTATUS1_TX_ID_ALIGN                              0
 #define TX1_ANATXASTATUS1_TX_ID_BITS                               2
 #define TX1_ANATXASTATUS1_TX_ID_SHIFT                              14
 
 /* Tx1 :: anaTxAStatus1 :: reserved0 [13:08] */
 #define TX1_ANATXASTATUS1_RESERVED0_MASK                           0x3f00
 #define TX1_ANATXASTATUS1_RESERVED0_ALIGN                          0
 #define TX1_ANATXASTATUS1_RESERVED0_BITS                           6
 #define TX1_ANATXASTATUS1_RESERVED0_SHIFT                          8
 
 /* Tx1 :: anaTxAStatus1 :: version_id [07:04] */
 #define TX1_ANATXASTATUS1_VERSION_ID_MASK                          0x00f0
 #define TX1_ANATXASTATUS1_VERSION_ID_ALIGN                         0
 #define TX1_ANATXASTATUS1_VERSION_ID_BITS                          4
 #define TX1_ANATXASTATUS1_VERSION_ID_SHIFT                         4
 
 /* Tx1 :: anaTxAStatus1 :: reserved1 [03:00] */
 #define TX1_ANATXASTATUS1_RESERVED1_MASK                           0x000f
 #define TX1_ANATXASTATUS1_RESERVED1_ALIGN                          0
 #define TX1_ANATXASTATUS1_RESERVED1_BITS                           4
 #define TX1_ANATXASTATUS1_RESERVED1_SHIFT                          0
 
 
 /****************************************************************************
  * Tx1 :: anaTxAControl1
  */
 /* Tx1 :: anaTxAControl1 :: ipredrv [15:13] */
 #define TX1_ANATXACONTROL1_IPREDRV_MASK                            0xe000
 #define TX1_ANATXACONTROL1_IPREDRV_ALIGN                           0
 #define TX1_ANATXACONTROL1_IPREDRV_BITS                            3
 #define TX1_ANATXACONTROL1_IPREDRV_SHIFT                           13
 
 /* Tx1 :: anaTxAControl1 :: refl_tx [12:12] */
 #define TX1_ANATXACONTROL1_REFL_TX_MASK                            0x1000
 #define TX1_ANATXACONTROL1_REFL_TX_ALIGN                           0
 #define TX1_ANATXACONTROL1_REFL_TX_BITS                            1
 #define TX1_ANATXACONTROL1_REFL_TX_SHIFT                           12
 
 /* Tx1 :: anaTxAControl1 :: refh_tx [11:11] */
 #define TX1_ANATXACONTROL1_REFH_TX_MASK                            0x0800
 #define TX1_ANATXACONTROL1_REFH_TX_ALIGN                           0
 #define TX1_ANATXACONTROL1_REFH_TX_BITS                            1
 #define TX1_ANATXACONTROL1_REFH_TX_SHIFT                           11
 
 /* Tx1 :: anaTxAControl1 :: newbias_en [10:10] */
 #define TX1_ANATXACONTROL1_NEWBIAS_EN_MASK                         0x0400
 #define TX1_ANATXACONTROL1_NEWBIAS_EN_ALIGN                        0
 #define TX1_ANATXACONTROL1_NEWBIAS_EN_BITS                         1
 #define TX1_ANATXACONTROL1_NEWBIAS_EN_SHIFT                        10
 
 /* Tx1 :: anaTxAControl1 :: drivermode [09:09] */
 #define TX1_ANATXACONTROL1_DRIVERMODE_MASK                         0x0200
 #define TX1_ANATXACONTROL1_DRIVERMODE_ALIGN                        0
 #define TX1_ANATXACONTROL1_DRIVERMODE_BITS                         1
 #define TX1_ANATXACONTROL1_DRIVERMODE_SHIFT                        9
 
 /* Tx1 :: anaTxAControl1 :: vddr_bgb [08:08] */
 #define TX1_ANATXACONTROL1_VDDR_BGB_MASK                           0x0100
 #define TX1_ANATXACONTROL1_VDDR_BGB_ALIGN                          0
 #define TX1_ANATXACONTROL1_VDDR_BGB_BITS                           1
 #define TX1_ANATXACONTROL1_VDDR_BGB_SHIFT                          8
 
 /* Tx1 :: anaTxAControl1 :: ticksel [07:06] */
 #define TX1_ANATXACONTROL1_TICKSEL_MASK                            0x00c0
 #define TX1_ANATXACONTROL1_TICKSEL_ALIGN                           0
 #define TX1_ANATXACONTROL1_TICKSEL_BITS                            2
 #define TX1_ANATXACONTROL1_TICKSEL_SHIFT                           6
 
 /* Tx1 :: anaTxAControl1 :: driver_vcm [05:04] */
 #define TX1_ANATXACONTROL1_DRIVER_VCM_MASK                         0x0030
 #define TX1_ANATXACONTROL1_DRIVER_VCM_ALIGN                        0
 #define TX1_ANATXACONTROL1_DRIVER_VCM_BITS                         2
 #define TX1_ANATXACONTROL1_DRIVER_VCM_SHIFT                        4
 
 /* Tx1 :: anaTxAControl1 :: amp_ctrl [03:03] */
 #define TX1_ANATXACONTROL1_AMP_CTRL_MASK                           0x0008
 #define TX1_ANATXACONTROL1_AMP_CTRL_ALIGN                          0
 #define TX1_ANATXACONTROL1_AMP_CTRL_BITS                           1
 #define TX1_ANATXACONTROL1_AMP_CTRL_SHIFT                          3
 
 /* Tx1 :: anaTxAControl1 :: ifullspd [02:00] */
 #define TX1_ANATXACONTROL1_IFULLSPD_MASK                           0x0007
 #define TX1_ANATXACONTROL1_IFULLSPD_ALIGN                          0
 #define TX1_ANATXACONTROL1_IFULLSPD_BITS                           3
 #define TX1_ANATXACONTROL1_IFULLSPD_SHIFT                          0
 
 
 /****************************************************************************
  * Tx1 :: anaTxAControl2
  */
 /* Tx1 :: anaTxAControl2 :: icbuf1t [15:14] */
 #define TX1_ANATXACONTROL2_ICBUF1T_MASK                            0xc000
 #define TX1_ANATXACONTROL2_ICBUF1T_ALIGN                           0
 #define TX1_ANATXACONTROL2_ICBUF1T_BITS                            2
 #define TX1_ANATXACONTROL2_ICBUF1T_SHIFT                           14
 
 /* Tx1 :: anaTxAControl2 :: icbuf2t [13:11] */
 #define TX1_ANATXACONTROL2_ICBUF2T_MASK                            0x3800
 #define TX1_ANATXACONTROL2_ICBUF2T_ALIGN                           0
 #define TX1_ANATXACONTROL2_ICBUF2T_BITS                            3
 #define TX1_ANATXACONTROL2_ICBUF2T_SHIFT                           11
 
 /* Tx1 :: anaTxAControl2 :: imin_predrv [10:10] */
 #define TX1_ANATXACONTROL2_IMIN_PREDRV_MASK                        0x0400
 #define TX1_ANATXACONTROL2_IMIN_PREDRV_ALIGN                       0
 #define TX1_ANATXACONTROL2_IMIN_PREDRV_BITS                        1
 #define TX1_ANATXACONTROL2_IMIN_PREDRV_SHIFT                       10
 
 /* Tx1 :: anaTxAControl2 :: imax_predrv [09:09] */
 #define TX1_ANATXACONTROL2_IMAX_PREDRV_MASK                        0x0200
 #define TX1_ANATXACONTROL2_IMAX_PREDRV_ALIGN                       0
 #define TX1_ANATXACONTROL2_IMAX_PREDRV_BITS                        1
 #define TX1_ANATXACONTROL2_IMAX_PREDRV_SHIFT                       9
 
 /* Tx1 :: anaTxAControl2 :: imode_predrv [08:08] */
 #define TX1_ANATXACONTROL2_IMODE_PREDRV_MASK                       0x0100
 #define TX1_ANATXACONTROL2_IMODE_PREDRV_ALIGN                      0
 #define TX1_ANATXACONTROL2_IMODE_PREDRV_BITS                       1
 #define TX1_ANATXACONTROL2_IMODE_PREDRV_SHIFT                      8
 
 /* Tx1 :: anaTxAControl2 :: i21mux [07:05] */
 #define TX1_ANATXACONTROL2_I21MUX_MASK                             0x00e0
 #define TX1_ANATXACONTROL2_I21MUX_ALIGN                            0
 #define TX1_ANATXACONTROL2_I21MUX_BITS                             3
 #define TX1_ANATXACONTROL2_I21MUX_SHIFT                            5
 
 /* Tx1 :: anaTxAControl2 :: imin_drvr [04:04] */
 #define TX1_ANATXACONTROL2_IMIN_DRVR_MASK                          0x0010
 #define TX1_ANATXACONTROL2_IMIN_DRVR_ALIGN                         0
 #define TX1_ANATXACONTROL2_IMIN_DRVR_BITS                          1
 #define TX1_ANATXACONTROL2_IMIN_DRVR_SHIFT                         4
 
 /* Tx1 :: anaTxAControl2 :: imax_drvr [03:03] */
 #define TX1_ANATXACONTROL2_IMAX_DRVR_MASK                          0x0008
 #define TX1_ANATXACONTROL2_IMAX_DRVR_ALIGN                         0
 #define TX1_ANATXACONTROL2_IMAX_DRVR_BITS                          1
 #define TX1_ANATXACONTROL2_IMAX_DRVR_SHIFT                         3
 
 /* Tx1 :: anaTxAControl2 :: imode_drvr [02:02] */
 #define TX1_ANATXACONTROL2_IMODE_DRVR_MASK                         0x0004
 #define TX1_ANATXACONTROL2_IMODE_DRVR_ALIGN                        0
 #define TX1_ANATXACONTROL2_IMODE_DRVR_BITS                         1
 #define TX1_ANATXACONTROL2_IMODE_DRVR_SHIFT                        2
 
 /* Tx1 :: anaTxAControl2 :: reserved0 [01:00] */
 #define TX1_ANATXACONTROL2_RESERVED0_MASK                          0x0003
 #define TX1_ANATXACONTROL2_RESERVED0_ALIGN                         0
 #define TX1_ANATXACONTROL2_RESERVED0_BITS                          2
 #define TX1_ANATXACONTROL2_RESERVED0_SHIFT                         0
 
 
 /****************************************************************************
  * Tx1 :: Tx_Driver
  */
 /* Tx1 :: Tx_Driver :: ElecIdle [15:15] */
 #define TX1_TX_DRIVER_ELECIDLE_MASK                                0x8000
 #define TX1_TX_DRIVER_ELECIDLE_ALIGN                               0
 #define TX1_TX_DRIVER_ELECIDLE_BITS                                1
 #define TX1_TX_DRIVER_ELECIDLE_SHIFT                               15
 
 /* Tx1 :: Tx_Driver :: post2_coeff [14:12] */
 #define TX1_TX_DRIVER_POST2_COEFF_MASK                             0x7000
 #define TX1_TX_DRIVER_POST2_COEFF_ALIGN                            0
 #define TX1_TX_DRIVER_POST2_COEFF_BITS                             3
 #define TX1_TX_DRIVER_POST2_COEFF_SHIFT                            12
 
 /* Tx1 :: Tx_Driver :: Idriver [11:08] */
 #define TX1_TX_DRIVER_IDRIVER_MASK                                 0x0f00
 #define TX1_TX_DRIVER_IDRIVER_ALIGN                                0
 #define TX1_TX_DRIVER_IDRIVER_BITS                                 4
 #define TX1_TX_DRIVER_IDRIVER_SHIFT                                8
 #define TX1_TX_DRIVER_IDRIVER_v680mV                               0
 #define TX1_TX_DRIVER_IDRIVER_v730mV                               1
 #define TX1_TX_DRIVER_IDRIVER_v780mV                               2
 #define TX1_TX_DRIVER_IDRIVER_v830mV                               3
 #define TX1_TX_DRIVER_IDRIVER_v880mV                               4
 #define TX1_TX_DRIVER_IDRIVER_v930mV                               5
 #define TX1_TX_DRIVER_IDRIVER_v980mV                               6
 #define TX1_TX_DRIVER_IDRIVER_v1010mV                              7
 #define TX1_TX_DRIVER_IDRIVER_v1040mV                              8
 #define TX1_TX_DRIVER_IDRIVER_v1060mV                              9
 #define TX1_TX_DRIVER_IDRIVER_v1070mV                              10
 #define TX1_TX_DRIVER_IDRIVER_v1080mV                              11
 #define TX1_TX_DRIVER_IDRIVER_v1085mV                              12
 #define TX1_TX_DRIVER_IDRIVER_v1090mV                              13
 #define TX1_TX_DRIVER_IDRIVER_v1095mV                              14
 #define TX1_TX_DRIVER_IDRIVER_v1100mV                              15
 
 /* Tx1 :: Tx_Driver :: Ipredriver [07:04] */
 #define TX1_TX_DRIVER_IPREDRIVER_MASK                              0x00f0
 #define TX1_TX_DRIVER_IPREDRIVER_ALIGN                             0
 #define TX1_TX_DRIVER_IPREDRIVER_BITS                              4
 #define TX1_TX_DRIVER_IPREDRIVER_SHIFT                             4
 
 /* Tx1 :: Tx_Driver :: ifir [03:01] */
 #define TX1_TX_DRIVER_IFIR_MASK                                    0x000e
 #define TX1_TX_DRIVER_IFIR_ALIGN                                   0
 #define TX1_TX_DRIVER_IFIR_BITS                                    3
 #define TX1_TX_DRIVER_IFIR_SHIFT                                   1
 
 /* Tx1 :: Tx_Driver :: icbuf1t2 [00:00] */
 #define TX1_TX_DRIVER_ICBUF1T2_MASK                                0x0001
 #define TX1_TX_DRIVER_ICBUF1T2_ALIGN                               0
 #define TX1_TX_DRIVER_ICBUF1T2_BITS                                1
 #define TX1_TX_DRIVER_ICBUF1T2_SHIFT                               0
 
 
 /****************************************************************************
  * Warpcore_USER_Tx2
  */
 /****************************************************************************
  * Tx2 :: anaTxAStatus0
  */
 /* union - case txStatusSelect_equals_0 [15:00] */
 /* Tx2 :: anaTxAStatus0 :: reserved0 [15:07] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_MASK   0xff80
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_ALIGN  0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_BITS   9
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_SHIFT  7
 
 /* Tx2 :: anaTxAStatus0 :: txdisable_ln [06:06] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_MASK 0x0040
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_ALIGN 0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_BITS 1
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_SHIFT 6
 
 /* Tx2 :: anaTxAStatus0 :: txferr_stky [05:05] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_MASK 0x0020
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_ALIGN 0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_BITS 1
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_SHIFT 5
 
 /* Tx2 :: anaTxAStatus0 :: tbi_mode [04:04] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_MASK    0x0010
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_ALIGN   0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_BITS    1
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_SHIFT   4
 
 /* Tx2 :: anaTxAStatus0 :: tx_reset [03:03] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_MASK    0x0008
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_ALIGN   0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_BITS    1
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_SHIFT   3
 
 /* Tx2 :: anaTxAStatus0 :: tx_pwrdn [02:02] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_MASK    0x0004
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_ALIGN   0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_BITS    1
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_SHIFT   2
 
 /* Tx2 :: anaTxAStatus0 :: rltxferr_stky [01:01] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_MASK 0x0002
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_ALIGN 0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_BITS 1
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_SHIFT 1
 
 /* Tx2 :: anaTxAStatus0 :: txpll_lock [00:00] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_MASK  0x0001
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_ALIGN 0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_BITS  1
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_SHIFT 0
 
 
 /* union - case txStatusSelect_equals_1 [15:00] */
 /* Tx2 :: anaTxAStatus0 :: tx_sel_halfrate [15:15] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_MASK 0x8000
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_ALIGN 0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_BITS 1
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_SHIFT 15
 
 /* Tx2 :: anaTxAStatus0 :: tx_fir_tap_post [14:10] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_MASK 0x7c00
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_ALIGN 0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_BITS 5
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_SHIFT 10
 
 /* Tx2 :: anaTxAStatus0 :: tx_fir_tap_main [09:04] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_MASK 0x03f0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_ALIGN 0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_BITS 6
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_SHIFT 4
 
 /* Tx2 :: anaTxAStatus0 :: tx_fir_tap_pre [03:00] */
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_MASK 0x000f
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_ALIGN 0
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_BITS 4
 #define TX2_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_SHIFT 0
 
 
 
 /****************************************************************************
  * Tx2 :: anaTxAControl0
  */
 /* Tx2 :: anaTxAControl0 :: reserved0 [15:15] */
 #define TX2_ANATXACONTROL0_RESERVED0_MASK                          0x8000
 #define TX2_ANATXACONTROL0_RESERVED0_ALIGN                         0
 #define TX2_ANATXACONTROL0_RESERVED0_BITS                          1
 #define TX2_ANATXACONTROL0_RESERVED0_SHIFT                         15
 
 /* Tx2 :: anaTxAControl0 :: force_txclk [14:14] */
 #define TX2_ANATXACONTROL0_FORCE_TXCLK_MASK                        0x4000
 #define TX2_ANATXACONTROL0_FORCE_TXCLK_ALIGN                       0
 #define TX2_ANATXACONTROL0_FORCE_TXCLK_BITS                        1
 #define TX2_ANATXACONTROL0_FORCE_TXCLK_SHIFT                       14
 
 /* Tx2 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_MASK                      0x2000
 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN                     0
 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_BITS                      1
 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT                     13
 
 /* Tx2 :: anaTxAControl0 :: force_ext_frst_SM [12:12] */
 #define TX2_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK                  0x1000
 #define TX2_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN                 0
 #define TX2_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS                  1
 #define TX2_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT                 12
 
 /* Tx2 :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */
 #define TX2_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK                0x0800
 #define TX2_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN               0
 #define TX2_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS                1
 #define TX2_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT               11
 
 /* Tx2 :: anaTxAControl0 :: txck_dme_en_SM [10:10] */
 #define TX2_ANATXACONTROL0_TXCK_DME_EN_SM_MASK                     0x0400
 #define TX2_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN                    0
 #define TX2_ANATXACONTROL0_TXCK_DME_EN_SM_BITS                     1
 #define TX2_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT                    10
 
 /* Tx2 :: anaTxAControl0 :: gloopOutDis [09:09] */
 #define TX2_ANATXACONTROL0_GLOOPOUTDIS_MASK                        0x0200
 #define TX2_ANATXACONTROL0_GLOOPOUTDIS_ALIGN                       0
 #define TX2_ANATXACONTROL0_GLOOPOUTDIS_BITS                        1
 #define TX2_ANATXACONTROL0_GLOOPOUTDIS_SHIFT                       9
 
 /* Tx2 :: anaTxAControl0 :: prbs_en [08:08] */
 #define TX2_ANATXACONTROL0_PRBS_EN_MASK                            0x0100
 #define TX2_ANATXACONTROL0_PRBS_EN_ALIGN                           0
 #define TX2_ANATXACONTROL0_PRBS_EN_BITS                            1
 #define TX2_ANATXACONTROL0_PRBS_EN_SHIFT                           8
 
 /* Tx2 :: anaTxAControl0 :: pckt_en [07:07] */
 #define TX2_ANATXACONTROL0_PCKT_EN_MASK                            0x0080
 #define TX2_ANATXACONTROL0_PCKT_EN_ALIGN                           0
 #define TX2_ANATXACONTROL0_PCKT_EN_BITS                            1
 #define TX2_ANATXACONTROL0_PCKT_EN_SHIFT                           7
 
 /* Tx2 :: anaTxAControl0 :: pckt_strt [06:06] */
 #define TX2_ANATXACONTROL0_PCKT_STRT_MASK                          0x0040
 #define TX2_ANATXACONTROL0_PCKT_STRT_ALIGN                         0
 #define TX2_ANATXACONTROL0_PCKT_STRT_BITS                          1
 #define TX2_ANATXACONTROL0_PCKT_STRT_SHIFT                         6
 
 /* Tx2 :: anaTxAControl0 :: txpol_flip [05:05] */
 #define TX2_ANATXACONTROL0_TXPOL_FLIP_MASK                         0x0020
 #define TX2_ANATXACONTROL0_TXPOL_FLIP_ALIGN                        0
 #define TX2_ANATXACONTROL0_TXPOL_FLIP_BITS                         1
 #define TX2_ANATXACONTROL0_TXPOL_FLIP_SHIFT                        5
 
 /* Tx2 :: anaTxAControl0 :: rtbi_flip [04:04] */
 #define TX2_ANATXACONTROL0_RTBI_FLIP_MASK                          0x0010
 #define TX2_ANATXACONTROL0_RTBI_FLIP_ALIGN                         0
 #define TX2_ANATXACONTROL0_RTBI_FLIP_BITS                          1
 #define TX2_ANATXACONTROL0_RTBI_FLIP_SHIFT                         4
 
 /* Tx2 :: anaTxAControl0 :: eden_r [03:03] */
 #define TX2_ANATXACONTROL0_EDEN_R_MASK                             0x0008
 #define TX2_ANATXACONTROL0_EDEN_R_ALIGN                            0
 #define TX2_ANATXACONTROL0_EDEN_R_BITS                             1
 #define TX2_ANATXACONTROL0_EDEN_R_SHIFT                            3
 
 /* Tx2 :: anaTxAControl0 :: eden_force_r [02:02] */
 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_MASK                       0x0004
 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_ALIGN                      0
 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_BITS                       1
 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_SHIFT                      2
 
 /* Tx2 :: anaTxAControl0 :: txpat_en [01:01] */
 #define TX2_ANATXACONTROL0_TXPAT_EN_MASK                           0x0002
 #define TX2_ANATXACONTROL0_TXPAT_EN_ALIGN                          0
 #define TX2_ANATXACONTROL0_TXPAT_EN_BITS                           1
 #define TX2_ANATXACONTROL0_TXPAT_EN_SHIFT                          1
 
 /* Tx2 :: anaTxAControl0 :: tx_mdata_en [00:00] */
 #define TX2_ANATXACONTROL0_TX_MDATA_EN_MASK                        0x0001
 #define TX2_ANATXACONTROL0_TX_MDATA_EN_ALIGN                       0
 #define TX2_ANATXACONTROL0_TX_MDATA_EN_BITS                        1
 #define TX2_ANATXACONTROL0_TX_MDATA_EN_SHIFT                       0
 
 
 /****************************************************************************
  * Tx2 :: anaTxmdata0
  */
 /* Tx2 :: anaTxmdata0 :: txTestMuxSel [15:13] */
 #define TX2_ANATXMDATA0_TXTESTMUXSEL_MASK                          0xe000
 #define TX2_ANATXMDATA0_TXTESTMUXSEL_ALIGN                         0
 #define TX2_ANATXMDATA0_TXTESTMUXSEL_BITS                          3
 #define TX2_ANATXMDATA0_TXTESTMUXSEL_SHIFT                         13
 
 /* Tx2 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_MASK                         0x1c00
 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN                        0
 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_BITS                         3
 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT                        10
 
 /* Tx2 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_MASK                        0x03ff
 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN                       0
 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_BITS                        10
 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT                       0
 
 
 /****************************************************************************
  * Tx2 :: anaTxmdata1
  */
 /* Tx2 :: anaTxmdata1 :: txStatusSelect [15:14] */
 #define TX2_ANATXMDATA1_TXSTATUSSELECT_MASK                        0xc000
 #define TX2_ANATXMDATA1_TXSTATUSSELECT_ALIGN                       0
 #define TX2_ANATXMDATA1_TXSTATUSSELECT_BITS                        2
 #define TX2_ANATXMDATA1_TXSTATUSSELECT_SHIFT                       14
 
 /* Tx2 :: anaTxmdata1 :: reserved0 [13:10] */
 #define TX2_ANATXMDATA1_RESERVED0_MASK                             0x3c00
 #define TX2_ANATXMDATA1_RESERVED0_ALIGN                            0
 #define TX2_ANATXMDATA1_RESERVED0_BITS                             4
 #define TX2_ANATXMDATA1_RESERVED0_SHIFT                            10
 
 /* Tx2 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_MASK                        0x03ff
 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN                       0
 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_BITS                        10
 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT                       0
 
 
 /****************************************************************************
  * Tx2 :: anaTxAStatus1
  */
 /* Tx2 :: anaTxAStatus1 :: tx_id [15:14] */
 #define TX2_ANATXASTATUS1_TX_ID_MASK                               0xc000
 #define TX2_ANATXASTATUS1_TX_ID_ALIGN                              0
 #define TX2_ANATXASTATUS1_TX_ID_BITS                               2
 #define TX2_ANATXASTATUS1_TX_ID_SHIFT                              14
 
 /* Tx2 :: anaTxAStatus1 :: reserved0 [13:08] */
 #define TX2_ANATXASTATUS1_RESERVED0_MASK                           0x3f00
 #define TX2_ANATXASTATUS1_RESERVED0_ALIGN                          0
 #define TX2_ANATXASTATUS1_RESERVED0_BITS                           6
 #define TX2_ANATXASTATUS1_RESERVED0_SHIFT                          8
 
 /* Tx2 :: anaTxAStatus1 :: version_id [07:04] */
 #define TX2_ANATXASTATUS1_VERSION_ID_MASK                          0x00f0
 #define TX2_ANATXASTATUS1_VERSION_ID_ALIGN                         0
 #define TX2_ANATXASTATUS1_VERSION_ID_BITS                          4
 #define TX2_ANATXASTATUS1_VERSION_ID_SHIFT                         4
 
 /* Tx2 :: anaTxAStatus1 :: reserved1 [03:00] */
 #define TX2_ANATXASTATUS1_RESERVED1_MASK                           0x000f
 #define TX2_ANATXASTATUS1_RESERVED1_ALIGN                          0
 #define TX2_ANATXASTATUS1_RESERVED1_BITS                           4
 #define TX2_ANATXASTATUS1_RESERVED1_SHIFT                          0
 
 
 /****************************************************************************
  * Tx2 :: anaTxAControl1
  */
 /* Tx2 :: anaTxAControl1 :: ipredrv [15:13] */
 #define TX2_ANATXACONTROL1_IPREDRV_MASK                            0xe000
 #define TX2_ANATXACONTROL1_IPREDRV_ALIGN                           0
 #define TX2_ANATXACONTROL1_IPREDRV_BITS                            3
 #define TX2_ANATXACONTROL1_IPREDRV_SHIFT                           13
 
 /* Tx2 :: anaTxAControl1 :: refl_tx [12:12] */
 #define TX2_ANATXACONTROL1_REFL_TX_MASK                            0x1000
 #define TX2_ANATXACONTROL1_REFL_TX_ALIGN                           0
 #define TX2_ANATXACONTROL1_REFL_TX_BITS                            1
 #define TX2_ANATXACONTROL1_REFL_TX_SHIFT                           12
 
 /* Tx2 :: anaTxAControl1 :: refh_tx [11:11] */
 #define TX2_ANATXACONTROL1_REFH_TX_MASK                            0x0800
 #define TX2_ANATXACONTROL1_REFH_TX_ALIGN                           0
 #define TX2_ANATXACONTROL1_REFH_TX_BITS                            1
 #define TX2_ANATXACONTROL1_REFH_TX_SHIFT                           11
 
 /* Tx2 :: anaTxAControl1 :: newbias_en [10:10] */
 #define TX2_ANATXACONTROL1_NEWBIAS_EN_MASK                         0x0400
 #define TX2_ANATXACONTROL1_NEWBIAS_EN_ALIGN                        0
 #define TX2_ANATXACONTROL1_NEWBIAS_EN_BITS                         1
 #define TX2_ANATXACONTROL1_NEWBIAS_EN_SHIFT                        10
 
 /* Tx2 :: anaTxAControl1 :: drivermode [09:09] */
 #define TX2_ANATXACONTROL1_DRIVERMODE_MASK                         0x0200
 #define TX2_ANATXACONTROL1_DRIVERMODE_ALIGN                        0
 #define TX2_ANATXACONTROL1_DRIVERMODE_BITS                         1
 #define TX2_ANATXACONTROL1_DRIVERMODE_SHIFT                        9
 
 /* Tx2 :: anaTxAControl1 :: vddr_bgb [08:08] */
 #define TX2_ANATXACONTROL1_VDDR_BGB_MASK                           0x0100
 #define TX2_ANATXACONTROL1_VDDR_BGB_ALIGN                          0
 #define TX2_ANATXACONTROL1_VDDR_BGB_BITS                           1
 #define TX2_ANATXACONTROL1_VDDR_BGB_SHIFT                          8
 
 /* Tx2 :: anaTxAControl1 :: ticksel [07:06] */
 #define TX2_ANATXACONTROL1_TICKSEL_MASK                            0x00c0
 #define TX2_ANATXACONTROL1_TICKSEL_ALIGN                           0
 #define TX2_ANATXACONTROL1_TICKSEL_BITS                            2
 #define TX2_ANATXACONTROL1_TICKSEL_SHIFT                           6
 
 /* Tx2 :: anaTxAControl1 :: driver_vcm [05:04] */
 #define TX2_ANATXACONTROL1_DRIVER_VCM_MASK                         0x0030
 #define TX2_ANATXACONTROL1_DRIVER_VCM_ALIGN                        0
 #define TX2_ANATXACONTROL1_DRIVER_VCM_BITS                         2
 #define TX2_ANATXACONTROL1_DRIVER_VCM_SHIFT                        4
 
 /* Tx2 :: anaTxAControl1 :: amp_ctrl [03:03] */
 #define TX2_ANATXACONTROL1_AMP_CTRL_MASK                           0x0008
 #define TX2_ANATXACONTROL1_AMP_CTRL_ALIGN                          0
 #define TX2_ANATXACONTROL1_AMP_CTRL_BITS                           1
 #define TX2_ANATXACONTROL1_AMP_CTRL_SHIFT                          3
 
 /* Tx2 :: anaTxAControl1 :: ifullspd [02:00] */
 #define TX2_ANATXACONTROL1_IFULLSPD_MASK                           0x0007
 #define TX2_ANATXACONTROL1_IFULLSPD_ALIGN                          0
 #define TX2_ANATXACONTROL1_IFULLSPD_BITS                           3
 #define TX2_ANATXACONTROL1_IFULLSPD_SHIFT                          0
 
 
 /****************************************************************************
  * Tx2 :: anaTxAControl2
  */
 /* Tx2 :: anaTxAControl2 :: icbuf1t [15:14] */
 #define TX2_ANATXACONTROL2_ICBUF1T_MASK                            0xc000
 #define TX2_ANATXACONTROL2_ICBUF1T_ALIGN                           0
 #define TX2_ANATXACONTROL2_ICBUF1T_BITS                            2
 #define TX2_ANATXACONTROL2_ICBUF1T_SHIFT                           14
 
 /* Tx2 :: anaTxAControl2 :: icbuf2t [13:11] */
 #define TX2_ANATXACONTROL2_ICBUF2T_MASK                            0x3800
 #define TX2_ANATXACONTROL2_ICBUF2T_ALIGN                           0
 #define TX2_ANATXACONTROL2_ICBUF2T_BITS                            3
 #define TX2_ANATXACONTROL2_ICBUF2T_SHIFT                           11
 
 /* Tx2 :: anaTxAControl2 :: imin_predrv [10:10] */
 #define TX2_ANATXACONTROL2_IMIN_PREDRV_MASK                        0x0400
 #define TX2_ANATXACONTROL2_IMIN_PREDRV_ALIGN                       0
 #define TX2_ANATXACONTROL2_IMIN_PREDRV_BITS                        1
 #define TX2_ANATXACONTROL2_IMIN_PREDRV_SHIFT                       10
 
 /* Tx2 :: anaTxAControl2 :: imax_predrv [09:09] */
 #define TX2_ANATXACONTROL2_IMAX_PREDRV_MASK                        0x0200
 #define TX2_ANATXACONTROL2_IMAX_PREDRV_ALIGN                       0
 #define TX2_ANATXACONTROL2_IMAX_PREDRV_BITS                        1
 #define TX2_ANATXACONTROL2_IMAX_PREDRV_SHIFT                       9
 
 /* Tx2 :: anaTxAControl2 :: imode_predrv [08:08] */
 #define TX2_ANATXACONTROL2_IMODE_PREDRV_MASK                       0x0100
 #define TX2_ANATXACONTROL2_IMODE_PREDRV_ALIGN                      0
 #define TX2_ANATXACONTROL2_IMODE_PREDRV_BITS                       1
 #define TX2_ANATXACONTROL2_IMODE_PREDRV_SHIFT                      8
 
 /* Tx2 :: anaTxAControl2 :: i21mux [07:05] */
 #define TX2_ANATXACONTROL2_I21MUX_MASK                             0x00e0
 #define TX2_ANATXACONTROL2_I21MUX_ALIGN                            0
 #define TX2_ANATXACONTROL2_I21MUX_BITS                             3
 #define TX2_ANATXACONTROL2_I21MUX_SHIFT                            5
 
 /* Tx2 :: anaTxAControl2 :: imin_drvr [04:04] */
 #define TX2_ANATXACONTROL2_IMIN_DRVR_MASK                          0x0010
 #define TX2_ANATXACONTROL2_IMIN_DRVR_ALIGN                         0
 #define TX2_ANATXACONTROL2_IMIN_DRVR_BITS                          1
 #define TX2_ANATXACONTROL2_IMIN_DRVR_SHIFT                         4
 
 /* Tx2 :: anaTxAControl2 :: imax_drvr [03:03] */
 #define TX2_ANATXACONTROL2_IMAX_DRVR_MASK                          0x0008
 #define TX2_ANATXACONTROL2_IMAX_DRVR_ALIGN                         0
 #define TX2_ANATXACONTROL2_IMAX_DRVR_BITS                          1
 #define TX2_ANATXACONTROL2_IMAX_DRVR_SHIFT                         3
 
 /* Tx2 :: anaTxAControl2 :: imode_drvr [02:02] */
 #define TX2_ANATXACONTROL2_IMODE_DRVR_MASK                         0x0004
 #define TX2_ANATXACONTROL2_IMODE_DRVR_ALIGN                        0
 #define TX2_ANATXACONTROL2_IMODE_DRVR_BITS                         1
 #define TX2_ANATXACONTROL2_IMODE_DRVR_SHIFT                        2
 
 /* Tx2 :: anaTxAControl2 :: reserved0 [01:00] */
 #define TX2_ANATXACONTROL2_RESERVED0_MASK                          0x0003
 #define TX2_ANATXACONTROL2_RESERVED0_ALIGN                         0
 #define TX2_ANATXACONTROL2_RESERVED0_BITS                          2
 #define TX2_ANATXACONTROL2_RESERVED0_SHIFT                         0
 
 
 /****************************************************************************
  * Tx2 :: Tx_Driver
  */
 /* Tx2 :: Tx_Driver :: ElecIdle [15:15] */
 #define TX2_TX_DRIVER_ELECIDLE_MASK                                0x8000
 #define TX2_TX_DRIVER_ELECIDLE_ALIGN                               0
 #define TX2_TX_DRIVER_ELECIDLE_BITS                                1
 #define TX2_TX_DRIVER_ELECIDLE_SHIFT                               15
 
 /* Tx2 :: Tx_Driver :: post2_coeff [14:12] */
 #define TX2_TX_DRIVER_POST2_COEFF_MASK                             0x7000
 #define TX2_TX_DRIVER_POST2_COEFF_ALIGN                            0
 #define TX2_TX_DRIVER_POST2_COEFF_BITS                             3
 #define TX2_TX_DRIVER_POST2_COEFF_SHIFT                            12
 
 /* Tx2 :: Tx_Driver :: Idriver [11:08] */
 #define TX2_TX_DRIVER_IDRIVER_MASK                                 0x0f00
 #define TX2_TX_DRIVER_IDRIVER_ALIGN                                0
 #define TX2_TX_DRIVER_IDRIVER_BITS                                 4
 #define TX2_TX_DRIVER_IDRIVER_SHIFT                                8
 #define TX2_TX_DRIVER_IDRIVER_v680mV                               0
 #define TX2_TX_DRIVER_IDRIVER_v730mV                               1
 #define TX2_TX_DRIVER_IDRIVER_v780mV                               2
 #define TX2_TX_DRIVER_IDRIVER_v830mV                               3
 #define TX2_TX_DRIVER_IDRIVER_v880mV                               4
 #define TX2_TX_DRIVER_IDRIVER_v930mV                               5
 #define TX2_TX_DRIVER_IDRIVER_v980mV                               6
 #define TX2_TX_DRIVER_IDRIVER_v1010mV                              7
 #define TX2_TX_DRIVER_IDRIVER_v1040mV                              8
 #define TX2_TX_DRIVER_IDRIVER_v1060mV                              9
 #define TX2_TX_DRIVER_IDRIVER_v1070mV                              10
 #define TX2_TX_DRIVER_IDRIVER_v1080mV                              11
 #define TX2_TX_DRIVER_IDRIVER_v1085mV                              12
 #define TX2_TX_DRIVER_IDRIVER_v1090mV                              13
 #define TX2_TX_DRIVER_IDRIVER_v1095mV                              14
 #define TX2_TX_DRIVER_IDRIVER_v1100mV                              15
 
 /* Tx2 :: Tx_Driver :: Ipredriver [07:04] */
 #define TX2_TX_DRIVER_IPREDRIVER_MASK                              0x00f0
 #define TX2_TX_DRIVER_IPREDRIVER_ALIGN                             0
 #define TX2_TX_DRIVER_IPREDRIVER_BITS                              4
 #define TX2_TX_DRIVER_IPREDRIVER_SHIFT                             4
 
 /* Tx2 :: Tx_Driver :: ifir [03:01] */
 #define TX2_TX_DRIVER_IFIR_MASK                                    0x000e
 #define TX2_TX_DRIVER_IFIR_ALIGN                                   0
 #define TX2_TX_DRIVER_IFIR_BITS                                    3
 #define TX2_TX_DRIVER_IFIR_SHIFT                                   1
 
 /* Tx2 :: Tx_Driver :: icbuf1t2 [00:00] */
 #define TX2_TX_DRIVER_ICBUF1T2_MASK                                0x0001
 #define TX2_TX_DRIVER_ICBUF1T2_ALIGN                               0
 #define TX2_TX_DRIVER_ICBUF1T2_BITS                                1
 #define TX2_TX_DRIVER_ICBUF1T2_SHIFT                               0
 
 
 /****************************************************************************
  * Warpcore_USER_Tx3
  */
 /****************************************************************************
  * Tx3 :: anaTxAStatus0
  */
 /* union - case txStatusSelect_equals_0 [15:00] */
 /* Tx3 :: anaTxAStatus0 :: reserved0 [15:07] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_MASK   0xff80
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_ALIGN  0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_BITS   9
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_SHIFT  7
 
 /* Tx3 :: anaTxAStatus0 :: txdisable_ln [06:06] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_MASK 0x0040
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_ALIGN 0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_BITS 1
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_SHIFT 6
 
 /* Tx3 :: anaTxAStatus0 :: txferr_stky [05:05] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_MASK 0x0020
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_ALIGN 0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_BITS 1
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_SHIFT 5
 
 /* Tx3 :: anaTxAStatus0 :: tbi_mode [04:04] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_MASK    0x0010
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_ALIGN   0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_BITS    1
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_SHIFT   4
 
 /* Tx3 :: anaTxAStatus0 :: tx_reset [03:03] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_MASK    0x0008
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_ALIGN   0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_BITS    1
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_SHIFT   3
 
 /* Tx3 :: anaTxAStatus0 :: tx_pwrdn [02:02] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_MASK    0x0004
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_ALIGN   0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_BITS    1
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_SHIFT   2
 
 /* Tx3 :: anaTxAStatus0 :: rltxferr_stky [01:01] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_MASK 0x0002
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_ALIGN 0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_BITS 1
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_SHIFT 1
 
 /* Tx3 :: anaTxAStatus0 :: txpll_lock [00:00] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_MASK  0x0001
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_ALIGN 0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_BITS  1
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_SHIFT 0
 
 
 /* union - case txStatusSelect_equals_1 [15:00] */
 /* Tx3 :: anaTxAStatus0 :: tx_sel_halfrate [15:15] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_MASK 0x8000
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_ALIGN 0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_BITS 1
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_SHIFT 15
 
 /* Tx3 :: anaTxAStatus0 :: tx_fir_tap_post [14:10] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_MASK 0x7c00
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_ALIGN 0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_BITS 5
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_SHIFT 10
 
 /* Tx3 :: anaTxAStatus0 :: tx_fir_tap_main [09:04] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_MASK 0x03f0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_ALIGN 0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_BITS 6
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_SHIFT 4
 
 /* Tx3 :: anaTxAStatus0 :: tx_fir_tap_pre [03:00] */
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_MASK 0x000f
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_ALIGN 0
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_BITS 4
 #define TX3_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_SHIFT 0
 
 
 
 /****************************************************************************
  * Tx3 :: anaTxAControl0
  */
 /* Tx3 :: anaTxAControl0 :: reserved0 [15:15] */
 #define TX3_ANATXACONTROL0_RESERVED0_MASK                          0x8000
 #define TX3_ANATXACONTROL0_RESERVED0_ALIGN                         0
 #define TX3_ANATXACONTROL0_RESERVED0_BITS                          1
 #define TX3_ANATXACONTROL0_RESERVED0_SHIFT                         15
 
 /* Tx3 :: anaTxAControl0 :: force_txclk [14:14] */
 #define TX3_ANATXACONTROL0_FORCE_TXCLK_MASK                        0x4000
 #define TX3_ANATXACONTROL0_FORCE_TXCLK_ALIGN                       0
 #define TX3_ANATXACONTROL0_FORCE_TXCLK_BITS                        1
 #define TX3_ANATXACONTROL0_FORCE_TXCLK_SHIFT                       14
 
 /* Tx3 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_MASK                      0x2000
 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN                     0
 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_BITS                      1
 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT                     13
 
 /* Tx3 :: anaTxAControl0 :: force_ext_frst_SM [12:12] */
 #define TX3_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK                  0x1000
 #define TX3_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN                 0
 #define TX3_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS                  1
 #define TX3_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT                 12
 
 /* Tx3 :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */
 #define TX3_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK                0x0800
 #define TX3_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN               0
 #define TX3_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS                1
 #define TX3_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT               11
 
 /* Tx3 :: anaTxAControl0 :: txck_dme_en_SM [10:10] */
 #define TX3_ANATXACONTROL0_TXCK_DME_EN_SM_MASK                     0x0400
 #define TX3_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN                    0
 #define TX3_ANATXACONTROL0_TXCK_DME_EN_SM_BITS                     1
 #define TX3_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT                    10
 
 /* Tx3 :: anaTxAControl0 :: gloopOutDis [09:09] */
 #define TX3_ANATXACONTROL0_GLOOPOUTDIS_MASK                        0x0200
 #define TX3_ANATXACONTROL0_GLOOPOUTDIS_ALIGN                       0
 #define TX3_ANATXACONTROL0_GLOOPOUTDIS_BITS                        1
 #define TX3_ANATXACONTROL0_GLOOPOUTDIS_SHIFT                       9
 
 /* Tx3 :: anaTxAControl0 :: prbs_en [08:08] */
 #define TX3_ANATXACONTROL0_PRBS_EN_MASK                            0x0100
 #define TX3_ANATXACONTROL0_PRBS_EN_ALIGN                           0
 #define TX3_ANATXACONTROL0_PRBS_EN_BITS                            1
 #define TX3_ANATXACONTROL0_PRBS_EN_SHIFT                           8
 
 /* Tx3 :: anaTxAControl0 :: pckt_en [07:07] */
 #define TX3_ANATXACONTROL0_PCKT_EN_MASK                            0x0080
 #define TX3_ANATXACONTROL0_PCKT_EN_ALIGN                           0
 #define TX3_ANATXACONTROL0_PCKT_EN_BITS                            1
 #define TX3_ANATXACONTROL0_PCKT_EN_SHIFT                           7
 
 /* Tx3 :: anaTxAControl0 :: pckt_strt [06:06] */
 #define TX3_ANATXACONTROL0_PCKT_STRT_MASK                          0x0040
 #define TX3_ANATXACONTROL0_PCKT_STRT_ALIGN                         0
 #define TX3_ANATXACONTROL0_PCKT_STRT_BITS                          1
 #define TX3_ANATXACONTROL0_PCKT_STRT_SHIFT                         6
 
 /* Tx3 :: anaTxAControl0 :: txpol_flip [05:05] */
 #define TX3_ANATXACONTROL0_TXPOL_FLIP_MASK                         0x0020
 #define TX3_ANATXACONTROL0_TXPOL_FLIP_ALIGN                        0
 #define TX3_ANATXACONTROL0_TXPOL_FLIP_BITS                         1
 #define TX3_ANATXACONTROL0_TXPOL_FLIP_SHIFT                        5
 
 /* Tx3 :: anaTxAControl0 :: rtbi_flip [04:04] */
 #define TX3_ANATXACONTROL0_RTBI_FLIP_MASK                          0x0010
 #define TX3_ANATXACONTROL0_RTBI_FLIP_ALIGN                         0
 #define TX3_ANATXACONTROL0_RTBI_FLIP_BITS                          1
 #define TX3_ANATXACONTROL0_RTBI_FLIP_SHIFT                         4
 
 /* Tx3 :: anaTxAControl0 :: eden_r [03:03] */
 #define TX3_ANATXACONTROL0_EDEN_R_MASK                             0x0008
 #define TX3_ANATXACONTROL0_EDEN_R_ALIGN                            0
 #define TX3_ANATXACONTROL0_EDEN_R_BITS                             1
 #define TX3_ANATXACONTROL0_EDEN_R_SHIFT                            3
 
 /* Tx3 :: anaTxAControl0 :: eden_force_r [02:02] */
 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_MASK                       0x0004
 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_ALIGN                      0
 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_BITS                       1
 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_SHIFT                      2
 
 /* Tx3 :: anaTxAControl0 :: txpat_en [01:01] */
 #define TX3_ANATXACONTROL0_TXPAT_EN_MASK                           0x0002
 #define TX3_ANATXACONTROL0_TXPAT_EN_ALIGN                          0
 #define TX3_ANATXACONTROL0_TXPAT_EN_BITS                           1
 #define TX3_ANATXACONTROL0_TXPAT_EN_SHIFT                          1
 
 /* Tx3 :: anaTxAControl0 :: tx_mdata_en [00:00] */
 #define TX3_ANATXACONTROL0_TX_MDATA_EN_MASK                        0x0001
 #define TX3_ANATXACONTROL0_TX_MDATA_EN_ALIGN                       0
 #define TX3_ANATXACONTROL0_TX_MDATA_EN_BITS                        1
 #define TX3_ANATXACONTROL0_TX_MDATA_EN_SHIFT                       0
 
 
 /****************************************************************************
  * Tx3 :: anaTxmdata0
  */
 /* Tx3 :: anaTxmdata0 :: txTestMuxSel [15:13] */
 #define TX3_ANATXMDATA0_TXTESTMUXSEL_MASK                          0xe000
 #define TX3_ANATXMDATA0_TXTESTMUXSEL_ALIGN                         0
 #define TX3_ANATXMDATA0_TXTESTMUXSEL_BITS                          3
 #define TX3_ANATXMDATA0_TXTESTMUXSEL_SHIFT                         13
 
 /* Tx3 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_MASK                         0x1c00
 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN                        0
 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_BITS                         3
 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT                        10
 
 /* Tx3 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_MASK                        0x03ff
 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN                       0
 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_BITS                        10
 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT                       0
 
 
 /****************************************************************************
  * Tx3 :: anaTxmdata1
  */
 /* Tx3 :: anaTxmdata1 :: txStatusSelect [15:14] */
 #define TX3_ANATXMDATA1_TXSTATUSSELECT_MASK                        0xc000
 #define TX3_ANATXMDATA1_TXSTATUSSELECT_ALIGN                       0
 #define TX3_ANATXMDATA1_TXSTATUSSELECT_BITS                        2
 #define TX3_ANATXMDATA1_TXSTATUSSELECT_SHIFT                       14
 
 /* Tx3 :: anaTxmdata1 :: reserved0 [13:10] */
 #define TX3_ANATXMDATA1_RESERVED0_MASK                             0x3c00
 #define TX3_ANATXMDATA1_RESERVED0_ALIGN                            0
 #define TX3_ANATXMDATA1_RESERVED0_BITS                             4
 #define TX3_ANATXMDATA1_RESERVED0_SHIFT                            10
 
 /* Tx3 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_MASK                        0x03ff
 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN                       0
 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_BITS                        10
 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT                       0
 
 
 /****************************************************************************
  * Tx3 :: anaTxAStatus1
  */
 /* Tx3 :: anaTxAStatus1 :: tx_id [15:14] */
 #define TX3_ANATXASTATUS1_TX_ID_MASK                               0xc000
 #define TX3_ANATXASTATUS1_TX_ID_ALIGN                              0
 #define TX3_ANATXASTATUS1_TX_ID_BITS                               2
 #define TX3_ANATXASTATUS1_TX_ID_SHIFT                              14
 
 /* Tx3 :: anaTxAStatus1 :: reserved0 [13:08] */
 #define TX3_ANATXASTATUS1_RESERVED0_MASK                           0x3f00
 #define TX3_ANATXASTATUS1_RESERVED0_ALIGN                          0
 #define TX3_ANATXASTATUS1_RESERVED0_BITS                           6
 #define TX3_ANATXASTATUS1_RESERVED0_SHIFT                          8
 
 /* Tx3 :: anaTxAStatus1 :: version_id [07:04] */
 #define TX3_ANATXASTATUS1_VERSION_ID_MASK                          0x00f0
 #define TX3_ANATXASTATUS1_VERSION_ID_ALIGN                         0
 #define TX3_ANATXASTATUS1_VERSION_ID_BITS                          4
 #define TX3_ANATXASTATUS1_VERSION_ID_SHIFT                         4
 
 /* Tx3 :: anaTxAStatus1 :: reserved1 [03:00] */
 #define TX3_ANATXASTATUS1_RESERVED1_MASK                           0x000f
 #define TX3_ANATXASTATUS1_RESERVED1_ALIGN                          0
 #define TX3_ANATXASTATUS1_RESERVED1_BITS                           4
 #define TX3_ANATXASTATUS1_RESERVED1_SHIFT                          0
 
 
 /****************************************************************************
  * Tx3 :: anaTxAControl1
  */
 /* Tx3 :: anaTxAControl1 :: ipredrv [15:13] */
 #define TX3_ANATXACONTROL1_IPREDRV_MASK                            0xe000
 #define TX3_ANATXACONTROL1_IPREDRV_ALIGN                           0
 #define TX3_ANATXACONTROL1_IPREDRV_BITS                            3
 #define TX3_ANATXACONTROL1_IPREDRV_SHIFT                           13
 
 /* Tx3 :: anaTxAControl1 :: refl_tx [12:12] */
 #define TX3_ANATXACONTROL1_REFL_TX_MASK                            0x1000
 #define TX3_ANATXACONTROL1_REFL_TX_ALIGN                           0
 #define TX3_ANATXACONTROL1_REFL_TX_BITS                            1
 #define TX3_ANATXACONTROL1_REFL_TX_SHIFT                           12
 
 /* Tx3 :: anaTxAControl1 :: refh_tx [11:11] */
 #define TX3_ANATXACONTROL1_REFH_TX_MASK                            0x0800
 #define TX3_ANATXACONTROL1_REFH_TX_ALIGN                           0
 #define TX3_ANATXACONTROL1_REFH_TX_BITS                            1
 #define TX3_ANATXACONTROL1_REFH_TX_SHIFT                           11
 
 /* Tx3 :: anaTxAControl1 :: newbias_en [10:10] */
 #define TX3_ANATXACONTROL1_NEWBIAS_EN_MASK                         0x0400
 #define TX3_ANATXACONTROL1_NEWBIAS_EN_ALIGN                        0
 #define TX3_ANATXACONTROL1_NEWBIAS_EN_BITS                         1
 #define TX3_ANATXACONTROL1_NEWBIAS_EN_SHIFT                        10
 
 /* Tx3 :: anaTxAControl1 :: drivermode [09:09] */
 #define TX3_ANATXACONTROL1_DRIVERMODE_MASK                         0x0200
 #define TX3_ANATXACONTROL1_DRIVERMODE_ALIGN                        0
 #define TX3_ANATXACONTROL1_DRIVERMODE_BITS                         1
 #define TX3_ANATXACONTROL1_DRIVERMODE_SHIFT                        9
 
 /* Tx3 :: anaTxAControl1 :: vddr_bgb [08:08] */
 #define TX3_ANATXACONTROL1_VDDR_BGB_MASK                           0x0100
 #define TX3_ANATXACONTROL1_VDDR_BGB_ALIGN                          0
 #define TX3_ANATXACONTROL1_VDDR_BGB_BITS                           1
 #define TX3_ANATXACONTROL1_VDDR_BGB_SHIFT                          8
 
 /* Tx3 :: anaTxAControl1 :: ticksel [07:06] */
 #define TX3_ANATXACONTROL1_TICKSEL_MASK                            0x00c0
 #define TX3_ANATXACONTROL1_TICKSEL_ALIGN                           0
 #define TX3_ANATXACONTROL1_TICKSEL_BITS                            2
 #define TX3_ANATXACONTROL1_TICKSEL_SHIFT                           6
 
 /* Tx3 :: anaTxAControl1 :: driver_vcm [05:04] */
 #define TX3_ANATXACONTROL1_DRIVER_VCM_MASK                         0x0030
 #define TX3_ANATXACONTROL1_DRIVER_VCM_ALIGN                        0
 #define TX3_ANATXACONTROL1_DRIVER_VCM_BITS                         2
 #define TX3_ANATXACONTROL1_DRIVER_VCM_SHIFT                        4
 
 /* Tx3 :: anaTxAControl1 :: amp_ctrl [03:03] */
 #define TX3_ANATXACONTROL1_AMP_CTRL_MASK                           0x0008
 #define TX3_ANATXACONTROL1_AMP_CTRL_ALIGN                          0
 #define TX3_ANATXACONTROL1_AMP_CTRL_BITS                           1
 #define TX3_ANATXACONTROL1_AMP_CTRL_SHIFT                          3
 
 /* Tx3 :: anaTxAControl1 :: ifullspd [02:00] */
 #define TX3_ANATXACONTROL1_IFULLSPD_MASK                           0x0007
 #define TX3_ANATXACONTROL1_IFULLSPD_ALIGN                          0
 #define TX3_ANATXACONTROL1_IFULLSPD_BITS                           3
 #define TX3_ANATXACONTROL1_IFULLSPD_SHIFT                          0
 
 
 /****************************************************************************
  * Tx3 :: anaTxAControl2
  */
 /* Tx3 :: anaTxAControl2 :: icbuf1t [15:14] */
 #define TX3_ANATXACONTROL2_ICBUF1T_MASK                            0xc000
 #define TX3_ANATXACONTROL2_ICBUF1T_ALIGN                           0
 #define TX3_ANATXACONTROL2_ICBUF1T_BITS                            2
 #define TX3_ANATXACONTROL2_ICBUF1T_SHIFT                           14
 
 /* Tx3 :: anaTxAControl2 :: icbuf2t [13:11] */
 #define TX3_ANATXACONTROL2_ICBUF2T_MASK                            0x3800
 #define TX3_ANATXACONTROL2_ICBUF2T_ALIGN                           0
 #define TX3_ANATXACONTROL2_ICBUF2T_BITS                            3
 #define TX3_ANATXACONTROL2_ICBUF2T_SHIFT                           11
 
 /* Tx3 :: anaTxAControl2 :: imin_predrv [10:10] */
 #define TX3_ANATXACONTROL2_IMIN_PREDRV_MASK                        0x0400
 #define TX3_ANATXACONTROL2_IMIN_PREDRV_ALIGN                       0
 #define TX3_ANATXACONTROL2_IMIN_PREDRV_BITS                        1
 #define TX3_ANATXACONTROL2_IMIN_PREDRV_SHIFT                       10
 
 /* Tx3 :: anaTxAControl2 :: imax_predrv [09:09] */
 #define TX3_ANATXACONTROL2_IMAX_PREDRV_MASK                        0x0200
 #define TX3_ANATXACONTROL2_IMAX_PREDRV_ALIGN                       0
 #define TX3_ANATXACONTROL2_IMAX_PREDRV_BITS                        1
 #define TX3_ANATXACONTROL2_IMAX_PREDRV_SHIFT                       9
 
 /* Tx3 :: anaTxAControl2 :: imode_predrv [08:08] */
 #define TX3_ANATXACONTROL2_IMODE_PREDRV_MASK                       0x0100
 #define TX3_ANATXACONTROL2_IMODE_PREDRV_ALIGN                      0
 #define TX3_ANATXACONTROL2_IMODE_PREDRV_BITS                       1
 #define TX3_ANATXACONTROL2_IMODE_PREDRV_SHIFT                      8
 
 /* Tx3 :: anaTxAControl2 :: i21mux [07:05] */
 #define TX3_ANATXACONTROL2_I21MUX_MASK                             0x00e0
 #define TX3_ANATXACONTROL2_I21MUX_ALIGN                            0
 #define TX3_ANATXACONTROL2_I21MUX_BITS                             3
 #define TX3_ANATXACONTROL2_I21MUX_SHIFT                            5
 
 /* Tx3 :: anaTxAControl2 :: imin_drvr [04:04] */
 #define TX3_ANATXACONTROL2_IMIN_DRVR_MASK                          0x0010
 #define TX3_ANATXACONTROL2_IMIN_DRVR_ALIGN                         0
 #define TX3_ANATXACONTROL2_IMIN_DRVR_BITS                          1
 #define TX3_ANATXACONTROL2_IMIN_DRVR_SHIFT                         4
 
 /* Tx3 :: anaTxAControl2 :: imax_drvr [03:03] */
 #define TX3_ANATXACONTROL2_IMAX_DRVR_MASK                          0x0008
 #define TX3_ANATXACONTROL2_IMAX_DRVR_ALIGN                         0
 #define TX3_ANATXACONTROL2_IMAX_DRVR_BITS                          1
 #define TX3_ANATXACONTROL2_IMAX_DRVR_SHIFT                         3
 
 /* Tx3 :: anaTxAControl2 :: imode_drvr [02:02] */
 #define TX3_ANATXACONTROL2_IMODE_DRVR_MASK                         0x0004
 #define TX3_ANATXACONTROL2_IMODE_DRVR_ALIGN                        0
 #define TX3_ANATXACONTROL2_IMODE_DRVR_BITS                         1
 #define TX3_ANATXACONTROL2_IMODE_DRVR_SHIFT                        2
 
 /* Tx3 :: anaTxAControl2 :: reserved0 [01:00] */
 #define TX3_ANATXACONTROL2_RESERVED0_MASK                          0x0003
 #define TX3_ANATXACONTROL2_RESERVED0_ALIGN                         0
 #define TX3_ANATXACONTROL2_RESERVED0_BITS                          2
 #define TX3_ANATXACONTROL2_RESERVED0_SHIFT                         0
 
 
 /****************************************************************************
  * Tx3 :: Tx_Driver
  */
 /* Tx3 :: Tx_Driver :: ElecIdle [15:15] */
 #define TX3_TX_DRIVER_ELECIDLE_MASK                                0x8000
 #define TX3_TX_DRIVER_ELECIDLE_ALIGN                               0
 #define TX3_TX_DRIVER_ELECIDLE_BITS                                1
 #define TX3_TX_DRIVER_ELECIDLE_SHIFT                               15
 
 /* Tx3 :: Tx_Driver :: post2_coeff [14:12] */
 #define TX3_TX_DRIVER_POST2_COEFF_MASK                             0x7000
 #define TX3_TX_DRIVER_POST2_COEFF_ALIGN                            0
 #define TX3_TX_DRIVER_POST2_COEFF_BITS                             3
 #define TX3_TX_DRIVER_POST2_COEFF_SHIFT                            12
 
 /* Tx3 :: Tx_Driver :: Idriver [11:08] */
 #define TX3_TX_DRIVER_IDRIVER_MASK                                 0x0f00
 #define TX3_TX_DRIVER_IDRIVER_ALIGN                                0
 #define TX3_TX_DRIVER_IDRIVER_BITS                                 4
 #define TX3_TX_DRIVER_IDRIVER_SHIFT                                8
 #define TX3_TX_DRIVER_IDRIVER_v680mV                               0
 #define TX3_TX_DRIVER_IDRIVER_v730mV                               1
 #define TX3_TX_DRIVER_IDRIVER_v780mV                               2
 #define TX3_TX_DRIVER_IDRIVER_v830mV                               3
 #define TX3_TX_DRIVER_IDRIVER_v880mV                               4
 #define TX3_TX_DRIVER_IDRIVER_v930mV                               5
 #define TX3_TX_DRIVER_IDRIVER_v980mV                               6
 #define TX3_TX_DRIVER_IDRIVER_v1010mV                              7
 #define TX3_TX_DRIVER_IDRIVER_v1040mV                              8
 #define TX3_TX_DRIVER_IDRIVER_v1060mV                              9
 #define TX3_TX_DRIVER_IDRIVER_v1070mV                              10
 #define TX3_TX_DRIVER_IDRIVER_v1080mV                              11
 #define TX3_TX_DRIVER_IDRIVER_v1085mV                              12
 #define TX3_TX_DRIVER_IDRIVER_v1090mV                              13
 #define TX3_TX_DRIVER_IDRIVER_v1095mV                              14
 #define TX3_TX_DRIVER_IDRIVER_v1100mV                              15
 
 /* Tx3 :: Tx_Driver :: Ipredriver [07:04] */
 #define TX3_TX_DRIVER_IPREDRIVER_MASK                              0x00f0
 #define TX3_TX_DRIVER_IPREDRIVER_ALIGN                             0
 #define TX3_TX_DRIVER_IPREDRIVER_BITS                              4
 #define TX3_TX_DRIVER_IPREDRIVER_SHIFT                             4
 
 /* Tx3 :: Tx_Driver :: ifir [03:01] */
 #define TX3_TX_DRIVER_IFIR_MASK                                    0x000e
 #define TX3_TX_DRIVER_IFIR_ALIGN                                   0
 #define TX3_TX_DRIVER_IFIR_BITS                                    3
 #define TX3_TX_DRIVER_IFIR_SHIFT                                   1
 
 /* Tx3 :: Tx_Driver :: icbuf1t2 [00:00] */
 #define TX3_TX_DRIVER_ICBUF1T2_MASK                                0x0001
 #define TX3_TX_DRIVER_ICBUF1T2_ALIGN                               0
 #define TX3_TX_DRIVER_ICBUF1T2_BITS                                1
 #define TX3_TX_DRIVER_ICBUF1T2_SHIFT                               0
 
 
 /****************************************************************************
  * Warpcore_USER_TxB
  */
 /****************************************************************************
  * TxB :: anaTxAStatus0
  */
 /* union - case txStatusSelect_equals_0 [15:00] */
 /* TxB :: anaTxAStatus0 :: reserved0 [15:07] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_MASK   0xff80
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_ALIGN  0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_BITS   9
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RESERVED0_SHIFT  7
 
 /* TxB :: anaTxAStatus0 :: txdisable_ln [06:06] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_MASK 0x0040
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_ALIGN 0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_BITS 1
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXDISABLE_LN_SHIFT 6
 
 /* TxB :: anaTxAStatus0 :: txferr_stky [05:05] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_MASK 0x0020
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_ALIGN 0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_BITS 1
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXFERR_STKY_SHIFT 5
 
 /* TxB :: anaTxAStatus0 :: tbi_mode [04:04] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_MASK    0x0010
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_ALIGN   0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_BITS    1
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TBI_MODE_SHIFT   4
 
 /* TxB :: anaTxAStatus0 :: tx_reset [03:03] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_MASK    0x0008
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_ALIGN   0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_BITS    1
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_RESET_SHIFT   3
 
 /* TxB :: anaTxAStatus0 :: tx_pwrdn [02:02] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_MASK    0x0004
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_ALIGN   0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_BITS    1
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TX_PWRDN_SHIFT   2
 
 /* TxB :: anaTxAStatus0 :: rltxferr_stky [01:01] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_MASK 0x0002
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_ALIGN 0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_BITS 1
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_RLTXFERR_STKY_SHIFT 1
 
 /* TxB :: anaTxAStatus0 :: txpll_lock [00:00] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_MASK  0x0001
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_ALIGN 0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_BITS  1
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_0_TXPLL_LOCK_SHIFT 0
 
 
 /* union - case txStatusSelect_equals_1 [15:00] */
 /* TxB :: anaTxAStatus0 :: tx_sel_halfrate [15:15] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_MASK 0x8000
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_ALIGN 0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_BITS 1
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_SEL_HALFRATE_SHIFT 15
 
 /* TxB :: anaTxAStatus0 :: tx_fir_tap_post [14:10] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_MASK 0x7c00
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_ALIGN 0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_BITS 5
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_POST_SHIFT 10
 
 /* TxB :: anaTxAStatus0 :: tx_fir_tap_main [09:04] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_MASK 0x03f0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_ALIGN 0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_BITS 6
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_MAIN_SHIFT 4
 
 /* TxB :: anaTxAStatus0 :: tx_fir_tap_pre [03:00] */
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_MASK 0x000f
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_ALIGN 0
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_BITS 4
 #define TXB_ANATXASTATUS0_TXSTATUSSELECT_EQUALS_1_TX_FIR_TAP_PRE_SHIFT 0
 
 
 
 /****************************************************************************
  * TxB :: anaTxAControl0
  */
 /* TxB :: anaTxAControl0 :: reserved0 [15:15] */
 #define TXB_ANATXACONTROL0_RESERVED0_MASK                          0x8000
 #define TXB_ANATXACONTROL0_RESERVED0_ALIGN                         0
 #define TXB_ANATXACONTROL0_RESERVED0_BITS                          1
 #define TXB_ANATXACONTROL0_RESERVED0_SHIFT                         15
 
 /* TxB :: anaTxAControl0 :: force_txclk [14:14] */
 #define TXB_ANATXACONTROL0_FORCE_TXCLK_MASK                        0x4000
 #define TXB_ANATXACONTROL0_FORCE_TXCLK_ALIGN                       0
 #define TXB_ANATXACONTROL0_FORCE_TXCLK_BITS                        1
 #define TXB_ANATXACONTROL0_FORCE_TXCLK_SHIFT                       14
 
 /* TxB :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_MASK                      0x2000
 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN                     0
 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_BITS                      1
 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT                     13
 
 /* TxB :: anaTxAControl0 :: force_ext_frst_SM [12:12] */
 #define TXB_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK                  0x1000
 #define TXB_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN                 0
 #define TXB_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS                  1
 #define TXB_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT                 12
 
 /* TxB :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */
 #define TXB_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK                0x0800
 #define TXB_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN               0
 #define TXB_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS                1
 #define TXB_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT               11
 
 /* TxB :: anaTxAControl0 :: txck_dme_en_SM [10:10] */
 #define TXB_ANATXACONTROL0_TXCK_DME_EN_SM_MASK                     0x0400
 #define TXB_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN                    0
 #define TXB_ANATXACONTROL0_TXCK_DME_EN_SM_BITS                     1
 #define TXB_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT                    10
 
 /* TxB :: anaTxAControl0 :: gloopOutDis [09:09] */
 #define TXB_ANATXACONTROL0_GLOOPOUTDIS_MASK                        0x0200
 #define TXB_ANATXACONTROL0_GLOOPOUTDIS_ALIGN                       0
 #define TXB_ANATXACONTROL0_GLOOPOUTDIS_BITS                        1
 #define TXB_ANATXACONTROL0_GLOOPOUTDIS_SHIFT                       9
 
 /* TxB :: anaTxAControl0 :: prbs_en [08:08] */
 #define TXB_ANATXACONTROL0_PRBS_EN_MASK                            0x0100
 #define TXB_ANATXACONTROL0_PRBS_EN_ALIGN                           0
 #define TXB_ANATXACONTROL0_PRBS_EN_BITS                            1
 #define TXB_ANATXACONTROL0_PRBS_EN_SHIFT                           8
 
 /* TxB :: anaTxAControl0 :: pckt_en [07:07] */
 #define TXB_ANATXACONTROL0_PCKT_EN_MASK                            0x0080
 #define TXB_ANATXACONTROL0_PCKT_EN_ALIGN                           0
 #define TXB_ANATXACONTROL0_PCKT_EN_BITS                            1
 #define TXB_ANATXACONTROL0_PCKT_EN_SHIFT                           7
 
 /* TxB :: anaTxAControl0 :: pckt_strt [06:06] */
 #define TXB_ANATXACONTROL0_PCKT_STRT_MASK                          0x0040
 #define TXB_ANATXACONTROL0_PCKT_STRT_ALIGN                         0
 #define TXB_ANATXACONTROL0_PCKT_STRT_BITS                          1
 #define TXB_ANATXACONTROL0_PCKT_STRT_SHIFT                         6
 
 /* TxB :: anaTxAControl0 :: txpol_flip [05:05] */
 #define TXB_ANATXACONTROL0_TXPOL_FLIP_MASK                         0x0020
 #define TXB_ANATXACONTROL0_TXPOL_FLIP_ALIGN                        0
 #define TXB_ANATXACONTROL0_TXPOL_FLIP_BITS                         1
 #define TXB_ANATXACONTROL0_TXPOL_FLIP_SHIFT                        5
 
 /* TxB :: anaTxAControl0 :: rtbi_flip [04:04] */
 #define TXB_ANATXACONTROL0_RTBI_FLIP_MASK                          0x0010
 #define TXB_ANATXACONTROL0_RTBI_FLIP_ALIGN                         0
 #define TXB_ANATXACONTROL0_RTBI_FLIP_BITS                          1
 #define TXB_ANATXACONTROL0_RTBI_FLIP_SHIFT                         4
 
 /* TxB :: anaTxAControl0 :: eden_r [03:03] */
 #define TXB_ANATXACONTROL0_EDEN_R_MASK                             0x0008
 #define TXB_ANATXACONTROL0_EDEN_R_ALIGN                            0
 #define TXB_ANATXACONTROL0_EDEN_R_BITS                             1
 #define TXB_ANATXACONTROL0_EDEN_R_SHIFT                            3
 
 /* TxB :: anaTxAControl0 :: eden_force_r [02:02] */
 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_MASK                       0x0004
 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_ALIGN                      0
 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_BITS                       1
 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_SHIFT                      2
 
 /* TxB :: anaTxAControl0 :: txpat_en [01:01] */
 #define TXB_ANATXACONTROL0_TXPAT_EN_MASK                           0x0002
 #define TXB_ANATXACONTROL0_TXPAT_EN_ALIGN                          0
 #define TXB_ANATXACONTROL0_TXPAT_EN_BITS                           1
 #define TXB_ANATXACONTROL0_TXPAT_EN_SHIFT                          1
 
 /* TxB :: anaTxAControl0 :: tx_mdata_en [00:00] */
 #define TXB_ANATXACONTROL0_TX_MDATA_EN_MASK                        0x0001
 #define TXB_ANATXACONTROL0_TX_MDATA_EN_ALIGN                       0
 #define TXB_ANATXACONTROL0_TX_MDATA_EN_BITS                        1
 #define TXB_ANATXACONTROL0_TX_MDATA_EN_SHIFT                       0
 
 
 /****************************************************************************
  * TxB :: anaTxmdata0
  */
 /* TxB :: anaTxmdata0 :: txTestMuxSel [15:13] */
 #define TXB_ANATXMDATA0_TXTESTMUXSEL_MASK                          0xe000
 #define TXB_ANATXMDATA0_TXTESTMUXSEL_ALIGN                         0
 #define TXB_ANATXMDATA0_TXTESTMUXSEL_BITS                          3
 #define TXB_ANATXMDATA0_TXTESTMUXSEL_SHIFT                         13
 
 /* TxB :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_MASK                         0x1c00
 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN                        0
 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_BITS                         3
 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT                        10
 
 /* TxB :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_MASK                        0x03ff
 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN                       0
 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_BITS                        10
 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT                       0
 
 
 /****************************************************************************
  * TxB :: anaTxmdata1
  */
 /* TxB :: anaTxmdata1 :: txStatusSelect [15:14] */
 #define TXB_ANATXMDATA1_TXSTATUSSELECT_MASK                        0xc000
 #define TXB_ANATXMDATA1_TXSTATUSSELECT_ALIGN                       0
 #define TXB_ANATXMDATA1_TXSTATUSSELECT_BITS                        2
 #define TXB_ANATXMDATA1_TXSTATUSSELECT_SHIFT                       14
 
 /* TxB :: anaTxmdata1 :: reserved0 [13:10] */
 #define TXB_ANATXMDATA1_RESERVED0_MASK                             0x3c00
 #define TXB_ANATXMDATA1_RESERVED0_ALIGN                            0
 #define TXB_ANATXMDATA1_RESERVED0_BITS                             4
 #define TXB_ANATXMDATA1_RESERVED0_SHIFT                            10
 
 /* TxB :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_MASK                        0x03ff
 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN                       0
 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_BITS                        10
 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT                       0
 
 
 /****************************************************************************
  * TxB :: anaTxAStatus1
  */
 /* TxB :: anaTxAStatus1 :: tx_id [15:14] */
 #define TXB_ANATXASTATUS1_TX_ID_MASK                               0xc000
 #define TXB_ANATXASTATUS1_TX_ID_ALIGN                              0
 #define TXB_ANATXASTATUS1_TX_ID_BITS                               2
 #define TXB_ANATXASTATUS1_TX_ID_SHIFT                              14
 
 /* TxB :: anaTxAStatus1 :: reserved0 [13:08] */
 #define TXB_ANATXASTATUS1_RESERVED0_MASK                           0x3f00
 #define TXB_ANATXASTATUS1_RESERVED0_ALIGN                          0
 #define TXB_ANATXASTATUS1_RESERVED0_BITS                           6
 #define TXB_ANATXASTATUS1_RESERVED0_SHIFT                          8
 
 /* TxB :: anaTxAStatus1 :: version_id [07:04] */
 #define TXB_ANATXASTATUS1_VERSION_ID_MASK                          0x00f0
 #define TXB_ANATXASTATUS1_VERSION_ID_ALIGN                         0
 #define TXB_ANATXASTATUS1_VERSION_ID_BITS                          4
 #define TXB_ANATXASTATUS1_VERSION_ID_SHIFT                         4
 
 /* TxB :: anaTxAStatus1 :: reserved1 [03:00] */
 #define TXB_ANATXASTATUS1_RESERVED1_MASK                           0x000f
 #define TXB_ANATXASTATUS1_RESERVED1_ALIGN                          0
 #define TXB_ANATXASTATUS1_RESERVED1_BITS                           4
 #define TXB_ANATXASTATUS1_RESERVED1_SHIFT                          0
 
 
 /****************************************************************************
  * TxB :: anaTxAControl1
  */
 /* TxB :: anaTxAControl1 :: ipredrv [15:13] */
 #define TXB_ANATXACONTROL1_IPREDRV_MASK                            0xe000
 #define TXB_ANATXACONTROL1_IPREDRV_ALIGN                           0
 #define TXB_ANATXACONTROL1_IPREDRV_BITS                            3
 #define TXB_ANATXACONTROL1_IPREDRV_SHIFT                           13
 
 /* TxB :: anaTxAControl1 :: refl_tx [12:12] */
 #define TXB_ANATXACONTROL1_REFL_TX_MASK                            0x1000
 #define TXB_ANATXACONTROL1_REFL_TX_ALIGN                           0
 #define TXB_ANATXACONTROL1_REFL_TX_BITS                            1
 #define TXB_ANATXACONTROL1_REFL_TX_SHIFT                           12
 
 /* TxB :: anaTxAControl1 :: refh_tx [11:11] */
 #define TXB_ANATXACONTROL1_REFH_TX_MASK                            0x0800
 #define TXB_ANATXACONTROL1_REFH_TX_ALIGN                           0
 #define TXB_ANATXACONTROL1_REFH_TX_BITS                            1
 #define TXB_ANATXACONTROL1_REFH_TX_SHIFT                           11
 
 /* TxB :: anaTxAControl1 :: newbias_en [10:10] */
 #define TXB_ANATXACONTROL1_NEWBIAS_EN_MASK                         0x0400
 #define TXB_ANATXACONTROL1_NEWBIAS_EN_ALIGN                        0
 #define TXB_ANATXACONTROL1_NEWBIAS_EN_BITS                         1
 #define TXB_ANATXACONTROL1_NEWBIAS_EN_SHIFT                        10
 
 /* TxB :: anaTxAControl1 :: drivermode [09:09] */
 #define TXB_ANATXACONTROL1_DRIVERMODE_MASK                         0x0200
 #define TXB_ANATXACONTROL1_DRIVERMODE_ALIGN                        0
 #define TXB_ANATXACONTROL1_DRIVERMODE_BITS                         1
 #define TXB_ANATXACONTROL1_DRIVERMODE_SHIFT                        9
 
 /* TxB :: anaTxAControl1 :: vddr_bgb [08:08] */
 #define TXB_ANATXACONTROL1_VDDR_BGB_MASK                           0x0100
 #define TXB_ANATXACONTROL1_VDDR_BGB_ALIGN                          0
 #define TXB_ANATXACONTROL1_VDDR_BGB_BITS                           1
 #define TXB_ANATXACONTROL1_VDDR_BGB_SHIFT                          8
 
 /* TxB :: anaTxAControl1 :: ticksel [07:06] */
 #define TXB_ANATXACONTROL1_TICKSEL_MASK                            0x00c0
 #define TXB_ANATXACONTROL1_TICKSEL_ALIGN                           0
 #define TXB_ANATXACONTROL1_TICKSEL_BITS                            2
 #define TXB_ANATXACONTROL1_TICKSEL_SHIFT                           6
 
 /* TxB :: anaTxAControl1 :: driver_vcm [05:04] */
 #define TXB_ANATXACONTROL1_DRIVER_VCM_MASK                         0x0030
 #define TXB_ANATXACONTROL1_DRIVER_VCM_ALIGN                        0
 #define TXB_ANATXACONTROL1_DRIVER_VCM_BITS                         2
 #define TXB_ANATXACONTROL1_DRIVER_VCM_SHIFT                        4
 
 /* TxB :: anaTxAControl1 :: amp_ctrl [03:03] */
 #define TXB_ANATXACONTROL1_AMP_CTRL_MASK                           0x0008
 #define TXB_ANATXACONTROL1_AMP_CTRL_ALIGN                          0
 #define TXB_ANATXACONTROL1_AMP_CTRL_BITS                           1
 #define TXB_ANATXACONTROL1_AMP_CTRL_SHIFT                          3
 
 /* TxB :: anaTxAControl1 :: ifullspd [02:00] */
 #define TXB_ANATXACONTROL1_IFULLSPD_MASK                           0x0007
 #define TXB_ANATXACONTROL1_IFULLSPD_ALIGN                          0
 #define TXB_ANATXACONTROL1_IFULLSPD_BITS                           3
 #define TXB_ANATXACONTROL1_IFULLSPD_SHIFT                          0
 
 
 /****************************************************************************
  * TxB :: anaTxAControl2
  */
 /* TxB :: anaTxAControl2 :: icbuf1t [15:14] */
 #define TXB_ANATXACONTROL2_ICBUF1T_MASK                            0xc000
 #define TXB_ANATXACONTROL2_ICBUF1T_ALIGN                           0
 #define TXB_ANATXACONTROL2_ICBUF1T_BITS                            2
 #define TXB_ANATXACONTROL2_ICBUF1T_SHIFT                           14
 
 /* TxB :: anaTxAControl2 :: icbuf2t [13:11] */
 #define TXB_ANATXACONTROL2_ICBUF2T_MASK                            0x3800
 #define TXB_ANATXACONTROL2_ICBUF2T_ALIGN                           0
 #define TXB_ANATXACONTROL2_ICBUF2T_BITS                            3
 #define TXB_ANATXACONTROL2_ICBUF2T_SHIFT                           11
 
 /* TxB :: anaTxAControl2 :: imin_predrv [10:10] */
 #define TXB_ANATXACONTROL2_IMIN_PREDRV_MASK                        0x0400
 #define TXB_ANATXACONTROL2_IMIN_PREDRV_ALIGN                       0
 #define TXB_ANATXACONTROL2_IMIN_PREDRV_BITS                        1
 #define TXB_ANATXACONTROL2_IMIN_PREDRV_SHIFT                       10
 
 /* TxB :: anaTxAControl2 :: imax_predrv [09:09] */
 #define TXB_ANATXACONTROL2_IMAX_PREDRV_MASK                        0x0200
 #define TXB_ANATXACONTROL2_IMAX_PREDRV_ALIGN                       0
 #define TXB_ANATXACONTROL2_IMAX_PREDRV_BITS                        1
 #define TXB_ANATXACONTROL2_IMAX_PREDRV_SHIFT                       9
 
 /* TxB :: anaTxAControl2 :: imode_predrv [08:08] */
 #define TXB_ANATXACONTROL2_IMODE_PREDRV_MASK                       0x0100
 #define TXB_ANATXACONTROL2_IMODE_PREDRV_ALIGN                      0
 #define TXB_ANATXACONTROL2_IMODE_PREDRV_BITS                       1
 #define TXB_ANATXACONTROL2_IMODE_PREDRV_SHIFT                      8
 
 /* TxB :: anaTxAControl2 :: i21mux [07:05] */
 #define TXB_ANATXACONTROL2_I21MUX_MASK                             0x00e0
 #define TXB_ANATXACONTROL2_I21MUX_ALIGN                            0
 #define TXB_ANATXACONTROL2_I21MUX_BITS                             3
 #define TXB_ANATXACONTROL2_I21MUX_SHIFT                            5
 
 /* TxB :: anaTxAControl2 :: imin_drvr [04:04] */
 #define TXB_ANATXACONTROL2_IMIN_DRVR_MASK                          0x0010
 #define TXB_ANATXACONTROL2_IMIN_DRVR_ALIGN                         0
 #define TXB_ANATXACONTROL2_IMIN_DRVR_BITS                          1
 #define TXB_ANATXACONTROL2_IMIN_DRVR_SHIFT                         4
 
 /* TxB :: anaTxAControl2 :: imax_drvr [03:03] */
 #define TXB_ANATXACONTROL2_IMAX_DRVR_MASK                          0x0008
 #define TXB_ANATXACONTROL2_IMAX_DRVR_ALIGN                         0
 #define TXB_ANATXACONTROL2_IMAX_DRVR_BITS                          1
 #define TXB_ANATXACONTROL2_IMAX_DRVR_SHIFT                         3
 
 /* TxB :: anaTxAControl2 :: imode_drvr [02:02] */
 #define TXB_ANATXACONTROL2_IMODE_DRVR_MASK                         0x0004
 #define TXB_ANATXACONTROL2_IMODE_DRVR_ALIGN                        0
 #define TXB_ANATXACONTROL2_IMODE_DRVR_BITS                         1
 #define TXB_ANATXACONTROL2_IMODE_DRVR_SHIFT                        2
 
 /* TxB :: anaTxAControl2 :: reserved0 [01:00] */
 #define TXB_ANATXACONTROL2_RESERVED0_MASK                          0x0003
 #define TXB_ANATXACONTROL2_RESERVED0_ALIGN                         0
 #define TXB_ANATXACONTROL2_RESERVED0_BITS                          2
 #define TXB_ANATXACONTROL2_RESERVED0_SHIFT                         0
 
 
 /****************************************************************************
  * TxB :: Tx_Driver
  */
 /* TxB :: Tx_Driver :: ElecIdle [15:15] */
 #define TXB_TX_DRIVER_ELECIDLE_MASK                                0x8000
 #define TXB_TX_DRIVER_ELECIDLE_ALIGN                               0
 #define TXB_TX_DRIVER_ELECIDLE_BITS                                1
 #define TXB_TX_DRIVER_ELECIDLE_SHIFT                               15
 
 /* TxB :: Tx_Driver :: post2_coeff [14:12] */
 #define TXB_TX_DRIVER_POST2_COEFF_MASK                             0x7000
 #define TXB_TX_DRIVER_POST2_COEFF_ALIGN                            0
 #define TXB_TX_DRIVER_POST2_COEFF_BITS                             3
 #define TXB_TX_DRIVER_POST2_COEFF_SHIFT                            12
 
 /* TxB :: Tx_Driver :: Idriver [11:08] */
 #define TXB_TX_DRIVER_IDRIVER_MASK                                 0x0f00
 #define TXB_TX_DRIVER_IDRIVER_ALIGN                                0
 #define TXB_TX_DRIVER_IDRIVER_BITS                                 4
 #define TXB_TX_DRIVER_IDRIVER_SHIFT                                8
 #define TXB_TX_DRIVER_IDRIVER_v680mV                               0
 #define TXB_TX_DRIVER_IDRIVER_v730mV                               1
 #define TXB_TX_DRIVER_IDRIVER_v780mV                               2
 #define TXB_TX_DRIVER_IDRIVER_v830mV                               3
 #define TXB_TX_DRIVER_IDRIVER_v880mV                               4
 #define TXB_TX_DRIVER_IDRIVER_v930mV                               5
 #define TXB_TX_DRIVER_IDRIVER_v980mV                               6
 #define TXB_TX_DRIVER_IDRIVER_v1010mV                              7
 #define TXB_TX_DRIVER_IDRIVER_v1040mV                              8
 #define TXB_TX_DRIVER_IDRIVER_v1060mV                              9
 #define TXB_TX_DRIVER_IDRIVER_v1070mV                              10
 #define TXB_TX_DRIVER_IDRIVER_v1080mV                              11
 #define TXB_TX_DRIVER_IDRIVER_v1085mV                              12
 #define TXB_TX_DRIVER_IDRIVER_v1090mV                              13
 #define TXB_TX_DRIVER_IDRIVER_v1095mV                              14
 #define TXB_TX_DRIVER_IDRIVER_v1100mV                              15
 
 /* TxB :: Tx_Driver :: Ipredriver [07:04] */
 #define TXB_TX_DRIVER_IPREDRIVER_MASK                              0x00f0
 #define TXB_TX_DRIVER_IPREDRIVER_ALIGN                             0
 #define TXB_TX_DRIVER_IPREDRIVER_BITS                              4
 #define TXB_TX_DRIVER_IPREDRIVER_SHIFT                             4
 
 /* TxB :: Tx_Driver :: ifir [03:01] */
 #define TXB_TX_DRIVER_IFIR_MASK                                    0x000e
 #define TXB_TX_DRIVER_IFIR_ALIGN                                   0
 #define TXB_TX_DRIVER_IFIR_BITS                                    3
 #define TXB_TX_DRIVER_IFIR_SHIFT                                   1
 
 /* TxB :: Tx_Driver :: icbuf1t2 [00:00] */
 #define TXB_TX_DRIVER_ICBUF1T2_MASK                                0x0001
 #define TXB_TX_DRIVER_ICBUF1T2_ALIGN                               0
 #define TXB_TX_DRIVER_ICBUF1T2_BITS                                1
 #define TXB_TX_DRIVER_ICBUF1T2_SHIFT                               0
 
 
 /****************************************************************************
  * Warpcore_USER_Rx0
  */
 /****************************************************************************
  * Rx0 :: anaRxStatus
  */
 /* union - case sigdet_Status [15:00] */
 /* Rx0 :: anaRxStatus :: cx4_sigdet [15:15] */
 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK              0x8000
 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN             0
 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS              1
 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT             15
 
 /* Rx0 :: anaRxStatus :: reserved0 [14:13] */
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK               0x6000
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN              0
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS               2
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT              13
 
 /* Rx0 :: anaRxStatus :: rxSeqDone [12:12] */
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK               0x1000
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN              0
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS               1
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT              12
 
 /* Rx0 :: anaRxStatus :: rx_sigdet_ll [11:11] */
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK            0x0800
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN           0
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS            1
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT           11
 
 /* Rx0 :: anaRxStatus :: cs4_sigdet_ll [10:10] */
 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK           0x0400
 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN          0
 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS           1
 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT          10
 
 /* Rx0 :: anaRxStatus :: rx_reset [09:09] */
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK                0x0200
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN               0
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS                1
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT               9
 
 /* Rx0 :: anaRxStatus :: rx_pwrdn [08:08] */
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK                0x0100
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN               0
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS                1
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT               8
 
 /* Rx0 :: anaRxStatus :: reserved1 [07:00] */
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK               0x00ff
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN              0
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS               8
 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT              0
 
 
 /* union - case sync_Status [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:11] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK                 0xf800
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN                0
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS                 5
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT                11
 
 /* Rx0 :: anaRxStatus :: test_acq_en [10:10] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK               0x0400
 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN              0
 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS               1
 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT              10
 
 /* Rx0 :: anaRxStatus :: reserved1 [09:09] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK                 0x0200
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN                0
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS                 1
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT                9
 
 /* Rx0 :: anaRxStatus :: rxSeqStart [08:08] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK                0x0100
 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN               0
 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS                1
 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT               8
 
 /* Rx0 :: anaRxStatus :: mux_comadj_sync_status [07:07] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK    0x0080
 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN   0
 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS    1
 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT   7
 
 /* Rx0 :: anaRxStatus :: sync_status [06:06] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK               0x0040
 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN              0
 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS               1
 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT              6
 
 /* Rx0 :: anaRxStatus :: rx_sigdet [05:05] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK                 0x0020
 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN                0
 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS                 1
 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT                5
 
 /* Rx0 :: anaRxStatus :: reserved2 [04:03] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK                 0x0018
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN                0
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS                 2
 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT                3
 
 /* Rx0 :: anaRxStatus :: saturate_status [02:02] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK           0x0004
 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN          0
 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS           1
 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT          2
 
 /* Rx0 :: anaRxStatus :: cx4_sigdet [01:01] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK                0x0002
 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN               0
 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS                1
 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT               1
 
 /* Rx0 :: anaRxStatus :: rxSeqDone [00:00] */
 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK                 0x0001
 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN                0
 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS                 1
 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT                0
 
 
 /* union - case rxTestSel_0 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:10] */
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK                 0xfc00
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN                0
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS                 6
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT                10
 
 /* Rx0 :: anaRxStatus :: indck_mode_en [09:09] */
 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK             0x0200
 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN            0
 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS             1
 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT            9
 
 /* Rx0 :: anaRxStatus :: pci_mode_en [08:08] */
 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK               0x0100
 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN              0
 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS               1
 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT              8
 
 /* Rx0 :: anaRxStatus :: rx_polarity [07:07] */
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK               0x0080
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN              0
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS               1
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT              7
 
 /* Rx0 :: anaRxStatus :: rxpol_flip [06:06] */
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                0x0040
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN               0
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                1
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT               6
 
 /* Rx0 :: anaRxStatus :: comma_mask [05:05] */
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK                0x0020
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN               0
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS                1
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT               5
 
 /* Rx0 :: anaRxStatus :: link_en_r [04:04] */
 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK                 0x0010
 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                0
 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS                 1
 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                4
 
 /* Rx0 :: anaRxStatus :: comma_adj_en [03:03] */
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK              0x0008
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN             0
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS              1
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT             3
 
 /* Rx0 :: anaRxStatus :: comma_adj_en_ext [02:02] */
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK          0x0004
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN         0
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS          1
 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT         2
 
 /* Rx0 :: anaRxStatus :: reserved1 [01:00] */
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK                 0x0003
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN                0
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS                 2
 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT                0
 
 
 /* union - case rxTestSel_1 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */
 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK                 0xffe0
 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN                0
 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS                 11
 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT                5
 
 /* Rx0 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK             0x0010
 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN            0
 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS             1
 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT            4
 
 /* Rx0 :: anaRxStatus :: freq_sel_PC [03:03] */
 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK               0x0008
 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN              0
 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS               1
 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT              3
 
 /* Rx0 :: anaRxStatus :: freq_sel_SM [02:02] */
 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK               0x0004
 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN              0
 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS               1
 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT              2
 
 /* Rx0 :: anaRxStatus :: integ_mode_SM [01:00] */
 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK             0x0003
 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN            0
 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS             2
 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT            0
 
 
 /* union - case scale_Status [15:00] */
 /* Rx0 :: anaRxStatus :: prop_scale [15:12] */
 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK               0xf000
 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN              0
 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS               4
 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT              12
 
 /* Rx0 :: anaRxStatus :: integ_scale [11:08] */
 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK              0x0f00
 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN             0
 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS              4
 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT             8
 
 /* Rx0 :: anaRxStatus :: prop_scale_acq [07:04] */
 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK           0x00f0
 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN          0
 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS           4
 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT          4
 
 /* Rx0 :: anaRxStatus :: integ_scale_acq [03:00] */
 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK          0x000f
 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN         0
 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS          4
 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT         0
 
 
 /* union - case adc_CdrStatus1 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:07] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK              0xff80
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS              9
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT             7
 
 /* Rx0 :: anaRxStatus :: rxMuxCkSel [06:06] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK             0x0040
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS             1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT            6
 
 /* Rx0 :: anaRxStatus :: glpbk_combo [05:05] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK            0x0020
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN           0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS            1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT           5
 
 /* Rx0 :: anaRxStatus :: clockSwitchSel [04:04] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK         0x0010
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN        0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS         1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT        4
 
 /* Rx0 :: anaRxStatus :: rxck_tst [03:03] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK               0x0008
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN              0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS               1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT              3
 
 /* Rx0 :: anaRxStatus :: rxck_i [02:02] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK                 0x0004
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS                 1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                2
 
 /* Rx0 :: anaRxStatus :: refclk [01:01] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK                 0x0002
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS                 1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                1
 
 /* Rx0 :: anaRxStatus :: pll_bypass [00:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK             0x0001
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS             1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT            0
 
 
 /* union - case adc_CdrStatus2 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:06] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK              0xffc0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS              10
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT             6
 
 /* Rx0 :: anaRxStatus :: rxMuxCkSel [05:05] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK             0x0020
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS             1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT            5
 
 /* Rx0 :: anaRxStatus :: rxSeqStart [04:04] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK             0x0010
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS             1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT            4
 
 /* Rx0 :: anaRxStatus :: reserved1 [03:01] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK              0x000e
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS              3
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT             1
 
 /* Rx0 :: anaRxStatus :: rxSeqDone [00:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK              0x0001
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS              1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT             0
 
 
 /* union - case adc_CdrStatus3 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:04] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK              0xfff0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS              12
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT             4
 
 /* Rx0 :: anaRxStatus :: rxSeqStart [03:03] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK             0x0008
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS             1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT            3
 
 /* Rx0 :: anaRxStatus :: reserved1 [02:01] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK              0x0006
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS              2
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT             1
 
 /* Rx0 :: anaRxStatus :: allow_increment_PC [00:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK     0x0001
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN    0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS     1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT    0
 
 
 /* union - case adc_CdrStatus4 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:08] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK              0xff00
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS              8
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT             8
 
 /* Rx0 :: anaRxStatus :: rx_pwrdn [07:07] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK               0x0080
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN              0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS               1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT              7
 
 /* Rx0 :: anaRxStatus :: freq_sel [06:06] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK               0x0040
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN              0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS               1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT              6
 
 /* Rx0 :: anaRxStatus :: pll_lock_rstb [05:05] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK          0x0020
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN         0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS          1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT         5
 
 /* Rx0 :: anaRxStatus :: pwrdn [04:04] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK                  0x0010
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                 0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS                  1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                 4
 
 /* Rx0 :: anaRxStatus :: reserved1 [03:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK              0x000f
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS              4
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT             0
 
 
 /* union - case adc_CdrStatus5 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK              0xffff
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS              16
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT             0
 
 
 /* union - case adc_CdrStatus6 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK              0xffe0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS              11
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT             5
 
 /* Rx0 :: anaRxStatus :: rx_reset [04:04] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK               0x0010
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN              0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS               1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT              4
 
 /* Rx0 :: anaRxStatus :: rx_pwrdn [03:03] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK               0x0008
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN              0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS               1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT              3
 
 /* Rx0 :: anaRxStatus :: reset_anlg [02:02] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK             0x0004
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS             1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT            2
 
 /* Rx0 :: anaRxStatus :: pwrdn_rx [01:01] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK               0x0002
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN              0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS               1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT              1
 
 /* Rx0 :: anaRxStatus :: pwrdn_pll [00:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK              0x0001
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS              1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT             0
 
 
 /* union - case adc_CdrStatus7e [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK             0xffe0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS             11
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT            5
 
 /* Rx0 :: anaRxStatus :: rxck0_even [04:04] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK            0x0010
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN           0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS            1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT           4
 
 /* Rx0 :: anaRxStatus :: rxck1_even [03:03] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK            0x0008
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN           0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS            1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT           3
 
 /* Rx0 :: anaRxStatus :: comdet_even [02:02] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK           0x0004
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN          0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS           1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT          2
 
 /* Rx0 :: anaRxStatus :: en_cdet_even [01:01] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK          0x0002
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN         0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS          1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT         1
 
 /* Rx0 :: anaRxStatus :: comma_adj_en_even [00:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK     0x0001
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN    0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS     1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT    0
 
 
 /* union - case adc_CdrStatus7o [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK             0xffe0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS             11
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT            5
 
 /* Rx0 :: anaRxStatus :: rxck0_odd [04:04] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK             0x0010
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS             1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT            4
 
 /* Rx0 :: anaRxStatus :: rxck1_odd [03:03] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK             0x0008
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS             1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT            3
 
 /* Rx0 :: anaRxStatus :: comdet_odd [02:02] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK            0x0004
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN           0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS            1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT           2
 
 /* Rx0 :: anaRxStatus :: en_cdet_odd [01:01] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK           0x0002
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN          0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS           1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT          1
 
 /* Rx0 :: anaRxStatus :: comma_adj_en_odd [00:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK      0x0001
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN     0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS      1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT     0
 
 
 /* union - case adc_CdrStatus8 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:01] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK              0xfffe
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS              15
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT             1
 
 /* Rx0 :: anaRxStatus :: sigdet [00:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK                 0x0001
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS                 1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                0
 
 
 /* union - case adc_CdrStatus9 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK              0xffff
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS              16
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT             0
 
 
 /* union - case adc_CdrStatus10 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:07] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK             0xff80
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS             9
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT            7
 
 /* Rx0 :: anaRxStatus :: prbs_en [06:06] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK               0x0040
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN              0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS               1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT              6
 
 /* Rx0 :: anaRxStatus :: rstb_tst [05:05] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK              0x0020
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN             0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS              1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT             5
 
 /* Rx0 :: anaRxStatus :: reserved1 [04:04] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK             0x0010
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS             1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT            4
 
 /* Rx0 :: anaRxStatus :: prbs_state [03:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK            0x000f
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN           0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS            4
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT           0
 
 
 /* union - case adc_CdrStatus11 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK             0xffff
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS             16
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT            0
 
 
 /* union - case adc_CdrStatus12_1 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:06] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK           0xffc0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN          0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS           10
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT          6
 
 /* Rx0 :: anaRxStatus :: enable4 [05:05] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK             0x0020
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN            0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS             1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT            5
 
 /* Rx0 :: anaRxStatus :: radr_test [04:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK           0x001f
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN          0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS           5
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT          0
 
 
 /* union - case adc_CdrStatus12_2 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK           0xffe0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN          0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS           11
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT          5
 
 /* Rx0 :: anaRxStatus :: wadr_test [04:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK           0x001f
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN          0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS           5
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT          0
 
 
 /* union - case adc_CdrStatus12_3 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:06] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK           0xffc0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN          0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS           10
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT          6
 
 /* Rx0 :: anaRxStatus :: rxck_66B_tmux [05:05] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK       0x0020
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN      0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS       1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT      5
 
 /* Rx0 :: anaRxStatus :: rstb_66B [04:04] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK            0x0010
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN           0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS            1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT           4
 
 /* Rx0 :: anaRxStatus :: prstb_66B_mux [03:03] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK       0x0008
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN      0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS       1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT      3
 
 /* Rx0 :: anaRxStatus :: rxck_i66_tmux [02:02] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK       0x0004
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN      0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS       1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT      2
 
 /* Rx0 :: anaRxStatus :: rstb_i66 [01:01] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK            0x0002
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN           0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS            1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT           1
 
 /* Rx0 :: anaRxStatus :: prstb_i66_mux [00:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK       0x0001
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN      0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS       1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT      0
 
 
 /* union - case adc_CdrStatus12_4 [15:00] */
 /* Rx0 :: anaRxStatus :: reserved0 [15:04] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK           0xfff0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN          0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS           12
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT          4
 
 /* Rx0 :: anaRxStatus :: rfifo_error_r [03:02] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK       0x000c
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN      0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS       2
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT      2
 
 /* Rx0 :: anaRxStatus :: rfifo_unflow [01:01] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK        0x0002
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN       0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS        1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT       1
 
 /* Rx0 :: anaRxStatus :: rfifo_ovflow [00:00] */
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK        0x0001
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN       0
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS        1
 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT       0
 
 
 /* union - case integ_Status [15:00] */
 /* Rx0 :: anaRxStatus :: integ_status [15:00] */
 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK             0xffff
 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN            0
 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS             16
 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT            0
 
 
 /* union - case vco_Status [15:00] */
 /* Rx0 :: anaRxStatus :: vco_status [15:00] */
 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK                 0xffff
 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN                0
 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS                 16
 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT                0
 
 
 /* union - case prbs_Status [15:00] */
 /* Rx0 :: anaRxStatus :: prbs_lock [15:15] */
 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK                 0x8000
 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                0
 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS                 1
 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                15
 
 /* Rx0 :: anaRxStatus :: prbs_stky [14:14] */
 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK                 0x4000
 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN                0
 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS                 1
 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT                14
 
 /* Rx0 :: anaRxStatus :: ptbs_errors [13:00] */
 #define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK               0x3fff
 #define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN              0
 #define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS               14
 #define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT              0
 
 
 
 /****************************************************************************
  * Rx0 :: anaRxControl
  */
 /* Rx0 :: anaRxControl :: reserved0 [15:10] */
 #define RX0_ANARXCONTROL_RESERVED0_MASK                            0xfc00
 #define RX0_ANARXCONTROL_RESERVED0_ALIGN                           0
 #define RX0_ANARXCONTROL_RESERVED0_BITS                            6
 #define RX0_ANARXCONTROL_RESERVED0_SHIFT                           10
 
 /* Rx0 :: anaRxControl :: override_sigdet_en [09:09] */
 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK                   0x0200
 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN                  0
 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS                   1
 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT                  9
 
 /* Rx0 :: anaRxControl :: override_sigdet_val [08:08] */
 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK                  0x0100
 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN                 0
 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS                  1
 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT                 8
 
 /* Rx0 :: anaRxControl :: reserved1 [07:03] */
 #define RX0_ANARXCONTROL_RESERVED1_MASK                            0x00f8
 #define RX0_ANARXCONTROL_RESERVED1_ALIGN                           0
 #define RX0_ANARXCONTROL_RESERVED1_BITS                            5
 #define RX0_ANARXCONTROL_RESERVED1_SHIFT                           3
 
 /* Rx0 :: anaRxControl :: status_sel [02:00] */
 #define RX0_ANARXCONTROL_STATUS_SEL_MASK                           0x0007
 #define RX0_ANARXCONTROL_STATUS_SEL_ALIGN                          0
 #define RX0_ANARXCONTROL_STATUS_SEL_BITS                           3
 #define RX0_ANARXCONTROL_STATUS_SEL_SHIFT                          0
 #define RX0_ANARXCONTROL_STATUS_SEL_sigdetStatus                   0
 #define RX0_ANARXCONTROL_STATUS_SEL_syncStatus                     1
 #define RX0_ANARXCONTROL_STATUS_SEL_rxTestSel                      2
 #define RX0_ANARXCONTROL_STATUS_SEL_scaleStatus                    3
 #define RX0_ANARXCONTROL_STATUS_SEL_adcCdrStatus                   4
 #define RX0_ANARXCONTROL_STATUS_SEL_integStatus                    5
 #define RX0_ANARXCONTROL_STATUS_SEL_vcoStatus                      6
 #define RX0_ANARXCONTROL_STATUS_SEL_prbsStatus                     7
 
 
 /****************************************************************************
  * Rx0 :: anaRxTest
  */
 /* Rx0 :: anaRxTest :: sigdet_mux_SM [15:12] */
 #define RX0_ANARXTEST_SIGDET_MUX_SM_MASK                           0xf000
 #define RX0_ANARXTEST_SIGDET_MUX_SM_ALIGN                          0
 #define RX0_ANARXTEST_SIGDET_MUX_SM_BITS                           4
 #define RX0_ANARXTEST_SIGDET_MUX_SM_SHIFT                          12
 
 /* Rx0 :: anaRxTest :: reserved0 [11:09] */
 #define RX0_ANARXTEST_RESERVED0_MASK                               0x0e00
 #define RX0_ANARXTEST_RESERVED0_ALIGN                              0
 #define RX0_ANARXTEST_RESERVED0_BITS                               3
 #define RX0_ANARXTEST_RESERVED0_SHIFT                              9
 
 /* Rx0 :: anaRxTest :: tpctrl_SM [08:04] */
 #define RX0_ANARXTEST_TPCTRL_SM_MASK                               0x01f0
 #define RX0_ANARXTEST_TPCTRL_SM_ALIGN                              0
 #define RX0_ANARXTEST_TPCTRL_SM_BITS                               5
 #define RX0_ANARXTEST_TPCTRL_SM_SHIFT                              4
 
 /* Rx0 :: anaRxTest :: testMuxSelect_SM [03:00] */
 #define RX0_ANARXTEST_TESTMUXSELECT_SM_MASK                        0x000f
 #define RX0_ANARXTEST_TESTMUXSELECT_SM_ALIGN                       0
 #define RX0_ANARXTEST_TESTMUXSELECT_SM_BITS                        4
 #define RX0_ANARXTEST_TESTMUXSELECT_SM_SHIFT                       0
 
 
 /****************************************************************************
  * Rx0 :: anaRxControl1G
  */
 /* Rx0 :: anaRxControl1G :: fpat_md [15:15] */
 #define RX0_ANARXCONTROL1G_FPAT_MD_MASK                            0x8000
 #define RX0_ANARXCONTROL1G_FPAT_MD_ALIGN                           0
 #define RX0_ANARXCONTROL1G_FPAT_MD_BITS                            1
 #define RX0_ANARXCONTROL1G_FPAT_MD_SHIFT                           15
 
 /* Rx0 :: anaRxControl1G :: pkt_count_en [14:14] */
 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_MASK                       0x4000
 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN                      0
 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_BITS                       1
 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT                      14
 
 /* Rx0 :: anaRxControl1G :: staMuxRegDis [13:13] */
 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_MASK                       0x2000
 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_ALIGN                      0
 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_BITS                       1
 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_SHIFT                      13
 
 /* Rx0 :: anaRxControl1G :: prbs_clr_dis [12:12] */
 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_MASK                       0x1000
 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN                      0
 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_BITS                       1
 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT                      12
 
 /* Rx0 :: anaRxControl1G :: rxd_dec_sel [11:11] */
 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_MASK                        0x0800
 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN                       0
 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_BITS                        1
 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT                       11
 
 /* Rx0 :: anaRxControl1G :: cgbad_tst [10:10] */
 #define RX0_ANARXCONTROL1G_CGBAD_TST_MASK                          0x0400
 #define RX0_ANARXCONTROL1G_CGBAD_TST_ALIGN                         0
 #define RX0_ANARXCONTROL1G_CGBAD_TST_BITS                          1
 #define RX0_ANARXCONTROL1G_CGBAD_TST_SHIFT                         10
 
 /* Rx0 :: anaRxControl1G :: Emon_en [09:09] */
 #define RX0_ANARXCONTROL1G_EMON_EN_MASK                            0x0200
 #define RX0_ANARXCONTROL1G_EMON_EN_ALIGN                           0
 #define RX0_ANARXCONTROL1G_EMON_EN_BITS                            1
 #define RX0_ANARXCONTROL1G_EMON_EN_SHIFT                           9
 
 /* Rx0 :: anaRxControl1G :: prbs_en [08:08] */
 #define RX0_ANARXCONTROL1G_PRBS_EN_MASK                            0x0100
 #define RX0_ANARXCONTROL1G_PRBS_EN_ALIGN                           0
 #define RX0_ANARXCONTROL1G_PRBS_EN_BITS                            1
 #define RX0_ANARXCONTROL1G_PRBS_EN_SHIFT                           8
 
 /* Rx0 :: anaRxControl1G :: cgbad_en [07:07] */
 #define RX0_ANARXCONTROL1G_CGBAD_EN_MASK                           0x0080
 #define RX0_ANARXCONTROL1G_CGBAD_EN_ALIGN                          0
 #define RX0_ANARXCONTROL1G_CGBAD_EN_BITS                           1
 #define RX0_ANARXCONTROL1G_CGBAD_EN_SHIFT                          7
 
 /* Rx0 :: anaRxControl1G :: cstretch [06:06] */
 #define RX0_ANARXCONTROL1G_CSTRETCH_MASK                           0x0040
 #define RX0_ANARXCONTROL1G_CSTRETCH_ALIGN                          0
 #define RX0_ANARXCONTROL1G_CSTRETCH_BITS                           1
 #define RX0_ANARXCONTROL1G_CSTRETCH_SHIFT                          6
 
 /* Rx0 :: anaRxControl1G :: comma_low_byte_SM [05:05] */
 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK                  0x0020
 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN                 0
 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS                  1
 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT                 5
 
 /* Rx0 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */
 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK               0x0010
 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN              0
 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS               1
 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT              4
 
 /* Rx0 :: anaRxControl1G :: reserved0 [03:02] */
 #define RX0_ANARXCONTROL1G_RESERVED0_MASK                          0x000c
 #define RX0_ANARXCONTROL1G_RESERVED0_ALIGN                         0
 #define RX0_ANARXCONTROL1G_RESERVED0_BITS                          2
 #define RX0_ANARXCONTROL1G_RESERVED0_SHIFT                         2
 
 /* Rx0 :: anaRxControl1G :: freq_sel_force [01:01] */
 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK                     0x0002
 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN                    0
 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS                     1
 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT                    1
 
 /* Rx0 :: anaRxControl1G :: freq_sel [00:00] */
 #define RX0_ANARXCONTROL1G_FREQ_SEL_MASK                           0x0001
 #define RX0_ANARXCONTROL1G_FREQ_SEL_ALIGN                          0
 #define RX0_ANARXCONTROL1G_FREQ_SEL_BITS                           1
 #define RX0_ANARXCONTROL1G_FREQ_SEL_SHIFT                          0
 
 
 /****************************************************************************
  * Rx0 :: anaRxControlPci
  */
 /* Rx0 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK                0x8000
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN               0
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS                1
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT               15
 
 /* Rx0 :: anaRxControlPci :: comma_mask_force_r [14:14] */
 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK                0x4000
 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN               0
 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS                1
 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT               14
 
 /* Rx0 :: anaRxControlPci :: comma_mask_r [13:13] */
 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_MASK                      0x2000
 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN                     0
 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_BITS                      1
 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT                     13
 
 /* Rx0 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK         0x1000
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN        0
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS         1
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT        12
 
 /* Rx0 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK            0x0800
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN           0
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS            1
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT           11
 
 /* Rx0 :: anaRxControlPci :: sync_status_force_r [10:10] */
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK               0x0400
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN              0
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS               1
 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT              10
 
 /* Rx0 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK         0x0200
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN        0
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS         1
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT        9
 
 /* Rx0 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK        0x0100
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN       0
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS        1
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT       8
 
 /* Rx0 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK           0x0080
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN          0
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS           1
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT          7
 
 /* Rx0 :: anaRxControlPci :: comma_adj_en_r [06:06] */
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK                    0x0040
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN                   0
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS                    1
 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT                   6
 
 /* Rx0 :: anaRxControlPci :: link_en_force_SM [05:05] */
 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK                  0x0020
 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN                 0
 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS                  1
 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT                 5
 
 /* Rx0 :: anaRxControlPci :: link_en_r [04:04] */
 #define RX0_ANARXCONTROLPCI_LINK_EN_R_MASK                         0x0010
 #define RX0_ANARXCONTROLPCI_LINK_EN_R_ALIGN                        0
 #define RX0_ANARXCONTROLPCI_LINK_EN_R_BITS                         1
 #define RX0_ANARXCONTROLPCI_LINK_EN_R_SHIFT                        4
 
 /* Rx0 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK              0x0008
 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN             0
 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS              1
 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT             3
 
 /* Rx0 :: anaRxControlPci :: rx_polarity_r [02:02] */
 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_MASK                     0x0004
 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN                    0
 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_BITS                     1
 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT                    2
 
 /* Rx0 :: anaRxControlPci :: integ_mode_SM [01:00] */
 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_MASK                     0x0003
 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN                    0
 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_BITS                     2
 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT                    0
 
 
 /****************************************************************************
  * Rx0 :: anaRxAstatus
  */
 /* Rx0 :: anaRxAstatus :: sigdet [15:15] */
 #define RX0_ANARXASTATUS_SIGDET_MASK                               0x8000
 #define RX0_ANARXASTATUS_SIGDET_ALIGN                              0
 #define RX0_ANARXASTATUS_SIGDET_BITS                               1
 #define RX0_ANARXASTATUS_SIGDET_SHIFT                              15
 
 /* Rx0 :: anaRxAstatus :: rx_pf [14:11] */
 #define RX0_ANARXASTATUS_RX_PF_MASK                                0x7800
 #define RX0_ANARXASTATUS_RX_PF_ALIGN                               0
 #define RX0_ANARXASTATUS_RX_PF_BITS                                4
 #define RX0_ANARXASTATUS_RX_PF_SHIFT                               11
 
 /* Rx0 :: anaRxAstatus :: tap1_dfe_gray [10:05] */
 #define RX0_ANARXASTATUS_TAP1_DFE_GRAY_MASK                        0x07e0
 #define RX0_ANARXASTATUS_TAP1_DFE_GRAY_ALIGN                       0
 #define RX0_ANARXASTATUS_TAP1_DFE_GRAY_BITS                        6
 #define RX0_ANARXASTATUS_TAP1_DFE_GRAY_SHIFT                       5
 
 /* Rx0 :: anaRxAstatus :: vga [04:00] */
 #define RX0_ANARXASTATUS_VGA_MASK                                  0x001f
 #define RX0_ANARXASTATUS_VGA_ALIGN                                 0
 #define RX0_ANARXASTATUS_VGA_BITS                                  5
 #define RX0_ANARXASTATUS_VGA_SHIFT                                 0
 
 
 /****************************************************************************
  * Rx0 :: anaRxAControl1
  */
 /* Rx0 :: anaRxAControl1 :: imode_vcm [15:15] */
 #define RX0_ANARXACONTROL1_IMODE_VCM_MASK                          0x8000
 #define RX0_ANARXACONTROL1_IMODE_VCM_ALIGN                         0
 #define RX0_ANARXACONTROL1_IMODE_VCM_BITS                          1
 #define RX0_ANARXACONTROL1_IMODE_VCM_SHIFT                         15
 
 /* Rx0 :: anaRxAControl1 :: imin_vcm [14:14] */
 #define RX0_ANARXACONTROL1_IMIN_VCM_MASK                           0x4000
 #define RX0_ANARXACONTROL1_IMIN_VCM_ALIGN                          0
 #define RX0_ANARXACONTROL1_IMIN_VCM_BITS                           1
 #define RX0_ANARXACONTROL1_IMIN_VCM_SHIFT                          14
 
 /* Rx0 :: anaRxAControl1 :: imax_sigdet [13:13] */
 #define RX0_ANARXACONTROL1_IMAX_SIGDET_MASK                        0x2000
 #define RX0_ANARXACONTROL1_IMAX_SIGDET_ALIGN                       0
 #define RX0_ANARXACONTROL1_IMAX_SIGDET_BITS                        1
 #define RX0_ANARXACONTROL1_IMAX_SIGDET_SHIFT                       13
 
 /* Rx0 :: anaRxAControl1 :: imode_sigdet [12:12] */
 #define RX0_ANARXACONTROL1_IMODE_SIGDET_MASK                       0x1000
 #define RX0_ANARXACONTROL1_IMODE_SIGDET_ALIGN                      0
 #define RX0_ANARXACONTROL1_IMODE_SIGDET_BITS                       1
 #define RX0_ANARXACONTROL1_IMODE_SIGDET_SHIFT                      12
 
 /* Rx0 :: anaRxAControl1 :: imin_sigdet [11:11] */
 #define RX0_ANARXACONTROL1_IMIN_SIGDET_MASK                        0x0800
 #define RX0_ANARXACONTROL1_IMIN_SIGDET_ALIGN                       0
 #define RX0_ANARXACONTROL1_IMIN_SIGDET_BITS                        1
 #define RX0_ANARXACONTROL1_IMIN_SIGDET_SHIFT                       11
 
 /* Rx0 :: anaRxAControl1 :: refh_rx [10:10] */
 #define RX0_ANARXACONTROL1_REFH_RX_MASK                            0x0400
 #define RX0_ANARXACONTROL1_REFH_RX_ALIGN                           0
 #define RX0_ANARXACONTROL1_REFH_RX_BITS                            1
 #define RX0_ANARXACONTROL1_REFH_RX_SHIFT                           10
 
 /* Rx0 :: anaRxAControl1 :: refl_rx [09:09] */
 #define RX0_ANARXACONTROL1_REFL_RX_MASK                            0x0200
 #define RX0_ANARXACONTROL1_REFL_RX_ALIGN                           0
 #define RX0_ANARXACONTROL1_REFL_RX_BITS                            1
 #define RX0_ANARXACONTROL1_REFL_RX_SHIFT                           9
 
 /* Rx0 :: anaRxAControl1 :: tport_en [08:08] */
 #define RX0_ANARXACONTROL1_TPORT_EN_MASK                           0x0100
 #define RX0_ANARXACONTROL1_TPORT_EN_ALIGN                          0
 #define RX0_ANARXACONTROL1_TPORT_EN_BITS                           1
 #define RX0_ANARXACONTROL1_TPORT_EN_SHIFT                          8
 
 /* Rx0 :: anaRxAControl1 :: vddrb_bgb [07:07] */
 #define RX0_ANARXACONTROL1_VDDRB_BGB_MASK                          0x0080
 #define RX0_ANARXACONTROL1_VDDRB_BGB_ALIGN                         0
 #define RX0_ANARXACONTROL1_VDDRB_BGB_BITS                          1
 #define RX0_ANARXACONTROL1_VDDRB_BGB_SHIFT                         7
 
 /* Rx0 :: anaRxAControl1 :: sig_pwrdn [06:06] */
 #define RX0_ANARXACONTROL1_SIG_PWRDN_MASK                          0x0040
 #define RX0_ANARXACONTROL1_SIG_PWRDN_ALIGN                         0
 #define RX0_ANARXACONTROL1_SIG_PWRDN_BITS                          1
 #define RX0_ANARXACONTROL1_SIG_PWRDN_SHIFT                         6
 
 /* Rx0 :: anaRxAControl1 :: offset_ctrl [05:03] */
 #define RX0_ANARXACONTROL1_OFFSET_CTRL_MASK                        0x0038
 #define RX0_ANARXACONTROL1_OFFSET_CTRL_ALIGN                       0
 #define RX0_ANARXACONTROL1_OFFSET_CTRL_BITS                        3
 #define RX0_ANARXACONTROL1_OFFSET_CTRL_SHIFT                       3
 
 /* Rx0 :: anaRxAControl1 :: offset_sel [02:02] */
 #define RX0_ANARXACONTROL1_OFFSET_SEL_MASK                         0x0004
 #define RX0_ANARXACONTROL1_OFFSET_SEL_ALIGN                        0
 #define RX0_ANARXACONTROL1_OFFSET_SEL_BITS                         1
 #define RX0_ANARXACONTROL1_OFFSET_SEL_SHIFT                        2
 
 /* Rx0 :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */
 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY1_MASK                    0x0002
 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN                   0
 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY1_BITS                    1
 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT                   1
 
 /* Rx0 :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */
 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY0_MASK                    0x0001
 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN                   0
 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY0_BITS                    1
 #define RX0_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT                   0
 
 
 /****************************************************************************
  * Rx0 :: anaRxAControl2
  */
 /* Rx0 :: anaRxAControl2 :: imax_ctat [15:15] */
 #define RX0_ANARXACONTROL2_IMAX_CTAT_MASK                          0x8000
 #define RX0_ANARXACONTROL2_IMAX_CTAT_ALIGN                         0
 #define RX0_ANARXACONTROL2_IMAX_CTAT_BITS                          1
 #define RX0_ANARXACONTROL2_IMAX_CTAT_SHIFT                         15
 
 /* Rx0 :: anaRxAControl2 :: imode_ctat [14:14] */
 #define RX0_ANARXACONTROL2_IMODE_CTAT_MASK                         0x4000
 #define RX0_ANARXACONTROL2_IMODE_CTAT_ALIGN                        0
 #define RX0_ANARXACONTROL2_IMODE_CTAT_BITS                         1
 #define RX0_ANARXACONTROL2_IMODE_CTAT_SHIFT                        14
 
 /* Rx0 :: anaRxAControl2 :: imin_ctat [13:13] */
 #define RX0_ANARXACONTROL2_IMIN_CTAT_MASK                          0x2000
 #define RX0_ANARXACONTROL2_IMIN_CTAT_ALIGN                         0
 #define RX0_ANARXACONTROL2_IMIN_CTAT_BITS                          1
 #define RX0_ANARXACONTROL2_IMIN_CTAT_SHIFT                         13
 
 /* Rx0 :: anaRxAControl2 :: imax_eqfl [12:12] */
 #define RX0_ANARXACONTROL2_IMAX_EQFL_MASK                          0x1000
 #define RX0_ANARXACONTROL2_IMAX_EQFL_ALIGN                         0
 #define RX0_ANARXACONTROL2_IMAX_EQFL_BITS                          1
 #define RX0_ANARXACONTROL2_IMAX_EQFL_SHIFT                         12
 
 /* Rx0 :: anaRxAControl2 :: imode_eqfl [11:11] */
 #define RX0_ANARXACONTROL2_IMODE_EQFL_MASK                         0x0800
 #define RX0_ANARXACONTROL2_IMODE_EQFL_ALIGN                        0
 #define RX0_ANARXACONTROL2_IMODE_EQFL_BITS                         1
 #define RX0_ANARXACONTROL2_IMODE_EQFL_SHIFT                        11
 
 /* Rx0 :: anaRxAControl2 :: imin_eqfl [10:10] */
 #define RX0_ANARXACONTROL2_IMIN_EQFL_MASK                          0x0400
 #define RX0_ANARXACONTROL2_IMIN_EQFL_ALIGN                         0
 #define RX0_ANARXACONTROL2_IMIN_EQFL_BITS                          1
 #define RX0_ANARXACONTROL2_IMIN_EQFL_SHIFT                         10
 
 /* Rx0 :: anaRxAControl2 :: imax_dfesum [09:09] */
 #define RX0_ANARXACONTROL2_IMAX_DFESUM_MASK                        0x0200
 #define RX0_ANARXACONTROL2_IMAX_DFESUM_ALIGN                       0
 #define RX0_ANARXACONTROL2_IMAX_DFESUM_BITS                        1
 #define RX0_ANARXACONTROL2_IMAX_DFESUM_SHIFT                       9
 
 /* Rx0 :: anaRxAControl2 :: imode_dfesum [08:08] */
 #define RX0_ANARXACONTROL2_IMODE_DFESUM_MASK                       0x0100
 #define RX0_ANARXACONTROL2_IMODE_DFESUM_ALIGN                      0
 #define RX0_ANARXACONTROL2_IMODE_DFESUM_BITS                       1
 #define RX0_ANARXACONTROL2_IMODE_DFESUM_SHIFT                      8
 
 /* Rx0 :: anaRxAControl2 :: imin_dfesum [07:07] */
 #define RX0_ANARXACONTROL2_IMIN_DFESUM_MASK                        0x0080
 #define RX0_ANARXACONTROL2_IMIN_DFESUM_ALIGN                       0
 #define RX0_ANARXACONTROL2_IMIN_DFESUM_BITS                        1
 #define RX0_ANARXACONTROL2_IMIN_DFESUM_SHIFT                       7
 
 /* Rx0 :: anaRxAControl2 :: imax_vga [06:06] */
 #define RX0_ANARXACONTROL2_IMAX_VGA_MASK                           0x0040
 #define RX0_ANARXACONTROL2_IMAX_VGA_ALIGN                          0
 #define RX0_ANARXACONTROL2_IMAX_VGA_BITS                           1
 #define RX0_ANARXACONTROL2_IMAX_VGA_SHIFT                          6
 
 /* Rx0 :: anaRxAControl2 :: imode_vga [05:05] */
 #define RX0_ANARXACONTROL2_IMODE_VGA_MASK                          0x0020
 #define RX0_ANARXACONTROL2_IMODE_VGA_ALIGN                         0
 #define RX0_ANARXACONTROL2_IMODE_VGA_BITS                          1
 #define RX0_ANARXACONTROL2_IMODE_VGA_SHIFT                         5
 
 /* Rx0 :: anaRxAControl2 :: imin_vga [04:04] */
 #define RX0_ANARXACONTROL2_IMIN_VGA_MASK                           0x0010
 #define RX0_ANARXACONTROL2_IMIN_VGA_ALIGN                          0
 #define RX0_ANARXACONTROL2_IMIN_VGA_BITS                           1
 #define RX0_ANARXACONTROL2_IMIN_VGA_SHIFT                          4
 
 /* Rx0 :: anaRxAControl2 :: imax_interp [03:03] */
 #define RX0_ANARXACONTROL2_IMAX_INTERP_MASK                        0x0008
 #define RX0_ANARXACONTROL2_IMAX_INTERP_ALIGN                       0
 #define RX0_ANARXACONTROL2_IMAX_INTERP_BITS                        1
 #define RX0_ANARXACONTROL2_IMAX_INTERP_SHIFT                       3
 
 /* Rx0 :: anaRxAControl2 :: imode_interp [02:02] */
 #define RX0_ANARXACONTROL2_IMODE_INTERP_MASK                       0x0004
 #define RX0_ANARXACONTROL2_IMODE_INTERP_ALIGN                      0
 #define RX0_ANARXACONTROL2_IMODE_INTERP_BITS                       1
 #define RX0_ANARXACONTROL2_IMODE_INTERP_SHIFT                      2
 
 /* Rx0 :: anaRxAControl2 :: imin_interp [01:01] */
 #define RX0_ANARXACONTROL2_IMIN_INTERP_MASK                        0x0002
 #define RX0_ANARXACONTROL2_IMIN_INTERP_ALIGN                       0
 #define RX0_ANARXACONTROL2_IMIN_INTERP_BITS                        1
 #define RX0_ANARXACONTROL2_IMIN_INTERP_SHIFT                       1
 
 /* Rx0 :: anaRxAControl2 :: imax_vcm [00:00] */
 #define RX0_ANARXACONTROL2_IMAX_VCM_MASK                           0x0001
 #define RX0_ANARXACONTROL2_IMAX_VCM_ALIGN                          0
 #define RX0_ANARXACONTROL2_IMAX_VCM_BITS                           1
 #define RX0_ANARXACONTROL2_IMAX_VCM_SHIFT                          0
 
 
 /****************************************************************************
  * Rx0 :: anaRxAControl3
  */
 /* Rx0 :: anaRxAControl3 :: en_clk16 [15:15] */
 #define RX0_ANARXACONTROL3_EN_CLK16_MASK                           0x8000
 #define RX0_ANARXACONTROL3_EN_CLK16_ALIGN                          0
 #define RX0_ANARXACONTROL3_EN_CLK16_BITS                           1
 #define RX0_ANARXACONTROL3_EN_CLK16_SHIFT                          15
 
 /* Rx0 :: anaRxAControl3 :: en_clk33 [14:14] */
 #define RX0_ANARXACONTROL3_EN_CLK33_MASK                           0x4000
 #define RX0_ANARXACONTROL3_EN_CLK33_ALIGN                          0
 #define RX0_ANARXACONTROL3_EN_CLK33_BITS                           1
 #define RX0_ANARXACONTROL3_EN_CLK33_SHIFT                          14
 
 /* Rx0 :: anaRxAControl3 :: en_vcctrl [13:13] */
 #define RX0_ANARXACONTROL3_EN_VCCTRL_MASK                          0x2000
 #define RX0_ANARXACONTROL3_EN_VCCTRL_ALIGN                         0
 #define RX0_ANARXACONTROL3_EN_VCCTRL_BITS                          1
 #define RX0_ANARXACONTROL3_EN_VCCTRL_SHIFT                         13
 
 /* Rx0 :: anaRxAControl3 :: sel_th4dfe1 [12:12] */
 #define RX0_ANARXACONTROL3_SEL_TH4DFE1_MASK                        0x1000
 #define RX0_ANARXACONTROL3_SEL_TH4DFE1_ALIGN                       0
 #define RX0_ANARXACONTROL3_SEL_TH4DFE1_BITS                        1
 #define RX0_ANARXACONTROL3_SEL_TH4DFE1_SHIFT                       12
 
 /* Rx0 :: anaRxAControl3 :: sel_th4dfe0 [11:11] */
 #define RX0_ANARXACONTROL3_SEL_TH4DFE0_MASK                        0x0800
 #define RX0_ANARXACONTROL3_SEL_TH4DFE0_ALIGN                       0
 #define RX0_ANARXACONTROL3_SEL_TH4DFE0_BITS                        1
 #define RX0_ANARXACONTROL3_SEL_TH4DFE0_SHIFT                       11
 
 /* Rx0 :: anaRxAControl3 :: selugbw1 [10:10] */
 #define RX0_ANARXACONTROL3_SELUGBW1_MASK                           0x0400
 #define RX0_ANARXACONTROL3_SELUGBW1_ALIGN                          0
 #define RX0_ANARXACONTROL3_SELUGBW1_BITS                           1
 #define RX0_ANARXACONTROL3_SELUGBW1_SHIFT                          10
 
 /* Rx0 :: anaRxAControl3 :: selugbw0 [09:09] */
 #define RX0_ANARXACONTROL3_SELUGBW0_MASK                           0x0200
 #define RX0_ANARXACONTROL3_SELUGBW0_ALIGN                          0
 #define RX0_ANARXACONTROL3_SELUGBW0_BITS                           1
 #define RX0_ANARXACONTROL3_SELUGBW0_SHIFT                          9
 
 /* Rx0 :: anaRxAControl3 :: imax_dfetap [08:08] */
 #define RX0_ANARXACONTROL3_IMAX_DFETAP_MASK                        0x0100
 #define RX0_ANARXACONTROL3_IMAX_DFETAP_ALIGN                       0
 #define RX0_ANARXACONTROL3_IMAX_DFETAP_BITS                        1
 #define RX0_ANARXACONTROL3_IMAX_DFETAP_SHIFT                       8
 
 /* Rx0 :: anaRxAControl3 :: imode_dfetap [07:07] */
 #define RX0_ANARXACONTROL3_IMODE_DFETAP_MASK                       0x0080
 #define RX0_ANARXACONTROL3_IMODE_DFETAP_ALIGN                      0
 #define RX0_ANARXACONTROL3_IMODE_DFETAP_BITS                       1
 #define RX0_ANARXACONTROL3_IMODE_DFETAP_SHIFT                      7
 
 /* Rx0 :: anaRxAControl3 :: imin_dfetap [06:06] */
 #define RX0_ANARXACONTROL3_IMIN_DFETAP_MASK                        0x0040
 #define RX0_ANARXACONTROL3_IMIN_DFETAP_ALIGN                       0
 #define RX0_ANARXACONTROL3_IMIN_DFETAP_BITS                        1
 #define RX0_ANARXACONTROL3_IMIN_DFETAP_SHIFT                       6
 
 /* Rx0 :: anaRxAControl3 :: imax_slcd2c [05:05] */
 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_MASK                        0x0020
 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_ALIGN                       0
 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_BITS                        1
 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_SHIFT                       5
 
 /* Rx0 :: anaRxAControl3 :: imode_slcd2c [04:04] */
 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_MASK                       0x0010
 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_ALIGN                      0
 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_BITS                       1
 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_SHIFT                      4
 
 /* Rx0 :: anaRxAControl3 :: imin_slcd2c [03:03] */
 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_MASK                        0x0008
 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_ALIGN                       0
 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_BITS                        1
 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_SHIFT                       3
 
 /* Rx0 :: anaRxAControl3 :: imax_dfevref [02:02] */
 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_MASK                       0x0004
 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_ALIGN                      0
 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_BITS                       1
 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_SHIFT                      2
 
 /* Rx0 :: anaRxAControl3 :: imode_dfevref [01:01] */
 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_MASK                      0x0002
 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_ALIGN                     0
 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_BITS                      1
 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_SHIFT                     1
 
 /* Rx0 :: anaRxAControl3 :: imin_dfevref [00:00] */
 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_MASK                       0x0001
 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_ALIGN                      0
 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_BITS                       1
 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_SHIFT                      0
 
 
 /****************************************************************************
  * Warpcore_USER_Rx1
  */
 /****************************************************************************
  * Rx1 :: anaRxStatus
  */
 /* union - case sigdet_Status [15:00] */
 /* Rx1 :: anaRxStatus :: cx4_sigdet [15:15] */
 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK              0x8000
 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN             0
 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS              1
 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT             15
 
 /* Rx1 :: anaRxStatus :: reserved0 [14:13] */
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK               0x6000
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN              0
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS               2
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT              13
 
 /* Rx1 :: anaRxStatus :: rxSeqDone [12:12] */
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK               0x1000
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN              0
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS               1
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT              12
 
 /* Rx1 :: anaRxStatus :: rx_sigdet_ll [11:11] */
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK            0x0800
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN           0
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS            1
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT           11
 
 /* Rx1 :: anaRxStatus :: cs4_sigdet_ll [10:10] */
 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK           0x0400
 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN          0
 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS           1
 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT          10
 
 /* Rx1 :: anaRxStatus :: rx_reset [09:09] */
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK                0x0200
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN               0
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS                1
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT               9
 
 /* Rx1 :: anaRxStatus :: rx_pwrdn [08:08] */
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK                0x0100
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN               0
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS                1
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT               8
 
 /* Rx1 :: anaRxStatus :: reserved1 [07:00] */
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK               0x00ff
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN              0
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS               8
 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT              0
 
 
 /* union - case sync_Status [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:11] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK                 0xf800
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN                0
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS                 5
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT                11
 
 /* Rx1 :: anaRxStatus :: test_acq_en [10:10] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK               0x0400
 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN              0
 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS               1
 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT              10
 
 /* Rx1 :: anaRxStatus :: reserved1 [09:09] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK                 0x0200
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN                0
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS                 1
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT                9
 
 /* Rx1 :: anaRxStatus :: rxSeqStart [08:08] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK                0x0100
 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN               0
 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS                1
 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT               8
 
 /* Rx1 :: anaRxStatus :: mux_comadj_sync_status [07:07] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK    0x0080
 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN   0
 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS    1
 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT   7
 
 /* Rx1 :: anaRxStatus :: sync_status [06:06] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK               0x0040
 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN              0
 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS               1
 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT              6
 
 /* Rx1 :: anaRxStatus :: rx_sigdet [05:05] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK                 0x0020
 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN                0
 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS                 1
 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT                5
 
 /* Rx1 :: anaRxStatus :: reserved2 [04:03] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK                 0x0018
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN                0
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS                 2
 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT                3
 
 /* Rx1 :: anaRxStatus :: saturate_status [02:02] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK           0x0004
 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN          0
 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS           1
 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT          2
 
 /* Rx1 :: anaRxStatus :: cx4_sigdet [01:01] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK                0x0002
 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN               0
 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS                1
 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT               1
 
 /* Rx1 :: anaRxStatus :: rxSeqDone [00:00] */
 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK                 0x0001
 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN                0
 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS                 1
 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT                0
 
 
 /* union - case rxTestSel_0 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:10] */
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK                 0xfc00
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN                0
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS                 6
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT                10
 
 /* Rx1 :: anaRxStatus :: indck_mode_en [09:09] */
 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK             0x0200
 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN            0
 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS             1
 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT            9
 
 /* Rx1 :: anaRxStatus :: pci_mode_en [08:08] */
 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK               0x0100
 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN              0
 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS               1
 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT              8
 
 /* Rx1 :: anaRxStatus :: rx_polarity [07:07] */
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK               0x0080
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN              0
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS               1
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT              7
 
 /* Rx1 :: anaRxStatus :: rxpol_flip [06:06] */
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                0x0040
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN               0
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                1
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT               6
 
 /* Rx1 :: anaRxStatus :: comma_mask [05:05] */
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK                0x0020
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN               0
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS                1
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT               5
 
 /* Rx1 :: anaRxStatus :: link_en_r [04:04] */
 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK                 0x0010
 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                0
 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS                 1
 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                4
 
 /* Rx1 :: anaRxStatus :: comma_adj_en [03:03] */
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK              0x0008
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN             0
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS              1
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT             3
 
 /* Rx1 :: anaRxStatus :: comma_adj_en_ext [02:02] */
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK          0x0004
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN         0
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS          1
 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT         2
 
 /* Rx1 :: anaRxStatus :: reserved1 [01:00] */
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK                 0x0003
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN                0
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS                 2
 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT                0
 
 
 /* union - case rxTestSel_1 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */
 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK                 0xffe0
 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN                0
 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS                 11
 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT                5
 
 /* Rx1 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK             0x0010
 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN            0
 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS             1
 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT            4
 
 /* Rx1 :: anaRxStatus :: freq_sel_PC [03:03] */
 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK               0x0008
 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN              0
 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS               1
 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT              3
 
 /* Rx1 :: anaRxStatus :: freq_sel_SM [02:02] */
 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK               0x0004
 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN              0
 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS               1
 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT              2
 
 /* Rx1 :: anaRxStatus :: integ_mode_SM [01:00] */
 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK             0x0003
 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN            0
 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS             2
 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT            0
 
 
 /* union - case scale_Status [15:00] */
 /* Rx1 :: anaRxStatus :: prop_scale [15:12] */
 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK               0xf000
 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN              0
 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS               4
 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT              12
 
 /* Rx1 :: anaRxStatus :: integ_scale [11:08] */
 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK              0x0f00
 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN             0
 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS              4
 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT             8
 
 /* Rx1 :: anaRxStatus :: prop_scale_acq [07:04] */
 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK           0x00f0
 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN          0
 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS           4
 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT          4
 
 /* Rx1 :: anaRxStatus :: integ_scale_acq [03:00] */
 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK          0x000f
 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN         0
 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS          4
 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT         0
 
 
 /* union - case adc_CdrStatus1 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:07] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK              0xff80
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS              9
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT             7
 
 /* Rx1 :: anaRxStatus :: rxMuxCkSel [06:06] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK             0x0040
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS             1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT            6
 
 /* Rx1 :: anaRxStatus :: glpbk_combo [05:05] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK            0x0020
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN           0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS            1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT           5
 
 /* Rx1 :: anaRxStatus :: clockSwitchSel [04:04] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK         0x0010
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN        0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS         1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT        4
 
 /* Rx1 :: anaRxStatus :: rxck_tst [03:03] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK               0x0008
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN              0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS               1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT              3
 
 /* Rx1 :: anaRxStatus :: rxck_i [02:02] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK                 0x0004
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS                 1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                2
 
 /* Rx1 :: anaRxStatus :: refclk [01:01] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK                 0x0002
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS                 1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                1
 
 /* Rx1 :: anaRxStatus :: pll_bypass [00:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK             0x0001
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS             1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT            0
 
 
 /* union - case adc_CdrStatus2 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:06] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK              0xffc0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS              10
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT             6
 
 /* Rx1 :: anaRxStatus :: rxMuxCkSel [05:05] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK             0x0020
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS             1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT            5
 
 /* Rx1 :: anaRxStatus :: rxSeqStart [04:04] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK             0x0010
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS             1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT            4
 
 /* Rx1 :: anaRxStatus :: reserved1 [03:01] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK              0x000e
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS              3
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT             1
 
 /* Rx1 :: anaRxStatus :: rxSeqDone [00:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK              0x0001
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS              1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT             0
 
 
 /* union - case adc_CdrStatus3 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:04] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK              0xfff0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS              12
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT             4
 
 /* Rx1 :: anaRxStatus :: rxSeqStart [03:03] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK             0x0008
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS             1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT            3
 
 /* Rx1 :: anaRxStatus :: reserved1 [02:01] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK              0x0006
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS              2
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT             1
 
 /* Rx1 :: anaRxStatus :: allow_increment_PC [00:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK     0x0001
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN    0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS     1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT    0
 
 
 /* union - case adc_CdrStatus4 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:08] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK              0xff00
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS              8
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT             8
 
 /* Rx1 :: anaRxStatus :: rx_pwrdn [07:07] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK               0x0080
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN              0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS               1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT              7
 
 /* Rx1 :: anaRxStatus :: freq_sel [06:06] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK               0x0040
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN              0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS               1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT              6
 
 /* Rx1 :: anaRxStatus :: pll_lock_rstb [05:05] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK          0x0020
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN         0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS          1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT         5
 
 /* Rx1 :: anaRxStatus :: pwrdn [04:04] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK                  0x0010
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                 0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS                  1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                 4
 
 /* Rx1 :: anaRxStatus :: reserved1 [03:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK              0x000f
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS              4
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT             0
 
 
 /* union - case adc_CdrStatus5 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK              0xffff
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS              16
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT             0
 
 
 /* union - case adc_CdrStatus6 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK              0xffe0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS              11
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT             5
 
 /* Rx1 :: anaRxStatus :: rx_reset [04:04] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK               0x0010
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN              0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS               1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT              4
 
 /* Rx1 :: anaRxStatus :: rx_pwrdn [03:03] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK               0x0008
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN              0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS               1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT              3
 
 /* Rx1 :: anaRxStatus :: reset_anlg [02:02] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK             0x0004
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS             1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT            2
 
 /* Rx1 :: anaRxStatus :: pwrdn_rx [01:01] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK               0x0002
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN              0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS               1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT              1
 
 /* Rx1 :: anaRxStatus :: pwrdn_pll [00:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK              0x0001
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS              1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT             0
 
 
 /* union - case adc_CdrStatus7e [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK             0xffe0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS             11
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT            5
 
 /* Rx1 :: anaRxStatus :: rxck0_even [04:04] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK            0x0010
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN           0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS            1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT           4
 
 /* Rx1 :: anaRxStatus :: rxck1_even [03:03] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK            0x0008
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN           0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS            1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT           3
 
 /* Rx1 :: anaRxStatus :: comdet_even [02:02] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK           0x0004
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN          0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS           1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT          2
 
 /* Rx1 :: anaRxStatus :: en_cdet_even [01:01] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK          0x0002
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN         0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS          1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT         1
 
 /* Rx1 :: anaRxStatus :: comma_adj_en_even [00:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK     0x0001
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN    0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS     1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT    0
 
 
 /* union - case adc_CdrStatus7o [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK             0xffe0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS             11
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT            5
 
 /* Rx1 :: anaRxStatus :: rxck0_odd [04:04] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK             0x0010
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS             1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT            4
 
 /* Rx1 :: anaRxStatus :: rxck1_odd [03:03] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK             0x0008
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS             1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT            3
 
 /* Rx1 :: anaRxStatus :: comdet_odd [02:02] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK            0x0004
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN           0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS            1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT           2
 
 /* Rx1 :: anaRxStatus :: en_cdet_odd [01:01] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK           0x0002
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN          0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS           1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT          1
 
 /* Rx1 :: anaRxStatus :: comma_adj_en_odd [00:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK      0x0001
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN     0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS      1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT     0
 
 
 /* union - case adc_CdrStatus8 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:01] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK              0xfffe
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS              15
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT             1
 
 /* Rx1 :: anaRxStatus :: sigdet [00:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK                 0x0001
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS                 1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                0
 
 
 /* union - case adc_CdrStatus9 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK              0xffff
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS              16
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT             0
 
 
 /* union - case adc_CdrStatus10 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:07] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK             0xff80
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS             9
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT            7
 
 /* Rx1 :: anaRxStatus :: prbs_en [06:06] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK               0x0040
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN              0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS               1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT              6
 
 /* Rx1 :: anaRxStatus :: rstb_tst [05:05] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK              0x0020
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN             0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS              1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT             5
 
 /* Rx1 :: anaRxStatus :: reserved1 [04:04] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK             0x0010
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS             1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT            4
 
 /* Rx1 :: anaRxStatus :: prbs_state [03:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK            0x000f
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN           0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS            4
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT           0
 
 
 /* union - case adc_CdrStatus11 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK             0xffff
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS             16
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT            0
 
 
 /* union - case adc_CdrStatus12_1 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:06] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK           0xffc0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN          0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS           10
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT          6
 
 /* Rx1 :: anaRxStatus :: enable4 [05:05] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK             0x0020
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN            0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS             1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT            5
 
 /* Rx1 :: anaRxStatus :: radr_test [04:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK           0x001f
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN          0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS           5
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT          0
 
 
 /* union - case adc_CdrStatus12_2 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK           0xffe0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN          0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS           11
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT          5
 
 /* Rx1 :: anaRxStatus :: wadr_test [04:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK           0x001f
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN          0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS           5
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT          0
 
 
 /* union - case adc_CdrStatus12_3 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:06] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK           0xffc0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN          0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS           10
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT          6
 
 /* Rx1 :: anaRxStatus :: rxck_66B_tmux [05:05] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK       0x0020
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN      0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS       1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT      5
 
 /* Rx1 :: anaRxStatus :: rstb_66B [04:04] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK            0x0010
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN           0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS            1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT           4
 
 /* Rx1 :: anaRxStatus :: prstb_66B_mux [03:03] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK       0x0008
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN      0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS       1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT      3
 
 /* Rx1 :: anaRxStatus :: rxck_i66_tmux [02:02] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK       0x0004
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN      0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS       1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT      2
 
 /* Rx1 :: anaRxStatus :: rstb_i66 [01:01] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK            0x0002
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN           0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS            1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT           1
 
 /* Rx1 :: anaRxStatus :: prstb_i66_mux [00:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK       0x0001
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN      0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS       1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT      0
 
 
 /* union - case adc_CdrStatus12_4 [15:00] */
 /* Rx1 :: anaRxStatus :: reserved0 [15:04] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK           0xfff0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN          0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS           12
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT          4
 
 /* Rx1 :: anaRxStatus :: rfifo_error_r [03:02] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK       0x000c
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN      0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS       2
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT      2
 
 /* Rx1 :: anaRxStatus :: rfifo_unflow [01:01] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK        0x0002
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN       0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS        1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT       1
 
 /* Rx1 :: anaRxStatus :: rfifo_ovflow [00:00] */
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK        0x0001
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN       0
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS        1
 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT       0
 
 
 /* union - case integ_Status [15:00] */
 /* Rx1 :: anaRxStatus :: integ_status [15:00] */
 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK             0xffff
 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN            0
 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS             16
 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT            0
 
 
 /* union - case vco_Status [15:00] */
 /* Rx1 :: anaRxStatus :: vco_status [15:00] */
 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK                 0xffff
 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN                0
 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS                 16
 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT                0
 
 
 /* union - case prbs_Status [15:00] */
 /* Rx1 :: anaRxStatus :: prbs_lock [15:15] */
 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK                 0x8000
 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                0
 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS                 1
 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                15
 
 /* Rx1 :: anaRxStatus :: prbs_stky [14:14] */
 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK                 0x4000
 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN                0
 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS                 1
 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT                14
 
 /* Rx1 :: anaRxStatus :: ptbs_errors [13:00] */
 #define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK               0x3fff
 #define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN              0
 #define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS               14
 #define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT              0
 
 
 
 /****************************************************************************
  * Rx1 :: anaRxControl
  */
 /* Rx1 :: anaRxControl :: reserved0 [15:10] */
 #define RX1_ANARXCONTROL_RESERVED0_MASK                            0xfc00
 #define RX1_ANARXCONTROL_RESERVED0_ALIGN                           0
 #define RX1_ANARXCONTROL_RESERVED0_BITS                            6
 #define RX1_ANARXCONTROL_RESERVED0_SHIFT                           10
 
 /* Rx1 :: anaRxControl :: override_sigdet_en [09:09] */
 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK                   0x0200
 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN                  0
 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS                   1
 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT                  9
 
 /* Rx1 :: anaRxControl :: override_sigdet_val [08:08] */
 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK                  0x0100
 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN                 0
 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS                  1
 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT                 8
 
 /* Rx1 :: anaRxControl :: reserved1 [07:03] */
 #define RX1_ANARXCONTROL_RESERVED1_MASK                            0x00f8
 #define RX1_ANARXCONTROL_RESERVED1_ALIGN                           0
 #define RX1_ANARXCONTROL_RESERVED1_BITS                            5
 #define RX1_ANARXCONTROL_RESERVED1_SHIFT                           3
 
 /* Rx1 :: anaRxControl :: status_sel [02:00] */
 #define RX1_ANARXCONTROL_STATUS_SEL_MASK                           0x0007
 #define RX1_ANARXCONTROL_STATUS_SEL_ALIGN                          0
 #define RX1_ANARXCONTROL_STATUS_SEL_BITS                           3
 #define RX1_ANARXCONTROL_STATUS_SEL_SHIFT                          0
 #define RX1_ANARXCONTROL_STATUS_SEL_sigdetStatus                   0
 #define RX1_ANARXCONTROL_STATUS_SEL_syncStatus                     1
 #define RX1_ANARXCONTROL_STATUS_SEL_rxTestSel                      2
 #define RX1_ANARXCONTROL_STATUS_SEL_scaleStatus                    3
 #define RX1_ANARXCONTROL_STATUS_SEL_adcCdrStatus                   4
 #define RX1_ANARXCONTROL_STATUS_SEL_integStatus                    5
 #define RX1_ANARXCONTROL_STATUS_SEL_vcoStatus                      6
 #define RX1_ANARXCONTROL_STATUS_SEL_prbsStatus                     7
 
 
 /****************************************************************************
  * Rx1 :: anaRxTest
  */
 /* Rx1 :: anaRxTest :: sigdet_mux_SM [15:12] */
 #define RX1_ANARXTEST_SIGDET_MUX_SM_MASK                           0xf000
 #define RX1_ANARXTEST_SIGDET_MUX_SM_ALIGN                          0
 #define RX1_ANARXTEST_SIGDET_MUX_SM_BITS                           4
 #define RX1_ANARXTEST_SIGDET_MUX_SM_SHIFT                          12
 
 /* Rx1 :: anaRxTest :: reserved0 [11:09] */
 #define RX1_ANARXTEST_RESERVED0_MASK                               0x0e00
 #define RX1_ANARXTEST_RESERVED0_ALIGN                              0
 #define RX1_ANARXTEST_RESERVED0_BITS                               3
 #define RX1_ANARXTEST_RESERVED0_SHIFT                              9
 
 /* Rx1 :: anaRxTest :: tpctrl_SM [08:04] */
 #define RX1_ANARXTEST_TPCTRL_SM_MASK                               0x01f0
 #define RX1_ANARXTEST_TPCTRL_SM_ALIGN                              0
 #define RX1_ANARXTEST_TPCTRL_SM_BITS                               5
 #define RX1_ANARXTEST_TPCTRL_SM_SHIFT                              4
 
 /* Rx1 :: anaRxTest :: testMuxSelect_SM [03:00] */
 #define RX1_ANARXTEST_TESTMUXSELECT_SM_MASK                        0x000f
 #define RX1_ANARXTEST_TESTMUXSELECT_SM_ALIGN                       0
 #define RX1_ANARXTEST_TESTMUXSELECT_SM_BITS                        4
 #define RX1_ANARXTEST_TESTMUXSELECT_SM_SHIFT                       0
 
 
 /****************************************************************************
  * Rx1 :: anaRxControl1G
  */
 /* Rx1 :: anaRxControl1G :: fpat_md [15:15] */
 #define RX1_ANARXCONTROL1G_FPAT_MD_MASK                            0x8000
 #define RX1_ANARXCONTROL1G_FPAT_MD_ALIGN                           0
 #define RX1_ANARXCONTROL1G_FPAT_MD_BITS                            1
 #define RX1_ANARXCONTROL1G_FPAT_MD_SHIFT                           15
 
 /* Rx1 :: anaRxControl1G :: pkt_count_en [14:14] */
 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_MASK                       0x4000
 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN                      0
 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_BITS                       1
 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT                      14
 
 /* Rx1 :: anaRxControl1G :: staMuxRegDis [13:13] */
 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_MASK                       0x2000
 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_ALIGN                      0
 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_BITS                       1
 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_SHIFT                      13
 
 /* Rx1 :: anaRxControl1G :: prbs_clr_dis [12:12] */
 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_MASK                       0x1000
 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN                      0
 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_BITS                       1
 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT                      12
 
 /* Rx1 :: anaRxControl1G :: rxd_dec_sel [11:11] */
 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_MASK                        0x0800
 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN                       0
 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_BITS                        1
 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT                       11
 
 /* Rx1 :: anaRxControl1G :: cgbad_tst [10:10] */
 #define RX1_ANARXCONTROL1G_CGBAD_TST_MASK                          0x0400
 #define RX1_ANARXCONTROL1G_CGBAD_TST_ALIGN                         0
 #define RX1_ANARXCONTROL1G_CGBAD_TST_BITS                          1
 #define RX1_ANARXCONTROL1G_CGBAD_TST_SHIFT                         10
 
 /* Rx1 :: anaRxControl1G :: Emon_en [09:09] */
 #define RX1_ANARXCONTROL1G_EMON_EN_MASK                            0x0200
 #define RX1_ANARXCONTROL1G_EMON_EN_ALIGN                           0
 #define RX1_ANARXCONTROL1G_EMON_EN_BITS                            1
 #define RX1_ANARXCONTROL1G_EMON_EN_SHIFT                           9
 
 /* Rx1 :: anaRxControl1G :: prbs_en [08:08] */
 #define RX1_ANARXCONTROL1G_PRBS_EN_MASK                            0x0100
 #define RX1_ANARXCONTROL1G_PRBS_EN_ALIGN                           0
 #define RX1_ANARXCONTROL1G_PRBS_EN_BITS                            1
 #define RX1_ANARXCONTROL1G_PRBS_EN_SHIFT                           8
 
 /* Rx1 :: anaRxControl1G :: cgbad_en [07:07] */
 #define RX1_ANARXCONTROL1G_CGBAD_EN_MASK                           0x0080
 #define RX1_ANARXCONTROL1G_CGBAD_EN_ALIGN                          0
 #define RX1_ANARXCONTROL1G_CGBAD_EN_BITS                           1
 #define RX1_ANARXCONTROL1G_CGBAD_EN_SHIFT                          7
 
 /* Rx1 :: anaRxControl1G :: cstretch [06:06] */
 #define RX1_ANARXCONTROL1G_CSTRETCH_MASK                           0x0040
 #define RX1_ANARXCONTROL1G_CSTRETCH_ALIGN                          0
 #define RX1_ANARXCONTROL1G_CSTRETCH_BITS                           1
 #define RX1_ANARXCONTROL1G_CSTRETCH_SHIFT                          6
 
 /* Rx1 :: anaRxControl1G :: comma_low_byte_SM [05:05] */
 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK                  0x0020
 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN                 0
 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS                  1
 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT                 5
 
 /* Rx1 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */
 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK               0x0010
 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN              0
 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS               1
 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT              4
 
 /* Rx1 :: anaRxControl1G :: reserved0 [03:02] */
 #define RX1_ANARXCONTROL1G_RESERVED0_MASK                          0x000c
 #define RX1_ANARXCONTROL1G_RESERVED0_ALIGN                         0
 #define RX1_ANARXCONTROL1G_RESERVED0_BITS                          2
 #define RX1_ANARXCONTROL1G_RESERVED0_SHIFT                         2
 
 /* Rx1 :: anaRxControl1G :: freq_sel_force [01:01] */
 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK                     0x0002
 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN                    0
 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS                     1
 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT                    1
 
 /* Rx1 :: anaRxControl1G :: freq_sel [00:00] */
 #define RX1_ANARXCONTROL1G_FREQ_SEL_MASK                           0x0001
 #define RX1_ANARXCONTROL1G_FREQ_SEL_ALIGN                          0
 #define RX1_ANARXCONTROL1G_FREQ_SEL_BITS                           1
 #define RX1_ANARXCONTROL1G_FREQ_SEL_SHIFT                          0
 
 
 /****************************************************************************
  * Rx1 :: anaRxControlPci
  */
 /* Rx1 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK                0x8000
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN               0
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS                1
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT               15
 
 /* Rx1 :: anaRxControlPci :: comma_mask_force_r [14:14] */
 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK                0x4000
 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN               0
 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS                1
 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT               14
 
 /* Rx1 :: anaRxControlPci :: comma_mask_r [13:13] */
 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_MASK                      0x2000
 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN                     0
 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_BITS                      1
 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT                     13
 
 /* Rx1 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK         0x1000
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN        0
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS         1
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT        12
 
 /* Rx1 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK            0x0800
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN           0
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS            1
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT           11
 
 /* Rx1 :: anaRxControlPci :: sync_status_force_r [10:10] */
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK               0x0400
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN              0
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS               1
 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT              10
 
 /* Rx1 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK         0x0200
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN        0
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS         1
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT        9
 
 /* Rx1 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK        0x0100
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN       0
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS        1
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT       8
 
 /* Rx1 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK           0x0080
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN          0
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS           1
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT          7
 
 /* Rx1 :: anaRxControlPci :: comma_adj_en_r [06:06] */
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK                    0x0040
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN                   0
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS                    1
 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT                   6
 
 /* Rx1 :: anaRxControlPci :: link_en_force_SM [05:05] */
 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK                  0x0020
 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN                 0
 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS                  1
 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT                 5
 
 /* Rx1 :: anaRxControlPci :: link_en_r [04:04] */
 #define RX1_ANARXCONTROLPCI_LINK_EN_R_MASK                         0x0010
 #define RX1_ANARXCONTROLPCI_LINK_EN_R_ALIGN                        0
 #define RX1_ANARXCONTROLPCI_LINK_EN_R_BITS                         1
 #define RX1_ANARXCONTROLPCI_LINK_EN_R_SHIFT                        4
 
 /* Rx1 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK              0x0008
 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN             0
 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS              1
 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT             3
 
 /* Rx1 :: anaRxControlPci :: rx_polarity_r [02:02] */
 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_MASK                     0x0004
 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN                    0
 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_BITS                     1
 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT                    2
 
 /* Rx1 :: anaRxControlPci :: integ_mode_SM [01:00] */
 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_MASK                     0x0003
 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN                    0
 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_BITS                     2
 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT                    0
 
 
 /****************************************************************************
  * Rx1 :: anaRxAstatus
  */
 /* Rx1 :: anaRxAstatus :: sigdet [15:15] */
 #define RX1_ANARXASTATUS_SIGDET_MASK                               0x8000
 #define RX1_ANARXASTATUS_SIGDET_ALIGN                              0
 #define RX1_ANARXASTATUS_SIGDET_BITS                               1
 #define RX1_ANARXASTATUS_SIGDET_SHIFT                              15
 
 /* Rx1 :: anaRxAstatus :: rx_pf [14:11] */
 #define RX1_ANARXASTATUS_RX_PF_MASK                                0x7800
 #define RX1_ANARXASTATUS_RX_PF_ALIGN                               0
 #define RX1_ANARXASTATUS_RX_PF_BITS                                4
 #define RX1_ANARXASTATUS_RX_PF_SHIFT                               11
 
 /* Rx1 :: anaRxAstatus :: tap1_dfe_gray [10:05] */
 #define RX1_ANARXASTATUS_TAP1_DFE_GRAY_MASK                        0x07e0
 #define RX1_ANARXASTATUS_TAP1_DFE_GRAY_ALIGN                       0
 #define RX1_ANARXASTATUS_TAP1_DFE_GRAY_BITS                        6
 #define RX1_ANARXASTATUS_TAP1_DFE_GRAY_SHIFT                       5
 
 /* Rx1 :: anaRxAstatus :: vga [04:00] */
 #define RX1_ANARXASTATUS_VGA_MASK                                  0x001f
 #define RX1_ANARXASTATUS_VGA_ALIGN                                 0
 #define RX1_ANARXASTATUS_VGA_BITS                                  5
 #define RX1_ANARXASTATUS_VGA_SHIFT                                 0
 
 
 /****************************************************************************
  * Rx1 :: anaRxAControl1
  */
 /* Rx1 :: anaRxAControl1 :: imode_vcm [15:15] */
 #define RX1_ANARXACONTROL1_IMODE_VCM_MASK                          0x8000
 #define RX1_ANARXACONTROL1_IMODE_VCM_ALIGN                         0
 #define RX1_ANARXACONTROL1_IMODE_VCM_BITS                          1
 #define RX1_ANARXACONTROL1_IMODE_VCM_SHIFT                         15
 
 /* Rx1 :: anaRxAControl1 :: imin_vcm [14:14] */
 #define RX1_ANARXACONTROL1_IMIN_VCM_MASK                           0x4000
 #define RX1_ANARXACONTROL1_IMIN_VCM_ALIGN                          0
 #define RX1_ANARXACONTROL1_IMIN_VCM_BITS                           1
 #define RX1_ANARXACONTROL1_IMIN_VCM_SHIFT                          14
 
 /* Rx1 :: anaRxAControl1 :: imax_sigdet [13:13] */
 #define RX1_ANARXACONTROL1_IMAX_SIGDET_MASK                        0x2000
 #define RX1_ANARXACONTROL1_IMAX_SIGDET_ALIGN                       0
 #define RX1_ANARXACONTROL1_IMAX_SIGDET_BITS                        1
 #define RX1_ANARXACONTROL1_IMAX_SIGDET_SHIFT                       13
 
 /* Rx1 :: anaRxAControl1 :: imode_sigdet [12:12] */
 #define RX1_ANARXACONTROL1_IMODE_SIGDET_MASK                       0x1000
 #define RX1_ANARXACONTROL1_IMODE_SIGDET_ALIGN                      0
 #define RX1_ANARXACONTROL1_IMODE_SIGDET_BITS                       1
 #define RX1_ANARXACONTROL1_IMODE_SIGDET_SHIFT                      12
 
 /* Rx1 :: anaRxAControl1 :: imin_sigdet [11:11] */
 #define RX1_ANARXACONTROL1_IMIN_SIGDET_MASK                        0x0800
 #define RX1_ANARXACONTROL1_IMIN_SIGDET_ALIGN                       0
 #define RX1_ANARXACONTROL1_IMIN_SIGDET_BITS                        1
 #define RX1_ANARXACONTROL1_IMIN_SIGDET_SHIFT                       11
 
 /* Rx1 :: anaRxAControl1 :: refh_rx [10:10] */
 #define RX1_ANARXACONTROL1_REFH_RX_MASK                            0x0400
 #define RX1_ANARXACONTROL1_REFH_RX_ALIGN                           0
 #define RX1_ANARXACONTROL1_REFH_RX_BITS                            1
 #define RX1_ANARXACONTROL1_REFH_RX_SHIFT                           10
 
 /* Rx1 :: anaRxAControl1 :: refl_rx [09:09] */
 #define RX1_ANARXACONTROL1_REFL_RX_MASK                            0x0200
 #define RX1_ANARXACONTROL1_REFL_RX_ALIGN                           0
 #define RX1_ANARXACONTROL1_REFL_RX_BITS                            1
 #define RX1_ANARXACONTROL1_REFL_RX_SHIFT                           9
 
 /* Rx1 :: anaRxAControl1 :: tport_en [08:08] */
 #define RX1_ANARXACONTROL1_TPORT_EN_MASK                           0x0100
 #define RX1_ANARXACONTROL1_TPORT_EN_ALIGN                          0
 #define RX1_ANARXACONTROL1_TPORT_EN_BITS                           1
 #define RX1_ANARXACONTROL1_TPORT_EN_SHIFT                          8
 
 /* Rx1 :: anaRxAControl1 :: vddrb_bgb [07:07] */
 #define RX1_ANARXACONTROL1_VDDRB_BGB_MASK                          0x0080
 #define RX1_ANARXACONTROL1_VDDRB_BGB_ALIGN                         0
 #define RX1_ANARXACONTROL1_VDDRB_BGB_BITS                          1
 #define RX1_ANARXACONTROL1_VDDRB_BGB_SHIFT                         7
 
 /* Rx1 :: anaRxAControl1 :: sig_pwrdn [06:06] */
 #define RX1_ANARXACONTROL1_SIG_PWRDN_MASK                          0x0040
 #define RX1_ANARXACONTROL1_SIG_PWRDN_ALIGN                         0
 #define RX1_ANARXACONTROL1_SIG_PWRDN_BITS                          1
 #define RX1_ANARXACONTROL1_SIG_PWRDN_SHIFT                         6
 
 /* Rx1 :: anaRxAControl1 :: offset_ctrl [05:03] */
 #define RX1_ANARXACONTROL1_OFFSET_CTRL_MASK                        0x0038
 #define RX1_ANARXACONTROL1_OFFSET_CTRL_ALIGN                       0
 #define RX1_ANARXACONTROL1_OFFSET_CTRL_BITS                        3
 #define RX1_ANARXACONTROL1_OFFSET_CTRL_SHIFT                       3
 
 /* Rx1 :: anaRxAControl1 :: offset_sel [02:02] */
 #define RX1_ANARXACONTROL1_OFFSET_SEL_MASK                         0x0004
 #define RX1_ANARXACONTROL1_OFFSET_SEL_ALIGN                        0
 #define RX1_ANARXACONTROL1_OFFSET_SEL_BITS                         1
 #define RX1_ANARXACONTROL1_OFFSET_SEL_SHIFT                        2
 
 /* Rx1 :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */
 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY1_MASK                    0x0002
 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN                   0
 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY1_BITS                    1
 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT                   1
 
 /* Rx1 :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */
 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY0_MASK                    0x0001
 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN                   0
 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY0_BITS                    1
 #define RX1_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT                   0
 
 
 /****************************************************************************
  * Rx1 :: anaRxAControl2
  */
 /* Rx1 :: anaRxAControl2 :: imax_ctat [15:15] */
 #define RX1_ANARXACONTROL2_IMAX_CTAT_MASK                          0x8000
 #define RX1_ANARXACONTROL2_IMAX_CTAT_ALIGN                         0
 #define RX1_ANARXACONTROL2_IMAX_CTAT_BITS                          1
 #define RX1_ANARXACONTROL2_IMAX_CTAT_SHIFT                         15
 
 /* Rx1 :: anaRxAControl2 :: imode_ctat [14:14] */
 #define RX1_ANARXACONTROL2_IMODE_CTAT_MASK                         0x4000
 #define RX1_ANARXACONTROL2_IMODE_CTAT_ALIGN                        0
 #define RX1_ANARXACONTROL2_IMODE_CTAT_BITS                         1
 #define RX1_ANARXACONTROL2_IMODE_CTAT_SHIFT                        14
 
 /* Rx1 :: anaRxAControl2 :: imin_ctat [13:13] */
 #define RX1_ANARXACONTROL2_IMIN_CTAT_MASK                          0x2000
 #define RX1_ANARXACONTROL2_IMIN_CTAT_ALIGN                         0
 #define RX1_ANARXACONTROL2_IMIN_CTAT_BITS                          1
 #define RX1_ANARXACONTROL2_IMIN_CTAT_SHIFT                         13
 
 /* Rx1 :: anaRxAControl2 :: imax_eqfl [12:12] */
 #define RX1_ANARXACONTROL2_IMAX_EQFL_MASK                          0x1000
 #define RX1_ANARXACONTROL2_IMAX_EQFL_ALIGN                         0
 #define RX1_ANARXACONTROL2_IMAX_EQFL_BITS                          1
 #define RX1_ANARXACONTROL2_IMAX_EQFL_SHIFT                         12
 
 /* Rx1 :: anaRxAControl2 :: imode_eqfl [11:11] */
 #define RX1_ANARXACONTROL2_IMODE_EQFL_MASK                         0x0800
 #define RX1_ANARXACONTROL2_IMODE_EQFL_ALIGN                        0
 #define RX1_ANARXACONTROL2_IMODE_EQFL_BITS                         1
 #define RX1_ANARXACONTROL2_IMODE_EQFL_SHIFT                        11
 
 /* Rx1 :: anaRxAControl2 :: imin_eqfl [10:10] */
 #define RX1_ANARXACONTROL2_IMIN_EQFL_MASK                          0x0400
 #define RX1_ANARXACONTROL2_IMIN_EQFL_ALIGN                         0
 #define RX1_ANARXACONTROL2_IMIN_EQFL_BITS                          1
 #define RX1_ANARXACONTROL2_IMIN_EQFL_SHIFT                         10
 
 /* Rx1 :: anaRxAControl2 :: imax_dfesum [09:09] */
 #define RX1_ANARXACONTROL2_IMAX_DFESUM_MASK                        0x0200
 #define RX1_ANARXACONTROL2_IMAX_DFESUM_ALIGN                       0
 #define RX1_ANARXACONTROL2_IMAX_DFESUM_BITS                        1
 #define RX1_ANARXACONTROL2_IMAX_DFESUM_SHIFT                       9
 
 /* Rx1 :: anaRxAControl2 :: imode_dfesum [08:08] */
 #define RX1_ANARXACONTROL2_IMODE_DFESUM_MASK                       0x0100
 #define RX1_ANARXACONTROL2_IMODE_DFESUM_ALIGN                      0
 #define RX1_ANARXACONTROL2_IMODE_DFESUM_BITS                       1
 #define RX1_ANARXACONTROL2_IMODE_DFESUM_SHIFT                      8
 
 /* Rx1 :: anaRxAControl2 :: imin_dfesum [07:07] */
 #define RX1_ANARXACONTROL2_IMIN_DFESUM_MASK                        0x0080
 #define RX1_ANARXACONTROL2_IMIN_DFESUM_ALIGN                       0
 #define RX1_ANARXACONTROL2_IMIN_DFESUM_BITS                        1
 #define RX1_ANARXACONTROL2_IMIN_DFESUM_SHIFT                       7
 
 /* Rx1 :: anaRxAControl2 :: imax_vga [06:06] */
 #define RX1_ANARXACONTROL2_IMAX_VGA_MASK                           0x0040
 #define RX1_ANARXACONTROL2_IMAX_VGA_ALIGN                          0
 #define RX1_ANARXACONTROL2_IMAX_VGA_BITS                           1
 #define RX1_ANARXACONTROL2_IMAX_VGA_SHIFT                          6
 
 /* Rx1 :: anaRxAControl2 :: imode_vga [05:05] */
 #define RX1_ANARXACONTROL2_IMODE_VGA_MASK                          0x0020
 #define RX1_ANARXACONTROL2_IMODE_VGA_ALIGN                         0
 #define RX1_ANARXACONTROL2_IMODE_VGA_BITS                          1
 #define RX1_ANARXACONTROL2_IMODE_VGA_SHIFT                         5
 
 /* Rx1 :: anaRxAControl2 :: imin_vga [04:04] */
 #define RX1_ANARXACONTROL2_IMIN_VGA_MASK                           0x0010
 #define RX1_ANARXACONTROL2_IMIN_VGA_ALIGN                          0
 #define RX1_ANARXACONTROL2_IMIN_VGA_BITS                           1
 #define RX1_ANARXACONTROL2_IMIN_VGA_SHIFT                          4
 
 /* Rx1 :: anaRxAControl2 :: imax_interp [03:03] */
 #define RX1_ANARXACONTROL2_IMAX_INTERP_MASK                        0x0008
 #define RX1_ANARXACONTROL2_IMAX_INTERP_ALIGN                       0
 #define RX1_ANARXACONTROL2_IMAX_INTERP_BITS                        1
 #define RX1_ANARXACONTROL2_IMAX_INTERP_SHIFT                       3
 
 /* Rx1 :: anaRxAControl2 :: imode_interp [02:02] */
 #define RX1_ANARXACONTROL2_IMODE_INTERP_MASK                       0x0004
 #define RX1_ANARXACONTROL2_IMODE_INTERP_ALIGN                      0
 #define RX1_ANARXACONTROL2_IMODE_INTERP_BITS                       1
 #define RX1_ANARXACONTROL2_IMODE_INTERP_SHIFT                      2
 
 /* Rx1 :: anaRxAControl2 :: imin_interp [01:01] */
 #define RX1_ANARXACONTROL2_IMIN_INTERP_MASK                        0x0002
 #define RX1_ANARXACONTROL2_IMIN_INTERP_ALIGN                       0
 #define RX1_ANARXACONTROL2_IMIN_INTERP_BITS                        1
 #define RX1_ANARXACONTROL2_IMIN_INTERP_SHIFT                       1
 
 /* Rx1 :: anaRxAControl2 :: imax_vcm [00:00] */
 #define RX1_ANARXACONTROL2_IMAX_VCM_MASK                           0x0001
 #define RX1_ANARXACONTROL2_IMAX_VCM_ALIGN                          0
 #define RX1_ANARXACONTROL2_IMAX_VCM_BITS                           1
 #define RX1_ANARXACONTROL2_IMAX_VCM_SHIFT                          0
 
 
 /****************************************************************************
  * Rx1 :: anaRxAControl3
  */
 /* Rx1 :: anaRxAControl3 :: en_clk16 [15:15] */
 #define RX1_ANARXACONTROL3_EN_CLK16_MASK                           0x8000
 #define RX1_ANARXACONTROL3_EN_CLK16_ALIGN                          0
 #define RX1_ANARXACONTROL3_EN_CLK16_BITS                           1
 #define RX1_ANARXACONTROL3_EN_CLK16_SHIFT                          15
 
 /* Rx1 :: anaRxAControl3 :: en_clk33 [14:14] */
 #define RX1_ANARXACONTROL3_EN_CLK33_MASK                           0x4000
 #define RX1_ANARXACONTROL3_EN_CLK33_ALIGN                          0
 #define RX1_ANARXACONTROL3_EN_CLK33_BITS                           1
 #define RX1_ANARXACONTROL3_EN_CLK33_SHIFT                          14
 
 /* Rx1 :: anaRxAControl3 :: en_vcctrl [13:13] */
 #define RX1_ANARXACONTROL3_EN_VCCTRL_MASK                          0x2000
 #define RX1_ANARXACONTROL3_EN_VCCTRL_ALIGN                         0
 #define RX1_ANARXACONTROL3_EN_VCCTRL_BITS                          1
 #define RX1_ANARXACONTROL3_EN_VCCTRL_SHIFT                         13
 
 /* Rx1 :: anaRxAControl3 :: sel_th4dfe1 [12:12] */
 #define RX1_ANARXACONTROL3_SEL_TH4DFE1_MASK                        0x1000
 #define RX1_ANARXACONTROL3_SEL_TH4DFE1_ALIGN                       0
 #define RX1_ANARXACONTROL3_SEL_TH4DFE1_BITS                        1
 #define RX1_ANARXACONTROL3_SEL_TH4DFE1_SHIFT                       12
 
 /* Rx1 :: anaRxAControl3 :: sel_th4dfe0 [11:11] */
 #define RX1_ANARXACONTROL3_SEL_TH4DFE0_MASK                        0x0800
 #define RX1_ANARXACONTROL3_SEL_TH4DFE0_ALIGN                       0
 #define RX1_ANARXACONTROL3_SEL_TH4DFE0_BITS                        1
 #define RX1_ANARXACONTROL3_SEL_TH4DFE0_SHIFT                       11
 
 /* Rx1 :: anaRxAControl3 :: selugbw1 [10:10] */
 #define RX1_ANARXACONTROL3_SELUGBW1_MASK                           0x0400
 #define RX1_ANARXACONTROL3_SELUGBW1_ALIGN                          0
 #define RX1_ANARXACONTROL3_SELUGBW1_BITS                           1
 #define RX1_ANARXACONTROL3_SELUGBW1_SHIFT                          10
 
 /* Rx1 :: anaRxAControl3 :: selugbw0 [09:09] */
 #define RX1_ANARXACONTROL3_SELUGBW0_MASK                           0x0200
 #define RX1_ANARXACONTROL3_SELUGBW0_ALIGN                          0
 #define RX1_ANARXACONTROL3_SELUGBW0_BITS                           1
 #define RX1_ANARXACONTROL3_SELUGBW0_SHIFT                          9
 
 /* Rx1 :: anaRxAControl3 :: imax_dfetap [08:08] */
 #define RX1_ANARXACONTROL3_IMAX_DFETAP_MASK                        0x0100
 #define RX1_ANARXACONTROL3_IMAX_DFETAP_ALIGN                       0
 #define RX1_ANARXACONTROL3_IMAX_DFETAP_BITS                        1
 #define RX1_ANARXACONTROL3_IMAX_DFETAP_SHIFT                       8
 
 /* Rx1 :: anaRxAControl3 :: imode_dfetap [07:07] */
 #define RX1_ANARXACONTROL3_IMODE_DFETAP_MASK                       0x0080
 #define RX1_ANARXACONTROL3_IMODE_DFETAP_ALIGN                      0
 #define RX1_ANARXACONTROL3_IMODE_DFETAP_BITS                       1
 #define RX1_ANARXACONTROL3_IMODE_DFETAP_SHIFT                      7
 
 /* Rx1 :: anaRxAControl3 :: imin_dfetap [06:06] */
 #define RX1_ANARXACONTROL3_IMIN_DFETAP_MASK                        0x0040
 #define RX1_ANARXACONTROL3_IMIN_DFETAP_ALIGN                       0
 #define RX1_ANARXACONTROL3_IMIN_DFETAP_BITS                        1
 #define RX1_ANARXACONTROL3_IMIN_DFETAP_SHIFT                       6
 
 /* Rx1 :: anaRxAControl3 :: imax_slcd2c [05:05] */
 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_MASK                        0x0020
 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_ALIGN                       0
 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_BITS                        1
 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_SHIFT                       5
 
 /* Rx1 :: anaRxAControl3 :: imode_slcd2c [04:04] */
 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_MASK                       0x0010
 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_ALIGN                      0
 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_BITS                       1
 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_SHIFT                      4
 
 /* Rx1 :: anaRxAControl3 :: imin_slcd2c [03:03] */
 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_MASK                        0x0008
 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_ALIGN                       0
 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_BITS                        1
 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_SHIFT                       3
 
 /* Rx1 :: anaRxAControl3 :: imax_dfevref [02:02] */
 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_MASK                       0x0004
 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_ALIGN                      0
 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_BITS                       1
 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_SHIFT                      2
 
 /* Rx1 :: anaRxAControl3 :: imode_dfevref [01:01] */
 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_MASK                      0x0002
 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_ALIGN                     0
 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_BITS                      1
 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_SHIFT                     1
 
 /* Rx1 :: anaRxAControl3 :: imin_dfevref [00:00] */
 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_MASK                       0x0001
 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_ALIGN                      0
 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_BITS                       1
 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_SHIFT                      0
 
 
 /****************************************************************************
  * Warpcore_USER_Rx2
  */
 /****************************************************************************
  * Rx2 :: anaRxStatus
  */
 /* union - case sigdet_Status [15:00] */
 /* Rx2 :: anaRxStatus :: cx4_sigdet [15:15] */
 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK              0x8000
 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN             0
 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS              1
 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT             15
 
 /* Rx2 :: anaRxStatus :: reserved0 [14:13] */
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK               0x6000
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN              0
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS               2
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT              13
 
 /* Rx2 :: anaRxStatus :: rxSeqDone [12:12] */
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK               0x1000
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN              0
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS               1
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT              12
 
 /* Rx2 :: anaRxStatus :: rx_sigdet_ll [11:11] */
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK            0x0800
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN           0
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS            1
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT           11
 
 /* Rx2 :: anaRxStatus :: cs4_sigdet_ll [10:10] */
 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK           0x0400
 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN          0
 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS           1
 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT          10
 
 /* Rx2 :: anaRxStatus :: rx_reset [09:09] */
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK                0x0200
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN               0
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS                1
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT               9
 
 /* Rx2 :: anaRxStatus :: rx_pwrdn [08:08] */
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK                0x0100
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN               0
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS                1
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT               8
 
 /* Rx2 :: anaRxStatus :: reserved1 [07:00] */
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK               0x00ff
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN              0
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS               8
 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT              0
 
 
 /* union - case sync_Status [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:11] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK                 0xf800
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN                0
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS                 5
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT                11
 
 /* Rx2 :: anaRxStatus :: test_acq_en [10:10] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK               0x0400
 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN              0
 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS               1
 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT              10
 
 /* Rx2 :: anaRxStatus :: reserved1 [09:09] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK                 0x0200
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN                0
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS                 1
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT                9
 
 /* Rx2 :: anaRxStatus :: rxSeqStart [08:08] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK                0x0100
 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN               0
 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS                1
 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT               8
 
 /* Rx2 :: anaRxStatus :: mux_comadj_sync_status [07:07] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK    0x0080
 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN   0
 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS    1
 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT   7
 
 /* Rx2 :: anaRxStatus :: sync_status [06:06] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK               0x0040
 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN              0
 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS               1
 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT              6
 
 /* Rx2 :: anaRxStatus :: rx_sigdet [05:05] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK                 0x0020
 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN                0
 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS                 1
 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT                5
 
 /* Rx2 :: anaRxStatus :: reserved2 [04:03] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK                 0x0018
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN                0
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS                 2
 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT                3
 
 /* Rx2 :: anaRxStatus :: saturate_status [02:02] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK           0x0004
 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN          0
 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS           1
 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT          2
 
 /* Rx2 :: anaRxStatus :: cx4_sigdet [01:01] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK                0x0002
 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN               0
 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS                1
 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT               1
 
 /* Rx2 :: anaRxStatus :: rxSeqDone [00:00] */
 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK                 0x0001
 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN                0
 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS                 1
 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT                0
 
 
 /* union - case rxTestSel_0 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:10] */
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK                 0xfc00
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN                0
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS                 6
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT                10
 
 /* Rx2 :: anaRxStatus :: indck_mode_en [09:09] */
 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK             0x0200
 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN            0
 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS             1
 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT            9
 
 /* Rx2 :: anaRxStatus :: pci_mode_en [08:08] */
 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK               0x0100
 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN              0
 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS               1
 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT              8
 
 /* Rx2 :: anaRxStatus :: rx_polarity [07:07] */
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK               0x0080
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN              0
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS               1
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT              7
 
 /* Rx2 :: anaRxStatus :: rxpol_flip [06:06] */
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                0x0040
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN               0
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                1
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT               6
 
 /* Rx2 :: anaRxStatus :: comma_mask [05:05] */
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK                0x0020
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN               0
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS                1
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT               5
 
 /* Rx2 :: anaRxStatus :: link_en_r [04:04] */
 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK                 0x0010
 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                0
 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS                 1
 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                4
 
 /* Rx2 :: anaRxStatus :: comma_adj_en [03:03] */
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK              0x0008
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN             0
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS              1
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT             3
 
 /* Rx2 :: anaRxStatus :: comma_adj_en_ext [02:02] */
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK          0x0004
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN         0
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS          1
 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT         2
 
 /* Rx2 :: anaRxStatus :: reserved1 [01:00] */
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK                 0x0003
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN                0
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS                 2
 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT                0
 
 
 /* union - case rxTestSel_1 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */
 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK                 0xffe0
 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN                0
 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS                 11
 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT                5
 
 /* Rx2 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK             0x0010
 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN            0
 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS             1
 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT            4
 
 /* Rx2 :: anaRxStatus :: freq_sel_PC [03:03] */
 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK               0x0008
 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN              0
 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS               1
 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT              3
 
 /* Rx2 :: anaRxStatus :: freq_sel_SM [02:02] */
 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK               0x0004
 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN              0
 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS               1
 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT              2
 
 /* Rx2 :: anaRxStatus :: integ_mode_SM [01:00] */
 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK             0x0003
 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN            0
 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS             2
 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT            0
 
 
 /* union - case scale_Status [15:00] */
 /* Rx2 :: anaRxStatus :: prop_scale [15:12] */
 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK               0xf000
 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN              0
 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS               4
 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT              12
 
 /* Rx2 :: anaRxStatus :: integ_scale [11:08] */
 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK              0x0f00
 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN             0
 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS              4
 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT             8
 
 /* Rx2 :: anaRxStatus :: prop_scale_acq [07:04] */
 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK           0x00f0
 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN          0
 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS           4
 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT          4
 
 /* Rx2 :: anaRxStatus :: integ_scale_acq [03:00] */
 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK          0x000f
 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN         0
 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS          4
 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT         0
 
 
 /* union - case adc_CdrStatus1 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:07] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK              0xff80
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS              9
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT             7
 
 /* Rx2 :: anaRxStatus :: rxMuxCkSel [06:06] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK             0x0040
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS             1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT            6
 
 /* Rx2 :: anaRxStatus :: glpbk_combo [05:05] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK            0x0020
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN           0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS            1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT           5
 
 /* Rx2 :: anaRxStatus :: clockSwitchSel [04:04] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK         0x0010
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN        0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS         1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT        4
 
 /* Rx2 :: anaRxStatus :: rxck_tst [03:03] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK               0x0008
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN              0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS               1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT              3
 
 /* Rx2 :: anaRxStatus :: rxck_i [02:02] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK                 0x0004
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS                 1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                2
 
 /* Rx2 :: anaRxStatus :: refclk [01:01] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK                 0x0002
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS                 1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                1
 
 /* Rx2 :: anaRxStatus :: pll_bypass [00:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK             0x0001
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS             1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT            0
 
 
 /* union - case adc_CdrStatus2 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:06] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK              0xffc0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS              10
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT             6
 
 /* Rx2 :: anaRxStatus :: rxMuxCkSel [05:05] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK             0x0020
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS             1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT            5
 
 /* Rx2 :: anaRxStatus :: rxSeqStart [04:04] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK             0x0010
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS             1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT            4
 
 /* Rx2 :: anaRxStatus :: reserved1 [03:01] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK              0x000e
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS              3
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT             1
 
 /* Rx2 :: anaRxStatus :: rxSeqDone [00:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK              0x0001
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS              1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT             0
 
 
 /* union - case adc_CdrStatus3 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:04] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK              0xfff0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS              12
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT             4
 
 /* Rx2 :: anaRxStatus :: rxSeqStart [03:03] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK             0x0008
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS             1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT            3
 
 /* Rx2 :: anaRxStatus :: reserved1 [02:01] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK              0x0006
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS              2
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT             1
 
 /* Rx2 :: anaRxStatus :: allow_increment_PC [00:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK     0x0001
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN    0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS     1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT    0
 
 
 /* union - case adc_CdrStatus4 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:08] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK              0xff00
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS              8
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT             8
 
 /* Rx2 :: anaRxStatus :: rx_pwrdn [07:07] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK               0x0080
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN              0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS               1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT              7
 
 /* Rx2 :: anaRxStatus :: freq_sel [06:06] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK               0x0040
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN              0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS               1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT              6
 
 /* Rx2 :: anaRxStatus :: pll_lock_rstb [05:05] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK          0x0020
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN         0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS          1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT         5
 
 /* Rx2 :: anaRxStatus :: pwrdn [04:04] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK                  0x0010
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                 0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS                  1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                 4
 
 /* Rx2 :: anaRxStatus :: reserved1 [03:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK              0x000f
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS              4
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT             0
 
 
 /* union - case adc_CdrStatus5 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK              0xffff
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS              16
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT             0
 
 
 /* union - case adc_CdrStatus6 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK              0xffe0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS              11
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT             5
 
 /* Rx2 :: anaRxStatus :: rx_reset [04:04] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK               0x0010
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN              0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS               1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT              4
 
 /* Rx2 :: anaRxStatus :: rx_pwrdn [03:03] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK               0x0008
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN              0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS               1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT              3
 
 /* Rx2 :: anaRxStatus :: reset_anlg [02:02] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK             0x0004
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS             1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT            2
 
 /* Rx2 :: anaRxStatus :: pwrdn_rx [01:01] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK               0x0002
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN              0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS               1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT              1
 
 /* Rx2 :: anaRxStatus :: pwrdn_pll [00:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK              0x0001
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS              1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT             0
 
 
 /* union - case adc_CdrStatus7e [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK             0xffe0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS             11
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT            5
 
 /* Rx2 :: anaRxStatus :: rxck0_even [04:04] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK            0x0010
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN           0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS            1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT           4
 
 /* Rx2 :: anaRxStatus :: rxck1_even [03:03] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK            0x0008
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN           0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS            1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT           3
 
 /* Rx2 :: anaRxStatus :: comdet_even [02:02] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK           0x0004
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN          0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS           1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT          2
 
 /* Rx2 :: anaRxStatus :: en_cdet_even [01:01] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK          0x0002
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN         0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS          1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT         1
 
 /* Rx2 :: anaRxStatus :: comma_adj_en_even [00:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK     0x0001
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN    0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS     1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT    0
 
 
 /* union - case adc_CdrStatus7o [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK             0xffe0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS             11
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT            5
 
 /* Rx2 :: anaRxStatus :: rxck0_odd [04:04] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK             0x0010
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS             1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT            4
 
 /* Rx2 :: anaRxStatus :: rxck1_odd [03:03] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK             0x0008
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS             1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT            3
 
 /* Rx2 :: anaRxStatus :: comdet_odd [02:02] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK            0x0004
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN           0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS            1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT           2
 
 /* Rx2 :: anaRxStatus :: en_cdet_odd [01:01] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK           0x0002
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN          0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS           1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT          1
 
 /* Rx2 :: anaRxStatus :: comma_adj_en_odd [00:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK      0x0001
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN     0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS      1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT     0
 
 
 /* union - case adc_CdrStatus8 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:01] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK              0xfffe
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS              15
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT             1
 
 /* Rx2 :: anaRxStatus :: sigdet [00:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK                 0x0001
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS                 1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                0
 
 
 /* union - case adc_CdrStatus9 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK              0xffff
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS              16
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT             0
 
 
 /* union - case adc_CdrStatus10 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:07] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK             0xff80
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS             9
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT            7
 
 /* Rx2 :: anaRxStatus :: prbs_en [06:06] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK               0x0040
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN              0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS               1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT              6
 
 /* Rx2 :: anaRxStatus :: rstb_tst [05:05] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK              0x0020
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN             0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS              1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT             5
 
 /* Rx2 :: anaRxStatus :: reserved1 [04:04] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK             0x0010
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS             1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT            4
 
 /* Rx2 :: anaRxStatus :: prbs_state [03:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK            0x000f
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN           0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS            4
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT           0
 
 
 /* union - case adc_CdrStatus11 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK             0xffff
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS             16
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT            0
 
 
 /* union - case adc_CdrStatus12_1 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:06] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK           0xffc0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN          0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS           10
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT          6
 
 /* Rx2 :: anaRxStatus :: enable4 [05:05] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK             0x0020
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN            0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS             1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT            5
 
 /* Rx2 :: anaRxStatus :: radr_test [04:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK           0x001f
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN          0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS           5
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT          0
 
 
 /* union - case adc_CdrStatus12_2 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK           0xffe0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN          0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS           11
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT          5
 
 /* Rx2 :: anaRxStatus :: wadr_test [04:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK           0x001f
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN          0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS           5
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT          0
 
 
 /* union - case adc_CdrStatus12_3 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:06] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK           0xffc0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN          0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS           10
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT          6
 
 /* Rx2 :: anaRxStatus :: rxck_66B_tmux [05:05] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK       0x0020
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN      0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS       1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT      5
 
 /* Rx2 :: anaRxStatus :: rstb_66B [04:04] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK            0x0010
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN           0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS            1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT           4
 
 /* Rx2 :: anaRxStatus :: prstb_66B_mux [03:03] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK       0x0008
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN      0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS       1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT      3
 
 /* Rx2 :: anaRxStatus :: rxck_i66_tmux [02:02] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK       0x0004
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN      0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS       1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT      2
 
 /* Rx2 :: anaRxStatus :: rstb_i66 [01:01] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK            0x0002
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN           0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS            1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT           1
 
 /* Rx2 :: anaRxStatus :: prstb_i66_mux [00:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK       0x0001
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN      0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS       1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT      0
 
 
 /* union - case adc_CdrStatus12_4 [15:00] */
 /* Rx2 :: anaRxStatus :: reserved0 [15:04] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK           0xfff0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN          0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS           12
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT          4
 
 /* Rx2 :: anaRxStatus :: rfifo_error_r [03:02] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK       0x000c
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN      0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS       2
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT      2
 
 /* Rx2 :: anaRxStatus :: rfifo_unflow [01:01] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK        0x0002
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN       0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS        1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT       1
 
 /* Rx2 :: anaRxStatus :: rfifo_ovflow [00:00] */
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK        0x0001
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN       0
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS        1
 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT       0
 
 
 /* union - case integ_Status [15:00] */
 /* Rx2 :: anaRxStatus :: integ_status [15:00] */
 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK             0xffff
 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN            0
 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS             16
 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT            0
 
 
 /* union - case vco_Status [15:00] */
 /* Rx2 :: anaRxStatus :: vco_status [15:00] */
 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK                 0xffff
 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN                0
 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS                 16
 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT                0
 
 
 /* union - case prbs_Status [15:00] */
 /* Rx2 :: anaRxStatus :: prbs_lock [15:15] */
 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK                 0x8000
 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                0
 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS                 1
 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                15
 
 /* Rx2 :: anaRxStatus :: prbs_stky [14:14] */
 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK                 0x4000
 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN                0
 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS                 1
 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT                14
 
 /* Rx2 :: anaRxStatus :: ptbs_errors [13:00] */
 #define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK               0x3fff
 #define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN              0
 #define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS               14
 #define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT              0
 
 
 
 /****************************************************************************
  * Rx2 :: anaRxControl
  */
 /* Rx2 :: anaRxControl :: reserved0 [15:10] */
 #define RX2_ANARXCONTROL_RESERVED0_MASK                            0xfc00
 #define RX2_ANARXCONTROL_RESERVED0_ALIGN                           0
 #define RX2_ANARXCONTROL_RESERVED0_BITS                            6
 #define RX2_ANARXCONTROL_RESERVED0_SHIFT                           10
 
 /* Rx2 :: anaRxControl :: override_sigdet_en [09:09] */
 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK                   0x0200
 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN                  0
 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS                   1
 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT                  9
 
 /* Rx2 :: anaRxControl :: override_sigdet_val [08:08] */
 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK                  0x0100
 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN                 0
 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS                  1
 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT                 8
 
 /* Rx2 :: anaRxControl :: reserved1 [07:03] */
 #define RX2_ANARXCONTROL_RESERVED1_MASK                            0x00f8
 #define RX2_ANARXCONTROL_RESERVED1_ALIGN                           0
 #define RX2_ANARXCONTROL_RESERVED1_BITS                            5
 #define RX2_ANARXCONTROL_RESERVED1_SHIFT                           3
 
 /* Rx2 :: anaRxControl :: status_sel [02:00] */
 #define RX2_ANARXCONTROL_STATUS_SEL_MASK                           0x0007
 #define RX2_ANARXCONTROL_STATUS_SEL_ALIGN                          0
 #define RX2_ANARXCONTROL_STATUS_SEL_BITS                           3
 #define RX2_ANARXCONTROL_STATUS_SEL_SHIFT                          0
 #define RX2_ANARXCONTROL_STATUS_SEL_sigdetStatus                   0
 #define RX2_ANARXCONTROL_STATUS_SEL_syncStatus                     1
 #define RX2_ANARXCONTROL_STATUS_SEL_rxTestSel                      2
 #define RX2_ANARXCONTROL_STATUS_SEL_scaleStatus                    3
 #define RX2_ANARXCONTROL_STATUS_SEL_adcCdrStatus                   4
 #define RX2_ANARXCONTROL_STATUS_SEL_integStatus                    5
 #define RX2_ANARXCONTROL_STATUS_SEL_vcoStatus                      6
 #define RX2_ANARXCONTROL_STATUS_SEL_prbsStatus                     7
 
 
 /****************************************************************************
  * Rx2 :: anaRxTest
  */
 /* Rx2 :: anaRxTest :: sigdet_mux_SM [15:12] */
 #define RX2_ANARXTEST_SIGDET_MUX_SM_MASK                           0xf000
 #define RX2_ANARXTEST_SIGDET_MUX_SM_ALIGN                          0
 #define RX2_ANARXTEST_SIGDET_MUX_SM_BITS                           4
 #define RX2_ANARXTEST_SIGDET_MUX_SM_SHIFT                          12
 
 /* Rx2 :: anaRxTest :: reserved0 [11:09] */
 #define RX2_ANARXTEST_RESERVED0_MASK                               0x0e00
 #define RX2_ANARXTEST_RESERVED0_ALIGN                              0
 #define RX2_ANARXTEST_RESERVED0_BITS                               3
 #define RX2_ANARXTEST_RESERVED0_SHIFT                              9
 
 /* Rx2 :: anaRxTest :: tpctrl_SM [08:04] */
 #define RX2_ANARXTEST_TPCTRL_SM_MASK                               0x01f0
 #define RX2_ANARXTEST_TPCTRL_SM_ALIGN                              0
 #define RX2_ANARXTEST_TPCTRL_SM_BITS                               5
 #define RX2_ANARXTEST_TPCTRL_SM_SHIFT                              4
 
 /* Rx2 :: anaRxTest :: testMuxSelect_SM [03:00] */
 #define RX2_ANARXTEST_TESTMUXSELECT_SM_MASK                        0x000f
 #define RX2_ANARXTEST_TESTMUXSELECT_SM_ALIGN                       0
 #define RX2_ANARXTEST_TESTMUXSELECT_SM_BITS                        4
 #define RX2_ANARXTEST_TESTMUXSELECT_SM_SHIFT                       0
 
 
 /****************************************************************************
  * Rx2 :: anaRxControl1G
  */
 /* Rx2 :: anaRxControl1G :: fpat_md [15:15] */
 #define RX2_ANARXCONTROL1G_FPAT_MD_MASK                            0x8000
 #define RX2_ANARXCONTROL1G_FPAT_MD_ALIGN                           0
 #define RX2_ANARXCONTROL1G_FPAT_MD_BITS                            1
 #define RX2_ANARXCONTROL1G_FPAT_MD_SHIFT                           15
 
 /* Rx2 :: anaRxControl1G :: pkt_count_en [14:14] */
 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_MASK                       0x4000
 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN                      0
 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_BITS                       1
 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT                      14
 
 /* Rx2 :: anaRxControl1G :: staMuxRegDis [13:13] */
 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_MASK                       0x2000
 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_ALIGN                      0
 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_BITS                       1
 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_SHIFT                      13
 
 /* Rx2 :: anaRxControl1G :: prbs_clr_dis [12:12] */
 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_MASK                       0x1000
 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN                      0
 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_BITS                       1
 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT                      12
 
 /* Rx2 :: anaRxControl1G :: rxd_dec_sel [11:11] */
 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_MASK                        0x0800
 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN                       0
 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_BITS                        1
 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT                       11
 
 /* Rx2 :: anaRxControl1G :: cgbad_tst [10:10] */
 #define RX2_ANARXCONTROL1G_CGBAD_TST_MASK                          0x0400
 #define RX2_ANARXCONTROL1G_CGBAD_TST_ALIGN                         0
 #define RX2_ANARXCONTROL1G_CGBAD_TST_BITS                          1
 #define RX2_ANARXCONTROL1G_CGBAD_TST_SHIFT                         10
 
 /* Rx2 :: anaRxControl1G :: Emon_en [09:09] */
 #define RX2_ANARXCONTROL1G_EMON_EN_MASK                            0x0200
 #define RX2_ANARXCONTROL1G_EMON_EN_ALIGN                           0
 #define RX2_ANARXCONTROL1G_EMON_EN_BITS                            1
 #define RX2_ANARXCONTROL1G_EMON_EN_SHIFT                           9
 
 /* Rx2 :: anaRxControl1G :: prbs_en [08:08] */
 #define RX2_ANARXCONTROL1G_PRBS_EN_MASK                            0x0100
 #define RX2_ANARXCONTROL1G_PRBS_EN_ALIGN                           0
 #define RX2_ANARXCONTROL1G_PRBS_EN_BITS                            1
 #define RX2_ANARXCONTROL1G_PRBS_EN_SHIFT                           8
 
 /* Rx2 :: anaRxControl1G :: cgbad_en [07:07] */
 #define RX2_ANARXCONTROL1G_CGBAD_EN_MASK                           0x0080
 #define RX2_ANARXCONTROL1G_CGBAD_EN_ALIGN                          0
 #define RX2_ANARXCONTROL1G_CGBAD_EN_BITS                           1
 #define RX2_ANARXCONTROL1G_CGBAD_EN_SHIFT                          7
 
 /* Rx2 :: anaRxControl1G :: cstretch [06:06] */
 #define RX2_ANARXCONTROL1G_CSTRETCH_MASK                           0x0040
 #define RX2_ANARXCONTROL1G_CSTRETCH_ALIGN                          0
 #define RX2_ANARXCONTROL1G_CSTRETCH_BITS                           1
 #define RX2_ANARXCONTROL1G_CSTRETCH_SHIFT                          6
 
 /* Rx2 :: anaRxControl1G :: comma_low_byte_SM [05:05] */
 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK                  0x0020
 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN                 0
 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS                  1
 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT                 5
 
 /* Rx2 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */
 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK               0x0010
 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN              0
 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS               1
 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT              4
 
 /* Rx2 :: anaRxControl1G :: reserved0 [03:02] */
 #define RX2_ANARXCONTROL1G_RESERVED0_MASK                          0x000c
 #define RX2_ANARXCONTROL1G_RESERVED0_ALIGN                         0
 #define RX2_ANARXCONTROL1G_RESERVED0_BITS                          2
 #define RX2_ANARXCONTROL1G_RESERVED0_SHIFT                         2
 
 /* Rx2 :: anaRxControl1G :: freq_sel_force [01:01] */
 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK                     0x0002
 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN                    0
 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS                     1
 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT                    1
 
 /* Rx2 :: anaRxControl1G :: freq_sel [00:00] */
 #define RX2_ANARXCONTROL1G_FREQ_SEL_MASK                           0x0001
 #define RX2_ANARXCONTROL1G_FREQ_SEL_ALIGN                          0
 #define RX2_ANARXCONTROL1G_FREQ_SEL_BITS                           1
 #define RX2_ANARXCONTROL1G_FREQ_SEL_SHIFT                          0
 
 
 /****************************************************************************
  * Rx2 :: anaRxControlPci
  */
 /* Rx2 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK                0x8000
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN               0
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS                1
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT               15
 
 /* Rx2 :: anaRxControlPci :: comma_mask_force_r [14:14] */
 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK                0x4000
 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN               0
 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS                1
 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT               14
 
 /* Rx2 :: anaRxControlPci :: comma_mask_r [13:13] */
 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_MASK                      0x2000
 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN                     0
 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_BITS                      1
 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT                     13
 
 /* Rx2 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK         0x1000
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN        0
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS         1
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT        12
 
 /* Rx2 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK            0x0800
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN           0
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS            1
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT           11
 
 /* Rx2 :: anaRxControlPci :: sync_status_force_r [10:10] */
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK               0x0400
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN              0
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS               1
 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT              10
 
 /* Rx2 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK         0x0200
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN        0
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS         1
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT        9
 
 /* Rx2 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK        0x0100
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN       0
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS        1
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT       8
 
 /* Rx2 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK           0x0080
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN          0
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS           1
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT          7
 
 /* Rx2 :: anaRxControlPci :: comma_adj_en_r [06:06] */
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK                    0x0040
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN                   0
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS                    1
 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT                   6
 
 /* Rx2 :: anaRxControlPci :: link_en_force_SM [05:05] */
 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK                  0x0020
 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN                 0
 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS                  1
 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT                 5
 
 /* Rx2 :: anaRxControlPci :: link_en_r [04:04] */
 #define RX2_ANARXCONTROLPCI_LINK_EN_R_MASK                         0x0010
 #define RX2_ANARXCONTROLPCI_LINK_EN_R_ALIGN                        0
 #define RX2_ANARXCONTROLPCI_LINK_EN_R_BITS                         1
 #define RX2_ANARXCONTROLPCI_LINK_EN_R_SHIFT                        4
 
 /* Rx2 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK              0x0008
 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN             0
 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS              1
 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT             3
 
 /* Rx2 :: anaRxControlPci :: rx_polarity_r [02:02] */
 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_MASK                     0x0004
 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN                    0
 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_BITS                     1
 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT                    2
 
 /* Rx2 :: anaRxControlPci :: integ_mode_SM [01:00] */
 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_MASK                     0x0003
 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN                    0
 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_BITS                     2
 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT                    0
 
 
 /****************************************************************************
  * Rx2 :: anaRxAstatus
  */
 /* Rx2 :: anaRxAstatus :: sigdet [15:15] */
 #define RX2_ANARXASTATUS_SIGDET_MASK                               0x8000
 #define RX2_ANARXASTATUS_SIGDET_ALIGN                              0
 #define RX2_ANARXASTATUS_SIGDET_BITS                               1
 #define RX2_ANARXASTATUS_SIGDET_SHIFT                              15
 
 /* Rx2 :: anaRxAstatus :: rx_pf [14:11] */
 #define RX2_ANARXASTATUS_RX_PF_MASK                                0x7800
 #define RX2_ANARXASTATUS_RX_PF_ALIGN                               0
 #define RX2_ANARXASTATUS_RX_PF_BITS                                4
 #define RX2_ANARXASTATUS_RX_PF_SHIFT                               11
 
 /* Rx2 :: anaRxAstatus :: tap1_dfe_gray [10:05] */
 #define RX2_ANARXASTATUS_TAP1_DFE_GRAY_MASK                        0x07e0
 #define RX2_ANARXASTATUS_TAP1_DFE_GRAY_ALIGN                       0
 #define RX2_ANARXASTATUS_TAP1_DFE_GRAY_BITS                        6
 #define RX2_ANARXASTATUS_TAP1_DFE_GRAY_SHIFT                       5
 
 /* Rx2 :: anaRxAstatus :: vga [04:00] */
 #define RX2_ANARXASTATUS_VGA_MASK                                  0x001f
 #define RX2_ANARXASTATUS_VGA_ALIGN                                 0
 #define RX2_ANARXASTATUS_VGA_BITS                                  5
 #define RX2_ANARXASTATUS_VGA_SHIFT                                 0
 
 
 /****************************************************************************
  * Rx2 :: anaRxAControl1
  */
 /* Rx2 :: anaRxAControl1 :: imode_vcm [15:15] */
 #define RX2_ANARXACONTROL1_IMODE_VCM_MASK                          0x8000
 #define RX2_ANARXACONTROL1_IMODE_VCM_ALIGN                         0
 #define RX2_ANARXACONTROL1_IMODE_VCM_BITS                          1
 #define RX2_ANARXACONTROL1_IMODE_VCM_SHIFT                         15
 
 /* Rx2 :: anaRxAControl1 :: imin_vcm [14:14] */
 #define RX2_ANARXACONTROL1_IMIN_VCM_MASK                           0x4000
 #define RX2_ANARXACONTROL1_IMIN_VCM_ALIGN                          0
 #define RX2_ANARXACONTROL1_IMIN_VCM_BITS                           1
 #define RX2_ANARXACONTROL1_IMIN_VCM_SHIFT                          14
 
 /* Rx2 :: anaRxAControl1 :: imax_sigdet [13:13] */
 #define RX2_ANARXACONTROL1_IMAX_SIGDET_MASK                        0x2000
 #define RX2_ANARXACONTROL1_IMAX_SIGDET_ALIGN                       0
 #define RX2_ANARXACONTROL1_IMAX_SIGDET_BITS                        1
 #define RX2_ANARXACONTROL1_IMAX_SIGDET_SHIFT                       13
 
 /* Rx2 :: anaRxAControl1 :: imode_sigdet [12:12] */
 #define RX2_ANARXACONTROL1_IMODE_SIGDET_MASK                       0x1000
 #define RX2_ANARXACONTROL1_IMODE_SIGDET_ALIGN                      0
 #define RX2_ANARXACONTROL1_IMODE_SIGDET_BITS                       1
 #define RX2_ANARXACONTROL1_IMODE_SIGDET_SHIFT                      12
 
 /* Rx2 :: anaRxAControl1 :: imin_sigdet [11:11] */
 #define RX2_ANARXACONTROL1_IMIN_SIGDET_MASK                        0x0800
 #define RX2_ANARXACONTROL1_IMIN_SIGDET_ALIGN                       0
 #define RX2_ANARXACONTROL1_IMIN_SIGDET_BITS                        1
 #define RX2_ANARXACONTROL1_IMIN_SIGDET_SHIFT                       11
 
 /* Rx2 :: anaRxAControl1 :: refh_rx [10:10] */
 #define RX2_ANARXACONTROL1_REFH_RX_MASK                            0x0400
 #define RX2_ANARXACONTROL1_REFH_RX_ALIGN                           0
 #define RX2_ANARXACONTROL1_REFH_RX_BITS                            1
 #define RX2_ANARXACONTROL1_REFH_RX_SHIFT                           10
 
 /* Rx2 :: anaRxAControl1 :: refl_rx [09:09] */
 #define RX2_ANARXACONTROL1_REFL_RX_MASK                            0x0200
 #define RX2_ANARXACONTROL1_REFL_RX_ALIGN                           0
 #define RX2_ANARXACONTROL1_REFL_RX_BITS                            1
 #define RX2_ANARXACONTROL1_REFL_RX_SHIFT                           9
 
 /* Rx2 :: anaRxAControl1 :: tport_en [08:08] */
 #define RX2_ANARXACONTROL1_TPORT_EN_MASK                           0x0100
 #define RX2_ANARXACONTROL1_TPORT_EN_ALIGN                          0
 #define RX2_ANARXACONTROL1_TPORT_EN_BITS                           1
 #define RX2_ANARXACONTROL1_TPORT_EN_SHIFT                          8
 
 /* Rx2 :: anaRxAControl1 :: vddrb_bgb [07:07] */
 #define RX2_ANARXACONTROL1_VDDRB_BGB_MASK                          0x0080
 #define RX2_ANARXACONTROL1_VDDRB_BGB_ALIGN                         0
 #define RX2_ANARXACONTROL1_VDDRB_BGB_BITS                          1
 #define RX2_ANARXACONTROL1_VDDRB_BGB_SHIFT                         7
 
 /* Rx2 :: anaRxAControl1 :: sig_pwrdn [06:06] */
 #define RX2_ANARXACONTROL1_SIG_PWRDN_MASK                          0x0040
 #define RX2_ANARXACONTROL1_SIG_PWRDN_ALIGN                         0
 #define RX2_ANARXACONTROL1_SIG_PWRDN_BITS                          1
 #define RX2_ANARXACONTROL1_SIG_PWRDN_SHIFT                         6
 
 /* Rx2 :: anaRxAControl1 :: offset_ctrl [05:03] */
 #define RX2_ANARXACONTROL1_OFFSET_CTRL_MASK                        0x0038
 #define RX2_ANARXACONTROL1_OFFSET_CTRL_ALIGN                       0
 #define RX2_ANARXACONTROL1_OFFSET_CTRL_BITS                        3
 #define RX2_ANARXACONTROL1_OFFSET_CTRL_SHIFT                       3
 
 /* Rx2 :: anaRxAControl1 :: offset_sel [02:02] */
 #define RX2_ANARXACONTROL1_OFFSET_SEL_MASK                         0x0004
 #define RX2_ANARXACONTROL1_OFFSET_SEL_ALIGN                        0
 #define RX2_ANARXACONTROL1_OFFSET_SEL_BITS                         1
 #define RX2_ANARXACONTROL1_OFFSET_SEL_SHIFT                        2
 
 /* Rx2 :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */
 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY1_MASK                    0x0002
 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN                   0
 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY1_BITS                    1
 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT                   1
 
 /* Rx2 :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */
 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY0_MASK                    0x0001
 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN                   0
 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY0_BITS                    1
 #define RX2_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT                   0
 
 
 /****************************************************************************
  * Rx2 :: anaRxAControl2
  */
 /* Rx2 :: anaRxAControl2 :: imax_ctat [15:15] */
 #define RX2_ANARXACONTROL2_IMAX_CTAT_MASK                          0x8000
 #define RX2_ANARXACONTROL2_IMAX_CTAT_ALIGN                         0
 #define RX2_ANARXACONTROL2_IMAX_CTAT_BITS                          1
 #define RX2_ANARXACONTROL2_IMAX_CTAT_SHIFT                         15
 
 /* Rx2 :: anaRxAControl2 :: imode_ctat [14:14] */
 #define RX2_ANARXACONTROL2_IMODE_CTAT_MASK                         0x4000
 #define RX2_ANARXACONTROL2_IMODE_CTAT_ALIGN                        0
 #define RX2_ANARXACONTROL2_IMODE_CTAT_BITS                         1
 #define RX2_ANARXACONTROL2_IMODE_CTAT_SHIFT                        14
 
 /* Rx2 :: anaRxAControl2 :: imin_ctat [13:13] */
 #define RX2_ANARXACONTROL2_IMIN_CTAT_MASK                          0x2000
 #define RX2_ANARXACONTROL2_IMIN_CTAT_ALIGN                         0
 #define RX2_ANARXACONTROL2_IMIN_CTAT_BITS                          1
 #define RX2_ANARXACONTROL2_IMIN_CTAT_SHIFT                         13
 
 /* Rx2 :: anaRxAControl2 :: imax_eqfl [12:12] */
 #define RX2_ANARXACONTROL2_IMAX_EQFL_MASK                          0x1000
 #define RX2_ANARXACONTROL2_IMAX_EQFL_ALIGN                         0
 #define RX2_ANARXACONTROL2_IMAX_EQFL_BITS                          1
 #define RX2_ANARXACONTROL2_IMAX_EQFL_SHIFT                         12
 
 /* Rx2 :: anaRxAControl2 :: imode_eqfl [11:11] */
 #define RX2_ANARXACONTROL2_IMODE_EQFL_MASK                         0x0800
 #define RX2_ANARXACONTROL2_IMODE_EQFL_ALIGN                        0
 #define RX2_ANARXACONTROL2_IMODE_EQFL_BITS                         1
 #define RX2_ANARXACONTROL2_IMODE_EQFL_SHIFT                        11
 
 /* Rx2 :: anaRxAControl2 :: imin_eqfl [10:10] */
 #define RX2_ANARXACONTROL2_IMIN_EQFL_MASK                          0x0400
 #define RX2_ANARXACONTROL2_IMIN_EQFL_ALIGN                         0
 #define RX2_ANARXACONTROL2_IMIN_EQFL_BITS                          1
 #define RX2_ANARXACONTROL2_IMIN_EQFL_SHIFT                         10
 
 /* Rx2 :: anaRxAControl2 :: imax_dfesum [09:09] */
 #define RX2_ANARXACONTROL2_IMAX_DFESUM_MASK                        0x0200
 #define RX2_ANARXACONTROL2_IMAX_DFESUM_ALIGN                       0
 #define RX2_ANARXACONTROL2_IMAX_DFESUM_BITS                        1
 #define RX2_ANARXACONTROL2_IMAX_DFESUM_SHIFT                       9
 
 /* Rx2 :: anaRxAControl2 :: imode_dfesum [08:08] */
 #define RX2_ANARXACONTROL2_IMODE_DFESUM_MASK                       0x0100
 #define RX2_ANARXACONTROL2_IMODE_DFESUM_ALIGN                      0
 #define RX2_ANARXACONTROL2_IMODE_DFESUM_BITS                       1
 #define RX2_ANARXACONTROL2_IMODE_DFESUM_SHIFT                      8
 
 /* Rx2 :: anaRxAControl2 :: imin_dfesum [07:07] */
 #define RX2_ANARXACONTROL2_IMIN_DFESUM_MASK                        0x0080
 #define RX2_ANARXACONTROL2_IMIN_DFESUM_ALIGN                       0
 #define RX2_ANARXACONTROL2_IMIN_DFESUM_BITS                        1
 #define RX2_ANARXACONTROL2_IMIN_DFESUM_SHIFT                       7
 
 /* Rx2 :: anaRxAControl2 :: imax_vga [06:06] */
 #define RX2_ANARXACONTROL2_IMAX_VGA_MASK                           0x0040
 #define RX2_ANARXACONTROL2_IMAX_VGA_ALIGN                          0
 #define RX2_ANARXACONTROL2_IMAX_VGA_BITS                           1
 #define RX2_ANARXACONTROL2_IMAX_VGA_SHIFT                          6
 
 /* Rx2 :: anaRxAControl2 :: imode_vga [05:05] */
 #define RX2_ANARXACONTROL2_IMODE_VGA_MASK                          0x0020
 #define RX2_ANARXACONTROL2_IMODE_VGA_ALIGN                         0
 #define RX2_ANARXACONTROL2_IMODE_VGA_BITS                          1
 #define RX2_ANARXACONTROL2_IMODE_VGA_SHIFT                         5
 
 /* Rx2 :: anaRxAControl2 :: imin_vga [04:04] */
 #define RX2_ANARXACONTROL2_IMIN_VGA_MASK                           0x0010
 #define RX2_ANARXACONTROL2_IMIN_VGA_ALIGN                          0
 #define RX2_ANARXACONTROL2_IMIN_VGA_BITS                           1
 #define RX2_ANARXACONTROL2_IMIN_VGA_SHIFT                          4
 
 /* Rx2 :: anaRxAControl2 :: imax_interp [03:03] */
 #define RX2_ANARXACONTROL2_IMAX_INTERP_MASK                        0x0008
 #define RX2_ANARXACONTROL2_IMAX_INTERP_ALIGN                       0
 #define RX2_ANARXACONTROL2_IMAX_INTERP_BITS                        1
 #define RX2_ANARXACONTROL2_IMAX_INTERP_SHIFT                       3
 
 /* Rx2 :: anaRxAControl2 :: imode_interp [02:02] */
 #define RX2_ANARXACONTROL2_IMODE_INTERP_MASK                       0x0004
 #define RX2_ANARXACONTROL2_IMODE_INTERP_ALIGN                      0
 #define RX2_ANARXACONTROL2_IMODE_INTERP_BITS                       1
 #define RX2_ANARXACONTROL2_IMODE_INTERP_SHIFT                      2
 
 /* Rx2 :: anaRxAControl2 :: imin_interp [01:01] */
 #define RX2_ANARXACONTROL2_IMIN_INTERP_MASK                        0x0002
 #define RX2_ANARXACONTROL2_IMIN_INTERP_ALIGN                       0
 #define RX2_ANARXACONTROL2_IMIN_INTERP_BITS                        1
 #define RX2_ANARXACONTROL2_IMIN_INTERP_SHIFT                       1
 
 /* Rx2 :: anaRxAControl2 :: imax_vcm [00:00] */
 #define RX2_ANARXACONTROL2_IMAX_VCM_MASK                           0x0001
 #define RX2_ANARXACONTROL2_IMAX_VCM_ALIGN                          0
 #define RX2_ANARXACONTROL2_IMAX_VCM_BITS                           1
 #define RX2_ANARXACONTROL2_IMAX_VCM_SHIFT                          0
 
 
 /****************************************************************************
  * Rx2 :: anaRxAControl3
  */
 /* Rx2 :: anaRxAControl3 :: en_clk16 [15:15] */
 #define RX2_ANARXACONTROL3_EN_CLK16_MASK                           0x8000
 #define RX2_ANARXACONTROL3_EN_CLK16_ALIGN                          0
 #define RX2_ANARXACONTROL3_EN_CLK16_BITS                           1
 #define RX2_ANARXACONTROL3_EN_CLK16_SHIFT                          15
 
 /* Rx2 :: anaRxAControl3 :: en_clk33 [14:14] */
 #define RX2_ANARXACONTROL3_EN_CLK33_MASK                           0x4000
 #define RX2_ANARXACONTROL3_EN_CLK33_ALIGN                          0
 #define RX2_ANARXACONTROL3_EN_CLK33_BITS                           1
 #define RX2_ANARXACONTROL3_EN_CLK33_SHIFT                          14
 
 /* Rx2 :: anaRxAControl3 :: en_vcctrl [13:13] */
 #define RX2_ANARXACONTROL3_EN_VCCTRL_MASK                          0x2000
 #define RX2_ANARXACONTROL3_EN_VCCTRL_ALIGN                         0
 #define RX2_ANARXACONTROL3_EN_VCCTRL_BITS                          1
 #define RX2_ANARXACONTROL3_EN_VCCTRL_SHIFT                         13
 
 /* Rx2 :: anaRxAControl3 :: sel_th4dfe1 [12:12] */
 #define RX2_ANARXACONTROL3_SEL_TH4DFE1_MASK                        0x1000
 #define RX2_ANARXACONTROL3_SEL_TH4DFE1_ALIGN                       0
 #define RX2_ANARXACONTROL3_SEL_TH4DFE1_BITS                        1
 #define RX2_ANARXACONTROL3_SEL_TH4DFE1_SHIFT                       12
 
 /* Rx2 :: anaRxAControl3 :: sel_th4dfe0 [11:11] */
 #define RX2_ANARXACONTROL3_SEL_TH4DFE0_MASK                        0x0800
 #define RX2_ANARXACONTROL3_SEL_TH4DFE0_ALIGN                       0
 #define RX2_ANARXACONTROL3_SEL_TH4DFE0_BITS                        1
 #define RX2_ANARXACONTROL3_SEL_TH4DFE0_SHIFT                       11
 
 /* Rx2 :: anaRxAControl3 :: selugbw1 [10:10] */
 #define RX2_ANARXACONTROL3_SELUGBW1_MASK                           0x0400
 #define RX2_ANARXACONTROL3_SELUGBW1_ALIGN                          0
 #define RX2_ANARXACONTROL3_SELUGBW1_BITS                           1
 #define RX2_ANARXACONTROL3_SELUGBW1_SHIFT                          10
 
 /* Rx2 :: anaRxAControl3 :: selugbw0 [09:09] */
 #define RX2_ANARXACONTROL3_SELUGBW0_MASK                           0x0200
 #define RX2_ANARXACONTROL3_SELUGBW0_ALIGN                          0
 #define RX2_ANARXACONTROL3_SELUGBW0_BITS                           1
 #define RX2_ANARXACONTROL3_SELUGBW0_SHIFT                          9
 
 /* Rx2 :: anaRxAControl3 :: imax_dfetap [08:08] */
 #define RX2_ANARXACONTROL3_IMAX_DFETAP_MASK                        0x0100
 #define RX2_ANARXACONTROL3_IMAX_DFETAP_ALIGN                       0
 #define RX2_ANARXACONTROL3_IMAX_DFETAP_BITS                        1
 #define RX2_ANARXACONTROL3_IMAX_DFETAP_SHIFT                       8
 
 /* Rx2 :: anaRxAControl3 :: imode_dfetap [07:07] */
 #define RX2_ANARXACONTROL3_IMODE_DFETAP_MASK                       0x0080
 #define RX2_ANARXACONTROL3_IMODE_DFETAP_ALIGN                      0
 #define RX2_ANARXACONTROL3_IMODE_DFETAP_BITS                       1
 #define RX2_ANARXACONTROL3_IMODE_DFETAP_SHIFT                      7
 
 /* Rx2 :: anaRxAControl3 :: imin_dfetap [06:06] */
 #define RX2_ANARXACONTROL3_IMIN_DFETAP_MASK                        0x0040
 #define RX2_ANARXACONTROL3_IMIN_DFETAP_ALIGN                       0
 #define RX2_ANARXACONTROL3_IMIN_DFETAP_BITS                        1
 #define RX2_ANARXACONTROL3_IMIN_DFETAP_SHIFT                       6
 
 /* Rx2 :: anaRxAControl3 :: imax_slcd2c [05:05] */
 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_MASK                        0x0020
 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_ALIGN                       0
 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_BITS                        1
 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_SHIFT                       5
 
 /* Rx2 :: anaRxAControl3 :: imode_slcd2c [04:04] */
 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_MASK                       0x0010
 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_ALIGN                      0
 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_BITS                       1
 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_SHIFT                      4
 
 /* Rx2 :: anaRxAControl3 :: imin_slcd2c [03:03] */
 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_MASK                        0x0008
 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_ALIGN                       0
 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_BITS                        1
 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_SHIFT                       3
 
 /* Rx2 :: anaRxAControl3 :: imax_dfevref [02:02] */
 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_MASK                       0x0004
 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_ALIGN                      0
 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_BITS                       1
 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_SHIFT                      2
 
 /* Rx2 :: anaRxAControl3 :: imode_dfevref [01:01] */
 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_MASK                      0x0002
 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_ALIGN                     0
 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_BITS                      1
 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_SHIFT                     1
 
 /* Rx2 :: anaRxAControl3 :: imin_dfevref [00:00] */
 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_MASK                       0x0001
 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_ALIGN                      0
 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_BITS                       1
 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_SHIFT                      0
 
 
 /****************************************************************************
  * Warpcore_USER_Rx3
  */
 /****************************************************************************
  * Rx3 :: anaRxStatus
  */
 /* union - case sigdet_Status [15:00] */
 /* Rx3 :: anaRxStatus :: cx4_sigdet [15:15] */
 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK              0x8000
 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN             0
 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS              1
 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT             15
 
 /* Rx3 :: anaRxStatus :: reserved0 [14:13] */
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK               0x6000
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN              0
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS               2
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT              13
 
 /* Rx3 :: anaRxStatus :: rxSeqDone [12:12] */
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK               0x1000
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN              0
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS               1
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT              12
 
 /* Rx3 :: anaRxStatus :: rx_sigdet_ll [11:11] */
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK            0x0800
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN           0
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS            1
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT           11
 
 /* Rx3 :: anaRxStatus :: cs4_sigdet_ll [10:10] */
 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK           0x0400
 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN          0
 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS           1
 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT          10
 
 /* Rx3 :: anaRxStatus :: rx_reset [09:09] */
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK                0x0200
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN               0
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS                1
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT               9
 
 /* Rx3 :: anaRxStatus :: rx_pwrdn [08:08] */
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK                0x0100
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN               0
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS                1
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT               8
 
 /* Rx3 :: anaRxStatus :: reserved1 [07:00] */
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK               0x00ff
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN              0
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS               8
 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT              0
 
 
 /* union - case sync_Status [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:11] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK                 0xf800
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN                0
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS                 5
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT                11
 
 /* Rx3 :: anaRxStatus :: test_acq_en [10:10] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK               0x0400
 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN              0
 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS               1
 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT              10
 
 /* Rx3 :: anaRxStatus :: reserved1 [09:09] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK                 0x0200
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN                0
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS                 1
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT                9
 
 /* Rx3 :: anaRxStatus :: rxSeqStart [08:08] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK                0x0100
 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN               0
 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS                1
 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT               8
 
 /* Rx3 :: anaRxStatus :: mux_comadj_sync_status [07:07] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK    0x0080
 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN   0
 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS    1
 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT   7
 
 /* Rx3 :: anaRxStatus :: sync_status [06:06] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK               0x0040
 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN              0
 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS               1
 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT              6
 
 /* Rx3 :: anaRxStatus :: rx_sigdet [05:05] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK                 0x0020
 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN                0
 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS                 1
 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT                5
 
 /* Rx3 :: anaRxStatus :: reserved2 [04:03] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK                 0x0018
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN                0
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS                 2
 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT                3
 
 /* Rx3 :: anaRxStatus :: saturate_status [02:02] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK           0x0004
 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN          0
 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS           1
 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT          2
 
 /* Rx3 :: anaRxStatus :: cx4_sigdet [01:01] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK                0x0002
 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN               0
 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS                1
 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT               1
 
 /* Rx3 :: anaRxStatus :: rxSeqDone [00:00] */
 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK                 0x0001
 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN                0
 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS                 1
 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT                0
 
 
 /* union - case rxTestSel_0 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:10] */
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK                 0xfc00
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN                0
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS                 6
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT                10
 
 /* Rx3 :: anaRxStatus :: indck_mode_en [09:09] */
 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK             0x0200
 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN            0
 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS             1
 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT            9
 
 /* Rx3 :: anaRxStatus :: pci_mode_en [08:08] */
 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK               0x0100
 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN              0
 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS               1
 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT              8
 
 /* Rx3 :: anaRxStatus :: rx_polarity [07:07] */
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK               0x0080
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN              0
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS               1
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT              7
 
 /* Rx3 :: anaRxStatus :: rxpol_flip [06:06] */
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                0x0040
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN               0
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                1
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT               6
 
 /* Rx3 :: anaRxStatus :: comma_mask [05:05] */
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK                0x0020
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN               0
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS                1
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT               5
 
 /* Rx3 :: anaRxStatus :: link_en_r [04:04] */
 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK                 0x0010
 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                0
 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS                 1
 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                4
 
 /* Rx3 :: anaRxStatus :: comma_adj_en [03:03] */
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK              0x0008
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN             0
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS              1
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT             3
 
 /* Rx3 :: anaRxStatus :: comma_adj_en_ext [02:02] */
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK          0x0004
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN         0
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS          1
 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT         2
 
 /* Rx3 :: anaRxStatus :: reserved1 [01:00] */
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK                 0x0003
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN                0
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS                 2
 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT                0
 
 
 /* union - case rxTestSel_1 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */
 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK                 0xffe0
 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN                0
 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS                 11
 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT                5
 
 /* Rx3 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK             0x0010
 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN            0
 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS             1
 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT            4
 
 /* Rx3 :: anaRxStatus :: freq_sel_PC [03:03] */
 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK               0x0008
 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN              0
 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS               1
 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT              3
 
 /* Rx3 :: anaRxStatus :: freq_sel_SM [02:02] */
 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK               0x0004
 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN              0
 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS               1
 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT              2
 
 /* Rx3 :: anaRxStatus :: integ_mode_SM [01:00] */
 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK             0x0003
 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN            0
 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS             2
 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT            0
 
 
 /* union - case scale_Status [15:00] */
 /* Rx3 :: anaRxStatus :: prop_scale [15:12] */
 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK               0xf000
 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN              0
 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS               4
 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT              12
 
 /* Rx3 :: anaRxStatus :: integ_scale [11:08] */
 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK              0x0f00
 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN             0
 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS              4
 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT             8
 
 /* Rx3 :: anaRxStatus :: prop_scale_acq [07:04] */
 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK           0x00f0
 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN          0
 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS           4
 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT          4
 
 /* Rx3 :: anaRxStatus :: integ_scale_acq [03:00] */
 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK          0x000f
 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN         0
 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS          4
 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT         0
 
 
 /* union - case adc_CdrStatus1 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:07] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK              0xff80
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS              9
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT             7
 
 /* Rx3 :: anaRxStatus :: rxMuxCkSel [06:06] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK             0x0040
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS             1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT            6
 
 /* Rx3 :: anaRxStatus :: glpbk_combo [05:05] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK            0x0020
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN           0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS            1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT           5
 
 /* Rx3 :: anaRxStatus :: clockSwitchSel [04:04] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK         0x0010
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN        0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS         1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT        4
 
 /* Rx3 :: anaRxStatus :: rxck_tst [03:03] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK               0x0008
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN              0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS               1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT              3
 
 /* Rx3 :: anaRxStatus :: rxck_i [02:02] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK                 0x0004
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS                 1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                2
 
 /* Rx3 :: anaRxStatus :: refclk [01:01] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK                 0x0002
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS                 1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                1
 
 /* Rx3 :: anaRxStatus :: pll_bypass [00:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK             0x0001
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS             1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT            0
 
 
 /* union - case adc_CdrStatus2 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:06] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK              0xffc0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS              10
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT             6
 
 /* Rx3 :: anaRxStatus :: rxMuxCkSel [05:05] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK             0x0020
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS             1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT            5
 
 /* Rx3 :: anaRxStatus :: rxSeqStart [04:04] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK             0x0010
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS             1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT            4
 
 /* Rx3 :: anaRxStatus :: reserved1 [03:01] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK              0x000e
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS              3
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT             1
 
 /* Rx3 :: anaRxStatus :: rxSeqDone [00:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK              0x0001
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS              1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT             0
 
 
 /* union - case adc_CdrStatus3 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:04] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK              0xfff0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS              12
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT             4
 
 /* Rx3 :: anaRxStatus :: rxSeqStart [03:03] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK             0x0008
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS             1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT            3
 
 /* Rx3 :: anaRxStatus :: reserved1 [02:01] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK              0x0006
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS              2
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT             1
 
 /* Rx3 :: anaRxStatus :: allow_increment_PC [00:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK     0x0001
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN    0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS     1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT    0
 
 
 /* union - case adc_CdrStatus4 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:08] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK              0xff00
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS              8
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT             8
 
 /* Rx3 :: anaRxStatus :: rx_pwrdn [07:07] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK               0x0080
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN              0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS               1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT              7
 
 /* Rx3 :: anaRxStatus :: freq_sel [06:06] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK               0x0040
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN              0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS               1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT              6
 
 /* Rx3 :: anaRxStatus :: pll_lock_rstb [05:05] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK          0x0020
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN         0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS          1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT         5
 
 /* Rx3 :: anaRxStatus :: pwrdn [04:04] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK                  0x0010
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                 0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS                  1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                 4
 
 /* Rx3 :: anaRxStatus :: reserved1 [03:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK              0x000f
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS              4
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT             0
 
 
 /* union - case adc_CdrStatus5 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK              0xffff
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS              16
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT             0
 
 
 /* union - case adc_CdrStatus6 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK              0xffe0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS              11
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT             5
 
 /* Rx3 :: anaRxStatus :: rx_reset [04:04] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK               0x0010
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN              0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS               1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT              4
 
 /* Rx3 :: anaRxStatus :: rx_pwrdn [03:03] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK               0x0008
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN              0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS               1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT              3
 
 /* Rx3 :: anaRxStatus :: reset_anlg [02:02] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK             0x0004
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS             1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT            2
 
 /* Rx3 :: anaRxStatus :: pwrdn_rx [01:01] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK               0x0002
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN              0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS               1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT              1
 
 /* Rx3 :: anaRxStatus :: pwrdn_pll [00:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK              0x0001
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS              1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT             0
 
 
 /* union - case adc_CdrStatus7e [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK             0xffe0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS             11
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT            5
 
 /* Rx3 :: anaRxStatus :: rxck0_even [04:04] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK            0x0010
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN           0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS            1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT           4
 
 /* Rx3 :: anaRxStatus :: rxck1_even [03:03] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK            0x0008
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN           0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS            1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT           3
 
 /* Rx3 :: anaRxStatus :: comdet_even [02:02] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK           0x0004
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN          0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS           1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT          2
 
 /* Rx3 :: anaRxStatus :: en_cdet_even [01:01] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK          0x0002
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN         0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS          1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT         1
 
 /* Rx3 :: anaRxStatus :: comma_adj_en_even [00:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK     0x0001
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN    0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS     1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT    0
 
 
 /* union - case adc_CdrStatus7o [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK             0xffe0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS             11
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT            5
 
 /* Rx3 :: anaRxStatus :: rxck0_odd [04:04] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK             0x0010
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS             1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT            4
 
 /* Rx3 :: anaRxStatus :: rxck1_odd [03:03] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK             0x0008
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS             1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT            3
 
 /* Rx3 :: anaRxStatus :: comdet_odd [02:02] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK            0x0004
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN           0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS            1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT           2
 
 /* Rx3 :: anaRxStatus :: en_cdet_odd [01:01] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK           0x0002
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN          0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS           1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT          1
 
 /* Rx3 :: anaRxStatus :: comma_adj_en_odd [00:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK      0x0001
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN     0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS      1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT     0
 
 
 /* union - case adc_CdrStatus8 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:01] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK              0xfffe
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS              15
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT             1
 
 /* Rx3 :: anaRxStatus :: sigdet [00:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK                 0x0001
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS                 1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                0
 
 
 /* union - case adc_CdrStatus9 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK              0xffff
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS              16
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT             0
 
 
 /* union - case adc_CdrStatus10 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:07] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK             0xff80
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS             9
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT            7
 
 /* Rx3 :: anaRxStatus :: prbs_en [06:06] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK               0x0040
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN              0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS               1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT              6
 
 /* Rx3 :: anaRxStatus :: rstb_tst [05:05] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK              0x0020
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN             0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS              1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT             5
 
 /* Rx3 :: anaRxStatus :: reserved1 [04:04] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK             0x0010
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS             1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT            4
 
 /* Rx3 :: anaRxStatus :: prbs_state [03:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK            0x000f
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN           0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS            4
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT           0
 
 
 /* union - case adc_CdrStatus11 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK             0xffff
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS             16
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT            0
 
 
 /* union - case adc_CdrStatus12_1 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:06] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK           0xffc0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN          0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS           10
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT          6
 
 /* Rx3 :: anaRxStatus :: enable4 [05:05] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK             0x0020
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN            0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS             1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT            5
 
 /* Rx3 :: anaRxStatus :: radr_test [04:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK           0x001f
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN          0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS           5
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT          0
 
 
 /* union - case adc_CdrStatus12_2 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK           0xffe0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN          0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS           11
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT          5
 
 /* Rx3 :: anaRxStatus :: wadr_test [04:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK           0x001f
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN          0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS           5
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT          0
 
 
 /* union - case adc_CdrStatus12_3 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:06] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK           0xffc0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN          0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS           10
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT          6
 
 /* Rx3 :: anaRxStatus :: rxck_66B_tmux [05:05] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK       0x0020
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN      0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS       1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT      5
 
 /* Rx3 :: anaRxStatus :: rstb_66B [04:04] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK            0x0010
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN           0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS            1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT           4
 
 /* Rx3 :: anaRxStatus :: prstb_66B_mux [03:03] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK       0x0008
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN      0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS       1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT      3
 
 /* Rx3 :: anaRxStatus :: rxck_i66_tmux [02:02] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK       0x0004
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN      0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS       1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT      2
 
 /* Rx3 :: anaRxStatus :: rstb_i66 [01:01] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK            0x0002
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN           0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS            1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT           1
 
 /* Rx3 :: anaRxStatus :: prstb_i66_mux [00:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK       0x0001
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN      0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS       1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT      0
 
 
 /* union - case adc_CdrStatus12_4 [15:00] */
 /* Rx3 :: anaRxStatus :: reserved0 [15:04] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK           0xfff0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN          0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS           12
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT          4
 
 /* Rx3 :: anaRxStatus :: rfifo_error_r [03:02] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK       0x000c
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN      0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS       2
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT      2
 
 /* Rx3 :: anaRxStatus :: rfifo_unflow [01:01] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK        0x0002
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN       0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS        1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT       1
 
 /* Rx3 :: anaRxStatus :: rfifo_ovflow [00:00] */
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK        0x0001
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN       0
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS        1
 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT       0
 
 
 /* union - case integ_Status [15:00] */
 /* Rx3 :: anaRxStatus :: integ_status [15:00] */
 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK             0xffff
 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN            0
 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS             16
 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT            0
 
 
 /* union - case vco_Status [15:00] */
 /* Rx3 :: anaRxStatus :: vco_status [15:00] */
 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK                 0xffff
 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN                0
 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS                 16
 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT                0
 
 
 /* union - case prbs_Status [15:00] */
 /* Rx3 :: anaRxStatus :: prbs_lock [15:15] */
 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK                 0x8000
 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                0
 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS                 1
 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                15
 
 /* Rx3 :: anaRxStatus :: prbs_stky [14:14] */
 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK                 0x4000
 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN                0
 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS                 1
 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT                14
 
 /* Rx3 :: anaRxStatus :: ptbs_errors [13:00] */
 #define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK               0x3fff
 #define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN              0
 #define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS               14
 #define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT              0
 
 
 
 /****************************************************************************
  * Rx3 :: anaRxControl
  */
 /* Rx3 :: anaRxControl :: reserved0 [15:10] */
 #define RX3_ANARXCONTROL_RESERVED0_MASK                            0xfc00
 #define RX3_ANARXCONTROL_RESERVED0_ALIGN                           0
 #define RX3_ANARXCONTROL_RESERVED0_BITS                            6
 #define RX3_ANARXCONTROL_RESERVED0_SHIFT                           10
 
 /* Rx3 :: anaRxControl :: override_sigdet_en [09:09] */
 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK                   0x0200
 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN                  0
 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS                   1
 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT                  9
 
 /* Rx3 :: anaRxControl :: override_sigdet_val [08:08] */
 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK                  0x0100
 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN                 0
 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS                  1
 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT                 8
 
 /* Rx3 :: anaRxControl :: reserved1 [07:03] */
 #define RX3_ANARXCONTROL_RESERVED1_MASK                            0x00f8
 #define RX3_ANARXCONTROL_RESERVED1_ALIGN                           0
 #define RX3_ANARXCONTROL_RESERVED1_BITS                            5
 #define RX3_ANARXCONTROL_RESERVED1_SHIFT                           3
 
 /* Rx3 :: anaRxControl :: status_sel [02:00] */
 #define RX3_ANARXCONTROL_STATUS_SEL_MASK                           0x0007
 #define RX3_ANARXCONTROL_STATUS_SEL_ALIGN                          0
 #define RX3_ANARXCONTROL_STATUS_SEL_BITS                           3
 #define RX3_ANARXCONTROL_STATUS_SEL_SHIFT                          0
 #define RX3_ANARXCONTROL_STATUS_SEL_sigdetStatus                   0
 #define RX3_ANARXCONTROL_STATUS_SEL_syncStatus                     1
 #define RX3_ANARXCONTROL_STATUS_SEL_rxTestSel                      2
 #define RX3_ANARXCONTROL_STATUS_SEL_scaleStatus                    3
 #define RX3_ANARXCONTROL_STATUS_SEL_adcCdrStatus                   4
 #define RX3_ANARXCONTROL_STATUS_SEL_integStatus                    5
 #define RX3_ANARXCONTROL_STATUS_SEL_vcoStatus                      6
 #define RX3_ANARXCONTROL_STATUS_SEL_prbsStatus                     7
 
 
 /****************************************************************************
  * Rx3 :: anaRxTest
  */
 /* Rx3 :: anaRxTest :: sigdet_mux_SM [15:12] */
 #define RX3_ANARXTEST_SIGDET_MUX_SM_MASK                           0xf000
 #define RX3_ANARXTEST_SIGDET_MUX_SM_ALIGN                          0
 #define RX3_ANARXTEST_SIGDET_MUX_SM_BITS                           4
 #define RX3_ANARXTEST_SIGDET_MUX_SM_SHIFT                          12
 
 /* Rx3 :: anaRxTest :: reserved0 [11:09] */
 #define RX3_ANARXTEST_RESERVED0_MASK                               0x0e00
 #define RX3_ANARXTEST_RESERVED0_ALIGN                              0
 #define RX3_ANARXTEST_RESERVED0_BITS                               3
 #define RX3_ANARXTEST_RESERVED0_SHIFT                              9
 
 /* Rx3 :: anaRxTest :: tpctrl_SM [08:04] */
 #define RX3_ANARXTEST_TPCTRL_SM_MASK                               0x01f0
 #define RX3_ANARXTEST_TPCTRL_SM_ALIGN                              0
 #define RX3_ANARXTEST_TPCTRL_SM_BITS                               5
 #define RX3_ANARXTEST_TPCTRL_SM_SHIFT                              4
 
 /* Rx3 :: anaRxTest :: testMuxSelect_SM [03:00] */
 #define RX3_ANARXTEST_TESTMUXSELECT_SM_MASK                        0x000f
 #define RX3_ANARXTEST_TESTMUXSELECT_SM_ALIGN                       0
 #define RX3_ANARXTEST_TESTMUXSELECT_SM_BITS                        4
 #define RX3_ANARXTEST_TESTMUXSELECT_SM_SHIFT                       0
 
 
 /****************************************************************************
  * Rx3 :: anaRxControl1G
  */
 /* Rx3 :: anaRxControl1G :: fpat_md [15:15] */
 #define RX3_ANARXCONTROL1G_FPAT_MD_MASK                            0x8000
 #define RX3_ANARXCONTROL1G_FPAT_MD_ALIGN                           0
 #define RX3_ANARXCONTROL1G_FPAT_MD_BITS                            1
 #define RX3_ANARXCONTROL1G_FPAT_MD_SHIFT                           15
 
 /* Rx3 :: anaRxControl1G :: pkt_count_en [14:14] */
 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_MASK                       0x4000
 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN                      0
 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_BITS                       1
 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT                      14
 
 /* Rx3 :: anaRxControl1G :: staMuxRegDis [13:13] */
 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_MASK                       0x2000
 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_ALIGN                      0
 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_BITS                       1
 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_SHIFT                      13
 
 /* Rx3 :: anaRxControl1G :: prbs_clr_dis [12:12] */
 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_MASK                       0x1000
 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN                      0
 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_BITS                       1
 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT                      12
 
 /* Rx3 :: anaRxControl1G :: rxd_dec_sel [11:11] */
 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_MASK                        0x0800
 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN                       0
 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_BITS                        1
 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT                       11
 
 /* Rx3 :: anaRxControl1G :: cgbad_tst [10:10] */
 #define RX3_ANARXCONTROL1G_CGBAD_TST_MASK                          0x0400
 #define RX3_ANARXCONTROL1G_CGBAD_TST_ALIGN                         0
 #define RX3_ANARXCONTROL1G_CGBAD_TST_BITS                          1
 #define RX3_ANARXCONTROL1G_CGBAD_TST_SHIFT                         10
 
 /* Rx3 :: anaRxControl1G :: Emon_en [09:09] */
 #define RX3_ANARXCONTROL1G_EMON_EN_MASK                            0x0200
 #define RX3_ANARXCONTROL1G_EMON_EN_ALIGN                           0
 #define RX3_ANARXCONTROL1G_EMON_EN_BITS                            1
 #define RX3_ANARXCONTROL1G_EMON_EN_SHIFT                           9
 
 /* Rx3 :: anaRxControl1G :: prbs_en [08:08] */
 #define RX3_ANARXCONTROL1G_PRBS_EN_MASK                            0x0100
 #define RX3_ANARXCONTROL1G_PRBS_EN_ALIGN                           0
 #define RX3_ANARXCONTROL1G_PRBS_EN_BITS                            1
 #define RX3_ANARXCONTROL1G_PRBS_EN_SHIFT                           8
 
 /* Rx3 :: anaRxControl1G :: cgbad_en [07:07] */
 #define RX3_ANARXCONTROL1G_CGBAD_EN_MASK                           0x0080
 #define RX3_ANARXCONTROL1G_CGBAD_EN_ALIGN                          0
 #define RX3_ANARXCONTROL1G_CGBAD_EN_BITS                           1
 #define RX3_ANARXCONTROL1G_CGBAD_EN_SHIFT                          7
 
 /* Rx3 :: anaRxControl1G :: cstretch [06:06] */
 #define RX3_ANARXCONTROL1G_CSTRETCH_MASK                           0x0040
 #define RX3_ANARXCONTROL1G_CSTRETCH_ALIGN                          0
 #define RX3_ANARXCONTROL1G_CSTRETCH_BITS                           1
 #define RX3_ANARXCONTROL1G_CSTRETCH_SHIFT                          6
 
 /* Rx3 :: anaRxControl1G :: comma_low_byte_SM [05:05] */
 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK                  0x0020
 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN                 0
 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS                  1
 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT                 5
 
 /* Rx3 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */
 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK               0x0010
 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN              0
 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS               1
 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT              4
 
 /* Rx3 :: anaRxControl1G :: reserved0 [03:02] */
 #define RX3_ANARXCONTROL1G_RESERVED0_MASK                          0x000c
 #define RX3_ANARXCONTROL1G_RESERVED0_ALIGN                         0
 #define RX3_ANARXCONTROL1G_RESERVED0_BITS                          2
 #define RX3_ANARXCONTROL1G_RESERVED0_SHIFT                         2
 
 /* Rx3 :: anaRxControl1G :: freq_sel_force [01:01] */
 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK                     0x0002
 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN                    0
 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS                     1
 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT                    1
 
 /* Rx3 :: anaRxControl1G :: freq_sel [00:00] */
 #define RX3_ANARXCONTROL1G_FREQ_SEL_MASK                           0x0001
 #define RX3_ANARXCONTROL1G_FREQ_SEL_ALIGN                          0
 #define RX3_ANARXCONTROL1G_FREQ_SEL_BITS                           1
 #define RX3_ANARXCONTROL1G_FREQ_SEL_SHIFT                          0
 
 
 /****************************************************************************
  * Rx3 :: anaRxControlPci
  */
 /* Rx3 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK                0x8000
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN               0
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS                1
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT               15
 
 /* Rx3 :: anaRxControlPci :: comma_mask_force_r [14:14] */
 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK                0x4000
 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN               0
 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS                1
 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT               14
 
 /* Rx3 :: anaRxControlPci :: comma_mask_r [13:13] */
 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_MASK                      0x2000
 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN                     0
 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_BITS                      1
 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT                     13
 
 /* Rx3 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK         0x1000
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN        0
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS         1
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT        12
 
 /* Rx3 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK            0x0800
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN           0
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS            1
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT           11
 
 /* Rx3 :: anaRxControlPci :: sync_status_force_r [10:10] */
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK               0x0400
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN              0
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS               1
 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT              10
 
 /* Rx3 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK         0x0200
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN        0
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS         1
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT        9
 
 /* Rx3 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK        0x0100
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN       0
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS        1
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT       8
 
 /* Rx3 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK           0x0080
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN          0
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS           1
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT          7
 
 /* Rx3 :: anaRxControlPci :: comma_adj_en_r [06:06] */
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK                    0x0040
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN                   0
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS                    1
 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT                   6
 
 /* Rx3 :: anaRxControlPci :: link_en_force_SM [05:05] */
 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK                  0x0020
 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN                 0
 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS                  1
 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT                 5
 
 /* Rx3 :: anaRxControlPci :: link_en_r [04:04] */
 #define RX3_ANARXCONTROLPCI_LINK_EN_R_MASK                         0x0010
 #define RX3_ANARXCONTROLPCI_LINK_EN_R_ALIGN                        0
 #define RX3_ANARXCONTROLPCI_LINK_EN_R_BITS                         1
 #define RX3_ANARXCONTROLPCI_LINK_EN_R_SHIFT                        4
 
 /* Rx3 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK              0x0008
 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN             0
 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS              1
 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT             3
 
 /* Rx3 :: anaRxControlPci :: rx_polarity_r [02:02] */
 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_MASK                     0x0004
 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN                    0
 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_BITS                     1
 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT                    2
 
 /* Rx3 :: anaRxControlPci :: integ_mode_SM [01:00] */
 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_MASK                     0x0003
 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN                    0
 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_BITS                     2
 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT                    0
 
 
 /****************************************************************************
  * Rx3 :: anaRxAstatus
  */
 /* Rx3 :: anaRxAstatus :: sigdet [15:15] */
 #define RX3_ANARXASTATUS_SIGDET_MASK                               0x8000
 #define RX3_ANARXASTATUS_SIGDET_ALIGN                              0
 #define RX3_ANARXASTATUS_SIGDET_BITS                               1
 #define RX3_ANARXASTATUS_SIGDET_SHIFT                              15
 
 /* Rx3 :: anaRxAstatus :: rx_pf [14:11] */
 #define RX3_ANARXASTATUS_RX_PF_MASK                                0x7800
 #define RX3_ANARXASTATUS_RX_PF_ALIGN                               0
 #define RX3_ANARXASTATUS_RX_PF_BITS                                4
 #define RX3_ANARXASTATUS_RX_PF_SHIFT                               11
 
 /* Rx3 :: anaRxAstatus :: tap1_dfe_gray [10:05] */
 #define RX3_ANARXASTATUS_TAP1_DFE_GRAY_MASK                        0x07e0
 #define RX3_ANARXASTATUS_TAP1_DFE_GRAY_ALIGN                       0
 #define RX3_ANARXASTATUS_TAP1_DFE_GRAY_BITS                        6
 #define RX3_ANARXASTATUS_TAP1_DFE_GRAY_SHIFT                       5
 
 /* Rx3 :: anaRxAstatus :: vga [04:00] */
 #define RX3_ANARXASTATUS_VGA_MASK                                  0x001f
 #define RX3_ANARXASTATUS_VGA_ALIGN                                 0
 #define RX3_ANARXASTATUS_VGA_BITS                                  5
 #define RX3_ANARXASTATUS_VGA_SHIFT                                 0
 
 
 /****************************************************************************
  * Rx3 :: anaRxAControl1
  */
 /* Rx3 :: anaRxAControl1 :: imode_vcm [15:15] */
 #define RX3_ANARXACONTROL1_IMODE_VCM_MASK                          0x8000
 #define RX3_ANARXACONTROL1_IMODE_VCM_ALIGN                         0
 #define RX3_ANARXACONTROL1_IMODE_VCM_BITS                          1
 #define RX3_ANARXACONTROL1_IMODE_VCM_SHIFT                         15
 
 /* Rx3 :: anaRxAControl1 :: imin_vcm [14:14] */
 #define RX3_ANARXACONTROL1_IMIN_VCM_MASK                           0x4000
 #define RX3_ANARXACONTROL1_IMIN_VCM_ALIGN                          0
 #define RX3_ANARXACONTROL1_IMIN_VCM_BITS                           1
 #define RX3_ANARXACONTROL1_IMIN_VCM_SHIFT                          14
 
 /* Rx3 :: anaRxAControl1 :: imax_sigdet [13:13] */
 #define RX3_ANARXACONTROL1_IMAX_SIGDET_MASK                        0x2000
 #define RX3_ANARXACONTROL1_IMAX_SIGDET_ALIGN                       0
 #define RX3_ANARXACONTROL1_IMAX_SIGDET_BITS                        1
 #define RX3_ANARXACONTROL1_IMAX_SIGDET_SHIFT                       13
 
 /* Rx3 :: anaRxAControl1 :: imode_sigdet [12:12] */
 #define RX3_ANARXACONTROL1_IMODE_SIGDET_MASK                       0x1000
 #define RX3_ANARXACONTROL1_IMODE_SIGDET_ALIGN                      0
 #define RX3_ANARXACONTROL1_IMODE_SIGDET_BITS                       1
 #define RX3_ANARXACONTROL1_IMODE_SIGDET_SHIFT                      12
 
 /* Rx3 :: anaRxAControl1 :: imin_sigdet [11:11] */
 #define RX3_ANARXACONTROL1_IMIN_SIGDET_MASK                        0x0800
 #define RX3_ANARXACONTROL1_IMIN_SIGDET_ALIGN                       0
 #define RX3_ANARXACONTROL1_IMIN_SIGDET_BITS                        1
 #define RX3_ANARXACONTROL1_IMIN_SIGDET_SHIFT                       11
 
 /* Rx3 :: anaRxAControl1 :: refh_rx [10:10] */
 #define RX3_ANARXACONTROL1_REFH_RX_MASK                            0x0400
 #define RX3_ANARXACONTROL1_REFH_RX_ALIGN                           0
 #define RX3_ANARXACONTROL1_REFH_RX_BITS                            1
 #define RX3_ANARXACONTROL1_REFH_RX_SHIFT                           10
 
 /* Rx3 :: anaRxAControl1 :: refl_rx [09:09] */
 #define RX3_ANARXACONTROL1_REFL_RX_MASK                            0x0200
 #define RX3_ANARXACONTROL1_REFL_RX_ALIGN                           0
 #define RX3_ANARXACONTROL1_REFL_RX_BITS                            1
 #define RX3_ANARXACONTROL1_REFL_RX_SHIFT                           9
 
 /* Rx3 :: anaRxAControl1 :: tport_en [08:08] */
 #define RX3_ANARXACONTROL1_TPORT_EN_MASK                           0x0100
 #define RX3_ANARXACONTROL1_TPORT_EN_ALIGN                          0
 #define RX3_ANARXACONTROL1_TPORT_EN_BITS                           1
 #define RX3_ANARXACONTROL1_TPORT_EN_SHIFT                          8
 
 /* Rx3 :: anaRxAControl1 :: vddrb_bgb [07:07] */
 #define RX3_ANARXACONTROL1_VDDRB_BGB_MASK                          0x0080
 #define RX3_ANARXACONTROL1_VDDRB_BGB_ALIGN                         0
 #define RX3_ANARXACONTROL1_VDDRB_BGB_BITS                          1
 #define RX3_ANARXACONTROL1_VDDRB_BGB_SHIFT                         7
 
 /* Rx3 :: anaRxAControl1 :: sig_pwrdn [06:06] */
 #define RX3_ANARXACONTROL1_SIG_PWRDN_MASK                          0x0040
 #define RX3_ANARXACONTROL1_SIG_PWRDN_ALIGN                         0
 #define RX3_ANARXACONTROL1_SIG_PWRDN_BITS                          1
 #define RX3_ANARXACONTROL1_SIG_PWRDN_SHIFT                         6
 
 /* Rx3 :: anaRxAControl1 :: offset_ctrl [05:03] */
 #define RX3_ANARXACONTROL1_OFFSET_CTRL_MASK                        0x0038
 #define RX3_ANARXACONTROL1_OFFSET_CTRL_ALIGN                       0
 #define RX3_ANARXACONTROL1_OFFSET_CTRL_BITS                        3
 #define RX3_ANARXACONTROL1_OFFSET_CTRL_SHIFT                       3
 
 /* Rx3 :: anaRxAControl1 :: offset_sel [02:02] */
 #define RX3_ANARXACONTROL1_OFFSET_SEL_MASK                         0x0004
 #define RX3_ANARXACONTROL1_OFFSET_SEL_ALIGN                        0
 #define RX3_ANARXACONTROL1_OFFSET_SEL_BITS                         1
 #define RX3_ANARXACONTROL1_OFFSET_SEL_SHIFT                        2
 
 /* Rx3 :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */
 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY1_MASK                    0x0002
 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN                   0
 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY1_BITS                    1
 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT                   1
 
 /* Rx3 :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */
 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY0_MASK                    0x0001
 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN                   0
 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY0_BITS                    1
 #define RX3_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT                   0
 
 
 /****************************************************************************
  * Rx3 :: anaRxAControl2
  */
 /* Rx3 :: anaRxAControl2 :: imax_ctat [15:15] */
 #define RX3_ANARXACONTROL2_IMAX_CTAT_MASK                          0x8000
 #define RX3_ANARXACONTROL2_IMAX_CTAT_ALIGN                         0
 #define RX3_ANARXACONTROL2_IMAX_CTAT_BITS                          1
 #define RX3_ANARXACONTROL2_IMAX_CTAT_SHIFT                         15
 
 /* Rx3 :: anaRxAControl2 :: imode_ctat [14:14] */
 #define RX3_ANARXACONTROL2_IMODE_CTAT_MASK                         0x4000
 #define RX3_ANARXACONTROL2_IMODE_CTAT_ALIGN                        0
 #define RX3_ANARXACONTROL2_IMODE_CTAT_BITS                         1
 #define RX3_ANARXACONTROL2_IMODE_CTAT_SHIFT                        14
 
 /* Rx3 :: anaRxAControl2 :: imin_ctat [13:13] */
 #define RX3_ANARXACONTROL2_IMIN_CTAT_MASK                          0x2000
 #define RX3_ANARXACONTROL2_IMIN_CTAT_ALIGN                         0
 #define RX3_ANARXACONTROL2_IMIN_CTAT_BITS                          1
 #define RX3_ANARXACONTROL2_IMIN_CTAT_SHIFT                         13
 
 /* Rx3 :: anaRxAControl2 :: imax_eqfl [12:12] */
 #define RX3_ANARXACONTROL2_IMAX_EQFL_MASK                          0x1000
 #define RX3_ANARXACONTROL2_IMAX_EQFL_ALIGN                         0
 #define RX3_ANARXACONTROL2_IMAX_EQFL_BITS                          1
 #define RX3_ANARXACONTROL2_IMAX_EQFL_SHIFT                         12
 
 /* Rx3 :: anaRxAControl2 :: imode_eqfl [11:11] */
 #define RX3_ANARXACONTROL2_IMODE_EQFL_MASK                         0x0800
 #define RX3_ANARXACONTROL2_IMODE_EQFL_ALIGN                        0
 #define RX3_ANARXACONTROL2_IMODE_EQFL_BITS                         1
 #define RX3_ANARXACONTROL2_IMODE_EQFL_SHIFT                        11
 
 /* Rx3 :: anaRxAControl2 :: imin_eqfl [10:10] */
 #define RX3_ANARXACONTROL2_IMIN_EQFL_MASK                          0x0400
 #define RX3_ANARXACONTROL2_IMIN_EQFL_ALIGN                         0
 #define RX3_ANARXACONTROL2_IMIN_EQFL_BITS                          1
 #define RX3_ANARXACONTROL2_IMIN_EQFL_SHIFT                         10
 
 /* Rx3 :: anaRxAControl2 :: imax_dfesum [09:09] */
 #define RX3_ANARXACONTROL2_IMAX_DFESUM_MASK                        0x0200
 #define RX3_ANARXACONTROL2_IMAX_DFESUM_ALIGN                       0
 #define RX3_ANARXACONTROL2_IMAX_DFESUM_BITS                        1
 #define RX3_ANARXACONTROL2_IMAX_DFESUM_SHIFT                       9
 
 /* Rx3 :: anaRxAControl2 :: imode_dfesum [08:08] */
 #define RX3_ANARXACONTROL2_IMODE_DFESUM_MASK                       0x0100
 #define RX3_ANARXACONTROL2_IMODE_DFESUM_ALIGN                      0
 #define RX3_ANARXACONTROL2_IMODE_DFESUM_BITS                       1
 #define RX3_ANARXACONTROL2_IMODE_DFESUM_SHIFT                      8
 
 /* Rx3 :: anaRxAControl2 :: imin_dfesum [07:07] */
 #define RX3_ANARXACONTROL2_IMIN_DFESUM_MASK                        0x0080
 #define RX3_ANARXACONTROL2_IMIN_DFESUM_ALIGN                       0
 #define RX3_ANARXACONTROL2_IMIN_DFESUM_BITS                        1
 #define RX3_ANARXACONTROL2_IMIN_DFESUM_SHIFT                       7
 
 /* Rx3 :: anaRxAControl2 :: imax_vga [06:06] */
 #define RX3_ANARXACONTROL2_IMAX_VGA_MASK                           0x0040
 #define RX3_ANARXACONTROL2_IMAX_VGA_ALIGN                          0
 #define RX3_ANARXACONTROL2_IMAX_VGA_BITS                           1
 #define RX3_ANARXACONTROL2_IMAX_VGA_SHIFT                          6
 
 /* Rx3 :: anaRxAControl2 :: imode_vga [05:05] */
 #define RX3_ANARXACONTROL2_IMODE_VGA_MASK                          0x0020
 #define RX3_ANARXACONTROL2_IMODE_VGA_ALIGN                         0
 #define RX3_ANARXACONTROL2_IMODE_VGA_BITS                          1
 #define RX3_ANARXACONTROL2_IMODE_VGA_SHIFT                         5
 
 /* Rx3 :: anaRxAControl2 :: imin_vga [04:04] */
 #define RX3_ANARXACONTROL2_IMIN_VGA_MASK                           0x0010
 #define RX3_ANARXACONTROL2_IMIN_VGA_ALIGN                          0
 #define RX3_ANARXACONTROL2_IMIN_VGA_BITS                           1
 #define RX3_ANARXACONTROL2_IMIN_VGA_SHIFT                          4
 
 /* Rx3 :: anaRxAControl2 :: imax_interp [03:03] */
 #define RX3_ANARXACONTROL2_IMAX_INTERP_MASK                        0x0008
 #define RX3_ANARXACONTROL2_IMAX_INTERP_ALIGN                       0
 #define RX3_ANARXACONTROL2_IMAX_INTERP_BITS                        1
 #define RX3_ANARXACONTROL2_IMAX_INTERP_SHIFT                       3
 
 /* Rx3 :: anaRxAControl2 :: imode_interp [02:02] */
 #define RX3_ANARXACONTROL2_IMODE_INTERP_MASK                       0x0004
 #define RX3_ANARXACONTROL2_IMODE_INTERP_ALIGN                      0
 #define RX3_ANARXACONTROL2_IMODE_INTERP_BITS                       1
 #define RX3_ANARXACONTROL2_IMODE_INTERP_SHIFT                      2
 
 /* Rx3 :: anaRxAControl2 :: imin_interp [01:01] */
 #define RX3_ANARXACONTROL2_IMIN_INTERP_MASK                        0x0002
 #define RX3_ANARXACONTROL2_IMIN_INTERP_ALIGN                       0
 #define RX3_ANARXACONTROL2_IMIN_INTERP_BITS                        1
 #define RX3_ANARXACONTROL2_IMIN_INTERP_SHIFT                       1
 
 /* Rx3 :: anaRxAControl2 :: imax_vcm [00:00] */
 #define RX3_ANARXACONTROL2_IMAX_VCM_MASK                           0x0001
 #define RX3_ANARXACONTROL2_IMAX_VCM_ALIGN                          0
 #define RX3_ANARXACONTROL2_IMAX_VCM_BITS                           1
 #define RX3_ANARXACONTROL2_IMAX_VCM_SHIFT                          0
 
 
 /****************************************************************************
  * Rx3 :: anaRxAControl3
  */
 /* Rx3 :: anaRxAControl3 :: en_clk16 [15:15] */
 #define RX3_ANARXACONTROL3_EN_CLK16_MASK                           0x8000
 #define RX3_ANARXACONTROL3_EN_CLK16_ALIGN                          0
 #define RX3_ANARXACONTROL3_EN_CLK16_BITS                           1
 #define RX3_ANARXACONTROL3_EN_CLK16_SHIFT                          15
 
 /* Rx3 :: anaRxAControl3 :: en_clk33 [14:14] */
 #define RX3_ANARXACONTROL3_EN_CLK33_MASK                           0x4000
 #define RX3_ANARXACONTROL3_EN_CLK33_ALIGN                          0
 #define RX3_ANARXACONTROL3_EN_CLK33_BITS                           1
 #define RX3_ANARXACONTROL3_EN_CLK33_SHIFT                          14
 
 /* Rx3 :: anaRxAControl3 :: en_vcctrl [13:13] */
 #define RX3_ANARXACONTROL3_EN_VCCTRL_MASK                          0x2000
 #define RX3_ANARXACONTROL3_EN_VCCTRL_ALIGN                         0
 #define RX3_ANARXACONTROL3_EN_VCCTRL_BITS                          1
 #define RX3_ANARXACONTROL3_EN_VCCTRL_SHIFT                         13
 
 /* Rx3 :: anaRxAControl3 :: sel_th4dfe1 [12:12] */
 #define RX3_ANARXACONTROL3_SEL_TH4DFE1_MASK                        0x1000
 #define RX3_ANARXACONTROL3_SEL_TH4DFE1_ALIGN                       0
 #define RX3_ANARXACONTROL3_SEL_TH4DFE1_BITS                        1
 #define RX3_ANARXACONTROL3_SEL_TH4DFE1_SHIFT                       12
 
 /* Rx3 :: anaRxAControl3 :: sel_th4dfe0 [11:11] */
 #define RX3_ANARXACONTROL3_SEL_TH4DFE0_MASK                        0x0800
 #define RX3_ANARXACONTROL3_SEL_TH4DFE0_ALIGN                       0
 #define RX3_ANARXACONTROL3_SEL_TH4DFE0_BITS                        1
 #define RX3_ANARXACONTROL3_SEL_TH4DFE0_SHIFT                       11
 
 /* Rx3 :: anaRxAControl3 :: selugbw1 [10:10] */
 #define RX3_ANARXACONTROL3_SELUGBW1_MASK                           0x0400
 #define RX3_ANARXACONTROL3_SELUGBW1_ALIGN                          0
 #define RX3_ANARXACONTROL3_SELUGBW1_BITS                           1
 #define RX3_ANARXACONTROL3_SELUGBW1_SHIFT                          10
 
 /* Rx3 :: anaRxAControl3 :: selugbw0 [09:09] */
 #define RX3_ANARXACONTROL3_SELUGBW0_MASK                           0x0200
 #define RX3_ANARXACONTROL3_SELUGBW0_ALIGN                          0
 #define RX3_ANARXACONTROL3_SELUGBW0_BITS                           1
 #define RX3_ANARXACONTROL3_SELUGBW0_SHIFT                          9
 
 /* Rx3 :: anaRxAControl3 :: imax_dfetap [08:08] */
 #define RX3_ANARXACONTROL3_IMAX_DFETAP_MASK                        0x0100
 #define RX3_ANARXACONTROL3_IMAX_DFETAP_ALIGN                       0
 #define RX3_ANARXACONTROL3_IMAX_DFETAP_BITS                        1
 #define RX3_ANARXACONTROL3_IMAX_DFETAP_SHIFT                       8
 
 /* Rx3 :: anaRxAControl3 :: imode_dfetap [07:07] */
 #define RX3_ANARXACONTROL3_IMODE_DFETAP_MASK                       0x0080
 #define RX3_ANARXACONTROL3_IMODE_DFETAP_ALIGN                      0
 #define RX3_ANARXACONTROL3_IMODE_DFETAP_BITS                       1
 #define RX3_ANARXACONTROL3_IMODE_DFETAP_SHIFT                      7
 
 /* Rx3 :: anaRxAControl3 :: imin_dfetap [06:06] */
 #define RX3_ANARXACONTROL3_IMIN_DFETAP_MASK                        0x0040
 #define RX3_ANARXACONTROL3_IMIN_DFETAP_ALIGN                       0
 #define RX3_ANARXACONTROL3_IMIN_DFETAP_BITS                        1
 #define RX3_ANARXACONTROL3_IMIN_DFETAP_SHIFT                       6
 
 /* Rx3 :: anaRxAControl3 :: imax_slcd2c [05:05] */
 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_MASK                        0x0020
 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_ALIGN                       0
 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_BITS                        1
 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_SHIFT                       5
 
 /* Rx3 :: anaRxAControl3 :: imode_slcd2c [04:04] */
 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_MASK                       0x0010
 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_ALIGN                      0
 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_BITS                       1
 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_SHIFT                      4
 
 /* Rx3 :: anaRxAControl3 :: imin_slcd2c [03:03] */
 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_MASK                        0x0008
 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_ALIGN                       0
 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_BITS                        1
 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_SHIFT                       3
 
 /* Rx3 :: anaRxAControl3 :: imax_dfevref [02:02] */
 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_MASK                       0x0004
 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_ALIGN                      0
 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_BITS                       1
 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_SHIFT                      2
 
 /* Rx3 :: anaRxAControl3 :: imode_dfevref [01:01] */
 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_MASK                      0x0002
 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_ALIGN                     0
 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_BITS                      1
 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_SHIFT                     1
 
 /* Rx3 :: anaRxAControl3 :: imin_dfevref [00:00] */
 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_MASK                       0x0001
 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_ALIGN                      0
 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_BITS                       1
 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_SHIFT                      0
 
 
 /****************************************************************************
  * Warpcore_USER_RxB
  */
 /****************************************************************************
  * RxB :: anaRxStatus
  */
 /* union - case sigdet_Status [15:00] */
 /* RxB :: anaRxStatus :: cx4_sigdet [15:15] */
 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK              0x8000
 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN             0
 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS              1
 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT             15
 
 /* RxB :: anaRxStatus :: reserved0 [14:13] */
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK               0x6000
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN              0
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS               2
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT              13
 
 /* RxB :: anaRxStatus :: rxSeqDone [12:12] */
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK               0x1000
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN              0
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS               1
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT              12
 
 /* RxB :: anaRxStatus :: rx_sigdet_ll [11:11] */
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK            0x0800
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN           0
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS            1
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT           11
 
 /* RxB :: anaRxStatus :: cs4_sigdet_ll [10:10] */
 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK           0x0400
 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN          0
 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS           1
 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT          10
 
 /* RxB :: anaRxStatus :: rx_reset [09:09] */
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK                0x0200
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN               0
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS                1
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT               9
 
 /* RxB :: anaRxStatus :: rx_pwrdn [08:08] */
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK                0x0100
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN               0
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS                1
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT               8
 
 /* RxB :: anaRxStatus :: reserved1 [07:00] */
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK               0x00ff
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN              0
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS               8
 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT              0
 
 
 /* union - case sync_Status [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:11] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK                 0xf800
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN                0
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS                 5
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT                11
 
 /* RxB :: anaRxStatus :: test_acq_en [10:10] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK               0x0400
 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN              0
 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS               1
 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT              10
 
 /* RxB :: anaRxStatus :: reserved1 [09:09] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK                 0x0200
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN                0
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS                 1
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT                9
 
 /* RxB :: anaRxStatus :: rxSeqStart [08:08] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK                0x0100
 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN               0
 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS                1
 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT               8
 
 /* RxB :: anaRxStatus :: mux_comadj_sync_status [07:07] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK    0x0080
 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN   0
 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS    1
 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT   7
 
 /* RxB :: anaRxStatus :: sync_status [06:06] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK               0x0040
 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN              0
 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS               1
 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT              6
 
 /* RxB :: anaRxStatus :: rx_sigdet [05:05] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK                 0x0020
 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN                0
 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS                 1
 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT                5
 
 /* RxB :: anaRxStatus :: reserved2 [04:03] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK                 0x0018
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN                0
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS                 2
 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT                3
 
 /* RxB :: anaRxStatus :: saturate_status [02:02] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK           0x0004
 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN          0
 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS           1
 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT          2
 
 /* RxB :: anaRxStatus :: cx4_sigdet [01:01] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK                0x0002
 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN               0
 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS                1
 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT               1
 
 /* RxB :: anaRxStatus :: rxSeqDone [00:00] */
 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK                 0x0001
 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN                0
 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS                 1
 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT                0
 
 
 /* union - case rxTestSel_0 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:10] */
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK                 0xfc00
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN                0
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS                 6
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT                10
 
 /* RxB :: anaRxStatus :: indck_mode_en [09:09] */
 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK             0x0200
 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN            0
 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS             1
 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT            9
 
 /* RxB :: anaRxStatus :: pci_mode_en [08:08] */
 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK               0x0100
 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN              0
 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS               1
 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT              8
 
 /* RxB :: anaRxStatus :: rx_polarity [07:07] */
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK               0x0080
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN              0
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS               1
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT              7
 
 /* RxB :: anaRxStatus :: rxpol_flip [06:06] */
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                0x0040
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN               0
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                1
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT               6
 
 /* RxB :: anaRxStatus :: comma_mask [05:05] */
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK                0x0020
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN               0
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS                1
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT               5
 
 /* RxB :: anaRxStatus :: link_en_r [04:04] */
 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK                 0x0010
 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                0
 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS                 1
 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                4
 
 /* RxB :: anaRxStatus :: comma_adj_en [03:03] */
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK              0x0008
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN             0
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS              1
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT             3
 
 /* RxB :: anaRxStatus :: comma_adj_en_ext [02:02] */
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK          0x0004
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN         0
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS          1
 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT         2
 
 /* RxB :: anaRxStatus :: reserved1 [01:00] */
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK                 0x0003
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN                0
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS                 2
 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT                0
 
 
 /* union - case rxTestSel_1 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:05] */
 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK                 0xffe0
 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN                0
 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS                 11
 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT                5
 
 /* RxB :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK             0x0010
 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN            0
 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS             1
 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT            4
 
 /* RxB :: anaRxStatus :: freq_sel_PC [03:03] */
 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK               0x0008
 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN              0
 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS               1
 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT              3
 
 /* RxB :: anaRxStatus :: freq_sel_SM [02:02] */
 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK               0x0004
 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN              0
 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS               1
 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT              2
 
 /* RxB :: anaRxStatus :: integ_mode_SM [01:00] */
 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK             0x0003
 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN            0
 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS             2
 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT            0
 
 
 /* union - case scale_Status [15:00] */
 /* RxB :: anaRxStatus :: prop_scale [15:12] */
 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK               0xf000
 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN              0
 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS               4
 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT              12
 
 /* RxB :: anaRxStatus :: integ_scale [11:08] */
 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK              0x0f00
 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN             0
 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS              4
 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT             8
 
 /* RxB :: anaRxStatus :: prop_scale_acq [07:04] */
 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK           0x00f0
 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN          0
 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS           4
 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT          4
 
 /* RxB :: anaRxStatus :: integ_scale_acq [03:00] */
 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK          0x000f
 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN         0
 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS          4
 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT         0
 
 
 /* union - case adc_CdrStatus1 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:07] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK              0xff80
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS              9
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT             7
 
 /* RxB :: anaRxStatus :: rxMuxCkSel [06:06] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK             0x0040
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS             1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT            6
 
 /* RxB :: anaRxStatus :: glpbk_combo [05:05] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK            0x0020
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN           0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS            1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT           5
 
 /* RxB :: anaRxStatus :: clockSwitchSel [04:04] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK         0x0010
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN        0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS         1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT        4
 
 /* RxB :: anaRxStatus :: rxck_tst [03:03] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK               0x0008
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN              0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS               1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT              3
 
 /* RxB :: anaRxStatus :: rxck_i [02:02] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK                 0x0004
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS                 1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                2
 
 /* RxB :: anaRxStatus :: refclk [01:01] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK                 0x0002
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS                 1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                1
 
 /* RxB :: anaRxStatus :: pll_bypass [00:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK             0x0001
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS             1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT            0
 
 
 /* union - case adc_CdrStatus2 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:06] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK              0xffc0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS              10
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT             6
 
 /* RxB :: anaRxStatus :: rxMuxCkSel [05:05] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK             0x0020
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS             1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT            5
 
 /* RxB :: anaRxStatus :: rxSeqStart [04:04] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK             0x0010
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS             1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT            4
 
 /* RxB :: anaRxStatus :: reserved1 [03:01] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK              0x000e
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS              3
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT             1
 
 /* RxB :: anaRxStatus :: rxSeqDone [00:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK              0x0001
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS              1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT             0
 
 
 /* union - case adc_CdrStatus3 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:04] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK              0xfff0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS              12
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT             4
 
 /* RxB :: anaRxStatus :: rxSeqStart [03:03] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK             0x0008
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS             1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT            3
 
 /* RxB :: anaRxStatus :: reserved1 [02:01] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK              0x0006
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS              2
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT             1
 
 /* RxB :: anaRxStatus :: allow_increment_PC [00:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK     0x0001
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN    0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS     1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT    0
 
 
 /* union - case adc_CdrStatus4 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:08] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK              0xff00
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS              8
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT             8
 
 /* RxB :: anaRxStatus :: rx_pwrdn [07:07] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK               0x0080
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN              0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS               1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT              7
 
 /* RxB :: anaRxStatus :: freq_sel [06:06] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK               0x0040
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN              0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS               1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT              6
 
 /* RxB :: anaRxStatus :: pll_lock_rstb [05:05] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK          0x0020
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN         0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS          1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT         5
 
 /* RxB :: anaRxStatus :: pwrdn [04:04] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK                  0x0010
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                 0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS                  1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                 4
 
 /* RxB :: anaRxStatus :: reserved1 [03:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK              0x000f
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS              4
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT             0
 
 
 /* union - case adc_CdrStatus5 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK              0xffff
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS              16
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT             0
 
 
 /* union - case adc_CdrStatus6 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:05] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK              0xffe0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS              11
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT             5
 
 /* RxB :: anaRxStatus :: rx_reset [04:04] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK               0x0010
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN              0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS               1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT              4
 
 /* RxB :: anaRxStatus :: rx_pwrdn [03:03] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK               0x0008
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN              0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS               1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT              3
 
 /* RxB :: anaRxStatus :: reset_anlg [02:02] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK             0x0004
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS             1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT            2
 
 /* RxB :: anaRxStatus :: pwrdn_rx [01:01] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK               0x0002
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN              0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS               1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT              1
 
 /* RxB :: anaRxStatus :: pwrdn_pll [00:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK              0x0001
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS              1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT             0
 
 
 /* union - case adc_CdrStatus7e [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:05] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK             0xffe0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS             11
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT            5
 
 /* RxB :: anaRxStatus :: rxck0_even [04:04] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK            0x0010
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN           0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS            1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT           4
 
 /* RxB :: anaRxStatus :: rxck1_even [03:03] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK            0x0008
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN           0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS            1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT           3
 
 /* RxB :: anaRxStatus :: comdet_even [02:02] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK           0x0004
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN          0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS           1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT          2
 
 /* RxB :: anaRxStatus :: en_cdet_even [01:01] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK          0x0002
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN         0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS          1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT         1
 
 /* RxB :: anaRxStatus :: comma_adj_en_even [00:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK     0x0001
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN    0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS     1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT    0
 
 
 /* union - case adc_CdrStatus7o [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:05] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK             0xffe0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS             11
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT            5
 
 /* RxB :: anaRxStatus :: rxck0_odd [04:04] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK             0x0010
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS             1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT            4
 
 /* RxB :: anaRxStatus :: rxck1_odd [03:03] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK             0x0008
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS             1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT            3
 
 /* RxB :: anaRxStatus :: comdet_odd [02:02] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK            0x0004
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN           0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS            1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT           2
 
 /* RxB :: anaRxStatus :: en_cdet_odd [01:01] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK           0x0002
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN          0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS           1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT          1
 
 /* RxB :: anaRxStatus :: comma_adj_en_odd [00:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK      0x0001
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN     0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS      1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT     0
 
 
 /* union - case adc_CdrStatus8 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:01] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK              0xfffe
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS              15
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT             1
 
 /* RxB :: anaRxStatus :: sigdet [00:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK                 0x0001
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS                 1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                0
 
 
 /* union - case adc_CdrStatus9 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK              0xffff
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS              16
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT             0
 
 
 /* union - case adc_CdrStatus10 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:07] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK             0xff80
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS             9
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT            7
 
 /* RxB :: anaRxStatus :: prbs_en [06:06] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK               0x0040
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN              0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS               1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT              6
 
 /* RxB :: anaRxStatus :: rstb_tst [05:05] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK              0x0020
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN             0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS              1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT             5
 
 /* RxB :: anaRxStatus :: reserved1 [04:04] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK             0x0010
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS             1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT            4
 
 /* RxB :: anaRxStatus :: prbs_state [03:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK            0x000f
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN           0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS            4
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT           0
 
 
 /* union - case adc_CdrStatus11 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK             0xffff
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS             16
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT            0
 
 
 /* union - case adc_CdrStatus12_1 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:06] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK           0xffc0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN          0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS           10
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT          6
 
 /* RxB :: anaRxStatus :: enable4 [05:05] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK             0x0020
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN            0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS             1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT            5
 
 /* RxB :: anaRxStatus :: radr_test [04:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK           0x001f
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN          0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS           5
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT          0
 
 
 /* union - case adc_CdrStatus12_2 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:05] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK           0xffe0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN          0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS           11
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT          5
 
 /* RxB :: anaRxStatus :: wadr_test [04:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK           0x001f
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN          0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS           5
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT          0
 
 
 /* union - case adc_CdrStatus12_3 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:06] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK           0xffc0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN          0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS           10
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT          6
 
 /* RxB :: anaRxStatus :: rxck_66B_tmux [05:05] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK       0x0020
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN      0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS       1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT      5
 
 /* RxB :: anaRxStatus :: rstb_66B [04:04] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK            0x0010
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN           0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS            1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT           4
 
 /* RxB :: anaRxStatus :: prstb_66B_mux [03:03] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK       0x0008
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN      0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS       1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT      3
 
 /* RxB :: anaRxStatus :: rxck_i66_tmux [02:02] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK       0x0004
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN      0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS       1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT      2
 
 /* RxB :: anaRxStatus :: rstb_i66 [01:01] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK            0x0002
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN           0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS            1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT           1
 
 /* RxB :: anaRxStatus :: prstb_i66_mux [00:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK       0x0001
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN      0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS       1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT      0
 
 
 /* union - case adc_CdrStatus12_4 [15:00] */
 /* RxB :: anaRxStatus :: reserved0 [15:04] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK           0xfff0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN          0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS           12
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT          4
 
 /* RxB :: anaRxStatus :: rfifo_error_r [03:02] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK       0x000c
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN      0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS       2
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT      2
 
 /* RxB :: anaRxStatus :: rfifo_unflow [01:01] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK        0x0002
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN       0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS        1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT       1
 
 /* RxB :: anaRxStatus :: rfifo_ovflow [00:00] */
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK        0x0001
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN       0
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS        1
 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT       0
 
 
 /* union - case integ_Status [15:00] */
 /* RxB :: anaRxStatus :: integ_status [15:00] */
 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK             0xffff
 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN            0
 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS             16
 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT            0
 
 
 /* union - case vco_Status [15:00] */
 /* RxB :: anaRxStatus :: vco_status [15:00] */
 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK                 0xffff
 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN                0
 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS                 16
 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT                0
 
 
 /* union - case prbs_Status [15:00] */
 /* RxB :: anaRxStatus :: prbs_lock [15:15] */
 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK                 0x8000
 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                0
 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS                 1
 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                15
 
 /* RxB :: anaRxStatus :: prbs_stky [14:14] */
 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK                 0x4000
 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN                0
 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS                 1
 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT                14
 
 /* RxB :: anaRxStatus :: ptbs_errors [13:00] */
 #define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK               0x3fff
 #define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN              0
 #define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS               14
 #define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT              0
 
 
 
 /****************************************************************************
  * RxB :: anaRxControl
  */
 /* RxB :: anaRxControl :: reserved0 [15:10] */
 #define RXB_ANARXCONTROL_RESERVED0_MASK                            0xfc00
 #define RXB_ANARXCONTROL_RESERVED0_ALIGN                           0
 #define RXB_ANARXCONTROL_RESERVED0_BITS                            6
 #define RXB_ANARXCONTROL_RESERVED0_SHIFT                           10
 
 /* RxB :: anaRxControl :: override_sigdet_en [09:09] */
 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK                   0x0200
 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN                  0
 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS                   1
 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT                  9
 
 /* RxB :: anaRxControl :: override_sigdet_val [08:08] */
 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK                  0x0100
 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN                 0
 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS                  1
 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT                 8
 
 /* RxB :: anaRxControl :: reserved1 [07:03] */
 #define RXB_ANARXCONTROL_RESERVED1_MASK                            0x00f8
 #define RXB_ANARXCONTROL_RESERVED1_ALIGN                           0
 #define RXB_ANARXCONTROL_RESERVED1_BITS                            5
 #define RXB_ANARXCONTROL_RESERVED1_SHIFT                           3
 
 /* RxB :: anaRxControl :: status_sel [02:00] */
 #define RXB_ANARXCONTROL_STATUS_SEL_MASK                           0x0007
 #define RXB_ANARXCONTROL_STATUS_SEL_ALIGN                          0
 #define RXB_ANARXCONTROL_STATUS_SEL_BITS                           3
 #define RXB_ANARXCONTROL_STATUS_SEL_SHIFT                          0
 #define RXB_ANARXCONTROL_STATUS_SEL_sigdetStatus                   0
 #define RXB_ANARXCONTROL_STATUS_SEL_syncStatus                     1
 #define RXB_ANARXCONTROL_STATUS_SEL_rxTestSel                      2
 #define RXB_ANARXCONTROL_STATUS_SEL_scaleStatus                    3
 #define RXB_ANARXCONTROL_STATUS_SEL_adcCdrStatus                   4
 #define RXB_ANARXCONTROL_STATUS_SEL_integStatus                    5
 #define RXB_ANARXCONTROL_STATUS_SEL_vcoStatus                      6
 #define RXB_ANARXCONTROL_STATUS_SEL_prbsStatus                     7
 
 
 /****************************************************************************
  * RxB :: anaRxTest
  */
 /* RxB :: anaRxTest :: sigdet_mux_SM [15:12] */
 #define RXB_ANARXTEST_SIGDET_MUX_SM_MASK                           0xf000
 #define RXB_ANARXTEST_SIGDET_MUX_SM_ALIGN                          0
 #define RXB_ANARXTEST_SIGDET_MUX_SM_BITS                           4
 #define RXB_ANARXTEST_SIGDET_MUX_SM_SHIFT                          12
 
 /* RxB :: anaRxTest :: reserved0 [11:09] */
 #define RXB_ANARXTEST_RESERVED0_MASK                               0x0e00
 #define RXB_ANARXTEST_RESERVED0_ALIGN                              0
 #define RXB_ANARXTEST_RESERVED0_BITS                               3
 #define RXB_ANARXTEST_RESERVED0_SHIFT                              9
 
 /* RxB :: anaRxTest :: tpctrl_SM [08:04] */
 #define RXB_ANARXTEST_TPCTRL_SM_MASK                               0x01f0
 #define RXB_ANARXTEST_TPCTRL_SM_ALIGN                              0
 #define RXB_ANARXTEST_TPCTRL_SM_BITS                               5
 #define RXB_ANARXTEST_TPCTRL_SM_SHIFT                              4
 
 /* RxB :: anaRxTest :: testMuxSelect_SM [03:00] */
 #define RXB_ANARXTEST_TESTMUXSELECT_SM_MASK                        0x000f
 #define RXB_ANARXTEST_TESTMUXSELECT_SM_ALIGN                       0
 #define RXB_ANARXTEST_TESTMUXSELECT_SM_BITS                        4
 #define RXB_ANARXTEST_TESTMUXSELECT_SM_SHIFT                       0
 
 
 /****************************************************************************
  * RxB :: anaRxControl1G
  */
 /* RxB :: anaRxControl1G :: fpat_md [15:15] */
 #define RXB_ANARXCONTROL1G_FPAT_MD_MASK                            0x8000
 #define RXB_ANARXCONTROL1G_FPAT_MD_ALIGN                           0
 #define RXB_ANARXCONTROL1G_FPAT_MD_BITS                            1
 #define RXB_ANARXCONTROL1G_FPAT_MD_SHIFT                           15
 
 /* RxB :: anaRxControl1G :: pkt_count_en [14:14] */
 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_MASK                       0x4000
 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN                      0
 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_BITS                       1
 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT                      14
 
 /* RxB :: anaRxControl1G :: staMuxRegDis [13:13] */
 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_MASK                       0x2000
 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_ALIGN                      0
 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_BITS                       1
 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_SHIFT                      13
 
 /* RxB :: anaRxControl1G :: prbs_clr_dis [12:12] */
 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_MASK                       0x1000
 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN                      0
 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_BITS                       1
 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT                      12
 
 /* RxB :: anaRxControl1G :: rxd_dec_sel [11:11] */
 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_MASK                        0x0800
 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN                       0
 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_BITS                        1
 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT                       11
 
 /* RxB :: anaRxControl1G :: cgbad_tst [10:10] */
 #define RXB_ANARXCONTROL1G_CGBAD_TST_MASK                          0x0400
 #define RXB_ANARXCONTROL1G_CGBAD_TST_ALIGN                         0
 #define RXB_ANARXCONTROL1G_CGBAD_TST_BITS                          1
 #define RXB_ANARXCONTROL1G_CGBAD_TST_SHIFT                         10
 
 /* RxB :: anaRxControl1G :: Emon_en [09:09] */
 #define RXB_ANARXCONTROL1G_EMON_EN_MASK                            0x0200
 #define RXB_ANARXCONTROL1G_EMON_EN_ALIGN                           0
 #define RXB_ANARXCONTROL1G_EMON_EN_BITS                            1
 #define RXB_ANARXCONTROL1G_EMON_EN_SHIFT                           9
 
 /* RxB :: anaRxControl1G :: prbs_en [08:08] */
 #define RXB_ANARXCONTROL1G_PRBS_EN_MASK                            0x0100
 #define RXB_ANARXCONTROL1G_PRBS_EN_ALIGN                           0
 #define RXB_ANARXCONTROL1G_PRBS_EN_BITS                            1
 #define RXB_ANARXCONTROL1G_PRBS_EN_SHIFT                           8
 
 /* RxB :: anaRxControl1G :: cgbad_en [07:07] */
 #define RXB_ANARXCONTROL1G_CGBAD_EN_MASK                           0x0080
 #define RXB_ANARXCONTROL1G_CGBAD_EN_ALIGN                          0
 #define RXB_ANARXCONTROL1G_CGBAD_EN_BITS                           1
 #define RXB_ANARXCONTROL1G_CGBAD_EN_SHIFT                          7
 
 /* RxB :: anaRxControl1G :: cstretch [06:06] */
 #define RXB_ANARXCONTROL1G_CSTRETCH_MASK                           0x0040
 #define RXB_ANARXCONTROL1G_CSTRETCH_ALIGN                          0
 #define RXB_ANARXCONTROL1G_CSTRETCH_BITS                           1
 #define RXB_ANARXCONTROL1G_CSTRETCH_SHIFT                          6
 
 /* RxB :: anaRxControl1G :: comma_low_byte_SM [05:05] */
 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK                  0x0020
 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN                 0
 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS                  1
 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT                 5
 
 /* RxB :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */
 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK               0x0010
 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN              0
 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS               1
 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT              4
 
 /* RxB :: anaRxControl1G :: reserved0 [03:02] */
 #define RXB_ANARXCONTROL1G_RESERVED0_MASK                          0x000c
 #define RXB_ANARXCONTROL1G_RESERVED0_ALIGN                         0
 #define RXB_ANARXCONTROL1G_RESERVED0_BITS                          2
 #define RXB_ANARXCONTROL1G_RESERVED0_SHIFT                         2
 
 /* RxB :: anaRxControl1G :: freq_sel_force [01:01] */
 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK                     0x0002
 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN                    0
 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS                     1
 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT                    1
 
 /* RxB :: anaRxControl1G :: freq_sel [00:00] */
 #define RXB_ANARXCONTROL1G_FREQ_SEL_MASK                           0x0001
 #define RXB_ANARXCONTROL1G_FREQ_SEL_ALIGN                          0
 #define RXB_ANARXCONTROL1G_FREQ_SEL_BITS                           1
 #define RXB_ANARXCONTROL1G_FREQ_SEL_SHIFT                          0
 
 
 /****************************************************************************
  * RxB :: anaRxControlPci
  */
 /* RxB :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK                0x8000
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN               0
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS                1
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT               15
 
 /* RxB :: anaRxControlPci :: comma_mask_force_r [14:14] */
 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK                0x4000
 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN               0
 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS                1
 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT               14
 
 /* RxB :: anaRxControlPci :: comma_mask_r [13:13] */
 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_MASK                      0x2000
 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN                     0
 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_BITS                      1
 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT                     13
 
 /* RxB :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK         0x1000
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN        0
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS         1
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT        12
 
 /* RxB :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK            0x0800
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN           0
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS            1
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT           11
 
 /* RxB :: anaRxControlPci :: sync_status_force_r [10:10] */
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK               0x0400
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN              0
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS               1
 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT              10
 
 /* RxB :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK         0x0200
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN        0
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS         1
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT        9
 
 /* RxB :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK        0x0100
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN       0
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS        1
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT       8
 
 /* RxB :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK           0x0080
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN          0
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS           1
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT          7
 
 /* RxB :: anaRxControlPci :: comma_adj_en_r [06:06] */
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK                    0x0040
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN                   0
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS                    1
 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT                   6
 
 /* RxB :: anaRxControlPci :: link_en_force_SM [05:05] */
 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK                  0x0020
 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN                 0
 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS                  1
 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT                 5
 
 /* RxB :: anaRxControlPci :: link_en_r [04:04] */
 #define RXB_ANARXCONTROLPCI_LINK_EN_R_MASK                         0x0010
 #define RXB_ANARXCONTROLPCI_LINK_EN_R_ALIGN                        0
 #define RXB_ANARXCONTROLPCI_LINK_EN_R_BITS                         1
 #define RXB_ANARXCONTROLPCI_LINK_EN_R_SHIFT                        4
 
 /* RxB :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK              0x0008
 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN             0
 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS              1
 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT             3
 
 /* RxB :: anaRxControlPci :: rx_polarity_r [02:02] */
 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_MASK                     0x0004
 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN                    0
 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_BITS                     1
 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT                    2
 
 /* RxB :: anaRxControlPci :: integ_mode_SM [01:00] */
 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_MASK                     0x0003
 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN                    0
 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_BITS                     2
 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT                    0
 
 
 /****************************************************************************
  * RxB :: anaRxAstatus
  */
 /* RxB :: anaRxAstatus :: sigdet [15:15] */
 #define RXB_ANARXASTATUS_SIGDET_MASK                               0x8000
 #define RXB_ANARXASTATUS_SIGDET_ALIGN                              0
 #define RXB_ANARXASTATUS_SIGDET_BITS                               1
 #define RXB_ANARXASTATUS_SIGDET_SHIFT                              15
 
 /* RxB :: anaRxAstatus :: rx_pf [14:11] */
 #define RXB_ANARXASTATUS_RX_PF_MASK                                0x7800
 #define RXB_ANARXASTATUS_RX_PF_ALIGN                               0
 #define RXB_ANARXASTATUS_RX_PF_BITS                                4
 #define RXB_ANARXASTATUS_RX_PF_SHIFT                               11
 
 /* RxB :: anaRxAstatus :: tap1_dfe_gray [10:05] */
 #define RXB_ANARXASTATUS_TAP1_DFE_GRAY_MASK                        0x07e0
 #define RXB_ANARXASTATUS_TAP1_DFE_GRAY_ALIGN                       0
 #define RXB_ANARXASTATUS_TAP1_DFE_GRAY_BITS                        6
 #define RXB_ANARXASTATUS_TAP1_DFE_GRAY_SHIFT                       5
 
 /* RxB :: anaRxAstatus :: vga [04:00] */
 #define RXB_ANARXASTATUS_VGA_MASK                                  0x001f
 #define RXB_ANARXASTATUS_VGA_ALIGN                                 0
 #define RXB_ANARXASTATUS_VGA_BITS                                  5
 #define RXB_ANARXASTATUS_VGA_SHIFT                                 0
 
 
 /****************************************************************************
  * RxB :: anaRxAControl1
  */
 /* RxB :: anaRxAControl1 :: imode_vcm [15:15] */
 #define RXB_ANARXACONTROL1_IMODE_VCM_MASK                          0x8000
 #define RXB_ANARXACONTROL1_IMODE_VCM_ALIGN                         0
 #define RXB_ANARXACONTROL1_IMODE_VCM_BITS                          1
 #define RXB_ANARXACONTROL1_IMODE_VCM_SHIFT                         15
 
 /* RxB :: anaRxAControl1 :: imin_vcm [14:14] */
 #define RXB_ANARXACONTROL1_IMIN_VCM_MASK                           0x4000
 #define RXB_ANARXACONTROL1_IMIN_VCM_ALIGN                          0
 #define RXB_ANARXACONTROL1_IMIN_VCM_BITS                           1
 #define RXB_ANARXACONTROL1_IMIN_VCM_SHIFT                          14
 
 /* RxB :: anaRxAControl1 :: imax_sigdet [13:13] */
 #define RXB_ANARXACONTROL1_IMAX_SIGDET_MASK                        0x2000
 #define RXB_ANARXACONTROL1_IMAX_SIGDET_ALIGN                       0
 #define RXB_ANARXACONTROL1_IMAX_SIGDET_BITS                        1
 #define RXB_ANARXACONTROL1_IMAX_SIGDET_SHIFT                       13
 
 /* RxB :: anaRxAControl1 :: imode_sigdet [12:12] */
 #define RXB_ANARXACONTROL1_IMODE_SIGDET_MASK                       0x1000
 #define RXB_ANARXACONTROL1_IMODE_SIGDET_ALIGN                      0
 #define RXB_ANARXACONTROL1_IMODE_SIGDET_BITS                       1
 #define RXB_ANARXACONTROL1_IMODE_SIGDET_SHIFT                      12
 
 /* RxB :: anaRxAControl1 :: imin_sigdet [11:11] */
 #define RXB_ANARXACONTROL1_IMIN_SIGDET_MASK                        0x0800
 #define RXB_ANARXACONTROL1_IMIN_SIGDET_ALIGN                       0
 #define RXB_ANARXACONTROL1_IMIN_SIGDET_BITS                        1
 #define RXB_ANARXACONTROL1_IMIN_SIGDET_SHIFT                       11
 
 /* RxB :: anaRxAControl1 :: refh_rx [10:10] */
 #define RXB_ANARXACONTROL1_REFH_RX_MASK                            0x0400
 #define RXB_ANARXACONTROL1_REFH_RX_ALIGN                           0
 #define RXB_ANARXACONTROL1_REFH_RX_BITS                            1
 #define RXB_ANARXACONTROL1_REFH_RX_SHIFT                           10
 
 /* RxB :: anaRxAControl1 :: refl_rx [09:09] */
 #define RXB_ANARXACONTROL1_REFL_RX_MASK                            0x0200
 #define RXB_ANARXACONTROL1_REFL_RX_ALIGN                           0
 #define RXB_ANARXACONTROL1_REFL_RX_BITS                            1
 #define RXB_ANARXACONTROL1_REFL_RX_SHIFT                           9
 
 /* RxB :: anaRxAControl1 :: tport_en [08:08] */
 #define RXB_ANARXACONTROL1_TPORT_EN_MASK                           0x0100
 #define RXB_ANARXACONTROL1_TPORT_EN_ALIGN                          0
 #define RXB_ANARXACONTROL1_TPORT_EN_BITS                           1
 #define RXB_ANARXACONTROL1_TPORT_EN_SHIFT                          8
 
 /* RxB :: anaRxAControl1 :: vddrb_bgb [07:07] */
 #define RXB_ANARXACONTROL1_VDDRB_BGB_MASK                          0x0080
 #define RXB_ANARXACONTROL1_VDDRB_BGB_ALIGN                         0
 #define RXB_ANARXACONTROL1_VDDRB_BGB_BITS                          1
 #define RXB_ANARXACONTROL1_VDDRB_BGB_SHIFT                         7
 
 /* RxB :: anaRxAControl1 :: sig_pwrdn [06:06] */
 #define RXB_ANARXACONTROL1_SIG_PWRDN_MASK                          0x0040
 #define RXB_ANARXACONTROL1_SIG_PWRDN_ALIGN                         0
 #define RXB_ANARXACONTROL1_SIG_PWRDN_BITS                          1
 #define RXB_ANARXACONTROL1_SIG_PWRDN_SHIFT                         6
 
 /* RxB :: anaRxAControl1 :: offset_ctrl [05:03] */
 #define RXB_ANARXACONTROL1_OFFSET_CTRL_MASK                        0x0038
 #define RXB_ANARXACONTROL1_OFFSET_CTRL_ALIGN                       0
 #define RXB_ANARXACONTROL1_OFFSET_CTRL_BITS                        3
 #define RXB_ANARXACONTROL1_OFFSET_CTRL_SHIFT                       3
 
 /* RxB :: anaRxAControl1 :: offset_sel [02:02] */
 #define RXB_ANARXACONTROL1_OFFSET_SEL_MASK                         0x0004
 #define RXB_ANARXACONTROL1_OFFSET_SEL_ALIGN                        0
 #define RXB_ANARXACONTROL1_OFFSET_SEL_BITS                         1
 #define RXB_ANARXACONTROL1_OFFSET_SEL_SHIFT                        2
 
 /* RxB :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */
 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY1_MASK                    0x0002
 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN                   0
 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY1_BITS                    1
 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT                   1
 
 /* RxB :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */
 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY0_MASK                    0x0001
 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN                   0
 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY0_BITS                    1
 #define RXB_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT                   0
 
 
 /****************************************************************************
  * RxB :: anaRxAControl2
  */
 /* RxB :: anaRxAControl2 :: imax_ctat [15:15] */
 #define RXB_ANARXACONTROL2_IMAX_CTAT_MASK                          0x8000
 #define RXB_ANARXACONTROL2_IMAX_CTAT_ALIGN                         0
 #define RXB_ANARXACONTROL2_IMAX_CTAT_BITS                          1
 #define RXB_ANARXACONTROL2_IMAX_CTAT_SHIFT                         15
 
 /* RxB :: anaRxAControl2 :: imode_ctat [14:14] */
 #define RXB_ANARXACONTROL2_IMODE_CTAT_MASK                         0x4000
 #define RXB_ANARXACONTROL2_IMODE_CTAT_ALIGN                        0
 #define RXB_ANARXACONTROL2_IMODE_CTAT_BITS                         1
 #define RXB_ANARXACONTROL2_IMODE_CTAT_SHIFT                        14
 
 /* RxB :: anaRxAControl2 :: imin_ctat [13:13] */
 #define RXB_ANARXACONTROL2_IMIN_CTAT_MASK                          0x2000
 #define RXB_ANARXACONTROL2_IMIN_CTAT_ALIGN                         0
 #define RXB_ANARXACONTROL2_IMIN_CTAT_BITS                          1
 #define RXB_ANARXACONTROL2_IMIN_CTAT_SHIFT                         13
 
 /* RxB :: anaRxAControl2 :: imax_eqfl [12:12] */
 #define RXB_ANARXACONTROL2_IMAX_EQFL_MASK                          0x1000
 #define RXB_ANARXACONTROL2_IMAX_EQFL_ALIGN                         0
 #define RXB_ANARXACONTROL2_IMAX_EQFL_BITS                          1
 #define RXB_ANARXACONTROL2_IMAX_EQFL_SHIFT                         12
 
 /* RxB :: anaRxAControl2 :: imode_eqfl [11:11] */
 #define RXB_ANARXACONTROL2_IMODE_EQFL_MASK                         0x0800
 #define RXB_ANARXACONTROL2_IMODE_EQFL_ALIGN                        0
 #define RXB_ANARXACONTROL2_IMODE_EQFL_BITS                         1
 #define RXB_ANARXACONTROL2_IMODE_EQFL_SHIFT                        11
 
 /* RxB :: anaRxAControl2 :: imin_eqfl [10:10] */
 #define RXB_ANARXACONTROL2_IMIN_EQFL_MASK                          0x0400
 #define RXB_ANARXACONTROL2_IMIN_EQFL_ALIGN                         0
 #define RXB_ANARXACONTROL2_IMIN_EQFL_BITS                          1
 #define RXB_ANARXACONTROL2_IMIN_EQFL_SHIFT                         10
 
 /* RxB :: anaRxAControl2 :: imax_dfesum [09:09] */
 #define RXB_ANARXACONTROL2_IMAX_DFESUM_MASK                        0x0200
 #define RXB_ANARXACONTROL2_IMAX_DFESUM_ALIGN                       0
 #define RXB_ANARXACONTROL2_IMAX_DFESUM_BITS                        1
 #define RXB_ANARXACONTROL2_IMAX_DFESUM_SHIFT                       9
 
 /* RxB :: anaRxAControl2 :: imode_dfesum [08:08] */
 #define RXB_ANARXACONTROL2_IMODE_DFESUM_MASK                       0x0100
 #define RXB_ANARXACONTROL2_IMODE_DFESUM_ALIGN                      0
 #define RXB_ANARXACONTROL2_IMODE_DFESUM_BITS                       1
 #define RXB_ANARXACONTROL2_IMODE_DFESUM_SHIFT                      8
 
 /* RxB :: anaRxAControl2 :: imin_dfesum [07:07] */
 #define RXB_ANARXACONTROL2_IMIN_DFESUM_MASK                        0x0080
 #define RXB_ANARXACONTROL2_IMIN_DFESUM_ALIGN                       0
 #define RXB_ANARXACONTROL2_IMIN_DFESUM_BITS                        1
 #define RXB_ANARXACONTROL2_IMIN_DFESUM_SHIFT                       7
 
 /* RxB :: anaRxAControl2 :: imax_vga [06:06] */
 #define RXB_ANARXACONTROL2_IMAX_VGA_MASK                           0x0040
 #define RXB_ANARXACONTROL2_IMAX_VGA_ALIGN                          0
 #define RXB_ANARXACONTROL2_IMAX_VGA_BITS                           1
 #define RXB_ANARXACONTROL2_IMAX_VGA_SHIFT                          6
 
 /* RxB :: anaRxAControl2 :: imode_vga [05:05] */
 #define RXB_ANARXACONTROL2_IMODE_VGA_MASK                          0x0020
 #define RXB_ANARXACONTROL2_IMODE_VGA_ALIGN                         0
 #define RXB_ANARXACONTROL2_IMODE_VGA_BITS                          1
 #define RXB_ANARXACONTROL2_IMODE_VGA_SHIFT                         5
 
 /* RxB :: anaRxAControl2 :: imin_vga [04:04] */
 #define RXB_ANARXACONTROL2_IMIN_VGA_MASK                           0x0010
 #define RXB_ANARXACONTROL2_IMIN_VGA_ALIGN                          0
 #define RXB_ANARXACONTROL2_IMIN_VGA_BITS                           1
 #define RXB_ANARXACONTROL2_IMIN_VGA_SHIFT                          4
 
 /* RxB :: anaRxAControl2 :: imax_interp [03:03] */
 #define RXB_ANARXACONTROL2_IMAX_INTERP_MASK                        0x0008
 #define RXB_ANARXACONTROL2_IMAX_INTERP_ALIGN                       0
 #define RXB_ANARXACONTROL2_IMAX_INTERP_BITS                        1
 #define RXB_ANARXACONTROL2_IMAX_INTERP_SHIFT                       3
 
 /* RxB :: anaRxAControl2 :: imode_interp [02:02] */
 #define RXB_ANARXACONTROL2_IMODE_INTERP_MASK                       0x0004
 #define RXB_ANARXACONTROL2_IMODE_INTERP_ALIGN                      0
 #define RXB_ANARXACONTROL2_IMODE_INTERP_BITS                       1
 #define RXB_ANARXACONTROL2_IMODE_INTERP_SHIFT                      2
 
 /* RxB :: anaRxAControl2 :: imin_interp [01:01] */
 #define RXB_ANARXACONTROL2_IMIN_INTERP_MASK                        0x0002
 #define RXB_ANARXACONTROL2_IMIN_INTERP_ALIGN                       0
 #define RXB_ANARXACONTROL2_IMIN_INTERP_BITS                        1
 #define RXB_ANARXACONTROL2_IMIN_INTERP_SHIFT                       1
 
 /* RxB :: anaRxAControl2 :: imax_vcm [00:00] */
 #define RXB_ANARXACONTROL2_IMAX_VCM_MASK                           0x0001
 #define RXB_ANARXACONTROL2_IMAX_VCM_ALIGN                          0
 #define RXB_ANARXACONTROL2_IMAX_VCM_BITS                           1
 #define RXB_ANARXACONTROL2_IMAX_VCM_SHIFT                          0
 
 
 /****************************************************************************
  * RxB :: anaRxAControl3
  */
 /* RxB :: anaRxAControl3 :: en_clk16 [15:15] */
 #define RXB_ANARXACONTROL3_EN_CLK16_MASK                           0x8000
 #define RXB_ANARXACONTROL3_EN_CLK16_ALIGN                          0
 #define RXB_ANARXACONTROL3_EN_CLK16_BITS                           1
 #define RXB_ANARXACONTROL3_EN_CLK16_SHIFT                          15
 
 /* RxB :: anaRxAControl3 :: en_clk33 [14:14] */
 #define RXB_ANARXACONTROL3_EN_CLK33_MASK                           0x4000
 #define RXB_ANARXACONTROL3_EN_CLK33_ALIGN                          0
 #define RXB_ANARXACONTROL3_EN_CLK33_BITS                           1
 #define RXB_ANARXACONTROL3_EN_CLK33_SHIFT                          14
 
 /* RxB :: anaRxAControl3 :: en_vcctrl [13:13] */
 #define RXB_ANARXACONTROL3_EN_VCCTRL_MASK                          0x2000
 #define RXB_ANARXACONTROL3_EN_VCCTRL_ALIGN                         0
 #define RXB_ANARXACONTROL3_EN_VCCTRL_BITS                          1
 #define RXB_ANARXACONTROL3_EN_VCCTRL_SHIFT                         13
 
 /* RxB :: anaRxAControl3 :: sel_th4dfe1 [12:12] */
 #define RXB_ANARXACONTROL3_SEL_TH4DFE1_MASK                        0x1000
 #define RXB_ANARXACONTROL3_SEL_TH4DFE1_ALIGN                       0
 #define RXB_ANARXACONTROL3_SEL_TH4DFE1_BITS                        1
 #define RXB_ANARXACONTROL3_SEL_TH4DFE1_SHIFT                       12
 
 /* RxB :: anaRxAControl3 :: sel_th4dfe0 [11:11] */
 #define RXB_ANARXACONTROL3_SEL_TH4DFE0_MASK                        0x0800
 #define RXB_ANARXACONTROL3_SEL_TH4DFE0_ALIGN                       0
 #define RXB_ANARXACONTROL3_SEL_TH4DFE0_BITS                        1
 #define RXB_ANARXACONTROL3_SEL_TH4DFE0_SHIFT                       11
 
 /* RxB :: anaRxAControl3 :: selugbw1 [10:10] */
 #define RXB_ANARXACONTROL3_SELUGBW1_MASK                           0x0400
 #define RXB_ANARXACONTROL3_SELUGBW1_ALIGN                          0
 #define RXB_ANARXACONTROL3_SELUGBW1_BITS                           1
 #define RXB_ANARXACONTROL3_SELUGBW1_SHIFT                          10
 
 /* RxB :: anaRxAControl3 :: selugbw0 [09:09] */
 #define RXB_ANARXACONTROL3_SELUGBW0_MASK                           0x0200
 #define RXB_ANARXACONTROL3_SELUGBW0_ALIGN                          0
 #define RXB_ANARXACONTROL3_SELUGBW0_BITS                           1
 #define RXB_ANARXACONTROL3_SELUGBW0_SHIFT                          9
 
 /* RxB :: anaRxAControl3 :: imax_dfetap [08:08] */
 #define RXB_ANARXACONTROL3_IMAX_DFETAP_MASK                        0x0100
 #define RXB_ANARXACONTROL3_IMAX_DFETAP_ALIGN                       0
 #define RXB_ANARXACONTROL3_IMAX_DFETAP_BITS                        1
 #define RXB_ANARXACONTROL3_IMAX_DFETAP_SHIFT                       8
 
 /* RxB :: anaRxAControl3 :: imode_dfetap [07:07] */
 #define RXB_ANARXACONTROL3_IMODE_DFETAP_MASK                       0x0080
 #define RXB_ANARXACONTROL3_IMODE_DFETAP_ALIGN                      0
 #define RXB_ANARXACONTROL3_IMODE_DFETAP_BITS                       1
 #define RXB_ANARXACONTROL3_IMODE_DFETAP_SHIFT                      7
 
 /* RxB :: anaRxAControl3 :: imin_dfetap [06:06] */
 #define RXB_ANARXACONTROL3_IMIN_DFETAP_MASK                        0x0040
 #define RXB_ANARXACONTROL3_IMIN_DFETAP_ALIGN                       0
 #define RXB_ANARXACONTROL3_IMIN_DFETAP_BITS                        1
 #define RXB_ANARXACONTROL3_IMIN_DFETAP_SHIFT                       6
 
 /* RxB :: anaRxAControl3 :: imax_slcd2c [05:05] */
 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_MASK                        0x0020
 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_ALIGN                       0
 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_BITS                        1
 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_SHIFT                       5
 
 /* RxB :: anaRxAControl3 :: imode_slcd2c [04:04] */
 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_MASK                       0x0010
 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_ALIGN                      0
 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_BITS                       1
 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_SHIFT                      4
 
 /* RxB :: anaRxAControl3 :: imin_slcd2c [03:03] */
 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_MASK                        0x0008
 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_ALIGN                       0
 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_BITS                        1
 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_SHIFT                       3
 
 /* RxB :: anaRxAControl3 :: imax_dfevref [02:02] */
 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_MASK                       0x0004
 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_ALIGN                      0
 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_BITS                       1
 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_SHIFT                      2
 
 /* RxB :: anaRxAControl3 :: imode_dfevref [01:01] */
 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_MASK                      0x0002
 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_ALIGN                     0
 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_BITS                      1
 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_SHIFT                     1
 
 /* RxB :: anaRxAControl3 :: imin_dfevref [00:00] */
 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_MASK                       0x0001
 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_ALIGN                      0
 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_BITS                       1
 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_SHIFT                      0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk2
  */
 /****************************************************************************
  * XgxsBlk2 :: rxLnSwap
  */
 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_en [15:15] */
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_MASK                        0x8000
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_ALIGN                       0
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_BITS                        1
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_SHIFT                       15
 
 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_force_en [14:14] */
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_MASK                  0x4000
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_ALIGN                 0
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_BITS                  1
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_SHIFT                 14
 
 /* XgxsBlk2 :: rxLnSwap :: Qset_prog_en [13:13] */
 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_MASK                        0x2000
 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_ALIGN                       0
 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_BITS                        1
 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_SHIFT                       13
 
 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_link_en [12:12] */
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_MASK                   0x1000
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_ALIGN                  0
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_BITS                   1
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_SHIFT                  12
 
 /* XgxsBlk2 :: rxLnSwap :: Q0_msb [11:11] */
 #define XGXSBLK2_RXLNSWAP_Q0_MSB_MASK                              0x0800
 #define XGXSBLK2_RXLNSWAP_Q0_MSB_ALIGN                             0
 #define XGXSBLK2_RXLNSWAP_Q0_MSB_BITS                              1
 #define XGXSBLK2_RXLNSWAP_Q0_MSB_SHIFT                             11
 
 /* XgxsBlk2 :: rxLnSwap :: Q1_msb [10:10] */
 #define XGXSBLK2_RXLNSWAP_Q1_MSB_MASK                              0x0400
 #define XGXSBLK2_RXLNSWAP_Q1_MSB_ALIGN                             0
 #define XGXSBLK2_RXLNSWAP_Q1_MSB_BITS                              1
 #define XGXSBLK2_RXLNSWAP_Q1_MSB_SHIFT                             10
 
 /* XgxsBlk2 :: rxLnSwap :: Q2_msb [09:09] */
 #define XGXSBLK2_RXLNSWAP_Q2_MSB_MASK                              0x0200
 #define XGXSBLK2_RXLNSWAP_Q2_MSB_ALIGN                             0
 #define XGXSBLK2_RXLNSWAP_Q2_MSB_BITS                              1
 #define XGXSBLK2_RXLNSWAP_Q2_MSB_SHIFT                             9
 
 /* XgxsBlk2 :: rxLnSwap :: Q3_msb [08:08] */
 #define XGXSBLK2_RXLNSWAP_Q3_MSB_MASK                              0x0100
 #define XGXSBLK2_RXLNSWAP_Q3_MSB_ALIGN                             0
 #define XGXSBLK2_RXLNSWAP_Q3_MSB_BITS                              1
 #define XGXSBLK2_RXLNSWAP_Q3_MSB_SHIFT                             8
 
 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force0 [07:06] */
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_MASK                    0x00c0
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_ALIGN                   0
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_BITS                    2
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_SHIFT                   6
 
 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force1 [05:04] */
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_MASK                    0x0030
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_ALIGN                   0
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_BITS                    2
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_SHIFT                   4
 
 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force2 [03:02] */
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_MASK                    0x000c
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_ALIGN                   0
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_BITS                    2
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_SHIFT                   2
 
 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force3 [01:00] */
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_MASK                    0x0003
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_ALIGN                   0
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_BITS                    2
 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_SHIFT                   0
 
 
 /****************************************************************************
  * XgxsBlk2 :: txLnSwap
  */
 /* XgxsBlk2 :: txLnSwap :: tx_lnswap_en [15:15] */
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_MASK                        0x8000
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_ALIGN                       0
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_BITS                        1
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_SHIFT                       15
 
 /* XgxsBlk2 :: txLnSwap :: reserved0 [14:08] */
 #define XGXSBLK2_TXLNSWAP_RESERVED0_MASK                           0x7f00
 #define XGXSBLK2_TXLNSWAP_RESERVED0_ALIGN                          0
 #define XGXSBLK2_TXLNSWAP_RESERVED0_BITS                           7
 #define XGXSBLK2_TXLNSWAP_RESERVED0_SHIFT                          8
 
 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force0 [07:06] */
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_MASK                    0x00c0
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_ALIGN                   0
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_BITS                    2
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_SHIFT                   6
 
 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force1 [05:04] */
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_MASK                    0x0030
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_ALIGN                   0
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_BITS                    2
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_SHIFT                   4
 
 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force2 [03:02] */
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_MASK                    0x000c
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_ALIGN                   0
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_BITS                    2
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_SHIFT                   2
 
 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force3 [01:00] */
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_MASK                    0x0003
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_ALIGN                   0
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_BITS                    2
 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_SHIFT                   0
 
 
 /****************************************************************************
  * XgxsBlk2 :: QsetLns01
  */
 /* XgxsBlk2 :: QsetLns01 :: Q1 [15:08] */
 #define XGXSBLK2_QSETLNS01_Q1_MASK                                 0xff00
 #define XGXSBLK2_QSETLNS01_Q1_ALIGN                                0
 #define XGXSBLK2_QSETLNS01_Q1_BITS                                 8
 #define XGXSBLK2_QSETLNS01_Q1_SHIFT                                8
 
 /* XgxsBlk2 :: QsetLns01 :: Q0 [07:00] */
 #define XGXSBLK2_QSETLNS01_Q0_MASK                                 0x00ff
 #define XGXSBLK2_QSETLNS01_Q0_ALIGN                                0
 #define XGXSBLK2_QSETLNS01_Q0_BITS                                 8
 #define XGXSBLK2_QSETLNS01_Q0_SHIFT                                0
 
 
 /****************************************************************************
  * XgxsBlk2 :: QsetLns23
  */
 /* XgxsBlk2 :: QsetLns23 :: Q3 [15:08] */
 #define XGXSBLK2_QSETLNS23_Q3_MASK                                 0xff00
 #define XGXSBLK2_QSETLNS23_Q3_ALIGN                                0
 #define XGXSBLK2_QSETLNS23_Q3_BITS                                 8
 #define XGXSBLK2_QSETLNS23_Q3_SHIFT                                8
 
 /* XgxsBlk2 :: QsetLns23 :: Q2 [07:00] */
 #define XGXSBLK2_QSETLNS23_Q2_MASK                                 0x00ff
 #define XGXSBLK2_QSETLNS23_Q2_ALIGN                                0
 #define XGXSBLK2_QSETLNS23_Q2_BITS                                 8
 #define XGXSBLK2_QSETLNS23_Q2_SHIFT                                0
 
 
 /****************************************************************************
  * XgxsBlk2 :: unicoreMode10g
  */
 /* XgxsBlk2 :: unicoreMode10g :: reserved0 [15:08] */
 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_MASK                     0xff00
 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_ALIGN                    0
 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_BITS                     8
 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_SHIFT                    8
 
 /* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gHiG [07:04] */
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_MASK             0x00f0
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_ALIGN            0
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_BITS             4
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT            4
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS             0
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXG_nCC         1
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_Indlane_OS8      4
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_IndLane_OS5      5
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PCI              7
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQ         8
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQnCC      9
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PBypass          10
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PBypass_nDSK     11
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_ComboCoreMode    12
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_Clocks_off       15
 
 /* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gCx4 [03:00] */
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_MASK             0x000f
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_ALIGN            0
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_BITS             4
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT            0
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS             0
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXG_nCC         1
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_Indlane_OS8      4
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_IndLane_OS5      5
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PCI              7
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS_nLQ         8
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS_nLQnCC      9
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PBypass          10
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PBypass_nDSK     11
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_ComboCoreMode    12
 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_Clocks_off       15
 
 
 /****************************************************************************
  * XgxsBlk2 :: indCombCtrl
  */
 /* XgxsBlk2 :: indCombCtrl :: reserved0 [15:02] */
 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_MASK                        0xfffc
 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_ALIGN                       0
 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_BITS                        14
 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_SHIFT                       2
 
 /* XgxsBlk2 :: indCombCtrl :: masterLn_indx [01:00] */
 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_MASK                    0x0003
 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_ALIGN                   0
 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_BITS                    2
 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_SHIFT                   0
 
 
 /****************************************************************************
  * XgxsBlk2 :: TestModeLane
  */
 /* XgxsBlk2 :: TestModeLane :: eee_fast_timer_en [15:15] */
 #define XGXSBLK2_TESTMODELANE_EEE_FAST_TIMER_EN_MASK               0x8000
 #define XGXSBLK2_TESTMODELANE_EEE_FAST_TIMER_EN_ALIGN              0
 #define XGXSBLK2_TESTMODELANE_EEE_FAST_TIMER_EN_BITS               1
 #define XGXSBLK2_TESTMODELANE_EEE_FAST_TIMER_EN_SHIFT              15
 
 /* XgxsBlk2 :: TestModeLane :: eee_gateclk_en [14:14] */
 #define XGXSBLK2_TESTMODELANE_EEE_GATECLK_EN_MASK                  0x4000
 #define XGXSBLK2_TESTMODELANE_EEE_GATECLK_EN_ALIGN                 0
 #define XGXSBLK2_TESTMODELANE_EEE_GATECLK_EN_BITS                  1
 #define XGXSBLK2_TESTMODELANE_EEE_GATECLK_EN_SHIFT                 14
 
 /* XgxsBlk2 :: TestModeLane :: eee_gateoutclk_en [13:13] */
 #define XGXSBLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_MASK               0x2000
 #define XGXSBLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_ALIGN              0
 #define XGXSBLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_BITS               1
 #define XGXSBLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_SHIFT              13
 
 /* XgxsBlk2 :: TestModeLane :: tx_lowpwr_6g_over_val [12:12] */
 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_VAL_MASK           0x1000
 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_VAL_ALIGN          0
 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_VAL_BITS           1
 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_VAL_SHIFT          12
 
 /* XgxsBlk2 :: TestModeLane :: tx_lowpwr_6g_over [11:11] */
 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_MASK               0x0800
 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_ALIGN              0
 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_BITS               1
 #define XGXSBLK2_TESTMODELANE_TX_LOWPWR_6G_OVER_SHIFT              11
 
 /* XgxsBlk2 :: TestModeLane :: reserved0 [10:02] */
 #define XGXSBLK2_TESTMODELANE_RESERVED0_MASK                       0x07fc
 #define XGXSBLK2_TESTMODELANE_RESERVED0_ALIGN                      0
 #define XGXSBLK2_TESTMODELANE_RESERVED0_BITS                       9
 #define XGXSBLK2_TESTMODELANE_RESERVED0_SHIFT                      2
 
 /* XgxsBlk2 :: TestModeLane :: slice_selector [01:00] */
 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_MASK                  0x0003
 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_ALIGN                 0
 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_BITS                  2
 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_SHIFT                 0
 
 
 /****************************************************************************
  * XgxsBlk2 :: TestModeCombo
  */
 /* XgxsBlk2 :: TestModeCombo :: reserved0 [15:12] */
 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_MASK                      0xf000
 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_ALIGN                     0
 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_BITS                      4
 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_SHIFT                     12
 
 /* XgxsBlk2 :: TestModeCombo :: test_monitor_mode2 [11:06] */
 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_MASK             0x0fc0
 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_ALIGN            0
 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_BITS             6
 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_SHIFT            6
 
 /* XgxsBlk2 :: TestModeCombo :: test_monitor_mode1 [05:00] */
 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_MASK             0x003f
 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_ALIGN            0
 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_BITS             6
 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_SHIFT            0
 
 
 /****************************************************************************
  * XgxsBlk2 :: TestModeMux
  */
 /* XgxsBlk2 :: TestModeMux :: to_dig_mux_ovr3 [15:14] */
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR3_MASK                  0xc000
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR3_ALIGN                 0
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR3_BITS                  2
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR3_SHIFT                 14
 
 /* XgxsBlk2 :: TestModeMux :: to_dig_mux_ovr2 [13:12] */
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR2_MASK                  0x3000
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR2_ALIGN                 0
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR2_BITS                  2
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR2_SHIFT                 12
 
 /* XgxsBlk2 :: TestModeMux :: to_dig_mux_ovr1 [11:10] */
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR1_MASK                  0x0c00
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR1_ALIGN                 0
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR1_BITS                  2
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR1_SHIFT                 10
 
 /* XgxsBlk2 :: TestModeMux :: to_dig_mux_ovr0 [09:08] */
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR0_MASK                  0x0300
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR0_ALIGN                 0
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR0_BITS                  2
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR0_SHIFT                 8
 
 /* XgxsBlk2 :: TestModeMux :: to_dig_mux_ovr_en [07:07] */
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR_EN_MASK                0x0080
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR_EN_ALIGN               0
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR_EN_BITS                1
 #define XGXSBLK2_TESTMODEMUX_TO_DIG_MUX_OVR_EN_SHIFT               7
 
 /* XgxsBlk2 :: TestModeMux :: reserved0 [06:04] */
 #define XGXSBLK2_TESTMODEMUX_RESERVED0_MASK                        0x0070
 #define XGXSBLK2_TESTMODEMUX_RESERVED0_ALIGN                       0
 #define XGXSBLK2_TESTMODEMUX_RESERVED0_BITS                        3
 #define XGXSBLK2_TESTMODEMUX_RESERVED0_SHIFT                       4
 
 /* XgxsBlk2 :: TestModeMux :: tmux_sel [03:01] */
 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_MASK                         0x000e
 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_ALIGN                        0
 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_BITS                         3
 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_SHIFT                        1
 
 /* XgxsBlk2 :: TestModeMux :: tmux_en [00:00] */
 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_MASK                          0x0001
 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_ALIGN                         0
 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_BITS                          1
 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_SHIFT                         0
 
 
 /****************************************************************************
  * XgxsBlk2 :: cx4SigdetCnt
  */
 /* XgxsBlk2 :: cx4SigdetCnt :: cx4SigdetCnt [15:00] */
 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_MASK                    0xffff
 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_ALIGN                   0
 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_BITS                    16
 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_SHIFT                   0
 
 
 /****************************************************************************
  * XgxsBlk2 :: laneReset
  */
 /* XgxsBlk2 :: laneReset :: reset_mdio [15:15] */
 #define XGXSBLK2_LANERESET_RESET_MDIO_MASK                         0x8000
 #define XGXSBLK2_LANERESET_RESET_MDIO_ALIGN                        0
 #define XGXSBLK2_LANERESET_RESET_MDIO_BITS                         1
 #define XGXSBLK2_LANERESET_RESET_MDIO_SHIFT                        15
 
 /* XgxsBlk2 :: laneReset :: reserved0 [14:09] */
 #define XGXSBLK2_LANERESET_RESERVED0_MASK                          0x7e00
 #define XGXSBLK2_LANERESET_RESERVED0_ALIGN                         0
 #define XGXSBLK2_LANERESET_RESERVED0_BITS                          6
 #define XGXSBLK2_LANERESET_RESERVED0_SHIFT                         9
 
 /* XgxsBlk2 :: laneReset :: reset_pll [08:08] */
 #define XGXSBLK2_LANERESET_RESET_PLL_MASK                          0x0100
 #define XGXSBLK2_LANERESET_RESET_PLL_ALIGN                         0
 #define XGXSBLK2_LANERESET_RESET_PLL_BITS                          1
 #define XGXSBLK2_LANERESET_RESET_PLL_SHIFT                         8
 
 /* XgxsBlk2 :: laneReset :: reset_tx [07:04] */
 #define XGXSBLK2_LANERESET_RESET_TX_MASK                           0x00f0
 #define XGXSBLK2_LANERESET_RESET_TX_ALIGN                          0
 #define XGXSBLK2_LANERESET_RESET_TX_BITS                           4
 #define XGXSBLK2_LANERESET_RESET_TX_SHIFT                          4
 
 /* XgxsBlk2 :: laneReset :: reset_rx [03:00] */
 #define XGXSBLK2_LANERESET_RESET_RX_MASK                           0x000f
 #define XGXSBLK2_LANERESET_RESET_RX_ALIGN                          0
 #define XGXSBLK2_LANERESET_RESET_RX_BITS                           4
 #define XGXSBLK2_LANERESET_RESET_RX_SHIFT                          0
 
 
 /****************************************************************************
  * XgxsBlk2 :: xgxsStatus6
  */
 /* XgxsBlk2 :: xgxsStatus6 :: reserved0 [15:11] */
 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_MASK                        0xf800
 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_ALIGN                       0
 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_BITS                        5
 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_SHIFT                       11
 
 /* XgxsBlk2 :: xgxsStatus6 :: hcd_over_1g [10:00] */
 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_MASK                      0x07ff
 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_ALIGN                     0
 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_BITS                      11
 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk2 :: Aswap66Control1
  */
 /* XgxsBlk2 :: Aswap66Control1 :: swap_count64B66B [15:00] */
 #define XGXSBLK2_ASWAP66CONTROL1_SWAP_COUNT64B66B_MASK             0xffff
 #define XGXSBLK2_ASWAP66CONTROL1_SWAP_COUNT64B66B_ALIGN            0
 #define XGXSBLK2_ASWAP66CONTROL1_SWAP_COUNT64B66B_BITS             16
 #define XGXSBLK2_ASWAP66CONTROL1_SWAP_COUNT64B66B_SHIFT            0
 
 
 /****************************************************************************
  * XgxsBlk2 :: Aswap66Control2
  */
 /* XgxsBlk2 :: Aswap66Control2 :: reserved0 [15:12] */
 #define XGXSBLK2_ASWAP66CONTROL2_RESERVED0_MASK                    0xf000
 #define XGXSBLK2_ASWAP66CONTROL2_RESERVED0_ALIGN                   0
 #define XGXSBLK2_ASWAP66CONTROL2_RESERVED0_BITS                    4
 #define XGXSBLK2_ASWAP66CONTROL2_RESERVED0_SHIFT                   12
 
 /* XgxsBlk2 :: Aswap66Control2 :: prst_by_bypass_en [11:11] */
 #define XGXSBLK2_ASWAP66CONTROL2_PRST_BY_BYPASS_EN_MASK            0x0800
 #define XGXSBLK2_ASWAP66CONTROL2_PRST_BY_BYPASS_EN_ALIGN           0
 #define XGXSBLK2_ASWAP66CONTROL2_PRST_BY_BYPASS_EN_BITS            1
 #define XGXSBLK2_ASWAP66CONTROL2_PRST_BY_BYPASS_EN_SHIFT           11
 
 /* XgxsBlk2 :: Aswap66Control2 :: rx10_fifo_bypass_override_en [10:10] */
 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_EN_MASK 0x0400
 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_EN_ALIGN 0
 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_EN_BITS 1
 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_EN_SHIFT 10
 
 /* XgxsBlk2 :: Aswap66Control2 :: rx10_fifo_bypass_override_val [09:09] */
 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_VAL_MASK 0x0200
 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_VAL_ALIGN 0
 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_VAL_BITS 1
 #define XGXSBLK2_ASWAP66CONTROL2_RX10_FIFO_BYPASS_OVERRIDE_VAL_SHIFT 9
 
 /* XgxsBlk2 :: Aswap66Control2 :: swap_count_sel_override_en [08:08] */
 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_EN_MASK   0x0100
 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_EN_ALIGN  0
 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_EN_BITS   1
 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_EN_SHIFT  8
 
 /* XgxsBlk2 :: Aswap66Control2 :: swap_count_sel_override_val [07:07] */
 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_VAL_MASK  0x0080
 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_VAL_ALIGN 0
 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_VAL_BITS  1
 #define XGXSBLK2_ASWAP66CONTROL2_SWAP_COUNT_SEL_OVERRIDE_VAL_SHIFT 7
 
 /* XgxsBlk2 :: Aswap66Control2 :: dswin_sel_override_en [06:06] */
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_EN_MASK        0x0040
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_EN_ALIGN       0
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_EN_BITS        1
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_EN_SHIFT       6
 
 /* XgxsBlk2 :: Aswap66Control2 :: dswin_sel_override_val [05:05] */
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_VAL_MASK       0x0020
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_VAL_ALIGN      0
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_VAL_BITS       1
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN_SEL_OVERRIDE_VAL_SHIFT      5
 
 /* XgxsBlk2 :: Aswap66Control2 :: dswin64B66B [04:00] */
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN64B66B_MASK                  0x001f
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN64B66B_ALIGN                 0
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN64B66B_BITS                  5
 #define XGXSBLK2_ASWAP66CONTROL2_DSWIN64B66B_SHIFT                 0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk3
  */
 /****************************************************************************
  * XgxsBlk3 :: localStatus
  */
 /* XgxsBlk3 :: localStatus :: reserved0 [15:03] */
 #define XGXSBLK3_LOCALSTATUS_RESERVED0_MASK                        0xfff8
 #define XGXSBLK3_LOCALSTATUS_RESERVED0_ALIGN                       0
 #define XGXSBLK3_LOCALSTATUS_RESERVED0_BITS                        13
 #define XGXSBLK3_LOCALSTATUS_RESERVED0_SHIFT                       3
 
 /* XgxsBlk3 :: localStatus :: localIACRdy [02:02] */
 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_MASK                      0x0004
 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_ALIGN                     0
 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_BITS                      1
 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_SHIFT                     2
 
 /* XgxsBlk3 :: localStatus :: localRdDataRdy [01:01] */
 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_MASK                   0x0002
 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_ALIGN                  0
 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_BITS                   1
 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_SHIFT                  1
 
 /* XgxsBlk3 :: localStatus :: localMdioEn [00:00] */
 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_MASK                      0x0001
 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_ALIGN                     0
 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_BITS                      1
 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk3 :: localControl0
  */
 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln3_msb [15:15] */
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_MASK            0x8000
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_ALIGN           0
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_BITS            1
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_SHIFT           15
 
 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln2_msb [14:14] */
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_MASK            0x4000
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_ALIGN           0
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_BITS            1
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_SHIFT           14
 
 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln1_msb [13:13] */
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_MASK            0x2000
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_ALIGN           0
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_BITS            1
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_SHIFT           13
 
 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln0_msb [12:12] */
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_MASK            0x1000
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_ALIGN           0
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_BITS            1
 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_SHIFT           12
 
 /* XgxsBlk3 :: localControl0 :: reserved0 [11:08] */
 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_MASK                      0x0f00
 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_ALIGN                     0
 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_BITS                      4
 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_SHIFT                     8
 
 /* XgxsBlk3 :: localControl0 :: Q0_DetDis [07:07] */
 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_MASK                      0x0080
 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_ALIGN                     0
 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_BITS                      1
 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_SHIFT                     7
 
 /* XgxsBlk3 :: localControl0 :: remoteMdioPassThru [06:06] */
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_MASK             0x0040
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_ALIGN            0
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_BITS             1
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_SHIFT            6
 
 /* XgxsBlk3 :: localControl0 :: remoteMdioEndPnt [05:05] */
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_MASK               0x0020
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_ALIGN              0
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_BITS               1
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_SHIFT              5
 
 /* XgxsBlk3 :: localControl0 :: extRemoteMdioEn [04:04] */
 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_MASK                0x0010
 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_ALIGN               0
 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_BITS                1
 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_SHIFT               4
 
 /* XgxsBlk3 :: localControl0 :: rx_inBandMdio_rst [03:03] */
 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_MASK              0x0008
 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_ALIGN             0
 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_BITS              1
 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_SHIFT             3
 
 /* XgxsBlk3 :: localControl0 :: tx_inBandMdio_rst [02:02] */
 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_MASK              0x0004
 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_ALIGN             0
 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_BITS              1
 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_SHIFT             2
 
 /* XgxsBlk3 :: localControl0 :: localWriteReq [01:01] */
 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_MASK                  0x0002
 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_ALIGN                 0
 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_BITS                  1
 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_SHIFT                 1
 
 /* XgxsBlk3 :: localControl0 :: remoteMdioEn_reg [00:00] */
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_MASK               0x0001
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_ALIGN              0
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_BITS               1
 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_SHIFT              0
 
 
 /****************************************************************************
  * XgxsBlk3 :: localControl1
  */
 /* XgxsBlk3 :: localControl1 :: rx_inBandMdio_Q0 [15:08] */
 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_MASK               0xff00
 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_ALIGN              0
 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_BITS               8
 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_SHIFT              8
 
 /* XgxsBlk3 :: localControl1 :: reserved0 [07:04] */
 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_MASK                      0x00f0
 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_ALIGN                     0
 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_BITS                      4
 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_SHIFT                     4
 
 /* XgxsBlk3 :: localControl1 :: localRemoteErrorClr [03:03] */
 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_MASK            0x0008
 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_ALIGN           0
 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_BITS            1
 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_SHIFT           3
 
 /* XgxsBlk3 :: localControl1 :: rx_inBandMdioStatSel [02:00] */
 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_MASK           0x0007
 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_ALIGN          0
 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_BITS           3
 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_SHIFT          0
 
 
 /****************************************************************************
  * XgxsBlk3 :: remoteWrite03
  */
 /* XgxsBlk3 :: remoteWrite03 :: localWrite_ln0_lsb [15:08] */
 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_MASK             0xff00
 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_ALIGN            0
 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_BITS             8
 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_SHIFT            8
 
 /* XgxsBlk3 :: remoteWrite03 :: localWrite_ln3_lsb [07:00] */
 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_MASK             0x00ff
 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_ALIGN            0
 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_BITS             8
 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_SHIFT            0
 
 
 /****************************************************************************
  * XgxsBlk3 :: remoteWrite12
  */
 /* XgxsBlk3 :: remoteWrite12 :: localWrite_ln1_lsb [15:08] */
 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_MASK             0xff00
 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_ALIGN            0
 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_BITS             8
 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_SHIFT            8
 
 /* XgxsBlk3 :: remoteWrite12 :: localWrite_ln2_lsb [07:00] */
 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_MASK             0x00ff
 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_ALIGN            0
 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_BITS             8
 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_SHIFT            0
 
 
 /****************************************************************************
  * XgxsBlk3 :: remoteRead12
  */
 /* XgxsBlk3 :: remoteRead12 :: localRdData [15:00] */
 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_MASK                     0xffff
 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_ALIGN                    0
 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_BITS                     16
 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_SHIFT                    0
 
 
 /****************************************************************************
  * XgxsBlk3 :: remoteReadx3
  */
 /* XgxsBlk3 :: remoteReadx3 :: reserved0 [15:08] */
 #define XGXSBLK3_REMOTEREADX3_RESERVED0_MASK                       0xff00
 #define XGXSBLK3_REMOTEREADX3_RESERVED0_ALIGN                      0
 #define XGXSBLK3_REMOTEREADX3_RESERVED0_BITS                       8
 #define XGXSBLK3_REMOTEREADX3_RESERVED0_SHIFT                      8
 
 /* XgxsBlk3 :: remoteReadx3 :: localRdDataId [07:00] */
 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_MASK                   0x00ff
 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_ALIGN                  0
 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_BITS                   8
 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_SHIFT                  0
 
 
 /****************************************************************************
  * XgxsBlk3 :: rx_inBandMdioStat
  */
 /* union - case remoteStatus [15:00] */
 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteStatus [15:00] */
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_MASK  0xffff
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_ALIGN 0
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_BITS  16
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_SHIFT 0
 
 
 /* union - case remoteControl [15:00] */
 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteControl [15:00] */
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_MASK 0xffff
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_ALIGN 0
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_BITS 16
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_SHIFT 0
 
 
 /* union - case remoteAddr [15:00] */
 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteAddr [15:00] */
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_MASK      0xffff
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_ALIGN     0
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_BITS      16
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_SHIFT     0
 
 
 /* union - case remoteWrtData [15:00] */
 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteWrtData [15:00] */
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_MASK 0xffff
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_ALIGN 0
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_BITS 16
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_SHIFT 0
 
 
 /* union - case remoteIACn_sel [15:00] */
 /* XgxsBlk3 :: rx_inBandMdioStat :: reserved0 [15:08] */
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_MASK   0xff00
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_ALIGN  0
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_BITS   8
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_SHIFT  8
 
 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteIACn [07:00] */
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_MASK  0x00ff
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_ALIGN 0
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_BITS  8
 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_SHIFT 0
 
 
 /* union - case rx_inBandTestBus [15:00] */
 /* XgxsBlk3 :: rx_inBandMdioStat :: rx_inBandTestBus [15:00] */
 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_MASK 0xffff
 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_ALIGN 0
 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_BITS 16
 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_SHIFT 0
 
 
 /* union - case StatusOff [15:00] */
 /* XgxsBlk3 :: rx_inBandMdioStat :: reserved0 [15:00] */
 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_MASK        0xffff
 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_ALIGN       0
 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_BITS        16
 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_SHIFT       0
 
 
 
 /****************************************************************************
  * XgxsBlk3 :: localIAC
  */
 /* XgxsBlk3 :: localIAC :: IAC_ln1_ln2 [15:08] */
 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_MASK                         0xff00
 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_ALIGN                        0
 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_BITS                         8
 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_SHIFT                        8
 
 /* XgxsBlk3 :: localIAC :: reserved0 [07:01] */
 #define XGXSBLK3_LOCALIAC_RESERVED0_MASK                           0x00fe
 #define XGXSBLK3_LOCALIAC_RESERVED0_ALIGN                          0
 #define XGXSBLK3_LOCALIAC_RESERVED0_BITS                           7
 #define XGXSBLK3_LOCALIAC_RESERVED0_SHIFT                          1
 
 /* XgxsBlk3 :: localIAC :: localIACReq [00:00] */
 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_MASK                         0x0001
 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_ALIGN                        0
 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_BITS                         1
 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_SHIFT                        0
 
 
 /****************************************************************************
  * XgxsBlk3 :: remoteIACn
  */
 /* XgxsBlk3 :: remoteIACn :: reserved0 [15:08] */
 #define XGXSBLK3_REMOTEIACN_RESERVED0_MASK                         0xff00
 #define XGXSBLK3_REMOTEIACN_RESERVED0_ALIGN                        0
 #define XGXSBLK3_REMOTEIACN_RESERVED0_BITS                         8
 #define XGXSBLK3_REMOTEIACN_RESERVED0_SHIFT                        8
 
 /* XgxsBlk3 :: remoteIACn :: localIACn [07:00] */
 #define XGXSBLK3_REMOTEIACN_LOCALIACN_MASK                         0x00ff
 #define XGXSBLK3_REMOTEIACN_LOCALIACN_ALIGN                        0
 #define XGXSBLK3_REMOTEIACN_LOCALIACN_BITS                         8
 #define XGXSBLK3_REMOTEIACN_LOCALIACN_SHIFT                        0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk4
  */
 /****************************************************************************
  * XgxsBlk4 :: MiscRxStatus
  */
 /* union - case statusSelect0 [15:00] */
 /* XgxsBlk4 :: MiscRxStatus :: capture_NP_lh [15:15] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK     0x8000
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN    0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS     1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT    15
 
 /* XgxsBlk4 :: MiscRxStatus :: teton_brk_link_lh [14:14] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14
 
 /* XgxsBlk4 :: MiscRxStatus :: UP3_lh [13:13] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK            0x2000
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN           0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS            1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT           13
 
 /* XgxsBlk4 :: MiscRxStatus :: MP5_lh [12:12] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK            0x1000
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN           0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS            1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT           12
 
 /* XgxsBlk4 :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11
 
 /* XgxsBlk4 :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10
 
 /* XgxsBlk4 :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9
 
 /* XgxsBlk4 :: MiscRxStatus :: invalidSeq_lh [08:08] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK     0x0100
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN    0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS     1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT    8
 
 /* XgxsBlk4 :: MiscRxStatus :: nullMP_lh [07:07] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK         0x0080
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN        0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS         1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT        7
 
 /* XgxsBlk4 :: MiscRxStatus :: remotePhyMP_lh [06:06] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK    0x0040
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN   0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS    1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT   6
 
 /* XgxsBlk4 :: MiscRxStatus :: nonMatchingMP_lh [05:05] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK  0x0020
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS  1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5
 
 /* XgxsBlk4 :: MiscRxStatus :: over1gMP_lh [04:04] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK       0x0010
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN      0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS       1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT      4
 
 /* XgxsBlk4 :: MiscRxStatus :: rx_config_is_0_lh [03:03] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3
 
 /* XgxsBlk4 :: MiscRxStatus :: np_toggle_err_lh [02:02] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK  0x0004
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS  1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2
 
 /* XgxsBlk4 :: MiscRxStatus :: mr_np_lh [01:01] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK          0x0002
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN         0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS          1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT         1
 
 /* XgxsBlk4 :: MiscRxStatus :: mr_bp_lh [00:00] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK          0x0001
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN         0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS          1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT         0
 
 
 /* union - case statusSelect1 [15:00] */
 /* XgxsBlk4 :: MiscRxStatus :: reserved0 [15:04] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK         0xfff0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN        0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS         12
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT        4
 
 /* XgxsBlk4 :: MiscRxStatus :: np_count [03:00] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK          0x000f
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN         0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS          4
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT         0
 
 
 /* union - case statusSelect2 [15:00] */
 /* XgxsBlk4 :: MiscRxStatus :: reserved0 [15:06] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK         0xffc0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN        0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS         10
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT        6
 
 /* XgxsBlk4 :: MiscRxStatus :: remote_phy_enable [05:05] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5
 
 /* XgxsBlk4 :: MiscRxStatus :: det_teton_mode [04:04] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK    0x0010
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN   0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS    1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT   4
 
 /* XgxsBlk4 :: MiscRxStatus :: cu_linkdown [03:03] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK       0x0008
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN      0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS       1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT      3
 
 /* XgxsBlk4 :: MiscRxStatus :: cu_resolution_error [02:02] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2
 
 /* XgxsBlk4 :: MiscRxStatus :: remotePhy_autosel [01:01] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1
 
 /* XgxsBlk4 :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0
 
 
 /* union - case statusSelect3 [15:00] */
 /* XgxsBlk4 :: MiscRxStatus :: reserved0 [15:06] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_MASK         0xffc0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_ALIGN        0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_BITS         10
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_SHIFT        6
 
 /* XgxsBlk4 :: MiscRxStatus :: sgmii_selector_mismatch [05:05] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_MASK 0x0020
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_SHIFT 5
 
 /* XgxsBlk4 :: MiscRxStatus :: autoneg_enable_ov [04:04] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_MASK 0x0010
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_ALIGN 0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_BITS 1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_SHIFT 4
 
 /* XgxsBlk4 :: MiscRxStatus :: s_mr_an_enable [03:03] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_MASK    0x0008
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_ALIGN   0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_BITS    1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_SHIFT   3
 
 /* XgxsBlk4 :: MiscRxStatus :: s_cl73_rslv_KX4 [02:02] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_MASK   0x0004
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_ALIGN  0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_BITS   1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_SHIFT  2
 
 /* XgxsBlk4 :: MiscRxStatus :: s_cl73_rslv_KX [01:01] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_MASK    0x0002
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_ALIGN   0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_BITS    1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_SHIFT   1
 
 /* XgxsBlk4 :: MiscRxStatus :: KX_detect [00:00] */
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_MASK         0x0001
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_ALIGN        0
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_BITS         1
 #define XGXSBLK4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_SHIFT        0
 
 
 
 /****************************************************************************
  * XgxsBlk4 :: xgxsStatus0
  */
 /* XgxsBlk4 :: xgxsStatus0 :: status_en [15:15] */
 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_MASK                        0x8000
 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_ALIGN                       0
 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_BITS                        1
 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_SHIFT                       15
 
 /* XgxsBlk4 :: xgxsStatus0 :: reserved0 [14:14] */
 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_MASK                        0x4000
 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_ALIGN                       0
 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_BITS                        1
 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_SHIFT                       14
 
 /* XgxsBlk4 :: xgxsStatus0 :: tx_remote_fault [13:13] */
 #define XGXSBLK4_XGXSSTATUS0_TX_REMOTE_FAULT_MASK                  0x2000
 #define XGXSBLK4_XGXSSTATUS0_TX_REMOTE_FAULT_ALIGN                 0
 #define XGXSBLK4_XGXSSTATUS0_TX_REMOTE_FAULT_BITS                  1
 #define XGXSBLK4_XGXSSTATUS0_TX_REMOTE_FAULT_SHIFT                 13
 
 /* XgxsBlk4 :: xgxsStatus0 :: rx_remote_fault [12:12] */
 #define XGXSBLK4_XGXSSTATUS0_RX_REMOTE_FAULT_MASK                  0x1000
 #define XGXSBLK4_XGXSSTATUS0_RX_REMOTE_FAULT_ALIGN                 0
 #define XGXSBLK4_XGXSSTATUS0_RX_REMOTE_FAULT_BITS                  1
 #define XGXSBLK4_XGXSSTATUS0_RX_REMOTE_FAULT_SHIFT                 12
 
 /* XgxsBlk4 :: xgxsStatus0 :: txpll_lock [11:11] */
 #define XGXSBLK4_XGXSSTATUS0_TXPLL_LOCK_MASK                       0x0800
 #define XGXSBLK4_XGXSSTATUS0_TXPLL_LOCK_ALIGN                      0
 #define XGXSBLK4_XGXSSTATUS0_TXPLL_LOCK_BITS                       1
 #define XGXSBLK4_XGXSSTATUS0_TXPLL_LOCK_SHIFT                      11
 
 /* XgxsBlk4 :: xgxsStatus0 :: txd_fifo_err [10:10] */
 #define XGXSBLK4_XGXSSTATUS0_TXD_FIFO_ERR_MASK                     0x0400
 #define XGXSBLK4_XGXSSTATUS0_TXD_FIFO_ERR_ALIGN                    0
 #define XGXSBLK4_XGXSSTATUS0_TXD_FIFO_ERR_BITS                     1
 #define XGXSBLK4_XGXSSTATUS0_TXD_FIFO_ERR_SHIFT                    10
 
 /* XgxsBlk4 :: xgxsStatus0 :: sequencer_done [09:09] */
 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_DONE_MASK                   0x0200
 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_DONE_ALIGN                  0
 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_DONE_BITS                   1
 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_DONE_SHIFT                  9
 
 /* XgxsBlk4 :: xgxsStatus0 :: sequencer_pass [08:08] */
 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_PASS_MASK                   0x0100
 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_PASS_ALIGN                  0
 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_PASS_BITS                   1
 #define XGXSBLK4_XGXSSTATUS0_SEQUENCER_PASS_SHIFT                  8
 
 /* XgxsBlk4 :: xgxsStatus0 :: rxferr [07:04] */
 #define XGXSBLK4_XGXSSTATUS0_RXFERR_MASK                           0x00f0
 #define XGXSBLK4_XGXSSTATUS0_RXFERR_ALIGN                          0
 #define XGXSBLK4_XGXSSTATUS0_RXFERR_BITS                           4
 #define XGXSBLK4_XGXSSTATUS0_RXFERR_SHIFT                          4
 
 /* XgxsBlk4 :: xgxsStatus0 :: pll_mode_afe [03:03] */
 #define XGXSBLK4_XGXSSTATUS0_PLL_MODE_AFE_MASK                     0x0008
 #define XGXSBLK4_XGXSSTATUS0_PLL_MODE_AFE_ALIGN                    0
 #define XGXSBLK4_XGXSSTATUS0_PLL_MODE_AFE_BITS                     1
 #define XGXSBLK4_XGXSSTATUS0_PLL_MODE_AFE_SHIFT                    3
 
 /* XgxsBlk4 :: xgxsStatus0 :: ckcmp_unflow [02:02] */
 #define XGXSBLK4_XGXSSTATUS0_CKCMP_UNFLOW_MASK                     0x0004
 #define XGXSBLK4_XGXSSTATUS0_CKCMP_UNFLOW_ALIGN                    0
 #define XGXSBLK4_XGXSSTATUS0_CKCMP_UNFLOW_BITS                     1
 #define XGXSBLK4_XGXSSTATUS0_CKCMP_UNFLOW_SHIFT                    2
 
 /* XgxsBlk4 :: xgxsStatus0 :: ckcmp_ovflow [01:01] */
 #define XGXSBLK4_XGXSSTATUS0_CKCMP_OVFLOW_MASK                     0x0002
 #define XGXSBLK4_XGXSSTATUS0_CKCMP_OVFLOW_ALIGN                    0
 #define XGXSBLK4_XGXSSTATUS0_CKCMP_OVFLOW_BITS                     1
 #define XGXSBLK4_XGXSSTATUS0_CKCMP_OVFLOW_SHIFT                    1
 
 /* XgxsBlk4 :: xgxsStatus0 :: skew_status [00:00] */
 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_MASK                      0x0001
 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_ALIGN                     0
 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_BITS                      1
 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk4 :: xgxsStatus1
  */
 /* XgxsBlk4 :: xgxsStatus1 :: mode_10g_tx [15:12] */
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_MASK                      0xf000
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_ALIGN                     0
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_BITS                      4
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_SHIFT                     12
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_XGXS                      0
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_XGXG_nCC                  1
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_Indlane_OS8               4
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_IndLane_OS5               5
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_PCI                       7
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQ                  8
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQnCC               9
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_PBypass                   10
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_PBypass_nDSK              11
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_ComboCoreMode             12
 #define XGXSBLK4_XGXSSTATUS1_MODE_10G_TX_Clocks_off                15
 
 /* XgxsBlk4 :: xgxsStatus1 :: serdesMode_en_tx [11:11] */
 #define XGXSBLK4_XGXSSTATUS1_SERDESMODE_EN_TX_MASK                 0x0800
 #define XGXSBLK4_XGXSSTATUS1_SERDESMODE_EN_TX_ALIGN                0
 #define XGXSBLK4_XGXSSTATUS1_SERDESMODE_EN_TX_BITS                 1
 #define XGXSBLK4_XGXSSTATUS1_SERDESMODE_EN_TX_SHIFT                11
 
 /* XgxsBlk4 :: xgxsStatus1 :: sgmii_mode [10:10] */
 #define XGXSBLK4_XGXSSTATUS1_SGMII_MODE_MASK                       0x0400
 #define XGXSBLK4_XGXSSTATUS1_SGMII_MODE_ALIGN                      0
 #define XGXSBLK4_XGXSSTATUS1_SGMII_MODE_BITS                       1
 #define XGXSBLK4_XGXSSTATUS1_SGMII_MODE_SHIFT                      10
 
 /* XgxsBlk4 :: xgxsStatus1 :: link10g [09:09] */
 #define XGXSBLK4_XGXSSTATUS1_LINK10G_MASK                          0x0200
 #define XGXSBLK4_XGXSSTATUS1_LINK10G_ALIGN                         0
 #define XGXSBLK4_XGXSSTATUS1_LINK10G_BITS                          1
 #define XGXSBLK4_XGXSSTATUS1_LINK10G_SHIFT                         9
 
 /* XgxsBlk4 :: xgxsStatus1 :: linkstat [08:08] */
 #define XGXSBLK4_XGXSSTATUS1_LINKSTAT_MASK                         0x0100
 #define XGXSBLK4_XGXSSTATUS1_LINKSTAT_ALIGN                        0
 #define XGXSBLK4_XGXSSTATUS1_LINKSTAT_BITS                         1
 #define XGXSBLK4_XGXSSTATUS1_LINKSTAT_SHIFT                        8
 
 /* XgxsBlk4 :: xgxsStatus1 :: autoneg_complete [07:07] */
 #define XGXSBLK4_XGXSSTATUS1_AUTONEG_COMPLETE_MASK                 0x0080
 #define XGXSBLK4_XGXSSTATUS1_AUTONEG_COMPLETE_ALIGN                0
 #define XGXSBLK4_XGXSSTATUS1_AUTONEG_COMPLETE_BITS                 1
 #define XGXSBLK4_XGXSSTATUS1_AUTONEG_COMPLETE_SHIFT                7
 
 /* XgxsBlk4 :: xgxsStatus1 :: reserved0 [06:06] */
 #define XGXSBLK4_XGXSSTATUS1_RESERVED0_MASK                        0x0040
 #define XGXSBLK4_XGXSSTATUS1_RESERVED0_ALIGN                       0
 #define XGXSBLK4_XGXSSTATUS1_RESERVED0_BITS                        1
 #define XGXSBLK4_XGXSSTATUS1_RESERVED0_SHIFT                       6
 
 /* XgxsBlk4 :: xgxsStatus1 :: pll_mode_afe [05:04] */
 #define XGXSBLK4_XGXSSTATUS1_PLL_MODE_AFE_MASK                     0x0030
 #define XGXSBLK4_XGXSSTATUS1_PLL_MODE_AFE_ALIGN                    0
 #define XGXSBLK4_XGXSSTATUS1_PLL_MODE_AFE_BITS                     2
 #define XGXSBLK4_XGXSSTATUS1_PLL_MODE_AFE_SHIFT                    4
 
 /* XgxsBlk4 :: xgxsStatus1 :: actual_speed_ln0 [03:00] */
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_MASK                 0x000f
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_ALIGN                0
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_BITS                 4
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_SHIFT                0
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10M               0
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_100M              1
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_1G                2
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_2p5G              3
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_5G_X4             4
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_6G_X4             5
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_HiG           6
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_CX4           7
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12G_HiG           8
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12p5G_X4          9
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_13G_X4            10
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_15G_X4            11
 #define XGXSBLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_16G_X4            12
 
 
 /****************************************************************************
  * XgxsBlk4 :: xgxsStatus2
  */
 /* XgxsBlk4 :: xgxsStatus2 :: gpwrdwn_rx [15:12] */
 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_RX_MASK                       0xf000
 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_RX_ALIGN                      0
 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_RX_BITS                       4
 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_RX_SHIFT                      12
 
 /* XgxsBlk4 :: xgxsStatus2 :: gpwrdwn_tx [11:08] */
 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_TX_MASK                       0x0f00
 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_TX_ALIGN                      0
 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_TX_BITS                       4
 #define XGXSBLK4_XGXSSTATUS2_GPWRDWN_TX_SHIFT                      8
 
 /* XgxsBlk4 :: xgxsStatus2 :: freq_sel_rx [07:04] */
 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_RX_MASK                      0x00f0
 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_RX_ALIGN                     0
 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_RX_BITS                      4
 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_RX_SHIFT                     4
 
 /* XgxsBlk4 :: xgxsStatus2 :: freq_sel_tx [03:00] */
 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_TX_MASK                      0x000f
 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_TX_ALIGN                     0
 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_TX_BITS                      4
 #define XGXSBLK4_XGXSSTATUS2_FREQ_SEL_TX_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk4 :: Status1000X1
  */
 /* XgxsBlk4 :: Status1000X1 :: txfifo_err_detected [15:15] */
 #define XGXSBLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK             0x8000
 #define XGXSBLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN            0
 #define XGXSBLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS             1
 #define XGXSBLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT            15
 
 /* XgxsBlk4 :: Status1000X1 :: rxfifo_err_detected [14:14] */
 #define XGXSBLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK             0x4000
 #define XGXSBLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN            0
 #define XGXSBLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS             1
 #define XGXSBLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT            14
 
 /* XgxsBlk4 :: Status1000X1 :: false_carrier_detected [13:13] */
 #define XGXSBLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK          0x2000
 #define XGXSBLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN         0
 #define XGXSBLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS          1
 #define XGXSBLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT         13
 
 /* XgxsBlk4 :: Status1000X1 :: crc_err_detected [12:12] */
 #define XGXSBLK4_STATUS1000X1_CRC_ERR_DETECTED_MASK                0x1000
 #define XGXSBLK4_STATUS1000X1_CRC_ERR_DETECTED_ALIGN               0
 #define XGXSBLK4_STATUS1000X1_CRC_ERR_DETECTED_BITS                1
 #define XGXSBLK4_STATUS1000X1_CRC_ERR_DETECTED_SHIFT               12
 
 /* XgxsBlk4 :: Status1000X1 :: tx_err_detected [11:11] */
 #define XGXSBLK4_STATUS1000X1_TX_ERR_DETECTED_MASK                 0x0800
 #define XGXSBLK4_STATUS1000X1_TX_ERR_DETECTED_ALIGN                0
 #define XGXSBLK4_STATUS1000X1_TX_ERR_DETECTED_BITS                 1
 #define XGXSBLK4_STATUS1000X1_TX_ERR_DETECTED_SHIFT                11
 
 /* XgxsBlk4 :: Status1000X1 :: rx_err_detected [10:10] */
 #define XGXSBLK4_STATUS1000X1_RX_ERR_DETECTED_MASK                 0x0400
 #define XGXSBLK4_STATUS1000X1_RX_ERR_DETECTED_ALIGN                0
 #define XGXSBLK4_STATUS1000X1_RX_ERR_DETECTED_BITS                 1
 #define XGXSBLK4_STATUS1000X1_RX_ERR_DETECTED_SHIFT                10
 
 /* XgxsBlk4 :: Status1000X1 :: carrier_extend_err_detected [09:09] */
 #define XGXSBLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK     0x0200
 #define XGXSBLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN    0
 #define XGXSBLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS     1
 #define XGXSBLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT    9
 
 /* XgxsBlk4 :: Status1000X1 :: early_end_extension_detected [08:08] */
 #define XGXSBLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK    0x0100
 #define XGXSBLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN   0
 #define XGXSBLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS    1
 #define XGXSBLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT   8
 
 /* XgxsBlk4 :: Status1000X1 :: link_status_change [07:07] */
 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_CHANGE_MASK              0x0080
 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN             0
 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_CHANGE_BITS              1
 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT             7
 
 /* XgxsBlk4 :: Status1000X1 :: pause_resolution_rxside [06:06] */
 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK         0x0040
 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN        0
 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS         1
 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT        6
 
 /* XgxsBlk4 :: Status1000X1 :: pause_resolution_txside [05:05] */
 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK         0x0020
 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN        0
 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS         1
 #define XGXSBLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT        5
 
 /* XgxsBlk4 :: Status1000X1 :: speed_status [04:03] */
 #define XGXSBLK4_STATUS1000X1_SPEED_STATUS_MASK                    0x0018
 #define XGXSBLK4_STATUS1000X1_SPEED_STATUS_ALIGN                   0
 #define XGXSBLK4_STATUS1000X1_SPEED_STATUS_BITS                    2
 #define XGXSBLK4_STATUS1000X1_SPEED_STATUS_SHIFT                   3
 
 /* XgxsBlk4 :: Status1000X1 :: duplex_status [02:02] */
 #define XGXSBLK4_STATUS1000X1_DUPLEX_STATUS_MASK                   0x0004
 #define XGXSBLK4_STATUS1000X1_DUPLEX_STATUS_ALIGN                  0
 #define XGXSBLK4_STATUS1000X1_DUPLEX_STATUS_BITS                   1
 #define XGXSBLK4_STATUS1000X1_DUPLEX_STATUS_SHIFT                  2
 
 /* XgxsBlk4 :: Status1000X1 :: link_status [01:01] */
 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_MASK                     0x0002
 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_ALIGN                    0
 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_BITS                     1
 #define XGXSBLK4_STATUS1000X1_LINK_STATUS_SHIFT                    1
 
 /* XgxsBlk4 :: Status1000X1 :: sgmii_mode [00:00] */
 #define XGXSBLK4_STATUS1000X1_SGMII_MODE_MASK                      0x0001
 #define XGXSBLK4_STATUS1000X1_SGMII_MODE_ALIGN                     0
 #define XGXSBLK4_STATUS1000X1_SGMII_MODE_BITS                      1
 #define XGXSBLK4_STATUS1000X1_SGMII_MODE_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk4 :: Status1000X2
  */
 /* XgxsBlk4 :: Status1000X2 :: sgmii_mode_change [15:15] */
 #define XGXSBLK4_STATUS1000X2_SGMII_MODE_CHANGE_MASK               0x8000
 #define XGXSBLK4_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN              0
 #define XGXSBLK4_STATUS1000X2_SGMII_MODE_CHANGE_BITS               1
 #define XGXSBLK4_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT              15
 
 /* XgxsBlk4 :: Status1000X2 :: consistency_mismatch [14:14] */
 #define XGXSBLK4_STATUS1000X2_CONSISTENCY_MISMATCH_MASK            0x4000
 #define XGXSBLK4_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN           0
 #define XGXSBLK4_STATUS1000X2_CONSISTENCY_MISMATCH_BITS            1
 #define XGXSBLK4_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT           14
 
 /* XgxsBlk4 :: Status1000X2 :: autoneg_resolution_err [13:13] */
 #define XGXSBLK4_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK          0x2000
 #define XGXSBLK4_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN         0
 #define XGXSBLK4_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS          1
 #define XGXSBLK4_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT         13
 
 /* XgxsBlk4 :: Status1000X2 :: sgmii_selector_mismatch [12:12] */
 #define XGXSBLK4_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK         0x1000
 #define XGXSBLK4_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN        0
 #define XGXSBLK4_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS         1
 #define XGXSBLK4_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT        12
 
 /* XgxsBlk4 :: Status1000X2 :: sync_status_fail [11:11] */
 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_FAIL_MASK                0x0800
 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN               0
 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_FAIL_BITS                1
 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT               11
 
 /* XgxsBlk4 :: Status1000X2 :: sync_status_ok [10:10] */
 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_OK_MASK                  0x0400
 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_OK_ALIGN                 0
 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_OK_BITS                  1
 #define XGXSBLK4_STATUS1000X2_SYNC_STATUS_OK_SHIFT                 10
 
 /* XgxsBlk4 :: Status1000X2 :: rudi_c [09:09] */
 #define XGXSBLK4_STATUS1000X2_RUDI_C_MASK                          0x0200
 #define XGXSBLK4_STATUS1000X2_RUDI_C_ALIGN                         0
 #define XGXSBLK4_STATUS1000X2_RUDI_C_BITS                          1
 #define XGXSBLK4_STATUS1000X2_RUDI_C_SHIFT                         9
 
 /* XgxsBlk4 :: Status1000X2 :: rudi_I [08:08] */
 #define XGXSBLK4_STATUS1000X2_RUDI_I_MASK                          0x0100
 #define XGXSBLK4_STATUS1000X2_RUDI_I_ALIGN                         0
 #define XGXSBLK4_STATUS1000X2_RUDI_I_BITS                          1
 #define XGXSBLK4_STATUS1000X2_RUDI_I_SHIFT                         8
 
 /* XgxsBlk4 :: Status1000X2 :: rudi_invalid [07:07] */
 #define XGXSBLK4_STATUS1000X2_RUDI_INVALID_MASK                    0x0080
 #define XGXSBLK4_STATUS1000X2_RUDI_INVALID_ALIGN                   0
 #define XGXSBLK4_STATUS1000X2_RUDI_INVALID_BITS                    1
 #define XGXSBLK4_STATUS1000X2_RUDI_INVALID_SHIFT                   7
 
 /* XgxsBlk4 :: Status1000X2 :: linkDown_syncLoss [06:06] */
 #define XGXSBLK4_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK               0x0040
 #define XGXSBLK4_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN              0
 #define XGXSBLK4_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS               1
 #define XGXSBLK4_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT              6
 
 /* XgxsBlk4 :: Status1000X2 :: idle_detect_state [05:05] */
 #define XGXSBLK4_STATUS1000X2_IDLE_DETECT_STATE_MASK               0x0020
 #define XGXSBLK4_STATUS1000X2_IDLE_DETECT_STATE_ALIGN              0
 #define XGXSBLK4_STATUS1000X2_IDLE_DETECT_STATE_BITS               1
 #define XGXSBLK4_STATUS1000X2_IDLE_DETECT_STATE_SHIFT              5
 
 /* XgxsBlk4 :: Status1000X2 :: complete_acknowledge_state [04:04] */
 #define XGXSBLK4_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK      0x0010
 #define XGXSBLK4_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN     0
 #define XGXSBLK4_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS      1
 #define XGXSBLK4_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT     4
 
 /* XgxsBlk4 :: Status1000X2 :: acknowledge_detect_state [03:03] */
 #define XGXSBLK4_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK        0x0008
 #define XGXSBLK4_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN       0
 #define XGXSBLK4_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS        1
 #define XGXSBLK4_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT       3
 
 /* XgxsBlk4 :: Status1000X2 :: ability_detect_state [02:02] */
 #define XGXSBLK4_STATUS1000X2_ABILITY_DETECT_STATE_MASK            0x0004
 #define XGXSBLK4_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN           0
 #define XGXSBLK4_STATUS1000X2_ABILITY_DETECT_STATE_BITS            1
 #define XGXSBLK4_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT           2
 
 /* union - case anError [01:01] */
 /* XgxsBlk4 :: Status1000X2 :: an_error_state [01:01] */
 #define XGXSBLK4_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK          0x0002
 #define XGXSBLK4_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN         0
 #define XGXSBLK4_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS          1
 #define XGXSBLK4_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT         1
 
 
 /* union - case anDisableLink [01:01] */
 /* XgxsBlk4 :: Status1000X2 :: an_disable_link_ok_state [01:01] */
 #define XGXSBLK4_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002
 #define XGXSBLK4_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0
 #define XGXSBLK4_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1
 #define XGXSBLK4_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1
 
 
 /* XgxsBlk4 :: Status1000X2 :: an_enable_state [00:00] */
 #define XGXSBLK4_STATUS1000X2_AN_ENABLE_STATE_MASK                 0x0001
 #define XGXSBLK4_STATUS1000X2_AN_ENABLE_STATE_ALIGN                0
 #define XGXSBLK4_STATUS1000X2_AN_ENABLE_STATE_BITS                 1
 #define XGXSBLK4_STATUS1000X2_AN_ENABLE_STATE_SHIFT                0
 
 
 /****************************************************************************
  * XgxsBlk4 :: Status1000X3
  */
 /* XgxsBlk4 :: Status1000X3 :: reserved0 [15:13] */
 #define XGXSBLK4_STATUS1000X3_RESERVED0_MASK                       0xe000
 #define XGXSBLK4_STATUS1000X3_RESERVED0_ALIGN                      0
 #define XGXSBLK4_STATUS1000X3_RESERVED0_BITS                       3
 #define XGXSBLK4_STATUS1000X3_RESERVED0_SHIFT                      13
 
 /* XgxsBlk4 :: Status1000X3 :: pd_park_an [12:12] */
 #define XGXSBLK4_STATUS1000X3_PD_PARK_AN_MASK                      0x1000
 #define XGXSBLK4_STATUS1000X3_PD_PARK_AN_ALIGN                     0
 #define XGXSBLK4_STATUS1000X3_PD_PARK_AN_BITS                      1
 #define XGXSBLK4_STATUS1000X3_PD_PARK_AN_SHIFT                     12
 
 /* XgxsBlk4 :: Status1000X3 :: remotePhy_autosel [11:11] */
 #define XGXSBLK4_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK               0x0800
 #define XGXSBLK4_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN              0
 #define XGXSBLK4_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS               1
 #define XGXSBLK4_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT              11
 
 /* XgxsBlk4 :: Status1000X3 :: latch_linkdown [10:10] */
 #define XGXSBLK4_STATUS1000X3_LATCH_LINKDOWN_MASK                  0x0400
 #define XGXSBLK4_STATUS1000X3_LATCH_LINKDOWN_ALIGN                 0
 #define XGXSBLK4_STATUS1000X3_LATCH_LINKDOWN_BITS                  1
 #define XGXSBLK4_STATUS1000X3_LATCH_LINKDOWN_SHIFT                 10
 
 /* XgxsBlk4 :: Status1000X3 :: sd_filter [09:09] */
 #define XGXSBLK4_STATUS1000X3_SD_FILTER_MASK                       0x0200
 #define XGXSBLK4_STATUS1000X3_SD_FILTER_ALIGN                      0
 #define XGXSBLK4_STATUS1000X3_SD_FILTER_BITS                       1
 #define XGXSBLK4_STATUS1000X3_SD_FILTER_SHIFT                      9
 
 /* XgxsBlk4 :: Status1000X3 :: sd_mux [08:08] */
 #define XGXSBLK4_STATUS1000X3_SD_MUX_MASK                          0x0100
 #define XGXSBLK4_STATUS1000X3_SD_MUX_ALIGN                         0
 #define XGXSBLK4_STATUS1000X3_SD_MUX_BITS                          1
 #define XGXSBLK4_STATUS1000X3_SD_MUX_SHIFT                         8
 
 /* XgxsBlk4 :: Status1000X3 :: sd_filter_chg [07:07] */
 #define XGXSBLK4_STATUS1000X3_SD_FILTER_CHG_MASK                   0x0080
 #define XGXSBLK4_STATUS1000X3_SD_FILTER_CHG_ALIGN                  0
 #define XGXSBLK4_STATUS1000X3_SD_FILTER_CHG_BITS                   1
 #define XGXSBLK4_STATUS1000X3_SD_FILTER_CHG_SHIFT                  7
 
 /* XgxsBlk4 :: Status1000X3 :: reserved1 [06:00] */
 #define XGXSBLK4_STATUS1000X3_RESERVED1_MASK                       0x007f
 #define XGXSBLK4_STATUS1000X3_RESERVED1_ALIGN                      0
 #define XGXSBLK4_STATUS1000X3_RESERVED1_BITS                       7
 #define XGXSBLK4_STATUS1000X3_RESERVED1_SHIFT                      0
 
 
 /****************************************************************************
  * XgxsBlk4 :: TPOUT_1
  */
 /* XgxsBlk4 :: TPOUT_1 :: tpout1 [15:00] */
 #define XGXSBLK4_TPOUT_1_TPOUT1_MASK                               0xffff
 #define XGXSBLK4_TPOUT_1_TPOUT1_ALIGN                              0
 #define XGXSBLK4_TPOUT_1_TPOUT1_BITS                               16
 #define XGXSBLK4_TPOUT_1_TPOUT1_SHIFT                              0
 
 
 /****************************************************************************
  * XgxsBlk4 :: TPOUT_2
  */
 /* XgxsBlk4 :: TPOUT_2 :: tpout2 [15:00] */
 #define XGXSBLK4_TPOUT_2_TPOUT2_MASK                               0xffff
 #define XGXSBLK4_TPOUT_2_TPOUT2_ALIGN                              0
 #define XGXSBLK4_TPOUT_2_TPOUT2_BITS                               16
 #define XGXSBLK4_TPOUT_2_TPOUT2_SHIFT                              0
 
 
 /****************************************************************************
  * XgxsBlk4 :: xgxsStatus3
  */
 /* XgxsBlk4 :: xgxsStatus3 :: link [15:15] */
 #define XGXSBLK4_XGXSSTATUS3_LINK_MASK                             0x8000
 #define XGXSBLK4_XGXSSTATUS3_LINK_ALIGN                            0
 #define XGXSBLK4_XGXSSTATUS3_LINK_BITS                             1
 #define XGXSBLK4_XGXSSTATUS3_LINK_SHIFT                            15
 
 /* XgxsBlk4 :: xgxsStatus3 :: link_latchdown [14:14] */
 #define XGXSBLK4_XGXSSTATUS3_LINK_LATCHDOWN_MASK                   0x4000
 #define XGXSBLK4_XGXSSTATUS3_LINK_LATCHDOWN_ALIGN                  0
 #define XGXSBLK4_XGXSSTATUS3_LINK_LATCHDOWN_BITS                   1
 #define XGXSBLK4_XGXSSTATUS3_LINK_LATCHDOWN_SHIFT                  14
 
 /* XgxsBlk4 :: xgxsStatus3 :: latch_linkdown_10g_o [13:13] */
 #define XGXSBLK4_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_MASK             0x2000
 #define XGXSBLK4_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_ALIGN            0
 #define XGXSBLK4_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_BITS             1
 #define XGXSBLK4_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_SHIFT            13
 
 /* XgxsBlk4 :: xgxsStatus3 :: pd_park_an [12:12] */
 #define XGXSBLK4_XGXSSTATUS3_PD_PARK_AN_MASK                       0x1000
 #define XGXSBLK4_XGXSSTATUS3_PD_PARK_AN_ALIGN                      0
 #define XGXSBLK4_XGXSSTATUS3_PD_PARK_AN_BITS                       1
 #define XGXSBLK4_XGXSSTATUS3_PD_PARK_AN_SHIFT                      12
 
 /* XgxsBlk4 :: xgxsStatus3 :: gpwrdwn_pll [11:11] */
 #define XGXSBLK4_XGXSSTATUS3_GPWRDWN_PLL_MASK                      0x0800
 #define XGXSBLK4_XGXSSTATUS3_GPWRDWN_PLL_ALIGN                     0
 #define XGXSBLK4_XGXSSTATUS3_GPWRDWN_PLL_BITS                      1
 #define XGXSBLK4_XGXSSTATUS3_GPWRDWN_PLL_SHIFT                     11
 
 /* XgxsBlk4 :: xgxsStatus3 :: hcd_over_1g [10:00] */
 #define XGXSBLK4_XGXSSTATUS3_HCD_OVER_1G_MASK                      0x07ff
 #define XGXSBLK4_XGXSSTATUS3_HCD_OVER_1G_ALIGN                     0
 #define XGXSBLK4_XGXSSTATUS3_HCD_OVER_1G_BITS                      11
 #define XGXSBLK4_XGXSSTATUS3_HCD_OVER_1G_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk4 :: x2500Status1
  */
 /* XgxsBlk4 :: x2500Status1 :: hcd_over_1g_or [15:15] */
 #define XGXSBLK4_X2500STATUS1_HCD_OVER_1G_OR_MASK                  0x8000
 #define XGXSBLK4_X2500STATUS1_HCD_OVER_1G_OR_ALIGN                 0
 #define XGXSBLK4_X2500STATUS1_HCD_OVER_1G_OR_BITS                  1
 #define XGXSBLK4_X2500STATUS1_HCD_OVER_1G_OR_SHIFT                 15
 
 /* XgxsBlk4 :: x2500Status1 :: latch_hcd_over_1g [14:14] */
 #define XGXSBLK4_X2500STATUS1_LATCH_HCD_OVER_1G_MASK               0x4000
 #define XGXSBLK4_X2500STATUS1_LATCH_HCD_OVER_1G_ALIGN              0
 #define XGXSBLK4_X2500STATUS1_LATCH_HCD_OVER_1G_BITS               1
 #define XGXSBLK4_X2500STATUS1_LATCH_HCD_OVER_1G_SHIFT              14
 
 /* XgxsBlk4 :: x2500Status1 :: latchmdio [13:13] */
 #define XGXSBLK4_X2500STATUS1_LATCHMDIO_MASK                       0x2000
 #define XGXSBLK4_X2500STATUS1_LATCHMDIO_ALIGN                      0
 #define XGXSBLK4_X2500STATUS1_LATCHMDIO_BITS                       1
 #define XGXSBLK4_X2500STATUS1_LATCHMDIO_SHIFT                      13
 
 /* XgxsBlk4 :: x2500Status1 :: s_bc_reg_rst [12:12] */
 #define XGXSBLK4_X2500STATUS1_S_BC_REG_RST_MASK                    0x1000
 #define XGXSBLK4_X2500STATUS1_S_BC_REG_RST_ALIGN                   0
 #define XGXSBLK4_X2500STATUS1_S_BC_REG_RST_BITS                    1
 #define XGXSBLK4_X2500STATUS1_S_BC_REG_RST_SHIFT                   12
 
 /* XgxsBlk4 :: x2500Status1 :: s_wait2res [11:11] */
 #define XGXSBLK4_X2500STATUS1_S_WAIT2RES_MASK                      0x0800
 #define XGXSBLK4_X2500STATUS1_S_WAIT2RES_ALIGN                     0
 #define XGXSBLK4_X2500STATUS1_S_WAIT2RES_BITS                      1
 #define XGXSBLK4_X2500STATUS1_S_WAIT2RES_SHIFT                     11
 
 /* XgxsBlk4 :: x2500Status1 :: s_wait30ms [10:10] */
 #define XGXSBLK4_X2500STATUS1_S_WAIT30MS_MASK                      0x0400
 #define XGXSBLK4_X2500STATUS1_S_WAIT30MS_ALIGN                     0
 #define XGXSBLK4_X2500STATUS1_S_WAIT30MS_BITS                      1
 #define XGXSBLK4_X2500STATUS1_S_WAIT30MS_SHIFT                     10
 
 /* XgxsBlk4 :: x2500Status1 :: s_clockswit [09:09] */
 #define XGXSBLK4_X2500STATUS1_S_CLOCKSWIT_MASK                     0x0200
 #define XGXSBLK4_X2500STATUS1_S_CLOCKSWIT_ALIGN                    0
 #define XGXSBLK4_X2500STATUS1_S_CLOCKSWIT_BITS                     1
 #define XGXSBLK4_X2500STATUS1_S_CLOCKSWIT_SHIFT                    9
 
 /* XgxsBlk4 :: x2500Status1 :: s_pllswit [08:08] */
 #define XGXSBLK4_X2500STATUS1_S_PLLSWIT_MASK                       0x0100
 #define XGXSBLK4_X2500STATUS1_S_PLLSWIT_ALIGN                      0
 #define XGXSBLK4_X2500STATUS1_S_PLLSWIT_BITS                       1
 #define XGXSBLK4_X2500STATUS1_S_PLLSWIT_SHIFT                      8
 
 /* XgxsBlk4 :: x2500Status1 :: s_wait4link [07:07] */
 #define XGXSBLK4_X2500STATUS1_S_WAIT4LINK_MASK                     0x0080
 #define XGXSBLK4_X2500STATUS1_S_WAIT4LINK_ALIGN                    0
 #define XGXSBLK4_X2500STATUS1_S_WAIT4LINK_BITS                     1
 #define XGXSBLK4_X2500STATUS1_S_WAIT4LINK_SHIFT                    7
 
 /* XgxsBlk4 :: x2500Status1 :: s_complete [06:06] */
 #define XGXSBLK4_X2500STATUS1_S_COMPLETE_MASK                      0x0040
 #define XGXSBLK4_X2500STATUS1_S_COMPLETE_ALIGN                     0
 #define XGXSBLK4_X2500STATUS1_S_COMPLETE_BITS                      1
 #define XGXSBLK4_X2500STATUS1_S_COMPLETE_SHIFT                     6
 
 /* XgxsBlk4 :: x2500Status1 :: s_lostlink [05:05] */
 #define XGXSBLK4_X2500STATUS1_S_LOSTLINK_MASK                      0x0020
 #define XGXSBLK4_X2500STATUS1_S_LOSTLINK_ALIGN                     0
 #define XGXSBLK4_X2500STATUS1_S_LOSTLINK_BITS                      1
 #define XGXSBLK4_X2500STATUS1_S_LOSTLINK_SHIFT                     5
 
 /* XgxsBlk4 :: x2500Status1 :: s_dead [04:04] */
 #define XGXSBLK4_X2500STATUS1_S_DEAD_MASK                          0x0010
 #define XGXSBLK4_X2500STATUS1_S_DEAD_ALIGN                         0
 #define XGXSBLK4_X2500STATUS1_S_DEAD_BITS                          1
 #define XGXSBLK4_X2500STATUS1_S_DEAD_SHIFT                         4
 
 /* XgxsBlk4 :: x2500Status1 :: fail_cnt [03:00] */
 #define XGXSBLK4_X2500STATUS1_FAIL_CNT_MASK                        0x000f
 #define XGXSBLK4_X2500STATUS1_FAIL_CNT_ALIGN                       0
 #define XGXSBLK4_X2500STATUS1_FAIL_CNT_BITS                        4
 #define XGXSBLK4_X2500STATUS1_FAIL_CNT_SHIFT                       0
 
 
 /****************************************************************************
  * XgxsBlk4 :: topANStatus1
  */
 /* XgxsBlk4 :: topANStatus1 :: reserved0 [15:14] */
 #define XGXSBLK4_TOPANSTATUS1_RESERVED0_MASK                       0xc000
 #define XGXSBLK4_TOPANSTATUS1_RESERVED0_ALIGN                      0
 #define XGXSBLK4_TOPANSTATUS1_RESERVED0_BITS                       2
 #define XGXSBLK4_TOPANSTATUS1_RESERVED0_SHIFT                      14
 
 /* XgxsBlk4 :: topANStatus1 :: actual_speed [13:08] */
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_MASK                    0x3f00
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_ALIGN                   0
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_BITS                    6
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_SHIFT                   8
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10M                  0
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_100M                 1
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_1G                   2
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_2p5G                 3
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_5G_X4                4
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_6G_X4                5
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_HiG              6
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_CX4              7
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_12G_HiG              8
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_12p5G_X4             9
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_13G_X4               10
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_15G_X4               11
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_16G_X4               12
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_1G_KX                13
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_KX4              14
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_KR               15
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_5G                   16
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_6p4G                 17
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_X4               18
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_21G_X4               19
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_25G_X4               20
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_HiG_DXGXS        21
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_DXGXS            22
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10p5G_HiG_DXGXS      23
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10p5G_DXGXS          24
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_12p773G_HiG_DXGXS    25
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_12p773G_DXGXS        26
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_XFI              27
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_40G                  28
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_HiG_DXGXS        29
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_DXGXS            30
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_SFI              31
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_31p5G                32
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_32p7G                33
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_SCR              34
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_HiG_DXGXS_SCR    35
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_DXGXS_SCR        36
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_12G_R2               37
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_X2               38
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_40G_KR4              39
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_40G_CR4              40
 #define XGXSBLK4_TOPANSTATUS1_ACTUAL_SPEED_dr_100G_CR10            41
 
 /* XgxsBlk4 :: topANStatus1 :: pause_resolution_rxside [07:07] */
 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_MASK         0x0080
 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_ALIGN        0
 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_BITS         1
 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_SHIFT        7
 
 /* XgxsBlk4 :: topANStatus1 :: pause_resolution_txside [06:06] */
 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_MASK         0x0040
 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_ALIGN        0
 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_BITS         1
 #define XGXSBLK4_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_SHIFT        6
 
 /* XgxsBlk4 :: topANStatus1 :: cl73_lp_np_BAM_able [05:05] */
 #define XGXSBLK4_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_MASK             0x0020
 #define XGXSBLK4_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_ALIGN            0
 #define XGXSBLK4_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_BITS             1
 #define XGXSBLK4_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_SHIFT            5
 
 /* XgxsBlk4 :: topANStatus1 :: cl73_mr_lp_autoneg_able [04:04] */
 #define XGXSBLK4_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_MASK         0x0010
 #define XGXSBLK4_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_ALIGN        0
 #define XGXSBLK4_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_BITS         1
 #define XGXSBLK4_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_SHIFT        4
 
 /* XgxsBlk4 :: topANStatus1 :: duplex_status [03:03] */
 #define XGXSBLK4_TOPANSTATUS1_DUPLEX_STATUS_MASK                   0x0008
 #define XGXSBLK4_TOPANSTATUS1_DUPLEX_STATUS_ALIGN                  0
 #define XGXSBLK4_TOPANSTATUS1_DUPLEX_STATUS_BITS                   1
 #define XGXSBLK4_TOPANSTATUS1_DUPLEX_STATUS_SHIFT                  3
 
 /* XgxsBlk4 :: topANStatus1 :: link_status [02:02] */
 #define XGXSBLK4_TOPANSTATUS1_LINK_STATUS_MASK                     0x0004
 #define XGXSBLK4_TOPANSTATUS1_LINK_STATUS_ALIGN                    0
 #define XGXSBLK4_TOPANSTATUS1_LINK_STATUS_BITS                     1
 #define XGXSBLK4_TOPANSTATUS1_LINK_STATUS_SHIFT                    2
 
 /* XgxsBlk4 :: topANStatus1 :: cl37_autoneg_complete [01:01] */
 #define XGXSBLK4_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_MASK           0x0002
 #define XGXSBLK4_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_ALIGN          0
 #define XGXSBLK4_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_BITS           1
 #define XGXSBLK4_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_SHIFT          1
 
 /* XgxsBlk4 :: topANStatus1 :: cl73_autoneg_complete [00:00] */
 #define XGXSBLK4_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_MASK           0x0001
 #define XGXSBLK4_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_ALIGN          0
 #define XGXSBLK4_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_BITS           1
 #define XGXSBLK4_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_SHIFT          0
 
 
 /****************************************************************************
  * XgxsBlk4 :: LP_UP1
  */
 /* XgxsBlk4 :: LP_UP1 :: reserved0 [15:11] */
 #define XGXSBLK4_LP_UP1_RESERVED0_MASK                             0xf800
 #define XGXSBLK4_LP_UP1_RESERVED0_ALIGN                            0
 #define XGXSBLK4_LP_UP1_RESERVED0_BITS                             5
 #define XGXSBLK4_LP_UP1_RESERVED0_SHIFT                            11
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_20GX4 [10:10] */
 #define XGXSBLK4_LP_UP1_DATARATE_20GX4_MASK                        0x0400
 #define XGXSBLK4_LP_UP1_DATARATE_20GX4_ALIGN                       0
 #define XGXSBLK4_LP_UP1_DATARATE_20GX4_BITS                        1
 #define XGXSBLK4_LP_UP1_DATARATE_20GX4_SHIFT                       10
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_16GX4 [09:09] */
 #define XGXSBLK4_LP_UP1_DATARATE_16GX4_MASK                        0x0200
 #define XGXSBLK4_LP_UP1_DATARATE_16GX4_ALIGN                       0
 #define XGXSBLK4_LP_UP1_DATARATE_16GX4_BITS                        1
 #define XGXSBLK4_LP_UP1_DATARATE_16GX4_SHIFT                       9
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_15GX4 [08:08] */
 #define XGXSBLK4_LP_UP1_DATARATE_15GX4_MASK                        0x0100
 #define XGXSBLK4_LP_UP1_DATARATE_15GX4_ALIGN                       0
 #define XGXSBLK4_LP_UP1_DATARATE_15GX4_BITS                        1
 #define XGXSBLK4_LP_UP1_DATARATE_15GX4_SHIFT                       8
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_13GX4 [07:07] */
 #define XGXSBLK4_LP_UP1_DATARATE_13GX4_MASK                        0x0080
 #define XGXSBLK4_LP_UP1_DATARATE_13GX4_ALIGN                       0
 #define XGXSBLK4_LP_UP1_DATARATE_13GX4_BITS                        1
 #define XGXSBLK4_LP_UP1_DATARATE_13GX4_SHIFT                       7
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_12p5GX4 [06:06] */
 #define XGXSBLK4_LP_UP1_DATARATE_12P5GX4_MASK                      0x0040
 #define XGXSBLK4_LP_UP1_DATARATE_12P5GX4_ALIGN                     0
 #define XGXSBLK4_LP_UP1_DATARATE_12P5GX4_BITS                      1
 #define XGXSBLK4_LP_UP1_DATARATE_12P5GX4_SHIFT                     6
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_12GX4 [05:05] */
 #define XGXSBLK4_LP_UP1_DATARATE_12GX4_MASK                        0x0020
 #define XGXSBLK4_LP_UP1_DATARATE_12GX4_ALIGN                       0
 #define XGXSBLK4_LP_UP1_DATARATE_12GX4_BITS                        1
 #define XGXSBLK4_LP_UP1_DATARATE_12GX4_SHIFT                       5
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_10GCX4 [04:04] */
 #define XGXSBLK4_LP_UP1_DATARATE_10GCX4_MASK                       0x0010
 #define XGXSBLK4_LP_UP1_DATARATE_10GCX4_ALIGN                      0
 #define XGXSBLK4_LP_UP1_DATARATE_10GCX4_BITS                       1
 #define XGXSBLK4_LP_UP1_DATARATE_10GCX4_SHIFT                      4
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_10GX4 [03:03] */
 #define XGXSBLK4_LP_UP1_DATARATE_10GX4_MASK                        0x0008
 #define XGXSBLK4_LP_UP1_DATARATE_10GX4_ALIGN                       0
 #define XGXSBLK4_LP_UP1_DATARATE_10GX4_BITS                        1
 #define XGXSBLK4_LP_UP1_DATARATE_10GX4_SHIFT                       3
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_6GX4 [02:02] */
 #define XGXSBLK4_LP_UP1_DATARATE_6GX4_MASK                         0x0004
 #define XGXSBLK4_LP_UP1_DATARATE_6GX4_ALIGN                        0
 #define XGXSBLK4_LP_UP1_DATARATE_6GX4_BITS                         1
 #define XGXSBLK4_LP_UP1_DATARATE_6GX4_SHIFT                        2
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_5GX4 [01:01] */
 #define XGXSBLK4_LP_UP1_DATARATE_5GX4_MASK                         0x0002
 #define XGXSBLK4_LP_UP1_DATARATE_5GX4_ALIGN                        0
 #define XGXSBLK4_LP_UP1_DATARATE_5GX4_BITS                         1
 #define XGXSBLK4_LP_UP1_DATARATE_5GX4_SHIFT                        1
 
 /* XgxsBlk4 :: LP_UP1 :: dataRate_2p5GX1 [00:00] */
 #define XGXSBLK4_LP_UP1_DATARATE_2P5GX1_MASK                       0x0001
 #define XGXSBLK4_LP_UP1_DATARATE_2P5GX1_ALIGN                      0
 #define XGXSBLK4_LP_UP1_DATARATE_2P5GX1_BITS                       1
 #define XGXSBLK4_LP_UP1_DATARATE_2P5GX1_SHIFT                      0
 
 
 /****************************************************************************
  * XgxsBlk4 :: LP_UP2
  */
 /* XgxsBlk4 :: LP_UP2 :: reserved0 [15:11] */
 #define XGXSBLK4_LP_UP2_RESERVED0_MASK                             0xf800
 #define XGXSBLK4_LP_UP2_RESERVED0_ALIGN                            0
 #define XGXSBLK4_LP_UP2_RESERVED0_BITS                             5
 #define XGXSBLK4_LP_UP2_RESERVED0_SHIFT                            11
 
 /* XgxsBlk4 :: LP_UP2 :: valid [10:10] */
 #define XGXSBLK4_LP_UP2_VALID_MASK                                 0x0400
 #define XGXSBLK4_LP_UP2_VALID_ALIGN                                0
 #define XGXSBLK4_LP_UP2_VALID_BITS                                 1
 #define XGXSBLK4_LP_UP2_VALID_SHIFT                                10
 
 /* XgxsBlk4 :: LP_UP2 :: preemphasis [09:06] */
 #define XGXSBLK4_LP_UP2_PREEMPHASIS_MASK                           0x03c0
 #define XGXSBLK4_LP_UP2_PREEMPHASIS_ALIGN                          0
 #define XGXSBLK4_LP_UP2_PREEMPHASIS_BITS                           4
 #define XGXSBLK4_LP_UP2_PREEMPHASIS_SHIFT                          6
 
 /* XgxsBlk4 :: LP_UP2 :: idriver [05:03] */
 #define XGXSBLK4_LP_UP2_IDRIVER_MASK                               0x0038
 #define XGXSBLK4_LP_UP2_IDRIVER_ALIGN                              0
 #define XGXSBLK4_LP_UP2_IDRIVER_BITS                               3
 #define XGXSBLK4_LP_UP2_IDRIVER_SHIFT                              3
 
 /* XgxsBlk4 :: LP_UP2 :: ipredriver [02:00] */
 #define XGXSBLK4_LP_UP2_IPREDRIVER_MASK                            0x0007
 #define XGXSBLK4_LP_UP2_IPREDRIVER_ALIGN                           0
 #define XGXSBLK4_LP_UP2_IPREDRIVER_BITS                            3
 #define XGXSBLK4_LP_UP2_IPREDRIVER_SHIFT                           0
 
 
 /****************************************************************************
  * XgxsBlk4 :: LP_UP3
  */
 /* XgxsBlk4 :: LP_UP3 :: reserved0 [15:11] */
 #define XGXSBLK4_LP_UP3_RESERVED0_MASK                             0xf800
 #define XGXSBLK4_LP_UP3_RESERVED0_ALIGN                            0
 #define XGXSBLK4_LP_UP3_RESERVED0_BITS                             5
 #define XGXSBLK4_LP_UP3_RESERVED0_SHIFT                            11
 
 /* XgxsBlk4 :: LP_UP3 :: last [10:10] */
 #define XGXSBLK4_LP_UP3_LAST_MASK                                  0x0400
 #define XGXSBLK4_LP_UP3_LAST_ALIGN                                 0
 #define XGXSBLK4_LP_UP3_LAST_BITS                                  1
 #define XGXSBLK4_LP_UP3_LAST_SHIFT                                 10
 
 /* XgxsBlk4 :: LP_UP3 :: dataRate_21GX4 [09:09] */
 #define XGXSBLK4_LP_UP3_DATARATE_21GX4_MASK                        0x0200
 #define XGXSBLK4_LP_UP3_DATARATE_21GX4_ALIGN                       0
 #define XGXSBLK4_LP_UP3_DATARATE_21GX4_BITS                        1
 #define XGXSBLK4_LP_UP3_DATARATE_21GX4_SHIFT                       9
 
 /* XgxsBlk4 :: LP_UP3 :: dataRate_25p45GX4 [08:08] */
 #define XGXSBLK4_LP_UP3_DATARATE_25P45GX4_MASK                     0x0100
 #define XGXSBLK4_LP_UP3_DATARATE_25P45GX4_ALIGN                    0
 #define XGXSBLK4_LP_UP3_DATARATE_25P45GX4_BITS                     1
 #define XGXSBLK4_LP_UP3_DATARATE_25P45GX4_SHIFT                    8
 
 /* XgxsBlk4 :: LP_UP3 :: reserved1 [07:02] */
 #define XGXSBLK4_LP_UP3_RESERVED1_MASK                             0x00fc
 #define XGXSBLK4_LP_UP3_RESERVED1_ALIGN                            0
 #define XGXSBLK4_LP_UP3_RESERVED1_BITS                             6
 #define XGXSBLK4_LP_UP3_RESERVED1_SHIFT                            2
 
 /* XgxsBlk4 :: LP_UP3 :: scramble_8B10B [01:01] */
 #define XGXSBLK4_LP_UP3_SCRAMBLE_8B10B_MASK                        0x0002
 #define XGXSBLK4_LP_UP3_SCRAMBLE_8B10B_ALIGN                       0
 #define XGXSBLK4_LP_UP3_SCRAMBLE_8B10B_BITS                        1
 #define XGXSBLK4_LP_UP3_SCRAMBLE_8B10B_SHIFT                       1
 
 /* XgxsBlk4 :: LP_UP3 :: HiGig2 [00:00] */
 #define XGXSBLK4_LP_UP3_HIGIG2_MASK                                0x0001
 #define XGXSBLK4_LP_UP3_HIGIG2_ALIGN                               0
 #define XGXSBLK4_LP_UP3_HIGIG2_BITS                                1
 #define XGXSBLK4_LP_UP3_HIGIG2_SHIFT                               0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk5
  */
 /****************************************************************************
  * XgxsBlk5 :: parDet10GStatus
  */
 /* union - case pdStatus0 [15:00] */
 /* XgxsBlk5 :: parDet10GStatus :: pd_link [15:15] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LINK_MASK            0x8000
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LINK_ALIGN           0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LINK_BITS            1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LINK_SHIFT           15
 
 /* XgxsBlk5 :: parDet10GStatus :: pd_CX4_en [14:14] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_MASK          0x4000
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_ALIGN         0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_BITS          1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_SHIFT         14
 
 /* XgxsBlk5 :: parDet10GStatus :: pd_lssFaultCount_en [13:13] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_MASK 0x2000
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_ALIGN 0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_BITS 1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_SHIFT 13
 
 /* XgxsBlk5 :: parDet10GStatus :: pd_tunePll12g [12:12] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_MASK      0x1000
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_ALIGN     0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_BITS      1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_SHIFT     12
 
 /* XgxsBlk5 :: parDet10GStatus :: pd_tunePll10g [11:11] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_MASK      0x0800
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_ALIGN     0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_BITS      1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_SHIFT     11
 
 /* XgxsBlk5 :: parDet10GStatus :: pd_txdLaneOff [10:10] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_MASK      0x0400
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_ALIGN     0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_BITS      1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_SHIFT     10
 
 /* XgxsBlk5 :: parDet10GStatus :: pd_busy [09:09] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_MASK            0x0200
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_ALIGN           0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_BITS            1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_SHIFT           9
 
 /* XgxsBlk5 :: parDet10GStatus :: pd_park_an [08:08] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_MASK         0x0100
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_ALIGN        0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_BITS         1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_SHIFT        8
 
 /* XgxsBlk5 :: parDet10GStatus :: pd_lssFaultCount [07:04] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_MASK   0x00f0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_ALIGN  0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_BITS   4
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_SHIFT  4
 
 /* XgxsBlk5 :: parDet10GStatus :: rxSeqDone [03:00] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_MASK          0x000f
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_ALIGN         0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_BITS          4
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_SHIFT         0
 
 
 /* union - case pdStatus1 [15:00] */
 /* XgxsBlk5 :: parDet10GStatus :: reserved0 [15:09] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_RESERVED0_MASK          0xfe00
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_RESERVED0_ALIGN         0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_RESERVED0_BITS          7
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_RESERVED0_SHIFT         9
 
 /* XgxsBlk5 :: parDet10GStatus :: fail_lh [08:08] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_MASK            0x0100
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_ALIGN           0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_BITS            1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_SHIFT           8
 
 /* XgxsBlk5 :: parDet10GStatus :: complete_lh [07:07] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_MASK        0x0080
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_ALIGN       0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_BITS        1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_SHIFT       7
 
 /* XgxsBlk5 :: parDet10GStatus :: link12gretry_lh [06:06] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_MASK    0x0040
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_ALIGN   0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_BITS    1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_SHIFT   6
 
 /* XgxsBlk5 :: parDet10GStatus :: wait4link12g_lh [05:05] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_MASK    0x0020
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_ALIGN   0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_BITS    1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_SHIFT   5
 
 /* XgxsBlk5 :: parDet10GStatus :: samplefault_lh [04:04] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_MASK     0x0010
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_ALIGN    0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_BITS     1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_SHIFT    4
 
 /* XgxsBlk5 :: parDet10GStatus :: link10gretry_lh [03:03] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_MASK    0x0008
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_ALIGN   0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_BITS    1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_SHIFT   3
 
 /* XgxsBlk5 :: parDet10GStatus :: wait4link10g_lh [02:02] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_MASK    0x0004
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_ALIGN   0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_BITS    1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_SHIFT   2
 
 /* XgxsBlk5 :: parDet10GStatus :: wait4sigdet_lh [01:01] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_MASK     0x0002
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_ALIGN    0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_BITS     1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_SHIFT    1
 
 /* XgxsBlk5 :: parDet10GStatus :: wait4lock_lh [00:00] */
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_MASK       0x0001
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_ALIGN      0
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_BITS       1
 #define XGXSBLK5_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_SHIFT      0
 
 
 
 /****************************************************************************
  * XgxsBlk5 :: parDet10GControl
  */
 /* XgxsBlk5 :: parDet10GControl :: force_parDet10g_en [15:15] */
 #define XGXSBLK5_PARDET10GCONTROL_FORCE_PARDET10G_EN_MASK          0x8000
 #define XGXSBLK5_PARDET10GCONTROL_FORCE_PARDET10G_EN_ALIGN         0
 #define XGXSBLK5_PARDET10GCONTROL_FORCE_PARDET10G_EN_BITS          1
 #define XGXSBLK5_PARDET10GCONTROL_FORCE_PARDET10G_EN_SHIFT         15
 
 /* XgxsBlk5 :: parDet10GControl :: pd_cx4_init [14:14] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_CX4_INIT_MASK                 0x4000
 #define XGXSBLK5_PARDET10GCONTROL_PD_CX4_INIT_ALIGN                0
 #define XGXSBLK5_PARDET10GCONTROL_PD_CX4_INIT_BITS                 1
 #define XGXSBLK5_PARDET10GCONTROL_PD_CX4_INIT_SHIFT                14
 
 /* XgxsBlk5 :: parDet10GControl :: pd_sw_overide [13:13] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_OVERIDE_MASK               0x2000
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_OVERIDE_ALIGN              0
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_OVERIDE_BITS               1
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_OVERIDE_SHIFT              13
 
 /* XgxsBlk5 :: parDet10GControl :: pd_sw_busy_an [12:12] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_BUSY_AN_MASK               0x1000
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_BUSY_AN_ALIGN              0
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_BUSY_AN_BITS               1
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_BUSY_AN_SHIFT              12
 
 /* XgxsBlk5 :: parDet10GControl :: pd_sw_CX4_en [11:11] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_CX4_EN_MASK                0x0800
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_CX4_EN_ALIGN               0
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_CX4_EN_BITS                1
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_CX4_EN_SHIFT               11
 
 /* XgxsBlk5 :: parDet10GControl :: pd_sw_tunePll12g [10:10] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL12G_MASK            0x0400
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL12G_ALIGN           0
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL12G_BITS            1
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL12G_SHIFT           10
 
 /* XgxsBlk5 :: parDet10GControl :: pd_sw_tunePll10g [09:09] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL10G_MASK            0x0200
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL10G_ALIGN           0
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL10G_BITS            1
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TUNEPLL10G_SHIFT           9
 
 /* XgxsBlk5 :: parDet10GControl :: pd_sw_lssFaultCount_en [08:08] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_MASK      0x0100
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_ALIGN     0
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_BITS      1
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_SHIFT     8
 
 /* XgxsBlk5 :: parDet10GControl :: pd_sw_txdOff [07:07] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TXDOFF_MASK                0x0080
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TXDOFF_ALIGN               0
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TXDOFF_BITS                1
 #define XGXSBLK5_PARDET10GCONTROL_PD_SW_TXDOFF_SHIFT               7
 
 /* XgxsBlk5 :: parDet10GControl :: pd_12g_txdOn_disable [06:06] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_MASK        0x0040
 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_ALIGN       0
 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_BITS        1
 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_SHIFT       6
 
 /* XgxsBlk5 :: parDet10GControl :: pd_12g_disable [05:05] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_DISABLE_MASK              0x0020
 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_DISABLE_ALIGN             0
 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_DISABLE_BITS              1
 #define XGXSBLK5_PARDET10GCONTROL_PD_12G_DISABLE_SHIFT             5
 
 /* XgxsBlk5 :: parDet10GControl :: pd_10g_txdOn_disable [04:04] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_MASK        0x0010
 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_ALIGN       0
 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_BITS        1
 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_SHIFT       4
 
 /* XgxsBlk5 :: parDet10GControl :: pd_10g_disable [03:03] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_DISABLE_MASK              0x0008
 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_DISABLE_ALIGN             0
 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_DISABLE_BITS              1
 #define XGXSBLK5_PARDET10GCONTROL_PD_10G_DISABLE_SHIFT             3
 
 /* XgxsBlk5 :: parDet10GControl :: pd_stat_sel [02:02] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_STAT_SEL_MASK                 0x0004
 #define XGXSBLK5_PARDET10GCONTROL_PD_STAT_SEL_ALIGN                0
 #define XGXSBLK5_PARDET10GCONTROL_PD_STAT_SEL_BITS                 1
 #define XGXSBLK5_PARDET10GCONTROL_PD_STAT_SEL_SHIFT                2
 
 /* XgxsBlk5 :: parDet10GControl :: pd_fast_timer_en [01:01] */
 #define XGXSBLK5_PARDET10GCONTROL_PD_FAST_TIMER_EN_MASK            0x0002
 #define XGXSBLK5_PARDET10GCONTROL_PD_FAST_TIMER_EN_ALIGN           0
 #define XGXSBLK5_PARDET10GCONTROL_PD_FAST_TIMER_EN_BITS            1
 #define XGXSBLK5_PARDET10GCONTROL_PD_FAST_TIMER_EN_SHIFT           1
 
 /* XgxsBlk5 :: parDet10GControl :: parDet10g_en [00:00] */
 #define XGXSBLK5_PARDET10GCONTROL_PARDET10G_EN_MASK                0x0001
 #define XGXSBLK5_PARDET10GCONTROL_PARDET10G_EN_ALIGN               0
 #define XGXSBLK5_PARDET10GCONTROL_PARDET10G_EN_BITS                1
 #define XGXSBLK5_PARDET10GCONTROL_PARDET10G_EN_SHIFT               0
 
 
 /****************************************************************************
  * XgxsBlk5 :: parDet10GSigDet
  */
 /* XgxsBlk5 :: parDet10GSigDet :: pd_sd_count [15:00] */
 #define XGXSBLK5_PARDET10GSIGDET_PD_SD_COUNT_MASK                  0xffff
 #define XGXSBLK5_PARDET10GSIGDET_PD_SD_COUNT_ALIGN                 0
 #define XGXSBLK5_PARDET10GSIGDET_PD_SD_COUNT_BITS                  16
 #define XGXSBLK5_PARDET10GSIGDET_PD_SD_COUNT_SHIFT                 0
 
 
 /****************************************************************************
  * XgxsBlk5 :: parDet10GLink
  */
 /* XgxsBlk5 :: parDet10GLink :: pd_link_count [15:00] */
 #define XGXSBLK5_PARDET10GLINK_PD_LINK_COUNT_MASK                  0xffff
 #define XGXSBLK5_PARDET10GLINK_PD_LINK_COUNT_ALIGN                 0
 #define XGXSBLK5_PARDET10GLINK_PD_LINK_COUNT_BITS                  16
 #define XGXSBLK5_PARDET10GLINK_PD_LINK_COUNT_SHIFT                 0
 
 
 /****************************************************************************
  * XgxsBlk5 :: parDet10GLostLink
  */
 /* XgxsBlk5 :: parDet10GLostLink :: pd_lostlink_count [15:00] */
 #define XGXSBLK5_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_MASK          0xffff
 #define XGXSBLK5_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_ALIGN         0
 #define XGXSBLK5_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_BITS          16
 #define XGXSBLK5_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_SHIFT         0
 
 
 /****************************************************************************
  * XgxsBlk5 :: cl73Control1
  */
 /* XgxsBlk5 :: cl73Control1 :: reserved0 [15:08] */
 #define XGXSBLK5_CL73CONTROL1_RESERVED0_MASK                       0xff00
 #define XGXSBLK5_CL73CONTROL1_RESERVED0_ALIGN                      0
 #define XGXSBLK5_CL73CONTROL1_RESERVED0_BITS                       8
 #define XGXSBLK5_CL73CONTROL1_RESERVED0_SHIFT                      8
 
 /* XgxsBlk5 :: cl73Control1 :: cl73_internal_10us_timer_val [07:00] */
 #define XGXSBLK5_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_MASK    0x00ff
 #define XGXSBLK5_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_ALIGN   0
 #define XGXSBLK5_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_BITS    8
 #define XGXSBLK5_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_SHIFT   0
 
 
 /****************************************************************************
  * XgxsBlk5 :: cl73Control2
  */
 /* XgxsBlk5 :: cl73Control2 :: reserved0 [15:13] */
 #define XGXSBLK5_CL73CONTROL2_RESERVED0_MASK                       0xe000
 #define XGXSBLK5_CL73CONTROL2_RESERVED0_ALIGN                      0
 #define XGXSBLK5_CL73CONTROL2_RESERVED0_BITS                       3
 #define XGXSBLK5_CL73CONTROL2_RESERVED0_SHIFT                      13
 
 /* XgxsBlk5 :: cl73Control2 :: cl73_link_fail_inhibit_timer_val [12:00] */
 #define XGXSBLK5_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_MASK 0x1fff
 #define XGXSBLK5_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_ALIGN 0
 #define XGXSBLK5_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_BITS 13
 #define XGXSBLK5_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_SHIFT 0
 
 
 /****************************************************************************
  * XgxsBlk5 :: cl73Control3
  */
 /* XgxsBlk5 :: cl73Control3 :: reserved0 [15:13] */
 #define XGXSBLK5_CL73CONTROL3_RESERVED0_MASK                       0xe000
 #define XGXSBLK5_CL73CONTROL3_RESERVED0_ALIGN                      0
 #define XGXSBLK5_CL73CONTROL3_RESERVED0_BITS                       3
 #define XGXSBLK5_CL73CONTROL3_RESERVED0_SHIFT                      13
 
 /* XgxsBlk5 :: cl73Control3 :: cl73_an_wait_timer_val [12:00] */
 #define XGXSBLK5_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_MASK          0x1fff
 #define XGXSBLK5_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_ALIGN         0
 #define XGXSBLK5_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_BITS          13
 #define XGXSBLK5_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_SHIFT         0
 
 
 /****************************************************************************
  * XgxsBlk5 :: cl73Control4
  */
 /* XgxsBlk5 :: cl73Control4 :: reserved0 [15:13] */
 #define XGXSBLK5_CL73CONTROL4_RESERVED0_MASK                       0xe000
 #define XGXSBLK5_CL73CONTROL4_RESERVED0_ALIGN                      0
 #define XGXSBLK5_CL73CONTROL4_RESERVED0_BITS                       3
 #define XGXSBLK5_CL73CONTROL4_RESERVED0_SHIFT                      13
 
 /* XgxsBlk5 :: cl73Control4 :: cl73_break_link_timer_val [12:00] */
 #define XGXSBLK5_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_MASK       0x1fff
 #define XGXSBLK5_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_ALIGN      0
 #define XGXSBLK5_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_BITS       13
 #define XGXSBLK5_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_SHIFT      0
 
 
 /****************************************************************************
  * XgxsBlk5 :: cl73Control5
  */
 /* XgxsBlk5 :: cl73Control5 :: reserved0 [15:13] */
 #define XGXSBLK5_CL73CONTROL5_RESERVED0_MASK                       0xe000
 #define XGXSBLK5_CL73CONTROL5_RESERVED0_ALIGN                      0
 #define XGXSBLK5_CL73CONTROL5_RESERVED0_BITS                       3
 #define XGXSBLK5_CL73CONTROL5_RESERVED0_SHIFT                      13
 
 /* XgxsBlk5 :: cl73Control5 :: cl73_link_fail_inhibit_timer_bam_val [12:00] */
 #define XGXSBLK5_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_MASK 0x1fff
 #define XGXSBLK5_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_ALIGN 0
 #define XGXSBLK5_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_BITS 13
 #define XGXSBLK5_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_SHIFT 0
 
 
 /****************************************************************************
  * XgxsBlk5 :: cl73Control6
  */
 /* XgxsBlk5 :: cl73Control6 :: reserved0 [15:13] */
 #define XGXSBLK5_CL73CONTROL6_RESERVED0_MASK                       0xe000
 #define XGXSBLK5_CL73CONTROL6_RESERVED0_ALIGN                      0
 #define XGXSBLK5_CL73CONTROL6_RESERVED0_BITS                       3
 #define XGXSBLK5_CL73CONTROL6_RESERVED0_SHIFT                      13
 
 /* XgxsBlk5 :: cl73Control6 :: cl73_ignore_link_timer_val [12:00] */
 #define XGXSBLK5_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_MASK      0x1fff
 #define XGXSBLK5_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_ALIGN     0
 #define XGXSBLK5_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_BITS      13
 #define XGXSBLK5_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_SHIFT     0
 
 
 /****************************************************************************
  * XgxsBlk5 :: cl73DmeTmrs
  */
 /* XgxsBlk5 :: cl73DmeTmrs :: cl73_dme_page_test_max_cnt_val [15:08] */
 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_MASK   0xff00
 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_ALIGN  0
 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_BITS   8
 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_SHIFT  8
 
 /* XgxsBlk5 :: cl73DmeTmrs :: cl73_dme_page_test_min_cnt_val [07:00] */
 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_MASK   0x00ff
 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_ALIGN  0
 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_BITS   8
 #define XGXSBLK5_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_SHIFT  0
 
 
 /****************************************************************************
  * XgxsBlk5 :: xgxsStatus4
  */
 /* XgxsBlk5 :: xgxsStatus4 :: reserved0 [15:15] */
 #define XGXSBLK5_XGXSSTATUS4_RESERVED0_MASK                        0x8000
 #define XGXSBLK5_XGXSSTATUS4_RESERVED0_ALIGN                       0
 #define XGXSBLK5_XGXSSTATUS4_RESERVED0_BITS                        1
 #define XGXSBLK5_XGXSSTATUS4_RESERVED0_SHIFT                       15
 
 /* XgxsBlk5 :: xgxsStatus4 :: sgmii_mode [14:14] */
 #define XGXSBLK5_XGXSSTATUS4_SGMII_MODE_MASK                       0x4000
 #define XGXSBLK5_XGXSSTATUS4_SGMII_MODE_ALIGN                      0
 #define XGXSBLK5_XGXSSTATUS4_SGMII_MODE_BITS                       1
 #define XGXSBLK5_XGXSSTATUS4_SGMII_MODE_SHIFT                      14
 
 /* XgxsBlk5 :: xgxsStatus4 :: link10g [13:13] */
 #define XGXSBLK5_XGXSSTATUS4_LINK10G_MASK                          0x2000
 #define XGXSBLK5_XGXSSTATUS4_LINK10G_ALIGN                         0
 #define XGXSBLK5_XGXSSTATUS4_LINK10G_BITS                          1
 #define XGXSBLK5_XGXSSTATUS4_LINK10G_SHIFT                         13
 
 /* XgxsBlk5 :: xgxsStatus4 :: link_status [12:12] */
 #define XGXSBLK5_XGXSSTATUS4_LINK_STATUS_MASK                      0x1000
 #define XGXSBLK5_XGXSSTATUS4_LINK_STATUS_ALIGN                     0
 #define XGXSBLK5_XGXSSTATUS4_LINK_STATUS_BITS                      1
 #define XGXSBLK5_XGXSSTATUS4_LINK_STATUS_SHIFT                     12
 
 /* XgxsBlk5 :: xgxsStatus4 :: pll_mode_afe [11:08] */
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_MASK                     0x0f00
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_ALIGN                    0
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_BITS                     4
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_SHIFT                    8
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div32                    0
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div36                    1
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div40                    2
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div42                    3
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div48                    4
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div50                    5
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div52                    6
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div54                    7
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div60                    8
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div64                    9
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div66                    10
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div68                    11
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div80                    12
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div120                   13
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div200                   14
 #define XGXSBLK5_XGXSSTATUS4_PLL_MODE_AFE_div240                   15
 
 /* XgxsBlk5 :: xgxsStatus4 :: reserved1 [07:06] */
 #define XGXSBLK5_XGXSSTATUS4_RESERVED1_MASK                        0x00c0
 #define XGXSBLK5_XGXSSTATUS4_RESERVED1_ALIGN                       0
 #define XGXSBLK5_XGXSSTATUS4_RESERVED1_BITS                        2
 #define XGXSBLK5_XGXSSTATUS4_RESERVED1_SHIFT                       6
 
 /* XgxsBlk5 :: xgxsStatus4 :: actual_speed_ln0 [05:00] */
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_MASK                 0x003f
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_ALIGN                0
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_BITS                 6
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_SHIFT                0
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10M               0
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_100M              1
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_1G                2
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_2p5G              3
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G_X4             4
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_6G_X4             5
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_HiG           6
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_CX4           7
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12G_HiG           8
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p5G_X4          9
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_13G_X4            10
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_15G_X4            11
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_16G_X4            12
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_1G_KX             13
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_KX4           14
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_KR            15
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G                16
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_6p4G              17
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_X4            18
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_21G_X4            19
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_25G_X4            20
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_HiG_DXGXS     21
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_DXGXS         22
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10p5G_HiG_DXGXS   23
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10p5G_DXGXS       24
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p773G_HiG_DXGXS 25
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p773G_DXGXS     26
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_XFI           27
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_40G               28
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_HiG_DXGXS     29
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_DXGXS         30
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_SFI           31
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_31p5G             32
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_32p7G             33
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_SCR           34
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_HiG_DXGXS_SCR 35
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_DXGXS_SCR     36
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12G_R2            37
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_X2            38
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_40G_KR4           39
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_40G_CR4           40
 #define XGXSBLK5_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_100G_CR10         41
 
 
 /****************************************************************************
  * XgxsBlk5 :: xgxsStatus5
  */
 /* XgxsBlk5 :: xgxsStatus5 :: tx1g_mode_ln3 [15:14] */
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_MASK                    0xc000
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_ALIGN                   0
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_BITS                    2
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_SHIFT                   14
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_SWSDR_div2              0
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_SWSDR_div1              1
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_DWSDR_div2              2
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN3_DWSDR_div1              3
 
 /* XgxsBlk5 :: xgxsStatus5 :: tx1g_mode_ln2 [13:12] */
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_MASK                    0x3000
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_ALIGN                   0
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_BITS                    2
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_SHIFT                   12
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_SWSDR_div2              0
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_SWSDR_div1              1
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_DWSDR_div2              2
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN2_DWSDR_div1              3
 
 /* XgxsBlk5 :: xgxsStatus5 :: tx1g_mode_ln1 [11:10] */
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_MASK                    0x0c00
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_ALIGN                   0
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_BITS                    2
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_SHIFT                   10
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_SWSDR_div2              0
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_SWSDR_div1              1
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_DWSDR_div2              2
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN1_DWSDR_div1              3
 
 /* XgxsBlk5 :: xgxsStatus5 :: tx1g_mode_ln0 [09:08] */
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_MASK                    0x0300
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_ALIGN                   0
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_BITS                    2
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_SHIFT                   8
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_SWSDR_div2              0
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_SWSDR_div1              1
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_DWSDR_div2              2
 #define XGXSBLK5_XGXSSTATUS5_TX1G_MODE_LN0_DWSDR_div1              3
 
 /* XgxsBlk5 :: xgxsStatus5 :: rx1g_mode_ln3 [07:06] */
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_MASK                    0x00c0
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_ALIGN                   0
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_BITS                    2
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_SHIFT                   6
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_SWSDR_div2              0
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_SWSDR_div1              1
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_DWSDR_div2              2
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN3_DWSDR_div1              3
 
 /* XgxsBlk5 :: xgxsStatus5 :: rx1g_mode_ln2 [05:04] */
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_MASK                    0x0030
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_ALIGN                   0
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_BITS                    2
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_SHIFT                   4
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_SWSDR_div2              0
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_SWSDR_div1              1
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_DWSDR_div2              2
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN2_DWSDR_div1              3
 
 /* XgxsBlk5 :: xgxsStatus5 :: rx1g_mode_ln1 [03:02] */
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_MASK                    0x000c
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_ALIGN                   0
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_BITS                    2
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_SHIFT                   2
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_SWSDR_div2              0
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_SWSDR_div1              1
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_DWSDR_div2              2
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN1_DWSDR_div1              3
 
 /* XgxsBlk5 :: xgxsStatus5 :: rx1g_mode_ln0 [01:00] */
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_MASK                    0x0003
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_ALIGN                   0
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_BITS                    2
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_SHIFT                   0
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_SWSDR_div2              0
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_SWSDR_div1              1
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_DWSDR_div2              2
 #define XGXSBLK5_XGXSSTATUS5_RX1G_MODE_LN0_DWSDR_div1              3
 
 
 /****************************************************************************
  * XgxsBlk5 :: parDet10GControl2
  */
 /* XgxsBlk5 :: parDet10GControl2 :: reserved0 [15:04] */
 #define XGXSBLK5_PARDET10GCONTROL2_RESERVED0_MASK                  0xfff0
 #define XGXSBLK5_PARDET10GCONTROL2_RESERVED0_ALIGN                 0
 #define XGXSBLK5_PARDET10GCONTROL2_RESERVED0_BITS                  12
 #define XGXSBLK5_PARDET10GCONTROL2_RESERVED0_SHIFT                 4
 
 /* XgxsBlk5 :: parDet10GControl2 :: pd_parkFail [03:03] */
 #define XGXSBLK5_PARDET10GCONTROL2_PD_PARKFAIL_MASK                0x0008
 #define XGXSBLK5_PARDET10GCONTROL2_PD_PARKFAIL_ALIGN               0
 #define XGXSBLK5_PARDET10GCONTROL2_PD_PARKFAIL_BITS                1
 #define XGXSBLK5_PARDET10GCONTROL2_PD_PARKFAIL_SHIFT               3
 
 /* XgxsBlk5 :: parDet10GControl2 :: pd_useLinkStatus [02:02] */
 #define XGXSBLK5_PARDET10GCONTROL2_PD_USELINKSTATUS_MASK           0x0004
 #define XGXSBLK5_PARDET10GCONTROL2_PD_USELINKSTATUS_ALIGN          0
 #define XGXSBLK5_PARDET10GCONTROL2_PD_USELINKSTATUS_BITS           1
 #define XGXSBLK5_PARDET10GCONTROL2_PD_USELINKSTATUS_SHIFT          2
 
 /* XgxsBlk5 :: parDet10GControl2 :: pd_cl73_couple_dis [01:01] */
 #define XGXSBLK5_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_MASK         0x0002
 #define XGXSBLK5_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_ALIGN        0
 #define XGXSBLK5_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_BITS         1
 #define XGXSBLK5_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_SHIFT        1
 
 /* XgxsBlk5 :: parDet10GControl2 :: pd_IgnoreLink_dis [00:00] */
 #define XGXSBLK5_PARDET10GCONTROL2_PD_IGNORELINK_DIS_MASK          0x0001
 #define XGXSBLK5_PARDET10GCONTROL2_PD_IGNORELINK_DIS_ALIGN         0
 #define XGXSBLK5_PARDET10GCONTROL2_PD_IGNORELINK_DIS_BITS          1
 #define XGXSBLK5_PARDET10GCONTROL2_PD_IGNORELINK_DIS_SHIFT         0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk6
  */
 /****************************************************************************
  * XgxsBlk6 :: xgxsX2Control1
  */
 /* XgxsBlk6 :: xgxsX2Control1 :: reserved0 [15:05] */
 #define XGXSBLK6_XGXSX2CONTROL1_RESERVED0_MASK                     0xffe0
 #define XGXSBLK6_XGXSX2CONTROL1_RESERVED0_ALIGN                    0
 #define XGXSBLK6_XGXSX2CONTROL1_RESERVED0_BITS                     11
 #define XGXSBLK6_XGXSX2CONTROL1_RESERVED0_SHIFT                    5
 
 /* XgxsBlk6 :: xgxsX2Control1 :: xgxsX2_outdiv_ctrl_override [04:04] */
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_OVERRIDE_MASK   0x0010
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_OVERRIDE_ALIGN  0
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_OVERRIDE_BITS   1
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_OVERRIDE_SHIFT  4
 
 /* XgxsBlk6 :: xgxsX2Control1 :: xgxsX2_outdiv_ctrl_val [03:03] */
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_VAL_MASK        0x0008
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_VAL_ALIGN       0
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_VAL_BITS        1
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_OUTDIV_CTRL_VAL_SHIFT       3
 
 /* XgxsBlk6 :: xgxsX2Control1 :: xgxsX2_1_en_mdio_ctrl [02:02] */
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_1_EN_MDIO_CTRL_MASK         0x0004
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_1_EN_MDIO_CTRL_ALIGN        0
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_1_EN_MDIO_CTRL_BITS         1
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_1_EN_MDIO_CTRL_SHIFT        2
 
 /* XgxsBlk6 :: xgxsX2Control1 :: xgxsX2_en_override [01:01] */
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_OVERRIDE_MASK            0x0002
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_OVERRIDE_ALIGN           0
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_OVERRIDE_BITS            1
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_OVERRIDE_SHIFT           1
 
 /* XgxsBlk6 :: xgxsX2Control1 :: xgxsX2_en [00:00] */
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_MASK                     0x0001
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_ALIGN                    0
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_BITS                     1
 #define XGXSBLK6_XGXSX2CONTROL1_XGXSX2_EN_SHIFT                    0
 
 
 /****************************************************************************
  * XgxsBlk6 :: xgxsX2Control2
  */
 /* XgxsBlk6 :: xgxsX2Control2 :: reserved0 [15:05] */
 #define XGXSBLK6_XGXSX2CONTROL2_RESERVED0_MASK                     0xffe0
 #define XGXSBLK6_XGXSX2CONTROL2_RESERVED0_ALIGN                    0
 #define XGXSBLK6_XGXSX2CONTROL2_RESERVED0_BITS                     11
 #define XGXSBLK6_XGXSX2CONTROL2_RESERVED0_SHIFT                    5
 
 /* XgxsBlk6 :: xgxsX2Control2 :: xgxsX2_ba_hyst_en [04:04] */
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_HYST_EN_MASK             0x0010
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_HYST_EN_ALIGN            0
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_HYST_EN_BITS             1
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_HYST_EN_SHIFT            4
 
 /* XgxsBlk6 :: xgxsX2Control2 :: xgxsX2_ba_link_en [03:03] */
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_LINK_EN_MASK             0x0008
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_LINK_EN_ALIGN            0
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_LINK_EN_BITS             1
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_LINK_EN_SHIFT            3
 
 /* XgxsBlk6 :: xgxsX2Control2 :: xgxs_ba_link_force [02:02] */
 #define XGXSBLK6_XGXSX2CONTROL2_XGXS_BA_LINK_FORCE_MASK            0x0004
 #define XGXSBLK6_XGXSX2CONTROL2_XGXS_BA_LINK_FORCE_ALIGN           0
 #define XGXSBLK6_XGXSX2CONTROL2_XGXS_BA_LINK_FORCE_BITS            1
 #define XGXSBLK6_XGXSX2CONTROL2_XGXS_BA_LINK_FORCE_SHIFT           2
 
 /* XgxsBlk6 :: xgxsX2Control2 :: xgxsX2_ba_sync_status_cya [01:01] */
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_SYNC_STATUS_CYA_MASK     0x0002
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_SYNC_STATUS_CYA_ALIGN    0
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_SYNC_STATUS_CYA_BITS     1
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_SYNC_STATUS_CYA_SHIFT    1
 
 /* XgxsBlk6 :: xgxsX2Control2 :: xgxsX2_ba_dataout_cya [00:00] */
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_DATAOUT_CYA_MASK         0x0001
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_DATAOUT_CYA_ALIGN        0
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_DATAOUT_CYA_BITS         1
 #define XGXSBLK6_XGXSX2CONTROL2_XGXSX2_BA_DATAOUT_CYA_SHIFT        0
 
 
 /****************************************************************************
  * XgxsBlk6 :: xgxsX2Test1
  */
 /* XgxsBlk6 :: xgxsX2Test1 :: reserved0 [15:06] */
 #define XGXSBLK6_XGXSX2TEST1_RESERVED0_MASK                        0xffc0
 #define XGXSBLK6_XGXSX2TEST1_RESERVED0_ALIGN                       0
 #define XGXSBLK6_XGXSX2TEST1_RESERVED0_BITS                        10
 #define XGXSBLK6_XGXSX2TEST1_RESERVED0_SHIFT                       6
 
 /* XgxsBlk6 :: xgxsX2Test1 :: xgxsX2_ba_blkln_sel [05:03] */
 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_BLKLN_SEL_MASK              0x0038
 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_BLKLN_SEL_ALIGN             0
 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_BLKLN_SEL_BITS              3
 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_BLKLN_SEL_SHIFT             3
 
 /* XgxsBlk6 :: xgxsX2Test1 :: xgxsX2_ba_tstsel [02:00] */
 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_TSTSEL_MASK                 0x0007
 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_TSTSEL_ALIGN                0
 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_TSTSEL_BITS                 3
 #define XGXSBLK6_XGXSX2TEST1_XGXSX2_BA_TSTSEL_SHIFT                0
 
 
 /****************************************************************************
  * XgxsBlk6 :: xgxsX2Status1
  */
 /* XgxsBlk6 :: xgxsX2Status1 :: reserved0 [15:02] */
 #define XGXSBLK6_XGXSX2STATUS1_RESERVED0_MASK                      0xfffc
 #define XGXSBLK6_XGXSX2STATUS1_RESERVED0_ALIGN                     0
 #define XGXSBLK6_XGXSX2STATUS1_RESERVED0_BITS                      14
 #define XGXSBLK6_XGXSX2STATUS1_RESERVED0_SHIFT                     2
 
 /* XgxsBlk6 :: xgxsX2Status1 :: xgxsX2_ba_skew_status_ln1 [01:01] */
 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_LN1_MASK      0x0002
 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_LN1_ALIGN     0
 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_LN1_BITS      1
 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_LN1_SHIFT     1
 
 /* XgxsBlk6 :: xgxsX2Status1 :: xgxsX2_ba_skew_status_ln0 [00:00] */
 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_LN0_MASK      0x0001
 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_LN0_ALIGN     0
 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_LN0_BITS      1
 #define XGXSBLK6_XGXSX2STATUS1_XGXSX2_BA_SKEW_STATUS_LN0_SHIFT     0
 
 
 /****************************************************************************
  * XgxsBlk6 :: bpmControl
  */
 /* XgxsBlk6 :: bpmControl :: bpm_link_stable_timer_val [15:09] */
 #define XGXSBLK6_BPMCONTROL_BPM_LINK_STABLE_TIMER_VAL_MASK         0xfe00
 #define XGXSBLK6_BPMCONTROL_BPM_LINK_STABLE_TIMER_VAL_ALIGN        0
 #define XGXSBLK6_BPMCONTROL_BPM_LINK_STABLE_TIMER_VAL_BITS         7
 #define XGXSBLK6_BPMCONTROL_BPM_LINK_STABLE_TIMER_VAL_SHIFT        9
 
 /* XgxsBlk6 :: bpmControl :: reserved0 [08:02] */
 #define XGXSBLK6_BPMCONTROL_RESERVED0_MASK                         0x01fc
 #define XGXSBLK6_BPMCONTROL_RESERVED0_ALIGN                        0
 #define XGXSBLK6_BPMCONTROL_RESERVED0_BITS                         7
 #define XGXSBLK6_BPMCONTROL_RESERVED0_SHIFT                        2
 
 /* XgxsBlk6 :: bpmControl :: bpm_tx_squelch_en [01:01] */
 #define XGXSBLK6_BPMCONTROL_BPM_TX_SQUELCH_EN_MASK                 0x0002
 #define XGXSBLK6_BPMCONTROL_BPM_TX_SQUELCH_EN_ALIGN                0
 #define XGXSBLK6_BPMCONTROL_BPM_TX_SQUELCH_EN_BITS                 1
 #define XGXSBLK6_BPMCONTROL_BPM_TX_SQUELCH_EN_SHIFT                1
 
 /* XgxsBlk6 :: bpmControl :: bpm_mode [00:00] */
 #define XGXSBLK6_BPMCONTROL_BPM_MODE_MASK                          0x0001
 #define XGXSBLK6_BPMCONTROL_BPM_MODE_ALIGN                         0
 #define XGXSBLK6_BPMCONTROL_BPM_MODE_BITS                          1
 #define XGXSBLK6_BPMCONTROL_BPM_MODE_SHIFT                         0
 
 
 /****************************************************************************
  * XgxsBlk6 :: bpmStatus
  */
 /* XgxsBlk6 :: bpmStatus :: reserved0 [15:02] */
 #define XGXSBLK6_BPMSTATUS_RESERVED0_MASK                          0xfffc
 #define XGXSBLK6_BPMSTATUS_RESERVED0_ALIGN                         0
 #define XGXSBLK6_BPMSTATUS_RESERVED0_BITS                          14
 #define XGXSBLK6_BPMSTATUS_RESERVED0_SHIFT                         2
 
 /* XgxsBlk6 :: bpmStatus :: bpm_link10g_status [01:01] */
 #define XGXSBLK6_BPMSTATUS_BPM_LINK10G_STATUS_MASK                 0x0002
 #define XGXSBLK6_BPMSTATUS_BPM_LINK10G_STATUS_ALIGN                0
 #define XGXSBLK6_BPMSTATUS_BPM_LINK10G_STATUS_BITS                 1
 #define XGXSBLK6_BPMSTATUS_BPM_LINK10G_STATUS_SHIFT                1
 
 /* XgxsBlk6 :: bpmStatus :: bpm_pd_fault [00:00] */
 #define XGXSBLK6_BPMSTATUS_BPM_PD_FAULT_MASK                       0x0001
 #define XGXSBLK6_BPMSTATUS_BPM_PD_FAULT_ALIGN                      0
 #define XGXSBLK6_BPMSTATUS_BPM_PD_FAULT_BITS                       1
 #define XGXSBLK6_BPMSTATUS_BPM_PD_FAULT_SHIFT                      0
 
 
 /****************************************************************************
  * XgxsBlk6 :: bpm10GTimer
  */
 /* XgxsBlk6 :: bpm10GTimer :: bpm_10g_timer_val [15:00] */
 #define XGXSBLK6_BPM10GTIMER_BPM_10G_TIMER_VAL_MASK                0xffff
 #define XGXSBLK6_BPM10GTIMER_BPM_10G_TIMER_VAL_ALIGN               0
 #define XGXSBLK6_BPM10GTIMER_BPM_10G_TIMER_VAL_BITS                16
 #define XGXSBLK6_BPM10GTIMER_BPM_10G_TIMER_VAL_SHIFT               0
 
 
 /****************************************************************************
  * XgxsBlk6 :: bpm1GTimer
  */
 /* XgxsBlk6 :: bpm1GTimer :: bpm_1g_timer_val [15:00] */
 #define XGXSBLK6_BPM1GTIMER_BPM_1G_TIMER_VAL_MASK                  0xffff
 #define XGXSBLK6_BPM1GTIMER_BPM_1G_TIMER_VAL_ALIGN                 0
 #define XGXSBLK6_BPM1GTIMER_BPM_1G_TIMER_VAL_BITS                  16
 #define XGXSBLK6_BPM1GTIMER_BPM_1G_TIMER_VAL_SHIFT                 0
 
 
 /****************************************************************************
  * XgxsBlk6 :: bpmTxDisTimer
  */
 /* XgxsBlk6 :: bpmTxDisTimer :: reserved0 [15:13] */
 #define XGXSBLK6_BPMTXDISTIMER_RESERVED0_MASK                      0xe000
 #define XGXSBLK6_BPMTXDISTIMER_RESERVED0_ALIGN                     0
 #define XGXSBLK6_BPMTXDISTIMER_RESERVED0_BITS                      3
 #define XGXSBLK6_BPMTXDISTIMER_RESERVED0_SHIFT                     13
 
 /* XgxsBlk6 :: bpmTxDisTimer :: bpm_txdis_timer_val [12:00] */
 #define XGXSBLK6_BPMTXDISTIMER_BPM_TXDIS_TIMER_VAL_MASK            0x1fff
 #define XGXSBLK6_BPMTXDISTIMER_BPM_TXDIS_TIMER_VAL_ALIGN           0
 #define XGXSBLK6_BPMTXDISTIMER_BPM_TXDIS_TIMER_VAL_BITS            13
 #define XGXSBLK6_BPMTXDISTIMER_BPM_TXDIS_TIMER_VAL_SHIFT           0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk7
  */
 /****************************************************************************
  * XgxsBlk7 :: EEEControl
  */
 /* XgxsBlk7 :: EEEControl :: reserved_for_eco0 [15:08] */
 #define XGXSBLK7_EEECONTROL_RESERVED_FOR_ECO0_MASK                 0xff00
 #define XGXSBLK7_EEECONTROL_RESERVED_FOR_ECO0_ALIGN                0
 #define XGXSBLK7_EEECONTROL_RESERVED_FOR_ECO0_BITS                 8
 #define XGXSBLK7_EEECONTROL_RESERVED_FOR_ECO0_SHIFT                8
 
 /* XgxsBlk7 :: EEEControl :: brcm_66_ll_swap_cya [07:07] */
 #define XGXSBLK7_EEECONTROL_BRCM_66_LL_SWAP_CYA_MASK               0x0080
 #define XGXSBLK7_EEECONTROL_BRCM_66_LL_SWAP_CYA_ALIGN              0
 #define XGXSBLK7_EEECONTROL_BRCM_66_LL_SWAP_CYA_BITS               1
 #define XGXSBLK7_EEECONTROL_BRCM_66_LL_SWAP_CYA_SHIFT              7
 
 /* XgxsBlk7 :: EEEControl :: LPI_hyst_cnt_10g [06:04] */
 #define XGXSBLK7_EEECONTROL_LPI_HYST_CNT_10G_MASK                  0x0070
 #define XGXSBLK7_EEECONTROL_LPI_HYST_CNT_10G_ALIGN                 0
 #define XGXSBLK7_EEECONTROL_LPI_HYST_CNT_10G_BITS                  3
 #define XGXSBLK7_EEECONTROL_LPI_HYST_CNT_10G_SHIFT                 4
 
 /* XgxsBlk7 :: EEEControl :: LPI_hyst_en_10g [03:03] */
 #define XGXSBLK7_EEECONTROL_LPI_HYST_EN_10G_MASK                   0x0008
 #define XGXSBLK7_EEECONTROL_LPI_HYST_EN_10G_ALIGN                  0
 #define XGXSBLK7_EEECONTROL_LPI_HYST_EN_10G_BITS                   1
 #define XGXSBLK7_EEECONTROL_LPI_HYST_EN_10G_SHIFT                  3
 
 /* XgxsBlk7 :: EEEControl :: LPI_col_det_en [02:02] */
 #define XGXSBLK7_EEECONTROL_LPI_COL_DET_EN_MASK                    0x0004
 #define XGXSBLK7_EEECONTROL_LPI_COL_DET_EN_ALIGN                   0
 #define XGXSBLK7_EEECONTROL_LPI_COL_DET_EN_BITS                    1
 #define XGXSBLK7_EEECONTROL_LPI_COL_DET_EN_SHIFT                   2
 
 /* XgxsBlk7 :: EEEControl :: LPI_en_rx [01:01] */
 #define XGXSBLK7_EEECONTROL_LPI_EN_RX_MASK                         0x0002
 #define XGXSBLK7_EEECONTROL_LPI_EN_RX_ALIGN                        0
 #define XGXSBLK7_EEECONTROL_LPI_EN_RX_BITS                         1
 #define XGXSBLK7_EEECONTROL_LPI_EN_RX_SHIFT                        1
 
 /* XgxsBlk7 :: EEEControl :: LPI_en_tx [00:00] */
 #define XGXSBLK7_EEECONTROL_LPI_EN_TX_MASK                         0x0001
 #define XGXSBLK7_EEECONTROL_LPI_EN_TX_ALIGN                        0
 #define XGXSBLK7_EEECONTROL_LPI_EN_TX_BITS                         1
 #define XGXSBLK7_EEECONTROL_LPI_EN_TX_SHIFT                        0
 
 
 /****************************************************************************
  * XgxsBlk7 :: EEEstatus
  */
 /* XgxsBlk7 :: EEEstatus :: reserved_for_eco0 [15:04] */
 #define XGXSBLK7_EEESTATUS_RESERVED_FOR_ECO0_MASK                  0xfff0
 #define XGXSBLK7_EEESTATUS_RESERVED_FOR_ECO0_ALIGN                 0
 #define XGXSBLK7_EEESTATUS_RESERVED_FOR_ECO0_BITS                  12
 #define XGXSBLK7_EEESTATUS_RESERVED_FOR_ECO0_SHIFT                 4
 
 /* XgxsBlk7 :: EEEstatus :: rx10g_LPI_ind [03:03] */
 #define XGXSBLK7_EEESTATUS_RX10G_LPI_IND_MASK                      0x0008
 #define XGXSBLK7_EEESTATUS_RX10G_LPI_IND_ALIGN                     0
 #define XGXSBLK7_EEESTATUS_RX10G_LPI_IND_BITS                      1
 #define XGXSBLK7_EEESTATUS_RX10G_LPI_IND_SHIFT                     3
 
 /* XgxsBlk7 :: EEEstatus :: tx10g_LPI_ind [02:02] */
 #define XGXSBLK7_EEESTATUS_TX10G_LPI_IND_MASK                      0x0004
 #define XGXSBLK7_EEESTATUS_TX10G_LPI_IND_ALIGN                     0
 #define XGXSBLK7_EEESTATUS_TX10G_LPI_IND_BITS                      1
 #define XGXSBLK7_EEESTATUS_TX10G_LPI_IND_SHIFT                     2
 
 /* XgxsBlk7 :: EEEstatus :: LPI_tx_det [01:01] */
 #define XGXSBLK7_EEESTATUS_LPI_TX_DET_MASK                         0x0002
 #define XGXSBLK7_EEESTATUS_LPI_TX_DET_ALIGN                        0
 #define XGXSBLK7_EEESTATUS_LPI_TX_DET_BITS                         1
 #define XGXSBLK7_EEESTATUS_LPI_TX_DET_SHIFT                        1
 
 /* XgxsBlk7 :: EEEstatus :: LPI_rx_det [00:00] */
 #define XGXSBLK7_EEESTATUS_LPI_RX_DET_MASK                         0x0001
 #define XGXSBLK7_EEESTATUS_LPI_RX_DET_ALIGN                        0
 #define XGXSBLK7_EEESTATUS_LPI_RX_DET_BITS                         1
 #define XGXSBLK7_EEESTATUS_LPI_RX_DET_SHIFT                        0
 
 
 /****************************************************************************
  * XgxsBlk7 :: xgmiiLPI
  */
 /* XgxsBlk7 :: xgmiiLPI :: Quiet [15:08] */
 #define XGXSBLK7_XGMIILPI_QUIET_MASK                               0xff00
 #define XGXSBLK7_XGMIILPI_QUIET_ALIGN                              0
 #define XGXSBLK7_XGMIILPI_QUIET_BITS                               8
 #define XGXSBLK7_XGMIILPI_QUIET_SHIFT                              8
 
 /* XgxsBlk7 :: xgmiiLPI :: LPI [07:00] */
 #define XGXSBLK7_XGMIILPI_LPI_MASK                                 0x00ff
 #define XGXSBLK7_XGMIILPI_LPI_ALIGN                                0
 #define XGXSBLK7_XGMIILPI_LPI_BITS                                 8
 #define XGXSBLK7_XGMIILPI_LPI_SHIFT                                0
 
 
 /****************************************************************************
  * XgxsBlk7 :: LPIlane13
  */
 /* XgxsBlk7 :: LPIlane13 :: reserved_for_eco0 [15:09] */
 #define XGXSBLK7_LPILANE13_RESERVED_FOR_ECO0_MASK                  0xfe00
 #define XGXSBLK7_LPILANE13_RESERVED_FOR_ECO0_ALIGN                 0
 #define XGXSBLK7_LPILANE13_RESERVED_FOR_ECO0_BITS                  7
 #define XGXSBLK7_LPILANE13_RESERVED_FOR_ECO0_SHIFT                 9
 
 /* XgxsBlk7 :: LPIlane13 :: LPI_lane13 [08:00] */
 #define XGXSBLK7_LPILANE13_LPI_LANE13_MASK                         0x01ff
 #define XGXSBLK7_LPILANE13_LPI_LANE13_ALIGN                        0
 #define XGXSBLK7_LPILANE13_LPI_LANE13_BITS                         9
 #define XGXSBLK7_LPILANE13_LPI_LANE13_SHIFT                        0
 
 
 /****************************************************************************
  * XgxsBlk7 :: Qrsvd1
  */
 /* XgxsBlk7 :: Qrsvd1 :: reserved_for_eco0 [15:11] */
 #define XGXSBLK7_QRSVD1_RESERVED_FOR_ECO0_MASK                     0xf800
 #define XGXSBLK7_QRSVD1_RESERVED_FOR_ECO0_ALIGN                    0
 #define XGXSBLK7_QRSVD1_RESERVED_FOR_ECO0_BITS                     5
 #define XGXSBLK7_QRSVD1_RESERVED_FOR_ECO0_SHIFT                    11
 
 /* XgxsBlk7 :: Qrsvd1 :: Qrsvd3_msb [10:10] */
 #define XGXSBLK7_QRSVD1_QRSVD3_MSB_MASK                            0x0400
 #define XGXSBLK7_QRSVD1_QRSVD3_MSB_ALIGN                           0
 #define XGXSBLK7_QRSVD1_QRSVD3_MSB_BITS                            1
 #define XGXSBLK7_QRSVD1_QRSVD3_MSB_SHIFT                           10
 
 /* XgxsBlk7 :: Qrsvd1 :: Qrsvd2_msb [09:09] */
 #define XGXSBLK7_QRSVD1_QRSVD2_MSB_MASK                            0x0200
 #define XGXSBLK7_QRSVD1_QRSVD2_MSB_ALIGN                           0
 #define XGXSBLK7_QRSVD1_QRSVD2_MSB_BITS                            1
 #define XGXSBLK7_QRSVD1_QRSVD2_MSB_SHIFT                           9
 
 /* XgxsBlk7 :: Qrsvd1 :: Qrsvd1 [08:00] */
 #define XGXSBLK7_QRSVD1_QRSVD1_MASK                                0x01ff
 #define XGXSBLK7_QRSVD1_QRSVD1_ALIGN                               0
 #define XGXSBLK7_QRSVD1_QRSVD1_BITS                                9
 #define XGXSBLK7_QRSVD1_QRSVD1_SHIFT                               0
 
 
 /****************************************************************************
  * XgxsBlk7 :: Qrsvd23
  */
 /* XgxsBlk7 :: Qrsvd23 :: Qrsvd2 [15:08] */
 #define XGXSBLK7_QRSVD23_QRSVD2_MASK                               0xff00
 #define XGXSBLK7_QRSVD23_QRSVD2_ALIGN                              0
 #define XGXSBLK7_QRSVD23_QRSVD2_BITS                               8
 #define XGXSBLK7_QRSVD23_QRSVD2_SHIFT                              8
 
 /* XgxsBlk7 :: Qrsvd23 :: Qrsvd3 [07:00] */
 #define XGXSBLK7_QRSVD23_QRSVD3_MASK                               0x00ff
 #define XGXSBLK7_QRSVD23_QRSVD3_ALIGN                              0
 #define XGXSBLK7_QRSVD23_QRSVD3_BITS                               8
 #define XGXSBLK7_QRSVD23_QRSVD3_SHIFT                              0
 
 
 /****************************************************************************
  * XgxsBlk7 :: Qrsvdswap
  */
 /* XgxsBlk7 :: Qrsvdswap :: reserved_for_eco0 [15:15] */
 #define XGXSBLK7_QRSVDSWAP_RESERVED_FOR_ECO0_MASK                  0x8000
 #define XGXSBLK7_QRSVDSWAP_RESERVED_FOR_ECO0_ALIGN                 0
 #define XGXSBLK7_QRSVDSWAP_RESERVED_FOR_ECO0_BITS                  1
 #define XGXSBLK7_QRSVDSWAP_RESERVED_FOR_ECO0_SHIFT                 15
 
 /* XgxsBlk7 :: Qrsvdswap :: lf_rf_swap_cya [14:14] */
 #define XGXSBLK7_QRSVDSWAP_LF_RF_SWAP_CYA_MASK                     0x4000
 #define XGXSBLK7_QRSVDSWAP_LF_RF_SWAP_CYA_ALIGN                    0
 #define XGXSBLK7_QRSVDSWAP_LF_RF_SWAP_CYA_BITS                     1
 #define XGXSBLK7_QRSVDSWAP_LF_RF_SWAP_CYA_SHIFT                    14
 
 /* XgxsBlk7 :: Qrsvdswap :: Qrsvdswap_ctrl [13:10] */
 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_CTRL_MASK                     0x3c00
 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_CTRL_ALIGN                    0
 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_CTRL_BITS                     4
 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_CTRL_SHIFT                    10
 
 /* XgxsBlk7 :: Qrsvdswap :: Qrsvdswap [09:00] */
 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_MASK                          0x03ff
 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_ALIGN                         0
 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_BITS                          10
 #define XGXSBLK7_QRSVDSWAP_QRSVDSWAP_SHIFT                         0
 
 
 /****************************************************************************
  * XgxsBlk7 :: Qrsvdstatus
  */
 /* XgxsBlk7 :: Qrsvdstatus :: rx_Q_char3 [15:07] */
 #define XGXSBLK7_QRSVDSTATUS_RX_Q_CHAR3_MASK                       0xff80
 #define XGXSBLK7_QRSVDSTATUS_RX_Q_CHAR3_ALIGN                      0
 #define XGXSBLK7_QRSVDSTATUS_RX_Q_CHAR3_BITS                       9
 #define XGXSBLK7_QRSVDSTATUS_RX_Q_CHAR3_SHIFT                      7
 
 /* XgxsBlk7 :: Qrsvdstatus :: reserved_for_eco0 [06:05] */
 #define XGXSBLK7_QRSVDSTATUS_RESERVED_FOR_ECO0_MASK                0x0060
 #define XGXSBLK7_QRSVDSTATUS_RESERVED_FOR_ECO0_ALIGN               0
 #define XGXSBLK7_QRSVDSTATUS_RESERVED_FOR_ECO0_BITS                2
 #define XGXSBLK7_QRSVDSTATUS_RESERVED_FOR_ECO0_SHIFT               5
 
 /* XgxsBlk7 :: Qrsvdstatus :: rx_undef_Q_det [04:04] */
 #define XGXSBLK7_QRSVDSTATUS_RX_UNDEF_Q_DET_MASK                   0x0010
 #define XGXSBLK7_QRSVDSTATUS_RX_UNDEF_Q_DET_ALIGN                  0
 #define XGXSBLK7_QRSVDSTATUS_RX_UNDEF_Q_DET_BITS                   1
 #define XGXSBLK7_QRSVDSTATUS_RX_UNDEF_Q_DET_SHIFT                  4
 
 /* XgxsBlk7 :: Qrsvdstatus :: xaui_rx_rf_det [03:03] */
 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_RF_DET_MASK                   0x0008
 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_RF_DET_ALIGN                  0
 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_RF_DET_BITS                   1
 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_RF_DET_SHIFT                  3
 
 /* XgxsBlk7 :: Qrsvdstatus :: xaui_rx_lf_det [02:02] */
 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_LF_DET_MASK                   0x0004
 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_LF_DET_ALIGN                  0
 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_LF_DET_BITS                   1
 #define XGXSBLK7_QRSVDSTATUS_XAUI_RX_LF_DET_SHIFT                  2
 
 /* XgxsBlk7 :: Qrsvdstatus :: Qrsvd_rx_det [01:01] */
 #define XGXSBLK7_QRSVDSTATUS_QRSVD_RX_DET_MASK                     0x0002
 #define XGXSBLK7_QRSVDSTATUS_QRSVD_RX_DET_ALIGN                    0
 #define XGXSBLK7_QRSVDSTATUS_QRSVD_RX_DET_BITS                     1
 #define XGXSBLK7_QRSVDSTATUS_QRSVD_RX_DET_SHIFT                    1
 
 /* XgxsBlk7 :: Qrsvdstatus :: Qrsvd_tx_det [00:00] */
 #define XGXSBLK7_QRSVDSTATUS_QRSVD_TX_DET_MASK                     0x0001
 #define XGXSBLK7_QRSVDSTATUS_QRSVD_TX_DET_ALIGN                    0
 #define XGXSBLK7_QRSVDSTATUS_QRSVD_TX_DET_BITS                     1
 #define XGXSBLK7_QRSVDSTATUS_QRSVD_TX_DET_SHIFT                    0
 
 
 /****************************************************************************
  * XgxsBlk7 :: cl48_tx_lpi_sm
  */
 /* XgxsBlk7 :: cl48_tx_lpi_sm :: reserved_for_eco0 [15:07] */
 #define XGXSBLK7_CL48_TX_LPI_SM_RESERVED_FOR_ECO0_MASK             0xff80
 #define XGXSBLK7_CL48_TX_LPI_SM_RESERVED_FOR_ECO0_ALIGN            0
 #define XGXSBLK7_CL48_TX_LPI_SM_RESERVED_FOR_ECO0_BITS             9
 #define XGXSBLK7_CL48_TX_LPI_SM_RESERVED_FOR_ECO0_SHIFT            7
 
 /* XgxsBlk7 :: cl48_tx_lpi_sm :: cl48_tx_lpi_state_l [06:03] */
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_MASK           0x0078
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_ALIGN          0
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_BITS           4
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_SHIFT          3
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_TX_REFRESH     8
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_TX_QUIET       4
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_TX_SLEEP       2
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_L_TX_ACTIVE      1
 
 /* XgxsBlk7 :: cl48_tx_lpi_sm :: cl48_tx_lpi_state_c [02:00] */
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_MASK           0x0007
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_ALIGN          0
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_BITS           3
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_SHIFT          0
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_TX_REFRESH     3
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_TX_QUIET       2
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_TX_SLEEP       1
 #define XGXSBLK7_CL48_TX_LPI_SM_CL48_TX_LPI_STATE_C_TX_ACTIVE      0
 
 
 /****************************************************************************
  * XgxsBlk7 :: cl48_rx_lpi_sm
  */
 /* XgxsBlk7 :: cl48_rx_lpi_sm :: reserved_for_eco0 [15:09] */
 #define XGXSBLK7_CL48_RX_LPI_SM_RESERVED_FOR_ECO0_MASK             0xfe00
 #define XGXSBLK7_CL48_RX_LPI_SM_RESERVED_FOR_ECO0_ALIGN            0
 #define XGXSBLK7_CL48_RX_LPI_SM_RESERVED_FOR_ECO0_BITS             7
 #define XGXSBLK7_CL48_RX_LPI_SM_RESERVED_FOR_ECO0_SHIFT            9
 
 /* XgxsBlk7 :: cl48_rx_lpi_sm :: cl48_rx_lpi_state_l [08:03] */
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_MASK           0x01f8
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_ALIGN          0
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_BITS           6
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_SHIFT          3
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_LINK_FAIL   32
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_WAKE        16
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_QUIET       8
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_DEACT       4
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_SLEEP       2
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_L_RX_ACTIVE      1
 
 /* XgxsBlk7 :: cl48_rx_lpi_sm :: cl48_rx_lpi_state_c [02:00] */
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_MASK           0x0007
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_ALIGN          0
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_BITS           3
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_SHIFT          0
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_LINK_FAIL   5
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_WAKE        4
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_QUIET       3
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_DEACT       2
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_SLEEP       1
 #define XGXSBLK7_CL48_RX_LPI_SM_CL48_RX_LPI_STATE_C_RX_ACTIVE      0
 
 
 /****************************************************************************
  * XgxsBlk7 :: fifo_ctrl
  */
 /* XgxsBlk7 :: fifo_ctrl :: reserved_for_eco0 [15:10] */
 #define XGXSBLK7_FIFO_CTRL_RESERVED_FOR_ECO0_MASK                  0xfc00
 #define XGXSBLK7_FIFO_CTRL_RESERVED_FOR_ECO0_ALIGN                 0
 #define XGXSBLK7_FIFO_CTRL_RESERVED_FOR_ECO0_BITS                  6
 #define XGXSBLK7_FIFO_CTRL_RESERVED_FOR_ECO0_SHIFT                 10
 
 /* XgxsBlk7 :: fifo_ctrl :: txfifo_chk_cya [09:09] */
 #define XGXSBLK7_FIFO_CTRL_TXFIFO_CHK_CYA_MASK                     0x0200
 #define XGXSBLK7_FIFO_CTRL_TXFIFO_CHK_CYA_ALIGN                    0
 #define XGXSBLK7_FIFO_CTRL_TXFIFO_CHK_CYA_BITS                     1
 #define XGXSBLK7_FIFO_CTRL_TXFIFO_CHK_CYA_SHIFT                    9
 
 /* XgxsBlk7 :: fifo_ctrl :: eee_txfifo_ckgate_en [08:08] */
 #define XGXSBLK7_FIFO_CTRL_EEE_TXFIFO_CKGATE_EN_MASK               0x0100
 #define XGXSBLK7_FIFO_CTRL_EEE_TXFIFO_CKGATE_EN_ALIGN              0
 #define XGXSBLK7_FIFO_CTRL_EEE_TXFIFO_CKGATE_EN_BITS               1
 #define XGXSBLK7_FIFO_CTRL_EEE_TXFIFO_CKGATE_EN_SHIFT              8
 
 /* XgxsBlk7 :: fifo_ctrl :: force_rxfifo_mode_en [07:07] */
 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_EN_MASK               0x0080
 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_EN_ALIGN              0
 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_EN_BITS               1
 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_EN_SHIFT              7
 
 /* XgxsBlk7 :: fifo_ctrl :: force_rxfifo_mode_value [06:04] */
 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_VALUE_MASK            0x0070
 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_VALUE_ALIGN           0
 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_VALUE_BITS            3
 #define XGXSBLK7_FIFO_CTRL_FORCE_RXFIFO_MODE_VALUE_SHIFT           4
 
 /* XgxsBlk7 :: fifo_ctrl :: force_txfifo_mode_en [03:03] */
 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_EN_MASK               0x0008
 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_EN_ALIGN              0
 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_EN_BITS               1
 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_EN_SHIFT              3
 
 /* XgxsBlk7 :: fifo_ctrl :: force_txfifo_mode_value [02:00] */
 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_VALUE_MASK            0x0007
 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_VALUE_ALIGN           0
 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_VALUE_BITS            3
 #define XGXSBLK7_FIFO_CTRL_FORCE_TXFIFO_MODE_VALUE_SHIFT           0
 
 
 /****************************************************************************
  * XgxsBlk7 :: fifo_status
  */
 /* XgxsBlk7 :: fifo_status :: reserved_for_eco0 [15:06] */
 #define XGXSBLK7_FIFO_STATUS_RESERVED_FOR_ECO0_MASK                0xffc0
 #define XGXSBLK7_FIFO_STATUS_RESERVED_FOR_ECO0_ALIGN               0
 #define XGXSBLK7_FIFO_STATUS_RESERVED_FOR_ECO0_BITS                10
 #define XGXSBLK7_FIFO_STATUS_RESERVED_FOR_ECO0_SHIFT               6
 
 /* XgxsBlk7 :: fifo_status :: txfifo_mode [05:03] */
 #define XGXSBLK7_FIFO_STATUS_TXFIFO_MODE_MASK                      0x0038
 #define XGXSBLK7_FIFO_STATUS_TXFIFO_MODE_ALIGN                     0
 #define XGXSBLK7_FIFO_STATUS_TXFIFO_MODE_BITS                      3
 #define XGXSBLK7_FIFO_STATUS_TXFIFO_MODE_SHIFT                     3
 
 /* XgxsBlk7 :: fifo_status :: rxfifo_mode [02:00] */
 #define XGXSBLK7_FIFO_STATUS_RXFIFO_MODE_MASK                      0x0007
 #define XGXSBLK7_FIFO_STATUS_RXFIFO_MODE_ALIGN                     0
 #define XGXSBLK7_FIFO_STATUS_RXFIFO_MODE_BITS                      3
 #define XGXSBLK7_FIFO_STATUS_RXFIFO_MODE_SHIFT                     0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk8
  */
 /****************************************************************************
  * XgxsBlk8 :: cl73Control7
  */
 /* XgxsBlk8 :: cl73Control7 :: cl73_an_switch_cntL [15:00] */
 #define XGXSBLK8_CL73CONTROL7_CL73_AN_SWITCH_CNTL_MASK             0xffff
 #define XGXSBLK8_CL73CONTROL7_CL73_AN_SWITCH_CNTL_ALIGN            0
 #define XGXSBLK8_CL73CONTROL7_CL73_AN_SWITCH_CNTL_BITS             16
 #define XGXSBLK8_CL73CONTROL7_CL73_AN_SWITCH_CNTL_SHIFT            0
 
 
 /****************************************************************************
  * XgxsBlk8 :: cl73Control8
  */
 /* XgxsBlk8 :: cl73Control8 :: cl73_refclk_161_offset_cnt [15:08] */
 #define XGXSBLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_MASK      0xff00
 #define XGXSBLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_ALIGN     0
 #define XGXSBLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_BITS      8
 #define XGXSBLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_SHIFT     8
 
 /* XgxsBlk8 :: cl73Control8 :: cl73_an_switch_cntH [07:00] */
 #define XGXSBLK8_CL73CONTROL8_CL73_AN_SWITCH_CNTH_MASK             0x00ff
 #define XGXSBLK8_CL73CONTROL8_CL73_AN_SWITCH_CNTH_ALIGN            0
 #define XGXSBLK8_CL73CONTROL8_CL73_AN_SWITCH_CNTH_BITS             8
 #define XGXSBLK8_CL73CONTROL8_CL73_AN_SWITCH_CNTH_SHIFT            0
 
 
 /****************************************************************************
  * XgxsBlk8 :: cl73Control9
  */
 /* XgxsBlk8 :: cl73Control9 :: reserved0 [15:14] */
 #define XGXSBLK8_CL73CONTROL9_RESERVED0_MASK                       0xc000
 #define XGXSBLK8_CL73CONTROL9_RESERVED0_ALIGN                      0
 #define XGXSBLK8_CL73CONTROL9_RESERVED0_BITS                       2
 #define XGXSBLK8_CL73CONTROL9_RESERVED0_SHIFT                      14
 
 /* XgxsBlk8 :: cl73Control9 :: cl73_link_fail_inhibit_timer_kr_val [13:00] */
 #define XGXSBLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_MASK 0x3fff
 #define XGXSBLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_ALIGN 0
 #define XGXSBLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_BITS 14
 #define XGXSBLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_SHIFT 0
 
 
 /****************************************************************************
  * XgxsBlk8 :: cl73Control10
  */
 /* XgxsBlk8 :: cl73Control10 :: reserved0 [15:14] */
 #define XGXSBLK8_CL73CONTROL10_RESERVED0_MASK                      0xc000
 #define XGXSBLK8_CL73CONTROL10_RESERVED0_ALIGN                     0
 #define XGXSBLK8_CL73CONTROL10_RESERVED0_BITS                      2
 #define XGXSBLK8_CL73CONTROL10_RESERVED0_SHIFT                     14
 
 /* XgxsBlk8 :: cl73Control10 :: cl73_link_fail_inhibit_timer_cl72_val [13:00] */
 #define XGXSBLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_MASK 0x3fff
 #define XGXSBLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_ALIGN 0
 #define XGXSBLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_BITS 14
 #define XGXSBLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_SHIFT 0
 
 
 /****************************************************************************
  * XgxsBlk8 :: tx_pi_control1
  */
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_integ_sat_sel [15:15] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_MASK           0x8000
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_ALIGN          0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_BITS           1
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_SHIFT          15
 
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_integ_sat_1_or_2 [14:14] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_MASK        0x4000
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_ALIGN       0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_BITS        1
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_SHIFT       14
 
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_invert [13:13] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_MASK            0x2000
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_ALIGN           0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_BITS            1
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_SHIFT           13
 
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_step_mult [12:12] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_MASK         0x1000
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_ALIGN        0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_BITS         1
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_SHIFT        12
 
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_step_dir [11:11] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_MASK          0x0800
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_ALIGN         0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_BITS          1
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_SHIFT         11
 
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_step [10:09] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MASK              0x0600
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_ALIGN             0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_BITS              2
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STEP_SHIFT             9
 
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_delta [08:04] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_MASK             0x01f0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_ALIGN            0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_BITS             5
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_SHIFT            4
 
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_strobe [03:03] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_MASK            0x0008
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_ALIGN           0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_BITS            1
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_SHIFT           3
 
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_phase_override [02:02] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_MASK          0x0004
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_ALIGN         0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_BITS          1
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_SHIFT         2
 
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_bypass_mode [01:01] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_MASK             0x0002
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_ALIGN            0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_BITS             1
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_SHIFT            1
 
 /* XgxsBlk8 :: tx_pi_control1 :: tx_pi_en [00:00] */
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_EN_MASK                      0x0001
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_EN_ALIGN                     0
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_EN_BITS                      1
 #define XGXSBLK8_TX_PI_CONTROL1_TX_PI_EN_SHIFT                     0
 
 
 /****************************************************************************
  * XgxsBlk8 :: tx_pi_control2
  */
 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_sm_timer_sel [15:14] */
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_MASK            0xc000
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_ALIGN           0
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_BITS            2
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_SHIFT           14
 
 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_sm_done_override [13:13] */
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_MASK        0x2000
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_ALIGN       0
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_BITS        1
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_SHIFT       13
 
 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_sm_en_override [12:12] */
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_MASK          0x1000
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_ALIGN         0
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_BITS          1
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_SHIFT         12
 
 /* XgxsBlk8 :: tx_pi_control2 :: reserved_for_eco0 [11:08] */
 #define XGXSBLK8_TX_PI_CONTROL2_RESERVED_FOR_ECO0_MASK             0x0f00
 #define XGXSBLK8_TX_PI_CONTROL2_RESERVED_FOR_ECO0_ALIGN            0
 #define XGXSBLK8_TX_PI_CONTROL2_RESERVED_FOR_ECO0_BITS             4
 #define XGXSBLK8_TX_PI_CONTROL2_RESERVED_FOR_ECO0_SHIFT            8
 
 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_loopback_mode [07:07] */
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_MASK           0x0080
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_ALIGN          0
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_BITS           1
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_SHIFT          7
 
 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_sm_bypass [06:06] */
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_BYPASS_MASK               0x0040
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_BYPASS_ALIGN              0
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_BYPASS_BITS               1
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_SM_BYPASS_SHIFT              6
 
 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_integ_reg_clr [05:05] */
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_MASK           0x0020
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_ALIGN          0
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_BITS           1
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_SHIFT          5
 
 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_bwsel_integ [04:02] */
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_MASK             0x001c
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_ALIGN            0
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_BITS             3
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_SHIFT            2
 
 /* XgxsBlk8 :: tx_pi_control2 :: tx_pi_rx_lane_sel [01:00] */
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_MASK             0x0003
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_ALIGN            0
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_BITS             2
 #define XGXSBLK8_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_SHIFT            0
 
 
 /****************************************************************************
  * XgxsBlk8 :: tx_pi_control3
  */
 /* XgxsBlk8 :: tx_pi_control3 :: tx_pi_freq_override_val [15:01] */
 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_MASK       0xfffe
 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_ALIGN      0
 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_BITS       15
 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_SHIFT      1
 
 /* XgxsBlk8 :: tx_pi_control3 :: tx_pi_freq_override_en [00:00] */
 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_MASK        0x0001
 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_ALIGN       0
 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_BITS        1
 #define XGXSBLK8_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_SHIFT       0
 
 
 /****************************************************************************
  * XgxsBlk8 :: tx_pi_status1
  */
 /* XgxsBlk8 :: tx_pi_status1 :: reserved_for_eco0 [15:15] */
 #define XGXSBLK8_TX_PI_STATUS1_RESERVED_FOR_ECO0_MASK              0x8000
 #define XGXSBLK8_TX_PI_STATUS1_RESERVED_FOR_ECO0_ALIGN             0
 #define XGXSBLK8_TX_PI_STATUS1_RESERVED_FOR_ECO0_BITS              1
 #define XGXSBLK8_TX_PI_STATUS1_RESERVED_FOR_ECO0_SHIFT             15
 
 /* XgxsBlk8 :: tx_pi_status1 :: tx_pi_integ_reg [14:00] */
 #define XGXSBLK8_TX_PI_STATUS1_TX_PI_INTEG_REG_MASK                0x7fff
 #define XGXSBLK8_TX_PI_STATUS1_TX_PI_INTEG_REG_ALIGN               0
 #define XGXSBLK8_TX_PI_STATUS1_TX_PI_INTEG_REG_BITS                15
 #define XGXSBLK8_TX_PI_STATUS1_TX_PI_INTEG_REG_SHIFT               0
 
 
 /****************************************************************************
  * XgxsBlk8 :: tx_pi_status2
  */
 /* XgxsBlk8 :: tx_pi_status2 :: reserved_for_eco0 [15:07] */
 #define XGXSBLK8_TX_PI_STATUS2_RESERVED_FOR_ECO0_MASK              0xff80
 #define XGXSBLK8_TX_PI_STATUS2_RESERVED_FOR_ECO0_ALIGN             0
 #define XGXSBLK8_TX_PI_STATUS2_RESERVED_FOR_ECO0_BITS              9
 #define XGXSBLK8_TX_PI_STATUS2_RESERVED_FOR_ECO0_SHIFT             7
 
 /* XgxsBlk8 :: tx_pi_status2 :: tx_pi_phase_cntr [06:00] */
 #define XGXSBLK8_TX_PI_STATUS2_TX_PI_PHASE_CNTR_MASK               0x007f
 #define XGXSBLK8_TX_PI_STATUS2_TX_PI_PHASE_CNTR_ALIGN              0
 #define XGXSBLK8_TX_PI_STATUS2_TX_PI_PHASE_CNTR_BITS               7
 #define XGXSBLK8_TX_PI_STATUS2_TX_PI_PHASE_CNTR_SHIFT              0
 
 
 /****************************************************************************
  * XgxsBlk8 :: txLnSwap1
  */
 /* XgxsBlk8 :: txLnSwap1 :: reserved_for_eco0 [15:08] */
 #define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_MASK                  0xff00
 #define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_ALIGN                 0
 #define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_BITS                  8
 #define XGXSBLK8_TXLNSWAP1_RESERVED_FOR_ECO0_SHIFT                 8
 
 /* XgxsBlk8 :: txLnSwap1 :: tx3_lnswap_sel [07:06] */
 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_MASK                     0x00c0
 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_ALIGN                    0
 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_BITS                     2
 #define XGXSBLK8_TXLNSWAP1_TX3_LNSWAP_SEL_SHIFT                    6
 
 /* XgxsBlk8 :: txLnSwap1 :: tx2_lnswap_sel [05:04] */
 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_MASK                     0x0030
 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_ALIGN                    0
 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_BITS                     2
 #define XGXSBLK8_TXLNSWAP1_TX2_LNSWAP_SEL_SHIFT                    4
 
 /* XgxsBlk8 :: txLnSwap1 :: tx1_lnswap_sel [03:02] */
 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_MASK                     0x000c
 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_ALIGN                    0
 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_BITS                     2
 #define XGXSBLK8_TXLNSWAP1_TX1_LNSWAP_SEL_SHIFT                    2
 
 /* XgxsBlk8 :: txLnSwap1 :: tx0_lnswap_sel [01:00] */
 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_MASK                     0x0003
 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_ALIGN                    0
 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_BITS                     2
 #define XGXSBLK8_TXLNSWAP1_TX0_LNSWAP_SEL_SHIFT                    0
 
 
 /****************************************************************************
  * XgxsBlk8 :: txLnSwap2
  */
 /* XgxsBlk8 :: txLnSwap2 :: reserved_for_eco0 [15:09] */
 #define XGXSBLK8_TXLNSWAP2_RESERVED_FOR_ECO0_MASK                  0xfe00
 #define XGXSBLK8_TXLNSWAP2_RESERVED_FOR_ECO0_ALIGN                 0
 #define XGXSBLK8_TXLNSWAP2_RESERVED_FOR_ECO0_BITS                  7
 #define XGXSBLK8_TXLNSWAP2_RESERVED_FOR_ECO0_SHIFT                 9
 
 /* XgxsBlk8 :: txLnSwap2 :: force_tx_ana_lnswap_sel [08:08] */
 #define XGXSBLK8_TXLNSWAP2_FORCE_TX_ANA_LNSWAP_SEL_MASK            0x0100
 #define XGXSBLK8_TXLNSWAP2_FORCE_TX_ANA_LNSWAP_SEL_ALIGN           0
 #define XGXSBLK8_TXLNSWAP2_FORCE_TX_ANA_LNSWAP_SEL_BITS            1
 #define XGXSBLK8_TXLNSWAP2_FORCE_TX_ANA_LNSWAP_SEL_SHIFT           8
 
 /* XgxsBlk8 :: txLnSwap2 :: tx3_ana_lnswap_sel [07:06] */
 #define XGXSBLK8_TXLNSWAP2_TX3_ANA_LNSWAP_SEL_MASK                 0x00c0
 #define XGXSBLK8_TXLNSWAP2_TX3_ANA_LNSWAP_SEL_ALIGN                0
 #define XGXSBLK8_TXLNSWAP2_TX3_ANA_LNSWAP_SEL_BITS                 2
 #define XGXSBLK8_TXLNSWAP2_TX3_ANA_LNSWAP_SEL_SHIFT                6
 
 /* XgxsBlk8 :: txLnSwap2 :: tx2_ana_lnswap_sel [05:04] */
 #define XGXSBLK8_TXLNSWAP2_TX2_ANA_LNSWAP_SEL_MASK                 0x0030
 #define XGXSBLK8_TXLNSWAP2_TX2_ANA_LNSWAP_SEL_ALIGN                0
 #define XGXSBLK8_TXLNSWAP2_TX2_ANA_LNSWAP_SEL_BITS                 2
 #define XGXSBLK8_TXLNSWAP2_TX2_ANA_LNSWAP_SEL_SHIFT                4
 
 /* XgxsBlk8 :: txLnSwap2 :: tx1_ana_lnswap_sel [03:02] */
 #define XGXSBLK8_TXLNSWAP2_TX1_ANA_LNSWAP_SEL_MASK                 0x000c
 #define XGXSBLK8_TXLNSWAP2_TX1_ANA_LNSWAP_SEL_ALIGN                0
 #define XGXSBLK8_TXLNSWAP2_TX1_ANA_LNSWAP_SEL_BITS                 2
 #define XGXSBLK8_TXLNSWAP2_TX1_ANA_LNSWAP_SEL_SHIFT                2
 
 /* XgxsBlk8 :: txLnSwap2 :: tx0_ana_lnswap_sel [01:00] */
 #define XGXSBLK8_TXLNSWAP2_TX0_ANA_LNSWAP_SEL_MASK                 0x0003
 #define XGXSBLK8_TXLNSWAP2_TX0_ANA_LNSWAP_SEL_ALIGN                0
 #define XGXSBLK8_TXLNSWAP2_TX0_ANA_LNSWAP_SEL_BITS                 2
 #define XGXSBLK8_TXLNSWAP2_TX0_ANA_LNSWAP_SEL_SHIFT                0
 
 
 /****************************************************************************
  * XgxsBlk8 :: rxLnSwap1
  */
 /* XgxsBlk8 :: rxLnSwap1 :: reserved_for_eco0 [15:08] */
 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_MASK                  0xff00
 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_ALIGN                 0
 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_BITS                  8
 #define XGXSBLK8_RXLNSWAP1_RESERVED_FOR_ECO0_SHIFT                 8
 
 /* XgxsBlk8 :: rxLnSwap1 :: rx3_lnswap_sel [07:06] */
 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_MASK                     0x00c0
 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_ALIGN                    0
 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_BITS                     2
 #define XGXSBLK8_RXLNSWAP1_RX3_LNSWAP_SEL_SHIFT                    6
 
 /* XgxsBlk8 :: rxLnSwap1 :: rx2_lnswap_sel [05:04] */
 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_MASK                     0x0030
 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_ALIGN                    0
 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_BITS                     2
 #define XGXSBLK8_RXLNSWAP1_RX2_LNSWAP_SEL_SHIFT                    4
 
 /* XgxsBlk8 :: rxLnSwap1 :: rx1_lnswap_sel [03:02] */
 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_MASK                     0x000c
 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_ALIGN                    0
 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_BITS                     2
 #define XGXSBLK8_RXLNSWAP1_RX1_LNSWAP_SEL_SHIFT                    2
 
 /* XgxsBlk8 :: rxLnSwap1 :: rx0_lnswap_sel [01:00] */
 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_MASK                     0x0003
 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_ALIGN                    0
 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_BITS                     2
 #define XGXSBLK8_RXLNSWAP1_RX0_LNSWAP_SEL_SHIFT                    0
 
 
 /****************************************************************************
  * XgxsBlk8 :: rxLnSwap2
  */
 /* XgxsBlk8 :: rxLnSwap2 :: reserved_for_eco0 [15:09] */
 #define XGXSBLK8_RXLNSWAP2_RESERVED_FOR_ECO0_MASK                  0xfe00
 #define XGXSBLK8_RXLNSWAP2_RESERVED_FOR_ECO0_ALIGN                 0
 #define XGXSBLK8_RXLNSWAP2_RESERVED_FOR_ECO0_BITS                  7
 #define XGXSBLK8_RXLNSWAP2_RESERVED_FOR_ECO0_SHIFT                 9
 
 /* XgxsBlk8 :: rxLnSwap2 :: force_rx_dig_lnswap_sel [08:08] */
 #define XGXSBLK8_RXLNSWAP2_FORCE_RX_DIG_LNSWAP_SEL_MASK            0x0100
 #define XGXSBLK8_RXLNSWAP2_FORCE_RX_DIG_LNSWAP_SEL_ALIGN           0
 #define XGXSBLK8_RXLNSWAP2_FORCE_RX_DIG_LNSWAP_SEL_BITS            1
 #define XGXSBLK8_RXLNSWAP2_FORCE_RX_DIG_LNSWAP_SEL_SHIFT           8
 
 /* XgxsBlk8 :: rxLnSwap2 :: rx3_dig_lnswap_sel [07:06] */
 #define XGXSBLK8_RXLNSWAP2_RX3_DIG_LNSWAP_SEL_MASK                 0x00c0
 #define XGXSBLK8_RXLNSWAP2_RX3_DIG_LNSWAP_SEL_ALIGN                0
 #define XGXSBLK8_RXLNSWAP2_RX3_DIG_LNSWAP_SEL_BITS                 2
 #define XGXSBLK8_RXLNSWAP2_RX3_DIG_LNSWAP_SEL_SHIFT                6
 
 /* XgxsBlk8 :: rxLnSwap2 :: rx2_dig_lnswap_sel [05:04] */
 #define XGXSBLK8_RXLNSWAP2_RX2_DIG_LNSWAP_SEL_MASK                 0x0030
 #define XGXSBLK8_RXLNSWAP2_RX2_DIG_LNSWAP_SEL_ALIGN                0
 #define XGXSBLK8_RXLNSWAP2_RX2_DIG_LNSWAP_SEL_BITS                 2
 #define XGXSBLK8_RXLNSWAP2_RX2_DIG_LNSWAP_SEL_SHIFT                4
 
 /* XgxsBlk8 :: rxLnSwap2 :: rx1_dig_lnswap_sel [03:02] */
 #define XGXSBLK8_RXLNSWAP2_RX1_DIG_LNSWAP_SEL_MASK                 0x000c
 #define XGXSBLK8_RXLNSWAP2_RX1_DIG_LNSWAP_SEL_ALIGN                0
 #define XGXSBLK8_RXLNSWAP2_RX1_DIG_LNSWAP_SEL_BITS                 2
 #define XGXSBLK8_RXLNSWAP2_RX1_DIG_LNSWAP_SEL_SHIFT                2
 
 /* XgxsBlk8 :: rxLnSwap2 :: rx0_dig_lnswap_sel [01:00] */
 #define XGXSBLK8_RXLNSWAP2_RX0_DIG_LNSWAP_SEL_MASK                 0x0003
 #define XGXSBLK8_RXLNSWAP2_RX0_DIG_LNSWAP_SEL_ALIGN                0
 #define XGXSBLK8_RXLNSWAP2_RX0_DIG_LNSWAP_SEL_BITS                 2
 #define XGXSBLK8_RXLNSWAP2_RX0_DIG_LNSWAP_SEL_SHIFT                0
 
 
 /****************************************************************************
  * XgxsBlk8 :: temp_sensor1
  */
 /* XgxsBlk8 :: temp_sensor1 :: reserved0 [15:03] */
 #define XGXSBLK8_TEMP_SENSOR1_RESERVED0_MASK                       0xfff8
 #define XGXSBLK8_TEMP_SENSOR1_RESERVED0_ALIGN                      0
 #define XGXSBLK8_TEMP_SENSOR1_RESERVED0_BITS                       13
 #define XGXSBLK8_TEMP_SENSOR1_RESERVED0_SHIFT                      3
 
 /* XgxsBlk8 :: temp_sensor1 :: temp_sensor_resetb [02:02] */
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_RESETB_MASK              0x0004
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_RESETB_ALIGN             0
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_RESETB_BITS              1
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_RESETB_SHIFT             2
 
 /* XgxsBlk8 :: temp_sensor1 :: temp_sensor_pwrdn [01:01] */
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_PWRDN_MASK               0x0002
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_PWRDN_ALIGN              0
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_PWRDN_BITS               1
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_PWRDN_SHIFT              1
 
 /* XgxsBlk8 :: temp_sensor1 :: temp_sensor_bg_pwrdn [00:00] */
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_BG_PWRDN_MASK            0x0001
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_BG_PWRDN_ALIGN           0
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_BG_PWRDN_BITS            1
 #define XGXSBLK8_TEMP_SENSOR1_TEMP_SENSOR_BG_PWRDN_SHIFT           0
 
 
 /****************************************************************************
  * XgxsBlk8 :: temp_sensor2
  */
 /* XgxsBlk8 :: temp_sensor2 :: temp_sensor_control [15:00] */
 #define XGXSBLK8_TEMP_SENSOR2_TEMP_SENSOR_CONTROL_MASK             0xffff
 #define XGXSBLK8_TEMP_SENSOR2_TEMP_SENSOR_CONTROL_ALIGN            0
 #define XGXSBLK8_TEMP_SENSOR2_TEMP_SENSOR_CONTROL_BITS             16
 #define XGXSBLK8_TEMP_SENSOR2_TEMP_SENSOR_CONTROL_SHIFT            0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk9
  */
 /****************************************************************************
  * XgxsBlk9 :: R2_control
  */
 /* XgxsBlk9 :: R2_control :: R2_rloop_en [15:15] */
 #define XGXSBLK9_R2_CONTROL_R2_RLOOP_EN_MASK                       0x8000
 #define XGXSBLK9_R2_CONTROL_R2_RLOOP_EN_ALIGN                      0
 #define XGXSBLK9_R2_CONTROL_R2_RLOOP_EN_BITS                       1
 #define XGXSBLK9_R2_CONTROL_R2_RLOOP_EN_SHIFT                      15
 
 /* XgxsBlk9 :: R2_control :: btf_cnt_max_SM [14:10] */
 #define XGXSBLK9_R2_CONTROL_BTF_CNT_MAX_SM_MASK                    0x7c00
 #define XGXSBLK9_R2_CONTROL_BTF_CNT_MAX_SM_ALIGN                   0
 #define XGXSBLK9_R2_CONTROL_BTF_CNT_MAX_SM_BITS                    5
 #define XGXSBLK9_R2_CONTROL_BTF_CNT_MAX_SM_SHIFT                   10
 
 /* XgxsBlk9 :: R2_control :: btf_invalid_cnt_max_SM [09:05] */
 #define XGXSBLK9_R2_CONTROL_BTF_INVALID_CNT_MAX_SM_MASK            0x03e0
 #define XGXSBLK9_R2_CONTROL_BTF_INVALID_CNT_MAX_SM_ALIGN           0
 #define XGXSBLK9_R2_CONTROL_BTF_INVALID_CNT_MAX_SM_BITS            5
 #define XGXSBLK9_R2_CONTROL_BTF_INVALID_CNT_MAX_SM_SHIFT           5
 
 /* XgxsBlk9 :: R2_control :: rx66_R2_tstsel [04:01] */
 #define XGXSBLK9_R2_CONTROL_RX66_R2_TSTSEL_MASK                    0x001e
 #define XGXSBLK9_R2_CONTROL_RX66_R2_TSTSEL_ALIGN                   0
 #define XGXSBLK9_R2_CONTROL_RX66_R2_TSTSEL_BITS                    4
 #define XGXSBLK9_R2_CONTROL_RX66_R2_TSTSEL_SHIFT                   1
 
 /* XgxsBlk9 :: R2_control :: rx66_R2_deskew_en [00:00] */
 #define XGXSBLK9_R2_CONTROL_RX66_R2_DESKEW_EN_MASK                 0x0001
 #define XGXSBLK9_R2_CONTROL_RX66_R2_DESKEW_EN_ALIGN                0
 #define XGXSBLK9_R2_CONTROL_RX66_R2_DESKEW_EN_BITS                 1
 #define XGXSBLK9_R2_CONTROL_RX66_R2_DESKEW_EN_SHIFT                0
 
 
 /****************************************************************************
  * XgxsBlk9 :: R2_status
  */
 /* XgxsBlk9 :: R2_status :: reserved_for_eco0 [15:06] */
 #define XGXSBLK9_R2_STATUS_RESERVED_FOR_ECO0_MASK                  0xffc0
 #define XGXSBLK9_R2_STATUS_RESERVED_FOR_ECO0_ALIGN                 0
 #define XGXSBLK9_R2_STATUS_RESERVED_FOR_ECO0_BITS                  10
 #define XGXSBLK9_R2_STATUS_RESERVED_FOR_ECO0_SHIFT                 6
 
 /* XgxsBlk9 :: R2_status :: rx66_R2_frame_lock_1_lost [05:05] */
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_LOST_MASK          0x0020
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_LOST_ALIGN         0
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_LOST_BITS          1
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_LOST_SHIFT         5
 
 /* XgxsBlk9 :: R2_status :: rx66_R2_frame_lock_0_lost [04:04] */
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_LOST_MASK          0x0010
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_LOST_ALIGN         0
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_LOST_BITS          1
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_LOST_SHIFT         4
 
 /* XgxsBlk9 :: R2_status :: rx66_R2_deskew_lock_lost [03:03] */
 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_LOST_MASK           0x0008
 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_LOST_ALIGN          0
 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_LOST_BITS           1
 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_LOST_SHIFT          3
 
 /* XgxsBlk9 :: R2_status :: rx66_R2_frame_lock_1 [02:02] */
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_MASK               0x0004
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_ALIGN              0
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_BITS               1
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_1_SHIFT              2
 
 /* XgxsBlk9 :: R2_status :: rx66_R2_frame_lock_0 [01:01] */
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_MASK               0x0002
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_ALIGN              0
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_BITS               1
 #define XGXSBLK9_R2_STATUS_RX66_R2_FRAME_LOCK_0_SHIFT              1
 
 /* XgxsBlk9 :: R2_status :: rx66_R2_deskew_lock [00:00] */
 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_MASK                0x0001
 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_ALIGN               0
 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_BITS                1
 #define XGXSBLK9_R2_STATUS_RX66_R2_DESKEW_LOCK_SHIFT               0
 
 
 /****************************************************************************
  * XgxsBlk9 :: R2_deskew_control
  */
 /* XgxsBlk9 :: R2_deskew_control :: reserved_for_eco0 [15:08] */
 #define XGXSBLK9_R2_DESKEW_CONTROL_RESERVED_FOR_ECO0_MASK          0xff00
 #define XGXSBLK9_R2_DESKEW_CONTROL_RESERVED_FOR_ECO0_ALIGN         0
 #define XGXSBLK9_R2_DESKEW_CONTROL_RESERVED_FOR_ECO0_BITS          8
 #define XGXSBLK9_R2_DESKEW_CONTROL_RESERVED_FOR_ECO0_SHIFT         8
 
 /* XgxsBlk9 :: R2_deskew_control :: R2_link_block_lock_cya [07:07] */
 #define XGXSBLK9_R2_DESKEW_CONTROL_R2_LINK_BLOCK_LOCK_CYA_MASK     0x0080
 #define XGXSBLK9_R2_DESKEW_CONTROL_R2_LINK_BLOCK_LOCK_CYA_ALIGN    0
 #define XGXSBLK9_R2_DESKEW_CONTROL_R2_LINK_BLOCK_LOCK_CYA_BITS     1
 #define XGXSBLK9_R2_DESKEW_CONTROL_R2_LINK_BLOCK_LOCK_CYA_SHIFT    7
 
 /* XgxsBlk9 :: R2_deskew_control :: xgxsBlk9_mdio_R2_mode_strap [06:06] */
 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_MODE_STRAP_MASK 0x0040
 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_MODE_STRAP_ALIGN 0
 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_MODE_STRAP_BITS 1
 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_MODE_STRAP_SHIFT 6
 
 /* XgxsBlk9 :: R2_deskew_control :: xgxsBlk9_mdio_R2_deskew_ovr [05:00] */
 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_DESKEW_OVR_MASK 0x003f
 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_DESKEW_OVR_ALIGN 0
 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_DESKEW_OVR_BITS 6
 #define XGXSBLK9_R2_DESKEW_CONTROL_XGXSBLK9_MDIO_R2_DESKEW_OVR_SHIFT 0
 
 
 /****************************************************************************
  * Warpcore_USER_XgxsBlk10
  */
 /****************************************************************************
  * XgxsBlk10 :: tx_pi_control4
  */
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_sm_enable_override [15:15] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_MASK     0x8000
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_ALIGN    0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_BITS     1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_SHIFT    15
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_sm_enable_override_value [14:14] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_MASK 0x4000
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_ALIGN 0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_BITS 1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_SHIFT 14
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_cdr_lkdt_override [13:13] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_MASK      0x2000
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_ALIGN     0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_BITS      1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_SHIFT     13
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_cdr_lkdt_override_value [12:12] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_MASK 0x1000
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_ALIGN 0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_BITS 1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_SHIFT 12
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_halfSpd_override_ctl [11:11] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_MASK   0x0800
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_ALIGN  0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_BITS   1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_SHIFT  11
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_halfSpd_ctl [10:10] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_MASK            0x0400
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_ALIGN           0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_BITS            1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_SHIFT           10
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_loopback_mode_override_ctl [09:09] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_MASK 0x0200
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_ALIGN 0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_BITS 1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_SHIFT 9
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_loopback_mode_ctl [08:08] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_MASK      0x0100
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_ALIGN     0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_BITS      1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_SHIFT     8
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_status3_mux_sel [07:06] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_MASK        0x00c0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_ALIGN       0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_BITS        2
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_SHIFT       6
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_status_latch [05:05] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_MASK           0x0020
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_ALIGN          0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_BITS           1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_SHIFT          5
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_prop_bypass [04:04] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_MASK            0x0010
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_ALIGN           0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_BITS            1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_SHIFT           4
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_prop_gain [03:01] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_GAIN_MASK              0x000e
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_GAIN_ALIGN             0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_GAIN_BITS              3
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_GAIN_SHIFT             1
 
 /* XgxsBlk10 :: tx_pi_control4 :: tx_pi_prop_acq [00:00] */
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_ACQ_MASK               0x0001
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_ACQ_ALIGN              0
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_ACQ_BITS               1
 #define XGXSBLK10_TX_PI_CONTROL4_TX_PI_PROP_ACQ_SHIFT              0
 
 
 /****************************************************************************
  * XgxsBlk10 :: xfi_afe_ctl1
  */
 /* XgxsBlk10 :: xfi_afe_ctl1 :: xfi_afe_ctl1 [15:00] */
 #define XGXSBLK10_XFI_AFE_CTL1_XFI_AFE_CTL1_MASK                   0xffff
 #define XGXSBLK10_XFI_AFE_CTL1_XFI_AFE_CTL1_ALIGN                  0
 #define XGXSBLK10_XFI_AFE_CTL1_XFI_AFE_CTL1_BITS                   16
 #define XGXSBLK10_XFI_AFE_CTL1_XFI_AFE_CTL1_SHIFT                  0
 
 
 /****************************************************************************
  * XgxsBlk10 :: xfi_afe_ctl2
  */
 /* XgxsBlk10 :: xfi_afe_ctl2 :: xfi_afe_ctl2 [15:00] */
 #define XGXSBLK10_XFI_AFE_CTL2_XFI_AFE_CTL2_MASK                   0xffff
 #define XGXSBLK10_XFI_AFE_CTL2_XFI_AFE_CTL2_ALIGN                  0
 #define XGXSBLK10_XFI_AFE_CTL2_XFI_AFE_CTL2_BITS                   16
 #define XGXSBLK10_XFI_AFE_CTL2_XFI_AFE_CTL2_SHIFT                  0
 
 
 /****************************************************************************
  * XgxsBlk10 :: xfi_afe_acjval
  */
 /* XgxsBlk10 :: xfi_afe_acjval :: xfi_afe_acjval [15:00] */
 #define XGXSBLK10_XFI_AFE_ACJVAL_XFI_AFE_ACJVAL_MASK               0xffff
 #define XGXSBLK10_XFI_AFE_ACJVAL_XFI_AFE_ACJVAL_ALIGN              0
 #define XGXSBLK10_XFI_AFE_ACJVAL_XFI_AFE_ACJVAL_BITS               16
 #define XGXSBLK10_XFI_AFE_ACJVAL_XFI_AFE_ACJVAL_SHIFT              0
 
 
 /****************************************************************************
  * XgxsBlk10 :: tx_pi_status3
  */
 /* XgxsBlk10 :: tx_pi_status3 :: tx_pi_phase_ctrl [15:00] */
 #define XGXSBLK10_TX_PI_STATUS3_TX_PI_PHASE_CTRL_MASK              0xffff
 #define XGXSBLK10_TX_PI_STATUS3_TX_PI_PHASE_CTRL_ALIGN             0
 #define XGXSBLK10_TX_PI_STATUS3_TX_PI_PHASE_CTRL_BITS              16
 #define XGXSBLK10_TX_PI_STATUS3_TX_PI_PHASE_CTRL_SHIFT             0
 
 
 /****************************************************************************
  * XgxsBlk10 :: tx_pi_status4
  */
 /* XgxsBlk10 :: tx_pi_status4 :: reserved_for_eco0 [15:02] */
 #define XGXSBLK10_TX_PI_STATUS4_RESERVED_FOR_ECO0_MASK             0xfffc
 #define XGXSBLK10_TX_PI_STATUS4_RESERVED_FOR_ECO0_ALIGN            0
 #define XGXSBLK10_TX_PI_STATUS4_RESERVED_FOR_ECO0_BITS             14
 #define XGXSBLK10_TX_PI_STATUS4_RESERVED_FOR_ECO0_SHIFT            2
 
 /* XgxsBlk10 :: tx_pi_status4 :: tx_pi_sm_en [01:01] */
 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_EN_MASK                   0x0002
 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_EN_ALIGN                  0
 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_EN_BITS                   1
 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_EN_SHIFT                  1
 
 /* XgxsBlk10 :: tx_pi_status4 :: tx_pi_sm_done [00:00] */
 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_DONE_MASK                 0x0001
 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_DONE_ALIGN                0
 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_DONE_BITS                 1
 #define XGXSBLK10_TX_PI_STATUS4_TX_PI_SM_DONE_SHIFT                0
 
 
 /****************************************************************************
  * XgxsBlk10 :: tx_pi_control5
  */
 /* XgxsBlk10 :: tx_pi_control5 :: reserved_for_eco0 [15:01] */
 #define XGXSBLK10_TX_PI_CONTROL5_RESERVED_FOR_ECO0_MASK            0xfffe
 #define XGXSBLK10_TX_PI_CONTROL5_RESERVED_FOR_ECO0_ALIGN           0
 #define XGXSBLK10_TX_PI_CONTROL5_RESERVED_FOR_ECO0_BITS            15
 #define XGXSBLK10_TX_PI_CONTROL5_RESERVED_FOR_ECO0_SHIFT           1
 
 /* XgxsBlk10 :: tx_pi_control5 :: tx_pi_sm_rst [00:00] */
 #define XGXSBLK10_TX_PI_CONTROL5_TX_PI_SM_RST_MASK                 0x0001
 #define XGXSBLK10_TX_PI_CONTROL5_TX_PI_SM_RST_ALIGN                0
 #define XGXSBLK10_TX_PI_CONTROL5_TX_PI_SM_RST_BITS                 1
 #define XGXSBLK10_TX_PI_CONTROL5_TX_PI_SM_RST_SHIFT                0
 
 
 /****************************************************************************
  * Warpcore_USER_GP2_reg
  */
 /****************************************************************************
  * GP2_reg :: GP2_0
  */
 /* GP2_reg :: GP2_0 :: pll_mode [15:12] */
 #define GP2_REG_GP2_0_PLL_MODE_MASK                                0xf000
 #define GP2_REG_GP2_0_PLL_MODE_ALIGN                               0
 #define GP2_REG_GP2_0_PLL_MODE_BITS                                4
 #define GP2_REG_GP2_0_PLL_MODE_SHIFT                               12
 
 /* GP2_reg :: GP2_0 :: sigdet [11:08] */
 #define GP2_REG_GP2_0_SIGDET_MASK                                  0x0f00
 #define GP2_REG_GP2_0_SIGDET_ALIGN                                 0
 #define GP2_REG_GP2_0_SIGDET_BITS                                  4
 #define GP2_REG_GP2_0_SIGDET_SHIFT                                 8
 
 /* GP2_reg :: GP2_0 :: pll_lock_1g [07:04] */
 #define GP2_REG_GP2_0_PLL_LOCK_1G_MASK                             0x00f0
 #define GP2_REG_GP2_0_PLL_LOCK_1G_ALIGN                            0
 #define GP2_REG_GP2_0_PLL_LOCK_1G_BITS                             4
 #define GP2_REG_GP2_0_PLL_LOCK_1G_SHIFT                            4
 
 /* GP2_reg :: GP2_0 :: sync_status_combo [03:00] */
 #define GP2_REG_GP2_0_SYNC_STATUS_COMBO_MASK                       0x000f
 #define GP2_REG_GP2_0_SYNC_STATUS_COMBO_ALIGN                      0
 #define GP2_REG_GP2_0_SYNC_STATUS_COMBO_BITS                       4
 #define GP2_REG_GP2_0_SYNC_STATUS_COMBO_SHIFT                      0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_1
  */
 /* GP2_reg :: GP2_1 :: link_KR [15:12] */
 #define GP2_REG_GP2_1_LINK_KR_MASK                                 0xf000
 #define GP2_REG_GP2_1_LINK_KR_ALIGN                                0
 #define GP2_REG_GP2_1_LINK_KR_BITS                                 4
 #define GP2_REG_GP2_1_LINK_KR_SHIFT                                12
 
 /* GP2_reg :: GP2_1 :: link_status [11:08] */
 #define GP2_REG_GP2_1_LINK_STATUS_MASK                             0x0f00
 #define GP2_REG_GP2_1_LINK_STATUS_ALIGN                            0
 #define GP2_REG_GP2_1_LINK_STATUS_BITS                             4
 #define GP2_REG_GP2_1_LINK_STATUS_SHIFT                            8
 
 /* GP2_reg :: GP2_1 :: link_100fx [07:04] */
 #define GP2_REG_GP2_1_LINK_100FX_MASK                              0x00f0
 #define GP2_REG_GP2_1_LINK_100FX_ALIGN                             0
 #define GP2_REG_GP2_1_LINK_100FX_BITS                              4
 #define GP2_REG_GP2_1_LINK_100FX_SHIFT                             4
 
 /* GP2_reg :: GP2_1 :: link_an [03:00] */
 #define GP2_REG_GP2_1_LINK_AN_MASK                                 0x000f
 #define GP2_REG_GP2_1_LINK_AN_ALIGN                                0
 #define GP2_REG_GP2_1_LINK_AN_BITS                                 4
 #define GP2_REG_GP2_1_LINK_AN_SHIFT                                0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_2
  */
 /* GP2_reg :: GP2_2 :: reserved0 [15:14] */
 #define GP2_REG_GP2_2_RESERVED0_MASK                               0xc000
 #define GP2_REG_GP2_2_RESERVED0_ALIGN                              0
 #define GP2_REG_GP2_2_RESERVED0_BITS                               2
 #define GP2_REG_GP2_2_RESERVED0_SHIFT                              14
 
 /* GP2_reg :: GP2_2 :: actual_speed_ln1 [13:08] */
 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_MASK                        0x3f00
 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_ALIGN                       0
 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_BITS                        6
 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN1_SHIFT                       8
 
 /* GP2_reg :: GP2_2 :: reserved1 [07:06] */
 #define GP2_REG_GP2_2_RESERVED1_MASK                               0x00c0
 #define GP2_REG_GP2_2_RESERVED1_ALIGN                              0
 #define GP2_REG_GP2_2_RESERVED1_BITS                               2
 #define GP2_REG_GP2_2_RESERVED1_SHIFT                              6
 
 /* GP2_reg :: GP2_2 :: actual_speed_ln0 [05:00] */
 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_MASK                        0x003f
 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_ALIGN                       0
 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_BITS                        6
 #define GP2_REG_GP2_2_ACTUAL_SPEED_LN0_SHIFT                       0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_3
  */
 /* GP2_reg :: GP2_3 :: reserved0 [15:14] */
 #define GP2_REG_GP2_3_RESERVED0_MASK                               0xc000
 #define GP2_REG_GP2_3_RESERVED0_ALIGN                              0
 #define GP2_REG_GP2_3_RESERVED0_BITS                               2
 #define GP2_REG_GP2_3_RESERVED0_SHIFT                              14
 
 /* GP2_reg :: GP2_3 :: actual_speed_ln3 [13:08] */
 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_MASK                        0x3f00
 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_ALIGN                       0
 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_BITS                        6
 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN3_SHIFT                       8
 
 /* GP2_reg :: GP2_3 :: reserved1 [07:06] */
 #define GP2_REG_GP2_3_RESERVED1_MASK                               0x00c0
 #define GP2_REG_GP2_3_RESERVED1_ALIGN                              0
 #define GP2_REG_GP2_3_RESERVED1_BITS                               2
 #define GP2_REG_GP2_3_RESERVED1_SHIFT                              6
 
 /* GP2_reg :: GP2_3 :: actual_speed_ln2 [05:00] */
 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_MASK                        0x003f
 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_ALIGN                       0
 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_BITS                        6
 #define GP2_REG_GP2_3_ACTUAL_SPEED_LN2_SHIFT                       0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_4
  */
 /* GP2_reg :: GP2_4 :: cl73_autoneg_complete [15:12] */
 #define GP2_REG_GP2_4_CL73_AUTONEG_COMPLETE_MASK                   0xf000
 #define GP2_REG_GP2_4_CL73_AUTONEG_COMPLETE_ALIGN                  0
 #define GP2_REG_GP2_4_CL73_AUTONEG_COMPLETE_BITS                   4
 #define GP2_REG_GP2_4_CL73_AUTONEG_COMPLETE_SHIFT                  12
 
 /* GP2_reg :: GP2_4 :: autoneg_complete [11:08] */
 #define GP2_REG_GP2_4_AUTONEG_COMPLETE_MASK                        0x0f00
 #define GP2_REG_GP2_4_AUTONEG_COMPLETE_ALIGN                       0
 #define GP2_REG_GP2_4_AUTONEG_COMPLETE_BITS                        4
 #define GP2_REG_GP2_4_AUTONEG_COMPLETE_SHIFT                       8
 
 /* GP2_reg :: GP2_4 :: cl73_mr_lp_autoneg_able [07:04] */
 #define GP2_REG_GP2_4_CL73_MR_LP_AUTONEG_ABLE_MASK                 0x00f0
 #define GP2_REG_GP2_4_CL73_MR_LP_AUTONEG_ABLE_ALIGN                0
 #define GP2_REG_GP2_4_CL73_MR_LP_AUTONEG_ABLE_BITS                 4
 #define GP2_REG_GP2_4_CL73_MR_LP_AUTONEG_ABLE_SHIFT                4
 
 /* GP2_reg :: GP2_4 :: cl73_mr_autoneg_able [03:00] */
 #define GP2_REG_GP2_4_CL73_MR_AUTONEG_ABLE_MASK                    0x000f
 #define GP2_REG_GP2_4_CL73_MR_AUTONEG_ABLE_ALIGN                   0
 #define GP2_REG_GP2_4_CL73_MR_AUTONEG_ABLE_BITS                    4
 #define GP2_REG_GP2_4_CL73_MR_AUTONEG_ABLE_SHIFT                   0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_5
  */
 /* GP2_reg :: GP2_5 :: Cl73_BAMStat1_ln0 [15:00] */
 #define GP2_REG_GP2_5_CL73_BAMSTAT1_LN0_MASK                       0xffff
 #define GP2_REG_GP2_5_CL73_BAMSTAT1_LN0_ALIGN                      0
 #define GP2_REG_GP2_5_CL73_BAMSTAT1_LN0_BITS                       16
 #define GP2_REG_GP2_5_CL73_BAMSTAT1_LN0_SHIFT                      0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_6
  */
 /* GP2_reg :: GP2_6 :: Cl73_BAMStat2_ln0 [15:00] */
 #define GP2_REG_GP2_6_CL73_BAMSTAT2_LN0_MASK                       0xffff
 #define GP2_REG_GP2_6_CL73_BAMSTAT2_LN0_ALIGN                      0
 #define GP2_REG_GP2_6_CL73_BAMSTAT2_LN0_BITS                       16
 #define GP2_REG_GP2_6_CL73_BAMSTAT2_LN0_SHIFT                      0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_7
  */
 /* GP2_reg :: GP2_7 :: Cl73_BAMStat3_ln0 [15:00] */
 #define GP2_REG_GP2_7_CL73_BAMSTAT3_LN0_MASK                       0xffff
 #define GP2_REG_GP2_7_CL73_BAMSTAT3_LN0_ALIGN                      0
 #define GP2_REG_GP2_7_CL73_BAMSTAT3_LN0_BITS                       16
 #define GP2_REG_GP2_7_CL73_BAMSTAT3_LN0_SHIFT                      0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_8
  */
 /* GP2_reg :: GP2_8 :: reserved0 [15:09] */
 #define GP2_REG_GP2_8_RESERVED0_MASK                               0xfe00
 #define GP2_REG_GP2_8_RESERVED0_ALIGN                              0
 #define GP2_REG_GP2_8_RESERVED0_BITS                               7
 #define GP2_REG_GP2_8_RESERVED0_SHIFT                              9
 
 /* GP2_reg :: GP2_8 :: micro_init_done [08:08] */
 #define GP2_REG_GP2_8_MICRO_INIT_DONE_MASK                         0x0100
 #define GP2_REG_GP2_8_MICRO_INIT_DONE_ALIGN                        0
 #define GP2_REG_GP2_8_MICRO_INIT_DONE_BITS                         1
 #define GP2_REG_GP2_8_MICRO_INIT_DONE_SHIFT                        8
 
 /* GP2_reg :: GP2_8 :: micro_fsm [07:04] */
 #define GP2_REG_GP2_8_MICRO_FSM_MASK                               0x00f0
 #define GP2_REG_GP2_8_MICRO_FSM_ALIGN                              0
 #define GP2_REG_GP2_8_MICRO_FSM_BITS                               4
 #define GP2_REG_GP2_8_MICRO_FSM_SHIFT                              4
 
 /* GP2_reg :: GP2_8 :: micro_err [03:02] */
 #define GP2_REG_GP2_8_MICRO_ERR_MASK                               0x000c
 #define GP2_REG_GP2_8_MICRO_ERR_ALIGN                              0
 #define GP2_REG_GP2_8_MICRO_ERR_BITS                               2
 #define GP2_REG_GP2_8_MICRO_ERR_SHIFT                              2
 
 /* GP2_reg :: GP2_8 :: micro_wdog [01:00] */
 #define GP2_REG_GP2_8_MICRO_WDOG_MASK                              0x0003
 #define GP2_REG_GP2_8_MICRO_WDOG_ALIGN                             0
 #define GP2_REG_GP2_8_MICRO_WDOG_BITS                              2
 #define GP2_REG_GP2_8_MICRO_WDOG_SHIFT                             0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_9
  */
 /* GP2_reg :: GP2_9 :: prbs_lock_ln0 [15:15] */
 #define GP2_REG_GP2_9_PRBS_LOCK_LN0_MASK                           0x8000
 #define GP2_REG_GP2_9_PRBS_LOCK_LN0_ALIGN                          0
 #define GP2_REG_GP2_9_PRBS_LOCK_LN0_BITS                           1
 #define GP2_REG_GP2_9_PRBS_LOCK_LN0_SHIFT                          15
 
 /* GP2_reg :: GP2_9 :: tx0_fir_tap_main [14:09] */
 #define GP2_REG_GP2_9_TX0_FIR_TAP_MAIN_MASK                        0x7e00
 #define GP2_REG_GP2_9_TX0_FIR_TAP_MAIN_ALIGN                       0
 #define GP2_REG_GP2_9_TX0_FIR_TAP_MAIN_BITS                        6
 #define GP2_REG_GP2_9_TX0_FIR_TAP_MAIN_SHIFT                       9
 
 /* GP2_reg :: GP2_9 :: tx0_fir_tap_pre [08:05] */
 #define GP2_REG_GP2_9_TX0_FIR_TAP_PRE_MASK                         0x01e0
 #define GP2_REG_GP2_9_TX0_FIR_TAP_PRE_ALIGN                        0
 #define GP2_REG_GP2_9_TX0_FIR_TAP_PRE_BITS                         4
 #define GP2_REG_GP2_9_TX0_FIR_TAP_PRE_SHIFT                        5
 
 /* GP2_reg :: GP2_9 :: tx0_fir_tap_post [04:00] */
 #define GP2_REG_GP2_9_TX0_FIR_TAP_POST_MASK                        0x001f
 #define GP2_REG_GP2_9_TX0_FIR_TAP_POST_ALIGN                       0
 #define GP2_REG_GP2_9_TX0_FIR_TAP_POST_BITS                        5
 #define GP2_REG_GP2_9_TX0_FIR_TAP_POST_SHIFT                       0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_A
  */
 /* GP2_reg :: GP2_A :: prbs_lock_ln1 [15:15] */
 #define GP2_REG_GP2_A_PRBS_LOCK_LN1_MASK                           0x8000
 #define GP2_REG_GP2_A_PRBS_LOCK_LN1_ALIGN                          0
 #define GP2_REG_GP2_A_PRBS_LOCK_LN1_BITS                           1
 #define GP2_REG_GP2_A_PRBS_LOCK_LN1_SHIFT                          15
 
 /* GP2_reg :: GP2_A :: tx1_fir_tap_main [14:09] */
 #define GP2_REG_GP2_A_TX1_FIR_TAP_MAIN_MASK                        0x7e00
 #define GP2_REG_GP2_A_TX1_FIR_TAP_MAIN_ALIGN                       0
 #define GP2_REG_GP2_A_TX1_FIR_TAP_MAIN_BITS                        6
 #define GP2_REG_GP2_A_TX1_FIR_TAP_MAIN_SHIFT                       9
 
 /* GP2_reg :: GP2_A :: tx1_fir_tap_pre [08:05] */
 #define GP2_REG_GP2_A_TX1_FIR_TAP_PRE_MASK                         0x01e0
 #define GP2_REG_GP2_A_TX1_FIR_TAP_PRE_ALIGN                        0
 #define GP2_REG_GP2_A_TX1_FIR_TAP_PRE_BITS                         4
 #define GP2_REG_GP2_A_TX1_FIR_TAP_PRE_SHIFT                        5
 
 /* GP2_reg :: GP2_A :: tx1_fir_tap_post [04:00] */
 #define GP2_REG_GP2_A_TX1_FIR_TAP_POST_MASK                        0x001f
 #define GP2_REG_GP2_A_TX1_FIR_TAP_POST_ALIGN                       0
 #define GP2_REG_GP2_A_TX1_FIR_TAP_POST_BITS                        5
 #define GP2_REG_GP2_A_TX1_FIR_TAP_POST_SHIFT                       0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_B
  */
 /* GP2_reg :: GP2_B :: prbs_lock_ln2 [15:15] */
 #define GP2_REG_GP2_B_PRBS_LOCK_LN2_MASK                           0x8000
 #define GP2_REG_GP2_B_PRBS_LOCK_LN2_ALIGN                          0
 #define GP2_REG_GP2_B_PRBS_LOCK_LN2_BITS                           1
 #define GP2_REG_GP2_B_PRBS_LOCK_LN2_SHIFT                          15
 
 /* GP2_reg :: GP2_B :: tx2_fir_tap_main [14:09] */
 #define GP2_REG_GP2_B_TX2_FIR_TAP_MAIN_MASK                        0x7e00
 #define GP2_REG_GP2_B_TX2_FIR_TAP_MAIN_ALIGN                       0
 #define GP2_REG_GP2_B_TX2_FIR_TAP_MAIN_BITS                        6
 #define GP2_REG_GP2_B_TX2_FIR_TAP_MAIN_SHIFT                       9
 
 /* GP2_reg :: GP2_B :: tx2_fir_tap_pre [08:05] */
 #define GP2_REG_GP2_B_TX2_FIR_TAP_PRE_MASK                         0x01e0
 #define GP2_REG_GP2_B_TX2_FIR_TAP_PRE_ALIGN                        0
 #define GP2_REG_GP2_B_TX2_FIR_TAP_PRE_BITS                         4
 #define GP2_REG_GP2_B_TX2_FIR_TAP_PRE_SHIFT                        5
 
 /* GP2_reg :: GP2_B :: tx2_fir_tap_post [04:00] */
 #define GP2_REG_GP2_B_TX2_FIR_TAP_POST_MASK                        0x001f
 #define GP2_REG_GP2_B_TX2_FIR_TAP_POST_ALIGN                       0
 #define GP2_REG_GP2_B_TX2_FIR_TAP_POST_BITS                        5
 #define GP2_REG_GP2_B_TX2_FIR_TAP_POST_SHIFT                       0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_C
  */
 /* GP2_reg :: GP2_C :: prbs_lock_ln3 [15:15] */
 #define GP2_REG_GP2_C_PRBS_LOCK_LN3_MASK                           0x8000
 #define GP2_REG_GP2_C_PRBS_LOCK_LN3_ALIGN                          0
 #define GP2_REG_GP2_C_PRBS_LOCK_LN3_BITS                           1
 #define GP2_REG_GP2_C_PRBS_LOCK_LN3_SHIFT                          15
 
 /* GP2_reg :: GP2_C :: tx3_fir_tap_main [14:09] */
 #define GP2_REG_GP2_C_TX3_FIR_TAP_MAIN_MASK                        0x7e00
 #define GP2_REG_GP2_C_TX3_FIR_TAP_MAIN_ALIGN                       0
 #define GP2_REG_GP2_C_TX3_FIR_TAP_MAIN_BITS                        6
 #define GP2_REG_GP2_C_TX3_FIR_TAP_MAIN_SHIFT                       9
 
 /* GP2_reg :: GP2_C :: tx3_fir_tap_pre [08:05] */
 #define GP2_REG_GP2_C_TX3_FIR_TAP_PRE_MASK                         0x01e0
 #define GP2_REG_GP2_C_TX3_FIR_TAP_PRE_ALIGN                        0
 #define GP2_REG_GP2_C_TX3_FIR_TAP_PRE_BITS                         4
 #define GP2_REG_GP2_C_TX3_FIR_TAP_PRE_SHIFT                        5
 
 /* GP2_reg :: GP2_C :: tx3_fir_tap_post [04:00] */
 #define GP2_REG_GP2_C_TX3_FIR_TAP_POST_MASK                        0x001f
 #define GP2_REG_GP2_C_TX3_FIR_TAP_POST_ALIGN                       0
 #define GP2_REG_GP2_C_TX3_FIR_TAP_POST_BITS                        5
 #define GP2_REG_GP2_C_TX3_FIR_TAP_POST_SHIFT                       0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_D
  */
 /* GP2_reg :: GP2_D :: reserved0 [15:08] */
 #define GP2_REG_GP2_D_RESERVED0_MASK                               0xff00
 #define GP2_REG_GP2_D_RESERVED0_ALIGN                              0
 #define GP2_REG_GP2_D_RESERVED0_BITS                               8
 #define GP2_REG_GP2_D_RESERVED0_SHIFT                              8
 
 /* GP2_reg :: GP2_D :: rx_LPI_rcvd [07:04] */
 #define GP2_REG_GP2_D_RX_LPI_RCVD_MASK                             0x00f0
 #define GP2_REG_GP2_D_RX_LPI_RCVD_ALIGN                            0
 #define GP2_REG_GP2_D_RX_LPI_RCVD_BITS                             4
 #define GP2_REG_GP2_D_RX_LPI_RCVD_SHIFT                            4
 
 /* GP2_reg :: GP2_D :: tx_LPI_rcvd [03:00] */
 #define GP2_REG_GP2_D_TX_LPI_RCVD_MASK                             0x000f
 #define GP2_REG_GP2_D_TX_LPI_RCVD_ALIGN                            0
 #define GP2_REG_GP2_D_TX_LPI_RCVD_BITS                             4
 #define GP2_REG_GP2_D_TX_LPI_RCVD_SHIFT                            0
 
 
 /****************************************************************************
  * GP2_reg :: GP2_E
  */
 /* GP2_reg :: GP2_E :: cl49_en [15:12] */
 #define GP2_REG_GP2_E_CL49_EN_MASK                                 0xf000
 #define GP2_REG_GP2_E_CL49_EN_ALIGN                                0
 #define GP2_REG_GP2_E_CL49_EN_BITS                                 4
 #define GP2_REG_GP2_E_CL49_EN_SHIFT                                12
 
 /* GP2_reg :: GP2_E :: ed66en [11:08] */
 #define GP2_REG_GP2_E_ED66EN_MASK                                  0x0f00
 #define GP2_REG_GP2_E_ED66EN_ALIGN                                 0
 #define GP2_REG_GP2_E_ED66EN_BITS                                  4
 #define GP2_REG_GP2_E_ED66EN_SHIFT                                 8
 
 /* GP2_reg :: GP2_E :: fec_enable [07:04] */
 #define GP2_REG_GP2_E_FEC_ENABLE_MASK                              0x00f0
 #define GP2_REG_GP2_E_FEC_ENABLE_ALIGN                             0
 #define GP2_REG_GP2_E_FEC_ENABLE_BITS                              4
 #define GP2_REG_GP2_E_FEC_ENABLE_SHIFT                             4
 
 /* GP2_reg :: GP2_E :: fec_signal_Ok [03:00] */
 #define GP2_REG_GP2_E_FEC_SIGNAL_OK_MASK                           0x000f
 #define GP2_REG_GP2_E_FEC_SIGNAL_OK_ALIGN                          0
 #define GP2_REG_GP2_E_FEC_SIGNAL_OK_BITS                           4
 #define GP2_REG_GP2_E_FEC_SIGNAL_OK_SHIFT                          0
 
 
 /****************************************************************************
  * Warpcore_USER_uC_info_B0
  */
 /****************************************************************************
  * uC_info_B0 :: state_debug_ln0
  */
 /* uC_info_B0 :: state_debug_ln0 :: CDR_LOCK_CORR [15:15] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_CORR_MASK              0x8000
 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_CORR_ALIGN             0
 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_CORR_BITS              1
 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_CORR_SHIFT             15
 
 /* uC_info_B0 :: state_debug_ln0 :: DSC_DONE [14:14] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_DSC_DONE_MASK                   0x4000
 #define UC_INFO_B0_STATE_DEBUG_LN0_DSC_DONE_ALIGN                  0
 #define UC_INFO_B0_STATE_DEBUG_LN0_DSC_DONE_BITS                   1
 #define UC_INFO_B0_STATE_DEBUG_LN0_DSC_DONE_SHIFT                  14
 
 /* uC_info_B0 :: state_debug_ln0 :: TUNING_DONE [13:13] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_TUNING_DONE_MASK                0x2000
 #define UC_INFO_B0_STATE_DEBUG_LN0_TUNING_DONE_ALIGN               0
 #define UC_INFO_B0_STATE_DEBUG_LN0_TUNING_DONE_BITS                1
 #define UC_INFO_B0_STATE_DEBUG_LN0_TUNING_DONE_SHIFT               13
 
 /* uC_info_B0 :: state_debug_ln0 :: KR4_DIV16CK_BCST [12:12] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_MASK           0x1000
 #define UC_INFO_B0_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_ALIGN          0
 #define UC_INFO_B0_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_BITS           1
 #define UC_INFO_B0_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_SHIFT          12
 
 /* uC_info_B0 :: state_debug_ln0 :: DCD_DFE_TUNING [11:11] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_DCD_DFE_TUNING_MASK             0x0800
 #define UC_INFO_B0_STATE_DEBUG_LN0_DCD_DFE_TUNING_ALIGN            0
 #define UC_INFO_B0_STATE_DEBUG_LN0_DCD_DFE_TUNING_BITS             1
 #define UC_INFO_B0_STATE_DEBUG_LN0_DCD_DFE_TUNING_SHIFT            11
 
 /* uC_info_B0 :: state_debug_ln0 :: OSDFE_P1_TUNING [10:10] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_OSDFE_P1_TUNING_MASK            0x0400
 #define UC_INFO_B0_STATE_DEBUG_LN0_OSDFE_P1_TUNING_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN0_OSDFE_P1_TUNING_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN0_OSDFE_P1_TUNING_SHIFT           10
 
 /* uC_info_B0 :: state_debug_ln0 :: SLICER_OFFSET_TUNING [09:09] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_MASK       0x0200
 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_ALIGN      0
 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_BITS       1
 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_SHIFT      9
 
 /* uC_info_B0 :: state_debug_ln0 :: CL72_REMOTE_TUNING [08:08] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_MASK         0x0100
 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_ALIGN        0
 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_BITS         1
 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_SHIFT        8
 
 /* uC_info_B0 :: state_debug_ln0 :: CL72_TUNING [07:07] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_TUNING_MASK                0x0080
 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_TUNING_ALIGN               0
 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_TUNING_BITS                1
 #define UC_INFO_B0_STATE_DEBUG_LN0_CL72_TUNING_SHIFT               7
 
 /* uC_info_B0 :: state_debug_ln0 :: SLICER_TARGET_TUNING [06:06] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_MASK       0x0040
 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_ALIGN      0
 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_BITS       1
 #define UC_INFO_B0_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_SHIFT      6
 
 /* uC_info_B0 :: state_debug_ln0 :: VGA_BIAS_TUNING [05:05] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_VGA_BIAS_TUNING_MASK            0x0020
 #define UC_INFO_B0_STATE_DEBUG_LN0_VGA_BIAS_TUNING_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN0_VGA_BIAS_TUNING_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN0_VGA_BIAS_TUNING_SHIFT           5
 
 /* uC_info_B0 :: state_debug_ln0 :: PF_TUNING [04:04] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_PF_TUNING_MASK                  0x0010
 #define UC_INFO_B0_STATE_DEBUG_LN0_PF_TUNING_ALIGN                 0
 #define UC_INFO_B0_STATE_DEBUG_LN0_PF_TUNING_BITS                  1
 #define UC_INFO_B0_STATE_DEBUG_LN0_PF_TUNING_SHIFT                 4
 
 /* uC_info_B0 :: state_debug_ln0 :: CLK90_OFFSET_TUNING [03:03] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_MASK        0x0008
 #define UC_INFO_B0_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_ALIGN       0
 #define UC_INFO_B0_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_BITS        1
 #define UC_INFO_B0_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_SHIFT       3
 
 /* uC_info_B0 :: state_debug_ln0 :: OS_VGA_TUNING [02:02] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_OS_VGA_TUNING_MASK              0x0004
 #define UC_INFO_B0_STATE_DEBUG_LN0_OS_VGA_TUNING_ALIGN             0
 #define UC_INFO_B0_STATE_DEBUG_LN0_OS_VGA_TUNING_BITS              1
 #define UC_INFO_B0_STATE_DEBUG_LN0_OS_VGA_TUNING_SHIFT             2
 
 /* uC_info_B0 :: state_debug_ln0 :: DFE_TAPS_2_5_EN [01:01] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_MASK            0x0002
 #define UC_INFO_B0_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_SHIFT           1
 
 /* uC_info_B0 :: state_debug_ln0 :: CDR_LOCK [00:00] */
 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_MASK                   0x0001
 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_ALIGN                  0
 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_BITS                   1
 #define UC_INFO_B0_STATE_DEBUG_LN0_CDR_LOCK_SHIFT                  0
 
 
 /****************************************************************************
  * uC_info_B0 :: state_debug_ln1
  */
 /* uC_info_B0 :: state_debug_ln1 :: CDR_LOCK_CORR [15:15] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_CORR_MASK              0x8000
 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_CORR_ALIGN             0
 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_CORR_BITS              1
 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_CORR_SHIFT             15
 
 /* uC_info_B0 :: state_debug_ln1 :: DSC_DONE [14:14] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_DSC_DONE_MASK                   0x4000
 #define UC_INFO_B0_STATE_DEBUG_LN1_DSC_DONE_ALIGN                  0
 #define UC_INFO_B0_STATE_DEBUG_LN1_DSC_DONE_BITS                   1
 #define UC_INFO_B0_STATE_DEBUG_LN1_DSC_DONE_SHIFT                  14
 
 /* uC_info_B0 :: state_debug_ln1 :: TUNING_DONE [13:13] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_TUNING_DONE_MASK                0x2000
 #define UC_INFO_B0_STATE_DEBUG_LN1_TUNING_DONE_ALIGN               0
 #define UC_INFO_B0_STATE_DEBUG_LN1_TUNING_DONE_BITS                1
 #define UC_INFO_B0_STATE_DEBUG_LN1_TUNING_DONE_SHIFT               13
 
 /* uC_info_B0 :: state_debug_ln1 :: KR4_DIV16CK_BCST [12:12] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_MASK           0x1000
 #define UC_INFO_B0_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_ALIGN          0
 #define UC_INFO_B0_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_BITS           1
 #define UC_INFO_B0_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_SHIFT          12
 
 /* uC_info_B0 :: state_debug_ln1 :: DCD_DFE_TUNING [11:11] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_DCD_DFE_TUNING_MASK             0x0800
 #define UC_INFO_B0_STATE_DEBUG_LN1_DCD_DFE_TUNING_ALIGN            0
 #define UC_INFO_B0_STATE_DEBUG_LN1_DCD_DFE_TUNING_BITS             1
 #define UC_INFO_B0_STATE_DEBUG_LN1_DCD_DFE_TUNING_SHIFT            11
 
 /* uC_info_B0 :: state_debug_ln1 :: OSDFE_P1_TUNING [10:10] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_OSDFE_P1_TUNING_MASK            0x0400
 #define UC_INFO_B0_STATE_DEBUG_LN1_OSDFE_P1_TUNING_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN1_OSDFE_P1_TUNING_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN1_OSDFE_P1_TUNING_SHIFT           10
 
 /* uC_info_B0 :: state_debug_ln1 :: SLICER_OFFSET_TUNING [09:09] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_MASK       0x0200
 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_ALIGN      0
 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_BITS       1
 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_SHIFT      9
 
 /* uC_info_B0 :: state_debug_ln1 :: CL72_REMOTE_TUNING [08:08] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_MASK         0x0100
 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_ALIGN        0
 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_BITS         1
 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_SHIFT        8
 
 /* uC_info_B0 :: state_debug_ln1 :: CL72_TUNING [07:07] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_TUNING_MASK                0x0080
 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_TUNING_ALIGN               0
 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_TUNING_BITS                1
 #define UC_INFO_B0_STATE_DEBUG_LN1_CL72_TUNING_SHIFT               7
 
 /* uC_info_B0 :: state_debug_ln1 :: SLICER_TARGET_TUNING [06:06] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_MASK       0x0040
 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_ALIGN      0
 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_BITS       1
 #define UC_INFO_B0_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_SHIFT      6
 
 /* uC_info_B0 :: state_debug_ln1 :: VGA_BIAS_TUNING [05:05] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_VGA_BIAS_TUNING_MASK            0x0020
 #define UC_INFO_B0_STATE_DEBUG_LN1_VGA_BIAS_TUNING_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN1_VGA_BIAS_TUNING_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN1_VGA_BIAS_TUNING_SHIFT           5
 
 /* uC_info_B0 :: state_debug_ln1 :: PF_TUNING [04:04] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_PF_TUNING_MASK                  0x0010
 #define UC_INFO_B0_STATE_DEBUG_LN1_PF_TUNING_ALIGN                 0
 #define UC_INFO_B0_STATE_DEBUG_LN1_PF_TUNING_BITS                  1
 #define UC_INFO_B0_STATE_DEBUG_LN1_PF_TUNING_SHIFT                 4
 
 /* uC_info_B0 :: state_debug_ln1 :: CLK90_OFFSET_TUNING [03:03] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_MASK        0x0008
 #define UC_INFO_B0_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_ALIGN       0
 #define UC_INFO_B0_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_BITS        1
 #define UC_INFO_B0_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_SHIFT       3
 
 /* uC_info_B0 :: state_debug_ln1 :: OS_VGA_TUNING [02:02] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_OS_VGA_TUNING_MASK              0x0004
 #define UC_INFO_B0_STATE_DEBUG_LN1_OS_VGA_TUNING_ALIGN             0
 #define UC_INFO_B0_STATE_DEBUG_LN1_OS_VGA_TUNING_BITS              1
 #define UC_INFO_B0_STATE_DEBUG_LN1_OS_VGA_TUNING_SHIFT             2
 
 /* uC_info_B0 :: state_debug_ln1 :: DFE_TAPS_2_5_EN [01:01] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_MASK            0x0002
 #define UC_INFO_B0_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_SHIFT           1
 
 /* uC_info_B0 :: state_debug_ln1 :: CDR_LOCK [00:00] */
 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_MASK                   0x0001
 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_ALIGN                  0
 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_BITS                   1
 #define UC_INFO_B0_STATE_DEBUG_LN1_CDR_LOCK_SHIFT                  0
 
 
 /****************************************************************************
  * uC_info_B0 :: state_debug_ln2
  */
 /* uC_info_B0 :: state_debug_ln2 :: CDR_LOCK_CORR [15:15] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_CORR_MASK              0x8000
 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_CORR_ALIGN             0
 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_CORR_BITS              1
 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_CORR_SHIFT             15
 
 /* uC_info_B0 :: state_debug_ln2 :: DSC_DONE [14:14] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_DSC_DONE_MASK                   0x4000
 #define UC_INFO_B0_STATE_DEBUG_LN2_DSC_DONE_ALIGN                  0
 #define UC_INFO_B0_STATE_DEBUG_LN2_DSC_DONE_BITS                   1
 #define UC_INFO_B0_STATE_DEBUG_LN2_DSC_DONE_SHIFT                  14
 
 /* uC_info_B0 :: state_debug_ln2 :: TUNING_DONE [13:13] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_TUNING_DONE_MASK                0x2000
 #define UC_INFO_B0_STATE_DEBUG_LN2_TUNING_DONE_ALIGN               0
 #define UC_INFO_B0_STATE_DEBUG_LN2_TUNING_DONE_BITS                1
 #define UC_INFO_B0_STATE_DEBUG_LN2_TUNING_DONE_SHIFT               13
 
 /* uC_info_B0 :: state_debug_ln2 :: KR4_DIV16CK_BCST [12:12] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_MASK           0x1000
 #define UC_INFO_B0_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_ALIGN          0
 #define UC_INFO_B0_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_BITS           1
 #define UC_INFO_B0_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_SHIFT          12
 
 /* uC_info_B0 :: state_debug_ln2 :: DCD_DFE_TUNING [11:11] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_DCD_DFE_TUNING_MASK             0x0800
 #define UC_INFO_B0_STATE_DEBUG_LN2_DCD_DFE_TUNING_ALIGN            0
 #define UC_INFO_B0_STATE_DEBUG_LN2_DCD_DFE_TUNING_BITS             1
 #define UC_INFO_B0_STATE_DEBUG_LN2_DCD_DFE_TUNING_SHIFT            11
 
 /* uC_info_B0 :: state_debug_ln2 :: OSDFE_P1_TUNING [10:10] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_OSDFE_P1_TUNING_MASK            0x0400
 #define UC_INFO_B0_STATE_DEBUG_LN2_OSDFE_P1_TUNING_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN2_OSDFE_P1_TUNING_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN2_OSDFE_P1_TUNING_SHIFT           10
 
 /* uC_info_B0 :: state_debug_ln2 :: SLICER_OFFSET_TUNING [09:09] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_MASK       0x0200
 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_ALIGN      0
 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_BITS       1
 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_SHIFT      9
 
 /* uC_info_B0 :: state_debug_ln2 :: CL72_REMOTE_TUNING [08:08] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_MASK         0x0100
 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_ALIGN        0
 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_BITS         1
 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_SHIFT        8
 
 /* uC_info_B0 :: state_debug_ln2 :: CL72_TUNING [07:07] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_TUNING_MASK                0x0080
 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_TUNING_ALIGN               0
 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_TUNING_BITS                1
 #define UC_INFO_B0_STATE_DEBUG_LN2_CL72_TUNING_SHIFT               7
 
 /* uC_info_B0 :: state_debug_ln2 :: SLICER_TARGET_TUNING [06:06] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_MASK       0x0040
 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_ALIGN      0
 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_BITS       1
 #define UC_INFO_B0_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_SHIFT      6
 
 /* uC_info_B0 :: state_debug_ln2 :: VGA_BIAS_TUNING [05:05] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_VGA_BIAS_TUNING_MASK            0x0020
 #define UC_INFO_B0_STATE_DEBUG_LN2_VGA_BIAS_TUNING_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN2_VGA_BIAS_TUNING_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN2_VGA_BIAS_TUNING_SHIFT           5
 
 /* uC_info_B0 :: state_debug_ln2 :: PF_TUNING [04:04] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_PF_TUNING_MASK                  0x0010
 #define UC_INFO_B0_STATE_DEBUG_LN2_PF_TUNING_ALIGN                 0
 #define UC_INFO_B0_STATE_DEBUG_LN2_PF_TUNING_BITS                  1
 #define UC_INFO_B0_STATE_DEBUG_LN2_PF_TUNING_SHIFT                 4
 
 /* uC_info_B0 :: state_debug_ln2 :: CLK90_OFFSET_TUNING [03:03] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_MASK        0x0008
 #define UC_INFO_B0_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_ALIGN       0
 #define UC_INFO_B0_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_BITS        1
 #define UC_INFO_B0_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_SHIFT       3
 
 /* uC_info_B0 :: state_debug_ln2 :: OS_VGA_TUNING [02:02] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_OS_VGA_TUNING_MASK              0x0004
 #define UC_INFO_B0_STATE_DEBUG_LN2_OS_VGA_TUNING_ALIGN             0
 #define UC_INFO_B0_STATE_DEBUG_LN2_OS_VGA_TUNING_BITS              1
 #define UC_INFO_B0_STATE_DEBUG_LN2_OS_VGA_TUNING_SHIFT             2
 
 /* uC_info_B0 :: state_debug_ln2 :: DFE_TAPS_2_5_EN [01:01] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_MASK            0x0002
 #define UC_INFO_B0_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_SHIFT           1
 
 /* uC_info_B0 :: state_debug_ln2 :: CDR_LOCK [00:00] */
 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_MASK                   0x0001
 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_ALIGN                  0
 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_BITS                   1
 #define UC_INFO_B0_STATE_DEBUG_LN2_CDR_LOCK_SHIFT                  0
 
 
 /****************************************************************************
  * uC_info_B0 :: state_debug_ln3
  */
 /* uC_info_B0 :: state_debug_ln3 :: CDR_LOCK_CORR [15:15] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_CORR_MASK              0x8000
 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_CORR_ALIGN             0
 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_CORR_BITS              1
 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_CORR_SHIFT             15
 
 /* uC_info_B0 :: state_debug_ln3 :: DSC_DONE [14:14] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_DSC_DONE_MASK                   0x4000
 #define UC_INFO_B0_STATE_DEBUG_LN3_DSC_DONE_ALIGN                  0
 #define UC_INFO_B0_STATE_DEBUG_LN3_DSC_DONE_BITS                   1
 #define UC_INFO_B0_STATE_DEBUG_LN3_DSC_DONE_SHIFT                  14
 
 /* uC_info_B0 :: state_debug_ln3 :: TUNING_DONE [13:13] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_TUNING_DONE_MASK                0x2000
 #define UC_INFO_B0_STATE_DEBUG_LN3_TUNING_DONE_ALIGN               0
 #define UC_INFO_B0_STATE_DEBUG_LN3_TUNING_DONE_BITS                1
 #define UC_INFO_B0_STATE_DEBUG_LN3_TUNING_DONE_SHIFT               13
 
 /* uC_info_B0 :: state_debug_ln3 :: KR4_DIV16CK_BCST [12:12] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_MASK           0x1000
 #define UC_INFO_B0_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_ALIGN          0
 #define UC_INFO_B0_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_BITS           1
 #define UC_INFO_B0_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_SHIFT          12
 
 /* uC_info_B0 :: state_debug_ln3 :: DCD_DFE_TUNING [11:11] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_DCD_DFE_TUNING_MASK             0x0800
 #define UC_INFO_B0_STATE_DEBUG_LN3_DCD_DFE_TUNING_ALIGN            0
 #define UC_INFO_B0_STATE_DEBUG_LN3_DCD_DFE_TUNING_BITS             1
 #define UC_INFO_B0_STATE_DEBUG_LN3_DCD_DFE_TUNING_SHIFT            11
 
 /* uC_info_B0 :: state_debug_ln3 :: OSDFE_P1_TUNING [10:10] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_OSDFE_P1_TUNING_MASK            0x0400
 #define UC_INFO_B0_STATE_DEBUG_LN3_OSDFE_P1_TUNING_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN3_OSDFE_P1_TUNING_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN3_OSDFE_P1_TUNING_SHIFT           10
 
 /* uC_info_B0 :: state_debug_ln3 :: SLICER_OFFSET_TUNING [09:09] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_MASK       0x0200
 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_ALIGN      0
 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_BITS       1
 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_SHIFT      9
 
 /* uC_info_B0 :: state_debug_ln3 :: CL72_REMOTE_TUNING [08:08] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_MASK         0x0100
 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_ALIGN        0
 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_BITS         1
 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_SHIFT        8
 
 /* uC_info_B0 :: state_debug_ln3 :: CL72_TUNING [07:07] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_TUNING_MASK                0x0080
 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_TUNING_ALIGN               0
 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_TUNING_BITS                1
 #define UC_INFO_B0_STATE_DEBUG_LN3_CL72_TUNING_SHIFT               7
 
 /* uC_info_B0 :: state_debug_ln3 :: SLICER_TARGET_TUNING [06:06] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_MASK       0x0040
 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_ALIGN      0
 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_BITS       1
 #define UC_INFO_B0_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_SHIFT      6
 
 /* uC_info_B0 :: state_debug_ln3 :: VGA_BIAS_TUNING [05:05] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_VGA_BIAS_TUNING_MASK            0x0020
 #define UC_INFO_B0_STATE_DEBUG_LN3_VGA_BIAS_TUNING_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN3_VGA_BIAS_TUNING_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN3_VGA_BIAS_TUNING_SHIFT           5
 
 /* uC_info_B0 :: state_debug_ln3 :: PF_TUNING [04:04] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_PF_TUNING_MASK                  0x0010
 #define UC_INFO_B0_STATE_DEBUG_LN3_PF_TUNING_ALIGN                 0
 #define UC_INFO_B0_STATE_DEBUG_LN3_PF_TUNING_BITS                  1
 #define UC_INFO_B0_STATE_DEBUG_LN3_PF_TUNING_SHIFT                 4
 
 /* uC_info_B0 :: state_debug_ln3 :: CLK90_OFFSET_TUNING [03:03] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_MASK        0x0008
 #define UC_INFO_B0_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_ALIGN       0
 #define UC_INFO_B0_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_BITS        1
 #define UC_INFO_B0_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_SHIFT       3
 
 /* uC_info_B0 :: state_debug_ln3 :: OS_VGA_TUNING [02:02] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_OS_VGA_TUNING_MASK              0x0004
 #define UC_INFO_B0_STATE_DEBUG_LN3_OS_VGA_TUNING_ALIGN             0
 #define UC_INFO_B0_STATE_DEBUG_LN3_OS_VGA_TUNING_BITS              1
 #define UC_INFO_B0_STATE_DEBUG_LN3_OS_VGA_TUNING_SHIFT             2
 
 /* uC_info_B0 :: state_debug_ln3 :: DFE_TAPS_2_5_EN [01:01] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_MASK            0x0002
 #define UC_INFO_B0_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_ALIGN           0
 #define UC_INFO_B0_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_BITS            1
 #define UC_INFO_B0_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_SHIFT           1
 
 /* uC_info_B0 :: state_debug_ln3 :: CDR_LOCK [00:00] */
 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_MASK                   0x0001
 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_ALIGN                  0
 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_BITS                   1
 #define UC_INFO_B0_STATE_DEBUG_LN3_CDR_LOCK_SHIFT                  0
 
 
 /****************************************************************************
  * uC_info_B0 :: speed_debug_ln0
  */
 /* uC_info_B0 :: speed_debug_ln0 :: LOS_counter [15:12] */
 #define UC_INFO_B0_SPEED_DEBUG_LN0_LOS_COUNTER_MASK                0xf000
 #define UC_INFO_B0_SPEED_DEBUG_LN0_LOS_COUNTER_ALIGN               0
 #define UC_INFO_B0_SPEED_DEBUG_LN0_LOS_COUNTER_BITS                4
 #define UC_INFO_B0_SPEED_DEBUG_LN0_LOS_COUNTER_SHIFT               12
 
 /* uC_info_B0 :: speed_debug_ln0 :: need_br_dfe [11:11] */
 #define UC_INFO_B0_SPEED_DEBUG_LN0_NEED_BR_DFE_MASK                0x0800
 #define UC_INFO_B0_SPEED_DEBUG_LN0_NEED_BR_DFE_ALIGN               0
 #define UC_INFO_B0_SPEED_DEBUG_LN0_NEED_BR_DFE_BITS                1
 #define UC_INFO_B0_SPEED_DEBUG_LN0_NEED_BR_DFE_SHIFT               11
 
 /* uC_info_B0 :: speed_debug_ln0 :: br_dfe_enabled [10:10] */
 #define UC_INFO_B0_SPEED_DEBUG_LN0_BR_DFE_ENABLED_MASK             0x0400
 #define UC_INFO_B0_SPEED_DEBUG_LN0_BR_DFE_ENABLED_ALIGN            0
 #define UC_INFO_B0_SPEED_DEBUG_LN0_BR_DFE_ENABLED_BITS             1
 #define UC_INFO_B0_SPEED_DEBUG_LN0_BR_DFE_ENABLED_SHIFT            10
 
 /* uC_info_B0 :: speed_debug_ln0 :: os_dfe_enabled [09:09] */
 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_DFE_ENABLED_MASK             0x0200
 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_DFE_ENABLED_ALIGN            0
 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_DFE_ENABLED_BITS             1
 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_DFE_ENABLED_SHIFT            9
 
 /* uC_info_B0 :: speed_debug_ln0 :: os_enabled [08:08] */
 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_ENABLED_MASK                 0x0100
 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_ENABLED_ALIGN                0
 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_ENABLED_BITS                 1
 #define UC_INFO_B0_SPEED_DEBUG_LN0_OS_ENABLED_SHIFT                8
 
 /* uC_info_B0 :: speed_debug_ln0 :: actual_speed [07:00] */
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_MASK               0x00ff
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_ALIGN              0
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_BITS               8
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_SHIFT              0
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10M             0
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_100M            1
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_1G              2
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_2p5G            3
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_5G_X4           4
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_6G_X4           5
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_HiG         6
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_CX4         7
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_12G_HiG         8
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_12p5G_X4        9
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_13G_X4          10
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_15G_X4          11
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_16G_X4          12
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_1G_KX           13
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_KX4         14
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_KR          15
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_5G              16
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_6p4G            17
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_20G_X4          18
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_21G_X4          19
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_25G_X4          20
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_HiG_DXGXS   21
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_DXGXS       22
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10p5G_HiG_DXGXS 23
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10p5G_DXGXS     24
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_12p773G_HiG_DXGXS 25
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_12p773G_DXGXS   26
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_XFI         27
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_40G             28
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_20G_HiG_DXGXS   29
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_20G_DXGXS       30
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_SFI         31
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_31p5G           32
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_32p7G           33
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_20G_SCR         34
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_HiG_DXGXS_SCR 35
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_DXGXS_SCR   36
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_12G_R2          37
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_10G_X2          38
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_40G_KR4         39
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_40G_CR4         40
 #define UC_INFO_B0_SPEED_DEBUG_LN0_ACTUAL_SPEED_dr_100G_CR10       41
 
 
 /****************************************************************************
  * uC_info_B0 :: speed_debug_ln1
  */
 /* uC_info_B0 :: speed_debug_ln1 :: LOS_counter [15:12] */
 #define UC_INFO_B0_SPEED_DEBUG_LN1_LOS_COUNTER_MASK                0xf000
 #define UC_INFO_B0_SPEED_DEBUG_LN1_LOS_COUNTER_ALIGN               0
 #define UC_INFO_B0_SPEED_DEBUG_LN1_LOS_COUNTER_BITS                4
 #define UC_INFO_B0_SPEED_DEBUG_LN1_LOS_COUNTER_SHIFT               12
 
 /* uC_info_B0 :: speed_debug_ln1 :: need_br_dfe [11:11] */
 #define UC_INFO_B0_SPEED_DEBUG_LN1_NEED_BR_DFE_MASK                0x0800
 #define UC_INFO_B0_SPEED_DEBUG_LN1_NEED_BR_DFE_ALIGN               0
 #define UC_INFO_B0_SPEED_DEBUG_LN1_NEED_BR_DFE_BITS                1
 #define UC_INFO_B0_SPEED_DEBUG_LN1_NEED_BR_DFE_SHIFT               11
 
 /* uC_info_B0 :: speed_debug_ln1 :: br_dfe_enabled [10:10] */
 #define UC_INFO_B0_SPEED_DEBUG_LN1_BR_DFE_ENABLED_MASK             0x0400
 #define UC_INFO_B0_SPEED_DEBUG_LN1_BR_DFE_ENABLED_ALIGN            0
 #define UC_INFO_B0_SPEED_DEBUG_LN1_BR_DFE_ENABLED_BITS             1
 #define UC_INFO_B0_SPEED_DEBUG_LN1_BR_DFE_ENABLED_SHIFT            10
 
 /* uC_info_B0 :: speed_debug_ln1 :: os_dfe_enabled [09:09] */
 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_DFE_ENABLED_MASK             0x0200
 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_DFE_ENABLED_ALIGN            0
 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_DFE_ENABLED_BITS             1
 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_DFE_ENABLED_SHIFT            9
 
 /* uC_info_B0 :: speed_debug_ln1 :: os_enabled [08:08] */
 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_ENABLED_MASK                 0x0100
 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_ENABLED_ALIGN                0
 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_ENABLED_BITS                 1
 #define UC_INFO_B0_SPEED_DEBUG_LN1_OS_ENABLED_SHIFT                8
 
 /* uC_info_B0 :: speed_debug_ln1 :: actual_speed [07:00] */
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_MASK               0x00ff
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_ALIGN              0
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_BITS               8
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_SHIFT              0
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10M             0
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_100M            1
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_1G              2
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_2p5G            3
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_5G_X4           4
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_6G_X4           5
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_HiG         6
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_CX4         7
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_12G_HiG         8
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_12p5G_X4        9
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_13G_X4          10
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_15G_X4          11
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_16G_X4          12
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_1G_KX           13
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_KX4         14
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_KR          15
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_5G              16
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_6p4G            17
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_20G_X4          18
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_21G_X4          19
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_25G_X4          20
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_HiG_DXGXS   21
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_DXGXS       22
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10p5G_HiG_DXGXS 23
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10p5G_DXGXS     24
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_12p773G_HiG_DXGXS 25
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_12p773G_DXGXS   26
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_XFI         27
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_40G             28
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_20G_HiG_DXGXS   29
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_20G_DXGXS       30
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_SFI         31
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_31p5G           32
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_32p7G           33
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_20G_SCR         34
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_HiG_DXGXS_SCR 35
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_DXGXS_SCR   36
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_12G_R2          37
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_10G_X2          38
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_40G_KR4         39
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_40G_CR4         40
 #define UC_INFO_B0_SPEED_DEBUG_LN1_ACTUAL_SPEED_dr_100G_CR10       41
 
 
 /****************************************************************************
  * uC_info_B0 :: speed_debug_ln2
  */
 /* uC_info_B0 :: speed_debug_ln2 :: LOS_counter [15:12] */
 #define UC_INFO_B0_SPEED_DEBUG_LN2_LOS_COUNTER_MASK                0xf000
 #define UC_INFO_B0_SPEED_DEBUG_LN2_LOS_COUNTER_ALIGN               0
 #define UC_INFO_B0_SPEED_DEBUG_LN2_LOS_COUNTER_BITS                4
 #define UC_INFO_B0_SPEED_DEBUG_LN2_LOS_COUNTER_SHIFT               12
 
 /* uC_info_B0 :: speed_debug_ln2 :: need_br_dfe [11:11] */
 #define UC_INFO_B0_SPEED_DEBUG_LN2_NEED_BR_DFE_MASK                0x0800
 #define UC_INFO_B0_SPEED_DEBUG_LN2_NEED_BR_DFE_ALIGN               0
 #define UC_INFO_B0_SPEED_DEBUG_LN2_NEED_BR_DFE_BITS                1
 #define UC_INFO_B0_SPEED_DEBUG_LN2_NEED_BR_DFE_SHIFT               11
 
 /* uC_info_B0 :: speed_debug_ln2 :: br_dfe_enabled [10:10] */
 #define UC_INFO_B0_SPEED_DEBUG_LN2_BR_DFE_ENABLED_MASK             0x0400
 #define UC_INFO_B0_SPEED_DEBUG_LN2_BR_DFE_ENABLED_ALIGN            0
 #define UC_INFO_B0_SPEED_DEBUG_LN2_BR_DFE_ENABLED_BITS             1
 #define UC_INFO_B0_SPEED_DEBUG_LN2_BR_DFE_ENABLED_SHIFT            10
 
 /* uC_info_B0 :: speed_debug_ln2 :: os_dfe_enabled [09:09] */
 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_DFE_ENABLED_MASK             0x0200
 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_DFE_ENABLED_ALIGN            0
 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_DFE_ENABLED_BITS             1
 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_DFE_ENABLED_SHIFT            9
 
 /* uC_info_B0 :: speed_debug_ln2 :: os_enabled [08:08] */
 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_ENABLED_MASK                 0x0100
 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_ENABLED_ALIGN                0
 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_ENABLED_BITS                 1
 #define UC_INFO_B0_SPEED_DEBUG_LN2_OS_ENABLED_SHIFT                8
 
 /* uC_info_B0 :: speed_debug_ln2 :: actual_speed [07:00] */
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_MASK               0x00ff
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_ALIGN              0
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_BITS               8
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_SHIFT              0
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10M             0
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_100M            1
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_1G              2
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_2p5G            3
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_5G_X4           4
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_6G_X4           5
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_HiG         6
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_CX4         7
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_12G_HiG         8
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_12p5G_X4        9
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_13G_X4          10
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_15G_X4          11
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_16G_X4          12
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_1G_KX           13
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_KX4         14
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_KR          15
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_5G              16
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_6p4G            17
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_20G_X4          18
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_21G_X4          19
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_25G_X4          20
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_HiG_DXGXS   21
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_DXGXS       22
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10p5G_HiG_DXGXS 23
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10p5G_DXGXS     24
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_12p773G_HiG_DXGXS 25
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_12p773G_DXGXS   26
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_XFI         27
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_40G             28
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_20G_HiG_DXGXS   29
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_20G_DXGXS       30
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_SFI         31
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_31p5G           32
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_32p7G           33
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_20G_SCR         34
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_HiG_DXGXS_SCR 35
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_DXGXS_SCR   36
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_12G_R2          37
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_10G_X2          38
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_40G_KR4         39
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_40G_CR4         40
 #define UC_INFO_B0_SPEED_DEBUG_LN2_ACTUAL_SPEED_dr_100G_CR10       41
 
 
 /****************************************************************************
  * uC_info_B0 :: speed_debug_ln3
  */
 /* uC_info_B0 :: speed_debug_ln3 :: LOS_counter [15:12] */
 #define UC_INFO_B0_SPEED_DEBUG_LN3_LOS_COUNTER_MASK                0xf000
 #define UC_INFO_B0_SPEED_DEBUG_LN3_LOS_COUNTER_ALIGN               0
 #define UC_INFO_B0_SPEED_DEBUG_LN3_LOS_COUNTER_BITS                4
 #define UC_INFO_B0_SPEED_DEBUG_LN3_LOS_COUNTER_SHIFT               12
 
 /* uC_info_B0 :: speed_debug_ln3 :: need_br_dfe [11:11] */
 #define UC_INFO_B0_SPEED_DEBUG_LN3_NEED_BR_DFE_MASK                0x0800
 #define UC_INFO_B0_SPEED_DEBUG_LN3_NEED_BR_DFE_ALIGN               0
 #define UC_INFO_B0_SPEED_DEBUG_LN3_NEED_BR_DFE_BITS                1
 #define UC_INFO_B0_SPEED_DEBUG_LN3_NEED_BR_DFE_SHIFT               11
 
 /* uC_info_B0 :: speed_debug_ln3 :: br_dfe_enabled [10:10] */
 #define UC_INFO_B0_SPEED_DEBUG_LN3_BR_DFE_ENABLED_MASK             0x0400
 #define UC_INFO_B0_SPEED_DEBUG_LN3_BR_DFE_ENABLED_ALIGN            0
 #define UC_INFO_B0_SPEED_DEBUG_LN3_BR_DFE_ENABLED_BITS             1
 #define UC_INFO_B0_SPEED_DEBUG_LN3_BR_DFE_ENABLED_SHIFT            10
 
 /* uC_info_B0 :: speed_debug_ln3 :: os_dfe_enabled [09:09] */
 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_DFE_ENABLED_MASK             0x0200
 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_DFE_ENABLED_ALIGN            0
 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_DFE_ENABLED_BITS             1
 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_DFE_ENABLED_SHIFT            9
 
 /* uC_info_B0 :: speed_debug_ln3 :: os_enabled [08:08] */
 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_ENABLED_MASK                 0x0100
 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_ENABLED_ALIGN                0
 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_ENABLED_BITS                 1
 #define UC_INFO_B0_SPEED_DEBUG_LN3_OS_ENABLED_SHIFT                8
 
 /* uC_info_B0 :: speed_debug_ln3 :: actual_speed [07:00] */
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_MASK               0x00ff
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_ALIGN              0
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_BITS               8
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_SHIFT              0
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10M             0
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_100M            1
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_1G              2
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_2p5G            3
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_5G_X4           4
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_6G_X4           5
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_HiG         6
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_CX4         7
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_12G_HiG         8
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_12p5G_X4        9
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_13G_X4          10
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_15G_X4          11
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_16G_X4          12
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_1G_KX           13
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_KX4         14
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_KR          15
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_5G              16
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_6p4G            17
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_20G_X4          18
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_21G_X4          19
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_25G_X4          20
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_HiG_DXGXS   21
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_DXGXS       22
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10p5G_HiG_DXGXS 23
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10p5G_DXGXS     24
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_12p773G_HiG_DXGXS 25
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_12p773G_DXGXS   26
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_XFI         27
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_40G             28
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_20G_HiG_DXGXS   29
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_20G_DXGXS       30
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_SFI         31
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_31p5G           32
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_32p7G           33
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_20G_SCR         34
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_HiG_DXGXS_SCR 35
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_DXGXS_SCR   36
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_12G_R2          37
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_10G_X2          38
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_40G_KR4         39
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_40G_CR4         40
 #define UC_INFO_B0_SPEED_DEBUG_LN3_ACTUAL_SPEED_dr_100G_CR10       41
 
 
 /****************************************************************************
  * uC_info_B0 :: cl72_status_ln0
  */
 /* uC_info_B0 :: cl72_status_ln0 :: temp_idx [15:12] */
 #define UC_INFO_B0_CL72_STATUS_LN0_TEMP_IDX_MASK                   0xf000
 #define UC_INFO_B0_CL72_STATUS_LN0_TEMP_IDX_ALIGN                  0
 #define UC_INFO_B0_CL72_STATUS_LN0_TEMP_IDX_BITS                   4
 #define UC_INFO_B0_CL72_STATUS_LN0_TEMP_IDX_SHIFT                  12
 
 /* uC_info_B0 :: cl72_status_ln0 :: dfe_tap1 [11:06] */
 #define UC_INFO_B0_CL72_STATUS_LN0_DFE_TAP1_MASK                   0x0fc0
 #define UC_INFO_B0_CL72_STATUS_LN0_DFE_TAP1_ALIGN                  0
 #define UC_INFO_B0_CL72_STATUS_LN0_DFE_TAP1_BITS                   6
 #define UC_INFO_B0_CL72_STATUS_LN0_DFE_TAP1_SHIFT                  6
 
 /* uC_info_B0 :: cl72_status_ln0 :: vga [05:00] */
 #define UC_INFO_B0_CL72_STATUS_LN0_VGA_MASK                        0x003f
 #define UC_INFO_B0_CL72_STATUS_LN0_VGA_ALIGN                       0
 #define UC_INFO_B0_CL72_STATUS_LN0_VGA_BITS                        6
 #define UC_INFO_B0_CL72_STATUS_LN0_VGA_SHIFT                       0
 
 
 /****************************************************************************
  * uC_info_B0 :: cl72_status_ln1
  */
 /* uC_info_B0 :: cl72_status_ln1 :: temp_idx [15:12] */
 #define UC_INFO_B0_CL72_STATUS_LN1_TEMP_IDX_MASK                   0xf000
 #define UC_INFO_B0_CL72_STATUS_LN1_TEMP_IDX_ALIGN                  0
 #define UC_INFO_B0_CL72_STATUS_LN1_TEMP_IDX_BITS                   4
 #define UC_INFO_B0_CL72_STATUS_LN1_TEMP_IDX_SHIFT                  12
 
 /* uC_info_B0 :: cl72_status_ln1 :: dfe_tap1 [11:06] */
 #define UC_INFO_B0_CL72_STATUS_LN1_DFE_TAP1_MASK                   0x0fc0
 #define UC_INFO_B0_CL72_STATUS_LN1_DFE_TAP1_ALIGN                  0
 #define UC_INFO_B0_CL72_STATUS_LN1_DFE_TAP1_BITS                   6
 #define UC_INFO_B0_CL72_STATUS_LN1_DFE_TAP1_SHIFT                  6
 
 /* uC_info_B0 :: cl72_status_ln1 :: vga [05:00] */
 #define UC_INFO_B0_CL72_STATUS_LN1_VGA_MASK                        0x003f
 #define UC_INFO_B0_CL72_STATUS_LN1_VGA_ALIGN                       0
 #define UC_INFO_B0_CL72_STATUS_LN1_VGA_BITS                        6
 #define UC_INFO_B0_CL72_STATUS_LN1_VGA_SHIFT                       0
 
 
 /****************************************************************************
  * uC_info_B0 :: cl72_status_ln2
  */
 /* uC_info_B0 :: cl72_status_ln2 :: temp_idx [15:12] */
 #define UC_INFO_B0_CL72_STATUS_LN2_TEMP_IDX_MASK                   0xf000
 #define UC_INFO_B0_CL72_STATUS_LN2_TEMP_IDX_ALIGN                  0
 #define UC_INFO_B0_CL72_STATUS_LN2_TEMP_IDX_BITS                   4
 #define UC_INFO_B0_CL72_STATUS_LN2_TEMP_IDX_SHIFT                  12
 
 /* uC_info_B0 :: cl72_status_ln2 :: dfe_tap1 [11:06] */
 #define UC_INFO_B0_CL72_STATUS_LN2_DFE_TAP1_MASK                   0x0fc0
 #define UC_INFO_B0_CL72_STATUS_LN2_DFE_TAP1_ALIGN                  0
 #define UC_INFO_B0_CL72_STATUS_LN2_DFE_TAP1_BITS                   6
 #define UC_INFO_B0_CL72_STATUS_LN2_DFE_TAP1_SHIFT                  6
 
 /* uC_info_B0 :: cl72_status_ln2 :: vga [05:00] */
 #define UC_INFO_B0_CL72_STATUS_LN2_VGA_MASK                        0x003f
 #define UC_INFO_B0_CL72_STATUS_LN2_VGA_ALIGN                       0
 #define UC_INFO_B0_CL72_STATUS_LN2_VGA_BITS                        6
 #define UC_INFO_B0_CL72_STATUS_LN2_VGA_SHIFT                       0
 
 
 /****************************************************************************
  * uC_info_B0 :: cl72_status_ln3
  */
 /* uC_info_B0 :: cl72_status_ln3 :: temp_idx [15:12] */
 #define UC_INFO_B0_CL72_STATUS_LN3_TEMP_IDX_MASK                   0xf000
 #define UC_INFO_B0_CL72_STATUS_LN3_TEMP_IDX_ALIGN                  0
 #define UC_INFO_B0_CL72_STATUS_LN3_TEMP_IDX_BITS                   4
 #define UC_INFO_B0_CL72_STATUS_LN3_TEMP_IDX_SHIFT                  12
 
 /* uC_info_B0 :: cl72_status_ln3 :: dfe_tap1 [11:06] */
 #define UC_INFO_B0_CL72_STATUS_LN3_DFE_TAP1_MASK                   0x0fc0
 #define UC_INFO_B0_CL72_STATUS_LN3_DFE_TAP1_ALIGN                  0
 #define UC_INFO_B0_CL72_STATUS_LN3_DFE_TAP1_BITS                   6
 #define UC_INFO_B0_CL72_STATUS_LN3_DFE_TAP1_SHIFT                  6
 
 /* uC_info_B0 :: cl72_status_ln3 :: vga [05:00] */
 #define UC_INFO_B0_CL72_STATUS_LN3_VGA_MASK                        0x003f
 #define UC_INFO_B0_CL72_STATUS_LN3_VGA_ALIGN                       0
 #define UC_INFO_B0_CL72_STATUS_LN3_VGA_BITS                        6
 #define UC_INFO_B0_CL72_STATUS_LN3_VGA_SHIFT                       0
 
 
 /****************************************************************************
  * uC_info_B0 :: debug_reg0
  */
 /* uC_info_B0 :: debug_reg0 :: reserved_for_eco0 [15:00] */
 #define UC_INFO_B0_DEBUG_REG0_RESERVED_FOR_ECO0_MASK               0xffff
 #define UC_INFO_B0_DEBUG_REG0_RESERVED_FOR_ECO0_ALIGN              0
 #define UC_INFO_B0_DEBUG_REG0_RESERVED_FOR_ECO0_BITS               16
 #define UC_INFO_B0_DEBUG_REG0_RESERVED_FOR_ECO0_SHIFT              0
 
 
 /****************************************************************************
  * uC_info_B0 :: debug_reg1
  */
 /* uC_info_B0 :: debug_reg1 :: reserved_for_eco0 [15:00] */
 #define UC_INFO_B0_DEBUG_REG1_RESERVED_FOR_ECO0_MASK               0xffff
 #define UC_INFO_B0_DEBUG_REG1_RESERVED_FOR_ECO0_ALIGN              0
 #define UC_INFO_B0_DEBUG_REG1_RESERVED_FOR_ECO0_BITS               16
 #define UC_INFO_B0_DEBUG_REG1_RESERVED_FOR_ECO0_SHIFT              0
 
 
 /****************************************************************************
  * uC_info_B0 :: dead_trap
  */
 /* uC_info_B0 :: dead_trap :: dead_code_trap [15:15] */
 #define UC_INFO_B0_DEAD_TRAP_DEAD_CODE_TRAP_MASK                   0x8000
 #define UC_INFO_B0_DEAD_TRAP_DEAD_CODE_TRAP_ALIGN                  0
 #define UC_INFO_B0_DEAD_TRAP_DEAD_CODE_TRAP_BITS                   1
 #define UC_INFO_B0_DEAD_TRAP_DEAD_CODE_TRAP_SHIFT                  15
 
 /* uC_info_B0 :: dead_trap :: reserved_for_eco0 [14:08] */
 #define UC_INFO_B0_DEAD_TRAP_RESERVED_FOR_ECO0_MASK                0x7f00
 #define UC_INFO_B0_DEAD_TRAP_RESERVED_FOR_ECO0_ALIGN               0
 #define UC_INFO_B0_DEAD_TRAP_RESERVED_FOR_ECO0_BITS                7
 #define UC_INFO_B0_DEAD_TRAP_RESERVED_FOR_ECO0_SHIFT               8
 
 /* uC_info_B0 :: dead_trap :: micro_reset_counter [07:00] */
 #define UC_INFO_B0_DEAD_TRAP_MICRO_RESET_COUNTER_MASK              0x00ff
 #define UC_INFO_B0_DEAD_TRAP_MICRO_RESET_COUNTER_ALIGN             0
 #define UC_INFO_B0_DEAD_TRAP_MICRO_RESET_COUNTER_BITS              8
 #define UC_INFO_B0_DEAD_TRAP_MICRO_RESET_COUNTER_SHIFT             0
 
 
 /****************************************************************************
  * Warpcore_USER_uC_info_B1
  */
 /****************************************************************************
  * uC_info_B1 :: version
  */
 /* uC_info_B1 :: version :: version [15:00] */
 #define UC_INFO_B1_VERSION_VERSION_MASK                            0xffff
 #define UC_INFO_B1_VERSION_VERSION_ALIGN                           0
 #define UC_INFO_B1_VERSION_VERSION_BITS                            16
 #define UC_INFO_B1_VERSION_VERSION_SHIFT                           0
 
 
 /****************************************************************************
  * uC_info_B1 :: target
  */
 /* uC_info_B1 :: target :: target [15:00] */
 #define UC_INFO_B1_TARGET_TARGET_MASK                              0xffff
 #define UC_INFO_B1_TARGET_TARGET_ALIGN                             0
 #define UC_INFO_B1_TARGET_TARGET_BITS                              16
 #define UC_INFO_B1_TARGET_TARGET_SHIFT                             0
 
 
 /****************************************************************************
  * uC_info_B1 :: firmware_mode
  */
 /* uC_info_B1 :: firmware_mode :: LN3_mode [15:12] */
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_MASK                     0xf000
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_ALIGN                    0
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_BITS                     4
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_SHIFT                    12
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_DEFAULT                  0
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_SFP_OPT_LR               1
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_SFP_DAC                  2
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_XLAUI                    3
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_LONG_CH_6G               4
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_BR_DFE                   5
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_SW_CL72                  6
 #define UC_INFO_B1_FIRMWARE_MODE_LN3_MODE_CL72_WO_AN               7
 
 /* uC_info_B1 :: firmware_mode :: LN2_mode [11:08] */
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_MASK                     0x0f00
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_ALIGN                    0
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_BITS                     4
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_SHIFT                    8
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_DEFAULT                  0
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_SFP_OPT_LR               1
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_SFP_DAC                  2
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_XLAUI                    3
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_LONG_CH_6G               4
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_BR_DFE                   5
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_SW_CL72                  6
 #define UC_INFO_B1_FIRMWARE_MODE_LN2_MODE_CL72_WO_AN               7
 
 /* uC_info_B1 :: firmware_mode :: LN1_mode [07:04] */
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_MASK                     0x00f0
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_ALIGN                    0
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_BITS                     4
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_SHIFT                    4
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_DEFAULT                  0
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_SFP_OPT_LR               1
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_SFP_DAC                  2
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_XLAUI                    3
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_LONG_CH_6G               4
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_BR_DFE                   5
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_SW_CL72                  6
 #define UC_INFO_B1_FIRMWARE_MODE_LN1_MODE_CL72_WO_AN               7
 
 /* uC_info_B1 :: firmware_mode :: LN0_mode [03:00] */
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_MASK                     0x000f
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_ALIGN                    0
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_BITS                     4
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_SHIFT                    0
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_DEFAULT                  0
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_SFP_OPT_LR               1
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_SFP_DAC                  2
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_XLAUI                    3
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_LONG_CH_6G               4
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_BR_DFE                   5
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_SW_CL72                  6
 #define UC_INFO_B1_FIRMWARE_MODE_LN0_MODE_CL72_WO_AN               7
 
 
 /****************************************************************************
  * uC_info_B1 :: gpio_ctrl_ln0
  */
 /* uC_info_B1 :: gpio_ctrl_ln0 :: GPIO_CTRL_LN0 [15:00] */
 #define UC_INFO_B1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_MASK                0xffff
 #define UC_INFO_B1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_ALIGN               0
 #define UC_INFO_B1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_BITS                16
 #define UC_INFO_B1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_SHIFT               0
 
 
 /****************************************************************************
  * uC_info_B1 :: gpio_ctrl_ln1
  */
 /* uC_info_B1 :: gpio_ctrl_ln1 :: GPIO_CTRL_LN1 [15:00] */
 #define UC_INFO_B1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_MASK                0xffff
 #define UC_INFO_B1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_ALIGN               0
 #define UC_INFO_B1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_BITS                16
 #define UC_INFO_B1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_SHIFT               0
 
 
 /****************************************************************************
  * uC_info_B1 :: gpio_ctrl_ln2
  */
 /* uC_info_B1 :: gpio_ctrl_ln2 :: GPIO_CTRL_LN2 [15:00] */
 #define UC_INFO_B1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_MASK                0xffff
 #define UC_INFO_B1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_ALIGN               0
 #define UC_INFO_B1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_BITS                16
 #define UC_INFO_B1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_SHIFT               0
 
 
 /****************************************************************************
  * uC_info_B1 :: gpio_ctrl_ln3
  */
 /* uC_info_B1 :: gpio_ctrl_ln3 :: GPIO_CTRL_LN3 [15:00] */
 #define UC_INFO_B1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_MASK                0xffff
 #define UC_INFO_B1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_ALIGN               0
 #define UC_INFO_B1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_BITS                16
 #define UC_INFO_B1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_SHIFT               0
 
 
 /****************************************************************************
  * uC_info_B1 :: gpio_sts_ln0
  */
 /* uC_info_B1 :: gpio_sts_ln0 :: GPIO_STS_LN0 [15:00] */
 #define UC_INFO_B1_GPIO_STS_LN0_GPIO_STS_LN0_MASK                  0xffff
 #define UC_INFO_B1_GPIO_STS_LN0_GPIO_STS_LN0_ALIGN                 0
 #define UC_INFO_B1_GPIO_STS_LN0_GPIO_STS_LN0_BITS                  16
 #define UC_INFO_B1_GPIO_STS_LN0_GPIO_STS_LN0_SHIFT                 0
 
 
 /****************************************************************************
  * uC_info_B1 :: gpio_sts_ln1
  */
 /* uC_info_B1 :: gpio_sts_ln1 :: GPIO_STS_LN1 [15:00] */
 #define UC_INFO_B1_GPIO_STS_LN1_GPIO_STS_LN1_MASK                  0xffff
 #define UC_INFO_B1_GPIO_STS_LN1_GPIO_STS_LN1_ALIGN                 0
 #define UC_INFO_B1_GPIO_STS_LN1_GPIO_STS_LN1_BITS                  16
 #define UC_INFO_B1_GPIO_STS_LN1_GPIO_STS_LN1_SHIFT                 0
 
 
 /****************************************************************************
  * uC_info_B1 :: gpio_sts_ln2
  */
 /* uC_info_B1 :: gpio_sts_ln2 :: GPIO_STS_LN2 [15:00] */
 #define UC_INFO_B1_GPIO_STS_LN2_GPIO_STS_LN2_MASK                  0xffff
 #define UC_INFO_B1_GPIO_STS_LN2_GPIO_STS_LN2_ALIGN                 0
 #define UC_INFO_B1_GPIO_STS_LN2_GPIO_STS_LN2_BITS                  16
 #define UC_INFO_B1_GPIO_STS_LN2_GPIO_STS_LN2_SHIFT                 0
 
 
 /****************************************************************************
  * uC_info_B1 :: gpio_sts_ln3
  */
 /* uC_info_B1 :: gpio_sts_ln3 :: GPIO_STS_LN3 [15:00] */
 #define UC_INFO_B1_GPIO_STS_LN3_GPIO_STS_LN3_MASK                  0xffff
 #define UC_INFO_B1_GPIO_STS_LN3_GPIO_STS_LN3_ALIGN                 0
 #define UC_INFO_B1_GPIO_STS_LN3_GPIO_STS_LN3_BITS                  16
 #define UC_INFO_B1_GPIO_STS_LN3_GPIO_STS_LN3_SHIFT                 0
 
 
 /****************************************************************************
  * uC_info_B1 :: regB
  */
 /* uC_info_B1 :: regB :: reserved_for_eco0 [15:00] */
 #define UC_INFO_B1_REGB_RESERVED_FOR_ECO0_MASK                     0xffff
 #define UC_INFO_B1_REGB_RESERVED_FOR_ECO0_ALIGN                    0
 #define UC_INFO_B1_REGB_RESERVED_FOR_ECO0_BITS                     16
 #define UC_INFO_B1_REGB_RESERVED_FOR_ECO0_SHIFT                    0
 
 
 /****************************************************************************
  * uC_info_B1 :: tuning_state_bypass
  */
 /* uC_info_B1 :: tuning_state_bypass :: reserved_for_eco0 [15:09] */
 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_MASK      0xfe00
 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_ALIGN     0
 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_BITS      7
 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_SHIFT     9
 
 /* uC_info_B1 :: tuning_state_bypass :: bypass_steady_state_tuning [08:08] */
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_MASK 0x0100
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_ALIGN 0
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_BITS 1
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_SHIFT 8
 
 /* uC_info_B1 :: tuning_state_bypass :: bypass_cdr_lock_monitor [07:07] */
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_MASK 0x0080
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_ALIGN 0
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_BITS 1
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_SHIFT 7
 
 /* uC_info_B1 :: tuning_state_bypass :: bypass_dcd_tuning [06:06] */
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_MASK      0x0040
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_ALIGN     0
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_BITS      1
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_SHIFT     6
 
 /* uC_info_B1 :: tuning_state_bypass :: bypass_slicer_offset_tuning [05:05] */
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_MASK 0x0020
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_ALIGN 0
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_BITS 1
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_SHIFT 5
 
 /* uC_info_B1 :: tuning_state_bypass :: bypass_slicer_target_tuning [04:04] */
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_MASK 0x0010
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_ALIGN 0
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_BITS 1
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_SHIFT 4
 
 /* uC_info_B1 :: tuning_state_bypass :: bypass_vga_bias_tuning [03:03] */
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_MASK 0x0008
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_ALIGN 0
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_BITS 1
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_SHIFT 3
 
 /* uC_info_B1 :: tuning_state_bypass :: bypass_pf_tuning [02:02] */
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_MASK       0x0004
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_ALIGN      0
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_BITS       1
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_SHIFT      2
 
 /* uC_info_B1 :: tuning_state_bypass :: bypass_clk90_tuning [01:01] */
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_MASK    0x0002
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_ALIGN   0
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_BITS    1
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_SHIFT   1
 
 /* uC_info_B1 :: tuning_state_bypass :: bypass_os_vga_tuning [00:00] */
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_MASK   0x0001
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_ALIGN  0
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_BITS   1
 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_SHIFT  0
 
 
 /****************************************************************************
  * uC_info_B1 :: temperature
  */
 /* uC_info_B1 :: temperature :: force_temperature [15:15] */
 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_MASK              0x8000
 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_ALIGN             0
 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_BITS              1
 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_SHIFT             15
 
 /* uC_info_B1 :: temperature :: reserved_for_eco0 [14:14] */
 #define UC_INFO_B1_TEMPERATURE_RESERVED_FOR_ECO0_MASK              0x4000
 #define UC_INFO_B1_TEMPERATURE_RESERVED_FOR_ECO0_ALIGN             0
 #define UC_INFO_B1_TEMPERATURE_RESERVED_FOR_ECO0_BITS              1
 #define UC_INFO_B1_TEMPERATURE_RESERVED_FOR_ECO0_SHIFT             14
 
 /* uC_info_B1 :: temperature :: temp_idx [13:10] */
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_MASK                       0x3c00
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_ALIGN                      0
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_BITS                       4
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_SHIFT                      10
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE__22p9C                 15
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE__12p6C                 14
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE__3p0C                  13
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_6p7C                   12
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_16p4C                  11
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_26p6C                  10
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_36p3C                  9
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_46p0C                  8
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_56p2C                  7
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_65p9C                  6
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_75p6C                  5
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_85p3C                  4
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_95p5C                  3
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_105p2C                 2
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_114p9C                 1
 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_125p1C                 0
 
 /* uC_info_B1 :: temperature :: temperature [09:00] */
 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_MASK                    0x03ff
 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_ALIGN                   0
 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_BITS                    10
 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_SHIFT                   0
 
 
 /****************************************************************************
  * uC_info_B1 :: crc
  */
 /* uC_info_B1 :: crc :: crc [15:00] */
 #define UC_INFO_B1_CRC_CRC_MASK                                    0xffff
 #define UC_INFO_B1_CRC_CRC_ALIGN                                   0
 #define UC_INFO_B1_CRC_CRC_BITS                                    16
 #define UC_INFO_B1_CRC_CRC_SHIFT                                   0
 
 
 /****************************************************************************
  * Warpcore_USER_Dsc1b0
  */
 /****************************************************************************
  * Dsc1b0 :: cdr_ctrl0
  */
 /* Dsc1b0 :: cdr_ctrl0 :: cdros_xfi_integ_sat_sel [15:15] */
 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_MASK              0x8000
 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_ALIGN             0
 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_BITS              1
 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_SHIFT             15
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_m1_slicer_only [14:14] */
 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_MASK                 0x4000
 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_ALIGN                0
 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_BITS                 1
 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_SHIFT                14
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_p1_slicer_only [13:13] */
 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_MASK                 0x2000
 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_ALIGN                0
 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_BITS                 1
 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_SHIFT                13
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */
 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_MASK                       0x1000
 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_ALIGN                      0
 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_BITS                       1
 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_SHIFT                      12
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */
 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                   0x0800
 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                  0
 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                   1
 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                  11
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */
 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_MASK                    0x0400
 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN                   0
 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_BITS                    1
 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT                   10
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */
 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_MASK                   0x0200
 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN                  0
 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_BITS                   1
 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT                  9
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */
 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK                 0x0180
 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN                0
 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS                 2
 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT                7
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */
 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK                  0x0040
 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN                 0
 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS                  1
 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT                 6
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */
 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK                  0x0020
 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN                 0
 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS                  1
 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT                 5
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */
 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK                    0x0010
 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN                   0
 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS                    1
 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT                   4
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */
 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK                    0x0008
 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN                   0
 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS                    1
 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT                   3
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK                      0x0004
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN                     0
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS                      1
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT                     2
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_en [01:01] */
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_MASK                          0x0002
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_ALIGN                         0
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_BITS                          1
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_SHIFT                         1
 
 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK                 0x0001
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN                0
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS                 1
 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT                0
 
 
 /****************************************************************************
  * Dsc1b0 :: cdr_ctrl1
  */
 /* Dsc1b0 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */
 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK                0xffff
 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN               0
 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS                16
 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT               0
 
 
 /****************************************************************************
  * Dsc1b0 :: cdr_ctrl2
  */
 /* Dsc1b0 :: cdr_ctrl2 :: reserved_for_eco0 [15:10] */
 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                    0xfc00
 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                    6
 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                   10
 
 /* Dsc1b0 :: cdr_ctrl2 :: cdros_phase_err_offset [09:06] */
 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_MASK               0x03c0
 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_ALIGN              0
 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_BITS               4
 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_SHIFT              6
 
 /* Dsc1b0 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */
 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK               0x003f
 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN              0
 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS               6
 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT              0
 
 
 /****************************************************************************
  * Dsc1b0 :: pi_ctrl0
  */
 /* Dsc1b0 :: pi_ctrl0 :: pi_cw_rst [15:15] */
 #define DSC1B0_PI_CTRL0_PI_CW_RST_MASK                             0x8000
 #define DSC1B0_PI_CTRL0_PI_CW_RST_ALIGN                            0
 #define DSC1B0_PI_CTRL0_PI_CW_RST_BITS                             1
 #define DSC1B0_PI_CTRL0_PI_CW_RST_SHIFT                            15
 
 /* Dsc1b0 :: pi_ctrl0 :: interp_ctrl_dsel [14:12] */
 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_MASK                      0x7000
 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_ALIGN                     0
 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_BITS                      3
 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_SHIFT                     12
 
 /* Dsc1b0 :: pi_ctrl0 :: interp_ctrl_cap [11:11] */
 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_MASK                       0x0800
 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_ALIGN                      0
 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_BITS                       1
 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_SHIFT                      11
 
 /* Dsc1b0 :: pi_ctrl0 :: reserved_for_eco0 [10:06] */
 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_MASK                     0x07c0
 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_BITS                     5
 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                    6
 
 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult_os8 [05:05] */
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_MASK                0x0020
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_ALIGN               0
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_BITS                1
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_SHIFT               5
 
 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult_os4 [04:04] */
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_MASK                0x0010
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_ALIGN               0
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_BITS                1
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_SHIFT               4
 
 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult_os3 [03:03] */
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_MASK                0x0008
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_ALIGN               0
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_BITS                1
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_SHIFT               3
 
 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult_os2 [02:02] */
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_MASK                0x0004
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_ALIGN               0
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_BITS                1
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_SHIFT               2
 
 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_invert [01:01] */
 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_MASK                       0x0002
 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_ALIGN                      0
 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_BITS                       1
 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_SHIFT                      1
 
 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                    0x0001
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                   0
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                    1
 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                   0
 
 
 /****************************************************************************
  * Dsc1b0 :: pi_ctrl1
  */
 /* Dsc1b0 :: pi_ctrl1 :: reserved_for_eco0 [15:12] */
 #define DSC1B0_PI_CTRL1_RESERVED_FOR_ECO0_MASK                     0xf000
 #define DSC1B0_PI_CTRL1_RESERVED_FOR_ECO0_ALIGN                    0
 #define DSC1B0_PI_CTRL1_RESERVED_FOR_ECO0_BITS                     4
 #define DSC1B0_PI_CTRL1_RESERVED_FOR_ECO0_SHIFT                    12
 
 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_step_dir [11:11] */
 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_MASK                     0x0800
 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_ALIGN                    0
 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_BITS                     1
 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_SHIFT                    11
 
 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_step [10:09] */
 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_MASK                         0x0600
 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_ALIGN                        0
 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_BITS                         2
 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_SHIFT                        9
 
 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_delta [08:04] */
 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_MASK                        0x01f0
 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_ALIGN                       0
 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_BITS                        5
 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_SHIFT                       4
 
 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_strobe [03:03] */
 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_MASK                       0x0008
 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_ALIGN                      0
 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_BITS                       1
 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_SHIFT                      3
 
 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_rotate_override [02:02] */
 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_MASK              0x0004
 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_ALIGN             0
 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_BITS              1
 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_SHIFT             2
 
 /* Dsc1b0 :: pi_ctrl1 :: pi_clk90_offset_override [01:01] */
 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_MASK              0x0002
 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_ALIGN             0
 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_BITS              1
 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_SHIFT             1
 
 /* Dsc1b0 :: pi_ctrl1 :: pi_dual_phase_override [00:00] */
 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_MASK                0x0001
 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_ALIGN               0
 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_BITS                1
 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_SHIFT               0
 
 
 /****************************************************************************
  * Dsc1b0 :: dfe_vga_ctrl0
  */
 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_abs_sum_max [15:09] */
 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_MASK                  0xfe00
 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_ALIGN                 0
 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_BITS                  7
 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_SHIFT                 9
 
 /* Dsc1b0 :: dfe_vga_ctrl0 :: random_tapsel_disable [08:08] */
 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_MASK            0x0100
 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_ALIGN           0
 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_BITS            1
 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_SHIFT           8
 
 /* Dsc1b0 :: dfe_vga_ctrl0 :: cor_neg2_en [07:07] */
 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_MASK                      0x0080
 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_ALIGN                     0
 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_BITS                      1
 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_SHIFT                     7
 
 /* Dsc1b0 :: dfe_vga_ctrl0 :: cor_neg1_en [06:06] */
 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_MASK                      0x0040
 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_ALIGN                     0
 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_BITS                      1
 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_SHIFT                     6
 
 /* Dsc1b0 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */
 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_MASK                     0x0020
 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN                    0
 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_BITS                     1
 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT                    5
 
 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */
 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_MASK                     0x0010
 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN                    0
 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_BITS                     1
 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT                    4
 
 /* Dsc1b0 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */
 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                 0x0008
 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN                0
 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                 1
 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT                3
 
 /* Dsc1b0 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */
 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_MASK                        0x0004
 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                       0
 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_BITS                        1
 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                       2
 
 /* Dsc1b0 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */
 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_MASK                        0x0002
 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN                       0
 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_BITS                        1
 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT                       1
 
 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */
 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                    0x0001
 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                   0
 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                    1
 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                   0
 
 
 /****************************************************************************
  * Dsc1b0 :: dfe_vga_ctrl1
  */
 /* Dsc1b0 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:14] */
 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK                0xc000
 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN               0
 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS                2
 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT               14
 
 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_llms_update_count_sel [13:12] */
 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_MASK        0x3000
 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_ALIGN       0
 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_BITS        2
 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_SHIFT       12
 
 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_llms_en [11:11] */
 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_MASK                      0x0800
 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_ALIGN                     0
 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_BITS                      1
 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_SHIFT                     11
 
 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_cdros_qphase_mult_en [10:10] */
 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_MASK         0x0400
 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_ALIGN        0
 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_BITS         1
 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_SHIFT        10
 
 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_tap_2_dcd [09:06] */
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_MASK                    0x03c0
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_ALIGN                   0
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_BITS                    4
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_SHIFT                   6
 
 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_tap_1_do [05:03] */
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_MASK                     0x0038
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_ALIGN                    0
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_BITS                     3
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_SHIFT                    3
 
 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_tap_1_de [02:00] */
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_MASK                     0x0007
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_ALIGN                    0
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_BITS                     3
 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_SHIFT                    0
 
 
 /****************************************************************************
  * Dsc1b0 :: dfe_vga_ctrl2
  */
 /* Dsc1b0 :: dfe_vga_ctrl2 :: vga3_override_val [15:12] */
 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_MASK                0xf000
 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_ALIGN               0
 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_BITS                4
 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_SHIFT               12
 
 /* Dsc1b0 :: dfe_vga_ctrl2 :: vga3_override_en [11:11] */
 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_MASK                 0x0800
 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_ALIGN                0
 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_BITS                 1
 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_SHIFT                11
 
 /* Dsc1b0 :: dfe_vga_ctrl2 :: reserved_for_eco0 [10:10] */
 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK                0x0400
 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN               0
 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS                1
 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT               10
 
 /* Dsc1b0 :: dfe_vga_ctrl2 :: dfe_vga_write_tapsel [09:07] */
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_MASK             0x0380
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_ALIGN            0
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_BITS             3
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_SHIFT            7
 
 /* Dsc1b0 :: dfe_vga_ctrl2 :: dfe_vga_write_val [06:01] */
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_MASK                0x007e
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_ALIGN               0
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_BITS                6
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_SHIFT               1
 
 /* Dsc1b0 :: dfe_vga_ctrl2 :: dfe_vga_write_en [00:00] */
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_MASK                 0x0001
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_ALIGN                0
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_BITS                 1
 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_SHIFT                0
 
 
 /****************************************************************************
  * Dsc1b0 :: dfe_vga_ctrl3
  */
 /* Dsc1b0 :: dfe_vga_ctrl3 :: trnsum_otap_en [15:08] */
 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_MASK                   0xff00
 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_ALIGN                  0
 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_BITS                   8
 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_SHIFT                  8
 
 /* Dsc1b0 :: dfe_vga_ctrl3 :: trnsum_etap_en [07:00] */
 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_MASK                   0x00ff
 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_ALIGN                  0
 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_BITS                   8
 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_SHIFT                  0
 
 
 /****************************************************************************
  * Dsc1b0 :: dfe_vga_ctrl4
  */
 /* Dsc1b0 :: dfe_vga_ctrl4 :: trnsum_otap_sign [15:08] */
 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_MASK                 0xff00
 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_ALIGN                0
 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_BITS                 8
 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_SHIFT                8
 
 /* Dsc1b0 :: dfe_vga_ctrl4 :: trnsum_etap_sign [07:00] */
 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_MASK                 0x00ff
 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_ALIGN                0
 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_BITS                 8
 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_SHIFT                0
 
 
 /****************************************************************************
  * Dsc1b0 :: dfe_vga_ctrl5
  */
 /* Dsc1b0 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */
 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK                0xfc00
 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN               0
 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS                6
 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT               10
 
 /* Dsc1b0 :: dfe_vga_ctrl5 :: vga_cor_sel_e [09:05] */
 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_MASK                    0x03e0
 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_ALIGN                   0
 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_BITS                    5
 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_SHIFT                   5
 
 /* Dsc1b0 :: dfe_vga_ctrl5 :: vga_cor_sel_o [04:00] */
 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_MASK                    0x001f
 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_ALIGN                   0
 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_BITS                    5
 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_SHIFT                   0
 
 
 /****************************************************************************
  * Dsc1b0 :: dfe_vga_ctrl6
  */
 /* Dsc1b0 :: dfe_vga_ctrl6 :: reserved_for_eco0 [15:10] */
 #define DSC1B0_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_MASK                0xfc00
 #define DSC1B0_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_ALIGN               0
 #define DSC1B0_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_BITS                6
 #define DSC1B0_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_SHIFT               10
 
 /* Dsc1b0 :: dfe_vga_ctrl6 :: dfe_cor_sel_e [09:05] */
 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_MASK                    0x03e0
 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_ALIGN                   0
 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_BITS                    5
 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_SHIFT                   5
 
 /* Dsc1b0 :: dfe_vga_ctrl6 :: dfe_cor_sel_o [04:00] */
 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_MASK                    0x001f
 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_ALIGN                   0
 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_BITS                    5
 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_SHIFT                   0
 
 
 /****************************************************************************
  * Dsc1b0 :: dfe_vga_ctrl7
  */
 /* Dsc1b0 :: dfe_vga_ctrl7 :: disable_cl72_rcving_ctrl_frame [15:15] */
 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_MASK   0x8000
 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_ALIGN  0
 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_BITS   1
 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_SHIFT  15
 
 /* Dsc1b0 :: dfe_vga_ctrl7 :: pattern [14:08] */
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_MASK                          0x7f00
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_ALIGN                         0
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BITS                          7
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_SHIFT                         8
 
 /* Dsc1b0 :: dfe_vga_ctrl7 :: pattern_bit_en [07:01] */
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_MASK                   0x00fe
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_ALIGN                  0
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_BITS                   7
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_SHIFT                  1
 
 /* Dsc1b0 :: dfe_vga_ctrl7 :: pattern_en [00:00] */
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_MASK                       0x0001
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_ALIGN                      0
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_BITS                       1
 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_SHIFT                      0
 
 
 /****************************************************************************
  * Dsc1b0 :: dsc_diag_ctrl0
  */
 /* Dsc1b0 :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:12] */
 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK               0xf000
 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS               4
 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT              12
 
 /* Dsc1b0 :: dsc_diag_ctrl0 :: osx2_diag_ctrl [11:11] */
 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_MASK                  0x0800
 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_ALIGN                 0
 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_BITS                  1
 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_SHIFT                 11
 
 /* Dsc1b0 :: dsc_diag_ctrl0 :: voffset [10:07] */
 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_MASK                         0x0780
 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_ALIGN                        0
 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_BITS                         4
 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_SHIFT                        7
 
 /* Dsc1b0 :: dsc_diag_ctrl0 :: hoffset [06:01] */
 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_MASK                         0x007e
 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_ALIGN                        0
 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_BITS                         6
 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_SHIFT                        1
 
 /* Dsc1b0 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */
 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK                  0x0001
 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN                 0
 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS                  1
 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT                 0
 
 
 /****************************************************************************
  * Dsc1b0 :: uC_ctrl
  */
 /* Dsc1b0 :: uC_ctrl :: supplement_info [15:08] */
 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_MASK                        0xff00
 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_ALIGN                       0
 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_BITS                        8
 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_SHIFT                       8
 
 /* Dsc1b0 :: uC_ctrl :: ready_for_cmd [07:07] */
 #define DSC1B0_UC_CTRL_READY_FOR_CMD_MASK                          0x0080
 #define DSC1B0_UC_CTRL_READY_FOR_CMD_ALIGN                         0
 #define DSC1B0_UC_CTRL_READY_FOR_CMD_BITS                          1
 #define DSC1B0_UC_CTRL_READY_FOR_CMD_SHIFT                         7
 
 /* Dsc1b0 :: uC_ctrl :: error_found [06:06] */
 #define DSC1B0_UC_CTRL_ERROR_FOUND_MASK                            0x0040
 #define DSC1B0_UC_CTRL_ERROR_FOUND_ALIGN                           0
 #define DSC1B0_UC_CTRL_ERROR_FOUND_BITS                            1
 #define DSC1B0_UC_CTRL_ERROR_FOUND_SHIFT                           6
 
 /* Dsc1b0 :: uC_ctrl :: cmd_info [05:04] */
 #define DSC1B0_UC_CTRL_CMD_INFO_MASK                               0x0030
 #define DSC1B0_UC_CTRL_CMD_INFO_ALIGN                              0
 #define DSC1B0_UC_CTRL_CMD_INFO_BITS                               2
 #define DSC1B0_UC_CTRL_CMD_INFO_SHIFT                              4
 
 /* Dsc1b0 :: uC_ctrl :: gp_uC_req [03:00] */
 #define DSC1B0_UC_CTRL_GP_UC_REQ_MASK                              0x000f
 #define DSC1B0_UC_CTRL_GP_UC_REQ_ALIGN                             0
 #define DSC1B0_UC_CTRL_GP_UC_REQ_BITS                              4
 #define DSC1B0_UC_CTRL_GP_UC_REQ_SHIFT                             0
 
 
 /****************************************************************************
  * Warpcore_USER_Dsc2b0
  */
 /****************************************************************************
  * Dsc2b0 :: acq_sm_ctrl0
  */
 /* Dsc2b0 :: acq_sm_ctrl0 :: cl72_timer_en [15:15] */
 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_MASK                     0x8000
 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_ALIGN                    0
 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_BITS                     1
 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_SHIFT                    15
 
 /* Dsc2b0 :: acq_sm_ctrl0 :: acq2_timeout [14:10] */
 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_MASK                      0x7c00
 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_ALIGN                     0
 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_BITS                      5
 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_SHIFT                     10
 
 /* Dsc2b0 :: acq_sm_ctrl0 :: acq1_timeout [09:05] */
 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_MASK                      0x03e0
 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_ALIGN                     0
 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_BITS                      5
 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_SHIFT                     5
 
 /* Dsc2b0 :: acq_sm_ctrl0 :: acqcdr_timeout [04:00] */
 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_MASK                    0x001f
 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_ALIGN                   0
 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_BITS                    5
 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_SHIFT                   0
 
 
 /****************************************************************************
  * Dsc2b0 :: acq_sm_ctrl1
  */
 /* Dsc2b0 :: acq_sm_ctrl1 :: acqvga_timeout [15:11] */
 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_MASK                    0xf800
 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_ALIGN                   0
 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_BITS                    5
 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_SHIFT                   11
 
 /* Dsc2b0 :: acq_sm_ctrl1 :: bypass_os_integ_xfer [10:10] */
 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_MASK              0x0400
 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_ALIGN             0
 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_BITS              1
 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_SHIFT             10
 
 /* Dsc2b0 :: acq_sm_ctrl1 :: dfe_frzval [09:05] */
 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_MASK                        0x03e0
 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_ALIGN                       0
 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_BITS                        5
 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_SHIFT                       5
 
 /* Dsc2b0 :: acq_sm_ctrl1 :: dfe_frcfrz [04:04] */
 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_MASK                        0x0010
 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_ALIGN                       0
 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_BITS                        1
 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_SHIFT                       4
 
 /* Dsc2b0 :: acq_sm_ctrl1 :: vga_frzval [03:03] */
 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_MASK                        0x0008
 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_ALIGN                       0
 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_BITS                        1
 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_SHIFT                       3
 
 /* Dsc2b0 :: acq_sm_ctrl1 :: vga_frcfrz [02:02] */
 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_MASK                        0x0004
 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_ALIGN                       0
 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_BITS                        1
 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_SHIFT                       2
 
 /* Dsc2b0 :: acq_sm_ctrl1 :: dsc_clr_val [01:01] */
 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_MASK                       0x0002
 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_ALIGN                      0
 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_BITS                       1
 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_SHIFT                      1
 
 /* Dsc2b0 :: acq_sm_ctrl1 :: dsc_clr_frc [00:00] */
 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_MASK                       0x0001
 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_ALIGN                      0
 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_BITS                       1
 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_SHIFT                      0
 
 
 /****************************************************************************
  * Dsc2b0 :: acq_sm_ctrl2
  */
 /* Dsc2b0 :: acq_sm_ctrl2 :: sw_handover [15:15] */
 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_MASK                       0x8000
 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_ALIGN                      0
 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_BITS                       1
 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_SHIFT                      15
 
 /* Dsc2b0 :: acq_sm_ctrl2 :: eee_acq_2_timeout [14:10] */
 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_MASK                 0x7c00
 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_ALIGN                0
 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_BITS                 5
 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_SHIFT                10
 
 /* Dsc2b0 :: acq_sm_ctrl2 :: eee_acq_phase_timeout [09:05] */
 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_MASK             0x03e0
 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_ALIGN            0
 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_BITS             5
 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_SHIFT            5
 
 /* Dsc2b0 :: acq_sm_ctrl2 :: skip_acq [04:04] */
 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_MASK                          0x0010
 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_ALIGN                         0
 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_BITS                          1
 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_SHIFT                         4
 
 /* Dsc2b0 :: acq_sm_ctrl2 :: train2_req [03:03] */
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_MASK                        0x0008
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_ALIGN                       0
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_BITS                        1
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_SHIFT                       3
 
 /* Dsc2b0 :: acq_sm_ctrl2 :: train1_req [02:02] */
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_MASK                        0x0004
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_ALIGN                       0
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_BITS                        1
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_SHIFT                       2
 
 /* Dsc2b0 :: acq_sm_ctrl2 :: soft_ack [01:01] */
 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_MASK                          0x0002
 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_ALIGN                         0
 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_BITS                          1
 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_SHIFT                         1
 
 /* Dsc2b0 :: acq_sm_ctrl2 :: train_mode_en [00:00] */
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_MASK                     0x0001
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_ALIGN                    0
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_BITS                     1
 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_SHIFT                    0
 
 
 /****************************************************************************
  * Dsc2b0 :: acq_sm_ctrl3
  */
 /* Dsc2b0 :: acq_sm_ctrl3 :: reserved_for_eco0 [15:14] */
 #define DSC2B0_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_MASK                 0xc000
 #define DSC2B0_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                0
 #define DSC2B0_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_BITS                 2
 #define DSC2B0_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                14
 
 /* Dsc2b0 :: acq_sm_ctrl3 :: os_dfe_en [13:13] */
 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_MASK                         0x2000
 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_ALIGN                        0
 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_BITS                         1
 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_SHIFT                        13
 
 /* Dsc2b0 :: acq_sm_ctrl3 :: dfe_taps2_5_en [12:12] */
 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_MASK                    0x1000
 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_ALIGN                   0
 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_BITS                    1
 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_SHIFT                   12
 
 /* Dsc2b0 :: acq_sm_ctrl3 :: dfe_gain_acq2 [11:10] */
 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_MASK                     0x0c00
 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN                    0
 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_BITS                     2
 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT                    10
 
 /* Dsc2b0 :: acq_sm_ctrl3 :: dfe_gain_acq1 [09:08] */
 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_MASK                     0x0300
 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN                    0
 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_BITS                     2
 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT                    8
 
 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acq2 [07:06] */
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_MASK                     0x00c0
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN                    0
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_BITS                     2
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT                    6
 
 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acq1 [05:04] */
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_MASK                     0x0030
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN                    0
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_BITS                     2
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT                    4
 
 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acqcdr [03:02] */
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_MASK                   0x000c
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN                  0
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_BITS                   2
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT                  2
 
 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acqvga [01:00] */
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_MASK                   0x0003
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN                  0
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_BITS                   2
 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT                  0
 
 
 /****************************************************************************
  * Dsc2b0 :: acq_sm_ctrl4
  */
 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */
 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK         0xc000
 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN        0
 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS         2
 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT        14
 
 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros38_bwsel_prop_offset [13:12] */
 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_MASK         0x3000
 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_ALIGN        0
 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_BITS         2
 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_SHIFT        12
 
 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [11:08] */
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK           0x0f00
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN          0
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS           4
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT          8
 
 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acqcdr [07:04] */
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK           0x00f0
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN          0
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS           4
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT          4
 
 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acqvga [03:00] */
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_MASK           0x000f
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_ALIGN          0
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_BITS           4
 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_SHIFT          0
 
 
 /****************************************************************************
  * Dsc2b0 :: acq_sm_ctrl5
  */
 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_eee_acq2 [15:12] */
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_MASK        0xf000
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_ALIGN       0
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_BITS        4
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_SHIFT       12
 
 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [11:08] */
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK          0x0f00
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN         0
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS          4
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT         8
 
 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acqcdr [07:04] */
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK          0x00f0
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN         0
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS          4
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT         4
 
 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acqvga [03:00] */
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_MASK          0x000f
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_ALIGN         0
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_BITS          4
 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_SHIFT         0
 
 
 /****************************************************************************
  * Dsc2b0 :: acq_sm_ctrl6
  */
 /* Dsc2b0 :: acq_sm_ctrl6 :: reserved_for_eco0 [15:12] */
 #define DSC2B0_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_MASK                 0xf000
 #define DSC2B0_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN                0
 #define DSC2B0_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_BITS                 4
 #define DSC2B0_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT                12
 
 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acq2 [11:09] */
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_MASK             0x0e00
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_ALIGN            0
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_BITS             3
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_SHIFT            9
 
 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acq1 [08:06] */
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_MASK             0x01c0
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_ALIGN            0
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_BITS             3
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_SHIFT            6
 
 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acqcdr [05:03] */
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_MASK           0x0038
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_ALIGN          0
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_BITS           3
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_SHIFT          3
 
 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [02:00] */
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK         0x0007
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN        0
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS         3
 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT        0
 
 
 /****************************************************************************
  * Dsc2b0 :: acq_sm_ctrl7
  */
 /* Dsc2b0 :: acq_sm_ctrl7 :: reserved_for_eco0 [15:12] */
 #define DSC2B0_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_MASK                 0xf000
 #define DSC2B0_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN                0
 #define DSC2B0_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_BITS                 4
 #define DSC2B0_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT                12
 
 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acq2 [11:09] */
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_MASK            0x0e00
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_ALIGN           0
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_BITS            3
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_SHIFT           9
 
 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acq1 [08:06] */
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_MASK            0x01c0
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_ALIGN           0
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_BITS            3
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_SHIFT           6
 
 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acqcdr [05:03] */
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_MASK          0x0038
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN         0
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_BITS          3
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT         3
 
 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acqphase [02:00] */
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_MASK        0x0007
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN       0
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_BITS        3
 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT       0
 
 
 /****************************************************************************
  * Dsc2b0 :: acq_sm_ctrl8
  */
 /* Dsc2b0 :: acq_sm_ctrl8 :: reserved_for_eco0 [15:15] */
 #define DSC2B0_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_MASK                 0x8000
 #define DSC2B0_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN                0
 #define DSC2B0_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_BITS                 1
 #define DSC2B0_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT                15
 
 /* Dsc2b0 :: acq_sm_ctrl8 :: cdros_bwsel_prop_eee_acqphase [14:11] */
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_MASK     0x7800
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_ALIGN    0
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_BITS     4
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_SHIFT    11
 
 /* Dsc2b0 :: acq_sm_ctrl8 :: phase_sat_ctrl_100fx [10:09] */
 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_MASK              0x0600
 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_ALIGN             0
 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_BITS              2
 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_SHIFT             9
 
 /* Dsc2b0 :: acq_sm_ctrl8 :: pi_phase_step_mult_100fx [08:08] */
 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_MASK          0x0100
 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_ALIGN         0
 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_BITS          1
 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_SHIFT         8
 
 /* Dsc2b0 :: acq_sm_ctrl8 :: cdros_bwsel_integ_100fx [07:04] */
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_MASK           0x00f0
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_ALIGN          0
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_BITS           4
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_SHIFT          4
 
 /* Dsc2b0 :: acq_sm_ctrl8 :: cdros_bwsel_prop_100fx [03:00] */
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_MASK            0x000f
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_ALIGN           0
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_BITS            4
 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_SHIFT           0
 
 
 /****************************************************************************
  * Dsc2b0 :: dsc_ana_ctrl0
  */
 /* Dsc2b0 :: dsc_ana_ctrl0 :: reserved_for_eco0 [15:15] */
 #define DSC2B0_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_MASK                0x8000
 #define DSC2B0_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_ALIGN               0
 #define DSC2B0_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_BITS                1
 #define DSC2B0_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_SHIFT               15
 
 /* Dsc2b0 :: dsc_ana_ctrl0 :: force_p1_ctrl_strobe [14:14] */
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_MASK             0x4000
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_ALIGN            0
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_BITS             1
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_SHIFT            14
 
 /* Dsc2b0 :: dsc_ana_ctrl0 :: force_p1_odd_ctrl [13:13] */
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_MASK                0x2000
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_ALIGN               0
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_BITS                1
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_SHIFT               13
 
 /* Dsc2b0 :: dsc_ana_ctrl0 :: force_p1_evn_ctrl [12:12] */
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_MASK                0x1000
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_ALIGN               0
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_BITS                1
 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_SHIFT               12
 
 /* Dsc2b0 :: dsc_ana_ctrl0 :: p1_odd_ctrl [11:06] */
 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK                      0x0fc0
 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN                     0
 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS                      6
 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT                     6
 
 /* Dsc2b0 :: dsc_ana_ctrl0 :: p1_evn_ctrl [05:00] */
 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_MASK                      0x003f
 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_ALIGN                     0
 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_BITS                      6
 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_SHIFT                     0
 
 
 /****************************************************************************
  * Dsc2b0 :: dsc_ana_ctrl1
  */
 /* Dsc2b0 :: dsc_ana_ctrl1 :: reserved_for_eco0 [15:15] */
 #define DSC2B0_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_MASK                0x8000
 #define DSC2B0_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_ALIGN               0
 #define DSC2B0_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_BITS                1
 #define DSC2B0_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_SHIFT               15
 
 /* Dsc2b0 :: dsc_ana_ctrl1 :: force_d_ctrl_strobe [14:14] */
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_MASK              0x4000
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_ALIGN             0
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_BITS              1
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_SHIFT             14
 
 /* Dsc2b0 :: dsc_ana_ctrl1 :: force_d_odd_ctrl [13:13] */
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_MASK                 0x2000
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_ALIGN                0
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_BITS                 1
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_SHIFT                13
 
 /* Dsc2b0 :: dsc_ana_ctrl1 :: force_d_evn_ctrl [12:12] */
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_MASK                 0x1000
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_ALIGN                0
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_BITS                 1
 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_SHIFT                12
 
 /* Dsc2b0 :: dsc_ana_ctrl1 :: d_odd_ctrl [11:06] */
 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_MASK                       0x0fc0
 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_ALIGN                      0
 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_BITS                       6
 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_SHIFT                      6
 
 /* Dsc2b0 :: dsc_ana_ctrl1 :: d_evn_ctrl [05:00] */
 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_MASK                       0x003f
 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN                      0
 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_BITS                       6
 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT                      0
 
 
 /****************************************************************************
  * Dsc2b0 :: dsc_ana_ctrl2
  */
 /* Dsc2b0 :: dsc_ana_ctrl2 :: reserved_for_eco0 [15:15] */
 #define DSC2B0_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_MASK                0x8000
 #define DSC2B0_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_ALIGN               0
 #define DSC2B0_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_BITS                1
 #define DSC2B0_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_SHIFT               15
 
 /* Dsc2b0 :: dsc_ana_ctrl2 :: force_m1_ctrl_strobe [14:14] */
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_MASK             0x4000
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_ALIGN            0
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_BITS             1
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_SHIFT            14
 
 /* Dsc2b0 :: dsc_ana_ctrl2 :: force_m1_odd_ctrl [13:13] */
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_MASK                0x2000
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_ALIGN               0
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_BITS                1
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_SHIFT               13
 
 /* Dsc2b0 :: dsc_ana_ctrl2 :: force_m1_evn_ctrl [12:12] */
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_MASK                0x1000
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_ALIGN               0
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_BITS                1
 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_SHIFT               12
 
 /* Dsc2b0 :: dsc_ana_ctrl2 :: m1_odd_ctrl [11:06] */
 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_MASK                      0x0fc0
 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_ALIGN                     0
 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_BITS                      6
 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_SHIFT                     6
 
 /* Dsc2b0 :: dsc_ana_ctrl2 :: m1_evn_ctrl [05:00] */
 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_MASK                      0x003f
 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_ALIGN                     0
 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_BITS                      6
 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_SHIFT                     0
 
 
 /****************************************************************************
  * Dsc2b0 :: dsc_ana_ctrl3
  */
 /* Dsc2b0 :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:10] */
 #define DSC2B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK                0xfc00
 #define DSC2B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
 #define DSC2B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS                6
 #define DSC2B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT               10
 
 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_pf_hiz [09:09] */
 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_MASK                        0x0200
 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_ALIGN                       0
 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_BITS                        1
 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_SHIFT                       9
 
 /* Dsc2b0 :: dsc_ana_ctrl3 :: force_rx_m1_thresh_zero [08:08] */
 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_MASK          0x0100
 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_ALIGN         0
 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_BITS          1
 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_SHIFT         8
 
 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_m1_thresh_zero [07:07] */
 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_MASK                0x0080
 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_ALIGN               0
 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_BITS                1
 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_SHIFT               7
 
 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_thresh_sel [06:05] */
 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_MASK                    0x0060
 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_ALIGN                   0
 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_BITS                    2
 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_SHIFT                   5
 
 /* Dsc2b0 :: dsc_ana_ctrl3 :: force_rx_pf_ctrl [04:04] */
 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_MASK                 0x0010
 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_ALIGN                0
 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_BITS                 1
 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_SHIFT                4
 
 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_pf_ctrl [03:00] */
 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_MASK                       0x000f
 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_ALIGN                      0
 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_BITS                       4
 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_SHIFT                      0
 
 
 /****************************************************************************
  * Dsc2b0 :: dsc_ana_ctrl4
  */
 /* Dsc2b0 :: dsc_ana_ctrl4 :: reserved_for_eco0 [15:08] */
 #define DSC2B0_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_MASK                0xff00
 #define DSC2B0_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_ALIGN               0
 #define DSC2B0_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_BITS                8
 #define DSC2B0_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_SHIFT               8
 
 /* Dsc2b0 :: dsc_ana_ctrl4 :: br_offset_pd [07:07] */
 #define DSC2B0_DSC_ANA_CTRL4_BR_OFFSET_PD_MASK                     0x0080
 #define DSC2B0_DSC_ANA_CTRL4_BR_OFFSET_PD_ALIGN                    0
 #define DSC2B0_DSC_ANA_CTRL4_BR_OFFSET_PD_BITS                     1
 #define DSC2B0_DSC_ANA_CTRL4_BR_OFFSET_PD_SHIFT                    7
 
 /* Dsc2b0 :: dsc_ana_ctrl4 :: br_en_hgain [06:06] */
 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_HGAIN_MASK                      0x0040
 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_HGAIN_ALIGN                     0
 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_HGAIN_BITS                      1
 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_HGAIN_SHIFT                     6
 
 /* Dsc2b0 :: dsc_ana_ctrl4 :: br_en_dfe_clk [05:05] */
 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_DFE_CLK_MASK                    0x0020
 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_DFE_CLK_ALIGN                   0
 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_DFE_CLK_BITS                    1
 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_DFE_CLK_SHIFT                   5
 
 /* Dsc2b0 :: dsc_ana_ctrl4 :: br_pd_ch_p1 [04:04] */
 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_MASK                      0x0010
 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_ALIGN                     0
 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_BITS                      1
 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_SHIFT                     4
 
 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_offset_pd [03:03] */
 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_MASK                    0x0008
 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_ALIGN                   0
 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_BITS                    1
 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_SHIFT                   3
 
 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_en_hgain [02:02] */
 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_MASK                     0x0004
 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_ALIGN                    0
 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_BITS                     1
 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_SHIFT                    2
 
 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_en_dfe_clk [01:01] */
 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_MASK                   0x0002
 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_ALIGN                  0
 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_BITS                   1
 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_SHIFT                  1
 
 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_pd_ch_p1 [00:00] */
 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_MASK                     0x0001
 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_ALIGN                    0
 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_BITS                     1
 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_SHIFT                    0
 
 
 /****************************************************************************
  * Dsc2b0 :: dsc_misc_ctrl0
  */
 /* Dsc2b0 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */
 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_MASK                      0x8000
 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_ALIGN                     0
 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_BITS                      1
 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_SHIFT                     15
 
 /* Dsc2b0 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */
 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK                  0x4000
 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN                 0
 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS                  1
 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT                 14
 
 /* Dsc2b0 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */
 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK                0x2000
 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN               0
 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS                1
 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT               13
 
 /* Dsc2b0 :: dsc_misc_ctrl0 :: forceRxSeqDone_val [12:12] */
 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_MASK              0x1000
 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_ALIGN             0
 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_BITS              1
 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_SHIFT             12
 
 /* Dsc2b0 :: dsc_misc_ctrl0 :: rxSeqStart_AN_disable [11:11] */
 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_MASK           0x0800
 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_ALIGN          0
 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_BITS           1
 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_SHIFT          11
 
 /* Dsc2b0 :: dsc_misc_ctrl0 :: test_bus_sel_bit4 [10:10] */
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_MASK               0x0400
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_ALIGN              0
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_BITS               1
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_SHIFT              10
 
 /* Dsc2b0 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */
 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK                 0x0200
 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN                0
 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS                 1
 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT                9
 
 /* Dsc2b0 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */
 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK             0x0100
 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN            0
 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS             1
 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT            8
 
 /* Dsc2b0 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */
 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK                  0x0080
 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN                 0
 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS                  1
 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT                 7
 
 /* Dsc2b0 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */
 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK              0x0070
 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN             0
 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS              3
 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT             4
 
 /* Dsc2b0 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK                    0x000f
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN                   0
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS                    4
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT                   0
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_Off                     0
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data                1
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1             2
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1           3
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco             4
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg                 6
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr             7
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd           8
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe            9
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum               10
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe1                 12
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe2                 13
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe3                 14
 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe4                 15
 
 
 /****************************************************************************
  * Warpcore_USER_Dsc3b0
  */
 /****************************************************************************
  * Dsc3b0 :: cdr_status0
  */
 /* Dsc3b0 :: cdr_status0 :: integ_reg [15:00] */
 #define DSC3B0_CDR_STATUS0_INTEG_REG_MASK                          0xffff
 #define DSC3B0_CDR_STATUS0_INTEG_REG_ALIGN                         0
 #define DSC3B0_CDR_STATUS0_INTEG_REG_BITS                          16
 #define DSC3B0_CDR_STATUS0_INTEG_REG_SHIFT                         0
 
 
 /****************************************************************************
  * Dsc3b0 :: cdr_status1
  */
 /* Dsc3b0 :: cdr_status1 :: integ_reg_xfer [15:00] */
 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_MASK                     0xffff
 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_ALIGN                    0
 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_BITS                     16
 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_SHIFT                    0
 
 
 /****************************************************************************
  * Dsc3b0 :: cdr_status2
  */
 /* Dsc3b0 :: cdr_status2 :: reserved_for_eco0 [15:11] */
 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_MASK                  0xf800
 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN                 0
 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_BITS                  5
 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT                 11
 
 /* Dsc3b0 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */
 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK                  0x0400
 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN                 0
 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS                  1
 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT                 10
 
 /* Dsc3b0 :: cdr_status2 :: br_cdr_enabled [09:09] */
 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_MASK                     0x0200
 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_ALIGN                    0
 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_BITS                     1
 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_SHIFT                    9
 
 /* Dsc3b0 :: cdr_status2 :: oscdr_mode [08:06] */
 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_MASK                         0x01c0
 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_ALIGN                        0
 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_BITS                         3
 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_SHIFT                        6
 
 /* Dsc3b0 :: cdr_status2 :: phase_err [05:00] */
 #define DSC3B0_CDR_STATUS2_PHASE_ERR_MASK                          0x003f
 #define DSC3B0_CDR_STATUS2_PHASE_ERR_ALIGN                         0
 #define DSC3B0_CDR_STATUS2_PHASE_ERR_BITS                          6
 #define DSC3B0_CDR_STATUS2_PHASE_ERR_SHIFT                         0
 
 
 /****************************************************************************
  * Dsc3b0 :: pi_status0
  */
 /* Dsc3b0 :: pi_status0 :: reserved_for_eco0 [15:14] */
 #define DSC3B0_PI_STATUS0_RESERVED_FOR_ECO0_MASK                   0xc000
 #define DSC3B0_PI_STATUS0_RESERVED_FOR_ECO0_ALIGN                  0
 #define DSC3B0_PI_STATUS0_RESERVED_FOR_ECO0_BITS                   2
 #define DSC3B0_PI_STATUS0_RESERVED_FOR_ECO0_SHIFT                  14
 
 /* Dsc3b0 :: pi_status0 :: clk90_phase_offset [13:07] */
 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                  0x3f80
 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                 0
 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                  7
 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                 7
 
 /* Dsc3b0 :: pi_status0 :: phase_cntr [06:00] */
 #define DSC3B0_PI_STATUS0_PHASE_CNTR_MASK                          0x007f
 #define DSC3B0_PI_STATUS0_PHASE_CNTR_ALIGN                         0
 #define DSC3B0_PI_STATUS0_PHASE_CNTR_BITS                          7
 #define DSC3B0_PI_STATUS0_PHASE_CNTR_SHIFT                         0
 
 
 /****************************************************************************
  * Dsc3b0 :: pi_status1
  */
 /* Dsc3b0 :: pi_status1 :: phs_interp_status [15:00] */
 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_MASK                   0xffff
 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_ALIGN                  0
 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_BITS                   16
 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_SHIFT                  0
 
 
 /****************************************************************************
  * Dsc3b0 :: dfe_vga_status0
  */
 /* Dsc3b0 :: dfe_vga_status0 :: reserved_for_eco0 [15:12] */
 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK              0xf000
 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS              4
 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT             12
 
 /* Dsc3b0 :: dfe_vga_status0 :: dfe_tap_1_bin [11:06] */
 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_MASK                  0x0fc0
 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_ALIGN                 0
 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_BITS                  6
 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_SHIFT                 6
 
 /* Dsc3b0 :: dfe_vga_status0 :: vga_sum [05:00] */
 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_MASK                        0x003f
 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_ALIGN                       0
 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_BITS                        6
 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_SHIFT                       0
 
 
 /****************************************************************************
  * Dsc3b0 :: dfe_vga_status1
  */
 /* Dsc3b0 :: dfe_vga_status1 :: reserved_for_eco0 [15:12] */
 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK              0xf000
 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS              4
 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT             12
 
 /* Dsc3b0 :: dfe_vga_status1 :: dfe_tap_3_bin [11:06] */
 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_MASK                  0x0fc0
 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_ALIGN                 0
 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_BITS                  6
 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_SHIFT                 6
 
 /* Dsc3b0 :: dfe_vga_status1 :: dfe_tap_2_bin [05:00] */
 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_MASK                  0x003f
 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_ALIGN                 0
 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_BITS                  6
 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_SHIFT                 0
 
 
 /****************************************************************************
  * Dsc3b0 :: dfe_vga_status2
  */
 /* Dsc3b0 :: dfe_vga_status2 :: reserved_for_eco0 [15:10] */
 #define DSC3B0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_MASK              0xfc00
 #define DSC3B0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC3B0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_BITS              6
 #define DSC3B0_DFE_VGA_STATUS2_RESERVED_FOR_ECO0_SHIFT             10
 
 /* Dsc3b0 :: dfe_vga_status2 :: dfe_tap_5_bin [09:05] */
 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_MASK                  0x03e0
 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_ALIGN                 0
 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_BITS                  5
 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_SHIFT                 5
 
 /* Dsc3b0 :: dfe_vga_status2 :: dfe_tap_4_bin [04:00] */
 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_MASK                  0x001f
 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_ALIGN                 0
 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_BITS                  5
 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_SHIFT                 0
 
 
 /****************************************************************************
  * Dsc3b0 :: dfe_vga_status3
  */
 /* Dsc3b0 :: dfe_vga_status3 :: reserved_for_eco0 [15:11] */
 #define DSC3B0_DFE_VGA_STATUS3_RESERVED_FOR_ECO0_MASK              0xf800
 #define DSC3B0_DFE_VGA_STATUS3_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC3B0_DFE_VGA_STATUS3_RESERVED_FOR_ECO0_BITS              5
 #define DSC3B0_DFE_VGA_STATUS3_RESERVED_FOR_ECO0_SHIFT             11
 
 /* Dsc3b0 :: dfe_vga_status3 :: trnsum [10:00] */
 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_MASK                         0x07ff
 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_ALIGN                        0
 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_BITS                         11
 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_SHIFT                        0
 
 
 /****************************************************************************
  * Dsc3b0 :: acq_sm_status0
  */
 /* Dsc3b0 :: acq_sm_status0 :: reserved_for_eco0 [15:09] */
 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO0_MASK               0xfe00
 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN              0
 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO0_BITS               7
 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT              9
 
 /* Dsc3b0 :: acq_sm_status0 :: dsc_state_eee_acq_2 [08:08] */
 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_MASK             0x0100
 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_ALIGN            0
 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_BITS             1
 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_SHIFT            8
 
 /* Dsc3b0 :: acq_sm_status0 :: reserved_for_eco1 [07:05] */
 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO1_MASK               0x00e0
 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO1_ALIGN              0
 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO1_BITS               3
 #define DSC3B0_ACQ_SM_STATUS0_RESERVED_FOR_ECO1_SHIFT              5
 
 /* Dsc3b0 :: acq_sm_status0 :: dsc_state [04:00] */
 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_MASK                       0x001f
 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_ALIGN                      0
 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_BITS                       5
 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_SHIFT                      0
 
 
 /****************************************************************************
  * Dsc3b0 :: acq_sm_status1
  */
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_eee_acq_cdr_phase [15:15] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_MASK     0x8000
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_ALIGN    0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_BITS     1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_SHIFT    15
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_eee_quiet [14:14] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_MASK             0x4000
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_ALIGN            0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_BITS             1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_SHIFT            14
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_done [13:13] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_MASK                  0x2000
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_ALIGN                 0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_BITS                  1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_SHIFT                 13
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_measure [12:12] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_MASK               0x1000
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_ALIGN              0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_BITS               1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_SHIFT              12
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_train_2 [11:11] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_MASK               0x0800
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_ALIGN              0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_BITS               1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_SHIFT              11
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_train_1 [10:10] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_MASK               0x0400
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_ALIGN              0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_BITS               1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_SHIFT              10
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_soft_ack [09:09] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_MASK              0x0200
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_ALIGN             0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_BITS              1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_SHIFT             9
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_2 [08:08] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_MASK                 0x0100
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_ALIGN                0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_BITS                 1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_SHIFT                8
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_1 [07:07] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_MASK                 0x0080
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_ALIGN                0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_BITS                 1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_SHIFT                7
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_cdr [06:06] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_MASK               0x0040
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_ALIGN              0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_BITS               1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_SHIFT              6
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_cdrbr_phase [05:05] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_MASK       0x0020
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_ALIGN      0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_BITS       1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_SHIFT      5
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_os_integ_xfer [04:04] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_MASK         0x0010
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_ALIGN        0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_BITS         1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_SHIFT        4
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_vga [03:03] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_MASK               0x0008
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_ALIGN              0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_BITS               1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_SHIFT              3
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_setup [02:02] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_MASK                 0x0004
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_ALIGN                0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_BITS                 1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_SHIFT                2
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_pause [01:01] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_MASK                 0x0002
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_ALIGN                0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_BITS                 1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_SHIFT                1
 
 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_init [00:00] */
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_MASK                  0x0001
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_ALIGN                 0
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_BITS                  1
 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_SHIFT                 0
 
 
 /****************************************************************************
  * Dsc3b0 :: ana_status0
  */
 /* Dsc3b0 :: ana_status0 :: reserved_for_eco0 [15:08] */
 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_MASK                  0xff00
 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_BITS                  8
 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT                 8
 
 /* Dsc3b0 :: ana_status0 :: pd_ch_p1 [07:07] */
 #define DSC3B0_ANA_STATUS0_PD_CH_P1_MASK                           0x0080
 #define DSC3B0_ANA_STATUS0_PD_CH_P1_ALIGN                          0
 #define DSC3B0_ANA_STATUS0_PD_CH_P1_BITS                           1
 #define DSC3B0_ANA_STATUS0_PD_CH_P1_SHIFT                          7
 
 /* Dsc3b0 :: ana_status0 :: en_dfe_clk [06:06] */
 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_MASK                         0x0040
 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_ALIGN                        0
 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_BITS                         1
 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_SHIFT                        6
 
 /* Dsc3b0 :: ana_status0 :: en_hgain [05:05] */
 #define DSC3B0_ANA_STATUS0_EN_HGAIN_MASK                           0x0020
 #define DSC3B0_ANA_STATUS0_EN_HGAIN_ALIGN                          0
 #define DSC3B0_ANA_STATUS0_EN_HGAIN_BITS                           1
 #define DSC3B0_ANA_STATUS0_EN_HGAIN_SHIFT                          5
 
 /* Dsc3b0 :: ana_status0 :: offset_pd [04:04] */
 #define DSC3B0_ANA_STATUS0_OFFSET_PD_MASK                          0x0010
 #define DSC3B0_ANA_STATUS0_OFFSET_PD_ALIGN                         0
 #define DSC3B0_ANA_STATUS0_OFFSET_PD_BITS                          1
 #define DSC3B0_ANA_STATUS0_OFFSET_PD_SHIFT                         4
 
 /* Dsc3b0 :: ana_status0 :: pf_ctrl_bin [03:00] */
 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_MASK                        0x000f
 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_ALIGN                       0
 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_BITS                        4
 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_SHIFT                       0
 
 
 /****************************************************************************
  * Dsc3b0 :: ana_status1
  */
 /* Dsc3b0 :: ana_status1 :: reserved_for_eco0 [15:12] */
 #define DSC3B0_ANA_STATUS1_RESERVED_FOR_ECO0_MASK                  0xf000
 #define DSC3B0_ANA_STATUS1_RESERVED_FOR_ECO0_ALIGN                 0
 #define DSC3B0_ANA_STATUS1_RESERVED_FOR_ECO0_BITS                  4
 #define DSC3B0_ANA_STATUS1_RESERVED_FOR_ECO0_SHIFT                 12
 
 /* Dsc3b0 :: ana_status1 :: slicer_offset_po [11:06] */
 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_MASK                   0x0fc0
 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_ALIGN                  0
 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_BITS                   6
 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_SHIFT                  6
 
 /* Dsc3b0 :: ana_status1 :: slicer_offset_pe [05:00] */
 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_MASK                   0x003f
 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_ALIGN                  0
 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_BITS                   6
 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_SHIFT                  0
 
 
 /****************************************************************************
  * Dsc3b0 :: ana_status2
  */
 /* Dsc3b0 :: ana_status2 :: reserved_for_eco0 [15:12] */
 #define DSC3B0_ANA_STATUS2_RESERVED_FOR_ECO0_MASK                  0xf000
 #define DSC3B0_ANA_STATUS2_RESERVED_FOR_ECO0_ALIGN                 0
 #define DSC3B0_ANA_STATUS2_RESERVED_FOR_ECO0_BITS                  4
 #define DSC3B0_ANA_STATUS2_RESERVED_FOR_ECO0_SHIFT                 12
 
 /* Dsc3b0 :: ana_status2 :: slicer_offset_zo [11:06] */
 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_MASK                   0x0fc0
 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_ALIGN                  0
 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_BITS                   6
 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_SHIFT                  6
 
 /* Dsc3b0 :: ana_status2 :: slicer_offset_ze [05:00] */
 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_MASK                   0x003f
 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_ALIGN                  0
 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_BITS                   6
 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_SHIFT                  0
 
 
 /****************************************************************************
  * Dsc3b0 :: ana_status3
  */
 /* Dsc3b0 :: ana_status3 :: reserved_for_eco0 [15:12] */
 #define DSC3B0_ANA_STATUS3_RESERVED_FOR_ECO0_MASK                  0xf000
 #define DSC3B0_ANA_STATUS3_RESERVED_FOR_ECO0_ALIGN                 0
 #define DSC3B0_ANA_STATUS3_RESERVED_FOR_ECO0_BITS                  4
 #define DSC3B0_ANA_STATUS3_RESERVED_FOR_ECO0_SHIFT                 12
 
 /* Dsc3b0 :: ana_status3 :: slicer_offset_mo [11:06] */
 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_MASK                   0x0fc0
 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_ALIGN                  0
 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_BITS                   6
 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_SHIFT                  6
 
 /* Dsc3b0 :: ana_status3 :: slicer_offset_me [05:00] */
 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_MASK                   0x003f
 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_ALIGN                  0
 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_BITS                   6
 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_SHIFT                  0
 
 
 /****************************************************************************
  * Warpcore_USER_Dsc4b0
  */
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl0
  */
 /* Dsc4b0 :: tuning_sm_ctrl0 :: reserved_for_eco0 [15:15] */
 #define DSC4B0_TUNING_SM_CTRL0_RESERVED_FOR_ECO0_MASK              0x8000
 #define DSC4B0_TUNING_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL0_RESERVED_FOR_ECO0_BITS              1
 #define DSC4B0_TUNING_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT             15
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_tx_postc_cal [14:14] */
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK            0x4000
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN           0
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS            1
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT           14
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_br_vga [13:13] */
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_MASK                  0x2000
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_ALIGN                 0
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_BITS                  1
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_SHIFT                 13
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: postc_metric_ctrl [12:12] */
 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_MASK              0x1000
 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_BITS              1
 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT             12
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: hysteresis_en [11:11] */
 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_MASK                  0x0800
 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_ALIGN                 0
 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_BITS                  1
 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_SHIFT                 11
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: slicer_cal_linear_srch [10:10] */
 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK         0x0400
 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN        0
 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS         1
 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT        10
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_br_pf_cal [09:09] */
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_MASK               0x0200
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN              0
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_BITS               1
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT              9
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK             0x0100
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN            0
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS             1
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT            8
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK             0x0080
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN            0
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS             1
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT            7
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_data_slicer_recal [06:06] */
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK       0x0040
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN      0
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS       1
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT      6
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK        0x0020
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN       0
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS        1
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT       5
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK        0x0010
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN       0
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS        1
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT       4
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK      0x0008
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN     0
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS      1
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT     3
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK      0x0004
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN     0
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS      1
 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT     2
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: restart_tuning [01:01] */
 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_MASK                 0x0002
 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_ALIGN                0
 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_BITS                 1
 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_SHIFT                1
 
 /* Dsc4b0 :: tuning_sm_ctrl0 :: tuning_sm_en [00:00] */
 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_MASK                   0x0001
 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_ALIGN                  0
 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_BITS                   1
 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_SHIFT                  0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl1
  */
 /* Dsc4b0 :: tuning_sm_ctrl1 :: reserved_for_eco0 [15:15] */
 #define DSC4B0_TUNING_SM_CTRL1_RESERVED_FOR_ECO0_MASK              0x8000
 #define DSC4B0_TUNING_SM_CTRL1_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL1_RESERVED_FOR_ECO0_BITS              1
 #define DSC4B0_TUNING_SM_CTRL1_RESERVED_FOR_ECO0_SHIFT             15
 
 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_br_offset [14:12] */
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_MASK              0x7000
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_BITS              3
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_SHIFT             12
 
 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_osx1_offset [11:09] */
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_MASK            0x0e00
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_ALIGN           0
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_BITS            3
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_SHIFT           9
 
 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_osx2_offset [08:06] */
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_MASK            0x01c0
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_ALIGN           0
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_BITS            3
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_SHIFT           6
 
 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_br_init [05:03] */
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_MASK                0x0038
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_ALIGN               0
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_BITS                3
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_SHIFT               3
 
 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_os_init [02:00] */
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_MASK                0x0007
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_ALIGN               0
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_BITS                3
 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_SHIFT               0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl2
  */
 /* Dsc4b0 :: tuning_sm_ctrl2 :: reserved_for_eco0 [15:12] */
 #define DSC4B0_TUNING_SM_CTRL2_RESERVED_FOR_ECO0_MASK              0xf000
 #define DSC4B0_TUNING_SM_CTRL2_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL2_RESERVED_FOR_ECO0_BITS              4
 #define DSC4B0_TUNING_SM_CTRL2_RESERVED_FOR_ECO0_SHIFT             12
 
 /* Dsc4b0 :: tuning_sm_ctrl2 :: vga_max_val [11:06] */
 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_MASK                    0x0fc0
 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_ALIGN                   0
 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_BITS                    6
 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_SHIFT                   6
 
 /* Dsc4b0 :: tuning_sm_ctrl2 :: vga_min_val [05:00] */
 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_MASK                    0x003f
 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_ALIGN                   0
 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_BITS                    6
 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_SHIFT                   0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl3
  */
 /* Dsc4b0 :: tuning_sm_ctrl3 :: reserved_for_eco0 [15:12] */
 #define DSC4B0_TUNING_SM_CTRL3_RESERVED_FOR_ECO0_MASK              0xf000
 #define DSC4B0_TUNING_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL3_RESERVED_FOR_ECO0_BITS              4
 #define DSC4B0_TUNING_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT             12
 
 /* Dsc4b0 :: tuning_sm_ctrl3 :: dfe_max_val [11:06] */
 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_MASK                    0x0fc0
 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_ALIGN                   0
 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_BITS                    6
 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_SHIFT                   6
 
 /* Dsc4b0 :: tuning_sm_ctrl3 :: dfe_min_val [05:00] */
 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_MASK                    0x003f
 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_ALIGN                   0
 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_BITS                    6
 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_SHIFT                   0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl4
  */
 /* Dsc4b0 :: tuning_sm_ctrl4 :: reserved_for_eco0 [15:14] */
 #define DSC4B0_TUNING_SM_CTRL4_RESERVED_FOR_ECO0_MASK              0xc000
 #define DSC4B0_TUNING_SM_CTRL4_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL4_RESERVED_FOR_ECO0_BITS              2
 #define DSC4B0_TUNING_SM_CTRL4_RESERVED_FOR_ECO0_SHIFT             14
 
 /* Dsc4b0 :: tuning_sm_ctrl4 :: br_pf_tap_en [13:07] */
 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_MASK                   0x3f80
 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_ALIGN                  0
 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_BITS                   7
 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_SHIFT                  7
 
 /* Dsc4b0 :: tuning_sm_ctrl4 :: osx1_pf_tap_en [06:00] */
 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_MASK                 0x007f
 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_ALIGN                0
 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_BITS                 7
 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_SHIFT                0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl5
  */
 /* Dsc4b0 :: tuning_sm_ctrl5 :: reserved_for_eco0 [15:15] */
 #define DSC4B0_TUNING_SM_CTRL5_RESERVED_FOR_ECO0_MASK              0x8000
 #define DSC4B0_TUNING_SM_CTRL5_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL5_RESERVED_FOR_ECO0_BITS              1
 #define DSC4B0_TUNING_SM_CTRL5_RESERVED_FOR_ECO0_SHIFT             15
 
 /* Dsc4b0 :: tuning_sm_ctrl5 :: msr_br_vga_timeout [14:10] */
 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_MASK             0x7c00
 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_ALIGN            0
 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_BITS             5
 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_SHIFT            10
 
 /* Dsc4b0 :: tuning_sm_ctrl5 :: hysteresis_timeout [09:05] */
 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_MASK             0x03e0
 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_ALIGN            0
 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_BITS             5
 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_SHIFT            5
 
 /* Dsc4b0 :: tuning_sm_ctrl5 :: msr_postc_timeout [04:00] */
 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_MASK              0x001f
 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_BITS              5
 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_SHIFT             0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl6
  */
 /* Dsc4b0 :: tuning_sm_ctrl6 :: reserved_for_eco0 [15:14] */
 #define DSC4B0_TUNING_SM_CTRL6_RESERVED_FOR_ECO0_MASK              0xc000
 #define DSC4B0_TUNING_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL6_RESERVED_FOR_ECO0_BITS              2
 #define DSC4B0_TUNING_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT             14
 
 /* Dsc4b0 :: tuning_sm_ctrl6 :: br_vga_lms_gain [13:12] */
 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_MASK                0x3000
 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_ALIGN               0
 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_BITS                2
 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_SHIFT               12
 
 /* Dsc4b0 :: tuning_sm_ctrl6 :: postc_dfe_lms_gain [11:10] */
 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_MASK             0x0c00
 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_ALIGN            0
 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_BITS             2
 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_SHIFT            10
 
 /* Dsc4b0 :: tuning_sm_ctrl6 :: cdr_phase_inversion_timeout [09:05] */
 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_MASK    0x03e0
 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_ALIGN   0
 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_BITS    5
 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_SHIFT   5
 
 /* Dsc4b0 :: tuning_sm_ctrl6 :: msr_pf_timeout [04:00] */
 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_MASK                 0x001f
 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_ALIGN                0
 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_BITS                 5
 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_SHIFT                0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl7
  */
 /* Dsc4b0 :: tuning_sm_ctrl7 :: reserved0 [15:15] */
 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_MASK                      0x8000
 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_ALIGN                     0
 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_BITS                      1
 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_SHIFT                     15
 
 /* Dsc4b0 :: tuning_sm_ctrl7 :: br_vga_trn2_timeout [14:10] */
 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_MASK            0x7c00
 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_ALIGN           0
 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_BITS            5
 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_SHIFT           10
 
 /* Dsc4b0 :: tuning_sm_ctrl7 :: br_pf_trn2_timeout [09:05] */
 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_MASK             0x03e0
 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_ALIGN            0
 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_BITS             5
 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_SHIFT            5
 
 /* Dsc4b0 :: tuning_sm_ctrl7 :: br_pf_trn1_timeout [04:00] */
 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_MASK             0x001f
 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_ALIGN            0
 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_BITS             5
 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_SHIFT            0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl8
  */
 /* Dsc4b0 :: tuning_sm_ctrl8 :: reserved0 [15:14] */
 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_MASK                      0xc000
 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_ALIGN                     0
 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_BITS                      2
 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_SHIFT                     14
 
 /* Dsc4b0 :: tuning_sm_ctrl8 :: br_postc_tap_en [13:07] */
 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_MASK                0x3f80
 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_ALIGN               0
 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_BITS                7
 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_SHIFT               7
 
 /* Dsc4b0 :: tuning_sm_ctrl8 :: osx2_pf_tap_en [06:00] */
 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_MASK                 0x007f
 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_ALIGN                0
 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_BITS                 7
 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_SHIFT                0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl9
  */
 /* Dsc4b0 :: tuning_sm_ctrl9 :: reserved0 [15:14] */
 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_MASK                      0xc000
 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_ALIGN                     0
 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_BITS                      2
 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_SHIFT                     14
 
 /* Dsc4b0 :: tuning_sm_ctrl9 :: osx2_postc_tap_en [13:07] */
 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_MASK              0x3f80
 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_BITS              7
 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_SHIFT             7
 
 /* Dsc4b0 :: tuning_sm_ctrl9 :: osx1_postc_tap_en [06:00] */
 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_MASK              0x007f
 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_ALIGN             0
 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_BITS              7
 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_SHIFT             0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl10
  */
 /* Dsc4b0 :: tuning_sm_ctrl10 :: reserved0 [15:15] */
 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_MASK                     0x8000
 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_ALIGN                    0
 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_BITS                     1
 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_SHIFT                    15
 
 /* Dsc4b0 :: tuning_sm_ctrl10 :: msr_slicer_slow_timeout [14:10] */
 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_MASK       0x7c00
 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_ALIGN      0
 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_BITS       5
 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_SHIFT      10
 
 /* Dsc4b0 :: tuning_sm_ctrl10 :: msr_slicer_fast_timeout [09:05] */
 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_MASK       0x03e0
 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_ALIGN      0
 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_BITS       5
 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_SHIFT      5
 
 /* Dsc4b0 :: tuning_sm_ctrl10 :: default_trn2_timeout [04:00] */
 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_MASK          0x001f
 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_ALIGN         0
 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_BITS          5
 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_SHIFT         0
 
 
 /****************************************************************************
  * Dsc4b0 :: tuning_sm_ctrl11
  */
 /* Dsc4b0 :: tuning_sm_ctrl11 :: phase_sat_ctrl_os8 [15:14] */
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS8_MASK            0xc000
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS8_ALIGN           0
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS8_BITS            2
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS8_SHIFT           14
 
 /* Dsc4b0 :: tuning_sm_ctrl11 :: phase_sat_ctrl_os4 [13:12] */
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS4_MASK            0x3000
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS4_ALIGN           0
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS4_BITS            2
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS4_SHIFT           12
 
 /* Dsc4b0 :: tuning_sm_ctrl11 :: phase_sat_ctrl_os3 [11:10] */
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS3_MASK            0x0c00
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS3_ALIGN           0
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS3_BITS            2
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS3_SHIFT           10
 
 /* Dsc4b0 :: tuning_sm_ctrl11 :: phase_sat_ctrl_os2 [09:08] */
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS2_MASK            0x0300
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS2_ALIGN           0
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS2_BITS            2
 #define DSC4B0_TUNING_SM_CTRL11_PHASE_SAT_CTRL_OS2_SHIFT           8
 
 /* Dsc4b0 :: tuning_sm_ctrl11 :: pf_fine_en [07:07] */
 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_MASK                    0x0080
 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_ALIGN                   0
 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_BITS                    1
 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_SHIFT                   7
 
 /* Dsc4b0 :: tuning_sm_ctrl11 :: reserved0 [06:06] */
 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_MASK                     0x0040
 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_ALIGN                    0
 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_BITS                     1
 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_SHIFT                    6
 
 /* Dsc4b0 :: tuning_sm_ctrl11 :: pf_max_val [05:02] */
 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_MASK                    0x003c
 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_ALIGN                   0
 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_BITS                    4
 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_SHIFT                   2
 
 /* Dsc4b0 :: tuning_sm_ctrl11 :: bypass_osx1_slicer_cal [01:01] */
 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_MASK        0x0002
 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_ALIGN       0
 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_BITS        1
 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_SHIFT       1
 
 /* Dsc4b0 :: tuning_sm_ctrl11 :: bypass_osx2_slicer_cal [00:00] */
 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_MASK        0x0001
 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_ALIGN       0
 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_BITS        1
 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_SHIFT       0
 
 
 /****************************************************************************
  * Dsc4b0 :: acq_sm_ctrl9
  */
 /* Dsc4b0 :: acq_sm_ctrl9 :: integ_sat_sel_os8 [15:15] */
 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS8_MASK                 0x8000
 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS8_ALIGN                0
 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS8_BITS                 1
 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS8_SHIFT                15
 
 /* Dsc4b0 :: acq_sm_ctrl9 :: integ_sat_sel_os4 [14:14] */
 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS4_MASK                 0x4000
 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS4_ALIGN                0
 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS4_BITS                 1
 #define DSC4B0_ACQ_SM_CTRL9_INTEG_SAT_SEL_OS4_SHIFT                14
 
 /* Dsc4b0 :: acq_sm_ctrl9 :: reserved_for_eco0 [13:13] */
 #define DSC4B0_ACQ_SM_CTRL9_RESERVED_FOR_ECO0_MASK                 0x2000
 #define DSC4B0_ACQ_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN                0
 #define DSC4B0_ACQ_SM_CTRL9_RESERVED_FOR_ECO0_BITS                 1
 #define DSC4B0_ACQ_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT                13
 
 /* Dsc4b0 :: acq_sm_ctrl9 :: eee_lfsr_cnt [12:00] */
 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_MASK                      0x1fff
 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_ALIGN                     0
 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_BITS                      13
 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_SHIFT                     0
 
 
 /****************************************************************************
  * Dsc4b0 :: acq_sm_ctrl10
  */
 /* Dsc4b0 :: acq_sm_ctrl10 :: integ_sat_sel_os3 [15:15] */
 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS3_MASK                0x8000
 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS3_ALIGN               0
 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS3_BITS                1
 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS3_SHIFT               15
 
 /* Dsc4b0 :: acq_sm_ctrl10 :: integ_sat_sel_os2 [14:14] */
 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS2_MASK                0x4000
 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS2_ALIGN               0
 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS2_BITS                1
 #define DSC4B0_ACQ_SM_CTRL10_INTEG_SAT_SEL_OS2_SHIFT               14
 
 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros8_bwsel_prop_acq12_offset [13:12] */
 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_ACQ12_OFFSET_MASK   0x3000
 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_ACQ12_OFFSET_ALIGN  0
 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_ACQ12_OFFSET_BITS   2
 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_ACQ12_OFFSET_SHIFT  12
 
 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros4_bwsel_prop_acq12_offset [11:10] */
 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_ACQ12_OFFSET_MASK   0x0c00
 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_ACQ12_OFFSET_ALIGN  0
 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_ACQ12_OFFSET_BITS   2
 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_ACQ12_OFFSET_SHIFT  10
 
 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros3_bwsel_prop_acq12_offset [09:08] */
 #define DSC4B0_ACQ_SM_CTRL10_CDROS3_BWSEL_PROP_ACQ12_OFFSET_MASK   0x0300
 #define DSC4B0_ACQ_SM_CTRL10_CDROS3_BWSEL_PROP_ACQ12_OFFSET_ALIGN  0
 #define DSC4B0_ACQ_SM_CTRL10_CDROS3_BWSEL_PROP_ACQ12_OFFSET_BITS   2
 #define DSC4B0_ACQ_SM_CTRL10_CDROS3_BWSEL_PROP_ACQ12_OFFSET_SHIFT  8
 
 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros2_bwsel_prop_acq12_offset [07:06] */
 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_ACQ12_OFFSET_MASK   0x00c0
 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_ACQ12_OFFSET_ALIGN  0
 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_ACQ12_OFFSET_BITS   2
 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_ACQ12_OFFSET_SHIFT  6
 
 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros8_bwsel_prop_offset [05:04] */
 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_OFFSET_MASK         0x0030
 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_OFFSET_ALIGN        0
 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_OFFSET_BITS         2
 #define DSC4B0_ACQ_SM_CTRL10_CDROS8_BWSEL_PROP_OFFSET_SHIFT        4
 
 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros4_bwsel_prop_offset [03:02] */
 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_OFFSET_MASK         0x000c
 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_OFFSET_ALIGN        0
 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_OFFSET_BITS         2
 #define DSC4B0_ACQ_SM_CTRL10_CDROS4_BWSEL_PROP_OFFSET_SHIFT        2
 
 /* Dsc4b0 :: acq_sm_ctrl10 :: cdros2_bwsel_prop_offset [01:00] */
 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_OFFSET_MASK         0x0003
 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_OFFSET_ALIGN        0
 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_OFFSET_BITS         2
 #define DSC4B0_ACQ_SM_CTRL10_CDROS2_BWSEL_PROP_OFFSET_SHIFT        0
 
 
 /****************************************************************************
  * Dsc4b0 :: acq_sm_ctrl11
  */
 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros8_bwsel_integ_acq12_offset [15:14] */
 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_ACQ12_OFFSET_MASK  0xc000
 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_ACQ12_OFFSET_ALIGN 0
 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_ACQ12_OFFSET_BITS  2
 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_ACQ12_OFFSET_SHIFT 14
 
 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros4_bwsel_integ_acq12_offset [13:12] */
 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_ACQ12_OFFSET_MASK  0x3000
 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_ACQ12_OFFSET_ALIGN 0
 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_ACQ12_OFFSET_BITS  2
 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_ACQ12_OFFSET_SHIFT 12
 
 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros3_bwsel_integ_acq12_offset [11:10] */
 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_ACQ12_OFFSET_MASK  0x0c00
 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_ACQ12_OFFSET_ALIGN 0
 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_ACQ12_OFFSET_BITS  2
 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_ACQ12_OFFSET_SHIFT 10
 
 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros2_bwsel_integ_acq12_offset [09:08] */
 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_ACQ12_OFFSET_MASK  0x0300
 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_ACQ12_OFFSET_ALIGN 0
 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_ACQ12_OFFSET_BITS  2
 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_ACQ12_OFFSET_SHIFT 8
 
 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros8_bwsel_integ_offset [07:06] */
 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_OFFSET_MASK        0x00c0
 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_OFFSET_ALIGN       0
 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_OFFSET_BITS        2
 #define DSC4B0_ACQ_SM_CTRL11_CDROS8_BWSEL_INTEG_OFFSET_SHIFT       6
 
 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros4_bwsel_integ_offset [05:04] */
 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_OFFSET_MASK        0x0030
 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_OFFSET_ALIGN       0
 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_OFFSET_BITS        2
 #define DSC4B0_ACQ_SM_CTRL11_CDROS4_BWSEL_INTEG_OFFSET_SHIFT       4
 
 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros3_bwsel_integ_offset [03:02] */
 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_OFFSET_MASK        0x000c
 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_OFFSET_ALIGN       0
 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_OFFSET_BITS        2
 #define DSC4B0_ACQ_SM_CTRL11_CDROS3_BWSEL_INTEG_OFFSET_SHIFT       2
 
 /* Dsc4b0 :: acq_sm_ctrl11 :: cdros2_bwsel_integ_offset [01:00] */
 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_OFFSET_MASK        0x0003
 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_OFFSET_ALIGN       0
 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_OFFSET_BITS        2
 #define DSC4B0_ACQ_SM_CTRL11_CDROS2_BWSEL_INTEG_OFFSET_SHIFT       0
 
 
 /****************************************************************************
  * Warpcore_USER_Dsc5b0
  */
 /****************************************************************************
  * Dsc5b0 :: tuning_sm_status0
  */
 /* Dsc5b0 :: tuning_sm_status0 :: reserved_for_eco0 [15:14] */
 #define DSC5B0_TUNING_SM_STATUS0_RESERVED_FOR_ECO0_MASK            0xc000
 #define DSC5B0_TUNING_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN           0
 #define DSC5B0_TUNING_SM_STATUS0_RESERVED_FOR_ECO0_BITS            2
 #define DSC5B0_TUNING_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT           14
 
 /* Dsc5b0 :: tuning_sm_status0 :: tuning_done [13:13] */
 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_MASK                  0x2000
 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_ALIGN                 0
 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_BITS                  1
 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_SHIFT                 13
 
 /* Dsc5b0 :: tuning_sm_status0 :: srch_state [12:09] */
 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_MASK                   0x1e00
 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_ALIGN                  0
 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_BITS                   4
 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_SHIFT                  9
 
 /* Dsc5b0 :: tuning_sm_status0 :: tuning_state [08:04] */
 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_MASK                 0x01f0
 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_ALIGN                0
 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_BITS                 5
 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_SHIFT                4
 
 /* Dsc5b0 :: tuning_sm_status0 :: dsc_state [03:00] */
 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_MASK                    0x000f
 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_ALIGN                   0
 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_BITS                    4
 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_SHIFT                   0
 
 
 /****************************************************************************
  * Dsc5b0 :: tuning_sm_status1
  */
 /* Dsc5b0 :: tuning_sm_status1 :: reserved_for_eco0 [15:11] */
 #define DSC5B0_TUNING_SM_STATUS1_RESERVED_FOR_ECO0_MASK            0xf800
 #define DSC5B0_TUNING_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN           0
 #define DSC5B0_TUNING_SM_STATUS1_RESERVED_FOR_ECO0_BITS            5
 #define DSC5B0_TUNING_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT           11
 
 /* Dsc5b0 :: tuning_sm_status1 :: postc_metric [10:00] */
 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_MASK                 0x07ff
 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_ALIGN                0
 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_BITS                 11
 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_SHIFT                0
 
 
 /****************************************************************************
  * Dsc5b0 :: tuning_sm_status2
  */
 /* Dsc5b0 :: tuning_sm_status2 :: reserved_for_eco0 [15:06] */
 #define DSC5B0_TUNING_SM_STATUS2_RESERVED_FOR_ECO0_MASK            0xffc0
 #define DSC5B0_TUNING_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN           0
 #define DSC5B0_TUNING_SM_STATUS2_RESERVED_FOR_ECO0_BITS            10
 #define DSC5B0_TUNING_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT           6
 
 /* Dsc5b0 :: tuning_sm_status2 :: dfe_max [05:05] */
 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_MASK                      0x0020
 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_ALIGN                     0
 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_BITS                      1
 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_SHIFT                     5
 
 /* Dsc5b0 :: tuning_sm_status2 :: dfe_min [04:04] */
 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_MASK                      0x0010
 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_ALIGN                     0
 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_BITS                      1
 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_SHIFT                     4
 
 /* Dsc5b0 :: tuning_sm_status2 :: vga_max [03:03] */
 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_MASK                      0x0008
 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_ALIGN                     0
 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_BITS                      1
 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_SHIFT                     3
 
 /* Dsc5b0 :: tuning_sm_status2 :: vga_min [02:02] */
 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_MASK                      0x0004
 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_ALIGN                     0
 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_BITS                      1
 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_SHIFT                     2
 
 /* Dsc5b0 :: tuning_sm_status2 :: pf_max [01:01] */
 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_MASK                       0x0002
 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_ALIGN                      0
 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_BITS                       1
 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_SHIFT                      1
 
 /* Dsc5b0 :: tuning_sm_status2 :: pf_min [00:00] */
 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_MASK                       0x0001
 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_ALIGN                      0
 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_BITS                       1
 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_SHIFT                      0
 
 
 /****************************************************************************
  * Dsc5b0 :: tuning_sm_status3
  */
 /* Dsc5b0 :: tuning_sm_status3 :: reserved_for_eco0 [15:11] */
 #define DSC5B0_TUNING_SM_STATUS3_RESERVED_FOR_ECO0_MASK            0xf800
 #define DSC5B0_TUNING_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN           0
 #define DSC5B0_TUNING_SM_STATUS3_RESERVED_FOR_ECO0_BITS            5
 #define DSC5B0_TUNING_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT           11
 
 /* Dsc5b0 :: tuning_sm_status3 :: trnsum_br_vga [10:00] */
 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_MASK                0x07ff
 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_ALIGN               0
 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_BITS                11
 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_SHIFT               0
 
 
 /****************************************************************************
  * Dsc5b0 :: tuning_sm_status4
  */
 /* Dsc5b0 :: tuning_sm_status4 :: reserved_for_eco0 [15:11] */
 #define DSC5B0_TUNING_SM_STATUS4_RESERVED_FOR_ECO0_MASK            0xf800
 #define DSC5B0_TUNING_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN           0
 #define DSC5B0_TUNING_SM_STATUS4_RESERVED_FOR_ECO0_BITS            5
 #define DSC5B0_TUNING_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT           11
 
 /* Dsc5b0 :: tuning_sm_status4 :: trnsum_pf [10:00] */
 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_MASK                    0x07ff
 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_ALIGN                   0
 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_BITS                    11
 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_SHIFT                   0
 
 
 /****************************************************************************
  * Dsc5b0 :: tuning_sm_status5
  */
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_tx_postc [15:15] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_MASK     0x8000
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_ALIGN    0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_BITS     1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_SHIFT    15
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_pf [14:14] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_MASK           0x4000
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_ALIGN          0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_BITS           1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_SHIFT          14
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_vga [13:13] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_MASK          0x2000
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_ALIGN         0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_BITS          1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_SHIFT         13
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_po [12:12] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_MASK    0x1000
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_ALIGN   0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_BITS    1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_SHIFT   12
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_pe [11:11] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_MASK    0x0800
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_ALIGN   0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_BITS    1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_SHIFT   11
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_mo [10:10] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_MASK    0x0400
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_ALIGN   0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_BITS    1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_SHIFT   10
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_me [09:09] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_MASK    0x0200
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_ALIGN   0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_BITS    1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_SHIFT   9
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_do [08:08] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_MASK    0x0100
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_ALIGN   0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_BITS    1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_SHIFT   8
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_de [07:07] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_MASK    0x0080
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_ALIGN   0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_BITS    1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_SHIFT   7
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_tx_postc [06:06] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_MASK     0x0040
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_ALIGN    0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_BITS     1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_SHIFT    6
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_pf [05:05] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_MASK           0x0020
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_ALIGN          0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_BITS           1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_SHIFT          5
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_mo [04:04] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_MASK    0x0010
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_ALIGN   0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_BITS    1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_SHIFT   4
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_me [03:03] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_MASK    0x0008
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_ALIGN   0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_BITS    1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_SHIFT   3
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_do [02:02] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_MASK    0x0004
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_ALIGN   0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_BITS    1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_SHIFT   2
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_de [01:01] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_MASK    0x0002
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_ALIGN   0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_BITS    1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_SHIFT   1
 
 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_wait_for_lock [00:00] */
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_MASK   0x0001
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_ALIGN  0
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_BITS   1
 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_SHIFT  0
 
 
 /****************************************************************************
  * Dsc5b0 :: tuning_sm_status6
  */
 /* Dsc5b0 :: tuning_sm_status6 :: reserved_for_eco0 [15:12] */
 #define DSC5B0_TUNING_SM_STATUS6_RESERVED_FOR_ECO0_MASK            0xf000
 #define DSC5B0_TUNING_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN           0
 #define DSC5B0_TUNING_SM_STATUS6_RESERVED_FOR_ECO0_BITS            4
 #define DSC5B0_TUNING_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT           12
 
 /* Dsc5b0 :: tuning_sm_status6 :: tuning_state_hysteresis [11:11] */
 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_MASK      0x0800
 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_ALIGN     0
 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_BITS      1
 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_SHIFT     11
 
 /* Dsc5b0 :: tuning_sm_status6 :: tuning_state_tuning_done [10:10] */
 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_MASK     0x0400
 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_ALIGN    0
 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_BITS     1
 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_SHIFT    10
 
 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_done [09:09] */
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_MASK         0x0200
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_ALIGN        0
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_BITS         1
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_SHIFT        9
 
 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait_undo_setup [08:08] */
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_MASK 0x0100
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_ALIGN 0
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_BITS 1
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_SHIFT 8
 
 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_undo_setup [07:07] */
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_MASK   0x0080
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_ALIGN  0
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_BITS   1
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_SHIFT  7
 
 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait_msr [06:06] */
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_MASK     0x0040
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_ALIGN    0
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_BITS     1
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_SHIFT    6
 
 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_set_msr [05:05] */
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_MASK      0x0020
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_ALIGN     0
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_BITS      1
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_SHIFT     5
 
 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait_trn [04:04] */
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_MASK     0x0010
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_ALIGN    0
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_BITS     1
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_SHIFT    4
 
 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_set_trn [03:03] */
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_MASK      0x0008
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_ALIGN     0
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_BITS      1
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_SHIFT     3
 
 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait [02:02] */
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MASK         0x0004
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_ALIGN        0
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_BITS         1
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_SHIFT        2
 
 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_setup [01:01] */
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_MASK        0x0002
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_ALIGN       0
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_BITS        1
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_SHIFT       1
 
 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_disable [00:00] */
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_MASK      0x0001
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_ALIGN     0
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_BITS      1
 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_SHIFT     0
 
 
 /****************************************************************************
  * Warpcore_USER_CL72_UserB0
  */
 /****************************************************************************
  * CL72_UserB0 :: cl72_xmt_control_register
  */
 /* CL72_UserB0 :: cl72_xmt_control_register :: xmt_control_page [15:00] */
 #define CL72_USERB0_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_MASK 0xffff
 #define CL72_USERB0_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_ALIGN 0
 #define CL72_USERB0_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_BITS 16
 #define CL72_USERB0_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_SHIFT 0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_rcvd_status_register
  */
 /* CL72_UserB0 :: cl72_rcvd_status_register :: rcvd_status_page [15:00] */
 #define CL72_USERB0_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_MASK 0xffff
 #define CL72_USERB0_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_ALIGN 0
 #define CL72_USERB0_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_BITS 16
 #define CL72_USERB0_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_SHIFT 0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_tx_fir_tap_register
  */
 /* CL72_UserB0 :: cl72_tx_fir_tap_register :: tx_fir_tap_force [15:15] */
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_MASK 0x8000
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_ALIGN 0
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_BITS 1
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_SHIFT 15
 
 /* CL72_UserB0 :: cl72_tx_fir_tap_register :: tx_fir_tap_post [14:10] */
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_MASK  0x7c00
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_ALIGN 0
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_BITS  5
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_SHIFT 10
 
 /* CL72_UserB0 :: cl72_tx_fir_tap_register :: tx_fir_tap_main [09:04] */
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_MASK  0x03f0
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_ALIGN 0
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_BITS  6
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_SHIFT 4
 
 /* CL72_UserB0 :: cl72_tx_fir_tap_register :: tx_fir_tap_pre [03:00] */
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_MASK   0x000f
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_ALIGN  0
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_BITS   4
 #define CL72_USERB0_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_SHIFT  0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_misc1_control
  */
 /* CL72_UserB0 :: cl72_misc1_control :: link_control_force [15:15] */
 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_MASK     0x8000
 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_ALIGN    0
 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_BITS     1
 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_SHIFT    15
 
 /* CL72_UserB0 :: cl72_misc1_control :: link_control_forceval [14:14] */
 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_MASK  0x4000
 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_ALIGN 0
 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_BITS  1
 #define CL72_USERB0_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_SHIFT 14
 
 /* CL72_UserB0 :: cl72_misc1_control :: tx_fir_tap_main_kx_init_val [13:08] */
 #define CL72_USERB0_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_MASK 0x3f00
 #define CL72_USERB0_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_BITS 6
 #define CL72_USERB0_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_SHIFT 8
 
 /* CL72_UserB0 :: cl72_misc1_control :: tap_default_muxsel_force [07:07] */
 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_MASK 0x0080
 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_ALIGN 0
 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_BITS 1
 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_SHIFT 7
 
 /* CL72_UserB0 :: cl72_misc1_control :: tap_default_muxsel_forceval [06:04] */
 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_MASK 0x0070
 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_ALIGN 0
 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_BITS 3
 #define CL72_USERB0_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_SHIFT 4
 
 /* CL72_UserB0 :: cl72_misc1_control :: reserved0 [03:02] */
 #define CL72_USERB0_CL72_MISC1_CONTROL_RESERVED0_MASK              0x000c
 #define CL72_USERB0_CL72_MISC1_CONTROL_RESERVED0_ALIGN             0
 #define CL72_USERB0_CL72_MISC1_CONTROL_RESERVED0_BITS              2
 #define CL72_USERB0_CL72_MISC1_CONTROL_RESERVED0_SHIFT             2
 
 /* CL72_UserB0 :: cl72_misc1_control :: tr_coarse_lock [01:01] */
 #define CL72_USERB0_CL72_MISC1_CONTROL_TR_COARSE_LOCK_MASK         0x0002
 #define CL72_USERB0_CL72_MISC1_CONTROL_TR_COARSE_LOCK_ALIGN        0
 #define CL72_USERB0_CL72_MISC1_CONTROL_TR_COARSE_LOCK_BITS         1
 #define CL72_USERB0_CL72_MISC1_CONTROL_TR_COARSE_LOCK_SHIFT        1
 
 /* CL72_UserB0 :: cl72_misc1_control :: rx_trained [00:00] */
 #define CL72_USERB0_CL72_MISC1_CONTROL_RX_TRAINED_MASK             0x0001
 #define CL72_USERB0_CL72_MISC1_CONTROL_RX_TRAINED_ALIGN            0
 #define CL72_USERB0_CL72_MISC1_CONTROL_RX_TRAINED_BITS             1
 #define CL72_USERB0_CL72_MISC1_CONTROL_RX_TRAINED_SHIFT            0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_misc2_control
  */
 /* CL72_UserB0 :: cl72_misc2_control :: reserved0 [15:14] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_RESERVED0_MASK              0xc000
 #define CL72_USERB0_CL72_MISC2_CONTROL_RESERVED0_ALIGN             0
 #define CL72_USERB0_CL72_MISC2_CONTROL_RESERVED0_BITS              2
 #define CL72_USERB0_CL72_MISC2_CONTROL_RESERVED0_SHIFT             14
 
 /* CL72_UserB0 :: cl72_misc2_control :: rxfifo_data_swap_r20clk [13:13] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_MASK 0x2000
 #define CL72_USERB0_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_ALIGN 0
 #define CL72_USERB0_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_BITS 1
 #define CL72_USERB0_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_SHIFT 13
 
 /* CL72_UserB0 :: cl72_misc2_control :: txfifo_data_swap_t20clk [12:12] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_MASK 0x1000
 #define CL72_USERB0_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_ALIGN 0
 #define CL72_USERB0_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_BITS 1
 #define CL72_USERB0_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_SHIFT 12
 
 /* CL72_UserB0 :: cl72_misc2_control :: signal_detect_fec_sel [11:11] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_MASK  0x0800
 #define CL72_USERB0_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_ALIGN 0
 #define CL72_USERB0_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_BITS  1
 #define CL72_USERB0_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_SHIFT 11
 
 /* CL72_UserB0 :: cl72_misc2_control :: wait_timer_frame_inc_en [10:10] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_MASK 0x0400
 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_ALIGN 0
 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_BITS 1
 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_SHIFT 10
 
 /* CL72_UserB0 :: cl72_misc2_control :: wait_timer_frame_cnt_init_sel [09:08] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_MASK 0x0300
 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_ALIGN 0
 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_BITS 2
 #define CL72_USERB0_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_SHIFT 8
 
 /* CL72_UserB0 :: cl72_misc2_control :: main_tap_adjust_force [07:07] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_MASK  0x0080
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_ALIGN 0
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_BITS  1
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_SHIFT 7
 
 /* CL72_UserB0 :: cl72_misc2_control :: main_tap_adjust_forceval [06:06] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_MASK 0x0040
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_ALIGN 0
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_BITS 1
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_SHIFT 6
 
 /* CL72_UserB0 :: cl72_misc2_control :: main_tap_adjust_en [05:05] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_MASK     0x0020
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_ALIGN    0
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_BITS     1
 #define CL72_USERB0_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_SHIFT    5
 
 /* CL72_UserB0 :: cl72_misc2_control :: newpg_rcvd_override [04:04] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_MASK    0x0010
 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_ALIGN   0
 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_BITS    1
 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_SHIFT   4
 
 /* CL72_UserB0 :: cl72_misc2_control :: newpg_rcvd_load [03:03] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_MASK        0x0008
 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_ALIGN       0
 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_BITS        1
 #define CL72_USERB0_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_SHIFT       3
 
 /* CL72_UserB0 :: cl72_misc2_control :: inc_dec_val_sel [02:02] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_MASK        0x0004
 #define CL72_USERB0_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_ALIGN       0
 #define CL72_USERB0_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_BITS        1
 #define CL72_USERB0_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_SHIFT       2
 
 /* CL72_UserB0 :: cl72_misc2_control :: dis_max_wait_timer_force [01:01] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_MASK 0x0002
 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_ALIGN 0
 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_BITS 1
 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_SHIFT 1
 
 /* CL72_UserB0 :: cl72_misc2_control :: dis_max_wait_timer_forceval [00:00] */
 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_MASK 0x0001
 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_ALIGN 0
 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_BITS 1
 #define CL72_USERB0_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_SHIFT 0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_kr_default_control
  */
 /* CL72_UserB0 :: cl72_kr_default_control :: reserved0 [15:15] */
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_RESERVED0_MASK         0x8000
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_RESERVED0_ALIGN        0
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_RESERVED0_BITS         1
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_RESERVED0_SHIFT        15
 
 /* CL72_UserB0 :: cl72_kr_default_control :: tx_fir_tap_post_kr_init_val [14:10] */
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_MASK 0x7c00
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_BITS 5
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_SHIFT 10
 
 /* CL72_UserB0 :: cl72_kr_default_control :: tx_fir_tap_main_kr_init_val [09:04] */
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_MASK 0x03f0
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_BITS 6
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_SHIFT 4
 
 /* CL72_UserB0 :: cl72_kr_default_control :: tx_fir_tap_pre_kr_init_val [03:00] */
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_MASK 0x000f
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_BITS 4
 #define CL72_USERB0_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_SHIFT 0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_os_default_control
  */
 /* CL72_UserB0 :: cl72_os_default_control :: reserved0 [15:15] */
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_RESERVED0_MASK         0x8000
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_RESERVED0_ALIGN        0
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_RESERVED0_BITS         1
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_RESERVED0_SHIFT        15
 
 /* CL72_UserB0 :: cl72_os_default_control :: tx_fir_tap_post_os_init_val [14:10] */
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_MASK 0x7c00
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_BITS 5
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_SHIFT 10
 
 /* CL72_UserB0 :: cl72_os_default_control :: tx_fir_tap_main_os_init_val [09:04] */
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_MASK 0x03f0
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_BITS 6
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_SHIFT 4
 
 /* CL72_UserB0 :: cl72_os_default_control :: tx_fir_tap_pre_os_init_val [03:00] */
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_MASK 0x000f
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_BITS 4
 #define CL72_USERB0_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_SHIFT 0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_br_default_control
  */
 /* CL72_UserB0 :: cl72_br_default_control :: reserved0 [15:15] */
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_RESERVED0_MASK         0x8000
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_RESERVED0_ALIGN        0
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_RESERVED0_BITS         1
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_RESERVED0_SHIFT        15
 
 /* CL72_UserB0 :: cl72_br_default_control :: tx_fir_tap_post_br_init_val [14:10] */
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_MASK 0x7c00
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_BITS 5
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_SHIFT 10
 
 /* CL72_UserB0 :: cl72_br_default_control :: tx_fir_tap_main_br_init_val [09:04] */
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_MASK 0x03f0
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_BITS 6
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_SHIFT 4
 
 /* CL72_UserB0 :: cl72_br_default_control :: tx_fir_tap_pre_br_init_val [03:00] */
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_MASK 0x000f
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_BITS 4
 #define CL72_USERB0_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_SHIFT 0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_2p5_default_control
  */
 /* CL72_UserB0 :: cl72_2p5_default_control :: reserved0 [15:15] */
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_RESERVED0_MASK        0x8000
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_RESERVED0_ALIGN       0
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_RESERVED0_BITS        1
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_RESERVED0_SHIFT       15
 
 /* CL72_UserB0 :: cl72_2p5_default_control :: tx_fir_tap_post_2p5_init_val [14:10] */
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_MASK 0x7c00
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_BITS 5
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_SHIFT 10
 
 /* CL72_UserB0 :: cl72_2p5_default_control :: tx_fir_tap_main_2p5_init_val [09:04] */
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_MASK 0x03f0
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_BITS 6
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_SHIFT 4
 
 /* CL72_UserB0 :: cl72_2p5_default_control :: tx_fir_tap_pre_2p5_init_val [03:00] */
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_MASK 0x000f
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_ALIGN 0
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_BITS 4
 #define CL72_USERB0_CL72_2P5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_SHIFT 0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_tap_limit_control
  */
 /* CL72_UserB0 :: cl72_tap_limit_control :: reserved0 [15:15] */
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_RESERVED0_MASK          0x8000
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_RESERVED0_ALIGN         0
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_RESERVED0_BITS          1
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_RESERVED0_SHIFT         15
 
 /* CL72_UserB0 :: cl72_tap_limit_control :: post_tap_limit [14:10] */
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_MASK     0x7c00
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_ALIGN    0
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_BITS     5
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_SHIFT    10
 
 /* CL72_UserB0 :: cl72_tap_limit_control :: main_tap_limit [09:04] */
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_MASK     0x03f0
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_ALIGN    0
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_BITS     6
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_SHIFT    4
 
 /* CL72_UserB0 :: cl72_tap_limit_control :: pre_tap_limit [03:00] */
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_MASK      0x000f
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_ALIGN     0
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_BITS      4
 #define CL72_USERB0_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_SHIFT     0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_misc3_control
  */
 /* CL72_UserB0 :: cl72_misc3_control :: cl72_en_mask [15:00] */
 #define CL72_USERB0_CL72_MISC3_CONTROL_CL72_EN_MASK_MASK           0xffff
 #define CL72_USERB0_CL72_MISC3_CONTROL_CL72_EN_MASK_ALIGN          0
 #define CL72_USERB0_CL72_MISC3_CONTROL_CL72_EN_MASK_BITS           16
 #define CL72_USERB0_CL72_MISC3_CONTROL_CL72_EN_MASK_SHIFT          0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_tap_preset_control
  */
 /* CL72_UserB0 :: cl72_tap_preset_control :: reserved0 [15:09] */
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_RESERVED0_MASK         0xfe00
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_RESERVED0_ALIGN        0
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_RESERVED0_BITS         7
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_RESERVED0_SHIFT        9
 
 /* CL72_UserB0 :: cl72_tap_preset_control :: pre_init_val [08:05] */
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_MASK      0x01e0
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_ALIGN     0
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_BITS      4
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_SHIFT     5
 
 /* CL72_UserB0 :: cl72_tap_preset_control :: post_init_val [04:00] */
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_MASK     0x001f
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_ALIGN    0
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_BITS     5
 #define CL72_USERB0_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_SHIFT    0
 
 
 /****************************************************************************
  * CL72_UserB0 :: cl72_misc4_control
  */
 /* CL72_UserB0 :: cl72_misc4_control :: reserved0 [15:10] */
 #define CL72_USERB0_CL72_MISC4_CONTROL_RESERVED0_MASK              0xfc00
 #define CL72_USERB0_CL72_MISC4_CONTROL_RESERVED0_ALIGN             0
 #define CL72_USERB0_CL72_MISC4_CONTROL_RESERVED0_BITS              6
 #define CL72_USERB0_CL72_MISC4_CONTROL_RESERVED0_SHIFT             10
 
 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk16_ckgate_off [09:09] */
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_MASK   0x0200
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_ALIGN  0
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_BITS   1
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_SHIFT  9
 
 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk16_legacy_clkmode [08:08] */
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_MASK 0x0100
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_ALIGN 0
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_BITS 1
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_SHIFT 8
 
 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk16_wclk20_per_lane [07:07] */
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_MASK 0x0080
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_ALIGN 0
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_BITS 1
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_SHIFT 7
 
 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk_16_mode_sel [06:05] */
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_MASK    0x0060
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_ALIGN   0
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_BITS    2
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_SHIFT   5
 
 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk33_mode_sel [04:03] */
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_MASK     0x0018
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_ALIGN    0
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_BITS     2
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_SHIFT    3
 
 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk_cl72_rst_sw [02:02] */
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_MASK    0x0004
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_ALIGN   0
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_BITS    1
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_SHIFT   2
 
 /* CL72_UserB0 :: cl72_misc4_control :: rx_wclk_cl72_ckgate_sw [01:01] */
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_MASK 0x0002
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_ALIGN 0
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_BITS 1
 #define CL72_USERB0_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_SHIFT 1
 
 /* CL72_UserB0 :: cl72_misc4_control :: cl72_en_mask [00:00] */
 #define CL72_USERB0_CL72_MISC4_CONTROL_CL72_EN_MASK_MASK           0x0001
 #define CL72_USERB0_CL72_MISC4_CONTROL_CL72_EN_MASK_ALIGN          0
 #define CL72_USERB0_CL72_MISC4_CONTROL_CL72_EN_MASK_BITS           1
 #define CL72_USERB0_CL72_MISC4_CONTROL_CL72_EN_MASK_SHIFT          0
 
 
 /****************************************************************************
  * Warpcore_USER_CL72_UserB1
  */
 /****************************************************************************
  * CL72_UserB1 :: cl72_fault_register
  */
 /* CL72_UserB1 :: cl72_fault_register :: reserved0 [15:04] */
 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED0_MASK             0xfff0
 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED0_ALIGN            0
 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED0_BITS             12
 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED0_SHIFT            4
 
 /* CL72_UserB1 :: cl72_fault_register :: frame_lock [03:03] */
 #define CL72_USERB1_CL72_FAULT_REGISTER_FRAME_LOCK_MASK            0x0008
 #define CL72_USERB1_CL72_FAULT_REGISTER_FRAME_LOCK_ALIGN           0
 #define CL72_USERB1_CL72_FAULT_REGISTER_FRAME_LOCK_BITS            1
 #define CL72_USERB1_CL72_FAULT_REGISTER_FRAME_LOCK_SHIFT           3
 
 /* CL72_UserB1 :: cl72_fault_register :: reserved1 [02:00] */
 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED1_MASK             0x0007
 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED1_ALIGN            0
 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED1_BITS             3
 #define CL72_USERB1_CL72_FAULT_REGISTER_RESERVED1_SHIFT            0
 
 
 /****************************************************************************
  * CL72_UserB1 :: cl72_debug_1_register
  */
 /* CL72_UserB1 :: cl72_debug_1_register :: reserved0 [15:12] */
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_RESERVED0_MASK           0xf000
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_RESERVED0_ALIGN          0
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_RESERVED0_BITS           4
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_RESERVED0_SHIFT          12
 
 /* CL72_UserB1 :: cl72_debug_1_register :: tap_max_val [11:06] */
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_MASK         0x0fc0
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_ALIGN        0
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_BITS         6
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_SHIFT        6
 
 /* CL72_UserB1 :: cl72_debug_1_register :: tap_min_val [05:00] */
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_MASK         0x003f
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_ALIGN        0
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_BITS         6
 #define CL72_USERB1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_SHIFT        0
 
 
 /****************************************************************************
  * CL72_UserB1 :: cl72_debug_2_register
  */
 /* CL72_UserB1 :: cl72_debug_2_register :: pmd_data_swap [15:15] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_MASK       0x8000
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_ALIGN      0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_BITS       1
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_SHIFT      15
 
 /* CL72_UserB1 :: cl72_debug_2_register :: brk_ring_osc_ [14:14] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC__MASK       0x4000
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC__ALIGN      0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC__BITS       1
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC__SHIFT      14
 
 /* CL72_UserB1 :: cl72_debug_2_register :: strict_marker_chk [13:13] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_MASK   0x2000
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_ALIGN  0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_BITS   1
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_SHIFT  13
 
 /* CL72_UserB1 :: cl72_debug_2_register :: strict_dme_chk [12:12] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_MASK      0x1000
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_ALIGN     0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_BITS      1
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_SHIFT     12
 
 /* CL72_UserB1 :: cl72_debug_2_register :: dis_max_wait_timer [11:11] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_MASK  0x0800
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_ALIGN 0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_BITS  1
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_SHIFT 11
 
 /* CL72_UserB1 :: cl72_debug_2_register :: max_wait_timer_val [10:09] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_MASK  0x0600
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_ALIGN 0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_BITS  2
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_SHIFT 9
 
 /* CL72_UserB1 :: cl72_debug_2_register :: signal_det_force [08:08] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_MASK    0x0100
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_ALIGN   0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_BITS    1
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_SHIFT   8
 
 /* CL72_UserB1 :: cl72_debug_2_register :: tr_coarse_lock_force [07:07] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_MASK 0x0080
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_ALIGN 0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_BITS 1
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_SHIFT 7
 
 /* CL72_UserB1 :: cl72_debug_2_register :: clk_gate_force_ [06:06] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__MASK     0x0040
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__ALIGN    0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__BITS     1
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__SHIFT    6
 
 /* CL72_UserB1 :: cl72_debug_2_register :: clk_gate_forceval [05:05] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_MASK   0x0020
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_ALIGN  0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_BITS   1
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_SHIFT  5
 
 /* CL72_UserB1 :: cl72_debug_2_register :: bad_marker_cnt [04:02] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_MASK      0x001c
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_ALIGN     0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_BITS      3
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_SHIFT     2
 
 /* CL72_UserB1 :: cl72_debug_2_register :: good_marker_cnt [01:00] */
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_MASK     0x0003
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_ALIGN    0
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_BITS     2
 #define CL72_USERB1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_SHIFT    0
 
 
 /****************************************************************************
  * CL72_UserB1 :: cl72_debug_3_register
  */
 /* CL72_UserB1 :: cl72_debug_3_register :: signal_ok_force [15:15] */
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_MASK     0x8000
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_ALIGN    0
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_BITS     1
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_SHIFT    15
 
 /* CL72_UserB1 :: cl72_debug_3_register :: ctrl_frame_dly [14:11] */
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_MASK      0x7800
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_ALIGN     0
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_BITS      4
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_SHIFT     11
 
 /* CL72_UserB1 :: cl72_debug_3_register :: random_seed [10:00] */
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_MASK         0x07ff
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_ALIGN        0
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_BITS         11
 #define CL72_USERB1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_SHIFT        0
 
 
 /****************************************************************************
  * CL72_UserB1 :: cl72_debug_4_register
  */
 /* CL72_UserB1 :: cl72_debug_4_register :: reserved0 [15:14] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_RESERVED0_MASK           0xc000
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_RESERVED0_ALIGN          0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_RESERVED0_BITS           2
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_RESERVED0_SHIFT          14
 
 /* CL72_UserB1 :: cl72_debug_4_register :: brcm_mode_force [13:13] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_MASK     0x2000
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_ALIGN    0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_BITS     1
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_SHIFT    13
 
 /* CL72_UserB1 :: cl72_debug_4_register :: brcm_mode_forceval [12:12] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_MASK  0x1000
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_ALIGN 0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_BITS  1
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_SHIFT 12
 
 /* CL72_UserB1 :: cl72_debug_4_register :: v2_constraint_dis [11:11] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_MASK   0x0800
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_ALIGN  0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_BITS   1
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_SHIFT  11
 
 /* CL72_UserB1 :: cl72_debug_4_register :: tap_v2_val [10:06] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_MASK          0x07c0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_ALIGN         0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_BITS          5
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_SHIFT         6
 
 /* CL72_UserB1 :: cl72_debug_4_register :: micro_reg_reset [05:05] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_MASK     0x0020
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_ALIGN    0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_BITS     1
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_SHIFT    5
 
 /* CL72_UserB1 :: cl72_debug_4_register :: sigdet_forceval [04:04] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_MASK     0x0010
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_ALIGN    0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_BITS     1
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_SHIFT    4
 
 /* CL72_UserB1 :: cl72_debug_4_register :: sigdet_force [03:03] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_MASK        0x0008
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_ALIGN       0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_BITS        1
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_SHIFT       3
 
 /* CL72_UserB1 :: cl72_debug_4_register :: trnpat_en_forceval [02:02] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_MASK  0x0004
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_ALIGN 0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_BITS  1
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_SHIFT 2
 
 /* CL72_UserB1 :: cl72_debug_4_register :: trnpat_en_force [01:01] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_MASK     0x0002
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_ALIGN    0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_BITS     1
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_SHIFT    1
 
 /* CL72_UserB1 :: cl72_debug_4_register :: ppm_offset_en [00:00] */
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_MASK       0x0001
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_ALIGN      0
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_BITS       1
 #define CL72_USERB1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_SHIFT      0
 
 
 /****************************************************************************
  * Warpcore_USER_SerdesDigital
  */
 /****************************************************************************
  * SerdesDigital :: Control1000X1
  */
 /* SerdesDigital :: Control1000X1 :: reserved0 [15:15] */
 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_MASK                 0x8000
 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_ALIGN                0
 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_BITS                 1
 #define SERDESDIGITAL_CONTROL1000X1_RESERVED0_SHIFT                15
 
 /* SerdesDigital :: Control1000X1 :: disable_signal_detect_filter [14:14] */
 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK 0x4000
 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN 0
 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS 1
 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT 14
 
 /* SerdesDigital :: Control1000X1 :: reserved1 [13:12] */
 #define SERDESDIGITAL_CONTROL1000X1_RESERVED1_MASK                 0x3000
 #define SERDESDIGITAL_CONTROL1000X1_RESERVED1_ALIGN                0
 #define SERDESDIGITAL_CONTROL1000X1_RESERVED1_BITS                 2
 #define SERDESDIGITAL_CONTROL1000X1_RESERVED1_SHIFT                12
 
 /* SerdesDigital :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */
 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK      0x0800
 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN     0
 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS      1
 #define SERDESDIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT     11
 
 /* SerdesDigital :: Control1000X1 :: remote_loopback [10:10] */
 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_MASK           0x0400
 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN          0
 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_BITS           1
 #define SERDESDIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT          10
 
 /* SerdesDigital :: Control1000X1 :: zero_comma_detector_phase [09:09] */
 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200
 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0
 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1
 #define SERDESDIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9
 
 /* SerdesDigital :: Control1000X1 :: comma_det_en [08:08] */
 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_MASK              0x0100
 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_ALIGN             0
 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_BITS              1
 #define SERDESDIGITAL_CONTROL1000X1_COMMA_DET_EN_SHIFT             8
 
 /* SerdesDigital :: Control1000X1 :: crc_checker_disable [07:07] */
 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK       0x0080
 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN      0
 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS       1
 #define SERDESDIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT      7
 
 /* SerdesDigital :: Control1000X1 :: disable_pll_pwrdwn [06:06] */
 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK        0x0040
 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN       0
 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS        1
 #define SERDESDIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT       6
 
 /* SerdesDigital :: Control1000X1 :: sgmii_master_mode [05:05] */
 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_MASK         0x0020
 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN        0
 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_BITS         1
 #define SERDESDIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT        5
 
 /* SerdesDigital :: Control1000X1 :: autodet_en [04:04] */
 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_MASK                0x0010
 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_ALIGN               0
 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_BITS                1
 #define SERDESDIGITAL_CONTROL1000X1_AUTODET_EN_SHIFT               4
 
 /* SerdesDigital :: Control1000X1 :: invert_signal_detect [03:03] */
 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK      0x0008
 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN     0
 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS      1
 #define SERDESDIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT     3
 
 /* SerdesDigital :: Control1000X1 :: signal_detect_en [02:02] */
 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_MASK          0x0004
 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN         0
 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_BITS          1
 #define SERDESDIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT         2
 
 /* SerdesDigital :: Control1000X1 :: tbi_interface [01:01] */
 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_MASK             0x0002
 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_ALIGN            0
 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_BITS             1
 #define SERDESDIGITAL_CONTROL1000X1_TBI_INTERFACE_SHIFT            1
 
 /* SerdesDigital :: Control1000X1 :: fiber_mode_1000X [00:00] */
 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_MASK          0x0001
 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_ALIGN         0
 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_BITS          1
 #define SERDESDIGITAL_CONTROL1000X1_FIBER_MODE_1000X_SHIFT         0
 
 
 /****************************************************************************
  * SerdesDigital :: Control1000X2
  */
 /* SerdesDigital :: Control1000X2 :: disable_extend_fdx_only [15:15] */
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK   0x8000
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN  0
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS   1
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT  15
 
 /* SerdesDigital :: Control1000X2 :: clear_ber_counter [14:14] */
 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_MASK         0x4000
 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN        0
 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_BITS         1
 #define SERDESDIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT        14
 
 /* SerdesDigital :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */
 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK 0x2000
 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN 0
 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS 1
 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT 13
 
 /* SerdesDigital :: Control1000X2 :: transmit_packet_seq_test [12:12] */
 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK  0x1000
 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN 0
 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS  1
 #define SERDESDIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT 12
 
 /* SerdesDigital :: Control1000X2 :: test_cntr [11:11] */
 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_MASK                 0x0800
 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_ALIGN                0
 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_BITS                 1
 #define SERDESDIGITAL_CONTROL1000X2_TEST_CNTR_SHIFT                11
 
 /* SerdesDigital :: Control1000X2 :: bypass_pcs_tx [10:10] */
 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_MASK             0x0400
 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_ALIGN            0
 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_BITS             1
 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_TX_SHIFT            10
 
 /* SerdesDigital :: Control1000X2 :: bypass_pcs_rx [09:09] */
 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_MASK             0x0200
 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_ALIGN            0
 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_BITS             1
 #define SERDESDIGITAL_CONTROL1000X2_BYPASS_PCS_RX_SHIFT            9
 
 /* SerdesDigital :: Control1000X2 :: disable_TRRR_generation [08:08] */
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK   0x0100
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN  0
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS   1
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT  8
 
 /* SerdesDigital :: Control1000X2 :: disable_carrier_extend [07:07] */
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK    0x0080
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN   0
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS    1
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT   7
 
 /* SerdesDigital :: Control1000X2 :: autoneg_fast_timers [06:06] */
 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK       0x0040
 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN      0
 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS       1
 #define SERDESDIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT      6
 
 /* SerdesDigital :: Control1000X2 :: force_xmit_data_on_txside [05:05] */
 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK 0x0020
 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN 0
 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS 1
 #define SERDESDIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT 5
 
 /* SerdesDigital :: Control1000X2 :: disable_remote_fault_sensing [04:04] */
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK 0x0010
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN 0
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS 1
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT 4
 
 /* SerdesDigital :: Control1000X2 :: enable_autoneg_err_timer [03:03] */
 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK  0x0008
 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0
 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS  1
 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3
 
 /* SerdesDigital :: Control1000X2 :: filter_force_link [02:02] */
 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_MASK         0x0004
 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN        0
 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_BITS         1
 #define SERDESDIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT        2
 
 /* SerdesDigital :: Control1000X2 :: disable_false_link [01:01] */
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_MASK        0x0002
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN       0
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_BITS        1
 #define SERDESDIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT       1
 
 /* SerdesDigital :: Control1000X2 :: enable_parallel_detection [00:00] */
 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_MASK 0x0001
 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_ALIGN 0
 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_BITS 1
 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_SHIFT 0
 
 
 /****************************************************************************
  * SerdesDigital :: Control1000X3
  */
 /* SerdesDigital :: Control1000X3 :: disable_packet_misalign [15:15] */
 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK   0x8000
 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN  0
 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS   1
 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT  15
 
 /* SerdesDigital :: Control1000X3 :: rxfifo_gmii_reset [14:14] */
 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_MASK         0x4000
 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN        0
 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_BITS         1
 #define SERDESDIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT        14
 
 /* SerdesDigital :: Control1000X3 :: disable_tx_crs [13:13] */
 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_MASK            0x2000
 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_ALIGN           0
 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_BITS            1
 #define SERDESDIGITAL_CONTROL1000X3_DISABLE_TX_CRS_SHIFT           13
 
 /* SerdesDigital :: Control1000X3 :: invert_ext_phy_crs [12:12] */
 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK        0x1000
 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN       0
 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS        1
 #define SERDESDIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT       12
 
 /* SerdesDigital :: Control1000X3 :: ext_phy_crs_mode [11:11] */
 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK          0x0800
 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN         0
 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS          1
 #define SERDESDIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT         11
 
 /* SerdesDigital :: Control1000X3 :: jam_false_carrier_mode [10:10] */
 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK    0x0400
 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN   0
 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS    1
 #define SERDESDIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT   10
 
 /* SerdesDigital :: Control1000X3 :: block_txen_mode [09:09] */
 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_MASK           0x0200
 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN          0
 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_BITS           1
 #define SERDESDIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT          9
 
 /* SerdesDigital :: Control1000X3 :: force_txfifo_on [08:08] */
 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_MASK           0x0100
 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN          0
 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_BITS           1
 #define SERDESDIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT          8
 
 /* SerdesDigital :: Control1000X3 :: bypass_txfifo1000 [07:07] */
 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_MASK         0x0080
 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN        0
 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_BITS         1
 #define SERDESDIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT        7
 
 /* SerdesDigital :: Control1000X3 :: freq_lock_elasticity_tx [06:06] */
 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_MASK   0x0040
 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_ALIGN  0
 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_BITS   1
 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_SHIFT  6
 
 /* SerdesDigital :: Control1000X3 :: freq_lock_elasticity_rx [05:05] */
 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_MASK   0x0020
 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_ALIGN  0
 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_BITS   1
 #define SERDESDIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_SHIFT  5
 
 /* SerdesDigital :: Control1000X3 :: early_preamble_rx [04:04] */
 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK         0x0010
 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN        0
 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS         1
 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT        4
 
 /* SerdesDigital :: Control1000X3 :: early_preamble_tx [03:03] */
 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK         0x0008
 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN        0
 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS         1
 #define SERDESDIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT        3
 
 /* SerdesDigital :: Control1000X3 :: fifo_elasicity_tx [02:01] */
 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_MASK         0x0006
 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_ALIGN        0
 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_BITS         2
 #define SERDESDIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_SHIFT        1
 
 /* SerdesDigital :: Control1000X3 :: tx_fifo_rst [00:00] */
 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_MASK               0x0001
 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_ALIGN              0
 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_BITS               1
 #define SERDESDIGITAL_CONTROL1000X3_TX_FIFO_RST_SHIFT              0
 
 
 /****************************************************************************
  * SerdesDigital :: Control1000X4
  */
 /* SerdesDigital :: Control1000X4 :: reserved0 [15:14] */
 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_MASK                 0xc000
 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_ALIGN                0
 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_BITS                 2
 #define SERDESDIGITAL_CONTROL1000X4_RESERVED0_SHIFT                14
 
 /* SerdesDigital :: Control1000X4 :: disable_resolution_err_restart [13:13] */
 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK 0x2000
 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0
 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS 1
 #define SERDESDIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13
 
 /* SerdesDigital :: Control1000X4 :: enable_last_resolution_err [12:12] */
 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK 0x1000
 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN 0
 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS 1
 #define SERDESDIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT 12
 
 /* SerdesDigital :: Control1000X4 :: tx_config_reg_sel [11:11] */
 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK         0x0800
 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN        0
 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS         1
 #define SERDESDIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT        11
 
 /* SerdesDigital :: Control1000X4 :: zero_rxdgmii [10:10] */
 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_MASK              0x0400
 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_ALIGN             0
 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_BITS              1
 #define SERDESDIGITAL_CONTROL1000X4_ZERO_RXDGMII_SHIFT             10
 
 /* SerdesDigital :: Control1000X4 :: clear_linkdown [09:09] */
 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_MASK            0x0200
 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN           0
 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_BITS            1
 #define SERDESDIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT           9
 
 /* SerdesDigital :: Control1000X4 :: latch_linkdown_enable [08:08] */
 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK     0x0100
 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN    0
 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS     1
 #define SERDESDIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT    8
 
 /* SerdesDigital :: Control1000X4 :: link_force [07:07] */
 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_MASK                0x0080
 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_ALIGN               0
 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_BITS                1
 #define SERDESDIGITAL_CONTROL1000X4_LINK_FORCE_SHIFT               7
 
 /* SerdesDigital :: Control1000X4 :: reserved1 [06:06] */
 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_MASK                 0x0040
 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_ALIGN                0
 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_BITS                 1
 #define SERDESDIGITAL_CONTROL1000X4_RESERVED1_SHIFT                6
 
 /* SerdesDigital :: Control1000X4 :: lp_next_page_sel [05:05] */
 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_MASK          0x0020
 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_ALIGN         0
 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_BITS          1
 #define SERDESDIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_SHIFT         5
 
 /* SerdesDigital :: Control1000X4 :: np_count_ClrnBp [04:04] */
 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_MASK           0x0010
 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_ALIGN          0
 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_BITS           1
 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_SHIFT          4
 
 /* SerdesDigital :: Control1000X4 :: np_count_ClrnRd [03:03] */
 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_MASK           0x0008
 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_ALIGN          0
 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_BITS           1
 #define SERDESDIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_SHIFT          3
 
 /* SerdesDigital :: Control1000X4 :: MiscRxStatus_sel [02:00] */
 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_MASK          0x0007
 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN         0
 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_BITS          3
 #define SERDESDIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT         0
 
 
 /****************************************************************************
  * SerdesDigital :: Status1000X1
  */
 /* SerdesDigital :: Status1000X1 :: txfifo_err_detected [15:15] */
 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK        0x8000
 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN       0
 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS        1
 #define SERDESDIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT       15
 
 /* SerdesDigital :: Status1000X1 :: rxfifo_err_detected [14:14] */
 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK        0x4000
 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN       0
 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS        1
 #define SERDESDIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT       14
 
 /* SerdesDigital :: Status1000X1 :: false_carrier_detected [13:13] */
 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK     0x2000
 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN    0
 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS     1
 #define SERDESDIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT    13
 
 /* SerdesDigital :: Status1000X1 :: crc_err_detected [12:12] */
 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_MASK           0x1000
 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_ALIGN          0
 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_BITS           1
 #define SERDESDIGITAL_STATUS1000X1_CRC_ERR_DETECTED_SHIFT          12
 
 /* SerdesDigital :: Status1000X1 :: tx_err_detected [11:11] */
 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_MASK            0x0800
 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_ALIGN           0
 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_BITS            1
 #define SERDESDIGITAL_STATUS1000X1_TX_ERR_DETECTED_SHIFT           11
 
 /* SerdesDigital :: Status1000X1 :: rx_err_detected [10:10] */
 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_MASK            0x0400
 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_ALIGN           0
 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_BITS            1
 #define SERDESDIGITAL_STATUS1000X1_RX_ERR_DETECTED_SHIFT           10
 
 /* SerdesDigital :: Status1000X1 :: carrier_extend_err_detected [09:09] */
 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200
 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0
 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1
 #define SERDESDIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9
 
 /* SerdesDigital :: Status1000X1 :: early_end_extension_detected [08:08] */
 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100
 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0
 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1
 #define SERDESDIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8
 
 /* SerdesDigital :: Status1000X1 :: link_status_change [07:07] */
 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_MASK         0x0080
 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN        0
 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_BITS         1
 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT        7
 
 /* SerdesDigital :: Status1000X1 :: pause_resolution_rxside [06:06] */
 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK    0x0040
 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN   0
 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS    1
 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT   6
 
 /* SerdesDigital :: Status1000X1 :: pause_resolution_txside [05:05] */
 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK    0x0020
 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN   0
 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS    1
 #define SERDESDIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT   5
 
 /* SerdesDigital :: Status1000X1 :: speed_status [04:03] */
 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_MASK               0x0018
 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_ALIGN              0
 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_BITS               2
 #define SERDESDIGITAL_STATUS1000X1_SPEED_STATUS_SHIFT              3
 
 /* SerdesDigital :: Status1000X1 :: duplex_status [02:02] */
 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_MASK              0x0004
 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_ALIGN             0
 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_BITS              1
 #define SERDESDIGITAL_STATUS1000X1_DUPLEX_STATUS_SHIFT             2
 
 /* SerdesDigital :: Status1000X1 :: link_status [01:01] */
 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_MASK                0x0002
 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_ALIGN               0
 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_BITS                1
 #define SERDESDIGITAL_STATUS1000X1_LINK_STATUS_SHIFT               1
 
 /* SerdesDigital :: Status1000X1 :: sgmii_mode [00:00] */
 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_MASK                 0x0001
 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_ALIGN                0
 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_BITS                 1
 #define SERDESDIGITAL_STATUS1000X1_SGMII_MODE_SHIFT                0
 
 
 /****************************************************************************
  * SerdesDigital :: Status1000X2
  */
 /* SerdesDigital :: Status1000X2 :: sgmii_mode_change [15:15] */
 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_MASK          0x8000
 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN         0
 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_BITS          1
 #define SERDESDIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT         15
 
 /* SerdesDigital :: Status1000X2 :: consistency_mismatch [14:14] */
 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_MASK       0x4000
 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN      0
 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_BITS       1
 #define SERDESDIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT      14
 
 /* SerdesDigital :: Status1000X2 :: autoneg_resolution_err [13:13] */
 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK     0x2000
 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN    0
 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS     1
 #define SERDESDIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT    13
 
 /* SerdesDigital :: Status1000X2 :: sgmii_selector_mismatch [12:12] */
 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK    0x1000
 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN   0
 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS    1
 #define SERDESDIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT   12
 
 /* SerdesDigital :: Status1000X2 :: sync_status_fail [11:11] */
 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_MASK           0x0800
 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN          0
 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_BITS           1
 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT          11
 
 /* SerdesDigital :: Status1000X2 :: sync_status_ok [10:10] */
 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_MASK             0x0400
 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_ALIGN            0
 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_BITS             1
 #define SERDESDIGITAL_STATUS1000X2_SYNC_STATUS_OK_SHIFT            10
 
 /* SerdesDigital :: Status1000X2 :: rudi_c [09:09] */
 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_MASK                     0x0200
 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_ALIGN                    0
 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_BITS                     1
 #define SERDESDIGITAL_STATUS1000X2_RUDI_C_SHIFT                    9
 
 /* SerdesDigital :: Status1000X2 :: rudi_I [08:08] */
 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_MASK                     0x0100
 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_ALIGN                    0
 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_BITS                     1
 #define SERDESDIGITAL_STATUS1000X2_RUDI_I_SHIFT                    8
 
 /* SerdesDigital :: Status1000X2 :: rudi_invalid [07:07] */
 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_MASK               0x0080
 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_ALIGN              0
 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_BITS               1
 #define SERDESDIGITAL_STATUS1000X2_RUDI_INVALID_SHIFT              7
 
 /* SerdesDigital :: Status1000X2 :: linkDown_syncLoss [06:06] */
 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK          0x0040
 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN         0
 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS          1
 #define SERDESDIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT         6
 
 /* SerdesDigital :: Status1000X2 :: idle_detect_state [05:05] */
 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_MASK          0x0020
 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_ALIGN         0
 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_BITS          1
 #define SERDESDIGITAL_STATUS1000X2_IDLE_DETECT_STATE_SHIFT         5
 
 /* SerdesDigital :: Status1000X2 :: complete_acknowledge_state [04:04] */
 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010
 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0
 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1
 #define SERDESDIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4
 
 /* SerdesDigital :: Status1000X2 :: acknowledge_detect_state [03:03] */
 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK   0x0008
 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN  0
 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS   1
 #define SERDESDIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT  3
 
 /* SerdesDigital :: Status1000X2 :: ability_detect_state [02:02] */
 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_MASK       0x0004
 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN      0
 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_BITS       1
 #define SERDESDIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT      2
 
 /* union - case anError [01:01] */
 /* SerdesDigital :: Status1000X2 :: an_error_state [01:01] */
 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK     0x0002
 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN    0
 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS     1
 #define SERDESDIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT    1
 
 
 /* union - case anDisableLink [01:01] */
 /* SerdesDigital :: Status1000X2 :: an_disable_link_ok_state [01:01] */
 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002
 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0
 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1
 #define SERDESDIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1
 
 
 /* SerdesDigital :: Status1000X2 :: an_enable_state [00:00] */
 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_MASK            0x0001
 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_ALIGN           0
 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_BITS            1
 #define SERDESDIGITAL_STATUS1000X2_AN_ENABLE_STATE_SHIFT           0
 
 
 /****************************************************************************
  * SerdesDigital :: Status1000X3
  */
 /* SerdesDigital :: Status1000X3 :: reserved0 [15:13] */
 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_MASK                  0xe000
 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_ALIGN                 0
 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_BITS                  3
 #define SERDESDIGITAL_STATUS1000X3_RESERVED0_SHIFT                 13
 
 /* SerdesDigital :: Status1000X3 :: pd_park_an [12:12] */
 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_MASK                 0x1000
 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_ALIGN                0
 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_BITS                 1
 #define SERDESDIGITAL_STATUS1000X3_PD_PARK_AN_SHIFT                12
 
 /* SerdesDigital :: Status1000X3 :: remotePhy_autosel [11:11] */
 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK          0x0800
 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN         0
 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS          1
 #define SERDESDIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT         11
 
 /* SerdesDigital :: Status1000X3 :: latch_linkdown [10:10] */
 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_MASK             0x0400
 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_ALIGN            0
 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_BITS             1
 #define SERDESDIGITAL_STATUS1000X3_LATCH_LINKDOWN_SHIFT            10
 
 /* SerdesDigital :: Status1000X3 :: sd_filter [09:09] */
 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_MASK                  0x0200
 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_ALIGN                 0
 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_BITS                  1
 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_SHIFT                 9
 
 /* SerdesDigital :: Status1000X3 :: sd_mux [08:08] */
 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_MASK                     0x0100
 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_ALIGN                    0
 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_BITS                     1
 #define SERDESDIGITAL_STATUS1000X3_SD_MUX_SHIFT                    8
 
 /* SerdesDigital :: Status1000X3 :: sd_filter_chg [07:07] */
 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_MASK              0x0080
 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_ALIGN             0
 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_BITS              1
 #define SERDESDIGITAL_STATUS1000X3_SD_FILTER_CHG_SHIFT             7
 
 /* SerdesDigital :: Status1000X3 :: reserved1 [06:00] */
 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_MASK                  0x007f
 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_ALIGN                 0
 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_BITS                  7
 #define SERDESDIGITAL_STATUS1000X3_RESERVED1_SHIFT                 0
 
 
 /****************************************************************************
  * SerdesDigital :: BadCodeGroup
  */
 /* SerdesDigital :: BadCodeGroup :: badCodeGroups [15:08] */
 #define SERDESDIGITAL_BADCODEGROUP_BADCODEGROUPS_MASK              0xff00
 #define SERDESDIGITAL_BADCODEGROUP_BADCODEGROUPS_ALIGN             0
 #define SERDESDIGITAL_BADCODEGROUP_BADCODEGROUPS_BITS              8
 #define SERDESDIGITAL_BADCODEGROUP_BADCODEGROUPS_SHIFT             8
 
 /* SerdesDigital :: BadCodeGroup :: reserved0 [07:00] */
 #define SERDESDIGITAL_BADCODEGROUP_RESERVED0_MASK                  0x00ff
 #define SERDESDIGITAL_BADCODEGROUP_RESERVED0_ALIGN                 0
 #define SERDESDIGITAL_BADCODEGROUP_RESERVED0_BITS                  8
 #define SERDESDIGITAL_BADCODEGROUP_RESERVED0_SHIFT                 0
 
 
 /****************************************************************************
  * SerdesDigital :: Misc1
  */
 /* SerdesDigital :: Misc1 :: refclk_sel [15:13] */
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_MASK                        0xe000
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_ALIGN                       0
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_BITS                        3
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_SHIFT                       13
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_25MHz                   0
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_100MHz                  1
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_125MHz                  2
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_156p25MHz               3
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_187p5MHz                4
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_161p25Mhz               5
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_50Mhz                   6
 #define SERDESDIGITAL_MISC1_REFCLK_SEL_clk_106p25Mhz               7
 
 /* SerdesDigital :: Misc1 :: force_pll_mode_afe_sel [12:12] */
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_MASK            0x1000
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_ALIGN           0
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_BITS            1
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_SHIFT           12
 
 /* SerdesDigital :: Misc1 :: force_pll_mode_afe [11:08] */
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_MASK                0x0f00
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_ALIGN               0
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_BITS                4
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_SHIFT               8
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div32               0
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div36               1
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div40               2
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div42               3
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div48               4
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div50               5
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div52               6
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div54               7
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div60               8
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div64               9
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div66               10
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div68               11
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div80               12
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div120              13
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div200              14
 #define SERDESDIGITAL_MISC1_FORCE_PLL_MODE_AFE_div240              15
 
 /* SerdesDigital :: Misc1 :: force_tick0_sw2 [07:07] */
 #define SERDESDIGITAL_MISC1_FORCE_TICK0_SW2_MASK                   0x0080
 #define SERDESDIGITAL_MISC1_FORCE_TICK0_SW2_ALIGN                  0
 #define SERDESDIGITAL_MISC1_FORCE_TICK0_SW2_BITS                   1
 #define SERDESDIGITAL_MISC1_FORCE_TICK0_SW2_SHIFT                  7
 
 /* SerdesDigital :: Misc1 :: tx_underrun_1000_dis [06:06] */
 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_MASK              0x0040
 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_ALIGN             0
 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_BITS              1
 #define SERDESDIGITAL_MISC1_TX_UNDERRUN_1000_DIS_SHIFT             6
 
 /* SerdesDigital :: Misc1 :: force_ln_mode [05:05] */
 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_MASK                     0x0020
 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_ALIGN                    0
 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_BITS                     1
 #define SERDESDIGITAL_MISC1_FORCE_LN_MODE_SHIFT                    5
 
 /* SerdesDigital :: Misc1 :: force_speed [04:00] */
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_MASK                       0x001f
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_ALIGN                      0
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_BITS                       5
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SHIFT                      0
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_2500BRCM_X1             16
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X4             17
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_6000BRCM_X4             18
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10GHiGig_X4             19
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10GBASE_CX4             20
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_12GHiGig_X4             21
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_12p5GHiGig_X4           22
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_13GHiGig_X4             23
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_15GHiGig_X4             24
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_16GHiGig_X4             25
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X1             26
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_6363BRCM_X1             27
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_20GHiGig_X4             28
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_21GHiGig_X4             29
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_25p45GHiGig_X4          30
 #define SERDESDIGITAL_MISC1_FORCE_SPEED_dr_10G_HiG_DXGXS           31
 
 
 /****************************************************************************
  * SerdesDigital :: Misc2
  */
 /* SerdesDigital :: Misc2 :: rxckpl_sel_combo [15:15] */
 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_MASK                  0x8000
 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_ALIGN                 0
 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_BITS                  1
 #define SERDESDIGITAL_MISC2_RXCKPL_SEL_COMBO_SHIFT                 15
 
 /* SerdesDigital :: Misc2 :: rxck_mii_gen_sel_force [14:14] */
 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_MASK            0x4000
 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_ALIGN           0
 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_BITS            1
 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_SHIFT           14
 
 /* SerdesDigital :: Misc2 :: rxck_mii_gen_sel_val [13:13] */
 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_MASK              0x2000
 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_ALIGN             0
 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_BITS              1
 #define SERDESDIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_SHIFT             13
 
 /* SerdesDigital :: Misc2 :: rlpbk_sw_force [12:12] */
 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_MASK                    0x1000
 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_ALIGN                   0
 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_BITS                    1
 #define SERDESDIGITAL_MISC2_RLPBK_SW_FORCE_SHIFT                   12
 
 /* SerdesDigital :: Misc2 :: rlpbk_RxRst_en [11:11] */
 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_MASK                    0x0800
 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_ALIGN                   0
 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_BITS                    1
 #define SERDESDIGITAL_MISC2_RLPBK_RXRST_EN_SHIFT                   11
 
 /* SerdesDigital :: Misc2 :: clkSigdet_bypass [10:10] */
 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_MASK                  0x0400
 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_ALIGN                 0
 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_BITS                  1
 #define SERDESDIGITAL_MISC2_CLKSIGDET_BYPASS_SHIFT                 10
 
 /* SerdesDigital :: Misc2 :: clk41_bypass [09:09] */
 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_MASK                      0x0200
 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_ALIGN                     0
 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_BITS                      1
 #define SERDESDIGITAL_MISC2_CLK41_BYPASS_SHIFT                     9
 
 /* SerdesDigital :: Misc2 :: miiGmiiDly_en [08:08] */
 #define SERDESDIGITAL_MISC2_MIIGMIIDLY_EN_MASK                     0x0100
 #define SERDESDIGITAL_MISC2_MIIGMIIDLY_EN_ALIGN                    0
 #define SERDESDIGITAL_MISC2_MIIGMIIDLY_EN_BITS                     1
 #define SERDESDIGITAL_MISC2_MIIGMIIDLY_EN_SHIFT                    8
 
 /* SerdesDigital :: Misc2 :: miiGmiiMux_en [07:07] */
 #define SERDESDIGITAL_MISC2_MIIGMIIMUX_EN_MASK                     0x0080
 #define SERDESDIGITAL_MISC2_MIIGMIIMUX_EN_ALIGN                    0
 #define SERDESDIGITAL_MISC2_MIIGMIIMUX_EN_BITS                     1
 #define SERDESDIGITAL_MISC2_MIIGMIIMUX_EN_SHIFT                    7
 
 /* SerdesDigital :: Misc2 :: KX_cl73_an_en [06:06] */
 #define SERDESDIGITAL_MISC2_KX_CL73_AN_EN_MASK                     0x0040
 #define SERDESDIGITAL_MISC2_KX_CL73_AN_EN_ALIGN                    0
 #define SERDESDIGITAL_MISC2_KX_CL73_AN_EN_BITS                     1
 #define SERDESDIGITAL_MISC2_KX_CL73_AN_EN_SHIFT                    6
 
 /* SerdesDigital :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */
 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK       0x0020
 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN      0
 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS       1
 #define SERDESDIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT      5
 
 /* SerdesDigital :: Misc2 :: fifo_err_cya [04:04] */
 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_MASK                      0x0010
 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_ALIGN                     0
 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_BITS                      1
 #define SERDESDIGITAL_MISC2_FIFO_ERR_CYA_SHIFT                     4
 
 /* SerdesDigital :: Misc2 :: an_txdisablePhase [03:03] */
 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_MASK                 0x0008
 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_ALIGN                0
 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_BITS                 1
 #define SERDESDIGITAL_MISC2_AN_TXDISABLEPHASE_SHIFT                3
 
 /* SerdesDigital :: Misc2 :: an_rxSeqStartDis [02:02] */
 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_MASK                  0x0004
 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_ALIGN                 0
 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_BITS                  1
 #define SERDESDIGITAL_MISC2_AN_RXSEQSTARTDIS_SHIFT                 2
 
 /* SerdesDigital :: Misc2 :: an_txdisable_ln [01:01] */
 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_MASK                   0x0002
 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_ALIGN                  0
 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_BITS                   1
 #define SERDESDIGITAL_MISC2_AN_TXDISABLE_LN_SHIFT                  1
 
 /* SerdesDigital :: Misc2 :: an_deadTrap [00:00] */
 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_MASK                       0x0001
 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_ALIGN                      0
 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_BITS                       1
 #define SERDESDIGITAL_MISC2_AN_DEADTRAP_SHIFT                      0
 
 
 /****************************************************************************
  * SerdesDigital :: PatGenCtrl
  */
 /* SerdesDigital :: PatGenCtrl :: patgen_lpi_en [15:15] */
 #define SERDESDIGITAL_PATGENCTRL_PATGEN_LPI_EN_MASK                0x8000
 #define SERDESDIGITAL_PATGENCTRL_PATGEN_LPI_EN_ALIGN               0
 #define SERDESDIGITAL_PATGENCTRL_PATGEN_LPI_EN_BITS                1
 #define SERDESDIGITAL_PATGENCTRL_PATGEN_LPI_EN_SHIFT               15
 
 /* SerdesDigital :: PatGenCtrl :: tx_err [14:14] */
 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_MASK                       0x4000
 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_ALIGN                      0
 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_BITS                       1
 #define SERDESDIGITAL_PATGENCTRL_TX_ERR_SHIFT                      14
 
 /* SerdesDigital :: PatGenCtrl :: skip_crc [13:13] */
 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_MASK                     0x2000
 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_ALIGN                    0
 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_BITS                     1
 #define SERDESDIGITAL_PATGENCTRL_SKIP_CRC_SHIFT                    13
 
 /* SerdesDigital :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */
 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK 0x1000
 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN 0
 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS 1
 #define SERDESDIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT 12
 
 /* SerdesDigital :: PatGenCtrl :: ipg_select [11:09] */
 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_MASK                   0x0e00
 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_ALIGN                  0
 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_BITS                   3
 #define SERDESDIGITAL_PATGENCTRL_IPG_SELECT_SHIFT                  9
 
 /* SerdesDigital :: PatGenCtrl :: pkt_size [08:03] */
 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_MASK                     0x01f8
 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_ALIGN                    0
 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_BITS                     6
 #define SERDESDIGITAL_PATGENCTRL_PKT_SIZE_SHIFT                    3
 
 /* SerdesDigital :: PatGenCtrl :: single_pass_mode [02:02] */
 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_MASK             0x0004
 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_ALIGN            0
 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_BITS             1
 #define SERDESDIGITAL_PATGENCTRL_SINGLE_PASS_MODE_SHIFT            2
 
 /* SerdesDigital :: PatGenCtrl :: run_pattern_gen [01:01] */
 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_MASK              0x0002
 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_ALIGN             0
 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_BITS              1
 #define SERDESDIGITAL_PATGENCTRL_RUN_PATTERN_GEN_SHIFT             1
 
 /* SerdesDigital :: PatGenCtrl :: sel_pattern_gen_data [00:00] */
 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK         0x0001
 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN        0
 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS         1
 #define SERDESDIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT        0
 
 
 /****************************************************************************
  * SerdesDigital :: PatGenStat
  */
 /* SerdesDigital :: PatGenStat :: reserved0 [15:04] */
 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_MASK                    0xfff0
 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_ALIGN                   0
 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_BITS                    12
 #define SERDESDIGITAL_PATGENSTAT_RESERVED0_SHIFT                   4
 
 /* SerdesDigital :: PatGenStat :: pattern_gen_active [03:03] */
 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK           0x0008
 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN          0
 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS           1
 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT          3
 
 /* SerdesDigital :: PatGenStat :: pattern_gen_fsm [02:00] */
 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_MASK              0x0007
 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_ALIGN             0
 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_BITS              3
 #define SERDESDIGITAL_PATGENSTAT_PATTERN_GEN_FSM_SHIFT             0
 
 
 /****************************************************************************
  * SerdesDigital :: TestMode
  */
 /* SerdesDigital :: TestMode :: disable_reset_cnt [15:15] */
 #define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_MASK              0x8000
 #define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_ALIGN             0
 #define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_BITS              1
 #define SERDESDIGITAL_TESTMODE_DISABLE_RESET_CNT_SHIFT             15
 
 /* SerdesDigital :: TestMode :: clear_packet_counters [14:14] */
 #define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_MASK          0x4000
 #define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_ALIGN         0
 #define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_BITS          1
 #define SERDESDIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_SHIFT         14
 
 /* SerdesDigital :: TestMode :: reserved0 [13:05] */
 #define SERDESDIGITAL_TESTMODE_RESERVED0_MASK                      0x3fe0
 #define SERDESDIGITAL_TESTMODE_RESERVED0_ALIGN                     0
 #define SERDESDIGITAL_TESTMODE_RESERVED0_BITS                      9
 #define SERDESDIGITAL_TESTMODE_RESERVED0_SHIFT                     5
 
 /* SerdesDigital :: TestMode :: fifo_fsm_cya_rx [04:04] */
 #define SERDESDIGITAL_TESTMODE_FIFO_FSM_CYA_RX_MASK                0x0010
 #define SERDESDIGITAL_TESTMODE_FIFO_FSM_CYA_RX_ALIGN               0
 #define SERDESDIGITAL_TESTMODE_FIFO_FSM_CYA_RX_BITS                1
 #define SERDESDIGITAL_TESTMODE_FIFO_FSM_CYA_RX_SHIFT               4
 
 /* SerdesDigital :: TestMode :: dig1000x_afrst_cya [03:03] */
 #define SERDESDIGITAL_TESTMODE_DIG1000X_AFRST_CYA_MASK             0x0008
 #define SERDESDIGITAL_TESTMODE_DIG1000X_AFRST_CYA_ALIGN            0
 #define SERDESDIGITAL_TESTMODE_DIG1000X_AFRST_CYA_BITS             1
 #define SERDESDIGITAL_TESTMODE_DIG1000X_AFRST_CYA_SHIFT            3
 
 /* SerdesDigital :: TestMode :: fifo_elasicity_rx [02:01] */
 #define SERDESDIGITAL_TESTMODE_FIFO_ELASICITY_RX_MASK              0x0006
 #define SERDESDIGITAL_TESTMODE_FIFO_ELASICITY_RX_ALIGN             0
 #define SERDESDIGITAL_TESTMODE_FIFO_ELASICITY_RX_BITS              2
 #define SERDESDIGITAL_TESTMODE_FIFO_ELASICITY_RX_SHIFT             1
 
 /* SerdesDigital :: TestMode :: fifo_ipg_rx_cya [00:00] */
 #define SERDESDIGITAL_TESTMODE_FIFO_IPG_RX_CYA_MASK                0x0001
 #define SERDESDIGITAL_TESTMODE_FIFO_IPG_RX_CYA_ALIGN               0
 #define SERDESDIGITAL_TESTMODE_FIFO_IPG_RX_CYA_BITS                1
 #define SERDESDIGITAL_TESTMODE_FIFO_IPG_RX_CYA_SHIFT               0
 
 
 /****************************************************************************
  * SerdesDigital :: TxPktCnt
  */
 /* SerdesDigital :: TxPktCnt :: TxPktCnt [15:00] */
 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_MASK                       0xffff
 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_ALIGN                      0
 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_BITS                       16
 #define SERDESDIGITAL_TXPKTCNT_TXPKTCNT_SHIFT                      0
 
 
 /****************************************************************************
  * SerdesDigital :: RxPktCnt
  */
 /* SerdesDigital :: RxPktCnt :: RxPktCnt [15:00] */
 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_MASK                       0xffff
 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_ALIGN                      0
 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_BITS                       16
 #define SERDESDIGITAL_RXPKTCNT_RXPKTCNT_SHIFT                      0
 
 
 /****************************************************************************
  * Warpcore_USER_SerdesID
  */
 /****************************************************************************
  * SerdesID :: serdesID0
  */
 /* SerdesID :: serdesID0 :: rev_letter [15:14] */
 #define SERDESID_SERDESID0_REV_LETTER_MASK                         0xc000
 #define SERDESID_SERDESID0_REV_LETTER_ALIGN                        0
 #define SERDESID_SERDESID0_REV_LETTER_BITS                         2
 #define SERDESID_SERDESID0_REV_LETTER_SHIFT                        14
 
 /* SerdesID :: serdesID0 :: rev_number [13:11] */
 #define SERDESID_SERDESID0_REV_NUMBER_MASK                         0x3800
 #define SERDESID_SERDESID0_REV_NUMBER_ALIGN                        0
 #define SERDESID_SERDESID0_REV_NUMBER_BITS                         3
 #define SERDESID_SERDESID0_REV_NUMBER_SHIFT                        11
 
 /* SerdesID :: serdesID0 :: bonding [10:09] */
 #define SERDESID_SERDESID0_BONDING_MASK                            0x0600
 #define SERDESID_SERDESID0_BONDING_ALIGN                           0
 #define SERDESID_SERDESID0_BONDING_BITS                            2
 #define SERDESID_SERDESID0_BONDING_SHIFT                           9
 
 /* SerdesID :: serdesID0 :: tech_proc [08:06] */
 #define SERDESID_SERDESID0_TECH_PROC_MASK                          0x01c0
 #define SERDESID_SERDESID0_TECH_PROC_ALIGN                         0
 #define SERDESID_SERDESID0_TECH_PROC_BITS                          3
 #define SERDESID_SERDESID0_TECH_PROC_SHIFT                         6
 
 /* SerdesID :: serdesID0 :: model_number [05:00] */
 #define SERDESID_SERDESID0_MODEL_NUMBER_MASK                       0x003f
 #define SERDESID_SERDESID0_MODEL_NUMBER_ALIGN                      0
 #define SERDESID_SERDESID0_MODEL_NUMBER_BITS                       6
 #define SERDESID_SERDESID0_MODEL_NUMBER_SHIFT                      0
 
 
 /****************************************************************************
  * SerdesID :: serdesID1
  */
 /* SerdesID :: serdesID1 :: multiplicity [15:12] */
 #define SERDESID_SERDESID1_MULTIPLICITY_MASK                       0xf000
 #define SERDESID_SERDESID1_MULTIPLICITY_ALIGN                      0
 #define SERDESID_SERDESID1_MULTIPLICITY_BITS                       4
 #define SERDESID_SERDESID1_MULTIPLICITY_SHIFT                      12
 
 /* SerdesID :: serdesID1 :: CL37 [11:11] */
 #define SERDESID_SERDESID1_CL37_MASK                               0x0800
 #define SERDESID_SERDESID1_CL37_ALIGN                              0
 #define SERDESID_SERDESID1_CL37_BITS                               1
 #define SERDESID_SERDESID1_CL37_SHIFT                              11
 
 /* SerdesID :: serdesID1 :: CL73 [10:10] */
 #define SERDESID_SERDESID1_CL73_MASK                               0x0400
 #define SERDESID_SERDESID1_CL73_ALIGN                              0
 #define SERDESID_SERDESID1_CL73_BITS                               1
 #define SERDESID_SERDESID1_CL73_SHIFT                              10
 
 /* SerdesID :: serdesID1 :: CL36 [09:09] */
 #define SERDESID_SERDESID1_CL36_MASK                               0x0200
 #define SERDESID_SERDESID1_CL36_ALIGN                              0
 #define SERDESID_SERDESID1_CL36_BITS                               1
 #define SERDESID_SERDESID1_CL36_SHIFT                              9
 
 /* SerdesID :: serdesID1 :: CL48 [08:08] */
 #define SERDESID_SERDESID1_CL48_MASK                               0x0100
 #define SERDESID_SERDESID1_CL48_ALIGN                              0
 #define SERDESID_SERDESID1_CL48_BITS                               1
 #define SERDESID_SERDESID1_CL48_SHIFT                              8
 
 /* SerdesID :: serdesID1 :: HiGig [07:07] */
 #define SERDESID_SERDESID1_HIGIG_MASK                              0x0080
 #define SERDESID_SERDESID1_HIGIG_ALIGN                             0
 #define SERDESID_SERDESID1_HIGIG_BITS                              1
 #define SERDESID_SERDESID1_HIGIG_SHIFT                             7
 
 /* SerdesID :: serdesID1 :: HiGigII [06:06] */
 #define SERDESID_SERDESID1_HIGIGII_MASK                            0x0040
 #define SERDESID_SERDESID1_HIGIGII_ALIGN                           0
 #define SERDESID_SERDESID1_HIGIGII_BITS                            1
 #define SERDESID_SERDESID1_HIGIGII_SHIFT                           6
 
 /* SerdesID :: serdesID1 :: PCIE [05:05] */
 #define SERDESID_SERDESID1_PCIE_MASK                               0x0020
 #define SERDESID_SERDESID1_PCIE_ALIGN                              0
 #define SERDESID_SERDESID1_PCIE_BITS                               1
 #define SERDESID_SERDESID1_PCIE_SHIFT                              5
 
 /* SerdesID :: serdesID1 :: PCIE_II [04:04] */
 #define SERDESID_SERDESID1_PCIE_II_MASK                            0x0010
 #define SERDESID_SERDESID1_PCIE_II_ALIGN                           0
 #define SERDESID_SERDESID1_PCIE_II_BITS                            1
 #define SERDESID_SERDESID1_PCIE_II_SHIFT                           4
 
 /* SerdesID :: serdesID1 :: brcm_64B66B [03:03] */
 #define SERDESID_SERDESID1_BRCM_64B66B_MASK                        0x0008
 #define SERDESID_SERDESID1_BRCM_64B66B_ALIGN                       0
 #define SERDESID_SERDESID1_BRCM_64B66B_BITS                        1
 #define SERDESID_SERDESID1_BRCM_64B66B_SHIFT                       3
 
 /* SerdesID :: serdesID1 :: Scrambler [02:02] */
 #define SERDESID_SERDESID1_SCRAMBLER_MASK                          0x0004
 #define SERDESID_SERDESID1_SCRAMBLER_ALIGN                         0
 #define SERDESID_SERDESID1_SCRAMBLER_BITS                          1
 #define SERDESID_SERDESID1_SCRAMBLER_SHIFT                         2
 
 /* SerdesID :: serdesID1 :: reserved0 [01:00] */
 #define SERDESID_SERDESID1_RESERVED0_MASK                          0x0003
 #define SERDESID_SERDESID1_RESERVED0_ALIGN                         0
 #define SERDESID_SERDESID1_RESERVED0_BITS                          2
 #define SERDESID_SERDESID1_RESERVED0_SHIFT                         0
 
 
 /****************************************************************************
  * SerdesID :: serdesID2
  */
 /* SerdesID :: serdesID2 :: ID3present [15:15] */
 #define SERDESID_SERDESID2_ID3PRESENT_MASK                         0x8000
 #define SERDESID_SERDESID2_ID3PRESENT_ALIGN                        0
 #define SERDESID_SERDESID2_ID3PRESENT_BITS                         1
 #define SERDESID_SERDESID2_ID3PRESENT_SHIFT                        15
 
 /* SerdesID :: serdesID2 :: dr_25G_4L [14:14] */
 #define SERDESID_SERDESID2_DR_25G_4L_MASK                          0x4000
 #define SERDESID_SERDESID2_DR_25G_4L_ALIGN                         0
 #define SERDESID_SERDESID2_DR_25G_4L_BITS                          1
 #define SERDESID_SERDESID2_DR_25G_4L_SHIFT                         14
 
 /* SerdesID :: serdesID2 :: dr_21G_4L [13:13] */
 #define SERDESID_SERDESID2_DR_21G_4L_MASK                          0x2000
 #define SERDESID_SERDESID2_DR_21G_4L_ALIGN                         0
 #define SERDESID_SERDESID2_DR_21G_4L_BITS                          1
 #define SERDESID_SERDESID2_DR_21G_4L_SHIFT                         13
 
 /* SerdesID :: serdesID2 :: dr_20G_4L [12:12] */
 #define SERDESID_SERDESID2_DR_20G_4L_MASK                          0x1000
 #define SERDESID_SERDESID2_DR_20G_4L_ALIGN                         0
 #define SERDESID_SERDESID2_DR_20G_4L_BITS                          1
 #define SERDESID_SERDESID2_DR_20G_4L_SHIFT                         12
 
 /* SerdesID :: serdesID2 :: dr_16G_4L [11:11] */
 #define SERDESID_SERDESID2_DR_16G_4L_MASK                          0x0800
 #define SERDESID_SERDESID2_DR_16G_4L_ALIGN                         0
 #define SERDESID_SERDESID2_DR_16G_4L_BITS                          1
 #define SERDESID_SERDESID2_DR_16G_4L_SHIFT                         11
 
 /* SerdesID :: serdesID2 :: dr_15G_4L [10:10] */
 #define SERDESID_SERDESID2_DR_15G_4L_MASK                          0x0400
 #define SERDESID_SERDESID2_DR_15G_4L_ALIGN                         0
 #define SERDESID_SERDESID2_DR_15G_4L_BITS                          1
 #define SERDESID_SERDESID2_DR_15G_4L_SHIFT                         10
 
 /* SerdesID :: serdesID2 :: dr_13G_4L [09:09] */
 #define SERDESID_SERDESID2_DR_13G_4L_MASK                          0x0200
 #define SERDESID_SERDESID2_DR_13G_4L_ALIGN                         0
 #define SERDESID_SERDESID2_DR_13G_4L_BITS                          1
 #define SERDESID_SERDESID2_DR_13G_4L_SHIFT                         9
 
 /* SerdesID :: serdesID2 :: dr_12_5G_4L [08:08] */
 #define SERDESID_SERDESID2_DR_12_5G_4L_MASK                        0x0100
 #define SERDESID_SERDESID2_DR_12_5G_4L_ALIGN                       0
 #define SERDESID_SERDESID2_DR_12_5G_4L_BITS                        1
 #define SERDESID_SERDESID2_DR_12_5G_4L_SHIFT                       8
 
 /* SerdesID :: serdesID2 :: dr_12G_4L [07:07] */
 #define SERDESID_SERDESID2_DR_12G_4L_MASK                          0x0080
 #define SERDESID_SERDESID2_DR_12G_4L_ALIGN                         0
 #define SERDESID_SERDESID2_DR_12G_4L_BITS                          1
 #define SERDESID_SERDESID2_DR_12G_4L_SHIFT                         7
 
 /* SerdesID :: serdesID2 :: dr_10G_4L [06:06] */
 #define SERDESID_SERDESID2_DR_10G_4L_MASK                          0x0040
 #define SERDESID_SERDESID2_DR_10G_4L_ALIGN                         0
 #define SERDESID_SERDESID2_DR_10G_4L_BITS                          1
 #define SERDESID_SERDESID2_DR_10G_4L_SHIFT                         6
 
 /* SerdesID :: serdesID2 :: dr_6G_4L [05:05] */
 #define SERDESID_SERDESID2_DR_6G_4L_MASK                           0x0020
 #define SERDESID_SERDESID2_DR_6G_4L_ALIGN                          0
 #define SERDESID_SERDESID2_DR_6G_4L_BITS                           1
 #define SERDESID_SERDESID2_DR_6G_4L_SHIFT                          5
 
 /* SerdesID :: serdesID2 :: dr_5G_4L [04:04] */
 #define SERDESID_SERDESID2_DR_5G_4L_MASK                           0x0010
 #define SERDESID_SERDESID2_DR_5G_4L_ALIGN                          0
 #define SERDESID_SERDESID2_DR_5G_4L_BITS                           1
 #define SERDESID_SERDESID2_DR_5G_4L_SHIFT                          4
 
 /* SerdesID :: serdesID2 :: dr_2p5G_SL [03:03] */
 #define SERDESID_SERDESID2_DR_2P5G_SL_MASK                         0x0008
 #define SERDESID_SERDESID2_DR_2P5G_SL_ALIGN                        0
 #define SERDESID_SERDESID2_DR_2P5G_SL_BITS                         1
 #define SERDESID_SERDESID2_DR_2P5G_SL_SHIFT                        3
 
 /* SerdesID :: serdesID2 :: dr_1G_SL [02:02] */
 #define SERDESID_SERDESID2_DR_1G_SL_MASK                           0x0004
 #define SERDESID_SERDESID2_DR_1G_SL_ALIGN                          0
 #define SERDESID_SERDESID2_DR_1G_SL_BITS                           1
 #define SERDESID_SERDESID2_DR_1G_SL_SHIFT                          2
 
 /* SerdesID :: serdesID2 :: dr_100M_SL [01:01] */
 #define SERDESID_SERDESID2_DR_100M_SL_MASK                         0x0002
 #define SERDESID_SERDESID2_DR_100M_SL_ALIGN                        0
 #define SERDESID_SERDESID2_DR_100M_SL_BITS                         1
 #define SERDESID_SERDESID2_DR_100M_SL_SHIFT                        1
 
 /* SerdesID :: serdesID2 :: dr_10M_SL [00:00] */
 #define SERDESID_SERDESID2_DR_10M_SL_MASK                          0x0001
 #define SERDESID_SERDESID2_DR_10M_SL_ALIGN                         0
 #define SERDESID_SERDESID2_DR_10M_SL_BITS                          1
 #define SERDESID_SERDESID2_DR_10M_SL_SHIFT                         0
 
 
 /****************************************************************************
  * SerdesID :: serdesID3
  */
 /* SerdesID :: serdesID3 :: ID4present [15:15] */
 #define SERDESID_SERDESID3_ID4PRESENT_MASK                         0x8000
 #define SERDESID_SERDESID3_ID4PRESENT_ALIGN                        0
 #define SERDESID_SERDESID3_ID4PRESENT_BITS                         1
 #define SERDESID_SERDESID3_ID4PRESENT_SHIFT                        15
 
 /* SerdesID :: serdesID3 :: reserved0 [14:10] */
 #define SERDESID_SERDESID3_RESERVED0_MASK                          0x7c00
 #define SERDESID_SERDESID3_RESERVED0_ALIGN                         0
 #define SERDESID_SERDESID3_RESERVED0_BITS                          5
 #define SERDESID_SERDESID3_RESERVED0_SHIFT                         10
 
 /* SerdesID :: serdesID3 :: dr_40000_4L [09:09] */
 #define SERDESID_SERDESID3_DR_40000_4L_MASK                        0x0200
 #define SERDESID_SERDESID3_DR_40000_4L_ALIGN                       0
 #define SERDESID_SERDESID3_DR_40000_4L_BITS                        1
 #define SERDESID_SERDESID3_DR_40000_4L_SHIFT                       9
 
 /* SerdesID :: serdesID3 :: dr_32700_4L [08:08] */
 #define SERDESID_SERDESID3_DR_32700_4L_MASK                        0x0100
 #define SERDESID_SERDESID3_DR_32700_4L_ALIGN                       0
 #define SERDESID_SERDESID3_DR_32700_4L_BITS                        1
 #define SERDESID_SERDESID3_DR_32700_4L_SHIFT                       8
 
 /* SerdesID :: serdesID3 :: dr_31500_4L [07:07] */
 #define SERDESID_SERDESID3_DR_31500_4L_MASK                        0x0080
 #define SERDESID_SERDESID3_DR_31500_4L_ALIGN                       0
 #define SERDESID_SERDESID3_DR_31500_4L_BITS                        1
 #define SERDESID_SERDESID3_DR_31500_4L_SHIFT                       7
 
 /* SerdesID :: serdesID3 :: dr_2400_SL [06:06] */
 #define SERDESID_SERDESID3_DR_2400_SL_MASK                         0x0040
 #define SERDESID_SERDESID3_DR_2400_SL_ALIGN                        0
 #define SERDESID_SERDESID3_DR_2400_SL_BITS                         1
 #define SERDESID_SERDESID3_DR_2400_SL_SHIFT                        6
 
 /* SerdesID :: serdesID3 :: dr_1200_SL [05:05] */
 #define SERDESID_SERDESID3_DR_1200_SL_MASK                         0x0020
 #define SERDESID_SERDESID3_DR_1200_SL_ALIGN                        0
 #define SERDESID_SERDESID3_DR_1200_SL_BITS                         1
 #define SERDESID_SERDESID3_DR_1200_SL_SHIFT                        5
 
 /* SerdesID :: serdesID3 :: dr_6400_SL [04:04] */
 #define SERDESID_SERDESID3_DR_6400_SL_MASK                         0x0010
 #define SERDESID_SERDESID3_DR_6400_SL_ALIGN                        0
 #define SERDESID_SERDESID3_DR_6400_SL_BITS                         1
 #define SERDESID_SERDESID3_DR_6400_SL_SHIFT                        4
 
 /* SerdesID :: serdesID3 :: dr_5000_SL [03:03] */
 #define SERDESID_SERDESID3_DR_5000_SL_MASK                         0x0008
 #define SERDESID_SERDESID3_DR_5000_SL_ALIGN                        0
 #define SERDESID_SERDESID3_DR_5000_SL_BITS                         1
 #define SERDESID_SERDESID3_DR_5000_SL_SHIFT                        3
 
 /* SerdesID :: serdesID3 :: dr_4000_SL [02:02] */
 #define SERDESID_SERDESID3_DR_4000_SL_MASK                         0x0004
 #define SERDESID_SERDESID3_DR_4000_SL_ALIGN                        0
 #define SERDESID_SERDESID3_DR_4000_SL_BITS                         1
 #define SERDESID_SERDESID3_DR_4000_SL_SHIFT                        2
 
 /* SerdesID :: serdesID3 :: dr_2000_SL [01:01] */
 #define SERDESID_SERDESID3_DR_2000_SL_MASK                         0x0002
 #define SERDESID_SERDESID3_DR_2000_SL_ALIGN                        0
 #define SERDESID_SERDESID3_DR_2000_SL_BITS                         1
 #define SERDESID_SERDESID3_DR_2000_SL_SHIFT                        1
 
 /* SerdesID :: serdesID3 :: dr_100FX [00:00] */
 #define SERDESID_SERDESID3_DR_100FX_MASK                           0x0001
 #define SERDESID_SERDESID3_DR_100FX_ALIGN                          0
 #define SERDESID_SERDESID3_DR_100FX_BITS                           1
 #define SERDESID_SERDESID3_DR_100FX_SHIFT                          0
 
 
 /****************************************************************************
  * SerdesID :: serdesID4
  */
 /* SerdesID :: serdesID4 :: ID5present [15:15] */
 #define SERDESID_SERDESID4_ID5PRESENT_MASK                         0x8000
 #define SERDESID_SERDESID4_ID5PRESENT_ALIGN                        0
 #define SERDESID_SERDESID4_ID5PRESENT_BITS                         1
 #define SERDESID_SERDESID4_ID5PRESENT_SHIFT                        15
 
 /* SerdesID :: serdesID4 :: process [14:13] */
 #define SERDESID_SERDESID4_PROCESS_MASK                            0x6000
 #define SERDESID_SERDESID4_PROCESS_ALIGN                           0
 #define SERDESID_SERDESID4_PROCESS_BITS                            2
 #define SERDESID_SERDESID4_PROCESS_SHIFT                           13
 
 /* SerdesID :: serdesID4 :: CL82 [12:12] */
 #define SERDESID_SERDESID4_CL82_MASK                               0x1000
 #define SERDESID_SERDESID4_CL82_ALIGN                              0
 #define SERDESID_SERDESID4_CL82_BITS                               1
 #define SERDESID_SERDESID4_CL82_SHIFT                              12
 
 /* SerdesID :: serdesID4 :: CL78 [11:11] */
 #define SERDESID_SERDESID4_CL78_MASK                               0x0800
 #define SERDESID_SERDESID4_CL78_ALIGN                              0
 #define SERDESID_SERDESID4_CL78_BITS                               1
 #define SERDESID_SERDESID4_CL78_SHIFT                              11
 
 /* SerdesID :: serdesID4 :: CL74 [10:10] */
 #define SERDESID_SERDESID4_CL74_MASK                               0x0400
 #define SERDESID_SERDESID4_CL74_ALIGN                              0
 #define SERDESID_SERDESID4_CL74_BITS                               1
 #define SERDESID_SERDESID4_CL74_SHIFT                              10
 
 /* SerdesID :: serdesID4 :: CL72 [09:09] */
 #define SERDESID_SERDESID4_CL72_MASK                               0x0200
 #define SERDESID_SERDESID4_CL72_ALIGN                              0
 #define SERDESID_SERDESID4_CL72_BITS                               1
 #define SERDESID_SERDESID4_CL72_SHIFT                              9
 
 /* SerdesID :: serdesID4 :: CL49 [08:08] */
 #define SERDESID_SERDESID4_CL49_MASK                               0x0100
 #define SERDESID_SERDESID4_CL49_ALIGN                              0
 #define SERDESID_SERDESID4_CL49_BITS                               1
 #define SERDESID_SERDESID4_CL49_SHIFT                              8
 
 /* SerdesID :: serdesID4 :: DXGXS [07:07] */
 #define SERDESID_SERDESID4_DXGXS_MASK                              0x0080
 #define SERDESID_SERDESID4_DXGXS_ALIGN                             0
 #define SERDESID_SERDESID4_DXGXS_BITS                              1
 #define SERDESID_SERDESID4_DXGXS_SHIFT                             7
 
 /* SerdesID :: serdesID4 :: X2 [06:06] */
 #define SERDESID_SERDESID4_X2_MASK                                 0x0040
 #define SERDESID_SERDESID4_X2_ALIGN                                0
 #define SERDESID_SERDESID4_X2_BITS                                 1
 #define SERDESID_SERDESID4_X2_SHIFT                                6
 
 /* SerdesID :: serdesID4 :: R2 [05:05] */
 #define SERDESID_SERDESID4_R2_MASK                                 0x0020
 #define SERDESID_SERDESID4_R2_ALIGN                                0
 #define SERDESID_SERDESID4_R2_BITS                                 1
 #define SERDESID_SERDESID4_R2_SHIFT                                5
 
 /* SerdesID :: serdesID4 :: UC [04:04] */
 #define SERDESID_SERDESID4_UC_MASK                                 0x0010
 #define SERDESID_SERDESID4_UC_ALIGN                                0
 #define SERDESID_SERDESID4_UC_BITS                                 1
 #define SERDESID_SERDESID4_UC_SHIFT                                4
 
 /* SerdesID :: serdesID4 :: reserved0 [03:00] */
 #define SERDESID_SERDESID4_RESERVED0_MASK                          0x000f
 #define SERDESID_SERDESID4_RESERVED0_ALIGN                         0
 #define SERDESID_SERDESID4_RESERVED0_BITS                          4
 #define SERDESID_SERDESID4_RESERVED0_SHIFT                         0
 
 
 /****************************************************************************
  * Warpcore_USER_Digital3
  */
 /****************************************************************************
  * Digital3 :: digctl_3_0
  */
 /* Digital3 :: digctl_3_0 :: an_lostLink_cnt [15:00] */
 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_MASK                   0xffff
 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_ALIGN                  0
 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_BITS                   16
 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_SHIFT                  0
 
 
 /****************************************************************************
  * Digital3 :: digctl_3_1
  */
 /* Digital3 :: digctl_3_1 :: an_switch_cnt [15:00] */
 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_MASK                     0xffff
 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_ALIGN                    0
 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_BITS                     16
 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_SHIFT                    0
 
 
 /****************************************************************************
  * Digital3 :: digctl_3_2
  */
 /* Digital3 :: digctl_3_2 :: an_link_cnt [15:00] */
 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_MASK                       0xffff
 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_ALIGN                      0
 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_BITS                       16
 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_SHIFT                      0
 
 
 /****************************************************************************
  * Digital3 :: digctl_3_3
  */
 /* Digital3 :: digctl_3_3 :: an_switch_cnt2 [15:08] */
 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_MASK                    0xff00
 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_ALIGN                   0
 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_BITS                    8
 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_SHIFT                   8
 
 /* Digital3 :: digctl_3_3 :: an_link_cnt2 [07:00] */
 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_MASK                      0x00ff
 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_ALIGN                     0
 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_BITS                      8
 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_SHIFT                     0
 
 
 /****************************************************************************
  * Digital3 :: digctl_3_4
  */
 /* Digital3 :: digctl_3_4 :: mp_number [15:05] */
 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_MASK                         0xffe0
 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_ALIGN                        0
 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_BITS                         11
 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_SHIFT                        5
 
 /* Digital3 :: digctl_3_4 :: no_fail_cnt [04:04] */
 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_MASK                       0x0010
 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_ALIGN                      0
 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_BITS                       1
 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_SHIFT                      4
 
 /* Digital3 :: digctl_3_4 :: an_fail_cnt [03:00] */
 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_MASK                       0x000f
 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_ALIGN                      0
 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_BITS                       4
 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_SHIFT                      0
 
 
 /****************************************************************************
  * Digital3 :: digctl_3_5
  */
 /* Digital3 :: digctl_3_5 :: an_ignoreLink_cnt [15:00] */
 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_MASK                 0xffff
 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_ALIGN                0
 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_BITS                 16
 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_SHIFT                0
 
 
 /****************************************************************************
  * Digital3 :: digctl_3_6
  */
 /* Digital3 :: digctl_3_6 :: an_lostLink_cnt2 [15:08] */
 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_MASK                  0xff00
 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_ALIGN                 0
 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_BITS                  8
 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_SHIFT                 8
 
 /* Digital3 :: digctl_3_6 :: an_ingoreLink_cnt2 [07:00] */
 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_MASK                0x00ff
 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_ALIGN               0
 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_BITS                8
 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_SHIFT               0
 
 
 /****************************************************************************
  * Digital3 :: TPOUT_1
  */
 /* Digital3 :: TPOUT_1 :: tpout1 [15:00] */
 #define DIGITAL3_TPOUT_1_TPOUT1_MASK                               0xffff
 #define DIGITAL3_TPOUT_1_TPOUT1_ALIGN                              0
 #define DIGITAL3_TPOUT_1_TPOUT1_BITS                               16
 #define DIGITAL3_TPOUT_1_TPOUT1_SHIFT                              0
 
 
 /****************************************************************************
  * Digital3 :: TPOUT_2
  */
 /* Digital3 :: TPOUT_2 :: tpout2 [15:00] */
 #define DIGITAL3_TPOUT_2_TPOUT2_MASK                               0xffff
 #define DIGITAL3_TPOUT_2_TPOUT2_ALIGN                              0
 #define DIGITAL3_TPOUT_2_TPOUT2_BITS                               16
 #define DIGITAL3_TPOUT_2_TPOUT2_SHIFT                              0
 
 
 /****************************************************************************
  * Digital3 :: UP1
  */
 /* Digital3 :: UP1 :: reserved0 [15:11] */
 #define DIGITAL3_UP1_RESERVED0_MASK                                0xf800
 #define DIGITAL3_UP1_RESERVED0_ALIGN                               0
 #define DIGITAL3_UP1_RESERVED0_BITS                                5
 #define DIGITAL3_UP1_RESERVED0_SHIFT                               11
 
 /* Digital3 :: UP1 :: dataRate_20GX4 [10:10] */
 #define DIGITAL3_UP1_DATARATE_20GX4_MASK                           0x0400
 #define DIGITAL3_UP1_DATARATE_20GX4_ALIGN                          0
 #define DIGITAL3_UP1_DATARATE_20GX4_BITS                           1
 #define DIGITAL3_UP1_DATARATE_20GX4_SHIFT                          10
 
 /* Digital3 :: UP1 :: dataRate_16GX4 [09:09] */
 #define DIGITAL3_UP1_DATARATE_16GX4_MASK                           0x0200
 #define DIGITAL3_UP1_DATARATE_16GX4_ALIGN                          0
 #define DIGITAL3_UP1_DATARATE_16GX4_BITS                           1
 #define DIGITAL3_UP1_DATARATE_16GX4_SHIFT                          9
 
 /* Digital3 :: UP1 :: dataRate_15GX4 [08:08] */
 #define DIGITAL3_UP1_DATARATE_15GX4_MASK                           0x0100
 #define DIGITAL3_UP1_DATARATE_15GX4_ALIGN                          0
 #define DIGITAL3_UP1_DATARATE_15GX4_BITS                           1
 #define DIGITAL3_UP1_DATARATE_15GX4_SHIFT                          8
 
 /* Digital3 :: UP1 :: dataRate_13GX4 [07:07] */
 #define DIGITAL3_UP1_DATARATE_13GX4_MASK                           0x0080
 #define DIGITAL3_UP1_DATARATE_13GX4_ALIGN                          0
 #define DIGITAL3_UP1_DATARATE_13GX4_BITS                           1
 #define DIGITAL3_UP1_DATARATE_13GX4_SHIFT                          7
 
 /* Digital3 :: UP1 :: dataRate_12p5GX4 [06:06] */
 #define DIGITAL3_UP1_DATARATE_12P5GX4_MASK                         0x0040
 #define DIGITAL3_UP1_DATARATE_12P5GX4_ALIGN                        0
 #define DIGITAL3_UP1_DATARATE_12P5GX4_BITS                         1
 #define DIGITAL3_UP1_DATARATE_12P5GX4_SHIFT                        6
 
 /* Digital3 :: UP1 :: dataRate_12GX4 [05:05] */
 #define DIGITAL3_UP1_DATARATE_12GX4_MASK                           0x0020
 #define DIGITAL3_UP1_DATARATE_12GX4_ALIGN                          0
 #define DIGITAL3_UP1_DATARATE_12GX4_BITS                           1
 #define DIGITAL3_UP1_DATARATE_12GX4_SHIFT                          5
 
 /* Digital3 :: UP1 :: dataRate_10GCX4 [04:04] */
 #define DIGITAL3_UP1_DATARATE_10GCX4_MASK                          0x0010
 #define DIGITAL3_UP1_DATARATE_10GCX4_ALIGN                         0
 #define DIGITAL3_UP1_DATARATE_10GCX4_BITS                          1
 #define DIGITAL3_UP1_DATARATE_10GCX4_SHIFT                         4
 
 /* Digital3 :: UP1 :: dataRate_10GX4 [03:03] */
 #define DIGITAL3_UP1_DATARATE_10GX4_MASK                           0x0008
 #define DIGITAL3_UP1_DATARATE_10GX4_ALIGN                          0
 #define DIGITAL3_UP1_DATARATE_10GX4_BITS                           1
 #define DIGITAL3_UP1_DATARATE_10GX4_SHIFT                          3
 
 /* Digital3 :: UP1 :: dataRate_6GX4 [02:02] */
 #define DIGITAL3_UP1_DATARATE_6GX4_MASK                            0x0004
 #define DIGITAL3_UP1_DATARATE_6GX4_ALIGN                           0
 #define DIGITAL3_UP1_DATARATE_6GX4_BITS                            1
 #define DIGITAL3_UP1_DATARATE_6GX4_SHIFT                           2
 
 /* Digital3 :: UP1 :: dataRate_5GX4 [01:01] */
 #define DIGITAL3_UP1_DATARATE_5GX4_MASK                            0x0002
 #define DIGITAL3_UP1_DATARATE_5GX4_ALIGN                           0
 #define DIGITAL3_UP1_DATARATE_5GX4_BITS                            1
 #define DIGITAL3_UP1_DATARATE_5GX4_SHIFT                           1
 
 /* Digital3 :: UP1 :: dataRate_2p5GX1 [00:00] */
 #define DIGITAL3_UP1_DATARATE_2P5GX1_MASK                          0x0001
 #define DIGITAL3_UP1_DATARATE_2P5GX1_ALIGN                         0
 #define DIGITAL3_UP1_DATARATE_2P5GX1_BITS                          1
 #define DIGITAL3_UP1_DATARATE_2P5GX1_SHIFT                         0
 
 
 /****************************************************************************
  * Digital3 :: UP2
  */
 /* Digital3 :: UP2 :: reserved0 [15:11] */
 #define DIGITAL3_UP2_RESERVED0_MASK                                0xf800
 #define DIGITAL3_UP2_RESERVED0_ALIGN                               0
 #define DIGITAL3_UP2_RESERVED0_BITS                                5
 #define DIGITAL3_UP2_RESERVED0_SHIFT                               11
 
 /* Digital3 :: UP2 :: valid [10:10] */
 #define DIGITAL3_UP2_VALID_MASK                                    0x0400
 #define DIGITAL3_UP2_VALID_ALIGN                                   0
 #define DIGITAL3_UP2_VALID_BITS                                    1
 #define DIGITAL3_UP2_VALID_SHIFT                                   10
 
 /* Digital3 :: UP2 :: preemphasis [09:06] */
 #define DIGITAL3_UP2_PREEMPHASIS_MASK                              0x03c0
 #define DIGITAL3_UP2_PREEMPHASIS_ALIGN                             0
 #define DIGITAL3_UP2_PREEMPHASIS_BITS                              4
 #define DIGITAL3_UP2_PREEMPHASIS_SHIFT                             6
 
 /* Digital3 :: UP2 :: idriver [05:03] */
 #define DIGITAL3_UP2_IDRIVER_MASK                                  0x0038
 #define DIGITAL3_UP2_IDRIVER_ALIGN                                 0
 #define DIGITAL3_UP2_IDRIVER_BITS                                  3
 #define DIGITAL3_UP2_IDRIVER_SHIFT                                 3
 
 /* Digital3 :: UP2 :: ipredriver [02:00] */
 #define DIGITAL3_UP2_IPREDRIVER_MASK                               0x0007
 #define DIGITAL3_UP2_IPREDRIVER_ALIGN                              0
 #define DIGITAL3_UP2_IPREDRIVER_BITS                               3
 #define DIGITAL3_UP2_IPREDRIVER_SHIFT                              0
 
 
 /****************************************************************************
  * Digital3 :: UP3
  */
 /* Digital3 :: UP3 :: reserved0 [15:11] */
 #define DIGITAL3_UP3_RESERVED0_MASK                                0xf800
 #define DIGITAL3_UP3_RESERVED0_ALIGN                               0
 #define DIGITAL3_UP3_RESERVED0_BITS                                5
 #define DIGITAL3_UP3_RESERVED0_SHIFT                               11
 
 /* Digital3 :: UP3 :: last [10:10] */
 #define DIGITAL3_UP3_LAST_MASK                                     0x0400
 #define DIGITAL3_UP3_LAST_ALIGN                                    0
 #define DIGITAL3_UP3_LAST_BITS                                     1
 #define DIGITAL3_UP3_LAST_SHIFT                                    10
 
 /* Digital3 :: UP3 :: dataRate_21GX4 [09:09] */
 #define DIGITAL3_UP3_DATARATE_21GX4_MASK                           0x0200
 #define DIGITAL3_UP3_DATARATE_21GX4_ALIGN                          0
 #define DIGITAL3_UP3_DATARATE_21GX4_BITS                           1
 #define DIGITAL3_UP3_DATARATE_21GX4_SHIFT                          9
 
 /* Digital3 :: UP3 :: dataRate_25p45GX4 [08:08] */
 #define DIGITAL3_UP3_DATARATE_25P45GX4_MASK                        0x0100
 #define DIGITAL3_UP3_DATARATE_25P45GX4_ALIGN                       0
 #define DIGITAL3_UP3_DATARATE_25P45GX4_BITS                        1
 #define DIGITAL3_UP3_DATARATE_25P45GX4_SHIFT                       8
 
 /* Digital3 :: UP3 :: dataRate_31p5G [07:07] */
 #define DIGITAL3_UP3_DATARATE_31P5G_MASK                           0x0080
 #define DIGITAL3_UP3_DATARATE_31P5G_ALIGN                          0
 #define DIGITAL3_UP3_DATARATE_31P5G_BITS                           1
 #define DIGITAL3_UP3_DATARATE_31P5G_SHIFT                          7
 
 /* Digital3 :: UP3 :: reserved1 [06:06] */
 #define DIGITAL3_UP3_RESERVED1_MASK                                0x0040
 #define DIGITAL3_UP3_RESERVED1_ALIGN                               0
 #define DIGITAL3_UP3_RESERVED1_BITS                                1
 #define DIGITAL3_UP3_RESERVED1_SHIFT                               6
 
 /* Digital3 :: UP3 :: dataRate_40G [05:05] */
 #define DIGITAL3_UP3_DATARATE_40G_MASK                             0x0020
 #define DIGITAL3_UP3_DATARATE_40G_ALIGN                            0
 #define DIGITAL3_UP3_DATARATE_40G_BITS                             1
 #define DIGITAL3_UP3_DATARATE_40G_SHIFT                            5
 
 /* Digital3 :: UP3 :: reserved2 [04:03] */
 #define DIGITAL3_UP3_RESERVED2_MASK                                0x0018
 #define DIGITAL3_UP3_RESERVED2_ALIGN                               0
 #define DIGITAL3_UP3_RESERVED2_BITS                                2
 #define DIGITAL3_UP3_RESERVED2_SHIFT                               3
 
 /* Digital3 :: UP3 :: Cl72 [02:02] */
 #define DIGITAL3_UP3_CL72_MASK                                     0x0004
 #define DIGITAL3_UP3_CL72_ALIGN                                    0
 #define DIGITAL3_UP3_CL72_BITS                                     1
 #define DIGITAL3_UP3_CL72_SHIFT                                    2
 
 /* Digital3 :: UP3 :: FEC [01:01] */
 #define DIGITAL3_UP3_FEC_MASK                                      0x0002
 #define DIGITAL3_UP3_FEC_ALIGN                                     0
 #define DIGITAL3_UP3_FEC_BITS                                      1
 #define DIGITAL3_UP3_FEC_SHIFT                                     1
 
 /* Digital3 :: UP3 :: HiGig2 [00:00] */
 #define DIGITAL3_UP3_HIGIG2_MASK                                   0x0001
 #define DIGITAL3_UP3_HIGIG2_ALIGN                                  0
 #define DIGITAL3_UP3_HIGIG2_BITS                                   1
 #define DIGITAL3_UP3_HIGIG2_SHIFT                                  0
 
 
 /****************************************************************************
  * Digital3 :: LP_UP1
  */
 /* Digital3 :: LP_UP1 :: reserved0 [15:11] */
 #define DIGITAL3_LP_UP1_RESERVED0_MASK                             0xf800
 #define DIGITAL3_LP_UP1_RESERVED0_ALIGN                            0
 #define DIGITAL3_LP_UP1_RESERVED0_BITS                             5
 #define DIGITAL3_LP_UP1_RESERVED0_SHIFT                            11
 
 /* Digital3 :: LP_UP1 :: dataRate_20GX4 [10:10] */
 #define DIGITAL3_LP_UP1_DATARATE_20GX4_MASK                        0x0400
 #define DIGITAL3_LP_UP1_DATARATE_20GX4_ALIGN                       0
 #define DIGITAL3_LP_UP1_DATARATE_20GX4_BITS                        1
 #define DIGITAL3_LP_UP1_DATARATE_20GX4_SHIFT                       10
 
 /* Digital3 :: LP_UP1 :: dataRate_16GX4 [09:09] */
 #define DIGITAL3_LP_UP1_DATARATE_16GX4_MASK                        0x0200
 #define DIGITAL3_LP_UP1_DATARATE_16GX4_ALIGN                       0
 #define DIGITAL3_LP_UP1_DATARATE_16GX4_BITS                        1
 #define DIGITAL3_LP_UP1_DATARATE_16GX4_SHIFT                       9
 
 /* Digital3 :: LP_UP1 :: dataRate_15GX4 [08:08] */
 #define DIGITAL3_LP_UP1_DATARATE_15GX4_MASK                        0x0100
 #define DIGITAL3_LP_UP1_DATARATE_15GX4_ALIGN                       0
 #define DIGITAL3_LP_UP1_DATARATE_15GX4_BITS                        1
 #define DIGITAL3_LP_UP1_DATARATE_15GX4_SHIFT                       8
 
 /* Digital3 :: LP_UP1 :: dataRate_13GX4 [07:07] */
 #define DIGITAL3_LP_UP1_DATARATE_13GX4_MASK                        0x0080
 #define DIGITAL3_LP_UP1_DATARATE_13GX4_ALIGN                       0
 #define DIGITAL3_LP_UP1_DATARATE_13GX4_BITS                        1
 #define DIGITAL3_LP_UP1_DATARATE_13GX4_SHIFT                       7
 
 /* Digital3 :: LP_UP1 :: dataRate_12p5GX4 [06:06] */
 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_MASK                      0x0040
 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_ALIGN                     0
 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_BITS                      1
 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_SHIFT                     6
 
 /* Digital3 :: LP_UP1 :: dataRate_12GX4 [05:05] */
 #define DIGITAL3_LP_UP1_DATARATE_12GX4_MASK                        0x0020
 #define DIGITAL3_LP_UP1_DATARATE_12GX4_ALIGN                       0
 #define DIGITAL3_LP_UP1_DATARATE_12GX4_BITS                        1
 #define DIGITAL3_LP_UP1_DATARATE_12GX4_SHIFT                       5
 
 /* Digital3 :: LP_UP1 :: dataRate_10GCX4 [04:04] */
 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_MASK                       0x0010
 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_ALIGN                      0
 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_BITS                       1
 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_SHIFT                      4
 
 /* Digital3 :: LP_UP1 :: dataRate_10GX4 [03:03] */
 #define DIGITAL3_LP_UP1_DATARATE_10GX4_MASK                        0x0008
 #define DIGITAL3_LP_UP1_DATARATE_10GX4_ALIGN                       0
 #define DIGITAL3_LP_UP1_DATARATE_10GX4_BITS                        1
 #define DIGITAL3_LP_UP1_DATARATE_10GX4_SHIFT                       3
 
 /* Digital3 :: LP_UP1 :: dataRate_6GX4 [02:02] */
 #define DIGITAL3_LP_UP1_DATARATE_6GX4_MASK                         0x0004
 #define DIGITAL3_LP_UP1_DATARATE_6GX4_ALIGN                        0
 #define DIGITAL3_LP_UP1_DATARATE_6GX4_BITS                         1
 #define DIGITAL3_LP_UP1_DATARATE_6GX4_SHIFT                        2
 
 /* Digital3 :: LP_UP1 :: dataRate_5GX4 [01:01] */
 #define DIGITAL3_LP_UP1_DATARATE_5GX4_MASK                         0x0002
 #define DIGITAL3_LP_UP1_DATARATE_5GX4_ALIGN                        0
 #define DIGITAL3_LP_UP1_DATARATE_5GX4_BITS                         1
 #define DIGITAL3_LP_UP1_DATARATE_5GX4_SHIFT                        1
 
 /* Digital3 :: LP_UP1 :: dataRate_2p5GX1 [00:00] */
 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_MASK                       0x0001
 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_ALIGN                      0
 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_BITS                       1
 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_SHIFT                      0
 
 
 /****************************************************************************
  * Digital3 :: LP_UP2
  */
 /* Digital3 :: LP_UP2 :: reserved0 [15:11] */
 #define DIGITAL3_LP_UP2_RESERVED0_MASK                             0xf800
 #define DIGITAL3_LP_UP2_RESERVED0_ALIGN                            0
 #define DIGITAL3_LP_UP2_RESERVED0_BITS                             5
 #define DIGITAL3_LP_UP2_RESERVED0_SHIFT                            11
 
 /* Digital3 :: LP_UP2 :: valid [10:10] */
 #define DIGITAL3_LP_UP2_VALID_MASK                                 0x0400
 #define DIGITAL3_LP_UP2_VALID_ALIGN                                0
 #define DIGITAL3_LP_UP2_VALID_BITS                                 1
 #define DIGITAL3_LP_UP2_VALID_SHIFT                                10
 
 /* Digital3 :: LP_UP2 :: preemphasis [09:06] */
 #define DIGITAL3_LP_UP2_PREEMPHASIS_MASK                           0x03c0
 #define DIGITAL3_LP_UP2_PREEMPHASIS_ALIGN                          0
 #define DIGITAL3_LP_UP2_PREEMPHASIS_BITS                           4
 #define DIGITAL3_LP_UP2_PREEMPHASIS_SHIFT                          6
 
 /* Digital3 :: LP_UP2 :: idriver [05:03] */
 #define DIGITAL3_LP_UP2_IDRIVER_MASK                               0x0038
 #define DIGITAL3_LP_UP2_IDRIVER_ALIGN                              0
 #define DIGITAL3_LP_UP2_IDRIVER_BITS                               3
 #define DIGITAL3_LP_UP2_IDRIVER_SHIFT                              3
 
 /* Digital3 :: LP_UP2 :: ipredriver [02:00] */
 #define DIGITAL3_LP_UP2_IPREDRIVER_MASK                            0x0007
 #define DIGITAL3_LP_UP2_IPREDRIVER_ALIGN                           0
 #define DIGITAL3_LP_UP2_IPREDRIVER_BITS                            3
 #define DIGITAL3_LP_UP2_IPREDRIVER_SHIFT                           0
 
 
 /****************************************************************************
  * Digital3 :: LP_UP3
  */
 /* Digital3 :: LP_UP3 :: reserved0 [15:11] */
 #define DIGITAL3_LP_UP3_RESERVED0_MASK                             0xf800
 #define DIGITAL3_LP_UP3_RESERVED0_ALIGN                            0
 #define DIGITAL3_LP_UP3_RESERVED0_BITS                             5
 #define DIGITAL3_LP_UP3_RESERVED0_SHIFT                            11
 
 /* Digital3 :: LP_UP3 :: last [10:10] */
 #define DIGITAL3_LP_UP3_LAST_MASK                                  0x0400
 #define DIGITAL3_LP_UP3_LAST_ALIGN                                 0
 #define DIGITAL3_LP_UP3_LAST_BITS                                  1
 #define DIGITAL3_LP_UP3_LAST_SHIFT                                 10
 
 /* Digital3 :: LP_UP3 :: dataRate_21GX4 [09:09] */
 #define DIGITAL3_LP_UP3_DATARATE_21GX4_MASK                        0x0200
 #define DIGITAL3_LP_UP3_DATARATE_21GX4_ALIGN                       0
 #define DIGITAL3_LP_UP3_DATARATE_21GX4_BITS                        1
 #define DIGITAL3_LP_UP3_DATARATE_21GX4_SHIFT                       9
 
 /* Digital3 :: LP_UP3 :: dataRate_25p45GX4 [08:08] */
 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_MASK                     0x0100
 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_ALIGN                    0
 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_BITS                     1
 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_SHIFT                    8
 
 /* Digital3 :: LP_UP3 :: dataRate_31p5G [07:07] */
 #define DIGITAL3_LP_UP3_DATARATE_31P5G_MASK                        0x0080
 #define DIGITAL3_LP_UP3_DATARATE_31P5G_ALIGN                       0
 #define DIGITAL3_LP_UP3_DATARATE_31P5G_BITS                        1
 #define DIGITAL3_LP_UP3_DATARATE_31P5G_SHIFT                       7
 
 /* Digital3 :: LP_UP3 :: reserved1 [06:06] */
 #define DIGITAL3_LP_UP3_RESERVED1_MASK                             0x0040
 #define DIGITAL3_LP_UP3_RESERVED1_ALIGN                            0
 #define DIGITAL3_LP_UP3_RESERVED1_BITS                             1
 #define DIGITAL3_LP_UP3_RESERVED1_SHIFT                            6
 
 /* Digital3 :: LP_UP3 :: dataRate_40G [05:05] */
 #define DIGITAL3_LP_UP3_DATARATE_40G_MASK                          0x0020
 #define DIGITAL3_LP_UP3_DATARATE_40G_ALIGN                         0
 #define DIGITAL3_LP_UP3_DATARATE_40G_BITS                          1
 #define DIGITAL3_LP_UP3_DATARATE_40G_SHIFT                         5
 
 /* Digital3 :: LP_UP3 :: reserved2 [04:03] */
 #define DIGITAL3_LP_UP3_RESERVED2_MASK                             0x0018
 #define DIGITAL3_LP_UP3_RESERVED2_ALIGN                            0
 #define DIGITAL3_LP_UP3_RESERVED2_BITS                             2
 #define DIGITAL3_LP_UP3_RESERVED2_SHIFT                            3
 
 /* Digital3 :: LP_UP3 :: Cl72 [02:02] */
 #define DIGITAL3_LP_UP3_CL72_MASK                                  0x0004
 #define DIGITAL3_LP_UP3_CL72_ALIGN                                 0
 #define DIGITAL3_LP_UP3_CL72_BITS                                  1
 #define DIGITAL3_LP_UP3_CL72_SHIFT                                 2
 
 /* Digital3 :: LP_UP3 :: FEC [01:01] */
 #define DIGITAL3_LP_UP3_FEC_MASK                                   0x0002
 #define DIGITAL3_LP_UP3_FEC_ALIGN                                  0
 #define DIGITAL3_LP_UP3_FEC_BITS                                   1
 #define DIGITAL3_LP_UP3_FEC_SHIFT                                  1
 
 /* Digital3 :: LP_UP3 :: HiGig2 [00:00] */
 #define DIGITAL3_LP_UP3_HIGIG2_MASK                                0x0001
 #define DIGITAL3_LP_UP3_HIGIG2_ALIGN                               0
 #define DIGITAL3_LP_UP3_HIGIG2_BITS                                1
 #define DIGITAL3_LP_UP3_HIGIG2_SHIFT                               0
 
 
 /****************************************************************************
  * Warpcore_USER_Digital4
  */
 /****************************************************************************
  * Digital4 :: MiscRxStatus
  */
 /* union - case statusSelect0 [15:00] */
 /* Digital4 :: MiscRxStatus :: capture_NP_lh [15:15] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK     0x8000
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN    0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS     1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT    15
 
 /* Digital4 :: MiscRxStatus :: teton_brk_link_lh [14:14] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14
 
 /* Digital4 :: MiscRxStatus :: UP3_lh [13:13] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK            0x2000
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN           0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS            1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT           13
 
 /* Digital4 :: MiscRxStatus :: MP5_lh [12:12] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK            0x1000
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN           0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS            1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT           12
 
 /* Digital4 :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11
 
 /* Digital4 :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10
 
 /* Digital4 :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9
 
 /* Digital4 :: MiscRxStatus :: invalidSeq_lh [08:08] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK     0x0100
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN    0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS     1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT    8
 
 /* Digital4 :: MiscRxStatus :: nullMP_lh [07:07] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK         0x0080
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN        0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS         1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT        7
 
 /* Digital4 :: MiscRxStatus :: remotePhyMP_lh [06:06] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK    0x0040
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN   0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS    1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT   6
 
 /* Digital4 :: MiscRxStatus :: nonMatchingMP_lh [05:05] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK  0x0020
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS  1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5
 
 /* Digital4 :: MiscRxStatus :: over1gMP_lh [04:04] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK       0x0010
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN      0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS       1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT      4
 
 /* Digital4 :: MiscRxStatus :: rx_config_is_0_lh [03:03] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3
 
 /* Digital4 :: MiscRxStatus :: np_toggle_err_lh [02:02] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK  0x0004
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS  1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2
 
 /* Digital4 :: MiscRxStatus :: mr_np_lh [01:01] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK          0x0002
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN         0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS          1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT         1
 
 /* Digital4 :: MiscRxStatus :: mr_bp_lh [00:00] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK          0x0001
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN         0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS          1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT         0
 
 
 /* union - case statusSelect1 [15:00] */
 /* Digital4 :: MiscRxStatus :: reserved0 [15:04] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK         0xfff0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN        0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS         12
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT        4
 
 /* Digital4 :: MiscRxStatus :: np_count [03:00] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK          0x000f
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN         0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS          4
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT         0
 
 
 /* union - case statusSelect2 [15:00] */
 /* Digital4 :: MiscRxStatus :: reserved0 [15:06] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK         0xffc0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN        0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS         10
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT        6
 
 /* Digital4 :: MiscRxStatus :: remote_phy_enable [05:05] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5
 
 /* Digital4 :: MiscRxStatus :: det_teton_mode [04:04] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK    0x0010
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN   0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS    1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT   4
 
 /* Digital4 :: MiscRxStatus :: cu_linkdown [03:03] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK       0x0008
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN      0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS       1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT      3
 
 /* Digital4 :: MiscRxStatus :: cu_resolution_error [02:02] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2
 
 /* Digital4 :: MiscRxStatus :: remotePhy_autosel [01:01] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1
 
 /* Digital4 :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0
 
 
 /* union - case statusSelect3 [15:00] */
 /* Digital4 :: MiscRxStatus :: reserved0 [15:06] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_MASK         0xffc0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_ALIGN        0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_BITS         10
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_SHIFT        6
 
 /* Digital4 :: MiscRxStatus :: sgmii_selector_mismatch [05:05] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_MASK 0x0020
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_SHIFT 5
 
 /* Digital4 :: MiscRxStatus :: autoneg_enable_ov [04:04] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_MASK 0x0010
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_ALIGN 0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_BITS 1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_SHIFT 4
 
 /* Digital4 :: MiscRxStatus :: s_mr_an_enable [03:03] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_MASK    0x0008
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_ALIGN   0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_BITS    1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_SHIFT   3
 
 /* Digital4 :: MiscRxStatus :: s_cl73_rslv_KX4 [02:02] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_MASK   0x0004
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_ALIGN  0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_BITS   1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_SHIFT  2
 
 /* Digital4 :: MiscRxStatus :: s_cl73_rslv_KX [01:01] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_MASK    0x0002
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_ALIGN   0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_BITS    1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_SHIFT   1
 
 /* Digital4 :: MiscRxStatus :: KX_detect [00:00] */
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_MASK         0x0001
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_ALIGN        0
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_BITS         1
 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_SHIFT        0
 
 
 
 /****************************************************************************
  * Digital4 :: lp_basePage
  */
 /* Digital4 :: lp_basePage :: lp_basePage [15:00] */
 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_MASK                      0xffff
 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_ALIGN                     0
 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_BITS                      16
 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_SHIFT                     0
 
 
 /****************************************************************************
  * Digital4 :: lp_nextPage_0
  */
 /* Digital4 :: lp_nextPage_0 :: lp_nextPage_0 [15:00] */
 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_MASK                  0xffff
 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_ALIGN                 0
 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_BITS                  16
 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_SHIFT                 0
 
 
 /****************************************************************************
  * Digital4 :: lp_nextPage_1
  */
 /* Digital4 :: lp_nextPage_1 :: lp_nextPage_1 [15:00] */
 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_MASK                  0xffff
 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_ALIGN                 0
 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_BITS                  16
 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_SHIFT                 0
 
 
 /****************************************************************************
  * Digital4 :: lp_nextPage_2
  */
 /* Digital4 :: lp_nextPage_2 :: lp_nextPage_2 [15:00] */
 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_MASK                  0xffff
 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_ALIGN                 0
 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_BITS                  16
 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_SHIFT                 0
 
 
 /****************************************************************************
  * Digital4 :: lp_nextPage_3
  */
 /* Digital4 :: lp_nextPage_3 :: lp_nextPage_3 [15:00] */
 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_MASK                  0xffff
 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_ALIGN                 0
 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_BITS                  16
 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_SHIFT                 0
 
 
 /****************************************************************************
  * Digital4 :: lp_nextPage_4
  */
 /* Digital4 :: lp_nextPage_4 :: lp_nextPage_4 [15:00] */
 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_MASK                  0xffff
 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_ALIGN                 0
 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_BITS                  16
 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_SHIFT                 0
 
 
 /****************************************************************************
  * Digital4 :: rp_nextPage_0
  */
 /* Digital4 :: rp_nextPage_0 :: reserved0 [15:15] */
 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_MASK                      0x8000
 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_ALIGN                     0
 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_BITS                      1
 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_SHIFT                     15
 
 /* Digital4 :: rp_nextPage_0 :: extra_page_disable [14:14] */
 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_MASK             0x4000
 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_ALIGN            0
 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_BITS             1
 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_SHIFT            14
 
 /* Digital4 :: rp_nextPage_0 :: null_page_enable [13:13] */
 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_MASK               0x2000
 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_ALIGN              0
 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_BITS               1
 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_SHIFT              13
 
 /* Digital4 :: rp_nextPage_0 :: over_1g_disable [12:12] */
 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_MASK                0x1000
 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_ALIGN               0
 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_BITS                1
 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_SHIFT               12
 
 /* Digital4 :: rp_nextPage_0 :: remote_phy_enable [11:11] */
 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_MASK              0x0800
 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_ALIGN             0
 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_BITS              1
 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_SHIFT             11
 
 /* Digital4 :: rp_nextPage_0 :: rp_nextPage_0 [10:00] */
 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_MASK                  0x07ff
 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_ALIGN                 0
 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_BITS                  11
 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_SHIFT                 0
 
 
 /****************************************************************************
  * Digital4 :: rp_nextPage_1
  */
 /* Digital4 :: rp_nextPage_1 :: reserved0 [15:15] */
 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_MASK                      0x8000
 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_ALIGN                     0
 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_BITS                      1
 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_SHIFT                     15
 
 /* Digital4 :: rp_nextPage_1 :: remotePhy_linkDown_rstrt_disable [14:14] */
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_MASK 0x4000
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_ALIGN 0
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_BITS 1
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_SHIFT 14
 
 /* Digital4 :: rp_nextPage_1 :: remotePhy_rsltn_err_rstrt_disable [13:13] */
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_MASK 0x2000
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_ALIGN 0
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_BITS 1
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_SHIFT 13
 
 /* Digital4 :: rp_nextPage_1 :: remotePhy_resolution_disable [12:12] */
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_MASK   0x1000
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_ALIGN  0
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_BITS   1
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_SHIFT  12
 
 /* Digital4 :: rp_nextPage_1 :: remotePhy_decode_enable [11:11] */
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_MASK        0x0800
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_ALIGN       0
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_BITS        1
 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_SHIFT       11
 
 /* Digital4 :: rp_nextPage_1 :: rp_nextPage_1 [10:00] */
 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_MASK                  0x07ff
 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_ALIGN                 0
 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_BITS                  11
 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_SHIFT                 0
 
 
 /****************************************************************************
  * Digital4 :: rp_nextPage_2
  */
 /* Digital4 :: rp_nextPage_2 :: reserved0 [15:12] */
 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_MASK                      0xf000
 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_ALIGN                     0
 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_BITS                      4
 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_SHIFT                     12
 
 /* Digital4 :: rp_nextPage_2 :: remPhy_NP_clr_disable [11:11] */
 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_MASK          0x0800
 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_ALIGN         0
 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_BITS          1
 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_SHIFT         11
 
 /* Digital4 :: rp_nextPage_2 :: rp_nextPage_2 [10:00] */
 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_MASK                  0x07ff
 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_ALIGN                 0
 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_BITS                  11
 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_SHIFT                 0
 
 
 /****************************************************************************
  * Digital4 :: rp_nextPage_3
  */
 /* Digital4 :: rp_nextPage_3 :: reserved0 [15:11] */
 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_MASK                      0xf800
 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_ALIGN                     0
 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_BITS                      5
 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_SHIFT                     11
 
 /* Digital4 :: rp_nextPage_3 :: rp_nextPage_3 [10:00] */
 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_MASK                  0x07ff
 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_ALIGN                 0
 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_BITS                  11
 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_SHIFT                 0
 
 
 /****************************************************************************
  * Digital4 :: rp_nextPage_4
  */
 /* Digital4 :: rp_nextPage_4 :: reserved0 [15:11] */
 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_MASK                      0xf800
 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_ALIGN                     0
 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_BITS                      5
 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_SHIFT                     11
 
 /* Digital4 :: rp_nextPage_4 :: rp_nextPage_4 [10:00] */
 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_MASK                  0x07ff
 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_ALIGN                 0
 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_BITS                  11
 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_SHIFT                 0
 
 
 /****************************************************************************
  * Digital4 :: Misc3
  */
 /* Digital4 :: Misc3 :: ind_40bitif [15:15] */
 #define DIGITAL4_MISC3_IND_40BITIF_MASK                            0x8000
 #define DIGITAL4_MISC3_IND_40BITIF_ALIGN                           0
 #define DIGITAL4_MISC3_IND_40BITIF_BITS                            1
 #define DIGITAL4_MISC3_IND_40BITIF_SHIFT                           15
 
 /* Digital4 :: Misc3 :: cl49_ed66_en_override [14:14] */
 #define DIGITAL4_MISC3_CL49_ED66_EN_OVERRIDE_MASK                  0x4000
 #define DIGITAL4_MISC3_CL49_ED66_EN_OVERRIDE_ALIGN                 0
 #define DIGITAL4_MISC3_CL49_ED66_EN_OVERRIDE_BITS                  1
 #define DIGITAL4_MISC3_CL49_ED66_EN_OVERRIDE_SHIFT                 14
 
 /* Digital4 :: Misc3 :: cl49_ed66_en_val [13:13] */
 #define DIGITAL4_MISC3_CL49_ED66_EN_VAL_MASK                       0x2000
 #define DIGITAL4_MISC3_CL49_ED66_EN_VAL_ALIGN                      0
 #define DIGITAL4_MISC3_CL49_ED66_EN_VAL_BITS                       1
 #define DIGITAL4_MISC3_CL49_ED66_EN_VAL_SHIFT                      13
 
 /* Digital4 :: Misc3 :: fifo_fsm_cya [12:12] */
 #define DIGITAL4_MISC3_FIFO_FSM_CYA_MASK                           0x1000
 #define DIGITAL4_MISC3_FIFO_FSM_CYA_ALIGN                          0
 #define DIGITAL4_MISC3_FIFO_FSM_CYA_BITS                           1
 #define DIGITAL4_MISC3_FIFO_FSM_CYA_SHIFT                          12
 
 /* Digital4 :: Misc3 :: rxck_mii_override_val [11:11] */
 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_MASK                  0x0800
 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_ALIGN                 0
 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_BITS                  1
 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_SHIFT                 11
 
 /* Digital4 :: Misc3 :: rxck_mii_override [10:10] */
 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_MASK                      0x0400
 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_ALIGN                     0
 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_BITS                      1
 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_SHIFT                     10
 
 /* Digital4 :: Misc3 :: fifo_ipg_cya [09:09] */
 #define DIGITAL4_MISC3_FIFO_IPG_CYA_MASK                           0x0200
 #define DIGITAL4_MISC3_FIFO_IPG_CYA_ALIGN                          0
 #define DIGITAL4_MISC3_FIFO_IPG_CYA_BITS                           1
 #define DIGITAL4_MISC3_FIFO_IPG_CYA_SHIFT                          9
 
 /* Digital4 :: Misc3 :: scr_en_per_lane [08:08] */
 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_MASK                        0x0100
 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_ALIGN                       0
 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_BITS                        1
 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_SHIFT                       8
 
 /* Digital4 :: Misc3 :: force_speed_b5 [07:07] */
 #define DIGITAL4_MISC3_FORCE_SPEED_B5_MASK                         0x0080
 #define DIGITAL4_MISC3_FORCE_SPEED_B5_ALIGN                        0
 #define DIGITAL4_MISC3_FORCE_SPEED_B5_BITS                         1
 #define DIGITAL4_MISC3_FORCE_SPEED_B5_SHIFT                        7
 
 /* Digital4 :: Misc3 :: laneDisable [06:06] */
 #define DIGITAL4_MISC3_LANEDISABLE_MASK                            0x0040
 #define DIGITAL4_MISC3_LANEDISABLE_ALIGN                           0
 #define DIGITAL4_MISC3_LANEDISABLE_BITS                            1
 #define DIGITAL4_MISC3_LANEDISABLE_SHIFT                           6
 
 /* Digital4 :: Misc3 :: fifo_err_cya2 [05:05] */
 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_MASK                          0x0020
 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_ALIGN                         0
 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_BITS                          1
 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_SHIFT                         5
 
 /* Digital4 :: Misc3 :: disable_pcs_tx_r [04:04] */
 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_MASK                       0x0010
 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_ALIGN                      0
 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_BITS                       1
 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_SHIFT                      4
 
 /* Digital4 :: Misc3 :: disable_pcs_tx_force_r [03:03] */
 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_MASK                 0x0008
 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_ALIGN                0
 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_BITS                 1
 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_SHIFT                3
 
 /* Digital4 :: Misc3 :: tbi_mode_force_r [02:02] */
 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_MASK                       0x0004
 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_ALIGN                      0
 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_BITS                       1
 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_SHIFT                      2
 
 /* Digital4 :: Misc3 :: rxSigdetPwrdn_override_val [01:01] */
 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_MASK             0x0002
 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_ALIGN            0
 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_BITS             1
 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_SHIFT            1
 
 /* Digital4 :: Misc3 :: rxSigdetPwrdn_override [00:00] */
 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_MASK                 0x0001
 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_ALIGN                0
 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_BITS                 1
 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_SHIFT                0
 
 
 /****************************************************************************
  * Digital4 :: Misc4
  */
 /* Digital4 :: Misc4 :: reserved0 [15:15] */
 #define DIGITAL4_MISC4_RESERVED0_MASK                              0x8000
 #define DIGITAL4_MISC4_RESERVED0_ALIGN                             0
 #define DIGITAL4_MISC4_RESERVED0_BITS                              1
 #define DIGITAL4_MISC4_RESERVED0_SHIFT                             15
 
 /* Digital4 :: Misc4 :: scr_en_over [14:14] */
 #define DIGITAL4_MISC4_SCR_EN_OVER_MASK                            0x4000
 #define DIGITAL4_MISC4_SCR_EN_OVER_ALIGN                           0
 #define DIGITAL4_MISC4_SCR_EN_OVER_BITS                            1
 #define DIGITAL4_MISC4_SCR_EN_OVER_SHIFT                           14
 
 /* Digital4 :: Misc4 :: div33_clk_use_cya [13:13] */
 #define DIGITAL4_MISC4_DIV33_CLK_USE_CYA_MASK                      0x2000
 #define DIGITAL4_MISC4_DIV33_CLK_USE_CYA_ALIGN                     0
 #define DIGITAL4_MISC4_DIV33_CLK_USE_CYA_BITS                      1
 #define DIGITAL4_MISC4_DIV33_CLK_USE_CYA_SHIFT                     13
 
 /* Digital4 :: Misc4 :: os3_en_val [12:12] */
 #define DIGITAL4_MISC4_OS3_EN_VAL_MASK                             0x1000
 #define DIGITAL4_MISC4_OS3_EN_VAL_ALIGN                            0
 #define DIGITAL4_MISC4_OS3_EN_VAL_BITS                             1
 #define DIGITAL4_MISC4_OS3_EN_VAL_SHIFT                            12
 
 /* Digital4 :: Misc4 :: os3_en_override [11:11] */
 #define DIGITAL4_MISC4_OS3_EN_OVERRIDE_MASK                        0x0800
 #define DIGITAL4_MISC4_OS3_EN_OVERRIDE_ALIGN                       0
 #define DIGITAL4_MISC4_OS3_EN_OVERRIDE_BITS                        1
 #define DIGITAL4_MISC4_OS3_EN_OVERRIDE_SHIFT                       11
 
 /* Digital4 :: Misc4 :: decouple_actual_speed [10:10] */
 #define DIGITAL4_MISC4_DECOUPLE_ACTUAL_SPEED_MASK                  0x0400
 #define DIGITAL4_MISC4_DECOUPLE_ACTUAL_SPEED_ALIGN                 0
 #define DIGITAL4_MISC4_DECOUPLE_ACTUAL_SPEED_BITS                  1
 #define DIGITAL4_MISC4_DECOUPLE_ACTUAL_SPEED_SHIFT                 10
 
 /* Digital4 :: Misc4 :: fx_mode_rx_pre [09:09] */
 #define DIGITAL4_MISC4_FX_MODE_RX_PRE_MASK                         0x0200
 #define DIGITAL4_MISC4_FX_MODE_RX_PRE_ALIGN                        0
 #define DIGITAL4_MISC4_FX_MODE_RX_PRE_BITS                         1
 #define DIGITAL4_MISC4_FX_MODE_RX_PRE_SHIFT                        9
 
 /* Digital4 :: Misc4 :: fiber_select_rx_pre [08:08] */
 #define DIGITAL4_MISC4_FIBER_SELECT_RX_PRE_MASK                    0x0100
 #define DIGITAL4_MISC4_FIBER_SELECT_RX_PRE_ALIGN                   0
 #define DIGITAL4_MISC4_FIBER_SELECT_RX_PRE_BITS                    1
 #define DIGITAL4_MISC4_FIBER_SELECT_RX_PRE_SHIFT                   8
 
 /* Digital4 :: Misc4 :: force_speed_rx_pre [07:02] */
 #define DIGITAL4_MISC4_FORCE_SPEED_RX_PRE_MASK                     0x00fc
 #define DIGITAL4_MISC4_FORCE_SPEED_RX_PRE_ALIGN                    0
 #define DIGITAL4_MISC4_FORCE_SPEED_RX_PRE_BITS                     6
 #define DIGITAL4_MISC4_FORCE_SPEED_RX_PRE_SHIFT                    2
 
 /* Digital4 :: Misc4 :: reg0_forced_speed_rx_pre [01:00] */
 #define DIGITAL4_MISC4_REG0_FORCED_SPEED_RX_PRE_MASK               0x0003
 #define DIGITAL4_MISC4_REG0_FORCED_SPEED_RX_PRE_ALIGN              0
 #define DIGITAL4_MISC4_REG0_FORCED_SPEED_RX_PRE_BITS               2
 #define DIGITAL4_MISC4_REG0_FORCED_SPEED_RX_PRE_SHIFT              0
 
 
 /****************************************************************************
  * Digital4 :: Misc5
  */
 /* Digital4 :: Misc5 :: LPI_en_rx [15:15] */
 #define DIGITAL4_MISC5_LPI_EN_RX_MASK                              0x8000
 #define DIGITAL4_MISC5_LPI_EN_RX_ALIGN                             0
 #define DIGITAL4_MISC5_LPI_EN_RX_BITS                              1
 #define DIGITAL4_MISC5_LPI_EN_RX_SHIFT                             15
 
 /* Digital4 :: Misc5 :: LPI_en_tx [14:14] */
 #define DIGITAL4_MISC5_LPI_EN_TX_MASK                              0x4000
 #define DIGITAL4_MISC5_LPI_EN_TX_ALIGN                             0
 #define DIGITAL4_MISC5_LPI_EN_TX_BITS                              1
 #define DIGITAL4_MISC5_LPI_EN_TX_SHIFT                             14
 
 /* Digital4 :: Misc5 :: tgen_data_sel [13:13] */
 #define DIGITAL4_MISC5_TGEN_DATA_SEL_MASK                          0x2000
 #define DIGITAL4_MISC5_TGEN_DATA_SEL_ALIGN                         0
 #define DIGITAL4_MISC5_TGEN_DATA_SEL_BITS                          1
 #define DIGITAL4_MISC5_TGEN_DATA_SEL_SHIFT                         13
 
 /* Digital4 :: Misc5 :: tgen_cx4 [12:12] */
 #define DIGITAL4_MISC5_TGEN_CX4_MASK                               0x1000
 #define DIGITAL4_MISC5_TGEN_CX4_ALIGN                              0
 #define DIGITAL4_MISC5_TGEN_CX4_BITS                               1
 #define DIGITAL4_MISC5_TGEN_CX4_SHIFT                              12
 
 /* Digital4 :: Misc5 :: tgen_link [11:11] */
 #define DIGITAL4_MISC5_TGEN_LINK_MASK                              0x0800
 #define DIGITAL4_MISC5_TGEN_LINK_ALIGN                             0
 #define DIGITAL4_MISC5_TGEN_LINK_BITS                              1
 #define DIGITAL4_MISC5_TGEN_LINK_SHIFT                             11
 
 /* Digital4 :: Misc5 :: tgen_tmsel [10:08] */
 #define DIGITAL4_MISC5_TGEN_TMSEL_MASK                             0x0700
 #define DIGITAL4_MISC5_TGEN_TMSEL_ALIGN                            0
 #define DIGITAL4_MISC5_TGEN_TMSEL_BITS                             3
 #define DIGITAL4_MISC5_TGEN_TMSEL_SHIFT                            8
 
 /* Digital4 :: Misc5 :: reserved0 [07:04] */
 #define DIGITAL4_MISC5_RESERVED0_MASK                              0x00f0
 #define DIGITAL4_MISC5_RESERVED0_ALIGN                             0
 #define DIGITAL4_MISC5_RESERVED0_BITS                              4
 #define DIGITAL4_MISC5_RESERVED0_SHIFT                             4
 
 /* Digital4 :: Misc5 :: rchk_en [03:03] */
 #define DIGITAL4_MISC5_RCHK_EN_MASK                                0x0008
 #define DIGITAL4_MISC5_RCHK_EN_ALIGN                               0
 #define DIGITAL4_MISC5_RCHK_EN_BITS                                1
 #define DIGITAL4_MISC5_RCHK_EN_SHIFT                               3
 
 /* Digital4 :: Misc5 :: rchk_tmsel [02:00] */
 #define DIGITAL4_MISC5_RCHK_TMSEL_MASK                             0x0007
 #define DIGITAL4_MISC5_RCHK_TMSEL_ALIGN                            0
 #define DIGITAL4_MISC5_RCHK_TMSEL_BITS                             3
 #define DIGITAL4_MISC5_RCHK_TMSEL_SHIFT                            0
 
 
 /****************************************************************************
  * Warpcore_USER_Digital5
  */
 /****************************************************************************
  * Digital5 :: linkcnt_cl72_msb
  */
 /* Digital5 :: linkcnt_cl72_msb :: reserved_for_eco0 [15:08] */
 #define DIGITAL5_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_MASK           0xff00
 #define DIGITAL5_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_ALIGN          0
 #define DIGITAL5_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_BITS           8
 #define DIGITAL5_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_SHIFT          8
 
 /* Digital5 :: linkcnt_cl72_msb :: link_cnt_cl72_msbB [07:00] */
 #define DIGITAL5_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_MASK          0x00ff
 #define DIGITAL5_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_ALIGN         0
 #define DIGITAL5_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_BITS          8
 #define DIGITAL5_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_SHIFT         0
 
 
 /****************************************************************************
  * Digital5 :: linkcnt_cl72_lsb
  */
 /* Digital5 :: linkcnt_cl72_lsb :: link_cnt_cl72_lsbB [15:00] */
 #define DIGITAL5_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_MASK          0xffff
 #define DIGITAL5_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_ALIGN         0
 #define DIGITAL5_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_BITS          16
 #define DIGITAL5_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_SHIFT         0
 
 
 /****************************************************************************
  * Digital5 :: LP_UP4
  */
 /* Digital5 :: LP_UP4 :: reserved0 [15:11] */
 #define DIGITAL5_LP_UP4_RESERVED0_MASK                             0xf800
 #define DIGITAL5_LP_UP4_RESERVED0_ALIGN                            0
 #define DIGITAL5_LP_UP4_RESERVED0_BITS                             5
 #define DIGITAL5_LP_UP4_RESERVED0_SHIFT                            11
 
 /* Digital5 :: LP_UP4 :: last [10:10] */
 #define DIGITAL5_LP_UP4_LAST_MASK                                  0x0400
 #define DIGITAL5_LP_UP4_LAST_ALIGN                                 0
 #define DIGITAL5_LP_UP4_LAST_BITS                                  1
 #define DIGITAL5_LP_UP4_LAST_SHIFT                                 10
 
 /* Digital5 :: LP_UP4 :: reserved1 [09:08] */
 #define DIGITAL5_LP_UP4_RESERVED1_MASK                             0x0300
 #define DIGITAL5_LP_UP4_RESERVED1_ALIGN                            0
 #define DIGITAL5_LP_UP4_RESERVED1_BITS                             2
 #define DIGITAL5_LP_UP4_RESERVED1_SHIFT                            8
 
 /* Digital5 :: LP_UP4 :: dataRate_15p75G_dxgxs [07:07] */
 #define DIGITAL5_LP_UP4_DATARATE_15P75G_DXGXS_MASK                 0x0080
 #define DIGITAL5_LP_UP4_DATARATE_15P75G_DXGXS_ALIGN                0
 #define DIGITAL5_LP_UP4_DATARATE_15P75G_DXGXS_BITS                 1
 #define DIGITAL5_LP_UP4_DATARATE_15P75G_DXGXS_SHIFT                7
 
 /* Digital5 :: LP_UP4 :: dataRate_20G_dxgxs [06:06] */
 #define DIGITAL5_LP_UP4_DATARATE_20G_DXGXS_MASK                    0x0040
 #define DIGITAL5_LP_UP4_DATARATE_20G_DXGXS_ALIGN                   0
 #define DIGITAL5_LP_UP4_DATARATE_20G_DXGXS_BITS                    1
 #define DIGITAL5_LP_UP4_DATARATE_20G_DXGXS_SHIFT                   6
 
 /* Digital5 :: LP_UP4 :: dataRate_20Gh_dxgxs [05:05] */
 #define DIGITAL5_LP_UP4_DATARATE_20GH_DXGXS_MASK                   0x0020
 #define DIGITAL5_LP_UP4_DATARATE_20GH_DXGXS_ALIGN                  0
 #define DIGITAL5_LP_UP4_DATARATE_20GH_DXGXS_BITS                   1
 #define DIGITAL5_LP_UP4_DATARATE_20GH_DXGXS_SHIFT                  5
 
 /* Digital5 :: LP_UP4 :: dataRate_12p7G_dxgxs [04:04] */
 #define DIGITAL5_LP_UP4_DATARATE_12P7G_DXGXS_MASK                  0x0010
 #define DIGITAL5_LP_UP4_DATARATE_12P7G_DXGXS_ALIGN                 0
 #define DIGITAL5_LP_UP4_DATARATE_12P7G_DXGXS_BITS                  1
 #define DIGITAL5_LP_UP4_DATARATE_12P7G_DXGXS_SHIFT                 4
 
 /* Digital5 :: LP_UP4 :: dataRate_10p5G_dxgxs [03:03] */
 #define DIGITAL5_LP_UP4_DATARATE_10P5G_DXGXS_MASK                  0x0008
 #define DIGITAL5_LP_UP4_DATARATE_10P5G_DXGXS_ALIGN                 0
 #define DIGITAL5_LP_UP4_DATARATE_10P5G_DXGXS_BITS                  1
 #define DIGITAL5_LP_UP4_DATARATE_10P5G_DXGXS_SHIFT                 3
 
 /* Digital5 :: LP_UP4 :: dataRate_10G_dxgxs [02:02] */
 #define DIGITAL5_LP_UP4_DATARATE_10G_DXGXS_MASK                    0x0004
 #define DIGITAL5_LP_UP4_DATARATE_10G_DXGXS_ALIGN                   0
 #define DIGITAL5_LP_UP4_DATARATE_10G_DXGXS_BITS                    1
 #define DIGITAL5_LP_UP4_DATARATE_10G_DXGXS_SHIFT                   2
 
 /* Digital5 :: LP_UP4 :: dataRate_10Gh_dxgxs [01:01] */
 #define DIGITAL5_LP_UP4_DATARATE_10GH_DXGXS_MASK                   0x0002
 #define DIGITAL5_LP_UP4_DATARATE_10GH_DXGXS_ALIGN                  0
 #define DIGITAL5_LP_UP4_DATARATE_10GH_DXGXS_BITS                   1
 #define DIGITAL5_LP_UP4_DATARATE_10GH_DXGXS_SHIFT                  1
 
 /* Digital5 :: LP_UP4 :: dataRate_20G [00:00] */
 #define DIGITAL5_LP_UP4_DATARATE_20G_MASK                          0x0001
 #define DIGITAL5_LP_UP4_DATARATE_20G_ALIGN                         0
 #define DIGITAL5_LP_UP4_DATARATE_20G_BITS                          1
 #define DIGITAL5_LP_UP4_DATARATE_20G_SHIFT                         0
 
 
 /****************************************************************************
  * Digital5 :: LP_UP5
  */
 /* Digital5 :: LP_UP5 :: reserved0 [15:11] */
 #define DIGITAL5_LP_UP5_RESERVED0_MASK                             0xf800
 #define DIGITAL5_LP_UP5_RESERVED0_ALIGN                            0
 #define DIGITAL5_LP_UP5_RESERVED0_BITS                             5
 #define DIGITAL5_LP_UP5_RESERVED0_SHIFT                            11
 
 /* Digital5 :: LP_UP5 :: last [10:10] */
 #define DIGITAL5_LP_UP5_LAST_MASK                                  0x0400
 #define DIGITAL5_LP_UP5_LAST_ALIGN                                 0
 #define DIGITAL5_LP_UP5_LAST_BITS                                  1
 #define DIGITAL5_LP_UP5_LAST_SHIFT                                 10
 
 /* Digital5 :: LP_UP5 :: reserved1 [09:00] */
 #define DIGITAL5_LP_UP5_RESERVED1_MASK                             0x03ff
 #define DIGITAL5_LP_UP5_RESERVED1_ALIGN                            0
 #define DIGITAL5_LP_UP5_RESERVED1_BITS                             10
 #define DIGITAL5_LP_UP5_RESERVED1_SHIFT                            0
 
 
 /****************************************************************************
  * Digital5 :: LPI_hyst
  */
 /* Digital5 :: LPI_hyst :: reserved_for_eco0 [15:04] */
 #define DIGITAL5_LPI_HYST_RESERVED_FOR_ECO0_MASK                   0xfff0
 #define DIGITAL5_LPI_HYST_RESERVED_FOR_ECO0_ALIGN                  0
 #define DIGITAL5_LPI_HYST_RESERVED_FOR_ECO0_BITS                   12
 #define DIGITAL5_LPI_HYST_RESERVED_FOR_ECO0_SHIFT                  4
 
 /* Digital5 :: LPI_hyst :: LPI_hyst_cnt [03:01] */
 #define DIGITAL5_LPI_HYST_LPI_HYST_CNT_MASK                        0x000e
 #define DIGITAL5_LPI_HYST_LPI_HYST_CNT_ALIGN                       0
 #define DIGITAL5_LPI_HYST_LPI_HYST_CNT_BITS                        3
 #define DIGITAL5_LPI_HYST_LPI_HYST_CNT_SHIFT                       1
 
 /* Digital5 :: LPI_hyst :: LPI_hyst_en [00:00] */
 #define DIGITAL5_LPI_HYST_LPI_HYST_EN_MASK                         0x0001
 #define DIGITAL5_LPI_HYST_LPI_HYST_EN_ALIGN                        0
 #define DIGITAL5_LPI_HYST_LPI_HYST_EN_BITS                         1
 #define DIGITAL5_LPI_HYST_LPI_HYST_EN_SHIFT                        0
 
 
 /****************************************************************************
  * Digital5 :: Misc6
  */
 /* Digital5 :: Misc6 :: reset_rx_asic [15:15] */
 #define DIGITAL5_MISC6_RESET_RX_ASIC_MASK                          0x8000
 #define DIGITAL5_MISC6_RESET_RX_ASIC_ALIGN                         0
 #define DIGITAL5_MISC6_RESET_RX_ASIC_BITS                          1
 #define DIGITAL5_MISC6_RESET_RX_ASIC_SHIFT                         15
 
 /* Digital5 :: Misc6 :: reset_tx_asic [14:14] */
 #define DIGITAL5_MISC6_RESET_TX_ASIC_MASK                          0x4000
 #define DIGITAL5_MISC6_RESET_TX_ASIC_ALIGN                         0
 #define DIGITAL5_MISC6_RESET_TX_ASIC_BITS                          1
 #define DIGITAL5_MISC6_RESET_TX_ASIC_SHIFT                         14
 
 /* Digital5 :: Misc6 :: pmd_energy_detect_dgltch_en [13:13] */
 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_EN_MASK            0x2000
 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_EN_ALIGN           0
 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_EN_BITS            1
 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_EN_SHIFT           13
 
 /* Digital5 :: Misc6 :: pmd_energy_detect_dgltch_sel [12:11] */
 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_SEL_MASK           0x1800
 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_SEL_ALIGN          0
 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_SEL_BITS           2
 #define DIGITAL5_MISC6_PMD_ENERGY_DETECT_DGLTCH_SEL_SHIFT          11
 
 /* Digital5 :: Misc6 :: pcs1g_ckgate_en [10:10] */
 #define DIGITAL5_MISC6_PCS1G_CKGATE_EN_MASK                        0x0400
 #define DIGITAL5_MISC6_PCS1G_CKGATE_EN_ALIGN                       0
 #define DIGITAL5_MISC6_PCS1G_CKGATE_EN_BITS                        1
 #define DIGITAL5_MISC6_PCS1G_CKGATE_EN_SHIFT                       10
 
 /* Digital5 :: Misc6 :: ind_80bitif [09:09] */
 #define DIGITAL5_MISC6_IND_80BITIF_MASK                            0x0200
 #define DIGITAL5_MISC6_IND_80BITIF_ALIGN                           0
 #define DIGITAL5_MISC6_IND_80BITIF_BITS                            1
 #define DIGITAL5_MISC6_IND_80BITIF_SHIFT                           9
 
 /* Digital5 :: Misc6 :: rx_os8_frst_SM [08:08] */
 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_MASK                         0x0100
 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_ALIGN                        0
 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_BITS                         1
 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_SHIFT                        8
 
 /* Digital5 :: Misc6 :: use_brcm6466_31500_cya [07:07] */
 #define DIGITAL5_MISC6_USE_BRCM6466_31500_CYA_MASK                 0x0080
 #define DIGITAL5_MISC6_USE_BRCM6466_31500_CYA_ALIGN                0
 #define DIGITAL5_MISC6_USE_BRCM6466_31500_CYA_BITS                 1
 #define DIGITAL5_MISC6_USE_BRCM6466_31500_CYA_SHIFT                7
 
 /* Digital5 :: Misc6 :: cx4_sigdet_filt_all_speed [06:06] */
 #define DIGITAL5_MISC6_CX4_SIGDET_FILT_ALL_SPEED_MASK              0x0040
 #define DIGITAL5_MISC6_CX4_SIGDET_FILT_ALL_SPEED_ALIGN             0
 #define DIGITAL5_MISC6_CX4_SIGDET_FILT_ALL_SPEED_BITS              1
 #define DIGITAL5_MISC6_CX4_SIGDET_FILT_ALL_SPEED_SHIFT             6
 
 /* Digital5 :: Misc6 :: pcs_type_sel_1000x_cya [05:05] */
 #define DIGITAL5_MISC6_PCS_TYPE_SEL_1000X_CYA_MASK                 0x0020
 #define DIGITAL5_MISC6_PCS_TYPE_SEL_1000X_CYA_ALIGN                0
 #define DIGITAL5_MISC6_PCS_TYPE_SEL_1000X_CYA_BITS                 1
 #define DIGITAL5_MISC6_PCS_TYPE_SEL_1000X_CYA_SHIFT                5
 
 /* Digital5 :: Misc6 :: rx_os8_os3_alt_bits_cya [04:04] */
 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_MASK                0x0010
 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_ALIGN               0
 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_BITS                1
 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_SHIFT               4
 
 /* Digital5 :: Misc6 :: an_completeTrap [03:03] */
 #define DIGITAL5_MISC6_AN_COMPLETETRAP_MASK                        0x0008
 #define DIGITAL5_MISC6_AN_COMPLETETRAP_ALIGN                       0
 #define DIGITAL5_MISC6_AN_COMPLETETRAP_BITS                        1
 #define DIGITAL5_MISC6_AN_COMPLETETRAP_SHIFT                       3
 
 /* Digital5 :: Misc6 :: an_wait4linkTrap [02:02] */
 #define DIGITAL5_MISC6_AN_WAIT4LINKTRAP_MASK                       0x0004
 #define DIGITAL5_MISC6_AN_WAIT4LINKTRAP_ALIGN                      0
 #define DIGITAL5_MISC6_AN_WAIT4LINKTRAP_BITS                       1
 #define DIGITAL5_MISC6_AN_WAIT4LINKTRAP_SHIFT                      2
 
 /* Digital5 :: Misc6 :: tx_os8_afrst_en [01:01] */
 #define DIGITAL5_MISC6_TX_OS8_AFRST_EN_MASK                        0x0002
 #define DIGITAL5_MISC6_TX_OS8_AFRST_EN_ALIGN                       0
 #define DIGITAL5_MISC6_TX_OS8_AFRST_EN_BITS                        1
 #define DIGITAL5_MISC6_TX_OS8_AFRST_EN_SHIFT                       1
 
 /* Digital5 :: Misc6 :: tx_os8_frst_SM [00:00] */
 #define DIGITAL5_MISC6_TX_OS8_FRST_SM_MASK                         0x0001
 #define DIGITAL5_MISC6_TX_OS8_FRST_SM_ALIGN                        0
 #define DIGITAL5_MISC6_TX_OS8_FRST_SM_BITS                         1
 #define DIGITAL5_MISC6_TX_OS8_FRST_SM_SHIFT                        0
 
 
 /****************************************************************************
  * Digital5 :: parDetINDStatus
  */
 /* union - case pd_stat_sel_equals_0 [15:00] */
 /* Digital5 :: parDetINDStatus :: rcv100fx_lh [15:15] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RCV100FX_LH_MASK 0x8000
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RCV100FX_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RCV100FX_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RCV100FX_LH_SHIFT 15
 
 /* Digital5 :: parDetINDStatus :: wait4link_100fx_lh [14:14] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_WAIT4LINK_100FX_LH_MASK 0x4000
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_WAIT4LINK_100FX_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_WAIT4LINK_100FX_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_WAIT4LINK_100FX_LH_SHIFT 14
 
 /* Digital5 :: parDetINDStatus :: txdon_100fx_lh [13:13] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_TXDON_100FX_LH_MASK 0x2000
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_TXDON_100FX_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_TXDON_100FX_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_TXDON_100FX_LH_SHIFT 13
 
 /* Digital5 :: parDetINDStatus :: link_100fx_retry_lh [12:12] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_LINK_100FX_RETRY_LH_MASK 0x1000
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_LINK_100FX_RETRY_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_LINK_100FX_RETRY_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_LINK_100FX_RETRY_LH_SHIFT 12
 
 /* Digital5 :: parDetINDStatus :: reserved0 [11:11] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RESERVED0_MASK 0x0800
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RESERVED0_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RESERVED0_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RESERVED0_SHIFT 11
 
 /* Digital5 :: parDetINDStatus :: pd_xfi_en_rx [10:10] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_RX_MASK 0x0400
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_RX_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_RX_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_RX_SHIFT 10
 
 /* Digital5 :: parDetINDStatus :: pd_2p5g_en_rx [09:09] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_RX_MASK 0x0200
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_RX_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_RX_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_RX_SHIFT 9
 
 /* Digital5 :: parDetINDStatus :: pd_100fx_en_rx [08:08] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_RX_MASK 0x0100
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_RX_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_RX_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_RX_SHIFT 8
 
 /* Digital5 :: parDetINDStatus :: pd_link_ind [07:07] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_LINK_IND_MASK 0x0080
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_LINK_IND_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_LINK_IND_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_LINK_IND_SHIFT 7
 
 /* Digital5 :: parDetINDStatus :: pd_xfi_en_tx [06:06] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_TX_MASK 0x0040
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_TX_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_TX_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_XFI_EN_TX_SHIFT 6
 
 /* Digital5 :: parDetINDStatus :: pd_2p5g_en_tx [05:05] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_TX_MASK 0x0020
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_TX_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_TX_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_2P5G_EN_TX_SHIFT 5
 
 /* Digital5 :: parDetINDStatus :: pd_100fx_en_tx [04:04] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_TX_MASK 0x0010
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_TX_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_TX_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_100FX_EN_TX_SHIFT 4
 
 /* Digital5 :: parDetINDStatus :: pd_ind_txdLaneOff [03:03] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_IND_TXDLANEOFF_MASK 0x0008
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_IND_TXDLANEOFF_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_IND_TXDLANEOFF_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_IND_TXDLANEOFF_SHIFT 3
 
 /* Digital5 :: parDetINDStatus :: pd_busy [02:02] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_BUSY_MASK 0x0004
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_BUSY_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_BUSY_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_BUSY_SHIFT 2
 
 /* Digital5 :: parDetINDStatus :: pd_park_IND_an [01:01] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_PARK_IND_AN_MASK 0x0002
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_PARK_IND_AN_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_PARK_IND_AN_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_PD_PARK_IND_AN_SHIFT 1
 
 /* Digital5 :: parDetINDStatus :: rxSeqDone [00:00] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RXSEQDONE_MASK 0x0001
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RXSEQDONE_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RXSEQDONE_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_0_RXSEQDONE_SHIFT 0
 
 
 /* union - case pd_stat_sel_equals_1 [15:00] */
 /* Digital5 :: parDetINDStatus :: wait4lock_lh [15:15] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LOCK_LH_MASK 0x8000
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LOCK_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LOCK_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LOCK_LH_SHIFT 15
 
 /* Digital5 :: parDetINDStatus :: wait4sigdet_lh [14:14] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4SIGDET_LH_MASK 0x4000
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4SIGDET_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4SIGDET_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4SIGDET_LH_SHIFT 14
 
 /* Digital5 :: parDetINDStatus :: txdfreeze_lh [13:13] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDFREEZE_LH_MASK 0x2000
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDFREEZE_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDFREEZE_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDFREEZE_LH_SHIFT 13
 
 /* Digital5 :: parDetINDStatus :: rcvxfi_lh [12:12] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCVXFI_LH_MASK 0x1000
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCVXFI_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCVXFI_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCVXFI_LH_SHIFT 12
 
 /* Digital5 :: parDetINDStatus :: rcv2p5g_lh [11:11] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCV2P5G_LH_MASK 0x0800
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCV2P5G_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCV2P5G_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_RCV2P5G_LH_SHIFT 11
 
 /* Digital5 :: parDetINDStatus :: wait4link_xfi_lh [10:10] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_XFI_LH_MASK 0x0400
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_XFI_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_XFI_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_XFI_LH_SHIFT 10
 
 /* Digital5 :: parDetINDStatus :: wait4link_2p5g_lh [09:09] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_2P5G_LH_MASK 0x0200
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_2P5G_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_2P5G_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_WAIT4LINK_2P5G_LH_SHIFT 9
 
 /* Digital5 :: parDetINDStatus :: link_xfi_retry_lh [08:08] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_XFI_RETRY_LH_MASK 0x0100
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_XFI_RETRY_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_XFI_RETRY_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_XFI_RETRY_LH_SHIFT 8
 
 /* Digital5 :: parDetINDStatus :: txdon_xfi_lh [07:07] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_XFI_LH_MASK 0x0080
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_XFI_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_XFI_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_XFI_LH_SHIFT 7
 
 /* Digital5 :: parDetINDStatus :: txdon_2p5g_lh [06:06] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_2P5G_LH_MASK 0x0040
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_2P5G_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_2P5G_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_2P5G_LH_SHIFT 6
 
 /* Digital5 :: parDetINDStatus :: txdon_lh [05:05] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_LH_MASK 0x0020
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_TXDON_LH_SHIFT 5
 
 /* Digital5 :: parDetINDStatus :: lostlink_lh [04:04] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LOSTLINK_LH_MASK 0x0010
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LOSTLINK_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LOSTLINK_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LOSTLINK_LH_SHIFT 4
 
 /* Digital5 :: parDetINDStatus :: link_2p5g_retry_lh [03:03] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_2P5G_RETRY_LH_MASK 0x0008
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_2P5G_RETRY_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_2P5G_RETRY_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_LINK_2P5G_RETRY_LH_SHIFT 3
 
 /* Digital5 :: parDetINDStatus :: complete_lh [02:02] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_COMPLETE_LH_MASK 0x0004
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_COMPLETE_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_COMPLETE_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_COMPLETE_LH_SHIFT 2
 
 /* Digital5 :: parDetINDStatus :: fail_lh [01:01] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_FAIL_LH_MASK 0x0002
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_FAIL_LH_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_FAIL_LH_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_FAIL_LH_SHIFT 1
 
 /* Digital5 :: parDetINDStatus :: s_parDet_ind_en [00:00] */
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_S_PARDET_IND_EN_MASK 0x0001
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_S_PARDET_IND_EN_ALIGN 0
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_S_PARDET_IND_EN_BITS 1
 #define DIGITAL5_PARDETINDSTATUS_PD_STAT_SEL_EQUALS_1_S_PARDET_IND_EN_SHIFT 0
 
 
 
 /****************************************************************************
  * Digital5 :: parDetINDControl1
  */
 /* Digital5 :: parDetINDControl1 :: pd_parkFail [15:15] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_PARKFAIL_MASK                0x8000
 #define DIGITAL5_PARDETINDCONTROL1_PD_PARKFAIL_ALIGN               0
 #define DIGITAL5_PARDETINDCONTROL1_PD_PARKFAIL_BITS                1
 #define DIGITAL5_PARDETINDCONTROL1_PD_PARKFAIL_SHIFT               15
 
 /* Digital5 :: parDetINDControl1 :: pd_sw_overide [14:14] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_OVERIDE_MASK              0x4000
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_OVERIDE_ALIGN             0
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_OVERIDE_BITS              1
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_OVERIDE_SHIFT             14
 
 /* Digital5 :: parDetINDControl1 :: pd_txdfreeze_en [13:13] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_TXDFREEZE_EN_MASK            0x2000
 #define DIGITAL5_PARDETINDCONTROL1_PD_TXDFREEZE_EN_ALIGN           0
 #define DIGITAL5_PARDETINDCONTROL1_PD_TXDFREEZE_EN_BITS            1
 #define DIGITAL5_PARDETINDCONTROL1_PD_TXDFREEZE_EN_SHIFT           13
 
 /* Digital5 :: parDetINDControl1 :: pd_sw_xfi_en_tx [12:12] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_TX_MASK            0x1000
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_TX_ALIGN           0
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_TX_BITS            1
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_TX_SHIFT           12
 
 /* Digital5 :: parDetINDControl1 :: pd_sw_2p5g_en_tx [11:11] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_TX_MASK           0x0800
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_TX_ALIGN          0
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_TX_BITS           1
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_TX_SHIFT          11
 
 /* Digital5 :: parDetINDControl1 :: pd_sw_100fx_en_tx [10:10] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_TX_MASK          0x0400
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_TX_ALIGN         0
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_TX_BITS          1
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_TX_SHIFT         10
 
 /* Digital5 :: parDetINDControl1 :: pd_sw_txdOff [09:09] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_TXDOFF_MASK               0x0200
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_TXDOFF_ALIGN              0
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_TXDOFF_BITS               1
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_TXDOFF_SHIFT              9
 
 /* Digital5 :: parDetINDControl1 :: pd_sw_100fx_en_rx [08:08] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_RX_MASK          0x0100
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_RX_ALIGN         0
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_RX_BITS          1
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_100FX_EN_RX_SHIFT         8
 
 /* Digital5 :: parDetINDControl1 :: pd_100fx_disable [07:07] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_100FX_DISABLE_MASK           0x0080
 #define DIGITAL5_PARDETINDCONTROL1_PD_100FX_DISABLE_ALIGN          0
 #define DIGITAL5_PARDETINDCONTROL1_PD_100FX_DISABLE_BITS           1
 #define DIGITAL5_PARDETINDCONTROL1_PD_100FX_DISABLE_SHIFT          7
 
 /* Digital5 :: parDetINDControl1 :: pd_sw_2p5g_en_rx [06:06] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_RX_MASK           0x0040
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_RX_ALIGN          0
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_RX_BITS           1
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_2P5G_EN_RX_SHIFT          6
 
 /* Digital5 :: parDetINDControl1 :: pd_2p5g_disable [05:05] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_2P5G_DISABLE_MASK            0x0020
 #define DIGITAL5_PARDETINDCONTROL1_PD_2P5G_DISABLE_ALIGN           0
 #define DIGITAL5_PARDETINDCONTROL1_PD_2P5G_DISABLE_BITS            1
 #define DIGITAL5_PARDETINDCONTROL1_PD_2P5G_DISABLE_SHIFT           5
 
 /* Digital5 :: parDetINDControl1 :: pd_sw_xfi_en_rx [04:04] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_RX_MASK            0x0010
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_RX_ALIGN           0
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_RX_BITS            1
 #define DIGITAL5_PARDETINDCONTROL1_PD_SW_XFI_EN_RX_SHIFT           4
 
 /* Digital5 :: parDetINDControl1 :: pd_xfi_disable [03:03] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_XFI_DISABLE_MASK             0x0008
 #define DIGITAL5_PARDETINDCONTROL1_PD_XFI_DISABLE_ALIGN            0
 #define DIGITAL5_PARDETINDCONTROL1_PD_XFI_DISABLE_BITS             1
 #define DIGITAL5_PARDETINDCONTROL1_PD_XFI_DISABLE_SHIFT            3
 
 /* Digital5 :: parDetINDControl1 :: pd_stat_sel [02:02] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_STAT_SEL_MASK                0x0004
 #define DIGITAL5_PARDETINDCONTROL1_PD_STAT_SEL_ALIGN               0
 #define DIGITAL5_PARDETINDCONTROL1_PD_STAT_SEL_BITS                1
 #define DIGITAL5_PARDETINDCONTROL1_PD_STAT_SEL_SHIFT               2
 
 /* Digital5 :: parDetINDControl1 :: pd_fast_timer_en [01:01] */
 #define DIGITAL5_PARDETINDCONTROL1_PD_FAST_TIMER_EN_MASK           0x0002
 #define DIGITAL5_PARDETINDCONTROL1_PD_FAST_TIMER_EN_ALIGN          0
 #define DIGITAL5_PARDETINDCONTROL1_PD_FAST_TIMER_EN_BITS           1
 #define DIGITAL5_PARDETINDCONTROL1_PD_FAST_TIMER_EN_SHIFT          1
 
 /* Digital5 :: parDetINDControl1 :: parDetind_en [00:00] */
 #define DIGITAL5_PARDETINDCONTROL1_PARDETIND_EN_MASK               0x0001
 #define DIGITAL5_PARDETINDCONTROL1_PARDETIND_EN_ALIGN              0
 #define DIGITAL5_PARDETINDCONTROL1_PARDETIND_EN_BITS               1
 #define DIGITAL5_PARDETINDCONTROL1_PARDETIND_EN_SHIFT              0
 
 
 /****************************************************************************
  * Digital5 :: parDetINDControl2
  */
 /* Digital5 :: parDetINDControl2 :: reserved0 [15:04] */
 #define DIGITAL5_PARDETINDCONTROL2_RESERVED0_MASK                  0xfff0
 #define DIGITAL5_PARDETINDCONTROL2_RESERVED0_ALIGN                 0
 #define DIGITAL5_PARDETINDCONTROL2_RESERVED0_BITS                  12
 #define DIGITAL5_PARDETINDCONTROL2_RESERVED0_SHIFT                 4
 
 /* Digital5 :: parDetINDControl2 :: pd_xfi_init [03:03] */
 #define DIGITAL5_PARDETINDCONTROL2_PD_XFI_INIT_MASK                0x0008
 #define DIGITAL5_PARDETINDCONTROL2_PD_XFI_INIT_ALIGN               0
 #define DIGITAL5_PARDETINDCONTROL2_PD_XFI_INIT_BITS                1
 #define DIGITAL5_PARDETINDCONTROL2_PD_XFI_INIT_SHIFT               3
 
 /* Digital5 :: parDetINDControl2 :: pd_sw_busy_an [02:02] */
 #define DIGITAL5_PARDETINDCONTROL2_PD_SW_BUSY_AN_MASK              0x0004
 #define DIGITAL5_PARDETINDCONTROL2_PD_SW_BUSY_AN_ALIGN             0
 #define DIGITAL5_PARDETINDCONTROL2_PD_SW_BUSY_AN_BITS              1
 #define DIGITAL5_PARDETINDCONTROL2_PD_SW_BUSY_AN_SHIFT             2
 
 /* Digital5 :: parDetINDControl2 :: pd_cl73_couple_dis [01:01] */
 #define DIGITAL5_PARDETINDCONTROL2_PD_CL73_COUPLE_DIS_MASK         0x0002
 #define DIGITAL5_PARDETINDCONTROL2_PD_CL73_COUPLE_DIS_ALIGN        0
 #define DIGITAL5_PARDETINDCONTROL2_PD_CL73_COUPLE_DIS_BITS         1
 #define DIGITAL5_PARDETINDCONTROL2_PD_CL73_COUPLE_DIS_SHIFT        1
 
 /* Digital5 :: parDetINDControl2 :: pd_IgnoreLink_dis [00:00] */
 #define DIGITAL5_PARDETINDCONTROL2_PD_IGNORELINK_DIS_MASK          0x0001
 #define DIGITAL5_PARDETINDCONTROL2_PD_IGNORELINK_DIS_ALIGN         0
 #define DIGITAL5_PARDETINDCONTROL2_PD_IGNORELINK_DIS_BITS          1
 #define DIGITAL5_PARDETINDCONTROL2_PD_IGNORELINK_DIS_SHIFT         0
 
 
 /****************************************************************************
  * Digital5 :: Misc7
  */
 /* Digital5 :: Misc7 :: reserved0 [15:08] */
 #define DIGITAL5_MISC7_RESERVED0_MASK                              0xff00
 #define DIGITAL5_MISC7_RESERVED0_ALIGN                             0
 #define DIGITAL5_MISC7_RESERVED0_BITS                              8
 #define DIGITAL5_MISC7_RESERVED0_SHIFT                             8
 
 /* Digital5 :: Misc7 :: force_speed_rx_pre_7_6 [07:06] */
 #define DIGITAL5_MISC7_FORCE_SPEED_RX_PRE_7_6_MASK                 0x00c0
 #define DIGITAL5_MISC7_FORCE_SPEED_RX_PRE_7_6_ALIGN                0
 #define DIGITAL5_MISC7_FORCE_SPEED_RX_PRE_7_6_BITS                 2
 #define DIGITAL5_MISC7_FORCE_SPEED_RX_PRE_7_6_SHIFT                6
 
 /* Digital5 :: Misc7 :: brcm6466_cl49_in_all_mode_cya [05:05] */
 #define DIGITAL5_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_MASK          0x0020
 #define DIGITAL5_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_ALIGN         0
 #define DIGITAL5_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_BITS          1
 #define DIGITAL5_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_SHIFT         5
 
 /* Digital5 :: Misc7 :: xfi_txfault_pll_cya [04:04] */
 #define DIGITAL5_MISC7_XFI_TXFAULT_PLL_CYA_MASK                    0x0010
 #define DIGITAL5_MISC7_XFI_TXFAULT_PLL_CYA_ALIGN                   0
 #define DIGITAL5_MISC7_XFI_TXFAULT_PLL_CYA_BITS                    1
 #define DIGITAL5_MISC7_XFI_TXFAULT_PLL_CYA_SHIFT                   4
 
 /* Digital5 :: Misc7 :: xfi_txfault_ext_cya [03:03] */
 #define DIGITAL5_MISC7_XFI_TXFAULT_EXT_CYA_MASK                    0x0008
 #define DIGITAL5_MISC7_XFI_TXFAULT_EXT_CYA_ALIGN                   0
 #define DIGITAL5_MISC7_XFI_TXFAULT_EXT_CYA_BITS                    1
 #define DIGITAL5_MISC7_XFI_TXFAULT_EXT_CYA_SHIFT                   3
 
 /* Digital5 :: Misc7 :: xfi_txfault_det_cya [02:02] */
 #define DIGITAL5_MISC7_XFI_TXFAULT_DET_CYA_MASK                    0x0004
 #define DIGITAL5_MISC7_XFI_TXFAULT_DET_CYA_ALIGN                   0
 #define DIGITAL5_MISC7_XFI_TXFAULT_DET_CYA_BITS                    1
 #define DIGITAL5_MISC7_XFI_TXFAULT_DET_CYA_SHIFT                   2
 
 /* Digital5 :: Misc7 :: xfi_rxfault_link_cya [01:01] */
 #define DIGITAL5_MISC7_XFI_RXFAULT_LINK_CYA_MASK                   0x0002
 #define DIGITAL5_MISC7_XFI_RXFAULT_LINK_CYA_ALIGN                  0
 #define DIGITAL5_MISC7_XFI_RXFAULT_LINK_CYA_BITS                   1
 #define DIGITAL5_MISC7_XFI_RXFAULT_LINK_CYA_SHIFT                  1
 
 /* Digital5 :: Misc7 :: xfi_rxfault_det_cya [00:00] */
 #define DIGITAL5_MISC7_XFI_RXFAULT_DET_CYA_MASK                    0x0001
 #define DIGITAL5_MISC7_XFI_RXFAULT_DET_CYA_ALIGN                   0
 #define DIGITAL5_MISC7_XFI_RXFAULT_DET_CYA_BITS                    1
 #define DIGITAL5_MISC7_XFI_RXFAULT_DET_CYA_SHIFT                   0
 
 
 /****************************************************************************
  * Digital5 :: link_status
  */
 /* Digital5 :: link_status :: reserved0 [15:06] */
 #define DIGITAL5_LINK_STATUS_RESERVED0_MASK                        0xffc0
 #define DIGITAL5_LINK_STATUS_RESERVED0_ALIGN                       0
 #define DIGITAL5_LINK_STATUS_RESERVED0_BITS                        10
 #define DIGITAL5_LINK_STATUS_RESERVED0_SHIFT                       6
 
 /* Digital5 :: link_status :: ll_link [05:05] */
 #define DIGITAL5_LINK_STATUS_LL_LINK_MASK                          0x0020
 #define DIGITAL5_LINK_STATUS_LL_LINK_ALIGN                         0
 #define DIGITAL5_LINK_STATUS_LL_LINK_BITS                          1
 #define DIGITAL5_LINK_STATUS_LL_LINK_SHIFT                         5
 
 /* Digital5 :: link_status :: l_an_link [04:04] */
 #define DIGITAL5_LINK_STATUS_L_AN_LINK_MASK                        0x0010
 #define DIGITAL5_LINK_STATUS_L_AN_LINK_ALIGN                       0
 #define DIGITAL5_LINK_STATUS_L_AN_LINK_BITS                        1
 #define DIGITAL5_LINK_STATUS_L_AN_LINK_SHIFT                       4
 
 /* Digital5 :: link_status :: l_link_kr [03:03] */
 #define DIGITAL5_LINK_STATUS_L_LINK_KR_MASK                        0x0008
 #define DIGITAL5_LINK_STATUS_L_LINK_KR_ALIGN                       0
 #define DIGITAL5_LINK_STATUS_L_LINK_KR_BITS                        1
 #define DIGITAL5_LINK_STATUS_L_LINK_KR_SHIFT                       3
 
 /* Digital5 :: link_status :: l_link10g [02:02] */
 #define DIGITAL5_LINK_STATUS_L_LINK10G_MASK                        0x0004
 #define DIGITAL5_LINK_STATUS_L_LINK10G_ALIGN                       0
 #define DIGITAL5_LINK_STATUS_L_LINK10G_BITS                        1
 #define DIGITAL5_LINK_STATUS_L_LINK10G_SHIFT                       2
 
 /* Digital5 :: link_status :: l_link_status [01:01] */
 #define DIGITAL5_LINK_STATUS_L_LINK_STATUS_MASK                    0x0002
 #define DIGITAL5_LINK_STATUS_L_LINK_STATUS_ALIGN                   0
 #define DIGITAL5_LINK_STATUS_L_LINK_STATUS_BITS                    1
 #define DIGITAL5_LINK_STATUS_L_LINK_STATUS_SHIFT                   1
 
 /* Digital5 :: link_status :: l_link [00:00] */
 #define DIGITAL5_LINK_STATUS_L_LINK_MASK                           0x0001
 #define DIGITAL5_LINK_STATUS_L_LINK_ALIGN                          0
 #define DIGITAL5_LINK_STATUS_L_LINK_BITS                           1
 #define DIGITAL5_LINK_STATUS_L_LINK_SHIFT                          0
 
 
 /****************************************************************************
  * Digital5 :: actual_speed
  */
 /* Digital5 :: actual_speed :: reserved_for_eco0 [15:14] */
 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO0_MASK               0xc000
 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO0_ALIGN              0
 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO0_BITS               2
 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO0_SHIFT              14
 
 /* Digital5 :: actual_speed :: actual_speed_rx [13:08] */
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_MASK                 0x3f00
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_ALIGN                0
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_BITS                 6
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_SHIFT                8
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10M               0
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_100M              1
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_1G                2
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_2p5G              3
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_5G_X4             4
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_6G_X4             5
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_HiG           6
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_CX4           7
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_12G_HiG           8
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_12p5G_X4          9
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_13G_X4            10
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_15G_X4            11
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_16G_X4            12
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_1G_KX             13
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_KX4           14
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_KR            15
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_5G                16
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_6p4G              17
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_20G_X4            18
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_21G_X4            19
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_25G_X4            20
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_HiG_DXGXS     21
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_DXGXS         22
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10p5G_HiG_DXGXS   23
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10p5G_DXGXS       24
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_12p773G_HiG_DXGXS 25
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_12p773G_DXGXS     26
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_XFI           27
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_40G               28
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_20G_HiG_DXGXS     29
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_20G_DXGXS         30
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_SFI           31
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_31p5G             32
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_32p7G             33
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_20G_SCR           34
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_HiG_DXGXS_SCR 35
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_DXGXS_SCR     36
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_12G_R2            37
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_10G_X2            38
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_40G_KR4           39
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_40G_CR4           40
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_RX_dr_100G_CR10         41
 
 /* Digital5 :: actual_speed :: reserved_for_eco1 [07:06] */
 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO1_MASK               0x00c0
 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO1_ALIGN              0
 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO1_BITS               2
 #define DIGITAL5_ACTUAL_SPEED_RESERVED_FOR_ECO1_SHIFT              6
 
 /* Digital5 :: actual_speed :: actual_speed_tx [05:00] */
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_MASK                 0x003f
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_ALIGN                0
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_BITS                 6
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_SHIFT                0
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10M               0
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_100M              1
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_1G                2
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_2p5G              3
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_5G_X4             4
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_6G_X4             5
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_HiG           6
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_CX4           7
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_12G_HiG           8
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_12p5G_X4          9
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_13G_X4            10
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_15G_X4            11
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_16G_X4            12
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_1G_KX             13
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_KX4           14
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_KR            15
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_5G                16
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_6p4G              17
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_20G_X4            18
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_21G_X4            19
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_25G_X4            20
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_HiG_DXGXS     21
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_DXGXS         22
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10p5G_HiG_DXGXS   23
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10p5G_DXGXS       24
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_12p773G_HiG_DXGXS 25
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_12p773G_DXGXS     26
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_XFI           27
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_40G               28
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_20G_HiG_DXGXS     29
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_20G_DXGXS         30
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_SFI           31
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_31p5G             32
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_32p7G             33
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_20G_SCR           34
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_HiG_DXGXS_SCR 35
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_DXGXS_SCR     36
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_12G_R2            37
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_10G_X2            38
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_40G_KR4           39
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_40G_CR4           40
 #define DIGITAL5_ACTUAL_SPEED_ACTUAL_SPEED_TX_dr_100G_CR10         41
 
 
 /****************************************************************************
  * Warpcore_USER_Digital6
  */
 /****************************************************************************
  * Digital6 :: mp5_NextPageCtrl
  */
 /* Digital6 :: mp5_NextPageCtrl :: reserved0 [15:04] */
 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_MASK                   0xfff0
 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_ALIGN                  0
 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_BITS                   12
 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_SHIFT                  4
 
 /* Digital6 :: mp5_NextPageCtrl :: np_sw_overRide_en [03:03] */
 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_MASK           0x0008
 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_ALIGN          0
 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_BITS           1
 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_SHIFT          3
 
 /* Digital6 :: mp5_NextPageCtrl :: teton_mode_up3_en [02:02] */
 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_MASK           0x0004
 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_ALIGN          0
 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_BITS           1
 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_SHIFT          2
 
 /* Digital6 :: mp5_NextPageCtrl :: teton_mode [01:01] */
 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_MASK                  0x0002
 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_ALIGN                 0
 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_BITS                  1
 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_SHIFT                 1
 
 /* Digital6 :: mp5_NextPageCtrl :: bam_mode [00:00] */
 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_MASK                    0x0001
 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_ALIGN                   0
 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_BITS                    1
 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_SHIFT                   0
 
 
 /****************************************************************************
  * Digital6 :: link_timer_offset1
  */
 /* Digital6 :: link_timer_offset1 :: sgmii_offset [15:08] */
 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_MASK              0xff00
 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_ALIGN             0
 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_BITS              8
 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_SHIFT             8
 
 /* Digital6 :: link_timer_offset1 :: max_offset [07:00] */
 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_MASK                0x00ff
 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_ALIGN               0
 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_BITS                8
 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_SHIFT               0
 
 
 /****************************************************************************
  * Digital6 :: link_timer_offset2
  */
 /* Digital6 :: link_timer_offset2 :: link_up_offset [15:08] */
 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_MASK            0xff00
 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_ALIGN           0
 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_BITS            8
 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_SHIFT           8
 
 /* Digital6 :: link_timer_offset2 :: link_down_offset [07:00] */
 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_MASK          0x00ff
 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_ALIGN         0
 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_BITS          8
 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_SHIFT         0
 
 
 /****************************************************************************
  * Digital6 :: link_timer_offset3
  */
 /* Digital6 :: link_timer_offset3 :: break_link_offset [15:08] */
 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_MASK         0xff00
 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_ALIGN        0
 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_BITS         8
 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_SHIFT        8
 
 /* Digital6 :: link_timer_offset3 :: np_link_offset [07:00] */
 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_MASK            0x00ff
 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_ALIGN           0
 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_BITS            8
 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_SHIFT           0
 
 
 /****************************************************************************
  * Digital6 :: oui_msb_field
  */
 /* Digital6 :: oui_msb_field :: reserved0 [15:11] */
 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_MASK                      0xf800
 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_ALIGN                     0
 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_BITS                      5
 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_SHIFT                     11
 
 /* Digital6 :: oui_msb_field :: oui_msb_field [10:00] */
 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK                  0x07ff
 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN                 0
 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS                  11
 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT                 0
 
 
 /****************************************************************************
  * Digital6 :: oui_lsb_field
  */
 /* Digital6 :: oui_lsb_field :: reserved0 [15:11] */
 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_MASK                      0xf800
 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_ALIGN                     0
 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_BITS                      5
 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_SHIFT                     11
 
 /* Digital6 :: oui_lsb_field :: oui_lsb_field [10:00] */
 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK                  0x07ff
 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN                 0
 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS                  11
 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT                 0
 
 
 /****************************************************************************
  * Digital6 :: bam_field
  */
 /* Digital6 :: bam_field :: reserved0 [15:11] */
 #define DIGITAL6_BAM_FIELD_RESERVED0_MASK                          0xf800
 #define DIGITAL6_BAM_FIELD_RESERVED0_ALIGN                         0
 #define DIGITAL6_BAM_FIELD_RESERVED0_BITS                          5
 #define DIGITAL6_BAM_FIELD_RESERVED0_SHIFT                         11
 
 /* Digital6 :: bam_field :: oui_1_0 [10:09] */
 #define DIGITAL6_BAM_FIELD_OUI_1_0_MASK                            0x0600
 #define DIGITAL6_BAM_FIELD_OUI_1_0_ALIGN                           0
 #define DIGITAL6_BAM_FIELD_OUI_1_0_BITS                            2
 #define DIGITAL6_BAM_FIELD_OUI_1_0_SHIFT                           9
 
 /* Digital6 :: bam_field :: bam_field [08:00] */
 #define DIGITAL6_BAM_FIELD_BAM_FIELD_MASK                          0x01ff
 #define DIGITAL6_BAM_FIELD_BAM_FIELD_ALIGN                         0
 #define DIGITAL6_BAM_FIELD_BAM_FIELD_BITS                          9
 #define DIGITAL6_BAM_FIELD_BAM_FIELD_SHIFT                         0
 
 
 /****************************************************************************
  * Digital6 :: ud_field
  */
 /* Digital6 :: ud_field :: reserved0 [15:11] */
 #define DIGITAL6_UD_FIELD_RESERVED0_MASK                           0xf800
 #define DIGITAL6_UD_FIELD_RESERVED0_ALIGN                          0
 #define DIGITAL6_UD_FIELD_RESERVED0_BITS                           5
 #define DIGITAL6_UD_FIELD_RESERVED0_SHIFT                          11
 
 /* Digital6 :: ud_field :: ud_reserved [10:06] */
 #define DIGITAL6_UD_FIELD_UD_RESERVED_MASK                         0x07c0
 #define DIGITAL6_UD_FIELD_UD_RESERVED_ALIGN                        0
 #define DIGITAL6_UD_FIELD_UD_RESERVED_BITS                         5
 #define DIGITAL6_UD_FIELD_UD_RESERVED_SHIFT                        6
 
 /* Digital6 :: ud_field :: remote_BN_page [05:05] */
 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_MASK                      0x0020
 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_ALIGN                     0
 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_BITS                      1
 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_SHIFT                     5
 
 /* Digital6 :: ud_field :: inband_MDIO [04:04] */
 #define DIGITAL6_UD_FIELD_INBAND_MDIO_MASK                         0x0010
 #define DIGITAL6_UD_FIELD_INBAND_MDIO_ALIGN                        0
 #define DIGITAL6_UD_FIELD_INBAND_MDIO_BITS                         1
 #define DIGITAL6_UD_FIELD_INBAND_MDIO_SHIFT                        4
 
 /* Digital6 :: ud_field :: autoneg_MDIO [03:03] */
 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_MASK                        0x0008
 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_ALIGN                       0
 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_BITS                        1
 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_SHIFT                       3
 
 /* Digital6 :: ud_field :: remote_serdes_phy [02:02] */
 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_MASK                   0x0004
 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_ALIGN                  0
 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_BITS                   1
 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_SHIFT                  2
 
 /* Digital6 :: ud_field :: remote_cu_phy [01:01] */
 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_MASK                       0x0002
 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_ALIGN                      0
 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_BITS                       1
 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_SHIFT                      1
 
 /* Digital6 :: ud_field :: over1g [00:00] */
 #define DIGITAL6_UD_FIELD_OVER1G_MASK                              0x0001
 #define DIGITAL6_UD_FIELD_OVER1G_ALIGN                             0
 #define DIGITAL6_UD_FIELD_OVER1G_BITS                              1
 #define DIGITAL6_UD_FIELD_OVER1G_SHIFT                             0
 
 
 /****************************************************************************
  * Digital6 :: lp_oui_msb_field
  */
 /* Digital6 :: lp_oui_msb_field :: reserved0 [15:11] */
 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_MASK                   0xf800
 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_ALIGN                  0
 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_BITS                   5
 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_SHIFT                  11
 
 /* Digital6 :: lp_oui_msb_field :: oui_msb_field [10:00] */
 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK               0x07ff
 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN              0
 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS               11
 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT              0
 
 
 /****************************************************************************
  * Digital6 :: lp_oui_lsb_field
  */
 /* Digital6 :: lp_oui_lsb_field :: reserved0 [15:11] */
 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_MASK                   0xf800
 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_ALIGN                  0
 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_BITS                   5
 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_SHIFT                  11
 
 /* Digital6 :: lp_oui_lsb_field :: oui_lsb_field [10:00] */
 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK               0x07ff
 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN              0
 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS               11
 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT              0
 
 
 /****************************************************************************
  * Digital6 :: lp_bam_field
  */
 /* Digital6 :: lp_bam_field :: reserved0 [15:11] */
 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_MASK                       0xf800
 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_ALIGN                      0
 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_BITS                       5
 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_SHIFT                      11
 
 /* Digital6 :: lp_bam_field :: oui_1_0 [10:09] */
 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_MASK                         0x0600
 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_ALIGN                        0
 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_BITS                         2
 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_SHIFT                        9
 
 /* Digital6 :: lp_bam_field :: bam_field [08:00] */
 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_MASK                       0x01ff
 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_ALIGN                      0
 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_BITS                       9
 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_SHIFT                      0
 
 
 /****************************************************************************
  * Digital6 :: lp_ud_field
  */
 /* Digital6 :: lp_ud_field :: reserved0 [15:11] */
 #define DIGITAL6_LP_UD_FIELD_RESERVED0_MASK                        0xf800
 #define DIGITAL6_LP_UD_FIELD_RESERVED0_ALIGN                       0
 #define DIGITAL6_LP_UD_FIELD_RESERVED0_BITS                        5
 #define DIGITAL6_LP_UD_FIELD_RESERVED0_SHIFT                       11
 
 /* Digital6 :: lp_ud_field :: ud_reserved [10:06] */
 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_MASK                      0x07c0
 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_ALIGN                     0
 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_BITS                      5
 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_SHIFT                     6
 
 /* Digital6 :: lp_ud_field :: remote_BN_page [05:05] */
 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_MASK                   0x0020
 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_ALIGN                  0
 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_BITS                   1
 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_SHIFT                  5
 
 /* Digital6 :: lp_ud_field :: inband_MDIO [04:04] */
 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_MASK                      0x0010
 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_ALIGN                     0
 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_BITS                      1
 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_SHIFT                     4
 
 /* Digital6 :: lp_ud_field :: autoneg_MDIO [03:03] */
 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_MASK                     0x0008
 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_ALIGN                    0
 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_BITS                     1
 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_SHIFT                    3
 
 /* Digital6 :: lp_ud_field :: remote_serdes_phy [02:02] */
 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_MASK                0x0004
 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_ALIGN               0
 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_BITS                1
 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_SHIFT               2
 
 /* Digital6 :: lp_ud_field :: remote_cu_phy [01:01] */
 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_MASK                    0x0002
 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_ALIGN                   0
 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_BITS                    1
 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_SHIFT                   1
 
 /* Digital6 :: lp_ud_field :: over1g [00:00] */
 #define DIGITAL6_LP_UD_FIELD_OVER1G_MASK                           0x0001
 #define DIGITAL6_LP_UD_FIELD_OVER1G_ALIGN                          0
 #define DIGITAL6_LP_UD_FIELD_OVER1G_BITS                           1
 #define DIGITAL6_LP_UD_FIELD_OVER1G_SHIFT                          0
 
 
 /****************************************************************************
  * Digital6 :: UP4
  */
 /* Digital6 :: UP4 :: reserved0 [15:11] */
 #define DIGITAL6_UP4_RESERVED0_MASK                                0xf800
 #define DIGITAL6_UP4_RESERVED0_ALIGN                               0
 #define DIGITAL6_UP4_RESERVED0_BITS                                5
 #define DIGITAL6_UP4_RESERVED0_SHIFT                               11
 
 /* Digital6 :: UP4 :: last [10:10] */
 #define DIGITAL6_UP4_LAST_MASK                                     0x0400
 #define DIGITAL6_UP4_LAST_ALIGN                                    0
 #define DIGITAL6_UP4_LAST_BITS                                     1
 #define DIGITAL6_UP4_LAST_SHIFT                                    10
 
 /* Digital6 :: UP4 :: reserved1 [09:08] */
 #define DIGITAL6_UP4_RESERVED1_MASK                                0x0300
 #define DIGITAL6_UP4_RESERVED1_ALIGN                               0
 #define DIGITAL6_UP4_RESERVED1_BITS                                2
 #define DIGITAL6_UP4_RESERVED1_SHIFT                               8
 
 /* Digital6 :: UP4 :: dataRate_15p75G_dxgxs [07:07] */
 #define DIGITAL6_UP4_DATARATE_15P75G_DXGXS_MASK                    0x0080
 #define DIGITAL6_UP4_DATARATE_15P75G_DXGXS_ALIGN                   0
 #define DIGITAL6_UP4_DATARATE_15P75G_DXGXS_BITS                    1
 #define DIGITAL6_UP4_DATARATE_15P75G_DXGXS_SHIFT                   7
 
 /* Digital6 :: UP4 :: dataRate_20G_dxgxs [06:06] */
 #define DIGITAL6_UP4_DATARATE_20G_DXGXS_MASK                       0x0040
 #define DIGITAL6_UP4_DATARATE_20G_DXGXS_ALIGN                      0
 #define DIGITAL6_UP4_DATARATE_20G_DXGXS_BITS                       1
 #define DIGITAL6_UP4_DATARATE_20G_DXGXS_SHIFT                      6
 
 /* Digital6 :: UP4 :: dataRate_20Gh_dxgxs [05:05] */
 #define DIGITAL6_UP4_DATARATE_20GH_DXGXS_MASK                      0x0020
 #define DIGITAL6_UP4_DATARATE_20GH_DXGXS_ALIGN                     0
 #define DIGITAL6_UP4_DATARATE_20GH_DXGXS_BITS                      1
 #define DIGITAL6_UP4_DATARATE_20GH_DXGXS_SHIFT                     5
 
 /* Digital6 :: UP4 :: dataRate_12p7G_dxgxs [04:04] */
 #define DIGITAL6_UP4_DATARATE_12P7G_DXGXS_MASK                     0x0010
 #define DIGITAL6_UP4_DATARATE_12P7G_DXGXS_ALIGN                    0
 #define DIGITAL6_UP4_DATARATE_12P7G_DXGXS_BITS                     1
 #define DIGITAL6_UP4_DATARATE_12P7G_DXGXS_SHIFT                    4
 
 /* Digital6 :: UP4 :: dataRate_10p5G_dxgxs [03:03] */
 #define DIGITAL6_UP4_DATARATE_10P5G_DXGXS_MASK                     0x0008
 #define DIGITAL6_UP4_DATARATE_10P5G_DXGXS_ALIGN                    0
 #define DIGITAL6_UP4_DATARATE_10P5G_DXGXS_BITS                     1
 #define DIGITAL6_UP4_DATARATE_10P5G_DXGXS_SHIFT                    3
 
 /* Digital6 :: UP4 :: dataRate_10G_dxgxs [02:02] */
 #define DIGITAL6_UP4_DATARATE_10G_DXGXS_MASK                       0x0004
 #define DIGITAL6_UP4_DATARATE_10G_DXGXS_ALIGN                      0
 #define DIGITAL6_UP4_DATARATE_10G_DXGXS_BITS                       1
 #define DIGITAL6_UP4_DATARATE_10G_DXGXS_SHIFT                      2
 
 /* Digital6 :: UP4 :: dataRate_10Gh_dxgxs [01:01] */
 #define DIGITAL6_UP4_DATARATE_10GH_DXGXS_MASK                      0x0002
 #define DIGITAL6_UP4_DATARATE_10GH_DXGXS_ALIGN                     0
 #define DIGITAL6_UP4_DATARATE_10GH_DXGXS_BITS                      1
 #define DIGITAL6_UP4_DATARATE_10GH_DXGXS_SHIFT                     1
 
 /* Digital6 :: UP4 :: dataRate_20G [00:00] */
 #define DIGITAL6_UP4_DATARATE_20G_MASK                             0x0001
 #define DIGITAL6_UP4_DATARATE_20G_ALIGN                            0
 #define DIGITAL6_UP4_DATARATE_20G_BITS                             1
 #define DIGITAL6_UP4_DATARATE_20G_SHIFT                            0
 
 
 /****************************************************************************
  * Digital6 :: UP5
  */
 /* Digital6 :: UP5 :: reserved0 [15:11] */
 #define DIGITAL6_UP5_RESERVED0_MASK                                0xf800
 #define DIGITAL6_UP5_RESERVED0_ALIGN                               0
 #define DIGITAL6_UP5_RESERVED0_BITS                                5
 #define DIGITAL6_UP5_RESERVED0_SHIFT                               11
 
 /* Digital6 :: UP5 :: last [10:10] */
 #define DIGITAL6_UP5_LAST_MASK                                     0x0400
 #define DIGITAL6_UP5_LAST_ALIGN                                    0
 #define DIGITAL6_UP5_LAST_BITS                                     1
 #define DIGITAL6_UP5_LAST_SHIFT                                    10
 
 /* Digital6 :: UP5 :: reserved1 [09:00] */
 #define DIGITAL6_UP5_RESERVED1_MASK                                0x03ff
 #define DIGITAL6_UP5_RESERVED1_ALIGN                               0
 #define DIGITAL6_UP5_RESERVED1_BITS                                10
 #define DIGITAL6_UP5_RESERVED1_SHIFT                               0
 
 
 /****************************************************************************
  * Warpcore_USER_CL49_UserB0
  */
 /****************************************************************************
  * CL49_UserB0 :: Control1
  */
 /* CL49_UserB0 :: Control1 :: reserved_for_eco0 [15:05] */
 #define CL49_USERB0_CONTROL1_RESERVED_FOR_ECO0_MASK                0xffe0
 #define CL49_USERB0_CONTROL1_RESERVED_FOR_ECO0_ALIGN               0
 #define CL49_USERB0_CONTROL1_RESERVED_FOR_ECO0_BITS                11
 #define CL49_USERB0_CONTROL1_RESERVED_FOR_ECO0_SHIFT               5
 
 /* CL49_UserB0 :: Control1 :: cl49_txsm_init_lpi_cya [04:04] */
 #define CL49_USERB0_CONTROL1_CL49_TXSM_INIT_LPI_CYA_MASK           0x0010
 #define CL49_USERB0_CONTROL1_CL49_TXSM_INIT_LPI_CYA_ALIGN          0
 #define CL49_USERB0_CONTROL1_CL49_TXSM_INIT_LPI_CYA_BITS           1
 #define CL49_USERB0_CONTROL1_CL49_TXSM_INIT_LPI_CYA_SHIFT          4
 
 /* CL49_UserB0 :: Control1 :: scramblerControl [03:02] */
 #define CL49_USERB0_CONTROL1_SCRAMBLERCONTROL_MASK                 0x000c
 #define CL49_USERB0_CONTROL1_SCRAMBLERCONTROL_ALIGN                0
 #define CL49_USERB0_CONTROL1_SCRAMBLERCONTROL_BITS                 2
 #define CL49_USERB0_CONTROL1_SCRAMBLERCONTROL_SHIFT                2
 
 /* CL49_UserB0 :: Control1 :: tfifo_sbitclr [01:01] */
 #define CL49_USERB0_CONTROL1_TFIFO_SBITCLR_MASK                    0x0002
 #define CL49_USERB0_CONTROL1_TFIFO_SBITCLR_ALIGN                   0
 #define CL49_USERB0_CONTROL1_TFIFO_SBITCLR_BITS                    1
 #define CL49_USERB0_CONTROL1_TFIFO_SBITCLR_SHIFT                   1
 
 /* CL49_UserB0 :: Control1 :: tfifo_afrst_en [00:00] */
 #define CL49_USERB0_CONTROL1_TFIFO_AFRST_EN_MASK                   0x0001
 #define CL49_USERB0_CONTROL1_TFIFO_AFRST_EN_ALIGN                  0
 #define CL49_USERB0_CONTROL1_TFIFO_AFRST_EN_BITS                   1
 #define CL49_USERB0_CONTROL1_TFIFO_AFRST_EN_SHIFT                  0
 
 
 /****************************************************************************
  * CL49_UserB0 :: Status1
  */
 /* CL49_UserB0 :: Status1 :: reserved_for_eco0 [15:03] */
 #define CL49_USERB0_STATUS1_RESERVED_FOR_ECO0_MASK                 0xfff8
 #define CL49_USERB0_STATUS1_RESERVED_FOR_ECO0_ALIGN                0
 #define CL49_USERB0_STATUS1_RESERVED_FOR_ECO0_BITS                 13
 #define CL49_USERB0_STATUS1_RESERVED_FOR_ECO0_SHIFT                3
 
 /* CL49_UserB0 :: Status1 :: ovflow [02:02] */
 #define CL49_USERB0_STATUS1_OVFLOW_MASK                            0x0004
 #define CL49_USERB0_STATUS1_OVFLOW_ALIGN                           0
 #define CL49_USERB0_STATUS1_OVFLOW_BITS                            1
 #define CL49_USERB0_STATUS1_OVFLOW_SHIFT                           2
 
 /* CL49_UserB0 :: Status1 :: unflow [01:01] */
 #define CL49_USERB0_STATUS1_UNFLOW_MASK                            0x0002
 #define CL49_USERB0_STATUS1_UNFLOW_ALIGN                           0
 #define CL49_USERB0_STATUS1_UNFLOW_BITS                            1
 #define CL49_USERB0_STATUS1_UNFLOW_SHIFT                           1
 
 /* CL49_UserB0 :: Status1 :: afrst [00:00] */
 #define CL49_USERB0_STATUS1_AFRST_MASK                             0x0001
 #define CL49_USERB0_STATUS1_AFRST_ALIGN                            0
 #define CL49_USERB0_STATUS1_AFRST_BITS                             1
 #define CL49_USERB0_STATUS1_AFRST_SHIFT                            0
 
 
 /****************************************************************************
  * CL49_UserB0 :: symboldetect
  */
 /* CL49_UserB0 :: symboldetect :: reserved_for_eco0 [15:09] */
 #define CL49_USERB0_SYMBOLDETECT_RESERVED_FOR_ECO0_MASK            0xfe00
 #define CL49_USERB0_SYMBOLDETECT_RESERVED_FOR_ECO0_ALIGN           0
 #define CL49_USERB0_SYMBOLDETECT_RESERVED_FOR_ECO0_BITS            7
 #define CL49_USERB0_SYMBOLDETECT_RESERVED_FOR_ECO0_SHIFT           9
 
 /* CL49_UserB0 :: symboldetect :: symboldetect [08:00] */
 #define CL49_USERB0_SYMBOLDETECT_SYMBOLDETECT_MASK                 0x01ff
 #define CL49_USERB0_SYMBOLDETECT_SYMBOLDETECT_ALIGN                0
 #define CL49_USERB0_SYMBOLDETECT_SYMBOLDETECT_BITS                 9
 #define CL49_USERB0_SYMBOLDETECT_SYMBOLDETECT_SHIFT                0
 
 
 /****************************************************************************
  * CL49_UserB0 :: symbolinsert
  */
 /* CL49_UserB0 :: symbolinsert :: reserved_for_eco0 [15:09] */
 #define CL49_USERB0_SYMBOLINSERT_RESERVED_FOR_ECO0_MASK            0xfe00
 #define CL49_USERB0_SYMBOLINSERT_RESERVED_FOR_ECO0_ALIGN           0
 #define CL49_USERB0_SYMBOLINSERT_RESERVED_FOR_ECO0_BITS            7
 #define CL49_USERB0_SYMBOLINSERT_RESERVED_FOR_ECO0_SHIFT           9
 
 /* CL49_UserB0 :: symbolinsert :: symbolinsert [08:00] */
 #define CL49_USERB0_SYMBOLINSERT_SYMBOLINSERT_MASK                 0x01ff
 #define CL49_USERB0_SYMBOLINSERT_SYMBOLINSERT_ALIGN                0
 #define CL49_USERB0_SYMBOLINSERT_SYMBOLINSERT_BITS                 9
 #define CL49_USERB0_SYMBOLINSERT_SYMBOLINSERT_SHIFT                0
 
 
 /****************************************************************************
  * CL49_UserB0 :: Control2
  */
 /* CL49_UserB0 :: Control2 :: reserved_for_eco0 [15:04] */
 #define CL49_USERB0_CONTROL2_RESERVED_FOR_ECO0_MASK                0xfff0
 #define CL49_USERB0_CONTROL2_RESERVED_FOR_ECO0_ALIGN               0
 #define CL49_USERB0_CONTROL2_RESERVED_FOR_ECO0_BITS                12
 #define CL49_USERB0_CONTROL2_RESERVED_FOR_ECO0_SHIFT               4
 
 /* CL49_UserB0 :: Control2 :: sqwbitcount_SM [03:00] */
 #define CL49_USERB0_CONTROL2_SQWBITCOUNT_SM_MASK                   0x000f
 #define CL49_USERB0_CONTROL2_SQWBITCOUNT_SM_ALIGN                  0
 #define CL49_USERB0_CONTROL2_SQWBITCOUNT_SM_BITS                   4
 #define CL49_USERB0_CONTROL2_SQWBITCOUNT_SM_SHIFT                  0
 
 
 /****************************************************************************
  * CL49_UserB0 :: txsm_status
  */
 /* CL49_UserB0 :: txsm_status :: t_type [15:10] */
 #define CL49_USERB0_TXSM_STATUS_T_TYPE_MASK                        0xfc00
 #define CL49_USERB0_TXSM_STATUS_T_TYPE_ALIGN                       0
 #define CL49_USERB0_TXSM_STATUS_T_TYPE_BITS                        6
 #define CL49_USERB0_TXSM_STATUS_T_TYPE_SHIFT                       10
 
 /* CL49_UserB0 :: txsm_status :: reserved_for_eco0 [09:09] */
 #define CL49_USERB0_TXSM_STATUS_RESERVED_FOR_ECO0_MASK             0x0200
 #define CL49_USERB0_TXSM_STATUS_RESERVED_FOR_ECO0_ALIGN            0
 #define CL49_USERB0_TXSM_STATUS_RESERVED_FOR_ECO0_BITS             1
 #define CL49_USERB0_TXSM_STATUS_RESERVED_FOR_ECO0_SHIFT            9
 
 /* CL49_UserB0 :: txsm_status :: ltxsm_state [08:03] */
 #define CL49_USERB0_TXSM_STATUS_LTXSM_STATE_MASK                   0x01f8
 #define CL49_USERB0_TXSM_STATUS_LTXSM_STATE_ALIGN                  0
 #define CL49_USERB0_TXSM_STATUS_LTXSM_STATE_BITS                   6
 #define CL49_USERB0_TXSM_STATUS_LTXSM_STATE_SHIFT                  3
 
 /* CL49_UserB0 :: txsm_status :: txsm_state [02:00] */
 #define CL49_USERB0_TXSM_STATUS_TXSM_STATE_MASK                    0x0007
 #define CL49_USERB0_TXSM_STATUS_TXSM_STATE_ALIGN                   0
 #define CL49_USERB0_TXSM_STATUS_TXSM_STATE_BITS                    3
 #define CL49_USERB0_TXSM_STATUS_TXSM_STATE_SHIFT                   0
 
 
 /****************************************************************************
  * CL49_UserB0 :: rxsm_status
  */
 /* CL49_UserB0 :: rxsm_status :: r_type [15:10] */
 #define CL49_USERB0_RXSM_STATUS_R_TYPE_MASK                        0xfc00
 #define CL49_USERB0_RXSM_STATUS_R_TYPE_ALIGN                       0
 #define CL49_USERB0_RXSM_STATUS_R_TYPE_BITS                        6
 #define CL49_USERB0_RXSM_STATUS_R_TYPE_SHIFT                       10
 
 /* CL49_UserB0 :: rxsm_status :: reserved0 [09:09] */
 #define CL49_USERB0_RXSM_STATUS_RESERVED0_MASK                     0x0200
 #define CL49_USERB0_RXSM_STATUS_RESERVED0_ALIGN                    0
 #define CL49_USERB0_RXSM_STATUS_RESERVED0_BITS                     1
 #define CL49_USERB0_RXSM_STATUS_RESERVED0_SHIFT                    9
 
 /* CL49_UserB0 :: rxsm_status :: lrxsm_state [08:03] */
 #define CL49_USERB0_RXSM_STATUS_LRXSM_STATE_MASK                   0x01f8
 #define CL49_USERB0_RXSM_STATUS_LRXSM_STATE_ALIGN                  0
 #define CL49_USERB0_RXSM_STATUS_LRXSM_STATE_BITS                   6
 #define CL49_USERB0_RXSM_STATUS_LRXSM_STATE_SHIFT                  3
 
 /* CL49_UserB0 :: rxsm_status :: rxsm_state [02:00] */
 #define CL49_USERB0_RXSM_STATUS_RXSM_STATE_MASK                    0x0007
 #define CL49_USERB0_RXSM_STATUS_RXSM_STATE_ALIGN                   0
 #define CL49_USERB0_RXSM_STATUS_RXSM_STATE_BITS                    3
 #define CL49_USERB0_RXSM_STATUS_RXSM_STATE_SHIFT                   0
 
 
 /****************************************************************************
  * CL49_UserB0 :: lsm_status
  */
 /* CL49_UserB0 :: lsm_status :: block_lock [15:15] */
 #define CL49_USERB0_LSM_STATUS_BLOCK_LOCK_MASK                     0x8000
 #define CL49_USERB0_LSM_STATUS_BLOCK_LOCK_ALIGN                    0
 #define CL49_USERB0_LSM_STATUS_BLOCK_LOCK_BITS                     1
 #define CL49_USERB0_LSM_STATUS_BLOCK_LOCK_SHIFT                    15
 
 /* CL49_UserB0 :: lsm_status :: signal_ok [14:14] */
 #define CL49_USERB0_LSM_STATUS_SIGNAL_OK_MASK                      0x4000
 #define CL49_USERB0_LSM_STATUS_SIGNAL_OK_ALIGN                     0
 #define CL49_USERB0_LSM_STATUS_SIGNAL_OK_BITS                      1
 #define CL49_USERB0_LSM_STATUS_SIGNAL_OK_SHIFT                     14
 
 /* CL49_UserB0 :: lsm_status :: reserved0 [13:13] */
 #define CL49_USERB0_LSM_STATUS_RESERVED0_MASK                      0x2000
 #define CL49_USERB0_LSM_STATUS_RESERVED0_ALIGN                     0
 #define CL49_USERB0_LSM_STATUS_RESERVED0_BITS                      1
 #define CL49_USERB0_LSM_STATUS_RESERVED0_SHIFT                     13
 
 /* CL49_UserB0 :: lsm_status :: llsm_state [12:04] */
 #define CL49_USERB0_LSM_STATUS_LLSM_STATE_MASK                     0x1ff0
 #define CL49_USERB0_LSM_STATUS_LLSM_STATE_ALIGN                    0
 #define CL49_USERB0_LSM_STATUS_LLSM_STATE_BITS                     9
 #define CL49_USERB0_LSM_STATUS_LLSM_STATE_SHIFT                    4
 
 /* CL49_UserB0 :: lsm_status :: lsm_state [03:00] */
 #define CL49_USERB0_LSM_STATUS_LSM_STATE_MASK                      0x000f
 #define CL49_USERB0_LSM_STATUS_LSM_STATE_ALIGN                     0
 #define CL49_USERB0_LSM_STATUS_LSM_STATE_BITS                      4
 #define CL49_USERB0_LSM_STATUS_LSM_STATE_SHIFT                     0
 
 
 /****************************************************************************
  * CL49_UserB0 :: Control
  */
 /* CL49_UserB0 :: Control :: reserved0 [15:10] */
 #define CL49_USERB0_CONTROL_RESERVED0_MASK                         0xfc00
 #define CL49_USERB0_CONTROL_RESERVED0_ALIGN                        0
 #define CL49_USERB0_CONTROL_RESERVED0_BITS                         6
 #define CL49_USERB0_CONTROL_RESERVED0_SHIFT                        10
 
 /* CL49_UserB0 :: Control :: r2_ckgate_en_ovr_value [09:09] */
 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_VALUE_MASK            0x0200
 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_VALUE_ALIGN           0
 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_VALUE_BITS            1
 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_VALUE_SHIFT           9
 
 /* CL49_UserB0 :: Control :: r2_ckgate_en_ovr_ctrl [08:08] */
 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_CTRL_MASK             0x0100
 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_CTRL_ALIGN            0
 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_CTRL_BITS             1
 #define CL49_USERB0_CONTROL_R2_CKGATE_EN_OVR_CTRL_SHIFT            8
 
 /* CL49_UserB0 :: Control :: cl82_ckgate_en_ovr_value [07:07] */
 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_VALUE_MASK          0x0080
 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_VALUE_ALIGN         0
 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_VALUE_BITS          1
 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_VALUE_SHIFT         7
 
 /* CL49_UserB0 :: Control :: cl82_ckgate_en_ovr_ctrl [06:06] */
 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_CTRL_MASK           0x0040
 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_CTRL_ALIGN          0
 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_CTRL_BITS           1
 #define CL49_USERB0_CONTROL_CL82_CKGATE_EN_OVR_CTRL_SHIFT          6
 
 /* CL49_UserB0 :: Control :: fast_lock_cya [05:05] */
 #define CL49_USERB0_CONTROL_FAST_LOCK_CYA_MASK                     0x0020
 #define CL49_USERB0_CONTROL_FAST_LOCK_CYA_ALIGN                    0
 #define CL49_USERB0_CONTROL_FAST_LOCK_CYA_BITS                     1
 #define CL49_USERB0_CONTROL_FAST_LOCK_CYA_SHIFT                    5
 
 /* CL49_UserB0 :: Control :: prbs9rx_en [04:04] */
 #define CL49_USERB0_CONTROL_PRBS9RX_EN_MASK                        0x0010
 #define CL49_USERB0_CONTROL_PRBS9RX_EN_ALIGN                       0
 #define CL49_USERB0_CONTROL_PRBS9RX_EN_BITS                        1
 #define CL49_USERB0_CONTROL_PRBS9RX_EN_SHIFT                       4
 
 /* CL49_UserB0 :: Control :: descramblerControl [03:02] */
 #define CL49_USERB0_CONTROL_DESCRAMBLERCONTROL_MASK                0x000c
 #define CL49_USERB0_CONTROL_DESCRAMBLERCONTROL_ALIGN               0
 #define CL49_USERB0_CONTROL_DESCRAMBLERCONTROL_BITS                2
 #define CL49_USERB0_CONTROL_DESCRAMBLERCONTROL_SHIFT               2
 
 /* CL49_UserB0 :: Control :: rfifo_sbitclr [01:01] */
 #define CL49_USERB0_CONTROL_RFIFO_SBITCLR_MASK                     0x0002
 #define CL49_USERB0_CONTROL_RFIFO_SBITCLR_ALIGN                    0
 #define CL49_USERB0_CONTROL_RFIFO_SBITCLR_BITS                     1
 #define CL49_USERB0_CONTROL_RFIFO_SBITCLR_SHIFT                    1
 
 /* CL49_UserB0 :: Control :: rfifo_afrst_en [00:00] */
 #define CL49_USERB0_CONTROL_RFIFO_AFRST_EN_MASK                    0x0001
 #define CL49_USERB0_CONTROL_RFIFO_AFRST_EN_ALIGN                   0
 #define CL49_USERB0_CONTROL_RFIFO_AFRST_EN_BITS                    1
 #define CL49_USERB0_CONTROL_RFIFO_AFRST_EN_SHIFT                   0
 
 
 /****************************************************************************
  * CL49_UserB0 :: Status
  */
 /* CL49_UserB0 :: Status :: reserved0 [15:05] */
 #define CL49_USERB0_STATUS_RESERVED0_MASK                          0xffe0
 #define CL49_USERB0_STATUS_RESERVED0_ALIGN                         0
 #define CL49_USERB0_STATUS_RESERVED0_BITS                          11
 #define CL49_USERB0_STATUS_RESERVED0_SHIFT                         5
 
 /* CL49_UserB0 :: Status :: pseudo_lock [04:04] */
 #define CL49_USERB0_STATUS_PSEUDO_LOCK_MASK                        0x0010
 #define CL49_USERB0_STATUS_PSEUDO_LOCK_ALIGN                       0
 #define CL49_USERB0_STATUS_PSEUDO_LOCK_BITS                        1
 #define CL49_USERB0_STATUS_PSEUDO_LOCK_SHIFT                       4
 
 /* CL49_UserB0 :: Status :: prbs_lock [03:03] */
 #define CL49_USERB0_STATUS_PRBS_LOCK_MASK                          0x0008
 #define CL49_USERB0_STATUS_PRBS_LOCK_ALIGN                         0
 #define CL49_USERB0_STATUS_PRBS_LOCK_BITS                          1
 #define CL49_USERB0_STATUS_PRBS_LOCK_SHIFT                         3
 
 /* CL49_UserB0 :: Status :: unflow [02:02] */
 #define CL49_USERB0_STATUS_UNFLOW_MASK                             0x0004
 #define CL49_USERB0_STATUS_UNFLOW_ALIGN                            0
 #define CL49_USERB0_STATUS_UNFLOW_BITS                             1
 #define CL49_USERB0_STATUS_UNFLOW_SHIFT                            2
 
 /* CL49_UserB0 :: Status :: ovflow [01:01] */
 #define CL49_USERB0_STATUS_OVFLOW_MASK                             0x0002
 #define CL49_USERB0_STATUS_OVFLOW_ALIGN                            0
 #define CL49_USERB0_STATUS_OVFLOW_BITS                             1
 #define CL49_USERB0_STATUS_OVFLOW_SHIFT                            1
 
 /* CL49_UserB0 :: Status :: afrst [00:00] */
 #define CL49_USERB0_STATUS_AFRST_MASK                              0x0001
 #define CL49_USERB0_STATUS_AFRST_ALIGN                             0
 #define CL49_USERB0_STATUS_AFRST_BITS                              1
 #define CL49_USERB0_STATUS_AFRST_SHIFT                             0
 
 
 /****************************************************************************
  * CL49_UserB0 :: shcounter
  */
 /* CL49_UserB0 :: shcounter :: valid_sh_cnt [15:08] */
 #define CL49_USERB0_SHCOUNTER_VALID_SH_CNT_MASK                    0xff00
 #define CL49_USERB0_SHCOUNTER_VALID_SH_CNT_ALIGN                   0
 #define CL49_USERB0_SHCOUNTER_VALID_SH_CNT_BITS                    8
 #define CL49_USERB0_SHCOUNTER_VALID_SH_CNT_SHIFT                   8
 
 /* CL49_UserB0 :: shcounter :: invalid_sh_cnt [07:00] */
 #define CL49_USERB0_SHCOUNTER_INVALID_SH_CNT_MASK                  0x00ff
 #define CL49_USERB0_SHCOUNTER_INVALID_SH_CNT_ALIGN                 0
 #define CL49_USERB0_SHCOUNTER_INVALID_SH_CNT_BITS                  8
 #define CL49_USERB0_SHCOUNTER_INVALID_SH_CNT_SHIFT                 0
 
 
 /****************************************************************************
  * CL49_UserB0 :: timer125us
  */
 /* CL49_UserB0 :: timer125us :: timer125us [15:00] */
 #define CL49_USERB0_TIMER125US_TIMER125US_MASK                     0xffff
 #define CL49_USERB0_TIMER125US_TIMER125US_ALIGN                    0
 #define CL49_USERB0_TIMER125US_TIMER125US_BITS                     16
 #define CL49_USERB0_TIMER125US_TIMER125US_SHIFT                    0
 
 
 /****************************************************************************
  * CL49_UserB0 :: bercnt
  */
 /* CL49_UserB0 :: bercnt :: reserved0 [15:10] */
 #define CL49_USERB0_BERCNT_RESERVED0_MASK                          0xfc00
 #define CL49_USERB0_BERCNT_RESERVED0_ALIGN                         0
 #define CL49_USERB0_BERCNT_RESERVED0_BITS                          6
 #define CL49_USERB0_BERCNT_RESERVED0_SHIFT                         10
 
 /* CL49_UserB0 :: bercnt :: match_cnt [09:06] */
 #define CL49_USERB0_BERCNT_MATCH_CNT_MASK                          0x03c0
 #define CL49_USERB0_BERCNT_MATCH_CNT_ALIGN                         0
 #define CL49_USERB0_BERCNT_MATCH_CNT_BITS                          4
 #define CL49_USERB0_BERCNT_MATCH_CNT_SHIFT                         6
 
 /* CL49_UserB0 :: bercnt :: bercnt [05:00] */
 #define CL49_USERB0_BERCNT_BERCNT_MASK                             0x003f
 #define CL49_USERB0_BERCNT_BERCNT_ALIGN                            0
 #define CL49_USERB0_BERCNT_BERCNT_BITS                             6
 #define CL49_USERB0_BERCNT_BERCNT_SHIFT                            0
 
 
 /****************************************************************************
  * CL49_UserB0 :: bermon_status
  */
 /* CL49_UserB0 :: bermon_status :: reserved0 [15:14] */
 #define CL49_USERB0_BERMON_STATUS_RESERVED0_MASK                   0xc000
 #define CL49_USERB0_BERMON_STATUS_RESERVED0_ALIGN                  0
 #define CL49_USERB0_BERMON_STATUS_RESERVED0_BITS                   2
 #define CL49_USERB0_BERMON_STATUS_RESERVED0_SHIFT                  14
 
 /* CL49_UserB0 :: bermon_status :: hi_ber [13:13] */
 #define CL49_USERB0_BERMON_STATUS_HI_BER_MASK                      0x2000
 #define CL49_USERB0_BERMON_STATUS_HI_BER_ALIGN                     0
 #define CL49_USERB0_BERMON_STATUS_HI_BER_BITS                      1
 #define CL49_USERB0_BERMON_STATUS_HI_BER_SHIFT                     13
 
 /* CL49_UserB0 :: bermon_status :: t125us_done [12:12] */
 #define CL49_USERB0_BERMON_STATUS_T125US_DONE_MASK                 0x1000
 #define CL49_USERB0_BERMON_STATUS_T125US_DONE_ALIGN                0
 #define CL49_USERB0_BERMON_STATUS_T125US_DONE_BITS                 1
 #define CL49_USERB0_BERMON_STATUS_T125US_DONE_SHIFT                12
 
 /* CL49_UserB0 :: bermon_status :: lbermon_state [11:06] */
 #define CL49_USERB0_BERMON_STATUS_LBERMON_STATE_MASK               0x0fc0
 #define CL49_USERB0_BERMON_STATUS_LBERMON_STATE_ALIGN              0
 #define CL49_USERB0_BERMON_STATUS_LBERMON_STATE_BITS               6
 #define CL49_USERB0_BERMON_STATUS_LBERMON_STATE_SHIFT              6
 
 /* CL49_UserB0 :: bermon_status :: bermon_state [05:00] */
 #define CL49_USERB0_BERMON_STATUS_BERMON_STATE_MASK                0x003f
 #define CL49_USERB0_BERMON_STATUS_BERMON_STATE_ALIGN               0
 #define CL49_USERB0_BERMON_STATUS_BERMON_STATE_BITS                6
 #define CL49_USERB0_BERMON_STATUS_BERMON_STATE_SHIFT               0
 
 
 /****************************************************************************
  * CL49_UserB0 :: tstcnt1
  */
 /* CL49_UserB0 :: tstcnt1 :: sync_cnt [15:08] */
 #define CL49_USERB0_TSTCNT1_SYNC_CNT_MASK                          0xff00
 #define CL49_USERB0_TSTCNT1_SYNC_CNT_ALIGN                         0
 #define CL49_USERB0_TSTCNT1_SYNC_CNT_BITS                          8
 #define CL49_USERB0_TSTCNT1_SYNC_CNT_SHIFT                         8
 
 /* CL49_UserB0 :: tstcnt1 :: block_cnt [07:00] */
 #define CL49_USERB0_TSTCNT1_BLOCK_CNT_MASK                         0x00ff
 #define CL49_USERB0_TSTCNT1_BLOCK_CNT_ALIGN                        0
 #define CL49_USERB0_TSTCNT1_BLOCK_CNT_BITS                         8
 #define CL49_USERB0_TSTCNT1_BLOCK_CNT_SHIFT                        0
 
 
 /****************************************************************************
  * Warpcore_USER_CL73_UserB0
  */
 /****************************************************************************
  * CL73_UserB0 :: CL73_UCtrl1
  */
 /* CL73_UserB0 :: CL73_UCtrl1 :: reserved0 [15:13] */
 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_MASK                     0xe000
 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_ALIGN                    0
 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_BITS                     3
 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_SHIFT                    13
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_lossOfSyncFail_en [12:12] */
 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_MASK        0x1000
 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_ALIGN       0
 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_BITS        1
 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_SHIFT       12
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_parDet_dis [11:11] */
 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_MASK               0x0800
 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_ALIGN              0
 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_BITS               1
 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_SHIFT              11
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_allowCl37AN [10:10] */
 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_MASK              0x0400
 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_ALIGN             0
 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_BITS              1
 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_SHIFT             10
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: longParDetTimer_dis [09:09] */
 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_MASK           0x0200
 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_ALIGN          0
 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_BITS           1
 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_SHIFT          9
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimer_dis [08:08] */
 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_MASK             0x0100
 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_ALIGN            0
 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_BITS             1
 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_SHIFT            8
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimerQual_en [07:07] */
 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_MASK          0x0080
 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_ALIGN         0
 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_BITS          1
 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_SHIFT         7
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_over [06:06] */
 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_MASK         0x0040
 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_ALIGN        0
 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_BITS         1
 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_SHIFT        6
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_val [05:05] */
 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_MASK          0x0020
 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_ALIGN         0
 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_BITS          1
 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_SHIFT         5
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart_wo_link_fail [04:04] */
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_MASK 0x0010
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_ALIGN 0
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_BITS 1
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_SHIFT 4
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart [03:03] */
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_MASK         0x0008
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_ALIGN        0
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_BITS         1
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_SHIFT        3
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl37_restart [02:02] */
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_MASK         0x0004
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_ALIGN        0
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_BITS         1
 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_SHIFT        2
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: CL73_Ustat1_muxsel [01:01] */
 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_MASK            0x0002
 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_ALIGN           0
 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_BITS            1
 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_SHIFT           1
 
 /* CL73_UserB0 :: CL73_UCtrl1 :: force_cl73_tx_omux_en [00:00] */
 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_MASK         0x0001
 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_ALIGN        0
 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_BITS         1
 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_SHIFT        0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_Ustat1
  */
 /* CL73_UserB0 :: CL73_Ustat1 :: reserved0 [15:10] */
 #define CL73_USERB0_CL73_USTAT1_RESERVED0_MASK                     0xfc00
 #define CL73_USERB0_CL73_USTAT1_RESERVED0_ALIGN                    0
 #define CL73_USERB0_CL73_USTAT1_RESERVED0_BITS                     6
 #define CL73_USERB0_CL73_USTAT1_RESERVED0_SHIFT                    10
 
 /* CL73_UserB0 :: CL73_Ustat1 :: arb_fsm [09:00] */
 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_MASK                       0x03ff
 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_ALIGN                      0
 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_BITS                       10
 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_SHIFT                      0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_BAMCtrl1
  */
 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamEn [15:15] */
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_MASK                  0x8000
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_ALIGN                 0
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_BITS                  1
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_SHIFT                 15
 
 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_station_mngr_en [14:14] */
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_MASK    0x4000
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_ALIGN   0
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_BITS    1
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_SHIFT   14
 
 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamNP_after_bp_en [13:13] */
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_MASK      0x2000
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_ALIGN     0
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_BITS      1
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_SHIFT     13
 
 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_en [12:12] */
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_MASK   0x1000
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_ALIGN  0
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_BITS   1
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_SHIFT  12
 
 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_step [11:11] */
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_MASK 0x0800
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_ALIGN 0
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_BITS 1
 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_SHIFT 11
 
 /* CL73_UserB0 :: CL73_BAMCtrl1 :: reserved0 [10:10] */
 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_MASK                   0x0400
 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_ALIGN                  0
 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_BITS                   1
 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_SHIFT                  10
 
 /* CL73_UserB0 :: CL73_BAMCtrl1 :: UD_code_field [09:00] */
 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_MASK               0x03ff
 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_ALIGN              0
 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_BITS               10
 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_SHIFT              0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_BAMCtrl2
  */
 /* CL73_UserB0 :: CL73_BAMCtrl2 :: UD_code_field [15:00] */
 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_MASK               0xffff
 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_ALIGN              0
 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_BITS               16
 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_SHIFT              0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_BAMCtrl3
  */
 /* CL73_UserB0 :: CL73_BAMCtrl3 :: UD_code_field [15:00] */
 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_MASK               0xffff
 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_ALIGN              0
 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_BITS               16
 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_SHIFT              0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_BAMStat1
  */
 /* CL73_UserB0 :: CL73_BAMStat1 :: reserved0 [15:10] */
 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_MASK                   0xfc00
 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_ALIGN                  0
 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_BITS                   6
 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_SHIFT                  10
 
 /* CL73_UserB0 :: CL73_BAMStat1 :: LP_UD_code_field [09:00] */
 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_MASK            0x03ff
 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_ALIGN           0
 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_BITS            10
 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_SHIFT           0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_BAMStat2
  */
 /* CL73_UserB0 :: CL73_BAMStat2 :: LP_UD_code_field [15:00] */
 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_MASK            0xffff
 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_ALIGN           0
 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_BITS            16
 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_SHIFT           0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_BAMStat3
  */
 /* CL73_UserB0 :: CL73_BAMStat3 :: LP_UD_code_field [15:00] */
 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_MASK            0xffff
 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_ALIGN           0
 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_BITS            16
 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_SHIFT           0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_UCtrl2
  */
 /* CL73_UserB0 :: CL73_UCtrl2 :: reserved0 [15:12] */
 #define CL73_USERB0_CL73_UCTRL2_RESERVED0_MASK                     0xf000
 #define CL73_USERB0_CL73_UCTRL2_RESERVED0_ALIGN                    0
 #define CL73_USERB0_CL73_UCTRL2_RESERVED0_BITS                     4
 #define CL73_USERB0_CL73_UCTRL2_RESERVED0_SHIFT                    12
 
 /* CL73_UserB0 :: CL73_UCtrl2 :: useLink [11:11] */
 #define CL73_USERB0_CL73_UCTRL2_USELINK_MASK                       0x0800
 #define CL73_USERB0_CL73_UCTRL2_USELINK_ALIGN                      0
 #define CL73_USERB0_CL73_UCTRL2_USELINK_BITS                       1
 #define CL73_USERB0_CL73_UCTRL2_USELINK_SHIFT                      11
 
 /* CL73_UserB0 :: CL73_UCtrl2 :: rx_dme_status_sel [10:09] */
 #define CL73_USERB0_CL73_UCTRL2_RX_DME_STATUS_SEL_MASK             0x0600
 #define CL73_USERB0_CL73_UCTRL2_RX_DME_STATUS_SEL_ALIGN            0
 #define CL73_USERB0_CL73_UCTRL2_RX_DME_STATUS_SEL_BITS             2
 #define CL73_USERB0_CL73_UCTRL2_RX_DME_STATUS_SEL_SHIFT            9
 
 /* CL73_UserB0 :: CL73_UCtrl2 :: cl73_suppress_mr_page_rx_dis [08:08] */
 #define CL73_USERB0_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_MASK  0x0100
 #define CL73_USERB0_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_ALIGN 0
 #define CL73_USERB0_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_BITS  1
 #define CL73_USERB0_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_SHIFT 8
 
 /* CL73_UserB0 :: CL73_UCtrl2 :: cl73_record_2NP_after_BP_en [07:07] */
 #define CL73_USERB0_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_MASK   0x0080
 #define CL73_USERB0_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_ALIGN  0
 #define CL73_USERB0_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_BITS   1
 #define CL73_USERB0_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_SHIFT  7
 
 /* CL73_UserB0 :: CL73_UCtrl2 :: cl73_BAMStat123_sel [06:04] */
 #define CL73_USERB0_CL73_UCTRL2_CL73_BAMSTAT123_SEL_MASK           0x0070
 #define CL73_USERB0_CL73_UCTRL2_CL73_BAMSTAT123_SEL_ALIGN          0
 #define CL73_USERB0_CL73_UCTRL2_CL73_BAMSTAT123_SEL_BITS           3
 #define CL73_USERB0_CL73_UCTRL2_CL73_BAMSTAT123_SEL_SHIFT          4
 
 /* CL73_UserB0 :: CL73_UCtrl2 :: sigdet_timer_dis [03:03] */
 #define CL73_USERB0_CL73_UCTRL2_SIGDET_TIMER_DIS_MASK              0x0008
 #define CL73_USERB0_CL73_UCTRL2_SIGDET_TIMER_DIS_ALIGN             0
 #define CL73_USERB0_CL73_UCTRL2_SIGDET_TIMER_DIS_BITS              1
 #define CL73_USERB0_CL73_UCTRL2_SIGDET_TIMER_DIS_SHIFT             3
 
 /* CL73_UserB0 :: CL73_UCtrl2 :: an_good_check_bam37_dis [02:02] */
 #define CL73_USERB0_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_MASK       0x0004
 #define CL73_USERB0_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_ALIGN      0
 #define CL73_USERB0_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_BITS       1
 #define CL73_USERB0_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_SHIFT      2
 
 /* CL73_UserB0 :: CL73_UCtrl2 :: config_match_dis [01:01] */
 #define CL73_USERB0_CL73_UCTRL2_CONFIG_MATCH_DIS_MASK              0x0002
 #define CL73_USERB0_CL73_UCTRL2_CONFIG_MATCH_DIS_ALIGN             0
 #define CL73_USERB0_CL73_UCTRL2_CONFIG_MATCH_DIS_BITS              1
 #define CL73_USERB0_CL73_UCTRL2_CONFIG_MATCH_DIS_SHIFT             1
 
 /* CL73_UserB0 :: CL73_UCtrl2 :: hold_lp_ability [00:00] */
 #define CL73_USERB0_CL73_UCTRL2_HOLD_LP_ABILITY_MASK               0x0001
 #define CL73_USERB0_CL73_UCTRL2_HOLD_LP_ABILITY_ALIGN              0
 #define CL73_USERB0_CL73_UCTRL2_HOLD_LP_ABILITY_BITS               1
 #define CL73_USERB0_CL73_UCTRL2_HOLD_LP_ABILITY_SHIFT              0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_UCtrl3
  */
 /* CL73_UserB0 :: CL73_UCtrl3 :: anerr_max [15:00] */
 #define CL73_USERB0_CL73_UCTRL3_ANERR_MAX_MASK                     0xffff
 #define CL73_USERB0_CL73_UCTRL3_ANERR_MAX_ALIGN                    0
 #define CL73_USERB0_CL73_UCTRL3_ANERR_MAX_BITS                     16
 #define CL73_USERB0_CL73_UCTRL3_ANERR_MAX_SHIFT                    0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_UCtrl4
  */
 /* CL73_UserB0 :: CL73_UCtrl4 :: reserved0 [15:09] */
 #define CL73_USERB0_CL73_UCTRL4_RESERVED0_MASK                     0xfe00
 #define CL73_USERB0_CL73_UCTRL4_RESERVED0_ALIGN                    0
 #define CL73_USERB0_CL73_UCTRL4_RESERVED0_BITS                     7
 #define CL73_USERB0_CL73_UCTRL4_RESERVED0_SHIFT                    9
 
 /* CL73_UserB0 :: CL73_UCtrl4 :: anerr_timer_mask [08:03] */
 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_MASK_MASK              0x01f8
 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_MASK_ALIGN             0
 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_MASK_BITS              6
 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_MASK_SHIFT             3
 
 /* CL73_UserB0 :: CL73_UCtrl4 :: disable_sigdet_timer [02:02] */
 #define CL73_USERB0_CL73_UCTRL4_DISABLE_SIGDET_TIMER_MASK          0x0004
 #define CL73_USERB0_CL73_UCTRL4_DISABLE_SIGDET_TIMER_ALIGN         0
 #define CL73_USERB0_CL73_UCTRL4_DISABLE_SIGDET_TIMER_BITS          1
 #define CL73_USERB0_CL73_UCTRL4_DISABLE_SIGDET_TIMER_SHIFT         2
 
 /* CL73_UserB0 :: CL73_UCtrl4 :: cl73_anerr_status_sel [01:01] */
 #define CL73_USERB0_CL73_UCTRL4_CL73_ANERR_STATUS_SEL_MASK         0x0002
 #define CL73_USERB0_CL73_UCTRL4_CL73_ANERR_STATUS_SEL_ALIGN        0
 #define CL73_USERB0_CL73_UCTRL4_CL73_ANERR_STATUS_SEL_BITS         1
 #define CL73_USERB0_CL73_UCTRL4_CL73_ANERR_STATUS_SEL_SHIFT        1
 
 /* CL73_UserB0 :: CL73_UCtrl4 :: anerr_timer_en [00:00] */
 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_EN_MASK                0x0001
 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_EN_ALIGN               0
 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_EN_BITS                1
 #define CL73_USERB0_CL73_UCTRL4_ANERR_TIMER_EN_SHIFT               0
 
 
 /****************************************************************************
  * CL73_UserB0 :: CL73_EEECtrl
  */
 /* CL73_UserB0 :: CL73_EEECtrl :: CL73_eeeEn [15:15] */
 #define CL73_USERB0_CL73_EEECTRL_CL73_EEEEN_MASK                   0x8000
 #define CL73_USERB0_CL73_EEECTRL_CL73_EEEEN_ALIGN                  0
 #define CL73_USERB0_CL73_EEECTRL_CL73_EEEEN_BITS                   1
 #define CL73_USERB0_CL73_EEECTRL_CL73_EEEEN_SHIFT                  15
 
 /* CL73_UserB0 :: CL73_EEECtrl :: CL73_eeeNP_after_bp_en [14:14] */
 #define CL73_USERB0_CL73_EEECTRL_CL73_EEENP_AFTER_BP_EN_MASK       0x4000
 #define CL73_USERB0_CL73_EEECTRL_CL73_EEENP_AFTER_BP_EN_ALIGN      0
 #define CL73_USERB0_CL73_EEECTRL_CL73_EEENP_AFTER_BP_EN_BITS       1
 #define CL73_USERB0_CL73_EEECTRL_CL73_EEENP_AFTER_BP_EN_SHIFT      14
 
 /* CL73_UserB0 :: CL73_EEECtrl :: hold_eee_lp_ability [13:13] */
 #define CL73_USERB0_CL73_EEECTRL_HOLD_EEE_LP_ABILITY_MASK          0x2000
 #define CL73_USERB0_CL73_EEECTRL_HOLD_EEE_LP_ABILITY_ALIGN         0
 #define CL73_USERB0_CL73_EEECTRL_HOLD_EEE_LP_ABILITY_BITS          1
 #define CL73_USERB0_CL73_EEECTRL_HOLD_EEE_LP_ABILITY_SHIFT         13
 
 /* CL73_UserB0 :: CL73_EEECtrl :: reserved0 [12:00] */
 #define CL73_USERB0_CL73_EEECTRL_RESERVED0_MASK                    0x1fff
 #define CL73_USERB0_CL73_EEECTRL_RESERVED0_ALIGN                   0
 #define CL73_USERB0_CL73_EEECTRL_RESERVED0_BITS                    13
 #define CL73_USERB0_CL73_EEECTRL_RESERVED0_SHIFT                   0
 
 
 /****************************************************************************
  * Warpcore_USER_CL74_UserB0
  */
 /****************************************************************************
  * CL74_UserB0 :: uFecControl1
  */
 /* CL74_UserB0 :: uFecControl1 :: dbg_enable [15:15] */
 #define CL74_USERB0_UFECCONTROL1_DBG_ENABLE_MASK                   0x8000
 #define CL74_USERB0_UFECCONTROL1_DBG_ENABLE_ALIGN                  0
 #define CL74_USERB0_UFECCONTROL1_DBG_ENABLE_BITS                   1
 #define CL74_USERB0_UFECCONTROL1_DBG_ENABLE_SHIFT                  15
 
 /* CL74_UserB0 :: uFecControl1 :: invParityCnt [14:11] */
 #define CL74_USERB0_UFECCONTROL1_INVPARITYCNT_MASK                 0x7800
 #define CL74_USERB0_UFECCONTROL1_INVPARITYCNT_ALIGN                0
 #define CL74_USERB0_UFECCONTROL1_INVPARITYCNT_BITS                 4
 #define CL74_USERB0_UFECCONTROL1_INVPARITYCNT_SHIFT                11
 
 /* CL74_UserB0 :: uFecControl1 :: good_parity_cnt [10:08] */
 #define CL74_USERB0_UFECCONTROL1_GOOD_PARITY_CNT_MASK              0x0700
 #define CL74_USERB0_UFECCONTROL1_GOOD_PARITY_CNT_ALIGN             0
 #define CL74_USERB0_UFECCONTROL1_GOOD_PARITY_CNT_BITS              3
 #define CL74_USERB0_UFECCONTROL1_GOOD_PARITY_CNT_SHIFT             8
 
 /* CL74_UserB0 :: uFecControl1 :: fec_dec_max_pm [07:03] */
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_MAX_PM_MASK               0x00f8
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_MAX_PM_ALIGN              0
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_MAX_PM_BITS               5
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_MAX_PM_SHIFT              3
 
 /* CL74_UserB0 :: uFecControl1 :: fec_dec_pm_mode [02:02] */
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_PM_MODE_MASK              0x0004
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_PM_MODE_ALIGN             0
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_PM_MODE_BITS              1
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_PM_MODE_SHIFT             2
 
 /* CL74_UserB0 :: uFecControl1 :: fec_enc_data_swap [01:01] */
 #define CL74_USERB0_UFECCONTROL1_FEC_ENC_DATA_SWAP_MASK            0x0002
 #define CL74_USERB0_UFECCONTROL1_FEC_ENC_DATA_SWAP_ALIGN           0
 #define CL74_USERB0_UFECCONTROL1_FEC_ENC_DATA_SWAP_BITS            1
 #define CL74_USERB0_UFECCONTROL1_FEC_ENC_DATA_SWAP_SHIFT           1
 
 /* CL74_UserB0 :: uFecControl1 :: fec_dec_data_swap [00:00] */
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_DATA_SWAP_MASK            0x0001
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_DATA_SWAP_ALIGN           0
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_DATA_SWAP_BITS            1
 #define CL74_USERB0_UFECCONTROL1_FEC_DEC_DATA_SWAP_SHIFT           0
 
 
 /****************************************************************************
  * CL74_UserB0 :: uFecControl2
  */
 /* CL74_UserB0 :: uFecControl2 :: reserved0 [15:04] */
 #define CL74_USERB0_UFECCONTROL2_RESERVED0_MASK                    0xfff0
 #define CL74_USERB0_UFECCONTROL2_RESERVED0_ALIGN                   0
 #define CL74_USERB0_UFECCONTROL2_RESERVED0_BITS                    12
 #define CL74_USERB0_UFECCONTROL2_RESERVED0_SHIFT                   4
 
 /* CL74_UserB0 :: uFecControl2 :: dbg_err_mode [03:03] */
 #define CL74_USERB0_UFECCONTROL2_DBG_ERR_MODE_MASK                 0x0008
 #define CL74_USERB0_UFECCONTROL2_DBG_ERR_MODE_ALIGN                0
 #define CL74_USERB0_UFECCONTROL2_DBG_ERR_MODE_BITS                 1
 #define CL74_USERB0_UFECCONTROL2_DBG_ERR_MODE_SHIFT                3
 
 /* CL74_UserB0 :: uFecControl2 :: reserved_for_eco1 [02:00] */
 #define CL74_USERB0_UFECCONTROL2_RESERVED_FOR_ECO1_MASK            0x0007
 #define CL74_USERB0_UFECCONTROL2_RESERVED_FOR_ECO1_ALIGN           0
 #define CL74_USERB0_UFECCONTROL2_RESERVED_FOR_ECO1_BITS            3
 #define CL74_USERB0_UFECCONTROL2_RESERVED_FOR_ECO1_SHIFT           0
 
 
 /****************************************************************************
  * CL74_UserB0 :: uFecControl3
  */
 /* CL74_UserB0 :: uFecControl3 :: reserved0 [15:04] */
 #define CL74_USERB0_UFECCONTROL3_RESERVED0_MASK                    0xfff0
 #define CL74_USERB0_UFECCONTROL3_RESERVED0_ALIGN                   0
 #define CL74_USERB0_UFECCONTROL3_RESERVED0_BITS                    12
 #define CL74_USERB0_UFECCONTROL3_RESERVED0_SHIFT                   4
 
 /* CL74_UserB0 :: uFecControl3 :: brcm_fec_error_en_ovr [03:03] */
 #define CL74_USERB0_UFECCONTROL3_BRCM_FEC_ERROR_EN_OVR_MASK        0x0008
 #define CL74_USERB0_UFECCONTROL3_BRCM_FEC_ERROR_EN_OVR_ALIGN       0
 #define CL74_USERB0_UFECCONTROL3_BRCM_FEC_ERROR_EN_OVR_BITS        1
 #define CL74_USERB0_UFECCONTROL3_BRCM_FEC_ERROR_EN_OVR_SHIFT       3
 
 /* CL74_UserB0 :: uFecControl3 :: brcm_fec_error_en_ovr_val [02:02] */
 #define CL74_USERB0_UFECCONTROL3_BRCM_FEC_ERROR_EN_OVR_VAL_MASK    0x0004
 #define CL74_USERB0_UFECCONTROL3_BRCM_FEC_ERROR_EN_OVR_VAL_ALIGN   0
 #define CL74_USERB0_UFECCONTROL3_BRCM_FEC_ERROR_EN_OVR_VAL_BITS    1
 #define CL74_USERB0_UFECCONTROL3_BRCM_FEC_ERROR_EN_OVR_VAL_SHIFT   2
 
 /* CL74_UserB0 :: uFecControl3 :: fec_enable_ovr [01:01] */
 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_MASK               0x0002
 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_ALIGN              0
 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_BITS               1
 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_SHIFT              1
 
 /* CL74_UserB0 :: uFecControl3 :: fec_enable_ovr_val [00:00] */
 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_VAL_MASK           0x0001
 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_VAL_ALIGN          0
 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_VAL_BITS           1
 #define CL74_USERB0_UFECCONTROL3_FEC_ENABLE_OVR_VAL_SHIFT          0
 
 
 /****************************************************************************
  * CL74_UserB0 :: uFecdbg_edataL
  */
 /* CL74_UserB0 :: uFecdbg_edataL :: uFecdbg_edataL [15:00] */
 #define CL74_USERB0_UFECDBG_EDATAL_UFECDBG_EDATAL_MASK             0xffff
 #define CL74_USERB0_UFECDBG_EDATAL_UFECDBG_EDATAL_ALIGN            0
 #define CL74_USERB0_UFECDBG_EDATAL_UFECDBG_EDATAL_BITS             16
 #define CL74_USERB0_UFECDBG_EDATAL_UFECDBG_EDATAL_SHIFT            0
 
 
 /****************************************************************************
  * CL74_UserB0 :: uFecdbg_edataH
  */
 /* CL74_UserB0 :: uFecdbg_edataH :: uFecdbg_edataH [15:00] */
 #define CL74_USERB0_UFECDBG_EDATAH_UFECDBG_EDATAH_MASK             0xffff
 #define CL74_USERB0_UFECDBG_EDATAH_UFECDBG_EDATAH_ALIGN            0
 #define CL74_USERB0_UFECDBG_EDATAH_UFECDBG_EDATAH_BITS             16
 #define CL74_USERB0_UFECDBG_EDATAH_UFECDBG_EDATAH_SHIFT            0
 
 
 /****************************************************************************
  * Warpcore_USER_EEE_UserB0
  */
 /****************************************************************************
  * EEE_UserB0 :: eee_combo_control0
  */
 /* EEE_UserB0 :: eee_combo_control0 :: R2_eee_en [15:15] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_EEE_EN_MASK               0x8000
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_EEE_EN_ALIGN              0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_EEE_EN_BITS               1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_EEE_EN_SHIFT              15
 
 /* EEE_UserB0 :: eee_combo_control0 :: R2_LPI_en_rx [14:14] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_RX_MASK            0x4000
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_RX_ALIGN           0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_RX_BITS            1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_RX_SHIFT           14
 
 /* EEE_UserB0 :: eee_combo_control0 :: R2_LPI_en_tx [13:13] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_TX_MASK            0x2000
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_TX_ALIGN           0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_TX_BITS            1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_R2_LPI_EN_TX_SHIFT           13
 
 /* EEE_UserB0 :: eee_combo_control0 :: reserved_for_eco0 [12:08] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_RESERVED_FOR_ECO0_MASK       0x1f00
 #define EEE_USERB0_EEE_COMBO_CONTROL0_RESERVED_FOR_ECO0_ALIGN      0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_RESERVED_FOR_ECO0_BITS       5
 #define EEE_USERB0_EEE_COMBO_CONTROL0_RESERVED_FOR_ECO0_SHIFT      8
 
 /* EEE_UserB0 :: eee_combo_control0 :: afe_rx_quiet_en [07:07] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_AFE_RX_QUIET_EN_MASK         0x0080
 #define EEE_USERB0_EEE_COMBO_CONTROL0_AFE_RX_QUIET_EN_ALIGN        0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_AFE_RX_QUIET_EN_BITS         1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_AFE_RX_QUIET_EN_SHIFT        7
 
 /* EEE_UserB0 :: eee_combo_control0 :: eee_bypass_sigdet_filt [06:06] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_BYPASS_SIGDET_FILT_MASK  0x0040
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_BYPASS_SIGDET_FILT_ALIGN 0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_BYPASS_SIGDET_FILT_BITS  1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_BYPASS_SIGDET_FILT_SHIFT 6
 
 /* EEE_UserB0 :: eee_combo_control0 :: cl36_eee_rx_os8_afrst_en [05:05] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_RX_OS8_AFRST_EN_MASK 0x0020
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_RX_OS8_AFRST_EN_ALIGN 0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_RX_OS8_AFRST_EN_BITS 1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_RX_OS8_AFRST_EN_SHIFT 5
 
 /* EEE_UserB0 :: eee_combo_control0 :: cl36_eee_tx_os8_afrst_en [04:04] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_TX_OS8_AFRST_EN_MASK 0x0010
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_TX_OS8_AFRST_EN_ALIGN 0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_TX_OS8_AFRST_EN_BITS 1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL36_EEE_TX_OS8_AFRST_EN_SHIFT 4
 
 /* EEE_UserB0 :: eee_combo_control0 :: cl49_eee_txfifo_ckgate_en [03:03] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL49_EEE_TXFIFO_CKGATE_EN_MASK 0x0008
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL49_EEE_TXFIFO_CKGATE_EN_ALIGN 0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL49_EEE_TXFIFO_CKGATE_EN_BITS 1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_CL49_EEE_TXFIFO_CKGATE_EN_SHIFT 3
 
 /* EEE_UserB0 :: eee_combo_control0 :: lpi_en_force [02:02] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_LPI_EN_FORCE_MASK            0x0004
 #define EEE_USERB0_EEE_COMBO_CONTROL0_LPI_EN_FORCE_ALIGN           0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_LPI_EN_FORCE_BITS            1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_LPI_EN_FORCE_SHIFT           2
 
 /* EEE_UserB0 :: eee_combo_control0 :: eee_en_force_val [01:01] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_VAL_MASK        0x0002
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_VAL_ALIGN       0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_VAL_BITS        1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_VAL_SHIFT       1
 
 /* EEE_UserB0 :: eee_combo_control0 :: eee_en_force [00:00] */
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_MASK            0x0001
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_ALIGN           0
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_BITS            1
 #define EEE_USERB0_EEE_COMBO_CONTROL0_EEE_EN_FORCE_SHIFT           0
 
 
 /****************************************************************************
  * EEE_UserB0 :: cl36_tx_lpi_sm
  */
 /* EEE_UserB0 :: cl36_tx_lpi_sm :: tx1g_LPI_rcvd [15:15] */
 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_RCVD_MASK               0x8000
 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_RCVD_ALIGN              0
 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_RCVD_BITS               1
 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_RCVD_SHIFT              15
 
 /* EEE_UserB0 :: cl36_tx_lpi_sm :: tx1g_LPI_detect [14:14] */
 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_DETECT_MASK             0x4000
 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_DETECT_ALIGN            0
 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_DETECT_BITS             1
 #define EEE_USERB0_CL36_TX_LPI_SM_TX1G_LPI_DETECT_SHIFT            14
 
 /* EEE_UserB0 :: cl36_tx_lpi_sm :: reserved_for_eco0 [13:07] */
 #define EEE_USERB0_CL36_TX_LPI_SM_RESERVED_FOR_ECO0_MASK           0x3f80
 #define EEE_USERB0_CL36_TX_LPI_SM_RESERVED_FOR_ECO0_ALIGN          0
 #define EEE_USERB0_CL36_TX_LPI_SM_RESERVED_FOR_ECO0_BITS           7
 #define EEE_USERB0_CL36_TX_LPI_SM_RESERVED_FOR_ECO0_SHIFT          7
 
 /* EEE_UserB0 :: cl36_tx_lpi_sm :: cl36_tx_lpi_state_l [06:03] */
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_MASK         0x0078
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_ALIGN        0
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_BITS         4
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_SHIFT        3
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_TX_REFRESH   8
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_TX_QUIET     4
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_TX_SLEEP     2
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_L_TX_ACTIVE    1
 
 /* EEE_UserB0 :: cl36_tx_lpi_sm :: cl36_tx_lpi_state_c [02:00] */
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_MASK         0x0007
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_ALIGN        0
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_BITS         3
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_SHIFT        0
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_TX_REFRESH   3
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_TX_QUIET     2
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_TX_SLEEP     1
 #define EEE_USERB0_CL36_TX_LPI_SM_CL36_TX_LPI_STATE_C_TX_ACTIVE    0
 
 
 /****************************************************************************
  * EEE_UserB0 :: cl36_rx_lpi_sm
  */
 /* EEE_UserB0 :: cl36_rx_lpi_sm :: rx1g_LPI_rcvd [15:15] */
 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_RCVD_MASK               0x8000
 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_RCVD_ALIGN              0
 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_RCVD_BITS               1
 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_RCVD_SHIFT              15
 
 /* EEE_UserB0 :: cl36_rx_lpi_sm :: rx1g_LPI_detect [14:14] */
 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_DETECT_MASK             0x4000
 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_DETECT_ALIGN            0
 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_DETECT_BITS             1
 #define EEE_USERB0_CL36_RX_LPI_SM_RX1G_LPI_DETECT_SHIFT            14
 
 /* EEE_UserB0 :: cl36_rx_lpi_sm :: reserved_for_eco0 [13:09] */
 #define EEE_USERB0_CL36_RX_LPI_SM_RESERVED_FOR_ECO0_MASK           0x3e00
 #define EEE_USERB0_CL36_RX_LPI_SM_RESERVED_FOR_ECO0_ALIGN          0
 #define EEE_USERB0_CL36_RX_LPI_SM_RESERVED_FOR_ECO0_BITS           5
 #define EEE_USERB0_CL36_RX_LPI_SM_RESERVED_FOR_ECO0_SHIFT          9
 
 /* EEE_UserB0 :: cl36_rx_lpi_sm :: cl36_rx_lpi_state_l [08:03] */
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_MASK         0x01f8
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_ALIGN        0
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_BITS         6
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_SHIFT        3
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_LINK_FAIL 32
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_WTF       16
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_WAKE      8
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_QUIET     4
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_SLEEP     2
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_L_RX_ACTIVE    1
 
 /* EEE_UserB0 :: cl36_rx_lpi_sm :: cl36_rx_lpi_state_c [02:00] */
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_MASK         0x0007
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_ALIGN        0
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_BITS         3
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_SHIFT        0
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_LINK_FAIL 5
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_WTF       4
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_WAKE      3
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_QUIET     2
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_SLEEP     1
 #define EEE_USERB0_CL36_RX_LPI_SM_CL36_RX_LPI_STATE_C_RX_ACTIVE    0
 
 
 /****************************************************************************
  * EEE_UserB0 :: cl49_tx_lpi_sm
  */
 /* EEE_UserB0 :: cl49_tx_lpi_sm :: cl49_tx_LPI_rcvd [15:15] */
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_RCVD_MASK            0x8000
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_RCVD_ALIGN           0
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_RCVD_BITS            1
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_RCVD_SHIFT           15
 
 /* EEE_UserB0 :: cl49_tx_lpi_sm :: cl49_tx_LPI_detect [14:14] */
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_DETECT_MASK          0x4000
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_DETECT_ALIGN         0
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_DETECT_BITS          1
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_DETECT_SHIFT         14
 
 /* EEE_UserB0 :: cl49_tx_lpi_sm :: reserved_for_eco0 [13:10] */
 #define EEE_USERB0_CL49_TX_LPI_SM_RESERVED_FOR_ECO0_MASK           0x3c00
 #define EEE_USERB0_CL49_TX_LPI_SM_RESERVED_FOR_ECO0_ALIGN          0
 #define EEE_USERB0_CL49_TX_LPI_SM_RESERVED_FOR_ECO0_BITS           4
 #define EEE_USERB0_CL49_TX_LPI_SM_RESERVED_FOR_ECO0_SHIFT          10
 
 /* EEE_UserB0 :: cl49_tx_lpi_sm :: cl49_tx_lpi_state_l [09:03] */
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_MASK         0x03f8
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_ALIGN        0
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_BITS         7
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_SHIFT        3
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_SCR_RESET_2  64
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_SCR_RESET_1  32
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_TX_WAKE      16
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_TX_REFRESH   8
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_TX_QUIET     4
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_TX_SLEEP     2
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_L_TX_ACTIVE    1
 
 /* EEE_UserB0 :: cl49_tx_lpi_sm :: cl49_tx_lpi_state_c [02:00] */
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_MASK         0x0007
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_ALIGN        0
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_BITS         3
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_SHIFT        0
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_SCR_RESET_2  6
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_SCR_RESET_1  5
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_TX_WAKE      4
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_TX_REFRESH   3
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_TX_QUIET     2
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_TX_SLEEP     1
 #define EEE_USERB0_CL49_TX_LPI_SM_CL49_TX_LPI_STATE_C_TX_ACTIVE    0
 
 
 /****************************************************************************
  * EEE_UserB0 :: cl49_rx_lpi_sm
  */
 /* EEE_UserB0 :: cl49_rx_lpi_sm :: cl49_rx_LPI_rcvd [15:15] */
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_RCVD_MASK            0x8000
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_RCVD_ALIGN           0
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_RCVD_BITS            1
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_RCVD_SHIFT           15
 
 /* EEE_UserB0 :: cl49_rx_lpi_sm :: cl49_rx_LPI_detect [14:14] */
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_DETECT_MASK          0x4000
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_DETECT_ALIGN         0
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_DETECT_BITS          1
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_DETECT_SHIFT         14
 
 /* EEE_UserB0 :: cl49_rx_lpi_sm :: reserved_for_eco0 [13:09] */
 #define EEE_USERB0_CL49_RX_LPI_SM_RESERVED_FOR_ECO0_MASK           0x3e00
 #define EEE_USERB0_CL49_RX_LPI_SM_RESERVED_FOR_ECO0_ALIGN          0
 #define EEE_USERB0_CL49_RX_LPI_SM_RESERVED_FOR_ECO0_BITS           5
 #define EEE_USERB0_CL49_RX_LPI_SM_RESERVED_FOR_ECO0_SHIFT          9
 
 /* EEE_UserB0 :: cl49_rx_lpi_sm :: cl49_rx_lpi_state_l [08:03] */
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_MASK         0x01f8
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_ALIGN        0
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_BITS         6
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_SHIFT        3
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_LINK_FAIL 32
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_WTF       16
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_WAKE      8
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_QUIET     4
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_SLEEP     2
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_L_RX_ACTIVE    1
 
 /* EEE_UserB0 :: cl49_rx_lpi_sm :: cl49_rx_lpi_state_c [02:00] */
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_MASK         0x0007
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_ALIGN        0
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_BITS         3
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_SHIFT        0
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_LINK_FAIL 5
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_WTF       4
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_WAKE      3
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_QUIET     2
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_SLEEP     1
 #define EEE_USERB0_CL49_RX_LPI_SM_CL49_RX_LPI_STATE_C_RX_ACTIVE    0
 
 
 /****************************************************************************
  * EEE_UserB0 :: tx_sleep_timer
  */
 /* EEE_UserB0 :: tx_sleep_timer :: tx_ts_cnt_mdio [15:00] */
 #define EEE_USERB0_TX_SLEEP_TIMER_TX_TS_CNT_MDIO_MASK              0xffff
 #define EEE_USERB0_TX_SLEEP_TIMER_TX_TS_CNT_MDIO_ALIGN             0
 #define EEE_USERB0_TX_SLEEP_TIMER_TX_TS_CNT_MDIO_BITS              16
 #define EEE_USERB0_TX_SLEEP_TIMER_TX_TS_CNT_MDIO_SHIFT             0
 
 
 /****************************************************************************
  * EEE_UserB0 :: cl49_tx_sleep_timer
  */
 /* EEE_UserB0 :: cl49_tx_sleep_timer :: cl49_tx_ts_cnt_mdio [15:00] */
 #define EEE_USERB0_CL49_TX_SLEEP_TIMER_CL49_TX_TS_CNT_MDIO_MASK    0xffff
 #define EEE_USERB0_CL49_TX_SLEEP_TIMER_CL49_TX_TS_CNT_MDIO_ALIGN   0
 #define EEE_USERB0_CL49_TX_SLEEP_TIMER_CL49_TX_TS_CNT_MDIO_BITS    16
 #define EEE_USERB0_CL49_TX_SLEEP_TIMER_CL49_TX_TS_CNT_MDIO_SHIFT   0
 
 
 /****************************************************************************
  * EEE_UserB0 :: tx_wake_timer
  */
 /* EEE_UserB0 :: tx_wake_timer :: tx_tw_cnt_mdio [15:00] */
 #define EEE_USERB0_TX_WAKE_TIMER_TX_TW_CNT_MDIO_MASK               0xffff
 #define EEE_USERB0_TX_WAKE_TIMER_TX_TW_CNT_MDIO_ALIGN              0
 #define EEE_USERB0_TX_WAKE_TIMER_TX_TW_CNT_MDIO_BITS               16
 #define EEE_USERB0_TX_WAKE_TIMER_TX_TW_CNT_MDIO_SHIFT              0
 
 
 /****************************************************************************
  * EEE_UserB0 :: rx_offset_timer
  */
 /* EEE_UserB0 :: rx_offset_timer :: rx_tq_offset_mdio [15:00] */
 #define EEE_USERB0_RX_OFFSET_TIMER_RX_TQ_OFFSET_MDIO_MASK          0xffff
 #define EEE_USERB0_RX_OFFSET_TIMER_RX_TQ_OFFSET_MDIO_ALIGN         0
 #define EEE_USERB0_RX_OFFSET_TIMER_RX_TQ_OFFSET_MDIO_BITS          16
 #define EEE_USERB0_RX_OFFSET_TIMER_RX_TQ_OFFSET_MDIO_SHIFT         0
 
 
 /****************************************************************************
  * EEE_UserB0 :: rx_wake_time_fault_timer
  */
 /* EEE_UserB0 :: rx_wake_time_fault_timer :: rx_wtf_cnt_mdio [15:00] */
 #define EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER_RX_WTF_CNT_MDIO_MASK   0xffff
 #define EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER_RX_WTF_CNT_MDIO_ALIGN  0
 #define EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER_RX_WTF_CNT_MDIO_BITS   16
 #define EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER_RX_WTF_CNT_MDIO_SHIFT  0
 
 
 /****************************************************************************
  * EEE_UserB0 :: misc_timer
  */
 /* EEE_UserB0 :: misc_timer :: reserved_for_eco0 [15:10] */
 #define EEE_USERB0_MISC_TIMER_RESERVED_FOR_ECO0_MASK               0xfc00
 #define EEE_USERB0_MISC_TIMER_RESERVED_FOR_ECO0_ALIGN              0
 #define EEE_USERB0_MISC_TIMER_RESERVED_FOR_ECO0_BITS               6
 #define EEE_USERB0_MISC_TIMER_RESERVED_FOR_ECO0_SHIFT              10
 
 /* EEE_UserB0 :: misc_timer :: grp5_tx_tq_cnt_msb_mdio [09:08] */
 #define EEE_USERB0_MISC_TIMER_GRP5_TX_TQ_CNT_MSB_MDIO_MASK         0x0300
 #define EEE_USERB0_MISC_TIMER_GRP5_TX_TQ_CNT_MSB_MDIO_ALIGN        0
 #define EEE_USERB0_MISC_TIMER_GRP5_TX_TQ_CNT_MSB_MDIO_BITS         2
 #define EEE_USERB0_MISC_TIMER_GRP5_TX_TQ_CNT_MSB_MDIO_SHIFT        8
 
 /* EEE_UserB0 :: misc_timer :: grp4_tx_tq_cnt_msb_mdio [07:06] */
 #define EEE_USERB0_MISC_TIMER_GRP4_TX_TQ_CNT_MSB_MDIO_MASK         0x00c0
 #define EEE_USERB0_MISC_TIMER_GRP4_TX_TQ_CNT_MSB_MDIO_ALIGN        0
 #define EEE_USERB0_MISC_TIMER_GRP4_TX_TQ_CNT_MSB_MDIO_BITS         2
 #define EEE_USERB0_MISC_TIMER_GRP4_TX_TQ_CNT_MSB_MDIO_SHIFT        6
 
 /* EEE_UserB0 :: misc_timer :: grp3_tx_tq_cnt_msb_mdio [05:04] */
 #define EEE_USERB0_MISC_TIMER_GRP3_TX_TQ_CNT_MSB_MDIO_MASK         0x0030
 #define EEE_USERB0_MISC_TIMER_GRP3_TX_TQ_CNT_MSB_MDIO_ALIGN        0
 #define EEE_USERB0_MISC_TIMER_GRP3_TX_TQ_CNT_MSB_MDIO_BITS         2
 #define EEE_USERB0_MISC_TIMER_GRP3_TX_TQ_CNT_MSB_MDIO_SHIFT        4
 
 /* EEE_UserB0 :: misc_timer :: grp2_tx_tq_cnt_msb_mdio [03:02] */
 #define EEE_USERB0_MISC_TIMER_GRP2_TX_TQ_CNT_MSB_MDIO_MASK         0x000c
 #define EEE_USERB0_MISC_TIMER_GRP2_TX_TQ_CNT_MSB_MDIO_ALIGN        0
 #define EEE_USERB0_MISC_TIMER_GRP2_TX_TQ_CNT_MSB_MDIO_BITS         2
 #define EEE_USERB0_MISC_TIMER_GRP2_TX_TQ_CNT_MSB_MDIO_SHIFT        2
 
 /* EEE_UserB0 :: misc_timer :: grp1_tx_tq_cnt_msb_mdio [01:00] */
 #define EEE_USERB0_MISC_TIMER_GRP1_TX_TQ_CNT_MSB_MDIO_MASK         0x0003
 #define EEE_USERB0_MISC_TIMER_GRP1_TX_TQ_CNT_MSB_MDIO_ALIGN        0
 #define EEE_USERB0_MISC_TIMER_GRP1_TX_TQ_CNT_MSB_MDIO_BITS         2
 #define EEE_USERB0_MISC_TIMER_GRP1_TX_TQ_CNT_MSB_MDIO_SHIFT        0
 
 
 /****************************************************************************
  * EEE_UserB0 :: eee_hyst_timer
  */
 /* EEE_UserB0 :: eee_hyst_timer :: cl49_tx_us_cnt [15:09] */
 #define EEE_USERB0_EEE_HYST_TIMER_CL49_TX_US_CNT_MASK              0xfe00
 #define EEE_USERB0_EEE_HYST_TIMER_CL49_TX_US_CNT_ALIGN             0
 #define EEE_USERB0_EEE_HYST_TIMER_CL49_TX_US_CNT_BITS              7
 #define EEE_USERB0_EEE_HYST_TIMER_CL49_TX_US_CNT_SHIFT             9
 
 /* EEE_UserB0 :: eee_hyst_timer :: LPI_hyst_cnt [08:06] */
 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_CNT_MASK                0x01c0
 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_CNT_ALIGN               0
 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_CNT_BITS                3
 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_CNT_SHIFT               6
 
 /* EEE_UserB0 :: eee_hyst_timer :: LPI_hyst_en [05:05] */
 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_EN_MASK                 0x0020
 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_EN_ALIGN                0
 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_EN_BITS                 1
 #define EEE_USERB0_EEE_HYST_TIMER_LPI_HYST_EN_SHIFT                5
 
 /* EEE_UserB0 :: eee_hyst_timer :: eee_sigdet_cnt [04:00] */
 #define EEE_USERB0_EEE_HYST_TIMER_EEE_SIGDET_CNT_MASK              0x001f
 #define EEE_USERB0_EEE_HYST_TIMER_EEE_SIGDET_CNT_ALIGN             0
 #define EEE_USERB0_EEE_HYST_TIMER_EEE_SIGDET_CNT_BITS              5
 #define EEE_USERB0_EEE_HYST_TIMER_EEE_SIGDET_CNT_SHIFT             0
 
 
 /****************************************************************************
  * EEE_UserB0 :: eee_override_ctrl
  */
 /* EEE_UserB0 :: eee_override_ctrl :: reserved_for_eco0 [15:10] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RESERVED_FOR_ECO0_MASK        0xfc00
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RESERVED_FOR_ECO0_ALIGN       0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RESERVED_FOR_ECO0_BITS        6
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RESERVED_FOR_ECO0_SHIFT       10
 
 /* EEE_UserB0 :: eee_override_ctrl :: rx_wake_dis [09:09] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_WAKE_DIS_MASK              0x0200
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_WAKE_DIS_ALIGN             0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_WAKE_DIS_BITS              1
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_WAKE_DIS_SHIFT             9
 
 /* EEE_UserB0 :: eee_override_ctrl :: tx_refresh_dis [08:08] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_REFRESH_DIS_MASK           0x0100
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_REFRESH_DIS_ALIGN          0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_REFRESH_DIS_BITS           1
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_REFRESH_DIS_SHIFT          8
 
 /* EEE_UserB0 :: eee_override_ctrl :: TxElectIdle_force_val [07:07] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_VAL_MASK    0x0080
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_VAL_ALIGN   0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_VAL_BITS    1
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_VAL_SHIFT   7
 
 /* EEE_UserB0 :: eee_override_ctrl :: TxElectIdle_force [06:06] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_MASK        0x0040
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_ALIGN       0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_BITS        1
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TXELECTIDLE_FORCE_SHIFT       6
 
 /* EEE_UserB0 :: eee_override_ctrl :: rx_lpi_active_force_val [05:05] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_VAL_MASK  0x0020
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_VAL_ALIGN 0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_VAL_BITS  1
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_VAL_SHIFT 5
 
 /* EEE_UserB0 :: eee_override_ctrl :: rx_lpi_active_force [04:04] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_MASK      0x0010
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_ALIGN     0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_BITS      1
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_LPI_ACTIVE_FORCE_SHIFT     4
 
 /* EEE_UserB0 :: eee_override_ctrl :: rx_quiet_force_val [03:03] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_VAL_MASK       0x0008
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_VAL_ALIGN      0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_VAL_BITS       1
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_VAL_SHIFT      3
 
 /* EEE_UserB0 :: eee_override_ctrl :: rx_quiet_force [02:02] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_MASK           0x0004
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_ALIGN          0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_BITS           1
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_RX_QUIET_FORCE_SHIFT          2
 
 /* EEE_UserB0 :: eee_override_ctrl :: tx_quiet_force_val [01:01] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_VAL_MASK       0x0002
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_VAL_ALIGN      0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_VAL_BITS       1
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_VAL_SHIFT      1
 
 /* EEE_UserB0 :: eee_override_ctrl :: tx_quiet_force [00:00] */
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_MASK           0x0001
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_ALIGN          0
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_BITS           1
 #define EEE_USERB0_EEE_OVERRIDE_CTRL_TX_QUIET_FORCE_SHIFT          0
 
 
 /****************************************************************************
  * EEE_UserB0 :: eee_combo_control1
  */
 /* EEE_UserB0 :: eee_combo_control1 :: reserved_for_eco0 [15:05] */
 #define EEE_USERB0_EEE_COMBO_CONTROL1_RESERVED_FOR_ECO0_MASK       0xffe0
 #define EEE_USERB0_EEE_COMBO_CONTROL1_RESERVED_FOR_ECO0_ALIGN      0
 #define EEE_USERB0_EEE_COMBO_CONTROL1_RESERVED_FOR_ECO0_BITS       11
 #define EEE_USERB0_EEE_COMBO_CONTROL1_RESERVED_FOR_ECO0_SHIFT      5
 
 /* EEE_UserB0 :: eee_combo_control1 :: tx_elec_idle_dly_cnt [04:00] */
 #define EEE_USERB0_EEE_COMBO_CONTROL1_TX_ELEC_IDLE_DLY_CNT_MASK    0x001f
 #define EEE_USERB0_EEE_COMBO_CONTROL1_TX_ELEC_IDLE_DLY_CNT_ALIGN   0
 #define EEE_USERB0_EEE_COMBO_CONTROL1_TX_ELEC_IDLE_DLY_CNT_BITS    5
 #define EEE_USERB0_EEE_COMBO_CONTROL1_TX_ELEC_IDLE_DLY_CNT_SHIFT   0
 
 
 /****************************************************************************
  * EEE_UserB0 :: cl49_eee_char
  */
 /* EEE_UserB0 :: cl49_eee_char :: reserved_for_eco0 [15:15] */
 #define EEE_USERB0_CL49_EEE_CHAR_RESERVED_FOR_ECO0_MASK            0x8000
 #define EEE_USERB0_CL49_EEE_CHAR_RESERVED_FOR_ECO0_ALIGN           0
 #define EEE_USERB0_CL49_EEE_CHAR_RESERVED_FOR_ECO0_BITS            1
 #define EEE_USERB0_CL49_EEE_CHAR_RESERVED_FOR_ECO0_SHIFT           15
 
 /* EEE_UserB0 :: cl49_eee_char :: cl49_lpi [14:08] */
 #define EEE_USERB0_CL49_EEE_CHAR_CL49_LPI_MASK                     0x7f00
 #define EEE_USERB0_CL49_EEE_CHAR_CL49_LPI_ALIGN                    0
 #define EEE_USERB0_CL49_EEE_CHAR_CL49_LPI_BITS                     7
 #define EEE_USERB0_CL49_EEE_CHAR_CL49_LPI_SHIFT                    8
 
 /* EEE_UserB0 :: cl49_eee_char :: xgmii_lpi [07:00] */
 #define EEE_USERB0_CL49_EEE_CHAR_XGMII_LPI_MASK                    0x00ff
 #define EEE_USERB0_CL49_EEE_CHAR_XGMII_LPI_ALIGN                   0
 #define EEE_USERB0_CL49_EEE_CHAR_XGMII_LPI_BITS                    8
 #define EEE_USERB0_CL49_EEE_CHAR_XGMII_LPI_SHIFT                   0
 
 
 /****************************************************************************
  * Warpcore_USER_EEE_UserB1
  */
 /****************************************************************************
  * EEE_UserB1 :: EEE_AN_Ctrl
  */
 /* EEE_UserB1 :: EEE_AN_Ctrl :: EEE_res_status_CL_sel [15:14] */
 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_CL_SEL_MASK          0xc000
 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_CL_SEL_ALIGN         0
 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_CL_SEL_BITS          2
 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_CL_SEL_SHIFT         14
 
 /* EEE_UserB1 :: EEE_AN_Ctrl :: EEE_res_status_Timer_sel [13:12] */
 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_TIMER_SEL_MASK       0x3000
 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_TIMER_SEL_ALIGN      0
 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_TIMER_SEL_BITS       2
 #define EEE_USERB1_EEE_AN_CTRL_EEE_RES_STATUS_TIMER_SEL_SHIFT      12
 
 /* EEE_UserB1 :: EEE_AN_Ctrl :: reserved0 [11:11] */
 #define EEE_USERB1_EEE_AN_CTRL_RESERVED0_MASK                      0x0800
 #define EEE_USERB1_EEE_AN_CTRL_RESERVED0_ALIGN                     0
 #define EEE_USERB1_EEE_AN_CTRL_RESERVED0_BITS                      1
 #define EEE_USERB1_EEE_AN_CTRL_RESERVED0_SHIFT                     11
 
 /* EEE_UserB1 :: EEE_AN_Ctrl :: EEE_page_number [10:00] */
 #define EEE_USERB1_EEE_AN_CTRL_EEE_PAGE_NUMBER_MASK                0x07ff
 #define EEE_USERB1_EEE_AN_CTRL_EEE_PAGE_NUMBER_ALIGN               0
 #define EEE_USERB1_EEE_AN_CTRL_EEE_PAGE_NUMBER_BITS                11
 #define EEE_USERB1_EEE_AN_CTRL_EEE_PAGE_NUMBER_SHIFT               0
 
 
 /****************************************************************************
  * EEE_UserB1 :: EEE_UP1
  */
 /* EEE_UserB1 :: EEE_UP1 :: reserved0 [15:11] */
 #define EEE_USERB1_EEE_UP1_RESERVED0_MASK                          0xf800
 #define EEE_USERB1_EEE_UP1_RESERVED0_ALIGN                         0
 #define EEE_USERB1_EEE_UP1_RESERVED0_BITS                          5
 #define EEE_USERB1_EEE_UP1_RESERVED0_SHIFT                         11
 
 /* EEE_UserB1 :: EEE_UP1 :: Group2_Level [10:07] */
 #define EEE_USERB1_EEE_UP1_GROUP2_LEVEL_MASK                       0x0780
 #define EEE_USERB1_EEE_UP1_GROUP2_LEVEL_ALIGN                      0
 #define EEE_USERB1_EEE_UP1_GROUP2_LEVEL_BITS                       4
 #define EEE_USERB1_EEE_UP1_GROUP2_LEVEL_SHIFT                      7
 
 /* EEE_UserB1 :: EEE_UP1 :: Group1_Level [06:03] */
 #define EEE_USERB1_EEE_UP1_GROUP1_LEVEL_MASK                       0x0078
 #define EEE_USERB1_EEE_UP1_GROUP1_LEVEL_ALIGN                      0
 #define EEE_USERB1_EEE_UP1_GROUP1_LEVEL_BITS                       4
 #define EEE_USERB1_EEE_UP1_GROUP1_LEVEL_SHIFT                      3
 
 /* EEE_UserB1 :: EEE_UP1 :: cl73_override [02:02] */
 #define EEE_USERB1_EEE_UP1_CL73_OVERRIDE_MASK                      0x0004
 #define EEE_USERB1_EEE_UP1_CL73_OVERRIDE_ALIGN                     0
 #define EEE_USERB1_EEE_UP1_CL73_OVERRIDE_BITS                      1
 #define EEE_USERB1_EEE_UP1_CL73_OVERRIDE_SHIFT                     2
 
 /* EEE_UserB1 :: EEE_UP1 :: Pwrdn [01:01] */
 #define EEE_USERB1_EEE_UP1_PWRDN_MASK                              0x0002
 #define EEE_USERB1_EEE_UP1_PWRDN_ALIGN                             0
 #define EEE_USERB1_EEE_UP1_PWRDN_BITS                              1
 #define EEE_USERB1_EEE_UP1_PWRDN_SHIFT                             1
 
 /* EEE_UserB1 :: EEE_UP1 :: EEE [00:00] */
 #define EEE_USERB1_EEE_UP1_EEE_MASK                                0x0001
 #define EEE_USERB1_EEE_UP1_EEE_ALIGN                               0
 #define EEE_USERB1_EEE_UP1_EEE_BITS                                1
 #define EEE_USERB1_EEE_UP1_EEE_SHIFT                               0
 
 
 /****************************************************************************
  * EEE_UserB1 :: EEE_UP2
  */
 /* EEE_UserB1 :: EEE_UP2 :: reserved0 [15:08] */
 #define EEE_USERB1_EEE_UP2_RESERVED0_MASK                          0xff00
 #define EEE_USERB1_EEE_UP2_RESERVED0_ALIGN                         0
 #define EEE_USERB1_EEE_UP2_RESERVED0_BITS                          8
 #define EEE_USERB1_EEE_UP2_RESERVED0_SHIFT                         8
 
 /* EEE_UserB1 :: EEE_UP2 :: Group4_Level [07:04] */
 #define EEE_USERB1_EEE_UP2_GROUP4_LEVEL_MASK                       0x00f0
 #define EEE_USERB1_EEE_UP2_GROUP4_LEVEL_ALIGN                      0
 #define EEE_USERB1_EEE_UP2_GROUP4_LEVEL_BITS                       4
 #define EEE_USERB1_EEE_UP2_GROUP4_LEVEL_SHIFT                      4
 
 /* EEE_UserB1 :: EEE_UP2 :: Group3_Level [03:00] */
 #define EEE_USERB1_EEE_UP2_GROUP3_LEVEL_MASK                       0x000f
 #define EEE_USERB1_EEE_UP2_GROUP3_LEVEL_ALIGN                      0
 #define EEE_USERB1_EEE_UP2_GROUP3_LEVEL_BITS                       4
 #define EEE_USERB1_EEE_UP2_GROUP3_LEVEL_SHIFT                      0
 
 
 /****************************************************************************
  * EEE_UserB1 :: EEE_UP3
  */
 /* EEE_UserB1 :: EEE_UP3 :: reserved0 [15:04] */
 #define EEE_USERB1_EEE_UP3_RESERVED0_MASK                          0xfff0
 #define EEE_USERB1_EEE_UP3_RESERVED0_ALIGN                         0
 #define EEE_USERB1_EEE_UP3_RESERVED0_BITS                          12
 #define EEE_USERB1_EEE_UP3_RESERVED0_SHIFT                         4
 
 /* EEE_UserB1 :: EEE_UP3 :: Group5_Level [03:00] */
 #define EEE_USERB1_EEE_UP3_GROUP5_LEVEL_MASK                       0x000f
 #define EEE_USERB1_EEE_UP3_GROUP5_LEVEL_ALIGN                      0
 #define EEE_USERB1_EEE_UP3_GROUP5_LEVEL_BITS                       4
 #define EEE_USERB1_EEE_UP3_GROUP5_LEVEL_SHIFT                      0
 
 
 /****************************************************************************
  * EEE_UserB1 :: LP_EEE_UP1
  */
 /* EEE_UserB1 :: LP_EEE_UP1 :: reserved0 [15:11] */
 #define EEE_USERB1_LP_EEE_UP1_RESERVED0_MASK                       0xf800
 #define EEE_USERB1_LP_EEE_UP1_RESERVED0_ALIGN                      0
 #define EEE_USERB1_LP_EEE_UP1_RESERVED0_BITS                       5
 #define EEE_USERB1_LP_EEE_UP1_RESERVED0_SHIFT                      11
 
 /* EEE_UserB1 :: LP_EEE_UP1 :: LP_Group2_Level [10:07] */
 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP2_LEVEL_MASK                 0x0780
 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP2_LEVEL_ALIGN                0
 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP2_LEVEL_BITS                 4
 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP2_LEVEL_SHIFT                7
 
 /* EEE_UserB1 :: LP_EEE_UP1 :: LP_Group1_Level [06:03] */
 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP1_LEVEL_MASK                 0x0078
 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP1_LEVEL_ALIGN                0
 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP1_LEVEL_BITS                 4
 #define EEE_USERB1_LP_EEE_UP1_LP_GROUP1_LEVEL_SHIFT                3
 
 /* EEE_UserB1 :: LP_EEE_UP1 :: LP_cl73_override [02:02] */
 #define EEE_USERB1_LP_EEE_UP1_LP_CL73_OVERRIDE_MASK                0x0004
 #define EEE_USERB1_LP_EEE_UP1_LP_CL73_OVERRIDE_ALIGN               0
 #define EEE_USERB1_LP_EEE_UP1_LP_CL73_OVERRIDE_BITS                1
 #define EEE_USERB1_LP_EEE_UP1_LP_CL73_OVERRIDE_SHIFT               2
 
 /* EEE_UserB1 :: LP_EEE_UP1 :: LP_Pwrdn [01:01] */
 #define EEE_USERB1_LP_EEE_UP1_LP_PWRDN_MASK                        0x0002
 #define EEE_USERB1_LP_EEE_UP1_LP_PWRDN_ALIGN                       0
 #define EEE_USERB1_LP_EEE_UP1_LP_PWRDN_BITS                        1
 #define EEE_USERB1_LP_EEE_UP1_LP_PWRDN_SHIFT                       1
 
 /* EEE_UserB1 :: LP_EEE_UP1 :: LP_EEE [00:00] */
 #define EEE_USERB1_LP_EEE_UP1_LP_EEE_MASK                          0x0001
 #define EEE_USERB1_LP_EEE_UP1_LP_EEE_ALIGN                         0
 #define EEE_USERB1_LP_EEE_UP1_LP_EEE_BITS                          1
 #define EEE_USERB1_LP_EEE_UP1_LP_EEE_SHIFT                         0
 
 
 /****************************************************************************
  * EEE_UserB1 :: LP_EEE_UP2
  */
 /* EEE_UserB1 :: LP_EEE_UP2 :: reserved0 [15:08] */
 #define EEE_USERB1_LP_EEE_UP2_RESERVED0_MASK                       0xff00
 #define EEE_USERB1_LP_EEE_UP2_RESERVED0_ALIGN                      0
 #define EEE_USERB1_LP_EEE_UP2_RESERVED0_BITS                       8
 #define EEE_USERB1_LP_EEE_UP2_RESERVED0_SHIFT                      8
 
 /* EEE_UserB1 :: LP_EEE_UP2 :: LP_Group4_Level [07:04] */
 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP4_LEVEL_MASK                 0x00f0
 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP4_LEVEL_ALIGN                0
 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP4_LEVEL_BITS                 4
 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP4_LEVEL_SHIFT                4
 
 /* EEE_UserB1 :: LP_EEE_UP2 :: LP_Group3_Level [03:00] */
 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP3_LEVEL_MASK                 0x000f
 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP3_LEVEL_ALIGN                0
 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP3_LEVEL_BITS                 4
 #define EEE_USERB1_LP_EEE_UP2_LP_GROUP3_LEVEL_SHIFT                0
 
 
 /****************************************************************************
  * EEE_UserB1 :: LP_EEE_UP3
  */
 /* EEE_UserB1 :: LP_EEE_UP3 :: reserved0 [15:04] */
 #define EEE_USERB1_LP_EEE_UP3_RESERVED0_MASK                       0xfff0
 #define EEE_USERB1_LP_EEE_UP3_RESERVED0_ALIGN                      0
 #define EEE_USERB1_LP_EEE_UP3_RESERVED0_BITS                       12
 #define EEE_USERB1_LP_EEE_UP3_RESERVED0_SHIFT                      4
 
 /* EEE_UserB1 :: LP_EEE_UP3 :: LP_Group5_Level [03:00] */
 #define EEE_USERB1_LP_EEE_UP3_LP_GROUP5_LEVEL_MASK                 0x000f
 #define EEE_USERB1_LP_EEE_UP3_LP_GROUP5_LEVEL_ALIGN                0
 #define EEE_USERB1_LP_EEE_UP3_LP_GROUP5_LEVEL_BITS                 4
 #define EEE_USERB1_LP_EEE_UP3_LP_GROUP5_LEVEL_SHIFT                0
 
 
 /****************************************************************************
  * EEE_UserB1 :: EEE_RES_STATUS
  */
 /* EEE_UserB1 :: EEE_RES_STATUS :: EEE_RES_STATUS [15:00] */
 #define EEE_USERB1_EEE_RES_STATUS_EEE_RES_STATUS_MASK              0xffff
 #define EEE_USERB1_EEE_RES_STATUS_EEE_RES_STATUS_ALIGN             0
 #define EEE_USERB1_EEE_RES_STATUS_EEE_RES_STATUS_BITS              16
 #define EEE_USERB1_EEE_RES_STATUS_EEE_RES_STATUS_SHIFT             0
 
 
 /****************************************************************************
  * Warpcore_USER_tx66
  */
 /****************************************************************************
  * tx66 :: Control
  */
 /* tx66 :: Control :: fifo_spc_cya [15:15] */
 #define TX66_CONTROL_FIFO_SPC_CYA_MASK                             0x8000
 #define TX66_CONTROL_FIFO_SPC_CYA_ALIGN                            0
 #define TX66_CONTROL_FIFO_SPC_CYA_BITS                             1
 #define TX66_CONTROL_FIFO_SPC_CYA_SHIFT                            15
 
 /* tx66 :: Control :: scramblerControl_ovr [14:14] */
 #define TX66_CONTROL_SCRAMBLERCONTROL_OVR_MASK                     0x4000
 #define TX66_CONTROL_SCRAMBLERCONTROL_OVR_ALIGN                    0
 #define TX66_CONTROL_SCRAMBLERCONTROL_OVR_BITS                     1
 #define TX66_CONTROL_SCRAMBLERCONTROL_OVR_SHIFT                    14
 
 /* tx66 :: Control :: reserved0 [13:06] */
 #define TX66_CONTROL_RESERVED0_MASK                                0x3fc0
 #define TX66_CONTROL_RESERVED0_ALIGN                               0
 #define TX66_CONTROL_RESERVED0_BITS                                8
 #define TX66_CONTROL_RESERVED0_SHIFT                               6
 
 /* tx66 :: Control :: brcm_cl49_tx_fault_en [05:05] */
 #define TX66_CONTROL_BRCM_CL49_TX_FAULT_EN_MASK                    0x0020
 #define TX66_CONTROL_BRCM_CL49_TX_FAULT_EN_ALIGN                   0
 #define TX66_CONTROL_BRCM_CL49_TX_FAULT_EN_BITS                    1
 #define TX66_CONTROL_BRCM_CL49_TX_FAULT_EN_SHIFT                   5
 
 /* tx66 :: Control :: rloop_en [04:04] */
 #define TX66_CONTROL_RLOOP_EN_MASK                                 0x0010
 #define TX66_CONTROL_RLOOP_EN_ALIGN                                0
 #define TX66_CONTROL_RLOOP_EN_BITS                                 1
 #define TX66_CONTROL_RLOOP_EN_SHIFT                                4
 
 /* tx66 :: Control :: scramblerControl [03:02] */
 #define TX66_CONTROL_SCRAMBLERCONTROL_MASK                         0x000c
 #define TX66_CONTROL_SCRAMBLERCONTROL_ALIGN                        0
 #define TX66_CONTROL_SCRAMBLERCONTROL_BITS                         2
 #define TX66_CONTROL_SCRAMBLERCONTROL_SHIFT                        2
 
 /* tx66 :: Control :: tfifo_sbitclr [01:01] */
 #define TX66_CONTROL_TFIFO_SBITCLR_MASK                            0x0002
 #define TX66_CONTROL_TFIFO_SBITCLR_ALIGN                           0
 #define TX66_CONTROL_TFIFO_SBITCLR_BITS                            1
 #define TX66_CONTROL_TFIFO_SBITCLR_SHIFT                           1
 
 /* tx66 :: Control :: tfifo_afrst_en [00:00] */
 #define TX66_CONTROL_TFIFO_AFRST_EN_MASK                           0x0001
 #define TX66_CONTROL_TFIFO_AFRST_EN_ALIGN                          0
 #define TX66_CONTROL_TFIFO_AFRST_EN_BITS                           1
 #define TX66_CONTROL_TFIFO_AFRST_EN_SHIFT                          0
 
 
 /****************************************************************************
  * tx66 :: Status
  */
 /* tx66 :: Status :: reserved_for_eco0 [15:03] */
 #define TX66_STATUS_RESERVED_FOR_ECO0_MASK                         0xfff8
 #define TX66_STATUS_RESERVED_FOR_ECO0_ALIGN                        0
 #define TX66_STATUS_RESERVED_FOR_ECO0_BITS                         13
 #define TX66_STATUS_RESERVED_FOR_ECO0_SHIFT                        3
 
 /* tx66 :: Status :: ovflow [02:02] */
 #define TX66_STATUS_OVFLOW_MASK                                    0x0004
 #define TX66_STATUS_OVFLOW_ALIGN                                   0
 #define TX66_STATUS_OVFLOW_BITS                                    1
 #define TX66_STATUS_OVFLOW_SHIFT                                   2
 
 /* tx66 :: Status :: unflow [01:01] */
 #define TX66_STATUS_UNFLOW_MASK                                    0x0002
 #define TX66_STATUS_UNFLOW_ALIGN                                   0
 #define TX66_STATUS_UNFLOW_BITS                                    1
 #define TX66_STATUS_UNFLOW_SHIFT                                   1
 
 /* tx66 :: Status :: ferr [00:00] */
 #define TX66_STATUS_FERR_MASK                                      0x0001
 #define TX66_STATUS_FERR_ALIGN                                     0
 #define TX66_STATUS_FERR_BITS                                      1
 #define TX66_STATUS_FERR_SHIFT                                     0
 
 
 /****************************************************************************
  * tx66 :: Progmmable_TL
  */
 /* tx66 :: Progmmable_TL :: reserved_for_eco0 [15:09] */
 #define TX66_PROGMMABLE_TL_RESERVED_FOR_ECO0_MASK                  0xfe00
 #define TX66_PROGMMABLE_TL_RESERVED_FOR_ECO0_ALIGN                 0
 #define TX66_PROGMMABLE_TL_RESERVED_FOR_ECO0_BITS                  7
 #define TX66_PROGMMABLE_TL_RESERVED_FOR_ECO0_SHIFT                 9
 
 /* tx66 :: Progmmable_TL :: prog_tl_en [08:08] */
 #define TX66_PROGMMABLE_TL_PROG_TL_EN_MASK                         0x0100
 #define TX66_PROGMMABLE_TL_PROG_TL_EN_ALIGN                        0
 #define TX66_PROGMMABLE_TL_PROG_TL_EN_BITS                         1
 #define TX66_PROGMMABLE_TL_PROG_TL_EN_SHIFT                        8
 
 /* tx66 :: Progmmable_TL :: prog_tl_char [07:00] */
 #define TX66_PROGMMABLE_TL_PROG_TL_CHAR_MASK                       0x00ff
 #define TX66_PROGMMABLE_TL_PROG_TL_CHAR_ALIGN                      0
 #define TX66_PROGMMABLE_TL_PROG_TL_CHAR_BITS                       8
 #define TX66_PROGMMABLE_TL_PROG_TL_CHAR_SHIFT                      0
 
 
 /****************************************************************************
  * Warpcore_USER_rx66
  */
 /****************************************************************************
  * rx66 :: Control
  */
 /* rx66 :: Control :: fifo_spc_cya [15:15] */
 #define RX66_CONTROL_FIFO_SPC_CYA_MASK                             0x8000
 #define RX66_CONTROL_FIFO_SPC_CYA_ALIGN                            0
 #define RX66_CONTROL_FIFO_SPC_CYA_BITS                             1
 #define RX66_CONTROL_FIFO_SPC_CYA_SHIFT                            15
 
 /* rx66 :: Control :: cc_data_sel [14:14] */
 #define RX66_CONTROL_CC_DATA_SEL_MASK                              0x4000
 #define RX66_CONTROL_CC_DATA_SEL_ALIGN                             0
 #define RX66_CONTROL_CC_DATA_SEL_BITS                              1
 #define RX66_CONTROL_CC_DATA_SEL_SHIFT                             14
 
 /* rx66 :: Control :: cc_en [13:13] */
 #define RX66_CONTROL_CC_EN_MASK                                    0x2000
 #define RX66_CONTROL_CC_EN_ALIGN                                   0
 #define RX66_CONTROL_CC_EN_BITS                                    1
 #define RX66_CONTROL_CC_EN_SHIFT                                   13
 
 /* rx66 :: Control :: cc_afrst_en [12:12] */
 #define RX66_CONTROL_CC_AFRST_EN_MASK                              0x1000
 #define RX66_CONTROL_CC_AFRST_EN_ALIGN                             0
 #define RX66_CONTROL_CC_AFRST_EN_BITS                              1
 #define RX66_CONTROL_CC_AFRST_EN_SHIFT                             12
 
 /* rx66 :: Control :: cc_noIPG_en [11:11] */
 #define RX66_CONTROL_CC_NOIPG_EN_MASK                              0x0800
 #define RX66_CONTROL_CC_NOIPG_EN_ALIGN                             0
 #define RX66_CONTROL_CC_NOIPG_EN_BITS                              1
 #define RX66_CONTROL_CC_NOIPG_EN_SHIFT                             11
 
 /* rx66 :: Control :: cc_gt1_I_dis [10:10] */
 #define RX66_CONTROL_CC_GT1_I_DIS_MASK                             0x0400
 #define RX66_CONTROL_CC_GT1_I_DIS_ALIGN                            0
 #define RX66_CONTROL_CC_GT1_I_DIS_BITS                             1
 #define RX66_CONTROL_CC_GT1_I_DIS_SHIFT                            10
 
 /* rx66 :: Control :: rxSeqDoneMask [09:09] */
 #define RX66_CONTROL_RXSEQDONEMASK_MASK                            0x0200
 #define RX66_CONTROL_RXSEQDONEMASK_ALIGN                           0
 #define RX66_CONTROL_RXSEQDONEMASK_BITS                            1
 #define RX66_CONTROL_RXSEQDONEMASK_SHIFT                           9
 
 /* rx66 :: Control :: cwCount_sel [08:08] */
 #define RX66_CONTROL_CWCOUNT_SEL_MASK                              0x0100
 #define RX66_CONTROL_CWCOUNT_SEL_ALIGN                             0
 #define RX66_CONTROL_CWCOUNT_SEL_BITS                              1
 #define RX66_CONTROL_CWCOUNT_SEL_SHIFT                             8
 
 /* rx66 :: Control :: cwCount_en [07:07] */
 #define RX66_CONTROL_CWCOUNT_EN_MASK                               0x0080
 #define RX66_CONTROL_CWCOUNT_EN_ALIGN                              0
 #define RX66_CONTROL_CWCOUNT_EN_BITS                               1
 #define RX66_CONTROL_CWCOUNT_EN_SHIFT                              7
 
 /* rx66 :: Control :: sync66ErrCount_en [06:06] */
 #define RX66_CONTROL_SYNC66ERRCOUNT_EN_MASK                        0x0040
 #define RX66_CONTROL_SYNC66ERRCOUNT_EN_ALIGN                       0
 #define RX66_CONTROL_SYNC66ERRCOUNT_EN_BITS                        1
 #define RX66_CONTROL_SYNC66ERRCOUNT_EN_SHIFT                       6
 
 /* rx66 :: Control :: kcode66ErrCount_en [05:05] */
 #define RX66_CONTROL_KCODE66ERRCOUNT_EN_MASK                       0x0020
 #define RX66_CONTROL_KCODE66ERRCOUNT_EN_ALIGN                      0
 #define RX66_CONTROL_KCODE66ERRCOUNT_EN_BITS                       1
 #define RX66_CONTROL_KCODE66ERRCOUNT_EN_SHIFT                      5
 
 /* rx66 :: Control :: cgbad_kcode66Err_en [04:04] */
 #define RX66_CONTROL_CGBAD_KCODE66ERR_EN_MASK                      0x0010
 #define RX66_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN                     0
 #define RX66_CONTROL_CGBAD_KCODE66ERR_EN_BITS                      1
 #define RX66_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT                     4
 
 /* rx66 :: Control :: descramblerControl [03:02] */
 #define RX66_CONTROL_DESCRAMBLERCONTROL_MASK                       0x000c
 #define RX66_CONTROL_DESCRAMBLERCONTROL_ALIGN                      0
 #define RX66_CONTROL_DESCRAMBLERCONTROL_BITS                       2
 #define RX66_CONTROL_DESCRAMBLERCONTROL_SHIFT                      2
 
 /* rx66 :: Control :: rfifo_sbitclr [01:01] */
 #define RX66_CONTROL_RFIFO_SBITCLR_MASK                            0x0002
 #define RX66_CONTROL_RFIFO_SBITCLR_ALIGN                           0
 #define RX66_CONTROL_RFIFO_SBITCLR_BITS                            1
 #define RX66_CONTROL_RFIFO_SBITCLR_SHIFT                           1
 
 /* rx66 :: Control :: rfifo_afrst_en [00:00] */
 #define RX66_CONTROL_RFIFO_AFRST_EN_MASK                           0x0001
 #define RX66_CONTROL_RFIFO_AFRST_EN_ALIGN                          0
 #define RX66_CONTROL_RFIFO_AFRST_EN_BITS                           1
 #define RX66_CONTROL_RFIFO_AFRST_EN_SHIFT                          0
 
 
 /****************************************************************************
  * rx66 :: Status
  */
 /* rx66 :: Status :: LOSS_OF_SYNC [15:15] */
 #define RX66_STATUS_LOSS_OF_SYNC_MASK                              0x8000
 #define RX66_STATUS_LOSS_OF_SYNC_ALIGN                             0
 #define RX66_STATUS_LOSS_OF_SYNC_BITS                              1
 #define RX66_STATUS_LOSS_OF_SYNC_SHIFT                             15
 
 /* rx66 :: Status :: COMMA_DETECT [14:14] */
 #define RX66_STATUS_COMMA_DETECT_MASK                              0x4000
 #define RX66_STATUS_COMMA_DETECT_ALIGN                             0
 #define RX66_STATUS_COMMA_DETECT_BITS                              1
 #define RX66_STATUS_COMMA_DETECT_SHIFT                             14
 
 /* rx66 :: Status :: SYNC_ACQD1 [13:13] */
 #define RX66_STATUS_SYNC_ACQD1_MASK                                0x2000
 #define RX66_STATUS_SYNC_ACQD1_ALIGN                               0
 #define RX66_STATUS_SYNC_ACQD1_BITS                                1
 #define RX66_STATUS_SYNC_ACQD1_SHIFT                               13
 
 /* rx66 :: Status :: SYNC_ACQD2 [12:12] */
 #define RX66_STATUS_SYNC_ACQD2_MASK                                0x1000
 #define RX66_STATUS_SYNC_ACQD2_ALIGN                               0
 #define RX66_STATUS_SYNC_ACQD2_BITS                                1
 #define RX66_STATUS_SYNC_ACQD2_SHIFT                               12
 
 /* rx66 :: Status :: reserved0 [11:06] */
 #define RX66_STATUS_RESERVED0_MASK                                 0x0fc0
 #define RX66_STATUS_RESERVED0_ALIGN                                0
 #define RX66_STATUS_RESERVED0_BITS                                 6
 #define RX66_STATUS_RESERVED0_SHIFT                                6
 
 /* rx66 :: Status :: cc_ovflow [05:05] */
 #define RX66_STATUS_CC_OVFLOW_MASK                                 0x0020
 #define RX66_STATUS_CC_OVFLOW_ALIGN                                0
 #define RX66_STATUS_CC_OVFLOW_BITS                                 1
 #define RX66_STATUS_CC_OVFLOW_SHIFT                                5
 
 /* rx66 :: Status :: cc_unflow [04:04] */
 #define RX66_STATUS_CC_UNFLOW_MASK                                 0x0010
 #define RX66_STATUS_CC_UNFLOW_ALIGN                                0
 #define RX66_STATUS_CC_UNFLOW_BITS                                 1
 #define RX66_STATUS_CC_UNFLOW_SHIFT                                4
 
 /* rx66 :: Status :: syncDone [03:03] */
 #define RX66_STATUS_SYNCDONE_MASK                                  0x0008
 #define RX66_STATUS_SYNCDONE_ALIGN                                 0
 #define RX66_STATUS_SYNCDONE_BITS                                  1
 #define RX66_STATUS_SYNCDONE_SHIFT                                 3
 
 /* rx66 :: Status :: unflow [02:02] */
 #define RX66_STATUS_UNFLOW_MASK                                    0x0004
 #define RX66_STATUS_UNFLOW_ALIGN                                   0
 #define RX66_STATUS_UNFLOW_BITS                                    1
 #define RX66_STATUS_UNFLOW_SHIFT                                   2
 
 /* rx66 :: Status :: ovflow [01:01] */
 #define RX66_STATUS_OVFLOW_MASK                                    0x0002
 #define RX66_STATUS_OVFLOW_ALIGN                                   0
 #define RX66_STATUS_OVFLOW_BITS                                    1
 #define RX66_STATUS_OVFLOW_SHIFT                                   1
 
 /* rx66 :: Status :: ferr [00:00] */
 #define RX66_STATUS_FERR_MASK                                      0x0001
 #define RX66_STATUS_FERR_ALIGN                                     0
 #define RX66_STATUS_FERR_BITS                                      1
 #define RX66_STATUS_FERR_SHIFT                                     0
 
 
 /****************************************************************************
  * rx66 :: scw0
  */
 /* rx66 :: scw0 :: scw0 [15:00] */
 #define RX66_SCW0_SCW0_MASK                                        0xffff
 #define RX66_SCW0_SCW0_ALIGN                                       0
 #define RX66_SCW0_SCW0_BITS                                        16
 #define RX66_SCW0_SCW0_SHIFT                                       0
 
 
 /****************************************************************************
  * rx66 :: scw1
  */
 /* rx66 :: scw1 :: scw1 [15:00] */
 #define RX66_SCW1_SCW1_MASK                                        0xffff
 #define RX66_SCW1_SCW1_ALIGN                                       0
 #define RX66_SCW1_SCW1_BITS                                        16
 #define RX66_SCW1_SCW1_SHIFT                                       0
 
 
 /****************************************************************************
  * rx66 :: scw2
  */
 /* rx66 :: scw2 :: scw2 [15:00] */
 #define RX66_SCW2_SCW2_MASK                                        0xffff
 #define RX66_SCW2_SCW2_ALIGN                                       0
 #define RX66_SCW2_SCW2_BITS                                        16
 #define RX66_SCW2_SCW2_SHIFT                                       0
 
 
 /****************************************************************************
  * rx66 :: scw3
  */
 /* rx66 :: scw3 :: scw3 [15:00] */
 #define RX66_SCW3_SCW3_MASK                                        0xffff
 #define RX66_SCW3_SCW3_ALIGN                                       0
 #define RX66_SCW3_SCW3_BITS                                        16
 #define RX66_SCW3_SCW3_SHIFT                                       0
 
 
 /****************************************************************************
  * rx66 :: scw0_mask
  */
 /* rx66 :: scw0_mask :: scw0_mask [15:00] */
 #define RX66_SCW0_MASK_SCW0_MASK_MASK                              0xffff
 #define RX66_SCW0_MASK_SCW0_MASK_ALIGN                             0
 #define RX66_SCW0_MASK_SCW0_MASK_BITS                              16
 #define RX66_SCW0_MASK_SCW0_MASK_SHIFT                             0
 
 
 /****************************************************************************
  * rx66 :: scw1_mask
  */
 /* rx66 :: scw1_mask :: scw1_mask [15:00] */
 #define RX66_SCW1_MASK_SCW1_MASK_MASK                              0xffff
 #define RX66_SCW1_MASK_SCW1_MASK_ALIGN                             0
 #define RX66_SCW1_MASK_SCW1_MASK_BITS                              16
 #define RX66_SCW1_MASK_SCW1_MASK_SHIFT                             0
 
 
 /****************************************************************************
  * rx66 :: scw2_mask
  */
 /* rx66 :: scw2_mask :: scw2_mask [15:00] */
 #define RX66_SCW2_MASK_SCW2_MASK_MASK                              0xffff
 #define RX66_SCW2_MASK_SCW2_MASK_ALIGN                             0
 #define RX66_SCW2_MASK_SCW2_MASK_BITS                              16
 #define RX66_SCW2_MASK_SCW2_MASK_SHIFT                             0
 
 
 /****************************************************************************
  * rx66 :: scw3_mask
  */
 /* rx66 :: scw3_mask :: scw3_mask [15:00] */
 #define RX66_SCW3_MASK_SCW3_MASK_MASK                              0xffff
 #define RX66_SCW3_MASK_SCW3_MASK_ALIGN                             0
 #define RX66_SCW3_MASK_SCW3_MASK_BITS                              16
 #define RX66_SCW3_MASK_SCW3_MASK_SHIFT                             0
 
 
 /****************************************************************************
  * rx66 :: syncbits
  */
 /* rx66 :: syncbits :: cc_tmsel [15:13] */
 #define RX66_SYNCBITS_CC_TMSEL_MASK                                0xe000
 #define RX66_SYNCBITS_CC_TMSEL_ALIGN                               0
 #define RX66_SYNCBITS_CC_TMSEL_BITS                                3
 #define RX66_SYNCBITS_CC_TMSEL_SHIFT                               13
 
 /* rx66 :: syncbits :: prog_tl_en [12:12] */
 #define RX66_SYNCBITS_PROG_TL_EN_MASK                              0x1000
 #define RX66_SYNCBITS_PROG_TL_EN_ALIGN                             0
 #define RX66_SYNCBITS_PROG_TL_EN_BITS                              1
 #define RX66_SYNCBITS_PROG_TL_EN_SHIFT                             12
 
 /* rx66 :: syncbits :: prog_tl_char [11:04] */
 #define RX66_SYNCBITS_PROG_TL_CHAR_MASK                            0x0ff0
 #define RX66_SYNCBITS_PROG_TL_CHAR_ALIGN                           0
 #define RX66_SYNCBITS_PROG_TL_CHAR_BITS                            8
 #define RX66_SYNCBITS_PROG_TL_CHAR_SHIFT                           4
 
 /* rx66 :: syncbits :: syncbits [03:02] */
 #define RX66_SYNCBITS_SYNCBITS_MASK                                0x000c
 #define RX66_SYNCBITS_SYNCBITS_ALIGN                               0
 #define RX66_SYNCBITS_SYNCBITS_BITS                                2
 #define RX66_SYNCBITS_SYNCBITS_SHIFT                               2
 
 /* rx66 :: syncbits :: syncbits_mask [01:00] */
 #define RX66_SYNCBITS_SYNCBITS_MASK_MASK                           0x0003
 #define RX66_SYNCBITS_SYNCBITS_MASK_ALIGN                          0
 #define RX66_SYNCBITS_SYNCBITS_MASK_BITS                           2
 #define RX66_SYNCBITS_SYNCBITS_MASK_SHIFT                          0
 
 
 /****************************************************************************
  * rx66 :: scwControl
  */
 /* rx66 :: scwControl :: descramblerControl_ovr [15:15] */
 #define RX66_SCWCONTROL_DESCRAMBLERCONTROL_OVR_MASK                0x8000
 #define RX66_SCWCONTROL_DESCRAMBLERCONTROL_OVR_ALIGN               0
 #define RX66_SCWCONTROL_DESCRAMBLERCONTROL_OVR_BITS                1
 #define RX66_SCWCONTROL_DESCRAMBLERCONTROL_OVR_SHIFT               15
 
 /* rx66 :: scwControl :: scwCount [14:10] */
 #define RX66_SCWCONTROL_SCWCOUNT_MASK                              0x7c00
 #define RX66_SCWCONTROL_SCWCOUNT_ALIGN                             0
 #define RX66_SCWCONTROL_SCWCOUNT_BITS                              5
 #define RX66_SCWCONTROL_SCWCOUNT_SHIFT                             10
 
 /* rx66 :: scwControl :: gcwCount [09:05] */
 #define RX66_SCWCONTROL_GCWCOUNT_MASK                              0x03e0
 #define RX66_SCWCONTROL_GCWCOUNT_ALIGN                             0
 #define RX66_SCWCONTROL_GCWCOUNT_BITS                              5
 #define RX66_SCWCONTROL_GCWCOUNT_SHIFT                             5
 
 /* rx66 :: scwControl :: hystCount [04:00] */
 #define RX66_SCWCONTROL_HYSTCOUNT_MASK                             0x001f
 #define RX66_SCWCONTROL_HYSTCOUNT_ALIGN                            0
 #define RX66_SCWCONTROL_HYSTCOUNT_BITS                             5
 #define RX66_SCWCONTROL_HYSTCOUNT_SHIFT                            0
 
 
 /****************************************************************************
  * rx66 :: cc_eventCount
  */
 /* rx66 :: cc_eventCount :: cc_event_count [15:00] */
 #define RX66_CC_EVENTCOUNT_CC_EVENT_COUNT_MASK                     0xffff
 #define RX66_CC_EVENTCOUNT_CC_EVENT_COUNT_ALIGN                    0
 #define RX66_CC_EVENTCOUNT_CC_EVENT_COUNT_BITS                     16
 #define RX66_CC_EVENTCOUNT_CC_EVENT_COUNT_SHIFT                    0
 
 
 /****************************************************************************
  * rx66 :: scwCount
  */
 /* rx66 :: scwCount :: reserved0 [15:15] */
 #define RX66_SCWCOUNT_RESERVED0_MASK                               0x8000
 #define RX66_SCWCOUNT_RESERVED0_ALIGN                              0
 #define RX66_SCWCOUNT_RESERVED0_BITS                               1
 #define RX66_SCWCOUNT_RESERVED0_SHIFT                              15
 
 /* rx66 :: scwCount :: scwShift [14:08] */
 #define RX66_SCWCOUNT_SCWSHIFT_MASK                                0x7f00
 #define RX66_SCWCOUNT_SCWSHIFT_ALIGN                               0
 #define RX66_SCWCOUNT_SCWSHIFT_BITS                                7
 #define RX66_SCWCOUNT_SCWSHIFT_SHIFT                               8
 
 /* union - case COMMA_DETECT [07:00] */
 /* rx66 :: scwCount :: cwCount [07:00] */
 #define RX66_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK                    0x00ff
 #define RX66_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN                   0
 #define RX66_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS                    8
 #define RX66_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT                   0
 
 
 /* union - case SYNC_ACQD2 [07:00] */
 /* rx66 :: scwCount :: cwCount [07:00] */
 #define RX66_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK                      0x00ff
 #define RX66_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN                     0
 #define RX66_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS                      8
 #define RX66_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT                     0
 
 
 
 /****************************************************************************
  * rx66 :: errCount
  */
 /* rx66 :: errCount :: sync66ErrCount [15:08] */
 #define RX66_ERRCOUNT_SYNC66ERRCOUNT_MASK                          0xff00
 #define RX66_ERRCOUNT_SYNC66ERRCOUNT_ALIGN                         0
 #define RX66_ERRCOUNT_SYNC66ERRCOUNT_BITS                          8
 #define RX66_ERRCOUNT_SYNC66ERRCOUNT_SHIFT                         8
 
 /* rx66 :: errCount :: kcode66ErrCount [07:00] */
 #define RX66_ERRCOUNT_KCODE66ERRCOUNT_MASK                         0x00ff
 #define RX66_ERRCOUNT_KCODE66ERRCOUNT_ALIGN                        0
 #define RX66_ERRCOUNT_KCODE66ERRCOUNT_BITS                         8
 #define RX66_ERRCOUNT_KCODE66ERRCOUNT_SHIFT                        0
 
 
 /****************************************************************************
  * Warpcore_USER_LnTxBert
  */
 /****************************************************************************
  * LnTxBert :: txBertCtrl
  */
 /* LnTxBert :: txBertCtrl :: pkt_en [15:15] */
 #define LNTXBERT_TXBERTCTRL_PKT_EN_MASK                            0x8000
 #define LNTXBERT_TXBERTCTRL_PKT_EN_ALIGN                           0
 #define LNTXBERT_TXBERTCTRL_PKT_EN_BITS                            1
 #define LNTXBERT_TXBERTCTRL_PKT_EN_SHIFT                           15
 
 /* LnTxBert :: txBertCtrl :: seed_ld [14:14] */
 #define LNTXBERT_TXBERTCTRL_SEED_LD_MASK                           0x4000
 #define LNTXBERT_TXBERTCTRL_SEED_LD_ALIGN                          0
 #define LNTXBERT_TXBERTCTRL_SEED_LD_BITS                           1
 #define LNTXBERT_TXBERTCTRL_SEED_LD_SHIFT                          14
 
 /* LnTxBert :: txBertCtrl :: prbs_order [13:12] */
 #define LNTXBERT_TXBERTCTRL_PRBS_ORDER_MASK                        0x3000
 #define LNTXBERT_TXBERTCTRL_PRBS_ORDER_ALIGN                       0
 #define LNTXBERT_TXBERTCTRL_PRBS_ORDER_BITS                        2
 #define LNTXBERT_TXBERTCTRL_PRBS_ORDER_SHIFT                       12
 
 /* LnTxBert :: txBertCtrl :: ramp_en [11:11] */
 #define LNTXBERT_TXBERTCTRL_RAMP_EN_MASK                           0x0800
 #define LNTXBERT_TXBERTCTRL_RAMP_EN_ALIGN                          0
 #define LNTXBERT_TXBERTCTRL_RAMP_EN_BITS                           1
 #define LNTXBERT_TXBERTCTRL_RAMP_EN_SHIFT                          11
 
 /* LnTxBert :: txBertCtrl :: rndm_en [10:10] */
 #define LNTXBERT_TXBERTCTRL_RNDM_EN_MASK                           0x0400
 #define LNTXBERT_TXBERTCTRL_RNDM_EN_ALIGN                          0
 #define LNTXBERT_TXBERTCTRL_RNDM_EN_BITS                           1
 #define LNTXBERT_TXBERTCTRL_RNDM_EN_SHIFT                          10
 
 /* LnTxBert :: txBertCtrl :: Q_en [09:09] */
 #define LNTXBERT_TXBERTCTRL_Q_EN_MASK                              0x0200
 #define LNTXBERT_TXBERTCTRL_Q_EN_ALIGN                             0
 #define LNTXBERT_TXBERTCTRL_Q_EN_BITS                              1
 #define LNTXBERT_TXBERTCTRL_Q_EN_SHIFT                             9
 
 /* LnTxBert :: txBertCtrl :: Q_link_en [08:08] */
 #define LNTXBERT_TXBERTCTRL_Q_LINK_EN_MASK                         0x0100
 #define LNTXBERT_TXBERTCTRL_Q_LINK_EN_ALIGN                        0
 #define LNTXBERT_TXBERTCTRL_Q_LINK_EN_BITS                         1
 #define LNTXBERT_TXBERTCTRL_Q_LINK_EN_SHIFT                        8
 
 /* LnTxBert :: txBertCtrl :: skew_en [07:07] */
 #define LNTXBERT_TXBERTCTRL_SKEW_EN_MASK                           0x0080
 #define LNTXBERT_TXBERTCTRL_SKEW_EN_ALIGN                          0
 #define LNTXBERT_TXBERTCTRL_SKEW_EN_BITS                           1
 #define LNTXBERT_TXBERTCTRL_SKEW_EN_SHIFT                          7
 
 /* LnTxBert :: txBertCtrl :: cjpat_en [06:06] */
 #define LNTXBERT_TXBERTCTRL_CJPAT_EN_MASK                          0x0040
 #define LNTXBERT_TXBERTCTRL_CJPAT_EN_ALIGN                         0
 #define LNTXBERT_TXBERTCTRL_CJPAT_EN_BITS                          1
 #define LNTXBERT_TXBERTCTRL_CJPAT_EN_SHIFT                         6
 
 /* LnTxBert :: txBertCtrl :: crpat_en [05:05] */
 #define LNTXBERT_TXBERTCTRL_CRPAT_EN_MASK                          0x0020
 #define LNTXBERT_TXBERTCTRL_CRPAT_EN_ALIGN                         0
 #define LNTXBERT_TXBERTCTRL_CRPAT_EN_BITS                          1
 #define LNTXBERT_TXBERTCTRL_CRPAT_EN_SHIFT                         5
 
 /* LnTxBert :: txBertCtrl :: cjrmp_en [04:04] */
 #define LNTXBERT_TXBERTCTRL_CJRMP_EN_MASK                          0x0010
 #define LNTXBERT_TXBERTCTRL_CJRMP_EN_ALIGN                         0
 #define LNTXBERT_TXBERTCTRL_CJRMP_EN_BITS                          1
 #define LNTXBERT_TXBERTCTRL_CJRMP_EN_SHIFT                         4
 
 /* LnTxBert :: txBertCtrl :: txck_out_force [03:03] */
 #define LNTXBERT_TXBERTCTRL_TXCK_OUT_FORCE_MASK                    0x0008
 #define LNTXBERT_TXBERTCTRL_TXCK_OUT_FORCE_ALIGN                   0
 #define LNTXBERT_TXBERTCTRL_TXCK_OUT_FORCE_BITS                    1
 #define LNTXBERT_TXBERTCTRL_TXCK_OUT_FORCE_SHIFT                   3
 
 /* LnTxBert :: txBertCtrl :: fifo_rst [02:02] */
 #define LNTXBERT_TXBERTCTRL_FIFO_RST_MASK                          0x0004
 #define LNTXBERT_TXBERTCTRL_FIFO_RST_ALIGN                         0
 #define LNTXBERT_TXBERTCTRL_FIFO_RST_BITS                          1
 #define LNTXBERT_TXBERTCTRL_FIFO_RST_SHIFT                         2
 
 /* LnTxBert :: txBertCtrl :: countRst_dis [01:01] */
 #define LNTXBERT_TXBERTCTRL_COUNTRST_DIS_MASK                      0x0002
 #define LNTXBERT_TXBERTCTRL_COUNTRST_DIS_ALIGN                     0
 #define LNTXBERT_TXBERTCTRL_COUNTRST_DIS_BITS                      1
 #define LNTXBERT_TXBERTCTRL_COUNTRST_DIS_SHIFT                     1
 
 /* LnTxBert :: txBertCtrl :: count_clr [00:00] */
 #define LNTXBERT_TXBERTCTRL_COUNT_CLR_MASK                         0x0001
 #define LNTXBERT_TXBERTCTRL_COUNT_CLR_ALIGN                        0
 #define LNTXBERT_TXBERTCTRL_COUNT_CLR_BITS                         1
 #define LNTXBERT_TXBERTCTRL_COUNT_CLR_SHIFT                        0
 
 
 /****************************************************************************
  * LnTxBert :: txBertSopEop
  */
 /* LnTxBert :: txBertSopEop :: SOP [15:08] */
 #define LNTXBERT_TXBERTSOPEOP_SOP_MASK                             0xff00
 #define LNTXBERT_TXBERTSOPEOP_SOP_ALIGN                            0
 #define LNTXBERT_TXBERTSOPEOP_SOP_BITS                             8
 #define LNTXBERT_TXBERTSOPEOP_SOP_SHIFT                            8
 
 /* LnTxBert :: txBertSopEop :: EOP [07:00] */
 #define LNTXBERT_TXBERTSOPEOP_EOP_MASK                             0x00ff
 #define LNTXBERT_TXBERTSOPEOP_EOP_ALIGN                            0
 #define LNTXBERT_TXBERTSOPEOP_EOP_BITS                             8
 #define LNTXBERT_TXBERTSOPEOP_EOP_SHIFT                            0
 
 
 /****************************************************************************
  * LnTxBert :: txBertSize0
  */
 /* LnTxBert :: txBertSize0 :: ipg_size [15:10] */
 #define LNTXBERT_TXBERTSIZE0_IPG_SIZE_MASK                         0xfc00
 #define LNTXBERT_TXBERTSIZE0_IPG_SIZE_ALIGN                        0
 #define LNTXBERT_TXBERTSIZE0_IPG_SIZE_BITS                         6
 #define LNTXBERT_TXBERTSIZE0_IPG_SIZE_SHIFT                        10
 
 /* LnTxBert :: txBertSize0 :: pkt_size [09:00] */
 #define LNTXBERT_TXBERTSIZE0_PKT_SIZE_MASK                         0x03ff
 #define LNTXBERT_TXBERTSIZE0_PKT_SIZE_ALIGN                        0
 #define LNTXBERT_TXBERTSIZE0_PKT_SIZE_BITS                         10
 #define LNTXBERT_TXBERTSIZE0_PKT_SIZE_SHIFT                        0
 
 
 /****************************************************************************
  * LnTxBert :: txBertSize1
  */
 /* LnTxBert :: txBertSize1 :: awin_size [15:10] */
 #define LNTXBERT_TXBERTSIZE1_AWIN_SIZE_MASK                        0xfc00
 #define LNTXBERT_TXBERTSIZE1_AWIN_SIZE_ALIGN                       0
 #define LNTXBERT_TXBERTSIZE1_AWIN_SIZE_BITS                        6
 #define LNTXBERT_TXBERTSIZE1_AWIN_SIZE_SHIFT                       10
 
 /* LnTxBert :: txBertSize1 :: PktStpCnt [09:00] */
 #define LNTXBERT_TXBERTSIZE1_PKTSTPCNT_MASK                        0x03ff
 #define LNTXBERT_TXBERTSIZE1_PKTSTPCNT_ALIGN                       0
 #define LNTXBERT_TXBERTSIZE1_PKTSTPCNT_BITS                        10
 #define LNTXBERT_TXBERTSIZE1_PKTSTPCNT_SHIFT                       0
 
 
 /****************************************************************************
  * LnTxBert :: txBertSize2
  */
 /* LnTxBert :: txBertSize2 :: skew3 [15:12] */
 #define LNTXBERT_TXBERTSIZE2_SKEW3_MASK                            0xf000
 #define LNTXBERT_TXBERTSIZE2_SKEW3_ALIGN                           0
 #define LNTXBERT_TXBERTSIZE2_SKEW3_BITS                            4
 #define LNTXBERT_TXBERTSIZE2_SKEW3_SHIFT                           12
 
 /* LnTxBert :: txBertSize2 :: skew2 [11:08] */
 #define LNTXBERT_TXBERTSIZE2_SKEW2_MASK                            0x0f00
 #define LNTXBERT_TXBERTSIZE2_SKEW2_ALIGN                           0
 #define LNTXBERT_TXBERTSIZE2_SKEW2_BITS                            4
 #define LNTXBERT_TXBERTSIZE2_SKEW2_SHIFT                           8
 
 /* LnTxBert :: txBertSize2 :: skew1 [07:04] */
 #define LNTXBERT_TXBERTSIZE2_SKEW1_MASK                            0x00f0
 #define LNTXBERT_TXBERTSIZE2_SKEW1_ALIGN                           0
 #define LNTXBERT_TXBERTSIZE2_SKEW1_BITS                            4
 #define LNTXBERT_TXBERTSIZE2_SKEW1_SHIFT                           4
 
 /* LnTxBert :: txBertSize2 :: skew0 [03:00] */
 #define LNTXBERT_TXBERTSIZE2_SKEW0_MASK                            0x000f
 #define LNTXBERT_TXBERTSIZE2_SKEW0_ALIGN                           0
 #define LNTXBERT_TXBERTSIZE2_SKEW0_BITS                            4
 #define LNTXBERT_TXBERTSIZE2_SKEW0_SHIFT                           0
 
 
 /****************************************************************************
  * LnTxBert :: txBertIpg0
  */
 /* LnTxBert :: txBertIpg0 :: ipg1 [15:08] */
 #define LNTXBERT_TXBERTIPG0_IPG1_MASK                              0xff00
 #define LNTXBERT_TXBERTIPG0_IPG1_ALIGN                             0
 #define LNTXBERT_TXBERTIPG0_IPG1_BITS                              8
 #define LNTXBERT_TXBERTIPG0_IPG1_SHIFT                             8
 
 /* LnTxBert :: txBertIpg0 :: ipg0 [07:00] */
 #define LNTXBERT_TXBERTIPG0_IPG0_MASK                              0x00ff
 #define LNTXBERT_TXBERTIPG0_IPG0_ALIGN                             0
 #define LNTXBERT_TXBERTIPG0_IPG0_BITS                              8
 #define LNTXBERT_TXBERTIPG0_IPG0_SHIFT                             0
 
 
 /****************************************************************************
  * LnTxBert :: txBertIpg1
  */
 /* LnTxBert :: txBertIpg1 :: ipg3 [15:08] */
 #define LNTXBERT_TXBERTIPG1_IPG3_MASK                              0xff00
 #define LNTXBERT_TXBERTIPG1_IPG3_ALIGN                             0
 #define LNTXBERT_TXBERTIPG1_IPG3_BITS                              8
 #define LNTXBERT_TXBERTIPG1_IPG3_SHIFT                             8
 
 /* LnTxBert :: txBertIpg1 :: ipg2 [07:00] */
 #define LNTXBERT_TXBERTIPG1_IPG2_MASK                              0x00ff
 #define LNTXBERT_TXBERTIPG1_IPG2_ALIGN                             0
 #define LNTXBERT_TXBERTIPG1_IPG2_BITS                              8
 #define LNTXBERT_TXBERTIPG1_IPG2_SHIFT                             0
 
 
 /****************************************************************************
  * LnTxBert :: txBertByteU
  */
 /* LnTxBert :: txBertByteU :: byte_count_high [15:00] */
 #define LNTXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_MASK                  0xffff
 #define LNTXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN                 0
 #define LNTXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_BITS                  16
 #define LNTXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT                 0
 
 
 /****************************************************************************
  * LnTxBert :: txBertByteL
  */
 /* LnTxBert :: txBertByteL :: byte_count_low [15:00] */
 #define LNTXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_MASK                   0xffff
 #define LNTXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_ALIGN                  0
 #define LNTXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_BITS                   16
 #define LNTXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_SHIFT                  0
 
 
 /****************************************************************************
  * LnTxBert :: txBertPacketU
  */
 /* LnTxBert :: txBertPacketU :: pkt_count_high [15:00] */
 #define LNTXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_MASK                 0xffff
 #define LNTXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_ALIGN                0
 #define LNTXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_BITS                 16
 #define LNTXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_SHIFT                0
 
 
 /****************************************************************************
  * LnTxBert :: txBertPacketL
  */
 /* LnTxBert :: txBertPacketL :: pkt_count_low [15:00] */
 #define LNTXBERT_TXBERTPACKETL_PKT_COUNT_LOW_MASK                  0xffff
 #define LNTXBERT_TXBERTPACKETL_PKT_COUNT_LOW_ALIGN                 0
 #define LNTXBERT_TXBERTPACKETL_PKT_COUNT_LOW_BITS                  16
 #define LNTXBERT_TXBERTPACKETL_PKT_COUNT_LOW_SHIFT                 0
 
 
 /****************************************************************************
  * LnTxBert :: txBertCtrl1
  */
 /* LnTxBert :: txBertCtrl1 :: reserved0 [15:01] */
 #define LNTXBERT_TXBERTCTRL1_RESERVED0_MASK                        0xfffe
 #define LNTXBERT_TXBERTCTRL1_RESERVED0_ALIGN                       0
 #define LNTXBERT_TXBERTCTRL1_RESERVED0_BITS                        15
 #define LNTXBERT_TXBERTCTRL1_RESERVED0_SHIFT                       1
 
 /* LnTxBert :: txBertCtrl1 :: lpi_en [00:00] */
 #define LNTXBERT_TXBERTCTRL1_LPI_EN_MASK                           0x0001
 #define LNTXBERT_TXBERTCTRL1_LPI_EN_ALIGN                          0
 #define LNTXBERT_TXBERTCTRL1_LPI_EN_BITS                           1
 #define LNTXBERT_TXBERTCTRL1_LPI_EN_SHIFT                          0
 
 
 /****************************************************************************
  * Warpcore_USER_LnRxBert
  */
 /****************************************************************************
  * LnRxBert :: rxBertCtrl
  */
 /* LnRxBert :: rxBertCtrl :: pkt_en [15:15] */
 #define LNRXBERT_RXBERTCTRL_PKT_EN_MASK                            0x8000
 #define LNRXBERT_RXBERTCTRL_PKT_EN_ALIGN                           0
 #define LNRXBERT_RXBERTCTRL_PKT_EN_BITS                            1
 #define LNRXBERT_RXBERTCTRL_PKT_EN_SHIFT                           15
 
 /* LnRxBert :: rxBertCtrl :: seed_ld [14:14] */
 #define LNRXBERT_RXBERTCTRL_SEED_LD_MASK                           0x4000
 #define LNRXBERT_RXBERTCTRL_SEED_LD_ALIGN                          0
 #define LNRXBERT_RXBERTCTRL_SEED_LD_BITS                           1
 #define LNRXBERT_RXBERTCTRL_SEED_LD_SHIFT                          14
 
 /* LnRxBert :: rxBertCtrl :: prbs_order [13:12] */
 #define LNRXBERT_RXBERTCTRL_PRBS_ORDER_MASK                        0x3000
 #define LNRXBERT_RXBERTCTRL_PRBS_ORDER_ALIGN                       0
 #define LNRXBERT_RXBERTCTRL_PRBS_ORDER_BITS                        2
 #define LNRXBERT_RXBERTCTRL_PRBS_ORDER_SHIFT                       12
 
 /* LnRxBert :: rxBertCtrl :: ramp_en [11:11] */
 #define LNRXBERT_RXBERTCTRL_RAMP_EN_MASK                           0x0800
 #define LNRXBERT_RXBERTCTRL_RAMP_EN_ALIGN                          0
 #define LNRXBERT_RXBERTCTRL_RAMP_EN_BITS                           1
 #define LNRXBERT_RXBERTCTRL_RAMP_EN_SHIFT                          11
 
 /* LnRxBert :: rxBertCtrl :: cgbad_tst_en [10:10] */
 #define LNRXBERT_RXBERTCTRL_CGBAD_TST_EN_MASK                      0x0400
 #define LNRXBERT_RXBERTCTRL_CGBAD_TST_EN_ALIGN                     0
 #define LNRXBERT_RXBERTCTRL_CGBAD_TST_EN_BITS                      1
 #define LNRXBERT_RXBERTCTRL_CGBAD_TST_EN_SHIFT                     10
 
 /* LnRxBert :: rxBertCtrl :: crcChk_en [09:09] */
 #define LNRXBERT_RXBERTCTRL_CRCCHK_EN_MASK                         0x0200
 #define LNRXBERT_RXBERTCTRL_CRCCHK_EN_ALIGN                        0
 #define LNRXBERT_RXBERTCTRL_CRCCHK_EN_BITS                         1
 #define LNRXBERT_RXBERTCTRL_CRCCHK_EN_SHIFT                        9
 
 /* LnRxBert :: rxBertCtrl :: countRst_dis [08:08] */
 #define LNRXBERT_RXBERTCTRL_COUNTRST_DIS_MASK                      0x0100
 #define LNRXBERT_RXBERTCTRL_COUNTRST_DIS_ALIGN                     0
 #define LNRXBERT_RXBERTCTRL_COUNTRST_DIS_BITS                      1
 #define LNRXBERT_RXBERTCTRL_COUNTRST_DIS_SHIFT                     8
 
 /* LnRxBert :: rxBertCtrl :: rxStatSel [07:07] */
 #define LNRXBERT_RXBERTCTRL_RXSTATSEL_MASK                         0x0080
 #define LNRXBERT_RXBERTCTRL_RXSTATSEL_ALIGN                        0
 #define LNRXBERT_RXBERTCTRL_RXSTATSEL_BITS                         1
 #define LNRXBERT_RXBERTCTRL_RXSTATSEL_SHIFT                        7
 
 /* LnRxBert :: rxBertCtrl :: source_sel_r [06:06] */
 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_R_MASK                      0x0040
 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_R_ALIGN                     0
 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_R_BITS                      1
 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_R_SHIFT                     6
 
 /* LnRxBert :: rxBertCtrl :: source_sel [05:04] */
 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_MASK                        0x0030
 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_ALIGN                       0
 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_BITS                        2
 #define LNRXBERT_RXBERTCTRL_SOURCE_SEL_SHIFT                       4
 
 /* LnRxBert :: rxBertCtrl :: slice_sel [03:02] */
 #define LNRXBERT_RXBERTCTRL_SLICE_SEL_MASK                         0x000c
 #define LNRXBERT_RXBERTCTRL_SLICE_SEL_ALIGN                        0
 #define LNRXBERT_RXBERTCTRL_SLICE_SEL_BITS                         2
 #define LNRXBERT_RXBERTCTRL_SLICE_SEL_SHIFT                        2
 
 /* LnRxBert :: rxBertCtrl :: err_clr [01:01] */
 #define LNRXBERT_RXBERTCTRL_ERR_CLR_MASK                           0x0002
 #define LNRXBERT_RXBERTCTRL_ERR_CLR_ALIGN                          0
 #define LNRXBERT_RXBERTCTRL_ERR_CLR_BITS                           1
 #define LNRXBERT_RXBERTCTRL_ERR_CLR_SHIFT                          1
 
 /* LnRxBert :: rxBertCtrl :: count_clr [00:00] */
 #define LNRXBERT_RXBERTCTRL_COUNT_CLR_MASK                         0x0001
 #define LNRXBERT_RXBERTCTRL_COUNT_CLR_ALIGN                        0
 #define LNRXBERT_RXBERTCTRL_COUNT_CLR_BITS                         1
 #define LNRXBERT_RXBERTCTRL_COUNT_CLR_SHIFT                        0
 
 
 /****************************************************************************
  * LnRxBert :: rxBertSopEop
  */
 /* LnRxBert :: rxBertSopEop :: SOP [15:08] */
 #define LNRXBERT_RXBERTSOPEOP_SOP_MASK                             0xff00
 #define LNRXBERT_RXBERTSOPEOP_SOP_ALIGN                            0
 #define LNRXBERT_RXBERTSOPEOP_SOP_BITS                             8
 #define LNRXBERT_RXBERTSOPEOP_SOP_SHIFT                            8
 
 /* LnRxBert :: rxBertSopEop :: EOP [07:00] */
 #define LNRXBERT_RXBERTSOPEOP_EOP_MASK                             0x00ff
 #define LNRXBERT_RXBERTSOPEOP_EOP_ALIGN                            0
 #define LNRXBERT_RXBERTSOPEOP_EOP_BITS                             8
 #define LNRXBERT_RXBERTSOPEOP_EOP_SHIFT                            0
 
 
 /****************************************************************************
  * LnRxBert :: rxBertByteU
  */
 /* LnRxBert :: rxBertByteU :: byte_count_high [15:00] */
 #define LNRXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_MASK                  0xffff
 #define LNRXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN                 0
 #define LNRXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_BITS                  16
 #define LNRXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT                 0
 
 
 /****************************************************************************
  * LnRxBert :: rxBertByteL
  */
 /* LnRxBert :: rxBertByteL :: byte_count_low [15:00] */
 #define LNRXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_MASK                   0xffff
 #define LNRXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_ALIGN                  0
 #define LNRXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_BITS                   16
 #define LNRXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_SHIFT                  0
 
 
 /****************************************************************************
  * LnRxBert :: rxBertPacketU
  */
 /* LnRxBert :: rxBertPacketU :: pkt_count_high [15:00] */
 #define LNRXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_MASK                 0xffff
 #define LNRXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_ALIGN                0
 #define LNRXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_BITS                 16
 #define LNRXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_SHIFT                0
 
 
 /****************************************************************************
  * LnRxBert :: rxBertPacketL
  */
 /* LnRxBert :: rxBertPacketL :: pkt_count_low [15:00] */
 #define LNRXBERT_RXBERTPACKETL_PKT_COUNT_LOW_MASK                  0xffff
 #define LNRXBERT_RXBERTPACKETL_PKT_COUNT_LOW_ALIGN                 0
 #define LNRXBERT_RXBERTPACKETL_PKT_COUNT_LOW_BITS                  16
 #define LNRXBERT_RXBERTPACKETL_PKT_COUNT_LOW_SHIFT                 0
 
 
 /****************************************************************************
  * LnRxBert :: rxBertBitErr
  */
 /* LnRxBert :: rxBertBitErr :: bit_err_count [15:00] */
 #define LNRXBERT_RXBERTBITERR_BIT_ERR_COUNT_MASK                   0xffff
 #define LNRXBERT_RXBERTBITERR_BIT_ERR_COUNT_ALIGN                  0
 #define LNRXBERT_RXBERTBITERR_BIT_ERR_COUNT_BITS                   16
 #define LNRXBERT_RXBERTBITERR_BIT_ERR_COUNT_SHIFT                  0
 
 
 /****************************************************************************
  * LnRxBert :: rxBertByteErr
  */
 /* LnRxBert :: rxBertByteErr :: byte_err_count [15:00] */
 #define LNRXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_MASK                 0xffff
 #define LNRXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_ALIGN                0
 #define LNRXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_BITS                 16
 #define LNRXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_SHIFT                0
 
 
 /****************************************************************************
  * LnRxBert :: rxBertPktErr
  */
 /* LnRxBert :: rxBertPktErr :: pkt_err_count [15:00] */
 #define LNRXBERT_RXBERTPKTERR_PKT_ERR_COUNT_MASK                   0xffff
 #define LNRXBERT_RXBERTPKTERR_PKT_ERR_COUNT_ALIGN                  0
 #define LNRXBERT_RXBERTPKTERR_PKT_ERR_COUNT_BITS                   16
 #define LNRXBERT_RXBERTPKTERR_PKT_ERR_COUNT_SHIFT                  0
 
 
 /****************************************************************************
  * LnRxBert :: rxBertStatus
  */
 /* union - case rxStatSel [15:00] */
 /* LnRxBert :: rxBertStatus :: reserved0 [15:08] */
 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_MASK             0xff00
 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_ALIGN            0
 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_BITS             8
 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_SHIFT            8
 
 /* LnRxBert :: rxBertStatus :: rx_10g_tmux [07:00] */
 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_MASK           0x00ff
 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_ALIGN          0
 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_BITS           8
 #define LNRXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_SHIFT          0
 
 
 /* union - case crcChk_en [15:00] */
 /* LnRxBert :: rxBertStatus :: link [15:15] */
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_MASK                  0x8000
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_ALIGN                 0
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_BITS                  1
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_SHIFT                 15
 
 /* LnRxBert :: rxBertStatus :: prbs_stky [14:14] */
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_MASK             0x4000
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_ALIGN            0
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_BITS             1
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_SHIFT            14
 
 /* LnRxBert :: rxBertStatus :: reserved0 [13:00] */
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_MASK             0x3fff
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_ALIGN            0
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_BITS             14
 #define LNRXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_SHIFT            0
 
 
 /* union - case rxBert [15:00] */
 /* LnRxBert :: rxBertStatus :: prbs_lock [15:15] */
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_MASK                0x8000
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_ALIGN               0
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_BITS                1
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_SHIFT               15
 
 /* LnRxBert :: rxBertStatus :: prbs_stky [14:14] */
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_MASK                0x4000
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_ALIGN               0
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_BITS                1
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_SHIFT               14
 
 /* LnRxBert :: rxBertStatus :: prbs_state [13:11] */
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_MASK               0x3800
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_ALIGN              0
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_BITS               3
 #define LNRXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_SHIFT              11
 
 /* LnRxBert :: rxBertStatus :: reserved0 [10:07] */
 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED0_MASK                0x0780
 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED0_ALIGN               0
 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED0_BITS                4
 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED0_SHIFT               7
 
 /* LnRxBert :: rxBertStatus :: bit_err_overflow [06:06] */
 #define LNRXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_MASK         0x0040
 #define LNRXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_ALIGN        0
 #define LNRXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_BITS         1
 #define LNRXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_SHIFT        6
 
 /* LnRxBert :: rxBertStatus :: reserved1 [05:04] */
 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED1_MASK                0x0030
 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED1_ALIGN               0
 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED1_BITS                2
 #define LNRXBERT_RXBERTSTATUS_RXBERT_RESERVED1_SHIFT               4
 
 /* LnRxBert :: rxBertStatus :: onefe_det [03:03] */
 #define LNRXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_MASK                0x0008
 #define LNRXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_ALIGN               0
 #define LNRXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_BITS                1
 #define LNRXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_SHIFT               3
 
 /* LnRxBert :: rxBertStatus :: xor_comp [02:00] */
 #define LNRXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_MASK                 0x0007
 #define LNRXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_ALIGN                0
 #define LNRXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_BITS                 3
 #define LNRXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_SHIFT                0
 
 
 
 /****************************************************************************
  * Warpcore_USER_FX100
  */
 /****************************************************************************
  * FX100 :: Control1
  */
 /* FX100 :: Control1 :: data_sampler_en [15:15] */
 #define FX100_CONTROL1_DATA_SAMPLER_EN_MASK                        0x8000
 #define FX100_CONTROL1_DATA_SAMPLER_EN_ALIGN                       0
 #define FX100_CONTROL1_DATA_SAMPLER_EN_BITS                        1
 #define FX100_CONTROL1_DATA_SAMPLER_EN_SHIFT                       15
 
 /* FX100 :: Control1 :: reserved0 [14:10] */
 #define FX100_CONTROL1_RESERVED0_MASK                              0x7c00
 #define FX100_CONTROL1_RESERVED0_ALIGN                             0
 #define FX100_CONTROL1_RESERVED0_BITS                              5
 #define FX100_CONTROL1_RESERVED0_SHIFT                             10
 
 /* FX100 :: Control1 :: rxdata_sel [09:06] */
 #define FX100_CONTROL1_RXDATA_SEL_MASK                             0x03c0
 #define FX100_CONTROL1_RXDATA_SEL_ALIGN                            0
 #define FX100_CONTROL1_RXDATA_SEL_BITS                             4
 #define FX100_CONTROL1_RXDATA_SEL_SHIFT                            6
 
 /* FX100 :: Control1 :: disable_rx_qual [05:05] */
 #define FX100_CONTROL1_DISABLE_RX_QUAL_MASK                        0x0020
 #define FX100_CONTROL1_DISABLE_RX_QUAL_ALIGN                       0
 #define FX100_CONTROL1_DISABLE_RX_QUAL_BITS                        1
 #define FX100_CONTROL1_DISABLE_RX_QUAL_SHIFT                       5
 
 /* FX100 :: Control1 :: force_rx_qual [04:04] */
 #define FX100_CONTROL1_FORCE_RX_QUAL_MASK                          0x0010
 #define FX100_CONTROL1_FORCE_RX_QUAL_ALIGN                         0
 #define FX100_CONTROL1_FORCE_RX_QUAL_BITS                          1
 #define FX100_CONTROL1_FORCE_RX_QUAL_SHIFT                         4
 
 /* FX100 :: Control1 :: far_end_fault_en [03:03] */
 #define FX100_CONTROL1_FAR_END_FAULT_EN_MASK                       0x0008
 #define FX100_CONTROL1_FAR_END_FAULT_EN_ALIGN                      0
 #define FX100_CONTROL1_FAR_END_FAULT_EN_BITS                       1
 #define FX100_CONTROL1_FAR_END_FAULT_EN_SHIFT                      3
 
 /* FX100 :: Control1 :: reserved1 [02:02] */
 #define FX100_CONTROL1_RESERVED1_MASK                              0x0004
 #define FX100_CONTROL1_RESERVED1_ALIGN                             0
 #define FX100_CONTROL1_RESERVED1_BITS                              1
 #define FX100_CONTROL1_RESERVED1_SHIFT                             2
 
 /* FX100 :: Control1 :: full_duplex [01:01] */
 #define FX100_CONTROL1_FULL_DUPLEX_MASK                            0x0002
 #define FX100_CONTROL1_FULL_DUPLEX_ALIGN                           0
 #define FX100_CONTROL1_FULL_DUPLEX_BITS                            1
 #define FX100_CONTROL1_FULL_DUPLEX_SHIFT                           1
 
 /* FX100 :: Control1 :: enable [00:00] */
 #define FX100_CONTROL1_ENABLE_MASK                                 0x0001
 #define FX100_CONTROL1_ENABLE_ALIGN                                0
 #define FX100_CONTROL1_ENABLE_BITS                                 1
 #define FX100_CONTROL1_ENABLE_SHIFT                                0
 
 
 /****************************************************************************
  * FX100 :: Control2
  */
 /* FX100 :: Control2 :: reserved0 [15:12] */
 #define FX100_CONTROL2_RESERVED0_MASK                              0xf000
 #define FX100_CONTROL2_RESERVED0_ALIGN                             0
 #define FX100_CONTROL2_RESERVED0_BITS                              4
 #define FX100_CONTROL2_RESERVED0_SHIFT                             12
 
 /* FX100 :: Control2 :: ping_pong_disable [11:11] */
 #define FX100_CONTROL2_PING_PONG_DISABLE_MASK                      0x0800
 #define FX100_CONTROL2_PING_PONG_DISABLE_ALIGN                     0
 #define FX100_CONTROL2_PING_PONG_DISABLE_BITS                      1
 #define FX100_CONTROL2_PING_PONG_DISABLE_SHIFT                     11
 
 /* FX100 :: Control2 :: pll_clk125_sw_ref [10:10] */
 #define FX100_CONTROL2_PLL_CLK125_SW_REF_MASK                      0x0400
 #define FX100_CONTROL2_PLL_CLK125_SW_REF_ALIGN                     0
 #define FX100_CONTROL2_PLL_CLK125_SW_REF_BITS                      1
 #define FX100_CONTROL2_PLL_CLK125_SW_REF_SHIFT                     10
 
 /* FX100 :: Control2 :: pll_clk125_sw_en [09:09] */
 #define FX100_CONTROL2_PLL_CLK125_SW_EN_MASK                       0x0200
 #define FX100_CONTROL2_PLL_CLK125_SW_EN_ALIGN                      0
 #define FX100_CONTROL2_PLL_CLK125_SW_EN_BITS                       1
 #define FX100_CONTROL2_PLL_CLK125_SW_EN_SHIFT                      9
 
 /* FX100 :: Control2 :: clk_out_1000_sw_def [08:08] */
 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_MASK                    0x0100
 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_ALIGN                   0
 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_BITS                    1
 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_SHIFT                   8
 
 /* FX100 :: Control2 :: clk_out_1000_sw_en [07:07] */
 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_MASK                     0x0080
 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_ALIGN                    0
 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_BITS                     1
 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_SHIFT                    7
 
 /* FX100 :: Control2 :: mii_rxc_out_sw_ref [06:06] */
 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_MASK                     0x0040
 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_ALIGN                    0
 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_BITS                     1
 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_SHIFT                    6
 
 /* FX100 :: Control2 :: mii_rxc_out_sw_en [05:05] */
 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_MASK                      0x0020
 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_ALIGN                     0
 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_BITS                      1
 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_SHIFT                     5
 
 /* FX100 :: Control2 :: mii_rxc_out_sm_rst [04:04] */
 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_MASK                     0x0010
 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_ALIGN                    0
 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_BITS                     1
 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_SHIFT                    4
 
 /* FX100 :: Control2 :: mode_chg_nrst [03:03] */
 #define FX100_CONTROL2_MODE_CHG_NRST_MASK                          0x0008
 #define FX100_CONTROL2_MODE_CHG_NRST_ALIGN                         0
 #define FX100_CONTROL2_MODE_CHG_NRST_BITS                          1
 #define FX100_CONTROL2_MODE_CHG_NRST_SHIFT                         3
 
 /* FX100 :: Control2 :: reset_rxfifo [02:02] */
 #define FX100_CONTROL2_RESET_RXFIFO_MASK                           0x0004
 #define FX100_CONTROL2_RESET_RXFIFO_ALIGN                          0
 #define FX100_CONTROL2_RESET_RXFIFO_BITS                           1
 #define FX100_CONTROL2_RESET_RXFIFO_SHIFT                          2
 
 /* FX100 :: Control2 :: bypass_rxfifo [01:01] */
 #define FX100_CONTROL2_BYPASS_RXFIFO_MASK                          0x0002
 #define FX100_CONTROL2_BYPASS_RXFIFO_ALIGN                         0
 #define FX100_CONTROL2_BYPASS_RXFIFO_BITS                          1
 #define FX100_CONTROL2_BYPASS_RXFIFO_SHIFT                         1
 
 /* FX100 :: Control2 :: extend_pkt_size [00:00] */
 #define FX100_CONTROL2_EXTEND_PKT_SIZE_MASK                        0x0001
 #define FX100_CONTROL2_EXTEND_PKT_SIZE_ALIGN                       0
 #define FX100_CONTROL2_EXTEND_PKT_SIZE_BITS                        1
 #define FX100_CONTROL2_EXTEND_PKT_SIZE_SHIFT                       0
 
 
 /****************************************************************************
  * FX100 :: Control3
  */
 /* FX100 :: Control3 :: number_of_idle [15:08] */
 #define FX100_CONTROL3_NUMBER_OF_IDLE_MASK                         0xff00
 #define FX100_CONTROL3_NUMBER_OF_IDLE_ALIGN                        0
 #define FX100_CONTROL3_NUMBER_OF_IDLE_BITS                         8
 #define FX100_CONTROL3_NUMBER_OF_IDLE_SHIFT                        8
 
 /* FX100 :: Control3 :: correlator_disable [07:07] */
 #define FX100_CONTROL3_CORRELATOR_DISABLE_MASK                     0x0080
 #define FX100_CONTROL3_CORRELATOR_DISABLE_ALIGN                    0
 #define FX100_CONTROL3_CORRELATOR_DISABLE_BITS                     1
 #define FX100_CONTROL3_CORRELATOR_DISABLE_SHIFT                    7
 
 /* FX100 :: Control3 :: bypass_nrz [06:06] */
 #define FX100_CONTROL3_BYPASS_NRZ_MASK                             0x0040
 #define FX100_CONTROL3_BYPASS_NRZ_ALIGN                            0
 #define FX100_CONTROL3_BYPASS_NRZ_BITS                             1
 #define FX100_CONTROL3_BYPASS_NRZ_SHIFT                            6
 
 /* FX100 :: Control3 :: bypass_encoder [05:05] */
 #define FX100_CONTROL3_BYPASS_ENCODER_MASK                         0x0020
 #define FX100_CONTROL3_BYPASS_ENCODER_ALIGN                        0
 #define FX100_CONTROL3_BYPASS_ENCODER_BITS                         1
 #define FX100_CONTROL3_BYPASS_ENCODER_SHIFT                        5
 
 /* FX100 :: Control3 :: bypass_alignment [04:04] */
 #define FX100_CONTROL3_BYPASS_ALIGNMENT_MASK                       0x0010
 #define FX100_CONTROL3_BYPASS_ALIGNMENT_ALIGN                      0
 #define FX100_CONTROL3_BYPASS_ALIGNMENT_BITS                       1
 #define FX100_CONTROL3_BYPASS_ALIGNMENT_SHIFT                      4
 
 /* FX100 :: Control3 :: force_link [03:03] */
 #define FX100_CONTROL3_FORCE_LINK_MASK                             0x0008
 #define FX100_CONTROL3_FORCE_LINK_ALIGN                            0
 #define FX100_CONTROL3_FORCE_LINK_BITS                             1
 #define FX100_CONTROL3_FORCE_LINK_SHIFT                            3
 
 /* FX100 :: Control3 :: force_lock [02:02] */
 #define FX100_CONTROL3_FORCE_LOCK_MASK                             0x0004
 #define FX100_CONTROL3_FORCE_LOCK_ALIGN                            0
 #define FX100_CONTROL3_FORCE_LOCK_BITS                             1
 #define FX100_CONTROL3_FORCE_LOCK_SHIFT                            2
 
 /* FX100 :: Control3 :: fast_unlock_timer [01:01] */
 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_MASK                      0x0002
 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_ALIGN                     0
 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_BITS                      1
 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_SHIFT                     1
 
 /* FX100 :: Control3 :: fast_timers [00:00] */
 #define FX100_CONTROL3_FAST_TIMERS_MASK                            0x0001
 #define FX100_CONTROL3_FAST_TIMERS_ALIGN                           0
 #define FX100_CONTROL3_FAST_TIMERS_BITS                            1
 #define FX100_CONTROL3_FAST_TIMERS_SHIFT                           0
 
 
 /****************************************************************************
  * FX100 :: Status1
  */
 /* FX100 :: Status1 :: mode_change [15:15] */
 #define FX100_STATUS1_MODE_CHANGE_MASK                             0x8000
 #define FX100_STATUS1_MODE_CHANGE_ALIGN                            0
 #define FX100_STATUS1_MODE_CHANGE_BITS                             1
 #define FX100_STATUS1_MODE_CHANGE_SHIFT                            15
 
 /* FX100 :: Status1 :: reserved0 [14:12] */
 #define FX100_STATUS1_RESERVED0_MASK                               0x7000
 #define FX100_STATUS1_RESERVED0_ALIGN                              0
 #define FX100_STATUS1_RESERVED0_BITS                               3
 #define FX100_STATUS1_RESERVED0_SHIFT                              12
 
 /* FX100 :: Status1 :: fiber_pwrdwn_status_chg [11:11] */
 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_MASK                 0x0800
 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_ALIGN                0
 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_BITS                 1
 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_SHIFT                11
 
 /* FX100 :: Status1 :: fiber_pwrdwn [10:10] */
 #define FX100_STATUS1_FIBER_PWRDWN_MASK                            0x0400
 #define FX100_STATUS1_FIBER_PWRDWN_ALIGN                           0
 #define FX100_STATUS1_FIBER_PWRDWN_BITS                            1
 #define FX100_STATUS1_FIBER_PWRDWN_SHIFT                           10
 
 /* FX100 :: Status1 :: link_status_chg [09:09] */
 #define FX100_STATUS1_LINK_STATUS_CHG_MASK                         0x0200
 #define FX100_STATUS1_LINK_STATUS_CHG_ALIGN                        0
 #define FX100_STATUS1_LINK_STATUS_CHG_BITS                         1
 #define FX100_STATUS1_LINK_STATUS_CHG_SHIFT                        9
 
 /* FX100 :: Status1 :: bad_esd_detected [08:08] */
 #define FX100_STATUS1_BAD_ESD_DETECTED_MASK                        0x0100
 #define FX100_STATUS1_BAD_ESD_DETECTED_ALIGN                       0
 #define FX100_STATUS1_BAD_ESD_DETECTED_BITS                        1
 #define FX100_STATUS1_BAD_ESD_DETECTED_SHIFT                       8
 
 /* FX100 :: Status1 :: false_carrier_detected [07:07] */
 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_MASK                  0x0080
 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_ALIGN                 0
 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_BITS                  1
 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_SHIFT                 7
 
 /* FX100 :: Status1 :: tx_err_detected [06:06] */
 #define FX100_STATUS1_TX_ERR_DETECTED_MASK                         0x0040
 #define FX100_STATUS1_TX_ERR_DETECTED_ALIGN                        0
 #define FX100_STATUS1_TX_ERR_DETECTED_BITS                         1
 #define FX100_STATUS1_TX_ERR_DETECTED_SHIFT                        6
 
 /* FX100 :: Status1 :: rx_err_detected [05:05] */
 #define FX100_STATUS1_RX_ERR_DETECTED_MASK                         0x0020
 #define FX100_STATUS1_RX_ERR_DETECTED_ALIGN                        0
 #define FX100_STATUS1_RX_ERR_DETECTED_BITS                         1
 #define FX100_STATUS1_RX_ERR_DETECTED_SHIFT                        5
 
 /* FX100 :: Status1 :: lock_timer_expired [04:04] */
 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_MASK                      0x0010
 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_ALIGN                     0
 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_BITS                      1
 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_SHIFT                     4
 
 /* FX100 :: Status1 :: lost_lock [03:03] */
 #define FX100_STATUS1_LOST_LOCK_MASK                               0x0008
 #define FX100_STATUS1_LOST_LOCK_ALIGN                              0
 #define FX100_STATUS1_LOST_LOCK_BITS                               1
 #define FX100_STATUS1_LOST_LOCK_SHIFT                              3
 
 /* FX100 :: Status1 :: faulting [02:02] */
 #define FX100_STATUS1_FAULTING_MASK                                0x0004
 #define FX100_STATUS1_FAULTING_ALIGN                               0
 #define FX100_STATUS1_FAULTING_BITS                                1
 #define FX100_STATUS1_FAULTING_SHIFT                               2
 
 /* FX100 :: Status1 :: locked [01:01] */
 #define FX100_STATUS1_LOCKED_MASK                                  0x0002
 #define FX100_STATUS1_LOCKED_ALIGN                                 0
 #define FX100_STATUS1_LOCKED_BITS                                  1
 #define FX100_STATUS1_LOCKED_SHIFT                                 1
 
 /* FX100 :: Status1 :: link [00:00] */
 #define FX100_STATUS1_LINK_MASK                                    0x0001
 #define FX100_STATUS1_LINK_ALIGN                                   0
 #define FX100_STATUS1_LINK_BITS                                    1
 #define FX100_STATUS1_LINK_SHIFT                                   0
 
 
 /****************************************************************************
  * FX100 :: Status3
  */
 /* FX100 :: Status3 :: linkmon_cntr [15:08] */
 #define FX100_STATUS3_LINKMON_CNTR_MASK                            0xff00
 #define FX100_STATUS3_LINKMON_CNTR_ALIGN                           0
 #define FX100_STATUS3_LINKMON_CNTR_BITS                            8
 #define FX100_STATUS3_LINKMON_CNTR_SHIFT                           8
 
 /* FX100 :: Status3 :: reserved0 [07:07] */
 #define FX100_STATUS3_RESERVED0_MASK                               0x0080
 #define FX100_STATUS3_RESERVED0_ALIGN                              0
 #define FX100_STATUS3_RESERVED0_BITS                               1
 #define FX100_STATUS3_RESERVED0_SHIFT                              7
 
 /* FX100 :: Status3 :: idles_detected_5b [06:06] */
 #define FX100_STATUS3_IDLES_DETECTED_5B_MASK                       0x0040
 #define FX100_STATUS3_IDLES_DETECTED_5B_ALIGN                      0
 #define FX100_STATUS3_IDLES_DETECTED_5B_BITS                       1
 #define FX100_STATUS3_IDLES_DETECTED_5B_SHIFT                      6
 
 /* FX100 :: Status3 :: crs_ind_detected [05:05] */
 #define FX100_STATUS3_CRS_IND_DETECTED_MASK                        0x0020
 #define FX100_STATUS3_CRS_IND_DETECTED_ALIGN                       0
 #define FX100_STATUS3_CRS_IND_DETECTED_BITS                        1
 #define FX100_STATUS3_CRS_IND_DETECTED_SHIFT                       5
 
 /* FX100 :: Status3 :: err_detected [04:04] */
 #define FX100_STATUS3_ERR_DETECTED_MASK                            0x0010
 #define FX100_STATUS3_ERR_DETECTED_ALIGN                           0
 #define FX100_STATUS3_ERR_DETECTED_BITS                            1
 #define FX100_STATUS3_ERR_DETECTED_SHIFT                           4
 
 /* FX100 :: Status3 :: esd_detected [03:03] */
 #define FX100_STATUS3_ESD_DETECTED_MASK                            0x0008
 #define FX100_STATUS3_ESD_DETECTED_ALIGN                           0
 #define FX100_STATUS3_ESD_DETECTED_BITS                            1
 #define FX100_STATUS3_ESD_DETECTED_SHIFT                           3
 
 /* FX100 :: Status3 :: ssd_detected [02:02] */
 #define FX100_STATUS3_SSD_DETECTED_MASK                            0x0004
 #define FX100_STATUS3_SSD_DETECTED_ALIGN                           0
 #define FX100_STATUS3_SSD_DETECTED_BITS                            1
 #define FX100_STATUS3_SSD_DETECTED_SHIFT                           2
 
 /* FX100 :: Status3 :: ij_detected [01:01] */
 #define FX100_STATUS3_IJ_DETECTED_MASK                             0x0002
 #define FX100_STATUS3_IJ_DETECTED_ALIGN                            0
 #define FX100_STATUS3_IJ_DETECTED_BITS                             1
 #define FX100_STATUS3_IJ_DETECTED_SHIFT                            1
 
 /* FX100 :: Status3 :: idles_detected [00:00] */
 #define FX100_STATUS3_IDLES_DETECTED_MASK                          0x0001
 #define FX100_STATUS3_IDLES_DETECTED_ALIGN                         0
 #define FX100_STATUS3_IDLES_DETECTED_BITS                          1
 #define FX100_STATUS3_IDLES_DETECTED_SHIFT                         0
 
 
 /****************************************************************************
  * FX100 :: Status4
  */
 /* FX100 :: Status4 :: reserved0 [15:15] */
 #define FX100_STATUS4_RESERVED0_MASK                               0x8000
 #define FX100_STATUS4_RESERVED0_ALIGN                              0
 #define FX100_STATUS4_RESERVED0_BITS                               1
 #define FX100_STATUS4_RESERVED0_SHIFT                              15
 
 /* FX100 :: Status4 :: rx_badend [14:14] */
 #define FX100_STATUS4_RX_BADEND_MASK                               0x4000
 #define FX100_STATUS4_RX_BADEND_ALIGN                              0
 #define FX100_STATUS4_RX_BADEND_BITS                               1
 #define FX100_STATUS4_RX_BADEND_SHIFT                              14
 
 /* FX100 :: Status4 :: rx_data [13:13] */
 #define FX100_STATUS4_RX_DATA_MASK                                 0x2000
 #define FX100_STATUS4_RX_DATA_ALIGN                                0
 #define FX100_STATUS4_RX_DATA_BITS                                 1
 #define FX100_STATUS4_RX_DATA_SHIFT                                13
 
 /* FX100 :: Status4 :: rx_ssk [12:12] */
 #define FX100_STATUS4_RX_SSK_MASK                                  0x1000
 #define FX100_STATUS4_RX_SSK_ALIGN                                 0
 #define FX100_STATUS4_RX_SSK_BITS                                  1
 #define FX100_STATUS4_RX_SSK_SHIFT                                 12
 
 /* FX100 :: Status4 :: rx_ssj [11:11] */
 #define FX100_STATUS4_RX_SSJ_MASK                                  0x0800
 #define FX100_STATUS4_RX_SSJ_ALIGN                                 0
 #define FX100_STATUS4_RX_SSJ_BITS                                  1
 #define FX100_STATUS4_RX_SSJ_SHIFT                                 11
 
 /* FX100 :: Status4 :: rx_confirmk [10:10] */
 #define FX100_STATUS4_RX_CONFIRMK_MASK                             0x0400
 #define FX100_STATUS4_RX_CONFIRMK_ALIGN                            0
 #define FX100_STATUS4_RX_CONFIRMK_BITS                             1
 #define FX100_STATUS4_RX_CONFIRMK_SHIFT                            10
 
 /* FX100 :: Status4 :: rx_badssd [09:09] */
 #define FX100_STATUS4_RX_BADSSD_MASK                               0x0200
 #define FX100_STATUS4_RX_BADSSD_ALIGN                              0
 #define FX100_STATUS4_RX_BADSSD_BITS                               1
 #define FX100_STATUS4_RX_BADSSD_SHIFT                              9
 
 /* FX100 :: Status4 :: fx_linkfail [08:08] */
 #define FX100_STATUS4_FX_LINKFAIL_MASK                             0x0100
 #define FX100_STATUS4_FX_LINKFAIL_ALIGN                            0
 #define FX100_STATUS4_FX_LINKFAIL_BITS                             1
 #define FX100_STATUS4_FX_LINKFAIL_SHIFT                            8
 
 /* FX100 :: Status4 :: tx_esr [07:07] */
 #define FX100_STATUS4_TX_ESR_MASK                                  0x0080
 #define FX100_STATUS4_TX_ESR_ALIGN                                 0
 #define FX100_STATUS4_TX_ESR_BITS                                  1
 #define FX100_STATUS4_TX_ESR_SHIFT                                 7
 
 /* FX100 :: Status4 :: tx_est [06:06] */
 #define FX100_STATUS4_TX_EST_MASK                                  0x0040
 #define FX100_STATUS4_TX_EST_ALIGN                                 0
 #define FX100_STATUS4_TX_EST_BITS                                  1
 #define FX100_STATUS4_TX_EST_SHIFT                                 6
 
 /* FX100 :: Status4 :: tx_terror [05:05] */
 #define FX100_STATUS4_TX_TERROR_MASK                               0x0020
 #define FX100_STATUS4_TX_TERROR_ALIGN                              0
 #define FX100_STATUS4_TX_TERROR_BITS                               1
 #define FX100_STATUS4_TX_TERROR_SHIFT                              5
 
 /* FX100 :: Status4 :: tx_tdata [04:04] */
 #define FX100_STATUS4_TX_TDATA_MASK                                0x0010
 #define FX100_STATUS4_TX_TDATA_ALIGN                               0
 #define FX100_STATUS4_TX_TDATA_BITS                                1
 #define FX100_STATUS4_TX_TDATA_SHIFT                               4
 
 /* FX100 :: Status4 :: tx_ssk [03:03] */
 #define FX100_STATUS4_TX_SSK_MASK                                  0x0008
 #define FX100_STATUS4_TX_SSK_ALIGN                                 0
 #define FX100_STATUS4_TX_SSK_BITS                                  1
 #define FX100_STATUS4_TX_SSK_SHIFT                                 3
 
 /* FX100 :: Status4 :: tx_sek [02:02] */
 #define FX100_STATUS4_TX_SEK_MASK                                  0x0004
 #define FX100_STATUS4_TX_SEK_ALIGN                                 0
 #define FX100_STATUS4_TX_SEK_BITS                                  1
 #define FX100_STATUS4_TX_SEK_SHIFT                                 2
 
 /* FX100 :: Status4 :: tx_ssj [01:01] */
 #define FX100_STATUS4_TX_SSJ_MASK                                  0x0002
 #define FX100_STATUS4_TX_SSJ_ALIGN                                 0
 #define FX100_STATUS4_TX_SSJ_BITS                                  1
 #define FX100_STATUS4_TX_SSJ_SHIFT                                 1
 
 /* FX100 :: Status4 :: tx_sej [00:00] */
 #define FX100_STATUS4_TX_SEJ_MASK                                  0x0001
 #define FX100_STATUS4_TX_SEJ_ALIGN                                 0
 #define FX100_STATUS4_TX_SEJ_BITS                                  1
 #define FX100_STATUS4_TX_SEJ_SHIFT                                 0
 
 
 /****************************************************************************
  * FX100 :: fx100Idle1
  */
 /* FX100 :: fx100Idle1 :: reserved0 [15:10] */
 #define FX100_FX100IDLE1_RESERVED0_MASK                            0xfc00
 #define FX100_FX100IDLE1_RESERVED0_ALIGN                           0
 #define FX100_FX100IDLE1_RESERVED0_BITS                            6
 #define FX100_FX100IDLE1_RESERVED0_SHIFT                           10
 
 /* FX100 :: fx100Idle1 :: fx100_idle1 [09:00] */
 #define FX100_FX100IDLE1_FX100_IDLE1_MASK                          0x03ff
 #define FX100_FX100IDLE1_FX100_IDLE1_ALIGN                         0
 #define FX100_FX100IDLE1_FX100_IDLE1_BITS                          10
 #define FX100_FX100IDLE1_FX100_IDLE1_SHIFT                         0
 
 
 /****************************************************************************
  * FX100 :: fx100idle2
  */
 /* FX100 :: fx100idle2 :: reserved0 [15:10] */
 #define FX100_FX100IDLE2_RESERVED0_MASK                            0xfc00
 #define FX100_FX100IDLE2_RESERVED0_ALIGN                           0
 #define FX100_FX100IDLE2_RESERVED0_BITS                            6
 #define FX100_FX100IDLE2_RESERVED0_SHIFT                           10
 
 /* FX100 :: fx100idle2 :: fx100_idle2 [09:00] */
 #define FX100_FX100IDLE2_FX100_IDLE2_MASK                          0x03ff
 #define FX100_FX100IDLE2_FX100_IDLE2_ALIGN                         0
 #define FX100_FX100IDLE2_FX100_IDLE2_BITS                          10
 #define FX100_FX100IDLE2_FX100_IDLE2_SHIFT                         0
 
 
 /****************************************************************************
  * FX100 :: fx100IdleStatus
  */
 /* FX100 :: fx100IdleStatus :: reserved0 [15:07] */
 #define FX100_FX100IDLESTATUS_RESERVED0_MASK                       0xff80
 #define FX100_FX100IDLESTATUS_RESERVED0_ALIGN                      0
 #define FX100_FX100IDLESTATUS_RESERVED0_BITS                       9
 #define FX100_FX100IDLESTATUS_RESERVED0_SHIFT                      7
 
 /* FX100 :: fx100IdleStatus :: fx100_idleCorr_cnt [06:00] */
 #define FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_MASK              0x007f
 #define FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_ALIGN             0
 #define FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_BITS              7
 #define FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_SHIFT             0
 
 
 /****************************************************************************
  * FX100 :: fx100IdleThres
  */
 /* FX100 :: fx100IdleThres :: reserved0 [15:14] */
 #define FX100_FX100IDLETHRES_RESERVED0_MASK                        0xc000
 #define FX100_FX100IDLETHRES_RESERVED0_ALIGN                       0
 #define FX100_FX100IDLETHRES_RESERVED0_BITS                        2
 #define FX100_FX100IDLETHRES_RESERVED0_SHIFT                       14
 
 /* FX100 :: fx100IdleThres :: fx100_idle_min_thres [13:07] */
 #define FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_MASK             0x3f80
 #define FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_ALIGN            0
 #define FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_BITS             7
 #define FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_SHIFT            7
 
 /* FX100 :: fx100IdleThres :: fx100_idle_max_thres [06:00] */
 #define FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_MASK             0x007f
 #define FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_ALIGN            0
 #define FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_BITS             7
 #define FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_SHIFT            0
 
 
 /****************************************************************************
  * FX100 :: fx100LockTmr
  */
 /* FX100 :: fx100LockTmr :: fx100_lock_thres [15:12] */
 #define FX100_FX100LOCKTMR_FX100_LOCK_THRES_MASK                   0xf000
 #define FX100_FX100LOCKTMR_FX100_LOCK_THRES_ALIGN                  0
 #define FX100_FX100LOCKTMR_FX100_LOCK_THRES_BITS                   4
 #define FX100_FX100LOCKTMR_FX100_LOCK_THRES_SHIFT                  12
 
 /* FX100 :: fx100LockTmr :: fx100_unlock_thres [11:08] */
 #define FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_MASK                 0x0f00
 #define FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_ALIGN                0
 #define FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_BITS                 4
 #define FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_SHIFT                8
 
 /* FX100 :: fx100LockTmr :: fx100_lock_maxtime [07:00] */
 #define FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_MASK                 0x00ff
 #define FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_ALIGN                0
 #define FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_BITS                 8
 #define FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_SHIFT                0
 
 
 /****************************************************************************
  * FX100 :: fx100LinkTmr
  */
 /* FX100 :: fx100LinkTmr :: fx100_linkup_count [15:08] */
 #define FX100_FX100LINKTMR_FX100_LINKUP_COUNT_MASK                 0xff00
 #define FX100_FX100LINKTMR_FX100_LINKUP_COUNT_ALIGN                0
 #define FX100_FX100LINKTMR_FX100_LINKUP_COUNT_BITS                 8
 #define FX100_FX100LINKTMR_FX100_LINKUP_COUNT_SHIFT                8
 
 /* FX100 :: fx100LinkTmr :: fx100_linkdn_count [07:00] */
 #define FX100_FX100LINKTMR_FX100_LINKDN_COUNT_MASK                 0x00ff
 #define FX100_FX100LINKTMR_FX100_LINKDN_COUNT_ALIGN                0
 #define FX100_FX100LINKTMR_FX100_LINKDN_COUNT_BITS                 8
 #define FX100_FX100LINKTMR_FX100_LINKDN_COUNT_SHIFT                0
 
 
 /****************************************************************************
  * Warpcore_USER_EEE_TimerB0
  */
 /****************************************************************************
  * EEE_TimerB0 :: grp1_tx_refresh_timer
  */
 /* EEE_TimerB0 :: grp1_tx_refresh_timer :: grp1_tx_tr_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP1_TX_REFRESH_TIMER_GRP1_TX_TR_CNT_MDIO_MASK 0xffff
 #define EEE_TIMERB0_GRP1_TX_REFRESH_TIMER_GRP1_TX_TR_CNT_MDIO_ALIGN 0
 #define EEE_TIMERB0_GRP1_TX_REFRESH_TIMER_GRP1_TX_TR_CNT_MDIO_BITS 16
 #define EEE_TIMERB0_GRP1_TX_REFRESH_TIMER_GRP1_TX_TR_CNT_MDIO_SHIFT 0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp1_tx_quiet_timer
  */
 /* EEE_TimerB0 :: grp1_tx_quiet_timer :: grp1_tx_tq_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP1_TX_QUIET_TIMER_GRP1_TX_TQ_CNT_MDIO_MASK   0xffff
 #define EEE_TIMERB0_GRP1_TX_QUIET_TIMER_GRP1_TX_TQ_CNT_MDIO_ALIGN  0
 #define EEE_TIMERB0_GRP1_TX_QUIET_TIMER_GRP1_TX_TQ_CNT_MDIO_BITS   16
 #define EEE_TIMERB0_GRP1_TX_QUIET_TIMER_GRP1_TX_TQ_CNT_MDIO_SHIFT  0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp1_rx_wake_timer
  */
 /* EEE_TimerB0 :: grp1_rx_wake_timer :: grp1_rx_tw_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP1_RX_WAKE_TIMER_GRP1_RX_TW_CNT_MDIO_MASK    0xffff
 #define EEE_TIMERB0_GRP1_RX_WAKE_TIMER_GRP1_RX_TW_CNT_MDIO_ALIGN   0
 #define EEE_TIMERB0_GRP1_RX_WAKE_TIMER_GRP1_RX_TW_CNT_MDIO_BITS    16
 #define EEE_TIMERB0_GRP1_RX_WAKE_TIMER_GRP1_RX_TW_CNT_MDIO_SHIFT   0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp2_tx_refresh_timer
  */
 /* EEE_TimerB0 :: grp2_tx_refresh_timer :: grp2_tx_tr_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP2_TX_REFRESH_TIMER_GRP2_TX_TR_CNT_MDIO_MASK 0xffff
 #define EEE_TIMERB0_GRP2_TX_REFRESH_TIMER_GRP2_TX_TR_CNT_MDIO_ALIGN 0
 #define EEE_TIMERB0_GRP2_TX_REFRESH_TIMER_GRP2_TX_TR_CNT_MDIO_BITS 16
 #define EEE_TIMERB0_GRP2_TX_REFRESH_TIMER_GRP2_TX_TR_CNT_MDIO_SHIFT 0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp2_tx_quiet_timer
  */
 /* EEE_TimerB0 :: grp2_tx_quiet_timer :: grp2_tx_tq_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP2_TX_QUIET_TIMER_GRP2_TX_TQ_CNT_MDIO_MASK   0xffff
 #define EEE_TIMERB0_GRP2_TX_QUIET_TIMER_GRP2_TX_TQ_CNT_MDIO_ALIGN  0
 #define EEE_TIMERB0_GRP2_TX_QUIET_TIMER_GRP2_TX_TQ_CNT_MDIO_BITS   16
 #define EEE_TIMERB0_GRP2_TX_QUIET_TIMER_GRP2_TX_TQ_CNT_MDIO_SHIFT  0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp2_rx_wake_timer
  */
 /* EEE_TimerB0 :: grp2_rx_wake_timer :: grp2_rx_tw_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP2_RX_WAKE_TIMER_GRP2_RX_TW_CNT_MDIO_MASK    0xffff
 #define EEE_TIMERB0_GRP2_RX_WAKE_TIMER_GRP2_RX_TW_CNT_MDIO_ALIGN   0
 #define EEE_TIMERB0_GRP2_RX_WAKE_TIMER_GRP2_RX_TW_CNT_MDIO_BITS    16
 #define EEE_TIMERB0_GRP2_RX_WAKE_TIMER_GRP2_RX_TW_CNT_MDIO_SHIFT   0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp3_tx_refresh_timer
  */
 /* EEE_TimerB0 :: grp3_tx_refresh_timer :: grp3_tx_tr_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP3_TX_REFRESH_TIMER_GRP3_TX_TR_CNT_MDIO_MASK 0xffff
 #define EEE_TIMERB0_GRP3_TX_REFRESH_TIMER_GRP3_TX_TR_CNT_MDIO_ALIGN 0
 #define EEE_TIMERB0_GRP3_TX_REFRESH_TIMER_GRP3_TX_TR_CNT_MDIO_BITS 16
 #define EEE_TIMERB0_GRP3_TX_REFRESH_TIMER_GRP3_TX_TR_CNT_MDIO_SHIFT 0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp3_tx_quiet_timer
  */
 /* EEE_TimerB0 :: grp3_tx_quiet_timer :: grp3_tx_tq_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP3_TX_QUIET_TIMER_GRP3_TX_TQ_CNT_MDIO_MASK   0xffff
 #define EEE_TIMERB0_GRP3_TX_QUIET_TIMER_GRP3_TX_TQ_CNT_MDIO_ALIGN  0
 #define EEE_TIMERB0_GRP3_TX_QUIET_TIMER_GRP3_TX_TQ_CNT_MDIO_BITS   16
 #define EEE_TIMERB0_GRP3_TX_QUIET_TIMER_GRP3_TX_TQ_CNT_MDIO_SHIFT  0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp3_rx_wake_timer
  */
 /* EEE_TimerB0 :: grp3_rx_wake_timer :: grp3_rx_tw_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP3_RX_WAKE_TIMER_GRP3_RX_TW_CNT_MDIO_MASK    0xffff
 #define EEE_TIMERB0_GRP3_RX_WAKE_TIMER_GRP3_RX_TW_CNT_MDIO_ALIGN   0
 #define EEE_TIMERB0_GRP3_RX_WAKE_TIMER_GRP3_RX_TW_CNT_MDIO_BITS    16
 #define EEE_TIMERB0_GRP3_RX_WAKE_TIMER_GRP3_RX_TW_CNT_MDIO_SHIFT   0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp4_tx_refresh_timer
  */
 /* EEE_TimerB0 :: grp4_tx_refresh_timer :: grp4_tx_tr_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP4_TX_REFRESH_TIMER_GRP4_TX_TR_CNT_MDIO_MASK 0xffff
 #define EEE_TIMERB0_GRP4_TX_REFRESH_TIMER_GRP4_TX_TR_CNT_MDIO_ALIGN 0
 #define EEE_TIMERB0_GRP4_TX_REFRESH_TIMER_GRP4_TX_TR_CNT_MDIO_BITS 16
 #define EEE_TIMERB0_GRP4_TX_REFRESH_TIMER_GRP4_TX_TR_CNT_MDIO_SHIFT 0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp4_tx_quiet_timer
  */
 /* EEE_TimerB0 :: grp4_tx_quiet_timer :: grp4_tx_tq_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP4_TX_QUIET_TIMER_GRP4_TX_TQ_CNT_MDIO_MASK   0xffff
 #define EEE_TIMERB0_GRP4_TX_QUIET_TIMER_GRP4_TX_TQ_CNT_MDIO_ALIGN  0
 #define EEE_TIMERB0_GRP4_TX_QUIET_TIMER_GRP4_TX_TQ_CNT_MDIO_BITS   16
 #define EEE_TIMERB0_GRP4_TX_QUIET_TIMER_GRP4_TX_TQ_CNT_MDIO_SHIFT  0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp4_rx_wake_timer
  */
 /* EEE_TimerB0 :: grp4_rx_wake_timer :: grp4_rx_tw_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP4_RX_WAKE_TIMER_GRP4_RX_TW_CNT_MDIO_MASK    0xffff
 #define EEE_TIMERB0_GRP4_RX_WAKE_TIMER_GRP4_RX_TW_CNT_MDIO_ALIGN   0
 #define EEE_TIMERB0_GRP4_RX_WAKE_TIMER_GRP4_RX_TW_CNT_MDIO_BITS    16
 #define EEE_TIMERB0_GRP4_RX_WAKE_TIMER_GRP4_RX_TW_CNT_MDIO_SHIFT   0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp5_tx_refresh_timer
  */
 /* EEE_TimerB0 :: grp5_tx_refresh_timer :: grp5_tx_tr_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP5_TX_REFRESH_TIMER_GRP5_TX_TR_CNT_MDIO_MASK 0xffff
 #define EEE_TIMERB0_GRP5_TX_REFRESH_TIMER_GRP5_TX_TR_CNT_MDIO_ALIGN 0
 #define EEE_TIMERB0_GRP5_TX_REFRESH_TIMER_GRP5_TX_TR_CNT_MDIO_BITS 16
 #define EEE_TIMERB0_GRP5_TX_REFRESH_TIMER_GRP5_TX_TR_CNT_MDIO_SHIFT 0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp5_tx_quiet_timer
  */
 /* EEE_TimerB0 :: grp5_tx_quiet_timer :: grp5_tx_tq_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP5_TX_QUIET_TIMER_GRP5_TX_TQ_CNT_MDIO_MASK   0xffff
 #define EEE_TIMERB0_GRP5_TX_QUIET_TIMER_GRP5_TX_TQ_CNT_MDIO_ALIGN  0
 #define EEE_TIMERB0_GRP5_TX_QUIET_TIMER_GRP5_TX_TQ_CNT_MDIO_BITS   16
 #define EEE_TIMERB0_GRP5_TX_QUIET_TIMER_GRP5_TX_TQ_CNT_MDIO_SHIFT  0
 
 
 /****************************************************************************
  * EEE_TimerB0 :: grp5_rx_wake_timer
  */
 /* EEE_TimerB0 :: grp5_rx_wake_timer :: grp5_rx_tw_cnt_mdio [15:00] */
 #define EEE_TIMERB0_GRP5_RX_WAKE_TIMER_GRP5_RX_TW_CNT_MDIO_MASK    0xffff
 #define EEE_TIMERB0_GRP5_RX_WAKE_TIMER_GRP5_RX_TW_CNT_MDIO_ALIGN   0
 #define EEE_TIMERB0_GRP5_RX_WAKE_TIMER_GRP5_RX_TW_CNT_MDIO_BITS    16
 #define EEE_TIMERB0_GRP5_RX_WAKE_TIMER_GRP5_RX_TW_CNT_MDIO_SHIFT   0
 
 
 /****************************************************************************
  * Warpcore_USER_CL82_UserB0
  */
 /****************************************************************************
  * CL82_UserB0 :: tx_control_1
  */
 /* CL82_UserB0 :: tx_control_1 :: reserved0 [15:07] */
 #define CL82_USERB0_TX_CONTROL_1_RESERVED0_MASK                    0xff80
 #define CL82_USERB0_TX_CONTROL_1_RESERVED0_ALIGN                   0
 #define CL82_USERB0_TX_CONTROL_1_RESERVED0_BITS                    9
 #define CL82_USERB0_TX_CONTROL_1_RESERVED0_SHIFT                   7
 
 /* CL82_UserB0 :: tx_control_1 :: scr_bypass [06:06] */
 #define CL82_USERB0_TX_CONTROL_1_SCR_BYPASS_MASK                   0x0040
 #define CL82_USERB0_TX_CONTROL_1_SCR_BYPASS_ALIGN                  0
 #define CL82_USERB0_TX_CONTROL_1_SCR_BYPASS_BITS                   1
 #define CL82_USERB0_TX_CONTROL_1_SCR_BYPASS_SHIFT                  6
 
 /* CL82_UserB0 :: tx_control_1 :: am_timer_init_val_tx_HI [05:03] */
 #define CL82_USERB0_TX_CONTROL_1_AM_TIMER_INIT_VAL_TX_HI_MASK      0x0038
 #define CL82_USERB0_TX_CONTROL_1_AM_TIMER_INIT_VAL_TX_HI_ALIGN     0
 #define CL82_USERB0_TX_CONTROL_1_AM_TIMER_INIT_VAL_TX_HI_BITS      3
 #define CL82_USERB0_TX_CONTROL_1_AM_TIMER_INIT_VAL_TX_HI_SHIFT     3
 
 /* CL82_UserB0 :: tx_control_1 :: ctrl_100G_en [02:02] */
 #define CL82_USERB0_TX_CONTROL_1_CTRL_100G_EN_MASK                 0x0004
 #define CL82_USERB0_TX_CONTROL_1_CTRL_100G_EN_ALIGN                0
 #define CL82_USERB0_TX_CONTROL_1_CTRL_100G_EN_BITS                 1
 #define CL82_USERB0_TX_CONTROL_1_CTRL_100G_EN_SHIFT                2
 
 /* CL82_UserB0 :: tx_control_1 :: cl82_en_val [01:01] */
 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_VAL_MASK                  0x0002
 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_VAL_ALIGN                 0
 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_VAL_BITS                  1
 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_VAL_SHIFT                 1
 
 /* CL82_UserB0 :: tx_control_1 :: cl82_en_override [00:00] */
 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_OVERRIDE_MASK             0x0001
 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_OVERRIDE_ALIGN            0
 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_OVERRIDE_BITS             1
 #define CL82_USERB0_TX_CONTROL_1_CL82_EN_OVERRIDE_SHIFT            0
 
 
 /****************************************************************************
  * CL82_UserB0 :: tx_control_2
  */
 /* CL82_UserB0 :: tx_control_2 :: am_timer_init_val_tx_LO [15:00] */
 #define CL82_USERB0_TX_CONTROL_2_AM_TIMER_INIT_VAL_TX_LO_MASK      0xffff
 #define CL82_USERB0_TX_CONTROL_2_AM_TIMER_INIT_VAL_TX_LO_ALIGN     0
 #define CL82_USERB0_TX_CONTROL_2_AM_TIMER_INIT_VAL_TX_LO_BITS      16
 #define CL82_USERB0_TX_CONTROL_2_AM_TIMER_INIT_VAL_TX_LO_SHIFT     0
 
 
 /****************************************************************************
  * CL82_UserB0 :: tx_status_1
  */
 /* CL82_UserB0 :: tx_status_1 :: reserved_for_eco0 [15:15] */
 #define CL82_USERB0_TX_STATUS_1_RESERVED_FOR_ECO0_MASK             0x8000
 #define CL82_USERB0_TX_STATUS_1_RESERVED_FOR_ECO0_ALIGN            0
 #define CL82_USERB0_TX_STATUS_1_RESERVED_FOR_ECO0_BITS             1
 #define CL82_USERB0_TX_STATUS_1_RESERVED_FOR_ECO0_SHIFT            15
 
 /* CL82_UserB0 :: tx_status_1 :: t_type [14:10] */
 #define CL82_USERB0_TX_STATUS_1_T_TYPE_MASK                        0x7c00
 #define CL82_USERB0_TX_STATUS_1_T_TYPE_ALIGN                       0
 #define CL82_USERB0_TX_STATUS_1_T_TYPE_BITS                        5
 #define CL82_USERB0_TX_STATUS_1_T_TYPE_SHIFT                       10
 
 /* CL82_UserB0 :: tx_status_1 :: ltxsm_state [09:05] */
 #define CL82_USERB0_TX_STATUS_1_LTXSM_STATE_MASK                   0x03e0
 #define CL82_USERB0_TX_STATUS_1_LTXSM_STATE_ALIGN                  0
 #define CL82_USERB0_TX_STATUS_1_LTXSM_STATE_BITS                   5
 #define CL82_USERB0_TX_STATUS_1_LTXSM_STATE_SHIFT                  5
 
 /* CL82_UserB0 :: tx_status_1 :: txsm_state [04:00] */
 #define CL82_USERB0_TX_STATUS_1_TXSM_STATE_MASK                    0x001f
 #define CL82_USERB0_TX_STATUS_1_TXSM_STATE_ALIGN                   0
 #define CL82_USERB0_TX_STATUS_1_TXSM_STATE_BITS                    5
 #define CL82_USERB0_TX_STATUS_1_TXSM_STATE_SHIFT                   0
 
 
 /****************************************************************************
  * CL82_UserB0 :: tx_status_2
  */
 /* CL82_UserB0 :: tx_status_2 :: reserved0 [15:02] */
 #define CL82_USERB0_TX_STATUS_2_RESERVED0_MASK                     0xfffc
 #define CL82_USERB0_TX_STATUS_2_RESERVED0_ALIGN                    0
 #define CL82_USERB0_TX_STATUS_2_RESERVED0_BITS                     14
 #define CL82_USERB0_TX_STATUS_2_RESERVED0_SHIFT                    2
 
 /* CL82_UserB0 :: tx_status_2 :: tx_cl82_fptr_err_latch [01:01] */
 #define CL82_USERB0_TX_STATUS_2_TX_CL82_FPTR_ERR_LATCH_MASK        0x0002
 #define CL82_USERB0_TX_STATUS_2_TX_CL82_FPTR_ERR_LATCH_ALIGN       0
 #define CL82_USERB0_TX_STATUS_2_TX_CL82_FPTR_ERR_LATCH_BITS        1
 #define CL82_USERB0_TX_STATUS_2_TX_CL82_FPTR_ERR_LATCH_SHIFT       1
 
 /* CL82_UserB0 :: tx_status_2 :: PCS_lane_num_not_synced_err_latch [00:00] */
 #define CL82_USERB0_TX_STATUS_2_PCS_LANE_NUM_NOT_SYNCED_ERR_LATCH_MASK 0x0001
 #define CL82_USERB0_TX_STATUS_2_PCS_LANE_NUM_NOT_SYNCED_ERR_LATCH_ALIGN 0
 #define CL82_USERB0_TX_STATUS_2_PCS_LANE_NUM_NOT_SYNCED_ERR_LATCH_BITS 1
 #define CL82_USERB0_TX_STATUS_2_PCS_LANE_NUM_NOT_SYNCED_ERR_LATCH_SHIFT 0
 
 
 /****************************************************************************
  * CL82_UserB0 :: rx_status_1
  */
 /* CL82_UserB0 :: rx_status_1 :: mode_strap [15:15] */
 #define CL82_USERB0_RX_STATUS_1_MODE_STRAP_MASK                    0x8000
 #define CL82_USERB0_RX_STATUS_1_MODE_STRAP_ALIGN                   0
 #define CL82_USERB0_RX_STATUS_1_MODE_STRAP_BITS                    1
 #define CL82_USERB0_RX_STATUS_1_MODE_STRAP_SHIFT                   15
 
 /* CL82_UserB0 :: rx_status_1 :: r_type [14:10] */
 #define CL82_USERB0_RX_STATUS_1_R_TYPE_MASK                        0x7c00
 #define CL82_USERB0_RX_STATUS_1_R_TYPE_ALIGN                       0
 #define CL82_USERB0_RX_STATUS_1_R_TYPE_BITS                        5
 #define CL82_USERB0_RX_STATUS_1_R_TYPE_SHIFT                       10
 
 /* CL82_UserB0 :: rx_status_1 :: lrxsm_state [09:05] */
 #define CL82_USERB0_RX_STATUS_1_LRXSM_STATE_MASK                   0x03e0
 #define CL82_USERB0_RX_STATUS_1_LRXSM_STATE_ALIGN                  0
 #define CL82_USERB0_RX_STATUS_1_LRXSM_STATE_BITS                   5
 #define CL82_USERB0_RX_STATUS_1_LRXSM_STATE_SHIFT                  5
 
 /* CL82_UserB0 :: rx_status_1 :: rxsm_state [04:00] */
 #define CL82_USERB0_RX_STATUS_1_RXSM_STATE_MASK                    0x001f
 #define CL82_USERB0_RX_STATUS_1_RXSM_STATE_ALIGN                   0
 #define CL82_USERB0_RX_STATUS_1_RXSM_STATE_BITS                    5
 #define CL82_USERB0_RX_STATUS_1_RXSM_STATE_SHIFT                   0
 
 
 /****************************************************************************
  * CL82_UserB0 :: rx_status_2
  */
 /* CL82_UserB0 :: rx_status_2 :: pseudo_lock [15:15] */
 #define CL82_USERB0_RX_STATUS_2_PSEUDO_LOCK_MASK                   0x8000
 #define CL82_USERB0_RX_STATUS_2_PSEUDO_LOCK_ALIGN                  0
 #define CL82_USERB0_RX_STATUS_2_PSEUDO_LOCK_BITS                   1
 #define CL82_USERB0_RX_STATUS_2_PSEUDO_LOCK_SHIFT                  15
 
 /* CL82_UserB0 :: rx_status_2 :: deskew_state [14:14] */
 #define CL82_USERB0_RX_STATUS_2_DESKEW_STATE_MASK                  0x4000
 #define CL82_USERB0_RX_STATUS_2_DESKEW_STATE_ALIGN                 0
 #define CL82_USERB0_RX_STATUS_2_DESKEW_STATE_BITS                  1
 #define CL82_USERB0_RX_STATUS_2_DESKEW_STATE_SHIFT                 14
 
 /* CL82_UserB0 :: rx_status_2 :: deskew_his_state [13:12] */
 #define CL82_USERB0_RX_STATUS_2_DESKEW_HIS_STATE_MASK              0x3000
 #define CL82_USERB0_RX_STATUS_2_DESKEW_HIS_STATE_ALIGN             0
 #define CL82_USERB0_RX_STATUS_2_DESKEW_HIS_STATE_BITS              2
 #define CL82_USERB0_RX_STATUS_2_DESKEW_HIS_STATE_SHIFT             12
 
 /* CL82_UserB0 :: rx_status_2 :: lbermon_state [11:06] */
 #define CL82_USERB0_RX_STATUS_2_LBERMON_STATE_MASK                 0x0fc0
 #define CL82_USERB0_RX_STATUS_2_LBERMON_STATE_ALIGN                0
 #define CL82_USERB0_RX_STATUS_2_LBERMON_STATE_BITS                 6
 #define CL82_USERB0_RX_STATUS_2_LBERMON_STATE_SHIFT                6
 
 /* CL82_UserB0 :: rx_status_2 :: bermon_state [05:00] */
 #define CL82_USERB0_RX_STATUS_2_BERMON_STATE_MASK                  0x003f
 #define CL82_USERB0_RX_STATUS_2_BERMON_STATE_ALIGN                 0
 #define CL82_USERB0_RX_STATUS_2_BERMON_STATE_BITS                  6
 #define CL82_USERB0_RX_STATUS_2_BERMON_STATE_SHIFT                 0
 
 
 /****************************************************************************
  * CL82_UserB0 :: rx_status_3
  */
 /* CL82_UserB0 :: rx_status_3 :: non_unique_Amrkr_err_mux [15:15] */
 #define CL82_USERB0_RX_STATUS_3_NON_UNIQUE_AMRKR_ERR_MUX_MASK      0x8000
 #define CL82_USERB0_RX_STATUS_3_NON_UNIQUE_AMRKR_ERR_MUX_ALIGN     0
 #define CL82_USERB0_RX_STATUS_3_NON_UNIQUE_AMRKR_ERR_MUX_BITS      1
 #define CL82_USERB0_RX_STATUS_3_NON_UNIQUE_AMRKR_ERR_MUX_SHIFT     15
 
 /* CL82_UserB0 :: rx_status_3 :: amrkr_spacing_err_latch_mux [14:14] */
 #define CL82_USERB0_RX_STATUS_3_AMRKR_SPACING_ERR_LATCH_MUX_MASK   0x4000
 #define CL82_USERB0_RX_STATUS_3_AMRKR_SPACING_ERR_LATCH_MUX_ALIGN  0
 #define CL82_USERB0_RX_STATUS_3_AMRKR_SPACING_ERR_LATCH_MUX_BITS   1
 #define CL82_USERB0_RX_STATUS_3_AMRKR_SPACING_ERR_LATCH_MUX_SHIFT  14
 
 /* CL82_UserB0 :: rx_status_3 :: am_lock_state [13:10] */
 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_STATE_MASK                 0x3c00
 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_STATE_ALIGN                0
 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_STATE_BITS                 4
 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_STATE_SHIFT                10
 
 /* CL82_UserB0 :: rx_status_3 :: am_lock_his_state [09:00] */
 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_HIS_STATE_MASK             0x03ff
 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_HIS_STATE_ALIGN            0
 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_HIS_STATE_BITS             10
 #define CL82_USERB0_RX_STATUS_3_AM_LOCK_HIS_STATE_SHIFT            0
 
 
 /****************************************************************************
  * CL82_UserB0 :: rx_control_1
  */
 /* CL82_UserB0 :: rx_control_1 :: timer125us [15:00] */
 #define CL82_USERB0_RX_CONTROL_1_TIMER125US_MASK                   0xffff
 #define CL82_USERB0_RX_CONTROL_1_TIMER125US_ALIGN                  0
 #define CL82_USERB0_RX_CONTROL_1_TIMER125US_BITS                   16
 #define CL82_USERB0_RX_CONTROL_1_TIMER125US_SHIFT                  0
 
 
 /****************************************************************************
  * CL82_UserB0 :: rx_control_2
  */
 /* CL82_UserB0 :: rx_control_2 :: bercnt [15:08] */
 #define CL82_USERB0_RX_CONTROL_2_BERCNT_MASK                       0xff00
 #define CL82_USERB0_RX_CONTROL_2_BERCNT_ALIGN                      0
 #define CL82_USERB0_RX_CONTROL_2_BERCNT_BITS                       8
 #define CL82_USERB0_RX_CONTROL_2_BERCNT_SHIFT                      8
 
 /* CL82_UserB0 :: rx_control_2 :: reserved0 [07:06] */
 #define CL82_USERB0_RX_CONTROL_2_RESERVED0_MASK                    0x00c0
 #define CL82_USERB0_RX_CONTROL_2_RESERVED0_ALIGN                   0
 #define CL82_USERB0_RX_CONTROL_2_RESERVED0_BITS                    2
 #define CL82_USERB0_RX_CONTROL_2_RESERVED0_SHIFT                   6
 
 /* CL82_UserB0 :: rx_control_2 :: am_lane_sel [05:04] */
 #define CL82_USERB0_RX_CONTROL_2_AM_LANE_SEL_MASK                  0x0030
 #define CL82_USERB0_RX_CONTROL_2_AM_LANE_SEL_ALIGN                 0
 #define CL82_USERB0_RX_CONTROL_2_AM_LANE_SEL_BITS                  2
 #define CL82_USERB0_RX_CONTROL_2_AM_LANE_SEL_SHIFT                 4
 
 /* CL82_UserB0 :: rx_control_2 :: timer125us_ho [03:00] */
 #define CL82_USERB0_RX_CONTROL_2_TIMER125US_HO_MASK                0x000f
 #define CL82_USERB0_RX_CONTROL_2_TIMER125US_HO_ALIGN               0
 #define CL82_USERB0_RX_CONTROL_2_TIMER125US_HO_BITS                4
 #define CL82_USERB0_RX_CONTROL_2_TIMER125US_HO_SHIFT               0
 
 
 /****************************************************************************
  * CL82_UserB0 :: rx_control_3
  */
 /* CL82_UserB0 :: rx_control_3 :: am_timer_init_val [15:00] */
 #define CL82_USERB0_RX_CONTROL_3_AM_TIMER_INIT_VAL_MASK            0xffff
 #define CL82_USERB0_RX_CONTROL_3_AM_TIMER_INIT_VAL_ALIGN           0
 #define CL82_USERB0_RX_CONTROL_3_AM_TIMER_INIT_VAL_BITS            16
 #define CL82_USERB0_RX_CONTROL_3_AM_TIMER_INIT_VAL_SHIFT           0
 
 
 /****************************************************************************
  * CL82_UserB0 :: rx_control_4
  */
 /* CL82_UserB0 :: rx_control_4 :: mode_sel [15:15] */
 #define CL82_USERB0_RX_CONTROL_4_MODE_SEL_MASK                     0x8000
 #define CL82_USERB0_RX_CONTROL_4_MODE_SEL_ALIGN                    0
 #define CL82_USERB0_RX_CONTROL_4_MODE_SEL_BITS                     1
 #define CL82_USERB0_RX_CONTROL_4_MODE_SEL_SHIFT                    15
 
 /* CL82_UserB0 :: rx_control_4 :: reserved0 [14:10] */
 #define CL82_USERB0_RX_CONTROL_4_RESERVED0_MASK                    0x7c00
 #define CL82_USERB0_RX_CONTROL_4_RESERVED0_ALIGN                   0
 #define CL82_USERB0_RX_CONTROL_4_RESERVED0_BITS                    5
 #define CL82_USERB0_RX_CONTROL_4_RESERVED0_SHIFT                   10
 
 /* CL82_UserB0 :: rx_control_4 :: descr_bypass [09:09] */
 #define CL82_USERB0_RX_CONTROL_4_DESCR_BYPASS_MASK                 0x0200
 #define CL82_USERB0_RX_CONTROL_4_DESCR_BYPASS_ALIGN                0
 #define CL82_USERB0_RX_CONTROL_4_DESCR_BYPASS_BITS                 1
 #define CL82_USERB0_RX_CONTROL_4_DESCR_BYPASS_SHIFT                9
 
 /* CL82_UserB0 :: rx_control_4 :: rf_det_en_cya [08:08] */
 #define CL82_USERB0_RX_CONTROL_4_RF_DET_EN_CYA_MASK                0x0100
 #define CL82_USERB0_RX_CONTROL_4_RF_DET_EN_CYA_ALIGN               0
 #define CL82_USERB0_RX_CONTROL_4_RF_DET_EN_CYA_BITS                1
 #define CL82_USERB0_RX_CONTROL_4_RF_DET_EN_CYA_SHIFT               8
 
 /* CL82_UserB0 :: rx_control_4 :: lf_det_en_cya [07:07] */
 #define CL82_USERB0_RX_CONTROL_4_LF_DET_EN_CYA_MASK                0x0080
 #define CL82_USERB0_RX_CONTROL_4_LF_DET_EN_CYA_ALIGN               0
 #define CL82_USERB0_RX_CONTROL_4_LF_DET_EN_CYA_BITS                1
 #define CL82_USERB0_RX_CONTROL_4_LF_DET_EN_CYA_SHIFT               7
 
 /* CL82_UserB0 :: rx_control_4 :: linkdown_as_fault_cya [06:06] */
 #define CL82_USERB0_RX_CONTROL_4_LINKDOWN_AS_FAULT_CYA_MASK        0x0040
 #define CL82_USERB0_RX_CONTROL_4_LINKDOWN_AS_FAULT_CYA_ALIGN       0
 #define CL82_USERB0_RX_CONTROL_4_LINKDOWN_AS_FAULT_CYA_BITS        1
 #define CL82_USERB0_RX_CONTROL_4_LINKDOWN_AS_FAULT_CYA_SHIFT       6
 
 /* CL82_UserB0 :: rx_control_4 :: outidle_def_cya [05:05] */
 #define CL82_USERB0_RX_CONTROL_4_OUTIDLE_DEF_CYA_MASK              0x0020
 #define CL82_USERB0_RX_CONTROL_4_OUTIDLE_DEF_CYA_ALIGN             0
 #define CL82_USERB0_RX_CONTROL_4_OUTIDLE_DEF_CYA_BITS              1
 #define CL82_USERB0_RX_CONTROL_4_OUTIDLE_DEF_CYA_SHIFT             5
 
 /* CL82_UserB0 :: rx_control_4 :: deskew_win [04:00] */
 #define CL82_USERB0_RX_CONTROL_4_DESKEW_WIN_MASK                   0x001f
 #define CL82_USERB0_RX_CONTROL_4_DESKEW_WIN_ALIGN                  0
 #define CL82_USERB0_RX_CONTROL_4_DESKEW_WIN_BITS                   5
 #define CL82_USERB0_RX_CONTROL_4_DESKEW_WIN_SHIFT                  0
 
 
 /****************************************************************************
  * CL82_UserB0 :: rx_control_5
  */
 /* CL82_UserB0 :: rx_control_5 :: reserved0 [15:13] */
 #define CL82_USERB0_RX_CONTROL_5_RESERVED0_MASK                    0xe000
 #define CL82_USERB0_RX_CONTROL_5_RESERVED0_ALIGN                   0
 #define CL82_USERB0_RX_CONTROL_5_RESERVED0_BITS                    3
 #define CL82_USERB0_RX_CONTROL_5_RESERVED0_SHIFT                   13
 
 /* CL82_UserB0 :: rx_control_5 :: use_cl49_lsm_for_cl82_cya [12:12] */
 #define CL82_USERB0_RX_CONTROL_5_USE_CL49_LSM_FOR_CL82_CYA_MASK    0x1000
 #define CL82_USERB0_RX_CONTROL_5_USE_CL49_LSM_FOR_CL82_CYA_ALIGN   0
 #define CL82_USERB0_RX_CONTROL_5_USE_CL49_LSM_FOR_CL82_CYA_BITS    1
 #define CL82_USERB0_RX_CONTROL_5_USE_CL49_LSM_FOR_CL82_CYA_SHIFT   12
 
 /* CL82_UserB0 :: rx_control_5 :: sh_cnt_cl82_ext [11:00] */
 #define CL82_USERB0_RX_CONTROL_5_SH_CNT_CL82_EXT_MASK              0x0fff
 #define CL82_USERB0_RX_CONTROL_5_SH_CNT_CL82_EXT_ALIGN             0
 #define CL82_USERB0_RX_CONTROL_5_SH_CNT_CL82_EXT_BITS              12
 #define CL82_USERB0_RX_CONTROL_5_SH_CNT_CL82_EXT_SHIFT             0
 
 
 /****************************************************************************
  * CL82_UserB0 :: rx_control_6
  */
 /* CL82_UserB0 :: rx_control_6 :: reserved0 [15:12] */
 #define CL82_USERB0_RX_CONTROL_6_RESERVED0_MASK                    0xf000
 #define CL82_USERB0_RX_CONTROL_6_RESERVED0_ALIGN                   0
 #define CL82_USERB0_RX_CONTROL_6_RESERVED0_BITS                    4
 #define CL82_USERB0_RX_CONTROL_6_RESERVED0_SHIFT                   12
 
 /* CL82_UserB0 :: rx_control_6 :: invalid_sh_cnt_cl82_ext [11:00] */
 #define CL82_USERB0_RX_CONTROL_6_INVALID_SH_CNT_CL82_EXT_MASK      0x0fff
 #define CL82_USERB0_RX_CONTROL_6_INVALID_SH_CNT_CL82_EXT_ALIGN     0
 #define CL82_USERB0_RX_CONTROL_6_INVALID_SH_CNT_CL82_EXT_BITS      12
 #define CL82_USERB0_RX_CONTROL_6_INVALID_SH_CNT_CL82_EXT_SHIFT     0
 
 
 /****************************************************************************
  * CL82_UserB0 :: rx_status_4
  */
 /* CL82_UserB0 :: rx_status_4 :: reserved0 [15:10] */
 #define CL82_USERB0_RX_STATUS_4_RESERVED0_MASK                     0xfc00
 #define CL82_USERB0_RX_STATUS_4_RESERVED0_ALIGN                    0
 #define CL82_USERB0_RX_STATUS_4_RESERVED0_BITS                     6
 #define CL82_USERB0_RX_STATUS_4_RESERVED0_SHIFT                    10
 
 /* CL82_UserB0 :: rx_status_4 :: am_status [09:09] */
 #define CL82_USERB0_RX_STATUS_4_AM_STATUS_MASK                     0x0200
 #define CL82_USERB0_RX_STATUS_4_AM_STATUS_ALIGN                    0
 #define CL82_USERB0_RX_STATUS_4_AM_STATUS_BITS                     1
 #define CL82_USERB0_RX_STATUS_4_AM_STATUS_SHIFT                    9
 
 /* CL82_UserB0 :: rx_status_4 :: am_rmfifo_overflow [08:08] */
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_OVERFLOW_MASK            0x0100
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_OVERFLOW_ALIGN           0
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_OVERFLOW_BITS            1
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_OVERFLOW_SHIFT           8
 
 /* CL82_UserB0 :: rx_status_4 :: am_rmfifo_underflow [07:07] */
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_UNDERFLOW_MASK           0x0080
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_UNDERFLOW_ALIGN          0
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_UNDERFLOW_BITS           1
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_UNDERFLOW_SHIFT          7
 
 /* CL82_UserB0 :: rx_status_4 :: am_rmfifo_fptr_err [06:06] */
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_FPTR_ERR_MASK            0x0040
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_FPTR_ERR_ALIGN           0
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_FPTR_ERR_BITS            1
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_FPTR_ERR_SHIFT           6
 
 /* CL82_UserB0 :: rx_status_4 :: am_rmfifo_state [05:04] */
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_STATE_MASK               0x0030
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_STATE_ALIGN              0
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_STATE_BITS               2
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_STATE_SHIFT              4
 
 /* CL82_UserB0 :: rx_status_4 :: am_rmfifo_his_state [03:00] */
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_HIS_STATE_MASK           0x000f
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_HIS_STATE_ALIGN          0
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_HIS_STATE_BITS           4
 #define CL82_USERB0_RX_STATUS_4_AM_RMFIFO_HIS_STATE_SHIFT          0
 
 
 /****************************************************************************
  * Warpcore_USER_CL82_UserB1
  */
 /****************************************************************************
  * CL82_UserB1 :: rx_control_7
  */
 /* CL82_UserB1 :: rx_control_7 :: rx_misc_control [15:08] */
 #define CL82_USERB1_RX_CONTROL_7_RX_MISC_CONTROL_MASK              0xff00
 #define CL82_USERB1_RX_CONTROL_7_RX_MISC_CONTROL_ALIGN             0
 #define CL82_USERB1_RX_CONTROL_7_RX_MISC_CONTROL_BITS              8
 #define CL82_USERB1_RX_CONTROL_7_RX_MISC_CONTROL_SHIFT             8
 
 /* CL82_UserB1 :: rx_control_7 :: rx_test_block_sel [07:04] */
 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_BLOCK_SEL_MASK            0x00f0
 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_BLOCK_SEL_ALIGN           0
 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_BLOCK_SEL_BITS            4
 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_BLOCK_SEL_SHIFT           4
 
 /* CL82_UserB1 :: rx_control_7 :: rx_test_data_sel [03:00] */
 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_DATA_SEL_MASK             0x000f
 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_DATA_SEL_ALIGN            0
 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_DATA_SEL_BITS             4
 #define CL82_USERB1_RX_CONTROL_7_RX_TEST_DATA_SEL_SHIFT            0
 
 
 /****************************************************************************
  * CL82_UserB1 :: rx_status_5
  */
 /* CL82_UserB1 :: rx_status_5 :: rx_misc_status_data [15:08] */
 #define CL82_USERB1_RX_STATUS_5_RX_MISC_STATUS_DATA_MASK           0xff00
 #define CL82_USERB1_RX_STATUS_5_RX_MISC_STATUS_DATA_ALIGN          0
 #define CL82_USERB1_RX_STATUS_5_RX_MISC_STATUS_DATA_BITS           8
 #define CL82_USERB1_RX_STATUS_5_RX_MISC_STATUS_DATA_SHIFT          8
 
 /* CL82_UserB1 :: rx_status_5 :: rx_test_status_data [07:00] */
 #define CL82_USERB1_RX_STATUS_5_RX_TEST_STATUS_DATA_MASK           0x00ff
 #define CL82_USERB1_RX_STATUS_5_RX_TEST_STATUS_DATA_ALIGN          0
 #define CL82_USERB1_RX_STATUS_5_RX_TEST_STATUS_DATA_BITS           8
 #define CL82_USERB1_RX_STATUS_5_RX_TEST_STATUS_DATA_SHIFT          0
 
 
 /****************************************************************************
  * CL82_UserB1 :: tx_control_3
  */
 /* CL82_UserB1 :: tx_control_3 :: tx_misc_control [15:08] */
 #define CL82_USERB1_TX_CONTROL_3_TX_MISC_CONTROL_MASK              0xff00
 #define CL82_USERB1_TX_CONTROL_3_TX_MISC_CONTROL_ALIGN             0
 #define CL82_USERB1_TX_CONTROL_3_TX_MISC_CONTROL_BITS              8
 #define CL82_USERB1_TX_CONTROL_3_TX_MISC_CONTROL_SHIFT             8
 
 /* CL82_UserB1 :: tx_control_3 :: tx_test_block_sel [07:04] */
 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_BLOCK_SEL_MASK            0x00f0
 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_BLOCK_SEL_ALIGN           0
 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_BLOCK_SEL_BITS            4
 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_BLOCK_SEL_SHIFT           4
 
 /* CL82_UserB1 :: tx_control_3 :: tx_test_data_sel [03:00] */
 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_DATA_SEL_MASK             0x000f
 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_DATA_SEL_ALIGN            0
 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_DATA_SEL_BITS             4
 #define CL82_USERB1_TX_CONTROL_3_TX_TEST_DATA_SEL_SHIFT            0
 
 
 /****************************************************************************
  * CL82_UserB1 :: tx_status_3
  */
 /* CL82_UserB1 :: tx_status_3 :: tx_misc_status_data [15:08] */
 #define CL82_USERB1_TX_STATUS_3_TX_MISC_STATUS_DATA_MASK           0xff00
 #define CL82_USERB1_TX_STATUS_3_TX_MISC_STATUS_DATA_ALIGN          0
 #define CL82_USERB1_TX_STATUS_3_TX_MISC_STATUS_DATA_BITS           8
 #define CL82_USERB1_TX_STATUS_3_TX_MISC_STATUS_DATA_SHIFT          8
 
 /* CL82_UserB1 :: tx_status_3 :: tx_test_status_data [07:00] */
 #define CL82_USERB1_TX_STATUS_3_TX_TEST_STATUS_DATA_MASK           0x00ff
 #define CL82_USERB1_TX_STATUS_3_TX_TEST_STATUS_DATA_ALIGN          0
 #define CL82_USERB1_TX_STATUS_3_TX_TEST_STATUS_DATA_BITS           8
 #define CL82_USERB1_TX_STATUS_3_TX_TEST_STATUS_DATA_SHIFT          0
 
 
 /****************************************************************************
  * Warpcore_USER_rx66b1
  */
 /****************************************************************************
  * rx66b1 :: brcm_cl49_Control
  */
 /* rx66b1 :: brcm_cl49_Control :: reserved0 [15:04] */
 #define RX66B1_BRCM_CL49_CONTROL_RESERVED0_MASK                    0xfff0
 #define RX66B1_BRCM_CL49_CONTROL_RESERVED0_ALIGN                   0
 #define RX66B1_BRCM_CL49_CONTROL_RESERVED0_BITS                    12
 #define RX66B1_BRCM_CL49_CONTROL_RESERVED0_SHIFT                   4
 
 /* rx66b1 :: brcm_cl49_Control :: mdio_brcmfault_det_en [03:03] */
 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCMFAULT_DET_EN_MASK        0x0008
 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCMFAULT_DET_EN_ALIGN       0
 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCMFAULT_DET_EN_BITS        1
 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCMFAULT_DET_EN_SHIFT       3
 
 /* rx66b1 :: brcm_cl49_Control :: brcm_cl49_dout_ctrl [02:01] */
 #define RX66B1_BRCM_CL49_CONTROL_BRCM_CL49_DOUT_CTRL_MASK          0x0006
 #define RX66B1_BRCM_CL49_CONTROL_BRCM_CL49_DOUT_CTRL_ALIGN         0
 #define RX66B1_BRCM_CL49_CONTROL_BRCM_CL49_DOUT_CTRL_BITS          2
 #define RX66B1_BRCM_CL49_CONTROL_BRCM_CL49_DOUT_CTRL_SHIFT         1
 
 /* rx66b1 :: brcm_cl49_Control :: mdio_brcm6466_cl49_en [00:00] */
 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCM6466_CL49_EN_MASK        0x0001
 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCM6466_CL49_EN_ALIGN       0
 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCM6466_CL49_EN_BITS        1
 #define RX66B1_BRCM_CL49_CONTROL_MDIO_BRCM6466_CL49_EN_SHIFT       0
 
 
 /****************************************************************************
  * Warpcore_USER_XFI_BD0
  */
 /****************************************************************************
  * XFI_BD0 :: pmd_and_pcs_status_register
  */
 /* XFI_BD0 :: pmd_and_pcs_status_register :: reserved0 [15:15] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED0_MASK         0x8000
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED0_ALIGN        0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED0_BITS         1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED0_SHIFT        15
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_losbi_bar [14:14] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_BAR_MASK       0x4000
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_BAR_ALIGN      0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_BAR_BITS       1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_BAR_SHIFT      14
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_losb_bar [13:13] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_BAR_MASK        0x2000
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_BAR_ALIGN       0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_BAR_BITS        1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_BAR_SHIFT       13
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: reserved1 [12:12] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED1_MASK         0x1000
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED1_ALIGN        0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED1_BITS         1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED1_SHIFT        12
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdtcmu_bar [11:11] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_BAR_MASK     0x0800
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_BAR_ALIGN    0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_BAR_BITS     1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_BAR_SHIFT    11
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdtcdr_bar [10:10] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_BAR_MASK     0x0400
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_BAR_ALIGN    0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_BAR_BITS     1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_BAR_SHIFT    10
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdt_ep_bar [09:09] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_BAR_MASK     0x0200
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_BAR_ALIGN    0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_BAR_BITS     1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_BAR_SHIFT    9
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_linelpbk_cls [08:08] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LINELPBK_CLS_MASK    0x0100
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LINELPBK_CLS_ALIGN   0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LINELPBK_CLS_BITS    1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LINELPBK_CLS_SHIFT   8
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: reserved2 [07:07] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED2_MASK         0x0080
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED2_ALIGN        0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED2_BITS         1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED2_SHIFT        7
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_losbi [06:06] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_MASK           0x0040
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_ALIGN          0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_BITS           1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSBI_SHIFT          6
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_losb [05:05] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_MASK            0x0020
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_ALIGN           0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_BITS            1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LOSB_SHIFT           5
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: reserved3 [04:04] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED3_MASK         0x0010
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED3_ALIGN        0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED3_BITS         1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED3_SHIFT        4
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdtcmu [03:03] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_MASK         0x0008
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_ALIGN        0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_BITS         1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCMU_SHIFT        3
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdtcdr [02:02] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_MASK         0x0004
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_ALIGN        0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_BITS         1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDTCDR_SHIFT        2
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: p_lkdt_ep [01:01] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_MASK         0x0002
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_ALIGN        0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_BITS         1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_P_LKDT_EP_SHIFT        1
 
 /* XFI_BD0 :: pmd_and_pcs_status_register :: reserved4 [00:00] */
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED4_MASK         0x0001
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED4_ALIGN        0
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED4_BITS         1
 #define XFI_BD0_PMD_AND_PCS_STATUS_REGISTER_RESERVED4_SHIFT        0
 
 
 /****************************************************************************
  * XFI_BD0 :: pmd_optics_digital_control_register
  */
 /* XFI_BD0 :: pmd_optics_digital_control_register :: cl73_txdis_en [15:15] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_CL73_TXDIS_EN_MASK 0x8000
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_CL73_TXDIS_EN_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_CL73_TXDIS_EN_BITS 1
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_CL73_TXDIS_EN_SHIFT 15
 
 /* XFI_BD0 :: pmd_optics_digital_control_register :: reserved0 [14:13] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED0_MASK 0x6000
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED0_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED0_BITS 2
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED0_SHIFT 13
 
 /* XFI_BD0 :: pmd_optics_digital_control_register :: pcs_rx_order [12:12] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_ORDER_MASK 0x1000
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_ORDER_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_ORDER_BITS 1
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_ORDER_SHIFT 12
 
 /* XFI_BD0 :: pmd_optics_digital_control_register :: pcs_tx_order [11:11] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_ORDER_MASK 0x0800
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_ORDER_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_ORDER_BITS 1
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_ORDER_SHIFT 11
 
 /* XFI_BD0 :: pmd_optics_digital_control_register :: pcs_tx_inv [10:10] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_INV_MASK 0x0400
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_INV_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_INV_BITS 1
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_TX_INV_SHIFT 10
 
 /* XFI_BD0 :: pmd_optics_digital_control_register :: pcs_rx_inv [09:09] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_INV_MASK 0x0200
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_INV_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_INV_BITS 1
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_PCS_RX_INV_SHIFT 9
 
 /* XFI_BD0 :: pmd_optics_digital_control_register :: higig2_ent [08:08] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_ENT_MASK 0x0100
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_ENT_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_ENT_BITS 1
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_ENT_SHIFT 8
 
 /* XFI_BD0 :: pmd_optics_digital_control_register :: higig2_size [07:07] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_SIZE_MASK 0x0080
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_SIZE_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_SIZE_BITS 1
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_HIGIG2_SIZE_SHIFT 7
 
 /* XFI_BD0 :: pmd_optics_digital_control_register :: reserved1 [06:04] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED1_MASK 0x0070
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED1_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED1_BITS 3
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED1_SHIFT 4
 
 /* XFI_BD0 :: pmd_optics_digital_control_register :: lpbk_err_dis [03:03] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_LPBK_ERR_DIS_MASK 0x0008
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_LPBK_ERR_DIS_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_LPBK_ERR_DIS_BITS 1
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_LPBK_ERR_DIS_SHIFT 3
 
 /* XFI_BD0 :: pmd_optics_digital_control_register :: reserved2 [02:00] */
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED2_MASK 0x0007
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED2_ALIGN 0
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED2_BITS 3
 #define XFI_BD0_PMD_OPTICS_DIGITAL_CONTROL_REGISTER_RESERVED2_SHIFT 0
 
 
 /****************************************************************************
  * XFI_BD0 :: pmd_digital_status_register
  */
 /* XFI_BD0 :: pmd_digital_status_register :: t64_gbox_ovf [15:15] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_GBOX_OVF_MASK      0x8000
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_GBOX_OVF_ALIGN     0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_GBOX_OVF_BITS      1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_GBOX_OVF_SHIFT     15
 
 /* XFI_BD0 :: pmd_digital_status_register :: t64_init_error [14:14] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_INIT_ERROR_MASK    0x4000
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_INIT_ERROR_ALIGN   0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_INIT_ERROR_BITS    1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_INIT_ERROR_SHIFT   14
 
 /* XFI_BD0 :: pmd_digital_status_register :: t64_c_error [13:13] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_C_ERROR_MASK       0x2000
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_C_ERROR_ALIGN      0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_C_ERROR_BITS       1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_C_ERROR_SHIFT      13
 
 /* XFI_BD0 :: pmd_digital_status_register :: t64_d_error [12:12] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_D_ERROR_MASK       0x1000
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_D_ERROR_ALIGN      0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_D_ERROR_BITS       1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_D_ERROR_SHIFT      12
 
 /* XFI_BD0 :: pmd_digital_status_register :: t64_t_error [11:11] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_T_ERROR_MASK       0x0800
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_T_ERROR_ALIGN      0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_T_ERROR_BITS       1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_T64_T_ERROR_SHIFT      11
 
 /* XFI_BD0 :: pmd_digital_status_register :: r64_gbox_ovf [10:10] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_GBOX_OVF_MASK      0x0400
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_GBOX_OVF_ALIGN     0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_GBOX_OVF_BITS      1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_GBOX_OVF_SHIFT     10
 
 /* XFI_BD0 :: pmd_digital_status_register :: r64_sync_acq [09:09] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_SYNC_ACQ_MASK      0x0200
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_SYNC_ACQ_ALIGN     0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_SYNC_ACQ_BITS      1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_SYNC_ACQ_SHIFT     9
 
 /* XFI_BD0 :: pmd_digital_status_register :: r64_los [08:08] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_LOS_MASK           0x0100
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_LOS_ALIGN          0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_LOS_BITS           1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_LOS_SHIFT          8
 
 /* XFI_BD0 :: pmd_digital_status_register :: r64_init_error [07:07] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_INIT_ERROR_MASK    0x0080
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_INIT_ERROR_ALIGN   0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_INIT_ERROR_BITS    1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_INIT_ERROR_SHIFT   7
 
 /* XFI_BD0 :: pmd_digital_status_register :: r64_c_error [06:06] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_C_ERROR_MASK       0x0040
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_C_ERROR_ALIGN      0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_C_ERROR_BITS       1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_C_ERROR_SHIFT      6
 
 /* XFI_BD0 :: pmd_digital_status_register :: r64_d_error [05:05] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_D_ERROR_MASK       0x0020
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_D_ERROR_ALIGN      0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_D_ERROR_BITS       1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_D_ERROR_SHIFT      5
 
 /* XFI_BD0 :: pmd_digital_status_register :: r64_t_error [04:04] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_T_ERROR_MASK       0x0010
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_T_ERROR_ALIGN      0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_T_ERROR_BITS       1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_T_ERROR_SHIFT      4
 
 /* XFI_BD0 :: pmd_digital_status_register :: reserved0 [03:01] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_RESERVED0_MASK         0x000e
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_RESERVED0_ALIGN        0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_RESERVED0_BITS         3
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_RESERVED0_SHIFT        1
 
 /* XFI_BD0 :: pmd_digital_status_register :: r64_jitt_pat_det [00:00] */
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_JITT_PAT_DET_MASK  0x0001
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_JITT_PAT_DET_ALIGN 0
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_JITT_PAT_DET_BITS  1
 #define XFI_BD0_PMD_DIGITAL_STATUS_REGISTER_R64_JITT_PAT_DET_SHIFT 0
 
 
 /****************************************************************************
  * XFI_BD0 :: pmd_and_pcs_test_control_register
  */
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: tx_gptpat_ent [15:15] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_GPTPAT_ENT_MASK 0x8000
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_GPTPAT_ENT_ALIGN 0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_GPTPAT_ENT_BITS 1
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_GPTPAT_ENT_SHIFT 15
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: tx_6sqwave_ent [14:14] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_6SQWAVE_ENT_MASK 0x4000
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_6SQWAVE_ENT_ALIGN 0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_6SQWAVE_ENT_BITS 1
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_6SQWAVE_ENT_SHIFT 14
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: bist_ierr [13:13] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_BIST_IERR_MASK   0x2000
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_BIST_IERR_ALIGN  0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_BIST_IERR_BITS   1
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_BIST_IERR_SHIFT  13
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: tx_prbs7_en [12:12] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_PRBS7_EN_MASK 0x1000
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_PRBS7_EN_ALIGN 0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_PRBS7_EN_BITS 1
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_PRBS7_EN_SHIFT 12
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: tx_scrb_dis [11:11] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_SCRB_DIS_MASK 0x0800
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_SCRB_DIS_ALIGN 0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_SCRB_DIS_BITS 1
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_TX_SCRB_DIS_SHIFT 11
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: rx_descrb_dis [10:10] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_DESCRB_DIS_MASK 0x0400
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_DESCRB_DIS_ALIGN 0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_DESCRB_DIS_BITS 1
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_DESCRB_DIS_SHIFT 10
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: rx_buf_rd_on [09:09] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_ON_MASK 0x0200
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_ON_ALIGN 0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_ON_BITS 1
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_ON_SHIFT 9
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: rx_buf_rd_sel [08:07] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_SEL_MASK 0x0180
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_SEL_ALIGN 0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_SEL_BITS 2
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RX_BUF_RD_SEL_SHIFT 7
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: reserved0 [06:04] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED0_MASK   0x0070
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED0_ALIGN  0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED0_BITS   3
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED0_SHIFT  4
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: fec_dbg_err_mode [03:03] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_FEC_DBG_ERR_MODE_MASK 0x0008
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_FEC_DBG_ERR_MODE_ALIGN 0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_FEC_DBG_ERR_MODE_BITS 1
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_FEC_DBG_ERR_MODE_SHIFT 3
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: reserved1 [02:01] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED1_MASK   0x0006
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED1_ALIGN  0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED1_BITS   2
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_RESERVED1_SHIFT  1
 
 /* XFI_BD0 :: pmd_and_pcs_test_control_register :: pmd_pma_lineloopback [00:00] */
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_PMD_PMA_LINELOOPBACK_MASK 0x0001
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_PMD_PMA_LINELOOPBACK_ALIGN 0
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_PMD_PMA_LINELOOPBACK_BITS 1
 #define XFI_BD0_PMD_AND_PCS_TEST_CONTROL_REGISTER_PMD_PMA_LINELOOPBACK_SHIFT 0
 
 
 /****************************************************************************
  * XFI_BD0 :: pmd_general_purpose_tx_pattern_register_0
  */
 /* XFI_BD0 :: pmd_general_purpose_tx_pattern_register_0 :: pmd_tx_gprpat15_0 [15:00] */
 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0_PMD_TX_GPRPAT15_0_MASK 0xffff
 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0_PMD_TX_GPRPAT15_0_ALIGN 0
 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0_PMD_TX_GPRPAT15_0_BITS 16
 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_0_PMD_TX_GPRPAT15_0_SHIFT 0
 
 
 /****************************************************************************
  * XFI_BD0 :: pmd_general_purpose_tx_pattern_register_1
  */
 /* XFI_BD0 :: pmd_general_purpose_tx_pattern_register_1 :: pmd_tx_gprpat31_16 [15:00] */
 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1_PMD_TX_GPRPAT31_16_MASK 0xffff
 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1_PMD_TX_GPRPAT31_16_ALIGN 0
 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1_PMD_TX_GPRPAT31_16_BITS 16
 #define XFI_BD0_PMD_GENERAL_PURPOSE_TX_PATTERN_REGISTER_1_PMD_TX_GPRPAT31_16_SHIFT 0
 
 
 /****************************************************************************
  * Warpcore_USER_XFI_BD1
  */
 /****************************************************************************
  * XFI_BD1 :: prbs_31_test_window_1_register
  */
 /* XFI_BD1 :: prbs_31_test_window_1_register :: prbs31_win31_16 [15:00] */
 #define XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTER_PRBS31_WIN31_16_MASK 0xffff
 #define XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTER_PRBS31_WIN31_16_ALIGN 0
 #define XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTER_PRBS31_WIN31_16_BITS 16
 #define XFI_BD1_PRBS_31_TEST_WINDOW_1_REGISTER_PRBS31_WIN31_16_SHIFT 0
 
 
 /****************************************************************************
  * XFI_BD1 :: prbs_31_test_window_2_register
  */
 /* XFI_BD1 :: prbs_31_test_window_2_register :: reserved0 [15:13] */
 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_RESERVED0_MASK      0xe000
 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_RESERVED0_ALIGN     0
 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_RESERVED0_BITS      3
 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_RESERVED0_SHIFT     13
 
 /* XFI_BD1 :: prbs_31_test_window_2_register :: prbs31_win44_32 [12:00] */
 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_PRBS31_WIN44_32_MASK 0x1fff
 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_PRBS31_WIN44_32_ALIGN 0
 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_PRBS31_WIN44_32_BITS 13
 #define XFI_BD1_PRBS_31_TEST_WINDOW_2_REGISTER_PRBS31_WIN44_32_SHIFT 0
 
 
 /****************************************************************************
  * XFI_BD1 :: user_prbs_control_0_register
  */
 /* XFI_BD1 :: user_prbs_control_0_register :: prbs_inv_rx [15:15] */
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_RX_MASK      0x8000
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_RX_ALIGN     0
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_RX_BITS      1
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_RX_SHIFT     15
 
 /* XFI_BD1 :: user_prbs_control_0_register :: prbs_sel_rx [14:12] */
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_RX_MASK      0x7000
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_RX_ALIGN     0
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_RX_BITS      3
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_RX_SHIFT     12
 
 /* XFI_BD1 :: user_prbs_control_0_register :: reserved0 [11:05] */
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED0_MASK        0x0fe0
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED0_ALIGN       0
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED0_BITS        7
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED0_SHIFT       5
 
 /* XFI_BD1 :: user_prbs_control_0_register :: prbs_inv_tx [04:04] */
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_TX_MASK      0x0010
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_TX_ALIGN     0
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_TX_BITS      1
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_INV_TX_SHIFT     4
 
 /* XFI_BD1 :: user_prbs_control_0_register :: reserved1 [03:03] */
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED1_MASK        0x0008
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED1_ALIGN       0
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED1_BITS        1
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_RESERVED1_SHIFT       3
 
 /* XFI_BD1 :: user_prbs_control_0_register :: prbs_sel_tx [02:00] */
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_TX_MASK      0x0007
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_TX_ALIGN     0
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_TX_BITS      3
 #define XFI_BD1_USER_PRBS_CONTROL_0_REGISTER_PRBS_SEL_TX_SHIFT     0
 
 
 /****************************************************************************
  * XFI_BD1 :: user_prbs_status_0_register
  */
 /* XFI_BD1 :: user_prbs_status_0_register :: prbs_lock [15:15] */
 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_LOCK_MASK         0x8000
 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_LOCK_ALIGN        0
 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_LOCK_BITS         1
 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_LOCK_SHIFT        15
 
 /* XFI_BD1 :: user_prbs_status_0_register :: prbs_rx_errors [14:00] */
 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_RX_ERRORS_MASK    0x7fff
 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_RX_ERRORS_ALIGN   0
 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_RX_ERRORS_BITS    15
 #define XFI_BD1_USER_PRBS_STATUS_0_REGISTER_PRBS_RX_ERRORS_SHIFT   0
 
 
 /****************************************************************************
  * XFI_BD1 :: prbs_31_test_window_0_register
  */
 /* XFI_BD1 :: prbs_31_test_window_0_register :: prbs31_win15_0 [15:00] */
 #define XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTER_PRBS31_WIN15_0_MASK 0xffff
 #define XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTER_PRBS31_WIN15_0_ALIGN 0
 #define XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTER_PRBS31_WIN15_0_BITS 16
 #define XFI_BD1_PRBS_31_TEST_WINDOW_0_REGISTER_PRBS31_WIN15_0_SHIFT 0
 
 
 /****************************************************************************
  * XFI_BD1 :: pattern_insertion_control_register
  */
 /* XFI_BD1 :: pattern_insertion_control_register :: pattern_insertion_control [15:00] */
 #define XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTER_PATTERN_INSERTION_CONTROL_MASK 0xffff
 #define XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTER_PATTERN_INSERTION_CONTROL_ALIGN 0
 #define XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTER_PATTERN_INSERTION_CONTROL_BITS 16
 #define XFI_BD1_PATTERN_INSERTION_CONTROL_REGISTER_PATTERN_INSERTION_CONTROL_SHIFT 0
 
 
 /****************************************************************************
  * Warpcore_USER_microBlk
  */
 /****************************************************************************
  * microBlk :: ramword
  */
 /* microBlk :: ramword :: ram_count [15:00] */
 #define MICROBLK_RAMWORD_RAM_COUNT_MASK                            0xffff
 #define MICROBLK_RAMWORD_RAM_COUNT_ALIGN                           0
 #define MICROBLK_RAMWORD_RAM_COUNT_BITS                            16
 #define MICROBLK_RAMWORD_RAM_COUNT_SHIFT                           0
 
 
 /****************************************************************************
  * microBlk :: address
  */
 /* microBlk :: address :: ram_address [15:00] */
 #define MICROBLK_ADDRESS_RAM_ADDRESS_MASK                          0xffff
 #define MICROBLK_ADDRESS_RAM_ADDRESS_ALIGN                         0
 #define MICROBLK_ADDRESS_RAM_ADDRESS_BITS                          16
 #define MICROBLK_ADDRESS_RAM_ADDRESS_SHIFT                         0
 
 
 /****************************************************************************
  * microBlk :: command
  */
 /* microBlk :: command :: init_cmd [15:15] */
 #define MICROBLK_COMMAND_INIT_CMD_MASK                             0x8000
 #define MICROBLK_COMMAND_INIT_CMD_ALIGN                            0
 #define MICROBLK_COMMAND_INIT_CMD_BITS                             1
 #define MICROBLK_COMMAND_INIT_CMD_SHIFT                            15
 
 /* microBlk :: command :: uc_md_en_override [14:14] */
 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_MASK                    0x4000
 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_ALIGN                   0
 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_BITS                    1
 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_SHIFT                   14
 
 /* microBlk :: command :: uc_md_en_override_value [13:13] */
 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_VALUE_MASK              0x2000
 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_VALUE_ALIGN             0
 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_VALUE_BITS              1
 #define MICROBLK_COMMAND_UC_MD_EN_OVERRIDE_VALUE_SHIFT             13
 
 /* microBlk :: command :: mdio_ram_cs_force_val [12:12] */
 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_VAL_MASK                0x1000
 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_VAL_ALIGN               0
 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_VAL_BITS                1
 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_VAL_SHIFT               12
 
 /* microBlk :: command :: mdio_ram_cs_force [11:11] */
 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_MASK                    0x0800
 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_ALIGN                   0
 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_BITS                    1
 #define MICROBLK_COMMAND_MDIO_RAM_CS_FORCE_SHIFT                   11
 
 /* microBlk :: command :: mdio_autowakeup [10:10] */
 #define MICROBLK_COMMAND_MDIO_AUTOWAKEUP_MASK                      0x0400
 #define MICROBLK_COMMAND_MDIO_AUTOWAKEUP_ALIGN                     0
 #define MICROBLK_COMMAND_MDIO_AUTOWAKEUP_BITS                      1
 #define MICROBLK_COMMAND_MDIO_AUTOWAKEUP_SHIFT                     10
 
 /* microBlk :: command :: byte_mode [09:09] */
 #define MICROBLK_COMMAND_BYTE_MODE_MASK                            0x0200
 #define MICROBLK_COMMAND_BYTE_MODE_ALIGN                           0
 #define MICROBLK_COMMAND_BYTE_MODE_BITS                            1
 #define MICROBLK_COMMAND_BYTE_MODE_SHIFT                           9
 
 /* microBlk :: command :: refdiv4_en_int [08:08] */
 #define MICROBLK_COMMAND_REFDIV4_EN_INT_MASK                       0x0100
 #define MICROBLK_COMMAND_REFDIV4_EN_INT_ALIGN                      0
 #define MICROBLK_COMMAND_REFDIV4_EN_INT_BITS                       1
 #define MICROBLK_COMMAND_REFDIV4_EN_INT_SHIFT                      8
 
 /* microBlk :: command :: refdiv2_en_int [07:07] */
 #define MICROBLK_COMMAND_REFDIV2_EN_INT_MASK                       0x0080
 #define MICROBLK_COMMAND_REFDIV2_EN_INT_ALIGN                      0
 #define MICROBLK_COMMAND_REFDIV2_EN_INT_BITS                       1
 #define MICROBLK_COMMAND_REFDIV2_EN_INT_SHIFT                      7
 
 /* microBlk :: command :: mdio_disable_ucclk [06:06] */
 #define MICROBLK_COMMAND_MDIO_DISABLE_UCCLK_MASK                   0x0040
 #define MICROBLK_COMMAND_MDIO_DISABLE_UCCLK_ALIGN                  0
 #define MICROBLK_COMMAND_MDIO_DISABLE_UCCLK_BITS                   1
 #define MICROBLK_COMMAND_MDIO_DISABLE_UCCLK_SHIFT                  6
 
 /* microBlk :: command :: reserved_for_eco0 [05:05] */
 #define MICROBLK_COMMAND_RESERVED_FOR_ECO0_MASK                    0x0020
 #define MICROBLK_COMMAND_RESERVED_FOR_ECO0_ALIGN                   0
 #define MICROBLK_COMMAND_RESERVED_FOR_ECO0_BITS                    1
 #define MICROBLK_COMMAND_RESERVED_FOR_ECO0_SHIFT                   5
 
 /* microBlk :: command :: mdio_uC_reset_n [04:04] */
 #define MICROBLK_COMMAND_MDIO_UC_RESET_N_MASK                      0x0010
 #define MICROBLK_COMMAND_MDIO_UC_RESET_N_ALIGN                     0
 #define MICROBLK_COMMAND_MDIO_UC_RESET_N_BITS                      1
 #define MICROBLK_COMMAND_MDIO_UC_RESET_N_SHIFT                     4
 
 /* microBlk :: command :: write [03:03] */
 #define MICROBLK_COMMAND_WRITE_MASK                                0x0008
 #define MICROBLK_COMMAND_WRITE_ALIGN                               0
 #define MICROBLK_COMMAND_WRITE_BITS                                1
 #define MICROBLK_COMMAND_WRITE_SHIFT                               3
 
 /* microBlk :: command :: read [02:02] */
 #define MICROBLK_COMMAND_READ_MASK                                 0x0004
 #define MICROBLK_COMMAND_READ_ALIGN                                0
 #define MICROBLK_COMMAND_READ_BITS                                 1
 #define MICROBLK_COMMAND_READ_SHIFT                                2
 
 /* microBlk :: command :: stop [01:01] */
 #define MICROBLK_COMMAND_STOP_MASK                                 0x0002
 #define MICROBLK_COMMAND_STOP_ALIGN                                0
 #define MICROBLK_COMMAND_STOP_BITS                                 1
 #define MICROBLK_COMMAND_STOP_SHIFT                                1
 
 /* microBlk :: command :: run [00:00] */
 #define MICROBLK_COMMAND_RUN_MASK                                  0x0001
 #define MICROBLK_COMMAND_RUN_ALIGN                                 0
 #define MICROBLK_COMMAND_RUN_BITS                                  1
 #define MICROBLK_COMMAND_RUN_SHIFT                                 0
 
 
 /****************************************************************************
  * microBlk :: wrdata
  */
 /* microBlk :: wrdata :: wrdata [15:00] */
 #define MICROBLK_WRDATA_WRDATA_MASK                                0xffff
 #define MICROBLK_WRDATA_WRDATA_ALIGN                               0
 #define MICROBLK_WRDATA_WRDATA_BITS                                16
 #define MICROBLK_WRDATA_WRDATA_SHIFT                               0
 
 
 /****************************************************************************
  * microBlk :: rddata
  */
 /* microBlk :: rddata :: rddata [15:00] */
 #define MICROBLK_RDDATA_RDDATA_MASK                                0xffff
 #define MICROBLK_RDDATA_RDDATA_ALIGN                               0
 #define MICROBLK_RDDATA_RDDATA_BITS                                16
 #define MICROBLK_RDDATA_RDDATA_SHIFT                               0
 
 
 /****************************************************************************
  * microBlk :: download_status
  */
 /* microBlk :: download_status :: init_done [15:15] */
 #define MICROBLK_DOWNLOAD_STATUS_INIT_DONE_MASK                    0x8000
 #define MICROBLK_DOWNLOAD_STATUS_INIT_DONE_ALIGN                   0
 #define MICROBLK_DOWNLOAD_STATUS_INIT_DONE_BITS                    1
 #define MICROBLK_DOWNLOAD_STATUS_INIT_DONE_SHIFT                   15
 
 /* microBlk :: download_status :: reserved0 [14:06] */
 #define MICROBLK_DOWNLOAD_STATUS_RESERVED0_MASK                    0x7fc0
 #define MICROBLK_DOWNLOAD_STATUS_RESERVED0_ALIGN                   0
 #define MICROBLK_DOWNLOAD_STATUS_RESERVED0_BITS                    9
 #define MICROBLK_DOWNLOAD_STATUS_RESERVED0_SHIFT                   6
 
 /* microBlk :: download_status :: FSM [05:02] */
 #define MICROBLK_DOWNLOAD_STATUS_FSM_MASK                          0x003c
 #define MICROBLK_DOWNLOAD_STATUS_FSM_ALIGN                         0
 #define MICROBLK_DOWNLOAD_STATUS_FSM_BITS                          4
 #define MICROBLK_DOWNLOAD_STATUS_FSM_SHIFT                         2
 
 /* microBlk :: download_status :: ERR1 [01:01] */
 #define MICROBLK_DOWNLOAD_STATUS_ERR1_MASK                         0x0002
 #define MICROBLK_DOWNLOAD_STATUS_ERR1_ALIGN                        0
 #define MICROBLK_DOWNLOAD_STATUS_ERR1_BITS                         1
 #define MICROBLK_DOWNLOAD_STATUS_ERR1_SHIFT                        1
 
 /* microBlk :: download_status :: ERR0 [00:00] */
 #define MICROBLK_DOWNLOAD_STATUS_ERR0_MASK                         0x0001
 #define MICROBLK_DOWNLOAD_STATUS_ERR0_ALIGN                        0
 #define MICROBLK_DOWNLOAD_STATUS_ERR0_BITS                         1
 #define MICROBLK_DOWNLOAD_STATUS_ERR0_SHIFT                        0
 
 
 /****************************************************************************
  * microBlk :: sfr_status
  */
 /* union - case ecc_error_counters [15:00] */
 /* microBlk :: sfr_status :: ecc_error_counters [15:00] */
 #define MICROBLK_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_MASK 0xffff
 #define MICROBLK_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_ALIGN 0
 #define MICROBLK_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_BITS 16
 #define MICROBLK_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_SHIFT 0
 
 
 /* union - case dw8051_to_pcb_fsm_L [15:00] */
 /* microBlk :: sfr_status :: dw8051_to_pcb_fsm_L [15:00] */
 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_MASK 0xffff
 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_ALIGN 0
 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_BITS 16
 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_SHIFT 0
 
 
 /* union - case dw8051_to_pcb_fsm_U [15:00] */
 /* microBlk :: sfr_status :: dw8051_to_pcb_fsm_U [15:00] */
 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_MASK 0xffff
 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_ALIGN 0
 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_BITS 16
 #define MICROBLK_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_SHIFT 0
 
 
 
 /****************************************************************************
  * microBlk :: command4
  */
 /* microBlk :: command4 :: reserved_for_eco0 [15:06] */
 #define MICROBLK_COMMAND4_RESERVED_FOR_ECO0_MASK                   0xffc0
 #define MICROBLK_COMMAND4_RESERVED_FOR_ECO0_ALIGN                  0
 #define MICROBLK_COMMAND4_RESERVED_FOR_ECO0_BITS                   10
 #define MICROBLK_COMMAND4_RESERVED_FOR_ECO0_SHIFT                  6
 
 /* microBlk :: command4 :: mdio_eitu_int5 [05:05] */
 #define MICROBLK_COMMAND4_MDIO_EITU_INT5_MASK                      0x0020
 #define MICROBLK_COMMAND4_MDIO_EITU_INT5_ALIGN                     0
 #define MICROBLK_COMMAND4_MDIO_EITU_INT5_BITS                      1
 #define MICROBLK_COMMAND4_MDIO_EITU_INT5_SHIFT                     5
 
 /* microBlk :: command4 :: mdio_eitu_int4 [04:04] */
 #define MICROBLK_COMMAND4_MDIO_EITU_INT4_MASK                      0x0010
 #define MICROBLK_COMMAND4_MDIO_EITU_INT4_ALIGN                     0
 #define MICROBLK_COMMAND4_MDIO_EITU_INT4_BITS                      1
 #define MICROBLK_COMMAND4_MDIO_EITU_INT4_SHIFT                     4
 
 /* microBlk :: command4 :: mdio_eitu_int3 [03:03] */
 #define MICROBLK_COMMAND4_MDIO_EITU_INT3_MASK                      0x0008
 #define MICROBLK_COMMAND4_MDIO_EITU_INT3_ALIGN                     0
 #define MICROBLK_COMMAND4_MDIO_EITU_INT3_BITS                      1
 #define MICROBLK_COMMAND4_MDIO_EITU_INT3_SHIFT                     3
 
 /* microBlk :: command4 :: mdio_eitu_int2 [02:02] */
 #define MICROBLK_COMMAND4_MDIO_EITU_INT2_MASK                      0x0004
 #define MICROBLK_COMMAND4_MDIO_EITU_INT2_ALIGN                     0
 #define MICROBLK_COMMAND4_MDIO_EITU_INT2_BITS                      1
 #define MICROBLK_COMMAND4_MDIO_EITU_INT2_SHIFT                     2
 
 /* microBlk :: command4 :: mdio_eitu_int1 [01:01] */
 #define MICROBLK_COMMAND4_MDIO_EITU_INT1_MASK                      0x0002
 #define MICROBLK_COMMAND4_MDIO_EITU_INT1_ALIGN                     0
 #define MICROBLK_COMMAND4_MDIO_EITU_INT1_BITS                      1
 #define MICROBLK_COMMAND4_MDIO_EITU_INT1_SHIFT                     1
 
 /* microBlk :: command4 :: mdio_eitu_int0 [00:00] */
 #define MICROBLK_COMMAND4_MDIO_EITU_INT0_MASK                      0x0001
 #define MICROBLK_COMMAND4_MDIO_EITU_INT0_ALIGN                     0
 #define MICROBLK_COMMAND4_MDIO_EITU_INT0_BITS                      1
 #define MICROBLK_COMMAND4_MDIO_EITU_INT0_SHIFT                     0
 
 
 /****************************************************************************
  * microBlk :: mdio_uC_mailbox
  */
 /* microBlk :: mdio_uC_mailbox :: mdio_uC_mailbox [15:00] */
 #define MICROBLK_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_MASK              0xffff
 #define MICROBLK_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_ALIGN             0
 #define MICROBLK_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_BITS              16
 #define MICROBLK_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_SHIFT             0
 
 
 /****************************************************************************
  * microBlk :: uC_mdio_mailbox
  */
 /* microBlk :: uC_mdio_mailbox :: uC_mdio_mailbox [15:00] */
 #define MICROBLK_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_MASK              0xffff
 #define MICROBLK_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_ALIGN             0
 #define MICROBLK_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_BITS              16
 #define MICROBLK_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_SHIFT             0
 
 
 /****************************************************************************
  * microBlk :: command2
  */
 /* microBlk :: command2 :: mdio_to_8051_reset [15:15] */
 #define MICROBLK_COMMAND2_MDIO_TO_8051_RESET_MASK                  0x8000
 #define MICROBLK_COMMAND2_MDIO_TO_8051_RESET_ALIGN                 0
 #define MICROBLK_COMMAND2_MDIO_TO_8051_RESET_BITS                  1
 #define MICROBLK_COMMAND2_MDIO_TO_8051_RESET_SHIFT                 15
 
 /* microBlk :: command2 :: m8051_to_pcb_reset [14:14] */
 #define MICROBLK_COMMAND2_M8051_TO_PCB_RESET_MASK                  0x4000
 #define MICROBLK_COMMAND2_M8051_TO_PCB_RESET_ALIGN                 0
 #define MICROBLK_COMMAND2_M8051_TO_PCB_RESET_BITS                  1
 #define MICROBLK_COMMAND2_M8051_TO_PCB_RESET_SHIFT                 14
 
 /* microBlk :: command2 :: firmware_reset_disable [13:13] */
 #define MICROBLK_COMMAND2_FIRMWARE_RESET_DISABLE_MASK              0x2000
 #define MICROBLK_COMMAND2_FIRMWARE_RESET_DISABLE_ALIGN             0
 #define MICROBLK_COMMAND2_FIRMWARE_RESET_DISABLE_BITS              1
 #define MICROBLK_COMMAND2_FIRMWARE_RESET_DISABLE_SHIFT             13
 
 /* microBlk :: command2 :: zero_rom_dataout [12:12] */
 #define MICROBLK_COMMAND2_ZERO_ROM_DATAOUT_MASK                    0x1000
 #define MICROBLK_COMMAND2_ZERO_ROM_DATAOUT_ALIGN                   0
 #define MICROBLK_COMMAND2_ZERO_ROM_DATAOUT_BITS                    1
 #define MICROBLK_COMMAND2_ZERO_ROM_DATAOUT_SHIFT                   12
 
 /* microBlk :: command2 :: reserved_for_eco0 [11:10] */
 #define MICROBLK_COMMAND2_RESERVED_FOR_ECO0_MASK                   0x0c00
 #define MICROBLK_COMMAND2_RESERVED_FOR_ECO0_ALIGN                  0
 #define MICROBLK_COMMAND2_RESERVED_FOR_ECO0_BITS                   2
 #define MICROBLK_COMMAND2_RESERVED_FOR_ECO0_SHIFT                  10
 
 /* microBlk :: command2 :: timer_mux_sel [09:08] */
 #define MICROBLK_COMMAND2_TIMER_MUX_SEL_MASK                       0x0300
 #define MICROBLK_COMMAND2_TIMER_MUX_SEL_ALIGN                      0
 #define MICROBLK_COMMAND2_TIMER_MUX_SEL_BITS                       2
 #define MICROBLK_COMMAND2_TIMER_MUX_SEL_SHIFT                      8
 
 /* microBlk :: command2 :: wdog_disable [07:07] */
 #define MICROBLK_COMMAND2_WDOG_DISABLE_MASK                        0x0080
 #define MICROBLK_COMMAND2_WDOG_DISABLE_ALIGN                       0
 #define MICROBLK_COMMAND2_WDOG_DISABLE_BITS                        1
 #define MICROBLK_COMMAND2_WDOG_DISABLE_SHIFT                       7
 
 /* microBlk :: command2 :: refdiv4_tmr_en [06:06] */
 #define MICROBLK_COMMAND2_REFDIV4_TMR_EN_MASK                      0x0040
 #define MICROBLK_COMMAND2_REFDIV4_TMR_EN_ALIGN                     0
 #define MICROBLK_COMMAND2_REFDIV4_TMR_EN_BITS                      1
 #define MICROBLK_COMMAND2_REFDIV4_TMR_EN_SHIFT                     6
 
 /* microBlk :: command2 :: refdiv2_tmr_en [05:05] */
 #define MICROBLK_COMMAND2_REFDIV2_TMR_EN_MASK                      0x0020
 #define MICROBLK_COMMAND2_REFDIV2_TMR_EN_ALIGN                     0
 #define MICROBLK_COMMAND2_REFDIV2_TMR_EN_BITS                      1
 #define MICROBLK_COMMAND2_REFDIV2_TMR_EN_SHIFT                     5
 
 /* microBlk :: command2 :: wdog_en [04:04] */
 #define MICROBLK_COMMAND2_WDOG_EN_MASK                             0x0010
 #define MICROBLK_COMMAND2_WDOG_EN_ALIGN                            0
 #define MICROBLK_COMMAND2_WDOG_EN_BITS                             1
 #define MICROBLK_COMMAND2_WDOG_EN_SHIFT                            4
 
 /* microBlk :: command2 :: tmr_en [03:00] */
 #define MICROBLK_COMMAND2_TMR_EN_MASK                              0x000f
 #define MICROBLK_COMMAND2_TMR_EN_ALIGN                             0
 #define MICROBLK_COMMAND2_TMR_EN_BITS                              4
 #define MICROBLK_COMMAND2_TMR_EN_SHIFT                             0
 
 
 /****************************************************************************
  * microBlk :: wdog_evnt_cnt
  */
 /* microBlk :: wdog_evnt_cnt :: wdog_evnt_cnt [15:00] */
 #define MICROBLK_WDOG_EVNT_CNT_WDOG_EVNT_CNT_MASK                  0xffff
 #define MICROBLK_WDOG_EVNT_CNT_WDOG_EVNT_CNT_ALIGN                 0
 #define MICROBLK_WDOG_EVNT_CNT_WDOG_EVNT_CNT_BITS                  16
 #define MICROBLK_WDOG_EVNT_CNT_WDOG_EVNT_CNT_SHIFT                 0
 
 
 /****************************************************************************
  * microBlk :: command3
  */
 /* microBlk :: command3 :: gen_status_sel [15:12] */
 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_MASK                      0xf000
 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_ALIGN                     0
 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_BITS                      4
 #define MICROBLK_COMMAND3_GEN_STATUS_SEL_SHIFT                     12
 
 /* microBlk :: command3 :: disable_ecc [11:11] */
 #define MICROBLK_COMMAND3_DISABLE_ECC_MASK                         0x0800
 #define MICROBLK_COMMAND3_DISABLE_ECC_ALIGN                        0
 #define MICROBLK_COMMAND3_DISABLE_ECC_BITS                         1
 #define MICROBLK_COMMAND3_DISABLE_ECC_SHIFT                        11
 
 /* microBlk :: command3 :: out_staging_flop_bypass [10:10] */
 #define MICROBLK_COMMAND3_OUT_STAGING_FLOP_BYPASS_MASK             0x0400
 #define MICROBLK_COMMAND3_OUT_STAGING_FLOP_BYPASS_ALIGN            0
 #define MICROBLK_COMMAND3_OUT_STAGING_FLOP_BYPASS_BITS             1
 #define MICROBLK_COMMAND3_OUT_STAGING_FLOP_BYPASS_SHIFT            10
 
 /* microBlk :: command3 :: tm [09:05] */
 #define MICROBLK_COMMAND3_TM_MASK                                  0x03e0
 #define MICROBLK_COMMAND3_TM_ALIGN                                 0
 #define MICROBLK_COMMAND3_TM_BITS                                  5
 #define MICROBLK_COMMAND3_TM_SHIFT                                 5
 
 /* microBlk :: command3 :: pm_override_value [04:04] */
 #define MICROBLK_COMMAND3_PM_OVERRIDE_VALUE_MASK                   0x0010
 #define MICROBLK_COMMAND3_PM_OVERRIDE_VALUE_ALIGN                  0
 #define MICROBLK_COMMAND3_PM_OVERRIDE_VALUE_BITS                   1
 #define MICROBLK_COMMAND3_PM_OVERRIDE_VALUE_SHIFT                  4
 
 /* microBlk :: command3 :: enable_pm_override [03:03] */
 #define MICROBLK_COMMAND3_ENABLE_PM_OVERRIDE_MASK                  0x0008
 #define MICROBLK_COMMAND3_ENABLE_PM_OVERRIDE_ALIGN                 0
 #define MICROBLK_COMMAND3_ENABLE_PM_OVERRIDE_BITS                  1
 #define MICROBLK_COMMAND3_ENABLE_PM_OVERRIDE_SHIFT                 3
 
 /* microBlk :: command3 :: in_staging_flop_bypass [02:02] */
 #define MICROBLK_COMMAND3_IN_STAGING_FLOP_BYPASS_MASK              0x0004
 #define MICROBLK_COMMAND3_IN_STAGING_FLOP_BYPASS_ALIGN             0
 #define MICROBLK_COMMAND3_IN_STAGING_FLOP_BYPASS_BITS              1
 #define MICROBLK_COMMAND3_IN_STAGING_FLOP_BYPASS_SHIFT             2
 
 /* microBlk :: command3 :: ext_clk_enable [01:01] */
 #define MICROBLK_COMMAND3_EXT_CLK_ENABLE_MASK                      0x0002
 #define MICROBLK_COMMAND3_EXT_CLK_ENABLE_ALIGN                     0
 #define MICROBLK_COMMAND3_EXT_CLK_ENABLE_BITS                      1
 #define MICROBLK_COMMAND3_EXT_CLK_ENABLE_SHIFT                     1
 
 /* microBlk :: command3 :: ext_mem_enable [00:00] */
 #define MICROBLK_COMMAND3_EXT_MEM_ENABLE_MASK                      0x0001
 #define MICROBLK_COMMAND3_EXT_MEM_ENABLE_ALIGN                     0
 #define MICROBLK_COMMAND3_EXT_MEM_ENABLE_BITS                      1
 #define MICROBLK_COMMAND3_EXT_MEM_ENABLE_SHIFT                     0
 
 
 /****************************************************************************
  * microBlk :: timer_lower16
  */
 /* microBlk :: timer_lower16 :: timer_lower16bits [15:00] */
 #define MICROBLK_TIMER_LOWER16_TIMER_LOWER16BITS_MASK              0xffff
 #define MICROBLK_TIMER_LOWER16_TIMER_LOWER16BITS_ALIGN             0
 #define MICROBLK_TIMER_LOWER16_TIMER_LOWER16BITS_BITS              16
 #define MICROBLK_TIMER_LOWER16_TIMER_LOWER16BITS_SHIFT             0
 
 
 /****************************************************************************
  * microBlk :: timer_upper16
  */
 /* microBlk :: timer_upper16 :: timer_upper16bits [15:00] */
 #define MICROBLK_TIMER_UPPER16_TIMER_UPPER16BITS_MASK              0xffff
 #define MICROBLK_TIMER_UPPER16_TIMER_UPPER16BITS_ALIGN             0
 #define MICROBLK_TIMER_UPPER16_TIMER_UPPER16BITS_BITS              16
 #define MICROBLK_TIMER_UPPER16_TIMER_UPPER16BITS_SHIFT             0
 
 
 /****************************************************************************
  * Warpcore_USER_aerBlk
  */
 /****************************************************************************
  * aerBlk :: aer
  */
 /* aerBlk :: aer :: MMD_deviceType [15:11] */
 #define AERBLK_AER_MMD_DEVICETYPE_MASK                             0xf800
 #define AERBLK_AER_MMD_DEVICETYPE_ALIGN                            0
 #define AERBLK_AER_MMD_DEVICETYPE_BITS                             5
 #define AERBLK_AER_MMD_DEVICETYPE_SHIFT                            11
 #define AERBLK_AER_MMD_DEVICETYPE_combo_core                       0
 #define AERBLK_AER_MMD_DEVICETYPE_PMA_PMD                          1
 #define AERBLK_AER_MMD_DEVICETYPE_PCS                              3
 #define AERBLK_AER_MMD_DEVICETYPE_PHY                              4
 #define AERBLK_AER_MMD_DEVICETYPE_DTE                              5
 #define AERBLK_AER_MMD_DEVICETYPE_CL73_AN                          7
 
 /* aerBlk :: aer :: MMD_port [10:00] */
 #define AERBLK_AER_MMD_PORT_MASK                                   0x07ff
 #define AERBLK_AER_MMD_PORT_ALIGN                                  0
 #define AERBLK_AER_MMD_PORT_BITS                                   11
 #define AERBLK_AER_MMD_PORT_SHIFT                                  0
 #define AERBLK_AER_MMD_PORT_ln0                                    0
 #define AERBLK_AER_MMD_PORT_ln1                                    1
 #define AERBLK_AER_MMD_PORT_ln2                                    2
 #define AERBLK_AER_MMD_PORT_ln3                                    3
 #define AERBLK_AER_MMD_PORT_BCST                                   511
 
 
 /****************************************************************************
  * Warpcore_USER_Combo_IEEE0
  */
 /****************************************************************************
  * Combo_IEEE0 :: MIICntl
  */
 /* Combo_IEEE0 :: MIICntl :: rst_hw [15:15] */
 #define COMBO_IEEE0_MIICNTL_RST_HW_MASK                            0x8000
 #define COMBO_IEEE0_MIICNTL_RST_HW_ALIGN                           0
 #define COMBO_IEEE0_MIICNTL_RST_HW_BITS                            1
 #define COMBO_IEEE0_MIICNTL_RST_HW_SHIFT                           15
 
 /* Combo_IEEE0 :: MIICntl :: gloopback [14:14] */
 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_MASK                         0x4000
 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_ALIGN                        0
 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_BITS                         1
 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_SHIFT                        14
 
 /* Combo_IEEE0 :: MIICntl :: manual_speed0 [13:13] */
 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_MASK                     0x2000
 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_ALIGN                    0
 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_BITS                     1
 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_SHIFT                    13
 
 /* Combo_IEEE0 :: MIICntl :: autoneg_enable [12:12] */
 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_MASK                    0x1000
 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_ALIGN                   0
 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_BITS                    1
 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_SHIFT                   12
 
 /* Combo_IEEE0 :: MIICntl :: pwrdwn_sw [11:11] */
 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_MASK                         0x0800
 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_ALIGN                        0
 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_BITS                         1
 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_SHIFT                        11
 
 /* Combo_IEEE0 :: MIICntl :: reserved0 [10:10] */
 #define COMBO_IEEE0_MIICNTL_RESERVED0_MASK                         0x0400
 #define COMBO_IEEE0_MIICNTL_RESERVED0_ALIGN                        0
 #define COMBO_IEEE0_MIICNTL_RESERVED0_BITS                         1
 #define COMBO_IEEE0_MIICNTL_RESERVED0_SHIFT                        10
 
 /* Combo_IEEE0 :: MIICntl :: restart_autoneg [09:09] */
 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_MASK                   0x0200
 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_ALIGN                  0
 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_BITS                   1
 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_SHIFT                  9
 
 /* Combo_IEEE0 :: MIICntl :: full_duplex [08:08] */
 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_MASK                       0x0100
 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_ALIGN                      0
 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_BITS                       1
 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_SHIFT                      8
 
 /* Combo_IEEE0 :: MIICntl :: collision_test_en [07:07] */
 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_MASK                 0x0080
 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_ALIGN                0
 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_BITS                 1
 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_SHIFT                7
 
 /* Combo_IEEE0 :: MIICntl :: manual_speed1 [06:06] */
 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_MASK                     0x0040
 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_ALIGN                    0
 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_BITS                     1
 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_SHIFT                    6
 
 /* Combo_IEEE0 :: MIICntl :: reserved1 [05:00] */
 #define COMBO_IEEE0_MIICNTL_RESERVED1_MASK                         0x003f
 #define COMBO_IEEE0_MIICNTL_RESERVED1_ALIGN                        0
 #define COMBO_IEEE0_MIICNTL_RESERVED1_BITS                         6
 #define COMBO_IEEE0_MIICNTL_RESERVED1_SHIFT                        0
 
 
 /****************************************************************************
  * Combo_IEEE0 :: MIIStat
  */
 /* Combo_IEEE0 :: MIIStat :: s100BASE_T4_capable [15:15] */
 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_MASK               0x8000
 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN              0
 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_BITS               1
 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT              15
 
 /* Combo_IEEE0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK    0x4000
 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN   0
 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS    1
 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT   14
 
 /* Combo_IEEE0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK    0x2000
 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN   0
 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS    1
 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT   13
 
 /* Combo_IEEE0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK     0x1000
 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN    0
 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS     1
 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT    12
 
 /* Combo_IEEE0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK     0x0800
 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN    0
 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS     1
 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT    11
 
 /* Combo_IEEE0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK   0x0400
 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN  0
 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS   1
 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT  10
 
 /* Combo_IEEE0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK   0x0200
 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN  0
 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS   1
 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT  9
 
 /* Combo_IEEE0 :: MIIStat :: extended_status [08:08] */
 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_MASK                   0x0100
 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_ALIGN                  0
 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_BITS                   1
 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_SHIFT                  8
 
 /* Combo_IEEE0 :: MIIStat :: reserved0 [07:07] */
 #define COMBO_IEEE0_MIISTAT_RESERVED0_MASK                         0x0080
 #define COMBO_IEEE0_MIISTAT_RESERVED0_ALIGN                        0
 #define COMBO_IEEE0_MIISTAT_RESERVED0_BITS                         1
 #define COMBO_IEEE0_MIISTAT_RESERVED0_SHIFT                        7
 
 /* Combo_IEEE0 :: MIIStat :: mf_preamble_supression [06:06] */
 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK            0x0040
 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN           0
 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS            1
 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT           6
 
 /* Combo_IEEE0 :: MIIStat :: autoneg_complete [05:05] */
 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_MASK                  0x0020
 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_ALIGN                 0
 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_BITS                  1
 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_SHIFT                 5
 
 /* Combo_IEEE0 :: MIIStat :: remote_fault [04:04] */
 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_MASK                      0x0010
 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_ALIGN                     0
 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_BITS                      1
 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_SHIFT                     4
 
 /* Combo_IEEE0 :: MIIStat :: autoneg_ability [03:03] */
 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_MASK                   0x0008
 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_ALIGN                  0
 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_BITS                   1
 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_SHIFT                  3
 
 /* Combo_IEEE0 :: MIIStat :: link_status [02:02] */
 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_MASK                       0x0004
 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_ALIGN                      0
 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_BITS                       1
 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_SHIFT                      2
 
 /* Combo_IEEE0 :: MIIStat :: jabber_detect [01:01] */
 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_MASK                     0x0002
 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_ALIGN                    0
 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_BITS                     1
 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_SHIFT                    1
 
 /* Combo_IEEE0 :: MIIStat :: extended_capability [00:00] */
 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_MASK               0x0001
 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_ALIGN              0
 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_BITS               1
 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_SHIFT              0
 
 
 /****************************************************************************
  * Combo_IEEE0 :: Id1
  */
 /* Combo_IEEE0 :: Id1 :: regid [15:00] */
 #define COMBO_IEEE0_ID1_REGID_MASK                                 0xffff
 #define COMBO_IEEE0_ID1_REGID_ALIGN                                0
 #define COMBO_IEEE0_ID1_REGID_BITS                                 16
 #define COMBO_IEEE0_ID1_REGID_SHIFT                                0
 
 
 /****************************************************************************
  * Combo_IEEE0 :: Id2
  */
 /* Combo_IEEE0 :: Id2 :: regid [15:00] */
 #define COMBO_IEEE0_ID2_REGID_MASK                                 0xffff
 #define COMBO_IEEE0_ID2_REGID_ALIGN                                0
 #define COMBO_IEEE0_ID2_REGID_BITS                                 16
 #define COMBO_IEEE0_ID2_REGID_SHIFT                                0
 
 
 /****************************************************************************
  * Combo_IEEE0 :: AutoNegAdv
  */
 /* Combo_IEEE0 :: AutoNegAdv :: next_page [15:15] */
 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_MASK                      0x8000
 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_ALIGN                     0
 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_BITS                      1
 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_SHIFT                     15
 
 /* Combo_IEEE0 :: AutoNegAdv :: reserved0 [14:14] */
 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_MASK                      0x4000
 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_ALIGN                     0
 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_BITS                      1
 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_SHIFT                     14
 
 /* Combo_IEEE0 :: AutoNegAdv :: remote_fault [13:12] */
 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_MASK                   0x3000
 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_ALIGN                  0
 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_BITS                   2
 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_SHIFT                  12
 
 /* Combo_IEEE0 :: AutoNegAdv :: reserved1 [11:09] */
 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_MASK                      0x0e00
 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_ALIGN                     0
 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_BITS                      3
 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_SHIFT                     9
 
 /* Combo_IEEE0 :: AutoNegAdv :: pause [08:07] */
 #define COMBO_IEEE0_AUTONEGADV_PAUSE_MASK                          0x0180
 #define COMBO_IEEE0_AUTONEGADV_PAUSE_ALIGN                         0
 #define COMBO_IEEE0_AUTONEGADV_PAUSE_BITS                          2
 #define COMBO_IEEE0_AUTONEGADV_PAUSE_SHIFT                         7
 
 /* Combo_IEEE0 :: AutoNegAdv :: half_duplex [06:06] */
 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_MASK                    0x0040
 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_ALIGN                   0
 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_BITS                    1
 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_SHIFT                   6
 
 /* Combo_IEEE0 :: AutoNegAdv :: full_duplex [05:05] */
 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_MASK                    0x0020
 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_ALIGN                   0
 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_BITS                    1
 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_SHIFT                   5
 
 /* Combo_IEEE0 :: AutoNegAdv :: reserved2 [04:00] */
 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_MASK                      0x001f
 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_ALIGN                     0
 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_BITS                      5
 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_SHIFT                     0
 
 
 /****************************************************************************
  * Combo_IEEE0 :: AutoNegLPAbil
  */
 /* Combo_IEEE0 :: AutoNegLPAbil :: next_page [15:15] */
 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_MASK                   0x8000
 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_ALIGN                  0
 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_BITS                   1
 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_SHIFT                  15
 
 /* Combo_IEEE0 :: AutoNegLPAbil :: acknowledge [14:14] */
 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_MASK                 0x4000
 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN                0
 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_BITS                 1
 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT                14
 
 /* Combo_IEEE0 :: AutoNegLPAbil :: remote_fault [13:12] */
 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_MASK                0x3000
 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN               0
 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_BITS                2
 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT               12
 
 /* Combo_IEEE0 :: AutoNegLPAbil :: reserved0 [11:09] */
 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_MASK                   0x0e00
 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_ALIGN                  0
 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_BITS                   3
 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_SHIFT                  9
 
 /* Combo_IEEE0 :: AutoNegLPAbil :: pause [08:07] */
 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_MASK                       0x0180
 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_ALIGN                      0
 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_BITS                       2
 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_SHIFT                      7
 
 /* Combo_IEEE0 :: AutoNegLPAbil :: half_duplex [06:06] */
 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_MASK                 0x0040
 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN                0
 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_BITS                 1
 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT                6
 
 /* Combo_IEEE0 :: AutoNegLPAbil :: full_duplex [05:05] */
 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_MASK                 0x0020
 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN                0
 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_BITS                 1
 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT                5
 
 /* Combo_IEEE0 :: AutoNegLPAbil :: reserved1 [04:01] */
 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_MASK                   0x001e
 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_ALIGN                  0
 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_BITS                   4
 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_SHIFT                  1
 
 /* Combo_IEEE0 :: AutoNegLPAbil :: sgmii_mode [00:00] */
 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_MASK                  0x0001
 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_ALIGN                 0
 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_BITS                  1
 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_SHIFT                 0
 
 
 /****************************************************************************
  * Combo_IEEE0 :: AutoNegExp
  */
 /* Combo_IEEE0 :: AutoNegExp :: reserved0 [15:03] */
 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_MASK                      0xfff8
 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_ALIGN                     0
 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_BITS                      13
 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_SHIFT                     3
 
 /* Combo_IEEE0 :: AutoNegExp :: next_page_ability [02:02] */
 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK              0x0004
 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN             0
 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS              1
 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT             2
 
 /* Combo_IEEE0 :: AutoNegExp :: page_received [01:01] */
 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_MASK                  0x0002
 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_ALIGN                 0
 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_BITS                  1
 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_SHIFT                 1
 
 /* Combo_IEEE0 :: AutoNegExp :: reserved1 [00:00] */
 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_MASK                      0x0001
 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_ALIGN                     0
 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_BITS                      1
 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_SHIFT                     0
 
 
 /****************************************************************************
  * Combo_IEEE0 :: AutoNegNP
  */
 /* Combo_IEEE0 :: AutoNegNP :: Next_Page [15:15] */
 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_MASK                       0x8000
 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_ALIGN                      0
 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_BITS                       1
 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_SHIFT                      15
 
 /* Combo_IEEE0 :: AutoNegNP :: Ack [14:14] */
 #define COMBO_IEEE0_AUTONEGNP_ACK_MASK                             0x4000
 #define COMBO_IEEE0_AUTONEGNP_ACK_ALIGN                            0
 #define COMBO_IEEE0_AUTONEGNP_ACK_BITS                             1
 #define COMBO_IEEE0_AUTONEGNP_ACK_SHIFT                            14
 
 /* Combo_IEEE0 :: AutoNegNP :: Message_Page [13:13] */
 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_MASK                    0x2000
 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_ALIGN                   0
 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_BITS                    1
 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_SHIFT                   13
 
 /* Combo_IEEE0 :: AutoNegNP :: Ack2 [12:12] */
 #define COMBO_IEEE0_AUTONEGNP_ACK2_MASK                            0x1000
 #define COMBO_IEEE0_AUTONEGNP_ACK2_ALIGN                           0
 #define COMBO_IEEE0_AUTONEGNP_ACK2_BITS                            1
 #define COMBO_IEEE0_AUTONEGNP_ACK2_SHIFT                           12
 
 /* Combo_IEEE0 :: AutoNegNP :: Toggle [11:11] */
 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_MASK                          0x0800
 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_ALIGN                         0
 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_BITS                          1
 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_SHIFT                         11
 
 /* Combo_IEEE0 :: AutoNegNP :: Message [10:00] */
 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_MASK                         0x07ff
 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_ALIGN                        0
 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_BITS                         11
 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_SHIFT                        0
 
 
 /****************************************************************************
  * Combo_IEEE0 :: AutoNegLPAbil2
  */
 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Next_Page [15:15] */
 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_MASK                  0x8000
 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN                 0
 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_BITS                  1
 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT                 15
 
 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack [14:14] */
 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_MASK                        0x4000
 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_ALIGN                       0
 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_BITS                        1
 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_SHIFT                       14
 
 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Message_Page [13:13] */
 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK               0x2000
 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN              0
 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS               1
 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT              13
 
 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack2 [12:12] */
 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_MASK                       0x1000
 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_ALIGN                      0
 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_BITS                       1
 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_SHIFT                      12
 
 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Toggle [11:11] */
 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_MASK                     0x0800
 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_ALIGN                    0
 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_BITS                     1
 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_SHIFT                    11
 
 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Message [10:00] */
 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_MASK                    0x07ff
 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_ALIGN                   0
 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_BITS                    11
 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_SHIFT                   0
 
 
 /****************************************************************************
  * Combo_IEEE0 :: MIIextStat
  */
 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15
 
 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14
 
 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13
 
 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12
 
 /* Combo_IEEE0 :: MIIextStat :: reserved0 [11:00] */
 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_MASK                      0x0fff
 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_ALIGN                     0
 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_BITS                      12
 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_SHIFT                     0
 
 
 /****************************************************************************
  * Warpcore_IEEE_PMD_PMD_ieee0Blk
  */
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_ieeeControl1
  */
 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: rst_sw [15:15] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_MASK                  0x8000
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_ALIGN                 0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_BITS                  1
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_SHIFT                 15
 
 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved0 [14:14] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_MASK               0x4000
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_ALIGN              0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_BITS               1
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_SHIFT              14
 
 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection0 [13:13] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_MASK         0x2000
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_ALIGN        0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_BITS         1
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_SHIFT        13
 
 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved1 [12:12] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_MASK               0x1000
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_ALIGN              0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_BITS               1
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_SHIFT              12
 
 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: pwrdwn_sw_10g [11:11] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_MASK           0x0800
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_ALIGN          0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_BITS           1
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_SHIFT          11
 
 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved2 [10:07] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_MASK               0x0780
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_ALIGN              0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_BITS               4
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_SHIFT              7
 
 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection1 [06:06] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_MASK         0x0040
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_ALIGN        0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_BITS         1
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_SHIFT        6
 
 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection2 [05:02] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_MASK         0x003c
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_ALIGN        0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_BITS         4
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_SHIFT        2
 
 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved3 [01:01] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_MASK               0x0002
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_ALIGN              0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_BITS               1
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_SHIFT              1
 
 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: gloop10g [00:00] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_MASK                0x0001
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_ALIGN               0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_BITS                1
 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_SHIFT               0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_ieeeStatus1
  */
 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved0 [15:08] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_MASK                0xff00
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_ALIGN               0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_BITS                8
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_SHIFT               8
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: Fault [07:07] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_MASK                    0x0080
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_ALIGN                   0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_BITS                    1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_SHIFT                   7
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved1 [06:03] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_MASK                0x0078
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_ALIGN               0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_BITS                4
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_SHIFT               3
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: Rx_linkStatus [02:02] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_MASK            0x0004
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_ALIGN           0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_BITS            1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_SHIFT           2
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: lowPoerwAbility [01:01] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_MASK          0x0002
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_ALIGN         0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_BITS          1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_SHIFT         1
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved2 [00:00] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_MASK                0x0001
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_ALIGN               0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_BITS                1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_SHIFT               0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_ieeeId1
  */
 /* PMD_ieee0Blk :: PMD_ieeeId1 :: IEEEID1 [15:00] */
 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_MASK                      0xffff
 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_ALIGN                     0
 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_BITS                      16
 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_SHIFT                     0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_ieeeId2
  */
 /* PMD_ieee0Blk :: PMD_ieeeId2 :: IEEEID2 [15:00] */
 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_MASK                      0xffff
 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_ALIGN                     0
 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_BITS                      16
 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_SHIFT                     0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_ieeeSpeedAbility
  */
 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: reserved0 [15:07] */
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_MASK           0xff80
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_ALIGN          0
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_BITS           9
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_SHIFT          7
 
 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10M [06:06] */
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_MASK            0x0040
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_ALIGN           0
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_BITS            1
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_SHIFT           6
 
 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed100M [05:05] */
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_MASK           0x0020
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_ALIGN          0
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_BITS           1
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_SHIFT          5
 
 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed1000B [04:04] */
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_MASK          0x0010
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_ALIGN         0
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_BITS          1
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_SHIFT         4
 
 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: reserved1 [03:03] */
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_MASK           0x0008
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_ALIGN          0
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_BITS           1
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_SHIFT          3
 
 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10PASS_TS [02:02] */
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_MASK      0x0004
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_ALIGN     0
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_BITS      1
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_SHIFT     2
 
 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed2BASE_TL [01:01] */
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_MASK       0x0002
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_ALIGN      0
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_BITS       1
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_SHIFT      1
 
 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10G [00:00] */
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_MASK            0x0001
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_ALIGN           0
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_BITS            1
 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_SHIFT           0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_ieeeDevInPkg1
  */
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: Vendor2 [15:15] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR2_MASK                0x8000
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR2_ALIGN               0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR2_BITS                1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR2_SHIFT               15
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: Vendor1 [14:14] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR1_MASK                0x4000
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR1_ALIGN               0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR1_BITS                1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_VENDOR1_SHIFT               14
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: CL22ext [13:13] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CL22EXT_MASK                0x2000
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CL22EXT_ALIGN               0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CL22EXT_BITS                1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CL22EXT_SHIFT               13
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: reserved0 [12:00] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_MASK              0x1fff
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_ALIGN             0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_BITS              13
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_SHIFT             0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_ieeeDevInPkg2
  */
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: reserved0 [15:08] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_MASK              0xff00
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_ALIGN             0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_BITS              8
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_SHIFT             8
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: AN [07:07] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_AN_MASK                     0x0080
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_AN_ALIGN                    0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_AN_BITS                     1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_AN_SHIFT                    7
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: TC [06:06] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_TC_MASK                     0x0040
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_TC_ALIGN                    0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_TC_BITS                     1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_TC_SHIFT                    6
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: DTE_XS [05:05] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_DTE_XS_MASK                 0x0020
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_DTE_XS_ALIGN                0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_DTE_XS_BITS                 1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_DTE_XS_SHIFT                5
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: PHY_XS [04:04] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PHY_XS_MASK                 0x0010
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PHY_XS_ALIGN                0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PHY_XS_BITS                 1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PHY_XS_SHIFT                4
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: PCS_XS [03:03] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PCS_XS_MASK                 0x0008
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PCS_XS_ALIGN                0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PCS_XS_BITS                 1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PCS_XS_SHIFT                3
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: WIS [02:02] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_WIS_MASK                    0x0004
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_WIS_ALIGN                   0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_WIS_BITS                    1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_WIS_SHIFT                   2
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: PMA_PMD [01:01] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PMA_PMD_MASK                0x0002
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PMA_PMD_ALIGN               0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PMA_PMD_BITS                1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_PMA_PMD_SHIFT               1
 
 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: Clause22 [00:00] */
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CLAUSE22_MASK               0x0001
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CLAUSE22_ALIGN              0
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CLAUSE22_BITS               1
 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CLAUSE22_SHIFT              0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_ieeeControl2
  */
 /* PMD_ieee0Blk :: PMD_ieeeControl2 :: reserved0 [15:03] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_MASK               0xfff8
 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_ALIGN              0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_BITS               13
 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_SHIFT              3
 
 /* PMD_ieee0Blk :: PMD_ieeeControl2 :: PMA_PMD_typeSel [02:00] */
 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_MASK         0x0007
 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_ALIGN        0
 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_BITS         3
 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_SHIFT        0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_ieeeStatus2
  */
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: devPresent [15:14] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_MASK               0xc000
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_ALIGN              0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_BITS               2
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_SHIFT              14
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: txFaultAbility [13:13] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_MASK           0x2000
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_ALIGN          0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_BITS           1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_SHIFT          13
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: rxFaultAbility [12:12] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_MASK           0x1000
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_ALIGN          0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_BITS           1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_SHIFT          12
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: txFault [11:11] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_MASK                  0x0800
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_ALIGN                 0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_BITS                  1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_SHIFT                 11
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: rxFault [10:10] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_MASK                  0x0400
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_ALIGN                 0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_BITS                  1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_SHIFT                 10
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: extAbilities [09:09] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_MASK             0x0200
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_ALIGN            0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_BITS             1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_SHIFT            9
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_txDisableAble [08:08] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_MASK        0x0100
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_ALIGN       0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_BITS        1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_SHIFT       8
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_SR_able [07:07] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_MASK      0x0080
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_ALIGN     0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_BITS      1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_SHIFT     7
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LR_able [06:06] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_MASK      0x0040
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_ALIGN     0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_BITS      1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_SHIFT     6
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_ER_able [05:05] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_MASK      0x0020
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_ALIGN     0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_BITS      1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_SHIFT     5
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LX4_able [04:04] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_MASK     0x0010
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_ALIGN    0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_BITS     1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_SHIFT    4
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_SW_able [03:03] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_MASK      0x0008
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_ALIGN     0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_BITS      1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_SHIFT     3
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LW_able [02:02] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_MASK      0x0004
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_ALIGN     0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_BITS      1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_SHIFT     2
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_EW_able [01:01] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_MASK      0x0002
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_ALIGN     0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_BITS      1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_SHIFT     1
 
 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMA_loopback_able [00:00] */
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_MASK        0x0001
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_ALIGN       0
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_BITS        1
 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_SHIFT       0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_txDisable
  */
 /* PMD_ieee0Blk :: PMD_txDisable :: reserved0 [15:05] */
 #define PMD_IEEE0BLK_PMD_TXDISABLE_RESERVED0_MASK                  0xffe0
 #define PMD_IEEE0BLK_PMD_TXDISABLE_RESERVED0_ALIGN                 0
 #define PMD_IEEE0BLK_PMD_TXDISABLE_RESERVED0_BITS                  11
 #define PMD_IEEE0BLK_PMD_TXDISABLE_RESERVED0_SHIFT                 5
 
 /* PMD_ieee0Blk :: PMD_txDisable :: tx_disable_ln3 [04:04] */
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN3_MASK             0x0010
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN3_ALIGN            0
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN3_BITS             1
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN3_SHIFT            4
 
 /* PMD_ieee0Blk :: PMD_txDisable :: tx_disable_ln2 [03:03] */
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN2_MASK             0x0008
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN2_ALIGN            0
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN2_BITS             1
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN2_SHIFT            3
 
 /* PMD_ieee0Blk :: PMD_txDisable :: tx_disable_ln1 [02:02] */
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN1_MASK             0x0004
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN1_ALIGN            0
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN1_BITS             1
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN1_SHIFT            2
 
 /* PMD_ieee0Blk :: PMD_txDisable :: tx_disable_ln0 [01:01] */
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN0_MASK             0x0002
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN0_ALIGN            0
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN0_BITS             1
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_LN0_SHIFT            1
 
 /* PMD_ieee0Blk :: PMD_txDisable :: tx_disable_global [00:00] */
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_GLOBAL_MASK          0x0001
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_GLOBAL_ALIGN         0
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_GLOBAL_BITS          1
 #define PMD_IEEE0BLK_PMD_TXDISABLE_TX_DISABLE_GLOBAL_SHIFT         0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_rxSigDet
  */
 /* PMD_ieee0Blk :: PMD_rxSigDet :: reserved0 [15:05] */
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RESERVED0_MASK                   0xffe0
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RESERVED0_ALIGN                  0
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RESERVED0_BITS                   11
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RESERVED0_SHIFT                  5
 
 /* PMD_ieee0Blk :: PMD_rxSigDet :: rxSigdet_ln3 [04:04] */
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN3_MASK                0x0010
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN3_ALIGN               0
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN3_BITS                1
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN3_SHIFT               4
 
 /* PMD_ieee0Blk :: PMD_rxSigDet :: rxSigdet_ln2 [03:03] */
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN2_MASK                0x0008
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN2_ALIGN               0
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN2_BITS                1
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN2_SHIFT               3
 
 /* PMD_ieee0Blk :: PMD_rxSigDet :: rxSigdet_ln1 [02:02] */
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN1_MASK                0x0004
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN1_ALIGN               0
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN1_BITS                1
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN1_SHIFT               2
 
 /* PMD_ieee0Blk :: PMD_rxSigDet :: rxSigdet_ln0 [01:01] */
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN0_MASK                0x0002
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN0_ALIGN               0
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN0_BITS                1
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_LN0_SHIFT               1
 
 /* PMD_ieee0Blk :: PMD_rxSigDet :: rxSigdet_global [00:00] */
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_GLOBAL_MASK             0x0001
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_GLOBAL_ALIGN            0
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_GLOBAL_BITS             1
 #define PMD_IEEE0BLK_PMD_RXSIGDET_RXSIGDET_GLOBAL_SHIFT            0
 
 
 /****************************************************************************
  * PMD_ieee0Blk :: PMD_extendedAbility
  */
 /* PMD_ieee0Blk :: PMD_extendedAbility :: reserved0 [15:09] */
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_MASK            0xfe00
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_ALIGN           0
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_BITS            7
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_SHIFT           9
 
 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10BASE_T_Ability [08:08] */
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_MASK 0x0100
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_ALIGN 0
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_BITS 1
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_SHIFT 8
 
 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_100BASE_TX_Ability [07:07] */
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_MASK 0x0080
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_ALIGN 0
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_BITS 1
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_SHIFT 7
 
 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_1000BASE_KX_Ability [06:06] */
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_MASK 0x0040
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_ALIGN 0
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_BITS 1
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_SHIFT 6
 
 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_1000BASE_T_Ability [05:05] */
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_MASK 0x0020
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_ALIGN 0
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_BITS 1
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_SHIFT 5
 
 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_KR_Ability [04:04] */
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_MASK 0x0010
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_ALIGN 0
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_BITS 1
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_SHIFT 4
 
 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_KX4_Ability [03:03] */
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_MASK 0x0008
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_ALIGN 0
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_BITS 1
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_SHIFT 3
 
 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_T_Ability [02:02] */
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_MASK 0x0004
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_ALIGN 0
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_BITS 1
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_SHIFT 2
 
 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_LRM_Ability [01:01] */
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_MASK 0x0002
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_ALIGN 0
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_BITS 1
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_SHIFT 1
 
 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_CX4_Ability [00:00] */
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_MASK 0x0001
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_ALIGN 0
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_BITS 1
 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_SHIFT 0
 
 
 /****************************************************************************
  * Warpcore_IEEE_PMD_PMD_ieee9Blk
  */
 /****************************************************************************
  * PMD_ieee9Blk :: tengbase_kr_pmd_control_register_150
  */
 /* PMD_ieee9Blk :: tengbase_kr_pmd_control_register_150 :: reserved0 [15:02] */
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_MASK 0xfffc
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_BITS 14
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_SHIFT 2
 
 /* PMD_ieee9Blk :: tengbase_kr_pmd_control_register_150 :: training_enable [01:01] */
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_MASK 0x0002
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_BITS 1
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_SHIFT 1
 
 /* PMD_ieee9Blk :: tengbase_kr_pmd_control_register_150 :: restart_training [00:00] */
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_MASK 0x0001
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_BITS 1
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_SHIFT 0
 
 
 /****************************************************************************
  * PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151
  */
 /* PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 :: reserved0 [15:04] */
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_MASK 0xfff0
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_BITS 12
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_SHIFT 4
 
 /* PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 :: training_failure [03:03] */
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_MASK 0x0008
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_BITS 1
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_SHIFT 3
 
 /* PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 :: training_status [02:02] */
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_MASK 0x0004
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_BITS 1
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_SHIFT 2
 
 /* PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 :: frame_lock [01:01] */
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_MASK 0x0002
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_BITS 1
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_SHIFT 1
 
 /* PMD_ieee9Blk :: tengbase_kr_pmd_status_register_151 :: receiver_status [00:00] */
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_MASK 0x0001
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_BITS 1
 #define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_SHIFT 0
 
 
 /****************************************************************************
  * PMD_ieee9Blk :: tengbase_kr_lp_coefficient_upd_152
  */
 /* PMD_ieee9Blk :: tengbase_kr_lp_coefficient_upd_152 :: lp_coeff_upd_reg [15:00] */
 #define PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_MASK 0xffff
 #define PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_BITS 16
 #define PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_SHIFT 0
 
 
 /****************************************************************************
  * PMD_ieee9Blk :: tengbase_kr_lp_status_report_reg_153
  */
 /* PMD_ieee9Blk :: tengbase_kr_lp_status_report_reg_153 :: lp_coeff_status_reg [15:00] */
 #define PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_MASK 0xffff
 #define PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_BITS 16
 #define PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_SHIFT 0
 
 
 /****************************************************************************
  * PMD_ieee9Blk :: tengbase_kr_ld_coefficient_upd_154
  */
 /* PMD_ieee9Blk :: tengbase_kr_ld_coefficient_upd_154 :: ld_coeff_upd_reg [15:00] */
 #define PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_MASK 0xffff
 #define PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_BITS 16
 #define PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_SHIFT 0
 
 
 /****************************************************************************
  * PMD_ieee9Blk :: tengbase_kr_ld_status_report_reg_155
  */
 /* PMD_ieee9Blk :: tengbase_kr_ld_status_report_reg_155 :: ld_coeff_status_reg [15:00] */
 #define PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_MASK 0xffff
 #define PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_ALIGN 0
 #define PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_BITS 16
 #define PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_SHIFT 0
 
 
 /****************************************************************************
  * Warpcore_IEEE_PMD_PMD_ieee10Blk
  */
 /****************************************************************************
  * PMD_ieee10Blk :: PMD_KX_control
  */
 /* PMD_ieee10Blk :: PMD_KX_control :: reserved0 [15:01] */
 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_MASK                0xfffe
 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_ALIGN               0
 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_BITS                15
 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_SHIFT               1
 
 /* PMD_ieee10Blk :: PMD_KX_control :: tx_disable [00:00] */
 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_MASK               0x0001
 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_ALIGN              0
 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_BITS               1
 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_SHIFT              0
 
 
 /****************************************************************************
  * PMD_ieee10Blk :: PMD_KX_status
  */
 /* PMD_ieee10Blk :: PMD_KX_status :: reserved0 [15:14] */
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_MASK                 0xc000
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_ALIGN                0
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_BITS                 2
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_SHIFT                14
 
 /* PMD_ieee10Blk :: PMD_KX_status :: KX_txFaultAbility [13:13] */
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_MASK         0x2000
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_ALIGN        0
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_BITS         1
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_SHIFT        13
 
 /* PMD_ieee10Blk :: PMD_KX_status :: KX_rxFaultAbility [12:12] */
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_MASK         0x1000
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_ALIGN        0
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_BITS         1
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_SHIFT        12
 
 /* PMD_ieee10Blk :: PMD_KX_status :: KX_txFault [11:11] */
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_MASK                0x0800
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_ALIGN               0
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_BITS                1
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_SHIFT               11
 
 /* PMD_ieee10Blk :: PMD_KX_status :: KX_rsFault [10:10] */
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_MASK                0x0400
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_ALIGN               0
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_BITS                1
 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_SHIFT               10
 
 /* PMD_ieee10Blk :: PMD_KX_status :: reserved1 [09:09] */
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_MASK                 0x0200
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_ALIGN                0
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_BITS                 1
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_SHIFT                9
 
 /* PMD_ieee10Blk :: PMD_KX_status :: txDisableAbility [08:08] */
 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_MASK          0x0100
 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_ALIGN         0
 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_BITS          1
 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_SHIFT         8
 
 /* PMD_ieee10Blk :: PMD_KX_status :: reserved2 [07:01] */
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_MASK                 0x00fe
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_ALIGN                0
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_BITS                 7
 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_SHIFT                1
 
 /* PMD_ieee10Blk :: PMD_KX_status :: PMD_sigdet [00:00] */
 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_MASK                0x0001
 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_ALIGN               0
 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_BITS                1
 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_SHIFT               0
 
 
 /****************************************************************************
  * PMD_ieee10Blk :: PMD_fecAbility
  */
 /* PMD_ieee10Blk :: PMD_fecAbility :: reserved0 [15:02] */
 #define PMD_IEEE10BLK_PMD_FECABILITY_RESERVED0_MASK                0xfffc
 #define PMD_IEEE10BLK_PMD_FECABILITY_RESERVED0_ALIGN               0
 #define PMD_IEEE10BLK_PMD_FECABILITY_RESERVED0_BITS                14
 #define PMD_IEEE10BLK_PMD_FECABILITY_RESERVED0_SHIFT               2
 
 /* PMD_ieee10Blk :: PMD_fecAbility :: errorCnt_able [01:01] */
 #define PMD_IEEE10BLK_PMD_FECABILITY_ERRORCNT_ABLE_MASK            0x0002
 #define PMD_IEEE10BLK_PMD_FECABILITY_ERRORCNT_ABLE_ALIGN           0
 #define PMD_IEEE10BLK_PMD_FECABILITY_ERRORCNT_ABLE_BITS            1
 #define PMD_IEEE10BLK_PMD_FECABILITY_ERRORCNT_ABLE_SHIFT           1
 
 /* PMD_ieee10Blk :: PMD_fecAbility :: fec_able [00:00] */
 #define PMD_IEEE10BLK_PMD_FECABILITY_FEC_ABLE_MASK                 0x0001
 #define PMD_IEEE10BLK_PMD_FECABILITY_FEC_ABLE_ALIGN                0
 #define PMD_IEEE10BLK_PMD_FECABILITY_FEC_ABLE_BITS                 1
 #define PMD_IEEE10BLK_PMD_FECABILITY_FEC_ABLE_SHIFT                0
 
 
 /****************************************************************************
  * PMD_ieee10Blk :: PMD_fecControl
  */
 /* PMD_ieee10Blk :: PMD_fecControl :: reserved0 [15:02] */
 #define PMD_IEEE10BLK_PMD_FECCONTROL_RESERVED0_MASK                0xfffc
 #define PMD_IEEE10BLK_PMD_FECCONTROL_RESERVED0_ALIGN               0
 #define PMD_IEEE10BLK_PMD_FECCONTROL_RESERVED0_BITS                14
 #define PMD_IEEE10BLK_PMD_FECCONTROL_RESERVED0_SHIFT               2
 
 /* PMD_ieee10Blk :: PMD_fecControl :: errorCnt_en [01:01] */
 #define PMD_IEEE10BLK_PMD_FECCONTROL_ERRORCNT_EN_MASK              0x0002
 #define PMD_IEEE10BLK_PMD_FECCONTROL_ERRORCNT_EN_ALIGN             0
 #define PMD_IEEE10BLK_PMD_FECCONTROL_ERRORCNT_EN_BITS              1
 #define PMD_IEEE10BLK_PMD_FECCONTROL_ERRORCNT_EN_SHIFT             1
 
 /* PMD_ieee10Blk :: PMD_fecControl :: fec_en [00:00] */
 #define PMD_IEEE10BLK_PMD_FECCONTROL_FEC_EN_MASK                   0x0001
 #define PMD_IEEE10BLK_PMD_FECCONTROL_FEC_EN_ALIGN                  0
 #define PMD_IEEE10BLK_PMD_FECCONTROL_FEC_EN_BITS                   1
 #define PMD_IEEE10BLK_PMD_FECCONTROL_FEC_EN_SHIFT                  0
 
 
 /****************************************************************************
  * PMD_ieee10Blk :: PMD_CorrectedBlksL
  */
 /* PMD_ieee10Blk :: PMD_CorrectedBlksL :: corCountL [15:00] */
 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSL_CORCOUNTL_MASK            0xffff
 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSL_CORCOUNTL_ALIGN           0
 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSL_CORCOUNTL_BITS            16
 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSL_CORCOUNTL_SHIFT           0
 
 
 /****************************************************************************
  * PMD_ieee10Blk :: PMD_CorrectedBlksH
  */
 /* PMD_ieee10Blk :: PMD_CorrectedBlksH :: corCountH [15:00] */
 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSH_CORCOUNTH_MASK            0xffff
 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSH_CORCOUNTH_ALIGN           0
 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSH_CORCOUNTH_BITS            16
 #define PMD_IEEE10BLK_PMD_CORRECTEDBLKSH_CORCOUNTH_SHIFT           0
 
 
 /****************************************************************************
  * PMD_ieee10Blk :: PMD_UncorrectedBlksL
  */
 /* PMD_ieee10Blk :: PMD_UncorrectedBlksL :: uncorCountL [15:00] */
 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_MASK        0xffff
 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_ALIGN       0
 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_BITS        16
 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_SHIFT       0
 
 
 /****************************************************************************
  * PMD_ieee10Blk :: PMD_UncorrectedBlksH
  */
 /* PMD_ieee10Blk :: PMD_UncorrectedBlksH :: uncorCountH [15:00] */
 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_MASK        0xffff
 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_ALIGN       0
 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_BITS        16
 #define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_SHIFT       0
 
 
 /****************************************************************************
  * Warpcore_IEEE_PCS_PCS_ieee0Blk
  */
 /****************************************************************************
  * PCS_ieee0Blk :: PCS_ieeeControl1
  */
 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: rst_sw [15:15] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RST_SW_MASK                  0x8000
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RST_SW_ALIGN                 0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RST_SW_BITS                  1
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RST_SW_SHIFT                 15
 
 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: gloop10g [14:14] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_GLOOP10G_MASK                0x4000
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_GLOOP10G_ALIGN               0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_GLOOP10G_BITS                1
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_GLOOP10G_SHIFT               14
 
 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: SpeedSelection0 [13:13] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION0_MASK         0x2000
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION0_ALIGN        0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION0_BITS         1
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION0_SHIFT        13
 
 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: reserved0 [12:12] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED0_MASK               0x1000
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED0_ALIGN              0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED0_BITS               1
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED0_SHIFT              12
 
 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: pwrdwn_sw_10g [11:11] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_PWRDWN_SW_10G_MASK           0x0800
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_PWRDWN_SW_10G_ALIGN          0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_PWRDWN_SW_10G_BITS           1
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_PWRDWN_SW_10G_SHIFT          11
 
 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: clockStoppable [10:10] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_CLOCKSTOPPABLE_MASK          0x0400
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_CLOCKSTOPPABLE_ALIGN         0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_CLOCKSTOPPABLE_BITS          1
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_CLOCKSTOPPABLE_SHIFT         10
 
 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: reserved1 [09:07] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED1_MASK               0x0380
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED1_ALIGN              0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED1_BITS               3
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED1_SHIFT              7
 
 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: SpeedSelection1 [06:06] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION1_MASK         0x0040
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION1_ALIGN        0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION1_BITS         1
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION1_SHIFT        6
 
 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: SpeedSelection2 [05:02] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION2_MASK         0x003c
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION2_ALIGN        0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION2_BITS         4
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_SPEEDSELECTION2_SHIFT        2
 
 /* PCS_ieee0Blk :: PCS_ieeeControl1 :: reserved2 [01:00] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED2_MASK               0x0003
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED2_ALIGN              0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED2_BITS               2
 #define PCS_IEEE0BLK_PCS_IEEECONTROL1_RESERVED2_SHIFT              0
 
 
 /****************************************************************************
  * PCS_ieee0Blk :: PCS_ieeeStatus1
  */
 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: reserved0 [15:12] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED0_MASK                0xf000
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED0_ALIGN               0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED0_BITS                4
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED0_SHIFT               12
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Tx_LPI_received [11:11] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_RECEIVED_MASK          0x0800
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_RECEIVED_ALIGN         0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_RECEIVED_BITS          1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_RECEIVED_SHIFT         11
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Rx_LPI_received [10:10] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_RECEIVED_MASK          0x0400
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_RECEIVED_ALIGN         0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_RECEIVED_BITS          1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_RECEIVED_SHIFT         10
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Tx_LPI_indication [09:09] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_INDICATION_MASK        0x0200
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_INDICATION_ALIGN       0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_INDICATION_BITS        1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_TX_LPI_INDICATION_SHIFT       9
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Rx_LPI_indication [08:08] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_INDICATION_MASK        0x0100
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_INDICATION_ALIGN       0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_INDICATION_BITS        1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LPI_INDICATION_SHIFT       8
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Fault [07:07] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_FAULT_MASK                    0x0080
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_FAULT_ALIGN                   0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_FAULT_BITS                    1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_FAULT_SHIFT                   7
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: reserved1 [06:03] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED1_MASK                0x0078
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED1_ALIGN               0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED1_BITS                4
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED1_SHIFT               3
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: Rx_linkStatus [02:02] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LINKSTATUS_MASK            0x0004
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LINKSTATUS_ALIGN           0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LINKSTATUS_BITS            1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RX_LINKSTATUS_SHIFT           2
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: lowPowerAbility [01:01] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_LOWPOWERABILITY_MASK          0x0002
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_LOWPOWERABILITY_ALIGN         0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_LOWPOWERABILITY_BITS          1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_LOWPOWERABILITY_SHIFT         1
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus1 :: reserved2 [00:00] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED2_MASK                0x0001
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED2_ALIGN               0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED2_BITS                1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS1_RESERVED2_SHIFT               0
 
 
 /****************************************************************************
  * PCS_ieee0Blk :: PCS_ieeeControl2
  */
 /* PCS_ieee0Blk :: PCS_ieeeControl2 :: reserved0 [15:03] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_RESERVED0_MASK               0xfff8
 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_RESERVED0_ALIGN              0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_RESERVED0_BITS               13
 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_RESERVED0_SHIFT              3
 
 /* PCS_ieee0Blk :: PCS_ieeeControl2 :: PCS_typeSel [02:00] */
 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_PCS_TYPESEL_MASK             0x0007
 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_PCS_TYPESEL_ALIGN            0
 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_PCS_TYPESEL_BITS             3
 #define PCS_IEEE0BLK_PCS_IEEECONTROL2_PCS_TYPESEL_SHIFT            0
 
 
 /****************************************************************************
  * PCS_ieee0Blk :: PCS_ieeeStatus2
  */
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: devPresent [15:14] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_DEVPRESENT_MASK               0xc000
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_DEVPRESENT_ALIGN              0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_DEVPRESENT_BITS               2
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_DEVPRESENT_SHIFT              14
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: reserved0 [13:12] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED0_MASK                0x3000
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED0_ALIGN               0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED0_BITS                2
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED0_SHIFT               12
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_txFault [11:11] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_TXFAULT_MASK              0x0800
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_TXFAULT_ALIGN             0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_TXFAULT_BITS              1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_TXFAULT_SHIFT             11
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_rxFault [10:10] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_RXFAULT_MASK              0x0400
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_RXFAULT_ALIGN             0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_RXFAULT_BITS              1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_RXFAULT_SHIFT             10
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: reserved1 [09:06] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED1_MASK                0x03c0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED1_ALIGN               0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED1_BITS                4
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_RESERVED1_SHIFT               6
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_100GBASE_R_able [05:05] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_100GBASE_R_ABLE_MASK      0x0020
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_100GBASE_R_ABLE_ALIGN     0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_100GBASE_R_ABLE_BITS      1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_100GBASE_R_ABLE_SHIFT     5
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_40GBASE_R_able [04:04] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_40GBASE_R_ABLE_MASK       0x0010
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_40GBASE_R_ABLE_ALIGN      0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_40GBASE_R_ABLE_BITS       1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_40GBASE_R_ABLE_SHIFT      4
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_10GBASE_T_able [03:03] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_T_ABLE_MASK       0x0008
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_T_ABLE_ALIGN      0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_T_ABLE_BITS       1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_T_ABLE_SHIFT      3
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_10GBASE_W_able [02:02] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_W_ABLE_MASK       0x0004
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_W_ABLE_ALIGN      0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_W_ABLE_BITS       1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_W_ABLE_SHIFT      2
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_10GBASE_X_able [01:01] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_X_ABLE_MASK       0x0002
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_X_ABLE_ALIGN      0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_X_ABLE_BITS       1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_X_ABLE_SHIFT      1
 
 /* PCS_ieee0Blk :: PCS_ieeeStatus2 :: PCS_10GBASE_R_able [00:00] */
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_R_ABLE_MASK       0x0001
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_R_ABLE_ALIGN      0
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_R_ABLE_BITS       1
 #define PCS_IEEE0BLK_PCS_IEEESTATUS2_PCS_10GBASE_R_ABLE_SHIFT      0
 
 
 /****************************************************************************
  * Warpcore_IEEE_PCS_PCS_ieee1Blk
  */
 /****************************************************************************
  * PCS_ieee1Blk :: PCS_laneStatus
  */
 /* PCS_ieee1Blk :: PCS_laneStatus :: reserved0 [15:13] */
 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED0_MASK                 0xe000
 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED0_ALIGN                0
 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED0_BITS                 3
 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED0_SHIFT                13
 
 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_alignStatus [12:12] */
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_ALIGNSTATUS_MASK           0x1000
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_ALIGNSTATUS_ALIGN          0
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_ALIGNSTATUS_BITS           1
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_ALIGNSTATUS_SHIFT          12
 
 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_PatTestAbility [11:11] */
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_PATTESTABILITY_MASK        0x0800
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_PATTESTABILITY_ALIGN       0
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_PATTESTABILITY_BITS        1
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_PATTESTABILITY_SHIFT       11
 
 /* PCS_ieee1Blk :: PCS_laneStatus :: reserved1 [10:04] */
 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED1_MASK                 0x07f0
 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED1_ALIGN                0
 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED1_BITS                 7
 #define PCS_IEEE1BLK_PCS_LANESTATUS_RESERVED1_SHIFT                4
 
 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_lane3Sync [03:03] */
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE3SYNC_MASK             0x0008
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE3SYNC_ALIGN            0
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE3SYNC_BITS             1
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE3SYNC_SHIFT            3
 
 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_lane2Sync [02:02] */
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE2SYNC_MASK             0x0004
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE2SYNC_ALIGN            0
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE2SYNC_BITS             1
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE2SYNC_SHIFT            2
 
 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_lane1Sync [01:01] */
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE1SYNC_MASK             0x0002
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE1SYNC_ALIGN            0
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE1SYNC_BITS             1
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE1SYNC_SHIFT            1
 
 /* PCS_ieee1Blk :: PCS_laneStatus :: PCS_lane0Sync [00:00] */
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE0SYNC_MASK             0x0001
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE0SYNC_ALIGN            0
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE0SYNC_BITS             1
 #define PCS_IEEE1BLK_PCS_LANESTATUS_PCS_LANE0SYNC_SHIFT            0
 
 
 /****************************************************************************
  * PCS_ieee1Blk :: PCS_ieeeTestControl
  */
 /* PCS_ieee1Blk :: PCS_ieeeTestControl :: reserved0 [15:03] */
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_RESERVED0_MASK            0xfff8
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_RESERVED0_ALIGN           0
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_RESERVED0_BITS            13
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_RESERVED0_SHIFT           3
 
 /* PCS_ieee1Blk :: PCS_ieeeTestControl :: PCS_txTestPatEn [02:02] */
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TXTESTPATEN_MASK      0x0004
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TXTESTPATEN_ALIGN     0
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TXTESTPATEN_BITS      1
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TXTESTPATEN_SHIFT     2
 
 /* PCS_ieee1Blk :: PCS_ieeeTestControl :: PCS_testPatSel [01:00] */
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TESTPATSEL_MASK       0x0003
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TESTPATSEL_ALIGN      0
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TESTPATSEL_BITS       2
 #define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_PCS_TESTPATSEL_SHIFT      0
 
 
 /****************************************************************************
  * Warpcore_IEEE_PCS_PCS_ieee2Blk
  */
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_Status1
  */
 /* PCS_ieee2Blk :: PCS_Status1 :: reserved0 [15:13] */
 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED0_MASK                    0xe000
 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED0_ALIGN                   0
 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED0_BITS                    3
 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED0_SHIFT                   13
 
 /* PCS_ieee2Blk :: PCS_Status1 :: PCS_link_status [12:12] */
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_LINK_STATUS_MASK              0x1000
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_LINK_STATUS_ALIGN             0
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_LINK_STATUS_BITS              1
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_LINK_STATUS_SHIFT             12
 
 /* PCS_ieee2Blk :: PCS_Status1 :: reserved1 [11:04] */
 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED1_MASK                    0x0ff0
 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED1_ALIGN                   0
 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED1_BITS                    8
 #define PCS_IEEE2BLK_PCS_STATUS1_RESERVED1_SHIFT                   4
 
 /* PCS_ieee2Blk :: PCS_Status1 :: PRBS9_ability [03:03] */
 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS9_ABILITY_MASK                0x0008
 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS9_ABILITY_ALIGN               0
 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS9_ABILITY_BITS                1
 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS9_ABILITY_SHIFT               3
 
 /* PCS_ieee2Blk :: PCS_Status1 :: PRBS31_ability [02:02] */
 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS31_ABILITY_MASK               0x0004
 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS31_ABILITY_ALIGN              0
 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS31_ABILITY_BITS               1
 #define PCS_IEEE2BLK_PCS_STATUS1_PRBS31_ABILITY_SHIFT              2
 
 /* PCS_ieee2Blk :: PCS_Status1 :: PCS_hi_BER [01:01] */
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_HI_BER_MASK                   0x0002
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_HI_BER_ALIGN                  0
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_HI_BER_BITS                   1
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_HI_BER_SHIFT                  1
 
 /* PCS_ieee2Blk :: PCS_Status1 :: PCS_block_lock [00:00] */
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_BLOCK_LOCK_MASK               0x0001
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_BLOCK_LOCK_ALIGN              0
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_BLOCK_LOCK_BITS               1
 #define PCS_IEEE2BLK_PCS_STATUS1_PCS_BLOCK_LOCK_SHIFT              0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_Status2
  */
 /* PCS_ieee2Blk :: PCS_Status2 :: latch_block_lock [15:15] */
 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_BLOCK_LOCK_MASK             0x8000
 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_BLOCK_LOCK_ALIGN            0
 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_BLOCK_LOCK_BITS             1
 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_BLOCK_LOCK_SHIFT            15
 
 /* PCS_ieee2Blk :: PCS_Status2 :: latch_hi_BER [14:14] */
 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_HI_BER_MASK                 0x4000
 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_HI_BER_ALIGN                0
 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_HI_BER_BITS                 1
 #define PCS_IEEE2BLK_PCS_STATUS2_LATCH_HI_BER_SHIFT                14
 
 /* PCS_ieee2Blk :: PCS_Status2 :: BER [13:08] */
 #define PCS_IEEE2BLK_PCS_STATUS2_BER_MASK                          0x3f00
 #define PCS_IEEE2BLK_PCS_STATUS2_BER_ALIGN                         0
 #define PCS_IEEE2BLK_PCS_STATUS2_BER_BITS                          6
 #define PCS_IEEE2BLK_PCS_STATUS2_BER_SHIFT                         8
 
 /* PCS_ieee2Blk :: PCS_Status2 :: errored_blocks [07:00] */
 #define PCS_IEEE2BLK_PCS_STATUS2_ERRORED_BLOCKS_MASK               0x00ff
 #define PCS_IEEE2BLK_PCS_STATUS2_ERRORED_BLOCKS_ALIGN              0
 #define PCS_IEEE2BLK_PCS_STATUS2_ERRORED_BLOCKS_BITS               8
 #define PCS_IEEE2BLK_PCS_STATUS2_ERRORED_BLOCKS_SHIFT              0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_seedA0
  */
 /* PCS_ieee2Blk :: PCS_seedA0 :: seedA0 [15:00] */
 #define PCS_IEEE2BLK_PCS_SEEDA0_SEEDA0_MASK                        0xffff
 #define PCS_IEEE2BLK_PCS_SEEDA0_SEEDA0_ALIGN                       0
 #define PCS_IEEE2BLK_PCS_SEEDA0_SEEDA0_BITS                        16
 #define PCS_IEEE2BLK_PCS_SEEDA0_SEEDA0_SHIFT                       0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_seedA1
  */
 /* PCS_ieee2Blk :: PCS_seedA1 :: seedA1 [15:00] */
 #define PCS_IEEE2BLK_PCS_SEEDA1_SEEDA1_MASK                        0xffff
 #define PCS_IEEE2BLK_PCS_SEEDA1_SEEDA1_ALIGN                       0
 #define PCS_IEEE2BLK_PCS_SEEDA1_SEEDA1_BITS                        16
 #define PCS_IEEE2BLK_PCS_SEEDA1_SEEDA1_SHIFT                       0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_seedA2
  */
 /* PCS_ieee2Blk :: PCS_seedA2 :: seedA2 [15:00] */
 #define PCS_IEEE2BLK_PCS_SEEDA2_SEEDA2_MASK                        0xffff
 #define PCS_IEEE2BLK_PCS_SEEDA2_SEEDA2_ALIGN                       0
 #define PCS_IEEE2BLK_PCS_SEEDA2_SEEDA2_BITS                        16
 #define PCS_IEEE2BLK_PCS_SEEDA2_SEEDA2_SHIFT                       0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_seedA3
  */
 /* PCS_ieee2Blk :: PCS_seedA3 :: reserved0 [15:10] */
 #define PCS_IEEE2BLK_PCS_SEEDA3_RESERVED0_MASK                     0xfc00
 #define PCS_IEEE2BLK_PCS_SEEDA3_RESERVED0_ALIGN                    0
 #define PCS_IEEE2BLK_PCS_SEEDA3_RESERVED0_BITS                     6
 #define PCS_IEEE2BLK_PCS_SEEDA3_RESERVED0_SHIFT                    10
 
 /* PCS_ieee2Blk :: PCS_seedA3 :: seedA3 [09:00] */
 #define PCS_IEEE2BLK_PCS_SEEDA3_SEEDA3_MASK                        0x03ff
 #define PCS_IEEE2BLK_PCS_SEEDA3_SEEDA3_ALIGN                       0
 #define PCS_IEEE2BLK_PCS_SEEDA3_SEEDA3_BITS                        10
 #define PCS_IEEE2BLK_PCS_SEEDA3_SEEDA3_SHIFT                       0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_seedB0
  */
 /* PCS_ieee2Blk :: PCS_seedB0 :: seedB0 [15:00] */
 #define PCS_IEEE2BLK_PCS_SEEDB0_SEEDB0_MASK                        0xffff
 #define PCS_IEEE2BLK_PCS_SEEDB0_SEEDB0_ALIGN                       0
 #define PCS_IEEE2BLK_PCS_SEEDB0_SEEDB0_BITS                        16
 #define PCS_IEEE2BLK_PCS_SEEDB0_SEEDB0_SHIFT                       0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_seedB1
  */
 /* PCS_ieee2Blk :: PCS_seedB1 :: seedB1 [15:00] */
 #define PCS_IEEE2BLK_PCS_SEEDB1_SEEDB1_MASK                        0xffff
 #define PCS_IEEE2BLK_PCS_SEEDB1_SEEDB1_ALIGN                       0
 #define PCS_IEEE2BLK_PCS_SEEDB1_SEEDB1_BITS                        16
 #define PCS_IEEE2BLK_PCS_SEEDB1_SEEDB1_SHIFT                       0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_seedB2
  */
 /* PCS_ieee2Blk :: PCS_seedB2 :: seedB2 [15:00] */
 #define PCS_IEEE2BLK_PCS_SEEDB2_SEEDB2_MASK                        0xffff
 #define PCS_IEEE2BLK_PCS_SEEDB2_SEEDB2_ALIGN                       0
 #define PCS_IEEE2BLK_PCS_SEEDB2_SEEDB2_BITS                        16
 #define PCS_IEEE2BLK_PCS_SEEDB2_SEEDB2_SHIFT                       0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_seedB3
  */
 /* PCS_ieee2Blk :: PCS_seedB3 :: reserved0 [15:10] */
 #define PCS_IEEE2BLK_PCS_SEEDB3_RESERVED0_MASK                     0xfc00
 #define PCS_IEEE2BLK_PCS_SEEDB3_RESERVED0_ALIGN                    0
 #define PCS_IEEE2BLK_PCS_SEEDB3_RESERVED0_BITS                     6
 #define PCS_IEEE2BLK_PCS_SEEDB3_RESERVED0_SHIFT                    10
 
 /* PCS_ieee2Blk :: PCS_seedB3 :: seedB3 [09:00] */
 #define PCS_IEEE2BLK_PCS_SEEDB3_SEEDB3_MASK                        0x03ff
 #define PCS_IEEE2BLK_PCS_SEEDB3_SEEDB3_ALIGN                       0
 #define PCS_IEEE2BLK_PCS_SEEDB3_SEEDB3_BITS                        10
 #define PCS_IEEE2BLK_PCS_SEEDB3_SEEDB3_SHIFT                       0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_tpControl
  */
 /* PCS_ieee2Blk :: PCS_tpControl :: reserved0 [15:07] */
 #define PCS_IEEE2BLK_PCS_TPCONTROL_RESERVED0_MASK                  0xff80
 #define PCS_IEEE2BLK_PCS_TPCONTROL_RESERVED0_ALIGN                 0
 #define PCS_IEEE2BLK_PCS_TPCONTROL_RESERVED0_BITS                  9
 #define PCS_IEEE2BLK_PCS_TPCONTROL_RESERVED0_SHIFT                 7
 
 /* PCS_ieee2Blk :: PCS_tpControl :: prbs9tx_en [06:06] */
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_MASK                 0x0040
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_ALIGN                0
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_BITS                 1
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_SHIFT                6
 
 /* PCS_ieee2Blk :: PCS_tpControl :: prbs31rx_en [05:05] */
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_MASK                0x0020
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_ALIGN               0
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_BITS                1
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_SHIFT               5
 
 /* PCS_ieee2Blk :: PCS_tpControl :: prbs31tx_en [04:04] */
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_MASK                0x0010
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_ALIGN               0
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_BITS                1
 #define PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_SHIFT               4
 
 /* PCS_ieee2Blk :: PCS_tpControl :: tptx_en [03:03] */
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPTX_EN_MASK                    0x0008
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPTX_EN_ALIGN                   0
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPTX_EN_BITS                    1
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPTX_EN_SHIFT                   3
 
 /* PCS_ieee2Blk :: PCS_tpControl :: tprx_en [02:02] */
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPRX_EN_MASK                    0x0004
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPRX_EN_ALIGN                   0
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPRX_EN_BITS                    1
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TPRX_EN_SHIFT                   2
 
 /* PCS_ieee2Blk :: PCS_tpControl :: tp_sel [01:01] */
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TP_SEL_MASK                     0x0002
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TP_SEL_ALIGN                    0
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TP_SEL_BITS                     1
 #define PCS_IEEE2BLK_PCS_TPCONTROL_TP_SEL_SHIFT                    1
 
 /* PCS_ieee2Blk :: PCS_tpControl :: dp_sel [00:00] */
 #define PCS_IEEE2BLK_PCS_TPCONTROL_DP_SEL_MASK                     0x0001
 #define PCS_IEEE2BLK_PCS_TPCONTROL_DP_SEL_ALIGN                    0
 #define PCS_IEEE2BLK_PCS_TPCONTROL_DP_SEL_BITS                     1
 #define PCS_IEEE2BLK_PCS_TPCONTROL_DP_SEL_SHIFT                    0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: PCS_tpErrCounter
  */
 /* PCS_ieee2Blk :: PCS_tpErrCounter :: tpErrCounter [15:00] */
 #define PCS_IEEE2BLK_PCS_TPERRCOUNTER_TPERRCOUNTER_MASK            0xffff
 #define PCS_IEEE2BLK_PCS_TPERRCOUNTER_TPERRCOUNTER_ALIGN           0
 #define PCS_IEEE2BLK_PCS_TPERRCOUNTER_TPERRCOUNTER_BITS            16
 #define PCS_IEEE2BLK_PCS_TPERRCOUNTER_TPERRCOUNTER_SHIFT           0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: BER_ho
  */
 /* PCS_ieee2Blk :: BER_ho :: BER_ho_present [15:15] */
 #define PCS_IEEE2BLK_BER_HO_BER_HO_PRESENT_MASK                    0x8000
 #define PCS_IEEE2BLK_BER_HO_BER_HO_PRESENT_ALIGN                   0
 #define PCS_IEEE2BLK_BER_HO_BER_HO_PRESENT_BITS                    1
 #define PCS_IEEE2BLK_BER_HO_BER_HO_PRESENT_SHIFT                   15
 
 /* PCS_ieee2Blk :: BER_ho :: reserved0 [14:14] */
 #define PCS_IEEE2BLK_BER_HO_RESERVED0_MASK                         0x4000
 #define PCS_IEEE2BLK_BER_HO_RESERVED0_ALIGN                        0
 #define PCS_IEEE2BLK_BER_HO_RESERVED0_BITS                         1
 #define PCS_IEEE2BLK_BER_HO_RESERVED0_SHIFT                        14
 
 /* PCS_ieee2Blk :: BER_ho :: BER_ho [13:00] */
 #define PCS_IEEE2BLK_BER_HO_BER_HO_MASK                            0x3fff
 #define PCS_IEEE2BLK_BER_HO_BER_HO_ALIGN                           0
 #define PCS_IEEE2BLK_BER_HO_BER_HO_BITS                            14
 #define PCS_IEEE2BLK_BER_HO_BER_HO_SHIFT                           0
 
 
 /****************************************************************************
  * PCS_ieee2Blk :: errored_blocks_ho
  */
 /* PCS_ieee2Blk :: errored_blocks_ho :: errored_blocks_ho_present [15:15] */
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_MASK 0x8000
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_ALIGN 0
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_BITS 1
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_SHIFT 15
 
 /* PCS_ieee2Blk :: errored_blocks_ho :: reserved0 [14:14] */
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_RESERVED0_MASK              0x4000
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_RESERVED0_ALIGN             0
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_RESERVED0_BITS              1
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_RESERVED0_SHIFT             14
 
 /* PCS_ieee2Blk :: errored_blocks_ho :: errored_blocks_ho [13:00] */
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_MASK      0x3fff
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_ALIGN     0
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_BITS      14
 #define PCS_IEEE2BLK_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_SHIFT     0
 
 
 /****************************************************************************
  * Warpcore_IEEE_PCS_PCS_ieee3Blk
  */
 /****************************************************************************
  * PCS_ieee3Blk :: multi_lane_status_1
  */
 /* PCS_ieee3Blk :: multi_lane_status_1 :: reserved0 [15:13] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED0_MASK            0xe000
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED0_ALIGN           0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED0_BITS            3
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED0_SHIFT           13
 
 /* PCS_ieee3Blk :: multi_lane_status_1 :: align_status [12:12] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_ALIGN_STATUS_MASK         0x1000
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_ALIGN_STATUS_ALIGN        0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_ALIGN_STATUS_BITS         1
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_ALIGN_STATUS_SHIFT        12
 
 /* PCS_ieee3Blk :: multi_lane_status_1 :: reserved1 [11:04] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED1_MASK            0x0ff0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED1_ALIGN           0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED1_BITS            8
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_RESERVED1_SHIFT           4
 
 /* PCS_ieee3Blk :: multi_lane_status_1 :: lane_3_lock [03:03] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_3_LOCK_MASK          0x0008
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_3_LOCK_ALIGN         0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_3_LOCK_BITS          1
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_3_LOCK_SHIFT         3
 
 /* PCS_ieee3Blk :: multi_lane_status_1 :: lane_2_lock [02:02] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_2_LOCK_MASK          0x0004
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_2_LOCK_ALIGN         0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_2_LOCK_BITS          1
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_2_LOCK_SHIFT         2
 
 /* PCS_ieee3Blk :: multi_lane_status_1 :: lane_1_lock [01:01] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_1_LOCK_MASK          0x0002
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_1_LOCK_ALIGN         0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_1_LOCK_BITS          1
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_1_LOCK_SHIFT         1
 
 /* PCS_ieee3Blk :: multi_lane_status_1 :: lane_0_lock [00:00] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_0_LOCK_MASK          0x0001
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_0_LOCK_ALIGN         0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_0_LOCK_BITS          1
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_1_LANE_0_LOCK_SHIFT         0
 
 
 /****************************************************************************
  * PCS_ieee3Blk :: multi_lane_status_3
  */
 /* PCS_ieee3Blk :: multi_lane_status_3 :: reserved0 [15:04] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_RESERVED0_MASK            0xfff0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_RESERVED0_ALIGN           0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_RESERVED0_BITS            12
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_RESERVED0_SHIFT           4
 
 /* PCS_ieee3Blk :: multi_lane_status_3 :: am_3_lock [03:03] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_3_LOCK_MASK            0x0008
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_3_LOCK_ALIGN           0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_3_LOCK_BITS            1
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_3_LOCK_SHIFT           3
 
 /* PCS_ieee3Blk :: multi_lane_status_3 :: am_2_lock [02:02] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_2_LOCK_MASK            0x0004
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_2_LOCK_ALIGN           0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_2_LOCK_BITS            1
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_2_LOCK_SHIFT           2
 
 /* PCS_ieee3Blk :: multi_lane_status_3 :: am_1_lock [01:01] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_1_LOCK_MASK            0x0002
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_1_LOCK_ALIGN           0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_1_LOCK_BITS            1
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_1_LOCK_SHIFT           1
 
 /* PCS_ieee3Blk :: multi_lane_status_3 :: am_0_lock [00:00] */
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_0_LOCK_MASK            0x0001
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_0_LOCK_ALIGN           0
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_0_LOCK_BITS            1
 #define PCS_IEEE3BLK_MULTI_LANE_STATUS_3_AM_0_LOCK_SHIFT           0
 
 
 /****************************************************************************
  * Warpcore_IEEE_PCS_PCS_ieee5Blk
  */
 /****************************************************************************
  * PCS_ieee5Blk :: BIP_error_counter_ln01
  */
 /* PCS_ieee5Blk :: BIP_error_counter_ln01 :: BIP_err_count_ln1 [15:08] */
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN1_MASK 0xff00
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN1_ALIGN 0
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN1_BITS 8
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN1_SHIFT 8
 
 /* PCS_ieee5Blk :: BIP_error_counter_ln01 :: BIP_err_count_ln0 [07:00] */
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN0_MASK 0x00ff
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN0_ALIGN 0
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN0_BITS 8
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN01_BIP_ERR_COUNT_LN0_SHIFT 0
 
 
 /****************************************************************************
  * PCS_ieee5Blk :: BIP_error_counter_ln23
  */
 /* PCS_ieee5Blk :: BIP_error_counter_ln23 :: BIP_err_count_ln3 [15:08] */
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN3_MASK 0xff00
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN3_ALIGN 0
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN3_BITS 8
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN3_SHIFT 8
 
 /* PCS_ieee5Blk :: BIP_error_counter_ln23 :: BIP_err_count_ln2 [07:00] */
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN2_MASK 0x00ff
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN2_ALIGN 0
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN2_BITS 8
 #define PCS_IEEE5BLK_BIP_ERROR_COUNTER_LN23_BIP_ERR_COUNT_LN2_SHIFT 0
 
 
 /****************************************************************************
  * Warpcore_IEEE_CL73_AN_ieee0Blk
  */
 /****************************************************************************
  * AN_ieee0Blk :: AN_ieeeControl1
  */
 /* AN_ieee0Blk :: AN_ieeeControl1 :: rst_sw [15:15] */
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_MASK                    0x8000
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_ALIGN                   0
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_BITS                    1
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_SHIFT                   15
 
 /* AN_ieee0Blk :: AN_ieeeControl1 :: gloop10g [14:14] */
 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_MASK                  0x4000
 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_ALIGN                 0
 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_BITS                  1
 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_SHIFT                 14
 
 /* AN_ieee0Blk :: AN_ieeeControl1 :: ExtendNPen [13:13] */
 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_MASK                0x2000
 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_ALIGN               0
 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_BITS                1
 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_SHIFT               13
 
 /* AN_ieee0Blk :: AN_ieeeControl1 :: AN_enable [12:12] */
 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_MASK                 0x1000
 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_ALIGN                0
 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_BITS                 1
 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_SHIFT                12
 
 /* AN_ieee0Blk :: AN_ieeeControl1 :: reserved0 [11:10] */
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_MASK                 0x0c00
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_ALIGN                0
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_BITS                 2
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_SHIFT                10
 
 /* AN_ieee0Blk :: AN_ieeeControl1 :: restartAN [09:09] */
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_MASK                 0x0200
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_ALIGN                0
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_BITS                 1
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_SHIFT                9
 
 /* AN_ieee0Blk :: AN_ieeeControl1 :: reserved1 [08:00] */
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_MASK                 0x01ff
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_ALIGN                0
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_BITS                 9
 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_SHIFT                0
 
 
 /****************************************************************************
  * AN_ieee0Blk :: AN_ieeeStatus1
  */
 /* AN_ieee0Blk :: AN_ieeeStatus1 :: reserved0 [15:08] */
 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_MASK                  0xff00
 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_ALIGN                 0
 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_BITS                  8
 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_SHIFT                 8
 
 /* AN_ieee0Blk :: AN_ieeeStatus1 :: ExtendedNP_able [07:07] */
 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_MASK            0x0080
 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_ALIGN           0
 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_BITS            1
 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_SHIFT           7
 
 /* AN_ieee0Blk :: AN_ieeeStatus1 :: pageReceived [06:06] */
 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_MASK               0x0040
 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_ALIGN              0
 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_BITS               1
 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_SHIFT              6
 
 /* AN_ieee0Blk :: AN_ieeeStatus1 :: ANcomplete [05:05] */
 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_MASK                 0x0020
 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_ALIGN                0
 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_BITS                 1
 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_SHIFT                5
 
 /* AN_ieee0Blk :: AN_ieeeStatus1 :: remoteFault [04:04] */
 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_MASK                0x0010
 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_ALIGN               0
 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_BITS                1
 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_SHIFT               4
 
 /* AN_ieee0Blk :: AN_ieeeStatus1 :: ANability [03:03] */
 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_MASK                  0x0008
 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_ALIGN                 0
 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_BITS                  1
 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_SHIFT                 3
 
 /* AN_ieee0Blk :: AN_ieeeStatus1 :: linkStatus [02:02] */
 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_MASK                 0x0004
 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_ALIGN                0
 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_BITS                 1
 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_SHIFT                2
 
 /* AN_ieee0Blk :: AN_ieeeStatus1 :: reserved1 [01:01] */
 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_MASK                  0x0002
 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_ALIGN                 0
 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_BITS                  1
 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_SHIFT                 1
 
 /* AN_ieee0Blk :: AN_ieeeStatus1 :: LP_ANability [00:00] */
 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_MASK               0x0001
 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_ALIGN              0
 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_BITS               1
 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_SHIFT              0
 
 
 /****************************************************************************
  * AN_ieee0Blk :: AN_ieeeId1
  */
 /* AN_ieee0Blk :: AN_ieeeId1 :: IEEEID1 [15:00] */
 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_MASK                        0xffff
 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_ALIGN                       0
 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_BITS                        16
 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_SHIFT                       0
 
 
 /****************************************************************************
  * AN_ieee0Blk :: AN_ieeeId2
  */
 /* AN_ieee0Blk :: AN_ieeeId2 :: IEEEID2 [15:00] */
 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_MASK                        0xffff
 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_ALIGN                       0
 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_BITS                        16
 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_SHIFT                       0
 
 
 /****************************************************************************
  * AN_ieee0Blk :: AN_ieeeDevInPkg2
  */
 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: Vendor2 [15:15] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_MASK                  0x8000
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_ALIGN                 0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_BITS                  1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_SHIFT                 15
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: Vendor1 [14:14] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_MASK                  0x4000
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_ALIGN                 0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_BITS                  1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_SHIFT                 14
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: CL22ext [13:13] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_MASK                  0x2000
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_ALIGN                 0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_BITS                  1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_SHIFT                 13
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: reserved0 [12:00] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_MASK                0x1fff
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_ALIGN               0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_BITS                13
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_SHIFT               0
 
 
 /****************************************************************************
  * AN_ieee0Blk :: AN_ieeeDevInPkg1
  */
 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: reserved0 [15:08] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_MASK                0xff00
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_ALIGN               0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_BITS                8
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_SHIFT               8
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: AN [07:07] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_MASK                       0x0080
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_ALIGN                      0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_BITS                       1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_SHIFT                      7
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: TC [06:06] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_MASK                       0x0040
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_ALIGN                      0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_BITS                       1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_SHIFT                      6
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: DTE_XS [05:05] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_MASK                   0x0020
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_ALIGN                  0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_BITS                   1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_SHIFT                  5
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: PHY_XS [04:04] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_MASK                   0x0010
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_ALIGN                  0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_BITS                   1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_SHIFT                  4
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: PCS_XS [03:03] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_MASK                   0x0008
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_ALIGN                  0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_BITS                   1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_SHIFT                  3
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: WIS [02:02] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_MASK                      0x0004
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_ALIGN                     0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_BITS                      1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_SHIFT                     2
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: PMA_PMD [01:01] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_MASK                  0x0002
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_ALIGN                 0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_BITS                  1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_SHIFT                 1
 
 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: Clause22 [00:00] */
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_MASK                 0x0001
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_ALIGN                0
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_BITS                 1
 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_SHIFT                0
 
 
 /****************************************************************************
  * Warpcore_IEEE_CL73_AN_ieee1Blk
  */
 /****************************************************************************
  * AN_ieee1Blk :: AN_advertisement0
  */
 /* AN_ieee1Blk :: AN_advertisement0 :: NP [15:15] */
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_MASK                      0x8000
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_ALIGN                     0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_BITS                      1
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_SHIFT                     15
 
 /* AN_ieee1Blk :: AN_advertisement0 :: Ack [14:14] */
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_MASK                     0x4000
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_ALIGN                    0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_BITS                     1
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_SHIFT                    14
 
 /* AN_ieee1Blk :: AN_advertisement0 :: RF [13:13] */
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_MASK                      0x2000
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_ALIGN                     0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_BITS                      1
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_SHIFT                     13
 
 /* AN_ieee1Blk :: AN_advertisement0 :: pause [12:10] */
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_PAUSE_MASK                   0x1c00
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_PAUSE_ALIGN                  0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_PAUSE_BITS                   3
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_PAUSE_SHIFT                  10
 
 /* AN_ieee1Blk :: AN_advertisement0 :: echoed_nonce [09:05] */
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ECHOED_NONCE_MASK            0x03e0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ECHOED_NONCE_ALIGN           0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ECHOED_NONCE_BITS            5
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ECHOED_NONCE_SHIFT           5
 
 /* AN_ieee1Blk :: AN_advertisement0 :: selector [04:00] */
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_MASK                0x001f
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_ALIGN               0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_BITS                5
 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_SHIFT               0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_advertisement1
  */
 /* AN_ieee1Blk :: AN_advertisement1 :: techAbility [15:05] */
 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECHABILITY_MASK             0xffe0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECHABILITY_ALIGN            0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECHABILITY_BITS             11
 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TECHABILITY_SHIFT            5
 
 /* AN_ieee1Blk :: AN_advertisement1 :: transmitted_nonce [04:00] */
 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TRANSMITTED_NONCE_MASK       0x001f
 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TRANSMITTED_NONCE_ALIGN      0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TRANSMITTED_NONCE_BITS       5
 #define AN_IEEE1BLK_AN_ADVERTISEMENT1_TRANSMITTED_NONCE_SHIFT      0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_advertisement2
  */
 /* AN_ieee1Blk :: AN_advertisement2 :: fec_requested [15:14] */
 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_FEC_REQUESTED_MASK           0xc000
 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_FEC_REQUESTED_ALIGN          0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_FEC_REQUESTED_BITS           2
 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_FEC_REQUESTED_SHIFT          14
 
 /* AN_ieee1Blk :: AN_advertisement2 :: reserved0 [13:00] */
 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_RESERVED0_MASK               0x3fff
 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_RESERVED0_ALIGN              0
 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_RESERVED0_BITS               14
 #define AN_IEEE1BLK_AN_ADVERTISEMENT2_RESERVED0_SHIFT              0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_LP_basePageAbility0
  */
 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: NP [15:15] */
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_MASK                 0x8000
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_ALIGN                0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_BITS                 1
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_SHIFT                15
 
 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: Ack [14:14] */
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_MASK                0x4000
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_ALIGN               0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_BITS                1
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_SHIFT               14
 
 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: RF [13:13] */
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_MASK                 0x2000
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_ALIGN                0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_BITS                 1
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_SHIFT                13
 
 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: pause [12:10] */
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_PAUSE_MASK              0x1c00
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_PAUSE_ALIGN             0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_PAUSE_BITS              3
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_PAUSE_SHIFT             10
 
 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: echoed_nonce [09:05] */
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ECHOED_NONCE_MASK       0x03e0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ECHOED_NONCE_ALIGN      0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ECHOED_NONCE_BITS       5
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ECHOED_NONCE_SHIFT      5
 
 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: selector [04:00] */
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_MASK           0x001f
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_ALIGN          0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_BITS           5
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_SHIFT          0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_LP_basePageAbility1
  */
 /* AN_ieee1Blk :: AN_LP_basePageAbility1 :: techAbility [15:05] */
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TECHABILITY_MASK        0xffe0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TECHABILITY_ALIGN       0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TECHABILITY_BITS        11
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TECHABILITY_SHIFT       5
 
 /* AN_ieee1Blk :: AN_LP_basePageAbility1 :: transmitted_nonce [04:00] */
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TRANSMITTED_NONCE_MASK  0x001f
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TRANSMITTED_NONCE_ALIGN 0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TRANSMITTED_NONCE_BITS  5
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_TRANSMITTED_NONCE_SHIFT 0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_LP_basePageAbility2
  */
 /* AN_ieee1Blk :: AN_LP_basePageAbility2 :: fec_requested [15:14] */
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_FEC_REQUESTED_MASK      0xc000
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_FEC_REQUESTED_ALIGN     0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_FEC_REQUESTED_BITS      2
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_FEC_REQUESTED_SHIFT     14
 
 /* AN_ieee1Blk :: AN_LP_basePageAbility2 :: reserved0 [13:00] */
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_RESERVED0_MASK          0x3fff
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_RESERVED0_ALIGN         0
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_RESERVED0_BITS          14
 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_RESERVED0_SHIFT         0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_XNP_transmit0
  */
 /* AN_ieee1Blk :: AN_XNP_transmit0 :: NP [15:15] */
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_MASK                       0x8000
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_ALIGN                      0
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_BITS                       1
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_SHIFT                      15
 
 /* AN_ieee1Blk :: AN_XNP_transmit0 :: reserved0 [14:14] */
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_MASK                0x4000
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_ALIGN               0
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_BITS                1
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_SHIFT               14
 
 /* AN_ieee1Blk :: AN_XNP_transmit0 :: MP [13:13] */
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_MASK                       0x2000
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_ALIGN                      0
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_BITS                       1
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_SHIFT                      13
 
 /* AN_ieee1Blk :: AN_XNP_transmit0 :: Ack2 [12:12] */
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_MASK                     0x1000
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_ALIGN                    0
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_BITS                     1
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_SHIFT                    12
 
 /* AN_ieee1Blk :: AN_XNP_transmit0 :: Toggle [11:11] */
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_MASK                   0x0800
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_ALIGN                  0
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_BITS                   1
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_SHIFT                  11
 
 /* AN_ieee1Blk :: AN_XNP_transmit0 :: MSG [10:00] */
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_MASK                      0x07ff
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_ALIGN                     0
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_BITS                      11
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_SHIFT                     0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_XNP_transmit1
  */
 /* AN_ieee1Blk :: AN_XNP_transmit1 :: UCF1 [15:00] */
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_MASK                     0xffff
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_ALIGN                    0
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_BITS                     16
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_SHIFT                    0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_XNP_transmit2
  */
 /* AN_ieee1Blk :: AN_XNP_transmit2 :: UCF2 [15:00] */
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_MASK                     0xffff
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_ALIGN                    0
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_BITS                     16
 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_SHIFT                    0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_LP_XNP_ability0
  */
 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: NP [15:15] */
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_MASK                     0x8000
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_ALIGN                    0
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_BITS                     1
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_SHIFT                    15
 
 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: reserved0 [14:14] */
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_MASK              0x4000
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_ALIGN             0
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_BITS              1
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_SHIFT             14
 
 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: MP [13:13] */
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_MASK                     0x2000
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_ALIGN                    0
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_BITS                     1
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_SHIFT                    13
 
 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: Ack2 [12:12] */
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_MASK                   0x1000
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_ALIGN                  0
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_BITS                   1
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_SHIFT                  12
 
 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: Toggle [11:11] */
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_MASK                 0x0800
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_ALIGN                0
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_BITS                 1
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_SHIFT                11
 
 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: MSG [10:00] */
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_MASK                    0x07ff
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_ALIGN                   0
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_BITS                    11
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_SHIFT                   0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_LP_XNP_ability1
  */
 /* AN_ieee1Blk :: AN_LP_XNP_ability1 :: UCF1 [15:00] */
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_MASK                   0xffff
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_ALIGN                  0
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_BITS                   16
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_SHIFT                  0
 
 
 /****************************************************************************
  * AN_ieee1Blk :: AN_LP_XNP_ability2
  */
 /* AN_ieee1Blk :: AN_LP_XNP_ability2 :: UCF2 [15:00] */
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_MASK                   0xffff
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_ALIGN                  0
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_BITS                   16
 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_SHIFT                  0
 
 
 /****************************************************************************
  * Warpcore_IEEE_CL73_AN_ieee3Blk
  */
 /****************************************************************************
  * AN_ieee3Blk :: AN_BPstatus
  */
 /* AN_ieee3Blk :: AN_BPstatus :: reserved0 [15:09] */
 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_MASK                     0xfe00
 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_ALIGN                    0
 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_BITS                     7
 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_SHIFT                    9
 
 /* AN_ieee3Blk :: AN_BPstatus :: CR10 [08:08] */
 #define AN_IEEE3BLK_AN_BPSTATUS_CR10_MASK                          0x0100
 #define AN_IEEE3BLK_AN_BPSTATUS_CR10_ALIGN                         0
 #define AN_IEEE3BLK_AN_BPSTATUS_CR10_BITS                          1
 #define AN_IEEE3BLK_AN_BPSTATUS_CR10_SHIFT                         8
 
 /* AN_ieee3Blk :: AN_BPstatus :: reserved1 [07:07] */
 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_MASK                     0x0080
 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_ALIGN                    0
 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_BITS                     1
 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_SHIFT                    7
 
 /* AN_ieee3Blk :: AN_BPstatus :: CR4 [06:06] */
 #define AN_IEEE3BLK_AN_BPSTATUS_CR4_MASK                           0x0040
 #define AN_IEEE3BLK_AN_BPSTATUS_CR4_ALIGN                          0
 #define AN_IEEE3BLK_AN_BPSTATUS_CR4_BITS                           1
 #define AN_IEEE3BLK_AN_BPSTATUS_CR4_SHIFT                          6
 
 /* AN_ieee3Blk :: AN_BPstatus :: KR4 [05:05] */
 #define AN_IEEE3BLK_AN_BPSTATUS_KR4_MASK                           0x0020
 #define AN_IEEE3BLK_AN_BPSTATUS_KR4_ALIGN                          0
 #define AN_IEEE3BLK_AN_BPSTATUS_KR4_BITS                           1
 #define AN_IEEE3BLK_AN_BPSTATUS_KR4_SHIFT                          5
 
 /* AN_ieee3Blk :: AN_BPstatus :: R_with_FEC [04:04] */
 #define AN_IEEE3BLK_AN_BPSTATUS_R_WITH_FEC_MASK                    0x0010
 #define AN_IEEE3BLK_AN_BPSTATUS_R_WITH_FEC_ALIGN                   0
 #define AN_IEEE3BLK_AN_BPSTATUS_R_WITH_FEC_BITS                    1
 #define AN_IEEE3BLK_AN_BPSTATUS_R_WITH_FEC_SHIFT                   4
 
 /* AN_ieee3Blk :: AN_BPstatus :: KR [03:03] */
 #define AN_IEEE3BLK_AN_BPSTATUS_KR_MASK                            0x0008
 #define AN_IEEE3BLK_AN_BPSTATUS_KR_ALIGN                           0
 #define AN_IEEE3BLK_AN_BPSTATUS_KR_BITS                            1
 #define AN_IEEE3BLK_AN_BPSTATUS_KR_SHIFT                           3
 
 /* AN_ieee3Blk :: AN_BPstatus :: KX4 [02:02] */
 #define AN_IEEE3BLK_AN_BPSTATUS_KX4_MASK                           0x0004
 #define AN_IEEE3BLK_AN_BPSTATUS_KX4_ALIGN                          0
 #define AN_IEEE3BLK_AN_BPSTATUS_KX4_BITS                           1
 #define AN_IEEE3BLK_AN_BPSTATUS_KX4_SHIFT                          2
 
 /* AN_ieee3Blk :: AN_BPstatus :: KX [01:01] */
 #define AN_IEEE3BLK_AN_BPSTATUS_KX_MASK                            0x0002
 #define AN_IEEE3BLK_AN_BPSTATUS_KX_ALIGN                           0
 #define AN_IEEE3BLK_AN_BPSTATUS_KX_BITS                            1
 #define AN_IEEE3BLK_AN_BPSTATUS_KX_SHIFT                           1
 
 /* AN_ieee3Blk :: AN_BPstatus :: BP_AN_ability [00:00] */
 #define AN_IEEE3BLK_AN_BPSTATUS_BP_AN_ABILITY_MASK                 0x0001
 #define AN_IEEE3BLK_AN_BPSTATUS_BP_AN_ABILITY_ALIGN                0
 #define AN_IEEE3BLK_AN_BPSTATUS_BP_AN_ABILITY_BITS                 1
 #define AN_IEEE3BLK_AN_BPSTATUS_BP_AN_ABILITY_SHIFT                0
 
 
 /****************************************************************************
  * AN_ieee3Blk :: EEE_adv
  */
 /* AN_ieee3Blk :: EEE_adv :: reserved0 [15:07] */
 #define AN_IEEE3BLK_EEE_ADV_RESERVED0_MASK                         0xff80
 #define AN_IEEE3BLK_EEE_ADV_RESERVED0_ALIGN                        0
 #define AN_IEEE3BLK_EEE_ADV_RESERVED0_BITS                         9
 #define AN_IEEE3BLK_EEE_ADV_RESERVED0_SHIFT                        7
 
 /* AN_ieee3Blk :: EEE_adv :: EEE_10G_KR [06:06] */
 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KR_MASK                        0x0040
 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KR_ALIGN                       0
 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KR_BITS                        1
 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KR_SHIFT                       6
 
 /* AN_ieee3Blk :: EEE_adv :: EEE_10G_KX4 [05:05] */
 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KX4_MASK                       0x0020
 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KX4_ALIGN                      0
 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KX4_BITS                       1
 #define AN_IEEE3BLK_EEE_ADV_EEE_10G_KX4_SHIFT                      5
 
 /* AN_ieee3Blk :: EEE_adv :: EEE_1G_KX [04:04] */
 #define AN_IEEE3BLK_EEE_ADV_EEE_1G_KX_MASK                         0x0010
 #define AN_IEEE3BLK_EEE_ADV_EEE_1G_KX_ALIGN                        0
 #define AN_IEEE3BLK_EEE_ADV_EEE_1G_KX_BITS                         1
 #define AN_IEEE3BLK_EEE_ADV_EEE_1G_KX_SHIFT                        4
 
 /* AN_ieee3Blk :: EEE_adv :: reserved1 [03:00] */
 #define AN_IEEE3BLK_EEE_ADV_RESERVED1_MASK                         0x000f
 #define AN_IEEE3BLK_EEE_ADV_RESERVED1_ALIGN                        0
 #define AN_IEEE3BLK_EEE_ADV_RESERVED1_BITS                         4
 #define AN_IEEE3BLK_EEE_ADV_RESERVED1_SHIFT                        0
 
 
 /****************************************************************************
  * AN_ieee3Blk :: EEE_lp_adv
  */
 /* AN_ieee3Blk :: EEE_lp_adv :: reserved0 [15:07] */
 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED0_MASK                      0xff80
 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED0_ALIGN                     0
 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED0_BITS                      9
 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED0_SHIFT                     7
 
 /* AN_ieee3Blk :: EEE_lp_adv :: EEE_10G_KR [06:06] */
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KR_MASK                     0x0040
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KR_ALIGN                    0
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KR_BITS                     1
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KR_SHIFT                    6
 
 /* AN_ieee3Blk :: EEE_lp_adv :: EEE_10G_KX4 [05:05] */
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KX4_MASK                    0x0020
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KX4_ALIGN                   0
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KX4_BITS                    1
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_10G_KX4_SHIFT                   5
 
 /* AN_ieee3Blk :: EEE_lp_adv :: EEE_1G_KX [04:04] */
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_1G_KX_MASK                      0x0010
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_1G_KX_ALIGN                     0
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_1G_KX_BITS                      1
 #define AN_IEEE3BLK_EEE_LP_ADV_EEE_1G_KX_SHIFT                     4
 
 /* AN_ieee3Blk :: EEE_lp_adv :: reserved1 [03:00] */
 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED1_MASK                      0x000f
 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED1_ALIGN                     0
 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED1_BITS                      4
 #define AN_IEEE3BLK_EEE_LP_ADV_RESERVED1_SHIFT                     0
 
 
 /****************************************************************************
  * Datatype Definitions.
  */
 #endif /* #ifndef WC40_H__ */
 
 /* End of File */