tscmod_main.h (50893B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * $Copyright: (c) 2012 Broadcom Corp. 10 * All Rights Reserved.$ 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *---------------------------------------------------------------------- 15 * Description: Main header file for TSCMod. 16 *---------------------------------------------------------------------*/ 17 18 #ifndef _TSCMOD_MAIN_H_ 19 #define _TSCMOD_MAIN_H_ 20 21 #if defined (_DV_TRIDENT2) || defined(STANDALONE) 22 #else 23 #define _SDK_TSCMOD_ 24 #endif 25 26 #ifdef _SDK_TSCMOD_ 27 #include <sal/types.h> 28 #endif 29 30 #ifndef STATIC 31 #define STATIC static 32 #endif /* STATIC */ 33 34 #ifndef __KERNEL__ 35 #include <stdio.h> 36 #include <string.h> 37 #include <stdlib.h> 38 #include "errno.h" 39 #endif 40 #include "tscmod_defines.h" 41 42 #ifndef STANDALONE 43 #if defined (_DV_TRIDENT2) 44 #define printf io_printf 45 #endif 46 #endif 47 48 #ifdef CADENCE 49 #include <veriuser.h> 50 #endif /* CADENCE */ 51 52 53 #ifdef SYNOPSYS 54 #include <vcsuser.h> 55 #endif /* SYNOPSYS */ 56 57 #ifdef _SDK_TSCMOD_ 58 #include <sal/types.h> 59 #include <soc/error.h> 60 #include <soc/cm.h> 61 #include <soc/util.h> 62 #include <soc/cmic.h> 63 #include <soc/phyreg.h> 64 #include <shared/phyreg.h> 65 #endif 66 67 68 #ifdef _SDK_TSCMOD_ 69 #define _SAL_TYPES_H 70 #define printf bsl_printf 71 #endif 72 73 #ifndef _SDK_TSCMOD_ 74 typedef unsigned char uint8; /* 8-bit quantity */ 75 typedef unsigned short uint16; /* 16-bit quantity */ 76 typedef unsigned int uint32; /* 32-bit quantity */ 77 78 79 /* from "sal/core/time.h" */ 80 typedef uint32 sal_usecs_t; 81 82 /* from "soc/types.h" */ 83 typedef int soc_port_t; 84 85 /* dev 2 is almost always the testbench. */ 86 #define SOC_MAX_NUM_DEVICES 2 87 88 89 #define SOC_MAX_NUM_PORTS 72 90 #define NUM_PORTS SOC_MAX_NUM_PORTS 91 #endif /*#ifndef _SDK_TSCMOD_ */ 92 93 94 #ifndef _SDK_TSCMOD_ 95 #define SOC_E_MULT_REG 1 /* this means no errors */ 96 #define SOC_E_FUNC_NOT_FOUND 3 /* function not found. Continue search */ 97 #define SOC_E_NONE 0 98 #define SOC_E_UNAVAIL -1 99 #define SOC_E_FAIL -2 /* generic */ 100 #define SOC_E_TIMEOUT -3 101 #define SOC_E_ERROR -4 102 #define SOC_E_FUNC_ERROR -5 /* function found. But did not execute well. */ 103 #define SOC_E_PARAM -6 104 #else 105 #define SOC_E_MULT_REG 1 /* this means no errors */ 106 #define SOC_E_FUNC_NOT_FOUND 3 /* function not found. Continue search */ 107 #define SOC_E_ERROR SOC_E_INTERNAL 108 #endif 109 110 #define INT_PHY_SW_STATE(unit, port) (int_phy_ctrl[unit][port]) 111 112 #define TSC_REG_READ(_unit, _pc, _flags, _reg_addr, _val) \ 113 tscmod_reg_aer_read((_unit), (_pc), (_reg_addr), (_val)) 114 115 #define TSC_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \ 116 tscmod_reg_aer_write((_unit), (_pc), (_reg_addr), (_val)) 117 118 #define TSC_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \ 119 tscmod_reg_aer_modify((_unit), (_pc), (_reg_addr), (_val),(_mask)) 120 121 #define TSC_UDELAY(_time) sal_udelay(_time) 122 123 #define PRINTF_ERROR(fmt) printf fmt /* from bcmdrv/systemInit.h */ 124 125 #ifndef _SDK_TSCMOD_ 126 #define SOC_IF_ERROR_RETURN(op) \ 127 do { int __rv__; if ((__rv__ = (op)) < 0) \ 128 { PRINTF_ERROR((__FILE__ " : " #op " %d\n", __LINE__)); \ 129 return(__rv__);} } \ 130 while(0) 131 #endif /*_SDK_TSCMOD_ */ 132 133 #define CHK_RET_VAL_FUNC(op) \ 134 { int rv; if ((rv=(op)) != 0) \ 135 printf("ERROR %s:%d. #op# returned %d\n", __FILE__,__LINE__,rv);} 136 137 #define TSC_AER_BCST_OFS_STRAP 0x1ff 138 #define PHYCTRL_MDIO_ADDR_SHARE (1 << 0) /*use phy base addr. to access lanes */ 139 #define PHYCTRL_MDIO_CL45 (1 << 1) /*use MDIO CL45 to access device */ 140 #define PHY_AER_REG_ADDR_AER(_addr) (((_addr) >> 16) & 0x0000FFFF) 141 #define PHY_AER_REG_ADDR_BLK(_addr) (((_addr) & 0x000FFF0)) 142 #define PHY_AER_REG_ADDR_REGAD(_addr) ((((_addr) & 0x00008000) >> 11) | \ 143 ((_addr) & 0x0000000F)) 144 145 #define PHY_AER_REG 0xFFDE 146 #define PHY_AER_REG_ADDR_CL45_DEVID(_addr) (((_addr) >> 27) & 0x0000001F) 147 #define PHY_AER_REG_ADDR_LANE_NUM(_addr) (((_addr) >> 16) & 0x07FF) 148 #define PHY_AER_REG_ADDR_CL45_REGAD(_addr) (((_addr) & 0x000FFFF)) 149 150 #ifndef _SDK_TSCMOD_ 151 #define DEV_CFG_PTR(_pc) (&(((TSC40_DEV_DESC_t *)((_pc)->driver_data))->cfg)) 152 #define SOC_PHY_CLAUSE45_ADDR(_devad,_regad) \ 153 ((((_devad) & 0x003F) << 16) | ((_regad) & 0xFFFF)) 154 #endif 155 156 #ifndef _MDK_TSCMOD_ 157 #ifndef _SDK_TSCMOD_ 158 #define FALSE 0 159 #define TRUE 1 160 #endif /*_SDK_TSCMOD_ */ 161 #else 162 int getLane0Phyad(int phyad); 163 #endif /* _MDK_TSCMOD_ */ 164 165 /* Borrowed from SDK. This struct controls iterations and time durations 166 * while executing a 'wait' or a 'poll'. No doxygen documentation for this. 167 */ 168 #ifndef _SDK_TSCMOD_ 169 typedef struct soc_timeout_s 170 { 171 sal_usecs_t expire; 172 sal_usecs_t usec; 173 int min_polls; 174 int polls; 175 int exp_delay; 176 } soc_timeout_t; 177 #endif /* !_SDK_TSCMOD_ */ 178 179 #define TSC40_XGXSBLK0_XGXSSTATUSr 0x8001 180 #define TSC40_PLL_WAIT 2500 181 #define TSC40_RX_X4_STATUS1_PMA_PMD_LIVE_STATUSr 0xc150 182 #define TSC40_RX_X4_CONTROL0_PMA_CONTROL_0r 0xc137 183 #define TSC40_DSC2B0_DSC_MISC_CTRL0r 0xc21e 184 #define TSC40_DSC1B0_UC_CTRLr 0xc20e 185 #define TSC40_CL72_MISC1_CONTROLr 0xc253 186 187 #define TSC40_VER_NAME_LEN 3 188 189 #define NUMBER_PCS_FUNCTION_TABLE_ENTRIES 100 190 191 #define TSCMOD_UC_MACRO_SHIFT 8 192 #define TSCMOD_UC_INIT 1 193 #define TSCMOD_UC_OFFSET 2 194 #define TSCMOD_UC_SIZE 3 195 #define TSCMOD_UC_W_OP 4 196 #define TSCMOD_UC_W_DATA 5 197 #define TSCMOD_UC_STOP 6 198 #define TSCMOD_UC_LOAD_STATUS 7 199 #define TSCMOD_UC_NO_CKSUM 8 200 #define TSCMOD_UC_RELEASE 9 201 #define TSCMOD_UC_R_CKSUM 10 202 #define TSCMOD_UC_R_VER 11 203 #define TSCMOD_UC_EXT_ON 12 204 #define TSCMOD_UC_EXT_OFF 13 205 #define TSCMOD_UC_R_OP 14 206 #define TSCMOD_UC_R_DATA 15 207 #define TSCMOD_UC_W_RAM_DATA 16 208 #define TSCMOD_UC_W_RAM_OP 17 209 210 211 #define TSCMOD_ENABLE 0x1 212 #define TSCMOD_DISABLE 0x0 213 214 #define TSCMOD_MODEL_TSC 0x11 215 216 #define TSCMOD_DBG_FLOW 0x1 217 #define TSCMOD_DBG_REG 0x2 218 #define TSCMOD_DBG_MDIO 0x4 219 #define TSCMOD_DBG_PRINT 0x8 220 #define TSCMOD_DBG_FUNC 0x10 221 #define TSCMOD_DBG_SUB 0x40 222 #define TSCMOD_DBG_SPD 0x100 223 #define TSCMOD_DBG_AN 0x400 224 #define TSCMOD_DBG_DSC 0x1000 225 #define TSCMOD_DBG_TXDRV 0x2000 226 #define TSCMOD_DBG_LINK 0x4000 227 #define TSCMOD_DBG_PATH 0x8000 228 #define TSCMOD_DBG_TO 0x10000 229 #define TSCMOD_DBG_INIT 0x40000 230 #define TSCMOD_DBG_CFG 0x100000 231 #define TSCMOD_DBG_PAT 0x400000 232 #define TSCMOD_DBG_UC 0x1000000 233 #define TSCMOD_DBG_FSM 0x2000000 234 #define TSCMOD_DBG_SCAN 0x4000000 235 #define TSCMOD_DBG_FLEX 0x8000000 236 #define TSCMOD_DBG_LOCK 0x10000000 237 #define TSCMOD_DBG_FW_LOAD 0x20000000 238 #define TSCMOD_DBG_WB 0x40000000 239 240 #define USE_CJPAT 1 241 #define USE_CRPAT 2 242 243 #define TSCMOD_CTL_AN_CHIP_INIT 1 244 #define TSCMOD_CTL_AN_MODE_INIT 2 245 #define TSCMOD_CTL_AN_MODE_SHARE 3 246 247 #define TSCMOD_MISC_CTL_MASK 0xff 248 #define TSCMOD_MISC_CTL_SHIFT 8 249 #define TSCMOD_MISC_CTL_PORT_MODE_SELECT 1 250 #define TSCMOD_MISC_CTL_CL72_STAT_GET 2 251 #define TSCMOD_MISC_CTL_DISABLE_DSC_SM 3 252 #define TSCMOD_MISC_CTL_ENABLE_DSC_SM 4 253 #define TSCMOD_MISC_CTL_DISABLE_PLL 5 254 #define TSCMOD_MISC_CTL_ENABLE_PLL 6 255 #define TSCMOD_MISC_CTL_ENABLE_PWR_TIMER 7 256 #define TSCMOD_MISC_CTL_MAIN_TAP_ADJUST_EN_0 8 257 #define TSCMOD_MISC_CTL_TUNING_SM_EN 9 258 #define TSCMOD_MISC_CTL_PORT_CLEAN_UP 10 259 #define TSCMOD_MISC_CTL_CLK_SEL_156 11 260 #define TSCMOD_MISC_CTL_PWR_DOWN 12 261 #define TSCMOD_MISC_CTL_NULL 13 262 #define TSCMOD_MISC_CTL_DSC_HW_RESET 14 263 #define TSCMOD_MISC_CTL_DSC_HW_ENABLE 15 264 #define TSCMOD_MISC_CTL_LFCK_BYPASS_0 16 265 #define TSCMOD_MISC_CTL_TEMP_DEFAULT 17 266 #define TSCMOD_MISC_CTL_NONCE_MATCH 18 267 #define TSCMOD_MISC_CTL_AN_RESTART 19 268 #define TSCMOD_MISC_CTL_PDET_COMPL 20 269 #define TSCMOD_MISC_CTL_PDET_KX_COMPL 21 270 271 #define TSCMOD_SRESET_SHIFT 8 272 #define TSCMOD_SRESET_MASK 0xff 273 #define TSCMOD_SRESET_AN_UNLOCK 0 274 #define TSCMOD_SRESET_DSC_HW 1 275 #define TSCMOD_SRESET_DSC_SM 2 276 #define TSCMOD_SRESET_FIRMWARE_MODE 3 277 #define TSCMOD_SRESET_PORT_MODE 4 278 #define TSCMOD_SRESET_ANATX_INPUT 5 279 #define TSCMOD_SRESET_AFE_ANALOG 6 280 #define TSCMOD_SRESET_AFE_TX_ANALOG 7 281 #define TSCMOD_SRESET_AFE_RX_ANALOG 8 282 #define TSCMOD_SRESET_AFE_TX_VOLT 9 283 #define TSCMOD_SRESET_CL72_LINK_FAIL_TIMER 10 284 #define TSCMOD_SRESET_CL72_MAX_WAIT_TIMER 11 285 #define TSCMOD_SRESET_TAP_MUXSEL 12 286 #define TSCMOD_SRESET_UC_NO_RESP 13 287 #define TSCMOD_SRESET_RX_SIG_DET 14 288 #define TSCMOD_SRESET_AER_ALL_PROXY 15 289 #define TSCMOD_SRESET_AER_ALL_PROXY_BLK_ADR 16 290 #define TSCMOD_SRESET_BAM37_ACOL_SWAP 17 291 #define TSCMOD_SRESET_HP_BAM_AM 18 292 #define TSCMOD_SRESET_HP_BAM_SWM_TIMER 19 293 #define TSCMOD_SRESET_AN_MODES 20 294 #define TSCMOD_SRESET_CL72_FW_MODE 21 295 296 #define TSCMOD_DIAG_PRBS_LANE_EN_GET 1 297 #define TSCMOD_DIAG_PRBS_POLYNOMIAL_GET 2 298 #define TSCMOD_DIAG_PRBS_INVERT_DATA_GET 3 299 #define TSCMOD_DIAG_PRBS_MODE_GET 4 300 #define TSCMOD_DIAG_PRBS_RX_INVERT_DATA_GET 5 301 #define TSCMOD_DIAG_PRBS_CHECK_MODE_GET 6 302 #define TSCMOD_DIAG_PRBS_CTRL_GET 7 303 304 305 #define TSCMOD_DIAG_P_HELP 0 306 #define TSCMOD_DIAG_P_VERB 1 307 #define TSCMOD_DIAG_P_LINK_UP_BERT 2 308 #define TSCMOD_DIAG_P_RAM_WRITE 3 309 #define TSCMOD_DIAG_P_CTRL_TYPE 4 310 #define TSCMOD_DIAG_P_AN_CTL 5 311 #define TSCMOD_DIAG_P_SILICON 6 312 #define TSCMOD_DIAG_P_FEC_CTL 7 313 314 #define TSCMOD_DIAG_LINK_LIVE 0x2 315 #define TSCMOD_DIAG_LINK_LATCH 0x1 316 317 /* the cmd value for eyescan API */ 318 #define TSC_UTIL_2D_LIVELINK_EYESCAN 0 319 #define TSC_UTIL_2D_PRBS_EYESCAN 1 320 #define TSC_UTIL_ENABLE_LIVELINK 2 321 #define TSC_UTIL_DISABLE_LIVELINK 3 322 #define TSC_UTIL_ENABLE_DEADLINK 4 323 #define TSC_UTIL_DISABLE_DEADLINK 5 324 #define TSC_UTIL_SET_VOFFSET 6 325 #define TSC_UTIL_SET_HOFFSET 7 326 #define TSC_UTIL_GET_MAX_VOFFSET 8 327 #define TSC_UTIL_GET_MIN_VOFFSET 9 328 #define TSC_UTIL_GET_MAX_LEFT_HOFFSET 10 329 #define TSC_UTIL_GET_MAX_RIGHT_HOFFSET 11 330 #define TSC_UTIL_START_LIVELINK 12 331 #define TSC_UTIL_START_DEADLINK 13 332 #define TSC_UTIL_STOP_LIVELINK 14 333 #define TSC_UTIL_CLEAR_LIVELINK 15 334 #define TSC_UTIL_READ_LIVELINK 16 335 #define TSC_UTIL_READ_DEADLINK 17 336 #define TSC_UTIL_GET_INIT_VOFFSET 18 337 #define TSC_UTIL_VEYE_U 19 338 #define TSC_UTIL_VEYE_D 20 339 #define TSC_UTIL_HEYE_R 21 340 #define TSC_UTIL_HEYE_L 22 341 342 #define TSCMOD_CTRL_TYPE_DEFAULT 0xc0000000 343 #define TSCMOD_CTRL_TYPE_MASK 0x3fffffff 344 #define TSCMOD_CTRL_TYPE_LB 0x1 345 #define TSCMOD_CTRL_TYPE_RMT_LB 0x2 346 #define TSCMOD_CTRL_TYPE_HG 0x4 347 #define TSCMOD_CTRL_TYPE_LINK_BER 0x8 348 #define TSCMOD_CTRL_TYPE_FW_LOADED 0x10 349 #define TSCMOD_CTRL_TYPE_FAULT_DIS 0x20 350 #define TSCMOD_CTRL_TYPE_FW_AVAIL 0x40 351 #define TSCMOD_CTRL_TYPE_PRBS_ON 0x80 352 #define TSCMOD_CTRL_TYPE_CL72_WAR_ON 0x100 353 #define TSCMOD_CTRL_TYPE_UC_STALL 0x200 354 #define TSCMOD_CTRL_TYPE_CL72_TR_DIS 0x400 355 #define TSCMOD_CTRL_TYPE_MSG 0x800 356 #define TSCMOD_CTRL_TYPE_ERR 0x1000 357 #define TSCMOD_CTRL_TYPE_LINK_DIS 0x2000 358 #define TSCMOD_CTRL_TYPE_SEMA_CHK 0x4000 359 #define TSCMOD_CTRL_TYPE_SEMA_ON 0x8000 360 #define TSCMOD_CTRL_TYPE_PCB_STALL0 0x10000 361 #define TSCMOD_CTRL_TYPE_PCB_STALL1 0x20000 362 #define TSCMOD_CTRL_TYPE_UC_CAP_RXP 0x40000 363 #define TSCMOD_CTRL_TYPE_UC_RXP 0x80000 364 #define TSCMOD_CTRL_TYPE_UC_CL72_FW 0x100000 365 #define TSCMOD_CTRL_TYPE_UC_WR_MASK_EN 0x200000 366 #define TSCMOD_CTRL_TYPE_ALL_PROXY 0x400000 367 #define TSCMOD_CTRL_TYPE_ALL_PROXY_BLK_ADR 0x800000 368 #define TSCMOD_CTRL_TYPE_SOME_PROXY 0x1000000 369 #define TSCMOD_CTRL_TYPE_HPAM_AUTODET 0x2000000 370 #define TSCMOD_CTRL_TYPE_WB_DIS 0x4000000 371 #define TSCMOD_CTRL_TYPE_SILICON 0x8000000 372 #define TSCMOD_CTRL_TYPE_TX_SQUELCH 0x10000000 373 #define TSCMOD_CTRL_TYPE_FS_FEC_ON 0x20000000 374 375 #define TSCMOD_MSG_FW_CHIP_VER_UNKNOWN 0x1 376 #define TSCMOD_MSG_PORT_MODE_SEL_RST 0x2 377 #define TSCMOD_MSG_UC_STALL 0x4 378 #define TSCMOD_MSG_UC_SYNC_CMD_PORT_RECOVERY_MASK 0xf0 379 #define TSCMOD_MSG_UC_SYNC_CMD_PORT_RECOVERY_SHIFT 4 380 #define TSCMOD_MSG_UC_SYNC_CMD_CORE_RECOVERY_MASK 0xf00 381 #define TSCMOD_MSG_UC_SYNC_CMD_CORE_RECOVERY_SHIFT 8 382 383 #define TSCMOD_ERR_PLLDIV_DIFF 0x1 384 #define TSCMOD_ERR_AN_PLL_DIFF 0x2 385 #define TSCMOD_ERR_AN_BAD_CFG 0x4 386 #define TSCMOD_ERR_FS_SPD_MODE 0x8 387 #define TSCMOD_ERR_UC_SYNC_CMD_TO 0x10 388 #define TSCMOD_ERR_REG_UC_SYNC_CMD_TO 0x20 389 #define TSCMOD_ERR_PLLDIV_INIT_PLL 0x10000 390 #define TSCMOD_ERR_PLLDIV_SPD_SET 0x20000 391 #define TSCMOD_ERR_UC_FW_ARG 0x40000 392 #define TSCMOD_ERR_UC_CLR_FAIL_CL72 0x80000 393 #define TSCMOD_ERR_UC_CLR_FAIL_RXP 0x100000 394 395 #define TSCMOD_CFG_CTRL_FLAG_WR_MASK_EN 0x1 396 397 #define TSCMOD_TX_LANE_TRAFFIC 0x10 398 #define TSCMOD_TX_LANE_RESET 0x20 399 400 #define TSCMOD_UC_PROXY_WAIT_TIME 425000 401 #define TSCMOD_UC_PROXY_WAIT_TIME_STRIKE1 525000 402 #define TSCMOD_UC_PROXY_WAIT_TIME_STRIKE2 625000 403 404 #define TSCMOD_UC_PROXY_LOOP_CNT 500 405 #define TSCMOD_UC_PROXY_CNT_CAP 3 406 407 #define TSCMOD_UC_SYNC_REQ_MASK 0x1 408 #define TSCMOD_UC_SYNC_RDY_MASK 0x2 409 #define TSCMOD_UC_SYNC_BUSY_MASK 0x4 410 #define TSCMOD_UC_SYNC_RAM_MASK 0x8 411 #define TSCMOD_UC_SYNC_WR_MASK 0x10 412 #define TSCMOD_UC_SYNC_DONE_MASK 0x8000 413 414 #define TSCMOD_UC_SYNC_REQ_SHIFT 0 415 #define TSCMOD_UC_SYNC_RDY_SHIFT 1 416 #define TSCMOD_UC_SYNC_BUSY_SHIFT 2 417 #define TSCMOD_UC_SYNC_RAM_SHIFT 3 418 #define TSCMOD_UC_SYNC_WR_SHIFT 4 419 #define TSCMOD_UC_SYNC_DONE_SHIFT 15 420 421 /* TSCMOD HG2 CONTROL */ 422 #define TSCMOD_HG2_CONTROL_DISABLE_ALL 0x0 423 #define TSCMOD_HG2_CONTROL_ENABLE_ALL 0x1 424 #define TSCMOD_HG2_CONTROL_DISABLE_CODEC 0x2 425 #define TSCMOD_HG2_CONTROL_ENABLE_CODEC 0x4 426 #define TSCMOD_HG2_CONTROL_READ_CODEC 0x8 427 428 /* TSCMOD PDET CONTROL */ 429 #define TSCMOD_PDET_CONTROL_1G 0x1 430 #define TSCMOD_PDET_CONTROL_10G 0x2 431 #define TSCMOD_PDET_CONTROL_MASK 0x4 432 #define TSCMOD_PDET_CONTROL_SHIFT 0x2 433 #define TSCMOD_PDET_CONTROL_CMD_MASK 0x8 434 #define TSCMOD_PDET_CONTROL_CMD_SHIFT 0x3 435 436 /* for per_lane_control */ 437 #define TSCMOD_UC_SYNC_RAM_MODE 0x1 438 #define TSCMOD_UC_SYNC_WR_MODE 0x2 439 #define TSCMOD_UC_SYNC_REG_MODE 0x0 440 #define TSCMOD_UC_SYNC_RD_MODE 0x0 441 #define TSCMOD_UC_SYNC_MASK_SHIFT 4 442 443 /* 444 #define TSCMOD_UC_SYNC_CMDr 0xf010 445 #define TSCMOD_UC_SYNC_LADDr 0xf011 446 #define TSCMOD_UC_SYNC_HADDr 0xf015 447 #define TSCMOD_UC_SYNC_DATAr 0xffc3 448 */ 449 #define TSCMOD_UC_SYNC_BLOCK 0xffc0 450 #define TSCMOD_UC_SYNC_CMDr 0xffc8 451 #define TSCMOD_UC_SYNC_LADDr 0xffc0 452 #define TSCMOD_UC_SYNC_HADDr 0xffc1 453 #define TSCMOD_UC_SYNC_DATAr 0xffc3 454 455 #define TSCMOD_FAULT_CL49 0x1 456 #define TSCMOD_FAULT_CL48 0x2 457 #define TSCMOD_FAULT_CL82 0x4 458 #define TSCMOD_FAULT_RF 0x1 459 #define TSCMOD_FAULT_LF 0x2 460 #define TSCMOD_FAULT_LI 0x4 461 462 #define TSCMOD_REG_RD 0 463 #define TSCMOD_REG_WR 1 464 #define TSCMOD_REG_MO 2 465 466 #define TSCMOD_CL72_AN_MASK 0xf0 467 #define TSCMOD_CL72_AN_FORCED_ENABLE 0x30 468 #define TSCMOD_CL72_AN_FORCED_DISABLE 0x70 469 #define TSCMOD_CL72_AN_NO_FORCED 0x10 470 471 #define TSCMOD_CL72_HW_MASK 0x0f 472 #define TSCMOD_CL72_HW_ENABLE 0x03 473 #define TSCMOD_CL72_HW_DISABLE 0x01 474 #define TSCMOD_CL72_HW_RESTART 0x08 475 476 #define TSCMOD_CL72_STATUS_RESET 0x100 477 #define TSCMOD_CL72_STATUS_READ 0x200 478 479 #define TSCMOD_SYMM_PAUSE 0x1 480 #define TSCMOD_ASYM_PAUSE 0x2 481 482 #define TSCMOD_ABILITY_SYMM_PAUSE 0x10000 483 #define TSCMOD_ABILITY_ASYM_PAUSE 0x20000 484 485 #define TSCMOD_AN_SET_RF_DISABLE 0x400 486 #define TSCMOD_AN_SET_SGMII_SPEED 0x100 487 #define TSCMOD_AN_SET_SGMII_MASTER 0x200 488 #define TSCMOD_AN_SET_HG_MODE 0x1000 489 #define TSCMOD_AN_SET_FEC_MODE 0x2000 490 #define TSCMOD_AN_SET_CL72_MODE 0x4000 491 #define TSCMOD_AN_SET_CL37_ATTR 0x8000 492 #define TSCMOD_AN_SET_CL48_SYNC 0x10000 493 #define TSCMOD_AN_SET_LK_FAIL_INHIBIT_TIMER_NO_CL72 0x20000 494 #define TSCMOD_AN_SET_CL73_FEC_OFF 0x40000 495 #define TSCMOD_AN_SET_CL73_FEC_ON 0x80000 496 497 498 #define TSCMOD_COLD_RESET_MODE_MASK 0xff 499 #define TSCMOD_COLD_RESET_MODE_SHIFT 8 500 #define TSCMOD_COLD_RESET_BASIC 0x1 501 #define TSCMOD_AN_CTL_LINK_FAIL_CL72_WAIT_TIMER 0x2 502 #define TSCMOD_AN_CTL_LINK_FAIL_NOCL72_WAIT_TIMER 0x4 503 #define TSCMOD_AN_CTL_CL73_ERROR_TIMER 0x8 504 #define TSCMOD_PLL_VCO_STEP 0x10 505 #define TSCMOD_RAM_BASE_ADDR 0x20 506 507 508 #define TSCMOD_AN_GET_CL73_ABIL 0xa 509 #define TSCMOD_AN_GET_CL37_ABIL 0xb 510 #define TSCMOD_AN_GET_MISC_ABIL 0xc 511 #define TSCMOD_AN_GET_LP_CL73_ABIL 0xa8 512 #define TSCMOD_AN_GET_LP_CL37_ABIL 0xb8 513 #define TSCMOD_AN_GET_LP_MISC_ABIL 0xc8 514 #define TSCMOD_AN_GET_LP_SGMII_ABIL 0xd8 515 516 #define TSCMOD_TAP_KX 0x1 517 #define TSCMOD_TAP_OS 0x2 518 #define TSCMOD_TAP_BR 0x4 519 #define TSCMOD_TAP_KR 0x8 520 #define TSCMOD_TAP_2P5 0x10 521 #define TSCMOD_TAP_REG 0x20 522 523 524 /* internal if macro */ 525 #define TSCMOD_IIF_XLAUI 0x10 526 #define TSCMOD_IIF_SR4 0x20 527 #define TSCMOD_IIF_SFPDAC 0x40 528 #define TSCMOD_IIF_NOXFI 0x80 529 530 #define TSCMOD_DIAG_CL72_DONE 0x0 531 #define TSCMOD_DIAG_CL72_START 0x1 532 #define TSCMOD_DIAG_CL72_LOCK 0x2 533 #define TSCMOD_DIAG_CL72_RX_TRAINED 0x4 534 535 #define TSCMOD_DIAG_PMD_LOCK_LIVE 0x0 536 #define TSCMOD_DIAG_PMD_LOCK_LATCH 0x1 537 #define TSCMOD_DIAG_PMD_INFO_LIVE 0x2 538 #define TSCMOD_DIAG_PMD_INFO_LATCH 0x4 539 #define TSCMOD_DIAG_PMD_INFO_LOCK_BIT 0x1 540 #define TSCMOD_DIAG_PMD_INFO_SDET_BIT 0x2 541 542 #define TSCMOD_DIAG_AN_MODE_CL73 0x1 543 #define TSCMOD_DIAG_AN_MODE_CL37 0x2 544 #define TSCMOD_DIAG_AN_MODE_CL73BAM 0x4 545 #define TSCMOD_DIAG_AN_MODE_CL37BAM 0x8 546 #define TSCMOD_DIAG_AN_MODE_HPAM 0x10 547 #define TSCMOD_DIAG_AN_MODE_SGMII 0x20 548 549 #define TSCMOD_FWMODE_RD 0x0 550 #define TSCMOD_FWMODE_WR 0x1 551 552 #define TSCMOD_RXP_REG_OFF 0x0 553 #define TSCMOD_RXP_REG_ON 0x1 554 #define TSCMOD_RXP_UC_OFF 0x2 555 #define TSCMOD_RXP_UC_ON 0x3 556 #define TSCMOD_RXP_REG_RD 0xa 557 #define TSCMOD_RXP_UC_RD 0xb 558 #define TSCMOD_RXP_UC_CLR 0xc 559 560 #define TSCMOD_UC_CAP_ALL 0x1 561 #define TSCMOD_UC_CAP_RXP 0x2 562 563 #define TSCMOD_UC_L0 0x0 564 #define TSCMOD_UC_L1 0x1 565 #define TSCMOD_UC_L2 0x2 566 #define TSCMOD_UC_L3 0x3 567 #define TSCMOD_UC_CORE 0x4 568 #define TSCMOD_UC_D0 0x5 569 #define TSCMOD_UC_D1 0x6 570 571 #define TSCMOD_UC_CL72_SWITCH_OVER 0x2 572 #define TSCMOD_UC_CREDIT_PROGRAM 0x3 573 #define TSCMOD_UC_CL37_HR2_WAR 0x4 574 #define TSCMOD_UC_CL72_CLEAR 0x5 575 #define TSCMOD_UC_CL72_WAIT_CLEAN 0x6 576 #define TSCMOD_UC_CL72_DEBUG_INFO 0x7 577 578 579 #define TSCMOD_FEC_VAL_MASK 0x0f 580 #define TSCMOD_FEC_CTRL_MASK 0xf0 581 #define TSCMOD_FEC_LANE_MASK 0xf00 582 #define TSCMOD_FEC_LANE_OVRW_MASK 0xf000 583 #define TSCMOD_FEC_SUB_MODE_MASK 0xff0000 584 #define TSCMOD_FEC_CTRL_SHIFT 4 585 #define TSCMOD_FEC_LANE_SHIFT 8 586 #define TSCMOD_FEC_LANE_OVRW_SHIFT 12 587 #define TSCMOD_FEC_SUB_MODE_SHIFT 16 588 #define TSCMOD_FEC_CTL_CNTR 0x0 589 #define TSCMOD_FEC_CTL_CC 0x1 590 #define TSCMOD_FEC_CTL_UC 0x2 591 #define TSCMOD_FEC_CTL_INJECT 0x3 592 #define TSCMOD_FEC_CTL_FS_RD 0x4 593 /* FS: forced speed */ 594 #define TSCMOD_FEC_CTL_FS_SET_ON 0x5 595 #define TSCMOD_FEC_CTL_FS_SET_OFF 0x6 596 #define TSCMOD_FEC_CTL_AN_CL73_RD 0x7 597 #define TSCMOD_FEC_CTL_AN_CL37_RD 0x8 598 #define TSCMOD_FEC_SUB_MODE_ERR0 0x1 599 600 /* for cidL */ 601 #define TSC623_SDK_42585_A1 0x1 602 #define TSC623_SDK_45197 0x2 603 #define TSC623_PHY_887 0x8 604 #define TSC623_PHY_891 0x10 605 #define TSC623_PHY_884 0x20 606 #define TSC623_PHY_896 0x40 607 #define TSC623_PHY_867 0x80 608 #define TSC623_SDK_45418 0x200 609 #define TSC623_SDK_45283 0x400 610 #define TSC623_SDK_45731 0x800 611 #define TSC623_PHY_916 0x1000 612 #define TSC623_PHY_892 0x4000 613 #define TSC623_SDK_45682 0x8000 614 #define TSC623_SDK_45789_A1 0x10000 615 #define TSC623_SDK_46061 0x20000 616 #define TSC623_SDK_46060 0x40000 617 #define TSC623_PHY_917 0x200000 618 #define TSC623_PHY_863 0x400000 619 #define TSC623_PHY_864 0x800000 620 #define TSC623_SDK_46338 0x1000000 621 #define TSC623_SDK_43138 0x2000000 622 #define TSC623_SDK_46475 0x4000000 623 #define TSC623_SDK_46753 0x8000000 624 #define TSC623_SDK_46913 0x10000000 625 #define TSC623_SDK_46955 0x40000000 626 627 #define TSC623_SDK_46725_P0 0x1 628 #define TSC623_SDK_46725_P1 0x2 629 #define TSC623_SDK_47112 0x10 630 #define TSC623_SDK_47114 0x20 631 #define TSC623_SDK_46764 0x80 632 #define TSC623_SDK_46923 0x200 633 #define TSC623_PHY_999 0x400 634 #define TSC623_PHY_926 0x800 635 #define TSC623_SDK_47195 0x1000 636 #define TSC623_SDK_47058 0x2000 637 #define TSC623_SDK_47365 0x4000 638 #define TSC623_PHY_1015 0x8000 639 #define TSC623_SDK_46788 0x10000 640 #define TSC623_PHY_965 0x20000 641 #define TSC623_PHY_1023 0x80000 642 #define TSC623_SDK_46785 0x100000 643 #define TSC623_SDK_46786 0x200000 644 #define TSC623_PHY_1013 0x400000 645 #define TSC623_PHY_1073 0x1000000 646 #define TSC623_SDK_48904 0x2000000 647 #define TSC623_PHY_1100 0x4000000 648 #define TSC623_SDK_48705 0x8000000 649 #define TSC628_PHY_1095 0x10000000 650 #define TSC628_PHY_1108 0x20000000 651 #define TSC628_PHY_1105 0x80000000 652 653 #define TSC628_PHY_1111 0x1 654 #define TSC628_SDK_49139 0x2 655 #define TSC628_PHY_1116 0x4 656 #define TSC628_PHY_1119 0x8 657 #define TSC628_SDK_49889 0x10 658 #define TSC628_SDK_51300 0x20 659 #define TSC628_PHY_1092 0x100 660 #define TSC628_SDK_49465 0x200 661 #define TSC628_PHY_1123 0x1000 662 #define TSC628_SDK_51441 0x2000 663 #define TSC628_SDK_49835 0x4000 664 #define TSC628_SDK_51674 0x8000 665 #define TSC628_SDK_50095 0x10000 666 #define TSC628_PHY_1166 0x20000 667 #define TSC628_SDK_48752 0x100000 668 #define TSC628_SDK_47653 0x200000 669 #define TSC628_SDK_48449 0x400000 670 #define TSC628_SDK_51547 0x800000 671 #define TSC628_SDK_52038 0x1000000 672 #define TSC628_SDK_50212 0x2000000 673 #define TSC628_SDK_48449_P2 0x4000000 674 #define TSC628_SDK_52713 0x8000000 675 #define TSC628_SDK_52241 0x10000000 676 #define TSC628_SDK_52715 0x20000000 677 #define TSC628_SDK_52833 0x40000000 678 #define TSC628_SDK_53261 0x80000000 679 680 #define TSC640_SDK_39435 0x1 681 #define TSC640_SDK_53070 0x4 682 #define TSC640_SDK_53940 0x8 683 #define TSC640_SDK_54357 0x10 684 #define TSC640_SDK_54950 0x20 685 #define TSC640_SDK_48996 0x80 686 #define TSC640_SDK_54392 0x100 687 #define TSC640_SDK_54943 0x200 688 #define TSC640_SDK_54606 0x800 689 #define TSC640_SDK_53855 0x1000 690 #define TSC640_SDK_55448 0x2000 691 #define TSC640_SDK_56119 0x4000 692 #define TSC640_SDK_56749 0x8000 693 #define TSC640_SDK_55315 0x10000 694 #define TSC640_SDK_57764 0x20000 695 #define TSC640_SDK_58338 0x40000 696 697 #define TSCMOD_MODEL_REVID_A0 0x00 698 #define TSCMOD_MODEL_REVID_A1 0x01 699 #define TSCMOD_MODEL_REVID_A2 0x02 700 701 #define TSCMOD_MODEL_PROJ_TD2 0x0001 702 #define TSCMOD_MODEL_PROJ_HR2 0x0002 703 #define TSCMOD_MODEL_TYPE_MASK 0x000f 704 #define TSCMOD_MODEL_LET_MASK 0x00f0 705 #define TSCMOD_MODEL_REV_MASK 0x0f00 706 #define TSCMOD_MODEL_PROJ_MASK 0xf000 707 #define TSCMOD_MODEL_LET_SHIFT 4 708 #define TSCMOD_MODEL_REV_SHIFT 8 709 #define TSCMOD_MODEL_PROJ_SHIFT 12 710 #define TSCMOD_MODEL_TYPE_IS(_tsc) \ 711 ((_tsc)->model_type) 712 713 #define TSCMOD_MODEL_TYPE_GET(_tsc) \ 714 ((_tsc->model_type)&TSCMOD_MODEL_TYPE_MASK) 715 716 #define TSCMOD_MODEL_TYPE_SET(_tsc,_val) \ 717 ((_tsc->model_type)=(((_tsc->model_type) & ~TSCMOD_MODEL_TYPE_MASK)|(_val&TSCMOD_MODEL_TYPE_MASK))) 718 719 #define TSCMOD_MODEL_LET_GET(_tsc) \ 720 (((_tsc->model_type)&TSCMOD_MODEL_LET_MASK)>>TSCMOD_MODEL_LET_SHIFT) 721 722 #define TSCMOD_MODEL_LET_SET(_tsc,_val) \ 723 ((_tsc->model_type)=(((_tsc->model_type)& ~TSCMOD_MODEL_LET_MASK)|((_val<<TSCMOD_MODEL_LET_SHIFT)&TSCMOD_MODEL_LET_MASK))) 724 725 #define TSCMOD_MODEL_REV_GET(_tsc) \ 726 (((_tsc->model_type)&TSCMOD_MODEL_REV_MASK)>>TSCMOD_MODEL_REV_SHIFT) 727 728 #define TSCMOD_MODEL_REV_SET(_tsc,_val) \ 729 ((_tsc->model_type)=(((_tsc->model_type)& ~TSCMOD_MODEL_REV_MASK)|((_val<<TSCMOD_MODEL_REV_SHIFT)&TSCMOD_MODEL_REV_MASK))) 730 731 #define TSCMOD_MODEL_REVID_GET(_tsc) \ 732 ((((_tsc->model_type)&TSCMOD_MODEL_REV_MASK)>>TSCMOD_MODEL_REV_SHIFT)|((_tsc->model_type)&TSCMOD_MODEL_LET_MASK)) 733 734 #define TSCMOD_MODEL_PROJ_GET(_tsc) \ 735 (((_tsc->model_type)&TSCMOD_MODEL_PROJ_MASK)>>TSCMOD_MODEL_PROJ_SHIFT) 736 737 #define TSCMOD_MODEL_PROJ_SET(_tsc,_val) \ 738 ((_tsc->model_type)=(((_tsc->model_type)& ~TSCMOD_MODEL_PROJ_MASK)|((_val<<TSCMOD_MODEL_PROJ_SHIFT)&TSCMOD_MODEL_PROJ_MASK))) 739 740 #define TSCMOD_TX_PI_MODE_MASK 0xf 741 #define TSCMOD_TX_PI_PPM_RESET 0x1 742 #define TSCMOD_TX_PI_PPM_SET 0x2 743 #define TSCMOD_TX_PI_PPM_RD 0x3 744 745 #define TSCMOD_LPI_BYPASS 0x10 /**< enable/disable LPI Bypass the SerDes */ 746 #define TSCMOD_LPI_BYPASS_SET(enable) (enable |= TSCMOD_LPI_BYPASS) 747 #define TSCMOD_LPI_BYPASS_CLR(enable) (enable &= ~TSCMOD_LPI_BYPASS) 748 #define TSCMOD_LPI_BYPASS_GET(enable) (enable & TSCMOD_LPI_BYPASS ? 1 : 0) 749 750 #define TSCMOD_DIAG_PRBS_POLY7 0 751 #define TSCMOD_DIAG_PRBS_POLY9 1 752 #define TSCMOD_DIAG_PRBS_POLY11 2 753 #define TSCMOD_DIAG_PRBS_POLY15 3 754 #define TSCMOD_DIAG_PRBS_POLY23 4 755 #define TSCMOD_DIAG_PRBS_POLY31 5 756 #define TSCMOD_DIAG_PRBS_POLY58 6 757 758 /* 759 #define BRCM_TSCMOD_DEBUG 1 760 */ 761 762 /* This struct is a building block of a string associated function table. 763 * It is used to override native PCS Tier1 functions. No doxygen documentation 764 * for this. 765 */ 766 typedef struct strToPCSFunction { 767 char* p; 768 int (*fp)(tscmod_st*); 769 } str2PCSFn; 770 771 #include "tscmod.h" 772 773 774 extern str2PCSFn str2PCSFunc; 775 776 extern void tscmod_init_called(int x); 777 extern void tscmod_init(void); 778 extern void tscmod_tier1_selector(const char* s,tscmod_st* c, int *retVal); 779 extern void tscmod_read_cfg(const char* fileName); 780 extern void print_config(int unit, int port); 781 extern int tscmod_searchPCSFuncTable(const char* selStr, tscmod_st* ws); 782 extern void copy_tscmod_st(tscmod_st *from, tscmod_st *to); 783 /* extern int isLaneEnabled(tscmod_lane_select ls, int lane); */ 784 /* extern tscmod_model_type getGenericModelType(tscmod_model_type model); */ 785 extern const char* getLaneStr(tscmod_lane_select ls); 786 extern tscmod_spd_intfc_type tscmod_spd_intf_s2e(char* s); 787 extern const char* tscmod_aspd_e2s(tscmod_aspd_type aspd_e) ; 788 extern const char* tscmod_aspd_vec2s(int vec) ; 789 extern tscmod_aspd_type tscmod_spd2aspd(tscmod_st* ws) ; 790 extern int getLaneSelect(int lane) ; 791 792 /*! 793 \mainpage TSCMOD Documentation (Beta) 794 795 This is the documentation site for TSCMod (<b>T</b>DM <b>S</b>erdes controller</b> <b>C</b>onfiguration <b>MOD</b>ule) 796 797 \version 0.2 798 799 \author TSCMod Team 800 801 \date 06/25/10 802 803 <B>Introduction</B><br> 804 805 TDM Serdes controller Configuration Module (TSCMod) is a source-code/binary distributable 806 multi tiered library that defines a hardware abstraction layer for various 807 configuration modes of the broadcom TDM serdes IP. This document expects 808 the reader to be familiar with the TSC architecture. 809 810 The tiered structure progressively encapsulates register accesses and sequence 811 hiding complexities like indirect addressing (Address extension registers or 812 AER) and access protocol (MDIO CL22/CL45) implementation. The Tier1 layer, 813 also called TSCMod Procedures are building blocks to construct comprehensive 814 TSC Tier2 layers also called TSCMod sequences. 815 816 Tier1 procedures are fixed sequences of register accesses, accomplishing a 817 specific sub-configuration. In general they are mode aware (combo or 818 independent) and only affect independent ports. 819 820 The full list of Tier1 procedures are tabulated below. 821 822 TSCMod architecture documentation is created using doxygen and so follows the 823 code structure. Please use the following guidelines to use the documentation. 824 825 The documentation is stored in tabs. If you are reading this you are in the 826 main tab. (See the top left corner of our browser). The other tabs you will 827 see are 'classes' where the #tscmod_st struct is visible and 'files', where following files are visible. 828 829 \li tscmod_cfg_seq.c 830 \li tscmod_enum_defines.c 831 \li tscmod_main.c 832 \li tscmod_phyreg.c 833 834 \li tscmod_defines.h 835 \li tscmod_enum_defines.h 836 \li tscmod_main.h 837 \li tscmod_phyreg.h 838 839 All Tier1 procedures have a fixed signature. They return an error code and 840 accept a reference to a C struct (called #tscmod_st). #tscmod_st is used to pass 841 input parameters to the Tier1 procedures and occassionally stores a return 842 value from the Tier1 procedure. #tscmod_st remembers the context of one TSC 843 (not one port or one lane). If the system has multiple TSCs, the software 844 platform must create and maintain that many #tscmod_st structures. 845 846 TSCs can be programmed per lane or per port (independent lane mode or 847 combo mode). Platforms control the lanes on which Tier1 procedures operate by 848 setting the #tscmod_st.lane_select element. The lane specific information is set 849 in the #tscmod_st.per_lane_control element which has fields dedicated to each of 850 the 4 lanes. In combo mode, the lane_select element should be set to zero and 851 any inputs to the Tier1 functions should be set in the lane 0 fields. 852 853 Tier1 procedures have no programmatic order dependencies. This implies that the 854 effect of a Tier1 is constant regardless of the state of the TSC. 855 856 The exceptions are 857 \li #tscmod_set_port_mode function must be called before others. 858 \li Order mandated by TSC architecture. 859 \li Aggregate registers which control features of multiple lanes in TSC. 860 861 <B>TSCMod interface to System Platforms</B><br> 862 863 TSCMod has an unambiguous interface mechanism to system platforms. Platforms can 864 be software systems like MDK, and SDK or customer specific software. It can 865 also be validation platforms including HDL (verilog/systemVerilog/Vera) based 866 testbenches. 867 868 TSCMod functions (tier1 and tier2) operates on a single TSC at a time. It 869 can be used to access multiple lanes within the TSC, but cannot access 870 multiple TSCs simultaneously. To access different TSCs multiple calls 871 to tier1 procedures are needed. 872 873 TSCMod defines a structure (called tscmod_st) which encapsulates all information 874 of a TSC needed by TSCMod. This structure should be created and maintained 875 by system platforms, one per TSC. Typically an array of tscmod_st structs 876 is created, accessible by the TSC's unique physical address. 877 878 All Tier1 procedures are called with a reference to a tscmod_st struct. of the 879 TSC being accessed. TSCMod will read and write information to the struct. 880 as needed. Adopting platforms should treat this struct as read only and should 881 not modify it. 882 883 TSC lanes can architecturally be accessed in two ways. 884 \li 1.If the 'prt_ad' straps of the TSC are strapped to a specific 885 value, say 'lane_add' and the multiport_en strap is enabled, lanes are accessed 886 as lane_add, lane_add+1, lane_add+2 and lane_add+3. This method is not 887 currently supported by TSCMod. 888 \li 2.Lanes can be accessed by using the AER offset method. This is the 889 preferred method and is currently supported by TSCMod. 890 891 Register access within lanes have the following pattern. 892 893 \li In independent mode tier1 procedures can be called for multiple lanes 894 lanes simultaneously. The lanes are chosen using #tscmod_st.lane_select 895 \li In dual xgxs mode two lanes form a logical port. So Tier1 procedures are 896 called for each dual port. Individual lanes are still accessible. 897 \li In combo mode, Tier1 procedures are called for a TSC. Register access 898 for individual lanes are still available via #tscmod_st.lane_select. 899 900 <B>Input/Output for Tier1 procedures</B><br> 901 902 As previously mentioned the only input to all tier1 procedures is #tscmod_st. 903 All Tier1 procedures return a status value. Certain procedures, such as 904 'read_rev_id' which have to return a value modify a general purpose element 905 #tscmod_st.accData. Platforms that don't use returned information can ignore 906 this element. Others can pick up the information from #tscmod_st::accData 907 908 <B>TSCMod Register Access Methods</B><br> 909 910 The virtual drivers in TSCMod will eventually attach to platform specific 911 drivers. But prior to that, the registers, fields, and thier address (which 912 depends on the addressing mode and cl22/cl45 considerations) are disambiguated. 913 The psueodo code below illustrates this breakdown. 914 915 \code 916 TSC40_REG_READ(unit, pc, flags, reg_addr, val); 917 * unit ignored 918 * pc is tscmod_st 919 * flags ignored 920 * reg_addr is the arch. address (i.e. needs to decoded) 921 * val is a short int pointer to store the read value. 922 923 tscmod_reg_aer_read(unit, pc, reg_addr, val); 924 * pc is the same tscmod_st 925 * reg_addr is unresolved addr 926 * val is the same short int pointer to store the read value. 927 928 * We fix address for dual XGXS mode. 929 * We fix address for dual strap offsets, multiport_addr_en port etc. 930 * i.e. reg_addr converted to phy_reg_addr 931 * call cl22 or cl45 drivers as needed. Assume we go cl22 way here. 932 933 tscmod_aer_cl22_read(pc, phy_reg_addr, val) 934 * pc is the same tscmod_st 935 * phy_reg_addr is the resolved addr 936 * val is the same short int pointer to store the read value. 937 938 * Figure out broadcast/per lane. 939 * Adjust address again for per lane. i.e. write lane num to bits 16,17 940 * Conduct a series of reg. accesses based on indirect (AER) reg. access 941 * For example, write the offset to reg. 0x1f etc. 942 943 tscmod_cl22_read(pc, phy_reg_addr, val) 944 * pc is the same tscmod_st 945 * phy_reg_addr is the resolved addr 946 * val is the same short int pointer to store the read value. 947 948 * call the physical driver. (compiled for target platform) 949 * In TSC verilog, we call a DPI which calls the verilog task 950 * In Trident verilog, we call a DPI which directly access the Parallel 951 952 * control bus of the MDIO ( for simulation speedup) 953 * In MDK (vxworks vers.), we call our cdk_miim_read(), BRCM medium 954 * independent driver 955 * In SDK(all versions) we call a function ptr. that is provided by 956 * the broadcom software team. 957 \endcode 958 959 \note The TSCMod and documentation is work in progress. Table below 960 961 <table cellspacing=0> 962 963 <tr><td colspan=3><B>'Current Status' bit-mappings</B></td></tr> 964 965 <tr><td><B>Tier1 </B> </td><td><B>Handle</B> </td><td>PCS or PMA</td><td><B>Status</B></td></tr> 966 <tr><td>tscmod_aer_lane_select </td><td> AER_LANE_SELECT </td><td> PMA/PMD </td><td>- <td></tr> 967 <tr><td>tscmod_tx_lane_disable </td><td> TX_LANE_DISABLE </td><td> PMA/PMD </td><td>- <td></tr> 968 <tr><td>tscmod_autoneg_page_set </td><td> AUTONEG_PAGE_SET </td><td> PMA/PMD </td><td>- <td></tr> 969 <tr><td>tscmod_cjpat_crpat_control </td><td> CJPAT_CRPAT_CONTROL </td><td> PCS </td><td>DONE <td></tr> 970 <tr><td>tscmod_lane_swap </td><td> LANE_SWAP </td><td> PMA/PMD </td><td>DONE <td></tr> 971 <tr><td>tscmod_pll_lock_wait </td><td> PLL_LOCK_WAIT </td><td> PMA/PMD </td><td>DONE <td></tr> 972 <tr><td>tscmod_wait_pmd_lock </td><td> WAIT_PMD_LOCK </td><td> PMA/PMD </td><td>DONE <td></tr> 973 <tr><td>tscmod_prbs_check </td><td> PRBS_CHECK </td><td> PMA/PMD </td><td>DONE <td></tr> 974 <tr><td>tscmod_print_tscmod_st </td><td> PRINT_TSCMOD_ST </td><td> NONE </td><td>- <td></tr> 975 <tr><td>tscmod_prog_data </td><td> PROG_DATA </td><td> PCS </td><td>NOTDONE <td></tr> 976 <tr><td>tscmod_reg_read </td><td> REG_READ </td><td> PCS </td><td>- <td></tr> 977 <tr><td>tscmod_reg_write </td><td> REG_WRITE </td><td> PCS </td><td>- <td></tr> 978 <tr><td>tscmod_revid_read </td><td> REVID_READ </td><td> PCS </td><td>DONE <td></tr> 979 <tr><td>tscmod_rx_loopback_control </td><td> RX_LOOPBACK_CONTROL </td><td> PCS </td><td>DONE <td></tr> 980 <tr><td>tscmod_rx_seq_control </td><td> RX_SEQ_CONTROL </td><td> PMA/PMD </td><td>DONE <td></tr> 981 <tr><td>tscmod_set_port_mode </td><td> SET_PORT_MODE </td><td> BOTH </td><td>DONE <td></tr> 982 <tr><td>tscmod_soft_reset </td><td> SOFT_RESET </td><td> PCS </td><td>DONE <td></tr> 983 <tr><td>tscmod_tx_bert_control </td><td> TX_BERT_CONTROL </td><td> PCS </td><td>DONE <td></tr> 984 <tr><td>tscmod_tx_loopback_control </td><td> TX_LOOPBACK_CONTROL </td><td> PCS </td><td>DONE <td></tr> 985 <tr><td>tscmod_tx_rx_packets_check </td><td> TX_RX_PACKETS_CHECK </td><td> PCS </td><td>NOTDONE <td></tr> 986 <tr><td>tscmod_tx_rx_polarity </td><td> TX_RX_POLARITY </td><td> PCS </td><td>DONE <td></tr> 987 <tr><td>tscmod_100fx_control </td><td> 100FX_CONTROL </td><td> PCS </td><td>NOTDONE <td></tr> 988 <tr><td>tscmod_autoneg_set </td><td> AUTONEG_SET </td><td> PCS </td><td>INPROG <td></tr> 989 <tr><td>tscmod_autoneg_get </td><td> AUTONEG_GET </td><td> PCS </td><td>INPROG <td></tr> 990 <tr><td>tscmod_autoneg_control </td><td> AUTONEG_CONTROL </td><td> PCS </td><td>INPROG <td></tr> 991 <tr><td>tscmod_cjpat_crpat_check </td><td> CJPAT_CRPAT_CHECK </td><td> PCS </td><td>DONE <td></tr> 992 <tr><td>tscmod_clause72_control </td><td> CLAUSE72_CONTROL </td><td> PCS </td><td>NOTDONE <td></tr> 993 <tr><td>tscmod_core_reset </td><td> CORE_RESET </td><td> PCS </td><td>DONE <td></tr> 994 <tr><td>tscmod_fwmode_control </td><td> FWMODE_CONTROL </td><td> PMD </td><td>DONE <td></tr> 995 <tr><td>tscmod_duplex_control </td><td> DUPLEX_CONTROL </td><td> PCS </td><td>NOTDONE <td></tr> 996 <tr><td>tscmod_parallel_detect_control </td><td> PARALLEL_DETECT_CONTROL </td><td> PCS </td><td>NOTDONE <td></tr> 997 <tr><td>tscmod_pll_sequencer_control </td><td> PLL_SEQUENCER_CONTROL </td><td> PMA/PMD </td><td>DONE <td></tr> 998 <tr><td>tscmod_port_stat_display </td><td> PORT_STAT_DISPLAY </td><td> BOTH </td><td>NOTDONE <td></tr> 999 <tr><td>tscmod_prbs_control </td><td> PRBS_CONTROL </td><td> PMA/PMD </td><td>DONE <td></tr> 1000 <tr><td>tscmod_set_spd_intf </td><td> SET_SPEED_INTF </td><td> BOTH </td><td>INPROG <td></tr> 1001 <tr><td> .SPEED_10M </td><td> SPD_10_SGMII </td><td>DONE <td></tr> 1002 <tr><td> .SPEED_100M </td><td> SPD_100_SGMII </td><td>DONE <td></tr> 1003 <tr><td> .SPEED_1000M </td><td> SPD_1000_SGMII </td><td>DONE <td></tr> 1004 <tr><td> .SPEED_2p5G_X1 </td><td> SPD_2500 </td><td>DONE <td></tr> 1005 <tr><td> .SPEED_5G_X4 </td><td> </td><td> <td></tr> 1006 <tr><td> .SPEED_6G_X4 </td><td> </td><td> <td></tr> 1007 <tr><td> .SPEED_10G_X4 </td><td> </td><td> <td></tr> 1008 <tr><td> .SPEED_10G_CX4 </td><td> SPD_10000/SPD_10000_HI </td><td>DONE<td></tr> 1009 <tr><td> .SPEED_12G_X4 </td><td> </td><td> <td></tr> 1010 <tr><td> .SPEED_12p5G_X4 </td><td> </td><td> <td></tr> 1011 <tr><td> .SPEED_13G_X4 </td><td> </td><td> <td></tr> 1012 <tr><td> .SPEED_15G_X4 </td><td> </td><td> <td></tr> 1013 <tr><td> .SPEED_16G_X4 </td><td> </td><td> <td></tr> 1014 <tr><td> .SPEED_1G_KX1 </td><td> </td><td> <td></tr> 1015 <tr><td> .SPEED_10G_KX4 </td><td> </td><td> <td></tr> 1016 <tr><td> .SPEED_10G_KR1 </td><td> </td><td> <td></tr> 1017 <tr><td> .SPEED_5G_X1 </td><td> </td><td> <td></tr> 1018 <tr><td> .SPEED_6p36G_X1 </td><td> </td><td> <td></tr> 1019 <tr><td> .SPEED_20G_CX4 </td><td> </td><td> <td></tr> 1020 <tr><td> .SPEED_21G_X4 </td><td> </td><td> <td></tr> 1021 <tr><td> .SPEED_25p45G_X4 </td><td> </td><td> <td></tr> 1022 <tr><td> .SPEED_10G_X2_NOSCRAMBLE </td><td> </td><td> <td></tr> 1023 <tr><td> .SPEED_10G_CX2_NOSCRAMBLE </td><td> </td><td> <td></tr> 1024 <tr><td> .SPEED_10p5G_X2 </td><td> </td><td> <td></tr> 1025 <tr><td> .SPEED_10p5G_CX2_NOSCRAMBLE </td><td> </td><td> <td></tr> 1026 <tr><td> .SPEED_12p7G_X2 </td><td> </td><td> <td></tr> 1027 <tr><td> .SPEED_12p7G_CX2 </td><td> </td><td> <td></tr> 1028 <tr><td> .SPEED_10G_X1 </td><td> SPD_10000_XFI </td><td>DONE <td></tr> 1029 <tr><td> .SPEED_40G_X4 </td><td> SPD_40G_X4 </td><td>DONE <td></tr> 1030 <tr><td> .SPEED_20G_X2 </td><td> </td><td> <td></tr> 1031 <tr><td> .SPEED_20G_CX2 </td><td> SPD_20G_DXGXS </td><td>DONE <td></tr> 1032 <tr><td> .SPEED_10G_SFI </td><td> </td><td> <td></tr> 1033 <tr><td> .SPEED_31p5G_X4 </td><td> </td><td> <td></tr> 1034 <tr><td> .SPEED_32p7G_X4 </td><td> </td><td> <td></tr> 1035 <tr><td> .SPEED_20G_X4 </td><td> </td><td> <td></tr> 1036 <tr><td> .SPEED_10G_X2 </td><td> </td><td> <td></tr> 1037 <tr><td> .SPEED_10G_CX2 </td><td> </td><td> <td></tr> 1038 <tr><td> .SPEED_12G_SCO_R2 </td><td> </td><td> <td></tr> 1039 <tr><td> .SPEED_10G_SCO_X2 </td><td> </td><td> <td></tr> 1040 <tr><td> .SPEED_40G_KR4 </td><td> SPD_40G_XLAUI </td><td>DONE <td></tr> 1041 <tr><td> .SPEED_40G_CR4 </td><td> SPD_40G_XLAUI </td><td>DONE <td></tr> 1042 <tr><td> .SPEED_100G_CR10 </td><td> </td><td> <td></tr> 1043 <tr><td> .SPEED_5G_X2 </td><td> </td><td> <td></tr> 1044 <tr><td> .SPEED_15p75G_X2 </td><td> </td><td> <td></tr> 1045 <tr><td> .SPEED_2G_FC </td><td> </td><td> <td></tr> 1046 <tr><td> .SPEED_4G_FC </td><td> </td><td> <td></tr> 1047 <tr><td> .SPEED_8G_FC </td><td> </td><td> <td></tr> 1048 <tr><td> .SPEED_10G_CX1 </td><td> </td><td> <td></tr> 1049 <tr><td> .SPEED_1G_CX1 </td><td> </td><td> <td></tr> 1050 <tr><td> .SPEED_20G_KR2 </td><td> SPD_20G_MLD_DXGXS </td><td>DONE <td></tr> 1051 <tr><td> .SPEED_20G_CR2 </td><td> SPD_20G_MLD_DXGXS </td><td>DONE <td></tr> 1052 <tr><td>tscmod_Idriver_Ipredriver_set </td><td> IDRIVER_IPREDRIVER_SET </td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1053 <tr><td>tscmod_FEC_control </td><td> FEC_CONTROL </td><td> PCS </td><td>NOTDONE <td></tr> 1054 <tr><td>tscmod_firmware_set </td><td> FIRMWARE_SET </td><td> PCS </td><td>NOTDONE <td></tr> 1055 <tr><td>tscmod_packet_size_IPG_set </td><td> PACKET_SIZE_IPG_SET </td><td> PCS </td><td>NOTDONE<td></tr> 1056 <tr><td>tscmod_power_control </td><td> POWER_CONTROL </td><td> PMA/PMD </td><td>DONE<td></tr> 1057 <tr><td>tscmod_rx_loopback_sfpplus </td><td> RX_LOOPBACK_SFPPLUS </td><td> PCS </td><td>NOTDONE <td></tr> 1058 <tr><td>tscmod_scrambler_control </td><td> SCRAMBLER_CONTROL </td><td> PCS </td><td>NOTDONE<td></tr> 1059 <tr><td>tscmod_set_BRCM64B66B </td><td> SET_BRCM64B66B </td><td> PCS </td><td>NOTDONE<td></tr> 1060 <tr><td>tscmod_set_rx_DFE_tap1_override</td><td> SET_RX_DFE_TAP1_OVERRIDE</td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1061 <tr><td>tscmod_set_rx_DFE_tap2_override</td><td> SET_RX_DFE_TAP2_OVERRIDE</td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1062 <tr><td>tscmod_set_rx_DFE_tap3_override</td><td> SET_RX_DFE_TAP3_OVERRIDE</td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1063 <tr><td>tscmod_set_rx_DFE_tap4_override</td><td> SET_RX_DFE_TAP4_OVERRIDE</td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1064 <tr><td>tscmod_set_rx_DFE_tap5_override</td><td> SET_RX_DFE_TAP5_OVERRIDE</td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1065 <tr><td>tscmod_set_rx_PF_override </td><td> SET_RX_PF_OVERRIDE </td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1066 <tr><td>tscmod_set_rx_VGA_override </td><td> SET_RX_VGA_OVERRIDE </td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1067 <tr><td>tscmod_tx_tap_control </td><td> TX_TAP_CONTROL </td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1068 <tr><td>tscmod_rx_p1_slicer_control </td><td> RX_P1_SLICER_CONTROL </td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1069 <tr><td>tscmod_rx_m1_slicer_control </td><td> RX_M1_SLICER_CONTROL </td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1070 <tr><td>tscmod_rx_d_slicer_control </td><td> RX_D_SLICER_CONTROL </td><td> PMA/PMD </td><td>NOTDONE <td></tr> 1071 <tr><td>tscmod_diag </td><td> TSCMOD_DIAG </td><td> BOTH </td><td>INPROG <td></tr> 1072 <tr><td>tscmod_misc_control </td><td> MISC_CONTROL </td><td> BOTH </td><td>INPROG <td></tr> 1073 <tr><td>tscmod_firmware_set </td><td> FIRMWARE_SET </td><td> UCODE </td><td>DONE <td></tr> 1074 </table> 1075 1076 <B>Overriding native with Customer PCS Functions.</B><br> 1077 1078 Customers can attach custom functions to TSCMod. Though it seems to indicate 1079 replacement or augmentation of Tier1 functions accessing registers in the PCS 1080 domain only (PCS Functions), any TSCMod function can be selectively replaced 1081 with this methodology. This makes TSCMod more versatile in handling PHY modules 1082 with different PCS blocks and also locale specific interpretation of tier1 1083 functions. The flow chart provided below shows how overriding is possible. 1084 1085 TSCMod provides a structure, #str2PCSFn, to store a function pointer and 1086 string pointers to identify it. A function Pointer Table #pcsFuncTable is 1087 an array of these structures. The following steps populate #pcsFuncTable table. 1088 \li 1. Initialize each element's string pointer to an identifying string 1089 \li 2. Initialize same element's function pointer to a function 1090 \li 3. Create one element for each overriding function 1091 \li 4. The last table entry must have string pointer and function pointer NULLed 1092 1093 <B>Function Execution.</B><br> 1094 TSCMod user interface provides unique strings to identify all tier1 functions. 1095 Execution of a Tier1 function involves the following steps. 1096 1097 \li 1. Use input string and query Customer PCS Function Table. 1098 \li 2. If the string matches and the associated function pointer is NULLed, we 1099 assume user does not want this Tier1 function. 1100 \li 3. If a non-NULL function pointer is found, we execute it and evaluate the return code. 1101 \li 4. If return code is zero, we exit the loop. Any negative return value is 1102 treated as an error. If return code is 1 (Augmentation mode), we continue to 1103 search for this function in local table and execute it if found. 1104 \li 5. If function is not found we try to find it in the local function table. 1105 1106 <IMG SRC="../../doc/customerPCSsupport.jpg"> 1107 1108 */ 1109 1110 #endif /* _TSCMOD_MAIN_H_ */