tscmod_extra.h (23355B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: wc40_extra.h 8 * Purpose: non-register Macro, data structures and function prototypes for WC driver. 9 */ 10 11 12 #ifndef TSCMOD_EXTRA_H__ 13 #define TSCMOD_EXTRA_H__ 14 15 /* 16 * wc40.h has definitions related to WC registers. It is automatically generated 17 * from RDB files. This file has all non-register Macro, data structures and 18 * function prototypes the WC driver. 19 */ 20 21 /* additional missed register definitions */ 22 23 #define TSCMOD_XGXSBLK0_XGXSSTATUSr 0x8001 24 #define TSCMOD_TX0_ANATXACONTROL0r 0x8061 25 #define TSCMOD_RX0_ANARXCONTROLPCIr 0x80ba 26 #define TSCMOD_COMBO_IEEE0_MIICNTLr 0xffe0 27 #define TSCMOD_MICROBLK_DOWNLOAD_STATUSr 0xffc5 28 #define SERDESDIGITAL_FORCE_SPEED_dr_10G_XFI 0x25 29 #define SERDESDIGITAL_FORCE_SPEED_dr_10G_SFI 0x29 30 31 /* misc. */ 32 #define TSCMOD_PLL_WAIT 400000 /* 400ms */ 33 #define TSCMOD_AN_WAIT 400000 /* 400ms */ 34 #define TX_DRIVER_DFT_LN_CTRL 0x7fff 35 36 #define SERDES_ID0_MODEL_NUMBER_WARPCORE 0x9 37 #define WC_AER_BCST_OFS_STRAP 0x1ff 38 #define OVER1G_UP3_20GPLUS_MASK (DIGITAL3_UP3_DATARATE_25P45GX4_MASK | \ 39 DIGITAL3_UP3_DATARATE_21GX4_MASK | \ 40 DIGITAL3_UP3_DATARATE_31P5G_MASK | \ 41 DIGITAL3_UP3_DATARATE_40G_MASK | \ 42 DIGITAL3_UP3_LAST_MASK) 43 #define PLL_PLLACONTROL4_BIT12_MASK 0x1000 44 #define TSCMOD_UCODE_MAX_LEN (32*1024) 45 #define NUM_LANES 4 /* num of lanes per core */ 46 #define MAX_NUM_LANES 4 /* max num of lanes per port */ 47 #define PROG_DATA_NUM 8 /* 8 * 32 = 256 bits */ 48 49 /* no clock comp in HG combo mode */ 50 #define COMBO_HG_XGXS_nLQnCC \ 51 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQnCC << \ 52 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT) 53 #define COMBO_HG_XGXS_nCC \ 54 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXG_nCC << \ 55 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT) 56 57 /* no clock comp in XE combo mode */ 58 #define COMBO_XE_XGXG_nCC \ 59 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXG_nCC << \ 60 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT) 61 62 /* clock comp in HG combo mode */ 63 #define COMBO_HG_XGXS_nLQ \ 64 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQ << \ 65 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT) 66 67 /* clock comp in XE combo mode */ 68 #define COMBO_XE_XGXS \ 69 (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS << \ 70 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT) 71 72 #define COMBO_CLOCK_COMP_DEFAULT (COMBO_HG_XGXS_nLQnCC | COMBO_XE_XGXG_nCC) 73 #define COMBO_CLOCK_COMP_MASK (XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_MASK | \ 74 XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_MASK) 75 #define IND_CLOCK_COMP_DEFAULT (COMBO_HG_XGXS_nLQnCC | COMBO_XE_XGXG_nCC) 76 #define IND_CLOCK_COMP_DEFAULT_REV_A (COMBO_HG_XGXS_nLQ | COMBO_XE_XGXS) 77 78 /* TSC revision IDs */ 79 80 #define TSCMOD_SERDES_ID0_REVID_A0 0x0000 81 #define TSCMOD_SERDES_ID0_REVID_A1 0x0800 82 #define TSCMOD_SERDES_ID0_REVID_A2 0x1000 83 /* 84 #define TSCMOD_SERDES_ID0_REVID_B0 0x4000 85 #define TSCMOD_SERDES_ID0_REVID_C0 0x8000 86 #define TSCMOD_SERDES_ID0_REVID_D0 0xc000 87 */ 88 89 #define REV_VER_MASK (MAIN0_SERDESID_REV_LETTER_MASK | \ 90 MAIN0_SERDESID_REV_NUMBER_MASK) 91 #define TSCMOD_REVID(_pc) \ 92 ((((TSCMOD_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) 93 #define TSCMOD_REVID_A0(_pc) \ 94 (((((TSCMOD_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 95 TSCMOD_SERDES_ID0_REVID_A0) 96 #define TSCMOD_REVID_A1(_pc) \ 97 (((((TSCMOD_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 98 TSCMOD_SERDES_ID0_REVID_A1) 99 #define TSCMOD_REVID_B0(_pc) \ 100 (((((TSCMOD_DEV_DESC_t *)((_pc) + 1))->info.serdes_id0) & REV_VER_MASK) == \ 101 TSCMOD_SERDES_ID0_REVID_B0) 102 #define TSCMOD_LINK_WAR_REVS(_pc) (TSCMOD_REVID_A0(_pc) || TSCMOD_REVID_A1(_pc)) 103 104 /* div16 and div33 clocks */ 105 106 #define CL72_MISC4_CTRL_DIV16_SHIFT 5 107 #define CL72_MISC4_CTRL_DIV33_SHIFT 3 108 #define CL72_MISC4_CTRL_DIV16_FIELD(_fd) ((_fd) << CL72_MISC4_CTRL_DIV16_SHIFT) 109 #define CL72_MISC4_CTRL_DIV33_FIELD(_fd) ((_fd) << CL72_MISC4_CTRL_DIV33_SHIFT) 110 #define CL72_MISC4_CTRL_DIV16_MASK (0xf << CL72_MISC4_CTRL_DIV16_SHIFT) 111 #define CL72_MISC4_CTRL_DIV33_MASK (0x3 << CL72_MISC4_CTRL_DIV33_SHIFT) 112 113 /* CL73 */ 114 115 #define CL73_AN_ADV_TECH_20G_KR2 (1 << 13) 116 #define CL73_AN_ADV_TECH_100G_CR10 (1 << 10) 117 #define CL73_AN_ADV_TECH_40G_CR4 (1 << 9) 118 #define CL73_AN_ADV_TECH_40G_KR4 (1 << 8) 119 #define CL73_AN_ADV_TECH_10G_KR (1 << 7) 120 #define CL73_AN_ADV_TECH_10G_KX4 (1 << 6) 121 #define CL73_AN_ADV_TECH_1G_KX (1 << 5) 122 #define CL73_AN_ADV_TECH_SPEEDS_MASK (0x3F << 5) 123 #define CL73_AN_ADV_PLUS_KR2_MASK (CL73_AN_ADV_TECH_SPEEDS_MASK | \ 124 CL73_AN_ADV_TECH_20G_KR2) 125 #define CL73_AN_ADV_PAUSE (1 << 10) 126 #define CL73_AN_ADV_ASYM_PAUSE (1 << 11) 127 128 /* VCO frequency ctrl */ 129 130 #define TSCMOD_OS5_VCO_FREQ 0x7200 131 #define TSCMOD_OS8_VCO_FERQ 0x7A00 132 #define TSCMOD_TXCK_MASK 0x1E0 133 #define TSCMOD_RXCK_OVERIDE_MASK (1 << 11) 134 #define TSCMOD_TXCK_SHIFTER 5 135 136 /* Bit 0 CL73 BAM 137 Bit 1 CL73 138 Bit 2 HPBAM 139 Bit 3 HPBAM_vs_SW 140 AutoDetect to 141 Bit 4 CL73 142 Bit 5 143 Bit 6 144 Bit 7 145 SW switch to 146 Bit 8 CL37 147 148 Only 0x5 is the exception. (= 0x102) 149 */ 150 #define TSCMOD_CL73_HPAM_CL37 0x104 151 #define TSCMOD_CL73_HPAM_AUTOCL73_CL37 0x114 152 #define TSCMOD_CL73_HPAM_AUTOCL73 0x014 153 #define TSCMOD_CL73_SW_CL37 0x102 154 155 #define TSCMOD_CL73_HG 0x6 156 #define TSCMOD_CL73_CL37 0x5 157 #define TSCMOD_CL73_HPAM 0x4 158 #define TSCMOD_CL73_HPAM_VS_SW 0x8 159 #define TSCMOD_CL73_WO_BAM 0x2 160 #define TSCMOD_CL73_W_BAM 0x1 161 #define TSCMOD_CL73_DISABLE 0x0 162 163 #define TSCMOD_CL37_W_BAM_HG 6 164 #define TSCMOD_CL37_HR2SPM_W_10G 5 165 #define TSCMOD_CL37_HR2SPM 4 166 #define TSCMOD_CL37_W_10G 3 167 #define TSCMOD_CL37_WO_BAM 2 168 #define TSCMOD_CL37_W_BAM 1 169 #define TSCMOD_CL37_DISABLE 0 170 171 172 /* lane swap functions in XGXSBLK2 are obsolete, use ones in XGXSBLK8 173 * i.e. define TSCMOD_PCS_LANE_SWAP 174 */ 175 #define TSCMOD_PCS_LANE_SWAP 176 #ifdef TSCMOD_PCS_LANE_SWAP 177 /* For Tx lane swap 178 * bits 15-12 11-8 7-4 3-0 represents pcs lane 3,2,1,0 179 * value in each field represents corresponding pmd/pma lane number. 180 * the default map is pma/pmd lane3 maps to pcs lane3, pma lane2 181 * to pcs lane2 and so on. 182 * 183 * For Rx lane swap 184 * The same bit fields represents the pmd/pma lane 3,2,1,0 185 * and the value corresponds the pma/pmd lane number. 186 */ 187 #define TSCMOD_RX_LANE_MAP_DEFAULT 0x3210 188 #define TSCMOD_TX_LANE_MAP_DEFAULT 0x3210 189 #else 190 #define TSCMOD_RX_LANE_MAP_DEFAULT 0x0123 191 #define TSCMOD_TX_LANE_MAP_DEFAULT 0x0123 192 #endif 193 194 /* Register lane access. fixed value, must not change */ 195 196 #define LANE0_ACCESS 1 197 #define LANE1_ACCESS 2 198 #define LANE2_ACCESS 3 199 #define LANE3_ACCESS 4 200 #define LANE_BCST 0xF 201 #define LANE_ACCESS_MASK 0xF 202 203 /* operation modes */ 204 205 #define CUSTOM1_MODE(_pc) ((_pc)->phy_mode == PHYCTRL_LANE_MODE_CUSTOM1) 206 #define CUSTOM_MODE(_pc) (((_pc)->phy_mode == PHYCTRL_LANE_MODE_CUSTOM) || \ 207 ((_pc)->phy_mode == PHYCTRL_LANE_MODE_CUSTOM_3p125MHZ)) 208 #define CUSTOMX_MODE(_pc) (CUSTOM_MODE(_pc) || CUSTOM1_MODE(_pc)) 209 210 #define IS_DUAL_LANE_PORT(_pc) (((_pc)->phy_mode == PHYCTRL_DUAL_LANE_PORT) || \ 211 CUSTOM1_MODE(_pc)) 212 #define IS_QUAD_LANE_PORT(_pc) ((_pc)->phy_mode == PHYCTRL_QUAD_LANE_PORT) 213 #define IS_ONE_LANE_PORT(_pc) ((_pc)->phy_mode == PHYCTRL_ONE_LANE_PORT) 214 215 #define DUAL_LANE_BCST_ENABLE(_pc) \ 216 do { \ 217 if (IS_DUAL_LANE_PORT(_pc)) { \ 218 DEV_CFG_PTR(_pc)->dxgxs = (_pc)->lane_num? 2 :1; \ 219 } \ 220 } while (0) 221 #define DUAL_LANE_BCST_DISABLE(_pc) \ 222 do { \ 223 if (IS_DUAL_LANE_PORT(_pc)) { \ 224 DEV_CFG_PTR(_pc)->dxgxs = 0; \ 225 } \ 226 } while (0) 227 #define AUTONEG_MODE_UNAVAIL(_pc) (CUSTOMX_MODE(_pc)) 228 229 #define TSCMOD_MEM_ALLOC(_size,_name) sal_alloc(_size,_name) 230 #define TSCMOD_MEM_SET(_dst,_val,_len) sal_memset(_dst,_val,_len) 231 #define TSCMOD_UDELAY(_time) sal_udelay(_time) 232 #define TSCMOD_USLEEP(_time) sal_usleep(_time) 233 234 #define FX100_CONTROL1_AUTODET_EN_MASK 4 235 236 /* similar to SOC_PORT_IF_, but within 32 bit range */ 237 typedef enum tscmod_port_if_e { 238 TSCMOD_PORT_IF_NOCXN, /* No physical connection */ 239 TSCMOD_PORT_IF_NULL, /* Pass-through connection without PHY */ 240 TSCMOD_PORT_IF_MII, 241 TSCMOD_PORT_IF_GMII, 242 TSCMOD_PORT_IF_SGMII, 243 TSCMOD_PORT_IF_TBI, 244 TSCMOD_PORT_IF_XGMII, 245 TSCMOD_PORT_IF_RGMII, 246 TSCMOD_PORT_IF_RvMII, 247 TSCMOD_PORT_IF_SFI, 248 TSCMOD_PORT_IF_XFI, 249 TSCMOD_PORT_IF_KR, 250 TSCMOD_PORT_IF_KR4, 251 TSCMOD_PORT_IF_CR, 252 TSCMOD_PORT_IF_CR4, 253 TSCMOD_PORT_IF_XLAUI, 254 TSCMOD_PORT_IF_SR, 255 TSCMOD_PORT_IF_RXAUI, 256 TSCMOD_PORT_IF_XAUI, 257 /* 258 TSCMOD_PORT_IF_SPAUI, 259 TSCMOD_PORT_IF_QSGMII, 260 TSCMOD_PORT_IF_ILKN, 261 TSCMOD_PORT_IF_RCY, 262 TSCMOD_PORT_IF_FAT_PIPE, 263 TSCMOD_PORT_IF_CGMII, 264 TSCMOD_PORT_IF_CAUI, 265 */ 266 TSCMOD_PORT_IF_LR, 267 TSCMOD_PORT_IF_LR4, 268 TSCMOD_PORT_IF_SR4, 269 TSCMOD_PORT_IF_KX, 270 /* 271 TSCMOD_PORT_IF_ZR, 272 TSCMOD_PORT_IF_SR10, 273 TSCMOD_PORT_IF_OTL, 274 TSCMOD_PORT_IF_CPU, 275 TSCMOD_PORT_IF_OLP, 276 TSCMOD_PORT_IF_OAMP, 277 TSCMOD_PORT_IF_ERP, 278 TSCMOD_PORT_IF_TM_INTERNAL_PKT, 279 */ 280 TSCMOD_PORT_IF_SR2, 281 TSCMOD_PORT_IF_KR2, 282 TSCMOD_PORT_IF_CR2, 283 TSCMOD_PORT_IF_XFI2, 284 TSCMOD_PORT_IF_XLAUI2, 285 TSCMOD_PORT_IF_COUNT /* last, please */ 286 } tscmod_port_if_t; 287 288 #define TSCMOD_IF_SR (1 << TSCMOD_PORT_IF_SR) 289 #define TSCMOD_IF_SR4 (1 << TSCMOD_PORT_IF_SR4) 290 #define TSCMOD_IF_LR (1 << TSCMOD_PORT_IF_LR) 291 #define TSCMOD_IF_LR4 (1 << TSCMOD_PORT_IF_LR4) 292 #define TSCMOD_IF_KR (1 << TSCMOD_PORT_IF_KR) 293 #define TSCMOD_IF_KR2 (1 << TSCMOD_PORT_IF_KR2) 294 #define TSCMOD_IF_KR4 (1 << TSCMOD_PORT_IF_KR4) 295 #define TSCMOD_IF_CR (1 << TSCMOD_PORT_IF_CR) 296 #define TSCMOD_IF_CR2 (1 << TSCMOD_PORT_IF_CR2) 297 #define TSCMOD_IF_CR4 (1 << TSCMOD_PORT_IF_CR4) 298 #define TSCMOD_IF_XFI (1 << TSCMOD_PORT_IF_XFI) 299 #define TSCMOD_IF_SFI (1 << TSCMOD_PORT_IF_SFI) 300 #define TSCMOD_IF_XLAUI (1 << TSCMOD_PORT_IF_XLAUI) 301 #define TSCMOD_IF_XGMII (1 << TSCMOD_PORT_IF_XGMII) 302 #define TSCMOD_IF_ILKN (1 << TSCMOD_PORT_IF_ILKN) 303 #define TSCMOD_40G_10G_INTF(_if) ((_if) == TSCMOD_PORT_IF_KR4 || (_if) == TSCMOD_PORT_IF_XLAUI || \ 304 (_if) == TSCMOD_PORT_IF_CR4 || (_if) == TSCMOD_PORT_IF_SR || \ 305 (_if) == TSCMOD_PORT_IF_SR4 || \ 306 (_if) == TSCMOD_PORT_IF_LR4 || (_if) == TSCMOD_PORT_IF_LR || \ 307 (_if) == TSCMOD_PORT_IF_KR2 || (_if) == TSCMOD_PORT_IF_CR2 || \ 308 (_if) == TSCMOD_PORT_IF_KR || (_if) == TSCMOD_PORT_IF_CR || \ 309 (_if) == TSCMOD_PORT_IF_XFI || (_if) == TSCMOD_PORT_IF_SFI || \ 310 (_if) == TSCMOD_PORT_IF_XGMII) 311 312 #define TSCMOD_40G_10G_INTF_ALL (TSCMOD_IF_KR4 | TSCMOD_IF_XLAUI | TSCMOD_IF_CR4 | TSCMOD_IF_SR4 | \ 313 TSCMOD_IF_LR4 | TSCMOD_IF_LR | \ 314 TSCMOD_IF_KR2 | TSCMOD_IF_CR2 | \ 315 TSCMOD_IF_SR | TSCMOD_IF_KR | TSCMOD_IF_CR | TSCMOD_IF_XFI | TSCMOD_IF_SFI | \ 316 TSCMOD_IF_XGMII) 317 318 #define TSCMOD_UC_CTRL_XLAUI 0x3 319 #define TSCMOD_UC_CTRL_SR4 0x1 320 #define TSCMOD_UC_CTRL_SFP_DAC 0x2 321 #define TSCMOD_UC_CTRL_OPT_PF_TEMP_COMP 0x8 322 323 #define TSCMOD_AN_WAIT_INTERVAL 1000000 /* 1 second */ 324 325 #define TSCMOD_AN_WAIT_RESTART_TMR 4000000 326 #define TSCMOD_AN_WAIT_CL73_TMR 4000000 327 #define TSCMOD_AN_WAIT_HPBAM_TMR 6000000 328 #define TSCMOD_AN_WAIT_CL37_TMR 1000000 329 330 #define TSCMOD_AN_CL73_CL37_OFF 0x0 331 #define TSCMOD_AN_CL73_CL37_ON 0x1 332 #define TSCMOD_AN_WAIT_CL73 0x2 333 #define TSCMOD_AN_WAIT_CL37 0x3 334 #define TSCMOD_AN_CL73_CL37_DONE 0x4 335 336 #define TSCMOD_AN_MODE_CL37_TRIED 0x1 337 338 #define TSCMOD_SP_TIME(_pc) \ 339 (DEV_CTRL_PTR(_pc)->lkwa.start_time) 340 #define TSCMOD_SP_VALID(_pc) \ 341 (DEV_CTRL_PTR(_pc)->lkwa.state) 342 #define TSCMOD_SP_CNT(_pc) \ 343 (DEV_CTRL_PTR(_pc)->lkwa.cnt) 344 345 #define TSCMOD_SP_RECORD_TIME(_pc) \ 346 (DEV_CTRL_PTR(_pc)->lkwa.start_time) = sal_time_usecs() 347 #define TSCMOD_SP_CNT_INC(_pc) \ 348 (DEV_CTRL_PTR(_pc)->lkwa.cnt)++ 349 #define TSCMOD_SP_CNT_CLEAR(_pc) \ 350 (DEV_CTRL_PTR(_pc)->lkwa.cnt) = 0 351 #define TSCMOD_SP_VALID_SET(_pc) \ 352 (DEV_CTRL_PTR(_pc)->lkwa.state) = TRUE 353 #define TSCMOD_SP_VALID_RESET(_pc) \ 354 (DEV_CTRL_PTR(_pc)->lkwa.state) = FALSE 355 356 #define TSCMOD_AN_TIME(_pc) \ 357 (DEV_CTRL_PTR(_pc)->an.start_time) 358 #define TSCMOD_AN_STATE(_pc) \ 359 (DEV_CTRL_PTR(_pc)->an.state) 360 #define TSCMOD_AN_RECORD_TIME(_pc) \ 361 (DEV_CTRL_PTR(_pc)->an.start_time) = sal_time_usecs() 362 #define TSCMOD_AN_VALID_SET(_pc) \ 363 (DEV_CTRL_PTR(_pc)->an.state) = TRUE 364 #define TSCMOD_AN_VALID_RESET(_pc) \ 365 (DEV_CTRL_PTR(_pc)->an.state) = FALSE 366 #define TSCMOD_AN_CHECK_TIMEOUT(_pc) \ 367 ((uint32)SAL_USECS_SUB(sal_time_usecs(), TSCMOD_AN_TIME((_pc))) \ 368 >= TSCMOD_AN_WAIT_INTERVAL) 369 #define TSCMOD_AN_TICK_CNT(_pc) \ 370 (DEV_CTRL_PTR(_pc)->an.tick_cnt) 371 #define TSCMOD_AN_MODE(_pc) \ 372 (DEV_CTRL_PTR(_pc)->an.mode) 373 374 /* Indicate whether to power down TX on lane n */ 375 #define PWR_DOWN_TX0 0x1 376 #define PWR_DOWN_TX1 0x2 377 #define PWR_DOWN_TX2 0x4 378 #define PWR_DOWN_TX3 0x8 379 380 /* Indicate whether to power down RX on lane n */ 381 #define PWR_DOWN_RX0 0x100 382 #define PWR_DOWN_RX1 0x200 383 #define PWR_DOWN_RX2 0x400 384 #define PWR_DOWN_RX3 0x800 385 386 /* Indicate whether to power down TX on lane n */ 387 #define CHANGE_TX0_PWRED_STATE 0x10 388 #define CHANGE_TX1_PWRED_STATE 0x20 389 #define CHANGE_TX2_PWRED_STATE 0x40 390 #define CHANGE_TX3_PWRED_STATE 0x80 391 392 /* Indicate whether to power down RX on lane n */ 393 #define CHANGE_RX0_PWRED_STATE 0x1000 394 #define CHANGE_RX1_PWRED_STATE 0x2000 395 #define CHANGE_RX2_PWRED_STATE 0x4000 396 #define CHANGE_RX3_PWRED_STATE 0x8000 397 398 399 /* TX drive configuration */ 400 401 #define TSCMOD_NO_CFG_VALUE (-1) 402 #define TXDRV_PREEMPH(_tdrv) (((_tdrv).force << 15) | ((_tdrv).post << 10) | \ 403 ((_tdrv).main << 4) | ((_tdrv).pre)) 404 405 /* CL49 PRBS control */ 406 407 #define TSCMOD_PRBS_TYPE_STD 0 408 #define TSCMOD_PRBS_TYPE_CL49 1 409 #define TSCMOD_PRBS_CFG_POLY31 3 410 #define TSCMOD_PRBS_CL49_POLY31 (PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31TX_EN_MASK | \ 411 PCS_IEEE2BLK_PCS_TPCONTROL_PRBS31RX_EN_MASK) 412 #define TSCMOD_PRBS_CL49_POLY9 (PCS_IEEE2BLK_PCS_TPCONTROL_PRBS9TX_EN_MASK | \ 413 0x80) 414 415 /* typedefs */ 416 417 /* index to TX drive configuration table for each VCO setting. 418 */ 419 typedef enum txdrv_inxs { 420 TXDRV_6250_INX, /* 6.26G, 3.125G 1.25G */ 421 TXDRV_103125_INX, /* 10.3125G */ 422 TXDRV_109375_INX, /* 10.9375G */ 423 TXDRV_12500_INX, /* 12.5G */ 424 TXDRV_11500_INX, /* 11.5G, 6.25G 5.75G */ 425 TXDRV_XFI_INX, /* 10G XFI */ 426 TXDRV_XLAUI_INX, /* 40G XLAUI mode */ 427 TXDRV_SFI_INX, /* 10G SR fiber mode */ 428 TXDRV_SFIDAC_INX, /* 10G SFI DAC mode */ 429 TXDRV_SR4_INX, /* 40G SR4 */ 430 TXDRV_6GOS1_INX, /* BRCM 40G mode */ 431 TXDRV_6GOS2_INX, /* */ 432 TXDRV_6GOS2_CX4_INX, /* */ 433 TXDRV_AN_INX, /* a common entry for autoneg mode */ 434 TXDRV_DFT_INX, /* temp for any missing speed modes */ 435 TXDRV_ILKN, 436 TXDRV_LAST_INX /* always last */ 437 } TXDRV_INXS_t; 438 439 #define TXDRV_ENTRY_NUM (TXDRV_LAST_INX) 440 441 typedef struct 442 { 443 unsigned int force: 1; /* forced */ 444 unsigned int post : 5; /* TX post tap */ 445 unsigned int main : 6; /* TX main tap */ 446 unsigned int pre : 4; /* TX pre tap */ 447 unsigned int rsvd : 16; /* reserved */ 448 } TSCMOD_TX_TAP_t; 449 450 451 typedef struct { 452 union { 453 TSCMOD_TX_TAP_t tap; 454 uint16 preemph; 455 } u; 456 union { 457 TSCMOD_TX_TAP_t tap; 458 uint16 preemph; 459 } u_kx; 460 union { 461 TSCMOD_TX_TAP_t tap; 462 uint16 preemph; 463 } u_os; 464 union { 465 TSCMOD_TX_TAP_t tap; 466 uint16 preemph; 467 } u_br; 468 union { 469 TSCMOD_TX_TAP_t tap; 470 uint16 preemph; 471 } u_kr; 472 union { 473 TSCMOD_TX_TAP_t tap; 474 uint16 preemph; 475 } u_2p5; 476 477 uint8 post2; /* TX post2 coeff */ 478 uint8 idrive; /* TX idrive */ 479 uint8 ipredrive; /* TX pre-idrive */ 480 } TSCMOD_TX_DRIVE_t; 481 482 483 typedef enum tscmod_rx_los_states { 484 RXLOS_RESET, 485 RXLOS_LINK_WAIT_P1, 486 RXLOS_INITIAL_LINK_UP, 487 RXLOS_RESTART, 488 RXLOS_LINK_WAIT_P2, 489 RXLOS_LINK_UP 490 } TSCMOD_RX_LOS_STATES_t; 491 492 /* The structure is only for the use 493 * for RX LOS (Loss of Signal) workaround. 494 * The workaround is to handle the situations 495 * through s/w where no reliable LOS detect 496 * is available to WC 497 */ 498 typedef struct { 499 uint8 enable; 500 uint8 sys_link; 501 uint8 link_status; 502 uint8 count ; 503 uint8 rf_dis ; 504 uint32 start_time ; 505 uint32 count_time ; 506 TSCMOD_RX_LOS_STATES_t state; 507 } TSCMOD_SOFTWARE_RX_LOS_t; 508 509 typedef struct { 510 int preemph[MAX_NUM_LANES]; /* pre-emphasis */ 511 int idriver[MAX_NUM_LANES]; 512 int pdriver[MAX_NUM_LANES]; 513 int post2driver[MAX_NUM_LANES]; 514 int auto_medium; 515 int fiber_pref; 516 int medium; 517 int sgmii_mstr; 518 int pdetect10g; /* 10G paralell detect */ 519 int pdetect1000x; /* 1000X paralell detect */ 520 int cx42hg; 521 int rxlane_map[MAX_NUM_LANES/4]; 522 int txlane_map[MAX_NUM_LANES/4]; 523 int cl73an; 524 int cl37an; 525 int an_cl72; 526 int init_mode ; 527 int forced_init_cl72; 528 int sw_init_drive; 529 int lane_mode; 530 int pattern_data[PROG_DATA_NUM]; 531 int cx4_10g; 532 int lane0_rst; 533 int rxaui; 534 int dxgxs; 535 int custom; 536 uint32 line_intf; 537 int scrambler_en; 538 int custom1; 539 int txpol; 540 int rxpol; 541 int load_mthd; 542 int load_ucode_done; 543 int uc_cksum; 544 int uc_ver ; 545 int uc_crc ; 546 int firmware_mode ; 547 int hg_mode; /* choose HG speed mode */ 548 int refclk; 549 int pll_divider; 550 int init_speed ; 551 int oversample_mode; 552 TSCMOD_TX_DRIVE_t tx_drive[TXDRV_ENTRY_NUM]; 553 TSCMOD_SOFTWARE_RX_LOS_t sw_rx_los; 554 int diag_regs ; 555 int diag_port ; 556 int diag_verb ; 557 int linkup_bert ; 558 int fault_disable ; 559 int svk_id ; 560 uint32 los_usec ; 561 int an_ctl ; 562 int an_link_fail_nocl72_wait_timer ; 563 int pll_vco_step ; 564 int ability_mask ; 565 int ctrl_flag ; 566 int cidL ; 567 int cidH ; 568 int cidU ; 569 int cidV ; 570 mac_driver_t *macd; /* Attached MAC driver */ 571 int am_reserved ; 572 uint8 *scache_ptr ; 573 uint32 scache_ver ; 574 int scache_size ; 575 int pcs_mode ; 576 uint32 rxlos_link_wait_timer ; 577 uint32 rxlos_restart_timer ; 578 uint32 rxlos_first_linkup_time ; 579 } TSCMOD_DEV_CFG_t; 580 581 #define TSCMOD_LANE_NAME_LEN 30 582 583 typedef struct { 584 uint16 serdes_id0; 585 char name[TSCMOD_LANE_NAME_LEN]; 586 } TSCMOD_DEV_INFO_t; 587 588 typedef struct { 589 uint32 start_time; 590 uint32 state; 591 uint32 cnt; 592 } TSCMOD_LINK_WAR; 593 594 typedef struct { 595 uint32 start_time; 596 uint32 state; 597 uint8 tick_cnt ; 598 uint8 mode ; 599 } TSCMOD_AN_TIMER; 600 601 typedef struct { 602 int type; 603 int poly; 604 } TSCMOD_PRBS_CTRL; 605 606 typedef struct { 607 uint16 state; 608 uint16 mode; 609 uint16 enabled; 610 uint16 tick_cnt; 611 uint16 restart_cnt; 612 uint32 start_time; 613 } TSCMOD_FORCE_CL72_t; 614 615 typedef struct { 616 TSCMOD_LINK_WAR lkwa; 617 TSCMOD_AN_TIMER an; 618 /* TSCMOD_PRBS_CTRL prbs; */ 619 TSCMOD_FORCE_CL72_t cl72; 620 } TSCMOD_DEV_CTRL_t; 621 622 typedef struct { 623 TSCMOD_DEV_CFG_t cfg; 624 TSCMOD_DEV_INFO_t info; 625 TSCMOD_DEV_CTRL_t ctrl; 626 } TSCMOD_DEV_DESC_t; 627 628 #define DEV_CFG_PTR(_pc) (&(((TSCMOD_DEV_DESC_t *)((_pc) + 1))->cfg)) 629 #define DEV_INFO_PTR(_pc) (&(((TSCMOD_DEV_DESC_t *)((_pc) + 1))->info)) 630 #define DEV_CTRL_PTR(_pc) (&(((TSCMOD_DEV_DESC_t *)((_pc) + 1))->ctrl)) 631 632 /* force cl72 */ 633 #define FORCE_CL72_MODE(_pc) (DEV_CTRL_PTR(_pc)->cl72.mode) 634 #define FORCE_CL72_ENABLED(_pc) (DEV_CTRL_PTR(_pc)->cl72.enabled) 635 #define FORCE_CL72_STATE(_pc) (DEV_CTRL_PTR(_pc)->cl72.state) 636 #define FORCE_CL72_TICK_CNT(_pc) (DEV_CTRL_PTR(_pc)->cl72.tick_cnt) 637 #define FORCE_CL72_RESTART_CNT(_pc) (DEV_CTRL_PTR(_pc)->cl72.restart_cnt) 638 #define FORCE_CL72_START_TIME(_pc) (DEV_CTRL_PTR(_pc)->cl72.start_time) 639 640 #define TSCMOD_FORCE_CL72_IDLE 0 641 #define TSCMOD_FORCE_CL72_WAIT_TRAINING_LOCK 1 642 #define TSCMOD_FORCE_CL72_WAIT_TRAINING_DONE 2 643 #define TSCMOD_FORCE_CL72_TXP_ENABLED 3 644 #define TSCMOD_FORCE_CL72_DONE 4 645 #define TSCMOD_FORCE_CL72_RESTART 5 646 #define TSCMOD_FORCE_CL72_LINK_DOWN 6 647 #define TSCMOD_FORCE_CL72_CMD_DIS_IDLE 7 648 #define TSCMOD_FORCE_CL72_RESTART_ACTION 8 649 650 #define TSCMOD_FORCE_CL72_RESTART_TIME 1000000 651 #define TSCMOD_FORCE_CL72_RESTART_CNT 6 652 #define TSCMOD_FORCE_CL72_RESTART_TXIDLE_TIME 75000 653 #define TSCMOD_FORCE_CL72_RESTART_TXIDLE_CNT 1 654 655 #define TSCMOD_RXLOS_TIMEOUT2 2000000 656 #define TSCMOD_RXLOS_TIMEOUT1 1000000 657 #define TSCMOD_RXLOS_TIMEOUTp5 500000 658 #define TSCMOD_RXLOS_TIMEOUTp25 250000 659 #define TSCMOD_RXLOS_TIMEOUTp1 100000 660 #define TSCMOD_RXLOS_TIMEOUTp2 200000 661 #define TSCMOD_RXLOS_LINK_FLAP_WAR 0x2 662 #define TSCMOD_RXLOS_LINK_UP_FAST_WAR 0x4 663 #define TSCMOD_INIT_MODE_SKIP 0x1 664 665 typedef struct { 666 uint8 *pdata; 667 int *plen; 668 uint16 chip_rev; 669 } TSCMOD_UCODE_DESC; 670 671 /* external functions shared within WC driver files */ 672 /* extern int phy_wc40_config_init(phy_ctrl_t *pc); */ 673 674 #define DSC2B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK 0xfc00 675 #define DSC2B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT 10 676 #define DSC2B0_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_MASK 0x8000 677 #define DSC2B0_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_SHIFT 15 678 679 /* (*_offset_p) and _size will accumulate by the sizeof(_var) */ 680 #define TSCMOD_WB_ID_CMD(_ptr, _var, _t, _offset_p,_size_p) \ 681 do { \ 682 uint8 *_vptr_ ; \ 683 int _vsize_ ; \ 684 _vptr_ = (_ptr) + (*(_offset_p)) ; \ 685 _vsize_ = sizeof((_var)) ; \ 686 if((_t)==TSCMOD_WB_SC_UPDATE){ \ 687 sal_memcpy(_vptr_,(&(_var)),_vsize_) ; \ 688 } else if((_t)==TSCMOD_WB_SC_RETRIEVE) { \ 689 sal_memcpy((&(_var)),_vptr_,_vsize_); \ 690 } \ 691 (*(_size_p)) = (*(_size_p)) + _vsize_ ; \ 692 (*(_offset_p)) += _vsize_ ; \ 693 } while(0) 694 695 typedef enum tscmod_wb_handler_type { 696 TSCMOD_WB_SC_COUNT, 697 TSCMOD_WB_SC_RETRIEVE, 698 TSCMOD_WB_SC_UPDATE 699 } TSCMOD_WB_HANDLER_TYPE_t ; 700 701 typedef enum tscmod_wb_data_id { 702 TSCMOD_WB_SC_VER=0, 703 TSCMOD_WB_FW_MODE, 704 TSCMOD_WB_CTRL_TYPE, 705 TSCMOD_WB_RXLOS, 706 TSCMOD_WB_CL72_WAR, 707 TSCMOD_WB_INTF, 708 TSCMOD_WB_AN_MODE, 709 TSCMOD_WB_SC_LAST 710 } TSCMOD_WB_DATA_ID_t ; 711 712 #define TSCMOD_WB_SC_VER1 0x6401 713 #define TSCMOD_WB_SC_VER2 0x6402 714 715 716 #endif /* WL_TSCMOD_H__ */