tscmod.h (1071465B)
1 /*************************************************************************** 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Copyright (c) 1999-2012, Broadcom Corporation 8 * All Rights Reserved 9 * Confidential Property of Broadcom Corporation 10 * 11 * 12 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 13 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 14 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 15 * 16 * $brcm_Workfile: $ 17 * $brcm_Revision: $ 18 * $brcm_Date: $ 19 * 20 * Module Description: 21 * DO NOT EDIT THIS FILE DIRECTLY 22 * 23 * This module was generated magically with RDB from a source description 24 * file. You must edit the source file for changes to be made to this file. 25 * 26 * 27 * Date: Generated on Mon Apr 16 13:59:44 2012 28 * MD5 Checksum 669ce1e23392543807bc38a9d02ecf49 29 * 30 * Compiled with: RDB Utility 5.0 31 * RDB Parser 3.0 32 * rdb2macro.pm 4.0 33 * Perl Interpreter 5.008008 34 * Operating System linux 35 * 36 * Spec Versions: UCSS_X4 1 37 * aer 1 38 * an_x1_control 1 39 * an_x1_timers 1 40 * an_x4_abilities 1 41 * an_x4_hw_lp_pages 1 42 * an_x4_sw_management 1 43 * anapll 1 44 * anarx 1 45 * anatx 1 46 * cl49 1 47 * cl72 1 48 * cl72_shared 1 49 * cl73 1 50 * cl82 1 51 * cl82_am 1 52 * cl82_am_tsc_12 1 53 * cl82_shared 1 54 * digital 1 55 * digital5 1 56 * dsc_1 1 57 * dsc_2 1 58 * dsc_3 1 59 * dsc_4 1 60 * dsc_5 1 61 * ed6466_user 1 62 * generic 1 63 * gp2 1 64 * ieee0_cl22 1 65 * ieee1_cl22 1 66 * ieee_an0 1 67 * ieee_an3 1 68 * ieee_pcs1 1 69 * ieee_pcs2 1 70 * ieee_pcs3 1 71 * ieee_pma_pmd0 1 72 * ieee_pma_pmd10 1 73 * ieee_pma_pmd10_tsc_121 74 * ieee_pma_pmd9 1 75 * main0 1 76 * micro 1 77 * microtmp2 1 78 * patgen_0 1 79 * patgen_1 1 80 * rx_x1_control0 1 81 * rx_x1_control1 1 82 * rx_x2_control0 1 83 * rx_x2_status0 1 84 * rx_x4_control0 1 85 * rx_x4_control0_tsc_121 86 * rx_x4_status0 1 87 * rx_x4_status0_tsc_12 1 88 * rx_x4_status1 1 89 * test0 1 90 * test1 1 91 * testmux 1 92 * testshared0 1 93 * testshared1 1 94 * tx_x1_control0 1 95 * tx_x1_status0 1 96 * tx_x2_control0 1 97 * tx_x2_status0 1 98 * tx_x4_control0 1 99 * tx_x4_credit_gen0 1 100 * tx_x4_status0 1 101 * xgxsblk1 1 102 * xgxsblk10 1 103 * xgxsblk4 1 104 * 105 * RDB Files: /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/WC4_TSC_ALL.rdb 106 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee0_cl22Regs.rdb 107 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee1_cl22Regs.rdb 108 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/patgen_0_regs.rdb 109 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/patgen_1_regs.rdb 110 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee_cl45pma_pmd0Regs.rdb 111 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee_cl45pma_pmd9Regs.rdb 112 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee_cl45pma_pmd10Regs.rdb 113 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee_cl45pma_pmd10_tsc_12Regs.rdb 114 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee_cl45pcs1Regs.rdb 115 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee_cl45pcs2Regs.rdb 116 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee_cl45pcs3Regs.rdb 117 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee_cl45an0Regs.rdb 118 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 119 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ieee_cl45an3Regs.rdb 120 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 121 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/anapll_regs.rdb 122 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 123 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/testshared0_regs.rdb 124 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/testshared1_regs.rdb 125 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/testmux_regs.rdb 126 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/xgxsblock1_regs.rdb 127 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/xgxsblock4_regs.rdb 128 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 129 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/xgxsblock10_regs.rdb 130 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/an_x1_timers_regs.rdb 131 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/gp2_regs.rdb 132 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 133 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/cl72_shared_regs.rdb 134 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/cl82_shared_regs.rdb 135 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/cl82_am_regs.rdb 136 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/cl82_am_tsc_12_regs.rdb 137 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/main0_regs.rdb 138 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 139 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/rx_x1_control0_regs.rdb 140 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/rx_x1_control1_regs.rdb 141 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/tx_x1_control0_regs.rdb 142 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/tx_x1_status0_regs.rdb 143 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/an_x1_control_regs.rdb 144 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/cl82_user_regs.rdb 145 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/tx_x2_control0_regs.rdb 146 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/tx_x2_status0_regs.rdb 147 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/rx_x2_control0_regs.rdb 148 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/rx_x2_status0_regs.rdb 149 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/gen_per_lane_regs.rdb 150 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 151 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/anatx_regs.rdb 152 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 153 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/anarx_regs.rdb 154 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 155 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/test0_regs.rdb 156 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/test1_regs.rdb 157 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/tx_x4_credit_gen0_regs.rdb 158 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 159 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/tx_x4_control0_regs.rdb 160 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/tx_x4_status0_regs.rdb 161 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/rx_x4_control0_regs.rdb 162 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/rx_x4_status0_regs.rdb 163 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/rx_x4_status1_regs.rdb 164 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/rx_x4_control0_tsc_12_regs.rdb 165 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/rx_x4_status0_tsc_12_regs.rdb 166 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/an_x4_abilities_regs.rdb 167 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/an_x4_hw_lp_pages_regs.rdb 168 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/an_x4_sw_management_regs.rdb 169 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ucss_x4_regs.rdb 170 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 171 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/dsc_1_regs.rdb 172 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/dsc_2_regs.rdb 173 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/dsc_3_regs.rdb 174 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/dsc_4_regs.rdb 175 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/dsc_5_regs.rdb 176 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/digital_regs.rdb 177 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 178 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/digital5_regs.rdb 179 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 180 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/cl49_user_regs.rdb 181 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/cl72_user_regs.rdb 182 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/cl73_user_regs.rdb 183 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/ed6466_user_regs.rdb 184 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/microtmp2_regs.rdb 185 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 186 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/micro_regs.rdb 187 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/aer_regs.rdb 188 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/enum_inc.rdb 189 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/WC4_ieeeBlockCL22.rdb 190 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/WC4_ieeeBlockPMA_PMD.rdb 191 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/WC4_ieeeBlockPCS.rdb 192 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/WC4_userBlocks1.rdb 193 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/WC4_userBlocks2.rdb 194 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/WC4_userBlocks4.rdb 195 * /projects/trident2_scratch/mjang/td2_nq_regr/trident2/ip_cores/tsc/rtl/rdb/WC4_userBlocksX.rdb 196 * 197 * Revision History: 198 * 199 * $brcm_Log: $ 200 */ 201 202 #ifndef TSCMOD_H_TMP__ 203 #define TSCMOD_H_TMP__ 204 205 /** 206 * m = memory, c = core, r = register, f = field, d = data. 207 */ 208 #if !defined(GET_FIELD) && !defined(SET_FIELD) 209 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 210 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 211 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 212 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 213 214 #define GET_FIELD(m,c,r,f) \ 215 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 216 217 #define SET_FIELD(m,c,r,f,d) \ 218 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 219 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 220 ) 221 222 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 223 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 224 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 225 226 #endif /* GET & SET */ 227 228 /**************************************************************************** 229 * Core Enums. 230 */ 231 /**************************************************************************** 232 * Enums: UCSS_X4_cl36TxEEEStates_l 233 */ 234 #define UCSS_X4_cl36TxEEEStates_l_TX_REFRESH 8 235 #define UCSS_X4_cl36TxEEEStates_l_TX_QUIET 4 236 #define UCSS_X4_cl36TxEEEStates_l_TX_SLEEP 2 237 #define UCSS_X4_cl36TxEEEStates_l_TX_ACTIVE 1 238 239 /**************************************************************************** 240 * Enums: UCSS_X4_cl36TxEEEStates_c 241 */ 242 #define UCSS_X4_cl36TxEEEStates_c_TX_REFRESH 3 243 #define UCSS_X4_cl36TxEEEStates_c_TX_QUIET 2 244 #define UCSS_X4_cl36TxEEEStates_c_TX_SLEEP 1 245 #define UCSS_X4_cl36TxEEEStates_c_TX_ACTIVE 0 246 247 /**************************************************************************** 248 * Enums: UCSS_X4_cl49TxEEEStates_l 249 */ 250 #define UCSS_X4_cl49TxEEEStates_l_SCR_RESET_2 64 251 #define UCSS_X4_cl49TxEEEStates_l_SCR_RESET_1 32 252 #define UCSS_X4_cl49TxEEEStates_l_TX_WAKE 16 253 #define UCSS_X4_cl49TxEEEStates_l_TX_REFRESH 8 254 #define UCSS_X4_cl49TxEEEStates_l_TX_QUIET 4 255 #define UCSS_X4_cl49TxEEEStates_l_TX_SLEEP 2 256 #define UCSS_X4_cl49TxEEEStates_l_TX_ACTIVE 1 257 258 /**************************************************************************** 259 * Enums: UCSS_X4_cl49TxEEEStates_c 260 */ 261 #define UCSS_X4_cl49TxEEEStates_c_SCR_RESET_2 6 262 #define UCSS_X4_cl49TxEEEStates_c_SCR_RESET_1 5 263 #define UCSS_X4_cl49TxEEEStates_c_TX_WAKE 4 264 #define UCSS_X4_cl49TxEEEStates_c_TX_REFRESH 3 265 #define UCSS_X4_cl49TxEEEStates_c_TX_QUIET 2 266 #define UCSS_X4_cl49TxEEEStates_c_TX_SLEEP 1 267 #define UCSS_X4_cl49TxEEEStates_c_TX_ACTIVE 0 268 269 /**************************************************************************** 270 * Enums: UCSS_X4_cl36RxEEEStates_l 271 */ 272 #define UCSS_X4_cl36RxEEEStates_l_RX_LINK_FAIL 32 273 #define UCSS_X4_cl36RxEEEStates_l_RX_WTF 16 274 #define UCSS_X4_cl36RxEEEStates_l_RX_WAKE 8 275 #define UCSS_X4_cl36RxEEEStates_l_RX_QUIET 4 276 #define UCSS_X4_cl36RxEEEStates_l_RX_SLEEP 2 277 #define UCSS_X4_cl36RxEEEStates_l_RX_ACTIVE 1 278 279 /**************************************************************************** 280 * Enums: UCSS_X4_cl36RxEEEStates_c 281 */ 282 #define UCSS_X4_cl36RxEEEStates_c_RX_LINK_FAIL 5 283 #define UCSS_X4_cl36RxEEEStates_c_RX_WTF 4 284 #define UCSS_X4_cl36RxEEEStates_c_RX_WAKE 3 285 #define UCSS_X4_cl36RxEEEStates_c_RX_QUIET 2 286 #define UCSS_X4_cl36RxEEEStates_c_RX_SLEEP 1 287 #define UCSS_X4_cl36RxEEEStates_c_RX_ACTIVE 0 288 289 /**************************************************************************** 290 * Enums: UCSS_X4_cl49RxEEEStates_l 291 */ 292 #define UCSS_X4_cl49RxEEEStates_l_RX_LINK_FAIL 32 293 #define UCSS_X4_cl49RxEEEStates_l_RX_WTF 16 294 #define UCSS_X4_cl49RxEEEStates_l_RX_WAKE 8 295 #define UCSS_X4_cl49RxEEEStates_l_RX_QUIET 4 296 #define UCSS_X4_cl49RxEEEStates_l_RX_SLEEP 2 297 #define UCSS_X4_cl49RxEEEStates_l_RX_ACTIVE 1 298 299 /**************************************************************************** 300 * Enums: UCSS_X4_cl49RxEEEStates_c 301 */ 302 #define UCSS_X4_cl49RxEEEStates_c_RX_LINK_FAIL 5 303 #define UCSS_X4_cl49RxEEEStates_c_RX_WTF 4 304 #define UCSS_X4_cl49RxEEEStates_c_RX_WAKE 3 305 #define UCSS_X4_cl49RxEEEStates_c_RX_QUIET 2 306 #define UCSS_X4_cl49RxEEEStates_c_RX_SLEEP 1 307 #define UCSS_X4_cl49RxEEEStates_c_RX_ACTIVE 0 308 309 /**************************************************************************** 310 * Enums: UCSS_X4_cl48TxEEEStates_l 311 */ 312 #define UCSS_X4_cl48TxEEEStates_l_TX_REFRESH 8 313 #define UCSS_X4_cl48TxEEEStates_l_TX_QUIET 4 314 #define UCSS_X4_cl48TxEEEStates_l_TX_SLEEP 2 315 #define UCSS_X4_cl48TxEEEStates_l_TX_ACTIVE 1 316 317 /**************************************************************************** 318 * Enums: UCSS_X4_cl48TxEEEStates_c 319 */ 320 #define UCSS_X4_cl48TxEEEStates_c_TX_REFRESH 3 321 #define UCSS_X4_cl48TxEEEStates_c_TX_QUIET 2 322 #define UCSS_X4_cl48TxEEEStates_c_TX_SLEEP 1 323 #define UCSS_X4_cl48TxEEEStates_c_TX_ACTIVE 0 324 325 /**************************************************************************** 326 * Enums: UCSS_X4_cl48RxEEEStates_l 327 */ 328 #define UCSS_X4_cl48RxEEEStates_l_RX_LINK_FAIL 32 329 #define UCSS_X4_cl48RxEEEStates_l_RX_WAKE 16 330 #define UCSS_X4_cl48RxEEEStates_l_RX_QUIET 8 331 #define UCSS_X4_cl48RxEEEStates_l_RX_DEACT 4 332 #define UCSS_X4_cl48RxEEEStates_l_RX_SLEEP 2 333 #define UCSS_X4_cl48RxEEEStates_l_RX_ACTIVE 1 334 335 /**************************************************************************** 336 * Enums: UCSS_X4_cl48RxEEEStates_c 337 */ 338 #define UCSS_X4_cl48RxEEEStates_c_RX_LINK_FAIL 5 339 #define UCSS_X4_cl48RxEEEStates_c_RX_WAKE 4 340 #define UCSS_X4_cl48RxEEEStates_c_RX_QUIET 3 341 #define UCSS_X4_cl48RxEEEStates_c_RX_DEACT 2 342 #define UCSS_X4_cl48RxEEEStates_c_RX_SLEEP 1 343 #define UCSS_X4_cl48RxEEEStates_c_RX_ACTIVE 0 344 345 /**************************************************************************** 346 * Enums: UCSS_X4_IQP_Options 347 */ 348 #define UCSS_X4_IQP_Options_i50uA 0 349 #define UCSS_X4_IQP_Options_i100uA 1 350 #define UCSS_X4_IQP_Options_i150uA 2 351 #define UCSS_X4_IQP_Options_i200uA 3 352 #define UCSS_X4_IQP_Options_i250uA 4 353 #define UCSS_X4_IQP_Options_i300uA 5 354 #define UCSS_X4_IQP_Options_i350uA 6 355 #define UCSS_X4_IQP_Options_i400uA 7 356 #define UCSS_X4_IQP_Options_i450uA 8 357 #define UCSS_X4_IQP_Options_i500uA 9 358 #define UCSS_X4_IQP_Options_i550uA 10 359 #define UCSS_X4_IQP_Options_i600uA 11 360 #define UCSS_X4_IQP_Options_i650uA 12 361 #define UCSS_X4_IQP_Options_i700uA 13 362 #define UCSS_X4_IQP_Options_i750uA 14 363 #define UCSS_X4_IQP_Options_i800uA 15 364 365 /**************************************************************************** 366 * Enums: UCSS_X4_IDriver_Options 367 */ 368 #define UCSS_X4_IDriver_Options_v680mV 0 369 #define UCSS_X4_IDriver_Options_v730mV 1 370 #define UCSS_X4_IDriver_Options_v780mV 2 371 #define UCSS_X4_IDriver_Options_v830mV 3 372 #define UCSS_X4_IDriver_Options_v880mV 4 373 #define UCSS_X4_IDriver_Options_v930mV 5 374 #define UCSS_X4_IDriver_Options_v980mV 6 375 #define UCSS_X4_IDriver_Options_v1010mV 7 376 #define UCSS_X4_IDriver_Options_v1040mV 8 377 #define UCSS_X4_IDriver_Options_v1060mV 9 378 #define UCSS_X4_IDriver_Options_v1070mV 10 379 #define UCSS_X4_IDriver_Options_v1080mV 11 380 #define UCSS_X4_IDriver_Options_v1085mV 12 381 #define UCSS_X4_IDriver_Options_v1090mV 13 382 #define UCSS_X4_IDriver_Options_v1095mV 14 383 #define UCSS_X4_IDriver_Options_v1100mV 15 384 385 /**************************************************************************** 386 * Enums: UCSS_X4_operationModes 387 */ 388 #define UCSS_X4_operationModes_XGXS 0 389 #define UCSS_X4_operationModes_XGXG_nCC 1 390 #define UCSS_X4_operationModes_Indlane_OS8 4 391 #define UCSS_X4_operationModes_IndLane_OS5 5 392 #define UCSS_X4_operationModes_PCI 7 393 #define UCSS_X4_operationModes_XGXS_nLQ 8 394 #define UCSS_X4_operationModes_XGXS_nLQnCC 9 395 #define UCSS_X4_operationModes_PBypass 10 396 #define UCSS_X4_operationModes_PBypass_nDSK 11 397 #define UCSS_X4_operationModes_ComboCoreMode 12 398 #define UCSS_X4_operationModes_Clocks_off 15 399 400 /**************************************************************************** 401 * Enums: UCSS_X4_actualSpeeds 402 */ 403 #define UCSS_X4_actualSpeeds_dr_10M 0 404 #define UCSS_X4_actualSpeeds_dr_100M 1 405 #define UCSS_X4_actualSpeeds_dr_1G 2 406 #define UCSS_X4_actualSpeeds_dr_2p5G 3 407 #define UCSS_X4_actualSpeeds_dr_5G_X4 4 408 #define UCSS_X4_actualSpeeds_dr_6G_X4 5 409 #define UCSS_X4_actualSpeeds_dr_10G_HiG 6 410 #define UCSS_X4_actualSpeeds_dr_10G_CX4 7 411 #define UCSS_X4_actualSpeeds_dr_12G_HiG 8 412 #define UCSS_X4_actualSpeeds_dr_12p5G_X4 9 413 #define UCSS_X4_actualSpeeds_dr_13G_X4 10 414 #define UCSS_X4_actualSpeeds_dr_15G_X4 11 415 #define UCSS_X4_actualSpeeds_dr_16G_X4 12 416 #define UCSS_X4_actualSpeeds_dr_1G_KX 13 417 #define UCSS_X4_actualSpeeds_dr_10G_KX4 14 418 #define UCSS_X4_actualSpeeds_dr_10G_KR 15 419 #define UCSS_X4_actualSpeeds_dr_5G 16 420 #define UCSS_X4_actualSpeeds_dr_6p4G 17 421 #define UCSS_X4_actualSpeeds_dr_20G_X4 18 422 #define UCSS_X4_actualSpeeds_dr_21G_X4 19 423 #define UCSS_X4_actualSpeeds_dr_25G_X4 20 424 #define UCSS_X4_actualSpeeds_dr_10G_HiG_DXGXS 21 425 #define UCSS_X4_actualSpeeds_dr_10G_DXGXS 22 426 #define UCSS_X4_actualSpeeds_dr_10p5G_HiG_DXGXS 23 427 #define UCSS_X4_actualSpeeds_dr_10p5G_DXGXS 24 428 #define UCSS_X4_actualSpeeds_dr_12p773G_HiG_DXGXS 25 429 #define UCSS_X4_actualSpeeds_dr_12p773G_DXGXS 26 430 #define UCSS_X4_actualSpeeds_dr_10G_XFI 27 431 #define UCSS_X4_actualSpeeds_dr_40G 28 432 #define UCSS_X4_actualSpeeds_dr_20G_HiG_DXGXS 29 433 #define UCSS_X4_actualSpeeds_dr_20G_DXGXS 30 434 #define UCSS_X4_actualSpeeds_dr_10G_SFI 31 435 #define UCSS_X4_actualSpeeds_dr_31p5G 32 436 #define UCSS_X4_actualSpeeds_dr_32p7G 33 437 #define UCSS_X4_actualSpeeds_dr_20G_SCR 34 438 #define UCSS_X4_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 439 #define UCSS_X4_actualSpeeds_dr_10G_DXGXS_SCR 36 440 #define UCSS_X4_actualSpeeds_dr_12G_R2 37 441 #define UCSS_X4_actualSpeeds_dr_10G_X2 38 442 #define UCSS_X4_actualSpeeds_dr_40G_KR4 39 443 #define UCSS_X4_actualSpeeds_dr_40G_CR4 40 444 #define UCSS_X4_actualSpeeds_dr_100G_CR10 41 445 #define UCSS_X4_actualSpeeds_dr_15p75G_DXGXS 44 446 #define UCSS_X4_actualSpeeds_dr_20G_KR2 57 447 #define UCSS_X4_actualSpeeds_dr_20G_CR2 58 448 449 /**************************************************************************** 450 * Enums: UCSS_X4_actualSpeedsMisc1 451 */ 452 #define UCSS_X4_actualSpeedsMisc1_dr_2500BRCM_X1 16 453 #define UCSS_X4_actualSpeedsMisc1_dr_5000BRCM_X4 17 454 #define UCSS_X4_actualSpeedsMisc1_dr_6000BRCM_X4 18 455 #define UCSS_X4_actualSpeedsMisc1_dr_10GHiGig_X4 19 456 #define UCSS_X4_actualSpeedsMisc1_dr_10GBASE_CX4 20 457 #define UCSS_X4_actualSpeedsMisc1_dr_12GHiGig_X4 21 458 #define UCSS_X4_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 459 #define UCSS_X4_actualSpeedsMisc1_dr_13GHiGig_X4 23 460 #define UCSS_X4_actualSpeedsMisc1_dr_15GHiGig_X4 24 461 #define UCSS_X4_actualSpeedsMisc1_dr_16GHiGig_X4 25 462 #define UCSS_X4_actualSpeedsMisc1_dr_5000BRCM_X1 26 463 #define UCSS_X4_actualSpeedsMisc1_dr_6363BRCM_X1 27 464 #define UCSS_X4_actualSpeedsMisc1_dr_20GHiGig_X4 28 465 #define UCSS_X4_actualSpeedsMisc1_dr_21GHiGig_X4 29 466 #define UCSS_X4_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 467 #define UCSS_X4_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 468 469 /**************************************************************************** 470 * Enums: UCSS_X4_IndLaneModes 471 */ 472 #define UCSS_X4_IndLaneModes_SWSDR_div2 0 473 #define UCSS_X4_IndLaneModes_SWSDR_div1 1 474 #define UCSS_X4_IndLaneModes_DWSDR_div2 2 475 #define UCSS_X4_IndLaneModes_DWSDR_div1 3 476 477 /**************************************************************************** 478 * Enums: UCSS_X4_prbsSelect 479 */ 480 #define UCSS_X4_prbsSelect_prbs7 0 481 #define UCSS_X4_prbsSelect_prbs15 1 482 #define UCSS_X4_prbsSelect_prbs23 2 483 #define UCSS_X4_prbsSelect_prbs31 3 484 485 /**************************************************************************** 486 * Enums: UCSS_X4_vcoDivider 487 */ 488 #define UCSS_X4_vcoDivider_div32 0 489 #define UCSS_X4_vcoDivider_div36 1 490 #define UCSS_X4_vcoDivider_div40 2 491 #define UCSS_X4_vcoDivider_div42 3 492 #define UCSS_X4_vcoDivider_div48 4 493 #define UCSS_X4_vcoDivider_div50 5 494 #define UCSS_X4_vcoDivider_div52 6 495 #define UCSS_X4_vcoDivider_div54 7 496 #define UCSS_X4_vcoDivider_div60 8 497 #define UCSS_X4_vcoDivider_div64 9 498 #define UCSS_X4_vcoDivider_div66 10 499 #define UCSS_X4_vcoDivider_div68 11 500 #define UCSS_X4_vcoDivider_div70 12 501 #define UCSS_X4_vcoDivider_div80 13 502 #define UCSS_X4_vcoDivider_div92 14 503 #define UCSS_X4_vcoDivider_div100 15 504 505 /**************************************************************************** 506 * Enums: UCSS_X4_refClkSelect 507 */ 508 #define UCSS_X4_refClkSelect_clk_25MHz 0 509 #define UCSS_X4_refClkSelect_clk_100MHz 1 510 #define UCSS_X4_refClkSelect_clk_125MHz 2 511 #define UCSS_X4_refClkSelect_clk_156p25MHz 3 512 #define UCSS_X4_refClkSelect_clk_187p5MHz 4 513 #define UCSS_X4_refClkSelect_clk_161p25Mhz 5 514 #define UCSS_X4_refClkSelect_clk_50Mhz 6 515 #define UCSS_X4_refClkSelect_clk_106p25Mhz 7 516 517 /**************************************************************************** 518 * Enums: UCSS_X4_aerMMDdevTypeSelect 519 */ 520 #define UCSS_X4_aerMMDdevTypeSelect_combo_core 0 521 #define UCSS_X4_aerMMDdevTypeSelect_PMA_PMD 1 522 #define UCSS_X4_aerMMDdevTypeSelect_PCS 3 523 #define UCSS_X4_aerMMDdevTypeSelect_PHY 4 524 #define UCSS_X4_aerMMDdevTypeSelect_DTE 5 525 #define UCSS_X4_aerMMDdevTypeSelect_CL73_AN 7 526 527 /**************************************************************************** 528 * Enums: UCSS_X4_aerMMDportSelect 529 */ 530 #define UCSS_X4_aerMMDportSelect_ln0 0 531 #define UCSS_X4_aerMMDportSelect_ln1 1 532 #define UCSS_X4_aerMMDportSelect_ln2 2 533 #define UCSS_X4_aerMMDportSelect_ln3 3 534 #define UCSS_X4_aerMMDportSelect_BCST_ln0_1_2_3 511 535 #define UCSS_X4_aerMMDportSelect_BCST_ln0_1 512 536 #define UCSS_X4_aerMMDportSelect_BCST_ln2_3 513 537 538 /**************************************************************************** 539 * Enums: UCSS_X4_firmwareModeSelect 540 */ 541 #define UCSS_X4_firmwareModeSelect_DEFAULT 0 542 #define UCSS_X4_firmwareModeSelect_SFP_OPT_LR 1 543 #define UCSS_X4_firmwareModeSelect_SFP_DAC 2 544 #define UCSS_X4_firmwareModeSelect_XLAUI 3 545 #define UCSS_X4_firmwareModeSelect_LONG_CH_6G 4 546 547 /**************************************************************************** 548 * Enums: UCSS_X4_tempIdxSelect 549 */ 550 #define UCSS_X4_tempIdxSelect_LTE__22p9C 15 551 #define UCSS_X4_tempIdxSelect_LTE__12p6C 14 552 #define UCSS_X4_tempIdxSelect_LTE__3p0C 13 553 #define UCSS_X4_tempIdxSelect_LTE_6p7C 12 554 #define UCSS_X4_tempIdxSelect_LTE_16p4C 11 555 #define UCSS_X4_tempIdxSelect_LTE_26p6C 10 556 #define UCSS_X4_tempIdxSelect_LTE_36p3C 9 557 #define UCSS_X4_tempIdxSelect_LTE_46p0C 8 558 #define UCSS_X4_tempIdxSelect_LTE_56p2C 7 559 #define UCSS_X4_tempIdxSelect_LTE_65p9C 6 560 #define UCSS_X4_tempIdxSelect_LTE_75p6C 5 561 #define UCSS_X4_tempIdxSelect_LTE_85p3C 4 562 #define UCSS_X4_tempIdxSelect_LTE_95p5C 3 563 #define UCSS_X4_tempIdxSelect_LTE_105p2C 2 564 #define UCSS_X4_tempIdxSelect_LTE_114p9C 1 565 #define UCSS_X4_tempIdxSelect_LTE_125p1C 0 566 567 /**************************************************************************** 568 * Enums: aer_cl36TxEEEStates_l 569 */ 570 #define aer_cl36TxEEEStates_l_TX_REFRESH 8 571 #define aer_cl36TxEEEStates_l_TX_QUIET 4 572 #define aer_cl36TxEEEStates_l_TX_SLEEP 2 573 #define aer_cl36TxEEEStates_l_TX_ACTIVE 1 574 575 /**************************************************************************** 576 * Enums: aer_cl36TxEEEStates_c 577 */ 578 #define aer_cl36TxEEEStates_c_TX_REFRESH 3 579 #define aer_cl36TxEEEStates_c_TX_QUIET 2 580 #define aer_cl36TxEEEStates_c_TX_SLEEP 1 581 #define aer_cl36TxEEEStates_c_TX_ACTIVE 0 582 583 /**************************************************************************** 584 * Enums: aer_cl49TxEEEStates_l 585 */ 586 #define aer_cl49TxEEEStates_l_SCR_RESET_2 64 587 #define aer_cl49TxEEEStates_l_SCR_RESET_1 32 588 #define aer_cl49TxEEEStates_l_TX_WAKE 16 589 #define aer_cl49TxEEEStates_l_TX_REFRESH 8 590 #define aer_cl49TxEEEStates_l_TX_QUIET 4 591 #define aer_cl49TxEEEStates_l_TX_SLEEP 2 592 #define aer_cl49TxEEEStates_l_TX_ACTIVE 1 593 594 /**************************************************************************** 595 * Enums: aer_cl49TxEEEStates_c 596 */ 597 #define aer_cl49TxEEEStates_c_SCR_RESET_2 6 598 #define aer_cl49TxEEEStates_c_SCR_RESET_1 5 599 #define aer_cl49TxEEEStates_c_TX_WAKE 4 600 #define aer_cl49TxEEEStates_c_TX_REFRESH 3 601 #define aer_cl49TxEEEStates_c_TX_QUIET 2 602 #define aer_cl49TxEEEStates_c_TX_SLEEP 1 603 #define aer_cl49TxEEEStates_c_TX_ACTIVE 0 604 605 /**************************************************************************** 606 * Enums: aer_cl36RxEEEStates_l 607 */ 608 #define aer_cl36RxEEEStates_l_RX_LINK_FAIL 32 609 #define aer_cl36RxEEEStates_l_RX_WTF 16 610 #define aer_cl36RxEEEStates_l_RX_WAKE 8 611 #define aer_cl36RxEEEStates_l_RX_QUIET 4 612 #define aer_cl36RxEEEStates_l_RX_SLEEP 2 613 #define aer_cl36RxEEEStates_l_RX_ACTIVE 1 614 615 /**************************************************************************** 616 * Enums: aer_cl36RxEEEStates_c 617 */ 618 #define aer_cl36RxEEEStates_c_RX_LINK_FAIL 5 619 #define aer_cl36RxEEEStates_c_RX_WTF 4 620 #define aer_cl36RxEEEStates_c_RX_WAKE 3 621 #define aer_cl36RxEEEStates_c_RX_QUIET 2 622 #define aer_cl36RxEEEStates_c_RX_SLEEP 1 623 #define aer_cl36RxEEEStates_c_RX_ACTIVE 0 624 625 /**************************************************************************** 626 * Enums: aer_cl49RxEEEStates_l 627 */ 628 #define aer_cl49RxEEEStates_l_RX_LINK_FAIL 32 629 #define aer_cl49RxEEEStates_l_RX_WTF 16 630 #define aer_cl49RxEEEStates_l_RX_WAKE 8 631 #define aer_cl49RxEEEStates_l_RX_QUIET 4 632 #define aer_cl49RxEEEStates_l_RX_SLEEP 2 633 #define aer_cl49RxEEEStates_l_RX_ACTIVE 1 634 635 /**************************************************************************** 636 * Enums: aer_cl49RxEEEStates_c 637 */ 638 #define aer_cl49RxEEEStates_c_RX_LINK_FAIL 5 639 #define aer_cl49RxEEEStates_c_RX_WTF 4 640 #define aer_cl49RxEEEStates_c_RX_WAKE 3 641 #define aer_cl49RxEEEStates_c_RX_QUIET 2 642 #define aer_cl49RxEEEStates_c_RX_SLEEP 1 643 #define aer_cl49RxEEEStates_c_RX_ACTIVE 0 644 645 /**************************************************************************** 646 * Enums: aer_cl48TxEEEStates_l 647 */ 648 #define aer_cl48TxEEEStates_l_TX_REFRESH 8 649 #define aer_cl48TxEEEStates_l_TX_QUIET 4 650 #define aer_cl48TxEEEStates_l_TX_SLEEP 2 651 #define aer_cl48TxEEEStates_l_TX_ACTIVE 1 652 653 /**************************************************************************** 654 * Enums: aer_cl48TxEEEStates_c 655 */ 656 #define aer_cl48TxEEEStates_c_TX_REFRESH 3 657 #define aer_cl48TxEEEStates_c_TX_QUIET 2 658 #define aer_cl48TxEEEStates_c_TX_SLEEP 1 659 #define aer_cl48TxEEEStates_c_TX_ACTIVE 0 660 661 /**************************************************************************** 662 * Enums: aer_cl48RxEEEStates_l 663 */ 664 #define aer_cl48RxEEEStates_l_RX_LINK_FAIL 32 665 #define aer_cl48RxEEEStates_l_RX_WAKE 16 666 #define aer_cl48RxEEEStates_l_RX_QUIET 8 667 #define aer_cl48RxEEEStates_l_RX_DEACT 4 668 #define aer_cl48RxEEEStates_l_RX_SLEEP 2 669 #define aer_cl48RxEEEStates_l_RX_ACTIVE 1 670 671 /**************************************************************************** 672 * Enums: aer_cl48RxEEEStates_c 673 */ 674 #define aer_cl48RxEEEStates_c_RX_LINK_FAIL 5 675 #define aer_cl48RxEEEStates_c_RX_WAKE 4 676 #define aer_cl48RxEEEStates_c_RX_QUIET 3 677 #define aer_cl48RxEEEStates_c_RX_DEACT 2 678 #define aer_cl48RxEEEStates_c_RX_SLEEP 1 679 #define aer_cl48RxEEEStates_c_RX_ACTIVE 0 680 681 /**************************************************************************** 682 * Enums: aer_IQP_Options 683 */ 684 #define aer_IQP_Options_i50uA 0 685 #define aer_IQP_Options_i100uA 1 686 #define aer_IQP_Options_i150uA 2 687 #define aer_IQP_Options_i200uA 3 688 #define aer_IQP_Options_i250uA 4 689 #define aer_IQP_Options_i300uA 5 690 #define aer_IQP_Options_i350uA 6 691 #define aer_IQP_Options_i400uA 7 692 #define aer_IQP_Options_i450uA 8 693 #define aer_IQP_Options_i500uA 9 694 #define aer_IQP_Options_i550uA 10 695 #define aer_IQP_Options_i600uA 11 696 #define aer_IQP_Options_i650uA 12 697 #define aer_IQP_Options_i700uA 13 698 #define aer_IQP_Options_i750uA 14 699 #define aer_IQP_Options_i800uA 15 700 701 /**************************************************************************** 702 * Enums: aer_IDriver_Options 703 */ 704 #define aer_IDriver_Options_v680mV 0 705 #define aer_IDriver_Options_v730mV 1 706 #define aer_IDriver_Options_v780mV 2 707 #define aer_IDriver_Options_v830mV 3 708 #define aer_IDriver_Options_v880mV 4 709 #define aer_IDriver_Options_v930mV 5 710 #define aer_IDriver_Options_v980mV 6 711 #define aer_IDriver_Options_v1010mV 7 712 #define aer_IDriver_Options_v1040mV 8 713 #define aer_IDriver_Options_v1060mV 9 714 #define aer_IDriver_Options_v1070mV 10 715 #define aer_IDriver_Options_v1080mV 11 716 #define aer_IDriver_Options_v1085mV 12 717 #define aer_IDriver_Options_v1090mV 13 718 #define aer_IDriver_Options_v1095mV 14 719 #define aer_IDriver_Options_v1100mV 15 720 721 /**************************************************************************** 722 * Enums: aer_operationModes 723 */ 724 #define aer_operationModes_XGXS 0 725 #define aer_operationModes_XGXG_nCC 1 726 #define aer_operationModes_Indlane_OS8 4 727 #define aer_operationModes_IndLane_OS5 5 728 #define aer_operationModes_PCI 7 729 #define aer_operationModes_XGXS_nLQ 8 730 #define aer_operationModes_XGXS_nLQnCC 9 731 #define aer_operationModes_PBypass 10 732 #define aer_operationModes_PBypass_nDSK 11 733 #define aer_operationModes_ComboCoreMode 12 734 #define aer_operationModes_Clocks_off 15 735 736 /**************************************************************************** 737 * Enums: aer_actualSpeeds 738 */ 739 #define aer_actualSpeeds_dr_10M 0 740 #define aer_actualSpeeds_dr_100M 1 741 #define aer_actualSpeeds_dr_1G 2 742 #define aer_actualSpeeds_dr_2p5G 3 743 #define aer_actualSpeeds_dr_5G_X4 4 744 #define aer_actualSpeeds_dr_6G_X4 5 745 #define aer_actualSpeeds_dr_10G_HiG 6 746 #define aer_actualSpeeds_dr_10G_CX4 7 747 #define aer_actualSpeeds_dr_12G_HiG 8 748 #define aer_actualSpeeds_dr_12p5G_X4 9 749 #define aer_actualSpeeds_dr_13G_X4 10 750 #define aer_actualSpeeds_dr_15G_X4 11 751 #define aer_actualSpeeds_dr_16G_X4 12 752 #define aer_actualSpeeds_dr_1G_KX 13 753 #define aer_actualSpeeds_dr_10G_KX4 14 754 #define aer_actualSpeeds_dr_10G_KR 15 755 #define aer_actualSpeeds_dr_5G 16 756 #define aer_actualSpeeds_dr_6p4G 17 757 #define aer_actualSpeeds_dr_20G_X4 18 758 #define aer_actualSpeeds_dr_21G_X4 19 759 #define aer_actualSpeeds_dr_25G_X4 20 760 #define aer_actualSpeeds_dr_10G_HiG_DXGXS 21 761 #define aer_actualSpeeds_dr_10G_DXGXS 22 762 #define aer_actualSpeeds_dr_10p5G_HiG_DXGXS 23 763 #define aer_actualSpeeds_dr_10p5G_DXGXS 24 764 #define aer_actualSpeeds_dr_12p773G_HiG_DXGXS 25 765 #define aer_actualSpeeds_dr_12p773G_DXGXS 26 766 #define aer_actualSpeeds_dr_10G_XFI 27 767 #define aer_actualSpeeds_dr_40G 28 768 #define aer_actualSpeeds_dr_20G_HiG_DXGXS 29 769 #define aer_actualSpeeds_dr_20G_DXGXS 30 770 #define aer_actualSpeeds_dr_10G_SFI 31 771 #define aer_actualSpeeds_dr_31p5G 32 772 #define aer_actualSpeeds_dr_32p7G 33 773 #define aer_actualSpeeds_dr_20G_SCR 34 774 #define aer_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 775 #define aer_actualSpeeds_dr_10G_DXGXS_SCR 36 776 #define aer_actualSpeeds_dr_12G_R2 37 777 #define aer_actualSpeeds_dr_10G_X2 38 778 #define aer_actualSpeeds_dr_40G_KR4 39 779 #define aer_actualSpeeds_dr_40G_CR4 40 780 #define aer_actualSpeeds_dr_100G_CR10 41 781 #define aer_actualSpeeds_dr_15p75G_DXGXS 44 782 #define aer_actualSpeeds_dr_20G_KR2 57 783 #define aer_actualSpeeds_dr_20G_CR2 58 784 785 /**************************************************************************** 786 * Enums: aer_actualSpeedsMisc1 787 */ 788 #define aer_actualSpeedsMisc1_dr_2500BRCM_X1 16 789 #define aer_actualSpeedsMisc1_dr_5000BRCM_X4 17 790 #define aer_actualSpeedsMisc1_dr_6000BRCM_X4 18 791 #define aer_actualSpeedsMisc1_dr_10GHiGig_X4 19 792 #define aer_actualSpeedsMisc1_dr_10GBASE_CX4 20 793 #define aer_actualSpeedsMisc1_dr_12GHiGig_X4 21 794 #define aer_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 795 #define aer_actualSpeedsMisc1_dr_13GHiGig_X4 23 796 #define aer_actualSpeedsMisc1_dr_15GHiGig_X4 24 797 #define aer_actualSpeedsMisc1_dr_16GHiGig_X4 25 798 #define aer_actualSpeedsMisc1_dr_5000BRCM_X1 26 799 #define aer_actualSpeedsMisc1_dr_6363BRCM_X1 27 800 #define aer_actualSpeedsMisc1_dr_20GHiGig_X4 28 801 #define aer_actualSpeedsMisc1_dr_21GHiGig_X4 29 802 #define aer_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 803 #define aer_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 804 805 /**************************************************************************** 806 * Enums: aer_IndLaneModes 807 */ 808 #define aer_IndLaneModes_SWSDR_div2 0 809 #define aer_IndLaneModes_SWSDR_div1 1 810 #define aer_IndLaneModes_DWSDR_div2 2 811 #define aer_IndLaneModes_DWSDR_div1 3 812 813 /**************************************************************************** 814 * Enums: aer_prbsSelect 815 */ 816 #define aer_prbsSelect_prbs7 0 817 #define aer_prbsSelect_prbs15 1 818 #define aer_prbsSelect_prbs23 2 819 #define aer_prbsSelect_prbs31 3 820 821 /**************************************************************************** 822 * Enums: aer_vcoDivider 823 */ 824 #define aer_vcoDivider_div32 0 825 #define aer_vcoDivider_div36 1 826 #define aer_vcoDivider_div40 2 827 #define aer_vcoDivider_div42 3 828 #define aer_vcoDivider_div48 4 829 #define aer_vcoDivider_div50 5 830 #define aer_vcoDivider_div52 6 831 #define aer_vcoDivider_div54 7 832 #define aer_vcoDivider_div60 8 833 #define aer_vcoDivider_div64 9 834 #define aer_vcoDivider_div66 10 835 #define aer_vcoDivider_div68 11 836 #define aer_vcoDivider_div70 12 837 #define aer_vcoDivider_div80 13 838 #define aer_vcoDivider_div92 14 839 #define aer_vcoDivider_div100 15 840 841 /**************************************************************************** 842 * Enums: aer_refClkSelect 843 */ 844 #define aer_refClkSelect_clk_25MHz 0 845 #define aer_refClkSelect_clk_100MHz 1 846 #define aer_refClkSelect_clk_125MHz 2 847 #define aer_refClkSelect_clk_156p25MHz 3 848 #define aer_refClkSelect_clk_187p5MHz 4 849 #define aer_refClkSelect_clk_161p25Mhz 5 850 #define aer_refClkSelect_clk_50Mhz 6 851 #define aer_refClkSelect_clk_106p25Mhz 7 852 853 /**************************************************************************** 854 * Enums: aer_aerMMDdevTypeSelect 855 */ 856 #define aer_aerMMDdevTypeSelect_combo_core 0 857 #define aer_aerMMDdevTypeSelect_PMA_PMD 1 858 #define aer_aerMMDdevTypeSelect_PCS 3 859 #define aer_aerMMDdevTypeSelect_PHY 4 860 #define aer_aerMMDdevTypeSelect_DTE 5 861 #define aer_aerMMDdevTypeSelect_CL73_AN 7 862 863 /**************************************************************************** 864 * Enums: aer_aerMMDportSelect 865 */ 866 #define aer_aerMMDportSelect_ln0 0 867 #define aer_aerMMDportSelect_ln1 1 868 #define aer_aerMMDportSelect_ln2 2 869 #define aer_aerMMDportSelect_ln3 3 870 #define aer_aerMMDportSelect_BCST_ln0_1_2_3 511 871 #define aer_aerMMDportSelect_BCST_ln0_1 512 872 #define aer_aerMMDportSelect_BCST_ln2_3 513 873 874 /**************************************************************************** 875 * Enums: aer_firmwareModeSelect 876 */ 877 #define aer_firmwareModeSelect_DEFAULT 0 878 #define aer_firmwareModeSelect_SFP_OPT_LR 1 879 #define aer_firmwareModeSelect_SFP_DAC 2 880 #define aer_firmwareModeSelect_XLAUI 3 881 #define aer_firmwareModeSelect_LONG_CH_6G 4 882 883 /**************************************************************************** 884 * Enums: aer_tempIdxSelect 885 */ 886 #define aer_tempIdxSelect_LTE__22p9C 15 887 #define aer_tempIdxSelect_LTE__12p6C 14 888 #define aer_tempIdxSelect_LTE__3p0C 13 889 #define aer_tempIdxSelect_LTE_6p7C 12 890 #define aer_tempIdxSelect_LTE_16p4C 11 891 #define aer_tempIdxSelect_LTE_26p6C 10 892 #define aer_tempIdxSelect_LTE_36p3C 9 893 #define aer_tempIdxSelect_LTE_46p0C 8 894 #define aer_tempIdxSelect_LTE_56p2C 7 895 #define aer_tempIdxSelect_LTE_65p9C 6 896 #define aer_tempIdxSelect_LTE_75p6C 5 897 #define aer_tempIdxSelect_LTE_85p3C 4 898 #define aer_tempIdxSelect_LTE_95p5C 3 899 #define aer_tempIdxSelect_LTE_105p2C 2 900 #define aer_tempIdxSelect_LTE_114p9C 1 901 #define aer_tempIdxSelect_LTE_125p1C 0 902 903 /**************************************************************************** 904 * Enums: an_x4_sw_management_tla_ln_seq_status 905 */ 906 #define an_x4_sw_management_tla_ln_seq_status_INIT 1 907 #define an_x4_sw_management_tla_ln_seq_status_RESTART_AN 2 908 #define an_x4_sw_management_tla_ln_seq_status_WAIT4RES 4 909 #define an_x4_sw_management_tla_ln_seq_status_RESET_PIPELINE 8 910 #define an_x4_sw_management_tla_ln_seq_status_CONFIG_PIPELINE 16 911 #define an_x4_sw_management_tla_ln_seq_status_IGNORE_LINK 32 912 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD_CHECK 64 913 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD 128 914 #define an_x4_sw_management_tla_ln_seq_status_AN_DEAD 256 915 #define an_x4_sw_management_tla_ln_seq_status_PLL_RESET 512 916 #define an_x4_sw_management_tla_ln_seq_status_SET_PD_HCD 1024 917 918 /**************************************************************************** 919 * Enums: anapll_cl36TxEEEStates_l 920 */ 921 #define anapll_cl36TxEEEStates_l_TX_REFRESH 8 922 #define anapll_cl36TxEEEStates_l_TX_QUIET 4 923 #define anapll_cl36TxEEEStates_l_TX_SLEEP 2 924 #define anapll_cl36TxEEEStates_l_TX_ACTIVE 1 925 926 /**************************************************************************** 927 * Enums: anapll_cl36TxEEEStates_c 928 */ 929 #define anapll_cl36TxEEEStates_c_TX_REFRESH 3 930 #define anapll_cl36TxEEEStates_c_TX_QUIET 2 931 #define anapll_cl36TxEEEStates_c_TX_SLEEP 1 932 #define anapll_cl36TxEEEStates_c_TX_ACTIVE 0 933 934 /**************************************************************************** 935 * Enums: anapll_cl49TxEEEStates_l 936 */ 937 #define anapll_cl49TxEEEStates_l_SCR_RESET_2 64 938 #define anapll_cl49TxEEEStates_l_SCR_RESET_1 32 939 #define anapll_cl49TxEEEStates_l_TX_WAKE 16 940 #define anapll_cl49TxEEEStates_l_TX_REFRESH 8 941 #define anapll_cl49TxEEEStates_l_TX_QUIET 4 942 #define anapll_cl49TxEEEStates_l_TX_SLEEP 2 943 #define anapll_cl49TxEEEStates_l_TX_ACTIVE 1 944 945 /**************************************************************************** 946 * Enums: anapll_cl49TxEEEStates_c 947 */ 948 #define anapll_cl49TxEEEStates_c_SCR_RESET_2 6 949 #define anapll_cl49TxEEEStates_c_SCR_RESET_1 5 950 #define anapll_cl49TxEEEStates_c_TX_WAKE 4 951 #define anapll_cl49TxEEEStates_c_TX_REFRESH 3 952 #define anapll_cl49TxEEEStates_c_TX_QUIET 2 953 #define anapll_cl49TxEEEStates_c_TX_SLEEP 1 954 #define anapll_cl49TxEEEStates_c_TX_ACTIVE 0 955 956 /**************************************************************************** 957 * Enums: anapll_cl36RxEEEStates_l 958 */ 959 #define anapll_cl36RxEEEStates_l_RX_LINK_FAIL 32 960 #define anapll_cl36RxEEEStates_l_RX_WTF 16 961 #define anapll_cl36RxEEEStates_l_RX_WAKE 8 962 #define anapll_cl36RxEEEStates_l_RX_QUIET 4 963 #define anapll_cl36RxEEEStates_l_RX_SLEEP 2 964 #define anapll_cl36RxEEEStates_l_RX_ACTIVE 1 965 966 /**************************************************************************** 967 * Enums: anapll_cl36RxEEEStates_c 968 */ 969 #define anapll_cl36RxEEEStates_c_RX_LINK_FAIL 5 970 #define anapll_cl36RxEEEStates_c_RX_WTF 4 971 #define anapll_cl36RxEEEStates_c_RX_WAKE 3 972 #define anapll_cl36RxEEEStates_c_RX_QUIET 2 973 #define anapll_cl36RxEEEStates_c_RX_SLEEP 1 974 #define anapll_cl36RxEEEStates_c_RX_ACTIVE 0 975 976 /**************************************************************************** 977 * Enums: anapll_cl49RxEEEStates_l 978 */ 979 #define anapll_cl49RxEEEStates_l_RX_LINK_FAIL 32 980 #define anapll_cl49RxEEEStates_l_RX_WTF 16 981 #define anapll_cl49RxEEEStates_l_RX_WAKE 8 982 #define anapll_cl49RxEEEStates_l_RX_QUIET 4 983 #define anapll_cl49RxEEEStates_l_RX_SLEEP 2 984 #define anapll_cl49RxEEEStates_l_RX_ACTIVE 1 985 986 /**************************************************************************** 987 * Enums: anapll_cl49RxEEEStates_c 988 */ 989 #define anapll_cl49RxEEEStates_c_RX_LINK_FAIL 5 990 #define anapll_cl49RxEEEStates_c_RX_WTF 4 991 #define anapll_cl49RxEEEStates_c_RX_WAKE 3 992 #define anapll_cl49RxEEEStates_c_RX_QUIET 2 993 #define anapll_cl49RxEEEStates_c_RX_SLEEP 1 994 #define anapll_cl49RxEEEStates_c_RX_ACTIVE 0 995 996 /**************************************************************************** 997 * Enums: anapll_cl48TxEEEStates_l 998 */ 999 #define anapll_cl48TxEEEStates_l_TX_REFRESH 8 1000 #define anapll_cl48TxEEEStates_l_TX_QUIET 4 1001 #define anapll_cl48TxEEEStates_l_TX_SLEEP 2 1002 #define anapll_cl48TxEEEStates_l_TX_ACTIVE 1 1003 1004 /**************************************************************************** 1005 * Enums: anapll_cl48TxEEEStates_c 1006 */ 1007 #define anapll_cl48TxEEEStates_c_TX_REFRESH 3 1008 #define anapll_cl48TxEEEStates_c_TX_QUIET 2 1009 #define anapll_cl48TxEEEStates_c_TX_SLEEP 1 1010 #define anapll_cl48TxEEEStates_c_TX_ACTIVE 0 1011 1012 /**************************************************************************** 1013 * Enums: anapll_cl48RxEEEStates_l 1014 */ 1015 #define anapll_cl48RxEEEStates_l_RX_LINK_FAIL 32 1016 #define anapll_cl48RxEEEStates_l_RX_WAKE 16 1017 #define anapll_cl48RxEEEStates_l_RX_QUIET 8 1018 #define anapll_cl48RxEEEStates_l_RX_DEACT 4 1019 #define anapll_cl48RxEEEStates_l_RX_SLEEP 2 1020 #define anapll_cl48RxEEEStates_l_RX_ACTIVE 1 1021 1022 /**************************************************************************** 1023 * Enums: anapll_cl48RxEEEStates_c 1024 */ 1025 #define anapll_cl48RxEEEStates_c_RX_LINK_FAIL 5 1026 #define anapll_cl48RxEEEStates_c_RX_WAKE 4 1027 #define anapll_cl48RxEEEStates_c_RX_QUIET 3 1028 #define anapll_cl48RxEEEStates_c_RX_DEACT 2 1029 #define anapll_cl48RxEEEStates_c_RX_SLEEP 1 1030 #define anapll_cl48RxEEEStates_c_RX_ACTIVE 0 1031 1032 /**************************************************************************** 1033 * Enums: anapll_IQP_Options 1034 */ 1035 #define anapll_IQP_Options_i50uA 0 1036 #define anapll_IQP_Options_i100uA 1 1037 #define anapll_IQP_Options_i150uA 2 1038 #define anapll_IQP_Options_i200uA 3 1039 #define anapll_IQP_Options_i250uA 4 1040 #define anapll_IQP_Options_i300uA 5 1041 #define anapll_IQP_Options_i350uA 6 1042 #define anapll_IQP_Options_i400uA 7 1043 #define anapll_IQP_Options_i450uA 8 1044 #define anapll_IQP_Options_i500uA 9 1045 #define anapll_IQP_Options_i550uA 10 1046 #define anapll_IQP_Options_i600uA 11 1047 #define anapll_IQP_Options_i650uA 12 1048 #define anapll_IQP_Options_i700uA 13 1049 #define anapll_IQP_Options_i750uA 14 1050 #define anapll_IQP_Options_i800uA 15 1051 1052 /**************************************************************************** 1053 * Enums: anapll_IDriver_Options 1054 */ 1055 #define anapll_IDriver_Options_v680mV 0 1056 #define anapll_IDriver_Options_v730mV 1 1057 #define anapll_IDriver_Options_v780mV 2 1058 #define anapll_IDriver_Options_v830mV 3 1059 #define anapll_IDriver_Options_v880mV 4 1060 #define anapll_IDriver_Options_v930mV 5 1061 #define anapll_IDriver_Options_v980mV 6 1062 #define anapll_IDriver_Options_v1010mV 7 1063 #define anapll_IDriver_Options_v1040mV 8 1064 #define anapll_IDriver_Options_v1060mV 9 1065 #define anapll_IDriver_Options_v1070mV 10 1066 #define anapll_IDriver_Options_v1080mV 11 1067 #define anapll_IDriver_Options_v1085mV 12 1068 #define anapll_IDriver_Options_v1090mV 13 1069 #define anapll_IDriver_Options_v1095mV 14 1070 #define anapll_IDriver_Options_v1100mV 15 1071 1072 /**************************************************************************** 1073 * Enums: anapll_operationModes 1074 */ 1075 #define anapll_operationModes_XGXS 0 1076 #define anapll_operationModes_XGXG_nCC 1 1077 #define anapll_operationModes_Indlane_OS8 4 1078 #define anapll_operationModes_IndLane_OS5 5 1079 #define anapll_operationModes_PCI 7 1080 #define anapll_operationModes_XGXS_nLQ 8 1081 #define anapll_operationModes_XGXS_nLQnCC 9 1082 #define anapll_operationModes_PBypass 10 1083 #define anapll_operationModes_PBypass_nDSK 11 1084 #define anapll_operationModes_ComboCoreMode 12 1085 #define anapll_operationModes_Clocks_off 15 1086 1087 /**************************************************************************** 1088 * Enums: anapll_actualSpeeds 1089 */ 1090 #define anapll_actualSpeeds_dr_10M 0 1091 #define anapll_actualSpeeds_dr_100M 1 1092 #define anapll_actualSpeeds_dr_1G 2 1093 #define anapll_actualSpeeds_dr_2p5G 3 1094 #define anapll_actualSpeeds_dr_5G_X4 4 1095 #define anapll_actualSpeeds_dr_6G_X4 5 1096 #define anapll_actualSpeeds_dr_10G_HiG 6 1097 #define anapll_actualSpeeds_dr_10G_CX4 7 1098 #define anapll_actualSpeeds_dr_12G_HiG 8 1099 #define anapll_actualSpeeds_dr_12p5G_X4 9 1100 #define anapll_actualSpeeds_dr_13G_X4 10 1101 #define anapll_actualSpeeds_dr_15G_X4 11 1102 #define anapll_actualSpeeds_dr_16G_X4 12 1103 #define anapll_actualSpeeds_dr_1G_KX 13 1104 #define anapll_actualSpeeds_dr_10G_KX4 14 1105 #define anapll_actualSpeeds_dr_10G_KR 15 1106 #define anapll_actualSpeeds_dr_5G 16 1107 #define anapll_actualSpeeds_dr_6p4G 17 1108 #define anapll_actualSpeeds_dr_20G_X4 18 1109 #define anapll_actualSpeeds_dr_21G_X4 19 1110 #define anapll_actualSpeeds_dr_25G_X4 20 1111 #define anapll_actualSpeeds_dr_10G_HiG_DXGXS 21 1112 #define anapll_actualSpeeds_dr_10G_DXGXS 22 1113 #define anapll_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1114 #define anapll_actualSpeeds_dr_10p5G_DXGXS 24 1115 #define anapll_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1116 #define anapll_actualSpeeds_dr_12p773G_DXGXS 26 1117 #define anapll_actualSpeeds_dr_10G_XFI 27 1118 #define anapll_actualSpeeds_dr_40G 28 1119 #define anapll_actualSpeeds_dr_20G_HiG_DXGXS 29 1120 #define anapll_actualSpeeds_dr_20G_DXGXS 30 1121 #define anapll_actualSpeeds_dr_10G_SFI 31 1122 #define anapll_actualSpeeds_dr_31p5G 32 1123 #define anapll_actualSpeeds_dr_32p7G 33 1124 #define anapll_actualSpeeds_dr_20G_SCR 34 1125 #define anapll_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1126 #define anapll_actualSpeeds_dr_10G_DXGXS_SCR 36 1127 #define anapll_actualSpeeds_dr_12G_R2 37 1128 #define anapll_actualSpeeds_dr_10G_X2 38 1129 #define anapll_actualSpeeds_dr_40G_KR4 39 1130 #define anapll_actualSpeeds_dr_40G_CR4 40 1131 #define anapll_actualSpeeds_dr_100G_CR10 41 1132 #define anapll_actualSpeeds_dr_15p75G_DXGXS 44 1133 #define anapll_actualSpeeds_dr_20G_KR2 57 1134 #define anapll_actualSpeeds_dr_20G_CR2 58 1135 1136 /**************************************************************************** 1137 * Enums: anapll_actualSpeedsMisc1 1138 */ 1139 #define anapll_actualSpeedsMisc1_dr_2500BRCM_X1 16 1140 #define anapll_actualSpeedsMisc1_dr_5000BRCM_X4 17 1141 #define anapll_actualSpeedsMisc1_dr_6000BRCM_X4 18 1142 #define anapll_actualSpeedsMisc1_dr_10GHiGig_X4 19 1143 #define anapll_actualSpeedsMisc1_dr_10GBASE_CX4 20 1144 #define anapll_actualSpeedsMisc1_dr_12GHiGig_X4 21 1145 #define anapll_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1146 #define anapll_actualSpeedsMisc1_dr_13GHiGig_X4 23 1147 #define anapll_actualSpeedsMisc1_dr_15GHiGig_X4 24 1148 #define anapll_actualSpeedsMisc1_dr_16GHiGig_X4 25 1149 #define anapll_actualSpeedsMisc1_dr_5000BRCM_X1 26 1150 #define anapll_actualSpeedsMisc1_dr_6363BRCM_X1 27 1151 #define anapll_actualSpeedsMisc1_dr_20GHiGig_X4 28 1152 #define anapll_actualSpeedsMisc1_dr_21GHiGig_X4 29 1153 #define anapll_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1154 #define anapll_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1155 1156 /**************************************************************************** 1157 * Enums: anapll_IndLaneModes 1158 */ 1159 #define anapll_IndLaneModes_SWSDR_div2 0 1160 #define anapll_IndLaneModes_SWSDR_div1 1 1161 #define anapll_IndLaneModes_DWSDR_div2 2 1162 #define anapll_IndLaneModes_DWSDR_div1 3 1163 1164 /**************************************************************************** 1165 * Enums: anapll_prbsSelect 1166 */ 1167 #define anapll_prbsSelect_prbs7 0 1168 #define anapll_prbsSelect_prbs15 1 1169 #define anapll_prbsSelect_prbs23 2 1170 #define anapll_prbsSelect_prbs31 3 1171 1172 /**************************************************************************** 1173 * Enums: anapll_vcoDivider 1174 */ 1175 #define anapll_vcoDivider_div32 0 1176 #define anapll_vcoDivider_div36 1 1177 #define anapll_vcoDivider_div40 2 1178 #define anapll_vcoDivider_div42 3 1179 #define anapll_vcoDivider_div48 4 1180 #define anapll_vcoDivider_div50 5 1181 #define anapll_vcoDivider_div52 6 1182 #define anapll_vcoDivider_div54 7 1183 #define anapll_vcoDivider_div60 8 1184 #define anapll_vcoDivider_div64 9 1185 #define anapll_vcoDivider_div66 10 1186 #define anapll_vcoDivider_div68 11 1187 #define anapll_vcoDivider_div70 12 1188 #define anapll_vcoDivider_div80 13 1189 #define anapll_vcoDivider_div92 14 1190 #define anapll_vcoDivider_div100 15 1191 1192 /**************************************************************************** 1193 * Enums: anapll_refClkSelect 1194 */ 1195 #define anapll_refClkSelect_clk_25MHz 0 1196 #define anapll_refClkSelect_clk_100MHz 1 1197 #define anapll_refClkSelect_clk_125MHz 2 1198 #define anapll_refClkSelect_clk_156p25MHz 3 1199 #define anapll_refClkSelect_clk_187p5MHz 4 1200 #define anapll_refClkSelect_clk_161p25Mhz 5 1201 #define anapll_refClkSelect_clk_50Mhz 6 1202 #define anapll_refClkSelect_clk_106p25Mhz 7 1203 1204 /**************************************************************************** 1205 * Enums: anapll_aerMMDdevTypeSelect 1206 */ 1207 #define anapll_aerMMDdevTypeSelect_combo_core 0 1208 #define anapll_aerMMDdevTypeSelect_PMA_PMD 1 1209 #define anapll_aerMMDdevTypeSelect_PCS 3 1210 #define anapll_aerMMDdevTypeSelect_PHY 4 1211 #define anapll_aerMMDdevTypeSelect_DTE 5 1212 #define anapll_aerMMDdevTypeSelect_CL73_AN 7 1213 1214 /**************************************************************************** 1215 * Enums: anapll_aerMMDportSelect 1216 */ 1217 #define anapll_aerMMDportSelect_ln0 0 1218 #define anapll_aerMMDportSelect_ln1 1 1219 #define anapll_aerMMDportSelect_ln2 2 1220 #define anapll_aerMMDportSelect_ln3 3 1221 #define anapll_aerMMDportSelect_BCST_ln0_1_2_3 511 1222 #define anapll_aerMMDportSelect_BCST_ln0_1 512 1223 #define anapll_aerMMDportSelect_BCST_ln2_3 513 1224 1225 /**************************************************************************** 1226 * Enums: anapll_firmwareModeSelect 1227 */ 1228 #define anapll_firmwareModeSelect_DEFAULT 0 1229 #define anapll_firmwareModeSelect_SFP_OPT_LR 1 1230 #define anapll_firmwareModeSelect_SFP_DAC 2 1231 #define anapll_firmwareModeSelect_XLAUI 3 1232 #define anapll_firmwareModeSelect_LONG_CH_6G 4 1233 1234 /**************************************************************************** 1235 * Enums: anapll_tempIdxSelect 1236 */ 1237 #define anapll_tempIdxSelect_LTE__22p9C 15 1238 #define anapll_tempIdxSelect_LTE__12p6C 14 1239 #define anapll_tempIdxSelect_LTE__3p0C 13 1240 #define anapll_tempIdxSelect_LTE_6p7C 12 1241 #define anapll_tempIdxSelect_LTE_16p4C 11 1242 #define anapll_tempIdxSelect_LTE_26p6C 10 1243 #define anapll_tempIdxSelect_LTE_36p3C 9 1244 #define anapll_tempIdxSelect_LTE_46p0C 8 1245 #define anapll_tempIdxSelect_LTE_56p2C 7 1246 #define anapll_tempIdxSelect_LTE_65p9C 6 1247 #define anapll_tempIdxSelect_LTE_75p6C 5 1248 #define anapll_tempIdxSelect_LTE_85p3C 4 1249 #define anapll_tempIdxSelect_LTE_95p5C 3 1250 #define anapll_tempIdxSelect_LTE_105p2C 2 1251 #define anapll_tempIdxSelect_LTE_114p9C 1 1252 #define anapll_tempIdxSelect_LTE_125p1C 0 1253 1254 /**************************************************************************** 1255 * Enums: anarx_cl36TxEEEStates_l 1256 */ 1257 #define anarx_cl36TxEEEStates_l_TX_REFRESH 8 1258 #define anarx_cl36TxEEEStates_l_TX_QUIET 4 1259 #define anarx_cl36TxEEEStates_l_TX_SLEEP 2 1260 #define anarx_cl36TxEEEStates_l_TX_ACTIVE 1 1261 1262 /**************************************************************************** 1263 * Enums: anarx_cl36TxEEEStates_c 1264 */ 1265 #define anarx_cl36TxEEEStates_c_TX_REFRESH 3 1266 #define anarx_cl36TxEEEStates_c_TX_QUIET 2 1267 #define anarx_cl36TxEEEStates_c_TX_SLEEP 1 1268 #define anarx_cl36TxEEEStates_c_TX_ACTIVE 0 1269 1270 /**************************************************************************** 1271 * Enums: anarx_cl49TxEEEStates_l 1272 */ 1273 #define anarx_cl49TxEEEStates_l_SCR_RESET_2 64 1274 #define anarx_cl49TxEEEStates_l_SCR_RESET_1 32 1275 #define anarx_cl49TxEEEStates_l_TX_WAKE 16 1276 #define anarx_cl49TxEEEStates_l_TX_REFRESH 8 1277 #define anarx_cl49TxEEEStates_l_TX_QUIET 4 1278 #define anarx_cl49TxEEEStates_l_TX_SLEEP 2 1279 #define anarx_cl49TxEEEStates_l_TX_ACTIVE 1 1280 1281 /**************************************************************************** 1282 * Enums: anarx_cl49TxEEEStates_c 1283 */ 1284 #define anarx_cl49TxEEEStates_c_SCR_RESET_2 6 1285 #define anarx_cl49TxEEEStates_c_SCR_RESET_1 5 1286 #define anarx_cl49TxEEEStates_c_TX_WAKE 4 1287 #define anarx_cl49TxEEEStates_c_TX_REFRESH 3 1288 #define anarx_cl49TxEEEStates_c_TX_QUIET 2 1289 #define anarx_cl49TxEEEStates_c_TX_SLEEP 1 1290 #define anarx_cl49TxEEEStates_c_TX_ACTIVE 0 1291 1292 /**************************************************************************** 1293 * Enums: anarx_cl36RxEEEStates_l 1294 */ 1295 #define anarx_cl36RxEEEStates_l_RX_LINK_FAIL 32 1296 #define anarx_cl36RxEEEStates_l_RX_WTF 16 1297 #define anarx_cl36RxEEEStates_l_RX_WAKE 8 1298 #define anarx_cl36RxEEEStates_l_RX_QUIET 4 1299 #define anarx_cl36RxEEEStates_l_RX_SLEEP 2 1300 #define anarx_cl36RxEEEStates_l_RX_ACTIVE 1 1301 1302 /**************************************************************************** 1303 * Enums: anarx_cl36RxEEEStates_c 1304 */ 1305 #define anarx_cl36RxEEEStates_c_RX_LINK_FAIL 5 1306 #define anarx_cl36RxEEEStates_c_RX_WTF 4 1307 #define anarx_cl36RxEEEStates_c_RX_WAKE 3 1308 #define anarx_cl36RxEEEStates_c_RX_QUIET 2 1309 #define anarx_cl36RxEEEStates_c_RX_SLEEP 1 1310 #define anarx_cl36RxEEEStates_c_RX_ACTIVE 0 1311 1312 /**************************************************************************** 1313 * Enums: anarx_cl49RxEEEStates_l 1314 */ 1315 #define anarx_cl49RxEEEStates_l_RX_LINK_FAIL 32 1316 #define anarx_cl49RxEEEStates_l_RX_WTF 16 1317 #define anarx_cl49RxEEEStates_l_RX_WAKE 8 1318 #define anarx_cl49RxEEEStates_l_RX_QUIET 4 1319 #define anarx_cl49RxEEEStates_l_RX_SLEEP 2 1320 #define anarx_cl49RxEEEStates_l_RX_ACTIVE 1 1321 1322 /**************************************************************************** 1323 * Enums: anarx_cl49RxEEEStates_c 1324 */ 1325 #define anarx_cl49RxEEEStates_c_RX_LINK_FAIL 5 1326 #define anarx_cl49RxEEEStates_c_RX_WTF 4 1327 #define anarx_cl49RxEEEStates_c_RX_WAKE 3 1328 #define anarx_cl49RxEEEStates_c_RX_QUIET 2 1329 #define anarx_cl49RxEEEStates_c_RX_SLEEP 1 1330 #define anarx_cl49RxEEEStates_c_RX_ACTIVE 0 1331 1332 /**************************************************************************** 1333 * Enums: anarx_cl48TxEEEStates_l 1334 */ 1335 #define anarx_cl48TxEEEStates_l_TX_REFRESH 8 1336 #define anarx_cl48TxEEEStates_l_TX_QUIET 4 1337 #define anarx_cl48TxEEEStates_l_TX_SLEEP 2 1338 #define anarx_cl48TxEEEStates_l_TX_ACTIVE 1 1339 1340 /**************************************************************************** 1341 * Enums: anarx_cl48TxEEEStates_c 1342 */ 1343 #define anarx_cl48TxEEEStates_c_TX_REFRESH 3 1344 #define anarx_cl48TxEEEStates_c_TX_QUIET 2 1345 #define anarx_cl48TxEEEStates_c_TX_SLEEP 1 1346 #define anarx_cl48TxEEEStates_c_TX_ACTIVE 0 1347 1348 /**************************************************************************** 1349 * Enums: anarx_cl48RxEEEStates_l 1350 */ 1351 #define anarx_cl48RxEEEStates_l_RX_LINK_FAIL 32 1352 #define anarx_cl48RxEEEStates_l_RX_WAKE 16 1353 #define anarx_cl48RxEEEStates_l_RX_QUIET 8 1354 #define anarx_cl48RxEEEStates_l_RX_DEACT 4 1355 #define anarx_cl48RxEEEStates_l_RX_SLEEP 2 1356 #define anarx_cl48RxEEEStates_l_RX_ACTIVE 1 1357 1358 /**************************************************************************** 1359 * Enums: anarx_cl48RxEEEStates_c 1360 */ 1361 #define anarx_cl48RxEEEStates_c_RX_LINK_FAIL 5 1362 #define anarx_cl48RxEEEStates_c_RX_WAKE 4 1363 #define anarx_cl48RxEEEStates_c_RX_QUIET 3 1364 #define anarx_cl48RxEEEStates_c_RX_DEACT 2 1365 #define anarx_cl48RxEEEStates_c_RX_SLEEP 1 1366 #define anarx_cl48RxEEEStates_c_RX_ACTIVE 0 1367 1368 /**************************************************************************** 1369 * Enums: anarx_IQP_Options 1370 */ 1371 #define anarx_IQP_Options_i50uA 0 1372 #define anarx_IQP_Options_i100uA 1 1373 #define anarx_IQP_Options_i150uA 2 1374 #define anarx_IQP_Options_i200uA 3 1375 #define anarx_IQP_Options_i250uA 4 1376 #define anarx_IQP_Options_i300uA 5 1377 #define anarx_IQP_Options_i350uA 6 1378 #define anarx_IQP_Options_i400uA 7 1379 #define anarx_IQP_Options_i450uA 8 1380 #define anarx_IQP_Options_i500uA 9 1381 #define anarx_IQP_Options_i550uA 10 1382 #define anarx_IQP_Options_i600uA 11 1383 #define anarx_IQP_Options_i650uA 12 1384 #define anarx_IQP_Options_i700uA 13 1385 #define anarx_IQP_Options_i750uA 14 1386 #define anarx_IQP_Options_i800uA 15 1387 1388 /**************************************************************************** 1389 * Enums: anarx_IDriver_Options 1390 */ 1391 #define anarx_IDriver_Options_v680mV 0 1392 #define anarx_IDriver_Options_v730mV 1 1393 #define anarx_IDriver_Options_v780mV 2 1394 #define anarx_IDriver_Options_v830mV 3 1395 #define anarx_IDriver_Options_v880mV 4 1396 #define anarx_IDriver_Options_v930mV 5 1397 #define anarx_IDriver_Options_v980mV 6 1398 #define anarx_IDriver_Options_v1010mV 7 1399 #define anarx_IDriver_Options_v1040mV 8 1400 #define anarx_IDriver_Options_v1060mV 9 1401 #define anarx_IDriver_Options_v1070mV 10 1402 #define anarx_IDriver_Options_v1080mV 11 1403 #define anarx_IDriver_Options_v1085mV 12 1404 #define anarx_IDriver_Options_v1090mV 13 1405 #define anarx_IDriver_Options_v1095mV 14 1406 #define anarx_IDriver_Options_v1100mV 15 1407 1408 /**************************************************************************** 1409 * Enums: anarx_operationModes 1410 */ 1411 #define anarx_operationModes_XGXS 0 1412 #define anarx_operationModes_XGXG_nCC 1 1413 #define anarx_operationModes_Indlane_OS8 4 1414 #define anarx_operationModes_IndLane_OS5 5 1415 #define anarx_operationModes_PCI 7 1416 #define anarx_operationModes_XGXS_nLQ 8 1417 #define anarx_operationModes_XGXS_nLQnCC 9 1418 #define anarx_operationModes_PBypass 10 1419 #define anarx_operationModes_PBypass_nDSK 11 1420 #define anarx_operationModes_ComboCoreMode 12 1421 #define anarx_operationModes_Clocks_off 15 1422 1423 /**************************************************************************** 1424 * Enums: anarx_actualSpeeds 1425 */ 1426 #define anarx_actualSpeeds_dr_10M 0 1427 #define anarx_actualSpeeds_dr_100M 1 1428 #define anarx_actualSpeeds_dr_1G 2 1429 #define anarx_actualSpeeds_dr_2p5G 3 1430 #define anarx_actualSpeeds_dr_5G_X4 4 1431 #define anarx_actualSpeeds_dr_6G_X4 5 1432 #define anarx_actualSpeeds_dr_10G_HiG 6 1433 #define anarx_actualSpeeds_dr_10G_CX4 7 1434 #define anarx_actualSpeeds_dr_12G_HiG 8 1435 #define anarx_actualSpeeds_dr_12p5G_X4 9 1436 #define anarx_actualSpeeds_dr_13G_X4 10 1437 #define anarx_actualSpeeds_dr_15G_X4 11 1438 #define anarx_actualSpeeds_dr_16G_X4 12 1439 #define anarx_actualSpeeds_dr_1G_KX 13 1440 #define anarx_actualSpeeds_dr_10G_KX4 14 1441 #define anarx_actualSpeeds_dr_10G_KR 15 1442 #define anarx_actualSpeeds_dr_5G 16 1443 #define anarx_actualSpeeds_dr_6p4G 17 1444 #define anarx_actualSpeeds_dr_20G_X4 18 1445 #define anarx_actualSpeeds_dr_21G_X4 19 1446 #define anarx_actualSpeeds_dr_25G_X4 20 1447 #define anarx_actualSpeeds_dr_10G_HiG_DXGXS 21 1448 #define anarx_actualSpeeds_dr_10G_DXGXS 22 1449 #define anarx_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1450 #define anarx_actualSpeeds_dr_10p5G_DXGXS 24 1451 #define anarx_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1452 #define anarx_actualSpeeds_dr_12p773G_DXGXS 26 1453 #define anarx_actualSpeeds_dr_10G_XFI 27 1454 #define anarx_actualSpeeds_dr_40G 28 1455 #define anarx_actualSpeeds_dr_20G_HiG_DXGXS 29 1456 #define anarx_actualSpeeds_dr_20G_DXGXS 30 1457 #define anarx_actualSpeeds_dr_10G_SFI 31 1458 #define anarx_actualSpeeds_dr_31p5G 32 1459 #define anarx_actualSpeeds_dr_32p7G 33 1460 #define anarx_actualSpeeds_dr_20G_SCR 34 1461 #define anarx_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1462 #define anarx_actualSpeeds_dr_10G_DXGXS_SCR 36 1463 #define anarx_actualSpeeds_dr_12G_R2 37 1464 #define anarx_actualSpeeds_dr_10G_X2 38 1465 #define anarx_actualSpeeds_dr_40G_KR4 39 1466 #define anarx_actualSpeeds_dr_40G_CR4 40 1467 #define anarx_actualSpeeds_dr_100G_CR10 41 1468 #define anarx_actualSpeeds_dr_15p75G_DXGXS 44 1469 #define anarx_actualSpeeds_dr_20G_KR2 57 1470 #define anarx_actualSpeeds_dr_20G_CR2 58 1471 1472 /**************************************************************************** 1473 * Enums: anarx_actualSpeedsMisc1 1474 */ 1475 #define anarx_actualSpeedsMisc1_dr_2500BRCM_X1 16 1476 #define anarx_actualSpeedsMisc1_dr_5000BRCM_X4 17 1477 #define anarx_actualSpeedsMisc1_dr_6000BRCM_X4 18 1478 #define anarx_actualSpeedsMisc1_dr_10GHiGig_X4 19 1479 #define anarx_actualSpeedsMisc1_dr_10GBASE_CX4 20 1480 #define anarx_actualSpeedsMisc1_dr_12GHiGig_X4 21 1481 #define anarx_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1482 #define anarx_actualSpeedsMisc1_dr_13GHiGig_X4 23 1483 #define anarx_actualSpeedsMisc1_dr_15GHiGig_X4 24 1484 #define anarx_actualSpeedsMisc1_dr_16GHiGig_X4 25 1485 #define anarx_actualSpeedsMisc1_dr_5000BRCM_X1 26 1486 #define anarx_actualSpeedsMisc1_dr_6363BRCM_X1 27 1487 #define anarx_actualSpeedsMisc1_dr_20GHiGig_X4 28 1488 #define anarx_actualSpeedsMisc1_dr_21GHiGig_X4 29 1489 #define anarx_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1490 #define anarx_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1491 1492 /**************************************************************************** 1493 * Enums: anarx_IndLaneModes 1494 */ 1495 #define anarx_IndLaneModes_SWSDR_div2 0 1496 #define anarx_IndLaneModes_SWSDR_div1 1 1497 #define anarx_IndLaneModes_DWSDR_div2 2 1498 #define anarx_IndLaneModes_DWSDR_div1 3 1499 1500 /**************************************************************************** 1501 * Enums: anarx_prbsSelect 1502 */ 1503 #define anarx_prbsSelect_prbs7 0 1504 #define anarx_prbsSelect_prbs15 1 1505 #define anarx_prbsSelect_prbs23 2 1506 #define anarx_prbsSelect_prbs31 3 1507 1508 /**************************************************************************** 1509 * Enums: anarx_vcoDivider 1510 */ 1511 #define anarx_vcoDivider_div32 0 1512 #define anarx_vcoDivider_div36 1 1513 #define anarx_vcoDivider_div40 2 1514 #define anarx_vcoDivider_div42 3 1515 #define anarx_vcoDivider_div48 4 1516 #define anarx_vcoDivider_div50 5 1517 #define anarx_vcoDivider_div52 6 1518 #define anarx_vcoDivider_div54 7 1519 #define anarx_vcoDivider_div60 8 1520 #define anarx_vcoDivider_div64 9 1521 #define anarx_vcoDivider_div66 10 1522 #define anarx_vcoDivider_div68 11 1523 #define anarx_vcoDivider_div70 12 1524 #define anarx_vcoDivider_div80 13 1525 #define anarx_vcoDivider_div92 14 1526 #define anarx_vcoDivider_div100 15 1527 1528 /**************************************************************************** 1529 * Enums: anarx_refClkSelect 1530 */ 1531 #define anarx_refClkSelect_clk_25MHz 0 1532 #define anarx_refClkSelect_clk_100MHz 1 1533 #define anarx_refClkSelect_clk_125MHz 2 1534 #define anarx_refClkSelect_clk_156p25MHz 3 1535 #define anarx_refClkSelect_clk_187p5MHz 4 1536 #define anarx_refClkSelect_clk_161p25Mhz 5 1537 #define anarx_refClkSelect_clk_50Mhz 6 1538 #define anarx_refClkSelect_clk_106p25Mhz 7 1539 1540 /**************************************************************************** 1541 * Enums: anarx_aerMMDdevTypeSelect 1542 */ 1543 #define anarx_aerMMDdevTypeSelect_combo_core 0 1544 #define anarx_aerMMDdevTypeSelect_PMA_PMD 1 1545 #define anarx_aerMMDdevTypeSelect_PCS 3 1546 #define anarx_aerMMDdevTypeSelect_PHY 4 1547 #define anarx_aerMMDdevTypeSelect_DTE 5 1548 #define anarx_aerMMDdevTypeSelect_CL73_AN 7 1549 1550 /**************************************************************************** 1551 * Enums: anarx_aerMMDportSelect 1552 */ 1553 #define anarx_aerMMDportSelect_ln0 0 1554 #define anarx_aerMMDportSelect_ln1 1 1555 #define anarx_aerMMDportSelect_ln2 2 1556 #define anarx_aerMMDportSelect_ln3 3 1557 #define anarx_aerMMDportSelect_BCST_ln0_1_2_3 511 1558 #define anarx_aerMMDportSelect_BCST_ln0_1 512 1559 #define anarx_aerMMDportSelect_BCST_ln2_3 513 1560 1561 /**************************************************************************** 1562 * Enums: anarx_firmwareModeSelect 1563 */ 1564 #define anarx_firmwareModeSelect_DEFAULT 0 1565 #define anarx_firmwareModeSelect_SFP_OPT_LR 1 1566 #define anarx_firmwareModeSelect_SFP_DAC 2 1567 #define anarx_firmwareModeSelect_XLAUI 3 1568 #define anarx_firmwareModeSelect_LONG_CH_6G 4 1569 1570 /**************************************************************************** 1571 * Enums: anarx_tempIdxSelect 1572 */ 1573 #define anarx_tempIdxSelect_LTE__22p9C 15 1574 #define anarx_tempIdxSelect_LTE__12p6C 14 1575 #define anarx_tempIdxSelect_LTE__3p0C 13 1576 #define anarx_tempIdxSelect_LTE_6p7C 12 1577 #define anarx_tempIdxSelect_LTE_16p4C 11 1578 #define anarx_tempIdxSelect_LTE_26p6C 10 1579 #define anarx_tempIdxSelect_LTE_36p3C 9 1580 #define anarx_tempIdxSelect_LTE_46p0C 8 1581 #define anarx_tempIdxSelect_LTE_56p2C 7 1582 #define anarx_tempIdxSelect_LTE_65p9C 6 1583 #define anarx_tempIdxSelect_LTE_75p6C 5 1584 #define anarx_tempIdxSelect_LTE_85p3C 4 1585 #define anarx_tempIdxSelect_LTE_95p5C 3 1586 #define anarx_tempIdxSelect_LTE_105p2C 2 1587 #define anarx_tempIdxSelect_LTE_114p9C 1 1588 #define anarx_tempIdxSelect_LTE_125p1C 0 1589 1590 /**************************************************************************** 1591 * Enums: anatx_cl36TxEEEStates_l 1592 */ 1593 #define anatx_cl36TxEEEStates_l_TX_REFRESH 8 1594 #define anatx_cl36TxEEEStates_l_TX_QUIET 4 1595 #define anatx_cl36TxEEEStates_l_TX_SLEEP 2 1596 #define anatx_cl36TxEEEStates_l_TX_ACTIVE 1 1597 1598 /**************************************************************************** 1599 * Enums: anatx_cl36TxEEEStates_c 1600 */ 1601 #define anatx_cl36TxEEEStates_c_TX_REFRESH 3 1602 #define anatx_cl36TxEEEStates_c_TX_QUIET 2 1603 #define anatx_cl36TxEEEStates_c_TX_SLEEP 1 1604 #define anatx_cl36TxEEEStates_c_TX_ACTIVE 0 1605 1606 /**************************************************************************** 1607 * Enums: anatx_cl49TxEEEStates_l 1608 */ 1609 #define anatx_cl49TxEEEStates_l_SCR_RESET_2 64 1610 #define anatx_cl49TxEEEStates_l_SCR_RESET_1 32 1611 #define anatx_cl49TxEEEStates_l_TX_WAKE 16 1612 #define anatx_cl49TxEEEStates_l_TX_REFRESH 8 1613 #define anatx_cl49TxEEEStates_l_TX_QUIET 4 1614 #define anatx_cl49TxEEEStates_l_TX_SLEEP 2 1615 #define anatx_cl49TxEEEStates_l_TX_ACTIVE 1 1616 1617 /**************************************************************************** 1618 * Enums: anatx_cl49TxEEEStates_c 1619 */ 1620 #define anatx_cl49TxEEEStates_c_SCR_RESET_2 6 1621 #define anatx_cl49TxEEEStates_c_SCR_RESET_1 5 1622 #define anatx_cl49TxEEEStates_c_TX_WAKE 4 1623 #define anatx_cl49TxEEEStates_c_TX_REFRESH 3 1624 #define anatx_cl49TxEEEStates_c_TX_QUIET 2 1625 #define anatx_cl49TxEEEStates_c_TX_SLEEP 1 1626 #define anatx_cl49TxEEEStates_c_TX_ACTIVE 0 1627 1628 /**************************************************************************** 1629 * Enums: anatx_cl36RxEEEStates_l 1630 */ 1631 #define anatx_cl36RxEEEStates_l_RX_LINK_FAIL 32 1632 #define anatx_cl36RxEEEStates_l_RX_WTF 16 1633 #define anatx_cl36RxEEEStates_l_RX_WAKE 8 1634 #define anatx_cl36RxEEEStates_l_RX_QUIET 4 1635 #define anatx_cl36RxEEEStates_l_RX_SLEEP 2 1636 #define anatx_cl36RxEEEStates_l_RX_ACTIVE 1 1637 1638 /**************************************************************************** 1639 * Enums: anatx_cl36RxEEEStates_c 1640 */ 1641 #define anatx_cl36RxEEEStates_c_RX_LINK_FAIL 5 1642 #define anatx_cl36RxEEEStates_c_RX_WTF 4 1643 #define anatx_cl36RxEEEStates_c_RX_WAKE 3 1644 #define anatx_cl36RxEEEStates_c_RX_QUIET 2 1645 #define anatx_cl36RxEEEStates_c_RX_SLEEP 1 1646 #define anatx_cl36RxEEEStates_c_RX_ACTIVE 0 1647 1648 /**************************************************************************** 1649 * Enums: anatx_cl49RxEEEStates_l 1650 */ 1651 #define anatx_cl49RxEEEStates_l_RX_LINK_FAIL 32 1652 #define anatx_cl49RxEEEStates_l_RX_WTF 16 1653 #define anatx_cl49RxEEEStates_l_RX_WAKE 8 1654 #define anatx_cl49RxEEEStates_l_RX_QUIET 4 1655 #define anatx_cl49RxEEEStates_l_RX_SLEEP 2 1656 #define anatx_cl49RxEEEStates_l_RX_ACTIVE 1 1657 1658 /**************************************************************************** 1659 * Enums: anatx_cl49RxEEEStates_c 1660 */ 1661 #define anatx_cl49RxEEEStates_c_RX_LINK_FAIL 5 1662 #define anatx_cl49RxEEEStates_c_RX_WTF 4 1663 #define anatx_cl49RxEEEStates_c_RX_WAKE 3 1664 #define anatx_cl49RxEEEStates_c_RX_QUIET 2 1665 #define anatx_cl49RxEEEStates_c_RX_SLEEP 1 1666 #define anatx_cl49RxEEEStates_c_RX_ACTIVE 0 1667 1668 /**************************************************************************** 1669 * Enums: anatx_cl48TxEEEStates_l 1670 */ 1671 #define anatx_cl48TxEEEStates_l_TX_REFRESH 8 1672 #define anatx_cl48TxEEEStates_l_TX_QUIET 4 1673 #define anatx_cl48TxEEEStates_l_TX_SLEEP 2 1674 #define anatx_cl48TxEEEStates_l_TX_ACTIVE 1 1675 1676 /**************************************************************************** 1677 * Enums: anatx_cl48TxEEEStates_c 1678 */ 1679 #define anatx_cl48TxEEEStates_c_TX_REFRESH 3 1680 #define anatx_cl48TxEEEStates_c_TX_QUIET 2 1681 #define anatx_cl48TxEEEStates_c_TX_SLEEP 1 1682 #define anatx_cl48TxEEEStates_c_TX_ACTIVE 0 1683 1684 /**************************************************************************** 1685 * Enums: anatx_cl48RxEEEStates_l 1686 */ 1687 #define anatx_cl48RxEEEStates_l_RX_LINK_FAIL 32 1688 #define anatx_cl48RxEEEStates_l_RX_WAKE 16 1689 #define anatx_cl48RxEEEStates_l_RX_QUIET 8 1690 #define anatx_cl48RxEEEStates_l_RX_DEACT 4 1691 #define anatx_cl48RxEEEStates_l_RX_SLEEP 2 1692 #define anatx_cl48RxEEEStates_l_RX_ACTIVE 1 1693 1694 /**************************************************************************** 1695 * Enums: anatx_cl48RxEEEStates_c 1696 */ 1697 #define anatx_cl48RxEEEStates_c_RX_LINK_FAIL 5 1698 #define anatx_cl48RxEEEStates_c_RX_WAKE 4 1699 #define anatx_cl48RxEEEStates_c_RX_QUIET 3 1700 #define anatx_cl48RxEEEStates_c_RX_DEACT 2 1701 #define anatx_cl48RxEEEStates_c_RX_SLEEP 1 1702 #define anatx_cl48RxEEEStates_c_RX_ACTIVE 0 1703 1704 /**************************************************************************** 1705 * Enums: anatx_IQP_Options 1706 */ 1707 #define anatx_IQP_Options_i50uA 0 1708 #define anatx_IQP_Options_i100uA 1 1709 #define anatx_IQP_Options_i150uA 2 1710 #define anatx_IQP_Options_i200uA 3 1711 #define anatx_IQP_Options_i250uA 4 1712 #define anatx_IQP_Options_i300uA 5 1713 #define anatx_IQP_Options_i350uA 6 1714 #define anatx_IQP_Options_i400uA 7 1715 #define anatx_IQP_Options_i450uA 8 1716 #define anatx_IQP_Options_i500uA 9 1717 #define anatx_IQP_Options_i550uA 10 1718 #define anatx_IQP_Options_i600uA 11 1719 #define anatx_IQP_Options_i650uA 12 1720 #define anatx_IQP_Options_i700uA 13 1721 #define anatx_IQP_Options_i750uA 14 1722 #define anatx_IQP_Options_i800uA 15 1723 1724 /**************************************************************************** 1725 * Enums: anatx_IDriver_Options 1726 */ 1727 #define anatx_IDriver_Options_v680mV 0 1728 #define anatx_IDriver_Options_v730mV 1 1729 #define anatx_IDriver_Options_v780mV 2 1730 #define anatx_IDriver_Options_v830mV 3 1731 #define anatx_IDriver_Options_v880mV 4 1732 #define anatx_IDriver_Options_v930mV 5 1733 #define anatx_IDriver_Options_v980mV 6 1734 #define anatx_IDriver_Options_v1010mV 7 1735 #define anatx_IDriver_Options_v1040mV 8 1736 #define anatx_IDriver_Options_v1060mV 9 1737 #define anatx_IDriver_Options_v1070mV 10 1738 #define anatx_IDriver_Options_v1080mV 11 1739 #define anatx_IDriver_Options_v1085mV 12 1740 #define anatx_IDriver_Options_v1090mV 13 1741 #define anatx_IDriver_Options_v1095mV 14 1742 #define anatx_IDriver_Options_v1100mV 15 1743 1744 /**************************************************************************** 1745 * Enums: anatx_operationModes 1746 */ 1747 #define anatx_operationModes_XGXS 0 1748 #define anatx_operationModes_XGXG_nCC 1 1749 #define anatx_operationModes_Indlane_OS8 4 1750 #define anatx_operationModes_IndLane_OS5 5 1751 #define anatx_operationModes_PCI 7 1752 #define anatx_operationModes_XGXS_nLQ 8 1753 #define anatx_operationModes_XGXS_nLQnCC 9 1754 #define anatx_operationModes_PBypass 10 1755 #define anatx_operationModes_PBypass_nDSK 11 1756 #define anatx_operationModes_ComboCoreMode 12 1757 #define anatx_operationModes_Clocks_off 15 1758 1759 /**************************************************************************** 1760 * Enums: anatx_actualSpeeds 1761 */ 1762 #define anatx_actualSpeeds_dr_10M 0 1763 #define anatx_actualSpeeds_dr_100M 1 1764 #define anatx_actualSpeeds_dr_1G 2 1765 #define anatx_actualSpeeds_dr_2p5G 3 1766 #define anatx_actualSpeeds_dr_5G_X4 4 1767 #define anatx_actualSpeeds_dr_6G_X4 5 1768 #define anatx_actualSpeeds_dr_10G_HiG 6 1769 #define anatx_actualSpeeds_dr_10G_CX4 7 1770 #define anatx_actualSpeeds_dr_12G_HiG 8 1771 #define anatx_actualSpeeds_dr_12p5G_X4 9 1772 #define anatx_actualSpeeds_dr_13G_X4 10 1773 #define anatx_actualSpeeds_dr_15G_X4 11 1774 #define anatx_actualSpeeds_dr_16G_X4 12 1775 #define anatx_actualSpeeds_dr_1G_KX 13 1776 #define anatx_actualSpeeds_dr_10G_KX4 14 1777 #define anatx_actualSpeeds_dr_10G_KR 15 1778 #define anatx_actualSpeeds_dr_5G 16 1779 #define anatx_actualSpeeds_dr_6p4G 17 1780 #define anatx_actualSpeeds_dr_20G_X4 18 1781 #define anatx_actualSpeeds_dr_21G_X4 19 1782 #define anatx_actualSpeeds_dr_25G_X4 20 1783 #define anatx_actualSpeeds_dr_10G_HiG_DXGXS 21 1784 #define anatx_actualSpeeds_dr_10G_DXGXS 22 1785 #define anatx_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1786 #define anatx_actualSpeeds_dr_10p5G_DXGXS 24 1787 #define anatx_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1788 #define anatx_actualSpeeds_dr_12p773G_DXGXS 26 1789 #define anatx_actualSpeeds_dr_10G_XFI 27 1790 #define anatx_actualSpeeds_dr_40G 28 1791 #define anatx_actualSpeeds_dr_20G_HiG_DXGXS 29 1792 #define anatx_actualSpeeds_dr_20G_DXGXS 30 1793 #define anatx_actualSpeeds_dr_10G_SFI 31 1794 #define anatx_actualSpeeds_dr_31p5G 32 1795 #define anatx_actualSpeeds_dr_32p7G 33 1796 #define anatx_actualSpeeds_dr_20G_SCR 34 1797 #define anatx_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1798 #define anatx_actualSpeeds_dr_10G_DXGXS_SCR 36 1799 #define anatx_actualSpeeds_dr_12G_R2 37 1800 #define anatx_actualSpeeds_dr_10G_X2 38 1801 #define anatx_actualSpeeds_dr_40G_KR4 39 1802 #define anatx_actualSpeeds_dr_40G_CR4 40 1803 #define anatx_actualSpeeds_dr_100G_CR10 41 1804 #define anatx_actualSpeeds_dr_15p75G_DXGXS 44 1805 #define anatx_actualSpeeds_dr_20G_KR2 57 1806 #define anatx_actualSpeeds_dr_20G_CR2 58 1807 1808 /**************************************************************************** 1809 * Enums: anatx_actualSpeedsMisc1 1810 */ 1811 #define anatx_actualSpeedsMisc1_dr_2500BRCM_X1 16 1812 #define anatx_actualSpeedsMisc1_dr_5000BRCM_X4 17 1813 #define anatx_actualSpeedsMisc1_dr_6000BRCM_X4 18 1814 #define anatx_actualSpeedsMisc1_dr_10GHiGig_X4 19 1815 #define anatx_actualSpeedsMisc1_dr_10GBASE_CX4 20 1816 #define anatx_actualSpeedsMisc1_dr_12GHiGig_X4 21 1817 #define anatx_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1818 #define anatx_actualSpeedsMisc1_dr_13GHiGig_X4 23 1819 #define anatx_actualSpeedsMisc1_dr_15GHiGig_X4 24 1820 #define anatx_actualSpeedsMisc1_dr_16GHiGig_X4 25 1821 #define anatx_actualSpeedsMisc1_dr_5000BRCM_X1 26 1822 #define anatx_actualSpeedsMisc1_dr_6363BRCM_X1 27 1823 #define anatx_actualSpeedsMisc1_dr_20GHiGig_X4 28 1824 #define anatx_actualSpeedsMisc1_dr_21GHiGig_X4 29 1825 #define anatx_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1826 #define anatx_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1827 1828 /**************************************************************************** 1829 * Enums: anatx_IndLaneModes 1830 */ 1831 #define anatx_IndLaneModes_SWSDR_div2 0 1832 #define anatx_IndLaneModes_SWSDR_div1 1 1833 #define anatx_IndLaneModes_DWSDR_div2 2 1834 #define anatx_IndLaneModes_DWSDR_div1 3 1835 1836 /**************************************************************************** 1837 * Enums: anatx_prbsSelect 1838 */ 1839 #define anatx_prbsSelect_prbs7 0 1840 #define anatx_prbsSelect_prbs15 1 1841 #define anatx_prbsSelect_prbs23 2 1842 #define anatx_prbsSelect_prbs31 3 1843 1844 /**************************************************************************** 1845 * Enums: anatx_vcoDivider 1846 */ 1847 #define anatx_vcoDivider_div32 0 1848 #define anatx_vcoDivider_div36 1 1849 #define anatx_vcoDivider_div40 2 1850 #define anatx_vcoDivider_div42 3 1851 #define anatx_vcoDivider_div48 4 1852 #define anatx_vcoDivider_div50 5 1853 #define anatx_vcoDivider_div52 6 1854 #define anatx_vcoDivider_div54 7 1855 #define anatx_vcoDivider_div60 8 1856 #define anatx_vcoDivider_div64 9 1857 #define anatx_vcoDivider_div66 10 1858 #define anatx_vcoDivider_div68 11 1859 #define anatx_vcoDivider_div70 12 1860 #define anatx_vcoDivider_div80 13 1861 #define anatx_vcoDivider_div92 14 1862 #define anatx_vcoDivider_div100 15 1863 1864 /**************************************************************************** 1865 * Enums: anatx_refClkSelect 1866 */ 1867 #define anatx_refClkSelect_clk_25MHz 0 1868 #define anatx_refClkSelect_clk_100MHz 1 1869 #define anatx_refClkSelect_clk_125MHz 2 1870 #define anatx_refClkSelect_clk_156p25MHz 3 1871 #define anatx_refClkSelect_clk_187p5MHz 4 1872 #define anatx_refClkSelect_clk_161p25Mhz 5 1873 #define anatx_refClkSelect_clk_50Mhz 6 1874 #define anatx_refClkSelect_clk_106p25Mhz 7 1875 1876 /**************************************************************************** 1877 * Enums: anatx_aerMMDdevTypeSelect 1878 */ 1879 #define anatx_aerMMDdevTypeSelect_combo_core 0 1880 #define anatx_aerMMDdevTypeSelect_PMA_PMD 1 1881 #define anatx_aerMMDdevTypeSelect_PCS 3 1882 #define anatx_aerMMDdevTypeSelect_PHY 4 1883 #define anatx_aerMMDdevTypeSelect_DTE 5 1884 #define anatx_aerMMDdevTypeSelect_CL73_AN 7 1885 1886 /**************************************************************************** 1887 * Enums: anatx_aerMMDportSelect 1888 */ 1889 #define anatx_aerMMDportSelect_ln0 0 1890 #define anatx_aerMMDportSelect_ln1 1 1891 #define anatx_aerMMDportSelect_ln2 2 1892 #define anatx_aerMMDportSelect_ln3 3 1893 #define anatx_aerMMDportSelect_BCST_ln0_1_2_3 511 1894 #define anatx_aerMMDportSelect_BCST_ln0_1 512 1895 #define anatx_aerMMDportSelect_BCST_ln2_3 513 1896 1897 /**************************************************************************** 1898 * Enums: anatx_firmwareModeSelect 1899 */ 1900 #define anatx_firmwareModeSelect_DEFAULT 0 1901 #define anatx_firmwareModeSelect_SFP_OPT_LR 1 1902 #define anatx_firmwareModeSelect_SFP_DAC 2 1903 #define anatx_firmwareModeSelect_XLAUI 3 1904 #define anatx_firmwareModeSelect_LONG_CH_6G 4 1905 1906 /**************************************************************************** 1907 * Enums: anatx_tempIdxSelect 1908 */ 1909 #define anatx_tempIdxSelect_LTE__22p9C 15 1910 #define anatx_tempIdxSelect_LTE__12p6C 14 1911 #define anatx_tempIdxSelect_LTE__3p0C 13 1912 #define anatx_tempIdxSelect_LTE_6p7C 12 1913 #define anatx_tempIdxSelect_LTE_16p4C 11 1914 #define anatx_tempIdxSelect_LTE_26p6C 10 1915 #define anatx_tempIdxSelect_LTE_36p3C 9 1916 #define anatx_tempIdxSelect_LTE_46p0C 8 1917 #define anatx_tempIdxSelect_LTE_56p2C 7 1918 #define anatx_tempIdxSelect_LTE_65p9C 6 1919 #define anatx_tempIdxSelect_LTE_75p6C 5 1920 #define anatx_tempIdxSelect_LTE_85p3C 4 1921 #define anatx_tempIdxSelect_LTE_95p5C 3 1922 #define anatx_tempIdxSelect_LTE_105p2C 2 1923 #define anatx_tempIdxSelect_LTE_114p9C 1 1924 #define anatx_tempIdxSelect_LTE_125p1C 0 1925 1926 /**************************************************************************** 1927 * Enums: cl73_cl73_fsm 1928 */ 1929 #define cl73_cl73_fsm_AN_ENABLE 1 1930 #define cl73_cl73_fsm_TRANSMIT_DISABLE 2 1931 #define cl73_cl73_fsm_ABILITY_DETECT 4 1932 #define cl73_cl73_fsm_ACKNOWLEDGE_DETECT 8 1933 #define cl73_cl73_fsm_COMPLETE_ACKNOWLEDGE 16 1934 #define cl73_cl73_fsm_NEXT_PAGE_WAIT 32 1935 #define cl73_cl73_fsm_AN_GOOD_CHECK 64 1936 #define cl73_cl73_fsm_AN_GOOD 128 1937 #define cl73_cl73_fsm_LINK_STATUS_CHECK 256 1938 #define cl73_cl73_fsm_PARALLEL_DETECTION_FAULT 512 1939 #define cl73_cl73_fsm_AN_GOOD_CHECK_BAM37 1024 1940 #define cl73_cl73_fsm_TRANSMIT_DISABLE_BAM37 2048 1941 1942 /**************************************************************************** 1943 * Enums: digital_cl36TxEEEStates_l 1944 */ 1945 #define digital_cl36TxEEEStates_l_TX_REFRESH 8 1946 #define digital_cl36TxEEEStates_l_TX_QUIET 4 1947 #define digital_cl36TxEEEStates_l_TX_SLEEP 2 1948 #define digital_cl36TxEEEStates_l_TX_ACTIVE 1 1949 1950 /**************************************************************************** 1951 * Enums: digital_cl36TxEEEStates_c 1952 */ 1953 #define digital_cl36TxEEEStates_c_TX_REFRESH 3 1954 #define digital_cl36TxEEEStates_c_TX_QUIET 2 1955 #define digital_cl36TxEEEStates_c_TX_SLEEP 1 1956 #define digital_cl36TxEEEStates_c_TX_ACTIVE 0 1957 1958 /**************************************************************************** 1959 * Enums: digital_cl49TxEEEStates_l 1960 */ 1961 #define digital_cl49TxEEEStates_l_SCR_RESET_2 64 1962 #define digital_cl49TxEEEStates_l_SCR_RESET_1 32 1963 #define digital_cl49TxEEEStates_l_TX_WAKE 16 1964 #define digital_cl49TxEEEStates_l_TX_REFRESH 8 1965 #define digital_cl49TxEEEStates_l_TX_QUIET 4 1966 #define digital_cl49TxEEEStates_l_TX_SLEEP 2 1967 #define digital_cl49TxEEEStates_l_TX_ACTIVE 1 1968 1969 /**************************************************************************** 1970 * Enums: digital_cl49TxEEEStates_c 1971 */ 1972 #define digital_cl49TxEEEStates_c_SCR_RESET_2 6 1973 #define digital_cl49TxEEEStates_c_SCR_RESET_1 5 1974 #define digital_cl49TxEEEStates_c_TX_WAKE 4 1975 #define digital_cl49TxEEEStates_c_TX_REFRESH 3 1976 #define digital_cl49TxEEEStates_c_TX_QUIET 2 1977 #define digital_cl49TxEEEStates_c_TX_SLEEP 1 1978 #define digital_cl49TxEEEStates_c_TX_ACTIVE 0 1979 1980 /**************************************************************************** 1981 * Enums: digital_cl36RxEEEStates_l 1982 */ 1983 #define digital_cl36RxEEEStates_l_RX_LINK_FAIL 32 1984 #define digital_cl36RxEEEStates_l_RX_WTF 16 1985 #define digital_cl36RxEEEStates_l_RX_WAKE 8 1986 #define digital_cl36RxEEEStates_l_RX_QUIET 4 1987 #define digital_cl36RxEEEStates_l_RX_SLEEP 2 1988 #define digital_cl36RxEEEStates_l_RX_ACTIVE 1 1989 1990 /**************************************************************************** 1991 * Enums: digital_cl36RxEEEStates_c 1992 */ 1993 #define digital_cl36RxEEEStates_c_RX_LINK_FAIL 5 1994 #define digital_cl36RxEEEStates_c_RX_WTF 4 1995 #define digital_cl36RxEEEStates_c_RX_WAKE 3 1996 #define digital_cl36RxEEEStates_c_RX_QUIET 2 1997 #define digital_cl36RxEEEStates_c_RX_SLEEP 1 1998 #define digital_cl36RxEEEStates_c_RX_ACTIVE 0 1999 2000 /**************************************************************************** 2001 * Enums: digital_cl49RxEEEStates_l 2002 */ 2003 #define digital_cl49RxEEEStates_l_RX_LINK_FAIL 32 2004 #define digital_cl49RxEEEStates_l_RX_WTF 16 2005 #define digital_cl49RxEEEStates_l_RX_WAKE 8 2006 #define digital_cl49RxEEEStates_l_RX_QUIET 4 2007 #define digital_cl49RxEEEStates_l_RX_SLEEP 2 2008 #define digital_cl49RxEEEStates_l_RX_ACTIVE 1 2009 2010 /**************************************************************************** 2011 * Enums: digital_cl49RxEEEStates_c 2012 */ 2013 #define digital_cl49RxEEEStates_c_RX_LINK_FAIL 5 2014 #define digital_cl49RxEEEStates_c_RX_WTF 4 2015 #define digital_cl49RxEEEStates_c_RX_WAKE 3 2016 #define digital_cl49RxEEEStates_c_RX_QUIET 2 2017 #define digital_cl49RxEEEStates_c_RX_SLEEP 1 2018 #define digital_cl49RxEEEStates_c_RX_ACTIVE 0 2019 2020 /**************************************************************************** 2021 * Enums: digital_cl48TxEEEStates_l 2022 */ 2023 #define digital_cl48TxEEEStates_l_TX_REFRESH 8 2024 #define digital_cl48TxEEEStates_l_TX_QUIET 4 2025 #define digital_cl48TxEEEStates_l_TX_SLEEP 2 2026 #define digital_cl48TxEEEStates_l_TX_ACTIVE 1 2027 2028 /**************************************************************************** 2029 * Enums: digital_cl48TxEEEStates_c 2030 */ 2031 #define digital_cl48TxEEEStates_c_TX_REFRESH 3 2032 #define digital_cl48TxEEEStates_c_TX_QUIET 2 2033 #define digital_cl48TxEEEStates_c_TX_SLEEP 1 2034 #define digital_cl48TxEEEStates_c_TX_ACTIVE 0 2035 2036 /**************************************************************************** 2037 * Enums: digital_cl48RxEEEStates_l 2038 */ 2039 #define digital_cl48RxEEEStates_l_RX_LINK_FAIL 32 2040 #define digital_cl48RxEEEStates_l_RX_WAKE 16 2041 #define digital_cl48RxEEEStates_l_RX_QUIET 8 2042 #define digital_cl48RxEEEStates_l_RX_DEACT 4 2043 #define digital_cl48RxEEEStates_l_RX_SLEEP 2 2044 #define digital_cl48RxEEEStates_l_RX_ACTIVE 1 2045 2046 /**************************************************************************** 2047 * Enums: digital_cl48RxEEEStates_c 2048 */ 2049 #define digital_cl48RxEEEStates_c_RX_LINK_FAIL 5 2050 #define digital_cl48RxEEEStates_c_RX_WAKE 4 2051 #define digital_cl48RxEEEStates_c_RX_QUIET 3 2052 #define digital_cl48RxEEEStates_c_RX_DEACT 2 2053 #define digital_cl48RxEEEStates_c_RX_SLEEP 1 2054 #define digital_cl48RxEEEStates_c_RX_ACTIVE 0 2055 2056 /**************************************************************************** 2057 * Enums: digital_IQP_Options 2058 */ 2059 #define digital_IQP_Options_i50uA 0 2060 #define digital_IQP_Options_i100uA 1 2061 #define digital_IQP_Options_i150uA 2 2062 #define digital_IQP_Options_i200uA 3 2063 #define digital_IQP_Options_i250uA 4 2064 #define digital_IQP_Options_i300uA 5 2065 #define digital_IQP_Options_i350uA 6 2066 #define digital_IQP_Options_i400uA 7 2067 #define digital_IQP_Options_i450uA 8 2068 #define digital_IQP_Options_i500uA 9 2069 #define digital_IQP_Options_i550uA 10 2070 #define digital_IQP_Options_i600uA 11 2071 #define digital_IQP_Options_i650uA 12 2072 #define digital_IQP_Options_i700uA 13 2073 #define digital_IQP_Options_i750uA 14 2074 #define digital_IQP_Options_i800uA 15 2075 2076 /**************************************************************************** 2077 * Enums: digital_IDriver_Options 2078 */ 2079 #define digital_IDriver_Options_v680mV 0 2080 #define digital_IDriver_Options_v730mV 1 2081 #define digital_IDriver_Options_v780mV 2 2082 #define digital_IDriver_Options_v830mV 3 2083 #define digital_IDriver_Options_v880mV 4 2084 #define digital_IDriver_Options_v930mV 5 2085 #define digital_IDriver_Options_v980mV 6 2086 #define digital_IDriver_Options_v1010mV 7 2087 #define digital_IDriver_Options_v1040mV 8 2088 #define digital_IDriver_Options_v1060mV 9 2089 #define digital_IDriver_Options_v1070mV 10 2090 #define digital_IDriver_Options_v1080mV 11 2091 #define digital_IDriver_Options_v1085mV 12 2092 #define digital_IDriver_Options_v1090mV 13 2093 #define digital_IDriver_Options_v1095mV 14 2094 #define digital_IDriver_Options_v1100mV 15 2095 2096 /**************************************************************************** 2097 * Enums: digital_operationModes 2098 */ 2099 #define digital_operationModes_XGXS 0 2100 #define digital_operationModes_XGXG_nCC 1 2101 #define digital_operationModes_Indlane_OS8 4 2102 #define digital_operationModes_IndLane_OS5 5 2103 #define digital_operationModes_PCI 7 2104 #define digital_operationModes_XGXS_nLQ 8 2105 #define digital_operationModes_XGXS_nLQnCC 9 2106 #define digital_operationModes_PBypass 10 2107 #define digital_operationModes_PBypass_nDSK 11 2108 #define digital_operationModes_ComboCoreMode 12 2109 #define digital_operationModes_Clocks_off 15 2110 2111 /**************************************************************************** 2112 * Enums: digital_actualSpeeds 2113 */ 2114 #define digital_actualSpeeds_dr_10M 0 2115 #define digital_actualSpeeds_dr_100M 1 2116 #define digital_actualSpeeds_dr_1G 2 2117 #define digital_actualSpeeds_dr_2p5G 3 2118 #define digital_actualSpeeds_dr_5G_X4 4 2119 #define digital_actualSpeeds_dr_6G_X4 5 2120 #define digital_actualSpeeds_dr_10G_HiG 6 2121 #define digital_actualSpeeds_dr_10G_CX4 7 2122 #define digital_actualSpeeds_dr_12G_HiG 8 2123 #define digital_actualSpeeds_dr_12p5G_X4 9 2124 #define digital_actualSpeeds_dr_13G_X4 10 2125 #define digital_actualSpeeds_dr_15G_X4 11 2126 #define digital_actualSpeeds_dr_16G_X4 12 2127 #define digital_actualSpeeds_dr_1G_KX 13 2128 #define digital_actualSpeeds_dr_10G_KX4 14 2129 #define digital_actualSpeeds_dr_10G_KR 15 2130 #define digital_actualSpeeds_dr_5G 16 2131 #define digital_actualSpeeds_dr_6p4G 17 2132 #define digital_actualSpeeds_dr_20G_X4 18 2133 #define digital_actualSpeeds_dr_21G_X4 19 2134 #define digital_actualSpeeds_dr_25G_X4 20 2135 #define digital_actualSpeeds_dr_10G_HiG_DXGXS 21 2136 #define digital_actualSpeeds_dr_10G_DXGXS 22 2137 #define digital_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2138 #define digital_actualSpeeds_dr_10p5G_DXGXS 24 2139 #define digital_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2140 #define digital_actualSpeeds_dr_12p773G_DXGXS 26 2141 #define digital_actualSpeeds_dr_10G_XFI 27 2142 #define digital_actualSpeeds_dr_40G 28 2143 #define digital_actualSpeeds_dr_20G_HiG_DXGXS 29 2144 #define digital_actualSpeeds_dr_20G_DXGXS 30 2145 #define digital_actualSpeeds_dr_10G_SFI 31 2146 #define digital_actualSpeeds_dr_31p5G 32 2147 #define digital_actualSpeeds_dr_32p7G 33 2148 #define digital_actualSpeeds_dr_20G_SCR 34 2149 #define digital_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2150 #define digital_actualSpeeds_dr_10G_DXGXS_SCR 36 2151 #define digital_actualSpeeds_dr_12G_R2 37 2152 #define digital_actualSpeeds_dr_10G_X2 38 2153 #define digital_actualSpeeds_dr_40G_KR4 39 2154 #define digital_actualSpeeds_dr_40G_CR4 40 2155 #define digital_actualSpeeds_dr_100G_CR10 41 2156 #define digital_actualSpeeds_dr_15p75G_DXGXS 44 2157 #define digital_actualSpeeds_dr_20G_KR2 57 2158 #define digital_actualSpeeds_dr_20G_CR2 58 2159 2160 /**************************************************************************** 2161 * Enums: digital_actualSpeedsMisc1 2162 */ 2163 #define digital_actualSpeedsMisc1_dr_2500BRCM_X1 16 2164 #define digital_actualSpeedsMisc1_dr_5000BRCM_X4 17 2165 #define digital_actualSpeedsMisc1_dr_6000BRCM_X4 18 2166 #define digital_actualSpeedsMisc1_dr_10GHiGig_X4 19 2167 #define digital_actualSpeedsMisc1_dr_10GBASE_CX4 20 2168 #define digital_actualSpeedsMisc1_dr_12GHiGig_X4 21 2169 #define digital_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2170 #define digital_actualSpeedsMisc1_dr_13GHiGig_X4 23 2171 #define digital_actualSpeedsMisc1_dr_15GHiGig_X4 24 2172 #define digital_actualSpeedsMisc1_dr_16GHiGig_X4 25 2173 #define digital_actualSpeedsMisc1_dr_5000BRCM_X1 26 2174 #define digital_actualSpeedsMisc1_dr_6363BRCM_X1 27 2175 #define digital_actualSpeedsMisc1_dr_20GHiGig_X4 28 2176 #define digital_actualSpeedsMisc1_dr_21GHiGig_X4 29 2177 #define digital_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2178 #define digital_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2179 2180 /**************************************************************************** 2181 * Enums: digital_IndLaneModes 2182 */ 2183 #define digital_IndLaneModes_SWSDR_div2 0 2184 #define digital_IndLaneModes_SWSDR_div1 1 2185 #define digital_IndLaneModes_DWSDR_div2 2 2186 #define digital_IndLaneModes_DWSDR_div1 3 2187 2188 /**************************************************************************** 2189 * Enums: digital_prbsSelect 2190 */ 2191 #define digital_prbsSelect_prbs7 0 2192 #define digital_prbsSelect_prbs15 1 2193 #define digital_prbsSelect_prbs23 2 2194 #define digital_prbsSelect_prbs31 3 2195 2196 /**************************************************************************** 2197 * Enums: digital_vcoDivider 2198 */ 2199 #define digital_vcoDivider_div32 0 2200 #define digital_vcoDivider_div36 1 2201 #define digital_vcoDivider_div40 2 2202 #define digital_vcoDivider_div42 3 2203 #define digital_vcoDivider_div48 4 2204 #define digital_vcoDivider_div50 5 2205 #define digital_vcoDivider_div52 6 2206 #define digital_vcoDivider_div54 7 2207 #define digital_vcoDivider_div60 8 2208 #define digital_vcoDivider_div64 9 2209 #define digital_vcoDivider_div66 10 2210 #define digital_vcoDivider_div68 11 2211 #define digital_vcoDivider_div70 12 2212 #define digital_vcoDivider_div80 13 2213 #define digital_vcoDivider_div92 14 2214 #define digital_vcoDivider_div100 15 2215 2216 /**************************************************************************** 2217 * Enums: digital_refClkSelect 2218 */ 2219 #define digital_refClkSelect_clk_25MHz 0 2220 #define digital_refClkSelect_clk_100MHz 1 2221 #define digital_refClkSelect_clk_125MHz 2 2222 #define digital_refClkSelect_clk_156p25MHz 3 2223 #define digital_refClkSelect_clk_187p5MHz 4 2224 #define digital_refClkSelect_clk_161p25Mhz 5 2225 #define digital_refClkSelect_clk_50Mhz 6 2226 #define digital_refClkSelect_clk_106p25Mhz 7 2227 2228 /**************************************************************************** 2229 * Enums: digital_aerMMDdevTypeSelect 2230 */ 2231 #define digital_aerMMDdevTypeSelect_combo_core 0 2232 #define digital_aerMMDdevTypeSelect_PMA_PMD 1 2233 #define digital_aerMMDdevTypeSelect_PCS 3 2234 #define digital_aerMMDdevTypeSelect_PHY 4 2235 #define digital_aerMMDdevTypeSelect_DTE 5 2236 #define digital_aerMMDdevTypeSelect_CL73_AN 7 2237 2238 /**************************************************************************** 2239 * Enums: digital_aerMMDportSelect 2240 */ 2241 #define digital_aerMMDportSelect_ln0 0 2242 #define digital_aerMMDportSelect_ln1 1 2243 #define digital_aerMMDportSelect_ln2 2 2244 #define digital_aerMMDportSelect_ln3 3 2245 #define digital_aerMMDportSelect_BCST_ln0_1_2_3 511 2246 #define digital_aerMMDportSelect_BCST_ln0_1 512 2247 #define digital_aerMMDportSelect_BCST_ln2_3 513 2248 2249 /**************************************************************************** 2250 * Enums: digital_firmwareModeSelect 2251 */ 2252 #define digital_firmwareModeSelect_DEFAULT 0 2253 #define digital_firmwareModeSelect_SFP_OPT_LR 1 2254 #define digital_firmwareModeSelect_SFP_DAC 2 2255 #define digital_firmwareModeSelect_XLAUI 3 2256 #define digital_firmwareModeSelect_LONG_CH_6G 4 2257 2258 /**************************************************************************** 2259 * Enums: digital_tempIdxSelect 2260 */ 2261 #define digital_tempIdxSelect_LTE__22p9C 15 2262 #define digital_tempIdxSelect_LTE__12p6C 14 2263 #define digital_tempIdxSelect_LTE__3p0C 13 2264 #define digital_tempIdxSelect_LTE_6p7C 12 2265 #define digital_tempIdxSelect_LTE_16p4C 11 2266 #define digital_tempIdxSelect_LTE_26p6C 10 2267 #define digital_tempIdxSelect_LTE_36p3C 9 2268 #define digital_tempIdxSelect_LTE_46p0C 8 2269 #define digital_tempIdxSelect_LTE_56p2C 7 2270 #define digital_tempIdxSelect_LTE_65p9C 6 2271 #define digital_tempIdxSelect_LTE_75p6C 5 2272 #define digital_tempIdxSelect_LTE_85p3C 4 2273 #define digital_tempIdxSelect_LTE_95p5C 3 2274 #define digital_tempIdxSelect_LTE_105p2C 2 2275 #define digital_tempIdxSelect_LTE_114p9C 1 2276 #define digital_tempIdxSelect_LTE_125p1C 0 2277 2278 /**************************************************************************** 2279 * Enums: digital5_cl36TxEEEStates_l 2280 */ 2281 #define digital5_cl36TxEEEStates_l_TX_REFRESH 8 2282 #define digital5_cl36TxEEEStates_l_TX_QUIET 4 2283 #define digital5_cl36TxEEEStates_l_TX_SLEEP 2 2284 #define digital5_cl36TxEEEStates_l_TX_ACTIVE 1 2285 2286 /**************************************************************************** 2287 * Enums: digital5_cl36TxEEEStates_c 2288 */ 2289 #define digital5_cl36TxEEEStates_c_TX_REFRESH 3 2290 #define digital5_cl36TxEEEStates_c_TX_QUIET 2 2291 #define digital5_cl36TxEEEStates_c_TX_SLEEP 1 2292 #define digital5_cl36TxEEEStates_c_TX_ACTIVE 0 2293 2294 /**************************************************************************** 2295 * Enums: digital5_cl49TxEEEStates_l 2296 */ 2297 #define digital5_cl49TxEEEStates_l_SCR_RESET_2 64 2298 #define digital5_cl49TxEEEStates_l_SCR_RESET_1 32 2299 #define digital5_cl49TxEEEStates_l_TX_WAKE 16 2300 #define digital5_cl49TxEEEStates_l_TX_REFRESH 8 2301 #define digital5_cl49TxEEEStates_l_TX_QUIET 4 2302 #define digital5_cl49TxEEEStates_l_TX_SLEEP 2 2303 #define digital5_cl49TxEEEStates_l_TX_ACTIVE 1 2304 2305 /**************************************************************************** 2306 * Enums: digital5_cl49TxEEEStates_c 2307 */ 2308 #define digital5_cl49TxEEEStates_c_SCR_RESET_2 6 2309 #define digital5_cl49TxEEEStates_c_SCR_RESET_1 5 2310 #define digital5_cl49TxEEEStates_c_TX_WAKE 4 2311 #define digital5_cl49TxEEEStates_c_TX_REFRESH 3 2312 #define digital5_cl49TxEEEStates_c_TX_QUIET 2 2313 #define digital5_cl49TxEEEStates_c_TX_SLEEP 1 2314 #define digital5_cl49TxEEEStates_c_TX_ACTIVE 0 2315 2316 /**************************************************************************** 2317 * Enums: digital5_cl36RxEEEStates_l 2318 */ 2319 #define digital5_cl36RxEEEStates_l_RX_LINK_FAIL 32 2320 #define digital5_cl36RxEEEStates_l_RX_WTF 16 2321 #define digital5_cl36RxEEEStates_l_RX_WAKE 8 2322 #define digital5_cl36RxEEEStates_l_RX_QUIET 4 2323 #define digital5_cl36RxEEEStates_l_RX_SLEEP 2 2324 #define digital5_cl36RxEEEStates_l_RX_ACTIVE 1 2325 2326 /**************************************************************************** 2327 * Enums: digital5_cl36RxEEEStates_c 2328 */ 2329 #define digital5_cl36RxEEEStates_c_RX_LINK_FAIL 5 2330 #define digital5_cl36RxEEEStates_c_RX_WTF 4 2331 #define digital5_cl36RxEEEStates_c_RX_WAKE 3 2332 #define digital5_cl36RxEEEStates_c_RX_QUIET 2 2333 #define digital5_cl36RxEEEStates_c_RX_SLEEP 1 2334 #define digital5_cl36RxEEEStates_c_RX_ACTIVE 0 2335 2336 /**************************************************************************** 2337 * Enums: digital5_cl49RxEEEStates_l 2338 */ 2339 #define digital5_cl49RxEEEStates_l_RX_LINK_FAIL 32 2340 #define digital5_cl49RxEEEStates_l_RX_WTF 16 2341 #define digital5_cl49RxEEEStates_l_RX_WAKE 8 2342 #define digital5_cl49RxEEEStates_l_RX_QUIET 4 2343 #define digital5_cl49RxEEEStates_l_RX_SLEEP 2 2344 #define digital5_cl49RxEEEStates_l_RX_ACTIVE 1 2345 2346 /**************************************************************************** 2347 * Enums: digital5_cl49RxEEEStates_c 2348 */ 2349 #define digital5_cl49RxEEEStates_c_RX_LINK_FAIL 5 2350 #define digital5_cl49RxEEEStates_c_RX_WTF 4 2351 #define digital5_cl49RxEEEStates_c_RX_WAKE 3 2352 #define digital5_cl49RxEEEStates_c_RX_QUIET 2 2353 #define digital5_cl49RxEEEStates_c_RX_SLEEP 1 2354 #define digital5_cl49RxEEEStates_c_RX_ACTIVE 0 2355 2356 /**************************************************************************** 2357 * Enums: digital5_cl48TxEEEStates_l 2358 */ 2359 #define digital5_cl48TxEEEStates_l_TX_REFRESH 8 2360 #define digital5_cl48TxEEEStates_l_TX_QUIET 4 2361 #define digital5_cl48TxEEEStates_l_TX_SLEEP 2 2362 #define digital5_cl48TxEEEStates_l_TX_ACTIVE 1 2363 2364 /**************************************************************************** 2365 * Enums: digital5_cl48TxEEEStates_c 2366 */ 2367 #define digital5_cl48TxEEEStates_c_TX_REFRESH 3 2368 #define digital5_cl48TxEEEStates_c_TX_QUIET 2 2369 #define digital5_cl48TxEEEStates_c_TX_SLEEP 1 2370 #define digital5_cl48TxEEEStates_c_TX_ACTIVE 0 2371 2372 /**************************************************************************** 2373 * Enums: digital5_cl48RxEEEStates_l 2374 */ 2375 #define digital5_cl48RxEEEStates_l_RX_LINK_FAIL 32 2376 #define digital5_cl48RxEEEStates_l_RX_WAKE 16 2377 #define digital5_cl48RxEEEStates_l_RX_QUIET 8 2378 #define digital5_cl48RxEEEStates_l_RX_DEACT 4 2379 #define digital5_cl48RxEEEStates_l_RX_SLEEP 2 2380 #define digital5_cl48RxEEEStates_l_RX_ACTIVE 1 2381 2382 /**************************************************************************** 2383 * Enums: digital5_cl48RxEEEStates_c 2384 */ 2385 #define digital5_cl48RxEEEStates_c_RX_LINK_FAIL 5 2386 #define digital5_cl48RxEEEStates_c_RX_WAKE 4 2387 #define digital5_cl48RxEEEStates_c_RX_QUIET 3 2388 #define digital5_cl48RxEEEStates_c_RX_DEACT 2 2389 #define digital5_cl48RxEEEStates_c_RX_SLEEP 1 2390 #define digital5_cl48RxEEEStates_c_RX_ACTIVE 0 2391 2392 /**************************************************************************** 2393 * Enums: digital5_IQP_Options 2394 */ 2395 #define digital5_IQP_Options_i50uA 0 2396 #define digital5_IQP_Options_i100uA 1 2397 #define digital5_IQP_Options_i150uA 2 2398 #define digital5_IQP_Options_i200uA 3 2399 #define digital5_IQP_Options_i250uA 4 2400 #define digital5_IQP_Options_i300uA 5 2401 #define digital5_IQP_Options_i350uA 6 2402 #define digital5_IQP_Options_i400uA 7 2403 #define digital5_IQP_Options_i450uA 8 2404 #define digital5_IQP_Options_i500uA 9 2405 #define digital5_IQP_Options_i550uA 10 2406 #define digital5_IQP_Options_i600uA 11 2407 #define digital5_IQP_Options_i650uA 12 2408 #define digital5_IQP_Options_i700uA 13 2409 #define digital5_IQP_Options_i750uA 14 2410 #define digital5_IQP_Options_i800uA 15 2411 2412 /**************************************************************************** 2413 * Enums: digital5_IDriver_Options 2414 */ 2415 #define digital5_IDriver_Options_v680mV 0 2416 #define digital5_IDriver_Options_v730mV 1 2417 #define digital5_IDriver_Options_v780mV 2 2418 #define digital5_IDriver_Options_v830mV 3 2419 #define digital5_IDriver_Options_v880mV 4 2420 #define digital5_IDriver_Options_v930mV 5 2421 #define digital5_IDriver_Options_v980mV 6 2422 #define digital5_IDriver_Options_v1010mV 7 2423 #define digital5_IDriver_Options_v1040mV 8 2424 #define digital5_IDriver_Options_v1060mV 9 2425 #define digital5_IDriver_Options_v1070mV 10 2426 #define digital5_IDriver_Options_v1080mV 11 2427 #define digital5_IDriver_Options_v1085mV 12 2428 #define digital5_IDriver_Options_v1090mV 13 2429 #define digital5_IDriver_Options_v1095mV 14 2430 #define digital5_IDriver_Options_v1100mV 15 2431 2432 /**************************************************************************** 2433 * Enums: digital5_operationModes 2434 */ 2435 #define digital5_operationModes_XGXS 0 2436 #define digital5_operationModes_XGXG_nCC 1 2437 #define digital5_operationModes_Indlane_OS8 4 2438 #define digital5_operationModes_IndLane_OS5 5 2439 #define digital5_operationModes_PCI 7 2440 #define digital5_operationModes_XGXS_nLQ 8 2441 #define digital5_operationModes_XGXS_nLQnCC 9 2442 #define digital5_operationModes_PBypass 10 2443 #define digital5_operationModes_PBypass_nDSK 11 2444 #define digital5_operationModes_ComboCoreMode 12 2445 #define digital5_operationModes_Clocks_off 15 2446 2447 /**************************************************************************** 2448 * Enums: digital5_actualSpeeds 2449 */ 2450 #define digital5_actualSpeeds_dr_10M 0 2451 #define digital5_actualSpeeds_dr_100M 1 2452 #define digital5_actualSpeeds_dr_1G 2 2453 #define digital5_actualSpeeds_dr_2p5G 3 2454 #define digital5_actualSpeeds_dr_5G_X4 4 2455 #define digital5_actualSpeeds_dr_6G_X4 5 2456 #define digital5_actualSpeeds_dr_10G_HiG 6 2457 #define digital5_actualSpeeds_dr_10G_CX4 7 2458 #define digital5_actualSpeeds_dr_12G_HiG 8 2459 #define digital5_actualSpeeds_dr_12p5G_X4 9 2460 #define digital5_actualSpeeds_dr_13G_X4 10 2461 #define digital5_actualSpeeds_dr_15G_X4 11 2462 #define digital5_actualSpeeds_dr_16G_X4 12 2463 #define digital5_actualSpeeds_dr_1G_KX 13 2464 #define digital5_actualSpeeds_dr_10G_KX4 14 2465 #define digital5_actualSpeeds_dr_10G_KR 15 2466 #define digital5_actualSpeeds_dr_5G 16 2467 #define digital5_actualSpeeds_dr_6p4G 17 2468 #define digital5_actualSpeeds_dr_20G_X4 18 2469 #define digital5_actualSpeeds_dr_21G_X4 19 2470 #define digital5_actualSpeeds_dr_25G_X4 20 2471 #define digital5_actualSpeeds_dr_10G_HiG_DXGXS 21 2472 #define digital5_actualSpeeds_dr_10G_DXGXS 22 2473 #define digital5_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2474 #define digital5_actualSpeeds_dr_10p5G_DXGXS 24 2475 #define digital5_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2476 #define digital5_actualSpeeds_dr_12p773G_DXGXS 26 2477 #define digital5_actualSpeeds_dr_10G_XFI 27 2478 #define digital5_actualSpeeds_dr_40G 28 2479 #define digital5_actualSpeeds_dr_20G_HiG_DXGXS 29 2480 #define digital5_actualSpeeds_dr_20G_DXGXS 30 2481 #define digital5_actualSpeeds_dr_10G_SFI 31 2482 #define digital5_actualSpeeds_dr_31p5G 32 2483 #define digital5_actualSpeeds_dr_32p7G 33 2484 #define digital5_actualSpeeds_dr_20G_SCR 34 2485 #define digital5_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2486 #define digital5_actualSpeeds_dr_10G_DXGXS_SCR 36 2487 #define digital5_actualSpeeds_dr_12G_R2 37 2488 #define digital5_actualSpeeds_dr_10G_X2 38 2489 #define digital5_actualSpeeds_dr_40G_KR4 39 2490 #define digital5_actualSpeeds_dr_40G_CR4 40 2491 #define digital5_actualSpeeds_dr_100G_CR10 41 2492 #define digital5_actualSpeeds_dr_15p75G_DXGXS 44 2493 #define digital5_actualSpeeds_dr_20G_KR2 57 2494 #define digital5_actualSpeeds_dr_20G_CR2 58 2495 2496 /**************************************************************************** 2497 * Enums: digital5_actualSpeedsMisc1 2498 */ 2499 #define digital5_actualSpeedsMisc1_dr_2500BRCM_X1 16 2500 #define digital5_actualSpeedsMisc1_dr_5000BRCM_X4 17 2501 #define digital5_actualSpeedsMisc1_dr_6000BRCM_X4 18 2502 #define digital5_actualSpeedsMisc1_dr_10GHiGig_X4 19 2503 #define digital5_actualSpeedsMisc1_dr_10GBASE_CX4 20 2504 #define digital5_actualSpeedsMisc1_dr_12GHiGig_X4 21 2505 #define digital5_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2506 #define digital5_actualSpeedsMisc1_dr_13GHiGig_X4 23 2507 #define digital5_actualSpeedsMisc1_dr_15GHiGig_X4 24 2508 #define digital5_actualSpeedsMisc1_dr_16GHiGig_X4 25 2509 #define digital5_actualSpeedsMisc1_dr_5000BRCM_X1 26 2510 #define digital5_actualSpeedsMisc1_dr_6363BRCM_X1 27 2511 #define digital5_actualSpeedsMisc1_dr_20GHiGig_X4 28 2512 #define digital5_actualSpeedsMisc1_dr_21GHiGig_X4 29 2513 #define digital5_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2514 #define digital5_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2515 2516 /**************************************************************************** 2517 * Enums: digital5_IndLaneModes 2518 */ 2519 #define digital5_IndLaneModes_SWSDR_div2 0 2520 #define digital5_IndLaneModes_SWSDR_div1 1 2521 #define digital5_IndLaneModes_DWSDR_div2 2 2522 #define digital5_IndLaneModes_DWSDR_div1 3 2523 2524 /**************************************************************************** 2525 * Enums: digital5_prbsSelect 2526 */ 2527 #define digital5_prbsSelect_prbs7 0 2528 #define digital5_prbsSelect_prbs15 1 2529 #define digital5_prbsSelect_prbs23 2 2530 #define digital5_prbsSelect_prbs31 3 2531 2532 /**************************************************************************** 2533 * Enums: digital5_vcoDivider 2534 */ 2535 #define digital5_vcoDivider_div32 0 2536 #define digital5_vcoDivider_div36 1 2537 #define digital5_vcoDivider_div40 2 2538 #define digital5_vcoDivider_div42 3 2539 #define digital5_vcoDivider_div48 4 2540 #define digital5_vcoDivider_div50 5 2541 #define digital5_vcoDivider_div52 6 2542 #define digital5_vcoDivider_div54 7 2543 #define digital5_vcoDivider_div60 8 2544 #define digital5_vcoDivider_div64 9 2545 #define digital5_vcoDivider_div66 10 2546 #define digital5_vcoDivider_div68 11 2547 #define digital5_vcoDivider_div70 12 2548 #define digital5_vcoDivider_div80 13 2549 #define digital5_vcoDivider_div92 14 2550 #define digital5_vcoDivider_div100 15 2551 2552 /**************************************************************************** 2553 * Enums: digital5_refClkSelect 2554 */ 2555 #define digital5_refClkSelect_clk_25MHz 0 2556 #define digital5_refClkSelect_clk_100MHz 1 2557 #define digital5_refClkSelect_clk_125MHz 2 2558 #define digital5_refClkSelect_clk_156p25MHz 3 2559 #define digital5_refClkSelect_clk_187p5MHz 4 2560 #define digital5_refClkSelect_clk_161p25Mhz 5 2561 #define digital5_refClkSelect_clk_50Mhz 6 2562 #define digital5_refClkSelect_clk_106p25Mhz 7 2563 2564 /**************************************************************************** 2565 * Enums: digital5_aerMMDdevTypeSelect 2566 */ 2567 #define digital5_aerMMDdevTypeSelect_combo_core 0 2568 #define digital5_aerMMDdevTypeSelect_PMA_PMD 1 2569 #define digital5_aerMMDdevTypeSelect_PCS 3 2570 #define digital5_aerMMDdevTypeSelect_PHY 4 2571 #define digital5_aerMMDdevTypeSelect_DTE 5 2572 #define digital5_aerMMDdevTypeSelect_CL73_AN 7 2573 2574 /**************************************************************************** 2575 * Enums: digital5_aerMMDportSelect 2576 */ 2577 #define digital5_aerMMDportSelect_ln0 0 2578 #define digital5_aerMMDportSelect_ln1 1 2579 #define digital5_aerMMDportSelect_ln2 2 2580 #define digital5_aerMMDportSelect_ln3 3 2581 #define digital5_aerMMDportSelect_BCST_ln0_1_2_3 511 2582 #define digital5_aerMMDportSelect_BCST_ln0_1 512 2583 #define digital5_aerMMDportSelect_BCST_ln2_3 513 2584 2585 /**************************************************************************** 2586 * Enums: digital5_firmwareModeSelect 2587 */ 2588 #define digital5_firmwareModeSelect_DEFAULT 0 2589 #define digital5_firmwareModeSelect_SFP_OPT_LR 1 2590 #define digital5_firmwareModeSelect_SFP_DAC 2 2591 #define digital5_firmwareModeSelect_XLAUI 3 2592 #define digital5_firmwareModeSelect_LONG_CH_6G 4 2593 2594 /**************************************************************************** 2595 * Enums: digital5_tempIdxSelect 2596 */ 2597 #define digital5_tempIdxSelect_LTE__22p9C 15 2598 #define digital5_tempIdxSelect_LTE__12p6C 14 2599 #define digital5_tempIdxSelect_LTE__3p0C 13 2600 #define digital5_tempIdxSelect_LTE_6p7C 12 2601 #define digital5_tempIdxSelect_LTE_16p4C 11 2602 #define digital5_tempIdxSelect_LTE_26p6C 10 2603 #define digital5_tempIdxSelect_LTE_36p3C 9 2604 #define digital5_tempIdxSelect_LTE_46p0C 8 2605 #define digital5_tempIdxSelect_LTE_56p2C 7 2606 #define digital5_tempIdxSelect_LTE_65p9C 6 2607 #define digital5_tempIdxSelect_LTE_75p6C 5 2608 #define digital5_tempIdxSelect_LTE_85p3C 4 2609 #define digital5_tempIdxSelect_LTE_95p5C 3 2610 #define digital5_tempIdxSelect_LTE_105p2C 2 2611 #define digital5_tempIdxSelect_LTE_114p9C 1 2612 #define digital5_tempIdxSelect_LTE_125p1C 0 2613 2614 /**************************************************************************** 2615 * Enums: generic_cl36TxEEEStates_l 2616 */ 2617 #define generic_cl36TxEEEStates_l_TX_REFRESH 8 2618 #define generic_cl36TxEEEStates_l_TX_QUIET 4 2619 #define generic_cl36TxEEEStates_l_TX_SLEEP 2 2620 #define generic_cl36TxEEEStates_l_TX_ACTIVE 1 2621 2622 /**************************************************************************** 2623 * Enums: generic_cl36TxEEEStates_c 2624 */ 2625 #define generic_cl36TxEEEStates_c_TX_REFRESH 3 2626 #define generic_cl36TxEEEStates_c_TX_QUIET 2 2627 #define generic_cl36TxEEEStates_c_TX_SLEEP 1 2628 #define generic_cl36TxEEEStates_c_TX_ACTIVE 0 2629 2630 /**************************************************************************** 2631 * Enums: generic_cl49TxEEEStates_l 2632 */ 2633 #define generic_cl49TxEEEStates_l_SCR_RESET_2 64 2634 #define generic_cl49TxEEEStates_l_SCR_RESET_1 32 2635 #define generic_cl49TxEEEStates_l_TX_WAKE 16 2636 #define generic_cl49TxEEEStates_l_TX_REFRESH 8 2637 #define generic_cl49TxEEEStates_l_TX_QUIET 4 2638 #define generic_cl49TxEEEStates_l_TX_SLEEP 2 2639 #define generic_cl49TxEEEStates_l_TX_ACTIVE 1 2640 2641 /**************************************************************************** 2642 * Enums: generic_cl49TxEEEStates_c 2643 */ 2644 #define generic_cl49TxEEEStates_c_SCR_RESET_2 6 2645 #define generic_cl49TxEEEStates_c_SCR_RESET_1 5 2646 #define generic_cl49TxEEEStates_c_TX_WAKE 4 2647 #define generic_cl49TxEEEStates_c_TX_REFRESH 3 2648 #define generic_cl49TxEEEStates_c_TX_QUIET 2 2649 #define generic_cl49TxEEEStates_c_TX_SLEEP 1 2650 #define generic_cl49TxEEEStates_c_TX_ACTIVE 0 2651 2652 /**************************************************************************** 2653 * Enums: generic_cl36RxEEEStates_l 2654 */ 2655 #define generic_cl36RxEEEStates_l_RX_LINK_FAIL 32 2656 #define generic_cl36RxEEEStates_l_RX_WTF 16 2657 #define generic_cl36RxEEEStates_l_RX_WAKE 8 2658 #define generic_cl36RxEEEStates_l_RX_QUIET 4 2659 #define generic_cl36RxEEEStates_l_RX_SLEEP 2 2660 #define generic_cl36RxEEEStates_l_RX_ACTIVE 1 2661 2662 /**************************************************************************** 2663 * Enums: generic_cl36RxEEEStates_c 2664 */ 2665 #define generic_cl36RxEEEStates_c_RX_LINK_FAIL 5 2666 #define generic_cl36RxEEEStates_c_RX_WTF 4 2667 #define generic_cl36RxEEEStates_c_RX_WAKE 3 2668 #define generic_cl36RxEEEStates_c_RX_QUIET 2 2669 #define generic_cl36RxEEEStates_c_RX_SLEEP 1 2670 #define generic_cl36RxEEEStates_c_RX_ACTIVE 0 2671 2672 /**************************************************************************** 2673 * Enums: generic_cl49RxEEEStates_l 2674 */ 2675 #define generic_cl49RxEEEStates_l_RX_LINK_FAIL 32 2676 #define generic_cl49RxEEEStates_l_RX_WTF 16 2677 #define generic_cl49RxEEEStates_l_RX_WAKE 8 2678 #define generic_cl49RxEEEStates_l_RX_QUIET 4 2679 #define generic_cl49RxEEEStates_l_RX_SLEEP 2 2680 #define generic_cl49RxEEEStates_l_RX_ACTIVE 1 2681 2682 /**************************************************************************** 2683 * Enums: generic_cl49RxEEEStates_c 2684 */ 2685 #define generic_cl49RxEEEStates_c_RX_LINK_FAIL 5 2686 #define generic_cl49RxEEEStates_c_RX_WTF 4 2687 #define generic_cl49RxEEEStates_c_RX_WAKE 3 2688 #define generic_cl49RxEEEStates_c_RX_QUIET 2 2689 #define generic_cl49RxEEEStates_c_RX_SLEEP 1 2690 #define generic_cl49RxEEEStates_c_RX_ACTIVE 0 2691 2692 /**************************************************************************** 2693 * Enums: generic_cl48TxEEEStates_l 2694 */ 2695 #define generic_cl48TxEEEStates_l_TX_REFRESH 8 2696 #define generic_cl48TxEEEStates_l_TX_QUIET 4 2697 #define generic_cl48TxEEEStates_l_TX_SLEEP 2 2698 #define generic_cl48TxEEEStates_l_TX_ACTIVE 1 2699 2700 /**************************************************************************** 2701 * Enums: generic_cl48TxEEEStates_c 2702 */ 2703 #define generic_cl48TxEEEStates_c_TX_REFRESH 3 2704 #define generic_cl48TxEEEStates_c_TX_QUIET 2 2705 #define generic_cl48TxEEEStates_c_TX_SLEEP 1 2706 #define generic_cl48TxEEEStates_c_TX_ACTIVE 0 2707 2708 /**************************************************************************** 2709 * Enums: generic_cl48RxEEEStates_l 2710 */ 2711 #define generic_cl48RxEEEStates_l_RX_LINK_FAIL 32 2712 #define generic_cl48RxEEEStates_l_RX_WAKE 16 2713 #define generic_cl48RxEEEStates_l_RX_QUIET 8 2714 #define generic_cl48RxEEEStates_l_RX_DEACT 4 2715 #define generic_cl48RxEEEStates_l_RX_SLEEP 2 2716 #define generic_cl48RxEEEStates_l_RX_ACTIVE 1 2717 2718 /**************************************************************************** 2719 * Enums: generic_cl48RxEEEStates_c 2720 */ 2721 #define generic_cl48RxEEEStates_c_RX_LINK_FAIL 5 2722 #define generic_cl48RxEEEStates_c_RX_WAKE 4 2723 #define generic_cl48RxEEEStates_c_RX_QUIET 3 2724 #define generic_cl48RxEEEStates_c_RX_DEACT 2 2725 #define generic_cl48RxEEEStates_c_RX_SLEEP 1 2726 #define generic_cl48RxEEEStates_c_RX_ACTIVE 0 2727 2728 /**************************************************************************** 2729 * Enums: generic_IQP_Options 2730 */ 2731 #define generic_IQP_Options_i50uA 0 2732 #define generic_IQP_Options_i100uA 1 2733 #define generic_IQP_Options_i150uA 2 2734 #define generic_IQP_Options_i200uA 3 2735 #define generic_IQP_Options_i250uA 4 2736 #define generic_IQP_Options_i300uA 5 2737 #define generic_IQP_Options_i350uA 6 2738 #define generic_IQP_Options_i400uA 7 2739 #define generic_IQP_Options_i450uA 8 2740 #define generic_IQP_Options_i500uA 9 2741 #define generic_IQP_Options_i550uA 10 2742 #define generic_IQP_Options_i600uA 11 2743 #define generic_IQP_Options_i650uA 12 2744 #define generic_IQP_Options_i700uA 13 2745 #define generic_IQP_Options_i750uA 14 2746 #define generic_IQP_Options_i800uA 15 2747 2748 /**************************************************************************** 2749 * Enums: generic_IDriver_Options 2750 */ 2751 #define generic_IDriver_Options_v680mV 0 2752 #define generic_IDriver_Options_v730mV 1 2753 #define generic_IDriver_Options_v780mV 2 2754 #define generic_IDriver_Options_v830mV 3 2755 #define generic_IDriver_Options_v880mV 4 2756 #define generic_IDriver_Options_v930mV 5 2757 #define generic_IDriver_Options_v980mV 6 2758 #define generic_IDriver_Options_v1010mV 7 2759 #define generic_IDriver_Options_v1040mV 8 2760 #define generic_IDriver_Options_v1060mV 9 2761 #define generic_IDriver_Options_v1070mV 10 2762 #define generic_IDriver_Options_v1080mV 11 2763 #define generic_IDriver_Options_v1085mV 12 2764 #define generic_IDriver_Options_v1090mV 13 2765 #define generic_IDriver_Options_v1095mV 14 2766 #define generic_IDriver_Options_v1100mV 15 2767 2768 /**************************************************************************** 2769 * Enums: generic_operationModes 2770 */ 2771 #define generic_operationModes_XGXS 0 2772 #define generic_operationModes_XGXG_nCC 1 2773 #define generic_operationModes_Indlane_OS8 4 2774 #define generic_operationModes_IndLane_OS5 5 2775 #define generic_operationModes_PCI 7 2776 #define generic_operationModes_XGXS_nLQ 8 2777 #define generic_operationModes_XGXS_nLQnCC 9 2778 #define generic_operationModes_PBypass 10 2779 #define generic_operationModes_PBypass_nDSK 11 2780 #define generic_operationModes_ComboCoreMode 12 2781 #define generic_operationModes_Clocks_off 15 2782 2783 /**************************************************************************** 2784 * Enums: generic_actualSpeeds 2785 */ 2786 #define generic_actualSpeeds_dr_10M 0 2787 #define generic_actualSpeeds_dr_100M 1 2788 #define generic_actualSpeeds_dr_1G 2 2789 #define generic_actualSpeeds_dr_2p5G 3 2790 #define generic_actualSpeeds_dr_5G_X4 4 2791 #define generic_actualSpeeds_dr_6G_X4 5 2792 #define generic_actualSpeeds_dr_10G_HiG 6 2793 #define generic_actualSpeeds_dr_10G_CX4 7 2794 #define generic_actualSpeeds_dr_12G_HiG 8 2795 #define generic_actualSpeeds_dr_12p5G_X4 9 2796 #define generic_actualSpeeds_dr_13G_X4 10 2797 #define generic_actualSpeeds_dr_15G_X4 11 2798 #define generic_actualSpeeds_dr_16G_X4 12 2799 #define generic_actualSpeeds_dr_1G_KX 13 2800 #define generic_actualSpeeds_dr_10G_KX4 14 2801 #define generic_actualSpeeds_dr_10G_KR 15 2802 #define generic_actualSpeeds_dr_5G 16 2803 #define generic_actualSpeeds_dr_6p4G 17 2804 #define generic_actualSpeeds_dr_20G_X4 18 2805 #define generic_actualSpeeds_dr_21G_X4 19 2806 #define generic_actualSpeeds_dr_25G_X4 20 2807 #define generic_actualSpeeds_dr_10G_HiG_DXGXS 21 2808 #define generic_actualSpeeds_dr_10G_DXGXS 22 2809 #define generic_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2810 #define generic_actualSpeeds_dr_10p5G_DXGXS 24 2811 #define generic_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2812 #define generic_actualSpeeds_dr_12p773G_DXGXS 26 2813 #define generic_actualSpeeds_dr_10G_XFI 27 2814 #define generic_actualSpeeds_dr_40G 28 2815 #define generic_actualSpeeds_dr_20G_HiG_DXGXS 29 2816 #define generic_actualSpeeds_dr_20G_DXGXS 30 2817 #define generic_actualSpeeds_dr_10G_SFI 31 2818 #define generic_actualSpeeds_dr_31p5G 32 2819 #define generic_actualSpeeds_dr_32p7G 33 2820 #define generic_actualSpeeds_dr_20G_SCR 34 2821 #define generic_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2822 #define generic_actualSpeeds_dr_10G_DXGXS_SCR 36 2823 #define generic_actualSpeeds_dr_12G_R2 37 2824 #define generic_actualSpeeds_dr_10G_X2 38 2825 #define generic_actualSpeeds_dr_40G_KR4 39 2826 #define generic_actualSpeeds_dr_40G_CR4 40 2827 #define generic_actualSpeeds_dr_100G_CR10 41 2828 #define generic_actualSpeeds_dr_15p75G_DXGXS 44 2829 #define generic_actualSpeeds_dr_20G_KR2 57 2830 #define generic_actualSpeeds_dr_20G_CR2 58 2831 2832 /**************************************************************************** 2833 * Enums: generic_actualSpeedsMisc1 2834 */ 2835 #define generic_actualSpeedsMisc1_dr_2500BRCM_X1 16 2836 #define generic_actualSpeedsMisc1_dr_5000BRCM_X4 17 2837 #define generic_actualSpeedsMisc1_dr_6000BRCM_X4 18 2838 #define generic_actualSpeedsMisc1_dr_10GHiGig_X4 19 2839 #define generic_actualSpeedsMisc1_dr_10GBASE_CX4 20 2840 #define generic_actualSpeedsMisc1_dr_12GHiGig_X4 21 2841 #define generic_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2842 #define generic_actualSpeedsMisc1_dr_13GHiGig_X4 23 2843 #define generic_actualSpeedsMisc1_dr_15GHiGig_X4 24 2844 #define generic_actualSpeedsMisc1_dr_16GHiGig_X4 25 2845 #define generic_actualSpeedsMisc1_dr_5000BRCM_X1 26 2846 #define generic_actualSpeedsMisc1_dr_6363BRCM_X1 27 2847 #define generic_actualSpeedsMisc1_dr_20GHiGig_X4 28 2848 #define generic_actualSpeedsMisc1_dr_21GHiGig_X4 29 2849 #define generic_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2850 #define generic_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2851 2852 /**************************************************************************** 2853 * Enums: generic_IndLaneModes 2854 */ 2855 #define generic_IndLaneModes_SWSDR_div2 0 2856 #define generic_IndLaneModes_SWSDR_div1 1 2857 #define generic_IndLaneModes_DWSDR_div2 2 2858 #define generic_IndLaneModes_DWSDR_div1 3 2859 2860 /**************************************************************************** 2861 * Enums: generic_prbsSelect 2862 */ 2863 #define generic_prbsSelect_prbs7 0 2864 #define generic_prbsSelect_prbs15 1 2865 #define generic_prbsSelect_prbs23 2 2866 #define generic_prbsSelect_prbs31 3 2867 2868 /**************************************************************************** 2869 * Enums: generic_vcoDivider 2870 */ 2871 #define generic_vcoDivider_div32 0 2872 #define generic_vcoDivider_div36 1 2873 #define generic_vcoDivider_div40 2 2874 #define generic_vcoDivider_div42 3 2875 #define generic_vcoDivider_div48 4 2876 #define generic_vcoDivider_div50 5 2877 #define generic_vcoDivider_div52 6 2878 #define generic_vcoDivider_div54 7 2879 #define generic_vcoDivider_div60 8 2880 #define generic_vcoDivider_div64 9 2881 #define generic_vcoDivider_div66 10 2882 #define generic_vcoDivider_div68 11 2883 #define generic_vcoDivider_div70 12 2884 #define generic_vcoDivider_div80 13 2885 #define generic_vcoDivider_div92 14 2886 #define generic_vcoDivider_div100 15 2887 2888 /**************************************************************************** 2889 * Enums: generic_refClkSelect 2890 */ 2891 #define generic_refClkSelect_clk_25MHz 0 2892 #define generic_refClkSelect_clk_100MHz 1 2893 #define generic_refClkSelect_clk_125MHz 2 2894 #define generic_refClkSelect_clk_156p25MHz 3 2895 #define generic_refClkSelect_clk_187p5MHz 4 2896 #define generic_refClkSelect_clk_161p25Mhz 5 2897 #define generic_refClkSelect_clk_50Mhz 6 2898 #define generic_refClkSelect_clk_106p25Mhz 7 2899 2900 /**************************************************************************** 2901 * Enums: generic_aerMMDdevTypeSelect 2902 */ 2903 #define generic_aerMMDdevTypeSelect_combo_core 0 2904 #define generic_aerMMDdevTypeSelect_PMA_PMD 1 2905 #define generic_aerMMDdevTypeSelect_PCS 3 2906 #define generic_aerMMDdevTypeSelect_PHY 4 2907 #define generic_aerMMDdevTypeSelect_DTE 5 2908 #define generic_aerMMDdevTypeSelect_CL73_AN 7 2909 2910 /**************************************************************************** 2911 * Enums: generic_aerMMDportSelect 2912 */ 2913 #define generic_aerMMDportSelect_ln0 0 2914 #define generic_aerMMDportSelect_ln1 1 2915 #define generic_aerMMDportSelect_ln2 2 2916 #define generic_aerMMDportSelect_ln3 3 2917 #define generic_aerMMDportSelect_BCST_ln0_1_2_3 511 2918 #define generic_aerMMDportSelect_BCST_ln0_1 512 2919 #define generic_aerMMDportSelect_BCST_ln2_3 513 2920 2921 /**************************************************************************** 2922 * Enums: generic_firmwareModeSelect 2923 */ 2924 #define generic_firmwareModeSelect_DEFAULT 0 2925 #define generic_firmwareModeSelect_SFP_OPT_LR 1 2926 #define generic_firmwareModeSelect_SFP_DAC 2 2927 #define generic_firmwareModeSelect_XLAUI 3 2928 #define generic_firmwareModeSelect_LONG_CH_6G 4 2929 2930 /**************************************************************************** 2931 * Enums: generic_tempIdxSelect 2932 */ 2933 #define generic_tempIdxSelect_LTE__22p9C 15 2934 #define generic_tempIdxSelect_LTE__12p6C 14 2935 #define generic_tempIdxSelect_LTE__3p0C 13 2936 #define generic_tempIdxSelect_LTE_6p7C 12 2937 #define generic_tempIdxSelect_LTE_16p4C 11 2938 #define generic_tempIdxSelect_LTE_26p6C 10 2939 #define generic_tempIdxSelect_LTE_36p3C 9 2940 #define generic_tempIdxSelect_LTE_46p0C 8 2941 #define generic_tempIdxSelect_LTE_56p2C 7 2942 #define generic_tempIdxSelect_LTE_65p9C 6 2943 #define generic_tempIdxSelect_LTE_75p6C 5 2944 #define generic_tempIdxSelect_LTE_85p3C 4 2945 #define generic_tempIdxSelect_LTE_95p5C 3 2946 #define generic_tempIdxSelect_LTE_105p2C 2 2947 #define generic_tempIdxSelect_LTE_114p9C 1 2948 #define generic_tempIdxSelect_LTE_125p1C 0 2949 2950 /**************************************************************************** 2951 * Enums: gp2_cl36TxEEEStates_l 2952 */ 2953 #define gp2_cl36TxEEEStates_l_TX_REFRESH 8 2954 #define gp2_cl36TxEEEStates_l_TX_QUIET 4 2955 #define gp2_cl36TxEEEStates_l_TX_SLEEP 2 2956 #define gp2_cl36TxEEEStates_l_TX_ACTIVE 1 2957 2958 /**************************************************************************** 2959 * Enums: gp2_cl36TxEEEStates_c 2960 */ 2961 #define gp2_cl36TxEEEStates_c_TX_REFRESH 3 2962 #define gp2_cl36TxEEEStates_c_TX_QUIET 2 2963 #define gp2_cl36TxEEEStates_c_TX_SLEEP 1 2964 #define gp2_cl36TxEEEStates_c_TX_ACTIVE 0 2965 2966 /**************************************************************************** 2967 * Enums: gp2_cl49TxEEEStates_l 2968 */ 2969 #define gp2_cl49TxEEEStates_l_SCR_RESET_2 64 2970 #define gp2_cl49TxEEEStates_l_SCR_RESET_1 32 2971 #define gp2_cl49TxEEEStates_l_TX_WAKE 16 2972 #define gp2_cl49TxEEEStates_l_TX_REFRESH 8 2973 #define gp2_cl49TxEEEStates_l_TX_QUIET 4 2974 #define gp2_cl49TxEEEStates_l_TX_SLEEP 2 2975 #define gp2_cl49TxEEEStates_l_TX_ACTIVE 1 2976 2977 /**************************************************************************** 2978 * Enums: gp2_cl49TxEEEStates_c 2979 */ 2980 #define gp2_cl49TxEEEStates_c_SCR_RESET_2 6 2981 #define gp2_cl49TxEEEStates_c_SCR_RESET_1 5 2982 #define gp2_cl49TxEEEStates_c_TX_WAKE 4 2983 #define gp2_cl49TxEEEStates_c_TX_REFRESH 3 2984 #define gp2_cl49TxEEEStates_c_TX_QUIET 2 2985 #define gp2_cl49TxEEEStates_c_TX_SLEEP 1 2986 #define gp2_cl49TxEEEStates_c_TX_ACTIVE 0 2987 2988 /**************************************************************************** 2989 * Enums: gp2_cl36RxEEEStates_l 2990 */ 2991 #define gp2_cl36RxEEEStates_l_RX_LINK_FAIL 32 2992 #define gp2_cl36RxEEEStates_l_RX_WTF 16 2993 #define gp2_cl36RxEEEStates_l_RX_WAKE 8 2994 #define gp2_cl36RxEEEStates_l_RX_QUIET 4 2995 #define gp2_cl36RxEEEStates_l_RX_SLEEP 2 2996 #define gp2_cl36RxEEEStates_l_RX_ACTIVE 1 2997 2998 /**************************************************************************** 2999 * Enums: gp2_cl36RxEEEStates_c 3000 */ 3001 #define gp2_cl36RxEEEStates_c_RX_LINK_FAIL 5 3002 #define gp2_cl36RxEEEStates_c_RX_WTF 4 3003 #define gp2_cl36RxEEEStates_c_RX_WAKE 3 3004 #define gp2_cl36RxEEEStates_c_RX_QUIET 2 3005 #define gp2_cl36RxEEEStates_c_RX_SLEEP 1 3006 #define gp2_cl36RxEEEStates_c_RX_ACTIVE 0 3007 3008 /**************************************************************************** 3009 * Enums: gp2_cl49RxEEEStates_l 3010 */ 3011 #define gp2_cl49RxEEEStates_l_RX_LINK_FAIL 32 3012 #define gp2_cl49RxEEEStates_l_RX_WTF 16 3013 #define gp2_cl49RxEEEStates_l_RX_WAKE 8 3014 #define gp2_cl49RxEEEStates_l_RX_QUIET 4 3015 #define gp2_cl49RxEEEStates_l_RX_SLEEP 2 3016 #define gp2_cl49RxEEEStates_l_RX_ACTIVE 1 3017 3018 /**************************************************************************** 3019 * Enums: gp2_cl49RxEEEStates_c 3020 */ 3021 #define gp2_cl49RxEEEStates_c_RX_LINK_FAIL 5 3022 #define gp2_cl49RxEEEStates_c_RX_WTF 4 3023 #define gp2_cl49RxEEEStates_c_RX_WAKE 3 3024 #define gp2_cl49RxEEEStates_c_RX_QUIET 2 3025 #define gp2_cl49RxEEEStates_c_RX_SLEEP 1 3026 #define gp2_cl49RxEEEStates_c_RX_ACTIVE 0 3027 3028 /**************************************************************************** 3029 * Enums: gp2_cl48TxEEEStates_l 3030 */ 3031 #define gp2_cl48TxEEEStates_l_TX_REFRESH 8 3032 #define gp2_cl48TxEEEStates_l_TX_QUIET 4 3033 #define gp2_cl48TxEEEStates_l_TX_SLEEP 2 3034 #define gp2_cl48TxEEEStates_l_TX_ACTIVE 1 3035 3036 /**************************************************************************** 3037 * Enums: gp2_cl48TxEEEStates_c 3038 */ 3039 #define gp2_cl48TxEEEStates_c_TX_REFRESH 3 3040 #define gp2_cl48TxEEEStates_c_TX_QUIET 2 3041 #define gp2_cl48TxEEEStates_c_TX_SLEEP 1 3042 #define gp2_cl48TxEEEStates_c_TX_ACTIVE 0 3043 3044 /**************************************************************************** 3045 * Enums: gp2_cl48RxEEEStates_l 3046 */ 3047 #define gp2_cl48RxEEEStates_l_RX_LINK_FAIL 32 3048 #define gp2_cl48RxEEEStates_l_RX_WAKE 16 3049 #define gp2_cl48RxEEEStates_l_RX_QUIET 8 3050 #define gp2_cl48RxEEEStates_l_RX_DEACT 4 3051 #define gp2_cl48RxEEEStates_l_RX_SLEEP 2 3052 #define gp2_cl48RxEEEStates_l_RX_ACTIVE 1 3053 3054 /**************************************************************************** 3055 * Enums: gp2_cl48RxEEEStates_c 3056 */ 3057 #define gp2_cl48RxEEEStates_c_RX_LINK_FAIL 5 3058 #define gp2_cl48RxEEEStates_c_RX_WAKE 4 3059 #define gp2_cl48RxEEEStates_c_RX_QUIET 3 3060 #define gp2_cl48RxEEEStates_c_RX_DEACT 2 3061 #define gp2_cl48RxEEEStates_c_RX_SLEEP 1 3062 #define gp2_cl48RxEEEStates_c_RX_ACTIVE 0 3063 3064 /**************************************************************************** 3065 * Enums: gp2_IQP_Options 3066 */ 3067 #define gp2_IQP_Options_i50uA 0 3068 #define gp2_IQP_Options_i100uA 1 3069 #define gp2_IQP_Options_i150uA 2 3070 #define gp2_IQP_Options_i200uA 3 3071 #define gp2_IQP_Options_i250uA 4 3072 #define gp2_IQP_Options_i300uA 5 3073 #define gp2_IQP_Options_i350uA 6 3074 #define gp2_IQP_Options_i400uA 7 3075 #define gp2_IQP_Options_i450uA 8 3076 #define gp2_IQP_Options_i500uA 9 3077 #define gp2_IQP_Options_i550uA 10 3078 #define gp2_IQP_Options_i600uA 11 3079 #define gp2_IQP_Options_i650uA 12 3080 #define gp2_IQP_Options_i700uA 13 3081 #define gp2_IQP_Options_i750uA 14 3082 #define gp2_IQP_Options_i800uA 15 3083 3084 /**************************************************************************** 3085 * Enums: gp2_IDriver_Options 3086 */ 3087 #define gp2_IDriver_Options_v680mV 0 3088 #define gp2_IDriver_Options_v730mV 1 3089 #define gp2_IDriver_Options_v780mV 2 3090 #define gp2_IDriver_Options_v830mV 3 3091 #define gp2_IDriver_Options_v880mV 4 3092 #define gp2_IDriver_Options_v930mV 5 3093 #define gp2_IDriver_Options_v980mV 6 3094 #define gp2_IDriver_Options_v1010mV 7 3095 #define gp2_IDriver_Options_v1040mV 8 3096 #define gp2_IDriver_Options_v1060mV 9 3097 #define gp2_IDriver_Options_v1070mV 10 3098 #define gp2_IDriver_Options_v1080mV 11 3099 #define gp2_IDriver_Options_v1085mV 12 3100 #define gp2_IDriver_Options_v1090mV 13 3101 #define gp2_IDriver_Options_v1095mV 14 3102 #define gp2_IDriver_Options_v1100mV 15 3103 3104 /**************************************************************************** 3105 * Enums: gp2_operationModes 3106 */ 3107 #define gp2_operationModes_XGXS 0 3108 #define gp2_operationModes_XGXG_nCC 1 3109 #define gp2_operationModes_Indlane_OS8 4 3110 #define gp2_operationModes_IndLane_OS5 5 3111 #define gp2_operationModes_PCI 7 3112 #define gp2_operationModes_XGXS_nLQ 8 3113 #define gp2_operationModes_XGXS_nLQnCC 9 3114 #define gp2_operationModes_PBypass 10 3115 #define gp2_operationModes_PBypass_nDSK 11 3116 #define gp2_operationModes_ComboCoreMode 12 3117 #define gp2_operationModes_Clocks_off 15 3118 3119 /**************************************************************************** 3120 * Enums: gp2_actualSpeeds 3121 */ 3122 #define gp2_actualSpeeds_dr_10M 0 3123 #define gp2_actualSpeeds_dr_100M 1 3124 #define gp2_actualSpeeds_dr_1G 2 3125 #define gp2_actualSpeeds_dr_2p5G 3 3126 #define gp2_actualSpeeds_dr_5G_X4 4 3127 #define gp2_actualSpeeds_dr_6G_X4 5 3128 #define gp2_actualSpeeds_dr_10G_HiG 6 3129 #define gp2_actualSpeeds_dr_10G_CX4 7 3130 #define gp2_actualSpeeds_dr_12G_HiG 8 3131 #define gp2_actualSpeeds_dr_12p5G_X4 9 3132 #define gp2_actualSpeeds_dr_13G_X4 10 3133 #define gp2_actualSpeeds_dr_15G_X4 11 3134 #define gp2_actualSpeeds_dr_16G_X4 12 3135 #define gp2_actualSpeeds_dr_1G_KX 13 3136 #define gp2_actualSpeeds_dr_10G_KX4 14 3137 #define gp2_actualSpeeds_dr_10G_KR 15 3138 #define gp2_actualSpeeds_dr_5G 16 3139 #define gp2_actualSpeeds_dr_6p4G 17 3140 #define gp2_actualSpeeds_dr_20G_X4 18 3141 #define gp2_actualSpeeds_dr_21G_X4 19 3142 #define gp2_actualSpeeds_dr_25G_X4 20 3143 #define gp2_actualSpeeds_dr_10G_HiG_DXGXS 21 3144 #define gp2_actualSpeeds_dr_10G_DXGXS 22 3145 #define gp2_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3146 #define gp2_actualSpeeds_dr_10p5G_DXGXS 24 3147 #define gp2_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3148 #define gp2_actualSpeeds_dr_12p773G_DXGXS 26 3149 #define gp2_actualSpeeds_dr_10G_XFI 27 3150 #define gp2_actualSpeeds_dr_40G 28 3151 #define gp2_actualSpeeds_dr_20G_HiG_DXGXS 29 3152 #define gp2_actualSpeeds_dr_20G_DXGXS 30 3153 #define gp2_actualSpeeds_dr_10G_SFI 31 3154 #define gp2_actualSpeeds_dr_31p5G 32 3155 #define gp2_actualSpeeds_dr_32p7G 33 3156 #define gp2_actualSpeeds_dr_20G_SCR 34 3157 #define gp2_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3158 #define gp2_actualSpeeds_dr_10G_DXGXS_SCR 36 3159 #define gp2_actualSpeeds_dr_12G_R2 37 3160 #define gp2_actualSpeeds_dr_10G_X2 38 3161 #define gp2_actualSpeeds_dr_40G_KR4 39 3162 #define gp2_actualSpeeds_dr_40G_CR4 40 3163 #define gp2_actualSpeeds_dr_100G_CR10 41 3164 #define gp2_actualSpeeds_dr_15p75G_DXGXS 44 3165 #define gp2_actualSpeeds_dr_20G_KR2 57 3166 #define gp2_actualSpeeds_dr_20G_CR2 58 3167 3168 /**************************************************************************** 3169 * Enums: gp2_actualSpeedsMisc1 3170 */ 3171 #define gp2_actualSpeedsMisc1_dr_2500BRCM_X1 16 3172 #define gp2_actualSpeedsMisc1_dr_5000BRCM_X4 17 3173 #define gp2_actualSpeedsMisc1_dr_6000BRCM_X4 18 3174 #define gp2_actualSpeedsMisc1_dr_10GHiGig_X4 19 3175 #define gp2_actualSpeedsMisc1_dr_10GBASE_CX4 20 3176 #define gp2_actualSpeedsMisc1_dr_12GHiGig_X4 21 3177 #define gp2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3178 #define gp2_actualSpeedsMisc1_dr_13GHiGig_X4 23 3179 #define gp2_actualSpeedsMisc1_dr_15GHiGig_X4 24 3180 #define gp2_actualSpeedsMisc1_dr_16GHiGig_X4 25 3181 #define gp2_actualSpeedsMisc1_dr_5000BRCM_X1 26 3182 #define gp2_actualSpeedsMisc1_dr_6363BRCM_X1 27 3183 #define gp2_actualSpeedsMisc1_dr_20GHiGig_X4 28 3184 #define gp2_actualSpeedsMisc1_dr_21GHiGig_X4 29 3185 #define gp2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3186 #define gp2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3187 3188 /**************************************************************************** 3189 * Enums: gp2_IndLaneModes 3190 */ 3191 #define gp2_IndLaneModes_SWSDR_div2 0 3192 #define gp2_IndLaneModes_SWSDR_div1 1 3193 #define gp2_IndLaneModes_DWSDR_div2 2 3194 #define gp2_IndLaneModes_DWSDR_div1 3 3195 3196 /**************************************************************************** 3197 * Enums: gp2_prbsSelect 3198 */ 3199 #define gp2_prbsSelect_prbs7 0 3200 #define gp2_prbsSelect_prbs15 1 3201 #define gp2_prbsSelect_prbs23 2 3202 #define gp2_prbsSelect_prbs31 3 3203 3204 /**************************************************************************** 3205 * Enums: gp2_vcoDivider 3206 */ 3207 #define gp2_vcoDivider_div32 0 3208 #define gp2_vcoDivider_div36 1 3209 #define gp2_vcoDivider_div40 2 3210 #define gp2_vcoDivider_div42 3 3211 #define gp2_vcoDivider_div48 4 3212 #define gp2_vcoDivider_div50 5 3213 #define gp2_vcoDivider_div52 6 3214 #define gp2_vcoDivider_div54 7 3215 #define gp2_vcoDivider_div60 8 3216 #define gp2_vcoDivider_div64 9 3217 #define gp2_vcoDivider_div66 10 3218 #define gp2_vcoDivider_div68 11 3219 #define gp2_vcoDivider_div70 12 3220 #define gp2_vcoDivider_div80 13 3221 #define gp2_vcoDivider_div92 14 3222 #define gp2_vcoDivider_div100 15 3223 3224 /**************************************************************************** 3225 * Enums: gp2_refClkSelect 3226 */ 3227 #define gp2_refClkSelect_clk_25MHz 0 3228 #define gp2_refClkSelect_clk_100MHz 1 3229 #define gp2_refClkSelect_clk_125MHz 2 3230 #define gp2_refClkSelect_clk_156p25MHz 3 3231 #define gp2_refClkSelect_clk_187p5MHz 4 3232 #define gp2_refClkSelect_clk_161p25Mhz 5 3233 #define gp2_refClkSelect_clk_50Mhz 6 3234 #define gp2_refClkSelect_clk_106p25Mhz 7 3235 3236 /**************************************************************************** 3237 * Enums: gp2_aerMMDdevTypeSelect 3238 */ 3239 #define gp2_aerMMDdevTypeSelect_combo_core 0 3240 #define gp2_aerMMDdevTypeSelect_PMA_PMD 1 3241 #define gp2_aerMMDdevTypeSelect_PCS 3 3242 #define gp2_aerMMDdevTypeSelect_PHY 4 3243 #define gp2_aerMMDdevTypeSelect_DTE 5 3244 #define gp2_aerMMDdevTypeSelect_CL73_AN 7 3245 3246 /**************************************************************************** 3247 * Enums: gp2_aerMMDportSelect 3248 */ 3249 #define gp2_aerMMDportSelect_ln0 0 3250 #define gp2_aerMMDportSelect_ln1 1 3251 #define gp2_aerMMDportSelect_ln2 2 3252 #define gp2_aerMMDportSelect_ln3 3 3253 #define gp2_aerMMDportSelect_BCST_ln0_1_2_3 511 3254 #define gp2_aerMMDportSelect_BCST_ln0_1 512 3255 #define gp2_aerMMDportSelect_BCST_ln2_3 513 3256 3257 /**************************************************************************** 3258 * Enums: gp2_firmwareModeSelect 3259 */ 3260 #define gp2_firmwareModeSelect_DEFAULT 0 3261 #define gp2_firmwareModeSelect_SFP_OPT_LR 1 3262 #define gp2_firmwareModeSelect_SFP_DAC 2 3263 #define gp2_firmwareModeSelect_XLAUI 3 3264 #define gp2_firmwareModeSelect_LONG_CH_6G 4 3265 3266 /**************************************************************************** 3267 * Enums: gp2_tempIdxSelect 3268 */ 3269 #define gp2_tempIdxSelect_LTE__22p9C 15 3270 #define gp2_tempIdxSelect_LTE__12p6C 14 3271 #define gp2_tempIdxSelect_LTE__3p0C 13 3272 #define gp2_tempIdxSelect_LTE_6p7C 12 3273 #define gp2_tempIdxSelect_LTE_16p4C 11 3274 #define gp2_tempIdxSelect_LTE_26p6C 10 3275 #define gp2_tempIdxSelect_LTE_36p3C 9 3276 #define gp2_tempIdxSelect_LTE_46p0C 8 3277 #define gp2_tempIdxSelect_LTE_56p2C 7 3278 #define gp2_tempIdxSelect_LTE_65p9C 6 3279 #define gp2_tempIdxSelect_LTE_75p6C 5 3280 #define gp2_tempIdxSelect_LTE_85p3C 4 3281 #define gp2_tempIdxSelect_LTE_95p5C 3 3282 #define gp2_tempIdxSelect_LTE_105p2C 2 3283 #define gp2_tempIdxSelect_LTE_114p9C 1 3284 #define gp2_tempIdxSelect_LTE_125p1C 0 3285 3286 /**************************************************************************** 3287 * Enums: ieee_an0_cl36TxEEEStates_l 3288 */ 3289 #define ieee_an0_cl36TxEEEStates_l_TX_REFRESH 8 3290 #define ieee_an0_cl36TxEEEStates_l_TX_QUIET 4 3291 #define ieee_an0_cl36TxEEEStates_l_TX_SLEEP 2 3292 #define ieee_an0_cl36TxEEEStates_l_TX_ACTIVE 1 3293 3294 /**************************************************************************** 3295 * Enums: ieee_an0_cl36TxEEEStates_c 3296 */ 3297 #define ieee_an0_cl36TxEEEStates_c_TX_REFRESH 3 3298 #define ieee_an0_cl36TxEEEStates_c_TX_QUIET 2 3299 #define ieee_an0_cl36TxEEEStates_c_TX_SLEEP 1 3300 #define ieee_an0_cl36TxEEEStates_c_TX_ACTIVE 0 3301 3302 /**************************************************************************** 3303 * Enums: ieee_an0_cl49TxEEEStates_l 3304 */ 3305 #define ieee_an0_cl49TxEEEStates_l_SCR_RESET_2 64 3306 #define ieee_an0_cl49TxEEEStates_l_SCR_RESET_1 32 3307 #define ieee_an0_cl49TxEEEStates_l_TX_WAKE 16 3308 #define ieee_an0_cl49TxEEEStates_l_TX_REFRESH 8 3309 #define ieee_an0_cl49TxEEEStates_l_TX_QUIET 4 3310 #define ieee_an0_cl49TxEEEStates_l_TX_SLEEP 2 3311 #define ieee_an0_cl49TxEEEStates_l_TX_ACTIVE 1 3312 3313 /**************************************************************************** 3314 * Enums: ieee_an0_cl49TxEEEStates_c 3315 */ 3316 #define ieee_an0_cl49TxEEEStates_c_SCR_RESET_2 6 3317 #define ieee_an0_cl49TxEEEStates_c_SCR_RESET_1 5 3318 #define ieee_an0_cl49TxEEEStates_c_TX_WAKE 4 3319 #define ieee_an0_cl49TxEEEStates_c_TX_REFRESH 3 3320 #define ieee_an0_cl49TxEEEStates_c_TX_QUIET 2 3321 #define ieee_an0_cl49TxEEEStates_c_TX_SLEEP 1 3322 #define ieee_an0_cl49TxEEEStates_c_TX_ACTIVE 0 3323 3324 /**************************************************************************** 3325 * Enums: ieee_an0_cl36RxEEEStates_l 3326 */ 3327 #define ieee_an0_cl36RxEEEStates_l_RX_LINK_FAIL 32 3328 #define ieee_an0_cl36RxEEEStates_l_RX_WTF 16 3329 #define ieee_an0_cl36RxEEEStates_l_RX_WAKE 8 3330 #define ieee_an0_cl36RxEEEStates_l_RX_QUIET 4 3331 #define ieee_an0_cl36RxEEEStates_l_RX_SLEEP 2 3332 #define ieee_an0_cl36RxEEEStates_l_RX_ACTIVE 1 3333 3334 /**************************************************************************** 3335 * Enums: ieee_an0_cl36RxEEEStates_c 3336 */ 3337 #define ieee_an0_cl36RxEEEStates_c_RX_LINK_FAIL 5 3338 #define ieee_an0_cl36RxEEEStates_c_RX_WTF 4 3339 #define ieee_an0_cl36RxEEEStates_c_RX_WAKE 3 3340 #define ieee_an0_cl36RxEEEStates_c_RX_QUIET 2 3341 #define ieee_an0_cl36RxEEEStates_c_RX_SLEEP 1 3342 #define ieee_an0_cl36RxEEEStates_c_RX_ACTIVE 0 3343 3344 /**************************************************************************** 3345 * Enums: ieee_an0_cl49RxEEEStates_l 3346 */ 3347 #define ieee_an0_cl49RxEEEStates_l_RX_LINK_FAIL 32 3348 #define ieee_an0_cl49RxEEEStates_l_RX_WTF 16 3349 #define ieee_an0_cl49RxEEEStates_l_RX_WAKE 8 3350 #define ieee_an0_cl49RxEEEStates_l_RX_QUIET 4 3351 #define ieee_an0_cl49RxEEEStates_l_RX_SLEEP 2 3352 #define ieee_an0_cl49RxEEEStates_l_RX_ACTIVE 1 3353 3354 /**************************************************************************** 3355 * Enums: ieee_an0_cl49RxEEEStates_c 3356 */ 3357 #define ieee_an0_cl49RxEEEStates_c_RX_LINK_FAIL 5 3358 #define ieee_an0_cl49RxEEEStates_c_RX_WTF 4 3359 #define ieee_an0_cl49RxEEEStates_c_RX_WAKE 3 3360 #define ieee_an0_cl49RxEEEStates_c_RX_QUIET 2 3361 #define ieee_an0_cl49RxEEEStates_c_RX_SLEEP 1 3362 #define ieee_an0_cl49RxEEEStates_c_RX_ACTIVE 0 3363 3364 /**************************************************************************** 3365 * Enums: ieee_an0_cl48TxEEEStates_l 3366 */ 3367 #define ieee_an0_cl48TxEEEStates_l_TX_REFRESH 8 3368 #define ieee_an0_cl48TxEEEStates_l_TX_QUIET 4 3369 #define ieee_an0_cl48TxEEEStates_l_TX_SLEEP 2 3370 #define ieee_an0_cl48TxEEEStates_l_TX_ACTIVE 1 3371 3372 /**************************************************************************** 3373 * Enums: ieee_an0_cl48TxEEEStates_c 3374 */ 3375 #define ieee_an0_cl48TxEEEStates_c_TX_REFRESH 3 3376 #define ieee_an0_cl48TxEEEStates_c_TX_QUIET 2 3377 #define ieee_an0_cl48TxEEEStates_c_TX_SLEEP 1 3378 #define ieee_an0_cl48TxEEEStates_c_TX_ACTIVE 0 3379 3380 /**************************************************************************** 3381 * Enums: ieee_an0_cl48RxEEEStates_l 3382 */ 3383 #define ieee_an0_cl48RxEEEStates_l_RX_LINK_FAIL 32 3384 #define ieee_an0_cl48RxEEEStates_l_RX_WAKE 16 3385 #define ieee_an0_cl48RxEEEStates_l_RX_QUIET 8 3386 #define ieee_an0_cl48RxEEEStates_l_RX_DEACT 4 3387 #define ieee_an0_cl48RxEEEStates_l_RX_SLEEP 2 3388 #define ieee_an0_cl48RxEEEStates_l_RX_ACTIVE 1 3389 3390 /**************************************************************************** 3391 * Enums: ieee_an0_cl48RxEEEStates_c 3392 */ 3393 #define ieee_an0_cl48RxEEEStates_c_RX_LINK_FAIL 5 3394 #define ieee_an0_cl48RxEEEStates_c_RX_WAKE 4 3395 #define ieee_an0_cl48RxEEEStates_c_RX_QUIET 3 3396 #define ieee_an0_cl48RxEEEStates_c_RX_DEACT 2 3397 #define ieee_an0_cl48RxEEEStates_c_RX_SLEEP 1 3398 #define ieee_an0_cl48RxEEEStates_c_RX_ACTIVE 0 3399 3400 /**************************************************************************** 3401 * Enums: ieee_an0_IQP_Options 3402 */ 3403 #define ieee_an0_IQP_Options_i50uA 0 3404 #define ieee_an0_IQP_Options_i100uA 1 3405 #define ieee_an0_IQP_Options_i150uA 2 3406 #define ieee_an0_IQP_Options_i200uA 3 3407 #define ieee_an0_IQP_Options_i250uA 4 3408 #define ieee_an0_IQP_Options_i300uA 5 3409 #define ieee_an0_IQP_Options_i350uA 6 3410 #define ieee_an0_IQP_Options_i400uA 7 3411 #define ieee_an0_IQP_Options_i450uA 8 3412 #define ieee_an0_IQP_Options_i500uA 9 3413 #define ieee_an0_IQP_Options_i550uA 10 3414 #define ieee_an0_IQP_Options_i600uA 11 3415 #define ieee_an0_IQP_Options_i650uA 12 3416 #define ieee_an0_IQP_Options_i700uA 13 3417 #define ieee_an0_IQP_Options_i750uA 14 3418 #define ieee_an0_IQP_Options_i800uA 15 3419 3420 /**************************************************************************** 3421 * Enums: ieee_an0_IDriver_Options 3422 */ 3423 #define ieee_an0_IDriver_Options_v680mV 0 3424 #define ieee_an0_IDriver_Options_v730mV 1 3425 #define ieee_an0_IDriver_Options_v780mV 2 3426 #define ieee_an0_IDriver_Options_v830mV 3 3427 #define ieee_an0_IDriver_Options_v880mV 4 3428 #define ieee_an0_IDriver_Options_v930mV 5 3429 #define ieee_an0_IDriver_Options_v980mV 6 3430 #define ieee_an0_IDriver_Options_v1010mV 7 3431 #define ieee_an0_IDriver_Options_v1040mV 8 3432 #define ieee_an0_IDriver_Options_v1060mV 9 3433 #define ieee_an0_IDriver_Options_v1070mV 10 3434 #define ieee_an0_IDriver_Options_v1080mV 11 3435 #define ieee_an0_IDriver_Options_v1085mV 12 3436 #define ieee_an0_IDriver_Options_v1090mV 13 3437 #define ieee_an0_IDriver_Options_v1095mV 14 3438 #define ieee_an0_IDriver_Options_v1100mV 15 3439 3440 /**************************************************************************** 3441 * Enums: ieee_an0_operationModes 3442 */ 3443 #define ieee_an0_operationModes_XGXS 0 3444 #define ieee_an0_operationModes_XGXG_nCC 1 3445 #define ieee_an0_operationModes_Indlane_OS8 4 3446 #define ieee_an0_operationModes_IndLane_OS5 5 3447 #define ieee_an0_operationModes_PCI 7 3448 #define ieee_an0_operationModes_XGXS_nLQ 8 3449 #define ieee_an0_operationModes_XGXS_nLQnCC 9 3450 #define ieee_an0_operationModes_PBypass 10 3451 #define ieee_an0_operationModes_PBypass_nDSK 11 3452 #define ieee_an0_operationModes_ComboCoreMode 12 3453 #define ieee_an0_operationModes_Clocks_off 15 3454 3455 /**************************************************************************** 3456 * Enums: ieee_an0_actualSpeeds 3457 */ 3458 #define ieee_an0_actualSpeeds_dr_10M 0 3459 #define ieee_an0_actualSpeeds_dr_100M 1 3460 #define ieee_an0_actualSpeeds_dr_1G 2 3461 #define ieee_an0_actualSpeeds_dr_2p5G 3 3462 #define ieee_an0_actualSpeeds_dr_5G_X4 4 3463 #define ieee_an0_actualSpeeds_dr_6G_X4 5 3464 #define ieee_an0_actualSpeeds_dr_10G_HiG 6 3465 #define ieee_an0_actualSpeeds_dr_10G_CX4 7 3466 #define ieee_an0_actualSpeeds_dr_12G_HiG 8 3467 #define ieee_an0_actualSpeeds_dr_12p5G_X4 9 3468 #define ieee_an0_actualSpeeds_dr_13G_X4 10 3469 #define ieee_an0_actualSpeeds_dr_15G_X4 11 3470 #define ieee_an0_actualSpeeds_dr_16G_X4 12 3471 #define ieee_an0_actualSpeeds_dr_1G_KX 13 3472 #define ieee_an0_actualSpeeds_dr_10G_KX4 14 3473 #define ieee_an0_actualSpeeds_dr_10G_KR 15 3474 #define ieee_an0_actualSpeeds_dr_5G 16 3475 #define ieee_an0_actualSpeeds_dr_6p4G 17 3476 #define ieee_an0_actualSpeeds_dr_20G_X4 18 3477 #define ieee_an0_actualSpeeds_dr_21G_X4 19 3478 #define ieee_an0_actualSpeeds_dr_25G_X4 20 3479 #define ieee_an0_actualSpeeds_dr_10G_HiG_DXGXS 21 3480 #define ieee_an0_actualSpeeds_dr_10G_DXGXS 22 3481 #define ieee_an0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3482 #define ieee_an0_actualSpeeds_dr_10p5G_DXGXS 24 3483 #define ieee_an0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3484 #define ieee_an0_actualSpeeds_dr_12p773G_DXGXS 26 3485 #define ieee_an0_actualSpeeds_dr_10G_XFI 27 3486 #define ieee_an0_actualSpeeds_dr_40G 28 3487 #define ieee_an0_actualSpeeds_dr_20G_HiG_DXGXS 29 3488 #define ieee_an0_actualSpeeds_dr_20G_DXGXS 30 3489 #define ieee_an0_actualSpeeds_dr_10G_SFI 31 3490 #define ieee_an0_actualSpeeds_dr_31p5G 32 3491 #define ieee_an0_actualSpeeds_dr_32p7G 33 3492 #define ieee_an0_actualSpeeds_dr_20G_SCR 34 3493 #define ieee_an0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3494 #define ieee_an0_actualSpeeds_dr_10G_DXGXS_SCR 36 3495 #define ieee_an0_actualSpeeds_dr_12G_R2 37 3496 #define ieee_an0_actualSpeeds_dr_10G_X2 38 3497 #define ieee_an0_actualSpeeds_dr_40G_KR4 39 3498 #define ieee_an0_actualSpeeds_dr_40G_CR4 40 3499 #define ieee_an0_actualSpeeds_dr_100G_CR10 41 3500 #define ieee_an0_actualSpeeds_dr_15p75G_DXGXS 44 3501 #define ieee_an0_actualSpeeds_dr_20G_KR2 57 3502 #define ieee_an0_actualSpeeds_dr_20G_CR2 58 3503 3504 /**************************************************************************** 3505 * Enums: ieee_an0_actualSpeedsMisc1 3506 */ 3507 #define ieee_an0_actualSpeedsMisc1_dr_2500BRCM_X1 16 3508 #define ieee_an0_actualSpeedsMisc1_dr_5000BRCM_X4 17 3509 #define ieee_an0_actualSpeedsMisc1_dr_6000BRCM_X4 18 3510 #define ieee_an0_actualSpeedsMisc1_dr_10GHiGig_X4 19 3511 #define ieee_an0_actualSpeedsMisc1_dr_10GBASE_CX4 20 3512 #define ieee_an0_actualSpeedsMisc1_dr_12GHiGig_X4 21 3513 #define ieee_an0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3514 #define ieee_an0_actualSpeedsMisc1_dr_13GHiGig_X4 23 3515 #define ieee_an0_actualSpeedsMisc1_dr_15GHiGig_X4 24 3516 #define ieee_an0_actualSpeedsMisc1_dr_16GHiGig_X4 25 3517 #define ieee_an0_actualSpeedsMisc1_dr_5000BRCM_X1 26 3518 #define ieee_an0_actualSpeedsMisc1_dr_6363BRCM_X1 27 3519 #define ieee_an0_actualSpeedsMisc1_dr_20GHiGig_X4 28 3520 #define ieee_an0_actualSpeedsMisc1_dr_21GHiGig_X4 29 3521 #define ieee_an0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3522 #define ieee_an0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3523 3524 /**************************************************************************** 3525 * Enums: ieee_an0_IndLaneModes 3526 */ 3527 #define ieee_an0_IndLaneModes_SWSDR_div2 0 3528 #define ieee_an0_IndLaneModes_SWSDR_div1 1 3529 #define ieee_an0_IndLaneModes_DWSDR_div2 2 3530 #define ieee_an0_IndLaneModes_DWSDR_div1 3 3531 3532 /**************************************************************************** 3533 * Enums: ieee_an0_prbsSelect 3534 */ 3535 #define ieee_an0_prbsSelect_prbs7 0 3536 #define ieee_an0_prbsSelect_prbs15 1 3537 #define ieee_an0_prbsSelect_prbs23 2 3538 #define ieee_an0_prbsSelect_prbs31 3 3539 3540 /**************************************************************************** 3541 * Enums: ieee_an0_vcoDivider 3542 */ 3543 #define ieee_an0_vcoDivider_div32 0 3544 #define ieee_an0_vcoDivider_div36 1 3545 #define ieee_an0_vcoDivider_div40 2 3546 #define ieee_an0_vcoDivider_div42 3 3547 #define ieee_an0_vcoDivider_div48 4 3548 #define ieee_an0_vcoDivider_div50 5 3549 #define ieee_an0_vcoDivider_div52 6 3550 #define ieee_an0_vcoDivider_div54 7 3551 #define ieee_an0_vcoDivider_div60 8 3552 #define ieee_an0_vcoDivider_div64 9 3553 #define ieee_an0_vcoDivider_div66 10 3554 #define ieee_an0_vcoDivider_div68 11 3555 #define ieee_an0_vcoDivider_div70 12 3556 #define ieee_an0_vcoDivider_div80 13 3557 #define ieee_an0_vcoDivider_div92 14 3558 #define ieee_an0_vcoDivider_div100 15 3559 3560 /**************************************************************************** 3561 * Enums: ieee_an0_refClkSelect 3562 */ 3563 #define ieee_an0_refClkSelect_clk_25MHz 0 3564 #define ieee_an0_refClkSelect_clk_100MHz 1 3565 #define ieee_an0_refClkSelect_clk_125MHz 2 3566 #define ieee_an0_refClkSelect_clk_156p25MHz 3 3567 #define ieee_an0_refClkSelect_clk_187p5MHz 4 3568 #define ieee_an0_refClkSelect_clk_161p25Mhz 5 3569 #define ieee_an0_refClkSelect_clk_50Mhz 6 3570 #define ieee_an0_refClkSelect_clk_106p25Mhz 7 3571 3572 /**************************************************************************** 3573 * Enums: ieee_an0_aerMMDdevTypeSelect 3574 */ 3575 #define ieee_an0_aerMMDdevTypeSelect_combo_core 0 3576 #define ieee_an0_aerMMDdevTypeSelect_PMA_PMD 1 3577 #define ieee_an0_aerMMDdevTypeSelect_PCS 3 3578 #define ieee_an0_aerMMDdevTypeSelect_PHY 4 3579 #define ieee_an0_aerMMDdevTypeSelect_DTE 5 3580 #define ieee_an0_aerMMDdevTypeSelect_CL73_AN 7 3581 3582 /**************************************************************************** 3583 * Enums: ieee_an0_aerMMDportSelect 3584 */ 3585 #define ieee_an0_aerMMDportSelect_ln0 0 3586 #define ieee_an0_aerMMDportSelect_ln1 1 3587 #define ieee_an0_aerMMDportSelect_ln2 2 3588 #define ieee_an0_aerMMDportSelect_ln3 3 3589 #define ieee_an0_aerMMDportSelect_BCST_ln0_1_2_3 511 3590 #define ieee_an0_aerMMDportSelect_BCST_ln0_1 512 3591 #define ieee_an0_aerMMDportSelect_BCST_ln2_3 513 3592 3593 /**************************************************************************** 3594 * Enums: ieee_an0_firmwareModeSelect 3595 */ 3596 #define ieee_an0_firmwareModeSelect_DEFAULT 0 3597 #define ieee_an0_firmwareModeSelect_SFP_OPT_LR 1 3598 #define ieee_an0_firmwareModeSelect_SFP_DAC 2 3599 #define ieee_an0_firmwareModeSelect_XLAUI 3 3600 #define ieee_an0_firmwareModeSelect_LONG_CH_6G 4 3601 3602 /**************************************************************************** 3603 * Enums: ieee_an0_tempIdxSelect 3604 */ 3605 #define ieee_an0_tempIdxSelect_LTE__22p9C 15 3606 #define ieee_an0_tempIdxSelect_LTE__12p6C 14 3607 #define ieee_an0_tempIdxSelect_LTE__3p0C 13 3608 #define ieee_an0_tempIdxSelect_LTE_6p7C 12 3609 #define ieee_an0_tempIdxSelect_LTE_16p4C 11 3610 #define ieee_an0_tempIdxSelect_LTE_26p6C 10 3611 #define ieee_an0_tempIdxSelect_LTE_36p3C 9 3612 #define ieee_an0_tempIdxSelect_LTE_46p0C 8 3613 #define ieee_an0_tempIdxSelect_LTE_56p2C 7 3614 #define ieee_an0_tempIdxSelect_LTE_65p9C 6 3615 #define ieee_an0_tempIdxSelect_LTE_75p6C 5 3616 #define ieee_an0_tempIdxSelect_LTE_85p3C 4 3617 #define ieee_an0_tempIdxSelect_LTE_95p5C 3 3618 #define ieee_an0_tempIdxSelect_LTE_105p2C 2 3619 #define ieee_an0_tempIdxSelect_LTE_114p9C 1 3620 #define ieee_an0_tempIdxSelect_LTE_125p1C 0 3621 3622 /**************************************************************************** 3623 * Enums: ieee_an3_cl36TxEEEStates_l 3624 */ 3625 #define ieee_an3_cl36TxEEEStates_l_TX_REFRESH 8 3626 #define ieee_an3_cl36TxEEEStates_l_TX_QUIET 4 3627 #define ieee_an3_cl36TxEEEStates_l_TX_SLEEP 2 3628 #define ieee_an3_cl36TxEEEStates_l_TX_ACTIVE 1 3629 3630 /**************************************************************************** 3631 * Enums: ieee_an3_cl36TxEEEStates_c 3632 */ 3633 #define ieee_an3_cl36TxEEEStates_c_TX_REFRESH 3 3634 #define ieee_an3_cl36TxEEEStates_c_TX_QUIET 2 3635 #define ieee_an3_cl36TxEEEStates_c_TX_SLEEP 1 3636 #define ieee_an3_cl36TxEEEStates_c_TX_ACTIVE 0 3637 3638 /**************************************************************************** 3639 * Enums: ieee_an3_cl49TxEEEStates_l 3640 */ 3641 #define ieee_an3_cl49TxEEEStates_l_SCR_RESET_2 64 3642 #define ieee_an3_cl49TxEEEStates_l_SCR_RESET_1 32 3643 #define ieee_an3_cl49TxEEEStates_l_TX_WAKE 16 3644 #define ieee_an3_cl49TxEEEStates_l_TX_REFRESH 8 3645 #define ieee_an3_cl49TxEEEStates_l_TX_QUIET 4 3646 #define ieee_an3_cl49TxEEEStates_l_TX_SLEEP 2 3647 #define ieee_an3_cl49TxEEEStates_l_TX_ACTIVE 1 3648 3649 /**************************************************************************** 3650 * Enums: ieee_an3_cl49TxEEEStates_c 3651 */ 3652 #define ieee_an3_cl49TxEEEStates_c_SCR_RESET_2 6 3653 #define ieee_an3_cl49TxEEEStates_c_SCR_RESET_1 5 3654 #define ieee_an3_cl49TxEEEStates_c_TX_WAKE 4 3655 #define ieee_an3_cl49TxEEEStates_c_TX_REFRESH 3 3656 #define ieee_an3_cl49TxEEEStates_c_TX_QUIET 2 3657 #define ieee_an3_cl49TxEEEStates_c_TX_SLEEP 1 3658 #define ieee_an3_cl49TxEEEStates_c_TX_ACTIVE 0 3659 3660 /**************************************************************************** 3661 * Enums: ieee_an3_cl36RxEEEStates_l 3662 */ 3663 #define ieee_an3_cl36RxEEEStates_l_RX_LINK_FAIL 32 3664 #define ieee_an3_cl36RxEEEStates_l_RX_WTF 16 3665 #define ieee_an3_cl36RxEEEStates_l_RX_WAKE 8 3666 #define ieee_an3_cl36RxEEEStates_l_RX_QUIET 4 3667 #define ieee_an3_cl36RxEEEStates_l_RX_SLEEP 2 3668 #define ieee_an3_cl36RxEEEStates_l_RX_ACTIVE 1 3669 3670 /**************************************************************************** 3671 * Enums: ieee_an3_cl36RxEEEStates_c 3672 */ 3673 #define ieee_an3_cl36RxEEEStates_c_RX_LINK_FAIL 5 3674 #define ieee_an3_cl36RxEEEStates_c_RX_WTF 4 3675 #define ieee_an3_cl36RxEEEStates_c_RX_WAKE 3 3676 #define ieee_an3_cl36RxEEEStates_c_RX_QUIET 2 3677 #define ieee_an3_cl36RxEEEStates_c_RX_SLEEP 1 3678 #define ieee_an3_cl36RxEEEStates_c_RX_ACTIVE 0 3679 3680 /**************************************************************************** 3681 * Enums: ieee_an3_cl49RxEEEStates_l 3682 */ 3683 #define ieee_an3_cl49RxEEEStates_l_RX_LINK_FAIL 32 3684 #define ieee_an3_cl49RxEEEStates_l_RX_WTF 16 3685 #define ieee_an3_cl49RxEEEStates_l_RX_WAKE 8 3686 #define ieee_an3_cl49RxEEEStates_l_RX_QUIET 4 3687 #define ieee_an3_cl49RxEEEStates_l_RX_SLEEP 2 3688 #define ieee_an3_cl49RxEEEStates_l_RX_ACTIVE 1 3689 3690 /**************************************************************************** 3691 * Enums: ieee_an3_cl49RxEEEStates_c 3692 */ 3693 #define ieee_an3_cl49RxEEEStates_c_RX_LINK_FAIL 5 3694 #define ieee_an3_cl49RxEEEStates_c_RX_WTF 4 3695 #define ieee_an3_cl49RxEEEStates_c_RX_WAKE 3 3696 #define ieee_an3_cl49RxEEEStates_c_RX_QUIET 2 3697 #define ieee_an3_cl49RxEEEStates_c_RX_SLEEP 1 3698 #define ieee_an3_cl49RxEEEStates_c_RX_ACTIVE 0 3699 3700 /**************************************************************************** 3701 * Enums: ieee_an3_cl48TxEEEStates_l 3702 */ 3703 #define ieee_an3_cl48TxEEEStates_l_TX_REFRESH 8 3704 #define ieee_an3_cl48TxEEEStates_l_TX_QUIET 4 3705 #define ieee_an3_cl48TxEEEStates_l_TX_SLEEP 2 3706 #define ieee_an3_cl48TxEEEStates_l_TX_ACTIVE 1 3707 3708 /**************************************************************************** 3709 * Enums: ieee_an3_cl48TxEEEStates_c 3710 */ 3711 #define ieee_an3_cl48TxEEEStates_c_TX_REFRESH 3 3712 #define ieee_an3_cl48TxEEEStates_c_TX_QUIET 2 3713 #define ieee_an3_cl48TxEEEStates_c_TX_SLEEP 1 3714 #define ieee_an3_cl48TxEEEStates_c_TX_ACTIVE 0 3715 3716 /**************************************************************************** 3717 * Enums: ieee_an3_cl48RxEEEStates_l 3718 */ 3719 #define ieee_an3_cl48RxEEEStates_l_RX_LINK_FAIL 32 3720 #define ieee_an3_cl48RxEEEStates_l_RX_WAKE 16 3721 #define ieee_an3_cl48RxEEEStates_l_RX_QUIET 8 3722 #define ieee_an3_cl48RxEEEStates_l_RX_DEACT 4 3723 #define ieee_an3_cl48RxEEEStates_l_RX_SLEEP 2 3724 #define ieee_an3_cl48RxEEEStates_l_RX_ACTIVE 1 3725 3726 /**************************************************************************** 3727 * Enums: ieee_an3_cl48RxEEEStates_c 3728 */ 3729 #define ieee_an3_cl48RxEEEStates_c_RX_LINK_FAIL 5 3730 #define ieee_an3_cl48RxEEEStates_c_RX_WAKE 4 3731 #define ieee_an3_cl48RxEEEStates_c_RX_QUIET 3 3732 #define ieee_an3_cl48RxEEEStates_c_RX_DEACT 2 3733 #define ieee_an3_cl48RxEEEStates_c_RX_SLEEP 1 3734 #define ieee_an3_cl48RxEEEStates_c_RX_ACTIVE 0 3735 3736 /**************************************************************************** 3737 * Enums: ieee_an3_IQP_Options 3738 */ 3739 #define ieee_an3_IQP_Options_i50uA 0 3740 #define ieee_an3_IQP_Options_i100uA 1 3741 #define ieee_an3_IQP_Options_i150uA 2 3742 #define ieee_an3_IQP_Options_i200uA 3 3743 #define ieee_an3_IQP_Options_i250uA 4 3744 #define ieee_an3_IQP_Options_i300uA 5 3745 #define ieee_an3_IQP_Options_i350uA 6 3746 #define ieee_an3_IQP_Options_i400uA 7 3747 #define ieee_an3_IQP_Options_i450uA 8 3748 #define ieee_an3_IQP_Options_i500uA 9 3749 #define ieee_an3_IQP_Options_i550uA 10 3750 #define ieee_an3_IQP_Options_i600uA 11 3751 #define ieee_an3_IQP_Options_i650uA 12 3752 #define ieee_an3_IQP_Options_i700uA 13 3753 #define ieee_an3_IQP_Options_i750uA 14 3754 #define ieee_an3_IQP_Options_i800uA 15 3755 3756 /**************************************************************************** 3757 * Enums: ieee_an3_IDriver_Options 3758 */ 3759 #define ieee_an3_IDriver_Options_v680mV 0 3760 #define ieee_an3_IDriver_Options_v730mV 1 3761 #define ieee_an3_IDriver_Options_v780mV 2 3762 #define ieee_an3_IDriver_Options_v830mV 3 3763 #define ieee_an3_IDriver_Options_v880mV 4 3764 #define ieee_an3_IDriver_Options_v930mV 5 3765 #define ieee_an3_IDriver_Options_v980mV 6 3766 #define ieee_an3_IDriver_Options_v1010mV 7 3767 #define ieee_an3_IDriver_Options_v1040mV 8 3768 #define ieee_an3_IDriver_Options_v1060mV 9 3769 #define ieee_an3_IDriver_Options_v1070mV 10 3770 #define ieee_an3_IDriver_Options_v1080mV 11 3771 #define ieee_an3_IDriver_Options_v1085mV 12 3772 #define ieee_an3_IDriver_Options_v1090mV 13 3773 #define ieee_an3_IDriver_Options_v1095mV 14 3774 #define ieee_an3_IDriver_Options_v1100mV 15 3775 3776 /**************************************************************************** 3777 * Enums: ieee_an3_operationModes 3778 */ 3779 #define ieee_an3_operationModes_XGXS 0 3780 #define ieee_an3_operationModes_XGXG_nCC 1 3781 #define ieee_an3_operationModes_Indlane_OS8 4 3782 #define ieee_an3_operationModes_IndLane_OS5 5 3783 #define ieee_an3_operationModes_PCI 7 3784 #define ieee_an3_operationModes_XGXS_nLQ 8 3785 #define ieee_an3_operationModes_XGXS_nLQnCC 9 3786 #define ieee_an3_operationModes_PBypass 10 3787 #define ieee_an3_operationModes_PBypass_nDSK 11 3788 #define ieee_an3_operationModes_ComboCoreMode 12 3789 #define ieee_an3_operationModes_Clocks_off 15 3790 3791 /**************************************************************************** 3792 * Enums: ieee_an3_actualSpeeds 3793 */ 3794 #define ieee_an3_actualSpeeds_dr_10M 0 3795 #define ieee_an3_actualSpeeds_dr_100M 1 3796 #define ieee_an3_actualSpeeds_dr_1G 2 3797 #define ieee_an3_actualSpeeds_dr_2p5G 3 3798 #define ieee_an3_actualSpeeds_dr_5G_X4 4 3799 #define ieee_an3_actualSpeeds_dr_6G_X4 5 3800 #define ieee_an3_actualSpeeds_dr_10G_HiG 6 3801 #define ieee_an3_actualSpeeds_dr_10G_CX4 7 3802 #define ieee_an3_actualSpeeds_dr_12G_HiG 8 3803 #define ieee_an3_actualSpeeds_dr_12p5G_X4 9 3804 #define ieee_an3_actualSpeeds_dr_13G_X4 10 3805 #define ieee_an3_actualSpeeds_dr_15G_X4 11 3806 #define ieee_an3_actualSpeeds_dr_16G_X4 12 3807 #define ieee_an3_actualSpeeds_dr_1G_KX 13 3808 #define ieee_an3_actualSpeeds_dr_10G_KX4 14 3809 #define ieee_an3_actualSpeeds_dr_10G_KR 15 3810 #define ieee_an3_actualSpeeds_dr_5G 16 3811 #define ieee_an3_actualSpeeds_dr_6p4G 17 3812 #define ieee_an3_actualSpeeds_dr_20G_X4 18 3813 #define ieee_an3_actualSpeeds_dr_21G_X4 19 3814 #define ieee_an3_actualSpeeds_dr_25G_X4 20 3815 #define ieee_an3_actualSpeeds_dr_10G_HiG_DXGXS 21 3816 #define ieee_an3_actualSpeeds_dr_10G_DXGXS 22 3817 #define ieee_an3_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3818 #define ieee_an3_actualSpeeds_dr_10p5G_DXGXS 24 3819 #define ieee_an3_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3820 #define ieee_an3_actualSpeeds_dr_12p773G_DXGXS 26 3821 #define ieee_an3_actualSpeeds_dr_10G_XFI 27 3822 #define ieee_an3_actualSpeeds_dr_40G 28 3823 #define ieee_an3_actualSpeeds_dr_20G_HiG_DXGXS 29 3824 #define ieee_an3_actualSpeeds_dr_20G_DXGXS 30 3825 #define ieee_an3_actualSpeeds_dr_10G_SFI 31 3826 #define ieee_an3_actualSpeeds_dr_31p5G 32 3827 #define ieee_an3_actualSpeeds_dr_32p7G 33 3828 #define ieee_an3_actualSpeeds_dr_20G_SCR 34 3829 #define ieee_an3_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3830 #define ieee_an3_actualSpeeds_dr_10G_DXGXS_SCR 36 3831 #define ieee_an3_actualSpeeds_dr_12G_R2 37 3832 #define ieee_an3_actualSpeeds_dr_10G_X2 38 3833 #define ieee_an3_actualSpeeds_dr_40G_KR4 39 3834 #define ieee_an3_actualSpeeds_dr_40G_CR4 40 3835 #define ieee_an3_actualSpeeds_dr_100G_CR10 41 3836 #define ieee_an3_actualSpeeds_dr_15p75G_DXGXS 44 3837 #define ieee_an3_actualSpeeds_dr_20G_KR2 57 3838 #define ieee_an3_actualSpeeds_dr_20G_CR2 58 3839 3840 /**************************************************************************** 3841 * Enums: ieee_an3_actualSpeedsMisc1 3842 */ 3843 #define ieee_an3_actualSpeedsMisc1_dr_2500BRCM_X1 16 3844 #define ieee_an3_actualSpeedsMisc1_dr_5000BRCM_X4 17 3845 #define ieee_an3_actualSpeedsMisc1_dr_6000BRCM_X4 18 3846 #define ieee_an3_actualSpeedsMisc1_dr_10GHiGig_X4 19 3847 #define ieee_an3_actualSpeedsMisc1_dr_10GBASE_CX4 20 3848 #define ieee_an3_actualSpeedsMisc1_dr_12GHiGig_X4 21 3849 #define ieee_an3_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3850 #define ieee_an3_actualSpeedsMisc1_dr_13GHiGig_X4 23 3851 #define ieee_an3_actualSpeedsMisc1_dr_15GHiGig_X4 24 3852 #define ieee_an3_actualSpeedsMisc1_dr_16GHiGig_X4 25 3853 #define ieee_an3_actualSpeedsMisc1_dr_5000BRCM_X1 26 3854 #define ieee_an3_actualSpeedsMisc1_dr_6363BRCM_X1 27 3855 #define ieee_an3_actualSpeedsMisc1_dr_20GHiGig_X4 28 3856 #define ieee_an3_actualSpeedsMisc1_dr_21GHiGig_X4 29 3857 #define ieee_an3_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3858 #define ieee_an3_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3859 3860 /**************************************************************************** 3861 * Enums: ieee_an3_IndLaneModes 3862 */ 3863 #define ieee_an3_IndLaneModes_SWSDR_div2 0 3864 #define ieee_an3_IndLaneModes_SWSDR_div1 1 3865 #define ieee_an3_IndLaneModes_DWSDR_div2 2 3866 #define ieee_an3_IndLaneModes_DWSDR_div1 3 3867 3868 /**************************************************************************** 3869 * Enums: ieee_an3_prbsSelect 3870 */ 3871 #define ieee_an3_prbsSelect_prbs7 0 3872 #define ieee_an3_prbsSelect_prbs15 1 3873 #define ieee_an3_prbsSelect_prbs23 2 3874 #define ieee_an3_prbsSelect_prbs31 3 3875 3876 /**************************************************************************** 3877 * Enums: ieee_an3_vcoDivider 3878 */ 3879 #define ieee_an3_vcoDivider_div32 0 3880 #define ieee_an3_vcoDivider_div36 1 3881 #define ieee_an3_vcoDivider_div40 2 3882 #define ieee_an3_vcoDivider_div42 3 3883 #define ieee_an3_vcoDivider_div48 4 3884 #define ieee_an3_vcoDivider_div50 5 3885 #define ieee_an3_vcoDivider_div52 6 3886 #define ieee_an3_vcoDivider_div54 7 3887 #define ieee_an3_vcoDivider_div60 8 3888 #define ieee_an3_vcoDivider_div64 9 3889 #define ieee_an3_vcoDivider_div66 10 3890 #define ieee_an3_vcoDivider_div68 11 3891 #define ieee_an3_vcoDivider_div70 12 3892 #define ieee_an3_vcoDivider_div80 13 3893 #define ieee_an3_vcoDivider_div92 14 3894 #define ieee_an3_vcoDivider_div100 15 3895 3896 /**************************************************************************** 3897 * Enums: ieee_an3_refClkSelect 3898 */ 3899 #define ieee_an3_refClkSelect_clk_25MHz 0 3900 #define ieee_an3_refClkSelect_clk_100MHz 1 3901 #define ieee_an3_refClkSelect_clk_125MHz 2 3902 #define ieee_an3_refClkSelect_clk_156p25MHz 3 3903 #define ieee_an3_refClkSelect_clk_187p5MHz 4 3904 #define ieee_an3_refClkSelect_clk_161p25Mhz 5 3905 #define ieee_an3_refClkSelect_clk_50Mhz 6 3906 #define ieee_an3_refClkSelect_clk_106p25Mhz 7 3907 3908 /**************************************************************************** 3909 * Enums: ieee_an3_aerMMDdevTypeSelect 3910 */ 3911 #define ieee_an3_aerMMDdevTypeSelect_combo_core 0 3912 #define ieee_an3_aerMMDdevTypeSelect_PMA_PMD 1 3913 #define ieee_an3_aerMMDdevTypeSelect_PCS 3 3914 #define ieee_an3_aerMMDdevTypeSelect_PHY 4 3915 #define ieee_an3_aerMMDdevTypeSelect_DTE 5 3916 #define ieee_an3_aerMMDdevTypeSelect_CL73_AN 7 3917 3918 /**************************************************************************** 3919 * Enums: ieee_an3_aerMMDportSelect 3920 */ 3921 #define ieee_an3_aerMMDportSelect_ln0 0 3922 #define ieee_an3_aerMMDportSelect_ln1 1 3923 #define ieee_an3_aerMMDportSelect_ln2 2 3924 #define ieee_an3_aerMMDportSelect_ln3 3 3925 #define ieee_an3_aerMMDportSelect_BCST_ln0_1_2_3 511 3926 #define ieee_an3_aerMMDportSelect_BCST_ln0_1 512 3927 #define ieee_an3_aerMMDportSelect_BCST_ln2_3 513 3928 3929 /**************************************************************************** 3930 * Enums: ieee_an3_firmwareModeSelect 3931 */ 3932 #define ieee_an3_firmwareModeSelect_DEFAULT 0 3933 #define ieee_an3_firmwareModeSelect_SFP_OPT_LR 1 3934 #define ieee_an3_firmwareModeSelect_SFP_DAC 2 3935 #define ieee_an3_firmwareModeSelect_XLAUI 3 3936 #define ieee_an3_firmwareModeSelect_LONG_CH_6G 4 3937 3938 /**************************************************************************** 3939 * Enums: ieee_an3_tempIdxSelect 3940 */ 3941 #define ieee_an3_tempIdxSelect_LTE__22p9C 15 3942 #define ieee_an3_tempIdxSelect_LTE__12p6C 14 3943 #define ieee_an3_tempIdxSelect_LTE__3p0C 13 3944 #define ieee_an3_tempIdxSelect_LTE_6p7C 12 3945 #define ieee_an3_tempIdxSelect_LTE_16p4C 11 3946 #define ieee_an3_tempIdxSelect_LTE_26p6C 10 3947 #define ieee_an3_tempIdxSelect_LTE_36p3C 9 3948 #define ieee_an3_tempIdxSelect_LTE_46p0C 8 3949 #define ieee_an3_tempIdxSelect_LTE_56p2C 7 3950 #define ieee_an3_tempIdxSelect_LTE_65p9C 6 3951 #define ieee_an3_tempIdxSelect_LTE_75p6C 5 3952 #define ieee_an3_tempIdxSelect_LTE_85p3C 4 3953 #define ieee_an3_tempIdxSelect_LTE_95p5C 3 3954 #define ieee_an3_tempIdxSelect_LTE_105p2C 2 3955 #define ieee_an3_tempIdxSelect_LTE_114p9C 1 3956 #define ieee_an3_tempIdxSelect_LTE_125p1C 0 3957 3958 /**************************************************************************** 3959 * Enums: main0_cl36TxEEEStates_l 3960 */ 3961 #define main0_cl36TxEEEStates_l_TX_REFRESH 8 3962 #define main0_cl36TxEEEStates_l_TX_QUIET 4 3963 #define main0_cl36TxEEEStates_l_TX_SLEEP 2 3964 #define main0_cl36TxEEEStates_l_TX_ACTIVE 1 3965 3966 /**************************************************************************** 3967 * Enums: main0_cl36TxEEEStates_c 3968 */ 3969 #define main0_cl36TxEEEStates_c_TX_REFRESH 3 3970 #define main0_cl36TxEEEStates_c_TX_QUIET 2 3971 #define main0_cl36TxEEEStates_c_TX_SLEEP 1 3972 #define main0_cl36TxEEEStates_c_TX_ACTIVE 0 3973 3974 /**************************************************************************** 3975 * Enums: main0_cl49TxEEEStates_l 3976 */ 3977 #define main0_cl49TxEEEStates_l_SCR_RESET_2 64 3978 #define main0_cl49TxEEEStates_l_SCR_RESET_1 32 3979 #define main0_cl49TxEEEStates_l_TX_WAKE 16 3980 #define main0_cl49TxEEEStates_l_TX_REFRESH 8 3981 #define main0_cl49TxEEEStates_l_TX_QUIET 4 3982 #define main0_cl49TxEEEStates_l_TX_SLEEP 2 3983 #define main0_cl49TxEEEStates_l_TX_ACTIVE 1 3984 3985 /**************************************************************************** 3986 * Enums: main0_cl49TxEEEStates_c 3987 */ 3988 #define main0_cl49TxEEEStates_c_SCR_RESET_2 6 3989 #define main0_cl49TxEEEStates_c_SCR_RESET_1 5 3990 #define main0_cl49TxEEEStates_c_TX_WAKE 4 3991 #define main0_cl49TxEEEStates_c_TX_REFRESH 3 3992 #define main0_cl49TxEEEStates_c_TX_QUIET 2 3993 #define main0_cl49TxEEEStates_c_TX_SLEEP 1 3994 #define main0_cl49TxEEEStates_c_TX_ACTIVE 0 3995 3996 /**************************************************************************** 3997 * Enums: main0_cl36RxEEEStates_l 3998 */ 3999 #define main0_cl36RxEEEStates_l_RX_LINK_FAIL 32 4000 #define main0_cl36RxEEEStates_l_RX_WTF 16 4001 #define main0_cl36RxEEEStates_l_RX_WAKE 8 4002 #define main0_cl36RxEEEStates_l_RX_QUIET 4 4003 #define main0_cl36RxEEEStates_l_RX_SLEEP 2 4004 #define main0_cl36RxEEEStates_l_RX_ACTIVE 1 4005 4006 /**************************************************************************** 4007 * Enums: main0_cl36RxEEEStates_c 4008 */ 4009 #define main0_cl36RxEEEStates_c_RX_LINK_FAIL 5 4010 #define main0_cl36RxEEEStates_c_RX_WTF 4 4011 #define main0_cl36RxEEEStates_c_RX_WAKE 3 4012 #define main0_cl36RxEEEStates_c_RX_QUIET 2 4013 #define main0_cl36RxEEEStates_c_RX_SLEEP 1 4014 #define main0_cl36RxEEEStates_c_RX_ACTIVE 0 4015 4016 /**************************************************************************** 4017 * Enums: main0_cl49RxEEEStates_l 4018 */ 4019 #define main0_cl49RxEEEStates_l_RX_LINK_FAIL 32 4020 #define main0_cl49RxEEEStates_l_RX_WTF 16 4021 #define main0_cl49RxEEEStates_l_RX_WAKE 8 4022 #define main0_cl49RxEEEStates_l_RX_QUIET 4 4023 #define main0_cl49RxEEEStates_l_RX_SLEEP 2 4024 #define main0_cl49RxEEEStates_l_RX_ACTIVE 1 4025 4026 /**************************************************************************** 4027 * Enums: main0_cl49RxEEEStates_c 4028 */ 4029 #define main0_cl49RxEEEStates_c_RX_LINK_FAIL 5 4030 #define main0_cl49RxEEEStates_c_RX_WTF 4 4031 #define main0_cl49RxEEEStates_c_RX_WAKE 3 4032 #define main0_cl49RxEEEStates_c_RX_QUIET 2 4033 #define main0_cl49RxEEEStates_c_RX_SLEEP 1 4034 #define main0_cl49RxEEEStates_c_RX_ACTIVE 0 4035 4036 /**************************************************************************** 4037 * Enums: main0_cl48TxEEEStates_l 4038 */ 4039 #define main0_cl48TxEEEStates_l_TX_REFRESH 8 4040 #define main0_cl48TxEEEStates_l_TX_QUIET 4 4041 #define main0_cl48TxEEEStates_l_TX_SLEEP 2 4042 #define main0_cl48TxEEEStates_l_TX_ACTIVE 1 4043 4044 /**************************************************************************** 4045 * Enums: main0_cl48TxEEEStates_c 4046 */ 4047 #define main0_cl48TxEEEStates_c_TX_REFRESH 3 4048 #define main0_cl48TxEEEStates_c_TX_QUIET 2 4049 #define main0_cl48TxEEEStates_c_TX_SLEEP 1 4050 #define main0_cl48TxEEEStates_c_TX_ACTIVE 0 4051 4052 /**************************************************************************** 4053 * Enums: main0_cl48RxEEEStates_l 4054 */ 4055 #define main0_cl48RxEEEStates_l_RX_LINK_FAIL 32 4056 #define main0_cl48RxEEEStates_l_RX_WAKE 16 4057 #define main0_cl48RxEEEStates_l_RX_QUIET 8 4058 #define main0_cl48RxEEEStates_l_RX_DEACT 4 4059 #define main0_cl48RxEEEStates_l_RX_SLEEP 2 4060 #define main0_cl48RxEEEStates_l_RX_ACTIVE 1 4061 4062 /**************************************************************************** 4063 * Enums: main0_cl48RxEEEStates_c 4064 */ 4065 #define main0_cl48RxEEEStates_c_RX_LINK_FAIL 5 4066 #define main0_cl48RxEEEStates_c_RX_WAKE 4 4067 #define main0_cl48RxEEEStates_c_RX_QUIET 3 4068 #define main0_cl48RxEEEStates_c_RX_DEACT 2 4069 #define main0_cl48RxEEEStates_c_RX_SLEEP 1 4070 #define main0_cl48RxEEEStates_c_RX_ACTIVE 0 4071 4072 /**************************************************************************** 4073 * Enums: main0_IQP_Options 4074 */ 4075 #define main0_IQP_Options_i50uA 0 4076 #define main0_IQP_Options_i100uA 1 4077 #define main0_IQP_Options_i150uA 2 4078 #define main0_IQP_Options_i200uA 3 4079 #define main0_IQP_Options_i250uA 4 4080 #define main0_IQP_Options_i300uA 5 4081 #define main0_IQP_Options_i350uA 6 4082 #define main0_IQP_Options_i400uA 7 4083 #define main0_IQP_Options_i450uA 8 4084 #define main0_IQP_Options_i500uA 9 4085 #define main0_IQP_Options_i550uA 10 4086 #define main0_IQP_Options_i600uA 11 4087 #define main0_IQP_Options_i650uA 12 4088 #define main0_IQP_Options_i700uA 13 4089 #define main0_IQP_Options_i750uA 14 4090 #define main0_IQP_Options_i800uA 15 4091 4092 /**************************************************************************** 4093 * Enums: main0_IDriver_Options 4094 */ 4095 #define main0_IDriver_Options_v680mV 0 4096 #define main0_IDriver_Options_v730mV 1 4097 #define main0_IDriver_Options_v780mV 2 4098 #define main0_IDriver_Options_v830mV 3 4099 #define main0_IDriver_Options_v880mV 4 4100 #define main0_IDriver_Options_v930mV 5 4101 #define main0_IDriver_Options_v980mV 6 4102 #define main0_IDriver_Options_v1010mV 7 4103 #define main0_IDriver_Options_v1040mV 8 4104 #define main0_IDriver_Options_v1060mV 9 4105 #define main0_IDriver_Options_v1070mV 10 4106 #define main0_IDriver_Options_v1080mV 11 4107 #define main0_IDriver_Options_v1085mV 12 4108 #define main0_IDriver_Options_v1090mV 13 4109 #define main0_IDriver_Options_v1095mV 14 4110 #define main0_IDriver_Options_v1100mV 15 4111 4112 /**************************************************************************** 4113 * Enums: main0_operationModes 4114 */ 4115 #define main0_operationModes_XGXS 0 4116 #define main0_operationModes_XGXG_nCC 1 4117 #define main0_operationModes_Indlane_OS8 4 4118 #define main0_operationModes_IndLane_OS5 5 4119 #define main0_operationModes_PCI 7 4120 #define main0_operationModes_XGXS_nLQ 8 4121 #define main0_operationModes_XGXS_nLQnCC 9 4122 #define main0_operationModes_PBypass 10 4123 #define main0_operationModes_PBypass_nDSK 11 4124 #define main0_operationModes_ComboCoreMode 12 4125 #define main0_operationModes_Clocks_off 15 4126 4127 /**************************************************************************** 4128 * Enums: main0_actualSpeeds 4129 */ 4130 #define main0_actualSpeeds_dr_10M 0 4131 #define main0_actualSpeeds_dr_100M 1 4132 #define main0_actualSpeeds_dr_1G 2 4133 #define main0_actualSpeeds_dr_2p5G 3 4134 #define main0_actualSpeeds_dr_5G_X4 4 4135 #define main0_actualSpeeds_dr_6G_X4 5 4136 #define main0_actualSpeeds_dr_10G_HiG 6 4137 #define main0_actualSpeeds_dr_10G_CX4 7 4138 #define main0_actualSpeeds_dr_12G_HiG 8 4139 #define main0_actualSpeeds_dr_12p5G_X4 9 4140 #define main0_actualSpeeds_dr_13G_X4 10 4141 #define main0_actualSpeeds_dr_15G_X4 11 4142 #define main0_actualSpeeds_dr_16G_X4 12 4143 #define main0_actualSpeeds_dr_1G_KX 13 4144 #define main0_actualSpeeds_dr_10G_KX4 14 4145 #define main0_actualSpeeds_dr_10G_KR 15 4146 #define main0_actualSpeeds_dr_5G 16 4147 #define main0_actualSpeeds_dr_6p4G 17 4148 #define main0_actualSpeeds_dr_20G_X4 18 4149 #define main0_actualSpeeds_dr_21G_X4 19 4150 #define main0_actualSpeeds_dr_25G_X4 20 4151 #define main0_actualSpeeds_dr_10G_HiG_DXGXS 21 4152 #define main0_actualSpeeds_dr_10G_DXGXS 22 4153 #define main0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4154 #define main0_actualSpeeds_dr_10p5G_DXGXS 24 4155 #define main0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4156 #define main0_actualSpeeds_dr_12p773G_DXGXS 26 4157 #define main0_actualSpeeds_dr_10G_XFI 27 4158 #define main0_actualSpeeds_dr_40G 28 4159 #define main0_actualSpeeds_dr_20G_HiG_DXGXS 29 4160 #define main0_actualSpeeds_dr_20G_DXGXS 30 4161 #define main0_actualSpeeds_dr_10G_SFI 31 4162 #define main0_actualSpeeds_dr_31p5G 32 4163 #define main0_actualSpeeds_dr_32p7G 33 4164 #define main0_actualSpeeds_dr_20G_SCR 34 4165 #define main0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4166 #define main0_actualSpeeds_dr_10G_DXGXS_SCR 36 4167 #define main0_actualSpeeds_dr_12G_R2 37 4168 #define main0_actualSpeeds_dr_10G_X2 38 4169 #define main0_actualSpeeds_dr_40G_KR4 39 4170 #define main0_actualSpeeds_dr_40G_CR4 40 4171 #define main0_actualSpeeds_dr_100G_CR10 41 4172 #define main0_actualSpeeds_dr_15p75G_DXGXS 44 4173 #define main0_actualSpeeds_dr_20G_KR2 57 4174 #define main0_actualSpeeds_dr_20G_CR2 58 4175 4176 /**************************************************************************** 4177 * Enums: main0_actualSpeedsMisc1 4178 */ 4179 #define main0_actualSpeedsMisc1_dr_2500BRCM_X1 16 4180 #define main0_actualSpeedsMisc1_dr_5000BRCM_X4 17 4181 #define main0_actualSpeedsMisc1_dr_6000BRCM_X4 18 4182 #define main0_actualSpeedsMisc1_dr_10GHiGig_X4 19 4183 #define main0_actualSpeedsMisc1_dr_10GBASE_CX4 20 4184 #define main0_actualSpeedsMisc1_dr_12GHiGig_X4 21 4185 #define main0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4186 #define main0_actualSpeedsMisc1_dr_13GHiGig_X4 23 4187 #define main0_actualSpeedsMisc1_dr_15GHiGig_X4 24 4188 #define main0_actualSpeedsMisc1_dr_16GHiGig_X4 25 4189 #define main0_actualSpeedsMisc1_dr_5000BRCM_X1 26 4190 #define main0_actualSpeedsMisc1_dr_6363BRCM_X1 27 4191 #define main0_actualSpeedsMisc1_dr_20GHiGig_X4 28 4192 #define main0_actualSpeedsMisc1_dr_21GHiGig_X4 29 4193 #define main0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4194 #define main0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4195 4196 /**************************************************************************** 4197 * Enums: main0_IndLaneModes 4198 */ 4199 #define main0_IndLaneModes_SWSDR_div2 0 4200 #define main0_IndLaneModes_SWSDR_div1 1 4201 #define main0_IndLaneModes_DWSDR_div2 2 4202 #define main0_IndLaneModes_DWSDR_div1 3 4203 4204 /**************************************************************************** 4205 * Enums: main0_prbsSelect 4206 */ 4207 #define main0_prbsSelect_prbs7 0 4208 #define main0_prbsSelect_prbs15 1 4209 #define main0_prbsSelect_prbs23 2 4210 #define main0_prbsSelect_prbs31 3 4211 4212 /**************************************************************************** 4213 * Enums: main0_vcoDivider 4214 */ 4215 #define main0_vcoDivider_div32 0 4216 #define main0_vcoDivider_div36 1 4217 #define main0_vcoDivider_div40 2 4218 #define main0_vcoDivider_div42 3 4219 #define main0_vcoDivider_div48 4 4220 #define main0_vcoDivider_div50 5 4221 #define main0_vcoDivider_div52 6 4222 #define main0_vcoDivider_div54 7 4223 #define main0_vcoDivider_div60 8 4224 #define main0_vcoDivider_div64 9 4225 #define main0_vcoDivider_div66 10 4226 #define main0_vcoDivider_div68 11 4227 #define main0_vcoDivider_div70 12 4228 #define main0_vcoDivider_div80 13 4229 #define main0_vcoDivider_div92 14 4230 #define main0_vcoDivider_div100 15 4231 4232 /**************************************************************************** 4233 * Enums: main0_refClkSelect 4234 */ 4235 #define main0_refClkSelect_clk_25MHz 0 4236 #define main0_refClkSelect_clk_100MHz 1 4237 #define main0_refClkSelect_clk_125MHz 2 4238 #define main0_refClkSelect_clk_156p25MHz 3 4239 #define main0_refClkSelect_clk_187p5MHz 4 4240 #define main0_refClkSelect_clk_161p25Mhz 5 4241 #define main0_refClkSelect_clk_50Mhz 6 4242 #define main0_refClkSelect_clk_106p25Mhz 7 4243 4244 /**************************************************************************** 4245 * Enums: main0_aerMMDdevTypeSelect 4246 */ 4247 #define main0_aerMMDdevTypeSelect_combo_core 0 4248 #define main0_aerMMDdevTypeSelect_PMA_PMD 1 4249 #define main0_aerMMDdevTypeSelect_PCS 3 4250 #define main0_aerMMDdevTypeSelect_PHY 4 4251 #define main0_aerMMDdevTypeSelect_DTE 5 4252 #define main0_aerMMDdevTypeSelect_CL73_AN 7 4253 4254 /**************************************************************************** 4255 * Enums: main0_aerMMDportSelect 4256 */ 4257 #define main0_aerMMDportSelect_ln0 0 4258 #define main0_aerMMDportSelect_ln1 1 4259 #define main0_aerMMDportSelect_ln2 2 4260 #define main0_aerMMDportSelect_ln3 3 4261 #define main0_aerMMDportSelect_BCST_ln0_1_2_3 511 4262 #define main0_aerMMDportSelect_BCST_ln0_1 512 4263 #define main0_aerMMDportSelect_BCST_ln2_3 513 4264 4265 /**************************************************************************** 4266 * Enums: main0_firmwareModeSelect 4267 */ 4268 #define main0_firmwareModeSelect_DEFAULT 0 4269 #define main0_firmwareModeSelect_SFP_OPT_LR 1 4270 #define main0_firmwareModeSelect_SFP_DAC 2 4271 #define main0_firmwareModeSelect_XLAUI 3 4272 #define main0_firmwareModeSelect_LONG_CH_6G 4 4273 4274 /**************************************************************************** 4275 * Enums: main0_tempIdxSelect 4276 */ 4277 #define main0_tempIdxSelect_LTE__22p9C 15 4278 #define main0_tempIdxSelect_LTE__12p6C 14 4279 #define main0_tempIdxSelect_LTE__3p0C 13 4280 #define main0_tempIdxSelect_LTE_6p7C 12 4281 #define main0_tempIdxSelect_LTE_16p4C 11 4282 #define main0_tempIdxSelect_LTE_26p6C 10 4283 #define main0_tempIdxSelect_LTE_36p3C 9 4284 #define main0_tempIdxSelect_LTE_46p0C 8 4285 #define main0_tempIdxSelect_LTE_56p2C 7 4286 #define main0_tempIdxSelect_LTE_65p9C 6 4287 #define main0_tempIdxSelect_LTE_75p6C 5 4288 #define main0_tempIdxSelect_LTE_85p3C 4 4289 #define main0_tempIdxSelect_LTE_95p5C 3 4290 #define main0_tempIdxSelect_LTE_105p2C 2 4291 #define main0_tempIdxSelect_LTE_114p9C 1 4292 #define main0_tempIdxSelect_LTE_125p1C 0 4293 4294 /**************************************************************************** 4295 * Enums: microtmp2_cl36TxEEEStates_l 4296 */ 4297 #define microtmp2_cl36TxEEEStates_l_TX_REFRESH 8 4298 #define microtmp2_cl36TxEEEStates_l_TX_QUIET 4 4299 #define microtmp2_cl36TxEEEStates_l_TX_SLEEP 2 4300 #define microtmp2_cl36TxEEEStates_l_TX_ACTIVE 1 4301 4302 /**************************************************************************** 4303 * Enums: microtmp2_cl36TxEEEStates_c 4304 */ 4305 #define microtmp2_cl36TxEEEStates_c_TX_REFRESH 3 4306 #define microtmp2_cl36TxEEEStates_c_TX_QUIET 2 4307 #define microtmp2_cl36TxEEEStates_c_TX_SLEEP 1 4308 #define microtmp2_cl36TxEEEStates_c_TX_ACTIVE 0 4309 4310 /**************************************************************************** 4311 * Enums: microtmp2_cl49TxEEEStates_l 4312 */ 4313 #define microtmp2_cl49TxEEEStates_l_SCR_RESET_2 64 4314 #define microtmp2_cl49TxEEEStates_l_SCR_RESET_1 32 4315 #define microtmp2_cl49TxEEEStates_l_TX_WAKE 16 4316 #define microtmp2_cl49TxEEEStates_l_TX_REFRESH 8 4317 #define microtmp2_cl49TxEEEStates_l_TX_QUIET 4 4318 #define microtmp2_cl49TxEEEStates_l_TX_SLEEP 2 4319 #define microtmp2_cl49TxEEEStates_l_TX_ACTIVE 1 4320 4321 /**************************************************************************** 4322 * Enums: microtmp2_cl49TxEEEStates_c 4323 */ 4324 #define microtmp2_cl49TxEEEStates_c_SCR_RESET_2 6 4325 #define microtmp2_cl49TxEEEStates_c_SCR_RESET_1 5 4326 #define microtmp2_cl49TxEEEStates_c_TX_WAKE 4 4327 #define microtmp2_cl49TxEEEStates_c_TX_REFRESH 3 4328 #define microtmp2_cl49TxEEEStates_c_TX_QUIET 2 4329 #define microtmp2_cl49TxEEEStates_c_TX_SLEEP 1 4330 #define microtmp2_cl49TxEEEStates_c_TX_ACTIVE 0 4331 4332 /**************************************************************************** 4333 * Enums: microtmp2_cl36RxEEEStates_l 4334 */ 4335 #define microtmp2_cl36RxEEEStates_l_RX_LINK_FAIL 32 4336 #define microtmp2_cl36RxEEEStates_l_RX_WTF 16 4337 #define microtmp2_cl36RxEEEStates_l_RX_WAKE 8 4338 #define microtmp2_cl36RxEEEStates_l_RX_QUIET 4 4339 #define microtmp2_cl36RxEEEStates_l_RX_SLEEP 2 4340 #define microtmp2_cl36RxEEEStates_l_RX_ACTIVE 1 4341 4342 /**************************************************************************** 4343 * Enums: microtmp2_cl36RxEEEStates_c 4344 */ 4345 #define microtmp2_cl36RxEEEStates_c_RX_LINK_FAIL 5 4346 #define microtmp2_cl36RxEEEStates_c_RX_WTF 4 4347 #define microtmp2_cl36RxEEEStates_c_RX_WAKE 3 4348 #define microtmp2_cl36RxEEEStates_c_RX_QUIET 2 4349 #define microtmp2_cl36RxEEEStates_c_RX_SLEEP 1 4350 #define microtmp2_cl36RxEEEStates_c_RX_ACTIVE 0 4351 4352 /**************************************************************************** 4353 * Enums: microtmp2_cl49RxEEEStates_l 4354 */ 4355 #define microtmp2_cl49RxEEEStates_l_RX_LINK_FAIL 32 4356 #define microtmp2_cl49RxEEEStates_l_RX_WTF 16 4357 #define microtmp2_cl49RxEEEStates_l_RX_WAKE 8 4358 #define microtmp2_cl49RxEEEStates_l_RX_QUIET 4 4359 #define microtmp2_cl49RxEEEStates_l_RX_SLEEP 2 4360 #define microtmp2_cl49RxEEEStates_l_RX_ACTIVE 1 4361 4362 /**************************************************************************** 4363 * Enums: microtmp2_cl49RxEEEStates_c 4364 */ 4365 #define microtmp2_cl49RxEEEStates_c_RX_LINK_FAIL 5 4366 #define microtmp2_cl49RxEEEStates_c_RX_WTF 4 4367 #define microtmp2_cl49RxEEEStates_c_RX_WAKE 3 4368 #define microtmp2_cl49RxEEEStates_c_RX_QUIET 2 4369 #define microtmp2_cl49RxEEEStates_c_RX_SLEEP 1 4370 #define microtmp2_cl49RxEEEStates_c_RX_ACTIVE 0 4371 4372 /**************************************************************************** 4373 * Enums: microtmp2_cl48TxEEEStates_l 4374 */ 4375 #define microtmp2_cl48TxEEEStates_l_TX_REFRESH 8 4376 #define microtmp2_cl48TxEEEStates_l_TX_QUIET 4 4377 #define microtmp2_cl48TxEEEStates_l_TX_SLEEP 2 4378 #define microtmp2_cl48TxEEEStates_l_TX_ACTIVE 1 4379 4380 /**************************************************************************** 4381 * Enums: microtmp2_cl48TxEEEStates_c 4382 */ 4383 #define microtmp2_cl48TxEEEStates_c_TX_REFRESH 3 4384 #define microtmp2_cl48TxEEEStates_c_TX_QUIET 2 4385 #define microtmp2_cl48TxEEEStates_c_TX_SLEEP 1 4386 #define microtmp2_cl48TxEEEStates_c_TX_ACTIVE 0 4387 4388 /**************************************************************************** 4389 * Enums: microtmp2_cl48RxEEEStates_l 4390 */ 4391 #define microtmp2_cl48RxEEEStates_l_RX_LINK_FAIL 32 4392 #define microtmp2_cl48RxEEEStates_l_RX_WAKE 16 4393 #define microtmp2_cl48RxEEEStates_l_RX_QUIET 8 4394 #define microtmp2_cl48RxEEEStates_l_RX_DEACT 4 4395 #define microtmp2_cl48RxEEEStates_l_RX_SLEEP 2 4396 #define microtmp2_cl48RxEEEStates_l_RX_ACTIVE 1 4397 4398 /**************************************************************************** 4399 * Enums: microtmp2_cl48RxEEEStates_c 4400 */ 4401 #define microtmp2_cl48RxEEEStates_c_RX_LINK_FAIL 5 4402 #define microtmp2_cl48RxEEEStates_c_RX_WAKE 4 4403 #define microtmp2_cl48RxEEEStates_c_RX_QUIET 3 4404 #define microtmp2_cl48RxEEEStates_c_RX_DEACT 2 4405 #define microtmp2_cl48RxEEEStates_c_RX_SLEEP 1 4406 #define microtmp2_cl48RxEEEStates_c_RX_ACTIVE 0 4407 4408 /**************************************************************************** 4409 * Enums: microtmp2_IQP_Options 4410 */ 4411 #define microtmp2_IQP_Options_i50uA 0 4412 #define microtmp2_IQP_Options_i100uA 1 4413 #define microtmp2_IQP_Options_i150uA 2 4414 #define microtmp2_IQP_Options_i200uA 3 4415 #define microtmp2_IQP_Options_i250uA 4 4416 #define microtmp2_IQP_Options_i300uA 5 4417 #define microtmp2_IQP_Options_i350uA 6 4418 #define microtmp2_IQP_Options_i400uA 7 4419 #define microtmp2_IQP_Options_i450uA 8 4420 #define microtmp2_IQP_Options_i500uA 9 4421 #define microtmp2_IQP_Options_i550uA 10 4422 #define microtmp2_IQP_Options_i600uA 11 4423 #define microtmp2_IQP_Options_i650uA 12 4424 #define microtmp2_IQP_Options_i700uA 13 4425 #define microtmp2_IQP_Options_i750uA 14 4426 #define microtmp2_IQP_Options_i800uA 15 4427 4428 /**************************************************************************** 4429 * Enums: microtmp2_IDriver_Options 4430 */ 4431 #define microtmp2_IDriver_Options_v680mV 0 4432 #define microtmp2_IDriver_Options_v730mV 1 4433 #define microtmp2_IDriver_Options_v780mV 2 4434 #define microtmp2_IDriver_Options_v830mV 3 4435 #define microtmp2_IDriver_Options_v880mV 4 4436 #define microtmp2_IDriver_Options_v930mV 5 4437 #define microtmp2_IDriver_Options_v980mV 6 4438 #define microtmp2_IDriver_Options_v1010mV 7 4439 #define microtmp2_IDriver_Options_v1040mV 8 4440 #define microtmp2_IDriver_Options_v1060mV 9 4441 #define microtmp2_IDriver_Options_v1070mV 10 4442 #define microtmp2_IDriver_Options_v1080mV 11 4443 #define microtmp2_IDriver_Options_v1085mV 12 4444 #define microtmp2_IDriver_Options_v1090mV 13 4445 #define microtmp2_IDriver_Options_v1095mV 14 4446 #define microtmp2_IDriver_Options_v1100mV 15 4447 4448 /**************************************************************************** 4449 * Enums: microtmp2_operationModes 4450 */ 4451 #define microtmp2_operationModes_XGXS 0 4452 #define microtmp2_operationModes_XGXG_nCC 1 4453 #define microtmp2_operationModes_Indlane_OS8 4 4454 #define microtmp2_operationModes_IndLane_OS5 5 4455 #define microtmp2_operationModes_PCI 7 4456 #define microtmp2_operationModes_XGXS_nLQ 8 4457 #define microtmp2_operationModes_XGXS_nLQnCC 9 4458 #define microtmp2_operationModes_PBypass 10 4459 #define microtmp2_operationModes_PBypass_nDSK 11 4460 #define microtmp2_operationModes_ComboCoreMode 12 4461 #define microtmp2_operationModes_Clocks_off 15 4462 4463 /**************************************************************************** 4464 * Enums: microtmp2_actualSpeeds 4465 */ 4466 #define microtmp2_actualSpeeds_dr_10M 0 4467 #define microtmp2_actualSpeeds_dr_100M 1 4468 #define microtmp2_actualSpeeds_dr_1G 2 4469 #define microtmp2_actualSpeeds_dr_2p5G 3 4470 #define microtmp2_actualSpeeds_dr_5G_X4 4 4471 #define microtmp2_actualSpeeds_dr_6G_X4 5 4472 #define microtmp2_actualSpeeds_dr_10G_HiG 6 4473 #define microtmp2_actualSpeeds_dr_10G_CX4 7 4474 #define microtmp2_actualSpeeds_dr_12G_HiG 8 4475 #define microtmp2_actualSpeeds_dr_12p5G_X4 9 4476 #define microtmp2_actualSpeeds_dr_13G_X4 10 4477 #define microtmp2_actualSpeeds_dr_15G_X4 11 4478 #define microtmp2_actualSpeeds_dr_16G_X4 12 4479 #define microtmp2_actualSpeeds_dr_1G_KX 13 4480 #define microtmp2_actualSpeeds_dr_10G_KX4 14 4481 #define microtmp2_actualSpeeds_dr_10G_KR 15 4482 #define microtmp2_actualSpeeds_dr_5G 16 4483 #define microtmp2_actualSpeeds_dr_6p4G 17 4484 #define microtmp2_actualSpeeds_dr_20G_X4 18 4485 #define microtmp2_actualSpeeds_dr_21G_X4 19 4486 #define microtmp2_actualSpeeds_dr_25G_X4 20 4487 #define microtmp2_actualSpeeds_dr_10G_HiG_DXGXS 21 4488 #define microtmp2_actualSpeeds_dr_10G_DXGXS 22 4489 #define microtmp2_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4490 #define microtmp2_actualSpeeds_dr_10p5G_DXGXS 24 4491 #define microtmp2_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4492 #define microtmp2_actualSpeeds_dr_12p773G_DXGXS 26 4493 #define microtmp2_actualSpeeds_dr_10G_XFI 27 4494 #define microtmp2_actualSpeeds_dr_40G 28 4495 #define microtmp2_actualSpeeds_dr_20G_HiG_DXGXS 29 4496 #define microtmp2_actualSpeeds_dr_20G_DXGXS 30 4497 #define microtmp2_actualSpeeds_dr_10G_SFI 31 4498 #define microtmp2_actualSpeeds_dr_31p5G 32 4499 #define microtmp2_actualSpeeds_dr_32p7G 33 4500 #define microtmp2_actualSpeeds_dr_20G_SCR 34 4501 #define microtmp2_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4502 #define microtmp2_actualSpeeds_dr_10G_DXGXS_SCR 36 4503 #define microtmp2_actualSpeeds_dr_12G_R2 37 4504 #define microtmp2_actualSpeeds_dr_10G_X2 38 4505 #define microtmp2_actualSpeeds_dr_40G_KR4 39 4506 #define microtmp2_actualSpeeds_dr_40G_CR4 40 4507 #define microtmp2_actualSpeeds_dr_100G_CR10 41 4508 #define microtmp2_actualSpeeds_dr_15p75G_DXGXS 44 4509 #define microtmp2_actualSpeeds_dr_20G_KR2 57 4510 #define microtmp2_actualSpeeds_dr_20G_CR2 58 4511 4512 /**************************************************************************** 4513 * Enums: microtmp2_actualSpeedsMisc1 4514 */ 4515 #define microtmp2_actualSpeedsMisc1_dr_2500BRCM_X1 16 4516 #define microtmp2_actualSpeedsMisc1_dr_5000BRCM_X4 17 4517 #define microtmp2_actualSpeedsMisc1_dr_6000BRCM_X4 18 4518 #define microtmp2_actualSpeedsMisc1_dr_10GHiGig_X4 19 4519 #define microtmp2_actualSpeedsMisc1_dr_10GBASE_CX4 20 4520 #define microtmp2_actualSpeedsMisc1_dr_12GHiGig_X4 21 4521 #define microtmp2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4522 #define microtmp2_actualSpeedsMisc1_dr_13GHiGig_X4 23 4523 #define microtmp2_actualSpeedsMisc1_dr_15GHiGig_X4 24 4524 #define microtmp2_actualSpeedsMisc1_dr_16GHiGig_X4 25 4525 #define microtmp2_actualSpeedsMisc1_dr_5000BRCM_X1 26 4526 #define microtmp2_actualSpeedsMisc1_dr_6363BRCM_X1 27 4527 #define microtmp2_actualSpeedsMisc1_dr_20GHiGig_X4 28 4528 #define microtmp2_actualSpeedsMisc1_dr_21GHiGig_X4 29 4529 #define microtmp2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4530 #define microtmp2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4531 4532 /**************************************************************************** 4533 * Enums: microtmp2_IndLaneModes 4534 */ 4535 #define microtmp2_IndLaneModes_SWSDR_div2 0 4536 #define microtmp2_IndLaneModes_SWSDR_div1 1 4537 #define microtmp2_IndLaneModes_DWSDR_div2 2 4538 #define microtmp2_IndLaneModes_DWSDR_div1 3 4539 4540 /**************************************************************************** 4541 * Enums: microtmp2_prbsSelect 4542 */ 4543 #define microtmp2_prbsSelect_prbs7 0 4544 #define microtmp2_prbsSelect_prbs15 1 4545 #define microtmp2_prbsSelect_prbs23 2 4546 #define microtmp2_prbsSelect_prbs31 3 4547 4548 /**************************************************************************** 4549 * Enums: microtmp2_vcoDivider 4550 */ 4551 #define microtmp2_vcoDivider_div32 0 4552 #define microtmp2_vcoDivider_div36 1 4553 #define microtmp2_vcoDivider_div40 2 4554 #define microtmp2_vcoDivider_div42 3 4555 #define microtmp2_vcoDivider_div48 4 4556 #define microtmp2_vcoDivider_div50 5 4557 #define microtmp2_vcoDivider_div52 6 4558 #define microtmp2_vcoDivider_div54 7 4559 #define microtmp2_vcoDivider_div60 8 4560 #define microtmp2_vcoDivider_div64 9 4561 #define microtmp2_vcoDivider_div66 10 4562 #define microtmp2_vcoDivider_div68 11 4563 #define microtmp2_vcoDivider_div70 12 4564 #define microtmp2_vcoDivider_div80 13 4565 #define microtmp2_vcoDivider_div92 14 4566 #define microtmp2_vcoDivider_div100 15 4567 4568 /**************************************************************************** 4569 * Enums: microtmp2_refClkSelect 4570 */ 4571 #define microtmp2_refClkSelect_clk_25MHz 0 4572 #define microtmp2_refClkSelect_clk_100MHz 1 4573 #define microtmp2_refClkSelect_clk_125MHz 2 4574 #define microtmp2_refClkSelect_clk_156p25MHz 3 4575 #define microtmp2_refClkSelect_clk_187p5MHz 4 4576 #define microtmp2_refClkSelect_clk_161p25Mhz 5 4577 #define microtmp2_refClkSelect_clk_50Mhz 6 4578 #define microtmp2_refClkSelect_clk_106p25Mhz 7 4579 4580 /**************************************************************************** 4581 * Enums: microtmp2_aerMMDdevTypeSelect 4582 */ 4583 #define microtmp2_aerMMDdevTypeSelect_combo_core 0 4584 #define microtmp2_aerMMDdevTypeSelect_PMA_PMD 1 4585 #define microtmp2_aerMMDdevTypeSelect_PCS 3 4586 #define microtmp2_aerMMDdevTypeSelect_PHY 4 4587 #define microtmp2_aerMMDdevTypeSelect_DTE 5 4588 #define microtmp2_aerMMDdevTypeSelect_CL73_AN 7 4589 4590 /**************************************************************************** 4591 * Enums: microtmp2_aerMMDportSelect 4592 */ 4593 #define microtmp2_aerMMDportSelect_ln0 0 4594 #define microtmp2_aerMMDportSelect_ln1 1 4595 #define microtmp2_aerMMDportSelect_ln2 2 4596 #define microtmp2_aerMMDportSelect_ln3 3 4597 #define microtmp2_aerMMDportSelect_BCST_ln0_1_2_3 511 4598 #define microtmp2_aerMMDportSelect_BCST_ln0_1 512 4599 #define microtmp2_aerMMDportSelect_BCST_ln2_3 513 4600 4601 /**************************************************************************** 4602 * Enums: microtmp2_firmwareModeSelect 4603 */ 4604 #define microtmp2_firmwareModeSelect_DEFAULT 0 4605 #define microtmp2_firmwareModeSelect_SFP_OPT_LR 1 4606 #define microtmp2_firmwareModeSelect_SFP_DAC 2 4607 #define microtmp2_firmwareModeSelect_XLAUI 3 4608 #define microtmp2_firmwareModeSelect_LONG_CH_6G 4 4609 4610 /**************************************************************************** 4611 * Enums: microtmp2_tempIdxSelect 4612 */ 4613 #define microtmp2_tempIdxSelect_LTE__22p9C 15 4614 #define microtmp2_tempIdxSelect_LTE__12p6C 14 4615 #define microtmp2_tempIdxSelect_LTE__3p0C 13 4616 #define microtmp2_tempIdxSelect_LTE_6p7C 12 4617 #define microtmp2_tempIdxSelect_LTE_16p4C 11 4618 #define microtmp2_tempIdxSelect_LTE_26p6C 10 4619 #define microtmp2_tempIdxSelect_LTE_36p3C 9 4620 #define microtmp2_tempIdxSelect_LTE_46p0C 8 4621 #define microtmp2_tempIdxSelect_LTE_56p2C 7 4622 #define microtmp2_tempIdxSelect_LTE_65p9C 6 4623 #define microtmp2_tempIdxSelect_LTE_75p6C 5 4624 #define microtmp2_tempIdxSelect_LTE_85p3C 4 4625 #define microtmp2_tempIdxSelect_LTE_95p5C 3 4626 #define microtmp2_tempIdxSelect_LTE_105p2C 2 4627 #define microtmp2_tempIdxSelect_LTE_114p9C 1 4628 #define microtmp2_tempIdxSelect_LTE_125p1C 0 4629 4630 /**************************************************************************** 4631 * Enums: tx_x1_status0_tla_pll_status 4632 */ 4633 #define tx_x1_status0_tla_pll_status_INIT 1 4634 #define tx_x1_status0_tla_pll_status_PLL_LOCKED 2 4635 #define tx_x1_status0_tla_pll_status_RESET_PLL 4 4636 #define tx_x1_status0_tla_pll_status_CHANGE_PLL_MODE 8 4637 #define tx_x1_status0_tla_pll_status_PLL_SWITCH 16 4638 4639 /**************************************************************************** 4640 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_l 4641 */ 4642 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_REFRESH 8 4643 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_QUIET 4 4644 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_SLEEP 2 4645 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_ACTIVE 1 4646 4647 /**************************************************************************** 4648 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_c 4649 */ 4650 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_REFRESH 3 4651 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_QUIET 2 4652 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_SLEEP 1 4653 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_ACTIVE 0 4654 4655 /**************************************************************************** 4656 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_l 4657 */ 4658 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_2 64 4659 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_1 32 4660 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_WAKE 16 4661 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_REFRESH 8 4662 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_QUIET 4 4663 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_SLEEP 2 4664 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_ACTIVE 1 4665 4666 /**************************************************************************** 4667 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_c 4668 */ 4669 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_2 6 4670 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_1 5 4671 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_WAKE 4 4672 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_REFRESH 3 4673 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_QUIET 2 4674 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_SLEEP 1 4675 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_ACTIVE 0 4676 4677 /**************************************************************************** 4678 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_l 4679 */ 4680 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_LINK_FAIL 32 4681 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WTF 16 4682 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WAKE 8 4683 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_QUIET 4 4684 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_SLEEP 2 4685 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_ACTIVE 1 4686 4687 /**************************************************************************** 4688 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_c 4689 */ 4690 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_LINK_FAIL 5 4691 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WTF 4 4692 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WAKE 3 4693 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_QUIET 2 4694 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_SLEEP 1 4695 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_ACTIVE 0 4696 4697 /**************************************************************************** 4698 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_l 4699 */ 4700 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_LINK_FAIL 32 4701 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WTF 16 4702 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WAKE 8 4703 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_QUIET 4 4704 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_SLEEP 2 4705 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_ACTIVE 1 4706 4707 /**************************************************************************** 4708 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_c 4709 */ 4710 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_LINK_FAIL 5 4711 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WTF 4 4712 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WAKE 3 4713 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_QUIET 2 4714 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_SLEEP 1 4715 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_ACTIVE 0 4716 4717 /**************************************************************************** 4718 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_l 4719 */ 4720 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_REFRESH 8 4721 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_QUIET 4 4722 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_SLEEP 2 4723 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_ACTIVE 1 4724 4725 /**************************************************************************** 4726 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_c 4727 */ 4728 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_REFRESH 3 4729 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_QUIET 2 4730 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_SLEEP 1 4731 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_ACTIVE 0 4732 4733 /**************************************************************************** 4734 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_l 4735 */ 4736 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_LINK_FAIL 32 4737 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_WAKE 16 4738 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_QUIET 8 4739 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_DEACT 4 4740 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_SLEEP 2 4741 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_ACTIVE 1 4742 4743 /**************************************************************************** 4744 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_c 4745 */ 4746 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_LINK_FAIL 5 4747 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_WAKE 4 4748 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_QUIET 3 4749 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_DEACT 2 4750 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_SLEEP 1 4751 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_ACTIVE 0 4752 4753 /**************************************************************************** 4754 * Enums: tx_x4_credit_gen0_IQP_Options 4755 */ 4756 #define tx_x4_credit_gen0_IQP_Options_i50uA 0 4757 #define tx_x4_credit_gen0_IQP_Options_i100uA 1 4758 #define tx_x4_credit_gen0_IQP_Options_i150uA 2 4759 #define tx_x4_credit_gen0_IQP_Options_i200uA 3 4760 #define tx_x4_credit_gen0_IQP_Options_i250uA 4 4761 #define tx_x4_credit_gen0_IQP_Options_i300uA 5 4762 #define tx_x4_credit_gen0_IQP_Options_i350uA 6 4763 #define tx_x4_credit_gen0_IQP_Options_i400uA 7 4764 #define tx_x4_credit_gen0_IQP_Options_i450uA 8 4765 #define tx_x4_credit_gen0_IQP_Options_i500uA 9 4766 #define tx_x4_credit_gen0_IQP_Options_i550uA 10 4767 #define tx_x4_credit_gen0_IQP_Options_i600uA 11 4768 #define tx_x4_credit_gen0_IQP_Options_i650uA 12 4769 #define tx_x4_credit_gen0_IQP_Options_i700uA 13 4770 #define tx_x4_credit_gen0_IQP_Options_i750uA 14 4771 #define tx_x4_credit_gen0_IQP_Options_i800uA 15 4772 4773 /**************************************************************************** 4774 * Enums: tx_x4_credit_gen0_IDriver_Options 4775 */ 4776 #define tx_x4_credit_gen0_IDriver_Options_v680mV 0 4777 #define tx_x4_credit_gen0_IDriver_Options_v730mV 1 4778 #define tx_x4_credit_gen0_IDriver_Options_v780mV 2 4779 #define tx_x4_credit_gen0_IDriver_Options_v830mV 3 4780 #define tx_x4_credit_gen0_IDriver_Options_v880mV 4 4781 #define tx_x4_credit_gen0_IDriver_Options_v930mV 5 4782 #define tx_x4_credit_gen0_IDriver_Options_v980mV 6 4783 #define tx_x4_credit_gen0_IDriver_Options_v1010mV 7 4784 #define tx_x4_credit_gen0_IDriver_Options_v1040mV 8 4785 #define tx_x4_credit_gen0_IDriver_Options_v1060mV 9 4786 #define tx_x4_credit_gen0_IDriver_Options_v1070mV 10 4787 #define tx_x4_credit_gen0_IDriver_Options_v1080mV 11 4788 #define tx_x4_credit_gen0_IDriver_Options_v1085mV 12 4789 #define tx_x4_credit_gen0_IDriver_Options_v1090mV 13 4790 #define tx_x4_credit_gen0_IDriver_Options_v1095mV 14 4791 #define tx_x4_credit_gen0_IDriver_Options_v1100mV 15 4792 4793 /**************************************************************************** 4794 * Enums: tx_x4_credit_gen0_operationModes 4795 */ 4796 #define tx_x4_credit_gen0_operationModes_XGXS 0 4797 #define tx_x4_credit_gen0_operationModes_XGXG_nCC 1 4798 #define tx_x4_credit_gen0_operationModes_Indlane_OS8 4 4799 #define tx_x4_credit_gen0_operationModes_IndLane_OS5 5 4800 #define tx_x4_credit_gen0_operationModes_PCI 7 4801 #define tx_x4_credit_gen0_operationModes_XGXS_nLQ 8 4802 #define tx_x4_credit_gen0_operationModes_XGXS_nLQnCC 9 4803 #define tx_x4_credit_gen0_operationModes_PBypass 10 4804 #define tx_x4_credit_gen0_operationModes_PBypass_nDSK 11 4805 #define tx_x4_credit_gen0_operationModes_ComboCoreMode 12 4806 #define tx_x4_credit_gen0_operationModes_Clocks_off 15 4807 4808 /**************************************************************************** 4809 * Enums: tx_x4_credit_gen0_actualSpeeds 4810 */ 4811 #define tx_x4_credit_gen0_actualSpeeds_dr_10M 0 4812 #define tx_x4_credit_gen0_actualSpeeds_dr_100M 1 4813 #define tx_x4_credit_gen0_actualSpeeds_dr_1G 2 4814 #define tx_x4_credit_gen0_actualSpeeds_dr_2p5G 3 4815 #define tx_x4_credit_gen0_actualSpeeds_dr_5G_X4 4 4816 #define tx_x4_credit_gen0_actualSpeeds_dr_6G_X4 5 4817 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG 6 4818 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_CX4 7 4819 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_HiG 8 4820 #define tx_x4_credit_gen0_actualSpeeds_dr_12p5G_X4 9 4821 #define tx_x4_credit_gen0_actualSpeeds_dr_13G_X4 10 4822 #define tx_x4_credit_gen0_actualSpeeds_dr_15G_X4 11 4823 #define tx_x4_credit_gen0_actualSpeeds_dr_16G_X4 12 4824 #define tx_x4_credit_gen0_actualSpeeds_dr_1G_KX 13 4825 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KX4 14 4826 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KR 15 4827 #define tx_x4_credit_gen0_actualSpeeds_dr_5G 16 4828 #define tx_x4_credit_gen0_actualSpeeds_dr_6p4G 17 4829 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_X4 18 4830 #define tx_x4_credit_gen0_actualSpeeds_dr_21G_X4 19 4831 #define tx_x4_credit_gen0_actualSpeeds_dr_25G_X4 20 4832 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS 21 4833 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS 22 4834 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4835 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_DXGXS 24 4836 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4837 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_DXGXS 26 4838 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_XFI 27 4839 #define tx_x4_credit_gen0_actualSpeeds_dr_40G 28 4840 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_HiG_DXGXS 29 4841 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_DXGXS 30 4842 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_SFI 31 4843 #define tx_x4_credit_gen0_actualSpeeds_dr_31p5G 32 4844 #define tx_x4_credit_gen0_actualSpeeds_dr_32p7G 33 4845 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_SCR 34 4846 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4847 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS_SCR 36 4848 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_R2 37 4849 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_X2 38 4850 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_KR4 39 4851 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_CR4 40 4852 #define tx_x4_credit_gen0_actualSpeeds_dr_100G_CR10 41 4853 #define tx_x4_credit_gen0_actualSpeeds_dr_15p75G_DXGXS 44 4854 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_KR2 57 4855 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_CR2 58 4856 4857 /**************************************************************************** 4858 * Enums: tx_x4_credit_gen0_actualSpeedsMisc1 4859 */ 4860 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_2500BRCM_X1 16 4861 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X4 17 4862 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6000BRCM_X4 18 4863 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GHiGig_X4 19 4864 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GBASE_CX4 20 4865 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12GHiGig_X4 21 4866 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4867 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_13GHiGig_X4 23 4868 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_15GHiGig_X4 24 4869 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_16GHiGig_X4 25 4870 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X1 26 4871 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6363BRCM_X1 27 4872 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_20GHiGig_X4 28 4873 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_21GHiGig_X4 29 4874 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4875 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4876 4877 /**************************************************************************** 4878 * Enums: tx_x4_credit_gen0_IndLaneModes 4879 */ 4880 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div2 0 4881 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div1 1 4882 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div2 2 4883 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div1 3 4884 4885 /**************************************************************************** 4886 * Enums: tx_x4_credit_gen0_prbsSelect 4887 */ 4888 #define tx_x4_credit_gen0_prbsSelect_prbs7 0 4889 #define tx_x4_credit_gen0_prbsSelect_prbs15 1 4890 #define tx_x4_credit_gen0_prbsSelect_prbs23 2 4891 #define tx_x4_credit_gen0_prbsSelect_prbs31 3 4892 4893 /**************************************************************************** 4894 * Enums: tx_x4_credit_gen0_vcoDivider 4895 */ 4896 #define tx_x4_credit_gen0_vcoDivider_div32 0 4897 #define tx_x4_credit_gen0_vcoDivider_div36 1 4898 #define tx_x4_credit_gen0_vcoDivider_div40 2 4899 #define tx_x4_credit_gen0_vcoDivider_div42 3 4900 #define tx_x4_credit_gen0_vcoDivider_div48 4 4901 #define tx_x4_credit_gen0_vcoDivider_div50 5 4902 #define tx_x4_credit_gen0_vcoDivider_div52 6 4903 #define tx_x4_credit_gen0_vcoDivider_div54 7 4904 #define tx_x4_credit_gen0_vcoDivider_div60 8 4905 #define tx_x4_credit_gen0_vcoDivider_div64 9 4906 #define tx_x4_credit_gen0_vcoDivider_div66 10 4907 #define tx_x4_credit_gen0_vcoDivider_div68 11 4908 #define tx_x4_credit_gen0_vcoDivider_div70 12 4909 #define tx_x4_credit_gen0_vcoDivider_div80 13 4910 #define tx_x4_credit_gen0_vcoDivider_div92 14 4911 #define tx_x4_credit_gen0_vcoDivider_div100 15 4912 4913 /**************************************************************************** 4914 * Enums: tx_x4_credit_gen0_refClkSelect 4915 */ 4916 #define tx_x4_credit_gen0_refClkSelect_clk_25MHz 0 4917 #define tx_x4_credit_gen0_refClkSelect_clk_100MHz 1 4918 #define tx_x4_credit_gen0_refClkSelect_clk_125MHz 2 4919 #define tx_x4_credit_gen0_refClkSelect_clk_156p25MHz 3 4920 #define tx_x4_credit_gen0_refClkSelect_clk_187p5MHz 4 4921 #define tx_x4_credit_gen0_refClkSelect_clk_161p25Mhz 5 4922 #define tx_x4_credit_gen0_refClkSelect_clk_50Mhz 6 4923 #define tx_x4_credit_gen0_refClkSelect_clk_106p25Mhz 7 4924 4925 /**************************************************************************** 4926 * Enums: tx_x4_credit_gen0_aerMMDdevTypeSelect 4927 */ 4928 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_combo_core 0 4929 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PMA_PMD 1 4930 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PCS 3 4931 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PHY 4 4932 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_DTE 5 4933 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_CL73_AN 7 4934 4935 /**************************************************************************** 4936 * Enums: tx_x4_credit_gen0_aerMMDportSelect 4937 */ 4938 #define tx_x4_credit_gen0_aerMMDportSelect_ln0 0 4939 #define tx_x4_credit_gen0_aerMMDportSelect_ln1 1 4940 #define tx_x4_credit_gen0_aerMMDportSelect_ln2 2 4941 #define tx_x4_credit_gen0_aerMMDportSelect_ln3 3 4942 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1_2_3 511 4943 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1 512 4944 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln2_3 513 4945 4946 /**************************************************************************** 4947 * Enums: tx_x4_credit_gen0_firmwareModeSelect 4948 */ 4949 #define tx_x4_credit_gen0_firmwareModeSelect_DEFAULT 0 4950 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_OPT_LR 1 4951 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_DAC 2 4952 #define tx_x4_credit_gen0_firmwareModeSelect_XLAUI 3 4953 #define tx_x4_credit_gen0_firmwareModeSelect_LONG_CH_6G 4 4954 4955 /**************************************************************************** 4956 * Enums: tx_x4_credit_gen0_tempIdxSelect 4957 */ 4958 #define tx_x4_credit_gen0_tempIdxSelect_LTE__22p9C 15 4959 #define tx_x4_credit_gen0_tempIdxSelect_LTE__12p6C 14 4960 #define tx_x4_credit_gen0_tempIdxSelect_LTE__3p0C 13 4961 #define tx_x4_credit_gen0_tempIdxSelect_LTE_6p7C 12 4962 #define tx_x4_credit_gen0_tempIdxSelect_LTE_16p4C 11 4963 #define tx_x4_credit_gen0_tempIdxSelect_LTE_26p6C 10 4964 #define tx_x4_credit_gen0_tempIdxSelect_LTE_36p3C 9 4965 #define tx_x4_credit_gen0_tempIdxSelect_LTE_46p0C 8 4966 #define tx_x4_credit_gen0_tempIdxSelect_LTE_56p2C 7 4967 #define tx_x4_credit_gen0_tempIdxSelect_LTE_65p9C 6 4968 #define tx_x4_credit_gen0_tempIdxSelect_LTE_75p6C 5 4969 #define tx_x4_credit_gen0_tempIdxSelect_LTE_85p3C 4 4970 #define tx_x4_credit_gen0_tempIdxSelect_LTE_95p5C 3 4971 #define tx_x4_credit_gen0_tempIdxSelect_LTE_105p2C 2 4972 #define tx_x4_credit_gen0_tempIdxSelect_LTE_114p9C 1 4973 #define tx_x4_credit_gen0_tempIdxSelect_LTE_125p1C 0 4974 4975 /**************************************************************************** 4976 * Enums: xgxsblk4_cl36TxEEEStates_l 4977 */ 4978 #define xgxsblk4_cl36TxEEEStates_l_TX_REFRESH 8 4979 #define xgxsblk4_cl36TxEEEStates_l_TX_QUIET 4 4980 #define xgxsblk4_cl36TxEEEStates_l_TX_SLEEP 2 4981 #define xgxsblk4_cl36TxEEEStates_l_TX_ACTIVE 1 4982 4983 /**************************************************************************** 4984 * Enums: xgxsblk4_cl36TxEEEStates_c 4985 */ 4986 #define xgxsblk4_cl36TxEEEStates_c_TX_REFRESH 3 4987 #define xgxsblk4_cl36TxEEEStates_c_TX_QUIET 2 4988 #define xgxsblk4_cl36TxEEEStates_c_TX_SLEEP 1 4989 #define xgxsblk4_cl36TxEEEStates_c_TX_ACTIVE 0 4990 4991 /**************************************************************************** 4992 * Enums: xgxsblk4_cl49TxEEEStates_l 4993 */ 4994 #define xgxsblk4_cl49TxEEEStates_l_SCR_RESET_2 64 4995 #define xgxsblk4_cl49TxEEEStates_l_SCR_RESET_1 32 4996 #define xgxsblk4_cl49TxEEEStates_l_TX_WAKE 16 4997 #define xgxsblk4_cl49TxEEEStates_l_TX_REFRESH 8 4998 #define xgxsblk4_cl49TxEEEStates_l_TX_QUIET 4 4999 #define xgxsblk4_cl49TxEEEStates_l_TX_SLEEP 2 5000 #define xgxsblk4_cl49TxEEEStates_l_TX_ACTIVE 1 5001 5002 /**************************************************************************** 5003 * Enums: xgxsblk4_cl49TxEEEStates_c 5004 */ 5005 #define xgxsblk4_cl49TxEEEStates_c_SCR_RESET_2 6 5006 #define xgxsblk4_cl49TxEEEStates_c_SCR_RESET_1 5 5007 #define xgxsblk4_cl49TxEEEStates_c_TX_WAKE 4 5008 #define xgxsblk4_cl49TxEEEStates_c_TX_REFRESH 3 5009 #define xgxsblk4_cl49TxEEEStates_c_TX_QUIET 2 5010 #define xgxsblk4_cl49TxEEEStates_c_TX_SLEEP 1 5011 #define xgxsblk4_cl49TxEEEStates_c_TX_ACTIVE 0 5012 5013 /**************************************************************************** 5014 * Enums: xgxsblk4_cl36RxEEEStates_l 5015 */ 5016 #define xgxsblk4_cl36RxEEEStates_l_RX_LINK_FAIL 32 5017 #define xgxsblk4_cl36RxEEEStates_l_RX_WTF 16 5018 #define xgxsblk4_cl36RxEEEStates_l_RX_WAKE 8 5019 #define xgxsblk4_cl36RxEEEStates_l_RX_QUIET 4 5020 #define xgxsblk4_cl36RxEEEStates_l_RX_SLEEP 2 5021 #define xgxsblk4_cl36RxEEEStates_l_RX_ACTIVE 1 5022 5023 /**************************************************************************** 5024 * Enums: xgxsblk4_cl36RxEEEStates_c 5025 */ 5026 #define xgxsblk4_cl36RxEEEStates_c_RX_LINK_FAIL 5 5027 #define xgxsblk4_cl36RxEEEStates_c_RX_WTF 4 5028 #define xgxsblk4_cl36RxEEEStates_c_RX_WAKE 3 5029 #define xgxsblk4_cl36RxEEEStates_c_RX_QUIET 2 5030 #define xgxsblk4_cl36RxEEEStates_c_RX_SLEEP 1 5031 #define xgxsblk4_cl36RxEEEStates_c_RX_ACTIVE 0 5032 5033 /**************************************************************************** 5034 * Enums: xgxsblk4_cl49RxEEEStates_l 5035 */ 5036 #define xgxsblk4_cl49RxEEEStates_l_RX_LINK_FAIL 32 5037 #define xgxsblk4_cl49RxEEEStates_l_RX_WTF 16 5038 #define xgxsblk4_cl49RxEEEStates_l_RX_WAKE 8 5039 #define xgxsblk4_cl49RxEEEStates_l_RX_QUIET 4 5040 #define xgxsblk4_cl49RxEEEStates_l_RX_SLEEP 2 5041 #define xgxsblk4_cl49RxEEEStates_l_RX_ACTIVE 1 5042 5043 /**************************************************************************** 5044 * Enums: xgxsblk4_cl49RxEEEStates_c 5045 */ 5046 #define xgxsblk4_cl49RxEEEStates_c_RX_LINK_FAIL 5 5047 #define xgxsblk4_cl49RxEEEStates_c_RX_WTF 4 5048 #define xgxsblk4_cl49RxEEEStates_c_RX_WAKE 3 5049 #define xgxsblk4_cl49RxEEEStates_c_RX_QUIET 2 5050 #define xgxsblk4_cl49RxEEEStates_c_RX_SLEEP 1 5051 #define xgxsblk4_cl49RxEEEStates_c_RX_ACTIVE 0 5052 5053 /**************************************************************************** 5054 * Enums: xgxsblk4_cl48TxEEEStates_l 5055 */ 5056 #define xgxsblk4_cl48TxEEEStates_l_TX_REFRESH 8 5057 #define xgxsblk4_cl48TxEEEStates_l_TX_QUIET 4 5058 #define xgxsblk4_cl48TxEEEStates_l_TX_SLEEP 2 5059 #define xgxsblk4_cl48TxEEEStates_l_TX_ACTIVE 1 5060 5061 /**************************************************************************** 5062 * Enums: xgxsblk4_cl48TxEEEStates_c 5063 */ 5064 #define xgxsblk4_cl48TxEEEStates_c_TX_REFRESH 3 5065 #define xgxsblk4_cl48TxEEEStates_c_TX_QUIET 2 5066 #define xgxsblk4_cl48TxEEEStates_c_TX_SLEEP 1 5067 #define xgxsblk4_cl48TxEEEStates_c_TX_ACTIVE 0 5068 5069 /**************************************************************************** 5070 * Enums: xgxsblk4_cl48RxEEEStates_l 5071 */ 5072 #define xgxsblk4_cl48RxEEEStates_l_RX_LINK_FAIL 32 5073 #define xgxsblk4_cl48RxEEEStates_l_RX_WAKE 16 5074 #define xgxsblk4_cl48RxEEEStates_l_RX_QUIET 8 5075 #define xgxsblk4_cl48RxEEEStates_l_RX_DEACT 4 5076 #define xgxsblk4_cl48RxEEEStates_l_RX_SLEEP 2 5077 #define xgxsblk4_cl48RxEEEStates_l_RX_ACTIVE 1 5078 5079 /**************************************************************************** 5080 * Enums: xgxsblk4_cl48RxEEEStates_c 5081 */ 5082 #define xgxsblk4_cl48RxEEEStates_c_RX_LINK_FAIL 5 5083 #define xgxsblk4_cl48RxEEEStates_c_RX_WAKE 4 5084 #define xgxsblk4_cl48RxEEEStates_c_RX_QUIET 3 5085 #define xgxsblk4_cl48RxEEEStates_c_RX_DEACT 2 5086 #define xgxsblk4_cl48RxEEEStates_c_RX_SLEEP 1 5087 #define xgxsblk4_cl48RxEEEStates_c_RX_ACTIVE 0 5088 5089 /**************************************************************************** 5090 * Enums: xgxsblk4_IQP_Options 5091 */ 5092 #define xgxsblk4_IQP_Options_i50uA 0 5093 #define xgxsblk4_IQP_Options_i100uA 1 5094 #define xgxsblk4_IQP_Options_i150uA 2 5095 #define xgxsblk4_IQP_Options_i200uA 3 5096 #define xgxsblk4_IQP_Options_i250uA 4 5097 #define xgxsblk4_IQP_Options_i300uA 5 5098 #define xgxsblk4_IQP_Options_i350uA 6 5099 #define xgxsblk4_IQP_Options_i400uA 7 5100 #define xgxsblk4_IQP_Options_i450uA 8 5101 #define xgxsblk4_IQP_Options_i500uA 9 5102 #define xgxsblk4_IQP_Options_i550uA 10 5103 #define xgxsblk4_IQP_Options_i600uA 11 5104 #define xgxsblk4_IQP_Options_i650uA 12 5105 #define xgxsblk4_IQP_Options_i700uA 13 5106 #define xgxsblk4_IQP_Options_i750uA 14 5107 #define xgxsblk4_IQP_Options_i800uA 15 5108 5109 /**************************************************************************** 5110 * Enums: xgxsblk4_IDriver_Options 5111 */ 5112 #define xgxsblk4_IDriver_Options_v680mV 0 5113 #define xgxsblk4_IDriver_Options_v730mV 1 5114 #define xgxsblk4_IDriver_Options_v780mV 2 5115 #define xgxsblk4_IDriver_Options_v830mV 3 5116 #define xgxsblk4_IDriver_Options_v880mV 4 5117 #define xgxsblk4_IDriver_Options_v930mV 5 5118 #define xgxsblk4_IDriver_Options_v980mV 6 5119 #define xgxsblk4_IDriver_Options_v1010mV 7 5120 #define xgxsblk4_IDriver_Options_v1040mV 8 5121 #define xgxsblk4_IDriver_Options_v1060mV 9 5122 #define xgxsblk4_IDriver_Options_v1070mV 10 5123 #define xgxsblk4_IDriver_Options_v1080mV 11 5124 #define xgxsblk4_IDriver_Options_v1085mV 12 5125 #define xgxsblk4_IDriver_Options_v1090mV 13 5126 #define xgxsblk4_IDriver_Options_v1095mV 14 5127 #define xgxsblk4_IDriver_Options_v1100mV 15 5128 5129 /**************************************************************************** 5130 * Enums: xgxsblk4_operationModes 5131 */ 5132 #define xgxsblk4_operationModes_XGXS 0 5133 #define xgxsblk4_operationModes_XGXG_nCC 1 5134 #define xgxsblk4_operationModes_Indlane_OS8 4 5135 #define xgxsblk4_operationModes_IndLane_OS5 5 5136 #define xgxsblk4_operationModes_PCI 7 5137 #define xgxsblk4_operationModes_XGXS_nLQ 8 5138 #define xgxsblk4_operationModes_XGXS_nLQnCC 9 5139 #define xgxsblk4_operationModes_PBypass 10 5140 #define xgxsblk4_operationModes_PBypass_nDSK 11 5141 #define xgxsblk4_operationModes_ComboCoreMode 12 5142 #define xgxsblk4_operationModes_Clocks_off 15 5143 5144 /**************************************************************************** 5145 * Enums: xgxsblk4_actualSpeeds 5146 */ 5147 #define xgxsblk4_actualSpeeds_dr_10M 0 5148 #define xgxsblk4_actualSpeeds_dr_100M 1 5149 #define xgxsblk4_actualSpeeds_dr_1G 2 5150 #define xgxsblk4_actualSpeeds_dr_2p5G 3 5151 #define xgxsblk4_actualSpeeds_dr_5G_X4 4 5152 #define xgxsblk4_actualSpeeds_dr_6G_X4 5 5153 #define xgxsblk4_actualSpeeds_dr_10G_HiG 6 5154 #define xgxsblk4_actualSpeeds_dr_10G_CX4 7 5155 #define xgxsblk4_actualSpeeds_dr_12G_HiG 8 5156 #define xgxsblk4_actualSpeeds_dr_12p5G_X4 9 5157 #define xgxsblk4_actualSpeeds_dr_13G_X4 10 5158 #define xgxsblk4_actualSpeeds_dr_15G_X4 11 5159 #define xgxsblk4_actualSpeeds_dr_16G_X4 12 5160 #define xgxsblk4_actualSpeeds_dr_1G_KX 13 5161 #define xgxsblk4_actualSpeeds_dr_10G_KX4 14 5162 #define xgxsblk4_actualSpeeds_dr_10G_KR 15 5163 #define xgxsblk4_actualSpeeds_dr_5G 16 5164 #define xgxsblk4_actualSpeeds_dr_6p4G 17 5165 #define xgxsblk4_actualSpeeds_dr_20G_X4 18 5166 #define xgxsblk4_actualSpeeds_dr_21G_X4 19 5167 #define xgxsblk4_actualSpeeds_dr_25G_X4 20 5168 #define xgxsblk4_actualSpeeds_dr_10G_HiG_DXGXS 21 5169 #define xgxsblk4_actualSpeeds_dr_10G_DXGXS 22 5170 #define xgxsblk4_actualSpeeds_dr_10p5G_HiG_DXGXS 23 5171 #define xgxsblk4_actualSpeeds_dr_10p5G_DXGXS 24 5172 #define xgxsblk4_actualSpeeds_dr_12p773G_HiG_DXGXS 25 5173 #define xgxsblk4_actualSpeeds_dr_12p773G_DXGXS 26 5174 #define xgxsblk4_actualSpeeds_dr_10G_XFI 27 5175 #define xgxsblk4_actualSpeeds_dr_40G 28 5176 #define xgxsblk4_actualSpeeds_dr_20G_HiG_DXGXS 29 5177 #define xgxsblk4_actualSpeeds_dr_20G_DXGXS 30 5178 #define xgxsblk4_actualSpeeds_dr_10G_SFI 31 5179 #define xgxsblk4_actualSpeeds_dr_31p5G 32 5180 #define xgxsblk4_actualSpeeds_dr_32p7G 33 5181 #define xgxsblk4_actualSpeeds_dr_20G_SCR 34 5182 #define xgxsblk4_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 5183 #define xgxsblk4_actualSpeeds_dr_10G_DXGXS_SCR 36 5184 #define xgxsblk4_actualSpeeds_dr_12G_R2 37 5185 #define xgxsblk4_actualSpeeds_dr_10G_X2 38 5186 #define xgxsblk4_actualSpeeds_dr_40G_KR4 39 5187 #define xgxsblk4_actualSpeeds_dr_40G_CR4 40 5188 #define xgxsblk4_actualSpeeds_dr_100G_CR10 41 5189 #define xgxsblk4_actualSpeeds_dr_15p75G_DXGXS 44 5190 #define xgxsblk4_actualSpeeds_dr_20G_KR2 57 5191 #define xgxsblk4_actualSpeeds_dr_20G_CR2 58 5192 5193 /**************************************************************************** 5194 * Enums: xgxsblk4_actualSpeedsMisc1 5195 */ 5196 #define xgxsblk4_actualSpeedsMisc1_dr_2500BRCM_X1 16 5197 #define xgxsblk4_actualSpeedsMisc1_dr_5000BRCM_X4 17 5198 #define xgxsblk4_actualSpeedsMisc1_dr_6000BRCM_X4 18 5199 #define xgxsblk4_actualSpeedsMisc1_dr_10GHiGig_X4 19 5200 #define xgxsblk4_actualSpeedsMisc1_dr_10GBASE_CX4 20 5201 #define xgxsblk4_actualSpeedsMisc1_dr_12GHiGig_X4 21 5202 #define xgxsblk4_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 5203 #define xgxsblk4_actualSpeedsMisc1_dr_13GHiGig_X4 23 5204 #define xgxsblk4_actualSpeedsMisc1_dr_15GHiGig_X4 24 5205 #define xgxsblk4_actualSpeedsMisc1_dr_16GHiGig_X4 25 5206 #define xgxsblk4_actualSpeedsMisc1_dr_5000BRCM_X1 26 5207 #define xgxsblk4_actualSpeedsMisc1_dr_6363BRCM_X1 27 5208 #define xgxsblk4_actualSpeedsMisc1_dr_20GHiGig_X4 28 5209 #define xgxsblk4_actualSpeedsMisc1_dr_21GHiGig_X4 29 5210 #define xgxsblk4_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 5211 #define xgxsblk4_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 5212 5213 /**************************************************************************** 5214 * Enums: xgxsblk4_IndLaneModes 5215 */ 5216 #define xgxsblk4_IndLaneModes_SWSDR_div2 0 5217 #define xgxsblk4_IndLaneModes_SWSDR_div1 1 5218 #define xgxsblk4_IndLaneModes_DWSDR_div2 2 5219 #define xgxsblk4_IndLaneModes_DWSDR_div1 3 5220 5221 /**************************************************************************** 5222 * Enums: xgxsblk4_prbsSelect 5223 */ 5224 #define xgxsblk4_prbsSelect_prbs7 0 5225 #define xgxsblk4_prbsSelect_prbs15 1 5226 #define xgxsblk4_prbsSelect_prbs23 2 5227 #define xgxsblk4_prbsSelect_prbs31 3 5228 5229 /**************************************************************************** 5230 * Enums: xgxsblk4_vcoDivider 5231 */ 5232 #define xgxsblk4_vcoDivider_div32 0 5233 #define xgxsblk4_vcoDivider_div36 1 5234 #define xgxsblk4_vcoDivider_div40 2 5235 #define xgxsblk4_vcoDivider_div42 3 5236 #define xgxsblk4_vcoDivider_div48 4 5237 #define xgxsblk4_vcoDivider_div50 5 5238 #define xgxsblk4_vcoDivider_div52 6 5239 #define xgxsblk4_vcoDivider_div54 7 5240 #define xgxsblk4_vcoDivider_div60 8 5241 #define xgxsblk4_vcoDivider_div64 9 5242 #define xgxsblk4_vcoDivider_div66 10 5243 #define xgxsblk4_vcoDivider_div68 11 5244 #define xgxsblk4_vcoDivider_div70 12 5245 #define xgxsblk4_vcoDivider_div80 13 5246 #define xgxsblk4_vcoDivider_div92 14 5247 #define xgxsblk4_vcoDivider_div100 15 5248 5249 /**************************************************************************** 5250 * Enums: xgxsblk4_refClkSelect 5251 */ 5252 #define xgxsblk4_refClkSelect_clk_25MHz 0 5253 #define xgxsblk4_refClkSelect_clk_100MHz 1 5254 #define xgxsblk4_refClkSelect_clk_125MHz 2 5255 #define xgxsblk4_refClkSelect_clk_156p25MHz 3 5256 #define xgxsblk4_refClkSelect_clk_187p5MHz 4 5257 #define xgxsblk4_refClkSelect_clk_161p25Mhz 5 5258 #define xgxsblk4_refClkSelect_clk_50Mhz 6 5259 #define xgxsblk4_refClkSelect_clk_106p25Mhz 7 5260 5261 /**************************************************************************** 5262 * Enums: xgxsblk4_aerMMDdevTypeSelect 5263 */ 5264 #define xgxsblk4_aerMMDdevTypeSelect_combo_core 0 5265 #define xgxsblk4_aerMMDdevTypeSelect_PMA_PMD 1 5266 #define xgxsblk4_aerMMDdevTypeSelect_PCS 3 5267 #define xgxsblk4_aerMMDdevTypeSelect_PHY 4 5268 #define xgxsblk4_aerMMDdevTypeSelect_DTE 5 5269 #define xgxsblk4_aerMMDdevTypeSelect_CL73_AN 7 5270 5271 /**************************************************************************** 5272 * Enums: xgxsblk4_aerMMDportSelect 5273 */ 5274 #define xgxsblk4_aerMMDportSelect_ln0 0 5275 #define xgxsblk4_aerMMDportSelect_ln1 1 5276 #define xgxsblk4_aerMMDportSelect_ln2 2 5277 #define xgxsblk4_aerMMDportSelect_ln3 3 5278 #define xgxsblk4_aerMMDportSelect_BCST_ln0_1_2_3 511 5279 #define xgxsblk4_aerMMDportSelect_BCST_ln0_1 512 5280 #define xgxsblk4_aerMMDportSelect_BCST_ln2_3 513 5281 5282 /**************************************************************************** 5283 * Enums: xgxsblk4_firmwareModeSelect 5284 */ 5285 #define xgxsblk4_firmwareModeSelect_DEFAULT 0 5286 #define xgxsblk4_firmwareModeSelect_SFP_OPT_LR 1 5287 #define xgxsblk4_firmwareModeSelect_SFP_DAC 2 5288 #define xgxsblk4_firmwareModeSelect_XLAUI 3 5289 #define xgxsblk4_firmwareModeSelect_LONG_CH_6G 4 5290 5291 /**************************************************************************** 5292 * Enums: xgxsblk4_tempIdxSelect 5293 */ 5294 #define xgxsblk4_tempIdxSelect_LTE__22p9C 15 5295 #define xgxsblk4_tempIdxSelect_LTE__12p6C 14 5296 #define xgxsblk4_tempIdxSelect_LTE__3p0C 13 5297 #define xgxsblk4_tempIdxSelect_LTE_6p7C 12 5298 #define xgxsblk4_tempIdxSelect_LTE_16p4C 11 5299 #define xgxsblk4_tempIdxSelect_LTE_26p6C 10 5300 #define xgxsblk4_tempIdxSelect_LTE_36p3C 9 5301 #define xgxsblk4_tempIdxSelect_LTE_46p0C 8 5302 #define xgxsblk4_tempIdxSelect_LTE_56p2C 7 5303 #define xgxsblk4_tempIdxSelect_LTE_65p9C 6 5304 #define xgxsblk4_tempIdxSelect_LTE_75p6C 5 5305 #define xgxsblk4_tempIdxSelect_LTE_85p3C 4 5306 #define xgxsblk4_tempIdxSelect_LTE_95p5C 3 5307 #define xgxsblk4_tempIdxSelect_LTE_105p2C 2 5308 #define xgxsblk4_tempIdxSelect_LTE_114p9C 1 5309 #define xgxsblk4_tempIdxSelect_LTE_125p1C 0 5310 5311 /**************************************************************************** 5312 * TSC_IEEE_CL22_CL22_B0 5313 */ 5314 /* IEEE phyID2 Register: 00000000*/ 5315 #define READ_WC40_CL22_B0_PHYID2r(_unit, _pc, _val) \ 5316 TSC_REG_READ((_unit), (_pc), 0x00, 0x00000002, (_val)) 5317 #define WRITE_WC40_CL22_B0_PHYID2r(_unit, _pc, _val) \ 5318 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00000002, (_val)) 5319 #define MODIFY_WC40_CL22_B0_PHYID2r(_unit, _pc, _val, _mask) \ 5320 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00000002, (_val), (_mask)) 5321 5322 /* IEEE phyID3 Register: 00000000*/ 5323 #define READ_WC40_CL22_B0_PHYID3r(_unit, _pc, _val) \ 5324 TSC_REG_READ((_unit), (_pc), 0x00, 0x00000003, (_val)) 5325 #define WRITE_WC40_CL22_B0_PHYID3r(_unit, _pc, _val) \ 5326 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00000003, (_val)) 5327 #define MODIFY_WC40_CL22_B0_PHYID3r(_unit, _pc, _val, _mask) \ 5328 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00000003, (_val), (_mask)) 5329 5330 /* IEEE MMD Access Control Register: 00000000*/ 5331 #define READ_WC40_CL22_B0_MMDACCESSCONTROLr(_unit, _pc, _val) \ 5332 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000000d, (_val)) 5333 #define WRITE_WC40_CL22_B0_MMDACCESSCONTROLr(_unit, _pc, _val) \ 5334 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000000d, (_val)) 5335 #define MODIFY_WC40_CL22_B0_MMDACCESSCONTROLr(_unit, _pc, _val, _mask) \ 5336 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000000d, (_val), (_mask)) 5337 5338 /* IEEE MMD Address Data Register: 00000000*/ 5339 #define READ_WC40_CL22_B0_MMDACCESSADDRESSDATAr(_unit, _pc, _val) \ 5340 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000000e, (_val)) 5341 #define WRITE_WC40_CL22_B0_MMDACCESSADDRESSDATAr(_unit, _pc, _val) \ 5342 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000000e, (_val)) 5343 #define MODIFY_WC40_CL22_B0_MMDACCESSADDRESSDATAr(_unit, _pc, _val, _mask) \ 5344 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000000e, (_val), (_mask)) 5345 5346 5347 5348 /**************************************************************************** 5349 * TSC_IEEE_CL22_CL22_B1 5350 */ 5351 /* Block Address Register: 00000000*/ 5352 #define READ_WC40_CL22_B1_BLKADRr(_unit, _pc, _val) \ 5353 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000001f, (_val)) 5354 #define WRITE_WC40_CL22_B1_BLKADRr(_unit, _pc, _val) \ 5355 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000001f, (_val)) 5356 #define MODIFY_WC40_CL22_B1_BLKADRr(_unit, _pc, _val, _mask) \ 5357 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000001f, (_val), (_mask)) 5358 5359 5360 5361 /**************************************************************************** 5362 * TSC_WC4_TSC_USER1_Main0 5363 */ 5364 /* main control register: 00000000*/ 5365 #define READ_WC40_MAIN0_SETUPr(_unit, _pc, _val) \ 5366 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009000, (_val)) 5367 #define WRITE_WC40_MAIN0_SETUPr(_unit, _pc, _val) \ 5368 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009000, (_val)) 5369 #define MODIFY_WC40_MAIN0_SETUPr(_unit, _pc, _val, _mask) \ 5370 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009000, (_val), (_mask)) 5371 5372 /* reset control register: 00000000*/ 5373 #define READ_WC40_MAIN0_RESETr(_unit, _pc, _val) \ 5374 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009001, (_val)) 5375 #define WRITE_WC40_MAIN0_RESETr(_unit, _pc, _val) \ 5376 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009001, (_val)) 5377 #define MODIFY_WC40_MAIN0_RESETr(_unit, _pc, _val, _mask) \ 5378 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009001, (_val), (_mask)) 5379 5380 /* power control register: 00000000*/ 5381 #define READ_WC40_MAIN0_POWERr(_unit, _pc, _val) \ 5382 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009002, (_val)) 5383 #define WRITE_WC40_MAIN0_POWERr(_unit, _pc, _val) \ 5384 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009002, (_val)) 5385 #define MODIFY_WC40_MAIN0_POWERr(_unit, _pc, _val, _mask) \ 5386 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009002, (_val), (_mask)) 5387 5388 /* Lane Swap Control Register: 00000000*/ 5389 #define READ_WC40_MAIN0_LANE_SWAPr(_unit, _pc, _val) \ 5390 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009003, (_val)) 5391 #define WRITE_WC40_MAIN0_LANE_SWAPr(_unit, _pc, _val) \ 5392 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009003, (_val)) 5393 #define MODIFY_WC40_MAIN0_LANE_SWAPr(_unit, _pc, _val, _mask) \ 5394 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009003, (_val), (_mask)) 5395 5396 /* Devices in Package5: 00000000*/ 5397 #define READ_WC40_MAIN0_DEVICEINPKG5r(_unit, _pc, _val) \ 5398 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009004, (_val)) 5399 #define WRITE_WC40_MAIN0_DEVICEINPKG5r(_unit, _pc, _val) \ 5400 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009004, (_val)) 5401 #define MODIFY_WC40_MAIN0_DEVICEINPKG5r(_unit, _pc, _val, _mask) \ 5402 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009004, (_val), (_mask)) 5403 5404 /* Miscellaneous Controls: 00000000*/ 5405 #define READ_WC40_MAIN0_MISCr(_unit, _pc, _val) \ 5406 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009005, (_val)) 5407 #define WRITE_WC40_MAIN0_MISCr(_unit, _pc, _val) \ 5408 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009005, (_val)) 5409 #define MODIFY_WC40_MAIN0_MISCr(_unit, _pc, _val, _mask) \ 5410 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009005, (_val), (_mask)) 5411 5412 /* Temp Sensor Control Register: 00000000*/ 5413 #define READ_WC40_MAIN0_TEMP_SENSORr(_unit, _pc, _val) \ 5414 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009006, (_val)) 5415 #define WRITE_WC40_MAIN0_TEMP_SENSORr(_unit, _pc, _val) \ 5416 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009006, (_val)) 5417 #define MODIFY_WC40_MAIN0_TEMP_SENSORr(_unit, _pc, _val, _mask) \ 5418 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009006, (_val), (_mask)) 5419 5420 /* TICK GENERATION CONTROL REGISTER 1: 00000000*/ 5421 #define READ_WC40_MAIN0_TICK_CONTROL_1r(_unit, _pc, _val) \ 5422 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009007, (_val)) 5423 #define WRITE_WC40_MAIN0_TICK_CONTROL_1r(_unit, _pc, _val) \ 5424 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009007, (_val)) 5425 #define MODIFY_WC40_MAIN0_TICK_CONTROL_1r(_unit, _pc, _val, _mask) \ 5426 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009007, (_val), (_mask)) 5427 5428 /* TICK GENERATION CONTROL REGISTER 1: 00000000*/ 5429 #define READ_WC40_MAIN0_TICK_CONTROL_0r(_unit, _pc, _val) \ 5430 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009008, (_val)) 5431 #define WRITE_WC40_MAIN0_TICK_CONTROL_0r(_unit, _pc, _val) \ 5432 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009008, (_val)) 5433 #define MODIFY_WC40_MAIN0_TICK_CONTROL_0r(_unit, _pc, _val, _mask) \ 5434 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009008, (_val), (_mask)) 5435 5436 /* LOOPBACK CONTROL REGISTER: 00000000*/ 5437 #define READ_WC40_MAIN0_LOOPBACK_CONTROLr(_unit, _pc, _val) \ 5438 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009009, (_val)) 5439 #define WRITE_WC40_MAIN0_LOOPBACK_CONTROLr(_unit, _pc, _val) \ 5440 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009009, (_val)) 5441 #define MODIFY_WC40_MAIN0_LOOPBACK_CONTROLr(_unit, _pc, _val, _mask) \ 5442 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009009, (_val), (_mask)) 5443 5444 /* PRTAD Broadcast Values: 00000000*/ 5445 #define READ_WC40_MAIN0_MDIO_BROADCASTr(_unit, _pc, _val) \ 5446 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000900a, (_val)) 5447 #define WRITE_WC40_MAIN0_MDIO_BROADCASTr(_unit, _pc, _val) \ 5448 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000900a, (_val)) 5449 #define MODIFY_WC40_MAIN0_MDIO_BROADCASTr(_unit, _pc, _val, _mask) \ 5450 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000900a, (_val), (_mask)) 5451 5452 /* Serdes ID Register: 00000000*/ 5453 #define READ_WC40_MAIN0_SERDESIDr(_unit, _pc, _val) \ 5454 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000900e, (_val)) 5455 #define WRITE_WC40_MAIN0_SERDESIDr(_unit, _pc, _val) \ 5456 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000900e, (_val)) 5457 #define MODIFY_WC40_MAIN0_SERDESIDr(_unit, _pc, _val, _mask) \ 5458 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000900e, (_val), (_mask)) 5459 5460 5461 5462 /**************************************************************************** 5463 * TSC_WC4_TSC_USER1_anaPLL 5464 */ 5465 /* PLL status register: 00000000*/ 5466 #define READ_WC40_ANAPLL_STATUSr(_unit, _pc, _val) \ 5467 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009010, (_val)) 5468 #define WRITE_WC40_ANAPLL_STATUSr(_unit, _pc, _val) \ 5469 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009010, (_val)) 5470 #define MODIFY_WC40_ANAPLL_STATUSr(_unit, _pc, _val, _mask) \ 5471 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009010, (_val), (_mask)) 5472 5473 /* PLL control register: 00000000*/ 5474 #define READ_WC40_ANAPLL_CONTROLr(_unit, _pc, _val) \ 5475 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009011, (_val)) 5476 #define WRITE_WC40_ANAPLL_CONTROLr(_unit, _pc, _val) \ 5477 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009011, (_val)) 5478 #define MODIFY_WC40_ANAPLL_CONTROLr(_unit, _pc, _val, _mask) \ 5479 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009011, (_val), (_mask)) 5480 5481 /* PLL start up state machine vco timers: 00000000*/ 5482 #define READ_WC40_ANAPLL_TIMER1r(_unit, _pc, _val) \ 5483 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009012, (_val)) 5484 #define WRITE_WC40_ANAPLL_TIMER1r(_unit, _pc, _val) \ 5485 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009012, (_val)) 5486 #define MODIFY_WC40_ANAPLL_TIMER1r(_unit, _pc, _val, _mask) \ 5487 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009012, (_val), (_mask)) 5488 5489 /* PLL start up state machine retry timer: 00000000*/ 5490 #define READ_WC40_ANAPLL_TIMER2r(_unit, _pc, _val) \ 5491 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009013, (_val)) 5492 #define WRITE_WC40_ANAPLL_TIMER2r(_unit, _pc, _val) \ 5493 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009013, (_val)) 5494 #define MODIFY_WC40_ANAPLL_TIMER2r(_unit, _pc, _val, _mask) \ 5495 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009013, (_val), (_mask)) 5496 5497 /* PLL start up state machine freq. detect timer: 00000000*/ 5498 #define READ_WC40_ANAPLL_TIMER3r(_unit, _pc, _val) \ 5499 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009014, (_val)) 5500 #define WRITE_WC40_ANAPLL_TIMER3r(_unit, _pc, _val) \ 5501 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009014, (_val)) 5502 #define MODIFY_WC40_ANAPLL_TIMER3r(_unit, _pc, _val, _mask) \ 5503 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009014, (_val), (_mask)) 5504 5505 /* PLL vco range control state machine: 00000000*/ 5506 #define READ_WC40_ANAPLL_CAPCONTROLr(_unit, _pc, _val) \ 5507 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009015, (_val)) 5508 #define WRITE_WC40_ANAPLL_CAPCONTROLr(_unit, _pc, _val) \ 5509 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009015, (_val)) 5510 #define MODIFY_WC40_ANAPLL_CAPCONTROLr(_unit, _pc, _val, _mask) \ 5511 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009015, (_val), (_mask)) 5512 5513 /* Debug status testmux bus: 00000000*/ 5514 #define READ_WC40_ANAPLL_ANAPLL_DEBUG_STATUSr(_unit, _pc, _val) \ 5515 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009016, (_val)) 5516 #define WRITE_WC40_ANAPLL_ANAPLL_DEBUG_STATUSr(_unit, _pc, _val) \ 5517 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009016, (_val)) 5518 #define MODIFY_WC40_ANAPLL_ANAPLL_DEBUG_STATUSr(_unit, _pc, _val, _mask) \ 5519 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009016, (_val), (_mask)) 5520 5521 /* Frequency detector control: 00000000*/ 5522 #define READ_WC40_ANAPLL_FREQDETCNTRr(_unit, _pc, _val) \ 5523 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009017, (_val)) 5524 #define WRITE_WC40_ANAPLL_FREQDETCNTRr(_unit, _pc, _val) \ 5525 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009017, (_val)) 5526 #define MODIFY_WC40_ANAPLL_FREQDETCNTRr(_unit, _pc, _val, _mask) \ 5527 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009017, (_val), (_mask)) 5528 5529 /* PLL analog status (AFE pll_sts[15:0], not applicable to XFICore): 00000000*/ 5530 #define READ_WC40_ANAPLL_ASTATUS1r(_unit, _pc, _val) \ 5531 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009018, (_val)) 5532 #define WRITE_WC40_ANAPLL_ASTATUS1r(_unit, _pc, _val) \ 5533 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009018, (_val)) 5534 #define MODIFY_WC40_ANAPLL_ASTATUS1r(_unit, _pc, _val, _mask) \ 5535 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009018, (_val), (_mask)) 5536 5537 /* PLL analog controls (AFE pll_clrl[15:00], not applicable to XFICore): 00000000*/ 5538 #define READ_WC40_ANAPLL_ACONTROL0r(_unit, _pc, _val) \ 5539 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000901a, (_val)) 5540 #define WRITE_WC40_ANAPLL_ACONTROL0r(_unit, _pc, _val) \ 5541 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000901a, (_val)) 5542 #define MODIFY_WC40_ANAPLL_ACONTROL0r(_unit, _pc, _val, _mask) \ 5543 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000901a, (_val), (_mask)) 5544 5545 /* PLL analog controls (AFE pll_ctrl[31:16], not applicable to XFICore): 00000000*/ 5546 #define READ_WC40_ANAPLL_ACONTROL1r(_unit, _pc, _val) \ 5547 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000901b, (_val)) 5548 #define WRITE_WC40_ANAPLL_ACONTROL1r(_unit, _pc, _val) \ 5549 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000901b, (_val)) 5550 #define MODIFY_WC40_ANAPLL_ACONTROL1r(_unit, _pc, _val, _mask) \ 5551 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000901b, (_val), (_mask)) 5552 5553 /* PLL analog controls (AFE pll_ctrl[47:32], not applicable to XFICore): 00000000*/ 5554 #define READ_WC40_ANAPLL_ACONTROL2r(_unit, _pc, _val) \ 5555 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000901c, (_val)) 5556 #define WRITE_WC40_ANAPLL_ACONTROL2r(_unit, _pc, _val) \ 5557 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000901c, (_val)) 5558 #define MODIFY_WC40_ANAPLL_ACONTROL2r(_unit, _pc, _val, _mask) \ 5559 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000901c, (_val), (_mask)) 5560 5561 /* PLL analog controls (AFE pll_ctrl[63:48], not applicable to XFICore): 00000000*/ 5562 #define READ_WC40_ANAPLL_ACONTROL3r(_unit, _pc, _val) \ 5563 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000901d, (_val)) 5564 #define WRITE_WC40_ANAPLL_ACONTROL3r(_unit, _pc, _val) \ 5565 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000901d, (_val)) 5566 #define MODIFY_WC40_ANAPLL_ACONTROL3r(_unit, _pc, _val, _mask) \ 5567 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000901d, (_val), (_mask)) 5568 5569 /* PLL analog controls (AFE pll_ctrl[79:64], not applicable to XFICore): 00000000*/ 5570 #define READ_WC40_ANAPLL_ACONTROL4r(_unit, _pc, _val) \ 5571 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000901e, (_val)) 5572 #define WRITE_WC40_ANAPLL_ACONTROL4r(_unit, _pc, _val) \ 5573 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000901e, (_val)) 5574 #define MODIFY_WC40_ANAPLL_ACONTROL4r(_unit, _pc, _val, _mask) \ 5575 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000901e, (_val), (_mask)) 5576 5577 5578 5579 /**************************************************************************** 5580 * TSC_WC4_TSC_USER1_PktGen0 5581 */ 5582 /* Number of Packets: 00000000*/ 5583 #define READ_WC40_PKTGEN0_PKTGENCTRL1r(_unit, _pc, _val) \ 5584 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009030, (_val)) 5585 #define WRITE_WC40_PKTGEN0_PKTGENCTRL1r(_unit, _pc, _val) \ 5586 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009030, (_val)) 5587 #define MODIFY_WC40_PKTGEN0_PKTGENCTRL1r(_unit, _pc, _val, _mask) \ 5588 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009030, (_val), (_mask)) 5589 5590 /* Packet and IPG Size: 00000000*/ 5591 #define READ_WC40_PKTGEN0_PKTGENCTRL2r(_unit, _pc, _val) \ 5592 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009031, (_val)) 5593 #define WRITE_WC40_PKTGEN0_PKTGENCTRL2r(_unit, _pc, _val) \ 5594 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009031, (_val)) 5595 #define MODIFY_WC40_PKTGEN0_PKTGENCTRL2r(_unit, _pc, _val, _mask) \ 5596 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009031, (_val), (_mask)) 5597 5598 /* PRTP CONTROLS: 00000000*/ 5599 #define READ_WC40_PKTGEN0_PRTPCONTROLr(_unit, _pc, _val) \ 5600 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009032, (_val)) 5601 #define WRITE_WC40_PKTGEN0_PRTPCONTROLr(_unit, _pc, _val) \ 5602 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009032, (_val)) 5603 #define MODIFY_WC40_PKTGEN0_PRTPCONTROLr(_unit, _pc, _val, _mask) \ 5604 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009032, (_val), (_mask)) 5605 5606 /* CRC Error Count Register: 00000000*/ 5607 #define READ_WC40_PKTGEN0_CRCERRORCOUNTr(_unit, _pc, _val) \ 5608 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009033, (_val)) 5609 #define WRITE_WC40_PKTGEN0_CRCERRORCOUNTr(_unit, _pc, _val) \ 5610 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009033, (_val)) 5611 #define MODIFY_WC40_PKTGEN0_CRCERRORCOUNTr(_unit, _pc, _val, _mask) \ 5612 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009033, (_val), (_mask)) 5613 5614 /* PRTP Error Count Register: 00000000*/ 5615 #define READ_WC40_PKTGEN0_PRTPERRORCOUNTERr(_unit, _pc, _val) \ 5616 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009034, (_val)) 5617 #define WRITE_WC40_PKTGEN0_PRTPERRORCOUNTERr(_unit, _pc, _val) \ 5618 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009034, (_val)) 5619 #define MODIFY_WC40_PKTGEN0_PRTPERRORCOUNTERr(_unit, _pc, _val, _mask) \ 5620 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009034, (_val), (_mask)) 5621 5622 /* 10GBASE-R PCS 0022 test pattern seed A word bits 15:00: 00000000*/ 5623 #define READ_WC40_PKTGEN0_PCS_SEEDA0r(_unit, _pc, _val) \ 5624 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009037, (_val)) 5625 #define WRITE_WC40_PKTGEN0_PCS_SEEDA0r(_unit, _pc, _val) \ 5626 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009037, (_val)) 5627 #define MODIFY_WC40_PKTGEN0_PCS_SEEDA0r(_unit, _pc, _val, _mask) \ 5628 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009037, (_val), (_mask)) 5629 5630 /* 10GBASE-R PCS 0023 test pattern seed A word bits 31:16: 00000000*/ 5631 #define READ_WC40_PKTGEN0_PCS_SEEDA1r(_unit, _pc, _val) \ 5632 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009038, (_val)) 5633 #define WRITE_WC40_PKTGEN0_PCS_SEEDA1r(_unit, _pc, _val) \ 5634 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009038, (_val)) 5635 #define MODIFY_WC40_PKTGEN0_PCS_SEEDA1r(_unit, _pc, _val, _mask) \ 5636 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009038, (_val), (_mask)) 5637 5638 /* 10GBASE-R PCS 0024 test pattern seed A word bits 47:32: 00000000*/ 5639 #define READ_WC40_PKTGEN0_PCS_SEEDA2r(_unit, _pc, _val) \ 5640 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009039, (_val)) 5641 #define WRITE_WC40_PKTGEN0_PCS_SEEDA2r(_unit, _pc, _val) \ 5642 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009039, (_val)) 5643 #define MODIFY_WC40_PKTGEN0_PCS_SEEDA2r(_unit, _pc, _val, _mask) \ 5644 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009039, (_val), (_mask)) 5645 5646 /* 10GBASE-R PCS 0025 test pattern seed A word bits 57:48: 00000000*/ 5647 #define READ_WC40_PKTGEN0_PCS_SEEDA3r(_unit, _pc, _val) \ 5648 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000903a, (_val)) 5649 #define WRITE_WC40_PKTGEN0_PCS_SEEDA3r(_unit, _pc, _val) \ 5650 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000903a, (_val)) 5651 #define MODIFY_WC40_PKTGEN0_PCS_SEEDA3r(_unit, _pc, _val, _mask) \ 5652 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000903a, (_val), (_mask)) 5653 5654 /* 10GBASE-R PCS 0026 test pattern seed B word bits 15:00: 00000000*/ 5655 #define READ_WC40_PKTGEN0_PCS_SEEDB0r(_unit, _pc, _val) \ 5656 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000903b, (_val)) 5657 #define WRITE_WC40_PKTGEN0_PCS_SEEDB0r(_unit, _pc, _val) \ 5658 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000903b, (_val)) 5659 #define MODIFY_WC40_PKTGEN0_PCS_SEEDB0r(_unit, _pc, _val, _mask) \ 5660 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000903b, (_val), (_mask)) 5661 5662 /* 10GBASE-R PCS 0027 test pattern seed B word bits 31:16: 00000000*/ 5663 #define READ_WC40_PKTGEN0_PCS_SEEDB1r(_unit, _pc, _val) \ 5664 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000903c, (_val)) 5665 #define WRITE_WC40_PKTGEN0_PCS_SEEDB1r(_unit, _pc, _val) \ 5666 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000903c, (_val)) 5667 #define MODIFY_WC40_PKTGEN0_PCS_SEEDB1r(_unit, _pc, _val, _mask) \ 5668 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000903c, (_val), (_mask)) 5669 5670 /* 10GBASE-R PCS 0028 test pattern seed B word bits 47:32: 00000000*/ 5671 #define READ_WC40_PKTGEN0_PCS_SEEDB2r(_unit, _pc, _val) \ 5672 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000903d, (_val)) 5673 #define WRITE_WC40_PKTGEN0_PCS_SEEDB2r(_unit, _pc, _val) \ 5674 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000903d, (_val)) 5675 #define MODIFY_WC40_PKTGEN0_PCS_SEEDB2r(_unit, _pc, _val, _mask) \ 5676 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000903d, (_val), (_mask)) 5677 5678 /* 10GBASE-R PCS 0029 test pattern seed B word bits 57:48: 00000000*/ 5679 #define READ_WC40_PKTGEN0_PCS_SEEDB3r(_unit, _pc, _val) \ 5680 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000903e, (_val)) 5681 #define WRITE_WC40_PKTGEN0_PCS_SEEDB3r(_unit, _pc, _val) \ 5682 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000903e, (_val)) 5683 #define MODIFY_WC40_PKTGEN0_PCS_SEEDB3r(_unit, _pc, _val, _mask) \ 5684 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000903e, (_val), (_mask)) 5685 5686 5687 5688 /**************************************************************************** 5689 * TSC_WC4_TSC_USER1_PktGen1 5690 */ 5691 /* Repeated Payload Bytes: 00000000*/ 5692 #define READ_WC40_PKTGEN1_PAYLOADBYTESr(_unit, _pc, _val) \ 5693 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009040, (_val)) 5694 #define WRITE_WC40_PKTGEN1_PAYLOADBYTESr(_unit, _pc, _val) \ 5695 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009040, (_val)) 5696 #define MODIFY_WC40_PKTGEN1_PAYLOADBYTESr(_unit, _pc, _val, _mask) \ 5697 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009040, (_val), (_mask)) 5698 5699 /* Error mask bits 79:64: 00000000*/ 5700 #define READ_WC40_PKTGEN1_ERRORMASK4r(_unit, _pc, _val) \ 5701 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009041, (_val)) 5702 #define WRITE_WC40_PKTGEN1_ERRORMASK4r(_unit, _pc, _val) \ 5703 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009041, (_val)) 5704 #define MODIFY_WC40_PKTGEN1_ERRORMASK4r(_unit, _pc, _val, _mask) \ 5705 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009041, (_val), (_mask)) 5706 5707 /* Error mask bits 63:48: 00000000*/ 5708 #define READ_WC40_PKTGEN1_ERRORMASK3r(_unit, _pc, _val) \ 5709 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009042, (_val)) 5710 #define WRITE_WC40_PKTGEN1_ERRORMASK3r(_unit, _pc, _val) \ 5711 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009042, (_val)) 5712 #define MODIFY_WC40_PKTGEN1_ERRORMASK3r(_unit, _pc, _val, _mask) \ 5713 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009042, (_val), (_mask)) 5714 5715 /* Error mask bits 47:32: 00000000*/ 5716 #define READ_WC40_PKTGEN1_ERRORMASK2r(_unit, _pc, _val) \ 5717 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009043, (_val)) 5718 #define WRITE_WC40_PKTGEN1_ERRORMASK2r(_unit, _pc, _val) \ 5719 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009043, (_val)) 5720 #define MODIFY_WC40_PKTGEN1_ERRORMASK2r(_unit, _pc, _val, _mask) \ 5721 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009043, (_val), (_mask)) 5722 5723 /* Error mask bits 31:16: 00000000*/ 5724 #define READ_WC40_PKTGEN1_ERRORMASK1r(_unit, _pc, _val) \ 5725 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009044, (_val)) 5726 #define WRITE_WC40_PKTGEN1_ERRORMASK1r(_unit, _pc, _val) \ 5727 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009044, (_val)) 5728 #define MODIFY_WC40_PKTGEN1_ERRORMASK1r(_unit, _pc, _val, _mask) \ 5729 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009044, (_val), (_mask)) 5730 5731 /* Error mask bits 15:0: 00000000*/ 5732 #define READ_WC40_PKTGEN1_ERRORMASK0r(_unit, _pc, _val) \ 5733 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009045, (_val)) 5734 #define WRITE_WC40_PKTGEN1_ERRORMASK0r(_unit, _pc, _val) \ 5735 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009045, (_val)) 5736 #define MODIFY_WC40_PKTGEN1_ERRORMASK0r(_unit, _pc, _val, _mask) \ 5737 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009045, (_val), (_mask)) 5738 5739 /* test control register: 00000000*/ 5740 #define READ_WC40_PKTGEN1_PRTP_TEST_COUNTSr(_unit, _pc, _val) \ 5741 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009046, (_val)) 5742 #define WRITE_WC40_PKTGEN1_PRTP_TEST_COUNTSr(_unit, _pc, _val) \ 5743 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009046, (_val)) 5744 #define MODIFY_WC40_PKTGEN1_PRTP_TEST_COUNTSr(_unit, _pc, _val, _mask) \ 5745 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009046, (_val), (_mask)) 5746 5747 5748 5749 /**************************************************************************** 5750 * TSC_WC4_TSC_USER1_PATGEN_256_0 5751 */ 5752 /* Pattern Genertor 0 Register: 00000000*/ 5753 #define READ_WC40_PATGEN_256_0_REG0r(_unit, _pc, _val) \ 5754 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009050, (_val)) 5755 #define WRITE_WC40_PATGEN_256_0_REG0r(_unit, _pc, _val) \ 5756 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009050, (_val)) 5757 #define MODIFY_WC40_PATGEN_256_0_REG0r(_unit, _pc, _val, _mask) \ 5758 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009050, (_val), (_mask)) 5759 5760 /* Pattern Genertor 1 Register: 00000000*/ 5761 #define READ_WC40_PATGEN_256_0_REG1r(_unit, _pc, _val) \ 5762 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009051, (_val)) 5763 #define WRITE_WC40_PATGEN_256_0_REG1r(_unit, _pc, _val) \ 5764 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009051, (_val)) 5765 #define MODIFY_WC40_PATGEN_256_0_REG1r(_unit, _pc, _val, _mask) \ 5766 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009051, (_val), (_mask)) 5767 5768 /* Pattern Genertor 2 Register: 00000000*/ 5769 #define READ_WC40_PATGEN_256_0_REG2r(_unit, _pc, _val) \ 5770 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009052, (_val)) 5771 #define WRITE_WC40_PATGEN_256_0_REG2r(_unit, _pc, _val) \ 5772 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009052, (_val)) 5773 #define MODIFY_WC40_PATGEN_256_0_REG2r(_unit, _pc, _val, _mask) \ 5774 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009052, (_val), (_mask)) 5775 5776 /* Pattern Genertor 3 Register: 00000000*/ 5777 #define READ_WC40_PATGEN_256_0_REG3r(_unit, _pc, _val) \ 5778 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009053, (_val)) 5779 #define WRITE_WC40_PATGEN_256_0_REG3r(_unit, _pc, _val) \ 5780 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009053, (_val)) 5781 #define MODIFY_WC40_PATGEN_256_0_REG3r(_unit, _pc, _val, _mask) \ 5782 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009053, (_val), (_mask)) 5783 5784 /* Pattern Genertor 4 Register: 00000000*/ 5785 #define READ_WC40_PATGEN_256_0_REG4r(_unit, _pc, _val) \ 5786 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009054, (_val)) 5787 #define WRITE_WC40_PATGEN_256_0_REG4r(_unit, _pc, _val) \ 5788 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009054, (_val)) 5789 #define MODIFY_WC40_PATGEN_256_0_REG4r(_unit, _pc, _val, _mask) \ 5790 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009054, (_val), (_mask)) 5791 5792 /* Pattern Genertor 5 Register: 00000000*/ 5793 #define READ_WC40_PATGEN_256_0_REG5r(_unit, _pc, _val) \ 5794 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009055, (_val)) 5795 #define WRITE_WC40_PATGEN_256_0_REG5r(_unit, _pc, _val) \ 5796 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009055, (_val)) 5797 #define MODIFY_WC40_PATGEN_256_0_REG5r(_unit, _pc, _val, _mask) \ 5798 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009055, (_val), (_mask)) 5799 5800 /* Pattern Genertor 6 Register: 00000000*/ 5801 #define READ_WC40_PATGEN_256_0_REG6r(_unit, _pc, _val) \ 5802 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009056, (_val)) 5803 #define WRITE_WC40_PATGEN_256_0_REG6r(_unit, _pc, _val) \ 5804 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009056, (_val)) 5805 #define MODIFY_WC40_PATGEN_256_0_REG6r(_unit, _pc, _val, _mask) \ 5806 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009056, (_val), (_mask)) 5807 5808 /* Pattern Genertor 7 Register: 00000000*/ 5809 #define READ_WC40_PATGEN_256_0_REG7r(_unit, _pc, _val) \ 5810 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009057, (_val)) 5811 #define WRITE_WC40_PATGEN_256_0_REG7r(_unit, _pc, _val) \ 5812 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009057, (_val)) 5813 #define MODIFY_WC40_PATGEN_256_0_REG7r(_unit, _pc, _val, _mask) \ 5814 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009057, (_val), (_mask)) 5815 5816 /* Pattern Genertor 8 Register: 00000000*/ 5817 #define READ_WC40_PATGEN_256_0_REG8r(_unit, _pc, _val) \ 5818 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009058, (_val)) 5819 #define WRITE_WC40_PATGEN_256_0_REG8r(_unit, _pc, _val) \ 5820 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009058, (_val)) 5821 #define MODIFY_WC40_PATGEN_256_0_REG8r(_unit, _pc, _val, _mask) \ 5822 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009058, (_val), (_mask)) 5823 5824 /* Pattern Genertor 9 Register: 00000000*/ 5825 #define READ_WC40_PATGEN_256_0_REG9r(_unit, _pc, _val) \ 5826 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009059, (_val)) 5827 #define WRITE_WC40_PATGEN_256_0_REG9r(_unit, _pc, _val) \ 5828 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009059, (_val)) 5829 #define MODIFY_WC40_PATGEN_256_0_REG9r(_unit, _pc, _val, _mask) \ 5830 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009059, (_val), (_mask)) 5831 5832 /* Pattern Genertor 10 Register: 00000000*/ 5833 #define READ_WC40_PATGEN_256_0_REG10r(_unit, _pc, _val) \ 5834 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000905a, (_val)) 5835 #define WRITE_WC40_PATGEN_256_0_REG10r(_unit, _pc, _val) \ 5836 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000905a, (_val)) 5837 #define MODIFY_WC40_PATGEN_256_0_REG10r(_unit, _pc, _val, _mask) \ 5838 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000905a, (_val), (_mask)) 5839 5840 /* Pattern Genertor 11 Register: 00000000*/ 5841 #define READ_WC40_PATGEN_256_0_REG11r(_unit, _pc, _val) \ 5842 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000905b, (_val)) 5843 #define WRITE_WC40_PATGEN_256_0_REG11r(_unit, _pc, _val) \ 5844 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000905b, (_val)) 5845 #define MODIFY_WC40_PATGEN_256_0_REG11r(_unit, _pc, _val, _mask) \ 5846 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000905b, (_val), (_mask)) 5847 5848 /* Pattern Genertor 12 Register: 00000000*/ 5849 #define READ_WC40_PATGEN_256_0_REG12r(_unit, _pc, _val) \ 5850 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000905c, (_val)) 5851 #define WRITE_WC40_PATGEN_256_0_REG12r(_unit, _pc, _val) \ 5852 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000905c, (_val)) 5853 #define MODIFY_WC40_PATGEN_256_0_REG12r(_unit, _pc, _val, _mask) \ 5854 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000905c, (_val), (_mask)) 5855 5856 /* Pattern Genertor 13 Register: 00000000*/ 5857 #define READ_WC40_PATGEN_256_0_REG13r(_unit, _pc, _val) \ 5858 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000905d, (_val)) 5859 #define WRITE_WC40_PATGEN_256_0_REG13r(_unit, _pc, _val) \ 5860 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000905d, (_val)) 5861 #define MODIFY_WC40_PATGEN_256_0_REG13r(_unit, _pc, _val, _mask) \ 5862 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000905d, (_val), (_mask)) 5863 5864 /* Pattern Genertor 14 Register: 00000000*/ 5865 #define READ_WC40_PATGEN_256_0_REG14r(_unit, _pc, _val) \ 5866 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000905e, (_val)) 5867 #define WRITE_WC40_PATGEN_256_0_REG14r(_unit, _pc, _val) \ 5868 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000905e, (_val)) 5869 #define MODIFY_WC40_PATGEN_256_0_REG14r(_unit, _pc, _val, _mask) \ 5870 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000905e, (_val), (_mask)) 5871 5872 5873 5874 /**************************************************************************** 5875 * TSC_WC4_TSC_USER1_PATGEN_256_1 5876 */ 5877 /* Pattern Genertor F Register: 00000000*/ 5878 #define READ_WC40_PATGEN_256_1_REGFr(_unit, _pc, _val) \ 5879 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009060, (_val)) 5880 #define WRITE_WC40_PATGEN_256_1_REGFr(_unit, _pc, _val) \ 5881 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009060, (_val)) 5882 #define MODIFY_WC40_PATGEN_256_1_REGFr(_unit, _pc, _val, _mask) \ 5883 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009060, (_val), (_mask)) 5884 5885 /* Prbs Error Check Config: 00000000*/ 5886 #define READ_WC40_PATGEN_256_1_PRBSERRCHKCFGr(_unit, _pc, _val) \ 5887 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009061, (_val)) 5888 #define WRITE_WC40_PATGEN_256_1_PRBSERRCHKCFGr(_unit, _pc, _val) \ 5889 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009061, (_val)) 5890 #define MODIFY_WC40_PATGEN_256_1_PRBSERRCHKCFGr(_unit, _pc, _val, _mask) \ 5891 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009061, (_val), (_mask)) 5892 5893 5894 5895 /**************************************************************************** 5896 * TSC_XgxsBlk1 5897 */ 5898 /* Lane test control register: 00000000*/ 5899 #define READ_WC40_XGXSBLK1_LANETESTr(_unit, _pc, _val) \ 5900 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000909a, (_val)) 5901 #define WRITE_WC40_XGXSBLK1_LANETESTr(_unit, _pc, _val) \ 5902 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000909a, (_val)) 5903 #define MODIFY_WC40_XGXSBLK1_LANETESTr(_unit, _pc, _val, _mask) \ 5904 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000909a, (_val), (_mask)) 5905 5906 5907 5908 /**************************************************************************** 5909 * TSC_XgxsBlk4 5910 */ 5911 /* XGXS status register: 00000000*/ 5912 #define READ_WC40_XGXSBLK4_XGXSSTATUS0r(_unit, _pc, _val) \ 5913 TSC_REG_READ((_unit), (_pc), 0x00, 0x000090b1, (_val)) 5914 #define WRITE_WC40_XGXSBLK4_XGXSSTATUS0r(_unit, _pc, _val) \ 5915 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x000090b1, (_val)) 5916 #define MODIFY_WC40_XGXSBLK4_XGXSSTATUS0r(_unit, _pc, _val, _mask) \ 5917 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x000090b1, (_val), (_mask)) 5918 5919 5920 5921 /**************************************************************************** 5922 * TSC_GP2 5923 */ 5924 /* GP2 status 8 register: 00000000*/ 5925 #define READ_WC40_GP2_REG_8r(_unit, _pc, _val) \ 5926 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009108, (_val)) 5927 #define WRITE_WC40_GP2_REG_8r(_unit, _pc, _val) \ 5928 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009108, (_val)) 5929 #define MODIFY_WC40_GP2_REG_8r(_unit, _pc, _val, _mask) \ 5930 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009108, (_val), (_mask)) 5931 5932 5933 5934 /**************************************************************************** 5935 * TSC_CL72_Shared 5936 */ 5937 /* AN OS Default Control Register: 00000000*/ 5938 #define READ_WC40_CL72_SHARED_AN_OS_DEFAULT_CONTROLr(_unit, _pc, _val) \ 5939 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009111, (_val)) 5940 #define WRITE_WC40_CL72_SHARED_AN_OS_DEFAULT_CONTROLr(_unit, _pc, _val) \ 5941 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009111, (_val)) 5942 #define MODIFY_WC40_CL72_SHARED_AN_OS_DEFAULT_CONTROLr(_unit, _pc, _val, _mask) \ 5943 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009111, (_val), (_mask)) 5944 5945 /* AN BR Default Control Register: 00000000*/ 5946 #define READ_WC40_CL72_SHARED_AN_BR_DEFAULT_CONTROLr(_unit, _pc, _val) \ 5947 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009112, (_val)) 5948 #define WRITE_WC40_CL72_SHARED_AN_BR_DEFAULT_CONTROLr(_unit, _pc, _val) \ 5949 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009112, (_val)) 5950 #define MODIFY_WC40_CL72_SHARED_AN_BR_DEFAULT_CONTROLr(_unit, _pc, _val, _mask) \ 5951 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009112, (_val), (_mask)) 5952 5953 /* AN 2p5 Default Control Register: 00000000*/ 5954 #define READ_WC40_CL72_SHARED_AN_TWOP5_DEFAULT_CONTROLr(_unit, _pc, _val) \ 5955 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009113, (_val)) 5956 #define WRITE_WC40_CL72_SHARED_AN_TWOP5_DEFAULT_CONTROLr(_unit, _pc, _val) \ 5957 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009113, (_val)) 5958 #define MODIFY_WC40_CL72_SHARED_AN_TWOP5_DEFAULT_CONTROLr(_unit, _pc, _val, _mask) \ 5959 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009113, (_val), (_mask)) 5960 5961 /* CL72 Tap Limit Control Register: 00000000*/ 5962 #define READ_WC40_CL72_SHARED_CL72_TAP_LIMIT_CONTROLr(_unit, _pc, _val) \ 5963 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009114, (_val)) 5964 #define WRITE_WC40_CL72_SHARED_CL72_TAP_LIMIT_CONTROLr(_unit, _pc, _val) \ 5965 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009114, (_val)) 5966 #define MODIFY_WC40_CL72_SHARED_CL72_TAP_LIMIT_CONTROLr(_unit, _pc, _val, _mask) \ 5967 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009114, (_val), (_mask)) 5968 5969 /* CL72 Miscellaneous_3 Control Register: 00000000*/ 5970 #define READ_WC40_CL72_SHARED_CL72_MISC3_CONTROLr(_unit, _pc, _val) \ 5971 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009115, (_val)) 5972 #define WRITE_WC40_CL72_SHARED_CL72_MISC3_CONTROLr(_unit, _pc, _val) \ 5973 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009115, (_val)) 5974 #define MODIFY_WC40_CL72_SHARED_CL72_MISC3_CONTROLr(_unit, _pc, _val, _mask) \ 5975 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009115, (_val), (_mask)) 5976 5977 /* CL72 Tap Present Control Register: 00000000*/ 5978 #define READ_WC40_CL72_SHARED_CL72_TAP_PRESET_CONTROLr(_unit, _pc, _val) \ 5979 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009116, (_val)) 5980 #define WRITE_WC40_CL72_SHARED_CL72_TAP_PRESET_CONTROLr(_unit, _pc, _val) \ 5981 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009116, (_val)) 5982 #define MODIFY_WC40_CL72_SHARED_CL72_TAP_PRESET_CONTROLr(_unit, _pc, _val, _mask) \ 5983 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009116, (_val), (_mask)) 5984 5985 /* CL72 Debug 1 Register: 00000000*/ 5986 #define READ_WC40_CL72_SHARED_CL72_DEBUG_1_REGISTERr(_unit, _pc, _val) \ 5987 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009117, (_val)) 5988 #define WRITE_WC40_CL72_SHARED_CL72_DEBUG_1_REGISTERr(_unit, _pc, _val) \ 5989 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009117, (_val)) 5990 #define MODIFY_WC40_CL72_SHARED_CL72_DEBUG_1_REGISTERr(_unit, _pc, _val, _mask) \ 5991 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009117, (_val), (_mask)) 5992 5993 /* CL72 PRBS CONTROL REGISTER: 00000000*/ 5994 #define READ_WC40_CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPEr(_unit, _pc, _val) \ 5995 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009118, (_val)) 5996 #define WRITE_WC40_CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPEr(_unit, _pc, _val) \ 5997 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009118, (_val)) 5998 #define MODIFY_WC40_CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPEr(_unit, _pc, _val, _mask) \ 5999 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009118, (_val), (_mask)) 6000 6001 6002 6003 /**************************************************************************** 6004 * TSC_CL82_Shared 6005 */ 6006 /* cl82 rx AM timer register: 00000000*/ 6007 #define READ_WC40_CL82_SHARED_CL82_RX_AM_TIMERr(_unit, _pc, _val) \ 6008 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009123, (_val)) 6009 #define WRITE_WC40_CL82_SHARED_CL82_RX_AM_TIMERr(_unit, _pc, _val) \ 6010 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009123, (_val)) 6011 #define MODIFY_WC40_CL82_SHARED_CL82_RX_AM_TIMERr(_unit, _pc, _val, _mask) \ 6012 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009123, (_val), (_mask)) 6013 6014 6015 6016 /**************************************************************************** 6017 * TSC_CL82_AM_regs 6018 */ 6019 /* cl82 LANE 0 AM BYTES 1 AND 0 register: 00000000*/ 6020 #define READ_WC40_CL82_AM_REGS_LANE_0_AM_BYTE10r(_unit, _pc, _val) \ 6021 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009130, (_val)) 6022 #define WRITE_WC40_CL82_AM_REGS_LANE_0_AM_BYTE10r(_unit, _pc, _val) \ 6023 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009130, (_val)) 6024 #define MODIFY_WC40_CL82_AM_REGS_LANE_0_AM_BYTE10r(_unit, _pc, _val, _mask) \ 6025 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009130, (_val), (_mask)) 6026 6027 /* cl82 LANE 1 AM BYTES 1 AND 0 register: 00000000*/ 6028 #define READ_WC40_CL82_AM_REGS_LANE_1_AM_BYTE10r(_unit, _pc, _val) \ 6029 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009131, (_val)) 6030 #define WRITE_WC40_CL82_AM_REGS_LANE_1_AM_BYTE10r(_unit, _pc, _val) \ 6031 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009131, (_val)) 6032 #define MODIFY_WC40_CL82_AM_REGS_LANE_1_AM_BYTE10r(_unit, _pc, _val, _mask) \ 6033 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009131, (_val), (_mask)) 6034 6035 /* cl82 LANES 1 and 0 AM BYTE 2 register: 00000000*/ 6036 #define READ_WC40_CL82_AM_REGS_LANES_1_0_AM_BYTE2r(_unit, _pc, _val) \ 6037 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009132, (_val)) 6038 #define WRITE_WC40_CL82_AM_REGS_LANES_1_0_AM_BYTE2r(_unit, _pc, _val) \ 6039 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009132, (_val)) 6040 #define MODIFY_WC40_CL82_AM_REGS_LANES_1_0_AM_BYTE2r(_unit, _pc, _val, _mask) \ 6041 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009132, (_val), (_mask)) 6042 6043 6044 6045 /**************************************************************************** 6046 * TSC_CL82_AM_regs_tsc_12 6047 */ 6048 /* cl82 LANE 2 AM BYTES 1 AND 0 register: 00000000*/ 6049 #define READ_WC40_CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10r(_unit, _pc, _val) \ 6050 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009140, (_val)) 6051 #define WRITE_WC40_CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10r(_unit, _pc, _val) \ 6052 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009140, (_val)) 6053 #define MODIFY_WC40_CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10r(_unit, _pc, _val, _mask) \ 6054 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009140, (_val), (_mask)) 6055 6056 /* cl82 LANE 3 AM BYTES 1 AND 0 register: 00000000*/ 6057 #define READ_WC40_CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10r(_unit, _pc, _val) \ 6058 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009141, (_val)) 6059 #define WRITE_WC40_CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10r(_unit, _pc, _val) \ 6060 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009141, (_val)) 6061 #define MODIFY_WC40_CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10r(_unit, _pc, _val, _mask) \ 6062 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009141, (_val), (_mask)) 6063 6064 /* cl82 LANES 3 and 2 AM BYTE 2 register: 00000000*/ 6065 #define READ_WC40_CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2r(_unit, _pc, _val) \ 6066 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009142, (_val)) 6067 #define WRITE_WC40_CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2r(_unit, _pc, _val) \ 6068 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009142, (_val)) 6069 #define MODIFY_WC40_CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2r(_unit, _pc, _val, _mask) \ 6070 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009142, (_val), (_mask)) 6071 6072 6073 6074 /**************************************************************************** 6075 * TSC_TX_X1_Control0 6076 */ 6077 /* TX Phase interpolator Control 1 Register: 00000000*/ 6078 #define READ_WC40_TX_X1_CONTROL0_TX_PI_CONTROL1r(_unit, _pc, _val) \ 6079 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009200, (_val)) 6080 #define WRITE_WC40_TX_X1_CONTROL0_TX_PI_CONTROL1r(_unit, _pc, _val) \ 6081 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009200, (_val)) 6082 #define MODIFY_WC40_TX_X1_CONTROL0_TX_PI_CONTROL1r(_unit, _pc, _val, _mask) \ 6083 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009200, (_val), (_mask)) 6084 6085 /* TX Phase interpolator Control 2 Register: 00000000*/ 6086 #define READ_WC40_TX_X1_CONTROL0_TX_PI_CONTROL2r(_unit, _pc, _val) \ 6087 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009201, (_val)) 6088 #define WRITE_WC40_TX_X1_CONTROL0_TX_PI_CONTROL2r(_unit, _pc, _val) \ 6089 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009201, (_val)) 6090 #define MODIFY_WC40_TX_X1_CONTROL0_TX_PI_CONTROL2r(_unit, _pc, _val, _mask) \ 6091 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009201, (_val), (_mask)) 6092 6093 /* TX Phase interpolator Control 3 Register: 00000000*/ 6094 #define READ_WC40_TX_X1_CONTROL0_TX_PI_CONTROL3r(_unit, _pc, _val) \ 6095 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009202, (_val)) 6096 #define WRITE_WC40_TX_X1_CONTROL0_TX_PI_CONTROL3r(_unit, _pc, _val) \ 6097 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009202, (_val)) 6098 #define MODIFY_WC40_TX_X1_CONTROL0_TX_PI_CONTROL3r(_unit, _pc, _val, _mask) \ 6099 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009202, (_val), (_mask)) 6100 6101 6102 6103 /**************************************************************************** 6104 * TSC_TX_X1_status0 6105 */ 6106 /* TX Phase interpolator Status 1 Register: 00000000*/ 6107 #define READ_WC40_TX_X1_STATUS0_TX_PI_STATUS1r(_unit, _pc, _val) \ 6108 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009210, (_val)) 6109 #define WRITE_WC40_TX_X1_STATUS0_TX_PI_STATUS1r(_unit, _pc, _val) \ 6110 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009210, (_val)) 6111 #define MODIFY_WC40_TX_X1_STATUS0_TX_PI_STATUS1r(_unit, _pc, _val, _mask) \ 6112 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009210, (_val), (_mask)) 6113 6114 /* TX Phase interpolator Status 2 Register: 00000000*/ 6115 #define READ_WC40_TX_X1_STATUS0_TX_PI_STATUS2r(_unit, _pc, _val) \ 6116 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009211, (_val)) 6117 #define WRITE_WC40_TX_X1_STATUS0_TX_PI_STATUS2r(_unit, _pc, _val) \ 6118 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009211, (_val)) 6119 #define MODIFY_WC40_TX_X1_STATUS0_TX_PI_STATUS2r(_unit, _pc, _val, _mask) \ 6120 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009211, (_val), (_mask)) 6121 6122 /* TLA STATUS REGISTER: 00000000*/ 6123 #define READ_WC40_TX_X1_STATUS0_TLA_STATUSr(_unit, _pc, _val) \ 6124 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009212, (_val)) 6125 #define WRITE_WC40_TX_X1_STATUS0_TLA_STATUSr(_unit, _pc, _val) \ 6126 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009212, (_val)) 6127 #define MODIFY_WC40_TX_X1_STATUS0_TLA_STATUSr(_unit, _pc, _val, _mask) \ 6128 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009212, (_val), (_mask)) 6129 6130 6131 6132 /**************************************************************************** 6133 * TSC_RX_X1_Control0 6134 */ 6135 /* Sync code word statemachine control register: 00000000*/ 6136 #define READ_WC40_RX_X1_CONTROL0_DECODE_CONTROL_0r(_unit, _pc, _val) \ 6137 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009220, (_val)) 6138 #define WRITE_WC40_RX_X1_CONTROL0_DECODE_CONTROL_0r(_unit, _pc, _val) \ 6139 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009220, (_val)) 6140 #define MODIFY_WC40_RX_X1_CONTROL0_DECODE_CONTROL_0r(_unit, _pc, _val, _mask) \ 6141 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009220, (_val), (_mask)) 6142 6143 /* decode_control_1 register: 00000000*/ 6144 #define READ_WC40_RX_X1_CONTROL0_DECODE_CONTROL_1r(_unit, _pc, _val) \ 6145 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009221, (_val)) 6146 #define WRITE_WC40_RX_X1_CONTROL0_DECODE_CONTROL_1r(_unit, _pc, _val) \ 6147 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009221, (_val)) 6148 #define MODIFY_WC40_RX_X1_CONTROL0_DECODE_CONTROL_1r(_unit, _pc, _val, _mask) \ 6149 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009221, (_val), (_mask)) 6150 6151 /* deskew_windows register: 00000000*/ 6152 #define READ_WC40_RX_X1_CONTROL0_DESKEW_WINDOWSr(_unit, _pc, _val) \ 6153 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009222, (_val)) 6154 #define WRITE_WC40_RX_X1_CONTROL0_DESKEW_WINDOWSr(_unit, _pc, _val) \ 6155 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009222, (_val)) 6156 #define MODIFY_WC40_RX_X1_CONTROL0_DESKEW_WINDOWSr(_unit, _pc, _val, _mask) \ 6157 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009222, (_val), (_mask)) 6158 6159 /* CX4 signal detect filter: 00000000*/ 6160 #define READ_WC40_RX_X1_CONTROL0_CX4_SIGDET_FILTERr(_unit, _pc, _val) \ 6161 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009224, (_val)) 6162 #define WRITE_WC40_RX_X1_CONTROL0_CX4_SIGDET_FILTERr(_unit, _pc, _val) \ 6163 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009224, (_val)) 6164 #define MODIFY_WC40_RX_X1_CONTROL0_CX4_SIGDET_FILTERr(_unit, _pc, _val, _mask) \ 6165 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009224, (_val), (_mask)) 6166 6167 6168 6169 /**************************************************************************** 6170 * TSC_RX_X1_Control1 6171 */ 6172 /* CL49 sync header valid/invalid counters: 00000000*/ 6173 #define READ_WC40_RX_X1_CONTROL1_SHCNT_CL49r(_unit, _pc, _val) \ 6174 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009230, (_val)) 6175 #define WRITE_WC40_RX_X1_CONTROL1_SHCNT_CL49r(_unit, _pc, _val) \ 6176 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009230, (_val)) 6177 #define MODIFY_WC40_RX_X1_CONTROL1_SHCNT_CL49r(_unit, _pc, _val, _mask) \ 6178 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009230, (_val), (_mask)) 6179 6180 /* CL49 sync header valid counter: 00000000*/ 6181 #define READ_WC40_RX_X1_CONTROL1_VALID_SHCNT_CL82r(_unit, _pc, _val) \ 6182 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009231, (_val)) 6183 #define WRITE_WC40_RX_X1_CONTROL1_VALID_SHCNT_CL82r(_unit, _pc, _val) \ 6184 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009231, (_val)) 6185 #define MODIFY_WC40_RX_X1_CONTROL1_VALID_SHCNT_CL82r(_unit, _pc, _val, _mask) \ 6186 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009231, (_val), (_mask)) 6187 6188 /* CL49 sync header invalid counter: 00000000*/ 6189 #define READ_WC40_RX_X1_CONTROL1_INVALID_SHCNT_CL82r(_unit, _pc, _val) \ 6190 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009232, (_val)) 6191 #define WRITE_WC40_RX_X1_CONTROL1_INVALID_SHCNT_CL82r(_unit, _pc, _val) \ 6192 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009232, (_val)) 6193 #define MODIFY_WC40_RX_X1_CONTROL1_INVALID_SHCNT_CL82r(_unit, _pc, _val, _mask) \ 6194 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009232, (_val), (_mask)) 6195 6196 /* Sync code word bits 65:50: 00000000*/ 6197 #define READ_WC40_RX_X1_CONTROL1_SCW0r(_unit, _pc, _val) \ 6198 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009233, (_val)) 6199 #define WRITE_WC40_RX_X1_CONTROL1_SCW0r(_unit, _pc, _val) \ 6200 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009233, (_val)) 6201 #define MODIFY_WC40_RX_X1_CONTROL1_SCW0r(_unit, _pc, _val, _mask) \ 6202 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009233, (_val), (_mask)) 6203 6204 /* Sync code word bits 49;34: 00000000*/ 6205 #define READ_WC40_RX_X1_CONTROL1_SCW1r(_unit, _pc, _val) \ 6206 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009234, (_val)) 6207 #define WRITE_WC40_RX_X1_CONTROL1_SCW1r(_unit, _pc, _val) \ 6208 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009234, (_val)) 6209 #define MODIFY_WC40_RX_X1_CONTROL1_SCW1r(_unit, _pc, _val, _mask) \ 6210 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009234, (_val), (_mask)) 6211 6212 /* Sync code word bits 33:18: 00000000*/ 6213 #define READ_WC40_RX_X1_CONTROL1_SCW2r(_unit, _pc, _val) \ 6214 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009235, (_val)) 6215 #define WRITE_WC40_RX_X1_CONTROL1_SCW2r(_unit, _pc, _val) \ 6216 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009235, (_val)) 6217 #define MODIFY_WC40_RX_X1_CONTROL1_SCW2r(_unit, _pc, _val, _mask) \ 6218 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009235, (_val), (_mask)) 6219 6220 /* Sync code word bits 17:2: 00000000*/ 6221 #define READ_WC40_RX_X1_CONTROL1_SCW3r(_unit, _pc, _val) \ 6222 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009236, (_val)) 6223 #define WRITE_WC40_RX_X1_CONTROL1_SCW3r(_unit, _pc, _val) \ 6224 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009236, (_val)) 6225 #define MODIFY_WC40_RX_X1_CONTROL1_SCW3r(_unit, _pc, _val, _mask) \ 6226 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009236, (_val), (_mask)) 6227 6228 /* Sync code word bits 1:0: 00000000*/ 6229 #define READ_WC40_RX_X1_CONTROL1_SCW4r(_unit, _pc, _val) \ 6230 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009237, (_val)) 6231 #define WRITE_WC40_RX_X1_CONTROL1_SCW4r(_unit, _pc, _val) \ 6232 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009237, (_val)) 6233 #define MODIFY_WC40_RX_X1_CONTROL1_SCW4r(_unit, _pc, _val, _mask) \ 6234 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009237, (_val), (_mask)) 6235 6236 /* Sync code word mask bits 65:50: 00000000*/ 6237 #define READ_WC40_RX_X1_CONTROL1_SCW0_MASKr(_unit, _pc, _val) \ 6238 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009238, (_val)) 6239 #define WRITE_WC40_RX_X1_CONTROL1_SCW0_MASKr(_unit, _pc, _val) \ 6240 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009238, (_val)) 6241 #define MODIFY_WC40_RX_X1_CONTROL1_SCW0_MASKr(_unit, _pc, _val, _mask) \ 6242 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009238, (_val), (_mask)) 6243 6244 /* Sync code word mask bits 49:34: 00000000*/ 6245 #define READ_WC40_RX_X1_CONTROL1_SCW1_MASKr(_unit, _pc, _val) \ 6246 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009239, (_val)) 6247 #define WRITE_WC40_RX_X1_CONTROL1_SCW1_MASKr(_unit, _pc, _val) \ 6248 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009239, (_val)) 6249 #define MODIFY_WC40_RX_X1_CONTROL1_SCW1_MASKr(_unit, _pc, _val, _mask) \ 6250 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009239, (_val), (_mask)) 6251 6252 /* Sync code word mask bits 33:18: 00000000*/ 6253 #define READ_WC40_RX_X1_CONTROL1_SCW2_MASKr(_unit, _pc, _val) \ 6254 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000923a, (_val)) 6255 #define WRITE_WC40_RX_X1_CONTROL1_SCW2_MASKr(_unit, _pc, _val) \ 6256 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000923a, (_val)) 6257 #define MODIFY_WC40_RX_X1_CONTROL1_SCW2_MASKr(_unit, _pc, _val, _mask) \ 6258 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000923a, (_val), (_mask)) 6259 6260 /* Sync code word mask bits 17:2: 00000000*/ 6261 #define READ_WC40_RX_X1_CONTROL1_SCW3_MASKr(_unit, _pc, _val) \ 6262 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000923b, (_val)) 6263 #define WRITE_WC40_RX_X1_CONTROL1_SCW3_MASKr(_unit, _pc, _val) \ 6264 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000923b, (_val)) 6265 #define MODIFY_WC40_RX_X1_CONTROL1_SCW3_MASKr(_unit, _pc, _val, _mask) \ 6266 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000923b, (_val), (_mask)) 6267 6268 /* Sync code word mask bits 1:0: 00000000*/ 6269 #define READ_WC40_RX_X1_CONTROL1_SCW4_MASKr(_unit, _pc, _val) \ 6270 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000923c, (_val)) 6271 #define WRITE_WC40_RX_X1_CONTROL1_SCW4_MASKr(_unit, _pc, _val) \ 6272 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000923c, (_val)) 6273 #define MODIFY_WC40_RX_X1_CONTROL1_SCW4_MASKr(_unit, _pc, _val, _mask) \ 6274 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000923c, (_val), (_mask)) 6275 6276 6277 6278 /**************************************************************************** 6279 * TSC_AN_X1_CONTROL 6280 */ 6281 /* OUI UPPER BITS REGISTER: 00000000*/ 6282 #define READ_WC40_AN_X1_CONTROL_OUI_UPPERr(_unit, _pc, _val) \ 6283 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009240, (_val)) 6284 #define WRITE_WC40_AN_X1_CONTROL_OUI_UPPERr(_unit, _pc, _val) \ 6285 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009240, (_val)) 6286 #define MODIFY_WC40_AN_X1_CONTROL_OUI_UPPERr(_unit, _pc, _val, _mask) \ 6287 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009240, (_val), (_mask)) 6288 6289 /* OUI LOWEr BITS REGISTER: 00000000*/ 6290 #define READ_WC40_AN_X1_CONTROL_OUI_LOWERr(_unit, _pc, _val) \ 6291 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009241, (_val)) 6292 #define WRITE_WC40_AN_X1_CONTROL_OUI_LOWERr(_unit, _pc, _val) \ 6293 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009241, (_val)) 6294 #define MODIFY_WC40_AN_X1_CONTROL_OUI_LOWERr(_unit, _pc, _val, _mask) \ 6295 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009241, (_val), (_mask)) 6296 6297 /* REMAP PRIORITY REGISTER: 00000000*/ 6298 #define READ_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_5_0r(_unit, _pc, _val) \ 6299 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009242, (_val)) 6300 #define WRITE_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_5_0r(_unit, _pc, _val) \ 6301 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009242, (_val)) 6302 #define MODIFY_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_5_0r(_unit, _pc, _val, _mask) \ 6303 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009242, (_val), (_mask)) 6304 6305 /* REMAP PRIORITY REGISTER: 00000000*/ 6306 #define READ_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_11_6r(_unit, _pc, _val) \ 6307 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009243, (_val)) 6308 #define WRITE_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_11_6r(_unit, _pc, _val) \ 6309 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009243, (_val)) 6310 #define MODIFY_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_11_6r(_unit, _pc, _val, _mask) \ 6311 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009243, (_val), (_mask)) 6312 6313 /* REMAP PRIORITY REGISTER: 00000000*/ 6314 #define READ_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_17_12r(_unit, _pc, _val) \ 6315 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009244, (_val)) 6316 #define WRITE_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_17_12r(_unit, _pc, _val) \ 6317 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009244, (_val)) 6318 #define MODIFY_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_17_12r(_unit, _pc, _val, _mask) \ 6319 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009244, (_val), (_mask)) 6320 6321 /* REMAP PRIORITY REGISTER: 00000000*/ 6322 #define READ_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_23_18r(_unit, _pc, _val) \ 6323 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009245, (_val)) 6324 #define WRITE_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_23_18r(_unit, _pc, _val) \ 6325 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009245, (_val)) 6326 #define MODIFY_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_23_18r(_unit, _pc, _val, _mask) \ 6327 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009245, (_val), (_mask)) 6328 6329 /* REMAP PRIORITY REGISTER: 00000000*/ 6330 #define READ_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_29_24r(_unit, _pc, _val) \ 6331 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009246, (_val)) 6332 #define WRITE_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_29_24r(_unit, _pc, _val) \ 6333 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009246, (_val)) 6334 #define MODIFY_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_29_24r(_unit, _pc, _val, _mask) \ 6335 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009246, (_val), (_mask)) 6336 6337 /* REMAP PRIORITY REGISTER: 00000000*/ 6338 #define READ_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_35_30r(_unit, _pc, _val) \ 6339 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009247, (_val)) 6340 #define WRITE_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_35_30r(_unit, _pc, _val) \ 6341 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009247, (_val)) 6342 #define MODIFY_WC40_AN_X1_CONTROL_BAM_SPEED_PRI_35_30r(_unit, _pc, _val, _mask) \ 6343 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009247, (_val), (_mask)) 6344 6345 /* REMAP PRIORITY REGISTER: 00000000*/ 6346 #define READ_WC40_AN_X1_CONTROL_CONFIG_CONTROLr(_unit, _pc, _val) \ 6347 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009248, (_val)) 6348 #define WRITE_WC40_AN_X1_CONTROL_CONFIG_CONTROLr(_unit, _pc, _val) \ 6349 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009248, (_val)) 6350 #define MODIFY_WC40_AN_X1_CONTROL_CONFIG_CONTROLr(_unit, _pc, _val, _mask) \ 6351 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009248, (_val), (_mask)) 6352 6353 /* PLL RESET TIMER PERIOD: 00000000*/ 6354 #define READ_WC40_AN_X1_CONTROL_PLL_RESET_TIMERr(_unit, _pc, _val) \ 6355 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009249, (_val)) 6356 #define WRITE_WC40_AN_X1_CONTROL_PLL_RESET_TIMERr(_unit, _pc, _val) \ 6357 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009249, (_val)) 6358 #define MODIFY_WC40_AN_X1_CONTROL_PLL_RESET_TIMERr(_unit, _pc, _val, _mask) \ 6359 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009249, (_val), (_mask)) 6360 6361 6362 6363 /**************************************************************************** 6364 * TSC_AN_X1_TIMERS 6365 */ 6366 /* CL37 AUTO-NEG RESTART TIMER: 00000000*/ 6367 #define READ_WC40_AN_X1_TIMERS_CL37_RESTARTr(_unit, _pc, _val) \ 6368 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009250, (_val)) 6369 #define WRITE_WC40_AN_X1_TIMERS_CL37_RESTARTr(_unit, _pc, _val) \ 6370 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009250, (_val)) 6371 #define MODIFY_WC40_AN_X1_TIMERS_CL37_RESTARTr(_unit, _pc, _val, _mask) \ 6372 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009250, (_val), (_mask)) 6373 6374 /* CL37 AUTO-NEG COMPLETE-ACKNOWLEDGE TIMER: 00000000*/ 6375 #define READ_WC40_AN_X1_TIMERS_CL37_ACKr(_unit, _pc, _val) \ 6376 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009251, (_val)) 6377 #define WRITE_WC40_AN_X1_TIMERS_CL37_ACKr(_unit, _pc, _val) \ 6378 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009251, (_val)) 6379 #define MODIFY_WC40_AN_X1_TIMERS_CL37_ACKr(_unit, _pc, _val, _mask) \ 6380 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009251, (_val), (_mask)) 6381 6382 /* CL37 AUTO-NEG TIMEOUT-ERROR TIMER: 00000000*/ 6383 #define READ_WC40_AN_X1_TIMERS_CL37_ERRORr(_unit, _pc, _val) \ 6384 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009252, (_val)) 6385 #define WRITE_WC40_AN_X1_TIMERS_CL37_ERRORr(_unit, _pc, _val) \ 6386 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009252, (_val)) 6387 #define MODIFY_WC40_AN_X1_TIMERS_CL37_ERRORr(_unit, _pc, _val, _mask) \ 6388 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009252, (_val), (_mask)) 6389 6390 /* CL73 AUTO-NEG BREAK-LINK TIMER: 00000000*/ 6391 #define READ_WC40_AN_X1_TIMERS_CL73_BREAK_LINKr(_unit, _pc, _val) \ 6392 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009253, (_val)) 6393 #define WRITE_WC40_AN_X1_TIMERS_CL73_BREAK_LINKr(_unit, _pc, _val) \ 6394 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009253, (_val)) 6395 #define MODIFY_WC40_AN_X1_TIMERS_CL73_BREAK_LINKr(_unit, _pc, _val, _mask) \ 6396 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009253, (_val), (_mask)) 6397 6398 /* CL73 AUTO-NEG TIMEOUT-ERROR TIMER: 00000000*/ 6399 #define READ_WC40_AN_X1_TIMERS_CL73_ERRORr(_unit, _pc, _val) \ 6400 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009254, (_val)) 6401 #define WRITE_WC40_AN_X1_TIMERS_CL73_ERRORr(_unit, _pc, _val) \ 6402 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009254, (_val)) 6403 #define MODIFY_WC40_AN_X1_TIMERS_CL73_ERRORr(_unit, _pc, _val, _mask) \ 6404 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009254, (_val), (_mask)) 6405 6406 /* CL73 PARALLEL-DETECT DME-CLOCK TIMER: 00000000*/ 6407 #define READ_WC40_AN_X1_TIMERS_CL73_DME_LOCKr(_unit, _pc, _val) \ 6408 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009255, (_val)) 6409 #define WRITE_WC40_AN_X1_TIMERS_CL73_DME_LOCKr(_unit, _pc, _val) \ 6410 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009255, (_val)) 6411 #define MODIFY_WC40_AN_X1_TIMERS_CL73_DME_LOCKr(_unit, _pc, _val, _mask) \ 6412 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009255, (_val), (_mask)) 6413 6414 /* CL73 LINK-UP TIMER: 00000000*/ 6415 #define READ_WC40_AN_X1_TIMERS_LINK_UPr(_unit, _pc, _val) \ 6416 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009256, (_val)) 6417 #define WRITE_WC40_AN_X1_TIMERS_LINK_UPr(_unit, _pc, _val) \ 6418 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009256, (_val)) 6419 #define MODIFY_WC40_AN_X1_TIMERS_LINK_UPr(_unit, _pc, _val, _mask) \ 6420 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009256, (_val), (_mask)) 6421 6422 /* TIMER FOR QUALIFYING A LINK_STATUS: 00000000*/ 6423 #define READ_WC40_AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r(_unit, _pc, _val) \ 6424 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009257, (_val)) 6425 #define WRITE_WC40_AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r(_unit, _pc, _val) \ 6426 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009257, (_val)) 6427 #define MODIFY_WC40_AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r(_unit, _pc, _val, _mask) \ 6428 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009257, (_val), (_mask)) 6429 6430 /* Timer FOR QUALIFYING A LINK_STATUS: 00000000*/ 6431 #define READ_WC40_AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r(_unit, _pc, _val) \ 6432 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009258, (_val)) 6433 #define WRITE_WC40_AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r(_unit, _pc, _val) \ 6434 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009258, (_val)) 6435 #define MODIFY_WC40_AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r(_unit, _pc, _val, _mask) \ 6436 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009258, (_val), (_mask)) 6437 6438 /* PARALLEL-DETECT SIGNAL DETECT TIMER: 00000000*/ 6439 #define READ_WC40_AN_X1_TIMERS_PD_SD_TIMERr(_unit, _pc, _val) \ 6440 TSC_REG_READ((_unit), (_pc), 0x00, 0x00009259, (_val)) 6441 #define WRITE_WC40_AN_X1_TIMERS_PD_SD_TIMERr(_unit, _pc, _val) \ 6442 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x00009259, (_val)) 6443 #define MODIFY_WC40_AN_X1_TIMERS_PD_SD_TIMERr(_unit, _pc, _val, _mask) \ 6444 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x00009259, (_val), (_mask)) 6445 6446 /* MAXIMUM TRAINING TIME: 00000000*/ 6447 #define READ_WC40_AN_X1_TIMERS_CL72_MAX_WAIT_TIMERr(_unit, _pc, _val) \ 6448 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000925a, (_val)) 6449 #define WRITE_WC40_AN_X1_TIMERS_CL72_MAX_WAIT_TIMERr(_unit, _pc, _val) \ 6450 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000925a, (_val)) 6451 #define MODIFY_WC40_AN_X1_TIMERS_CL72_MAX_WAIT_TIMERr(_unit, _pc, _val, _mask) \ 6452 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000925a, (_val), (_mask)) 6453 6454 /* PERIOD TO KEEP TRANSIMING FRAMES: 00000000*/ 6455 #define READ_WC40_AN_X1_TIMERS_CL72_WAIT_TIMERr(_unit, _pc, _val) \ 6456 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000925b, (_val)) 6457 #define WRITE_WC40_AN_X1_TIMERS_CL72_WAIT_TIMERr(_unit, _pc, _val) \ 6458 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000925b, (_val)) 6459 #define MODIFY_WC40_AN_X1_TIMERS_CL72_WAIT_TIMERr(_unit, _pc, _val, _mask) \ 6460 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000925b, (_val), (_mask)) 6461 6462 /* PERIOD TO IGNORE THE LINK: 00000000*/ 6463 #define READ_WC40_AN_X1_TIMERS_IGNORE_LINK_TIMERr(_unit, _pc, _val) \ 6464 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000925c, (_val)) 6465 #define WRITE_WC40_AN_X1_TIMERS_IGNORE_LINK_TIMERr(_unit, _pc, _val) \ 6466 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000925c, (_val)) 6467 #define MODIFY_WC40_AN_X1_TIMERS_IGNORE_LINK_TIMERr(_unit, _pc, _val, _mask) \ 6468 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000925c, (_val), (_mask)) 6469 6470 /* DME PAGE TIMERS: 00000000*/ 6471 #define READ_WC40_AN_X1_TIMERS_DME_PAGE_TIMERr(_unit, _pc, _val) \ 6472 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000925d, (_val)) 6473 #define WRITE_WC40_AN_X1_TIMERS_DME_PAGE_TIMERr(_unit, _pc, _val) \ 6474 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000925d, (_val)) 6475 #define MODIFY_WC40_AN_X1_TIMERS_DME_PAGE_TIMERr(_unit, _pc, _val, _mask) \ 6476 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000925d, (_val), (_mask)) 6477 6478 /* CL73 SGMII TIMER: 00000000*/ 6479 #define READ_WC40_AN_X1_TIMERS_SGMII_CL73_TIMER_TYPEr(_unit, _pc, _val) \ 6480 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000925e, (_val)) 6481 #define WRITE_WC40_AN_X1_TIMERS_SGMII_CL73_TIMER_TYPEr(_unit, _pc, _val) \ 6482 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000925e, (_val)) 6483 #define MODIFY_WC40_AN_X1_TIMERS_SGMII_CL73_TIMER_TYPEr(_unit, _pc, _val, _mask) \ 6484 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000925e, (_val), (_mask)) 6485 6486 6487 6488 /**************************************************************************** 6489 * TSC_WC4_TSC_USER2_TX_X2_Control0 6490 */ 6491 /* Swap Count register: 00000000*/ 6492 #define READ_WC40_TX_X2_CONTROL0_MLD_SWAP_COUNTr(_unit, _pc, _val) \ 6493 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a000, (_val)) 6494 #define WRITE_WC40_TX_X2_CONTROL0_MLD_SWAP_COUNTr(_unit, _pc, _val) \ 6495 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a000, (_val)) 6496 #define MODIFY_WC40_TX_X2_CONTROL0_MLD_SWAP_COUNTr(_unit, _pc, _val, _mask) \ 6497 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a000, (_val), (_mask)) 6498 6499 /* CL48 register: 00000000*/ 6500 #define READ_WC40_TX_X2_CONTROL0_CL48_0r(_unit, _pc, _val) \ 6501 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a001, (_val)) 6502 #define WRITE_WC40_TX_X2_CONTROL0_CL48_0r(_unit, _pc, _val) \ 6503 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a001, (_val)) 6504 #define MODIFY_WC40_TX_X2_CONTROL0_CL48_0r(_unit, _pc, _val, _mask) \ 6505 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a001, (_val), (_mask)) 6506 6507 /* CL82 register: 00000000*/ 6508 #define READ_WC40_TX_X2_CONTROL0_CL82_0r(_unit, _pc, _val) \ 6509 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a002, (_val)) 6510 #define WRITE_WC40_TX_X2_CONTROL0_CL82_0r(_unit, _pc, _val) \ 6511 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a002, (_val)) 6512 #define MODIFY_WC40_TX_X2_CONTROL0_CL82_0r(_unit, _pc, _val, _mask) \ 6513 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a002, (_val), (_mask)) 6514 6515 /* BROADCOM 64/66 ACOL INSERTION COUNT: 00000000*/ 6516 #define READ_WC40_TX_X2_CONTROL0_BRCM_MODEr(_unit, _pc, _val) \ 6517 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a003, (_val)) 6518 #define WRITE_WC40_TX_X2_CONTROL0_BRCM_MODEr(_unit, _pc, _val) \ 6519 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a003, (_val)) 6520 #define MODIFY_WC40_TX_X2_CONTROL0_BRCM_MODEr(_unit, _pc, _val, _mask) \ 6521 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a003, (_val), (_mask)) 6522 6523 6524 6525 /**************************************************************************** 6526 * TSC_WC4_TSC_USER2_TX_X2_Status0 6527 */ 6528 /* CL82 Status 0 register: 00000000*/ 6529 #define READ_WC40_TX_X2_STATUS0_CL82_TX_STATUS_0r(_unit, _pc, _val) \ 6530 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a011, (_val)) 6531 #define WRITE_WC40_TX_X2_STATUS0_CL82_TX_STATUS_0r(_unit, _pc, _val) \ 6532 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a011, (_val)) 6533 #define MODIFY_WC40_TX_X2_STATUS0_CL82_TX_STATUS_0r(_unit, _pc, _val, _mask) \ 6534 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a011, (_val), (_mask)) 6535 6536 6537 6538 /**************************************************************************** 6539 * TSC_WC4_TSC_USER2_RX_X2_Control0 6540 */ 6541 /* qrsvd 0 register: 00000000*/ 6542 #define READ_WC40_RX_X2_CONTROL0_QRSVD_0r(_unit, _pc, _val) \ 6543 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a020, (_val)) 6544 #define WRITE_WC40_RX_X2_CONTROL0_QRSVD_0r(_unit, _pc, _val) \ 6545 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a020, (_val)) 6546 #define MODIFY_WC40_RX_X2_CONTROL0_QRSVD_0r(_unit, _pc, _val, _mask) \ 6547 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a020, (_val), (_mask)) 6548 6549 /* qrsvd 1 register: 00000000*/ 6550 #define READ_WC40_RX_X2_CONTROL0_QRSVD_1r(_unit, _pc, _val) \ 6551 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a021, (_val)) 6552 #define WRITE_WC40_RX_X2_CONTROL0_QRSVD_1r(_unit, _pc, _val) \ 6553 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a021, (_val)) 6554 #define MODIFY_WC40_RX_X2_CONTROL0_QRSVD_1r(_unit, _pc, _val, _mask) \ 6555 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a021, (_val), (_mask)) 6556 6557 /* qrsvd 2 register: 00000000*/ 6558 #define READ_WC40_RX_X2_CONTROL0_QRSVD_2r(_unit, _pc, _val) \ 6559 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a022, (_val)) 6560 #define WRITE_WC40_RX_X2_CONTROL0_QRSVD_2r(_unit, _pc, _val) \ 6561 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a022, (_val)) 6562 #define MODIFY_WC40_RX_X2_CONTROL0_QRSVD_2r(_unit, _pc, _val, _mask) \ 6563 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a022, (_val), (_mask)) 6564 6565 /* misc 0 register: 00000000*/ 6566 #define READ_WC40_RX_X2_CONTROL0_MISC_0r(_unit, _pc, _val) \ 6567 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a023, (_val)) 6568 #define WRITE_WC40_RX_X2_CONTROL0_MISC_0r(_unit, _pc, _val) \ 6569 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a023, (_val)) 6570 #define MODIFY_WC40_RX_X2_CONTROL0_MISC_0r(_unit, _pc, _val, _mask) \ 6571 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a023, (_val), (_mask)) 6572 6573 /* misc 1 register: 00000000*/ 6574 #define READ_WC40_RX_X2_CONTROL0_MISC_1r(_unit, _pc, _val) \ 6575 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a024, (_val)) 6576 #define WRITE_WC40_RX_X2_CONTROL0_MISC_1r(_unit, _pc, _val) \ 6577 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a024, (_val)) 6578 #define MODIFY_WC40_RX_X2_CONTROL0_MISC_1r(_unit, _pc, _val, _mask) \ 6579 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a024, (_val), (_mask)) 6580 6581 6582 6583 /**************************************************************************** 6584 * TSC_WC4_TSC_USER2_RX_X2_Status0 6585 */ 6586 /* skew_status_0 register: 00000000*/ 6587 #define READ_WC40_RX_X2_STATUS0_SKEW_STATUS_0r(_unit, _pc, _val) \ 6588 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a031, (_val)) 6589 #define WRITE_WC40_RX_X2_STATUS0_SKEW_STATUS_0r(_unit, _pc, _val) \ 6590 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a031, (_val)) 6591 #define MODIFY_WC40_RX_X2_STATUS0_SKEW_STATUS_0r(_unit, _pc, _val, _mask) \ 6592 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a031, (_val), (_mask)) 6593 6594 /* skew_status_1 register: 00000000*/ 6595 #define READ_WC40_RX_X2_STATUS0_SKEW_STATUS_1r(_unit, _pc, _val) \ 6596 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a032, (_val)) 6597 #define WRITE_WC40_RX_X2_STATUS0_SKEW_STATUS_1r(_unit, _pc, _val) \ 6598 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a032, (_val)) 6599 #define MODIFY_WC40_RX_X2_STATUS0_SKEW_STATUS_1r(_unit, _pc, _val, _mask) \ 6600 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a032, (_val), (_mask)) 6601 6602 6603 6604 /**************************************************************************** 6605 * TSC_WC4_TSC_USER2_CL82 6606 */ 6607 /* cl82 rx decoder status register: 00000000*/ 6608 #define READ_WC40_CL82_RX_DECODER_STATUSr(_unit, _pc, _val) \ 6609 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a080, (_val)) 6610 #define WRITE_WC40_CL82_RX_DECODER_STATUSr(_unit, _pc, _val) \ 6611 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a080, (_val)) 6612 #define MODIFY_WC40_CL82_RX_DECODER_STATUSr(_unit, _pc, _val, _mask) \ 6613 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a080, (_val), (_mask)) 6614 6615 /* cl82 rx deskew status register: 00000000*/ 6616 #define READ_WC40_CL82_RX_DESKEW_BER_STATUSr(_unit, _pc, _val) \ 6617 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a081, (_val)) 6618 #define WRITE_WC40_CL82_RX_DESKEW_BER_STATUSr(_unit, _pc, _val) \ 6619 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a081, (_val)) 6620 #define MODIFY_WC40_CL82_RX_DESKEW_BER_STATUSr(_unit, _pc, _val, _mask) \ 6621 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a081, (_val), (_mask)) 6622 6623 /* CL82 BER HIGH ORDER bits register: 00000000*/ 6624 #define READ_WC40_CL82_CL82_BER_HOr(_unit, _pc, _val) \ 6625 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000a085, (_val)) 6626 #define WRITE_WC40_CL82_CL82_BER_HOr(_unit, _pc, _val) \ 6627 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000a085, (_val)) 6628 #define MODIFY_WC40_CL82_CL82_BER_HOr(_unit, _pc, _val, _mask) \ 6629 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000a085, (_val), (_mask)) 6630 6631 6632 6633 /**************************************************************************** 6634 * TSC_WC4_TSC_USER4_anaTx 6635 */ 6636 /* Tx analog status 0 register: 00000000*/ 6637 #define READ_WC40_ANATX_ASTATUS0r(_unit, _pc, _val) \ 6638 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c010, (_val)) 6639 #define WRITE_WC40_ANATX_ASTATUS0r(_unit, _pc, _val) \ 6640 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c010, (_val)) 6641 #define MODIFY_WC40_ANATX_ASTATUS0r(_unit, _pc, _val, _mask) \ 6642 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c010, (_val), (_mask)) 6643 6644 /* Tx analog control 0 register: 00000000*/ 6645 #define READ_WC40_ANATX_ACONTROL0r(_unit, _pc, _val) \ 6646 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c011, (_val)) 6647 #define WRITE_WC40_ANATX_ACONTROL0r(_unit, _pc, _val) \ 6648 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c011, (_val)) 6649 #define MODIFY_WC40_ANATX_ACONTROL0r(_unit, _pc, _val, _mask) \ 6650 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c011, (_val), (_mask)) 6651 6652 /* Tx analog status 1 register (AFE tx_sts[15:0]): 00000000*/ 6653 #define READ_WC40_ANATX_ASTATUS1r(_unit, _pc, _val) \ 6654 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c014, (_val)) 6655 #define WRITE_WC40_ANATX_ASTATUS1r(_unit, _pc, _val) \ 6656 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c014, (_val)) 6657 #define MODIFY_WC40_ANATX_ASTATUS1r(_unit, _pc, _val, _mask) \ 6658 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c014, (_val), (_mask)) 6659 6660 /* Tx reserved analog control register (AFE tx_ctrl[15:00], not applicable to XFICore): 00000000*/ 6661 #define READ_WC40_ANATX_TXACONTROL1r(_unit, _pc, _val) \ 6662 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c015, (_val)) 6663 #define WRITE_WC40_ANATX_TXACONTROL1r(_unit, _pc, _val) \ 6664 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c015, (_val)) 6665 #define MODIFY_WC40_ANATX_TXACONTROL1r(_unit, _pc, _val, _mask) \ 6666 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c015, (_val), (_mask)) 6667 6668 /* Tx reserved analog control register (AFE tx_ctrl[31:16], not applicable to XFICore): 00000000*/ 6669 #define READ_WC40_ANATX_TXACONTROL2r(_unit, _pc, _val) \ 6670 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c016, (_val)) 6671 #define WRITE_WC40_ANATX_TXACONTROL2r(_unit, _pc, _val) \ 6672 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c016, (_val)) 6673 #define MODIFY_WC40_ANATX_TXACONTROL2r(_unit, _pc, _val, _mask) \ 6674 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c016, (_val), (_mask)) 6675 6676 /* Tx reserved analog control register (AFE tx_ctrl[47:32], not applicable to XFICore): 00000000*/ 6677 #define READ_WC40_ANATX_TX_DRIVERr(_unit, _pc, _val) \ 6678 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c017, (_val)) 6679 #define WRITE_WC40_ANATX_TX_DRIVERr(_unit, _pc, _val) \ 6680 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c017, (_val)) 6681 #define MODIFY_WC40_ANATX_TX_DRIVERr(_unit, _pc, _val, _mask) \ 6682 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c017, (_val), (_mask)) 6683 6684 /* Tx analog control 5 register: 00000000*/ 6685 #define READ_WC40_ANATX_ACONTROL5r(_unit, _pc, _val) \ 6686 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c019, (_val)) 6687 #define WRITE_WC40_ANATX_ACONTROL5r(_unit, _pc, _val) \ 6688 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c019, (_val)) 6689 #define MODIFY_WC40_ANATX_ACONTROL5r(_unit, _pc, _val, _mask) \ 6690 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c019, (_val), (_mask)) 6691 6692 /* Tx analog control 6 register: 00000000*/ 6693 #define READ_WC40_ANATX_ACONTROL6r(_unit, _pc, _val) \ 6694 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c01a, (_val)) 6695 #define WRITE_WC40_ANATX_ACONTROL6r(_unit, _pc, _val) \ 6696 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c01a, (_val)) 6697 #define MODIFY_WC40_ANATX_ACONTROL6r(_unit, _pc, _val, _mask) \ 6698 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c01a, (_val), (_mask)) 6699 6700 6701 6702 /**************************************************************************** 6703 * TSC_WC4_TSC_USER4_anaRx 6704 */ 6705 /* Rx lane control register: 00000000*/ 6706 #define READ_WC40_ANARX_ACONTROL0r(_unit, _pc, _val) \ 6707 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c021, (_val)) 6708 #define WRITE_WC40_ANARX_ACONTROL0r(_unit, _pc, _val) \ 6709 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c021, (_val)) 6710 #define MODIFY_WC40_ANARX_ACONTROL0r(_unit, _pc, _val, _mask) \ 6711 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c021, (_val), (_mask)) 6712 6713 /* Rx analog status register (AFE rx_sts[15:0]): 00000000*/ 6714 #define READ_WC40_ANARX_ASTATUS1r(_unit, _pc, _val) \ 6715 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c02b, (_val)) 6716 #define WRITE_WC40_ANARX_ASTATUS1r(_unit, _pc, _val) \ 6717 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c02b, (_val)) 6718 #define MODIFY_WC40_ANARX_ASTATUS1r(_unit, _pc, _val, _mask) \ 6719 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c02b, (_val), (_mask)) 6720 6721 /* Rx reserved analog control register (AFE rx_ctrl[15:00], not applicable to XFICore): 00000000*/ 6722 #define READ_WC40_ANARX_RXACONTROL1r(_unit, _pc, _val) \ 6723 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c02c, (_val)) 6724 #define WRITE_WC40_ANARX_RXACONTROL1r(_unit, _pc, _val) \ 6725 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c02c, (_val)) 6726 #define MODIFY_WC40_ANARX_RXACONTROL1r(_unit, _pc, _val, _mask) \ 6727 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c02c, (_val), (_mask)) 6728 6729 /* Rx reserved analog control register (AFE rx_ctrl[31:16], not applicable to XFICore): 00000000*/ 6730 #define READ_WC40_ANARX_RXACONTROL2r(_unit, _pc, _val) \ 6731 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c02d, (_val)) 6732 #define WRITE_WC40_ANARX_RXACONTROL2r(_unit, _pc, _val) \ 6733 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c02d, (_val)) 6734 #define MODIFY_WC40_ANARX_RXACONTROL2r(_unit, _pc, _val, _mask) \ 6735 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c02d, (_val), (_mask)) 6736 6737 /* Rx reserved analog control register (AFE rx_ctrl[47:32], not applicable to XFICore): 00000000*/ 6738 #define READ_WC40_ANARX_RXACONTROL3r(_unit, _pc, _val) \ 6739 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c02e, (_val)) 6740 #define WRITE_WC40_ANARX_RXACONTROL3r(_unit, _pc, _val) \ 6741 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c02e, (_val)) 6742 #define MODIFY_WC40_ANARX_RXACONTROL3r(_unit, _pc, _val, _mask) \ 6743 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c02e, (_val), (_mask)) 6744 6745 6746 6747 /**************************************************************************** 6748 * TSC_WC4_TSC_USER4_PatGen0 6749 */ 6750 /* Pattern Generator Control: 00000000*/ 6751 #define READ_WC40_PATGEN0_PATGENCTRLr(_unit, _pc, _val) \ 6752 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c030, (_val)) 6753 #define WRITE_WC40_PATGEN0_PATGENCTRLr(_unit, _pc, _val) \ 6754 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c030, (_val)) 6755 #define MODIFY_WC40_PATGEN0_PATGENCTRLr(_unit, _pc, _val, _mask) \ 6756 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c030, (_val), (_mask)) 6757 6758 /* PRBS Control: 00000000*/ 6759 #define READ_WC40_PATGEN0_PRBSCTRLr(_unit, _pc, _val) \ 6760 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c031, (_val)) 6761 #define WRITE_WC40_PATGEN0_PRBSCTRLr(_unit, _pc, _val) \ 6762 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c031, (_val)) 6763 #define MODIFY_WC40_PATGEN0_PRBSCTRLr(_unit, _pc, _val, _mask) \ 6764 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c031, (_val), (_mask)) 6765 6766 /* PRBS Status: 00000000*/ 6767 #define READ_WC40_PATGEN0_PRBSSTAT0r(_unit, _pc, _val) \ 6768 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c032, (_val)) 6769 #define WRITE_WC40_PATGEN0_PRBSSTAT0r(_unit, _pc, _val) \ 6770 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c032, (_val)) 6771 #define MODIFY_WC40_PATGEN0_PRBSSTAT0r(_unit, _pc, _val, _mask) \ 6772 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c032, (_val), (_mask)) 6773 6774 /* PRBS Status: 00000000*/ 6775 #define READ_WC40_PATGEN0_PRBSSTAT1r(_unit, _pc, _val) \ 6776 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c033, (_val)) 6777 #define WRITE_WC40_PATGEN0_PRBSSTAT1r(_unit, _pc, _val) \ 6778 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c033, (_val)) 6779 #define MODIFY_WC40_PATGEN0_PRBSSTAT1r(_unit, _pc, _val, _mask) \ 6780 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c033, (_val), (_mask)) 6781 6782 /* MISCELLANEOUS TEST Status: 00000000*/ 6783 #define READ_WC40_PATGEN0_TESTMISCSTATUSr(_unit, _pc, _val) \ 6784 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c034, (_val)) 6785 #define WRITE_WC40_PATGEN0_TESTMISCSTATUSr(_unit, _pc, _val) \ 6786 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c034, (_val)) 6787 #define MODIFY_WC40_PATGEN0_TESTMISCSTATUSr(_unit, _pc, _val, _mask) \ 6788 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c034, (_val), (_mask)) 6789 6790 6791 6792 /**************************************************************************** 6793 * TSC_WC4_TSC_USER4_PatGen1 6794 */ 6795 /* TX Packet Count Upper Register: 00000000*/ 6796 #define READ_WC40_PATGEN1_TXPKTCNT_Ur(_unit, _pc, _val) \ 6797 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c040, (_val)) 6798 #define WRITE_WC40_PATGEN1_TXPKTCNT_Ur(_unit, _pc, _val) \ 6799 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c040, (_val)) 6800 #define MODIFY_WC40_PATGEN1_TXPKTCNT_Ur(_unit, _pc, _val, _mask) \ 6801 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c040, (_val), (_mask)) 6802 6803 /* TX Packet Count Lower Register: 00000000*/ 6804 #define READ_WC40_PATGEN1_TXPKTCNT_Lr(_unit, _pc, _val) \ 6805 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c041, (_val)) 6806 #define WRITE_WC40_PATGEN1_TXPKTCNT_Lr(_unit, _pc, _val) \ 6807 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c041, (_val)) 6808 #define MODIFY_WC40_PATGEN1_TXPKTCNT_Lr(_unit, _pc, _val, _mask) \ 6809 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c041, (_val), (_mask)) 6810 6811 /* RX Packet Count Upper Register: 00000000*/ 6812 #define READ_WC40_PATGEN1_RXPKTCNT_Ur(_unit, _pc, _val) \ 6813 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c042, (_val)) 6814 #define WRITE_WC40_PATGEN1_RXPKTCNT_Ur(_unit, _pc, _val) \ 6815 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c042, (_val)) 6816 #define MODIFY_WC40_PATGEN1_RXPKTCNT_Ur(_unit, _pc, _val, _mask) \ 6817 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c042, (_val), (_mask)) 6818 6819 /* RX Packet Count Lower Register: 00000000*/ 6820 #define READ_WC40_PATGEN1_RXPKTCNT_Lr(_unit, _pc, _val) \ 6821 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c043, (_val)) 6822 #define WRITE_WC40_PATGEN1_RXPKTCNT_Lr(_unit, _pc, _val) \ 6823 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c043, (_val)) 6824 #define MODIFY_WC40_PATGEN1_RXPKTCNT_Lr(_unit, _pc, _val, _mask) \ 6825 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c043, (_val), (_mask)) 6826 6827 6828 6829 /**************************************************************************** 6830 * TSC_WC4_TSC_USER4_TX_X4_Credit0 6831 */ 6832 /* clock count 0 register: 00000000*/ 6833 #define READ_WC40_TX_X4_CREDIT0_CREDIT0r(_unit, _pc, _val) \ 6834 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c100, (_val)) 6835 #define WRITE_WC40_TX_X4_CREDIT0_CREDIT0r(_unit, _pc, _val) \ 6836 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c100, (_val)) 6837 #define MODIFY_WC40_TX_X4_CREDIT0_CREDIT0r(_unit, _pc, _val, _mask) \ 6838 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c100, (_val), (_mask)) 6839 6840 /* clock count 1 register: 00000000*/ 6841 #define READ_WC40_TX_X4_CREDIT0_CREDIT1r(_unit, _pc, _val) \ 6842 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c101, (_val)) 6843 #define WRITE_WC40_TX_X4_CREDIT0_CREDIT1r(_unit, _pc, _val) \ 6844 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c101, (_val)) 6845 #define MODIFY_WC40_TX_X4_CREDIT0_CREDIT1r(_unit, _pc, _val, _mask) \ 6846 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c101, (_val), (_mask)) 6847 6848 /* loop count 1_0 register: 00000000*/ 6849 #define READ_WC40_TX_X4_CREDIT0_LOOPCNTr(_unit, _pc, _val) \ 6850 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c102, (_val)) 6851 #define WRITE_WC40_TX_X4_CREDIT0_LOOPCNTr(_unit, _pc, _val) \ 6852 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c102, (_val)) 6853 #define MODIFY_WC40_TX_X4_CREDIT0_LOOPCNTr(_unit, _pc, _val, _mask) \ 6854 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c102, (_val), (_mask)) 6855 6856 /* credit gen count register: 00000000*/ 6857 #define READ_WC40_TX_X4_CREDIT0_MAC_CREDITGENCNTr(_unit, _pc, _val) \ 6858 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c103, (_val)) 6859 #define WRITE_WC40_TX_X4_CREDIT0_MAC_CREDITGENCNTr(_unit, _pc, _val) \ 6860 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c103, (_val)) 6861 #define MODIFY_WC40_TX_X4_CREDIT0_MAC_CREDITGENCNTr(_unit, _pc, _val, _mask) \ 6862 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c103, (_val), (_mask)) 6863 6864 /* pcs clock count 0 register: 00000000*/ 6865 #define READ_WC40_TX_X4_CREDIT0_PCS_CLOCKCNT0r(_unit, _pc, _val) \ 6866 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c104, (_val)) 6867 #define WRITE_WC40_TX_X4_CREDIT0_PCS_CLOCKCNT0r(_unit, _pc, _val) \ 6868 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c104, (_val)) 6869 #define MODIFY_WC40_TX_X4_CREDIT0_PCS_CLOCKCNT0r(_unit, _pc, _val, _mask) \ 6870 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c104, (_val), (_mask)) 6871 6872 /* pcs credit gen count register: 00000000*/ 6873 #define READ_WC40_TX_X4_CREDIT0_PCS_CREDITGENCNTr(_unit, _pc, _val) \ 6874 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c105, (_val)) 6875 #define WRITE_WC40_TX_X4_CREDIT0_PCS_CREDITGENCNTr(_unit, _pc, _val) \ 6876 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c105, (_val)) 6877 #define MODIFY_WC40_TX_X4_CREDIT0_PCS_CREDITGENCNTr(_unit, _pc, _val, _mask) \ 6878 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c105, (_val), (_mask)) 6879 6880 6881 6882 /**************************************************************************** 6883 * TSC_WC4_TSC_USER4_TX_X4_Control0 6884 */ 6885 /* CL72 KR Default Control Register: 00000000*/ 6886 #define READ_WC40_TX_X4_CONTROL0_KR_DEFAULT_CONTROLr(_unit, _pc, _val) \ 6887 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c110, (_val)) 6888 #define WRITE_WC40_TX_X4_CONTROL0_KR_DEFAULT_CONTROLr(_unit, _pc, _val) \ 6889 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c110, (_val)) 6890 #define MODIFY_WC40_TX_X4_CONTROL0_KR_DEFAULT_CONTROLr(_unit, _pc, _val, _mask) \ 6891 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c110, (_val), (_mask)) 6892 6893 /* Encode 0 register: 00000000*/ 6894 #define READ_WC40_TX_X4_CONTROL0_ENCODE_0r(_unit, _pc, _val) \ 6895 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c111, (_val)) 6896 #define WRITE_WC40_TX_X4_CONTROL0_ENCODE_0r(_unit, _pc, _val) \ 6897 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c111, (_val)) 6898 #define MODIFY_WC40_TX_X4_CONTROL0_ENCODE_0r(_unit, _pc, _val, _mask) \ 6899 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c111, (_val), (_mask)) 6900 6901 /* Encode 1 register 64/66 Encoder Programmable Table Lookup Control Character: 00000000*/ 6902 #define READ_WC40_TX_X4_CONTROL0_ENCODE_1r(_unit, _pc, _val) \ 6903 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c112, (_val)) 6904 #define WRITE_WC40_TX_X4_CONTROL0_ENCODE_1r(_unit, _pc, _val) \ 6905 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c112, (_val)) 6906 #define MODIFY_WC40_TX_X4_CONTROL0_ENCODE_1r(_unit, _pc, _val, _mask) \ 6907 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c112, (_val), (_mask)) 6908 6909 /* Misc register: 00000000*/ 6910 #define READ_WC40_TX_X4_CONTROL0_MISCr(_unit, _pc, _val) \ 6911 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c113, (_val)) 6912 #define WRITE_WC40_TX_X4_CONTROL0_MISCr(_unit, _pc, _val) \ 6913 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c113, (_val)) 6914 #define MODIFY_WC40_TX_X4_CONTROL0_MISCr(_unit, _pc, _val, _mask) \ 6915 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c113, (_val), (_mask)) 6916 6917 /* cl36 tx 0 register: 00000000*/ 6918 #define READ_WC40_TX_X4_CONTROL0_CL36_TX_0r(_unit, _pc, _val) \ 6919 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c114, (_val)) 6920 #define WRITE_WC40_TX_X4_CONTROL0_CL36_TX_0r(_unit, _pc, _val) \ 6921 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c114, (_val)) 6922 #define MODIFY_WC40_TX_X4_CONTROL0_CL36_TX_0r(_unit, _pc, _val, _mask) \ 6923 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c114, (_val), (_mask)) 6924 6925 6926 6927 /**************************************************************************** 6928 * TSC_WC4_TSC_USER4_TX_X4_Status0 6929 */ 6930 /* Encode Status 0 register: 00000000*/ 6931 #define READ_WC40_TX_X4_STATUS0_ENCODE_STATUS_0r(_unit, _pc, _val) \ 6932 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c120, (_val)) 6933 #define WRITE_WC40_TX_X4_STATUS0_ENCODE_STATUS_0r(_unit, _pc, _val) \ 6934 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c120, (_val)) 6935 #define MODIFY_WC40_TX_X4_STATUS0_ENCODE_STATUS_0r(_unit, _pc, _val, _mask) \ 6936 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c120, (_val), (_mask)) 6937 6938 /* "Status of PCS Information": 00000000*/ 6939 #define READ_WC40_TX_X4_STATUS0_PCS_STATUSr(_unit, _pc, _val) \ 6940 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c121, (_val)) 6941 #define WRITE_WC40_TX_X4_STATUS0_PCS_STATUSr(_unit, _pc, _val) \ 6942 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c121, (_val)) 6943 #define MODIFY_WC40_TX_X4_STATUS0_PCS_STATUSr(_unit, _pc, _val, _mask) \ 6944 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c121, (_val), (_mask)) 6945 6946 6947 6948 /**************************************************************************** 6949 * TSC_WC4_TSC_USER4_RX_X4_Control0 6950 */ 6951 /* pcs control 0 register: 00000000*/ 6952 #define READ_WC40_RX_X4_CONTROL0_PCS_CONTROL_0r(_unit, _pc, _val) \ 6953 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c130, (_val)) 6954 #define WRITE_WC40_RX_X4_CONTROL0_PCS_CONTROL_0r(_unit, _pc, _val) \ 6955 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c130, (_val)) 6956 #define MODIFY_WC40_RX_X4_CONTROL0_PCS_CONTROL_0r(_unit, _pc, _val, _mask) \ 6957 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c130, (_val), (_mask)) 6958 6959 /* User FEC Control 0 register: 00000000*/ 6960 #define READ_WC40_RX_X4_CONTROL0_FEC_0r(_unit, _pc, _val) \ 6961 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c131, (_val)) 6962 #define WRITE_WC40_RX_X4_CONTROL0_FEC_0r(_unit, _pc, _val) \ 6963 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c131, (_val)) 6964 #define MODIFY_WC40_RX_X4_CONTROL0_FEC_0r(_unit, _pc, _val, _mask) \ 6965 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c131, (_val), (_mask)) 6966 6967 /* User FEC Control 1 register: 00000000*/ 6968 #define READ_WC40_RX_X4_CONTROL0_FEC_1r(_unit, _pc, _val) \ 6969 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c132, (_val)) 6970 #define WRITE_WC40_RX_X4_CONTROL0_FEC_1r(_unit, _pc, _val) \ 6971 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c132, (_val)) 6972 #define MODIFY_WC40_RX_X4_CONTROL0_FEC_1r(_unit, _pc, _val, _mask) \ 6973 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c132, (_val), (_mask)) 6974 6975 /* User FEC Control 2 register: 00000000*/ 6976 #define READ_WC40_RX_X4_CONTROL0_FEC_2r(_unit, _pc, _val) \ 6977 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c133, (_val)) 6978 #define WRITE_WC40_RX_X4_CONTROL0_FEC_2r(_unit, _pc, _val) \ 6979 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c133, (_val)) 6980 #define MODIFY_WC40_RX_X4_CONTROL0_FEC_2r(_unit, _pc, _val, _mask) \ 6981 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c133, (_val), (_mask)) 6982 6983 /* Decoder control 0 register: 00000000*/ 6984 #define READ_WC40_RX_X4_CONTROL0_DECODE_CONTROL_0r(_unit, _pc, _val) \ 6985 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c134, (_val)) 6986 #define WRITE_WC40_RX_X4_CONTROL0_DECODE_CONTROL_0r(_unit, _pc, _val) \ 6987 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c134, (_val)) 6988 #define MODIFY_WC40_RX_X4_CONTROL0_DECODE_CONTROL_0r(_unit, _pc, _val, _mask) \ 6989 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c134, (_val), (_mask)) 6990 6991 /* Decoder control 1 register: 00000000*/ 6992 #define READ_WC40_RX_X4_CONTROL0_DECODE_CONTROL_1r(_unit, _pc, _val) \ 6993 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c135, (_val)) 6994 #define WRITE_WC40_RX_X4_CONTROL0_DECODE_CONTROL_1r(_unit, _pc, _val) \ 6995 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c135, (_val)) 6996 #define MODIFY_WC40_RX_X4_CONTROL0_DECODE_CONTROL_1r(_unit, _pc, _val, _mask) \ 6997 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c135, (_val), (_mask)) 6998 6999 /* cl36_rx_0 register: 00000000*/ 7000 #define READ_WC40_RX_X4_CONTROL0_CL36_RX_0r(_unit, _pc, _val) \ 7001 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c136, (_val)) 7002 #define WRITE_WC40_RX_X4_CONTROL0_CL36_RX_0r(_unit, _pc, _val) \ 7003 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c136, (_val)) 7004 #define MODIFY_WC40_RX_X4_CONTROL0_CL36_RX_0r(_unit, _pc, _val, _mask) \ 7005 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c136, (_val), (_mask)) 7006 7007 /* pma_control_0 register: 00000000*/ 7008 #define READ_WC40_RX_X4_CONTROL0_PMA_CONTROL_0r(_unit, _pc, _val) \ 7009 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c137, (_val)) 7010 #define WRITE_WC40_RX_X4_CONTROL0_PMA_CONTROL_0r(_unit, _pc, _val) \ 7011 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c137, (_val)) 7012 #define MODIFY_WC40_RX_X4_CONTROL0_PMA_CONTROL_0r(_unit, _pc, _val, _mask) \ 7013 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c137, (_val), (_mask)) 7014 7015 /* Rx Sigdet Control: 00000000*/ 7016 #define READ_WC40_RX_X4_CONTROL0_RX_SIGDETr(_unit, _pc, _val) \ 7017 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c138, (_val)) 7018 #define WRITE_WC40_RX_X4_CONTROL0_RX_SIGDETr(_unit, _pc, _val) \ 7019 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c138, (_val)) 7020 #define MODIFY_WC40_RX_X4_CONTROL0_RX_SIGDETr(_unit, _pc, _val, _mask) \ 7021 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c138, (_val), (_mask)) 7022 7023 /* Link status control: 00000000*/ 7024 #define READ_WC40_RX_X4_CONTROL0_LINK_CONTROLr(_unit, _pc, _val) \ 7025 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c139, (_val)) 7026 #define WRITE_WC40_RX_X4_CONTROL0_LINK_CONTROLr(_unit, _pc, _val) \ 7027 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c139, (_val)) 7028 #define MODIFY_WC40_RX_X4_CONTROL0_LINK_CONTROLr(_unit, _pc, _val, _mask) \ 7029 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c139, (_val), (_mask)) 7030 7031 7032 7033 /**************************************************************************** 7034 * TSC_WC4_TSC_USER4_RX_X4_Status0 7035 */ 7036 /* "User FEC debug read data [15:0]": 00000000*/ 7037 #define READ_WC40_RX_X4_STATUS0_FEC_DBG_ERRLr(_unit, _pc, _val) \ 7038 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c140, (_val)) 7039 #define WRITE_WC40_RX_X4_STATUS0_FEC_DBG_ERRLr(_unit, _pc, _val) \ 7040 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c140, (_val)) 7041 #define MODIFY_WC40_RX_X4_STATUS0_FEC_DBG_ERRLr(_unit, _pc, _val, _mask) \ 7042 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c140, (_val), (_mask)) 7043 7044 /* "User FEC debug read data [31:16]": 00000000*/ 7045 #define READ_WC40_RX_X4_STATUS0_FEC_DBG_ERRAHr(_unit, _pc, _val) \ 7046 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c141, (_val)) 7047 #define WRITE_WC40_RX_X4_STATUS0_FEC_DBG_ERRAHr(_unit, _pc, _val) \ 7048 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c141, (_val)) 7049 #define MODIFY_WC40_RX_X4_STATUS0_FEC_DBG_ERRAHr(_unit, _pc, _val, _mask) \ 7050 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c141, (_val), (_mask)) 7051 7052 /* "fec burst error status lower 16 bits": 00000000*/ 7053 #define READ_WC40_RX_X4_STATUS0_FEC_BURST_ERR_STATUSLr(_unit, _pc, _val) \ 7054 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c142, (_val)) 7055 #define WRITE_WC40_RX_X4_STATUS0_FEC_BURST_ERR_STATUSLr(_unit, _pc, _val) \ 7056 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c142, (_val)) 7057 #define MODIFY_WC40_RX_X4_STATUS0_FEC_BURST_ERR_STATUSLr(_unit, _pc, _val, _mask) \ 7058 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c142, (_val), (_mask)) 7059 7060 /* "fec burst error status lower 16 bits": 00000000*/ 7061 #define READ_WC40_RX_X4_STATUS0_FEC_BURST_ERR_STATUSHr(_unit, _pc, _val) \ 7062 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c143, (_val)) 7063 #define WRITE_WC40_RX_X4_STATUS0_FEC_BURST_ERR_STATUSHr(_unit, _pc, _val) \ 7064 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c143, (_val)) 7065 #define MODIFY_WC40_RX_X4_STATUS0_FEC_BURST_ERR_STATUSHr(_unit, _pc, _val, _mask) \ 7066 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c143, (_val), (_mask)) 7067 7068 /* "Barrel Shifter State": 00000000*/ 7069 #define READ_WC40_RX_X4_STATUS0_BARREL_SHIFTER_STATEr(_unit, _pc, _val) \ 7070 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c144, (_val)) 7071 #define WRITE_WC40_RX_X4_STATUS0_BARREL_SHIFTER_STATEr(_unit, _pc, _val) \ 7072 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c144, (_val)) 7073 #define MODIFY_WC40_RX_X4_STATUS0_BARREL_SHIFTER_STATEr(_unit, _pc, _val, _mask) \ 7074 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c144, (_val), (_mask)) 7075 7076 /* cl49_lock_fsm_status register: 00000000*/ 7077 #define READ_WC40_RX_X4_STATUS0_CL49_LOCK_FSM_STATUSr(_unit, _pc, _val) \ 7078 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c145, (_val)) 7079 #define WRITE_WC40_RX_X4_STATUS0_CL49_LOCK_FSM_STATUSr(_unit, _pc, _val) \ 7080 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c145, (_val)) 7081 #define MODIFY_WC40_RX_X4_STATUS0_CL49_LOCK_FSM_STATUSr(_unit, _pc, _val, _mask) \ 7082 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c145, (_val), (_mask)) 7083 7084 /* decode status 0 register: 00000000*/ 7085 #define READ_WC40_RX_X4_STATUS0_DECODE_STATUS_0r(_unit, _pc, _val) \ 7086 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c146, (_val)) 7087 #define WRITE_WC40_RX_X4_STATUS0_DECODE_STATUS_0r(_unit, _pc, _val) \ 7088 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c146, (_val)) 7089 #define MODIFY_WC40_RX_X4_STATUS0_DECODE_STATUS_0r(_unit, _pc, _val, _mask) \ 7090 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c146, (_val), (_mask)) 7091 7092 /* decode status 1 register: 00000000*/ 7093 #define READ_WC40_RX_X4_STATUS0_DECODE_STATUS_1r(_unit, _pc, _val) \ 7094 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c147, (_val)) 7095 #define WRITE_WC40_RX_X4_STATUS0_DECODE_STATUS_1r(_unit, _pc, _val) \ 7096 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c147, (_val)) 7097 #define MODIFY_WC40_RX_X4_STATUS0_DECODE_STATUS_1r(_unit, _pc, _val, _mask) \ 7098 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c147, (_val), (_mask)) 7099 7100 /* scw & K-code group error counters: 00000000*/ 7101 #define READ_WC40_RX_X4_STATUS0_DECODE_STATUS_2r(_unit, _pc, _val) \ 7102 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c148, (_val)) 7103 #define WRITE_WC40_RX_X4_STATUS0_DECODE_STATUS_2r(_unit, _pc, _val) \ 7104 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c148, (_val)) 7105 #define MODIFY_WC40_RX_X4_STATUS0_DECODE_STATUS_2r(_unit, _pc, _val, _mask) \ 7106 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c148, (_val), (_mask)) 7107 7108 /* decode status 3 register: 00000000*/ 7109 #define READ_WC40_RX_X4_STATUS0_DECODE_STATUS_3r(_unit, _pc, _val) \ 7110 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c149, (_val)) 7111 #define WRITE_WC40_RX_X4_STATUS0_DECODE_STATUS_3r(_unit, _pc, _val) \ 7112 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c149, (_val)) 7113 #define MODIFY_WC40_RX_X4_STATUS0_DECODE_STATUS_3r(_unit, _pc, _val, _mask) \ 7114 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c149, (_val), (_mask)) 7115 7116 /* decode status 4 register: 00000000*/ 7117 #define READ_WC40_RX_X4_STATUS0_DECODE_STATUS_4r(_unit, _pc, _val) \ 7118 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c14a, (_val)) 7119 #define WRITE_WC40_RX_X4_STATUS0_DECODE_STATUS_4r(_unit, _pc, _val) \ 7120 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c14a, (_val)) 7121 #define MODIFY_WC40_RX_X4_STATUS0_DECODE_STATUS_4r(_unit, _pc, _val, _mask) \ 7122 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c14a, (_val), (_mask)) 7123 7124 /* decode status 5 register: 00000000*/ 7125 #define READ_WC40_RX_X4_STATUS0_DECODE_STATUS_5r(_unit, _pc, _val) \ 7126 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c14b, (_val)) 7127 #define WRITE_WC40_RX_X4_STATUS0_DECODE_STATUS_5r(_unit, _pc, _val) \ 7128 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c14b, (_val)) 7129 #define MODIFY_WC40_RX_X4_STATUS0_DECODE_STATUS_5r(_unit, _pc, _val, _mask) \ 7130 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c14b, (_val), (_mask)) 7131 7132 /* syncacq_status_0 register: 00000000*/ 7133 #define READ_WC40_RX_X4_STATUS0_SYNCACQ_STATUS_0r(_unit, _pc, _val) \ 7134 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c14c, (_val)) 7135 #define WRITE_WC40_RX_X4_STATUS0_SYNCACQ_STATUS_0r(_unit, _pc, _val) \ 7136 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c14c, (_val)) 7137 #define MODIFY_WC40_RX_X4_STATUS0_SYNCACQ_STATUS_0r(_unit, _pc, _val, _mask) \ 7138 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c14c, (_val), (_mask)) 7139 7140 /* syncacq_status_1 register: 00000000*/ 7141 #define READ_WC40_RX_X4_STATUS0_SYNCACQ_STATUS_1r(_unit, _pc, _val) \ 7142 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c14d, (_val)) 7143 #define WRITE_WC40_RX_X4_STATUS0_SYNCACQ_STATUS_1r(_unit, _pc, _val) \ 7144 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c14d, (_val)) 7145 #define MODIFY_WC40_RX_X4_STATUS0_SYNCACQ_STATUS_1r(_unit, _pc, _val, _mask) \ 7146 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c14d, (_val), (_mask)) 7147 7148 /* bercount register: 00000000*/ 7149 #define READ_WC40_RX_X4_STATUS0_BERCOUNTr(_unit, _pc, _val) \ 7150 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c14e, (_val)) 7151 #define WRITE_WC40_RX_X4_STATUS0_BERCOUNTr(_unit, _pc, _val) \ 7152 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c14e, (_val)) 7153 #define MODIFY_WC40_RX_X4_STATUS0_BERCOUNTr(_unit, _pc, _val, _mask) \ 7154 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c14e, (_val), (_mask)) 7155 7156 7157 7158 /**************************************************************************** 7159 * TSC_WC4_TSC_USER4_RX_X4_Status1 7160 */ 7161 /* "Live status of PMA/PMD Information": 00000000*/ 7162 #define READ_WC40_RX_X4_STATUS1_PMA_PMD_LIVE_STATUSr(_unit, _pc, _val) \ 7163 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c150, (_val)) 7164 #define WRITE_WC40_RX_X4_STATUS1_PMA_PMD_LIVE_STATUSr(_unit, _pc, _val) \ 7165 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c150, (_val)) 7166 #define MODIFY_WC40_RX_X4_STATUS1_PMA_PMD_LIVE_STATUSr(_unit, _pc, _val, _mask) \ 7167 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c150, (_val), (_mask)) 7168 7169 /* "Latched status of PMA/PMD Information": 00000000*/ 7170 #define READ_WC40_RX_X4_STATUS1_PMA_PMD_LATCHED_STATUSr(_unit, _pc, _val) \ 7171 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c151, (_val)) 7172 #define WRITE_WC40_RX_X4_STATUS1_PMA_PMD_LATCHED_STATUSr(_unit, _pc, _val) \ 7173 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c151, (_val)) 7174 #define MODIFY_WC40_RX_X4_STATUS1_PMA_PMD_LATCHED_STATUSr(_unit, _pc, _val, _mask) \ 7175 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c151, (_val), (_mask)) 7176 7177 /* "Latched status of PCS Information": 00000000*/ 7178 #define READ_WC40_RX_X4_STATUS1_PCS_LATCHED_STATUS_1r(_unit, _pc, _val) \ 7179 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c152, (_val)) 7180 #define WRITE_WC40_RX_X4_STATUS1_PCS_LATCHED_STATUS_1r(_unit, _pc, _val) \ 7181 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c152, (_val)) 7182 #define MODIFY_WC40_RX_X4_STATUS1_PCS_LATCHED_STATUS_1r(_unit, _pc, _val, _mask) \ 7183 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c152, (_val), (_mask)) 7184 7185 /* "Latched status of PCS Information": 00000000*/ 7186 #define READ_WC40_RX_X4_STATUS1_PCS_LATCHED_STATUS_0r(_unit, _pc, _val) \ 7187 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c153, (_val)) 7188 #define WRITE_WC40_RX_X4_STATUS1_PCS_LATCHED_STATUS_0r(_unit, _pc, _val) \ 7189 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c153, (_val)) 7190 #define MODIFY_WC40_RX_X4_STATUS1_PCS_LATCHED_STATUS_0r(_unit, _pc, _val, _mask) \ 7191 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c153, (_val), (_mask)) 7192 7193 /* LiveLatched status of PCS Information": 00000000*/ 7194 #define READ_WC40_RX_X4_STATUS1_PCS_LIVE_STATUSr(_unit, _pc, _val) \ 7195 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c154, (_val)) 7196 #define WRITE_WC40_RX_X4_STATUS1_PCS_LIVE_STATUSr(_unit, _pc, _val) \ 7197 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c154, (_val)) 7198 #define MODIFY_WC40_RX_X4_STATUS1_PCS_LIVE_STATUSr(_unit, _pc, _val, _mask) \ 7199 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c154, (_val), (_mask)) 7200 7201 /* cl82 AM lock state machine latched status per lane: 00000000*/ 7202 #define READ_WC40_RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUSr(_unit, _pc, _val) \ 7203 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c155, (_val)) 7204 #define WRITE_WC40_RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUSr(_unit, _pc, _val) \ 7205 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c155, (_val)) 7206 #define MODIFY_WC40_RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUSr(_unit, _pc, _val, _mask) \ 7207 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c155, (_val), (_mask)) 7208 7209 /* cl82 AM lock state machine live status per lane: 00000000*/ 7210 #define READ_WC40_RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUSr(_unit, _pc, _val) \ 7211 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c156, (_val)) 7212 #define WRITE_WC40_RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUSr(_unit, _pc, _val) \ 7213 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c156, (_val)) 7214 #define MODIFY_WC40_RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUSr(_unit, _pc, _val, _mask) \ 7215 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c156, (_val), (_mask)) 7216 7217 7218 7219 /**************************************************************************** 7220 * TSC_WC4_TSC_USER4_RX_X4_Control0_tsc_12 7221 */ 7222 /* User FEC Control 0 register: 00000000*/ 7223 #define READ_WC40_RX_X4_CONTROL0_TSC_12_FEC_0r(_unit, _pc, _val) \ 7224 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c161, (_val)) 7225 #define WRITE_WC40_RX_X4_CONTROL0_TSC_12_FEC_0r(_unit, _pc, _val) \ 7226 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c161, (_val)) 7227 #define MODIFY_WC40_RX_X4_CONTROL0_TSC_12_FEC_0r(_unit, _pc, _val, _mask) \ 7228 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c161, (_val), (_mask)) 7229 7230 /* User FEC Control 1 register: 00000000*/ 7231 #define READ_WC40_RX_X4_CONTROL0_TSC_12_FEC_1r(_unit, _pc, _val) \ 7232 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c162, (_val)) 7233 #define WRITE_WC40_RX_X4_CONTROL0_TSC_12_FEC_1r(_unit, _pc, _val) \ 7234 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c162, (_val)) 7235 #define MODIFY_WC40_RX_X4_CONTROL0_TSC_12_FEC_1r(_unit, _pc, _val, _mask) \ 7236 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c162, (_val), (_mask)) 7237 7238 /* User FEC Control 2 register: 00000000*/ 7239 #define READ_WC40_RX_X4_CONTROL0_TSC_12_FEC_2r(_unit, _pc, _val) \ 7240 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c163, (_val)) 7241 #define WRITE_WC40_RX_X4_CONTROL0_TSC_12_FEC_2r(_unit, _pc, _val) \ 7242 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c163, (_val)) 7243 #define MODIFY_WC40_RX_X4_CONTROL0_TSC_12_FEC_2r(_unit, _pc, _val, _mask) \ 7244 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c163, (_val), (_mask)) 7245 7246 7247 7248 /**************************************************************************** 7249 * TSC_WC4_TSC_USER4_RX_X4_Status0_tsc_12 7250 */ 7251 /* "User FEC debug read data [15:0]": 00000000*/ 7252 #define READ_WC40_RX_X4_STATUS0_TSC_12_FEC_DBG_ERRLr(_unit, _pc, _val) \ 7253 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c170, (_val)) 7254 #define WRITE_WC40_RX_X4_STATUS0_TSC_12_FEC_DBG_ERRLr(_unit, _pc, _val) \ 7255 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c170, (_val)) 7256 #define MODIFY_WC40_RX_X4_STATUS0_TSC_12_FEC_DBG_ERRLr(_unit, _pc, _val, _mask) \ 7257 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c170, (_val), (_mask)) 7258 7259 /* "User FEC debug read data [31:16]": 00000000*/ 7260 #define READ_WC40_RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAHr(_unit, _pc, _val) \ 7261 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c171, (_val)) 7262 #define WRITE_WC40_RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAHr(_unit, _pc, _val) \ 7263 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c171, (_val)) 7264 #define MODIFY_WC40_RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAHr(_unit, _pc, _val, _mask) \ 7265 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c171, (_val), (_mask)) 7266 7267 /* "fec burst error status lower 16 bits": 00000000*/ 7268 #define READ_WC40_RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSLr(_unit, _pc, _val) \ 7269 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c172, (_val)) 7270 #define WRITE_WC40_RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSLr(_unit, _pc, _val) \ 7271 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c172, (_val)) 7272 #define MODIFY_WC40_RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSLr(_unit, _pc, _val, _mask) \ 7273 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c172, (_val), (_mask)) 7274 7275 /* "fec burst error status lower 16 bits": 00000000*/ 7276 #define READ_WC40_RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSHr(_unit, _pc, _val) \ 7277 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c173, (_val)) 7278 #define WRITE_WC40_RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSHr(_unit, _pc, _val) \ 7279 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c173, (_val)) 7280 #define MODIFY_WC40_RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSHr(_unit, _pc, _val, _mask) \ 7281 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c173, (_val), (_mask)) 7282 7283 /* bercount register: 00000000*/ 7284 #define READ_WC40_RX_X4_STATUS0_TSC_12_BERCOUNTr(_unit, _pc, _val) \ 7285 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c174, (_val)) 7286 #define WRITE_WC40_RX_X4_STATUS0_TSC_12_BERCOUNTr(_unit, _pc, _val) \ 7287 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c174, (_val)) 7288 #define MODIFY_WC40_RX_X4_STATUS0_TSC_12_BERCOUNTr(_unit, _pc, _val, _mask) \ 7289 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c174, (_val), (_mask)) 7290 7291 /* TSC_12 EXTENSION of CL49 Lock Status register: 00000000*/ 7292 #define READ_WC40_RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPEr(_unit, _pc, _val) \ 7293 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c175, (_val)) 7294 #define WRITE_WC40_RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPEr(_unit, _pc, _val) \ 7295 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c175, (_val)) 7296 #define MODIFY_WC40_RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPEr(_unit, _pc, _val, _mask) \ 7297 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c175, (_val), (_mask)) 7298 7299 /* TSC_12 VIRTUAL LANE MAPPING: 00000000*/ 7300 #define READ_WC40_RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0r(_unit, _pc, _val) \ 7301 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c176, (_val)) 7302 #define WRITE_WC40_RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0r(_unit, _pc, _val) \ 7303 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c176, (_val)) 7304 #define MODIFY_WC40_RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0r(_unit, _pc, _val, _mask) \ 7305 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c176, (_val), (_mask)) 7306 7307 /* "Barrel Shifter State": 00000000*/ 7308 #define READ_WC40_RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATEr(_unit, _pc, _val) \ 7309 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c177, (_val)) 7310 #define WRITE_WC40_RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATEr(_unit, _pc, _val) \ 7311 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c177, (_val)) 7312 #define MODIFY_WC40_RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATEr(_unit, _pc, _val, _mask) \ 7313 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c177, (_val), (_mask)) 7314 7315 7316 7317 /**************************************************************************** 7318 * TSC_WC4_TSC_USER4_AN_X4_ABILITIES 7319 */ 7320 /* AN ENABLES: 00000000*/ 7321 #define READ_WC40_AN_X4_ABILITIES_ENABLESr(_unit, _pc, _val) \ 7322 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c180, (_val)) 7323 #define WRITE_WC40_AN_X4_ABILITIES_ENABLESr(_unit, _pc, _val) \ 7324 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c180, (_val)) 7325 #define MODIFY_WC40_AN_X4_ABILITIES_ENABLESr(_unit, _pc, _val, _mask) \ 7326 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c180, (_val), (_mask)) 7327 7328 /* CL37 BASE PAGE ABILITIES: 00000000*/ 7329 #define READ_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIESr(_unit, _pc, _val) \ 7330 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c181, (_val)) 7331 #define WRITE_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIESr(_unit, _pc, _val) \ 7332 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c181, (_val)) 7333 #define MODIFY_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIESr(_unit, _pc, _val, _mask) \ 7334 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c181, (_val), (_mask)) 7335 7336 /* CL37 BAM ABILITIES: 00000000*/ 7337 #define READ_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIESr(_unit, _pc, _val) \ 7338 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c182, (_val)) 7339 #define WRITE_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIESr(_unit, _pc, _val) \ 7340 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c182, (_val)) 7341 #define MODIFY_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIESr(_unit, _pc, _val, _mask) \ 7342 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c182, (_val), (_mask)) 7343 7344 /* Cl37 OVER1G ABILITIES REG 1: 00000000*/ 7345 #define READ_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1r(_unit, _pc, _val) \ 7346 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c183, (_val)) 7347 #define WRITE_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1r(_unit, _pc, _val) \ 7348 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c183, (_val)) 7349 #define MODIFY_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1r(_unit, _pc, _val, _mask) \ 7350 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c183, (_val), (_mask)) 7351 7352 /* Cl37 OVER1G ABILITIES REG 0: 00000000*/ 7353 #define READ_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0r(_unit, _pc, _val) \ 7354 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c184, (_val)) 7355 #define WRITE_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0r(_unit, _pc, _val) \ 7356 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c184, (_val)) 7357 #define MODIFY_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0r(_unit, _pc, _val, _mask) \ 7358 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c184, (_val), (_mask)) 7359 7360 /* CL73 BASE PAGE ABILITIES REG 1: 00000000*/ 7361 #define READ_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1r(_unit, _pc, _val) \ 7362 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c185, (_val)) 7363 #define WRITE_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1r(_unit, _pc, _val) \ 7364 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c185, (_val)) 7365 #define MODIFY_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1r(_unit, _pc, _val, _mask) \ 7366 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c185, (_val), (_mask)) 7367 7368 /* CL73 BASE PAGE ABILITIES REG 0: 00000000*/ 7369 #define READ_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0r(_unit, _pc, _val) \ 7370 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c186, (_val)) 7371 #define WRITE_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0r(_unit, _pc, _val) \ 7372 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c186, (_val)) 7373 #define MODIFY_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0r(_unit, _pc, _val, _mask) \ 7374 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c186, (_val), (_mask)) 7375 7376 /* CL73 BAM ABILITIES: 00000000*/ 7377 #define READ_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIESr(_unit, _pc, _val) \ 7378 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c187, (_val)) 7379 #define WRITE_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIESr(_unit, _pc, _val) \ 7380 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c187, (_val)) 7381 #define MODIFY_WC40_AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIESr(_unit, _pc, _val, _mask) \ 7382 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c187, (_val), (_mask)) 7383 7384 /* AN MISC CONTROLS: 00000000*/ 7385 #define READ_WC40_AN_X4_ABILITIES_CONTROLSr(_unit, _pc, _val) \ 7386 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c188, (_val)) 7387 #define WRITE_WC40_AN_X4_ABILITIES_CONTROLSr(_unit, _pc, _val) \ 7388 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c188, (_val)) 7389 #define MODIFY_WC40_AN_X4_ABILITIES_CONTROLSr(_unit, _pc, _val, _mask) \ 7390 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c188, (_val), (_mask)) 7391 7392 7393 7394 /**************************************************************************** 7395 * TSC_WC4_TSC_USER4_AN_X4_HW_LP_PAGES 7396 */ 7397 /* LINK PARTNER MESSAGE_PAGE 5 USER PAGE 1: 00000000*/ 7398 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP1r(_unit, _pc, _val) \ 7399 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c190, (_val)) 7400 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP1r(_unit, _pc, _val) \ 7401 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c190, (_val)) 7402 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP1r(_unit, _pc, _val, _mask) \ 7403 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c190, (_val), (_mask)) 7404 7405 /* LINK PARTNER MESSAGE_PAGE 5 USER PAGE 2: 00000000*/ 7406 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP2r(_unit, _pc, _val) \ 7407 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c191, (_val)) 7408 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP2r(_unit, _pc, _val) \ 7409 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c191, (_val)) 7410 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP2r(_unit, _pc, _val, _mask) \ 7411 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c191, (_val), (_mask)) 7412 7413 /* LINK PARTNER MESSAGE_PAGE 5 USER PAGE 3: 00000000*/ 7414 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP3r(_unit, _pc, _val) \ 7415 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c192, (_val)) 7416 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP3r(_unit, _pc, _val) \ 7417 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c192, (_val)) 7418 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP3r(_unit, _pc, _val, _mask) \ 7419 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c192, (_val), (_mask)) 7420 7421 /* LINK PARTNER MESSAGE_PAGE 5 USER PAGE 4: 00000000*/ 7422 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP4r(_unit, _pc, _val) \ 7423 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c193, (_val)) 7424 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP4r(_unit, _pc, _val) \ 7425 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c193, (_val)) 7426 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_MP5_UP4r(_unit, _pc, _val, _mask) \ 7427 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c193, (_val), (_mask)) 7428 7429 /* LINK PARTNER MESSAGE_PAGE 1024 USER PAGE 1: 00000000*/ 7430 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP1r(_unit, _pc, _val) \ 7431 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c194, (_val)) 7432 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP1r(_unit, _pc, _val) \ 7433 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c194, (_val)) 7434 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP1r(_unit, _pc, _val, _mask) \ 7435 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c194, (_val), (_mask)) 7436 7437 /* LINK PARTNER MESSAGE_PAGE 1024 USER PAGE 2: 00000000*/ 7438 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP2r(_unit, _pc, _val) \ 7439 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c195, (_val)) 7440 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP2r(_unit, _pc, _val) \ 7441 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c195, (_val)) 7442 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP2r(_unit, _pc, _val, _mask) \ 7443 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c195, (_val), (_mask)) 7444 7445 /* LINK PARTNER MESSAGE_PAGE 1024 USER PAGE 3: 00000000*/ 7446 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP3r(_unit, _pc, _val) \ 7447 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c196, (_val)) 7448 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP3r(_unit, _pc, _val) \ 7449 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c196, (_val)) 7450 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP3r(_unit, _pc, _val, _mask) \ 7451 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c196, (_val), (_mask)) 7452 7453 /* LINK PARTNER MESSAGE_PAGE 1024 USER PAGE 4: 00000000*/ 7454 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP4r(_unit, _pc, _val) \ 7455 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c197, (_val)) 7456 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP4r(_unit, _pc, _val) \ 7457 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c197, (_val)) 7458 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_MP1024_UP4r(_unit, _pc, _val, _mask) \ 7459 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c197, (_val), (_mask)) 7460 7461 /* LINK PARTNER BASE PAGE 1: 00000000*/ 7462 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_BASE_PAGE1r(_unit, _pc, _val) \ 7463 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c198, (_val)) 7464 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_BASE_PAGE1r(_unit, _pc, _val) \ 7465 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c198, (_val)) 7466 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_BASE_PAGE1r(_unit, _pc, _val, _mask) \ 7467 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c198, (_val), (_mask)) 7468 7469 /* LINK PARTNER BASE PAGE 2: 00000000*/ 7470 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_BASE_PAGE2r(_unit, _pc, _val) \ 7471 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c199, (_val)) 7472 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_BASE_PAGE2r(_unit, _pc, _val) \ 7473 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c199, (_val)) 7474 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_BASE_PAGE2r(_unit, _pc, _val, _mask) \ 7475 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c199, (_val), (_mask)) 7476 7477 /* LINK PARTNER BASE PAGE 3: 00000000*/ 7478 #define READ_WC40_AN_X4_HW_LP_PAGES_LP_BASE_PAGE3r(_unit, _pc, _val) \ 7479 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c19a, (_val)) 7480 #define WRITE_WC40_AN_X4_HW_LP_PAGES_LP_BASE_PAGE3r(_unit, _pc, _val) \ 7481 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c19a, (_val)) 7482 #define MODIFY_WC40_AN_X4_HW_LP_PAGES_LP_BASE_PAGE3r(_unit, _pc, _val, _mask) \ 7483 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c19a, (_val), (_mask)) 7484 7485 7486 7487 /**************************************************************************** 7488 * TSC_WC4_TSC_USER4_AN_X4_SW_MANAGEMENT 7489 */ 7490 /* LOCAL DEVICE SW CONTROL PAGE 2: 00000000*/ 7491 #define READ_WC40_AN_X4_SW_MANAGEMENT_LD_PAGE_2r(_unit, _pc, _val) \ 7492 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1a0, (_val)) 7493 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_LD_PAGE_2r(_unit, _pc, _val) \ 7494 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1a0, (_val)) 7495 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_LD_PAGE_2r(_unit, _pc, _val, _mask) \ 7496 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1a0, (_val), (_mask)) 7497 7498 /* LOCAL DEVICE SW CONTROL PAGE 1: 00000000*/ 7499 #define READ_WC40_AN_X4_SW_MANAGEMENT_LD_PAGE_1r(_unit, _pc, _val) \ 7500 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1a1, (_val)) 7501 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_LD_PAGE_1r(_unit, _pc, _val) \ 7502 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1a1, (_val)) 7503 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_LD_PAGE_1r(_unit, _pc, _val, _mask) \ 7504 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1a1, (_val), (_mask)) 7505 7506 /* LOCAL DEVICE SW CONTROL PAGE 0: 00000000*/ 7507 #define READ_WC40_AN_X4_SW_MANAGEMENT_LD_PAGE_0r(_unit, _pc, _val) \ 7508 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1a2, (_val)) 7509 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_LD_PAGE_0r(_unit, _pc, _val) \ 7510 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1a2, (_val)) 7511 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_LD_PAGE_0r(_unit, _pc, _val, _mask) \ 7512 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1a2, (_val), (_mask)) 7513 7514 /* LINK PARNTER SW CONTROL PAGE 2: 00000000*/ 7515 #define READ_WC40_AN_X4_SW_MANAGEMENT_LP_PAGE_2r(_unit, _pc, _val) \ 7516 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1a3, (_val)) 7517 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_LP_PAGE_2r(_unit, _pc, _val) \ 7518 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1a3, (_val)) 7519 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_LP_PAGE_2r(_unit, _pc, _val, _mask) \ 7520 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1a3, (_val), (_mask)) 7521 7522 /* LINK PARNTER SW CONTROL PAGE 1: 00000000*/ 7523 #define READ_WC40_AN_X4_SW_MANAGEMENT_LP_PAGE_1r(_unit, _pc, _val) \ 7524 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1a4, (_val)) 7525 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_LP_PAGE_1r(_unit, _pc, _val) \ 7526 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1a4, (_val)) 7527 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_LP_PAGE_1r(_unit, _pc, _val, _mask) \ 7528 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1a4, (_val), (_mask)) 7529 7530 /* LINK PARNTER SW CONTROL PAGE 0: 00000000*/ 7531 #define READ_WC40_AN_X4_SW_MANAGEMENT_LP_PAGE_0r(_unit, _pc, _val) \ 7532 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1a5, (_val)) 7533 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_LP_PAGE_0r(_unit, _pc, _val) \ 7534 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1a5, (_val)) 7535 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_LP_PAGE_0r(_unit, _pc, _val, _mask) \ 7536 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1a5, (_val), (_mask)) 7537 7538 /* SW CONTROL STATUS INFORMATION: 00000000*/ 7539 #define READ_WC40_AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUSr(_unit, _pc, _val) \ 7540 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1a6, (_val)) 7541 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUSr(_unit, _pc, _val) \ 7542 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1a6, (_val)) 7543 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUSr(_unit, _pc, _val, _mask) \ 7544 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1a6, (_val), (_mask)) 7545 7546 /* LOCAL DEVICE CONTROLS: 00000000*/ 7547 #define READ_WC40_AN_X4_SW_MANAGEMENT_LD_CONTROLr(_unit, _pc, _val) \ 7548 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1a7, (_val)) 7549 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_LD_CONTROLr(_unit, _pc, _val) \ 7550 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1a7, (_val)) 7551 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_LD_CONTROLr(_unit, _pc, _val, _mask) \ 7552 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1a7, (_val), (_mask)) 7553 7554 /* AN PAGE SEQUENCER STATUS: 00000000*/ 7555 #define READ_WC40_AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUSr(_unit, _pc, _val) \ 7556 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1a8, (_val)) 7557 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUSr(_unit, _pc, _val) \ 7558 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1a8, (_val)) 7559 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUSr(_unit, _pc, _val, _mask) \ 7560 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1a8, (_val), (_mask)) 7561 7562 /* AN PAGE EXCHANGER STATUS: 00000000*/ 7563 #define READ_WC40_AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUSr(_unit, _pc, _val) \ 7564 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1a9, (_val)) 7565 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUSr(_unit, _pc, _val) \ 7566 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1a9, (_val)) 7567 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUSr(_unit, _pc, _val, _mask) \ 7568 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1a9, (_val), (_mask)) 7569 7570 /* AN PAGE DECODER STATUS: 00000000*/ 7571 #define READ_WC40_AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUSr(_unit, _pc, _val) \ 7572 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1aa, (_val)) 7573 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUSr(_unit, _pc, _val) \ 7574 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1aa, (_val)) 7575 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUSr(_unit, _pc, _val, _mask) \ 7576 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1aa, (_val), (_mask)) 7577 7578 /* AN ABILITY RESOLUTION INFORMATION: 00000000*/ 7579 #define READ_WC40_AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUSr(_unit, _pc, _val) \ 7580 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1ab, (_val)) 7581 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUSr(_unit, _pc, _val) \ 7582 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1ab, (_val)) 7583 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUSr(_unit, _pc, _val, _mask) \ 7584 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1ab, (_val), (_mask)) 7585 7586 /* MISCILLANEOUS AN STATUS: 00000000*/ 7587 #define READ_WC40_AN_X4_SW_MANAGEMENT_AN_MISC_STATUSr(_unit, _pc, _val) \ 7588 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1ac, (_val)) 7589 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_AN_MISC_STATUSr(_unit, _pc, _val) \ 7590 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1ac, (_val)) 7591 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_AN_MISC_STATUSr(_unit, _pc, _val, _mask) \ 7592 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1ac, (_val), (_mask)) 7593 7594 /* TLA SEQUENCER STATUS: 00000000*/ 7595 #define READ_WC40_AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUSr(_unit, _pc, _val) \ 7596 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1ad, (_val)) 7597 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUSr(_unit, _pc, _val) \ 7598 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1ad, (_val)) 7599 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUSr(_unit, _pc, _val, _mask) \ 7600 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1ad, (_val), (_mask)) 7601 7602 /* AN SEQUENCER UNEXPECTED PAGE: 00000000*/ 7603 #define READ_WC40_AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGEr(_unit, _pc, _val) \ 7604 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c1ae, (_val)) 7605 #define WRITE_WC40_AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGEr(_unit, _pc, _val) \ 7606 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c1ae, (_val)) 7607 #define MODIFY_WC40_AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGEr(_unit, _pc, _val, _mask) \ 7608 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c1ae, (_val), (_mask)) 7609 7610 7611 7612 /**************************************************************************** 7613 * TSC_WC4_TSC_USER4_Dsc1b0 7614 */ 7615 /* CDR Control 0 Register: 00000000*/ 7616 #define READ_WC40_DSC1B0_CDR_CTRL0r(_unit, _pc, _val) \ 7617 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c200, (_val)) 7618 #define WRITE_WC40_DSC1B0_CDR_CTRL0r(_unit, _pc, _val) \ 7619 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c200, (_val)) 7620 #define MODIFY_WC40_DSC1B0_CDR_CTRL0r(_unit, _pc, _val, _mask) \ 7621 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c200, (_val), (_mask)) 7622 7623 /* CDR Control 1 Register: 00000000*/ 7624 #define READ_WC40_DSC1B0_CDR_CTRL1r(_unit, _pc, _val) \ 7625 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c201, (_val)) 7626 #define WRITE_WC40_DSC1B0_CDR_CTRL1r(_unit, _pc, _val) \ 7627 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c201, (_val)) 7628 #define MODIFY_WC40_DSC1B0_CDR_CTRL1r(_unit, _pc, _val, _mask) \ 7629 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c201, (_val), (_mask)) 7630 7631 /* CDR Control 2 Register: 00000000*/ 7632 #define READ_WC40_DSC1B0_CDR_CTRL2r(_unit, _pc, _val) \ 7633 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c202, (_val)) 7634 #define WRITE_WC40_DSC1B0_CDR_CTRL2r(_unit, _pc, _val) \ 7635 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c202, (_val)) 7636 #define MODIFY_WC40_DSC1B0_CDR_CTRL2r(_unit, _pc, _val, _mask) \ 7637 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c202, (_val), (_mask)) 7638 7639 /* Phase Interpolator Control 0 Register: 00000000*/ 7640 #define READ_WC40_DSC1B0_PI_CTRL0r(_unit, _pc, _val) \ 7641 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c203, (_val)) 7642 #define WRITE_WC40_DSC1B0_PI_CTRL0r(_unit, _pc, _val) \ 7643 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c203, (_val)) 7644 #define MODIFY_WC40_DSC1B0_PI_CTRL0r(_unit, _pc, _val, _mask) \ 7645 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c203, (_val), (_mask)) 7646 7647 /* Phase Interpolator Control 1 Register: 00000000*/ 7648 #define READ_WC40_DSC1B0_PI_CTRL1r(_unit, _pc, _val) \ 7649 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c204, (_val)) 7650 #define WRITE_WC40_DSC1B0_PI_CTRL1r(_unit, _pc, _val) \ 7651 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c204, (_val)) 7652 #define MODIFY_WC40_DSC1B0_PI_CTRL1r(_unit, _pc, _val, _mask) \ 7653 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c204, (_val), (_mask)) 7654 7655 /* DFE VGA Control 0 Register: 00000000*/ 7656 #define READ_WC40_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 7657 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c205, (_val)) 7658 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 7659 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c205, (_val)) 7660 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \ 7661 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c205, (_val), (_mask)) 7662 7663 /* DFE VGA Control 1 Register: 00000000*/ 7664 #define READ_WC40_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 7665 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c206, (_val)) 7666 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 7667 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c206, (_val)) 7668 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \ 7669 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c206, (_val), (_mask)) 7670 7671 /* DFE VGA Control 2 Register: 00000000*/ 7672 #define READ_WC40_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 7673 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c207, (_val)) 7674 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 7675 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c207, (_val)) 7676 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \ 7677 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c207, (_val), (_mask)) 7678 7679 /* DFE VGA Control 3 Register: 00000000*/ 7680 #define READ_WC40_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 7681 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c208, (_val)) 7682 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 7683 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c208, (_val)) 7684 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \ 7685 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c208, (_val), (_mask)) 7686 7687 /* DFE VGA Control 4 Register: 00000000*/ 7688 #define READ_WC40_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 7689 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c209, (_val)) 7690 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 7691 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c209, (_val)) 7692 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \ 7693 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c209, (_val), (_mask)) 7694 7695 /* DFE VGA Control 5 Register: 00000000*/ 7696 #define READ_WC40_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 7697 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c20a, (_val)) 7698 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 7699 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c20a, (_val)) 7700 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \ 7701 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c20a, (_val), (_mask)) 7702 7703 /* DFE VGA Control 6 Register: 00000000*/ 7704 #define READ_WC40_DSC1B0_DFE_VGA_CTRL6r(_unit, _pc, _val) \ 7705 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c20b, (_val)) 7706 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL6r(_unit, _pc, _val) \ 7707 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c20b, (_val)) 7708 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL6r(_unit, _pc, _val, _mask) \ 7709 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c20b, (_val), (_mask)) 7710 7711 /* DFE VGA Control 7 Register: 00000000*/ 7712 #define READ_WC40_DSC1B0_DFE_VGA_CTRL7r(_unit, _pc, _val) \ 7713 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c20c, (_val)) 7714 #define WRITE_WC40_DSC1B0_DFE_VGA_CTRL7r(_unit, _pc, _val) \ 7715 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c20c, (_val)) 7716 #define MODIFY_WC40_DSC1B0_DFE_VGA_CTRL7r(_unit, _pc, _val, _mask) \ 7717 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c20c, (_val), (_mask)) 7718 7719 /* DSC Diagnostics Control 0 Register: 00000000*/ 7720 #define READ_WC40_DSC1B0_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 7721 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c20d, (_val)) 7722 #define WRITE_WC40_DSC1B0_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 7723 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c20d, (_val)) 7724 #define MODIFY_WC40_DSC1B0_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \ 7725 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c20d, (_val), (_mask)) 7726 7727 /* DSC to uController Control Register: 00000000*/ 7728 #define READ_WC40_DSC1B0_UC_CTRLr(_unit, _pc, _val) \ 7729 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c20e, (_val)) 7730 #define WRITE_WC40_DSC1B0_UC_CTRLr(_unit, _pc, _val) \ 7731 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c20e, (_val)) 7732 #define MODIFY_WC40_DSC1B0_UC_CTRLr(_unit, _pc, _val, _mask) \ 7733 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c20e, (_val), (_mask)) 7734 7735 7736 7737 /**************************************************************************** 7738 * TSC_WC4_TSC_USER4_Dsc2b0 7739 */ 7740 /* DSC State Machine Control 0 Register: 00000000*/ 7741 #define READ_WC40_DSC2B0_ACQ_SM_CTRL0r(_unit, _pc, _val) \ 7742 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c210, (_val)) 7743 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL0r(_unit, _pc, _val) \ 7744 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c210, (_val)) 7745 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL0r(_unit, _pc, _val, _mask) \ 7746 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c210, (_val), (_mask)) 7747 7748 /* DSC State Machine Control 1 Register: 00000000*/ 7749 #define READ_WC40_DSC2B0_ACQ_SM_CTRL1r(_unit, _pc, _val) \ 7750 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c211, (_val)) 7751 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL1r(_unit, _pc, _val) \ 7752 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c211, (_val)) 7753 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL1r(_unit, _pc, _val, _mask) \ 7754 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c211, (_val), (_mask)) 7755 7756 /* DSC State Machine Control 2 Register: 00000000*/ 7757 #define READ_WC40_DSC2B0_ACQ_SM_CTRL2r(_unit, _pc, _val) \ 7758 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c212, (_val)) 7759 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL2r(_unit, _pc, _val) \ 7760 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c212, (_val)) 7761 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL2r(_unit, _pc, _val, _mask) \ 7762 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c212, (_val), (_mask)) 7763 7764 /* DSC State Machine Control 3 Register: 00000000*/ 7765 #define READ_WC40_DSC2B0_ACQ_SM_CTRL3r(_unit, _pc, _val) \ 7766 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c213, (_val)) 7767 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL3r(_unit, _pc, _val) \ 7768 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c213, (_val)) 7769 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL3r(_unit, _pc, _val, _mask) \ 7770 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c213, (_val), (_mask)) 7771 7772 /* DSC State Machine Control 4 Register: 00000000*/ 7773 #define READ_WC40_DSC2B0_ACQ_SM_CTRL4r(_unit, _pc, _val) \ 7774 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c214, (_val)) 7775 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL4r(_unit, _pc, _val) \ 7776 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c214, (_val)) 7777 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL4r(_unit, _pc, _val, _mask) \ 7778 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c214, (_val), (_mask)) 7779 7780 /* DSC State Machine Control 5 Register: 00000000*/ 7781 #define READ_WC40_DSC2B0_ACQ_SM_CTRL5r(_unit, _pc, _val) \ 7782 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c215, (_val)) 7783 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL5r(_unit, _pc, _val) \ 7784 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c215, (_val)) 7785 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL5r(_unit, _pc, _val, _mask) \ 7786 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c215, (_val), (_mask)) 7787 7788 /* DSC State Machine Control 6 Register: 00000000*/ 7789 #define READ_WC40_DSC2B0_ACQ_SM_CTRL6r(_unit, _pc, _val) \ 7790 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c216, (_val)) 7791 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL6r(_unit, _pc, _val) \ 7792 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c216, (_val)) 7793 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL6r(_unit, _pc, _val, _mask) \ 7794 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c216, (_val), (_mask)) 7795 7796 /* DSC State Machine Control 7 Register: 00000000*/ 7797 #define READ_WC40_DSC2B0_ACQ_SM_CTRL7r(_unit, _pc, _val) \ 7798 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c217, (_val)) 7799 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL7r(_unit, _pc, _val) \ 7800 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c217, (_val)) 7801 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL7r(_unit, _pc, _val, _mask) \ 7802 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c217, (_val), (_mask)) 7803 7804 /* DSC State Machine Control 8 Register: 00000000*/ 7805 #define READ_WC40_DSC2B0_ACQ_SM_CTRL8r(_unit, _pc, _val) \ 7806 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c218, (_val)) 7807 #define WRITE_WC40_DSC2B0_ACQ_SM_CTRL8r(_unit, _pc, _val) \ 7808 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c218, (_val)) 7809 #define MODIFY_WC40_DSC2B0_ACQ_SM_CTRL8r(_unit, _pc, _val, _mask) \ 7810 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c218, (_val), (_mask)) 7811 7812 /* DSC Analog Control 0 Register: 00000000*/ 7813 #define READ_WC40_DSC2B0_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 7814 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c219, (_val)) 7815 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 7816 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c219, (_val)) 7817 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \ 7818 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c219, (_val), (_mask)) 7819 7820 /* DSC Analog Control 1 Register: 00000000*/ 7821 #define READ_WC40_DSC2B0_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 7822 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c21a, (_val)) 7823 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 7824 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c21a, (_val)) 7825 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \ 7826 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c21a, (_val), (_mask)) 7827 7828 /* DSC Analog Control 2 Register: 00000000*/ 7829 #define READ_WC40_DSC2B0_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 7830 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c21b, (_val)) 7831 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 7832 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c21b, (_val)) 7833 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \ 7834 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c21b, (_val), (_mask)) 7835 7836 /* DSC Analog Control 3 Register: 00000000*/ 7837 #define READ_WC40_DSC2B0_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 7838 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c21c, (_val)) 7839 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 7840 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c21c, (_val)) 7841 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \ 7842 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c21c, (_val), (_mask)) 7843 7844 /* DSC Analog Control 4 Register: 00000000*/ 7845 #define READ_WC40_DSC2B0_DSC_ANA_CTRL4r(_unit, _pc, _val) \ 7846 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c21d, (_val)) 7847 #define WRITE_WC40_DSC2B0_DSC_ANA_CTRL4r(_unit, _pc, _val) \ 7848 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c21d, (_val)) 7849 #define MODIFY_WC40_DSC2B0_DSC_ANA_CTRL4r(_unit, _pc, _val, _mask) \ 7850 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c21d, (_val), (_mask)) 7851 7852 /* DSC Misc Control 0 Register: 00000000*/ 7853 #define READ_WC40_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 7854 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c21e, (_val)) 7855 #define WRITE_WC40_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 7856 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c21e, (_val)) 7857 #define MODIFY_WC40_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \ 7858 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c21e, (_val), (_mask)) 7859 7860 7861 7862 /**************************************************************************** 7863 * TSC_WC4_TSC_USER4_Dsc3b0 7864 */ 7865 /* CDR Status 0 Register: 00000000*/ 7866 #define READ_WC40_DSC3B0_CDR_STATUS0r(_unit, _pc, _val) \ 7867 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c220, (_val)) 7868 #define WRITE_WC40_DSC3B0_CDR_STATUS0r(_unit, _pc, _val) \ 7869 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c220, (_val)) 7870 #define MODIFY_WC40_DSC3B0_CDR_STATUS0r(_unit, _pc, _val, _mask) \ 7871 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c220, (_val), (_mask)) 7872 7873 /* CDR Status 1 Register: 00000000*/ 7874 #define READ_WC40_DSC3B0_CDR_STATUS1r(_unit, _pc, _val) \ 7875 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c221, (_val)) 7876 #define WRITE_WC40_DSC3B0_CDR_STATUS1r(_unit, _pc, _val) \ 7877 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c221, (_val)) 7878 #define MODIFY_WC40_DSC3B0_CDR_STATUS1r(_unit, _pc, _val, _mask) \ 7879 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c221, (_val), (_mask)) 7880 7881 /* CDR Status 2 Register: 00000000*/ 7882 #define READ_WC40_DSC3B0_CDR_STATUS2r(_unit, _pc, _val) \ 7883 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c222, (_val)) 7884 #define WRITE_WC40_DSC3B0_CDR_STATUS2r(_unit, _pc, _val) \ 7885 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c222, (_val)) 7886 #define MODIFY_WC40_DSC3B0_CDR_STATUS2r(_unit, _pc, _val, _mask) \ 7887 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c222, (_val), (_mask)) 7888 7889 /* Phase Interpolator Status 0 Register: 00000000*/ 7890 #define READ_WC40_DSC3B0_PI_STATUS0r(_unit, _pc, _val) \ 7891 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c223, (_val)) 7892 #define WRITE_WC40_DSC3B0_PI_STATUS0r(_unit, _pc, _val) \ 7893 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c223, (_val)) 7894 #define MODIFY_WC40_DSC3B0_PI_STATUS0r(_unit, _pc, _val, _mask) \ 7895 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c223, (_val), (_mask)) 7896 7897 /* Phase Interpolator Status 1 Register: 00000000*/ 7898 #define READ_WC40_DSC3B0_PI_STATUS1r(_unit, _pc, _val) \ 7899 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c224, (_val)) 7900 #define WRITE_WC40_DSC3B0_PI_STATUS1r(_unit, _pc, _val) \ 7901 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c224, (_val)) 7902 #define MODIFY_WC40_DSC3B0_PI_STATUS1r(_unit, _pc, _val, _mask) \ 7903 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c224, (_val), (_mask)) 7904 7905 /* DFE VGA Status 0 Register: 00000000*/ 7906 #define READ_WC40_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 7907 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c225, (_val)) 7908 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 7909 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c225, (_val)) 7910 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \ 7911 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c225, (_val), (_mask)) 7912 7913 /* DFE VGA Status 1 Register: 00000000*/ 7914 #define READ_WC40_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 7915 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c226, (_val)) 7916 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 7917 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c226, (_val)) 7918 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \ 7919 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c226, (_val), (_mask)) 7920 7921 /* DFE VGA Status 2 Register: 00000000*/ 7922 #define READ_WC40_DSC3B0_DFE_VGA_STATUS2r(_unit, _pc, _val) \ 7923 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c227, (_val)) 7924 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS2r(_unit, _pc, _val) \ 7925 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c227, (_val)) 7926 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS2r(_unit, _pc, _val, _mask) \ 7927 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c227, (_val), (_mask)) 7928 7929 /* DFE VGA Status 3 Register: 00000000*/ 7930 #define READ_WC40_DSC3B0_DFE_VGA_STATUS3r(_unit, _pc, _val) \ 7931 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c228, (_val)) 7932 #define WRITE_WC40_DSC3B0_DFE_VGA_STATUS3r(_unit, _pc, _val) \ 7933 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c228, (_val)) 7934 #define MODIFY_WC40_DSC3B0_DFE_VGA_STATUS3r(_unit, _pc, _val, _mask) \ 7935 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c228, (_val), (_mask)) 7936 7937 /* ACQ State Machine Status 0 Register: 00000000*/ 7938 #define READ_WC40_DSC3B0_ACQ_SM_STATUS0r(_unit, _pc, _val) \ 7939 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c229, (_val)) 7940 #define WRITE_WC40_DSC3B0_ACQ_SM_STATUS0r(_unit, _pc, _val) \ 7941 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c229, (_val)) 7942 #define MODIFY_WC40_DSC3B0_ACQ_SM_STATUS0r(_unit, _pc, _val, _mask) \ 7943 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c229, (_val), (_mask)) 7944 7945 /* ACQ State Machine Status 1 Register: 00000000*/ 7946 #define READ_WC40_DSC3B0_ACQ_SM_STATUS1r(_unit, _pc, _val) \ 7947 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c22a, (_val)) 7948 #define WRITE_WC40_DSC3B0_ACQ_SM_STATUS1r(_unit, _pc, _val) \ 7949 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c22a, (_val)) 7950 #define MODIFY_WC40_DSC3B0_ACQ_SM_STATUS1r(_unit, _pc, _val, _mask) \ 7951 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c22a, (_val), (_mask)) 7952 7953 /* DSC Analog Status 0 Register: 00000000*/ 7954 #define READ_WC40_DSC3B0_ANA_STATUS0r(_unit, _pc, _val) \ 7955 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c22b, (_val)) 7956 #define WRITE_WC40_DSC3B0_ANA_STATUS0r(_unit, _pc, _val) \ 7957 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c22b, (_val)) 7958 #define MODIFY_WC40_DSC3B0_ANA_STATUS0r(_unit, _pc, _val, _mask) \ 7959 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c22b, (_val), (_mask)) 7960 7961 /* DSC Analog Status 1 Register: 00000000*/ 7962 #define READ_WC40_DSC3B0_ANA_STATUS1r(_unit, _pc, _val) \ 7963 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c22c, (_val)) 7964 #define WRITE_WC40_DSC3B0_ANA_STATUS1r(_unit, _pc, _val) \ 7965 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c22c, (_val)) 7966 #define MODIFY_WC40_DSC3B0_ANA_STATUS1r(_unit, _pc, _val, _mask) \ 7967 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c22c, (_val), (_mask)) 7968 7969 /* DSC Analog Status 2 Register: 00000000*/ 7970 #define READ_WC40_DSC3B0_ANA_STATUS2r(_unit, _pc, _val) \ 7971 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c22d, (_val)) 7972 #define WRITE_WC40_DSC3B0_ANA_STATUS2r(_unit, _pc, _val) \ 7973 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c22d, (_val)) 7974 #define MODIFY_WC40_DSC3B0_ANA_STATUS2r(_unit, _pc, _val, _mask) \ 7975 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c22d, (_val), (_mask)) 7976 7977 /* DSC Analog Status 3 Register: 00000000*/ 7978 #define READ_WC40_DSC3B0_ANA_STATUS3r(_unit, _pc, _val) \ 7979 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c22e, (_val)) 7980 #define WRITE_WC40_DSC3B0_ANA_STATUS3r(_unit, _pc, _val) \ 7981 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c22e, (_val)) 7982 #define MODIFY_WC40_DSC3B0_ANA_STATUS3r(_unit, _pc, _val, _mask) \ 7983 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c22e, (_val), (_mask)) 7984 7985 7986 7987 /**************************************************************************** 7988 * TSC_WC4_TSC_USER4_Dsc4b0 7989 */ 7990 /* State Machine Control 0 Register: 00000000*/ 7991 #define READ_WC40_DSC4B0_TUNING_SM_CTRL0r(_unit, _pc, _val) \ 7992 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c230, (_val)) 7993 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL0r(_unit, _pc, _val) \ 7994 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c230, (_val)) 7995 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL0r(_unit, _pc, _val, _mask) \ 7996 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c230, (_val), (_mask)) 7997 7998 /* State Machine Control 1 Register: 00000000*/ 7999 #define READ_WC40_DSC4B0_TUNING_SM_CTRL1r(_unit, _pc, _val) \ 8000 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c231, (_val)) 8001 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL1r(_unit, _pc, _val) \ 8002 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c231, (_val)) 8003 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL1r(_unit, _pc, _val, _mask) \ 8004 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c231, (_val), (_mask)) 8005 8006 /* State Machine Control 2 Register: 00000000*/ 8007 #define READ_WC40_DSC4B0_TUNING_SM_CTRL2r(_unit, _pc, _val) \ 8008 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c232, (_val)) 8009 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL2r(_unit, _pc, _val) \ 8010 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c232, (_val)) 8011 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL2r(_unit, _pc, _val, _mask) \ 8012 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c232, (_val), (_mask)) 8013 8014 /* State Machine Control 3 Register: 00000000*/ 8015 #define READ_WC40_DSC4B0_TUNING_SM_CTRL3r(_unit, _pc, _val) \ 8016 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c233, (_val)) 8017 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL3r(_unit, _pc, _val) \ 8018 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c233, (_val)) 8019 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL3r(_unit, _pc, _val, _mask) \ 8020 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c233, (_val), (_mask)) 8021 8022 /* State Machine Control 4 Register: 00000000*/ 8023 #define READ_WC40_DSC4B0_TUNING_SM_CTRL4r(_unit, _pc, _val) \ 8024 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c234, (_val)) 8025 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL4r(_unit, _pc, _val) \ 8026 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c234, (_val)) 8027 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL4r(_unit, _pc, _val, _mask) \ 8028 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c234, (_val), (_mask)) 8029 8030 /* State Machine Control 5 Register: 00000000*/ 8031 #define READ_WC40_DSC4B0_TUNING_SM_CTRL5r(_unit, _pc, _val) \ 8032 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c235, (_val)) 8033 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL5r(_unit, _pc, _val) \ 8034 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c235, (_val)) 8035 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL5r(_unit, _pc, _val, _mask) \ 8036 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c235, (_val), (_mask)) 8037 8038 /* State Machine Control 6 Register: 00000000*/ 8039 #define READ_WC40_DSC4B0_TUNING_SM_CTRL6r(_unit, _pc, _val) \ 8040 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c236, (_val)) 8041 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL6r(_unit, _pc, _val) \ 8042 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c236, (_val)) 8043 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL6r(_unit, _pc, _val, _mask) \ 8044 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c236, (_val), (_mask)) 8045 8046 /* State Machine Control 7 Register: 00000000*/ 8047 #define READ_WC40_DSC4B0_TUNING_SM_CTRL7r(_unit, _pc, _val) \ 8048 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c237, (_val)) 8049 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL7r(_unit, _pc, _val) \ 8050 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c237, (_val)) 8051 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL7r(_unit, _pc, _val, _mask) \ 8052 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c237, (_val), (_mask)) 8053 8054 /* State Machine Control 8 Register: 00000000*/ 8055 #define READ_WC40_DSC4B0_TUNING_SM_CTRL8r(_unit, _pc, _val) \ 8056 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c238, (_val)) 8057 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL8r(_unit, _pc, _val) \ 8058 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c238, (_val)) 8059 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL8r(_unit, _pc, _val, _mask) \ 8060 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c238, (_val), (_mask)) 8061 8062 /* State Machine Control 9 Register: 00000000*/ 8063 #define READ_WC40_DSC4B0_TUNING_SM_CTRL9r(_unit, _pc, _val) \ 8064 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c239, (_val)) 8065 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL9r(_unit, _pc, _val) \ 8066 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c239, (_val)) 8067 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL9r(_unit, _pc, _val, _mask) \ 8068 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c239, (_val), (_mask)) 8069 8070 /* State Machine Control 10 Register: 00000000*/ 8071 #define READ_WC40_DSC4B0_TUNING_SM_CTRL10r(_unit, _pc, _val) \ 8072 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c23a, (_val)) 8073 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL10r(_unit, _pc, _val) \ 8074 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c23a, (_val)) 8075 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL10r(_unit, _pc, _val, _mask) \ 8076 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c23a, (_val), (_mask)) 8077 8078 /* State Machine Control 11 Register: 00000000*/ 8079 #define READ_WC40_DSC4B0_TUNING_SM_CTRL11r(_unit, _pc, _val) \ 8080 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c23b, (_val)) 8081 #define WRITE_WC40_DSC4B0_TUNING_SM_CTRL11r(_unit, _pc, _val) \ 8082 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c23b, (_val)) 8083 #define MODIFY_WC40_DSC4B0_TUNING_SM_CTRL11r(_unit, _pc, _val, _mask) \ 8084 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c23b, (_val), (_mask)) 8085 8086 /* Acquisition State Machine Control 9 Register: 00000000*/ 8087 #define READ_WC40_DSC4B0_ACQ_SM_CTRL9r(_unit, _pc, _val) \ 8088 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c23c, (_val)) 8089 #define WRITE_WC40_DSC4B0_ACQ_SM_CTRL9r(_unit, _pc, _val) \ 8090 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c23c, (_val)) 8091 #define MODIFY_WC40_DSC4B0_ACQ_SM_CTRL9r(_unit, _pc, _val, _mask) \ 8092 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c23c, (_val), (_mask)) 8093 8094 8095 8096 /**************************************************************************** 8097 * TSC_WC4_TSC_USER4_Dsc5b0 8098 */ 8099 /* State Machine Status 0 Register: 00000000*/ 8100 #define READ_WC40_DSC5B0_TUNING_SM_STATUS0r(_unit, _pc, _val) \ 8101 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c240, (_val)) 8102 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS0r(_unit, _pc, _val) \ 8103 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c240, (_val)) 8104 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS0r(_unit, _pc, _val, _mask) \ 8105 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c240, (_val), (_mask)) 8106 8107 /* State Machine Status 1 Register: 00000000*/ 8108 #define READ_WC40_DSC5B0_TUNING_SM_STATUS1r(_unit, _pc, _val) \ 8109 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c241, (_val)) 8110 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS1r(_unit, _pc, _val) \ 8111 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c241, (_val)) 8112 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS1r(_unit, _pc, _val, _mask) \ 8113 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c241, (_val), (_mask)) 8114 8115 /* State Machine Status 2 Register: 00000000*/ 8116 #define READ_WC40_DSC5B0_TUNING_SM_STATUS2r(_unit, _pc, _val) \ 8117 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c242, (_val)) 8118 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS2r(_unit, _pc, _val) \ 8119 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c242, (_val)) 8120 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS2r(_unit, _pc, _val, _mask) \ 8121 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c242, (_val), (_mask)) 8122 8123 /* State Machine Status 3 Register: 00000000*/ 8124 #define READ_WC40_DSC5B0_TUNING_SM_STATUS3r(_unit, _pc, _val) \ 8125 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c243, (_val)) 8126 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS3r(_unit, _pc, _val) \ 8127 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c243, (_val)) 8128 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS3r(_unit, _pc, _val, _mask) \ 8129 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c243, (_val), (_mask)) 8130 8131 /* State Machine Status 4 Register: 00000000*/ 8132 #define READ_WC40_DSC5B0_TUNING_SM_STATUS4r(_unit, _pc, _val) \ 8133 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c244, (_val)) 8134 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS4r(_unit, _pc, _val) \ 8135 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c244, (_val)) 8136 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS4r(_unit, _pc, _val, _mask) \ 8137 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c244, (_val), (_mask)) 8138 8139 /* State Machine Status 5 Register: 00000000*/ 8140 #define READ_WC40_DSC5B0_TUNING_SM_STATUS5r(_unit, _pc, _val) \ 8141 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c245, (_val)) 8142 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS5r(_unit, _pc, _val) \ 8143 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c245, (_val)) 8144 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS5r(_unit, _pc, _val, _mask) \ 8145 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c245, (_val), (_mask)) 8146 8147 /* State Machine Status 6 Register: 00000000*/ 8148 #define READ_WC40_DSC5B0_TUNING_SM_STATUS6r(_unit, _pc, _val) \ 8149 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c246, (_val)) 8150 #define WRITE_WC40_DSC5B0_TUNING_SM_STATUS6r(_unit, _pc, _val) \ 8151 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c246, (_val)) 8152 #define MODIFY_WC40_DSC5B0_TUNING_SM_STATUS6r(_unit, _pc, _val, _mask) \ 8153 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c246, (_val), (_mask)) 8154 8155 8156 8157 /**************************************************************************** 8158 * TSC_WC4_TSC_USER4_CL72 8159 */ 8160 /* CL72 TX Coefficient Update Register: 00000000*/ 8161 #define READ_WC40_CL72_XMT_CONTROL_REGISTERr(_unit, _pc, _val) \ 8162 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c250, (_val)) 8163 #define WRITE_WC40_CL72_XMT_CONTROL_REGISTERr(_unit, _pc, _val) \ 8164 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c250, (_val)) 8165 #define MODIFY_WC40_CL72_XMT_CONTROL_REGISTERr(_unit, _pc, _val, _mask) \ 8166 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c250, (_val), (_mask)) 8167 8168 /* CL72 Status Report Register: 00000000*/ 8169 #define READ_WC40_CL72_RCVD_STATUS_REGISTERr(_unit, _pc, _val) \ 8170 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c251, (_val)) 8171 #define WRITE_WC40_CL72_RCVD_STATUS_REGISTERr(_unit, _pc, _val) \ 8172 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c251, (_val)) 8173 #define MODIFY_WC40_CL72_RCVD_STATUS_REGISTERr(_unit, _pc, _val, _mask) \ 8174 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c251, (_val), (_mask)) 8175 8176 /* CL72 TX FIR Tap Register: 00000000*/ 8177 #define READ_WC40_CL72_TX_FIR_TAP_REGISTERr(_unit, _pc, _val) \ 8178 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c252, (_val)) 8179 #define WRITE_WC40_CL72_TX_FIR_TAP_REGISTERr(_unit, _pc, _val) \ 8180 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c252, (_val)) 8181 #define MODIFY_WC40_CL72_TX_FIR_TAP_REGISTERr(_unit, _pc, _val, _mask) \ 8182 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c252, (_val), (_mask)) 8183 8184 /* CL72 Miscellaneous_1 Control Register: 00000000*/ 8185 #define READ_WC40_CL72_MISC1_CONTROLr(_unit, _pc, _val) \ 8186 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c253, (_val)) 8187 #define WRITE_WC40_CL72_MISC1_CONTROLr(_unit, _pc, _val) \ 8188 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c253, (_val)) 8189 #define MODIFY_WC40_CL72_MISC1_CONTROLr(_unit, _pc, _val, _mask) \ 8190 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c253, (_val), (_mask)) 8191 8192 /* CL72 Miscellaneous_2 Control Register: 00000000*/ 8193 #define READ_WC40_CL72_MISC2_CONTROLr(_unit, _pc, _val) \ 8194 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c254, (_val)) 8195 #define WRITE_WC40_CL72_MISC2_CONTROLr(_unit, _pc, _val) \ 8196 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c254, (_val)) 8197 #define MODIFY_WC40_CL72_MISC2_CONTROLr(_unit, _pc, _val, _mask) \ 8198 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c254, (_val), (_mask)) 8199 8200 /* CL72 Debug 2 Register: 00000000*/ 8201 #define READ_WC40_CL72_DEBUG_2_REGISTERr(_unit, _pc, _val) \ 8202 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c256, (_val)) 8203 #define WRITE_WC40_CL72_DEBUG_2_REGISTERr(_unit, _pc, _val) \ 8204 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c256, (_val)) 8205 #define MODIFY_WC40_CL72_DEBUG_2_REGISTERr(_unit, _pc, _val, _mask) \ 8206 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c256, (_val), (_mask)) 8207 8208 /* CL72 Debug 3 Register: 00000000*/ 8209 #define READ_WC40_CL72_DEBUG_3_REGISTERr(_unit, _pc, _val) \ 8210 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c257, (_val)) 8211 #define WRITE_WC40_CL72_DEBUG_3_REGISTERr(_unit, _pc, _val) \ 8212 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c257, (_val)) 8213 #define MODIFY_WC40_CL72_DEBUG_3_REGISTERr(_unit, _pc, _val, _mask) \ 8214 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c257, (_val), (_mask)) 8215 8216 /* CL72 Debug 4 Register: 00000000*/ 8217 #define READ_WC40_CL72_DEBUG_4_REGISTERr(_unit, _pc, _val) \ 8218 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c258, (_val)) 8219 #define WRITE_WC40_CL72_DEBUG_4_REGISTERr(_unit, _pc, _val) \ 8220 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c258, (_val)) 8221 #define MODIFY_WC40_CL72_DEBUG_4_REGISTERr(_unit, _pc, _val, _mask) \ 8222 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c258, (_val), (_mask)) 8223 8224 /* : 00000000*/ 8225 #define READ_WC40_CL72_CL72_LD_STATUS_PAGEr(_unit, _pc, _val) \ 8226 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c259, (_val)) 8227 #define WRITE_WC40_CL72_CL72_LD_STATUS_PAGEr(_unit, _pc, _val) \ 8228 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c259, (_val)) 8229 #define MODIFY_WC40_CL72_CL72_LD_STATUS_PAGEr(_unit, _pc, _val, _mask) \ 8230 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c259, (_val), (_mask)) 8231 8232 /* : 00000000*/ 8233 #define READ_WC40_CL72_CL72_LP_CONTROL_PAGEr(_unit, _pc, _val) \ 8234 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c25a, (_val)) 8235 #define WRITE_WC40_CL72_CL72_LP_CONTROL_PAGEr(_unit, _pc, _val) \ 8236 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c25a, (_val)) 8237 #define MODIFY_WC40_CL72_CL72_LP_CONTROL_PAGEr(_unit, _pc, _val, _mask) \ 8238 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c25a, (_val), (_mask)) 8239 8240 /* : 00000000*/ 8241 #define READ_WC40_CL72_CL72_NEWPG_RCVD_OVERRIDE_PAGEr(_unit, _pc, _val) \ 8242 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c25b, (_val)) 8243 #define WRITE_WC40_CL72_CL72_NEWPG_RCVD_OVERRIDE_PAGEr(_unit, _pc, _val) \ 8244 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c25b, (_val)) 8245 #define MODIFY_WC40_CL72_CL72_NEWPG_RCVD_OVERRIDE_PAGEr(_unit, _pc, _val, _mask) \ 8246 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c25b, (_val), (_mask)) 8247 8248 /* : 00000000*/ 8249 #define READ_WC40_CL72_CL72_READY_FOR_CMD_REGISTERr(_unit, _pc, _val) \ 8250 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c25c, (_val)) 8251 #define WRITE_WC40_CL72_CL72_READY_FOR_CMD_REGISTERr(_unit, _pc, _val) \ 8252 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c25c, (_val)) 8253 #define MODIFY_WC40_CL72_CL72_READY_FOR_CMD_REGISTERr(_unit, _pc, _val, _mask) \ 8254 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c25c, (_val), (_mask)) 8255 8256 8257 8258 /**************************************************************************** 8259 * TSC_WC4_TSC_USER4_UCSS_X4 8260 */ 8261 /* Micro-controller firmware_mode Register: 00000000*/ 8262 #define READ_WC40_UCSS_X4_FIRMWARE_MODEr(_unit, _pc, _val) \ 8263 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c260, (_val)) 8264 #define WRITE_WC40_UCSS_X4_FIRMWARE_MODEr(_unit, _pc, _val) \ 8265 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c260, (_val)) 8266 #define MODIFY_WC40_UCSS_X4_FIRMWARE_MODEr(_unit, _pc, _val, _mask) \ 8267 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c260, (_val), (_mask)) 8268 8269 /* Micro-controller GPIO Control Register: 00000000*/ 8270 #define READ_WC40_UCSS_X4_GPIO_CTRLr(_unit, _pc, _val) \ 8271 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c261, (_val)) 8272 #define WRITE_WC40_UCSS_X4_GPIO_CTRLr(_unit, _pc, _val) \ 8273 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c261, (_val)) 8274 #define MODIFY_WC40_UCSS_X4_GPIO_CTRLr(_unit, _pc, _val, _mask) \ 8275 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c261, (_val), (_mask)) 8276 8277 /* Micro-controller GPIO Status Register: 00000000*/ 8278 #define READ_WC40_UCSS_X4_GPIO_STSr(_unit, _pc, _val) \ 8279 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c262, (_val)) 8280 #define WRITE_WC40_UCSS_X4_GPIO_STSr(_unit, _pc, _val) \ 8281 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c262, (_val)) 8282 #define MODIFY_WC40_UCSS_X4_GPIO_STSr(_unit, _pc, _val, _mask) \ 8283 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c262, (_val), (_mask)) 8284 8285 /* Micro-controller GPR Register: 00000000*/ 8286 #define READ_WC40_UCSS_X4_GPR_TYPEr(_unit, _pc, _val) \ 8287 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c263, (_val)) 8288 #define WRITE_WC40_UCSS_X4_GPR_TYPEr(_unit, _pc, _val) \ 8289 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c263, (_val)) 8290 #define MODIFY_WC40_UCSS_X4_GPR_TYPEr(_unit, _pc, _val, _mask) \ 8291 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c263, (_val), (_mask)) 8292 8293 8294 8295 /**************************************************************************** 8296 * TSC_WC4_TSC_USER4_Digital 8297 */ 8298 /* 1000X control 1 register: 00000000*/ 8299 #define READ_WC40_DIGITAL_CONTROL1000X1r(_unit, _pc, _val) \ 8300 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c300, (_val)) 8301 #define WRITE_WC40_DIGITAL_CONTROL1000X1r(_unit, _pc, _val) \ 8302 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c300, (_val)) 8303 #define MODIFY_WC40_DIGITAL_CONTROL1000X1r(_unit, _pc, _val, _mask) \ 8304 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c300, (_val), (_mask)) 8305 8306 /* 1000X control 2 register: 00000000*/ 8307 #define READ_WC40_DIGITAL_CONTROL1000X2r(_unit, _pc, _val) \ 8308 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c301, (_val)) 8309 #define WRITE_WC40_DIGITAL_CONTROL1000X2r(_unit, _pc, _val) \ 8310 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c301, (_val)) 8311 #define MODIFY_WC40_DIGITAL_CONTROL1000X2r(_unit, _pc, _val, _mask) \ 8312 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c301, (_val), (_mask)) 8313 8314 /* 1000X control 4 register: 00000000*/ 8315 #define READ_WC40_DIGITAL_CONTROL1000X4r(_unit, _pc, _val) \ 8316 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c303, (_val)) 8317 #define WRITE_WC40_DIGITAL_CONTROL1000X4r(_unit, _pc, _val) \ 8318 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c303, (_val)) 8319 #define MODIFY_WC40_DIGITAL_CONTROL1000X4r(_unit, _pc, _val, _mask) \ 8320 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c303, (_val), (_mask)) 8321 8322 /* 1000X status 1 register: 00000000*/ 8323 #define READ_WC40_DIGITAL_STATUS1000X1r(_unit, _pc, _val) \ 8324 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c304, (_val)) 8325 #define WRITE_WC40_DIGITAL_STATUS1000X1r(_unit, _pc, _val) \ 8326 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c304, (_val)) 8327 #define MODIFY_WC40_DIGITAL_STATUS1000X1r(_unit, _pc, _val, _mask) \ 8328 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c304, (_val), (_mask)) 8329 8330 /* Invalid code group count register: 00000000*/ 8331 #define READ_WC40_DIGITAL_BADCODEGROUPr(_unit, _pc, _val) \ 8332 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c307, (_val)) 8333 #define WRITE_WC40_DIGITAL_BADCODEGROUPr(_unit, _pc, _val) \ 8334 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c307, (_val)) 8335 #define MODIFY_WC40_DIGITAL_BADCODEGROUPr(_unit, _pc, _val, _mask) \ 8336 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c307, (_val), (_mask)) 8337 8338 /* Miscellaneous 2 control register: 00000000*/ 8339 #define READ_WC40_DIGITAL_MISC2r(_unit, _pc, _val) \ 8340 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c309, (_val)) 8341 #define WRITE_WC40_DIGITAL_MISC2r(_unit, _pc, _val) \ 8342 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c309, (_val)) 8343 #define MODIFY_WC40_DIGITAL_MISC2r(_unit, _pc, _val, _mask) \ 8344 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c309, (_val), (_mask)) 8345 8346 /* spare register: 00000000*/ 8347 #define READ_WC40_DIGITAL_SPAREr(_unit, _pc, _val) \ 8348 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c30a, (_val)) 8349 #define WRITE_WC40_DIGITAL_SPAREr(_unit, _pc, _val) \ 8350 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c30a, (_val)) 8351 #define MODIFY_WC40_DIGITAL_SPAREr(_unit, _pc, _val, _mask) \ 8352 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c30a, (_val), (_mask)) 8353 8354 8355 8356 /**************************************************************************** 8357 * TSC_WC4_TSC_USER4_Digital5 8358 */ 8359 /* Misc6: 00000000*/ 8360 #define READ_WC40_DIGITAL5_MISC6r(_unit, _pc, _val) \ 8361 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c310, (_val)) 8362 #define WRITE_WC40_DIGITAL5_MISC6r(_unit, _pc, _val) \ 8363 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c310, (_val)) 8364 #define MODIFY_WC40_DIGITAL5_MISC6r(_unit, _pc, _val, _mask) \ 8365 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c310, (_val), (_mask)) 8366 8367 8368 8369 /**************************************************************************** 8370 * TSC_WC4_TSC_USER4_CL49 8371 */ 8372 /* BER fsm - ber counter: 00000000*/ 8373 #define READ_WC40_CL49_CL49_BERCNTr(_unit, _pc, _val) \ 8374 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c324, (_val)) 8375 #define WRITE_WC40_CL49_CL49_BERCNTr(_unit, _pc, _val) \ 8376 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c324, (_val)) 8377 #define MODIFY_WC40_CL49_CL49_BERCNTr(_unit, _pc, _val, _mask) \ 8378 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c324, (_val), (_mask)) 8379 8380 8381 8382 /**************************************************************************** 8383 * TSC_WC4_TSC_USER4_CL73 8384 */ 8385 /* Clause 73 user control: 00000000*/ 8386 #define READ_WC40_CL73_UCTRL1r(_unit, _pc, _val) \ 8387 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c340, (_val)) 8388 #define WRITE_WC40_CL73_UCTRL1r(_unit, _pc, _val) \ 8389 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c340, (_val)) 8390 #define MODIFY_WC40_CL73_UCTRL1r(_unit, _pc, _val, _mask) \ 8391 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c340, (_val), (_mask)) 8392 8393 /* Clause 73 user status: 00000000*/ 8394 #define READ_WC40_CL73_USTAT1r(_unit, _pc, _val) \ 8395 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c341, (_val)) 8396 #define WRITE_WC40_CL73_USTAT1r(_unit, _pc, _val) \ 8397 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c341, (_val)) 8398 #define MODIFY_WC40_CL73_USTAT1r(_unit, _pc, _val, _mask) \ 8399 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c341, (_val), (_mask)) 8400 8401 /* Clause 73 user control2: 00000000*/ 8402 #define READ_WC40_CL73_UCTRL2r(_unit, _pc, _val) \ 8403 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000c342, (_val)) 8404 #define WRITE_WC40_CL73_UCTRL2r(_unit, _pc, _val) \ 8405 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000c342, (_val)) 8406 #define MODIFY_WC40_CL73_UCTRL2r(_unit, _pc, _val, _mask) \ 8407 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000c342, (_val), (_mask)) 8408 8409 8410 8411 /**************************************************************************** 8412 * TSC_WC4_TSC_USERX_uC_Info_B1 8413 */ 8414 /* Micro-controller Version Register: 00000000*/ 8415 #define READ_WC40_UC_INFO_B1_VERSIONr(_unit, _pc, _val) \ 8416 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000f010, (_val)) 8417 #define WRITE_WC40_UC_INFO_B1_VERSIONr(_unit, _pc, _val) \ 8418 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000f010, (_val)) 8419 #define MODIFY_WC40_UC_INFO_B1_VERSIONr(_unit, _pc, _val, _mask) \ 8420 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000f010, (_val), (_mask)) 8421 8422 /* Micro-controller Target Register: 00000000*/ 8423 #define READ_WC40_UC_INFO_B1_TARGETr(_unit, _pc, _val) \ 8424 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000f011, (_val)) 8425 #define WRITE_WC40_UC_INFO_B1_TARGETr(_unit, _pc, _val) \ 8426 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000f011, (_val)) 8427 #define MODIFY_WC40_UC_INFO_B1_TARGETr(_unit, _pc, _val, _mask) \ 8428 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000f011, (_val), (_mask)) 8429 8430 /* Micro Tuning states Bypass Register: 00000000*/ 8431 #define READ_WC40_UC_INFO_B1_TUNING_STATE_BYPASSr(_unit, _pc, _val) \ 8432 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000f013, (_val)) 8433 #define WRITE_WC40_UC_INFO_B1_TUNING_STATE_BYPASSr(_unit, _pc, _val) \ 8434 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000f013, (_val)) 8435 #define MODIFY_WC40_UC_INFO_B1_TUNING_STATE_BYPASSr(_unit, _pc, _val, _mask) \ 8436 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000f013, (_val), (_mask)) 8437 8438 /* Die-Temperature Register: 00000000*/ 8439 #define READ_WC40_UC_INFO_B1_TEMPERATUREr(_unit, _pc, _val) \ 8440 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000f014, (_val)) 8441 #define WRITE_WC40_UC_INFO_B1_TEMPERATUREr(_unit, _pc, _val) \ 8442 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000f014, (_val)) 8443 #define MODIFY_WC40_UC_INFO_B1_TEMPERATUREr(_unit, _pc, _val, _mask) \ 8444 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000f014, (_val), (_mask)) 8445 8446 /* Micro-controller code-ram crc Register: 00000000*/ 8447 #define READ_WC40_UC_INFO_B1_CRCr(_unit, _pc, _val) \ 8448 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000f015, (_val)) 8449 #define WRITE_WC40_UC_INFO_B1_CRCr(_unit, _pc, _val) \ 8450 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000f015, (_val)) 8451 #define MODIFY_WC40_UC_INFO_B1_CRCr(_unit, _pc, _val, _mask) \ 8452 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000f015, (_val), (_mask)) 8453 8454 /* TSC_12 Micro-controller TIMER CONTROLS: 00000000*/ 8455 #define READ_WC40_UC_INFO_B1_TSC_12_TIMER_CONTROLr(_unit, _pc, _val) \ 8456 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000f016, (_val)) 8457 #define WRITE_WC40_UC_INFO_B1_TSC_12_TIMER_CONTROLr(_unit, _pc, _val) \ 8458 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000f016, (_val)) 8459 #define MODIFY_WC40_UC_INFO_B1_TSC_12_TIMER_CONTROLr(_unit, _pc, _val, _mask) \ 8460 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000f016, (_val), (_mask)) 8461 8462 8463 8464 /**************************************************************************** 8465 * TSC_WC4_TSC_USERX_uC 8466 */ 8467 /* ramWord Register: 00000000*/ 8468 #define READ_WC40_UC_RAMWORDr(_unit, _pc, _val) \ 8469 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffc0, (_val)) 8470 #define WRITE_WC40_UC_RAMWORDr(_unit, _pc, _val) \ 8471 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc0, (_val)) 8472 #define MODIFY_WC40_UC_RAMWORDr(_unit, _pc, _val, _mask) \ 8473 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc0, (_val), (_mask)) 8474 8475 /* Adress Register: 00000000*/ 8476 #define READ_WC40_UC_ADDRESSr(_unit, _pc, _val) \ 8477 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffc1, (_val)) 8478 #define WRITE_WC40_UC_ADDRESSr(_unit, _pc, _val) \ 8479 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc1, (_val)) 8480 #define MODIFY_WC40_UC_ADDRESSr(_unit, _pc, _val, _mask) \ 8481 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc1, (_val), (_mask)) 8482 8483 /* Command Register: 00000000*/ 8484 #define READ_WC40_UC_COMMANDr(_unit, _pc, _val) \ 8485 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffc2, (_val)) 8486 #define WRITE_WC40_UC_COMMANDr(_unit, _pc, _val) \ 8487 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc2, (_val)) 8488 #define MODIFY_WC40_UC_COMMANDr(_unit, _pc, _val, _mask) \ 8489 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc2, (_val), (_mask)) 8490 8491 /* Write Data Register: 00000000*/ 8492 #define READ_WC40_UC_WRDATAr(_unit, _pc, _val) \ 8493 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffc3, (_val)) 8494 #define WRITE_WC40_UC_WRDATAr(_unit, _pc, _val) \ 8495 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc3, (_val)) 8496 #define MODIFY_WC40_UC_WRDATAr(_unit, _pc, _val, _mask) \ 8497 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc3, (_val), (_mask)) 8498 8499 /* Read Data Register: 00000000*/ 8500 #define READ_WC40_UC_RDDATAr(_unit, _pc, _val) \ 8501 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffc4, (_val)) 8502 #define WRITE_WC40_UC_RDDATAr(_unit, _pc, _val) \ 8503 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc4, (_val)) 8504 #define MODIFY_WC40_UC_RDDATAr(_unit, _pc, _val, _mask) \ 8505 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc4, (_val), (_mask)) 8506 8507 /* MDIO to 8051 FSM Status Register: 00000000*/ 8508 #define READ_WC40_UC_DOWNLOAD_STATUSr(_unit, _pc, _val) \ 8509 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffc5, (_val)) 8510 #define WRITE_WC40_UC_DOWNLOAD_STATUSr(_unit, _pc, _val) \ 8511 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc5, (_val)) 8512 #define MODIFY_WC40_UC_DOWNLOAD_STATUSr(_unit, _pc, _val, _mask) \ 8513 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc5, (_val), (_mask)) 8514 8515 /* 8051 SFR FSM status: 00000000*/ 8516 #define READ_WC40_UC_SFR_STATUSr(_unit, _pc, _val) \ 8517 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffc6, (_val)) 8518 #define WRITE_WC40_UC_SFR_STATUSr(_unit, _pc, _val) \ 8519 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc6, (_val)) 8520 #define MODIFY_WC40_UC_SFR_STATUSr(_unit, _pc, _val, _mask) \ 8521 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc6, (_val), (_mask)) 8522 8523 /* Command Register 4: 00000000*/ 8524 #define READ_WC40_UC_COMMAND4r(_unit, _pc, _val) \ 8525 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffc7, (_val)) 8526 #define WRITE_WC40_UC_COMMAND4r(_unit, _pc, _val) \ 8527 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc7, (_val)) 8528 #define MODIFY_WC40_UC_COMMAND4r(_unit, _pc, _val, _mask) \ 8529 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc7, (_val), (_mask)) 8530 8531 /* External station to uC mailbox: 00000000*/ 8532 #define READ_WC40_UC_MDIO_UC_MAILBOXr(_unit, _pc, _val) \ 8533 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffc8, (_val)) 8534 #define WRITE_WC40_UC_MDIO_UC_MAILBOXr(_unit, _pc, _val) \ 8535 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc8, (_val)) 8536 #define MODIFY_WC40_UC_MDIO_UC_MAILBOXr(_unit, _pc, _val, _mask) \ 8537 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc8, (_val), (_mask)) 8538 8539 /* uC to external station mailbox: 00000000*/ 8540 #define READ_WC40_UC_UC_MDIO_MAILBOXr(_unit, _pc, _val) \ 8541 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffc9, (_val)) 8542 #define WRITE_WC40_UC_UC_MDIO_MAILBOXr(_unit, _pc, _val) \ 8543 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffc9, (_val)) 8544 #define MODIFY_WC40_UC_UC_MDIO_MAILBOXr(_unit, _pc, _val, _mask) \ 8545 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffc9, (_val), (_mask)) 8546 8547 /* Command Register 2: 00000000*/ 8548 #define READ_WC40_UC_COMMAND2r(_unit, _pc, _val) \ 8549 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffca, (_val)) 8550 #define WRITE_WC40_UC_COMMAND2r(_unit, _pc, _val) \ 8551 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffca, (_val)) 8552 #define MODIFY_WC40_UC_COMMAND2r(_unit, _pc, _val, _mask) \ 8553 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffca, (_val), (_mask)) 8554 8555 /* wdog_evnt_cnt Register: 00000000*/ 8556 #define READ_WC40_UC_WDOG_EVNT_CNTr(_unit, _pc, _val) \ 8557 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffcb, (_val)) 8558 #define WRITE_WC40_UC_WDOG_EVNT_CNTr(_unit, _pc, _val) \ 8559 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffcb, (_val)) 8560 #define MODIFY_WC40_UC_WDOG_EVNT_CNTr(_unit, _pc, _val, _mask) \ 8561 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffcb, (_val), (_mask)) 8562 8563 /* Command Register 3: 00000000*/ 8564 #define READ_WC40_UC_COMMAND3r(_unit, _pc, _val) \ 8565 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffcc, (_val)) 8566 #define WRITE_WC40_UC_COMMAND3r(_unit, _pc, _val) \ 8567 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffcc, (_val)) 8568 #define MODIFY_WC40_UC_COMMAND3r(_unit, _pc, _val, _mask) \ 8569 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffcc, (_val), (_mask)) 8570 8571 /* Muxed Micro Timer (lower timer[15:0]): 00000000*/ 8572 #define READ_WC40_UC_TIMER_LOWER16r(_unit, _pc, _val) \ 8573 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffcd, (_val)) 8574 #define WRITE_WC40_UC_TIMER_LOWER16r(_unit, _pc, _val) \ 8575 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffcd, (_val)) 8576 #define MODIFY_WC40_UC_TIMER_LOWER16r(_unit, _pc, _val, _mask) \ 8577 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffcd, (_val), (_mask)) 8578 8579 /* Muxed Micro Timer (upper timer[31:16]): 00000000*/ 8580 #define READ_WC40_UC_TIMER_UPPER16r(_unit, _pc, _val) \ 8581 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffce, (_val)) 8582 #define WRITE_WC40_UC_TIMER_UPPER16r(_unit, _pc, _val) \ 8583 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffce, (_val)) 8584 #define MODIFY_WC40_UC_TIMER_UPPER16r(_unit, _pc, _val, _mask) \ 8585 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffce, (_val), (_mask)) 8586 8587 8588 8589 /**************************************************************************** 8590 * TSC_WC4_TSC_USERX_AER 8591 */ 8592 /* Address Expansion Register: 00000000*/ 8593 #define READ_WC40_AER_ADDRESSEXPANSIONr(_unit, _pc, _val) \ 8594 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffde, (_val)) 8595 #define WRITE_WC40_AER_ADDRESSEXPANSIONr(_unit, _pc, _val) \ 8596 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffde, (_val)) 8597 #define MODIFY_WC40_AER_ADDRESSEXPANSIONr(_unit, _pc, _val, _mask) \ 8598 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffde, (_val), (_mask)) 8599 8600 8601 8602 /**************************************************************************** 8603 * TSC_WC4_TSC_USERX_Combo_IEEE 8604 */ 8605 /* IEEE phyID2 Register: 00000000*/ 8606 #define READ_WC40_COMBO_IEEE_PHYID2r(_unit, _pc, _val) \ 8607 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffe2, (_val)) 8608 #define WRITE_WC40_COMBO_IEEE_PHYID2r(_unit, _pc, _val) \ 8609 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe2, (_val)) 8610 #define MODIFY_WC40_COMBO_IEEE_PHYID2r(_unit, _pc, _val, _mask) \ 8611 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe2, (_val), (_mask)) 8612 8613 /* IEEE phyID3 Register: 00000000*/ 8614 #define READ_WC40_COMBO_IEEE_PHYID3r(_unit, _pc, _val) \ 8615 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffe3, (_val)) 8616 #define WRITE_WC40_COMBO_IEEE_PHYID3r(_unit, _pc, _val) \ 8617 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe3, (_val)) 8618 #define MODIFY_WC40_COMBO_IEEE_PHYID3r(_unit, _pc, _val, _mask) \ 8619 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe3, (_val), (_mask)) 8620 8621 /* IEEE MMD Access Control Register: 00000000*/ 8622 #define READ_WC40_COMBO_IEEE_MMDACCESSCONTROLr(_unit, _pc, _val) \ 8623 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffed, (_val)) 8624 #define WRITE_WC40_COMBO_IEEE_MMDACCESSCONTROLr(_unit, _pc, _val) \ 8625 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffed, (_val)) 8626 #define MODIFY_WC40_COMBO_IEEE_MMDACCESSCONTROLr(_unit, _pc, _val, _mask) \ 8627 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffed, (_val), (_mask)) 8628 8629 /* IEEE MMD Address Data Register: 00000000*/ 8630 #define READ_WC40_COMBO_IEEE_MMDACCESSADDRESSDATAr(_unit, _pc, _val) \ 8631 TSC_REG_READ((_unit), (_pc), 0x00, 0x0000ffee, (_val)) 8632 #define WRITE_WC40_COMBO_IEEE_MMDACCESSADDRESSDATAr(_unit, _pc, _val) \ 8633 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffee, (_val)) 8634 #define MODIFY_WC40_COMBO_IEEE_MMDACCESSADDRESSDATAr(_unit, _pc, _val, _mask) \ 8635 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffee, (_val), (_mask)) 8636 8637 8638 8639 /**************************************************************************** 8640 * TSC_IEEE_PMA_PMD_dev1_ieee0 8641 */ 8642 /* AN Device ID [15:0]: 00000000*/ 8643 #define READ_WC40_DEV1_IEEE0_AN_IEEEID1r(_unit, _pc, _val) \ 8644 TSC_REG_READ((_unit), (_pc), 0x00, 0x08000002, (_val)) 8645 #define WRITE_WC40_DEV1_IEEE0_AN_IEEEID1r(_unit, _pc, _val) \ 8646 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x08000002, (_val)) 8647 #define MODIFY_WC40_DEV1_IEEE0_AN_IEEEID1r(_unit, _pc, _val, _mask) \ 8648 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x08000002, (_val), (_mask)) 8649 8650 /* AN Device ID [31:16]: 00000000*/ 8651 #define READ_WC40_DEV1_IEEE0_AN_IEEEID2r(_unit, _pc, _val) \ 8652 TSC_REG_READ((_unit), (_pc), 0x00, 0x08000003, (_val)) 8653 #define WRITE_WC40_DEV1_IEEE0_AN_IEEEID2r(_unit, _pc, _val) \ 8654 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x08000003, (_val)) 8655 #define MODIFY_WC40_DEV1_IEEE0_AN_IEEEID2r(_unit, _pc, _val, _mask) \ 8656 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x08000003, (_val), (_mask)) 8657 8658 8659 8660 /**************************************************************************** 8661 * TSC_IEEE_PMA_PMD_dev1_ieee9 8662 */ 8663 /* TenGBASE_KR PMD control register 150: 00000000*/ 8664 #define READ_WC40_DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150r(_unit, _pc, _val) \ 8665 TSC_REG_READ((_unit), (_pc), 0x00, 0x08000096, (_val)) 8666 #define WRITE_WC40_DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150r(_unit, _pc, _val) \ 8667 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x08000096, (_val)) 8668 #define MODIFY_WC40_DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150r(_unit, _pc, _val, _mask) \ 8669 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x08000096, (_val), (_mask)) 8670 8671 /* TenGBASE_KR PMD status register 151: 00000000*/ 8672 #define READ_WC40_DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151r(_unit, _pc, _val) \ 8673 TSC_REG_READ((_unit), (_pc), 0x00, 0x08000097, (_val)) 8674 #define WRITE_WC40_DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151r(_unit, _pc, _val) \ 8675 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x08000097, (_val)) 8676 #define MODIFY_WC40_DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151r(_unit, _pc, _val, _mask) \ 8677 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x08000097, (_val), (_mask)) 8678 8679 8680 8681 /**************************************************************************** 8682 * TSC_IEEE_PMA_PMD_dev1_ieee10 8683 */ 8684 /* "FEC corrected blocks counter [15:0]": 00000000*/ 8685 #define READ_WC40_DEV1_IEEE10_PMD_CORRECTEDBLKSLr(_unit, _pc, _val) \ 8686 TSC_REG_READ((_unit), (_pc), 0x00, 0x080000ac, (_val)) 8687 #define WRITE_WC40_DEV1_IEEE10_PMD_CORRECTEDBLKSLr(_unit, _pc, _val) \ 8688 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x080000ac, (_val)) 8689 #define MODIFY_WC40_DEV1_IEEE10_PMD_CORRECTEDBLKSLr(_unit, _pc, _val, _mask) \ 8690 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x080000ac, (_val), (_mask)) 8691 8692 /* "FEC corrected blocks counter [31:16]": 00000000*/ 8693 #define READ_WC40_DEV1_IEEE10_PMD_CORRECTEDBLKSHr(_unit, _pc, _val) \ 8694 TSC_REG_READ((_unit), (_pc), 0x00, 0x080000ad, (_val)) 8695 #define WRITE_WC40_DEV1_IEEE10_PMD_CORRECTEDBLKSHr(_unit, _pc, _val) \ 8696 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x080000ad, (_val)) 8697 #define MODIFY_WC40_DEV1_IEEE10_PMD_CORRECTEDBLKSHr(_unit, _pc, _val, _mask) \ 8698 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x080000ad, (_val), (_mask)) 8699 8700 /* "FEC uncorrected blocks counter [15:0]": 00000000*/ 8701 #define READ_WC40_DEV1_IEEE10_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _val) \ 8702 TSC_REG_READ((_unit), (_pc), 0x00, 0x080000ae, (_val)) 8703 #define WRITE_WC40_DEV1_IEEE10_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _val) \ 8704 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x080000ae, (_val)) 8705 #define MODIFY_WC40_DEV1_IEEE10_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _val, _mask) \ 8706 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x080000ae, (_val), (_mask)) 8707 8708 /* "FEC uncorrected blocks counter [31:16]": 00000000*/ 8709 #define READ_WC40_DEV1_IEEE10_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _val) \ 8710 TSC_REG_READ((_unit), (_pc), 0x00, 0x080000af, (_val)) 8711 #define WRITE_WC40_DEV1_IEEE10_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _val) \ 8712 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x080000af, (_val)) 8713 #define MODIFY_WC40_DEV1_IEEE10_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _val, _mask) \ 8714 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x080000af, (_val), (_mask)) 8715 8716 8717 8718 /**************************************************************************** 8719 * TSC_IEEE_PMA_PMD_dev1_ieee10_tsc_12 8720 */ 8721 /* "FEC ability register": 00000000*/ 8722 #define READ_WC40_DEV1_IEEE10_TSC_12_PMD_FECABILITYr(_unit, _pc, _val) \ 8723 TSC_REG_READ((_unit), (_pc), 0x00, 0x080000ba, (_val)) 8724 #define WRITE_WC40_DEV1_IEEE10_TSC_12_PMD_FECABILITYr(_unit, _pc, _val) \ 8725 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x080000ba, (_val)) 8726 #define MODIFY_WC40_DEV1_IEEE10_TSC_12_PMD_FECABILITYr(_unit, _pc, _val, _mask) \ 8727 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x080000ba, (_val), (_mask)) 8728 8729 /* "FEC control register": 00000000*/ 8730 #define READ_WC40_DEV1_IEEE10_TSC_12_PMD_FECCONTROLr(_unit, _pc, _val) \ 8731 TSC_REG_READ((_unit), (_pc), 0x00, 0x080000bb, (_val)) 8732 #define WRITE_WC40_DEV1_IEEE10_TSC_12_PMD_FECCONTROLr(_unit, _pc, _val) \ 8733 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x080000bb, (_val)) 8734 #define MODIFY_WC40_DEV1_IEEE10_TSC_12_PMD_FECCONTROLr(_unit, _pc, _val, _mask) \ 8735 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x080000bb, (_val), (_mask)) 8736 8737 /* "FEC corrected blocks counter [15:0]": 00000000*/ 8738 #define READ_WC40_DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSLr(_unit, _pc, _val) \ 8739 TSC_REG_READ((_unit), (_pc), 0x00, 0x080000bc, (_val)) 8740 #define WRITE_WC40_DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSLr(_unit, _pc, _val) \ 8741 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x080000bc, (_val)) 8742 #define MODIFY_WC40_DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSLr(_unit, _pc, _val, _mask) \ 8743 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x080000bc, (_val), (_mask)) 8744 8745 /* "FEC corrected blocks counter [31:16]": 00000000*/ 8746 #define READ_WC40_DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSHr(_unit, _pc, _val) \ 8747 TSC_REG_READ((_unit), (_pc), 0x00, 0x080000bd, (_val)) 8748 #define WRITE_WC40_DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSHr(_unit, _pc, _val) \ 8749 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x080000bd, (_val)) 8750 #define MODIFY_WC40_DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSHr(_unit, _pc, _val, _mask) \ 8751 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x080000bd, (_val), (_mask)) 8752 8753 /* "FEC uncorrected blocks counter [15:0]": 00000000*/ 8754 #define READ_WC40_DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _val) \ 8755 TSC_REG_READ((_unit), (_pc), 0x00, 0x080000be, (_val)) 8756 #define WRITE_WC40_DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _val) \ 8757 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x080000be, (_val)) 8758 #define MODIFY_WC40_DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSLr(_unit, _pc, _val, _mask) \ 8759 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x080000be, (_val), (_mask)) 8760 8761 /* "FEC uncorrected blocks counter [31:16]": 00000000*/ 8762 #define READ_WC40_DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _val) \ 8763 TSC_REG_READ((_unit), (_pc), 0x00, 0x080000bf, (_val)) 8764 #define WRITE_WC40_DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _val) \ 8765 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x080000bf, (_val)) 8766 #define MODIFY_WC40_DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSHr(_unit, _pc, _val, _mask) \ 8767 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x080000bf, (_val), (_mask)) 8768 8769 8770 8771 /**************************************************************************** 8772 * TSC_IEEE_PCS_dev3_ieee2 8773 */ 8774 /* 40G/100GBASE-R Errored blocks high order counter: 00000000*/ 8775 #define READ_WC40_DEV3_IEEE2_PCS_ERRORED_BLOCKS_HOr(_unit, _pc, _val) \ 8776 TSC_REG_READ((_unit), (_pc), 0x00, 0x1800002d, (_val)) 8777 #define WRITE_WC40_DEV3_IEEE2_PCS_ERRORED_BLOCKS_HOr(_unit, _pc, _val) \ 8778 TSC_REG_WRITE((_unit), (_pc), 0x00, 0x1800002d, (_val)) 8779 #define MODIFY_WC40_DEV3_IEEE2_PCS_ERRORED_BLOCKS_HOr(_unit, _pc, _val, _mask) \ 8780 TSC_REG_MODIFY((_unit), (_pc), 0x00, 0x1800002d, (_val), (_mask)) 8781 8782 8783 8784 /**************************************************************************** 8785 * TSC_IEEE_CL22_CL22_B0 8786 */ 8787 /**************************************************************************** 8788 * CL22_B0 :: phyid2 8789 */ 8790 /* CL22_B0 :: phyid2 :: regid1 [15:00] */ 8791 #define CL22_B0_PHYID2_REGID1_MASK 0xffff 8792 #define CL22_B0_PHYID2_REGID1_ALIGN 0 8793 #define CL22_B0_PHYID2_REGID1_BITS 16 8794 #define CL22_B0_PHYID2_REGID1_SHIFT 0 8795 8796 8797 /**************************************************************************** 8798 * CL22_B0 :: phyid3 8799 */ 8800 /* CL22_B0 :: phyid3 :: regid2 [15:00] */ 8801 #define CL22_B0_PHYID3_REGID2_MASK 0xffff 8802 #define CL22_B0_PHYID3_REGID2_ALIGN 0 8803 #define CL22_B0_PHYID3_REGID2_BITS 16 8804 #define CL22_B0_PHYID3_REGID2_SHIFT 0 8805 8806 8807 /**************************************************************************** 8808 * CL22_B0 :: MMDAccessControl 8809 */ 8810 /* CL22_B0 :: MMDAccessControl :: increment_control [15:14] */ 8811 #define CL22_B0_MMDACCESSCONTROL_INCREMENT_CONTROL_MASK 0xc000 8812 #define CL22_B0_MMDACCESSCONTROL_INCREMENT_CONTROL_ALIGN 0 8813 #define CL22_B0_MMDACCESSCONTROL_INCREMENT_CONTROL_BITS 2 8814 #define CL22_B0_MMDACCESSCONTROL_INCREMENT_CONTROL_SHIFT 14 8815 8816 /* CL22_B0 :: MMDAccessControl :: reserved0 [13:05] */ 8817 #define CL22_B0_MMDACCESSCONTROL_RESERVED0_MASK 0x3fe0 8818 #define CL22_B0_MMDACCESSCONTROL_RESERVED0_ALIGN 0 8819 #define CL22_B0_MMDACCESSCONTROL_RESERVED0_BITS 9 8820 #define CL22_B0_MMDACCESSCONTROL_RESERVED0_SHIFT 5 8821 8822 /* CL22_B0 :: MMDAccessControl :: DEVAD [04:00] */ 8823 #define CL22_B0_MMDACCESSCONTROL_DEVAD_MASK 0x001f 8824 #define CL22_B0_MMDACCESSCONTROL_DEVAD_ALIGN 0 8825 #define CL22_B0_MMDACCESSCONTROL_DEVAD_BITS 5 8826 #define CL22_B0_MMDACCESSCONTROL_DEVAD_SHIFT 0 8827 8828 8829 /**************************************************************************** 8830 * CL22_B0 :: MMDAccessAddressData 8831 */ 8832 /* CL22_B0 :: MMDAccessAddressData :: AddressData [15:00] */ 8833 #define CL22_B0_MMDACCESSADDRESSDATA_ADDRESSDATA_MASK 0xffff 8834 #define CL22_B0_MMDACCESSADDRESSDATA_ADDRESSDATA_ALIGN 0 8835 #define CL22_B0_MMDACCESSADDRESSDATA_ADDRESSDATA_BITS 16 8836 #define CL22_B0_MMDACCESSADDRESSDATA_ADDRESSDATA_SHIFT 0 8837 8838 8839 /**************************************************************************** 8840 * TSC_IEEE_CL22_CL22_B1 8841 */ 8842 /**************************************************************************** 8843 * CL22_B1 :: BlkAdr 8844 */ 8845 /* CL22_B1 :: BlkAdr :: BlkAdr [15:00] */ 8846 #define CL22_B1_BLKADR_BLKADR_MASK 0xffff 8847 #define CL22_B1_BLKADR_BLKADR_ALIGN 0 8848 #define CL22_B1_BLKADR_BLKADR_BITS 16 8849 #define CL22_B1_BLKADR_BLKADR_SHIFT 0 8850 8851 8852 /**************************************************************************** 8853 * TSC_WC4_TSC_USER1_Main0 8854 */ 8855 /**************************************************************************** 8856 * Main0 :: setup 8857 */ 8858 /* Main0 :: setup :: refclk_sel [15:13] */ 8859 #define MAIN0_SETUP_REFCLK_SEL_MASK 0xe000 8860 #define MAIN0_SETUP_REFCLK_SEL_ALIGN 0 8861 #define MAIN0_SETUP_REFCLK_SEL_BITS 3 8862 #define MAIN0_SETUP_REFCLK_SEL_SHIFT 13 8863 #define MAIN0_SETUP_REFCLK_SEL_clk_25MHz 0 8864 #define MAIN0_SETUP_REFCLK_SEL_clk_100MHz 1 8865 #define MAIN0_SETUP_REFCLK_SEL_clk_125MHz 2 8866 #define MAIN0_SETUP_REFCLK_SEL_clk_156p25MHz 3 8867 #define MAIN0_SETUP_REFCLK_SEL_clk_187p5MHz 4 8868 #define MAIN0_SETUP_REFCLK_SEL_clk_161p25Mhz 5 8869 #define MAIN0_SETUP_REFCLK_SEL_clk_50Mhz 6 8870 #define MAIN0_SETUP_REFCLK_SEL_clk_106p25Mhz 7 8871 8872 /* Main0 :: setup :: force_pll_mode_afe_sel [12:12] */ 8873 #define MAIN0_SETUP_FORCE_PLL_MODE_AFE_SEL_MASK 0x1000 8874 #define MAIN0_SETUP_FORCE_PLL_MODE_AFE_SEL_ALIGN 0 8875 #define MAIN0_SETUP_FORCE_PLL_MODE_AFE_SEL_BITS 1 8876 #define MAIN0_SETUP_FORCE_PLL_MODE_AFE_SEL_SHIFT 12 8877 8878 /* Main0 :: setup :: default_pll_mode_afe [11:08] */ 8879 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_MASK 0x0f00 8880 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_ALIGN 0 8881 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_BITS 4 8882 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_SHIFT 8 8883 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div32 0 8884 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div36 1 8885 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div40 2 8886 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div42 3 8887 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div48 4 8888 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div50 5 8889 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div52 6 8890 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div54 7 8891 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div60 8 8892 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div64 9 8893 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div66 10 8894 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div68 11 8895 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div70 12 8896 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div80 13 8897 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div92 14 8898 #define MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div100 15 8899 8900 /* Main0 :: setup :: start_sequencer [07:07] */ 8901 #define MAIN0_SETUP_START_SEQUENCER_MASK 0x0080 8902 #define MAIN0_SETUP_START_SEQUENCER_ALIGN 0 8903 #define MAIN0_SETUP_START_SEQUENCER_BITS 1 8904 #define MAIN0_SETUP_START_SEQUENCER_SHIFT 7 8905 8906 /* Main0 :: setup :: port_mode_sel [06:04] */ 8907 #define MAIN0_SETUP_PORT_MODE_SEL_MASK 0x0070 8908 #define MAIN0_SETUP_PORT_MODE_SEL_ALIGN 0 8909 #define MAIN0_SETUP_PORT_MODE_SEL_BITS 3 8910 #define MAIN0_SETUP_PORT_MODE_SEL_SHIFT 4 8911 8912 /* Main0 :: setup :: single_port_mode [03:03] */ 8913 #define MAIN0_SETUP_SINGLE_PORT_MODE_MASK 0x0008 8914 #define MAIN0_SETUP_SINGLE_PORT_MODE_ALIGN 0 8915 #define MAIN0_SETUP_SINGLE_PORT_MODE_BITS 1 8916 #define MAIN0_SETUP_SINGLE_PORT_MODE_SHIFT 3 8917 8918 /* Main0 :: setup :: stand_alone_mode [02:02] */ 8919 #define MAIN0_SETUP_STAND_ALONE_MODE_MASK 0x0004 8920 #define MAIN0_SETUP_STAND_ALONE_MODE_ALIGN 0 8921 #define MAIN0_SETUP_STAND_ALONE_MODE_BITS 1 8922 #define MAIN0_SETUP_STAND_ALONE_MODE_SHIFT 2 8923 8924 /* Main0 :: setup :: reserved0 [01:00] */ 8925 #define MAIN0_SETUP_RESERVED0_MASK 0x0003 8926 #define MAIN0_SETUP_RESERVED0_ALIGN 0 8927 #define MAIN0_SETUP_RESERVED0_BITS 2 8928 #define MAIN0_SETUP_RESERVED0_SHIFT 0 8929 8930 8931 /**************************************************************************** 8932 * Main0 :: reset 8933 */ 8934 /* Main0 :: reset :: rx_reset_analog [15:12] */ 8935 #define MAIN0_RESET_RX_RESET_ANALOG_MASK 0xf000 8936 #define MAIN0_RESET_RX_RESET_ANALOG_ALIGN 0 8937 #define MAIN0_RESET_RX_RESET_ANALOG_BITS 4 8938 #define MAIN0_RESET_RX_RESET_ANALOG_SHIFT 12 8939 8940 /* Main0 :: reset :: tx_reset_analog [11:08] */ 8941 #define MAIN0_RESET_TX_RESET_ANALOG_MASK 0x0f00 8942 #define MAIN0_RESET_TX_RESET_ANALOG_ALIGN 0 8943 #define MAIN0_RESET_TX_RESET_ANALOG_BITS 4 8944 #define MAIN0_RESET_TX_RESET_ANALOG_SHIFT 8 8945 8946 /* Main0 :: reset :: reset_pll [07:07] */ 8947 #define MAIN0_RESET_RESET_PLL_MASK 0x0080 8948 #define MAIN0_RESET_RESET_PLL_ALIGN 0 8949 #define MAIN0_RESET_RESET_PLL_BITS 1 8950 #define MAIN0_RESET_RESET_PLL_SHIFT 7 8951 8952 /* Main0 :: reset :: pll_bypass [06:06] */ 8953 #define MAIN0_RESET_PLL_BYPASS_MASK 0x0040 8954 #define MAIN0_RESET_PLL_BYPASS_ALIGN 0 8955 #define MAIN0_RESET_PLL_BYPASS_BITS 1 8956 #define MAIN0_RESET_PLL_BYPASS_SHIFT 6 8957 8958 /* Main0 :: reset :: rx_DSC_reset [05:02] */ 8959 #define MAIN0_RESET_RX_DSC_RESET_MASK 0x003c 8960 #define MAIN0_RESET_RX_DSC_RESET_ALIGN 0 8961 #define MAIN0_RESET_RX_DSC_RESET_BITS 4 8962 #define MAIN0_RESET_RX_DSC_RESET_SHIFT 2 8963 8964 /* Main0 :: reset :: reserved0 [01:00] */ 8965 #define MAIN0_RESET_RESERVED0_MASK 0x0003 8966 #define MAIN0_RESET_RESERVED0_ALIGN 0 8967 #define MAIN0_RESET_RESERVED0_BITS 2 8968 #define MAIN0_RESET_RESERVED0_SHIFT 0 8969 8970 8971 /**************************************************************************** 8972 * Main0 :: power 8973 */ 8974 /* Main0 :: power :: rx_pwrdwn_analog [15:12] */ 8975 #define MAIN0_POWER_RX_PWRDWN_ANALOG_MASK 0xf000 8976 #define MAIN0_POWER_RX_PWRDWN_ANALOG_ALIGN 0 8977 #define MAIN0_POWER_RX_PWRDWN_ANALOG_BITS 4 8978 #define MAIN0_POWER_RX_PWRDWN_ANALOG_SHIFT 12 8979 8980 /* Main0 :: power :: tx_pwrdwn_analog [11:08] */ 8981 #define MAIN0_POWER_TX_PWRDWN_ANALOG_MASK 0x0f00 8982 #define MAIN0_POWER_TX_PWRDWN_ANALOG_ALIGN 0 8983 #define MAIN0_POWER_TX_PWRDWN_ANALOG_BITS 4 8984 #define MAIN0_POWER_TX_PWRDWN_ANALOG_SHIFT 8 8985 8986 /* Main0 :: power :: pwrdwn_pll [07:07] */ 8987 #define MAIN0_POWER_PWRDWN_PLL_MASK 0x0080 8988 #define MAIN0_POWER_PWRDWN_PLL_ALIGN 0 8989 #define MAIN0_POWER_PWRDWN_PLL_BITS 1 8990 #define MAIN0_POWER_PWRDWN_PLL_SHIFT 7 8991 8992 /* Main0 :: power :: tx_lowpwr_6g_over_val [06:06] */ 8993 #define MAIN0_POWER_TX_LOWPWR_6G_OVER_VAL_MASK 0x0040 8994 #define MAIN0_POWER_TX_LOWPWR_6G_OVER_VAL_ALIGN 0 8995 #define MAIN0_POWER_TX_LOWPWR_6G_OVER_VAL_BITS 1 8996 #define MAIN0_POWER_TX_LOWPWR_6G_OVER_VAL_SHIFT 6 8997 8998 /* Main0 :: power :: tx_lowpwr_6g_override_enable [05:05] */ 8999 #define MAIN0_POWER_TX_LOWPWR_6G_OVERRIDE_ENABLE_MASK 0x0020 9000 #define MAIN0_POWER_TX_LOWPWR_6G_OVERRIDE_ENABLE_ALIGN 0 9001 #define MAIN0_POWER_TX_LOWPWR_6G_OVERRIDE_ENABLE_BITS 1 9002 #define MAIN0_POWER_TX_LOWPWR_6G_OVERRIDE_ENABLE_SHIFT 5 9003 9004 /* Main0 :: power :: power_on_timer_enable [04:04] */ 9005 #define MAIN0_POWER_POWER_ON_TIMER_ENABLE_MASK 0x0010 9006 #define MAIN0_POWER_POWER_ON_TIMER_ENABLE_ALIGN 0 9007 #define MAIN0_POWER_POWER_ON_TIMER_ENABLE_BITS 1 9008 #define MAIN0_POWER_POWER_ON_TIMER_ENABLE_SHIFT 4 9009 9010 /* Main0 :: power :: reserved0 [03:00] */ 9011 #define MAIN0_POWER_RESERVED0_MASK 0x000f 9012 #define MAIN0_POWER_RESERVED0_ALIGN 0 9013 #define MAIN0_POWER_RESERVED0_BITS 4 9014 #define MAIN0_POWER_RESERVED0_SHIFT 0 9015 9016 9017 /**************************************************************************** 9018 * Main0 :: lane_swap 9019 */ 9020 /* Main0 :: lane_swap :: rx3_lnswap_sel [15:14] */ 9021 #define MAIN0_LANE_SWAP_RX3_LNSWAP_SEL_MASK 0xc000 9022 #define MAIN0_LANE_SWAP_RX3_LNSWAP_SEL_ALIGN 0 9023 #define MAIN0_LANE_SWAP_RX3_LNSWAP_SEL_BITS 2 9024 #define MAIN0_LANE_SWAP_RX3_LNSWAP_SEL_SHIFT 14 9025 9026 /* Main0 :: lane_swap :: rx2_lnswap_sel [13:12] */ 9027 #define MAIN0_LANE_SWAP_RX2_LNSWAP_SEL_MASK 0x3000 9028 #define MAIN0_LANE_SWAP_RX2_LNSWAP_SEL_ALIGN 0 9029 #define MAIN0_LANE_SWAP_RX2_LNSWAP_SEL_BITS 2 9030 #define MAIN0_LANE_SWAP_RX2_LNSWAP_SEL_SHIFT 12 9031 9032 /* Main0 :: lane_swap :: rx1_lnswap_sel [11:10] */ 9033 #define MAIN0_LANE_SWAP_RX1_LNSWAP_SEL_MASK 0x0c00 9034 #define MAIN0_LANE_SWAP_RX1_LNSWAP_SEL_ALIGN 0 9035 #define MAIN0_LANE_SWAP_RX1_LNSWAP_SEL_BITS 2 9036 #define MAIN0_LANE_SWAP_RX1_LNSWAP_SEL_SHIFT 10 9037 9038 /* Main0 :: lane_swap :: rx0_lnswap_sel [09:08] */ 9039 #define MAIN0_LANE_SWAP_RX0_LNSWAP_SEL_MASK 0x0300 9040 #define MAIN0_LANE_SWAP_RX0_LNSWAP_SEL_ALIGN 0 9041 #define MAIN0_LANE_SWAP_RX0_LNSWAP_SEL_BITS 2 9042 #define MAIN0_LANE_SWAP_RX0_LNSWAP_SEL_SHIFT 8 9043 9044 /* Main0 :: lane_swap :: tx3_lnswap_sel [07:06] */ 9045 #define MAIN0_LANE_SWAP_TX3_LNSWAP_SEL_MASK 0x00c0 9046 #define MAIN0_LANE_SWAP_TX3_LNSWAP_SEL_ALIGN 0 9047 #define MAIN0_LANE_SWAP_TX3_LNSWAP_SEL_BITS 2 9048 #define MAIN0_LANE_SWAP_TX3_LNSWAP_SEL_SHIFT 6 9049 9050 /* Main0 :: lane_swap :: tx2_lnswap_sel [05:04] */ 9051 #define MAIN0_LANE_SWAP_TX2_LNSWAP_SEL_MASK 0x0030 9052 #define MAIN0_LANE_SWAP_TX2_LNSWAP_SEL_ALIGN 0 9053 #define MAIN0_LANE_SWAP_TX2_LNSWAP_SEL_BITS 2 9054 #define MAIN0_LANE_SWAP_TX2_LNSWAP_SEL_SHIFT 4 9055 9056 /* Main0 :: lane_swap :: tx1_lnswap_sel [03:02] */ 9057 #define MAIN0_LANE_SWAP_TX1_LNSWAP_SEL_MASK 0x000c 9058 #define MAIN0_LANE_SWAP_TX1_LNSWAP_SEL_ALIGN 0 9059 #define MAIN0_LANE_SWAP_TX1_LNSWAP_SEL_BITS 2 9060 #define MAIN0_LANE_SWAP_TX1_LNSWAP_SEL_SHIFT 2 9061 9062 /* Main0 :: lane_swap :: tx0_lnswap_sel [01:00] */ 9063 #define MAIN0_LANE_SWAP_TX0_LNSWAP_SEL_MASK 0x0003 9064 #define MAIN0_LANE_SWAP_TX0_LNSWAP_SEL_ALIGN 0 9065 #define MAIN0_LANE_SWAP_TX0_LNSWAP_SEL_BITS 2 9066 #define MAIN0_LANE_SWAP_TX0_LNSWAP_SEL_SHIFT 0 9067 9068 9069 /**************************************************************************** 9070 * Main0 :: deviceInPkg5 9071 */ 9072 /* Main0 :: deviceInPkg5 :: reserved0 [15:08] */ 9073 #define MAIN0_DEVICEINPKG5_RESERVED0_MASK 0xff00 9074 #define MAIN0_DEVICEINPKG5_RESERVED0_ALIGN 0 9075 #define MAIN0_DEVICEINPKG5_RESERVED0_BITS 8 9076 #define MAIN0_DEVICEINPKG5_RESERVED0_SHIFT 8 9077 9078 /* Main0 :: deviceInPkg5 :: AN [07:07] */ 9079 #define MAIN0_DEVICEINPKG5_AN_MASK 0x0080 9080 #define MAIN0_DEVICEINPKG5_AN_ALIGN 0 9081 #define MAIN0_DEVICEINPKG5_AN_BITS 1 9082 #define MAIN0_DEVICEINPKG5_AN_SHIFT 7 9083 9084 /* Main0 :: deviceInPkg5 :: TC [06:06] */ 9085 #define MAIN0_DEVICEINPKG5_TC_MASK 0x0040 9086 #define MAIN0_DEVICEINPKG5_TC_ALIGN 0 9087 #define MAIN0_DEVICEINPKG5_TC_BITS 1 9088 #define MAIN0_DEVICEINPKG5_TC_SHIFT 6 9089 9090 /* Main0 :: deviceInPkg5 :: DTE_XS [05:05] */ 9091 #define MAIN0_DEVICEINPKG5_DTE_XS_MASK 0x0020 9092 #define MAIN0_DEVICEINPKG5_DTE_XS_ALIGN 0 9093 #define MAIN0_DEVICEINPKG5_DTE_XS_BITS 1 9094 #define MAIN0_DEVICEINPKG5_DTE_XS_SHIFT 5 9095 9096 /* Main0 :: deviceInPkg5 :: PHY_XS [04:04] */ 9097 #define MAIN0_DEVICEINPKG5_PHY_XS_MASK 0x0010 9098 #define MAIN0_DEVICEINPKG5_PHY_XS_ALIGN 0 9099 #define MAIN0_DEVICEINPKG5_PHY_XS_BITS 1 9100 #define MAIN0_DEVICEINPKG5_PHY_XS_SHIFT 4 9101 9102 /* Main0 :: deviceInPkg5 :: PCS_XS [03:03] */ 9103 #define MAIN0_DEVICEINPKG5_PCS_XS_MASK 0x0008 9104 #define MAIN0_DEVICEINPKG5_PCS_XS_ALIGN 0 9105 #define MAIN0_DEVICEINPKG5_PCS_XS_BITS 1 9106 #define MAIN0_DEVICEINPKG5_PCS_XS_SHIFT 3 9107 9108 /* Main0 :: deviceInPkg5 :: WIS [02:02] */ 9109 #define MAIN0_DEVICEINPKG5_WIS_MASK 0x0004 9110 #define MAIN0_DEVICEINPKG5_WIS_ALIGN 0 9111 #define MAIN0_DEVICEINPKG5_WIS_BITS 1 9112 #define MAIN0_DEVICEINPKG5_WIS_SHIFT 2 9113 9114 /* Main0 :: deviceInPkg5 :: PMA_PMD [01:01] */ 9115 #define MAIN0_DEVICEINPKG5_PMA_PMD_MASK 0x0002 9116 #define MAIN0_DEVICEINPKG5_PMA_PMD_ALIGN 0 9117 #define MAIN0_DEVICEINPKG5_PMA_PMD_BITS 1 9118 #define MAIN0_DEVICEINPKG5_PMA_PMD_SHIFT 1 9119 9120 /* Main0 :: deviceInPkg5 :: Clause22 [00:00] */ 9121 #define MAIN0_DEVICEINPKG5_CLAUSE22_MASK 0x0001 9122 #define MAIN0_DEVICEINPKG5_CLAUSE22_ALIGN 0 9123 #define MAIN0_DEVICEINPKG5_CLAUSE22_BITS 1 9124 #define MAIN0_DEVICEINPKG5_CLAUSE22_SHIFT 0 9125 9126 9127 /**************************************************************************** 9128 * Main0 :: misc 9129 */ 9130 /* Main0 :: misc :: reserved0 [15:12] */ 9131 #define MAIN0_MISC_RESERVED0_MASK 0xf000 9132 #define MAIN0_MISC_RESERVED0_ALIGN 0 9133 #define MAIN0_MISC_RESERVED0_BITS 4 9134 #define MAIN0_MISC_RESERVED0_SHIFT 12 9135 9136 /* Main0 :: misc :: cl49_low_latency_en [11:11] */ 9137 #define MAIN0_MISC_CL49_LOW_LATENCY_EN_MASK 0x0800 9138 #define MAIN0_MISC_CL49_LOW_LATENCY_EN_ALIGN 0 9139 #define MAIN0_MISC_CL49_LOW_LATENCY_EN_BITS 1 9140 #define MAIN0_MISC_CL49_LOW_LATENCY_EN_SHIFT 11 9141 9142 /* Main0 :: misc :: cl82_multi_pipe_mode [10:09] */ 9143 #define MAIN0_MISC_CL82_MULTI_PIPE_MODE_MASK 0x0600 9144 #define MAIN0_MISC_CL82_MULTI_PIPE_MODE_ALIGN 0 9145 #define MAIN0_MISC_CL82_MULTI_PIPE_MODE_BITS 2 9146 #define MAIN0_MISC_CL82_MULTI_PIPE_MODE_SHIFT 9 9147 9148 /* Main0 :: misc :: cl82_mld_phys_map [08:07] */ 9149 #define MAIN0_MISC_CL82_MLD_PHYS_MAP_MASK 0x0180 9150 #define MAIN0_MISC_CL82_MLD_PHYS_MAP_ALIGN 0 9151 #define MAIN0_MISC_CL82_MLD_PHYS_MAP_BITS 2 9152 #define MAIN0_MISC_CL82_MLD_PHYS_MAP_SHIFT 7 9153 9154 /* Main0 :: misc :: temp_sensor_resetb [06:06] */ 9155 #define MAIN0_MISC_TEMP_SENSOR_RESETB_MASK 0x0040 9156 #define MAIN0_MISC_TEMP_SENSOR_RESETB_ALIGN 0 9157 #define MAIN0_MISC_TEMP_SENSOR_RESETB_BITS 1 9158 #define MAIN0_MISC_TEMP_SENSOR_RESETB_SHIFT 6 9159 9160 /* Main0 :: misc :: temp_sensor_pwrdn [05:05] */ 9161 #define MAIN0_MISC_TEMP_SENSOR_PWRDN_MASK 0x0020 9162 #define MAIN0_MISC_TEMP_SENSOR_PWRDN_ALIGN 0 9163 #define MAIN0_MISC_TEMP_SENSOR_PWRDN_BITS 1 9164 #define MAIN0_MISC_TEMP_SENSOR_PWRDN_SHIFT 5 9165 9166 /* Main0 :: misc :: temp_sensor_bg_pwrdn [04:04] */ 9167 #define MAIN0_MISC_TEMP_SENSOR_BG_PWRDN_MASK 0x0010 9168 #define MAIN0_MISC_TEMP_SENSOR_BG_PWRDN_ALIGN 0 9169 #define MAIN0_MISC_TEMP_SENSOR_BG_PWRDN_BITS 1 9170 #define MAIN0_MISC_TEMP_SENSOR_BG_PWRDN_SHIFT 4 9171 9172 /* Main0 :: misc :: reserved1 [03:00] */ 9173 #define MAIN0_MISC_RESERVED1_MASK 0x000f 9174 #define MAIN0_MISC_RESERVED1_ALIGN 0 9175 #define MAIN0_MISC_RESERVED1_BITS 4 9176 #define MAIN0_MISC_RESERVED1_SHIFT 0 9177 9178 9179 /**************************************************************************** 9180 * Main0 :: temp_sensor 9181 */ 9182 /* Main0 :: temp_sensor :: temp_sensor_control [15:00] */ 9183 #define MAIN0_TEMP_SENSOR_TEMP_SENSOR_CONTROL_MASK 0xffff 9184 #define MAIN0_TEMP_SENSOR_TEMP_SENSOR_CONTROL_ALIGN 0 9185 #define MAIN0_TEMP_SENSOR_TEMP_SENSOR_CONTROL_BITS 16 9186 #define MAIN0_TEMP_SENSOR_TEMP_SENSOR_CONTROL_SHIFT 0 9187 9188 9189 /**************************************************************************** 9190 * Main0 :: tick_control_1 9191 */ 9192 /* Main0 :: tick_control_1 :: tick_override [15:15] */ 9193 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_MASK 0x8000 9194 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_ALIGN 0 9195 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_BITS 1 9196 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_SHIFT 15 9197 9198 /* Main0 :: tick_control_1 :: tick_numerator_upper [14:00] */ 9199 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_MASK 0x7fff 9200 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_ALIGN 0 9201 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_BITS 15 9202 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_SHIFT 0 9203 9204 9205 /**************************************************************************** 9206 * Main0 :: tick_control_0 9207 */ 9208 /* Main0 :: tick_control_0 :: tick_numerator_lower [15:12] */ 9209 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_MASK 0xf000 9210 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_ALIGN 0 9211 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_BITS 4 9212 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_SHIFT 12 9213 9214 /* Main0 :: tick_control_0 :: tick_denominator [11:02] */ 9215 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_MASK 0x0ffc 9216 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_ALIGN 0 9217 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_BITS 10 9218 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_SHIFT 2 9219 9220 /* Main0 :: tick_control_0 :: reserved0 [01:00] */ 9221 #define MAIN0_TICK_CONTROL_0_RESERVED0_MASK 0x0003 9222 #define MAIN0_TICK_CONTROL_0_RESERVED0_ALIGN 0 9223 #define MAIN0_TICK_CONTROL_0_RESERVED0_BITS 2 9224 #define MAIN0_TICK_CONTROL_0_RESERVED0_SHIFT 0 9225 9226 9227 /**************************************************************************** 9228 * Main0 :: loopback_control 9229 */ 9230 /* Main0 :: loopback_control :: remote_pcs_loopback_enable [15:12] */ 9231 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_MASK 0xf000 9232 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_ALIGN 0 9233 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_BITS 4 9234 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_SHIFT 12 9235 9236 /* Main0 :: loopback_control :: remote_pmd_loopback_enable [11:08] */ 9237 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PMD_LOOPBACK_ENABLE_MASK 0x0f00 9238 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PMD_LOOPBACK_ENABLE_ALIGN 0 9239 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PMD_LOOPBACK_ENABLE_BITS 4 9240 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PMD_LOOPBACK_ENABLE_SHIFT 8 9241 9242 /* Main0 :: loopback_control :: local_pcs_loopback_enable [07:04] */ 9243 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_MASK 0x00f0 9244 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_ALIGN 0 9245 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_BITS 4 9246 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_SHIFT 4 9247 9248 /* Main0 :: loopback_control :: reserved0 [03:00] */ 9249 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_MASK 0x000f 9250 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_ALIGN 0 9251 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_BITS 4 9252 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_SHIFT 0 9253 9254 9255 /**************************************************************************** 9256 * Main0 :: mdio_broadcast 9257 */ 9258 /* Main0 :: mdio_broadcast :: prtad_bcst [15:11] */ 9259 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_MASK 0xf800 9260 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_ALIGN 0 9261 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_BITS 5 9262 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_SHIFT 11 9263 9264 /* Main0 :: mdio_broadcast :: multiPRTs_en [10:07] */ 9265 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_MASK 0x0780 9266 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_ALIGN 0 9267 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_BITS 4 9268 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_SHIFT 7 9269 9270 /* Main0 :: mdio_broadcast :: reserved0 [06:00] */ 9271 #define MAIN0_MDIO_BROADCAST_RESERVED0_MASK 0x007f 9272 #define MAIN0_MDIO_BROADCAST_RESERVED0_ALIGN 0 9273 #define MAIN0_MDIO_BROADCAST_RESERVED0_BITS 7 9274 #define MAIN0_MDIO_BROADCAST_RESERVED0_SHIFT 0 9275 9276 9277 /**************************************************************************** 9278 * Main0 :: serdesID 9279 */ 9280 /* Main0 :: serdesID :: rev_letter [15:14] */ 9281 #define MAIN0_SERDESID_REV_LETTER_MASK 0xc000 9282 #define MAIN0_SERDESID_REV_LETTER_ALIGN 0 9283 #define MAIN0_SERDESID_REV_LETTER_BITS 2 9284 #define MAIN0_SERDESID_REV_LETTER_SHIFT 14 9285 9286 /* Main0 :: serdesID :: rev_number [13:11] */ 9287 #define MAIN0_SERDESID_REV_NUMBER_MASK 0x3800 9288 #define MAIN0_SERDESID_REV_NUMBER_ALIGN 0 9289 #define MAIN0_SERDESID_REV_NUMBER_BITS 3 9290 #define MAIN0_SERDESID_REV_NUMBER_SHIFT 11 9291 9292 /* Main0 :: serdesID :: bonding [10:09] */ 9293 #define MAIN0_SERDESID_BONDING_MASK 0x0600 9294 #define MAIN0_SERDESID_BONDING_ALIGN 0 9295 #define MAIN0_SERDESID_BONDING_BITS 2 9296 #define MAIN0_SERDESID_BONDING_SHIFT 9 9297 9298 /* Main0 :: serdesID :: tech_proc [08:06] */ 9299 #define MAIN0_SERDESID_TECH_PROC_MASK 0x01c0 9300 #define MAIN0_SERDESID_TECH_PROC_ALIGN 0 9301 #define MAIN0_SERDESID_TECH_PROC_BITS 3 9302 #define MAIN0_SERDESID_TECH_PROC_SHIFT 6 9303 9304 /* Main0 :: serdesID :: model_number [05:00] */ 9305 #define MAIN0_SERDESID_MODEL_NUMBER_MASK 0x003f 9306 #define MAIN0_SERDESID_MODEL_NUMBER_ALIGN 0 9307 #define MAIN0_SERDESID_MODEL_NUMBER_BITS 6 9308 #define MAIN0_SERDESID_MODEL_NUMBER_SHIFT 0 9309 9310 9311 /**************************************************************************** 9312 * TSC_WC4_TSC_USER1_anaPLL 9313 */ 9314 /**************************************************************************** 9315 * anaPLL :: Status 9316 */ 9317 /* anaPLL :: Status :: pllSeqDone [15:15] */ 9318 #define ANAPLL_STATUS_PLLSEQDONE_MASK 0x8000 9319 #define ANAPLL_STATUS_PLLSEQDONE_ALIGN 0 9320 #define ANAPLL_STATUS_PLLSEQDONE_BITS 1 9321 #define ANAPLL_STATUS_PLLSEQDONE_SHIFT 15 9322 9323 /* anaPLL :: Status :: freqDone [14:14] */ 9324 #define ANAPLL_STATUS_FREQDONE_MASK 0x4000 9325 #define ANAPLL_STATUS_FREQDONE_ALIGN 0 9326 #define ANAPLL_STATUS_FREQDONE_BITS 1 9327 #define ANAPLL_STATUS_FREQDONE_SHIFT 14 9328 9329 /* anaPLL :: Status :: vcoDone [13:13] */ 9330 #define ANAPLL_STATUS_VCODONE_MASK 0x2000 9331 #define ANAPLL_STATUS_VCODONE_ALIGN 0 9332 #define ANAPLL_STATUS_VCODONE_BITS 1 9333 #define ANAPLL_STATUS_VCODONE_SHIFT 13 9334 9335 /* anaPLL :: Status :: reserved0 [12:12] */ 9336 #define ANAPLL_STATUS_RESERVED0_MASK 0x1000 9337 #define ANAPLL_STATUS_RESERVED0_ALIGN 0 9338 #define ANAPLL_STATUS_RESERVED0_BITS 1 9339 #define ANAPLL_STATUS_RESERVED0_SHIFT 12 9340 9341 /* anaPLL :: Status :: pllSeqPass [11:11] */ 9342 #define ANAPLL_STATUS_PLLSEQPASS_MASK 0x0800 9343 #define ANAPLL_STATUS_PLLSEQPASS_ALIGN 0 9344 #define ANAPLL_STATUS_PLLSEQPASS_BITS 1 9345 #define ANAPLL_STATUS_PLLSEQPASS_SHIFT 11 9346 9347 /* anaPLL :: Status :: freqPass [10:10] */ 9348 #define ANAPLL_STATUS_FREQPASS_MASK 0x0400 9349 #define ANAPLL_STATUS_FREQPASS_ALIGN 0 9350 #define ANAPLL_STATUS_FREQPASS_BITS 1 9351 #define ANAPLL_STATUS_FREQPASS_SHIFT 10 9352 9353 /* anaPLL :: Status :: vcoPass [09:09] */ 9354 #define ANAPLL_STATUS_VCOPASS_MASK 0x0200 9355 #define ANAPLL_STATUS_VCOPASS_ALIGN 0 9356 #define ANAPLL_STATUS_VCOPASS_BITS 1 9357 #define ANAPLL_STATUS_VCOPASS_SHIFT 9 9358 9359 /* anaPLL :: Status :: reserved1 [08:08] */ 9360 #define ANAPLL_STATUS_RESERVED1_MASK 0x0100 9361 #define ANAPLL_STATUS_RESERVED1_ALIGN 0 9362 #define ANAPLL_STATUS_RESERVED1_BITS 1 9363 #define ANAPLL_STATUS_RESERVED1_SHIFT 8 9364 9365 /* anaPLL :: Status :: slowdn [07:07] */ 9366 #define ANAPLL_STATUS_SLOWDN_MASK 0x0080 9367 #define ANAPLL_STATUS_SLOWDN_ALIGN 0 9368 #define ANAPLL_STATUS_SLOWDN_BITS 1 9369 #define ANAPLL_STATUS_SLOWDN_SHIFT 7 9370 9371 /* anaPLL :: Status :: lostPllLock_SM [06:06] */ 9372 #define ANAPLL_STATUS_LOSTPLLLOCK_SM_MASK 0x0040 9373 #define ANAPLL_STATUS_LOSTPLLLOCK_SM_ALIGN 0 9374 #define ANAPLL_STATUS_LOSTPLLLOCK_SM_BITS 1 9375 #define ANAPLL_STATUS_LOSTPLLLOCK_SM_SHIFT 6 9376 9377 /* anaPLL :: Status :: reserved2 [05:04] */ 9378 #define ANAPLL_STATUS_RESERVED2_MASK 0x0030 9379 #define ANAPLL_STATUS_RESERVED2_ALIGN 0 9380 #define ANAPLL_STATUS_RESERVED2_BITS 2 9381 #define ANAPLL_STATUS_RESERVED2_SHIFT 4 9382 9383 /* anaPLL :: Status :: pll_mode_afe [03:00] */ 9384 #define ANAPLL_STATUS_PLL_MODE_AFE_MASK 0x000f 9385 #define ANAPLL_STATUS_PLL_MODE_AFE_ALIGN 0 9386 #define ANAPLL_STATUS_PLL_MODE_AFE_BITS 4 9387 #define ANAPLL_STATUS_PLL_MODE_AFE_SHIFT 0 9388 #define ANAPLL_STATUS_PLL_MODE_AFE_div32 0 9389 #define ANAPLL_STATUS_PLL_MODE_AFE_div36 1 9390 #define ANAPLL_STATUS_PLL_MODE_AFE_div40 2 9391 #define ANAPLL_STATUS_PLL_MODE_AFE_div42 3 9392 #define ANAPLL_STATUS_PLL_MODE_AFE_div48 4 9393 #define ANAPLL_STATUS_PLL_MODE_AFE_div50 5 9394 #define ANAPLL_STATUS_PLL_MODE_AFE_div52 6 9395 #define ANAPLL_STATUS_PLL_MODE_AFE_div54 7 9396 #define ANAPLL_STATUS_PLL_MODE_AFE_div60 8 9397 #define ANAPLL_STATUS_PLL_MODE_AFE_div64 9 9398 #define ANAPLL_STATUS_PLL_MODE_AFE_div66 10 9399 #define ANAPLL_STATUS_PLL_MODE_AFE_div68 11 9400 #define ANAPLL_STATUS_PLL_MODE_AFE_div70 12 9401 #define ANAPLL_STATUS_PLL_MODE_AFE_div80 13 9402 #define ANAPLL_STATUS_PLL_MODE_AFE_div92 14 9403 #define ANAPLL_STATUS_PLL_MODE_AFE_div100 15 9404 9405 9406 /**************************************************************************** 9407 * anaPLL :: Control 9408 */ 9409 /* anaPLL :: Control :: reserved0 [15:15] */ 9410 #define ANAPLL_CONTROL_RESERVED0_MASK 0x8000 9411 #define ANAPLL_CONTROL_RESERVED0_ALIGN 0 9412 #define ANAPLL_CONTROL_RESERVED0_BITS 1 9413 #define ANAPLL_CONTROL_RESERVED0_SHIFT 15 9414 9415 /* anaPLL :: Control :: FreqDetRetry_en [14:14] */ 9416 #define ANAPLL_CONTROL_FREQDETRETRY_EN_MASK 0x4000 9417 #define ANAPLL_CONTROL_FREQDETRETRY_EN_ALIGN 0 9418 #define ANAPLL_CONTROL_FREQDETRETRY_EN_BITS 1 9419 #define ANAPLL_CONTROL_FREQDETRETRY_EN_SHIFT 14 9420 9421 /* anaPLL :: Control :: FreqDetRestart_en [13:13] */ 9422 #define ANAPLL_CONTROL_FREQDETRESTART_EN_MASK 0x2000 9423 #define ANAPLL_CONTROL_FREQDETRESTART_EN_ALIGN 0 9424 #define ANAPLL_CONTROL_FREQDETRESTART_EN_BITS 1 9425 #define ANAPLL_CONTROL_FREQDETRESTART_EN_SHIFT 13 9426 9427 /* anaPLL :: Control :: FreqMonitor_en [12:12] */ 9428 #define ANAPLL_CONTROL_FREQMONITOR_EN_MASK 0x1000 9429 #define ANAPLL_CONTROL_FREQMONITOR_EN_ALIGN 0 9430 #define ANAPLL_CONTROL_FREQMONITOR_EN_BITS 1 9431 #define ANAPLL_CONTROL_FREQMONITOR_EN_SHIFT 12 9432 9433 /* anaPLL :: Control :: VcopRetry_en [11:11] */ 9434 #define ANAPLL_CONTROL_VCOPRETRY_EN_MASK 0x0800 9435 #define ANAPLL_CONTROL_VCOPRETRY_EN_ALIGN 0 9436 #define ANAPLL_CONTROL_VCOPRETRY_EN_BITS 1 9437 #define ANAPLL_CONTROL_VCOPRETRY_EN_SHIFT 11 9438 9439 /* anaPLL :: Control :: VcoDone_en [10:10] */ 9440 #define ANAPLL_CONTROL_VCODONE_EN_MASK 0x0400 9441 #define ANAPLL_CONTROL_VCODONE_EN_ALIGN 0 9442 #define ANAPLL_CONTROL_VCODONE_EN_BITS 1 9443 #define ANAPLL_CONTROL_VCODONE_EN_SHIFT 10 9444 9445 /* anaPLL :: Control :: LinkRestart_en [09:09] */ 9446 #define ANAPLL_CONTROL_LINKRESTART_EN_MASK 0x0200 9447 #define ANAPLL_CONTROL_LINKRESTART_EN_ALIGN 0 9448 #define ANAPLL_CONTROL_LINKRESTART_EN_BITS 1 9449 #define ANAPLL_CONTROL_LINKRESTART_EN_SHIFT 9 9450 9451 /* anaPLL :: Control :: ByteSyncRestart_en [08:08] */ 9452 #define ANAPLL_CONTROL_BYTESYNCRESTART_EN_MASK 0x0100 9453 #define ANAPLL_CONTROL_BYTESYNCRESTART_EN_ALIGN 0 9454 #define ANAPLL_CONTROL_BYTESYNCRESTART_EN_BITS 1 9455 #define ANAPLL_CONTROL_BYTESYNCRESTART_EN_SHIFT 8 9456 9457 /* anaPLL :: Control :: PllForceDone_en [07:07] */ 9458 #define ANAPLL_CONTROL_PLLFORCEDONE_EN_MASK 0x0080 9459 #define ANAPLL_CONTROL_PLLFORCEDONE_EN_ALIGN 0 9460 #define ANAPLL_CONTROL_PLLFORCEDONE_EN_BITS 1 9461 #define ANAPLL_CONTROL_PLLFORCEDONE_EN_SHIFT 7 9462 9463 /* anaPLL :: Control :: PllForceDone [06:06] */ 9464 #define ANAPLL_CONTROL_PLLFORCEDONE_MASK 0x0040 9465 #define ANAPLL_CONTROL_PLLFORCEDONE_ALIGN 0 9466 #define ANAPLL_CONTROL_PLLFORCEDONE_BITS 1 9467 #define ANAPLL_CONTROL_PLLFORCEDONE_SHIFT 6 9468 9469 /* anaPLL :: Control :: PllForcePass [05:05] */ 9470 #define ANAPLL_CONTROL_PLLFORCEPASS_MASK 0x0020 9471 #define ANAPLL_CONTROL_PLLFORCEPASS_ALIGN 0 9472 #define ANAPLL_CONTROL_PLLFORCEPASS_BITS 1 9473 #define ANAPLL_CONTROL_PLLFORCEPASS_SHIFT 5 9474 9475 /* anaPLL :: Control :: PllForceVcoDone_en [04:04] */ 9476 #define ANAPLL_CONTROL_PLLFORCEVCODONE_EN_MASK 0x0010 9477 #define ANAPLL_CONTROL_PLLFORCEVCODONE_EN_ALIGN 0 9478 #define ANAPLL_CONTROL_PLLFORCEVCODONE_EN_BITS 1 9479 #define ANAPLL_CONTROL_PLLFORCEVCODONE_EN_SHIFT 4 9480 9481 /* anaPLL :: Control :: PllForceVcoDone [03:03] */ 9482 #define ANAPLL_CONTROL_PLLFORCEVCODONE_MASK 0x0008 9483 #define ANAPLL_CONTROL_PLLFORCEVCODONE_ALIGN 0 9484 #define ANAPLL_CONTROL_PLLFORCEVCODONE_BITS 1 9485 #define ANAPLL_CONTROL_PLLFORCEVCODONE_SHIFT 3 9486 9487 /* anaPLL :: Control :: PllForceVcoPass_en [02:02] */ 9488 #define ANAPLL_CONTROL_PLLFORCEVCOPASS_EN_MASK 0x0004 9489 #define ANAPLL_CONTROL_PLLFORCEVCOPASS_EN_ALIGN 0 9490 #define ANAPLL_CONTROL_PLLFORCEVCOPASS_EN_BITS 1 9491 #define ANAPLL_CONTROL_PLLFORCEVCOPASS_EN_SHIFT 2 9492 9493 /* anaPLL :: Control :: PllForceVcoPass [01:01] */ 9494 #define ANAPLL_CONTROL_PLLFORCEVCOPASS_MASK 0x0002 9495 #define ANAPLL_CONTROL_PLLFORCEVCOPASS_ALIGN 0 9496 #define ANAPLL_CONTROL_PLLFORCEVCOPASS_BITS 1 9497 #define ANAPLL_CONTROL_PLLFORCEVCOPASS_SHIFT 1 9498 9499 /* anaPLL :: Control :: PllForcePllLock [00:00] */ 9500 #define ANAPLL_CONTROL_PLLFORCEPLLLOCK_MASK 0x0001 9501 #define ANAPLL_CONTROL_PLLFORCEPLLLOCK_ALIGN 0 9502 #define ANAPLL_CONTROL_PLLFORCEPLLLOCK_BITS 1 9503 #define ANAPLL_CONTROL_PLLFORCEPLLLOCK_SHIFT 0 9504 9505 9506 /**************************************************************************** 9507 * anaPLL :: Timer1 9508 */ 9509 /* anaPLL :: Timer1 :: VcoStepTime [15:08] */ 9510 #define ANAPLL_TIMER1_VCOSTEPTIME_MASK 0xff00 9511 #define ANAPLL_TIMER1_VCOSTEPTIME_ALIGN 0 9512 #define ANAPLL_TIMER1_VCOSTEPTIME_BITS 8 9513 #define ANAPLL_TIMER1_VCOSTEPTIME_SHIFT 8 9514 9515 /* anaPLL :: Timer1 :: VcoStartTime [07:00] */ 9516 #define ANAPLL_TIMER1_VCOSTARTTIME_MASK 0x00ff 9517 #define ANAPLL_TIMER1_VCOSTARTTIME_ALIGN 0 9518 #define ANAPLL_TIMER1_VCOSTARTTIME_BITS 8 9519 #define ANAPLL_TIMER1_VCOSTARTTIME_SHIFT 0 9520 9521 9522 /**************************************************************************** 9523 * anaPLL :: Timer2 9524 */ 9525 /* anaPLL :: Timer2 :: reserved0 [15:13] */ 9526 #define ANAPLL_TIMER2_RESERVED0_MASK 0xe000 9527 #define ANAPLL_TIMER2_RESERVED0_ALIGN 0 9528 #define ANAPLL_TIMER2_RESERVED0_BITS 3 9529 #define ANAPLL_TIMER2_RESERVED0_SHIFT 13 9530 9531 /* anaPLL :: Timer2 :: testMuxSel [12:08] */ 9532 #define ANAPLL_TIMER2_TESTMUXSEL_MASK 0x1f00 9533 #define ANAPLL_TIMER2_TESTMUXSEL_ALIGN 0 9534 #define ANAPLL_TIMER2_TESTMUXSEL_BITS 5 9535 #define ANAPLL_TIMER2_TESTMUXSEL_SHIFT 8 9536 9537 /* anaPLL :: Timer2 :: retryTime [07:00] */ 9538 #define ANAPLL_TIMER2_RETRYTIME_MASK 0x00ff 9539 #define ANAPLL_TIMER2_RETRYTIME_ALIGN 0 9540 #define ANAPLL_TIMER2_RETRYTIME_BITS 8 9541 #define ANAPLL_TIMER2_RETRYTIME_SHIFT 0 9542 9543 9544 /**************************************************************************** 9545 * anaPLL :: Timer3 9546 */ 9547 /* anaPLL :: Timer3 :: reserved0 [15:08] */ 9548 #define ANAPLL_TIMER3_RESERVED0_MASK 0xff00 9549 #define ANAPLL_TIMER3_RESERVED0_ALIGN 0 9550 #define ANAPLL_TIMER3_RESERVED0_BITS 8 9551 #define ANAPLL_TIMER3_RESERVED0_SHIFT 8 9552 9553 /* anaPLL :: Timer3 :: freqDetTime [07:00] */ 9554 #define ANAPLL_TIMER3_FREQDETTIME_MASK 0x00ff 9555 #define ANAPLL_TIMER3_FREQDETTIME_ALIGN 0 9556 #define ANAPLL_TIMER3_FREQDETTIME_BITS 8 9557 #define ANAPLL_TIMER3_FREQDETTIME_SHIFT 0 9558 9559 9560 /**************************************************************************** 9561 * anaPLL :: CapControl 9562 */ 9563 /* anaPLL :: CapControl :: vcoSeqCYA [15:15] */ 9564 #define ANAPLL_CAPCONTROL_VCOSEQCYA_MASK 0x8000 9565 #define ANAPLL_CAPCONTROL_VCOSEQCYA_ALIGN 0 9566 #define ANAPLL_CAPCONTROL_VCOSEQCYA_BITS 1 9567 #define ANAPLL_CAPCONTROL_VCOSEQCYA_SHIFT 15 9568 9569 /* anaPLL :: CapControl :: vcoRestart [14:14] */ 9570 #define ANAPLL_CAPCONTROL_VCORESTART_MASK 0x4000 9571 #define ANAPLL_CAPCONTROL_VCORESTART_ALIGN 0 9572 #define ANAPLL_CAPCONTROL_VCORESTART_BITS 1 9573 #define ANAPLL_CAPCONTROL_VCORESTART_SHIFT 14 9574 9575 /* anaPLL :: CapControl :: vcoSelectM_en [13:13] */ 9576 #define ANAPLL_CAPCONTROL_VCOSELECTM_EN_MASK 0x2000 9577 #define ANAPLL_CAPCONTROL_VCOSELECTM_EN_ALIGN 0 9578 #define ANAPLL_CAPCONTROL_VCOSELECTM_EN_BITS 1 9579 #define ANAPLL_CAPCONTROL_VCOSELECTM_EN_SHIFT 13 9580 9581 /* anaPLL :: CapControl :: vcoForceSlowdn_en [12:12] */ 9582 #define ANAPLL_CAPCONTROL_VCOFORCESLOWDN_EN_MASK 0x1000 9583 #define ANAPLL_CAPCONTROL_VCOFORCESLOWDN_EN_ALIGN 0 9584 #define ANAPLL_CAPCONTROL_VCOFORCESLOWDN_EN_BITS 1 9585 #define ANAPLL_CAPCONTROL_VCOFORCESLOWDN_EN_SHIFT 12 9586 9587 /* anaPLL :: CapControl :: vcoRstEn [11:11] */ 9588 #define ANAPLL_CAPCONTROL_VCORSTEN_MASK 0x0800 9589 #define ANAPLL_CAPCONTROL_VCORSTEN_ALIGN 0 9590 #define ANAPLL_CAPCONTROL_VCORSTEN_BITS 1 9591 #define ANAPLL_CAPCONTROL_VCORSTEN_SHIFT 11 9592 9593 /* anaPLL :: CapControl :: vcoCntMask_en [10:10] */ 9594 #define ANAPLL_CAPCONTROL_VCOCNTMASK_EN_MASK 0x0400 9595 #define ANAPLL_CAPCONTROL_VCOCNTMASK_EN_ALIGN 0 9596 #define ANAPLL_CAPCONTROL_VCOCNTMASK_EN_BITS 1 9597 #define ANAPLL_CAPCONTROL_VCOCNTMASK_EN_SHIFT 10 9598 9599 /* anaPLL :: CapControl :: slowdn_xor [09:09] */ 9600 #define ANAPLL_CAPCONTROL_SLOWDN_XOR_MASK 0x0200 9601 #define ANAPLL_CAPCONTROL_SLOWDN_XOR_ALIGN 0 9602 #define ANAPLL_CAPCONTROL_SLOWDN_XOR_BITS 1 9603 #define ANAPLL_CAPCONTROL_SLOWDN_XOR_SHIFT 9 9604 9605 /* anaPLL :: CapControl :: vcoForceSlowDown [08:08] */ 9606 #define ANAPLL_CAPCONTROL_VCOFORCESLOWDOWN_MASK 0x0100 9607 #define ANAPLL_CAPCONTROL_VCOFORCESLOWDOWN_ALIGN 0 9608 #define ANAPLL_CAPCONTROL_VCOFORCESLOWDOWN_BITS 1 9609 #define ANAPLL_CAPCONTROL_VCOFORCESLOWDOWN_SHIFT 8 9610 9611 /* anaPLL :: CapControl :: vcoSelectM [07:00] */ 9612 #define ANAPLL_CAPCONTROL_VCOSELECTM_MASK 0x00ff 9613 #define ANAPLL_CAPCONTROL_VCOSELECTM_ALIGN 0 9614 #define ANAPLL_CAPCONTROL_VCOSELECTM_BITS 8 9615 #define ANAPLL_CAPCONTROL_VCOSELECTM_SHIFT 0 9616 9617 9618 /**************************************************************************** 9619 * anaPLL :: anaPll_debug_status 9620 */ 9621 /* anaPLL :: anaPll_debug_status :: reserved0 [15:08] */ 9622 #define ANAPLL_ANAPLL_DEBUG_STATUS_RESERVED0_MASK 0xff00 9623 #define ANAPLL_ANAPLL_DEBUG_STATUS_RESERVED0_ALIGN 0 9624 #define ANAPLL_ANAPLL_DEBUG_STATUS_RESERVED0_BITS 8 9625 #define ANAPLL_ANAPLL_DEBUG_STATUS_RESERVED0_SHIFT 8 9626 9627 /* anaPLL :: anaPll_debug_status :: tx_pll_tmux [07:00] */ 9628 #define ANAPLL_ANAPLL_DEBUG_STATUS_TX_PLL_TMUX_MASK 0x00ff 9629 #define ANAPLL_ANAPLL_DEBUG_STATUS_TX_PLL_TMUX_ALIGN 0 9630 #define ANAPLL_ANAPLL_DEBUG_STATUS_TX_PLL_TMUX_BITS 8 9631 #define ANAPLL_ANAPLL_DEBUG_STATUS_TX_PLL_TMUX_SHIFT 0 9632 9633 9634 /**************************************************************************** 9635 * anaPLL :: FreqDetCntr 9636 */ 9637 /* anaPLL :: FreqDetCntr :: resolution [15:08] */ 9638 #define ANAPLL_FREQDETCNTR_RESOLUTION_MASK 0xff00 9639 #define ANAPLL_FREQDETCNTR_RESOLUTION_ALIGN 0 9640 #define ANAPLL_FREQDETCNTR_RESOLUTION_BITS 8 9641 #define ANAPLL_FREQDETCNTR_RESOLUTION_SHIFT 8 9642 9643 /* anaPLL :: FreqDetCntr :: window [07:00] */ 9644 #define ANAPLL_FREQDETCNTR_WINDOW_MASK 0x00ff 9645 #define ANAPLL_FREQDETCNTR_WINDOW_ALIGN 0 9646 #define ANAPLL_FREQDETCNTR_WINDOW_BITS 8 9647 #define ANAPLL_FREQDETCNTR_WINDOW_SHIFT 0 9648 9649 9650 /**************************************************************************** 9651 * anaPLL :: AStatus1 9652 */ 9653 /* anaPLL :: AStatus1 :: kvh [15:14] */ 9654 #define ANAPLL_ASTATUS1_KVH_MASK 0xc000 9655 #define ANAPLL_ASTATUS1_KVH_ALIGN 0 9656 #define ANAPLL_ASTATUS1_KVH_BITS 2 9657 #define ANAPLL_ASTATUS1_KVH_SHIFT 14 9658 9659 /* anaPLL :: AStatus1 :: pll_range [13:06] */ 9660 #define ANAPLL_ASTATUS1_PLL_RANGE_MASK 0x3fc0 9661 #define ANAPLL_ASTATUS1_PLL_RANGE_ALIGN 0 9662 #define ANAPLL_ASTATUS1_PLL_RANGE_BITS 8 9663 #define ANAPLL_ASTATUS1_PLL_RANGE_SHIFT 6 9664 9665 /* anaPLL :: AStatus1 :: pll_low [05:05] */ 9666 #define ANAPLL_ASTATUS1_PLL_LOW_MASK 0x0020 9667 #define ANAPLL_ASTATUS1_PLL_LOW_ALIGN 0 9668 #define ANAPLL_ASTATUS1_PLL_LOW_BITS 1 9669 #define ANAPLL_ASTATUS1_PLL_LOW_SHIFT 5 9670 9671 /* anaPLL :: AStatus1 :: reserved0 [04:04] */ 9672 #define ANAPLL_ASTATUS1_RESERVED0_MASK 0x0010 9673 #define ANAPLL_ASTATUS1_RESERVED0_ALIGN 0 9674 #define ANAPLL_ASTATUS1_RESERVED0_BITS 1 9675 #define ANAPLL_ASTATUS1_RESERVED0_SHIFT 4 9676 9677 /* anaPLL :: AStatus1 :: pll_Ndiv [03:00] */ 9678 #define ANAPLL_ASTATUS1_PLL_NDIV_MASK 0x000f 9679 #define ANAPLL_ASTATUS1_PLL_NDIV_ALIGN 0 9680 #define ANAPLL_ASTATUS1_PLL_NDIV_BITS 4 9681 #define ANAPLL_ASTATUS1_PLL_NDIV_SHIFT 0 9682 9683 9684 /**************************************************************************** 9685 * anaPLL :: AControl0 9686 */ 9687 /* anaPLL :: AControl0 :: refl_clkgen [15:15] */ 9688 #define ANAPLL_ACONTROL0_REFL_CLKGEN_MASK 0x8000 9689 #define ANAPLL_ACONTROL0_REFL_CLKGEN_ALIGN 0 9690 #define ANAPLL_ACONTROL0_REFL_CLKGEN_BITS 1 9691 #define ANAPLL_ACONTROL0_REFL_CLKGEN_SHIFT 15 9692 9693 /* anaPLL :: AControl0 :: iclkidrv1 [14:12] */ 9694 #define ANAPLL_ACONTROL0_ICLKIDRV1_MASK 0x7000 9695 #define ANAPLL_ACONTROL0_ICLKIDRV1_ALIGN 0 9696 #define ANAPLL_ACONTROL0_ICLKIDRV1_BITS 3 9697 #define ANAPLL_ACONTROL0_ICLKIDRV1_SHIFT 12 9698 9699 /* anaPLL :: AControl0 :: iclkodrv1 [11:09] */ 9700 #define ANAPLL_ACONTROL0_ICLKODRV1_MASK 0x0e00 9701 #define ANAPLL_ACONTROL0_ICLKODRV1_ALIGN 0 9702 #define ANAPLL_ACONTROL0_ICLKODRV1_BITS 3 9703 #define ANAPLL_ACONTROL0_ICLKODRV1_SHIFT 9 9704 9705 /* anaPLL :: AControl0 :: iclkodrv2 [08:06] */ 9706 #define ANAPLL_ACONTROL0_ICLKODRV2_MASK 0x01c0 9707 #define ANAPLL_ACONTROL0_ICLKODRV2_ALIGN 0 9708 #define ANAPLL_ACONTROL0_ICLKODRV2_BITS 3 9709 #define ANAPLL_ACONTROL0_ICLKODRV2_SHIFT 6 9710 9711 /* anaPLL :: AControl0 :: iclkdiv2 [05:03] */ 9712 #define ANAPLL_ACONTROL0_ICLKDIV2_MASK 0x0038 9713 #define ANAPLL_ACONTROL0_ICLKDIV2_ALIGN 0 9714 #define ANAPLL_ACONTROL0_ICLKDIV2_BITS 3 9715 #define ANAPLL_ACONTROL0_ICLKDIV2_SHIFT 3 9716 9717 /* anaPLL :: AControl0 :: reserved0 [02:02] */ 9718 #define ANAPLL_ACONTROL0_RESERVED0_MASK 0x0004 9719 #define ANAPLL_ACONTROL0_RESERVED0_ALIGN 0 9720 #define ANAPLL_ACONTROL0_RESERVED0_BITS 1 9721 #define ANAPLL_ACONTROL0_RESERVED0_SHIFT 2 9722 9723 /* anaPLL :: AControl0 :: vddr_bgb [01:01] */ 9724 #define ANAPLL_ACONTROL0_VDDR_BGB_MASK 0x0002 9725 #define ANAPLL_ACONTROL0_VDDR_BGB_ALIGN 0 9726 #define ANAPLL_ACONTROL0_VDDR_BGB_BITS 1 9727 #define ANAPLL_ACONTROL0_VDDR_BGB_SHIFT 1 9728 9729 /* anaPLL :: AControl0 :: amp_ctrl [00:00] */ 9730 #define ANAPLL_ACONTROL0_AMP_CTRL_MASK 0x0001 9731 #define ANAPLL_ACONTROL0_AMP_CTRL_ALIGN 0 9732 #define ANAPLL_ACONTROL0_AMP_CTRL_BITS 1 9733 #define ANAPLL_ACONTROL0_AMP_CTRL_SHIFT 0 9734 9735 9736 /**************************************************************************** 9737 * anaPLL :: AControl1 9738 */ 9739 /* anaPLL :: AControl1 :: enable_ftune [15:15] */ 9740 #define ANAPLL_ACONTROL1_ENABLE_FTUNE_MASK 0x8000 9741 #define ANAPLL_ACONTROL1_ENABLE_FTUNE_ALIGN 0 9742 #define ANAPLL_ACONTROL1_ENABLE_FTUNE_BITS 1 9743 #define ANAPLL_ACONTROL1_ENABLE_FTUNE_SHIFT 15 9744 9745 /* anaPLL :: AControl1 :: pll_reset [14:14] */ 9746 #define ANAPLL_ACONTROL1_PLL_RESET_MASK 0x4000 9747 #define ANAPLL_ACONTROL1_PLL_RESET_ALIGN 0 9748 #define ANAPLL_ACONTROL1_PLL_RESET_BITS 1 9749 #define ANAPLL_ACONTROL1_PLL_RESET_SHIFT 14 9750 9751 /* anaPLL :: AControl1 :: reserved0 [13:08] */ 9752 #define ANAPLL_ACONTROL1_RESERVED0_MASK 0x3f00 9753 #define ANAPLL_ACONTROL1_RESERVED0_ALIGN 0 9754 #define ANAPLL_ACONTROL1_RESERVED0_BITS 6 9755 #define ANAPLL_ACONTROL1_RESERVED0_SHIFT 8 9756 9757 /* anaPLL :: AControl1 :: ickgen [07:05] */ 9758 #define ANAPLL_ACONTROL1_ICKGEN_MASK 0x00e0 9759 #define ANAPLL_ACONTROL1_ICKGEN_ALIGN 0 9760 #define ANAPLL_ACONTROL1_ICKGEN_BITS 3 9761 #define ANAPLL_ACONTROL1_ICKGEN_SHIFT 5 9762 9763 /* anaPLL :: AControl1 :: reserved1 [04:01] */ 9764 #define ANAPLL_ACONTROL1_RESERVED1_MASK 0x001e 9765 #define ANAPLL_ACONTROL1_RESERVED1_ALIGN 0 9766 #define ANAPLL_ACONTROL1_RESERVED1_BITS 4 9767 #define ANAPLL_ACONTROL1_RESERVED1_SHIFT 1 9768 9769 /* anaPLL :: AControl1 :: refh_clkgen [00:00] */ 9770 #define ANAPLL_ACONTROL1_REFH_CLKGEN_MASK 0x0001 9771 #define ANAPLL_ACONTROL1_REFH_CLKGEN_ALIGN 0 9772 #define ANAPLL_ACONTROL1_REFH_CLKGEN_BITS 1 9773 #define ANAPLL_ACONTROL1_REFH_CLKGEN_SHIFT 0 9774 9775 9776 /**************************************************************************** 9777 * anaPLL :: AControl2 9778 */ 9779 /* anaPLL :: AControl2 :: ick2 [15:15] */ 9780 #define ANAPLL_ACONTROL2_ICK2_MASK 0x8000 9781 #define ANAPLL_ACONTROL2_ICK2_ALIGN 0 9782 #define ANAPLL_ACONTROL2_ICK2_BITS 1 9783 #define ANAPLL_ACONTROL2_ICK2_SHIFT 15 9784 9785 /* anaPLL :: AControl2 :: ick0 [14:14] */ 9786 #define ANAPLL_ACONTROL2_ICK0_MASK 0x4000 9787 #define ANAPLL_ACONTROL2_ICK0_ALIGN 0 9788 #define ANAPLL_ACONTROL2_ICK0_BITS 1 9789 #define ANAPLL_ACONTROL2_ICK0_SHIFT 14 9790 9791 /* anaPLL :: AControl2 :: ick1 [13:13] */ 9792 #define ANAPLL_ACONTROL2_ICK1_MASK 0x2000 9793 #define ANAPLL_ACONTROL2_ICK1_ALIGN 0 9794 #define ANAPLL_ACONTROL2_ICK1_BITS 1 9795 #define ANAPLL_ACONTROL2_ICK1_SHIFT 13 9796 9797 /* anaPLL :: AControl2 :: icp2 [12:12] */ 9798 #define ANAPLL_ACONTROL2_ICP2_MASK 0x1000 9799 #define ANAPLL_ACONTROL2_ICP2_ALIGN 0 9800 #define ANAPLL_ACONTROL2_ICP2_BITS 1 9801 #define ANAPLL_ACONTROL2_ICP2_SHIFT 12 9802 9803 /* anaPLL :: AControl2 :: icp0 [11:11] */ 9804 #define ANAPLL_ACONTROL2_ICP0_MASK 0x0800 9805 #define ANAPLL_ACONTROL2_ICP0_ALIGN 0 9806 #define ANAPLL_ACONTROL2_ICP0_BITS 1 9807 #define ANAPLL_ACONTROL2_ICP0_SHIFT 11 9808 9809 /* anaPLL :: AControl2 :: icp1 [10:10] */ 9810 #define ANAPLL_ACONTROL2_ICP1_MASK 0x0400 9811 #define ANAPLL_ACONTROL2_ICP1_ALIGN 0 9812 #define ANAPLL_ACONTROL2_ICP1_BITS 1 9813 #define ANAPLL_ACONTROL2_ICP1_SHIFT 10 9814 9815 /* anaPLL :: AControl2 :: ibmax [09:09] */ 9816 #define ANAPLL_ACONTROL2_IBMAX_MASK 0x0200 9817 #define ANAPLL_ACONTROL2_IBMAX_ALIGN 0 9818 #define ANAPLL_ACONTROL2_IBMAX_BITS 1 9819 #define ANAPLL_ACONTROL2_IBMAX_SHIFT 9 9820 9821 /* anaPLL :: AControl2 :: ibmode [08:08] */ 9822 #define ANAPLL_ACONTROL2_IBMODE_MASK 0x0100 9823 #define ANAPLL_ACONTROL2_IBMODE_ALIGN 0 9824 #define ANAPLL_ACONTROL2_IBMODE_BITS 1 9825 #define ANAPLL_ACONTROL2_IBMODE_SHIFT 8 9826 9827 /* anaPLL :: AControl2 :: ibmin [07:07] */ 9828 #define ANAPLL_ACONTROL2_IBMIN_MASK 0x0080 9829 #define ANAPLL_ACONTROL2_IBMIN_ALIGN 0 9830 #define ANAPLL_ACONTROL2_IBMIN_BITS 1 9831 #define ANAPLL_ACONTROL2_IBMIN_SHIFT 7 9832 9833 /* anaPLL :: AControl2 :: refh_pll [06:06] */ 9834 #define ANAPLL_ACONTROL2_REFH_PLL_MASK 0x0040 9835 #define ANAPLL_ACONTROL2_REFH_PLL_ALIGN 0 9836 #define ANAPLL_ACONTROL2_REFH_PLL_BITS 1 9837 #define ANAPLL_ACONTROL2_REFH_PLL_SHIFT 6 9838 9839 /* anaPLL :: AControl2 :: refl_pll [05:05] */ 9840 #define ANAPLL_ACONTROL2_REFL_PLL_MASK 0x0020 9841 #define ANAPLL_ACONTROL2_REFL_PLL_ALIGN 0 9842 #define ANAPLL_ACONTROL2_REFL_PLL_BITS 1 9843 #define ANAPLL_ACONTROL2_REFL_PLL_SHIFT 5 9844 9845 /* anaPLL :: AControl2 :: iqp [04:01] */ 9846 #define ANAPLL_ACONTROL2_IQP_MASK 0x001e 9847 #define ANAPLL_ACONTROL2_IQP_ALIGN 0 9848 #define ANAPLL_ACONTROL2_IQP_BITS 4 9849 #define ANAPLL_ACONTROL2_IQP_SHIFT 1 9850 #define ANAPLL_ACONTROL2_IQP_i50uA 0 9851 #define ANAPLL_ACONTROL2_IQP_i100uA 1 9852 #define ANAPLL_ACONTROL2_IQP_i150uA 2 9853 #define ANAPLL_ACONTROL2_IQP_i200uA 3 9854 #define ANAPLL_ACONTROL2_IQP_i250uA 4 9855 #define ANAPLL_ACONTROL2_IQP_i300uA 5 9856 #define ANAPLL_ACONTROL2_IQP_i350uA 6 9857 #define ANAPLL_ACONTROL2_IQP_i400uA 7 9858 #define ANAPLL_ACONTROL2_IQP_i450uA 8 9859 #define ANAPLL_ACONTROL2_IQP_i500uA 9 9860 #define ANAPLL_ACONTROL2_IQP_i550uA 10 9861 #define ANAPLL_ACONTROL2_IQP_i600uA 11 9862 #define ANAPLL_ACONTROL2_IQP_i650uA 12 9863 #define ANAPLL_ACONTROL2_IQP_i700uA 13 9864 #define ANAPLL_ACONTROL2_IQP_i750uA 14 9865 #define ANAPLL_ACONTROL2_IQP_i800uA 15 9866 9867 /* anaPLL :: AControl2 :: en_HRz [00:00] */ 9868 #define ANAPLL_ACONTROL2_EN_HRZ_MASK 0x0001 9869 #define ANAPLL_ACONTROL2_EN_HRZ_ALIGN 0 9870 #define ANAPLL_ACONTROL2_EN_HRZ_BITS 1 9871 #define ANAPLL_ACONTROL2_EN_HRZ_SHIFT 0 9872 9873 9874 /**************************************************************************** 9875 * anaPLL :: AControl3 9876 */ 9877 /* anaPLL :: AControl3 :: test_rx [15:15] */ 9878 #define ANAPLL_ACONTROL3_TEST_RX_MASK 0x8000 9879 #define ANAPLL_ACONTROL3_TEST_RX_ALIGN 0 9880 #define ANAPLL_ACONTROL3_TEST_RX_BITS 1 9881 #define ANAPLL_ACONTROL3_TEST_RX_SHIFT 15 9882 9883 /* anaPLL :: AControl3 :: test_pll [14:14] */ 9884 #define ANAPLL_ACONTROL3_TEST_PLL_MASK 0x4000 9885 #define ANAPLL_ACONTROL3_TEST_PLL_ALIGN 0 9886 #define ANAPLL_ACONTROL3_TEST_PLL_BITS 1 9887 #define ANAPLL_ACONTROL3_TEST_PLL_SHIFT 14 9888 9889 /* anaPLL :: AControl3 :: test_vc [13:13] */ 9890 #define ANAPLL_ACONTROL3_TEST_VC_MASK 0x2000 9891 #define ANAPLL_ACONTROL3_TEST_VC_ALIGN 0 9892 #define ANAPLL_ACONTROL3_TEST_VC_BITS 1 9893 #define ANAPLL_ACONTROL3_TEST_VC_SHIFT 13 9894 9895 /* anaPLL :: AControl3 :: test_vref [12:12] */ 9896 #define ANAPLL_ACONTROL3_TEST_VREF_MASK 0x1000 9897 #define ANAPLL_ACONTROL3_TEST_VREF_ALIGN 0 9898 #define ANAPLL_ACONTROL3_TEST_VREF_BITS 1 9899 #define ANAPLL_ACONTROL3_TEST_VREF_SHIFT 12 9900 9901 /* anaPLL :: AControl3 :: iop2 [11:11] */ 9902 #define ANAPLL_ACONTROL3_IOP2_MASK 0x0800 9903 #define ANAPLL_ACONTROL3_IOP2_ALIGN 0 9904 #define ANAPLL_ACONTROL3_IOP2_BITS 1 9905 #define ANAPLL_ACONTROL3_IOP2_SHIFT 11 9906 9907 /* anaPLL :: AControl3 :: iop0 [10:10] */ 9908 #define ANAPLL_ACONTROL3_IOP0_MASK 0x0400 9909 #define ANAPLL_ACONTROL3_IOP0_ALIGN 0 9910 #define ANAPLL_ACONTROL3_IOP0_BITS 1 9911 #define ANAPLL_ACONTROL3_IOP0_SHIFT 10 9912 9913 /* anaPLL :: AControl3 :: iop1 [09:09] */ 9914 #define ANAPLL_ACONTROL3_IOP1_MASK 0x0200 9915 #define ANAPLL_ACONTROL3_IOP1_ALIGN 0 9916 #define ANAPLL_ACONTROL3_IOP1_BITS 1 9917 #define ANAPLL_ACONTROL3_IOP1_SHIFT 9 9918 9919 /* anaPLL :: AControl3 :: icomp2 [08:08] */ 9920 #define ANAPLL_ACONTROL3_ICOMP2_MASK 0x0100 9921 #define ANAPLL_ACONTROL3_ICOMP2_ALIGN 0 9922 #define ANAPLL_ACONTROL3_ICOMP2_BITS 1 9923 #define ANAPLL_ACONTROL3_ICOMP2_SHIFT 8 9924 9925 /* anaPLL :: AControl3 :: icomp0 [07:07] */ 9926 #define ANAPLL_ACONTROL3_ICOMP0_MASK 0x0080 9927 #define ANAPLL_ACONTROL3_ICOMP0_ALIGN 0 9928 #define ANAPLL_ACONTROL3_ICOMP0_BITS 1 9929 #define ANAPLL_ACONTROL3_ICOMP0_SHIFT 7 9930 9931 /* anaPLL :: AControl3 :: icomp1 [06:06] */ 9932 #define ANAPLL_ACONTROL3_ICOMP1_MASK 0x0040 9933 #define ANAPLL_ACONTROL3_ICOMP1_ALIGN 0 9934 #define ANAPLL_ACONTROL3_ICOMP1_BITS 1 9935 #define ANAPLL_ACONTROL3_ICOMP1_SHIFT 6 9936 9937 /* anaPLL :: AControl3 :: icml2 [05:05] */ 9938 #define ANAPLL_ACONTROL3_ICML2_MASK 0x0020 9939 #define ANAPLL_ACONTROL3_ICML2_ALIGN 0 9940 #define ANAPLL_ACONTROL3_ICML2_BITS 1 9941 #define ANAPLL_ACONTROL3_ICML2_SHIFT 5 9942 9943 /* anaPLL :: AControl3 :: icml0 [04:04] */ 9944 #define ANAPLL_ACONTROL3_ICML0_MASK 0x0010 9945 #define ANAPLL_ACONTROL3_ICML0_ALIGN 0 9946 #define ANAPLL_ACONTROL3_ICML0_BITS 1 9947 #define ANAPLL_ACONTROL3_ICML0_SHIFT 4 9948 9949 /* anaPLL :: AControl3 :: icml1 [03:03] */ 9950 #define ANAPLL_ACONTROL3_ICML1_MASK 0x0008 9951 #define ANAPLL_ACONTROL3_ICML1_ALIGN 0 9952 #define ANAPLL_ACONTROL3_ICML1_BITS 1 9953 #define ANAPLL_ACONTROL3_ICML1_SHIFT 3 9954 9955 /* anaPLL :: AControl3 :: i10Gbuf2 [02:02] */ 9956 #define ANAPLL_ACONTROL3_I10GBUF2_MASK 0x0004 9957 #define ANAPLL_ACONTROL3_I10GBUF2_ALIGN 0 9958 #define ANAPLL_ACONTROL3_I10GBUF2_BITS 1 9959 #define ANAPLL_ACONTROL3_I10GBUF2_SHIFT 2 9960 9961 /* anaPLL :: AControl3 :: i10Gbuf0 [01:01] */ 9962 #define ANAPLL_ACONTROL3_I10GBUF0_MASK 0x0002 9963 #define ANAPLL_ACONTROL3_I10GBUF0_ALIGN 0 9964 #define ANAPLL_ACONTROL3_I10GBUF0_BITS 1 9965 #define ANAPLL_ACONTROL3_I10GBUF0_SHIFT 1 9966 9967 /* anaPLL :: AControl3 :: i10Gbuf1 [00:00] */ 9968 #define ANAPLL_ACONTROL3_I10GBUF1_MASK 0x0001 9969 #define ANAPLL_ACONTROL3_I10GBUF1_ALIGN 0 9970 #define ANAPLL_ACONTROL3_I10GBUF1_BITS 1 9971 #define ANAPLL_ACONTROL3_I10GBUF1_SHIFT 0 9972 9973 9974 /**************************************************************************** 9975 * anaPLL :: AControl4 9976 */ 9977 /* anaPLL :: AControl4 :: en40lp [15:15] */ 9978 #define ANAPLL_ACONTROL4_EN40LP_MASK 0x8000 9979 #define ANAPLL_ACONTROL4_EN40LP_ALIGN 0 9980 #define ANAPLL_ACONTROL4_EN40LP_BITS 1 9981 #define ANAPLL_ACONTROL4_EN40LP_SHIFT 15 9982 9983 /* anaPLL :: AControl4 :: VCO_Imax [14:14] */ 9984 #define ANAPLL_ACONTROL4_VCO_IMAX_MASK 0x4000 9985 #define ANAPLL_ACONTROL4_VCO_IMAX_ALIGN 0 9986 #define ANAPLL_ACONTROL4_VCO_IMAX_BITS 1 9987 #define ANAPLL_ACONTROL4_VCO_IMAX_SHIFT 14 9988 9989 /* anaPLL :: AControl4 :: kvh_force [13:12] */ 9990 #define ANAPLL_ACONTROL4_KVH_FORCE_MASK 0x3000 9991 #define ANAPLL_ACONTROL4_KVH_FORCE_ALIGN 0 9992 #define ANAPLL_ACONTROL4_KVH_FORCE_BITS 2 9993 #define ANAPLL_ACONTROL4_KVH_FORCE_SHIFT 12 9994 9995 /* anaPLL :: AControl4 :: vvddr_bgb [11:11] */ 9996 #define ANAPLL_ACONTROL4_VVDDR_BGB_MASK 0x0800 9997 #define ANAPLL_ACONTROL4_VVDDR_BGB_ALIGN 0 9998 #define ANAPLL_ACONTROL4_VVDDR_BGB_BITS 1 9999 #define ANAPLL_ACONTROL4_VVDDR_BGB_SHIFT 11 10000 10001 /* anaPLL :: AControl4 :: comp_vth [10:10] */ 10002 #define ANAPLL_ACONTROL4_COMP_VTH_MASK 0x0400 10003 #define ANAPLL_ACONTROL4_COMP_VTH_ALIGN 0 10004 #define ANAPLL_ACONTROL4_COMP_VTH_BITS 1 10005 #define ANAPLL_ACONTROL4_COMP_VTH_SHIFT 10 10006 10007 /* anaPLL :: AControl4 :: pll2rx_clkbw [09:08] */ 10008 #define ANAPLL_ACONTROL4_PLL2RX_CLKBW_MASK 0x0300 10009 #define ANAPLL_ACONTROL4_PLL2RX_CLKBW_ALIGN 0 10010 #define ANAPLL_ACONTROL4_PLL2RX_CLKBW_BITS 2 10011 #define ANAPLL_ACONTROL4_PLL2RX_CLKBW_SHIFT 8 10012 10013 /* anaPLL :: AControl4 :: ctatadj [07:04] */ 10014 #define ANAPLL_ACONTROL4_CTATADJ_MASK 0x00f0 10015 #define ANAPLL_ACONTROL4_CTATADJ_ALIGN 0 10016 #define ANAPLL_ACONTROL4_CTATADJ_BITS 4 10017 #define ANAPLL_ACONTROL4_CTATADJ_SHIFT 4 10018 10019 /* anaPLL :: AControl4 :: ptatadj [03:00] */ 10020 #define ANAPLL_ACONTROL4_PTATADJ_MASK 0x000f 10021 #define ANAPLL_ACONTROL4_PTATADJ_ALIGN 0 10022 #define ANAPLL_ACONTROL4_PTATADJ_BITS 4 10023 #define ANAPLL_ACONTROL4_PTATADJ_SHIFT 0 10024 10025 10026 /**************************************************************************** 10027 * TSC_WC4_TSC_USER1_PktGen0 10028 */ 10029 /**************************************************************************** 10030 * PktGen0 :: PktGenCtrl1 10031 */ 10032 /* PktGen0 :: PktGenCtrl1 :: number_pkt [15:12] */ 10033 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_MASK 0xf000 10034 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_ALIGN 0 10035 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_BITS 4 10036 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_SHIFT 12 10037 10038 /* PktGen0 :: PktGenCtrl1 :: rx_pkt_check_en [11:11] */ 10039 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_MASK 0x0800 10040 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_ALIGN 0 10041 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_BITS 1 10042 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_SHIFT 11 10043 10044 /* PktGen0 :: PktGenCtrl1 :: rx_MSBUS_type [10:10] */ 10045 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_MASK 0x0400 10046 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_ALIGN 0 10047 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_BITS 1 10048 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_SHIFT 10 10049 10050 /* PktGen0 :: PktGenCtrl1 :: clr_crccnt [09:09] */ 10051 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_MASK 0x0200 10052 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_ALIGN 0 10053 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_BITS 1 10054 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_SHIFT 9 10055 10056 /* PktGen0 :: PktGenCtrl1 :: rx_port_sel [08:07] */ 10057 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_MASK 0x0180 10058 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_ALIGN 0 10059 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_BITS 2 10060 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_SHIFT 7 10061 10062 /* PktGen0 :: PktGenCtrl1 :: tx_prtp_en [06:06] */ 10063 #define PKTGEN0_PKTGENCTRL1_TX_PRTP_EN_MASK 0x0040 10064 #define PKTGEN0_PKTGENCTRL1_TX_PRTP_EN_ALIGN 0 10065 #define PKTGEN0_PKTGENCTRL1_TX_PRTP_EN_BITS 1 10066 #define PKTGEN0_PKTGENCTRL1_TX_PRTP_EN_SHIFT 6 10067 10068 /* PktGen0 :: PktGenCtrl1 :: prtp_data_pattern_sel [05:05] */ 10069 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_MASK 0x0020 10070 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_ALIGN 0 10071 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_BITS 1 10072 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_SHIFT 5 10073 10074 /* PktGen0 :: PktGenCtrl1 :: reserved0 [04:04] */ 10075 #define PKTGEN0_PKTGENCTRL1_RESERVED0_MASK 0x0010 10076 #define PKTGEN0_PKTGENCTRL1_RESERVED0_ALIGN 0 10077 #define PKTGEN0_PKTGENCTRL1_RESERVED0_BITS 1 10078 #define PKTGEN0_PKTGENCTRL1_RESERVED0_SHIFT 4 10079 10080 /* PktGen0 :: PktGenCtrl1 :: lpi_en [03:03] */ 10081 #define PKTGEN0_PKTGENCTRL1_LPI_EN_MASK 0x0008 10082 #define PKTGEN0_PKTGENCTRL1_LPI_EN_ALIGN 0 10083 #define PKTGEN0_PKTGENCTRL1_LPI_EN_BITS 1 10084 #define PKTGEN0_PKTGENCTRL1_LPI_EN_SHIFT 3 10085 10086 /* PktGen0 :: PktGenCtrl1 :: tx_test_port_sel [02:01] */ 10087 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_MASK 0x0006 10088 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_ALIGN 0 10089 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_BITS 2 10090 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_SHIFT 1 10091 10092 /* PktGen0 :: PktGenCtrl1 :: pkt_or_prtp [00:00] */ 10093 #define PKTGEN0_PKTGENCTRL1_PKT_OR_PRTP_MASK 0x0001 10094 #define PKTGEN0_PKTGENCTRL1_PKT_OR_PRTP_ALIGN 0 10095 #define PKTGEN0_PKTGENCTRL1_PKT_OR_PRTP_BITS 1 10096 #define PKTGEN0_PKTGENCTRL1_PKT_OR_PRTP_SHIFT 0 10097 10098 10099 /**************************************************************************** 10100 * PktGen0 :: PktGenCtrl2 10101 */ 10102 /* PktGen0 :: PktGenCtrl2 :: pktgen_en [15:15] */ 10103 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_MASK 0x8000 10104 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_ALIGN 0 10105 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_BITS 1 10106 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_SHIFT 15 10107 10108 /* PktGen0 :: PktGenCtrl2 :: tx_MSBUS_type [14:14] */ 10109 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_MASK 0x4000 10110 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_ALIGN 0 10111 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_BITS 1 10112 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_SHIFT 14 10113 10114 /* PktGen0 :: PktGenCtrl2 :: payload_type [13:11] */ 10115 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_MASK 0x3800 10116 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_ALIGN 0 10117 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_BITS 3 10118 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_SHIFT 11 10119 10120 /* PktGen0 :: PktGenCtrl2 :: pkt_size [10:05] */ 10121 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_MASK 0x07e0 10122 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_ALIGN 0 10123 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_BITS 6 10124 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_SHIFT 5 10125 10126 /* PktGen0 :: PktGenCtrl2 :: ipg_size [04:00] */ 10127 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_MASK 0x001f 10128 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_ALIGN 0 10129 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_BITS 5 10130 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_SHIFT 0 10131 10132 10133 /**************************************************************************** 10134 * PktGen0 :: PrtpControl 10135 */ 10136 /* PktGen0 :: PrtpControl :: reserved0 [15:09] */ 10137 #define PKTGEN0_PRTPCONTROL_RESERVED0_MASK 0xfe00 10138 #define PKTGEN0_PRTPCONTROL_RESERVED0_ALIGN 0 10139 #define PKTGEN0_PRTPCONTROL_RESERVED0_BITS 7 10140 #define PKTGEN0_PRTPCONTROL_RESERVED0_SHIFT 9 10141 10142 /* PktGen0 :: PrtpControl :: errgen_en [08:05] */ 10143 #define PKTGEN0_PRTPCONTROL_ERRGEN_EN_MASK 0x01e0 10144 #define PKTGEN0_PRTPCONTROL_ERRGEN_EN_ALIGN 0 10145 #define PKTGEN0_PRTPCONTROL_ERRGEN_EN_BITS 4 10146 #define PKTGEN0_PRTPCONTROL_ERRGEN_EN_SHIFT 5 10147 10148 /* PktGen0 :: PrtpControl :: rx_prtp_en [04:04] */ 10149 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_MASK 0x0010 10150 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_ALIGN 0 10151 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_BITS 1 10152 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_SHIFT 4 10153 10154 /* PktGen0 :: PrtpControl :: prtp_match_cnt [03:00] */ 10155 #define PKTGEN0_PRTPCONTROL_PRTP_MATCH_CNT_MASK 0x000f 10156 #define PKTGEN0_PRTPCONTROL_PRTP_MATCH_CNT_ALIGN 0 10157 #define PKTGEN0_PRTPCONTROL_PRTP_MATCH_CNT_BITS 4 10158 #define PKTGEN0_PRTPCONTROL_PRTP_MATCH_CNT_SHIFT 0 10159 10160 10161 /**************************************************************************** 10162 * PktGen0 :: CrcErrorCount 10163 */ 10164 /* PktGen0 :: CrcErrorCount :: crcerrcnt [15:00] */ 10165 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_MASK 0xffff 10166 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_ALIGN 0 10167 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_BITS 16 10168 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_SHIFT 0 10169 10170 10171 /**************************************************************************** 10172 * PktGen0 :: PrtpErrorCounter 10173 */ 10174 /* PktGen0 :: PrtpErrorCounter :: prtp_err_count [15:00] */ 10175 #define PKTGEN0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_MASK 0xffff 10176 #define PKTGEN0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_ALIGN 0 10177 #define PKTGEN0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_BITS 16 10178 #define PKTGEN0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_SHIFT 0 10179 10180 10181 /**************************************************************************** 10182 * PktGen0 :: PCS_seedA0 10183 */ 10184 /* PktGen0 :: PCS_seedA0 :: seedA0 [15:00] */ 10185 #define PKTGEN0_PCS_SEEDA0_SEEDA0_MASK 0xffff 10186 #define PKTGEN0_PCS_SEEDA0_SEEDA0_ALIGN 0 10187 #define PKTGEN0_PCS_SEEDA0_SEEDA0_BITS 16 10188 #define PKTGEN0_PCS_SEEDA0_SEEDA0_SHIFT 0 10189 10190 10191 /**************************************************************************** 10192 * PktGen0 :: PCS_seedA1 10193 */ 10194 /* PktGen0 :: PCS_seedA1 :: seedA1 [15:00] */ 10195 #define PKTGEN0_PCS_SEEDA1_SEEDA1_MASK 0xffff 10196 #define PKTGEN0_PCS_SEEDA1_SEEDA1_ALIGN 0 10197 #define PKTGEN0_PCS_SEEDA1_SEEDA1_BITS 16 10198 #define PKTGEN0_PCS_SEEDA1_SEEDA1_SHIFT 0 10199 10200 10201 /**************************************************************************** 10202 * PktGen0 :: PCS_seedA2 10203 */ 10204 /* PktGen0 :: PCS_seedA2 :: seedA2 [15:00] */ 10205 #define PKTGEN0_PCS_SEEDA2_SEEDA2_MASK 0xffff 10206 #define PKTGEN0_PCS_SEEDA2_SEEDA2_ALIGN 0 10207 #define PKTGEN0_PCS_SEEDA2_SEEDA2_BITS 16 10208 #define PKTGEN0_PCS_SEEDA2_SEEDA2_SHIFT 0 10209 10210 10211 /**************************************************************************** 10212 * PktGen0 :: PCS_seedA3 10213 */ 10214 /* PktGen0 :: PCS_seedA3 :: reserved0 [15:10] */ 10215 #define PKTGEN0_PCS_SEEDA3_RESERVED0_MASK 0xfc00 10216 #define PKTGEN0_PCS_SEEDA3_RESERVED0_ALIGN 0 10217 #define PKTGEN0_PCS_SEEDA3_RESERVED0_BITS 6 10218 #define PKTGEN0_PCS_SEEDA3_RESERVED0_SHIFT 10 10219 10220 /* PktGen0 :: PCS_seedA3 :: seedA3 [09:00] */ 10221 #define PKTGEN0_PCS_SEEDA3_SEEDA3_MASK 0x03ff 10222 #define PKTGEN0_PCS_SEEDA3_SEEDA3_ALIGN 0 10223 #define PKTGEN0_PCS_SEEDA3_SEEDA3_BITS 10 10224 #define PKTGEN0_PCS_SEEDA3_SEEDA3_SHIFT 0 10225 10226 10227 /**************************************************************************** 10228 * PktGen0 :: PCS_seedB0 10229 */ 10230 /* PktGen0 :: PCS_seedB0 :: seedB0 [15:00] */ 10231 #define PKTGEN0_PCS_SEEDB0_SEEDB0_MASK 0xffff 10232 #define PKTGEN0_PCS_SEEDB0_SEEDB0_ALIGN 0 10233 #define PKTGEN0_PCS_SEEDB0_SEEDB0_BITS 16 10234 #define PKTGEN0_PCS_SEEDB0_SEEDB0_SHIFT 0 10235 10236 10237 /**************************************************************************** 10238 * PktGen0 :: PCS_seedB1 10239 */ 10240 /* PktGen0 :: PCS_seedB1 :: seedB1 [15:00] */ 10241 #define PKTGEN0_PCS_SEEDB1_SEEDB1_MASK 0xffff 10242 #define PKTGEN0_PCS_SEEDB1_SEEDB1_ALIGN 0 10243 #define PKTGEN0_PCS_SEEDB1_SEEDB1_BITS 16 10244 #define PKTGEN0_PCS_SEEDB1_SEEDB1_SHIFT 0 10245 10246 10247 /**************************************************************************** 10248 * PktGen0 :: PCS_seedB2 10249 */ 10250 /* PktGen0 :: PCS_seedB2 :: seedB2 [15:00] */ 10251 #define PKTGEN0_PCS_SEEDB2_SEEDB2_MASK 0xffff 10252 #define PKTGEN0_PCS_SEEDB2_SEEDB2_ALIGN 0 10253 #define PKTGEN0_PCS_SEEDB2_SEEDB2_BITS 16 10254 #define PKTGEN0_PCS_SEEDB2_SEEDB2_SHIFT 0 10255 10256 10257 /**************************************************************************** 10258 * PktGen0 :: PCS_seedB3 10259 */ 10260 /* PktGen0 :: PCS_seedB3 :: reserved0 [15:10] */ 10261 #define PKTGEN0_PCS_SEEDB3_RESERVED0_MASK 0xfc00 10262 #define PKTGEN0_PCS_SEEDB3_RESERVED0_ALIGN 0 10263 #define PKTGEN0_PCS_SEEDB3_RESERVED0_BITS 6 10264 #define PKTGEN0_PCS_SEEDB3_RESERVED0_SHIFT 10 10265 10266 /* PktGen0 :: PCS_seedB3 :: seedB3 [09:00] */ 10267 #define PKTGEN0_PCS_SEEDB3_SEEDB3_MASK 0x03ff 10268 #define PKTGEN0_PCS_SEEDB3_SEEDB3_ALIGN 0 10269 #define PKTGEN0_PCS_SEEDB3_SEEDB3_BITS 10 10270 #define PKTGEN0_PCS_SEEDB3_SEEDB3_SHIFT 0 10271 10272 10273 /**************************************************************************** 10274 * TSC_WC4_TSC_USER1_PktGen1 10275 */ 10276 /**************************************************************************** 10277 * PktGen1 :: PayloadBytes 10278 */ 10279 /* PktGen1 :: PayloadBytes :: byte1 [15:08] */ 10280 #define PKTGEN1_PAYLOADBYTES_BYTE1_MASK 0xff00 10281 #define PKTGEN1_PAYLOADBYTES_BYTE1_ALIGN 0 10282 #define PKTGEN1_PAYLOADBYTES_BYTE1_BITS 8 10283 #define PKTGEN1_PAYLOADBYTES_BYTE1_SHIFT 8 10284 10285 /* PktGen1 :: PayloadBytes :: byte0 [07:00] */ 10286 #define PKTGEN1_PAYLOADBYTES_BYTE0_MASK 0x00ff 10287 #define PKTGEN1_PAYLOADBYTES_BYTE0_ALIGN 0 10288 #define PKTGEN1_PAYLOADBYTES_BYTE0_BITS 8 10289 #define PKTGEN1_PAYLOADBYTES_BYTE0_SHIFT 0 10290 10291 10292 /**************************************************************************** 10293 * PktGen1 :: ErrorMask4 10294 */ 10295 /* PktGen1 :: ErrorMask4 :: error_mask_79_64 [15:00] */ 10296 #define PKTGEN1_ERRORMASK4_ERROR_MASK_79_64_MASK 0xffff 10297 #define PKTGEN1_ERRORMASK4_ERROR_MASK_79_64_ALIGN 0 10298 #define PKTGEN1_ERRORMASK4_ERROR_MASK_79_64_BITS 16 10299 #define PKTGEN1_ERRORMASK4_ERROR_MASK_79_64_SHIFT 0 10300 10301 10302 /**************************************************************************** 10303 * PktGen1 :: ErrorMask3 10304 */ 10305 /* PktGen1 :: ErrorMask3 :: error_mask_63_48 [15:00] */ 10306 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_MASK 0xffff 10307 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_ALIGN 0 10308 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_BITS 16 10309 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_SHIFT 0 10310 10311 10312 /**************************************************************************** 10313 * PktGen1 :: ErrorMask2 10314 */ 10315 /* PktGen1 :: ErrorMask2 :: error_mask_47_32 [15:00] */ 10316 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_MASK 0xffff 10317 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_ALIGN 0 10318 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_BITS 16 10319 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_SHIFT 0 10320 10321 10322 /**************************************************************************** 10323 * PktGen1 :: ErrorMask1 10324 */ 10325 /* PktGen1 :: ErrorMask1 :: error_mask_31_16 [15:00] */ 10326 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_MASK 0xffff 10327 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_ALIGN 0 10328 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_BITS 16 10329 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_SHIFT 0 10330 10331 10332 /**************************************************************************** 10333 * PktGen1 :: ErrorMask0 10334 */ 10335 /* PktGen1 :: ErrorMask0 :: error_mask_15_0 [15:00] */ 10336 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_MASK 0xffff 10337 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_ALIGN 0 10338 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_BITS 16 10339 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_SHIFT 0 10340 10341 10342 /**************************************************************************** 10343 * PktGen1 :: Prtp_test_counts 10344 */ 10345 /* PktGen1 :: Prtp_test_counts :: sync_cnt [15:08] */ 10346 #define PKTGEN1_PRTP_TEST_COUNTS_SYNC_CNT_MASK 0xff00 10347 #define PKTGEN1_PRTP_TEST_COUNTS_SYNC_CNT_ALIGN 0 10348 #define PKTGEN1_PRTP_TEST_COUNTS_SYNC_CNT_BITS 8 10349 #define PKTGEN1_PRTP_TEST_COUNTS_SYNC_CNT_SHIFT 8 10350 10351 /* PktGen1 :: Prtp_test_counts :: block_cnt [07:00] */ 10352 #define PKTGEN1_PRTP_TEST_COUNTS_BLOCK_CNT_MASK 0x00ff 10353 #define PKTGEN1_PRTP_TEST_COUNTS_BLOCK_CNT_ALIGN 0 10354 #define PKTGEN1_PRTP_TEST_COUNTS_BLOCK_CNT_BITS 8 10355 #define PKTGEN1_PRTP_TEST_COUNTS_BLOCK_CNT_SHIFT 0 10356 10357 10358 /**************************************************************************** 10359 * TSC_WC4_TSC_USER1_PATGEN_256_0 10360 */ 10361 /**************************************************************************** 10362 * PATGEN_256_0 :: reg0 10363 */ 10364 /* PATGEN_256_0 :: reg0 :: reg0 [15:00] */ 10365 #define PATGEN_256_0_REG0_REG0_MASK 0xffff 10366 #define PATGEN_256_0_REG0_REG0_ALIGN 0 10367 #define PATGEN_256_0_REG0_REG0_BITS 16 10368 #define PATGEN_256_0_REG0_REG0_SHIFT 0 10369 10370 10371 /**************************************************************************** 10372 * PATGEN_256_0 :: reg1 10373 */ 10374 /* PATGEN_256_0 :: reg1 :: reg1 [15:00] */ 10375 #define PATGEN_256_0_REG1_REG1_MASK 0xffff 10376 #define PATGEN_256_0_REG1_REG1_ALIGN 0 10377 #define PATGEN_256_0_REG1_REG1_BITS 16 10378 #define PATGEN_256_0_REG1_REG1_SHIFT 0 10379 10380 10381 /**************************************************************************** 10382 * PATGEN_256_0 :: reg2 10383 */ 10384 /* PATGEN_256_0 :: reg2 :: reg2 [15:00] */ 10385 #define PATGEN_256_0_REG2_REG2_MASK 0xffff 10386 #define PATGEN_256_0_REG2_REG2_ALIGN 0 10387 #define PATGEN_256_0_REG2_REG2_BITS 16 10388 #define PATGEN_256_0_REG2_REG2_SHIFT 0 10389 10390 10391 /**************************************************************************** 10392 * PATGEN_256_0 :: reg3 10393 */ 10394 /* PATGEN_256_0 :: reg3 :: reg3 [15:00] */ 10395 #define PATGEN_256_0_REG3_REG3_MASK 0xffff 10396 #define PATGEN_256_0_REG3_REG3_ALIGN 0 10397 #define PATGEN_256_0_REG3_REG3_BITS 16 10398 #define PATGEN_256_0_REG3_REG3_SHIFT 0 10399 10400 10401 /**************************************************************************** 10402 * PATGEN_256_0 :: reg4 10403 */ 10404 /* PATGEN_256_0 :: reg4 :: reg4 [15:00] */ 10405 #define PATGEN_256_0_REG4_REG4_MASK 0xffff 10406 #define PATGEN_256_0_REG4_REG4_ALIGN 0 10407 #define PATGEN_256_0_REG4_REG4_BITS 16 10408 #define PATGEN_256_0_REG4_REG4_SHIFT 0 10409 10410 10411 /**************************************************************************** 10412 * PATGEN_256_0 :: reg5 10413 */ 10414 /* PATGEN_256_0 :: reg5 :: reg5 [15:00] */ 10415 #define PATGEN_256_0_REG5_REG5_MASK 0xffff 10416 #define PATGEN_256_0_REG5_REG5_ALIGN 0 10417 #define PATGEN_256_0_REG5_REG5_BITS 16 10418 #define PATGEN_256_0_REG5_REG5_SHIFT 0 10419 10420 10421 /**************************************************************************** 10422 * PATGEN_256_0 :: reg6 10423 */ 10424 /* PATGEN_256_0 :: reg6 :: reg6 [15:00] */ 10425 #define PATGEN_256_0_REG6_REG6_MASK 0xffff 10426 #define PATGEN_256_0_REG6_REG6_ALIGN 0 10427 #define PATGEN_256_0_REG6_REG6_BITS 16 10428 #define PATGEN_256_0_REG6_REG6_SHIFT 0 10429 10430 10431 /**************************************************************************** 10432 * PATGEN_256_0 :: reg7 10433 */ 10434 /* PATGEN_256_0 :: reg7 :: reg7 [15:00] */ 10435 #define PATGEN_256_0_REG7_REG7_MASK 0xffff 10436 #define PATGEN_256_0_REG7_REG7_ALIGN 0 10437 #define PATGEN_256_0_REG7_REG7_BITS 16 10438 #define PATGEN_256_0_REG7_REG7_SHIFT 0 10439 10440 10441 /**************************************************************************** 10442 * PATGEN_256_0 :: reg8 10443 */ 10444 /* PATGEN_256_0 :: reg8 :: reg8 [15:00] */ 10445 #define PATGEN_256_0_REG8_REG8_MASK 0xffff 10446 #define PATGEN_256_0_REG8_REG8_ALIGN 0 10447 #define PATGEN_256_0_REG8_REG8_BITS 16 10448 #define PATGEN_256_0_REG8_REG8_SHIFT 0 10449 10450 10451 /**************************************************************************** 10452 * PATGEN_256_0 :: reg9 10453 */ 10454 /* PATGEN_256_0 :: reg9 :: reg9 [15:00] */ 10455 #define PATGEN_256_0_REG9_REG9_MASK 0xffff 10456 #define PATGEN_256_0_REG9_REG9_ALIGN 0 10457 #define PATGEN_256_0_REG9_REG9_BITS 16 10458 #define PATGEN_256_0_REG9_REG9_SHIFT 0 10459 10460 10461 /**************************************************************************** 10462 * PATGEN_256_0 :: reg10 10463 */ 10464 /* PATGEN_256_0 :: reg10 :: reg10 [15:00] */ 10465 #define PATGEN_256_0_REG10_REG10_MASK 0xffff 10466 #define PATGEN_256_0_REG10_REG10_ALIGN 0 10467 #define PATGEN_256_0_REG10_REG10_BITS 16 10468 #define PATGEN_256_0_REG10_REG10_SHIFT 0 10469 10470 10471 /**************************************************************************** 10472 * PATGEN_256_0 :: reg11 10473 */ 10474 /* PATGEN_256_0 :: reg11 :: reg11 [15:00] */ 10475 #define PATGEN_256_0_REG11_REG11_MASK 0xffff 10476 #define PATGEN_256_0_REG11_REG11_ALIGN 0 10477 #define PATGEN_256_0_REG11_REG11_BITS 16 10478 #define PATGEN_256_0_REG11_REG11_SHIFT 0 10479 10480 10481 /**************************************************************************** 10482 * PATGEN_256_0 :: reg12 10483 */ 10484 /* PATGEN_256_0 :: reg12 :: reg12 [15:00] */ 10485 #define PATGEN_256_0_REG12_REG12_MASK 0xffff 10486 #define PATGEN_256_0_REG12_REG12_ALIGN 0 10487 #define PATGEN_256_0_REG12_REG12_BITS 16 10488 #define PATGEN_256_0_REG12_REG12_SHIFT 0 10489 10490 10491 /**************************************************************************** 10492 * PATGEN_256_0 :: reg13 10493 */ 10494 /* PATGEN_256_0 :: reg13 :: reg13 [15:00] */ 10495 #define PATGEN_256_0_REG13_REG13_MASK 0xffff 10496 #define PATGEN_256_0_REG13_REG13_ALIGN 0 10497 #define PATGEN_256_0_REG13_REG13_BITS 16 10498 #define PATGEN_256_0_REG13_REG13_SHIFT 0 10499 10500 10501 /**************************************************************************** 10502 * PATGEN_256_0 :: reg14 10503 */ 10504 /* PATGEN_256_0 :: reg14 :: reg14 [15:00] */ 10505 #define PATGEN_256_0_REG14_REG14_MASK 0xffff 10506 #define PATGEN_256_0_REG14_REG14_ALIGN 0 10507 #define PATGEN_256_0_REG14_REG14_BITS 16 10508 #define PATGEN_256_0_REG14_REG14_SHIFT 0 10509 10510 10511 /**************************************************************************** 10512 * TSC_WC4_TSC_USER1_PATGEN_256_1 10513 */ 10514 /**************************************************************************** 10515 * PATGEN_256_1 :: regF 10516 */ 10517 /* PATGEN_256_1 :: regF :: reg15 [15:00] */ 10518 #define PATGEN_256_1_REGF_REG15_MASK 0xffff 10519 #define PATGEN_256_1_REGF_REG15_ALIGN 0 10520 #define PATGEN_256_1_REGF_REG15_BITS 16 10521 #define PATGEN_256_1_REGF_REG15_SHIFT 0 10522 10523 10524 /**************************************************************************** 10525 * PATGEN_256_1 :: PrbsErrChkCfg 10526 */ 10527 /* PATGEN_256_1 :: PrbsErrChkCfg :: reserved0 [15:11] */ 10528 #define PATGEN_256_1_PRBSERRCHKCFG_RESERVED0_MASK 0xf800 10529 #define PATGEN_256_1_PRBSERRCHKCFG_RESERVED0_ALIGN 0 10530 #define PATGEN_256_1_PRBSERRCHKCFG_RESERVED0_BITS 5 10531 #define PATGEN_256_1_PRBSERRCHKCFG_RESERVED0_SHIFT 11 10532 10533 /* PATGEN_256_1 :: PrbsErrChkCfg :: good_blk_cnt_to_lock [10:08] */ 10534 #define PATGEN_256_1_PRBSERRCHKCFG_GOOD_BLK_CNT_TO_LOCK_MASK 0x0700 10535 #define PATGEN_256_1_PRBSERRCHKCFG_GOOD_BLK_CNT_TO_LOCK_ALIGN 0 10536 #define PATGEN_256_1_PRBSERRCHKCFG_GOOD_BLK_CNT_TO_LOCK_BITS 3 10537 #define PATGEN_256_1_PRBSERRCHKCFG_GOOD_BLK_CNT_TO_LOCK_SHIFT 8 10538 10539 /* PATGEN_256_1 :: PrbsErrChkCfg :: err_blk_cnt_to_unlock [07:03] */ 10540 #define PATGEN_256_1_PRBSERRCHKCFG_ERR_BLK_CNT_TO_UNLOCK_MASK 0x00f8 10541 #define PATGEN_256_1_PRBSERRCHKCFG_ERR_BLK_CNT_TO_UNLOCK_ALIGN 0 10542 #define PATGEN_256_1_PRBSERRCHKCFG_ERR_BLK_CNT_TO_UNLOCK_BITS 5 10543 #define PATGEN_256_1_PRBSERRCHKCFG_ERR_BLK_CNT_TO_UNLOCK_SHIFT 3 10544 10545 /* PATGEN_256_1 :: PrbsErrChkCfg :: burst_ignore_cnt [02:00] */ 10546 #define PATGEN_256_1_PRBSERRCHKCFG_BURST_IGNORE_CNT_MASK 0x0007 10547 #define PATGEN_256_1_PRBSERRCHKCFG_BURST_IGNORE_CNT_ALIGN 0 10548 #define PATGEN_256_1_PRBSERRCHKCFG_BURST_IGNORE_CNT_BITS 3 10549 #define PATGEN_256_1_PRBSERRCHKCFG_BURST_IGNORE_CNT_SHIFT 0 10550 10551 10552 /**************************************************************************** 10553 * TSC_XgxsBlk1 10554 */ 10555 /**************************************************************************** 10556 * XgxsBlk1 :: laneTest 10557 */ 10558 /* XgxsBlk1 :: laneTest :: reserved0 [15:09] */ 10559 #define XGXSBLK1_LANETEST_RESERVED0_MASK 0xfe00 10560 #define XGXSBLK1_LANETEST_RESERVED0_ALIGN 0 10561 #define XGXSBLK1_LANETEST_RESERVED0_BITS 7 10562 #define XGXSBLK1_LANETEST_RESERVED0_SHIFT 9 10563 10564 /* XgxsBlk1 :: laneTest :: pwrdwn_clks_en [08:08] */ 10565 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_MASK 0x0100 10566 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_ALIGN 0 10567 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_BITS 1 10568 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_SHIFT 8 10569 10570 /* XgxsBlk1 :: laneTest :: reserved1 [07:06] */ 10571 #define XGXSBLK1_LANETEST_RESERVED1_MASK 0x00c0 10572 #define XGXSBLK1_LANETEST_RESERVED1_ALIGN 0 10573 #define XGXSBLK1_LANETEST_RESERVED1_BITS 2 10574 #define XGXSBLK1_LANETEST_RESERVED1_SHIFT 6 10575 10576 /* XgxsBlk1 :: laneTest :: lfck_bypass [05:05] */ 10577 #define XGXSBLK1_LANETEST_LFCK_BYPASS_MASK 0x0020 10578 #define XGXSBLK1_LANETEST_LFCK_BYPASS_ALIGN 0 10579 #define XGXSBLK1_LANETEST_LFCK_BYPASS_BITS 1 10580 #define XGXSBLK1_LANETEST_LFCK_BYPASS_SHIFT 5 10581 10582 /* XgxsBlk1 :: laneTest :: reserved2 [04:00] */ 10583 #define XGXSBLK1_LANETEST_RESERVED2_MASK 0x001f 10584 #define XGXSBLK1_LANETEST_RESERVED2_ALIGN 0 10585 #define XGXSBLK1_LANETEST_RESERVED2_BITS 5 10586 #define XGXSBLK1_LANETEST_RESERVED2_SHIFT 0 10587 10588 10589 /**************************************************************************** 10590 * TSC_XgxsBlk4 10591 */ 10592 /**************************************************************************** 10593 * XgxsBlk4 :: xgxsStatus0 10594 */ 10595 /* XgxsBlk4 :: xgxsStatus0 :: status_en [15:15] */ 10596 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_MASK 0x8000 10597 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_ALIGN 0 10598 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_BITS 1 10599 #define XGXSBLK4_XGXSSTATUS0_STATUS_EN_SHIFT 15 10600 10601 /* XgxsBlk4 :: xgxsStatus0 :: reserved0 [14:01] */ 10602 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_MASK 0x7ffe 10603 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_ALIGN 0 10604 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_BITS 14 10605 #define XGXSBLK4_XGXSSTATUS0_RESERVED0_SHIFT 1 10606 10607 /* XgxsBlk4 :: xgxsStatus0 :: skew_status [00:00] */ 10608 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_MASK 0x0001 10609 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_ALIGN 0 10610 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_BITS 1 10611 #define XGXSBLK4_XGXSSTATUS0_SKEW_STATUS_SHIFT 0 10612 10613 10614 /**************************************************************************** 10615 * TSC_GP2 10616 */ 10617 /**************************************************************************** 10618 * GP2 :: reg_8 10619 */ 10620 /* GP2 :: reg_8 :: reserved0 [15:09] */ 10621 #define GP2_REG_8_RESERVED0_MASK 0xfe00 10622 #define GP2_REG_8_RESERVED0_ALIGN 0 10623 #define GP2_REG_8_RESERVED0_BITS 7 10624 #define GP2_REG_8_RESERVED0_SHIFT 9 10625 10626 /* GP2 :: reg_8 :: micro_init_done [08:08] */ 10627 #define GP2_REG_8_MICRO_INIT_DONE_MASK 0x0100 10628 #define GP2_REG_8_MICRO_INIT_DONE_ALIGN 0 10629 #define GP2_REG_8_MICRO_INIT_DONE_BITS 1 10630 #define GP2_REG_8_MICRO_INIT_DONE_SHIFT 8 10631 10632 /* GP2 :: reg_8 :: micro_fsm [07:04] */ 10633 #define GP2_REG_8_MICRO_FSM_MASK 0x00f0 10634 #define GP2_REG_8_MICRO_FSM_ALIGN 0 10635 #define GP2_REG_8_MICRO_FSM_BITS 4 10636 #define GP2_REG_8_MICRO_FSM_SHIFT 4 10637 10638 /* GP2 :: reg_8 :: micro_err [03:02] */ 10639 #define GP2_REG_8_MICRO_ERR_MASK 0x000c 10640 #define GP2_REG_8_MICRO_ERR_ALIGN 0 10641 #define GP2_REG_8_MICRO_ERR_BITS 2 10642 #define GP2_REG_8_MICRO_ERR_SHIFT 2 10643 10644 /* GP2 :: reg_8 :: micro_wdog [01:00] */ 10645 #define GP2_REG_8_MICRO_WDOG_MASK 0x0003 10646 #define GP2_REG_8_MICRO_WDOG_ALIGN 0 10647 #define GP2_REG_8_MICRO_WDOG_BITS 2 10648 #define GP2_REG_8_MICRO_WDOG_SHIFT 0 10649 10650 10651 /**************************************************************************** 10652 * TSC_CL72_Shared 10653 */ 10654 /**************************************************************************** 10655 * CL72_Shared :: AN_os_default_control 10656 */ 10657 /* CL72_Shared :: AN_os_default_control :: reserved0 [15:15] */ 10658 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 10659 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_RESERVED0_ALIGN 0 10660 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_RESERVED0_BITS 1 10661 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_RESERVED0_SHIFT 15 10662 10663 /* CL72_Shared :: AN_os_default_control :: tx_fir_tap_post_os_init_val [14:10] */ 10664 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_MASK 0x7c00 10665 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_ALIGN 0 10666 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_BITS 5 10667 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_SHIFT 10 10668 10669 /* CL72_Shared :: AN_os_default_control :: tx_fir_tap_main_os_init_val [09:04] */ 10670 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_MASK 0x03f0 10671 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_ALIGN 0 10672 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_BITS 6 10673 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_SHIFT 4 10674 10675 /* CL72_Shared :: AN_os_default_control :: tx_fir_tap_pre_os_init_val [03:00] */ 10676 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_MASK 0x000f 10677 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_ALIGN 0 10678 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_BITS 4 10679 #define CL72_SHARED_AN_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_SHIFT 0 10680 10681 10682 /**************************************************************************** 10683 * CL72_Shared :: AN_br_default_control 10684 */ 10685 /* CL72_Shared :: AN_br_default_control :: reserved0 [15:15] */ 10686 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 10687 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_RESERVED0_ALIGN 0 10688 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_RESERVED0_BITS 1 10689 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_RESERVED0_SHIFT 15 10690 10691 /* CL72_Shared :: AN_br_default_control :: tx_fir_tap_post_br_init_val [14:10] */ 10692 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_MASK 0x7c00 10693 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_ALIGN 0 10694 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_BITS 5 10695 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_SHIFT 10 10696 10697 /* CL72_Shared :: AN_br_default_control :: tx_fir_tap_main_br_init_val [09:04] */ 10698 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_MASK 0x03f0 10699 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_ALIGN 0 10700 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_BITS 6 10701 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_SHIFT 4 10702 10703 /* CL72_Shared :: AN_br_default_control :: tx_fir_tap_pre_br_init_val [03:00] */ 10704 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_MASK 0x000f 10705 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_ALIGN 0 10706 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_BITS 4 10707 #define CL72_SHARED_AN_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_SHIFT 0 10708 10709 10710 /**************************************************************************** 10711 * CL72_Shared :: AN_twop5_default_control 10712 */ 10713 /* CL72_Shared :: AN_twop5_default_control :: cl72_en_mask [15:15] */ 10714 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_CL72_EN_MASK_MASK 0x8000 10715 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_CL72_EN_MASK_ALIGN 0 10716 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_CL72_EN_MASK_BITS 1 10717 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_CL72_EN_MASK_SHIFT 15 10718 10719 /* CL72_Shared :: AN_twop5_default_control :: tx_fir_tap_post_2p5_init_val [14:10] */ 10720 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_MASK 0x7c00 10721 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_ALIGN 0 10722 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_BITS 5 10723 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_POST_2P5_INIT_VAL_SHIFT 10 10724 10725 /* CL72_Shared :: AN_twop5_default_control :: tx_fir_tap_main_2p5_init_val [09:04] */ 10726 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_MASK 0x03f0 10727 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_ALIGN 0 10728 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_BITS 6 10729 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_2P5_INIT_VAL_SHIFT 4 10730 10731 /* CL72_Shared :: AN_twop5_default_control :: tx_fir_tap_pre_2p5_init_val [03:00] */ 10732 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_MASK 0x000f 10733 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_ALIGN 0 10734 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_BITS 4 10735 #define CL72_SHARED_AN_TWOP5_DEFAULT_CONTROL_TX_FIR_TAP_PRE_2P5_INIT_VAL_SHIFT 0 10736 10737 10738 /**************************************************************************** 10739 * CL72_Shared :: CL72_tap_limit_control 10740 */ 10741 /* CL72_Shared :: CL72_tap_limit_control :: reserved0 [15:15] */ 10742 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_RESERVED0_MASK 0x8000 10743 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_RESERVED0_ALIGN 0 10744 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_RESERVED0_BITS 1 10745 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_RESERVED0_SHIFT 15 10746 10747 /* CL72_Shared :: CL72_tap_limit_control :: post_tap_limit [14:10] */ 10748 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_MASK 0x7c00 10749 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_ALIGN 0 10750 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_BITS 5 10751 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_SHIFT 10 10752 10753 /* CL72_Shared :: CL72_tap_limit_control :: main_tap_limit [09:04] */ 10754 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_MASK 0x03f0 10755 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_ALIGN 0 10756 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_BITS 6 10757 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_SHIFT 4 10758 10759 /* CL72_Shared :: CL72_tap_limit_control :: pre_tap_limit [03:00] */ 10760 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_MASK 0x000f 10761 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_ALIGN 0 10762 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_BITS 4 10763 #define CL72_SHARED_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_SHIFT 0 10764 10765 10766 /**************************************************************************** 10767 * CL72_Shared :: CL72_misc3_control 10768 */ 10769 /* CL72_Shared :: CL72_misc3_control :: cl72_en_mask_en [15:00] */ 10770 #define CL72_SHARED_CL72_MISC3_CONTROL_CL72_EN_MASK_EN_MASK 0xffff 10771 #define CL72_SHARED_CL72_MISC3_CONTROL_CL72_EN_MASK_EN_ALIGN 0 10772 #define CL72_SHARED_CL72_MISC3_CONTROL_CL72_EN_MASK_EN_BITS 16 10773 #define CL72_SHARED_CL72_MISC3_CONTROL_CL72_EN_MASK_EN_SHIFT 0 10774 10775 10776 /**************************************************************************** 10777 * CL72_Shared :: CL72_tap_preset_control 10778 */ 10779 /* CL72_Shared :: CL72_tap_preset_control :: reserved0 [15:09] */ 10780 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_RESERVED0_MASK 0xfe00 10781 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_RESERVED0_ALIGN 0 10782 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_RESERVED0_BITS 7 10783 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_RESERVED0_SHIFT 9 10784 10785 /* CL72_Shared :: CL72_tap_preset_control :: pre_init_val [08:05] */ 10786 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_MASK 0x01e0 10787 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_ALIGN 0 10788 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_BITS 4 10789 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_SHIFT 5 10790 10791 /* CL72_Shared :: CL72_tap_preset_control :: post_init_val [04:00] */ 10792 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_MASK 0x001f 10793 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_ALIGN 0 10794 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_BITS 5 10795 #define CL72_SHARED_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_SHIFT 0 10796 10797 10798 /**************************************************************************** 10799 * CL72_Shared :: CL72_debug_1_register 10800 */ 10801 /* CL72_Shared :: CL72_debug_1_register :: reserved0 [15:12] */ 10802 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_RESERVED0_MASK 0xf000 10803 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_RESERVED0_ALIGN 0 10804 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_RESERVED0_BITS 4 10805 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_RESERVED0_SHIFT 12 10806 10807 /* CL72_Shared :: CL72_debug_1_register :: tap_max_val [11:06] */ 10808 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_MASK 0x0fc0 10809 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_ALIGN 0 10810 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_BITS 6 10811 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_SHIFT 6 10812 10813 /* CL72_Shared :: CL72_debug_1_register :: tap_min_val [05:00] */ 10814 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_MASK 0x003f 10815 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_ALIGN 0 10816 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_BITS 6 10817 #define CL72_SHARED_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_SHIFT 0 10818 10819 10820 /**************************************************************************** 10821 * CL72_Shared :: cl72_debug_2_register_type 10822 */ 10823 /* CL72_Shared :: cl72_debug_2_register_type :: reserved0 [15:05] */ 10824 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_RESERVED0_MASK 0xffe0 10825 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_RESERVED0_ALIGN 0 10826 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_RESERVED0_BITS 11 10827 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_RESERVED0_SHIFT 5 10828 10829 /* CL72_Shared :: cl72_debug_2_register_type :: cl72_prbs_type [04:04] */ 10830 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_CL72_PRBS_TYPE_MASK 0x0010 10831 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_CL72_PRBS_TYPE_ALIGN 0 10832 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_CL72_PRBS_TYPE_BITS 1 10833 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_CL72_PRBS_TYPE_SHIFT 4 10834 10835 /* CL72_Shared :: cl72_debug_2_register_type :: cl72_prbs_enable [03:00] */ 10836 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_CL72_PRBS_ENABLE_MASK 0x000f 10837 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_CL72_PRBS_ENABLE_ALIGN 0 10838 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_CL72_PRBS_ENABLE_BITS 4 10839 #define CL72_SHARED_CL72_DEBUG_2_REGISTER_TYPE_CL72_PRBS_ENABLE_SHIFT 0 10840 10841 10842 /**************************************************************************** 10843 * TSC_CL82_Shared 10844 */ 10845 /**************************************************************************** 10846 * CL82_Shared :: cl82_rx_am_timer 10847 */ 10848 /* CL82_Shared :: cl82_rx_am_timer :: AM_timer_init_rx_val [15:00] */ 10849 #define CL82_SHARED_CL82_RX_AM_TIMER_AM_TIMER_INIT_RX_VAL_MASK 0xffff 10850 #define CL82_SHARED_CL82_RX_AM_TIMER_AM_TIMER_INIT_RX_VAL_ALIGN 0 10851 #define CL82_SHARED_CL82_RX_AM_TIMER_AM_TIMER_INIT_RX_VAL_BITS 16 10852 #define CL82_SHARED_CL82_RX_AM_TIMER_AM_TIMER_INIT_RX_VAL_SHIFT 0 10853 10854 10855 /**************************************************************************** 10856 * TSC_CL82_AM_regs 10857 */ 10858 /**************************************************************************** 10859 * CL82_AM_regs :: lane_0_am_byte10 10860 */ 10861 /* CL82_AM_regs :: lane_0_am_byte10 :: LANE_0_AM_1_0 [15:00] */ 10862 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_MASK 0xffff 10863 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_ALIGN 0 10864 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_BITS 16 10865 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_SHIFT 0 10866 10867 10868 /**************************************************************************** 10869 * CL82_AM_regs :: lane_1_am_byte10 10870 */ 10871 /* CL82_AM_regs :: lane_1_am_byte10 :: LANE_1_AM_1_0 [15:00] */ 10872 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_MASK 0xffff 10873 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_ALIGN 0 10874 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_BITS 16 10875 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_SHIFT 0 10876 10877 10878 /**************************************************************************** 10879 * CL82_AM_regs :: lanes_1_0_am_byte2 10880 */ 10881 /* CL82_AM_regs :: lanes_1_0_am_byte2 :: LANE_1_AM_0 [15:08] */ 10882 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_0_MASK 0xff00 10883 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_0_ALIGN 0 10884 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_0_BITS 8 10885 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_0_SHIFT 8 10886 10887 /* CL82_AM_regs :: lanes_1_0_am_byte2 :: LANE_0_AM_0 [07:00] */ 10888 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_0_MASK 0x00ff 10889 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_0_ALIGN 0 10890 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_0_BITS 8 10891 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_0_SHIFT 0 10892 10893 10894 /**************************************************************************** 10895 * TSC_CL82_AM_regs_tsc_12 10896 */ 10897 /**************************************************************************** 10898 * CL82_AM_regs_tsc_12 :: lane_2_am_byte10 10899 */ 10900 /* CL82_AM_regs_tsc_12 :: lane_2_am_byte10 :: LANE_2_AM_1_0 [15:00] */ 10901 #define CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10_LANE_2_AM_1_0_MASK 0xffff 10902 #define CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10_LANE_2_AM_1_0_ALIGN 0 10903 #define CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10_LANE_2_AM_1_0_BITS 16 10904 #define CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10_LANE_2_AM_1_0_SHIFT 0 10905 10906 10907 /**************************************************************************** 10908 * CL82_AM_regs_tsc_12 :: lane_3_am_byte10 10909 */ 10910 /* CL82_AM_regs_tsc_12 :: lane_3_am_byte10 :: LANE_3_AM_1_0 [15:00] */ 10911 #define CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10_LANE_3_AM_1_0_MASK 0xffff 10912 #define CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10_LANE_3_AM_1_0_ALIGN 0 10913 #define CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10_LANE_3_AM_1_0_BITS 16 10914 #define CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10_LANE_3_AM_1_0_SHIFT 0 10915 10916 10917 /**************************************************************************** 10918 * CL82_AM_regs_tsc_12 :: lanes_3_2_am_byte2 10919 */ 10920 /* CL82_AM_regs_tsc_12 :: lanes_3_2_am_byte2 :: LANE_3_AM_2 [15:08] */ 10921 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_3_AM_2_MASK 0xff00 10922 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_3_AM_2_ALIGN 0 10923 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_3_AM_2_BITS 8 10924 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_3_AM_2_SHIFT 8 10925 10926 /* CL82_AM_regs_tsc_12 :: lanes_3_2_am_byte2 :: LANE_2_AM_2 [07:00] */ 10927 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_2_AM_2_MASK 0x00ff 10928 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_2_AM_2_ALIGN 0 10929 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_2_AM_2_BITS 8 10930 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_2_AM_2_SHIFT 0 10931 10932 10933 /**************************************************************************** 10934 * TSC_TX_X1_Control0 10935 */ 10936 /**************************************************************************** 10937 * TX_X1_Control0 :: tx_pi_control1 10938 */ 10939 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_integ_sat_sel [15:15] */ 10940 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_MASK 0x8000 10941 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_ALIGN 0 10942 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_BITS 1 10943 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_SHIFT 15 10944 10945 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_integ_sat_1_or_2 [14:14] */ 10946 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_MASK 0x4000 10947 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_ALIGN 0 10948 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_BITS 1 10949 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_SHIFT 14 10950 10951 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_phase_invert [13:13] */ 10952 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_MASK 0x2000 10953 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_ALIGN 0 10954 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_BITS 1 10955 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_SHIFT 13 10956 10957 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_phase_step_mult [12:12] */ 10958 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_MASK 0x1000 10959 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_ALIGN 0 10960 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_BITS 1 10961 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_SHIFT 12 10962 10963 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_phase_step_dir [11:11] */ 10964 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_MASK 0x0800 10965 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_ALIGN 0 10966 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_BITS 1 10967 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_SHIFT 11 10968 10969 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_phase_step [10:09] */ 10970 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MASK 0x0600 10971 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_ALIGN 0 10972 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_BITS 2 10973 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STEP_SHIFT 9 10974 10975 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_phase_delta [08:04] */ 10976 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_MASK 0x01f0 10977 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_ALIGN 0 10978 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_BITS 5 10979 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_SHIFT 4 10980 10981 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_phase_strobe [03:03] */ 10982 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_MASK 0x0008 10983 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_ALIGN 0 10984 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_BITS 1 10985 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_SHIFT 3 10986 10987 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_phase_override [02:02] */ 10988 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_MASK 0x0004 10989 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_ALIGN 0 10990 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_BITS 1 10991 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_SHIFT 2 10992 10993 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_bypass_mode [01:01] */ 10994 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_MASK 0x0002 10995 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_ALIGN 0 10996 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_BITS 1 10997 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_SHIFT 1 10998 10999 /* TX_X1_Control0 :: tx_pi_control1 :: tx_pi_en [00:00] */ 11000 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_EN_MASK 0x0001 11001 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_EN_ALIGN 0 11002 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_EN_BITS 1 11003 #define TX_X1_CONTROL0_TX_PI_CONTROL1_TX_PI_EN_SHIFT 0 11004 11005 11006 /**************************************************************************** 11007 * TX_X1_Control0 :: tx_pi_control2 11008 */ 11009 /* TX_X1_Control0 :: tx_pi_control2 :: tx_pi_sm_timer_sel [15:14] */ 11010 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_MASK 0xc000 11011 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_ALIGN 0 11012 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_BITS 2 11013 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_SHIFT 14 11014 11015 /* TX_X1_Control0 :: tx_pi_control2 :: tx_pi_sm_done_override [13:13] */ 11016 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_MASK 0x2000 11017 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_ALIGN 0 11018 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_BITS 1 11019 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_SHIFT 13 11020 11021 /* TX_X1_Control0 :: tx_pi_control2 :: tx_pi_sm_en_override [12:12] */ 11022 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_MASK 0x1000 11023 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_ALIGN 0 11024 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_BITS 1 11025 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_SHIFT 12 11026 11027 /* TX_X1_Control0 :: tx_pi_control2 :: reserved0 [11:09] */ 11028 #define TX_X1_CONTROL0_TX_PI_CONTROL2_RESERVED0_MASK 0x0e00 11029 #define TX_X1_CONTROL0_TX_PI_CONTROL2_RESERVED0_ALIGN 0 11030 #define TX_X1_CONTROL0_TX_PI_CONTROL2_RESERVED0_BITS 3 11031 #define TX_X1_CONTROL0_TX_PI_CONTROL2_RESERVED0_SHIFT 9 11032 11033 /* TX_X1_Control0 :: tx_pi_control2 :: tx_pi_ckgate_en [08:08] */ 11034 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_CKGATE_EN_MASK 0x0100 11035 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_CKGATE_EN_ALIGN 0 11036 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_CKGATE_EN_BITS 1 11037 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_CKGATE_EN_SHIFT 8 11038 11039 /* TX_X1_Control0 :: tx_pi_control2 :: tx_pi_loopback_mode [07:07] */ 11040 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_MASK 0x0080 11041 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_ALIGN 0 11042 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_BITS 1 11043 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_SHIFT 7 11044 11045 /* TX_X1_Control0 :: tx_pi_control2 :: tx_pi_sm_bypass [06:06] */ 11046 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_BYPASS_MASK 0x0040 11047 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_BYPASS_ALIGN 0 11048 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_BYPASS_BITS 1 11049 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_SM_BYPASS_SHIFT 6 11050 11051 /* TX_X1_Control0 :: tx_pi_control2 :: tx_pi_integ_reg_clr [05:05] */ 11052 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_MASK 0x0020 11053 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_ALIGN 0 11054 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_BITS 1 11055 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_SHIFT 5 11056 11057 /* TX_X1_Control0 :: tx_pi_control2 :: tx_pi_bwsel_integ [04:02] */ 11058 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_MASK 0x001c 11059 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_ALIGN 0 11060 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_BITS 3 11061 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_SHIFT 2 11062 11063 /* TX_X1_Control0 :: tx_pi_control2 :: tx_pi_rx_lane_sel [01:00] */ 11064 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_MASK 0x0003 11065 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_ALIGN 0 11066 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_BITS 2 11067 #define TX_X1_CONTROL0_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_SHIFT 0 11068 11069 11070 /**************************************************************************** 11071 * TX_X1_Control0 :: tx_pi_control3 11072 */ 11073 /* TX_X1_Control0 :: tx_pi_control3 :: tx_pi_freq_override_val [15:01] */ 11074 #define TX_X1_CONTROL0_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_MASK 0xfffe 11075 #define TX_X1_CONTROL0_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_ALIGN 0 11076 #define TX_X1_CONTROL0_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_BITS 15 11077 #define TX_X1_CONTROL0_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_SHIFT 1 11078 11079 /* TX_X1_Control0 :: tx_pi_control3 :: tx_pi_freq_override_en [00:00] */ 11080 #define TX_X1_CONTROL0_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_MASK 0x0001 11081 #define TX_X1_CONTROL0_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_ALIGN 0 11082 #define TX_X1_CONTROL0_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_BITS 1 11083 #define TX_X1_CONTROL0_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_SHIFT 0 11084 11085 11086 /**************************************************************************** 11087 * TSC_TX_X1_status0 11088 */ 11089 /**************************************************************************** 11090 * TX_X1_status0 :: tx_pi_status1 11091 */ 11092 /* TX_X1_status0 :: tx_pi_status1 :: reserved0 [15:15] */ 11093 #define TX_X1_STATUS0_TX_PI_STATUS1_RESERVED0_MASK 0x8000 11094 #define TX_X1_STATUS0_TX_PI_STATUS1_RESERVED0_ALIGN 0 11095 #define TX_X1_STATUS0_TX_PI_STATUS1_RESERVED0_BITS 1 11096 #define TX_X1_STATUS0_TX_PI_STATUS1_RESERVED0_SHIFT 15 11097 11098 /* TX_X1_status0 :: tx_pi_status1 :: tx_pi_integ_reg [14:00] */ 11099 #define TX_X1_STATUS0_TX_PI_STATUS1_TX_PI_INTEG_REG_MASK 0x7fff 11100 #define TX_X1_STATUS0_TX_PI_STATUS1_TX_PI_INTEG_REG_ALIGN 0 11101 #define TX_X1_STATUS0_TX_PI_STATUS1_TX_PI_INTEG_REG_BITS 15 11102 #define TX_X1_STATUS0_TX_PI_STATUS1_TX_PI_INTEG_REG_SHIFT 0 11103 11104 11105 /**************************************************************************** 11106 * TX_X1_status0 :: tx_pi_status2 11107 */ 11108 /* TX_X1_status0 :: tx_pi_status2 :: reserved0 [15:07] */ 11109 #define TX_X1_STATUS0_TX_PI_STATUS2_RESERVED0_MASK 0xff80 11110 #define TX_X1_STATUS0_TX_PI_STATUS2_RESERVED0_ALIGN 0 11111 #define TX_X1_STATUS0_TX_PI_STATUS2_RESERVED0_BITS 9 11112 #define TX_X1_STATUS0_TX_PI_STATUS2_RESERVED0_SHIFT 7 11113 11114 /* TX_X1_status0 :: tx_pi_status2 :: tx_pi_phase_cntr [06:00] */ 11115 #define TX_X1_STATUS0_TX_PI_STATUS2_TX_PI_PHASE_CNTR_MASK 0x007f 11116 #define TX_X1_STATUS0_TX_PI_STATUS2_TX_PI_PHASE_CNTR_ALIGN 0 11117 #define TX_X1_STATUS0_TX_PI_STATUS2_TX_PI_PHASE_CNTR_BITS 7 11118 #define TX_X1_STATUS0_TX_PI_STATUS2_TX_PI_PHASE_CNTR_SHIFT 0 11119 11120 11121 /**************************************************************************** 11122 * TX_X1_status0 :: tla_status 11123 */ 11124 /* TX_X1_status0 :: tla_status :: reserved0 [15:05] */ 11125 #define TX_X1_STATUS0_TLA_STATUS_RESERVED0_MASK 0xffe0 11126 #define TX_X1_STATUS0_TLA_STATUS_RESERVED0_ALIGN 0 11127 #define TX_X1_STATUS0_TLA_STATUS_RESERVED0_BITS 11 11128 #define TX_X1_STATUS0_TLA_STATUS_RESERVED0_SHIFT 5 11129 11130 /* TX_X1_status0 :: tla_status :: tla_pll_sequencer_fsm_status [04:00] */ 11131 #define TX_X1_STATUS0_TLA_STATUS_TLA_PLL_SEQUENCER_FSM_STATUS_MASK 0x001f 11132 #define TX_X1_STATUS0_TLA_STATUS_TLA_PLL_SEQUENCER_FSM_STATUS_ALIGN 0 11133 #define TX_X1_STATUS0_TLA_STATUS_TLA_PLL_SEQUENCER_FSM_STATUS_BITS 5 11134 #define TX_X1_STATUS0_TLA_STATUS_TLA_PLL_SEQUENCER_FSM_STATUS_SHIFT 0 11135 #define TX_X1_STATUS0_TLA_STATUS_TLA_PLL_SEQUENCER_FSM_STATUS_INIT 1 11136 #define TX_X1_STATUS0_TLA_STATUS_TLA_PLL_SEQUENCER_FSM_STATUS_PLL_LOCKED 2 11137 #define TX_X1_STATUS0_TLA_STATUS_TLA_PLL_SEQUENCER_FSM_STATUS_RESET_PLL 4 11138 #define TX_X1_STATUS0_TLA_STATUS_TLA_PLL_SEQUENCER_FSM_STATUS_CHANGE_PLL_MODE 8 11139 #define TX_X1_STATUS0_TLA_STATUS_TLA_PLL_SEQUENCER_FSM_STATUS_PLL_SWITCH 16 11140 11141 11142 /**************************************************************************** 11143 * TSC_RX_X1_Control0 11144 */ 11145 /**************************************************************************** 11146 * RX_X1_Control0 :: decode_control_0 11147 */ 11148 /* RX_X1_Control0 :: decode_control_0 :: reserved0 [15:12] */ 11149 #define RX_X1_CONTROL0_DECODE_CONTROL_0_RESERVED0_MASK 0xf000 11150 #define RX_X1_CONTROL0_DECODE_CONTROL_0_RESERVED0_ALIGN 0 11151 #define RX_X1_CONTROL0_DECODE_CONTROL_0_RESERVED0_BITS 4 11152 #define RX_X1_CONTROL0_DECODE_CONTROL_0_RESERVED0_SHIFT 12 11153 11154 /* RX_X1_Control0 :: decode_control_0 :: scwCount [11:08] */ 11155 #define RX_X1_CONTROL0_DECODE_CONTROL_0_SCWCOUNT_MASK 0x0f00 11156 #define RX_X1_CONTROL0_DECODE_CONTROL_0_SCWCOUNT_ALIGN 0 11157 #define RX_X1_CONTROL0_DECODE_CONTROL_0_SCWCOUNT_BITS 4 11158 #define RX_X1_CONTROL0_DECODE_CONTROL_0_SCWCOUNT_SHIFT 8 11159 11160 /* RX_X1_Control0 :: decode_control_0 :: gcwCount [07:04] */ 11161 #define RX_X1_CONTROL0_DECODE_CONTROL_0_GCWCOUNT_MASK 0x00f0 11162 #define RX_X1_CONTROL0_DECODE_CONTROL_0_GCWCOUNT_ALIGN 0 11163 #define RX_X1_CONTROL0_DECODE_CONTROL_0_GCWCOUNT_BITS 4 11164 #define RX_X1_CONTROL0_DECODE_CONTROL_0_GCWCOUNT_SHIFT 4 11165 11166 /* RX_X1_Control0 :: decode_control_0 :: hystCount [03:00] */ 11167 #define RX_X1_CONTROL0_DECODE_CONTROL_0_HYSTCOUNT_MASK 0x000f 11168 #define RX_X1_CONTROL0_DECODE_CONTROL_0_HYSTCOUNT_ALIGN 0 11169 #define RX_X1_CONTROL0_DECODE_CONTROL_0_HYSTCOUNT_BITS 4 11170 #define RX_X1_CONTROL0_DECODE_CONTROL_0_HYSTCOUNT_SHIFT 0 11171 11172 11173 /**************************************************************************** 11174 * RX_X1_Control0 :: decode_control_1 11175 */ 11176 /* RX_X1_Control0 :: decode_control_1 :: SET_BER_WINDOW_512 [15:15] */ 11177 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_MASK 0x8000 11178 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_ALIGN 0 11179 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_BITS 1 11180 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_SHIFT 15 11181 11182 /* RX_X1_Control0 :: decode_control_1 :: CL82_BER_LIMIT [14:08] */ 11183 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_MASK 0x7f00 11184 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_ALIGN 0 11185 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_BITS 7 11186 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_SHIFT 8 11187 11188 /* RX_X1_Control0 :: decode_control_1 :: CL49_BER_LIMIT [07:02] */ 11189 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_MASK 0x00fc 11190 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_ALIGN 0 11191 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_BITS 6 11192 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_SHIFT 2 11193 11194 /* RX_X1_Control0 :: decode_control_1 :: reserved0 [01:00] */ 11195 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_MASK 0x0003 11196 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_ALIGN 0 11197 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_BITS 2 11198 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_SHIFT 0 11199 11200 11201 /**************************************************************************** 11202 * RX_X1_Control0 :: deskew_windows 11203 */ 11204 /* RX_X1_Control0 :: deskew_windows :: reserved0 [15:12] */ 11205 #define RX_X1_CONTROL0_DESKEW_WINDOWS_RESERVED0_MASK 0xf000 11206 #define RX_X1_CONTROL0_DESKEW_WINDOWS_RESERVED0_ALIGN 0 11207 #define RX_X1_CONTROL0_DESKEW_WINDOWS_RESERVED0_BITS 4 11208 #define RX_X1_CONTROL0_DESKEW_WINDOWS_RESERVED0_SHIFT 12 11209 11210 /* RX_X1_Control0 :: deskew_windows :: cl82_dswin [11:07] */ 11211 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_MASK 0x0f80 11212 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_ALIGN 0 11213 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_BITS 5 11214 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_SHIFT 7 11215 11216 /* RX_X1_Control0 :: deskew_windows :: cl48_dswin64b66b [06:04] */ 11217 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN64B66B_MASK 0x0070 11218 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN64B66B_ALIGN 0 11219 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN64B66B_BITS 3 11220 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN64B66B_SHIFT 4 11221 11222 /* RX_X1_Control0 :: deskew_windows :: cl48_dswin8b10b [03:00] */ 11223 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN8B10B_MASK 0x000f 11224 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN8B10B_ALIGN 0 11225 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN8B10B_BITS 4 11226 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN8B10B_SHIFT 0 11227 11228 11229 /**************************************************************************** 11230 * RX_X1_Control0 :: cx4_sigdet_filter 11231 */ 11232 /* RX_X1_Control0 :: cx4_sigdet_filter :: reserved0 [15:14] */ 11233 #define RX_X1_CONTROL0_CX4_SIGDET_FILTER_RESERVED0_MASK 0xc000 11234 #define RX_X1_CONTROL0_CX4_SIGDET_FILTER_RESERVED0_ALIGN 0 11235 #define RX_X1_CONTROL0_CX4_SIGDET_FILTER_RESERVED0_BITS 2 11236 #define RX_X1_CONTROL0_CX4_SIGDET_FILTER_RESERVED0_SHIFT 14 11237 11238 /* RX_X1_Control0 :: cx4_sigdet_filter :: Cx4_Signal_detect_filter_period [13:00] */ 11239 #define RX_X1_CONTROL0_CX4_SIGDET_FILTER_CX4_SIGNAL_DETECT_FILTER_PERIOD_MASK 0x3fff 11240 #define RX_X1_CONTROL0_CX4_SIGDET_FILTER_CX4_SIGNAL_DETECT_FILTER_PERIOD_ALIGN 0 11241 #define RX_X1_CONTROL0_CX4_SIGDET_FILTER_CX4_SIGNAL_DETECT_FILTER_PERIOD_BITS 14 11242 #define RX_X1_CONTROL0_CX4_SIGDET_FILTER_CX4_SIGNAL_DETECT_FILTER_PERIOD_SHIFT 0 11243 11244 11245 /**************************************************************************** 11246 * TSC_RX_X1_Control1 11247 */ 11248 /**************************************************************************** 11249 * RX_X1_Control1 :: shcnt_cl49 11250 */ 11251 /* RX_X1_Control1 :: shcnt_cl49 :: cl49_valid_sh_cnt [15:08] */ 11252 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_VALID_SH_CNT_MASK 0xff00 11253 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_VALID_SH_CNT_ALIGN 0 11254 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_VALID_SH_CNT_BITS 8 11255 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_VALID_SH_CNT_SHIFT 8 11256 11257 /* RX_X1_Control1 :: shcnt_cl49 :: cl49_invalid_sh_cnt [07:00] */ 11258 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_INVALID_SH_CNT_MASK 0x00ff 11259 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_INVALID_SH_CNT_ALIGN 0 11260 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_INVALID_SH_CNT_BITS 8 11261 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_INVALID_SH_CNT_SHIFT 0 11262 11263 11264 /**************************************************************************** 11265 * RX_X1_Control1 :: valid_shcnt_cl82 11266 */ 11267 /* RX_X1_Control1 :: valid_shcnt_cl82 :: reserved0 [15:12] */ 11268 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_RESERVED0_MASK 0xf000 11269 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_RESERVED0_ALIGN 0 11270 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_RESERVED0_BITS 4 11271 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_RESERVED0_SHIFT 12 11272 11273 /* RX_X1_Control1 :: valid_shcnt_cl82 :: cl82_valid_sh_cnt [11:00] */ 11274 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_CL82_VALID_SH_CNT_MASK 0x0fff 11275 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_CL82_VALID_SH_CNT_ALIGN 0 11276 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_CL82_VALID_SH_CNT_BITS 12 11277 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_CL82_VALID_SH_CNT_SHIFT 0 11278 11279 11280 /**************************************************************************** 11281 * RX_X1_Control1 :: invalid_shcnt_cl82 11282 */ 11283 /* RX_X1_Control1 :: invalid_shcnt_cl82 :: reserved0 [15:12] */ 11284 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_RESERVED0_MASK 0xf000 11285 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_RESERVED0_ALIGN 0 11286 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_RESERVED0_BITS 4 11287 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_RESERVED0_SHIFT 12 11288 11289 /* RX_X1_Control1 :: invalid_shcnt_cl82 :: cl82_invalid_sh_cnt [11:00] */ 11290 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_CL82_INVALID_SH_CNT_MASK 0x0fff 11291 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_CL82_INVALID_SH_CNT_ALIGN 0 11292 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_CL82_INVALID_SH_CNT_BITS 12 11293 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_CL82_INVALID_SH_CNT_SHIFT 0 11294 11295 11296 /**************************************************************************** 11297 * RX_X1_Control1 :: scw0 11298 */ 11299 /* RX_X1_Control1 :: scw0 :: scw0 [15:00] */ 11300 #define RX_X1_CONTROL1_SCW0_SCW0_MASK 0xffff 11301 #define RX_X1_CONTROL1_SCW0_SCW0_ALIGN 0 11302 #define RX_X1_CONTROL1_SCW0_SCW0_BITS 16 11303 #define RX_X1_CONTROL1_SCW0_SCW0_SHIFT 0 11304 11305 11306 /**************************************************************************** 11307 * RX_X1_Control1 :: scw1 11308 */ 11309 /* RX_X1_Control1 :: scw1 :: scw1 [15:00] */ 11310 #define RX_X1_CONTROL1_SCW1_SCW1_MASK 0xffff 11311 #define RX_X1_CONTROL1_SCW1_SCW1_ALIGN 0 11312 #define RX_X1_CONTROL1_SCW1_SCW1_BITS 16 11313 #define RX_X1_CONTROL1_SCW1_SCW1_SHIFT 0 11314 11315 11316 /**************************************************************************** 11317 * RX_X1_Control1 :: scw2 11318 */ 11319 /* RX_X1_Control1 :: scw2 :: scw2 [15:00] */ 11320 #define RX_X1_CONTROL1_SCW2_SCW2_MASK 0xffff 11321 #define RX_X1_CONTROL1_SCW2_SCW2_ALIGN 0 11322 #define RX_X1_CONTROL1_SCW2_SCW2_BITS 16 11323 #define RX_X1_CONTROL1_SCW2_SCW2_SHIFT 0 11324 11325 11326 /**************************************************************************** 11327 * RX_X1_Control1 :: scw3 11328 */ 11329 /* RX_X1_Control1 :: scw3 :: scw3 [15:00] */ 11330 #define RX_X1_CONTROL1_SCW3_SCW3_MASK 0xffff 11331 #define RX_X1_CONTROL1_SCW3_SCW3_ALIGN 0 11332 #define RX_X1_CONTROL1_SCW3_SCW3_BITS 16 11333 #define RX_X1_CONTROL1_SCW3_SCW3_SHIFT 0 11334 11335 11336 /**************************************************************************** 11337 * RX_X1_Control1 :: scw4 11338 */ 11339 /* RX_X1_Control1 :: scw4 :: reserved0 [15:02] */ 11340 #define RX_X1_CONTROL1_SCW4_RESERVED0_MASK 0xfffc 11341 #define RX_X1_CONTROL1_SCW4_RESERVED0_ALIGN 0 11342 #define RX_X1_CONTROL1_SCW4_RESERVED0_BITS 14 11343 #define RX_X1_CONTROL1_SCW4_RESERVED0_SHIFT 2 11344 11345 /* RX_X1_Control1 :: scw4 :: scw4 [01:00] */ 11346 #define RX_X1_CONTROL1_SCW4_SCW4_MASK 0x0003 11347 #define RX_X1_CONTROL1_SCW4_SCW4_ALIGN 0 11348 #define RX_X1_CONTROL1_SCW4_SCW4_BITS 2 11349 #define RX_X1_CONTROL1_SCW4_SCW4_SHIFT 0 11350 11351 11352 /**************************************************************************** 11353 * RX_X1_Control1 :: scw0_mask 11354 */ 11355 /* RX_X1_Control1 :: scw0_mask :: scw0_mask [15:00] */ 11356 #define RX_X1_CONTROL1_SCW0_MASK_SCW0_MASK_MASK 0xffff 11357 #define RX_X1_CONTROL1_SCW0_MASK_SCW0_MASK_ALIGN 0 11358 #define RX_X1_CONTROL1_SCW0_MASK_SCW0_MASK_BITS 16 11359 #define RX_X1_CONTROL1_SCW0_MASK_SCW0_MASK_SHIFT 0 11360 11361 11362 /**************************************************************************** 11363 * RX_X1_Control1 :: scw1_mask 11364 */ 11365 /* RX_X1_Control1 :: scw1_mask :: scw1_mask [15:00] */ 11366 #define RX_X1_CONTROL1_SCW1_MASK_SCW1_MASK_MASK 0xffff 11367 #define RX_X1_CONTROL1_SCW1_MASK_SCW1_MASK_ALIGN 0 11368 #define RX_X1_CONTROL1_SCW1_MASK_SCW1_MASK_BITS 16 11369 #define RX_X1_CONTROL1_SCW1_MASK_SCW1_MASK_SHIFT 0 11370 11371 11372 /**************************************************************************** 11373 * RX_X1_Control1 :: scw2_mask 11374 */ 11375 /* RX_X1_Control1 :: scw2_mask :: scw2_mask [15:00] */ 11376 #define RX_X1_CONTROL1_SCW2_MASK_SCW2_MASK_MASK 0xffff 11377 #define RX_X1_CONTROL1_SCW2_MASK_SCW2_MASK_ALIGN 0 11378 #define RX_X1_CONTROL1_SCW2_MASK_SCW2_MASK_BITS 16 11379 #define RX_X1_CONTROL1_SCW2_MASK_SCW2_MASK_SHIFT 0 11380 11381 11382 /**************************************************************************** 11383 * RX_X1_Control1 :: scw3_mask 11384 */ 11385 /* RX_X1_Control1 :: scw3_mask :: scw3_mask [15:00] */ 11386 #define RX_X1_CONTROL1_SCW3_MASK_SCW3_MASK_MASK 0xffff 11387 #define RX_X1_CONTROL1_SCW3_MASK_SCW3_MASK_ALIGN 0 11388 #define RX_X1_CONTROL1_SCW3_MASK_SCW3_MASK_BITS 16 11389 #define RX_X1_CONTROL1_SCW3_MASK_SCW3_MASK_SHIFT 0 11390 11391 11392 /**************************************************************************** 11393 * RX_X1_Control1 :: scw4_mask 11394 */ 11395 /* RX_X1_Control1 :: scw4_mask :: reserved0 [15:02] */ 11396 #define RX_X1_CONTROL1_SCW4_MASK_RESERVED0_MASK 0xfffc 11397 #define RX_X1_CONTROL1_SCW4_MASK_RESERVED0_ALIGN 0 11398 #define RX_X1_CONTROL1_SCW4_MASK_RESERVED0_BITS 14 11399 #define RX_X1_CONTROL1_SCW4_MASK_RESERVED0_SHIFT 2 11400 11401 /* RX_X1_Control1 :: scw4_mask :: scw4_mask [01:00] */ 11402 #define RX_X1_CONTROL1_SCW4_MASK_SCW4_MASK_MASK 0x0003 11403 #define RX_X1_CONTROL1_SCW4_MASK_SCW4_MASK_ALIGN 0 11404 #define RX_X1_CONTROL1_SCW4_MASK_SCW4_MASK_BITS 2 11405 #define RX_X1_CONTROL1_SCW4_MASK_SCW4_MASK_SHIFT 0 11406 11407 11408 /**************************************************************************** 11409 * TSC_AN_X1_CONTROL 11410 */ 11411 /**************************************************************************** 11412 * AN_X1_CONTROL :: oui_upper 11413 */ 11414 /* AN_X1_CONTROL :: oui_upper :: reserved0 [15:08] */ 11415 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_MASK 0xff00 11416 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_ALIGN 0 11417 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_BITS 8 11418 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_SHIFT 8 11419 11420 /* AN_X1_CONTROL :: oui_upper :: oui_upper_data [07:00] */ 11421 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_MASK 0x00ff 11422 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_ALIGN 0 11423 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_BITS 8 11424 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_SHIFT 0 11425 11426 11427 /**************************************************************************** 11428 * AN_X1_CONTROL :: oui_lower 11429 */ 11430 /* AN_X1_CONTROL :: oui_lower :: oui_lower_data [15:00] */ 11431 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_MASK 0xffff 11432 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_ALIGN 0 11433 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_BITS 16 11434 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_SHIFT 0 11435 11436 11437 /**************************************************************************** 11438 * AN_X1_CONTROL :: bam_speed_pri_5_0 11439 */ 11440 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: reserved0 [15:12] */ 11441 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_RESERVED0_MASK 0xf000 11442 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_RESERVED0_ALIGN 0 11443 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_RESERVED0_BITS 4 11444 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_RESERVED0_SHIFT 12 11445 11446 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_1GKX [11:10] */ 11447 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1GKX_MASK 0x0c00 11448 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1GKX_ALIGN 0 11449 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1GKX_BITS 2 11450 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1GKX_SHIFT 10 11451 11452 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_2p5GX1 [09:08] */ 11453 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_2P5GX1_MASK 0x0300 11454 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_2P5GX1_ALIGN 0 11455 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_2P5GX1_BITS 2 11456 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_2P5GX1_SHIFT 8 11457 11458 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_5GX4 [07:06] */ 11459 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_5GX4_MASK 0x00c0 11460 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_5GX4_ALIGN 0 11461 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_5GX4_BITS 2 11462 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_5GX4_SHIFT 6 11463 11464 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_10M [05:04] */ 11465 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_10M_MASK 0x0030 11466 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_10M_ALIGN 0 11467 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_10M_BITS 2 11468 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_10M_SHIFT 4 11469 11470 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_100M [03:02] */ 11471 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_100M_MASK 0x000c 11472 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_100M_ALIGN 0 11473 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_100M_BITS 2 11474 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_100M_SHIFT 2 11475 11476 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_1000M [01:00] */ 11477 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1000M_MASK 0x0003 11478 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1000M_ALIGN 0 11479 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1000M_BITS 2 11480 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1000M_SHIFT 0 11481 11482 11483 /**************************************************************************** 11484 * AN_X1_CONTROL :: bam_speed_pri_11_6 11485 */ 11486 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: reserved0 [15:12] */ 11487 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_RESERVED0_MASK 0xf000 11488 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_RESERVED0_ALIGN 0 11489 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_RESERVED0_BITS 4 11490 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_RESERVED0_SHIFT 12 11491 11492 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_10GKR [11:10] */ 11493 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKR_MASK 0x0c00 11494 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKR_ALIGN 0 11495 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKR_BITS 2 11496 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKR_SHIFT 10 11497 11498 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_10GKX4 [09:08] */ 11499 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKX4_MASK 0x0300 11500 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKX4_ALIGN 0 11501 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKX4_BITS 2 11502 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKX4_SHIFT 8 11503 11504 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_10GX4 [07:06] */ 11505 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GX4_MASK 0x00c0 11506 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GX4_ALIGN 0 11507 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GX4_BITS 2 11508 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GX4_SHIFT 6 11509 11510 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_6GX4 [05:04] */ 11511 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_6GX4_MASK 0x0030 11512 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_6GX4_ALIGN 0 11513 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_6GX4_BITS 2 11514 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_6GX4_SHIFT 4 11515 11516 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_10GCX1 [03:02] */ 11517 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX1_MASK 0x000c 11518 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX1_ALIGN 0 11519 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX1_BITS 2 11520 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX1_SHIFT 2 11521 11522 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_10GCX4 [01:00] */ 11523 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX4_MASK 0x0003 11524 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX4_ALIGN 0 11525 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX4_BITS 2 11526 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX4_SHIFT 0 11527 11528 11529 /**************************************************************************** 11530 * AN_X1_CONTROL :: bam_speed_pri_17_12 11531 */ 11532 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: reserved0 [15:12] */ 11533 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_RESERVED0_MASK 0xf000 11534 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_RESERVED0_ALIGN 0 11535 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_RESERVED0_BITS 4 11536 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_RESERVED0_SHIFT 12 11537 11538 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_12GX4 [11:10] */ 11539 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12GX4_MASK 0x0c00 11540 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12GX4_ALIGN 0 11541 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12GX4_BITS 2 11542 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12GX4_SHIFT 10 11543 11544 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_12p5GX4 [09:08] */ 11545 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P5GX4_MASK 0x0300 11546 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P5GX4_ALIGN 0 11547 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P5GX4_BITS 2 11548 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P5GX4_SHIFT 8 11549 11550 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_12p7GX2 [07:06] */ 11551 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P7GX2_MASK 0x00c0 11552 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P7GX2_ALIGN 0 11553 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P7GX2_BITS 2 11554 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P7GX2_SHIFT 6 11555 11556 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_10GCX2 [05:04] */ 11557 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GCX2_MASK 0x0030 11558 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GCX2_ALIGN 0 11559 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GCX2_BITS 2 11560 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GCX2_SHIFT 4 11561 11562 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_10GX2 [03:02] */ 11563 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GX2_MASK 0x000c 11564 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GX2_ALIGN 0 11565 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GX2_BITS 2 11566 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GX2_SHIFT 2 11567 11568 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_10p5GX2 [01:00] */ 11569 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10P5GX2_MASK 0x0003 11570 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10P5GX2_ALIGN 0 11571 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10P5GX2_BITS 2 11572 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10P5GX2_SHIFT 0 11573 11574 11575 /**************************************************************************** 11576 * AN_X1_CONTROL :: bam_speed_pri_23_18 11577 */ 11578 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: reserved0 [15:12] */ 11579 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_RESERVED0_MASK 0xf000 11580 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_RESERVED0_ALIGN 0 11581 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_RESERVED0_BITS 4 11582 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_RESERVED0_SHIFT 12 11583 11584 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_40GCR4 [11:10] */ 11585 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GCR4_MASK 0x0c00 11586 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GCR4_ALIGN 0 11587 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GCR4_BITS 2 11588 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GCR4_SHIFT 10 11589 11590 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_40GKR4 [09:08] */ 11591 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GKR4_MASK 0x0300 11592 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GKR4_ALIGN 0 11593 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GKR4_BITS 2 11594 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GKR4_SHIFT 8 11595 11596 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_100GCR10 [07:06] */ 11597 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_100GCR10_MASK 0x00c0 11598 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_100GCR10_ALIGN 0 11599 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_100GCR10_BITS 2 11600 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_100GCR10_SHIFT 6 11601 11602 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_13GX4 [05:04] */ 11603 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_13GX4_MASK 0x0030 11604 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_13GX4_ALIGN 0 11605 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_13GX4_BITS 2 11606 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_13GX4_SHIFT 4 11607 11608 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_15GX4 [03:02] */ 11609 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15GX4_MASK 0x000c 11610 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15GX4_ALIGN 0 11611 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15GX4_BITS 2 11612 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15GX4_SHIFT 2 11613 11614 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_15p75GX2 [01:00] */ 11615 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15P75GX2_MASK 0x0003 11616 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15P75GX2_ALIGN 0 11617 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15P75GX2_BITS 2 11618 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15P75GX2_SHIFT 0 11619 11620 11621 /**************************************************************************** 11622 * AN_X1_CONTROL :: bam_speed_pri_29_24 11623 */ 11624 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: reserved0 [15:12] */ 11625 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_RESERVED0_MASK 0xf000 11626 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_RESERVED0_ALIGN 0 11627 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_RESERVED0_BITS 4 11628 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_RESERVED0_SHIFT 12 11629 11630 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_20GKR2 [11:10] */ 11631 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GKR2_MASK 0x0c00 11632 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GKR2_ALIGN 0 11633 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GKR2_BITS 2 11634 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GKR2_SHIFT 10 11635 11636 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_20GCX4 [09:08] */ 11637 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX4_MASK 0x0300 11638 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX4_ALIGN 0 11639 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX4_BITS 2 11640 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX4_SHIFT 8 11641 11642 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_20GX2 [07:06] */ 11643 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GX2_MASK 0x00c0 11644 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GX2_ALIGN 0 11645 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GX2_BITS 2 11646 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GX2_SHIFT 6 11647 11648 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_16GX4 [05:04] */ 11649 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_16GX4_MASK 0x0030 11650 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_16GX4_ALIGN 0 11651 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_16GX4_BITS 2 11652 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_16GX4_SHIFT 4 11653 11654 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_20GCX2 [03:02] */ 11655 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX2_MASK 0x000c 11656 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX2_ALIGN 0 11657 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX2_BITS 2 11658 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX2_SHIFT 2 11659 11660 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_20GCR2 [01:00] */ 11661 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCR2_MASK 0x0003 11662 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCR2_ALIGN 0 11663 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCR2_BITS 2 11664 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCR2_SHIFT 0 11665 11666 11667 /**************************************************************************** 11668 * AN_X1_CONTROL :: bam_speed_pri_35_30 11669 */ 11670 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: reserved0 [15:12] */ 11671 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_RESERVED0_MASK 0xf000 11672 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_RESERVED0_ALIGN 0 11673 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_RESERVED0_BITS 4 11674 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_RESERVED0_SHIFT 12 11675 11676 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_31p5G [11:10] */ 11677 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_31P5G_MASK 0x0c00 11678 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_31P5G_ALIGN 0 11679 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_31P5G_BITS 2 11680 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_31P5G_SHIFT 10 11681 11682 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_32p7G [09:08] */ 11683 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_32P7G_MASK 0x0300 11684 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_32P7G_ALIGN 0 11685 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_32P7G_BITS 2 11686 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_32P7G_SHIFT 8 11687 11688 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_40GX4 [07:06] */ 11689 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_40GX4_MASK 0x00c0 11690 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_40GX4_ALIGN 0 11691 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_40GX4_BITS 2 11692 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_40GX4_SHIFT 6 11693 11694 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_20GX4 [05:04] */ 11695 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_20GX4_MASK 0x0030 11696 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_20GX4_ALIGN 0 11697 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_20GX4_BITS 2 11698 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_20GX4_SHIFT 4 11699 11700 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_21GX4 [03:02] */ 11701 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_21GX4_MASK 0x000c 11702 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_21GX4_ALIGN 0 11703 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_21GX4_BITS 2 11704 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_21GX4_SHIFT 2 11705 11706 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_25p45GX4 [01:00] */ 11707 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_25P45GX4_MASK 0x0003 11708 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_25P45GX4_ALIGN 0 11709 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_25P45GX4_BITS 2 11710 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_25P45GX4_SHIFT 0 11711 11712 11713 /**************************************************************************** 11714 * AN_X1_CONTROL :: config_control 11715 */ 11716 /* AN_X1_CONTROL :: config_control :: ram_base [15:00] */ 11717 #define AN_X1_CONTROL_CONFIG_CONTROL_RAM_BASE_MASK 0xffff 11718 #define AN_X1_CONTROL_CONFIG_CONTROL_RAM_BASE_ALIGN 0 11719 #define AN_X1_CONTROL_CONFIG_CONTROL_RAM_BASE_BITS 16 11720 #define AN_X1_CONTROL_CONFIG_CONTROL_RAM_BASE_SHIFT 0 11721 11722 11723 /**************************************************************************** 11724 * AN_X1_CONTROL :: pll_reset_timer 11725 */ 11726 /* AN_X1_CONTROL :: pll_reset_timer :: pll_reset_timer_period [15:00] */ 11727 #define AN_X1_CONTROL_PLL_RESET_TIMER_PLL_RESET_TIMER_PERIOD_MASK 0xffff 11728 #define AN_X1_CONTROL_PLL_RESET_TIMER_PLL_RESET_TIMER_PERIOD_ALIGN 0 11729 #define AN_X1_CONTROL_PLL_RESET_TIMER_PLL_RESET_TIMER_PERIOD_BITS 16 11730 #define AN_X1_CONTROL_PLL_RESET_TIMER_PLL_RESET_TIMER_PERIOD_SHIFT 0 11731 11732 11733 /**************************************************************************** 11734 * TSC_AN_X1_TIMERS 11735 */ 11736 /**************************************************************************** 11737 * AN_X1_TIMERS :: cl37_restart 11738 */ 11739 /* AN_X1_TIMERS :: cl37_restart :: cl37_restart_timer_period [15:00] */ 11740 #define AN_X1_TIMERS_CL37_RESTART_CL37_RESTART_TIMER_PERIOD_MASK 0xffff 11741 #define AN_X1_TIMERS_CL37_RESTART_CL37_RESTART_TIMER_PERIOD_ALIGN 0 11742 #define AN_X1_TIMERS_CL37_RESTART_CL37_RESTART_TIMER_PERIOD_BITS 16 11743 #define AN_X1_TIMERS_CL37_RESTART_CL37_RESTART_TIMER_PERIOD_SHIFT 0 11744 11745 11746 /**************************************************************************** 11747 * AN_X1_TIMERS :: cl37_ack 11748 */ 11749 /* AN_X1_TIMERS :: cl37_ack :: cl37_ack_timer_period [15:00] */ 11750 #define AN_X1_TIMERS_CL37_ACK_CL37_ACK_TIMER_PERIOD_MASK 0xffff 11751 #define AN_X1_TIMERS_CL37_ACK_CL37_ACK_TIMER_PERIOD_ALIGN 0 11752 #define AN_X1_TIMERS_CL37_ACK_CL37_ACK_TIMER_PERIOD_BITS 16 11753 #define AN_X1_TIMERS_CL37_ACK_CL37_ACK_TIMER_PERIOD_SHIFT 0 11754 11755 11756 /**************************************************************************** 11757 * AN_X1_TIMERS :: cl37_error 11758 */ 11759 /* AN_X1_TIMERS :: cl37_error :: cl37_error_timer_period [15:00] */ 11760 #define AN_X1_TIMERS_CL37_ERROR_CL37_ERROR_TIMER_PERIOD_MASK 0xffff 11761 #define AN_X1_TIMERS_CL37_ERROR_CL37_ERROR_TIMER_PERIOD_ALIGN 0 11762 #define AN_X1_TIMERS_CL37_ERROR_CL37_ERROR_TIMER_PERIOD_BITS 16 11763 #define AN_X1_TIMERS_CL37_ERROR_CL37_ERROR_TIMER_PERIOD_SHIFT 0 11764 11765 11766 /**************************************************************************** 11767 * AN_X1_TIMERS :: cl73_break_link 11768 */ 11769 /* AN_X1_TIMERS :: cl73_break_link :: tx_disable_timer_period [15:00] */ 11770 #define AN_X1_TIMERS_CL73_BREAK_LINK_TX_DISABLE_TIMER_PERIOD_MASK 0xffff 11771 #define AN_X1_TIMERS_CL73_BREAK_LINK_TX_DISABLE_TIMER_PERIOD_ALIGN 0 11772 #define AN_X1_TIMERS_CL73_BREAK_LINK_TX_DISABLE_TIMER_PERIOD_BITS 16 11773 #define AN_X1_TIMERS_CL73_BREAK_LINK_TX_DISABLE_TIMER_PERIOD_SHIFT 0 11774 11775 11776 /**************************************************************************** 11777 * AN_X1_TIMERS :: cl73_error 11778 */ 11779 /* AN_X1_TIMERS :: cl73_error :: cl73_error_timer_period [15:00] */ 11780 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_MASK 0xffff 11781 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_ALIGN 0 11782 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_BITS 16 11783 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_SHIFT 0 11784 11785 11786 /**************************************************************************** 11787 * AN_X1_TIMERS :: cl73_dme_lock 11788 */ 11789 /* AN_X1_TIMERS :: cl73_dme_lock :: pd_dme_lock_timer_period [15:00] */ 11790 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_MASK 0xffff 11791 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_ALIGN 0 11792 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_BITS 16 11793 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_SHIFT 0 11794 11795 11796 /**************************************************************************** 11797 * AN_X1_TIMERS :: link_up 11798 */ 11799 /* AN_X1_TIMERS :: link_up :: cl73_link_up_timer_period [15:00] */ 11800 #define AN_X1_TIMERS_LINK_UP_CL73_LINK_UP_TIMER_PERIOD_MASK 0xffff 11801 #define AN_X1_TIMERS_LINK_UP_CL73_LINK_UP_TIMER_PERIOD_ALIGN 0 11802 #define AN_X1_TIMERS_LINK_UP_CL73_LINK_UP_TIMER_PERIOD_BITS 16 11803 #define AN_X1_TIMERS_LINK_UP_CL73_LINK_UP_TIMER_PERIOD_SHIFT 0 11804 11805 11806 /**************************************************************************** 11807 * AN_X1_TIMERS :: link_fail_inhibit_timer_cl72 11808 */ 11809 /* AN_X1_TIMERS :: link_fail_inhibit_timer_cl72 :: link_fail_inhibit_timer_cl72_period [15:00] */ 11810 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_MASK 0xffff 11811 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_ALIGN 0 11812 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_BITS 16 11813 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_SHIFT 0 11814 11815 11816 /**************************************************************************** 11817 * AN_X1_TIMERS :: link_fail_inhibit_timer_not_cl72 11818 */ 11819 /* AN_X1_TIMERS :: link_fail_inhibit_timer_not_cl72 :: link_fail_inhibit_timer_ncl72_period [15:00] */ 11820 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_MASK 0xffff 11821 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_ALIGN 0 11822 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_BITS 16 11823 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_SHIFT 0 11824 11825 11826 /**************************************************************************** 11827 * AN_X1_TIMERS :: pd_sd_timer 11828 */ 11829 /* AN_X1_TIMERS :: pd_sd_timer :: pd_sd_timer_period [15:00] */ 11830 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_MASK 0xffff 11831 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_ALIGN 0 11832 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_BITS 16 11833 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_SHIFT 0 11834 11835 11836 /**************************************************************************** 11837 * AN_X1_TIMERS :: cl72_max_wait_timer 11838 */ 11839 /* AN_X1_TIMERS :: cl72_max_wait_timer :: cl72_max_wait_timer_period [15:00] */ 11840 #define AN_X1_TIMERS_CL72_MAX_WAIT_TIMER_CL72_MAX_WAIT_TIMER_PERIOD_MASK 0xffff 11841 #define AN_X1_TIMERS_CL72_MAX_WAIT_TIMER_CL72_MAX_WAIT_TIMER_PERIOD_ALIGN 0 11842 #define AN_X1_TIMERS_CL72_MAX_WAIT_TIMER_CL72_MAX_WAIT_TIMER_PERIOD_BITS 16 11843 #define AN_X1_TIMERS_CL72_MAX_WAIT_TIMER_CL72_MAX_WAIT_TIMER_PERIOD_SHIFT 0 11844 11845 11846 /**************************************************************************** 11847 * AN_X1_TIMERS :: cl72_wait_timer 11848 */ 11849 /* AN_X1_TIMERS :: cl72_wait_timer :: reserved0 [15:09] */ 11850 #define AN_X1_TIMERS_CL72_WAIT_TIMER_RESERVED0_MASK 0xfe00 11851 #define AN_X1_TIMERS_CL72_WAIT_TIMER_RESERVED0_ALIGN 0 11852 #define AN_X1_TIMERS_CL72_WAIT_TIMER_RESERVED0_BITS 7 11853 #define AN_X1_TIMERS_CL72_WAIT_TIMER_RESERVED0_SHIFT 9 11854 11855 /* AN_X1_TIMERS :: cl72_wait_timer :: cl72_wait_timer_period [08:00] */ 11856 #define AN_X1_TIMERS_CL72_WAIT_TIMER_CL72_WAIT_TIMER_PERIOD_MASK 0x01ff 11857 #define AN_X1_TIMERS_CL72_WAIT_TIMER_CL72_WAIT_TIMER_PERIOD_ALIGN 0 11858 #define AN_X1_TIMERS_CL72_WAIT_TIMER_CL72_WAIT_TIMER_PERIOD_BITS 9 11859 #define AN_X1_TIMERS_CL72_WAIT_TIMER_CL72_WAIT_TIMER_PERIOD_SHIFT 0 11860 11861 11862 /**************************************************************************** 11863 * AN_X1_TIMERS :: ignore_link_timer 11864 */ 11865 /* AN_X1_TIMERS :: ignore_link_timer :: ignore_link_timer_period [15:00] */ 11866 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_MASK 0xffff 11867 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_ALIGN 0 11868 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_BITS 16 11869 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_SHIFT 0 11870 11871 11872 /**************************************************************************** 11873 * AN_X1_TIMERS :: dme_page_timer 11874 */ 11875 /* AN_X1_TIMERS :: dme_page_timer :: reserved0 [15:14] */ 11876 #define AN_X1_TIMERS_DME_PAGE_TIMER_RESERVED0_MASK 0xc000 11877 #define AN_X1_TIMERS_DME_PAGE_TIMER_RESERVED0_ALIGN 0 11878 #define AN_X1_TIMERS_DME_PAGE_TIMER_RESERVED0_BITS 2 11879 #define AN_X1_TIMERS_DME_PAGE_TIMER_RESERVED0_SHIFT 14 11880 11881 /* AN_X1_TIMERS :: dme_page_timer :: cl73_page_test_max_timer [13:07] */ 11882 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MAX_TIMER_MASK 0x3f80 11883 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MAX_TIMER_ALIGN 0 11884 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MAX_TIMER_BITS 7 11885 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MAX_TIMER_SHIFT 7 11886 11887 /* AN_X1_TIMERS :: dme_page_timer :: cl73_page_test_min_timer [06:00] */ 11888 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MIN_TIMER_MASK 0x007f 11889 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MIN_TIMER_ALIGN 0 11890 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MIN_TIMER_BITS 7 11891 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MIN_TIMER_SHIFT 0 11892 11893 11894 /**************************************************************************** 11895 * AN_X1_TIMERS :: sgmii_cl73_timer_type 11896 */ 11897 /* AN_X1_TIMERS :: sgmii_cl73_timer_type :: sgmii_timer [15:00] */ 11898 #define AN_X1_TIMERS_SGMII_CL73_TIMER_TYPE_SGMII_TIMER_MASK 0xffff 11899 #define AN_X1_TIMERS_SGMII_CL73_TIMER_TYPE_SGMII_TIMER_ALIGN 0 11900 #define AN_X1_TIMERS_SGMII_CL73_TIMER_TYPE_SGMII_TIMER_BITS 16 11901 #define AN_X1_TIMERS_SGMII_CL73_TIMER_TYPE_SGMII_TIMER_SHIFT 0 11902 11903 11904 /**************************************************************************** 11905 * TSC_WC4_TSC_USER2_TX_X2_Control0 11906 */ 11907 /**************************************************************************** 11908 * TX_X2_Control0 :: MLD_swap_count 11909 */ 11910 /* TX_X2_Control0 :: MLD_swap_count :: MLD_swap_count [15:00] */ 11911 #define TX_X2_CONTROL0_MLD_SWAP_COUNT_MLD_SWAP_COUNT_MASK 0xffff 11912 #define TX_X2_CONTROL0_MLD_SWAP_COUNT_MLD_SWAP_COUNT_ALIGN 0 11913 #define TX_X2_CONTROL0_MLD_SWAP_COUNT_MLD_SWAP_COUNT_BITS 16 11914 #define TX_X2_CONTROL0_MLD_SWAP_COUNT_MLD_SWAP_COUNT_SHIFT 0 11915 11916 11917 /**************************************************************************** 11918 * TX_X2_Control0 :: cl48_0 11919 */ 11920 /* TX_X2_Control0 :: cl48_0 :: BRCM_MODE_USE_K20PT5 [15:15] */ 11921 #define TX_X2_CONTROL0_CL48_0_BRCM_MODE_USE_K20PT5_MASK 0x8000 11922 #define TX_X2_CONTROL0_CL48_0_BRCM_MODE_USE_K20PT5_ALIGN 0 11923 #define TX_X2_CONTROL0_CL48_0_BRCM_MODE_USE_K20PT5_BITS 1 11924 #define TX_X2_CONTROL0_CL48_0_BRCM_MODE_USE_K20PT5_SHIFT 15 11925 11926 /* TX_X2_Control0 :: cl48_0 :: reserved0 [14:07] */ 11927 #define TX_X2_CONTROL0_CL48_0_RESERVED0_MASK 0x7f80 11928 #define TX_X2_CONTROL0_CL48_0_RESERVED0_ALIGN 0 11929 #define TX_X2_CONTROL0_CL48_0_RESERVED0_BITS 8 11930 #define TX_X2_CONTROL0_CL48_0_RESERVED0_SHIFT 7 11931 11932 /* TX_X2_Control0 :: cl48_0 :: cl48_tx_li_enable [06:06] */ 11933 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LI_ENABLE_MASK 0x0040 11934 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LI_ENABLE_ALIGN 0 11935 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LI_ENABLE_BITS 1 11936 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LI_ENABLE_SHIFT 6 11937 11938 /* TX_X2_Control0 :: cl48_0 :: cl48_tx_lf_enable [05:05] */ 11939 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LF_ENABLE_MASK 0x0020 11940 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LF_ENABLE_ALIGN 0 11941 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LF_ENABLE_BITS 1 11942 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LF_ENABLE_SHIFT 5 11943 11944 /* TX_X2_Control0 :: cl48_0 :: cl48_tx_rf_enable [04:04] */ 11945 #define TX_X2_CONTROL0_CL48_0_CL48_TX_RF_ENABLE_MASK 0x0010 11946 #define TX_X2_CONTROL0_CL48_0_CL48_TX_RF_ENABLE_ALIGN 0 11947 #define TX_X2_CONTROL0_CL48_0_CL48_TX_RF_ENABLE_BITS 1 11948 #define TX_X2_CONTROL0_CL48_0_CL48_TX_RF_ENABLE_SHIFT 4 11949 11950 /* TX_X2_Control0 :: cl48_0 :: cl48_tx_QrsvdCtrl [03:00] */ 11951 #define TX_X2_CONTROL0_CL48_0_CL48_TX_QRSVDCTRL_MASK 0x000f 11952 #define TX_X2_CONTROL0_CL48_0_CL48_TX_QRSVDCTRL_ALIGN 0 11953 #define TX_X2_CONTROL0_CL48_0_CL48_TX_QRSVDCTRL_BITS 4 11954 #define TX_X2_CONTROL0_CL48_0_CL48_TX_QRSVDCTRL_SHIFT 0 11955 11956 11957 /**************************************************************************** 11958 * TX_X2_Control0 :: cl82_0 11959 */ 11960 /* TX_X2_Control0 :: cl82_0 :: reserved0 [15:11] */ 11961 #define TX_X2_CONTROL0_CL82_0_RESERVED0_MASK 0xf800 11962 #define TX_X2_CONTROL0_CL82_0_RESERVED0_ALIGN 0 11963 #define TX_X2_CONTROL0_CL82_0_RESERVED0_BITS 5 11964 #define TX_X2_CONTROL0_CL82_0_RESERVED0_SHIFT 11 11965 11966 /* TX_X2_Control0 :: cl82_0 :: cl82_bypass_txsm [10:10] */ 11967 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_MASK 0x0400 11968 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_ALIGN 0 11969 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_BITS 1 11970 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_SHIFT 10 11971 11972 /* TX_X2_Control0 :: cl82_0 :: reserved1 [09:07] */ 11973 #define TX_X2_CONTROL0_CL82_0_RESERVED1_MASK 0x0380 11974 #define TX_X2_CONTROL0_CL82_0_RESERVED1_ALIGN 0 11975 #define TX_X2_CONTROL0_CL82_0_RESERVED1_BITS 3 11976 #define TX_X2_CONTROL0_CL82_0_RESERVED1_SHIFT 7 11977 11978 /* TX_X2_Control0 :: cl82_0 :: cl82_tx_li_enable [06:06] */ 11979 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_MASK 0x0040 11980 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_ALIGN 0 11981 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_BITS 1 11982 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_SHIFT 6 11983 11984 /* TX_X2_Control0 :: cl82_0 :: cl82_tx_lf_enable [05:05] */ 11985 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_MASK 0x0020 11986 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_ALIGN 0 11987 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_BITS 1 11988 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_SHIFT 5 11989 11990 /* TX_X2_Control0 :: cl82_0 :: cl82_tx_rf_enable [04:04] */ 11991 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_MASK 0x0010 11992 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_ALIGN 0 11993 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_BITS 1 11994 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_SHIFT 4 11995 11996 /* TX_X2_Control0 :: cl82_0 :: reserved2 [03:00] */ 11997 #define TX_X2_CONTROL0_CL82_0_RESERVED2_MASK 0x000f 11998 #define TX_X2_CONTROL0_CL82_0_RESERVED2_ALIGN 0 11999 #define TX_X2_CONTROL0_CL82_0_RESERVED2_BITS 4 12000 #define TX_X2_CONTROL0_CL82_0_RESERVED2_SHIFT 0 12001 12002 12003 /**************************************************************************** 12004 * TX_X2_Control0 :: brcm_mode 12005 */ 12006 /* TX_X2_Control0 :: brcm_mode :: reserved0 [15:08] */ 12007 #define TX_X2_CONTROL0_BRCM_MODE_RESERVED0_MASK 0xff00 12008 #define TX_X2_CONTROL0_BRCM_MODE_RESERVED0_ALIGN 0 12009 #define TX_X2_CONTROL0_BRCM_MODE_RESERVED0_BITS 8 12010 #define TX_X2_CONTROL0_BRCM_MODE_RESERVED0_SHIFT 8 12011 12012 /* TX_X2_Control0 :: brcm_mode :: acol_swap_count64B66B [07:00] */ 12013 #define TX_X2_CONTROL0_BRCM_MODE_ACOL_SWAP_COUNT64B66B_MASK 0x00ff 12014 #define TX_X2_CONTROL0_BRCM_MODE_ACOL_SWAP_COUNT64B66B_ALIGN 0 12015 #define TX_X2_CONTROL0_BRCM_MODE_ACOL_SWAP_COUNT64B66B_BITS 8 12016 #define TX_X2_CONTROL0_BRCM_MODE_ACOL_SWAP_COUNT64B66B_SHIFT 0 12017 12018 12019 /**************************************************************************** 12020 * TSC_WC4_TSC_USER2_TX_X2_Status0 12021 */ 12022 /**************************************************************************** 12023 * TX_X2_Status0 :: cl82_tx_status_0 12024 */ 12025 /* TX_X2_Status0 :: cl82_tx_status_0 :: reserved0 [15:14] */ 12026 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_MASK 0xc000 12027 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_ALIGN 0 12028 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_BITS 2 12029 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_SHIFT 14 12030 12031 /* TX_X2_Status0 :: cl82_tx_status_0 :: cl82_idle_deletion_underflow [13:13] */ 12032 #define TX_X2_STATUS0_CL82_TX_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_MASK 0x2000 12033 #define TX_X2_STATUS0_CL82_TX_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_ALIGN 0 12034 #define TX_X2_STATUS0_CL82_TX_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_BITS 1 12035 #define TX_X2_STATUS0_CL82_TX_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_SHIFT 13 12036 12037 /* TX_X2_Status0 :: cl82_tx_status_0 :: t_type_coded [12:10] */ 12038 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_MASK 0x1c00 12039 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_ALIGN 0 12040 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_BITS 3 12041 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_SHIFT 10 12042 12043 /* TX_X2_Status0 :: cl82_tx_status_0 :: ltxsm_state [09:03] */ 12044 #define TX_X2_STATUS0_CL82_TX_STATUS_0_LTXSM_STATE_MASK 0x03f8 12045 #define TX_X2_STATUS0_CL82_TX_STATUS_0_LTXSM_STATE_ALIGN 0 12046 #define TX_X2_STATUS0_CL82_TX_STATUS_0_LTXSM_STATE_BITS 7 12047 #define TX_X2_STATUS0_CL82_TX_STATUS_0_LTXSM_STATE_SHIFT 3 12048 12049 /* TX_X2_Status0 :: cl82_tx_status_0 :: txsm_state [02:00] */ 12050 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_MASK 0x0007 12051 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_ALIGN 0 12052 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_BITS 3 12053 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_SHIFT 0 12054 12055 12056 /**************************************************************************** 12057 * TSC_WC4_TSC_USER2_RX_X2_Control0 12058 */ 12059 /**************************************************************************** 12060 * RX_X2_Control0 :: qrsvd_0 12061 */ 12062 /* RX_X2_Control0 :: qrsvd_0 :: reserved0 [15:15] */ 12063 #define RX_X2_CONTROL0_QRSVD_0_RESERVED0_MASK 0x8000 12064 #define RX_X2_CONTROL0_QRSVD_0_RESERVED0_ALIGN 0 12065 #define RX_X2_CONTROL0_QRSVD_0_RESERVED0_BITS 1 12066 #define RX_X2_CONTROL0_QRSVD_0_RESERVED0_SHIFT 15 12067 12068 /* RX_X2_Control0 :: qrsvd_0 :: QrsvdSwap [14:05] */ 12069 #define RX_X2_CONTROL0_QRSVD_0_QRSVDSWAP_MASK 0x7fe0 12070 #define RX_X2_CONTROL0_QRSVD_0_QRSVDSWAP_ALIGN 0 12071 #define RX_X2_CONTROL0_QRSVD_0_QRSVDSWAP_BITS 10 12072 #define RX_X2_CONTROL0_QRSVD_0_QRSVDSWAP_SHIFT 5 12073 12074 /* RX_X2_Control0 :: qrsvd_0 :: CL48_rx_QrsvdCtrl [04:01] */ 12075 #define RX_X2_CONTROL0_QRSVD_0_CL48_RX_QRSVDCTRL_MASK 0x001e 12076 #define RX_X2_CONTROL0_QRSVD_0_CL48_RX_QRSVDCTRL_ALIGN 0 12077 #define RX_X2_CONTROL0_QRSVD_0_CL48_RX_QRSVDCTRL_BITS 4 12078 #define RX_X2_CONTROL0_QRSVD_0_CL48_RX_QRSVDCTRL_SHIFT 1 12079 12080 /* RX_X2_Control0 :: qrsvd_0 :: reserved1 [00:00] */ 12081 #define RX_X2_CONTROL0_QRSVD_0_RESERVED1_MASK 0x0001 12082 #define RX_X2_CONTROL0_QRSVD_0_RESERVED1_ALIGN 0 12083 #define RX_X2_CONTROL0_QRSVD_0_RESERVED1_BITS 1 12084 #define RX_X2_CONTROL0_QRSVD_0_RESERVED1_SHIFT 0 12085 12086 12087 /**************************************************************************** 12088 * RX_X2_Control0 :: qrsvd_1 12089 */ 12090 /* RX_X2_Control0 :: qrsvd_1 :: Qrsvd1 [15:07] */ 12091 #define RX_X2_CONTROL0_QRSVD_1_QRSVD1_MASK 0xff80 12092 #define RX_X2_CONTROL0_QRSVD_1_QRSVD1_ALIGN 0 12093 #define RX_X2_CONTROL0_QRSVD_1_QRSVD1_BITS 9 12094 #define RX_X2_CONTROL0_QRSVD_1_QRSVD1_SHIFT 7 12095 12096 /* RX_X2_Control0 :: qrsvd_1 :: Qrsvd2_8_2 [06:00] */ 12097 #define RX_X2_CONTROL0_QRSVD_1_QRSVD2_8_2_MASK 0x007f 12098 #define RX_X2_CONTROL0_QRSVD_1_QRSVD2_8_2_ALIGN 0 12099 #define RX_X2_CONTROL0_QRSVD_1_QRSVD2_8_2_BITS 7 12100 #define RX_X2_CONTROL0_QRSVD_1_QRSVD2_8_2_SHIFT 0 12101 12102 12103 /**************************************************************************** 12104 * RX_X2_Control0 :: qrsvd_2 12105 */ 12106 /* RX_X2_Control0 :: qrsvd_2 :: Qrsvd2_1_0 [15:14] */ 12107 #define RX_X2_CONTROL0_QRSVD_2_QRSVD2_1_0_MASK 0xc000 12108 #define RX_X2_CONTROL0_QRSVD_2_QRSVD2_1_0_ALIGN 0 12109 #define RX_X2_CONTROL0_QRSVD_2_QRSVD2_1_0_BITS 2 12110 #define RX_X2_CONTROL0_QRSVD_2_QRSVD2_1_0_SHIFT 14 12111 12112 /* RX_X2_Control0 :: qrsvd_2 :: Qrsvd3 [13:05] */ 12113 #define RX_X2_CONTROL0_QRSVD_2_QRSVD3_MASK 0x3fe0 12114 #define RX_X2_CONTROL0_QRSVD_2_QRSVD3_ALIGN 0 12115 #define RX_X2_CONTROL0_QRSVD_2_QRSVD3_BITS 9 12116 #define RX_X2_CONTROL0_QRSVD_2_QRSVD3_SHIFT 5 12117 12118 /* RX_X2_Control0 :: qrsvd_2 :: reserved0 [04:00] */ 12119 #define RX_X2_CONTROL0_QRSVD_2_RESERVED0_MASK 0x001f 12120 #define RX_X2_CONTROL0_QRSVD_2_RESERVED0_ALIGN 0 12121 #define RX_X2_CONTROL0_QRSVD_2_RESERVED0_BITS 5 12122 #define RX_X2_CONTROL0_QRSVD_2_RESERVED0_SHIFT 0 12123 12124 12125 /**************************************************************************** 12126 * RX_X2_Control0 :: misc_0 12127 */ 12128 /* RX_X2_Control0 :: misc_0 :: reserved0 [15:13] */ 12129 #define RX_X2_CONTROL0_MISC_0_RESERVED0_MASK 0xe000 12130 #define RX_X2_CONTROL0_MISC_0_RESERVED0_ALIGN 0 12131 #define RX_X2_CONTROL0_MISC_0_RESERVED0_BITS 3 12132 #define RX_X2_CONTROL0_MISC_0_RESERVED0_SHIFT 13 12133 12134 /* RX_X2_Control0 :: misc_0 :: link_en [12:12] */ 12135 #define RX_X2_CONTROL0_MISC_0_LINK_EN_MASK 0x1000 12136 #define RX_X2_CONTROL0_MISC_0_LINK_EN_ALIGN 0 12137 #define RX_X2_CONTROL0_MISC_0_LINK_EN_BITS 1 12138 #define RX_X2_CONTROL0_MISC_0_LINK_EN_SHIFT 12 12139 12140 /* RX_X2_Control0 :: misc_0 :: reserved1 [11:11] */ 12141 #define RX_X2_CONTROL0_MISC_0_RESERVED1_MASK 0x0800 12142 #define RX_X2_CONTROL0_MISC_0_RESERVED1_ALIGN 0 12143 #define RX_X2_CONTROL0_MISC_0_RESERVED1_BITS 1 12144 #define RX_X2_CONTROL0_MISC_0_RESERVED1_SHIFT 11 12145 12146 /* RX_X2_Control0 :: misc_0 :: chk_end_en [10:10] */ 12147 #define RX_X2_CONTROL0_MISC_0_CHK_END_EN_MASK 0x0400 12148 #define RX_X2_CONTROL0_MISC_0_CHK_END_EN_ALIGN 0 12149 #define RX_X2_CONTROL0_MISC_0_CHK_END_EN_BITS 1 12150 #define RX_X2_CONTROL0_MISC_0_CHK_END_EN_SHIFT 10 12151 12152 /* RX_X2_Control0 :: misc_0 :: chk_end_override [09:09] */ 12153 #define RX_X2_CONTROL0_MISC_0_CHK_END_OVERRIDE_MASK 0x0200 12154 #define RX_X2_CONTROL0_MISC_0_CHK_END_OVERRIDE_ALIGN 0 12155 #define RX_X2_CONTROL0_MISC_0_CHK_END_OVERRIDE_BITS 1 12156 #define RX_X2_CONTROL0_MISC_0_CHK_END_OVERRIDE_SHIFT 9 12157 12158 /* RX_X2_Control0 :: misc_0 :: brcm_mode_use_k20pt5 [08:08] */ 12159 #define RX_X2_CONTROL0_MISC_0_BRCM_MODE_USE_K20PT5_MASK 0x0100 12160 #define RX_X2_CONTROL0_MISC_0_BRCM_MODE_USE_K20PT5_ALIGN 0 12161 #define RX_X2_CONTROL0_MISC_0_BRCM_MODE_USE_K20PT5_BITS 1 12162 #define RX_X2_CONTROL0_MISC_0_BRCM_MODE_USE_K20PT5_SHIFT 8 12163 12164 /* RX_X2_Control0 :: misc_0 :: reserved2 [07:02] */ 12165 #define RX_X2_CONTROL0_MISC_0_RESERVED2_MASK 0x00fc 12166 #define RX_X2_CONTROL0_MISC_0_RESERVED2_ALIGN 0 12167 #define RX_X2_CONTROL0_MISC_0_RESERVED2_BITS 6 12168 #define RX_X2_CONTROL0_MISC_0_RESERVED2_SHIFT 2 12169 12170 /* RX_X2_Control0 :: misc_0 :: dis_cl82_bermon [01:01] */ 12171 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_MASK 0x0002 12172 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_ALIGN 0 12173 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_BITS 1 12174 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_SHIFT 1 12175 12176 /* RX_X2_Control0 :: misc_0 :: bypass_cl82rxsm [00:00] */ 12177 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_MASK 0x0001 12178 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_ALIGN 0 12179 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_BITS 1 12180 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_SHIFT 0 12181 12182 12183 /**************************************************************************** 12184 * RX_X2_Control0 :: misc_1 12185 */ 12186 /* RX_X2_Control0 :: misc_1 :: reserved0 [15:10] */ 12187 #define RX_X2_CONTROL0_MISC_1_RESERVED0_MASK 0xfc00 12188 #define RX_X2_CONTROL0_MISC_1_RESERVED0_ALIGN 0 12189 #define RX_X2_CONTROL0_MISC_1_RESERVED0_BITS 6 12190 #define RX_X2_CONTROL0_MISC_1_RESERVED0_SHIFT 10 12191 12192 /* RX_X2_Control0 :: misc_1 :: cl82_rx_li_enable [09:09] */ 12193 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_MASK 0x0200 12194 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_ALIGN 0 12195 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_BITS 1 12196 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_SHIFT 9 12197 12198 /* RX_X2_Control0 :: misc_1 :: cl48_rx_li_enable [08:08] */ 12199 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LI_ENABLE_MASK 0x0100 12200 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LI_ENABLE_ALIGN 0 12201 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LI_ENABLE_BITS 1 12202 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LI_ENABLE_SHIFT 8 12203 12204 /* RX_X2_Control0 :: misc_1 :: reserved1 [07:04] */ 12205 #define RX_X2_CONTROL0_MISC_1_RESERVED1_MASK 0x00f0 12206 #define RX_X2_CONTROL0_MISC_1_RESERVED1_ALIGN 0 12207 #define RX_X2_CONTROL0_MISC_1_RESERVED1_BITS 4 12208 #define RX_X2_CONTROL0_MISC_1_RESERVED1_SHIFT 4 12209 12210 /* RX_X2_Control0 :: misc_1 :: cl48_rx_lf_enable [03:03] */ 12211 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LF_ENABLE_MASK 0x0008 12212 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LF_ENABLE_ALIGN 0 12213 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LF_ENABLE_BITS 1 12214 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LF_ENABLE_SHIFT 3 12215 12216 /* RX_X2_Control0 :: misc_1 :: cl48_rx_rf_enable [02:02] */ 12217 #define RX_X2_CONTROL0_MISC_1_CL48_RX_RF_ENABLE_MASK 0x0004 12218 #define RX_X2_CONTROL0_MISC_1_CL48_RX_RF_ENABLE_ALIGN 0 12219 #define RX_X2_CONTROL0_MISC_1_CL48_RX_RF_ENABLE_BITS 1 12220 #define RX_X2_CONTROL0_MISC_1_CL48_RX_RF_ENABLE_SHIFT 2 12221 12222 /* RX_X2_Control0 :: misc_1 :: cl82_rx_lf_enable [01:01] */ 12223 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_MASK 0x0002 12224 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_ALIGN 0 12225 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_BITS 1 12226 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_SHIFT 1 12227 12228 /* RX_X2_Control0 :: misc_1 :: cl82_rx_rf_enable [00:00] */ 12229 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_MASK 0x0001 12230 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_ALIGN 0 12231 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_BITS 1 12232 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_SHIFT 0 12233 12234 12235 /**************************************************************************** 12236 * TSC_WC4_TSC_USER2_RX_X2_Status0 12237 */ 12238 /**************************************************************************** 12239 * RX_X2_Status0 :: skew_status_0 12240 */ 12241 /* RX_X2_Status0 :: skew_status_0 :: cl48_skew_status [15:15] */ 12242 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEW_STATUS_MASK 0x8000 12243 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEW_STATUS_ALIGN 0 12244 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEW_STATUS_BITS 1 12245 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEW_STATUS_SHIFT 15 12246 12247 /* RX_X2_Status0 :: skew_status_0 :: cl48_skewacq_state_d_0 [14:12] */ 12248 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_0_MASK 0x7000 12249 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_0_ALIGN 0 12250 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_0_BITS 3 12251 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_0_SHIFT 12 12252 12253 /* RX_X2_Status0 :: skew_status_0 :: cl48_skewacq_state_d_1 [11:09] */ 12254 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_1_MASK 0x0e00 12255 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_1_ALIGN 0 12256 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_1_BITS 3 12257 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_1_SHIFT 9 12258 12259 /* RX_X2_Status0 :: skew_status_0 :: cl48_skewacq_state_d_2 [08:06] */ 12260 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_2_MASK 0x01c0 12261 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_2_ALIGN 0 12262 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_2_BITS 3 12263 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_2_SHIFT 6 12264 12265 /* RX_X2_Status0 :: skew_status_0 :: cl48_skewacq_state_d_3 [05:03] */ 12266 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_3_MASK 0x0038 12267 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_3_ALIGN 0 12268 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_3_BITS 3 12269 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_3_SHIFT 3 12270 12271 /* RX_X2_Status0 :: skew_status_0 :: reserved0 [02:00] */ 12272 #define RX_X2_STATUS0_SKEW_STATUS_0_RESERVED0_MASK 0x0007 12273 #define RX_X2_STATUS0_SKEW_STATUS_0_RESERVED0_ALIGN 0 12274 #define RX_X2_STATUS0_SKEW_STATUS_0_RESERVED0_BITS 3 12275 #define RX_X2_STATUS0_SKEW_STATUS_0_RESERVED0_SHIFT 0 12276 12277 12278 /**************************************************************************** 12279 * RX_X2_Status0 :: skew_status_1 12280 */ 12281 /* RX_X2_Status0 :: skew_status_1 :: reserved0 [15:08] */ 12282 #define RX_X2_STATUS0_SKEW_STATUS_1_RESERVED0_MASK 0xff00 12283 #define RX_X2_STATUS0_SKEW_STATUS_1_RESERVED0_ALIGN 0 12284 #define RX_X2_STATUS0_SKEW_STATUS_1_RESERVED0_BITS 8 12285 #define RX_X2_STATUS0_SKEW_STATUS_1_RESERVED0_SHIFT 8 12286 12287 /* RX_X2_Status0 :: skew_status_1 :: cl48_skewacq_state_l [07:00] */ 12288 #define RX_X2_STATUS0_SKEW_STATUS_1_CL48_SKEWACQ_STATE_L_MASK 0x00ff 12289 #define RX_X2_STATUS0_SKEW_STATUS_1_CL48_SKEWACQ_STATE_L_ALIGN 0 12290 #define RX_X2_STATUS0_SKEW_STATUS_1_CL48_SKEWACQ_STATE_L_BITS 8 12291 #define RX_X2_STATUS0_SKEW_STATUS_1_CL48_SKEWACQ_STATE_L_SHIFT 0 12292 12293 12294 /**************************************************************************** 12295 * TSC_WC4_TSC_USER2_CL82 12296 */ 12297 /**************************************************************************** 12298 * CL82 :: rx_decoder_status 12299 */ 12300 /* CL82 :: rx_decoder_status :: reserved0 [15:13] */ 12301 #define CL82_RX_DECODER_STATUS_RESERVED0_MASK 0xe000 12302 #define CL82_RX_DECODER_STATUS_RESERVED0_ALIGN 0 12303 #define CL82_RX_DECODER_STATUS_RESERVED0_BITS 3 12304 #define CL82_RX_DECODER_STATUS_RESERVED0_SHIFT 13 12305 12306 /* CL82 :: rx_decoder_status :: r_type_coded [12:07] */ 12307 #define CL82_RX_DECODER_STATUS_R_TYPE_CODED_MASK 0x1f80 12308 #define CL82_RX_DECODER_STATUS_R_TYPE_CODED_ALIGN 0 12309 #define CL82_RX_DECODER_STATUS_R_TYPE_CODED_BITS 6 12310 #define CL82_RX_DECODER_STATUS_R_TYPE_CODED_SHIFT 7 12311 12312 /* CL82 :: rx_decoder_status :: rxsm_state [06:00] */ 12313 #define CL82_RX_DECODER_STATUS_RXSM_STATE_MASK 0x007f 12314 #define CL82_RX_DECODER_STATUS_RXSM_STATE_ALIGN 0 12315 #define CL82_RX_DECODER_STATUS_RXSM_STATE_BITS 7 12316 #define CL82_RX_DECODER_STATUS_RXSM_STATE_SHIFT 0 12317 12318 12319 /**************************************************************************** 12320 * CL82 :: rx_deskew_ber_status 12321 */ 12322 /* CL82 :: rx_deskew_ber_status :: deskew_state [15:14] */ 12323 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_STATE_MASK 0xc000 12324 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_STATE_ALIGN 0 12325 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_STATE_BITS 2 12326 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_STATE_SHIFT 14 12327 12328 /* CL82 :: rx_deskew_ber_status :: deskew_his_state [13:12] */ 12329 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_HIS_STATE_MASK 0x3000 12330 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_HIS_STATE_ALIGN 0 12331 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_HIS_STATE_BITS 2 12332 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_HIS_STATE_SHIFT 12 12333 12334 /* CL82 :: rx_deskew_ber_status :: lbermon_state [11:06] */ 12335 #define CL82_RX_DESKEW_BER_STATUS_LBERMON_STATE_MASK 0x0fc0 12336 #define CL82_RX_DESKEW_BER_STATUS_LBERMON_STATE_ALIGN 0 12337 #define CL82_RX_DESKEW_BER_STATUS_LBERMON_STATE_BITS 6 12338 #define CL82_RX_DESKEW_BER_STATUS_LBERMON_STATE_SHIFT 6 12339 12340 /* CL82 :: rx_deskew_ber_status :: bermon_state [05:00] */ 12341 #define CL82_RX_DESKEW_BER_STATUS_BERMON_STATE_MASK 0x003f 12342 #define CL82_RX_DESKEW_BER_STATUS_BERMON_STATE_ALIGN 0 12343 #define CL82_RX_DESKEW_BER_STATUS_BERMON_STATE_BITS 6 12344 #define CL82_RX_DESKEW_BER_STATUS_BERMON_STATE_SHIFT 0 12345 12346 12347 /**************************************************************************** 12348 * CL82 :: cl82_ber_ho 12349 */ 12350 /* CL82 :: cl82_ber_ho :: reserved0 [15:14] */ 12351 #define CL82_CL82_BER_HO_RESERVED0_MASK 0xc000 12352 #define CL82_CL82_BER_HO_RESERVED0_ALIGN 0 12353 #define CL82_CL82_BER_HO_RESERVED0_BITS 2 12354 #define CL82_CL82_BER_HO_RESERVED0_SHIFT 14 12355 12356 /* CL82 :: cl82_ber_ho :: cl82_ber_ho [13:00] */ 12357 #define CL82_CL82_BER_HO_CL82_BER_HO_MASK 0x3fff 12358 #define CL82_CL82_BER_HO_CL82_BER_HO_ALIGN 0 12359 #define CL82_CL82_BER_HO_CL82_BER_HO_BITS 14 12360 #define CL82_CL82_BER_HO_CL82_BER_HO_SHIFT 0 12361 12362 12363 /**************************************************************************** 12364 * TSC_WC4_TSC_USER4_anaTx 12365 */ 12366 /**************************************************************************** 12367 * anaTx :: AStatus0 12368 */ 12369 /* anaTx :: AStatus0 :: tx_sel_halfrate [15:15] */ 12370 #define ANATX_ASTATUS0_TX_SEL_HALFRATE_MASK 0x8000 12371 #define ANATX_ASTATUS0_TX_SEL_HALFRATE_ALIGN 0 12372 #define ANATX_ASTATUS0_TX_SEL_HALFRATE_BITS 1 12373 #define ANATX_ASTATUS0_TX_SEL_HALFRATE_SHIFT 15 12374 12375 /* anaTx :: AStatus0 :: tx_fir_tap_post [14:10] */ 12376 #define ANATX_ASTATUS0_TX_FIR_TAP_POST_MASK 0x7c00 12377 #define ANATX_ASTATUS0_TX_FIR_TAP_POST_ALIGN 0 12378 #define ANATX_ASTATUS0_TX_FIR_TAP_POST_BITS 5 12379 #define ANATX_ASTATUS0_TX_FIR_TAP_POST_SHIFT 10 12380 12381 /* anaTx :: AStatus0 :: tx_fir_tap_main [09:04] */ 12382 #define ANATX_ASTATUS0_TX_FIR_TAP_MAIN_MASK 0x03f0 12383 #define ANATX_ASTATUS0_TX_FIR_TAP_MAIN_ALIGN 0 12384 #define ANATX_ASTATUS0_TX_FIR_TAP_MAIN_BITS 6 12385 #define ANATX_ASTATUS0_TX_FIR_TAP_MAIN_SHIFT 4 12386 12387 /* anaTx :: AStatus0 :: tx_fir_tap_pre [03:00] */ 12388 #define ANATX_ASTATUS0_TX_FIR_TAP_PRE_MASK 0x000f 12389 #define ANATX_ASTATUS0_TX_FIR_TAP_PRE_ALIGN 0 12390 #define ANATX_ASTATUS0_TX_FIR_TAP_PRE_BITS 4 12391 #define ANATX_ASTATUS0_TX_FIR_TAP_PRE_SHIFT 0 12392 12393 12394 /**************************************************************************** 12395 * anaTx :: AControl0 12396 */ 12397 /* anaTx :: AControl0 :: reserved0 [15:06] */ 12398 #define ANATX_ACONTROL0_RESERVED0_MASK 0xffc0 12399 #define ANATX_ACONTROL0_RESERVED0_ALIGN 0 12400 #define ANATX_ACONTROL0_RESERVED0_BITS 10 12401 #define ANATX_ACONTROL0_RESERVED0_SHIFT 6 12402 12403 /* anaTx :: AControl0 :: txpol_flip [05:05] */ 12404 #define ANATX_ACONTROL0_TXPOL_FLIP_MASK 0x0020 12405 #define ANATX_ACONTROL0_TXPOL_FLIP_ALIGN 0 12406 #define ANATX_ACONTROL0_TXPOL_FLIP_BITS 1 12407 #define ANATX_ACONTROL0_TXPOL_FLIP_SHIFT 5 12408 12409 /* anaTx :: AControl0 :: reserved1 [04:00] */ 12410 #define ANATX_ACONTROL0_RESERVED1_MASK 0x001f 12411 #define ANATX_ACONTROL0_RESERVED1_ALIGN 0 12412 #define ANATX_ACONTROL0_RESERVED1_BITS 5 12413 #define ANATX_ACONTROL0_RESERVED1_SHIFT 0 12414 12415 12416 /**************************************************************************** 12417 * anaTx :: AStatus1 12418 */ 12419 /* anaTx :: AStatus1 :: tx_sts [15:00] */ 12420 #define ANATX_ASTATUS1_TX_STS_MASK 0xffff 12421 #define ANATX_ASTATUS1_TX_STS_ALIGN 0 12422 #define ANATX_ASTATUS1_TX_STS_BITS 16 12423 #define ANATX_ASTATUS1_TX_STS_SHIFT 0 12424 12425 12426 /**************************************************************************** 12427 * anaTx :: TxAControl1 12428 */ 12429 /* anaTx :: TxAControl1 :: ipredrv [15:13] */ 12430 #define ANATX_TXACONTROL1_IPREDRV_MASK 0xe000 12431 #define ANATX_TXACONTROL1_IPREDRV_ALIGN 0 12432 #define ANATX_TXACONTROL1_IPREDRV_BITS 3 12433 #define ANATX_TXACONTROL1_IPREDRV_SHIFT 13 12434 12435 /* anaTx :: TxAControl1 :: refl_tx [12:12] */ 12436 #define ANATX_TXACONTROL1_REFL_TX_MASK 0x1000 12437 #define ANATX_TXACONTROL1_REFL_TX_ALIGN 0 12438 #define ANATX_TXACONTROL1_REFL_TX_BITS 1 12439 #define ANATX_TXACONTROL1_REFL_TX_SHIFT 12 12440 12441 /* anaTx :: TxAControl1 :: refh_tx [11:11] */ 12442 #define ANATX_TXACONTROL1_REFH_TX_MASK 0x0800 12443 #define ANATX_TXACONTROL1_REFH_TX_ALIGN 0 12444 #define ANATX_TXACONTROL1_REFH_TX_BITS 1 12445 #define ANATX_TXACONTROL1_REFH_TX_SHIFT 11 12446 12447 /* anaTx :: TxAControl1 :: newbias_en [10:10] */ 12448 #define ANATX_TXACONTROL1_NEWBIAS_EN_MASK 0x0400 12449 #define ANATX_TXACONTROL1_NEWBIAS_EN_ALIGN 0 12450 #define ANATX_TXACONTROL1_NEWBIAS_EN_BITS 1 12451 #define ANATX_TXACONTROL1_NEWBIAS_EN_SHIFT 10 12452 12453 /* anaTx :: TxAControl1 :: drivermode [09:09] */ 12454 #define ANATX_TXACONTROL1_DRIVERMODE_MASK 0x0200 12455 #define ANATX_TXACONTROL1_DRIVERMODE_ALIGN 0 12456 #define ANATX_TXACONTROL1_DRIVERMODE_BITS 1 12457 #define ANATX_TXACONTROL1_DRIVERMODE_SHIFT 9 12458 12459 /* anaTx :: TxAControl1 :: vddr_bgb [08:08] */ 12460 #define ANATX_TXACONTROL1_VDDR_BGB_MASK 0x0100 12461 #define ANATX_TXACONTROL1_VDDR_BGB_ALIGN 0 12462 #define ANATX_TXACONTROL1_VDDR_BGB_BITS 1 12463 #define ANATX_TXACONTROL1_VDDR_BGB_SHIFT 8 12464 12465 /* anaTx :: TxAControl1 :: ticksel [07:06] */ 12466 #define ANATX_TXACONTROL1_TICKSEL_MASK 0x00c0 12467 #define ANATX_TXACONTROL1_TICKSEL_ALIGN 0 12468 #define ANATX_TXACONTROL1_TICKSEL_BITS 2 12469 #define ANATX_TXACONTROL1_TICKSEL_SHIFT 6 12470 12471 /* anaTx :: TxAControl1 :: reserved0 [05:04] */ 12472 #define ANATX_TXACONTROL1_RESERVED0_MASK 0x0030 12473 #define ANATX_TXACONTROL1_RESERVED0_ALIGN 0 12474 #define ANATX_TXACONTROL1_RESERVED0_BITS 2 12475 #define ANATX_TXACONTROL1_RESERVED0_SHIFT 4 12476 12477 /* anaTx :: TxAControl1 :: amp_ctrl [03:03] */ 12478 #define ANATX_TXACONTROL1_AMP_CTRL_MASK 0x0008 12479 #define ANATX_TXACONTROL1_AMP_CTRL_ALIGN 0 12480 #define ANATX_TXACONTROL1_AMP_CTRL_BITS 1 12481 #define ANATX_TXACONTROL1_AMP_CTRL_SHIFT 3 12482 12483 /* anaTx :: TxAControl1 :: ibias [02:00] */ 12484 #define ANATX_TXACONTROL1_IBIAS_MASK 0x0007 12485 #define ANATX_TXACONTROL1_IBIAS_ALIGN 0 12486 #define ANATX_TXACONTROL1_IBIAS_BITS 3 12487 #define ANATX_TXACONTROL1_IBIAS_SHIFT 0 12488 12489 12490 /**************************************************************************** 12491 * anaTx :: TxAControl2 12492 */ 12493 /* anaTx :: TxAControl2 :: ickbuf [15:14] */ 12494 #define ANATX_TXACONTROL2_ICKBUF_MASK 0xc000 12495 #define ANATX_TXACONTROL2_ICKBUF_ALIGN 0 12496 #define ANATX_TXACONTROL2_ICKBUF_BITS 2 12497 #define ANATX_TXACONTROL2_ICKBUF_SHIFT 14 12498 12499 /* anaTx :: TxAControl2 :: ickbuf2T [13:11] */ 12500 #define ANATX_TXACONTROL2_ICKBUF2T_MASK 0x3800 12501 #define ANATX_TXACONTROL2_ICKBUF2T_ALIGN 0 12502 #define ANATX_TXACONTROL2_ICKBUF2T_BITS 3 12503 #define ANATX_TXACONTROL2_ICKBUF2T_SHIFT 11 12504 12505 /* anaTx :: TxAControl2 :: imin_predrv [10:10] */ 12506 #define ANATX_TXACONTROL2_IMIN_PREDRV_MASK 0x0400 12507 #define ANATX_TXACONTROL2_IMIN_PREDRV_ALIGN 0 12508 #define ANATX_TXACONTROL2_IMIN_PREDRV_BITS 1 12509 #define ANATX_TXACONTROL2_IMIN_PREDRV_SHIFT 10 12510 12511 /* anaTx :: TxAControl2 :: imax_predrv [09:09] */ 12512 #define ANATX_TXACONTROL2_IMAX_PREDRV_MASK 0x0200 12513 #define ANATX_TXACONTROL2_IMAX_PREDRV_ALIGN 0 12514 #define ANATX_TXACONTROL2_IMAX_PREDRV_BITS 1 12515 #define ANATX_TXACONTROL2_IMAX_PREDRV_SHIFT 9 12516 12517 /* anaTx :: TxAControl2 :: imode_predrv [08:08] */ 12518 #define ANATX_TXACONTROL2_IMODE_PREDRV_MASK 0x0100 12519 #define ANATX_TXACONTROL2_IMODE_PREDRV_ALIGN 0 12520 #define ANATX_TXACONTROL2_IMODE_PREDRV_BITS 1 12521 #define ANATX_TXACONTROL2_IMODE_PREDRV_SHIFT 8 12522 12523 /* anaTx :: TxAControl2 :: imux [07:05] */ 12524 #define ANATX_TXACONTROL2_IMUX_MASK 0x00e0 12525 #define ANATX_TXACONTROL2_IMUX_ALIGN 0 12526 #define ANATX_TXACONTROL2_IMUX_BITS 3 12527 #define ANATX_TXACONTROL2_IMUX_SHIFT 5 12528 12529 /* anaTx :: TxAControl2 :: imin_drvr [04:04] */ 12530 #define ANATX_TXACONTROL2_IMIN_DRVR_MASK 0x0010 12531 #define ANATX_TXACONTROL2_IMIN_DRVR_ALIGN 0 12532 #define ANATX_TXACONTROL2_IMIN_DRVR_BITS 1 12533 #define ANATX_TXACONTROL2_IMIN_DRVR_SHIFT 4 12534 12535 /* anaTx :: TxAControl2 :: imax_drvr [03:03] */ 12536 #define ANATX_TXACONTROL2_IMAX_DRVR_MASK 0x0008 12537 #define ANATX_TXACONTROL2_IMAX_DRVR_ALIGN 0 12538 #define ANATX_TXACONTROL2_IMAX_DRVR_BITS 1 12539 #define ANATX_TXACONTROL2_IMAX_DRVR_SHIFT 3 12540 12541 /* anaTx :: TxAControl2 :: imode_drvr [02:02] */ 12542 #define ANATX_TXACONTROL2_IMODE_DRVR_MASK 0x0004 12543 #define ANATX_TXACONTROL2_IMODE_DRVR_ALIGN 0 12544 #define ANATX_TXACONTROL2_IMODE_DRVR_BITS 1 12545 #define ANATX_TXACONTROL2_IMODE_DRVR_SHIFT 2 12546 12547 /* anaTx :: TxAControl2 :: reserved0 [01:00] */ 12548 #define ANATX_TXACONTROL2_RESERVED0_MASK 0x0003 12549 #define ANATX_TXACONTROL2_RESERVED0_ALIGN 0 12550 #define ANATX_TXACONTROL2_RESERVED0_BITS 2 12551 #define ANATX_TXACONTROL2_RESERVED0_SHIFT 0 12552 12553 12554 /**************************************************************************** 12555 * anaTx :: Tx_Driver 12556 */ 12557 /* anaTx :: Tx_Driver :: Elec_Idle [15:15] */ 12558 #define ANATX_TX_DRIVER_ELEC_IDLE_MASK 0x8000 12559 #define ANATX_TX_DRIVER_ELEC_IDLE_ALIGN 0 12560 #define ANATX_TX_DRIVER_ELEC_IDLE_BITS 1 12561 #define ANATX_TX_DRIVER_ELEC_IDLE_SHIFT 15 12562 12563 /* anaTx :: Tx_Driver :: post2_coeff [14:12] */ 12564 #define ANATX_TX_DRIVER_POST2_COEFF_MASK 0x7000 12565 #define ANATX_TX_DRIVER_POST2_COEFF_ALIGN 0 12566 #define ANATX_TX_DRIVER_POST2_COEFF_BITS 3 12567 #define ANATX_TX_DRIVER_POST2_COEFF_SHIFT 12 12568 12569 /* anaTx :: Tx_Driver :: Idriver [11:08] */ 12570 #define ANATX_TX_DRIVER_IDRIVER_MASK 0x0f00 12571 #define ANATX_TX_DRIVER_IDRIVER_ALIGN 0 12572 #define ANATX_TX_DRIVER_IDRIVER_BITS 4 12573 #define ANATX_TX_DRIVER_IDRIVER_SHIFT 8 12574 #define ANATX_TX_DRIVER_IDRIVER_v680mV 0 12575 #define ANATX_TX_DRIVER_IDRIVER_v730mV 1 12576 #define ANATX_TX_DRIVER_IDRIVER_v780mV 2 12577 #define ANATX_TX_DRIVER_IDRIVER_v830mV 3 12578 #define ANATX_TX_DRIVER_IDRIVER_v880mV 4 12579 #define ANATX_TX_DRIVER_IDRIVER_v930mV 5 12580 #define ANATX_TX_DRIVER_IDRIVER_v980mV 6 12581 #define ANATX_TX_DRIVER_IDRIVER_v1010mV 7 12582 #define ANATX_TX_DRIVER_IDRIVER_v1040mV 8 12583 #define ANATX_TX_DRIVER_IDRIVER_v1060mV 9 12584 #define ANATX_TX_DRIVER_IDRIVER_v1070mV 10 12585 #define ANATX_TX_DRIVER_IDRIVER_v1080mV 11 12586 #define ANATX_TX_DRIVER_IDRIVER_v1085mV 12 12587 #define ANATX_TX_DRIVER_IDRIVER_v1090mV 13 12588 #define ANATX_TX_DRIVER_IDRIVER_v1095mV 14 12589 #define ANATX_TX_DRIVER_IDRIVER_v1100mV 15 12590 12591 /* anaTx :: Tx_Driver :: Ipredriver [07:04] */ 12592 #define ANATX_TX_DRIVER_IPREDRIVER_MASK 0x00f0 12593 #define ANATX_TX_DRIVER_IPREDRIVER_ALIGN 0 12594 #define ANATX_TX_DRIVER_IPREDRIVER_BITS 4 12595 #define ANATX_TX_DRIVER_IPREDRIVER_SHIFT 4 12596 12597 /* anaTx :: Tx_Driver :: ifir [03:01] */ 12598 #define ANATX_TX_DRIVER_IFIR_MASK 0x000e 12599 #define ANATX_TX_DRIVER_IFIR_ALIGN 0 12600 #define ANATX_TX_DRIVER_IFIR_BITS 3 12601 #define ANATX_TX_DRIVER_IFIR_SHIFT 1 12602 12603 /* anaTx :: Tx_Driver :: ickbuf2 [00:00] */ 12604 #define ANATX_TX_DRIVER_ICKBUF2_MASK 0x0001 12605 #define ANATX_TX_DRIVER_ICKBUF2_ALIGN 0 12606 #define ANATX_TX_DRIVER_ICKBUF2_BITS 1 12607 #define ANATX_TX_DRIVER_ICKBUF2_SHIFT 0 12608 12609 12610 /**************************************************************************** 12611 * anaTx :: AControl5 12612 */ 12613 /* anaTx :: AControl5 :: reserved0 [15:02] */ 12614 #define ANATX_ACONTROL5_RESERVED0_MASK 0xfffc 12615 #define ANATX_ACONTROL5_RESERVED0_ALIGN 0 12616 #define ANATX_ACONTROL5_RESERVED0_BITS 14 12617 #define ANATX_ACONTROL5_RESERVED0_SHIFT 2 12618 12619 /* anaTx :: AControl5 :: force_tx_sel_halfrate_val [01:01] */ 12620 #define ANATX_ACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_MASK 0x0002 12621 #define ANATX_ACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_ALIGN 0 12622 #define ANATX_ACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_BITS 1 12623 #define ANATX_ACONTROL5_FORCE_TX_SEL_HALFRATE_VAL_SHIFT 1 12624 12625 /* anaTx :: AControl5 :: force_tx_sel_halfrate [00:00] */ 12626 #define ANATX_ACONTROL5_FORCE_TX_SEL_HALFRATE_MASK 0x0001 12627 #define ANATX_ACONTROL5_FORCE_TX_SEL_HALFRATE_ALIGN 0 12628 #define ANATX_ACONTROL5_FORCE_TX_SEL_HALFRATE_BITS 1 12629 #define ANATX_ACONTROL5_FORCE_TX_SEL_HALFRATE_SHIFT 0 12630 12631 12632 /**************************************************************************** 12633 * anaTx :: AControl6 12634 */ 12635 /* anaTx :: AControl6 :: reserved0 [15:01] */ 12636 #define ANATX_ACONTROL6_RESERVED0_MASK 0xfffe 12637 #define ANATX_ACONTROL6_RESERVED0_ALIGN 0 12638 #define ANATX_ACONTROL6_RESERVED0_BITS 15 12639 #define ANATX_ACONTROL6_RESERVED0_SHIFT 1 12640 12641 /* anaTx :: AControl6 :: disable_tx_r [00:00] */ 12642 #define ANATX_ACONTROL6_DISABLE_TX_R_MASK 0x0001 12643 #define ANATX_ACONTROL6_DISABLE_TX_R_ALIGN 0 12644 #define ANATX_ACONTROL6_DISABLE_TX_R_BITS 1 12645 #define ANATX_ACONTROL6_DISABLE_TX_R_SHIFT 0 12646 12647 12648 /**************************************************************************** 12649 * TSC_WC4_TSC_USER4_anaRx 12650 */ 12651 /**************************************************************************** 12652 * anaRx :: AControl0 12653 */ 12654 /* anaRx :: AControl0 :: rxpol_flip [15:15] */ 12655 #define ANARX_ACONTROL0_RXPOL_FLIP_MASK 0x8000 12656 #define ANARX_ACONTROL0_RXPOL_FLIP_ALIGN 0 12657 #define ANARX_ACONTROL0_RXPOL_FLIP_BITS 1 12658 #define ANARX_ACONTROL0_RXPOL_FLIP_SHIFT 15 12659 12660 /* anaRx :: AControl0 :: reserved0 [14:12] */ 12661 #define ANARX_ACONTROL0_RESERVED0_MASK 0x7000 12662 #define ANARX_ACONTROL0_RESERVED0_ALIGN 0 12663 #define ANARX_ACONTROL0_RESERVED0_BITS 3 12664 #define ANARX_ACONTROL0_RESERVED0_SHIFT 12 12665 12666 /* anaRx :: AControl0 :: Non_cx4_Signal_detect_filter_period [11:03] */ 12667 #define ANARX_ACONTROL0_NON_CX4_SIGNAL_DETECT_FILTER_PERIOD_MASK 0x0ff8 12668 #define ANARX_ACONTROL0_NON_CX4_SIGNAL_DETECT_FILTER_PERIOD_ALIGN 0 12669 #define ANARX_ACONTROL0_NON_CX4_SIGNAL_DETECT_FILTER_PERIOD_BITS 9 12670 #define ANARX_ACONTROL0_NON_CX4_SIGNAL_DETECT_FILTER_PERIOD_SHIFT 3 12671 12672 /* anaRx :: AControl0 :: reserved1 [02:00] */ 12673 #define ANARX_ACONTROL0_RESERVED1_MASK 0x0007 12674 #define ANARX_ACONTROL0_RESERVED1_ALIGN 0 12675 #define ANARX_ACONTROL0_RESERVED1_BITS 3 12676 #define ANARX_ACONTROL0_RESERVED1_SHIFT 0 12677 12678 12679 /**************************************************************************** 12680 * anaRx :: Astatus1 12681 */ 12682 /* anaRx :: Astatus1 :: sigdet [15:15] */ 12683 #define ANARX_ASTATUS1_SIGDET_MASK 0x8000 12684 #define ANARX_ASTATUS1_SIGDET_ALIGN 0 12685 #define ANARX_ASTATUS1_SIGDET_BITS 1 12686 #define ANARX_ASTATUS1_SIGDET_SHIFT 15 12687 12688 /* anaRx :: Astatus1 :: rx_pf [14:11] */ 12689 #define ANARX_ASTATUS1_RX_PF_MASK 0x7800 12690 #define ANARX_ASTATUS1_RX_PF_ALIGN 0 12691 #define ANARX_ASTATUS1_RX_PF_BITS 4 12692 #define ANARX_ASTATUS1_RX_PF_SHIFT 11 12693 12694 /* anaRx :: Astatus1 :: tap1_dfe_gray [10:05] */ 12695 #define ANARX_ASTATUS1_TAP1_DFE_GRAY_MASK 0x07e0 12696 #define ANARX_ASTATUS1_TAP1_DFE_GRAY_ALIGN 0 12697 #define ANARX_ASTATUS1_TAP1_DFE_GRAY_BITS 6 12698 #define ANARX_ASTATUS1_TAP1_DFE_GRAY_SHIFT 5 12699 12700 /* anaRx :: Astatus1 :: vga [04:00] */ 12701 #define ANARX_ASTATUS1_VGA_MASK 0x001f 12702 #define ANARX_ASTATUS1_VGA_ALIGN 0 12703 #define ANARX_ASTATUS1_VGA_BITS 5 12704 #define ANARX_ASTATUS1_VGA_SHIFT 0 12705 12706 12707 /**************************************************************************** 12708 * anaRx :: RxAControl1 12709 */ 12710 /* anaRx :: RxAControl1 :: imode_vcm [15:15] */ 12711 #define ANARX_RXACONTROL1_IMODE_VCM_MASK 0x8000 12712 #define ANARX_RXACONTROL1_IMODE_VCM_ALIGN 0 12713 #define ANARX_RXACONTROL1_IMODE_VCM_BITS 1 12714 #define ANARX_RXACONTROL1_IMODE_VCM_SHIFT 15 12715 12716 /* anaRx :: RxAControl1 :: imin_vcm [14:14] */ 12717 #define ANARX_RXACONTROL1_IMIN_VCM_MASK 0x4000 12718 #define ANARX_RXACONTROL1_IMIN_VCM_ALIGN 0 12719 #define ANARX_RXACONTROL1_IMIN_VCM_BITS 1 12720 #define ANARX_RXACONTROL1_IMIN_VCM_SHIFT 14 12721 12722 /* anaRx :: RxAControl1 :: en_10gmode [13:13] */ 12723 #define ANARX_RXACONTROL1_EN_10GMODE_MASK 0x2000 12724 #define ANARX_RXACONTROL1_EN_10GMODE_ALIGN 0 12725 #define ANARX_RXACONTROL1_EN_10GMODE_BITS 1 12726 #define ANARX_RXACONTROL1_EN_10GMODE_SHIFT 13 12727 12728 /* anaRx :: RxAControl1 :: imode_sigdet [12:12] */ 12729 #define ANARX_RXACONTROL1_IMODE_SIGDET_MASK 0x1000 12730 #define ANARX_RXACONTROL1_IMODE_SIGDET_ALIGN 0 12731 #define ANARX_RXACONTROL1_IMODE_SIGDET_BITS 1 12732 #define ANARX_RXACONTROL1_IMODE_SIGDET_SHIFT 12 12733 12734 /* anaRx :: RxAControl1 :: vga_bw_ext [11:11] */ 12735 #define ANARX_RXACONTROL1_VGA_BW_EXT_MASK 0x0800 12736 #define ANARX_RXACONTROL1_VGA_BW_EXT_ALIGN 0 12737 #define ANARX_RXACONTROL1_VGA_BW_EXT_BITS 1 12738 #define ANARX_RXACONTROL1_VGA_BW_EXT_SHIFT 11 12739 12740 /* anaRx :: RxAControl1 :: refh_rx [10:10] */ 12741 #define ANARX_RXACONTROL1_REFH_RX_MASK 0x0400 12742 #define ANARX_RXACONTROL1_REFH_RX_ALIGN 0 12743 #define ANARX_RXACONTROL1_REFH_RX_BITS 1 12744 #define ANARX_RXACONTROL1_REFH_RX_SHIFT 10 12745 12746 /* anaRx :: RxAControl1 :: refl_rx [09:09] */ 12747 #define ANARX_RXACONTROL1_REFL_RX_MASK 0x0200 12748 #define ANARX_RXACONTROL1_REFL_RX_ALIGN 0 12749 #define ANARX_RXACONTROL1_REFL_RX_BITS 1 12750 #define ANARX_RXACONTROL1_REFL_RX_SHIFT 9 12751 12752 /* anaRx :: RxAControl1 :: tport_en [08:08] */ 12753 #define ANARX_RXACONTROL1_TPORT_EN_MASK 0x0100 12754 #define ANARX_RXACONTROL1_TPORT_EN_ALIGN 0 12755 #define ANARX_RXACONTROL1_TPORT_EN_BITS 1 12756 #define ANARX_RXACONTROL1_TPORT_EN_SHIFT 8 12757 12758 /* anaRx :: RxAControl1 :: vddr_bg [07:07] */ 12759 #define ANARX_RXACONTROL1_VDDR_BG_MASK 0x0080 12760 #define ANARX_RXACONTROL1_VDDR_BG_ALIGN 0 12761 #define ANARX_RXACONTROL1_VDDR_BG_BITS 1 12762 #define ANARX_RXACONTROL1_VDDR_BG_SHIFT 7 12763 12764 /* anaRx :: RxAControl1 :: sig_pwrdn [06:06] */ 12765 #define ANARX_RXACONTROL1_SIG_PWRDN_MASK 0x0040 12766 #define ANARX_RXACONTROL1_SIG_PWRDN_ALIGN 0 12767 #define ANARX_RXACONTROL1_SIG_PWRDN_BITS 1 12768 #define ANARX_RXACONTROL1_SIG_PWRDN_SHIFT 6 12769 12770 /* anaRx :: RxAControl1 :: offset_ctrl [05:03] */ 12771 #define ANARX_RXACONTROL1_OFFSET_CTRL_MASK 0x0038 12772 #define ANARX_RXACONTROL1_OFFSET_CTRL_ALIGN 0 12773 #define ANARX_RXACONTROL1_OFFSET_CTRL_BITS 3 12774 #define ANARX_RXACONTROL1_OFFSET_CTRL_SHIFT 3 12775 12776 /* anaRx :: RxAControl1 :: offset_sel [02:02] */ 12777 #define ANARX_RXACONTROL1_OFFSET_SEL_MASK 0x0004 12778 #define ANARX_RXACONTROL1_OFFSET_SEL_ALIGN 0 12779 #define ANARX_RXACONTROL1_OFFSET_SEL_BITS 1 12780 #define ANARX_RXACONTROL1_OFFSET_SEL_SHIFT 2 12781 12782 /* anaRx :: RxAControl1 :: sel_dfeckdelay1 [01:01] */ 12783 #define ANARX_RXACONTROL1_SEL_DFECKDELAY1_MASK 0x0002 12784 #define ANARX_RXACONTROL1_SEL_DFECKDELAY1_ALIGN 0 12785 #define ANARX_RXACONTROL1_SEL_DFECKDELAY1_BITS 1 12786 #define ANARX_RXACONTROL1_SEL_DFECKDELAY1_SHIFT 1 12787 12788 /* anaRx :: RxAControl1 :: sel_dfeckdelay0 [00:00] */ 12789 #define ANARX_RXACONTROL1_SEL_DFECKDELAY0_MASK 0x0001 12790 #define ANARX_RXACONTROL1_SEL_DFECKDELAY0_ALIGN 0 12791 #define ANARX_RXACONTROL1_SEL_DFECKDELAY0_BITS 1 12792 #define ANARX_RXACONTROL1_SEL_DFECKDELAY0_SHIFT 0 12793 12794 12795 /**************************************************************************** 12796 * anaRx :: RxAControl2 12797 */ 12798 /* anaRx :: RxAControl2 :: imax_ctat [15:15] */ 12799 #define ANARX_RXACONTROL2_IMAX_CTAT_MASK 0x8000 12800 #define ANARX_RXACONTROL2_IMAX_CTAT_ALIGN 0 12801 #define ANARX_RXACONTROL2_IMAX_CTAT_BITS 1 12802 #define ANARX_RXACONTROL2_IMAX_CTAT_SHIFT 15 12803 12804 /* anaRx :: RxAControl2 :: imode_ctat [14:14] */ 12805 #define ANARX_RXACONTROL2_IMODE_CTAT_MASK 0x4000 12806 #define ANARX_RXACONTROL2_IMODE_CTAT_ALIGN 0 12807 #define ANARX_RXACONTROL2_IMODE_CTAT_BITS 1 12808 #define ANARX_RXACONTROL2_IMODE_CTAT_SHIFT 14 12809 12810 /* anaRx :: RxAControl2 :: imin_ctat [13:13] */ 12811 #define ANARX_RXACONTROL2_IMIN_CTAT_MASK 0x2000 12812 #define ANARX_RXACONTROL2_IMIN_CTAT_ALIGN 0 12813 #define ANARX_RXACONTROL2_IMIN_CTAT_BITS 1 12814 #define ANARX_RXACONTROL2_IMIN_CTAT_SHIFT 13 12815 12816 /* anaRx :: RxAControl2 :: imax_eqfl [12:12] */ 12817 #define ANARX_RXACONTROL2_IMAX_EQFL_MASK 0x1000 12818 #define ANARX_RXACONTROL2_IMAX_EQFL_ALIGN 0 12819 #define ANARX_RXACONTROL2_IMAX_EQFL_BITS 1 12820 #define ANARX_RXACONTROL2_IMAX_EQFL_SHIFT 12 12821 12822 /* anaRx :: RxAControl2 :: imode_eqfl [11:11] */ 12823 #define ANARX_RXACONTROL2_IMODE_EQFL_MASK 0x0800 12824 #define ANARX_RXACONTROL2_IMODE_EQFL_ALIGN 0 12825 #define ANARX_RXACONTROL2_IMODE_EQFL_BITS 1 12826 #define ANARX_RXACONTROL2_IMODE_EQFL_SHIFT 11 12827 12828 /* anaRx :: RxAControl2 :: imin_eqfl [10:10] */ 12829 #define ANARX_RXACONTROL2_IMIN_EQFL_MASK 0x0400 12830 #define ANARX_RXACONTROL2_IMIN_EQFL_ALIGN 0 12831 #define ANARX_RXACONTROL2_IMIN_EQFL_BITS 1 12832 #define ANARX_RXACONTROL2_IMIN_EQFL_SHIFT 10 12833 12834 /* anaRx :: RxAControl2 :: imax_dfesum [09:09] */ 12835 #define ANARX_RXACONTROL2_IMAX_DFESUM_MASK 0x0200 12836 #define ANARX_RXACONTROL2_IMAX_DFESUM_ALIGN 0 12837 #define ANARX_RXACONTROL2_IMAX_DFESUM_BITS 1 12838 #define ANARX_RXACONTROL2_IMAX_DFESUM_SHIFT 9 12839 12840 /* anaRx :: RxAControl2 :: imode_dfesum [08:08] */ 12841 #define ANARX_RXACONTROL2_IMODE_DFESUM_MASK 0x0100 12842 #define ANARX_RXACONTROL2_IMODE_DFESUM_ALIGN 0 12843 #define ANARX_RXACONTROL2_IMODE_DFESUM_BITS 1 12844 #define ANARX_RXACONTROL2_IMODE_DFESUM_SHIFT 8 12845 12846 /* anaRx :: RxAControl2 :: imin_dfesum [07:07] */ 12847 #define ANARX_RXACONTROL2_IMIN_DFESUM_MASK 0x0080 12848 #define ANARX_RXACONTROL2_IMIN_DFESUM_ALIGN 0 12849 #define ANARX_RXACONTROL2_IMIN_DFESUM_BITS 1 12850 #define ANARX_RXACONTROL2_IMIN_DFESUM_SHIFT 7 12851 12852 /* anaRx :: RxAControl2 :: imax_vga [06:06] */ 12853 #define ANARX_RXACONTROL2_IMAX_VGA_MASK 0x0040 12854 #define ANARX_RXACONTROL2_IMAX_VGA_ALIGN 0 12855 #define ANARX_RXACONTROL2_IMAX_VGA_BITS 1 12856 #define ANARX_RXACONTROL2_IMAX_VGA_SHIFT 6 12857 12858 /* anaRx :: RxAControl2 :: imode_vga [05:05] */ 12859 #define ANARX_RXACONTROL2_IMODE_VGA_MASK 0x0020 12860 #define ANARX_RXACONTROL2_IMODE_VGA_ALIGN 0 12861 #define ANARX_RXACONTROL2_IMODE_VGA_BITS 1 12862 #define ANARX_RXACONTROL2_IMODE_VGA_SHIFT 5 12863 12864 /* anaRx :: RxAControl2 :: imin_vga [04:04] */ 12865 #define ANARX_RXACONTROL2_IMIN_VGA_MASK 0x0010 12866 #define ANARX_RXACONTROL2_IMIN_VGA_ALIGN 0 12867 #define ANARX_RXACONTROL2_IMIN_VGA_BITS 1 12868 #define ANARX_RXACONTROL2_IMIN_VGA_SHIFT 4 12869 12870 /* anaRx :: RxAControl2 :: imax_interp [03:03] */ 12871 #define ANARX_RXACONTROL2_IMAX_INTERP_MASK 0x0008 12872 #define ANARX_RXACONTROL2_IMAX_INTERP_ALIGN 0 12873 #define ANARX_RXACONTROL2_IMAX_INTERP_BITS 1 12874 #define ANARX_RXACONTROL2_IMAX_INTERP_SHIFT 3 12875 12876 /* anaRx :: RxAControl2 :: imode_interp [02:02] */ 12877 #define ANARX_RXACONTROL2_IMODE_INTERP_MASK 0x0004 12878 #define ANARX_RXACONTROL2_IMODE_INTERP_ALIGN 0 12879 #define ANARX_RXACONTROL2_IMODE_INTERP_BITS 1 12880 #define ANARX_RXACONTROL2_IMODE_INTERP_SHIFT 2 12881 12882 /* anaRx :: RxAControl2 :: imin_interp [01:01] */ 12883 #define ANARX_RXACONTROL2_IMIN_INTERP_MASK 0x0002 12884 #define ANARX_RXACONTROL2_IMIN_INTERP_ALIGN 0 12885 #define ANARX_RXACONTROL2_IMIN_INTERP_BITS 1 12886 #define ANARX_RXACONTROL2_IMIN_INTERP_SHIFT 1 12887 12888 /* anaRx :: RxAControl2 :: imax_vcm [00:00] */ 12889 #define ANARX_RXACONTROL2_IMAX_VCM_MASK 0x0001 12890 #define ANARX_RXACONTROL2_IMAX_VCM_ALIGN 0 12891 #define ANARX_RXACONTROL2_IMAX_VCM_BITS 1 12892 #define ANARX_RXACONTROL2_IMAX_VCM_SHIFT 0 12893 12894 12895 /**************************************************************************** 12896 * anaRx :: RxAControl3 12897 */ 12898 /* anaRx :: RxAControl3 :: en_clk16 [15:15] */ 12899 #define ANARX_RXACONTROL3_EN_CLK16_MASK 0x8000 12900 #define ANARX_RXACONTROL3_EN_CLK16_ALIGN 0 12901 #define ANARX_RXACONTROL3_EN_CLK16_BITS 1 12902 #define ANARX_RXACONTROL3_EN_CLK16_SHIFT 15 12903 12904 /* anaRx :: RxAControl3 :: en_clk33 [14:14] */ 12905 #define ANARX_RXACONTROL3_EN_CLK33_MASK 0x4000 12906 #define ANARX_RXACONTROL3_EN_CLK33_ALIGN 0 12907 #define ANARX_RXACONTROL3_EN_CLK33_BITS 1 12908 #define ANARX_RXACONTROL3_EN_CLK33_SHIFT 14 12909 12910 /* anaRx :: RxAControl3 :: en_vcctrl [13:13] */ 12911 #define ANARX_RXACONTROL3_EN_VCCTRL_MASK 0x2000 12912 #define ANARX_RXACONTROL3_EN_VCCTRL_ALIGN 0 12913 #define ANARX_RXACONTROL3_EN_VCCTRL_BITS 1 12914 #define ANARX_RXACONTROL3_EN_VCCTRL_SHIFT 13 12915 12916 /* anaRx :: RxAControl3 :: sel_th4dfe1 [12:12] */ 12917 #define ANARX_RXACONTROL3_SEL_TH4DFE1_MASK 0x1000 12918 #define ANARX_RXACONTROL3_SEL_TH4DFE1_ALIGN 0 12919 #define ANARX_RXACONTROL3_SEL_TH4DFE1_BITS 1 12920 #define ANARX_RXACONTROL3_SEL_TH4DFE1_SHIFT 12 12921 12922 /* anaRx :: RxAControl3 :: sel_th4dfe0 [11:11] */ 12923 #define ANARX_RXACONTROL3_SEL_TH4DFE0_MASK 0x0800 12924 #define ANARX_RXACONTROL3_SEL_TH4DFE0_ALIGN 0 12925 #define ANARX_RXACONTROL3_SEL_TH4DFE0_BITS 1 12926 #define ANARX_RXACONTROL3_SEL_TH4DFE0_SHIFT 11 12927 12928 /* anaRx :: RxAControl3 :: selugbw1 [10:10] */ 12929 #define ANARX_RXACONTROL3_SELUGBW1_MASK 0x0400 12930 #define ANARX_RXACONTROL3_SELUGBW1_ALIGN 0 12931 #define ANARX_RXACONTROL3_SELUGBW1_BITS 1 12932 #define ANARX_RXACONTROL3_SELUGBW1_SHIFT 10 12933 12934 /* anaRx :: RxAControl3 :: selugbw0 [09:09] */ 12935 #define ANARX_RXACONTROL3_SELUGBW0_MASK 0x0200 12936 #define ANARX_RXACONTROL3_SELUGBW0_ALIGN 0 12937 #define ANARX_RXACONTROL3_SELUGBW0_BITS 1 12938 #define ANARX_RXACONTROL3_SELUGBW0_SHIFT 9 12939 12940 /* anaRx :: RxAControl3 :: imax_dfetap [08:08] */ 12941 #define ANARX_RXACONTROL3_IMAX_DFETAP_MASK 0x0100 12942 #define ANARX_RXACONTROL3_IMAX_DFETAP_ALIGN 0 12943 #define ANARX_RXACONTROL3_IMAX_DFETAP_BITS 1 12944 #define ANARX_RXACONTROL3_IMAX_DFETAP_SHIFT 8 12945 12946 /* anaRx :: RxAControl3 :: imode_dfetap [07:07] */ 12947 #define ANARX_RXACONTROL3_IMODE_DFETAP_MASK 0x0080 12948 #define ANARX_RXACONTROL3_IMODE_DFETAP_ALIGN 0 12949 #define ANARX_RXACONTROL3_IMODE_DFETAP_BITS 1 12950 #define ANARX_RXACONTROL3_IMODE_DFETAP_SHIFT 7 12951 12952 /* anaRx :: RxAControl3 :: imin_dfetap [06:06] */ 12953 #define ANARX_RXACONTROL3_IMIN_DFETAP_MASK 0x0040 12954 #define ANARX_RXACONTROL3_IMIN_DFETAP_ALIGN 0 12955 #define ANARX_RXACONTROL3_IMIN_DFETAP_BITS 1 12956 #define ANARX_RXACONTROL3_IMIN_DFETAP_SHIFT 6 12957 12958 /* anaRx :: RxAControl3 :: imax_slcd2c [05:05] */ 12959 #define ANARX_RXACONTROL3_IMAX_SLCD2C_MASK 0x0020 12960 #define ANARX_RXACONTROL3_IMAX_SLCD2C_ALIGN 0 12961 #define ANARX_RXACONTROL3_IMAX_SLCD2C_BITS 1 12962 #define ANARX_RXACONTROL3_IMAX_SLCD2C_SHIFT 5 12963 12964 /* anaRx :: RxAControl3 :: imode_slcd2c [04:04] */ 12965 #define ANARX_RXACONTROL3_IMODE_SLCD2C_MASK 0x0010 12966 #define ANARX_RXACONTROL3_IMODE_SLCD2C_ALIGN 0 12967 #define ANARX_RXACONTROL3_IMODE_SLCD2C_BITS 1 12968 #define ANARX_RXACONTROL3_IMODE_SLCD2C_SHIFT 4 12969 12970 /* anaRx :: RxAControl3 :: imin_slcd2c [03:03] */ 12971 #define ANARX_RXACONTROL3_IMIN_SLCD2C_MASK 0x0008 12972 #define ANARX_RXACONTROL3_IMIN_SLCD2C_ALIGN 0 12973 #define ANARX_RXACONTROL3_IMIN_SLCD2C_BITS 1 12974 #define ANARX_RXACONTROL3_IMIN_SLCD2C_SHIFT 3 12975 12976 /* anaRx :: RxAControl3 :: imax_dfevref [02:02] */ 12977 #define ANARX_RXACONTROL3_IMAX_DFEVREF_MASK 0x0004 12978 #define ANARX_RXACONTROL3_IMAX_DFEVREF_ALIGN 0 12979 #define ANARX_RXACONTROL3_IMAX_DFEVREF_BITS 1 12980 #define ANARX_RXACONTROL3_IMAX_DFEVREF_SHIFT 2 12981 12982 /* anaRx :: RxAControl3 :: imode_dfevref [01:01] */ 12983 #define ANARX_RXACONTROL3_IMODE_DFEVREF_MASK 0x0002 12984 #define ANARX_RXACONTROL3_IMODE_DFEVREF_ALIGN 0 12985 #define ANARX_RXACONTROL3_IMODE_DFEVREF_BITS 1 12986 #define ANARX_RXACONTROL3_IMODE_DFEVREF_SHIFT 1 12987 12988 /* anaRx :: RxAControl3 :: imin_dfevref [00:00] */ 12989 #define ANARX_RXACONTROL3_IMIN_DFEVREF_MASK 0x0001 12990 #define ANARX_RXACONTROL3_IMIN_DFEVREF_ALIGN 0 12991 #define ANARX_RXACONTROL3_IMIN_DFEVREF_BITS 1 12992 #define ANARX_RXACONTROL3_IMIN_DFEVREF_SHIFT 0 12993 12994 12995 /**************************************************************************** 12996 * TSC_WC4_TSC_USER4_PatGen0 12997 */ 12998 /**************************************************************************** 12999 * PatGen0 :: PatGenCtrl 13000 */ 13001 /* PatGen0 :: PatGenCtrl :: number_bit [15:13] */ 13002 #define PATGEN0_PATGENCTRL_NUMBER_BIT_MASK 0xe000 13003 #define PATGEN0_PATGENCTRL_NUMBER_BIT_ALIGN 0 13004 #define PATGEN0_PATGENCTRL_NUMBER_BIT_BITS 3 13005 #define PATGEN0_PATGENCTRL_NUMBER_BIT_SHIFT 13 13006 13007 /* PatGen0 :: PatGenCtrl :: reserved0 [12:09] */ 13008 #define PATGEN0_PATGENCTRL_RESERVED0_MASK 0x1e00 13009 #define PATGEN0_PATGENCTRL_RESERVED0_ALIGN 0 13010 #define PATGEN0_PATGENCTRL_RESERVED0_BITS 4 13011 #define PATGEN0_PATGENCTRL_RESERVED0_SHIFT 9 13012 13013 /* PatGen0 :: PatGenCtrl :: rx_fixed_pattern_check_enable [08:08] */ 13014 #define PATGEN0_PATGENCTRL_RX_FIXED_PATTERN_CHECK_ENABLE_MASK 0x0100 13015 #define PATGEN0_PATGENCTRL_RX_FIXED_PATTERN_CHECK_ENABLE_ALIGN 0 13016 #define PATGEN0_PATGENCTRL_RX_FIXED_PATTERN_CHECK_ENABLE_BITS 1 13017 #define PATGEN0_PATGENCTRL_RX_FIXED_PATTERN_CHECK_ENABLE_SHIFT 8 13018 13019 /* PatGen0 :: PatGenCtrl :: testgen_bus_width_rx [07:07] */ 13020 #define PATGEN0_PATGENCTRL_TESTGEN_BUS_WIDTH_RX_MASK 0x0080 13021 #define PATGEN0_PATGENCTRL_TESTGEN_BUS_WIDTH_RX_ALIGN 0 13022 #define PATGEN0_PATGENCTRL_TESTGEN_BUS_WIDTH_RX_BITS 1 13023 #define PATGEN0_PATGENCTRL_TESTGEN_BUS_WIDTH_RX_SHIFT 7 13024 13025 /* PatGen0 :: PatGenCtrl :: testgen_bus_width_tx [06:06] */ 13026 #define PATGEN0_PATGENCTRL_TESTGEN_BUS_WIDTH_TX_MASK 0x0040 13027 #define PATGEN0_PATGENCTRL_TESTGEN_BUS_WIDTH_TX_ALIGN 0 13028 #define PATGEN0_PATGENCTRL_TESTGEN_BUS_WIDTH_TX_BITS 1 13029 #define PATGEN0_PATGENCTRL_TESTGEN_BUS_WIDTH_TX_SHIFT 6 13030 13031 /* PatGen0 :: PatGenCtrl :: clr_rxcnt [05:05] */ 13032 #define PATGEN0_PATGENCTRL_CLR_RXCNT_MASK 0x0020 13033 #define PATGEN0_PATGENCTRL_CLR_RXCNT_ALIGN 0 13034 #define PATGEN0_PATGENCTRL_CLR_RXCNT_BITS 1 13035 #define PATGEN0_PATGENCTRL_CLR_RXCNT_SHIFT 5 13036 13037 /* PatGen0 :: PatGenCtrl :: clr_txcnt [04:04] */ 13038 #define PATGEN0_PATGENCTRL_CLR_TXCNT_MASK 0x0010 13039 #define PATGEN0_PATGENCTRL_CLR_TXCNT_ALIGN 0 13040 #define PATGEN0_PATGENCTRL_CLR_TXCNT_BITS 1 13041 #define PATGEN0_PATGENCTRL_CLR_TXCNT_SHIFT 4 13042 13043 /* PatGen0 :: PatGenCtrl :: patgen_en [03:03] */ 13044 #define PATGEN0_PATGENCTRL_PATGEN_EN_MASK 0x0008 13045 #define PATGEN0_PATGENCTRL_PATGEN_EN_ALIGN 0 13046 #define PATGEN0_PATGENCTRL_PATGEN_EN_BITS 1 13047 #define PATGEN0_PATGENCTRL_PATGEN_EN_SHIFT 3 13048 13049 /* PatGen0 :: PatGenCtrl :: prbs_rx_en [02:02] */ 13050 #define PATGEN0_PATGENCTRL_PRBS_RX_EN_MASK 0x0004 13051 #define PATGEN0_PATGENCTRL_PRBS_RX_EN_ALIGN 0 13052 #define PATGEN0_PATGENCTRL_PRBS_RX_EN_BITS 1 13053 #define PATGEN0_PATGENCTRL_PRBS_RX_EN_SHIFT 2 13054 13055 /* PatGen0 :: PatGenCtrl :: prbs_tx_en [01:01] */ 13056 #define PATGEN0_PATGENCTRL_PRBS_TX_EN_MASK 0x0002 13057 #define PATGEN0_PATGENCTRL_PRBS_TX_EN_ALIGN 0 13058 #define PATGEN0_PATGENCTRL_PRBS_TX_EN_BITS 1 13059 #define PATGEN0_PATGENCTRL_PRBS_TX_EN_SHIFT 1 13060 13061 /* PatGen0 :: PatGenCtrl :: testsource_sel [00:00] */ 13062 #define PATGEN0_PATGENCTRL_TESTSOURCE_SEL_MASK 0x0001 13063 #define PATGEN0_PATGENCTRL_TESTSOURCE_SEL_ALIGN 0 13064 #define PATGEN0_PATGENCTRL_TESTSOURCE_SEL_BITS 1 13065 #define PATGEN0_PATGENCTRL_TESTSOURCE_SEL_SHIFT 0 13066 13067 13068 /**************************************************************************** 13069 * PatGen0 :: PrbsCtrl 13070 */ 13071 /* PatGen0 :: PrbsCtrl :: reserved0 [15:15] */ 13072 #define PATGEN0_PRBSCTRL_RESERVED0_MASK 0x8000 13073 #define PATGEN0_PRBSCTRL_RESERVED0_ALIGN 0 13074 #define PATGEN0_PRBSCTRL_RESERVED0_BITS 1 13075 #define PATGEN0_PRBSCTRL_RESERVED0_SHIFT 15 13076 13077 /* PatGen0 :: PrbsCtrl :: prbs_check_mode [14:12] */ 13078 #define PATGEN0_PRBSCTRL_PRBS_CHECK_MODE_MASK 0x7000 13079 #define PATGEN0_PRBSCTRL_PRBS_CHECK_MODE_ALIGN 0 13080 #define PATGEN0_PRBSCTRL_PRBS_CHECK_MODE_BITS 3 13081 #define PATGEN0_PRBSCTRL_PRBS_CHECK_MODE_SHIFT 12 13082 13083 /* PatGen0 :: PrbsCtrl :: prbs_inv_rx [11:11] */ 13084 #define PATGEN0_PRBSCTRL_PRBS_INV_RX_MASK 0x0800 13085 #define PATGEN0_PRBSCTRL_PRBS_INV_RX_ALIGN 0 13086 #define PATGEN0_PRBSCTRL_PRBS_INV_RX_BITS 1 13087 #define PATGEN0_PRBSCTRL_PRBS_INV_RX_SHIFT 11 13088 13089 /* PatGen0 :: PrbsCtrl :: prbs_sel_rx [10:08] */ 13090 #define PATGEN0_PRBSCTRL_PRBS_SEL_RX_MASK 0x0700 13091 #define PATGEN0_PRBSCTRL_PRBS_SEL_RX_ALIGN 0 13092 #define PATGEN0_PRBSCTRL_PRBS_SEL_RX_BITS 3 13093 #define PATGEN0_PRBSCTRL_PRBS_SEL_RX_SHIFT 8 13094 13095 /* PatGen0 :: PrbsCtrl :: reserved1 [07:05] */ 13096 #define PATGEN0_PRBSCTRL_RESERVED1_MASK 0x00e0 13097 #define PATGEN0_PRBSCTRL_RESERVED1_ALIGN 0 13098 #define PATGEN0_PRBSCTRL_RESERVED1_BITS 3 13099 #define PATGEN0_PRBSCTRL_RESERVED1_SHIFT 5 13100 13101 /* PatGen0 :: PrbsCtrl :: load_prbs_seed [04:04] */ 13102 #define PATGEN0_PRBSCTRL_LOAD_PRBS_SEED_MASK 0x0010 13103 #define PATGEN0_PRBSCTRL_LOAD_PRBS_SEED_ALIGN 0 13104 #define PATGEN0_PRBSCTRL_LOAD_PRBS_SEED_BITS 1 13105 #define PATGEN0_PRBSCTRL_LOAD_PRBS_SEED_SHIFT 4 13106 13107 /* PatGen0 :: PrbsCtrl :: prbs_inv_tx [03:03] */ 13108 #define PATGEN0_PRBSCTRL_PRBS_INV_TX_MASK 0x0008 13109 #define PATGEN0_PRBSCTRL_PRBS_INV_TX_ALIGN 0 13110 #define PATGEN0_PRBSCTRL_PRBS_INV_TX_BITS 1 13111 #define PATGEN0_PRBSCTRL_PRBS_INV_TX_SHIFT 3 13112 13113 /* PatGen0 :: PrbsCtrl :: prbs_sel_tx [02:00] */ 13114 #define PATGEN0_PRBSCTRL_PRBS_SEL_TX_MASK 0x0007 13115 #define PATGEN0_PRBSCTRL_PRBS_SEL_TX_ALIGN 0 13116 #define PATGEN0_PRBSCTRL_PRBS_SEL_TX_BITS 3 13117 #define PATGEN0_PRBSCTRL_PRBS_SEL_TX_SHIFT 0 13118 13119 13120 /**************************************************************************** 13121 * PatGen0 :: PrbsStat0 13122 */ 13123 /* PatGen0 :: PrbsStat0 :: prbs_lock_lost_lh [15:15] */ 13124 #define PATGEN0_PRBSSTAT0_PRBS_LOCK_LOST_LH_MASK 0x8000 13125 #define PATGEN0_PRBSSTAT0_PRBS_LOCK_LOST_LH_ALIGN 0 13126 #define PATGEN0_PRBSSTAT0_PRBS_LOCK_LOST_LH_BITS 1 13127 #define PATGEN0_PRBSSTAT0_PRBS_LOCK_LOST_LH_SHIFT 15 13128 13129 /* PatGen0 :: PrbsStat0 :: prbs_error_HI [14:00] */ 13130 #define PATGEN0_PRBSSTAT0_PRBS_ERROR_HI_MASK 0x7fff 13131 #define PATGEN0_PRBSSTAT0_PRBS_ERROR_HI_ALIGN 0 13132 #define PATGEN0_PRBSSTAT0_PRBS_ERROR_HI_BITS 15 13133 #define PATGEN0_PRBSSTAT0_PRBS_ERROR_HI_SHIFT 0 13134 13135 13136 /**************************************************************************** 13137 * PatGen0 :: PrbsStat1 13138 */ 13139 /* PatGen0 :: PrbsStat1 :: prbs_error_LO [15:00] */ 13140 #define PATGEN0_PRBSSTAT1_PRBS_ERROR_LO_MASK 0xffff 13141 #define PATGEN0_PRBSSTAT1_PRBS_ERROR_LO_ALIGN 0 13142 #define PATGEN0_PRBSSTAT1_PRBS_ERROR_LO_BITS 16 13143 #define PATGEN0_PRBSSTAT1_PRBS_ERROR_LO_SHIFT 0 13144 13145 13146 /**************************************************************************** 13147 * PatGen0 :: TestMiscStatus 13148 */ 13149 /* PatGen0 :: TestMiscStatus :: reserved0 [15:02] */ 13150 #define PATGEN0_TESTMISCSTATUS_RESERVED0_MASK 0xfffc 13151 #define PATGEN0_TESTMISCSTATUS_RESERVED0_ALIGN 0 13152 #define PATGEN0_TESTMISCSTATUS_RESERVED0_BITS 14 13153 #define PATGEN0_TESTMISCSTATUS_RESERVED0_SHIFT 2 13154 13155 /* PatGen0 :: TestMiscStatus :: prbs_lock [01:01] */ 13156 #define PATGEN0_TESTMISCSTATUS_PRBS_LOCK_MASK 0x0002 13157 #define PATGEN0_TESTMISCSTATUS_PRBS_LOCK_ALIGN 0 13158 #define PATGEN0_TESTMISCSTATUS_PRBS_LOCK_BITS 1 13159 #define PATGEN0_TESTMISCSTATUS_PRBS_LOCK_SHIFT 1 13160 13161 /* PatGen0 :: TestMiscStatus :: prtp_lock [00:00] */ 13162 #define PATGEN0_TESTMISCSTATUS_PRTP_LOCK_MASK 0x0001 13163 #define PATGEN0_TESTMISCSTATUS_PRTP_LOCK_ALIGN 0 13164 #define PATGEN0_TESTMISCSTATUS_PRTP_LOCK_BITS 1 13165 #define PATGEN0_TESTMISCSTATUS_PRTP_LOCK_SHIFT 0 13166 13167 13168 /**************************************************************************** 13169 * TSC_WC4_TSC_USER4_PatGen1 13170 */ 13171 /**************************************************************************** 13172 * PatGen1 :: txpktcnt_U 13173 */ 13174 /* PatGen1 :: txpktcnt_U :: txpktcnt_U [15:00] */ 13175 #define PATGEN1_TXPKTCNT_U_TXPKTCNT_U_MASK 0xffff 13176 #define PATGEN1_TXPKTCNT_U_TXPKTCNT_U_ALIGN 0 13177 #define PATGEN1_TXPKTCNT_U_TXPKTCNT_U_BITS 16 13178 #define PATGEN1_TXPKTCNT_U_TXPKTCNT_U_SHIFT 0 13179 13180 13181 /**************************************************************************** 13182 * PatGen1 :: txpktcnt_L 13183 */ 13184 /* PatGen1 :: txpktcnt_L :: txpktcnt_L [15:00] */ 13185 #define PATGEN1_TXPKTCNT_L_TXPKTCNT_L_MASK 0xffff 13186 #define PATGEN1_TXPKTCNT_L_TXPKTCNT_L_ALIGN 0 13187 #define PATGEN1_TXPKTCNT_L_TXPKTCNT_L_BITS 16 13188 #define PATGEN1_TXPKTCNT_L_TXPKTCNT_L_SHIFT 0 13189 13190 13191 /**************************************************************************** 13192 * PatGen1 :: rxpktcnt_U 13193 */ 13194 /* PatGen1 :: rxpktcnt_U :: rxpktcnt_U [15:00] */ 13195 #define PATGEN1_RXPKTCNT_U_RXPKTCNT_U_MASK 0xffff 13196 #define PATGEN1_RXPKTCNT_U_RXPKTCNT_U_ALIGN 0 13197 #define PATGEN1_RXPKTCNT_U_RXPKTCNT_U_BITS 16 13198 #define PATGEN1_RXPKTCNT_U_RXPKTCNT_U_SHIFT 0 13199 13200 13201 /**************************************************************************** 13202 * PatGen1 :: rxpktcnt_L 13203 */ 13204 /* PatGen1 :: rxpktcnt_L :: rxpktcnt_L [15:00] */ 13205 #define PATGEN1_RXPKTCNT_L_RXPKTCNT_L_MASK 0xffff 13206 #define PATGEN1_RXPKTCNT_L_RXPKTCNT_L_ALIGN 0 13207 #define PATGEN1_RXPKTCNT_L_RXPKTCNT_L_BITS 16 13208 #define PATGEN1_RXPKTCNT_L_RXPKTCNT_L_SHIFT 0 13209 13210 13211 /**************************************************************************** 13212 * TSC_WC4_TSC_USER4_TX_X4_Credit0 13213 */ 13214 /**************************************************************************** 13215 * TX_X4_Credit0 :: credit0 13216 */ 13217 /* TX_X4_Credit0 :: credit0 :: sgmii_spd_switch [15:15] */ 13218 #define TX_X4_CREDIT0_CREDIT0_SGMII_SPD_SWITCH_MASK 0x8000 13219 #define TX_X4_CREDIT0_CREDIT0_SGMII_SPD_SWITCH_ALIGN 0 13220 #define TX_X4_CREDIT0_CREDIT0_SGMII_SPD_SWITCH_BITS 1 13221 #define TX_X4_CREDIT0_CREDIT0_SGMII_SPD_SWITCH_SHIFT 15 13222 13223 /* TX_X4_Credit0 :: credit0 :: creditenable [14:14] */ 13224 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_MASK 0x4000 13225 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_ALIGN 0 13226 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_BITS 1 13227 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_SHIFT 14 13228 13229 /* TX_X4_Credit0 :: credit0 :: clockcnt0 [13:00] */ 13230 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_MASK 0x3fff 13231 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_ALIGN 0 13232 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_BITS 14 13233 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_SHIFT 0 13234 13235 13236 /**************************************************************************** 13237 * TX_X4_Credit0 :: credit1 13238 */ 13239 /* TX_X4_Credit0 :: credit1 :: reserved0 [15:08] */ 13240 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_MASK 0xff00 13241 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_ALIGN 0 13242 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_BITS 8 13243 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_SHIFT 8 13244 13245 /* TX_X4_Credit0 :: credit1 :: clockcnt1 [07:00] */ 13246 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_MASK 0x00ff 13247 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_ALIGN 0 13248 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_BITS 8 13249 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_SHIFT 0 13250 13251 13252 /**************************************************************************** 13253 * TX_X4_Credit0 :: loopcnt 13254 */ 13255 /* TX_X4_Credit0 :: loopcnt :: reserved0 [15:14] */ 13256 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_MASK 0xc000 13257 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_ALIGN 0 13258 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_BITS 2 13259 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_SHIFT 14 13260 13261 /* TX_X4_Credit0 :: loopcnt :: loopcnt0 [13:06] */ 13262 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_MASK 0x3fc0 13263 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_ALIGN 0 13264 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_BITS 8 13265 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_SHIFT 6 13266 13267 /* TX_X4_Credit0 :: loopcnt :: loopcnt1 [05:00] */ 13268 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_MASK 0x003f 13269 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_ALIGN 0 13270 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_BITS 6 13271 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_SHIFT 0 13272 13273 13274 /**************************************************************************** 13275 * TX_X4_Credit0 :: mac_creditgencnt 13276 */ 13277 /* TX_X4_Credit0 :: mac_creditgencnt :: reserved0 [15:13] */ 13278 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_MASK 0xe000 13279 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_ALIGN 0 13280 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_BITS 3 13281 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_SHIFT 13 13282 13283 /* TX_X4_Credit0 :: mac_creditgencnt :: mac_creditgencnt [12:00] */ 13284 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_MASK 0x1fff 13285 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_ALIGN 0 13286 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_BITS 13 13287 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_SHIFT 0 13288 13289 13290 /**************************************************************************** 13291 * TX_X4_Credit0 :: pcs_clockcnt0 13292 */ 13293 /* TX_X4_Credit0 :: pcs_clockcnt0 :: replication_cnt [15:15] */ 13294 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_REPLICATION_CNT_MASK 0x8000 13295 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_REPLICATION_CNT_ALIGN 0 13296 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_REPLICATION_CNT_BITS 1 13297 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_REPLICATION_CNT_SHIFT 15 13298 13299 /* TX_X4_Credit0 :: pcs_clockcnt0 :: pcs_creditenable [14:14] */ 13300 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CREDITENABLE_MASK 0x4000 13301 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CREDITENABLE_ALIGN 0 13302 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CREDITENABLE_BITS 1 13303 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CREDITENABLE_SHIFT 14 13304 13305 /* TX_X4_Credit0 :: pcs_clockcnt0 :: pcs_clockcnt0 [13:00] */ 13306 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CLOCKCNT0_MASK 0x3fff 13307 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CLOCKCNT0_ALIGN 0 13308 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CLOCKCNT0_BITS 14 13309 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CLOCKCNT0_SHIFT 0 13310 13311 13312 /**************************************************************************** 13313 * TX_X4_Credit0 :: pcs_creditgencnt 13314 */ 13315 /* TX_X4_Credit0 :: pcs_creditgencnt :: reserved0 [15:13] */ 13316 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_RESERVED0_MASK 0xe000 13317 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_RESERVED0_ALIGN 0 13318 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_RESERVED0_BITS 3 13319 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_RESERVED0_SHIFT 13 13320 13321 /* TX_X4_Credit0 :: pcs_creditgencnt :: pcs_creditgencnt [12:00] */ 13322 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_PCS_CREDITGENCNT_MASK 0x1fff 13323 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_PCS_CREDITGENCNT_ALIGN 0 13324 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_PCS_CREDITGENCNT_BITS 13 13325 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_PCS_CREDITGENCNT_SHIFT 0 13326 13327 13328 /**************************************************************************** 13329 * TSC_WC4_TSC_USER4_TX_X4_Control0 13330 */ 13331 /**************************************************************************** 13332 * TX_X4_Control0 :: kr_default_control 13333 */ 13334 /* TX_X4_Control0 :: kr_default_control :: reserved0 [15:15] */ 13335 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 13336 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_RESERVED0_ALIGN 0 13337 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_RESERVED0_BITS 1 13338 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_RESERVED0_SHIFT 15 13339 13340 /* TX_X4_Control0 :: kr_default_control :: tx_fir_tap_post_kr_init_val [14:10] */ 13341 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_MASK 0x7c00 13342 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_ALIGN 0 13343 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_BITS 5 13344 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_SHIFT 10 13345 13346 /* TX_X4_Control0 :: kr_default_control :: tx_fir_tap_main_kr_init_val [09:04] */ 13347 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_MASK 0x03f0 13348 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_ALIGN 0 13349 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_BITS 6 13350 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_SHIFT 4 13351 13352 /* TX_X4_Control0 :: kr_default_control :: tx_fir_tap_pre_kr_init_val [03:00] */ 13353 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_MASK 0x000f 13354 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_ALIGN 0 13355 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_BITS 4 13356 #define TX_X4_CONTROL0_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_SHIFT 0 13357 13358 13359 /**************************************************************************** 13360 * TX_X4_Control0 :: encode_0 13361 */ 13362 /* TX_X4_Control0 :: encode_0 :: reserved0 [15:13] */ 13363 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_MASK 0xe000 13364 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_ALIGN 0 13365 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_BITS 3 13366 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_SHIFT 13 13367 13368 /* TX_X4_Control0 :: encode_0 :: HG2_CODEC [12:12] */ 13369 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_MASK 0x1000 13370 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_ALIGN 0 13371 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_BITS 1 13372 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_SHIFT 12 13373 13374 /* TX_X4_Control0 :: encode_0 :: HG2_MESSAGE_INVALID_CODE_ENABLE [11:11] */ 13375 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_MASK 0x0800 13376 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_ALIGN 0 13377 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_BITS 1 13378 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_SHIFT 11 13379 13380 /* TX_X4_Control0 :: encode_0 :: HG2_ENABLE [10:10] */ 13381 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_MASK 0x0400 13382 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_ALIGN 0 13383 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_BITS 1 13384 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_SHIFT 10 13385 13386 /* TX_X4_Control0 :: encode_0 :: cl49_bypass_txsm [09:09] */ 13387 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_MASK 0x0200 13388 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_ALIGN 0 13389 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_BITS 1 13390 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_SHIFT 9 13391 13392 /* TX_X4_Control0 :: encode_0 :: reserved1 [08:07] */ 13393 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_MASK 0x0180 13394 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_ALIGN 0 13395 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_BITS 2 13396 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_SHIFT 7 13397 13398 /* TX_X4_Control0 :: encode_0 :: cl49_tx_tl_mode [06:05] */ 13399 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_MASK 0x0060 13400 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_ALIGN 0 13401 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_BITS 2 13402 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_SHIFT 5 13403 13404 /* TX_X4_Control0 :: encode_0 :: encodeMode [04:02] */ 13405 #define TX_X4_CONTROL0_ENCODE_0_ENCODEMODE_MASK 0x001c 13406 #define TX_X4_CONTROL0_ENCODE_0_ENCODEMODE_ALIGN 0 13407 #define TX_X4_CONTROL0_ENCODE_0_ENCODEMODE_BITS 3 13408 #define TX_X4_CONTROL0_ENCODE_0_ENCODEMODE_SHIFT 2 13409 13410 /* TX_X4_Control0 :: encode_0 :: reserved2 [01:00] */ 13411 #define TX_X4_CONTROL0_ENCODE_0_RESERVED2_MASK 0x0003 13412 #define TX_X4_CONTROL0_ENCODE_0_RESERVED2_ALIGN 0 13413 #define TX_X4_CONTROL0_ENCODE_0_RESERVED2_BITS 2 13414 #define TX_X4_CONTROL0_ENCODE_0_RESERVED2_SHIFT 0 13415 13416 13417 /**************************************************************************** 13418 * TX_X4_Control0 :: encode_1 13419 */ 13420 /* TX_X4_Control0 :: encode_1 :: reserved0 [15:10] */ 13421 #define TX_X4_CONTROL0_ENCODE_1_RESERVED0_MASK 0xfc00 13422 #define TX_X4_CONTROL0_ENCODE_1_RESERVED0_ALIGN 0 13423 #define TX_X4_CONTROL0_ENCODE_1_RESERVED0_BITS 6 13424 #define TX_X4_CONTROL0_ENCODE_1_RESERVED0_SHIFT 10 13425 13426 /* TX_X4_Control0 :: encode_1 :: catch_all_8b10b_dis [09:09] */ 13427 #define TX_X4_CONTROL0_ENCODE_1_CATCH_ALL_8B10B_DIS_MASK 0x0200 13428 #define TX_X4_CONTROL0_ENCODE_1_CATCH_ALL_8B10B_DIS_ALIGN 0 13429 #define TX_X4_CONTROL0_ENCODE_1_CATCH_ALL_8B10B_DIS_BITS 1 13430 #define TX_X4_CONTROL0_ENCODE_1_CATCH_ALL_8B10B_DIS_SHIFT 9 13431 13432 /* TX_X4_Control0 :: encode_1 :: prog_tl_en [08:08] */ 13433 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_EN_MASK 0x0100 13434 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_EN_ALIGN 0 13435 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_EN_BITS 1 13436 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_EN_SHIFT 8 13437 13438 /* TX_X4_Control0 :: encode_1 :: prog_tl_char [07:00] */ 13439 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_CHAR_MASK 0x00ff 13440 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_CHAR_ALIGN 0 13441 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_CHAR_BITS 8 13442 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_CHAR_SHIFT 0 13443 13444 13445 /**************************************************************************** 13446 * TX_X4_Control0 :: misc 13447 */ 13448 /* TX_X4_Control0 :: misc :: scr_mode [15:14] */ 13449 #define TX_X4_CONTROL0_MISC_SCR_MODE_MASK 0xc000 13450 #define TX_X4_CONTROL0_MISC_SCR_MODE_ALIGN 0 13451 #define TX_X4_CONTROL0_MISC_SCR_MODE_BITS 2 13452 #define TX_X4_CONTROL0_MISC_SCR_MODE_SHIFT 14 13453 13454 /* TX_X4_Control0 :: misc :: reserved0 [13:11] */ 13455 #define TX_X4_CONTROL0_MISC_RESERVED0_MASK 0x3800 13456 #define TX_X4_CONTROL0_MISC_RESERVED0_ALIGN 0 13457 #define TX_X4_CONTROL0_MISC_RESERVED0_BITS 3 13458 #define TX_X4_CONTROL0_MISC_RESERVED0_SHIFT 11 13459 13460 /* TX_X4_Control0 :: misc :: fec_enable [10:10] */ 13461 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_MASK 0x0400 13462 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_ALIGN 0 13463 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_BITS 1 13464 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_SHIFT 10 13465 13466 /* TX_X4_Control0 :: misc :: reserved1 [09:09] */ 13467 #define TX_X4_CONTROL0_MISC_RESERVED1_MASK 0x0200 13468 #define TX_X4_CONTROL0_MISC_RESERVED1_ALIGN 0 13469 #define TX_X4_CONTROL0_MISC_RESERVED1_BITS 1 13470 #define TX_X4_CONTROL0_MISC_RESERVED1_SHIFT 9 13471 13472 /* TX_X4_Control0 :: misc :: cl49_tx_li_enable [08:08] */ 13473 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_MASK 0x0100 13474 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_ALIGN 0 13475 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_BITS 1 13476 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_SHIFT 8 13477 13478 /* TX_X4_Control0 :: misc :: cl49_tx_lf_enable [07:07] */ 13479 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_MASK 0x0080 13480 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_ALIGN 0 13481 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_BITS 1 13482 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_SHIFT 7 13483 13484 /* TX_X4_Control0 :: misc :: cl49_tx_rf_enable [06:06] */ 13485 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_MASK 0x0040 13486 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_ALIGN 0 13487 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_BITS 1 13488 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_SHIFT 6 13489 13490 /* TX_X4_Control0 :: misc :: reserved2 [05:04] */ 13491 #define TX_X4_CONTROL0_MISC_RESERVED2_MASK 0x0030 13492 #define TX_X4_CONTROL0_MISC_RESERVED2_ALIGN 0 13493 #define TX_X4_CONTROL0_MISC_RESERVED2_BITS 2 13494 #define TX_X4_CONTROL0_MISC_RESERVED2_SHIFT 4 13495 13496 /* TX_X4_Control0 :: misc :: tx_fifo_watermark [03:02] */ 13497 #define TX_X4_CONTROL0_MISC_TX_FIFO_WATERMARK_MASK 0x000c 13498 #define TX_X4_CONTROL0_MISC_TX_FIFO_WATERMARK_ALIGN 0 13499 #define TX_X4_CONTROL0_MISC_TX_FIFO_WATERMARK_BITS 2 13500 #define TX_X4_CONTROL0_MISC_TX_FIFO_WATERMARK_SHIFT 2 13501 13502 /* TX_X4_Control0 :: misc :: rstb_tx_lane [01:01] */ 13503 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_MASK 0x0002 13504 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_ALIGN 0 13505 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_BITS 1 13506 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_SHIFT 1 13507 13508 /* TX_X4_Control0 :: misc :: enable_tx_lane [00:00] */ 13509 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_MASK 0x0001 13510 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_ALIGN 0 13511 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_BITS 1 13512 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_SHIFT 0 13513 13514 13515 /**************************************************************************** 13516 * TX_X4_Control0 :: cl36_tx_0 13517 */ 13518 /* TX_X4_Control0 :: cl36_tx_0 :: reserved0 [15:05] */ 13519 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED0_MASK 0xffe0 13520 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED0_ALIGN 0 13521 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED0_BITS 11 13522 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED0_SHIFT 5 13523 13524 /* TX_X4_Control0 :: cl36_tx_0 :: disable_TRRR_tx [04:04] */ 13525 #define TX_X4_CONTROL0_CL36_TX_0_DISABLE_TRRR_TX_MASK 0x0010 13526 #define TX_X4_CONTROL0_CL36_TX_0_DISABLE_TRRR_TX_ALIGN 0 13527 #define TX_X4_CONTROL0_CL36_TX_0_DISABLE_TRRR_TX_BITS 1 13528 #define TX_X4_CONTROL0_CL36_TX_0_DISABLE_TRRR_TX_SHIFT 4 13529 13530 /* TX_X4_Control0 :: cl36_tx_0 :: reserved1 [03:03] */ 13531 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED1_MASK 0x0008 13532 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED1_ALIGN 0 13533 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED1_BITS 1 13534 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED1_SHIFT 3 13535 13536 /* TX_X4_Control0 :: cl36_tx_0 :: disable_packet_misalign [02:02] */ 13537 #define TX_X4_CONTROL0_CL36_TX_0_DISABLE_PACKET_MISALIGN_MASK 0x0004 13538 #define TX_X4_CONTROL0_CL36_TX_0_DISABLE_PACKET_MISALIGN_ALIGN 0 13539 #define TX_X4_CONTROL0_CL36_TX_0_DISABLE_PACKET_MISALIGN_BITS 1 13540 #define TX_X4_CONTROL0_CL36_TX_0_DISABLE_PACKET_MISALIGN_SHIFT 2 13541 13542 /* TX_X4_Control0 :: cl36_tx_0 :: reserved2 [01:00] */ 13543 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED2_MASK 0x0003 13544 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED2_ALIGN 0 13545 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED2_BITS 2 13546 #define TX_X4_CONTROL0_CL36_TX_0_RESERVED2_SHIFT 0 13547 13548 13549 /**************************************************************************** 13550 * TSC_WC4_TSC_USER4_TX_X4_Status0 13551 */ 13552 /**************************************************************************** 13553 * TX_X4_Status0 :: encode_status_0 13554 */ 13555 /* TX_X4_Status0 :: encode_status_0 :: cl49_t_type_coded [15:12] */ 13556 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_MASK 0xf000 13557 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_ALIGN 0 13558 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_BITS 4 13559 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_SHIFT 12 13560 13561 /* TX_X4_Status0 :: encode_status_0 :: cl49_tx_fault_det [11:11] */ 13562 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TX_FAULT_DET_MASK 0x0800 13563 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TX_FAULT_DET_ALIGN 0 13564 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TX_FAULT_DET_BITS 1 13565 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TX_FAULT_DET_SHIFT 11 13566 13567 /* TX_X4_Status0 :: encode_status_0 :: cl49_ltxsm_state [10:03] */ 13568 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_LTXSM_STATE_MASK 0x07f8 13569 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_LTXSM_STATE_ALIGN 0 13570 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_LTXSM_STATE_BITS 8 13571 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_LTXSM_STATE_SHIFT 3 13572 13573 /* TX_X4_Status0 :: encode_status_0 :: cl49_txsm_state [02:00] */ 13574 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_MASK 0x0007 13575 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_ALIGN 0 13576 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_BITS 3 13577 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_SHIFT 0 13578 13579 13580 /**************************************************************************** 13581 * TX_X4_Status0 :: pcs_status 13582 */ 13583 /* TX_X4_Status0 :: pcs_status :: reserved0 [15:09] */ 13584 #define TX_X4_STATUS0_PCS_STATUS_RESERVED0_MASK 0xfe00 13585 #define TX_X4_STATUS0_PCS_STATUS_RESERVED0_ALIGN 0 13586 #define TX_X4_STATUS0_PCS_STATUS_RESERVED0_BITS 7 13587 #define TX_X4_STATUS0_PCS_STATUS_RESERVED0_SHIFT 9 13588 13589 /* TX_X4_Status0 :: pcs_status :: tx_LOCAL_FAULT [08:08] */ 13590 #define TX_X4_STATUS0_PCS_STATUS_TX_LOCAL_FAULT_MASK 0x0100 13591 #define TX_X4_STATUS0_PCS_STATUS_TX_LOCAL_FAULT_ALIGN 0 13592 #define TX_X4_STATUS0_PCS_STATUS_TX_LOCAL_FAULT_BITS 1 13593 #define TX_X4_STATUS0_PCS_STATUS_TX_LOCAL_FAULT_SHIFT 8 13594 13595 /* TX_X4_Status0 :: pcs_status :: tx_REMOTE_FAULT [07:07] */ 13596 #define TX_X4_STATUS0_PCS_STATUS_TX_REMOTE_FAULT_MASK 0x0080 13597 #define TX_X4_STATUS0_PCS_STATUS_TX_REMOTE_FAULT_ALIGN 0 13598 #define TX_X4_STATUS0_PCS_STATUS_TX_REMOTE_FAULT_BITS 1 13599 #define TX_X4_STATUS0_PCS_STATUS_TX_REMOTE_FAULT_SHIFT 7 13600 13601 /* TX_X4_Status0 :: pcs_status :: tx_LINK_INTERRUPT [06:06] */ 13602 #define TX_X4_STATUS0_PCS_STATUS_TX_LINK_INTERRUPT_MASK 0x0040 13603 #define TX_X4_STATUS0_PCS_STATUS_TX_LINK_INTERRUPT_ALIGN 0 13604 #define TX_X4_STATUS0_PCS_STATUS_TX_LINK_INTERRUPT_BITS 1 13605 #define TX_X4_STATUS0_PCS_STATUS_TX_LINK_INTERRUPT_SHIFT 6 13606 13607 /* TX_X4_Status0 :: pcs_status :: tx_LPI_RECEIVED [05:05] */ 13608 #define TX_X4_STATUS0_PCS_STATUS_TX_LPI_RECEIVED_MASK 0x0020 13609 #define TX_X4_STATUS0_PCS_STATUS_TX_LPI_RECEIVED_ALIGN 0 13610 #define TX_X4_STATUS0_PCS_STATUS_TX_LPI_RECEIVED_BITS 1 13611 #define TX_X4_STATUS0_PCS_STATUS_TX_LPI_RECEIVED_SHIFT 5 13612 13613 /* TX_X4_Status0 :: pcs_status :: LINK_INTERRUPT_LH [04:04] */ 13614 #define TX_X4_STATUS0_PCS_STATUS_LINK_INTERRUPT_LH_MASK 0x0010 13615 #define TX_X4_STATUS0_PCS_STATUS_LINK_INTERRUPT_LH_ALIGN 0 13616 #define TX_X4_STATUS0_PCS_STATUS_LINK_INTERRUPT_LH_BITS 1 13617 #define TX_X4_STATUS0_PCS_STATUS_LINK_INTERRUPT_LH_SHIFT 4 13618 13619 /* TX_X4_Status0 :: pcs_status :: LOCAL_FAULT_LH [03:03] */ 13620 #define TX_X4_STATUS0_PCS_STATUS_LOCAL_FAULT_LH_MASK 0x0008 13621 #define TX_X4_STATUS0_PCS_STATUS_LOCAL_FAULT_LH_ALIGN 0 13622 #define TX_X4_STATUS0_PCS_STATUS_LOCAL_FAULT_LH_BITS 1 13623 #define TX_X4_STATUS0_PCS_STATUS_LOCAL_FAULT_LH_SHIFT 3 13624 13625 /* TX_X4_Status0 :: pcs_status :: REMOTE_FAULT_LH [02:02] */ 13626 #define TX_X4_STATUS0_PCS_STATUS_REMOTE_FAULT_LH_MASK 0x0004 13627 #define TX_X4_STATUS0_PCS_STATUS_REMOTE_FAULT_LH_ALIGN 0 13628 #define TX_X4_STATUS0_PCS_STATUS_REMOTE_FAULT_LH_BITS 1 13629 #define TX_X4_STATUS0_PCS_STATUS_REMOTE_FAULT_LH_SHIFT 2 13630 13631 /* TX_X4_Status0 :: pcs_status :: RESERVED_ORDERED_SET_LH [01:01] */ 13632 #define TX_X4_STATUS0_PCS_STATUS_RESERVED_ORDERED_SET_LH_MASK 0x0002 13633 #define TX_X4_STATUS0_PCS_STATUS_RESERVED_ORDERED_SET_LH_ALIGN 0 13634 #define TX_X4_STATUS0_PCS_STATUS_RESERVED_ORDERED_SET_LH_BITS 1 13635 #define TX_X4_STATUS0_PCS_STATUS_RESERVED_ORDERED_SET_LH_SHIFT 1 13636 13637 /* TX_X4_Status0 :: pcs_status :: LPI_RECEIVED_LH [00:00] */ 13638 #define TX_X4_STATUS0_PCS_STATUS_LPI_RECEIVED_LH_MASK 0x0001 13639 #define TX_X4_STATUS0_PCS_STATUS_LPI_RECEIVED_LH_ALIGN 0 13640 #define TX_X4_STATUS0_PCS_STATUS_LPI_RECEIVED_LH_BITS 1 13641 #define TX_X4_STATUS0_PCS_STATUS_LPI_RECEIVED_LH_SHIFT 0 13642 13643 13644 /**************************************************************************** 13645 * TSC_WC4_TSC_USER4_RX_X4_Control0 13646 */ 13647 /**************************************************************************** 13648 * RX_X4_Control0 :: pcs_control_0 13649 */ 13650 /* RX_X4_Control0 :: pcs_control_0 :: descramblermode [15:14] */ 13651 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCRAMBLERMODE_MASK 0xc000 13652 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCRAMBLERMODE_ALIGN 0 13653 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCRAMBLERMODE_BITS 2 13654 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCRAMBLERMODE_SHIFT 14 13655 13656 /* RX_X4_Control0 :: pcs_control_0 :: decodermode [13:11] */ 13657 #define RX_X4_CONTROL0_PCS_CONTROL_0_DECODERMODE_MASK 0x3800 13658 #define RX_X4_CONTROL0_PCS_CONTROL_0_DECODERMODE_ALIGN 0 13659 #define RX_X4_CONTROL0_PCS_CONTROL_0_DECODERMODE_BITS 3 13660 #define RX_X4_CONTROL0_PCS_CONTROL_0_DECODERMODE_SHIFT 11 13661 13662 /* RX_X4_Control0 :: pcs_control_0 :: deskewmode [10:08] */ 13663 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEWMODE_MASK 0x0700 13664 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEWMODE_ALIGN 0 13665 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEWMODE_BITS 3 13666 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEWMODE_SHIFT 8 13667 13668 /* RX_X4_Control0 :: pcs_control_0 :: desc2_mode [07:05] */ 13669 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESC2_MODE_MASK 0x00e0 13670 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESC2_MODE_ALIGN 0 13671 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESC2_MODE_BITS 3 13672 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESC2_MODE_SHIFT 5 13673 13674 /* RX_X4_Control0 :: pcs_control_0 :: CL36ByteDeleteMode [04:03] */ 13675 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL36BYTEDELETEMODE_MASK 0x0018 13676 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL36BYTEDELETEMODE_ALIGN 0 13677 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL36BYTEDELETEMODE_BITS 2 13678 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL36BYTEDELETEMODE_SHIFT 3 13679 13680 /* RX_X4_Control0 :: pcs_control_0 :: LPI_ENABLE [02:02] */ 13681 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_MASK 0x0004 13682 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_ALIGN 0 13683 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_BITS 1 13684 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_SHIFT 2 13685 13686 /* RX_X4_Control0 :: pcs_control_0 :: brcm64b66_descrambler_enable [01:01] */ 13687 #define RX_X4_CONTROL0_PCS_CONTROL_0_BRCM64B66_DESCRAMBLER_ENABLE_MASK 0x0002 13688 #define RX_X4_CONTROL0_PCS_CONTROL_0_BRCM64B66_DESCRAMBLER_ENABLE_ALIGN 0 13689 #define RX_X4_CONTROL0_PCS_CONTROL_0_BRCM64B66_DESCRAMBLER_ENABLE_BITS 1 13690 #define RX_X4_CONTROL0_PCS_CONTROL_0_BRCM64B66_DESCRAMBLER_ENABLE_SHIFT 1 13691 13692 /* RX_X4_Control0 :: pcs_control_0 :: reserved0 [00:00] */ 13693 #define RX_X4_CONTROL0_PCS_CONTROL_0_RESERVED0_MASK 0x0001 13694 #define RX_X4_CONTROL0_PCS_CONTROL_0_RESERVED0_ALIGN 0 13695 #define RX_X4_CONTROL0_PCS_CONTROL_0_RESERVED0_BITS 1 13696 #define RX_X4_CONTROL0_PCS_CONTROL_0_RESERVED0_SHIFT 0 13697 13698 13699 /**************************************************************************** 13700 * RX_X4_Control0 :: fec_0 13701 */ 13702 /* RX_X4_Control0 :: fec_0 :: block_sync_override [15:15] */ 13703 #define RX_X4_CONTROL0_FEC_0_BLOCK_SYNC_OVERRIDE_MASK 0x8000 13704 #define RX_X4_CONTROL0_FEC_0_BLOCK_SYNC_OVERRIDE_ALIGN 0 13705 #define RX_X4_CONTROL0_FEC_0_BLOCK_SYNC_OVERRIDE_BITS 1 13706 #define RX_X4_CONTROL0_FEC_0_BLOCK_SYNC_OVERRIDE_SHIFT 15 13707 13708 /* RX_X4_Control0 :: fec_0 :: reserved0 [14:14] */ 13709 #define RX_X4_CONTROL0_FEC_0_RESERVED0_MASK 0x4000 13710 #define RX_X4_CONTROL0_FEC_0_RESERVED0_ALIGN 0 13711 #define RX_X4_CONTROL0_FEC_0_RESERVED0_BITS 1 13712 #define RX_X4_CONTROL0_FEC_0_RESERVED0_SHIFT 14 13713 13714 /* RX_X4_Control0 :: fec_0 :: fec_err_enable [13:13] */ 13715 #define RX_X4_CONTROL0_FEC_0_FEC_ERR_ENABLE_MASK 0x2000 13716 #define RX_X4_CONTROL0_FEC_0_FEC_ERR_ENABLE_ALIGN 0 13717 #define RX_X4_CONTROL0_FEC_0_FEC_ERR_ENABLE_BITS 1 13718 #define RX_X4_CONTROL0_FEC_0_FEC_ERR_ENABLE_SHIFT 13 13719 13720 /* RX_X4_Control0 :: fec_0 :: error_en_ovr [12:12] */ 13721 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_MASK 0x1000 13722 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_ALIGN 0 13723 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_BITS 1 13724 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_SHIFT 12 13725 13726 /* RX_X4_Control0 :: fec_0 :: error_en_ovr_val [11:11] */ 13727 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_VAL_MASK 0x0800 13728 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_VAL_ALIGN 0 13729 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_VAL_BITS 1 13730 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_VAL_SHIFT 11 13731 13732 /* RX_X4_Control0 :: fec_0 :: dbg_enable [10:10] */ 13733 #define RX_X4_CONTROL0_FEC_0_DBG_ENABLE_MASK 0x0400 13734 #define RX_X4_CONTROL0_FEC_0_DBG_ENABLE_ALIGN 0 13735 #define RX_X4_CONTROL0_FEC_0_DBG_ENABLE_BITS 1 13736 #define RX_X4_CONTROL0_FEC_0_DBG_ENABLE_SHIFT 10 13737 13738 /* RX_X4_Control0 :: fec_0 :: fast_lock_en [09:09] */ 13739 #define RX_X4_CONTROL0_FEC_0_FAST_LOCK_EN_MASK 0x0200 13740 #define RX_X4_CONTROL0_FEC_0_FAST_LOCK_EN_ALIGN 0 13741 #define RX_X4_CONTROL0_FEC_0_FAST_LOCK_EN_BITS 1 13742 #define RX_X4_CONTROL0_FEC_0_FAST_LOCK_EN_SHIFT 9 13743 13744 /* RX_X4_Control0 :: fec_0 :: reserved1 [08:00] */ 13745 #define RX_X4_CONTROL0_FEC_0_RESERVED1_MASK 0x01ff 13746 #define RX_X4_CONTROL0_FEC_0_RESERVED1_ALIGN 0 13747 #define RX_X4_CONTROL0_FEC_0_RESERVED1_BITS 9 13748 #define RX_X4_CONTROL0_FEC_0_RESERVED1_SHIFT 0 13749 13750 13751 /**************************************************************************** 13752 * RX_X4_Control0 :: fec_1 13753 */ 13754 /* RX_X4_Control0 :: fec_1 :: fec_error_code_all [15:15] */ 13755 #define RX_X4_CONTROL0_FEC_1_FEC_ERROR_CODE_ALL_MASK 0x8000 13756 #define RX_X4_CONTROL0_FEC_1_FEC_ERROR_CODE_ALL_ALIGN 0 13757 #define RX_X4_CONTROL0_FEC_1_FEC_ERROR_CODE_ALL_BITS 1 13758 #define RX_X4_CONTROL0_FEC_1_FEC_ERROR_CODE_ALL_SHIFT 15 13759 13760 /* RX_X4_Control0 :: fec_1 :: good_parity_cnt [14:12] */ 13761 #define RX_X4_CONTROL0_FEC_1_GOOD_PARITY_CNT_MASK 0x7000 13762 #define RX_X4_CONTROL0_FEC_1_GOOD_PARITY_CNT_ALIGN 0 13763 #define RX_X4_CONTROL0_FEC_1_GOOD_PARITY_CNT_BITS 3 13764 #define RX_X4_CONTROL0_FEC_1_GOOD_PARITY_CNT_SHIFT 12 13765 13766 /* RX_X4_Control0 :: fec_1 :: invalid_parity_cnt [11:08] */ 13767 #define RX_X4_CONTROL0_FEC_1_INVALID_PARITY_CNT_MASK 0x0f00 13768 #define RX_X4_CONTROL0_FEC_1_INVALID_PARITY_CNT_ALIGN 0 13769 #define RX_X4_CONTROL0_FEC_1_INVALID_PARITY_CNT_BITS 4 13770 #define RX_X4_CONTROL0_FEC_1_INVALID_PARITY_CNT_SHIFT 8 13771 13772 /* RX_X4_Control0 :: fec_1 :: dec_max_pm [07:02] */ 13773 #define RX_X4_CONTROL0_FEC_1_DEC_MAX_PM_MASK 0x00fc 13774 #define RX_X4_CONTROL0_FEC_1_DEC_MAX_PM_ALIGN 0 13775 #define RX_X4_CONTROL0_FEC_1_DEC_MAX_PM_BITS 6 13776 #define RX_X4_CONTROL0_FEC_1_DEC_MAX_PM_SHIFT 2 13777 13778 /* RX_X4_Control0 :: fec_1 :: burst_err_status_mode [01:01] */ 13779 #define RX_X4_CONTROL0_FEC_1_BURST_ERR_STATUS_MODE_MASK 0x0002 13780 #define RX_X4_CONTROL0_FEC_1_BURST_ERR_STATUS_MODE_ALIGN 0 13781 #define RX_X4_CONTROL0_FEC_1_BURST_ERR_STATUS_MODE_BITS 1 13782 #define RX_X4_CONTROL0_FEC_1_BURST_ERR_STATUS_MODE_SHIFT 1 13783 13784 /* RX_X4_Control0 :: fec_1 :: dbg_err_mode [00:00] */ 13785 #define RX_X4_CONTROL0_FEC_1_DBG_ERR_MODE_MASK 0x0001 13786 #define RX_X4_CONTROL0_FEC_1_DBG_ERR_MODE_ALIGN 0 13787 #define RX_X4_CONTROL0_FEC_1_DBG_ERR_MODE_BITS 1 13788 #define RX_X4_CONTROL0_FEC_1_DBG_ERR_MODE_SHIFT 0 13789 13790 13791 /**************************************************************************** 13792 * RX_X4_Control0 :: fec_2 13793 */ 13794 /* RX_X4_Control0 :: fec_2 :: dec_pm_mode [15:11] */ 13795 #define RX_X4_CONTROL0_FEC_2_DEC_PM_MODE_MASK 0xf800 13796 #define RX_X4_CONTROL0_FEC_2_DEC_PM_MODE_ALIGN 0 13797 #define RX_X4_CONTROL0_FEC_2_DEC_PM_MODE_BITS 5 13798 #define RX_X4_CONTROL0_FEC_2_DEC_PM_MODE_SHIFT 11 13799 13800 /* RX_X4_Control0 :: fec_2 :: dec_19b_burst_gap_count [10:08] */ 13801 #define RX_X4_CONTROL0_FEC_2_DEC_19B_BURST_GAP_COUNT_MASK 0x0700 13802 #define RX_X4_CONTROL0_FEC_2_DEC_19B_BURST_GAP_COUNT_ALIGN 0 13803 #define RX_X4_CONTROL0_FEC_2_DEC_19B_BURST_GAP_COUNT_BITS 3 13804 #define RX_X4_CONTROL0_FEC_2_DEC_19B_BURST_GAP_COUNT_SHIFT 8 13805 13806 /* RX_X4_Control0 :: fec_2 :: dec_18b_burst_gap_count [07:05] */ 13807 #define RX_X4_CONTROL0_FEC_2_DEC_18B_BURST_GAP_COUNT_MASK 0x00e0 13808 #define RX_X4_CONTROL0_FEC_2_DEC_18B_BURST_GAP_COUNT_ALIGN 0 13809 #define RX_X4_CONTROL0_FEC_2_DEC_18B_BURST_GAP_COUNT_BITS 3 13810 #define RX_X4_CONTROL0_FEC_2_DEC_18B_BURST_GAP_COUNT_SHIFT 5 13811 13812 /* RX_X4_Control0 :: fec_2 :: dec_17b_burst_gap_count [04:02] */ 13813 #define RX_X4_CONTROL0_FEC_2_DEC_17B_BURST_GAP_COUNT_MASK 0x001c 13814 #define RX_X4_CONTROL0_FEC_2_DEC_17B_BURST_GAP_COUNT_ALIGN 0 13815 #define RX_X4_CONTROL0_FEC_2_DEC_17B_BURST_GAP_COUNT_BITS 3 13816 #define RX_X4_CONTROL0_FEC_2_DEC_17B_BURST_GAP_COUNT_SHIFT 2 13817 13818 /* RX_X4_Control0 :: fec_2 :: dec_gap_count_mode [01:01] */ 13819 #define RX_X4_CONTROL0_FEC_2_DEC_GAP_COUNT_MODE_MASK 0x0002 13820 #define RX_X4_CONTROL0_FEC_2_DEC_GAP_COUNT_MODE_ALIGN 0 13821 #define RX_X4_CONTROL0_FEC_2_DEC_GAP_COUNT_MODE_BITS 1 13822 #define RX_X4_CONTROL0_FEC_2_DEC_GAP_COUNT_MODE_SHIFT 1 13823 13824 /* RX_X4_Control0 :: fec_2 :: reserved0 [00:00] */ 13825 #define RX_X4_CONTROL0_FEC_2_RESERVED0_MASK 0x0001 13826 #define RX_X4_CONTROL0_FEC_2_RESERVED0_ALIGN 0 13827 #define RX_X4_CONTROL0_FEC_2_RESERVED0_BITS 1 13828 #define RX_X4_CONTROL0_FEC_2_RESERVED0_SHIFT 0 13829 13830 13831 /**************************************************************************** 13832 * RX_X4_Control0 :: decode_control_0 13833 */ 13834 /* RX_X4_Control0 :: decode_control_0 :: bypass_cl49rxsm [15:15] */ 13835 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_MASK 0x8000 13836 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_ALIGN 0 13837 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_BITS 1 13838 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_SHIFT 15 13839 13840 /* RX_X4_Control0 :: decode_control_0 :: r_test_mode_cfg [14:14] */ 13841 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_MASK 0x4000 13842 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_ALIGN 0 13843 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_BITS 1 13844 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_SHIFT 14 13845 13846 /* RX_X4_Control0 :: decode_control_0 :: HG2_MESSAGE_INVALID_CODE_ENABLE [13:13] */ 13847 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_MASK 0x2000 13848 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_ALIGN 0 13849 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_BITS 1 13850 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_SHIFT 13 13851 13852 /* RX_X4_Control0 :: decode_control_0 :: HG2_ENABLE [12:12] */ 13853 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_MASK 0x1000 13854 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_ALIGN 0 13855 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_BITS 1 13856 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_SHIFT 12 13857 13858 /* RX_X4_Control0 :: decode_control_0 :: cl48_syncacq_en [11:11] */ 13859 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_SYNCACQ_EN_MASK 0x0800 13860 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_SYNCACQ_EN_ALIGN 0 13861 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_SYNCACQ_EN_BITS 1 13862 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_SYNCACQ_EN_SHIFT 11 13863 13864 /* RX_X4_Control0 :: decode_control_0 :: cl48_cgbad_en [10:10] */ 13865 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_CGBAD_EN_MASK 0x0400 13866 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_CGBAD_EN_ALIGN 0 13867 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_CGBAD_EN_BITS 1 13868 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_CGBAD_EN_SHIFT 10 13869 13870 /* RX_X4_Control0 :: decode_control_0 :: HG2_CODEC [09:09] */ 13871 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_MASK 0x0200 13872 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_ALIGN 0 13873 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_BITS 1 13874 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_SHIFT 9 13875 13876 /* RX_X4_Control0 :: decode_control_0 :: disable_cl49_bermon [08:08] */ 13877 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_MASK 0x0100 13878 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_ALIGN 0 13879 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_BITS 1 13880 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_SHIFT 8 13881 13882 /* RX_X4_Control0 :: decode_control_0 :: reserved0 [07:07] */ 13883 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_MASK 0x0080 13884 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_ALIGN 0 13885 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_BITS 1 13886 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_SHIFT 7 13887 13888 /* RX_X4_Control0 :: decode_control_0 :: cl49_rx_li_enable [06:06] */ 13889 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_MASK 0x0040 13890 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_ALIGN 0 13891 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_BITS 1 13892 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_SHIFT 6 13893 13894 /* RX_X4_Control0 :: decode_control_0 :: cl49_rx_lf_enable [05:05] */ 13895 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_MASK 0x0020 13896 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_ALIGN 0 13897 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_BITS 1 13898 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_SHIFT 5 13899 13900 /* RX_X4_Control0 :: decode_control_0 :: cl49_rx_rf_enable [04:04] */ 13901 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_MASK 0x0010 13902 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_ALIGN 0 13903 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_BITS 1 13904 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_SHIFT 4 13905 13906 /* RX_X4_Control0 :: decode_control_0 :: reserved1 [03:03] */ 13907 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_MASK 0x0008 13908 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_ALIGN 0 13909 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_BITS 1 13910 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_SHIFT 3 13911 13912 /* RX_X4_Control0 :: decode_control_0 :: block_sync_mode [02:00] */ 13913 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BLOCK_SYNC_MODE_MASK 0x0007 13914 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BLOCK_SYNC_MODE_ALIGN 0 13915 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BLOCK_SYNC_MODE_BITS 3 13916 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BLOCK_SYNC_MODE_SHIFT 0 13917 13918 13919 /**************************************************************************** 13920 * RX_X4_Control0 :: decode_control_1 13921 */ 13922 /* RX_X4_Control0 :: decode_control_1 :: b66dec_dout_errors_if_bad_sync [15:15] */ 13923 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_DOUT_ERRORS_IF_BAD_SYNC_MASK 0x8000 13924 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_DOUT_ERRORS_IF_BAD_SYNC_ALIGN 0 13925 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_DOUT_ERRORS_IF_BAD_SYNC_BITS 1 13926 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_DOUT_ERRORS_IF_BAD_SYNC_SHIFT 15 13927 13928 /* RX_X4_Control0 :: decode_control_1 :: b66dec_noblocklock_dout_sel [14:13] */ 13929 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_NOBLOCKLOCK_DOUT_SEL_MASK 0x6000 13930 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_NOBLOCKLOCK_DOUT_SEL_ALIGN 0 13931 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_NOBLOCKLOCK_DOUT_SEL_BITS 2 13932 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_NOBLOCKLOCK_DOUT_SEL_SHIFT 13 13933 13934 /* RX_X4_Control0 :: decode_control_1 :: b66dec_prog_tl_en [12:12] */ 13935 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_EN_MASK 0x1000 13936 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_EN_ALIGN 0 13937 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_EN_BITS 1 13938 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_EN_SHIFT 12 13939 13940 /* RX_X4_Control0 :: decode_control_1 :: b66dec_prog_tl_char [11:04] */ 13941 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_CHAR_MASK 0x0ff0 13942 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_CHAR_ALIGN 0 13943 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_CHAR_BITS 8 13944 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_CHAR_SHIFT 4 13945 13946 /* RX_X4_Control0 :: decode_control_1 :: b66dec_fault_det_en [03:03] */ 13947 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_FAULT_DET_EN_MASK 0x0008 13948 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_FAULT_DET_EN_ALIGN 0 13949 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_FAULT_DET_EN_BITS 1 13950 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_FAULT_DET_EN_SHIFT 3 13951 13952 /* RX_X4_Control0 :: decode_control_1 :: b66dec_kcode66ErrCount_en [02:02] */ 13953 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_KCODE66ERRCOUNT_EN_MASK 0x0004 13954 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_KCODE66ERRCOUNT_EN_ALIGN 0 13955 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_KCODE66ERRCOUNT_EN_BITS 1 13956 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_KCODE66ERRCOUNT_EN_SHIFT 2 13957 13958 /* RX_X4_Control0 :: decode_control_1 :: b66dec_syncErrCount_en [01:01] */ 13959 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_SYNCERRCOUNT_EN_MASK 0x0002 13960 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_SYNCERRCOUNT_EN_ALIGN 0 13961 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_SYNCERRCOUNT_EN_BITS 1 13962 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_SYNCERRCOUNT_EN_SHIFT 1 13963 13964 /* RX_X4_Control0 :: decode_control_1 :: b66dec_cgbad_en [00:00] */ 13965 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_CGBAD_EN_MASK 0x0001 13966 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_CGBAD_EN_ALIGN 0 13967 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_CGBAD_EN_BITS 1 13968 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_CGBAD_EN_SHIFT 0 13969 13970 13971 /**************************************************************************** 13972 * RX_X4_Control0 :: cl36_rx_0 13973 */ 13974 /* RX_X4_Control0 :: cl36_rx_0 :: reserved0 [15:06] */ 13975 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED0_MASK 0xffc0 13976 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED0_ALIGN 0 13977 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED0_BITS 10 13978 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED0_SHIFT 6 13979 13980 /* RX_X4_Control0 :: cl36_rx_0 :: cl36_BER_en [05:05] */ 13981 #define RX_X4_CONTROL0_CL36_RX_0_CL36_BER_EN_MASK 0x0020 13982 #define RX_X4_CONTROL0_CL36_RX_0_CL36_BER_EN_ALIGN 0 13983 #define RX_X4_CONTROL0_CL36_RX_0_CL36_BER_EN_BITS 1 13984 #define RX_X4_CONTROL0_CL36_RX_0_CL36_BER_EN_SHIFT 5 13985 13986 /* RX_X4_Control0 :: cl36_rx_0 :: reserved1 [04:04] */ 13987 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED1_MASK 0x0010 13988 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED1_ALIGN 0 13989 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED1_BITS 1 13990 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED1_SHIFT 4 13991 13992 /* RX_X4_Control0 :: cl36_rx_0 :: cl36_force_comma_align_enable [03:03] */ 13993 #define RX_X4_CONTROL0_CL36_RX_0_CL36_FORCE_COMMA_ALIGN_ENABLE_MASK 0x0008 13994 #define RX_X4_CONTROL0_CL36_RX_0_CL36_FORCE_COMMA_ALIGN_ENABLE_ALIGN 0 13995 #define RX_X4_CONTROL0_CL36_RX_0_CL36_FORCE_COMMA_ALIGN_ENABLE_BITS 1 13996 #define RX_X4_CONTROL0_CL36_RX_0_CL36_FORCE_COMMA_ALIGN_ENABLE_SHIFT 3 13997 13998 /* RX_X4_Control0 :: cl36_rx_0 :: disable_carrier_extend [02:02] */ 13999 #define RX_X4_CONTROL0_CL36_RX_0_DISABLE_CARRIER_EXTEND_MASK 0x0004 14000 #define RX_X4_CONTROL0_CL36_RX_0_DISABLE_CARRIER_EXTEND_ALIGN 0 14001 #define RX_X4_CONTROL0_CL36_RX_0_DISABLE_CARRIER_EXTEND_BITS 1 14002 #define RX_X4_CONTROL0_CL36_RX_0_DISABLE_CARRIER_EXTEND_SHIFT 2 14003 14004 /* RX_X4_Control0 :: cl36_rx_0 :: reorder_en [01:01] */ 14005 #define RX_X4_CONTROL0_CL36_RX_0_REORDER_EN_MASK 0x0002 14006 #define RX_X4_CONTROL0_CL36_RX_0_REORDER_EN_ALIGN 0 14007 #define RX_X4_CONTROL0_CL36_RX_0_REORDER_EN_BITS 1 14008 #define RX_X4_CONTROL0_CL36_RX_0_REORDER_EN_SHIFT 1 14009 14010 /* RX_X4_Control0 :: cl36_rx_0 :: cl36_en [00:00] */ 14011 #define RX_X4_CONTROL0_CL36_RX_0_CL36_EN_MASK 0x0001 14012 #define RX_X4_CONTROL0_CL36_RX_0_CL36_EN_ALIGN 0 14013 #define RX_X4_CONTROL0_CL36_RX_0_CL36_EN_BITS 1 14014 #define RX_X4_CONTROL0_CL36_RX_0_CL36_EN_SHIFT 0 14015 14016 14017 /**************************************************************************** 14018 * RX_X4_Control0 :: pma_control_0 14019 */ 14020 /* RX_X4_Control0 :: pma_control_0 :: reserved0 [15:08] */ 14021 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_MASK 0xff00 14022 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_ALIGN 0 14023 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_BITS 8 14024 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_SHIFT 8 14025 14026 /* RX_X4_Control0 :: pma_control_0 :: override_os_mode [07:07] */ 14027 #define RX_X4_CONTROL0_PMA_CONTROL_0_OVERRIDE_OS_MODE_MASK 0x0080 14028 #define RX_X4_CONTROL0_PMA_CONTROL_0_OVERRIDE_OS_MODE_ALIGN 0 14029 #define RX_X4_CONTROL0_PMA_CONTROL_0_OVERRIDE_OS_MODE_BITS 1 14030 #define RX_X4_CONTROL0_PMA_CONTROL_0_OVERRIDE_OS_MODE_SHIFT 7 14031 14032 /* RX_X4_Control0 :: pma_control_0 :: os_mode [06:03] */ 14033 #define RX_X4_CONTROL0_PMA_CONTROL_0_OS_MODE_MASK 0x0078 14034 #define RX_X4_CONTROL0_PMA_CONTROL_0_OS_MODE_ALIGN 0 14035 #define RX_X4_CONTROL0_PMA_CONTROL_0_OS_MODE_BITS 4 14036 #define RX_X4_CONTROL0_PMA_CONTROL_0_OS_MODE_SHIFT 3 14037 14038 /* RX_X4_Control0 :: pma_control_0 :: reserved1 [02:02] */ 14039 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED1_MASK 0x0004 14040 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED1_ALIGN 0 14041 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED1_BITS 1 14042 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED1_SHIFT 2 14043 14044 /* RX_X4_Control0 :: pma_control_0 :: rx_gbox_afrst_en [01:01] */ 14045 #define RX_X4_CONTROL0_PMA_CONTROL_0_RX_GBOX_AFRST_EN_MASK 0x0002 14046 #define RX_X4_CONTROL0_PMA_CONTROL_0_RX_GBOX_AFRST_EN_ALIGN 0 14047 #define RX_X4_CONTROL0_PMA_CONTROL_0_RX_GBOX_AFRST_EN_BITS 1 14048 #define RX_X4_CONTROL0_PMA_CONTROL_0_RX_GBOX_AFRST_EN_SHIFT 1 14049 14050 /* RX_X4_Control0 :: pma_control_0 :: rstb_lane [00:00] */ 14051 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_MASK 0x0001 14052 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_ALIGN 0 14053 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_BITS 1 14054 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_SHIFT 0 14055 14056 14057 /**************************************************************************** 14058 * RX_X4_Control0 :: Rx_Sigdet 14059 */ 14060 /* RX_X4_Control0 :: Rx_Sigdet :: reserved0 [15:10] */ 14061 #define RX_X4_CONTROL0_RX_SIGDET_RESERVED0_MASK 0xfc00 14062 #define RX_X4_CONTROL0_RX_SIGDET_RESERVED0_ALIGN 0 14063 #define RX_X4_CONTROL0_RX_SIGDET_RESERVED0_BITS 6 14064 #define RX_X4_CONTROL0_RX_SIGDET_RESERVED0_SHIFT 10 14065 14066 /* RX_X4_Control0 :: Rx_Sigdet :: Enable_EXT_Signal_detect_Filtering [09:09] */ 14067 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_EXT_SIGNAL_DETECT_FILTERING_MASK 0x0200 14068 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_EXT_SIGNAL_DETECT_FILTERING_ALIGN 0 14069 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_EXT_SIGNAL_DETECT_FILTERING_BITS 1 14070 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_EXT_SIGNAL_DETECT_FILTERING_SHIFT 9 14071 14072 /* RX_X4_Control0 :: Rx_Sigdet :: Use_cx4_signal_detect_filter_sel [08:08] */ 14073 #define RX_X4_CONTROL0_RX_SIGDET_USE_CX4_SIGNAL_DETECT_FILTER_SEL_MASK 0x0100 14074 #define RX_X4_CONTROL0_RX_SIGDET_USE_CX4_SIGNAL_DETECT_FILTER_SEL_ALIGN 0 14075 #define RX_X4_CONTROL0_RX_SIGDET_USE_CX4_SIGNAL_DETECT_FILTER_SEL_BITS 1 14076 #define RX_X4_CONTROL0_RX_SIGDET_USE_CX4_SIGNAL_DETECT_FILTER_SEL_SHIFT 8 14077 14078 /* RX_X4_Control0 :: Rx_Sigdet :: Enable_AN_signal_detect_filter_sel [07:07] */ 14079 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_AN_SIGNAL_DETECT_FILTER_SEL_MASK 0x0080 14080 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_AN_SIGNAL_DETECT_FILTER_SEL_ALIGN 0 14081 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_AN_SIGNAL_DETECT_FILTER_SEL_BITS 1 14082 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_AN_SIGNAL_DETECT_FILTER_SEL_SHIFT 7 14083 14084 /* RX_X4_Control0 :: Rx_Sigdet :: External_Signal_detect_invert [06:06] */ 14085 #define RX_X4_CONTROL0_RX_SIGDET_EXTERNAL_SIGNAL_DETECT_INVERT_MASK 0x0040 14086 #define RX_X4_CONTROL0_RX_SIGDET_EXTERNAL_SIGNAL_DETECT_INVERT_ALIGN 0 14087 #define RX_X4_CONTROL0_RX_SIGDET_EXTERNAL_SIGNAL_DETECT_INVERT_BITS 1 14088 #define RX_X4_CONTROL0_RX_SIGDET_EXTERNAL_SIGNAL_DETECT_INVERT_SHIFT 6 14089 14090 /* RX_X4_Control0 :: Rx_Sigdet :: AFE_Signal_detect_invert [05:05] */ 14091 #define RX_X4_CONTROL0_RX_SIGDET_AFE_SIGNAL_DETECT_INVERT_MASK 0x0020 14092 #define RX_X4_CONTROL0_RX_SIGDET_AFE_SIGNAL_DETECT_INVERT_ALIGN 0 14093 #define RX_X4_CONTROL0_RX_SIGDET_AFE_SIGNAL_DETECT_INVERT_BITS 1 14094 #define RX_X4_CONTROL0_RX_SIGDET_AFE_SIGNAL_DETECT_INVERT_SHIFT 5 14095 14096 /* RX_X4_Control0 :: Rx_Sigdet :: External_Signal_detect_enable [04:04] */ 14097 #define RX_X4_CONTROL0_RX_SIGDET_EXTERNAL_SIGNAL_DETECT_ENABLE_MASK 0x0010 14098 #define RX_X4_CONTROL0_RX_SIGDET_EXTERNAL_SIGNAL_DETECT_ENABLE_ALIGN 0 14099 #define RX_X4_CONTROL0_RX_SIGDET_EXTERNAL_SIGNAL_DETECT_ENABLE_BITS 1 14100 #define RX_X4_CONTROL0_RX_SIGDET_EXTERNAL_SIGNAL_DETECT_ENABLE_SHIFT 4 14101 14102 /* RX_X4_Control0 :: Rx_Sigdet :: AFE_Signal_detect_enable [03:03] */ 14103 #define RX_X4_CONTROL0_RX_SIGDET_AFE_SIGNAL_DETECT_ENABLE_MASK 0x0008 14104 #define RX_X4_CONTROL0_RX_SIGDET_AFE_SIGNAL_DETECT_ENABLE_ALIGN 0 14105 #define RX_X4_CONTROL0_RX_SIGDET_AFE_SIGNAL_DETECT_ENABLE_BITS 1 14106 #define RX_X4_CONTROL0_RX_SIGDET_AFE_SIGNAL_DETECT_ENABLE_SHIFT 3 14107 14108 /* RX_X4_Control0 :: Rx_Sigdet :: Override_signal_ok [02:02] */ 14109 #define RX_X4_CONTROL0_RX_SIGDET_OVERRIDE_SIGNAL_OK_MASK 0x0004 14110 #define RX_X4_CONTROL0_RX_SIGDET_OVERRIDE_SIGNAL_OK_ALIGN 0 14111 #define RX_X4_CONTROL0_RX_SIGDET_OVERRIDE_SIGNAL_OK_BITS 1 14112 #define RX_X4_CONTROL0_RX_SIGDET_OVERRIDE_SIGNAL_OK_SHIFT 2 14113 14114 /* RX_X4_Control0 :: Rx_Sigdet :: Override_value_signal_ok [01:01] */ 14115 #define RX_X4_CONTROL0_RX_SIGDET_OVERRIDE_VALUE_SIGNAL_OK_MASK 0x0002 14116 #define RX_X4_CONTROL0_RX_SIGDET_OVERRIDE_VALUE_SIGNAL_OK_ALIGN 0 14117 #define RX_X4_CONTROL0_RX_SIGDET_OVERRIDE_VALUE_SIGNAL_OK_BITS 1 14118 #define RX_X4_CONTROL0_RX_SIGDET_OVERRIDE_VALUE_SIGNAL_OK_SHIFT 1 14119 14120 /* RX_X4_Control0 :: Rx_Sigdet :: Enable_AFE_Signal_detect_Filtering [00:00] */ 14121 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_AFE_SIGNAL_DETECT_FILTERING_MASK 0x0001 14122 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_AFE_SIGNAL_DETECT_FILTERING_ALIGN 0 14123 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_AFE_SIGNAL_DETECT_FILTERING_BITS 1 14124 #define RX_X4_CONTROL0_RX_SIGDET_ENABLE_AFE_SIGNAL_DETECT_FILTERING_SHIFT 0 14125 14126 14127 /**************************************************************************** 14128 * RX_X4_Control0 :: link_control 14129 */ 14130 /* RX_X4_Control0 :: link_control :: reserved0 [15:01] */ 14131 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_MASK 0xfffe 14132 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_ALIGN 0 14133 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_BITS 15 14134 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_SHIFT 1 14135 14136 /* RX_X4_Control0 :: link_control :: latch_linkdown_enable [00:00] */ 14137 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_MASK 0x0001 14138 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_ALIGN 0 14139 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_BITS 1 14140 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_SHIFT 0 14141 14142 14143 /**************************************************************************** 14144 * TSC_WC4_TSC_USER4_RX_X4_Status0 14145 */ 14146 /**************************************************************************** 14147 * RX_X4_Status0 :: fec_dbg_errL 14148 */ 14149 /* RX_X4_Status0 :: fec_dbg_errL :: dbg_errL [15:00] */ 14150 #define RX_X4_STATUS0_FEC_DBG_ERRL_DBG_ERRL_MASK 0xffff 14151 #define RX_X4_STATUS0_FEC_DBG_ERRL_DBG_ERRL_ALIGN 0 14152 #define RX_X4_STATUS0_FEC_DBG_ERRL_DBG_ERRL_BITS 16 14153 #define RX_X4_STATUS0_FEC_DBG_ERRL_DBG_ERRL_SHIFT 0 14154 14155 14156 /**************************************************************************** 14157 * RX_X4_Status0 :: fec_dbg_erraH 14158 */ 14159 /* RX_X4_Status0 :: fec_dbg_erraH :: dbg_errH [15:00] */ 14160 #define RX_X4_STATUS0_FEC_DBG_ERRAH_DBG_ERRH_MASK 0xffff 14161 #define RX_X4_STATUS0_FEC_DBG_ERRAH_DBG_ERRH_ALIGN 0 14162 #define RX_X4_STATUS0_FEC_DBG_ERRAH_DBG_ERRH_BITS 16 14163 #define RX_X4_STATUS0_FEC_DBG_ERRAH_DBG_ERRH_SHIFT 0 14164 14165 14166 /**************************************************************************** 14167 * RX_X4_Status0 :: fec_burst_err_statusL 14168 */ 14169 /* RX_X4_Status0 :: fec_burst_err_statusL :: burst_err_statusL [15:00] */ 14170 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_MASK 0xffff 14171 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_ALIGN 0 14172 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_BITS 16 14173 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_SHIFT 0 14174 14175 14176 /**************************************************************************** 14177 * RX_X4_Status0 :: fec_burst_err_statusH 14178 */ 14179 /* RX_X4_Status0 :: fec_burst_err_statusH :: burst_err_statusH [15:00] */ 14180 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_MASK 0xffff 14181 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_ALIGN 0 14182 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_BITS 16 14183 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_SHIFT 0 14184 14185 14186 /**************************************************************************** 14187 * RX_X4_Status0 :: barrel_shifter_state 14188 */ 14189 /* RX_X4_Status0 :: barrel_shifter_state :: reserved0 [15:08] */ 14190 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_RESERVED0_MASK 0xff00 14191 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_RESERVED0_ALIGN 0 14192 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_RESERVED0_BITS 8 14193 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_RESERVED0_SHIFT 8 14194 14195 /* RX_X4_Status0 :: barrel_shifter_state :: shift_ammount [07:00] */ 14196 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_MASK 0x00ff 14197 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_ALIGN 0 14198 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_BITS 8 14199 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_SHIFT 0 14200 14201 14202 /**************************************************************************** 14203 * RX_X4_Status0 :: cl49_lock_fsm_status 14204 */ 14205 /* RX_X4_Status0 :: cl49_lock_fsm_status :: reserved0 [15:05] */ 14206 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_RESERVED0_MASK 0xffe0 14207 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_RESERVED0_ALIGN 0 14208 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_RESERVED0_BITS 11 14209 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_RESERVED0_SHIFT 5 14210 14211 /* RX_X4_Status0 :: cl49_lock_fsm_status :: lsm_his_state [04:02] */ 14212 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_MASK 0x001c 14213 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_ALIGN 0 14214 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_BITS 3 14215 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_SHIFT 2 14216 14217 /* RX_X4_Status0 :: cl49_lock_fsm_status :: lsm_curr_state [01:00] */ 14218 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_MASK 0x0003 14219 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_ALIGN 0 14220 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_BITS 2 14221 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_SHIFT 0 14222 14223 14224 /**************************************************************************** 14225 * RX_X4_Status0 :: decode_status_0 14226 */ 14227 /* RX_X4_Status0 :: decode_status_0 :: cl49_r_type_coded [15:12] */ 14228 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_R_TYPE_CODED_MASK 0xf000 14229 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_R_TYPE_CODED_ALIGN 0 14230 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_R_TYPE_CODED_BITS 4 14231 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_R_TYPE_CODED_SHIFT 12 14232 14233 /* RX_X4_Status0 :: decode_status_0 :: reserved0 [11:11] */ 14234 #define RX_X4_STATUS0_DECODE_STATUS_0_RESERVED0_MASK 0x0800 14235 #define RX_X4_STATUS0_DECODE_STATUS_0_RESERVED0_ALIGN 0 14236 #define RX_X4_STATUS0_DECODE_STATUS_0_RESERVED0_BITS 1 14237 #define RX_X4_STATUS0_DECODE_STATUS_0_RESERVED0_SHIFT 11 14238 14239 /* RX_X4_Status0 :: decode_status_0 :: cl49_rxsm_history_state [10:03] */ 14240 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_HISTORY_STATE_MASK 0x07f8 14241 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_HISTORY_STATE_ALIGN 0 14242 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_HISTORY_STATE_BITS 8 14243 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_HISTORY_STATE_SHIFT 3 14244 14245 /* RX_X4_Status0 :: decode_status_0 :: cl49_rxsm_current_state [02:00] */ 14246 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_CURRENT_STATE_MASK 0x0007 14247 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_CURRENT_STATE_ALIGN 0 14248 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_CURRENT_STATE_BITS 3 14249 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_CURRENT_STATE_SHIFT 0 14250 14251 14252 /**************************************************************************** 14253 * RX_X4_Status0 :: decode_status_1 14254 */ 14255 /* RX_X4_Status0 :: decode_status_1 :: reserved0 [15:10] */ 14256 #define RX_X4_STATUS0_DECODE_STATUS_1_RESERVED0_MASK 0xfc00 14257 #define RX_X4_STATUS0_DECODE_STATUS_1_RESERVED0_ALIGN 0 14258 #define RX_X4_STATUS0_DECODE_STATUS_1_RESERVED0_BITS 6 14259 #define RX_X4_STATUS0_DECODE_STATUS_1_RESERVED0_SHIFT 10 14260 14261 /* RX_X4_Status0 :: decode_status_1 :: cl49_bermon_history_state [09:05] */ 14262 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_HISTORY_STATE_MASK 0x03e0 14263 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_HISTORY_STATE_ALIGN 0 14264 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_HISTORY_STATE_BITS 5 14265 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_HISTORY_STATE_SHIFT 5 14266 14267 /* RX_X4_Status0 :: decode_status_1 :: cl49_bermon_current_state [04:00] */ 14268 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_CURRENT_STATE_MASK 0x001f 14269 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_CURRENT_STATE_ALIGN 0 14270 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_CURRENT_STATE_BITS 5 14271 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_CURRENT_STATE_SHIFT 0 14272 14273 14274 /**************************************************************************** 14275 * RX_X4_Status0 :: decode_status_2 14276 */ 14277 /* RX_X4_Status0 :: decode_status_2 :: sync66ErrCount [15:08] */ 14278 #define RX_X4_STATUS0_DECODE_STATUS_2_SYNC66ERRCOUNT_MASK 0xff00 14279 #define RX_X4_STATUS0_DECODE_STATUS_2_SYNC66ERRCOUNT_ALIGN 0 14280 #define RX_X4_STATUS0_DECODE_STATUS_2_SYNC66ERRCOUNT_BITS 8 14281 #define RX_X4_STATUS0_DECODE_STATUS_2_SYNC66ERRCOUNT_SHIFT 8 14282 14283 /* RX_X4_Status0 :: decode_status_2 :: kcode66ErrCount [07:00] */ 14284 #define RX_X4_STATUS0_DECODE_STATUS_2_KCODE66ERRCOUNT_MASK 0x00ff 14285 #define RX_X4_STATUS0_DECODE_STATUS_2_KCODE66ERRCOUNT_ALIGN 0 14286 #define RX_X4_STATUS0_DECODE_STATUS_2_KCODE66ERRCOUNT_BITS 8 14287 #define RX_X4_STATUS0_DECODE_STATUS_2_KCODE66ERRCOUNT_SHIFT 0 14288 14289 14290 /**************************************************************************** 14291 * RX_X4_Status0 :: decode_status_3 14292 */ 14293 /* RX_X4_Status0 :: decode_status_3 :: reserved0 [15:10] */ 14294 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED0_MASK 0xfc00 14295 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED0_ALIGN 0 14296 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED0_BITS 6 14297 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED0_SHIFT 10 14298 14299 /* RX_X4_Status0 :: decode_status_3 :: cl49ieee_errored_blocks [09:02] */ 14300 #define RX_X4_STATUS0_DECODE_STATUS_3_CL49IEEE_ERRORED_BLOCKS_MASK 0x03fc 14301 #define RX_X4_STATUS0_DECODE_STATUS_3_CL49IEEE_ERRORED_BLOCKS_ALIGN 0 14302 #define RX_X4_STATUS0_DECODE_STATUS_3_CL49IEEE_ERRORED_BLOCKS_BITS 8 14303 #define RX_X4_STATUS0_DECODE_STATUS_3_CL49IEEE_ERRORED_BLOCKS_SHIFT 2 14304 14305 /* RX_X4_Status0 :: decode_status_3 :: reserved1 [01:00] */ 14306 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED1_MASK 0x0003 14307 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED1_ALIGN 0 14308 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED1_BITS 2 14309 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED1_SHIFT 0 14310 14311 14312 /**************************************************************************** 14313 * RX_X4_Status0 :: decode_status_4 14314 */ 14315 /* RX_X4_Status0 :: decode_status_4 :: b66dec_fault_det [15:15] */ 14316 #define RX_X4_STATUS0_DECODE_STATUS_4_B66DEC_FAULT_DET_MASK 0x8000 14317 #define RX_X4_STATUS0_DECODE_STATUS_4_B66DEC_FAULT_DET_ALIGN 0 14318 #define RX_X4_STATUS0_DECODE_STATUS_4_B66DEC_FAULT_DET_BITS 1 14319 #define RX_X4_STATUS0_DECODE_STATUS_4_B66DEC_FAULT_DET_SHIFT 15 14320 14321 /* RX_X4_Status0 :: decode_status_4 :: cl48_syncacq_state_l [14:04] */ 14322 #define RX_X4_STATUS0_DECODE_STATUS_4_CL48_SYNCACQ_STATE_L_MASK 0x7ff0 14323 #define RX_X4_STATUS0_DECODE_STATUS_4_CL48_SYNCACQ_STATE_L_ALIGN 0 14324 #define RX_X4_STATUS0_DECODE_STATUS_4_CL48_SYNCACQ_STATE_L_BITS 11 14325 #define RX_X4_STATUS0_DECODE_STATUS_4_CL48_SYNCACQ_STATE_L_SHIFT 4 14326 14327 /* RX_X4_Status0 :: decode_status_4 :: reserved0 [03:00] */ 14328 #define RX_X4_STATUS0_DECODE_STATUS_4_RESERVED0_MASK 0x000f 14329 #define RX_X4_STATUS0_DECODE_STATUS_4_RESERVED0_ALIGN 0 14330 #define RX_X4_STATUS0_DECODE_STATUS_4_RESERVED0_BITS 4 14331 #define RX_X4_STATUS0_DECODE_STATUS_4_RESERVED0_SHIFT 0 14332 14333 14334 /**************************************************************************** 14335 * RX_X4_Status0 :: decode_status_5 14336 */ 14337 /* RX_X4_Status0 :: decode_status_5 :: cl48_syncacq_state_d_0 [15:12] */ 14338 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_0_MASK 0xf000 14339 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_0_ALIGN 0 14340 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_0_BITS 4 14341 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_0_SHIFT 12 14342 14343 /* RX_X4_Status0 :: decode_status_5 :: cl48_syncacq_state_d_1 [11:08] */ 14344 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_1_MASK 0x0f00 14345 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_1_ALIGN 0 14346 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_1_BITS 4 14347 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_1_SHIFT 8 14348 14349 /* RX_X4_Status0 :: decode_status_5 :: cl48_syncacq_state_d_2 [07:04] */ 14350 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_2_MASK 0x00f0 14351 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_2_ALIGN 0 14352 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_2_BITS 4 14353 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_2_SHIFT 4 14354 14355 /* RX_X4_Status0 :: decode_status_5 :: cl48_syncacq_state_d_3 [03:00] */ 14356 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_3_MASK 0x000f 14357 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_3_ALIGN 0 14358 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_3_BITS 4 14359 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_3_SHIFT 0 14360 14361 14362 /**************************************************************************** 14363 * RX_X4_Status0 :: syncacq_status_0 14364 */ 14365 /* RX_X4_Status0 :: syncacq_status_0 :: reserved0 [15:04] */ 14366 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_RESERVED0_MASK 0xfff0 14367 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_RESERVED0_ALIGN 0 14368 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_RESERVED0_BITS 12 14369 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_RESERVED0_SHIFT 4 14370 14371 /* RX_X4_Status0 :: syncacq_status_0 :: cl36_syncacq_state_coded_per_ln [03:00] */ 14372 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_CL36_SYNCACQ_STATE_CODED_PER_LN_MASK 0x000f 14373 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_CL36_SYNCACQ_STATE_CODED_PER_LN_ALIGN 0 14374 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_CL36_SYNCACQ_STATE_CODED_PER_LN_BITS 4 14375 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_CL36_SYNCACQ_STATE_CODED_PER_LN_SHIFT 0 14376 14377 14378 /**************************************************************************** 14379 * RX_X4_Status0 :: syncacq_status_1 14380 */ 14381 /* RX_X4_Status0 :: syncacq_status_1 :: reserved0 [15:13] */ 14382 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_RESERVED0_MASK 0xe000 14383 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_RESERVED0_ALIGN 0 14384 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_RESERVED0_BITS 3 14385 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_RESERVED0_SHIFT 13 14386 14387 /* RX_X4_Status0 :: syncacq_status_1 :: cl36_syncacq_his_state_per_ln [12:00] */ 14388 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_CL36_SYNCACQ_HIS_STATE_PER_LN_MASK 0x1fff 14389 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_CL36_SYNCACQ_HIS_STATE_PER_LN_ALIGN 0 14390 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_CL36_SYNCACQ_HIS_STATE_PER_LN_BITS 13 14391 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_CL36_SYNCACQ_HIS_STATE_PER_LN_SHIFT 0 14392 14393 14394 /**************************************************************************** 14395 * RX_X4_Status0 :: bercount 14396 */ 14397 /* RX_X4_Status0 :: bercount :: BIP_ERROR_COUNT_PER_LANE [15:08] */ 14398 #define RX_X4_STATUS0_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_MASK 0xff00 14399 #define RX_X4_STATUS0_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_ALIGN 0 14400 #define RX_X4_STATUS0_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_BITS 8 14401 #define RX_X4_STATUS0_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_SHIFT 8 14402 14403 /* RX_X4_Status0 :: bercount :: BER_count_per_ln [07:00] */ 14404 #define RX_X4_STATUS0_BERCOUNT_BER_COUNT_PER_LN_MASK 0x00ff 14405 #define RX_X4_STATUS0_BERCOUNT_BER_COUNT_PER_LN_ALIGN 0 14406 #define RX_X4_STATUS0_BERCOUNT_BER_COUNT_PER_LN_BITS 8 14407 #define RX_X4_STATUS0_BERCOUNT_BER_COUNT_PER_LN_SHIFT 0 14408 14409 14410 /**************************************************************************** 14411 * TSC_WC4_TSC_USER4_RX_X4_Status1 14412 */ 14413 /**************************************************************************** 14414 * RX_X4_Status1 :: pma_pmd_live_status 14415 */ 14416 /* RX_X4_Status1 :: pma_pmd_live_status :: reserved0 [15:11] */ 14417 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RESERVED0_MASK 0xf800 14418 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RESERVED0_ALIGN 0 14419 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RESERVED0_BITS 5 14420 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RESERVED0_SHIFT 11 14421 14422 /* RX_X4_Status1 :: pma_pmd_live_status :: PLL_POWER_DOWN [10:10] */ 14423 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PLL_POWER_DOWN_MASK 0x0400 14424 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PLL_POWER_DOWN_ALIGN 0 14425 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PLL_POWER_DOWN_BITS 1 14426 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PLL_POWER_DOWN_SHIFT 10 14427 14428 /* RX_X4_Status1 :: pma_pmd_live_status :: PLL_RESET [09:09] */ 14429 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PLL_RESET_MASK 0x0200 14430 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PLL_RESET_ALIGN 0 14431 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PLL_RESET_BITS 1 14432 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PLL_RESET_SHIFT 9 14433 14434 /* RX_X4_Status1 :: pma_pmd_live_status :: TX_LOW_POWER_6G [08:08] */ 14435 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_LOW_POWER_6G_MASK 0x0100 14436 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_LOW_POWER_6G_ALIGN 0 14437 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_LOW_POWER_6G_BITS 1 14438 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_LOW_POWER_6G_SHIFT 8 14439 14440 /* RX_X4_Status1 :: pma_pmd_live_status :: TX_ANA_POWER_DOWN [07:07] */ 14441 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_ANA_POWER_DOWN_MASK 0x0080 14442 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_ANA_POWER_DOWN_ALIGN 0 14443 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_ANA_POWER_DOWN_BITS 1 14444 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_ANA_POWER_DOWN_SHIFT 7 14445 14446 /* RX_X4_Status1 :: pma_pmd_live_status :: TX_ANA_RESET [06:06] */ 14447 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_ANA_RESET_MASK 0x0040 14448 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_ANA_RESET_ALIGN 0 14449 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_ANA_RESET_BITS 1 14450 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_TX_ANA_RESET_SHIFT 6 14451 14452 /* RX_X4_Status1 :: pma_pmd_live_status :: RX_ANA_POWER_DOWN [05:05] */ 14453 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RX_ANA_POWER_DOWN_MASK 0x0020 14454 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RX_ANA_POWER_DOWN_ALIGN 0 14455 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RX_ANA_POWER_DOWN_BITS 1 14456 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RX_ANA_POWER_DOWN_SHIFT 5 14457 14458 /* RX_X4_Status1 :: pma_pmd_live_status :: RX_ANA_RESET [04:04] */ 14459 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RX_ANA_RESET_MASK 0x0010 14460 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RX_ANA_RESET_ALIGN 0 14461 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RX_ANA_RESET_BITS 1 14462 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_RX_ANA_RESET_SHIFT 4 14463 14464 /* RX_X4_Status1 :: pma_pmd_live_status :: PMD_LOCK [03:03] */ 14465 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PMD_LOCK_MASK 0x0008 14466 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PMD_LOCK_ALIGN 0 14467 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PMD_LOCK_BITS 1 14468 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_PMD_LOCK_SHIFT 3 14469 14470 /* RX_X4_Status1 :: pma_pmd_live_status :: External_Signal_detect [02:02] */ 14471 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_EXTERNAL_SIGNAL_DETECT_MASK 0x0004 14472 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_EXTERNAL_SIGNAL_DETECT_ALIGN 0 14473 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_EXTERNAL_SIGNAL_DETECT_BITS 1 14474 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_EXTERNAL_SIGNAL_DETECT_SHIFT 2 14475 14476 /* RX_X4_Status1 :: pma_pmd_live_status :: AFE_Signal_detect [01:01] */ 14477 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_AFE_SIGNAL_DETECT_MASK 0x0002 14478 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_AFE_SIGNAL_DETECT_ALIGN 0 14479 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_AFE_SIGNAL_DETECT_BITS 1 14480 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_AFE_SIGNAL_DETECT_SHIFT 1 14481 14482 /* RX_X4_Status1 :: pma_pmd_live_status :: signal_ok [00:00] */ 14483 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_SIGNAL_OK_MASK 0x0001 14484 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_SIGNAL_OK_ALIGN 0 14485 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_SIGNAL_OK_BITS 1 14486 #define RX_X4_STATUS1_PMA_PMD_LIVE_STATUS_SIGNAL_OK_SHIFT 0 14487 14488 14489 /**************************************************************************** 14490 * RX_X4_Status1 :: pma_pmd_latched_status 14491 */ 14492 /* RX_X4_Status1 :: pma_pmd_latched_status :: reserved0 [15:08] */ 14493 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_RESERVED0_MASK 0xff00 14494 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_RESERVED0_ALIGN 0 14495 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_RESERVED0_BITS 8 14496 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_RESERVED0_SHIFT 8 14497 14498 /* RX_X4_Status1 :: pma_pmd_latched_status :: PMD_LOCK_LH [07:07] */ 14499 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_PMD_LOCK_LH_MASK 0x0080 14500 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_PMD_LOCK_LH_ALIGN 0 14501 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_PMD_LOCK_LH_BITS 1 14502 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_PMD_LOCK_LH_SHIFT 7 14503 14504 /* RX_X4_Status1 :: pma_pmd_latched_status :: PMD_LOCK_LL [06:06] */ 14505 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_PMD_LOCK_LL_MASK 0x0040 14506 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_PMD_LOCK_LL_ALIGN 0 14507 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_PMD_LOCK_LL_BITS 1 14508 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_PMD_LOCK_LL_SHIFT 6 14509 14510 /* RX_X4_Status1 :: pma_pmd_latched_status :: External_Signal_detect_LH [05:05] */ 14511 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_EXTERNAL_SIGNAL_DETECT_LH_MASK 0x0020 14512 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_EXTERNAL_SIGNAL_DETECT_LH_ALIGN 0 14513 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_EXTERNAL_SIGNAL_DETECT_LH_BITS 1 14514 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_EXTERNAL_SIGNAL_DETECT_LH_SHIFT 5 14515 14516 /* RX_X4_Status1 :: pma_pmd_latched_status :: External_Signal_detect_LL [04:04] */ 14517 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_EXTERNAL_SIGNAL_DETECT_LL_MASK 0x0010 14518 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_EXTERNAL_SIGNAL_DETECT_LL_ALIGN 0 14519 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_EXTERNAL_SIGNAL_DETECT_LL_BITS 1 14520 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_EXTERNAL_SIGNAL_DETECT_LL_SHIFT 4 14521 14522 /* RX_X4_Status1 :: pma_pmd_latched_status :: AFE_Signal_detect_LH [03:03] */ 14523 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_AFE_SIGNAL_DETECT_LH_MASK 0x0008 14524 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_AFE_SIGNAL_DETECT_LH_ALIGN 0 14525 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_AFE_SIGNAL_DETECT_LH_BITS 1 14526 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_AFE_SIGNAL_DETECT_LH_SHIFT 3 14527 14528 /* RX_X4_Status1 :: pma_pmd_latched_status :: AFE_Signal_detect_LL [02:02] */ 14529 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_AFE_SIGNAL_DETECT_LL_MASK 0x0004 14530 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_AFE_SIGNAL_DETECT_LL_ALIGN 0 14531 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_AFE_SIGNAL_DETECT_LL_BITS 1 14532 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_AFE_SIGNAL_DETECT_LL_SHIFT 2 14533 14534 /* RX_X4_Status1 :: pma_pmd_latched_status :: signal_ok_LH [01:01] */ 14535 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_SIGNAL_OK_LH_MASK 0x0002 14536 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_SIGNAL_OK_LH_ALIGN 0 14537 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_SIGNAL_OK_LH_BITS 1 14538 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_SIGNAL_OK_LH_SHIFT 1 14539 14540 /* RX_X4_Status1 :: pma_pmd_latched_status :: signal_ok_LL [00:00] */ 14541 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_SIGNAL_OK_LL_MASK 0x0001 14542 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_SIGNAL_OK_LL_ALIGN 0 14543 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_SIGNAL_OK_LL_BITS 1 14544 #define RX_X4_STATUS1_PMA_PMD_LATCHED_STATUS_SIGNAL_OK_LL_SHIFT 0 14545 14546 14547 /**************************************************************************** 14548 * RX_X4_Status1 :: pcs_latched_status_1 14549 */ 14550 /* RX_X4_Status1 :: pcs_latched_status_1 :: LOCAL_FAULT_LH [15:15] */ 14551 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_MASK 0x8000 14552 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_ALIGN 0 14553 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_BITS 1 14554 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_SHIFT 15 14555 14556 /* RX_X4_Status1 :: pcs_latched_status_1 :: REMOTE_FAULT_LH [14:14] */ 14557 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_MASK 0x4000 14558 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_ALIGN 0 14559 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_BITS 1 14560 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_SHIFT 14 14561 14562 /* RX_X4_Status1 :: pcs_latched_status_1 :: LINK_INTERRUPT_LH [13:13] */ 14563 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_MASK 0x2000 14564 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_ALIGN 0 14565 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_BITS 1 14566 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_SHIFT 13 14567 14568 /* RX_X4_Status1 :: pcs_latched_status_1 :: RESERVED_ORDERED_SET_LH [12:12] */ 14569 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_SET_LH_MASK 0x1000 14570 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_SET_LH_ALIGN 0 14571 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_SET_LH_BITS 1 14572 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_SET_LH_SHIFT 12 14573 14574 /* RX_X4_Status1 :: pcs_latched_status_1 :: RESERVED_ORDERED_BYTE_3 [11:04] */ 14575 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_BYTE_3_MASK 0x0ff0 14576 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_BYTE_3_ALIGN 0 14577 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_BYTE_3_BITS 8 14578 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_BYTE_3_SHIFT 4 14579 14580 /* RX_X4_Status1 :: pcs_latched_status_1 :: LPI_RECEIVED_LH [03:03] */ 14581 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_MASK 0x0008 14582 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_ALIGN 0 14583 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_BITS 1 14584 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_SHIFT 3 14585 14586 /* RX_X4_Status1 :: pcs_latched_status_1 :: reserved0 [02:00] */ 14587 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_MASK 0x0007 14588 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_ALIGN 0 14589 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_BITS 3 14590 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_SHIFT 0 14591 14592 14593 /**************************************************************************** 14594 * RX_X4_Status1 :: pcs_latched_status_0 14595 */ 14596 /* RX_X4_Status1 :: pcs_latched_status_0 :: AM_LOCK_LH [15:15] */ 14597 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LH_MASK 0x8000 14598 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LH_ALIGN 0 14599 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LH_BITS 1 14600 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LH_SHIFT 15 14601 14602 /* RX_X4_Status1 :: pcs_latched_status_0 :: AM_LOCK_LL [14:14] */ 14603 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LL_MASK 0x4000 14604 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LL_ALIGN 0 14605 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LL_BITS 1 14606 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LL_SHIFT 14 14607 14608 /* RX_X4_Status1 :: pcs_latched_status_0 :: DESKEW_STATUS_LH [13:13] */ 14609 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LH_MASK 0x2000 14610 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LH_ALIGN 0 14611 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LH_BITS 1 14612 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LH_SHIFT 13 14613 14614 /* RX_X4_Status1 :: pcs_latched_status_0 :: DESKEW_STATUS_LL [12:12] */ 14615 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LL_MASK 0x1000 14616 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LL_ALIGN 0 14617 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LL_BITS 1 14618 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LL_SHIFT 12 14619 14620 /* RX_X4_Status1 :: pcs_latched_status_0 :: HI_BER_LH [11:11] */ 14621 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LH_MASK 0x0800 14622 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LH_ALIGN 0 14623 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LH_BITS 1 14624 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LH_SHIFT 11 14625 14626 /* RX_X4_Status1 :: pcs_latched_status_0 :: HI_BER_LL [10:10] */ 14627 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LL_MASK 0x0400 14628 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LL_ALIGN 0 14629 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LL_BITS 1 14630 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LL_SHIFT 10 14631 14632 /* RX_X4_Status1 :: pcs_latched_status_0 :: LINK_STATUS_LH [09:09] */ 14633 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LH_MASK 0x0200 14634 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LH_ALIGN 0 14635 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LH_BITS 1 14636 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LH_SHIFT 9 14637 14638 /* RX_X4_Status1 :: pcs_latched_status_0 :: LINK_STATUS_LL [08:08] */ 14639 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LL_MASK 0x0100 14640 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LL_ALIGN 0 14641 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LL_BITS 1 14642 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LL_SHIFT 8 14643 14644 /* RX_X4_Status1 :: pcs_latched_status_0 :: SYNC_STATUS_LH [07:07] */ 14645 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LH_MASK 0x0080 14646 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LH_ALIGN 0 14647 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LH_BITS 1 14648 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LH_SHIFT 7 14649 14650 /* RX_X4_Status1 :: pcs_latched_status_0 :: SYNC_STATUS_LL [06:06] */ 14651 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LL_MASK 0x0040 14652 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LL_ALIGN 0 14653 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LL_BITS 1 14654 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LL_SHIFT 6 14655 14656 /* RX_X4_Status1 :: pcs_latched_status_0 :: reserved0 [05:00] */ 14657 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_RESERVED0_MASK 0x003f 14658 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_RESERVED0_ALIGN 0 14659 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_RESERVED0_BITS 6 14660 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_RESERVED0_SHIFT 0 14661 14662 14663 /**************************************************************************** 14664 * RX_X4_Status1 :: pcs_live_status 14665 */ 14666 /* RX_X4_Status1 :: pcs_live_status :: reserved0 [15:09] */ 14667 #define RX_X4_STATUS1_PCS_LIVE_STATUS_RESERVED0_MASK 0xfe00 14668 #define RX_X4_STATUS1_PCS_LIVE_STATUS_RESERVED0_ALIGN 0 14669 #define RX_X4_STATUS1_PCS_LIVE_STATUS_RESERVED0_BITS 7 14670 #define RX_X4_STATUS1_PCS_LIVE_STATUS_RESERVED0_SHIFT 9 14671 14672 /* RX_X4_Status1 :: pcs_live_status :: LOCAL_FAULT [08:08] */ 14673 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LOCAL_FAULT_MASK 0x0100 14674 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LOCAL_FAULT_ALIGN 0 14675 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LOCAL_FAULT_BITS 1 14676 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LOCAL_FAULT_SHIFT 8 14677 14678 /* RX_X4_Status1 :: pcs_live_status :: REMOTE_FAULT [07:07] */ 14679 #define RX_X4_STATUS1_PCS_LIVE_STATUS_REMOTE_FAULT_MASK 0x0080 14680 #define RX_X4_STATUS1_PCS_LIVE_STATUS_REMOTE_FAULT_ALIGN 0 14681 #define RX_X4_STATUS1_PCS_LIVE_STATUS_REMOTE_FAULT_BITS 1 14682 #define RX_X4_STATUS1_PCS_LIVE_STATUS_REMOTE_FAULT_SHIFT 7 14683 14684 /* RX_X4_Status1 :: pcs_live_status :: LINK_INTERRUPT [06:06] */ 14685 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_INTERRUPT_MASK 0x0040 14686 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_INTERRUPT_ALIGN 0 14687 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_INTERRUPT_BITS 1 14688 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_INTERRUPT_SHIFT 6 14689 14690 /* RX_X4_Status1 :: pcs_live_status :: LPI_RECEIVED [05:05] */ 14691 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LPI_RECEIVED_MASK 0x0020 14692 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LPI_RECEIVED_ALIGN 0 14693 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LPI_RECEIVED_BITS 1 14694 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LPI_RECEIVED_SHIFT 5 14695 14696 /* RX_X4_Status1 :: pcs_live_status :: AM_LOCK [04:04] */ 14697 #define RX_X4_STATUS1_PCS_LIVE_STATUS_AM_LOCK_MASK 0x0010 14698 #define RX_X4_STATUS1_PCS_LIVE_STATUS_AM_LOCK_ALIGN 0 14699 #define RX_X4_STATUS1_PCS_LIVE_STATUS_AM_LOCK_BITS 1 14700 #define RX_X4_STATUS1_PCS_LIVE_STATUS_AM_LOCK_SHIFT 4 14701 14702 /* RX_X4_Status1 :: pcs_live_status :: DESKEW_STATUS [03:03] */ 14703 #define RX_X4_STATUS1_PCS_LIVE_STATUS_DESKEW_STATUS_MASK 0x0008 14704 #define RX_X4_STATUS1_PCS_LIVE_STATUS_DESKEW_STATUS_ALIGN 0 14705 #define RX_X4_STATUS1_PCS_LIVE_STATUS_DESKEW_STATUS_BITS 1 14706 #define RX_X4_STATUS1_PCS_LIVE_STATUS_DESKEW_STATUS_SHIFT 3 14707 14708 /* RX_X4_Status1 :: pcs_live_status :: HI_BER [02:02] */ 14709 #define RX_X4_STATUS1_PCS_LIVE_STATUS_HI_BER_MASK 0x0004 14710 #define RX_X4_STATUS1_PCS_LIVE_STATUS_HI_BER_ALIGN 0 14711 #define RX_X4_STATUS1_PCS_LIVE_STATUS_HI_BER_BITS 1 14712 #define RX_X4_STATUS1_PCS_LIVE_STATUS_HI_BER_SHIFT 2 14713 14714 /* RX_X4_Status1 :: pcs_live_status :: LINK_STATUS [01:01] */ 14715 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_STATUS_MASK 0x0002 14716 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_STATUS_ALIGN 0 14717 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_STATUS_BITS 1 14718 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_STATUS_SHIFT 1 14719 14720 /* RX_X4_Status1 :: pcs_live_status :: SYNC_STATUS [00:00] */ 14721 #define RX_X4_STATUS1_PCS_LIVE_STATUS_SYNC_STATUS_MASK 0x0001 14722 #define RX_X4_STATUS1_PCS_LIVE_STATUS_SYNC_STATUS_ALIGN 0 14723 #define RX_X4_STATUS1_PCS_LIVE_STATUS_SYNC_STATUS_BITS 1 14724 #define RX_X4_STATUS1_PCS_LIVE_STATUS_SYNC_STATUS_SHIFT 0 14725 14726 14727 /**************************************************************************** 14728 * RX_X4_Status1 :: cl82_rx_am_latched_status 14729 */ 14730 /* RX_X4_Status1 :: cl82_rx_am_latched_status :: reserved0 [15:11] */ 14731 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_RESERVED0_MASK 0xf800 14732 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_RESERVED0_ALIGN 0 14733 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_RESERVED0_BITS 5 14734 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_RESERVED0_SHIFT 11 14735 14736 /* RX_X4_Status1 :: cl82_rx_am_latched_status :: amrkr_spacing_err_latch_mux [10:10] */ 14737 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_MASK 0x0400 14738 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_ALIGN 0 14739 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_BITS 1 14740 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_SHIFT 10 14741 14742 /* RX_X4_Status1 :: cl82_rx_am_latched_status :: am_lock_his_state [09:00] */ 14743 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AM_LOCK_HIS_STATE_MASK 0x03ff 14744 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AM_LOCK_HIS_STATE_ALIGN 0 14745 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AM_LOCK_HIS_STATE_BITS 10 14746 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AM_LOCK_HIS_STATE_SHIFT 0 14747 14748 14749 /**************************************************************************** 14750 * RX_X4_Status1 :: cl82_rx_am_live_status 14751 */ 14752 /* RX_X4_Status1 :: cl82_rx_am_live_status :: reserved0 [15:10] */ 14753 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_RESERVED0_MASK 0xfc00 14754 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_RESERVED0_ALIGN 0 14755 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_RESERVED0_BITS 6 14756 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_RESERVED0_SHIFT 10 14757 14758 /* RX_X4_Status1 :: cl82_rx_am_live_status :: am_lock_state [09:00] */ 14759 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_AM_LOCK_STATE_MASK 0x03ff 14760 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_AM_LOCK_STATE_ALIGN 0 14761 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_AM_LOCK_STATE_BITS 10 14762 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_AM_LOCK_STATE_SHIFT 0 14763 14764 14765 /**************************************************************************** 14766 * TSC_WC4_TSC_USER4_RX_X4_Control0_tsc_12 14767 */ 14768 /**************************************************************************** 14769 * RX_X4_Control0_tsc_12 :: fec_0 14770 */ 14771 /* RX_X4_Control0_tsc_12 :: fec_0 :: reserved0 [15:14] */ 14772 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED0_MASK 0xc000 14773 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED0_ALIGN 0 14774 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED0_BITS 2 14775 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED0_SHIFT 14 14776 14777 /* RX_X4_Control0_tsc_12 :: fec_0 :: fec_err_enable [13:13] */ 14778 #define RX_X4_CONTROL0_TSC_12_FEC_0_FEC_ERR_ENABLE_MASK 0x2000 14779 #define RX_X4_CONTROL0_TSC_12_FEC_0_FEC_ERR_ENABLE_ALIGN 0 14780 #define RX_X4_CONTROL0_TSC_12_FEC_0_FEC_ERR_ENABLE_BITS 1 14781 #define RX_X4_CONTROL0_TSC_12_FEC_0_FEC_ERR_ENABLE_SHIFT 13 14782 14783 /* RX_X4_Control0_tsc_12 :: fec_0 :: error_en_ovr [12:12] */ 14784 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_MASK 0x1000 14785 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_ALIGN 0 14786 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_BITS 1 14787 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_SHIFT 12 14788 14789 /* RX_X4_Control0_tsc_12 :: fec_0 :: error_en_ovr_val [11:11] */ 14790 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_VAL_MASK 0x0800 14791 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_VAL_ALIGN 0 14792 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_VAL_BITS 1 14793 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_VAL_SHIFT 11 14794 14795 /* RX_X4_Control0_tsc_12 :: fec_0 :: dbg_enable [10:10] */ 14796 #define RX_X4_CONTROL0_TSC_12_FEC_0_DBG_ENABLE_MASK 0x0400 14797 #define RX_X4_CONTROL0_TSC_12_FEC_0_DBG_ENABLE_ALIGN 0 14798 #define RX_X4_CONTROL0_TSC_12_FEC_0_DBG_ENABLE_BITS 1 14799 #define RX_X4_CONTROL0_TSC_12_FEC_0_DBG_ENABLE_SHIFT 10 14800 14801 /* RX_X4_Control0_tsc_12 :: fec_0 :: fast_lock_en [09:09] */ 14802 #define RX_X4_CONTROL0_TSC_12_FEC_0_FAST_LOCK_EN_MASK 0x0200 14803 #define RX_X4_CONTROL0_TSC_12_FEC_0_FAST_LOCK_EN_ALIGN 0 14804 #define RX_X4_CONTROL0_TSC_12_FEC_0_FAST_LOCK_EN_BITS 1 14805 #define RX_X4_CONTROL0_TSC_12_FEC_0_FAST_LOCK_EN_SHIFT 9 14806 14807 /* RX_X4_Control0_tsc_12 :: fec_0 :: reserved1 [08:00] */ 14808 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED1_MASK 0x01ff 14809 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED1_ALIGN 0 14810 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED1_BITS 9 14811 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED1_SHIFT 0 14812 14813 14814 /**************************************************************************** 14815 * RX_X4_Control0_tsc_12 :: fec_1 14816 */ 14817 /* RX_X4_Control0_tsc_12 :: fec_1 :: fec_error_code_all [15:15] */ 14818 #define RX_X4_CONTROL0_TSC_12_FEC_1_FEC_ERROR_CODE_ALL_MASK 0x8000 14819 #define RX_X4_CONTROL0_TSC_12_FEC_1_FEC_ERROR_CODE_ALL_ALIGN 0 14820 #define RX_X4_CONTROL0_TSC_12_FEC_1_FEC_ERROR_CODE_ALL_BITS 1 14821 #define RX_X4_CONTROL0_TSC_12_FEC_1_FEC_ERROR_CODE_ALL_SHIFT 15 14822 14823 /* RX_X4_Control0_tsc_12 :: fec_1 :: good_parity_cnt [14:12] */ 14824 #define RX_X4_CONTROL0_TSC_12_FEC_1_GOOD_PARITY_CNT_MASK 0x7000 14825 #define RX_X4_CONTROL0_TSC_12_FEC_1_GOOD_PARITY_CNT_ALIGN 0 14826 #define RX_X4_CONTROL0_TSC_12_FEC_1_GOOD_PARITY_CNT_BITS 3 14827 #define RX_X4_CONTROL0_TSC_12_FEC_1_GOOD_PARITY_CNT_SHIFT 12 14828 14829 /* RX_X4_Control0_tsc_12 :: fec_1 :: invalid_parity_cnt [11:08] */ 14830 #define RX_X4_CONTROL0_TSC_12_FEC_1_INVALID_PARITY_CNT_MASK 0x0f00 14831 #define RX_X4_CONTROL0_TSC_12_FEC_1_INVALID_PARITY_CNT_ALIGN 0 14832 #define RX_X4_CONTROL0_TSC_12_FEC_1_INVALID_PARITY_CNT_BITS 4 14833 #define RX_X4_CONTROL0_TSC_12_FEC_1_INVALID_PARITY_CNT_SHIFT 8 14834 14835 /* RX_X4_Control0_tsc_12 :: fec_1 :: dec_max_pm [07:02] */ 14836 #define RX_X4_CONTROL0_TSC_12_FEC_1_DEC_MAX_PM_MASK 0x00fc 14837 #define RX_X4_CONTROL0_TSC_12_FEC_1_DEC_MAX_PM_ALIGN 0 14838 #define RX_X4_CONTROL0_TSC_12_FEC_1_DEC_MAX_PM_BITS 6 14839 #define RX_X4_CONTROL0_TSC_12_FEC_1_DEC_MAX_PM_SHIFT 2 14840 14841 /* RX_X4_Control0_tsc_12 :: fec_1 :: burst_err_status_mode [01:01] */ 14842 #define RX_X4_CONTROL0_TSC_12_FEC_1_BURST_ERR_STATUS_MODE_MASK 0x0002 14843 #define RX_X4_CONTROL0_TSC_12_FEC_1_BURST_ERR_STATUS_MODE_ALIGN 0 14844 #define RX_X4_CONTROL0_TSC_12_FEC_1_BURST_ERR_STATUS_MODE_BITS 1 14845 #define RX_X4_CONTROL0_TSC_12_FEC_1_BURST_ERR_STATUS_MODE_SHIFT 1 14846 14847 /* RX_X4_Control0_tsc_12 :: fec_1 :: dbg_err_mode [00:00] */ 14848 #define RX_X4_CONTROL0_TSC_12_FEC_1_DBG_ERR_MODE_MASK 0x0001 14849 #define RX_X4_CONTROL0_TSC_12_FEC_1_DBG_ERR_MODE_ALIGN 0 14850 #define RX_X4_CONTROL0_TSC_12_FEC_1_DBG_ERR_MODE_BITS 1 14851 #define RX_X4_CONTROL0_TSC_12_FEC_1_DBG_ERR_MODE_SHIFT 0 14852 14853 14854 /**************************************************************************** 14855 * RX_X4_Control0_tsc_12 :: fec_2 14856 */ 14857 /* RX_X4_Control0_tsc_12 :: fec_2 :: dec_pm_mode [15:11] */ 14858 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_PM_MODE_MASK 0xf800 14859 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_PM_MODE_ALIGN 0 14860 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_PM_MODE_BITS 5 14861 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_PM_MODE_SHIFT 11 14862 14863 /* RX_X4_Control0_tsc_12 :: fec_2 :: dec_19b_burst_gap_count [10:08] */ 14864 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_19B_BURST_GAP_COUNT_MASK 0x0700 14865 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_19B_BURST_GAP_COUNT_ALIGN 0 14866 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_19B_BURST_GAP_COUNT_BITS 3 14867 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_19B_BURST_GAP_COUNT_SHIFT 8 14868 14869 /* RX_X4_Control0_tsc_12 :: fec_2 :: dec_18b_burst_gap_count [07:05] */ 14870 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_18B_BURST_GAP_COUNT_MASK 0x00e0 14871 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_18B_BURST_GAP_COUNT_ALIGN 0 14872 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_18B_BURST_GAP_COUNT_BITS 3 14873 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_18B_BURST_GAP_COUNT_SHIFT 5 14874 14875 /* RX_X4_Control0_tsc_12 :: fec_2 :: dec_17b_burst_gap_count [04:02] */ 14876 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_17B_BURST_GAP_COUNT_MASK 0x001c 14877 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_17B_BURST_GAP_COUNT_ALIGN 0 14878 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_17B_BURST_GAP_COUNT_BITS 3 14879 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_17B_BURST_GAP_COUNT_SHIFT 2 14880 14881 /* RX_X4_Control0_tsc_12 :: fec_2 :: dec_gap_count_mode [01:01] */ 14882 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_GAP_COUNT_MODE_MASK 0x0002 14883 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_GAP_COUNT_MODE_ALIGN 0 14884 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_GAP_COUNT_MODE_BITS 1 14885 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_GAP_COUNT_MODE_SHIFT 1 14886 14887 /* RX_X4_Control0_tsc_12 :: fec_2 :: reserved0 [00:00] */ 14888 #define RX_X4_CONTROL0_TSC_12_FEC_2_RESERVED0_MASK 0x0001 14889 #define RX_X4_CONTROL0_TSC_12_FEC_2_RESERVED0_ALIGN 0 14890 #define RX_X4_CONTROL0_TSC_12_FEC_2_RESERVED0_BITS 1 14891 #define RX_X4_CONTROL0_TSC_12_FEC_2_RESERVED0_SHIFT 0 14892 14893 14894 /**************************************************************************** 14895 * TSC_WC4_TSC_USER4_RX_X4_Status0_tsc_12 14896 */ 14897 /**************************************************************************** 14898 * RX_X4_Status0_tsc_12 :: fec_dbg_errL 14899 */ 14900 /* RX_X4_Status0_tsc_12 :: fec_dbg_errL :: dbg_errL [15:00] */ 14901 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRL_DBG_ERRL_MASK 0xffff 14902 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRL_DBG_ERRL_ALIGN 0 14903 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRL_DBG_ERRL_BITS 16 14904 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRL_DBG_ERRL_SHIFT 0 14905 14906 14907 /**************************************************************************** 14908 * RX_X4_Status0_tsc_12 :: fec_dbg_erraH 14909 */ 14910 /* RX_X4_Status0_tsc_12 :: fec_dbg_erraH :: dbg_errH [15:00] */ 14911 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAH_DBG_ERRH_MASK 0xffff 14912 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAH_DBG_ERRH_ALIGN 0 14913 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAH_DBG_ERRH_BITS 16 14914 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAH_DBG_ERRH_SHIFT 0 14915 14916 14917 /**************************************************************************** 14918 * RX_X4_Status0_tsc_12 :: fec_burst_err_statusL 14919 */ 14920 /* RX_X4_Status0_tsc_12 :: fec_burst_err_statusL :: burst_err_statusL [15:00] */ 14921 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_MASK 0xffff 14922 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_ALIGN 0 14923 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_BITS 16 14924 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_SHIFT 0 14925 14926 14927 /**************************************************************************** 14928 * RX_X4_Status0_tsc_12 :: fec_burst_err_statusH 14929 */ 14930 /* RX_X4_Status0_tsc_12 :: fec_burst_err_statusH :: burst_err_statusH [15:00] */ 14931 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_MASK 0xffff 14932 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_ALIGN 0 14933 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_BITS 16 14934 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_SHIFT 0 14935 14936 14937 /**************************************************************************** 14938 * RX_X4_Status0_tsc_12 :: bercount 14939 */ 14940 /* RX_X4_Status0_tsc_12 :: bercount :: reserved0 [15:08] */ 14941 #define RX_X4_STATUS0_TSC_12_BERCOUNT_RESERVED0_MASK 0xff00 14942 #define RX_X4_STATUS0_TSC_12_BERCOUNT_RESERVED0_ALIGN 0 14943 #define RX_X4_STATUS0_TSC_12_BERCOUNT_RESERVED0_BITS 8 14944 #define RX_X4_STATUS0_TSC_12_BERCOUNT_RESERVED0_SHIFT 8 14945 14946 /* RX_X4_Status0_tsc_12 :: bercount :: BIP_ERROR_COUNT_PER_LANE [07:00] */ 14947 #define RX_X4_STATUS0_TSC_12_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_MASK 0x00ff 14948 #define RX_X4_STATUS0_TSC_12_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_ALIGN 0 14949 #define RX_X4_STATUS0_TSC_12_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_BITS 8 14950 #define RX_X4_STATUS0_TSC_12_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_SHIFT 0 14951 14952 14953 /**************************************************************************** 14954 * RX_X4_Status0_tsc_12 :: cl49_lock_fsm_status_type 14955 */ 14956 /* RX_X4_Status0_tsc_12 :: cl49_lock_fsm_status_type :: reserved0 [15:05] */ 14957 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_RESERVED0_MASK 0xffe0 14958 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_RESERVED0_ALIGN 0 14959 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_RESERVED0_BITS 11 14960 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_RESERVED0_SHIFT 5 14961 14962 /* RX_X4_Status0_tsc_12 :: cl49_lock_fsm_status_type :: lsm_his_state [04:02] */ 14963 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_LSM_HIS_STATE_MASK 0x001c 14964 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_LSM_HIS_STATE_ALIGN 0 14965 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_LSM_HIS_STATE_BITS 3 14966 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_LSM_HIS_STATE_SHIFT 2 14967 14968 /* RX_X4_Status0_tsc_12 :: cl49_lock_fsm_status_type :: lsm_curr_state [01:00] */ 14969 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_LSM_CURR_STATE_MASK 0x0003 14970 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_LSM_CURR_STATE_ALIGN 0 14971 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_LSM_CURR_STATE_BITS 2 14972 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_TYPE_LSM_CURR_STATE_SHIFT 0 14973 14974 14975 /**************************************************************************** 14976 * RX_X4_Status0_tsc_12 :: mld_vl_info_0 14977 */ 14978 /* RX_X4_Status0_tsc_12 :: mld_vl_info_0 :: reserved0 [15:10] */ 14979 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_RESERVED0_MASK 0xfc00 14980 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_RESERVED0_ALIGN 0 14981 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_RESERVED0_BITS 6 14982 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_RESERVED0_SHIFT 10 14983 14984 /* RX_X4_Status0_tsc_12 :: mld_vl_info_0 :: VL_ON_LL_1 [09:05] */ 14985 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_1_MASK 0x03e0 14986 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_1_ALIGN 0 14987 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_1_BITS 5 14988 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_1_SHIFT 5 14989 14990 /* RX_X4_Status0_tsc_12 :: mld_vl_info_0 :: VL_ON_LL_0 [04:00] */ 14991 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_0_MASK 0x001f 14992 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_0_ALIGN 0 14993 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_0_BITS 5 14994 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_0_SHIFT 0 14995 14996 14997 /**************************************************************************** 14998 * RX_X4_Status0_tsc_12 :: barrel_shifter_state 14999 */ 15000 /* RX_X4_Status0_tsc_12 :: barrel_shifter_state :: reserved0 [15:08] */ 15001 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_RESERVED0_MASK 0xff00 15002 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_RESERVED0_ALIGN 0 15003 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_RESERVED0_BITS 8 15004 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_RESERVED0_SHIFT 8 15005 15006 /* RX_X4_Status0_tsc_12 :: barrel_shifter_state :: shift_ammount [07:00] */ 15007 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_MASK 0x00ff 15008 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_ALIGN 0 15009 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_BITS 8 15010 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_SHIFT 0 15011 15012 15013 /**************************************************************************** 15014 * TSC_WC4_TSC_USER4_AN_X4_ABILITIES 15015 */ 15016 /**************************************************************************** 15017 * AN_X4_ABILITIES :: enables 15018 */ 15019 /* AN_X4_ABILITIES :: enables :: reserved0 [15:15] */ 15020 #define AN_X4_ABILITIES_ENABLES_RESERVED0_MASK 0x8000 15021 #define AN_X4_ABILITIES_ENABLES_RESERVED0_ALIGN 0 15022 #define AN_X4_ABILITIES_ENABLES_RESERVED0_BITS 1 15023 #define AN_X4_ABILITIES_ENABLES_RESERVED0_SHIFT 15 15024 15025 /* AN_X4_ABILITIES :: enables :: an_setup_enable [14:14] */ 15026 #define AN_X4_ABILITIES_ENABLES_AN_SETUP_ENABLE_MASK 0x4000 15027 #define AN_X4_ABILITIES_ENABLES_AN_SETUP_ENABLE_ALIGN 0 15028 #define AN_X4_ABILITIES_ENABLES_AN_SETUP_ENABLE_BITS 1 15029 #define AN_X4_ABILITIES_ENABLES_AN_SETUP_ENABLE_SHIFT 14 15030 15031 /* AN_X4_ABILITIES :: enables :: num_advertised_lanes [13:12] */ 15032 #define AN_X4_ABILITIES_ENABLES_NUM_ADVERTISED_LANES_MASK 0x3000 15033 #define AN_X4_ABILITIES_ENABLES_NUM_ADVERTISED_LANES_ALIGN 0 15034 #define AN_X4_ABILITIES_ENABLES_NUM_ADVERTISED_LANES_BITS 2 15035 #define AN_X4_ABILITIES_ENABLES_NUM_ADVERTISED_LANES_SHIFT 12 15036 15037 /* AN_X4_ABILITIES :: enables :: cl37_bam_enable [11:11] */ 15038 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_ENABLE_MASK 0x0800 15039 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_ENABLE_ALIGN 0 15040 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_ENABLE_BITS 1 15041 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_ENABLE_SHIFT 11 15042 15043 /* AN_X4_ABILITIES :: enables :: cl73_bam_enable [10:10] */ 15044 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_ENABLE_MASK 0x0400 15045 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_ENABLE_ALIGN 0 15046 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_ENABLE_BITS 1 15047 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_ENABLE_SHIFT 10 15048 15049 /* AN_X4_ABILITIES :: enables :: cl73_hpam_enable [09:09] */ 15050 #define AN_X4_ABILITIES_ENABLES_CL73_HPAM_ENABLE_MASK 0x0200 15051 #define AN_X4_ABILITIES_ENABLES_CL73_HPAM_ENABLE_ALIGN 0 15052 #define AN_X4_ABILITIES_ENABLES_CL73_HPAM_ENABLE_BITS 1 15053 #define AN_X4_ABILITIES_ENABLES_CL73_HPAM_ENABLE_SHIFT 9 15054 15055 /* AN_X4_ABILITIES :: enables :: cl73_enable [08:08] */ 15056 #define AN_X4_ABILITIES_ENABLES_CL73_ENABLE_MASK 0x0100 15057 #define AN_X4_ABILITIES_ENABLES_CL73_ENABLE_ALIGN 0 15058 #define AN_X4_ABILITIES_ENABLES_CL73_ENABLE_BITS 1 15059 #define AN_X4_ABILITIES_ENABLES_CL73_ENABLE_SHIFT 8 15060 15061 /* AN_X4_ABILITIES :: enables :: cl37_sgmii_enable [07:07] */ 15062 #define AN_X4_ABILITIES_ENABLES_CL37_SGMII_ENABLE_MASK 0x0080 15063 #define AN_X4_ABILITIES_ENABLES_CL37_SGMII_ENABLE_ALIGN 0 15064 #define AN_X4_ABILITIES_ENABLES_CL37_SGMII_ENABLE_BITS 1 15065 #define AN_X4_ABILITIES_ENABLES_CL37_SGMII_ENABLE_SHIFT 7 15066 15067 /* AN_X4_ABILITIES :: enables :: cl37_enable [06:06] */ 15068 #define AN_X4_ABILITIES_ENABLES_CL37_ENABLE_MASK 0x0040 15069 #define AN_X4_ABILITIES_ENABLES_CL37_ENABLE_ALIGN 0 15070 #define AN_X4_ABILITIES_ENABLES_CL37_ENABLE_BITS 1 15071 #define AN_X4_ABILITIES_ENABLES_CL37_ENABLE_SHIFT 6 15072 15073 /* AN_X4_ABILITIES :: enables :: cl37_bam_to_sgmii_auto_enable [05:05] */ 15074 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_TO_SGMII_AUTO_ENABLE_MASK 0x0020 15075 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_TO_SGMII_AUTO_ENABLE_ALIGN 0 15076 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_TO_SGMII_AUTO_ENABLE_BITS 1 15077 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_TO_SGMII_AUTO_ENABLE_SHIFT 5 15078 15079 /* AN_X4_ABILITIES :: enables :: sgmii_to_cl37_auto_enable [04:04] */ 15080 #define AN_X4_ABILITIES_ENABLES_SGMII_TO_CL37_AUTO_ENABLE_MASK 0x0010 15081 #define AN_X4_ABILITIES_ENABLES_SGMII_TO_CL37_AUTO_ENABLE_ALIGN 0 15082 #define AN_X4_ABILITIES_ENABLES_SGMII_TO_CL37_AUTO_ENABLE_BITS 1 15083 #define AN_X4_ABILITIES_ENABLES_SGMII_TO_CL37_AUTO_ENABLE_SHIFT 4 15084 15085 /* AN_X4_ABILITIES :: enables :: cl73_bam_to_hpam_auto_enable [03:03] */ 15086 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_TO_HPAM_AUTO_ENABLE_MASK 0x0008 15087 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_TO_HPAM_AUTO_ENABLE_ALIGN 0 15088 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_TO_HPAM_AUTO_ENABLE_BITS 1 15089 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_TO_HPAM_AUTO_ENABLE_SHIFT 3 15090 15091 /* AN_X4_ABILITIES :: enables :: hpam_to_cl37_auto_enable [02:02] */ 15092 #define AN_X4_ABILITIES_ENABLES_HPAM_TO_CL37_AUTO_ENABLE_MASK 0x0004 15093 #define AN_X4_ABILITIES_ENABLES_HPAM_TO_CL37_AUTO_ENABLE_ALIGN 0 15094 #define AN_X4_ABILITIES_ENABLES_HPAM_TO_CL37_AUTO_ENABLE_BITS 1 15095 #define AN_X4_ABILITIES_ENABLES_HPAM_TO_CL37_AUTO_ENABLE_SHIFT 2 15096 15097 /* AN_X4_ABILITIES :: enables :: cl37_an_restart [01:01] */ 15098 #define AN_X4_ABILITIES_ENABLES_CL37_AN_RESTART_MASK 0x0002 15099 #define AN_X4_ABILITIES_ENABLES_CL37_AN_RESTART_ALIGN 0 15100 #define AN_X4_ABILITIES_ENABLES_CL37_AN_RESTART_BITS 1 15101 #define AN_X4_ABILITIES_ENABLES_CL37_AN_RESTART_SHIFT 1 15102 15103 /* AN_X4_ABILITIES :: enables :: cl73_an_restart [00:00] */ 15104 #define AN_X4_ABILITIES_ENABLES_CL73_AN_RESTART_MASK 0x0001 15105 #define AN_X4_ABILITIES_ENABLES_CL73_AN_RESTART_ALIGN 0 15106 #define AN_X4_ABILITIES_ENABLES_CL73_AN_RESTART_BITS 1 15107 #define AN_X4_ABILITIES_ENABLES_CL73_AN_RESTART_SHIFT 0 15108 15109 15110 /**************************************************************************** 15111 * AN_X4_ABILITIES :: local_device_cl37_base_abilities 15112 */ 15113 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: reserved0 [15:10] */ 15114 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED0_MASK 0xfc00 15115 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED0_ALIGN 0 15116 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED0_BITS 6 15117 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED0_SHIFT 10 15118 15119 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: sgmii_master_mode [09:09] */ 15120 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_MASTER_MODE_MASK 0x0200 15121 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_MASTER_MODE_ALIGN 0 15122 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_MASTER_MODE_BITS 1 15123 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_MASTER_MODE_SHIFT 9 15124 15125 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: cl37_next_page [08:08] */ 15126 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_NEXT_PAGE_MASK 0x0100 15127 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_NEXT_PAGE_ALIGN 0 15128 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_NEXT_PAGE_BITS 1 15129 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_NEXT_PAGE_SHIFT 8 15130 15131 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: cl37_pause [07:06] */ 15132 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_PAUSE_MASK 0x00c0 15133 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_PAUSE_ALIGN 0 15134 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_PAUSE_BITS 2 15135 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_PAUSE_SHIFT 6 15136 15137 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: cl37_half_duplex [05:05] */ 15138 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_HALF_DUPLEX_MASK 0x0020 15139 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_HALF_DUPLEX_ALIGN 0 15140 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_HALF_DUPLEX_BITS 1 15141 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_HALF_DUPLEX_SHIFT 5 15142 15143 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: cl37_full_duplex [04:04] */ 15144 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_FULL_DUPLEX_MASK 0x0010 15145 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_FULL_DUPLEX_ALIGN 0 15146 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_FULL_DUPLEX_BITS 1 15147 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_FULL_DUPLEX_SHIFT 4 15148 15149 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: reserved1 [03:03] */ 15150 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED1_MASK 0x0008 15151 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED1_ALIGN 0 15152 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED1_BITS 1 15153 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED1_SHIFT 3 15154 15155 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: sgmii_full_duplex [02:02] */ 15156 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_FULL_DUPLEX_MASK 0x0004 15157 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_FULL_DUPLEX_ALIGN 0 15158 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_FULL_DUPLEX_BITS 1 15159 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_FULL_DUPLEX_SHIFT 2 15160 15161 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: sgmii_speed [01:00] */ 15162 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_SPEED_MASK 0x0003 15163 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_SPEED_ALIGN 0 15164 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_SPEED_BITS 2 15165 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_SPEED_SHIFT 0 15166 15167 15168 /**************************************************************************** 15169 * AN_X4_ABILITIES :: local_device_cl37_bam_abilities 15170 */ 15171 /* AN_X4_ABILITIES :: local_device_cl37_bam_abilities :: reserved0 [15:12] */ 15172 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_RESERVED0_MASK 0xf000 15173 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_RESERVED0_ALIGN 0 15174 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_RESERVED0_BITS 4 15175 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_RESERVED0_SHIFT 12 15176 15177 /* AN_X4_ABILITIES :: local_device_cl37_bam_abilities :: cl37_bam_code [11:03] */ 15178 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_CL37_BAM_CODE_MASK 0x0ff8 15179 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_CL37_BAM_CODE_ALIGN 0 15180 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_CL37_BAM_CODE_BITS 9 15181 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_CL37_BAM_CODE_SHIFT 3 15182 15183 /* AN_X4_ABILITIES :: local_device_cl37_bam_abilities :: over1g_ability [02:02] */ 15184 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_ABILITY_MASK 0x0004 15185 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_ABILITY_ALIGN 0 15186 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_ABILITY_BITS 1 15187 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_ABILITY_SHIFT 2 15188 15189 /* AN_X4_ABILITIES :: local_device_cl37_bam_abilities :: over1g_page_count [01:00] */ 15190 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_PAGE_COUNT_MASK 0x0003 15191 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_PAGE_COUNT_ALIGN 0 15192 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_PAGE_COUNT_BITS 2 15193 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_PAGE_COUNT_SHIFT 0 15194 15195 15196 /**************************************************************************** 15197 * AN_X4_ABILITIES :: local_device_over1g_abilities_1 15198 */ 15199 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: HG2 [15:15] */ 15200 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_HG2_MASK 0x8000 15201 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_HG2_ALIGN 0 15202 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_HG2_BITS 1 15203 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_HG2_SHIFT 15 15204 15205 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: FEC [14:14] */ 15206 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_FEC_MASK 0x4000 15207 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_FEC_ALIGN 0 15208 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_FEC_BITS 1 15209 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_FEC_SHIFT 14 15210 15211 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: CL72 [13:13] */ 15212 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_CL72_MASK 0x2000 15213 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_CL72_ALIGN 0 15214 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_CL72_BITS 1 15215 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_CL72_SHIFT 13 15216 15217 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_40GBASE_X4 [12:12] */ 15218 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_40GBASE_X4_MASK 0x1000 15219 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_40GBASE_X4_ALIGN 0 15220 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_40GBASE_X4_BITS 1 15221 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_40GBASE_X4_SHIFT 12 15222 15223 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_32p7GBASE_X4 [11:11] */ 15224 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_32P7GBASE_X4_MASK 0x0800 15225 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_32P7GBASE_X4_ALIGN 0 15226 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_32P7GBASE_X4_BITS 1 15227 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_32P7GBASE_X4_SHIFT 11 15228 15229 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_31p5GBASE_X4 [10:10] */ 15230 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_31P5GBASE_X4_MASK 0x0400 15231 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_31P5GBASE_X4_ALIGN 0 15232 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_31P5GBASE_X4_BITS 1 15233 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_31P5GBASE_X4_SHIFT 10 15234 15235 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_25p455GBASE_X4 [09:09] */ 15236 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_25P455GBASE_X4_MASK 0x0200 15237 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_25P455GBASE_X4_ALIGN 0 15238 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_25P455GBASE_X4_BITS 1 15239 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_25P455GBASE_X4_SHIFT 9 15240 15241 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_21GBASE_X4 [08:08] */ 15242 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_21GBASE_X4_MASK 0x0100 15243 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_21GBASE_X4_ALIGN 0 15244 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_21GBASE_X4_BITS 1 15245 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_21GBASE_X4_SHIFT 8 15246 15247 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_20GBASE_X2_CX4 [07:07] */ 15248 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_CX4_MASK 0x0080 15249 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_CX4_ALIGN 0 15250 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_CX4_BITS 1 15251 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_CX4_SHIFT 7 15252 15253 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_20GBASE_X2 [06:06] */ 15254 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_MASK 0x0040 15255 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_ALIGN 0 15256 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_BITS 1 15257 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_SHIFT 6 15258 15259 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_20GBASE_X4 [05:05] */ 15260 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_MASK 0x0020 15261 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_ALIGN 0 15262 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_BITS 1 15263 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_SHIFT 5 15264 15265 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_20GBASE_X4_CX4 [04:04] */ 15266 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_CX4_MASK 0x0010 15267 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_CX4_ALIGN 0 15268 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_CX4_BITS 1 15269 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_CX4_SHIFT 4 15270 15271 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_16GBASE_X4 [03:03] */ 15272 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_16GBASE_X4_MASK 0x0008 15273 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_16GBASE_X4_ALIGN 0 15274 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_16GBASE_X4_BITS 1 15275 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_16GBASE_X4_SHIFT 3 15276 15277 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_15p75GBASE_X2 [02:02] */ 15278 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15P75GBASE_X2_MASK 0x0004 15279 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15P75GBASE_X2_ALIGN 0 15280 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15P75GBASE_X2_BITS 1 15281 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15P75GBASE_X2_SHIFT 2 15282 15283 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_15GBASE_X4 [01:01] */ 15284 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15GBASE_X4_MASK 0x0002 15285 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15GBASE_X4_ALIGN 0 15286 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15GBASE_X4_BITS 1 15287 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15GBASE_X4_SHIFT 1 15288 15289 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_13GBASE_X4 [00:00] */ 15290 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_13GBASE_X4_MASK 0x0001 15291 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_13GBASE_X4_ALIGN 0 15292 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_13GBASE_X4_BITS 1 15293 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_13GBASE_X4_SHIFT 0 15294 15295 15296 /**************************************************************************** 15297 * AN_X4_ABILITIES :: local_device_over1g_abilities_0 15298 */ 15299 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: reserved0 [15:11] */ 15300 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_RESERVED0_MASK 0xf800 15301 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_RESERVED0_ALIGN 0 15302 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_RESERVED0_BITS 5 15303 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_RESERVED0_SHIFT 11 15304 15305 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_12p7GBASE_X2 [10:10] */ 15306 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P7GBASE_X2_MASK 0x0400 15307 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P7GBASE_X2_ALIGN 0 15308 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P7GBASE_X2_BITS 1 15309 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P7GBASE_X2_SHIFT 10 15310 15311 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_12p5GBASE_X4 [09:09] */ 15312 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P5GBASE_X4_MASK 0x0200 15313 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P5GBASE_X4_ALIGN 0 15314 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P5GBASE_X4_BITS 1 15315 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P5GBASE_X4_SHIFT 9 15316 15317 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_12GBASE_X4 [08:08] */ 15318 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12GBASE_X4_MASK 0x0100 15319 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12GBASE_X4_ALIGN 0 15320 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12GBASE_X4_BITS 1 15321 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12GBASE_X4_SHIFT 8 15322 15323 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_10p5GBASE_X2 [07:07] */ 15324 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10P5GBASE_X2_MASK 0x0080 15325 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10P5GBASE_X2_ALIGN 0 15326 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10P5GBASE_X2_BITS 1 15327 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10P5GBASE_X2_SHIFT 7 15328 15329 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_10GBASE_X2_CX4 [06:06] */ 15330 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_CX4_MASK 0x0040 15331 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_CX4_ALIGN 0 15332 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_CX4_BITS 1 15333 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_CX4_SHIFT 6 15334 15335 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_10GBASE_X2 [05:05] */ 15336 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_MASK 0x0020 15337 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_ALIGN 0 15338 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_BITS 1 15339 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_SHIFT 5 15340 15341 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_10GBASE_X4_CX4 [04:04] */ 15342 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_CX4_MASK 0x0010 15343 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_CX4_ALIGN 0 15344 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_CX4_BITS 1 15345 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_CX4_SHIFT 4 15346 15347 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_10GBASE_X4 [03:03] */ 15348 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_MASK 0x0008 15349 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_ALIGN 0 15350 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_BITS 1 15351 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_SHIFT 3 15352 15353 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_6GBASE_X4 [02:02] */ 15354 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_6GBASE_X4_MASK 0x0004 15355 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_6GBASE_X4_ALIGN 0 15356 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_6GBASE_X4_BITS 1 15357 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_6GBASE_X4_SHIFT 2 15358 15359 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_5GBASE_X4 [01:01] */ 15360 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_5GBASE_X4_MASK 0x0002 15361 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_5GBASE_X4_ALIGN 0 15362 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_5GBASE_X4_BITS 1 15363 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_5GBASE_X4_SHIFT 1 15364 15365 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_2p5GBASE_X [00:00] */ 15366 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_2P5GBASE_X_MASK 0x0001 15367 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_2P5GBASE_X_ALIGN 0 15368 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_2P5GBASE_X_BITS 1 15369 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_2P5GBASE_X_SHIFT 0 15370 15371 15372 /**************************************************************************** 15373 * AN_X4_ABILITIES :: local_device_cl73_base_abilities_1 15374 */ 15375 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_1 :: reserved0 [15:10] */ 15376 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_RESERVED0_MASK 0xfc00 15377 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_RESERVED0_ALIGN 0 15378 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_RESERVED0_BITS 6 15379 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_RESERVED0_SHIFT 10 15380 15381 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_1 :: transmit_nonce [09:05] */ 15382 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_TRANSMIT_NONCE_MASK 0x03e0 15383 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_TRANSMIT_NONCE_ALIGN 0 15384 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_TRANSMIT_NONCE_BITS 5 15385 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_TRANSMIT_NONCE_SHIFT 5 15386 15387 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_1 :: base_selector [04:00] */ 15388 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_BASE_SELECTOR_MASK 0x001f 15389 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_BASE_SELECTOR_ALIGN 0 15390 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_BASE_SELECTOR_BITS 5 15391 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_BASE_SELECTOR_SHIFT 0 15392 15393 15394 /**************************************************************************** 15395 * AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 15396 */ 15397 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: reserved0 [15:12] */ 15398 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_RESERVED0_MASK 0xf000 15399 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_RESERVED0_ALIGN 0 15400 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_RESERVED0_BITS 4 15401 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_RESERVED0_SHIFT 12 15402 15403 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: cl73_remote_fault [11:11] */ 15404 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_REMOTE_FAULT_MASK 0x0800 15405 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_REMOTE_FAULT_ALIGN 0 15406 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_REMOTE_FAULT_BITS 1 15407 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_REMOTE_FAULT_SHIFT 11 15408 15409 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: next_page [10:10] */ 15410 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_NEXT_PAGE_MASK 0x0400 15411 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_NEXT_PAGE_ALIGN 0 15412 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_NEXT_PAGE_BITS 1 15413 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_NEXT_PAGE_SHIFT 10 15414 15415 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: fec [09:08] */ 15416 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_FEC_MASK 0x0300 15417 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_FEC_ALIGN 0 15418 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_FEC_BITS 2 15419 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_FEC_SHIFT 8 15420 15421 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: cl73_pause [07:06] */ 15422 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_PAUSE_MASK 0x00c0 15423 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_PAUSE_ALIGN 0 15424 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_PAUSE_BITS 2 15425 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_PAUSE_SHIFT 6 15426 15427 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_1000BASE_KX [05:05] */ 15428 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_1000BASE_KX_MASK 0x0020 15429 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_1000BASE_KX_ALIGN 0 15430 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_1000BASE_KX_BITS 1 15431 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_1000BASE_KX_SHIFT 5 15432 15433 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_10GBASE_KX4 [04:04] */ 15434 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KX4_MASK 0x0010 15435 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KX4_ALIGN 0 15436 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KX4_BITS 1 15437 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KX4_SHIFT 4 15438 15439 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_10GBASE_KR [03:03] */ 15440 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KR_MASK 0x0008 15441 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KR_ALIGN 0 15442 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KR_BITS 1 15443 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KR_SHIFT 3 15444 15445 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_40GBASE_KR4 [02:02] */ 15446 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_KR4_MASK 0x0004 15447 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_KR4_ALIGN 0 15448 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_KR4_BITS 1 15449 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_KR4_SHIFT 2 15450 15451 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_40GBASE_CR4 [01:01] */ 15452 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_CR4_MASK 0x0002 15453 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_CR4_ALIGN 0 15454 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_CR4_BITS 1 15455 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_CR4_SHIFT 1 15456 15457 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_100GBASE_CR10 [00:00] */ 15458 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_100GBASE_CR10_MASK 0x0001 15459 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_100GBASE_CR10_ALIGN 0 15460 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_100GBASE_CR10_BITS 1 15461 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_100GBASE_CR10_SHIFT 0 15462 15463 15464 /**************************************************************************** 15465 * AN_X4_ABILITIES :: local_device_cl73_bam_abilities 15466 */ 15467 /* AN_X4_ABILITIES :: local_device_cl73_bam_abilities :: reserved0 [15:12] */ 15468 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_RESERVED0_MASK 0xf000 15469 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_RESERVED0_ALIGN 0 15470 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_RESERVED0_BITS 4 15471 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_RESERVED0_SHIFT 12 15472 15473 /* AN_X4_ABILITIES :: local_device_cl73_bam_abilities :: HPAM_20GKR2 [11:11] */ 15474 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_HPAM_20GKR2_MASK 0x0800 15475 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_HPAM_20GKR2_ALIGN 0 15476 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_HPAM_20GKR2_BITS 1 15477 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_HPAM_20GKR2_SHIFT 11 15478 15479 /* AN_X4_ABILITIES :: local_device_cl73_bam_abilities :: cl73_bam_code [10:02] */ 15480 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_CL73_BAM_CODE_MASK 0x07fc 15481 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_CL73_BAM_CODE_ALIGN 0 15482 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_CL73_BAM_CODE_BITS 9 15483 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_CL73_BAM_CODE_SHIFT 2 15484 15485 /* AN_X4_ABILITIES :: local_device_cl73_bam_abilities :: BAM_20GBASE_CR2 [01:01] */ 15486 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_CR2_MASK 0x0002 15487 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_CR2_ALIGN 0 15488 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_CR2_BITS 1 15489 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_CR2_SHIFT 1 15490 15491 /* AN_X4_ABILITIES :: local_device_cl73_bam_abilities :: BAM_20GBASE_KR2 [00:00] */ 15492 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_KR2_MASK 0x0001 15493 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_KR2_ALIGN 0 15494 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_KR2_BITS 1 15495 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_KR2_SHIFT 0 15496 15497 15498 /**************************************************************************** 15499 * AN_X4_ABILITIES :: controls 15500 */ 15501 /* AN_X4_ABILITIES :: controls :: OUI_CONTROL [15:10] */ 15502 #define AN_X4_ABILITIES_CONTROLS_OUI_CONTROL_MASK 0xfc00 15503 #define AN_X4_ABILITIES_CONTROLS_OUI_CONTROL_ALIGN 0 15504 #define AN_X4_ABILITIES_CONTROLS_OUI_CONTROL_BITS 6 15505 #define AN_X4_ABILITIES_CONTROLS_OUI_CONTROL_SHIFT 10 15506 15507 /* AN_X4_ABILITIES :: controls :: an_fail_count_limit [09:06] */ 15508 #define AN_X4_ABILITIES_CONTROLS_AN_FAIL_COUNT_LIMIT_MASK 0x03c0 15509 #define AN_X4_ABILITIES_CONTROLS_AN_FAIL_COUNT_LIMIT_ALIGN 0 15510 #define AN_X4_ABILITIES_CONTROLS_AN_FAIL_COUNT_LIMIT_BITS 4 15511 #define AN_X4_ABILITIES_CONTROLS_AN_FAIL_COUNT_LIMIT_SHIFT 6 15512 15513 /* AN_X4_ABILITIES :: controls :: linkFailTimerQual_en [05:05] */ 15514 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMERQUAL_EN_MASK 0x0020 15515 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMERQUAL_EN_ALIGN 0 15516 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMERQUAL_EN_BITS 1 15517 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMERQUAL_EN_SHIFT 5 15518 15519 /* AN_X4_ABILITIES :: controls :: linkFailTimer_dis [04:04] */ 15520 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMER_DIS_MASK 0x0010 15521 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMER_DIS_ALIGN 0 15522 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMER_DIS_BITS 1 15523 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMER_DIS_SHIFT 4 15524 15525 /* AN_X4_ABILITIES :: controls :: an_good_check_trap [03:03] */ 15526 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_CHECK_TRAP_MASK 0x0008 15527 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_CHECK_TRAP_ALIGN 0 15528 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_CHECK_TRAP_BITS 1 15529 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_CHECK_TRAP_SHIFT 3 15530 15531 /* AN_X4_ABILITIES :: controls :: an_good_trap [02:02] */ 15532 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_TRAP_MASK 0x0004 15533 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_TRAP_ALIGN 0 15534 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_TRAP_BITS 1 15535 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_TRAP_SHIFT 2 15536 15537 /* AN_X4_ABILITIES :: controls :: pd_KX_en [01:01] */ 15538 #define AN_X4_ABILITIES_CONTROLS_PD_KX_EN_MASK 0x0002 15539 #define AN_X4_ABILITIES_CONTROLS_PD_KX_EN_ALIGN 0 15540 #define AN_X4_ABILITIES_CONTROLS_PD_KX_EN_BITS 1 15541 #define AN_X4_ABILITIES_CONTROLS_PD_KX_EN_SHIFT 1 15542 15543 /* AN_X4_ABILITIES :: controls :: pd_KX4_en [00:00] */ 15544 #define AN_X4_ABILITIES_CONTROLS_PD_KX4_EN_MASK 0x0001 15545 #define AN_X4_ABILITIES_CONTROLS_PD_KX4_EN_ALIGN 0 15546 #define AN_X4_ABILITIES_CONTROLS_PD_KX4_EN_BITS 1 15547 #define AN_X4_ABILITIES_CONTROLS_PD_KX4_EN_SHIFT 0 15548 15549 15550 /**************************************************************************** 15551 * TSC_WC4_TSC_USER4_AN_X4_HW_LP_PAGES 15552 */ 15553 /**************************************************************************** 15554 * AN_X4_HW_LP_PAGES :: lp_mp5_up1 15555 */ 15556 /* AN_X4_HW_LP_PAGES :: lp_mp5_up1 :: lp_mp5_up1_page_data [15:00] */ 15557 #define AN_X4_HW_LP_PAGES_LP_MP5_UP1_LP_MP5_UP1_PAGE_DATA_MASK 0xffff 15558 #define AN_X4_HW_LP_PAGES_LP_MP5_UP1_LP_MP5_UP1_PAGE_DATA_ALIGN 0 15559 #define AN_X4_HW_LP_PAGES_LP_MP5_UP1_LP_MP5_UP1_PAGE_DATA_BITS 16 15560 #define AN_X4_HW_LP_PAGES_LP_MP5_UP1_LP_MP5_UP1_PAGE_DATA_SHIFT 0 15561 15562 15563 /**************************************************************************** 15564 * AN_X4_HW_LP_PAGES :: lp_mp5_up2 15565 */ 15566 /* AN_X4_HW_LP_PAGES :: lp_mp5_up2 :: lp_mp5_up2_page_data [15:00] */ 15567 #define AN_X4_HW_LP_PAGES_LP_MP5_UP2_LP_MP5_UP2_PAGE_DATA_MASK 0xffff 15568 #define AN_X4_HW_LP_PAGES_LP_MP5_UP2_LP_MP5_UP2_PAGE_DATA_ALIGN 0 15569 #define AN_X4_HW_LP_PAGES_LP_MP5_UP2_LP_MP5_UP2_PAGE_DATA_BITS 16 15570 #define AN_X4_HW_LP_PAGES_LP_MP5_UP2_LP_MP5_UP2_PAGE_DATA_SHIFT 0 15571 15572 15573 /**************************************************************************** 15574 * AN_X4_HW_LP_PAGES :: lp_mp5_up3 15575 */ 15576 /* AN_X4_HW_LP_PAGES :: lp_mp5_up3 :: lp_mp5_up3_page_data [15:00] */ 15577 #define AN_X4_HW_LP_PAGES_LP_MP5_UP3_LP_MP5_UP3_PAGE_DATA_MASK 0xffff 15578 #define AN_X4_HW_LP_PAGES_LP_MP5_UP3_LP_MP5_UP3_PAGE_DATA_ALIGN 0 15579 #define AN_X4_HW_LP_PAGES_LP_MP5_UP3_LP_MP5_UP3_PAGE_DATA_BITS 16 15580 #define AN_X4_HW_LP_PAGES_LP_MP5_UP3_LP_MP5_UP3_PAGE_DATA_SHIFT 0 15581 15582 15583 /**************************************************************************** 15584 * AN_X4_HW_LP_PAGES :: lp_mp5_up4 15585 */ 15586 /* AN_X4_HW_LP_PAGES :: lp_mp5_up4 :: lp_mp5_up4_page_data [15:00] */ 15587 #define AN_X4_HW_LP_PAGES_LP_MP5_UP4_LP_MP5_UP4_PAGE_DATA_MASK 0xffff 15588 #define AN_X4_HW_LP_PAGES_LP_MP5_UP4_LP_MP5_UP4_PAGE_DATA_ALIGN 0 15589 #define AN_X4_HW_LP_PAGES_LP_MP5_UP4_LP_MP5_UP4_PAGE_DATA_BITS 16 15590 #define AN_X4_HW_LP_PAGES_LP_MP5_UP4_LP_MP5_UP4_PAGE_DATA_SHIFT 0 15591 15592 15593 /**************************************************************************** 15594 * AN_X4_HW_LP_PAGES :: lp_mp1024_up1 15595 */ 15596 /* AN_X4_HW_LP_PAGES :: lp_mp1024_up1 :: lp_mp1024_up1_page_data [15:00] */ 15597 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP1_LP_MP1024_UP1_PAGE_DATA_MASK 0xffff 15598 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP1_LP_MP1024_UP1_PAGE_DATA_ALIGN 0 15599 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP1_LP_MP1024_UP1_PAGE_DATA_BITS 16 15600 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP1_LP_MP1024_UP1_PAGE_DATA_SHIFT 0 15601 15602 15603 /**************************************************************************** 15604 * AN_X4_HW_LP_PAGES :: lp_mp1024_up2 15605 */ 15606 /* AN_X4_HW_LP_PAGES :: lp_mp1024_up2 :: lp_mp1024_up2_page_data [15:00] */ 15607 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP2_LP_MP1024_UP2_PAGE_DATA_MASK 0xffff 15608 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP2_LP_MP1024_UP2_PAGE_DATA_ALIGN 0 15609 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP2_LP_MP1024_UP2_PAGE_DATA_BITS 16 15610 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP2_LP_MP1024_UP2_PAGE_DATA_SHIFT 0 15611 15612 15613 /**************************************************************************** 15614 * AN_X4_HW_LP_PAGES :: lp_mp1024_up3 15615 */ 15616 /* AN_X4_HW_LP_PAGES :: lp_mp1024_up3 :: lp_mp1024_up3_page_data [15:00] */ 15617 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP3_LP_MP1024_UP3_PAGE_DATA_MASK 0xffff 15618 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP3_LP_MP1024_UP3_PAGE_DATA_ALIGN 0 15619 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP3_LP_MP1024_UP3_PAGE_DATA_BITS 16 15620 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP3_LP_MP1024_UP3_PAGE_DATA_SHIFT 0 15621 15622 15623 /**************************************************************************** 15624 * AN_X4_HW_LP_PAGES :: lp_mp1024_up4 15625 */ 15626 /* AN_X4_HW_LP_PAGES :: lp_mp1024_up4 :: lp_mp1024_up4_page_data [15:00] */ 15627 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP4_LP_MP1024_UP4_PAGE_DATA_MASK 0xffff 15628 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP4_LP_MP1024_UP4_PAGE_DATA_ALIGN 0 15629 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP4_LP_MP1024_UP4_PAGE_DATA_BITS 16 15630 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP4_LP_MP1024_UP4_PAGE_DATA_SHIFT 0 15631 15632 15633 /**************************************************************************** 15634 * AN_X4_HW_LP_PAGES :: lp_base_page1 15635 */ 15636 /* AN_X4_HW_LP_PAGES :: lp_base_page1 :: lp_base_page1_page_data [15:00] */ 15637 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE1_LP_BASE_PAGE1_PAGE_DATA_MASK 0xffff 15638 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE1_LP_BASE_PAGE1_PAGE_DATA_ALIGN 0 15639 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE1_LP_BASE_PAGE1_PAGE_DATA_BITS 16 15640 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE1_LP_BASE_PAGE1_PAGE_DATA_SHIFT 0 15641 15642 15643 /**************************************************************************** 15644 * AN_X4_HW_LP_PAGES :: lp_base_page2 15645 */ 15646 /* AN_X4_HW_LP_PAGES :: lp_base_page2 :: lp_base_page2_page_data [15:00] */ 15647 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE2_LP_BASE_PAGE2_PAGE_DATA_MASK 0xffff 15648 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE2_LP_BASE_PAGE2_PAGE_DATA_ALIGN 0 15649 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE2_LP_BASE_PAGE2_PAGE_DATA_BITS 16 15650 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE2_LP_BASE_PAGE2_PAGE_DATA_SHIFT 0 15651 15652 15653 /**************************************************************************** 15654 * AN_X4_HW_LP_PAGES :: lp_base_page3 15655 */ 15656 /* AN_X4_HW_LP_PAGES :: lp_base_page3 :: lp_base_page3_page_data [15:00] */ 15657 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE3_LP_BASE_PAGE3_PAGE_DATA_MASK 0xffff 15658 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE3_LP_BASE_PAGE3_PAGE_DATA_ALIGN 0 15659 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE3_LP_BASE_PAGE3_PAGE_DATA_BITS 16 15660 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE3_LP_BASE_PAGE3_PAGE_DATA_SHIFT 0 15661 15662 15663 /**************************************************************************** 15664 * TSC_WC4_TSC_USER4_AN_X4_SW_MANAGEMENT 15665 */ 15666 /**************************************************************************** 15667 * AN_X4_SW_MANAGEMENT :: ld_page_2 15668 */ 15669 /* AN_X4_SW_MANAGEMENT :: ld_page_2 :: ld_page_2_page_data [15:00] */ 15670 #define AN_X4_SW_MANAGEMENT_LD_PAGE_2_LD_PAGE_2_PAGE_DATA_MASK 0xffff 15671 #define AN_X4_SW_MANAGEMENT_LD_PAGE_2_LD_PAGE_2_PAGE_DATA_ALIGN 0 15672 #define AN_X4_SW_MANAGEMENT_LD_PAGE_2_LD_PAGE_2_PAGE_DATA_BITS 16 15673 #define AN_X4_SW_MANAGEMENT_LD_PAGE_2_LD_PAGE_2_PAGE_DATA_SHIFT 0 15674 15675 15676 /**************************************************************************** 15677 * AN_X4_SW_MANAGEMENT :: ld_page_1 15678 */ 15679 /* AN_X4_SW_MANAGEMENT :: ld_page_1 :: ld_page_1_page_data [15:00] */ 15680 #define AN_X4_SW_MANAGEMENT_LD_PAGE_1_LD_PAGE_1_PAGE_DATA_MASK 0xffff 15681 #define AN_X4_SW_MANAGEMENT_LD_PAGE_1_LD_PAGE_1_PAGE_DATA_ALIGN 0 15682 #define AN_X4_SW_MANAGEMENT_LD_PAGE_1_LD_PAGE_1_PAGE_DATA_BITS 16 15683 #define AN_X4_SW_MANAGEMENT_LD_PAGE_1_LD_PAGE_1_PAGE_DATA_SHIFT 0 15684 15685 15686 /**************************************************************************** 15687 * AN_X4_SW_MANAGEMENT :: ld_page_0 15688 */ 15689 /* AN_X4_SW_MANAGEMENT :: ld_page_0 :: ld_page_0_page_data [15:00] */ 15690 #define AN_X4_SW_MANAGEMENT_LD_PAGE_0_LD_PAGE_0_PAGE_DATA_MASK 0xffff 15691 #define AN_X4_SW_MANAGEMENT_LD_PAGE_0_LD_PAGE_0_PAGE_DATA_ALIGN 0 15692 #define AN_X4_SW_MANAGEMENT_LD_PAGE_0_LD_PAGE_0_PAGE_DATA_BITS 16 15693 #define AN_X4_SW_MANAGEMENT_LD_PAGE_0_LD_PAGE_0_PAGE_DATA_SHIFT 0 15694 15695 15696 /**************************************************************************** 15697 * AN_X4_SW_MANAGEMENT :: lp_page_2 15698 */ 15699 /* AN_X4_SW_MANAGEMENT :: lp_page_2 :: lp_page_2_page_data [15:00] */ 15700 #define AN_X4_SW_MANAGEMENT_LP_PAGE_2_LP_PAGE_2_PAGE_DATA_MASK 0xffff 15701 #define AN_X4_SW_MANAGEMENT_LP_PAGE_2_LP_PAGE_2_PAGE_DATA_ALIGN 0 15702 #define AN_X4_SW_MANAGEMENT_LP_PAGE_2_LP_PAGE_2_PAGE_DATA_BITS 16 15703 #define AN_X4_SW_MANAGEMENT_LP_PAGE_2_LP_PAGE_2_PAGE_DATA_SHIFT 0 15704 15705 15706 /**************************************************************************** 15707 * AN_X4_SW_MANAGEMENT :: lp_page_1 15708 */ 15709 /* AN_X4_SW_MANAGEMENT :: lp_page_1 :: lp_page_1_page_data [15:00] */ 15710 #define AN_X4_SW_MANAGEMENT_LP_PAGE_1_LP_PAGE_1_PAGE_DATA_MASK 0xffff 15711 #define AN_X4_SW_MANAGEMENT_LP_PAGE_1_LP_PAGE_1_PAGE_DATA_ALIGN 0 15712 #define AN_X4_SW_MANAGEMENT_LP_PAGE_1_LP_PAGE_1_PAGE_DATA_BITS 16 15713 #define AN_X4_SW_MANAGEMENT_LP_PAGE_1_LP_PAGE_1_PAGE_DATA_SHIFT 0 15714 15715 15716 /**************************************************************************** 15717 * AN_X4_SW_MANAGEMENT :: lp_page_0 15718 */ 15719 /* AN_X4_SW_MANAGEMENT :: lp_page_0 :: lp_page_0_page_data [15:00] */ 15720 #define AN_X4_SW_MANAGEMENT_LP_PAGE_0_LP_PAGE_0_PAGE_DATA_MASK 0xffff 15721 #define AN_X4_SW_MANAGEMENT_LP_PAGE_0_LP_PAGE_0_PAGE_DATA_ALIGN 0 15722 #define AN_X4_SW_MANAGEMENT_LP_PAGE_0_LP_PAGE_0_PAGE_DATA_BITS 16 15723 #define AN_X4_SW_MANAGEMENT_LP_PAGE_0_LP_PAGE_0_PAGE_DATA_SHIFT 0 15724 15725 15726 /**************************************************************************** 15727 * AN_X4_SW_MANAGEMENT :: sw_control_status 15728 */ 15729 /* AN_X4_SW_MANAGEMENT :: sw_control_status :: reserved0 [15:03] */ 15730 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_RESERVED0_MASK 0xfff8 15731 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_RESERVED0_ALIGN 0 15732 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_RESERVED0_BITS 13 15733 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_RESERVED0_SHIFT 3 15734 15735 /* AN_X4_SW_MANAGEMENT :: sw_control_status :: an_completed_sw [02:02] */ 15736 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_AN_COMPLETED_SW_MASK 0x0004 15737 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_AN_COMPLETED_SW_ALIGN 0 15738 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_AN_COMPLETED_SW_BITS 1 15739 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_AN_COMPLETED_SW_SHIFT 2 15740 15741 /* AN_X4_SW_MANAGEMENT :: sw_control_status :: ld_control_valid [01:01] */ 15742 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LD_CONTROL_VALID_MASK 0x0002 15743 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LD_CONTROL_VALID_ALIGN 0 15744 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LD_CONTROL_VALID_BITS 1 15745 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LD_CONTROL_VALID_SHIFT 1 15746 15747 /* AN_X4_SW_MANAGEMENT :: sw_control_status :: lp_status_valid [00:00] */ 15748 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LP_STATUS_VALID_MASK 0x0001 15749 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LP_STATUS_VALID_ALIGN 0 15750 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LP_STATUS_VALID_BITS 1 15751 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LP_STATUS_VALID_SHIFT 0 15752 15753 15754 /**************************************************************************** 15755 * AN_X4_SW_MANAGEMENT :: ld_control 15756 */ 15757 /* AN_X4_SW_MANAGEMENT :: ld_control :: reserved0 [15:02] */ 15758 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_RESERVED0_MASK 0xfffc 15759 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_RESERVED0_ALIGN 0 15760 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_RESERVED0_BITS 14 15761 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_RESERVED0_SHIFT 2 15762 15763 /* AN_X4_SW_MANAGEMENT :: ld_control :: SW_AN [01:01] */ 15764 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_AN_MASK 0x0002 15765 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_AN_ALIGN 0 15766 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_AN_BITS 1 15767 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_AN_SHIFT 1 15768 15769 /* AN_X4_SW_MANAGEMENT :: ld_control :: SW_HCD [00:00] */ 15770 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_HCD_MASK 0x0001 15771 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_HCD_ALIGN 0 15772 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_HCD_BITS 1 15773 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_HCD_SHIFT 0 15774 15775 15776 /**************************************************************************** 15777 * AN_X4_SW_MANAGEMENT :: an_page_sequencer_status 15778 */ 15779 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_sgmii_mode [15:15] */ 15780 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_SGMII_MODE_MASK 0x8000 15781 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_SGMII_MODE_ALIGN 0 15782 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_SGMII_MODE_BITS 1 15783 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_SGMII_MODE_SHIFT 15 15784 15785 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_hp_mode [14:14] */ 15786 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_HP_MODE_MASK 0x4000 15787 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_HP_MODE_ALIGN 0 15788 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_HP_MODE_BITS 1 15789 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_HP_MODE_SHIFT 14 15790 15791 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_sgmii_mismatch [13:13] */ 15792 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_SGMII_MISMATCH_MASK 0x2000 15793 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_SGMII_MISMATCH_ALIGN 0 15794 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_SGMII_MISMATCH_BITS 1 15795 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_SGMII_MISMATCH_SHIFT 13 15796 15797 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_bp [12:12] */ 15798 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_BP_MASK 0x1000 15799 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_BP_ALIGN 0 15800 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_BP_BITS 1 15801 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_BP_SHIFT 12 15802 15803 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_np [11:11] */ 15804 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_MASK 0x0800 15805 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_ALIGN 0 15806 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_BITS 1 15807 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_SHIFT 11 15808 15809 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_mp_null [10:10] */ 15810 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_NULL_MASK 0x0400 15811 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_NULL_ALIGN 0 15812 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_NULL_BITS 1 15813 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_NULL_SHIFT 10 15814 15815 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_mp_oui [09:09] */ 15816 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OUI_MASK 0x0200 15817 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OUI_ALIGN 0 15818 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OUI_BITS 1 15819 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OUI_SHIFT 9 15820 15821 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_mp_over1g [08:08] */ 15822 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OVER1G_MASK 0x0100 15823 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OVER1G_ALIGN 0 15824 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OVER1G_BITS 1 15825 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OVER1G_SHIFT 8 15826 15827 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_mp_mismatch [07:07] */ 15828 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_MISMATCH_MASK 0x0080 15829 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_MISMATCH_ALIGN 0 15830 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_MISMATCH_BITS 1 15831 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_MISMATCH_SHIFT 7 15832 15833 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_up_3 [06:06] */ 15834 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_3_MASK 0x0040 15835 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_3_ALIGN 0 15836 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_3_BITS 1 15837 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_3_SHIFT 6 15838 15839 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_up_oui_mismatch [05:05] */ 15840 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MISMATCH_MASK 0x0020 15841 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MISMATCH_ALIGN 0 15842 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MISMATCH_BITS 1 15843 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MISMATCH_SHIFT 5 15844 15845 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_up_oui_match [04:04] */ 15846 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MATCH_MASK 0x0010 15847 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MATCH_ALIGN 0 15848 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MATCH_BITS 1 15849 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MATCH_SHIFT 4 15850 15851 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_invalid_seq [03:03] */ 15852 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_INVALID_SEQ_MASK 0x0008 15853 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_INVALID_SEQ_ALIGN 0 15854 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_INVALID_SEQ_BITS 1 15855 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_INVALID_SEQ_SHIFT 3 15856 15857 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_np_toggle_err [02:02] */ 15858 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_TOGGLE_ERR_MASK 0x0004 15859 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_TOGGLE_ERR_ALIGN 0 15860 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_TOGGLE_ERR_BITS 1 15861 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_TOGGLE_ERR_SHIFT 2 15862 15863 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_cl37_complete [01:01] */ 15864 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL37_COMPLETE_MASK 0x0002 15865 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL37_COMPLETE_ALIGN 0 15866 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL37_COMPLETE_BITS 1 15867 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL37_COMPLETE_SHIFT 1 15868 15869 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_cl73_complete [00:00] */ 15870 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL73_COMPLETE_MASK 0x0001 15871 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL73_COMPLETE_ALIGN 0 15872 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL73_COMPLETE_BITS 1 15873 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL73_COMPLETE_SHIFT 0 15874 15875 15876 /**************************************************************************** 15877 * AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status 15878 */ 15879 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: reserved0 [15:14] */ 15880 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_RESERVED0_MASK 0xc000 15881 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_RESERVED0_ALIGN 0 15882 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_RESERVED0_BITS 2 15883 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_RESERVED0_SHIFT 14 15884 15885 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_next_page_wait [13:13] */ 15886 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_NEXT_PAGE_WAIT_MASK 0x2000 15887 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_NEXT_PAGE_WAIT_ALIGN 0 15888 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_NEXT_PAGE_WAIT_BITS 1 15889 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_NEXT_PAGE_WAIT_SHIFT 13 15890 15891 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_link_ok [12:12] */ 15892 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_LINK_OK_MASK 0x1000 15893 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_LINK_OK_ALIGN 0 15894 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_LINK_OK_BITS 1 15895 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_LINK_OK_SHIFT 12 15896 15897 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_an_good_check [11:11] */ 15898 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_GOOD_CHECK_MASK 0x0800 15899 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_GOOD_CHECK_ALIGN 0 15900 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_GOOD_CHECK_BITS 1 15901 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_GOOD_CHECK_SHIFT 11 15902 15903 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_restart [10:10] */ 15904 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_RESTART_MASK 0x0400 15905 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_RESTART_ALIGN 0 15906 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_RESTART_BITS 1 15907 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_RESTART_SHIFT 10 15908 15909 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_config_nonzero [09:09] */ 15910 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_NONZERO_MASK 0x0200 15911 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_NONZERO_ALIGN 0 15912 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_NONZERO_BITS 1 15913 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_NONZERO_SHIFT 9 15914 15915 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_consistency_mismatch [08:08] */ 15916 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONSISTENCY_MISMATCH_MASK 0x0100 15917 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONSISTENCY_MISMATCH_ALIGN 0 15918 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONSISTENCY_MISMATCH_BITS 1 15919 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONSISTENCY_MISMATCH_SHIFT 8 15920 15921 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_complete_ack [07:07] */ 15922 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_COMPLETE_ACK_MASK 0x0080 15923 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_COMPLETE_ACK_ALIGN 0 15924 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_COMPLETE_ACK_BITS 1 15925 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_COMPLETE_ACK_SHIFT 7 15926 15927 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_ack_detect [06:06] */ 15928 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ACK_DETECT_MASK 0x0040 15929 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ACK_DETECT_ALIGN 0 15930 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ACK_DETECT_BITS 1 15931 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ACK_DETECT_SHIFT 6 15932 15933 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_ability_detect [05:05] */ 15934 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ABILITY_DETECT_MASK 0x0020 15935 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ABILITY_DETECT_ALIGN 0 15936 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ABILITY_DETECT_BITS 1 15937 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ABILITY_DETECT_SHIFT 5 15938 15939 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_an_enable [04:04] */ 15940 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_ENABLE_MASK 0x0010 15941 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_ENABLE_ALIGN 0 15942 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_ENABLE_BITS 1 15943 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_ENABLE_SHIFT 4 15944 15945 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_error_state [03:03] */ 15946 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ERROR_STATE_MASK 0x0008 15947 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ERROR_STATE_ALIGN 0 15948 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ERROR_STATE_BITS 1 15949 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ERROR_STATE_SHIFT 3 15950 15951 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_disable_link [02:02] */ 15952 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_DISABLE_LINK_MASK 0x0004 15953 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_DISABLE_LINK_ALIGN 0 15954 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_DISABLE_LINK_BITS 1 15955 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_DISABLE_LINK_SHIFT 2 15956 15957 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_idle_detect [01:01] */ 15958 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_IDLE_DETECT_MASK 0x0002 15959 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_IDLE_DETECT_ALIGN 0 15960 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_IDLE_DETECT_BITS 1 15961 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_IDLE_DETECT_SHIFT 1 15962 15963 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_config_restart [00:00] */ 15964 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_RESTART_MASK 0x0001 15965 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_RESTART_ALIGN 0 15966 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_RESTART_BITS 1 15967 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_RESTART_SHIFT 0 15968 15969 15970 /**************************************************************************** 15971 * AN_X4_SW_MANAGEMENT :: an_page_decoder_status 15972 */ 15973 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: reserved0 [15:13] */ 15974 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_RESERVED0_MASK 0xe000 15975 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_RESERVED0_ALIGN 0 15976 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_RESERVED0_BITS 3 15977 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_RESERVED0_SHIFT 13 15978 15979 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_pulse_too_moderate [12:12] */ 15980 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_MODERATE_MASK 0x1000 15981 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_MODERATE_ALIGN 0 15982 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_MODERATE_BITS 1 15983 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_MODERATE_SHIFT 12 15984 15985 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_pulse_too_short [11:11] */ 15986 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_SHORT_MASK 0x0800 15987 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_SHORT_ALIGN 0 15988 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_SHORT_BITS 1 15989 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_SHORT_SHIFT 11 15990 15991 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_pulse_too_long [10:10] */ 15992 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_LONG_MASK 0x0400 15993 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_LONG_ALIGN 0 15994 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_LONG_BITS 1 15995 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_LONG_SHIFT 10 15996 15997 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_page_too_short [09:09] */ 15998 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_SHORT_MASK 0x0200 15999 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_SHORT_ALIGN 0 16000 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_SHORT_BITS 1 16001 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_SHORT_SHIFT 9 16002 16003 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_page_too_long [08:08] */ 16004 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_LONG_MASK 0x0100 16005 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_LONG_ALIGN 0 16006 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_LONG_BITS 1 16007 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_LONG_SHIFT 8 16008 16009 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_clk_trans_miss [07:07] */ 16010 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_CLK_TRANS_MISS_MASK 0x0080 16011 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_CLK_TRANS_MISS_ALIGN 0 16012 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_CLK_TRANS_MISS_BITS 1 16013 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_CLK_TRANS_MISS_SHIFT 7 16014 16015 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_mv_pair [06:06] */ 16016 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_MV_PAIR_MASK 0x0040 16017 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_MV_PAIR_ALIGN 0 16018 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_MV_PAIR_BITS 1 16019 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_MV_PAIR_SHIFT 6 16020 16021 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_page [05:05] */ 16022 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_MASK 0x0020 16023 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_ALIGN 0 16024 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_BITS 1 16025 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_SHIFT 5 16026 16027 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_rudi_idle [04:04] */ 16028 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_IDLE_MASK 0x0010 16029 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_IDLE_ALIGN 0 16030 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_IDLE_BITS 1 16031 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_IDLE_SHIFT 4 16032 16033 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_rudi_config [03:03] */ 16034 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_CONFIG_MASK 0x0008 16035 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_CONFIG_ALIGN 0 16036 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_CONFIG_BITS 1 16037 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_CONFIG_SHIFT 3 16038 16039 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_rudi_invalid [02:02] */ 16040 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_INVALID_MASK 0x0004 16041 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_INVALID_ALIGN 0 16042 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_INVALID_BITS 1 16043 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_INVALID_SHIFT 2 16044 16045 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_state [01:00] */ 16046 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_STATE_MASK 0x0003 16047 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_STATE_ALIGN 0 16048 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_STATE_BITS 2 16049 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_STATE_SHIFT 0 16050 16051 16052 /**************************************************************************** 16053 * AN_X4_SW_MANAGEMENT :: an_ability_resolution_status 16054 */ 16055 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: reserved0 [15:14] */ 16056 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_RESERVED0_MASK 0xc000 16057 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_RESERVED0_ALIGN 0 16058 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_RESERVED0_BITS 2 16059 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_RESERVED0_SHIFT 14 16060 16061 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_st_resolution_err [13:13] */ 16062 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_ST_RESOLUTION_ERR_MASK 0x2000 16063 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_ST_RESOLUTION_ERR_ALIGN 0 16064 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_ST_RESOLUTION_ERR_BITS 1 16065 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_ST_RESOLUTION_ERR_SHIFT 13 16066 16067 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_duplex [12:12] */ 16068 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_MASK 0x1000 16069 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_ALIGN 0 16070 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_BITS 1 16071 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_SHIFT 12 16072 16073 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_pause [11:10] */ 16074 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_MASK 0x0c00 16075 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_ALIGN 0 16076 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_BITS 2 16077 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_SHIFT 10 16078 16079 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_speed [09:04] */ 16080 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_MASK 0x03f0 16081 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_ALIGN 0 16082 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_BITS 6 16083 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SHIFT 4 16084 16085 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_fec [03:03] */ 16086 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_MASK 0x0008 16087 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_ALIGN 0 16088 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_BITS 1 16089 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_SHIFT 3 16090 16091 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_cl72 [02:02] */ 16092 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_MASK 0x0004 16093 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_ALIGN 0 16094 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_BITS 1 16095 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_SHIFT 2 16096 16097 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_higig2 [01:01] */ 16098 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_HIGIG2_MASK 0x0002 16099 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_HIGIG2_ALIGN 0 16100 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_HIGIG2_BITS 1 16101 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_HIGIG2_SHIFT 1 16102 16103 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_switch_to_cl37 [00:00] */ 16104 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SWITCH_TO_CL37_MASK 0x0001 16105 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SWITCH_TO_CL37_ALIGN 0 16106 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SWITCH_TO_CL37_BITS 1 16107 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SWITCH_TO_CL37_SHIFT 0 16108 16109 16110 /**************************************************************************** 16111 * AN_X4_SW_MANAGEMENT :: an_misc_status 16112 */ 16113 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: an_complete [15:15] */ 16114 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_COMPLETE_MASK 0x8000 16115 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_COMPLETE_ALIGN 0 16116 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_COMPLETE_BITS 1 16117 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_COMPLETE_SHIFT 15 16118 16119 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: an_retry_count [14:09] */ 16120 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_RETRY_COUNT_MASK 0x7e00 16121 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_RETRY_COUNT_ALIGN 0 16122 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_RETRY_COUNT_BITS 6 16123 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_RETRY_COUNT_SHIFT 9 16124 16125 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: remote_fault_in_base_page [08:08] */ 16126 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_REMOTE_FAULT_IN_BASE_PAGE_MASK 0x0100 16127 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_REMOTE_FAULT_IN_BASE_PAGE_ALIGN 0 16128 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_REMOTE_FAULT_IN_BASE_PAGE_BITS 1 16129 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_REMOTE_FAULT_IN_BASE_PAGE_SHIFT 8 16130 16131 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: pd_completed [07:07] */ 16132 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_COMPLETED_MASK 0x0080 16133 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_COMPLETED_ALIGN 0 16134 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_COMPLETED_BITS 1 16135 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_COMPLETED_SHIFT 7 16136 16137 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: an_active [06:06] */ 16138 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_ACTIVE_MASK 0x0040 16139 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_ACTIVE_ALIGN 0 16140 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_ACTIVE_BITS 1 16141 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_ACTIVE_SHIFT 6 16142 16143 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: an_fail_count [05:02] */ 16144 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_FAIL_COUNT_MASK 0x003c 16145 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_FAIL_COUNT_ALIGN 0 16146 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_FAIL_COUNT_BITS 4 16147 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_FAIL_COUNT_SHIFT 2 16148 16149 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: pd_in_progress [01:01] */ 16150 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_IN_PROGRESS_MASK 0x0002 16151 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_IN_PROGRESS_ALIGN 0 16152 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_IN_PROGRESS_BITS 1 16153 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_IN_PROGRESS_SHIFT 1 16154 16155 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: pd_hcd_kx4_or_kx [00:00] */ 16156 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_HCD_KX4_OR_KX_MASK 0x0001 16157 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_HCD_KX4_OR_KX_ALIGN 0 16158 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_HCD_KX4_OR_KX_BITS 1 16159 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_HCD_KX4_OR_KX_SHIFT 0 16160 16161 16162 /**************************************************************************** 16163 * AN_X4_SW_MANAGEMENT :: tla_sequencer_status 16164 */ 16165 /* AN_X4_SW_MANAGEMENT :: tla_sequencer_status :: reserved0 [15:11] */ 16166 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_RESERVED0_MASK 0xf800 16167 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_RESERVED0_ALIGN 0 16168 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_RESERVED0_BITS 5 16169 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_RESERVED0_SHIFT 11 16170 16171 /* AN_X4_SW_MANAGEMENT :: tla_sequencer_status :: tla_ln_sequencer_fsm_status [10:00] */ 16172 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_MASK 0x07ff 16173 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_ALIGN 0 16174 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_BITS 11 16175 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_SHIFT 0 16176 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_INIT 1 16177 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_RESTART_AN 2 16178 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_WAIT4RES 4 16179 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_RESET_PIPELINE 8 16180 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_CONFIG_PIPELINE 16 16181 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_IGNORE_LINK 32 16182 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_AN_GOOD_CHECK 64 16183 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_AN_GOOD 128 16184 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_AN_DEAD 256 16185 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_PLL_RESET 512 16186 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_SET_PD_HCD 1024 16187 16188 16189 /**************************************************************************** 16190 * AN_X4_SW_MANAGEMENT :: an_seq_unexpected_page 16191 */ 16192 /* AN_X4_SW_MANAGEMENT :: an_seq_unexpected_page :: seq_unexpected_page [15:00] */ 16193 #define AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGE_SEQ_UNEXPECTED_PAGE_MASK 0xffff 16194 #define AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGE_SEQ_UNEXPECTED_PAGE_ALIGN 0 16195 #define AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGE_SEQ_UNEXPECTED_PAGE_BITS 16 16196 #define AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGE_SEQ_UNEXPECTED_PAGE_SHIFT 0 16197 16198 16199 /**************************************************************************** 16200 * TSC_WC4_TSC_USER4_Dsc1b0 16201 */ 16202 /**************************************************************************** 16203 * Dsc1b0 :: cdr_ctrl0 16204 */ 16205 /* Dsc1b0 :: cdr_ctrl0 :: cdros_xfi_integ_sat_sel [15:15] */ 16206 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_MASK 0x8000 16207 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_ALIGN 0 16208 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_BITS 1 16209 #define DSC1B0_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_SHIFT 15 16210 16211 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_m1_slicer_only [14:14] */ 16212 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_MASK 0x4000 16213 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_ALIGN 0 16214 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_BITS 1 16215 #define DSC1B0_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_SHIFT 14 16216 16217 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_p1_slicer_only [13:13] */ 16218 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_MASK 0x2000 16219 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_ALIGN 0 16220 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_BITS 1 16221 #define DSC1B0_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_SHIFT 13 16222 16223 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */ 16224 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_MASK 0x1000 16225 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 16226 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_BITS 1 16227 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_SHIFT 12 16228 16229 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */ 16230 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0800 16231 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 16232 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 16233 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 11 16234 16235 /* Dsc1b0 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */ 16236 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_MASK 0x0400 16237 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN 0 16238 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_BITS 1 16239 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT 10 16240 16241 /* Dsc1b0 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */ 16242 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_MASK 0x0200 16243 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN 0 16244 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_BITS 1 16245 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT 9 16246 16247 /* Dsc1b0 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */ 16248 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK 0x0180 16249 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN 0 16250 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS 2 16251 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT 7 16252 16253 /* Dsc1b0 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */ 16254 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK 0x0040 16255 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN 0 16256 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS 1 16257 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT 6 16258 16259 /* Dsc1b0 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */ 16260 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK 0x0020 16261 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN 0 16262 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS 1 16263 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT 5 16264 16265 /* Dsc1b0 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */ 16266 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK 0x0010 16267 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN 0 16268 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS 1 16269 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT 4 16270 16271 /* Dsc1b0 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */ 16272 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK 0x0008 16273 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN 0 16274 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS 1 16275 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT 3 16276 16277 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */ 16278 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK 0x0004 16279 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN 0 16280 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS 1 16281 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT 2 16282 16283 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_en [01:01] */ 16284 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_MASK 0x0002 16285 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_ALIGN 0 16286 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_BITS 1 16287 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_SHIFT 1 16288 16289 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */ 16290 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK 0x0001 16291 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 16292 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS 1 16293 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT 0 16294 16295 16296 /**************************************************************************** 16297 * Dsc1b0 :: cdr_ctrl1 16298 */ 16299 /* Dsc1b0 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */ 16300 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 16301 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 16302 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 16 16303 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 16304 16305 16306 /**************************************************************************** 16307 * Dsc1b0 :: cdr_ctrl2 16308 */ 16309 /* Dsc1b0 :: cdr_ctrl2 :: reserved0 [15:10] */ 16310 #define DSC1B0_CDR_CTRL2_RESERVED0_MASK 0xfc00 16311 #define DSC1B0_CDR_CTRL2_RESERVED0_ALIGN 0 16312 #define DSC1B0_CDR_CTRL2_RESERVED0_BITS 6 16313 #define DSC1B0_CDR_CTRL2_RESERVED0_SHIFT 10 16314 16315 /* Dsc1b0 :: cdr_ctrl2 :: cdros_phase_err_offset [09:06] */ 16316 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_MASK 0x03c0 16317 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_ALIGN 0 16318 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_BITS 4 16319 #define DSC1B0_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_SHIFT 6 16320 16321 /* Dsc1b0 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */ 16322 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK 0x003f 16323 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN 0 16324 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS 6 16325 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT 0 16326 16327 16328 /**************************************************************************** 16329 * Dsc1b0 :: pi_ctrl0 16330 */ 16331 /* Dsc1b0 :: pi_ctrl0 :: pi_cw_rst [15:15] */ 16332 #define DSC1B0_PI_CTRL0_PI_CW_RST_MASK 0x8000 16333 #define DSC1B0_PI_CTRL0_PI_CW_RST_ALIGN 0 16334 #define DSC1B0_PI_CTRL0_PI_CW_RST_BITS 1 16335 #define DSC1B0_PI_CTRL0_PI_CW_RST_SHIFT 15 16336 16337 /* Dsc1b0 :: pi_ctrl0 :: interp_ctrl_dsel [14:12] */ 16338 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_MASK 0x7000 16339 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_ALIGN 0 16340 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_BITS 3 16341 #define DSC1B0_PI_CTRL0_INTERP_CTRL_DSEL_SHIFT 12 16342 16343 /* Dsc1b0 :: pi_ctrl0 :: interp_ctrl_cap [11:11] */ 16344 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_MASK 0x0800 16345 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_ALIGN 0 16346 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_BITS 1 16347 #define DSC1B0_PI_CTRL0_INTERP_CTRL_CAP_SHIFT 11 16348 16349 /* Dsc1b0 :: pi_ctrl0 :: reserved0 [10:02] */ 16350 #define DSC1B0_PI_CTRL0_RESERVED0_MASK 0x07fc 16351 #define DSC1B0_PI_CTRL0_RESERVED0_ALIGN 0 16352 #define DSC1B0_PI_CTRL0_RESERVED0_BITS 9 16353 #define DSC1B0_PI_CTRL0_RESERVED0_SHIFT 2 16354 16355 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_invert [01:01] */ 16356 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0002 16357 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 16358 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_BITS 1 16359 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_SHIFT 1 16360 16361 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 16362 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 16363 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 16364 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 16365 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 16366 16367 16368 /**************************************************************************** 16369 * Dsc1b0 :: pi_ctrl1 16370 */ 16371 /* Dsc1b0 :: pi_ctrl1 :: reserved0 [15:12] */ 16372 #define DSC1B0_PI_CTRL1_RESERVED0_MASK 0xf000 16373 #define DSC1B0_PI_CTRL1_RESERVED0_ALIGN 0 16374 #define DSC1B0_PI_CTRL1_RESERVED0_BITS 4 16375 #define DSC1B0_PI_CTRL1_RESERVED0_SHIFT 12 16376 16377 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_step_dir [11:11] */ 16378 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_MASK 0x0800 16379 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_ALIGN 0 16380 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_BITS 1 16381 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_DIR_SHIFT 11 16382 16383 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_step [10:09] */ 16384 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_MASK 0x0600 16385 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_ALIGN 0 16386 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_BITS 2 16387 #define DSC1B0_PI_CTRL1_PI_PHASE_STEP_SHIFT 9 16388 16389 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_delta [08:04] */ 16390 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_MASK 0x01f0 16391 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_ALIGN 0 16392 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_BITS 5 16393 #define DSC1B0_PI_CTRL1_PI_PHASE_DELTA_SHIFT 4 16394 16395 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_strobe [03:03] */ 16396 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_MASK 0x0008 16397 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_ALIGN 0 16398 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_BITS 1 16399 #define DSC1B0_PI_CTRL1_PI_PHASE_STROBE_SHIFT 3 16400 16401 /* Dsc1b0 :: pi_ctrl1 :: pi_phase_rotate_override [02:02] */ 16402 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_MASK 0x0004 16403 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_ALIGN 0 16404 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_BITS 1 16405 #define DSC1B0_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_SHIFT 2 16406 16407 /* Dsc1b0 :: pi_ctrl1 :: pi_clk90_offset_override [01:01] */ 16408 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0002 16409 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 16410 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_BITS 1 16411 #define DSC1B0_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_SHIFT 1 16412 16413 /* Dsc1b0 :: pi_ctrl1 :: pi_dual_phase_override [00:00] */ 16414 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_MASK 0x0001 16415 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 16416 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_BITS 1 16417 #define DSC1B0_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_SHIFT 0 16418 16419 16420 /**************************************************************************** 16421 * Dsc1b0 :: dfe_vga_ctrl0 16422 */ 16423 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_abs_sum_max [15:09] */ 16424 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_MASK 0xfe00 16425 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_ALIGN 0 16426 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_BITS 7 16427 #define DSC1B0_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_SHIFT 9 16428 16429 /* Dsc1b0 :: dfe_vga_ctrl0 :: random_tapsel_disable [08:08] */ 16430 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_MASK 0x0100 16431 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_ALIGN 0 16432 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_BITS 1 16433 #define DSC1B0_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_SHIFT 8 16434 16435 /* Dsc1b0 :: dfe_vga_ctrl0 :: cor_neg2_en [07:07] */ 16436 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_MASK 0x0080 16437 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_ALIGN 0 16438 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_BITS 1 16439 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG2_EN_SHIFT 7 16440 16441 /* Dsc1b0 :: dfe_vga_ctrl0 :: cor_neg1_en [06:06] */ 16442 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_MASK 0x0040 16443 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_ALIGN 0 16444 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_BITS 1 16445 #define DSC1B0_DFE_VGA_CTRL0_COR_NEG1_EN_SHIFT 6 16446 16447 /* Dsc1b0 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */ 16448 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_MASK 0x0020 16449 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN 0 16450 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_BITS 1 16451 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT 5 16452 16453 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */ 16454 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_MASK 0x0010 16455 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN 0 16456 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_BITS 1 16457 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT 4 16458 16459 /* Dsc1b0 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */ 16460 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0008 16461 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 16462 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 16463 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 3 16464 16465 /* Dsc1b0 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */ 16466 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0004 16467 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 16468 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 16469 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 2 16470 16471 /* Dsc1b0 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */ 16472 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_MASK 0x0002 16473 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN 0 16474 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_BITS 1 16475 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT 1 16476 16477 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */ 16478 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0001 16479 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 16480 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 16481 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 0 16482 16483 16484 /**************************************************************************** 16485 * Dsc1b0 :: dfe_vga_ctrl1 16486 */ 16487 /* Dsc1b0 :: dfe_vga_ctrl1 :: reserved0 [15:14] */ 16488 #define DSC1B0_DFE_VGA_CTRL1_RESERVED0_MASK 0xc000 16489 #define DSC1B0_DFE_VGA_CTRL1_RESERVED0_ALIGN 0 16490 #define DSC1B0_DFE_VGA_CTRL1_RESERVED0_BITS 2 16491 #define DSC1B0_DFE_VGA_CTRL1_RESERVED0_SHIFT 14 16492 16493 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_llms_update_count_sel [13:12] */ 16494 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_MASK 0x3000 16495 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_ALIGN 0 16496 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_BITS 2 16497 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_SHIFT 12 16498 16499 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_llms_en [11:11] */ 16500 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_MASK 0x0800 16501 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_ALIGN 0 16502 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_BITS 1 16503 #define DSC1B0_DFE_VGA_CTRL1_DFE_LLMS_EN_SHIFT 11 16504 16505 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_cdros_qphase_mult_en [10:10] */ 16506 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_MASK 0x0400 16507 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_ALIGN 0 16508 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_BITS 1 16509 #define DSC1B0_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_SHIFT 10 16510 16511 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_tap_2_dcd [09:06] */ 16512 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_MASK 0x03c0 16513 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_ALIGN 0 16514 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_BITS 4 16515 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_2_DCD_SHIFT 6 16516 16517 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_tap_1_do [05:03] */ 16518 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_MASK 0x0038 16519 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_ALIGN 0 16520 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_BITS 3 16521 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DO_SHIFT 3 16522 16523 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_tap_1_de [02:00] */ 16524 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_MASK 0x0007 16525 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_ALIGN 0 16526 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_BITS 3 16527 #define DSC1B0_DFE_VGA_CTRL1_DFE_TAP_1_DE_SHIFT 0 16528 16529 16530 /**************************************************************************** 16531 * Dsc1b0 :: dfe_vga_ctrl2 16532 */ 16533 /* Dsc1b0 :: dfe_vga_ctrl2 :: vga3_override_val [15:12] */ 16534 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_MASK 0xf000 16535 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_ALIGN 0 16536 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_BITS 4 16537 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_SHIFT 12 16538 16539 /* Dsc1b0 :: dfe_vga_ctrl2 :: vga3_override_en [11:11] */ 16540 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_MASK 0x0800 16541 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_ALIGN 0 16542 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_BITS 1 16543 #define DSC1B0_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_SHIFT 11 16544 16545 /* Dsc1b0 :: dfe_vga_ctrl2 :: reserved0 [10:10] */ 16546 #define DSC1B0_DFE_VGA_CTRL2_RESERVED0_MASK 0x0400 16547 #define DSC1B0_DFE_VGA_CTRL2_RESERVED0_ALIGN 0 16548 #define DSC1B0_DFE_VGA_CTRL2_RESERVED0_BITS 1 16549 #define DSC1B0_DFE_VGA_CTRL2_RESERVED0_SHIFT 10 16550 16551 /* Dsc1b0 :: dfe_vga_ctrl2 :: dfe_vga_write_tapsel [09:07] */ 16552 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_MASK 0x0380 16553 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_ALIGN 0 16554 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_BITS 3 16555 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_SHIFT 7 16556 16557 /* Dsc1b0 :: dfe_vga_ctrl2 :: dfe_vga_write_val [06:01] */ 16558 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_MASK 0x007e 16559 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_ALIGN 0 16560 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_BITS 6 16561 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_SHIFT 1 16562 16563 /* Dsc1b0 :: dfe_vga_ctrl2 :: dfe_vga_write_en [00:00] */ 16564 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_MASK 0x0001 16565 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_ALIGN 0 16566 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_BITS 1 16567 #define DSC1B0_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_SHIFT 0 16568 16569 16570 /**************************************************************************** 16571 * Dsc1b0 :: dfe_vga_ctrl3 16572 */ 16573 /* Dsc1b0 :: dfe_vga_ctrl3 :: trnsum_otap_en [15:08] */ 16574 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_MASK 0xff00 16575 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_ALIGN 0 16576 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_BITS 8 16577 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_SHIFT 8 16578 16579 /* Dsc1b0 :: dfe_vga_ctrl3 :: trnsum_etap_en [07:00] */ 16580 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_MASK 0x00ff 16581 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_ALIGN 0 16582 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_BITS 8 16583 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_SHIFT 0 16584 16585 16586 /**************************************************************************** 16587 * Dsc1b0 :: dfe_vga_ctrl4 16588 */ 16589 /* Dsc1b0 :: dfe_vga_ctrl4 :: trnsum_otap_sign [15:08] */ 16590 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_MASK 0xff00 16591 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_ALIGN 0 16592 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_BITS 8 16593 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_SHIFT 8 16594 16595 /* Dsc1b0 :: dfe_vga_ctrl4 :: trnsum_etap_sign [07:00] */ 16596 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_MASK 0x00ff 16597 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_ALIGN 0 16598 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_BITS 8 16599 #define DSC1B0_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_SHIFT 0 16600 16601 16602 /**************************************************************************** 16603 * Dsc1b0 :: dfe_vga_ctrl5 16604 */ 16605 /* Dsc1b0 :: dfe_vga_ctrl5 :: reserved0 [15:10] */ 16606 #define DSC1B0_DFE_VGA_CTRL5_RESERVED0_MASK 0xfc00 16607 #define DSC1B0_DFE_VGA_CTRL5_RESERVED0_ALIGN 0 16608 #define DSC1B0_DFE_VGA_CTRL5_RESERVED0_BITS 6 16609 #define DSC1B0_DFE_VGA_CTRL5_RESERVED0_SHIFT 10 16610 16611 /* Dsc1b0 :: dfe_vga_ctrl5 :: vga_cor_sel_e [09:05] */ 16612 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_MASK 0x03e0 16613 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_ALIGN 0 16614 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_BITS 5 16615 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_E_SHIFT 5 16616 16617 /* Dsc1b0 :: dfe_vga_ctrl5 :: vga_cor_sel_o [04:00] */ 16618 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_MASK 0x001f 16619 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_ALIGN 0 16620 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_BITS 5 16621 #define DSC1B0_DFE_VGA_CTRL5_VGA_COR_SEL_O_SHIFT 0 16622 16623 16624 /**************************************************************************** 16625 * Dsc1b0 :: dfe_vga_ctrl6 16626 */ 16627 /* Dsc1b0 :: dfe_vga_ctrl6 :: reserved0 [15:10] */ 16628 #define DSC1B0_DFE_VGA_CTRL6_RESERVED0_MASK 0xfc00 16629 #define DSC1B0_DFE_VGA_CTRL6_RESERVED0_ALIGN 0 16630 #define DSC1B0_DFE_VGA_CTRL6_RESERVED0_BITS 6 16631 #define DSC1B0_DFE_VGA_CTRL6_RESERVED0_SHIFT 10 16632 16633 /* Dsc1b0 :: dfe_vga_ctrl6 :: dfe_cor_sel_e [09:05] */ 16634 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_MASK 0x03e0 16635 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_ALIGN 0 16636 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_BITS 5 16637 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_E_SHIFT 5 16638 16639 /* Dsc1b0 :: dfe_vga_ctrl6 :: dfe_cor_sel_o [04:00] */ 16640 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_MASK 0x001f 16641 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_ALIGN 0 16642 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_BITS 5 16643 #define DSC1B0_DFE_VGA_CTRL6_DFE_COR_SEL_O_SHIFT 0 16644 16645 16646 /**************************************************************************** 16647 * Dsc1b0 :: dfe_vga_ctrl7 16648 */ 16649 /* Dsc1b0 :: dfe_vga_ctrl7 :: disable_cl72_rcving_ctrl_frame [15:15] */ 16650 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_MASK 0x8000 16651 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_ALIGN 0 16652 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_BITS 1 16653 #define DSC1B0_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_SHIFT 15 16654 16655 /* Dsc1b0 :: dfe_vga_ctrl7 :: pattern [14:08] */ 16656 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_MASK 0x7f00 16657 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_ALIGN 0 16658 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BITS 7 16659 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_SHIFT 8 16660 16661 /* Dsc1b0 :: dfe_vga_ctrl7 :: pattern_bit_en [07:01] */ 16662 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_MASK 0x00fe 16663 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_ALIGN 0 16664 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_BITS 7 16665 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_BIT_EN_SHIFT 1 16666 16667 /* Dsc1b0 :: dfe_vga_ctrl7 :: pattern_en [00:00] */ 16668 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_MASK 0x0001 16669 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_ALIGN 0 16670 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_BITS 1 16671 #define DSC1B0_DFE_VGA_CTRL7_PATTERN_EN_SHIFT 0 16672 16673 16674 /**************************************************************************** 16675 * Dsc1b0 :: dsc_diag_ctrl0 16676 */ 16677 /* Dsc1b0 :: dsc_diag_ctrl0 :: reserved0 [15:12] */ 16678 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED0_MASK 0xf000 16679 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED0_ALIGN 0 16680 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED0_BITS 4 16681 #define DSC1B0_DSC_DIAG_CTRL0_RESERVED0_SHIFT 12 16682 16683 /* Dsc1b0 :: dsc_diag_ctrl0 :: osx2_diag_ctrl [11:11] */ 16684 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_MASK 0x0800 16685 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_ALIGN 0 16686 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_BITS 1 16687 #define DSC1B0_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_SHIFT 11 16688 16689 /* Dsc1b0 :: dsc_diag_ctrl0 :: voffset [10:07] */ 16690 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_MASK 0x0780 16691 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_ALIGN 0 16692 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_BITS 4 16693 #define DSC1B0_DSC_DIAG_CTRL0_VOFFSET_SHIFT 7 16694 16695 /* Dsc1b0 :: dsc_diag_ctrl0 :: hoffset [06:01] */ 16696 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_MASK 0x007e 16697 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_ALIGN 0 16698 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_BITS 6 16699 #define DSC1B0_DSC_DIAG_CTRL0_HOFFSET_SHIFT 1 16700 16701 /* Dsc1b0 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */ 16702 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK 0x0001 16703 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN 0 16704 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS 1 16705 #define DSC1B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT 0 16706 16707 16708 /**************************************************************************** 16709 * Dsc1b0 :: uC_ctrl 16710 */ 16711 /* Dsc1b0 :: uC_ctrl :: supplement_info [15:08] */ 16712 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_MASK 0xff00 16713 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_ALIGN 0 16714 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_BITS 8 16715 #define DSC1B0_UC_CTRL_SUPPLEMENT_INFO_SHIFT 8 16716 16717 /* Dsc1b0 :: uC_ctrl :: ready_for_cmd [07:07] */ 16718 #define DSC1B0_UC_CTRL_READY_FOR_CMD_MASK 0x0080 16719 #define DSC1B0_UC_CTRL_READY_FOR_CMD_ALIGN 0 16720 #define DSC1B0_UC_CTRL_READY_FOR_CMD_BITS 1 16721 #define DSC1B0_UC_CTRL_READY_FOR_CMD_SHIFT 7 16722 16723 /* Dsc1b0 :: uC_ctrl :: error_found [06:06] */ 16724 #define DSC1B0_UC_CTRL_ERROR_FOUND_MASK 0x0040 16725 #define DSC1B0_UC_CTRL_ERROR_FOUND_ALIGN 0 16726 #define DSC1B0_UC_CTRL_ERROR_FOUND_BITS 1 16727 #define DSC1B0_UC_CTRL_ERROR_FOUND_SHIFT 6 16728 16729 /* Dsc1b0 :: uC_ctrl :: cmd_info [05:04] */ 16730 #define DSC1B0_UC_CTRL_CMD_INFO_MASK 0x0030 16731 #define DSC1B0_UC_CTRL_CMD_INFO_ALIGN 0 16732 #define DSC1B0_UC_CTRL_CMD_INFO_BITS 2 16733 #define DSC1B0_UC_CTRL_CMD_INFO_SHIFT 4 16734 16735 /* Dsc1b0 :: uC_ctrl :: gp_uC_req [03:00] */ 16736 #define DSC1B0_UC_CTRL_GP_UC_REQ_MASK 0x000f 16737 #define DSC1B0_UC_CTRL_GP_UC_REQ_ALIGN 0 16738 #define DSC1B0_UC_CTRL_GP_UC_REQ_BITS 4 16739 #define DSC1B0_UC_CTRL_GP_UC_REQ_SHIFT 0 16740 16741 16742 /**************************************************************************** 16743 * TSC_WC4_TSC_USER4_Dsc2b0 16744 */ 16745 /**************************************************************************** 16746 * Dsc2b0 :: acq_sm_ctrl0 16747 */ 16748 /* Dsc2b0 :: acq_sm_ctrl0 :: cl72_timer_en [15:15] */ 16749 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_MASK 0x8000 16750 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_ALIGN 0 16751 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_BITS 1 16752 #define DSC2B0_ACQ_SM_CTRL0_CL72_TIMER_EN_SHIFT 15 16753 16754 /* Dsc2b0 :: acq_sm_ctrl0 :: acq2_timeout [14:10] */ 16755 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_MASK 0x7c00 16756 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_ALIGN 0 16757 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_BITS 5 16758 #define DSC2B0_ACQ_SM_CTRL0_ACQ2_TIMEOUT_SHIFT 10 16759 16760 /* Dsc2b0 :: acq_sm_ctrl0 :: acq1_timeout [09:05] */ 16761 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_MASK 0x03e0 16762 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_ALIGN 0 16763 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_BITS 5 16764 #define DSC2B0_ACQ_SM_CTRL0_ACQ1_TIMEOUT_SHIFT 5 16765 16766 /* Dsc2b0 :: acq_sm_ctrl0 :: acqcdr_timeout [04:00] */ 16767 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_MASK 0x001f 16768 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_ALIGN 0 16769 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_BITS 5 16770 #define DSC2B0_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_SHIFT 0 16771 16772 16773 /**************************************************************************** 16774 * Dsc2b0 :: acq_sm_ctrl1 16775 */ 16776 /* Dsc2b0 :: acq_sm_ctrl1 :: acqvga_timeout [15:11] */ 16777 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_MASK 0xf800 16778 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_ALIGN 0 16779 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_BITS 5 16780 #define DSC2B0_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_SHIFT 11 16781 16782 /* Dsc2b0 :: acq_sm_ctrl1 :: bypass_os_integ_xfer [10:10] */ 16783 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_MASK 0x0400 16784 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_ALIGN 0 16785 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_BITS 1 16786 #define DSC2B0_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_SHIFT 10 16787 16788 /* Dsc2b0 :: acq_sm_ctrl1 :: dfe_frzval [09:05] */ 16789 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_MASK 0x03e0 16790 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_ALIGN 0 16791 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_BITS 5 16792 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRZVAL_SHIFT 5 16793 16794 /* Dsc2b0 :: acq_sm_ctrl1 :: dfe_frcfrz [04:04] */ 16795 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_MASK 0x0010 16796 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_ALIGN 0 16797 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_BITS 1 16798 #define DSC2B0_ACQ_SM_CTRL1_DFE_FRCFRZ_SHIFT 4 16799 16800 /* Dsc2b0 :: acq_sm_ctrl1 :: vga_frzval [03:03] */ 16801 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_MASK 0x0008 16802 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_ALIGN 0 16803 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_BITS 1 16804 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRZVAL_SHIFT 3 16805 16806 /* Dsc2b0 :: acq_sm_ctrl1 :: vga_frcfrz [02:02] */ 16807 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_MASK 0x0004 16808 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_ALIGN 0 16809 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_BITS 1 16810 #define DSC2B0_ACQ_SM_CTRL1_VGA_FRCFRZ_SHIFT 2 16811 16812 /* Dsc2b0 :: acq_sm_ctrl1 :: dsc_clr_val [01:01] */ 16813 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_MASK 0x0002 16814 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_ALIGN 0 16815 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_BITS 1 16816 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_VAL_SHIFT 1 16817 16818 /* Dsc2b0 :: acq_sm_ctrl1 :: dsc_clr_frc [00:00] */ 16819 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_MASK 0x0001 16820 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_ALIGN 0 16821 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_BITS 1 16822 #define DSC2B0_ACQ_SM_CTRL1_DSC_CLR_FRC_SHIFT 0 16823 16824 16825 /**************************************************************************** 16826 * Dsc2b0 :: acq_sm_ctrl2 16827 */ 16828 /* Dsc2b0 :: acq_sm_ctrl2 :: sw_handover [15:15] */ 16829 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_MASK 0x8000 16830 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_ALIGN 0 16831 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_BITS 1 16832 #define DSC2B0_ACQ_SM_CTRL2_SW_HANDOVER_SHIFT 15 16833 16834 /* Dsc2b0 :: acq_sm_ctrl2 :: eee_acq_2_timeout [14:10] */ 16835 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_MASK 0x7c00 16836 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_ALIGN 0 16837 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_BITS 5 16838 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_SHIFT 10 16839 16840 /* Dsc2b0 :: acq_sm_ctrl2 :: eee_acq_phase_timeout [09:05] */ 16841 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_MASK 0x03e0 16842 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_ALIGN 0 16843 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_BITS 5 16844 #define DSC2B0_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_SHIFT 5 16845 16846 /* Dsc2b0 :: acq_sm_ctrl2 :: skip_acq [04:04] */ 16847 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_MASK 0x0010 16848 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_ALIGN 0 16849 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_BITS 1 16850 #define DSC2B0_ACQ_SM_CTRL2_SKIP_ACQ_SHIFT 4 16851 16852 /* Dsc2b0 :: acq_sm_ctrl2 :: train2_req [03:03] */ 16853 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_MASK 0x0008 16854 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_ALIGN 0 16855 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_BITS 1 16856 #define DSC2B0_ACQ_SM_CTRL2_TRAIN2_REQ_SHIFT 3 16857 16858 /* Dsc2b0 :: acq_sm_ctrl2 :: train1_req [02:02] */ 16859 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_MASK 0x0004 16860 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_ALIGN 0 16861 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_BITS 1 16862 #define DSC2B0_ACQ_SM_CTRL2_TRAIN1_REQ_SHIFT 2 16863 16864 /* Dsc2b0 :: acq_sm_ctrl2 :: soft_ack [01:01] */ 16865 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_MASK 0x0002 16866 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_ALIGN 0 16867 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_BITS 1 16868 #define DSC2B0_ACQ_SM_CTRL2_SOFT_ACK_SHIFT 1 16869 16870 /* Dsc2b0 :: acq_sm_ctrl2 :: train_mode_en [00:00] */ 16871 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_MASK 0x0001 16872 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_ALIGN 0 16873 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_BITS 1 16874 #define DSC2B0_ACQ_SM_CTRL2_TRAIN_MODE_EN_SHIFT 0 16875 16876 16877 /**************************************************************************** 16878 * Dsc2b0 :: acq_sm_ctrl3 16879 */ 16880 /* Dsc2b0 :: acq_sm_ctrl3 :: pause_level_trigger_en [15:15] */ 16881 #define DSC2B0_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_MASK 0x8000 16882 #define DSC2B0_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_ALIGN 0 16883 #define DSC2B0_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_BITS 1 16884 #define DSC2B0_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_SHIFT 15 16885 16886 /* Dsc2b0 :: acq_sm_ctrl3 :: reserved0 [14:14] */ 16887 #define DSC2B0_ACQ_SM_CTRL3_RESERVED0_MASK 0x4000 16888 #define DSC2B0_ACQ_SM_CTRL3_RESERVED0_ALIGN 0 16889 #define DSC2B0_ACQ_SM_CTRL3_RESERVED0_BITS 1 16890 #define DSC2B0_ACQ_SM_CTRL3_RESERVED0_SHIFT 14 16891 16892 /* Dsc2b0 :: acq_sm_ctrl3 :: os_dfe_en [13:13] */ 16893 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_MASK 0x2000 16894 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_ALIGN 0 16895 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_BITS 1 16896 #define DSC2B0_ACQ_SM_CTRL3_OS_DFE_EN_SHIFT 13 16897 16898 /* Dsc2b0 :: acq_sm_ctrl3 :: dfe_taps2_5_en [12:12] */ 16899 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_MASK 0x1000 16900 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_ALIGN 0 16901 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_BITS 1 16902 #define DSC2B0_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_SHIFT 12 16903 16904 /* Dsc2b0 :: acq_sm_ctrl3 :: dfe_gain_acq2 [11:10] */ 16905 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_MASK 0x0c00 16906 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN 0 16907 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_BITS 2 16908 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT 10 16909 16910 /* Dsc2b0 :: acq_sm_ctrl3 :: dfe_gain_acq1 [09:08] */ 16911 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_MASK 0x0300 16912 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN 0 16913 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_BITS 2 16914 #define DSC2B0_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT 8 16915 16916 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acq2 [07:06] */ 16917 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_MASK 0x00c0 16918 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN 0 16919 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_BITS 2 16920 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT 6 16921 16922 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acq1 [05:04] */ 16923 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_MASK 0x0030 16924 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN 0 16925 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_BITS 2 16926 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT 4 16927 16928 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acqcdr [03:02] */ 16929 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_MASK 0x000c 16930 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN 0 16931 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_BITS 2 16932 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT 2 16933 16934 /* Dsc2b0 :: acq_sm_ctrl3 :: vga_gain_acqvga [01:00] */ 16935 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_MASK 0x0003 16936 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN 0 16937 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_BITS 2 16938 #define DSC2B0_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT 0 16939 16940 16941 /**************************************************************************** 16942 * Dsc2b0 :: acq_sm_ctrl4 16943 */ 16944 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */ 16945 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK 0xc000 16946 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN 0 16947 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS 2 16948 #define DSC2B0_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT 14 16949 16950 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros38_bwsel_prop_offset [13:12] */ 16951 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_MASK 0x3000 16952 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_ALIGN 0 16953 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_BITS 2 16954 #define DSC2B0_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_SHIFT 12 16955 16956 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [11:08] */ 16957 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x0f00 16958 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 16959 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 16960 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 8 16961 16962 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acqcdr [07:04] */ 16963 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK 0x00f0 16964 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 16965 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS 4 16966 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT 4 16967 16968 /* Dsc2b0 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acqvga [03:00] */ 16969 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_MASK 0x000f 16970 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_ALIGN 0 16971 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_BITS 4 16972 #define DSC2B0_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_SHIFT 0 16973 16974 16975 /**************************************************************************** 16976 * Dsc2b0 :: acq_sm_ctrl5 16977 */ 16978 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_eee_acq2 [15:12] */ 16979 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_MASK 0xf000 16980 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_ALIGN 0 16981 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_BITS 4 16982 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_SHIFT 12 16983 16984 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [11:08] */ 16985 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0x0f00 16986 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 16987 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 16988 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 8 16989 16990 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acqcdr [07:04] */ 16991 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x00f0 16992 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 16993 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 16994 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 4 16995 16996 /* Dsc2b0 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acqvga [03:00] */ 16997 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_MASK 0x000f 16998 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_ALIGN 0 16999 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_BITS 4 17000 #define DSC2B0_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_SHIFT 0 17001 17002 17003 /**************************************************************************** 17004 * Dsc2b0 :: acq_sm_ctrl6 17005 */ 17006 /* Dsc2b0 :: acq_sm_ctrl6 :: reserved0 [15:12] */ 17007 #define DSC2B0_ACQ_SM_CTRL6_RESERVED0_MASK 0xf000 17008 #define DSC2B0_ACQ_SM_CTRL6_RESERVED0_ALIGN 0 17009 #define DSC2B0_ACQ_SM_CTRL6_RESERVED0_BITS 4 17010 #define DSC2B0_ACQ_SM_CTRL6_RESERVED0_SHIFT 12 17011 17012 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acq2 [11:09] */ 17013 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0e00 17014 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 17015 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_BITS 3 17016 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_SHIFT 9 17017 17018 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acq1 [08:06] */ 17019 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_MASK 0x01c0 17020 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 17021 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_BITS 3 17022 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_SHIFT 6 17023 17024 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acqcdr [05:03] */ 17025 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x0038 17026 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 17027 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 17028 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 3 17029 17030 /* Dsc2b0 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [02:00] */ 17031 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK 0x0007 17032 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN 0 17033 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS 3 17034 #define DSC2B0_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT 0 17035 17036 17037 /**************************************************************************** 17038 * Dsc2b0 :: acq_sm_ctrl7 17039 */ 17040 /* Dsc2b0 :: acq_sm_ctrl7 :: reserved0 [15:12] */ 17041 #define DSC2B0_ACQ_SM_CTRL7_RESERVED0_MASK 0xf000 17042 #define DSC2B0_ACQ_SM_CTRL7_RESERVED0_ALIGN 0 17043 #define DSC2B0_ACQ_SM_CTRL7_RESERVED0_BITS 4 17044 #define DSC2B0_ACQ_SM_CTRL7_RESERVED0_SHIFT 12 17045 17046 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acq2 [11:09] */ 17047 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0e00 17048 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 17049 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_BITS 3 17050 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 9 17051 17052 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acq1 [08:06] */ 17053 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x01c0 17054 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 17055 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_BITS 3 17056 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 6 17057 17058 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acqcdr [05:03] */ 17059 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x0038 17060 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 17061 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_BITS 3 17062 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 3 17063 17064 /* Dsc2b0 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acqphase [02:00] */ 17065 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_MASK 0x0007 17066 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN 0 17067 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_BITS 3 17068 #define DSC2B0_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT 0 17069 17070 17071 /**************************************************************************** 17072 * Dsc2b0 :: acq_sm_ctrl8 17073 */ 17074 /* Dsc2b0 :: acq_sm_ctrl8 :: reserved0 [15:15] */ 17075 #define DSC2B0_ACQ_SM_CTRL8_RESERVED0_MASK 0x8000 17076 #define DSC2B0_ACQ_SM_CTRL8_RESERVED0_ALIGN 0 17077 #define DSC2B0_ACQ_SM_CTRL8_RESERVED0_BITS 1 17078 #define DSC2B0_ACQ_SM_CTRL8_RESERVED0_SHIFT 15 17079 17080 /* Dsc2b0 :: acq_sm_ctrl8 :: cdros_bwsel_prop_eee_acqphase [14:11] */ 17081 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_MASK 0x7800 17082 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_ALIGN 0 17083 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_BITS 4 17084 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_SHIFT 11 17085 17086 /* Dsc2b0 :: acq_sm_ctrl8 :: phase_sat_ctrl_100fx [10:09] */ 17087 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_MASK 0x0600 17088 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_ALIGN 0 17089 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_BITS 2 17090 #define DSC2B0_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_SHIFT 9 17091 17092 /* Dsc2b0 :: acq_sm_ctrl8 :: pi_phase_step_mult_100fx [08:08] */ 17093 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_MASK 0x0100 17094 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_ALIGN 0 17095 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_BITS 1 17096 #define DSC2B0_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_SHIFT 8 17097 17098 /* Dsc2b0 :: acq_sm_ctrl8 :: cdros_bwsel_integ_100fx [07:04] */ 17099 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_MASK 0x00f0 17100 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_ALIGN 0 17101 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_BITS 4 17102 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_SHIFT 4 17103 17104 /* Dsc2b0 :: acq_sm_ctrl8 :: cdros_bwsel_prop_100fx [03:00] */ 17105 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_MASK 0x000f 17106 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_ALIGN 0 17107 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_BITS 4 17108 #define DSC2B0_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_SHIFT 0 17109 17110 17111 /**************************************************************************** 17112 * Dsc2b0 :: dsc_ana_ctrl0 17113 */ 17114 /* Dsc2b0 :: dsc_ana_ctrl0 :: reserved0 [15:15] */ 17115 #define DSC2B0_DSC_ANA_CTRL0_RESERVED0_MASK 0x8000 17116 #define DSC2B0_DSC_ANA_CTRL0_RESERVED0_ALIGN 0 17117 #define DSC2B0_DSC_ANA_CTRL0_RESERVED0_BITS 1 17118 #define DSC2B0_DSC_ANA_CTRL0_RESERVED0_SHIFT 15 17119 17120 /* Dsc2b0 :: dsc_ana_ctrl0 :: force_p1_ctrl_strobe [14:14] */ 17121 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_MASK 0x4000 17122 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_ALIGN 0 17123 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_BITS 1 17124 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_SHIFT 14 17125 17126 /* Dsc2b0 :: dsc_ana_ctrl0 :: force_p1_odd_ctrl [13:13] */ 17127 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_MASK 0x2000 17128 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_ALIGN 0 17129 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_BITS 1 17130 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_SHIFT 13 17131 17132 /* Dsc2b0 :: dsc_ana_ctrl0 :: force_p1_evn_ctrl [12:12] */ 17133 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_MASK 0x1000 17134 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_ALIGN 0 17135 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_BITS 1 17136 #define DSC2B0_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_SHIFT 12 17137 17138 /* Dsc2b0 :: dsc_ana_ctrl0 :: p1_odd_ctrl [11:06] */ 17139 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK 0x0fc0 17140 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN 0 17141 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS 6 17142 #define DSC2B0_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT 6 17143 17144 /* Dsc2b0 :: dsc_ana_ctrl0 :: p1_evn_ctrl [05:00] */ 17145 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_MASK 0x003f 17146 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_ALIGN 0 17147 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_BITS 6 17148 #define DSC2B0_DSC_ANA_CTRL0_P1_EVN_CTRL_SHIFT 0 17149 17150 17151 /**************************************************************************** 17152 * Dsc2b0 :: dsc_ana_ctrl1 17153 */ 17154 /* Dsc2b0 :: dsc_ana_ctrl1 :: reserved0 [15:15] */ 17155 #define DSC2B0_DSC_ANA_CTRL1_RESERVED0_MASK 0x8000 17156 #define DSC2B0_DSC_ANA_CTRL1_RESERVED0_ALIGN 0 17157 #define DSC2B0_DSC_ANA_CTRL1_RESERVED0_BITS 1 17158 #define DSC2B0_DSC_ANA_CTRL1_RESERVED0_SHIFT 15 17159 17160 /* Dsc2b0 :: dsc_ana_ctrl1 :: force_d_ctrl_strobe [14:14] */ 17161 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_MASK 0x4000 17162 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_ALIGN 0 17163 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_BITS 1 17164 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_SHIFT 14 17165 17166 /* Dsc2b0 :: dsc_ana_ctrl1 :: force_d_odd_ctrl [13:13] */ 17167 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_MASK 0x2000 17168 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_ALIGN 0 17169 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_BITS 1 17170 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_SHIFT 13 17171 17172 /* Dsc2b0 :: dsc_ana_ctrl1 :: force_d_evn_ctrl [12:12] */ 17173 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_MASK 0x1000 17174 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_ALIGN 0 17175 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_BITS 1 17176 #define DSC2B0_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_SHIFT 12 17177 17178 /* Dsc2b0 :: dsc_ana_ctrl1 :: d_odd_ctrl [11:06] */ 17179 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_MASK 0x0fc0 17180 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_ALIGN 0 17181 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_BITS 6 17182 #define DSC2B0_DSC_ANA_CTRL1_D_ODD_CTRL_SHIFT 6 17183 17184 /* Dsc2b0 :: dsc_ana_ctrl1 :: d_evn_ctrl [05:00] */ 17185 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_MASK 0x003f 17186 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN 0 17187 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_BITS 6 17188 #define DSC2B0_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT 0 17189 17190 17191 /**************************************************************************** 17192 * Dsc2b0 :: dsc_ana_ctrl2 17193 */ 17194 /* Dsc2b0 :: dsc_ana_ctrl2 :: reserved0 [15:15] */ 17195 #define DSC2B0_DSC_ANA_CTRL2_RESERVED0_MASK 0x8000 17196 #define DSC2B0_DSC_ANA_CTRL2_RESERVED0_ALIGN 0 17197 #define DSC2B0_DSC_ANA_CTRL2_RESERVED0_BITS 1 17198 #define DSC2B0_DSC_ANA_CTRL2_RESERVED0_SHIFT 15 17199 17200 /* Dsc2b0 :: dsc_ana_ctrl2 :: force_m1_ctrl_strobe [14:14] */ 17201 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_MASK 0x4000 17202 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_ALIGN 0 17203 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_BITS 1 17204 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_SHIFT 14 17205 17206 /* Dsc2b0 :: dsc_ana_ctrl2 :: force_m1_odd_ctrl [13:13] */ 17207 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_MASK 0x2000 17208 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_ALIGN 0 17209 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_BITS 1 17210 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_SHIFT 13 17211 17212 /* Dsc2b0 :: dsc_ana_ctrl2 :: force_m1_evn_ctrl [12:12] */ 17213 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_MASK 0x1000 17214 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_ALIGN 0 17215 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_BITS 1 17216 #define DSC2B0_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_SHIFT 12 17217 17218 /* Dsc2b0 :: dsc_ana_ctrl2 :: m1_odd_ctrl [11:06] */ 17219 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_MASK 0x0fc0 17220 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_ALIGN 0 17221 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_BITS 6 17222 #define DSC2B0_DSC_ANA_CTRL2_M1_ODD_CTRL_SHIFT 6 17223 17224 /* Dsc2b0 :: dsc_ana_ctrl2 :: m1_evn_ctrl [05:00] */ 17225 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_MASK 0x003f 17226 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_ALIGN 0 17227 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_BITS 6 17228 #define DSC2B0_DSC_ANA_CTRL2_M1_EVN_CTRL_SHIFT 0 17229 17230 17231 /**************************************************************************** 17232 * Dsc2b0 :: dsc_ana_ctrl3 17233 */ 17234 /* Dsc2b0 :: dsc_ana_ctrl3 :: reserved0 [15:10] */ 17235 #define DSC2B0_DSC_ANA_CTRL3_RESERVED0_MASK 0xfc00 17236 #define DSC2B0_DSC_ANA_CTRL3_RESERVED0_ALIGN 0 17237 #define DSC2B0_DSC_ANA_CTRL3_RESERVED0_BITS 6 17238 #define DSC2B0_DSC_ANA_CTRL3_RESERVED0_SHIFT 10 17239 17240 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_pf_hiz [09:09] */ 17241 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_MASK 0x0200 17242 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_ALIGN 0 17243 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_BITS 1 17244 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_HIZ_SHIFT 9 17245 17246 /* Dsc2b0 :: dsc_ana_ctrl3 :: force_rx_m1_thresh_zero [08:08] */ 17247 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_MASK 0x0100 17248 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_ALIGN 0 17249 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_BITS 1 17250 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_SHIFT 8 17251 17252 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_m1_thresh_zero [07:07] */ 17253 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_MASK 0x0080 17254 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_ALIGN 0 17255 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_BITS 1 17256 #define DSC2B0_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_SHIFT 7 17257 17258 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_thresh_sel [06:05] */ 17259 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_MASK 0x0060 17260 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_ALIGN 0 17261 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_BITS 2 17262 #define DSC2B0_DSC_ANA_CTRL3_RX_THRESH_SEL_SHIFT 5 17263 17264 /* Dsc2b0 :: dsc_ana_ctrl3 :: force_rx_pf_ctrl [04:04] */ 17265 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_MASK 0x0010 17266 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_ALIGN 0 17267 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_BITS 1 17268 #define DSC2B0_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_SHIFT 4 17269 17270 /* Dsc2b0 :: dsc_ana_ctrl3 :: rx_pf_ctrl [03:00] */ 17271 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_MASK 0x000f 17272 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_ALIGN 0 17273 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_BITS 4 17274 #define DSC2B0_DSC_ANA_CTRL3_RX_PF_CTRL_SHIFT 0 17275 17276 17277 /**************************************************************************** 17278 * Dsc2b0 :: dsc_ana_ctrl4 17279 */ 17280 /* Dsc2b0 :: dsc_ana_ctrl4 :: reserved0 [15:08] */ 17281 #define DSC2B0_DSC_ANA_CTRL4_RESERVED0_MASK 0xff00 17282 #define DSC2B0_DSC_ANA_CTRL4_RESERVED0_ALIGN 0 17283 #define DSC2B0_DSC_ANA_CTRL4_RESERVED0_BITS 8 17284 #define DSC2B0_DSC_ANA_CTRL4_RESERVED0_SHIFT 8 17285 17286 /* Dsc2b0 :: dsc_ana_ctrl4 :: br_offset_pd [07:07] */ 17287 #define DSC2B0_DSC_ANA_CTRL4_BR_OFFSET_PD_MASK 0x0080 17288 #define DSC2B0_DSC_ANA_CTRL4_BR_OFFSET_PD_ALIGN 0 17289 #define DSC2B0_DSC_ANA_CTRL4_BR_OFFSET_PD_BITS 1 17290 #define DSC2B0_DSC_ANA_CTRL4_BR_OFFSET_PD_SHIFT 7 17291 17292 /* Dsc2b0 :: dsc_ana_ctrl4 :: br_en_hgain [06:06] */ 17293 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_HGAIN_MASK 0x0040 17294 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_HGAIN_ALIGN 0 17295 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_HGAIN_BITS 1 17296 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_HGAIN_SHIFT 6 17297 17298 /* Dsc2b0 :: dsc_ana_ctrl4 :: br_en_dfe_clk [05:05] */ 17299 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_DFE_CLK_MASK 0x0020 17300 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_DFE_CLK_ALIGN 0 17301 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_DFE_CLK_BITS 1 17302 #define DSC2B0_DSC_ANA_CTRL4_BR_EN_DFE_CLK_SHIFT 5 17303 17304 /* Dsc2b0 :: dsc_ana_ctrl4 :: br_pd_ch_p1 [04:04] */ 17305 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_MASK 0x0010 17306 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_ALIGN 0 17307 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_BITS 1 17308 #define DSC2B0_DSC_ANA_CTRL4_BR_PD_CH_P1_SHIFT 4 17309 17310 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_offset_pd [03:03] */ 17311 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_MASK 0x0008 17312 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_ALIGN 0 17313 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_BITS 1 17314 #define DSC2B0_DSC_ANA_CTRL4_OSR_OFFSET_PD_SHIFT 3 17315 17316 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_en_hgain [02:02] */ 17317 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_MASK 0x0004 17318 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_ALIGN 0 17319 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_BITS 1 17320 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_HGAIN_SHIFT 2 17321 17322 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_en_dfe_clk [01:01] */ 17323 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_MASK 0x0002 17324 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_ALIGN 0 17325 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_BITS 1 17326 #define DSC2B0_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_SHIFT 1 17327 17328 /* Dsc2b0 :: dsc_ana_ctrl4 :: osr_pd_ch_p1 [00:00] */ 17329 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_MASK 0x0001 17330 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_ALIGN 0 17331 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_BITS 1 17332 #define DSC2B0_DSC_ANA_CTRL4_OSR_PD_CH_P1_SHIFT 0 17333 17334 17335 /**************************************************************************** 17336 * Dsc2b0 :: dsc_misc_ctrl0 17337 */ 17338 /* Dsc2b0 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */ 17339 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_MASK 0x8000 17340 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_ALIGN 0 17341 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_BITS 1 17342 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_SHIFT 15 17343 17344 /* Dsc2b0 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */ 17345 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK 0x4000 17346 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN 0 17347 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS 1 17348 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT 14 17349 17350 /* Dsc2b0 :: dsc_misc_ctrl0 :: reserved0 [13:13] */ 17351 #define DSC2B0_DSC_MISC_CTRL0_RESERVED0_MASK 0x2000 17352 #define DSC2B0_DSC_MISC_CTRL0_RESERVED0_ALIGN 0 17353 #define DSC2B0_DSC_MISC_CTRL0_RESERVED0_BITS 1 17354 #define DSC2B0_DSC_MISC_CTRL0_RESERVED0_SHIFT 13 17355 17356 /* Dsc2b0 :: dsc_misc_ctrl0 :: forceRxSeqDone_val [12:12] */ 17357 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_MASK 0x1000 17358 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_ALIGN 0 17359 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_BITS 1 17360 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_SHIFT 12 17361 17362 /* Dsc2b0 :: dsc_misc_ctrl0 :: rxSeqStart_AN_disable [11:11] */ 17363 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_MASK 0x0800 17364 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_ALIGN 0 17365 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_BITS 1 17366 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_SHIFT 11 17367 17368 /* Dsc2b0 :: dsc_misc_ctrl0 :: test_bus_sel_bit4 [10:10] */ 17369 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_MASK 0x0400 17370 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_ALIGN 0 17371 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_BITS 1 17372 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_SHIFT 10 17373 17374 /* Dsc2b0 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */ 17375 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK 0x0200 17376 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN 0 17377 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS 1 17378 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT 9 17379 17380 /* Dsc2b0 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */ 17381 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK 0x0100 17382 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN 0 17383 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS 1 17384 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT 8 17385 17386 /* Dsc2b0 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */ 17387 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK 0x0080 17388 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN 0 17389 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS 1 17390 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT 7 17391 17392 /* Dsc2b0 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */ 17393 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK 0x0070 17394 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN 0 17395 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS 3 17396 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT 4 17397 17398 /* Dsc2b0 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */ 17399 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK 0x000f 17400 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN 0 17401 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS 4 17402 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT 0 17403 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_Off 0 17404 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data 1 17405 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 17406 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 17407 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 17408 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg 6 17409 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 17410 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 17411 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 17412 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 17413 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe1 12 17414 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe2 13 17415 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe3 14 17416 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe4 15 17417 17418 17419 /**************************************************************************** 17420 * TSC_WC4_TSC_USER4_Dsc3b0 17421 */ 17422 /**************************************************************************** 17423 * Dsc3b0 :: cdr_status0 17424 */ 17425 /* Dsc3b0 :: cdr_status0 :: integ_reg [15:00] */ 17426 #define DSC3B0_CDR_STATUS0_INTEG_REG_MASK 0xffff 17427 #define DSC3B0_CDR_STATUS0_INTEG_REG_ALIGN 0 17428 #define DSC3B0_CDR_STATUS0_INTEG_REG_BITS 16 17429 #define DSC3B0_CDR_STATUS0_INTEG_REG_SHIFT 0 17430 17431 17432 /**************************************************************************** 17433 * Dsc3b0 :: cdr_status1 17434 */ 17435 /* Dsc3b0 :: cdr_status1 :: integ_reg_xfer [15:00] */ 17436 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_MASK 0xffff 17437 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_ALIGN 0 17438 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_BITS 16 17439 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_SHIFT 0 17440 17441 17442 /**************************************************************************** 17443 * Dsc3b0 :: cdr_status2 17444 */ 17445 /* Dsc3b0 :: cdr_status2 :: reserved0 [15:12] */ 17446 #define DSC3B0_CDR_STATUS2_RESERVED0_MASK 0xf000 17447 #define DSC3B0_CDR_STATUS2_RESERVED0_ALIGN 0 17448 #define DSC3B0_CDR_STATUS2_RESERVED0_BITS 4 17449 #define DSC3B0_CDR_STATUS2_RESERVED0_SHIFT 12 17450 17451 /* Dsc3b0 :: cdr_status2 :: rx_fifo_os8_error [11:11] */ 17452 #define DSC3B0_CDR_STATUS2_RX_FIFO_OS8_ERROR_MASK 0x0800 17453 #define DSC3B0_CDR_STATUS2_RX_FIFO_OS8_ERROR_ALIGN 0 17454 #define DSC3B0_CDR_STATUS2_RX_FIFO_OS8_ERROR_BITS 1 17455 #define DSC3B0_CDR_STATUS2_RX_FIFO_OS8_ERROR_SHIFT 11 17456 17457 /* Dsc3b0 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */ 17458 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK 0x0400 17459 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN 0 17460 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS 1 17461 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT 10 17462 17463 /* Dsc3b0 :: cdr_status2 :: br_cdr_enabled [09:09] */ 17464 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_MASK 0x0200 17465 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_ALIGN 0 17466 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_BITS 1 17467 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_SHIFT 9 17468 17469 /* Dsc3b0 :: cdr_status2 :: oscdr_mode [08:06] */ 17470 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_MASK 0x01c0 17471 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_ALIGN 0 17472 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_BITS 3 17473 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_SHIFT 6 17474 17475 /* Dsc3b0 :: cdr_status2 :: phase_err [05:00] */ 17476 #define DSC3B0_CDR_STATUS2_PHASE_ERR_MASK 0x003f 17477 #define DSC3B0_CDR_STATUS2_PHASE_ERR_ALIGN 0 17478 #define DSC3B0_CDR_STATUS2_PHASE_ERR_BITS 6 17479 #define DSC3B0_CDR_STATUS2_PHASE_ERR_SHIFT 0 17480 17481 17482 /**************************************************************************** 17483 * Dsc3b0 :: pi_status0 17484 */ 17485 /* Dsc3b0 :: pi_status0 :: reserved0 [15:14] */ 17486 #define DSC3B0_PI_STATUS0_RESERVED0_MASK 0xc000 17487 #define DSC3B0_PI_STATUS0_RESERVED0_ALIGN 0 17488 #define DSC3B0_PI_STATUS0_RESERVED0_BITS 2 17489 #define DSC3B0_PI_STATUS0_RESERVED0_SHIFT 14 17490 17491 /* Dsc3b0 :: pi_status0 :: clk90_phase_offset [13:07] */ 17492 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 17493 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 17494 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 17495 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 17496 17497 /* Dsc3b0 :: pi_status0 :: phase_cntr [06:00] */ 17498 #define DSC3B0_PI_STATUS0_PHASE_CNTR_MASK 0x007f 17499 #define DSC3B0_PI_STATUS0_PHASE_CNTR_ALIGN 0 17500 #define DSC3B0_PI_STATUS0_PHASE_CNTR_BITS 7 17501 #define DSC3B0_PI_STATUS0_PHASE_CNTR_SHIFT 0 17502 17503 17504 /**************************************************************************** 17505 * Dsc3b0 :: pi_status1 17506 */ 17507 /* Dsc3b0 :: pi_status1 :: phs_interp_status [15:00] */ 17508 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_MASK 0xffff 17509 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_ALIGN 0 17510 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_BITS 16 17511 #define DSC3B0_PI_STATUS1_PHS_INTERP_STATUS_SHIFT 0 17512 17513 17514 /**************************************************************************** 17515 * Dsc3b0 :: dfe_vga_status0 17516 */ 17517 /* Dsc3b0 :: dfe_vga_status0 :: reserved0 [15:12] */ 17518 #define DSC3B0_DFE_VGA_STATUS0_RESERVED0_MASK 0xf000 17519 #define DSC3B0_DFE_VGA_STATUS0_RESERVED0_ALIGN 0 17520 #define DSC3B0_DFE_VGA_STATUS0_RESERVED0_BITS 4 17521 #define DSC3B0_DFE_VGA_STATUS0_RESERVED0_SHIFT 12 17522 17523 /* Dsc3b0 :: dfe_vga_status0 :: dfe_tap_1_bin [11:06] */ 17524 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_MASK 0x0fc0 17525 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_ALIGN 0 17526 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_BITS 6 17527 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_1_BIN_SHIFT 6 17528 17529 /* Dsc3b0 :: dfe_vga_status0 :: vga_sum [05:00] */ 17530 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_MASK 0x003f 17531 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 17532 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_BITS 6 17533 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_SHIFT 0 17534 17535 17536 /**************************************************************************** 17537 * Dsc3b0 :: dfe_vga_status1 17538 */ 17539 /* Dsc3b0 :: dfe_vga_status1 :: reserved0 [15:12] */ 17540 #define DSC3B0_DFE_VGA_STATUS1_RESERVED0_MASK 0xf000 17541 #define DSC3B0_DFE_VGA_STATUS1_RESERVED0_ALIGN 0 17542 #define DSC3B0_DFE_VGA_STATUS1_RESERVED0_BITS 4 17543 #define DSC3B0_DFE_VGA_STATUS1_RESERVED0_SHIFT 12 17544 17545 /* Dsc3b0 :: dfe_vga_status1 :: dfe_tap_3_bin [11:06] */ 17546 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_MASK 0x0fc0 17547 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_ALIGN 0 17548 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_BITS 6 17549 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_3_BIN_SHIFT 6 17550 17551 /* Dsc3b0 :: dfe_vga_status1 :: dfe_tap_2_bin [05:00] */ 17552 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_MASK 0x003f 17553 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_ALIGN 0 17554 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_BITS 6 17555 #define DSC3B0_DFE_VGA_STATUS1_DFE_TAP_2_BIN_SHIFT 0 17556 17557 17558 /**************************************************************************** 17559 * Dsc3b0 :: dfe_vga_status2 17560 */ 17561 /* Dsc3b0 :: dfe_vga_status2 :: reserved0 [15:10] */ 17562 #define DSC3B0_DFE_VGA_STATUS2_RESERVED0_MASK 0xfc00 17563 #define DSC3B0_DFE_VGA_STATUS2_RESERVED0_ALIGN 0 17564 #define DSC3B0_DFE_VGA_STATUS2_RESERVED0_BITS 6 17565 #define DSC3B0_DFE_VGA_STATUS2_RESERVED0_SHIFT 10 17566 17567 /* Dsc3b0 :: dfe_vga_status2 :: dfe_tap_5_bin [09:05] */ 17568 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_MASK 0x03e0 17569 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_ALIGN 0 17570 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_BITS 5 17571 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_5_BIN_SHIFT 5 17572 17573 /* Dsc3b0 :: dfe_vga_status2 :: dfe_tap_4_bin [04:00] */ 17574 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_MASK 0x001f 17575 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_ALIGN 0 17576 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_BITS 5 17577 #define DSC3B0_DFE_VGA_STATUS2_DFE_TAP_4_BIN_SHIFT 0 17578 17579 17580 /**************************************************************************** 17581 * Dsc3b0 :: dfe_vga_status3 17582 */ 17583 /* Dsc3b0 :: dfe_vga_status3 :: reserved0 [15:11] */ 17584 #define DSC3B0_DFE_VGA_STATUS3_RESERVED0_MASK 0xf800 17585 #define DSC3B0_DFE_VGA_STATUS3_RESERVED0_ALIGN 0 17586 #define DSC3B0_DFE_VGA_STATUS3_RESERVED0_BITS 5 17587 #define DSC3B0_DFE_VGA_STATUS3_RESERVED0_SHIFT 11 17588 17589 /* Dsc3b0 :: dfe_vga_status3 :: trnsum [10:00] */ 17590 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_MASK 0x07ff 17591 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_ALIGN 0 17592 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_BITS 11 17593 #define DSC3B0_DFE_VGA_STATUS3_TRNSUM_SHIFT 0 17594 17595 17596 /**************************************************************************** 17597 * Dsc3b0 :: acq_sm_status0 17598 */ 17599 /* Dsc3b0 :: acq_sm_status0 :: reserved0 [15:09] */ 17600 #define DSC3B0_ACQ_SM_STATUS0_RESERVED0_MASK 0xfe00 17601 #define DSC3B0_ACQ_SM_STATUS0_RESERVED0_ALIGN 0 17602 #define DSC3B0_ACQ_SM_STATUS0_RESERVED0_BITS 7 17603 #define DSC3B0_ACQ_SM_STATUS0_RESERVED0_SHIFT 9 17604 17605 /* Dsc3b0 :: acq_sm_status0 :: dsc_state_eee_acq_2 [08:08] */ 17606 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_MASK 0x0100 17607 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_ALIGN 0 17608 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_BITS 1 17609 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_EEE_ACQ_2_SHIFT 8 17610 17611 /* Dsc3b0 :: acq_sm_status0 :: reserved1 [07:05] */ 17612 #define DSC3B0_ACQ_SM_STATUS0_RESERVED1_MASK 0x00e0 17613 #define DSC3B0_ACQ_SM_STATUS0_RESERVED1_ALIGN 0 17614 #define DSC3B0_ACQ_SM_STATUS0_RESERVED1_BITS 3 17615 #define DSC3B0_ACQ_SM_STATUS0_RESERVED1_SHIFT 5 17616 17617 /* Dsc3b0 :: acq_sm_status0 :: dsc_state [04:00] */ 17618 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_MASK 0x001f 17619 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_ALIGN 0 17620 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_BITS 5 17621 #define DSC3B0_ACQ_SM_STATUS0_DSC_STATE_SHIFT 0 17622 17623 17624 /**************************************************************************** 17625 * Dsc3b0 :: acq_sm_status1 17626 */ 17627 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_eee_acq_cdr_phase [15:15] */ 17628 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_MASK 0x8000 17629 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_ALIGN 0 17630 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_BITS 1 17631 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_ACQ_CDR_PHASE_SHIFT 15 17632 17633 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_eee_quiet [14:14] */ 17634 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_MASK 0x4000 17635 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_ALIGN 0 17636 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_BITS 1 17637 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_EEE_QUIET_SHIFT 14 17638 17639 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_done [13:13] */ 17640 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_MASK 0x2000 17641 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_ALIGN 0 17642 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_BITS 1 17643 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_DONE_SHIFT 13 17644 17645 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_measure [12:12] */ 17646 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_MASK 0x1000 17647 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_ALIGN 0 17648 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_BITS 1 17649 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_MEASURE_SHIFT 12 17650 17651 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_train_2 [11:11] */ 17652 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_MASK 0x0800 17653 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_ALIGN 0 17654 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_BITS 1 17655 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_2_SHIFT 11 17656 17657 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_train_1 [10:10] */ 17658 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_MASK 0x0400 17659 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_ALIGN 0 17660 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_BITS 1 17661 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_TRAIN_1_SHIFT 10 17662 17663 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_soft_ack [09:09] */ 17664 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_MASK 0x0200 17665 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_ALIGN 0 17666 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_BITS 1 17667 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SOFT_ACK_SHIFT 9 17668 17669 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_2 [08:08] */ 17670 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_MASK 0x0100 17671 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_ALIGN 0 17672 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_BITS 1 17673 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_2_SHIFT 8 17674 17675 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_1 [07:07] */ 17676 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_MASK 0x0080 17677 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_ALIGN 0 17678 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_BITS 1 17679 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_1_SHIFT 7 17680 17681 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_cdr [06:06] */ 17682 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_MASK 0x0040 17683 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_ALIGN 0 17684 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_BITS 1 17685 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDR_SHIFT 6 17686 17687 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_cdrbr_phase [05:05] */ 17688 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_MASK 0x0020 17689 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_ALIGN 0 17690 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_BITS 1 17691 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_CDRBR_PHASE_SHIFT 5 17692 17693 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_os_integ_xfer [04:04] */ 17694 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_MASK 0x0010 17695 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_ALIGN 0 17696 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_BITS 1 17697 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_OS_INTEG_XFER_SHIFT 4 17698 17699 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_acq_vga [03:03] */ 17700 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_MASK 0x0008 17701 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_ALIGN 0 17702 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_BITS 1 17703 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_ACQ_VGA_SHIFT 3 17704 17705 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_setup [02:02] */ 17706 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_MASK 0x0004 17707 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_ALIGN 0 17708 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_BITS 1 17709 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_SETUP_SHIFT 2 17710 17711 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_pause [01:01] */ 17712 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_MASK 0x0002 17713 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_ALIGN 0 17714 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_BITS 1 17715 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_PAUSE_SHIFT 1 17716 17717 /* Dsc3b0 :: acq_sm_status1 :: dsc_state_init [00:00] */ 17718 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_MASK 0x0001 17719 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_ALIGN 0 17720 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_BITS 1 17721 #define DSC3B0_ACQ_SM_STATUS1_DSC_STATE_INIT_SHIFT 0 17722 17723 17724 /**************************************************************************** 17725 * Dsc3b0 :: ana_status0 17726 */ 17727 /* Dsc3b0 :: ana_status0 :: reserved0 [15:08] */ 17728 #define DSC3B0_ANA_STATUS0_RESERVED0_MASK 0xff00 17729 #define DSC3B0_ANA_STATUS0_RESERVED0_ALIGN 0 17730 #define DSC3B0_ANA_STATUS0_RESERVED0_BITS 8 17731 #define DSC3B0_ANA_STATUS0_RESERVED0_SHIFT 8 17732 17733 /* Dsc3b0 :: ana_status0 :: pd_ch_p1 [07:07] */ 17734 #define DSC3B0_ANA_STATUS0_PD_CH_P1_MASK 0x0080 17735 #define DSC3B0_ANA_STATUS0_PD_CH_P1_ALIGN 0 17736 #define DSC3B0_ANA_STATUS0_PD_CH_P1_BITS 1 17737 #define DSC3B0_ANA_STATUS0_PD_CH_P1_SHIFT 7 17738 17739 /* Dsc3b0 :: ana_status0 :: en_dfe_clk [06:06] */ 17740 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_MASK 0x0040 17741 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_ALIGN 0 17742 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_BITS 1 17743 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_SHIFT 6 17744 17745 /* Dsc3b0 :: ana_status0 :: en_hgain [05:05] */ 17746 #define DSC3B0_ANA_STATUS0_EN_HGAIN_MASK 0x0020 17747 #define DSC3B0_ANA_STATUS0_EN_HGAIN_ALIGN 0 17748 #define DSC3B0_ANA_STATUS0_EN_HGAIN_BITS 1 17749 #define DSC3B0_ANA_STATUS0_EN_HGAIN_SHIFT 5 17750 17751 /* Dsc3b0 :: ana_status0 :: offset_pd [04:04] */ 17752 #define DSC3B0_ANA_STATUS0_OFFSET_PD_MASK 0x0010 17753 #define DSC3B0_ANA_STATUS0_OFFSET_PD_ALIGN 0 17754 #define DSC3B0_ANA_STATUS0_OFFSET_PD_BITS 1 17755 #define DSC3B0_ANA_STATUS0_OFFSET_PD_SHIFT 4 17756 17757 /* Dsc3b0 :: ana_status0 :: pf_ctrl_bin [03:00] */ 17758 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_MASK 0x000f 17759 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_ALIGN 0 17760 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_BITS 4 17761 #define DSC3B0_ANA_STATUS0_PF_CTRL_BIN_SHIFT 0 17762 17763 17764 /**************************************************************************** 17765 * Dsc3b0 :: ana_status1 17766 */ 17767 /* Dsc3b0 :: ana_status1 :: reserved0 [15:12] */ 17768 #define DSC3B0_ANA_STATUS1_RESERVED0_MASK 0xf000 17769 #define DSC3B0_ANA_STATUS1_RESERVED0_ALIGN 0 17770 #define DSC3B0_ANA_STATUS1_RESERVED0_BITS 4 17771 #define DSC3B0_ANA_STATUS1_RESERVED0_SHIFT 12 17772 17773 /* Dsc3b0 :: ana_status1 :: slicer_offset_po [11:06] */ 17774 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_MASK 0x0fc0 17775 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_ALIGN 0 17776 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_BITS 6 17777 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PO_SHIFT 6 17778 17779 /* Dsc3b0 :: ana_status1 :: slicer_offset_pe [05:00] */ 17780 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_MASK 0x003f 17781 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_ALIGN 0 17782 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_BITS 6 17783 #define DSC3B0_ANA_STATUS1_SLICER_OFFSET_PE_SHIFT 0 17784 17785 17786 /**************************************************************************** 17787 * Dsc3b0 :: ana_status2 17788 */ 17789 /* Dsc3b0 :: ana_status2 :: reserved0 [15:12] */ 17790 #define DSC3B0_ANA_STATUS2_RESERVED0_MASK 0xf000 17791 #define DSC3B0_ANA_STATUS2_RESERVED0_ALIGN 0 17792 #define DSC3B0_ANA_STATUS2_RESERVED0_BITS 4 17793 #define DSC3B0_ANA_STATUS2_RESERVED0_SHIFT 12 17794 17795 /* Dsc3b0 :: ana_status2 :: slicer_offset_zo [11:06] */ 17796 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_MASK 0x0fc0 17797 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_ALIGN 0 17798 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_BITS 6 17799 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZO_SHIFT 6 17800 17801 /* Dsc3b0 :: ana_status2 :: slicer_offset_ze [05:00] */ 17802 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_MASK 0x003f 17803 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_ALIGN 0 17804 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_BITS 6 17805 #define DSC3B0_ANA_STATUS2_SLICER_OFFSET_ZE_SHIFT 0 17806 17807 17808 /**************************************************************************** 17809 * Dsc3b0 :: ana_status3 17810 */ 17811 /* Dsc3b0 :: ana_status3 :: reserved0 [15:12] */ 17812 #define DSC3B0_ANA_STATUS3_RESERVED0_MASK 0xf000 17813 #define DSC3B0_ANA_STATUS3_RESERVED0_ALIGN 0 17814 #define DSC3B0_ANA_STATUS3_RESERVED0_BITS 4 17815 #define DSC3B0_ANA_STATUS3_RESERVED0_SHIFT 12 17816 17817 /* Dsc3b0 :: ana_status3 :: slicer_offset_mo [11:06] */ 17818 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_MASK 0x0fc0 17819 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_ALIGN 0 17820 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_BITS 6 17821 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_MO_SHIFT 6 17822 17823 /* Dsc3b0 :: ana_status3 :: slicer_offset_me [05:00] */ 17824 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_MASK 0x003f 17825 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_ALIGN 0 17826 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_BITS 6 17827 #define DSC3B0_ANA_STATUS3_SLICER_OFFSET_ME_SHIFT 0 17828 17829 17830 /**************************************************************************** 17831 * TSC_WC4_TSC_USER4_Dsc4b0 17832 */ 17833 /**************************************************************************** 17834 * Dsc4b0 :: tuning_sm_ctrl0 17835 */ 17836 /* Dsc4b0 :: tuning_sm_ctrl0 :: reserved0 [15:15] */ 17837 #define DSC4B0_TUNING_SM_CTRL0_RESERVED0_MASK 0x8000 17838 #define DSC4B0_TUNING_SM_CTRL0_RESERVED0_ALIGN 0 17839 #define DSC4B0_TUNING_SM_CTRL0_RESERVED0_BITS 1 17840 #define DSC4B0_TUNING_SM_CTRL0_RESERVED0_SHIFT 15 17841 17842 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_tx_postc_cal [14:14] */ 17843 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK 0x4000 17844 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN 0 17845 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS 1 17846 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT 14 17847 17848 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_br_vga [13:13] */ 17849 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_MASK 0x2000 17850 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_ALIGN 0 17851 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_BITS 1 17852 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_VGA_SHIFT 13 17853 17854 /* Dsc4b0 :: tuning_sm_ctrl0 :: postc_metric_ctrl [12:12] */ 17855 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_MASK 0x1000 17856 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN 0 17857 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_BITS 1 17858 #define DSC4B0_TUNING_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT 12 17859 17860 /* Dsc4b0 :: tuning_sm_ctrl0 :: hysteresis_en [11:11] */ 17861 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_MASK 0x0800 17862 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_ALIGN 0 17863 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_BITS 1 17864 #define DSC4B0_TUNING_SM_CTRL0_HYSTERESIS_EN_SHIFT 11 17865 17866 /* Dsc4b0 :: tuning_sm_ctrl0 :: slicer_cal_linear_srch [10:10] */ 17867 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK 0x0400 17868 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN 0 17869 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS 1 17870 #define DSC4B0_TUNING_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT 10 17871 17872 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_br_pf_cal [09:09] */ 17873 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_MASK 0x0200 17874 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN 0 17875 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_BITS 1 17876 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT 9 17877 17878 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */ 17879 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK 0x0100 17880 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN 0 17881 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS 1 17882 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT 8 17883 17884 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */ 17885 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK 0x0080 17886 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN 0 17887 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS 1 17888 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT 7 17889 17890 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_data_slicer_recal [06:06] */ 17891 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK 0x0040 17892 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN 0 17893 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS 1 17894 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT 6 17895 17896 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */ 17897 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK 0x0020 17898 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN 0 17899 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS 1 17900 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT 5 17901 17902 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */ 17903 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK 0x0010 17904 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN 0 17905 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS 1 17906 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT 4 17907 17908 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */ 17909 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK 0x0008 17910 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN 0 17911 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS 1 17912 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT 3 17913 17914 /* Dsc4b0 :: tuning_sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */ 17915 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK 0x0004 17916 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN 0 17917 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS 1 17918 #define DSC4B0_TUNING_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT 2 17919 17920 /* Dsc4b0 :: tuning_sm_ctrl0 :: restart_tuning [01:01] */ 17921 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_MASK 0x0002 17922 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_ALIGN 0 17923 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_BITS 1 17924 #define DSC4B0_TUNING_SM_CTRL0_RESTART_TUNING_SHIFT 1 17925 17926 /* Dsc4b0 :: tuning_sm_ctrl0 :: tuning_sm_en [00:00] */ 17927 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_MASK 0x0001 17928 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_ALIGN 0 17929 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_BITS 1 17930 #define DSC4B0_TUNING_SM_CTRL0_TUNING_SM_EN_SHIFT 0 17931 17932 17933 /**************************************************************************** 17934 * Dsc4b0 :: tuning_sm_ctrl1 17935 */ 17936 /* Dsc4b0 :: tuning_sm_ctrl1 :: reserved0 [15:15] */ 17937 #define DSC4B0_TUNING_SM_CTRL1_RESERVED0_MASK 0x8000 17938 #define DSC4B0_TUNING_SM_CTRL1_RESERVED0_ALIGN 0 17939 #define DSC4B0_TUNING_SM_CTRL1_RESERVED0_BITS 1 17940 #define DSC4B0_TUNING_SM_CTRL1_RESERVED0_SHIFT 15 17941 17942 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_br_offset [14:12] */ 17943 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_MASK 0x7000 17944 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_ALIGN 0 17945 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_BITS 3 17946 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_OFFSET_SHIFT 12 17947 17948 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_osx1_offset [11:09] */ 17949 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_MASK 0x0e00 17950 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_ALIGN 0 17951 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_BITS 3 17952 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX1_OFFSET_SHIFT 9 17953 17954 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_osx2_offset [08:06] */ 17955 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_MASK 0x01c0 17956 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_ALIGN 0 17957 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_BITS 3 17958 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OSX2_OFFSET_SHIFT 6 17959 17960 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_br_init [05:03] */ 17961 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_MASK 0x0038 17962 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_ALIGN 0 17963 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_BITS 3 17964 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_BR_INIT_SHIFT 3 17965 17966 /* Dsc4b0 :: tuning_sm_ctrl1 :: pf_ctrl_os_init [02:00] */ 17967 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_MASK 0x0007 17968 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_ALIGN 0 17969 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_BITS 3 17970 #define DSC4B0_TUNING_SM_CTRL1_PF_CTRL_OS_INIT_SHIFT 0 17971 17972 17973 /**************************************************************************** 17974 * Dsc4b0 :: tuning_sm_ctrl2 17975 */ 17976 /* Dsc4b0 :: tuning_sm_ctrl2 :: reserved0 [15:12] */ 17977 #define DSC4B0_TUNING_SM_CTRL2_RESERVED0_MASK 0xf000 17978 #define DSC4B0_TUNING_SM_CTRL2_RESERVED0_ALIGN 0 17979 #define DSC4B0_TUNING_SM_CTRL2_RESERVED0_BITS 4 17980 #define DSC4B0_TUNING_SM_CTRL2_RESERVED0_SHIFT 12 17981 17982 /* Dsc4b0 :: tuning_sm_ctrl2 :: vga_max_val [11:06] */ 17983 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_MASK 0x0fc0 17984 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_ALIGN 0 17985 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_BITS 6 17986 #define DSC4B0_TUNING_SM_CTRL2_VGA_MAX_VAL_SHIFT 6 17987 17988 /* Dsc4b0 :: tuning_sm_ctrl2 :: vga_min_val [05:00] */ 17989 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_MASK 0x003f 17990 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_ALIGN 0 17991 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_BITS 6 17992 #define DSC4B0_TUNING_SM_CTRL2_VGA_MIN_VAL_SHIFT 0 17993 17994 17995 /**************************************************************************** 17996 * Dsc4b0 :: tuning_sm_ctrl3 17997 */ 17998 /* Dsc4b0 :: tuning_sm_ctrl3 :: reserved0 [15:12] */ 17999 #define DSC4B0_TUNING_SM_CTRL3_RESERVED0_MASK 0xf000 18000 #define DSC4B0_TUNING_SM_CTRL3_RESERVED0_ALIGN 0 18001 #define DSC4B0_TUNING_SM_CTRL3_RESERVED0_BITS 4 18002 #define DSC4B0_TUNING_SM_CTRL3_RESERVED0_SHIFT 12 18003 18004 /* Dsc4b0 :: tuning_sm_ctrl3 :: dfe_max_val [11:06] */ 18005 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_MASK 0x0fc0 18006 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_ALIGN 0 18007 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_BITS 6 18008 #define DSC4B0_TUNING_SM_CTRL3_DFE_MAX_VAL_SHIFT 6 18009 18010 /* Dsc4b0 :: tuning_sm_ctrl3 :: dfe_min_val [05:00] */ 18011 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_MASK 0x003f 18012 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_ALIGN 0 18013 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_BITS 6 18014 #define DSC4B0_TUNING_SM_CTRL3_DFE_MIN_VAL_SHIFT 0 18015 18016 18017 /**************************************************************************** 18018 * Dsc4b0 :: tuning_sm_ctrl4 18019 */ 18020 /* Dsc4b0 :: tuning_sm_ctrl4 :: reserved0 [15:14] */ 18021 #define DSC4B0_TUNING_SM_CTRL4_RESERVED0_MASK 0xc000 18022 #define DSC4B0_TUNING_SM_CTRL4_RESERVED0_ALIGN 0 18023 #define DSC4B0_TUNING_SM_CTRL4_RESERVED0_BITS 2 18024 #define DSC4B0_TUNING_SM_CTRL4_RESERVED0_SHIFT 14 18025 18026 /* Dsc4b0 :: tuning_sm_ctrl4 :: br_pf_tap_en [13:07] */ 18027 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_MASK 0x3f80 18028 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_ALIGN 0 18029 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_BITS 7 18030 #define DSC4B0_TUNING_SM_CTRL4_BR_PF_TAP_EN_SHIFT 7 18031 18032 /* Dsc4b0 :: tuning_sm_ctrl4 :: osx1_pf_tap_en [06:00] */ 18033 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_MASK 0x007f 18034 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_ALIGN 0 18035 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_BITS 7 18036 #define DSC4B0_TUNING_SM_CTRL4_OSX1_PF_TAP_EN_SHIFT 0 18037 18038 18039 /**************************************************************************** 18040 * Dsc4b0 :: tuning_sm_ctrl5 18041 */ 18042 /* Dsc4b0 :: tuning_sm_ctrl5 :: reserved0 [15:15] */ 18043 #define DSC4B0_TUNING_SM_CTRL5_RESERVED0_MASK 0x8000 18044 #define DSC4B0_TUNING_SM_CTRL5_RESERVED0_ALIGN 0 18045 #define DSC4B0_TUNING_SM_CTRL5_RESERVED0_BITS 1 18046 #define DSC4B0_TUNING_SM_CTRL5_RESERVED0_SHIFT 15 18047 18048 /* Dsc4b0 :: tuning_sm_ctrl5 :: msr_br_vga_timeout [14:10] */ 18049 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_MASK 0x7c00 18050 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_ALIGN 0 18051 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_BITS 5 18052 #define DSC4B0_TUNING_SM_CTRL5_MSR_BR_VGA_TIMEOUT_SHIFT 10 18053 18054 /* Dsc4b0 :: tuning_sm_ctrl5 :: hysteresis_timeout [09:05] */ 18055 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_MASK 0x03e0 18056 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_ALIGN 0 18057 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_BITS 5 18058 #define DSC4B0_TUNING_SM_CTRL5_HYSTERESIS_TIMEOUT_SHIFT 5 18059 18060 /* Dsc4b0 :: tuning_sm_ctrl5 :: msr_postc_timeout [04:00] */ 18061 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_MASK 0x001f 18062 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_ALIGN 0 18063 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_BITS 5 18064 #define DSC4B0_TUNING_SM_CTRL5_MSR_POSTC_TIMEOUT_SHIFT 0 18065 18066 18067 /**************************************************************************** 18068 * Dsc4b0 :: tuning_sm_ctrl6 18069 */ 18070 /* Dsc4b0 :: tuning_sm_ctrl6 :: reserved0 [15:14] */ 18071 #define DSC4B0_TUNING_SM_CTRL6_RESERVED0_MASK 0xc000 18072 #define DSC4B0_TUNING_SM_CTRL6_RESERVED0_ALIGN 0 18073 #define DSC4B0_TUNING_SM_CTRL6_RESERVED0_BITS 2 18074 #define DSC4B0_TUNING_SM_CTRL6_RESERVED0_SHIFT 14 18075 18076 /* Dsc4b0 :: tuning_sm_ctrl6 :: br_vga_lms_gain [13:12] */ 18077 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_MASK 0x3000 18078 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_ALIGN 0 18079 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_BITS 2 18080 #define DSC4B0_TUNING_SM_CTRL6_BR_VGA_LMS_GAIN_SHIFT 12 18081 18082 /* Dsc4b0 :: tuning_sm_ctrl6 :: postc_dfe_lms_gain [11:10] */ 18083 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_MASK 0x0c00 18084 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_ALIGN 0 18085 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_BITS 2 18086 #define DSC4B0_TUNING_SM_CTRL6_POSTC_DFE_LMS_GAIN_SHIFT 10 18087 18088 /* Dsc4b0 :: tuning_sm_ctrl6 :: cdr_phase_inversion_timeout [09:05] */ 18089 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_MASK 0x03e0 18090 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_ALIGN 0 18091 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_BITS 5 18092 #define DSC4B0_TUNING_SM_CTRL6_CDR_PHASE_INVERSION_TIMEOUT_SHIFT 5 18093 18094 /* Dsc4b0 :: tuning_sm_ctrl6 :: msr_pf_timeout [04:00] */ 18095 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_MASK 0x001f 18096 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_ALIGN 0 18097 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_BITS 5 18098 #define DSC4B0_TUNING_SM_CTRL6_MSR_PF_TIMEOUT_SHIFT 0 18099 18100 18101 /**************************************************************************** 18102 * Dsc4b0 :: tuning_sm_ctrl7 18103 */ 18104 /* Dsc4b0 :: tuning_sm_ctrl7 :: reserved0 [15:15] */ 18105 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_MASK 0x8000 18106 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_ALIGN 0 18107 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_BITS 1 18108 #define DSC4B0_TUNING_SM_CTRL7_RESERVED0_SHIFT 15 18109 18110 /* Dsc4b0 :: tuning_sm_ctrl7 :: br_vga_trn2_timeout [14:10] */ 18111 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_MASK 0x7c00 18112 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_ALIGN 0 18113 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_BITS 5 18114 #define DSC4B0_TUNING_SM_CTRL7_BR_VGA_TRN2_TIMEOUT_SHIFT 10 18115 18116 /* Dsc4b0 :: tuning_sm_ctrl7 :: br_pf_trn2_timeout [09:05] */ 18117 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_MASK 0x03e0 18118 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_ALIGN 0 18119 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_BITS 5 18120 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN2_TIMEOUT_SHIFT 5 18121 18122 /* Dsc4b0 :: tuning_sm_ctrl7 :: br_pf_trn1_timeout [04:00] */ 18123 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_MASK 0x001f 18124 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_ALIGN 0 18125 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_BITS 5 18126 #define DSC4B0_TUNING_SM_CTRL7_BR_PF_TRN1_TIMEOUT_SHIFT 0 18127 18128 18129 /**************************************************************************** 18130 * Dsc4b0 :: tuning_sm_ctrl8 18131 */ 18132 /* Dsc4b0 :: tuning_sm_ctrl8 :: reserved0 [15:14] */ 18133 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_MASK 0xc000 18134 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_ALIGN 0 18135 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_BITS 2 18136 #define DSC4B0_TUNING_SM_CTRL8_RESERVED0_SHIFT 14 18137 18138 /* Dsc4b0 :: tuning_sm_ctrl8 :: br_postc_tap_en [13:07] */ 18139 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_MASK 0x3f80 18140 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_ALIGN 0 18141 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_BITS 7 18142 #define DSC4B0_TUNING_SM_CTRL8_BR_POSTC_TAP_EN_SHIFT 7 18143 18144 /* Dsc4b0 :: tuning_sm_ctrl8 :: osx2_pf_tap_en [06:00] */ 18145 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_MASK 0x007f 18146 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_ALIGN 0 18147 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_BITS 7 18148 #define DSC4B0_TUNING_SM_CTRL8_OSX2_PF_TAP_EN_SHIFT 0 18149 18150 18151 /**************************************************************************** 18152 * Dsc4b0 :: tuning_sm_ctrl9 18153 */ 18154 /* Dsc4b0 :: tuning_sm_ctrl9 :: reserved0 [15:14] */ 18155 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_MASK 0xc000 18156 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_ALIGN 0 18157 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_BITS 2 18158 #define DSC4B0_TUNING_SM_CTRL9_RESERVED0_SHIFT 14 18159 18160 /* Dsc4b0 :: tuning_sm_ctrl9 :: osx2_postc_tap_en [13:07] */ 18161 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_MASK 0x3f80 18162 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_ALIGN 0 18163 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_BITS 7 18164 #define DSC4B0_TUNING_SM_CTRL9_OSX2_POSTC_TAP_EN_SHIFT 7 18165 18166 /* Dsc4b0 :: tuning_sm_ctrl9 :: osx1_postc_tap_en [06:00] */ 18167 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_MASK 0x007f 18168 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_ALIGN 0 18169 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_BITS 7 18170 #define DSC4B0_TUNING_SM_CTRL9_OSX1_POSTC_TAP_EN_SHIFT 0 18171 18172 18173 /**************************************************************************** 18174 * Dsc4b0 :: tuning_sm_ctrl10 18175 */ 18176 /* Dsc4b0 :: tuning_sm_ctrl10 :: reserved0 [15:15] */ 18177 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_MASK 0x8000 18178 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_ALIGN 0 18179 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_BITS 1 18180 #define DSC4B0_TUNING_SM_CTRL10_RESERVED0_SHIFT 15 18181 18182 /* Dsc4b0 :: tuning_sm_ctrl10 :: msr_slicer_slow_timeout [14:10] */ 18183 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_MASK 0x7c00 18184 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_ALIGN 0 18185 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_BITS 5 18186 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_SLOW_TIMEOUT_SHIFT 10 18187 18188 /* Dsc4b0 :: tuning_sm_ctrl10 :: msr_slicer_fast_timeout [09:05] */ 18189 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_MASK 0x03e0 18190 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_ALIGN 0 18191 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_BITS 5 18192 #define DSC4B0_TUNING_SM_CTRL10_MSR_SLICER_FAST_TIMEOUT_SHIFT 5 18193 18194 /* Dsc4b0 :: tuning_sm_ctrl10 :: default_trn2_timeout [04:00] */ 18195 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_MASK 0x001f 18196 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_ALIGN 0 18197 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_BITS 5 18198 #define DSC4B0_TUNING_SM_CTRL10_DEFAULT_TRN2_TIMEOUT_SHIFT 0 18199 18200 18201 /**************************************************************************** 18202 * Dsc4b0 :: tuning_sm_ctrl11 18203 */ 18204 /* Dsc4b0 :: tuning_sm_ctrl11 :: reserved0 [15:08] */ 18205 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_MASK 0xff00 18206 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_ALIGN 0 18207 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_BITS 8 18208 #define DSC4B0_TUNING_SM_CTRL11_RESERVED0_SHIFT 8 18209 18210 /* Dsc4b0 :: tuning_sm_ctrl11 :: pf_fine_en [07:07] */ 18211 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_MASK 0x0080 18212 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_ALIGN 0 18213 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_BITS 1 18214 #define DSC4B0_TUNING_SM_CTRL11_PF_FINE_EN_SHIFT 7 18215 18216 /* Dsc4b0 :: tuning_sm_ctrl11 :: reserved1 [06:06] */ 18217 #define DSC4B0_TUNING_SM_CTRL11_RESERVED1_MASK 0x0040 18218 #define DSC4B0_TUNING_SM_CTRL11_RESERVED1_ALIGN 0 18219 #define DSC4B0_TUNING_SM_CTRL11_RESERVED1_BITS 1 18220 #define DSC4B0_TUNING_SM_CTRL11_RESERVED1_SHIFT 6 18221 18222 /* Dsc4b0 :: tuning_sm_ctrl11 :: pf_max_val [05:02] */ 18223 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_MASK 0x003c 18224 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_ALIGN 0 18225 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_BITS 4 18226 #define DSC4B0_TUNING_SM_CTRL11_PF_MAX_VAL_SHIFT 2 18227 18228 /* Dsc4b0 :: tuning_sm_ctrl11 :: bypass_osx1_slicer_cal [01:01] */ 18229 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_MASK 0x0002 18230 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_ALIGN 0 18231 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_BITS 1 18232 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX1_SLICER_CAL_SHIFT 1 18233 18234 /* Dsc4b0 :: tuning_sm_ctrl11 :: bypass_osx2_slicer_cal [00:00] */ 18235 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_MASK 0x0001 18236 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_ALIGN 0 18237 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_BITS 1 18238 #define DSC4B0_TUNING_SM_CTRL11_BYPASS_OSX2_SLICER_CAL_SHIFT 0 18239 18240 18241 /**************************************************************************** 18242 * Dsc4b0 :: acq_sm_ctrl9 18243 */ 18244 /* Dsc4b0 :: acq_sm_ctrl9 :: reserved0 [15:13] */ 18245 #define DSC4B0_ACQ_SM_CTRL9_RESERVED0_MASK 0xe000 18246 #define DSC4B0_ACQ_SM_CTRL9_RESERVED0_ALIGN 0 18247 #define DSC4B0_ACQ_SM_CTRL9_RESERVED0_BITS 3 18248 #define DSC4B0_ACQ_SM_CTRL9_RESERVED0_SHIFT 13 18249 18250 /* Dsc4b0 :: acq_sm_ctrl9 :: eee_lfsr_cnt [12:00] */ 18251 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_MASK 0x1fff 18252 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_ALIGN 0 18253 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_BITS 13 18254 #define DSC4B0_ACQ_SM_CTRL9_EEE_LFSR_CNT_SHIFT 0 18255 18256 18257 /**************************************************************************** 18258 * TSC_WC4_TSC_USER4_Dsc5b0 18259 */ 18260 /**************************************************************************** 18261 * Dsc5b0 :: tuning_sm_status0 18262 */ 18263 /* Dsc5b0 :: tuning_sm_status0 :: reserved0 [15:14] */ 18264 #define DSC5B0_TUNING_SM_STATUS0_RESERVED0_MASK 0xc000 18265 #define DSC5B0_TUNING_SM_STATUS0_RESERVED0_ALIGN 0 18266 #define DSC5B0_TUNING_SM_STATUS0_RESERVED0_BITS 2 18267 #define DSC5B0_TUNING_SM_STATUS0_RESERVED0_SHIFT 14 18268 18269 /* Dsc5b0 :: tuning_sm_status0 :: tuning_done [13:13] */ 18270 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_MASK 0x2000 18271 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_ALIGN 0 18272 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_BITS 1 18273 #define DSC5B0_TUNING_SM_STATUS0_TUNING_DONE_SHIFT 13 18274 18275 /* Dsc5b0 :: tuning_sm_status0 :: srch_state [12:09] */ 18276 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_MASK 0x1e00 18277 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_ALIGN 0 18278 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_BITS 4 18279 #define DSC5B0_TUNING_SM_STATUS0_SRCH_STATE_SHIFT 9 18280 18281 /* Dsc5b0 :: tuning_sm_status0 :: tuning_state [08:04] */ 18282 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_MASK 0x01f0 18283 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_ALIGN 0 18284 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_BITS 5 18285 #define DSC5B0_TUNING_SM_STATUS0_TUNING_STATE_SHIFT 4 18286 18287 /* Dsc5b0 :: tuning_sm_status0 :: dsc_state [03:00] */ 18288 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_MASK 0x000f 18289 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_ALIGN 0 18290 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_BITS 4 18291 #define DSC5B0_TUNING_SM_STATUS0_DSC_STATE_SHIFT 0 18292 18293 18294 /**************************************************************************** 18295 * Dsc5b0 :: tuning_sm_status1 18296 */ 18297 /* Dsc5b0 :: tuning_sm_status1 :: reserved0 [15:11] */ 18298 #define DSC5B0_TUNING_SM_STATUS1_RESERVED0_MASK 0xf800 18299 #define DSC5B0_TUNING_SM_STATUS1_RESERVED0_ALIGN 0 18300 #define DSC5B0_TUNING_SM_STATUS1_RESERVED0_BITS 5 18301 #define DSC5B0_TUNING_SM_STATUS1_RESERVED0_SHIFT 11 18302 18303 /* Dsc5b0 :: tuning_sm_status1 :: postc_metric [10:00] */ 18304 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_MASK 0x07ff 18305 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_ALIGN 0 18306 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_BITS 11 18307 #define DSC5B0_TUNING_SM_STATUS1_POSTC_METRIC_SHIFT 0 18308 18309 18310 /**************************************************************************** 18311 * Dsc5b0 :: tuning_sm_status2 18312 */ 18313 /* Dsc5b0 :: tuning_sm_status2 :: reserved0 [15:06] */ 18314 #define DSC5B0_TUNING_SM_STATUS2_RESERVED0_MASK 0xffc0 18315 #define DSC5B0_TUNING_SM_STATUS2_RESERVED0_ALIGN 0 18316 #define DSC5B0_TUNING_SM_STATUS2_RESERVED0_BITS 10 18317 #define DSC5B0_TUNING_SM_STATUS2_RESERVED0_SHIFT 6 18318 18319 /* Dsc5b0 :: tuning_sm_status2 :: dfe_max [05:05] */ 18320 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_MASK 0x0020 18321 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_ALIGN 0 18322 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_BITS 1 18323 #define DSC5B0_TUNING_SM_STATUS2_DFE_MAX_SHIFT 5 18324 18325 /* Dsc5b0 :: tuning_sm_status2 :: dfe_min [04:04] */ 18326 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_MASK 0x0010 18327 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_ALIGN 0 18328 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_BITS 1 18329 #define DSC5B0_TUNING_SM_STATUS2_DFE_MIN_SHIFT 4 18330 18331 /* Dsc5b0 :: tuning_sm_status2 :: vga_max [03:03] */ 18332 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_MASK 0x0008 18333 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_ALIGN 0 18334 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_BITS 1 18335 #define DSC5B0_TUNING_SM_STATUS2_VGA_MAX_SHIFT 3 18336 18337 /* Dsc5b0 :: tuning_sm_status2 :: vga_min [02:02] */ 18338 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_MASK 0x0004 18339 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_ALIGN 0 18340 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_BITS 1 18341 #define DSC5B0_TUNING_SM_STATUS2_VGA_MIN_SHIFT 2 18342 18343 /* Dsc5b0 :: tuning_sm_status2 :: pf_max [01:01] */ 18344 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_MASK 0x0002 18345 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_ALIGN 0 18346 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_BITS 1 18347 #define DSC5B0_TUNING_SM_STATUS2_PF_MAX_SHIFT 1 18348 18349 /* Dsc5b0 :: tuning_sm_status2 :: pf_min [00:00] */ 18350 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_MASK 0x0001 18351 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_ALIGN 0 18352 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_BITS 1 18353 #define DSC5B0_TUNING_SM_STATUS2_PF_MIN_SHIFT 0 18354 18355 18356 /**************************************************************************** 18357 * Dsc5b0 :: tuning_sm_status3 18358 */ 18359 /* Dsc5b0 :: tuning_sm_status3 :: reserved0 [15:11] */ 18360 #define DSC5B0_TUNING_SM_STATUS3_RESERVED0_MASK 0xf800 18361 #define DSC5B0_TUNING_SM_STATUS3_RESERVED0_ALIGN 0 18362 #define DSC5B0_TUNING_SM_STATUS3_RESERVED0_BITS 5 18363 #define DSC5B0_TUNING_SM_STATUS3_RESERVED0_SHIFT 11 18364 18365 /* Dsc5b0 :: tuning_sm_status3 :: trnsum_br_vga [10:00] */ 18366 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_MASK 0x07ff 18367 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_ALIGN 0 18368 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_BITS 11 18369 #define DSC5B0_TUNING_SM_STATUS3_TRNSUM_BR_VGA_SHIFT 0 18370 18371 18372 /**************************************************************************** 18373 * Dsc5b0 :: tuning_sm_status4 18374 */ 18375 /* Dsc5b0 :: tuning_sm_status4 :: reserved0 [15:11] */ 18376 #define DSC5B0_TUNING_SM_STATUS4_RESERVED0_MASK 0xf800 18377 #define DSC5B0_TUNING_SM_STATUS4_RESERVED0_ALIGN 0 18378 #define DSC5B0_TUNING_SM_STATUS4_RESERVED0_BITS 5 18379 #define DSC5B0_TUNING_SM_STATUS4_RESERVED0_SHIFT 11 18380 18381 /* Dsc5b0 :: tuning_sm_status4 :: trnsum_pf [10:00] */ 18382 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_MASK 0x07ff 18383 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_ALIGN 0 18384 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_BITS 11 18385 #define DSC5B0_TUNING_SM_STATUS4_TRNSUM_PF_SHIFT 0 18386 18387 18388 /**************************************************************************** 18389 * Dsc5b0 :: tuning_sm_status5 18390 */ 18391 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_tx_postc [15:15] */ 18392 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_MASK 0x8000 18393 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_ALIGN 0 18394 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_BITS 1 18395 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_TX_POSTC_SHIFT 15 18396 18397 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_pf [14:14] */ 18398 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_MASK 0x4000 18399 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_ALIGN 0 18400 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_BITS 1 18401 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_PF_SHIFT 14 18402 18403 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_vga [13:13] */ 18404 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_MASK 0x2000 18405 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_ALIGN 0 18406 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_BITS 1 18407 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_VGA_SHIFT 13 18408 18409 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_po [12:12] */ 18410 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_MASK 0x1000 18411 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_ALIGN 0 18412 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_BITS 1 18413 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PO_SHIFT 12 18414 18415 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_pe [11:11] */ 18416 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_MASK 0x0800 18417 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_ALIGN 0 18418 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_BITS 1 18419 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_PE_SHIFT 11 18420 18421 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_mo [10:10] */ 18422 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_MASK 0x0400 18423 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_ALIGN 0 18424 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_BITS 1 18425 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_MO_SHIFT 10 18426 18427 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_me [09:09] */ 18428 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_MASK 0x0200 18429 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_ALIGN 0 18430 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_BITS 1 18431 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_ME_SHIFT 9 18432 18433 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_do [08:08] */ 18434 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_MASK 0x0100 18435 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_ALIGN 0 18436 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_BITS 1 18437 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DO_SHIFT 8 18438 18439 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_br_slicer_de [07:07] */ 18440 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_MASK 0x0080 18441 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_ALIGN 0 18442 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_BITS 1 18443 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_BR_SLICER_DE_SHIFT 7 18444 18445 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_tx_postc [06:06] */ 18446 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_MASK 0x0040 18447 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_ALIGN 0 18448 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_BITS 1 18449 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_TX_POSTC_SHIFT 6 18450 18451 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_pf [05:05] */ 18452 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_MASK 0x0020 18453 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_ALIGN 0 18454 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_BITS 1 18455 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_PF_SHIFT 5 18456 18457 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_mo [04:04] */ 18458 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_MASK 0x0010 18459 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_ALIGN 0 18460 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_BITS 1 18461 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_MO_SHIFT 4 18462 18463 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_me [03:03] */ 18464 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_MASK 0x0008 18465 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_ALIGN 0 18466 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_BITS 1 18467 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_ME_SHIFT 3 18468 18469 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_do [02:02] */ 18470 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_MASK 0x0004 18471 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_ALIGN 0 18472 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_BITS 1 18473 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DO_SHIFT 2 18474 18475 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_os_slicer_de [01:01] */ 18476 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_MASK 0x0002 18477 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_ALIGN 0 18478 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_BITS 1 18479 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_OS_SLICER_DE_SHIFT 1 18480 18481 /* Dsc5b0 :: tuning_sm_status5 :: tuning_state_wait_for_lock [00:00] */ 18482 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_MASK 0x0001 18483 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_ALIGN 0 18484 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_BITS 1 18485 #define DSC5B0_TUNING_SM_STATUS5_TUNING_STATE_WAIT_FOR_LOCK_SHIFT 0 18486 18487 18488 /**************************************************************************** 18489 * Dsc5b0 :: tuning_sm_status6 18490 */ 18491 /* Dsc5b0 :: tuning_sm_status6 :: reserved0 [15:12] */ 18492 #define DSC5B0_TUNING_SM_STATUS6_RESERVED0_MASK 0xf000 18493 #define DSC5B0_TUNING_SM_STATUS6_RESERVED0_ALIGN 0 18494 #define DSC5B0_TUNING_SM_STATUS6_RESERVED0_BITS 4 18495 #define DSC5B0_TUNING_SM_STATUS6_RESERVED0_SHIFT 12 18496 18497 /* Dsc5b0 :: tuning_sm_status6 :: tuning_state_hysteresis [11:11] */ 18498 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_MASK 0x0800 18499 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_ALIGN 0 18500 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_BITS 1 18501 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_HYSTERESIS_SHIFT 11 18502 18503 /* Dsc5b0 :: tuning_sm_status6 :: tuning_state_tuning_done [10:10] */ 18504 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_MASK 0x0400 18505 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_ALIGN 0 18506 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_BITS 1 18507 #define DSC5B0_TUNING_SM_STATUS6_TUNING_STATE_TUNING_DONE_SHIFT 10 18508 18509 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_done [09:09] */ 18510 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_MASK 0x0200 18511 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_ALIGN 0 18512 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_BITS 1 18513 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DONE_SHIFT 9 18514 18515 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait_undo_setup [08:08] */ 18516 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_MASK 0x0100 18517 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_ALIGN 0 18518 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_BITS 1 18519 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_UNDO_SETUP_SHIFT 8 18520 18521 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_undo_setup [07:07] */ 18522 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_MASK 0x0080 18523 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_ALIGN 0 18524 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_BITS 1 18525 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_UNDO_SETUP_SHIFT 7 18526 18527 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait_msr [06:06] */ 18528 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_MASK 0x0040 18529 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_ALIGN 0 18530 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_BITS 1 18531 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MSR_SHIFT 6 18532 18533 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_set_msr [05:05] */ 18534 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_MASK 0x0020 18535 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_ALIGN 0 18536 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_BITS 1 18537 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_MSR_SHIFT 5 18538 18539 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait_trn [04:04] */ 18540 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_MASK 0x0010 18541 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_ALIGN 0 18542 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_BITS 1 18543 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_TRN_SHIFT 4 18544 18545 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_set_trn [03:03] */ 18546 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_MASK 0x0008 18547 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_ALIGN 0 18548 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_BITS 1 18549 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SET_TRN_SHIFT 3 18550 18551 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_wait [02:02] */ 18552 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_MASK 0x0004 18553 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_ALIGN 0 18554 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_BITS 1 18555 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_WAIT_SHIFT 2 18556 18557 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_setup [01:01] */ 18558 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_MASK 0x0002 18559 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_ALIGN 0 18560 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_BITS 1 18561 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_SETUP_SHIFT 1 18562 18563 /* Dsc5b0 :: tuning_sm_status6 :: srch_state_srch_disable [00:00] */ 18564 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_MASK 0x0001 18565 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_ALIGN 0 18566 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_BITS 1 18567 #define DSC5B0_TUNING_SM_STATUS6_SRCH_STATE_SRCH_DISABLE_SHIFT 0 18568 18569 18570 /**************************************************************************** 18571 * TSC_WC4_TSC_USER4_CL72 18572 */ 18573 /**************************************************************************** 18574 * CL72 :: xmt_control_register 18575 */ 18576 /* CL72 :: xmt_control_register :: xmt_control_page [15:00] */ 18577 #define CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_MASK 0xffff 18578 #define CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_ALIGN 0 18579 #define CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_BITS 16 18580 #define CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_SHIFT 0 18581 18582 18583 /**************************************************************************** 18584 * CL72 :: rcvd_status_register 18585 */ 18586 /* CL72 :: rcvd_status_register :: rcvd_status_page [15:00] */ 18587 #define CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_MASK 0xffff 18588 #define CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_ALIGN 0 18589 #define CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_BITS 16 18590 #define CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_SHIFT 0 18591 18592 18593 /**************************************************************************** 18594 * CL72 :: tx_fir_tap_register 18595 */ 18596 /* CL72 :: tx_fir_tap_register :: tx_fir_tap_force [15:15] */ 18597 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_MASK 0x8000 18598 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_ALIGN 0 18599 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_BITS 1 18600 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_SHIFT 15 18601 18602 /* CL72 :: tx_fir_tap_register :: tx_fir_tap_post [14:10] */ 18603 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_MASK 0x7c00 18604 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_ALIGN 0 18605 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_BITS 5 18606 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_SHIFT 10 18607 18608 /* CL72 :: tx_fir_tap_register :: tx_fir_tap_main [09:04] */ 18609 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_MASK 0x03f0 18610 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_ALIGN 0 18611 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_BITS 6 18612 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_SHIFT 4 18613 18614 /* CL72 :: tx_fir_tap_register :: tx_fir_tap_pre [03:00] */ 18615 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_MASK 0x000f 18616 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_ALIGN 0 18617 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_BITS 4 18618 #define CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_SHIFT 0 18619 18620 18621 /**************************************************************************** 18622 * CL72 :: misc1_control 18623 */ 18624 /* CL72 :: misc1_control :: link_control_force [15:15] */ 18625 #define CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_MASK 0x8000 18626 #define CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_ALIGN 0 18627 #define CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_BITS 1 18628 #define CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_SHIFT 15 18629 18630 /* CL72 :: misc1_control :: link_control_forceval [14:14] */ 18631 #define CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_MASK 0x4000 18632 #define CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_ALIGN 0 18633 #define CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_BITS 1 18634 #define CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_SHIFT 14 18635 18636 /* CL72 :: misc1_control :: tx_fir_tap_main_kx_init_val [13:08] */ 18637 #define CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_MASK 0x3f00 18638 #define CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_ALIGN 0 18639 #define CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_BITS 6 18640 #define CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_SHIFT 8 18641 18642 /* CL72 :: misc1_control :: tap_default_muxsel_force [07:07] */ 18643 #define CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_MASK 0x0080 18644 #define CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_ALIGN 0 18645 #define CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_BITS 1 18646 #define CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_SHIFT 7 18647 18648 /* CL72 :: misc1_control :: tap_default_muxsel_forceval [06:04] */ 18649 #define CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_MASK 0x0070 18650 #define CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_ALIGN 0 18651 #define CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_BITS 3 18652 #define CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_SHIFT 4 18653 18654 /* CL72 :: misc1_control :: reserved0 [03:02] */ 18655 #define CL72_MISC1_CONTROL_RESERVED0_MASK 0x000c 18656 #define CL72_MISC1_CONTROL_RESERVED0_ALIGN 0 18657 #define CL72_MISC1_CONTROL_RESERVED0_BITS 2 18658 #define CL72_MISC1_CONTROL_RESERVED0_SHIFT 2 18659 18660 /* CL72 :: misc1_control :: tr_coarse_lock [01:01] */ 18661 #define CL72_MISC1_CONTROL_TR_COARSE_LOCK_MASK 0x0002 18662 #define CL72_MISC1_CONTROL_TR_COARSE_LOCK_ALIGN 0 18663 #define CL72_MISC1_CONTROL_TR_COARSE_LOCK_BITS 1 18664 #define CL72_MISC1_CONTROL_TR_COARSE_LOCK_SHIFT 1 18665 18666 /* CL72 :: misc1_control :: rx_trained [00:00] */ 18667 #define CL72_MISC1_CONTROL_RX_TRAINED_MASK 0x0001 18668 #define CL72_MISC1_CONTROL_RX_TRAINED_ALIGN 0 18669 #define CL72_MISC1_CONTROL_RX_TRAINED_BITS 1 18670 #define CL72_MISC1_CONTROL_RX_TRAINED_SHIFT 0 18671 18672 18673 /**************************************************************************** 18674 * CL72 :: misc2_control 18675 */ 18676 /* CL72 :: misc2_control :: reserved0 [15:14] */ 18677 #define CL72_MISC2_CONTROL_RESERVED0_MASK 0xc000 18678 #define CL72_MISC2_CONTROL_RESERVED0_ALIGN 0 18679 #define CL72_MISC2_CONTROL_RESERVED0_BITS 2 18680 #define CL72_MISC2_CONTROL_RESERVED0_SHIFT 14 18681 18682 /* CL72 :: misc2_control :: SW_actual_speed [13:08] */ 18683 #define CL72_MISC2_CONTROL_SW_ACTUAL_SPEED_MASK 0x3f00 18684 #define CL72_MISC2_CONTROL_SW_ACTUAL_SPEED_ALIGN 0 18685 #define CL72_MISC2_CONTROL_SW_ACTUAL_SPEED_BITS 6 18686 #define CL72_MISC2_CONTROL_SW_ACTUAL_SPEED_SHIFT 8 18687 18688 /* CL72 :: misc2_control :: main_tap_adjust_force [07:07] */ 18689 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_MASK 0x0080 18690 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_ALIGN 0 18691 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_BITS 1 18692 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_SHIFT 7 18693 18694 /* CL72 :: misc2_control :: main_tap_adjust_forceval [06:06] */ 18695 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_MASK 0x0040 18696 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_ALIGN 0 18697 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_BITS 1 18698 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_SHIFT 6 18699 18700 /* CL72 :: misc2_control :: main_tap_adjust_en [05:05] */ 18701 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_MASK 0x0020 18702 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_ALIGN 0 18703 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_BITS 1 18704 #define CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_SHIFT 5 18705 18706 /* CL72 :: misc2_control :: newpg_rcvd_override [04:04] */ 18707 #define CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_MASK 0x0010 18708 #define CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_ALIGN 0 18709 #define CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_BITS 1 18710 #define CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_SHIFT 4 18711 18712 /* CL72 :: misc2_control :: newpg_rcvd_load [03:03] */ 18713 #define CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_MASK 0x0008 18714 #define CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_ALIGN 0 18715 #define CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_BITS 1 18716 #define CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_SHIFT 3 18717 18718 /* CL72 :: misc2_control :: inc_dec_val_sel [02:02] */ 18719 #define CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_MASK 0x0004 18720 #define CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_ALIGN 0 18721 #define CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_BITS 1 18722 #define CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_SHIFT 2 18723 18724 /* CL72 :: misc2_control :: reserved1 [01:00] */ 18725 #define CL72_MISC2_CONTROL_RESERVED1_MASK 0x0003 18726 #define CL72_MISC2_CONTROL_RESERVED1_ALIGN 0 18727 #define CL72_MISC2_CONTROL_RESERVED1_BITS 2 18728 #define CL72_MISC2_CONTROL_RESERVED1_SHIFT 0 18729 18730 18731 /**************************************************************************** 18732 * CL72 :: debug_2_register 18733 */ 18734 /* CL72 :: debug_2_register :: reserved0 [15:15] */ 18735 #define CL72_DEBUG_2_REGISTER_RESERVED0_MASK 0x8000 18736 #define CL72_DEBUG_2_REGISTER_RESERVED0_ALIGN 0 18737 #define CL72_DEBUG_2_REGISTER_RESERVED0_BITS 1 18738 #define CL72_DEBUG_2_REGISTER_RESERVED0_SHIFT 15 18739 18740 /* CL72 :: debug_2_register :: dis_max_wait_timer_override [14:14] */ 18741 #define CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_OVERRIDE_MASK 0x4000 18742 #define CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_OVERRIDE_ALIGN 0 18743 #define CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_OVERRIDE_BITS 1 18744 #define CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_OVERRIDE_SHIFT 14 18745 18746 /* CL72 :: debug_2_register :: strict_marker_chk [13:13] */ 18747 #define CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_MASK 0x2000 18748 #define CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_ALIGN 0 18749 #define CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_BITS 1 18750 #define CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_SHIFT 13 18751 18752 /* CL72 :: debug_2_register :: strict_dme_chk [12:12] */ 18753 #define CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_MASK 0x1000 18754 #define CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_ALIGN 0 18755 #define CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_BITS 1 18756 #define CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_SHIFT 12 18757 18758 /* CL72 :: debug_2_register :: dis_max_wait_timer [11:11] */ 18759 #define CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_MASK 0x0800 18760 #define CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_ALIGN 0 18761 #define CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_BITS 1 18762 #define CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_SHIFT 11 18763 18764 /* CL72 :: debug_2_register :: reserved1 [10:08] */ 18765 #define CL72_DEBUG_2_REGISTER_RESERVED1_MASK 0x0700 18766 #define CL72_DEBUG_2_REGISTER_RESERVED1_ALIGN 0 18767 #define CL72_DEBUG_2_REGISTER_RESERVED1_BITS 3 18768 #define CL72_DEBUG_2_REGISTER_RESERVED1_SHIFT 8 18769 18770 /* CL72 :: debug_2_register :: tr_coarse_lock_force [07:07] */ 18771 #define CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_MASK 0x0080 18772 #define CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_ALIGN 0 18773 #define CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_BITS 1 18774 #define CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_SHIFT 7 18775 18776 /* CL72 :: debug_2_register :: reserved2 [06:05] */ 18777 #define CL72_DEBUG_2_REGISTER_RESERVED2_MASK 0x0060 18778 #define CL72_DEBUG_2_REGISTER_RESERVED2_ALIGN 0 18779 #define CL72_DEBUG_2_REGISTER_RESERVED2_BITS 2 18780 #define CL72_DEBUG_2_REGISTER_RESERVED2_SHIFT 5 18781 18782 /* CL72 :: debug_2_register :: bad_marker_cnt [04:02] */ 18783 #define CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_MASK 0x001c 18784 #define CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_ALIGN 0 18785 #define CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_BITS 3 18786 #define CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_SHIFT 2 18787 18788 /* CL72 :: debug_2_register :: good_marker_cnt [01:00] */ 18789 #define CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_MASK 0x0003 18790 #define CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_ALIGN 0 18791 #define CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_BITS 2 18792 #define CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_SHIFT 0 18793 18794 18795 /**************************************************************************** 18796 * CL72 :: debug_3_register 18797 */ 18798 /* CL72 :: debug_3_register :: reserved0 [15:15] */ 18799 #define CL72_DEBUG_3_REGISTER_RESERVED0_MASK 0x8000 18800 #define CL72_DEBUG_3_REGISTER_RESERVED0_ALIGN 0 18801 #define CL72_DEBUG_3_REGISTER_RESERVED0_BITS 1 18802 #define CL72_DEBUG_3_REGISTER_RESERVED0_SHIFT 15 18803 18804 /* CL72 :: debug_3_register :: ctrl_frame_dly [14:11] */ 18805 #define CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_MASK 0x7800 18806 #define CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_ALIGN 0 18807 #define CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_BITS 4 18808 #define CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_SHIFT 11 18809 18810 /* CL72 :: debug_3_register :: random_seed [10:00] */ 18811 #define CL72_DEBUG_3_REGISTER_RANDOM_SEED_MASK 0x07ff 18812 #define CL72_DEBUG_3_REGISTER_RANDOM_SEED_ALIGN 0 18813 #define CL72_DEBUG_3_REGISTER_RANDOM_SEED_BITS 11 18814 #define CL72_DEBUG_3_REGISTER_RANDOM_SEED_SHIFT 0 18815 18816 18817 /**************************************************************************** 18818 * CL72 :: debug_4_register 18819 */ 18820 /* CL72 :: debug_4_register :: reserved0 [15:14] */ 18821 #define CL72_DEBUG_4_REGISTER_RESERVED0_MASK 0xc000 18822 #define CL72_DEBUG_4_REGISTER_RESERVED0_ALIGN 0 18823 #define CL72_DEBUG_4_REGISTER_RESERVED0_BITS 2 18824 #define CL72_DEBUG_4_REGISTER_RESERVED0_SHIFT 14 18825 18826 /* CL72 :: debug_4_register :: brcm_mode_force [13:13] */ 18827 #define CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_MASK 0x2000 18828 #define CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_ALIGN 0 18829 #define CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_BITS 1 18830 #define CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_SHIFT 13 18831 18832 /* CL72 :: debug_4_register :: brcm_mode_forceval [12:12] */ 18833 #define CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_MASK 0x1000 18834 #define CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_ALIGN 0 18835 #define CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_BITS 1 18836 #define CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_SHIFT 12 18837 18838 /* CL72 :: debug_4_register :: v2_constraint_dis [11:11] */ 18839 #define CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_MASK 0x0800 18840 #define CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_ALIGN 0 18841 #define CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_BITS 1 18842 #define CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_SHIFT 11 18843 18844 /* CL72 :: debug_4_register :: tap_v2_val [10:06] */ 18845 #define CL72_DEBUG_4_REGISTER_TAP_V2_VAL_MASK 0x07c0 18846 #define CL72_DEBUG_4_REGISTER_TAP_V2_VAL_ALIGN 0 18847 #define CL72_DEBUG_4_REGISTER_TAP_V2_VAL_BITS 5 18848 #define CL72_DEBUG_4_REGISTER_TAP_V2_VAL_SHIFT 6 18849 18850 /* CL72 :: debug_4_register :: reserved1 [05:04] */ 18851 #define CL72_DEBUG_4_REGISTER_RESERVED1_MASK 0x0030 18852 #define CL72_DEBUG_4_REGISTER_RESERVED1_ALIGN 0 18853 #define CL72_DEBUG_4_REGISTER_RESERVED1_BITS 2 18854 #define CL72_DEBUG_4_REGISTER_RESERVED1_SHIFT 4 18855 18856 /* CL72 :: debug_4_register :: sigdet_force [03:03] */ 18857 #define CL72_DEBUG_4_REGISTER_SIGDET_FORCE_MASK 0x0008 18858 #define CL72_DEBUG_4_REGISTER_SIGDET_FORCE_ALIGN 0 18859 #define CL72_DEBUG_4_REGISTER_SIGDET_FORCE_BITS 1 18860 #define CL72_DEBUG_4_REGISTER_SIGDET_FORCE_SHIFT 3 18861 18862 /* CL72 :: debug_4_register :: reserved2 [02:01] */ 18863 #define CL72_DEBUG_4_REGISTER_RESERVED2_MASK 0x0006 18864 #define CL72_DEBUG_4_REGISTER_RESERVED2_ALIGN 0 18865 #define CL72_DEBUG_4_REGISTER_RESERVED2_BITS 2 18866 #define CL72_DEBUG_4_REGISTER_RESERVED2_SHIFT 1 18867 18868 /* CL72 :: debug_4_register :: ppm_offset_en [00:00] */ 18869 #define CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_MASK 0x0001 18870 #define CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_ALIGN 0 18871 #define CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_BITS 1 18872 #define CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_SHIFT 0 18873 18874 18875 /**************************************************************************** 18876 * CL72 :: cl72_ld_status_page 18877 */ 18878 /* CL72 :: cl72_ld_status_page :: ld_status_page [15:00] */ 18879 #define CL72_CL72_LD_STATUS_PAGE_LD_STATUS_PAGE_MASK 0xffff 18880 #define CL72_CL72_LD_STATUS_PAGE_LD_STATUS_PAGE_ALIGN 0 18881 #define CL72_CL72_LD_STATUS_PAGE_LD_STATUS_PAGE_BITS 16 18882 #define CL72_CL72_LD_STATUS_PAGE_LD_STATUS_PAGE_SHIFT 0 18883 18884 18885 /**************************************************************************** 18886 * CL72 :: cl72_lp_control_page 18887 */ 18888 /* CL72 :: cl72_lp_control_page :: lp_control_page [15:00] */ 18889 #define CL72_CL72_LP_CONTROL_PAGE_LP_CONTROL_PAGE_MASK 0xffff 18890 #define CL72_CL72_LP_CONTROL_PAGE_LP_CONTROL_PAGE_ALIGN 0 18891 #define CL72_CL72_LP_CONTROL_PAGE_LP_CONTROL_PAGE_BITS 16 18892 #define CL72_CL72_LP_CONTROL_PAGE_LP_CONTROL_PAGE_SHIFT 0 18893 18894 18895 /**************************************************************************** 18896 * CL72 :: cl72_newpg_rcvd_override_page 18897 */ 18898 /* CL72 :: cl72_newpg_rcvd_override_page :: override_lp_control_page [15:00] */ 18899 #define CL72_CL72_NEWPG_RCVD_OVERRIDE_PAGE_OVERRIDE_LP_CONTROL_PAGE_MASK 0xffff 18900 #define CL72_CL72_NEWPG_RCVD_OVERRIDE_PAGE_OVERRIDE_LP_CONTROL_PAGE_ALIGN 0 18901 #define CL72_CL72_NEWPG_RCVD_OVERRIDE_PAGE_OVERRIDE_LP_CONTROL_PAGE_BITS 16 18902 #define CL72_CL72_NEWPG_RCVD_OVERRIDE_PAGE_OVERRIDE_LP_CONTROL_PAGE_SHIFT 0 18903 18904 18905 /**************************************************************************** 18906 * CL72 :: cl72_ready_for_cmd_register 18907 */ 18908 /* CL72 :: cl72_ready_for_cmd_register :: reserved0 [15:01] */ 18909 #define CL72_CL72_READY_FOR_CMD_REGISTER_RESERVED0_MASK 0xfffe 18910 #define CL72_CL72_READY_FOR_CMD_REGISTER_RESERVED0_ALIGN 0 18911 #define CL72_CL72_READY_FOR_CMD_REGISTER_RESERVED0_BITS 15 18912 #define CL72_CL72_READY_FOR_CMD_REGISTER_RESERVED0_SHIFT 1 18913 18914 /* CL72 :: cl72_ready_for_cmd_register :: cl72_ready_for_cmd [00:00] */ 18915 #define CL72_CL72_READY_FOR_CMD_REGISTER_CL72_READY_FOR_CMD_MASK 0x0001 18916 #define CL72_CL72_READY_FOR_CMD_REGISTER_CL72_READY_FOR_CMD_ALIGN 0 18917 #define CL72_CL72_READY_FOR_CMD_REGISTER_CL72_READY_FOR_CMD_BITS 1 18918 #define CL72_CL72_READY_FOR_CMD_REGISTER_CL72_READY_FOR_CMD_SHIFT 0 18919 18920 18921 /**************************************************************************** 18922 * TSC_WC4_TSC_USER4_UCSS_X4 18923 */ 18924 /**************************************************************************** 18925 * UCSS_X4 :: firmware_mode 18926 */ 18927 /* UCSS_X4 :: firmware_mode :: reserved0 [15:04] */ 18928 #define UCSS_X4_FIRMWARE_MODE_RESERVED0_MASK 0xfff0 18929 #define UCSS_X4_FIRMWARE_MODE_RESERVED0_ALIGN 0 18930 #define UCSS_X4_FIRMWARE_MODE_RESERVED0_BITS 12 18931 #define UCSS_X4_FIRMWARE_MODE_RESERVED0_SHIFT 4 18932 18933 /* UCSS_X4 :: firmware_mode :: firmware_mode [03:00] */ 18934 #define UCSS_X4_FIRMWARE_MODE_FIRMWARE_MODE_MASK 0x000f 18935 #define UCSS_X4_FIRMWARE_MODE_FIRMWARE_MODE_ALIGN 0 18936 #define UCSS_X4_FIRMWARE_MODE_FIRMWARE_MODE_BITS 4 18937 #define UCSS_X4_FIRMWARE_MODE_FIRMWARE_MODE_SHIFT 0 18938 #define UCSS_X4_FIRMWARE_MODE_FIRMWARE_MODE_DEFAULT 0 18939 #define UCSS_X4_FIRMWARE_MODE_FIRMWARE_MODE_SFP_OPT_LR 1 18940 #define UCSS_X4_FIRMWARE_MODE_FIRMWARE_MODE_SFP_DAC 2 18941 #define UCSS_X4_FIRMWARE_MODE_FIRMWARE_MODE_XLAUI 3 18942 #define UCSS_X4_FIRMWARE_MODE_FIRMWARE_MODE_LONG_CH_6G 4 18943 18944 18945 /**************************************************************************** 18946 * UCSS_X4 :: gpio_ctrl 18947 */ 18948 /* UCSS_X4 :: gpio_ctrl :: GPIO_CTRL [15:00] */ 18949 #define UCSS_X4_GPIO_CTRL_GPIO_CTRL_MASK 0xffff 18950 #define UCSS_X4_GPIO_CTRL_GPIO_CTRL_ALIGN 0 18951 #define UCSS_X4_GPIO_CTRL_GPIO_CTRL_BITS 16 18952 #define UCSS_X4_GPIO_CTRL_GPIO_CTRL_SHIFT 0 18953 18954 18955 /**************************************************************************** 18956 * UCSS_X4 :: gpio_sts 18957 */ 18958 /* UCSS_X4 :: gpio_sts :: GPIO_STS [15:00] */ 18959 #define UCSS_X4_GPIO_STS_GPIO_STS_MASK 0xffff 18960 #define UCSS_X4_GPIO_STS_GPIO_STS_ALIGN 0 18961 #define UCSS_X4_GPIO_STS_GPIO_STS_BITS 16 18962 #define UCSS_X4_GPIO_STS_GPIO_STS_SHIFT 0 18963 18964 18965 /**************************************************************************** 18966 * UCSS_X4 :: gpr_type 18967 */ 18968 /* UCSS_X4 :: gpr_type :: UC_GPR [15:00] */ 18969 #define UCSS_X4_GPR_TYPE_UC_GPR_MASK 0xffff 18970 #define UCSS_X4_GPR_TYPE_UC_GPR_ALIGN 0 18971 #define UCSS_X4_GPR_TYPE_UC_GPR_BITS 16 18972 #define UCSS_X4_GPR_TYPE_UC_GPR_SHIFT 0 18973 18974 18975 /**************************************************************************** 18976 * TSC_WC4_TSC_USER4_Digital 18977 */ 18978 /**************************************************************************** 18979 * Digital :: Control1000X1 18980 */ 18981 /* Digital :: Control1000X1 :: reserved0 [15:10] */ 18982 #define DIGITAL_CONTROL1000X1_RESERVED0_MASK 0xfc00 18983 #define DIGITAL_CONTROL1000X1_RESERVED0_ALIGN 0 18984 #define DIGITAL_CONTROL1000X1_RESERVED0_BITS 6 18985 #define DIGITAL_CONTROL1000X1_RESERVED0_SHIFT 10 18986 18987 /* Digital :: Control1000X1 :: zero_comma_detector_phase [09:09] */ 18988 #define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200 18989 #define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0 18990 #define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1 18991 #define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9 18992 18993 /* Digital :: Control1000X1 :: comma_det_en [08:08] */ 18994 #define DIGITAL_CONTROL1000X1_COMMA_DET_EN_MASK 0x0100 18995 #define DIGITAL_CONTROL1000X1_COMMA_DET_EN_ALIGN 0 18996 #define DIGITAL_CONTROL1000X1_COMMA_DET_EN_BITS 1 18997 #define DIGITAL_CONTROL1000X1_COMMA_DET_EN_SHIFT 8 18998 18999 /* Digital :: Control1000X1 :: reserved1 [07:00] */ 19000 #define DIGITAL_CONTROL1000X1_RESERVED1_MASK 0x00ff 19001 #define DIGITAL_CONTROL1000X1_RESERVED1_ALIGN 0 19002 #define DIGITAL_CONTROL1000X1_RESERVED1_BITS 8 19003 #define DIGITAL_CONTROL1000X1_RESERVED1_SHIFT 0 19004 19005 19006 /**************************************************************************** 19007 * Digital :: Control1000X2 19008 */ 19009 /* Digital :: Control1000X2 :: disable_extend_fdx_only [15:15] */ 19010 #define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK 0x8000 19011 #define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN 0 19012 #define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS 1 19013 #define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT 15 19014 19015 /* Digital :: Control1000X2 :: clear_ber_counter [14:14] */ 19016 #define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_MASK 0x4000 19017 #define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN 0 19018 #define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_BITS 1 19019 #define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT 14 19020 19021 /* Digital :: Control1000X2 :: reserved0 [13:09] */ 19022 #define DIGITAL_CONTROL1000X2_RESERVED0_MASK 0x3e00 19023 #define DIGITAL_CONTROL1000X2_RESERVED0_ALIGN 0 19024 #define DIGITAL_CONTROL1000X2_RESERVED0_BITS 5 19025 #define DIGITAL_CONTROL1000X2_RESERVED0_SHIFT 9 19026 19027 /* Digital :: Control1000X2 :: disable_TRRR_generation [08:08] */ 19028 #define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK 0x0100 19029 #define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN 0 19030 #define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS 1 19031 #define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT 8 19032 19033 /* Digital :: Control1000X2 :: disable_carrier_extend [07:07] */ 19034 #define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK 0x0080 19035 #define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN 0 19036 #define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS 1 19037 #define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT 7 19038 19039 /* Digital :: Control1000X2 :: reserved1 [06:05] */ 19040 #define DIGITAL_CONTROL1000X2_RESERVED1_MASK 0x0060 19041 #define DIGITAL_CONTROL1000X2_RESERVED1_ALIGN 0 19042 #define DIGITAL_CONTROL1000X2_RESERVED1_BITS 2 19043 #define DIGITAL_CONTROL1000X2_RESERVED1_SHIFT 5 19044 19045 /* Digital :: Control1000X2 :: disable_remote_fault_reporting [04:04] */ 19046 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_REPORTING_MASK 0x0010 19047 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_REPORTING_ALIGN 0 19048 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_REPORTING_BITS 1 19049 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_REPORTING_SHIFT 4 19050 19051 /* Digital :: Control1000X2 :: enable_autoneg_err_timer [03:03] */ 19052 #define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK 0x0008 19053 #define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0 19054 #define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS 1 19055 #define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3 19056 19057 /* Digital :: Control1000X2 :: filter_force_link [02:02] */ 19058 #define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_MASK 0x0004 19059 #define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN 0 19060 #define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_BITS 1 19061 #define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT 2 19062 19063 /* Digital :: Control1000X2 :: reserved2 [01:00] */ 19064 #define DIGITAL_CONTROL1000X2_RESERVED2_MASK 0x0003 19065 #define DIGITAL_CONTROL1000X2_RESERVED2_ALIGN 0 19066 #define DIGITAL_CONTROL1000X2_RESERVED2_BITS 2 19067 #define DIGITAL_CONTROL1000X2_RESERVED2_SHIFT 0 19068 19069 19070 /**************************************************************************** 19071 * Digital :: Control1000X4 19072 */ 19073 /* Digital :: Control1000X4 :: reserved0 [15:12] */ 19074 #define DIGITAL_CONTROL1000X4_RESERVED0_MASK 0xf000 19075 #define DIGITAL_CONTROL1000X4_RESERVED0_ALIGN 0 19076 #define DIGITAL_CONTROL1000X4_RESERVED0_BITS 4 19077 #define DIGITAL_CONTROL1000X4_RESERVED0_SHIFT 12 19078 19079 /* Digital :: Control1000X4 :: tx_config_reg_sel [11:11] */ 19080 #define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK 0x0800 19081 #define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN 0 19082 #define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS 1 19083 #define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT 11 19084 19085 /* Digital :: Control1000X4 :: reserved1 [10:10] */ 19086 #define DIGITAL_CONTROL1000X4_RESERVED1_MASK 0x0400 19087 #define DIGITAL_CONTROL1000X4_RESERVED1_ALIGN 0 19088 #define DIGITAL_CONTROL1000X4_RESERVED1_BITS 1 19089 #define DIGITAL_CONTROL1000X4_RESERVED1_SHIFT 10 19090 19091 /* Digital :: Control1000X4 :: clear_linkdown [09:09] */ 19092 #define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_MASK 0x0200 19093 #define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN 0 19094 #define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_BITS 1 19095 #define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT 9 19096 19097 /* Digital :: Control1000X4 :: latch_linkdown_enable [08:08] */ 19098 #define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK 0x0100 19099 #define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN 0 19100 #define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS 1 19101 #define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT 8 19102 19103 /* Digital :: Control1000X4 :: link_force [07:07] */ 19104 #define DIGITAL_CONTROL1000X4_LINK_FORCE_MASK 0x0080 19105 #define DIGITAL_CONTROL1000X4_LINK_FORCE_ALIGN 0 19106 #define DIGITAL_CONTROL1000X4_LINK_FORCE_BITS 1 19107 #define DIGITAL_CONTROL1000X4_LINK_FORCE_SHIFT 7 19108 19109 /* Digital :: Control1000X4 :: reserved2 [06:03] */ 19110 #define DIGITAL_CONTROL1000X4_RESERVED2_MASK 0x0078 19111 #define DIGITAL_CONTROL1000X4_RESERVED2_ALIGN 0 19112 #define DIGITAL_CONTROL1000X4_RESERVED2_BITS 4 19113 #define DIGITAL_CONTROL1000X4_RESERVED2_SHIFT 3 19114 19115 /* Digital :: Control1000X4 :: MiscRxStatus_sel [02:00] */ 19116 #define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_MASK 0x0007 19117 #define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN 0 19118 #define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_BITS 3 19119 #define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT 0 19120 19121 19122 /**************************************************************************** 19123 * Digital :: Status1000X1 19124 */ 19125 /* Digital :: Status1000X1 :: reserved0 [15:12] */ 19126 #define DIGITAL_STATUS1000X1_RESERVED0_MASK 0xf000 19127 #define DIGITAL_STATUS1000X1_RESERVED0_ALIGN 0 19128 #define DIGITAL_STATUS1000X1_RESERVED0_BITS 4 19129 #define DIGITAL_STATUS1000X1_RESERVED0_SHIFT 12 19130 19131 /* Digital :: Status1000X1 :: tx_err_detected [11:11] */ 19132 #define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_MASK 0x0800 19133 #define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_ALIGN 0 19134 #define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_BITS 1 19135 #define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_SHIFT 11 19136 19137 /* Digital :: Status1000X1 :: rx_err_detected [10:10] */ 19138 #define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_MASK 0x0400 19139 #define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_ALIGN 0 19140 #define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_BITS 1 19141 #define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_SHIFT 10 19142 19143 /* Digital :: Status1000X1 :: reserved1 [09:08] */ 19144 #define DIGITAL_STATUS1000X1_RESERVED1_MASK 0x0300 19145 #define DIGITAL_STATUS1000X1_RESERVED1_ALIGN 0 19146 #define DIGITAL_STATUS1000X1_RESERVED1_BITS 2 19147 #define DIGITAL_STATUS1000X1_RESERVED1_SHIFT 8 19148 19149 /* Digital :: Status1000X1 :: link_status_change [07:07] */ 19150 #define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_MASK 0x0080 19151 #define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN 0 19152 #define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_BITS 1 19153 #define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT 7 19154 19155 /* Digital :: Status1000X1 :: reserved2 [06:00] */ 19156 #define DIGITAL_STATUS1000X1_RESERVED2_MASK 0x007f 19157 #define DIGITAL_STATUS1000X1_RESERVED2_ALIGN 0 19158 #define DIGITAL_STATUS1000X1_RESERVED2_BITS 7 19159 #define DIGITAL_STATUS1000X1_RESERVED2_SHIFT 0 19160 19161 19162 /**************************************************************************** 19163 * Digital :: BadCodeGroup 19164 */ 19165 /* Digital :: BadCodeGroup :: badCodeGroups [15:08] */ 19166 #define DIGITAL_BADCODEGROUP_BADCODEGROUPS_MASK 0xff00 19167 #define DIGITAL_BADCODEGROUP_BADCODEGROUPS_ALIGN 0 19168 #define DIGITAL_BADCODEGROUP_BADCODEGROUPS_BITS 8 19169 #define DIGITAL_BADCODEGROUP_BADCODEGROUPS_SHIFT 8 19170 19171 /* Digital :: BadCodeGroup :: reserved0 [07:00] */ 19172 #define DIGITAL_BADCODEGROUP_RESERVED0_MASK 0x00ff 19173 #define DIGITAL_BADCODEGROUP_RESERVED0_ALIGN 0 19174 #define DIGITAL_BADCODEGROUP_RESERVED0_BITS 8 19175 #define DIGITAL_BADCODEGROUP_RESERVED0_SHIFT 0 19176 19177 19178 /**************************************************************************** 19179 * Digital :: Misc2 19180 */ 19181 /* Digital :: Misc2 :: reserved0 [15:10] */ 19182 #define DIGITAL_MISC2_RESERVED0_MASK 0xfc00 19183 #define DIGITAL_MISC2_RESERVED0_ALIGN 0 19184 #define DIGITAL_MISC2_RESERVED0_BITS 6 19185 #define DIGITAL_MISC2_RESERVED0_SHIFT 10 19186 19187 /* Digital :: Misc2 :: clk41_bypass [09:09] */ 19188 #define DIGITAL_MISC2_CLK41_BYPASS_MASK 0x0200 19189 #define DIGITAL_MISC2_CLK41_BYPASS_ALIGN 0 19190 #define DIGITAL_MISC2_CLK41_BYPASS_BITS 1 19191 #define DIGITAL_MISC2_CLK41_BYPASS_SHIFT 9 19192 19193 /* Digital :: Misc2 :: reserved1 [08:04] */ 19194 #define DIGITAL_MISC2_RESERVED1_MASK 0x01f0 19195 #define DIGITAL_MISC2_RESERVED1_ALIGN 0 19196 #define DIGITAL_MISC2_RESERVED1_BITS 5 19197 #define DIGITAL_MISC2_RESERVED1_SHIFT 4 19198 19199 /* Digital :: Misc2 :: an_txdisablePhase [03:03] */ 19200 #define DIGITAL_MISC2_AN_TXDISABLEPHASE_MASK 0x0008 19201 #define DIGITAL_MISC2_AN_TXDISABLEPHASE_ALIGN 0 19202 #define DIGITAL_MISC2_AN_TXDISABLEPHASE_BITS 1 19203 #define DIGITAL_MISC2_AN_TXDISABLEPHASE_SHIFT 3 19204 19205 /* Digital :: Misc2 :: reserved2 [02:00] */ 19206 #define DIGITAL_MISC2_RESERVED2_MASK 0x0007 19207 #define DIGITAL_MISC2_RESERVED2_ALIGN 0 19208 #define DIGITAL_MISC2_RESERVED2_BITS 3 19209 #define DIGITAL_MISC2_RESERVED2_SHIFT 0 19210 19211 19212 /**************************************************************************** 19213 * Digital :: spare 19214 */ 19215 /* Digital :: spare :: reserved0 [15:08] */ 19216 #define DIGITAL_SPARE_RESERVED0_MASK 0xff00 19217 #define DIGITAL_SPARE_RESERVED0_ALIGN 0 19218 #define DIGITAL_SPARE_RESERVED0_BITS 8 19219 #define DIGITAL_SPARE_RESERVED0_SHIFT 8 19220 19221 /* Digital :: spare :: spare [07:00] */ 19222 #define DIGITAL_SPARE_SPARE_MASK 0x00ff 19223 #define DIGITAL_SPARE_SPARE_ALIGN 0 19224 #define DIGITAL_SPARE_SPARE_BITS 8 19225 #define DIGITAL_SPARE_SPARE_SHIFT 0 19226 19227 19228 /**************************************************************************** 19229 * TSC_WC4_TSC_USER4_Digital5 19230 */ 19231 /**************************************************************************** 19232 * Digital5 :: Misc6 19233 */ 19234 /* Digital5 :: Misc6 :: indch_an_ckswitch_tmr_dis [15:15] */ 19235 #define DIGITAL5_MISC6_INDCH_AN_CKSWITCH_TMR_DIS_MASK 0x8000 19236 #define DIGITAL5_MISC6_INDCH_AN_CKSWITCH_TMR_DIS_ALIGN 0 19237 #define DIGITAL5_MISC6_INDCH_AN_CKSWITCH_TMR_DIS_BITS 1 19238 #define DIGITAL5_MISC6_INDCH_AN_CKSWITCH_TMR_DIS_SHIFT 15 19239 19240 /* Digital5 :: Misc6 :: brcm6466_cl49_in_all_mode_cya [14:14] */ 19241 #define DIGITAL5_MISC6_BRCM6466_CL49_IN_ALL_MODE_CYA_MASK 0x4000 19242 #define DIGITAL5_MISC6_BRCM6466_CL49_IN_ALL_MODE_CYA_ALIGN 0 19243 #define DIGITAL5_MISC6_BRCM6466_CL49_IN_ALL_MODE_CYA_BITS 1 19244 #define DIGITAL5_MISC6_BRCM6466_CL49_IN_ALL_MODE_CYA_SHIFT 14 19245 19246 /* Digital5 :: Misc6 :: reserved0 [13:09] */ 19247 #define DIGITAL5_MISC6_RESERVED0_MASK 0x3e00 19248 #define DIGITAL5_MISC6_RESERVED0_ALIGN 0 19249 #define DIGITAL5_MISC6_RESERVED0_BITS 5 19250 #define DIGITAL5_MISC6_RESERVED0_SHIFT 9 19251 19252 /* Digital5 :: Misc6 :: rx_os8_frst_SM [08:08] */ 19253 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_MASK 0x0100 19254 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_ALIGN 0 19255 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_BITS 1 19256 #define DIGITAL5_MISC6_RX_OS8_FRST_SM_SHIFT 8 19257 19258 /* Digital5 :: Misc6 :: reserved1 [07:05] */ 19259 #define DIGITAL5_MISC6_RESERVED1_MASK 0x00e0 19260 #define DIGITAL5_MISC6_RESERVED1_ALIGN 0 19261 #define DIGITAL5_MISC6_RESERVED1_BITS 3 19262 #define DIGITAL5_MISC6_RESERVED1_SHIFT 5 19263 19264 /* Digital5 :: Misc6 :: rx_os8_os3_alt_bits_cya [04:04] */ 19265 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_MASK 0x0010 19266 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_ALIGN 0 19267 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_BITS 1 19268 #define DIGITAL5_MISC6_RX_OS8_OS3_ALT_BITS_CYA_SHIFT 4 19269 19270 /* Digital5 :: Misc6 :: reserved2 [03:00] */ 19271 #define DIGITAL5_MISC6_RESERVED2_MASK 0x000f 19272 #define DIGITAL5_MISC6_RESERVED2_ALIGN 0 19273 #define DIGITAL5_MISC6_RESERVED2_BITS 4 19274 #define DIGITAL5_MISC6_RESERVED2_SHIFT 0 19275 19276 19277 /**************************************************************************** 19278 * TSC_WC4_TSC_USER4_CL49 19279 */ 19280 /**************************************************************************** 19281 * CL49 :: cl49_bercnt 19282 */ 19283 /* CL49 :: cl49_bercnt :: reserved0 [15:11] */ 19284 #define CL49_CL49_BERCNT_RESERVED0_MASK 0xf800 19285 #define CL49_CL49_BERCNT_RESERVED0_ALIGN 0 19286 #define CL49_CL49_BERCNT_RESERVED0_BITS 5 19287 #define CL49_CL49_BERCNT_RESERVED0_SHIFT 11 19288 19289 /* CL49 :: cl49_bercnt :: IdleErrorCount_en [10:10] */ 19290 #define CL49_CL49_BERCNT_IDLEERRORCOUNT_EN_MASK 0x0400 19291 #define CL49_CL49_BERCNT_IDLEERRORCOUNT_EN_ALIGN 0 19292 #define CL49_CL49_BERCNT_IDLEERRORCOUNT_EN_BITS 1 19293 #define CL49_CL49_BERCNT_IDLEERRORCOUNT_EN_SHIFT 10 19294 19295 /* CL49 :: cl49_bercnt :: reserved1 [09:00] */ 19296 #define CL49_CL49_BERCNT_RESERVED1_MASK 0x03ff 19297 #define CL49_CL49_BERCNT_RESERVED1_ALIGN 0 19298 #define CL49_CL49_BERCNT_RESERVED1_BITS 10 19299 #define CL49_CL49_BERCNT_RESERVED1_SHIFT 0 19300 19301 19302 /**************************************************************************** 19303 * TSC_WC4_TSC_USER4_CL73 19304 */ 19305 /**************************************************************************** 19306 * CL73 :: UCtrl1 19307 */ 19308 /* CL73 :: UCtrl1 :: reserved0 [15:07] */ 19309 #define CL73_UCTRL1_RESERVED0_MASK 0xff80 19310 #define CL73_UCTRL1_RESERVED0_ALIGN 0 19311 #define CL73_UCTRL1_RESERVED0_BITS 9 19312 #define CL73_UCTRL1_RESERVED0_SHIFT 7 19313 19314 /* CL73 :: UCtrl1 :: cl73_nonce_match_over [06:06] */ 19315 #define CL73_UCTRL1_CL73_NONCE_MATCH_OVER_MASK 0x0040 19316 #define CL73_UCTRL1_CL73_NONCE_MATCH_OVER_ALIGN 0 19317 #define CL73_UCTRL1_CL73_NONCE_MATCH_OVER_BITS 1 19318 #define CL73_UCTRL1_CL73_NONCE_MATCH_OVER_SHIFT 6 19319 19320 /* CL73 :: UCtrl1 :: cl73_nonce_match_val [05:05] */ 19321 #define CL73_UCTRL1_CL73_NONCE_MATCH_VAL_MASK 0x0020 19322 #define CL73_UCTRL1_CL73_NONCE_MATCH_VAL_ALIGN 0 19323 #define CL73_UCTRL1_CL73_NONCE_MATCH_VAL_BITS 1 19324 #define CL73_UCTRL1_CL73_NONCE_MATCH_VAL_SHIFT 5 19325 19326 /* CL73 :: UCtrl1 :: reserved1 [04:00] */ 19327 #define CL73_UCTRL1_RESERVED1_MASK 0x001f 19328 #define CL73_UCTRL1_RESERVED1_ALIGN 0 19329 #define CL73_UCTRL1_RESERVED1_BITS 5 19330 #define CL73_UCTRL1_RESERVED1_SHIFT 0 19331 19332 19333 /**************************************************************************** 19334 * CL73 :: Ustat1 19335 */ 19336 /* CL73 :: Ustat1 :: reserved0 [15:12] */ 19337 #define CL73_USTAT1_RESERVED0_MASK 0xf000 19338 #define CL73_USTAT1_RESERVED0_ALIGN 0 19339 #define CL73_USTAT1_RESERVED0_BITS 4 19340 #define CL73_USTAT1_RESERVED0_SHIFT 12 19341 19342 /* CL73 :: Ustat1 :: arb_fsm [11:00] */ 19343 #define CL73_USTAT1_ARB_FSM_MASK 0x0fff 19344 #define CL73_USTAT1_ARB_FSM_ALIGN 0 19345 #define CL73_USTAT1_ARB_FSM_BITS 12 19346 #define CL73_USTAT1_ARB_FSM_SHIFT 0 19347 #define CL73_USTAT1_ARB_FSM_AN_ENABLE 1 19348 #define CL73_USTAT1_ARB_FSM_TRANSMIT_DISABLE 2 19349 #define CL73_USTAT1_ARB_FSM_ABILITY_DETECT 4 19350 #define CL73_USTAT1_ARB_FSM_ACKNOWLEDGE_DETECT 8 19351 #define CL73_USTAT1_ARB_FSM_COMPLETE_ACKNOWLEDGE 16 19352 #define CL73_USTAT1_ARB_FSM_NEXT_PAGE_WAIT 32 19353 #define CL73_USTAT1_ARB_FSM_AN_GOOD_CHECK 64 19354 #define CL73_USTAT1_ARB_FSM_AN_GOOD 128 19355 #define CL73_USTAT1_ARB_FSM_LINK_STATUS_CHECK 256 19356 #define CL73_USTAT1_ARB_FSM_PARALLEL_DETECTION_FAULT 512 19357 #define CL73_USTAT1_ARB_FSM_AN_GOOD_CHECK_BAM37 1024 19358 #define CL73_USTAT1_ARB_FSM_TRANSMIT_DISABLE_BAM37 2048 19359 19360 19361 /**************************************************************************** 19362 * CL73 :: UCtrl2 19363 */ 19364 /* CL73 :: UCtrl2 :: reserved0 [15:12] */ 19365 #define CL73_UCTRL2_RESERVED0_MASK 0xf000 19366 #define CL73_UCTRL2_RESERVED0_ALIGN 0 19367 #define CL73_UCTRL2_RESERVED0_BITS 4 19368 #define CL73_UCTRL2_RESERVED0_SHIFT 12 19369 19370 /* CL73 :: UCtrl2 :: useLink [11:11] */ 19371 #define CL73_UCTRL2_USELINK_MASK 0x0800 19372 #define CL73_UCTRL2_USELINK_ALIGN 0 19373 #define CL73_UCTRL2_USELINK_BITS 1 19374 #define CL73_UCTRL2_USELINK_SHIFT 11 19375 19376 /* CL73 :: UCtrl2 :: reserved1 [10:00] */ 19377 #define CL73_UCTRL2_RESERVED1_MASK 0x07ff 19378 #define CL73_UCTRL2_RESERVED1_ALIGN 0 19379 #define CL73_UCTRL2_RESERVED1_BITS 11 19380 #define CL73_UCTRL2_RESERVED1_SHIFT 0 19381 19382 19383 /**************************************************************************** 19384 * TSC_WC4_TSC_USERX_uC_Info_B1 19385 */ 19386 /**************************************************************************** 19387 * uC_Info_B1 :: version 19388 */ 19389 /* uC_Info_B1 :: version :: version [15:00] */ 19390 #define UC_INFO_B1_VERSION_VERSION_MASK 0xffff 19391 #define UC_INFO_B1_VERSION_VERSION_ALIGN 0 19392 #define UC_INFO_B1_VERSION_VERSION_BITS 16 19393 #define UC_INFO_B1_VERSION_VERSION_SHIFT 0 19394 19395 19396 /**************************************************************************** 19397 * uC_Info_B1 :: target 19398 */ 19399 /* uC_Info_B1 :: target :: target [15:00] */ 19400 #define UC_INFO_B1_TARGET_TARGET_MASK 0xffff 19401 #define UC_INFO_B1_TARGET_TARGET_ALIGN 0 19402 #define UC_INFO_B1_TARGET_TARGET_BITS 16 19403 #define UC_INFO_B1_TARGET_TARGET_SHIFT 0 19404 19405 19406 /**************************************************************************** 19407 * uC_Info_B1 :: tuning_state_bypass 19408 */ 19409 /* uC_Info_B1 :: tuning_state_bypass :: reserved0 [15:09] */ 19410 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED0_MASK 0xfe00 19411 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED0_ALIGN 0 19412 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED0_BITS 7 19413 #define UC_INFO_B1_TUNING_STATE_BYPASS_RESERVED0_SHIFT 9 19414 19415 /* uC_Info_B1 :: tuning_state_bypass :: bypass_steady_state_tuning [08:08] */ 19416 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_MASK 0x0100 19417 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_ALIGN 0 19418 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_BITS 1 19419 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_SHIFT 8 19420 19421 /* uC_Info_B1 :: tuning_state_bypass :: bypass_cdr_lock_monitor [07:07] */ 19422 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_MASK 0x0080 19423 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_ALIGN 0 19424 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_BITS 1 19425 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_SHIFT 7 19426 19427 /* uC_Info_B1 :: tuning_state_bypass :: bypass_dcd_tuning [06:06] */ 19428 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_MASK 0x0040 19429 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_ALIGN 0 19430 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_BITS 1 19431 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_SHIFT 6 19432 19433 /* uC_Info_B1 :: tuning_state_bypass :: bypass_slicer_offset_tuning [05:05] */ 19434 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_MASK 0x0020 19435 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_ALIGN 0 19436 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_BITS 1 19437 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_SHIFT 5 19438 19439 /* uC_Info_B1 :: tuning_state_bypass :: bypass_slicer_target_tuning [04:04] */ 19440 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_MASK 0x0010 19441 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_ALIGN 0 19442 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_BITS 1 19443 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_SHIFT 4 19444 19445 /* uC_Info_B1 :: tuning_state_bypass :: bypass_vga_bias_tuning [03:03] */ 19446 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_MASK 0x0008 19447 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_ALIGN 0 19448 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_BITS 1 19449 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_SHIFT 3 19450 19451 /* uC_Info_B1 :: tuning_state_bypass :: bypass_pf_tuning [02:02] */ 19452 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_MASK 0x0004 19453 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_ALIGN 0 19454 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_BITS 1 19455 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_SHIFT 2 19456 19457 /* uC_Info_B1 :: tuning_state_bypass :: bypass_clk90_tuning [01:01] */ 19458 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_MASK 0x0002 19459 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_ALIGN 0 19460 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_BITS 1 19461 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_SHIFT 1 19462 19463 /* uC_Info_B1 :: tuning_state_bypass :: bypass_os_vga_tuning [00:00] */ 19464 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_MASK 0x0001 19465 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_ALIGN 0 19466 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_BITS 1 19467 #define UC_INFO_B1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_SHIFT 0 19468 19469 19470 /**************************************************************************** 19471 * uC_Info_B1 :: temperature 19472 */ 19473 /* uC_Info_B1 :: temperature :: force_temperature [15:15] */ 19474 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_MASK 0x8000 19475 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_ALIGN 0 19476 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_BITS 1 19477 #define UC_INFO_B1_TEMPERATURE_FORCE_TEMPERATURE_SHIFT 15 19478 19479 /* uC_Info_B1 :: temperature :: reserved0 [14:14] */ 19480 #define UC_INFO_B1_TEMPERATURE_RESERVED0_MASK 0x4000 19481 #define UC_INFO_B1_TEMPERATURE_RESERVED0_ALIGN 0 19482 #define UC_INFO_B1_TEMPERATURE_RESERVED0_BITS 1 19483 #define UC_INFO_B1_TEMPERATURE_RESERVED0_SHIFT 14 19484 19485 /* uC_Info_B1 :: temperature :: temp_idx [13:10] */ 19486 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_MASK 0x3c00 19487 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_ALIGN 0 19488 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_BITS 4 19489 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_SHIFT 10 19490 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE__22p9C 15 19491 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE__12p6C 14 19492 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE__3p0C 13 19493 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_6p7C 12 19494 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_16p4C 11 19495 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_26p6C 10 19496 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_36p3C 9 19497 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_46p0C 8 19498 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_56p2C 7 19499 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_65p9C 6 19500 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_75p6C 5 19501 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_85p3C 4 19502 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_95p5C 3 19503 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_105p2C 2 19504 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_114p9C 1 19505 #define UC_INFO_B1_TEMPERATURE_TEMP_IDX_LTE_125p1C 0 19506 19507 /* uC_Info_B1 :: temperature :: temperature [09:00] */ 19508 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_MASK 0x03ff 19509 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_ALIGN 0 19510 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_BITS 10 19511 #define UC_INFO_B1_TEMPERATURE_TEMPERATURE_SHIFT 0 19512 19513 19514 /**************************************************************************** 19515 * uC_Info_B1 :: crc 19516 */ 19517 /* uC_Info_B1 :: crc :: crc [15:00] */ 19518 #define UC_INFO_B1_CRC_CRC_MASK 0xffff 19519 #define UC_INFO_B1_CRC_CRC_ALIGN 0 19520 #define UC_INFO_B1_CRC_CRC_BITS 16 19521 #define UC_INFO_B1_CRC_CRC_SHIFT 0 19522 19523 19524 /**************************************************************************** 19525 * uC_Info_B1 :: tsc_12_timer_control 19526 */ 19527 /* uC_Info_B1 :: tsc_12_timer_control :: timer_mux_sel [15:12] */ 19528 #define UC_INFO_B1_TSC_12_TIMER_CONTROL_TIMER_MUX_SEL_MASK 0xf000 19529 #define UC_INFO_B1_TSC_12_TIMER_CONTROL_TIMER_MUX_SEL_ALIGN 0 19530 #define UC_INFO_B1_TSC_12_TIMER_CONTROL_TIMER_MUX_SEL_BITS 4 19531 #define UC_INFO_B1_TSC_12_TIMER_CONTROL_TIMER_MUX_SEL_SHIFT 12 19532 19533 /* uC_Info_B1 :: tsc_12_timer_control :: timer_enable [11:00] */ 19534 #define UC_INFO_B1_TSC_12_TIMER_CONTROL_TIMER_ENABLE_MASK 0x0fff 19535 #define UC_INFO_B1_TSC_12_TIMER_CONTROL_TIMER_ENABLE_ALIGN 0 19536 #define UC_INFO_B1_TSC_12_TIMER_CONTROL_TIMER_ENABLE_BITS 12 19537 #define UC_INFO_B1_TSC_12_TIMER_CONTROL_TIMER_ENABLE_SHIFT 0 19538 19539 19540 /**************************************************************************** 19541 * TSC_WC4_TSC_USERX_uC 19542 */ 19543 /**************************************************************************** 19544 * uC :: ramword 19545 */ 19546 /* uC :: ramword :: ram_count [15:00] */ 19547 #define UC_RAMWORD_RAM_COUNT_MASK 0xffff 19548 #define UC_RAMWORD_RAM_COUNT_ALIGN 0 19549 #define UC_RAMWORD_RAM_COUNT_BITS 16 19550 #define UC_RAMWORD_RAM_COUNT_SHIFT 0 19551 19552 19553 /**************************************************************************** 19554 * uC :: address 19555 */ 19556 /* uC :: address :: ram_address [15:00] */ 19557 #define UC_ADDRESS_RAM_ADDRESS_MASK 0xffff 19558 #define UC_ADDRESS_RAM_ADDRESS_ALIGN 0 19559 #define UC_ADDRESS_RAM_ADDRESS_BITS 16 19560 #define UC_ADDRESS_RAM_ADDRESS_SHIFT 0 19561 19562 19563 /**************************************************************************** 19564 * uC :: command 19565 */ 19566 /* uC :: command :: init_cmd [15:15] */ 19567 #define UC_COMMAND_INIT_CMD_MASK 0x8000 19568 #define UC_COMMAND_INIT_CMD_ALIGN 0 19569 #define UC_COMMAND_INIT_CMD_BITS 1 19570 #define UC_COMMAND_INIT_CMD_SHIFT 15 19571 19572 /* uC :: command :: uc_md_en_override [14:14] */ 19573 #define UC_COMMAND_UC_MD_EN_OVERRIDE_MASK 0x4000 19574 #define UC_COMMAND_UC_MD_EN_OVERRIDE_ALIGN 0 19575 #define UC_COMMAND_UC_MD_EN_OVERRIDE_BITS 1 19576 #define UC_COMMAND_UC_MD_EN_OVERRIDE_SHIFT 14 19577 19578 /* uC :: command :: uc_md_en_override_value [13:13] */ 19579 #define UC_COMMAND_UC_MD_EN_OVERRIDE_VALUE_MASK 0x2000 19580 #define UC_COMMAND_UC_MD_EN_OVERRIDE_VALUE_ALIGN 0 19581 #define UC_COMMAND_UC_MD_EN_OVERRIDE_VALUE_BITS 1 19582 #define UC_COMMAND_UC_MD_EN_OVERRIDE_VALUE_SHIFT 13 19583 19584 /* uC :: command :: mdio_ram_cs_force_val [12:12] */ 19585 #define UC_COMMAND_MDIO_RAM_CS_FORCE_VAL_MASK 0x1000 19586 #define UC_COMMAND_MDIO_RAM_CS_FORCE_VAL_ALIGN 0 19587 #define UC_COMMAND_MDIO_RAM_CS_FORCE_VAL_BITS 1 19588 #define UC_COMMAND_MDIO_RAM_CS_FORCE_VAL_SHIFT 12 19589 19590 /* uC :: command :: mdio_ram_cs_force [11:11] */ 19591 #define UC_COMMAND_MDIO_RAM_CS_FORCE_MASK 0x0800 19592 #define UC_COMMAND_MDIO_RAM_CS_FORCE_ALIGN 0 19593 #define UC_COMMAND_MDIO_RAM_CS_FORCE_BITS 1 19594 #define UC_COMMAND_MDIO_RAM_CS_FORCE_SHIFT 11 19595 19596 /* uC :: command :: mdio_autowakeup [10:10] */ 19597 #define UC_COMMAND_MDIO_AUTOWAKEUP_MASK 0x0400 19598 #define UC_COMMAND_MDIO_AUTOWAKEUP_ALIGN 0 19599 #define UC_COMMAND_MDIO_AUTOWAKEUP_BITS 1 19600 #define UC_COMMAND_MDIO_AUTOWAKEUP_SHIFT 10 19601 19602 /* uC :: command :: byte_mode [09:09] */ 19603 #define UC_COMMAND_BYTE_MODE_MASK 0x0200 19604 #define UC_COMMAND_BYTE_MODE_ALIGN 0 19605 #define UC_COMMAND_BYTE_MODE_BITS 1 19606 #define UC_COMMAND_BYTE_MODE_SHIFT 9 19607 19608 /* uC :: command :: reserved0 [08:05] */ 19609 #define UC_COMMAND_RESERVED0_MASK 0x01e0 19610 #define UC_COMMAND_RESERVED0_ALIGN 0 19611 #define UC_COMMAND_RESERVED0_BITS 4 19612 #define UC_COMMAND_RESERVED0_SHIFT 5 19613 19614 /* uC :: command :: mdio_uC_reset_n [04:04] */ 19615 #define UC_COMMAND_MDIO_UC_RESET_N_MASK 0x0010 19616 #define UC_COMMAND_MDIO_UC_RESET_N_ALIGN 0 19617 #define UC_COMMAND_MDIO_UC_RESET_N_BITS 1 19618 #define UC_COMMAND_MDIO_UC_RESET_N_SHIFT 4 19619 19620 /* uC :: command :: write [03:03] */ 19621 #define UC_COMMAND_WRITE_MASK 0x0008 19622 #define UC_COMMAND_WRITE_ALIGN 0 19623 #define UC_COMMAND_WRITE_BITS 1 19624 #define UC_COMMAND_WRITE_SHIFT 3 19625 19626 /* uC :: command :: read [02:02] */ 19627 #define UC_COMMAND_READ_MASK 0x0004 19628 #define UC_COMMAND_READ_ALIGN 0 19629 #define UC_COMMAND_READ_BITS 1 19630 #define UC_COMMAND_READ_SHIFT 2 19631 19632 /* uC :: command :: stop [01:01] */ 19633 #define UC_COMMAND_STOP_MASK 0x0002 19634 #define UC_COMMAND_STOP_ALIGN 0 19635 #define UC_COMMAND_STOP_BITS 1 19636 #define UC_COMMAND_STOP_SHIFT 1 19637 19638 /* uC :: command :: run [00:00] */ 19639 #define UC_COMMAND_RUN_MASK 0x0001 19640 #define UC_COMMAND_RUN_ALIGN 0 19641 #define UC_COMMAND_RUN_BITS 1 19642 #define UC_COMMAND_RUN_SHIFT 0 19643 19644 19645 /**************************************************************************** 19646 * uC :: wrdata 19647 */ 19648 /* uC :: wrdata :: wrdata [15:00] */ 19649 #define UC_WRDATA_WRDATA_MASK 0xffff 19650 #define UC_WRDATA_WRDATA_ALIGN 0 19651 #define UC_WRDATA_WRDATA_BITS 16 19652 #define UC_WRDATA_WRDATA_SHIFT 0 19653 19654 19655 /**************************************************************************** 19656 * uC :: rddata 19657 */ 19658 /* uC :: rddata :: rddata [15:00] */ 19659 #define UC_RDDATA_RDDATA_MASK 0xffff 19660 #define UC_RDDATA_RDDATA_ALIGN 0 19661 #define UC_RDDATA_RDDATA_BITS 16 19662 #define UC_RDDATA_RDDATA_SHIFT 0 19663 19664 19665 /**************************************************************************** 19666 * uC :: download_status 19667 */ 19668 /* uC :: download_status :: init_done [15:15] */ 19669 #define UC_DOWNLOAD_STATUS_INIT_DONE_MASK 0x8000 19670 #define UC_DOWNLOAD_STATUS_INIT_DONE_ALIGN 0 19671 #define UC_DOWNLOAD_STATUS_INIT_DONE_BITS 1 19672 #define UC_DOWNLOAD_STATUS_INIT_DONE_SHIFT 15 19673 19674 /* uC :: download_status :: reserved0 [14:06] */ 19675 #define UC_DOWNLOAD_STATUS_RESERVED0_MASK 0x7fc0 19676 #define UC_DOWNLOAD_STATUS_RESERVED0_ALIGN 0 19677 #define UC_DOWNLOAD_STATUS_RESERVED0_BITS 9 19678 #define UC_DOWNLOAD_STATUS_RESERVED0_SHIFT 6 19679 19680 /* uC :: download_status :: FSM [05:02] */ 19681 #define UC_DOWNLOAD_STATUS_FSM_MASK 0x003c 19682 #define UC_DOWNLOAD_STATUS_FSM_ALIGN 0 19683 #define UC_DOWNLOAD_STATUS_FSM_BITS 4 19684 #define UC_DOWNLOAD_STATUS_FSM_SHIFT 2 19685 19686 /* uC :: download_status :: ERR1 [01:01] */ 19687 #define UC_DOWNLOAD_STATUS_ERR1_MASK 0x0002 19688 #define UC_DOWNLOAD_STATUS_ERR1_ALIGN 0 19689 #define UC_DOWNLOAD_STATUS_ERR1_BITS 1 19690 #define UC_DOWNLOAD_STATUS_ERR1_SHIFT 1 19691 19692 /* uC :: download_status :: ERR0 [00:00] */ 19693 #define UC_DOWNLOAD_STATUS_ERR0_MASK 0x0001 19694 #define UC_DOWNLOAD_STATUS_ERR0_ALIGN 0 19695 #define UC_DOWNLOAD_STATUS_ERR0_BITS 1 19696 #define UC_DOWNLOAD_STATUS_ERR0_SHIFT 0 19697 19698 19699 /**************************************************************************** 19700 * uC :: sfr_status 19701 */ 19702 /* union - case ecc_error_counters [15:00] */ 19703 /* uC :: sfr_status :: ecc_error_counters [15:00] */ 19704 #define UC_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_MASK 0xffff 19705 #define UC_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_ALIGN 0 19706 #define UC_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_BITS 16 19707 #define UC_SFR_STATUS_ECC_ERROR_COUNTERS_ECC_ERROR_COUNTERS_SHIFT 0 19708 19709 19710 /* union - case dw8051_to_pcb_fsm_L [15:00] */ 19711 /* uC :: sfr_status :: dw8051_to_pcb_fsm_L [15:00] */ 19712 #define UC_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_MASK 0xffff 19713 #define UC_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_ALIGN 0 19714 #define UC_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_BITS 16 19715 #define UC_SFR_STATUS_DW8051_TO_PCB_FSM_L_DW8051_TO_PCB_FSM_L_SHIFT 0 19716 19717 19718 /* union - case dw8051_to_pcb_fsm_U [15:00] */ 19719 /* uC :: sfr_status :: dw8051_to_pcb_fsm_U [15:00] */ 19720 #define UC_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_MASK 0xffff 19721 #define UC_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_ALIGN 0 19722 #define UC_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_BITS 16 19723 #define UC_SFR_STATUS_DW8051_TO_PCB_FSM_U_DW8051_TO_PCB_FSM_U_SHIFT 0 19724 19725 19726 19727 /**************************************************************************** 19728 * uC :: command4 19729 */ 19730 /* uC :: command4 :: data_ram_access [15:15] */ 19731 #define UC_COMMAND4_DATA_RAM_ACCESS_MASK 0x8000 19732 #define UC_COMMAND4_DATA_RAM_ACCESS_ALIGN 0 19733 #define UC_COMMAND4_DATA_RAM_ACCESS_BITS 1 19734 #define UC_COMMAND4_DATA_RAM_ACCESS_SHIFT 15 19735 19736 /* uC :: command4 :: data_ram_r_w [14:14] */ 19737 #define UC_COMMAND4_DATA_RAM_R_W_MASK 0x4000 19738 #define UC_COMMAND4_DATA_RAM_R_W_ALIGN 0 19739 #define UC_COMMAND4_DATA_RAM_R_W_BITS 1 19740 #define UC_COMMAND4_DATA_RAM_R_W_SHIFT 14 19741 19742 /* uC :: command4 :: tm_data_ram [13:08] */ 19743 #define UC_COMMAND4_TM_DATA_RAM_MASK 0x3f00 19744 #define UC_COMMAND4_TM_DATA_RAM_ALIGN 0 19745 #define UC_COMMAND4_TM_DATA_RAM_BITS 6 19746 #define UC_COMMAND4_TM_DATA_RAM_SHIFT 8 19747 19748 /* uC :: command4 :: tm_register_ram [07:06] */ 19749 #define UC_COMMAND4_TM_REGISTER_RAM_MASK 0x00c0 19750 #define UC_COMMAND4_TM_REGISTER_RAM_ALIGN 0 19751 #define UC_COMMAND4_TM_REGISTER_RAM_BITS 2 19752 #define UC_COMMAND4_TM_REGISTER_RAM_SHIFT 6 19753 19754 /* uC :: command4 :: mdio_eitu_int5 [05:05] */ 19755 #define UC_COMMAND4_MDIO_EITU_INT5_MASK 0x0020 19756 #define UC_COMMAND4_MDIO_EITU_INT5_ALIGN 0 19757 #define UC_COMMAND4_MDIO_EITU_INT5_BITS 1 19758 #define UC_COMMAND4_MDIO_EITU_INT5_SHIFT 5 19759 19760 /* uC :: command4 :: mdio_eitu_int4 [04:04] */ 19761 #define UC_COMMAND4_MDIO_EITU_INT4_MASK 0x0010 19762 #define UC_COMMAND4_MDIO_EITU_INT4_ALIGN 0 19763 #define UC_COMMAND4_MDIO_EITU_INT4_BITS 1 19764 #define UC_COMMAND4_MDIO_EITU_INT4_SHIFT 4 19765 19766 /* uC :: command4 :: mdio_eitu_int3 [03:03] */ 19767 #define UC_COMMAND4_MDIO_EITU_INT3_MASK 0x0008 19768 #define UC_COMMAND4_MDIO_EITU_INT3_ALIGN 0 19769 #define UC_COMMAND4_MDIO_EITU_INT3_BITS 1 19770 #define UC_COMMAND4_MDIO_EITU_INT3_SHIFT 3 19771 19772 /* uC :: command4 :: mdio_eitu_int2 [02:02] */ 19773 #define UC_COMMAND4_MDIO_EITU_INT2_MASK 0x0004 19774 #define UC_COMMAND4_MDIO_EITU_INT2_ALIGN 0 19775 #define UC_COMMAND4_MDIO_EITU_INT2_BITS 1 19776 #define UC_COMMAND4_MDIO_EITU_INT2_SHIFT 2 19777 19778 /* uC :: command4 :: mdio_eitu_int1 [01:01] */ 19779 #define UC_COMMAND4_MDIO_EITU_INT1_MASK 0x0002 19780 #define UC_COMMAND4_MDIO_EITU_INT1_ALIGN 0 19781 #define UC_COMMAND4_MDIO_EITU_INT1_BITS 1 19782 #define UC_COMMAND4_MDIO_EITU_INT1_SHIFT 1 19783 19784 /* uC :: command4 :: mdio_eitu_int0 [00:00] */ 19785 #define UC_COMMAND4_MDIO_EITU_INT0_MASK 0x0001 19786 #define UC_COMMAND4_MDIO_EITU_INT0_ALIGN 0 19787 #define UC_COMMAND4_MDIO_EITU_INT0_BITS 1 19788 #define UC_COMMAND4_MDIO_EITU_INT0_SHIFT 0 19789 19790 19791 /**************************************************************************** 19792 * uC :: mdio_uC_mailbox 19793 */ 19794 /* uC :: mdio_uC_mailbox :: mdio_uC_mailbox [15:00] */ 19795 #define UC_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_MASK 0xffff 19796 #define UC_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_ALIGN 0 19797 #define UC_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_BITS 16 19798 #define UC_MDIO_UC_MAILBOX_MDIO_UC_MAILBOX_SHIFT 0 19799 19800 19801 /**************************************************************************** 19802 * uC :: uC_mdio_mailbox 19803 */ 19804 /* uC :: uC_mdio_mailbox :: uC_mdio_mailbox [15:00] */ 19805 #define UC_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_MASK 0xffff 19806 #define UC_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_ALIGN 0 19807 #define UC_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_BITS 16 19808 #define UC_UC_MDIO_MAILBOX_UC_MDIO_MAILBOX_SHIFT 0 19809 19810 19811 /**************************************************************************** 19812 * uC :: command2 19813 */ 19814 /* uC :: command2 :: mdio_to_8051_reset [15:15] */ 19815 #define UC_COMMAND2_MDIO_TO_8051_RESET_MASK 0x8000 19816 #define UC_COMMAND2_MDIO_TO_8051_RESET_ALIGN 0 19817 #define UC_COMMAND2_MDIO_TO_8051_RESET_BITS 1 19818 #define UC_COMMAND2_MDIO_TO_8051_RESET_SHIFT 15 19819 19820 /* uC :: command2 :: m8051_to_pcb_reset [14:14] */ 19821 #define UC_COMMAND2_M8051_TO_PCB_RESET_MASK 0x4000 19822 #define UC_COMMAND2_M8051_TO_PCB_RESET_ALIGN 0 19823 #define UC_COMMAND2_M8051_TO_PCB_RESET_BITS 1 19824 #define UC_COMMAND2_M8051_TO_PCB_RESET_SHIFT 14 19825 19826 /* uC :: command2 :: firmware_reset_disable [13:13] */ 19827 #define UC_COMMAND2_FIRMWARE_RESET_DISABLE_MASK 0x2000 19828 #define UC_COMMAND2_FIRMWARE_RESET_DISABLE_ALIGN 0 19829 #define UC_COMMAND2_FIRMWARE_RESET_DISABLE_BITS 1 19830 #define UC_COMMAND2_FIRMWARE_RESET_DISABLE_SHIFT 13 19831 19832 /* uC :: command2 :: zero_rom_dataout [12:12] */ 19833 #define UC_COMMAND2_ZERO_ROM_DATAOUT_MASK 0x1000 19834 #define UC_COMMAND2_ZERO_ROM_DATAOUT_ALIGN 0 19835 #define UC_COMMAND2_ZERO_ROM_DATAOUT_BITS 1 19836 #define UC_COMMAND2_ZERO_ROM_DATAOUT_SHIFT 12 19837 19838 /* uC :: command2 :: reserved0 [11:10] */ 19839 #define UC_COMMAND2_RESERVED0_MASK 0x0c00 19840 #define UC_COMMAND2_RESERVED0_ALIGN 0 19841 #define UC_COMMAND2_RESERVED0_BITS 2 19842 #define UC_COMMAND2_RESERVED0_SHIFT 10 19843 19844 /* uC :: command2 :: timer_mux_sel [09:08] */ 19845 #define UC_COMMAND2_TIMER_MUX_SEL_MASK 0x0300 19846 #define UC_COMMAND2_TIMER_MUX_SEL_ALIGN 0 19847 #define UC_COMMAND2_TIMER_MUX_SEL_BITS 2 19848 #define UC_COMMAND2_TIMER_MUX_SEL_SHIFT 8 19849 19850 /* uC :: command2 :: wdog_disable [07:07] */ 19851 #define UC_COMMAND2_WDOG_DISABLE_MASK 0x0080 19852 #define UC_COMMAND2_WDOG_DISABLE_ALIGN 0 19853 #define UC_COMMAND2_WDOG_DISABLE_BITS 1 19854 #define UC_COMMAND2_WDOG_DISABLE_SHIFT 7 19855 19856 /* uC :: command2 :: refdiv4_tmr_en [06:06] */ 19857 #define UC_COMMAND2_REFDIV4_TMR_EN_MASK 0x0040 19858 #define UC_COMMAND2_REFDIV4_TMR_EN_ALIGN 0 19859 #define UC_COMMAND2_REFDIV4_TMR_EN_BITS 1 19860 #define UC_COMMAND2_REFDIV4_TMR_EN_SHIFT 6 19861 19862 /* uC :: command2 :: refdiv2_tmr_en [05:05] */ 19863 #define UC_COMMAND2_REFDIV2_TMR_EN_MASK 0x0020 19864 #define UC_COMMAND2_REFDIV2_TMR_EN_ALIGN 0 19865 #define UC_COMMAND2_REFDIV2_TMR_EN_BITS 1 19866 #define UC_COMMAND2_REFDIV2_TMR_EN_SHIFT 5 19867 19868 /* uC :: command2 :: wdog_en [04:04] */ 19869 #define UC_COMMAND2_WDOG_EN_MASK 0x0010 19870 #define UC_COMMAND2_WDOG_EN_ALIGN 0 19871 #define UC_COMMAND2_WDOG_EN_BITS 1 19872 #define UC_COMMAND2_WDOG_EN_SHIFT 4 19873 19874 /* uC :: command2 :: tmr_en [03:00] */ 19875 #define UC_COMMAND2_TMR_EN_MASK 0x000f 19876 #define UC_COMMAND2_TMR_EN_ALIGN 0 19877 #define UC_COMMAND2_TMR_EN_BITS 4 19878 #define UC_COMMAND2_TMR_EN_SHIFT 0 19879 19880 19881 /**************************************************************************** 19882 * uC :: wdog_evnt_cnt 19883 */ 19884 /* uC :: wdog_evnt_cnt :: wdog_evnt_cnt [15:00] */ 19885 #define UC_WDOG_EVNT_CNT_WDOG_EVNT_CNT_MASK 0xffff 19886 #define UC_WDOG_EVNT_CNT_WDOG_EVNT_CNT_ALIGN 0 19887 #define UC_WDOG_EVNT_CNT_WDOG_EVNT_CNT_BITS 16 19888 #define UC_WDOG_EVNT_CNT_WDOG_EVNT_CNT_SHIFT 0 19889 19890 19891 /**************************************************************************** 19892 * uC :: command3 19893 */ 19894 /* uC :: command3 :: gen_status_sel [15:12] */ 19895 #define UC_COMMAND3_GEN_STATUS_SEL_MASK 0xf000 19896 #define UC_COMMAND3_GEN_STATUS_SEL_ALIGN 0 19897 #define UC_COMMAND3_GEN_STATUS_SEL_BITS 4 19898 #define UC_COMMAND3_GEN_STATUS_SEL_SHIFT 12 19899 #define UC_COMMAND3_GEN_STATUS_SEL_ecc_error_counters 0 19900 #define UC_COMMAND3_GEN_STATUS_SEL_dw8051_to_pcb_fsm_L 1 19901 #define UC_COMMAND3_GEN_STATUS_SEL_dw8051_to_pcb_fsm_U 2 19902 19903 /* uC :: command3 :: disable_ecc [11:11] */ 19904 #define UC_COMMAND3_DISABLE_ECC_MASK 0x0800 19905 #define UC_COMMAND3_DISABLE_ECC_ALIGN 0 19906 #define UC_COMMAND3_DISABLE_ECC_BITS 1 19907 #define UC_COMMAND3_DISABLE_ECC_SHIFT 11 19908 19909 /* uC :: command3 :: out_staging_flop_bypass [10:10] */ 19910 #define UC_COMMAND3_OUT_STAGING_FLOP_BYPASS_MASK 0x0400 19911 #define UC_COMMAND3_OUT_STAGING_FLOP_BYPASS_ALIGN 0 19912 #define UC_COMMAND3_OUT_STAGING_FLOP_BYPASS_BITS 1 19913 #define UC_COMMAND3_OUT_STAGING_FLOP_BYPASS_SHIFT 10 19914 19915 /* uC :: command3 :: tm [09:05] */ 19916 #define UC_COMMAND3_TM_MASK 0x03e0 19917 #define UC_COMMAND3_TM_ALIGN 0 19918 #define UC_COMMAND3_TM_BITS 5 19919 #define UC_COMMAND3_TM_SHIFT 5 19920 19921 /* uC :: command3 :: pm_override_value [04:04] */ 19922 #define UC_COMMAND3_PM_OVERRIDE_VALUE_MASK 0x0010 19923 #define UC_COMMAND3_PM_OVERRIDE_VALUE_ALIGN 0 19924 #define UC_COMMAND3_PM_OVERRIDE_VALUE_BITS 1 19925 #define UC_COMMAND3_PM_OVERRIDE_VALUE_SHIFT 4 19926 19927 /* uC :: command3 :: enable_pm_override [03:03] */ 19928 #define UC_COMMAND3_ENABLE_PM_OVERRIDE_MASK 0x0008 19929 #define UC_COMMAND3_ENABLE_PM_OVERRIDE_ALIGN 0 19930 #define UC_COMMAND3_ENABLE_PM_OVERRIDE_BITS 1 19931 #define UC_COMMAND3_ENABLE_PM_OVERRIDE_SHIFT 3 19932 19933 /* uC :: command3 :: in_staging_flop_bypass [02:02] */ 19934 #define UC_COMMAND3_IN_STAGING_FLOP_BYPASS_MASK 0x0004 19935 #define UC_COMMAND3_IN_STAGING_FLOP_BYPASS_ALIGN 0 19936 #define UC_COMMAND3_IN_STAGING_FLOP_BYPASS_BITS 1 19937 #define UC_COMMAND3_IN_STAGING_FLOP_BYPASS_SHIFT 2 19938 19939 /* uC :: command3 :: ext_clk_enable [01:01] */ 19940 #define UC_COMMAND3_EXT_CLK_ENABLE_MASK 0x0002 19941 #define UC_COMMAND3_EXT_CLK_ENABLE_ALIGN 0 19942 #define UC_COMMAND3_EXT_CLK_ENABLE_BITS 1 19943 #define UC_COMMAND3_EXT_CLK_ENABLE_SHIFT 1 19944 19945 /* uC :: command3 :: reserved0 [00:00] */ 19946 #define UC_COMMAND3_RESERVED0_MASK 0x0001 19947 #define UC_COMMAND3_RESERVED0_ALIGN 0 19948 #define UC_COMMAND3_RESERVED0_BITS 1 19949 #define UC_COMMAND3_RESERVED0_SHIFT 0 19950 19951 19952 /**************************************************************************** 19953 * uC :: timer_lower16 19954 */ 19955 /* uC :: timer_lower16 :: timer_lower16bits [15:00] */ 19956 #define UC_TIMER_LOWER16_TIMER_LOWER16BITS_MASK 0xffff 19957 #define UC_TIMER_LOWER16_TIMER_LOWER16BITS_ALIGN 0 19958 #define UC_TIMER_LOWER16_TIMER_LOWER16BITS_BITS 16 19959 #define UC_TIMER_LOWER16_TIMER_LOWER16BITS_SHIFT 0 19960 19961 19962 /**************************************************************************** 19963 * uC :: timer_upper16 19964 */ 19965 /* uC :: timer_upper16 :: timer_upper16bits [15:00] */ 19966 #define UC_TIMER_UPPER16_TIMER_UPPER16BITS_MASK 0xffff 19967 #define UC_TIMER_UPPER16_TIMER_UPPER16BITS_ALIGN 0 19968 #define UC_TIMER_UPPER16_TIMER_UPPER16BITS_BITS 16 19969 #define UC_TIMER_UPPER16_TIMER_UPPER16BITS_SHIFT 0 19970 19971 19972 /**************************************************************************** 19973 * TSC_WC4_TSC_USERX_AER 19974 */ 19975 /**************************************************************************** 19976 * AER :: AddressExpansion 19977 */ 19978 /* AER :: AddressExpansion :: MMD_deviceType [15:11] */ 19979 #define AER_ADDRESSEXPANSION_MMD_DEVICETYPE_MASK 0xf800 19980 #define AER_ADDRESSEXPANSION_MMD_DEVICETYPE_ALIGN 0 19981 #define AER_ADDRESSEXPANSION_MMD_DEVICETYPE_BITS 5 19982 #define AER_ADDRESSEXPANSION_MMD_DEVICETYPE_SHIFT 11 19983 #define AER_ADDRESSEXPANSION_MMD_DEVICETYPE_combo_core 0 19984 #define AER_ADDRESSEXPANSION_MMD_DEVICETYPE_PMA_PMD 1 19985 #define AER_ADDRESSEXPANSION_MMD_DEVICETYPE_PCS 3 19986 #define AER_ADDRESSEXPANSION_MMD_DEVICETYPE_PHY 4 19987 #define AER_ADDRESSEXPANSION_MMD_DEVICETYPE_DTE 5 19988 #define AER_ADDRESSEXPANSION_MMD_DEVICETYPE_CL73_AN 7 19989 19990 /* AER :: AddressExpansion :: reserved0 [10:03] */ 19991 #define AER_ADDRESSEXPANSION_RESERVED0_MASK 0x07f8 19992 #define AER_ADDRESSEXPANSION_RESERVED0_ALIGN 0 19993 #define AER_ADDRESSEXPANSION_RESERVED0_BITS 8 19994 #define AER_ADDRESSEXPANSION_RESERVED0_SHIFT 3 19995 19996 /* AER :: AddressExpansion :: PORT_MODE [02:00] */ 19997 #define AER_ADDRESSEXPANSION_PORT_MODE_MASK 0x0007 19998 #define AER_ADDRESSEXPANSION_PORT_MODE_ALIGN 0 19999 #define AER_ADDRESSEXPANSION_PORT_MODE_BITS 3 20000 #define AER_ADDRESSEXPANSION_PORT_MODE_SHIFT 0 20001 20002 20003 /**************************************************************************** 20004 * TSC_WC4_TSC_USERX_Combo_IEEE 20005 */ 20006 /**************************************************************************** 20007 * Combo_IEEE :: phyid2 20008 */ 20009 /* Combo_IEEE :: phyid2 :: regid1 [15:00] */ 20010 #define COMBO_IEEE_PHYID2_REGID1_MASK 0xffff 20011 #define COMBO_IEEE_PHYID2_REGID1_ALIGN 0 20012 #define COMBO_IEEE_PHYID2_REGID1_BITS 16 20013 #define COMBO_IEEE_PHYID2_REGID1_SHIFT 0 20014 20015 20016 /**************************************************************************** 20017 * Combo_IEEE :: phyid3 20018 */ 20019 /* Combo_IEEE :: phyid3 :: regid2 [15:00] */ 20020 #define COMBO_IEEE_PHYID3_REGID2_MASK 0xffff 20021 #define COMBO_IEEE_PHYID3_REGID2_ALIGN 0 20022 #define COMBO_IEEE_PHYID3_REGID2_BITS 16 20023 #define COMBO_IEEE_PHYID3_REGID2_SHIFT 0 20024 20025 20026 /**************************************************************************** 20027 * Combo_IEEE :: MMDAccessControl 20028 */ 20029 /* Combo_IEEE :: MMDAccessControl :: increment_control [15:14] */ 20030 #define COMBO_IEEE_MMDACCESSCONTROL_INCREMENT_CONTROL_MASK 0xc000 20031 #define COMBO_IEEE_MMDACCESSCONTROL_INCREMENT_CONTROL_ALIGN 0 20032 #define COMBO_IEEE_MMDACCESSCONTROL_INCREMENT_CONTROL_BITS 2 20033 #define COMBO_IEEE_MMDACCESSCONTROL_INCREMENT_CONTROL_SHIFT 14 20034 20035 /* Combo_IEEE :: MMDAccessControl :: reserved0 [13:05] */ 20036 #define COMBO_IEEE_MMDACCESSCONTROL_RESERVED0_MASK 0x3fe0 20037 #define COMBO_IEEE_MMDACCESSCONTROL_RESERVED0_ALIGN 0 20038 #define COMBO_IEEE_MMDACCESSCONTROL_RESERVED0_BITS 9 20039 #define COMBO_IEEE_MMDACCESSCONTROL_RESERVED0_SHIFT 5 20040 20041 /* Combo_IEEE :: MMDAccessControl :: DEVAD [04:00] */ 20042 #define COMBO_IEEE_MMDACCESSCONTROL_DEVAD_MASK 0x001f 20043 #define COMBO_IEEE_MMDACCESSCONTROL_DEVAD_ALIGN 0 20044 #define COMBO_IEEE_MMDACCESSCONTROL_DEVAD_BITS 5 20045 #define COMBO_IEEE_MMDACCESSCONTROL_DEVAD_SHIFT 0 20046 20047 20048 /**************************************************************************** 20049 * Combo_IEEE :: MMDAccessAddressData 20050 */ 20051 /* Combo_IEEE :: MMDAccessAddressData :: AddressData [15:00] */ 20052 #define COMBO_IEEE_MMDACCESSADDRESSDATA_ADDRESSDATA_MASK 0xffff 20053 #define COMBO_IEEE_MMDACCESSADDRESSDATA_ADDRESSDATA_ALIGN 0 20054 #define COMBO_IEEE_MMDACCESSADDRESSDATA_ADDRESSDATA_BITS 16 20055 #define COMBO_IEEE_MMDACCESSADDRESSDATA_ADDRESSDATA_SHIFT 0 20056 20057 20058 /**************************************************************************** 20059 * TSC_IEEE_PMA_PMD_dev1_ieee0 20060 */ 20061 /**************************************************************************** 20062 * dev1_ieee0 :: AN_ieeeId1 20063 */ 20064 /* dev1_ieee0 :: AN_ieeeId1 :: IEEEID1 [15:00] */ 20065 #define DEV1_IEEE0_AN_IEEEID1_IEEEID1_MASK 0xffff 20066 #define DEV1_IEEE0_AN_IEEEID1_IEEEID1_ALIGN 0 20067 #define DEV1_IEEE0_AN_IEEEID1_IEEEID1_BITS 16 20068 #define DEV1_IEEE0_AN_IEEEID1_IEEEID1_SHIFT 0 20069 20070 20071 /**************************************************************************** 20072 * dev1_ieee0 :: AN_ieeeId2 20073 */ 20074 /* dev1_ieee0 :: AN_ieeeId2 :: IEEEID2 [15:00] */ 20075 #define DEV1_IEEE0_AN_IEEEID2_IEEEID2_MASK 0xffff 20076 #define DEV1_IEEE0_AN_IEEEID2_IEEEID2_ALIGN 0 20077 #define DEV1_IEEE0_AN_IEEEID2_IEEEID2_BITS 16 20078 #define DEV1_IEEE0_AN_IEEEID2_IEEEID2_SHIFT 0 20079 20080 20081 /**************************************************************************** 20082 * TSC_IEEE_PMA_PMD_dev1_ieee9 20083 */ 20084 /**************************************************************************** 20085 * dev1_ieee9 :: PMD_10Gbase_kr_pmd_control_register_150 20086 */ 20087 /* dev1_ieee9 :: PMD_10Gbase_kr_pmd_control_register_150 :: reserved0 [15:02] */ 20088 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_MASK 0xfffc 20089 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_ALIGN 0 20090 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_BITS 14 20091 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_RESERVED0_SHIFT 2 20092 20093 /* dev1_ieee9 :: PMD_10Gbase_kr_pmd_control_register_150 :: training_enable [01:01] */ 20094 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_MASK 0x0002 20095 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_ALIGN 0 20096 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_BITS 1 20097 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_SHIFT 1 20098 20099 /* dev1_ieee9 :: PMD_10Gbase_kr_pmd_control_register_150 :: restart_training [00:00] */ 20100 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_MASK 0x0001 20101 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_ALIGN 0 20102 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_BITS 1 20103 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_SHIFT 0 20104 20105 20106 /**************************************************************************** 20107 * dev1_ieee9 :: PMD_10Gbase_kr_pmd_status_register_151 20108 */ 20109 /* dev1_ieee9 :: PMD_10Gbase_kr_pmd_status_register_151 :: reserved0 [15:04] */ 20110 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_MASK 0xfff0 20111 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_ALIGN 0 20112 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_BITS 12 20113 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_RESERVED0_SHIFT 4 20114 20115 /* dev1_ieee9 :: PMD_10Gbase_kr_pmd_status_register_151 :: training_failure [03:03] */ 20116 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_MASK 0x0008 20117 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_ALIGN 0 20118 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_BITS 1 20119 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_SHIFT 3 20120 20121 /* dev1_ieee9 :: PMD_10Gbase_kr_pmd_status_register_151 :: training_status [02:02] */ 20122 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_MASK 0x0004 20123 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_ALIGN 0 20124 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_BITS 1 20125 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_TRAINING_STATUS_SHIFT 2 20126 20127 /* dev1_ieee9 :: PMD_10Gbase_kr_pmd_status_register_151 :: frame_lock [01:01] */ 20128 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_MASK 0x0002 20129 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_ALIGN 0 20130 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_BITS 1 20131 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_FRAME_LOCK_SHIFT 1 20132 20133 /* dev1_ieee9 :: PMD_10Gbase_kr_pmd_status_register_151 :: receiver_status [00:00] */ 20134 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_MASK 0x0001 20135 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_ALIGN 0 20136 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_BITS 1 20137 #define DEV1_IEEE9_PMD_10GBASE_KR_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_SHIFT 0 20138 20139 20140 /**************************************************************************** 20141 * TSC_IEEE_PMA_PMD_dev1_ieee10 20142 */ 20143 /**************************************************************************** 20144 * dev1_ieee10 :: PMD_CorrectedBlksL 20145 */ 20146 /* dev1_ieee10 :: PMD_CorrectedBlksL :: corCountL [15:00] */ 20147 #define DEV1_IEEE10_PMD_CORRECTEDBLKSL_CORCOUNTL_MASK 0xffff 20148 #define DEV1_IEEE10_PMD_CORRECTEDBLKSL_CORCOUNTL_ALIGN 0 20149 #define DEV1_IEEE10_PMD_CORRECTEDBLKSL_CORCOUNTL_BITS 16 20150 #define DEV1_IEEE10_PMD_CORRECTEDBLKSL_CORCOUNTL_SHIFT 0 20151 20152 20153 /**************************************************************************** 20154 * dev1_ieee10 :: PMD_CorrectedBlksH 20155 */ 20156 /* dev1_ieee10 :: PMD_CorrectedBlksH :: corCountH [15:00] */ 20157 #define DEV1_IEEE10_PMD_CORRECTEDBLKSH_CORCOUNTH_MASK 0xffff 20158 #define DEV1_IEEE10_PMD_CORRECTEDBLKSH_CORCOUNTH_ALIGN 0 20159 #define DEV1_IEEE10_PMD_CORRECTEDBLKSH_CORCOUNTH_BITS 16 20160 #define DEV1_IEEE10_PMD_CORRECTEDBLKSH_CORCOUNTH_SHIFT 0 20161 20162 20163 /**************************************************************************** 20164 * dev1_ieee10 :: PMD_UncorrectedBlksL 20165 */ 20166 /* dev1_ieee10 :: PMD_UncorrectedBlksL :: uncorCountL [15:00] */ 20167 #define DEV1_IEEE10_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_MASK 0xffff 20168 #define DEV1_IEEE10_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_ALIGN 0 20169 #define DEV1_IEEE10_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_BITS 16 20170 #define DEV1_IEEE10_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_SHIFT 0 20171 20172 20173 /**************************************************************************** 20174 * dev1_ieee10 :: PMD_UncorrectedBlksH 20175 */ 20176 /* dev1_ieee10 :: PMD_UncorrectedBlksH :: uncorCountH [15:00] */ 20177 #define DEV1_IEEE10_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_MASK 0xffff 20178 #define DEV1_IEEE10_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_ALIGN 0 20179 #define DEV1_IEEE10_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_BITS 16 20180 #define DEV1_IEEE10_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_SHIFT 0 20181 20182 20183 /**************************************************************************** 20184 * TSC_IEEE_PMA_PMD_dev1_ieee10_tsc_12 20185 */ 20186 /**************************************************************************** 20187 * dev1_ieee10_tsc_12 :: PMD_fecAbility 20188 */ 20189 /* dev1_ieee10_tsc_12 :: PMD_fecAbility :: reserved0 [15:02] */ 20190 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_RESERVED0_MASK 0xfffc 20191 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_RESERVED0_ALIGN 0 20192 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_RESERVED0_BITS 14 20193 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_RESERVED0_SHIFT 2 20194 20195 /* dev1_ieee10_tsc_12 :: PMD_fecAbility :: errorCnt_able [01:01] */ 20196 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_ERRORCNT_ABLE_MASK 0x0002 20197 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_ERRORCNT_ABLE_ALIGN 0 20198 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_ERRORCNT_ABLE_BITS 1 20199 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_ERRORCNT_ABLE_SHIFT 1 20200 20201 /* dev1_ieee10_tsc_12 :: PMD_fecAbility :: fec_able [00:00] */ 20202 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_FEC_ABLE_MASK 0x0001 20203 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_FEC_ABLE_ALIGN 0 20204 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_FEC_ABLE_BITS 1 20205 #define DEV1_IEEE10_TSC_12_PMD_FECABILITY_FEC_ABLE_SHIFT 0 20206 20207 20208 /**************************************************************************** 20209 * dev1_ieee10_tsc_12 :: PMD_fecControl 20210 */ 20211 /* dev1_ieee10_tsc_12 :: PMD_fecControl :: reserved0 [15:02] */ 20212 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_RESERVED0_MASK 0xfffc 20213 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_RESERVED0_ALIGN 0 20214 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_RESERVED0_BITS 14 20215 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_RESERVED0_SHIFT 2 20216 20217 /* dev1_ieee10_tsc_12 :: PMD_fecControl :: errorCnt_en [01:01] */ 20218 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_ERRORCNT_EN_MASK 0x0002 20219 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_ERRORCNT_EN_ALIGN 0 20220 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_ERRORCNT_EN_BITS 1 20221 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_ERRORCNT_EN_SHIFT 1 20222 20223 /* dev1_ieee10_tsc_12 :: PMD_fecControl :: fec_en [00:00] */ 20224 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_FEC_EN_MASK 0x0001 20225 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_FEC_EN_ALIGN 0 20226 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_FEC_EN_BITS 1 20227 #define DEV1_IEEE10_TSC_12_PMD_FECCONTROL_FEC_EN_SHIFT 0 20228 20229 20230 /**************************************************************************** 20231 * dev1_ieee10_tsc_12 :: PMD_CorrectedBlksL 20232 */ 20233 /* dev1_ieee10_tsc_12 :: PMD_CorrectedBlksL :: corCountL [15:00] */ 20234 #define DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSL_CORCOUNTL_MASK 0xffff 20235 #define DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSL_CORCOUNTL_ALIGN 0 20236 #define DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSL_CORCOUNTL_BITS 16 20237 #define DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSL_CORCOUNTL_SHIFT 0 20238 20239 20240 /**************************************************************************** 20241 * dev1_ieee10_tsc_12 :: PMD_CorrectedBlksH 20242 */ 20243 /* dev1_ieee10_tsc_12 :: PMD_CorrectedBlksH :: corCountH [15:00] */ 20244 #define DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSH_CORCOUNTH_MASK 0xffff 20245 #define DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSH_CORCOUNTH_ALIGN 0 20246 #define DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSH_CORCOUNTH_BITS 16 20247 #define DEV1_IEEE10_TSC_12_PMD_CORRECTEDBLKSH_CORCOUNTH_SHIFT 0 20248 20249 20250 /**************************************************************************** 20251 * dev1_ieee10_tsc_12 :: PMD_UncorrectedBlksL 20252 */ 20253 /* dev1_ieee10_tsc_12 :: PMD_UncorrectedBlksL :: uncorCountL [15:00] */ 20254 #define DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_MASK 0xffff 20255 #define DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_ALIGN 0 20256 #define DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_BITS 16 20257 #define DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSL_UNCORCOUNTL_SHIFT 0 20258 20259 20260 /**************************************************************************** 20261 * dev1_ieee10_tsc_12 :: PMD_UncorrectedBlksH 20262 */ 20263 /* dev1_ieee10_tsc_12 :: PMD_UncorrectedBlksH :: uncorCountH [15:00] */ 20264 #define DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_MASK 0xffff 20265 #define DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_ALIGN 0 20266 #define DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_BITS 16 20267 #define DEV1_IEEE10_TSC_12_PMD_UNCORRECTEDBLKSH_UNCORCOUNTH_SHIFT 0 20268 20269 20270 /**************************************************************************** 20271 * TSC_IEEE_PCS_dev3_ieee2 20272 */ 20273 /**************************************************************************** 20274 * dev3_ieee2 :: PCS_errored_blocks_ho 20275 */ 20276 /* dev3_ieee2 :: PCS_errored_blocks_ho :: errored_blocks_ho_present [15:15] */ 20277 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_MASK 0x8000 20278 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_ALIGN 0 20279 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_BITS 1 20280 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_SHIFT 15 20281 20282 /* dev3_ieee2 :: PCS_errored_blocks_ho :: reserved0 [14:14] */ 20283 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_RESERVED0_MASK 0x4000 20284 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_RESERVED0_ALIGN 0 20285 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_RESERVED0_BITS 1 20286 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_RESERVED0_SHIFT 14 20287 20288 /* dev3_ieee2 :: PCS_errored_blocks_ho :: errored_blocks_ho [13:00] */ 20289 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_MASK 0x3fff 20290 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_ALIGN 0 20291 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_BITS 14 20292 #define DEV3_IEEE2_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_SHIFT 0 20293 20294 20295 /**************************************************************************** 20296 * Datatype Definitions. 20297 */ 20298 #endif /* #ifndef TSCMOD_H_TMP__ */ 20299 20300 /* End of File */ 20301