serdescombo65.h (56077B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: serdescombo65.h 8 * Purpose: BCM5621X (Raptor) Internal Combo Port PHY Driver 9 * 10/100/1000/2500 10 */ 11 12 #ifndef _SERDES_COMBO65_H_ 13 #define _SERDES_COMBO65_H_ 14 15 /* SERDES register access */ 16 #define SERDESCOMBO65_REG_READ(_unit, _phy_ctrl, flags, \ 17 _reg_addr, _val) \ 18 phy_reg_aer_read((_unit), (_phy_ctrl), \ 19 (_reg_addr), (_val)) 20 #define SERDESCOMBO65_REG_WRITE(_unit, _phy_ctrl, _flags, \ 21 _reg_addr, _val) \ 22 phy_reg_aer_write((_unit), (_phy_ctrl), \ 23 (_reg_addr), (_val)) 24 #define SERDESCOMBO65_REG_MODIFY(_unit, _phy_ctrl, _flags, \ 25 _reg_addr, _val, _mask) \ 26 phy_reg_aer_modify((_unit), (_phy_ctrl), \ 27 (_reg_addr), (_val), (_mask)) 28 29 30 /* 31 * Register definitions for Internal SerDes 10/100/1000/2500 PHY with CL73 32 */ 33 34 /***************************/ 35 /* Standard IEEE Registers */ 36 /***************************/ 37 38 /* MII Control (Addr 00h) */ 39 #define READ_COMBO_IEEE0_MII_CTRLr(_unit, _phy_ctrl, _val) \ 40 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 41 0x00, 0x0000FFE0, (_val)) 42 #define WRITE_COMBO_IEEE0_MII_CTRLr(_unit, _phy_ctrl, _val) \ 43 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 44 0x00, 0x0000FFE0, (_val)) 45 #define MODIFY_COMBO_IEEE0_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 46 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000FFE0, \ 47 (_val), (_mask)) 48 49 /* MII Status (Addr 01h) */ 50 #define READ_COMBO_IEEE0_MII_STATr(_unit, _phy_ctrl, _val) \ 51 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 52 0x00, 0xFFE1, (_val)) 53 #define WRITE_COMBO_IEEE0_MII_STATr(_unit, _phy_ctrl, _val) \ 54 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 55 0x00, 0xFFE1, (_val)) 56 #define MODIFY_COMBO_IEEE0_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 57 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0xFFE1, \ 58 (_val), (_mask)) 59 60 /* PHY ID 0 (Addr 02h) */ 61 #define READ_COMBO_IEEE0_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 62 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 63 0x00, 0xFFE2, (_val)) 64 #define WRITE_COMBO_IEEE0_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 65 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 66 0x00, 0xFFE2, (_val)) 67 #define MODIFY_COMBO_IEEE0_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 68 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0xFFE2, \ 69 (_val), (_mask)) 70 71 /* PHY ID 1 (Addr 03h) */ 72 #define READ_COMBO_IEEE0_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 73 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 74 0x00, 0xFFE3, (_val)) 75 #define WRITE_COMBO_IEEE0_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 76 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 77 0x00, 0xFFE3, (_val)) 78 #define MODIFY_COMBO_IEEE0_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 79 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0xFFE3, \ 80 (_val), (_mask)) 81 82 /* Autoneg Adv (Addr 04h) */ 83 #define READ_COMBO_IEEE0_MII_ANAr(_unit, _phy_ctrl, _val) \ 84 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 85 0x00, 0xFFE4, (_val)) 86 #define WRITE_COMBO_IEEE0_MII_ANAr(_unit, _phy_ctrl, _val) \ 87 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 88 0x00, 0xFFE4, (_val)) 89 #define MODIFY_COMBO_IEEE0_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 90 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0xFFE4, \ 91 (_val), (_mask)) 92 93 /* Autoneg Link Partner Ability (Addr 05h) */ 94 #define READ_COMBO_IEEE0_MII_ANPr(_unit, _phy_ctrl, _val) \ 95 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 96 0x00, 0xFFE5, (_val)) 97 #define WRITE_COMBO_IEEE0_MII_ANPr(_unit, _phy_ctrl, _val) \ 98 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 99 0x00, 0xFFE5, (_val)) 100 #define MODIFY_COMBO_IEEE0_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 101 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0xFFE5, \ 102 (_val), (_mask)) 103 104 /* Autoneg Expansion (Addr 06h) */ 105 #define READ_COMBO_IEEE0_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 106 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 107 0x00, 0xFFE6, (_val)) 108 #define WRITE_COMBO_IEEE0_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 109 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 110 0x00, 0xFFE6, (_val)) 111 #define MODIFY_COMBO_IEEE0_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 112 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0xFFE6, \ 113 (_val), (_mask)) 114 115 /* Extended Status (Addr 0fh) */ 116 117 /*****************************/ 118 /* XGXS Block 0 (Blk 0x8000) */ 119 /*****************************/ 120 /* XGXS Control Register (Addr 8000h) */ 121 #define READ_XGXS_BLK0_CTRLr(_unit, _phy_ctrl, _val) \ 122 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 123 0x00, 0x00008000, (_val)) 124 #define WRITE_XGXS_BLK0_CTRLr(_unit, _phy_ctrl, _val) \ 125 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 126 0x00, 0x00008000, (_val)) 127 #define MODIFY_XGXS_BLK0_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 128 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008000, \ 129 (_val), (_mask)) 130 131 /* XGXS Status Register (Addr 8001h) */ 132 #define READ_XGXS_BLK0_STATr(_unit, _phy_ctrl, _val) \ 133 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 134 0x00, 0x00008001, (_val)) 135 #define WRITE_XGXS_BLK0_STATr(_unit, _phy_ctrl, _val) \ 136 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 137 0x00, 0x00008001, (_val)) 138 #define MODIFY_XGXS_BLK0_STATr(_unit, _phy_ctrl, _val, _mask) \ 139 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008001, \ 140 (_val), (_mask)) 141 142 /*************************/ 143 /* TX ALL (Block 0x80A0) */ 144 /*************************/ 145 /* TX AStatus 0 (Addr 80A0h) */ 146 /* TX AControl 0 (Addr 80A1h) */ 147 /* TX mdata 0 (Addr 80A2h) */ 148 /* TX mdata 1 (Addr 80A3h) */ 149 /* TX AStatus 1 (Addr 80A4h) */ 150 /* TX BgVcm (Addr 80A5h) */ 151 /* TX lbuff 1T2T (Addr 80A6h) */ 152 153 /* TX Driver (Addr 80A7h) */ 154 #define READ_TX_ALL_DRIVERr(_unit, _phy_ctrl, _val) \ 155 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 156 0x00, 0x000080A7, (_val)) 157 #define WRITE_TX_ALL_DRIVERr(_unit, _phy_ctrl, _val) \ 158 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 159 0x00, 0x000080A7, (_val)) 160 #define MODIFY_TX_ALL_DRIVERr(_unit, _phy_ctrl, _val, _mask) \ 161 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000080A7, \ 162 (_val), (_mask)) 163 164 165 166 /*************************/ 167 /* SerDes Digital Block (Blk 0x8300) */ 168 /*************************/ 169 /* 1000X Control 1 (Addr 8300h) */ 170 #define READ_SERDES_DIGITAL_CTRL1r(_unit, _phy_ctrl, _val) \ 171 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 172 0x00, 0x8300, (_val)) 173 #define WRITE_SERDES_DIGITAL_CTRL1r(_unit, _phy_ctrl, _val) \ 174 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 175 0x00, 0x8300, (_val)) 176 #define MODIFY_SERDES_DIGITAL_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 177 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8300, \ 178 (_val), (_mask)) 179 180 /* DIGITAL_1000X Control 2 (Addr 8301h) */ 181 #define READ_SERDES_DIGITAL_CTRL2r(_unit, _phy_ctrl, _val) \ 182 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 183 0x00, 0x8301, (_val)) 184 #define WRITE_SERDES_DIGITAL_CTRL2r(_unit, _phy_ctrl, _val) \ 185 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 186 0x00, 0x8301, (_val)) 187 #define MODIFY_SERDES_DIGITAL_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 188 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8301, \ 189 (_val), (_mask)) 190 191 /* DIGITAL_1000X Control 3 (Addr 8302h) */ 192 #define READ_SERDES_DIGITAL_CTRL3r(_unit, _phy_ctrl, _val) \ 193 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 194 0x00, 0x8302, (_val)) 195 #define WRITE_SERDES_DIGITAL_CTRL3r(_unit, _phy_ctrl, _val) \ 196 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 197 0x00, 0x8302, (_val)) 198 #define MODIFY_SERDES_DIGITAL_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 199 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8302, \ 200 (_val), (_mask)) 201 202 /* DIGITAL_1000X Control 4 (Addr 8303h) */ 203 #define READ_SERDES_DIGITAL_CTRL4r(_unit, _phy_ctrl, _val) \ 204 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 205 0x00, 0x8303, (_val)) 206 #define WRITE_SERDES_DIGITAL_CTRL4r(_unit, _phy_ctrl, _val) \ 207 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 208 0x00, 0x8303, (_val)) 209 #define MODIFY_SERDES_DIGITAL_CTRL4r(_unit, _phy_ctrl, _val, _mask) \ 210 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8303, \ 211 (_val), (_mask)) 212 213 /* DIGITAL_1000X Status 1 (Addr 8304h) */ 214 #define READ_SERDES_DIGITAL_STAT1r(_unit, _phy_ctrl, _val) \ 215 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 216 0x00, 0x8304, (_val)) 217 #define WRITE_SERDES_DIGITAL_STAT1r(_unit, _phy_ctrl, _val) \ 218 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 219 0x00, 0x8304, (_val)) 220 #define MODIFY_SERDES_DIGITAL_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 221 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8304, \ 222 (_val), (_mask)) 223 224 /* DIGITAL_1000X Status 2 (Addr 8305h) */ 225 #define READ_SERDES_DIGITAL_STAT2r(_unit, _phy_ctrl, _val) \ 226 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 227 0x00, 0x8305, (_val)) 228 #define WRITE_SERDES_DIGITAL_STAT2r(_unit, _phy_ctrl, _val) \ 229 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 230 0x00, 0x8305, (_val)) 231 #define MODIFY_SERDES_DIGITAL_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 232 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8305, \ 233 (_val), (_mask)) 234 235 /* DIGITAL_1000X Status 3 (Addr 8306h) */ 236 #define READ_SERDES_DIGITAL_STAT3r(_unit, _phy_ctrl, _val) \ 237 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 238 0x00, 0x8306, (_val)) 239 #define WRITE_SERDES_DIGITAL_STAT3r(_unit, _phy_ctrl, _val) \ 240 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 241 0x00, 0x8306, (_val)) 242 #define MODIFY_SERDES_DIGITAL_STAT3r(_unit, _phy_ctrl, _val, _mask) \ 243 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8306, \ 244 (_val), (_mask)) 245 246 /* Ber Crc Err Rx Pkt cntr (Addr 8307h) */ 247 #define READ_SERDES_DIGITAL_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 248 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 249 0x00, 0x8307, (_val)) 250 #define WRITE_SERDES_DIGITAL_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 251 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 252 0x00, 0x8307, (_val)) 253 #define MODIFY_SERDES_DIGITAL_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 254 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8307, \ 255 (_val), (_mask)) 256 257 /* Misc1 (Addr 8308h) */ 258 #define READ_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val) \ 259 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 260 0x00, 0x8308, (_val)) 261 #define WRITE_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val) \ 262 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 263 0x00, 0x8308, (_val)) 264 #define MODIFY_SERDES_DIGITAL_MISC1r(_unit, _phy_ctrl, _val, _mask) \ 265 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8308, \ 266 (_val), (_mask)) 267 268 /* Misc2 (Addr 8309h) */ 269 #define READ_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val) \ 270 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 271 0x00, 0x8309, (_val)) 272 #define WRITE_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val) \ 273 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 274 0x00, 0x8309, (_val)) 275 #define MODIFY_SERDES_DIGITAL_MISC2r(_unit, _phy_ctrl, _val, _mask) \ 276 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8309, \ 277 (_val), (_mask)) 278 279 /* Pat Gen Control (Addr 830Ah) */ 280 #define READ_SERDES_DIGITAL_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 281 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 282 0x00, 0x830a, (_val)) 283 #define WRITE_SERDES_DIGITAL_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 284 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 285 0x00, 0x830a, (_val)) 286 #define MODIFY_SERDES_DIGITAL_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 287 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x830a, \ 288 (_val), (_mask)) 289 290 /* Pat Gen Status (Addr 830Bh) */ 291 #define READ_SERDES_DIGITAL_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 292 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 293 0x00, 0x830b, (_val)) 294 #define WRITE_SERDES_DIGITAL_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 295 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 296 0x00, 0x830b, (_val)) 297 #define MODIFY_SERDES_DIGITAL_PAT_GEN_STATr(_unit, _phy_ctrl, _val, _mask) \ 298 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x830b, \ 299 (_val), (_mask)) 300 301 /* Test Mode (Addr 830Ch) */ 302 #define READ_SERDES_DIGITAL_TEST_MODEr(_unit, _phy_ctrl, _val) \ 303 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 304 0x00, 0x830c, (_val)) 305 #define WRITE_SERDES_DIGITAL_TEST_MODEr(_unit, _phy_ctrl, _val) \ 306 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 307 0x00, 0x830c, (_val)) 308 #define MODIFY_SERDES_DIGITAL_TEST_MODEr(_unit, _phy_ctrl, _val, _mask) \ 309 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x830c, \ 310 (_val), (_mask)) 311 312 /* Tx Pkt Cnt (Addr 830Dh) */ 313 #define READ_SERDES_DIGITAL_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 314 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 315 0x00, 0x830d, (_val)) 316 #define WRITE_SERDES_DIGITAL_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 317 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 318 0x00, 0x830d, (_val)) 319 #define MODIFY_SERDES_DIGITAL_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val, _mask) \ 320 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x830d, \ 321 (_val), (_mask)) 322 323 /* Rx Pkt Cnt (Addr 830Eh) */ 324 #define READ_SERDES_DIGITAL_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 325 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 326 0x00, 0x830e, (_val)) 327 #define WRITE_SERDES_DIGITAL_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 328 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 329 0x00, 0x830e, (_val)) 330 #define MODIFY_SERDES_DIGITAL_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val, _mask) \ 331 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x830e, \ 332 (_val), (_mask)) 333 334 /************************/ 335 /* Test (Blk 8310-831F) */ 336 /************************/ 337 338 /***************************/ 339 /* Over 1G (Blk 8320-832F) */ 340 /***************************/ 341 #define READ_OVER_1G_DIGCTL_3_0r(_unit, _phy_ctrl, _val) \ 342 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 343 0x00, 0x00008320, (_val)) 344 #define WRITE_OVER_1G_DIGCTL_3_0r(_unit, _phy_ctrl, _val) \ 345 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 346 0x00, 0x00008320, (_val)) 347 #define MODIFY_OVER_1G_DIGCTL_3_0r(_unit, _phy_ctrl, _val, _mask) \ 348 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008320, \ 349 (_val), (_mask)) 350 351 #define READ_OVER_1G_DIGCTL_3_1r(_unit, _phy_ctrl, _val) \ 352 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 353 0x00, 0x00008321, (_val)) 354 #define WRITE_OVER_1G_DIGCTL_3_1r(_unit, _phy_ctrl, _val) \ 355 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 356 0x00, 0x00008321, (_val)) 357 #define MODIFY_OVER_1G_DIGCTL_3_1r(_unit, _phy_ctrl, _val, _mask) \ 358 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008321, \ 359 (_val), (_mask)) 360 361 #define READ_OVER_1G_DIGCTL_3_2r(_unit, _phy_ctrl, _val) \ 362 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 363 0x00, 0x00008322, (_val)) 364 #define WRITE_OVER_1G_DIGCTL_3_2r(_unit, _phy_ctrl, _val) \ 365 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 366 0x00, 0x00008322, (_val)) 367 #define MODIFY_OVER_1G_DIGCTL_3_2r(_unit, _phy_ctrl, _val, _mask) \ 368 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008322, \ 369 (_val), (_mask)) 370 371 #define READ_OVER_1G_DIGCTL_3_3r(_unit, _phy_ctrl, _val) \ 372 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 373 0x00, 0x00008323, (_val)) 374 #define WRITE_OVER_1G_DIGCTL_3_3r(_unit, _phy_ctrl, _val) \ 375 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 376 0x00, 0x00008323, (_val)) 377 #define MODIFY_OVER_1G_DIGCTL_3_3r(_unit, _phy_ctrl, _val, _mask) \ 378 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008323, \ 379 (_val), (_mask)) 380 381 #define READ_OVER_1G_DIGCTL_3_4r(_unit, _phy_ctrl, _val) \ 382 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 383 0x00, 0x00008324, (_val)) 384 #define WRITE_OVER_1G_DIGCTL_3_4r(_unit, _phy_ctrl, _val) \ 385 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 386 0x00, 0x00008324, (_val)) 387 #define MODIFY_OVER_1G_DIGCTL_3_4r(_unit, _phy_ctrl, _val, _mask) \ 388 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008324, \ 389 (_val), (_mask)) 390 391 #define READ_OVER_1G_DIGCTL_3_5r(_unit, _phy_ctrl, _val) \ 392 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 393 0x00, 0x00008325, (_val)) 394 #define WRITE_OVER_1G_DIGCTL_3_5r(_unit, _phy_ctrl, _val) \ 395 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 396 0x00, 0x00008325, (_val)) 397 #define MODIFY_OVER_1G_DIGCTL_3_5r(_unit, _phy_ctrl, _val, _mask) \ 398 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008325, \ 399 (_val), (_mask)) 400 401 #define READ_OVER_1G_DIGCTL_3_6r(_unit, _phy_ctrl, _val) \ 402 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 403 0x00, 0x00008326, (_val)) 404 #define WRITE_OVER_1G_DIGCTL_3_6r(_unit, _phy_ctrl, _val) \ 405 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 406 0x00, 0x00008326, (_val)) 407 #define MODIFY_OVER_1G_DIGCTL_3_6r(_unit, _phy_ctrl, _val, _mask) \ 408 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008326, \ 409 (_val), (_mask)) 410 411 #define READ_OVER_1G_TPOUT1r(_unit, _phy_ctrl, _val) \ 412 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 413 0x00, 0x00008327, (_val)) 414 #define WRITE_OVER_1G_TPOUT1r(_unit, _phy_ctrl, _val) \ 415 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 416 0x00, 0x00008327, (_val)) 417 #define MODIFY_OVER_1G_TPOUT1r(_unit, _phy_ctrl, _val, _mask) \ 418 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008327, \ 419 (_val), (_mask)) 420 421 #define READ_OVER_1G_TPOUT2r(_unit, _phy_ctrl, _val) \ 422 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 423 0x00, 0x00008328, (_val)) 424 #define WRITE_OVER_1G_TPOUT2r(_unit, _phy_ctrl, _val) \ 425 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 426 0x00, 0x00008328, (_val)) 427 #define MODIFY_OVER_1G_TPOUT2r(_unit, _phy_ctrl, _val, _mask) \ 428 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008328, \ 429 (_val), (_mask)) 430 431 #define READ_OVER_1G_UP1r(_unit, _phy_ctrl, _val) \ 432 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 433 0x00, 0x00008329, (_val)) 434 #define WRITE_OVER_1G_UP1r(_unit, _phy_ctrl, _val) \ 435 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 436 0x00, 0x00008329, (_val)) 437 #define MODIFY_OVER_1G_UP1r(_unit, _phy_ctrl, _val, _mask) \ 438 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008329, \ 439 (_val), (_mask)) 440 441 #define READ_OVER_1G_UP2r(_unit, _phy_ctrl, _val) \ 442 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 443 0x00, 0x0000832A, (_val)) 444 #define WRITE_OVER_1G_UP2r(_unit, _phy_ctrl, _val) \ 445 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 446 0x00, 0x0000832A, (_val)) 447 #define MODIFY_OVER_1G_UP2r(_unit, _phy_ctrl, _val, _mask) \ 448 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000832A, \ 449 (_val), (_mask)) 450 451 452 #define READ_OVER_1G_UP3r(_unit, _phy_ctrl, _val) \ 453 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 454 0x00, 0x0000832B, (_val)) 455 #define WRITE_OVER_1G_UP3r(_unit, _phy_ctrl, _val) \ 456 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 457 0x00, 0x0000832B, (_val)) 458 #define MODIFY_OVER_1G_UP3r(_unit, _phy_ctrl, _val, _mask) \ 459 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000832B, \ 460 (_val), (_mask)) 461 462 #define READ_OVER_1G_LP_UP1r(_unit, _phy_ctrl, _val) \ 463 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 464 0x00, 0x0000832C, (_val)) 465 #define WRITE_OVER_1G_LP_UP1r(_unit, _phy_ctrl, _val) \ 466 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 467 0x00, 0x0000832C, (_val)) 468 #define MODIFY_OVER_1G_LP_UP1r(_unit, _phy_ctrl, _val, _mask) \ 469 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000832C, \ 470 (_val), (_mask)) 471 472 #define READ_OVER_1G_LP_UP2r(_unit, _phy_ctrl, _val) \ 473 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 474 0x00, 0x0000832D, (_val)) 475 #define WRITE_OVER_1G_LP_UP2r(_unit, _phy_ctrl, _val) \ 476 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 477 0x00, 0x0000832D, (_val)) 478 #define MODIFY_OVER_1G_LP_UP2r(_unit, _phy_ctrl, _val, _mask) \ 479 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000832D, \ 480 (_val), (_mask)) 481 482 #define READ_OVER_1G_LP_UP3r(_unit, _phy_ctrl, _val) \ 483 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 484 0x00, 0x0000832E, (_val)) 485 #define WRITE_OVER_1G_LP_UP3r(_unit, _phy_ctrl, _val) \ 486 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 487 0x00, 0x0000832E, (_val)) 488 #define MODIFY_OVER_1G_LP_UP3r(_unit, _phy_ctrl, _val, _mask) \ 489 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000832E, \ 490 (_val), (_mask)) 491 492 /******************************/ 493 /* Remote PHY (Blk 8330-833F) */ 494 /******************************/ 495 496 /*********************************/ 497 /* BAM Next Page (Blk 8350-835F) */ 498 /*********************************/ 499 500 /*************************************/ 501 /* Clause 73 User B0 (BLK 8370-837F) */ 502 /*************************************/ 503 /* CL73 UCtrl 1 (Addr 8370h) */ 504 #define READ_CL73_USERB0_UCTRL1r(_unit, _phy_ctrl, _val) \ 505 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 506 0x00, 0x8370, (_val)) 507 #define WRITE_CL73_USERB0_UCTRL1r(_unit, _phy_ctrl, _val) \ 508 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 509 0x00, 0x8370, (_val)) 510 #define MODIFY_CL73_USERB0_UCTRL1r(_unit, _phy_ctrl, _val, _mask) \ 511 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8370, \ 512 (_val), (_mask)) 513 514 /* CL73_UStat1 (Addr 8371h) */ 515 #define READ_CL73_USERB0_USTAT1r(_unit, _phy_ctrl, _val) \ 516 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 517 0x00, 0x8371, (_val)) 518 #define WRITE_CL73_USERB0_USTAT1r(_unit, _phy_ctrl, _val) \ 519 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 520 0x00, 0x8371, (_val)) 521 #define MODIFY_CL73_USERB0_USTAT1r(_unit, _phy_ctrl, _val, _mask) \ 522 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8371, \ 523 (_val), (_mask)) 524 525 /* CL73_BAMCtrl1 (Addr 8372h) */ 526 #define READ_CL73_USERB0_BAMCTRL1r(_unit, _phy_ctrl, _val) \ 527 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 528 0x00, 0x8372, (_val)) 529 #define WRITE_CL73_USERB0_BAMCTRL1r(_unit, _phy_ctrl, _val) \ 530 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 531 0x00, 0x8372, (_val)) 532 #define MODIFY_CL73_USERB0_BAMCTRL1r(_unit, _phy_ctrl, _val, _mask) \ 533 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8372, \ 534 (_val), (_mask)) 535 536 /* CL73_BAMCtrl2 (Addr 8373h) */ 537 #define READ_CL73_USERB0_BAMCTRL2r(_unit, _phy_ctrl, _val) \ 538 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 539 0x00, 0x8373, (_val)) 540 #define WRITE_CL73_USERB0_BAMCTRL2r(_unit, _phy_ctrl, _val) \ 541 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 542 0x00, 0x8373, (_val)) 543 #define MODIFY_CL73_USERB0_BAMCTRL2r(_unit, _phy_ctrl, _val, _mask) \ 544 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8373, \ 545 (_val), (_mask)) 546 547 /* CL73_BAMCtrl3 (Addr 8374h) */ 548 #define READ_CL73_USERB0_BAMCTRL3r(_unit, _phy_ctrl, _val) \ 549 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 550 0x00, 0x8374, (_val)) 551 #define WRITE_CL73_USERB0_BAMCTRL3r(_unit, _phy_ctrl, _val) \ 552 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 553 0x00, 0x8374, (_val)) 554 #define MODIFY_CL73_USERB0_BAMCTRL3r(_unit, _phy_ctrl, _val, _mask) \ 555 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8374, \ 556 (_val), (_mask)) 557 558 /* CL73_BAMStat1 (Addr 8375h) */ 559 #define READ_CL73_USERB0_BAMSTAT1r(_unit, _phy_ctrl, _val) \ 560 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 561 0x00, 0x8375, (_val)) 562 #define WRITE_CL73_USERB0_BAMSTAT1r(_unit, _phy_ctrl, _val) \ 563 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 564 0x00, 0x8375, (_val)) 565 #define MODIFY_CL73_USERB0_BAMSTAT1r(_unit, _phy_ctrl, _val, _mask) \ 566 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8375, \ 567 (_val), (_mask)) 568 569 /* CL73_BAMStat2 (Addr 8376h) */ 570 #define READ_CL73_USERB0_BAMSTAT2r(_unit, _phy_ctrl, _val) \ 571 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 572 0x00, 0x8376, (_val)) 573 #define WRITE_CL73_USERB0_BAMSTAT2r(_unit, _phy_ctrl, _val) \ 574 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 575 0x00, 0x8376, (_val)) 576 #define MODIFY_CL73_USERB0_BAMSTAT2r(_unit, _phy_ctrl, _val, _mask) \ 577 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8376, \ 578 (_val), (_mask)) 579 580 /* CL73_BAMStat3 (Addr 8377h) */ 581 #define READ_CL73_USERB0_BAMSTAT3r(_unit, _phy_ctrl, _val) \ 582 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 583 0x00, 0x8377, (_val)) 584 #define WRITE_CL73_USERB0_BAMSTAT3r(_unit, _phy_ctrl, _val) \ 585 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 586 0x00, 0x8377, (_val)) 587 #define MODIFY_CL73_USERB0_BAMSTAT3r(_unit, _phy_ctrl, _val, _mask) \ 588 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x8377, \ 589 (_val), (_mask)) 590 591 /*****************/ 592 /* Clause 73 MMD */ 593 /*****************/ 594 /*********************/ 595 /* CL73_IEEEB0 Block */ 596 /*********************/ 597 /* CL73 AN Control (Addr 0000h) */ 598 #define READ_CL73_IEEEB0_AN_CTRLr(_unit, _phy_ctrl, _val) \ 599 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 600 0x00, 0x38000000, (_val)) 601 #define WRITE_CL73_IEEEB0_AN_CTRLr(_unit, _phy_ctrl, _val) \ 602 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 603 0x00, 0x38000000, (_val)) 604 #define MODIFY_CL73_IEEEB0_AN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 605 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000000, \ 606 (_val), (_mask)) 607 608 /* CL73 AN Status (Addr 0001h) */ 609 #define READ_CL73_IEEEB0_AN_STATr(_unit, _phy_ctrl, _val) \ 610 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 611 0x00, 0x38000001, (_val)) 612 #define WRITE_CL73_IEEEB0_AN_STATr(_unit, _phy_ctrl, _val) \ 613 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 614 0x00, 0x38000001, (_val)) 615 #define MODIFY_CL73_IEEEB0_AN_STATr(_unit, _phy_ctrl, _val, _mask) \ 616 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000001, \ 617 (_val), (_mask)) 618 619 /* CL73 PhyIdMsb (Addr 0002h) */ 620 #define READ_CL73_IEEEB0_PHY_ID_MSBr(_unit, _phy_ctrl, _val) \ 621 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 622 0x00, 0x38000002, (_val)) 623 #define WRITE_CL73_IEEEB0_PHY_ID_MSBr(_unit, _phy_ctrl, _val) \ 624 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 625 0x00, 0x38000002, (_val)) 626 #define MODIFY_CL73_IEEEB0_PHY_ID_MSBr(_unit, _phy_ctrl, _val, _mask) \ 627 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000002, \ 628 (_val), (_mask)) 629 630 /* CL73 PhyIdLsb (Addr 0003h) */ 631 #define READ_CL73_IEEEB0_PHY_ID_LSBr(_unit, _phy_ctrl, _val) \ 632 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 633 0x00, 0x38000003, (_val)) 634 #define WRITE_CL73_IEEEB0_PHY_ID_LSBr(_unit, _phy_ctrl, _val) \ 635 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 636 0x00, 0x38000003, (_val)) 637 #define MODIFY_CL73_IEEEB0_PHY_ID_LSBr(_unit, _phy_ctrl, _val, _mask) \ 638 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000003, \ 639 (_val), (_mask)) 640 641 /* IeeeDevInPkg1 (Addr 0005h) */ 642 #define READ_CL73_IEEEB0_DEV_IN_PKG1r(_unit, _phy_ctrl, _val) \ 643 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 644 0x00, 0x38000005, (_val)) 645 #define WRITE_CL73_IEEEB0_DEV_IN_PKG1r(_unit, _phy_ctrl, _val) \ 646 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 647 0x00, 0x38000005, (_val)) 648 #define MODIFY_CL73_IEEEB0_DEV_IN_PKG1r(_unit, _phy_ctrl, _val, _mask) \ 649 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000005, \ 650 (_val), (_mask)) 651 652 /* IeeeDevInPkg2 (Addr 0006h) */ 653 #define READ_CL73_IEEEB0_DEV_IN_PKG2r(_unit, _phy_ctrl, _val) \ 654 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 655 0x00, 0x38000006, (_val)) 656 #define WRITE_CL73_IEEEB0_DEV_IN_PKG2r(_unit, _phy_ctrl, _val) \ 657 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 658 0x00, 0x38000006, (_val)) 659 #define MODIFY_CL73_IEEEB0_DEV_IN_PKG2r(_unit, _phy_ctrl, _val, _mask) \ 660 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000006, \ 661 (_val), (_mask)) 662 663 /*********************/ 664 /* CL73 IEEEB1 Block */ 665 /*********************/ 666 /* AN adv1 (Addr 0010h) */ 667 #define READ_CL73_IEEEB1_AN_ADV1r(_unit, _phy_ctrl, _val) \ 668 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 669 0x00, 0x38000010, (_val)) 670 #define WRITE_CL73_IEEEB1_AN_ADV1r(_unit, _phy_ctrl, _val) \ 671 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 672 0x00, 0x38000010, (_val)) 673 #define MODIFY_CL73_IEEEB1_AN_ADV1r(_unit, _phy_ctrl, _val, _mask) \ 674 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000010, \ 675 (_val), (_mask)) 676 677 /* AN adv2 (Addr 0011h) */ 678 #define READ_CL73_IEEEB1_AN_ADV2r(_unit, _phy_ctrl, _val) \ 679 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 680 0x00, 0x38000011, (_val)) 681 #define WRITE_CL73_IEEEB1_AN_ADV2r(_unit, _phy_ctrl, _val) \ 682 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 683 0x00, 0x38000011, (_val)) 684 #define MODIFY_CL73_IEEEB1_AN_ADV2r(_unit, _phy_ctrl, _val, _mask) \ 685 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000011, \ 686 (_val), (_mask)) 687 688 /* AN adv3 (Addr 0012h) */ 689 #define READ_CL73_IEEEB1_AN_ADV3r(_unit, _phy_ctrl, _val) \ 690 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 691 0x00, 0x38000012, (_val)) 692 #define WRITE_CL73_IEEEB1_AN_ADV3r(_unit, _phy_ctrl, _val) \ 693 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 694 0x00, 0x38000012, (_val)) 695 #define MODIFY_CL73_IEEEB1_AN_ADV3r(_unit, _phy_ctrl, _val, _mask) \ 696 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000012, \ 697 (_val), (_mask)) 698 699 /* AN lp adv1 (Addr 0013h) */ 700 #define READ_CL73_IEEEB1_LP_ADV1r(_unit, _phy_ctrl, _val) \ 701 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 702 0x00, 0x38000013, (_val)) 703 #define WRITE_CL73_IEEEB1_LP_ADV1r(_unit, _phy_ctrl, _val) \ 704 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 705 0x00, 0x38000013, (_val)) 706 #define MODIFY_CL73_IEEEB1_LP_ADV1r(_unit, _phy_ctrl, _val, _mask) \ 707 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000013, \ 708 (_val), (_mask)) 709 710 /* AN lp adv2 (Addr 0014h) */ 711 #define READ_CL73_IEEEB1_LP_ADV2r(_unit, _phy_ctrl, _val) \ 712 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 713 0x00, 0x38000014, (_val)) 714 #define WRITE_CL73_IEEEB1_LP_ADV2r(_unit, _phy_ctrl, _val) \ 715 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 716 0x00, 0x38000014, (_val)) 717 #define MODIFY_CL73_IEEEB1_LP_ADV2r(_unit, _phy_ctrl, _val, _mask) \ 718 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000014, \ 719 (_val), (_mask)) 720 721 /* AN lp adv3 (Addr 0015h) */ 722 #define READ_CL73_IEEEB1_LP_ADV3r(_unit, _phy_ctrl, _val) \ 723 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 724 0x00, 0x38000015, (_val)) 725 #define WRITE_CL73_IEEEB1_LP_ADV3r(_unit, _phy_ctrl, _val) \ 726 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 727 0x00, 0x38000015, (_val)) 728 #define MODIFY_CL73_IEEEB1_LP_ADV3r(_unit, _phy_ctrl, _val, _mask) \ 729 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000015, \ 730 (_val), (_mask)) 731 732 /* AN np 1 (Addr 0016h) */ 733 #define READ_CL73_IEEEB1_AN_NP1r(_unit, _phy_ctrl, _val) \ 734 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 735 0x00, 0x38000016, (_val)) 736 #define WRITE_CL73_IEEEB1_AN_NP1r(_unit, _phy_ctrl, _val) \ 737 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 738 0x00, 0x38000016, (_val)) 739 #define MODIFY_CL73_IEEEB1_AN_NP1r(_unit, _phy_ctrl, _val, _mask) \ 740 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000016, \ 741 (_val), (_mask)) 742 743 /* AN np 2 (Addr 0017h) */ 744 #define READ_CL73_IEEEB1_AN_NP2r(_unit, _phy_ctrl, _val) \ 745 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 746 0x00, 0x38000017, (_val)) 747 #define WRITE_CL73_IEEEB1_AN_NP2r(_unit, _phy_ctrl, _val) \ 748 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 749 0x00, 0x38000017, (_val)) 750 #define MODIFY_CL73_IEEEB1_AN_NP2r(_unit, _phy_ctrl, _val, _mask) \ 751 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000017, \ 752 (_val), (_mask)) 753 754 /* AN np 3 (Addr 0018h) */ 755 #define READ_CL73_IEEEB1_AN_NP3r(_unit, _phy_ctrl, _val) \ 756 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 757 0x00, 0x38000018, (_val)) 758 #define WRITE_CL73_IEEEB1_AN_NP3r(_unit, _phy_ctrl, _val) \ 759 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 760 0x00, 0x38000018, (_val)) 761 #define MODIFY_CL73_IEEEB1_AN_NP3r(_unit, _phy_ctrl, _val, _mask) \ 762 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000018, \ 763 (_val), (_mask)) 764 765 /* AN lp np 1 (Addr 0019h) */ 766 #define READ_CL73_IEEEB1_LP_NP1r(_unit, _phy_ctrl, _val) \ 767 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 768 0x00, 0x38000010, (_val)) 769 #define WRITE_CL73_IEEEB1_LP_NP1r(_unit, _phy_ctrl, _val) \ 770 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 771 0x00, 0x38000010, (_val)) 772 #define MODIFY_CL73_IEEEB1_LP_NP1r(_unit, _phy_ctrl, _val, _mask) \ 773 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000010, \ 774 (_val), (_mask)) 775 776 /* AN lp np 2 (Addr 001Ah) */ 777 #define READ_CL73_IEEEB1_LP_NP2r(_unit, _phy_ctrl, _val) \ 778 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 779 0x00, 0x3800001A, (_val)) 780 #define WRITE_CL73_IEEEB1_LP_NP2r(_unit, _phy_ctrl, _val) \ 781 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 782 0x00, 0x3800001A, (_val)) 783 #define MODIFY_CL73_IEEEB1_LP_NP2r(_unit, _phy_ctrl, _val, _mask) \ 784 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x3800001A, \ 785 (_val), (_mask)) 786 787 /* AN lp np 3 (Addr 001Bh) */ 788 #define READ_CL73_IEEEB1_LP_NP3r(_unit, _phy_ctrl, _val) \ 789 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 790 0x00, 0x3800001B, (_val)) 791 #define WRITE_CL73_IEEEB1_LP_NP3r(_unit, _phy_ctrl, _val) \ 792 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 793 0x00, 0x3800001B, (_val)) 794 #define MODIFY_CL73_IEEEB1_LP_NP3r(_unit, _phy_ctrl, _val, _mask) \ 795 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x3800001B, \ 796 (_val), (_mask)) 797 798 /*******************/ 799 /* CL73 IEEEB3 Blk */ 800 /*******************/ 801 /* BPEther Stat (Addr 0030h) */ 802 #define READ_CL73_IEEEB3_BPETHER_STATr(_unit, _phy_ctrl, _val) \ 803 SERDESCOMBO65_REG_READ((_unit), (_phy_ctrl), \ 804 0x00, 0x38000030, (_val)) 805 #define WRITE_CL73_IEEEB3_BPETHER_STATr(_unit, _phy_ctrl, _val) \ 806 SERDESCOMBO65_REG_WRITE((_unit), (_phy_ctrl), \ 807 0x00, 0x38000030, (_val)) 808 #define MODIFY_CL73_IEEEB3_BPETHER_STATr(_unit, _phy_ctrl, _val, _mask) \ 809 SERDESCOMBO65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x38000030, \ 810 (_val), (_mask)) 811 812 813 /* SerDes Digital Block */ 814 /* 1000X Control 1 Register */ 815 #define CTRL1_FIBER_MODE (1 << 0) 816 #define CTRL1_TBI_INTERFACE (1 << 1) 817 #define CTRL1_SIGNAL_DETECT_EN (1 << 2) 818 #define CTRL1_INVERT_SIGNAL_DETECT (1 << 3) 819 #define CTRL1_AUTODET_EN (1 << 4) 820 #define CTRL1_SGMII_MASTER_MODE (1 << 5) 821 #define CTRL1_DISABLE_PLL_PWRDWN (1 << 6) 822 #define CTRL1_CRC_CHECKER_DISABLE (1 << 7) 823 #define CTRL1_COMMA_DET_EN (1 << 8) 824 #define CTRL1_ZERO_COMMA_DETECTOR_PHASE (1 << 9) 825 #define CTRL1_REMOTE_LOOPBACK (1 << 10) 826 #define CTRL1_SEL_RX_PKTS_FOR_CNTR (1 << 11) 827 #define CTRL1_SERDES_TX_AMPLITUDE_OVERRIDE (1 << 12) 828 #define CTRL1_MASTER_MDIO_PHY_SEL (1 << 13) 829 #define CTRL1_DISABLE_SIGNAL_DETECT_FILTER (1 << 14) 830 831 /* 1000X Control 2 Register */ 832 #define CTRL2_ENABLE_PARALLEL_DETECT (1 << 0) 833 #define CTRL2_DISABLE_FALSE_LINK (1 << 1) 834 #define CTRL2_FILTER_FORCE_LINK (1 << 2) 835 #define CTRL2_ENABLE_AUTONEG_ERR_TIMER (1 << 3) 836 #define CTRL2_DISABLE_REMOTE_ERR_TIMER (1 << 4) 837 #define CTRL2_FORCE_XMIT_DATA_ON_TXSIDE (1 << 5) 838 #define CTRL2_AUTONEG_FAST_TIMERS (1 << 6) 839 #define CTRL2_DISABLE_CARRIER_EXTEND (1 << 7) 840 #define CTRL2_DISABLE_TRRRR_GENERATION (1 << 8) 841 #define CTRL2_BYPASS_PCS_RX (1 << 9) 842 #define CTRL2_BYPASS_PCS_TX (1 << 10) 843 #define CTRL2_TEST_CNTR (1 << 11) 844 #define CTRL2_TRANSMIT_PACKET_SEQ_TEST (1 << 12) 845 #define CTRL2_TRANSMIT_IDLEJAM_SEQ_TEST (1 << 13) 846 #define CTRL2_CLEAR_BER_COUNT (1 << 14) 847 #define CTRL2_DISABLE_EXTEND_FDX_ONLY (1 << 15) 848 849 /* 1000X Control 3 Register */ 850 #define CTRL3_TX_FIFO_RST (1 << 0) 851 #define CTRL3_FIFO_ELASTICITY_TX_RX (3 << 1) 852 #define CTRL3_EARLY_PREAMBLE_TX (1 << 3) 853 #define CTRL3_EARLY_PREAMBLE_RX (1 << 4) 854 #define CTRL3_FREQ_LOCK_ELASTICITY_RX (1 << 5) 855 #define CTRL3_FREQ_LOCK_ELASTICITY_TX (1 << 6) 856 #define CTRL3_BYPASS_TXFIFO100 (1 << 7) 857 #define CTRL3_FORCE_FIFO_ON (1 << 8) 858 #define CTRL3_BLOCK_TXEN_MODE (1 << 9) 859 #define CTRL3_JAM_FALSE_CARRIER_MODE (1 << 10) 860 #define CTRL3_EXT_PHY_CRS_MODE (1 << 11) 861 #define CTRL3_INVERT_EXT_PHY_CRS (1 << 12) 862 #define CTRL3_DISABLE_TX_CRS (1 << 13) 863 #define CTRL3_RXFIFO_GMII_RESET (1 << 14) 864 #define CTRL3_DISABLE_PACKET_MISALIGN (1 << 15) 865 866 /* 1000X Control 4 Register */ 867 #define CTRL4_MISC_RX_STAT_SEL (7 << 0) 868 #define CTRL4_NP_COUNT_CLRNRD (1 << 3) 869 #define CTRL4_NP_COUNT_CLRNBP (1 << 4) 870 #define CTRL4_LP_NEXT_PAGE_SEL (1 << 5) 871 #define CTRL4_LINK_FORCE (1 << 7) 872 #define CTRL4_LATCH_LINKDOWN_ENABLE (1 << 8) 873 #define CTRL4_CLEAR_LINKDOWN (1 << 9) 874 #define CTRL4_ZERO_RXDGMII (1 << 10) 875 #define CTRL4_TX_CONFIG_REG_SEL (1 << 11) 876 #define CTRL4_ENABLE_LAST_RESOLUTION_ERR (1 << 12) 877 #define CTRL4_DISABLE_RESOLUTION_ERR_RESTART (1 << 13) 878 879 /* 1000X STATUS 1 Register */ 880 #define STAT1_SGMII_MODE (1 << 0) 881 #define STAT1_LINK_STATUS (1 << 1) 882 #define STAT1_DUPLEX_STATUS (1 << 2) 883 #define STAT1_SPEED_STATUS (3 << 3) 884 #define STAT1_SPEED_10MB (0 << 3) 885 #define STAT1_SPEED_100MB (1 << 3) 886 #define STAT1_SPEED_1000MB (2 << 3) 887 #define STAT1_SPEED_2P5GB (3 << 3) 888 #define STAT1_PAUSE_RESOLUTION_RXSIDE (1 << 5) 889 #define STAT1_PAUSE_RESOLUTION_TXSIDE (1 << 6) 890 #define STAT1_LINK_CHANGED (1 << 7) 891 #define STAT1_EARLY_END_EXTENSION_DETECTED (1 << 8) 892 #define STAT1_CARRIER_EXTEND_ERR_DETECTED (1 << 9) 893 #define STAT1_RX_ERR_DETECTED (1 << 10) 894 #define STAT1_TX_ERR_DETECTED (1 << 11) 895 #define STAT1_CRC_ERR_DETECTED (1 << 12) 896 #define STAT1_FALSE_CARRIER_DETECTED (1 << 13) 897 #define STAT1_RXFIFO_ERR_DETECTED (1 << 14) 898 #define STAT1_TXFIFO_ERR_DETECTED (1 << 15) 899 900 /* 1000X STATUS 2 Register */ 901 #define STAT2_AN_ENABLE_STATE (1 << 0) 902 #define STAT2_AN_ERROR_STATE (1 << 1) 903 #define STAT2_ABILITY_DETECT_STATE (1 << 2) 904 #define STAT2_ACKNOWLEDGE_DETECT_STATE (1 << 3) 905 #define STAT2_COMPLETE_ACKNOWLEDGE_STATE (1 << 4) 906 #define STAT2_IDLE_DETECT_STATE (1 << 5) 907 #define STAT2_LINK_DOWN_LOSS_SYNC (1 << 6) 908 #define STAT2_RUDI_INVALID (1 << 7) 909 #define STAT2_RUDI_L (1 << 8) 910 #define STAT2_RUDI_C (1 << 9) 911 #define STAT2_SYNC_STATUS_OK (1 << 10) 912 #define STAT2_SYNC_STATUS_FAIL (1 << 11) 913 #define STAT2_SGMII_SELECTOR_MISMATCH (1 << 12) 914 #define STAT2_AUTONEG_RESOLUTION_ERR (1 << 13) 915 #define STAT2_CONSISTENCY_MISTMATCH (1 << 14) 916 #define STAT2_SGMII_MODE_CHANGE (1 << 15) 917 918 /* 1000X STATUS 3 Register */ 919 #define STAT3_SD_FILTER_CHG (1 << 7) 920 #define STAT3_SD_MUX (1 << 8) 921 #define STAT3_SD_FILTER (1 << 9) 922 #define STAT3_LATCH_LINKDOWN (1 << 10) 923 #define STAT3_REMOTE_PHY_AUTOSEL (1 << 11) 924 #define STAT3_PD_PARK_AN (1 << 12) 925 926 /* CRC Error/RX Packet Counter Register */ 927 #define COUNTER_CRC_ERR (0xFF << 0) 928 #define COUNTER_RX_PKT (0xFF << 0) 929 #define COUNTER_BIT_ERR_RATE (0xFF << 8) 930 931 /* MISC 1 Register */ 932 #define MISC1_FORCE_SPEED (0xF << 0) 933 #define MISC1_FORCE_SPEED_2P5GB (0 << 0) 934 #define MISC1_FORCE_SPEED_5GB (1 << 0) 935 #define MISC1_FORCE_SPEED_6GB (2 << 0) 936 #define MISC1_FORCE_SPEED_10GB (3 << 0) 937 #define MISC1_FORCE_SPEED_10GB_CX4 (4 << 0) 938 #define MISC1_FORCE_SPEED_12GB (5 << 0) 939 #define MISC1_FORCE_SPEED_12P5GB (6 << 0) 940 #define MISC1_FORCE_SPEED_13GB (7 << 0) 941 #define MISC1_FORCE_SPEED_15GB (8 << 0) 942 #define MISC1_FORCE_SPEED_16GB (9 << 0) 943 #define MISC1_FORCE_SPEED_SEL (1 << 4) 944 #define MISC1_FORCE_LN_MODE (1 << 5) 945 #define MISC1_TX_UNDERRUN_1000_DIS (1 << 6) 946 #define MISC1_FORCE_TICK0_SW (1 << 7) 947 #define MISC1_FORCE_PLL_MODE_AFE (7 << 8) 948 #define MISC1_FORCE_PLL_MODE_AFE_SEL (1 << 12) 949 #define MISC1_REFCLK_SEL (7 << 13) 950 951 /* 952 * Useful constants for XGXS PHY chips 953 */ 954 955 /****************/ 956 /* XGXS Block 0 */ 957 /****************/ 958 /* XGXS Control Register */ 959 #define XGXS_CTRL_TXCKO_DIV (1 << 0) 960 #define XGXS_CTRL_AFRST_EN (1 << 1) 961 #define XGXS_CTRL_EDEN (1 << 2) 962 #define XGXS_CTRL_CDET_EN (1 << 3) 963 #define XGXS_CTRL_MDIO_CONT_EN (1 << 4) 964 #define XGXS_CTRL_HSTL (1 << 5) 965 #define XGXS_CTRL_RLOOP (1 << 6) 966 #define XGXS_CTRL_PLL_BYPASS (1 << 7) 967 #define XGXS_CTRL_MODE_10G (0xF << 8) 968 #define XGXS_CTRL_RESET_ANLG (1 << 12) 969 #define XGXS_CTRL_START_SEQUENCER (1 << 13) 970 #define XGXS_CTRL_PCMP_EN (1 << 14) 971 #define XGXS_CTRL_PGEN_EN (1 << 15) 972 973 /*****************/ 974 /* TX All Block */ 975 /*****************/ 976 /* TX Driver Register */ 977 #define TX_DRIVER_ICBUF1T (1 << 0) 978 #define TX_DRIVER_IFULLSPD (7 << 1) 979 #define TX_DRIVER_IPREDRIVER (0xF << 4) 980 #define TX_DRIVER_IDRIVER (0xF << 8) 981 #define TX_DRIVER_PREEMPHASIS (0xF << 12) 982 983 /*****************/ 984 /* Over 1G Block */ 985 /*****************/ 986 /* UP 1 Register */ 987 #define UP1_ADV_2P5GB (1 << 0) 988 #define UP1_ADV_5GB (1 << 1) 989 #define UP1_ADV_6GB (1 << 2) 990 #define UP1_ADV_10GB (1 << 3) 991 #define UP1_ADV_10GB_CX4 (1 << 4) 992 #define UP1_ADV_12GB (1 << 5) 993 #define UP1_ADV_12P5GB (1 << 6) 994 #define UP1_ADV_13GB (1 << 7) 995 #define UP1_ADV_15GB (1 << 8) 996 #define UP1_ADV_16GB (1 << 9) 997 998 /* LP_UP1 Register */ 999 #define LP_UP1_ADV_2P5GB (1 << 0) 1000 #define LP_UP1_ADV_5GB (1 << 1) 1001 #define LP_UP1_ADV_6GB (1 << 2) 1002 #define LP_UP1_ADV_10GB (1 << 3) 1003 #define LP_UP1_ADV_10GB_CX4 (1 << 4) 1004 #define LP_UP1_ADV_12GB (1 << 5) 1005 #define LP_UP1_ADV_12P5GB (1 << 6) 1006 #define LP_UP1_ADV_13GB (1 << 7) 1007 #define LP_UP1_ADV_15GB (1 << 8) 1008 #define LP_UP1_ADV_16GB (1 << 9) 1009 1010 1011 /* 1012 * Useful constants for CL73 autonegotion in XGXS PHY chips 1013 */ 1014 1015 /****************/ 1016 /* CL73 UserB0 */ 1017 /****************/ 1018 /* CL73_UCtrl1 Register */ 1019 #define CL73_UCTRL1_FORCE_TX_OMUX_EN (1 << 0) 1020 #define CL73_UCTRL1_USTAT1_MUXSEL (1 << 1) 1021 #define CL73_UCTRL1_COUPLE_W_CL37_RESTART (1 << 2) 1022 #define CL73_UCTRL1_COUPLE_W_CL73_RESTART (1 << 3) 1023 #define CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL (1 << 4) 1024 #define CL73_UCTRL1_NONCE_MATCH_VAL (1 << 5) 1025 #define CL73_UCTRL1_NONCE_MATCH_OVER (1 << 6) 1026 #define CL73_UCTRL1_LINK_FAIL_TIMER_QUAL_EN (1 << 7) 1027 #define CL73_UCTRL1_LINK_FAIL_TIMER_DIS (1 << 8) 1028 #define CL73_UCTRL1_LONG_PAR_DET_TIMER_DIS (1 << 9) 1029 #define CL73_UCTRL1_ALLOW_CL37_AN (1 << 10) 1030 #define CL73_UCTRL1_PAR_DET_DIS (1 << 11) 1031 #define CL73_UCTRL1_LOSS_OF_SYNC_FAIL_EN (1 << 12) 1032 1033 /* CL73_UStat1 Register */ 1034 #define CL73_USTAT1_ARB_FSM (0x3ff << 0) 1035 1036 /* CL73_BAMCtrl1 Register */ 1037 #define CL73_BAMCTRL1_UD_CODE_41_32 (0x3ff << 0) 1038 #define CL73_BAMCTRL1_TEST_MP5_HALT_STEP (1 << 11) 1039 #define CL73_BAMCTRL1_TEST_MP5_HALT_EN (1 << 12) 1040 #define CL73_BAMCTRL1_BAMNP_AFTER_BP_EN (1 << 13) 1041 #define CL73_BAMCTRL1_STATION_MNGR_EN (1 << 14) 1042 #define CL73_BAMCTRL1_BAMEN (1 << 15) 1043 1044 /* CL73_BAMCtrl2 Register */ 1045 #define CL73_BAMCTRL2_UD_CODE_31_16 (0xffff) 1046 1047 /* CL73_BAMCtrl3 Register */ 1048 #define CL73_BAMCTRL3_USE_CL73_HCD_MR (1 << 0) 1049 #define CL73_BAMCTRL3_UD_CODE_15_1 (0x7fff << 1) 1050 1051 /* CL73_BAMStat1 Register */ 1052 #define CL73_BAMSTAT1_LP_UD_CODE_41_32 (0x3ff << 0) 1053 1054 /* CL73_BAMStat2 Register */ 1055 #define CL73_BAMSTAT2_LP_UD_CODE_31_16 (0xffff) 1056 1057 /* CL73_BAMStat3 Register */ 1058 #define CL73_BAMSTAT3_USE_CL73_HCD_LP (1 << 0) 1059 #define CL73_BAMSTAT3_LP_UD_CODE_15_1 (0x7fff << 1) 1060 1061 /*********************/ 1062 /* CL73_IEEEB0 Block */ 1063 /*********************/ 1064 /* CL73 AN Control Register */ 1065 #define CL73_AN_CTRL_RES_NEGOTIATION (1 << 9) 1066 #define CL73_AN_CTRL_AUTONEG_EN (1 << 12) 1067 #define CL73_AN_CTRL_MAIN_RESET (1 << 15) 1068 1069 /* CL73 AN Status Register */ 1070 #define CL73_AN_STAT_LP_AN_ABLE (1 << 0) 1071 #define CL73_AN_STAT_LINK_STAT (1 << 2) 1072 #define CL73_AN_STAT_AN_ABILITY (1 << 3) 1073 #define CL73_AN_STAT_RF (1 << 4) 1074 #define CL73_AN_STAT_AN_DONE (1 << 5) 1075 #define CL73_AN_STAT_PAGE_RECEIVED (1 << 6) 1076 #define CL73_AN_STAT_EXT_NP_STAT (1 << 7) 1077 #define CL73_AN_STAT_PARALLEL_DETECT_FAULT (1 << 9) 1078 1079 /* CL73 PHY ID MSB */ 1080 /* CL73 PHY ID LSB */ 1081 /* IEEE Dev In Pkg 1 */ 1082 /* IEEE Dev In Pkg 2 */ 1083 1084 /*********************/ 1085 /* CL73_IEEEB1 Block */ 1086 /*********************/ 1087 /* AN_adv1 Register */ 1088 #define CL73_AN_ADV1_LD_SELECTOR (0x1f << 0) 1089 #define CL73_AN_ADV1_LD_ECHOED_NONCE (0x1f << 5) 1090 #define CL73_AN_ADV1_LD_PAUSE (7 << 10) 1091 #define CL73_AN_ADV1_LD_RF (1 << 13) 1092 #define CL73_AN_ADV1_LD_ACK (1 << 14) 1093 #define CL73_AN_ADV1_LD_NP (1 << 15) 1094 1095 /* AN_adv2 Register */ 1096 #define CL73_AN_ADV2_LD_TX_NONCE (0x1f << 0) 1097 #define CL73_AN_ADV2_LD_TECH_ABILITY_10_0 (0x7ff << 5) 1098 1099 /* AN_adv3 Register */ 1100 #define CL73_AN_ADV2_LD_TECH_ABILITY_26_11 (0xffff) 1101 1102 /* AN_lp_adv1 Register */ 1103 #define CL73_AN_ADV1_LP_SELECTOR (0x1f << 0) 1104 #define CL73_AN_ADV1_LP_ECHOED_NONCE (0x1f << 5) 1105 #define CL73_AN_ADV1_LP_PAUSE (1 << 10) 1106 #define CL73_AN_ADV1_LP_ASYM_PAUSE (1 << 11) 1107 #define CL73_AN_ADV1_LP_RF (1 << 13) 1108 #define CL73_AN_ADV1_LP_ACK (1 << 14) 1109 #define CL73_AN_ADV1_LP_NP (1 << 15) 1110 1111 /* AN_lp_adv2 Register */ 1112 #define CL73_AN_ADV2_LP_TX_NONCE (0x1f << 0) 1113 #define CL73_AN_ADV2_LP_TECH_ABILITY_10_0 (0x7ff << 5) 1114 #define CL73_AN_ADV2_LP_TECH_1G_KX (1 << 5) 1115 #define CL73_AN_ADV2_LP_TECH_10G_KX4 (1 << 6) 1116 #define CL73_AN_ADV2_LP_TECH_10G_KR (1 << 7) 1117 1118 /* AN_lp_adv3 Register */ 1119 #define CL73_AN_ADV2_LP_TECH_ABILITY_26_11 (0xffff) 1120 1121 /* AN_np1 Register */ 1122 /* AN_np2 Register */ 1123 /* AN_np3 Register */ 1124 /* AN_lp_np1 Register */ 1125 /* AN_lp_np2 Register */ 1126 /* AN_lp_np3 Register */ 1127 1128 /*********************/ 1129 /* CL73_IEEEB2 Block */ 1130 /*********************/ 1131 1132 1133 #endif /* _SERDES_COMBO65_H_ */